Lcd companion boards support (VKLCD50RTA & VKLCD70RT)

What is this ?

This is a demo program using Renesas RGA library & USB Camera to demonstrate VK-RZ/A1H's companion boards workability.


Supported companion Boards:

VKLCD50RTA

/media/uploads/tvendov/front_view_hmi_50.png /media/uploads/tvendov/side_view_hmi_50.png

VKLCD70RT

/media/uploads/tvendov/front_view_hmi_70.png/media/uploads/tvendov/side_view_hmi_70.png /media/uploads/tvendov/front_view_lvds.png/media/uploads/tvendov/back_view_lvds.png


How to Configure ?

You can choose which display is installed by altering the lcd_panel.h file

Leave the active one & comment out the others:

#define     LCD_VDC5_CH0_PANEL                  LCD_CH0_PANEL_VKLCD50RTA
//#define     LCD_VDC5_CH0_PANEL                  LCD_CH0_PANEL_VKLCD70RT

You can alter the whole demo with your pictures if you like:


How to compile ?

  • The Demo can be compiled in 3 modes:
    • I. Execution from the internal 10-MB on-chip SRAM.
      • After import in the online compiler just leave only the VKRZA1H_RAM.sct & delete all others linker files in the TOOLCHAIN_ARM_STD folder.
      • Save the result binary in the SD Card (<SD>:\vkrza1\lcd_sample ), altering vkrza1h.ini by this way
    • II. Execution from the on-board serial FALSH in dual (32-MB) mode.
      • After import in the online compiler just leave only the VKRZA1H_DOUBLE.sct & delete all others linker files in the TOOLCHAIN_ARM_STD folder.
      • Drag & drop the result binary in MBED disk, (previously inited in double flash mode)
    • III. Execution from the on-board serial FALSH in single (16-MB) mode.
      • After import in the online compiler just leave only the VKRZA1H_SINGLE.sct & delete all others linker files in the TOOLCHAIN_ARM_STD folder.
      • Drag & drop the result binary in MBED disk, (previously inited in single flash mode )

Quick presentation:


Other demos ?

More demos you can find on our FTP

Files at this revision

API Documentation at this revision

Comitter:
tvendov
Date:
Thu Feb 16 10:23:48 2017 +0000
Commit message:
Initial lcd support (VKLCD50RTA & VKLCD70RT companion boards)

Changed in this revision

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USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/ohci_wrapp_pipe.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/inc/usb0_host.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/inc/usb0_host_api.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/common/usb0_host_dataio.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/common/usb0_host_dma.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/common/usb0_host_intrn.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/common/usb0_host_lib.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/host/usb0_host_controlrw.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/host/usb0_host_drv_api.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/host/usb0_host_global.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/host/usb0_host_usbint.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/host/usb0_host_usbsig.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/inc/usb1_host.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/inc/usb1_host_api.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/common/usb1_host_dataio.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/common/usb1_host_dma.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/common/usb1_host_intrn.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/common/usb1_host_lib.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/host/usb1_host_controlrw.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/host/usb1_host_drv_api.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/host/usb1_host_global.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/host/usb1_host_usbint.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/host/usb1_host_usbsig.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb_host_setting.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/USBDeviceConnected.cpp Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/USBDeviceConnected.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/USBEndpoint.cpp Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/USBEndpoint.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/USBHALHost.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/USBHALHost_LPC17.cpp Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/USBHALHost_RZ_A1.cpp Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/USBHost.cpp Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/USBHost.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/USBHostConf.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/USBHostTypes.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHost/dbg.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHostCam/CamInfo.cpp Show annotated file Show diff for this revision Revisions of this file
USB/USBHostCam/USBHostCam.cpp Show annotated file Show diff for this revision Revisions of this file
USB/USBHostCam/USBHostCam.h Show annotated file Show diff for this revision Revisions of this file
USB/USBHostHub/USBHostHub.cpp Show annotated file Show diff for this revision Revisions of this file
USB/USBHostHub/USBHostHub.h Show annotated file Show diff for this revision Revisions of this file
USB/USBisochronous/USBIsochronous.cpp Show annotated file Show diff for this revision Revisions of this file
USB/USBisochronous/USBIsochronous.h Show annotated file Show diff for this revision Revisions of this file
USB/uvc/BaseUvc.cpp Show annotated file Show diff for this revision Revisions of this file
USB/uvc/BaseUvc.h Show annotated file Show diff for this revision Revisions of this file
USB/uvc/decodeMJPEG.cpp Show annotated file Show diff for this revision Revisions of this file
USB/uvc/decodeMJPEG.h Show annotated file Show diff for this revision Revisions of this file
USB/uvc/jconfig.h Show annotated file Show diff for this revision Revisions of this file
USB/uvc/jerror.h Show annotated file Show diff for this revision Revisions of this file
USB/uvc/jmorecfg.h Show annotated file Show diff for this revision Revisions of this file
USB/uvc/jpeglib.h Show annotated file Show diff for this revision Revisions of this file
USB/uvc/libjpeg.ar Show annotated file Show diff for this revision Revisions of this file
env/test_env.cpp Show annotated file Show diff for this revision Revisions of this file
env/test_env.h Show annotated file Show diff for this revision Revisions of this file
hal/api/AnalogIn.h Show annotated file Show diff for this revision Revisions of this file
hal/api/AnalogOut.h Show annotated file Show diff for this revision Revisions of this file
hal/api/BusIn.h Show annotated file Show diff for this revision Revisions of this file
hal/api/BusInOut.h Show annotated file Show diff for this revision Revisions of this file
hal/api/BusOut.h Show annotated file Show diff for this revision Revisions of this file
hal/api/CAN.h Show annotated file Show diff for this revision Revisions of this file
hal/api/CThunk.h Show annotated file Show diff for this revision Revisions of this file
hal/api/CallChain.h Show annotated file Show diff for this revision Revisions of this file
hal/api/Callback.h Show annotated file Show diff for this revision Revisions of this file
hal/api/CircularBuffer.h Show annotated file Show diff for this revision Revisions of this file
hal/api/DigitalIn.h Show annotated file Show diff for this revision Revisions of this file
hal/api/DigitalInOut.h Show annotated file Show diff for this revision Revisions of this file
hal/api/DigitalOut.h Show annotated file Show diff for this revision Revisions of this file
hal/api/DirHandle.h Show annotated file Show diff for this revision Revisions of this file
hal/api/Ethernet.h Show annotated file Show diff for this revision Revisions of this file
hal/api/FileBase.h Show annotated file Show diff for this revision Revisions of this file
hal/api/FileHandle.h Show annotated file Show diff for this revision Revisions of this file
hal/api/FileLike.h Show annotated file Show diff for this revision Revisions of this file
hal/api/FilePath.h Show annotated file Show diff for this revision Revisions of this file
hal/api/FileSystemLike.h Show annotated file Show diff for this revision Revisions of this file
hal/api/FunctionPointer.h Show annotated file Show diff for this revision Revisions of this file
hal/api/I2C.h Show annotated file Show diff for this revision Revisions of this file
hal/api/I2CSlave.h Show annotated file Show diff for this revision Revisions of this file
hal/api/InterruptIn.h Show annotated file Show diff for this revision Revisions of this file
hal/api/InterruptManager.h Show annotated file Show diff for this revision Revisions of this file
hal/api/LocalFileSystem.h Show annotated file Show diff for this revision Revisions of this file
hal/api/LowPowerTicker.h Show annotated file Show diff for this revision Revisions of this file
hal/api/LowPowerTimeout.h Show annotated file Show diff for this revision Revisions of this file
hal/api/LowPowerTimer.h Show annotated file Show diff for this revision Revisions of this file
hal/api/PlatformMutex.h Show annotated file Show diff for this revision Revisions of this file
hal/api/PortIn.h Show annotated file Show diff for this revision Revisions of this file
hal/api/PortInOut.h Show annotated file Show diff for this revision Revisions of this file
hal/api/PortOut.h Show annotated file Show diff for this revision Revisions of this file
hal/api/PwmOut.h Show annotated file Show diff for this revision Revisions of this file
hal/api/RawSerial.h Show annotated file Show diff for this revision Revisions of this file
hal/api/SPI.h Show annotated file Show diff for this revision Revisions of this file
hal/api/SPISlave.h Show annotated file Show diff for this revision Revisions of this file
hal/api/Serial.h Show annotated file Show diff for this revision Revisions of this file
hal/api/SerialBase.h Show annotated file Show diff for this revision Revisions of this file
hal/api/SingletonPtr.h Show annotated file Show diff for this revision Revisions of this file
hal/api/Stream.h Show annotated file Show diff for this revision Revisions of this file
hal/api/Ticker.h Show annotated file Show diff for this revision Revisions of this file
hal/api/Timeout.h Show annotated file Show diff for this revision Revisions of this file
hal/api/Timer.h Show annotated file Show diff for this revision Revisions of this file
hal/api/TimerEvent.h Show annotated file Show diff for this revision Revisions of this file
hal/api/Transaction.h Show annotated file Show diff for this revision Revisions of this file
hal/api/can_helper.h Show annotated file Show diff for this revision Revisions of this file
hal/api/critical.h Show annotated file Show diff for this revision Revisions of this file
hal/api/mbed.h Show annotated file Show diff for this revision Revisions of this file
hal/api/mbed_assert.h Show annotated file Show diff for this revision Revisions of this file
hal/api/mbed_debug.h Show annotated file Show diff for this revision Revisions of this file
hal/api/mbed_error.h Show annotated file Show diff for this revision Revisions of this file
hal/api/mbed_interface.h Show annotated file Show diff for this revision Revisions of this file
hal/api/mbed_mem_trace.h Show annotated file Show diff for this revision Revisions of this file
hal/api/mbed_stats.h Show annotated file Show diff for this revision Revisions of this file
hal/api/platform.h Show annotated file Show diff for this revision Revisions of this file
hal/api/rtc_time.h Show annotated file Show diff for this revision Revisions of this file
hal/api/semihost_api.h Show annotated file Show diff for this revision Revisions of this file
hal/api/toolchain.h Show annotated file Show diff for this revision Revisions of this file
hal/api/wait_api.h Show annotated file Show diff for this revision Revisions of this file
hal/common/AnalogIn.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/BusIn.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/BusInOut.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/BusOut.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/CAN.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/CallChain.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/Ethernet.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/FileBase.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/FileLike.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/FilePath.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/FileSystemLike.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/I2C.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/I2CSlave.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/InterruptIn.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/InterruptManager.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/LocalFileSystem.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/RawSerial.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/SPI.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/SPISlave.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/Serial.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/SerialBase.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/Stream.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/Ticker.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/Timeout.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/Timer.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/TimerEvent.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_alloc_wrappers.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_assert.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_board.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_critical.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_error.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_gpio.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_interface.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_lp_ticker_api.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_mem_trace.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_pinmap_common.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_rtc_time.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_semihost_api.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_ticker_api.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_us_ticker_api.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_wait_api_no_rtos.c Show annotated file Show diff for this revision Revisions of this file
hal/common/mbed_wait_api_rtos.cpp Show annotated file Show diff for this revision Revisions of this file
hal/common/retarget.cpp Show annotated file Show diff for this revision Revisions of this file
hal/hal/analogin_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/analogout_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/buffer.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/can_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/dma_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/ethernet_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/gpio_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/gpio_irq_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/i2c_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/lp_ticker_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/pinmap.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/port_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/pwmout_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/rtc_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/serial_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/sleep_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/spi_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/storage_abstraction/Driver_Common.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/storage_abstraction/Driver_Storage.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/ticker_api.h Show annotated file Show diff for this revision Revisions of this file
hal/hal/us_ticker_api.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/RZ_A1_Init.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/RZ_A1_Init.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/VKRZA1H_DOUBLE.sct Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/VKRZA1H_RAM.sct Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/VKRZA1H_SDRAM.sct Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/VKRZA1H_SINGLE.sct Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/VKRZA1H.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/cmsis.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/cmsis_nvic.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/cmsis_nvic.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/dev_drv.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/gic.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/gic.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/bsc_iobitmask.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/cpg_iobitmask.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/dmac_iobitmask.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/gpio_iobitmask.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/intc_iobitmask.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/mtu2_iobitmask.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/ostm_iobitmask.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/riic_iobitmask.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/rspi_iobitmask.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/scif_iobitmask.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/usb_iobitmask.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/adc_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/bsc_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ceu_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/cpg_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/disc_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/dmac_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/dvdec_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ether_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/flctl_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/gpio_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ieb_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/inb_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/intc_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/irda_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/jcu_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/l2c_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/lin_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/lvds_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/mlb_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/mmc_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/mtu2_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ostm_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/pfv_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/pwm_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/riic_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/romdec_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/rscan0_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/rspi_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/rtc_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/scif_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/scim_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/scux_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/sdg_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/spdif_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/spibsc_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ssif_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/usb20_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/vdc5_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/wdt_iodefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/reg32_t.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/rza_io_regrw.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/mmu_Renesas_RZ_A1.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/nvic_wrapper.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/nvic_wrapper.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/pl310.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/pl310.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/r_typedefs.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/rza_io_regrw.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/arm_common_tables.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/arm_const_structs.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/arm_math.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_ca9.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_caFunc.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_caInstr.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_ca_mmu.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_cm0.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_cm0plus.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_cm3.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_cm4.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_cm4_simd.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_cm7.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_cmFunc.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_cmInstr.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_cmSecureAccess.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_cmSimd.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_sc000.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/cmsis/core_sc300.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/PeripheralNames.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/PinNames.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/PortNames.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/analogin_api.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/device.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernet_api.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernetext_api.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_addrdefine.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_api.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_irq_api.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_object.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/i2c_api.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/objects.h Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/pinmap.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/port_api.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/pwmout_api.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/rtc_api.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/serial_api.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/spi_api.c Show annotated file Show diff for this revision Revisions of this file
hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/Mail.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/MemoryPool.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/Mutex.cpp Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/Mutex.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/Queue.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/RtosTimer.cpp Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/RtosTimer.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/Semaphore.cpp Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/Semaphore.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/Thread.cpp Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/Thread.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/rtos.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/rtos_idle.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtos/rtos_idle.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/HAL_CA.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/RTX_Config.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/HAL_CA9.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/SVC_Table.S Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/cmsis_os.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Event.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Event.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_HAL_CM.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_List.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_List.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_MemBox.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Memory.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Memory.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Mutex.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Mutex.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Robin.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Robin.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_System.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_System.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Task.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Task.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Time.c Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Time.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_Timer.h Show annotated file Show diff for this revision Revisions of this file
rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h Show annotated file Show diff for this revision Revisions of this file
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGA.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,79 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: RGA.h $
+* $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+* Description:
+******************************************************************************/
+
+
+/* This is MAIN header file */
+
+#ifndef  RGA_H
+#define  RGA_H
+
+#include  "Project_Config.h"
+
+
+#ifdef _MSC_VER
+	#include  "PC/RGA_Sub_PC.h"
+	#include  "sub/bitblt_alpha.h"
+	#include  "PC/RGA_PC.h"
+#endif
+#ifdef _SH
+	#include  "SH7269/RGA_Sub_SH7269.h"
+	#include  "sub/bitblt_alpha.h"
+	#include  "SH7269/RGA_SH.h"
+#endif
+#ifdef R_ARM
+	#include  "r_ospl.h"
+	#include  "r_typedefs.h"
+	#include  "RGA_Port.h"
+#endif
+
+#include  "RGA_API.h"
+#ifdef  __cplusplus
+	#include  "RGA_Cpp.h"
+#endif
+
+
+/* Sample window surfaces library */
+#ifdef _MSC_VER
+	#include  <PC/RGA_SampleLib_RZ_A1H.h>
+#endif
+#ifdef _SH
+	#include  <SH7269/RGA_SampleLib_RZ_A1H.h>
+#endif
+#ifdef R_ARM
+	#include  "RGA_raw_image.h"
+	#include  "window_surfaces.h"
+	#include  "RGA_Port.h"
+#endif
+
+
+#endif  /* RGA_H */
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/inc/ncg_debug.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,82 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG debug header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2012.08.21
+*          - Added debugging messase function.
+*          2012.08.22
+*          - Updated coding format.
+*          - Added debug macro.
+*            - NCG_DEBUG_MAKE_MSG
+*            - NCG_DEBUG_PRINT_MSG
+*          2013.01.08
+*            - Fixed release code.
+*
+*******************************************************************************/
+
+#ifndef NCG_DEBUG_H
+#define NCG_DEBUG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------------------------------*/
+#ifdef NCG_DEBUG
+/*-----------------------------------------------------------------------------------*/
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#define NCG_ASSERT(EXPR)                            if (!(EXPR)) { NCGSYS_Abort(__FILE__, __LINE__, #EXPR); }
+
+#define NCG_DEBUG_MAKE_MSG_START( buff, format )    sprintf( (buff), format
+#define NCG_DEBUG_MAKE_MSG_PARAMETER( param )           , (param)
+#define NCG_DEBUG_MAKE_MSG_END(  )                  )
+#define NCG_DEBUG_PRINT_MSG( msg )                  printf( msg )
+
+#ifdef NCG_DEBUG_API_LOG
+
+#define NCG_DEBUG_PRINT_STRING( msg )               printf( "%s%s", (msg), NCG_CRLF )
+
+#else /* #ifdef NCG_DEBUG_API_LOG */
+
+#define NCG_DEBUG_PRINT_STRING( msg )               /* No process */
+
+#endif /* #ifdef NCG_DEBUG_API_LOG */
+
+#define NCG_DEBUG_MSG_BUFFER_SIZE                   512
+
+#define NCG_CRLF                                    "\n"
+
+extern void NCGSYS_Abort(const NCGchar *filename, NCGint32 line, const NCGchar *condition);
+
+extern char NCG_G_MASSAGE_BUFF[NCG_DEBUG_MSG_BUFFER_SIZE];
+
+/*-----------------------------------------------------------------------------------*/
+#else   /* NCG_DEBUG */
+/*-----------------------------------------------------------------------------------*/
+
+#define NCG_ASSERT(EXPR)                                /* No process */
+#define NCG_DEBUG_MAKE_MSG_START( buff, format )        /* No process */
+#define NCG_DEBUG_MAKE_MSG_PARAMETER( param )           /* No process */
+#define NCG_DEBUG_MAKE_MSG_END(  )                      /* No process */
+#define NCG_DEBUG_PRINT_MSG( msg )                      /* No process */
+
+#define NCG_DEBUG_PRINT_STRING( msg )                   /* No process */
+
+/*-----------------------------------------------------------------------------------*/
+#endif  /* NCG_DEBUG */
+/*-----------------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_DEBUG_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/inc/ncg_defs.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,114 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG Type Definitions.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2011.03.04
+*          - Added the type of NCGfp.
+*          2012.08.22
+*          - Updated coding format.
+*          2012.11.14
+*          - Added the definition for Multi-Display.
+*             NCGDU_CH1
+*             NCGDU_CH2
+*          - Modified the type of NCGISRfp to NCGDUISRfp and NCGVGISRfp.
+*
+*******************************************************************************/
+
+#ifndef NCG_DEFS_H
+#define NCG_DEFS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+#define NCG_NULL    0
+#else
+#define NCG_NULL    ((void *)0)
+#endif
+
+#define NCG_FALSE   0
+#define NCG_TRUE    1
+
+#define NCG_UINT32_MAX (0xffffffffU)
+
+#define NCG_TIMEOUT_INFINITE NCG_UINT32_MAX
+#define NCG_INVALID_TLSINDEX NCG_UINT32_MAX
+
+/* Display chanel */
+#define NCGDU_CH1                   (0x00000001U)
+#define NCGDU_CH2                   (0x00000002U)
+
+
+#if !defined(NCG_UNREFERENCED_PARAMETER)
+#define NCG_UNREFERENCED_PARAMETER   R_UNREFERENCED_VARIABLE
+#endif
+
+/*
+ *  Error codes
+ */
+
+#define NCG_FIRST_ERROR (-255)
+enum
+{
+    NCG_no_err = 0,
+    NCG_err_unknown                 = NCG_FIRST_ERROR,
+    NCG_err_not_implemented         = NCG_FIRST_ERROR+ 1,
+    NCG_err_bad_parameter           = NCG_FIRST_ERROR+ 2,
+    NCG_err_no_host_mem             = NCG_FIRST_ERROR+ 3,
+    NCG_err_lost_host_mem           = NCG_FIRST_ERROR+ 4,
+    NCG_err_no_frame_mem            = NCG_FIRST_ERROR+ 5,
+    NCG_err_lost_frame_mem          = NCG_FIRST_ERROR+ 6,
+    NCG_err_already_created         = NCG_FIRST_ERROR+ 7,
+    NCG_err_isr_management_failed   = NCG_FIRST_ERROR+ 8,
+    NCG_err_wait_timeout            = NCG_FIRST_ERROR+ 9,
+    NCG_err_device_in_use           = NCG_FIRST_ERROR+10,
+    NCG_err_not_found               = NCG_FIRST_ERROR+11,
+    NCG_err_invalid_handle          = NCG_FIRST_ERROR+12,
+    NCG_err_resource_exceeded       = NCG_FIRST_ERROR+13,
+    NCG_last_err                    = NCG_FIRST_ERROR+14,
+};
+
+
+/*
+ *  NCG data type definitions
+ */
+
+typedef void                    NCGvoid;
+typedef unsigned int            NCGenum;
+typedef unsigned int            NCGboolean;
+typedef unsigned int            NCGbitfield;
+
+typedef char                    NCGchar;
+typedef signed char             NCGint8;
+typedef short                   NCGint16;
+typedef int                     NCGint32;
+typedef long long               NCGint64;
+typedef unsigned char           NCGuint8;
+typedef unsigned short          NCGuint16;
+typedef unsigned int            NCGuint32;
+typedef unsigned long long      NCGuint64;
+typedef float                   NCGfloat32;
+typedef double                  NCGfloat64;
+
+typedef int                     NCGsizei;
+typedef float                   NCGclampf;
+typedef long                    NCGfixed;
+
+typedef NCGuint32 (*NCGDUISRfp)(NCGbitfield uiDisplay);
+typedef NCGuint32 (*NCGVGISRfp)(void);
+typedef NCGvoid (*NCGfp)(NCGvoid *);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_DEFS_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/inc/ncg_memory.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,56 @@
+/******************************************************************************
+* Copyright(c) 2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : Sample code of NCG memory operation functions header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2013.06.25
+*          - Changed for RGAH
+*          2013.01.08
+*          - Created new code.
+*
+******************************************************************************/
+
+#ifndef NCG_MEMORY_H
+#define NCG_MEMORY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*=============================================================================
+ * Definitions
+ */
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ * Host memory management
+ */
+
+NCGvoid
+NCGSYS_PurgeCPUOperandCache (
+    void
+);
+
+NCGuint32
+NCGSYS_CPUVAddrToSysPAddr (
+    NCGuint32   ui32CPUAddr
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_MEMORY_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/inc/ncg_register.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,67 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG register read/write header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*
+*******************************************************************************/
+
+#ifndef NCG_REGISTER_H
+#define NCG_REGISTER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*=============================================================================
+ * Definitions
+ */
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ *  Register read/write
+ */
+NCGuint32
+NCGSYS_ReadReg (
+    NCGuint32   ui32RegBase,
+    NCGuint32   ui32Offset
+);
+
+NCGvoid
+NCGSYS_WriteReg (
+    NCGuint32   ui32RegBase,
+    NCGuint32   ui32Offset,
+    NCGuint32   ui32Value
+);
+
+NCGuint32
+NCGSYS_ModifyReg (
+    NCGuint32   ui32RegBase,
+    NCGuint32   ui32Offset,
+    NCGuint32   ui32Mask,
+    NCGuint32   ui32Value
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_REGISTER_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/inc/ncg_state.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,110 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG state variable control functions header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*
+*******************************************************************************/
+
+#ifndef NCG_STATE_H
+#define NCG_STATE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*=============================================================================
+ * Definitions
+ */
+
+/*
+ *  Mode Flags
+ */
+
+#define NCGSYS_STATE_CALL_MASK       (0x00000003U)
+#define NCGSYS_STATE_CALL_NORMAL     (0x00000000U)
+#define NCGSYS_STATE_CALL_INTERRUPT  (0x00000001U)
+#define NCGSYS_STATE_CALL_CALLBACK   (0x00000002U)
+
+#define NCGSYS_STATE_WAIT_MASK       (0x00000004U)
+#define NCGSYS_STATE_WAIT_OR         (0x00000004U)
+#define NCGSYS_STATE_WAIT_AND        (0x00000000U)
+
+#define NCGSYS_STATE_SET_MASK        (0x00000018U)
+#define NCGSYS_STATE_SET_AND         (0x00000000U)
+#define NCGSYS_STATE_SET_OR          (0x00000008U)
+#define NCGSYS_STATE_SET_SET         (0x00000010U)
+
+#define NCGSYS_STATE_OR             NCGSYS_STATE_SET_OR
+#define NCGSYS_STATE_SET            NCGSYS_STATE_SET_SET
+#define NCGSYS_STATE_CLEAR          NCGSYS_STATE_SET_AND
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ *  State control
+ */
+
+NCGint32
+NCGSYS_CreateState (
+    NCGvoid     **ppObj,
+    NCGuint32   ui32StateID
+);
+
+NCGint32
+NCGSYS_DestroyState (
+    NCGvoid     *pObj
+);
+
+NCGint32
+NCGSYS_SetState (
+    NCGvoid     *pObj,
+    NCGuint32   ui32State,
+    NCGuint32   ui32Flags
+);
+
+NCGuint32
+NCGSYS_GetState (
+    NCGvoid     *pObj,
+    NCGuint32   ui32Flags
+);
+
+NCGint32
+NCGSYS_WaitState (
+    NCGvoid     *pObj,
+    NCGuint32   ui32State,
+    NCGuint32   ui32Flags,
+    NCGuint32   ui32Timeout
+);
+
+NCGvoid
+NCGSYS_SetStateEventValue (
+    NCGvoid    *pObj,
+    NCGuint32   ui32EventValue
+);
+
+NCGvoid *
+NCGSYS_GetLastCreatedState(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_STATE_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/inc/ncg_time.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,65 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG time and delay control functions header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*
+*******************************************************************************/
+
+#ifndef NCG_TIME_H
+#define NCG_TIME_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*=============================================================================
+ * Definitions
+ */
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ *  Delay control
+ */
+NCGint32
+NCGSYS_Sleep (
+    NCGuint32   ui32MilliSeconds
+);
+
+/*
+ *  Time acquisition
+ */
+
+NCGint32
+NCGSYS_StartTickCount (
+    void
+);
+
+NCGuint32
+NCGSYS_GetTickCount (
+    void
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NCG_TIME_H__ */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/inc/ncg_vg.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,73 @@
+/******************************************************************************
+* Copyright(c) 2010-2013 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : R-GPVG Functions header
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2011.01.12
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*          2013.05.13
+*          - Added function of initialization.
+*          - Added function of finalization.
+*
+*******************************************************************************/
+
+#ifndef NCG_VG_H
+#define NCG_VG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ncg_defs.h"
+/*=============================================================================
+ * Definitions
+ */
+
+/* VGINFO */
+typedef struct VGINFO_TAG {
+    NCGuint32   ui32Flags;
+} NCGVGINFO, * PNCGVGINFO;
+
+/* RGPINFO */
+typedef struct RGPINFO_TAG {
+    NCGuint32   ui32WorkBufferStride;       /* Work Buffer Stride */
+    NCGuint32   ui32WorkBufferHeight;       /* Work Buffer Height */
+    NCGuint32   ui32StreamBuffer0Size;      /* Stream Buffer 0 Size */
+    NCGuint32   ui32StreamBuffer1Size;      /* Stream Buffer 1 Size */
+    NCGuint32   ui32DisplayListBufferSize;  /* Display List Buffer Size */
+} NCGRGPINFO, * PNCGRGPINFO;
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ *  VG initialization / finalization
+ */
+NCGvoid
+NCGVG_Init (
+    PNCGVGINFO      pVGInfo
+);
+
+NCGvoid
+NCGVG_DeInit (
+    PNCGVGINFO      pVGInfo
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_VG_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/inc/ncg_vg_isr.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,69 @@
+/******************************************************************************
+* Copyright(c) 2010-2013 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG R-GPVG interrupt handling functions header.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*          2013.01.08
+*          - Applied to R-GPVG2 for Aragon.
+*          2013.02.21
+*          - Modified the value of NCGVG_INT_LEVEL.
+*
+*******************************************************************************/
+
+#ifndef NCG_VG_ISR_H
+#define NCG_VG_ISR_H
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*=============================================================================
+ * Definitions
+ */
+
+#define NCGVG_INT0_VECT     (130)
+#define NCGVG_INT1_VECT     (131)
+#define NCGVG_INT2_VECT     (132)
+#define NCGVG_INT3_VECT     (133)
+
+#define NCGVG_INT_LEVEL     (5)               /* interrupt level */
+
+
+/*=============================================================================
+ *  Structures
+ */
+
+
+/*=============================================================================
+ *  Function prototyping
+ */
+
+/*
+ * VG interrupt handling
+ */
+
+NCGint32
+NCGVG_Attach_ISR (
+    NCGVGISRfp pfnInterrupt
+);
+
+NCGint32
+NCGVG_Detach_ISR (
+    NCGVGISRfp pfnInterrupt
+);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NCG_VG_ISR_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/src/ncg_memory.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,54 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG memory operation functions.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2013.06.25
+*          - Changed for RGAH
+*          2010.10.08
+*          - Created the initial code.
+*          2012.08.23
+*          - Created the initial code.
+*          2014.12.22
+*          - Applied to OSPL and RGA.
+*
+*******************************************************************************/
+
+/*=============================================================================
+ * Includes
+ */
+
+#include "Project_Config.h"
+#include "ncg_defs.h"
+#include "ncg_memory.h"
+
+#ifdef  RGAH_VERSION
+
+/*=============================================================================
+ * Internal definitions
+ */
+
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_CPUVAddrToSysPAddr
+ FUNCTION   : Get the system physical address of the given host memory block.
+ PARAMETERS : ui32CPUAddr  : [IN ] The address of the host memory area.
+ RETURN     : Phy.
+------------------------------------------------------------------------------*/
+NCGuint32
+NCGSYS_CPUVAddrToSysPAddr (
+    NCGuint32   ui32CPUAddr )
+{
+    NCGuint32   ui32Ret_addr;
+
+    ui32Ret_addr = ui32CPUAddr;
+
+    return ui32Ret_addr;
+}
+
+
+#endif
+/* -- end of file -- */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/src/ncg_register.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,86 @@
+/******************************************************************************
+* Copyright (c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG register read/write Functions
+*
+* author : Renesas Electronics Corporation.
+*
+* history: 2013.06.25
+*          - Changed for RGAH
+*          2010.10.08
+*          - Created the initial code.
+*          2012.08.22
+*          - Updated coding format.
+*          2014.12.22
+*          - Applied to OSPL and RGA.
+*
+*******************************************************************************/
+
+/*=============================================================================
+ * Includes
+ */
+
+#include "Project_Config.h"
+#include "ncg_defs.h"
+#include "ncg_register.h"
+
+#ifdef  RGAH_VERSION
+
+/*=============================================================================
+ * Internal definitions
+ */
+
+
+/*=============================================================================
+ *  Prototyping of internal functions
+ */
+
+
+/*=============================================================================
+ *  Private global variables and functions
+ */
+
+
+/*=============================================================================
+ *  Global Function
+ */
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_ReadReg
+ FUNCTION   : Read a hardware register.
+ PARAMETERS : ui32RegBase : [IN ] Base address.
+              ui32Offset  : [IN ] Address offset.
+ RETURN     : Register value.
+------------------------------------------------------------------------------*/
+NCGuint32
+NCGSYS_ReadReg (
+    NCGuint32       ui32RegBase,
+    NCGuint32       ui32Offset )
+{
+    NCGuint32 ui32RegVal;
+
+    ui32RegVal = *(((volatile NCGuint32 *)ui32RegBase) + (ui32Offset>>2));
+
+    return ui32RegVal;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_WriteReg
+ FUNCTION   : Write a hardware register.
+ PARAMETERS : ui32RegBase : [IN ] Base address.
+              ui32Offset  : [IN ] Address offset.
+              ui32Value   : [IN ] Register value.
+ RETURN     : None.
+------------------------------------------------------------------------------*/
+NCGvoid
+NCGSYS_WriteReg (
+    NCGuint32       ui32RegBase,
+    NCGuint32       ui32Offset,
+    NCGuint32       ui32Value )
+{
+    *(((volatile NCGuint32 *)ui32RegBase) + (ui32Offset>>2)) = ui32Value;
+}
+
+#endif
+/* -- end of file -- */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/src/ncg_state.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,500 @@
+/******************************************************************************
+* Copyright(c) 2010-2012 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : NCG State variable control functions.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2013.05.20
+*          - Applied to CMSIS-RTOS RTX.
+*          2014.12.10
+*          - Applied to OSPL and RGA.
+*
+*******************************************************************************/
+
+/*=============================================================================
+ * Includes
+ */
+#include "Project_Config.h"
+#include "r_ospl.h"
+
+#include    "ncg_defs.h"
+#include    "ncg_debug.h"
+#include    "ncg_state.h"
+
+#ifdef  RGAH_VERSION
+
+/*=============================================================================
+ * Internal definitions
+ */
+
+#define     NCG_MAX_STATE_OBJECTS   (1U)
+#define     NCG_MAX_THREAD_ID       (1U)
+
+struct NCG_STATE_T {
+    r_ospl_thread_id_t  id[NCG_MAX_THREAD_ID];
+    NCGboolean      bInUse;
+    int32_t         flgbit;
+    NCGuint32       ui32State;
+} ;
+
+
+/*=============================================================================
+ *  Prototyping of internal functions
+ */
+
+static NCGint32 ncg_init_states( void ) ;
+static NCGuint32 ncg_state_search( NCGvoid *pObj );
+
+
+/*=============================================================================
+ *  Private global variables and functions
+ */
+
+volatile static struct NCG_STATE_T tStates[NCG_MAX_STATE_OBJECTS];
+
+static NCGboolean ncg_state_initialized = NCG_FALSE ;
+static struct NCG_STATE_T *ncg_last_created_state;
+
+
+/*=============================================================================
+ *  Global Function
+ */
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_CreateState
+ FUNCTION   : Create a state control object.
+ PARAMETERS : ppObj       : [OUT] The pointer to the created state control object.
+              ui32StateID : [IN ] The identifier of the state variable.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGSYS_CreateState(
+    NCGvoid         **ppObj,
+    NCGuint32       ui32StateID )
+{
+    struct NCG_STATE_T  *p_state;
+    NCGuint32           state_idx;
+    NCGuint32           thread_idx;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGSYS_CreateState" );
+
+    NCG_UNREFERENCED_PARAMETER(ui32StateID);
+
+    if( ppObj == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_CreateState(1) invalid ppObj.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_invalid_handle ;
+    }
+
+    if( ncg_state_initialized == NCG_FALSE ) {
+        ncg_init_states();
+    }
+
+    p_state = NULL;
+    for ( state_idx = 0 ; state_idx < NCG_MAX_STATE_OBJECTS ; state_idx++ ) {
+        if ( tStates[state_idx].bInUse == NCG_FALSE ) {
+            p_state = (struct NCG_STATE_T *)&tStates[state_idx];
+            break ;
+        }
+    }
+    if ( p_state == NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_CreateState(2) Object over flow.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_resource_exceeded ;
+    }
+
+    /* set initial value */
+    for ( thread_idx = 1U ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+        p_state->id[thread_idx] = NULL;
+    }
+    p_state->id[0]     = R_OSPL_THREAD_GetCurrentId();    /* [0] is current thread id */
+    p_state->bInUse    = NCG_TRUE ;
+    p_state->ui32State = 0U ;
+
+    *ppObj = ( NCGvoid *)p_state ;
+    ncg_last_created_state = p_state;
+
+    return NCG_no_err ;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_DestroyState
+ FUNCTION   : Destroy the given state control object.
+ PARAMETERS : pObj : [IN ] The pointer to the state control object.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGSYS_DestroyState(
+    NCGvoid *pObj )
+{
+    volatile struct NCG_STATE_T *p_state;
+    NCGuint32                   state_idx;
+    NCGuint32                   thread_idx;
+    NCGboolean bDestroyFlg ;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGSYS_DestroyState" );
+
+    p_state = (struct NCG_STATE_T *)pObj;
+    if( p_state == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_DestroyState(1) Failed: pObj is NULL.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_invalid_handle ;
+    }
+
+    state_idx = ncg_state_search( pObj );
+    if ( state_idx >= NCG_MAX_STATE_OBJECTS ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_DestroyState(2) Failed: pObj is not found.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_not_found ;
+    }
+
+    if( p_state->bInUse == NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_DestroyState(3) Failed: pObj is not used.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_bad_parameter ;
+    }
+
+    /* clear status parameters */
+    for ( thread_idx = 0 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+        p_state->id[thread_idx] = NULL;
+    }
+    p_state->bInUse    = NCG_FALSE;
+    p_state->ui32State = 0U;
+
+    bDestroyFlg = NCG_TRUE ;
+    for ( state_idx = 0 ; state_idx < NCG_MAX_STATE_OBJECTS ; state_idx++ ) {
+        if ( tStates[state_idx].bInUse != NCG_FALSE ) {
+            bDestroyFlg = NCG_FALSE ;
+            break ;
+        }
+    }
+    if ( bDestroyFlg != NCG_FALSE ) {
+        ncg_state_initialized = NCG_FALSE ;
+    }
+    return NCG_no_err ;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_SetState
+ FUNCTION   : Set the state control object into the given state.
+ PARAMETERS : pObj      : [IN ] The pointer to the state control object.
+              ui32State : [IN ] The state value to set.
+              ui32Flags : [IN ] Flags.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGSYS_SetState(
+    NCGvoid         *pObj,
+    NCGuint32       ui32State,
+    NCGuint32       ui32Flags )
+{
+    volatile struct NCG_STATE_T *p_state = (volatile struct NCG_STATE_T *)pObj ;
+
+    NCGuint32                   uiSetMask;
+    NCGuint32                   thread_idx;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGSYS_SetState" );
+
+    if( pObj == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_SetState(1) Failed:pObj is NULL.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_unknown ;
+    }
+
+    if ( ncg_state_search( pObj ) >= NCG_MAX_STATE_OBJECTS ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_SetState(2) Failed: pObj is not found.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_not_found ;
+    }
+
+    p_state = (volatile struct NCG_STATE_T *)pObj;
+    if ( p_state->bInUse == NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_SetState(3) Failed: pObj is not used.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_bad_parameter ;
+    }
+
+    uiSetMask = ui32Flags & NCGSYS_STATE_SET_MASK;
+    switch( uiSetMask ) {
+        case NCGSYS_STATE_SET_AND :
+            p_state->ui32State &= ui32State ;
+            break ;
+
+        case NCGSYS_STATE_SET_OR :
+            p_state->ui32State |= ui32State ;
+            break ;
+
+        case NCGSYS_STATE_SET_SET :
+            p_state->ui32State = ui32State ;
+            break ;
+
+        default :
+            NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_SetState(5) Failed:ui32Flags (0x%08x).%s" )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( ui32Flags )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+            NCG_DEBUG_MAKE_MSG_END();
+            NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+            return NCG_err_bad_parameter ;
+    }
+
+    if ( uiSetMask == NCGSYS_STATE_SET_AND ) {
+        for ( thread_idx = 0 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+            if ( p_state->id[thread_idx] != NULL ) {
+                r_ospl_thread_id_t  thread = p_state->id[thread_idx];  /* ICCARM Pa082 : volatile's order */
+                R_OSPL_EVENT_Clear( thread, p_state->flgbit );
+            }
+        }
+    } else {
+        for ( thread_idx = 0 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+            if ( p_state->id[thread_idx] != NULL ) {
+                r_ospl_thread_id_t  thread = p_state->id[thread_idx];  /* ICCARM Pa082 : volatile's order */
+                R_OSPL_EVENT_Set( thread, p_state->flgbit );
+            }
+        }
+    }
+
+    return NCG_no_err ;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_GetState
+ FUNCTION   : Get the current state value from the state control object.
+ PARAMETERS : pObj       : [IN ] The pointer to the state control object.
+              ui32Flags  : [IN ] Flags.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGuint32
+NCGSYS_GetState(
+    NCGvoid         *pObj,
+    NCGuint32       ui32Flags )
+{
+    volatile struct NCG_STATE_T *p_state;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGSYS_GetState" );
+
+    NCG_UNREFERENCED_PARAMETER(ui32Flags);
+
+    if ( pObj == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_GetState(1) Failed: pObj.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return (NCGuint32)NCG_err_unknown ;
+    }
+
+    if ( ncg_state_search( pObj ) >= NCG_MAX_STATE_OBJECTS ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_GetState(2) Failed: pObj is not found.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return (NCGuint32)NCG_err_not_found ;
+    }
+
+    p_state = (volatile struct NCG_STATE_T *)pObj;
+    if( p_state->bInUse == NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_GetState(3) Failed: pObj is not used.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return (NCGuint32)NCG_err_bad_parameter ;
+    }
+    return ( NCGuint32 )p_state->ui32State ;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_WaitState
+ FUNCTION   : Wait for the state control object to be in the given state.
+ PARAMETERS : pObj        : [IN ] The pointer to the state control object.
+              ui32State   : [IN ] The state value to wait for.
+              ui32Flags   : [IN ] Flags.
+              ui32Timeout : [IN ] Timeout value in milli seconds.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGSYS_WaitState(
+    NCGvoid         *pObj,
+    NCGuint32       ui32State,
+    NCGuint32       ui32Flags,
+    NCGuint32       ui32Timeout )
+{
+    volatile struct NCG_STATE_T     *p_state;
+    NCGuint32                       wait_mode;
+    NCGuint32                       thread_idx;
+    NCGint32                        func_ret;
+    uint32_t                        time_out;
+    errnum_t                        e;
+
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGSYS_WaitState" );
+
+    p_state    = (volatile struct NCG_STATE_T *)pObj;
+    wait_mode = (ui32Flags & NCGSYS_STATE_WAIT_MASK);
+
+    if ( p_state == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_WaitState(1) Failed: pObj is NULL.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_unknown ;
+    }
+    if ( p_state->bInUse == NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_WaitState(2) Failed: pObj.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_unknown ;
+    }
+    if (( ui32Timeout != NCG_TIMEOUT_INFINITE ) && ( ui32Timeout > 0x7fffffffU )) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGSYS_WaitState(3) Failed: ui32Timeout.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        return NCG_err_unknown ;
+    }
+
+    if ( ui32Timeout == NCG_TIMEOUT_INFINITE ) {
+        time_out = R_OSPL_INFINITE;
+    } else {
+        time_out = ui32Timeout;
+    }
+
+    for ( thread_idx = 0 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+        if ( p_state->id[thread_idx] == R_OSPL_THREAD_GetCurrentId() ) {
+            break;
+        }
+        if ( p_state->id[thread_idx] == NULL ) {
+            /* add thread ID */
+            p_state->id[thread_idx] = R_OSPL_THREAD_GetCurrentId();
+            break;
+        }
+    }
+
+    while (1) {
+        if ( wait_mode == NCGSYS_STATE_WAIT_OR ) {
+            if ( (p_state->ui32State & ui32State) != 0 ) {
+                func_ret = NCG_no_err;
+                break;
+            }
+        } else {
+            /* wait_mode == NCGSYS_STATE_WAIT_AND */
+            if ( (p_state->ui32State & ui32State) == ui32State ) {
+                func_ret = NCG_no_err;
+                break;
+            }
+        }
+        e = R_OSPL_EVENT_Wait( p_state->flgbit, NULL, time_out );
+        IF ( e != 0 ) {
+            func_ret = NCG_err_unknown;
+            break;
+        }
+    }
+
+    for ( thread_idx = 1 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+        p_state->id[thread_idx] = NULL;
+    }
+
+    return func_ret;
+}
+
+
+/*=============================================================================
+ *  Internal functions
+ */
+
+/*----------------------------------------------------------------------------
+ NAME       : ncg_init_states
+ FUNCTION   : Initialize global variable in NCG state.
+ PARAMETERS : None.
+ RETURN     : None.
+------------------------------------------------------------------------------*/
+static NCGint32
+ncg_init_states( void )
+{
+    NCGuint32   i ;
+    NCGuint32   thread_idx;
+
+    for( i = 0 ; i < NCG_MAX_STATE_OBJECTS ; i++ ) {
+        for ( thread_idx = 0 ; thread_idx < NCG_MAX_THREAD_ID ; thread_idx++ ) {
+            tStates[i].id[thread_idx] = NULL;
+        }
+        tStates[i].bInUse    = NCG_FALSE ;
+        tStates[i].flgbit    = (int32_t)(1 << i) ;
+        tStates[ i ].ui32State = 0U ;
+    }
+    ncg_state_initialized = NCG_TRUE ;
+
+    return NCG_no_err;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : ncg_state_search
+ FUNCTION   : Search status object.
+ PARAMETERS : pObj :[IN ] Handle to the status object.
+ RETURN     : Index of the status object.
+------------------------------------------------------------------------------*/
+static NCGuint32 ncg_state_search(
+    NCGvoid     *pObj
+)
+{
+    NCGuint32               state_idx;
+
+    for ( state_idx = 0U ; state_idx < NCG_MAX_STATE_OBJECTS ; state_idx++ ) {
+        if ( pObj == &tStates[state_idx] ) {
+            break;
+        }
+    }
+
+    return state_idx;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_SetStateEventValue
+ FUNCTION   : Set the value of thread attached event.
+ PARAMETERS : pObj           : [IN ] The pointer to the state control object.
+              ui32EventValue : [IN ] The value of thread attached event.
+ RETURN     : None.
+------------------------------------------------------------------------------*/
+NCGvoid
+NCGSYS_SetStateEventValue(
+    NCGvoid         *pObj,
+    NCGuint32       ui32EventValue )
+{
+    volatile struct NCG_STATE_T *p_state = (volatile struct NCG_STATE_T *)pObj ;
+
+    p_state->flgbit = ui32EventValue;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGSYS_GetLastCreatedState
+ FUNCTION   : GetLastCreatedState.
+ PARAMETERS : None.
+ RETURN     : LastCreatedState.
+------------------------------------------------------------------------------*/
+NCGvoid *
+NCGSYS_GetLastCreatedState(void)
+{
+    return  (NCGvoid *) ncg_last_created_state;
+}
+
+#endif
+/* -- end of file -- */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/src/ncg_vg.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,162 @@
+/******************************************************************************
+* Copyright(c) 2010-2014 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : R-GPVG control functions.
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2011.01.20
+*          - Created the initial code.
+*          2012.08.22
+*          - Added return value to "NCGVG_InitResourceSize"
+*          2013.05.13
+*          - Added function of initialization.
+*          - Added function of finalization.
+*          2013.06.10
+*          - Applied to new VDC5 driver (Version 0.03.0046).
+*          2013.11.07
+*          - Modified value of NCG_VG_SBO1_SIZE to (4U) from (0U).
+*          2014.02.13
+*          - Modified the value of definitions.
+*              NCG_VG_WB_STRIDE
+*              NCG_VG_WB_HEIGHT
+*              NCG_VG_SBO0_SIZE
+*              NCG_VG_DLB_SIZE
+*          2014.03.25
+*          - Modified NCGVG_Init() and NCGVG_DeInit().
+*          2014.05.16
+*          - Modified NCGVG_Init() and NCGVG_DeInit().
+*          2014.12.22
+*          - Applied to OSPL and RGA.
+*
+*******************************************************************************/
+
+/*=============================================================================
+ * Includes
+ */
+
+#include "Project_Config.h"
+#include "ncg_defs.h"
+#include "ncg_debug.h"
+#include "r_ospl.h"
+
+#include "ncg_vg.h"
+
+/* Depending on the build environment */
+#include "r_typedefs.h"
+
+#include "iodefine.h"
+#include "iobitmasks/cpg_iobitmask.h"
+
+#ifdef  RGAH_VERSION
+
+/*=============================================================================
+ * Internal definitions
+ */
+
+/* TODO:
+    Please change these parameters in accordance with your system.
+ */
+#define NCG_VG_WB_STRIDE    (256U)
+#define NCG_VG_WB_HEIGHT    (480U)
+
+#define NCG_VG_SBO0_SIZE    (16384U)
+#define NCG_VG_SBO1_SIZE    (4U)
+#define NCG_VG_DLB_SIZE     (5120U)
+
+/*=============================================================================
+ *  Prototyping of internal functions
+ */
+
+
+/*=============================================================================
+ *  Private global variables and functions
+ */
+
+
+/*=============================================================================
+ *  Global Function
+ */
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGVG_Init
+ FUNCTION   : Initialize R-GPVG.
+ PARAMETERS : pVGInfo : [IN ] The pointer to the initialization information struct.
+ RETURN     : None.
+------------------------------------------------------------------------------*/
+NCGvoid
+NCGVG_Init (
+    PNCGVGINFO pVGInfo)
+{
+    /* Depending on the build environment */
+    volatile uint8_t    reg_value;
+
+    NCG_UNREFERENCED_PARAMETER( pVGInfo );
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGVG_Init" );
+
+    reg_value = CPG.STBCR10;
+    if ( CPG.STBCR10 & CPG_STBCR10_MSTP100 ) {
+        /* Standby control register 10 (STBCR10) : 0 : R-GPVG enable */
+        CPG.STBCR10 &= ~CPG_STBCR10_MSTP100;
+        /* dummy read */
+        reg_value = CPG.STBCR10;
+
+        if ( CPG.STBREQ2 & CPG_STBREQ2_STBRQ20 ) {
+            CPG.SWRSTCR3 |=  CPG_SWRSTCR3_SRST32;
+            /* dummy read */
+            reg_value = CPG.SWRSTCR3;
+
+            CPG.SWRSTCR3 &= ~CPG_SWRSTCR3_SRST32;
+            /* dummy read */
+            reg_value = CPG.SWRSTCR3;
+
+            CPG.STBREQ2 &= ~CPG_STBREQ2_STBRQ20;
+            /* dummy read */
+            reg_value = CPG.STBREQ2;
+            while ( (CPG.STBACK2 & CPG_STBACK2_STBAK20) != 0  ) ;
+        }
+    }
+
+    NCG_UNREFERENCED_PARAMETER( reg_value );  /* Avoid warning of "unused-but-set-variable" of GCC_ARM */
+
+    return ;
+}
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGVG_DeInit
+ FUNCTION   : Finalize R-GPVG.
+ PARAMETERS : pVGInfo : [IN ] The pointer to the finalization information struct.
+ RETURN     : None.
+------------------------------------------------------------------------------*/
+NCGvoid
+NCGVG_DeInit (
+    PNCGVGINFO      pVGInfo )
+{
+    /* Depending on the build environment */
+    volatile uint8_t    reg_value;
+
+    NCG_UNREFERENCED_PARAMETER(pVGInfo);
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGVG_DeInit" );
+
+    if ( (CPG.STBCR10 & CPG_STBCR10_MSTP100) != CPG_STBCR10_MSTP100 ) {
+        CPG.STBREQ2 |= CPG_STBREQ2_STBRQ20;
+        /* dummy read */
+        reg_value = CPG.STBREQ2;
+        while ( (CPG.STBACK2 & CPG_STBACK2_STBAK20) == 0  ) ;
+
+        /* Standby control register 10 (STBCR10) : 0 : R-GPVG disable */
+        CPG.STBCR10 |= CPG_STBCR10_MSTP100;
+        /* dummy read */
+        reg_value = CPG.STBCR10;
+    }
+
+    NCG_UNREFERENCED_PARAMETER( reg_value );  /* Avoid warning of "unused-but-set-variable" of GCC_ARM */
+
+    return ;
+}
+
+#endif
+/* -- end of file -- */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/RGPNCG/src/ncg_vg_isr.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,358 @@
+/******************************************************************************
+* Copyright(c) 2010-2015 Renesas Electronics Corporation. All rights reserved.
+*
+* brief  : R-GPVG control functions
+*
+* author : Renesas Electronics Corporation
+*
+* history: 2010.10.08
+*          - Created the initial code.
+*          2011.03.07
+*          - Fixed bug : NCGVG_Detach_ISR / [R-GPVG_common_P_033]
+*          2012.08.22
+*          - Moved definition to "ncg_vg_isr.h".
+*            - RGPVG_INT_LEVEL
+*          - Moved definition to "ncg_register.h".
+*            - RTIP_VG_BASE
+*            - VG_REG_VG_ISR
+*          2012.08.22
+*          - Added error message in the debug mode.
+*          - Update all comments
+*          2013.02.21
+*          - Modified the argument of the NCGVG_RGPVG_ISR.
+*          - Modified the call to R_INTC_RegistIntFunc function
+*            by NCGVG_Attach_ISR.
+*          2014.12.22
+*          - Applied to OSPL and RGA.
+*
+*******************************************************************************/
+
+
+/*=============================================================================
+ * Includes
+ */
+
+#include "Project_Config.h"
+#include    "ncg_defs.h"
+#include    "ncg_debug.h"
+#include    "ncg_vg_isr.h"
+#include    "RGA.h"
+
+/* Depending on the build environment */
+#include    "r_typedefs.h"
+#include    "r_ospl.h"
+
+#ifdef  RGAH_VERSION
+
+/*=============================================================================
+ * Internal definitions
+ */
+
+
+/*=============================================================================
+ *  Prototyping of internal functions
+ */
+static void NCGVG_RGPVG_ISR(void) ;
+static void NCGVG_RGPVG_ISR_0(void) ;
+static void NCGVG_RGPVG_ISR_1(void) ;
+static void NCGVG_RGPVG_ISR_2(void) ;
+static void NCGVG_RGPVG_ISR_3(void) ;
+
+
+/*=============================================================================
+ *  Private global variables and functions
+ */
+static NCGboolean NCGVG_ISR_Initialized  = NCG_FALSE ;
+static NCGVGISRfp NCGVG_pRGPVG_Interrupt = NCG_NULL ;
+
+
+/*=============================================================================
+ *  Global Function
+ */
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGVG_Attach_ISR
+ FUNCTION   : Attach the function pointer of OpenVG ISR.
+ PARAMETERS : pfnInterrupt : [IN ] The pointer to the function of OpenVG ISR.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGVG_Attach_ISR(
+    NCGVGISRfp      pfnInterrupt )
+{
+    NCGint32        rc_val = NCG_no_err;
+    bsp_int_err_t   eb;
+    errnum_t        e;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGVG_Attach_ISR" );
+
+    NCG_ASSERT(pfnInterrupt != NCG_NULL);
+
+    if( NCGVG_ISR_Initialized != NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGVG_Attach_ISR(1) Initialized.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        rc_val = NCG_err_isr_management_failed ;
+    } else {
+        NCGVG_ISR_Initialized  = NCG_TRUE ;
+        NCGVG_pRGPVG_Interrupt = pfnInterrupt ;
+
+        /* Regist function */
+        eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT0, NCGVG_RGPVG_ISR_0 );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT1, NCGVG_RGPVG_ISR_1 );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT2, NCGVG_RGPVG_ISR_2 );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT3, NCGVG_RGPVG_ISR_3 );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+
+        /* set priority */
+        e= R_OSPL_SetInterruptPriority( BSP_INT_SRC_INT0, NCGVG_INT_LEVEL );
+        IF(e) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        e= R_OSPL_SetInterruptPriority( BSP_INT_SRC_INT1, NCGVG_INT_LEVEL );
+        IF(e) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        e= R_OSPL_SetInterruptPriority( BSP_INT_SRC_INT2, NCGVG_INT_LEVEL );
+        IF(e) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        e= R_OSPL_SetInterruptPriority( BSP_INT_SRC_INT3, NCGVG_INT_LEVEL );
+        IF(e) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+
+        /* Enable interrupt from Renesas OpenVG library */
+        eb= R_BSP_InterruptControl( BSP_INT_SRC_INT0, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptControl( BSP_INT_SRC_INT1, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptControl( BSP_INT_SRC_INT2, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+        eb= R_BSP_InterruptControl( BSP_INT_SRC_INT3, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        IF ( eb != BSP_INT_SUCCESS ) {
+            rc_val = NCG_err_isr_management_failed;
+            goto fin;
+        }
+    }
+
+fin:
+    return rc_val;
+}
+
+
+/*----------------------------------------------------------------------------
+ NAME       : NCGVG_Detach_ISR
+ FUNCTION   : Detach the function pointer of OpenVG ISR.
+ PARAMETERS : pfnInterrupt : [IN ] The pointer to the function of OpenVG ISR.
+ RETURN     : Error code of the NCG.
+------------------------------------------------------------------------------*/
+NCGint32
+NCGVG_Detach_ISR(
+    NCGVGISRfp      pfnInterrupt )
+{
+    NCGint32        rc_val = NCG_no_err;
+    bsp_int_err_t   eb;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGVG_Detach_ISR" );
+
+    NCG_ASSERT(pfnInterrupt != NCG_NULL);
+
+    if ( NCGVG_ISR_Initialized == NCG_FALSE ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGVG_Detach_ISR(1) Not initialized.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        rc_val = NCG_err_isr_management_failed;
+    } else {
+        NCGVG_ISR_Initialized = NCG_FALSE ;
+
+        if( pfnInterrupt == NCGVG_pRGPVG_Interrupt ) {
+            /* Disable interrupt from Renesas OpenVG library */
+            eb= R_BSP_InterruptControl( BSP_INT_SRC_INT3, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptControl( BSP_INT_SRC_INT2, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptControl( BSP_INT_SRC_INT1, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptControl( BSP_INT_SRC_INT0, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+
+            /* Unregist function */
+            eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT3, FIT_NO_FUNC );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT2, FIT_NO_FUNC );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT1, FIT_NO_FUNC );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+            eb= R_BSP_InterruptWrite( BSP_INT_SRC_INT0, FIT_NO_FUNC );
+            IF ( eb != BSP_INT_SUCCESS ) {
+                rc_val = NCG_err_isr_management_failed;
+                goto fin;
+            }
+
+            NCGVG_pRGPVG_Interrupt = NCG_NULL ;
+        } else {
+            NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGVG_Detach_ISR(2) Miss match function pointer.%s" )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+            NCG_DEBUG_MAKE_MSG_END();
+            NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+            rc_val = NCG_err_isr_management_failed;
+        }
+    }
+
+fin:
+    return rc_val;
+}
+
+
+/*=============================================================================
+ *  Internal functions
+ */
+
+/*-----------------------------------------------------------------------------
+ NAME       : NCGVG_RGPVG_ISR
+ FUNCTION   : The Interrrupt from OpenVG.
+ PARAMETERS :
+ RETURN     : None.
+-----------------------------------------------------------------------------*/
+static void NCGVG_RGPVG_ISR(void)
+{
+    NCGuint32 ret ;
+    errnum_t  e;
+
+    NCG_DEBUG_PRINT_STRING( "[LOG] NCGVG_RGPVG_ISR" );
+
+    if( NCGVG_pRGPVG_Interrupt == NCG_NULL ) {
+        NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][INFO]NCGVG_RGPVG_ISR Not initialized.%s" )
+        NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+        NCG_DEBUG_MAKE_MSG_END();
+        NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+    } else {
+        ret = NCGVG_pRGPVG_Interrupt() ;
+        if ( ret != 0 ) {
+            NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGVG_RGPVG_ISR(0x%08x)%s" )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( ret )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+            NCG_DEBUG_MAKE_MSG_END();
+            NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        }
+
+        e= R_GRAPHICS_OnInterrupting();
+        if ( e != 0 ) {
+            NCG_DEBUG_MAKE_MSG_START( NCG_G_MASSAGE_BUFF, "[NCG][ERROR]NCGVG_RGPVG_ISR(e=0x%08x)%s" )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( e )
+            NCG_DEBUG_MAKE_MSG_PARAMETER( NCG_CRLF )
+            NCG_DEBUG_MAKE_MSG_END();
+            NCG_DEBUG_PRINT_MSG( NCG_G_MASSAGE_BUFF );
+        }
+    }
+
+    return ;
+}
+
+/*-----------------------------------------------------------------------------
+ NAME       : NCGVG_RGPVG_ISR_0
+ FUNCTION   : The Interrrupt from OpenVG.
+ PARAMETERS :
+ RETURN     : None.
+-----------------------------------------------------------------------------*/
+static void NCGVG_RGPVG_ISR_0(void)
+{
+    NCGVG_RGPVG_ISR();
+
+    GIC_EndInterrupt( BSP_INT_SRC_INT0 );
+}
+
+/*-----------------------------------------------------------------------------
+ NAME       : NCGVG_RGPVG_ISR_1
+ FUNCTION   : The Interrrupt from OpenVG.
+ PARAMETERS :
+ RETURN     : None.
+-----------------------------------------------------------------------------*/
+static void NCGVG_RGPVG_ISR_1(void)
+{
+    NCGVG_RGPVG_ISR();
+
+    GIC_EndInterrupt( BSP_INT_SRC_INT1 );
+}
+
+/*-----------------------------------------------------------------------------
+ NAME       : NCGVG_RGPVG_ISR_2
+ FUNCTION   : The Interrrupt from OpenVG.
+ PARAMETERS :
+ RETURN     : None.
+-----------------------------------------------------------------------------*/
+static void NCGVG_RGPVG_ISR_2(void)
+{
+    NCGVG_RGPVG_ISR();
+
+    GIC_EndInterrupt( BSP_INT_SRC_INT2 );
+}
+
+/*-----------------------------------------------------------------------------
+ NAME       : NCGVG_RGPVG_ISR_3
+ FUNCTION   : The Interrrupt from OpenVG.
+ PARAMETERS :
+ RETURN     : None.
+-----------------------------------------------------------------------------*/
+static void NCGVG_RGPVG_ISR_3(void)
+{
+    NCGVG_RGPVG_ISR();
+
+    GIC_EndInterrupt( BSP_INT_SRC_INT3 );
+}
+
+#endif
+/* -- end of file -- */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/RGA_API.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,223 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_API.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#ifndef  RGA_API_H
+#define  RGA_API_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "RGA_API_typedef.h"
+#include  "frame_buffer_typedef.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/***********************************************************************
+* Functions: R_RGA
+************************************************************************/
+bool_t  R_RGA_IsSupportedPixelFormatForRGAH( pixel_format_t pixel_format );
+
+
+/***********************************************************************
+* Class: graphics_image_t
+************************************************************************/
+errnum_t  R_GRAPHICS_IMAGE_InitR8G8B8A8(
+    graphics_image_t *self, void *ImageDataArray, size_t ImageDataArraySize,
+    int_fast32_t width, int_fast32_t height );
+errnum_t  R_GRAPHICS_IMAGE_InitSameSizeR8G8B8A8(
+    graphics_image_t *self, void *ImageDataArray, size_t ImageDataArraySize,
+    graphics_image_t *SameSizeImage );
+errnum_t  R_GRAPHICS_IMAGE_InitCopyFrameBufferR8G8B8A8(
+    graphics_image_t *self, void *ImageDataArray, size_t ImageDataArraySize,
+    graphics_t *Context, int_fast32_t MinX,  int_fast32_t MinY,  int_fast32_t width,  int_fast32_t height );
+errnum_t  R_GRAPHICS_IMAGE_InitByShareFrameBuffer( graphics_image_t *self, frame_buffer_t *frame_buffer );
+errnum_t  R_GRAPHICS_IMAGE_GetProperties( const graphics_image_t *self, graphics_image_properties_t *out_Properties );
+errnum_t  R_GRAPHICS_IMAGE_GetImageFormat( const graphics_image_t *self, pixel_format_t *out_Format );
+
+
+/***********************************************************************
+* Class: graphics_pattern_t
+************************************************************************/
+errnum_t  R_GRAPHICS_PATTERN_Initialize( graphics_pattern_t *self,
+        const graphics_image_t *image,  repetition_t repetition,  graphics_t *Context );
+
+
+/***********************************************************************
+* Class: graphics_t
+************************************************************************/
+void      R_GRAPHICS_InitConst( graphics_t *self );
+errnum_t  R_GRAPHICS_Initialize( graphics_t *self, graphics_config_t *Config );
+errnum_t  R_GRAPHICS_Finalize( graphics_t *self, errnum_t e );
+
+errnum_t  R_GRAPHICS_SetFrameBuffer( graphics_t *self, frame_buffer_t *frame_buffer );
+errnum_t  R_GRAPHICS_GetFrameBuffer( graphics_t *self, frame_buffer_t **out_frame_buffer );
+errnum_t  R_GRAPHICS_Finish( graphics_t *self );
+errnum_t  R_GRAPHICS_FinishStart( graphics_t *self, r_ospl_async_t *Async );
+errnum_t  R_GRAPHICS_GetAsyncStatus( graphics_t *self, const graphics_async_status_t **out_Status );
+errnum_t  R_GRAPHICS_OnInterrupting(void);
+
+errnum_t  R_GRAPHICS_Save( graphics_t *self, graphics_status_t *out_Status );
+errnum_t  R_GRAPHICS_Restore( graphics_t *self, graphics_status_t *Status, errnum_t e );
+
+errnum_t  R_GRAPHICS_ResetMatrix( graphics_t *self );
+errnum_t  R_GRAPHICS_SetMatrix_2x3( graphics_t *self,  graphics_matrix_float_t sx,  graphics_matrix_float_t ky,
+                                    graphics_matrix_float_t kx,  graphics_matrix_float_t sy,  graphics_matrix_float_t tx,  graphics_matrix_float_t ty );
+errnum_t  R_GRAPHICS_SetMatrix_3x3( graphics_t *self,  graphics_matrix_float_t *Matrix );
+errnum_t  R_GRAPHICS_GetMatrix_3x3( graphics_t *self,  graphics_matrix_float_t *out_Matrix );
+errnum_t  R_GRAPHICS_TranslateMatrixI( graphics_t *self, int_fast32_t tx, int_fast32_t ty );
+errnum_t  R_GRAPHICS_TranslateMatrix( graphics_t *self, graphics_matrix_float_t tx, graphics_matrix_float_t ty );
+errnum_t  R_GRAPHICS_ScaleMatrix( graphics_t *self, graphics_matrix_float_t sx, graphics_matrix_float_t sy );
+errnum_t  R_GRAPHICS_RotateMatrixDegree( graphics_t *self, graphics_matrix_float_t degree );
+errnum_t  R_GRAPHICS_ShearMatrix( graphics_t *self, graphics_matrix_float_t shx, graphics_matrix_float_t shy );
+errnum_t  R_GRAPHICS_TransformMatrix( graphics_t *self,  graphics_matrix_float_t sx,  graphics_matrix_float_t ky,
+                                      graphics_matrix_float_t kx,  graphics_matrix_float_t sy,  graphics_matrix_float_t tx,  graphics_matrix_float_t ty );
+errnum_t  R_GRAPHICS_MultiplyMatrix( graphics_t *self,  graphics_matrix_float_t *Matrix );
+errnum_t  R_GRAPHICS_GetProjectiveMatrix(
+    graphics_matrix_float_t SourceTopLeftX,           graphics_matrix_float_t SourceTopLeftY,
+    graphics_matrix_float_t SourceTopRightX,          graphics_matrix_float_t SourceTopRightY,
+    graphics_matrix_float_t SourceBottomLeftX,        graphics_matrix_float_t SourceBottomLeftY,
+    graphics_matrix_float_t SourceBottomRightX,       graphics_matrix_float_t SourceBottomRightY,
+    graphics_matrix_float_t DestinationTopLeftX,      graphics_matrix_float_t DestinationTopLeftY,
+    graphics_matrix_float_t DestinationTopRightX,     graphics_matrix_float_t DestinationTopRightY,
+    graphics_matrix_float_t DestinationBottomLeftX,   graphics_matrix_float_t DestinationBottomLeftY,
+    graphics_matrix_float_t DestinationBottomRightX,  graphics_matrix_float_t DestinationBottomRightY,
+    graphics_matrix_float_t *out_Matrix );
+
+errnum_t  R_GRAPHICS_SetBackgroundColor( graphics_t *self, r8g8b8a8_t Color );
+errnum_t  R_GRAPHICS_GetBackgroundColor( graphics_t *self, r8g8b8a8_t *out_Color );
+errnum_t  R_GRAPHICS_GetClearColor( graphics_t *self, r8g8b8a8_t *out_Color );
+errnum_t  R_GRAPHICS_Clear( graphics_t *self,
+                            int_fast32_t MinX, int_fast32_t MinY, int_fast32_t width, int_fast32_t height );
+
+errnum_t  R_GRAPHICS_DrawImage( graphics_t *self,  const graphics_image_t *image,
+                                int_fast32_t MinX,  int_fast32_t MinY );
+errnum_t  R_GRAPHICS_DrawImageResized( graphics_t *self,  const graphics_image_t *image,
+                                       int_fast32_t MinX,  int_fast32_t MinY,  int_fast32_t width,  int_fast32_t height );
+errnum_t  R_GRAPHICS_DrawImageChild( graphics_t *self,  const graphics_image_t *image,
+                                     int_fast32_t SourceMinX,        int_fast32_t SourceMinY,
+                                     int_fast32_t SourceWidth,       int_fast32_t SourceHeight,
+                                     int_fast32_t DestinationMinX,   int_fast32_t DestinationMinY,
+                                     int_fast32_t DestinationWidth,  int_fast32_t DestinationHeight );
+
+errnum_t  R_GRAPHICS_FillRect( graphics_t *self,  int_fast32_t MinX,  int_fast32_t MinY,
+                               int_fast32_t width,  int_fast32_t height );
+errnum_t  R_GRAPHICS_SetFillColor( graphics_t *self, r8g8b8a8_t Color );
+errnum_t  R_GRAPHICS_SetFillPattern( graphics_t *self, graphics_pattern_t *Pattern );
+
+errnum_t  R_GRAPHICS_StrokeRect( graphics_t *self,  int_fast32_t MinX,  int_fast32_t MinY,
+                                 int_fast32_t width,  int_fast32_t height );
+errnum_t  R_GRAPHICS_SetStrokeColor( graphics_t *self, r8g8b8a8_t Color );
+
+errnum_t  R_GRAPHICS_BeginPath( graphics_t *self );
+errnum_t  R_GRAPHICS_Rect( graphics_t *self,  int_t MinX,  int_t MinY,
+                           int_t width,  int_t height );
+errnum_t  R_GRAPHICS_Cilp( graphics_t *self );
+
+errnum_t  R_GRAPHICS_SetGlobalAlpha( graphics_t *self, uint8_t AlphaValue );
+errnum_t  R_GRAPHICS_GetGlobalAlpha( graphics_t *self, uint8_t *out_AlphaValue );
+errnum_t  R_GRAPHICS_SetGlobalCompositeOperation( graphics_t *self,
+        graphics_composite_operation_t CompositeOperation );
+errnum_t  R_GRAPHICS_GetGlobalCompositeOperation( graphics_t *self,
+        graphics_composite_operation_t *out_CompositeOperation );
+
+errnum_t  R_GRAPHICS_SetQualityFlags( graphics_t *self,
+                                      graphics_quality_flags_t Qualities );
+errnum_t  R_GRAPHICS_GetQualityFlags( graphics_t *self,
+                                      graphics_quality_flags_t *out_Qualities );
+
+
+/***********************************************************************
+* Class: graphics_static_t
+************************************************************************/
+graphics_static_t  *get_graphics_static(void);
+errnum_t  R_GRAPHICS_STATIC_GetVersion( uint32_t *out_Version );
+errnum_t  R_GRAPHICS_STATIC_OnInitializeDefault( graphics_t *self, graphics_config_t *in_out_Config,
+        void **out_CalleeDefined );
+errnum_t  R_GRAPHICS_STATIC_OnFinalizeDefault( graphics_t *self, void *CalleeDefined, errnum_t e );
+errnum_t  R_GRAPHICS_STATIC_SetOnInitialize(
+    R_GRAPHICS_OnInitialize_FuncType CallbackFunction );
+errnum_t  R_GRAPHICS_STATIC_SetOnFinalize(
+    R_GRAPHICS_OnFinalize_FuncType CallbackFunction );
+
+
+/***********************************************************************
+* Class: RGA_SHS
+*    Synchronize hardware and software rendering
+************************************************************************/
+errnum_t  R_GRAPHICS_BeginSoftwareRendering( graphics_t *self );
+errnum_t  R_GRAPHICS_BeginSoftwareRendering2( graphics_t *self );
+errnum_t  R_GRAPHICS_BeginSoftwareRenderingA( graphics_t *self, void *Address );
+errnum_t  R_GRAPHICS_EndSoftwareRendering( graphics_t *self );
+errnum_t  R_GRAPHICS_EndRenderingInFin( graphics_t *self, errnum_t e );
+
+
+/***********************************************************************
+* Class: animation_timing_function_t
+************************************************************************/
+errnum_t  R_Get_AnimationTimingFunction( char_t *TimingName,
+        animation_timing_function_t **out_Timing );
+
+float32_t  R_ANIMATION_TIMING_FUNCTION_GetValue( animation_timing_function_t *self,
+        float32_t ClampTime, float32_t ValueOfPreviousKeyFrame, float32_t ValueOfNextKeyFrame );
+
+
+/***********************************************************************
+* Functions: Self_Test_for_Package
+************************************************************************/
+errnum_t  R_RGA_CheckStructSize( size_t SizeOf_GraphicsClass, size_t SizeOf_GraphicsStatusClass,
+                                 size_t Zero );
+
+
+#ifdef  __cplusplus
+}  /* extern "C" */
+#endif
+
+#endif  /* RGA_API_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/RGA_API_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,324 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_API_typedef.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#ifndef  RGA_API_TYPEDEF_H
+#define  RGA_API_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_ospl_typedef.h"
+#include  "locking_typedef.h"
+#include  "clib_drivers_typedef.h"
+#include  "frame_buffer_typedef.h"
+#include  "RGA_raw_image_typedef.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   graphics_quality_flag_t
+* @brief  graphics_quality_flag_t
+*/
+typedef enum {
+    /* Set to "ON" */
+    GRAPHICS_RENDERING_QUALITY_ANTIALIASED     = 0x0001,
+    GRAPHICS_IMAGE_QUALITY_ANTIALIASED         = 0x0002,
+
+    /* Set to "OFF" */
+    GRAPHICS_RENDERING_QUALITY_NONANTIALIASED  = GRAPHICS_RENDERING_QUALITY_ANTIALIASED << 16,
+    GRAPHICS_IMAGE_QUALITY_NONANTIALIASED      = GRAPHICS_IMAGE_QUALITY_ANTIALIASED << 16
+}
+        graphics_quality_flag_t;
+
+
+/**
+* @enum   graphics_jpeg_decoder_t
+* @brief  graphics_jpeg_decoder_t
+*/
+typedef enum {
+    GRAPHICS_JPEG_DECODER_NONE = 0,
+    GRAPHICS_JPEG_DECODER_HARD = 1
+} graphics_jpeg_decoder_t;
+
+
+/**
+* @typedef  graphics_quality_flags_t
+* @brief  graphics_quality_flags_t
+*/
+typedef bit_flags_fast32_t /*<graphics_quality_flag_t>*/  graphics_quality_flags_t;
+
+
+/**
+* @struct  graphics_config_t
+* @brief  graphics_config_t
+*/
+typedef struct _GraphicsConfigClass  graphics_config_t;
+struct _GraphicsConfigClass {
+    bit_flags32_t    flags;
+    frame_buffer_t  *frame_buffer;  /* F_GRAPHICS_FRAME_BUFFER */
+
+    /* for RGAH/RGAS hardware renderer */
+    void   *work_buffer_address;         /* F_GRAPHICS_WORK_BUFFER_ADDRESS */
+    size_t  work_buffer_size;            /* F_GRAPHICS_WORK_BUFFER_SIZE */
+    int_fast32_t  max_width_of_frame_buffer;   /* F_GRAPHICS_MAX_WIDTH_OF_FRAME_BUFFER */
+    int_fast32_t  max_height_of_frame_buffer;  /* F_GRAPHICS_MAX_HEIGHT_OF_FRAME_BUFFER */
+
+    /* for any */
+    graphics_quality_flags_t  quality_flags;         /* F_GRAPHICS_QUALITY_FLAGS */
+    r8g8b8a8_t                background_color;      /* F_GRAPHICS_BACK_GROUND_COLOR */
+    bool_t                    is_fast_manual_flush;  /* F_GRAPHICS_IS_FAST_MANUAL_FLUSH */
+
+    /* work buffer B */
+    void   *work_buffer_b_address;       /* F_GRAPHICS_WORK_BUFFER_B_ADDRESS */
+    size_t  work_buffer_b_size;          /* F_GRAPHICS_WORK_BUFFER_B_SIZE */
+
+    /* JPEG */
+    graphics_jpeg_decoder_t  jpeg_decoder;  /* F_GRAPHICS_JPEG_DECODER */
+
+    /* PNG */
+    size_t  work_size_for_libPNG;  /* F_GRAPHICS_WORK_SIZE_FOR_LIBPNG */
+
+    /* Asynchronous call */
+    bit_flags32_t  internal_event_value;  /* F_GRAPHICS_INTERNAL_EVENT_VALUE : 16bit */
+
+    /* Thread safe */
+    BSP_CFG_USER_LOCKING_TYPE  *lock_object;  /* F_GRAPHICS_LOCK_OBJECT */
+
+    /* for RGAS */
+    int_fast32_t  channel_of_DMAC_1;      /* F_GRAPHICS_CHANNEL_OF_DMAC_1 */
+    int_fast32_t  channel_of_DMAC_2;      /* F_GRAPHICS_CHANNEL_OF_DMAC_2 */
+    int_fast32_t  event_value_of_DMAC_1;  /* F_GRAPHICS_EVENT_VALUE_OF_DMAC_1 */
+    int_fast32_t  event_value_of_DMAC_2;  /* F_GRAPHICS_EVENT_VALUE_OF_DMAC_2 */
+};
+enum {
+    F_GRAPHICS_FRAME_BUFFER               = 0x0001,
+    F_GRAPHICS_WORK_BUFFER_ADDRESS        = 0x0002,
+    F_GRAPHICS_WORK_BUFFER_SIZE           = 0x0004,
+    F_GRAPHICS_MAX_HEIGHT_OF_FRAME_BUFFER = 0x0008,
+    F_GRAPHICS_MAX_WIDTH_OF_FRAME_BUFFER  = 0x0080,
+    F_GRAPHICS_QUALITY_FLAGS              = 0x0010,
+    F_GRAPHICS_BACK_GROUND_COLOR          = 0x0020,
+    F_GRAPHICS_IS_FAST_MANUAL_FLUSH       = 0x0040,
+    F_GRAPHICS_WORK_BUFFER_B_ADDRESS      = 0x0100,
+    F_GRAPHICS_WORK_BUFFER_B_SIZE         = 0x0200,
+    F_GRAPHICS_JPEG_DECODER               = 0x1000,
+    F_GRAPHICS_WORK_SIZE_FOR_LIBPNG       = 0x8000,
+    F_GRAPHICS_INTERNAL_EVENT_VALUE       = 0x2000,
+    F_GRAPHICS_LOCK_OBJECT                = 0x4000,
+    F_GRAPHICS_CHANNEL_OF_DMAC_1          = 0x0400,
+    F_GRAPHICS_CHANNEL_OF_DMAC_2          = 0x0800,
+    F_GRAPHICS_EVENT_VALUE_OF_DMAC_1    = 0x040000,
+    F_GRAPHICS_EVENT_VALUE_OF_DMAC_2    = 0x080000
+};
+
+
+/**
+* @typedef  graphics_matrix_float_t
+* @brief  graphics_matrix_float_t
+*/
+typedef  float  graphics_matrix_float_t;
+
+
+/**
+* @struct  graphics_matrix3x3_t
+* @brief  graphics_matrix3x3_t
+*/
+typedef union {
+    graphics_matrix_float_t   xy[3][3];  /* [x][y] */
+    graphics_matrix_float_t   array[9];  /* { sx, shy, w0, shx, sy, w1, tx, ty, w2 } */
+} graphics_matrix3x3_t;
+
+
+/**
+* @struct  graphics_image_properties_t
+* @brief  graphics_image_properties_t
+*/
+#if  IS_SUPPORT_SAME_TYPEDEF  || ! defined( graphics_image_properties_t )
+typedef struct _GraphicsImagePropertiesClass  graphics_image_properties_t;
+#define         graphics_image_properties_t   graphics_image_properties_t
+#endif
+struct _GraphicsImagePropertiesClass {
+    int_fast32_t     width;
+    int_fast32_t     height;
+    uint8_t         *data;    /* NULL, if pixelFormat != PIXEL_FORMAT_R8G8B8A8 */
+    void            *pixels;  /* Same as "data" but not NULL */
+    pixel_format_t   pixelFormat;
+    uint32_t        *CLUT;
+    int_fast32_t     CLUT_count;
+};
+
+
+/**
+* @enum   repetition_t
+* @brief  repetition_t
+*/
+typedef enum st_repetition_t {
+    GRAPHICS_REPEAT = 1
+} repetition_t;
+
+
+/**
+* @struct  graphics_pattern_t
+* @brief  graphics_pattern_t
+*/
+typedef struct st_graphics_pattern_t  graphics_pattern_t;
+struct st_graphics_pattern_t {
+    graphics_image_t *image;
+    repetition_t      repetition;
+};
+
+
+/**
+* @enum   graphics_composite_operation_t
+* @brief  graphics_composite_operation_t
+*/
+typedef enum st_graphics_composite_operation_t {
+    GRAPHICS_SOURCE_OVER = 1,
+    GRAPHICS_DESTINATION_OUT = 7,
+    GRAPHICS_COPY = 0
+} graphics_composite_operation_t;
+
+
+/**
+* @struct  graphics_status_t
+* @brief  graphics_status_t
+*/
+typedef struct st_graphics_status_t  graphics_status_t;
+struct st_graphics_status_t {
+    uint8_t  __Members[0x30];
+};
+
+
+/**
+* @struct  graphics_hard_status_t
+* @brief  graphics_hard_status_t
+*/
+#ifdef  RGAH_VERSION
+typedef struct st_graphics_hard_status_t  graphics_hard_status_t;
+struct st_graphics_hard_status_t {
+    volatile bool_t  IsRenderingCompleted;
+};
+#endif
+
+
+/**
+* @struct  graphics_async_status_t
+* @brief  graphics_async_status_t
+*/
+typedef struct st_graphics_async_status_t  graphics_async_status_t;
+struct st_graphics_async_status_t {
+    volatile r_ospl_async_state_t  State;
+    r_ospl_async_t *volatile       Async;
+    BSP_CFG_USER_LOCKING_TYPE     *CLock;
+    r_ospl_thread_id_t             LockedThread;
+#ifdef  RGAH_VERSION
+    const graphics_hard_status_t  *Hardware;
+#endif
+};
+
+
+/**
+* @struct  graphics_t
+* @brief  graphics_t
+*/
+#if  IS_SUPPORT_SAME_TYPEDEF  || ! defined( graphics_t )
+typedef struct st_graphics_t  graphics_t;
+#endif
+struct st_graphics_t {
+    uint8_t  __Members[0x118];
+};
+
+
+/**
+* @brief   R_GRAPHICS_OnInitialize_FuncType
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+typedef  errnum_t  (*R_GRAPHICS_OnInitialize_FuncType)(
+    graphics_t *self, graphics_config_t *in_out_Config, void **out_CalleeDefined );
+
+/**
+* @brief   R_GRAPHICS_OnFinalize_FuncType
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+typedef  errnum_t  (*R_GRAPHICS_OnFinalize_FuncType)(
+    graphics_t *self, void *CalleeDefined, errnum_t e );
+
+
+/**
+* @struct  graphics_static_t
+* @brief  graphics_static_t
+*/
+typedef struct st_graphics_static_t  graphics_static_t;
+struct st_graphics_static_t {
+    R_GRAPHICS_OnInitialize_FuncType  OnInitialize;
+    R_GRAPHICS_OnFinalize_FuncType    OnFinalize;
+    graphics_t                       *Contexts[1];
+};
+
+
+/**
+* @struct  animation_timing_function_t
+* @brief  animation_timing_function_t
+*/
+typedef struct _CSS_animation_timing_function_Class  animation_timing_function_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+#ifdef  __cplusplus
+}  /* extern "C" */
+#endif
+
+#endif  /* RGA_API_TYPEDEF_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/RGA_Config.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,155 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Config.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+
+/* This file is included from "Project_Config.h" */
+
+
+#ifndef  RGA_CONFIG_H
+#define  RGA_CONFIG_H
+
+
+/**
+* @def  RGA_VERSION
+* @brief  RGA_VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  RGA_VERSION  120
+
+
+/**
+* @def  RGA_VERSION_STRING
+* @brief  RGA_VERSION_STRING
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  RGA_VERSION_STRING  "1.20"
+
+
+/**
+* @def  GSCE_VERSION
+* @brief  GSCE_VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  GSCE_VERSION  402
+
+
+/**
+* @def  RGAH_VERSION
+* @brief  RGAH_VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+/**
+* @def  RGAS_VERSION
+* @brief  RGAS_VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+
+#ifdef R_ARM
+#define  IS_RGAH_ARM_VERSION
+/* #define  IS_RGAS_ARM_VERSION */
+#endif
+
+#ifdef _SH
+#define  IS_RGAH_SH_VERSION
+/* #define  IS_RGAS_SH_VERSION */
+#endif
+
+#ifdef _MSC_VER
+/* #define  IS_RGAH_PC_VERSION */
+#define  IS_RGAS_PC_VERSION
+#endif
+
+#if defined( IS_RGAH_ARM_VERSION ) || defined( IS_RGAH_SH_VERSION ) || defined( IS_RGAH_PC_VERSION )
+#define  RGAH_VERSION  103
+#endif
+
+#if defined( IS_RGAS_ARM_VERSION ) || defined( IS_RGAS_SH_VERSION ) || defined( IS_RGAS_PC_VERSION )
+#define  RGAS_VERSION  203
+#endif
+
+#undef  IS_RGAS_ARM_VERSION
+#undef  IS_RGAH_ARM_VERSION
+#undef  IS_RGAS_SH_VERSION
+#undef  IS_RGAH_SH_VERSION
+#undef  IS_RGAS_PC_VERSION
+#undef  IS_RGAH_PC_VERSION
+/* Use "R_ARM" or "RGAH_VERSION" */
+
+
+/**
+* @def  IS_WINDOW_SURFACES_EX
+* @brief  define or not define
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_WINDOW_SURFACES_EX
+
+
+/***********************************************************************
+* Macros: RGA_LIMITATION_*
+*    0 or 1
+************************************************************************/
+#ifdef  RGAH_VERSION
+#define  RGA_LIMITATION_01_MATRIXED_IMAGE_STRIDE  1
+#define  RGA_LIMITATION_02_XRGB8888_BLEND         0
+#define  RGA_LIMITATION_03_INIT_BMP               1
+#define  RGA_LIMITATION_04_AYNCHRONOOUS_JCU       1
+#define  RGA_LIMITATION_06_COLOR_LITTLE_ERROR     1
+#define  RGA_LIMITATION_07_DRAWIMAGE_VERTEX_ERR   1
+#define  RGA_LIMITATION_08_OPTIMIZATION_ERR       0
+#define  RGA_LIMITATION_09_RGAH_BITBLT_CLIP       1
+#define  RGA_LIMITATION_11_SOURCE_FLUSH_B         0
+#else
+#define  RGA_LIMITATION_01_MATRIXED_IMAGE_STRIDE  0
+#define  RGA_LIMITATION_02_XRGB8888_BLEND         0
+#define  RGA_LIMITATION_03_INIT_BMP               0
+#define  RGA_LIMITATION_04_AYNCHRONOOUS_JCU       1
+#define  RGA_LIMITATION_06_COLOR_LITTLE_ERROR     0
+#define  RGA_LIMITATION_07_DRAWIMAGE_VERTEX_ERR   1
+#define  RGA_LIMITATION_08_OPTIMIZATION_ERR       0
+#define  RGA_LIMITATION_09_RGAH_BITBLT_CLIP       0
+#define  RGA_LIMITATION_11_SOURCE_FLUSH_B         0
+#endif
+
+
+#endif  /* __RGA_CONFIG_H */
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/RGA_Cpp.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,517 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Cpp.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#ifndef  RGA_CPP_H
+#define  RGA_CPP_H
+
+#ifndef __cplusplus
+#error C++ only
+#endif
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "RGA.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+typedef float  graphics_matrix_float_t;
+typedef double graphics_matrix_other_float_t;
+
+
+/***********************************************************************
+* Class: ObjectHandleClass
+************************************************************************/
+class  ObjectHandleClass
+{
+public:
+    void  *Entity;
+
+    ObjectHandleClass() {
+        this->Entity = NULL;
+    }
+};
+
+bool_t  operator == ( ObjectHandleClass Left, ObjectHandleClass Right );
+
+
+/** undefined */
+#define  undefined  get_undefined()
+extern ObjectHandleClass  get_undefined();
+
+
+/***********************************************************************
+* Class: saveList_st
+************************************************************************/
+struct saveList_st {
+    saveList_st       *beforePoint;
+    graphics_status_t  saveData;
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_ImageEntityClass
+************************************************************************/
+class Canvas2D_ImageEntityClass
+{
+public:
+    graphics_image_t  *C_Image;
+    bool_t               isImageDataComposition;
+
+    Canvas2D_ImageEntityClass( bool_t composition ) {
+        this->C_Image = NULL;
+        this->isImageDataComposition = composition;
+    }
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_ImageClass
+************************************************************************/
+class  Canvas2D_ImageClass
+{
+public:
+    Canvas2D_ImageEntityClass  *Entity;
+
+    Canvas2D_ImageClass() {
+        this->Entity = NULL;
+    }
+
+    operator ObjectHandleClass () {
+        return  *(ObjectHandleClass *) this;
+    }
+
+    Canvas2D_ImageClass &operator = ( ObjectHandleClass Right ) {
+        this->Entity = (Canvas2D_ImageEntityClass *) Right.Entity;
+        return  *this;
+    }
+
+
+    void  set_imageClass( graphics_image_t *imageClass );
+    inline void  operator= ( graphics_image_t *imageClass ) {
+        this->set_imageClass( imageClass );
+    }
+
+    inline operator graphics_image_t *() {
+        return  this->Entity->C_Image;
+    }
+
+
+    void destroy();
+
+
+    /* "width" property */
+    class  widthProperty
+    {
+    public:
+        inline operator int_t() {
+            graphics_image_properties_t  prop;
+            errnum_t e;
+            Canvas2D_ImageClass  *parent = (Canvas2D_ImageClass *)(
+                                               (char *) this - offsetof( Canvas2D_ImageClass, width ) );
+            e = R_GRAPHICS_IMAGE_GetProperties( parent->Entity->C_Image, &prop );
+            if( e ) {
+                R_OSPL_SetErrNum( e );
+                prop.width = 0;
+            }
+            return  prop.width;
+        }
+    } width;
+
+    /* "height" property */
+    class  heightProperty
+    {
+    public:
+        inline operator int_t() {
+            graphics_image_properties_t  prop;
+            errnum_t e;
+            Canvas2D_ImageClass  *parent = (Canvas2D_ImageClass *)(
+                                               (char *) this - offsetof( Canvas2D_ImageClass, height ) );
+            e = R_GRAPHICS_IMAGE_GetProperties( parent->Entity->C_Image, &prop );
+            if( e ) {
+                R_OSPL_SetErrNum( e );
+                prop.height = 0;
+            }
+            return  prop.height;
+        }
+    } height;
+
+    /* "data" property */
+    class  dataProperty
+    {
+    public:
+        inline operator uint8_t *() {
+            graphics_image_properties_t  prop;
+            errnum_t e;
+            Canvas2D_ImageClass  *parent = (Canvas2D_ImageClass *)(
+                                               (char *) this - offsetof( Canvas2D_ImageClass, data ) );
+            e = R_GRAPHICS_IMAGE_GetProperties( parent->Entity->C_Image, &prop );
+            if( e ) {
+                R_OSPL_SetErrNum( e );
+                prop.data = NULL;
+            }
+            return  prop.data;
+        }
+
+        inline operator r8g8b8a8_t *() {
+            return  (r8g8b8a8_t *)(uint8_t *) *this;
+        }
+
+        inline operator void *() {
+            return  (void *)(uint8_t *) *this;
+        }
+
+        inline uint8_t  &operator[]( int Index ) {
+            return  ( (uint8_t *) *this )[ Index ];
+        }
+
+        inline uint8_t  *operator+( int Index ) {
+            return  ( (uint8_t *) *this ) + Index;
+        }
+    } data;
+
+    /* "src" property */
+    class  srcProperty
+    {
+    public:
+        inline void  operator= ( const graphics_image_t *imageClass ) {
+            Canvas2D_ImageClass  *parent = (Canvas2D_ImageClass *)(
+                                               (char *) this - offsetof( Canvas2D_ImageClass, src ) );
+
+            parent->set_imageClass( (graphics_image_t *)imageClass );
+        }
+        inline operator graphics_image_t *() {
+            graphics_image_t *outData = NULL;
+            Canvas2D_ImageClass  *parent = (Canvas2D_ImageClass *)(
+                                               (char *) this - offsetof( Canvas2D_ImageClass, src ) );
+
+            if( parent->Entity != NULL ) {
+                outData = parent->Entity->C_Image;
+            }
+            return outData;
+        }
+    } src;
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_PatternClass
+************************************************************************/
+class  Canvas2D_PatternClass
+{
+public:
+    graphics_pattern_t  *Entity;
+
+    Canvas2D_PatternClass() {
+        this->Entity = NULL;
+    }
+
+    operator ObjectHandleClass () {
+        return  *(ObjectHandleClass *) this;
+    }
+
+    Canvas2D_PatternClass &operator = ( ObjectHandleClass Right ) {
+        this->Entity = (graphics_pattern_t *) Right.Entity;
+        return  *this;
+    }
+
+    void destroy();
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_ContextEntityClass
+************************************************************************/
+class Canvas2D_ContextEntityClass
+{
+public:
+    graphics_t  *C_Graphics;
+    saveList_st    *LastSavePoint;
+
+    Canvas2D_ContextEntityClass() {
+        this->C_Graphics = NULL;
+        this->LastSavePoint = NULL;
+    }
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_ContextClass
+************************************************************************/
+class  Canvas2D_ContextClass
+{
+public:
+    Canvas2D_ContextEntityClass  *Entity;
+
+    Canvas2D_ContextClass() {
+        this->Entity = NULL;
+    }
+
+    operator ObjectHandleClass () {
+        return  *(ObjectHandleClass *) this;
+    }
+
+    Canvas2D_ContextClass &operator = ( ObjectHandleClass Right ) {
+        this->Entity = (Canvas2D_ContextEntityClass *) Right.Entity;
+        return  *this;
+    }
+
+    void  destroy();
+    void  clearRect( int x, int y, int w, int h );
+    void  save();
+    void  restore();
+    void  drawImage( const graphics_image_t *image, int_t minX, int_t minY );
+    void  drawImage( const graphics_image_t *image, int_t minX, int_t minY , int_t width, int_t height );
+    void  drawImage( const graphics_image_t *image, int_t srcMinX,  int_t srcMinY,  int_t srcWidth,   int_t srcHeight,
+                     int_t destMinx, int_t destMinY, int_t destWidth , int_t destHeight );
+    Canvas2D_ImageClass  createImageData( Canvas2D_ImageClass image );
+    Canvas2D_ImageClass  createImageData( int_t width, int_t height );
+    Canvas2D_ImageClass  getImageData( int_t minX, int_t minY, int_t width, int_t height );
+    void  putImageData( Canvas2D_ImageClass imageData, int_t minX, int_t minY );
+    void  putImageData ( Canvas2D_ImageClass imageData, int_t minX, int_t minY, int_t dirtyX, int_t dirtyY, int_t dirtyWidth, int_t dirtyHeight );
+    void  fillRect( int x, int y, int w, int h );
+    Canvas2D_PatternClass  createPattern( const graphics_image_t *image, const char *repetition );
+    void  beginPath();
+    void  rect( int_t minX, int_t minY, int_t width, int_t height );
+    void  clip();
+
+    void  setTransform( graphics_matrix_float_t sx,  graphics_matrix_float_t ky,
+                        graphics_matrix_float_t kx,  graphics_matrix_float_t sy,
+                        graphics_matrix_float_t tx,  graphics_matrix_float_t ty );
+    void  setTransform( graphics_matrix_other_float_t sx,  graphics_matrix_other_float_t ky,
+                        graphics_matrix_other_float_t kx,  graphics_matrix_other_float_t sy,
+                        graphics_matrix_other_float_t tx,  graphics_matrix_other_float_t ty ) {
+        setTransform( (graphics_matrix_float_t) sx,  (graphics_matrix_float_t) ky,
+                      (graphics_matrix_float_t) kx,  (graphics_matrix_float_t) sy,
+                      (graphics_matrix_float_t) tx,  (graphics_matrix_float_t) ty );
+    }
+    void  setTransform( int_t sx,  int_t ky, int_t kx,  int_t sy, int_t tx,  int_t ty ) {
+        setTransform( (graphics_matrix_float_t) sx,  (graphics_matrix_float_t) ky,
+                      (graphics_matrix_float_t) kx,  (graphics_matrix_float_t) sy,
+                      (graphics_matrix_float_t) tx,  (graphics_matrix_float_t) ty );
+    }
+
+    void  translate( graphics_matrix_float_t tx, graphics_matrix_float_t ty );
+    void  translate( graphics_matrix_other_float_t tx, graphics_matrix_other_float_t ty ) {
+        translate( (graphics_matrix_float_t) tx, (graphics_matrix_float_t) ty );
+    }
+    void  translate( graphics_matrix_float_t tx, graphics_matrix_other_float_t ty ) {
+        translate( tx, (graphics_matrix_float_t) ty );
+    }
+    void  translate( graphics_matrix_other_float_t tx, graphics_matrix_float_t ty ) {
+        translate( (graphics_matrix_float_t) tx, ty );
+    }
+    void  translate( int_t tx, int_t ty ) {
+        translate( (graphics_matrix_float_t) tx, (graphics_matrix_float_t) ty );
+    }
+
+    void  scale( graphics_matrix_float_t sx, graphics_matrix_float_t sy );
+    void  scale( graphics_matrix_other_float_t sx, graphics_matrix_other_float_t sy ) {
+        scale( (graphics_matrix_float_t) sx, (graphics_matrix_float_t) sy );
+    }
+    void  scale( graphics_matrix_float_t sx, graphics_matrix_other_float_t sy ) {
+        scale( sx, (graphics_matrix_float_t) sy );
+    }
+    void  scale( graphics_matrix_other_float_t sx, graphics_matrix_float_t sy ) {
+        scale( (graphics_matrix_float_t) sx, sy );
+    }
+    void  scale( int_t sx, int_t sy ) {
+        scale( (graphics_matrix_float_t) sx, (graphics_matrix_float_t) sy );
+    }
+
+    void  rotate( graphics_matrix_float_t angle );
+    void  rotate( graphics_matrix_other_float_t angle ) {
+        rotate( (graphics_matrix_float_t) angle );
+    }
+
+    void  transform( graphics_matrix_float_t sx,  graphics_matrix_float_t ky,
+                     graphics_matrix_float_t kx,  graphics_matrix_float_t sy,
+                     graphics_matrix_float_t tx,  graphics_matrix_float_t ty );
+    void  transform( graphics_matrix_other_float_t sx,  graphics_matrix_other_float_t ky,
+                     graphics_matrix_other_float_t kx,  graphics_matrix_other_float_t sy,
+                     graphics_matrix_other_float_t tx,  graphics_matrix_other_float_t ty ) {
+        transform( (graphics_matrix_float_t) sx,  (graphics_matrix_float_t) ky,
+                   (graphics_matrix_float_t) kx,  (graphics_matrix_float_t) sy,
+                   (graphics_matrix_float_t) tx,  (graphics_matrix_float_t) ty );
+    }
+    void  transform( int_t sx,  int_t ky,  int_t kx,  int_t sy,  int_t tx,  int_t ty ) {
+        transform( (graphics_matrix_float_t) sx,  (graphics_matrix_float_t) ky,
+                   (graphics_matrix_float_t) kx,  (graphics_matrix_float_t) sy,
+                   (graphics_matrix_float_t) tx,  (graphics_matrix_float_t) ty );
+    }
+
+
+    /* "fillStyle" property */
+    void  Set_fillStyle( const char *Color );
+    void  Set_fillStyle( r8g8b8a8_t Color );
+    void  Set_fillStylePattern( const Canvas2D_PatternClass Pattern );
+#if 0
+    void  Set_fillStyleGradient( const Canvas2D_GradientClass Gradient );
+#endif
+    class  fillStyleProperty
+    {
+    public:
+        inline void  operator= ( const char *Color ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, fillStyle ) );
+
+            parent->Set_fillStyle( Color );
+        }
+        inline void  operator= ( r8g8b8a8_t Color ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, fillStyle ) );
+
+            parent->Set_fillStyle( Color );
+        }
+        inline void  operator= ( const Canvas2D_PatternClass Pattern ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, fillStyle ) );
+
+            parent->Set_fillStylePattern( Pattern );
+        }
+#if 0
+        inline void  operator= ( const Canvas2D_GradientClass Gradient ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, fillStyle ) );
+
+            parent->Set_fillStyleGradient( Gradient );
+        }
+#endif
+    } fillStyle;
+
+
+    /* "c_LanguageContext" property */
+    class  c_LanguageContextProperty
+    {
+        inline graphics_t  *get_c_LanguageContext() {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, c_LanguageContext ) );
+
+            return  parent->Entity->C_Graphics;
+        }
+    public:
+
+        inline operator graphics_t *() {
+            return  get_c_LanguageContext();
+        }
+        inline graphics_t *operator->() {
+            return  get_c_LanguageContext();
+        }
+    } c_LanguageContext;
+
+
+    /* "globalAlpha" property */
+    void set_globalAlpha( const float32_t alpha );
+    float32_t get_globalAlpha();
+    class  globalAlphaProperty
+    {
+    public:
+        inline void  operator= ( const float32_t alpha ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, globalAlpha ) );
+
+            parent->set_globalAlpha( alpha );
+        }
+        inline void  operator= ( const float64_t alpha ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, globalAlpha ) );
+
+            parent->set_globalAlpha( (float32_t) alpha );
+        }
+        inline operator float32_t() {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, globalAlpha ) );
+
+            return parent->get_globalAlpha();
+        }
+    } globalAlpha;
+
+
+    /* "globalCompositeOperation" property */
+    void set_globalCompositeOperation( const char *operation );
+    char *get_globalCompositeOperation();
+    class  globalCompositeOperationProperty
+    {
+    public:
+        inline void  operator= ( const char *operation ) {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, globalCompositeOperation ) );
+
+            parent->set_globalCompositeOperation( operation );
+        }
+        inline operator char *() {
+            Canvas2D_ContextClass  *parent = (Canvas2D_ContextClass *)(
+                                                 (char *) this - offsetof( Canvas2D_ContextClass, globalCompositeOperation ) );
+
+            return parent->get_globalCompositeOperation();
+        }
+    } globalCompositeOperation;
+
+};
+
+
+/***********************************************************************
+* Class: Canvas2D_ContextConfigClass
+************************************************************************/
+struct  Canvas2D_ContextConfigClass {
+    frame_buffer_t  *frame_buffer;
+    bool_t           is_fast_manual_flush;
+
+    Canvas2D_ContextConfigClass() {
+        frame_buffer = NULL;
+        is_fast_manual_flush = false;
+    }
+};
+
+
+/***********************************************************************
+* Functions: Canvas2D_Constructers
+************************************************************************/
+Canvas2D_ContextClass  R_RGA_New_Canvas2D_ContextClass( frame_buffer_t *frame_buffer );
+Canvas2D_ContextClass  R_RGA_New_Canvas2D_ContextClass( Canvas2D_ContextConfigClass &in_out_Config );
+Canvas2D_ImageClass  R_RGA_New_Canvas2D_ImageClass();
+
+#endif  // RGA_CPP_H
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/RGA_Port.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,135 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: RGA_Port.h $
+* $Module: RGA $ $PublicVersion: 1.03 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+* Description:
+******************************************************************************/
+
+#ifndef  RGA_PORT_H
+#define  RGA_PORT_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "RGA_API_typedef.h"
+#include  "RGA_Port_typedef.h"
+#include  "clib_drivers_typedef.h"  /* "R_CEIL_8U" in "R_RGA_CalcWorkBufferSize" */
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+errnum_t  drawCLUTImage( uint8_t *SrcAddress, const graphics_image_t *image, frame_buffer_t *frame );
+
+
+/***********************************************************************
+* Class: vram_ex_stack_t
+************************************************************************/
+errnum_t  R_VRAM_EX_STACK_Initialize( vram_ex_stack_t *self, void *NullConfig );
+errnum_t  R_VRAM_EX_STACK_Alloc( vram_ex_stack_t *self, frame_buffer_t *in_out_FrameBuffer );
+errnum_t  R_VRAM_EX_STACK_Free( vram_ex_stack_t *self, frame_buffer_t *frame_buffer );
+
+
+/* Section: Global */
+/**
+* @brief   Calculate size of hardware work buffer
+*
+* @param   max_height_of_frame_buffer int
+* @return  size of hardware work buffer
+*/
+#ifdef  RGAH_VERSION
+
+#define  R_RGA_CalcWorkBufferSize( max_height_of_frame_buffer ) \
+	( (size_t)( RGA_WORK_BUFFER_MAX_DISPLAY_LIST + \
+		RGA_WORK_BUFFER_STRIDE * R_CEIL_8U( max_height_of_frame_buffer ) * 4 * 2 ) )
+R_STATIC_ASSERT_GLOBAL( RGA_WORK_BUFFER_HEIGHT_ALIGNMENT == 8, "" );  /* check of R_CEIL_8U */
+
+#endif
+
+
+/**
+* @brief   Calculate size of hardware work buffer
+*
+* @param   max_width_of_frame_buffer int
+* @param   max_height_of_frame_buffer int
+* @return  size of hardware work buffer
+*/
+#ifdef  RGAH_VERSION
+
+#define  R_RGA_CalcWorkBufferSize2( max_width_of_frame_buffer, max_height_of_frame_buffer ) \
+	R_RGA_CalcWorkBufferSize( max_height_of_frame_buffer )
+#else
+
+#define  R_RGA_CalcWorkBufferSize2( max_width_of_frame_buffer, max_height_of_frame_buffer ) \
+	( (size_t)( (max_width_of_frame_buffer) * RGA_WORK_BUFFER_DMAC_LM_WIDTH_BYTE + \
+		(max_height_of_frame_buffer) * RGA_WORK_BUFFER_DMAC_LM_HEIGHT_BYTE ) )
+#endif
+
+
+/**
+* @brief   Calculate size of hardware work buffer B
+*
+* @param   MaxWidthOfJPEG int
+* @param   MaxHeightOfJPEG int
+* @param   MaxBytePerPixelOfFrameBuffer int
+* @return  size of hardware work buffer B
+*/
+#define  R_RGA_CalcWorkBufferB_Size( MaxWidthOfJPEG, MaxHeightOfJPEG, MaxBytePerPixelOfFrameBuffer ) \
+	( R_CEIL_16U( MaxWidthOfJPEG ) * R_CEIL_16U( MaxHeightOfJPEG ) * (MaxBytePerPixelOfFrameBuffer) )
+R_STATIC_ASSERT_GLOBAL( RGA_JPEG_MAX_WIDTH_ALIGNMENT  == 16, "" );  /* check of R_CEIL_16U */
+R_STATIC_ASSERT_GLOBAL( RGA_JPEG_MAX_HEIGHT_ALIGNMENT == 16, "" );  /* check of R_CEIL_16U */
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+/* Inline Functions */
+#include  "RGA_Port_inline.h"
+
+#endif  /* RGA_PORT_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/RGA_Port_inline.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,446 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: RGA_Port_inline.h $
+* $Module: RGA $ $PublicVersion: 1.03 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+* Description:
+******************************************************************************/
+
+
+/* This file is included from "RGA_Port.h" */
+
+
+#ifndef  RGA_PORT_INLINE_H
+#define  RGA_PORT_INLINE_H
+#ifndef  NOT_DEFINE_INLINE_FUNCTION
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "clib_drivers.h"
+#include  "frame_buffer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/**
+* @brief   SwapEndian to 2Byte
+*
+* @param   in_out_2byteVariable Address to 2 byte
+* @return  None
+*/
+INLINE void  SwapEndian2Byte( void *in_out_2byteVariable )
+{
+    byte_t   buffer[2];
+    byte_t  *data = (byte_t *) in_out_2byteVariable;
+
+    buffer[0] = data[0];
+    buffer[1] = data[1];
+
+    data[0] = buffer[1];
+    data[1] = buffer[0];
+}
+
+
+/**
+* @brief   SwapEndian to 4Byte
+*
+* @param   in_out_2byteVariable Address to 4 byte
+* @return  None
+*/
+INLINE void  SwapEndian4Byte( void *in_out_4byteVariable )
+{
+    byte_t   buffer[4];
+    byte_t  *data = (byte_t *) in_out_4byteVariable;
+
+    buffer[0] = data[0];
+    buffer[1] = data[1];
+    buffer[2] = data[2];
+    buffer[3] = data[3];
+
+    data[0] = buffer[3];
+    data[1] = buffer[2];
+    data[2] = buffer[1];
+    data[3] = buffer[0];
+}
+
+
+/**
+* @brief   Sets the value to the address not aligned 4byte
+*
+* @param   out_Variable <uint32_not_aligned_t>
+* @param   Value Set value
+* @return  None
+*/
+INLINE void  uint32_not_aligned_t_set( uint32_not_aligned_t *out_Variable,  uint32_t Value )
+{
+#if BYTE_ENDIAN == BYTE_LITTLE_ENDIAN
+    out_Variable->byte[0] = (byte_t)( ( Value & 0x000000FF ) );
+    out_Variable->byte[1] = (byte_t)( ( Value & 0x0000FF00 ) >>  8 );
+    out_Variable->byte[2] = (byte_t)( ( Value & 0x00FF0000 ) >> 16 );
+    out_Variable->byte[3] = (byte_t)( ( Value & 0xFF000000 ) >> 24 );
+#else
+    out_Variable->byte[0] = (byte_t)( ( Value & 0xFF000000 ) >> 24 );
+    out_Variable->byte[1] = (byte_t)( ( Value & 0x00FF0000 ) >> 16 );
+    out_Variable->byte[2] = (byte_t)( ( Value & 0x0000FF00 ) >>  8 );
+    out_Variable->byte[3] = (byte_t)( ( Value & 0x000000FF ) );
+#endif
+}
+
+
+/***********************************************************************
+* Class: byte_per_pixel_t
+************************************************************************/
+
+
+/**
+* @brief   R_RGA_BitPerPixelType_To_BytePerPixelType
+*
+* @param   BitPerPixel Input
+* @return  byte_per_pixel_t
+*/
+INLINE byte_per_pixel_t  R_RGA_BitPerPixelType_To_BytePerPixelType( int_fast32_t BitPerPixel )
+{
+    if ( R_Mod_8s( BitPerPixel ) == 0 )  {
+        return  (byte_per_pixel_t)( (uint_fast32_t) BitPerPixel / 8 );
+    } else                                 {
+        return  BitPerPixel << R_BYTE_PER_PIXEL_SHIFT;
+    }
+}
+
+
+/**
+* @brief   R_RGA_BytePerPixelType_To_BitPerPixelType
+*
+* @param   BytePerPixel byte_per_pixel_t
+* @return  BitPerPixel
+*/
+INLINE int_fast32_t  R_RGA_BytePerPixelType_To_BitPerPixelType( byte_per_pixel_t  BytePerPixel )
+{
+    return  ( ( BytePerPixel & R_BYTE_PER_PIXEL_MASK ) * 8 ) |
+            ( BytePerPixel >> R_BYTE_PER_PIXEL_SHIFT );
+}
+
+
+/**
+* @brief   R_BYTE_PER_PIXEL_IsInteger
+*
+* @param   BytePerPixel byte_per_pixel_t
+* @return  Whether "BytePerPixel" is integer type.
+*/
+INLINE bool_t  R_BYTE_PER_PIXEL_IsInteger( byte_per_pixel_t BytePerPixel )
+{
+    return  ( BytePerPixel & R_BYTE_PER_PIXEL_MASK ) != 0;
+}
+
+
+/* Section: Global */
+/**
+* @brief   argb8888_t_to_rgb565_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  rgb565_t  argb8888_t_to_rgb565_t( argb8888_t Color )
+{
+    rgb565_t  ret = {0};
+    /* Warning: C4017W: ret may be used before being set */
+    /* This warning is not correct */
+
+    ret.Value = (uint16_t)(
+                    ( ( Color.Value & 0x00F80000 ) >> 8 ) |
+                    ( ( Color.Value & 0x0000FC00 ) >> 5 ) |
+                    ( ( Color.Value & 0x000000F8 ) >> 3 ) );
+
+    return  ret;
+}
+
+
+/**
+* @brief   argb8888_t_to_argb1555_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb1555_t  argb8888_t_to_argb1555_t( argb8888_t Color )
+{
+    argb1555_t  ret = {0};
+    /* Warning: C4017W: ret may be used before being set */
+    /* This warning is not correct */
+
+    ret.Value = (uint16_t)(
+                    ( ( Color.Value & 0x80000000 ) >> 16 ) |  /* A */
+                    ( ( Color.Value & 0x00F80000 ) >>  9 ) |  /* R */
+                    ( ( Color.Value & 0x0000F800 ) >>  6 ) |  /* G */
+                    ( ( Color.Value & 0x000000F8 ) >>  3 ) ); /* B */
+
+    return  ret;
+}
+
+
+/**
+* @brief   argb8888_t_to_argb4444_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb4444_t  argb8888_t_to_argb4444_t( argb8888_t Color )
+{
+    argb4444_t  ret = {0};
+    /* Warning: C4017W: ret may be used before being set */
+    /* This warning is not correct */
+
+    ret.Value = (uint16_t)(
+                    ( ( Color.Value & 0xF0000000 ) >> 16 ) |
+                    ( ( Color.Value & 0x00F00000 ) >> 12 ) |
+                    ( ( Color.Value & 0x0000F000 ) >>  8 ) |
+                    ( ( Color.Value & 0x000000F0 ) >>  4 ) );
+
+    return  ret;
+}
+
+
+/**
+* @brief   argb8888_t_to_r8g8b8a8_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  r8g8b8a8_t  argb8888_t_to_r8g8b8a8_t( argb8888_t Color )
+{
+    r8g8b8a8_t  ret;
+    ret.Value = 0;  /* Avoid Warning: C4017W: ret may be used before being set */
+
+    ret.u.Red   = Color.u.Red;
+    ret.u.Green = Color.u.Green;
+    ret.u.Blue  = Color.u.Blue;
+    ret.u.Alpha = Color.u.Alpha;
+
+    return  ret;
+}
+
+
+/**
+* @brief   rgb565_t_to_argb8888_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb8888_t  rgb565_t_to_argb8888_t( rgb565_t Color )
+{
+    argb8888_t  ret;
+
+    ret.Value = 0xFF000000 | /* A */
+                ( ( Color.Value & 0xF800 ) << 8 ) | ( ( Color.Value & 0xE000 ) << 3 ) |  /* R */
+                ( ( Color.Value & 0x07E0 ) << 5 ) | ( ( Color.Value & 0x0600 ) >> 1 ) |  /* G */
+                ( ( Color.Value & 0x001F ) << 3 ) | ( ( Color.Value & 0x001C ) >> 2 );   /* B */
+
+    return  ret;
+}
+
+
+/**
+* @brief   argb1555_t_to_argb8888_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb8888_t  argb1555_t_to_argb8888_t( argb1555_t Color )
+{
+    argb8888_t  ret;
+
+    ret.Value =
+        ( ( Color.Value & 0x7C00 ) << 9 ) | ( ( Color.Value & 0x7000 ) << 4 ) |  /* R */
+        ( ( Color.Value & 0x03E0 ) << 6 ) | ( ( Color.Value & 0x0380 ) << 1 ) |  /* G */
+        ( ( Color.Value & 0x001F ) << 3 ) | ( ( Color.Value & 0x001C ) >> 2 );   /* B */
+
+    if ( Color.u.Alpha ) {
+        ret.Value |= 0xFF000000;    /* A */
+    }
+
+    return  ret;
+}
+
+
+/**
+* @brief   argb4444_t_to_argb8888_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb8888_t  argb4444_t_to_argb8888_t( argb4444_t Color )
+{
+    argb8888_t  ret;
+
+    ret.Value =
+        ( ( Color.Value & 0xF000 ) << 16 ) | ( ( Color.Value & 0xF000 ) << 12 ) |  /* A */
+        ( ( Color.Value & 0x0F00 ) << 12 ) | ( ( Color.Value & 0x0F00 ) <<  8 ) |  /* R */
+        ( ( Color.Value & 0x00F0 ) <<  8 ) | ( ( Color.Value & 0x00F0 ) <<  4 ) |  /* G */
+        ( ( Color.Value & 0x000F ) <<  4 ) | ( ( Color.Value & 0x000F )       );   /* B */
+
+    return  ret;
+}
+
+
+/**
+* @brief   rgba8888_t_to_rgb565_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE rgb565_t  rgba8888_t_to_rgb565_t( rgba8888_t Color )
+{
+    rgb565_t  ret;
+
+    ret.Value = (uint16_t) (
+                    ( ( Color.Value & 0xF8000000 ) >> 16 ) |  /* R */
+                    ( ( Color.Value & 0x00FC0000 ) >> 13 ) |  /* G */
+                    ( ( Color.Value & 0x0000F800 ) >> 11 ) ); /* B */
+
+    return  ret;
+}
+
+
+/**
+* @brief   rgba8888_t_to_argb1555_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE argb1555_t  rgba8888_t_to_argb1555_t( rgba8888_t Color )
+{
+    argb1555_t  ret;
+
+    ret.Value = (uint16_t) (
+                    ( ( Color.Value & 0xF8000000 ) >> 17 ) |  /* R */
+                    ( ( Color.Value & 0x00F80000 ) >> 14 ) |  /* G */
+                    ( ( Color.Value & 0x0000F800 ) >> 11 ) |  /* B */
+                    ( ( Color.Value & 0x00000080 ) <<  8 ) ); /* A */
+
+    return  ret;
+}
+
+
+/**
+* @brief   rgba8888_t_to_argb4444_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE argb4444_t  rgba8888_t_to_argb4444_t( rgba8888_t Color )
+{
+    argb4444_t  ret;
+
+    ret.Value = (uint16_t) (
+                    ( ( Color.Value & 0xF0000000 ) >> 20 ) |  /* R */
+                    ( ( Color.Value & 0x00F00000 ) >> 16 ) |  /* G */
+                    ( ( Color.Value & 0x0000F000 ) >> 12 ) |  /* B */
+                    ( ( Color.Value & 0x000000F0 ) <<  8 ) ); /* A */
+
+    return  ret;
+}
+
+
+/**
+* @brief   r8g8b8a8_t_to_argb8888_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE  argb8888_t  r8g8b8a8_t_to_argb8888_t( r8g8b8a8_t Color )
+{
+    argb8888_t  ret;
+
+    ret.Value =
+        ( Color.u.Alpha << 24 ) |
+        ( Color.u.Red   << 16 ) |
+        ( Color.u.Green <<  8 ) |
+        ( Color.u.Blue );
+
+    return  ret;
+}
+
+
+/**
+* @brief   rgba8888_t_to_argb8888_t
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE argb8888_t  rgba8888_t_to_argb8888_t( rgba8888_t Color )
+{
+    argb8888_t  ret;
+
+    ret.Value = (
+                    ( ( Color.Value & 0xFF000000 ) >>  8 ) |  /* R */
+                    ( ( Color.Value & 0x00FF0000 ) >>  8 ) |  /* G */
+                    ( ( Color.Value & 0x0000FF00 ) >>  8 ) |  /* B */
+                    ( ( Color.Value & 0x000000FF ) << 24 ) ); /* A */
+
+    return  ret;
+}
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* NOT_DEFINE_INLINE_FUNCTION */
+#endif  /* RGA_PORT_INLINE_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/RGA_Port_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,193 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Port_typedef.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#ifndef  RGA_PORT_TYPEDEF_H
+#define  RGA_PORT_TYPEDEF_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+#include  "clib_drivers.h"  /* ceil_8 */
+#include  "RGA_Port_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  uint16_not_aligned_t
+* @brief  uint16_not_aligned_t
+*/
+#pragma pack (push,1)
+/* uint16_not_aligned_t* variable raises warning, when it was passed to uint16_t* argument. */
+typedef struct _uint16_not_aligned_t {
+    uint8_t  byte[2];
+} uint16_not_aligned_t;
+#pragma pack (pop)
+
+
+/**
+* @struct  uint32_not_aligned_t
+* @brief  uint32_not_aligned_t
+*/
+#pragma pack (push,1)
+/* uint32_not_aligned_t* variable raises warning, when it was passed to uint32_t* argument. */
+typedef struct _uint32_not_aligned_t {
+    uint8_t  byte[4];
+} uint32_not_aligned_t;
+#pragma pack (pop)
+
+
+/**
+* @struct  BITMAPFILEHEADER
+* @brief  BITMAPFILEHEADER
+*/
+#pragma pack (push,1)
+typedef struct tagBITMAPFILEHEADER {
+    uint16_t  bfType;
+    uint32_t  bfSize;
+    uint16_t  bfReserved1;
+    uint16_t  bfReserved2;
+    uint32_t  bfOffBits;
+} BITMAPFILEHEADER;
+#pragma pack (pop)
+
+
+/**
+* @struct  BITMAPINFOHEADER
+* @brief  BITMAPINFOHEADER
+*/
+#pragma pack (push,1)
+typedef struct tagBITMAPINFOHEADER {
+    uint32_t  biSize;
+    int32_t   biWidth;
+    int32_t   biHeight;
+    uint16_t  biPlanes;
+    uint16_t  biBitCount;
+    uint32_t  biCompression;
+    uint32_t  biSizeImage;
+    int32_t   biXPelsPerMeter;
+    int32_t   biYPelsPerMeter;
+    uint32_t  biClrUsed;
+    uint32_t  biClrImportant;
+} BITMAPINFOHEADER;
+#pragma pack (pop)
+
+
+/**
+* @def  BI_BITFIELDS
+* @brief  BI_BITFIELDS
+*/
+enum { BI_BITFIELDS = 3 };
+
+
+/**
+* @struct  vram_ex_stack_t
+* @brief  vram_ex_stack_t
+*/
+typedef struct _vram_ex_stack_t  vram_ex_stack_t;
+struct _vram_ex_stack_t {
+    uint8_t  *Start;
+    uint8_t  *Over;
+    uint8_t  *StackPointer;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#ifdef  RGAH_VERSION
+#define  RGA_FRAME_BUFFER_ADDRESS_ALIGNMENT   32  /* byte */
+#define  RGA_SOURCE_IMAGE_STRIDE_ALIGNMENT    32  /* byte */
+#define  RGA_DESTINATION_STRIDE_ALIGNMENT     32  /* byte */
+#define  RGA_JPEG_ADDRESS_ALIGNMENT            8  /* byte */
+#define  RGA_JPEG_MAX_WIDTH_ALIGNMENT         16  /* pixel. Max of width_of_MCU */
+#define  RGA_JPEG_MAX_HEIGHT_ALIGNMENT        16  /* pixel. Max of height_of_MCU */
+#define  RGA_VDC5_BUFFER_ADDRESS_ALIGNMENT    64  /* byte */
+#define  RGA_WORK_BUFFER_MAX_DISPLAY_LIST    184  /* Constant value */
+#define  RGA_WORK_BUFFER_STRIDE               64  /* Constant value. This is not width of frame buffer */
+#define  RGA_WORK_BUFFER_ADDRESS_ALIGNMENT    64  /* byte */
+#define  RGA_WORK_BUFFER_HEIGHT_ALIGNMENT      8  /* pixel */
+#define  RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT  32  /* byte */
+/* RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT : RGA_RGAH_initBmp_ForSourceImage( colorBuffer ) */
+#endif
+#ifdef  RGAS_VERSION
+#define  RGA_FRAME_BUFFER_ADDRESS_ALIGNMENT    4  /* byte */
+#define  RGA_SOURCE_IMAGE_STRIDE_ALIGNMENT     4  /* byte */
+#define  RGA_DESTINATION_STRIDE_ALIGNMENT      4  /* byte */
+#define  RGA_JPEG_ADDRESS_ALIGNMENT            4  /* byte */
+#define  RGA_JPEG_MAX_WIDTH_ALIGNMENT         16  /* pixel. Max of width_of_MCU */
+#define  RGA_JPEG_MAX_HEIGHT_ALIGNMENT        16  /* pixel. Max of height_of_MCU */
+#define  RGA_WORK_BUFFER_ADDRESS_ALIGNMENT     4  /* byte */
+#define  RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT   4  /* byte */
+#endif
+#define  RGA_VDC5_BUFFER_ADDRESS_ALIGNMENT    64  /* byte */
+
+#define  RGA_MAX_WORK_SIZE_FOR_LIB_PNG_DEFAULT   0x40000 /* byte */ /* "work_size_for_libPNG" */
+
+#define  RGA_WORK_BUFFER_DMAC_LM_WIDTH_BYTE    4  /* byte */
+#define  RGA_WORK_BUFFER_DMAC_LM_HEIGHT_BYTE  32  /* byte */
+
+/**
+* @def  R_RGA_DEFAULT_CLEAR_COLOR
+* @brief  R_RGA_DEFAULT_CLEAR_COLOR
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_RGA_DEFAULT_CLEAR_COLOR  R_RGA_Get_R8G8B8A8( 255, 255, 255, 255 )
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* in RGA_Port_typedef.h */
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* RGA_PORT_TYPEDEF_H */
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/RGA_raw_image.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,68 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_raw_image.h
+* @brief   $Module: RGA_Image $ $PublicVersion: 0.91 $ (=RGA_IMAGE_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  RGA_RAW_IMAGE_H
+#define  RGA_RAW_IMAGE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "RGA_raw_image_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "RGA_raw_image_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "RGA_raw_image_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "RGA_raw_image_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/RGA_raw_image_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,110 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_raw_image_typedef.h
+* @brief   $Module: RGA_Image $ $PublicVersion: 0.91 $ (=RGA_IMAGE_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  RGA_RAW_IMAGE_TYPEDEF_H
+#define  RGA_RAW_IMAGE_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  graphics_image_t
+* @brief  Raw image format of RGA and ImagePackager.
+*/
+typedef struct st_graphics_image_t  graphics_image_t;
+struct st_graphics_image_t {
+
+    /** flags */
+    uint32_t    flags;
+
+    /** offset_to_image */
+    uint32_t    offset_to_image;
+
+    /** offset_to_alpha */
+    uint32_t    offset_to_alpha;
+
+    /** width */
+    uint16_t    width;
+
+    /** height */
+    uint16_t    height;
+
+    /** type */
+    uint8_t     type;
+
+    /** type2 */
+    uint8_t     type2;
+
+    /** color */
+    uint32_t    color;
+};
+
+enum { /* graphics_image_t::flags */
+    F_T_IMAGE_INF_RAW_MASK    = 0x01,
+    F_T_IMAGE_INF_RAW_ADDRESS = 0x00,  /* T_IMAGE_INF::image and Alpha are pointers */
+    F_T_IMAGE_INF_RAW_OFFSET  = 0x01,  /* T_IMAGE_INF::image and Alpha are offsets */
+
+    F_T_IMAGE_INF_PREMULTIPLIED_ALPHA  = 0x04,  /* Premultiplied alpha */
+
+    F_T_IMAGE_INF_LINE_OFFSET = 0x08,  /* Color member variable is line offset */
+
+    F_T_IMAGE_INF_USED_MASK = 0x0000000F
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "RGA_raw_image.h" */
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/frame_buffer.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,67 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  frame_buffer.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  FRAME_BUFFER_H
+#define  FRAME_BUFFER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "frame_buffer_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/frame_buffer_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,458 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  frame_buffer_typedef.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  FRAME_BUFFER_TYPEDEF_H
+#define  FRAME_BUFFER_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @typedef  byte_per_pixel_t
+* @brief  This can have shift value, if byte per pixel is less than 1
+*/
+typedef int  byte_per_pixel_t;
+#ifdef  IS_WINDOW_SURFACES_EX
+enum {
+    R_BYTE_PER_PIXEL_MASK  = 0xFF,  /*[R_BYTE_PER_PIXEL_MASK]*/
+    R_BYTE_PER_PIXEL_SHIFT = 8      /*[R_BYTE_PER_PIXEL_SHIFT]*/
+};
+#endif
+
+
+/**
+* @typedef  frame_buffer_delegate_t
+* @brief  This is user defined variable. Library does not access it.
+*/
+typedef void  frame_buffer_delegate_t;
+enum { /* int_fast32_t */  frame_buffer_t_max_buffer_count = 3 };
+
+
+/**
+* @enum   pixel_format_t
+* @brief  pixel_format_t
+*
+*    - PIXEL_FORMAT_UNKNOWN - 0,              0x00
+*    - PIXEL_FORMAT_ARGB8888 - 1,              0x01
+*    - PIXEL_FORMAT_RGB565 - 3,              0x03
+*    - PIXEL_FORMAT_ARGB4444 - 5,              0x05
+*    - PIXEL_FORMAT_A8 - 11,              0x0B
+*    - PIXEL_FORMAT_A4 - 14,              0x0E
+*    - PIXEL_FORMAT_A1 - 13,              0x0D
+*    - PIXEL_FORMAT_RGB888 - 15,              0x0F
+*    - PIXEL_FORMAT_R8G8B8A8 - 6 | (1 << 4),   0x16
+*    - PIXEL_FORMAT_XRGB8888 - 0 | (1 << 6),   0x40
+*    - PIXEL_FORMAT_ARGB1555 - 4 | (1 << 6),   0x10002
+*    - PIXEL_FORMAT_YCbCr422 - 2 | (1 << 16),  0x10002
+*    - PIXEL_FORMAT_YUV422 - 2 | (1 << 16),  0x10002
+*    - PIXEL_FORMAT_YUV422_GRAY_SCALE_IS_0x80 - 2 | (1 << 16),  0x10002
+*    - PIXEL_FORMAT_JPEG - 12 | (2 << 8),    0x20C
+*    - PIXEL_FORMAT_PNG - 12 | (3 << 8),    0x30C
+*    - PIXEL_FORMAT_GIF - 12 | (4 << 8),    0x40C
+*    - PIXEL_FORMAT_CLUT1 - 12 | (1 << 12),  0x100C
+*    - PIXEL_FORMAT_CLUT4 - 12 | (4 << 12),  0x400C
+*    - PIXEL_FORMAT_CLUT8 - 12 | (8 << 12)   0x800C
+*/
+enum _pixel_format_t {
+    PIXEL_FORMAT_UNKNOWN  =  0,
+    PIXEL_FORMAT_ARGB8888 =  1,
+    PIXEL_FORMAT_RGB565   =  3,
+    PIXEL_FORMAT_ARGB4444 =  5,
+    PIXEL_FORMAT_A8       = 11,
+    PIXEL_FORMAT_A4       = 14,
+    PIXEL_FORMAT_A1       = 13,
+    PIXEL_FORMAT_RGB888   = 15,
+    PIXEL_FORMAT_R8G8B8A8 =  6 | (1 << 4),
+    PIXEL_FORMAT_XRGB8888 =  0 | (1 << 6),
+    PIXEL_FORMAT_ARGB1555 =  4 | (1 << 6),
+    PIXEL_FORMAT_YCbCr422 =  2 | (1 << 16),
+    PIXEL_FORMAT_YUV422   =  2 | (1 << 16),
+    PIXEL_FORMAT_YUV422_GRAY_SCALE_IS_0x80  = 2 | (1 << 16),
+    PIXEL_FORMAT_JPEG     = 12 | (2 << 8),
+    PIXEL_FORMAT_PNG      = 12 | (3 << 8),
+    PIXEL_FORMAT_GIF      = 12 | (4 << 8),
+    PIXEL_FORMAT_CLUT1    = 12 | (1 << 12),
+    PIXEL_FORMAT_CLUT4    = 12 | (4 << 12),
+    PIXEL_FORMAT_CLUT8    = 12 | (8 << 12)
+};
+typedef enum _pixel_format_t  pixel_format_t;
+
+
+/**
+* @struct  frame_buffer_t
+* @brief  frame_buffer_t
+*/
+typedef struct st_frame_buffer_t  frame_buffer_t;
+struct st_frame_buffer_t {
+
+    /** Cached address, [2] is Reserved */
+    uint8_t          *buffer_address[ frame_buffer_t_max_buffer_count ];
+
+    /** max is 2 */
+    int_fast32_t      buffer_count;
+
+    /** Index of "buffer_address" */
+    int_fast32_t      show_buffer_index;
+
+    /** Index of "buffer_address" */
+    int_fast32_t      draw_buffer_index;
+
+    /** width */
+    int_fast32_t      width;
+
+    /** check Stride and PixelFormat */
+    byte_per_pixel_t  byte_per_pixel;
+
+    /** byte to next bottom line */
+    int_fast32_t      stride;
+
+    /** height */
+    int_fast32_t      height;
+
+    /** pixel_format */
+    pixel_format_t    pixel_format;
+
+    /** delegate */
+    frame_buffer_delegate_t  *delegate;
+};
+
+
+/**
+* @struct  r8g8b8a8_t
+* @brief  One of color type
+*/
+#define  r8g8b8a8_t  r8g8b8a8_t
+typedef union st_r8g8b8a8_t  r8g8b8a8_t;
+union st_r8g8b8a8_t {
+    struct {
+#if  BIT_FIELD_ENDIAN == BIT_FIELD_LITTLE_ENDIAN
+
+        /** u */
+        uint8_t  Red;
+
+        /** u */
+        uint8_t  Green;
+
+        /** u */
+        uint8_t  Blue;
+
+        /** u */
+        uint8_t  Alpha;
+#else
+        uint8_t  Alpha;
+        uint8_t  Blue;
+        uint8_t  Green;
+        uint8_t  Red;
+#endif
+    } u;  /* 1st member "u" can be used by initializer */
+
+    /** Value */
+    uint32_t  Value;  /* This is depend on CPU endian. Use only copy or compare */
+};
+
+
+/**
+* @struct  argb8888_t
+* @brief  One of color type
+*/
+#define        argb8888_t  argb8888_t
+typedef union _ARGB8888Type  argb8888_t;
+union _ARGB8888Type {
+    uint32_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if BYTE_ENDIAN == BYTE_LITTLE_ENDIAN
+
+        /** Blue is Value & 0x000000FF */
+        uint8_t  Blue;
+
+        /** u */
+        uint8_t  Green;
+
+        /** u */
+        uint8_t  Red;
+
+        /** u */
+        uint8_t  Alpha;
+#else
+        uint8_t  Alpha;
+        uint8_t  Red;
+        uint8_t  Green;
+        uint8_t  Blue;   /* Blue is Value & 0x000000FF */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  xrgb8888_t
+* @brief  One of color type
+*/
+#define        xrgb8888_t  xrgb8888_t
+typedef union _XRGB8888Type  xrgb8888_t;
+union _XRGB8888Type {
+    uint32_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if BYTE_ENDIAN == BYTE_LITTLE_ENDIAN
+
+        /** Blue is Value & 0x000000FF */
+        uint8_t  Blue;
+
+        /** u */
+        uint8_t  Green;
+
+        /** u */
+        uint8_t  Red;
+
+        /** u */
+        uint8_t  X;      /* zero */
+#else
+        uint8_t  X;      /* zero */
+        uint8_t  Red;
+        uint8_t  Green;
+        uint8_t  Blue;   /* Blue is Value & 0x000000FF */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  rgb565_t
+* @brief  One of color type
+*/
+#define        rgb565_t  rgb565_t
+typedef union _RGB565Type  rgb565_t;
+union _RGB565Type {
+    uint16_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if  BIT_FIELD_ENDIAN == BIT_FIELD_LITTLE_ENDIAN
+
+        /** Blue is at LSB */
+        unsigned  Blue  : 5;
+
+        /** u */
+        unsigned  Green : 6;
+
+        /** u */
+        unsigned  Red   : 5;
+#else
+        unsigned  Red   : 5;
+        unsigned  Green : 6;
+        unsigned  Blue  : 5;  /* Blue is at LSB */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  argb1555_t
+* @brief  One of color type
+*/
+#define        argb1555_t  argb1555_t
+typedef union _ARGB1555Type  argb1555_t;
+union _ARGB1555Type {
+    uint16_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if  BIT_FIELD_ENDIAN == BIT_FIELD_LITTLE_ENDIAN
+
+        /** Blue is at LSB */
+        unsigned  Blue  : 5;
+
+        /** u */
+        unsigned  Green : 5;
+
+        /** u */
+        unsigned  Red   : 5;
+
+        /** u */
+        unsigned  Alpha : 1;
+#else
+        unsigned  Alpha : 1;
+        unsigned  Red   : 5;
+        unsigned  Green : 5;
+        unsigned  Blue  : 5;  /* Blue is at LSB */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  argb4444_t
+* @brief  One of color type
+*/
+#define        argb4444_t  argb4444_t
+typedef union _ARGB4444Type  argb4444_t;
+union _ARGB4444Type {
+    uint16_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if  BIT_FIELD_ENDIAN == BIT_FIELD_LITTLE_ENDIAN
+
+        /** Blue is at LSB */
+        unsigned  Blue  : 4;
+
+        /** u */
+        unsigned  Green : 4;
+
+        /** u */
+        unsigned  Red   : 4;
+
+        /** u */
+        unsigned  Alpha : 4;
+#else
+        unsigned  Alpha : 4;
+        unsigned  Red   : 4;
+        unsigned  Green : 4;
+        unsigned  Blue  : 4;  /* Blue is at LSB */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  rgba8888_t
+* @brief  One of color type
+*/
+#define        rgba8888_t  rgba8888_t
+typedef union _RGBA8888Type  rgba8888_t;
+union _RGBA8888Type {
+    uint32_t  Value;  /* CPU Endian. Not frame buffer endian */
+    struct {
+#if  BIT_FIELD_ENDIAN == BIT_FIELD_LITTLE_ENDIAN
+
+        /** Alpha is at LSB */
+        unsigned  Alpha : 8;
+
+        /** u */
+        unsigned  Blue  : 8;
+
+        /** u */
+        unsigned  Green : 8;
+
+        /** u */
+        unsigned  Red   : 8;
+#else
+        unsigned  Red   : 8;
+        unsigned  Green : 8;
+        unsigned  Blue  : 8;
+        unsigned  Alpha : 8;  /* Alpha is at LSB */
+#endif
+    } u;
+};
+
+
+/**
+* @struct  y_cb_cr_422_t
+* @brief  Same as <yuv422_t>
+*/
+/**
+* @struct  yuv422_t
+* @brief  One of color type
+*/
+#define          y_cb_cr_422_t  y_cb_cr_422_t
+typedef union st_y_cb_cr_422_t  y_cb_cr_422_t;
+#define          yuv422_t       yuv422_t
+typedef union st_y_cb_cr_422_t  yuv422_t;
+union st_y_cb_cr_422_t {
+    struct {
+        /** U */
+        uint8_t  Cb_01;
+
+        /** u */
+        uint8_t  Y_0;
+
+        /** V */
+        uint8_t  Cr_01;
+
+        /** u */
+        uint8_t  Y_1;
+
+    } u;  /* 1st member "u" can be used by initializer */
+
+    struct {
+        /** uu */
+        uint8_t  U_01;
+
+        /** uu */
+        uint8_t  Y_0;
+
+        /** uu */
+        uint8_t  V_01;
+
+        /** uu */
+        uint8_t  Y_1;
+    } uu;
+
+    uint32_t  Value;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Section: Global */
+/**
+* @enum   E_CATEGORY_PIXEL_FORMAT
+* @brief  E_CATEGORY_PIXEL_FORMAT
+*
+*    - E_NOT_SUPPORTED_PIXEL_FORMAT - E_CATEGORY_PIXEL_FORMAT | 0x01
+*/
+#ifndef  E_CATEGORY_PIXEL_FORMAT
+#define  E_CATEGORY_PIXEL_FORMAT  E_CATEGORY_PIXEL_FORMAT
+enum {   E_CATEGORY_PIXEL_FORMAT = 0x00009400 };
+#endif
+enum { E_NOT_SUPPORTED_PIXEL_FORMAT  = E_CATEGORY_PIXEL_FORMAT | 0x01 }; /* 0x9401 = 37889 */
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "frame_buffer.h" */
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/video_input.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,104 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  video_input.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* - Description: V-Sync porting layer
+*/
+
+#ifndef  VIDEO_INPUT_H
+#define  VIDEO_INPUT_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "video_input_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "video_input_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "video_input_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "video_input_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/**
+* @brief   R_VIDEO_INPUT_InitConst
+*
+* @param   self video_input_t
+* @return  None
+*/
+void  R_VIDEO_INPUT_InitConst( video_input_t *const  self );
+
+
+/**
+* @brief   R_VIDEO_INPUT_Initialize
+*
+* @param   self video_input_t
+* @param   in_out_Config Configuration
+* @return  Error Code. 0=No Error.
+*
+* @par Description
+*    "R_WINDOW_SURFACES_SwapBuffers" must be called after calling this
+*    function for showing video layer.
+*    Set "window_surfaces_config_t::background_mode" = "BACKGROUND_MODE_VIDEO_INTERLACE"
+*/
+errnum_t  R_VIDEO_INPUT_Initialize( video_input_t *const  self,
+                                    video_input_config_t *in_out_Config );
+
+
+/**
+* @brief   R_VIDEO_INPUT_Finalize
+*
+* @param   self video_input_t
+* @param   e Errors that have occurred. No error = 0
+* @return  Error code or e, 0 = successful and input e=0
+*/
+errnum_t  R_VIDEO_INPUT_Finalize( video_input_t *const  self, errnum_t e );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/video_input.hpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,117 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  video_input.hpp
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* - Description: Video Input for mbed style C++ API
+*/
+
+#ifndef  VIDEO_INPUT_HPP
+#define  VIDEO_INPUT_HPP
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+#include  "video_input_typedef.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+class  VideoInputConfig;
+
+
+/***********************************************************************
+* Class: VideoInput
+*    mbed style C++ version of <video_input_t>
+************************************************************************/
+class  VideoInput {
+public:
+	/**
+* @brief   VideoInput
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	VideoInput();
+	~VideoInput();
+
+	/**
+* @brief   initialize
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  initialize( VideoInputConfig& in_out_Config );
+
+	/**
+* @brief   destroy
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	void  destroy();
+
+private:
+	video_input_t*  _self;
+};
+
+
+/***********************************************************************
+* Class: VideoInputConfig
+*    mbed style C++ version of <video_input_config_t>
+************************************************************************/
+class  VideoInputConfig : public video_input_config_t {
+public:
+	/**
+* @brief   VideoInputConfig
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	VideoInputConfig();
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/video_input_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,191 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  video_input_typedef.h
+* @brief   $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+*/
+
+#ifndef  VIDEO_INPUT_TYPEDEF_H
+#define  VIDEO_INPUT_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_vdc5.h"
+#include  "r_vdec.h"
+#include  "frame_buffer_typedef.h"
+#include  "r_ospl_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/***********************************************************************
+* Macros: INTERRUPT_FUNCTION_TYPE
+*    INTERRUPT_FUNCTION_TYPE
+*
+*    : INTERRUPT_FUNCTION_TYPE_OS_RTX  - RTX
+*    : INTERRUPT_FUNCTION_TYPE_OS_LESS - OS less
+************************************************************************/
+#if R_OSPL_IS_PREEMPTION
+#define  INTERRUPT_FUNCTION_TYPE  INTERRUPT_FUNCTION_TYPE_OS_RTX
+#else
+#define  INTERRUPT_FUNCTION_TYPE  INTERRUPT_FUNCTION_TYPE_OS_LESS
+#endif
+#define  INTERRUPT_FUNCTION_TYPE_OS_LESS  0
+#define  INTERRUPT_FUNCTION_TYPE_OS_RTX   1
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   video_input_channel_enum_t
+* @brief  Special integer value
+*
+*    - VIDEO_INPUT_NOT_DISPLAY - 0xFF
+*/
+enum st_video_input_channel_enum_t {
+    VIDEO_INPUT_NOT_DISPLAY = 0xFF
+};
+typedef enum st_video_input_channel_enum_t  video_input_channel_enum_t;
+/* "typedef" must be after "enum". Because GCC_ARM raises an error */
+
+
+/**
+* @struct  video_input_t
+* @brief  video_input_t
+*
+* @par Description
+*    Member variables can not be accessed by user.
+*/
+typedef struct st_video_input_t  video_input_t;
+struct st_video_input_t {
+
+    /*-----------------------------------------------------------*/
+    /* Group: Cannel */
+
+    /** video_input_channel */
+    vdc5_channel_t      video_input_channel;
+
+    /** video_input_select */
+    vdec_adc_vinsel_t   video_input_select;
+
+    /** is_data_control */
+    bool_t              is_data_control;
+
+    /** data_control_ID */
+    vdc5_layer_id_t     data_control_ID;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: Interrupt */
+
+    /** is_vsync_interrupt_registered */
+    bool_t              is_vsync_interrupt_registered[3];
+
+    /** interrupt_for_VDC5 */
+    vdc5_int_t          interrupt_for_VDC5;
+
+    /** interrupt_ID */
+    bsp_int_src_t       interrupt_ID;
+
+    /** interrupt_vector */
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+    bsp_int_cb_t        interrupt_vector;
+#endif
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: Buffer */
+
+    /** frame_buffer */
+    frame_buffer_t      frame_buffer;
+
+    /** captured_buffer_index */
+    int_fast32_t        captured_buffer_index;
+
+    /** captured_count */
+    int_fast32_t        captured_count;
+
+    /** captured_async */
+    r_ospl_async_t     *captured_async;
+};
+
+
+/**
+* @struct  video_input_config_t
+* @brief  Parameters of <R_VIDEO_INPUT_Initialize>
+*/
+typedef struct st_video_input_config_t  video_input_config_t;
+struct st_video_input_config_t {
+
+    /** 0 | VIDEO_INPUT_CONFIG_T_layer_ID | ... */
+    bit_flags_fast32_t  flags;
+
+
+    /** 0=ch0.VIN1, 1=ch1.VIN1, 2=ch0.VIN2, 3=ch1.VIN2 */
+    int_fast32_t        video_input_channel_num;
+
+    /** 0, 1 or VIDEO_INPUT_NOT_DISPLAY */
+    int_fast32_t        display_channel_num;
+
+    /** -1 or VIDEO_INPUT_NOT_DISPLAY */
+    int_fast32_t        display_layer_num;
+
+    /** frame_buffer */
+    frame_buffer_t     *frame_buffer;
+
+    /** captured_async */
+    r_ospl_async_t     *captured_async;
+};
+/* video_input_config_t::flags */
+#define  VIDEO_INPUT_CONFIG_T_VIDEO_INPUT_CHANNEL_NUM  0x0001
+#define  VIDEO_INPUT_CONFIG_T_DISPLAY_CHANNEL_NUM      0x0002
+#define  VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM        0x0004
+#define  VIDEO_INPUT_CONFIG_T_FRAME_BUFFER             0x0008
+#define  VIDEO_INPUT_CONFIG_T_CAPTURED_ASYNC           0x0010
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "video_input.h" */
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/vsync.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,139 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  vsync.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  VSYNC_H
+#define  VSYNC_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_typedefs.h"
+#include  "vsync_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "vsync_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "vsync_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "vsync_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Initialize V-Sync object of specified channel number
+*
+* @param   ChannelNum ChannelNum
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_V_SYNC_Initialize( int_fast32_t const  ChannelNum );
+
+
+/**
+* @brief   R_V_SYNC_Finalize
+*
+* @param   ChannelNum ChannelNum
+* @param   e Errors that have occurred. No error = 0
+* @return  Error code or e, 0 = successful and input e=0
+*/
+errnum_t  R_V_SYNC_Finalize( int_fast32_t const  ChannelNum,  errnum_t e );
+
+
+/**
+* @brief   Wait for V-Sync
+*
+* @param   ChannelNum ChannelNum
+* @param   SwapInterval If 1=60fps Then 2=30fps, 3=20fps
+* @param   Is1VSyncAtMinimum false = It is possible to return soon
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_V_SYNC_Wait( int_fast32_t const  ChannelNum,
+                         int_fast32_t const  SwapInterval,  bool_t const  Is1VSyncAtMinimum );
+
+
+/**
+* @brief   Asynchronous function of <R_V_SYNC_Wait>
+*
+* @param   ChannelNum ChannelNum
+* @param   SwapInterval If 1=60fps Then 2=30fps, 3=20fps
+* @param   Is1VSyncAtMinimum false = It is possible to set event soon
+* @param   Async r_ospl_async_t
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_V_SYNC_WaitStart( int_fast32_t const  ChannelNum,
+                              int_fast32_t const  SwapInterval,  bool_t const  Is1VSyncAtMinimum,
+                              r_ospl_async_t *const  Async );
+
+
+/**
+* @brief   Receive interrupt information.
+*
+* @param   InterruptSource r_ospl_interrupt_t
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_V_SYNC_OnInterrupting( const r_ospl_interrupt_t *const  InterruptSource );
+
+
+/**
+* @brief   Get <r_v_sync_async_status_t>
+*
+* @param   ChannelNum ChannelNum
+* @param   out_Status AsyncStatus
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_V_SYNC_GetAsyncStatus( int_fast32_t const  ChannelNum,
+                                   const r_v_sync_async_status_t **const  out_Status );
+
+
+/* Following functions can not be called from Application. */
+void      R_V_SYNC_EnableInterrupt( int_fast32_t const  ChannelNum );
+bool_t    R_V_SYNC_DisableInterrupt( int_fast32_t const  ChannelNum );
+/* It is not necessary: R_V_SYNC_FinalizeAsync(), R_V_SYNC_OnInterrupted() */
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/vsync_pl.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,140 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  vsync_pl.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+* - Description: V-Sync porting layer
+*/
+
+#ifndef  WINDOW_SURFACES_PL_H
+#define  WINDOW_SURFACES_PL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+#include  "vsync_typedef.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+    /******************************************************************************
+    Typedef definitions
+    ******************************************************************************/
+
+    /******************************************************************************
+    Macro definitions
+    ******************************************************************************/
+
+    /******************************************************************************
+    Variable Externs
+    ******************************************************************************/
+
+    /******************************************************************************
+    Functions Prototypes
+    ******************************************************************************/
+
+
+    /**
+    * @brief   Set default <r_ospl_async_t>
+    *
+    * @param   in_out_Async Async parameters
+    * @param   AsyncType r_ospl_async_type_t
+    * @return  None
+    */
+    void  R_V_SYNC_SetDefaultAsync( r_ospl_async_t *const  in_out_Async,  r_ospl_async_type_t AsyncType );
+
+
+    /**
+    * @brief   Called from <R_V_SYNC_Initialize>
+    *
+    * @param   ChannelNum ChannelNum parameters
+    * @return  Error Code. 0=No Error.
+    */
+    errnum_t  R_V_SYNC_OnInitialize( int_fast32_t const  ChannelNum );
+
+
+    /**
+    * @brief   Called from <R_V_SYNC_Finalize>
+    *
+    * @param   ChannelNum ChannelNum parameters
+    * @return  Error Code. 0=No Error.
+    */
+    errnum_t  R_V_SYNC_OnFinalize( int_fast32_t const  ChannelNum,  errnum_t e );
+
+
+    /**
+    * @brief   Send <r_ospl_caller_t> to porting layer
+    *
+    * @param   ChannelNum ChannelNum parameters
+    * @param   Caller r_ospl_caller_t
+    * @return  Error Code. 0=No Error.
+    */
+    errnum_t  R_V_SYNC_SetInterruptCallbackCaller( int_fast32_t const  ChannelNum,
+            const r_ospl_caller_t *const  Caller );
+
+
+    /**
+    * @brief   Enable interrupt lines
+    *
+    * @param   ChannelNum ChannelNum parameters
+    * @param   Enables <r_v_sync_interrupt_lines_t>. 1=Enable, 0=NotChange
+    * @return  Error Code. 0=No Error.
+    */
+    void   R_V_SYNC_OnEnableInterrupt( int_fast32_t const  ChannelNum,
+                                       r_v_sync_interrupt_lines_t const  Enables );
+
+
+    /**
+    * @brief   Disable interrupt lines
+    *
+    * @param   ChannelNum ChannelNum parameters
+    * @param   Disables <r_v_sync_interrupt_lines_t>. 1=Disable, 0=NotChange
+    * @return  Error Code. 0=No Error.
+    */
+    void      R_V_SYNC_OnDisableInterrupt( int_fast32_t const  ChannelNum,
+                                           r_v_sync_interrupt_lines_t const  Disables );
+
+
+    /**
+    * @brief   Default interrupt callback function
+    *
+    * @param   InterruptSource r_ospl_interrupt_t
+    * @param   Caller r_ospl_caller_t
+    * @return  Error Code. 0=No Error.
+    */
+    errnum_t  R_V_SYNC_OnInterruptDefault( const r_ospl_interrupt_t *const  InterruptSource,
+                                           const r_ospl_caller_t *const  Caller );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/vsync_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,108 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  vsync_typedef.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef  VSYNC_TYPEDEF_H
+#define  VSYNC_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_typedefs.h"
+#include  "r_ospl_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @typedef  r_v_sync_interrupt_line_t
+* @brief  r_v_sync_interrupt_line_t
+*/
+typedef uint_fast32_t  r_v_sync_interrupt_line_t;
+#define  R_V_SYNC_INTERRUPT_LINE_V_LINE  0x00000001u
+
+
+/**
+* @typedef  r_v_sync_interrupt_lines_t
+* @brief  r_v_sync_interrupt_lines_t
+*/
+typedef bit_flags_fast32_t /*<r_v_sync_interrupt_line_t>*/  r_v_sync_interrupt_lines_t;
+
+
+/**
+* @def  R_V_SYNC_INTERRUPT_LINE_ALL
+* @brief  All bits of <r_v_sync_interrupt_lines_t>
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_V_SYNC_INTERRUPT_LINE_ALL  ( R_V_SYNC_INTERRUPT_LINE_V_LINE )
+
+
+/**
+* @typedef  r_v_sync_async_status_t
+* @brief  r_v_sync_async_status_t
+*/
+typedef struct st_r_ospl_async_status_t  r_v_sync_async_status_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  R_V_SYNC_CHANNEL_COUNT
+* @brief  VDC5 channel count
+* @par Parameters
+*    None
+* @return  None.
+*/
+enum { R_V_SYNC_CHANNEL_COUNT = 2 };
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "vsync.h" */
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/window_surfaces.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,186 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: window_surfaces.h $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* Description: Sample API
+*******************************************************************************/
+
+#ifndef  WINDOW_SURFACES_H
+#define  WINDOW_SURFACES_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "clib_drivers_typedef.h"
+#include  "window_surfaces_typedef.h"
+#include  "r_multi_compiler_typedef.h"
+#include  "window_surfaces_inline.h"
+#ifdef  IS_WINDOW_SURFACES_EX
+#include  "window_surfaces_ex.h"
+#include  "RGA_API_typedef.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   R_WINDOW_SURFACES_InitConst
+*
+* @param   self window_surfaces_t
+* @return  None
+*/
+void      R_WINDOW_SURFACES_InitConst( window_surfaces_t *const  self );
+
+
+/**
+* @brief   R_WINDOW_SURFACES_Initialize
+*
+* @param   self window_surfaces_t
+* @param   in_out_config window_surfaces_config_t
+* @return  Error code, 0=No error
+*/
+errnum_t  R_WINDOW_SURFACES_Initialize( window_surfaces_t *const  self,
+                                        window_surfaces_config_t *in_out_config );
+
+
+/**
+* @brief   R_WINDOW_SURFACES_Finalize
+*
+* @param   self window_surfaces_t
+* @param   e Errors that have occurred. No error = 0
+* @return  Error code or e, 0 = successful and input e=0
+*/
+errnum_t  R_WINDOW_SURFACES_Finalize( window_surfaces_t *const  self, errnum_t e );
+
+
+/**
+* @brief   Get <frame_buffer_t>* of specified layer number
+*
+* @param   self window_surfaces_t
+* @param   layer_num layer_num
+* @param   out_frame_buffer out_frame_buffer
+* @return  Error code, 0=No error
+*/
+errnum_t  R_WINDOW_SURFACES_GetLayerFrameBuffer( const window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  frame_buffer_t **const  out_frame_buffer );
+
+
+/**
+* @brief   R_WINDOW_SURFACES_SwapBuffers
+*
+* @param   self window_surfaces_t
+* @param   layer_num layer_num
+* @param   context Graphics context or NULL
+* @return  Error code, 0=No error
+*/
+#ifdef  IS_WINDOW_SURFACES_EX
+errnum_t  R_WINDOW_SURFACES_SwapBuffers( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  graphics_t *const  context );
+#else
+errnum_t  R_WINDOW_SURFACES_SwapBuffers( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  const void *const  null_context );
+#endif
+
+
+/**
+* @brief   Asynchronous function of <R_WINDOW_SURFACES_SwapBuffers>
+*
+* @param   self window_surfaces_t
+* @param   layer_num layer_num
+* @param   async r_ospl_async_t
+* @return  Error code, 0=No error
+*/
+errnum_t  R_WINDOW_SURFACES_SwapBuffersStart( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  r_ospl_async_t *async );
+
+
+/**
+* @brief   Wait for V-Sync
+*
+* @param   swap_interval If 1=60fps Then 2=30fps, 3=20fps
+* @param   is_1_v_sync_at_minimum false = It is possible to return soon
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_WINDOW_SURFACES_WaitForVSync( window_surfaces_t *const  self,
+        int_fast32_t const  swap_interval,  bool_t const  is_1_v_sync_at_minimum );
+
+
+/**
+* @brief   Allocate offscreen from stack
+*
+* @param   self window_surfaces_t
+* @param   in_out_frame_buffer frame_buffer_t
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - (input) - >stride, ->height, ->buffer_count
+*    - (output) - >buffer_address[(all)]
+*/
+errnum_t  R_WINDOW_SURFACES_AllocOffscreenStack( window_surfaces_t *const  self,
+        frame_buffer_t *const  in_out_frame_buffer );
+
+
+/**
+* @brief   Free offscreen to stack
+*
+* @param   self window_surfaces_t
+* @param   frame_buffer frame_buffer_t
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - If frame_buffer - >buffer_count == 0, do nothing.
+*/
+errnum_t  R_WINDOW_SURFACES_FreeOffscreenStack( window_surfaces_t *const  self,
+        const frame_buffer_t *const  frame_buffer );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/window_surfaces.hpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,219 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces.hpp
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.20 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* - Description: Window Surfaces for mbed style C++ API
+*/
+
+#ifndef  WINDOW_SURFACES_HPP
+#define  WINDOW_SURFACES_HPP
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+#include  "window_surfaces_typedef.h"
+#include  "RGA.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+class  WindowSurfacesConfigClass;
+#ifdef  IS_WINDOW_SURFACES_EX
+class  GraphicsClass;
+class  LayerAttributes;
+#endif
+
+
+/***********************************************************************
+* Class: WindowSurfacesClass
+*    mbed style C++ version of <window_surfaces_t>
+************************************************************************/
+class  WindowSurfacesClass {
+public:
+	/**
+* @brief   WindowSurfacesClass
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	WindowSurfacesClass();
+	~WindowSurfacesClass();
+
+	/**
+* @brief   initialize
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  initialize( WindowSurfacesConfigClass& in_out_config );
+
+	/**
+* @brief   destroy
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	void  destroy();
+
+	/**
+* @brief   get_layer_frame_buffer
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  get_layer_frame_buffer( int_fast32_t const  layer_num,  frame_buffer_t** const  out_frame_buffer );
+
+	/**
+* @brief   swap_buffers
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	#ifdef  IS_WINDOW_SURFACES_EX
+	errnum_t  swap_buffers( int_fast32_t const  layer_num,  Canvas2D_ContextClass&  context );
+	#else
+	errnum_t  swap_buffers( int_fast32_t const  layer_num,  const void* const  null_context );
+	#endif
+
+	/**
+* @brief   swap_buffers_start
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  swap_buffers_start( int_fast32_t const  layer_num,  r_ospl_async_t* async );
+
+	/**
+* @brief   wait_for_v_sync
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  wait_for_v_sync( int_fast32_t const  swap_interval,  bool_t const  is_1_v_sync_at_minimum );
+
+	/**
+* @brief   alloc_offscreen_stack
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  alloc_offscreen_stack( frame_buffer_t* const  in_out_frame_buffer );
+
+	/**
+* @brief   free_offscreen_stack
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  free_offscreen_stack( const frame_buffer_t* const  frame_buffer );
+
+#ifdef  IS_WINDOW_SURFACES_EX
+	/**
+* @brief   do_message_loop
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  do_message_loop();
+
+	/**
+* @brief   access_layer_attributes
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	errnum_t  access_layer_attributes( LayerAttributes& in_out_Attributes );
+#endif
+
+private:
+	window_surfaces_t*  _self;
+};
+
+
+/***********************************************************************
+* Class: WindowSurfacesConfigClass
+*    mbed style C++ version of <window_surfaces_config_t>
+************************************************************************/
+class  WindowSurfacesConfigClass : public window_surfaces_config_t {
+public:
+	/**
+* @brief   WindowSurfacesConfigClass
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	WindowSurfacesConfigClass();
+};
+
+
+/***********************************************************************
+* Class: LayerAttributes
+*    mbed style C++ version of <layer_attributes_t>
+************************************************************************/
+#ifdef  IS_WINDOW_SURFACES_EX
+class  LayerAttributes : public layer_attributes_t {
+public:
+	/**
+* @brief   LayerAttributes
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+	LayerAttributes();
+};
+#endif
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#endif  /* WINDOW_SURFACES_HPP */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/window_surfaces_ex.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,134 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces_ex.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+*/
+#ifndef  WINDOW_SURFACES_EX_H
+#define  WINDOW_SURFACES_EX_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "window_surfaces_ex_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "frame_buffer_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/***********************************************************************
+* Class: window_surfaces_t
+*    Extra methods of <window_surfaces_t>
+************************************************************************/
+
+/**
+* @brief   Emulate message loop function.
+*
+* @param   self window_surfaces_t
+* @return  Error code, 0=No error
+*/
+errnum_t  R_WINDOW_SURFACES_DoMessageLoop( window_surfaces_t *self );
+
+
+/**
+* @brief   Set or get by <layer_attributes_t>
+*
+* @param   self window_surfaces_t
+* @param   in_out_Attributes <layer_attributes_t>
+* @return  Error code, 0=No error
+*/
+errnum_t  R_WINDOW_SURFACES_AccessLayerAttributes( window_surfaces_t *self,
+        layer_attributes_t *in_out_Attributes );
+
+
+/***********************************************************************
+* Class: vram_ex_stack_t
+*    VRAM stack in external RAM
+************************************************************************/
+
+/**
+* @brief   R_VRAM_EX_STACK_Initialize
+*
+* @param   self vram_ex_stack_t
+* @param   NullConfig NULL
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_VRAM_EX_STACK_Initialize( vram_ex_stack_t *self, void *NullConfig );
+
+
+/**
+* @brief   Allocate VRAM from external RAM
+*
+* @param   self vram_ex_stack_t
+* @param   in_out_FrameBuffer frame_buffer_t
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - (input) - >stride, ->height, ->buffer_count
+*    - (output) - >buffer_address[(all)]
+*/
+errnum_t  R_VRAM_EX_STACK_Alloc( vram_ex_stack_t *self, frame_buffer_t *in_out_FrameBuffer );
+
+
+/**
+* @brief   Free VRAM to external RAM
+*
+* @param   self vram_ex_stack_t
+* @param   frame_buffer frame_buffer_t
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - If frame_buffer - >buffer_count == 0, do nothing.
+*/
+errnum_t  R_VRAM_EX_STACK_Free( vram_ex_stack_t *self, frame_buffer_t *frame_buffer );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/window_surfaces_ex_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,190 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces_ex_typedef.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+*/
+
+#ifndef  WINDOW_SURFACES_EX_TYPEDEF_H
+#define  WINDOW_SURFACES_EX_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/**
+* @struct  window_surfaces_attribute_t
+* @brief  Type of <window_surfaces_t>::attributes.
+*/
+typedef  struct st_window_surfaces_attribute_t  window_surfaces_attribute_t;
+struct st_window_surfaces_attribute_t {
+
+    /** X */
+    int_fast32_t  X;
+
+    /** Y */
+    int_fast32_t  Y;
+
+    /** Width */
+    int_fast32_t  Width;
+
+    /** Height */
+    int_fast32_t  Height;
+
+    /** OffsetX */
+    int_fast32_t  OffsetX;
+
+    /** OffsetY */
+    int_fast32_t  OffsetY;
+
+    /** OffsetByte */
+    int_fast32_t  OffsetByte;
+};
+
+
+/* Section: Global */
+/**
+* @enum   access_t
+* @brief  access_t
+*    - ACCESS_READ - 1
+*    - ACCESS_WRITE - 2
+*    - ACCESS_READ_WRITE - 3
+*    - ACCESS_PLUS - 4
+*/
+enum st_access_t {
+    ACCESS_READ  = 1,
+    ACCESS_WRITE = 2,
+    ACCESS_READ_WRITE = ( 1 | 2 ),
+    ACCESS_PLUS  = 4,
+
+    ACCESS_ALL_MASK = ACCESS_READ | ACCESS_WRITE | ACCESS_READ_WRITE | ACCESS_PLUS
+};
+typedef  enum st_access_t  access_t;
+
+
+/**
+* @struct  layer_attributes_t
+* @brief  Parameters of <R_WINDOW_SURFACES_AccessLayerAttributes>.
+*/
+typedef  struct st_layer_attributes_t  layer_attributes_t;
+struct st_layer_attributes_t {
+
+    /** access */
+    access_t      access;
+
+    /** 0 | F_LAYER_IS_SHOW | ... */
+    bit_flags_fast32_t  flags;
+
+    /** id */
+    int_fast32_t  id;
+
+    /** priority */
+    int_fast32_t  priority;
+
+    /** is_show */
+    bool_t        is_show;
+
+    /** is_color_key */
+    bool_t        is_color_key;
+
+    /** color_key */
+    r8g8b8a8_t    color_key;
+
+    /** layer_color */
+    r8g8b8a8_t    layer_color;
+
+    /** x */
+    int_fast32_t  x;
+
+    /** y */
+    int_fast32_t  y;
+
+    /** width */
+    int_fast32_t  width;
+
+    /** height */
+    int_fast32_t  height;
+
+    /** offset_x */
+    int_fast32_t  offset_x;
+
+    /** offset_y */
+    int_fast32_t  offset_y;
+
+    /** CLUT (Color Look Up Table) */
+    uint32_t     *CLUT;
+
+    /** CLUT (Color Look Up Table) count */
+    int_fast32_t  CLUT_count;
+};
+
+enum {
+    F_LAYER_ID           = 0x0001,
+    F_LAYER_PRIORITY     = 0x0002,
+    F_LAYER_IS_SHOW      = 0x0004,
+    F_LAYER_IS_COLOR_KEY = 0x0008,
+    F_LAYER_COLOR_KEY    = 0x0010,
+    F_LAYER_LAYER_COLOR  = 0x0020,
+    F_LAYER_X            = 0x0040,
+    F_LAYER_Y            = 0x0080,
+    F_LAYER_WIDTH        = 0x0100,
+    F_LAYER_HEIGHT       = 0x0200,
+    F_LAYER_OFFSET_X     = 0x0400,
+    F_LAYER_OFFSET_Y     = 0x0800,
+    F_LAYER_CLUT         = 0x1000,
+    F_LAYER_CLUT_COUNT   = 0x2000
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "window_surfaces_ex.h" */
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/window_surfaces_inline.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,102 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces_inline.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+*/
+
+
+/* This file is included from "window_surfaces.h" */
+
+
+#ifndef  WINDOW_SURFACES_INLINE_H
+#define  WINDOW_SURFACES_INLINE_H
+#ifndef  NOT_DEFINE_INLINE_FUNCTION
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  <stdint.h>
+#include  "clib_drivers_typedef.h"
+#include  "frame_buffer_typedef.h"
+#include  "r_multi_compiler_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/**
+* @brief   Get color
+*
+* @param   Red Red.
+* @param   Green Green.
+* @param   Blue Blue.
+* @param   Alpha Alpha.
+* @return  Color code as "r8g8b8a8_t"
+*/
+INLINE r8g8b8a8_t  R_RGA_Get_R8G8B8A8( int_fast32_t const  Red,
+                                       int_fast32_t const  Green,
+                                       int_fast32_t const  Blue,
+                                       int_fast32_t const  Alpha )
+{
+    r8g8b8a8_t  color_;  /* _ is for MISRA 5.6 */
+
+    /* ->QAC 3198 */
+    color_.Value = DUMMY_INITIAL_VALUE;  /* for avoid ARMCC warning C4017W */
+    /* <-QAC 3198 */
+    color_.u.Red   = (uint8_t) Red;
+    color_.u.Green = (uint8_t) Green;
+    color_.u.Blue  = (uint8_t) Blue;
+    color_.u.Alpha = (uint8_t) Alpha;
+
+    return  color_;
+}
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* NOT_DEFINE_INLINE_FUNCTION */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/window_surfaces_private.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,71 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: window_surfaces_private.h $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* Description  : Sample API
+*******************************************************************************/
+
+#ifndef  WINDOW_SURFACES_PRIVATE_H
+#define  WINDOW_SURFACES_PRIVATE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "RGA_Port_typedef.h"
+#include  "r_ospl_typedef.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define  RGA_STACK_ADDRESS_ALIGNMENT  64
+R_STATIC_ASSERT_GLOBAL( RGA_STACK_ADDRESS_ALIGNMENT >= RGA_SOURCE_IMAGE_STRIDE_ALIGNMENT, "" );
+R_STATIC_ASSERT_GLOBAL( RGA_STACK_ADDRESS_ALIGNMENT >= RGA_VDC5_BUFFER_ADDRESS_ALIGNMENT, "" );
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+errnum_t  R_EXRAM_GetBigMemory( void * /*<type**>*/ out_Address, size_t *out_Size );
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* WINDOW_SURFACES_PRIVATE_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/inc/window_surfaces_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,229 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces_typedef.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+*/
+
+#ifndef  WINDOW_SURFACES_TYPEDEF_H
+#define  WINDOW_SURFACES_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_vdc5.h"
+#include  "frame_buffer_typedef.h"
+#include  "RGA_Port_typedef.h"
+#ifdef  IS_WINDOW_SURFACES_EX
+#include  "window_surfaces_ex_typedef.h"
+#endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   background_format_t
+* @brief  background_format_t
+*
+*    - BACKGROUND_FORMAT_SOLID_COLOR - 0
+*    - BACKGROUND_FORMAT_VIDEO_INTERLACE - 1
+*/
+enum st_background_format_t {
+    BACKGROUND_FORMAT_SOLID_COLOR,
+    BACKGROUND_FORMAT_VIDEO_INTERLACE
+};
+typedef enum st_background_format_t  background_format_t;
+/* "typedef" must be after "enum". Because GCC_ARM raises an error */
+
+
+/**
+* @struct  window_surfaces_vdc5_layer_t
+* @brief  VDC5 layer
+*/
+typedef struct st_window_surfaces_vdc5_layer_t  window_surfaces_vdc5_layer_t;
+struct st_window_surfaces_vdc5_layer_t {
+
+    /*-----------------------------------------------------------*/
+    /* Group: Layer */
+
+    /** layer_num */
+    int8_t  layer_num;
+
+    /** graphics_layer_ID */
+    vdc5_graphics_type_t  graphics_layer_ID;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: Data Control */
+
+    /** is_data_control */
+    bool_t  is_data_control;
+
+    /** data_control_ID */
+    vdc5_layer_id_t  data_control_ID;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: Color Format */
+
+    /** vdc5_format */
+    vdc5_gr_format_t  vdc5_format;
+
+    /** layer_color */
+    r8g8b8a8_t  layer_color;
+};
+
+
+/**
+* @struct  window_surfaces_t
+* @brief  window_surfaces_t
+*/
+typedef struct st_window_surfaces_t  window_surfaces_t;
+#define   WINDOW_SURFACES_T_MAX_LAYERS_COUNT   3
+
+struct st_window_surfaces_t {
+    /** Index is 0 .. (layer_num_max + background_frame_count) */
+    frame_buffer_t  frame_buffers[ WINDOW_SURFACES_T_MAX_LAYERS_COUNT ];
+
+    /** screen_channel */
+    vdc5_channel_t  screen_channel;
+
+    /** layer_num_min */
+    int8_t  layer_num_min;
+
+    /** layer_num_max */
+    int8_t  layer_num_max;
+
+    /** layers */
+    window_surfaces_vdc5_layer_t  layers[ WINDOW_SURFACES_T_MAX_LAYERS_COUNT ];
+
+    /** attributes */
+#ifdef  IS_WINDOW_SURFACES_EX
+    window_surfaces_attribute_t   attributes[ WINDOW_SURFACES_T_MAX_LAYERS_COUNT ];
+#endif
+
+    /** vdc5_disp_sel_array */
+    vdc5_gr_disp_sel_t   vdc5_disp_sel_array[ VDC5_GR_TYPE_NUM ];
+
+    /** background_format */
+    background_format_t  background_format;
+
+    /** background_frame_count */
+    int_fast32_t   background_frame_count;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: VRAM */
+
+    /** start_of_VRAM */
+    uint8_t  *start_of_VRAM;
+
+    /** over_of_VRAM */
+    uint8_t  *over_of_VRAM;
+
+    /** stack_pointer_of_VRAM */
+    uint8_t  *stack_pointer_of_VRAM;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: State */
+
+    /** is_initialized */
+    bool_t  is_initialized;  /* For reduce loading */
+};
+
+
+/**
+* @struct  window_surfaces_config_t
+* @brief  window_surfaces_config_t
+*/
+typedef struct st_window_surfaces_config_t  window_surfaces_config_t;
+struct st_window_surfaces_config_t {
+    /** 0 | F_WINDOW_SURFACES_PIXEL_FORMAT | ... */
+    bit_flags_fast32_t  flags;
+
+    /** pixel_format */
+    pixel_format_t  pixel_format;
+
+    /** layer_count */
+    int_fast32_t  layer_count;
+
+    /** buffer_height */
+    int_fast32_t  buffer_height;
+
+    /** background_color */
+    r8g8b8a8_t  background_color;
+
+    /** background_format */
+    background_format_t  background_format;
+};
+enum  /* "window_surfaces_config_t::flags" */
+{
+    F_WINDOW_SURFACES_PIXEL_FORMAT      = 0x08,
+    F_WINDOW_SURFACES_LAYER_COUNT       = 0x20,
+#define  F_WINDOW_SURFACES_BACKGROUND_COLOR    0x40u
+    F_WINDOW_SURFACES_BUFFER_HEIGHT     = 0x80,
+    F_WINDOW_SURFACES_BACKGROUND_FORMAT = 0x100
+};
+
+
+/***********************************************************************
+* Section: Global
+************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  WINDOW_SURFACES_DEFAULT_CHANNEL
+* @brief  0 or 1
+*/
+#define  WINDOW_SURFACES_DEFAULT_CHANNEL  0
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "frame_buffer.h" */
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
Binary file RGA/GraphicsFramework/RGA/libPNG_Zip.ar has changed
Binary file RGA/GraphicsFramework/RGA/libRGA.ar has changed
Binary file RGA/GraphicsFramework/RGA/libRGAH.ar has changed
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/porting/RGA_Callback.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,260 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Callback.c
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#include  <string.h>
+#include  "RGA.h"
+#include  "RGA_Callback_private.h"
+#include  "clib_drivers.h"
+
+
+
+/** gs_WorkBufferMemory */
+static uint8_t  *gs_WorkBufferMemory;
+static size_t    gs_WorkBufferMemory_Size;
+static uint8_t  *gs_WorkBufferB_Memory;
+static size_t    gs_WorkBufferB_Memory_Size;
+
+
+/**
+* @struct  GraphicsDefaultSubClass
+* @brief  GraphicsDefaultSubClass
+*/
+typedef struct _GraphicsDefaultSubClass  GraphicsDefaultSubClass;
+struct _GraphicsDefaultSubClass {
+    uint8_t  *WorkBufferMemory;
+    size_t    work_buffer_size;
+    bool_t    IsUsedWorkBuffer;
+    uint8_t  *WorkBufferB_Memory;
+    size_t    work_buffer_b_size;
+    bool_t    IsUsedWorkBufferB;
+};
+
+
+/* Section: Global */
+/** gs_GraphicsDefaultSub */
+static  GraphicsDefaultSubClass  gs_GraphicsDefaultSub = {
+    NULL,      /* WorkBufferMemory */
+    0,         /* work_buffer_size */
+    false,     /* IsUsedWorkBuffer */
+    NULL,      /* WorkBufferB_Memory */
+    0,         /* work_buffer_b_size */
+    false,     /* IsUsedWorkBufferB */
+};
+
+
+
+/**
+* @brief   R_GRAPHICS_STATIC_OnInitializeDefault
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t  R_GRAPHICS_STATIC_OnInitializeDefault( graphics_t *self, graphics_config_t *in_out_Config,
+        void **out_CalleeDefined )
+{
+    enum { work_buffer_flags =
+               F_GRAPHICS_WORK_BUFFER_ADDRESS |
+               F_GRAPHICS_WORK_BUFFER_SIZE |
+               F_GRAPHICS_MAX_WIDTH_OF_FRAME_BUFFER |
+               F_GRAPHICS_MAX_HEIGHT_OF_FRAME_BUFFER
+			   //F_GRAPHICS_IS_FAST_MANUAL_FLUSH
+         };
+
+    enum { work_buffer_B_flags =
+               F_GRAPHICS_WORK_BUFFER_B_ADDRESS |
+               F_GRAPHICS_WORK_BUFFER_B_SIZE
+         };
+
+    static r_ospl_c_lock_t  gs_c_lock_object;
+
+    errnum_t  e;
+
+    GraphicsDefaultSubClass  *sub = &gs_GraphicsDefaultSub;
+
+    R_UNREFERENCED_VARIABLE_2( self, out_CalleeDefined );
+
+    R_MEMORY_SECTION_GetMemory_RGA_WorkBuffer( &gs_WorkBufferMemory, &gs_WorkBufferMemory_Size,
+            &gs_WorkBufferB_Memory, &gs_WorkBufferB_Memory_Size );
+
+
+    /* Set default configuration */
+
+    /* Use work buffer */
+    if ( IS_ANY_BITS_NOT_SET( in_out_Config->flags, work_buffer_flags ) ) {
+        ASSERT_R( IS_ALL_BITS_NOT_SET( in_out_Config->flags, work_buffer_flags ),  e=E_OTHERS; goto fin );
+        ASSERT_R( ! sub->IsUsedWorkBuffer,  e=E_OTHERS; goto fin );
+
+#if  RGA_WORK_BUFFER_ADDRESS_ALIGNMENT == 64  /* Check of "R_Ceil_64u" */
+        sub->WorkBufferMemory = (uint8_t *) R_Ceil_64u( (uintptr_t) gs_WorkBufferMemory );
+#elif  RGA_WORK_BUFFER_ADDRESS_ALIGNMENT == 4  /* Check of "R_Ceil_4u" */
+        sub->WorkBufferMemory = (uint8_t *) R_Ceil_4u( (uintptr_t) gs_WorkBufferMemory );
+#else
+#error
+#endif
+        sub->work_buffer_size = gs_WorkBufferMemory_Size - ( sub->WorkBufferMemory - gs_WorkBufferMemory );
+
+        in_out_Config->flags |= work_buffer_flags;
+        in_out_Config->work_buffer_address = sub->WorkBufferMemory;
+        in_out_Config->work_buffer_size    = sub->work_buffer_size;
+        in_out_Config->max_width_of_frame_buffer = MAX_WIDTH_OF_FRAME_BUFFER;
+        in_out_Config->max_height_of_frame_buffer = MAX_HEIGHT_OF_FRAME_BUFFER;
+        //in_out_Config->is_fast_manual_flush = true;
+        sub->IsUsedWorkBuffer = true;
+    }
+
+    /* Use work buffer B */
+    if ( IS_ANY_BITS_NOT_SET( in_out_Config->flags, work_buffer_B_flags ) ) {
+        ASSERT_R( IS_ALL_BITS_NOT_SET( in_out_Config->flags, work_buffer_B_flags ),  e=E_OTHERS; goto fin );
+        ASSERT_R( ! sub->IsUsedWorkBufferB,  e=E_OTHERS; goto fin );
+
+#if  RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT == 32  /* Check of "R_Ceil_32u" */
+        sub->WorkBufferB_Memory = (uint8_t *) R_Ceil_32u( (uintptr_t) gs_WorkBufferB_Memory );
+#elif  RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT == 4  /* Check of "R_Ceil_4u" */
+        sub->WorkBufferB_Memory = (uint8_t *) R_Ceil_4u( (uintptr_t) gs_WorkBufferB_Memory );
+#else
+#error
+#endif
+        sub->work_buffer_b_size = gs_WorkBufferB_Memory_Size - ( sub->WorkBufferB_Memory - gs_WorkBufferB_Memory );
+
+        in_out_Config->flags |= work_buffer_B_flags;
+        in_out_Config->work_buffer_b_address = sub->WorkBufferB_Memory;
+        in_out_Config->work_buffer_b_size    = sub->work_buffer_b_size;
+
+        sub->IsUsedWorkBufferB = true;
+    }
+
+#ifdef  WORK_SIZE_FOR_LIB_PNG
+    in_out_Config->flags |= F_GRAPHICS_WORK_SIZE_FOR_LIBPNG;
+    in_out_Config->work_size_for_libPNG = WORK_SIZE_FOR_LIB_PNG;
+#endif
+
+    R_OSPL_MEMORY_Flush( R_OSPL_FLUSH_WRITEBACK_INVALIDATE );
+    /* Avoid write back by initialization to global variables of buffers */
+
+    /* Lock object */
+    in_out_Config->flags |= F_GRAPHICS_LOCK_OBJECT;
+    in_out_Config->lock_object = &gs_c_lock_object;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+
+/**
+* @brief   R_GRAPHICS_STATIC_OnFinalizeDefault
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t  R_GRAPHICS_STATIC_OnFinalizeDefault( graphics_t *self, void *CalleeDefined, errnum_t e )
+{
+    GraphicsDefaultSubClass  *sub = &gs_GraphicsDefaultSub;
+
+    R_UNREFERENCED_VARIABLE_2( self, CalleeDefined );
+    sub->IsUsedWorkBuffer  = false;
+    sub->IsUsedWorkBufferB = false;
+    return  e;
+}
+
+
+/**
+* @brief   drawCLUTImage
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t drawCLUTImage( uint8_t *SrcAddress, const graphics_image_t *image, frame_buffer_t *frame )
+{
+    errnum_t e;
+    int_t image_w;
+    int i;
+    uint32_t ImageWidthPoint;
+    uint8_t *DestAddress;
+    graphics_image_properties_t  image_prop;
+
+    DestAddress = frame->buffer_address[ frame->draw_buffer_index ];
+
+    switch( frame->pixel_format ) {
+        case PIXEL_FORMAT_CLUT8:
+            ImageWidthPoint = 1;
+            break;
+        case PIXEL_FORMAT_CLUT4:
+            ImageWidthPoint = 2;
+            break;
+        case PIXEL_FORMAT_CLUT1:
+            ImageWidthPoint = 8;
+            break;
+        default:
+            /* never comes here */
+            ImageWidthPoint = 1;
+            break;
+    }
+
+    e = R_GRAPHICS_IMAGE_GetProperties( image, &image_prop );
+    IF(e)goto fin;
+    ASSERT_R( image_prop.pixelFormat == frame->pixel_format , e=E_NOT_SUPPORTED_PIXEL_FORMAT; goto fin );
+    ASSERT_R( ( image->width % ImageWidthPoint ) == 0 , e=E_OTHERS; goto fin );
+    ASSERT_R( image->width <= frame->width , e=E_OTHERS; goto fin );
+    ASSERT_R( image->height <= frame->height , e=E_OTHERS; goto fin );
+    ASSERT_R( frame->stride % 32 == 0 , e=E_OTHERS; goto fin );
+
+    image_w = image_prop.width;
+    switch( frame->pixel_format ) {
+        case PIXEL_FORMAT_CLUT8:
+            SrcAddress += sizeof( uint32_t ) * 256;
+            break;
+        case PIXEL_FORMAT_CLUT4:
+            image_w = image_w / 2;
+            SrcAddress += sizeof( uint32_t ) * 16;
+            break;
+        case PIXEL_FORMAT_CLUT1:
+            image_w = image_w / 8;
+            SrcAddress += sizeof( uint32_t ) * 2;
+            break;
+        default:
+            e=E_OTHERS;
+            goto fin;
+    }
+    for( i = 0; i < image->height ; i++ ) {
+        memcpy(( void *) DestAddress, ( void *)SrcAddress, (size_t)image_w );
+        DestAddress += frame->stride;
+        SrcAddress += image_w;
+    }
+    e = 0;
+fin:
+    return e;
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/porting/RGA_Callback_WorkBuf.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Callback_WorkBuf.c
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#include  <string.h>
+#include  "RGA.h"
+#include  "RGA_Callback_private.h"
+
+
+/** gs_WorkBufferMemory */
+
+/* <MapSection attribute="Uncachable"/> */
+/* .WORK_SECTION1 is for only R_REE_INIT. This is ignored in other environments. */
+R_OSPL_ALIGNMENT( RGA_WORK_BUFFER_ADDRESS_ALIGNMENT,
+                  R_OSPL_SECTION_FOR_ZERO_INIT( "NC_BSS",
+                          static uint8_t  gs_WorkBufferMemory[ WORK_BUFFER_SIZE ] ));
+
+
+/** gs_WorkBufferB_Memory */
+
+R_OSPL_ALIGNMENT( RGA_WORK_BUFFER_B_ADDRESS_ALIGNMENT,
+                  static uint8_t  gs_WorkBufferB_Memory[ WORK_BUFFER_B_SIZE ] );
+
+
+/**
+* @brief   Get Memory of RGA WorkBuffer
+*
+* @param   out_WorkBufferAddress uint8_t*
+* @param   out_WorkBufferSize size_t
+* @param   out_WorkBufferB_Address uint8_t*
+* @param   out_WorkBufferB_Size size_t
+* @return  None
+*/
+void  R_MEMORY_SECTION_GetMemory_RGA_WorkBuffer(
+    uint8_t **out_WorkBufferAddress,  size_t *out_WorkBufferSize,
+    uint8_t **out_WorkBufferB_Address,  size_t *out_WorkBufferB_Size )
+{
+    *out_WorkBufferAddress = gs_WorkBufferMemory;
+    *out_WorkBufferSize = sizeof( gs_WorkBufferMemory );
+    *out_WorkBufferB_Address = gs_WorkBufferB_Memory;
+    *out_WorkBufferB_Size = sizeof( gs_WorkBufferB_Memory );
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/porting/RGA_Callback_private.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,60 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_Callback_private.h
+* @brief   $Module: RGA $ $PublicVersion: 1.20 $ (=RGA_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+#include  "r_typedefs.h"
+#include  "RGA_Port_typedef.h"
+#include  "lcd_panel.h"
+
+#ifdef  RZ_A1L  /* Reduce working buffer size for LibPNG */
+#define  WORK_SIZE_FOR_LIB_PNG   0x10000
+#endif
+
+enum {
+    MAX_WIDTH_OF_FRAME_BUFFER  = LCD_CH0_DISP_HW, //default: 1280,
+    MAX_HEIGHT_OF_FRAME_BUFFER = LCD_CH0_DISP_VW, //default: 800,
+
+    WORK_BUFFER_SIZE = R_RGA_CalcWorkBufferSize2(
+                           MAX_WIDTH_OF_FRAME_BUFFER, MAX_HEIGHT_OF_FRAME_BUFFER ),
+
+#ifdef  WORK_SIZE_FOR_LIB_PNG
+    WORK_BUFFER_B_SIZE = R_RGA_CalcWorkBufferB_Size(
+                             MAX_WIDTH_OF_FRAME_BUFFER, MAX_HEIGHT_OF_FRAME_BUFFER, 4 ) +
+                         WORK_SIZE_FOR_LIB_PNG
+#else
+    WORK_BUFFER_B_SIZE = R_RGA_CalcWorkBufferB_Size(
+                             MAX_WIDTH_OF_FRAME_BUFFER, MAX_HEIGHT_OF_FRAME_BUFFER, 4 ) +
+                         RGA_MAX_WORK_SIZE_FOR_LIB_PNG_DEFAULT
+#endif
+};
+
+void  R_MEMORY_SECTION_GetMemory_RGA_WorkBuffer(
+    uint8_t **out_WorkBufferAddress,  size_t *out_WorkBufferSize,
+    uint8_t **out_WorkBufferB_Address,  size_t *out_WorkBufferB_Size );
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/porting/RGA_VRAM.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,75 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: RGA_VRAM.c $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 40 $
+* $Date:: 2013-12-18 20:02:45 +0900#$
+* Description : Sample functions
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_typedefs.h"
+#include  "r_ospl.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+#if ! IS_VDC_SAMPLE_VRAM_USED
+
+/* <MapSection attribute="Uncached"/> */
+R_OSPL_SECTION_FOR_ZERO_INIT( "VRAM",
+                              static uint8_t gs_FrameBufferMemory[ 0x00300000 ] );
+
+void  R_MEMORY_SECTION_GetMemory_ClibSamplesC( uint8_t **out_Address,  size_t *out_Size )
+{
+    *out_Address = gs_FrameBufferMemory;
+    *out_Size = sizeof( gs_FrameBufferMemory );
+}
+
+#endif
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/porting/RGA_VRAM_EX.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,83 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  RGA_VRAM_EX.c
+* @brief   External VRAM Area
+*
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 51 $
+* $Date:: 2014-03-14 18:42:33 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_typedefs.h"
+#include  "window_surfaces_private.h"
+#include  "r_ospl.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/** gs_VRAM_Ex */
+/* <MapSection attribute="SDRAM_Cached"/> */
+R_OSPL_ALIGNMENT( RGA_STACK_ADDRESS_ALIGNMENT,
+                  R_OSPL_SECTION_FOR_ZERO_INIT( "VRAM_EX",
+                          static uint8_t gs_VRAM_Ex[ 0x00500000 ] ));
+
+
+/**
+* @brief   R_EXRAM_GetBigMemory
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t  R_EXRAM_GetBigMemory( void * /*<type**>*/ out_Address,  size_t *out_Size )
+{
+    *(void **) out_Address = gs_VRAM_Ex;
+    *out_Size = sizeof( gs_VRAM_Ex );
+    return  0;
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/porting/vsync_pl.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,413 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  vsync_pl.c
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 44 $
+* $Date:: 2013-12-20 11:20:00 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "r_ospl.h"
+#include  "r_vdc5.h"
+#include  "vsync.h"
+#include  "vsync_pl.h"
+
+#if ! R_OSPL_IS_PREEMPTION
+#include  "dev_drv.h"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+typedef void (* gs_rtx_interrupt_t )(void);  /* RTX */
+typedef void (* gs_cint_interrupt_t )( uint32_t int_sense );  /* OS less INTC */
+typedef void (* gs_vdc_interrupt_t )( vdc5_int_type_t int_type );
+
+typedef struct st_r_v_sync_pl_channel_t  r_v_sync_pl_channel_t;
+struct st_r_v_sync_pl_channel_t {
+    const r_ospl_caller_t             *InterruptCallbackCaller;
+    bool_t                             IsVDC5_Callback;
+};
+
+static r_v_sync_pl_channel_t  gs_v_sync_pl_channel[ R_V_SYNC_CHANNEL_COUNT ];
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  GS_VSYNC_INTERRUPT_PRIORITY
+* @brief  GS_VSYNC_INTERRUPT_PRIORITY
+* @par Parameters
+*    None
+* @return  None.
+*/
+enum { GS_VSYNC_INTERRUPT_PRIORITY = 7 };
+
+
+/**
+* @def  GS_INTERRUPT_FUNCTION_TYPE
+* @brief  GS_INTERRUPT_FUNCTION_TYPE
+* @par Parameters
+*    None
+* @return  None.
+*
+*    - 0 : RTX
+*    - 1 : INTC
+*/
+#if R_OSPL_IS_PREEMPTION
+#define  GS_INTERRUPT_FUNCTION_TYPE  0
+#else
+#define  GS_INTERRUPT_FUNCTION_TYPE  1
+#endif
+
+
+/**
+* @typedef  gs_interrupt_t
+* @brief  Interrupt callback function type
+*/
+#if  GS_INTERRUPT_FUNCTION_TYPE == 0
+#define  gs_interrupt_t  gs_rtx_interrupt_t
+#else
+#define  gs_interrupt_t  gs_cint_interrupt_t
+#endif
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void  R_V_SYNC_IRQ_HandlerN( int_fast32_t const  ChannelNum );
+static void  R_V_SYNC_IRQ_Handler0( vdc5_int_type_t const  int_type );
+static void  R_V_SYNC_IRQ_Handler1( vdc5_int_type_t const  int_type );
+#if  GS_INTERRUPT_FUNCTION_TYPE != 1
+static gs_cint_interrupt_t  gs_cint_vdc5_interrupt_handler[2];
+static void  R_V_SYNC_IRQ_HandlerRoot0(void);
+static void  R_V_SYNC_IRQ_HandlerRoot1(void);
+#endif
+
+
+/** Table of interrupt line to channel number */
+static const r_ospl_interrupt_t  gs_array_of_i_context[ R_V_SYNC_CHANNEL_COUNT ] = {
+    { BSP_INT_SRC_GR3_VLINE0,  0 },
+    { BSP_INT_SRC_GR3_VLINE1,  1 }
+};
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_SetDefaultAsync
+************************************************************************/
+void  R_V_SYNC_SetDefaultAsync( r_ospl_async_t *const  Async,  r_ospl_async_type_t AsyncType )
+{
+    R_UNREFERENCED_VARIABLE( AsyncType );
+
+    IF_DQ( Async == NULL ) {
+        goto fin;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_A_Thread ) ) {
+        Async->A_Thread = NULL;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_A_EventValue ) ) {
+        Async->A_EventValue = R_OSPL_A_FLAG;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_I_Thread ) ) {
+        Async->I_Thread = NULL;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_I_EventValue ) ) {
+        Async->I_EventValue = R_OSPL_I_FLAG;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_InterruptCallback ) ) {
+        Async->InterruptCallback = (r_ospl_callback_t)&( R_V_SYNC_OnInterruptDefault );
+    }
+    /* MISRA 16.9 */
+
+    Async->Flags = R_F_OSPL_A_Thread | R_F_OSPL_A_EventValue |
+                   R_F_OSPL_I_Thread | R_F_OSPL_I_EventValue |
+                   R_F_OSPL_InterruptCallback | R_F_OSPL_Delegate;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnInitialize
+************************************************************************/
+errnum_t  R_V_SYNC_OnInitialize( int_fast32_t const  ChannelNum )
+{
+#if GS_INTERRUPT_FUNCTION_TYPE == 1
+    bsp_int_cb_t    handler;
+#endif
+    errnum_t       e;
+    vdc5_error_t   er;
+    bsp_int_err_t  eb;
+    bsp_int_src_t  int_id;
+    vdc5_int_t     interrupt;
+    r_v_sync_pl_channel_t *const     self = &gs_v_sync_pl_channel[ ChannelNum ];
+    const r_ospl_interrupt_t *const  i_context = &gs_array_of_i_context[ ChannelNum ];
+
+    /*[gs_IRQHandlers]*/
+    static const gs_vdc_interrupt_t  gs_IRQHandlers[ R_V_SYNC_CHANNEL_COUNT ] = {
+        &( R_V_SYNC_IRQ_Handler0 ), /* MISRA 16.9 */
+        &( R_V_SYNC_IRQ_Handler1 )
+    };
+
+#if  GS_INTERRUPT_FUNCTION_TYPE != 1
+    /*[gs_IRQHandlerRoots]*/
+    static const gs_interrupt_t  gs_IRQHandlerRoots[ R_V_SYNC_CHANNEL_COUNT ] = {
+        &( R_V_SYNC_IRQ_HandlerRoot0 ), /* MISRA 16.9 */
+        &( R_V_SYNC_IRQ_HandlerRoot1 )
+    };
+#endif
+
+
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    self->InterruptCallbackCaller = NULL;
+
+    int_id  = i_context->IRQ_Num;
+#if GS_INTERRUPT_FUNCTION_TYPE == 1
+    handler = R_VDC5_GetISR( (vdc5_channel_t) ChannelNum, VDC5_INT_TYPE_VLINE );
+    eb= R_BSP_InterruptWrite( int_id, handler );
+#else
+    gs_cint_vdc5_interrupt_handler[ChannelNum] = R_VDC5_GetISR(
+                (vdc5_channel_t) ChannelNum, VDC5_INT_TYPE_VLINE );
+    eb= R_BSP_InterruptWrite( int_id, gs_IRQHandlerRoots[ChannelNum] );
+#endif
+    IF ( eb != BSP_INT_SUCCESS ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= R_OSPL_SetInterruptPriority( int_id, GS_VSYNC_INTERRUPT_PRIORITY );
+    IF ( e != 0 ) {
+        goto fin;
+    }
+
+    interrupt.type     = VDC5_INT_TYPE_VLINE;
+    interrupt.callback = gs_IRQHandlers[ ChannelNum ];
+    interrupt.line_num = (uint16_t) 0;
+
+    er = R_VDC5_CallbackISR( (vdc5_channel_t) ChannelNum, &interrupt );
+    IF ( er != VDC5_OK ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    self->IsVDC5_Callback = true;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnFinalize
+************************************************************************/
+errnum_t  R_V_SYNC_OnFinalize( int_fast32_t const  ChannelNum,  errnum_t e )
+{
+    r_v_sync_pl_channel_t *const  self = &gs_v_sync_pl_channel[ ChannelNum ];
+
+    if ( (ChannelNum >= 0) && (ChannelNum < R_V_SYNC_CHANNEL_COUNT) ) {
+        if ( IS( self->IsVDC5_Callback ) ) {
+            vdc5_error_t  er;
+            vdc5_int_t    interrupt;
+
+            interrupt.type     = VDC5_INT_TYPE_VLINE;
+            interrupt.callback = NULL;
+            interrupt.line_num = (uint16_t) 0;
+
+            er = R_VDC5_CallbackISR( (vdc5_channel_t) ChannelNum, &interrupt );
+            IF ( (er != VDC5_OK) && (e == 0) ) {
+                e=E_OTHERS;
+            }
+
+            self->IsVDC5_Callback = false;
+        }
+    }
+
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_SetInterruptCallbackCaller
+************************************************************************/
+errnum_t  R_V_SYNC_SetInterruptCallbackCaller( int_fast32_t const  ChannelNum,
+        const r_ospl_caller_t *const  Caller )
+{
+    r_v_sync_pl_channel_t *const  self = &gs_v_sync_pl_channel[ ChannelNum ];
+
+    self->InterruptCallbackCaller = Caller;
+
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnEnableInterrupt
+************************************************************************/
+void  R_V_SYNC_OnEnableInterrupt( int_fast32_t const  ChannelNum,
+                                  r_v_sync_interrupt_lines_t const  Enables )
+{
+    bsp_int_err_t  eb;
+
+    if ( IS_BIT_SET( Enables, R_V_SYNC_INTERRUPT_LINE_V_LINE ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_array_of_i_context[ ChannelNum ].IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnDisableInterrupt
+************************************************************************/
+void  R_V_SYNC_OnDisableInterrupt( int_fast32_t const  ChannelNum,
+                                   r_v_sync_interrupt_lines_t const  Disables1 )
+{
+    bsp_int_err_t  eb;
+
+    if ( IS_BIT_SET( Disables1, R_V_SYNC_INTERRUPT_LINE_V_LINE ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_array_of_i_context[ ChannelNum ].IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnInterruptDefault
+************************************************************************/
+errnum_t  R_V_SYNC_OnInterruptDefault( const r_ospl_interrupt_t *const  InterruptSource,
+                                       const r_ospl_caller_t *const  Caller )
+{
+    R_UNREFERENCED_VARIABLE( Caller );
+
+    return  R_V_SYNC_OnInterrupting( InterruptSource );
+}
+
+
+/**
+* @brief   Interrupt service routine for all channels
+*
+* @param   ChannelNum ChannelNum
+* @return  None
+*/
+static void  R_V_SYNC_IRQ_HandlerN( int_fast32_t const  ChannelNum )
+{
+    r_v_sync_pl_channel_t *const     self = &gs_v_sync_pl_channel[ ChannelNum ];
+    const r_ospl_interrupt_t *const  i_context = &gs_array_of_i_context[ ChannelNum ];
+
+    /* V-Sync interrupt always be enabled. Because clear interrupt status */
+
+    if ( self->InterruptCallbackCaller != NULL ) {
+        R_OSPL_CallInterruptCallback( self->InterruptCallbackCaller, i_context );
+    }
+}
+
+
+/**
+* @brief   Interrupt service routine for INTC channel 0
+*
+* @param   int_type ignored
+* @return  None
+*/
+static void  R_V_SYNC_IRQ_Handler0( vdc5_int_type_t const  int_type )
+{
+    R_UNREFERENCED_VARIABLE( int_type );
+    R_V_SYNC_IRQ_HandlerN( 0 );
+}
+
+
+/**
+* @brief   Interrupt service routine for INTC channel 1
+*
+* @param   int_type ignored
+* @return  None
+*/
+static void  R_V_SYNC_IRQ_Handler1( vdc5_int_type_t const  int_type )
+{
+    R_UNREFERENCED_VARIABLE( int_type );
+    R_V_SYNC_IRQ_HandlerN( 1 );
+}
+
+
+/**
+* @brief   Interrupt service routine for RTX channel 0
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+#if GS_INTERRUPT_FUNCTION_TYPE != 1
+static void  R_V_SYNC_IRQ_HandlerRoot0(void)
+{
+    gs_cint_vdc5_interrupt_handler[0]( 0 );
+    GIC_EndInterrupt( BSP_INT_SRC_GR3_VLINE0 );
+}
+#endif
+
+
+/**
+* @brief   Interrupt service routine for RTX channel 1
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+#if GS_INTERRUPT_FUNCTION_TYPE != 1
+static void  R_V_SYNC_IRQ_HandlerRoot1(void)
+{
+    gs_cint_vdc5_interrupt_handler[1]( 0 );
+    GIC_EndInterrupt( BSP_INT_SRC_GR3_VLINE0 );
+}
+#endif
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/src/video_input.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,906 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  video_input.c
+* @brief   $Rev: 51 $
+* $Date:: 2014-03-14 18:42:33 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "r_typedefs.h"
+#include  "r_ospl.h"
+#include  "video_input.h"
+#include  "video_decoder.h"
+#include  "window_surfaces_typedef.h"  /* WINDOW_SURFACES_DEFAULT_CHANNEL */
+#ifndef R_OSPL_NDEBUG
+#include  <stdio.h>
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @typedef  video_input_vdc5_layer_t
+* @brief  video_input_vdc5_layer_t
+*/
+typedef struct st_video_input_vdc5_layer_t  video_input_vdc5_layer_t;
+struct st_video_input_vdc5_layer_t {
+    bool_t                is_data_control;
+    vdc5_layer_id_t       data_control_ID;
+};
+
+
+/**
+* @typedef  vdc5_int_cb_t
+* @brief  vdc5_int_cb_t
+*/
+typedef  void (* vdc5_int_cb_t )( const uint32_t );
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define VSYNC_1_2_FH_TIMING  (858u) /* Vsync signal 1/2fH phase timing */
+#define VSYNC_1_4_FH_TIMING  (429u) /* Vsync signal 1/4fH phase timing */
+
+#define     IMGCAP_SIZE_NTSC_HS         (122u * 2u)
+#define     IMGCAP_SIZE_NTSC_HW         (720u * 2u)
+#define     IMGCAP_SIZE_NTSC_VS         (16u)
+#define     IMGCAP_SIZE_NTSC_VW         (480u/2u)
+
+#define     IMGCAP_SIZE_PAL_HS          (132u * 2u)
+#define     IMGCAP_SIZE_PAL_HW          (720u * 2u)
+#define     IMGCAP_SIZE_PAL_VS          (19u)
+#define     IMGCAP_SIZE_PAL_VW          (560u/2u)
+
+#define     VIDEO_FORMAT                (VDC5_RES_MD_YCBCR422)
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static void  R_VIDEO_INPUT_OnVideoInVSync( vdc5_channel_t  video_input_channel,  vdc5_int_type_t int_type );
+static void  R_VIDEO_INPUT_OnVideoInVSync_Ch0( vdc5_int_type_t int_type );
+static void  R_VIDEO_INPUT_OnVideoInVSync_Ch1( vdc5_int_type_t int_type );
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+static void  InterruptCallbackVector_S0_VI_VSYNC0(void);
+static void  InterruptCallbackVector_S0_VI_VSYNC1(void);
+static void  InterruptCallbackVector_S1_VI_VSYNC0(void);
+static void  InterruptCallbackVector_S1_VI_VSYNC1(void);
+vdc5_int_cb_t  gs_VDC5_ISR_S0_VI_VSYNC0;
+vdc5_int_cb_t  gs_VDC5_ISR_S0_VI_VSYNC1;
+vdc5_int_cb_t  gs_VDC5_ISR_S1_VI_VSYNC0;
+vdc5_int_cb_t  gs_VDC5_ISR_S1_VI_VSYNC1;
+#endif
+
+static video_input_t  *gs_InterruptToSelf[ 2 /* video_input_channel */ ][ 2 /* data_control_ID */ ];
+
+static errnum_t  R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t  *in_self );
+static errnum_t  R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t  *in_self );
+static errnum_t  R_VIDEO_INPUT_STATIC_GetSelfPointer(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t ***  out_self_pp );
+static errnum_t  R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_int_type_t  in_interrupt,
+    video_input_t  **out_self );
+
+
+/**
+* @brief   Initializes by constant data.
+*
+* @param   self video_input_t.
+* @return  None.
+*/
+void  R_VIDEO_INPUT_InitConst( video_input_t *const  self )
+{
+    self->is_data_control = false;
+    self->is_vsync_interrupt_registered[0] = false;
+    self->is_vsync_interrupt_registered[1] = false;
+    self->is_vsync_interrupt_registered[2] = false;
+}
+
+
+/***********************************************************************
+* Implement: R_VIDEO_INPUT_Initialize
+************************************************************************/
+errnum_t  R_VIDEO_INPUT_Initialize( video_input_t *const  self,
+                                    video_input_config_t *in_out_Config )
+{
+    errnum_t         e;
+    vdc5_error_t     e_vdc5;
+#ifdef  IS_MBED_USED
+    vdec_error_t     e_vdec;
+#endif
+    vdc5_write_t     writing_config;
+    frame_buffer_t  *frame;
+    uintptr_t        frame_physical_address[ R_COUNT_OF( frame->buffer_address ) ];
+
+
+    /* Initialize by constant */
+    ASSERT_R( ! self->is_data_control,  e=E_STATE; goto fin );
+    ASSERT_R( ! self->is_vsync_interrupt_registered[0],  e=E_STATE; goto fin );
+    ASSERT_R( ! self->is_vsync_interrupt_registered[1],  e=E_STATE; goto fin );
+    ASSERT_R( ! self->is_vsync_interrupt_registered[2],  e=E_STATE; goto fin );
+    self->captured_count = 0;
+
+
+    /* Check necessary flags */
+    {
+        enum { necessary_flags =
+                   VIDEO_INPUT_CONFIG_T_FRAME_BUFFER
+             };
+
+        ASSERT_R( IS_ALL_BITS_SET( in_out_Config->flags, necessary_flags ),
+                  e=E_OTHERS; goto fin );
+    }
+
+
+    /* Set "frame" */
+    {
+        int_fast32_t  i;
+
+        frame = in_out_Config->frame_buffer;
+        ASSERT_R( frame->buffer_count == 2,  e=E_OTHERS; goto fin );
+        self->frame_buffer = *frame;
+
+        for ( i = 0;  i < frame->buffer_count;  i += 1 ) {
+            e= R_OSPL_ToPhysicalAddress( frame->buffer_address[ i ],
+                                         &frame_physical_address[ i ] );
+            IF(e!=0) {
+                goto fin;
+            }
+        }
+    }
+
+
+    /* Set default "in_out_Config->video_input_channel_num" */
+    if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_VIDEO_INPUT_CHANNEL_NUM ) ) {
+        in_out_Config->video_input_channel_num = WINDOW_SURFACES_DEFAULT_CHANNEL;
+    }
+
+
+    /* Set from "in_out_Config->video_input_channel_num" */
+    switch ( in_out_Config->video_input_channel_num ) {
+        case  0:
+            self->video_input_channel = VDC5_CHANNEL_0;
+            self->video_input_select = VDEC_ADC_VINSEL_VIN1;
+            break;
+        case  1:
+            self->video_input_channel = VDC5_CHANNEL_1;
+            self->video_input_select = VDEC_ADC_VINSEL_VIN1;
+            break;
+        case  2:
+            self->video_input_channel = VDC5_CHANNEL_0;
+            self->video_input_select = VDEC_ADC_VINSEL_VIN2;
+            break;
+        case  3:
+            self->video_input_channel = VDC5_CHANNEL_1;
+            self->video_input_select = VDEC_ADC_VINSEL_VIN2;
+            break;
+        default:
+            ASSERT_R( false,  e=E_OTHERS; goto fin );
+    }
+
+
+    /* Set default "in_out_Config->display_channel_num" */
+    if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_DISPLAY_CHANNEL_NUM ) ) {
+        if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM ) ) {
+            in_out_Config->display_channel_num = VIDEO_INPUT_NOT_DISPLAY;
+        } else {
+            in_out_Config->display_channel_num = WINDOW_SURFACES_DEFAULT_CHANNEL;
+        }
+    }
+
+
+    /* Set default "in_out_Config->display_layer_num" */
+    if ( IS_BIT_NOT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM ) ) {
+        if ( in_out_Config->display_channel_num == VIDEO_INPUT_NOT_DISPLAY ) {
+            in_out_Config->display_layer_num = VIDEO_INPUT_NOT_DISPLAY;
+        } else {
+            in_out_Config->display_layer_num = -1;
+        }
+    }
+    ASSERT_D( in_out_Config->display_layer_num == VIDEO_INPUT_NOT_DISPLAY  ||
+              in_out_Config->display_layer_num <= -1,  e=E_OTHERS; goto fin );
+    ASSERT_D(
+        ( in_out_Config->display_channel_num == VIDEO_INPUT_NOT_DISPLAY  &&
+          in_out_Config->display_layer_num   == VIDEO_INPUT_NOT_DISPLAY ) ||
+        ( in_out_Config->display_channel_num != VIDEO_INPUT_NOT_DISPLAY  &&
+          in_out_Config->display_layer_num   != VIDEO_INPUT_NOT_DISPLAY ),
+        e=E_OTHERS; goto fin );
+
+
+    /* Set "self->data_control_ID" : No care of "display_layer_num" */
+    if ( in_out_Config->display_channel_num == 0 ) {
+        if ( self->video_input_channel == 0 ) {
+            self->data_control_ID = VDC5_LAYER_ID_0_WR;
+        } else {
+            self->data_control_ID = VDC5_LAYER_ID_1_WR;
+        }
+    } else if ( in_out_Config->display_channel_num == 1 ) {
+        if ( self->video_input_channel == 0 ) {
+            self->data_control_ID = VDC5_LAYER_ID_1_WR;
+        } else {
+            self->data_control_ID = VDC5_LAYER_ID_0_WR;
+        }
+    } else {
+        ASSERT_D( in_out_Config->display_channel_num == VIDEO_INPUT_NOT_DISPLAY,
+                  e=E_OTHERS; goto fin );
+
+        self->data_control_ID = VDC5_LAYER_ID_0_WR;
+    }
+
+
+    /* Set "self->captured_async" */
+    self->captured_async = NULL;
+    if ( IS_BIT_SET( in_out_Config->flags, VIDEO_INPUT_CONFIG_T_CAPTURED_ASYNC ) ) {
+        self->captured_async = in_out_Config->captured_async;
+    }
+
+
+    /* From GRPDRV_Init() */
+    {
+        vdc5_input_t      input;
+
+        /* Input parameter */
+        input.inp_sel   = VDC5_INPUT_SEL_VDEC;           /* Input select */
+        input.inp_fh50  = (uint16_t)VSYNC_1_2_FH_TIMING; /* Vsync signal 1/2fH phase timing */
+        input.inp_fh25  = (uint16_t)VSYNC_1_4_FH_TIMING; /* Vsync signal 1/4fH phase timing */
+        input.dly       = NULL;                          /* Sync signal delay adjustment */
+        input.ext_sig   = NULL;                          /* External input signal */
+        e_vdc5 = R_VDC5_VideoInput( self->video_input_channel, &input );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+    }
+
+
+    /* ... */
+    {
+        vdec_channel_t           vdec_channel;  /* video decoder channel */
+#ifdef  IS_MBED_USED
+        graphics_col_sys_t       color_system = GRPH_COL_SYS_NTSC_358;
+#else
+        graphics_col_sys_t       color_system;
+#endif
+        vdc5_scalingdown_rot_t  *writing_scale = &writing_config.scalingdown_rot;
+
+
+        /* From SetVideoDecoder() */
+
+        if ( self->video_input_channel == VDC5_CHANNEL_0 ) {
+            vdec_channel = VDEC_CHANNEL_0;
+        } else {
+            ASSERT_R( self->video_input_channel == VDC5_CHANNEL_1,  e=E_OTHERS; goto fin );
+            vdec_channel = VDEC_CHANNEL_1;
+        }
+#ifdef  IS_MBED_USED
+        e_vdec = GRAPHICS_VideoDecoderInit( self->video_input_select, vdec_channel, color_system );
+        IF ( e_vdec != VDEC_OK ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+#else
+        color_system = GRAPHICS_VideoDecoderInit( self->video_input_select, vdec_channel );
+        if ( color_system == GRPH_COL_SYS_UNKNOWN ) {
+            color_system = GRPH_COL_SYS_NTSC_358;
+        }
+#endif
+
+
+        /* From GRPDRV_VideoCreateNonDispSurface() */
+
+        /* Image area to be captured */
+#if  VIDEO_FORMAT_TYPE == VIDEO_FORMAT_TYPE_NTSC
+        ASSERT_R( (color_system == GRPH_COL_SYS_NTSC_358) ||
+                  (color_system == GRPH_COL_SYS_NTSC_443),
+                  e=E_OTHERS; goto fin );
+
+        writing_scale->res.vs = (uint16_t)( IMGCAP_SIZE_NTSC_VS - 1 );
+        writing_scale->res.vw = (uint16_t)IMGCAP_SIZE_NTSC_VW;
+        writing_scale->res.hs = (uint16_t)IMGCAP_SIZE_NTSC_HS;
+        writing_scale->res.hw = (uint16_t)IMGCAP_SIZE_NTSC_HW;
+        /* v = vertical, h = horizontal, s = start, w = width */
+#elif  VIDEO_FORMAT_TYPE == VIDEO_FORMAT_TYPE_PAL
+        ASSERT_R( (color_system != GRPH_COL_SYS_NTSC_358) &&
+                  (color_system != GRPH_COL_SYS_NTSC_443),
+                  e=E_OTHERS; goto fin );
+
+        writing_scale->res.vs = (uint16_t)( IMGCAP_SIZE_PAL_VS - 1 );
+        writing_scale->res.vw = (uint16_t)IMGCAP_SIZE_PAL_VW;
+        writing_scale->res.hs = (uint16_t)IMGCAP_SIZE_PAL_HS;
+        writing_scale->res.hw = (uint16_t)IMGCAP_SIZE_PAL_HW;
+#else
+#error
+#endif
+
+
+        /* Write data parameter */
+        writing_scale->res_pfil_sel = VDC5_ON;
+        /* Prefilter mode select for brightness signals (on/off) */
+
+        writing_scale->res_out_vw   = frame->height / 2;
+        /* Number of valid lines in vertical direction */
+        /* output by scaling-down control block */
+
+        writing_scale->res_out_hw   = frame->width;
+        /* Number of valid horizontal pixels */
+        /* output by scaling-down control block */
+
+        writing_scale->adj_sel      = VDC5_ON;
+        /* Measures to decrease the influence */
+        /* by lack of last-input line (on/off) */
+
+        writing_scale->res_ds_wr_md = VDC5_WR_MD_NORMAL;
+        /* Frame buffer writing mode */
+    }
+
+
+    /* From GRPDRV_VideoCreateNonDispSurface() */
+    {
+        writing_config.res_wrswa     = VDC5_WR_RD_WRSWA_16BIT;
+        /* Frame buffer swap setting */
+
+        writing_config.res_md        = VIDEO_FORMAT;
+        /* Frame buffer video-signal writing format */
+
+        writing_config.res_bst_md    = VDC5_BST_MD_32BYTE;
+        /* Transfer burst length for frame buffer */
+
+        writing_config.res_inter     = VDC5_RES_INTER_INTERLACE;
+        /* Field operating mode select */
+
+        writing_config.res_fs_rate   = VDC5_RES_FS_RATE_PER1;
+        /* Writing rate */
+
+        writing_config.res_fld_sel   = VDC5_RES_FLD_SEL_TOP;
+        /* Write field select */
+
+        writing_config.res_dth_on    = VDC5_ON;
+        /* Dither correction on/off */
+
+        writing_config.base          = (void *) frame_physical_address[0];
+        /* Frame buffer base address */
+
+        writing_config.ln_off        = frame->stride;
+        /* Frame buffer line offset address [byte] */
+
+        writing_config.flm_num       = (uint32_t)( frame->buffer_count - 1u );
+        /* Number of frames of buffer (res_flm_num + 1) */
+
+        writing_config.flm_off       = frame_physical_address[1] - frame_physical_address[0];
+
+        writing_config.btm_base      = NULL;
+        /* Frame buffer base address for bottom */
+
+
+        e_vdc5 = R_VDC5_WriteDataControl( self->video_input_channel,
+                                          self->data_control_ID,  &writing_config );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+
+        self->is_data_control = true;
+    }
+
+
+    {
+        vdc5_start_t  start;
+
+        e_vdc5 = R_VDC5_StartProcess( self->video_input_channel, self->data_control_ID, &start );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e = E_OTHERS;
+            goto fin;
+        }
+
+        /* This module does not call "R_VDC5_StartProcess" function for reading (showing). */
+    }
+
+
+    {
+        vdc5_int_t     *config = &self->interrupt_for_VDC5;
+        bsp_int_err_t   ret_b;
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+        vdc5_int_cb_t  *p_VDC5_ISR;
+#endif
+
+        e= R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt(
+               self->video_input_channel, self->data_control_ID, self );
+        IF(e) {
+            goto fin;
+        }
+
+        self->is_vsync_interrupt_registered[2] = true;
+
+
+        if ( self->data_control_ID == VDC5_LAYER_ID_0_WR ) {
+            config->type = VDC5_INT_TYPE_S0_VI_VSYNC;
+        } else {
+            config->type = VDC5_INT_TYPE_S1_VI_VSYNC;
+        }
+        if ( self->video_input_channel == 0 ) {
+            config->callback = R_VIDEO_INPUT_OnVideoInVSync_Ch0;
+
+            if ( self->data_control_ID == VDC5_LAYER_ID_0_WR ) {
+                self->interrupt_ID = BSP_INT_SRC_S0_VI_VSYNC0;
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+                p_VDC5_ISR = &gs_VDC5_ISR_S0_VI_VSYNC0;
+                self->interrupt_vector = InterruptCallbackVector_S0_VI_VSYNC0;
+#endif
+            } else {
+                self->interrupt_ID = BSP_INT_SRC_S1_VI_VSYNC0;
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+                p_VDC5_ISR = &gs_VDC5_ISR_S1_VI_VSYNC0;
+                self->interrupt_vector = InterruptCallbackVector_S1_VI_VSYNC0;
+#endif
+            }
+        } else {
+            config->callback = R_VIDEO_INPUT_OnVideoInVSync_Ch1;
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+            if ( self->data_control_ID == VDC5_LAYER_ID_0_WR ) {
+                self->interrupt_ID = BSP_INT_SRC_S0_VI_VSYNC1;
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+                p_VDC5_ISR = &gs_VDC5_ISR_S0_VI_VSYNC1;
+                self->interrupt_vector = InterruptCallbackVector_S0_VI_VSYNC1;
+#endif
+            } else {
+                self->interrupt_ID = BSP_INT_SRC_S1_VI_VSYNC1;
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+                p_VDC5_ISR = &gs_VDC5_ISR_S1_VI_VSYNC1;
+                self->interrupt_vector = InterruptCallbackVector_S1_VI_VSYNC1;
+#endif
+            }
+#endif
+        }
+        config->line_num = 0;
+
+        e_vdc5 = R_VDC5_CallbackISR( self->video_input_channel, config );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+
+        self->is_vsync_interrupt_registered[1] = true;
+
+
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_LESS
+        {
+            vdc5_int_cb_t  a_VDC5_ISR;
+
+            a_VDC5_ISR = R_VDC5_GetISR( self->video_input_channel, config->type );
+            ret_b = R_BSP_InterruptWrite( self->interrupt_ID, a_VDC5_ISR );
+            IF ( ret_b != BSP_INT_SUCCESS ) {
+                e=E_OTHERS;
+                goto fin;
+            }
+        }
+#else
+        *p_VDC5_ISR = R_VDC5_GetISR( self->video_input_channel, config->type );
+        ret_b = R_BSP_InterruptWrite( self->interrupt_ID, self->interrupt_vector );
+        IF ( ret_b != BSP_INT_SUCCESS ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+#endif
+
+        self->is_vsync_interrupt_registered[0] = true;
+    }
+
+
+#ifndef R_OSPL_NDEBUG
+    printf( "VideoInput %dx%dx%dx%d stride=%d \n address[0]=0x%08X address[1]=0x%08X\n",
+            frame->buffer_count, frame->width, frame->height, frame->byte_per_pixel,
+            frame->stride,
+            (uintptr_t) frame->buffer_address[0],
+            (uintptr_t) frame->buffer_address[1] );
+    /* Cast of "uintptr_t" is for avoiding "format" warning of GNU_ARM */
+#endif
+
+
+    e=0;
+fin:
+    if ( e != 0 ) {
+        e= R_VIDEO_INPUT_Finalize( self, e );
+    }
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_VIDEO_INPUT_Finalize
+************************************************************************/
+errnum_t  R_VIDEO_INPUT_Finalize( video_input_t *const  self, errnum_t e )
+{
+    errnum_t       ee;
+    vdc5_error_t   e_vdc5;
+    bsp_int_err_t  ret_b;
+
+    if ( self->is_vsync_interrupt_registered[0] ) {
+        ret_b = R_BSP_InterruptWrite( self->interrupt_ID, FIT_NO_FUNC );
+        IF ( ret_b != BSP_INT_SUCCESS ) {
+            e= R_OSPL_MergeErrNum( e, E_OTHERS );
+        }
+
+        self->is_vsync_interrupt_registered[0] = false;
+    }
+
+
+    if ( self->is_vsync_interrupt_registered[1] ) {
+        vdc5_int_t  *config = &self->interrupt_for_VDC5;
+
+        config->callback = NULL;
+        config->line_num = 0;
+
+        e_vdc5 = R_VDC5_CallbackISR( self->video_input_channel, config );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e= R_OSPL_MergeErrNum( e, E_OTHERS );
+        }
+
+        config->type = VDC5_INT_TYPE_NUM;  /* Not Used interrupt type */
+
+        self->is_vsync_interrupt_registered[1] = false;
+    }
+
+
+    if ( self->is_vsync_interrupt_registered[2] ) {
+        ee= R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt(
+                self->video_input_channel, self->data_control_ID, self );
+        e= R_OSPL_MergeErrNum( e, ee );
+
+        self->is_vsync_interrupt_registered[2] = false;
+    }
+
+
+    if ( self->is_data_control ) {
+        e_vdc5 = R_VDC5_StopProcess( self->video_input_channel,
+                                     self->data_control_ID );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e= R_OSPL_MergeErrNum( e, E_OTHERS );
+        }
+
+        e_vdc5 = R_VDC5_ReleaseDataControl( self->video_input_channel,
+                                            self->data_control_ID );
+        IF ( e_vdc5 != VDC5_OK ) {
+            e= R_OSPL_MergeErrNum( e, E_OTHERS );
+        }
+
+        self->is_data_control = false;
+    }
+
+    return  e;
+}
+
+
+/**
+* @brief   Video input V-Sync interrupt handler.
+*
+* @param   channel_num channel_num.
+* @param   int_type vdc5_int_type_t.
+* @return  None.
+*/
+static void  R_VIDEO_INPUT_OnVideoInVSync( vdc5_channel_t  video_input_channel,  vdc5_int_type_t int_type )
+{
+    errnum_t        e;
+    video_input_t  *self = NULL;
+    /* NULL is for avoiding warning C4017W of mbed cloud compiler */
+
+    e= R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt( video_input_channel,  int_type,  &self );
+    IF(e) {
+        R_NOOP();
+    }
+    else if (
+        int_type == VDC5_INT_TYPE_S0_VI_VSYNC  ||
+        int_type == VDC5_INT_TYPE_S1_VI_VSYNC  ||
+        int_type == VDC5_INT_TYPE_S0_WLINE  ||
+        int_type == VDC5_INT_TYPE_S1_WLINE ) {
+        if ( IS_BIT_SET( VDC51.SC0_SCL1_WR7, 0x00000001u ) ) {
+            self->captured_buffer_index = 0;
+        } else {
+            self->captured_buffer_index = 1;
+        }
+
+        self->captured_count += 1;
+
+        if ( self->captured_async != NULL ) {
+            R_OSPL_EVENT_Set(
+                self->captured_async->A_Thread,
+                self->captured_async->A_EventValue );
+        }
+    }
+
+    R_DEBUG_BREAK_IF_ERROR();
+}
+
+
+/**
+* @brief   R_VIDEO_INPUT_OnVideoInVSync_Ch0
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+static void  R_VIDEO_INPUT_OnVideoInVSync_Ch0( vdc5_int_type_t int_type )
+{
+    R_VIDEO_INPUT_OnVideoInVSync( VDC5_CHANNEL_0, int_type );
+}
+
+
+/**
+* @brief   R_VIDEO_INPUT_OnVideoInVSync_Ch1
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+static void  R_VIDEO_INPUT_OnVideoInVSync_Ch1( vdc5_int_type_t int_type )
+{
+    R_VIDEO_INPUT_OnVideoInVSync( VDC5_CHANNEL_1, int_type );
+}
+
+
+/**
+* @brief   InterruptCallbackVector_S0_VI_VSYNC0
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+static void  InterruptCallbackVector_S0_VI_VSYNC0(void)
+{
+    gs_VDC5_ISR_S0_VI_VSYNC0(0);
+    GIC_EndInterrupt( BSP_INT_SRC_S0_VI_VSYNC0 );
+}
+#endif
+
+
+/**
+* @brief   InterruptCallbackVector_S0_VI_VSYNC1
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+static void  InterruptCallbackVector_S0_VI_VSYNC1(void)
+{
+    gs_VDC5_ISR_S0_VI_VSYNC1(0);
+    GIC_EndInterrupt( BSP_INT_SRC_S0_VI_VSYNC1 );
+}
+#endif
+
+
+/**
+* @brief   InterruptCallbackVector_S1_VI_VSYNC0
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+static void  InterruptCallbackVector_S1_VI_VSYNC0(void)
+{
+    gs_VDC5_ISR_S1_VI_VSYNC0(0);
+    GIC_EndInterrupt( BSP_INT_SRC_S1_VI_VSYNC0 );
+}
+#endif
+
+
+/**
+* @brief   InterruptCallbackVector_S1_VI_VSYNC1
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if INTERRUPT_FUNCTION_TYPE == INTERRUPT_FUNCTION_TYPE_OS_RTX
+static void  InterruptCallbackVector_S1_VI_VSYNC1(void)
+{
+    gs_VDC5_ISR_S1_VI_VSYNC1(0);
+    GIC_EndInterrupt( BSP_INT_SRC_S1_VI_VSYNC1 );
+}
+#endif
+
+
+/**
+* @brief   R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt
+*
+* @param   in_video_input_channel vdc5_channel_t.
+* @param   in_data_control_ID vdc5_layer_id_t.
+* @param   in_self video_input_t*
+* @return  Error Code. 0=No Error.
+*/
+static errnum_t  R_VIDEO_INPUT_STATIC_AttachSelfToInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t  *in_self )
+{
+    errnum_t         e;
+    video_input_t  **self_pp = NULL;
+    /* NULL is for avoiding warning C4017W of mbed cloud compiler */
+
+    e= R_VIDEO_INPUT_STATIC_GetSelfPointer(
+           in_video_input_channel,  in_data_control_ID,
+           &self_pp );
+    IF(e) {
+        goto fin;
+    }
+
+    ASSERT_R( *self_pp == NULL,  e=E_OTHERS; goto fin );
+
+    *self_pp = in_self;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt
+*
+* @param   in_video_input_channel vdc5_channel_t.
+* @param   in_data_control_ID vdc5_layer_id_t.
+* @param   in_self video_input_t*
+* @return  Error Code. 0=No Error.
+*/
+static errnum_t  R_VIDEO_INPUT_STATIC_DetachSelfFromInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t  *in_self )
+{
+    errnum_t         e;
+    video_input_t  **self_pp = NULL;
+    /* NULL is for avoiding warning C4017W of mbed cloud compiler */
+
+    e= R_VIDEO_INPUT_STATIC_GetSelfPointer(
+           in_video_input_channel,  in_data_control_ID,
+           &self_pp );
+    IF(e) {
+        goto fin;
+    }
+
+    ASSERT_R( *self_pp == in_self,  e=E_OTHERS; goto fin );
+
+    *self_pp = NULL;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt
+*
+* @param   in_interrupt vdc5_int_type_t.
+* @param   in_self video_input_t*
+* @return  Error Code. 0=No Error.
+*/
+static errnum_t  R_VIDEO_INPUT_STATIC_GetSelfFromInterrupt(
+    vdc5_channel_t  in_video_input_channel,  vdc5_int_type_t  in_interrupt,
+    video_input_t  **out_self )
+{
+    errnum_t         e;
+    vdc5_layer_id_t  data_control_ID = VDC5_LAYER_ID_0_WR;
+    /* VDC5_LAYER_ID_0_WR is for avoiding warning C4017W of mbed cloud compiler */
+    video_input_t  **self_pp = NULL;
+    /* NULL is for avoiding warning C4017W of mbed cloud compiler */
+
+
+    switch ( in_interrupt ) {
+        case  VDC5_INT_TYPE_S0_VI_VSYNC:
+            data_control_ID = VDC5_LAYER_ID_0_WR;
+            break;
+
+        case  VDC5_INT_TYPE_S1_VI_VSYNC:
+            data_control_ID = VDC5_LAYER_ID_1_WR;
+            break;
+
+        default:
+            ASSERT_R( false,  e=E_OTHERS;  goto fin );
+    }
+
+
+    e= R_VIDEO_INPUT_STATIC_GetSelfPointer(
+           in_video_input_channel,  data_control_ID,  &self_pp );
+    IF(e) {
+        goto fin;
+    }
+
+    *out_self = *self_pp;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   R_VIDEO_INPUT_STATIC_GetSelfPointer
+*
+* @param   in_video_input_channel vdc5_channel_t.
+* @param   in_data_control_ID vdc5_layer_id_t.
+* @param   out_self_pp video_input_t*
+* @return  Error Code. 0=No Error.
+*/
+static errnum_t  R_VIDEO_INPUT_STATIC_GetSelfPointer(
+    vdc5_channel_t  in_video_input_channel,  vdc5_layer_id_t  in_data_control_ID,
+    video_input_t ***  out_self_pp )
+{
+    errnum_t      e;
+    int_fast32_t  video_input_index;
+    int_fast32_t  data_control_index;
+
+
+    if ( in_video_input_channel == VDC5_CHANNEL_0 ) {
+        video_input_index = 0;
+    } else {
+        ASSERT_D( in_video_input_channel == VDC5_CHANNEL_1,  e=E_OTHERS; goto fin );
+
+        video_input_index = 1;
+    }
+
+    if ( in_data_control_ID == VDC5_LAYER_ID_0_WR ) {
+        data_control_index = 0;
+    } else {
+        ASSERT_D( in_data_control_ID == VDC5_LAYER_ID_1_WR,  e=E_OTHERS; goto fin );
+
+        data_control_index = 1;
+    }
+
+    *out_self_pp = &gs_InterruptToSelf[ video_input_index ][ data_control_index ];
+
+    e=0;
+#ifndef  R_OSPL_NDEBUG
+fin:
+#endif
+    return  e;
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/src/video_input_cpp.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,147 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  video_input_cpp.cpp
+* @brief   $Rev: 51 $
+* $Date:: 2014-03-14 18:42:33 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "video_input.hpp"
+#include  "video_input.h"
+#include  "r_ospl.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define  GS_DEFAULT_INT_VALUE  -1
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/***********************************************************************
+* ClassImplement: VideoInput
+************************************************************************/
+
+/***********************************************************************
+* Implement: VideoInput
+************************************************************************/
+VideoInput::VideoInput()
+{
+    this->_self = NULL;
+}
+
+
+/***********************************************************************
+* Implement: ~VideoInput
+************************************************************************/
+VideoInput::~VideoInput()
+{
+    this->destroy();
+}
+
+
+/***********************************************************************
+* Implement: initialize
+************************************************************************/
+errnum_t  VideoInput::initialize( VideoInputConfig &in_out_config )
+{
+    this->_self = new  video_input_t;
+    ASSERT_R( this->_self != NULL,  return  E_FEW_MEMORY );
+
+    in_out_config.flags =
+        VIDEO_INPUT_CONFIG_T_VIDEO_INPUT_CHANNEL_NUM |
+        VIDEO_INPUT_CONFIG_T_DISPLAY_CHANNEL_NUM |
+        VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM |
+        VIDEO_INPUT_CONFIG_T_FRAME_BUFFER |
+        VIDEO_INPUT_CONFIG_T_CAPTURED_ASYNC;
+
+    if ( in_out_config.video_input_channel_num == GS_DEFAULT_INT_VALUE ) {
+        in_out_config.flags &= ~VIDEO_INPUT_CONFIG_T_VIDEO_INPUT_CHANNEL_NUM;
+    }
+    if ( in_out_config.display_channel_num == GS_DEFAULT_INT_VALUE ) {
+        in_out_config.flags &= ~VIDEO_INPUT_CONFIG_T_DISPLAY_CHANNEL_NUM;
+    }
+    if ( in_out_config.display_layer_num == GS_DEFAULT_INT_VALUE ) {
+        in_out_config.flags &= ~VIDEO_INPUT_CONFIG_T_DISPLAY_LAYER_NUM;
+    }
+    if ( in_out_config.frame_buffer == NULL ) {
+        in_out_config.flags &= ~VIDEO_INPUT_CONFIG_T_FRAME_BUFFER;
+    }
+    if ( in_out_config.captured_async == NULL ) {
+        in_out_config.flags &= ~VIDEO_INPUT_CONFIG_T_CAPTURED_ASYNC;
+    }
+
+    return  R_VIDEO_INPUT_Initialize( this->_self,  (video_input_config_t *) &in_out_config );
+}
+
+
+/***********************************************************************
+* Implement: destroy
+************************************************************************/
+void  VideoInput::destroy()
+{
+    if ( this->_self != NULL ) {
+        errnum_t  e = R_VIDEO_INPUT_Finalize( this->_self,  0 );
+        ASSERT_R( e == 0,  R_NOOP() );
+    }
+}
+
+
+/***********************************************************************
+* ClassImplement: VideoInputConfig
+************************************************************************/
+
+/***********************************************************************
+* Implement: VideoInputConfig
+************************************************************************/
+VideoInputConfig::VideoInputConfig()
+{
+    this->flags = 0;
+    this->video_input_channel_num = GS_DEFAULT_INT_VALUE;
+    this->display_channel_num = GS_DEFAULT_INT_VALUE;
+    this->display_layer_num = GS_DEFAULT_INT_VALUE;
+    this->frame_buffer = NULL;
+    this->captured_async = NULL;
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/src/vsync.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,544 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  vsync.c
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "vsync.h"
+#include  "vsync_pl.h"
+#include  "r_ospl.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  r_v_sync_i_lock_t
+* @brief  I-Lock
+*/
+typedef struct st_r_v_sync_i_lock_t  r_v_sync_i_lock_t;
+struct st_r_v_sync_i_lock_t {
+    /** is_lock */
+    bool_t  is_lock;
+
+    /** channel_num */
+    int_fast32_t  channel_num;
+};
+
+
+/**
+* @struct  r_v_sync_channel_t
+* @brief  V-Sync context
+*/
+typedef struct st_r_v_sync_channel_t  r_v_sync_channel_t;
+struct st_r_v_sync_channel_t {
+    /*-----------------------------------------------------------*/
+    /* Group: Count */
+
+    /** VSync_FrameCount */
+    volatile int_fast32_t  VSync_FrameCount;
+
+    /** VSync_PreviousFrameCount */
+    volatile int_fast32_t  VSync_PreviousFrameCount;
+
+    /** VSync_TargetCount */
+    volatile int_fast32_t  VSync_TargetCount;
+
+
+    /*-----------------------------------------------------------*/
+    /* Group: Interrupt */
+
+    /** AsyncStatus */
+    r_v_sync_async_status_t  AsyncStatus;
+
+    /** InterruptCallbackCaller */
+    r_ospl_caller_t    InterruptCallbackCaller;
+
+    /** InterruptFlag */
+    r_ospl_flag32_t    InterruptFlag;
+
+    /** IsEnabledInterrupt */
+    bool_t             IsEnabledInterrupt;
+
+    /** InterruptEnables */
+    r_ospl_flag32_t    InterruptEnables;
+
+    /** I_Lock */
+    r_v_sync_i_lock_t  I_Lock;
+};
+
+
+/* Section: Global */
+/** V-Sync context */
+static r_v_sync_channel_t  gs_v_sync_channel[ R_V_SYNC_CHANNEL_COUNT ];
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static void   R_V_SYNC_I_LOCK_Reset( r_v_sync_i_lock_t *const  self );
+static bool_t R_V_SYNC_I_LOCK_Lock( r_v_sync_i_lock_t *const  self );
+static void   R_V_SYNC_I_LOCK_Unlock( r_v_sync_i_lock_t *const  self );
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_Initialize
+************************************************************************/
+errnum_t  R_V_SYNC_Initialize( int_fast32_t const  ChannelNum )
+{
+    errnum_t  e;
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    self->I_Lock.channel_num = ChannelNum;
+    R_V_SYNC_I_LOCK_Reset( &self->I_Lock );
+
+    ASSERT_R( self->AsyncStatus.State == R_OSPL_UNINITIALIZED,  e=E_STATE; goto fin );
+    R_OSPL_FLAG32_InitConst( &self->AsyncStatus.InterruptFlags );
+    R_OSPL_FLAG32_InitConst( &self->AsyncStatus.CancelFlags );
+
+    e= R_V_SYNC_OnInitialize( ChannelNum );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    self->IsEnabledInterrupt = true;
+    R_OSPL_FLAG32_InitConst( &self->InterruptEnables );
+    self->AsyncStatus.State = R_OSPL_RUNNABLE;
+
+    R_OSPL_FLAG32_Set( &self->InterruptEnables, R_V_SYNC_INTERRUPT_LINE_V_LINE );
+    /* V-Sync interrupt always be enabled. Because clear interrupt status */
+
+    e=0;
+fin:
+    if ( e != 0 ) {
+        e= R_V_SYNC_Finalize( ChannelNum, e );
+        R_UNREFERENCED_VARIABLE( e );
+    }
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_Finalize
+************************************************************************/
+errnum_t  R_V_SYNC_Finalize( int_fast32_t const  ChannelNum,  errnum_t e )
+{
+    bool_t                     was_enabled; /* = false; */ /* QAC 3197 */
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    was_enabled = R_V_SYNC_I_LOCK_Lock( &self->I_Lock );
+
+    if ( ! ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) ) {
+        if ( self->AsyncStatus.State != R_OSPL_UNINITIALIZED ) {
+            R_OSPL_FLAG32_Clear( &self->InterruptEnables, R_V_SYNC_INTERRUPT_LINE_V_LINE );
+
+            R_OSPL_FLAG32_Set( &self->AsyncStatus.CancelFlags,
+                               R_OSPL_CANNEL_REQUEST | R_OSPL_CANNELING | R_OSPL_CANNELED |
+                               R_OSPL_FINALIZE_REQUEST | R_OSPL_FINALIZING );
+
+            e= R_V_SYNC_OnFinalize( ChannelNum, e );
+
+            R_OSPL_FLAG32_Set( &self->AsyncStatus.CancelFlags, R_OSPL_FINALIZED );
+            R_OSPL_FLAG32_Clear( &self->AsyncStatus.CancelFlags, R_OSPL_FLAG32_ALL_BITS );
+            self->AsyncStatus.State = R_OSPL_UNINITIALIZED;
+        }
+    }
+
+    if ( IS( was_enabled ) ) {
+        R_V_SYNC_I_LOCK_Unlock( &self->I_Lock );
+    }
+    R_V_SYNC_I_LOCK_Reset( &self->I_Lock );
+
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_Wait
+************************************************************************/
+errnum_t  R_V_SYNC_Wait( int_fast32_t const  ChannelNum,
+                         int_fast32_t const  SwapInterval,  bool_t const  Is1VSyncAtMinimum )
+{
+    errnum_t        e;
+    r_ospl_async_t  async;
+    bit_flags32_t   got_flags;
+
+    async.Flags = R_F_OSPL_A_Thread;
+    async.A_Thread = R_OSPL_THREAD_GetCurrentId();
+
+    e= R_V_SYNC_WaitStart( ChannelNum, SwapInterval, Is1VSyncAtMinimum, &async );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e= R_OSPL_EVENT_Wait( async.A_EventValue, &got_flags, R_OSPL_INFINITE );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e= async.ReturnValue;
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_WaitStart
+************************************************************************/
+errnum_t  R_V_SYNC_WaitStart( int_fast32_t const  ChannelNum,
+                              int_fast32_t const  SwapInterval,  bool_t const  Is1VSyncAtMinimum,
+                              r_ospl_async_t *const  Async )
+{
+    errnum_t                   e;
+    bool_t                     was_enabled = false;
+    int_fast32_t               target_count;
+    int_fast32_t               operand1;
+    int_fast32_t               operand2;
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF ( Async == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    R_V_SYNC_SetDefaultAsync( Async, R_OSPL_ASYNC_TYPE_NORMAL );
+    Async->ReturnValue = 0;
+    ASSERT_R( Async->I_Thread == NULL,  e=E_OTHERS; goto fin );
+
+    was_enabled = R_V_SYNC_I_LOCK_Lock( &self->I_Lock );
+
+    ASSERT_R( self->AsyncStatus.State == R_OSPL_RUNNABLE, e=E_STATE; goto fin );
+
+
+    /* Set "self->VSync_TargetCount" */
+    target_count = self->VSync_PreviousFrameCount + SwapInterval;
+    if ( (Is1VSyncAtMinimum) && (target_count < (self->VSync_FrameCount + 1)) ) {
+        target_count = self->VSync_FrameCount + 1;
+    }
+    self->VSync_TargetCount = target_count;
+
+
+    /* If already target count */
+    operand1 = self->VSync_TargetCount;  /* SEC R3.6.2 */
+    operand2 = self->VSync_FrameCount;   /* SEC R3.6.2 */
+    if ( (operand1 - operand2) <= 0 ) {
+        operand1 = self->VSync_FrameCount;  /* SEC R3.6.2 */
+        self->VSync_PreviousFrameCount = operand1;
+
+        /* Set application event */
+        R_OSPL_EVENT_Set( Async->A_Thread, Async->A_EventValue );
+    } else {
+        /* Change state to waiting */
+        self->AsyncStatus.State = R_OSPL_RUNNING;
+
+        /* Clear application event */
+        R_OSPL_EVENT_Clear( Async->A_Thread, Async->A_EventValue );
+
+        /* Attach "Async" to interrupt */
+        /* ->MISRA 11.4 : Not too big "enum" is same bit count as "int" */ /* ->SEC R2.7.1 */
+        R_OSPL_CALLER_Initialize( &self->InterruptCallbackCaller,
+                                  Async, (volatile int_t *) &self->AsyncStatus.State, R_OSPL_INTERRUPTING, NULL, NULL );
+        /* <-MISRA 11.4 */ /* <-SEC R2.7.1 */
+        e= R_V_SYNC_SetInterruptCallbackCaller( ChannelNum,
+                                                &self->InterruptCallbackCaller );
+        IF(e!=0) {
+            goto fin;
+        }
+    }
+
+    e=0;
+fin:
+    if ( IS( was_enabled ) ) {
+        R_V_SYNC_I_LOCK_Unlock( &self->I_Lock );
+    }
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_OnInterrupting
+************************************************************************/
+errnum_t  R_V_SYNC_OnInterrupting( const r_ospl_interrupt_t *const  InterruptSource )
+{
+    errnum_t      e;
+    bool_t        was_enabled  = false;
+    int_fast32_t  operand1;
+    int_fast32_t  operand2;
+    int_fast32_t  channel_num_;
+    r_v_sync_channel_t  *self;
+    r_ospl_async_t      *notify_async = NULL;
+
+    IF_DQ( InterruptSource == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    channel_num_ = InterruptSource->ChannelNum;
+    self = &gs_v_sync_channel[ channel_num_ ];
+
+    if ( self->AsyncStatus.State != R_OSPL_INTERRUPTING ) {
+        e=0;
+        goto fin;
+    }
+
+    self->AsyncStatus.State = R_OSPL_INTERRUPTED;
+
+
+    /* Operate like R_V_SYNC_OnInterrupted() */
+    was_enabled = R_V_SYNC_I_LOCK_Lock( &self->I_Lock );
+
+    self->VSync_FrameCount += 1;
+
+
+    operand1 = self->VSync_TargetCount;  /* SEC R3.6.2 */
+    operand2 = self->VSync_FrameCount;   /* SEC R3.6.2 */
+    if ( (operand1 - operand2) <= 0 ) {
+        operand1 = self->VSync_FrameCount;  /* SEC R3.6.2 */
+        self->VSync_PreviousFrameCount = operand1;
+
+        e= R_V_SYNC_SetInterruptCallbackCaller( channel_num_, NULL );
+
+        self->AsyncStatus.State = R_OSPL_RUNNABLE;
+        notify_async = self->InterruptCallbackCaller.Async;
+    } else {
+        self->AsyncStatus.State = R_OSPL_RUNNING;
+    }
+
+
+    e=0;
+fin:
+    if ( IS( was_enabled ) ) {
+        /* ->QAC 3353 : "self" is always assigned, if "was_enabled" is true */
+        IF_DQ( self == NULL ) {}  /* QAC 3353 raises SEC R3.2.2 */
+        else {
+            R_V_SYNC_I_LOCK_Unlock( &self->I_Lock );
+        }
+        /* <-QAC 3353 */
+        /* This is for disabling interrupt by R_V_SYNC_I_LOCK_Disable() */
+    }
+
+    if ( notify_async != NULL ) {
+        R_OSPL_EVENT_Set( notify_async->A_Thread, notify_async->A_EventValue );
+    }
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_V_SYNC_GetAsyncStatus
+************************************************************************/
+errnum_t  R_V_SYNC_GetAsyncStatus( int_fast32_t const  ChannelNum,
+                                   const r_v_sync_async_status_t **const  out_Status )
+{
+    errnum_t  e;
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    IF_DQ( out_Status == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    *out_Status = &self->AsyncStatus;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   Enable interrupt API
+*
+* @param   ChannelNum ChannelNum
+* @return  None
+*/
+void  R_V_SYNC_EnableInterrupt( int_fast32_t const  ChannelNum )
+{
+    errnum_t  e;
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    R_V_SYNC_OnEnableInterrupt( ChannelNum, self->InterruptEnables.Flags );
+    self->IsEnabledInterrupt = true;
+
+    e=0;
+fin:
+    R_UNREFERENCED_VARIABLE( e );
+}
+
+
+/**
+* @brief   Disable interrupt API
+*
+* @param   ChannelNum ChannelNum
+* @return  None
+*/
+bool_t  R_V_SYNC_DisableInterrupt( int_fast32_t const  ChannelNum )
+{
+    errnum_t  e;
+    bool_t    was_interrupted = false;
+    r_v_sync_channel_t *const  self = &gs_v_sync_channel[ ChannelNum ];
+
+    IF ( (ChannelNum < 0) || (ChannelNum >= R_V_SYNC_CHANNEL_COUNT) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    was_interrupted = self->IsEnabledInterrupt;
+    self->IsEnabledInterrupt = false;
+
+    R_V_SYNC_OnDisableInterrupt( ChannelNum, self->InterruptEnables.Flags );
+
+    e=0;
+fin:
+    R_UNREFERENCED_VARIABLE( e );
+    return  was_interrupted;
+}
+
+
+/**
+* @brief   Reset I-Lock (Interrupt Lock)
+*
+* @param   self r_v_sync_i_lock_t
+* @return  None
+*/
+static void  R_V_SYNC_I_LOCK_Reset( r_v_sync_i_lock_t *const  self )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->is_lock = false;
+    R_V_SYNC_OnDisableInterrupt( self->channel_num, R_V_SYNC_INTERRUPT_LINE_ALL );
+
+fin:
+    return;
+}
+
+
+/**
+* @brief   Lock
+*
+* @param   self r_v_sync_i_lock_t
+* @return  Was interrupt enabled
+*/
+static bool_t  R_V_SYNC_I_LOCK_Lock( r_v_sync_i_lock_t *const  self )
+{
+    bool_t  is_locked;
+    bool_t  was_all_enabled; /* = false; */ /* QAC 3197 */
+    bool_t  b;
+
+    IF_DQ( self == NULL ) {
+        is_locked = true;
+        goto fin;
+    }
+
+    was_all_enabled = R_OSPL_DisableAllInterrupt();
+
+    is_locked = self->is_lock;
+    if ( ! is_locked ) {
+        b= R_V_SYNC_DisableInterrupt( self->channel_num );
+        R_UNREFERENCED_VARIABLE( b );  /* QAC 3200 : This is not error information */
+        self->is_lock = true;
+    }
+
+    if ( IS( was_all_enabled ) ) {
+        R_OSPL_EnableAllInterrupt();
+    }
+
+fin:
+    return  ! is_locked;
+}
+
+
+/**
+* @brief   Unlock
+*
+* @param   self r_v_sync_i_lock_t
+* @return  None
+*/
+static void  R_V_SYNC_I_LOCK_Unlock( r_v_sync_i_lock_t *const  self )
+{
+    bool_t  was_all_enabled; /* = false; */ /* QAC 3197 */
+
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    was_all_enabled = R_OSPL_DisableAllInterrupt();
+
+    R_V_SYNC_EnableInterrupt( self->channel_num );
+    self->is_lock = false;
+
+    if ( IS( was_all_enabled ) ) {
+        R_OSPL_EnableAllInterrupt();
+    }
+fin:
+    return;
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/src/window_surfaces.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,2168 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces.c
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 51 $
+* $Date:: 2014-03-14 18:42:33 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "r_typedefs.h"
+#include  "lcd_panel.h"
+#include  "r_ospl.h"
+#include  "clib_registers.h"
+#include  "clib_drivers.h"
+#include  "clib_samples.h"
+#include  "window_surfaces.h"
+#include  "vsync.h"
+#include  "window_surfaces_private.h"
+#include  "RGA.h"
+#include  "RGA_Port.h"
+#if  USE_LCD
+#include  "lcd_if.h"
+#endif
+#include  <stdio.h>  /* in R_WINDOW_SURFACES_DoMessageLoop */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @typedef  gs_frame_width_height_t
+* @brief  gs_frame_width_height_t
+*/
+#ifdef  IS_WINDOW_SURFACES_EX
+typedef struct st_gs_frame_width_height_t  gs_frame_width_height_t;
+struct st_gs_frame_width_height_t {
+    int_fast32_t  Width;
+    int_fast32_t  Height;
+};
+#endif
+
+
+/**
+* @typedef  gs_rectangle_t
+* @brief  gs_rectangle_t
+*/
+#ifdef  IS_WINDOW_SURFACES_EX
+typedef struct st_gs_rectangle_t  gs_rectangle_t;
+struct st_gs_rectangle_t {
+    int_fast32_t  Left;
+    int_fast32_t  Top;
+    int_fast32_t  Right;   /* include right  bound pixel */
+    int_fast32_t  Bottom;  /* include bottom bound pixel */ /* Top < Bottom */
+};
+#endif
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* GS_ : global static */
+/* VDC5_CHANNEL_0 = LCD_VDC5_CH0_PANEL = ... */
+/* VDC5_CHANNEL_1 = LCD_VDC5_CH1_PANEL = ... */
+#if WINDOW_SURFACES_DEFAULT_CHANNEL
+#define   GS_CHANNEL_n              VDC5_CHANNEL_1
+#define   GS_LCD_CHn_SIG_FV         LCD_CH1_SIG_FV
+#define   GS_LCD_CHn_SIG_FH         LCD_CH1_SIG_FH
+#define   GS_LCD_CHn_DISP_VS        LCD_CH1_DISP_VS
+#define   GS_LCD_CHn_DISP_VW        LCD_CH1_DISP_VW
+#define   GS_LCD_CHn_DISP_HS        LCD_CH1_DISP_HS
+#define   GS_LCD_CHn_DISP_HW        LCD_CH1_DISP_HW
+#define   GS_LCD_CHn_TCON_HALF      LCD_CH1_TCON_HALF
+#define   GS_LCD_CHn_TCON_OFFSET    LCD_CH1_TCON_OFFSET
+#define   GS_LCD_CHn_OUT_EDGE       LCD_CH1_OUT_EDGE
+#define   GS_LCD_CHn_OUT_FORMAT     LCD_CH1_OUT_FORMAT
+#define   GS_LCD_CHn_PANEL_CLK      LCD_CH1_PANEL_CLK
+#define   GS_LCD_CHn_PANEL_CLK_DIV  LCD_CH1_PANEL_CLK_DIV
+#define   GS_DISPLAY_CH             1   /* 1 or 0 */
+#else
+#define   GS_CHANNEL_n              VDC5_CHANNEL_0
+#define   GS_LCD_CHn_SIG_FV         LCD_CH0_SIG_FV
+#define   GS_LCD_CHn_SIG_FH         LCD_CH0_SIG_FH
+#define   GS_LCD_CHn_DISP_VS        LCD_CH0_DISP_VS
+#define   GS_LCD_CHn_DISP_VW        LCD_CH0_DISP_VW
+#define   GS_LCD_CHn_DISP_HS        LCD_CH0_DISP_HS
+#define   GS_LCD_CHn_DISP_HW        LCD_CH0_DISP_HW
+#define   GS_LCD_CHn_TCON_HALF      LCD_CH0_TCON_HALF
+#define   GS_LCD_CHn_TCON_OFFSET    LCD_CH0_TCON_OFFSET
+#define   GS_LCD_CHn_OUT_EDGE       LCD_CH0_OUT_EDGE
+#define   GS_LCD_CHn_OUT_FORMAT     LCD_CH0_OUT_FORMAT
+#define   GS_LCD_CHn_PANEL_CLK      LCD_CH0_PANEL_CLK
+#define   GS_LCD_CHn_PANEL_CLK_DIV  LCD_CH0_PANEL_CLK_DIV
+#define   GS_DISPLAY_CH             0   /* 1 or 0 */
+#endif
+
+#if  0
+#define   GS_BUFFER_WIDTH           800
+#define   GS_BUFFER_HEIGHT          480
+#else
+#define   GS_BUFFER_WIDTH           GS_LCD_CHn_DISP_HW
+#define   GS_BUFFER_HEIGHT          GS_LCD_CHn_DISP_VW
+#endif
+
+#define   GS_MEASURE_GPU_LOAD       0
+
+#define  GS_DEFAULT_CLEAR_COLOR  R_RGA_DEFAULT_CLEAR_COLOR
+
+#ifdef  R_REE_INIT
+#define  GRAPHICS_GetLvdsParam        Graphics_GetLvdsParam
+#define  GRAPHICS_SetLcdTconSettings  Graphics_SetLcdTconSettings
+#define  GRAPHICS_SetLcdPanel         Graphics_SetLcdPanel
+#endif
+#ifdef  RZ_A1L
+#define  GRAPHICS_GetLvdsParam( ch )                 NULL
+#define  GRAPHICS_SetLcdTconSettings( ch, setting )  GRAPHICS_L_SetLcdTconSettings( setting )
+#define  GRAPHICS_SetLcdPanel( ch )                  GRAPHICS_L_SetLcdPanel()
+#endif
+
+/**
+* @def  GS_OFFSET_BYTE_NOT_SHOW
+* @brief  GS_OFFSET_BYTE_NOT_SHOW
+*/
+enum { GS_OFFSET_BYTE_NOT_SHOW = -1 };
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static errnum_t  R_WINDOW_SURFACES_SwapBuffers_Sub( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num );
+
+#ifdef  IS_WINDOW_SURFACES_EX
+errnum_t  GS_ToInFrame(
+    gs_frame_width_height_t *SourceFrameBuffer,
+    gs_frame_width_height_t *DestinationFrameBuffer,
+    gs_rectangle_t *SourceRect,
+    gs_rectangle_t *DestinationRect );
+#endif
+
+
+/**
+* @brief   alloc_VRAM_stack_sub
+*
+* @param   in_out_StackPointer in_out_StackPointer
+* @param   OverOfVRAM OverOfVRAM
+* @param   in_out_FrameBuffer in_out_FrameBuffer
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - (input) - >stride, ->height, ->buffer_count
+*    - (output) - >buffer_address[(all)]
+*/
+static errnum_t  alloc_VRAM_stack_sub( uint8_t **const  in_out_StackPointer,
+                                       const uint8_t *const  OverOfVRAM,
+                                       frame_buffer_t *const  in_out_FrameBuffer ); /* QAC-3450 */
+static errnum_t  alloc_VRAM_stack_sub( uint8_t **const  in_out_StackPointer,
+                                       const uint8_t *const  OverOfVRAM,
+                                       frame_buffer_t *const  in_out_FrameBuffer )
+{
+    errnum_t      e;
+    int_fast32_t  size_1;
+    int_fast32_t  size_all;
+    int_fast32_t  buffer_num;
+    uint8_t      *stack_pointer;
+
+
+    IF_DQ( in_out_StackPointer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( in_out_FrameBuffer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+
+    stack_pointer = *in_out_StackPointer;
+
+
+    /* Set "size_1" */
+    size_1 = in_out_FrameBuffer->stride * in_out_FrameBuffer->height;
+    size_1 = ( R_Ceil_64s( size_1 ) );
+
+
+    /* Set "size_all" */
+    size_all = in_out_FrameBuffer->buffer_count * size_1;
+
+
+    /* Check */
+    /* ->MISRA 17.4 */ /* ->SEC R1.3.1 (1) */
+    IF ( (stack_pointer + size_all) > OverOfVRAM ) {
+        in_out_FrameBuffer->buffer_count = 0;
+        e=E_FEW_ARRAY;
+        goto fin;
+    }
+    /* <-MISRA 17.4 */ /* <-SEC R1.3.1 (1) */
+
+    IF ( in_out_FrameBuffer->buffer_count >
+         (int_fast32_t) R_COUNT_OF( in_out_FrameBuffer->buffer_address ) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+
+    /* Set "in_out_FrameBuffer->buffer_address" */
+    for ( buffer_num = 0;
+            buffer_num < in_out_FrameBuffer->buffer_count;
+            buffer_num += 1 ) {
+        in_out_FrameBuffer->buffer_address[ buffer_num ] = stack_pointer;
+
+        /* ->MISRA 17.4 */ /* ->SEC R1.3.1 (1) */
+        stack_pointer += size_1;  /* MISRA 17.4: Bound check is done by "OverOfVRAM" */
+        /* <-MISRA 17.4 */ /* <-SEC R1.3.1 (1) */
+    }
+    for ( /* buffer_num */;
+                          buffer_num < (int_fast32_t) R_COUNT_OF( in_out_FrameBuffer->buffer_address );
+                          buffer_num += 1 ) {
+        in_out_FrameBuffer->buffer_address[ buffer_num ] = NULL;
+    }
+
+    *in_out_StackPointer = stack_pointer;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   free_VRAM_stack_sub
+*
+* @param   in_out_StackPointer in_out_StackPointer
+* @param   frame_buffer frame_buffer
+* @param   StartOfVRAM StartOfVRAM
+* @return  Error code, 0=No error
+*
+* @par Description
+*    - If frame_buffer - >buffer_count == 0, do nothing.
+*/
+static errnum_t  free_VRAM_stack_sub( uint8_t **const  in_out_StackPointer,
+                                      const frame_buffer_t *const  frame_buffer,
+                                      const uint8_t *const  StartOfVRAM ); /* QAC-3450 */
+static errnum_t  free_VRAM_stack_sub( uint8_t **const  in_out_StackPointer,
+                                      const frame_buffer_t *const  frame_buffer,
+                                      const uint8_t *const  StartOfVRAM )
+{
+    errnum_t      e;
+    int_fast32_t  size_1;
+    int_fast32_t  size_all;
+    int_fast32_t  buffer_num;
+    uint8_t      *next_stack_pointer;
+
+
+    IF_DQ( frame_buffer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( in_out_StackPointer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+
+    /* Set "size_1" */
+    size_1 = frame_buffer->stride * frame_buffer->height;
+    size_1 = ( R_Ceil_64s( size_1 ) );
+    R_STATIC_ASSERT( RGA_STACK_ADDRESS_ALIGNMENT == 64, "" );  /* check of ceil_xx */
+
+
+    /* Set "size_all" */
+    size_all = frame_buffer->buffer_count * size_1;
+
+
+    /* Set "next_stack_pointer" */
+    /* ->MISRA 17.4 */ /* ->SEC R1.3.1 (1) */
+    next_stack_pointer = *in_out_StackPointer - size_all;
+    /* MISRA 17.4: Bound check is done by "StartOfVRAM" */
+    /* <-MISRA 17.4 */ /* <-SEC R1.3.1 (1) */
+
+
+    /* Check */
+    IF ( next_stack_pointer < StartOfVRAM ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    IF ( frame_buffer->buffer_count > (int_fast32_t) R_COUNT_OF( frame_buffer->buffer_address ) ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    for ( buffer_num = frame_buffer->buffer_count - 1;  buffer_num >= 0;  buffer_num -= 1 ) {
+        /* ->MISRA 17.4 */ /* ->SEC R1.3.1 (1) */
+        IF ( frame_buffer->buffer_address[ buffer_num ] !=
+             (next_stack_pointer + (size_1 * buffer_num)) ) {
+            e=E_ACCESS_DENIED;
+            goto fin;
+        }
+        /* MISRA 17.4: Bound check is done by "size_all" */
+        /* <-MISRA 17.4 */ /* <-SEC R1.3.1 (1) */
+    }
+
+
+    /* Set "*in_out_StackPointer" */
+    *in_out_StackPointer = next_stack_pointer;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/*-------------------------------------------------------------------------*/
+/* <<<< ### (window_surfaces_vdc5_layer_t) Class implement >>>> */
+/*-------------------------------------------------------------------------*/
+
+/**
+* @brief   Initialize <window_surfaces_vdc5_layer_t>
+*
+* @param   self window_surfaces_vdc5_layer_t
+* @param   layer_num layer_num
+* @param   graphics_layer_ID graphics_layer_ID
+* @return  Error code, 0=No error
+*/
+static errnum_t  window_surfaces_vdc5_layer_t__initialize(
+    window_surfaces_vdc5_layer_t *const  self,
+    int_fast32_t const  layer_num,
+    vdc5_graphics_type_t const  graphics_layer_ID ); /* QAC-3450 */
+
+static errnum_t  window_surfaces_vdc5_layer_t__initialize(
+    window_surfaces_vdc5_layer_t *const  self,
+    int_fast32_t const  layer_num,
+    vdc5_graphics_type_t const  graphics_layer_ID )
+{
+    errnum_t  e;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= R_int_t_to_int8_t( layer_num, &self->layer_num );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    self->graphics_layer_ID = graphics_layer_ID;
+
+    self->is_data_control = false;
+
+    self->layer_color = GS_DEFAULT_CLEAR_COLOR;
+
+    switch ( graphics_layer_ID ) {
+        case  VDC5_GR_TYPE_GR0:
+            self->data_control_ID = VDC5_LAYER_ID_0_RD;
+            break;
+#ifndef  RZ_A1L
+        case  VDC5_GR_TYPE_GR1:
+            self->data_control_ID = VDC5_LAYER_ID_1_RD;
+            break;
+#endif
+        case  VDC5_GR_TYPE_GR2:
+            self->data_control_ID = VDC5_LAYER_ID_2_RD;
+            break;
+        case  VDC5_GR_TYPE_GR3:
+            self->data_control_ID = VDC5_LAYER_ID_3_RD;
+            break;
+        default:
+            e=E_OTHERS;
+            goto fin; /* Bad "graphics_layer_ID" */
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+
+/*-------------------------------------------------------------------------*/
+/* <<<< ### (window_surfaces_t) Class implement >>>> */
+/*-------------------------------------------------------------------------*/
+
+/**
+* @brief   Get <window_surfaces_vdc5_layer_t>
+*
+* @param   self window_surfaces_t
+* @param   in_LayerNum in_LayerNum
+* @param   out_Layer out_Layer
+* @return  Error code, 0=No error
+*/
+STATIC_INLINE errnum_t  window_surfaces_t__get_layer( window_surfaces_t *const  self,
+        int_fast32_t const  in_LayerNum,
+        window_surfaces_vdc5_layer_t **const  out_Layer );  /* QAC-3450 */
+/* ->MISRA 16.7 : "self" can not "const", because "out_Layer" is not "const" */
+/* ->SEC M1.11.1 */
+STATIC_INLINE errnum_t  window_surfaces_t__get_layer( window_surfaces_t *const  self,
+        int_fast32_t const  in_LayerNum,
+        window_surfaces_vdc5_layer_t **const  out_Layer )
+/* <-MISRA 16.7 */ /* <-SEC M1.11.1 */
+{
+    errnum_t       e;
+    uint_fast32_t  index;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( out_Layer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    index = in_LayerNum - self->layer_num_min;
+
+    IF ( index >= R_COUNT_OF( self->layers ) ) {
+        e = E_OTHERS;
+        goto fin;
+    }
+
+    *out_Layer = &self->layers[ index ];
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   Get <window_surfaces_attribute_t>
+*
+* @param   self window_surfaces_t
+* @param   in_LayerNum in_LayerNum
+* @param   out_Attribute out_Attribute
+* @return  Error code, 0=No error
+*/
+#ifdef  IS_WINDOW_SURFACES_EX
+STATIC_INLINE errnum_t  window_surfaces_t__get_attribute( window_surfaces_t *const  self,
+        int_fast32_t const  in_LayerNum,
+        window_surfaces_attribute_t **const  out_Attribute );  /* QAC-3450 */
+/* ->MISRA 16.7 : "self" can not "const", because "out_Attribute" is not "const" */
+/* ->SEC M1.11.1 */
+STATIC_INLINE errnum_t  window_surfaces_t__get_attribute( window_surfaces_t *const  self,
+        int_fast32_t const  in_LayerNum,
+        window_surfaces_attribute_t **const  out_Attribute )
+/* <-MISRA 16.7 */ /* <-SEC M1.11.1 */
+{
+    errnum_t       e;
+    uint_fast32_t  index;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( out_Attribute == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    index = in_LayerNum - self->layer_num_min;
+
+    IF ( index >= R_COUNT_OF( self->layers ) ) {
+        e = E_OTHERS;
+        goto fin;
+    }
+
+    *out_Attribute = &self->attributes[ index ];
+
+    e=0;
+fin:
+    return  e;
+}
+#endif
+
+
+/***********************************************************************
+* Class: window_surfaces_t
+************************************************************************/
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_InitConst
+************************************************************************/
+
+static bool_t  gs_window_surfaces_t_is_init = false;
+
+void  R_WINDOW_SURFACES_InitConst( window_surfaces_t *const  self )
+{
+    int_fast32_t  i;
+
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    for ( i = 0;  i < (ssize_t) R_COUNT_OF( self->frame_buffers );  i += 1 ) {
+        self->frame_buffers[i].buffer_address[0] = NULL;
+    }
+    self->is_initialized = gs_window_surfaces_t_is_init;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_Initialize
+************************************************************************/
+
+static void  vdc5_init_func( uint32_t user_num );
+
+errnum_t  R_WINDOW_SURFACES_Initialize( window_surfaces_t *const  self,
+                                        window_surfaces_config_t  *in_out_config )
+{
+    errnum_t                  e;
+    errnum_t                  ee;
+    vdc5_error_t              error_vdc;
+    window_surfaces_config_t  default_config;
+    int_fast32_t              layer_num;
+    window_surfaces_vdc5_layer_t  *main_layer[ R_COUNT_OF( self->frame_buffers ) ];
+    window_surfaces_vdc5_layer_t  *back_layer;
+
+    enum { num_2 = 2,  num_4 = 4 };
+
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    self->screen_channel = GS_CHANNEL_n;
+
+
+    /* Set default configuration */
+    if ( in_out_config == NULL ) {
+        in_out_config = &default_config;
+        in_out_config->flags = 0;
+    }
+
+    if ( IS_BIT_NOT_SET( in_out_config->flags, F_WINDOW_SURFACES_PIXEL_FORMAT ) ) {
+        in_out_config->pixel_format = PIXEL_FORMAT_ARGB8888;
+        in_out_config->flags |= F_WINDOW_SURFACES_PIXEL_FORMAT;
+    }
+
+
+    if ( IS_BIT_NOT_SET( in_out_config->flags, F_WINDOW_SURFACES_LAYER_COUNT ) ) {
+        in_out_config->layer_count = 1;
+        in_out_config->flags |= F_WINDOW_SURFACES_LAYER_COUNT;
+    }
+    ASSERT_D( in_out_config->layer_count >= 1  &&  in_out_config->layer_count <= 2,
+              e=E_OTHERS; goto fin );
+
+
+    if ( IS_BIT_NOT_SET( in_out_config->flags, F_WINDOW_SURFACES_BUFFER_HEIGHT ) ) {
+        in_out_config->buffer_height = R_ToSigned( GS_BUFFER_HEIGHT );
+        in_out_config->flags |= F_WINDOW_SURFACES_BUFFER_HEIGHT;
+    }
+
+
+    if ( IS_BIT_NOT_SET( in_out_config->flags, F_WINDOW_SURFACES_BACKGROUND_COLOR ) ) {
+        in_out_config->background_color = GS_DEFAULT_CLEAR_COLOR;
+        in_out_config->flags |= F_WINDOW_SURFACES_BACKGROUND_COLOR;
+    }
+
+
+    if ( IS_BIT_NOT_SET( in_out_config->flags, F_WINDOW_SURFACES_BACKGROUND_FORMAT ) ) {
+        in_out_config->background_format = BACKGROUND_FORMAT_SOLID_COLOR;
+        in_out_config->flags |= F_WINDOW_SURFACES_BACKGROUND_FORMAT;
+    }
+
+
+    /* Set layers */
+#ifndef  RZ_A1L  /* RZ/A1H */
+    self->layer_num_min = -1;
+    self->layer_num_max =  in_out_config->layer_count - 1;
+    ASSERT_D( (ssize_t) R_COUNT_OF( self->layers ) >= self->layer_num_max - self->layer_num_min + 1,
+              e=E_OTHERS; goto fin );
+    e= window_surfaces_vdc5_layer_t__initialize( &self->layers[0], -1, VDC5_GR_TYPE_GR0 );
+    IF(e!=0) {
+        goto fin;
+    }
+    e= window_surfaces_vdc5_layer_t__initialize( &self->layers[1],  0, VDC5_GR_TYPE_GR1 );
+    IF(e!=0) {
+        goto fin;
+    }
+    e= window_surfaces_vdc5_layer_t__initialize( &self->layers[2],  1, VDC5_GR_TYPE_GR2 );
+    IF(e!=0) {
+        goto fin;
+    }
+#else
+    if ( in_out_config->pixel_format != PIXEL_FORMAT_YUV422 ) {
+        self->layer_num_min = -1;
+        self->layer_num_max =  in_out_config->layer_count - 1;
+        ASSERT_D( R_COUNT_OF( self->layers ) >= self->layer_num_max - self->layer_num_min + 1,
+                  e=E_OTHERS; goto fin );
+        e= window_surfaces_vdc5_layer_t__initialize( &self->layers[0], -1, VDC5_GR_TYPE_GR0 );
+        IF(e!=0) {
+            goto fin;
+        }
+        e= window_surfaces_vdc5_layer_t__initialize( &self->layers[1],  0, VDC5_GR_TYPE_GR2 );
+        IF(e!=0) {
+            goto fin;
+        }
+        e= window_surfaces_vdc5_layer_t__initialize( &self->layers[2],  1, VDC5_GR_TYPE_GR3 );
+        IF(e!=0) {
+            goto fin;
+        }
+    } else { /* PIXEL_FORMAT_YUV422 */
+        self->layer_num_min = 0;
+        self->layer_num_max = in_out_config->layer_count - 1;
+        ASSERT_D( R_COUNT_OF( self->layers ) >= self->layer_num_max - self->layer_num_min + 1,
+                  e=E_OTHERS; goto fin );
+        e= window_surfaces_vdc5_layer_t__initialize( &self->layers[0],  0, VDC5_GR_TYPE_GR0 );
+        IF(e!=0) {
+            goto fin;
+        }
+        e= window_surfaces_vdc5_layer_t__initialize( &self->layers[1],  1, VDC5_GR_TYPE_GR2 );
+        IF(e!=0) {
+            goto fin;
+        }
+    }
+#endif
+
+
+    /* Set "main_layer", "back_layer" */
+    for ( layer_num = 0;  layer_num <= self->layer_num_max;  layer_num += 1 ) {
+        e= window_surfaces_t__get_layer( self,  layer_num,  &main_layer[ layer_num ] );
+        IF(e!=0) {
+            goto fin;
+        }
+        IF_DQ( main_layer[ layer_num ] == NULL ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+    }
+
+    self->background_format = in_out_config->background_format;
+    if ( self->layer_num_min >= 0 ) {
+        back_layer = NULL;
+        self->background_frame_count = 0;
+    } else {
+        back_layer = NULL;
+        /* NULL is for avoiding warning C417W of mbed cloud compiler */
+        e= window_surfaces_t__get_layer( self, -1, &back_layer );
+        IF(e!=0) {
+            goto fin;
+        }
+        IF_DQ( back_layer == NULL ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+
+        if ( in_out_config->background_format != BACKGROUND_FORMAT_SOLID_COLOR ) {
+            self->background_frame_count = 1;
+        } else {
+            self->background_frame_count = 0;
+        }
+    }
+
+
+    {
+        uint8_t   *memory_address;
+        size_t     memory_size;
+
+
+        /* Set "physical_address", ... */
+        e= R_Sample_GetBigMemory( &memory_address,  &memory_size );
+        IF ( e != 0 ) {
+            goto fin;
+        }
+        /* 64byte alignment */
+        ASSERT_R( R_Mod_64u( (uintptr_t) memory_address ) == 0,  e=E_OTHERS; goto fin );
+
+
+        /* Set "self->start_of_VRAM", ... */
+        self->start_of_VRAM = memory_address;
+        /* ->MISRA 17.4 */ /* ->SEC R1.3.1 (1) */
+        self->over_of_VRAM  = self->start_of_VRAM + memory_size;  /* MISRA 17.4: This is a bound */
+        /* <-MISRA 17.4 */ /* <-SEC R1.3.1 (1) */
+        self->stack_pointer_of_VRAM = self->start_of_VRAM;
+    }
+
+
+    for ( layer_num = -self->background_frame_count;  layer_num <= self->layer_num_max;  layer_num += 1 ) {
+        frame_buffer_t  *frame;
+        window_surfaces_vdc5_layer_t  *layer = main_layer[ layer_num ];
+        pixel_format_t  pixel_format;
+
+        e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, layer_num, &frame );
+        IF(e) {
+            goto fin;
+        }
+
+        if ( layer_num <= -1  &&  in_out_config->background_format != BACKGROUND_FORMAT_SOLID_COLOR ) {
+            pixel_format = PIXEL_FORMAT_YUV422;
+        } else if ( layer_num >= 1  &&  in_out_config->pixel_format == PIXEL_FORMAT_YUV422 ) {
+            pixel_format = PIXEL_FORMAT_ARGB4444;
+        } else {
+            pixel_format = in_out_config->pixel_format;
+        }
+
+
+        /* Set "self->frame_buffers" */
+        frame->buffer_count      = num_2;
+        frame->show_buffer_index = 0;
+        frame->draw_buffer_index = 0;
+        frame->width             = R_ToSigned( GS_BUFFER_WIDTH );
+        frame->height            = in_out_config->buffer_height;
+        frame->pixel_format      = pixel_format;
+        frame->delegate          = NULL;
+
+        switch ( frame->pixel_format ) {
+            case PIXEL_FORMAT_ARGB8888:
+                frame->buffer_count      = 1;
+                frame->draw_buffer_index = 0;
+                frame->byte_per_pixel    = num_4;
+                layer->vdc5_format = VDC5_GR_FORMAT_ARGB8888;
+                break;
+
+            case PIXEL_FORMAT_XRGB8888:
+                frame->buffer_count      = 1;
+                frame->draw_buffer_index = 0;
+                frame->byte_per_pixel    = num_4;
+                layer->vdc5_format = VDC5_GR_FORMAT_RGB888;
+                break;
+
+            case PIXEL_FORMAT_RGB565:
+                frame->buffer_count      = num_2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = num_2;
+                layer->vdc5_format = VDC5_GR_FORMAT_RGB565;
+                break;
+
+            case PIXEL_FORMAT_ARGB1555:
+                frame->buffer_count      = num_2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = num_2;
+                layer->vdc5_format = VDC5_GR_FORMAT_ARGB1555;
+                break;
+
+            case PIXEL_FORMAT_ARGB4444:
+                frame->buffer_count      = num_2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = num_2;
+                layer->vdc5_format = VDC5_GR_FORMAT_ARGB4444;
+                break;
+
+            case PIXEL_FORMAT_YUV422:
+                frame->buffer_count      = num_2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = num_2;
+                layer->vdc5_format = VDC5_GR_FORMAT_YCBCR422;
+                break;
+
+            case PIXEL_FORMAT_CLUT8:
+                frame->buffer_count      = 2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = R_RGA_BitPerPixelType_To_BytePerPixelType( 8 );
+                layer->vdc5_format = VDC5_GR_FORMAT_CLUT8;
+                break;
+
+            case PIXEL_FORMAT_CLUT4:
+                frame->buffer_count      = 2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = R_RGA_BitPerPixelType_To_BytePerPixelType( 4 );
+                layer->vdc5_format = VDC5_GR_FORMAT_CLUT4;
+                break;
+
+            case PIXEL_FORMAT_CLUT1:
+                frame->buffer_count      = 2;
+                frame->draw_buffer_index = 1;
+                frame->byte_per_pixel    = R_RGA_BitPerPixelType_To_BytePerPixelType( 1 );
+                layer->vdc5_format = VDC5_GR_FORMAT_CLUT1;
+                break;
+
+            default:
+                layer->vdc5_format = VDC5_GR_FORMAT_NUM;  /* dummy data */
+                break;
+        }
+        if( R_BYTE_PER_PIXEL_IsInteger( frame->byte_per_pixel ) ) {
+            frame->stride = frame->width * frame->byte_per_pixel;
+        } else {
+            frame->stride = R_Ceil_8s( frame->width *
+                                       R_RGA_BytePerPixelType_To_BitPerPixelType( frame->byte_per_pixel ) ) / 8;
+            frame->stride = R_Ceil_32s( frame->stride );
+        }
+        e= alloc_VRAM_stack_sub( &self->stack_pointer_of_VRAM,
+                                 self->over_of_VRAM, frame );
+        IF(e!=0) {
+            goto fin;
+        }
+
+#ifndef R_OSPL_NDEBUG
+        printf( "Screen %dx%dx%dx%d vdc5_format=%d stride=%d \n address[0]=0x%08X address[1]=0x%08X\n",
+                frame->buffer_count, frame->width, frame->height, frame->byte_per_pixel,
+                layer->vdc5_format, frame->stride,
+                (uintptr_t) frame->buffer_address[0], (uintptr_t) frame->buffer_address[1] );
+        /* Cast of "uintptr_t" is for avoiding "format" warning of GNU_ARM */
+#endif
+    }
+
+
+    if ( ! self->is_initialized ) {
+
+        /* Call "R_VDC5_Initialize" */
+        {
+            vdc5_init_t  init;
+
+            init.panel_icksel = GS_LCD_CHn_PANEL_CLK;
+            init.panel_dcdr   = GS_LCD_CHn_PANEL_CLK_DIV;
+            init.lvds = GRAPHICS_GetLvdsParam( self->screen_channel );
+
+            error_vdc = R_VDC5_Initialize( self->screen_channel, &init,
+                                           &vdc5_init_func, (uint32_t) self->screen_channel );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+        }
+
+
+        /* Call "R_VDC5_SyncControl" */
+        {
+            vdc5_sync_ctrl_t  sync_ctrl;
+
+            sync_ctrl.res_vs_sel    = VDC5_ON;                      /* Free-running Vsync ON/OFF */
+            sync_ctrl.res_vs_in_sel = VDC5_RES_VS_IN_SEL_SC0;       /* SC_RES_VS_IN_SEL */
+            sync_ctrl.res_fv        = (uint16_t)GS_LCD_CHn_SIG_FV;     /* Free-running Vsync period setting */
+            sync_ctrl.res_fh        = (uint16_t)GS_LCD_CHn_SIG_FH;     /* Hsync period setting */
+            sync_ctrl.res_vsdly     = (uint16_t)0u;                 /* Vsync signal delay control */
+            /* Full-screen enable control */
+            sync_ctrl.res_f.vs      = (uint16_t)GS_LCD_CHn_DISP_VS;
+            sync_ctrl.res_f.vw      = (uint16_t)GS_LCD_CHn_DISP_VW;
+            sync_ctrl.res_f.hs      = (uint16_t)GS_LCD_CHn_DISP_HS;
+            sync_ctrl.res_f.hw      = (uint16_t)GS_LCD_CHn_DISP_HW;
+            sync_ctrl.vsync_cpmpe   = NULL;                         /* Vsync signal compensation */
+
+            error_vdc = R_VDC5_SyncControl( self->screen_channel, &sync_ctrl );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+        }
+
+
+        /* Call "R_VDC5_DisplayOutput" */
+        {
+            vdc5_output_t  output;
+            argb8888_t     background_color_;  /* _ is for MISRA 5.6 */
+
+            /* ->QAC 3198 */
+            background_color_.Value = DUMMY_INITIAL_VALUE;  /* for avoid ARMCC warning C4017W */
+            /* <-QAC 3198 */
+            background_color_.u.Alpha = 0;
+            background_color_.u.Red   = in_out_config->background_color.u.Red;
+            background_color_.u.Green = in_out_config->background_color.u.Green;
+            background_color_.u.Blue  = in_out_config->background_color.u.Blue;
+
+
+            output.tcon_half        = (uint16_t)GS_LCD_CHn_TCON_HALF;  /* TCON reference timing, 1/2fH timing */
+            output.tcon_offset      = (uint16_t)GS_LCD_CHn_TCON_OFFSET;/* TCON reference timing, offset Hsync signal timing */
+            /* LCD TCON timing setting */
+            GRAPHICS_SetLcdTconSettings( self->screen_channel, output.outctrl );
+            output.outcnt_lcd_edge  = GS_LCD_CHn_OUT_EDGE;          /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+            output.out_endian_on    = VDC5_OFF;                     /* Bit endian change ON/OFF control */
+            output.out_swap_on      = VDC5_OFF;                     /* B/R signal swap ON/OFF control */
+            output.out_format       = GS_LCD_CHn_OUT_FORMAT;        /* LCD output format select */
+            output.out_frq_sel      = VDC5_LCD_PARALLEL_CLKFRQ_1;   /* Clock frequency control */
+            output.out_dir_sel      = VDC5_LCD_SERIAL_SCAN_FORWARD; /* Scan direction select */
+            output.out_phase        = VDC5_LCD_SERIAL_CLKPHASE_0;   /* Clock phase adjustment */
+            output.bg_color         = background_color_.Value;
+
+            error_vdc = R_VDC5_DisplayOutput( self->screen_channel, &output );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+
+            if ( back_layer != NULL ) {
+                back_layer->layer_color = in_out_config->background_color;
+            }
+        }
+
+        self->is_initialized = true;
+    }
+
+
+    /* Call "R_VDC5_ReadDataControl" */
+    {
+        vdc5_read_t           read;
+        vdc5_width_read_fb_t  read_area;
+
+
+        for ( layer_num = 0;  layer_num <= self->layer_num_max;  layer_num += 1 ) {
+            int_fast32_t     bit_per_pixel;
+            frame_buffer_t  *frame;
+            window_surfaces_vdc5_layer_t  *layer = main_layer[ layer_num ];
+
+            e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, layer_num, &frame );
+            IF(e) {
+                goto fin;
+            }
+
+
+            /* Read data parameter */
+            read.gr_ln_off_dir  = VDC5_GR_LN_OFF_DIR_INC;   /* Line offset address direction of the frame buffer */
+            read.gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM;  /* Selects a frame buffer address setting signal */
+            read.gr_imr_flm_inv = VDC5_OFF;                 /* Sets the frame buffer number for distortion correction */
+            read.gr_bst_md      = VDC5_BST_MD_32BYTE;       /* Frame buffer burst transfer mode */
+            /* ->QAC 0306 */
+            read.gr_base        = (void *) frame->buffer_address[ frame->show_buffer_index ]; /* Frame buffer base address */
+            /* <-QAC 0306 */
+            read.gr_ln_off      = (uint32_t) frame->stride; /* Frame buffer line offset address */
+            read.width_read_fb = NULL;             /* width of the image read from frame buffer */
+            read.adj_sel = VDC5_OFF;                /* Measures to decrease the influence
+		                                                   by folding pixels/lines (ON/OFF) */
+            read.gr_format      = layer->vdc5_format;       /* Graphics format of the frame buffer read signal */
+            read.gr_ycc_swap = VDC5_GR_YCCSWAP_Y1CRY0CB;
+            /* Controls swapping of data read from buffer in the YCbCr422 format */
+
+            bit_per_pixel = R_RGA_BytePerPixelType_To_BitPerPixelType( frame->byte_per_pixel );
+            if ( (bit_per_pixel == 32) || (frame->pixel_format == PIXEL_FORMAT_YCbCr422) ) {
+                read.gr_rdswa = VDC5_WR_RD_WRSWA_32BIT;
+            } else if ( bit_per_pixel == 16 ) {
+                read.gr_rdswa = VDC5_WR_RD_WRSWA_32_16BIT;
+            } else if ( bit_per_pixel <= 8 ) {
+                read.gr_rdswa = VDC5_WR_RD_WRSWA_32_16_8BIT;
+            }
+            /* Display area */
+            read.gr_grc.hs      = (uint16_t) GS_LCD_CHn_DISP_HS;
+            read.gr_grc.hw      = (uint16_t) GS_LCD_CHn_DISP_HW;
+            read.gr_grc.vs      = (uint16_t) GS_LCD_CHn_DISP_VS;
+            if ( GS_BUFFER_HEIGHT < GS_LCD_CHn_DISP_VW ) {
+                read.gr_grc.vw      = (uint16_t) GS_BUFFER_HEIGHT;
+            } else {
+                read.gr_grc.vw      = (uint16_t) GS_LCD_CHn_DISP_VW;
+            }
+
+            error_vdc = R_VDC5_ReadDataControl( self->screen_channel, layer->data_control_ID, &read );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+            layer->is_data_control = true;
+        }
+
+        if ( back_layer != NULL ) {
+            if ( self->background_format == BACKGROUND_FORMAT_SOLID_COLOR ) {
+
+                /* Set display area for back ground */
+                /* "read.gr_base", ... are ignored */
+
+                error_vdc = R_VDC5_ReadDataControl( self->screen_channel, back_layer->data_control_ID, &read );
+                IF ( error_vdc != VDC5_OK ) {
+                    e = E_OTHERS;
+                    goto fin;
+                }
+            } else {
+                frame_buffer_t                *frame;
+                window_surfaces_vdc5_layer_t  *layer = back_layer;
+
+                e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, -1, &frame );
+                IF(e) {
+                    goto fin;
+                }
+
+
+                /* Read data parameter */
+                read.gr_ln_off_dir  = VDC5_GR_LN_OFF_DIR_INC;   /* Line offset address direction of the frame buffer */
+                read.gr_flm_sel     = VDC5_GR_FLM_SEL_FLM_NUM;  /* Selects a frame buffer address setting signal */
+                read.gr_imr_flm_inv = VDC5_OFF;                 /* Sets the frame buffer number for distortion correction */
+                read.gr_bst_md      = VDC5_BST_MD_32BYTE;       /* Frame buffer burst transfer mode */
+                /* ->QAC 0306 */
+                read.gr_base        = (void *) frame->buffer_address[ frame->show_buffer_index ]; /* Frame buffer base address */
+                /* <-QAC 0306 */
+                read.gr_ln_off      = (uint32_t) frame->stride; /* Frame buffer line offset address */
+                read_area.in_hw     = frame->width;
+                read_area.in_vw     = frame->height / 2;
+                read.width_read_fb  = &read_area;
+                read.adj_sel        = VDC5_ON;
+                read.gr_format      = layer->vdc5_format;       /* Graphics format of the frame buffer read signal */
+                read.gr_ycc_swap    = VDC5_GR_YCCSWAP_CBY0CRY1;
+                /* Controls swapping of data read from buffer in the YCbCr422 format */
+                read.gr_rdswa = VDC5_WR_RD_WRSWA_16BIT;
+
+                /* Display area */
+                read.gr_grc.hs      = (uint16_t) GS_LCD_CHn_DISP_HS;
+                read.gr_grc.hw      = (uint16_t) GS_LCD_CHn_DISP_HW;
+                read.gr_grc.vs      = (uint16_t) GS_LCD_CHn_DISP_VS;
+                if ( GS_BUFFER_HEIGHT < GS_LCD_CHn_DISP_VW ) {
+                    read.gr_grc.vw = (uint16_t) GS_BUFFER_HEIGHT;
+                } else {
+                    read.gr_grc.vw = (uint16_t) GS_LCD_CHn_DISP_VW;
+                }
+
+                error_vdc = R_VDC5_ReadDataControl( self->screen_channel, layer->data_control_ID, &read );
+                IF ( error_vdc != VDC5_OK ) {
+                    e = E_OTHERS;
+                    goto fin;
+                }
+            }
+            back_layer->is_data_control = true;
+        }
+    }
+
+
+    /* Call "R_VDC5_AlphaBlending" for ARGB1555 */
+    for ( layer_num = 0;  layer_num <= self->layer_num_max;  layer_num += 1 ) {
+        frame_buffer_t  *frame;
+
+        e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, layer_num, &frame );
+        IF(e) {
+            goto fin;
+        }
+
+        if ( frame->pixel_format == PIXEL_FORMAT_ARGB1555 ) {
+            static vdc5_alpha_argb1555_t  alpha_for_argb1555 = { 0x00, U8_255 };
+            static vdc5_alpha_blending_t  blend = { &alpha_for_argb1555, NULL };
+
+            error_vdc = R_VDC5_AlphaBlending( self->screen_channel,
+                                              main_layer[ layer_num ]->data_control_ID,
+                                              &blend );
+            IF( error_vdc != VDC5_OK ) {
+                e=E_OTHERS;
+                goto fin;
+            }
+        }
+    }
+
+
+    /* Call "R_V_SYNC_Initialize" */
+    e= R_V_SYNC_Initialize( (int_fast32_t) self->screen_channel );
+    IF ( e != 0 ) {
+        goto fin;
+    }
+
+
+    /* Wait for avoiding LCD filled white (LCD-KIT-B01) */
+    e= R_OSPL_Delay( 80 );
+    IF(e) {
+        goto fin;
+    }
+
+
+    /* Set graphics display mode */
+    {
+        vdc5_start_t  start;
+        int_fast32_t  i;
+
+        for ( i = 0;  i < (int_fast32_t) R_COUNT_OF( self->vdc5_disp_sel_array );  i += 1 ) {
+            self->vdc5_disp_sel_array[ i ] = VDC5_DISPSEL_LOWER;  /* Reset */
+        }
+        self->vdc5_disp_sel_array[ VDC5_GR_TYPE_GR0 ] = VDC5_DISPSEL_BACK;
+
+        start.gr_disp_sel = self->vdc5_disp_sel_array;
+        error_vdc = R_VDC5_StartProcess( self->screen_channel, VDC5_LAYER_ID_ALL, &start );
+        IF ( error_vdc != VDC5_OK ) {
+            e = E_OTHERS;
+            goto fin;
+        }
+    }
+
+#if  USE_LCD
+    R_OSPL_Delay( 2*17 );  /* Synchronize to LCD */
+    LCD_SetBacklight( 100 );
+#endif
+
+
+    /* Set "self->attributes" */
+    for ( layer_num = self->layer_num_min;  layer_num <=  self->layer_num_max;  layer_num += 1 ) {
+        window_surfaces_attribute_t  *attribute = NULL;
+        /* NULL is for avoiding warning C417W of mbed cloud compiler */
+
+        e= window_surfaces_t__get_attribute( self, layer_num, &attribute );
+        IF(e) {
+            goto fin;
+        }
+
+        attribute->X = 0;
+        attribute->Y = 0;
+        attribute->Width  = R_ToSigned( GS_BUFFER_WIDTH );
+        attribute->Height = in_out_config->buffer_height;
+        attribute->OffsetX = 0;
+        attribute->OffsetY = 0;
+        attribute->OffsetByte = 0;
+    }
+
+
+    e=0;
+fin:
+    if ( e != 0 ) {
+        if ( self != NULL ) {
+            ee= R_WINDOW_SURFACES_Finalize( self, e );
+            R_UNREFERENCED_VARIABLE( ee );
+        }
+    }
+    return  e;
+}
+
+
+/**
+* @brief   vdc5_init_func
+*
+* @param   user_num channel
+* @return  None
+*/
+static void  vdc5_init_func( uint32_t const  user_num )
+{
+    vdc5_channel_t        channel;
+    struct st_cpg *const  reg_CPG = R_Get_CPG_Base();
+
+    IF_DQ( reg_CPG == NULL ) {
+        goto fin;
+    }
+
+    channel = (vdc5_channel_t)user_num;
+    if (channel == VDC5_CHANNEL_0) {
+        /* Standby control register 9 (STBCR9)
+        	b1      ------0-;  MSTP91 : 0 : Video display controller channel 0 & LVDS enable */
+        R_DRV_SET_REGISTER_BIT_FIELD( &reg_CPG->STBCR9, STBCR9, MSTP91, false );
+    } else {
+        /* Standby control register 9 (STBCR9)
+        	b1      ------0-;  MSTP91 : 0 : Video display controller channel 0 & LVDS enable
+        	b0      -------0;  MSTP90 : 0 : Video display controller channel 1 enable */
+        R_DRV_SET_REGISTER_BIT_FIELD( &reg_CPG->STBCR9, STBCR9, MSTP91, false );
+        R_DRV_SET_REGISTER_BIT_FIELD( &reg_CPG->STBCR9, STBCR9, MSTP90, false );
+    }
+    GRAPHICS_SetLcdPanel(channel);
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_Finalize
+************************************************************************/
+
+static void  vdc5_quit_func( uint32_t const  user_num );
+
+errnum_t  R_WINDOW_SURFACES_Finalize( window_surfaces_t *const  self,  errnum_t e )
+{
+    vdc5_error_t  error_vdc;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= R_V_SYNC_Finalize( (int_fast32_t) self->screen_channel, e );
+
+    if ( ! self->is_initialized ) {
+        error_vdc = R_VDC5_Terminate( self->screen_channel, &vdc5_quit_func,
+                                      (uint32_t) self->screen_channel );
+        IF ( (error_vdc != VDC5_OK) && (e == 0) ) {
+            e = E_OTHERS;
+        }
+    } else {
+        int_fast32_t  i;
+
+        for ( i = -self->background_frame_count;  i <= self->layer_num_max;  i += 1 ) {
+            frame_buffer_t  *frame;
+            errnum_t         ee;
+
+            ee= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, i, &frame );
+            e= R_OSPL_MergeErrNum( e, ee );
+            frame->buffer_address[0] = NULL;
+        }
+
+        for ( i = self->layer_num_min;  i <=  self->layer_num_max;  i += 1 ) {
+            window_surfaces_vdc5_layer_t  *layer = NULL;
+            /* NULL is for avoiding warning C417W of mbed cloud compiler */
+            errnum_t  ee = window_surfaces_t__get_layer( self, i, &layer );
+
+            IF_DQ ( layer == NULL ) {
+                e=E_OTHERS;    /* Same check as "ee" */
+                goto fin;
+            }
+
+            if ( (ee == 0) && (layer->is_data_control) ) {
+                error_vdc = R_VDC5_StopProcess( self->screen_channel,
+                                                layer->data_control_ID );
+                IF ( (error_vdc != VDC5_OK) && (e == 0) ) {
+                    e = E_OTHERS;
+                }
+                error_vdc = R_VDC5_ReleaseDataControl( self->screen_channel,
+                                                       layer->data_control_ID );
+                layer->is_data_control = false;
+                IF ( (error_vdc != VDC5_OK) && (e == 0) ) {
+                    e = E_OTHERS;
+                }
+            }
+        }
+
+#define  R_WINDOW_SURFACES_TERMINATE_VDC5  1  /* 0 or 1 */
+#if      R_WINDOW_SURFACES_TERMINATE_VDC5
+        self->is_initialized = false;
+
+        error_vdc = R_VDC5_Terminate( self->screen_channel, &vdc5_quit_func,
+                                      (uint32_t) self->screen_channel );
+        IF ( (error_vdc != VDC5_OK) && (e == 0) ) {
+            e = E_OTHERS;
+        }
+#endif
+    }
+
+    gs_window_surfaces_t_is_init = self->is_initialized;
+
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   vdc5_quit_func
+*
+* @param   user_num channel
+* @return  None
+*/
+static void  vdc5_quit_func( uint32_t const  user_num )
+{
+    vdc5_channel_t const  channel = (vdc5_channel_t) user_num;
+    struct st_cpg *const  reg_CPG = R_Get_CPG_Base();
+
+    IF_DQ( reg_CPG == NULL ) {
+        goto fin;
+    }
+
+    if (channel == VDC5_CHANNEL_0) {
+        /* If LVDS should remain enabled, the following code should be removed. */
+        R_DRV_SET_REGISTER_BIT_FIELD( &reg_CPG->STBCR9, STBCR9, MSTP91, true );
+    } else {
+        R_DRV_SET_REGISTER_BIT_FIELD( &reg_CPG->STBCR9, STBCR9, MSTP90, true );
+    }
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_GetLayerFrameBuffer
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_GetLayerFrameBuffer( const window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  frame_buffer_t **const  out_frame_buffer )
+{
+    errnum_t       e;
+    uint_fast32_t  index;
+
+    IF_DQ( out_frame_buffer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    index = layer_num + self->background_frame_count;
+    IF ( index >= R_COUNT_OF( self->frame_buffers ) ) {
+        e = E_OTHERS;
+        goto fin;
+    }
+
+    *out_frame_buffer = (frame_buffer_t *) &self->frame_buffers[ index ];
+    /* Cast is for const */
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_SwapBuffers
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_SwapBuffers( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  graphics_t *const  context )
+{
+    errnum_t  e;
+#if GS_MEASURE_GPU_LOAD
+    enum {                interval = 60 };
+    uint32_t              idle_start_time;
+    uint32_t              idle_end_time;
+    static  uint32_t      skip_count;
+    static  uint32_t      previous_idle_end_time;
+    r_ospl_ftimer_spec_t  ts;
+#endif
+
+
+    e= R_GRAPHICS_Finish( context );
+    IF(e!=0) {
+        goto fin;
+    }
+
+
+#if GS_MEASURE_GPU_LOAD
+    e= R_OSPL_FTIMER_InitializeIfNot( &ts );
+    IF(e) {
+        goto fin;
+    }
+    idle_start_time = R_OSPL_FTIMER_Get();
+#endif
+
+
+    e= R_WINDOW_SURFACES_SwapBuffers_Sub( self, layer_num );
+    IF(e!=0) {
+        goto fin;
+    }
+
+
+    e= R_V_SYNC_Wait( self->screen_channel, 1, true );
+    IF(e!=0) {
+        goto fin;
+    }
+
+
+#if GS_MEASURE_GPU_LOAD
+    idle_end_time = R_OSPL_FTIMER_Get();
+    if ( previous_idle_end_time != 0 ) {  /* Skip at first */
+        skip_count += 1;
+        if ( skip_count >= interval ) {
+            printf( "GPU %d%% in %dmsec\n",
+                    ( idle_start_time - previous_idle_end_time ) * 100 /
+                    ( idle_end_time   - previous_idle_end_time ),
+                    R_OSPL_FTIMER_CountToTime( &ts,
+                                               idle_end_time - previous_idle_end_time ) );
+            skip_count = 0;
+
+            /* __heapstats( (__heapprt) fprintf, stdout ); */
+
+            /* R_DEBUG_BREAK(); */ /* This is for measuring CPU load */
+        }
+    }
+    previous_idle_end_time = idle_end_time;
+#endif
+
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_SwapBuffersStart
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_SwapBuffersStart( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num,  r_ospl_async_t *async )
+{
+    errnum_t  e;
+
+
+    e= R_WINDOW_SURFACES_SwapBuffers_Sub( self, layer_num );
+    IF(e!=0) {
+        goto fin;
+    }
+
+
+    e= R_V_SYNC_WaitStart( self->screen_channel, 1, true, async );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   Sub routine of <R_WINDOW_SURFACES_SwapBuffers>
+*
+* @param   self window_surfaces_t
+* @param   layer_num layer_num
+* @return  Error code, 0=No error
+*/
+static errnum_t  R_WINDOW_SURFACES_SwapBuffers_Sub( window_surfaces_t *const  self,
+        int_fast32_t const  layer_num )
+{
+    errnum_t         e;
+    vdc5_error_t     error_vdc;
+    frame_buffer_t  *frame;
+    window_surfaces_vdc5_layer_t  *layer = NULL;
+    /* NULL is for avoiding warning C417W of mbed cloud compiler */
+
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= window_surfaces_t__get_layer( self, layer_num, &layer );
+    IF(e!=0) {
+        goto fin;
+    }
+    IF_DQ( layer == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+
+    /* Swap buffer index */
+    e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, layer_num, &frame );
+    IF(e) {
+        goto fin;
+    }
+    frame->show_buffer_index = frame->draw_buffer_index;
+    frame->draw_buffer_index += 1;
+    if ( frame->draw_buffer_index >= (int_t) frame->buffer_count ) {
+        frame->draw_buffer_index = 0;
+    }
+
+
+    /* Show the frame buffer */
+    {
+        vdc5_read_chg_t  config;
+        uintptr_t        physical_address;
+
+        window_surfaces_attribute_t   *attribute = NULL;
+        /* NULL is for avoiding warning C417W of mbed cloud compiler */
+
+        e= R_OSPL_ToPhysicalAddress( frame->buffer_address[ frame->show_buffer_index ],
+                                     &physical_address );
+        IF(e!=0) {
+            goto fin;
+        }
+
+        e= window_surfaces_t__get_attribute( self, layer_num, &attribute );
+        IF(e) {
+            goto fin;
+        }
+
+        if ( attribute->OffsetByte != GS_OFFSET_BYTE_NOT_SHOW ) {
+            physical_address += attribute->OffsetByte;
+
+            config.gr_base        = (void *) physical_address;
+            config.width_read_fb  = NULL;
+            config.gr_grc         = NULL;
+            config.gr_disp_sel    = NULL;
+            error_vdc = R_VDC5_ChangeReadProcess( self->screen_channel, layer->data_control_ID, &config );
+            IF ( error_vdc != VDC5_OK ) {
+                e=E_OTHERS;
+                goto  fin;
+            }
+        }
+    }
+
+
+    /* Show the layer */
+    {
+        vdc5_gr_disp_sel_t  new_value;
+
+        if ( layer_num == 1 ) {
+            new_value = VDC5_DISPSEL_BLEND;
+        } else if ( layer_num == 0 ) {
+            frame_buffer_t  *frame;
+
+            e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, layer_num, &frame );
+            IF(e) {
+                goto fin;
+            }
+
+            if ( frame->pixel_format == PIXEL_FORMAT_YUV422 ) {
+                new_value = VDC5_DISPSEL_CURRENT;
+            } else {
+                new_value = VDC5_DISPSEL_BLEND;
+            }
+        } else {
+            ASSERT_D( layer_num == -1,  e=E_OTHERS; goto fin );
+
+            if ( self->background_format == BACKGROUND_FORMAT_SOLID_COLOR ) {
+                new_value = VDC5_DISPSEL_CURRENT;
+            } else {
+                new_value = VDC5_DISPSEL_LOWER;  /* "*_LOWER" is "*_CURRENT" for resize */
+            }
+        }
+
+        if ( self->vdc5_disp_sel_array[ layer->graphics_layer_ID ] != new_value ) {
+            vdc5_start_t  start;
+
+            self->vdc5_disp_sel_array[ layer->graphics_layer_ID ] = new_value;
+
+            start.gr_disp_sel = self->vdc5_disp_sel_array;
+            error_vdc = R_VDC5_StartProcess( self->screen_channel, VDC5_LAYER_ID_ALL, &start );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+        }
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_WaitForVSync
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_WaitForVSync( window_surfaces_t *const  self,
+        int_fast32_t const  swap_interval,  bool_t const  is_1_v_sync_at_minimum )
+{
+    return  R_V_SYNC_Wait( self->screen_channel, swap_interval, is_1_v_sync_at_minimum );
+}
+
+
+/**
+* @brief   R_WINDOW_SURFACES_AllocOffscreenStack
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t  R_WINDOW_SURFACES_AllocOffscreenStack( window_surfaces_t *const  self,
+        frame_buffer_t *const  in_out_frame_buffer )
+{
+    errnum_t  e;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= alloc_VRAM_stack_sub( &self->stack_pointer_of_VRAM,  self->over_of_VRAM,
+                             in_out_frame_buffer );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   R_WINDOW_SURFACES_FreeOffscreenStack
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+errnum_t  R_WINDOW_SURFACES_FreeOffscreenStack( window_surfaces_t *const  self,
+        const frame_buffer_t *const  frame_buffer )
+{
+    errnum_t  e;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= free_VRAM_stack_sub( &self->stack_pointer_of_VRAM, frame_buffer,
+                            self->start_of_VRAM );
+    IF(e!=0) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_DoMessageLoop
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_DoMessageLoop( window_surfaces_t *self )
+{
+    R_UNREFERENCED_VARIABLE( self );
+
+    R_OSPL_Delay( 2000 );
+
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_WINDOW_SURFACES_AccessLayerAttributes
+************************************************************************/
+errnum_t  R_WINDOW_SURFACES_AccessLayerAttributes( window_surfaces_t *self,
+        layer_attributes_t *in_out_Attributes )
+{
+    errnum_t         e;
+    vdc5_error_t     error_vdc;
+    window_surfaces_vdc5_layer_t  *layer = NULL;
+
+    if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_ID ) ) {
+        e= window_surfaces_t__get_layer( self, in_out_Attributes->id, &layer );
+        IF(e) {
+            goto fin;
+        }
+    }
+
+    ASSERT_R( IS_ALL_BITS_NOT_SET( in_out_Attributes->access, ~ACCESS_ALL_MASK ),  e=E_OTHERS; goto fin );
+
+
+    if ( in_out_Attributes->flags & F_LAYER_LAYER_COLOR ) {
+        vdc5_output_t  output;
+        vdc5_read_t    read;
+        r8g8b8a8_t     previous_layer_color = { {0,0,0,0} };
+        /* Avoid Warning: C4017W: previous_layer_color may be used before being set */
+        enum { necessary_flags = F_LAYER_ID };
+
+
+        ASSERT_R( IS_ALL_BITS_SET( in_out_Attributes->flags, necessary_flags ),
+                  e=E_OTHERS; goto fin );
+        ASSERT_R( IS_ALL_BITS_NOT_SET( in_out_Attributes->access, ~(ACCESS_READ | ACCESS_WRITE) ),
+                  e=E_OTHERS; goto fin );
+
+
+        if ( IS_BIT_SET( in_out_Attributes->access, ACCESS_READ ) ) {
+            previous_layer_color = layer->layer_color;
+        }
+
+
+        if ( IS_BIT_SET( in_out_Attributes->access, ACCESS_WRITE ) ) {
+
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_LAYER_COLOR ) ) {
+
+                /* Set "output.bg_color" to "R_VDC5_DisplayOutput" */
+                output.tcon_half        = (uint16_t)GS_LCD_CHn_TCON_HALF;  /* TCON reference timing, 1/2fH timing */
+                output.tcon_offset      = (uint16_t)GS_LCD_CHn_TCON_OFFSET;/* TCON reference timing, offset Hsync signal timing */
+                GRAPHICS_SetLcdTconSettings( self->screen_channel, output.outctrl );
+                output.outcnt_lcd_edge  = GS_LCD_CHn_OUT_EDGE;          /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+                output.out_endian_on    = VDC5_OFF;                     /* Bit endian change ON/OFF control */
+                output.out_swap_on      = VDC5_OFF;                     /* B/R signal swap ON/OFF control */
+                output.out_format       = GS_LCD_CHn_OUT_FORMAT;        /* LCD output format select */
+                output.out_frq_sel      = VDC5_LCD_PARALLEL_CLKFRQ_1;   /* Clock frequency control */
+                output.out_dir_sel      = VDC5_LCD_SERIAL_SCAN_FORWARD; /* Scan direction select */
+                output.out_phase        = VDC5_LCD_SERIAL_CLKPHASE_0;   /* Clock phase adjustment */
+                output.bg_color         =
+                    ( in_out_Attributes->layer_color.u.Red << 16 ) |
+                    ( in_out_Attributes->layer_color.u.Green << 8 ) |
+                    ( in_out_Attributes->layer_color.u.Blue << 0 );  /* 24-bit RGB color format */
+
+                error_vdc = R_VDC5_DisplayOutput( self->screen_channel, &output );
+                IF ( error_vdc != VDC5_OK ) {
+                    e = E_OTHERS;
+                    goto fin;
+                }
+
+
+                /* Update ReadDataControl */
+
+                /* Release */
+                if ( layer->is_data_control ) {
+                    error_vdc = R_VDC5_StopProcess( self->screen_channel, layer->data_control_ID );
+                    IF ( error_vdc != VDC5_OK ) {
+                        R_NOOP();
+                    }
+                    error_vdc = R_VDC5_ReleaseDataControl( self->screen_channel, layer->data_control_ID );
+                    IF ( error_vdc != VDC5_OK ) {
+                        e=E_OTHERS;
+                        goto fin;
+                    }
+                    layer->is_data_control = false;
+                }
+
+                /* Read data parameter : These values are dummy */
+                read.gr_ln_off_dir  = VDC5_GR_LN_OFF_DIR_INC;   /* Line offset address direction of the frame buffer */
+                read.gr_flm_sel     = VDC5_GR_FLM_SEL_FLM_NUM;  /* Selects a frame buffer address setting signal */
+                read.gr_imr_flm_inv = VDC5_OFF;                 /* Sets the frame buffer number for distortion correction */
+                read.gr_bst_md      = VDC5_BST_MD_32BYTE;       /* Frame buffer burst transfer mode */
+                read.gr_base        = (void *) &read;           /* Dummy, Frame buffer base address */
+                read.gr_ln_off      = 3200;                     /* Dummy, Frame buffer line offset address */
+                read.width_read_fb  = NULL;                     /* width of the image read from frame buffer */
+                read.adj_sel        = VDC5_OFF;                 /* Measures to decrease the influence
+				                                                   by folding pixels/lines (ON/OFF) */
+                read.gr_format      = VDC5_GR_FORMAT_RGB888;    /* Graphics format of the frame buffer read signal */
+                read.gr_ycc_swap    = VDC5_GR_YCCSWAP_Y1CRY0CB; /* Controls swapping of data read from buffer
+				                                                   in the YCbCr422 format */
+                read.gr_rdswa       = VDC5_WR_RD_WRSWA_32BIT;   /* for 32 bit format */
+
+                /* Set bakcground color area */
+                read.gr_grc.hs      = GS_LCD_CHn_DISP_HS;
+                read.gr_grc.hw      = (uint16_t) GS_LCD_CHn_DISP_HW;
+                read.gr_grc.vs      = GS_LCD_CHn_DISP_VS;
+                if ( GS_BUFFER_HEIGHT < GS_LCD_CHn_DISP_VW ) {
+                    read.gr_grc.vw      = (uint16_t) GS_BUFFER_HEIGHT;
+                } else {
+                    read.gr_grc.vw      = GS_LCD_CHn_DISP_VW;
+                }
+
+                /* Start to read again */
+                error_vdc = R_VDC5_ReadDataControl( self->screen_channel, layer->data_control_ID, &read );
+                IF ( error_vdc != VDC5_OK ) {
+                    e = E_OTHERS;
+                    goto fin;
+                }
+                layer->is_data_control = true;
+            }
+
+
+            /* Set graphics display mode */
+            {
+                vdc5_start_t  start;
+
+                start.gr_disp_sel = self->vdc5_disp_sel_array;
+                error_vdc = R_VDC5_StartProcess( self->screen_channel, VDC5_LAYER_ID_ALL, &start );
+                IF ( error_vdc != VDC5_OK ) {
+                    e = E_OTHERS;
+                    goto fin;
+                }
+            }
+        }
+
+        if ( IS_BIT_SET( in_out_Attributes->access, ACCESS_READ ) ) {
+            in_out_Attributes->layer_color = previous_layer_color;
+        }
+    }
+
+
+    /* Set window position */
+    {
+        enum { flags_of_window_position =
+                   F_LAYER_X | F_LAYER_Y | F_LAYER_WIDTH | F_LAYER_HEIGHT |
+                   F_LAYER_OFFSET_X | F_LAYER_OFFSET_Y
+             };
+
+        if ( IS_ANY_BITS_SET( in_out_Attributes->flags, flags_of_window_position )  &&
+                IS_BIT_SET( in_out_Attributes->access, ACCESS_WRITE ) ) {
+            vdc5_read_chg_t          change;
+            vdc5_width_read_fb_t     change_source_rectangle;
+            vdc5_period_rect_t       change_destination_rectangle;
+            gs_frame_width_height_t  source_frame;
+            gs_frame_width_height_t  destination_frame;
+            gs_rectangle_t           source_rectangle;
+            gs_rectangle_t           destination_rectangle;
+            frame_buffer_t          *frame;
+            bool_t                   is_interlace;
+            bool_t                   is_solid_color;
+            bool_t                   is_show = true;
+            window_surfaces_attribute_t  *attribute = NULL;
+            /* NULL is for avoiding warning C417W of mbed cloud compiler */
+
+
+            ASSERT_R( IS_ALL_BITS_SET( in_out_Attributes->flags, F_LAYER_ID ), e=E_OTHERS; goto fin );
+
+            e= window_surfaces_t__get_attribute( self, in_out_Attributes->id, &attribute );
+            IF(e) {
+                goto fin;
+            }
+
+            is_interlace = ( self->background_format == BACKGROUND_FORMAT_VIDEO_INTERLACE  &&
+                             in_out_Attributes->id == -1 );
+
+            is_solid_color = ( self->background_format == BACKGROUND_FORMAT_SOLID_COLOR  &&
+                               in_out_Attributes->id == -1 );
+
+            change.gr_base = NULL;
+            change.width_read_fb = NULL;
+            change.gr_grc = NULL;
+            change.gr_disp_sel = NULL;
+
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_X ) ) {
+                attribute->X = in_out_Attributes->x;
+                change.gr_grc = &change_destination_rectangle;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_Y ) ) {
+                attribute->Y = in_out_Attributes->y;
+                change.gr_grc = &change_destination_rectangle;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_WIDTH ) ) {
+                attribute->Width = in_out_Attributes->width;
+                change.gr_grc = &change_destination_rectangle;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_HEIGHT ) ) {
+                attribute->Height = in_out_Attributes->height;
+                change.gr_grc = &change_destination_rectangle;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_OFFSET_X ) ) {
+                attribute->OffsetX = in_out_Attributes->offset_x;
+                change.gr_grc = &change_destination_rectangle;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_OFFSET_Y ) ) {
+                attribute->OffsetY = in_out_Attributes->offset_y;
+                change.gr_grc = &change_destination_rectangle;
+            }
+
+
+            /* Call "GS_ToInFrame" */
+            if ( is_solid_color ) {
+                e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, 0, &frame );
+                IF(e) {
+                    goto fin;
+                }
+            } else {
+                e= R_WINDOW_SURFACES_GetLayerFrameBuffer( self, in_out_Attributes->id, &frame );
+                IF(e) {
+                    goto fin;
+                }
+            }
+            source_frame.Width  = frame->width;
+            source_frame.Height = frame->height;
+            destination_frame.Width  = frame->width;
+            destination_frame.Height = frame->height;
+            source_rectangle.Left   = attribute->OffsetX;
+            source_rectangle.Top    = attribute->OffsetY;
+            source_rectangle.Right  = attribute->OffsetX + attribute->Width;
+            source_rectangle.Bottom = attribute->OffsetY + attribute->Height;
+            destination_rectangle.Left   = attribute->X;
+            destination_rectangle.Top    = attribute->Y;
+            destination_rectangle.Right  = attribute->X + attribute->Width;
+            destination_rectangle.Bottom = attribute->Y + attribute->Height;
+
+            e= GS_ToInFrame( &source_frame, &destination_frame,
+                             &source_rectangle, &destination_rectangle );
+            IF(e) {
+                goto fin;
+            }
+            if ( source_rectangle.Left > source_rectangle.Right ) {
+                is_show = false;
+            }
+
+
+            /* Call "R_VDC5_ChangeReadProcess" */
+            if ( is_show ) {
+                byte_t       *source_address;
+                int_fast32_t  offset_byte;
+
+                ASSERT_R( ! is_solid_color,  e=E_OTHERS; goto fin );
+
+                if ( is_interlace ) {
+                    source_address = frame->buffer_address[0];
+                    offset_byte = ( source_rectangle.Top / 2 ) * frame->stride;
+                } else {
+                    source_address = frame->buffer_address[ frame->show_buffer_index ];
+                    offset_byte = source_rectangle.Top * frame->stride;
+                }
+                offset_byte += source_rectangle.Left * frame->byte_per_pixel;
+                ASSERT_R( R_BYTE_PER_PIXEL_IsInteger( frame->byte_per_pixel ),
+                          e=E_OTHERS; goto fin );
+                attribute->OffsetByte = offset_byte;
+
+                change.gr_base = source_address + attribute->OffsetByte;
+            }
+            if ( change.gr_grc != NULL ) {
+                change_destination_rectangle.hs = destination_rectangle.Left + GS_LCD_CHn_DISP_HS;
+                change_destination_rectangle.vs = destination_rectangle.Top  + GS_LCD_CHn_DISP_VS;
+                change_destination_rectangle.hw = destination_rectangle.Right - destination_rectangle.Left + 1;
+                change_destination_rectangle.vw = destination_rectangle.Bottom - destination_rectangle.Top + 1;
+
+                change.width_read_fb = &change_source_rectangle;
+                change_source_rectangle.in_hw = change_destination_rectangle.hw;
+                change_source_rectangle.in_vw = change_destination_rectangle.vw;
+
+                if ( is_interlace ) {
+                    change_source_rectangle.in_vw /= 2;
+                }
+            }
+
+            if ( change_source_rectangle.in_hw < 3  ||  change_source_rectangle.in_vw == 0 ) {
+                is_show = false;
+            }
+
+            if ( ! is_show ) {
+                change_destination_rectangle.hs = GS_LCD_CHn_DISP_HS - 2;  /* out of visible */
+                change_destination_rectangle.vs = GS_LCD_CHn_DISP_VS;
+                change_destination_rectangle.hw = 3;
+                change_destination_rectangle.vw = 1;
+                change_source_rectangle.in_hw = 3;
+                change_source_rectangle.in_vw = 1;
+                attribute->OffsetByte = GS_OFFSET_BYTE_NOT_SHOW;
+            }
+
+            error_vdc = R_VDC5_ChangeReadProcess(
+                            self->screen_channel, layer->data_control_ID, &change );
+            IF ( error_vdc != VDC5_OK ) {
+                e = E_OTHERS;
+                goto fin;
+            }
+        }
+        if ( IS_ANY_BITS_SET( in_out_Attributes->flags, flags_of_window_position )  &&
+                IS_BIT_SET( in_out_Attributes->access, ACCESS_READ ) ) {
+            window_surfaces_attribute_t  *attribute = NULL;
+            /* NULL is for avoiding warning C417W of mbed cloud compiler */
+
+            ASSERT_R( IS_ALL_BITS_SET( in_out_Attributes->flags, F_LAYER_ID ), e=E_OTHERS; goto fin );
+
+            e= window_surfaces_t__get_attribute( self, in_out_Attributes->id, &attribute );
+            IF(e) {
+                goto fin;
+            }
+
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_X ) ) {
+                in_out_Attributes->x = attribute->X;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_Y ) ) {
+                in_out_Attributes->y = attribute->Y;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_WIDTH ) ) {
+                in_out_Attributes->width = attribute->Width;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_HEIGHT ) ) {
+                in_out_Attributes->height = attribute->Height;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_OFFSET_X ) ) {
+                in_out_Attributes->offset_x = attribute->OffsetX;
+            }
+            if ( IS_BIT_SET( in_out_Attributes->flags, F_LAYER_OFFSET_Y ) ) {
+                in_out_Attributes->offset_y = attribute->OffsetY;
+            }
+        }
+    }
+
+
+    /* Call "R_VDC5_CLUT" */
+    {
+        enum { flags_of_CLUT = F_LAYER_CLUT | F_LAYER_CLUT_COUNT };
+
+        if ( IS_ANY_BITS_SET( in_out_Attributes->flags, flags_of_CLUT ) ) {
+            vdc5_clut_t  clut_data;
+            enum { necessary_flags = flags_of_CLUT | F_LAYER_ID };
+
+            ASSERT_R( IS_ALL_BITS_SET( in_out_Attributes->flags, necessary_flags ),
+                      e=E_OTHERS; goto fin );
+            ASSERT_R( IS_ANY_BITS_NOT_SET(
+                          in_out_Attributes->access,  ~ (bit_flags_fast32_t) ACCESS_WRITE ),
+                      e=E_OTHERS; goto fin );
+
+            clut_data.color_num = in_out_Attributes->CLUT_count;
+            clut_data.clut = (uint32_t *)( in_out_Attributes->CLUT );
+            error_vdc = R_VDC5_CLUT( self->screen_channel, layer->data_control_ID, &clut_data );
+            IF( error_vdc != VDC5_OK ) {
+                e=E_OTHERS;
+                goto fin;
+            }
+        }
+    }
+
+    IF( IS_ANY_BITS_SET( in_out_Attributes->flags,
+                         ~( F_LAYER_ID | F_LAYER_LAYER_COLOR | F_LAYER_CLUT_COUNT | F_LAYER_CLUT |
+                            F_LAYER_X | F_LAYER_Y | F_LAYER_WIDTH | F_LAYER_HEIGHT |
+                            F_LAYER_OFFSET_X | F_LAYER_OFFSET_Y ) ) ) {
+        e=E_LIMITATION;
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/* Section: Global */
+/**
+* @brief   Put "SourceRect" and "DestinationRect" into the frame.
+*
+* @param   SourceFrameBuffer gs_frame_width_height_t
+* @param   DestinationFrameBuffer gs_frame_width_height_t
+* @param   SourceRect gs_rectangle_t
+* @param   DestinationRect gs_rectangle_t
+* @return  Error Code. 0=No Error.
+*
+* @par Description
+*    - If out of frame then "SourceRect - >Left > SourceRect->Right".
+*/
+errnum_t  GS_ToInFrame(
+    gs_frame_width_height_t *SourceFrameBuffer,
+    gs_frame_width_height_t *DestinationFrameBuffer,
+    gs_rectangle_t *SourceRect,
+    gs_rectangle_t *DestinationRect )
+{
+    errnum_t  e;
+    int  src_top,  src_bottom,  dst_top,  dst_bottom;  /* top down coord */
+    int  diff;
+
+
+    /* fast culling by out of frame buffer horizontal */
+    if (      SourceRect->Left >= SourceFrameBuffer->Width ||
+              DestinationRect->Left >= DestinationFrameBuffer->Width ||
+              SourceRect->Right < 0 ||
+              DestinationRect->Right < 0 ) {
+        SourceRect->Right = SourceRect->Left - 1;  /* out of frame */
+        e = 0;
+        goto fin;
+    }
+
+
+    /* set "src_top", "src_bottom", "dst_top", "dst_bottom" */
+    src_top    = SourceRect->Top;
+    src_bottom = SourceRect->Bottom;
+    dst_top    = DestinationRect->Top;
+    dst_bottom = DestinationRect->Bottom;
+
+
+    /* fast culling by out of frame buffer vertical */
+    if ( src_top >= SourceFrameBuffer->Height ||
+            dst_top >= DestinationFrameBuffer->Height ||
+            src_bottom < 0 ||
+            dst_bottom < 0 ) {
+        SourceRect->Right = SourceRect->Left - 1;  /* out of frame */
+        e = 0;
+        goto fin;
+    }
+
+
+    /* set top >= 0 */
+    if ( src_top < 0 ) {
+        dst_top += - src_top;
+        src_top = 0;
+    }
+
+    if ( dst_top < 0 ) {
+        src_top += - dst_top;
+        dst_top = 0;
+    }
+
+
+    /* set bottom < frame height */
+    if ( src_bottom >= SourceFrameBuffer->Height ) {
+        diff = src_bottom - SourceFrameBuffer->Height + 1;
+        src_bottom -= diff;
+        dst_bottom -= diff;
+    }
+
+    if ( dst_bottom >= DestinationFrameBuffer->Height ) {
+        diff = dst_bottom - DestinationFrameBuffer->Height + 1;
+        src_bottom -= diff;
+        dst_bottom -= diff;
+    }
+
+
+    /* culling by out of frame buffer vertical for modified top and bottom */
+    if ( src_top < 0 ||
+            dst_top < 0 ||
+            src_bottom >= SourceFrameBuffer->Height ||
+            dst_bottom >= DestinationFrameBuffer->Height ) {
+        SourceRect->Right = SourceRect->Left - 1;  /* out of frame */
+        e = 0;
+        goto fin;
+    }
+
+
+    /* return from "src_top", "src_bottom", "dst_top", "dst_bottom" */
+    SourceRect->Top    = src_top;
+    SourceRect->Bottom = src_bottom;
+    DestinationRect->Top    = dst_top;
+    DestinationRect->Bottom = dst_bottom;
+
+
+    /* set left >= 0 */
+    if ( SourceRect->Left < 0 ) {
+        DestinationRect->Left += - SourceRect->Left;
+        SourceRect->Left = 0;
+    }
+
+    if ( DestinationRect->Left < 0 ) {
+        SourceRect->Left += - DestinationRect->Left;
+        DestinationRect->Left = 0;
+    }
+
+
+    /* set right < frame width */
+    if ( SourceRect->Right >= SourceFrameBuffer->Width ) {
+        diff = SourceRect->Right - SourceFrameBuffer->Width + 1;
+        SourceRect->Right      -= diff;
+        DestinationRect->Right -= diff;
+    }
+
+    if ( DestinationRect->Right >= DestinationFrameBuffer->Width ) {
+        diff = DestinationRect->Right - DestinationFrameBuffer->Width + 1;
+        SourceRect->Right      -= diff;
+        DestinationRect->Right -= diff;
+    }
+
+
+    /* culling by out of frame buffer horizontal for modified top and bottom */
+    if (      SourceRect->Left >= SourceFrameBuffer->Width ||
+              DestinationRect->Left >= DestinationFrameBuffer->Width ||
+              SourceRect->Right < 0 ||
+              DestinationRect->Right < 0 ) {
+        SourceRect->Right = SourceRect->Left - 1;  /* out of frame */
+        e = 0;
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Class: vram_ex_stack_t
+************************************************************************/
+
+/***********************************************************************
+* Implement: R_VRAM_EX_STACK_Initialize
+************************************************************************/
+errnum_t  R_VRAM_EX_STACK_Initialize( vram_ex_stack_t *self, void *NullConfig )
+{
+    errnum_t  e;
+    uint8_t  *address;
+    size_t    size;
+
+    R_UNREFERENCED_VARIABLE( NullConfig );
+
+    e= R_EXRAM_GetBigMemory( &address, &size );
+    IF(e) {
+        goto fin;
+    }
+
+    self->Start = address;
+    self->Over  = address + size;
+    self->StackPointer = self->Start;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_VRAM_EX_STACK_Alloc
+************************************************************************/
+errnum_t  R_VRAM_EX_STACK_Alloc( vram_ex_stack_t *self, frame_buffer_t *in_out_FrameBuffer )
+{
+    return  alloc_VRAM_stack_sub( &self->StackPointer, self->Over, in_out_FrameBuffer );
+}
+
+
+/***********************************************************************
+* Implement: R_VRAM_EX_STACK_Free
+************************************************************************/
+errnum_t  R_VRAM_EX_STACK_Free( vram_ex_stack_t *self, frame_buffer_t *frame_buffer )
+{
+    return  free_VRAM_stack_sub( &self->StackPointer, frame_buffer, self->Start );
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/RGA/src/window_surfaces_cpp.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,300 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  window_surfaces_cpp.cpp
+* @brief   $Module: CLibCommon $ $PublicVersion: 1.20 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* - Description: Window Surfaces for mbed style C++ API
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "window_surfaces.hpp"
+#include  "window_surfaces.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define  GS_DEFAULT_INT_VALUE  0x7FFFFFFF
+#define  GS_DEFAULT_HEIGHT  -1
+#define  GS_DEFAULT_CLEAR_COLOR  0x00000100
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* ClassImplement: WindowSurfacesClass
+************************************************************************/
+
+/***********************************************************************
+* Implement: WindowSurfacesClass
+************************************************************************/
+WindowSurfacesClass::WindowSurfacesClass()
+{
+    this->_self = NULL;
+}
+
+
+/***********************************************************************
+* Implement: ~WindowSurfacesClass
+************************************************************************/
+WindowSurfacesClass::~WindowSurfacesClass()
+{
+    this->destroy();
+}
+
+
+/***********************************************************************
+* Implement: initialize
+************************************************************************/
+errnum_t  WindowSurfacesClass::initialize( WindowSurfacesConfigClass &in_out_config )
+{
+    this->_self = new  window_surfaces_t;
+    ASSERT_R( this->_self != NULL,  return  E_FEW_MEMORY );
+
+    in_out_config.flags =
+        F_WINDOW_SURFACES_PIXEL_FORMAT |
+        F_WINDOW_SURFACES_LAYER_COUNT |
+        F_WINDOW_SURFACES_BACKGROUND_COLOR |
+        F_WINDOW_SURFACES_BUFFER_HEIGHT;
+
+    if ( in_out_config.buffer_height == GS_DEFAULT_HEIGHT ) {
+        in_out_config.flags &= ~F_WINDOW_SURFACES_BUFFER_HEIGHT;
+    }
+    if ( in_out_config.background_color.Value == GS_DEFAULT_CLEAR_COLOR ) {
+        in_out_config.flags &= ~F_WINDOW_SURFACES_BACKGROUND_COLOR;
+    }
+
+    R_WINDOW_SURFACES_InitConst( this->_self );
+
+    return  R_WINDOW_SURFACES_Initialize( this->_self,
+                                          (window_surfaces_config_t *) &in_out_config );
+}
+
+
+/***********************************************************************
+* Implement: destroy
+************************************************************************/
+void  WindowSurfacesClass::destroy()
+{
+    if ( this->_self != NULL ) {
+        errnum_t  e = R_WINDOW_SURFACES_Finalize( this->_self,  0 );
+        ASSERT_R( e == 0,  R_NOOP() );
+    }
+}
+
+
+/***********************************************************************
+* Implement: get_layer_frame_buffer
+************************************************************************/
+errnum_t  WindowSurfacesClass::get_layer_frame_buffer( int_fast32_t const  layer_num,  frame_buffer_t **const  out_frame_buffer )
+{
+    return  R_WINDOW_SURFACES_GetLayerFrameBuffer( this->_self,  layer_num,  out_frame_buffer );
+}
+
+
+/***********************************************************************
+* Implement: swap_buffers
+************************************************************************/
+#ifdef  IS_WINDOW_SURFACES_EX
+errnum_t  WindowSurfacesClass::swap_buffers( int_fast32_t const  layer_num,  Canvas2D_ContextClass  &context )
+{
+    return  R_WINDOW_SURFACES_SwapBuffers( this->_self,  layer_num,  context.c_LanguageContext );
+}
+#else
+errnum_t  WindowSurfacesClass::swap_buffers( int_fast32_t const  layer_num,  const void *const  null_context )
+{
+    return  R_WINDOW_SURFACES_SwapBuffers( this->_self,  layer_num,  null_context );
+}
+#endif
+
+
+/***********************************************************************
+* Implement: swap_buffers_start
+************************************************************************/
+errnum_t  WindowSurfacesClass::swap_buffers_start( int_fast32_t const  layer_num,  r_ospl_async_t *async )
+{
+    return  R_WINDOW_SURFACES_SwapBuffersStart( this->_self,  layer_num,  async );
+}
+
+
+/***********************************************************************
+* Implement: wait_for_v_sync
+************************************************************************/
+errnum_t  WindowSurfacesClass::wait_for_v_sync( int_fast32_t const  swap_interval,  bool_t const  is_1_v_sync_at_minimum )
+{
+    return  R_WINDOW_SURFACES_WaitForVSync( this->_self,  swap_interval,  is_1_v_sync_at_minimum );
+}
+
+
+/***********************************************************************
+* Implement: alloc_offscreen_stack
+************************************************************************/
+errnum_t  WindowSurfacesClass::alloc_offscreen_stack( frame_buffer_t *const  in_out_frame_buffer )
+{
+    return  R_WINDOW_SURFACES_AllocOffscreenStack( this->_self,  in_out_frame_buffer );
+}
+
+
+/***********************************************************************
+* Implement: free_offscreen_stack
+************************************************************************/
+errnum_t  WindowSurfacesClass::free_offscreen_stack( const frame_buffer_t *const  frame_buffer )
+{
+    return  R_WINDOW_SURFACES_FreeOffscreenStack( this->_self,  frame_buffer );
+}
+
+
+/***********************************************************************
+* Implement: do_message_loop
+************************************************************************/
+#ifdef  IS_WINDOW_SURFACES_EX
+errnum_t  WindowSurfacesClass::do_message_loop()
+{
+    return  R_WINDOW_SURFACES_DoMessageLoop( this->_self );
+}
+#endif
+
+
+/***********************************************************************
+* Implement: access_layer_attributes
+************************************************************************/
+#ifdef  IS_WINDOW_SURFACES_EX
+errnum_t  WindowSurfacesClass::access_layer_attributes( LayerAttributes &in_out_Attributes )
+{
+    in_out_Attributes.flags =
+        F_LAYER_ID |
+        F_LAYER_PRIORITY |
+        F_LAYER_X |
+        F_LAYER_Y |
+        F_LAYER_WIDTH |
+        F_LAYER_HEIGHT |
+        F_LAYER_OFFSET_X |
+        F_LAYER_OFFSET_Y |
+        F_LAYER_CLUT |
+        F_LAYER_CLUT_COUNT;
+
+    if ( in_out_Attributes.id == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_ID;
+    }
+    if ( in_out_Attributes.priority == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_PRIORITY;
+    }
+    if ( in_out_Attributes.x == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_X;
+    }
+    if ( in_out_Attributes.y == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_Y;
+    }
+    if ( in_out_Attributes.width == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_WIDTH;
+    }
+    if ( in_out_Attributes.height == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_HEIGHT;
+    }
+    if ( in_out_Attributes.offset_x == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_OFFSET_X;
+    }
+    if ( in_out_Attributes.offset_y == GS_DEFAULT_INT_VALUE ) {
+        in_out_Attributes.flags &= ~F_LAYER_OFFSET_Y;
+    }
+    if ( in_out_Attributes.CLUT == NULL ) {
+        in_out_Attributes.flags &= ~F_LAYER_CLUT;
+    }
+    if ( in_out_Attributes.CLUT_count == 0 ) {
+        in_out_Attributes.flags &= ~F_LAYER_CLUT_COUNT;
+    }
+
+    return  R_WINDOW_SURFACES_AccessLayerAttributes( this->_self,
+            (layer_attributes_t *) &in_out_Attributes );
+}
+#endif
+
+
+/***********************************************************************
+* ClassImplement: WindowSurfacesConfigClass
+************************************************************************/
+
+/***********************************************************************
+* Implement: WindowSurfacesConfigClass
+************************************************************************/
+WindowSurfacesConfigClass::WindowSurfacesConfigClass()
+{
+    this->flags = 0;
+    this->pixel_format = PIXEL_FORMAT_ARGB8888;
+    this->layer_count = 1;
+    this->buffer_height = GS_DEFAULT_HEIGHT;
+    this->background_color.Value = GS_DEFAULT_CLEAR_COLOR;
+}
+
+
+/***********************************************************************
+* ClassImplement: LayerAttributes
+************************************************************************/
+
+/***********************************************************************
+* Implement: LayerAttributes
+************************************************************************/
+#ifdef  IS_WINDOW_SURFACES_EX
+LayerAttributes::LayerAttributes()
+{
+    this->access = ACCESS_READ;
+    this->flags = 0;
+    this->id       = GS_DEFAULT_INT_VALUE;
+    this->priority = GS_DEFAULT_INT_VALUE;
+    this->is_show = false;
+    this->is_color_key = false;
+    this->color_key.Value = GS_DEFAULT_CLEAR_COLOR;
+    this->layer_color.Value = 0;
+    this->x        = GS_DEFAULT_INT_VALUE;
+    this->y        = GS_DEFAULT_INT_VALUE;
+    this->width    = GS_DEFAULT_INT_VALUE;
+    this->height   = GS_DEFAULT_INT_VALUE;
+    this->offset_x = GS_DEFAULT_INT_VALUE;
+    this->offset_y = GS_DEFAULT_INT_VALUE;
+    this->CLUT     = NULL;
+    this->CLUT_count = 0;
+}
+#endif
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/common/inc/clib_drivers.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,82 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_drivers.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code for drivers and more.
+*/
+
+#ifndef  CLIB_DRIVERS_H
+#define  CLIB_DRIVERS_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+#include  "clib_drivers_typedef.h"
+
+/* for Inline Functions */
+#include  "r_multi_compiler.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+errnum_t  R_int32_t_to_int8_t( int32_t input, int8_t *output );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+/* Inline Functions */
+#include  "clib_drivers_inline.h"
+
+#endif  /* CLIB_DRIVERS_H */
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/common/inc/clib_drivers_config.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,128 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_drivers_config.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code for drivers and more.
+*/
+
+#ifndef  CLIB_DRIVERS_CONFIG_H
+#define  CLIB_DRIVERS_CONFIG_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  IS_SUPPORT_SAME_TYPEDEF
+* @brief  Whether compiler suppots duplicated same typedef.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_SUPPORT_SAME_TYPEDEF  1
+
+
+/**
+* @def  LIB_STATIC
+* @brief  Public library is complied by set "LIB_STATIC" static.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#ifndef LIB_STATIC
+#define LIB_STATIC
+#endif
+
+
+/**
+* @def  static_release
+* @brief  Hide if release version.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#ifndef R_OSPL_NDEBUG
+#define  static_release  static
+#else
+#define  static_release
+#endif
+
+
+/***********************************************************************
+* Macros: BYTE_ENDIAN
+*    BYTE_ENDIAN
+*
+*    : BYTE_LITTLE_ENDIAN - 1
+*    : BYTE_BIG_ENDIAN    - 2
+************************************************************************/
+#define  BYTE_ENDIAN           BYTE_LITTLE_ENDIAN
+#define  BYTE_LITTLE_ENDIAN    1
+#define  BYTE_BIG_ENDIAN       2
+
+
+/***********************************************************************
+* Macros: BIT_FIELD_ENDIAN
+*    BIT_FIELD_ENDIAN
+*
+*    : BIT_FIELD_LITTLE_ENDIAN - 1
+*    : BIT_FIELD_BIG_ENDIAN    - 2
+************************************************************************/
+#define  BIT_FIELD_ENDIAN           BIT_FIELD_LITTLE_ENDIAN
+#define  BIT_FIELD_LITTLE_ENDIAN    1
+#define  BIT_FIELD_BIG_ENDIAN       2
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* CLIB_DRIVERS_CONFIG_H */
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/common/inc/clib_drivers_inline.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,447 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_drivers_inline.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code for drivers and more.
+*/
+
+#ifndef  CLIB_DRIVERS_INLINE_H
+#define  CLIB_DRIVERS_INLINE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* in clib_drivers_typedef.h */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/**
+* @brief   Cast with range check
+*
+* @param   input Input value
+* @param   output Output value
+* @return  Error Code. 0=No Error.
+*/
+INLINE errnum_t  R_int_t_to_int8_t( int_t input, int8_t *output )
+{
+    return  R_int32_t_to_int8_t( input, output );
+}
+
+
+/**
+* @brief   Fast mod operation
+*
+* @param   value Left operand
+* @return  value % N
+*
+* @par Description
+* - This is shared description of
+*   R_Mod_2s, R_Mod_4s, R_Mod_8s, R_Mod_16s, R_Mod_32s, R_Mod_64s,
+*   R_Mod_2u, R_Mod_4u, R_Mod_8u, R_Mod_16u, R_Mod_32u, R_Mod_64u.
+* - Porting layer of fast % operator.
+* - MISRA & IPA SEC confirmed version.
+* - Minus value is expected 2's complement.
+* - Not same C99 % operator.
+*   - Sample: R_Mod_4s( - 7 ) == +1.  Sample: -7 % 4 == -3
+*/
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_2s( int_fast32_t const  value )
+{
+    enum { mask = 1 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_4s( int_fast32_t const  value )
+{
+    enum { mask = 3 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_8s( int_fast32_t const  value )
+{
+    enum { mask = 7 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_16s( int_fast32_t const  value )
+{
+    enum { mask = 15 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_32s( int_fast32_t const  value )
+{
+    enum { mask = 31 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Mod_64s( int_fast32_t const  value )
+{
+    enum { mask = 63 };
+    return  ((int_fast32_t)((uint_fast32_t)(value) & mask));
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_2u( uint_fast32_t const  value )
+{
+    return  ((value) & 1u);
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_4u( uint_fast32_t const  value )
+{
+    return  ((value) & 3u);
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_8u( uint_fast32_t const  value )
+{
+    return  ((value) & 7u);
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_16u( uint_fast32_t const  value )
+{
+    return  ((value) & 15u);
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_32u( uint_fast32_t const  value )
+{
+    return  ((value) & 31u);
+}
+
+
+/**
+* @brief   Fast mod operation. See <R_Mod_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Mod_64u( uint_fast32_t const  value )
+{
+    return  ((value) & 63u);
+}
+
+
+/**
+* @brief   Fast ceil operation
+*
+* @param   value Left operand
+* @return  Ceil( value / N )
+*
+* @par Description
+* - This is shared description of
+*   R_Ceil_2s, R_Ceil_4s, R_Ceil_8s, R_Ceil_16s, R_Ceil_32s, R_Ceil_64s,
+*   R_Ceil_2u, R_Ceil_4u, R_Ceil_8u, R_Ceil_16u, R_Ceil_32u, R_Ceil_64u.
+* - Porting layer of fast ceil operation.
+* - Function version is confirmed with MISRA & IPA SEC.
+*/
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_2s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 1;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_4s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 3;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_8s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 7;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_16s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 15;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_32s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 31;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE int_fast32_t  R_Ceil_64s( int_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 63;
+    return  ((int_fast32_t)((uint_fast32_t)((value)+mask)&~mask));
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_2u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 1;
+    return  (((value)+mask)&~mask);
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_4u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 3;
+    return  (((value)+mask)&~mask);
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_8u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 7;
+    return  (((value)+mask)&~mask);
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_16u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 15;
+    return  (((value)+mask)&~mask);
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_32u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 31;
+    return  (((value)+mask)&~mask);
+}
+
+
+/**
+* @brief   Fast ceil operation. See <R_Ceil_N>.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+INLINE uint_fast32_t  R_Ceil_64u( uint_fast32_t const  value )
+{
+    static const uint_fast32_t  mask = 63;
+    return  (((value)+mask)&~mask);
+}
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* CLIB_DRIVERS_INLINE_H */
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/common/inc/clib_drivers_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,207 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_drivers_typedef.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code for drivers and more.
+*/
+
+#ifndef  CLIB_DRIVERS_TYPEDEF_H
+#define  CLIB_DRIVERS_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @typedef  bool32_t
+* @brief  Boolean type in 32 bit variable. This is not C99.
+*/
+typedef  unsigned int    bool32_t;
+
+
+/**
+* @typedef  bool16_t
+* @brief  Boolean type in 16 bit variable. This is not C99.
+*/
+typedef  unsigned short  bool16_t;
+
+
+/**
+* @typedef  bool8_t
+* @brief  Boolean type in 8 bit variable. This is not C99.
+*/
+typedef  unsigned char   bool8_t;
+
+
+/**
+* @typedef  IntBoxType
+* @brief  IntBoxType
+*/
+typedef struct st_IntBoxType  IntBoxType;
+struct st_IntBoxType {
+    int  MinX;
+    int  MinY;
+    int  Width;
+    int  Height;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  DUMMY_INITIAL_VALUE
+* @brief  Avoids not right warning of not initialized.
+*
+* @par Description
+* - 0xDEDEDEDE means "not initialized".
+* - Disable VC++ warning C4701 : local variable may be used without having
+*   been initialized
+* - See @ref DUMMY_INITIAL_VALUE_8BIT, @ref DUMMY_INITIAL_VALUE_16BIT
+*/
+#ifndef  R_OSPL_NDEBUG
+#define  DUMMY_INITIAL_VALUE  0xDEDEDEDE
+#else
+enum { DUMMY_INITIAL_VALUE = 0 };
+#endif
+
+
+/**
+* @def  DUMMY_INITIAL_VALUE_8BIT
+* @brief  <DUMMY_INITIAL_VALUE> for 8 bit integer.
+*/
+#ifndef  R_OSPL_NDEBUG
+enum { DUMMY_INITIAL_VALUE_8BIT  = 0xDE };
+#else
+enum { DUMMY_INITIAL_VALUE_8BIT  = 0 };
+#endif
+
+
+/**
+* @def  DUMMY_INITIAL_VALUE_16BIT
+* @brief  <DUMMY_INITIAL_VALUE> for 16 bit integer.
+*/
+#ifndef  R_OSPL_NDEBUG
+enum { DUMMY_INITIAL_VALUE_16BIT = 0xDEDE };
+#else
+enum { DUMMY_INITIAL_VALUE_16BIT = 0 };
+#endif
+
+
+/**
+* @def  U8_255
+* @brief  Magic number of generally well known used.
+*    unsigned 8bit max value = UINT8_MAX
+*/
+#define  U8_255   255
+
+
+/**
+* @def  R_CEIL_2U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_2U( value )   (((value)+1)&~1)
+
+
+/**
+* @def  R_CEIL_4U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_4U( value )   (((value)+3)&~3)
+
+
+/**
+* @def  R_CEIL_8U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_8U( value )   (((value)+7)&~7)
+
+
+/**
+* @def  R_CEIL_16U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_16U( value )  (((value)+15)&~15)
+
+
+/**
+* @def  R_CEIL_32U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_32U( value )  (((value)+31)&~31)
+
+
+/**
+* @def  R_CEIL_64U
+* @brief  Fast ceil operation. Macro version. See <R_Ceil_N>.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_CEIL_64U( value )  (((value)+63)&~63)
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* CLIB_DRIVERS_TYPEDEF_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/common/inc/clib_registers.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,322 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_registers.h
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code for drivers and more.
+*/
+
+#ifndef  CLIB_REGISTERS_H
+#define  CLIB_REGISTERS_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_typedefs.h"
+#include  "r_ospl.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/******************************************************************************
+Inline Functions
+******************************************************************************/
+
+
+/**
+* @brief   CPG unit of RZ/A1H.
+*
+* @par Parameters
+*    None
+* @return  Pointer to CPG structure.
+*/
+INLINE struct st_cpg  *R_Get_CPG_Base(void) {
+    /* ->QAC 0306 */
+#if IODEFINE_H_VERSION >= 100
+    return  &CPG;
+#else
+    return  (struct st_cpg *) &CPG;
+#endif
+    /* <-QAC 0306 */
+}
+
+
+/***********************************************************************
+* Group: Register_Access
+************************************************************************/
+
+/**
+* @brief   Set a value to register bit field.
+*
+* @param   in_out_Register Address of register or variable
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @param   Value Writing value
+* @return  None.
+*
+* @par Description
+*    Bit width is got from "RegisterName".
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_SET_REGISTER_BIT_FIELD( \
+		in_out_Register, RegisterName, BitName, Value ) \
+	R_DRV_SET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
+		in_out_Register, RegisterName, BitName, Value, \
+		DRV__BIT_WIDTH__##RegisterName )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Set a value to register bit field with width parameter.
+*
+* @param   in_out_Register Address of register or variable
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @param   Value Writing value
+* @param   BitWidth BitWidth
+* @return  None.
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_SET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
+		in_out_Register, RegisterName, BitName, Value, BitWidth ) \
+	R_DRV_SET_REGISTER_BIT_FIELD_SUB0( \
+		in_out_Register, RegisterName##__##BitName, Value, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_SET_REGISTER_BIT_FIELD_SUB0( \
+		in_out_Register, RegisterBitName, Value, BitWidth ) \
+	R_DRV_SET_REGISTER_BIT_FIELD_SUB( \
+		in_out_Register, RegisterBitName, Value, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_SET_REGISTER_BIT_FIELD_SUB( \
+		in_out_Register, RegisterBitName, Value, BitWidth ) \
+	R_OSPL_SET_TO_##BitWidth##_BIT_REGISTER( \
+		(volatile uint##BitWidth##_t*)(in_out_Register), \
+		DRV__MASK##BitWidth##__##RegisterBitName, \
+		DRV__SHIFT__##RegisterBitName, \
+		(uint##BitWidth##_t)(Value) )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Get a value from register bit field.
+*
+* @param   RegisterValue Value of register or variable
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @return  Value of shifted bit field.
+*
+* @par Description
+*    Bit width is got from "RegisterName".
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_GET_REGISTER_BIT_FIELD( \
+		RegisterValue, RegisterName, BitName ) \
+	R_DRV_GET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
+		RegisterValue, RegisterName, BitName, \
+		DRV__BIT_WIDTH__##RegisterName )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Get a value from register bit field with width parameter.
+*
+* @param   RegisterValue Value of register or variable
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @param   BitWidth BitWidth
+* @return  Value of shifted bit field.
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_GET_REGISTER_BIT_FIELD_WITH_REG_WIDTH( \
+		RegisterValue, RegisterName, BitName, BitWidth ) \
+	R_DRV_GET_REGISTER_BIT_FIELD_SUB0( \
+		RegisterValue, RegisterName##__##BitName, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_GET_REGISTER_BIT_FIELD_SUB0( \
+		RegisterValue, RegisterBitName, BitWidth ) \
+	R_DRV_GET_REGISTER_BIT_FIELD_SUB( \
+		RegisterValue, RegisterBitName, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_GET_REGISTER_BIT_FIELD_SUB( \
+		RegisterValue, RegisterBitName, BitWidth ) \
+	R_OSPL_GET_FROM_##BitWidth##_BIT_REGISTER( \
+		(volatile const uint##BitWidth##_t*) &(RegisterValue), \
+		DRV__MASK##BitWidth##__##RegisterBitName, \
+		DRV__SHIFT__##RegisterBitName )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Returns whether specified value is overflowed from the bit field.
+*
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @param   Value Checking value
+* @return  Whether specified value is overflowed.
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_IS_OVERFLOW_BIT_FIELD( \
+		RegisterName, BitName, Value ) \
+	R_DRV_IS_OVERFLOW_BIT_FIELD_WITH_REG_WIDTH( \
+		RegisterName, BitName, Value, DRV__BIT_WIDTH__##RegisterName )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Returns whether specified value is overflowed from the bit field.
+*
+* @param   RegisterName Name of register
+* @param   BitName Name of bit
+* @param   Value Checking value
+* @param   BitWidth BitWidth
+* @return  Whether specified value is overflowed.
+*/
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "DRV__BIT_WIDTH__##RegisterName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_IS_OVERFLOW_BIT_FIELD_WITH_REG_WIDTH( \
+		RegisterName, BitName, Value, BitWidth ) \
+	R_DRV_IS_OVERFLOW_BIT_FIELD_SUB0( \
+		RegisterName##__##BitName, Value, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+/* ->MISRA 19.7 : Expand "RegisterName##__##BitName" macro */
+/* ->SEC M5.1.3 */
+#define  R_DRV_IS_OVERFLOW_BIT_FIELD_SUB0( \
+		RegisterBitName, Value, BitWidth ) \
+	R_DRV_IS_OVERFLOW_BIT_FIELD_SUB( \
+		RegisterBitName, Value, BitWidth )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+/* Sub macro */
+/* ->MISRA 19.12 */ /* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  R_DRV_IS_OVERFLOW_BIT_FIELD_SUB( \
+		RegisterBitName, Value, BitWidth ) \
+	R_DRV_IsOverflowBitField##BitWidth##_Sub( \
+		DRV__MASK##BitWidth##__##RegisterBitName, \
+		DRV__SHIFT__##RegisterBitName, \
+		Value )
+/* <-MISRA 19.12 */ /* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/* Sub function */
+/* : R_DRV_IsOverflowBitField32_Sub */
+/* : R_DRV_IsOverflowBitField16_Sub */
+/* : R_DRV_IsOverflowBitField8_Sub */
+INLINE bool_t  R_DRV_IsOverflowBitField32_Sub( uint32_t const  Mask,
+        int_fast32_t const  Shift,  uint32_t const  Value )
+{
+    return  ( ( (uint32_t)(Value) &
+                ~( (uint32_t)(Mask) >> (Shift) ) )
+              != 0u );
+}
+
+INLINE bool_t  R_DRV_IsOverflowBitField16_Sub( uint16_t const  Mask,
+        int_fast32_t const  Shift,  uint16_t const  Value )
+{
+    return  ( ( (uint_fast16_t)(Value) &
+                ~( (uint_fast16_t)(Mask) >> (Shift) ) )
+              != 0u );
+}
+
+INLINE bool_t  R_DRV_IsOverflowBitField8_Sub( uint8_t const  Mask,
+        int_fast32_t const  Shift, uint8_t const  Value )
+{
+    return  ( ( (uint_fast8_t)(Value) &
+                ~( (uint_fast8_t)(Mask) >> (Shift) ) )
+              != 0u );
+}
+
+
+/**
+* @def  CPG
+* @brief  CPG
+*/
+/* 0xFCFE0438 */
+
+#define  DRV__BIT_WIDTH__STBCR9  8
+
+enum { /*uint8_t */       DRV__MASK8__STBCR9__MSTP91 = 0x02 };  /* VDC5-0, LVDS */
+enum { /*uint8_t */       DRV__MASK8__STBCR9__MSTP90 = 0x01 };  /* VDC5-1 */
+
+enum { /* int_fast32_t */  DRV__SHIFT__STBCR9__MSTP91 =  1 };
+enum { /* int_fast32_t */  DRV__SHIFT__STBCR9__MSTP90 =  0 };
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif  /* CLIB_REGISTERS_H */
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/common/inc/clib_samples.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,78 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: clib_samples.h $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 40 $
+* $Date:: 2014-03-20 18:46:41 +0900#$
+* Description: Sample API
+*******************************************************************************/
+
+
+#ifndef  CLIB_SAMLES_H
+#define  CLIB_SAMLES_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl_typedef.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+    /******************************************************************************
+    Typedef definitions
+    ******************************************************************************/
+    /* In "clib_samples_typedef.h" */
+
+    /******************************************************************************
+    Macro definitions
+    ******************************************************************************/
+    /* In "clib_samples_typedef.h" */
+
+    /******************************************************************************
+    Variable Externs
+    ******************************************************************************/
+    /* In "clib_samples_typedef.h" */
+
+    /******************************************************************************
+    Functions Prototypes
+    ******************************************************************************/
+
+    errnum_t  R_Sample_GetBigMemory( uint8_t **const  out_Address,  size_t *const  out_Size );
+
+#if IS_VDC_SAMPLE_VRAM_USED
+    errnum_t  R_Sample_GetBigMemory_FromVDC_Sample( void * /*<type**>*/ out_Address, size_t *out_Size );
+#endif
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/common/inc/clib_samples_private.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,57 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: window_surfaces.h $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 47 $
+* $Date:: 2014-01-06 18:18:48 +0900#$
+* Description  : Sample API
+*******************************************************************************/
+
+#ifndef  CLIB_SAMPLES_PRIVATE_H
+#define  CLIB_SAMPLES_PRIVATE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+void  R_MEMORY_SECTION_GetMemory_ClibSamplesC( uint8_t **out_Address,  size_t *out_Size );
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/common/src/clib_drivers.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,170 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  clib_drivers.c
+* @brief   $Module: CLibCommon $ $PublicVersion: 0.90 $ (=CLIB_VERSION)
+* $Rev: 30 $
+* $Date:: 2014-02-13 21:21:47 +0900#$
+* - Description: Common code.
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "clib_drivers.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**
+* @brief   Cast with range check
+*
+* @param   input Input value
+* @param   output Output value
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_int32_t_to_int8_t( int32_t const  input, int8_t *const  output )
+{
+    errnum_t  e;
+
+    IF ( (input < INT8_MIN)  ||  (input > INT8_MAX) )  {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( output == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    *output = (int8_t) input;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**
+* @brief   Cast with range check
+*
+* @param   input Input value
+* @param   output Output value
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_int32_t_to_int16_t( int32_t input, int16_t *output )
+{
+    IF ( input < -32768  ||  input > 32767 ) {
+        return  E_OTHERS;
+    }
+
+    *output = (int16_t) input;
+    return  0;
+}
+
+
+/**
+* @brief   Cast with range check
+*
+* @param   input Input value
+* @param   output Output value
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_int32_t_to_uint8_t( int32_t input, uint8_t *output )
+{
+    IF ( input < 0  ||  input > 255 ) {
+        return  E_OTHERS;
+    }
+
+    *output = (uint8_t) input;
+    return  0;
+}
+
+
+/**
+* @brief   Returns whether specified value has 1 bit only 1.
+*
+* @param   Value Input value
+* @return  Returns whether specified value has 1 bit only 1.
+*/
+bool_t  Is1bitOnlyInt( uint32_t Value )
+{
+    if ( (Value & 0x0000FFFF) == 0 ) {
+        Value >>= 16;
+    }
+    if ( (Value & 0x000000FF) == 0 ) {
+        Value >>=  8;
+    }
+    if ( (Value & 0x0000000F) == 0 ) {
+        Value >>=  4;
+    }
+    if ( (Value & 0x00000003) == 0 ) {
+        Value >>=  2;
+    }
+    if ( (Value & 0x00000001) == 0 ) {
+        Value >>=  1;
+    }
+    return  ( Value == 1 );
+}
+
+
+/**
+* @brief   Get whether 2 "IntBoxType"s are same area.
+*
+* @param   in_BoxA A box
+* @param   in_BoxB Other box
+* @param   out_IsSame Whether 2 "IntBoxType"s are same area.
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  IntBoxType_isSame( const IntBoxType *in_BoxA, const IntBoxType *in_BoxB, bool_t *out_IsSame )
+{
+    *out_IsSame = (
+                      in_BoxA->MinX   == in_BoxB->MinX  &&
+                      in_BoxA->MinY   == in_BoxB->MinY  &&
+                      in_BoxA->Width  == in_BoxB->Width  &&
+                      in_BoxA->Height == in_BoxB->Height );
+
+    return  0;
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/common/src/clib_samples.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,105 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: clib_samples.c $
+* $Module: CLibCommon $ $PublicVersion: 1.00 $ (=CLIB_VERSION)
+* $Rev: 52 $
+* $Date:: 2014-03-20 18:41:05 +0900#$
+* Description: Sample functions
+*******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_typedefs.h"
+#include  "r_ospl.h"
+#include  "clib_samples.h"
+#if ! IS_VDC_SAMPLE_VRAM_USED
+#include  "clib_samples_private.h"
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: [R_Sample_GetBigMemory]
+* Description  :
+* Arguments    :
+* Return Value : Error code, 0=No error
+******************************************************************************/
+errnum_t  R_Sample_GetBigMemory( uint8_t **const  out_Address,  size_t *const  out_Size )
+{
+#if IS_VDC_SAMPLE_VRAM_USED
+    errnum_t          e;
+    static uint8_t   *address;
+    static size_t     memory_size;
+
+    IF_DQ( out_Address == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( out_Size    == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    if ( address == NULL ) {
+        e= R_Sample_GetBigMemory_FromVDC_Sample( &address, &memory_size );
+        IF(e!=0) {
+            goto fin;
+        }
+    }
+    *out_Address = address;
+    *out_Size    = memory_size;
+
+    e=0;
+fin:
+    return  e;
+#else
+    R_MEMORY_SECTION_GetMemory_ClibSamplesC( out_Address, out_Size );
+    return  0;
+#endif
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/config/Project_Config.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,74 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: Project_Config.h $
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+* Description  : This file is for drivers and applications
+******************************************************************************/
+
+#ifndef PROJECT_CONFIG_H
+#define PROJECT_CONFIG_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+/* This file must be included at first of source file */
+/* Include configuration header files of drivers and applications */
+/* The #include parameter must be not depended on include path for other projects */
+#include  "Project_Config_Sub.h"
+#include  "../ospl/inc/r_ospl_config.h"
+#include  "../common/inc/clib_drivers_config.h"
+#include  "../RGA/inc/RGA_Config.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_OSPL_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/config/Project_Config_Sub.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,125 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: Project_Config.h $
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+* Description  : This file is for drivers and applications
+******************************************************************************/
+
+#ifndef PROJECT_CONFIG_SUB_H
+#define PROJECT_CONFIG_SUB_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  IS_RZ_A1_BSP_USED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_RZ_A1_BSP_USED  1
+
+
+/**
+* @def  IS_CMSIS_USED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_CMSIS_USED  1
+
+
+/**
+* @def  IS_RTX_USED
+* @brief  0 or 1. Not CMSIS API.
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_RTX_USED  1
+
+
+/**
+* @def  IS_MBED_USED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_MBED_USED  1
+
+
+/**
+* @def  IS_VDC_SAMPLE_VRAM_USED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  IS_VDC_SAMPLE_VRAM_USED  0
+
+
+/**
+* @def  R_ARM
+* @brief  ARM core = 1, otherwise = not define
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_ARM  1
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* PROJECT_CONFIG_SUB_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/iobitmasks/cpg_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,462 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : cpg_iobitmask.h
+* $Rev: 809 $
+* $Date:: 2014-04-09 15:06:36 +0900#$
+* Description : CPG register define header
+*******************************************************************************/
+#ifndef CPG_IOBITMASK_H
+#define CPG_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define CPG_FRQCR_IFC                   (0x0300u)
+#define CPG_FRQCR_CKOEN                 (0x3000u)
+#define CPG_FRQCR_CKOEN2                (0x4000u)
+
+#define CPG_FRQCR2_GFC                  (0x0003u)
+
+#define CPG_CPUSTS_ISBUSY               (0x10u)
+
+#define CPG_STBCR1_DEEP                 (0x40u)
+#define CPG_STBCR1_STBY                 (0x80u)
+
+#define CPG_STBCR2_MSTP20               (0x01u)
+#define CPG_STBCR2_HIZ                  (0x80u)
+
+#define CPG_STBREQ1_STBRQ10             (0x01u)
+#define CPG_STBREQ1_STBRQ12             (0x04u)
+#define CPG_STBREQ1_STBRQ13             (0x08u)
+#define CPG_STBREQ1_STBRQ15             (0x20u)
+
+#define CPG_STBREQ2_STBRQ20             (0x01u)
+#define CPG_STBREQ2_STBRQ21             (0x02u)
+#define CPG_STBREQ2_STBRQ22             (0x04u)
+#define CPG_STBREQ2_STBRQ23             (0x08u)
+#define CPG_STBREQ2_STBRQ24             (0x10u)
+#define CPG_STBREQ2_STBRQ25             (0x20u)
+#define CPG_STBREQ2_STBRQ26             (0x40u)
+#define CPG_STBREQ2_STBRQ27             (0x80u)
+
+#define CPG_STBACK1_STBAK10             (0x01u)
+#define CPG_STBACK1_STBAK12             (0x04u)
+#define CPG_STBACK1_STBAK13             (0x08u)
+#define CPG_STBACK1_STBAK15             (0x20u)
+
+#define CPG_STBACK2_STBAK20             (0x01u)
+#define CPG_STBACK2_STBAK21             (0x02u)
+#define CPG_STBACK2_STBAK22             (0x04u)
+#define CPG_STBACK2_STBAK23             (0x08u)
+#define CPG_STBACK2_STBAK24             (0x10u)
+#define CPG_STBACK2_STBAK25             (0x20u)
+#define CPG_STBACK2_STBAK26             (0x40u)
+#define CPG_STBACK2_STBAK27             (0x80u)
+
+#define CPG_SYSCR1_VRAME0               (0x01u)
+#define CPG_SYSCR1_VRAME1               (0x02u)
+#define CPG_SYSCR1_VRAME2               (0x04u)
+#define CPG_SYSCR1_VRAME3               (0x08u)
+#define CPG_SYSCR1_VRAME4               (0x10u)
+
+#define CPG_SYSCR2_VRAMWE0              (0x01u)
+#define CPG_SYSCR2_VRAMWE1              (0x02u)
+#define CPG_SYSCR2_VRAMWE2              (0x04u)
+#define CPG_SYSCR2_VRAMWE3              (0x08u)
+#define CPG_SYSCR2_VRAMWE4              (0x10u)
+
+#define CPG_SYSCR3_RRAMWE0              (0x01u)
+#define CPG_SYSCR3_RRAMWE1              (0x02u)
+#define CPG_SYSCR3_RRAMWE2              (0x04u)
+#define CPG_SYSCR3_RRAMWE3              (0x08u)
+
+#define CPG_STBCR3_MSTP30               (0x01u)
+#define CPG_STBCR3_MSTP31               (0x02u)
+#define CPG_STBCR3_MSTP32               (0x04u)
+#define CPG_STBCR3_MSTP33               (0x08u)
+#define CPG_STBCR3_MSTP34               (0x10u)
+#define CPG_STBCR3_MSTP35               (0x20u)
+#define CPG_STBCR3_MSTP36               (0x40u)
+#define CPG_STBCR3_MSTP37               (0x80u)
+
+#define CPG_STBCR4_MSTP40               (0x01u)
+#define CPG_STBCR4_MSTP41               (0x02u)
+#define CPG_STBCR4_MSTP42               (0x04u)
+#define CPG_STBCR4_MSTP43               (0x08u)
+#define CPG_STBCR4_MSTP44               (0x10u)
+#define CPG_STBCR4_MSTP45               (0x20u)
+#define CPG_STBCR4_MSTP46               (0x40u)
+#define CPG_STBCR4_MSTP47               (0x80u)
+
+#define CPG_STBCR5_MSTP50               (0x01u)
+#define CPG_STBCR5_MSTP51               (0x02u)
+#define CPG_STBCR5_MSTP52               (0x04u)
+#define CPG_STBCR5_MSTP53               (0x08u)
+#define CPG_STBCR5_MSTP54               (0x10u)
+#define CPG_STBCR5_MSTP55               (0x20u)
+#define CPG_STBCR5_MSTP56               (0x40u)
+#define CPG_STBCR5_MSTP57               (0x80u)
+
+#define CPG_STBCR6_MSTP60               (0x01u)
+#define CPG_STBCR6_MSTP61               (0x02u)
+#define CPG_STBCR6_MSTP62               (0x04u)
+#define CPG_STBCR6_MSTP63               (0x08u)
+#define CPG_STBCR6_MSTP64               (0x10u)
+#define CPG_STBCR6_MSTP65               (0x20u)
+#define CPG_STBCR6_MSTP66               (0x40u)
+#define CPG_STBCR6_MSTP67               (0x80u)
+
+#define CPG_STBCR7_MSTP70               (0x01u)
+#define CPG_STBCR7_MSTP71               (0x02u)
+#define CPG_STBCR7_MSTP73               (0x08u)
+#define CPG_STBCR7_MSTP74               (0x10u)
+#define CPG_STBCR7_MSTP76               (0x40u)
+#define CPG_STBCR7_MSTP77               (0x80u)
+
+#define CPG_STBCR8_MSTP81               (0x02u)
+#define CPG_STBCR8_MSTP82               (0x04u)
+#define CPG_STBCR8_MSTP83               (0x08u)
+#define CPG_STBCR8_MSTP84               (0x10u)
+#define CPG_STBCR8_MSTP85               (0x20u)
+#define CPG_STBCR8_MSTP86               (0x40u)
+#define CPG_STBCR8_MSTP87               (0x80u)
+
+#define CPG_STBCR9_MSTP90               (0x01u)
+#define CPG_STBCR9_MSTP91               (0x02u)
+#define CPG_STBCR9_MSTP92               (0x04u)
+#define CPG_STBCR9_MSTP93               (0x08u)
+#define CPG_STBCR9_MSTP94               (0x10u)
+#define CPG_STBCR9_MSTP95               (0x20u)
+#define CPG_STBCR9_MSTP96               (0x40u)
+#define CPG_STBCR9_MSTP97               (0x80u)
+
+#define CPG_STBCR10_MSTP100             (0x01u)
+#define CPG_STBCR10_MSTP101             (0x02u)
+#define CPG_STBCR10_MSTP102             (0x04u)
+#define CPG_STBCR10_MSTP103             (0x08u)
+#define CPG_STBCR10_MSTP104             (0x10u)
+#define CPG_STBCR10_MSTP105             (0x20u)
+#define CPG_STBCR10_MSTP106             (0x40u)
+#define CPG_STBCR10_MSTP107             (0x80u)
+
+#define CPG_STBCR11_MSTP110             (0x01u)
+#define CPG_STBCR11_MSTP111             (0x02u)
+#define CPG_STBCR11_MSTP112             (0x04u)
+#define CPG_STBCR11_MSTP113             (0x08u)
+#define CPG_STBCR11_MSTP114             (0x10u)
+#define CPG_STBCR11_MSTP115             (0x20u)
+
+#define CPG_STBCR12_MSTP120             (0x01u)
+#define CPG_STBCR12_MSTP121             (0x02u)
+#define CPG_STBCR12_MSTP122             (0x04u)
+#define CPG_STBCR12_MSTP123             (0x08u)
+
+#define CPG_STBCR13_MSTP131             (0x02u)
+#define CPG_STBCR13_MSTP132             (0x04u)
+
+#define CPG_SWRSTCR1_SRST11             (0x02u)
+#define CPG_SWRSTCR1_SRST12             (0x04u)
+#define CPG_SWRSTCR1_SRST13             (0x08u)
+#define CPG_SWRSTCR1_SRST14             (0x10u)
+#define CPG_SWRSTCR1_SRST15             (0x20u)
+#define CPG_SWRSTCR1_SRST16             (0x40u)
+#define CPG_SWRSTCR1_AXTALE             (0x80u)
+
+#define CPG_SWRSTCR2_SRST21             (0x02u)
+
+#define CPG_SWRSTCR3_SRST32             (0x04u)
+
+#define CPG_RRAMKP_RRAMKP0              (0x01u)
+#define CPG_RRAMKP_RRAMKP1              (0x02u)
+#define CPG_RRAMKP_RRAMKP2              (0x04u)
+#define CPG_RRAMKP_RRAMKP3              (0x08u)
+
+#define CPG_DSCTR_RAMBOOT               (0x40u)
+#define CPG_DSCTR_EBUSKEEPE             (0x80u)
+
+#define CPG_DSSSR_P8_2                  (0x0001u)
+#define CPG_DSSSR_P9_1                  (0x0002u)
+#define CPG_DSSSR_P2_15                 (0x0004u)
+#define CPG_DSSSR_P7_8                  (0x0008u)
+#define CPG_DSSSR_P5_9                  (0x0010u)
+#define CPG_DSSSR_P6_4                  (0x0020u)
+#define CPG_DSSSR_RTCAR                 (0x0040u)
+#define CPG_DSSSR_NMI                   (0x0100u)
+#define CPG_DSSSR_P3_3                  (0x0200u)
+#define CPG_DSSSR_P8_7                  (0x0400u)
+#define CPG_DSSSR_P2_12                 (0x0800u)
+#define CPG_DSSSR_P3_1                  (0x1000u)
+#define CPG_DSSSR_P3_9                  (0x2000u)
+#define CPG_DSSSR_P6_2                  (0x4000u)
+
+#define CPG_DSESR_P8_2E                 (0x0001u)
+#define CPG_DSESR_P9_1E                 (0x0002u)
+#define CPG_DSESR_P2_15E                (0x0004u)
+#define CPG_DSESR_P7_8E                 (0x0008u)
+#define CPG_DSESR_P5_9E                 (0x0010u)
+#define CPG_DSESR_P6_4E                 (0x0020u)
+#define CPG_DSESR_NMIE                  (0x0100u)
+#define CPG_DSESR_P3_3E                 (0x0200u)
+#define CPG_DSESR_P8_7E                 (0x0400u)
+#define CPG_DSESR_P2_12E                (0x0800u)
+#define CPG_DSESR_P3_1E                 (0x1000u)
+#define CPG_DSESR_P3_9E                 (0x2000u)
+#define CPG_DSESR_P6_2E                 (0x4000u)
+
+#define CPG_DSFR_P8_2F                  (0x0001u)
+#define CPG_DSFR_P9_1F                  (0x0002u)
+#define CPG_DSFR_P2_15F                 (0x0004u)
+#define CPG_DSFR_P7_8F                  (0x0008u)
+#define CPG_DSFR_P5_9F                  (0x0010u)
+#define CPG_DSFR_P6_4F                  (0x0020u)
+#define CPG_DSFR_RTCARF                 (0x0040u)
+#define CPG_DSFR_NMIF                   (0x0100u)
+#define CPG_DSFR_P3_3F                  (0x0200u)
+#define CPG_DSFR_P8_7F                  (0x0400u)
+#define CPG_DSFR_P2_12F                 (0x0800u)
+#define CPG_DSFR_P3_1F                  (0x1000u)
+#define CPG_DSFR_P3_9F                  (0x2000u)
+#define CPG_DSFR_P6_2F                  (0x4000u)
+#define CPG_DSFR_IOKEEP                 (0x8000u)
+
+#define CPG_XTALCTR_GAIN0               (0x01u)
+#define CPG_XTALCTR_GAIN1               (0x02u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define CPG_FRQCR_IFC_SHIFT             (8u)
+#define CPG_FRQCR_CKOEN_SHIFT           (12u)
+#define CPG_FRQCR_CKOEN2_SHIFT          (14u)
+
+#define CPG_FRQCR2_GFC_SHIFT            (0u)
+
+#define CPG_CPUSTS_ISBUSY_SHIFT         (4u)
+
+#define CPG_STBCR1_DEEP_SHIFT           (6u)
+#define CPG_STBCR1_STBY_SHIFT           (7u)
+
+#define CPG_STBCR2_MSTP20_SHIFT         (0u)
+#define CPG_STBCR2_HIZ_SHIFT            (7u)
+
+#define CPG_STBREQ1_STBRQ10_SHIFT       (0u)
+#define CPG_STBREQ1_STBRQ12_SHIFT       (2u)
+#define CPG_STBREQ1_STBRQ13_SHIFT       (3u)
+#define CPG_STBREQ1_STBRQ15_SHIFT       (5u)
+
+#define CPG_STBREQ2_STBRQ20_SHIFT       (0u)
+#define CPG_STBREQ2_STBRQ21_SHIFT       (1u)
+#define CPG_STBREQ2_STBRQ22_SHIFT       (2u)
+#define CPG_STBREQ2_STBRQ23_SHIFT       (3u)
+#define CPG_STBREQ2_STBRQ24_SHIFT       (4u)
+#define CPG_STBREQ2_STBRQ25_SHIFT       (5u)
+#define CPG_STBREQ2_STBRQ26_SHIFT       (6u)
+#define CPG_STBREQ2_STBRQ27_SHIFT       (7u)
+
+#define CPG_STBACK1_STBAK10_SHIFT       (0u)
+#define CPG_STBACK1_STBAK12_SHIFT       (2u)
+#define CPG_STBACK1_STBAK13_SHIFT       (3u)
+#define CPG_STBACK1_STBAK15_SHIFT       (5u)
+
+#define CPG_STBACK2_STBAK20_SHIFT       (0u)
+#define CPG_STBACK2_STBAK21_SHIFT       (1u)
+#define CPG_STBACK2_STBAK22_SHIFT       (2u)
+#define CPG_STBACK2_STBAK23_SHIFT       (3u)
+#define CPG_STBACK2_STBAK24_SHIFT       (4u)
+#define CPG_STBACK2_STBAK25_SHIFT       (5u)
+#define CPG_STBACK2_STBAK26_SHIFT       (6u)
+#define CPG_STBACK2_STBAK27_SHIFT       (7u)
+
+#define CPG_SYSCR1_VRAME0_SHIFT         (0u)
+#define CPG_SYSCR1_VRAME1_SHIFT         (1u)
+#define CPG_SYSCR1_VRAME2_SHIFT         (2u)
+#define CPG_SYSCR1_VRAME3_SHIFT         (3u)
+#define CPG_SYSCR1_VRAME4_SHIFT         (4u)
+
+#define CPG_SYSCR2_VRAMWE0_SHIFT        (0u)
+#define CPG_SYSCR2_VRAMWE1_SHIFT        (1u)
+#define CPG_SYSCR2_VRAMWE2_SHIFT        (2u)
+#define CPG_SYSCR2_VRAMWE3_SHIFT        (3u)
+#define CPG_SYSCR2_VRAMWE4_SHIFT        (4u)
+
+#define CPG_SYSCR3_RRAMWE0_SHIFT        (0u)
+#define CPG_SYSCR3_RRAMWE1_SHIFT        (1u)
+#define CPG_SYSCR3_RRAMWE2_SHIFT        (2u)
+#define CPG_SYSCR3_RRAMWE3_SHIFT        (3u)
+
+#define CPG_STBCR3_MSTP30_SHIFT         (0u)
+#define CPG_STBCR3_MSTP31_SHIFT         (1u)
+#define CPG_STBCR3_MSTP32_SHIFT         (2u)
+#define CPG_STBCR3_MSTP33_SHIFT         (3u)
+#define CPG_STBCR3_MSTP34_SHIFT         (4u)
+#define CPG_STBCR3_MSTP35_SHIFT         (5u)
+#define CPG_STBCR3_MSTP36_SHIFT         (6u)
+#define CPG_STBCR3_MSTP37_SHIFT         (7u)
+
+#define CPG_STBCR4_MSTP40_SHIFT         (0u)
+#define CPG_STBCR4_MSTP41_SHIFT         (1u)
+#define CPG_STBCR4_MSTP42_SHIFT         (2u)
+#define CPG_STBCR4_MSTP43_SHIFT         (3u)
+#define CPG_STBCR4_MSTP44_SHIFT         (4u)
+#define CPG_STBCR4_MSTP45_SHIFT         (5u)
+#define CPG_STBCR4_MSTP46_SHIFT         (6u)
+#define CPG_STBCR4_MSTP47_SHIFT         (7u)
+
+#define CPG_STBCR5_MSTP50_SHIFT         (0u)
+#define CPG_STBCR5_MSTP51_SHIFT         (1u)
+#define CPG_STBCR5_MSTP52_SHIFT         (2u)
+#define CPG_STBCR5_MSTP53_SHIFT         (3u)
+#define CPG_STBCR5_MSTP54_SHIFT         (4u)
+#define CPG_STBCR5_MSTP55_SHIFT         (5u)
+#define CPG_STBCR5_MSTP56_SHIFT         (6u)
+#define CPG_STBCR5_MSTP57_SHIFT         (7u)
+
+#define CPG_STBCR6_MSTP60_SHIFT         (0u)
+#define CPG_STBCR6_MSTP61_SHIFT         (1u)
+#define CPG_STBCR6_MSTP62_SHIFT         (2u)
+#define CPG_STBCR6_MSTP63_SHIFT         (3u)
+#define CPG_STBCR6_MSTP64_SHIFT         (4u)
+#define CPG_STBCR6_MSTP65_SHIFT         (5u)
+#define CPG_STBCR6_MSTP66_SHIFT         (6u)
+#define CPG_STBCR6_MSTP67_SHIFT         (7u)
+
+#define CPG_STBCR7_MSTP70_SHIFT         (0u)
+#define CPG_STBCR7_MSTP71_SHIFT         (1u)
+#define CPG_STBCR7_MSTP73_SHIFT         (3u)
+#define CPG_STBCR7_MSTP74_SHIFT         (4u)
+#define CPG_STBCR7_MSTP76_SHIFT         (6u)
+#define CPG_STBCR7_MSTP77_SHIFT         (7u)
+
+#define CPG_STBCR8_MSTP81_SHIFT         (1u)
+#define CPG_STBCR8_MSTP82_SHIFT         (2u)
+#define CPG_STBCR8_MSTP83_SHIFT         (3u)
+#define CPG_STBCR8_MSTP84_SHIFT         (4u)
+#define CPG_STBCR8_MSTP85_SHIFT         (5u)
+#define CPG_STBCR8_MSTP86_SHIFT         (6u)
+#define CPG_STBCR8_MSTP87_SHIFT         (7u)
+
+#define CPG_STBCR9_MSTP90_SHIFT         (0u)
+#define CPG_STBCR9_MSTP91_SHIFT         (1u)
+#define CPG_STBCR9_MSTP92_SHIFT         (2u)
+#define CPG_STBCR9_MSTP93_SHIFT         (3u)
+#define CPG_STBCR9_MSTP94_SHIFT         (4u)
+#define CPG_STBCR9_MSTP95_SHIFT         (5u)
+#define CPG_STBCR9_MSTP96_SHIFT         (6u)
+#define CPG_STBCR9_MSTP97_SHIFT         (7u)
+
+#define CPG_STBCR10_MSTP100_SHIFT       (0u)
+#define CPG_STBCR10_MSTP101_SHIFT       (1u)
+#define CPG_STBCR10_MSTP102_SHIFT       (2u)
+#define CPG_STBCR10_MSTP103_SHIFT       (3u)
+#define CPG_STBCR10_MSTP104_SHIFT       (4u)
+#define CPG_STBCR10_MSTP105_SHIFT       (5u)
+#define CPG_STBCR10_MSTP106_SHIFT       (6u)
+#define CPG_STBCR10_MSTP107_SHIFT       (7u)
+
+#define CPG_STBCR11_MSTP110_SHIFT       (0u)
+#define CPG_STBCR11_MSTP111_SHIFT       (1u)
+#define CPG_STBCR11_MSTP112_SHIFT       (2u)
+#define CPG_STBCR11_MSTP113_SHIFT       (3u)
+#define CPG_STBCR11_MSTP114_SHIFT       (4u)
+#define CPG_STBCR11_MSTP115_SHIFT       (5u)
+
+#define CPG_STBCR12_MSTP120_SHIFT       (0u)
+#define CPG_STBCR12_MSTP121_SHIFT       (1u)
+#define CPG_STBCR12_MSTP122_SHIFT       (2u)
+#define CPG_STBCR12_MSTP123_SHIFT       (3u)
+
+#define CPG_STBCR13_MSTP131_SHIFT       (1u)
+#define CPG_STBCR13_MSTP132_SHIFT       (2u)
+
+#define CPG_SWRSTCR1_SRST11_SHIFT       (1u)
+#define CPG_SWRSTCR1_SRST12_SHIFT       (2u)
+#define CPG_SWRSTCR1_SRST13_SHIFT       (3u)
+#define CPG_SWRSTCR1_SRST14_SHIFT       (4u)
+#define CPG_SWRSTCR1_SRST15_SHIFT       (5u)
+#define CPG_SWRSTCR1_SRST16_SHIFT       (6u)
+#define CPG_SWRSTCR1_AXTALE_SHIFT       (7u)
+
+#define CPG_SWRSTCR2_SRST21_SHIFT       (1u)
+
+#define CPG_SWRSTCR3_SRST32_SHIFT       (2u)
+
+#define CPG_RRAMKP_RRAMKP0_SHIFT        (0u)
+#define CPG_RRAMKP_RRAMKP1_SHIFT        (1u)
+#define CPG_RRAMKP_RRAMKP2_SHIFT        (2u)
+#define CPG_RRAMKP_RRAMKP3_SHIFT        (3u)
+
+#define CPG_DSCTR_RAMBOOT_SHIFT         (6u)
+#define CPG_DSCTR_EBUSKEEPE_SHIFT       (7u)
+
+#define CPG_DSSSR_P8_2_SHIFT            (0u)
+#define CPG_DSSSR_P9_1_SHIFT            (1u)
+#define CPG_DSSSR_P2_15_SHIFT           (2u)
+#define CPG_DSSSR_P7_8_SHIFT            (3u)
+#define CPG_DSSSR_P5_9_SHIFT            (4u)
+#define CPG_DSSSR_P6_4_SHIFT            (5u)
+#define CPG_DSSSR_RTCAR_SHIFT           (6u)
+#define CPG_DSSSR_NMI_SHIFT             (8u)
+#define CPG_DSSSR_P3_3_SHIFT            (9u)
+#define CPG_DSSSR_P8_7_SHIFT            (10u)
+#define CPG_DSSSR_P2_12_SHIFT           (11u)
+#define CPG_DSSSR_P3_1_SHIFT            (12u)
+#define CPG_DSSSR_P3_9_SHIFT            (13u)
+#define CPG_DSSSR_P6_2_SHIFT            (14u)
+
+#define CPG_DSESR_P8_2E_SHIFT           (0u)
+#define CPG_DSESR_P9_1E_SHIFT           (1u)
+#define CPG_DSESR_P2_15E_SHIFT          (2u)
+#define CPG_DSESR_P7_8E_SHIFT           (3u)
+#define CPG_DSESR_P5_9E_SHIFT           (4u)
+#define CPG_DSESR_P6_4E_SHIFT           (5u)
+#define CPG_DSESR_NMIE_SHIFT            (8u)
+#define CPG_DSESR_P3_3E_SHIFT           (9u)
+#define CPG_DSESR_P8_7E_SHIFT           (10u)
+#define CPG_DSESR_P2_12E_SHIFT          (11u)
+#define CPG_DSESR_P3_1E_SHIFT           (12u)
+#define CPG_DSESR_P3_9E_SHIFT           (13u)
+#define CPG_DSESR_P6_2E_SHIFT           (14u)
+
+#define CPG_DSFR_P8_2F_SHIFT            (0u)
+#define CPG_DSFR_P9_1F_SHIFT            (1u)
+#define CPG_DSFR_P2_15F_SHIFT           (2u)
+#define CPG_DSFR_P7_8F_SHIFT            (3u)
+#define CPG_DSFR_P5_9F_SHIFT            (4u)
+#define CPG_DSFR_P6_4F_SHIFT            (5u)
+#define CPG_DSFR_RTCARF_SHIFT           (6u)
+#define CPG_DSFR_NMIF_SHIFT             (8u)
+#define CPG_DSFR_P3_3F_SHIFT            (9u)
+#define CPG_DSFR_P8_7F_SHIFT            (10u)
+#define CPG_DSFR_P2_12F_SHIFT           (11u)
+#define CPG_DSFR_P3_1F_SHIFT            (12u)
+#define CPG_DSFR_P3_9F_SHIFT            (13u)
+#define CPG_DSFR_P6_2F_SHIFT            (14u)
+#define CPG_DSFR_IOKEEP_SHIFT           (15u)
+
+#define CPG_XTALCTR_GAIN0_SHIFT         (0u)
+#define CPG_XTALCTR_GAIN1_SHIFT         (1u)
+
+
+#endif /* CPG_IOBITMASK_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/inc/JPEG_Converter.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,208 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          JPEG_Converter.h
+* @brief         JCU API
+******************************************************************************/
+
+#ifndef JPEG_CONVERTER_H
+#define JPEG_CONVERTER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/** A class to communicate a JCU
+ *
+ */
+class JPEG_Converter {
+
+public:
+    /*! @enum jpeg_conv_error_t
+        @brief Error codes
+     */
+    typedef enum {
+        JPEG_CONV_OK              =  0, /*!< Normal termination      */
+        JPEG_CONV_JCU_ERR         = -1, /*!< JCU driver error        */
+        JPEG_CONV_FORMA_ERR       = -2, /*!< Not support format      */
+        JPEG_CONV_PARAM_ERR       = -3, /*!< Parameter error         */
+        JPEG_CONV_BUSY            = -4, /*!< JCU Busy                */
+        JPEG_CONV_PARAM_RANGE_ERR = -7, /*!< Parameter range error   */
+    } jpeg_conv_error_t;
+
+    /*! @enum wr_rd_swa_t
+        @brief Write/Read image pixcel frame buffer swap setting
+     */
+    typedef enum {
+        WR_RD_WRSWA_NON        = 0,     /*!< Not swapped: 1-2-3-4-5-6-7-8 */
+        WR_RD_WRSWA_8BIT       = 1,     /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+        WR_RD_WRSWA_16BIT      = 2,     /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+        WR_RD_WRSWA_16_8BIT    = 3,     /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+        WR_RD_WRSWA_32BIT      = 4,     /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+        WR_RD_WRSWA_32_8BIT    = 5,     /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+        WR_RD_WRSWA_32_16BIT   = 6,     /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+        WR_RD_WRSWA_32_16_8BIT = 7,     /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+    } wr_rd_swa_t;
+
+    /*! @enum wr_rd_format_t
+        @brief Write/Read image pixcel format selects
+    */
+    typedef enum {
+        WR_RD_YCbCr422 = 0x00,          /*!< YCbCr422 (2byte / px)  */
+        WR_RD_ARGB8888 = 0x01,          /*!< ARGB8888 (4byte / px)  */
+        WR_RD_RGB565   = 0x02,          /*!< RGB565   (2byte / px)  */
+    } wr_rd_format_t;
+
+    /*! @enum sub_sampling_t
+        @brief Thinning output image selects
+    */
+    typedef enum {
+        SUB_SAMPLING_1_1 = 0x00,        /*!< Thinning output image to 1/1 */
+        SUB_SAMPLING_1_2 = 0x01,        /*!< Thinning output image to 1/2 */
+        SUB_SAMPLING_1_4 = 0x02,        /*!< Thinning output image to 1/4 */
+        SUB_SAMPLING_1_8 = 0x03         /*!< Thinning output image to 1/8 */
+    } sub_sampling_t;
+
+    /*! @enum cbcr_offset_t
+        @brief Cb/Cr range selects for decode
+    */
+    typedef enum {
+        CBCR_OFFSET_0   = 0x00,         /*!< Cb/Cr range -128 to 127 (all format used) */
+        CBCR_OFFSET_128 = 0x01,         /*!< Cb/Cr range    0 to 255 (Default and YCbCr format only used)      */
+    } cbcr_offset_t;
+
+    /*! @struct bitmap_buff_info_t
+        @brief Bitmap data setting struct
+     */
+    typedef struct {
+        int32_t         width;              /*!< width           width of bitmap data   */
+        int32_t         height;             /*!< height          height of bitmap data  */
+        wr_rd_format_t  format;             /*!< format          format of bitmap data  */
+        void*           buffer_address;     /*!< buffer_address  address of bitmap data */
+    } bitmap_buff_info_t;
+
+    /** Constructor method of JPEG converter(encode/decode)
+     */
+    JPEG_Converter();
+
+    /** Destructor method of JPEG converter(encode/decode)
+     */
+    virtual ~JPEG_Converter();
+
+    /*! @struct DecodeOptions_t
+        @brief Decode option setting
+     */
+    struct decode_options_t {
+        sub_sampling_t  vertical_sub_sampling;                      /*!< Vertical sampling setting */
+        sub_sampling_t  horizontal_sub_sampling;                    /*!< Horizontal sampling setting */
+        cbcr_offset_t   output_cb_cr_offset;                        /*!< Output data Cb/Cr range setting */
+        wr_rd_swa_t     output_swapsetting;                         /*!< Output data swap setteing */
+        int32_t         alpha;                                      /*!< alpha setting for ARGB8888 */
+        bool            check_jpeg_format;                          /*!< Flag check JPEG data format : Setting NULL does not check JPEG format when decoding */
+        void (* p_DecodeCallBackFunc)(jpeg_conv_error_t err_code);  /*!< Callback function address */
+
+        decode_options_t() {
+            vertical_sub_sampling   = SUB_SAMPLING_1_1;
+            horizontal_sub_sampling = SUB_SAMPLING_1_1;
+            output_cb_cr_offset     = CBCR_OFFSET_128;
+            output_swapsetting      = WR_RD_WRSWA_8BIT;
+            alpha                   = 0;
+            check_jpeg_format       = false;
+            p_DecodeCallBackFunc    = NULL;
+        }
+    };
+
+    /*! @struct encode_options_t
+        @brief Encode option setting
+     */
+    struct encode_options_t {
+        int32_t         DRI_value;              /*!< DRI setting */
+        int32_t         width;                  /*!< Encode width */
+        int32_t         height;                 /*!< Encode height */
+        cbcr_offset_t   input_cb_cr_offset;     /*!< Input data Cb/Cr range setting */
+        wr_rd_swa_t     input_swapsetting;      /*!< Input data swap setteing */
+        size_t          encode_buff_size;       /*!< Encode buffer size : Setting 0 does not the buffer size confirmation of when encoding  */
+        void*           quantization_table_Y;   /*!< Quantization table address(Y) */
+        void*           quantization_table_C;   /*!< Quantization table address(C) */
+        void*           huffman_table_Y_DC;     /*!< Huffman Table address(Y DC) */
+        void*           huffman_table_C_DC;     /*!< Huffman Table address(C DC) */
+        void*           huffman_table_Y_AC;     /*!< Huffman Table address(Y AC) */
+        void*           huffman_table_C_AC;     /*!< Huffman Table address(C AC) */
+        void (* p_EncodeCallBackFunc)(jpeg_conv_error_t err_code);  /*!< Callback function address */
+
+        encode_options_t() {
+            DRI_value           = 0;
+            width               = 0;
+            height              = 0;
+            input_cb_cr_offset  = CBCR_OFFSET_128;
+            input_swapsetting   = WR_RD_WRSWA_8BIT;
+            encode_buff_size    = 0;
+            quantization_table_Y = NULL;
+            quantization_table_C = NULL;
+            huffman_table_Y_DC = NULL;
+            huffman_table_C_DC = NULL;
+            huffman_table_Y_AC = NULL;
+            huffman_table_C_AC = NULL;
+            p_EncodeCallBackFunc = NULL;
+        }
+    };
+
+    /** Decode JPEG to rinear data
+     *
+     * @param[in]     void*                 pJpegBuff       : Input JPEG data address
+     * @param[in/out] bitmap_buff_info_t*   psOutputBuff    : Output bitmap data address
+     * @param[in]     decode_options_t*     pOptions        : Decode option(Optional)
+     * @return JPEG_CONV_OK              = success
+     *         JPEG_CONV_JCU_ERR         = failure (JCU error)
+     *         JPEG_CONV_FORMA_ERR       = failure (data format error)
+     *         JPEG_CONV_PARAM_ERR       = failure (input parameter error)
+     *         JPEG_CONV_PARAM_RANGE_ERR = failure (input parameter range error)
+     */
+    JPEG_Converter::jpeg_conv_error_t decode(void* pJpegBuff, bitmap_buff_info_t* psOutputBuff );
+    JPEG_Converter::jpeg_conv_error_t decode(void* pJpegBuff, bitmap_buff_info_t* psOutputBuff, decode_options_t* pOptions );
+
+    /** Encode rinear data to JPEG
+     *
+     * @param[in]   bitmap_buff_info_t*     psInputBuff     : Input bitmap data address
+     * @param[out]  void*                   pJpegBuff       : Output JPEG data address
+     * @param[out]  size_t*                 pEncodeSize     : Encode size address
+     * @param[in]   encode_options_t*       pOptions[IN]    : Encode option(Optional)
+     * @return JPEG_CONV_OK              = success
+     *         JPEG_CONV_JCU_ERR         = failure (JCU error)
+     *         JPEG_CONV_FORMA_ERR       = failure (data format error)
+     *         JPEG_CONV_PARAM_ERR       = failure (input parameter error)
+     *         JPEG_CONV_PARAM_RANGE_ERR = failure (input parameter range error)
+     */
+    JPEG_Converter::jpeg_conv_error_t encode(bitmap_buff_info_t* psInputBuff, void* pJpegBuff, size_t* pEncodeSize );
+    JPEG_Converter::jpeg_conv_error_t encode(bitmap_buff_info_t* psInputBuff, void* pJpegBuff, size_t* pEncodeSize, encode_options_t* pOptions );
+
+private:
+
+};
+
+#endif  /* JPEG_CONVERTER_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/inc/converter_wrapper.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,102 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         converter_wrapper.h
+* @version      1.00
+* $Rev: 1 $
+* $Date:: 2015-08-06 16:33:52 +0900#$
+* @brief        Graphics driver wrapper function definitions in C
+******************************************************************************/
+
+#ifndef CONVERTER_WRAPPER_H
+#define CONVERTER_WRAPPER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_ospl_typedef.h"
+#include "cmsis_os.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @enum mbed_jcu_err_t
+    @brief Error codes
+ */
+typedef	enum {
+        MBED_JCU_E_OK              =  0,	/*!< Normal termination      */
+        MBED_JCU_E_JCU_ERR         = -1,	/*!< JCU driver error        */
+        MBED_JCU_E_FORMA_ERR       = -2,	/*!< Not support format      */
+        MBED_JCU_E_PARAM_ERR       = -3,	/*!< Parameter error         */
+        MBED_JCU_E_PARAM_RANGE_ERR = -7,	/*!< Parameter range error   */
+ } mbed_jcu_err_t;
+
+
+/** Callback function format
+ */
+typedef void (mbed_CallbackFunc_t)(mbed_jcu_err_t err_code);
+
+
+/**************************************************************************//**
+ * @brief       Set callback function address for decode
+ * @param[in]   pSetCallbackAdr  Callback function address
+ * @param[in]   p_async          ospl async data address
+ * @param[in]   width            Decode data width
+ * @param[in]   height           Decode data height
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_set_decode_callback(mbed_CallbackFunc_t* pSetCallbackAdr, size_t width, size_t height);
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   InterruptSource  Interrput source data struct address
+ * @param[in]   Caller           ospl caller data address
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_LocalDecodeCallback(const r_ospl_interrupt_t *InterruptSource, const r_ospl_caller_t *Caller);
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   pSetCallbackAdr  Callback function address
+ * @param[in]   p_async          ospl async data address
+ * @param[in]   pSize            Encode size input address
+ * @param[in]   count_max        Encode count max num
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_set_encode_callback(mbed_CallbackFunc_t* pSetCallbackAdr, size_t* pSize, int32_t count_max);
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   InterruptSource  Interrput source data struct address
+ * @param[in]   Caller           ospl caller data address
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_LocalEncodeCallback(const r_ospl_interrupt_t *InterruptSource, const r_ospl_caller_t *Caller);
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif	/* CONVERTER_WRAPPER_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/inc/r_jcu_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,578 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_jcu_api.h
+* @brief   JCU (JPEG hardware) driver API. Main Header.
+*
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+#ifndef JCU_API_H_
+#define JCU_API_H_
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stddef.h>
+#include    "r_jcu_user.h"
+#include    "r_ospl.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   jcu_status_information_t
+* @brief  Status
+*
+*    - JCU_STATUS_UNDEF - 0x00, Undefined
+*    - JCU_STATUS_INIT - 0x01, Initialized
+*    - JCU_STATUS_SELECTED - 0x02, Codec is selected
+*    - JCU_STATUS_READY - 0x08, Ready
+*    - JCU_STATUS_RUN - 0x10, Run
+*    - JCU_STATUS_INTERRUPTING - 0x40, Interrupting
+*    - JCU_STATUS_INTERRUPTED - 0x80, Interrupted
+*/
+typedef enum {
+    JCU_STATUS_UNDEF        = 0x00,
+    JCU_STATUS_INIT         = 0x01,
+    JCU_STATUS_SELECTED     = 0x02,
+    JCU_STATUS_READY        = 0x08,
+    JCU_STATUS_RUN          = 0x10,
+    JCU_STATUS_INTERRUPTING = 0x40,
+    JCU_STATUS_INTERRUPTED  = 0x80
+} jcu_status_information_t;
+
+
+/**
+* @struct  jcu_async_status_t
+* @brief  Status of asynchronize
+*/
+typedef struct st_jcu_async_status_t  jcu_async_status_t;
+struct st_jcu_async_status_t {
+    jcu_status_information_t  Status;
+    bit_flags_fast32_t        SubStatusFlags;
+    bool_t                    IsPaused;
+    bool_t                    IsEnabledInterrupt;
+    r_ospl_flag32_t           InterruptEnables;
+    r_ospl_flag32_t           InterruptFlags;
+    r_ospl_flag32_t           CancelFlags;  /*<r_ospl_cancel_flag_t>*/
+};
+
+
+/* Section: Global */
+/**
+* @enum   SubStatusFlags
+* @brief  Sub Status
+*
+*    - JCU_SUB_INFOMATION_READY - 0x00000008
+*    - JCU_SUB_DECODE_OUTPUT_PAUSE - 0x00000100
+*    - JCU_SUB_DECODE_INPUT_PAUSE - 0x00000200
+*    - JCU_SUB_ENCODE_OUTPUT_PAUSE - 0x00001000
+*    - JCU_SUB_ENCODE_INPUT_PAUSE - 0x00002000
+*/
+#define JCU_SUB_INFOMATION_READY    0x00000008
+#define JCU_SUB_DECODE_OUTPUT_PAUSE 0x00000100
+#define JCU_SUB_DECODE_INPUT_PAUSE  0x00000200
+#define JCU_SUB_ENCODE_OUTPUT_PAUSE 0x00001000
+#define JCU_SUB_ENCODE_INPUT_PAUSE  0x00002000
+
+
+/**
+* @def  jcu_interrupt_line_t
+* @brief  Interrupt Lines
+*
+*    - JCU_INTERRUPT_LINE_JEDI - 1
+*    - JCU_INTERRUPT_LINE_JDTI - 2
+*    - JCU_INTERRUPT_LINE_ALL - 1 | 2
+*/
+typedef uint_fast32_t  jcu_interrupt_line_t;
+#define  JCU_INTERRUPT_LINE_JEDI  0x00000001u
+#define  JCU_INTERRUPT_LINE_JDTI  0x00000002u
+#define  JCU_INTERRUPT_LINE_ALL \
+    ( JCU_INTERRUPT_LINE_JEDI | JCU_INTERRUPT_LINE_JDTI )
+
+
+/**
+* @typedef  jcu_interrupt_lines_t
+* @brief  Bit flags of <jcu_interrupt_line_t>
+*/
+typedef bit_flags_fast32_t /*<jcu_interrupt_line_t>*/  jcu_interrupt_lines_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/**
+* @def  JCU_VERSION
+* @brief  VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define JCU_VERSION  100
+
+
+/**
+* @def  JCU_VERSION_STRING
+* @brief  String of <JCU_VERSION>
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define JCU_VERSION_STRING  "1.00"
+
+
+/**
+* @def  JCU_INT_TYPE_NUM
+* @brief  The number of the interrupt source
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define JCU_INT_TYPE_NUM  0x0009
+
+
+/**
+* @def  JCU_COLOR_ELEMENT_NUM
+* @brief  Y,Cb and Cr
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define JCU_COLOR_ELEMENT_NUM   3
+
+
+/******************************************************************************
+Struct & Enum definitions
+******************************************************************************/
+
+/**
+* @enum   jcu_errorcode_t
+* @brief  Error code of JCU driver
+*
+*    - JCU_ERROR_OK - 0
+*    - JCU_ERROR_PARAM - 0x4501
+*    - JCU_ERROR_STATUS - 0x4502
+*    - JCU_ERROR_CODEC_TYPE - 0x4503
+*    - JCU_ERROR_LIMITATION - 0x4504
+*/
+enum { E_CATEGORY_JCU_ERR = 0x4500 };  /* Offset of JCU error code */
+typedef errnum_t  jcu_errorcode_t;
+enum {
+    JCU_ERROR_OK            = 0x0000,
+    JCU_ERROR_PARAM         = 0x4501,
+    JCU_ERROR_STATUS        = 0x4502,
+    JCU_ERROR_CODEC_TYPE    = 0x4503,
+    JCU_ERROR_LIMITATION    = 0x4504
+};
+
+
+/**
+* @enum   jcu_detail_error_t
+* @brief  Kind of detailed error for decoding
+*
+*    - JCU_JCDERR_OK - 0x0000
+*    - JCU_JCDERR_SOI_NOT_FOUND - 0x4521
+*    - JCU_JCDERR_INVALID_SOF - 0x4522
+*    - JCU_JCDERR_UNPROVIDED_SOF - 0x4523
+*    - JCU_JCDERR_SOF_ACCURACY - 0x4524
+*    - JCU_JCDERR_DQT_ACCURACY - 0x4525
+*    - JCU_JCDERR_COMPONENT_1 - 0x4526
+*    - JCU_JCDERR_COMPONENT_2 - 0x4527
+*    - JCU_JCDERR_NO_SOF0_DQT_DHT - 0x4528
+*    - JCU_JCDERR_SOS_NOT_FOUND - 0x4529
+*    - JCU_JCDERR_EOI_NOT_FOUND - 0x452A
+*    - JCU_JCDERR_RESTART_INTERVAL - 0x452B
+*    - JCU_JCDERR_IMAGE_SIZE - 0x452C
+*    - JCU_JCDERR_LAST_MCU_DATA - 0x452D
+*    - JCU_JCDERR_BLOCK_DATA - 0x452E
+*/
+enum { E_CATEGORY_JCU_JCDERR = 0x4520 };  /* Offset of JCU detail error code */
+typedef errnum_t  jcu_detail_error_t;
+enum {
+    JCU_JCDERR_OK                = 0x0000,
+    JCU_JCDERR_SOI_NOT_FOUND     = 0x4521,
+    JCU_JCDERR_INVALID_SOF       = 0x4522,
+    JCU_JCDERR_UNPROVIDED_SOF    = 0x4523,
+    JCU_JCDERR_SOF_ACCURACY      = 0x4524,
+    JCU_JCDERR_DQT_ACCURACY      = 0x4525,
+    JCU_JCDERR_COMPONENT_1       = 0x4526,
+    JCU_JCDERR_COMPONENT_2       = 0x4527,
+    JCU_JCDERR_NO_SOF0_DQT_DHT   = 0x4528,
+    JCU_JCDERR_SOS_NOT_FOUND     = 0x4529,
+    JCU_JCDERR_EOI_NOT_FOUND     = 0x452A,
+    JCU_JCDERR_RESTART_INTERVAL  = 0x452B,
+    JCU_JCDERR_IMAGE_SIZE        = 0x452C,
+    JCU_JCDERR_LAST_MCU_DATA     = 0x452D,
+    JCU_JCDERR_BLOCK_DATA        = 0x452E
+};
+
+
+/**
+* @enum   jcu_codec_t
+* @brief  The type of codec
+*
+*    - JCU_ENCODE - 0
+*    - JCU_DECODE - 1
+*/
+typedef enum {
+    JCU_ENCODE  = 0,
+    JCU_DECODE  = 1
+} jcu_codec_t;
+
+
+/**
+* @struct  jcu_count_mode_param_t
+* @brief  Buffer settings for separating decode or encode
+*/
+typedef struct {
+    struct {
+        /** true: It uses the count mode process. */
+        bool_t      isEnable;
+
+        /** Address is changed when processing is stopped. */
+        bool_t      isInitAddress;
+
+        /** This is enable when isInitAddrss is true. */
+        uint32_t   *restartAddress;
+
+        /** Encode:8line Decode:8byte. */
+        uint32_t    dataCount;
+
+    } inputBuffer;
+
+    struct {
+        /** true: It uses the count mode process. */
+        bool_t      isEnable;
+
+        /** Address is changed when processing is stopped. */
+        bool_t      isInitAddress;      /*    */
+
+        /** This is enable when isInitAddress is true. */
+        uint32_t    *restartAddress;    /*     */
+
+        /** Encode:8byte Decode:8line. */
+        uint32_t    dataCount;
+
+    } outputBuffer;
+} jcu_count_mode_param_t;
+
+
+/* Section: Global */
+/**
+* @enum   jcu_continue_type_t
+* @brief  Type of continue buffer
+*
+*    - JCU_INPUT_BUFFER - 0
+*    - JCU_OUTPUT_BUFFER - 1
+*    - JCU_IMAGE_INFO - 2
+*/
+typedef enum {
+    JCU_INPUT_BUFFER,
+    JCU_OUTPUT_BUFFER,
+    JCU_IMAGE_INFO
+} jcu_continue_type_t;
+
+
+/**
+* @def  jcu_int_detail_error_t
+* @brief  Bit flags of detail error
+*
+*    - JCU_INT_ERROR_RESTART_INTERVAL_DATA - INT7_MASK
+*    - JCU_INT_ERROR_SEGMENT_TOTAL_DATA - INT6_MASK
+*    - JCU_INT_ERROR_MCU_BLOCK_DATA - INT5_MASK
+*    - JCU_INT_ERROR_ALL - e.g. for mask
+*/
+typedef uint_fast32_t  jcu_int_detail_error_t;
+#define JCU_INT_ERROR_RESTART_INTERVAL_DATA  (0x80u)
+#define JCU_INT_ERROR_SEGMENT_TOTAL_DATA     (0x40u)
+#define JCU_INT_ERROR_MCU_BLOCK_DATA         (0x20u)
+#define JCU_INT_ERROR_ALL \
+	( JCU_INT_ERROR_RESTART_INTERVAL_DATA | JCU_INT_ERROR_SEGMENT_TOTAL_DATA | \
+	JCU_INT_ERROR_MCU_BLOCK_DATA )
+
+
+/**
+* @typedef  jcu_int_detail_errors_t
+* @brief  Bit flags of detail error
+*/
+typedef bit_flags_fast32_t /*<jcu_int_detail_error_t>*/  jcu_int_detail_errors_t;
+
+
+/**
+* @enum   jcu_swap_t
+* @brief  SampleEnum
+*
+*    - SymbolA - 0, NULL
+*    - SymbolB - 1
+*/
+typedef int_t jcu_swap_t;
+#define JCU_SWAP_NONE                           (0x00)
+#define JCU_SWAP_BYTE                           (0x01)
+#define JCU_SWAP_WORD                           (0x02)
+#define JCU_SWAP_WORD_AND_BYTE                  (0x03)
+#define JCU_SWAP_LONG_WORD                      (0x04)
+#define JCU_SWAP_LONG_WORD_AND_BYTE             (0x05)
+#define JCU_SWAP_LONG_WORD_AND_WORD             (0x06)
+#define JCU_SWAP_LONG_WORD_AND_WORD_AND_BYTE    (0x07)
+
+
+/**
+* @struct  jcu_buffer_t
+* @brief  Buffer settings
+*/
+typedef struct {
+    jcu_swap_t    swapSetting;
+    uint32_t     *address;
+} jcu_buffer_t;
+
+
+/**
+* @struct  jcu_buffer_param_t
+* @brief  Buffer parameter for input and output
+*/
+typedef struct {
+    jcu_buffer_t  source;
+    jcu_buffer_t  destination;
+    int16_t       lineOffset;
+} jcu_buffer_param_t;
+
+
+/* Section: Global */
+/**
+* @enum   jcu_sub_sampling_t
+* @brief  Sub sampling settings for decoding
+*
+*    - JCU_SUB_SAMPLING_1_1 - 0x00 = 1/1
+*    - JCU_SUB_SAMPLING_1_2 - 0x01 = 1/2
+*    - JCU_SUB_SAMPLING_1_4 - 0x02 = 1/4
+*    - JCU_SUB_SAMPLING_1_8 - 0x03 = 1/8
+*/
+typedef enum {
+    JCU_SUB_SAMPLING_1_1 = 0x00,
+    JCU_SUB_SAMPLING_1_2 = 0x01,
+    JCU_SUB_SAMPLING_1_4 = 0x02,
+    JCU_SUB_SAMPLING_1_8 = 0x03
+} jcu_sub_sampling_t;
+
+
+/**
+* @enum   jcu_decode_format_t
+* @brief  Kind of pixel format can process the decoding
+*
+*    - JCU_OUTPUT_YCbCr422 - 0x00
+*    - JCU_OUTPUT_ARGB8888 - 0x01
+*    - JCU_OUTPUT_RGB565 - 0x02
+*/
+typedef enum {
+    JCU_OUTPUT_YCbCr422 = 0x00,
+    JCU_OUTPUT_ARGB8888 = 0x01,
+    JCU_OUTPUT_RGB565   = 0x02
+} jcu_decode_format_t;
+
+
+/**
+* @enum   jcu_cbcr_offset_t
+* @brief  Cb/Cr offset
+*
+*    - JCU_CBCR_OFFSET_0 - 0 = No offset
+*    - JCU_CBCR_OFFSET_128 - 1 = +128 offset
+*/
+typedef enum {
+    JCU_CBCR_OFFSET_0 = 0,
+    JCU_CBCR_OFFSET_128 = 1
+} jcu_cbcr_offset_t;
+
+
+/**
+* @enum   jcu_jpeg_format_t
+* @brief  Kind of pixel format for the jpeg file format when decoding
+*
+*    - JCU_JPEG_YCbCr444 - 0
+*    - JCU_JPEG_YCbCr422 - 1
+*    - JCU_JPEG_YCbCr420 - 2
+*    - JCU_JPEG_YCbCr411 - 6
+*/
+typedef enum {
+    JCU_JPEG_YCbCr444   = 0x00,
+    JCU_JPEG_YCbCr422   = 0x01,
+    JCU_JPEG_YCbCr420   = 0x02,
+    JCU_JPEG_YCbCr411   = 0x06
+} jcu_jpeg_format_t;
+
+
+/**
+* @struct  jcu_image_info_t
+* @brief  Image information data store variable
+*/
+typedef struct {
+    uint32_t            width;
+    uint32_t            height;
+    jcu_jpeg_format_t   encodedFormat;
+} jcu_image_info_t;
+
+
+/* Section: Global */
+/**
+* @enum   jcu_table_no_t
+* @brief  The index of the table
+*
+*    - JCU_TABLE_NO_0 - 0
+*    - JCU_TABLE_NO_1 - 1
+*    - JCU_TABLE_NO_2 - 2
+*    - JCU_TABLE_NO_3 - 3
+*/
+typedef enum {
+    JCU_TABLE_NO_0 = 0,
+    JCU_TABLE_NO_1 = 1,
+    JCU_TABLE_NO_2 = 2,
+    JCU_TABLE_NO_3 = 3
+} jcu_table_no_t;
+
+
+/**
+* @enum   jcu_huff_t
+* @brief  Kind of Huffman table
+*
+*    - JCU_HUFFMAN_AC - 0
+*    - JCU_HUFFMAN_DC - 1
+*/
+typedef enum {
+    JCU_HUFFMAN_AC,
+    JCU_HUFFMAN_DC
+} jcu_huff_t;
+
+
+/**
+* @enum   jcu_color_element_t
+* @brief  Kind of color data for using the encoder parameter
+*
+*    - JCU_ELEMENT_Y - 0
+*    - JCU_ELEMENT_Cb - 1
+*    - JCU_ELEMENT_Cr - 2
+*/
+typedef enum {
+    JCU_ELEMENT_Y,
+    JCU_ELEMENT_Cb,
+    JCU_ELEMENT_Cr
+} jcu_color_element_t;
+
+
+/**
+* @struct  jcu_decode_param_t
+* @brief  Setting parameter for the Decoding
+*/
+typedef struct {
+    jcu_sub_sampling_t  verticalSubSampling;
+    jcu_sub_sampling_t  horizontalSubSampling;
+    jcu_decode_format_t decodeFormat;
+    jcu_cbcr_offset_t   outputCbCrOffset;
+    uint8_t             alpha;
+} jcu_decode_param_t;
+
+
+/**
+* @struct  jcu_encode_param_t
+* @brief  Setting parameter for the Encoding
+*/
+typedef struct {
+    jcu_jpeg_format_t   encodeFormat;
+    int32_t             QuantizationTable[JCU_COLOR_ELEMENT_NUM];
+    int32_t             HuffmanTable[JCU_COLOR_ELEMENT_NUM];
+    uint32_t            DRI_value;
+    uint32_t            width;
+    uint32_t            height;
+    jcu_cbcr_offset_t   inputCbCrOffset;
+} jcu_encode_param_t;
+
+
+/* Section: Global */
+/**
+* @enum   jcu_codec_status_t
+* @brief  Codec type
+*
+*    - JCU_CODEC_NOT_SELECTED - -1
+*    - JCU_STATUS_ENCODE - 0
+*    - JCU_STATUS_DECODE - 1
+*/
+typedef enum {
+    JCU_CODEC_NOT_SELECTED  = -1,
+    JCU_STATUS_ENCODE       = 0,
+    JCU_STATUS_DECODE       = 1
+} jcu_codec_status_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+jcu_errorcode_t R_JCU_Initialize( void *const  NullConfig );
+jcu_errorcode_t R_JCU_Terminate(void);
+jcu_errorcode_t R_JCU_TerminateAsync( r_ospl_async_t *const  async );
+jcu_errorcode_t R_JCU_SelectCodec(const jcu_codec_t codec);
+jcu_errorcode_t R_JCU_Start(void);
+jcu_errorcode_t R_JCU_StartAsync( r_ospl_async_t *const  async );
+jcu_errorcode_t R_JCU_SetCountMode(const jcu_count_mode_param_t *const buffer);
+jcu_errorcode_t R_JCU_Continue(const jcu_continue_type_t type);
+jcu_errorcode_t R_JCU_ContinueAsync(const jcu_continue_type_t type, r_ospl_async_t *const  async);
+void            R_JCU_GetAsyncStatus(const jcu_async_status_t **const  out_Status);
+jcu_errorcode_t R_JCU_SetDecodeParam(const jcu_decode_param_t *const decode, const jcu_buffer_param_t *const buffer);
+jcu_errorcode_t R_JCU_SetPauseForImageInfo(const bool_t is_pause);
+jcu_errorcode_t R_JCU_GetImageInfo(jcu_image_info_t *const buffer);
+jcu_errorcode_t R_JCU_SetErrorFilter(jcu_int_detail_errors_t filter);
+jcu_errorcode_t R_JCU_SetQuantizationTable(const jcu_table_no_t tableNo, const uint8_t *const table);
+jcu_errorcode_t R_JCU_SetHuffmanTable(const jcu_table_no_t tableNo, const jcu_huff_t type, const uint8_t *const table);
+jcu_errorcode_t R_JCU_SetEncodeParam(const jcu_encode_param_t *const encode, const jcu_buffer_param_t *const buffer);
+jcu_errorcode_t R_JCU_GetEncodedSize(size_t *const out_Size);
+jcu_errorcode_t R_JCU_Set2ndCacheAttribute( r_ospl_axi_cache_attribute_t const  read_cache_attribute,
+        r_ospl_axi_cache_attribute_t const  write_cache_attribute );
+
+#ifndef R_OSPL_NDEBUG
+void            R_JCU_PrintRegisters(void);
+#endif
+
+/* For interrupt callback */
+errnum_t        R_JCU_OnInterrupting( const r_ospl_interrupt_t *const  InterruptSource );
+errnum_t        R_JCU_OnInterrupted(void);
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* #define JCU_API_H_ */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/inc/r_jcu_local.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,481 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: jcu_local.h $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description  : JCU driver local parameter
+******************************************************************************/
+
+#ifndef JCU_LOCAL_H
+#define JCU_LOCAL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_jcu_api.h"
+#include    "r_jcu_user.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+typedef struct st_jcu_i_lock_t   jcu_i_lock_t;  /*[jcu_i_lock_t]*/
+
+/*! [jcu_internal_information_t] Internal Information for this driver */
+typedef struct {
+    jcu_codec_status_t             Codec;
+    bool_t                         IsCountMode;
+    jcu_int_detail_errors_t        ErrorFilter;  /* 1=Enable */
+
+    jcu_async_status_t             AsyncStatus;
+    r_ospl_caller_t                InterruptCallbackCaller;
+    jcu_i_lock_t                  *I_Lock;
+    const r_ospl_i_lock_vtable_t  *I_LockVTable;
+    bool_t                         Is_I_LockMaster;
+    r_ospl_async_t                *AsyncForFinalize;
+} jcu_internal_information_t;
+
+/*[jcu_i_lock_t]*/
+struct st_jcu_i_lock_t {
+    bool_t        IsLock;
+    bool_t        IsRequestedFinalize;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+jcu_internal_information_t  *R_JCU_GetInternalInformation(void);
+jcu_i_lock_t    *R_JCU_GetILockObject(void);
+void             R_JCU_I_LOCK_Finalize(void);
+jcu_errorcode_t  R_JCU_TerminateStep2(void);
+
+#ifdef      JCU_PARAMETER_CHECK
+jcu_errorcode_t JCU_ParaCheckStart(void);
+jcu_errorcode_t JCU_ParaCheckSetCountMode(const jcu_count_mode_param_t  *const buffer);
+jcu_errorcode_t JCU_ParaCheckSelectCodec(const jcu_codec_t codec);
+jcu_errorcode_t JCU_ParaCheckSetCallbackFunc(const uintptr_t type);
+jcu_errorcode_t JCU_ParaCheckSetDecodeParam(const jcu_decode_param_t *const decode, const jcu_buffer_param_t *const buffer);
+jcu_errorcode_t JCU_ParaCheckGetImageInfo(const jcu_image_info_t *const buffer);
+jcu_errorcode_t JCU_ParaCheckGetErrorInfo(const jcu_detail_error_t *const errorCode);
+jcu_errorcode_t JCU_ParaCheckSetQuantizationTbl(const jcu_table_no_t tableNo);
+jcu_errorcode_t JCU_ParaCheckSetHuffmanTable(const jcu_table_no_t tableNo, const jcu_huff_t type);
+jcu_errorcode_t JCU_ParaCheckEncodeParam(const jcu_encode_param_t *const encode, const jcu_buffer_param_t *const buffer);
+jcu_errorcode_t JCU_CheckInterruptSource(const uint32_t interruptKind);
+#endif /* JCU_PARAMETER_CHECK */
+
+jcu_errorcode_t JCU_SetRegisterForInitialize(void);
+void JCU_SetRegisterForCodec(const jcu_codec_t codec);
+void JCU_SetRegisterForStart(const jcu_int_detail_error_t error_filter);
+void JCU_SetRegisterForReset(void);
+void JCU_SetRegisterForSetCountMode(const jcu_count_mode_param_t *const buffer);
+void JCU_SetRegisterForContinue(const jcu_continue_type_t type);
+void JCU_SetRegisterForSetDecodePrm(const jcu_decode_param_t *const decode, const jcu_buffer_param_t *const buffer);
+void JCU_SetRegisterForSetQtTable(const jcu_table_no_t tableNo, const uint8_t *const  table);
+void JCU_SetRegisterForSetHuffTbl(const jcu_table_no_t tableNo, const jcu_huff_t type, const uint8_t *const table);
+void JCU_SetRegisterForSetEncodePrm(const jcu_encode_param_t *const encode, const jcu_buffer_param_t *const buffer);
+void JCU_SetRegisterForSetPause(const bool_t is_pause, const jcu_int_detail_errors_t filter);
+void JCU_GetRegisterForGetImageInfo(jcu_image_info_t *const buffer);
+void JCU_GetEncodedSize(size_t *const out_Size);
+void JCU_ClearInterruptFlag(void);
+
+
+/* ->SEC M1.2.2(QAC-1259) */
+/*    If "Value" is signed, this is depend on CPU bit width. */
+/*    But driver code is no problem. */
+/*    This expects 32bit CPU. */
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at left of "=" and right of "=". */
+/*    But this is not depend on compiler spcifications. */
+/* ->MISRA 19.12 ->MISRA 19.13 ->SEC M5.1.2 (1) */
+#define R_SET_REG_BIT_FIELD( Register, BitName, Value ) \
+        ( (Register) = (BitName##_TYPE)( ( (uint32_t)(Register) & (uint32_t)(~(BitName##_MASK) ) ) |\
+        ( (uint32_t)( (uint32_t)(Value) << (BitName##_SHIFT) ) & (uint32_t)(BitName##_MASK) ) ) )
+#define R_GET_REG_BIT_FIELD( Register, BitName ) \
+        ( (BitName##_TYPE)( ( ((uint32_t)(Register)) & (uint32_t)(BitName##_MASK) ) >> (BitName##_SHIFT) ) )
+/* <-SEC M1.2.3(QAC-1259) */
+/* <-SEC R3.6.2(QAC-3345) */
+/* <-MISRA 19.12 <-MISRA 19.13 <-SEC M5.1.2 (1) */
+
+/* Value of register */
+/* 1bit(Flag) */
+#define REG_F_CLR (0u)
+#define REG_F_SET (1u)
+
+/* Bit field name (Register name) */
+
+/* SRST(CPG.SWRSTCR2) */
+#define SRST_MASK       (0x00000002u)
+#define SRST_SHIFT      (1u)
+#define SRST_TYPE       uint8_t
+
+
+/*DSP(JCU.JCMOD) */
+#define DSP_MASK        (0x00000008u)
+#define DSP_SHIFT       (3u)
+#define DSP_TYPE        uint8_t
+
+/*REDU(JCU.JCMOD) */
+#define REDU_MASK       (0x00000007u)
+#define REDU_SHIFT      (0u)
+#define REDU_TYPE       uint8_t
+
+
+/*BRST(JCU.JCCMD) */
+#define BRST_MASK       (0x00000080u)
+#define BRST_SHIFT      (7u)
+#define BRST_TYPE       uint8_t
+
+/*JEND(JCU.JCCMD) */
+#define JEND_MASK       (0x00000004u)
+#define JEND_SHIFT      (2u)
+#define JEND_TYPE       uint8_t
+
+/*JRST(JCU.JCCMD) */
+#define JRST_MASK       (0x00000002u)
+#define JRST_SHIFT      (1u)
+#define JRST_TYPE       uint8_t
+
+/*JSRT(JCU.JCCMD) */
+#define JSRT_MASK       (0x00000001u)
+#define JSRT_SHIFT      (0u)
+#define JSRT_TYPE       uint8_t
+
+
+/*QT3(JCU.JCQTN) */
+#define QT3_MASK        (0x00000030u)
+#define QT3_SHIFT       (4u)
+#define QT3_TYPE        uint8_t
+
+/*QT2(JCU.JCQTN) */
+#define QT2_MASK        (0x0000000Cu)
+#define QT2_SHIFT       (2u)
+#define QT2_TYPE        uint8_t
+
+/*QT1(JCU.JCQTN) */
+#define QT1_MASK        (0x00000003u)
+#define QT1_SHIFT       (0u)
+#define QT1_TYPE        uint8_t
+
+
+/*HTA3(JCU.JCHTN) */
+#define HTA3_MASK       (0x00000020u)
+#define HTA3_SHIFT      (5u)
+#define HTA3_TYPE       uint8_t
+
+/*HTD3(JCU.JCHTN) */
+#define HTD3_MASK       (0x00000010u)
+#define HTD3_SHIFT      (4u)
+#define HTD3_TYPE       uint8_t
+
+/*HTA2(JCU.JCHTN) */
+#define HTA2_MASK       (0x00000008u)
+#define HTA2_SHIFT      (3u)
+#define HTA2_TYPE       uint8_t
+
+/*HTD2(JCU.JCHTN) */
+#define HTD2_MASK       (0x00000004u)
+#define HTD2_SHIFT      (2u)
+#define HTD2_TYPE       uint8_t
+
+/*HTA1(JCU.JCHTN) */
+#define HTA1_MASK       (0x00000002u)
+#define HTA1_SHIFT      (1u)
+#define HTA1_TYPE       uint8_t
+
+/*HTD1(JCU.JCHTN) */
+#define HTD1_MASK       (0x00000001u)
+#define HTD1_SHIFT      (0u)
+#define HTD1_TYPE       uint8_t
+
+
+/*INT7(JCU.JINTE0) Error of restart interval data. JINTE0.INT7 -> JINTS0.INS5 */
+#define INT7_MASK       (0x00000080u)
+#define INT7_SHIFT      (7u)
+#define INT7_TYPE       uint8_t
+
+/*INT6(JCU.JINTE0) Error of Segment total data. JINTE0.INT6 -> JINTS0.INS5 */
+#define INT6_MASK       (0x00000040u)
+#define INT6_SHIFT      (6u)
+#define INT6_TYPE       uint8_t
+
+/*INT5(JCU.JINTE0) Error of MCU block data. JINTE0.INT5 -> JINTS0.INS5 */
+#define INT5_MASK       (0x00000020u)
+#define INT5_SHIFT      (5u)
+#define INT5_TYPE       uint8_t
+
+/*INT3(JCU.JINTE0) */
+#define INT3_MASK       (0x00000008u)
+#define INT3_SHIFT      (3u)
+#define INT3_TYPE       uint8_t
+
+
+/*INS6(JCU.JINTS0) End Core Only */
+#define INS6_MASK       (0x00000040u)
+#define INS6_SHIFT      (6u)
+#define INS6_TYPE       uint8_t
+
+/*INS5(JCU.JINTS0) Decode Error */
+#define INS5_MASK       (0x00000020u)
+#define INS5_SHIFT      (5u)
+#define INS5_TYPE       uint8_t
+
+/*INS3(JCU.JINTS0) Get Image Information */
+#define INS3_MASK       (0x00000008u)
+#define INS3_SHIFT      (3u)
+#define INS3_TYPE       uint8_t
+
+
+/*ERR(JCU.JCDERR) */
+#define ERR_MASK        (0x0000000Fu)
+#define ERR_SHIFT       (0u)
+#define ERR_TYPE        uint8_t
+
+
+/*JOUTRINI(JCU.JIFECNT) */
+#define JOUTRINI_MASK   (0x00004000u)
+#define JOUTRINI_SHIFT  (14u)
+#define JOUTRINI_TYPE   uint32_t
+
+/*JOUTRCMD(JCU.JIFECNT) */
+#define JOUTRCMD_MASK   (0x00002000u)
+#define JOUTRCMD_SHIFT  (13u)
+#define JOUTRCMD_TYPE   uint32_t
+
+/*JOUTC(JCU.JIFECNT) */
+#define JOUTC_MASK      (0x00001000u)
+#define JOUTC_SHIFT     (12u)
+#define JOUTC_TYPE      uint32_t
+
+/*JOUTSWAP(JCU.JIFECNT) */
+#define JOUTSWAP_MASK   (0x00000700u)
+#define JOUTSWAP_SHIFT  (8u)
+#define JOUTSWAP_TYPE   uint32_t
+
+/*DINRINI(JCU.JIFECNT) */
+#define DINRINI_MASK    (0x00000040u)
+#define DINRINI_SHIFT   (6u)
+#define DINRINI_TYPE    uint32_t
+
+/*DINRCMD(JCU.JIFECNT) */
+#define DINRCMD_MASK    (0x00000020u)
+#define DINRCMD_SHIFT   (5u)
+#define DINRCMD_TYPE    uint32_t
+
+/*DINLC(JCU.JIFECNT) */
+#define DINLC_MASK      (0x00000010u)
+#define DINLC_SHIFT     (4u)
+#define DINLC_TYPE      uint32_t
+
+/*DINSWAP(JCU.JIFECNT) */
+#define DINSWAP_MASK    (0x00000007u)
+#define DINSWAP_SHIFT   (0u)
+#define DINSWAP_TYPE    uint32_t
+
+
+/*ESMW(JCU.JIFESOFST) */
+#define ESMW_MASK       (0x00007FFFu)
+#define ESMW_SHIFT      (0u)
+#define ESMW_TYPE       uint32_t
+
+
+/*LINES(JCU.JIFESLC, JCU.JIFDDLC) */
+#define LINES_MASK      (0x0000FFFFu)
+#define LINES_SHIFT     (0u)
+#define LINES_TYPE      uint32_t
+#define LINES_CLEAR     (0u)
+
+
+/*JDATAS(JCU.JIFESLC, JCU.JIFDSDC, JCU.JIFEDDC) */
+#define JDATAS_MASK     (0x0000FFFFu)
+#define JDATAS_SHIFT    (0u)
+#define JDATAS_TYPE     uint32_t
+#define JDATAS_CLEAR    (0u)
+
+
+/*VINTER(JCU.JIFDCNT) */
+#define VINTER_MASK     (0x3C000000u)
+#define VINTER_SHIFT    (28u)
+#define VINTER_TYPE     uint32_t
+
+/*HINTER(JCU.JIFDCNT) */
+#define HINTER_MASK     (0x0C000000u)
+#define HINTER_SHIFT    (26u)
+#define HINTER_TYPE     uint32_t
+
+/*OPF(JCU.JIFDCNT) */
+#define OPF_MASK        (0x03000000u)
+#define OPF_SHIFT       (24u)
+#define OPF_TYPE        uint32_t
+
+/*JINRINI(JCU.JIFDCNT) */
+#define JINRINI_MASK    (0x00004000u)
+#define JINRINI_SHIFT   (14u)
+#define JINRINI_TYPE    uint32_t
+
+/*JINRCMD(JCU.JIFDCNT) */
+#define JINRCMD_MASK    (0x00002000u)
+#define JINRCMD_SHIFT   (13u)
+#define JINRCMD_TYPE    uint32_t
+
+/*JINC(JCU.JIFDCNT) */
+#define JINC_MASK       (0x00001000u)
+#define JINC_SHIFT      (12u)
+#define JINC_TYPE       uint32_t
+
+/*JINSWAP(JCU.JIFDCNT) */
+#define JINSWAP_MASK    (0x00000700u)
+#define JINSWAP_SHIFT   (8u)
+#define JINSWAP_TYPE    uint32_t
+
+/*DOUTRINI(JCU.JIFDCNT) */
+#define DOUTRINI_MASK   (0x00000040u)
+#define DOUTRINI_SHIFT  (6u)
+#define DOUTRINI_TYPE   uint32_t
+
+/*DOUTRCMD(JCU.JIFDCNT) */
+#define DOUTRCMD_MASK   (0x00000020u)
+#define DOUTRCMD_SHIFT  (5u)
+#define DOUTRCMD_TYPE   uint32_t
+
+/*DOUTLC(JCU.JIFDCNT) */
+#define DOUTLC_MASK     (0x00000010u)
+#define DOUTLC_SHIFT    (4u)
+#define DOUTLC_TYPE     uint32_t
+
+/*DOUTSWAP(JCU.JIFDCNT) */
+#define DOUTSWAP_MASK   (0x00000007u)
+#define DOUTSWAP_SHIFT  (0u)
+#define DOUTSWAP_TYPE   uint32_t
+
+
+/*DDMW(JCU.JIFDDOFST) */
+#define DDMW_MASK       (0x00007FFFu)
+#define DDMW_SHIFT      (0u)
+#define DDMW_TYPE       uint32_t
+
+
+/*ALPHA(JCU.JIFDADT) */
+#define ALPHA_MASK      (0x000000FFu)
+#define ALPHA_SHIFT     (0u)
+#define ALPHA_TYPE      uint32_t
+
+
+/*CBTEN(JCU.JINTE1) */
+#define CBTEN_MASK      (0x00000040u)
+#define CBTEN_SHIFT     (6u)
+#define CBTEN_TYPE      uint32_t
+
+/*DINLEN(JCU.JINTE1) */
+#define DINLEN_MASK     (0x00000020u)
+#define DINLEN_SHIFT    (5u)
+#define DINLEN_TYPE     uint32_t
+
+/*JOUTEN(JCU.JINTE1) */
+#define JOUTEN_MASK     (0x00000010u)
+#define JOUTEN_SHIFT    (4u)
+#define JOUTEN_TYPE     uint32_t
+
+/*DBTEN(JCU.JINTE1) */
+#define DBTEN_MASK      (0x00000004u)
+#define DBTEN_SHIFT     (2u)
+#define DBTEN_TYPE      uint32_t
+
+/*JINEN(JCU.JINTE1) */
+#define JINEN_MASK      (0x00000002u)
+#define JINEN_SHIFT     (1u)
+#define JINEN_TYPE      uint32_t
+
+/*DOUTLEN(JCU.JINTE1) */
+#define DOUTLEN_MASK    (0x00000001u)
+#define DOUTLEN_SHIFT   (0u)
+#define DOUTLEN_TYPE    uint32_t
+
+
+/*CBTF(JCU.JINTS1) JINTE1.CBTEN -> JINTS1.CBTF */
+#define CBTF_MASK       (0x00000040u)
+#define CBTF_SHIFT      (6u)
+#define CBTF_TYPE       uint32_t
+
+/*DINLF(JCU.JINTS1) Input Data for Encoding */
+#define DINLF_MASK      (0x00000020u)
+#define DINLF_SHIFT     (5u)
+#define DINLF_TYPE      uint32_t
+
+/*JOUTF(JCU.JINTS1) Output Data for Encoding */
+#define JOUTF_MASK      (0x00000010u)
+#define JOUTF_SHIFT     (4u)
+#define JOUTF_TYPE      uint32_t
+
+/*DBTF(JCU.JINTS1) JINTE1.DBTEN -> JINTS1.DBTF */
+#define DBTF_MASK       (0x00000004u)
+#define DBTF_SHIFT      (2u)
+#define DBTF_TYPE       uint32_t
+
+/*JINF(JCU.JINTS1) Input Data for Decoding */
+#define JINF_MASK       (0x00000002u)
+#define JINF_SHIFT      (1u)
+#define JINF_TYPE       uint32_t
+
+/*DOUTLF(JCU.JINTS1) Output Data for Decoding */
+#define DOUTLF_MASK     (0x00000001u)
+#define DOUTLF_SHIFT    (0u)
+#define DOUTLF_TYPE     uint32_t
+
+
+/*DINYCHG(JCU.JIFESVSZ) */
+#define DINYCHG_MASK     (0x00008000u)
+#define DINYCHG_SHIFT    (15u)
+#define DINYCHG_TYPE     uint32_t
+
+/*DOUTYCHG(JCU.JIFESHSZ) */
+#define DOUTYCHG_MASK     (0x00008000u)
+#define DOUTYCHG_SHIFT    (15u)
+#define DOUTYCHG_TYPE     uint32_t
+
+/* Others */
+#define JCU_JINTS1_ALL  ( CBTF_MASK | DINLF_MASK | JOUTF_MASK | DBTF_MASK | JINF_MASK | DOUTLF_MASK )
+#define SHIFT_16BITS    (16u)                               /* 16bit-SHIFT */
+#define SHIFT_8BITS     (8u)                                /* 8bit-SHIFT */
+#define JCU_SHIFT_JINTS1 (8)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* JCU_LOCAL_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/inc/r_jcu_pl.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,78 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: jcu_pl.h $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description  : Sample Data
+******************************************************************************/
+
+#ifndef JCU_PL_H
+#define JCU_PL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_jcu_api.h"
+#include  "r_ospl.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void      R_JCU_SetDefaultAsync( r_ospl_async_t *const  Async,  r_ospl_async_type_t AsyncType );
+errnum_t  R_JCU_OnInitialize(void);
+errnum_t  R_JCU_OnFinalize( errnum_t e );
+errnum_t  R_JCU_SetInterruptCallbackCaller( const r_ospl_caller_t *const  Caller );
+void      R_JCU_OnEnableInterrupt( jcu_interrupt_lines_t const  Enables );
+void      R_JCU_OnDisableInterrupt( jcu_interrupt_lines_t const  Disables1 );
+errnum_t  R_JCU_OnInterruptDefault( const r_ospl_interrupt_t *const  InterruptSource,
+                                    const r_ospl_caller_t *const  Caller );
+
+/* For integrating driver */
+bool_t    R_JCU_I_LOCK_Replace( void *const  I_Lock,  const r_ospl_i_lock_vtable_t *const  I_LockVTable );
+bool_t    R_JCU_DisableInterrupt(void);
+void      R_JCU_EnableInterrupt(void);
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _JCU_PL_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/inc/r_jcu_user.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,67 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* $FileName: jcu_user.h $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 32 $
+* $Date:: 2014-02-21 20:21:46 +0900#$
+* Description  : JCU driver User Configuration
+******************************************************************************/
+
+
+/* This file is included from "r_jcu_api.h" */
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+#ifndef JCU_USER_H
+#define JCU_USER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Parameter check */
+#define     JCU_PARAMETER_CHECK
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* JCU_USER_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/jcu_driver/JPEG_Coverter.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,614 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         jpeg_coverter.cpp
+* @version      1.00
+* $Rev: 1 $
+* $Date:: 2015-08-06 16:33:52 +0900#$
+* @brief        Decodes JPEG data and encodes to JPEG data
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  <string.h>
+#include  <stdio.h>
+#include  "r_typedefs.h"
+#include  "r_jcu_api.h"
+#include  "JPEG_Converter.h"
+#include  "converter_wrapper.h"
+#include  "mbed_error.h"
+#include  "rtos.h"
+#include  "Semaphore.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define  QUANTIZATION_TABLE_SIZE    (64u)
+#define  HUFFMAN_TABLE_DC_SIZE      (28u)
+#define  HUFFMAN_TABLE_AC_SIZE      (178u)
+#define  JPEG_HEADER_LETTER_1       (0xFFu)
+#define  JPEG_HEADER_LETTER_2       (0xD8u)
+#define  ALPHA_VAL_MAX              (0xFF)
+#define  LOC_KIND_COLOR_FORMAT      (3u)
+
+#define  ENC_SIZE_MAX               (1024 * 30)
+#define  MASK_8BYTE                 (0xFFFFFFF8)
+
+    /*[QuantizationTable_Y]*/
+    /* Quality is IJG75 */
+    static const uint8_t  csaDefaultQuantizationTable_Y[QUANTIZATION_TABLE_SIZE] = {
+        8, 6, 5, 8, 12, 20, 26, 31,
+        6, 6, 7, 10, 13, 29, 30, 28,
+        7, 7, 8, 12, 20, 29, 35, 28,
+        7, 9, 11, 15, 26, 44, 40, 31,
+        9, 11, 19, 28, 34, 55, 52, 39,
+        12, 18, 28, 32, 41, 52, 57, 46,
+        25, 32, 39, 44, 52, 61, 60, 51,
+        36, 46, 48, 49, 56, 50, 52, 50
+    };
+
+    /*[QuantizationTable_C]*/
+    /* Quality is IJG75 */
+    static const uint8_t  csaDefaultQuantizationTable_C[QUANTIZATION_TABLE_SIZE] = {
+        9, 9, 12, 24, 50, 50, 50, 50,
+        9, 11, 13, 33, 50, 50, 50, 50,
+        12, 13, 28, 50, 50, 50, 50, 50,
+        24, 33, 50, 50, 50, 50, 50, 50,
+        50, 50, 50, 50, 50, 50, 50, 50,
+        50, 50, 50, 50, 50, 50, 50, 50,
+        50, 50, 50, 50, 50, 50, 50, 50,
+        50, 50, 50, 50, 50, 50, 50, 50
+    };
+
+    /*[HuffmanTable_Y_DC]*/
+    /* Example written in ITU-T T81 specification */
+    static const uint8_t  csaDefaultHuffmanTable_Y_DC[HUFFMAN_TABLE_DC_SIZE] = {
+        0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B
+    };
+
+    /*[HuffmanTable_C_DC]*/
+    /* Example written in ITU-T T81 specification */
+    static const uint8_t  csaDefaultHuffmanTable_C_DC[HUFFMAN_TABLE_DC_SIZE] = {
+        0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B
+    };
+
+    /*[HuffmanTable_Y_AC]*/
+    /* Example written in ITU-T T81 specification */
+    static const uint8_t  csaDefaultHuffmanTable_Y_AC[HUFFMAN_TABLE_AC_SIZE] = {
+        0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D,
+        0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
+        0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0,
+        0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28,
+        0x29, 0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
+        0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
+        0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
+        0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7,
+        0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5,
+        0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2,
+        0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8,
+        0xF9, 0xFA
+    };
+
+    /*[HuffmanTable_C_AC]*/
+    /* Example written in ITU-T T81 specification */
+    static const uint8_t  csaDefaultHuffmanTable_C_AC[HUFFMAN_TABLE_AC_SIZE] = {
+        0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00, 0x01, 0x02, 0x77,
+        0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
+        0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0,
+        0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26,
+        0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
+        0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
+        0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+        0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5,
+        0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3,
+        0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA,
+        0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8,
+        0xF9, 0xFA
+    };
+
+typedef void (JPEG_CallbackFunc_t)(JPEG_Converter::jpeg_conv_error_t err_code);
+
+static uint32_t             driver_ac_count = 0;
+static bool                 jcu_error_flag;
+static JPEG_CallbackFunc_t* pJPEG_ConverterCallback;
+Semaphore                   jpeg_converter_semaphore(1);
+
+
+/**************************************************************************//**
+ * @brief       Callback function from JCU async mode
+ * @param[in]   mbed_jcu_err_t          err_code       : JCU result
+ * @retval      None
+******************************************************************************/
+void JPEG_CallbackFunction(mbed_jcu_err_t err_code) {
+    if (pJPEG_ConverterCallback != NULL) {
+        pJPEG_ConverterCallback((JPEG_Converter::jpeg_conv_error_t)err_code);
+    }
+    if (err_code != MBED_JCU_E_OK) {
+        jcu_error_flag = true;
+    }
+    jpeg_converter_semaphore.release(); // RELEASE
+} /* End of callback function method () */
+
+/**************************************************************************//**
+ * @brief       Constructor of the JPEG_Converter class
+ * @param[in]   None
+ * @retval      None
+******************************************************************************/
+JPEG_Converter::JPEG_Converter(void) {
+    jcu_errorcode_t           jcu_error;
+    
+    if (driver_ac_count == 0) {
+        jcu_error = R_JCU_Initialize(NULL);
+        if (jcu_error == JCU_ERROR_OK) {
+            driver_ac_count++;
+            jcu_error_flag = false;
+        }
+    } else {
+        driver_ac_count++;
+    }
+} /* End of constructor method () */
+
+/**************************************************************************//**
+ * @brief       Destructor of the JPEG_Converter class
+ * @param[in]   None
+ * @retval      None
+******************************************************************************/
+JPEG_Converter::~JPEG_Converter(void) {
+    if (driver_ac_count > 0) {
+        driver_ac_count--;
+        if (driver_ac_count == 0) {
+            (void)R_JCU_Terminate();
+        }
+    }
+} /* End of destructor method () */
+
+/**************************************************************************//**
+ * @brief         JPEG data decode to bitmap
+ * @param[in]     void*                 pJpegBuff       : Input JPEG data address
+ * @param[in/out] bitmap_buff_info_t*   psOutputBuff    : Output bitmap data address
+ * @retval        error code
+******************************************************************************/
+JPEG_Converter::jpeg_conv_error_t
+JPEG_Converter::decode(void* pJpegBuff, bitmap_buff_info_t* psOutputBuff) {
+    decode_options_t Options;
+    
+    return (decode(pJpegBuff, psOutputBuff, &Options));
+} /* End of method decode() */
+
+/**************************************************************************//**
+ * @brief       JPEG data decode to bitmap
+ * @param[in]     void*                 pJpegBuff       : Input JPEG data address
+ * @param[in/out] bitmap_buff_info_t*   psOutputBuff    : Output bitmap data address
+ * @param[in]     decode_options_t*     pOptions        : Decode option(Optional)
+ * @retval      error code
+******************************************************************************/
+JPEG_Converter::jpeg_conv_error_t
+JPEG_Converter::decode(void* pJpegBuff, bitmap_buff_info_t* psOutputBuff, decode_options_t* pOptions) {
+    jpeg_conv_error_t           e;
+    jcu_errorcode_t             jcu_error;
+    jcu_decode_param_t          decode;
+    jcu_buffer_param_t          buffer;
+    uint8_t*            pBuff = (uint8_t *)pJpegBuff;
+    const jcu_async_status_t*   status;
+    jcu_image_info_t            image_info;
+    bool                        mutex_release = false;
+    
+    // Check JCU initialized
+    if (driver_ac_count > 0) {
+        size_t calc_height;
+        size_t calc_width;
+        
+        calc_height = psOutputBuff->height * (2 ^ pOptions->vertical_sub_sampling);
+        calc_width  = psOutputBuff->width * (2 ^ pOptions->horizontal_sub_sampling);
+        
+        // Check input address
+        if ((pJpegBuff == NULL) || (psOutputBuff == NULL) || (pOptions == NULL)) {
+            e = JPEG_CONV_PARAM_ERR;  // Input address error
+            goto  fin;
+        }
+        // Check JPEG header
+        if (((uint32_t)(pBuff[0]) != JPEG_HEADER_LETTER_1) ||
+            ((uint32_t)(pBuff[1]) != JPEG_HEADER_LETTER_2)) {
+            e = JPEG_CONV_FORMA_ERR;  // JPEG data is not in ROM
+            goto  fin;
+        }
+        // JCU Error reset
+        if (jcu_error_flag == true) {
+            (void)R_JCU_Terminate();
+            (void)R_JCU_Initialize(NULL);
+            jcu_error_flag = false;
+        }
+        // Get mutex
+        if (pOptions->p_DecodeCallBackFunc == NULL) {
+            jpeg_converter_semaphore.wait(0xFFFFFFFFuL); // WAIT
+        } else {
+            if (!jpeg_converter_semaphore.wait(0)) {
+                e = JPEG_CONV_BUSY;  // Busy
+                goto  fin;
+            }
+        }
+        // Select decode
+        jcu_error = R_JCU_SelectCodec( JCU_DECODE );
+        if (jcu_error != JCU_ERROR_OK) {
+            e = JPEG_CONV_JCU_ERR;
+            mutex_release = true;
+            goto fin;
+        }
+        
+        buffer.source.swapSetting       = JCU_SWAP_LONG_WORD_AND_WORD_AND_BYTE;
+        buffer.source.address           = (uint32_t *)pBuff;
+        buffer.lineOffset               = (int16_t)psOutputBuff->width;
+        buffer.destination.address      = (uint32_t *)psOutputBuff->buffer_address;
+        decode.decodeFormat             = (jcu_decode_format_t)psOutputBuff->format;
+        buffer.destination.swapSetting  = (jcu_swap_t)pOptions->output_swapsetting;
+        decode.outputCbCrOffset         = (jcu_cbcr_offset_t)pOptions->output_cb_cr_offset;
+        decode.alpha                    = pOptions->alpha;
+        decode.horizontalSubSampling    = (jcu_sub_sampling_t)pOptions->horizontal_sub_sampling;
+        decode.verticalSubSampling      = (jcu_sub_sampling_t)pOptions->vertical_sub_sampling;
+
+        jcu_error = R_JCU_SetDecodeParam(&decode, &buffer);
+        if (jcu_error != JCU_ERROR_OK) {
+            e = JPEG_CONV_FORMA_ERR;
+            mutex_release = true;
+            jcu_error_flag = false;
+            goto fin;
+        }
+
+        if (pOptions->check_jpeg_format != false) {
+            jcu_error = R_JCU_SetPauseForImageInfo(true);
+            if (jcu_error != JCU_ERROR_OK) {
+                e = JPEG_CONV_JCU_ERR;
+                mutex_release = true;
+                jcu_error_flag = false;
+                goto fin;
+            }
+        }
+        if (pOptions->p_DecodeCallBackFunc == NULL) {
+            jcu_error = R_JCU_Start();
+            mutex_release = true;
+            if (jcu_error != JCU_ERROR_OK) {
+                e = JPEG_CONV_JCU_ERR;
+                jcu_error_flag = false;
+                goto fin;
+            }
+            if (pOptions->check_jpeg_format != false) {
+                R_JCU_GetAsyncStatus( &status );
+                if (status -> IsPaused == false) {
+                    e = JPEG_CONV_JCU_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+                if ((status->SubStatusFlags & JCU_SUB_INFOMATION_READY) == 0) {
+                    e = JPEG_CONV_JCU_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+                jcu_error = R_JCU_GetImageInfo( &image_info );
+                if (jcu_error != JCU_ERROR_OK) {
+                    e = JPEG_CONV_JCU_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+                if ((image_info.width == 0u) || (image_info.height == 0u) || 
+                    (image_info.width > calc_width) || 
+                    (image_info.height > calc_height)) {
+                    e = JPEG_CONV_FORMA_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+                if ((image_info.encodedFormat != JCU_JPEG_YCbCr444) &&
+                    (image_info.encodedFormat != JCU_JPEG_YCbCr422) &&
+                    (image_info.encodedFormat != JCU_JPEG_YCbCr420) &&
+                    (image_info.encodedFormat != JCU_JPEG_YCbCr411)) {
+                    e = JPEG_CONV_FORMA_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+                jcu_error = R_JCU_Continue(JCU_IMAGE_INFO);
+                if (jcu_error != JCU_ERROR_OK) {
+                    e = JPEG_CONV_JCU_ERR;
+                    jcu_error_flag = false;
+                    goto fin;
+                }
+            }
+        } else {
+            pJPEG_ConverterCallback = pOptions->p_DecodeCallBackFunc;
+            jcu_error = R_wrpper_set_decode_callback((mbed_CallbackFunc_t*)JPEG_CallbackFunction, (size_t)calc_width, calc_height);
+            if (jcu_error != JCU_ERROR_OK) {
+                e = JPEG_CONV_JCU_ERR;
+                mutex_release = true;
+                goto fin;
+            }
+        }
+        e = JPEG_CONV_OK;
+    }
+    else
+    {
+        e = JPEG_CONV_JCU_ERR;
+    }
+fin:
+    if (mutex_release == true) {
+        jpeg_converter_semaphore.release(); // RELEASE
+    }
+
+    return  e;
+} /* End of method decode() */
+
+
+/**************************************************************************//**
+ * @brief       Bitmap data encode to JPEG
+ * @param[in]   bitmap_buff_info_t*     psInputBuff     : Input bitmap data address
+ * @param[out]  void*                   pJpegBuff       : Output JPEG data address
+ * @param[out]  size_t*                 pEncodeSize     : Encode size address
+ * @retval      error code
+******************************************************************************/
+JPEG_Converter::jpeg_conv_error_t
+JPEG_Converter::encode(bitmap_buff_info_t* psInputBuff, void* pJpegBuff, size_t* pEncodeSize ) {
+    encode_options_t Options;
+    
+    return (encode(psInputBuff, pJpegBuff, pEncodeSize, &Options));
+} /* End of method encode() */
+
+
+/**************************************************************************//**
+ * @brief       Bitmap data encode to JPEG
+ * @param[in]   bitmap_buff_info_t*     psInputBuff     : Input bitmap data address
+ * @param[out]  void*                   pJpegBuff       : Output JPEG data address
+ * @param[out]  size_t*                 pEncodeSize     : Encode size address
+ * @param[in]   encode_options_t*       pOptions        : Encode option(Optional)
+ * @retval      error code
+******************************************************************************/
+JPEG_Converter::jpeg_conv_error_t
+JPEG_Converter::encode(bitmap_buff_info_t* psInputBuff, void* pJpegBuff, size_t* pEncodeSize, encode_options_t* pOptions ) {
+
+    jpeg_conv_error_t   e;
+    jcu_errorcode_t     jcu_error;
+    jcu_buffer_param_t  buffer;
+    uint8_t*            TableAddress;
+    jcu_encode_param_t  encode;
+    jcu_count_mode_param_t      count_para;
+    int32_t     encode_count;
+    int32_t    size_max_count = 1;
+    size_t      BufferSize = pOptions->encode_buff_size;
+    const jcu_async_status_t*  status;
+    bool                        mutex_release = false;
+
+    // Check JCU initialized
+    if (driver_ac_count > 0) {
+        // Check input address
+        if ((pJpegBuff == NULL) || (psInputBuff == NULL) || (pEncodeSize == NULL)) {
+            e = JPEG_CONV_PARAM_ERR;  // Input address error
+            goto  fin;
+        }
+        // JCU Error reset
+        if (jcu_error_flag == true) {
+            (void)R_JCU_Terminate();
+            (void)R_JCU_Initialize(NULL);
+            jcu_error_flag = false;
+        }
+        // Get mutex
+        if ( pOptions->p_EncodeCallBackFunc == NULL ) {
+            jpeg_converter_semaphore.wait(0xFFFFFFFFuL); // WAIT
+        } else {
+            if (!jpeg_converter_semaphore.wait(0)) {
+                e = JPEG_CONV_BUSY;  // Busy
+                goto  fin;
+            }
+        }
+        // Select encode
+        jcu_error = R_JCU_SelectCodec(JCU_ENCODE);
+        if (jcu_error != JCU_ERROR_OK) {
+            e = JPEG_CONV_JCU_ERR;
+            mutex_release = true;
+            goto fin;
+        }
+        /* Set tables */
+        if ( pOptions->quantization_table_Y != NULL ) {
+            TableAddress = (uint8_t*)pOptions->quantization_table_Y;
+        } else {
+            TableAddress = (uint8_t*)csaDefaultQuantizationTable_Y;
+        }
+        jcu_error = R_JCU_SetQuantizationTable( JCU_TABLE_NO_0, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if ( pOptions->quantization_table_C != NULL ) {
+            TableAddress = (uint8_t*)pOptions->quantization_table_C;
+        } else {
+            TableAddress = (uint8_t*)csaDefaultQuantizationTable_C;
+        }
+        jcu_error = R_JCU_SetQuantizationTable( JCU_TABLE_NO_1, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if ( pOptions->huffman_table_Y_DC != NULL ) {
+            TableAddress = (uint8_t*)pOptions->huffman_table_Y_DC;
+        } else {
+            TableAddress = (uint8_t*)csaDefaultHuffmanTable_Y_DC;
+        }
+        jcu_error = R_JCU_SetHuffmanTable( JCU_TABLE_NO_0, JCU_HUFFMAN_DC, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if ( pOptions->huffman_table_C_DC != NULL ) {
+            TableAddress = (uint8_t*)pOptions->huffman_table_C_DC;
+        } else {
+            TableAddress = (uint8_t*)csaDefaultHuffmanTable_C_DC;
+        }
+        jcu_error = R_JCU_SetHuffmanTable( JCU_TABLE_NO_1, JCU_HUFFMAN_DC, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if ( pOptions->huffman_table_Y_AC != NULL ) {
+            TableAddress = (uint8_t*)pOptions->huffman_table_Y_AC;
+        } else {
+            TableAddress = (uint8_t*)csaDefaultHuffmanTable_Y_AC;
+        }
+        jcu_error = R_JCU_SetHuffmanTable( JCU_TABLE_NO_0, JCU_HUFFMAN_AC, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if ( pOptions->huffman_table_C_AC != NULL ) {
+            TableAddress = (uint8_t*)pOptions->huffman_table_C_AC;
+        } else {
+            TableAddress = (uint8_t*)csaDefaultHuffmanTable_C_AC;
+        }
+        jcu_error = R_JCU_SetHuffmanTable( JCU_TABLE_NO_1, JCU_HUFFMAN_AC, (uint8_t*)TableAddress );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+
+        // JPEG encode
+        buffer.source.swapSetting       = (jcu_swap_t)pOptions->input_swapsetting;
+        buffer.source.address           = (uint32_t *)psInputBuff->buffer_address;
+        buffer.destination.swapSetting  = JCU_SWAP_LONG_WORD_AND_WORD_AND_BYTE;
+        buffer.destination.address      = (uint32_t *)pJpegBuff;
+        buffer.lineOffset               = psInputBuff->width;
+        encode.encodeFormat = (jcu_jpeg_format_t)JCU_JPEG_YCbCr422;
+        encode.QuantizationTable[ JCU_ELEMENT_Y  ] = JCU_TABLE_NO_0;
+        encode.QuantizationTable[ JCU_ELEMENT_Cb ] = JCU_TABLE_NO_1;
+        encode.QuantizationTable[ JCU_ELEMENT_Cr ] = JCU_TABLE_NO_1;
+        encode.HuffmanTable[ JCU_ELEMENT_Y  ] = JCU_TABLE_NO_0;
+        encode.HuffmanTable[ JCU_ELEMENT_Cb ] = JCU_TABLE_NO_1;
+        encode.HuffmanTable[ JCU_ELEMENT_Cr ] = JCU_TABLE_NO_1;
+        encode.DRI_value = pOptions->DRI_value;
+        if ( pOptions->width != 0 ) {
+            encode.width  = pOptions->width;
+        } else {
+            encode.width  = psInputBuff->width;
+        }
+        if ( pOptions->height != 0 ) {
+            encode.height = pOptions->height;
+        } else {
+            encode.height = psInputBuff->height;
+        }
+        encode.inputCbCrOffset = (jcu_cbcr_offset_t)pOptions->input_cb_cr_offset;
+        jcu_error = R_JCU_SetEncodeParam( &encode, &buffer );
+        if ( jcu_error != JCU_ERROR_OK ) {
+            e = JPEG_CONV_PARAM_RANGE_ERR;
+            mutex_release = true;
+            jcu_error_flag = true;
+            goto fin;
+        }
+        if (pOptions->encode_buff_size > 0) {
+
+            while(BufferSize > ENC_SIZE_MAX) {
+                size_max_count *= 2;
+                BufferSize /= 2;
+            }
+            BufferSize = BufferSize & MASK_8BYTE;
+            
+            count_para.inputBuffer.isEnable       = false;
+            count_para.inputBuffer.isInitAddress  = false;
+            count_para.inputBuffer.restartAddress = NULL;
+            count_para.inputBuffer.dataCount      = 0;
+            count_para.outputBuffer.isEnable       = true;
+            count_para.outputBuffer.isInitAddress  = false;
+            count_para.outputBuffer.restartAddress = NULL;
+            count_para.outputBuffer.dataCount      = BufferSize;
+            
+            R_JCU_SetCountMode(&count_para);
+        } else {
+            size_max_count = 0;
+        }
+        // Check async
+        if ( pOptions->p_EncodeCallBackFunc == NULL ) {
+            jcu_error = R_JCU_Start();
+            mutex_release = true;
+            if ( jcu_error != JCU_ERROR_OK ) {
+                e = JPEG_CONV_JCU_ERR;
+                jcu_error_flag = true;
+                goto fin;
+            }
+            if (pOptions->encode_buff_size > 0) {
+                // Check Pause flag
+                R_JCU_GetAsyncStatus( &status );
+                for ( encode_count = 1; (encode_count < size_max_count) && (status->IsPaused != false); encode_count++) {
+                    if ((status->SubStatusFlags & JCU_SUB_ENCODE_OUTPUT_PAUSE) == 0) {
+                        e = JPEG_CONV_JCU_ERR;
+                        jcu_error_flag = true;
+                        goto fin;
+                    }
+                    jcu_error = R_JCU_Continue( JCU_OUTPUT_BUFFER );
+                    if (jcu_error != JCU_ERROR_OK) {
+                        e = JPEG_CONV_JCU_ERR;
+                        jcu_error_flag = true;
+                        goto fin;
+                    }
+                    R_JCU_GetAsyncStatus( &status );
+                }
+                if (status->IsPaused != false) {
+                    e = JPEG_CONV_PARAM_RANGE_ERR;
+                    jcu_error_flag = true;
+                    goto fin;
+                }
+            }
+            (void)R_JCU_GetEncodedSize(pEncodeSize);
+        } else {
+            pJPEG_ConverterCallback = pOptions->p_EncodeCallBackFunc;
+            jcu_error = R_wrpper_set_encode_callback((mbed_CallbackFunc_t*)JPEG_CallbackFunction, pEncodeSize, size_max_count);
+            if ( jcu_error != JCU_ERROR_OK ) {
+                e = JPEG_CONV_JCU_ERR;
+                goto fin;
+            }
+        }
+        e = JPEG_CONV_OK;
+    } else {
+        e = JPEG_CONV_PARAM_RANGE_ERR;
+    }
+fin:
+    if (mutex_release == true) {
+        jpeg_converter_semaphore.release(); // RELEASE
+    }
+
+    return  e;
+} /* End of method encode() */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/jcu_driver/converter_wrapper.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,198 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         converter_wrapper.c
+* @version      1.00
+* $Rev: 1 $
+* $Date:: 2015-08-06 16:33:52 +0900#$
+* @brief        Graphics driver wrapper function definitions in C
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "converter_wrapper.h"
+#include  "r_ospl.h"
+#include  "r_jcu_api.h"
+#include  "r_jcu_pl.h"
+
+static mbed_CallbackFunc_t*     SetCallback;
+static size_t*                  pEncodeSize;
+static int32_t                  EncodeCount;
+static int32_t                  EncodeCountMax;
+static size_t                   DecodeWidth;
+static size_t                   DecodeHeight;
+static r_ospl_async_t           Async;
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Set callback function address for decode
+ * @param[in]   pSetCallbackAdr  Callback function address
+ * @param[in]   width            Decode data width
+ * @param[in]   height           Decode data height
+ * @retval      error code
+******************************************************************************/
+errnum_t    R_wrpper_set_decode_callback(mbed_CallbackFunc_t* pSetCallbackAdr, size_t width, size_t height)
+{
+    errnum_t    e;
+
+    Async.Flags             = R_F_OSPL_InterruptCallback;
+    Async.A_Thread          = R_OSPL_THREAD_GetCurrentId();
+    Async.InterruptCallback = &R_wrpper_LocalDecodeCallback;
+    SetCallback             = pSetCallbackAdr;
+    DecodeWidth             = width;
+    DecodeHeight            = height;
+
+    e = R_JCU_StartAsync(&Async);
+
+    return e;
+}
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   InterruptSource  Interrput source data struct address
+ * @param[in]   Caller           ospl caller data address
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_LocalDecodeCallback(const r_ospl_interrupt_t *InterruptSource, const r_ospl_caller_t *Caller)
+{
+    errnum_t                  e = 0;
+    const jcu_async_status_t* status;
+    jcu_image_info_t          image_info;
+    jcu_errorcode_t           jcu_error;
+
+    e = R_JCU_OnInterruptDefault(InterruptSource, Caller);
+    if (e != 0) {
+        SetCallback(MBED_JCU_E_JCU_ERR);
+        goto fin;
+    }
+    R_JCU_GetAsyncStatus( &status );
+    if (status -> IsPaused == true) {
+        if ((status->SubStatusFlags & JCU_SUB_INFOMATION_READY) == 0) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_FORMA_ERR);
+            goto fin;
+        }
+        R_JCU_GetImageInfo( &image_info );
+        if ((image_info.width == 0u) || (image_info.height == 0u) || 
+            (image_info.width > DecodeWidth) || 
+            (image_info.height > DecodeHeight)) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_FORMA_ERR);
+            goto fin;
+        }
+        if ((image_info.encodedFormat != JCU_JPEG_YCbCr444) &&
+            (image_info.encodedFormat != JCU_JPEG_YCbCr422) &&
+            (image_info.encodedFormat != JCU_JPEG_YCbCr420) &&
+            (image_info.encodedFormat != JCU_JPEG_YCbCr411)) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_FORMA_ERR);
+            goto fin;
+        }
+        jcu_error = R_JCU_ContinueAsync(JCU_IMAGE_INFO, &Async);
+        if (jcu_error != JCU_ERROR_OK) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_JCU_ERR);
+            goto fin;
+        }
+    } else {
+        SetCallback(MBED_JCU_E_OK);
+    }
+
+fin:
+    return  e;
+
+}
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   pSetCallbackAdr  Callback function address
+ * @param[in]   pSize            Encode size input address
+ * @param[in]   count_max        Encode count max num
+ * @retval      error code
+******************************************************************************/
+errnum_t R_wrpper_set_encode_callback( mbed_CallbackFunc_t* pSetCallbackAdr, size_t* pSize, int32_t count_max)
+{
+    errnum_t e;
+
+    Async.Flags             = R_F_OSPL_InterruptCallback;
+    Async.A_Thread          = R_OSPL_THREAD_GetCurrentId();
+    Async.InterruptCallback = &R_wrpper_LocalEncodeCallback;
+    SetCallback             = pSetCallbackAdr;
+    pEncodeSize             = pSize;
+    *pEncodeSize            = 0;
+    EncodeCount             = 1;
+    EncodeCountMax          = count_max;
+
+    e = R_JCU_StartAsync(&Async);
+
+    return e;
+}
+
+/**************************************************************************//**
+ * @brief       Set callback function address for encode
+ * @param[in]   InterruptSource  Interrput source data struct address
+ * @param[in]   Caller           ospl caller data address
+ * @retval      error code
+******************************************************************************/
+errnum_t    R_wrpper_LocalEncodeCallback(const r_ospl_interrupt_t *InterruptSource, const r_ospl_caller_t *Caller)
+{
+    errnum_t                  e = 0;
+    const jcu_async_status_t* status;
+    jcu_errorcode_t           jcu_error;
+
+    e = R_JCU_OnInterruptDefault(InterruptSource, Caller);
+    if (e != 0) {
+        SetCallback(MBED_JCU_E_JCU_ERR);
+        goto fin;
+    }
+    R_JCU_GetAsyncStatus(&status);
+    if (status -> IsPaused == true) {
+        if ((status->SubStatusFlags & JCU_SUB_ENCODE_OUTPUT_PAUSE) == 0) {
+            e = E_OTHERS;
+            goto fin;
+        }
+        if (EncodeCount > EncodeCountMax) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_JCU_ERR);
+            goto fin;
+        }
+        EncodeCount++;
+        jcu_error = R_JCU_ContinueAsync(JCU_OUTPUT_BUFFER, &Async);
+        if (jcu_error != JCU_ERROR_OK) {
+            e = E_OTHERS;
+            SetCallback(MBED_JCU_E_JCU_ERR);
+            goto fin;
+        }
+    } else {
+        (void)R_JCU_GetEncodedSize(pEncodeSize);
+        SetCallback(MBED_JCU_E_OK);
+    }
+
+fin:
+    return  e;
+
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/jcu_driver/jcu_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1340 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: jcu_api.c $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description : JCU driver API
+******************************************************************************/
+/**
+* @file  jcu_api.c
+* @brief   JCU (JPEG hardware) driver API. Main Code.
+*
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+*/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+#include    "r_ospl.h"
+#include    "r_jcu_api.h"
+#include    "r_jcu_local.h"
+#include    "r_jcu_pl.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/* Section: Internal Global */
+
+/** gs_jcu_internal_information */
+static jcu_internal_information_t  gs_jcu_internal_information;
+
+
+/** gs_jcu_i_lock */
+static jcu_i_lock_t  gs_jcu_i_lock;
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/***********************************************************************
+* Class: jcu_i_lock_t
+************************************************************************/
+static void    R_JCU_I_LOCK_Reset( jcu_i_lock_t *const  self );
+static bool_t  R_JCU_I_LOCK_Lock( void *const  self_ );
+static void    R_JCU_I_LOCK_Unlock( void *const  self_ );
+static void    R_JCU_I_LOCK_RequestFinalize( void *const  self_ );
+static int_fast32_t  R_JCU_I_LOCK_GetRootChannelNum( const void *const  self_ );
+
+
+/* Section: Global */
+/**
+* @brief   Initialize the driver
+*
+* @param   NullConfig (in) NULL
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_Initialize( void *const  NullConfig )
+/* <-SEC M1.1.1 */
+{
+    errnum_t          e;
+    jcu_errorcode_t   returnValue;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    static const r_ospl_i_lock_vtable_t  gs_I_LockVTable = {
+        &( R_JCU_I_LOCK_Lock ),  /* MISRA 16.9 */
+        &( R_JCU_I_LOCK_Unlock ),
+        &( R_JCU_I_LOCK_RequestFinalize ),
+        &( R_JCU_I_LOCK_GetRootChannelNum )
+    };
+
+    R_UNREFERENCED_VARIABLE( NullConfig );
+    R_IT_WILL_BE_NOT_CONST( NullConfig );
+
+    if ( self->I_Lock == NULL ) {
+        jcu_i_lock_t *const  i_lock = &gs_jcu_i_lock;
+
+        self->Is_I_LockMaster = R_JCU_I_LOCK_Replace(
+                                    i_lock,  &gs_I_LockVTable );
+    }
+
+    if ( IS( self->Is_I_LockMaster ) ) {
+        R_JCU_I_LOCK_Reset( self->I_Lock );
+    }
+    R_OSPL_FLAG32_InitConst( &self->AsyncStatus.InterruptFlags );
+    R_OSPL_FLAG32_InitConst( &self->AsyncStatus.InterruptEnables );
+    R_OSPL_FLAG32_InitConst( &self->AsyncStatus.CancelFlags );
+    self->AsyncStatus.IsEnabledInterrupt = false;
+
+    /* Error check */
+    if (self->AsyncStatus.Status != JCU_STATUS_UNDEF) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    /* Run the User-defined function if user set the function */
+    e= R_JCU_OnInitialize();
+    IF ( e != 0 ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+    /* Initialize the variable */
+    self->AsyncStatus.IsPaused = false;
+    self->AsyncStatus.SubStatusFlags = 0;
+    self->IsCountMode = false;
+    self->ErrorFilter = JCU_INT_ERROR_ALL;
+    self->AsyncForFinalize = NULL;
+
+    /* Set the register */
+    returnValue = JCU_SetRegisterForInitialize();
+
+    if (returnValue == JCU_ERROR_OK) {
+        /* Set the updated status */
+        self->AsyncStatus.Status = JCU_STATUS_INIT;
+
+        /* Initialize the status for the encode */
+        self->Codec = JCU_CODEC_NOT_SELECTED;
+    } /* end if */
+
+fin:
+    return returnValue;
+}
+
+
+/**
+* @brief   Terminate the driver function
+*
+* @par Parameters
+*    None
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_Terminate(void)
+/* <-SEC M1.1.1 */
+{
+    errnum_t         e;
+    jcu_errorcode_t  ej;
+    r_ospl_async_t   async;
+    bit_flags32_t    got_flags;
+
+    async.Flags = R_F_OSPL_A_Thread;
+    async.A_Thread = R_OSPL_THREAD_GetCurrentId();
+
+    ej= R_JCU_TerminateAsync( &async );
+    IF( ej != JCU_ERROR_OK ) {
+        goto fin;
+    }
+
+    e= R_OSPL_EVENT_Wait( async.A_EventValue, &got_flags, R_OSPL_INFINITE );
+    IF(e!=0) {
+        ej=JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+    e= async.ReturnValue;
+    IF(e!=0) {
+        ej=JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+fin:
+    return  ej;
+}
+
+
+/**
+* @brief   Terminate the driver function
+*
+* @param   async <r_ospl_async_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_TerminateAsync( r_ospl_async_t *const  async )
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue = JCU_ERROR_OK;
+    bool_t            was_enabled = false;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    IF_DQ( async == NULL ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+    R_JCU_SetDefaultAsync( async, R_OSPL_ASYNC_TYPE_FINALIZE );
+    async->ReturnValue = 0;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+    /* Check the status */
+    if ( self->AsyncStatus.Status == JCU_STATUS_UNDEF ) {
+        returnValue = JCU_ERROR_OK;
+        goto fin;
+    } /* end if */
+
+    if ( self->AsyncStatus.Status == JCU_STATUS_RUN ) {
+        self->AsyncForFinalize = async;
+
+        R_OSPL_FLAG32_Set( &self->AsyncStatus.CancelFlags, R_OSPL_FINALIZE_REQUEST );
+
+        /* "R_JCU_OnInterrupted" will be called */
+    } else {
+        returnValue = R_JCU_TerminateStep2();
+        R_OSPL_EVENT_Set( async->A_Thread, async->A_EventValue );
+    } /* end if */
+
+fin:
+    /* Finalize I-Lock */
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+
+        if ( IS( self->Is_I_LockMaster ) ) {
+            if ( IS( gs_jcu_i_lock.IsRequestedFinalize ) ) {
+                R_JCU_I_LOCK_Finalize();
+            }
+        }
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Terminate the driver function
+*
+* @par Parameters
+*    None
+* @return  <jcu_errorcode_t> type.
+*/
+jcu_errorcode_t  R_JCU_TerminateStep2(void)
+{
+    errnum_t         ee;
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    R_AVOID_UNSAFE_ALWAYS_WARNING( returnValue );
+
+
+    /* Set the updated status */
+    R_OSPL_FLAG32_Clear( &self->AsyncStatus.CancelFlags, R_OSPL_FLAG32_ALL_BITS );
+    self->AsyncStatus.Status = JCU_STATUS_UNDEF;
+    self->I_LockVTable->RequestFinalize( self->I_Lock );
+
+
+    /* Run the additional function selected by parameter */
+    ee= R_JCU_OnFinalize( returnValue );
+    IF ( (ee != 0) && (returnValue == JCU_ERROR_OK) ) {
+        returnValue = JCU_ERROR_PARAM;
+    }
+
+    return  returnValue;
+}
+
+
+/**
+* @brief   Select Codec Type
+*
+* @param   codec <jcu_codec_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SelectCodec(
+    const jcu_codec_t codec)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled;  /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF ((self->AsyncStatus.Status == JCU_STATUS_UNDEF)
+        || (self->AsyncStatus.Status == JCU_STATUS_RUN)) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckSelectCodec(codec);
+    IF (returnValue != JCU_ERROR_OK) {
+        goto fin;
+    }
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Clear the count mode flag */
+    self->IsCountMode = false;
+
+    /* Register set */
+    JCU_SetRegisterForCodec(codec);
+
+    /* Set the updated status */
+    self->AsyncStatus.Status = JCU_STATUS_SELECTED;
+
+    /* Set codec type to internal information variable */
+    switch (codec) {
+        case JCU_ENCODE:
+            self->Codec = JCU_STATUS_ENCODE;
+            break;
+        case JCU_DECODE:
+            self->Codec = JCU_STATUS_DECODE;
+            break;
+            /* ->QAC 2018 : For MISRA 15.3, SEC R3.5.2 */
+        default:
+            /* <-QAC 2018 */
+            R_NOOP();  /* NOT REACHED */
+            break;
+    } /* end switch */
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Start decoding or encoding. Synchronized.
+*
+* @par Parameters
+*    None
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_Start(
+    void)
+/* <-SEC M1.1.1 */
+{
+    errnum_t         e;
+    jcu_errorcode_t  ej;
+    r_ospl_async_t   async;
+    bit_flags32_t    got_flags;
+
+    async.Flags = R_F_OSPL_A_Thread;
+    async.A_Thread = R_OSPL_THREAD_GetCurrentId();
+
+    ej= R_JCU_StartAsync( &async );
+    IF( ej != JCU_ERROR_OK ) {
+        goto fin;
+    }
+
+    e= R_OSPL_EVENT_Wait( async.A_EventValue, &got_flags, R_OSPL_INFINITE );
+    IF(e!=0) {
+        ej=e;
+        goto fin;
+    }
+
+    e= async.ReturnValue;
+    IF(e!=0) {
+        ej=e;
+        goto fin;
+    }
+
+fin:
+    return  ej;
+}
+
+
+/**
+* @brief   Start decoding or encoding. Asynchronized.
+*
+* @par Parameters
+*    None
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_StartAsync(
+    r_ospl_async_t *const  async)
+/* <-SEC M1.1.1 */
+{
+    errnum_t          e;
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (self->AsyncStatus.Status != JCU_STATUS_READY) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckStart();
+    IF(returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+
+    IF ( async == NULL ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    R_JCU_SetDefaultAsync( async, R_OSPL_ASYNC_TYPE_NORMAL );
+    async->ReturnValue = 0;
+
+    /* Attach "Async" to interrupt */
+    /* ->MISRA 11.4 : Not too big "enum" is same bit count as "int" */ /* ->SEC R2.7.1 */
+    R_OSPL_CALLER_Initialize( &self->InterruptCallbackCaller,
+                              async, (int_fast32_t *)&self->AsyncStatus.Status, JCU_STATUS_INTERRUPTING,
+                              self->I_Lock, self->I_LockVTable );
+    /* <-MISRA 11.4 */ /* <-SEC R2.7.1 */
+    e= R_JCU_SetInterruptCallbackCaller( &self->InterruptCallbackCaller );
+    IF ( e != 0 ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }
+    R_OSPL_FLAG32_Set( &self->AsyncStatus.InterruptEnables, JCU_INTERRUPT_LINE_ALL );
+
+    /* Clear event flags */
+    R_OSPL_EVENT_Clear( async->A_Thread, async->A_EventValue );
+    R_OSPL_EVENT_Clear( async->I_Thread, async->I_EventValue );
+
+    /* Set the updated status when register update is finished */
+    /* Change the status */
+    self->AsyncStatus.Status = JCU_STATUS_RUN;
+
+    /* Register set */
+    JCU_SetRegisterForStart( self->ErrorFilter );
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Set the count mode (separate operating) parameter
+*
+* @param   buffer <jcu_count_mode_param_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SetCountMode(
+    const jcu_count_mode_param_t  *const buffer)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_SELECTED)
+          || (self->AsyncStatus.Status == JCU_STATUS_READY))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF(buffer == NULL) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckSetCountMode(buffer);
+    IF(returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Set the count mode flag */
+    if ((buffer->inputBuffer.isEnable != false) || (buffer->outputBuffer.isEnable != false)) {
+        self->IsCountMode = true;
+    } else {
+        self->IsCountMode = false;
+    } /* end if */
+
+    /* Register set */
+    JCU_SetRegisterForSetCountMode(buffer);
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Restart the processing caused by count mode. Synchronized.
+*
+* @param   type The target to continue
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_Continue(
+    const jcu_continue_type_t  type)
+/* <-SEC M1.1.1 */
+{
+    errnum_t         e;
+    jcu_errorcode_t  ej;
+    r_ospl_async_t   async;
+    bit_flags32_t    got_flags;
+
+    async.Flags = R_F_OSPL_A_Thread;
+    async.A_Thread = R_OSPL_THREAD_GetCurrentId();
+
+    ej= R_JCU_ContinueAsync( type, &async );
+    IF( ej != JCU_ERROR_OK ) {
+        goto fin;
+    }
+
+    e= R_OSPL_EVENT_Wait( async.A_EventValue, &got_flags, R_OSPL_INFINITE );
+    IF(e!=0) {
+        ej=JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+    e= async.ReturnValue;
+    IF(e!=0) {
+        ej=JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+fin:
+    return  ej;
+}
+
+
+/**
+* @brief   Restart the processing caused by count mode. Asynchronized.
+*
+* @param   type The target to continue
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_ContinueAsync(
+    const jcu_continue_type_t  type,
+    r_ospl_async_t *const  async)
+/* <-SEC M1.1.1 */
+{
+    errnum_t          e;
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    bit_flags32_t     mask;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (self->AsyncStatus.Status != JCU_STATUS_READY) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (self->AsyncStatus.IsPaused == false) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    IF ( async == NULL ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Clear the sub status flag */
+    switch ( type ) {
+        case JCU_INPUT_BUFFER:
+            mask = ( ( JINF_MASK | DINLF_MASK ) << JCU_SHIFT_JINTS1 );
+            break;
+        case JCU_OUTPUT_BUFFER:
+            mask = ( ( DOUTLF_MASK | JOUTF_MASK ) << JCU_SHIFT_JINTS1 );
+            break;
+        default:
+            ASSERT_R( type == JCU_IMAGE_INFO, returnValue=E_OTHERS; goto fin );
+            mask = INS3_MASK;
+            break;
+    }
+    ASSERT_R( IS_ANY_BITS_SET( self->AsyncStatus.SubStatusFlags, mask ), returnValue=E_OTHERS; goto fin );
+    self->AsyncStatus.SubStatusFlags &= ~mask;
+
+
+    R_JCU_SetDefaultAsync( async, R_OSPL_ASYNC_TYPE_NORMAL );
+    async->ReturnValue = 0;
+
+    /* Clear event flags */
+    R_OSPL_EVENT_Clear( async->A_Thread, async->A_EventValue );
+    R_OSPL_EVENT_Clear( async->I_Thread, async->I_EventValue );
+
+    /* JCU will restart */
+    if( self->AsyncStatus.SubStatusFlags == 0 ) {
+        /* Attach "Async" to interrupt */
+        /* ->MISRA 11.4 : Not too big "enum" is same bit count as "int" */ /* ->SEC R2.7.1 */
+        R_OSPL_CALLER_Initialize( &self->InterruptCallbackCaller,
+                                  async, (int_fast32_t *)&self->AsyncStatus.Status, JCU_STATUS_INTERRUPTING,
+                                  self->I_Lock, self->I_LockVTable );
+        /* <-MISRA 11.4 */ /* <-SEC R2.7.1 */
+        e= R_JCU_SetInterruptCallbackCaller( &self->InterruptCallbackCaller );
+        IF ( e != 0 ) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        }
+        R_OSPL_FLAG32_Set( &self->AsyncStatus.InterruptEnables, JCU_INTERRUPT_LINE_ALL );
+
+        /* Change the status */
+        self->AsyncStatus.Status = JCU_STATUS_RUN;
+        self->AsyncStatus.IsPaused = false;
+
+        /* Register set */
+        JCU_SetRegisterForContinue( type );
+    }
+
+    /* JCU will not restart */
+    else {
+        /* Register set */
+        JCU_SetRegisterForContinue( type );
+
+        /* Change the status */
+        self->AsyncStatus.Status = JCU_STATUS_READY;
+
+        /* Set event flags */
+        R_OSPL_EVENT_Set( async->A_Thread, async->A_EventValue );
+        R_OSPL_EVENT_Set( async->I_Thread, async->I_EventValue );
+    }
+
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   R_JCU_GetAsyncStatus.
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void  R_JCU_GetAsyncStatus( const jcu_async_status_t **const  out_Status )
+{
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    IF_DQ( out_Status == NULL ) {
+        goto fin;
+    }
+
+    *out_Status = &self->AsyncStatus;
+
+fin:
+    return;
+}
+
+
+/**
+* @brief   Set parameter for decode.
+*
+* @param   decode Select the encode parameter for decoding. <jcu_decode_param_t>
+* @param   buffer Buffer settings for decode. <jcu_buffer_param_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SetDecodeParam(
+    const jcu_decode_param_t   *const decode,
+    const jcu_buffer_param_t   *const buffer)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF(self->Codec != JCU_STATUS_DECODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF((decode == NULL) || (buffer == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckSetDecodeParam(decode, buffer);
+    IF(returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_SetRegisterForSetDecodePrm(decode, buffer);
+
+    /* Set the updated status */
+    self->AsyncStatus.Status = JCU_STATUS_READY;
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Whether stop or not stop for R_JCU_GetImageInfo()
+*
+* @param   is_pause Whether stop or not stop
+* @return  <jcu_errorcode_t> type.
+*/
+jcu_errorcode_t R_JCU_SetPauseForImageInfo( const bool_t is_pause )
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF(self->Codec != JCU_STATUS_DECODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_SetRegisterForSetPause( is_pause, self->ErrorFilter );
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   GetImageInfo
+*
+* @param   buffer Image information. <jcu_image_info_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_GetImageInfo(
+    jcu_image_info_t   *const buffer)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (self->AsyncStatus.Status != JCU_STATUS_READY) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (self->Codec != JCU_STATUS_DECODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (buffer == NULL) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckGetImageInfo(buffer);
+    if(returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_GetRegisterForGetImageInfo(buffer);
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   SetErrorFilter
+*
+* @param   filter enable bit of error. <jcu_int_detail_errors_t>
+* @return  <jcu_errorcode_t> type.
+*/
+jcu_errorcode_t R_JCU_SetErrorFilter(jcu_int_detail_errors_t filter)
+{
+    jcu_errorcode_t   returnValue;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_INIT)
+          || (self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    IF ( IS_ANY_BITS_SET( filter, ~JCU_INT_ERROR_ALL ) ) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    self->ErrorFilter = filter;
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    return returnValue;
+}
+
+
+/**
+* @brief   SetQuantizationTable
+*
+* @param   tableNo The table number to set the value. <jcu_table_no_t>
+* @param   table The body of the table to set.
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SetQuantizationTable(
+    const jcu_table_no_t   tableNo,
+    const uint8_t         *const table)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (self->Codec != JCU_STATUS_ENCODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (table == NULL) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckSetQuantizationTbl(tableNo);
+    IF (returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_SetRegisterForSetQtTable(tableNo, table);
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Set the Huffman table
+*
+* @param   tableNo The table number to set the value. <jcu_table_no_t>
+* @param   type The type of Huffman table type (AC or DC). <jcu_huff_t>
+* @param   table The body of the table to set
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SetHuffmanTable(
+    const jcu_table_no_t   tableNo,
+    const jcu_huff_t       type,
+    const uint8_t         *const table)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (self->Codec != JCU_STATUS_ENCODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (table == NULL) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckSetHuffmanTable(tableNo, type);
+    IF (returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_SetRegisterForSetHuffTbl(tableNo, type, table);
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   Set the parameter fo encoding
+*
+* @param   encode Select the encode parameter for encoding. <jcu_encode_param_t>
+* @param   buffer Select the buffer settings for encoding. <jcu_buffer_param_t>
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_SetEncodeParam(
+    const jcu_encode_param_t   *const encode,
+    const jcu_buffer_param_t   *const buffer)
+/* <-SEC M1.1.1 */
+{
+    jcu_errorcode_t   returnValue;
+    bool_t            was_enabled; /* = false; */ /* QAC 3197 */
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF (self->Codec != JCU_STATUS_ENCODE) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+
+    IF ((encode == NULL) || (buffer == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    returnValue = JCU_ParaCheckEncodeParam(encode, buffer);
+    IF (returnValue != JCU_ERROR_OK) {
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+    /* Register set */
+    JCU_SetRegisterForSetEncodePrm(encode, buffer);
+
+    /* Set the updated status */
+    self->AsyncStatus.Status = JCU_STATUS_READY;
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( IS( was_enabled ) ) {
+        self->I_LockVTable->Unlock( self->I_Lock );
+    }
+    return returnValue;
+}
+
+
+/**
+* @brief   GetEncodedSize
+*
+* @param   out_Size EncodedSize
+* @return  <jcu_errorcode_t> type.
+*/
+/* ->SEC M1.1.1 API Function */
+jcu_errorcode_t R_JCU_GetEncodedSize(
+    size_t *const out_Size)
+/* <-SEC M1.1.1 */
+{
+    JCU_GetEncodedSize(out_Size);
+    return  JCU_ERROR_OK;
+}
+
+
+/**
+* @brief   Set AXI bus A*CACHE bits for 2nd cache to JCU.
+*
+* @param   read_cache_attribute <r_ospl_axi_cache_attribute_t>
+* @param   write_cache_attribute <r_ospl_axi_cache_attribute_t>
+* @return  <jcu_errorcode_t> type.
+*/
+jcu_errorcode_t  R_JCU_Set2ndCacheAttribute(
+    r_ospl_axi_cache_attribute_t const  read_cache_attribute,
+    r_ospl_axi_cache_attribute_t const  write_cache_attribute )
+{
+    static const uint32_t  mask_JCU = 0xFFFF0000u;
+    jcu_errorcode_t    returnValue;
+    bool_t             was_all_enabled = false;
+    uint32_t           new_value;
+    volatile uint32_t  value;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+#ifdef JCU_PARAMETER_CHECK
+    IF (!((self->AsyncStatus.Status == JCU_STATUS_READY)
+          || (self->AsyncStatus.Status == JCU_STATUS_SELECTED))) {
+        returnValue = JCU_ERROR_STATUS;
+        goto fin;
+    } /* end if */
+#endif  /* #Ifdef JCU_PARAMETER_CHECK_ */
+
+
+    new_value = ( read_cache_attribute << 24 ) | ( write_cache_attribute << 16 );
+
+    was_all_enabled = R_OSPL_DisableAllInterrupt();
+
+    value = INB.AXIBUSCTL0;
+    value = new_value | ( value & ~mask_JCU );  /* Mutual Exclusion from Ether */
+    INB.AXIBUSCTL0 = value;
+
+    returnValue = JCU_ERROR_OK;
+fin:
+    if ( was_all_enabled ) {
+        R_OSPL_EnableAllInterrupt();
+    }
+
+    return  returnValue;
+}
+
+
+/**
+* @brief   EnableInterrupt
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void  R_JCU_EnableInterrupt(void)
+{
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    self->AsyncStatus.IsEnabledInterrupt = true;
+    R_JCU_OnEnableInterrupt( self->AsyncStatus.InterruptEnables.Flags );
+}
+
+
+/**
+* @brief   DisableInterrupt
+*
+* @par Parameters
+*    None
+* @return  Was interrupt enabled
+*/
+bool_t  R_JCU_DisableInterrupt(void)
+{
+    bool_t    was_interrupted;
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+
+    was_interrupted = self->AsyncStatus.IsEnabledInterrupt;
+
+    R_JCU_OnDisableInterrupt( self->AsyncStatus.InterruptEnables.Flags );
+    self->AsyncStatus.IsEnabledInterrupt = false;
+
+    return  was_interrupted;
+}
+
+
+/**
+* @brief   R_JCU_GetInternalInformation
+*
+* @par Parameters
+*    None
+* @return  <jcu_internal_information_t> type.
+*/
+jcu_internal_information_t  *R_JCU_GetInternalInformation(void)
+{
+    return  &gs_jcu_internal_information;
+}
+
+
+/**
+* @brief   R_JCU_GetILockObject
+*
+* @par Parameters
+*    None
+* @return  <jcu_i_lock_t> type.
+*/
+jcu_i_lock_t  *R_JCU_GetILockObject(void)
+{
+    return  &gs_jcu_i_lock;
+}
+
+
+/**
+* @brief   Replace associated I-Lock object
+*
+* @param   I_Lock I-Lock object
+* @param   I_LockVTable V-Table
+* @return  Whether success to replace
+*/
+bool_t  R_JCU_I_LOCK_Replace( void *const  I_Lock,  const r_ospl_i_lock_vtable_t *const  I_LockVTable )
+{
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+    bool_t  ret = false;
+
+    ASSERT_R( self->AsyncStatus.Status == JCU_STATUS_UNDEF,  ret = false; goto fin );
+
+    if ( I_Lock != NULL ) {
+        if ( self->I_Lock == NULL ) {
+            self->I_Lock = I_Lock;
+            self->I_LockVTable = I_LockVTable;
+            ret = true;
+        }
+    } else {
+        self->I_Lock = NULL;
+    }
+
+fin:
+    return  ret;
+}
+
+
+/**
+* @brief   Finalize the I-Lock object
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void  R_JCU_I_LOCK_Finalize(void)
+{
+    jcu_internal_information_t *const  self = &gs_jcu_internal_information;
+    bool_t  b;
+
+    ASSERT_D( self->Is_I_LockMaster, R_NOOP() );
+
+    R_JCU_I_LOCK_Reset( self->I_Lock );
+    b= R_JCU_I_LOCK_Replace( NULL, NULL );
+    R_UNREFERENCED_VARIABLE( b );  /* QAC 3200 : This is not error information */
+    self->Is_I_LockMaster = false;
+}
+
+
+/**
+* @brief   Reset the I-Lock object
+*
+* @param   self I-Lock object
+* @return  None
+*/
+static void   R_JCU_I_LOCK_Reset( jcu_i_lock_t *const  self )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->IsLock = false;
+    R_JCU_OnDisableInterrupt( JCU_INTERRUPT_LINE_ALL );
+    JCU_ClearInterruptFlag();
+    self->IsRequestedFinalize = false;
+
+fin:
+    return;
+}
+
+
+/**
+* @brief   Lock the I-Lock object
+*
+* @param   self_ I-Lock object
+* @return  Was interrupt enabled
+*/
+static bool_t  R_JCU_I_LOCK_Lock( void *const  self_ )
+{
+    bool_t  is_locked;
+    bool_t  was_all_enabled; /* = false; */ /* QAC 3197 */
+    bool_t  b;
+    jcu_i_lock_t *const  self = (jcu_i_lock_t *) self_;
+
+    IF_DQ( self == NULL ) {
+        is_locked = true;
+        goto fin;
+    }
+
+    was_all_enabled = R_OSPL_DisableAllInterrupt();
+
+    is_locked = self->IsLock;
+    if ( ! is_locked ) {
+        b= R_JCU_DisableInterrupt();
+        R_UNREFERENCED_VARIABLE( b );  /* QAC 3200 : This is not error information */
+        self->IsLock = true;
+    }
+
+    if ( IS( was_all_enabled ) ) {
+        R_OSPL_EnableAllInterrupt();
+    }
+
+fin:
+    return  ! is_locked;
+}
+
+
+/**
+* @brief   Unlock the I-Lock object
+*
+* @param   self_ I-Lock object
+* @return  None
+*/
+static void  R_JCU_I_LOCK_Unlock( void *const  self_ )
+{
+    bool_t  was_all_enabled; /* = false; */ /* QAC 3197 */
+    jcu_i_lock_t *const  self = (jcu_i_lock_t *) self_;
+
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    was_all_enabled = R_OSPL_DisableAllInterrupt();
+
+    R_JCU_EnableInterrupt();
+    self->IsLock = false;
+
+    if ( IS( was_all_enabled ) ) {
+        R_OSPL_EnableAllInterrupt();
+    }
+
+fin:
+    return;
+}
+
+
+/**
+* @brief   Request to finalize the I-Lock object
+*
+* @param   self_ I-Lock object
+* @return  None
+*/
+static void   R_JCU_I_LOCK_RequestFinalize( void *const  self_ )
+{
+    jcu_i_lock_t *const  self = (jcu_i_lock_t *) self_;
+
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->IsRequestedFinalize = true;
+
+fin:
+    return;
+}
+
+
+/**
+* @brief   Get root channel number of I-Lock object
+*
+* @param   self_ I-Lock object
+* @return  A channel number
+*/
+static int_fast32_t  R_JCU_I_LOCK_GetRootChannelNum( const void *const  self_ )
+{
+    R_UNREFERENCED_VARIABLE( self_ );
+
+    return  0;
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/jcu_driver/jcu_para.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,357 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: jcu_para.c $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-03-18 16:14:45 +0900#$
+* Description : JCU driver checking parameter
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+#include    "r_typedefs.h"
+#include    "r_ospl.h"
+#include    "r_jcu_api.h"
+#include    "r_jcu_local.h"
+#include    "r_jcu_user.h"
+#include    "iodefine.h"
+
+#ifdef      JCU_PARAMETER_CHECK
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define MASK_LOW_3BIT   (0x7u)
+#define MOD_8           (0x8u)
+#define MOD_16          (0x10u)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckSelectCodec]
+ * @brief       SelectCodec api's parameter checking
+ * @param       [in] codec  codec type
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckSelectCodec(
+    const jcu_codec_t   codec)
+{
+    jcu_errorcode_t  returnValue;
+
+    IF_DS ((codec != JCU_ENCODE)
+           && (codec != JCU_DECODE)) {
+        returnValue = JCU_ERROR_PARAM;
+    }
+    else {
+        returnValue = JCU_ERROR_OK;
+    } /* end if */
+
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckStart]
+ * @brief       Start api's parameter checking
+ * @param       [in] codec  codec type
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckStart(
+    void)
+{
+    jcu_errorcode_t   returnValue;
+
+    /* If jcu already start, it cannot update this bit (this is limitation of hardware) */
+    IF ( (uint32_t)R_GET_REG_BIT_FIELD( JCU.JCCMD, JSRT ) == REG_F_SET ) {
+        returnValue = JCU_ERROR_STATUS;
+    }
+    else {
+        returnValue = JCU_ERROR_OK;
+    } /* end if */
+
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckSetCountMode]
+ * @brief       parameter check for the SetCountMode
+ * @param       [in] buffer the parameter for the Count Mode
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckSetCountMode(
+    const jcu_count_mode_param_t  *const buffer)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    IF (buffer == NULL) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    IF ((buffer->inputBuffer.isEnable != false) && (buffer->outputBuffer.isEnable != false)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }
+
+    if (buffer->inputBuffer.isEnable != false) {
+        /* When initAddress is true, restartAddress has to set the address */
+        if (buffer->inputBuffer.isInitAddress != false) {
+            IF (buffer->inputBuffer.restartAddress == NULL) {
+                returnValue = JCU_ERROR_PARAM;
+                goto fin;
+            } /* end if */
+        } /* end if */
+
+        /* Datasize(JDATAS/LINES bit) have to 8byte alignment */
+        IF ((buffer->inputBuffer.dataCount & MASK_LOW_3BIT) != 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+
+        /* Datasize have to bigger than 0 */
+        IF (buffer->inputBuffer.dataCount == 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+
+    } /* end if */
+
+    if (buffer->outputBuffer.isEnable != false) {
+        /* When initAddress is true, restartAddress has to set the address */
+        if (buffer->outputBuffer.isInitAddress != false) {
+            IF (buffer->outputBuffer.restartAddress == NULL) {
+                returnValue = JCU_ERROR_PARAM;
+                goto fin;
+            } /* end if */
+        } /* end if */
+
+        /* Datasize(JDATAS/LINES bit) have to 8byte alignment */
+        IF ((buffer->outputBuffer.dataCount & MASK_LOW_3BIT) != 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+
+        /* Datasize have to bigger than 0 */
+        IF (buffer->outputBuffer.dataCount == 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+
+    } /* end if */
+fin:
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckSetDecodeParam]
+ * @brief       SetDecodeParam api's parameter checking
+ * @param       [in] buffer         input and output buffer settings
+ * @param       [in] interruptKind  tye type of interrupt that use in this system
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckSetDecodeParam(
+    const jcu_decode_param_t   *const decode,
+    const jcu_buffer_param_t   *const buffer)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    IF ((decode == NULL) || (buffer == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    /* NULL check for the address data */
+    IF ((buffer->source.address == NULL)
+        || (buffer->destination.address == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }  /* end if */
+
+    /* Check for the address alignment */
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    IF ((((uint32_t) (buffer->source.address) % MOD_8) != 0u) ||
+        (((uint32_t) (buffer->destination.address) % MOD_8) != 0u))
+    /* <-MISRA 11.3 */ { /* <-SEC R2.7.1 */
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }  /* end if */
+
+    /*Check for Cb/Cr offset */
+    if(decode->decodeFormat == JCU_OUTPUT_YCbCr422) {
+        IF (((decode->outputCbCrOffset) != JCU_CBCR_OFFSET_0) && ((decode->outputCbCrOffset) != JCU_CBCR_OFFSET_128)) {
+            returnValue = JCU_ERROR_PARAM;
+        }  /* end if */
+    } else {
+        IF ((decode->outputCbCrOffset) != JCU_CBCR_OFFSET_0) {
+            returnValue = JCU_ERROR_PARAM;
+        }  /* end if */
+    } /* end if */
+fin:
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckGetImageInfo]
+ * @brief       GetImageInfo api's parameter checking
+ * @param       [in] buffer         buffer address that set the image information
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckGetImageInfo(
+    const jcu_image_info_t   *const buffer)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    IF (buffer == NULL) {
+        returnValue = JCU_ERROR_PARAM;
+    } /* end if */
+
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckSetQuantizationTbl]
+ * @brief       SetQuantizationTable api's parameter checking
+ * @param       [in] tableNo        the table number that set the parameter
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckSetQuantizationTbl(
+    const jcu_table_no_t   tableNo)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    /* ->MISRA 13.7 : For fail safe. */
+    IF_DS (tableNo > JCU_TABLE_NO_3)
+    /* <-MISRA 13.7 */
+    /* ->MISRA 14.1 ->QAC 3201 : For fail safe. */
+    {
+        returnValue = JCU_ERROR_PARAM;
+    } /* end if */
+    /* <-MISRA 14.1 <-QAC 3201 */
+
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckSetHuffmanTable]
+ * @brief       SetHuffmanTable api's parameter checking
+ * @param       [in] tableNo        the table number that set the parameter
+ * @param       [in] type        the type which table is set(AC or DC)
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckSetHuffmanTable(
+    const jcu_table_no_t   tableNo,
+    const jcu_huff_t       type)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    /* ->MISRA 13.7 : For fail safe. */
+    IF (tableNo > JCU_TABLE_NO_1)
+    /* <-MISRA 13.7 */
+    {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    /* ->MISRA 13.7 : For fail safe. */
+    IF_DS ((type != JCU_HUFFMAN_AC)
+           && (type != JCU_HUFFMAN_DC))
+    /* <-MISRA 13.7 */
+    /* ->MISRA 14.1 ->QAC 3201 : For fail safe. */
+    {
+        returnValue = JCU_ERROR_PARAM;
+    } /* end if */
+    /* <-MISRA 14.1 <-QAC 3201 */
+fin:
+    return (returnValue);
+}
+
+/**************************************************************************//**
+ * Function Name : [JCU_ParaCheckEncodeParam]
+ * @brief        api's parameter checking
+ * @param       [in]
+ * @retval      jcu_errorcode_t
+ *****************************************************************************/
+jcu_errorcode_t JCU_ParaCheckEncodeParam(
+    const jcu_encode_param_t   *const encode,
+    const jcu_buffer_param_t   *const buffer)
+{
+    jcu_errorcode_t  returnValue = JCU_ERROR_OK;
+
+    IF ((encode == NULL) || (buffer == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    } /* end if */
+
+    /* NULL check for the address data */
+    IF ((buffer->source.address == NULL)
+        || (buffer->destination.address == NULL)) {
+        returnValue = JCU_ERROR_PARAM;
+        goto fin;
+    }  /* end if */
+
+
+    if (encode->encodeFormat == JCU_JPEG_YCbCr422) {
+        /* Check the width of the image data */
+        IF ((encode->width % MOD_16) != 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+
+        /* Check the height of the image data */
+        IF ((encode->height % MOD_8) != 0u) {
+            returnValue = JCU_ERROR_PARAM;
+            goto fin;
+        } /* end if */
+    } else {
+        returnValue = JCU_ERROR_PARAM;
+        ASSERT_D( false, R_NOOP() );
+        goto fin;
+    } /* end if */
+
+    /*Check for Cb/Cr offset */
+    IF (((encode->inputCbCrOffset) != JCU_CBCR_OFFSET_0) && ((encode->inputCbCrOffset) != JCU_CBCR_OFFSET_128)) {
+        returnValue = JCU_ERROR_PARAM;
+    }  /* end if */
+
+fin:
+    return (returnValue);
+}
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/jcu_driver/jcu_reg.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,805 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: jcu_reg.c $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description : JCU driver setting register
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <r_typedefs.h>
+#include    <iodefine.h>
+#include    <r_jcu_api.h>
+#include    <r_jcu_local.h>
+#include    <r_jcu_user.h>
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define NUMBER_OF_QUANTIZATION_TABLE_DATA   (64)
+#define NUMBER_OF_HUFFMAN_TABLE_DATA_DC     (28)
+#define NUMBER_OF_HUFFMAN_TABLE_DATA_AC     (178)
+
+#define CBCR_OFFSET_NUM     (2u)
+
+#define SWAP_NORMAL         (0u)
+#define SWAP_16BIT_OUTPUT   (1u)
+#define SWAP_32BIT_OUTPUT   (2u)
+
+#define KIND_COLOR_FORMAT   (3u)
+#define KIND_LINEOFFSET     (2u)
+#define KIND_TABLE          (4u)
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+STATIC_INLINE uint8_t  GET_UPPER_BYTE( uint32_t const  value );
+STATIC_INLINE uint8_t  GET_LOWER_BYTE( uint32_t const  value );
+static void JCU_GetRegisterForGetErrorInfo(jcu_detail_error_t *const errorCode);
+
+
+/**************************************************************************//**
+* Function Name: [GET_UPPER_BYTE]
+* @brief         GET_UPPER_BYTE
+* @retval        Byte
+******************************************************************************/
+STATIC_INLINE uint8_t  GET_UPPER_BYTE( uint32_t const  value )
+{
+    enum { num_8 = 8 }; /* SEC M1.10.1, QAC-3132 */
+    return  (uint8_t)( value >> num_8 );
+}
+
+/**************************************************************************//**
+* Function Name: [GET_LOWER_BYTE]
+* @brief         GET_LOWER_BYTE
+* @retval        Byte
+******************************************************************************/
+STATIC_INLINE uint8_t  GET_LOWER_BYTE( uint32_t const  value )
+{
+    return  (uint8_t)( value );
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForInitialize]
+* @brief         SetRegisterForInitialize
+* @retval        jcu_errorcode_t
+******************************************************************************/
+jcu_errorcode_t JCU_SetRegisterForInitialize(
+    void)
+{
+    return JCU_ERROR_OK;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForCodec]
+* @brief         SetRegisterForCodec
+* @param[out]    codec
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForCodec(
+    const jcu_codec_t codec)
+{
+    volatile uint8_t DummyRead;
+
+    /* Reset this IP */
+    R_SET_REG_BIT_FIELD( CPG.SWRSTCR2, SRST, REG_F_SET );
+    DummyRead = R_GET_REG_BIT_FIELD( CPG.SWRSTCR2, SRST );
+    R_UNREFERENCED_VARIABLE( DummyRead );
+
+    R_SET_REG_BIT_FIELD( CPG.SWRSTCR2, SRST, REG_F_CLR );
+    DummyRead = R_GET_REG_BIT_FIELD( CPG.SWRSTCR2, SRST );
+    R_UNREFERENCED_VARIABLE( DummyRead );
+
+    R_SET_REG_BIT_FIELD( JCU.JCCMD, BRST, REG_F_SET);
+
+    /* Enable interrupts in registers (Interrupt lines in INTC are still disabled) */
+    /* This registers are set to 0 by reset this IP */
+    /* ->QAC 0306 */
+
+    JCU.JINTE1 = JCU_JINTS1_ALL;
+    /* <-QAC 0306 */
+
+    /* Clear the all of count mode settings */
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINLC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFESLC = LINES_CLEAR;
+    /* <-QAC 0306 */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFEDDC = JDATAS_CLEAR;
+    /* <-QAC 0306 */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFDSDC = JDATAS_CLEAR;
+    /* <-QAC 0306 */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTLC, REG_F_CLR );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTRINI, REG_F_CLR );
+    /* ->QAC 0306 */
+    JCU.JIFDDLC = LINES_CLEAR;
+    /* <-QAC 0306 */
+
+    /* Set the which process is select */
+    R_SET_REG_BIT_FIELD( JCU.JCMOD, DSP, codec );
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_ClearInterruptFlag]
+* @brief         ClearInterruptFlag
+* @retval        None
+******************************************************************************/
+void JCU_ClearInterruptFlag(
+    void)
+{
+    /* Interrupt request clear */
+    R_SET_REG_BIT_FIELD( JCU.JCCMD, JEND, REG_F_SET);
+
+    /* Clear the JEDI interrupt source flag */
+    /* ->QAC 0306 */
+    JCU.JINTS0 = (uint8_t) 0u;  /* Write 0 only */
+    /* <-QAC 0306 */
+
+    /* Clear the JDTI interrupt source flag */
+    /* ->QAC 0306 */
+    JCU.JINTS1 &= ~JCU_JINTS1_ALL;
+    /* <-QAC 0306 */
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForStart]
+* @brief         SetRegisterForStart
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForStart(
+    const jcu_int_detail_error_t error_filter)
+{
+    uint32_t reg_jinte0;
+    reg_jinte0 = (uint32_t)JCU.JINTE0 & (uint32_t)(~JCU_INT_ERROR_ALL);
+    JCU.JINTE0 = (uint8_t)( reg_jinte0 | (uint32_t)error_filter );
+    R_SET_REG_BIT_FIELD( JCU.JCCMD, JSRT, REG_F_SET );
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetCountMode]
+* @brief         SetRegisterForSetCountMode
+* @param[in]     buffer
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetCountMode(
+    const jcu_count_mode_param_t    *const buffer)
+{
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    IF (buffer == NULL) {
+        goto fin;
+    } /* end if */
+
+    IF_DQ ( self == NULL ) {
+        goto fin;
+    } /* end if */
+
+    switch(self->Codec) {
+        case JCU_STATUS_ENCODE:
+            /* ->QAC 0306 */
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINRINI, buffer->inputBuffer.isInitAddress );
+            if ((buffer->inputBuffer.isEnable != false) && (buffer->inputBuffer.isInitAddress != false)) {
+                JCU.JIFESA = (uint32_t)(buffer->inputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFESLC = ( LINES_MASK & (buffer->inputBuffer.dataCount) );
+
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTRINI ,buffer->outputBuffer.isInitAddress );
+            if ((buffer->outputBuffer.isEnable != false) && (buffer->outputBuffer.isInitAddress != false)) {
+                JCU.JIFEDA = (uint32_t)(buffer->outputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFEDDC = ( JDATAS_MASK & ( buffer->outputBuffer.dataCount ) );
+            /* <-QAC 0306 */
+
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINLC ,buffer->inputBuffer.isEnable );
+            R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTC ,buffer->outputBuffer.isEnable );
+            break;
+
+        case JCU_STATUS_DECODE:
+            /* ->QAC 0306 */
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINRINI ,buffer->inputBuffer.isInitAddress );
+            if ((buffer->inputBuffer.isEnable != false) && (buffer->inputBuffer.isInitAddress != false)) {
+                JCU.JIFDSA = (uint32_t)(buffer->inputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFDSDC = ( JDATAS_MASK & (buffer->inputBuffer.dataCount ) );
+
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTRINI, buffer->outputBuffer.isInitAddress );
+            if ((buffer->outputBuffer.isEnable != false) && (buffer->outputBuffer.isInitAddress != false)) {
+                JCU.JIFDDA = (uint32_t)(buffer->outputBuffer.restartAddress);
+            } /* end if */
+            JCU.JIFDDLC = ( LINES_MASK & ( buffer->outputBuffer.dataCount ) );
+            /* <-QAC 0306 */
+
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINC, buffer->inputBuffer.isEnable );
+            R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTLC, buffer->outputBuffer.isEnable );
+            break;
+
+        case JCU_CODEC_NOT_SELECTED:
+            /* ->QAC 2018 : For MISRA 15.3, SEC R3.5.2 */
+        default:
+            /* <-QAC 2018 */
+            R_NOOP();  /* NOT REACHED */
+            break;
+    } /* end switch */
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForContinue]
+* @brief         SetRegisterForContinue
+* @param[in]     type
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForContinue(
+    const jcu_continue_type_t  type)
+{
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    IF_DQ ( self == NULL ) {
+        goto fin;
+    } /* end if */
+
+    /* Restart register setting */
+    switch (type) {
+        case JCU_INPUT_BUFFER:
+            if (self->Codec == JCU_STATUS_DECODE) {
+                R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINRCMD, REG_F_SET );
+            } else {
+                R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINRCMD, REG_F_SET );
+            } /* end if */
+            break;
+
+        case JCU_OUTPUT_BUFFER:
+            if (self->Codec == JCU_STATUS_DECODE) {
+                R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTRCMD, REG_F_SET );
+            } else {
+                R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTRCMD, REG_F_SET );
+            } /* end if */
+            break;
+
+        case JCU_IMAGE_INFO:
+            R_SET_REG_BIT_FIELD( JCU.JCCMD, JRST, REG_F_SET );
+            break;
+
+            /* ->QAC 2018 : For MISRA 15.3, SEC R3.5.2 */
+        default:
+            /* <-QAC 2018 */
+            R_NOOP();  /* NOT REACHED */
+            break;
+    } /* end switch */
+
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetDecodePrm]
+* @brief         SetRegisterForSetDecod
+* @param[in]     decode
+* @param[in]     buffer
+* @param[in]     interruptKind
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetDecodePrm(
+    const jcu_decode_param_t   *const decode,
+    const jcu_buffer_param_t   *const buffer)
+{
+    const uint32_t byteSize[KIND_COLOR_FORMAT] =
+        /* ->SEC M1.10.1 Table data. */
+    {
+        2u, /* JCU_OUTPUT_YCbCr422 */
+        4u, /* JCU_OUTPUT_ARGB8888 */
+        2u  /* JCU_OUTPUT_RGB565   */
+    };
+    /* <-SEC M1.10.1 */
+
+    if ((decode == NULL) || (buffer == NULL)) {
+        goto fin;
+    } /* end if */
+
+    /* Settings for the cull */
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, VINTER, decode->verticalSubSampling );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, HINTER, decode->horizontalSubSampling );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, OPF, decode->decodeFormat );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, JINSWAP, buffer->source.swapSetting );
+    R_SET_REG_BIT_FIELD( JCU.JIFDCNT, DOUTSWAP, buffer->destination.swapSetting );
+
+    /* Settings for input jpeg file information */
+    /* ->QAC 0306 */
+    JCU.JIFDSA = (uint32_t)(buffer->source.address);
+    /* <-QAC 0306 */
+    /* Settings for output image data information */
+    /* ->QAC 0306 */
+    JCU.JIFDDA = (uint32_t)(buffer->destination.address);
+    /* <-QAC 0306 */
+    R_SET_REG_BIT_FIELD( JCU.JIFDDOFST, DDMW, ((uint32_t)buffer->lineOffset * (uint32_t)(byteSize[decode->decodeFormat])) );
+    R_SET_REG_BIT_FIELD( JCU.JIFDADT, ALPHA, (uint32_t)(decode->alpha) );
+
+
+    /* Setting for Cb/Cr offset */
+    R_SET_REG_BIT_FIELD( JCU.JIFESHSZ, DOUTYCHG, decode->outputCbCrOffset );
+fin:
+    return;
+
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetQtTable]
+* @brief         SetRegisterForSetQtTable
+* @param[in]     tableNo
+* @param[in]     table
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetQtTable(
+    const jcu_table_no_t   tableNo,
+    const uint8_t *const   table)
+{
+    volatile uint8_t  *tableAtRegister;
+    int_fast32_t       counter;
+
+    /* Select the destination of the Quantization table */
+    switch (tableNo) {
+            /* ->QAC 0306 */
+        case JCU_TABLE_NO_0:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL0;
+            break;
+        case JCU_TABLE_NO_1:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL1;
+            break;
+        case JCU_TABLE_NO_2:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL2;
+            break;
+        case JCU_TABLE_NO_3:
+            tableAtRegister = (volatile uint8_t *)&JCU.JCQTBL3;
+            break;
+            /* ->QAC 2018 : For MISRA 15.3, SEC R3.5.2 */
+        default:
+            /* <-QAC 2018 */
+            /* NOT REACHED */
+            return;
+            /* <-QAC 0306 */
+    } /* end switch */
+
+    IF ((tableAtRegister == NULL) || (table == NULL)) {
+        goto fin;
+    } /* end if */
+
+    /* Update the quantization table data */
+    for (counter = 0; counter < NUMBER_OF_QUANTIZATION_TABLE_DATA; counter++) {
+        tableAtRegister[ counter ] = table[ counter ];
+    } /* end for */
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetHuffTbl]
+* @brief         SetRegisterForSetHuffTbl
+* @param[in]     tableNo
+* @param[in]     type
+* @param[in]     table
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetHuffTbl(
+    const jcu_table_no_t   tableNo,
+    const jcu_huff_t       type,
+    const uint8_t         *table)
+{
+    volatile uint8_t  *tableAtRegister;
+    int_fast32_t       copyCount;
+    int_fast32_t       counter;
+
+    /* Select the destination Huffman table and the size of copy data */
+    if (tableNo == JCU_TABLE_NO_0) {
+        /* ->QAC 0306 */
+        if (type == JCU_HUFFMAN_DC) {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBD0;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_DC;
+        } else {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBA0;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_AC;
+        } /* end if */
+        /* <-QAC 0306 */
+    } else {
+        /* ->QAC 0306 */
+        if (type == JCU_HUFFMAN_DC) {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBD1;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_DC;
+        } else {
+            tableAtRegister  = (volatile uint8_t *)&JCU.JCHTBA1;
+            copyCount        = NUMBER_OF_HUFFMAN_TABLE_DATA_AC;
+        } /* end if */
+        /* <-QAC 0306 */
+    }  /* end if */
+
+    IF(table == NULL) {
+        goto fin;
+    } /* end if */
+
+    /* Update the Huffman table */
+    for (counter = 0; counter < copyCount; counter++) {
+        tableAtRegister[ counter ] = table[ counter ];
+    } /* end for */
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetEncodePrm]
+* @brief         SetRegisterForSetEncode
+* @param[in]     encode
+* @param[in]     buffer
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetEncodePrm(
+    const jcu_encode_param_t   *const encode,
+    const jcu_buffer_param_t   *const buffer)
+{
+    jcu_jpeg_format_t encodeFormatTemp;
+    const uint32_t byteSize[KIND_LINEOFFSET] =
+        /* ->SEC M1.10.1 Table data. */
+    {
+        0u, /* Reserved          */
+        2u  /* JCU_JPEG_YCbCr422 */
+    };
+    /* <-SEC M1.10.1 */
+
+    IF ((encode == NULL) || (buffer == NULL)) {
+        goto fin;
+    } /* end if */
+
+    /* Settings for the input image format */
+    R_SET_REG_BIT_FIELD( JCU.JCMOD, REDU, encode->encodeFormat );
+
+    /* Settings for the quantization table */
+    R_SET_REG_BIT_FIELD( JCU.JCQTN, QT1, encode->QuantizationTable[JCU_ELEMENT_Y]  );
+    R_SET_REG_BIT_FIELD( JCU.JCQTN, QT2, encode->QuantizationTable[JCU_ELEMENT_Cb]  );
+    R_SET_REG_BIT_FIELD( JCU.JCQTN, QT3, encode->QuantizationTable[JCU_ELEMENT_Cr]  );
+
+    /* Settings for the Huffman table */
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTA1, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Y])  );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTD1, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Y])  );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTA2, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cb]) );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTD2, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cb]) );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTA3, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cr]) );
+    R_SET_REG_BIT_FIELD( JCU.JCHTN, HTD3, (uint32_t)(encode->HuffmanTable[JCU_ELEMENT_Cr]) );
+
+    /* ->QAC 0306 */
+    JCU.JCDRIU = GET_UPPER_BYTE(encode->DRI_value);
+    JCU.JCDRID = GET_LOWER_BYTE(encode->DRI_value);
+    /* Settings for the image size */
+    /* width setting */
+    JCU.JCHSZU = GET_UPPER_BYTE(encode->width);
+    JCU.JCHSZD = GET_LOWER_BYTE(encode->width);
+    /* height setting */
+    JCU.JCVSZU = GET_UPPER_BYTE(encode->height);
+    JCU.JCVSZD = GET_LOWER_BYTE(encode->height);
+    /* <-QAC 0306 */
+
+
+    /* Settings for input jpeg file information */
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, DINSWAP, buffer->source.swapSetting );
+
+    /* ->QAC 0306 */
+    JCU.JIFESA              = (uint32_t)(buffer->source.address);
+    /* <-QAC 0306 */
+
+    /* Settings for output image data information */
+    R_SET_REG_BIT_FIELD( JCU.JIFECNT, JOUTSWAP, buffer->destination.swapSetting );
+
+    /* ->QAC 0306 */
+    JCU.JIFEDA = (uint32_t)(buffer->destination.address);
+    /* <-QAC 0306 */
+
+    encodeFormatTemp = encode->encodeFormat;
+    if((encodeFormatTemp != JCU_JPEG_YCbCr444) && (encodeFormatTemp != JCU_JPEG_YCbCr422)) {
+        encodeFormatTemp = JCU_JPEG_YCbCr444;
+    } /* end if */
+
+    R_SET_REG_BIT_FIELD( JCU.JIFESOFST, ESMW, ((uint32_t)buffer->lineOffset * (uint32_t)(byteSize[encodeFormatTemp])) );
+
+    /* Setting for Cb/Cr offset */
+    R_SET_REG_BIT_FIELD( JCU.JIFESVSZ, DINYCHG, encode->inputCbCrOffset );
+fin:
+    return;
+
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_SetRegisterForSetPause]
+* @brief
+* @param[out]    is_stop
+* @retval        None
+******************************************************************************/
+void JCU_SetRegisterForSetPause( const bool_t is_pause, const jcu_int_detail_errors_t filter )
+{
+    /* ->QAC 0306 */
+    if ( IS( is_pause ) ) {
+        JCU.JINTE0 = filter | INT3_MASK;
+    } else {
+        JCU.JINTE0 = filter;
+    }
+    /* <-QAC 0306 */
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_GetRegisterForGetImageInfo]
+* @brief         Get "jcu_image_info_t" type value
+* @param[out]    buffer  :jcu_image_info_t
+* @retval        None
+******************************************************************************/
+void JCU_GetRegisterForGetImageInfo(
+    jcu_image_info_t *const buffer)
+{
+    if (buffer == NULL) {
+        goto fin;
+    } /* end if */
+
+    /* Set the register value to the variables */
+    /* ->QAC 0306 */
+    buffer->width           = ((uint32_t)JCU.JCHSZU << SHIFT_8BITS);
+    buffer->width           |= (uint32_t)JCU.JCHSZD;
+    buffer->height          = ((uint32_t)JCU.JCVSZU << SHIFT_8BITS);
+    buffer->height          |= (uint32_t)JCU.JCVSZD;
+    buffer->encodedFormat   = (jcu_jpeg_format_t)R_GET_REG_BIT_FIELD( JCU.JCMOD, REDU );
+    /* <-QAC 0306 */
+
+fin:
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_GetRegisterForGetErrorInfo]
+* @brief         Get "jcu_detail_error_t" type value
+* @param[out]    errorCode
+* @retval        None
+******************************************************************************/
+static void JCU_GetRegisterForGetErrorInfo(
+    jcu_detail_error_t *const errorCode)
+{
+    if (errorCode != NULL) {
+        /* ->QAC 0306 */
+        uint8_t const  code = R_GET_REG_BIT_FIELD( JCU.JCDERR, ERR );
+        /* <-QAC 0306 */
+
+        if ( (uint_fast8_t) code == 0u ) {
+            *errorCode = JCU_JCDERR_OK;
+        } else {
+            *errorCode = (jcu_detail_error_t)( (int_t) code + E_CATEGORY_JCU_JCDERR );
+        }
+    } /* end if */
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [JCU_GetEncodedSize]
+* @brief         GetEncodedSize
+* @param[out]    out_Size
+* @retval        None
+******************************************************************************/
+void JCU_GetEncodedSize(
+    size_t *const out_Size)
+{
+    if (out_Size != NULL) {
+        /* ->QAC 0306 */
+        *out_Size = (((uint32_t)JCU.JCDTCU) << SHIFT_16BITS);
+        *out_Size |= (((uint32_t)JCU.JCDTCM) << SHIFT_8BITS);
+        *out_Size |= ((uint32_t)JCU.JCDTCD);
+        /* <-QAC 0306 */
+    } /* end if */
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: [R_JCU_OnInterrupting]
+* @brief         Operations on interrupting
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_OnInterrupting( const r_ospl_interrupt_t *const  InterruptSource )
+{
+    errnum_t  e;
+    uint32_t  flags0;
+    uint32_t  flags1;
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    R_UNREFERENCED_VARIABLE( InterruptSource );
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    ASSERT_R( self->AsyncStatus.Status == JCU_STATUS_INTERRUPTING,  e=E_STATE; goto fin );
+
+    /* Get interrupt status */
+    /* ->QAC 0306 */
+    flags0 = JCU.JINTS0;
+    flags1 = JCU.JINTS1;
+    R_OSPL_FLAG32_Set( &self->AsyncStatus.InterruptFlags, flags0 );
+    R_OSPL_FLAG32_Set( &self->AsyncStatus.InterruptFlags, flags1 << JCU_SHIFT_JINTS1 );
+
+    /* Clear interrupt status "JINTS0" */
+    if ( flags0 != 0u ) {
+        R_SET_REG_BIT_FIELD( JCU.JCCMD, JEND, 1u );
+        JCU.JINTS0 = (uint8_t) 0u;  /* Write 0 only */
+    }
+
+    /* Clear interrupt status "JINTS1" */
+    JCU.JINTS1 = ~flags1 & JCU_JINTS1_ALL;
+    /* <-QAC 0306 */
+
+    /* Set state */
+    self->AsyncStatus.Status = JCU_STATUS_INTERRUPTED;
+
+    e=0;
+fin:
+    return  e;
+}
+
+/**************************************************************************//**
+* Function Name: [R_JCU_OnInterrupted]
+* @brief         Bottom half operations on interrupting
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_OnInterrupted(void)
+{
+    bit_flags32_t const  sub_status_bits =
+        ( INS3_MASK ) |
+        ( JINF_MASK   << JCU_SHIFT_JINTS1 ) |
+        ( DOUTLF_MASK << JCU_SHIFT_JINTS1 ) |
+        ( DINLF_MASK  << JCU_SHIFT_JINTS1 ) |
+        ( JOUTF_MASK  << JCU_SHIFT_JINTS1 );
+
+    errnum_t         e;
+    uint32_t         cancel_flag;
+    uint32_t         interrupt_flags;
+    bool_t           was_enabled = false;
+    bool_t           is_end;
+    bool_t           or;
+    jcu_errorcode_t  ej;
+    r_ospl_async_t  *notify_async_1 = NULL;
+    r_ospl_async_t  *notify_async_2 = NULL;
+    jcu_i_lock_t *const                i_lock = R_JCU_GetILockObject();
+    jcu_internal_information_t *const  self = R_JCU_GetInternalInformation();
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    was_enabled = self->I_LockVTable->Lock( self->I_Lock );
+
+    ASSERT_R( self->AsyncStatus.Status != JCU_STATUS_UNDEF,  e=E_STATE; goto fin );
+
+    interrupt_flags = R_OSPL_FLAG32_GetAndClear( &self->AsyncStatus.InterruptFlags );
+
+
+    if ( IS_ANY_BITS_SET( interrupt_flags, sub_status_bits ) ) {
+        if ( IS_BIT_NOT_SET( interrupt_flags, INS6_MASK ) ) {
+            self->AsyncStatus.IsPaused = true;
+            self->AsyncStatus.SubStatusFlags = interrupt_flags & sub_status_bits;
+        }
+    }
+
+
+    if ( IS_ANY_BITS_SET( interrupt_flags, INS6_MASK ) ) {
+        is_end = true;
+    } else {
+        is_end = false;
+    }
+
+
+    or = ( (is_end) || (self->AsyncStatus.IsPaused) );
+    if (!or) {
+        or = IS_BIT_SET( interrupt_flags, INS5_MASK );
+    }
+    if (IS( or )) {
+        /* Set "AsyncStatus" */
+        R_OSPL_FLAG32_Clear( &self->AsyncStatus.InterruptEnables, JCU_INTERRUPT_LINE_ALL );
+        self->AsyncStatus.Status = JCU_STATUS_READY;
+        notify_async_1 = self->InterruptCallbackCaller.Async;
+    } else {
+        self->AsyncStatus.Status = JCU_STATUS_RUN;
+    }
+
+
+    IF ( IS_BIT_SET( interrupt_flags, INS5_MASK ) ) {
+        jcu_detail_error_t  ed;
+
+        JCU_GetRegisterForGetErrorInfo( &ed );
+        e = ed;
+        goto fin;
+    }
+
+
+    if ( notify_async_1 != NULL ) {
+        cancel_flag = R_OSPL_FLAG32_Get( &self->AsyncStatus.CancelFlags );
+        if ( IS_BIT_SET( cancel_flag, R_OSPL_FINALIZE_REQUEST ) ) {
+            notify_async_2 = self->AsyncForFinalize;
+            ej= R_JCU_TerminateStep2();
+            IF ( ej != JCU_ERROR_OK ) {
+                e=E_OTHERS;
+                goto fin;
+            }
+        }
+    }
+
+    e=0;
+fin:
+    if ( IS( was_enabled ) ) {
+        /* ->QAC 3353 : "self" is always assigned, if "was_enabled" is true */
+        IF_DQ( self == NULL ) {}  /* QAC 3353 raises SEC R3.2.2 */
+        else {
+            self->I_LockVTable->Unlock( self->I_Lock );
+
+            if ( IS( self->Is_I_LockMaster ) ) {
+                IF_DQ( i_lock == NULL ) {}
+                else {
+                    if ( IS( i_lock->IsRequestedFinalize ) ) {
+                        R_JCU_I_LOCK_Finalize();
+                    }
+                }
+            }
+        }
+        /* <-QAC 3353 */
+    }
+
+    if ( notify_async_1 != NULL ) {
+        R_OSPL_EVENT_Set( notify_async_1->A_Thread, notify_async_1->A_EventValue );
+    }
+    if ( notify_async_2 != NULL ) {
+        R_OSPL_EVENT_Set( notify_async_2->A_Thread, notify_async_2->A_EventValue );
+    }
+
+    return  e;
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/porting/jcu_pl.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,336 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: jcu_pl.c $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description : JCU driver porting layer
+******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "iodefine.h"
+#include  "r_jcu_api.h"
+#include  "r_jcu_pl.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef struct st_jcu_pl_t  jcu_pl_t;
+
+/*[jcu_pl_t]*/
+struct st_jcu_pl_t {
+    const r_ospl_caller_t     *InterruptCallbackCaller;
+    const jcu_async_status_t  *Status;
+};
+
+/*[gs_jcu_pl]*/
+static jcu_pl_t  gs_jcu_pl
+;
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+enum { JCU_INT_PRI = 2 };
+#define  CPG_JCU_CLOCK_POWER_OFF  0x00000002u
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void  JCU_IRQ_JEDI_Handler(void);
+static void  JCU_IRQ_JDTI_Handler(void);
+
+/*[gs_jedi_interrupt_context] JEDI interrupt context */
+/*[gs_jdti_interrupt_context] JDTI interrupt context */
+static const r_ospl_interrupt_t  gs_jedi_interrupt_context = { BSP_INT_SRC_JEDI, 0 };
+static const r_ospl_interrupt_t  gs_jdti_interrupt_context = { BSP_INT_SRC_JDTI, 0 };
+
+
+/**************************************************************************//**
+* Function Name: [R_JCU_SetDefaultAsync]
+* @retval        None
+******************************************************************************/
+void  R_JCU_SetDefaultAsync( r_ospl_async_t *const  Async,  r_ospl_async_type_t AsyncType )
+{
+    IF_DQ( Async == NULL ) {
+        goto fin;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_A_Thread ) ) {
+        Async->A_Thread = NULL;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_A_EventValue ) ) {
+        if ( AsyncType == R_OSPL_ASYNC_TYPE_NORMAL ) {
+            Async->A_EventValue = R_OSPL_A_FLAG;
+        } else {
+            Async->A_EventValue = R_OSPL_FINAL_A_FLAG;
+        }
+    } else {
+        ASSERT_D( IS_BIT_SET( Async->Flags, R_F_OSPL_A_Thread ), R_NOOP() );
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_I_Thread ) ) {
+        Async->I_Thread = NULL;
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_I_EventValue ) ) {
+        Async->I_EventValue = R_OSPL_I_FLAG;
+    } else {
+        ASSERT_D( IS_BIT_SET( Async->Flags, R_F_OSPL_I_Thread ), R_NOOP() );
+    }
+
+    if ( IS_BIT_NOT_SET( Async->Flags, R_F_OSPL_InterruptCallback ) ) {
+        Async->InterruptCallback = &( R_JCU_OnInterruptDefault );    /* MISRA 16.9 */
+    }
+
+    Async->Flags = R_F_OSPL_A_Thread | R_F_OSPL_A_EventValue |
+                   R_F_OSPL_I_Thread | R_F_OSPL_I_EventValue |
+                   R_F_OSPL_InterruptCallback | R_F_OSPL_Delegate;
+fin:
+    return;
+}
+
+
+/**************************************************************************//**
+* Function Name: [R_JCU_OnInitialize]
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_OnInitialize(void)
+{
+    errnum_t         e;
+    bsp_int_err_t    eb;
+    bsp_int_src_t const  num_of_JEDI_IRQ = gs_jedi_interrupt_context.IRQ_Num;
+    bsp_int_src_t const  num_of_JDTI_IRQ = gs_jdti_interrupt_context.IRQ_Num;
+    jcu_pl_t *const  self = &gs_jcu_pl;
+
+    self->InterruptCallbackCaller = NULL;
+    self->Status = NULL;
+
+
+    /* Register "JEDI" */
+    eb= R_BSP_InterruptWrite( num_of_JEDI_IRQ, &( JCU_IRQ_JEDI_Handler ) );  /* MISRA 16.9 */
+    IF ( eb != 0 ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= R_OSPL_SetInterruptPriority( num_of_JEDI_IRQ, JCU_INT_PRI );
+    IF ( e != 0 ) {
+        goto fin;
+    }
+
+
+    /* Register "JDTI" */
+    eb= R_BSP_InterruptWrite( num_of_JDTI_IRQ, &( JCU_IRQ_JDTI_Handler ) );  /* MISRA 16.9 */
+    IF ( eb != 0 ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e= R_OSPL_SetInterruptPriority( num_of_JDTI_IRQ, JCU_INT_PRI );
+    IF ( e != 0 ) {
+        goto fin;
+    }
+
+
+    /* start to suuply the clock for JCU */
+    { /* ->QAC 0306 */
+        uint32_t cpg_reg;
+        cpg_reg = (uint32_t)(CPG.STBCR6) & ~CPG_JCU_CLOCK_POWER_OFF;
+        CPG.STBCR6 =(uint8_t)cpg_reg;
+    } /* <-QAC 0306 */
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/**************************************************************************//**
+* Function Name: [R_JCU_OnFinalize]
+* @retval        Error code, 0=No error and e=0
+******************************************************************************/
+/* ->QAC 3227 : "e" is usually changed in finalize function. */
+errnum_t  R_JCU_OnFinalize( errnum_t e )
+/* <-QAC 3227 */
+{
+    /* stop to suuply the clock for JCU */
+    { /* ->QAC 0306 */
+        uint32_t cpg_reg;
+        cpg_reg = (uint32_t)(CPG.STBCR6) | CPG_JCU_CLOCK_POWER_OFF;
+        CPG.STBCR6 = (uint8_t)cpg_reg;
+    } /* <-QAC 0306 */
+
+    return  e;
+}
+
+
+/******************************************************************************
+* Function Name: [R_JCU_SetInterruptCallbackCaller]
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_SetInterruptCallbackCaller( const r_ospl_caller_t *const  Caller )
+{
+    jcu_pl_t *const  self = &gs_jcu_pl;
+
+    self->InterruptCallbackCaller = Caller;
+
+    return  0;
+}
+
+
+/******************************************************************************
+* Function Name: [R_JCU_OnEnableInterrupt]
+* @retval        None
+******************************************************************************/
+void  R_JCU_OnEnableInterrupt( jcu_interrupt_lines_t const  Enables )
+{
+    bsp_int_err_t  eb;
+
+    if ( IS_BIT_SET( Enables, JCU_INTERRUPT_LINE_JEDI ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_jedi_interrupt_context.IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+
+    if ( IS_BIT_SET( Enables, JCU_INTERRUPT_LINE_JDTI ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_jdti_interrupt_context.IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_ENABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+}
+
+
+/******************************************************************************
+* Function Name: [R_JCU_OnDisableInterrupt]
+* @retval        None
+******************************************************************************/
+void  R_JCU_OnDisableInterrupt( jcu_interrupt_lines_t const  Disables1 )
+{
+    bsp_int_err_t  eb;
+
+    if ( IS_BIT_SET( Disables1, JCU_INTERRUPT_LINE_JEDI ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_jedi_interrupt_context.IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+
+    if ( IS_BIT_SET( Disables1, JCU_INTERRUPT_LINE_JDTI ) ) {
+        bsp_int_src_t const  num_of_IRQ = gs_jdti_interrupt_context.IRQ_Num;
+
+        eb= R_BSP_InterruptControl( num_of_IRQ, BSP_INT_CMD_INTERRUPT_DISABLE, FIT_NO_PTR );
+        ASSERT_D( eb == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( eb ); /* for Release configuration */
+    }
+}
+
+
+/******************************************************************************
+* Function Name: [R_JCU_OnInterruptDefault]
+* @retval        Error code, 0=No error
+******************************************************************************/
+errnum_t  R_JCU_OnInterruptDefault( const r_ospl_interrupt_t *const  InterruptSource,
+                                    const r_ospl_caller_t *const  Caller )
+{
+    errnum_t  e;
+    errnum_t  ee;
+    r_ospl_async_t  *async;
+
+    e = 0;
+    R_AVOID_UNSAFE_ALWAYS_WARNING( e );
+
+    IF_DQ( Caller == NULL ) {
+        goto fin;
+    }
+
+    ee= R_JCU_OnInterrupting( InterruptSource );
+    IF ( (ee != 0) && (e == 0) ) {
+        e = ee;
+    }
+
+    async = Caller->Async;
+
+    if ( async->I_Thread == NULL ) {
+        ee= R_JCU_OnInterrupted();
+        IF ( (ee != 0) && (e == 0) ) {
+            e = ee;
+        }
+    } else {
+        R_OSPL_EVENT_Set( async->I_Thread, async->I_EventValue );
+    }
+
+fin:
+    return  e;
+}
+
+
+/**************************************************************************//**
+* Function Name: [JCU_IRQ_JEDI_Handler]
+* @brief         JEDI (JCU Encode Decode Interrupt) interrupt handler
+* @retval        None
+******************************************************************************/
+static void  JCU_IRQ_JEDI_Handler(void)
+{
+    jcu_pl_t *const                  self = &gs_jcu_pl;
+    const r_ospl_interrupt_t *const  i_context = &gs_jedi_interrupt_context;
+
+    R_OSPL_CallInterruptCallback( self->InterruptCallbackCaller, i_context );
+    GIC_EndInterrupt( BSP_INT_SRC_JEDI );
+}
+
+
+/**************************************************************************//**
+* Function Name: [JCU_IRQ_JDTI_Handler]
+* @brief         JDTI (JCU Data Transfer Interrupt) interrupt handler
+* @retval        None
+******************************************************************************/
+static void  JCU_IRQ_JDTI_Handler(void)
+{
+    jcu_pl_t *const                  self = &gs_jcu_pl;
+    const r_ospl_interrupt_t *const  i_context = &gs_jdti_interrupt_context;
+
+    R_OSPL_CallInterruptCallback( self->InterruptCallbackCaller, i_context );
+    GIC_EndInterrupt( BSP_INT_SRC_JDTI );
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/jcu/userdef/jcu_user.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,119 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: jcu_user.c $
+* $Module: JCU $ $PublicVersion: 1.00 $ (=JCU_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-02-26 13:18:53 +0900#$
+* Description : JCU driver porting layer
+******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "iodefine.h"
+#include  "r_jcu_api.h"
+#ifndef R_OSPL_NDEBUG
+#include  <stdio.h>
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/**************************************************************************//**
+* Function Name: [R_JCU_PrintRegisters]
+* @brief
+* @retval        None
+******************************************************************************/
+#ifndef R_OSPL_NDEBUG
+void  R_JCU_PrintRegisters()
+{
+    printf( "\n" );
+    printf( "JCU Registers\n" );
+    printf( "JCMOD  = 0x%02X\n", JCU.JCMOD  );
+    printf( "JCCMD  = 0x%02X\n", JCU.JCCMD  );
+    printf( "JCQTN  = 0x%02X\n", JCU.JCQTN  );
+    printf( "JCHTN  = 0x%02X\n", JCU.JCHTN  );
+    printf( "JCDRIU = 0x%02X\n", JCU.JCDRIU );
+    printf( "JCDRID = 0x%02X\n", JCU.JCDRID );
+    printf( "JCVSZU = 0x%02X\n", JCU.JCVSZU );
+    printf( "JCVSZD = 0x%02X\n", JCU.JCVSZD );
+    printf( "JCHSZU = 0x%02X\n", JCU.JCHSZU );
+    printf( "JCHSZD = 0x%02X\n", JCU.JCHSZD );
+    printf( "JCDTCU = 0x%02X\n", JCU.JCDTCU );
+    printf( "JCDTCM = 0x%02X\n", JCU.JCDTCM );
+    printf( "JCDTCD = 0x%02X\n", JCU.JCDTCD );
+    printf( "JINTE0 = 0x%02X\n", JCU.JINTE0 );
+    printf( "JINTS0 = 0x%02X\n", JCU.JINTS0 );
+    printf( "JCDERR = 0x%02X\n", JCU.JCDERR );
+    printf( "JCRST  = 0x%02X\n", JCU.JCRST  );
+    printf( "JIFECNT   = 0x%08X\n", (uint_fast32_t) JCU.JIFECNT   );
+    /* Cast is for avoiding "format" warning of GCC_ARM */
+    printf( "JIFESA    = 0x%08X\n", (uint_fast32_t) JCU.JIFESA    );
+    printf( "JIFESOFST = 0x%08X\n", (uint_fast32_t) JCU.JIFESOFST );
+    printf( "JIFEDA    = 0x%08X\n", (uint_fast32_t) JCU.JIFEDA    );
+    printf( "JIFESLC   = 0x%08X\n", (uint_fast32_t) JCU.JIFESLC   );
+    printf( "JIFEDDC   = 0x%08X\n", (uint_fast32_t) JCU.JIFEDDC   );
+    printf( "JIFDCNT   = 0x%08X\n", (uint_fast32_t) JCU.JIFDCNT   );
+    printf( "JIFDSA    = 0x%08X\n", (uint_fast32_t) JCU.JIFDSA    );
+    printf( "JIFDDOFST = 0x%08X\n", (uint_fast32_t) JCU.JIFDDOFST );
+    printf( "JIFDDA    = 0x%08X\n", (uint_fast32_t) JCU.JIFDDA    );
+    printf( "JIFDSDC   = 0x%08X\n", (uint_fast32_t) JCU.JIFDSDC   );
+    printf( "JIFDDLC   = 0x%08X\n", (uint_fast32_t) JCU.JIFDDLC   );
+    printf( "JIFDADT   = 0x%08X\n", (uint_fast32_t) JCU.JIFDADT   );
+    printf( "JINTE1    = 0x%08X\n", (uint_fast32_t) JCU.JINTE1    );
+    printf( "JINTS1    = 0x%08X\n", (uint_fast32_t) JCU.JINTS1    );
+    printf( "JIFESVSZ  = 0x%08X\n", (uint_fast32_t) JCU.JIFESVSZ  );
+    printf( "JIFESHSZ  = 0x%08X\n", (uint_fast32_t) JCU.JIFESHSZ  );
+    printf( "JCQTBL0[0] = 0x%02X\n", (uint_fast32_t) JCU.JCQTBL0 );
+    printf( "JCQTBL1[0] = 0x%02X\n", (uint_fast32_t) JCU.JCQTBL1 );
+    printf( "JCQTBL2[0] = 0x%02X\n", (uint_fast32_t) JCU.JCQTBL2 );
+    printf( "JCQTBL3[0] = 0x%02X\n", (uint_fast32_t) JCU.JCQTBL3 );
+    printf( "JCHTBD0[0] = 0x%02X\n", (uint_fast32_t) JCU.JCHTBD0 );
+    printf( "JCHTBA0[0] = 0x%02X\n", (uint_fast32_t) JCU.JCHTBA0 );
+    printf( "JCHTBD1[0] = 0x%02X\n", (uint_fast32_t) JCU.JCHTBD1 );
+    printf( "JCHTBA1[0] = 0x%02X\n", (uint_fast32_t) JCU.JCHTBA1 );
+}
+#endif
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/cpu.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,93 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  cpu.h
+* @brief   CPU related FIT BSP.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef CPU_H
+#define CPU_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "cpu_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "cpu_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "cpu_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Globally enables interrupts.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+void  R_BSP_InterruptsEnable(void);
+
+
+/**
+* @brief   Globally disables interrupts.
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+void  R_BSP_InterruptsDisable(void);
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* CPU_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/locking.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,116 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  locking.h
+* @brief   Lock related FIT BSP. Functions.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef LOCKING_H
+#define LOCKING_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "Project_Config.h"
+#if BSP_CFG_USER_LOCKING_ENABLED
+#include "locking_user.h"
+#endif
+#include "r_typedefs.h"
+#include "locking_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "locking_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "locking_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "locking_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/**
+* @brief   Attempts to reserve a hardware peripheral lock.
+*
+* @param   HardwareIndex Index of lock to acquire from the hardware lock array.
+* @return  true = Successful, false = Failure
+*/
+bool_t  R_BSP_HardwareLock( mcu_lock_t const  HardwareIndex );
+
+
+/**
+* @brief   Releases a hardware peripheral lock.
+*
+* @param   HardwareIndex Index of lock to release from the hardware lock array.
+* @return  true = Successful, false = Failure
+*/
+bool_t  R_BSP_HardwareUnlock( mcu_lock_t const  HardwareIndex );
+
+
+/**
+* @brief   Attempts to reserve a lock.
+*
+* @param   LockObject Pointer to lock structure with lock to try and acquire.
+* @return  true = Successful, false = Failure
+*/
+bool_t  R_BSP_SoftwareLock( BSP_CFG_USER_LOCKING_TYPE *const  LockObject );
+
+
+/**
+* @brief   Releases a lock.
+*
+* @param   LockObject Pointer to lock structure with lock to release.
+* @return  true = Successful, false = Failure
+*/
+bool_t  R_BSP_SoftwareUnlock( BSP_CFG_USER_LOCKING_TYPE *const  LockObject );
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* LOCKING_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/locking_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,195 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  locking_typedef.h
+* @brief   Lock related FIT BSP. Data types.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 38 $
+* $Date:: 2014-05-15 16:39:09 +0900#$
+*/
+
+#ifndef LOCKING_TYPEDEF_H
+#define LOCKING_TYPEDEF_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  r_ospl_c_lock_t
+* @brief  C-lock
+*/
+typedef struct st_r_ospl_c_lock_t  r_ospl_c_lock_t;
+struct st_r_ospl_c_lock_t {
+
+    /** IsLocked */
+    volatile bool_t  IsLocked;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  BSP_CFG_USER_LOCKING_TYPE
+* @brief  C-lock (FIT BSP portable)
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if ! BSP_CFG_USER_LOCKING_ENABLED
+#define  BSP_CFG_USER_LOCKING_TYPE  r_ospl_c_lock_t
+#endif
+
+
+/**
+* @enum   mcu_lock_t
+* @brief  Hardware channel number for locking
+*
+*    : BSP_LOCK_ADC
+*    @par :
+*/
+typedef enum {
+    BSP_LOCK_ADC,
+    BSP_LOCK_BSC,
+    BSP_LOCK_CEU,
+    BSP_LOCK_CPG,
+    BSP_LOCK_DISC0,
+    BSP_LOCK_DISC1,
+    BSP_LOCK_DMAC0,
+    BSP_LOCK_DMAC1,
+    BSP_LOCK_DMAC2,
+    BSP_LOCK_DMAC3,
+    BSP_LOCK_DMAC4,
+    BSP_LOCK_DMAC5,
+    BSP_LOCK_DMAC6,
+    BSP_LOCK_DMAC7,
+    BSP_LOCK_DMAC8,
+    BSP_LOCK_DMAC9,
+    BSP_LOCK_DMAC10,
+    BSP_LOCK_DMAC11,
+    BSP_LOCK_DMAC12,
+    BSP_LOCK_DMAC13,
+    BSP_LOCK_DMAC14,
+    BSP_LOCK_DMAC15,
+    BSP_LOCK_DVDEC0,
+    BSP_LOCK_DVDEC1,
+    BSP_LOCK_ETHER,
+    BSP_LOCK_FLCTL,
+    BSP_LOCK_GPIO,
+    BSP_LOCK_IEB,
+    BSP_LOCK_INB,
+    BSP_LOCK_INTC,
+    BSP_LOCK_IRDA,
+    BSP_LOCK_JCU,
+    BSP_LOCK_I2C,
+    BSP_LOCK_LIN0,
+    BSP_LOCK_LIN1,
+    BSP_LOCK_LVDS,
+    BSP_LOCK_MLB,
+    BSP_LOCK_MMC,
+    BSP_LOCK_MTU2,
+    BSP_LOCK_OSTM0,
+    BSP_LOCK_OSTM1,
+    BSP_LOCK_PFV0,
+    BSP_LOCK_PFV1,
+    BSP_LOCK_PWM,
+    BSP_LOCK_RIIC0,
+    BSP_LOCK_RIIC1,
+    BSP_LOCK_RIIC2,
+    BSP_LOCK_RIIC3,
+    BSP_LOCK_ROMDEC,
+    BSP_LOCK_RSCAN0,
+    BSP_LOCK_RSPI0,
+    BSP_LOCK_RSPI1,
+    BSP_LOCK_RSPI2,
+    BSP_LOCK_RSPI3,
+    BSP_LOCK_RSPI4,
+    BSP_LOCK_RTC,
+    BSP_LOCK_SCIF0,
+    BSP_LOCK_SCIF1,
+    BSP_LOCK_SCIF2,
+    BSP_LOCK_SCIF3,
+    BSP_LOCK_SCIF4,
+    BSP_LOCK_SCIF5,
+    BSP_LOCK_SCIF6,
+    BSP_LOCK_SCIF7,
+    BSP_LOCK_SCIM0,
+    BSP_LOCK_SCIM1,
+    BSP_LOCK_SCUX,
+    BSP_LOCK_SDG0,
+    BSP_LOCK_SDG1,
+    BSP_LOCK_SDG2,
+    BSP_LOCK_SDG3,
+    BSP_LOCK_SPDIF,
+    BSP_LOCK_SPIBSC0,
+    BSP_LOCK_SPIBSC1,
+    BSP_LOCK_SSIF0,
+    BSP_LOCK_SSIF1,
+    BSP_LOCK_SSIF2,
+    BSP_LOCK_SSIF3,
+    BSP_LOCK_SSIF4,
+    BSP_LOCK_SSIF5,
+    BSP_LOCK_USB200,
+    BSP_LOCK_USB201,
+    BSP_LOCK_VDC50,
+    BSP_LOCK_VDC51,
+    BSP_LOCK_WDT,
+    BSP_NUM_LOCKS /* This entry is not a valid lock. It is used for sizing
+		g_bsp_Locks[] array below. Do not touch! */
+} mcu_lock_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "mcu_interrupts.h" */
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* LOCKING_TYPEDEF_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/locking_user.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,212 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  locking_user.h
+* @brief   Lock related FIT BSP. User defined.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef LOCKING_USER_H
+#define LOCKING_USER_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_typedefs.h"
+#include  "locking_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  r_ospl_user_lock_t
+* @brief  Example of user defined lock type
+*/
+typedef struct st_r_ospl_user_lock_t  r_ospl_user_lock_t;
+struct st_r_ospl_user_lock_t {
+    int  UserLockMember;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  BSP_CFG_USER_LOCKING_TYPE
+* @brief  C-lock (FIT BSP portable)
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    This is enabled, when "BSP_CFG_USER_LOCKING_ENABLED == 1".
+*/
+#define  BSP_CFG_USER_LOCKING_TYPE  r_ospl_user_lock_t
+
+
+/**
+* @def  BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION
+* @brief  Start C-lock for software module
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    This is enabled, when "BSP_CFG_USER_LOCKING_ENABLED == 1".
+*/
+#define  BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION    R_OSPL_USER_LOCK_SoftwareLock
+
+
+/**
+* @def  BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION
+* @brief  End C-lock for software module
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    This is enabled, when "BSP_CFG_USER_LOCKING_ENABLED == 1".
+*/
+#define  BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION  R_OSPL_USER_LOCK_SoftwareUnlock
+
+
+/**
+* @def  BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION
+* @brief  Start C-lock for hardware module
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    This is enabled, when "BSP_CFG_USER_LOCKING_ENABLED == 1".
+*/
+#define  BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION    R_OSPL_USER_LOCK_HardwareLock
+
+
+/**
+* @def  BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION
+* @brief  End C-lock for hardware module
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    This is enabled, when "BSP_CFG_USER_LOCKING_ENABLED == 1".
+*/
+#define  BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION  R_OSPL_USER_LOCK_HardwareUnlock
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Example of BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if BSP_CFG_USER_LOCKING_ENABLED == 1
+bool_t  R_OSPL_USER_LOCK_SoftwareLock( r_ospl_user_lock_t *LockObject );
+#endif
+
+
+/**
+* @brief   Example of BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if BSP_CFG_USER_LOCKING_ENABLED == 1
+bool_t  R_OSPL_USER_LOCK_SoftwareUnlock( r_ospl_user_lock_t *LockObject );
+#endif
+
+
+/**
+* @brief   Example of BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if BSP_CFG_USER_LOCKING_ENABLED == 1
+bool_t  R_OSPL_USER_LOCK_HardwareLock( mcu_lock_t  HardwareIndex );
+#endif
+
+
+/**
+* @brief   Example of BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if BSP_CFG_USER_LOCKING_ENABLED == 1
+bool_t  R_OSPL_USER_LOCK_HardwareUnlock( mcu_lock_t  HardwareIndex );
+#endif
+
+
+/**
+* @brief   For Test
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if BSP_CFG_USER_LOCKING_ENABLED == 1
+r_ospl_user_lock_t  *R_OSPL_GetHardwareLockObjectForTest( mcu_lock_t  HardwareIndex );
+#endif
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* LOCKING_USER_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/mcu_interrupts.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,107 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  mcu_interrupts.h
+* @brief   Interrupt related FIT BSP. Functions.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef MCU_INTERRUPTS_H
+#define MCU_INTERRUPTS_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "Project_Config.h"
+#include "mcu_interrupts_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Registers a interrupt handler
+*
+* @param   IRQ_Num Interrupt request number
+* @param   Callback The function as interrupt handler
+* @return  Error code.  If there is no error, the return value is BSP_INT_SUCCESS.
+*/
+bsp_int_err_t  R_BSP_InterruptWrite( bsp_int_src_t const  IRQ_Num,  bsp_int_cb_t const  Callback );
+
+
+/**
+* @brief   Returns registered interrupt handler
+*
+* @param   IRQ_Num Interrupt request number
+* @param   out_Callback Output: the function as interrupt handler
+* @return  Error code.  If there is no error, the return value is BSP_INT_SUCCESS.
+*/
+bsp_int_err_t  R_BSP_InterruptRead( bsp_int_src_t const  IRQ_Num,  bsp_int_cb_t *const  out_Callback );
+
+
+/**
+* @brief   Controls related to the interrupt
+*
+* @param   IRQ_Num Interrupt request number
+* @param   Command Control command. See <bsp_int_cmd_t>
+* @param   NotUsed Depend on "Command" argument
+* @return  Error code.  If there is no error, the return value is BSP_INT_SUCCESS.
+*/
+bsp_int_err_t  R_BSP_InterruptControl( bsp_int_src_t const  IRQ_Num,  bsp_int_cmd_t const  Command,
+                                       void *const  NotUsed );
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* MCU_INTERRUPTS_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/mcu_interrupts_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,658 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  mcu_interrupts_typedef.h
+* @brief   Interrupt related FIT BSP. Data types.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef MCU_INTERRUPTS_TYPEDEF_H
+#define MCU_INTERRUPTS_TYPEDEF_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_typedefs.h"
+#include  "r_multi_compiler_typedef.h"
+#if  IS_MBED_USED
+#include  "VKRZA1H.h"
+#else
+#include  "Renesas_RZ_A1.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   bsp_int_err_t
+* @brief  Error code defined by FIT BSP.
+*
+*    - BSP_INT_SUCCESS - 0
+*    - BSP_INT_ERR_NO_REGISTERED_CALLBACK - 0x2101
+*    - BSP_INT_ERR_INVALID_ARG - 1
+*    - BSP_INT_ERR_UNSUPPORTED - 15
+*/
+typedef enum {
+    BSP_INT_SUCCESS = 0,
+    BSP_INT_ERR_NO_REGISTERED_CALLBACK = 0x2101,
+    BSP_INT_ERR_INVALID_ARG = 1,
+    BSP_INT_ERR_UNSUPPORTED = 15
+}
+                          bsp_int_err_t;
+
+
+/**
+* @brief   Interrupt Handler
+*
+* @param   int_sense uint32_t
+* @return  None
+*/
+typedef void  (* bsp_int_cb_t )(void);
+
+
+/**
+* @enum   bsp_int_cmd_t
+* @brief  Control command related to the interrupt.
+*
+*    - BSP_INT_CMD_INTERRUPT_ENABLE - 0
+*    - BSP_INT_CMD_INTERRUPT_DISABLE - 1
+*/
+typedef enum {
+    BSP_INT_CMD_INTERRUPT_ENABLE,
+    BSP_INT_CMD_INTERRUPT_DISABLE
+} bsp_int_cmd_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  FIT_NO_PTR
+* @brief  None as pointer type
+*/
+#define  FIT_NO_PTR  ( (void*) 0 )
+
+
+/**
+* @def  FIT_NO_FUNC
+* @brief  None as function pointer type
+*/
+#define  FIT_NO_FUNC ( (void*) 0 )
+
+
+/**
+* @enum   bsp_int_src_t
+* @brief  Interrupt number.
+*/
+typedef IRQn_Type  bsp_int_src_t;
+#define BSP_INT_SRC_SW0             ((IRQn_Type)(0))     /* GIC software interrupt             */
+#define BSP_INT_SRC_SW1             ((IRQn_Type)(1))     /*                                    */
+#define BSP_INT_SRC_SW2             ((IRQn_Type)(2))     /*                                    */
+#define BSP_INT_SRC_SW3             ((IRQn_Type)(3))     /*                                    */
+#define BSP_INT_SRC_SW4             ((IRQn_Type)(4))     /*                                    */
+#define BSP_INT_SRC_SW5             ((IRQn_Type)(5))     /*                                    */
+#define BSP_INT_SRC_SW6             ((IRQn_Type)(6))     /*                                    */
+#define BSP_INT_SRC_SW7             ((IRQn_Type)(7))     /*                                    */
+#define BSP_INT_SRC_SW8             ((IRQn_Type)(8))     /*                                    */
+#define BSP_INT_SRC_SW9             ((IRQn_Type)(9))     /*                                    */
+#define BSP_INT_SRC_SW10            ((IRQn_Type)(10))    /*                                    */
+#define BSP_INT_SRC_SW11            ((IRQn_Type)(11))    /*                                    */
+#define BSP_INT_SRC_SW12            ((IRQn_Type)(12))    /*                                    */
+#define BSP_INT_SRC_SW13            ((IRQn_Type)(13))    /*                                    */
+#define BSP_INT_SRC_SW14            ((IRQn_Type)(14))    /*                                    */
+#define BSP_INT_SRC_SW15            ((IRQn_Type)(15))    /*                                    */
+#define BSP_INT_SRC_PMUIRQ0         ((IRQn_Type)(16))    /* CPU                                */
+#define BSP_INT_SRC_COMMRX0         ((IRQn_Type)(17))    /*                                    */
+#define BSP_INT_SRC_COMMTX0         ((IRQn_Type)(18))    /*                                    */
+#define BSP_INT_SRC_CTIIRQ0         ((IRQn_Type)(19))    /*                                    */
+#define BSP_INT_SRC_IRQ0            ((IRQn_Type)(32))    /* IRQ                                */
+#define BSP_INT_SRC_IRQ1            ((IRQn_Type)(33))    /*                                    */
+#define BSP_INT_SRC_IRQ2            ((IRQn_Type)(34))    /*                                    */
+#define BSP_INT_SRC_IRQ3            ((IRQn_Type)(35))    /*                                    */
+#define BSP_INT_SRC_IRQ4            ((IRQn_Type)(36))    /*                                    */
+#define BSP_INT_SRC_IRQ5            ((IRQn_Type)(37))    /*                                    */
+#define BSP_INT_SRC_IRQ6            ((IRQn_Type)(38))    /*                                    */
+#define BSP_INT_SRC_IRQ7            ((IRQn_Type)(39))    /*                                    */
+#define BSP_INT_SRC_PL310ERR        ((IRQn_Type)(40))    /* Level 2 cache                      */
+#define BSP_INT_SRC_DMAINT0         ((IRQn_Type)(41))    /* Direct memory access controller    */
+#define BSP_INT_SRC_DMAINT1         ((IRQn_Type)(42))    /*                                    */
+#define BSP_INT_SRC_DMAINT2         ((IRQn_Type)(43))    /*                                    */
+#define BSP_INT_SRC_DMAINT3         ((IRQn_Type)(44))    /*                                    */
+#define BSP_INT_SRC_DMAINT4         ((IRQn_Type)(45))    /*                                    */
+#define BSP_INT_SRC_DMAINT5         ((IRQn_Type)(46))    /*                                    */
+#define BSP_INT_SRC_DMAINT6         ((IRQn_Type)(47))    /*                                    */
+#define BSP_INT_SRC_DMAINT7         ((IRQn_Type)(48))    /*                                    */
+#define BSP_INT_SRC_DMAINT8         ((IRQn_Type)(49))    /*                                    */
+#define BSP_INT_SRC_DMAINT9         ((IRQn_Type)(50))    /*                                    */
+#define BSP_INT_SRC_DMAINT10        ((IRQn_Type)(51))    /*                                    */
+#define BSP_INT_SRC_DMAINT11        ((IRQn_Type)(52))    /*                                    */
+#define BSP_INT_SRC_DMAINT12        ((IRQn_Type)(53))    /*                                    */
+#define BSP_INT_SRC_DMAINT13        ((IRQn_Type)(54))    /*                                    */
+#define BSP_INT_SRC_DMAINT14        ((IRQn_Type)(55))    /*                                    */
+#define BSP_INT_SRC_DMAINT15        ((IRQn_Type)(56))    /*                                    */
+#define BSP_INT_SRC_DMAERR          ((IRQn_Type)(57))    /*                                    */
+#define BSP_INT_SRC_USBI0           ((IRQn_Type)(73))    /* USB 2.0 host/function module       */
+#define BSP_INT_SRC_USBI1           ((IRQn_Type)(74))    /*                                    */
+#define BSP_INT_SRC_S0_VI_VSYNC0    ((IRQn_Type)(75))    /* Video display controller 5         */
+#define BSP_INT_SRC_S0_LO_VSYNC0    ((IRQn_Type)(76))    /*                                    */
+#define BSP_INT_SRC_S0_VSYNCERR0    ((IRQn_Type)(77))    /*                                    */
+#define BSP_INT_SRC_GR3_VLINE0      ((IRQn_Type)(78))    /*                                    */
+#define BSP_INT_SRC_S0_VFIELD0      ((IRQn_Type)(79))    /*                                    */
+#define BSP_INT_SRC_IV1_VBUFERR0    ((IRQn_Type)(80))    /*                                    */
+#define BSP_INT_SRC_IV3_VBUFERR0    ((IRQn_Type)(81))    /*                                    */
+#define BSP_INT_SRC_IV5_VBUFERR0    ((IRQn_Type)(82))    /*                                    */
+#define BSP_INT_SRC_IV6_VBUFERR0    ((IRQn_Type)(83))    /*                                    */
+#define BSP_INT_SRC_S0_WLINE0       ((IRQn_Type)(84))    /*                                    */
+#define BSP_INT_SRC_S1_VI_VSYNC0    ((IRQn_Type)(85))    /*                                    */
+#define BSP_INT_SRC_S1_LO_VSYNC0    ((IRQn_Type)(86))    /*                                    */
+#define BSP_INT_SRC_S1_VSYNCERR0    ((IRQn_Type)(87))    /*                                    */
+#define BSP_INT_SRC_S1_VFIELD0      ((IRQn_Type)(88))    /*                                    */
+#define BSP_INT_SRC_IV2_VBUFERR0    ((IRQn_Type)(89))    /*                                    */
+#define BSP_INT_SRC_IV4_VBUFERR0    ((IRQn_Type)(90))    /*                                    */
+#define BSP_INT_SRC_S1_WLINE0       ((IRQn_Type)(91))    /*                                    */
+#define BSP_INT_SRC_OIR_VI_VSYNC0   ((IRQn_Type)(92))    /*                                    */
+#define BSP_INT_SRC_OIR_LO_VSYNC0   ((IRQn_Type)(93))    /*                                    */
+#define BSP_INT_SRC_OIR_VSYNCERR0   ((IRQn_Type)(94))    /*                                    */
+#define BSP_INT_SRC_OIR_VFIELD0     ((IRQn_Type)(95))    /*                                    */
+#define BSP_INT_SRC_IV7_VBUFERR0    ((IRQn_Type)(96))    /*                                    */
+#define BSP_INT_SRC_IV8_VBUFERR0    ((IRQn_Type)(97))    /*                                    */
+#define BSP_INT_SRC_OIR_WLINE0      ((IRQn_Type)(98))    /*                                    */
+#define BSP_INT_SRC_S0_VI_VSYNC1    ((IRQn_Type)(99))    /*                                    */
+#define BSP_INT_SRC_S0_LO_VSYNC1    ((IRQn_Type)(100))   /*                                    */
+#define BSP_INT_SRC_S0_VSYNCERR1    ((IRQn_Type)(101))   /*                                    */
+#define BSP_INT_SRC_GR3_VLINE1      ((IRQn_Type)(102))   /*                                    */
+#define BSP_INT_SRC_S0_VFIELD1      ((IRQn_Type)(103))   /*                                    */
+#define BSP_INT_SRC_IV1_VBUFERR1    ((IRQn_Type)(104))   /*                                    */
+#define BSP_INT_SRC_IV3_VBUFERR1    ((IRQn_Type)(105))   /*                                    */
+#define BSP_INT_SRC_IV5_VBUFERR1    ((IRQn_Type)(106))   /*                                    */
+#define BSP_INT_SRC_IV6_VBUFERR1    ((IRQn_Type)(107))   /*                                    */
+#define BSP_INT_SRC_S0_WLINE1       ((IRQn_Type)(108))   /*                                    */
+#define BSP_INT_SRC_S1_VI_VSYNC1    ((IRQn_Type)(109))   /*                                    */
+#define BSP_INT_SRC_S1_LO_VSYNC1    ((IRQn_Type)(110))   /*                                    */
+#define BSP_INT_SRC_S1_VSYNCERR1    ((IRQn_Type)(111))   /*                                    */
+#define BSP_INT_SRC_S1_VFIELD1      ((IRQn_Type)(112))   /*                                    */
+#define BSP_INT_SRC_IV2_VBUFERR1    ((IRQn_Type)(113))   /*                                    */
+#define BSP_INT_SRC_IV4_VBUFERR1    ((IRQn_Type)(114))   /*                                    */
+#define BSP_INT_SRC_S1_WLINE1       ((IRQn_Type)(115))   /*                                    */
+#define BSP_INT_SRC_OIR_VI_VSYNC1   ((IRQn_Type)(116))   /*                                    */
+#define BSP_INT_SRC_OIR_LO_VSYNC1   ((IRQn_Type)(117))   /*                                    */
+#define BSP_INT_SRC_OIR_VLINE1      ((IRQn_Type)(118))   /*                                    */
+#define BSP_INT_SRC_OIR_VFIELD1     ((IRQn_Type)(119))   /*                                    */
+#define BSP_INT_SRC_IV7_VBUFERR1    ((IRQn_Type)(120))   /*                                    */
+#define BSP_INT_SRC_IV8_VBUFERR1    ((IRQn_Type)(121))   /*                                    */
+#define BSP_INT_SRC_OIR_WLINE1      ((IRQn_Type)(122))   /*                                    */
+#define BSP_INT_SRC_IMRDI           ((IRQn_Type)(123))   /* Image renderer                     */
+#define BSP_INT_SRC_IMR2I0          ((IRQn_Type)(124))   /*                                    */
+#define BSP_INT_SRC_IMR2I1          ((IRQn_Type)(125))   /*                                    */
+#define BSP_INT_SRC_JEDI            ((IRQn_Type)(126))   /* JPEG Codec unit                    */
+#define BSP_INT_SRC_JDTI            ((IRQn_Type)(127))   /*                                    */
+#define BSP_INT_SRC_CMP0            ((IRQn_Type)(128))   /* Display out comparison unit        */
+#define BSP_INT_SRC_CMP1            ((IRQn_Type)(129))   /*                                    */
+#define BSP_INT_SRC_INT0            ((IRQn_Type)(130))   /* OpenVG-Compliant Renesas graphics processor */
+#define BSP_INT_SRC_INT1            ((IRQn_Type)(131))   /*                                    */
+#define BSP_INT_SRC_INT2            ((IRQn_Type)(132))   /*                                    */
+#define BSP_INT_SRC_INT3            ((IRQn_Type)(133))   /*                                    */
+#define BSP_INT_SRC_OSTM0TINT       ((IRQn_Type)(134))   /* OS timer                           */
+#define BSP_INT_SRC_OSTM1TINT       ((IRQn_Type)(135))   /*                                    */
+#define BSP_INT_SRC_CMI             ((IRQn_Type)(136))   /* Bus state controller               */
+#define BSP_INT_SRC_WTOUT           ((IRQn_Type)(137))   /*                                    */
+#define BSP_INT_SRC_ITI             ((IRQn_Type)(138))   /* Watchdog timer                     */
+#define BSP_INT_SRC_TGI0A           ((IRQn_Type)(139))   /* Multi-function timer pulse unit 2  */
+#define BSP_INT_SRC_TGI0B           ((IRQn_Type)(140))   /*                                    */
+#define BSP_INT_SRC_TGI0C           ((IRQn_Type)(141))   /*                                    */
+#define BSP_INT_SRC_TGI0D           ((IRQn_Type)(142))   /*                                    */
+#define BSP_INT_SRC_TGI0V           ((IRQn_Type)(143))   /*                                    */
+#define BSP_INT_SRC_TGI0E           ((IRQn_Type)(144))   /*                                    */
+#define BSP_INT_SRC_TGI0F           ((IRQn_Type)(145))   /*                                    */
+#define BSP_INT_SRC_TGI1A           ((IRQn_Type)(146))   /*                                    */
+#define BSP_INT_SRC_TGI1B           ((IRQn_Type)(147))   /*                                    */
+#define BSP_INT_SRC_TGI1V           ((IRQn_Type)(148))   /*                                    */
+#define BSP_INT_SRC_TGI1U           ((IRQn_Type)(149))   /*                                    */
+#define BSP_INT_SRC_TGI2A           ((IRQn_Type)(150))   /*                                    */
+#define BSP_INT_SRC_TGI2B           ((IRQn_Type)(151))   /*                                    */
+#define BSP_INT_SRC_TGI2V           ((IRQn_Type)(152))   /*                                    */
+#define BSP_INT_SRC_TGI2U           ((IRQn_Type)(153))   /*                                    */
+#define BSP_INT_SRC_TGI3A           ((IRQn_Type)(154))   /*                                    */
+#define BSP_INT_SRC_TGI3B           ((IRQn_Type)(155))   /*                                    */
+#define BSP_INT_SRC_TGI3C           ((IRQn_Type)(156))   /*                                    */
+#define BSP_INT_SRC_TGI3D           ((IRQn_Type)(157))   /*                                    */
+#define BSP_INT_SRC_TGI3V           ((IRQn_Type)(158))   /*                                    */
+#define BSP_INT_SRC_TGI4A           ((IRQn_Type)(159))   /*                                    */
+#define BSP_INT_SRC_TGI4B           ((IRQn_Type)(160))   /*                                    */
+#define BSP_INT_SRC_TGI4C           ((IRQn_Type)(161))   /*                                    */
+#define BSP_INT_SRC_TGI4D           ((IRQn_Type)(162))   /*                                    */
+#define BSP_INT_SRC_TGI4V           ((IRQn_Type)(163))   /*                                    */
+#define BSP_INT_SRC_CMI1            ((IRQn_Type)(164))   /* Motor control PWM timer            */
+#define BSP_INT_SRC_CMI2            ((IRQn_Type)(165))   /*                                    */
+#define BSP_INT_SRC_SGDEI0          ((IRQn_Type)(166))   /* Sound generator                    */
+#define BSP_INT_SRC_SGDEI1          ((IRQn_Type)(167))   /*                                    */
+#define BSP_INT_SRC_SGDEI2          ((IRQn_Type)(168))   /*                                    */
+#define BSP_INT_SRC_SGDEI3          ((IRQn_Type)(169))   /*                                    */
+#define BSP_INT_SRC_ADI             ((IRQn_Type)(170))   /* 12bit A/D converter                */
+#define BSP_INT_SRC_LMTI            ((IRQn_Type)(171))   /*                                    */
+#define BSP_INT_SRC_SSII0           ((IRQn_Type)(172))   /* Serial sound interface             */
+#define BSP_INT_SRC_SSIRXI0         ((IRQn_Type)(173))   /*                                    */
+#define BSP_INT_SRC_SSITXI0         ((IRQn_Type)(174))   /*                                    */
+#define BSP_INT_SRC_SSII1           ((IRQn_Type)(175))   /*                                    */
+#define BSP_INT_SRC_SSIRXI1         ((IRQn_Type)(176))   /*                                    */
+#define BSP_INT_SRC_SSITXI1         ((IRQn_Type)(177))   /*                                    */
+#define BSP_INT_SRC_SSII2           ((IRQn_Type)(178))   /*                                    */
+#define BSP_INT_SRC_SSIRTI2         ((IRQn_Type)(179))   /*                                    */
+#define BSP_INT_SRC_SSII3           ((IRQn_Type)(180))   /*                                    */
+#define BSP_INT_SRC_SSIRXI3         ((IRQn_Type)(181))   /*                                    */
+#define BSP_INT_SRC_SSITXI3         ((IRQn_Type)(182))   /*                                    */
+#define BSP_INT_SRC_SSII4           ((IRQn_Type)(183))   /*                                    */
+#define BSP_INT_SRC_SSIRTI4         ((IRQn_Type)(184))   /*                                    */
+#define BSP_INT_SRC_SSII5           ((IRQn_Type)(185))   /*                                    */
+#define BSP_INT_SRC_SSIRXI5         ((IRQn_Type)(186))   /*                                    */
+#define BSP_INT_SRC_SSITXI5         ((IRQn_Type)(187))   /*                                    */
+#define BSP_INT_SRC_SPDIFI          ((IRQn_Type)(188))   /* Renesas SPDIF interface            */
+#define BSP_INT_SRC_INTIICTEI0      ((IRQn_Type)(189))   /* I2C interface                      */
+#define BSP_INT_SRC_INTIICRI0       ((IRQn_Type)(190))   /*                                    */
+#define BSP_INT_SRC_INTIICTI0       ((IRQn_Type)(191))   /*                                    */
+#define BSP_INT_SRC_INTIICSPI0      ((IRQn_Type)(192))   /*                                    */
+#define BSP_INT_SRC_INTIICSTI0      ((IRQn_Type)(193))   /*                                    */
+#define BSP_INT_SRC_INTIICNAKI0     ((IRQn_Type)(194))   /*                                    */
+#define BSP_INT_SRC_INTIICALI0      ((IRQn_Type)(195))   /*                                    */
+#define BSP_INT_SRC_INTIICTMOI0     ((IRQn_Type)(196))   /*                                    */
+#define BSP_INT_SRC_INTIICTEI1      ((IRQn_Type)(197))   /*                                    */
+#define BSP_INT_SRC_INTIICRI1       ((IRQn_Type)(198))   /*                                    */
+#define BSP_INT_SRC_INTIICTI1       ((IRQn_Type)(199))   /*                                    */
+#define BSP_INT_SRC_INTIICSPI1      ((IRQn_Type)(200))   /*                                    */
+#define BSP_INT_SRC_INTIICSTI1      ((IRQn_Type)(201))   /*                                    */
+#define BSP_INT_SRC_INTIICNAKI1     ((IRQn_Type)(202))   /*                                    */
+#define BSP_INT_SRC_INTIICALI1      ((IRQn_Type)(203))   /*                                    */
+#define BSP_INT_SRC_INTIICTMOI1     ((IRQn_Type)(204))   /*                                    */
+#define BSP_INT_SRC_INTIICTEI2      ((IRQn_Type)(205))   /*                                    */
+#define BSP_INT_SRC_INTIICRI2       ((IRQn_Type)(206))   /*                                    */
+#define BSP_INT_SRC_INTIICTI2       ((IRQn_Type)(207))   /*                                    */
+#define BSP_INT_SRC_INTIICSPI2      ((IRQn_Type)(208))   /*                                    */
+#define BSP_INT_SRC_INTIICSTI2      ((IRQn_Type)(209))   /*                                    */
+#define BSP_INT_SRC_INTIICNAKI2     ((IRQn_Type)(210))   /*                                    */
+#define BSP_INT_SRC_INTIICALI2      ((IRQn_Type)(211))   /*                                    */
+#define BSP_INT_SRC_INTIICTMOI2     ((IRQn_Type)(212))   /*                                    */
+#define BSP_INT_SRC_INTIICTEI3      ((IRQn_Type)(213))   /*                                    */
+#define BSP_INT_SRC_INTIICRI3       ((IRQn_Type)(214))   /*                                    */
+#define BSP_INT_SRC_INTIICTI3       ((IRQn_Type)(215))   /*                                    */
+#define BSP_INT_SRC_INTIICSPI3      ((IRQn_Type)(216))   /*                                    */
+#define BSP_INT_SRC_INTIICSTI3      ((IRQn_Type)(217))   /*                                    */
+#define BSP_INT_SRC_INTIICNAKI3     ((IRQn_Type)(218))   /*                                    */
+#define BSP_INT_SRC_INTIICALI3      ((IRQn_Type)(219))   /*                                    */
+#define BSP_INT_SRC_INTIICTMOI3     ((IRQn_Type)(220))   /*                                    */
+#define BSP_INT_SRC_BRI0            ((IRQn_Type)(221))   /* Serial Communication Interface with FIFO */
+#define BSP_INT_SRC_ERI0            ((IRQn_Type)(222))   /*                                    */
+#define BSP_INT_SRC_RXI0            ((IRQn_Type)(223))   /*                                    */
+#define BSP_INT_SRC_TXI0            ((IRQn_Type)(224))   /*                                    */
+#define BSP_INT_SRC_BRI1            ((IRQn_Type)(225))   /*                                    */
+#define BSP_INT_SRC_ERI1            ((IRQn_Type)(226))   /*                                    */
+#define BSP_INT_SRC_RXI1            ((IRQn_Type)(227))   /*                                    */
+#define BSP_INT_SRC_TXI1            ((IRQn_Type)(228))   /*                                    */
+#define BSP_INT_SRC_BRI2            ((IRQn_Type)(229))   /*                                    */
+#define BSP_INT_SRC_ERI2            ((IRQn_Type)(230))   /*                                    */
+#define BSP_INT_SRC_RXI2            ((IRQn_Type)(231))   /*                                    */
+#define BSP_INT_SRC_TXI2            ((IRQn_Type)(232))   /*                                    */
+#define BSP_INT_SRC_BRI3            ((IRQn_Type)(233))   /*                                    */
+#define BSP_INT_SRC_ERI3            ((IRQn_Type)(234))   /*                                    */
+#define BSP_INT_SRC_RXI3            ((IRQn_Type)(235))   /*                                    */
+#define BSP_INT_SRC_TXI3            ((IRQn_Type)(236))   /*                                    */
+#define BSP_INT_SRC_BRI4            ((IRQn_Type)(237))   /*                                    */
+#define BSP_INT_SRC_ERI4            ((IRQn_Type)(238))   /*                                    */
+#define BSP_INT_SRC_RXI4            ((IRQn_Type)(239))   /*                                    */
+#define BSP_INT_SRC_TXI4            ((IRQn_Type)(240))   /*                                    */
+#define BSP_INT_SRC_BRI5            ((IRQn_Type)(241))   /*                                    */
+#define BSP_INT_SRC_ERI5            ((IRQn_Type)(242))   /*                                    */
+#define BSP_INT_SRC_RXI5            ((IRQn_Type)(243))   /*                                    */
+#define BSP_INT_SRC_TXI5            ((IRQn_Type)(244))   /*                                    */
+#define BSP_INT_SRC_BRI6            ((IRQn_Type)(245))   /*                                    */
+#define BSP_INT_SRC_ERI6            ((IRQn_Type)(246))   /*                                    */
+#define BSP_INT_SRC_RXI6            ((IRQn_Type)(247))   /*                                    */
+#define BSP_INT_SRC_TXI6            ((IRQn_Type)(248))   /*                                    */
+#define BSP_INT_SRC_BRI7            ((IRQn_Type)(249))   /*                                    */
+#define BSP_INT_SRC_ERI7            ((IRQn_Type)(250))   /*                                    */
+#define BSP_INT_SRC_RXI7            ((IRQn_Type)(251))   /*                                    */
+#define BSP_INT_SRC_TXI7            ((IRQn_Type)(252))   /*                                    */
+#define BSP_INT_SRC_INTRCANGERR     ((IRQn_Type)(253))   /* CAN interface                      */
+#define BSP_INT_SRC_INTRCANGRECC    ((IRQn_Type)(254))   /*                                    */
+#define BSP_INT_SRC_INTRCAN0REC     ((IRQn_Type)(255))   /*                                    */
+#define BSP_INT_SRC_INTRCAN0ERR     ((IRQn_Type)(256))   /*                                    */
+#define BSP_INT_SRC_INTRCAN0TRX     ((IRQn_Type)(257))   /*                                    */
+#define BSP_INT_SRC_INTRCAN1REC     ((IRQn_Type)(258))   /*                                    */
+#define BSP_INT_SRC_INTRCAN1ERR     ((IRQn_Type)(259))   /*                                    */
+#define BSP_INT_SRC_INTRCAN1TRX     ((IRQn_Type)(260))   /*                                    */
+#define BSP_INT_SRC_INTRCAN2REC     ((IRQn_Type)(261))   /*                                    */
+#define BSP_INT_SRC_INTRCAN2ERR     ((IRQn_Type)(262))   /*                                    */
+#define BSP_INT_SRC_INTRCAN2TRX     ((IRQn_Type)(263))   /*                                    */
+#define BSP_INT_SRC_INTRCAN3REC     ((IRQn_Type)(264))   /*                                    */
+#define BSP_INT_SRC_INTRCAN3ERR     ((IRQn_Type)(265))   /*                                    */
+#define BSP_INT_SRC_INTRCAN3TRX     ((IRQn_Type)(266))   /*                                    */
+#define BSP_INT_SRC_INTRCAN4REC     ((IRQn_Type)(267))   /*                                    */
+#define BSP_INT_SRC_INTRCAN4ERR     ((IRQn_Type)(268))   /*                                    */
+#define BSP_INT_SRC_INTRCAN4TRX     ((IRQn_Type)(269))   /*                                    */
+#define BSP_INT_SRC_SPEI0           ((IRQn_Type)(270))   /* Renesas serial peripheral interface */
+#define BSP_INT_SRC_SPRI0           ((IRQn_Type)(271))   /*                                    */
+#define BSP_INT_SRC_SPTI0           ((IRQn_Type)(272))   /*                                    */
+#define BSP_INT_SRC_SPEI1           ((IRQn_Type)(273))   /*                                    */
+#define BSP_INT_SRC_SPRI1           ((IRQn_Type)(274))   /*                                    */
+#define BSP_INT_SRC_SPTI1           ((IRQn_Type)(275))   /*                                    */
+#define BSP_INT_SRC_SPEI2           ((IRQn_Type)(276))   /*                                    */
+#define BSP_INT_SRC_SPRI2           ((IRQn_Type)(277))   /*                                    */
+#define BSP_INT_SRC_SPTI2           ((IRQn_Type)(278))   /*                                    */
+#define BSP_INT_SRC_SPEI3           ((IRQn_Type)(279))   /*                                    */
+#define BSP_INT_SRC_SPRI3           ((IRQn_Type)(280))   /*                                    */
+#define BSP_INT_SRC_SPTI3           ((IRQn_Type)(281))   /*                                    */
+#define BSP_INT_SRC_SPEI4           ((IRQn_Type)(282))   /*                                    */
+#define BSP_INT_SRC_SPRI4           ((IRQn_Type)(283))   /*                                    */
+#define BSP_INT_SRC_SPTI4           ((IRQn_Type)(284))   /*                                    */
+#define BSP_INT_SRC_IEBBTD          ((IRQn_Type)(285))   /* IEBusTM controller                 */
+#define BSP_INT_SRC_IEBBTERR        ((IRQn_Type)(286))   /*                                    */
+#define BSP_INT_SRC_IEBBTSTA        ((IRQn_Type)(287))   /*                                    */
+#define BSP_INT_SRC_IEBBTV          ((IRQn_Type)(288))   /*                                    */
+#define BSP_INT_SRC_ISY             ((IRQn_Type)(289))   /* CD-ROM decoder                     */
+#define BSP_INT_SRC_IERR            ((IRQn_Type)(290))   /*                                    */
+#define BSP_INT_SRC_ITARG           ((IRQn_Type)(291))   /*                                    */
+#define BSP_INT_SRC_ISEC            ((IRQn_Type)(292))   /*                                    */
+#define BSP_INT_SRC_IBUF            ((IRQn_Type)(293))   /*                                    */
+#define BSP_INT_SRC_IREADY          ((IRQn_Type)(294))   /*                                    */
+#define BSP_INT_SRC_FLSTE           ((IRQn_Type)(295))   /* NAND Flash memory controller       */
+#define BSP_INT_SRC_FLTENDI         ((IRQn_Type)(296))   /*                                    */
+#define BSP_INT_SRC_FLTREQ0I        ((IRQn_Type)(297))   /*                                    */
+#define BSP_INT_SRC_FLTREQ1I        ((IRQn_Type)(298))   /*                                    */
+#define BSP_INT_SRC_MMC0            ((IRQn_Type)(299))   /* MMC Host interface                 */
+#define BSP_INT_SRC_MMC1            ((IRQn_Type)(300))   /*                                    */
+#define BSP_INT_SRC_MMC2            ((IRQn_Type)(301))   /*                                    */
+#define BSP_INT_SRC_SDHI0_3         ((IRQn_Type)(302))   /* SD Host interface                  */
+#define BSP_INT_SRC_SDHI0_0         ((IRQn_Type)(303))   /*                                    */
+#define BSP_INT_SRC_SDHI0_1         ((IRQn_Type)(304))   /*                                    */
+#define BSP_INT_SRC_SDHI1_3         ((IRQn_Type)(305))   /*                                    */
+#define BSP_INT_SRC_SDHI1_0         ((IRQn_Type)(306))   /*                                    */
+#define BSP_INT_SRC_SDHI1_1         ((IRQn_Type)(307))   /*                                    */
+#define BSP_INT_SRC_ARM             ((IRQn_Type)(308))   /* Real time clock                    */
+#define BSP_INT_SRC_PRD             ((IRQn_Type)(309))   /*                                    */
+#define BSP_INT_SRC_CUP             ((IRQn_Type)(310))   /*                                    */
+#define BSP_INT_SRC_SCUAI0          ((IRQn_Type)(311))   /* SCUX                               */
+#define BSP_INT_SRC_SCUAI1          ((IRQn_Type)(312))   /*                                    */
+#define BSP_INT_SRC_SCUFDI0         ((IRQn_Type)(313))   /*                                    */
+#define BSP_INT_SRC_SCUFDI1         ((IRQn_Type)(314))   /*                                    */
+#define BSP_INT_SRC_SCUFDI2         ((IRQn_Type)(315))   /*                                    */
+#define BSP_INT_SRC_SCUFDI3         ((IRQn_Type)(316))   /*                                    */
+#define BSP_INT_SRC_SCUFUI0         ((IRQn_Type)(317))   /*                                    */
+#define BSP_INT_SRC_SCUFUI1         ((IRQn_Type)(318))   /*                                    */
+#define BSP_INT_SRC_SCUFUI2         ((IRQn_Type)(319))   /*                                    */
+#define BSP_INT_SRC_SCUFUI3         ((IRQn_Type)(320))   /*                                    */
+#define BSP_INT_SRC_SCUDVI0         ((IRQn_Type)(321))   /*                                    */
+#define BSP_INT_SRC_SCUDVI1         ((IRQn_Type)(322))   /*                                    */
+#define BSP_INT_SRC_SCUDVI2         ((IRQn_Type)(323))   /*                                    */
+#define BSP_INT_SRC_SCUDVI3         ((IRQn_Type)(324))   /*                                    */
+#define BSP_INT_SRC_MLB_CINT        ((IRQn_Type)(325))   /* Media local bus                    */
+#define BSP_INT_SRC_MLB_SINT        ((IRQn_Type)(326))   /*                                    */
+#define BSP_INT_SRC_DRC0            ((IRQn_Type)(327))   /* Dynamic range compalator           */
+#define BSP_INT_SRC_DRC1            ((IRQn_Type)(328))   /*                                    */
+#define BSP_INT_SRC_LINI0_INT_T     ((IRQn_Type)(331))   /* LIN/UART interface                 */
+#define BSP_INT_SRC_LINI0_INT_R     ((IRQn_Type)(332))   /*                                    */
+#define BSP_INT_SRC_LINI0_INT_S     ((IRQn_Type)(333))   /*                                    */
+#define BSP_INT_SRC_LINI0_INT_M     ((IRQn_Type)(334))   /*                                    */
+#define BSP_INT_SRC_LINI1_INT_T     ((IRQn_Type)(335))   /*                                    */
+#define BSP_INT_SRC_LINI1_INT_R     ((IRQn_Type)(336))   /*                                    */
+#define BSP_INT_SRC_LINI1_INT_S     ((IRQn_Type)(337))   /*                                    */
+#define BSP_INT_SRC_LINI1_INT_M     ((IRQn_Type)(338))   /*                                    */
+#define BSP_INT_SRC_SCI_ERI0        ((IRQn_Type)(347))   /* Serial communication interface     */
+#define BSP_INT_SRC_SCI_RXI0        ((IRQn_Type)(348))   /*                                    */
+#define BSP_INT_SRC_SCI_TXI0        ((IRQn_Type)(349))   /*                                    */
+#define BSP_INT_SRC_SCI_TEI0        ((IRQn_Type)(350))   /*                                    */
+#define BSP_INT_SRC_SCI_ERI1        ((IRQn_Type)(351))   /*                                    */
+#define BSP_INT_SRC_SCI_RXI1        ((IRQn_Type)(352))   /*                                    */
+#define BSP_INT_SRC_SCI_TXI1        ((IRQn_Type)(353))   /*                                    */
+#define BSP_INT_SRC_SCI_TEI1        ((IRQn_Type)(354))   /*                                    */
+#define BSP_INT_SRC_AVBI_DATA       ((IRQn_Type)(355))   /* EthernetAVB                        */
+#define BSP_INT_SRC_AVBI_ERROR      ((IRQn_Type)(356))   /*                                    */
+#define BSP_INT_SRC_AVBI_MANAGE     ((IRQn_Type)(357))   /*                                    */
+#define BSP_INT_SRC_AVBI_MAC        ((IRQn_Type)(358))   /*                                    */
+#define BSP_INT_SRC_ETHERI          ((IRQn_Type)(359))   /* Ethernet controller                */
+#define BSP_INT_SRC_CEUI            ((IRQn_Type)(364))   /* Capture engine unit                */
+#define BSP_INT_SRC_H2XMLB_ERRINT   ((IRQn_Type)(381))   /* Internal bus                       */
+#define BSP_INT_SRC_H2XIC1_ERRINT   ((IRQn_Type)(382))   /*                                    */
+#define BSP_INT_SRC_X2HPERI1_ERRINT ((IRQn_Type)(383))   /*                                    */
+#define BSP_INT_SRC_X2HPERI2_ERRINT ((IRQn_Type)(384))   /*                                    */
+#define BSP_INT_SRC_X2HPERI34_ERRINT ((IRQn_Type)(385))  /*                                    */
+#define BSP_INT_SRC_X2HPERI5_ERRINT ((IRQn_Type)(386))   /*                                    */
+#define BSP_INT_SRC_X2HPERI67_ERRINT ((IRQn_Type)(387))  /*                                    */
+#define BSP_INT_SRC_X2HDBGR_ERRINT  ((IRQn_Type)(388))   /*                                    */
+#define BSP_INT_SRC_X2HBSC_ERRINT   ((IRQn_Type)(389))   /*                                    */
+#define BSP_INT_SRC_X2HSPI1_ERRINT  ((IRQn_Type)(390))   /*                                    */
+#define BSP_INT_SRC_X2HSPI2_ERRINT  ((IRQn_Type)(391))   /*                                    */
+#define BSP_INT_SRC_PRRI            ((IRQn_Type)(392))   /*                                    */
+#define BSP_INT_SRC_IFEI0           ((IRQn_Type)(393))   /* Pixel format converter             */
+#define BSP_INT_SRC_OFFI0           ((IRQn_Type)(394))   /*                                    */
+#define BSP_INT_SRC_PFVEI0          ((IRQn_Type)(395))   /*                                    */
+#define BSP_INT_SRC_IFEI1           ((IRQn_Type)(396))   /*                                    */
+#define BSP_INT_SRC_OFFI1           ((IRQn_Type)(397))   /*                                    */
+#define BSP_INT_SRC_PFVEI1          ((IRQn_Type)(398))   /*                                    */
+#define BSP_INT_SRC_TINT0           ((IRQn_Type)(416))   /* Terminal interrupts                */
+#define BSP_INT_SRC_TINT1           ((IRQn_Type)(417))   /*                                    */
+#define BSP_INT_SRC_TINT2           ((IRQn_Type)(418))   /*                                    */
+#define BSP_INT_SRC_TINT3           ((IRQn_Type)(419))   /*                                    */
+#define BSP_INT_SRC_TINT4           ((IRQn_Type)(420))   /*                                    */
+#define BSP_INT_SRC_TINT5           ((IRQn_Type)(421))   /*                                    */
+#define BSP_INT_SRC_TINT6           ((IRQn_Type)(422))   /*                                    */
+#define BSP_INT_SRC_TINT7           ((IRQn_Type)(423))   /*                                    */
+#define BSP_INT_SRC_TINT8           ((IRQn_Type)(424))   /*                                    */
+#define BSP_INT_SRC_TINT9           ((IRQn_Type)(425))   /*                                    */
+#define BSP_INT_SRC_TINT10          ((IRQn_Type)(426))   /*                                    */
+#define BSP_INT_SRC_TINT11          ((IRQn_Type)(427))   /*                                    */
+#define BSP_INT_SRC_TINT12          ((IRQn_Type)(428))   /*                                    */
+#define BSP_INT_SRC_TINT13          ((IRQn_Type)(429))   /*                                    */
+#define BSP_INT_SRC_TINT14          ((IRQn_Type)(430))   /*                                    */
+#define BSP_INT_SRC_TINT15          ((IRQn_Type)(431))   /*                                    */
+#define BSP_INT_SRC_TINT16          ((IRQn_Type)(432))   /*                                    */
+#define BSP_INT_SRC_TINT17          ((IRQn_Type)(433))   /*                                    */
+#define BSP_INT_SRC_TINT18          ((IRQn_Type)(434))   /*                                    */
+#define BSP_INT_SRC_TINT19          ((IRQn_Type)(435))   /*                                    */
+#define BSP_INT_SRC_TINT20          ((IRQn_Type)(436))   /*                                    */
+#define BSP_INT_SRC_TINT21          ((IRQn_Type)(437))   /*                                    */
+#define BSP_INT_SRC_TINT22          ((IRQn_Type)(438))   /*                                    */
+#define BSP_INT_SRC_TINT23          ((IRQn_Type)(439))   /*                                    */
+#define BSP_INT_SRC_TINT24          ((IRQn_Type)(440))   /*                                    */
+#define BSP_INT_SRC_TINT25          ((IRQn_Type)(441))   /*                                    */
+#define BSP_INT_SRC_TINT26          ((IRQn_Type)(442))   /*                                    */
+#define BSP_INT_SRC_TINT27          ((IRQn_Type)(443))   /*                                    */
+#define BSP_INT_SRC_TINT28          ((IRQn_Type)(444))   /*                                    */
+#define BSP_INT_SRC_TINT29          ((IRQn_Type)(445))   /*                                    */
+#define BSP_INT_SRC_TINT30          ((IRQn_Type)(446))   /*                                    */
+#define BSP_INT_SRC_TINT31          ((IRQn_Type)(447))   /*                                    */
+#define BSP_INT_SRC_TINT32          ((IRQn_Type)(448))   /*                                    */
+#define BSP_INT_SRC_TINT33          ((IRQn_Type)(449))   /*                                    */
+#define BSP_INT_SRC_TINT34          ((IRQn_Type)(450))   /*                                    */
+#define BSP_INT_SRC_TINT35          ((IRQn_Type)(451))   /*                                    */
+#define BSP_INT_SRC_TINT36          ((IRQn_Type)(452))   /*                                    */
+#define BSP_INT_SRC_TINT37          ((IRQn_Type)(453))   /*                                    */
+#define BSP_INT_SRC_TINT38          ((IRQn_Type)(454))   /*                                    */
+#define BSP_INT_SRC_TINT39          ((IRQn_Type)(455))   /*                                    */
+#define BSP_INT_SRC_TINT40          ((IRQn_Type)(456))   /*                                    */
+#define BSP_INT_SRC_TINT41          ((IRQn_Type)(457))   /*                                    */
+#define BSP_INT_SRC_TINT42          ((IRQn_Type)(458))   /*                                    */
+#define BSP_INT_SRC_TINT43          ((IRQn_Type)(459))   /*                                    */
+#define BSP_INT_SRC_TINT44          ((IRQn_Type)(460))   /*                                    */
+#define BSP_INT_SRC_TINT45          ((IRQn_Type)(461))   /*                                    */
+#define BSP_INT_SRC_TINT46          ((IRQn_Type)(462))   /*                                    */
+#define BSP_INT_SRC_TINT47          ((IRQn_Type)(463))   /*                                    */
+#define BSP_INT_SRC_TINT48          ((IRQn_Type)(464))   /*                                    */
+#define BSP_INT_SRC_TINT49          ((IRQn_Type)(465))   /*                                    */
+#define BSP_INT_SRC_TINT50          ((IRQn_Type)(466))   /*                                    */
+#define BSP_INT_SRC_TINT51          ((IRQn_Type)(467))   /*                                    */
+#define BSP_INT_SRC_TINT52          ((IRQn_Type)(468))   /*                                    */
+#define BSP_INT_SRC_TINT53          ((IRQn_Type)(469))   /*                                    */
+#define BSP_INT_SRC_TINT54          ((IRQn_Type)(470))   /*                                    */
+#define BSP_INT_SRC_TINT55          ((IRQn_Type)(471))   /*                                    */
+#define BSP_INT_SRC_TINT56          ((IRQn_Type)(472))   /*                                    */
+#define BSP_INT_SRC_TINT57          ((IRQn_Type)(473))   /*                                    */
+#define BSP_INT_SRC_TINT58          ((IRQn_Type)(474))   /*                                    */
+#define BSP_INT_SRC_TINT59          ((IRQn_Type)(475))   /*                                    */
+#define BSP_INT_SRC_TINT60          ((IRQn_Type)(476))   /*                                    */
+#define BSP_INT_SRC_TINT61          ((IRQn_Type)(477))   /*                                    */
+#define BSP_INT_SRC_TINT62          ((IRQn_Type)(478))   /*                                    */
+#define BSP_INT_SRC_TINT63          ((IRQn_Type)(479))   /*                                    */
+#define BSP_INT_SRC_TINT64          ((IRQn_Type)(480))   /*                                    */
+#define BSP_INT_SRC_TINT65          ((IRQn_Type)(481))   /*                                    */
+#define BSP_INT_SRC_TINT66          ((IRQn_Type)(482))   /*                                    */
+#define BSP_INT_SRC_TINT67          ((IRQn_Type)(483))   /*                                    */
+#define BSP_INT_SRC_TINT68          ((IRQn_Type)(484))   /*                                    */
+#define BSP_INT_SRC_TINT69          ((IRQn_Type)(485))   /*                                    */
+#define BSP_INT_SRC_TINT70          ((IRQn_Type)(486))   /*                                    */
+#define BSP_INT_SRC_TINT71          ((IRQn_Type)(487))   /*                                    */
+#define BSP_INT_SRC_TINT72          ((IRQn_Type)(488))   /*                                    */
+#define BSP_INT_SRC_TINT73          ((IRQn_Type)(489))   /*                                    */
+#define BSP_INT_SRC_TINT74          ((IRQn_Type)(490))   /*                                    */
+#define BSP_INT_SRC_TINT75          ((IRQn_Type)(491))   /*                                    */
+#define BSP_INT_SRC_TINT76          ((IRQn_Type)(492))   /*                                    */
+#define BSP_INT_SRC_TINT77          ((IRQn_Type)(493))   /*                                    */
+#define BSP_INT_SRC_TINT78          ((IRQn_Type)(494))   /*                                    */
+#define BSP_INT_SRC_TINT79          ((IRQn_Type)(495))   /*                                    */
+#define BSP_INT_SRC_TINT80          ((IRQn_Type)(496))   /*                                    */
+#define BSP_INT_SRC_TINT81          ((IRQn_Type)(497))   /*                                    */
+#define BSP_INT_SRC_TINT82          ((IRQn_Type)(498))   /*                                    */
+#define BSP_INT_SRC_TINT83          ((IRQn_Type)(499))   /*                                    */
+#define BSP_INT_SRC_TINT84          ((IRQn_Type)(500))   /*                                    */
+#define BSP_INT_SRC_TINT85          ((IRQn_Type)(501))   /*                                    */
+#define BSP_INT_SRC_TINT86          ((IRQn_Type)(502))   /*                                    */
+#define BSP_INT_SRC_TINT87          ((IRQn_Type)(503))   /*                                    */
+#define BSP_INT_SRC_TINT88          ((IRQn_Type)(504))   /*                                    */
+#define BSP_INT_SRC_TINT89          ((IRQn_Type)(505))   /*                                    */
+#define BSP_INT_SRC_TINT90          ((IRQn_Type)(506))   /*                                    */
+#define BSP_INT_SRC_TINT91          ((IRQn_Type)(507))   /*                                    */
+#define BSP_INT_SRC_TINT92          ((IRQn_Type)(508))   /*                                    */
+#define BSP_INT_SRC_TINT93          ((IRQn_Type)(509))   /*                                    */
+#define BSP_INT_SRC_TINT94          ((IRQn_Type)(510))   /*                                    */
+#define BSP_INT_SRC_TINT95          ((IRQn_Type)(511))   /*                                    */
+#define BSP_INT_SRC_TINT96          ((IRQn_Type)(512))   /*                                    */
+#define BSP_INT_SRC_TINT97          ((IRQn_Type)(513))   /*                                    */
+#define BSP_INT_SRC_TINT98          ((IRQn_Type)(514))   /*                                    */
+#define BSP_INT_SRC_TINT99          ((IRQn_Type)(515))   /*                                    */
+#define BSP_INT_SRC_TINT100         ((IRQn_Type)(516))   /*                                    */
+#define BSP_INT_SRC_TINT101         ((IRQn_Type)(517))   /*                                    */
+#define BSP_INT_SRC_TINT102         ((IRQn_Type)(518))   /*                                    */
+#define BSP_INT_SRC_TINT103         ((IRQn_Type)(519))   /*                                    */
+#define BSP_INT_SRC_TINT104         ((IRQn_Type)(520))   /*                                    */
+#define BSP_INT_SRC_TINT105         ((IRQn_Type)(521))   /*                                    */
+#define BSP_INT_SRC_TINT106         ((IRQn_Type)(522))   /*                                    */
+#define BSP_INT_SRC_TINT107         ((IRQn_Type)(523))   /*                                    */
+#define BSP_INT_SRC_TINT108         ((IRQn_Type)(524))   /*                                    */
+#define BSP_INT_SRC_TINT109         ((IRQn_Type)(525))   /*                                    */
+#define BSP_INT_SRC_TINT110         ((IRQn_Type)(526))   /*                                    */
+#define BSP_INT_SRC_TINT111         ((IRQn_Type)(527))   /*                                    */
+#define BSP_INT_SRC_TINT112         ((IRQn_Type)(528))   /*                                    */
+#define BSP_INT_SRC_TINT113         ((IRQn_Type)(529))   /*                                    */
+#define BSP_INT_SRC_TINT114         ((IRQn_Type)(530))   /*                                    */
+#define BSP_INT_SRC_TINT115         ((IRQn_Type)(531))   /*                                    */
+#define BSP_INT_SRC_TINT116         ((IRQn_Type)(532))   /*                                    */
+#define BSP_INT_SRC_TINT117         ((IRQn_Type)(533))   /*                                    */
+#define BSP_INT_SRC_TINT118         ((IRQn_Type)(534))   /*                                    */
+#define BSP_INT_SRC_TINT119         ((IRQn_Type)(535))   /*                                    */
+#define BSP_INT_SRC_TINT120         ((IRQn_Type)(536))   /*                                    */
+#define BSP_INT_SRC_TINT121         ((IRQn_Type)(537))   /*                                    */
+#define BSP_INT_SRC_TINT122         ((IRQn_Type)(538))   /*                                    */
+#define BSP_INT_SRC_TINT123         ((IRQn_Type)(539))   /*                                    */
+#define BSP_INT_SRC_TINT124         ((IRQn_Type)(540))   /*                                    */
+#define BSP_INT_SRC_TINT125         ((IRQn_Type)(541))   /*                                    */
+#define BSP_INT_SRC_TINT126         ((IRQn_Type)(542))   /*                                    */
+#define BSP_INT_SRC_TINT127         ((IRQn_Type)(543))   /*                                    */
+#define BSP_INT_SRC_TINT128         ((IRQn_Type)(544))   /*                                    */
+#define BSP_INT_SRC_TINT129         ((IRQn_Type)(545))   /*                                    */
+#define BSP_INT_SRC_TINT130         ((IRQn_Type)(546))   /*                                    */
+#define BSP_INT_SRC_TINT131         ((IRQn_Type)(547))   /*                                    */
+#define BSP_INT_SRC_TINT132         ((IRQn_Type)(548))   /*                                    */
+#define BSP_INT_SRC_TINT133         ((IRQn_Type)(549))   /*                                    */
+#define BSP_INT_SRC_TINT134         ((IRQn_Type)(550))   /*                                    */
+#define BSP_INT_SRC_TINT135         ((IRQn_Type)(551))   /*                                    */
+#define BSP_INT_SRC_TINT136         ((IRQn_Type)(552))   /*                                    */
+#define BSP_INT_SRC_TINT137         ((IRQn_Type)(553))   /*                                    */
+#define BSP_INT_SRC_TINT138         ((IRQn_Type)(554))   /*                                    */
+#define BSP_INT_SRC_TINT139         ((IRQn_Type)(555))   /*                                    */
+#define BSP_INT_SRC_TINT140         ((IRQn_Type)(556))   /*                                    */
+#define BSP_INT_SRC_TINT141         ((IRQn_Type)(557))   /*                                    */
+#define BSP_INT_SRC_TINT142         ((IRQn_Type)(558))   /*                                    */
+#define BSP_INT_SRC_TINT143         ((IRQn_Type)(559))   /*                                    */
+#define BSP_INT_SRC_TINT144         ((IRQn_Type)(560))   /*                                    */
+#define BSP_INT_SRC_TINT145         ((IRQn_Type)(561))   /*                                    */
+#define BSP_INT_SRC_TINT146         ((IRQn_Type)(562))   /*                                    */
+#define BSP_INT_SRC_TINT147         ((IRQn_Type)(563))   /*                                    */
+#define BSP_INT_SRC_TINT148         ((IRQn_Type)(564))   /*                                    */
+#define BSP_INT_SRC_TINT149         ((IRQn_Type)(565))   /*                                    */
+#define BSP_INT_SRC_TINT150         ((IRQn_Type)(566))   /*                                    */
+#define BSP_INT_SRC_TINT151         ((IRQn_Type)(567))   /*                                    */
+#define BSP_INT_SRC_TINT152         ((IRQn_Type)(568))   /*                                    */
+#define BSP_INT_SRC_TINT153         ((IRQn_Type)(569))   /*                                    */
+#define BSP_INT_SRC_TINT154         ((IRQn_Type)(570))   /*                                    */
+#define BSP_INT_SRC_TINT155         ((IRQn_Type)(571))   /*                                    */
+#define BSP_INT_SRC_TINT156         ((IRQn_Type)(572))   /*                                    */
+#define BSP_INT_SRC_TINT157         ((IRQn_Type)(573))   /*                                    */
+#define BSP_INT_SRC_TINT158         ((IRQn_Type)(574))   /*                                    */
+#define BSP_INT_SRC_TINT159         ((IRQn_Type)(575))   /*                                    */
+#define BSP_INT_SRC_TINT160         ((IRQn_Type)(576))   /*                                    */
+#define BSP_INT_SRC_TINT161         ((IRQn_Type)(577))   /*                                    */
+#define BSP_INT_SRC_TINT162         ((IRQn_Type)(578))   /*                                    */
+#define BSP_INT_SRC_TINT163         ((IRQn_Type)(579))   /*                                    */
+#define BSP_INT_SRC_TINT164         ((IRQn_Type)(580))   /*                                    */
+#define BSP_INT_SRC_TINT165         ((IRQn_Type)(581))   /*                                    */
+#define BSP_INT_SRC_TINT166         ((IRQn_Type)(582))   /*                                    */
+#define BSP_INT_SRC_TINT167         ((IRQn_Type)(583))   /*                                    */
+#define BSP_INT_SRC_TINT168         ((IRQn_Type)(584))   /*                                    */
+#define BSP_INT_SRC_TINT169         ((IRQn_Type)(585))   /*                                    */
+#define BSP_INT_SRC_TINT170         ((IRQn_Type)(586))   /*                                    */
+
+INLINE IRQn_Type  R_CAST_bsp_int_src_t_to_IRQn_Type( bsp_int_src_t const  Value )
+{
+    return  (IRQn_Type) Value;
+}
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "mcu_interrupts.h" */
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* MCU_INTERRUPTS_TYPEDEF_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/platform.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,78 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  platform.h
+* @brief   Header files of FIT BSP.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef PLATFORM_H
+#define PLATFORM_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "Project_Config.h"
+#include "cpu.h"
+#include "locking.h"
+#include "mcu_interrupts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "mcu_interrupts_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* PLATFORM_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/platform_config.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,117 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  platform_config.h
+* @brief   Configuration of FIT BSP.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+
+/* This file is included from "Project_Config.h" */
+
+
+#ifndef PLATFORM_CONFIG_H
+#define PLATFORM_CONFIG_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  BSP_CFG_USER_LOCKING_ENABLED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This value can be changed.
+*    See locking_user.h file.
+*/
+#define  BSP_CFG_USER_LOCKING_ENABLED   0
+
+
+/**
+* @def  BSP_CFG_RTOS_USED
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This value cannot be changed.
+*    This value is 1 in OSPL for RTOS.
+*/
+#define  BSP_CFG_RTOS_USED  1
+
+
+/**
+* @def  BSP_CFG_PARAM_CHECKING_ENABLE
+* @brief  0 or 1
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This value can be changed.
+*/
+#define  BSP_CFG_PARAM_CHECKING_ENABLE  1
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* PLATFORM_CONFIG_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_multi_compiler.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,75 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_multi_compiler.h
+* @brief   Compiler Porting Layer. Functions.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef R_MULTI_COMPILER_H
+#define R_MULTI_COMPILER_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_multi_compiler_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "r_multi_compiler_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "r_multi_compiler_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "r_multi_compiler_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+} /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_MULTI_COMPILER_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_multi_compiler_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,392 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_multi_compiler_typedef.h
+* @brief   Compiler Porting Layer. Data types.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 42 $
+* $Date:: 2014-06-03 16:54:02 +0900#$
+*/
+
+#ifndef R_MULTI_COMPILER_TYPEDEF_H
+#define R_MULTI_COMPILER_TYPEDEF_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  R_OSPL_SECTION_INLINE_VERSION
+* @brief  R_OSPL_SECTION_INLINE_VERSION
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define R_OSPL_SECTION_INLINE_VERSION  4
+
+
+/**
+* @def  R_OSPL_LIST_UP_INLINE_BODY
+* @brief  Define or not define
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* #define  R_OSPL_LIST_UP_INLINE_BODY */
+
+
+/**
+* @def  R_OSPL_MAKE_INLINE_BODY
+* @brief  Define or not define
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* #define  R_OSPL_MAKE_INLINE_BODY */
+
+
+/**
+* @def  INLINE
+* @brief  Inline function
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    "__INLINE" is reserved by compiler.
+*/
+/* ->QAC 1252 : QAC considers that && is not short-circuit evaluation */
+#if defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 199901L  &&  ! defined( __ICCARM__ ) /* For C99 */ \
+&&  ! IS_MBED_USED  ||  defined( __cplusplus )
+/* <-QAC 1252 */
+#if defined( R_OSPL_MAKE_INLINE_BODY )  &&  ! defined( R_OSPL_LIST_UP_INLINE_BODY )
+#define  INLINE  extern inline
+#else
+#define  INLINE  inline
+#endif
+
+/* ->QAC 1252 : QAC considers that && is not short-circuit evaluation */
+#elif defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 199901L  &&  defined( __ICCARM__ ) /* For IAR C99 */
+/* <-QAC 1252 */
+#if defined( R_OSPL_MAKE_INLINE_BODY )
+#define  INLINE
+/* "extern inline" raises a error, if with "@" operator */
+#else
+#define  INLINE  inline  /* Special inline */
+#endif
+
+#elif defined( __CC_ARM )  &&  ! defined( __GNUC__ )  /* For ARMCC not C99, not -gnu */
+#if defined( R_OSPL_MAKE_INLINE_BODY )  &&  ! defined( R_OSPL_LIST_UP_INLINE_BODY )
+#if R_OSPL_LIBRARY_MAKING
+#define  INLINE  static __inline
+#else
+#define  INLINE  extern __inline  /* Special inline */
+#endif
+#else
+#if R_OSPL_LIBRARY_MAKING
+#define  INLINE  static __inline
+#else
+#define  INLINE  extern __inline  /* Special inline */
+#endif
+#endif
+/* Function bodys are in shared "i.<FunctionName>" section */
+
+#elif defined( __GNUC__ )  /* For gcc */
+#if  IS_MBED_USED
+#define  INLINE  static __inline
+#else
+#if defined( R_OSPL_MAKE_INLINE_BODY )  &&  ! defined( R_OSPL_LIST_UP_INLINE_BODY )
+#define  INLINE  __inline__  /* extern inline of C99 */
+#else
+#define  INLINE  extern __inline__  /* inline of C99 */
+#endif
+#endif
+
+#elif defined( _SH )  /* For SH compiler */
+#if defined( R_OSPL_MAKE_INLINE_BODY )  &&  ! defined( R_OSPL_LIST_UP_INLINE_BODY )
+#define  INLINE
+#else
+#define  INLINE  static
+/* "extern" is ignored, if 'C1400 (W) Function "..." in #pragma inline is not expanded' */
+#endif
+/* No inline qualifier */
+/* #ifdef _SH */
+/* #pragma inline <function_name> */
+/* #endif */
+
+#else
+#error
+#endif
+
+
+/**
+* @def  STATIC_INLINE
+* @brief  Static inline in C source file
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    "__STATIC_INLINE" is reserved by compiler.
+*/
+
+#ifndef  __cplusplus
+
+#ifdef __CC_ARM
+#define  STATIC_INLINE  static __inline
+#endif
+
+#ifdef __ICCARM__
+#define  STATIC_INLINE  static inline
+#endif
+
+#if  defined( __GNUC__ )  &&  ! defined( __CC_ARM )
+#define  STATIC_INLINE  static inline
+#endif
+
+#else
+
+#define  STATIC_INLINE  static inline
+
+#endif  /* __cplusplus */
+
+
+/**
+* @def  R_OSPL_SECTION
+* @brief  Names section name to function or varaible
+* @par Parameters
+*    None
+* @return  None.
+*/
+/**
+* @def  R_OSPL_SECTION_FOR_ZERO_INIT
+* @brief  Names section name to zero initialized varaible
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* ->MISRA 19.10 : Cannot ( ) */ /* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#if defined( __CC_ARM )
+#define  R_OSPL_SECTION( SectionName, Declaration ) \
+		__attribute__ ((section (SectionName)))  Declaration
+
+#define  R_OSPL_SECTION_FOR_ZERO_INIT( SectionName, Declaration ) \
+		__attribute__ ((section (SectionName), zero_init))  Declaration
+
+#elif defined( __GNUC__ )  &&  ! defined( __CC_ARM )
+#define  R_OSPL_SECTION( SectionName, Declaration ) \
+		__attribute__ ((section (SectionName)))  Declaration
+
+#define  R_OSPL_SECTION_FOR_ZERO_INIT( SectionName, Declaration ) \
+		__attribute__ ((section (SectionName)))  Declaration
+
+#elif defined( __ICCARM__ )
+#define  R_OSPL_SECTION( SectionName, Declaration ) \
+		Declaration @ SectionName
+
+#define  R_OSPL_SECTION_FOR_ZERO_INIT( SectionName, Declaration ) \
+		Declaration @ SectionName
+
+#elif defined( _SH )  /* For SH compiler */
+#define  R_OSPL_SECTION( SectionName, Declaration ) \
+		Declaration
+/* No section qualifier */
+/* #ifdef _SH */
+/* #pragma section <section_name> */
+/* #endif */
+/*   :   */
+/* <Not extern code> */
+/*   :   */
+/* #ifdef _SH */
+/* #pragma section */
+/* #endif */
+
+#define  R_OSPL_SECTION_FOR_ZERO_INIT( SectionName, Declaration ) \
+		Declaration
+
+#else
+#error
+#endif
+/* <-MISRA 19.10 */ /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @def  R_OSPL_SECTION_FOR_INLINE
+* @brief  Names section name to inline function
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* ->MISRA 19.10 : Cannot ( ) */ /* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#if defined( __CC_ARM )  ||  defined( __GNUC__ )
+#if defined( R_OSPL_LIST_UP_INLINE_BODY )
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+			__attribute__ ((section ("INLINE_BODY")))  Declaration
+#else
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+			__attribute__ ((section (SectionName)))  Declaration
+#endif
+
+#elif defined( __ICCARM__ )
+#if defined( R_OSPL_MAKE_INLINE_BODY )
+#if defined( R_OSPL_LIST_UP_INLINE_BODY )
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+				Declaration @ "INLINE_BODY"
+#else
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+				Declaration @ SectionName
+#endif
+#else
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+			Declaration
+#endif
+
+#elif defined( _SH )  /* For SH compiler */
+#define  R_OSPL_SECTION_FOR_INLINE( SectionName, Declaration ) \
+		Declaration
+/* No section qualifier */
+/* #ifdef _SH */
+/* #pragma section <section_name> */
+/* #endif */
+/*   :   */
+/* <Not extern code> */
+/*   :   */
+/* #ifdef _SH */
+/* #pragma section */
+/* #endif */
+
+#else
+#error
+#endif
+/* <-MISRA 19.10 */ /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @def  R_OSPL_ALIGNMENT
+* @brief  Alignments first addres of global variable
+* @param   ByteCount Value of alignment
+* @param   Declaration_with_Semicolon Declaration of the variable
+* @return  None.
+*/
+/* ->MISRA 19.10 : Cannot ( ) */ /* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#if defined( __CC_ARM )
+#define  R_OSPL_ALIGNMENT( ByteCount, Declaration_with_Semicolon ) \
+		__align( ByteCount )  Declaration_with_Semicolon
+
+#elif defined( __GNUC__ )  &&  ! defined( __CC_ARM )
+#define  R_OSPL_ALIGNMENT( ByteCount, Declaration_with_Semicolon ) \
+		__attribute__((aligned( ByteCount )))  Declaration_with_Semicolon
+
+#elif defined( __ICCARM__ )
+#define  R_OSPL_ALIGNMENT( ByteCount, Declaration_with_Semicolon ) \
+		R_OSPL_ALIGNMENT_SUB( ByteCount, Declaration_with_Semicolon )
+#define  R_OSPL_ALIGNMENT_SUB( ByteCount, Declaration_with_Semicolon ) \
+		_Pragma( "diag_suppress=Pe606" ) \
+		_Pragma( "diag_suppress=Pa060" ) \
+		_Pragma( "diag_suppress=Pe609" ) \
+		R_OSPL_ALIGNMENT_##ByteCount() \
+		Declaration_with_Semicolon \
+		R_OSPL_ALIGNMENT_##0x4()
+/* align 0x4 must be written after ";" */
+
+#define  R_OSPL_ALIGNMENT_0x4()      _Pragma( "data_alignment=0x4" )
+#define  R_OSPL_ALIGNMENT_0x8()      _Pragma( "data_alignment=0x8" )
+#define  R_OSPL_ALIGNMENT_0x10()     _Pragma( "data_alignment=0x10" )
+#define  R_OSPL_ALIGNMENT_0x20()     _Pragma( "data_alignment=0x20" )
+#define  R_OSPL_ALIGNMENT_0x40()     _Pragma( "data_alignment=0x40" )
+#define  R_OSPL_ALIGNMENT_0x80()     _Pragma( "data_alignment=0x80" )
+#define  R_OSPL_ALIGNMENT_0x100()    _Pragma( "data_alignment=0x100" )
+#define  R_OSPL_ALIGNMENT_0x200()    _Pragma( "data_alignment=0x200" )
+#define  R_OSPL_ALIGNMENT_0x400()    _Pragma( "data_alignment=0x400" )
+#define  R_OSPL_ALIGNMENT_0x800()    _Pragma( "data_alignment=0x800" )
+#define  R_OSPL_ALIGNMENT_0x1000()   _Pragma( "data_alignment=0x1000" )
+#define  R_OSPL_ALIGNMENT_0x2000()   _Pragma( "data_alignment=0x2000" )
+#define  R_OSPL_ALIGNMENT_0x4000()   _Pragma( "data_alignment=0x4000" )
+#define  R_OSPL_ALIGNMENT_0x8000()   _Pragma( "data_alignment=0x8000" )
+#define  R_OSPL_ALIGNMENT_0x10000()  _Pragma( "data_alignment=0x10000" )
+#define  R_OSPL_ALIGNMENT_0x20000()  _Pragma( "data_alignment=0x20000" )
+#define  R_OSPL_ALIGNMENT_0x40000()  _Pragma( "data_alignment=0x40000" )
+#define  R_OSPL_ALIGNMENT_0x80000()  _Pragma( "data_alignment=0x80000" )
+#define  R_OSPL_ALIGNMENT_0x100000() _Pragma( "data_alignment=0x100000" )
+
+#define  R_OSPL_ALIGNMENT_4()        _Pragma( "data_alignment=4" )
+#define  R_OSPL_ALIGNMENT_8()        _Pragma( "data_alignment=8" )
+#define  R_OSPL_ALIGNMENT_16()       _Pragma( "data_alignment=16" )
+#define  R_OSPL_ALIGNMENT_32()       _Pragma( "data_alignment=32" )
+#define  R_OSPL_ALIGNMENT_64()       _Pragma( "data_alignment=64" )
+#define  R_OSPL_ALIGNMENT_128()      _Pragma( "data_alignment=128" )
+#define  R_OSPL_ALIGNMENT_256()      _Pragma( "data_alignment=256" )
+#define  R_OSPL_ALIGNMENT_512()      _Pragma( "data_alignment=512" )
+#define  R_OSPL_ALIGNMENT_1024()     _Pragma( "data_alignment=1024" )
+#define  R_OSPL_ALIGNMENT_2048()     _Pragma( "data_alignment=2048" )
+#define  R_OSPL_ALIGNMENT_4096()     _Pragma( "data_alignment=4096" )
+#define  R_OSPL_ALIGNMENT_8192()     _Pragma( "data_alignment=8192" )
+#define  R_OSPL_ALIGNMENT_16384()    _Pragma( "data_alignment=16384" )
+#define  R_OSPL_ALIGNMENT_32768()    _Pragma( "data_alignment=32768" )
+#define  R_OSPL_ALIGNMENT_65536()    _Pragma( "data_alignment=65536" )
+
+#elif defined( _SH )
+#define  R_OSPL_ALIGNMENT( ByteCount, Declaration_with_Semicolon ) \
+		Declaration_with_Semicolon
+/* No alignment qualifier */
+/* Set aligned address by "Map section information" */
+
+#else
+#error
+#endif
+/* <-MISRA 19.10 */ /* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/* Form: C Language Header */
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "r_multi_compiler.h" */
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* End of extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_MULTI_COMPILER_TYPEDEF_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_ospl.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,2040 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl.h
+* @brief   OS Porting Layer. Main Header. Functions.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef R_OSPL_H
+#define R_OSPL_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "Project_Config.h"
+#include "platform.h"
+#include "r_ospl_typedef.h"
+#include "r_multi_compiler_typedef.h"
+#include "locking.h"
+#include "r_static_an_tag.h"
+#include "r_ospl_debug.h"
+#if ! R_OSPL_IS_PREEMPTION
+#include "r_ospl_os_less.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "r_ospl_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "r_ospl_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "r_ospl_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+
+/* Section: Version and initialize */
+/**
+* @brief   Returns version number of OSPL
+*
+* @par Parameters
+*    None
+* @return  Version number of OSPL
+*
+* @par Description
+*    Return value is same as "R_OSPL_VERSION" macro.
+*/
+int32_t   R_OSPL_GetVersion(void);
+
+
+/**
+* @brief   Returns whether the environment is supported preemption
+*
+* @par Parameters
+*    None
+* @return  Whether the environment is RTOS supported preemption
+*
+* @par Description
+*    Return value is same as "R_OSPL_IS_PREEMPTION" macro.
+*/
+bool_t    R_OSPL_IsPreemption(void);
+
+
+/**
+* @brief   Initializes the internal of OSPL
+*
+* @param   NullConfig Specify NULL
+* @return  None
+*
+* @par Description
+*    Initializes internal mutual exclusion objects.
+*    However, "R_OSPL_Initialize" function does not have to be called for
+*    OSPL of "R_OSPL_IS_PREEMPTION = 0".
+*    "E_ACCESS_DENIED" error is raised, when the OSPL API that it is
+*    necessary to call "R_OSPL_Initialize" before calling the API was called.
+*/
+errnum_t  R_OSPL_Initialize( const void *const  NullConfig );
+
+
+/* Section: Standard functions */
+/**
+* @brief   No operation from C++ specification
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    Compatible with __noop (MS C++). But our naming rule is not match.
+*/
+INLINE void  R_NOOP(void) {}
+
+
+/**
+* @brief   Returns element count of the array
+*
+* @param   Array An array
+* @return  Count of specified array's element
+*
+* @par Description
+*    Compatible with _countof (MS C++) and ARRAY_SIZE (Linux).
+*    But our naming rule is not match.
+*
+* @par Example
+*    @code
+*    uint32_t  array[10];
+*    R_COUNT_OF( array )  // = 10
+*    @endcode
+*
+* @par Example
+*    Array argument must not be specified the pointer using like array.
+*    @code
+*    uint32_t   array[10];
+*    func( array );
+*
+*    void  func( uint32_t array[] )  // "array" is a pointer
+*    {
+*        R_COUNT_OF( array )  // NG
+*    }
+*    @endcode
+*/
+/* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#define  R_COUNT_OF( Array )  ( sizeof( Array ) / sizeof( *(Array) ) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/* Section: Error handling and debugging (1) */
+
+
+/**
+* @def  IF
+* @brief  Breaks and transits to error state, if condition expression is not 0
+* @param   Condition Condition expression
+* @return  None
+*
+* @par Example
+*    @code
+*    e= TestFunction(); IF(e){goto fin;}
+*    @endcode
+*
+* @par Description
+*    "IF" is as same as general "if", if "R_OSPL_ERROR_BREAK" macro was
+*    defined to be 0. The following descriptions are available,
+*    if "R_OSPL_ERROR_BREAK" macro was defined to be 1.
+*
+*    "IF" macro supports to find the code raising an error.
+*
+*    If the "if statement" that is frequently seen in guard condition and
+*    after calling functions was changed to "IF" macro, the CPU breaks
+*    at raising an error. Then the status (values of variables) can be
+*    looked immediately and the code (call stack) can be looked. Thus,
+*    debug work grows in efficiency.
+*
+*    "IF" macro promotes recognizing normal code and exceptional code.
+*    Reading speed will grow up by skipping exceptional code.
+*
+*    Call "R_OSPL_SET_BREAK_ERROR_ID" function, if set to break at the code
+*    raising an error.
+*
+*    Whether the state was error state or the error raised count is stored
+*    in the thread local storage. In Release configuration, the variable
+*    of error state and the error raised count is deleted. Manage the error
+*    code using auto variable and so on at out of OSPL.
+*
+*    The error state is resolved by calling "R_OSPL_CLEAR_ERROR" function.
+*    If "R_DEBUG_BREAK_IF_ERROR" macro was called with any error state,
+*    the process breaks at the macro.
+*/
+#if R_OSPL_ERROR_BREAK
+
+/* ->MISRA 19.4 : Abnormal termination. Compliant with C language syntax. */ /* ->SEC M1.8.2 */
+#define  IF( Condition ) \
+		if ( IS( R_OSPL_OnRaisingErrorForMISRA( \
+			IS( (int_fast32_t)( Condition ) ), __FILE__, __LINE__ ) ) )
+/* (int_fast32_t) cast is for QAC warning of implicit cast unsigned to signed */
+/* != 0 is for QAC warning of MISRA 13.2 Advice */
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+
+#else  /* ! R_OSPL_ERROR_BREAK */
+
+/* ->MISRA 19.4 : Abnormal termination. Compliant with C language syntax. */ /* ->SEC M1.8.2 */
+#define  IF  if
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+#endif
+
+
+/**
+* @def  IF_D
+* @brief  It is same as "IF" (for Debug configuration only)
+* @param   Condition Condition expression
+* @return  None
+*
+* @par Description
+*    In Release configuration, the result of condition expression is always "false".
+*    The release configuration is the configuration defined "R_OSPL_NDEBUG".
+*/
+/* ->MISRA 19.4 : Compliant with C language syntax. */ /* ->SEC M1.8.2 */
+/* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#ifndef R_OSPL_NDEBUG
+#define  IF_D( Condition )  IF ( Condition )
+#else
+#define  IF_D( Condition )  if ( false )
+#endif
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+
+
+/**
+* @def  ASSERT_R
+* @brief  Assertion (Programming By Contract)
+* @param   Condition The condition expression expected true
+* @param   goto_fin_Statement The operation doing at condition is false
+* @return  None
+*
+* @par Description
+*    It is possible to write complex sentence divided by ";" in
+*    "goto_fin_Statement" argument.
+*
+*    @par - Case of defined "R_OSPL_ERROR_BREAK" to be 0
+*    If the result of condition expression is 0(false), do "StatementsForError".
+*    If operations did nothing, write "R_NOOP()" at "StatementsForError" argument.
+*
+*    @par - Case of defined "R_OSPL_ERROR_BREAK" to be 1
+*    If the result of condition expression is 0(false), the error state
+*    will become active and the operation of "StatementForError" argument
+*    will be done.
+*/
+#ifndef  __cplusplus
+#define  ASSERT_R( Condition, goto_fin_Statement ) \
+		do{ IF(!(Condition)) { goto_fin_Statement; } } while(0)  /* do-while is CERT standard PRE10-C */
+#else
+#define  ASSERT_R( Condition, goto_fin_Statement ) \
+		{ IF(!(Condition)) { goto_fin_Statement; } }  /* no C5236(I) */
+#endif
+
+
+/**
+* @def  ASSERT_D
+* @brief  Assertion (Programming By Contract) (for Debug configuration only)
+* @param   Condition The condition expression expected true
+* @param   goto_fin_Statement The operation doing at condition is false
+* @return  None
+*
+* @par Description
+*    This does nothing in Release configuration.
+*    Release configuration is the configuration defined "R_OSPL_NDEBUG"
+*    as same as standard library.
+*/
+#ifndef R_OSPL_NDEBUG
+#define  ASSERT_D  ASSERT_R
+#else
+/* ->MISRA 19.7 : Function's argument can not get "goto_fin_Statement" */ /* ->SEC M5.1.3 */
+#define  ASSERT_D( Condition, goto_fin_Statement )  R_NOOP()
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+#endif
+
+
+/**
+* @brief   Sub routine of IF macro
+*
+* @param   Condition Condition in IF macro
+* @param   File File name
+* @param   Line Line number
+* @return  "Condition" argument
+*
+* @par Description
+*    - This part is for compliant to MISRA 2004 - 19.7.
+*/
+bool_t  R_OSPL_OnRaisingErrorForMISRA( bool_t const  Condition,  const char_t *const  File,
+                                       int_t const  Line );
+
+
+/***********************************************************************
+* Class: r_ospl_thread_id_t
+************************************************************************/
+
+/**
+* @brief   Get running thread ID (for OS less and OS-using environment)
+*
+* @par Parameters
+*    None
+* @return  The current running thread ID
+*
+* @par Description
+*    - It is possible to use this function for both OS less and OS - using environment.
+*    For OS less, returns thread ID passed to "R_OSPL_THREAD_SetCurrentId" function.
+*    "NULL" is returned, if in interrupt context.
+*/
+r_ospl_thread_id_t  R_OSPL_THREAD_GetCurrentId(void);
+
+
+/**
+* @brief   Set one or some bits to 1
+*
+* @param   ThreadId The thread ID attached the target event
+* @param   SetFlags The value of bit flags that target bit is 1
+* @return  None
+*
+* @par Description
+*    For OS less, there is the area disabled all interrupts.
+*
+*    - For OS - using environment, the thread waiting in "R_OSPL_EVENT_Wait"
+*    function might wake up soon.
+*
+*    Do nothing, when "ThreadId" = "NULL"
+*/
+void  R_OSPL_EVENT_Set( r_ospl_thread_id_t const  ThreadId, bit_flags32_t const  SetFlags );
+
+
+/**
+* @brief   Set one or some bits to 0
+*
+* @param   ThreadId The thread ID attached the target event
+* @param   ClearFlags1 The value of bit flags that clearing bit is 1
+* @return  None
+*
+* @par Description
+*    It is not necessary to call this function after called "R_OSPL_EVENT_Wait"
+*    function.
+*
+*    The way that all bit flags is cleared is setting "R_OSPL_EVENT_ALL_BITS"
+*    (=0x0000FFFF) at "ClearFlags1" argument.
+*
+*    When other thread was nofied by calling "R_OSPL_EVENT_Set", "R_OSPL_EVENT_Clear"
+*    must not be called from caller (notifier) thread.
+*
+*    For OS less, there is the area disabled all interrupts.
+*
+*    Do nothing, when "ThreadId" = "NULL"
+*/
+void  R_OSPL_EVENT_Clear( r_ospl_thread_id_t const  ThreadId, bit_flags32_t const  ClearFlags1 );
+
+
+/**
+* @brief   Get 16bit flags value
+*
+* @param   ThreadId The thread ID attached the target event
+* @return  The value of 16bit flags
+*
+* @par Description
+*    This API cannot be used in newest specification.
+*
+*    In receiving the event, call "R_OSPL_EVENT_Wait" function instead of
+*    "R_OSPL_EVENT_Get" function or call "R_OSPL_EVENT_Clear" function
+*    passed the NOT operated value of flags got by "R_OSPL_EVENT_Get" function.
+*/
+#if ( ! defined( osCMSIS )  ||  osCMSIS <= 0x10001 ) &&  R_OSPL_VERSION < 85
+bit_flags32_t  R_OSPL_EVENT_Get( r_ospl_thread_id_t const  ThreadId );
+#endif
+
+
+/**
+* @brief   Waits for setting the flags in 16bit and clear received flags
+*
+* @param   WaigingFlags The bit flags set to 1 waiting or "R_OSPL_ANY_FLAG"
+* @param   out_GotFlags NULL is permitted. Output: 16 bit flags or "R_OSPL_TIMEOUT"
+* @param   Timeout_msec Time out (millisecond) or "R_OSPL_INFINITE"
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    Waits in this function until the flags become passed flags pattern
+*    by "R_OSPL_EVENT_Set" function.
+*
+*    Check "r_ospl_async_t::ReturnValue", when the asynchronous operation
+*    was ended.
+*/
+errnum_t  R_OSPL_EVENT_Wait( bit_flags32_t const  WaigingFlags,  bit_flags32_t *const  out_GotFlags,
+                             uint32_t const  Timeout_msec );
+/* Unsigned flag (bit_flags32_t) is for QAC 4130 */
+
+
+/***********************************************************************
+* Class: r_ospl_flag32_t
+************************************************************************/
+
+/**
+* @brief   Clears all flags in 32bit to 0
+*
+* @param   self The value of 32bit flags
+* @return  None
+*
+* @par Description
+*    Operates following operation.
+*    @code
+*    volatile bit_flags32_t  self->flags;
+*    self->flags = 0;
+*    @endcode
+*/
+void  R_OSPL_FLAG32_InitConst( volatile r_ospl_flag32_t *const  self );
+
+
+/**
+* @brief   Set one or some bits to 1
+*
+* @param   self The value of 32bit flags
+* @param   SetFlags The value of bit flags that target bit is 1
+* @return  None
+*
+* @par Description
+*    Operates following operation.
+*    @code
+*    volatile bit_flags32_t  self->Flags;
+*    bit_flags32_t           SetFlags;
+*    self->Flags |= SetFlags;
+*    @endcode
+*    This function is not atomic because "|=" operator is "Read Modify Write" operation.
+*/
+void  R_OSPL_FLAG32_Set( volatile r_ospl_flag32_t *const  self, bit_flags32_t const  SetFlags );
+
+
+/**
+* @brief   Set one or some bits to 0
+*
+* @param   self The value of 32bit flags
+* @param   ClearFlags1 The value of bit flags that clearing bit is 1
+* @return  None
+*
+* @par Description
+*    Operates following operation.
+*    @code
+*    volatile bit_flags32_t  self->Flags;
+*    bit_flags32_t           ClearFlags1;
+*
+*    self->Flags &= ~ClearFlags1;
+*    @endcode
+*
+*    Set "R_OSPL_FLAG32_ALL_BITS", if you wanted to clear all bits.
+*
+*    This function is not atomic because "&=" operator is "Read Modify Write" operation.
+*/
+void  R_OSPL_FLAG32_Clear( volatile r_ospl_flag32_t *const  self, bit_flags32_t const  ClearFlags1 );
+
+
+/**
+* @brief   Get 32bit flags value
+*
+* @param   self The value of 32bit flags
+* @return  The value of 32bit flags
+*
+* @par Description
+*    In receiving the event, call "R_OSPL_FLAG32_GetAndClear" function
+*    instead of "R_OSPL_FLAG32_Get" function or call "R_OSPL_FLAG32_Clear"
+*    function passed the NOT operated value of flags got by "R_OSPL_FLAG32_Get"
+*    function.
+*
+*    @code
+*    Operates following operation.
+*    volatile bit_flags32_t  self->Flags;
+*    bit_flags32_t           return_flags;
+*
+*    return_flags = self->Flags;
+*
+*    return  return_flags;
+*    @endcode
+*/
+bit_flags32_t  R_OSPL_FLAG32_Get( volatile const r_ospl_flag32_t *const  self );
+
+
+/**
+* @brief   Get 32bit flags value
+*
+* @param   self The value of 32bit flags
+* @return  The value of 32bit flags
+*
+* @par Description
+*    Operates following operation.
+*    @code
+*    volatile bit_flags32_t  self->Flags;
+*    bit_flags32_t           return_flags;
+*
+*    return_flags = self->Flags;
+*    self->Flags = 0;
+*
+*    return  return_flags;
+*    @endcode
+*
+*    This function is not atomic because the value might be set before clearing to 0.
+*/
+bit_flags32_t  R_OSPL_FLAG32_GetAndClear( volatile r_ospl_flag32_t *const  self );
+
+
+/***********************************************************************
+* Class: r_ospl_queue_t
+************************************************************************/
+
+/**
+* @brief   Initializes a queue
+*
+* @param   out_self Output: Address of initialized queue object
+* @param   QueueDefine Initial attributes of queue and work area
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    It is not possible to call this function from the library.
+*    This function is called from porting layer of the driver and send
+*    created queue to the driver.
+*
+*    OSPL does not have finalizing function (portabled with CMSIS).
+*    An object specified "QueueDefine" argument can be specified to the
+*    create function 1 times only. Some OS does not have this limitation.
+*
+*    The address of a variable as "r_ospl_queue_t*" type is set at
+*    "out_self" argument.
+*    Internal variables of the queue are stored in the variable specified
+*    with "QueueDefine" argument.
+*/
+errnum_t  R_OSPL_QUEUE_Create( r_ospl_queue_t **out_self, r_ospl_queue_def_t *QueueDefine );
+
+
+/**
+* @brief   Gets status of the queue
+*
+* @param   self A queue object
+* @param   out_Status Output: Pointer to the status structure
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    Got status are the information at calling moment.
+*    If ohter threads were run, the status will be changed.
+*    See "R_DRIVER_GetAsyncStatus" function about pointer type of
+*    "out_Status" argument
+*/
+errnum_t  R_OSPL_QUEUE_GetStatus( r_ospl_queue_t *self,  const r_ospl_queue_status_t **out_Status );
+
+
+/**
+* @brief   Allocates an element from the queue object
+*
+* @param   self A queue object
+* @param   out_Address Output: Address of allocated element
+* @param   Timeout_msec Timeout (msec) or R_OSPL_INFINITE
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    An error will be raised, if "Timeout_msec != 0" in interrupt context.
+*    It becomes "*out_Address = NULL", when it was timeout and
+*    "Timeout_msec = 0".
+*    E_TIME_OUT error is raised, when it was timeout and "Timeout_msec != 0".
+*/
+errnum_t  R_OSPL_QUEUE_Allocate( r_ospl_queue_t *self,  void *out_Address,  uint32_t Timeout_msec );
+
+
+/**
+* @brief   Sends the element to the queue
+*
+* @param   self A queue object
+* @param   Address Address of element to put
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    It is correct, even if other thread put to the queue or get from
+*    the queue from calling "R_OSPL_QUEUE_Allocate" to calling
+*    "R_OSPL_QUEUE_Put".
+*
+*    The message put to the queue by this function receives the thread
+*    calling "R_OSPL_QUEUE_Get" function.
+*/
+errnum_t  R_OSPL_QUEUE_Put( r_ospl_queue_t *self,  void *Address );
+
+
+/**
+* @brief   Receives the element from the queue
+*
+* @param   self A queue object
+* @param   out_Address Output: Address of received element
+* @param   Timeout_msec Timeout (msec) or R_OSPL_INFINITE
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    Call "R_OSPL_QUEUE_Free" function after finishing to access to
+*    the element. Don't access the memory area of the element after
+*    calling "R_OSPL_QUEUE_Free".
+*
+*    "E_NOT_THREAD" error is raised, if "Timeout_msec = 0" was specified
+*    from interrupt context. It is not possible to wait for put data to
+*    the queue in interrupt context.
+*
+*    "*out_Address" is NULL and any errors are not raised, if it becomed
+*    to timeout and "Timeout_msec = 0". "E_TIME_OUT" is raised,
+*    if "Timeout_msec != 0".
+*
+*    Specify "Timeout_msec = 0", call the following functions by the following
+*    order and use an event for preventing to block to receive other events
+*    by the thread having waited for the queue.
+*
+*    Sending Side
+*    - R_OSPL_QUEUE_Allocate
+*    - R_OSPL_QUEUE_Put
+*    - R_OSPL_EVENT_Set
+*
+*    Receiving Side
+*    - R_OSPL_EVENT_Wait
+*    - R_OSPL_QUEUE_Get
+*    - R_OSPL_QUEUE_Free
+*
+*    In OS less environment, "R_OSPL_QUEUE_Get" supports pseudo multi
+*    threading. See "R_OSPL_THREAD_GetIsWaiting" function.
+*/
+errnum_t  R_OSPL_QUEUE_Get( r_ospl_queue_t *self,  void *out_Address,  uint32_t Timeout_msec );
+
+
+/**
+* @brief   Releases the element to the queue object
+*
+* @param   self A queue object
+* @param   Address Address of received element
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    It is correct, even if other thread put to the queue or get from
+*    the queue from calling "R_OSPL_QUEUE_Get" to calling "R_OSPL_QUEUE_Free".
+*/
+errnum_t  R_OSPL_QUEUE_Free( r_ospl_queue_t *self,  void *Address );
+
+
+/**
+* @brief   Print status of the queue object
+*
+* @param   self A queue object
+* @return  Error code.  If there is no error, the return value is 0
+*/
+#ifndef  R_OSPL_NDEBUG
+errnum_t  R_OSPL_QUEUE_Print( r_ospl_queue_t *self );
+#endif
+
+
+/***********************************************************************
+* Class: r_ospl_async_t
+************************************************************************/
+
+/**
+* @brief   CopyExceptAThread
+*
+* @param   Source Source
+* @param   Destination Destination
+* @return  None
+*/
+void  R_OSPL_ASYNC_CopyExceptAThread( const r_ospl_async_t *const  Source,
+                                      r_ospl_async_t *const  Destination );
+
+
+/***********************************************************************
+* Class: r_ospl_caller_t
+************************************************************************/
+
+/**
+* @brief   Calls the interrupt callback function. It is called from OS porting layer in the driver
+*
+* @param   self The internal parameters about interrupt operations
+* @param   InterruptSource The source of the interrupt
+* @return  None
+*/
+void  R_OSPL_CallInterruptCallback( const r_ospl_caller_t *const  self,
+                                    const r_ospl_interrupt_t *const  InterruptSource );
+
+
+/**
+* @brief   Initialize <r_ospl_caller_t>.
+*
+* @param   self The internal parameters about interrupt operations
+* @param   Async <r_ospl_async_t>
+* @return  None
+*/
+void  R_OSPL_CALLER_Initialize( r_ospl_caller_t *const  self,  r_ospl_async_t *const  Async,
+                                volatile void *const  PointerToState,  int_t const  StateValueOfOnInterrupting,
+                                void *const  I_Lock, const r_ospl_i_lock_vtable_t *const  I_LockVTable );
+
+
+/**
+* @brief   GetRootChannelNum.
+*
+* @param   self The internal parameters about interrupt operations
+* @return  RootChannelNum
+*/
+INLINE int_fast32_t  R_OSPL_CALLER_GetRootChannelNum( const r_ospl_caller_t *const  self );
+
+
+/* Section: Interrupt */
+/**
+* @brief   Interrupt callback function for unregisterd interrupt.
+*
+* @param   int_sense (See INTC driver)
+* @return  None
+*/
+void  R_OSPL_OnInterruptForUnregistered( uint32_t const  int_sense );
+
+
+/**
+* @brief   Releases all disabled interrupts
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    Driver user should not call this function.
+*    Call this function at the end of area of all interrupts disabled.
+*    Do not release, if all interrupts was already disabled by caller function.
+*    This function does not release disabled NMI.
+*/
+void  R_OSPL_EnableAllInterrupt(void);
+
+
+/**
+* @brief   Disables all interrupts
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    Driver user should not call this function.
+*    Call this function at begin of area of all interrupts disabled.
+*    This function does not disable NMI.
+*
+* @par Example
+*    @code
+*    void  Func()
+*    {
+*        bool_t  was_all_enabled = false;
+*
+*        was_all_enabled = R_OSPL_DisableAllInterrupt();
+*
+*        // All interrupt disabled
+*
+*        if ( was_all_enabled )
+*            { R_OSPL_EnableAllInterrupt(); }
+*    }
+*    @endcode
+*/
+bool_t    R_OSPL_DisableAllInterrupt(void);
+
+
+/**
+* @brief   Sets the priority of the interrupt line.
+*
+* @param   IRQ_Num Interrupt request number
+* @param   Priority Priority. The less the prior.
+* @return  Error code.  If there is no error, the return value is 0
+*/
+errnum_t  R_OSPL_SetInterruptPriority( bsp_int_src_t const  IRQ_Num, int_fast32_t const  Priority );
+
+
+/* Section: Locking channel */
+/**
+* @brief   Locks by channel number.
+*
+* @param   ChannelNum Locking channel number or "R_OSPL_UNLOCKED_CHANNEL"
+* @param   out_ChannelNum Output: Locked channel number, (in) NULL is permitted
+* @param   HardwareIndexMin Hardware index of channel number = 0
+* @param   HardwareIndexMax Hardware index of max channel number
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    This function is called from the internal of "R_DRIVER_Initialize"
+*    function or "R_DRIVER_LockChannel" function.
+*    This function calls "R_BSP_HardwareLock".
+*/
+errnum_t  R_OSPL_LockChannel( int_fast32_t ChannelNum, int_fast32_t *out_ChannelNum,
+                              mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax );
+
+
+/**
+* @brief   Unlocks by channel number.
+*
+* @param   ChannelNum Channel number
+* @param   e Raising error code, If there is no error, 0
+* @param   HardwareIndexMin Hardware index of channel number = 0
+* @param   HardwareIndexMax Hardware index of max channel number
+* @return  Error code.  If there is no error, the return value is 0
+*
+* @par Description
+*    This function is called from the internal of "R_DRIVER_Finalize"
+*    function or "R_DRIVER_UnlockChannel" function.
+*    This function calls "R_BSP_HardwareUnlock".
+*/
+errnum_t  R_OSPL_UnlockChannel( int_fast32_t ChannelNum,  errnum_t  e,
+                                mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax );
+
+
+/***********************************************************************
+* Class: r_ospl_c_lock_t
+************************************************************************/
+
+/**
+* @brief   Initializes the C-lock object
+*
+* @param   self C-lock object
+* @return  None
+*
+* @par Description
+*    If *self is global variable or static variable initialized 0,
+*    this function does not have to be called.
+*/
+void      R_OSPL_C_LOCK_InitConst( r_ospl_c_lock_t *const  self );
+
+
+/**
+* @brief   Locks the target, if lockable state.
+*
+* @param   self C-lock object
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    Even if lock owner called this function, if lock object was already
+*    locked, E_ACCESS_DENIED error is raised.
+*
+*    "R_OSPL_C_LOCK_Lock" does not do exclusive control.
+*/
+errnum_t  R_OSPL_C_LOCK_Lock( r_ospl_c_lock_t *const  self );
+
+
+/**
+* @brief   Unlocks the target.
+*
+* @param   self C-lock object
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    If this function was called with unlocked object, this function
+*    does nothing and raises "E_ACCESS_DENIED" error.
+*
+*    If self == NULL, this function does nothing and raises no error.
+*    E_NOT_THREAD error is raised, if this function was called from the
+*    interrupt context.
+*
+*    - I - lock does not do in this function.
+*
+*    "R_OSPL_C_LOCK_Unlock" does not do exclusive control.
+*/
+errnum_t  R_OSPL_C_LOCK_Unlock( r_ospl_c_lock_t *const  self );
+
+
+/***********************************************************************
+* Class: r_ospl_i_lock_vtable_t
+************************************************************************/
+
+/**
+* @brief   Do nothing. This is registered to r_ospl_i_lock_vtable_t::Lock.
+*
+* @param   self_ I-lock object
+* @return  false
+*/
+bool_t    R_OSPL_I_LOCK_LockStub( void *const  self_ );
+
+
+/**
+* @brief   Do nothing. This is registered to r_ospl_i_lock_vtable_t::Unlock.
+*
+* @param   self_ I-lock object
+* @return  None
+*/
+void      R_OSPL_I_LOCK_UnlockStub( void *const  self_ );
+
+
+/**
+* @brief   Do nothing. This is registered to r_ospl_i_lock_vtable_t::RequestFinalize.
+*
+* @param   self_ I-lock object
+* @return  None
+*/
+void      R_OSPL_I_LOCK_RequestFinalizeStub( void *const  self_ );
+
+
+/**
+* @brief   Get root channel number
+*
+* @param   self <r_ospl_caller_t> object
+* @return  Root channel number
+*/
+INLINE int_fast32_t  R_OSPL_CALLER_GetRootChannelNum( const r_ospl_caller_t *const  self )
+{
+    int_fast32_t  root_channel_num;
+
+    IF_DQ( self == NULL ) {
+        root_channel_num = 0;
+    }
+    else {
+        root_channel_num = self->I_LockVTable->GetRootChannelNum( self->I_Lock );
+    }
+
+    return  root_channel_num;
+}
+
+
+/* Section: Memory Operation */
+/**
+* @brief   Flushes cache memory
+*
+* @param   FlushType The operation of flush
+* @return  None
+*
+* @par Description
+*    Call the function of the driver after flushing input output buffer
+*    in the cache memory, If the data area accessing by the hardware is
+*    on cache and the driver did not manage the cache memory.
+*    Whether the driver manages the cache memory is depend on the driver
+*    specification.
+*/
+void  R_OSPL_MEMORY_Flush( r_ospl_flush_t const  FlushType );
+
+
+/**
+* @brief   Flushes cache memory with the range of virtual address.
+*
+* @param   FlushType The operation of flush
+* @return  None
+*
+* @par Description
+*    Align "StartAddress" argument and "Length" argument to cache line size.
+*    If not aligned, E_OTHERS error is raised.
+*    Refer to : R_OSPL_MEMORY_GetSpecification
+*
+*    If the data area written by the hardware and read from CPU was in cache
+*    rea, when the hardware started without invalidate
+*    ("R_OSPL_FLUSH_WRITEBACK_INVALIDATE" or "R_OSPL_FLUSH_INVALIDATE"),
+*    invalidate the data area and read it after finished to write by hardware.
+*    (If the driver does not manage the cache memory.)
+*/
+errnum_t  R_OSPL_MEMORY_RangeFlush( r_ospl_flush_t const  FlushType,
+                                    const void *const  StartAddress,  size_t const  Length );
+
+
+/**
+* @brief   Gets the specification about memory and cache memory.
+*
+* @param   out_MemorySpec The specification about memory and cache memory
+* @return  None
+*/
+void      R_OSPL_MEMORY_GetSpecification( r_ospl_memory_spec_t *const  out_MemorySpec );
+
+
+/**
+* @brief   Set a memory barrier.
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    In ARM, This function calls DSB assembler operation.
+*    This effects to L1 cache only.
+*/
+void      R_OSPL_MEMORY_Barrier(void);
+
+
+/**
+* @brief   Set a instruction barrier.
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    In ARM, This function calls ISB assembler operation.
+*/
+void      R_OSPL_InstructionSyncBarrier(void);
+
+
+/**
+* @brief   Changes to physical address
+*
+* @param   Address Virtual address
+* @param   out_PhysicalAddress Output: Physical address
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    This function must be modified by MMU setting.
+*/
+errnum_t  R_OSPL_ToPhysicalAddress( const volatile void *const  Address, uintptr_t *const  out_PhysicalAddress );
+
+
+/**
+* @brief   Changes to the address in the L1 cache area
+*
+* @param   Address Virtual address
+* @param   out_CachedAddress Output: Virtual address for cached area
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    This function must be modified by MMU setting.
+*    If "E_ACCESS_DENIED" error was raised, you may know the variable by
+*    looking at value of "Address" argument and map file.
+*/
+errnum_t  R_OSPL_ToCachedAddress( const volatile void *const  Address, void *const  out_CachedAddress );
+
+
+/**
+* @brief   Changes to the address in the L1 uncached area
+*
+* @param   Address Virtual address
+* @param   out_UncachedAddress Output: Virtual address for uncached area
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    This function must be modified by MMU setting.
+*    If "E_ACCESS_DENIED" error was raised, you may know the variable by
+*    looking at value of "Address" argument and map file.
+*/
+errnum_t  R_OSPL_ToUncachedAddress( const volatile void *const  Address, void *const  out_UncachedAddress );
+
+
+/**
+* @brief   Gets the level of cache for flushing the memory indicated by the address.
+*
+* @param   Address The address in flushing memory
+* @param   out_Level Output: 0=Not need to flush, 1=L1 cache only, 2=both of L1 and L2 cache
+* @return  Error code.  If there is no error, the return value is 0.
+*/
+errnum_t  R_OSPL_MEMORY_GetLevelOfFlush( const void *Address, int_fast32_t *out_Level );
+
+
+/**
+* @brief   Get 2nd cache attribute of AXI bus for peripheral (not CPU) from physical address.
+*
+* @param   PhysicalAddress The physical address in the memory area
+* @param   out_CacheAttribute Output: Cache_attribute, AWCACHE[3:0], ARCACHE[3:0]
+* @return  Error code.  If there is no error, the return value is 0.
+*/
+errnum_t  R_OSPL_AXI_Get2ndCacheAttribute( uintptr_t const  PhysicalAddress,
+        r_ospl_axi_cache_attribute_t *const  out_CacheAttribute );
+
+
+/**
+* @brief   Gets protection attribute of AXI bus from the address
+*
+* @param   PhysicalAddress The physical address in the memory area
+* @param   out_CacheAttribute Output: The protection attribute of AXI bus AWPROT[2:0], ARPROT[2:0]
+* @return  Error code.  If there is no error, the return value is 0.
+*/
+errnum_t  R_OSPL_AXI_GetProtection( uintptr_t const  physical_address,
+                                    r_ospl_axi_protection_t *const  out_protection );
+
+
+/* Section: Timer */
+/**
+* @brief   Waits for a while until passed time
+*
+* @param   DelayTime_msec Time of waiting (millisecond)
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    Maximum value is "R_OSPL_MAX_TIME_OUT" (=65533).
+*/
+errnum_t  R_OSPL_Delay( uint32_t const  DelayTime_msec );
+
+
+/**
+* @brief   Set up the free running timer
+*
+* @param   out_Specification NULL is permitted. Output: The precision of the free run timer
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    The free running timer does not stop.
+*
+*    If the counter of the free running timer was overflow, the counter returns to 0.
+*    Even in interrupt handler, the counter does count up.
+*    OSPL free running timer does not use any interrupt.
+*
+*    Using timer can be selected by "R_OSPL_FTIMER_IS" macro.
+*
+*    If the free running timer was already set up, this function does not set up it,
+*    outputs to "out_Specification" argument and does not raise any error.
+*
+*    When OSPL API function with timeout or "R_OSPL_Delay" function was called,
+*    "R_OSPL_FTIMER_InitializeIfNot" function is callbacked from these functions.
+*
+*    There is all interrupt disabled area inside.
+*/
+errnum_t  R_OSPL_FTIMER_InitializeIfNot(  r_ospl_ftimer_spec_t *const  out_Specification );
+
+
+/**
+* @brief   Gets the specification of free running timer.
+*
+* @param   out_Specification Output: The precision of the free run timer
+* @return  None
+*/
+void      R_OSPL_FTIMER_GetSpecification( r_ospl_ftimer_spec_t *const  out_Specification );
+
+
+/**
+* @brief   Get current time of free running timer.
+*
+* @par Parameters
+*    None
+* @return  The current clock count of free run timer
+*
+* @par Description
+*    Call "R_OSPL_FTIMER_InitializeIfNot" function before calling this function.
+*    Call "R_OSPL_FTIMER_IsPast" function, when it is determined whether time passed.
+*
+* @par Example
+*    @code
+*    errnum_t              e;
+*    r_ospl_ftimer_spec_t  ts;
+*    uint32_t              start;
+*    uint32_t              end;
+*
+*    e= R_OSPL_FTIMER_InitializeIfNot( &ts ); IF(e){goto fin;}
+*    start = R_OSPL_FTIMER_Get();
+*
+*    // The section of measuring
+*
+*    end = R_OSPL_FTIMER_Get();
+*    printf( "%d msec\n", R_OSPL_FTIMER_CountToTime(
+*            &ts, end - start ) );
+*    @endcode
+*/
+uint32_t  R_OSPL_FTIMER_Get(void);
+
+
+/**
+* @brief   Returns whether specified time was passed
+*
+* @param   ts Precision of the free running timer
+* @param   Now Count of current time
+* @param   TargetTime Count of target time
+* @param   out_IsPast Output: Whether the target time was past or not
+* @return  Error code.  If there is no error, the return value is 0.
+*/
+errnum_t  R_OSPL_FTIMER_IsPast( const r_ospl_ftimer_spec_t *const  ts,
+                                uint32_t const  Now,  uint32_t const  TargetTime,  bool_t *const  out_IsPast );
+
+
+/**
+* @brief   Change from mili-second unit to free running timer unit
+*
+* @param   ts Precision of the free running timer
+* @param   msec The value of mili-second unit
+* @return  The value of free running timer unit
+*
+* @par Description
+*    The fractional part is been round up. (For waiting time must be more
+*    than specified time.)
+*
+*    This function calculates like the following formula.
+*    @code
+*    ( msec * ts->msec_Denominator + ts->msec_Numerator - 1 ) / ts->msec_Numerator
+*    @endcode
+*
+*    - Attention: If "ts - >msec_Denominator" was more than "ts->msec_Numerator",
+*    take care of overflow.
+*/
+INLINE uint32_t  R_OSPL_FTIMER_TimeToCount( const r_ospl_ftimer_spec_t *const  ts,
+        uint32_t const  msec )
+{
+    uint32_t  count;
+
+    IF_DQ( ts == NULL ) {
+        count = 0;
+    }
+    else {
+        count = ( ((msec * ts->msec_Denominator) + ts->msec_Numerator) - 1u ) / ts->msec_Numerator;
+    }
+    return  count;
+}
+
+
+/**
+* @brief   Change from free running timer unit to mili-second unit
+*
+* @param   ts Precision of the free running timer
+* @param   Count The value of free running timer unit
+* @return  The value of mili-second unit
+*
+* @par Description
+*    The fractional part is been round down. (Because overflow does not
+*    occur, when "Count = r_ospl_ftimer_spec_t::MaxCount" )
+*
+*    This function calculates like the following formula.
+*    @code
+*    ( Count * ts->msec_Numerator ) / ts->msec_Denominator
+*    @endcode
+*/
+INLINE uint32_t  R_OSPL_FTIMER_CountToTime( const r_ospl_ftimer_spec_t *const  ts,
+        uint32_t const  Count )
+{
+    uint32_t  time;
+
+    IF_DQ( ts == NULL ) {
+        time = 0;
+    }
+    else {
+        time = ( Count * ts->msec_Numerator ) / ts->msec_Denominator;
+    }
+    return  time;
+}
+
+
+/***********************************************************************
+* Class: r_ospl_table_t
+************************************************************************/
+
+/**
+* @brief   Initializes an index table
+*
+* @param   self Index table object
+* @param   Area First address of the index table
+* @param   AreaByteSize Size of the index table. See <R_OSPL_TABLE_SIZE>
+* @param   Is_T_Lock Whether to call <R_OSPL_Start_T_Lock>
+* @return  None
+*/
+void  R_OSPL_TABLE_InitConst( r_ospl_table_t *const  self,
+                              void *const  Area, size_t const  AreaByteSize, bool_t const  Is_T_Lock );
+
+
+/**
+* @brief   Returns index from related key
+*
+* @param   self Index table object
+* @param   Key Key number
+* @param   out_Index Output: Related index
+* @param   TypeOfIfNot Behavior when key was not registerd. See <r_ospl_if_not_t>
+* @return  Error code.  If there is no error, the return value is 0.
+*/
+errnum_t  R_OSPL_TABLE_GetIndex( r_ospl_table_t *const  self, const void *const  Key,
+                                 int_fast32_t *const  out_Index,  r_ospl_if_not_t const  TypeOfIfNot );
+
+
+/**
+* @brief   Separates relationship of specified key and related index
+*
+* @param   self Index table object
+* @param   Key Key number
+* @return  None
+*
+* @par Description
+*    Error is not raised, even if specified key was already separated.
+*/
+void  R_OSPL_TABLE_Free( r_ospl_table_t *const  self, const void *const  Key );
+
+
+/**
+* @brief   Print status of specified index table object (for debug)
+*
+* @param   self Index table object
+* @return  None
+*/
+#if R_OSPL_DEBUG_TOOL
+void  R_OSPL_TABLE_Print( r_ospl_table_t *const  self );
+#endif
+
+
+/* Section: Bit flags */
+/**
+* @brief   Evaluate whether any passed bits are 1 or not
+*
+* @param   Variable The value of target bit flags
+* @param   ConstValue The value that investigating bits are 1
+* @return  Whether the any passed bit are 1
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_BIT_SET( Variable, ConstValue ) \
+	( BIT_And_Sub( Variable, ConstValue ) != 0u )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Evaluate whether any passed bits are 1 or not
+*
+* @param   Variable The value of target bit flags
+* @param   OrConstValue The value that investigating bits are 1
+* @return  Whether the any passed bit are 1
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_ANY_BITS_SET( Variable, OrConstValue ) \
+	( BIT_And_Sub( Variable, OrConstValue ) != 0u )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Evaluate whether all passed bits are 1 or not
+*
+* @param   Variable The value of target bit flags
+* @param   OrConstValue The value that investigating bits are 1
+* @return  Whether the all passed bit are 1
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_ALL_BITS_SET( Variable, OrConstValue ) \
+	( BIT_And_Sub( Variable, OrConstValue ) == (OrConstValue) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Evaluate whether the passed bit is 0 or not
+*
+* @param   Variable The value of target bit flags
+* @param   ConstValue The value that investigating bit is 1
+* @return  Whether the passed bit is 0
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_BIT_NOT_SET( Variable, ConstValue ) \
+	( BIT_And_Sub( Variable, ConstValue ) == 0u )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Evaluate whether any passed bits are 0 or not
+*
+* @param   Variable The value of target bit flags
+* @param   OrConstValue The value that investigating bits are 1
+* @return  Whether the any passed bit are 0
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_ANY_BITS_NOT_SET( Variable, OrConstValue ) \
+	( BIT_And_Sub( Variable, OrConstValue ) != (OrConstValue) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Evaluate whether all passed bits are 0 or not
+*
+* @param   Variable The value of target bit flags
+* @param   OrConstValue The value that investigating bits are 1
+* @return  Whether the all passed bit are 0
+*/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#define  IS_ALL_BITS_NOT_SET( Variable, OrConstValue ) \
+	( BIT_And_Sub( Variable, OrConstValue ) == 0u )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @brief   Sub routine of bitwise operation
+*
+* @param   Variable The value of target bit flags
+* @param   ConstValue The value that investigating bits are 1
+* @return  Whether the all passed bit are 0
+*
+* @par Description
+*    - This part is for compliant to MISRA 2004 - 19.7.
+*/
+INLINE uint_fast32_t  BIT_And_Sub( bit_flags_fast32_t const  Variable,
+                                   bit_flags_fast32_t const  ConstValue )
+{
+    return  ((Variable) & (ConstValue));
+}
+
+
+/***********************************************************************
+* About: IS_BIT_SET__Warning
+*
+* - This is for QAC-3344 warning : MISRA 13.2 Advice : Tests of a value against
+*   zero should be made explicit, unless the operand is effectively Boolean.
+* - This is for QAC-1253 warning : SEC M1.2.2 : A "U" suffix shall be applied
+*   to all constants of unsigned type.
+************************************************************************/
+
+
+/* Section: Error handling and debugging (2) */
+/**
+* @brief   Breaks here
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    Does break by calling "R_DebugBreak" function.
+*    This macro is not influenced the setting of "R_OSPL_ERROR_BREAK" macro.
+*/
+#define  R_DEBUG_BREAK()  R_DebugBreak(__FILE__,__LINE__)
+
+
+/**
+* @brief   The function callbacked from OSPL for breaking
+*
+* @param   Variable The value of target bit flags
+* @param   ConstValue The value that investigating bits are 1
+* @return  Whether the all passed bit are 0
+*
+* @par Description
+*    Set a break point at this function.
+*    In Release configuration, "File = NULL, Line = 0".
+*    If "File = NULL", "Line" argument is error code.
+*    This function can be customized by application developer.
+*/
+void  R_DebugBreak( const char_t *const  File,  int_fast32_t const  Line );
+
+
+/**
+* @brief   Breaks here, if it is error state
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro was defined
+*    to be 0. The following descriptions are available, if "R_OSPL_ERROR_BREAK"
+*    macro was defined to be 1.
+*
+*    Checks the error state of the current thread.
+*    Call this macro from the last of each thread.
+*    Does break by calling "R_DebugBreak" function.
+*
+*    If an error was raised, this function calls "printf" with following message.
+*    Set "error_ID" to "R_OSPL_SET_BREAK_ERROR_ID"
+*    @code
+*    <ERROR error_ID="0x1" file="../src/api.c(336)"/>
+*    @endcode
+*/
+#if R_OSPL_ERROR_BREAK
+#define  R_DEBUG_BREAK_IF_ERROR()  R_OSPL_DebugBreakIfError(__FILE__,__LINE__)
+void  R_OSPL_DebugBreakIfError( const char_t *const  File,  int_fast32_t const  Line );
+#else
+INLINE void  R_DEBUG_BREAK_IF_ERROR(void) {}
+#endif
+
+
+/**
+* @brief   Raises the error of system unrecoverable
+*
+* @param   e Error code
+* @return  None
+*
+* @par Description
+*    The error of system unrecoverable is the error of impossible to
+*    - self - recover by process or main system. Example, the heap area was
+*    broken or there are not any responses from hardware. This error can
+*    be recoverable by OS or the system controller(e.g. Software reset)
+*
+*    Example, when an error of recovery process was raised,
+*    "R_OSPL_RaiseUnrecoverable" function must be called.
+*
+*    "R_OSPL_RaiseUnrecoverable" function can be customized by the
+*    application. By default, it calls "R_DebugBreak" function and falls
+*    into the infinite loop.
+*/
+void  R_OSPL_RaiseUnrecoverable( errnum_t const  e );
+
+
+/**
+* @brief   Merge the error code raised in the finalizing operation
+*
+* @param   CurrentError Current error code
+* @param   AppendError New append error code
+* @return  Merged error code
+*
+* @par Description
+*    When the state was error state, if other new error was raised,
+*    new error code is ignored.
+*    - If "CurrentError != 0", this function returns "CurrentError" argument.
+*    - If "CurrentError == 0", this function returns "AppendError" argument.
+*
+*    This function can be modify by user.
+*
+* @par Example
+*    @code
+*    ee= Sample();
+*    e= R_OSPL_MergeErrNum( e, ee );
+*    return  e;
+*    @endcode
+*/
+INLINE errnum_t  R_OSPL_MergeErrNum( errnum_t const  CurrentError,  errnum_t const  AppendError )
+{
+    errnum_t  e;
+
+    if ( CurrentError != 0 ) {
+        e = CurrentError;
+    } else {
+        e = AppendError;
+    }
+    return  e;
+}
+
+
+/**
+* @brief   Sets an error code to TLS (Thread Local Storage).
+*
+* @param   e Raising error code
+* @return  None
+*
+* @par Description
+*    Usually error code is returned. If API function cannot return any
+*    error code, API function can have the specification of setting error
+*    code by "R_OSPL_SetErrNum".
+*
+*    There is this function, if "R_OSPL_TLS_ERROR_CODE" macro was defined
+*    to be 1.
+*    This function does nothing, if any error code was stored already in TLS.
+*    The state does not change to error state, if "R_OSPL_SetErrNum" function
+*    was called only. See "R_OSPL_GET_ERROR_ID".
+*/
+#if R_OSPL_TLS_ERROR_CODE
+void  R_OSPL_SetErrNum( errnum_t const  e );
+#endif
+
+
+/**
+* @brief   Returns the error code from TLS (Thread Local Storage).
+*
+* @par Parameters
+*    None
+* @return  Error code
+*
+* @par Description
+*    Usually error code is returned. If API function cannot return any
+*    error code, API function may have the specification of getting error
+*    code by "R_OSPL_GetErrNum".
+*
+*    There is this function, if "R_OSPL_TLS_ERROR_CODE" macro was defined
+*    to be 1. This function returns 0 after called "R_OSPL_CLEAR_ERROR"
+*    function.
+*/
+#if R_OSPL_TLS_ERROR_CODE
+errnum_t  R_OSPL_GetErrNum(void);
+#endif
+
+
+/**
+* @brief   Clears the error state
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro and
+*    "R_OSPL_TLS_ERROR_CODE" macro were defined to be 0. The following
+*    descriptions are available, if "R_OSPL_ERROR_BREAK" macro was
+*    defined to be 1.
+*
+*    Whether the state is the error state is stored in thread local
+*    storage. "R_OSPL_GetErrNum" function returns 0 after called this
+*    function.
+*
+*    If the error state was not cleared, the following descriptions were caused.
+*    - Breaks at "R_DEBUG_BREAK_IF_ERROR" macro
+*    - "R_OSPL_SET_BREAK_ERROR_ID" function behaves not expected behavior
+*       because the count of error is not counted up.
+*/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+void  R_OSPL_CLEAR_ERROR(void);
+#else
+INLINE void  R_OSPL_CLEAR_ERROR(void) {}  /* QAC 3138 */
+#endif
+
+
+/**
+* @brief   Returns the number of current error
+*
+* @par Parameters
+*    None
+* @return  The number of current error
+*
+* @par Description
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro was defined
+*    to be 0. The following descriptions are available, if "R_OSPL_ERROR_BREAK"
+*    macro was defined to be 1.
+*
+*    This function returns 0, if any errors were not raised.
+*
+*    This function returns 1, if first error was raised.
+*
+*    After that, this function returns 2, if second error was raised after
+*    calling "R_OSPL_CLEAR_ERROR" function.
+*    This function does not return 0 after that the error was cleared by
+*    calling "R_OSPL_CLEAR_ERROR".
+*    The number of current error is running number in the whole of system
+*    (all threads).
+*
+*    Error is raised by following macros.
+*    @code
+*    IF, IF_D, ASSERT_R, ASSERT_D
+*    @endcode
+*    The process breaks at a moment of error raised, if the number of current
+*    error was set to "R_OSPL_SET_BREAK_ERROR_ID" macro.
+*/
+#if R_OSPL_ERROR_BREAK
+int_fast32_t  R_OSPL_GET_ERROR_ID(void);
+#else
+INLINE int_fast32_t  R_OSPL_GET_ERROR_ID(void)
+{
+    return -1;
+}
+#endif
+
+
+/**
+* @brief   Register to break at raising error at the moment
+*
+* @param   ID Breaking number of error
+* @return  None
+*
+* @par Description
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro was defined
+*    to be 0. The following descriptions are available, if "R_OSPL_ERROR_BREAK"
+*    macro was defined to be 1.
+*
+*    Set a break point at "R_DebugBreak" function, when the process breaks
+*    at the error raised code.
+*
+*    The number of "ErrorID" argument can be known by "R_DEBUG_BREAK_IF_ERROR"
+*    macro or "R_OSPL_GET_ERROR_ID" macro.
+*    - In multi - threading environment, the number of "ErrorID" argument is the
+*    number of raised errors in all threads. But when "ErrorID" argument was
+*    set to be over 2, call "R_OSPL_SET_DEBUG_WORK" function before calling
+*    "R_OSPL_SET_BREAK_ERROR_ID" function.
+*
+*    The following code breaks at first error.
+*    @code
+*    R_OSPL_SET_BREAK_ERROR_ID( 1 );
+*    @endcode
+*
+*    The following code breaks at next error after resuming from meny errors.
+*    @code
+*    R_OSPL_SET_BREAK_ERROR_ID( R_OSPL_GET_ERROR_ID() + 1 );
+*    @endcode
+*/
+#if R_OSPL_ERROR_BREAK
+void  R_OSPL_SET_BREAK_ERROR_ID( int_fast32_t ID );
+#else
+INLINE void  R_OSPL_SET_BREAK_ERROR_ID( int_fast32_t const ID )
+{
+    R_UNREFERENCED_VARIABLE( ID );
+}
+#endif
+
+
+/**
+* @brief   Set the debug work area
+*
+* @param   WorkArea Start address of work area
+* @param   WorkAreaSize Size of work area (byte). See. <R_OSPL_DEBUG_WORK_SIZE>
+* @return  None
+*
+* @par Description
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro was defined
+*    to be 0. The following descriptions are available, if "R_OSPL_ERROR_BREAK"
+*    macro was defined to be 1.
+*
+*    Set the debug work area, when "R_OSPL_SET_BREAK_ERROR_ID" function
+*    supports multi thread. "E_NO_DEBUG_TLS" error is raised, if the debug
+*    work area was not set, when errors was raised in 2 or more threads.
+*    It is not necessary to call this function, if error handling did by one
+*    thread only.
+*
+* @par Example
+*    @code
+*    #if R_OSPL_ERROR_BREAK
+*    #define  GS_MAX_THREAD  10
+*    static uint8_t  gs_DebugWorkArea[ R_OSPL_DEBUG_WORK_SIZE( GS_MAX_THREAD ) ];
+*    #endif
+*
+*    R_OSPL_SET_DEBUG_WORK( gs_DebugWorkArea, sizeof(gs_DebugWorkArea) );
+*    @endcode
+*/
+#if R_OSPL_ERROR_BREAK
+void  R_OSPL_SET_DEBUG_WORK( void *WorkArea, uint32_t WorkAreaSize );
+#else
+INLINE void  R_OSPL_SET_DEBUG_WORK( const void *const WorkArea, uint32_t const WorkAreaSize )
+{
+    R_UNREFERENCED_VARIABLE_2( WorkArea, WorkAreaSize );
+}
+#endif
+
+
+/**
+* @brief   Returns debbug information of current thread.
+*
+* @par Parameters
+*    None
+* @return  Debbug information of current thread.
+*/
+#if R_OSPL_ERROR_BREAK
+r_ospl_error_t  *R_OSPL_GetCurrentThreadError(void);
+#endif
+
+
+/**
+* @brief   Modifies count of objects that current thread has locked.
+*
+* @param   Plus The value of adding to the counter.
+* @return  None
+*
+* @par Description
+*    The counter is subtracted, if this argument was minus.
+*
+*    Drivers calls this function.
+*    This function is not called from OSPL.
+*    This function does nothing, if "R_OSPL_ERROR_BREAK" macro is 0.
+*/
+#if R_OSPL_ERROR_BREAK
+#if R_OSPL_IS_PREEMPTION
+void         R_OSPL_MODIFY_THREAD_LOCKED_COUNT( int_fast32_t Plus );
+#else
+INLINE void  R_OSPL_MODIFY_THREAD_LOCKED_COUNT( int_fast32_t Plus ) {}
+#endif
+#else
+INLINE void          R_OSPL_MODIFY_THREAD_LOCKED_COUNT( int_fast32_t Plus ) {}
+#endif
+
+
+/**
+* @brief   Returns count of objects that current thread has locked.
+*
+* @par Parameters
+*    None
+* @return  Count of objects that current thread has locked
+*
+* @par Description
+*    This function returns 0, if "R_OSPL_ERROR_BREAK" macro is 0.
+*/
+#if R_OSPL_ERROR_BREAK
+#if R_OSPL_IS_PREEMPTION
+int_fast32_t  R_OSPL_GET_THREAD_LOCKED_COUNT(void);
+#else
+INLINE int_fast32_t  R_OSPL_GET_THREAD_LOCKED_COUNT(void)
+{
+    return 0;
+}
+#endif
+#else
+INLINE int_fast32_t  R_OSPL_GET_THREAD_LOCKED_COUNT(void)
+{
+    return 0;
+}
+#endif
+
+
+/* Section: Accessing to register bit field */
+/**
+* @brief   Reads modifies writes for bit field of 32bit register.
+*
+* @param   in_out_Register Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @param   Value Writing value before shift to the bit field
+* @return  None
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at left of "=" and right of "=". But this is not depend on compiler spcifications. */
+/* ->SEC M1.2.2(QAC-1259) */
+/*    If "Value" is signed, this is depend on CPU bit width. This expects 32bit CPU. But driver code is no problem. */
+
+#define  R_OSPL_SET_TO_32_BIT_REGISTER( in_out_Register, Mask, Shift, Value ) \
+	( *(volatile uint32_t*)(in_out_Register) = (uint32_t)( \
+		( ((uint32_t) *(volatile uint32_t*)(in_out_Register)) & \
+		~(Mask) ) | ( (Mask) & ( ( (uint_fast32_t)(Value) << (Shift) ) & (Mask) ) ) ) )
+/* This code is optimized well. */
+
+/* <-SEC M1.2.2(QAC-1259) */
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else
+
+INLINE void  R_OSPL_SET_TO_32_BIT_REGISTER( volatile uint32_t *const  Register,
+        uint32_t const  Mask,  int_fast32_t const  Shift,  uint32_t const  Value )
+{
+    uint32_t  reg_value;
+
+    IF_DQ ( Register == NULL ) {}
+    else {
+        reg_value = *Register;
+        reg_value = ( reg_value & ~Mask ) | ( ( Value << Shift ) & Mask );
+        *Register = reg_value;
+    }
+}
+
+#endif
+
+
+/**
+* @brief   Reads modifies writes for bit field of 16bit register.
+*
+* @param   in_out_Register Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @param   Value Writing value before shift to the bit field
+* @return  None
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at left of "=" and right of "=". But this is not depend on compiler spcifications. */
+/* ->SEC M1.2.2(QAC-1259) */
+/*    If "Value" is signed, this is depend on CPU bit width. This expects 32bit CPU. But driver code is no problem. */
+
+#define  R_OSPL_SET_TO_16_BIT_REGISTER( in_out_Register, Mask, Shift, Value ) \
+	( *(volatile uint16_t*)(in_out_Register) = (uint16_t)( \
+		( ((uint16_t) *(volatile uint16_t*)(in_out_Register)) & \
+		~(Mask) ) | ( (Mask) & ( ( (uint_fast16_t)(Value) << (Shift) ) & (Mask) ) ) ) )
+/* This code is optimized well. */
+
+
+/* <-SEC M1.2.2(QAC-1259) */
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else
+
+INLINE void  R_OSPL_SET_TO_16_BIT_REGISTER( volatile uint16_t *const  Register,
+        uint16_t const  Mask,  int_fast32_t const  Shift,  uint16_t const  Value )
+{
+    uint16_t  reg_value;
+
+    IF_DQ ( Register == NULL ) {}
+    else {
+        reg_value = *Register;
+        reg_value = (uint16_t)( ( (uint_fast32_t) reg_value & ~(uint_fast32_t) Mask ) |
+                                ( ( (uint_fast32_t) Value << Shift ) & (uint_fast32_t) Mask ) );
+        /* Cast is for SEC R2.4.2 */
+        *Register = reg_value;
+    }
+}
+
+#endif
+
+
+/**
+* @brief   Reads modifies writes for bit field of 8bit register.
+*
+* @param   in_out_Register Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @param   Value Writing value before shift to the bit field
+* @return  None
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at left of "=" and right of "=". But this is not depend on compiler spcifications. */
+/* ->SEC M1.2.2(QAC-1259) */
+/*    If "Value" is signed, this is depend on CPU bit width. This expects 32bit CPU. But driver code is no problem. */
+
+
+#define  R_OSPL_SET_TO_8_BIT_REGISTER( in_out_Register, Mask, Shift, Value ) \
+	( *(volatile uint8_t*)(in_out_Register) = (uint8_t)( \
+		( ((uint8_t) *(volatile uint8_t*)(in_out_Register)) & \
+		~(Mask) ) | ( (Mask) & ( ( (uint_fast8_t)(Value) << (Shift) ) & (Mask) ) ) ) )
+/* This code is optimized well. */
+
+/* <-SEC M1.2.2(QAC-1259) */
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else
+
+INLINE void  R_OSPL_SET_TO_8_BIT_REGISTER( volatile uint8_t *const  Register,
+        uint8_t const  Mask,  int_fast32_t const  Shift,  uint8_t const  Value )
+{
+    uint8_t  reg_value;
+
+    IF_DQ ( Register == NULL ) {}
+    else {
+        reg_value = *Register;
+        reg_value = (uint8_t)( ( (uint_fast32_t) reg_value & ~(uint_fast32_t) Mask ) |
+                               ( ( (uint_fast32_t) Value << Shift ) & (uint_fast32_t) Mask ) );
+        /* Cast is for SEC R2.4.2 */
+        *Register = reg_value;
+    }
+}
+
+#endif
+
+
+/**
+* @brief   Reads for bit field of 32bit register.
+*
+* @param   RegisterValueAddress Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @return  Read value after shift
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at &(get address), cast and *(memory load). But this is not double volatile access. */
+/*    RegisterValueAddress is for avoid QAC-0310,QAC-3345 by cast code at caller. */
+
+#define  R_OSPL_GET_FROM_32_BIT_REGISTER( RegisterValueAddress, Mask, Shift ) \
+	( (uint32_t)( ( (uint32_t)*(volatile const uint32_t*) (RegisterValueAddress) \
+		&  (uint_fast32_t)(Mask) ) >> (Shift) ) )
+/* This code is optimized well. */
+
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else  /* __QAC_ARM_H__ */  /* This code must be tested defined "__QAC_ARM_H__" */
+
+
+/* This inline functions is not expanded on __CC_ARM 5.15 */
+INLINE uint32_t  R_OSPL_GET_FROM_32_BIT_REGISTER( volatile const uint32_t *const  RegisterAddress,
+        uint32_t const  Mask,  int_fast32_t const  Shift )
+{
+    uint32_t  reg_value;
+
+    IF_DQ ( RegisterAddress == NULL ) {
+        enum { num = 0x0EDEDEDE };  /* SEC M1.10.1 */
+        reg_value = num;
+    }
+    else {
+        reg_value = *RegisterAddress;
+        reg_value = ( reg_value & Mask ) >> Shift;
+    }
+    return  reg_value;
+}
+
+#endif
+
+
+/**
+* @brief   Reads for bit field of 16bit register.
+*
+* @param   RegisterValueAddress Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @return  Read value after shift
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at &(get address), cast and *(memory load). But this is not double volatile access. */
+/*    RegisterValueAddress is for avoid QAC-0310,QAC-3345 by cast code at caller. */
+
+#define  R_OSPL_GET_FROM_16_BIT_REGISTER( RegisterValueAddress, Mask, Shift ) \
+	( (uint16_t)( ( (uint_fast32_t)*(volatile const uint16_t*) (RegisterValueAddress) \
+		&  (uint_fast16_t)(Mask) ) >> (Shift) ) )
+/* This code is optimized well. */
+
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else  /* __QAC_ARM_H__ */  /* This code must be tested defined "__QAC_ARM_H__" */
+
+/* This inline functions is not expanded on __CC_ARM 5.15 */
+INLINE uint16_t  R_OSPL_GET_FROM_16_BIT_REGISTER( volatile const uint16_t *const  RegisterAddress,
+        uint16_t const  Mask,  int_fast32_t const  Shift )
+{
+    uint16_t  reg_value;
+
+    IF_DQ ( RegisterAddress == NULL ) {
+        enum { num = 0xDEDE };  /* SEC M1.10.1 */
+        reg_value = num;
+    }
+    else {
+        reg_value = *RegisterAddress;
+        reg_value = (uint16_t)( ( (uint_fast32_t) reg_value & (uint_fast32_t) Mask ) >> Shift );
+        /* Cast is for SEC R2.4.2 */
+    }
+    return  reg_value;
+}
+
+#endif
+
+
+/**
+* @brief   Reads for bit field of 8bit register.
+*
+* @param   RegisterValueAddress Address of accessing register
+* @param   Mask Mask of accessing bit field
+* @param   Shift Shift count. Lowest bit number
+* @return  Read value after shift
+*/
+#if R_OSPL_BIT_FIELD_ACCESS_MACRO
+
+/* ->SEC R3.6.2(QAC-3345) */
+/*    Volatile access at &(get address), cast and *(memory load). But this is not double volatile access. */
+/*    RegisterValueAddress is for avoid QAC-0310,QAC-3345 by cast code at caller. */
+
+#define  R_OSPL_GET_FROM_8_BIT_REGISTER( RegisterValueAddress, Mask, Shift ) \
+	( (uint8_t)( ( (uint_fast32_t)*(volatile const uint8_t*) (RegisterValueAddress) \
+		&  (uint_fast8_t)(Mask) ) >> (Shift) ) )
+/* This code is optimized well. */
+
+/* <-SEC R3.6.2(QAC-3345) */
+
+#else  /* __QAC_ARM_H__ */  /* This code must be tested defined "__QAC_ARM_H__" */
+
+/* This inline functions is not expanded on __CC_ARM 5.15 */
+INLINE uint8_t  R_OSPL_GET_FROM_8_BIT_REGISTER( volatile const uint8_t *const  RegisterAddress,
+        uint8_t const  Mask,  int_fast32_t const  Shift )
+{
+    uint8_t  reg_value;
+
+    IF_DQ ( RegisterAddress == NULL ) {
+        enum { num = 0xDE };  /* SEC M1.10.1 */
+        reg_value = num;
+    }
+    else {
+        reg_value = *RegisterAddress;
+        reg_value = (uint8_t)( ( (uint_fast32_t) reg_value & (uint_fast32_t) Mask ) >> Shift );
+        /* Cast is for SEC R2.4.2 */
+    }
+    return  reg_value;
+}
+
+#endif
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_OSPL_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_ospl_RTX_private.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,87 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_RTX_private.h
+* @brief   OS Porting Layer API for RTX
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef OSPL_RTX_PRIVATE_H
+#define OSPL_RTX_PRIVATE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_ospl_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Starts T-Lock. It is mutual exclusion of threads.
+*
+* @par Parameters
+*    None
+* @return  Error Code. 0=No Error.
+*/
+errnum_t  R_OSPL_Start_T_Lock(void);
+
+
+/**
+* @brief   Ends T-Lock. It is mutual exclusion of threads.
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void      R_OSPL_End_T_Lock(void);
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* OSPL_RTX_PRIVATE_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_ospl_config.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,244 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_config.h
+* @brief   Configuration of OSPL.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+
+/* This file is included from "Project_Config.h" */
+
+
+#ifndef R_OSPL_CONFIG_H
+#define R_OSPL_CONFIG_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "platform_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  R_OSPL_VERSION
+* @brief  Version number of OSPL
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can not be changed.
+*    101 = version 1.01.
+*    Hundreds place is version number of OSPL specification.
+*    Tens place and one's place are minor version number in specified OS and board.
+*/
+#define  R_OSPL_VERSION  90
+
+
+/**
+* @def  R_OSPL_VERSION_STRING
+* @brief  String of version number of OSPL.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can not be changed.
+*/
+#define  R_OSPL_VERSION_STRING  "0.90"
+
+
+/**
+* @def  R_OSPL_IS_PREEMPTION
+* @brief  Whether preemptive RTOS or not.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can not be changed.
+*    The value is 1 or 0.
+*    This value is 0, if the environment was OS less.
+*    It is necessary to configure to pseudo multithreading, if this value was 0.
+*/
+#define  R_OSPL_IS_PREEMPTION   BSP_CFG_RTOS_USED
+
+
+/**
+* @def  R_OSPL_NDEBUG
+* @brief  Debug configuration or Release configuration.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    Define (=Release) or not define (=Debug).
+*    This is same as "NDEBUG" of standard library.
+*    The system can run with the debug configuration OSPL and the release
+*    configuration application.
+*    If the library (compiled binary) called the debug configuration OSPL,
+*    compile the OSPL source with debug configuration.
+*/
+#ifndef  R_OSPL_NDEBUG
+#define  R_OSPL_NDEBUG
+#endif
+
+
+/**
+* @def  R_OSPL_ERROR_BREAK
+* @brief  Whether it is supported to break, when error was raised.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 or 0.
+*/
+#ifndef  R_OSPL_ERROR_BREAK
+#ifdef  R_OSPL_NDEBUG
+#define  R_OSPL_ERROR_BREAK  0
+#else
+#define  R_OSPL_ERROR_BREAK  1
+#endif
+#endif
+
+
+/**
+* @def  R_OSPL_TLS_ERROR_CODE
+* @brief  Whether it is supported that error code is stored in thread local storage
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 or 0.
+*    This value must be 1 by some application or some library with OSPL.
+*/
+#ifndef  R_OSPL_TLS_ERROR_CODE
+#define  R_OSPL_TLS_ERROR_CODE  1
+#endif
+
+
+/**
+* @def  R_OSPL_LIBRARY_MAKING
+* @brief  Whether current project makes library.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 or 0.
+*/
+#ifndef  R_OSPL_LIBRARY_MAKING
+#define  R_OSPL_LIBRARY_MAKING  0
+#endif
+
+
+/**
+* @def  R_BOOL_IS_SIGNED
+* @brief  Whether compiler defines that bool_t type is signed.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 or 0.
+*/
+#define  R_BOOL_IS_SIGNED  1
+
+
+/**
+* @def  R_OSPL_BIT_FIELD_ACCESS_MACRO
+* @brief  Whether bit field access function is provided as macro or function.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 (=macro) or 0 (=function).
+*/
+#define  R_OSPL_BIT_FIELD_ACCESS_MACRO  1
+
+
+/***********************************************************************
+* Macros: R_OSPL_FTIMER_IS
+*    Which channel of timer to use.
+*
+*    : R_OSPL_FTIMER_IS_OSTM0    - OSTM0
+*    : R_OSPL_FTIMER_IS_OSTM1    - OSTM1
+*    : R_OSPL_FTIMER_IS_MTU2_1_2 - MTU2 ch1 and ch2
+*
+* Description:
+*    The value can be changed.
+************************************************************************/
+#define  R_OSPL_FTIMER_IS        R_OSPL_FTIMER_IS_MTU2_1_2
+#define  R_OSPL_FTIMER_IS_OSTM0     0
+#define  R_OSPL_FTIMER_IS_OSTM1     1
+#define  R_OSPL_FTIMER_IS_MTU2_1_2  2
+
+#if R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM0
+#error  OSTM0 is used by RTX
+#endif
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_OSPL_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_ospl_debug.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,251 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_debug.h
+* @brief   Debug tools provided by OSPL.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef OSPL_DEBUG_H
+#define OSPL_DEBUG_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  R_OSPL_DEBUG_TOOL
+* @brief  Whether debug tools function is defined
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value can be changed.
+*    The value is 1 or 0.
+*/
+#ifndef  R_OSPL_DEBUG_TOOL
+#ifndef R_OSPL_NDEBUG
+#define  R_OSPL_DEBUG_TOOL  1
+#else
+#define  R_OSPL_DEBUG_TOOL  0
+#endif
+#endif
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/* Group: Watch */
+
+/**
+* @brief   Registers watching integer variable or pointer variable
+*
+* @param   IndexNum Watch Number, 0 or more
+* @param   Address Address of watching integer variable or pointer variable
+* @param   BreakValue Breaking value of variable when "R_D_Watch" was called
+* @param   IsPrintf Whether "printf" is called, when "R_D_Watch" was called
+* @return  None
+*
+* @par Description
+*    @ref R_D_Add and @ref R_D_Watch are APIs related to watch function.
+*    This debug tool is available, if @ref R_OSPL_DEBUG_TOOL was set to 1.
+*
+*    There is not this function, if @ref R_OSPL_DEBUG_TOOL macro was defined
+*    to be 0. This function is available, if @ref R_OSPL_DEBUG_TOOL macro was
+*    defined to be 1.
+*
+* @par Example
+*    @code
+*    R_D_Add( 0, &var, 0xB0, true );  // 0xB0 may be not hit
+*    @endcode
+*/
+#if R_OSPL_DEBUG_TOOL
+void  R_D_Add( int_fast32_t IndexNum, volatile const void *Address, uint32_t BreakValue, bool_t IsPrintf );
+#endif
+
+
+/**
+* @brief   Show and Check watching variable's value
+*
+* @param   IndexNum Watch Number, 0 or more
+* @return  None
+*
+* @par Description
+*    @ref R_D_Add and @ref R_D_Watch are APIs related to watch function.
+*    This debug tool is available, if "R_OSPL_DEBUG_TOOL" was set to 1.
+*    This function calls "printf" with the value of variable registered
+*    by "R_D_Add" and breaks when watching variable becomes registered value.
+*    This function can be called from out of scope of registered variable.
+*    Then this function can be written at many places without care of the scope.
+*
+*    There is not this function, if @ref R_OSPL_DEBUG_TOOL macro was defined
+*    to be 0. This function is available, if @ref R_OSPL_DEBUG_TOOL macro was
+*    defined to be 1.
+*
+*    If internal data of the debug tool was broken, the global variable in
+*    "r_ospl_debug.o" file should be move to safe address (memory map).
+*
+* @par Example
+*    @code
+*    printf( 41 );  // Show the value indicated this place
+*    R_D_Watch( 0 );
+*    @endcode
+*/
+#if R_OSPL_DEBUG_TOOL
+void  R_D_Watch( int_fast32_t IndexNum );
+#endif
+
+
+/* Group: Int Log */
+
+/**
+* @brief   Records to the log fast
+*
+* @param   Value Recording value
+* @return  None
+*
+* @par Description
+*    @ref R_D_AddToIntLog, @ref g_IntLog and @ref g_IntLogLength are APIs related
+*    to Int Log function.
+*    This debug tool is available, if @ref R_OSPL_DEBUG_TOOL was set to 1.
+*    This function overwrites from the first of the log, if max element
+*    value of "g_IntLog" was over.
+*    It is recommended to record not only the showing value of variable,
+*    but also the value of the identifier of the place and the value of
+*    current time.
+*
+*    There is not this function, if @ref R_OSPL_DEBUG_TOOL macro was defined
+*    to be 0. This function is available, if @ref R_OSPL_DEBUG_TOOL macro was
+*    defined to be 1.
+*
+*    If internal data of the debug tool was broken, the global variable in
+*    "r_ospl_debug.o" file should be move to safe address (memory map).
+*/
+#if R_OSPL_DEBUG_TOOL
+void  R_D_AddToIntLog( int_fast32_t Value );
+#endif
+
+
+/**
+* @def  g_IntLogCount
+* @brief  Max count of int log
+*/
+#if R_OSPL_DEBUG_TOOL
+enum { g_IntLogCount = 100 };
+#endif
+
+
+/** Memory area of int log */
+#if R_OSPL_DEBUG_TOOL
+extern volatile int_fast32_t   g_IntLog[ g_IntLogCount ];
+#endif
+
+
+/** Length of recorded in <g_IntLog> */
+#if R_OSPL_DEBUG_TOOL
+extern volatile int_fast32_t   g_IntLogLength;
+#endif
+
+
+/* Group: Debug Variable */
+
+/**
+* @def  g_DebugVarCount
+* @brief  Count of debug variable.
+*/
+#if R_OSPL_DEBUG_TOOL
+enum { g_DebugVarCount = 10 };
+#endif
+
+
+/** Debug variables. */
+#if R_OSPL_DEBUG_TOOL
+extern volatile uint_fast32_t  g_DebugVar[ g_DebugVarCount ];
+#endif
+
+
+/* Group: Through Counter */
+
+/**
+* @brief   Count the through count
+*
+* @param   in_out_Counter Input/Output: The through counter
+* @param   TargetCount The value comparing with the through counter
+* @param   Label The label for "printf", NULL=printf : no output
+* @return  None
+*
+* @par Description
+*    This debug tool is available, if @ref R_OSPL_DEBUG_TOOL was set to 1.
+*    If this function was called with "TargetCount = 0", the count of
+*    through is output by "printf" for each calling. If "TargetCount"
+*    argument was set to the through count and restart the program,
+*    when the counter was counted up to "TargetCount", this function
+*    returns "true". If there were many "printf" output, set "Label = NULL".
+*    At first calling, the address of the counter is output by "printf".
+*    The counter can be look by the debugger.
+*
+* @par Example
+*    @code
+*    { static int tc;  if ( R_D_Counter( &tc, 0, "A" ) ) {
+*    R_DEBUG_BREAK(); }}
+*    @endcode
+*/
+#if R_OSPL_DEBUG_TOOL
+bool_t  R_D_Counter( int_fast32_t *in_out_Counter, int_fast32_t TargetCount, char_t *Label );
+#endif
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* _OSPL_DEBUG_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_ospl_os_less.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,198 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_os_less.h
+* @brief   OS Porting Layer API for OS less Compatibility
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef OSPL_OS_LESS_H
+#define OSPL_OS_LESS_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_ospl_os_less_typedef.h"
+#include "./r_ospl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/* In "ospl_os_less_typedef.h" */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* In "ospl_os_less_typedef.h" */
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+/* In "ospl_os_less_typedef.h" */
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Set waiting behavior of current thread.
+*
+* @param   OnWait Behavior on waiting
+* @return  Error code.  If there is no error, the return value is 0.
+*
+* @par Description
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 0
+*
+*    Initial value is @ref R_OSPL_WAIT_POLLING.
+*    If this function was called from the interrupt context, E_STATE error is raised.
+*
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 1
+*
+*    This function is for compatibility only.
+*    Arguments are ignored.
+*    This function returns 0.
+*
+*    Refer to: @ref R_OSPL_THREAD_GetIsWaiting
+*/
+INLINE errnum_t  R_OSPL_THREAD_SetOnWait( r_ospl_wait_t const  OnWait )
+{
+    return  0;
+}
+
+
+/**
+* @brief   Get waiting behavior of current thread.
+*
+* @par Parameters
+*    None
+* @return  Behavior on waiting
+*
+* @par Description
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 0
+*
+*    Initial value is @ref R_OSPL_WAIT_POLLING.
+*    If this function was called from the interrupt context,
+*    this function returns @ref R_OSPL_WAIT_POLLING.
+*
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 1
+*
+*    This function is for compatibility only.
+*    This function returns R_OSPL_WAIT_POLLING.
+*    But it does not polling on waiting
+*
+*    Refer to: @ref R_OSPL_THREAD_SetOnWait
+*/
+INLINE r_ospl_wait_t  R_OSPL_THREAD_GetOnWait(void)
+{
+    return  R_OSPL_WAIT_POLLING;
+}
+
+
+/**
+* @brief   Get whether the current thread is waiting or not.
+*
+* @par Parameters
+*    None
+* @return  Whether the current thread is waiting or not
+*
+* @par Description
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 0
+*
+*    If @ref R_OSPL_WAIT_PM_THREAD was set by @ref R_OSPL_THREAD_SetOnWait function,
+*    some waiting functions return soon even if the state is waiting and
+*    @ref R_OSPL_THREAD_GetIsWaiting function returns true.
+*
+*    If time out was set to 0, @ref R_OSPL_THREAD_GetIsWaiting function returns
+*    true at time out, even if any value was passed to @ref R_OSPL_THREAD_SetOnWait
+*    function,
+*
+*    If this function was called from the interrupt context, this function
+*    returns false and @ref ASSERT_D in this function notifies in debug configuration.
+*
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 1
+*
+*    This function is for compatibility only.
+*    This function returns false.
+*
+* @par Example
+*    @code
+*    e= R_OSPL_Delay( 100 ); IF(e){goto fin;}
+*    if ( R_OSPL_THREAD_GetIsWaiting() ) { e=0; goto fin; }
+*    @endcode
+*/
+INLINE bool_t  R_OSPL_THREAD_GetIsWaiting(void)
+{
+    return  false;
+}
+
+
+/**
+* @brief   Exit waiting state, if current thread was waiting state.
+*
+* @par Parameters
+*    None
+* @return  None
+*
+* @par Description
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 0
+*
+*    The thread returned true from @ref R_OSPL_THREAD_GetIsWaiting function
+*    after a waiting function must call the waiting function again.
+*    After exiting waiting state, other operation and other waiting can
+*    be done. If time out was set to 0, exiting does not have to do.
+*
+*    If it was detected in OSPL API that necessary exiting was not done,
+*    E_STATE error is raised. However sometimes the state can not be detected.
+*    In this case, time out will be not correct.
+*
+*    This function does not do anything called from the interrupt context.
+*    "ASSERT_D" in this function notifies in debug configuration.
+*
+*    @par - Case of <R_OSPL_IS_PREEMPTION> = 1
+*
+*    This function is for compatibility only.
+*    This function does not do anything.
+*/
+INLINE void  R_OSPL_THREAD_ExitWaiting(void)
+{
+}
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* OSPL_OS_LESS_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_ospl_os_less_private.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,134 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_os_less_private.h
+* @brief   OS Porting Layer private functions for OS less
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef OSPL_OS_LESS_PRIVATE_H
+#define OSPL_OS_LESS_PRIVATE_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_ospl_os_less_typedef.h"
+#include "./r_ospl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/**
+* @struct  r_ospl_master_t
+* @brief  Variables for OSPL
+*/
+typedef struct st_r_ospl_master_t  r_ospl_master_t;
+struct st_r_ospl_master_t {
+#if ! R_OSPL_IS_PREEMPTION
+    /** CurrentThread */
+    r_ospl_thread_def_t    *CurrentThread;
+
+    /** IdleCallback */
+    r_ospl_idle_callback_t  IdleCallback;
+#endif
+    /** IsFreeRunTimerSpec */
+    bool_t  IsFreeRunTimerSpec;
+
+    /** FreeRunTimerSpec */
+    r_ospl_ftimer_spec_t  FreeRunTimerSpec;
+
+    /** MaxOneTimeoutTime */
+    uint32_t  MaxOneTimeoutTime;
+};
+
+
+/* Section: Global */
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   Returns <r_ospl_master_t> type variable.
+*
+* @par Parameters
+*    None
+* @return  <r_ospl_master_t> type variable.
+*/
+r_ospl_master_t  *R_OSPL_GetPrivateContext(void);
+
+
+/**
+* @brief   Sub routine of <R_OSPL_MEMORY_Flush>
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void    R_OSPL_MEMORY_Flush_Sub(void);
+
+
+/**
+* @brief   GetCacheLineSize
+*
+* @par Parameters
+*    None
+* @return  CacheLineSize
+*/
+size_t  R_OSPL_MEMORY_GetCacheLineSize(void);
+
+
+/**
+* @brief   Sub routine of <R_OSPL_MEMORY_RangeFlush>
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+void    R_OSPL_MEMORY_RangeFlush_Sub( uintptr_t Start,  uintptr_t Over,  size_t CacheLineSize );
+
+
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* OSPL_OS_LESS_PRIVATE_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_ospl_os_less_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_os_less_typedef.h
+* @brief   OS Porting Layer API for OS less Compatibility. Data types.
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef OSPL_OS_LESS_TYPEDEF_H
+#define OSPL_OS_LESS_TYPEDEF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @enum   r_ospl_wait_t
+* @brief  Waitnig mode of pseudo multi thread
+*
+*    - R_OSPL_WAIT_POLLING - 0
+*    - R_OSPL_WAIT_PM_THREAD - 1
+*/
+typedef enum {
+    R_OSPL_WAIT_POLLING   = 0,
+    R_OSPL_WAIT_PM_THREAD = 1
+}
+                        r_ospl_wait_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "r_ospl_os_less.h" */
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* OSPL_OS_LESS_TYPEDEF_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_ospl_private.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,138 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_private.h
+* @brief   OS Porting Layer private API for OS less
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef R_OSPL_PRIVATE_H
+#define R_OSPL_PRIVATE_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  r_ospl_table_block_t
+* @brief  Block of <r_ospl_table_t>
+*/
+typedef struct st_r_ospl_table_block_t  r_ospl_table_block_t;
+struct st_r_ospl_table_block_t {
+
+    /** this[ SortedKeyIndex ].Key ... */
+    const void  *Key;
+
+    /** Index */
+    int16_t  Index;
+
+    /** this[ Index ].NextFreeIndex  : Index is not same as SortedKeyIndex */
+    int16_t  NextFreeIndex;
+};
+enum {
+    R_OSPL_TABLE_BLOCK_USED    = -1,
+    R_OSPL_TABLE_BLOCK_NO_NEXT = -2
+};
+
+
+/**
+* @struct  r_ospl_table_searched_t
+* @brief  Result of searching
+*/
+typedef struct st_r_ospl_table_searched_t  r_ospl_table_searched_t;
+struct st_r_ospl_table_searched_t {
+
+    /** SortedKeyIndex */
+    int_fast32_t  SortedKeyIndex;
+
+    /** IsFound */
+    bool_t  IsFound;
+};
+
+
+/* Section: Global */
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+#if ! IS_MBED_USED
+#if  defined( __CC_ARM )
+
+/* ->QAC 0289 */ /* ->QAC 1002 */ /* ->MISRA 5.1 */
+extern uint32_t  Image$$BEGIN_OF_CACHED_RAM_BARRIER$$Base;
+extern uint32_t  Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base;
+extern uint32_t  Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$ZI$$Limit;
+extern uint32_t  Image$$END_OF_INTERNAL_RAM_BARRIER$$ZI$$Limit;
+/* <-QAC 0289 */ /* <-QAC 1002 */ /* <-MISRA 5.1 */
+
+#endif
+#else  /* IS_MBED_USED */
+extern uint32_t  Image$$RW_DATA_NC$$Base;
+#endif
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/**
+* @brief   LockUnlockedChannel
+*
+* @param   out_ChannelNum ChannelNum
+* @param   HardwareIndexMin HardwareIndexMin
+* @param   HardwareIndexMax HardwareIndexMax
+* @return  Error Code. 0=No Error.
+*/
+#if ! BSP_CFG_USER_LOCKING_ENABLED
+errnum_t  R_OSPL_LockUnlockedChannel( int_fast32_t *out_ChannelNum,
+                                      mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax );
+#endif
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_OSPL_PRIVATE_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_ospl_typedef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,918 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_typedef.h
+* @brief   OS Porting Layer. Data types.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef R_OSPL_TYPEDEF_H
+#define R_OSPL_TYPEDEF_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#ifdef  __GNUC__
+#include  <stdint.h>
+#include  <stdbool.h>
+#endif
+#include  "Project_Config.h"
+#include  "r_typedefs.h"
+#include  "mcu_interrupts_typedef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+typedef struct st_r_ospl_async_t          r_ospl_async_t;
+typedef struct st_r_ospl_async_status_t   r_ospl_async_status_t;
+typedef struct st_r_ospl_flag32_t         r_ospl_flag32_t;
+typedef struct st_r_ospl_interrupt_t      r_ospl_interrupt_t;
+typedef struct st_r_ospl_irq_mask_t       r_ospl_irq_mask_t;
+typedef struct st_r_ospl_memory_spec_t    r_ospl_memory_spec_t;
+typedef struct st_r_ospl_ftimer_spec_t    r_ospl_ftimer_spec_t;
+typedef struct st_r_ospl_table_t          r_ospl_table_t;
+typedef struct st_r_ospl_i_lock_vtable_t  r_ospl_i_lock_vtable_t;
+typedef struct st_r_ospl_caller_t         r_ospl_caller_t;
+
+
+/**
+* @typedef  errnum_t
+* @brief  Error number
+*/
+typedef int_fast32_t   errnum_t;
+
+
+/**
+* @typedef  bit_flags_fast32_t
+* @brief  Bit flags as "uint_fast32_t"
+*/
+typedef uint_fast32_t  bit_flags_fast32_t;
+
+
+/**
+* @typedef  bit_flags32_t
+* @brief  Bit flags as "uint32_t"
+*/
+typedef uint32_t       bit_flags32_t;
+
+
+/**
+* @typedef  bit_flags16_t
+* @brief  Bit flags as "uint16_t"
+*/
+typedef uint16_t       bit_flags16_t;
+
+
+/**
+* @typedef  bit_flags8_t
+* @brief  Bit flags as "uint8_t"
+*/
+typedef uint8_t       bit_flags8_t;
+
+
+/**
+* @typedef  byte_t
+* @brief  Byte type
+*/
+typedef uint8_t        byte_t;
+
+
+/**
+* @typedef  ssize_t
+* @brief  Signed size type. This is a POSIX specification.
+*/
+#if ! defined( __GNUC__ )  ||  defined( __CC_ARM )
+typedef int  ssize_t;
+#endif
+
+
+/***********************************************************************
+* Section: Global
+************************************************************************/
+/* Start of a part of CMSIS : Copy from cmsys_os.h */
+/* This is for not calling CMSIS function */
+
+
+/**
+* @typedef  osMailQId
+* @brief  osMailQId
+*/
+#ifdef IS_CMSIS_USED
+typedef struct os_mailQ_cb *osMailQId;
+#endif
+
+
+/**
+* @struct  r_ospl_rtx_osMailQDef_t
+* @brief  RTX:osMailQDef_t
+*/
+#ifdef IS_CMSIS_USED
+typedef struct r_ospl_rtx_os_mailQ_def  {
+    uint32_t                queue_sz;    ///< number of elements in the queue
+    uint32_t                 item_sz;    ///< size of an item
+    void                       *pool;    ///< memory array for mail
+} r_ospl_rtx_osMailQDef_t;
+#endif
+
+
+/* Section: Global */
+/**
+* @def  r_ospl_rtx_osMailQDef
+* @brief  RTX:osMailQDef
+* @par Parameters
+*    None
+* @return  None.
+*/
+#ifdef IS_CMSIS_USED
+#if defined (osObjectsExternal)  // object is external
+#define r_ospl_rtx_osMailQDef(name, queue_sz, type) \
+extern const osMailQDef_t os_mailQ_def_##name
+#else                            // define the object
+#define r_ospl_rtx_osMailQDef(name, queue_sz, type) \
+uint32_t os_mailQ_q_##name[4+(queue_sz)] = { 0 }; \
+uint32_t os_mailQ_m_##name[3+((sizeof(type)+3)/4)*(queue_sz)]; \
+void *   os_mailQ_p_##name[2] = { (os_mailQ_q_##name), os_mailQ_m_##name }; \
+const r_ospl_rtx_osMailQDef_t os_mailQ_def_##name =  \
+{ (queue_sz), sizeof(type), (os_mailQ_p_##name) }
+#endif
+#endif
+
+
+/**
+* @def  osMailQ
+* @brief  osMailQ
+* @par Parameters
+*    None
+* @return  None.
+*/
+#ifdef IS_CMSIS_USED
+#define osMailQ(name)  \
+&os_mailQ_def_##name
+#endif
+
+
+/***********************************************************************
+*  Section: Global
+************************************************************************/
+/* End of a part of CMSIS */
+
+
+/**
+* @struct  r_ospl_thread_id_t
+* @brief  Pointer to a thread
+*/
+#ifdef IS_CMSIS_USED
+typedef void * /*<r_ospl_thread_def_t*>*/  r_ospl_thread_id_t;
+#define  R_OSPL_THREAD_INTERRUPT  ((void*) 0 )
+#endif
+
+
+/* Section: Global */
+/**
+* @brief   The function type of interrupt callback
+*
+* @param   InterruptSource Source of interrupt
+* @param   Caller Driver's internal parameters about interrupt operations
+* @return  Error code.  If there is no error, the return value is 0. The value set to "r_ospl_async_t::ReturnValue"
+*
+* @par Description
+*    This is type of the interrupt callback function running in the
+*    interrupt context and called from the interrupt handler.
+*
+*    It is possible to replace to application defined interrupt callback function
+*    by setting to "r_ospl_async_t::InterruptCallback". But it is usually not
+*    necessary to replace.
+*
+*    As interrupt callback function, the default interrupt callback function
+*    provided from the driver is used. It is unusual to use application defined
+*    interrupt callback function.
+*    Write the response code of the interrupt (event driven code) next to the
+*    code calling @ref R_OSPL_EVENT_Wait function
+*
+*    Whether the asynchronous operation was ended is possible to know whether
+*    the variable of "r_ospl_async_state_t" type referred from
+*    @ref R_DRIVER_GetAsyncStatus function is set to @ref R_OSPL_RUNNABLE value.
+*
+*    It is not necessary to write the code of interrupt return (IRET) in
+*    the interrupt callback function. The interrupt handlers calling interrupt
+*    callback function calls IRET, if necessary.
+*
+*    It is not possible to divide interrupt callback functions by the kind of
+*    interrupt. Alternatively, it is possible to write operations in interrupt
+*    handlers calling interrupt callback function in porting layer under the driver.
+*    There are interrupt handlers by each interrupt numbers.
+*
+*    It is possible to signal any event from application defined interrupt
+*    @par callback function. But it is necessary to do following operations
+*/
+typedef errnum_t  (* r_ospl_callback_t )( const r_ospl_interrupt_t *InterruptSource, const r_ospl_caller_t *Caller );
+
+
+/**
+* @enum   r_ospl_async_state_t
+* @brief  Asynchronous State
+*
+*    - R_OSPL_UNINITIALIZED - 0
+*    - R_OSPL_RUNNABLE - 1, Runnable or Waitable
+*    - R_OSPL_RUNNING - 2, Running  or Waiting
+*    - R_OSPL_INTERRUPTING - 3
+*    - R_OSPL_INTERRUPTED - 4
+*/
+typedef enum {
+    R_OSPL_UNINITIALIZED = 0,
+    R_OSPL_RUNNABLE,
+    R_OSPL_RUNNING,
+    R_OSPL_INTERRUPTING,
+    R_OSPL_INTERRUPTED
+} r_ospl_async_state_t;
+
+
+/**
+* @enum   r_ospl_async_type_t
+* @brief  Asynchronous State
+*
+*    - R_OSPL_ASYNC_TYPE_NORMAL - 1
+*    - R_OSPL_ASYNC_TYPE_FINALIZE - 2, Asynchronous finalizing
+*/
+typedef enum {
+    R_OSPL_ASYNC_TYPE_NORMAL   = 1,
+    R_OSPL_ASYNC_TYPE_FINALIZE = 2
+} r_ospl_async_type_t;
+
+
+/**
+* @struct  r_ospl_block_t
+* @brief  Block in queue
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+typedef struct st_r_ospl_block_t  r_ospl_block_t;
+struct st_r_ospl_block_t {
+    r_ospl_block_t  *Next;
+};
+
+
+/**
+* @struct  r_ospl_queue_status_t
+* @brief  r_ospl_queue_status_t
+*/
+typedef struct st_r_ospl_queue_status_t {
+
+    /** UsedCount */
+    int_fast32_t  UsedCount;
+
+    /** MaxCount */
+    int_fast32_t  MaxCount;
+} r_ospl_queue_status_t;
+
+
+/**
+* @struct  r_ospl_queue_def_t
+* @brief  r_ospl_queue_def_t
+* @par Description
+*    Member variables should not be accessed.
+*/
+typedef struct st_r_ospl_queue_def_t {
+    osMailQId                       MailQId;
+    r_ospl_queue_status_t           PublicStatus;
+    const r_ospl_rtx_osMailQDef_t  *MailQDef;
+} r_ospl_queue_def_t;
+
+
+/**
+* @struct  r_ospl_queue_t
+* @brief  r_ospl_queue_t
+* @par Description
+*    Member variables should not be accessed.
+*/
+typedef r_ospl_queue_def_t  r_ospl_queue_t;
+
+
+/* Section: Global */
+/**
+* @def  R_OSPL_QUEUE_DEF
+* @brief  Defines attributes of queue and work area.
+* @param   Name Thread name. Do not bracket by ""
+* @param   MaxCount Max count of elements in the queue
+* @param   Type Output
+* @return  None.
+*
+* @par Description
+*    It is not possible to use this macro in the library.
+*    If implement of OSPL was changed, the library must be recompiled.
+*/
+#define  R_OSPL_QUEUE_DEF( Name, MaxCount, Type ) \
+	r_ospl_rtx_osMailQDef( Name, MaxCount, Type ); \
+	r_ospl_queue_def_t  Name##_OSPL_DEF = { NULL, 0, (MaxCount), osMailQ( Name ) }
+
+
+/**
+* @def  R_OSPL_QUEUE
+* @brief  Returns initial attributes of queue and work area.
+* @param   Name Queue's name. Do not bracket by ""
+* @return  None.
+*
+* @par Description
+*    It is not possible to use this macro in the library.
+*    If implement of OSPL was changed, the library must be recompiled.
+*/
+#define  R_OSPL_QUEUE( Name )  (&Name##_OSPL_DEF)
+
+
+/**
+* @typedef  r_ospl_flush_t
+* @brief  r_ospl_flush_t
+*/
+typedef bit_flags_fast32_t  r_ospl_flush_t;
+#define  /*<uint_fast32_t>*/  R_OSPL_FLUSH_INVALIDATE                0u
+#define  /*<uint_fast32_t>*/  R_OSPL_FLUSH_WRITEBACK_INVALIDATE      2u
+#define  /*<uint_fast32_t>*/  R_OSPL_FLUSH_WRITEBACK_INVALIDATE_2ND  8u
+
+
+/**
+* @struct  r_ospl_flag32_t
+* @brief  This is the type of flags having 32bit
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+struct st_r_ospl_flag32_t {
+    volatile uint32_t  Flags;
+};
+
+
+/**
+* @struct  r_ospl_interrupt_t
+* @brief  Structure related to interrupt source. e.g. interrupt number
+*/
+struct st_r_ospl_interrupt_t {
+
+    /** <bsp_int_src_t> */
+    bsp_int_src_t  IRQ_Num;
+
+    /** ChannelNum */
+    int_fast32_t   ChannelNum;
+
+    /** Type */
+    int_fast32_t   Type;
+
+    /** Delegate */
+    void  *Delegate;
+};
+
+
+/**
+* @struct  r_ospl_async_status_t
+* @brief  Structure of driver's status and interrupt status defined by OSPL
+*/
+struct st_r_ospl_async_status_t {
+
+    /** <r_ospl_async_state_t> */
+    volatile r_ospl_async_state_t  State;
+
+    /** IsEnabledInterrupt */
+    volatile bool_t  IsEnabledInterrupt;
+
+    /** InterruptEnables */
+    volatile r_ospl_flag32_t  InterruptEnables;
+
+    /** InterruptFlags */
+    volatile r_ospl_flag32_t  InterruptFlags;
+
+    /** r_ospl_flag32_t < <r_ospl_cancel_flag_t> > */
+    volatile r_ospl_flag32_t  CancelFlags;  /*<r_ospl_cancel_flag_t>*/
+#if  R_OSPL_IS_PREEMPTION
+    union {
+
+        /** LockOwner */
+        volatile r_ospl_thread_id_t  Thread;
+
+        /** LockOwner */
+        volatile void  *Context;
+    } LockOwner;
+#endif
+};
+
+
+/**
+* @struct  r_ospl_async_t
+* @brief  Setting of notifications
+*/
+struct st_r_ospl_async_t {
+
+    /** Flags */
+    bit_flags_fast32_t  Flags;
+
+    /** Delegate */
+    void  *Delegate;
+
+    /** A_Thread */
+    r_ospl_thread_id_t  A_Thread;
+
+    /** A_EventValue */
+    uint32_t  A_EventValue;  /* QAC 4130 */
+
+    /** I_Thread */
+    r_ospl_thread_id_t  I_Thread;
+
+    /** I_EventValue */
+    uint32_t  I_EventValue;  /* QAC 4130 */
+
+    /** InterruptCallback */
+    r_ospl_callback_t  InterruptCallback;
+
+    /** ReturnValue */
+    errnum_t  ReturnValue;
+};
+
+enum {
+    R_F_OSPL_A_Thread          = 0x0001,
+    R_F_OSPL_A_EventValue      = 0x0002,
+    R_F_OSPL_I_Thread          = 0x0004,
+    R_F_OSPL_I_EventValue      = 0x0008,
+    R_F_OSPL_InterruptCallback = 0x0010,
+    R_F_OSPL_Delegate          = 0x0080
+};
+
+
+/* Section: Global */
+/***********************************************************************
+* Macros: r_ospl_internal_sentinel
+*
+*    : R_F_OSPL_ASYNC_FLAGS_SENTINEL_MASK  - 0x7FFFFF40
+*    : R_F_OSPL_ASYNC_FLAGS_SENTINEL_VALUE - 0x4A5C0000
+************************************************************************/
+#ifndef R_OSPL_NDEBUG
+enum {
+    R_F_OSPL_ASYNC_FLAGS_SENTINEL_MASK  = 0x7FFFFF40,
+    R_F_OSPL_ASYNC_FLAGS_SENTINEL_VALUE = 0x4A5C0000
+};
+#endif
+
+
+/**
+* @struct  r_ospl_caller_t
+* @brief  Context of interrupt callback function caller
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+struct st_r_ospl_caller_t {
+    r_ospl_async_t                *Async;
+    volatile int_fast32_t         *PointerToState;
+    int_fast32_t                   StateValueOfOnInterrupting;
+    void                          *I_Lock;
+    const r_ospl_i_lock_vtable_t  *I_LockVTable;
+};
+
+
+/***********************************************************************
+* Class: r_ospl_i_lock_vtable_t
+*    I-Lock V-Table
+************************************************************************/
+typedef bool_t (* r_ospl_i_lock_lock_func_t )( void *const  self_ );
+typedef void   (* r_ospl_i_lock_unlock_func_t )( void *const  self_ );
+typedef void   (* r_ospl_i_lock_get_rf_func_t )( void *const  self_ );    /* rf = RequestFinalize */
+typedef bool_t (* r_ospl_i_lock_get_rcn_func_t )( const void *const  self_ );   /* rcn = RootChannelNum */
+
+struct st_r_ospl_i_lock_vtable_t {
+
+    /**
+    * @brief   Lock
+    *
+    * @par Parameters
+    *    None
+    * @return  None.
+    */
+    bool_t  (* Lock )( void *const  self_ );
+
+    /**
+    * @brief   Unlock
+    *
+    * @par Parameters
+    *    None
+    * @return  None.
+    */
+    void    (* Unlock )( void *const  self_ );
+
+    /**
+    * @brief   RequestFinalize
+    *
+    * @par Parameters
+    *    None
+    * @return  None.
+    */
+    void    (* RequestFinalize )( void *const  self_ );
+
+    /**
+    * @brief   GetRootChannelNum
+    *
+    * @par Parameters
+    *    None
+    * @return  None.
+    */
+    int_fast32_t  (* GetRootChannelNum )( const void *const  self_ );
+};
+
+
+/**
+* @struct  r_ospl_memory_spec_t
+* @brief  Memory specification
+*/
+struct st_r_ospl_memory_spec_t {
+
+    /** (byte) */
+    uint_fast32_t  CacheLineSize;
+};
+
+
+/**
+* @struct  r_ospl_ftimer_spec_t
+* @brief  Free run timer specification
+*/
+struct st_r_ospl_ftimer_spec_t {
+
+    /** msec_Numerator */
+    uint32_t  msec_Numerator;
+
+    /** msec_Denominator */
+    uint32_t  msec_Denominator;
+
+    /** MaxCount */
+    uint32_t  MaxCount;
+
+    /** ExtensionOfCount */
+    uint32_t  ExtensionOfCount;
+};
+
+
+/**
+* @struct  r_ospl_table_t
+* @brief  Index table
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+struct st_r_ospl_table_t {
+    void         *Area;
+    int_fast32_t  Count;
+    int_fast32_t  MaxCount;
+    const void   *KeyCache;
+    int_fast32_t  IndexCache;  /* Not SortedKeyIndex */
+    int16_t       FirstFreeIndex;
+#if R_OSPL_IS_PREEMPTION
+    bool_t        Is_T_Lock;
+#endif
+};
+
+
+/* Section: Global */
+/**
+* @enum   r_ospl_if_not_t
+* @brief  Operation if not exists
+*
+*    - R_OSPL_ERROR_IF_NOT - 0
+*    - R_OSPL_ALLOCATE_IF_NOT - 1
+*    - R_OSPL_DO_NOTHING_IF_NOT - 2
+*/
+typedef enum {
+    R_OSPL_ERROR_IF_NOT      = 0,
+    R_OSPL_ALLOCATE_IF_NOT   = 1,
+    R_OSPL_DO_NOTHING_IF_NOT = 2
+} r_ospl_if_not_t;
+
+
+/**
+* @struct  r_ospl_error_t
+* @brief  Error status of a thread
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+typedef  struct st_r_ospl_error_t  r_ospl_error_t;
+struct st_r_ospl_error_t {
+#if R_OSPL_ERROR_BREAK
+    bool_t         IsError;
+    int_fast32_t   ErrorID;
+    const char_t  *FilePath;
+    int_fast32_t   LineNum;
+#if R_OSPL_IS_PREEMPTION
+    int_fast32_t   ThreadLockedCount;
+#endif
+#endif
+#if R_OSPL_TLS_ERROR_CODE
+    errnum_t       ErrNum;
+#endif
+};
+#endif
+
+
+/**
+* @struct  r_ospl_global_error_t
+* @brief  Error status of global
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+typedef  struct st_r_ospl_global_error_t  r_ospl_global_error_t;
+struct st_r_ospl_global_error_t {
+    r_ospl_table_t   ThreadIndexTable;
+    r_ospl_error_t  *ErrorArray;
+
+#if R_OSPL_ERROR_BREAK
+    int_fast32_t     RaisedGlobalErrorID;
+    int_fast32_t     BreakGlobalErrorID;
+#endif
+};
+#endif
+
+
+/* Section: Global */
+/**
+* @enum   r_ospl_axi_cache_attribute_t
+* @brief  Cache attribute on AXI bus.
+*
+*    - R_OSPL_AXI_CACHE_ZERO - Not AXI
+*    - R_OSPL_AXI_STRONGLY - Strongly order access
+*    - R_OSPL_AXI_DEVICE - DEVICE
+*    - R_OSPL_AXI_UNCACHED - Normal access (Out of order) uncached
+*    - R_OSPL_AXI_WRITE_BACK_W - Write back, allocate on write
+*    - R_OSPL_AXI_WRITE_BACK - Write back, allocate on both read and write
+*/
+typedef enum {
+    R_OSPL_AXI_CACHE_ZERO     =  0,
+    R_OSPL_AXI_STRONGLY       =  0,
+    R_OSPL_AXI_DEVICE         =  1,
+    R_OSPL_AXI_UNCACHED       =  3,
+    R_OSPL_AXI_WRITE_BACK_W   = 11,
+    R_OSPL_AXI_WRITE_BACK     = 15
+} r_ospl_axi_cache_attribute_t;
+
+
+/**
+* @enum   r_ospl_axi_protection_t
+* @brief  Protection on AXI bus.
+*
+*    - R_OSPL_AXI_PROTECTION_ZERO - Not AXI
+*    - R_OSPL_AXI_SECURE - TrustZone secure acccess
+*    - R_OSPL_AXI_NON_SECURE - TrustZone non-secure acccess
+*/
+typedef enum {
+    R_OSPL_AXI_PROTECTION_ZERO = 0,
+    R_OSPL_AXI_SECURE          = 0,
+    R_OSPL_AXI_NON_SECURE      = 2
+} r_ospl_axi_protection_t;
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @enum   Event_Bit_Name
+* @brief  Event_Bit_Name
+*    - R_OSPL_ANY_FLAG - 0x0000
+*    - R_OSPL_A_FLAG - 0x0001
+*    - R_OSPL_I_FLAG - 0x0002
+*    - R_OSPL_FINAL_A_FLAG - 0x0004
+*/
+enum {
+    R_OSPL_ANY_FLAG         = 0x00000000,
+    R_OSPL_A_FLAG           = 0x00000001,
+    R_OSPL_I_FLAG           = 0x00000002,
+    R_OSPL_FINAL_A_FLAG     = 0x00000004
+};
+
+
+/**
+* @typedef  r_ospl_cancel_flag_t
+* @brief  Bit flags of <r_ospl_cancel_bit_t>
+*/
+typedef int_t  r_ospl_cancel_flag_t;
+
+
+/**
+* @enum   r_ospl_cancel_bit_t
+* @brief  r_ospl_cancel_bit_t
+*    - R_OSPL_CANNEL_REQUEST - 0x0001
+*    - R_OSPL_CANNELING - 0x0002
+*    - R_OSPL_CANNELED - 0x0004
+*    - R_OSPL_FINALIZE_REQUEST - 0x0010
+*    - R_OSPL_FINALIZING - 0x0020
+*    - R_OSPL_FINALIZED - 0x0040
+*/
+enum {
+    R_OSPL_CANNEL_REQUEST   = 0x00000001,
+    R_OSPL_CANNELING        = 0x00000002,
+    R_OSPL_CANNELED         = 0x00000004,
+    R_OSPL_FINALIZE_REQUEST = 0x00000010,
+    R_OSPL_FINALIZING       = 0x00000020,
+    R_OSPL_FINALIZED        = 0x00000040
+};
+
+
+/***********************************************************************
+* Macros: OSPL_Others
+*
+*    : R_OSPL_INFINITE         - One of time out value
+*    : R_OSPL_FLAG32_ALL_BITS  - R_OSPL_FLAG32_ALL_BITS
+*    : R_OSPL_EVENT_ALL_BITS   - R_OSPL_EVENT_ALL_BITS
+*    : R_OSPL_TIMEOUT          - Raised time out
+*    : R_OSPL_MAX_TIME_OUT     - Max value of time out
+*    : R_OSPL_NO_INDEX         - R_OSPL_NO_INDEX
+*    : R_OSPL_UNLOCKED_CHANNEL - R_OSPL_UNLOCKED_CHANNEL
+************************************************************************/
+#define R_OSPL_INFINITE           0xFFFFFFFFu   /* uint32_t */
+#define R_OSPL_FLAG32_ALL_BITS    0xFFFFFFFFu   /* uint32_t */
+enum {  R_OSPL_EVENT_ALL_BITS   = 0x0000FFFF };
+enum {  R_OSPL_TIMEOUT          = 0x40000000 };
+enum {  R_OSPL_MAX_TIME_OUT     = 65533 };
+enum {  R_OSPL_NO_INDEX         = -1         };
+enum {  R_OSPL_UNLOCKED_CHANNEL = 0x00000FEE };
+
+
+/**
+* @def  R_OSPL_TABLE_SIZE
+* @brief  Calculates the size of <r_ospl_table_t> type index table
+* @param   MaxCount Max index count
+* @return  Table size
+*/
+/* ->MISRA 19.7 : Array count must const */ /* ->SEC M5.1.3 */
+#define  R_OSPL_TABLE_1_SIZE  8  /* sizeof(r_ospl_table_block_t) */
+#define  R_OSPL_TABLE_SIZE( MaxCount ) \
+	( (MaxCount) * R_OSPL_TABLE_1_SIZE )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @def  R_OSPL_DEBUG_WORK_SIZE
+* @brief  Calculates the size of debug work area
+* @param   ThreadMaxCount Max thread count using error breaking system of OSPL
+* @return  Size of debug work area
+*/
+/* ->MISRA 19.7 : Array count must const */ /* ->SEC M5.1.3 */
+#define  R_OSPL_DEBUG_WORK_1_SIZE  32  /* sizeof(r_ospl_table_block_t) + sizeof(r_ospl_error_t) */
+#define  R_OSPL_DEBUG_WORK_SIZE( ThreadMaxCount ) \
+	( (ThreadMaxCount) * R_OSPL_DEBUG_WORK_1_SIZE )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+
+/**
+* @enum   errnum_t
+* @brief  Error code defined by OSPL
+*
+*    - E_OTHERS - 0x01
+*    - E_FEW_ARRAY - 0x02
+*    - E_FEW_MEMORY - 0x03
+*    - E_FIFO_OVER - 0x04
+*    - E_NOT_FOUND_SYMBOL - 0x05
+*    - E_NO_NEXT - 0x06
+*    - E_ACCESS_DENIED - 0x07
+*    - E_NOT_IMPLEMENT_YET - 0x09
+*    - E_ERRNO - 0x0E
+*    - E_LIMITATION - 0x0F
+*    - E_STATE - 0x10
+*    - E_NOT_THREAD - 0x11
+*    - E_PATH_NOT_FOUND - 0x12
+*    - E_BAD_COMMAND_ID - 0x16
+*    - E_TIME_OUT - 0x17
+*    - E_NO_DEBUG_TLS - 0x1D
+*    - E_EXIT_TEST - 0x1E
+*/
+#define  E_CATEGORY_MASK   0xFFFFFFE0u  /* E_CATEGORY_* */
+enum {   E_OFFSET_MASK   = 0x0000001F };
+
+#ifndef  E_CATEGORY_COMMON  /* Overwritable */
+#define  E_CATEGORY_COMMON  E_CATEGORY_COMMON
+enum { E_CATEGORY_COMMON = 0x00000000 };  /* 0x01, 0x02 .. 0x1F : Reseved */
+#endif
+
+enum { E_OTHERS             = E_CATEGORY_COMMON | 0x01 }; /*  1 */
+enum { E_FEW_ARRAY          = E_CATEGORY_COMMON | 0x02 }; /*  2 */
+enum { E_FEW_MEMORY         = E_CATEGORY_COMMON | 0x03 }; /*  3 */
+enum { E_FIFO_OVER          = E_CATEGORY_COMMON | 0x04 }; /*  4 */
+enum { E_NOT_FOUND_SYMBOL   = E_CATEGORY_COMMON | 0x05 }; /*  5 */
+enum { E_NO_NEXT            = E_CATEGORY_COMMON | 0x06 }; /*  6 */
+enum { E_ACCESS_DENIED      = E_CATEGORY_COMMON | 0x07 }; /*  7 */
+enum { E_NOT_IMPLEMENT_YET  = E_CATEGORY_COMMON | 0x09 }; /*  9 */
+enum { E_ERRNO              = E_CATEGORY_COMMON | 0x0E }; /* 14 */
+enum { E_LIMITATION         = E_CATEGORY_COMMON | 0x0F }; /* 15 */
+enum { E_STATE              = E_CATEGORY_COMMON | 0x10 }; /* 16 */
+enum { E_NOT_THREAD         = E_CATEGORY_COMMON | 0x11 }; /* 17 */
+enum { E_PATH_NOT_FOUND     = E_CATEGORY_COMMON | 0x12 }; /* 18 */
+enum { E_BAD_COMMAND_ID     = E_CATEGORY_COMMON | 0x16 }; /* 22 */
+enum { E_TIME_OUT           = E_CATEGORY_COMMON | 0x17 }; /* 23 */
+enum { E_NO_DEBUG_TLS       = E_CATEGORY_COMMON | 0x1D }; /* 29 */
+enum { E_EXIT_TEST          = E_CATEGORY_COMMON | 0x1E }; /* 30 */
+
+
+/**
+* @def  R_JOIN_SYMBOL_FOR_ASSERT
+* @brief  Sub routine of <R_STATIC_ASSERT>
+* @par Parameters
+*    None
+* @return  None.
+*
+* - This macro extends "x", "y"
+* - This code is referenced by CERT secure coding standard PRE05-C
+*/
+/* ->MISRA 19.7 : Extend macro arguments */ /* ->SEC M5.1.3 */
+#define R_JOIN_SYMBOL_FOR_ASSERT(x, y)  R_JOIN_SYMBOL_FOR_ASSERT_SUB(x, y)
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->MISRA 19.13 : This is used only assertion in compiling */ /* ->SEC M5.1.2 (1) */
+#define R_JOIN_SYMBOL_FOR_ASSERT_SUB(x, y) x##y
+/* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @def  R_STATIC_ASSERT
+* @brief  "static_assert" for in function
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    Compatible with static_assert (C++0x). But our naming rule is not match.
+*    - This code is referenced by CERT secure coding standard DCL03 - C.
+*    This macro raised QAC warning 3205. This is no problem.
+*/
+/* ->SEC M1.1.1 */
+#define  R_STATIC_ASSERT( ConstantExpression, StringLiteral ) \
+	do { typedef char_t R_JOIN_SYMBOL_FOR_ASSERT( assertion_failed_t_, __LINE__ ) \
+		[(ConstantExpression) ? 1 : -1]; } while(0)
+/* If "ConstantExpression" is false, illegal array size error will be raised. */
+/* <-SEC M1.1.1 */
+
+
+/**
+* @def  R_STATIC_ASSERT_GLOBAL
+* @brief  "static_assert" for in global scope
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* ->SEC M1.1.1 */
+/* ->MISRA 19.4 : There is not if statement in global */ /* ->SEC M1.8.2 */
+/* ->MISRA 19.7 : Cannot function */ /* ->SEC M5.1.3 */
+#define  R_STATIC_ASSERT_GLOBAL( ConstantExpression, StringLiteral ) \
+	     typedef char_t R_JOIN_SYMBOL_FOR_ASSERT( assertion_failed_t_, __LINE__ ) \
+		[(ConstantExpression) ? 1 : -1]
+/* If "ConstantExpression" is false, illegal array size error will be raised. */
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+/* <-SEC M1.1.1 */
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+/* In "r_ospl.h" */
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_OSPL_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/inc/r_static_an_tag.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,377 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_static_an_tag.h
+* @brief   Reviewed tag for warnings of static code analysis.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#ifndef R_STATIC_AN_TAG_H
+#define R_STATIC_AN_TAG_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "Project_Config.h"
+#include  "r_typedefs.h"
+#include  "r_multi_compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/***********************************************************************
+* Macros: IS
+*    Changes the code accepted with MISRA 13.2 to readable
+*
+* Arguments:
+*    bool_value - The expression that evaluated result becomes boolean type
+*
+* Return Value:
+*    Evaluate result of "bool_value != 0".
+*
+* Description:
+*   Avoid "not 0" as double negation.
+*   "IS" macro corresponds to cast to boolean type specified in the language.
+*
+*   This is for QAC warning : MISRA 13.2 Advice : Tests of a value against
+*   zero should be made explicit, unless the operand is effectively Boolean.
+*
+*   Write this macro after being warned by static code analyzer.
+*
+* Example:
+*    > if ( IS( bool_value ) ) {...}
+*    > if ( IS( bool_value ) && IS( bool_value2 ) && ! bool_value3 ) {...}
+*    > if ( IS( unsigned_bitfield ) ) {...}
+*    > bool_t is_flag = (bool_t) unsigned_bitfield;  ("IS" is not used)
+************************************************************************/
+/* ->MISRA 19.7 : For return _Bool type */ /* ->SEC M5.1.3 */
+#if ! R_BOOL_IS_SIGNED
+#define  IS( bool_value )  ( (bool_t)( bool_value ) != 0u )
+#else
+#define  IS( bool_value )  ( (bool_t)( bool_value ) != 0 )
+#endif
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+
+#if 0
+/* Comment out because if checking type function(this) was called, raises SEC R3.6.2(QAC 3441) */
+#define  IS( bool_value )  ( IS_Sub( bool_value ) != 0 )
+INLINE bool_t  IS_Sub( bool_t const  value )   /* Check type only */
+{
+    return  value;
+}
+#endif
+
+
+/***********************************************************************
+* Macros: IF_DQ
+*    Error check on DEBUG and QAC version for faster
+************************************************************************/
+/* ->MISRA 19.4 : Compliant with C language syntax. */ /* ->SEC M1.8.2 */
+#if defined(__QAC_ARM_H__)
+#define  IF_DQ  if
+#else
+#define  IF_DQ  IF_D
+#endif
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+
+
+/***********************************************************************
+* Macros: IF_DS
+*    Error check on DEBUG and QAC version for always false
+*
+* Description:
+*    QAC assist tool founds IF_DS keyword.
+*    Sentence using this expects IPA SEC O4.1, O1.1.
+************************************************************************/
+#define  IF_DS  IF_DQ
+
+
+/***********************************************************************
+* Macros: IF_S
+*    Error check on QAC version for always false
+*
+* Description:
+*    QAC assist tool founds IF_S keyword.
+*    Compiler always does not check it.
+************************************************************************/
+/* ->MISRA 19.4 : Compliant with C language syntax. */ /* ->SEC M1.8.2 */
+#if defined(__QAC_ARM_H__)
+#define  IF_S               if
+#else
+#define  IF_S( Condition )  if ( false )
+#endif
+/* <-MISRA 19.4 */ /* <-SEC M1.8.2 */
+
+
+/**
+* @def  R_CUT_IF_ALWAYS
+* @brief  Whether a expression always true/false was cut or not.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    The value is 0 or 1.
+*    This macro is for @ref R_CUT_IF_ALWAYS_TRUE and @ref R_CUT_IF_ALWAYS_FALSE.
+*/
+#ifndef  R_CUT_IF_ALWAYS
+#if defined(__QAC_ARM_H__)
+#define  R_CUT_IF_ALWAYS  0
+#else
+#define  R_CUT_IF_ALWAYS  1
+#endif
+#endif
+
+
+/**
+* @def  R_CUT_IF_ALWAYS_TRUE
+* @brief  Assertion that the expression is always true
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if R_CUT_IF_ALWAYS
+#define  R_CUT_IF_ALWAYS_TRUE( expression_and )
+#else
+/* ->MISRA 19.10 : Can not in ( ). e.g. expression_and = " a >= 0  &&" */
+#define  R_CUT_IF_ALWAYS_TRUE( expression_and )  expression_and
+/* <-MISRA 19.10 */
+#endif
+
+
+/**
+* @def  R_CUT_IF_ALWAYS_FALSE
+* @brief  Assertion that the expression is always false
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if R_CUT_IF_ALWAYS
+#define  R_CUT_IF_ALWAYS_FALSE( expression_or )
+#else
+/* ->MISRA 19.10 : Can not in ( ). e.g. expression_and = " a >= 0  &&" */
+#define  R_CUT_IF_ALWAYS_FALSE( expression_or )  expression_or
+/* <-MISRA 19.10 */
+#endif
+
+
+/**
+* @def  R_UNREFERENCED_VARIABLE
+* @brief  Assertion that specified variable is not referenced
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoids warning of "set but never used".
+*/
+/* ->MISRA 19.7 : Argument must be any type */ /* ->SEC M5.1.3 */
+#define  R_UNREFERENCED_VARIABLE( a1 )  R_UNREFERENCED_VARIABLE_Sub( &(a1) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->QAC 3206 : Not used argument */
+INLINE void  R_UNREFERENCED_VARIABLE_Sub( volatile const void *a1 ) { }
+/* <-QAC 3206 */
+
+
+/**
+* @def  R_UNREFERENCED_VARIABLE_2
+* @brief  Assertion that specified variable is not referenced
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoids warning of "set but never used".
+*/
+/* ->MISRA 19.7 : Argument must be any type */ /* ->SEC M5.1.3 */
+#define  R_UNREFERENCED_VARIABLE_2( a1,a2 )  R_UNREFERENCED_VARIABLE_2_Sub( &(a1), &(a2) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->QAC 3206 : Not used argument */
+INLINE void  R_UNREFERENCED_VARIABLE_2_Sub( volatile const void *a1, volatile const void *a2 ) { }
+/* <-QAC 3206 */
+
+
+/**
+* @def  R_UNREFERENCED_VARIABLE_3
+* @brief  Assertion that specified variable is not referenced
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoids warning of "set but never used".
+*/
+/* ->MISRA 19.7 : Argument must be any type */ /* ->SEC M5.1.3 */
+#define  R_UNREFERENCED_VARIABLE_3( a1,a2,a3 )  R_UNREFERENCED_VARIABLE_3_Sub( &(a1), &(a2), &(a3) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->QAC 3206 : Not used argument */
+INLINE void  R_UNREFERENCED_VARIABLE_3_Sub( volatile const void *a1, volatile const void *a2,
+        volatile const void *a3 ) { }
+/* <-QAC 3206 */
+
+
+/**
+* @def  R_UNREFERENCED_VARIABLE_4
+* @brief  Assertion that specified variable is not referenced
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoids warning of "set but never used".
+*/
+/* ->MISRA 19.7 : Argument must be any type */ /* ->SEC M5.1.3 */
+#define  R_UNREFERENCED_VARIABLE_4( a1,a2,a3,a4 )  R_UNREFERENCED_VARIABLE_4_Sub( &(a1), &(a2), &(a3), &(a4) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->QAC 3206 : Not used argument */
+INLINE void  R_UNREFERENCED_VARIABLE_4_Sub( volatile const void *a1, volatile const void *a2,
+        volatile const void *a3, volatile const void *a4 ) { }
+/* <-QAC 3206 */
+
+
+/**
+* @def  R_IT_WILL_BE_NOT_CONST
+* @brief  variable WILL_BE_NOT_CONST
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoids MISRA 16.7 advisory and SEC M1.11.1 for not modified API argument
+*    will be not const future.
+*/
+/* ->MISRA 16.7 */ /* ->SEC M1.11.1 : Tell to QAC/compiler that "*Pointer" was changed */
+INLINE void  R_IT_WILL_BE_NOT_CONST( void *Pointer );  /* MISRA 8.1 Advice */
+INLINE void  R_IT_WILL_BE_NOT_CONST( void *Pointer )
+{
+    R_UNREFERENCED_VARIABLE( Pointer );
+}
+/* <-MISRA 16.7 */ /* <-SEC M1.11.1 */
+
+
+/**
+* @def  R_AVOID_UNSAFE_ALWAYS_WARNING
+* @brief  Specifies the code cannot be cut.
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This avoid MISRA 13.7 require always true/false condition.
+*    This tells to QAC/compiler that "Variable" was changed.
+*/
+/* ->MISRA 19.7 : Argument must be any type */ /* ->SEC M5.1.3 */
+#define  R_AVOID_UNSAFE_ALWAYS_WARNING( Variable ) \
+	R_AVOID_UNSAFE_ALWAYS_WARNING_SUB( &(Variable) )
+/* <-MISRA 19.7 */ /* <-SEC M5.1.3 */
+/* ->MISRA 16.7 : Tell to QAC/compiler that "Variable" was changed */ /* ->SEC M1.11.1 */
+INLINE void  R_AVOID_UNSAFE_ALWAYS_WARNING_SUB( void *Pointer );  /* MISRA 8.1 Advice */
+INLINE void  R_AVOID_UNSAFE_ALWAYS_WARNING_SUB( void *Pointer )
+/* <-MISRA 16.7 */ /* <-SEC M1.11.1 */
+{
+    R_UNREFERENCED_VARIABLE( Pointer );
+}
+
+
+/**
+* @def  TO_UNSIGNED
+* @brief  Cast to unsigned type constant value
+* @par Parameters
+*    None
+* @return  None.
+*/
+/* ->MISRA 19.7 : It is not able to replace to function because this expands macro's parameter */
+/* ->SEC M5.1.3 */
+#define  TO_UNSIGNED(x)  TO_UNSIGNED_AGAIN(x)  /* Expand "x" */
+/* <-MISRA 19.7 */
+/* <-SEC M5.1.3 */
+
+/* ->MISRA 19.13 */ /* ->SEC M5.1.2 (1) */
+#define  TO_UNSIGNED_AGAIN(x)  (x##u)
+/* <-MISRA 19.13 */ /* <-SEC M5.1.2 (1) */
+
+
+/**
+* @brief   Cast to unsigned type constant value
+*
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This can not avoid QAC warning. This macro is for count reviewed code automatically.
+*/
+INLINE uint32_t  R_ToUnsigned( int32_t const  ConstantInteger )
+{
+    return  (uint32_t) ConstantInteger;
+}
+
+
+/**
+* @brief   Cast to signed type constant value
+*
+* @par Parameters
+*    None
+* @return  None.
+*
+* @par Description
+*    This can not avoid QAC warning. This macro is for count reviewed code automatically.
+*/
+INLINE int32_t  R_ToSigned( uint32_t const  ConstantInteger )
+{
+    return  (int32_t) ConstantInteger;
+}
+
+
+/***********************************************************************
+* End of File:
+************************************************************************/
+#ifdef __cplusplus
+}  /* extern "C" */
+#endif /* __cplusplus */
+
+#endif /* R_STATIC_AN_TAG_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/porting/DebugBreak.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,79 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  DebugBreak.c
+* @brief   General Break Point
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#ifndef  R_OSPL_NDEBUG
+#include  <stdio.h>
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* Implement: R_DebugBreak
+************************************************************************/
+void  R_DebugBreak( const char_t *const  File, int_fast32_t const  Line )
+{
+#ifndef  R_OSPL_NDEBUG
+    if ( File == NULL ) {
+        printf( "in R_DebugBreak errnum_t:0x%X\n", Line );
+    } else {
+        printf( "in R_DebugBreak (%d) %s\n", Line, File );
+    }
+#else
+    R_UNREFERENCED_VARIABLE_2( File, Line );
+#endif
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/porting/TOOLCHAIN_ARM/r_ospl_os_less_asm.s	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,152 @@
+;/*******************************************************************************
+;* DISCLAIMER
+;* This software is supplied by Renesas Electronics Corporation and is only
+;* intended for use with Renesas products. No other uses are authorized. This
+;* software is owned by Renesas Electronics Corporation and is protected under
+;* all applicable laws, including copyright laws.
+;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+;* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+;* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+;* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+;* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+;* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+;* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+;* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+;* Renesas reserves the right, without notice, to make changes to this software
+;* and to discontinue the availability of this software. By using this software,
+;* you agree to the additional terms and conditions found by accessing the
+;* following link:
+;* http://www.renesas.com/disclaimer
+;* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+;*******************************************************************************/
+;/*******************************************************************************
+;* $FileName: r_ospl_os_less_asm.s $
+;* $Module: OSPL $ $PublicVersion: 0.84 $ (=R_OSPL_VERSION)
+;* $Rev: 35 $
+;* $Date:: 2014-04-15 21:38:18 +0900#$
+;* Description : OS Porting Layer API
+;******************************************************************************/
+
+
+	AREA    |.text|, CODE, READONLY
+
+
+;/******************************************************************************
+;* Function Name: [R_OSPL_MEMORY_Flush_Sub]
+;* Description  :
+;* Arguments    : None
+;* Return Value : None
+;******************************************************************************/
+
+	EXPORT  R_OSPL_MEMORY_Flush_Sub
+
+R_OSPL_MEMORY_Flush_Sub    FUNCTION
+
+	ARM
+
+	PUSH    {r4-r7}
+
+	MRC     p15, 1, r7, c0, c0, 1   ;// r7 = p15(CLIDR);  // [r4] CLIDR(LoC) * 2  // LoC: level of coherency
+	MOV     r4, r7, LSR #23         ;// r4 = r7 >> 23;    //   :
+	ANDS    r4, r4, #0xE            ;// r4 &= 0xE;        //   :
+	BEQ     Fin                     ;// if ( r4 == 0 ) goto Fin;  // if LoC == 0, no need to clean
+
+	MOV     r3, #0                  ;// for ( r3 = 0;  r3 < r4;  r3 += 2 ) { // [r3]: current_cache_level * 2
+Loop1
+	ADD     r2, r3, r3, LSR #1      ;// r2 = r3 + (r3 >> 1);  // r2 = current_cache_level * 3
+	MOV     r0, r7, LSR r2          ;// r0 = (r7 >> r2);  // r0 = CLIDR(Ctype#)
+	AND     r0, r0, #7              ;// r0 &= 7;          //  :
+	CMP     r0, #2                  ;// if ( r0 < 2 ) goto Continue1;
+	BLT     Continue1               ;//  :        // If no cache or only instruction cache at this level
+
+	MCR     p15, 2, r3, c0, c0, 0   ;// p15(CSSELR) = r3;    // CSSELR: Cache Size Selection Register
+	ISB                             ;// Guarantee MCR operation
+	MRC     p15, 1, r0, c0, c0, 0   ;// r0 = p15(CCSIDR);    // CCSIDR: Cache Size ID Registers
+	AND     r6, r0, #7              ;// r6 = r0 & 7;         // CCSIDR(LineSize): log2(cache_line_byte)-4
+	ADD     r6, r6, #4              ;// r6 += 4;             // [r6] log2(cache_line_byte)
+	LDR     r7, =0x3FF              ;// r7 = 0x3FF;          // [r7] CCSIDR(Associativity): associativity_value - 1
+	AND     r7, r7, r0, LSR #3      ;// r7 = r7 & r0 >> 3;   //   :
+	CLZ     r5, r7                  ;// r5 = CLZ( r7 );      // [r5] log2(WaySize), if exponential 2
+	LDR     r2, =0x7FFF             ;// r2 = 0x7FFF;         // CCSIDR(NumSets) : max number of the index size - 1
+	AND     r2, r2, r0, LSR #13     ;// r2 = r2 & r0 >> 13;  //  :
+	                                ;// for ( /*r2*/;   r2 >= 0;  r2 -= 1 ) {  // [r2] Set number
+Loop2
+	MOV     r1, r7                  ;// for ( r1 = r7;  r1 >= 0;  r1 -= 1 ) {  // [r1] Way number
+Loop3
+	ORR     r0, r3, r1, LSL r5      ;//     r0 = r3 | (r1 << r5)
+	ORR     r0, r0, r2, LSL r6      ;//             | (r2 << r6);
+	MCR     p15, 0, r0, c7, c14, 2  ;//     p15(DCCISW) = r0;  // Clean(WriteBack) and Invalidate
+	SUBS    r1, r1, #1              ;// }  /* End of r1 loop */
+	BGE     Loop3                   ;//  :
+	SUBS    r2, r2, #1              ;// }  /* End of r2 loop */
+	BGE     Loop2                   ;//  :
+Continue1
+	ADD     r3, r3, #2              ;// }  /* End of r3 loop */
+	CMP     r4, r3                  ;//  :
+	BGT     Loop1                   ;//  :
+
+Fin
+	DSB
+	POP    {r4-r7}
+	BX     lr
+
+	ENDFUNC
+
+
+;/******************************************************************************
+;* Function Name: [R_OSPL_MEMORY_GetCacheLineSize]
+;* Description  :
+;* Arguments    : None
+;* Return Value : None
+;******************************************************************************/
+
+	EXPORT  R_OSPL_MEMORY_GetCacheLineSize
+
+R_OSPL_MEMORY_GetCacheLineSize    FUNCTION
+
+	ARM
+
+	MRC     p15, 1, r0, c0, c0, 0   ;// r0 = p15(CCSIDR);    // CCSIDR: Cache Size ID Registers
+	AND     r0, r0, #7              ;// r0 = r0 & 7;         // CCSIDR.LineSize: log2(cache_line_byte)-4
+	ADD     r0, r0, #4              ;// r0 += 4;             //
+	MOV     r1, #1                  ;// r0 = 1 << r0;        // [r0] cache_line_byte
+	MOV     r0, r1, LSL r0          ;    :
+
+	BX     lr
+
+	ENDFUNC
+
+
+;/******************************************************************************
+;* Function Name: [R_OSPL_MEMORY_RangeFlush_Sub]
+;* Description  :
+;* Arguments    : r0: Start address
+;*              : r1: Over address (Last + 1)
+;*              : r2: Cache line size
+;* Return Value : None
+;******************************************************************************/
+
+	EXPORT  R_OSPL_MEMORY_RangeFlush_Sub
+
+R_OSPL_MEMORY_RangeFlush_Sub    FUNCTION
+
+	ARM
+
+Loop
+	CMP     r0, r1                  ;// for ( r0 = r0;  r0 < r1;  r0 += r2 ) {
+	BGE     Fin2                    ;//  :
+	MCR     p15, 0, r0, c7, c6, 1   ;//     p15(DCIMVAC) = r0;  // Invalidate
+	ADD     r0, r0, r2              ;// }
+	B       Loop                    ;//  :
+Fin2
+	DSB
+	BX     lr
+
+	ENDFUNC
+
+	END
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/porting/inline_body.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,40 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  inline_body.c
+* @brief   Body of inline functions
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+#define  R_OSPL_MAKE_INLINE_BODY
+#include  "Project_Config.h"
+#include  "r_ospl.h"
+#include  "iodefine.h" /* for inline function in "clib_registers.h" */
+#include  "clib_registers.h"
+#include  "clib_drivers.h"
+#include  "window_surfaces.h"
+#include  "RGA_Port.h"
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/porting/locking.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,394 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  locking.c
+* @brief   Lock related FIT BSP.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#if R_OSPL_IS_PREEMPTION
+#include  "r_ospl_RTX_private.h"
+#endif
+#if IS_RZ_A1_BSP_USED
+#include  "dma_if.h"  /* R_DMA_Alloc */
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/** gs_ospl_mutex */
+#if R_OSPL_IS_PREEMPTION
+static osMutexId  gs_ospl_mutex;  /* gs_OSPL_Mutex */
+#endif
+
+
+/** g_bsp_Locks */
+BSP_CFG_USER_LOCKING_TYPE  g_bsp_Locks[ BSP_NUM_LOCKS ];
+
+
+/***********************************************************************
+* Implement: R_BSP_HardwareLock
+************************************************************************/
+bool_t  R_BSP_HardwareLock( mcu_lock_t const  HardwareIndex )
+{
+#if BSP_CFG_USER_LOCKING_ENABLED
+    return  BSP_CFG_USER_LOCKING_HW_LOCK_FUNCTION( HardwareIndex );
+#else
+    bool_t  is_success;
+
+
+#if IS_RZ_A1_BSP_USED
+    if ( HardwareIndex >= BSP_LOCK_DMAC0  &&  HardwareIndex <= BSP_LOCK_DMAC15 ) {
+        int_fast32_t  channel_of_DMAC = HardwareIndex - BSP_LOCK_DMAC0;
+
+        channel_of_DMAC = R_DMA_Alloc( channel_of_DMAC, NULL );
+        IF ( channel_of_DMAC == -1 ) {
+            is_success = false;
+            goto fin;
+        }
+
+        is_success = true;
+        goto fin;
+    }
+#endif
+
+    IF_D ( R_CUT_IF_ALWAYS_FALSE( HardwareIndex < 0u  ||)  HardwareIndex >= R_COUNT_OF( g_bsp_Locks ) ) {
+        is_success = false;
+        goto fin;
+    }
+
+    is_success = R_BSP_SoftwareLock( &g_bsp_Locks[ HardwareIndex ] );
+    IF ( ! is_success ) {
+        goto fin;
+    }
+
+    is_success = true;
+fin:
+    return  is_success;
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_LockUnlockedChannel
+************************************************************************/
+#if ! BSP_CFG_USER_LOCKING_ENABLED
+errnum_t  R_OSPL_LockUnlockedChannel( int_fast32_t *out_ChannelNum,
+                                      mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax )
+{
+    errnum_t    e;
+    mcu_lock_t  hardware_index;
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+
+#if R_OSPL_IS_PREEMPTION
+    if ( R_OSPL_THREAD_GetCurrentId() == NULL ) {  /* If interrrupt context */
+        e = E_NOT_THREAD;
+        goto fin;
+    }
+    e= R_OSPL_Start_T_Lock();
+    if ( e != 0 ) {
+        R_OSPL_RaiseUnrecoverable( e );
+        goto fin;
+    }
+    is_lock = true;  /* T-Lock to "self" */
+#endif
+
+
+#if IS_RZ_A1_BSP_USED
+    if ( HardwareIndexMin == BSP_LOCK_DMAC0 ) {
+        int_fast32_t  channel_of_DMAC;
+
+        channel_of_DMAC = R_DMA_Alloc( DMA_ALLOC_CH, NULL );
+        IF ( channel_of_DMAC == -1 ) {
+            e = E_FEW_ARRAY;
+            goto fin;
+        }
+
+        *out_ChannelNum = channel_of_DMAC;
+        e = 0;
+        goto fin;
+    }
+#endif
+
+
+    for ( hardware_index = HardwareIndexMin;  hardware_index <= HardwareIndexMax;
+            hardware_index += 1 ) {
+        r_ospl_c_lock_t  *lock = &g_bsp_Locks[ hardware_index ];
+
+        if ( ! lock->IsLocked ) {
+            lock->IsLocked = true;
+            break;
+        }
+    }
+    IF ( hardware_index > HardwareIndexMax ) {
+        e=E_FEW_ARRAY;
+        goto fin;
+    }
+
+
+    *out_ChannelNum = hardware_index - HardwareIndexMin;
+
+
+    e=0;
+fin:
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+
+    return  e;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_BSP_HardwareUnlock
+************************************************************************/
+bool_t  R_BSP_HardwareUnlock( mcu_lock_t const  HardwareIndex )
+{
+#if BSP_CFG_USER_LOCKING_ENABLED
+    return  BSP_CFG_USER_LOCKING_HW_UNLOCK_FUNCTION( HardwareIndex );
+#else
+    bool_t  is_success;
+
+
+#if IS_RZ_A1_BSP_USED
+    if ( HardwareIndex >= BSP_LOCK_DMAC0  &&  HardwareIndex <= BSP_LOCK_DMAC15 ) {
+        int_fast32_t  channel_of_DMAC = HardwareIndex - BSP_LOCK_DMAC0;
+        int_fast32_t  err2;
+
+        err2 = R_DMA_Free( channel_of_DMAC, NULL );
+        IF ( err2 != ESUCCESS ) {
+            is_success = false;
+            goto fin;
+        }
+
+        is_success = true;
+        goto fin;
+    }
+#endif
+
+
+    IF_D ( R_CUT_IF_ALWAYS_FALSE( HardwareIndex < 0u  ||)  HardwareIndex >= R_COUNT_OF( g_bsp_Locks ) ) {
+        is_success = false;
+        R_OSPL_RaiseUnrecoverable( E_FEW_ARRAY );
+        goto fin;
+    }
+
+    is_success = R_BSP_SoftwareUnlock( &g_bsp_Locks[ HardwareIndex ] );
+    IF ( ! is_success ) {
+        goto fin;
+    }
+
+    is_success = true;
+fin:
+    return  is_success;
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_SoftwareLock
+************************************************************************/
+bool_t  R_BSP_SoftwareLock( BSP_CFG_USER_LOCKING_TYPE *const  LockObject )
+{
+#if BSP_CFG_USER_LOCKING_ENABLED
+    return  BSP_CFG_USER_LOCKING_SW_LOCK_FUNCTION( LockObject );
+#else
+    errnum_t  e;
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+
+#if R_OSPL_IS_PREEMPTION
+    if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+        e= R_OSPL_Start_T_Lock();
+        IF(e!=0) {
+            goto fin;
+        }
+        is_lock = true;  /* T-Lock to "self" */
+    }
+#endif
+
+
+    e= R_OSPL_C_LOCK_Lock( LockObject );
+    if ( e == E_ACCESS_DENIED ) {
+        R_OSPL_CLEAR_ERROR();
+        goto fin;
+    }
+    IF(e) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+
+    return  (bool_t)( e == 0 );
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_SoftwareUnlock
+************************************************************************/
+bool_t  R_BSP_SoftwareUnlock( BSP_CFG_USER_LOCKING_TYPE *const  LockObject )
+{
+#if BSP_CFG_USER_LOCKING_ENABLED
+    return  BSP_CFG_USER_LOCKING_SW_UNLOCK_FUNCTION( LockObject );
+#else
+    errnum_t  e;
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+
+#if R_OSPL_IS_PREEMPTION
+    if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+        e= R_OSPL_Start_T_Lock();
+        IF ( e != 0 ) {
+            R_OSPL_RaiseUnrecoverable( e );
+            goto fin;
+        }
+        is_lock = true;  /* T-Lock to "self" */
+    }
+#endif
+
+
+    e= R_OSPL_C_LOCK_Unlock( LockObject );
+    if ( e == E_ACCESS_DENIED ) {
+        R_OSPL_CLEAR_ERROR();
+        goto fin;
+    }
+    IF(e) {
+        goto fin;
+    }
+
+    e=0;
+fin:
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+
+    return  (bool_t)( e == 0 );
+#endif
+}
+
+
+/**
+* @brief   The function callbacked from OSPL internal, when T-Lock started
+*
+* @par Parameters
+*    None
+* @return  Error Code. 0=No Error.
+*/
+#if R_OSPL_IS_PREEMPTION
+errnum_t  R_OSPL_Start_T_Lock(void)
+{
+    errnum_t  e;
+    osStatus  es;
+
+    static osMutexDef( gs_ospl_mutex );
+
+    if ( gs_ospl_mutex == NULL ) {
+        gs_ospl_mutex = osMutexCreate( osMutex( gs_ospl_mutex ) );
+        if ( gs_ospl_mutex == NULL ) {
+            e=E_OTHERS;
+            goto fin;
+        }
+    }
+
+    es= osMutexWait( gs_ospl_mutex, TO_UNSIGNED( osWaitForever ) );
+    if ( es == osErrorISR ) {
+        es = osOK;
+    }
+    if ( es != osOK ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+#endif
+
+
+/**
+* @brief   The function callbacked from OSPL internal, when T-Lock ended
+*
+* @par Parameters
+*    None
+* @return  None
+*/
+#if R_OSPL_IS_PREEMPTION
+void  R_OSPL_End_T_Lock(void)
+{
+    if ( gs_ospl_mutex != NULL ) {
+        osStatus  rs;
+
+        rs= osMutexRelease( gs_ospl_mutex );
+        if ( rs == osErrorISR ) {
+            rs = osOK;
+        }
+        ASSERT_R( rs == osOK,  R_OSPL_RaiseUnrecoverable( E_OTHERS ) );
+    }
+}
+#endif
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/porting/mcu_interrupts.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,148 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  mcu_interrupts.c
+* @brief   Interrupt related FIT BSP.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "mcu_interrupts.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* Implement: R_BSP_InterruptWrite
+************************************************************************/
+bsp_int_err_t  R_BSP_InterruptWrite( bsp_int_src_t const  in_IRQ_Num,  bsp_int_cb_t const  in_Callback )
+{
+    uint32_t       er;
+    bsp_int_err_t  eb;
+    IRQn_Type      irq;  /* QAC 3441 */
+
+    if ( in_Callback == FIT_NO_FUNC ) {
+        irq = R_CAST_bsp_int_src_t_to_IRQn_Type( in_IRQ_Num );
+        er= InterruptHandlerUnregister( irq );
+        IF ( er != 0u ) {
+            eb=BSP_INT_ERR_INVALID_ARG;
+            goto fin;
+        }
+    } else {
+        irq = R_CAST_bsp_int_src_t_to_IRQn_Type( in_IRQ_Num );  /* QAC 3441 */
+        er= InterruptHandlerRegister( irq, in_Callback );
+        IF ( er != 0u ) {
+            eb=BSP_INT_ERR_INVALID_ARG;
+            goto fin;
+        }
+    }
+
+    eb = BSP_INT_SUCCESS;
+fin:
+    return  eb;
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_InterruptRead
+************************************************************************/
+bsp_int_err_t  R_BSP_InterruptRead( bsp_int_src_t const  in_IRQ_Num,  bsp_int_cb_t *const  out_Callback )
+{
+    R_UNREFERENCED_VARIABLE_2( in_IRQ_Num, out_Callback );
+    return  BSP_INT_ERR_UNSUPPORTED;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_OnInterruptForUnregistered
+************************************************************************/
+void  R_OSPL_OnInterruptForUnregistered( uint32_t const  int_sense )
+{
+    R_UNREFERENCED_VARIABLE( int_sense );
+    R_OSPL_RaiseUnrecoverable( E_OTHERS );
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_InterruptControl
+************************************************************************/
+bsp_int_err_t  R_BSP_InterruptControl( bsp_int_src_t const  in_IRQ_Num,  bsp_int_cmd_t const  in_Command,
+                                       void *const  in_NotUsed )
+{
+    bsp_int_err_t  eb;
+    IRQn_Type      irq;  /* QAC 3441 */
+
+    R_UNREFERENCED_VARIABLE( in_NotUsed );
+    R_IT_WILL_BE_NOT_CONST( in_NotUsed );
+
+    switch ( in_Command ) {
+        case  BSP_INT_CMD_INTERRUPT_ENABLE:
+
+            irq = R_CAST_bsp_int_src_t_to_IRQn_Type( in_IRQ_Num );
+            GIC_EnableIRQ( irq );
+            break;
+
+        default:
+            IF_DS( in_Command != BSP_INT_CMD_INTERRUPT_DISABLE ) {
+                eb=BSP_INT_ERR_INVALID_ARG;
+                goto fin;
+            }
+
+            irq = R_CAST_bsp_int_src_t_to_IRQn_Type( in_IRQ_Num );
+            GIC_DisableIRQ( irq );
+            break;
+    }
+
+    eb = BSP_INT_SUCCESS;
+fin:
+    return  eb;
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/porting/r_ospl_RTX.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,529 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_RTX.c
+* @brief   OS Porting Layer API for RTX
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "r_ospl_os_less_private.h"
+#include  "r_ospl_private.h"
+#include  "pl310.h"  /* 2nd cache */
+#if R_OSPL_IS_PREEMPTION
+#include  "cmsis_os.h"
+#include  "gic.h"
+#include  "r_ospl_RTX_private.h"
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/**
+* @def  OS_ERROR_SIGNAL
+* @brief  CMSIS-RTOS defined immediate value
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  OS_ERROR_SIGNAL  0x80000000
+
+
+/**
+* @def  R_OSPL_EVENT_WATCH
+* @brief  Debug tool
+* @par Parameters
+*    None
+* @return  None.
+*/
+#define  R_OSPL_EVENT_WATCH  0  /* [R_OSPL_EVENT_WATCH] 0 or 1 */
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* Implement: R_OSPL_Initialize
+************************************************************************/
+errnum_t  R_OSPL_Initialize( const void *const  in_NullConfig )
+{
+    R_UNREFERENCED_VARIABLE( in_NullConfig );
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_THREAD_GetCurrentId
+************************************************************************/
+r_ospl_thread_id_t  R_OSPL_THREAD_GetCurrentId(void)
+{
+    return  osThreadGetId();
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_EVENT_Set
+************************************************************************/
+void  R_OSPL_EVENT_Set( r_ospl_thread_id_t const  ThreadId,  bit_flags32_t const  SetFlags )
+{
+    int32_t  ret;
+
+    if ( ThreadId != NULL ) {
+#if  R_OSPL_EVENT_WATCH
+        R_D_AddToIntLog( 0x70100000 + SetFlags );
+        R_D_AddToIntLog( (uintptr_t) R_OSPL_THREAD_GetCurrentId() );
+        R_D_AddToIntLog( (uintptr_t) ThreadId );
+#endif
+
+        ret = osSignalSet( (osThreadId) ThreadId, (int32_t) SetFlags );
+        ASSERT_D( (ret & OS_ERROR_SIGNAL) == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( ret );  /* for Release configuration */
+    }
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_EVENT_Clear
+************************************************************************/
+void  R_OSPL_EVENT_Clear( r_ospl_thread_id_t const  ThreadId,  bit_flags32_t const  ClearFlags1 )
+{
+    int32_t  ret;
+
+    if ( ThreadId != NULL ) {
+        IF_D( ( ClearFlags1 & ~0xFFFF ) != 0 ) {
+            R_NOOP();
+        }
+
+#if  R_OSPL_EVENT_WATCH
+        R_D_AddToIntLog( 0x70C00000 + ClearFlags1 );
+        R_D_AddToIntLog( (uintptr_t) R_OSPL_THREAD_GetCurrentId() );
+        R_D_AddToIntLog( (uintptr_t) ThreadId );
+#endif
+
+        ret = osSignalClear( (osThreadId) ThreadId, (int32_t) ClearFlags1 );
+        /* "& 0xFFFF" is for avoiding error in osSignalClear */
+        ASSERT_D( (ret & OS_ERROR_SIGNAL) == 0,  R_NOOP() );
+        R_UNREFERENCED_VARIABLE( ret );  /* for Release configuration */
+    }
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_EVENT_Get
+************************************************************************/
+#if ( ! defined( osCMSIS )  ||  osCMSIS <= 0x10001 ) &&  R_OSPL_VERSION < 85
+bit_flags32_t  R_OSPL_EVENT_Get( r_ospl_thread_id_t const  ThreadId )
+{
+    int32_t  ret;
+
+    if ( ThreadId == NULL ) {
+        ret = 0;
+    } else {
+        ret = osSignalGet( (osThreadId) ThreadId );
+        ASSERT_D( (ret & OS_ERROR_SIGNAL) == 0,  R_NOOP() );
+    }
+
+    return  (bit_flags32_t) ret;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_EVENT_Wait
+************************************************************************/
+errnum_t  R_OSPL_EVENT_Wait( bit_flags32_t const  WaigingFlags,  bit_flags32_t *const  out_GotFlags,
+                             uint32_t const  Timeout_msec )
+{
+    errnum_t  e;
+    osEvent   event;
+
+    R_STATIC_ASSERT( R_OSPL_INFINITE == TO_UNSIGNED( osWaitForever ), "" );
+
+#if  R_OSPL_EVENT_WATCH
+    R_D_AddToIntLog( 0x70BE0000 + WaigingFlags );
+    R_D_AddToIntLog( (uintptr_t) R_OSPL_THREAD_GetCurrentId() );
+
+    {
+        static int tc;
+        if ( R_D_Counter( &tc, 0, NULL ) ) {
+            R_DEBUG_BREAK();
+        }
+    }
+#endif
+
+
+    event = osSignalWait( (int32_t) WaigingFlags, Timeout_msec );
+
+
+#if  R_OSPL_EVENT_WATCH
+    R_D_AddToIntLog( 0x70AF0000 );
+    R_D_AddToIntLog( (uintptr_t) R_OSPL_THREAD_GetCurrentId() );
+#endif
+
+    if ( (event.status == osOK) || (event.status == osEventTimeout) ) {
+        if ( out_GotFlags != NULL ) {
+            *out_GotFlags = R_OSPL_TIMEOUT;
+        }
+        IF ( event.status == osEventTimeout ) {
+            e=E_TIME_OUT;
+            goto fin;
+        }
+    } else {
+        ASSERT_R( event.status == osEventSignal,  e=E_OTHERS;  goto fin );
+
+        if ( out_GotFlags != NULL ) {
+            *out_GotFlags = (bit_flags32_t) event.value.signals;
+        }
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_SetInterruptPriority
+************************************************************************/
+errnum_t  R_OSPL_SetInterruptPriority( bsp_int_src_t const  IRQ_Num, int_fast32_t const  Priority )
+{
+    GIC_SetPriority( IRQ_Num, (uint32_t) Priority );
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_MEMORY_Flush
+************************************************************************/
+void  R_OSPL_MEMORY_Flush( r_ospl_flush_t const  FlushType )
+{
+    if ( FlushType == R_OSPL_FLUSH_WRITEBACK_INVALIDATE ) {
+#if 0
+        printf( "L1Flush\n" );
+#endif
+
+#if IS_RTX_USED
+        __v7_clean_inv_dcache_all();
+#else
+#error
+#endif
+    } else if ( FlushType == R_OSPL_FLUSH_WRITEBACK_INVALIDATE_2ND ) {
+#if 0
+        printf( "PL310Flush\n" );
+#endif
+
+        PL310_CleanInvAllByWay();
+    } else {
+        ASSERT_D( false,  R_NOOP() );
+    }
+}
+
+
+/**
+* @brief   R_OSPL_Is1bitOnly_Fast32_Sub
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#ifndef  R_OSPL_NDEBUG
+static bool_t  R_OSPL_Is1bitOnly_Fast32_Sub( uint_fast32_t Value )
+{
+    if ( (Value & 0x0000FFFFu) == 0 ) {
+        Value >>= 16;
+    }
+    if ( (Value & 0x000000FFu) == 0 ) {
+        Value >>=  8;
+    }
+    if ( (Value & 0x0000000Fu) == 0 ) {
+        Value >>=  4;
+    }
+    if ( (Value & 0x00000003u) == 0 ) {
+        Value >>=  2;
+    }
+    if ( (Value & 0x00000001u) == 0 ) {
+        Value >>=  1;
+    }
+    return  ( Value == 1 );
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_MEMORY_RangeFlush
+************************************************************************/
+errnum_t  R_OSPL_MEMORY_RangeFlush( r_ospl_flush_t const  FlushType,
+                                    const void *const  StartAddress,  size_t const  Length )
+{
+    errnum_t   e;
+    size_t     cache_line_size;
+    size_t     cache_line_mask;
+    uintptr_t  start;
+    uintptr_t  over;
+
+    ASSERT_R( FlushType == R_OSPL_FLUSH_INVALIDATE,  e=E_BAD_COMMAND_ID; goto fin );
+
+    cache_line_size = R_OSPL_MEMORY_GetCacheLineSize();
+    cache_line_mask = cache_line_size - 1u;
+    ASSERT_D( R_OSPL_Is1bitOnly_Fast32_Sub( cache_line_size ), e=E_OTHERS; goto fin );
+
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    ASSERT_R( ( (uintptr_t) StartAddress & cache_line_mask ) == 0u, e=E_OTHERS; goto fin );
+    ASSERT_R( ( Length & cache_line_mask ) == 0u, e=E_OTHERS; goto fin );
+
+    start = (uintptr_t) StartAddress;
+    over  = ((uintptr_t) StartAddress + Length) - 1u;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+
+    R_OSPL_MEMORY_RangeFlush_Sub( start, over, cache_line_size );
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_MEMORY_GetSpecification
+************************************************************************/
+void  R_OSPL_MEMORY_GetSpecification( r_ospl_memory_spec_t *const  out_MemorySpec )
+{
+    IF_DQ( out_MemorySpec == NULL ) {
+        goto fin;
+    }
+
+    out_MemorySpec->CacheLineSize = R_OSPL_MEMORY_GetCacheLineSize();
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_Delay
+************************************************************************/
+errnum_t  R_OSPL_Delay( uint32_t const  DelayTime_msec )
+{
+    errnum_t  e;
+    osStatus  rs;
+    bool_t const    is_overflow = ( DelayTime_msec > R_OSPL_MAX_TIME_OUT );
+    uint32_t const  delay_parameter = DelayTime_msec + 1u;
+
+    ASSERT_D( ! is_overflow, R_NOOP() );
+    /* RTX 5.16: If delay_parameter = 100000, "osDelay" waits 65534 */
+
+    rs= osDelay( delay_parameter );
+    IF ( rs == osErrorISR ) {
+        e=E_NOT_THREAD;
+        R_OSPL_RaiseUnrecoverable( e );
+        goto fin;
+    }
+    IF ( IS( is_overflow ) ) {
+        e=E_TIME_OUT;
+        goto fin;
+    }
+
+    IF (
+        (rs != osOK) &&           /* for delay_parameter == 0 */
+        (rs != osEventTimeout) ) { /* for delay_parameter != 0 */
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_Create
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_Create( r_ospl_queue_t **out_self, r_ospl_queue_def_t *QueueDefine )
+{
+    errnum_t  e;
+    r_ospl_queue_t  *self = QueueDefine;
+
+    self->MailQId = osMailCreate( (osMailQDef_t *) QueueDefine->MailQDef, NULL );
+    IF ( self->MailQId == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    self->PublicStatus.UsedCount = 0;
+
+    *out_self = self;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_GetStatus
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_GetStatus( r_ospl_queue_t *self,  const r_ospl_queue_status_t **out_Status )
+{
+    *out_Status = &self->PublicStatus;
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_Allocate
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_Allocate( r_ospl_queue_t *self,  void *out_Address,  uint32_t Timeout_msec )
+{
+    errnum_t  e;
+    void     *address;
+    bool_t    was_all_enabled = false;
+
+    address = osMailAlloc( self->MailQId, Timeout_msec );
+    *(void **) out_Address = address;
+    IF ( address == NULL  &&  Timeout_msec > 0 ) {
+        if ( R_OSPL_THREAD_GetCurrentId() == NULL ) {
+            e=E_NOT_THREAD;
+        } else {
+            e=E_TIME_OUT;
+        }
+        goto fin;
+    }
+
+    was_all_enabled = R_OSPL_DisableAllInterrupt();
+    self->PublicStatus.UsedCount += 1;
+
+    e=0;
+fin:
+    if ( was_all_enabled ) {
+        R_OSPL_EnableAllInterrupt();
+    }
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_Put
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_Put( r_ospl_queue_t *self,  void *Address )
+{
+    errnum_t  e;
+    osStatus  status;
+
+    status = osMailPut( self->MailQId, Address );
+    IF ( status != osOK ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_Get
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_Get( r_ospl_queue_t *self,  void *out_Address,  uint32_t Timeout_msec )
+{
+    errnum_t  e;
+    osEvent   event;
+
+    event = osMailGet( self->MailQId, Timeout_msec );
+
+    if ( event.status != osOK ) {
+        IF ( event.status != osEventMail ) {
+            if ( event.status == osEventTimeout ) {
+                e = E_TIME_OUT;
+            } else if ( event.status == osErrorParameter ) {
+                if ( R_OSPL_THREAD_GetCurrentId() == NULL ) {
+                    e = E_NOT_THREAD;
+                } else {
+                    e = E_OTHERS;
+                }
+            } else {
+                e = E_OTHERS;
+            }
+            goto fin;
+        }
+    }
+
+    *(void **) out_Address = event.value.p;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_QUEUE_Free
+************************************************************************/
+errnum_t  R_OSPL_QUEUE_Free( r_ospl_queue_t *self,  void *Address )
+{
+    errnum_t  e;
+    osStatus  status;
+    bool_t    was_all_enabled = false;
+
+    status = osMailFree( self->MailQId, Address );
+    IF ( status != osOK ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    was_all_enabled = R_OSPL_DisableAllInterrupt();
+    self->PublicStatus.UsedCount -= 1;
+
+    e=0;
+fin:
+    if ( was_all_enabled ) {
+        R_OSPL_EnableAllInterrupt();
+    }
+    return  e;
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/porting/r_ospl_debug.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,187 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_debug.c
+* @brief   Debug tools provided by OSPL.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "r_ospl_debug.h"
+#if R_OSPL_DEBUG_TOOL
+#include  <stdio.h>
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  r_ospl_debug_watch4_t
+* @brief  Watch context
+*
+* @par Description
+*    Member variables should not be accessed.
+*/
+#if R_OSPL_DEBUG_TOOL
+typedef struct st_r_ospl_debug_watch4_t  r_ospl_debug_watch4_t;
+struct st_r_ospl_debug_watch4_t {
+    volatile const uint32_t  *Address;
+    uint32_t  BreakValue;
+    bool_t    IsPrintf;
+};
+static r_ospl_debug_watch4_t  g_r_ospl_debug_watch4[ 10 ];
+#endif
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* Implement: R_D_Add
+************************************************************************/
+#if R_OSPL_DEBUG_TOOL
+void  R_D_Add( int_fast32_t IndexNum, volatile const void *in_Address, uint32_t BreakValue, bool_t IsPrintf )
+{
+    r_ospl_debug_watch4_t  *self = &g_r_ospl_debug_watch4[ IndexNum ];
+    bool_t                  was_all_enabled; /* = false; */ /* QAC 3197 */
+    int_t                   r;
+
+    was_all_enabled = R_OSPL_DisableAllInterrupt();
+
+    if ( IS( IsPrintf ) ) {
+        r= printf( "Debug_add( %d, 0x%08X )\n", IndexNum, (uintptr_t) in_Address );
+        R_UNREFERENCED_VARIABLE( r ); /* QAC 3200 : This is not error information */
+    }
+    self->Address = (uint32_t *) in_Address;
+    self->BreakValue = BreakValue;
+    self->IsPrintf = IsPrintf;
+
+    if ( IS( was_all_enabled ) ) {
+        R_OSPL_EnableAllInterrupt();
+    }
+}
+#endif  /* R_OSPL_DEBUG_TOOL */
+
+
+/***********************************************************************
+* Implement: R_D_Watch
+************************************************************************/
+#if R_OSPL_DEBUG_TOOL
+void  R_D_Watch( int_fast32_t in_IndexNum )
+{
+    r_ospl_debug_watch4_t  *self = &g_r_ospl_debug_watch4[ in_IndexNum ];
+    bool_t                  was_all_enabled; /* = false; */ /* QAC 3197 */
+    int_t                   r;
+
+    was_all_enabled = R_OSPL_DisableAllInterrupt();
+
+    if ( self->Address != NULL ) {
+        if ( IS( self->IsPrintf ) ) {
+            r= printf( "Debug_watch( %d ): 0x%08X\n", in_IndexNum, (uintptr_t) *self->Address );
+            R_UNREFERENCED_VARIABLE( r ); /* QAC 3200 : This is not error information */
+            /* Cast of "uintptr_t" is for avoiding "format" warning of GNU_ARM */
+        }
+        if ( *self->Address == self->BreakValue ) {
+            R_DEBUG_BREAK();
+        }
+    }
+
+    if ( IS( was_all_enabled ) ) {
+        R_OSPL_EnableAllInterrupt();
+    }
+}
+#endif  /* R_OSPL_DEBUG_TOOL */
+
+
+/***********************************************************************
+* Implement: R_D_AddToIntLog
+************************************************************************/
+#if R_OSPL_DEBUG_TOOL
+#define  IntLogBreakID  -1   /* -1=not break */
+
+volatile uint_fast32_t  g_DebugVar[ g_DebugVarCount ];
+volatile int_fast32_t   g_IntLog[ g_IntLogCount ];
+volatile int_fast32_t   g_IntLogLength;
+
+void  R_D_AddToIntLog( int_fast32_t in_Value )  /* Add to g_IntLog, g_IntLogLength */
+{
+    g_IntLog[ (uint_fast32_t) g_IntLogLength % ( sizeof(g_IntLog) / sizeof(*g_IntLog) ) ] = in_Value;
+    if ( g_IntLogLength == IntLogBreakID ) {
+        R_DEBUG_BREAK();
+    }
+    g_IntLogLength += 1;
+}
+#endif  /* R_OSPL_DEBUG_TOOL */
+
+
+/***********************************************************************
+* Implement: R_D_Counter
+************************************************************************/
+#if R_OSPL_DEBUG_TOOL
+bool_t  R_D_Counter( int_fast32_t *in_out_Counter, int_fast32_t TargetCount, char_t *in_Label )
+{
+    int_fast32_t  counter;
+    bool_t        is_stop;
+    int_t         r;
+
+    counter = *in_out_Counter;
+    counter += 1;
+    is_stop = ( counter == TargetCount );
+    if ( in_Label != NULL ) {
+        r= printf( "%s %d:\n", in_Label, counter );
+        R_UNREFERENCED_VARIABLE( r );  /* QAC 3200 : This is not error information */
+    } else {
+        if ( counter == 1 ) {
+            printf( "R_D_Counter address: 0x%08X\n", (uintptr_t) in_out_Counter );
+        }
+    }
+    *in_out_Counter = counter;
+
+    return  is_stop;
+}
+#endif  /* R_OSPL_DEBUG_TOOL */
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/porting/r_ospl_memory.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,429 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl_memory.c
+* @brief   Memory map
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: $
+* $Date::                           $
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#ifdef R_OSPL_TEST_CODE
+#include  "r_ospl_test.h"
+#endif
+#include  "r_ospl_private.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/**
+* @struct  gs_address_table_line_t
+* @brief  gs_address_table_line_t
+*/
+typedef struct st_gs_address_table_line_t  gs_address_table_line_t;
+struct st_gs_address_table_line_t {
+
+    /** Address */
+    uintptr_t  Address;
+
+    /** Value */
+    int_fast32_t  Value;
+};
+
+
+/**
+* @struct  gs_address_table_line_c_t
+* @brief  gs_address_table_line_c_t
+*/
+typedef struct st_gs_address_table_line_c_t  gs_address_table_line_c_t;
+struct st_gs_address_table_line_c_t {
+
+    /** Address */
+    uintptr_t  Address;
+
+    /** Value */
+    r_ospl_axi_cache_attribute_t  Value;
+};
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* ->MISRA 17.4 : These are addresses */
+
+#define GS_MIRROR_SIZE    0x40000000u
+#define GS_CACHED_START   0x00000000u
+#define GS_CACHED_END     ( GS_CACHED_START + GS_MIRROR_SIZE )
+#define GS_UNCACHED_START 0x40000000u
+#define GS_UNCACHED_END   ( GS_UNCACHED_START + GS_MIRROR_SIZE )
+
+#define GS_IO_START       0x60A00000u
+
+/* From "scatter.scat" file */
+#if defined( RZ_A1L )
+#define LRAM_SIZE                   0x00300000u
+#else  /* RZ/A1H */
+#define LRAM_SIZE                   0x00A00000u
+#endif
+#define LRAM_START                  0x20000000u
+#define LRAM_END                    ( LRAM_START + LRAM_SIZE )
+#define UNUSED_UNCACHED_LRAM_START  0x60000000u
+#define UNCACHED_LRAM_END           ( UNUSED_UNCACHED_LRAM_START + LRAM_SIZE )
+
+/* <-MISRA 17.4 */
+
+#define  GS_EXTERNAL_START_0x00000000               0x00000000u
+#define  GS_EXTERNAL_SDRAM_START_0x08000000         0x08000000u
+#define  GS_INTERNAL_RAM_START_0x20000000           0x20000000u
+#define  GS_INTERNAL_REGISTERS_START_0x80000000     0x80000000u
+
+#if defined( RZ_A1L_EV_BOARD )
+#define  GS_SDRAM_SIZE  0x04000000u
+#else
+#define  GS_SDRAM_SIZE  0x02000000u
+#endif
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+#ifdef R_OSPL_TEST_CODE
+static  r_ospl_axi_envronment_t  gs_Environment;
+#endif
+
+
+/******************************************************************************
+* Implement: R_OSPL_ToPhysicalAddress
+******************************************************************************/
+errnum_t  R_OSPL_ToPhysicalAddress( const volatile void *in_Address, uintptr_t *out_PhysicalAddress )
+{
+    errnum_t  e;
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    uintptr_t const  address = (uintptr_t) in_Address;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+
+    IF_DQ( out_PhysicalAddress == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    *out_PhysicalAddress = address;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/******************************************************************************
+* Implement: R_OSPL_ToCachedAddress
+******************************************************************************/
+errnum_t  R_OSPL_ToCachedAddress( const volatile void *in_Address, void *out_CachedAddress )
+{
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    /* ->QAC 0289 */ /* ->QAC 1002 : Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base */
+    errnum_t  e;
+#if  IS_MBED_USED
+    uintptr_t  address = (uintptr_t) in_Address;
+    const uintptr_t  uncached_from_cached = UNUSED_UNCACHED_LRAM_START - LRAM_START;
+#else
+    uintptr_t const  address = (uintptr_t) in_Address;
+#endif
+
+    IF_DQ( out_CachedAddress == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+#if  IS_MBED_USED
+    IF ( address < LRAM_START ) {
+        e = E_ACCESS_DENIED;
+    }
+    else if ( address < LRAM_END ) {
+        e = 0;
+    } else IF ( address < UNUSED_UNCACHED_LRAM_START ) {
+        e = E_ACCESS_DENIED;
+    }
+    else if ( address < UNCACHED_LRAM_END ) {
+        address -= uncached_from_cached;
+        e = 0;
+    } else {
+        e = E_ACCESS_DENIED;
+    }
+#else
+    IF ( (address >= (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base)  &&
+         (address < (uintptr_t)&Image$$END_OF_INTERNAL_RAM_BARRIER$$ZI$$Limit) ) {
+        /* "BEGIN_OF_NOCACHE_RAM_BARRIER" is defined in "scatter.sct" file. */
+        /* Image$$ execution region symbols */
+        /* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0377d/CHDFHJDJ.html */
+
+        e = E_ACCESS_DENIED;
+    }
+    else IF ( address >= UNUSED_UNCACHED_LRAM_START ) {
+        e = E_ACCESS_DENIED;
+    }
+    else {
+        e = 0;
+    }
+#endif
+
+    *(void **) out_CachedAddress = (void *) address;
+
+fin:
+    return  e;
+    /* <-QAC 0289 *//* <-QAC 1002 */
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+}
+
+
+/******************************************************************************
+* Implement: R_OSPL_ToUncachedAddress
+******************************************************************************/
+errnum_t  R_OSPL_ToUncachedAddress( const volatile void *in_Address, void *out_UncachedAddress )
+{
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    /* ->QAC 0289 */ /* ->QAC 1002 : Image$$BEGIN_OF_CACHED_RAM_BARRIER$$Base */
+    errnum_t  e;
+#if  IS_MBED_USED
+    uintptr_t  address = (uintptr_t) in_Address;
+    uintptr_t  nc_base = UNUSED_UNCACHED_LRAM_START;
+    const uintptr_t  uncached_from_cached = UNUSED_UNCACHED_LRAM_START - LRAM_START;
+#else
+    uintptr_t const  address = (uintptr_t) in_Address;
+#endif
+
+    IF_DQ( out_UncachedAddress == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+#if  IS_MBED_USED
+    IF ( address < nc_base - uncached_from_cached ) {
+        e = E_ACCESS_DENIED;
+    }
+    else if ( address < LRAM_END ) {
+        address += uncached_from_cached;
+        e = 0;
+    } else IF ( address < nc_base ) {
+        e = E_ACCESS_DENIED;
+    }
+    else if ( address < UNCACHED_LRAM_END ) {
+        e = 0;
+    } else {
+        e = E_ACCESS_DENIED;
+    }
+#else
+    IF ( (address >= (uintptr_t)&Image$$BEGIN_OF_CACHED_RAM_BARRIER$$Base)  &&
+         (address < (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$ZI$$Limit) ) {
+        e = E_ACCESS_DENIED;
+    }
+    else if ( (address >= (uintptr_t)&Image$$BEGIN_OF_NOCACHE_RAM_BARRIER$$Base)  &&
+              (address < (uintptr_t)&Image$$END_OF_INTERNAL_RAM_BARRIER$$ZI$$Limit) ) {
+        e = 0;
+    } else IF ( R_CUT_IF_ALWAYS_TRUE( (address >= GS_CACHED_START)  &&)  (address < GS_CACHED_END) ) {
+        e = E_ACCESS_DENIED;
+    }
+    else IF ( (address >= UNUSED_UNCACHED_LRAM_START) && (address < GS_IO_START) ) {
+        e = E_ACCESS_DENIED;
+    }
+    else {
+        e = 0;
+    }
+#endif
+
+    *(void **) out_UncachedAddress = (void *) address;
+
+fin:
+    return  e;
+    /* <-QAC 0289 *//* <-QAC 1002 */
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+}
+
+
+/******************************************************************************
+* Implement: R_OSPL_MEMORY_GetLevelOfFlush
+******************************************************************************/
+errnum_t  R_OSPL_MEMORY_GetLevelOfFlush( const void *in_Address, int_fast32_t *out_Level )
+{
+    uintptr_t  address = (uintptr_t) in_Address;
+
+#ifdef R_OSPL_TEST_CODE
+    if ( gs_Environment == R_OSPL_AXI_L2CACHED ) {
+#endif
+        static const gs_address_table_line_t  table[] = {
+            /* .Address                                       .Value */
+            { GS_EXTERNAL_START_0x00000000,                        0 },
+            { GS_EXTERNAL_SDRAM_START_0x08000000,                  1 },
+            { GS_EXTERNAL_SDRAM_START_0x08000000 + GS_SDRAM_SIZE,  0 },
+            { GS_INTERNAL_RAM_START_0x20000000,                    1 },
+            { GS_INTERNAL_RAM_START_0x20000000 + LRAM_SIZE,        0 }
+        };
+
+
+        if ( address < table[1].Address ) {
+            *out_Level = table[0].Value;
+        } else if ( address < table[2].Address ) {
+            *out_Level = table[1].Value;
+        } else if ( address < table[3].Address ) {
+            *out_Level = table[2].Value;
+        } else if ( address < table[4].Address ) {
+            *out_Level = table[3].Value;
+        } else {
+            *out_Level = table[4].Value;
+        }
+        R_STATIC_ASSERT( R_COUNT_OF( table ) == 5, "" );
+
+#ifdef R_OSPL_TEST_CODE
+    } else {
+        static const gs_address_table_line_t  table[] = {
+            /* .Address                                       .Value */
+            { GS_EXTERNAL_START_0x00000000,                        0 },
+            { GS_EXTERNAL_SDRAM_START_0x08000000,                  2 },
+            { GS_EXTERNAL_SDRAM_START_0x08000000 + GS_SDRAM_SIZE,  0 },
+            { GS_INTERNAL_RAM_START_0x20000000,                    1 },
+            { GS_INTERNAL_RAM_START_0x20000000 + LRAM_SIZE,        0 },
+            /* { GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000,                 2 }, */
+            /* { GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000 + GS_SDRAM_SIZE, 0 }, */
+            /* { GS_INTERNAL_RAM_MIRROR_START_0x60000000,                   0 }, */
+            /* { GS_INTERNAL_RAM_MIRROR_START_0x60000000 + LRAM_SIZE,       0 } */
+        };
+
+
+        ASSERT_R( gs_Environment == R_OSPL_AXI_L2STRONGLY, R_NOOP() );
+
+        if ( address < table[1].Address ) {
+            *out_Level = table[0].Value;
+        } else if ( address < table[2].Address ) {
+            *out_Level = table[1].Value;
+        } else if ( address < table[3].Address ) {
+            *out_Level = table[2].Value;
+        } else if ( address < table[4].Address ) {
+            *out_Level = table[3].Value;
+        } else {
+            *out_Level = table[4].Value;
+        }
+        R_STATIC_ASSERT( R_COUNT_OF( table ) == 5, "" );
+    }
+#endif
+    return  0;
+}
+
+
+/******************************************************************************
+* Implement: R_OSPL_AXI_Get2ndCacheAttribute
+******************************************************************************/
+errnum_t  R_OSPL_AXI_Get2ndCacheAttribute( uintptr_t const  in_PhysicalAddress,
+        r_ospl_axi_cache_attribute_t *const  out_CacheAttribute )
+{
+    uintptr_t  address = in_PhysicalAddress;
+
+#ifdef R_OSPL_TEST_CODE
+    if ( gs_Environment == R_OSPL_AXI_L2CACHED ) {
+#endif
+        static const gs_address_table_line_c_t  table[] = {
+            /* .Address                                  .Value */
+            { GS_EXTERNAL_START_0x00000000,               R_OSPL_AXI_WRITE_BACK_W },
+            /*{ GS_EXTERNAL_SDRAM_START_0x08000000,       R_OSPL_AXI_WRITE_BACK_W },*/
+            { GS_INTERNAL_RAM_START_0x20000000,           R_OSPL_AXI_CACHE_ZERO },
+            /*{ GS_INTERNAL_REGISTERS_START_0x80000000,   R_OSPL_AXI_CACHE_ZERO }*/
+            /* If external I/O existed, "*out_CacheAttribute = R_AXI_DEVICE;" */
+        };
+
+
+        if ( address < table[1].Address ) {
+            *out_CacheAttribute = table[0].Value;
+        } else {
+            *out_CacheAttribute = table[1].Value;
+        }
+        R_STATIC_ASSERT( R_COUNT_OF( table ) == 2, "" );
+
+#ifdef R_OSPL_TEST_CODE
+    } else {
+        static const gs_address_table_line_c_t  table[] = {
+            /* .Address                                  .Value */
+            { GS_EXTERNAL_START_0x00000000,               R_OSPL_AXI_STRONGLY },
+            /*{ GS_EXTERNAL_SDRAM_START_0x08000000,       R_OSPL_AXI_STRONGLY },*/
+            { GS_INTERNAL_RAM_START_0x20000000,           R_OSPL_AXI_CACHE_ZERO },
+            /*{ GS_EXTERNAL_MIRROR_START_0x40000000,        R_OSPL_AXI_STRONGLY },*/
+            /*{ GS_EXTERNAL_SDRAM_MIRROR_START_0x48000000,R_OSPL_AXI_STRONGLY },*/
+            /*{ GS_INTERNAL_RAM_MIRROR_START_0x60000000,    R_OSPL_AXI_CACHE_ZERO },*/
+            /*{ GS_INTERNAL_REGISTERS_START_0x80000000,   R_OSPL_AXI_CACHE_ZERO }*/
+            /* If external I/O existed, "*out_CacheAttribute = R_AXI_DEVICE;" */
+        };
+
+
+        ASSERT_R( gs_Environment == R_OSPL_AXI_L2STRONGLY, R_NOOP() );
+
+        if ( address < table[1].Address ) {
+            *out_CacheAttribute = table[0].Value;
+        } else {
+            *out_CacheAttribute = table[1].Value;
+        }
+        R_STATIC_ASSERT( R_COUNT_OF( table ) == 2, "" );
+    }
+#endif
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_AXI_GetProtection
+************************************************************************/
+errnum_t  R_OSPL_AXI_GetProtection( uintptr_t const  in_PhysicalAddress,
+                                    r_ospl_axi_protection_t *const  out_Protection )
+{
+    *out_Protection = R_OSPL_AXI_NON_SECURE;  /* Same as CPU(TTB) NS bit */
+
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_AXI_SetEnvironment
+************************************************************************/
+#ifdef R_OSPL_TEST_CODE
+errnum_t  R_OSPL_AXI_SetEnvironment( r_ospl_axi_envronment_t in_Environment )
+{
+    gs_Environment = in_Environment;
+    return  0;
+}
+#endif
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/porting/r_ospl_unrecoverable.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* $FileName: r_ospl_unrecoverable.c $
+*    Unrecoverable State
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+******************************************************************************/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/***********************************************************************
+* Implement: R_OSPL_RaiseUnrecoverable
+************************************************************************/
+void  R_OSPL_RaiseUnrecoverable( errnum_t const  e )
+{
+    bool_t    was_all_enabled;  /* = false; */ /* QAC 3197 */
+    /* ->QAC 3204 */
+    volatile  bool_t  is_loop = true;
+    /* <-QAC 3204 */
+
+    was_all_enabled = R_OSPL_DisableAllInterrupt();
+
+    R_DebugBreak( NULL, e );
+
+    while ( IS( is_loop ) ) {
+        /* Infinite Loop. Set "is_loop" by the debugger */
+    }
+
+    if ( IS( was_all_enabled ) ) {
+        R_OSPL_EnableAllInterrupt();
+    }
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/GraphicsFramework/ospl/src/r_ospl.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1626 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**
+* @file  r_ospl.c
+* @brief   OS Porting Layer. Functions not depended on any environment.
+*
+* $Module: OSPL $ $PublicVersion: 0.90 $ (=R_OSPL_VERSION)
+* $Rev: 35 $
+* $Date:: 2014-04-15 21:38:18 +0900#$
+*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include  "r_ospl.h"
+#include  "iodefine.h"
+#include  "iobitmasks/cpg_iobitmask.h"
+#include  "r_ospl_private.h"
+#include  "r_ospl_os_less_private.h"
+#if R_OSPL_IS_PREEMPTION
+#include  "r_ospl_RTX_private.h"
+#endif
+#include  "locking.h"
+#ifdef __ICCARM__
+#include <intrinsics.h>
+#endif
+#ifdef  __GNUC__
+#if ! IS_MBED_USED
+#include  "irq.h"
+#endif
+#endif
+#if R_OSPL_DEBUG_TOOL
+#include  <stdio.h>
+#endif
+#ifndef R_OSPL_NDEBUG
+#include  <string.h>
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static void  R_OSPL_TABLE_Search_Sub( const r_ospl_table_t *self,
+                                      const void *Key, r_ospl_table_searched_t *out_Searched );
+
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+static r_ospl_error_t  *R_OSPL_GetCurrentThreadError_Sub( r_ospl_if_not_t TypeOfIfNot );
+#endif
+
+
+/**
+* @def  R_OSPL_DEFAULT_DEBUG_THREAD_COUNT
+* @brief  For until calling "R_OSPL_SET_DEBUG_WORK"
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+#define  R_OSPL_DEFAULT_DEBUG_THREAD_COUNT  2
+#endif
+
+
+/** For until calling "R_OSPL_SET_DEBUG_WORK" */
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+static r_ospl_table_block_t  gs_thread_index_table_body[ R_OSPL_DEFAULT_DEBUG_THREAD_COUNT ];
+#endif
+
+
+/** For until calling "R_OSPL_SET_DEBUG_WORK" */
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+static r_ospl_error_t  gs_error;
+#endif
+
+
+/** as <r_ospl_global_error_t> */
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+
+/* ->MISRA 8.7 : If not defined R_OSPL_ERROR_BREAK, this is referenced by only 1 function. */ /* ->SEC M2.2.1 */
+static r_ospl_global_error_t  gs_global_error =
+    /* <-MISRA 8.7 */ /* <-SEC M2.2.1 */
+{
+    {	                                  /* .ThreadIndexTable */
+        gs_thread_index_table_body,          /* .Area */
+        0,                                   /* .Count */
+        R_OSPL_DEFAULT_DEBUG_THREAD_COUNT,   /* .MaxCount */
+        NULL,                                /* .KeyCache */
+        0,                                   /* .IndexCache */
+        0,                                   /* .FirstFreeIndex */
+#if R_OSPL_IS_PREEMPTION
+        true                                 /* .Is_T_Lock */
+#endif
+    },
+    &gs_error,  /* .ErrorArray */
+
+#if R_OSPL_ERROR_BREAK
+    0,          /* .RaisedGlobalErrorID */  /* Necessary T-Lock */
+    0           /* .BreakGlobalErrorID */
+#endif
+};
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_GetVersion
+************************************************************************/
+int32_t  R_OSPL_GetVersion(void)
+{
+    return  R_OSPL_VERSION;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_IsPreemption
+************************************************************************/
+bool_t  R_OSPL_IsPreemption(void)
+{
+    return  R_OSPL_IS_PREEMPTION;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FLAG32_InitConst
+************************************************************************/
+void  R_OSPL_FLAG32_InitConst( volatile r_ospl_flag32_t *const  self )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->Flags = 0;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FLAG32_Set
+************************************************************************/
+void  R_OSPL_FLAG32_Set( volatile r_ospl_flag32_t *const  self, bit_flags32_t const  SetFlags )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->Flags |= SetFlags;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FLAG32_Clear
+************************************************************************/
+void  R_OSPL_FLAG32_Clear( volatile r_ospl_flag32_t *const  self, bit_flags32_t const  ClearFlags1 )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->Flags &= ~ClearFlags1;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FLAG32_Get
+************************************************************************/
+bit_flags32_t  R_OSPL_FLAG32_Get( volatile const r_ospl_flag32_t *const  self )
+{
+    bit_flags32_t  return_value;
+
+    IF_DQ( self == NULL ) {
+        return_value = 0;
+        goto fin;
+    }
+
+    return_value = self->Flags;
+
+fin:
+    return  return_value;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FLAG32_GetAndClear
+************************************************************************/
+bit_flags32_t  R_OSPL_FLAG32_GetAndClear( volatile r_ospl_flag32_t *const  self )
+{
+    bit_flags32_t  return_value;
+
+    IF_DQ( self == NULL ) {
+        return_value = 0;
+        goto fin;
+    }
+
+    return_value = self->Flags;
+    self->Flags = 0;
+
+fin:
+    return  return_value;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_ASYNC_CopyExceptAThread
+************************************************************************/
+void  R_OSPL_ASYNC_CopyExceptAThread( const r_ospl_async_t *const  Source,
+                                      r_ospl_async_t *const  Destination )
+{
+    IF_DQ( Destination == NULL ) {
+        goto fin;
+    }
+    IF_DQ( Source == NULL ) {
+        goto fin;
+    }
+
+    *Destination = *Source;
+    Destination->A_Thread = NULL;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_EnableAllInterrupt
+************************************************************************/
+void  R_OSPL_EnableAllInterrupt(void)
+{
+    __enable_irq();
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_DisableAllInterrupt
+************************************************************************/
+bool_t  R_OSPL_DisableAllInterrupt(void)
+{
+#ifdef __ICCARM__
+    bool_t  was_enabled = ( ( __get_interrupt_state() & 0x80 ) == 0 );
+    __disable_irq();
+    return  was_enabled;
+#else
+    return  (bool_t)( __disable_irq() == 0 );
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_InterruptsEnable
+************************************************************************/
+void  R_BSP_InterruptsEnable(void)
+{
+    __enable_irq();
+}
+
+
+/***********************************************************************
+* Implement: R_BSP_InterruptsDisable
+************************************************************************/
+void  R_BSP_InterruptsDisable(void)
+{
+#ifdef __ICCARM__
+    __disable_irq();
+#else
+    int_fast32_t  ret;
+
+    ret = __disable_irq();
+    R_UNREFERENCED_VARIABLE( ret );  /* QAC 3200 : This is not error information */
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_LockChannel
+************************************************************************/
+errnum_t  R_OSPL_LockChannel( int_fast32_t ChannelNum, int_fast32_t *out_ChannelNum,
+                              mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax )
+{
+    errnum_t    e;
+    bool_t      is_success;
+    mcu_lock_t  hardware_index;
+
+    ASSERT_D( HardwareIndexMin <= HardwareIndexMax,  e=E_OTHERS; goto fin );
+
+    if ( ChannelNum == R_OSPL_UNLOCKED_CHANNEL ) {
+        ASSERT_D( out_ChannelNum != NULL,  e=E_OTHERS; goto fin );
+
+#if BSP_CFG_USER_LOCKING_ENABLED
+        for ( hardware_index = HardwareIndexMin;  hardware_index <= HardwareIndexMax;
+                hardware_index += 1 ) {
+            is_success = R_BSP_HardwareLock( hardware_index );
+            if ( is_success ) {
+                break;
+            }
+        }
+        IF ( hardware_index > HardwareIndexMax ) {
+            e=E_FEW_ARRAY;
+            goto fin;
+        }
+#else
+        e= R_OSPL_LockUnlockedChannel( out_ChannelNum,
+                                       HardwareIndexMin, HardwareIndexMax );
+        IF(e) {
+            goto fin;
+        }
+        out_ChannelNum = NULL;
+#endif
+    } else {
+        hardware_index = (mcu_lock_t)( HardwareIndexMin + ChannelNum );
+
+        IF_D ( hardware_index < HardwareIndexMin  ||  hardware_index > HardwareIndexMax ) {
+            e=E_FEW_ARRAY;
+            goto fin;
+        }
+
+        is_success = R_BSP_HardwareLock( hardware_index );
+        IF ( ! is_success ) {
+            e=E_ACCESS_DENIED;
+            goto fin;
+        }
+    }
+
+    if ( out_ChannelNum != NULL ) {
+        *out_ChannelNum = hardware_index - HardwareIndexMin;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_UnlockChannel
+************************************************************************/
+errnum_t  R_OSPL_UnlockChannel( int_fast32_t ChannelNum,  errnum_t  e,
+                                mcu_lock_t  HardwareIndexMin,  mcu_lock_t  HardwareIndexMax )
+{
+    bool_t      is_success;
+    mcu_lock_t  hardware_index;
+
+    ASSERT_D( HardwareIndexMin <= HardwareIndexMax,  e= R_OSPL_MergeErrNum( e, E_OTHERS ) );
+
+    hardware_index = (mcu_lock_t)( HardwareIndexMin + ChannelNum );
+
+    if ( hardware_index >= HardwareIndexMin  &&  hardware_index <= HardwareIndexMax ) {
+        is_success = R_BSP_HardwareUnlock( hardware_index );
+        IF ( ! is_success ) {
+            e= R_OSPL_MergeErrNum( e, E_ACCESS_DENIED );
+        }
+    }
+
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_C_LOCK_InitConst
+************************************************************************/
+void  R_OSPL_C_LOCK_InitConst( r_ospl_c_lock_t *const  self )
+{
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+
+    self->IsLocked = false;
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_C_LOCK_Lock
+************************************************************************/
+errnum_t  R_OSPL_C_LOCK_Lock( r_ospl_c_lock_t *const  self )
+{
+    errnum_t  e;
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    IF ( R_OSPL_THREAD_GetCurrentId() == NULL ) {  /* Interrupt */
+        e = E_NOT_THREAD;
+        R_OSPL_RaiseUnrecoverable( e );
+        goto fin;
+    }
+
+    IF ( IS( self->IsLocked ) ) {
+        e=E_ACCESS_DENIED;
+        goto fin;
+    }
+
+    self->IsLocked = true;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_C_LOCK_Unlock
+************************************************************************/
+errnum_t  R_OSPL_C_LOCK_Unlock( r_ospl_c_lock_t *const  self )
+{
+    errnum_t  e;
+
+    if ( self != NULL ) {
+
+        IF ( R_OSPL_THREAD_GetCurrentId() == NULL ) {  /* Interrupt */
+            e = E_NOT_THREAD;
+            R_OSPL_RaiseUnrecoverable( e );
+            goto fin;
+        }
+
+        IF ( ! self->IsLocked ) {
+            /* Check not unlock the object that was initialized by other thread */
+            e = E_ACCESS_DENIED;
+            goto fin;
+        }
+
+        self->IsLocked = false;
+    }
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_I_LOCK_LockStub
+************************************************************************/
+bool_t  R_OSPL_I_LOCK_LockStub( void *const  self_ )
+{
+    R_IT_WILL_BE_NOT_CONST( self_ );
+    R_UNREFERENCED_VARIABLE( self_ );
+    return  false;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_I_LOCK_UnlockStub
+************************************************************************/
+void  R_OSPL_I_LOCK_UnlockStub( void *const  self_ )
+{
+    R_IT_WILL_BE_NOT_CONST( self_ );
+    R_UNREFERENCED_VARIABLE( self_ );
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_I_LOCK_RequestFinalizeStub
+************************************************************************/
+void  R_OSPL_I_LOCK_RequestFinalizeStub( void *const  self_ )
+{
+    R_IT_WILL_BE_NOT_CONST( self_ );
+    R_UNREFERENCED_VARIABLE( self_ );
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_MEMORY_Barrier
+************************************************************************/
+void  R_OSPL_MEMORY_Barrier(void)
+{
+    /* ->QAC 1006 : asm */
+    __asm("DSB");
+    /* <-QAC 1006 */
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_InstructionSyncBarrier
+************************************************************************/
+void  R_OSPL_InstructionSyncBarrier(void)
+{
+    /* ->QAC 1006 : asm */
+    __asm("ISB");
+    /* <-QAC 1006 */
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_CALLER_Initialize
+************************************************************************/
+void  R_OSPL_CALLER_Initialize( r_ospl_caller_t *const  self,  r_ospl_async_t *const  Async,
+                                volatile void *const  PointerToState,  int_t const  StateValueOfOnInterrupting,
+                                void *const  I_Lock, const r_ospl_i_lock_vtable_t *const  I_LockVTable )
+{
+    ASSERT_D( Async != NULL,  R_NOOP() );
+    ASSERT_D( PointerToState != NULL,  R_NOOP() );
+    IF_DQ( self == NULL ) {}
+    else {
+        self->Async = Async;
+        self->PointerToState = (volatile int_fast32_t *) PointerToState;
+        self->StateValueOfOnInterrupting = StateValueOfOnInterrupting;
+        self->I_Lock = I_Lock;
+        self->I_LockVTable = I_LockVTable;
+    }
+
+#ifndef R_OSPL_NDEBUG
+    /* Set sentinel */
+    ASSERT_D( IS_ALL_BITS_NOT_SET( Async->Flags, R_F_OSPL_ASYNC_FLAGS_SENTINEL_MASK ),
+              R_NOOP() );
+    ASSERT_D( IS_ALL_BITS_NOT_SET( R_F_OSPL_ASYNC_FLAGS_SENTINEL_VALUE,
+                                   ~R_F_OSPL_ASYNC_FLAGS_SENTINEL_MASK ),  R_NOOP() );
+
+    Async->Flags |= R_F_OSPL_ASYNC_FLAGS_SENTINEL_VALUE;
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FTIMER_InitializeIfNot
+************************************************************************/
+errnum_t  R_OSPL_FTIMER_InitializeIfNot( r_ospl_ftimer_spec_t *const  out_Specification )
+{
+    /* ->SEC M1.11.1 : Can not const "is_initialized" because timing */
+    bool_t  is_initialized;
+    /* <-SEC M1.11.1 */
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_MTU2_1_2
+    enum { bits_CST1_CST2 = 0x06 };
+#endif
+
+    /* ->QAC 0306 */
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM0
+    struct st_ostm *const  reg_OSTM = &OSTM0;
+#elif  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM1
+    struct st_ostm *const  reg_OSTM = &OSTM1;
+#endif
+    /* <-QAC 0306 */
+
+    /* ->QAC 0306 */
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM0
+    R_OSPL_SET_TO_8_BIT_REGISTER( &CPG.STBCR5, CPG_STBCR5_MSTP51,
+                                  CPG_STBCR5_MSTP51_SHIFT, 0 );
+
+#elif  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM1
+    R_OSPL_SET_TO_8_BIT_REGISTER( &CPG.STBCR5, CPG_STBCR5_MSTP50,
+                                  CPG_STBCR5_MSTP50_SHIFT, 0 );
+
+#elif  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_MTU2_1_2
+    R_OSPL_SET_TO_8_BIT_REGISTER( &CPG.STBCR3, CPG_STBCR3_MSTP33,
+                                  CPG_STBCR3_MSTP33_SHIFT, 0 );
+#endif
+
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_MTU2_1_2
+    is_initialized = IS_ALL_BITS_NOT_SET( MTU2.TSTR, bits_CST1_CST2 );
+#else
+    is_initialized = ( (int_fast32_t) reg_OSTM->OSTMnTE == 0 );
+#endif
+    /* <-QAC 0306 */
+
+    if ( IS( is_initialized ) ) {  /* Integer Promotions */
+#if  R_OSPL_FTIMER_IS != R_OSPL_FTIMER_IS_MTU2_1_2
+        enum {  free_running_no_interrupt = 2 };
+#endif
+        bool_t  was_all_enabled; /* = false; */ /* QAC 3197 */
+
+        was_all_enabled = R_OSPL_DisableAllInterrupt();
+
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_MTU2_1_2
+        {
+            enum { external_clock_TCLKD = 0x07u };
+
+            /* ->QAC 0306 */
+
+            /* Channel 1 */
+            MTU2.TCR_1  = (uint8_t) external_clock_TCLKD;  /* overflow of the timer2 */
+            MTU2.TMDR_1 = 0;
+            MTU2.TIOR_1 = 0;
+            MTU2.TIER_1 = 0;
+            MTU2.TSR_1  = 0;
+            MTU2.TCNT_1 = 0;
+
+            /* Channel 2 */
+            MTU2.TCR_2  = 0;  /* 33MHz */
+            MTU2.TMDR_2 = 0;
+            MTU2.TIOR_2 = 0;
+            MTU2.TIER_2 = 0;
+            MTU2.TSR_2  = 0;
+            MTU2.TCNT_2 = 0;
+
+            /* Timer start */
+            /* MTU2.TSTR |= bits_CST1_CST2; */
+            {
+                uint8_t const  value = MTU2.TSTR;
+                MTU2.TSTR = (uint8_t)( (uint_fast32_t) value | bits_CST1_CST2 );
+            } /* QAC 2100 */
+
+            /* <-QAC 0306 */
+        }
+#else
+        if ( (int_fast32_t) reg_OSTM->OSTMnTE == 0 ) {  /* Integer Promotions */
+            reg_OSTM->OSTMnCTL = free_running_no_interrupt;
+            reg_OSTM->OSTMnTS = 1;
+        }
+#endif
+
+        if ( IS( was_all_enabled ) ) {
+            R_OSPL_EnableAllInterrupt();
+        }
+    }
+
+    R_OSPL_FTIMER_GetSpecification( out_Specification );
+
+    return  0;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FTIMER_GetSpecification
+************************************************************************/
+void  R_OSPL_FTIMER_GetSpecification( r_ospl_ftimer_spec_t *const  out_Specification )
+{
+    if ( out_Specification != NULL ) {
+        enum { msec_numerator   = 1 };      /* SEC M1.10.1, QAC-3132 */
+        enum { msec_denominator = 33333 };  /* SEC M1.10.1, QAC-3132 */
+        static const uint32_t  max_count = 0xFFFFFFFFu;  /* SEC M1.10.1, QAC-3132 */
+        static const uint32_t  extension_of_count = (1000 * msec_denominator) / msec_numerator;
+        /* SEC M1.10.1, QAC-3132 */
+
+        out_Specification->msec_Numerator   = msec_numerator;
+        out_Specification->msec_Denominator = msec_denominator;
+        out_Specification->MaxCount = max_count;
+        out_Specification->ExtensionOfCount = extension_of_count;
+    }
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FTIMER_Get
+************************************************************************/
+uint32_t  R_OSPL_FTIMER_Get(void)
+{
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_MTU2_1_2
+    enum { num_16bit = 16 }; /* SEC M1.10.1, QAC-3132 */
+    /* ->QAC 0306 */
+
+    uint32_t  now_high = (uint32_t)(MTU2.TCNT_1);
+    uint32_t  not_low  = (uint32_t)(MTU2.TCNT_2);
+
+    while( now_high != (uint32_t)(MTU2.TCNT_1) ) {
+        /* If higher byte was changed while reading lower byte, re-read. */
+        now_high = (uint32_t)(MTU2.TCNT_1);
+        not_low  = (uint32_t)(MTU2.TCNT_2);
+    }
+
+    return  ( now_high << num_16bit ) | not_low;
+
+    /* <-QAC 0306 */
+#else
+
+    /* ->QAC 0306 */
+#if  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM0
+    struct st_ostm *const  reg_OSTM = &OSTM0;
+#elif  R_OSPL_FTIMER_IS == R_OSPL_FTIMER_IS_OSTM1
+    struct st_ostm *const  reg_OSTM = &OSTM1;
+#endif
+    /* <-QAC 0306 */
+
+    ASSERT_R( reg_OSTM->OSTMnCMP == 0x0000000u,  R_NOOP() );
+    /* If "OSTMnCMP != 0", OSTMnCNT is set from 0 to OSTMnCMP-1 */
+
+    return  reg_OSTM->OSTMnCNT;
+
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_FTIMER_IsPast
+************************************************************************/
+errnum_t  R_OSPL_FTIMER_IsPast( const r_ospl_ftimer_spec_t *const  ts,
+                                uint32_t const  Now,  uint32_t const  TargetTime,  bool_t *const  out_IsPast )
+{
+    uint32_t const         target_minus_now = TargetTime - Now;
+    static const uint32_t  minus_flag = 0x80000000u;
+    errnum_t       e;
+    bool_t const   is_past = IS_BIT_SET( target_minus_now, minus_flag );
+
+    IF_DQ( ts == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( out_IsPast == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    if ( IS( is_past ) ) {
+        uint32_t const  now_minus_target = Now - TargetTime;
+
+        IF ( now_minus_target > ts->ExtensionOfCount ) {
+            e=E_TIME_OUT;
+            goto fin;
+        }
+    }
+
+    *out_IsPast = is_past;
+
+    e=0;
+fin:
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_TABLE_InitConst
+************************************************************************/
+void  R_OSPL_TABLE_InitConst( r_ospl_table_t *const  self,
+                              void *const  Area,  size_t const  AreaByteSize,  bool_t const  Is_T_Lock )
+{
+#if  ! defined( R_OSPL_NDEBUG ) ||  R_OSPL_IS_PREEMPTION
+    errnum_t  e;
+#endif
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+
+    IF_DQ( self == NULL ) {
+#ifndef R_OSPL_NDEBUG
+        e=E_OTHERS;
+#endif
+        goto fin;
+    }
+
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( Is_T_Lock ) ) {
+        if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+            e= R_OSPL_Start_T_Lock();
+            if(e!=0) {
+                goto fin;
+            }
+            is_lock = true;  /* T-Lock to "self" */
+        }
+    }
+#endif
+
+    self->Area       = Area;
+    self->Count      = 0;
+    self->MaxCount   = (int_fast32_t)( AreaByteSize / sizeof( r_ospl_table_block_t ) );
+    self->KeyCache   = NULL;
+    self->FirstFreeIndex = 0;
+#if R_OSPL_IS_PREEMPTION
+    self->Is_T_Lock  = Is_T_Lock;
+#else
+    R_UNREFERENCED_VARIABLE( Is_T_Lock );
+#endif
+
+    /* Set "self->Area[].NextFreeIndex" */
+    {
+        r_ospl_table_block_t *const  block_array = (r_ospl_table_block_t *) Area;
+        int_fast32_t                 index;
+        int_fast32_t const           max_index = self->MaxCount - 1;
+
+        IF_DQ( block_array == NULL ) {
+#ifndef R_OSPL_NDEBUG
+            e=E_OTHERS;
+#endif
+            goto fin;
+        }
+
+        for ( index = 0;  index < max_index;  index += 1 ) {
+            block_array[ index ].NextFreeIndex = (int16_t)( index + 1 );
+        }
+        block_array[ max_index ].NextFreeIndex = (int16_t) R_OSPL_TABLE_BLOCK_NO_NEXT;
+    }
+
+#ifndef R_OSPL_NDEBUG
+    e=0;
+#endif
+fin:
+    R_NOOP();/* for following all #if is false */
+
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+#ifndef R_OSPL_NDEBUG
+    if ( e != 0 ) {
+        R_DebugBreak( NULL, e );
+    }
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_TABLE_GetIndex
+************************************************************************/
+errnum_t  R_OSPL_TABLE_GetIndex( r_ospl_table_t *const  self,  const void *const  Key,
+                                 int_fast32_t *const  out_Index,  r_ospl_if_not_t const  TypeOfIfNot )
+{
+    errnum_t  e;
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( out_Index == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( self->Is_T_Lock ) ) {
+        if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+            e= R_OSPL_Start_T_Lock();
+            if(e!=0) {
+                goto fin;
+            }
+            is_lock = true;  /* T-Lock to "self" */
+        }
+    }
+#endif
+
+
+    if ( (Key == self->KeyCache)  &&  (self->Count >= 1) ) {
+        *out_Index = self->IndexCache;
+    } else {
+        r_ospl_table_searched_t      searched;
+        r_ospl_table_block_t *const  block_array = self->Area;
+        int_fast32_t                 found_index;
+
+        R_OSPL_TABLE_Search_Sub( self, Key, &searched );
+
+        if ( ! searched.IsFound ) {
+            int_fast32_t  so_index;  /* sorted_key_index */
+            int_fast32_t  first_index;  /* FirstFreeIndex */
+
+            if ( TypeOfIfNot == R_OSPL_ALLOCATE_IF_NOT ) {
+                if ( self->Count == self->MaxCount ) {
+                    e = E_FEW_ARRAY;
+                    goto fin;
+                }
+
+                /* Insert and Set "block_array[ searched.SortedKeyIndex ].Key" */
+                for ( so_index = self->Count - 1;
+                        so_index >= searched.SortedKeyIndex;
+                        so_index -= 1 ) {
+                    block_array[ so_index + 1 ].Key   = block_array[ so_index ].Key;
+                    block_array[ so_index + 1 ].Index = block_array[ so_index ].Index;
+                }
+                block_array[ searched.SortedKeyIndex ].Key = Key;
+                self->Count += 1;
+
+                /* Set "block_array[ searched.SortedKeyIndex ].Index" */
+                first_index = self->FirstFreeIndex;
+                block_array[ searched.SortedKeyIndex ].Index = (int16_t) first_index;
+                self->FirstFreeIndex = block_array[ first_index ].NextFreeIndex;
+                block_array[ first_index ].NextFreeIndex = R_OSPL_TABLE_BLOCK_USED;
+
+            } else if ( TypeOfIfNot == R_OSPL_ERROR_IF_NOT ) {
+                e = E_NOT_FOUND_SYMBOL;
+                goto fin;
+            } else { /* TypeOfIfNot == R_OSPL_DO_NOTHING_IF_NOT */
+                e = 0;
+                goto fin;
+            }
+            /* Don't use "IF", Because this function called from "IF". */
+        }
+
+        self->KeyCache = Key;
+        found_index = block_array[ searched.SortedKeyIndex ].Index;
+        self->IndexCache = found_index;
+        *out_Index = found_index;
+    }
+
+    e=0;
+fin:
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+    return  e;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_TABLE_Free
+************************************************************************/
+void  R_OSPL_TABLE_Free( r_ospl_table_t *const  self,  const void *const  Key )
+{
+#if  ! defined( R_OSPL_NDEBUG ) ||  R_OSPL_IS_PREEMPTION
+    errnum_t  e;
+#endif
+#if R_OSPL_IS_PREEMPTION
+    bool_t    is_lock = false;
+#endif
+    r_ospl_table_searched_t  searched;
+
+    IF_DQ( self == NULL ) {
+#ifndef R_OSPL_NDEBUG
+        e=0;
+#endif
+        goto fin;
+    }
+
+#if R_OSPL_IS_PREEMPTION
+    if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+        e= R_OSPL_Start_T_Lock();
+        if(e!=0) {
+            goto fin;
+        }
+        is_lock = true;  /* T-Lock to "gs_global_error" */
+    }
+#endif
+
+    R_OSPL_TABLE_Search_Sub( self, Key, &searched );
+
+    if ( IS( searched.IsFound ) ) {
+        r_ospl_table_block_t *const  block_array = self->Area;
+        int_fast32_t                 so_index;  /* sorted_key_index */
+        int_fast32_t                 first_index;  /* FirstFreeIndex */
+        int_fast32_t const           count_ = self->Count;  /* _ is for MISRA 5.6 */
+
+        /* Set "FirstFreeIndex", ".NextFreeIndex" */
+        first_index = self->FirstFreeIndex;
+        self->FirstFreeIndex = block_array[ searched.SortedKeyIndex ].Index;
+        block_array[ self->FirstFreeIndex ].NextFreeIndex = (int16_t) first_index;
+
+        /* Remove one "r_ospl_table_block_t" */
+        /* Set "self->KeyCache" */
+        if ( searched.SortedKeyIndex < count_ ) {
+            for ( so_index = searched.SortedKeyIndex;  so_index < count_ ;  so_index += 1 ) {
+                block_array[ so_index ].Key   = block_array[ so_index + 1 ].Key;
+                block_array[ so_index ].Index = block_array[ so_index + 1 ].Index;
+            }
+            self->KeyCache   = block_array[ searched.SortedKeyIndex ].Key;
+            self->IndexCache = block_array[ searched.SortedKeyIndex ].Index;
+        } else if ( searched.SortedKeyIndex > 0 ) { /* searched.SortedKeyIndex >= 1 */
+            self->KeyCache   = block_array[ searched.SortedKeyIndex - 1 ].Key;
+            self->IndexCache = block_array[ searched.SortedKeyIndex - 1 ].Index;
+        } else {
+            self->KeyCache = NULL;
+        }
+        self->Count -= 1;
+    }
+
+#if  ! defined( R_OSPL_NDEBUG )
+    e=0;
+#endif
+fin:
+    R_NOOP();/* for following all #if is false */
+
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+#ifndef R_OSPL_NDEBUG
+    if ( e != 0 ) {
+        R_DebugBreak( NULL, e );
+    }
+#endif
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_TABLE_Search_Sub
+************************************************************************/
+static void  R_OSPL_TABLE_Search_Sub( const r_ospl_table_t *const  self,
+                                      const void *const  Key,  r_ospl_table_searched_t *const  out_Searched )
+{
+    int_fast32_t     left;
+    int_fast32_t     right;
+    int_fast32_t     middle;
+    /* ->QAC 0306 : Sort by pointer value */
+    uintptr_t const  target_key = (uintptr_t) Key;
+    /* <-QAC 0306 */
+    uintptr_t        middle_key;
+    enum {           num_2 = 2 };  /* SEC M1.10.1, QAC-3132 */
+    r_ospl_table_block_t  *array;
+
+    IF_DQ( self == NULL ) {
+        goto fin;
+    }
+    IF_DQ( out_Searched == NULL ) {
+        goto fin;
+    }
+
+    array = self->Area;
+
+
+    if ( self->Count == 0 ) {
+        out_Searched->SortedKeyIndex = 0;
+        out_Searched->IsFound = false;
+    } else {
+        left = 0;
+        right = self->Count - 1;
+
+        while ( (right - left) >= num_2 ) {
+            middle = (int_fast32_t)( (uint_fast32_t)( right + left ) / num_2 );
+            /* ->QAC 0306 : Sort by pointer value */
+            middle_key = (uintptr_t) array[ middle ].Key;
+            /* <-QAC 0306 */
+
+            if ( target_key == middle_key ) {
+                out_Searched->SortedKeyIndex = middle;
+                out_Searched->IsFound = true;
+                goto fin;
+            } else if ( target_key <  middle_key ) {
+                right = (int_fast32_t)( middle - 1 );
+            } else {
+                left = (int_fast32_t)( middle + 1 );
+            }
+        }
+
+        /* ->QAC 0306 : Sort by pointer value */
+        if ( target_key == (uintptr_t) array[ left ].Key ) {
+            out_Searched->SortedKeyIndex = left;
+            out_Searched->IsFound = true;
+        } else if ( target_key == (uintptr_t) array[ right ].Key ) {
+            out_Searched->SortedKeyIndex = right;
+            out_Searched->IsFound = true;
+        } else if ( target_key < (uintptr_t) array[ left ].Key ) {
+            out_Searched->SortedKeyIndex = left;
+            out_Searched->IsFound = false;
+        } else if ( target_key > (uintptr_t) array[ right ].Key ) {
+            out_Searched->SortedKeyIndex = right + 1;
+            out_Searched->IsFound = false;
+        } else {
+            out_Searched->SortedKeyIndex = right;
+            out_Searched->IsFound = false;
+        }
+        /* <-QAC 0306 */
+    }
+
+fin:
+    return;
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_TABLE_Print
+************************************************************************/
+#if R_OSPL_DEBUG_TOOL
+void  R_OSPL_TABLE_Print( r_ospl_table_t *const  self )
+{
+    int_fast32_t  so_index;  /* sorted_key_index */
+    int_fast32_t  index;
+    r_ospl_table_block_t *const  array = self->Area;
+
+    printf( "R_OSPL_TABLE_Print: r_ospl_table_t 0x%08X\n", (uintptr_t) self );
+    printf( "    .Count = %d\n", self->Count );
+    for ( so_index = 0;  so_index < self->Count;  so_index += 1 ) {
+        printf( "    .Area[%d].Key, Index = 0x%08X, %d\n",
+                so_index,  (uintptr_t) array[ so_index ].Key,  array[ so_index ].Index );
+    }
+    printf( "    .FirstFreeIndex = %d\n", self->FirstFreeIndex );
+    for ( index = 0;  index < self->MaxCount;  index += 1 ) {
+        printf( "    .Area[%d].NextFreeIndex = %d\n", index,  array[ index ].NextFreeIndex );
+    }
+    printf( "        %d = R_OSPL_TABLE_BLOCK_NO_NEXT\n", R_OSPL_TABLE_BLOCK_NO_NEXT );
+    printf( "        %d = R_OSPL_TABLE_BLOCK_USED\n", R_OSPL_TABLE_BLOCK_USED );
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_CallInterruptCallback
+************************************************************************/
+void  R_OSPL_CallInterruptCallback( const r_ospl_caller_t *const  self,
+                                    const r_ospl_interrupt_t *const  InterruptSource )
+{
+    errnum_t  e;
+    r_ospl_async_t  *async;
+#if ! R_OSPL_IS_PREEMPTION
+    r_ospl_master_t *const  gs_master = R_OSPL_GetPrivateContext();
+    r_ospl_thread_def_t  *current_thread = NULL;  /* NULL is for avoid QAC 3353 */
+#endif
+#if R_OSPL_ERROR_BREAK
+    static int_fast32_t  gs_nested_interrupt_level = 0;
+#endif
+
+#if R_OSPL_ERROR_BREAK
+    gs_nested_interrupt_level += 1;
+#endif
+
+#if ! R_OSPL_IS_PREEMPTION
+    IF_DQ( gs_master == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+#if R_OSPL_CPU_LOAD
+    e= gs_master->IdleCallback( R_OSPL_INTERRUPT_START );
+    IF(e) {
+        goto fin;
+    }
+#endif
+
+    current_thread = gs_master->CurrentThread;
+#endif
+
+    IF_DQ( self == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( self->Async == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+    async = self->Async;
+
+    ASSERT_D( ( async->Flags & R_F_OSPL_ASYNC_FLAGS_SENTINEL_MASK ) ==
+              R_F_OSPL_ASYNC_FLAGS_SENTINEL_VALUE,  e=E_OTHERS; goto fin );
+    /* If failed, memory area of "Async" variable was overwritten by other variable. */
+    /* Reason of failed may be not disabled interrupt */
+    /* or not called "*_I_LOCK_Unlock()" disabling interrupt by "*_I_LOCK_Disable()". */
+
+    IF_DQ( self->PointerToState == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+    IF_DQ( async->InterruptCallback == NULL ) {
+        e=E_OTHERS;
+        goto fin;
+    }
+
+#if ! R_OSPL_IS_PREEMPTION
+    gs_master->CurrentThread = NULL;  /* Interrupt */
+#endif
+
+    *self->PointerToState = self->StateValueOfOnInterrupting;
+
+
+
+    e= async->InterruptCallback( InterruptSource, self );  /* Main of callback */
+
+
+
+    if ( e != 0 ) {
+        if ( async->ReturnValue == 0 ) {
+            async->ReturnValue = e;
+        }
+        R_OSPL_CLEAR_ERROR();
+    }
+
+    e=0;
+fin:
+#if ! R_OSPL_IS_PREEMPTION
+    IF_DQ ( gs_master == NULL ) {}
+    else {
+        gs_master->CurrentThread = current_thread;
+
+#if R_OSPL_CPU_LOAD
+        {
+            errnum_t  ee;
+
+            ee= gs_master->IdleCallback( R_OSPL_INTERRUPT_END );
+            e= R_OSPL_MergeErrNum( e, ee );
+        }
+#endif
+    }
+#endif
+
+
+#if R_OSPL_ERROR_BREAK
+    gs_nested_interrupt_level -= 1;
+
+    if ( gs_nested_interrupt_level == 0 ) {
+        if ( gs_master != NULL ) {
+            current_thread = gs_master->CurrentThread;
+            gs_master->CurrentThread = NULL;
+        }
+
+
+        R_DEBUG_BREAK_IF_ERROR();
+
+
+        if ( gs_master != NULL ) {
+            gs_master->CurrentThread = current_thread;
+        }
+    }
+#endif
+    R_UNREFERENCED_VARIABLE( e );
+}
+
+
+/***********************************************************************
+* Implement: R_OSPL_SetErrNum
+************************************************************************/
+#if  R_OSPL_TLS_ERROR_CODE
+void  R_OSPL_SetErrNum( errnum_t const  e )
+{
+    r_ospl_error_t  *err;
+
+    if ( e != 0 ) {
+
+        err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+
+        if ( err != NULL ) {
+            if ( err->ErrNum == 0 ) {
+                err->ErrNum = e;
+            }
+        }
+    }
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_GetErrNum
+************************************************************************/
+#if  R_OSPL_TLS_ERROR_CODE
+errnum_t  R_OSPL_GetErrNum(void)
+{
+    errnum_t         e;
+    r_ospl_error_t  *err;
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+
+    if ( err != NULL ) {
+        e = err->ErrNum;
+    } else {
+        e = E_NO_DEBUG_TLS;
+    }
+
+    return  e;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_CLEAR_ERROR
+************************************************************************/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+void  R_OSPL_CLEAR_ERROR(void)
+{
+    r_ospl_error_t  *err;
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_DO_NOTHING_IF_NOT );
+
+    if ( err != NULL ) {
+#if R_OSPL_ERROR_BREAK
+        err->IsError = false;
+#endif
+
+#if R_OSPL_TLS_ERROR_CODE
+        err->ErrNum = 0;
+#endif
+    }
+}
+#endif
+
+
+/**
+* @brief   Function part of error break
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if R_OSPL_ERROR_BREAK
+static bool_t  R_OSPL_OnRaisingError_Sub( const char_t *const  FilePath,
+        int_fast32_t const  LineNum );  /* QAC-3450 */
+static bool_t  R_OSPL_OnRaisingError_Sub( const char_t *const  FilePath,
+        int_fast32_t const  LineNum )
+{
+#if  ! defined( R_OSPL_NDEBUG ) ||  R_OSPL_IS_PREEMPTION
+    errnum_t         e;
+#endif
+    bool_t           is_break = false;
+#if R_OSPL_IS_PREEMPTION
+    bool_t           is_lock = false;
+#endif
+    r_ospl_error_t  *err;
+
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+
+
+    if ( err != NULL ) {
+        if ( IS( err->IsError ) ) {
+            is_break = false;
+        } else {
+#if R_OSPL_IS_PREEMPTION
+            if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+                e= R_OSPL_Start_T_Lock();
+                if(e!=0) {
+                    goto fin;
+                }
+                is_lock = true;  /* T-Lock to "gs_global_error" */
+            }
+#endif
+
+            gs_global_error.RaisedGlobalErrorID ++;
+            is_break = ( gs_global_error.RaisedGlobalErrorID ==
+                         gs_global_error.BreakGlobalErrorID );
+
+            err->IsError = true;
+            err->ErrorID = gs_global_error.RaisedGlobalErrorID;
+            err->FilePath = FilePath;
+            err->LineNum = LineNum;
+        }
+    }
+
+#ifndef R_OSPL_NDEBUG
+    e=0;
+#endif
+#if R_OSPL_IS_PREEMPTION
+fin:
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+#ifndef R_OSPL_NDEBUG
+    if ( e != 0 ) {
+        R_DebugBreak( NULL, e );
+    }
+#endif
+    return  is_break;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_OnRaisingErrorForMISRA
+************************************************************************/
+#if R_OSPL_ERROR_BREAK
+bool_t  R_OSPL_OnRaisingErrorForMISRA( bool_t const  Condition,  const char_t *const  File,
+                                       int_t const  Line )
+{
+    if ( IS( Condition ) ) {
+        if ( R_OSPL_OnRaisingError_Sub( File, Line ) != 0 ) {
+            R_DebugBreak( File, Line );
+        }
+    }
+    return  Condition;
+}
+#endif
+
+
+/**
+* @brief   Function part of <R_DEBUG_BREAK_IF_ERROR>
+*
+* @par Parameters
+*    None
+* @return  None.
+*/
+#if R_OSPL_ERROR_BREAK
+void  R_OSPL_DebugBreakIfError( const char_t *const  File,  int_t const  Line )
+{
+    r_ospl_error_t  *err;
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_DO_NOTHING_IF_NOT );
+
+    if ( err != NULL  &&  err->IsError ) {
+        /* See the value of "err->ErrorID" in watch window. */
+        /* Call R_OSPL_SET_BREAK_ERROR_ID( N ); at main function. */
+        printf( "<ERROR error_ID=\"0x%X\" file=\"%s(%d)\"/>\n",
+                err->ErrorID, err->FilePath, err->LineNum );
+        R_DebugBreak( File, Line );
+    }
+
+    R_OSPL_CLEAR_ERROR();
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_GET_ERROR_ID
+************************************************************************/
+#if R_OSPL_ERROR_BREAK
+int_fast32_t  R_OSPL_GET_ERROR_ID(void)
+{
+    return  gs_global_error.RaisedGlobalErrorID;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_SET_BREAK_ERROR_ID
+************************************************************************/
+#if R_OSPL_ERROR_BREAK
+void  R_OSPL_SET_BREAK_ERROR_ID( int_fast32_t const  ErrorID )
+{
+#ifndef R_OSPL_NDEBUG
+    if ( gs_global_error.BreakGlobalErrorID != ErrorID ) {
+        printf( ">R_OSPL_SET_BREAK_ERROR_ID( %d );\n", ErrorID );
+    }
+#endif
+
+    gs_global_error.BreakGlobalErrorID = ErrorID;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_GetCurrentThreadError
+************************************************************************/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+r_ospl_error_t  *R_OSPL_GetCurrentThreadError(void)
+{
+    return  R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+}
+#endif
+
+
+/**
+* @brief   GetCurrentThreadError
+*
+* @param   TypeOfIfNot <r_ospl_if_not_t>
+* @return  Error information of current thread
+*/
+#if R_OSPL_ERROR_BREAK  ||  R_OSPL_TLS_ERROR_CODE
+static r_ospl_error_t  *R_OSPL_GetCurrentThreadError_Sub( r_ospl_if_not_t const  TypeOfIfNot )
+{
+    errnum_t            e;
+    int_fast32_t        index;
+    r_ospl_error_t     *err = NULL;
+    r_ospl_thread_id_t  th;  /* QAC 3441 */
+
+    index = R_OSPL_NO_INDEX;
+
+    th = R_OSPL_THREAD_GetCurrentId();
+    e= R_OSPL_TABLE_GetIndex( &gs_global_error.ThreadIndexTable, th, &index, TypeOfIfNot );
+    if ( e == E_FEW_ARRAY ) {
+#ifndef R_OSPL_NDEBUG
+        if ( gs_global_error.ThreadIndexTable.Area == gs_thread_index_table_body ) {
+            e = E_NO_DEBUG_TLS;
+        }
+#endif
+        goto fin;
+    }
+    if ( e != 0 ) {
+        goto fin;
+    }
+
+    if ( index != R_OSPL_NO_INDEX ) {
+        IF_DQ( gs_global_error.ErrorArray == NULL ) {
+#ifndef R_OSPL_NDEBUG
+            e=E_OTHERS;
+#endif
+            goto fin;
+        }
+        IF_DQ( index < -1 ) {
+#ifndef R_OSPL_NDEBUG
+            e=E_OTHERS;
+#endif
+            goto fin;
+        }
+
+        err = &gs_global_error.ErrorArray[ index ];
+    }
+
+#ifndef R_OSPL_NDEBUG
+    e=0;
+#endif
+fin:
+#ifndef R_OSPL_NDEBUG
+    if ( e != 0 ) {
+        R_DebugBreak( NULL, e );
+        /* If e == 2 (E_FEW_ARRAY), Set big work area by "R_OSPL_SET_DEBUG_WORK". */
+        /* If e == 29 (E_NO_DEBUG_TLS), Call "R_OSPL_SET_DEBUG_WORK". */
+    }
+#endif
+
+    return  err;
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_SET_DEBUG_WORK
+************************************************************************/
+#if R_OSPL_ERROR_BREAK
+void  R_OSPL_SET_DEBUG_WORK( void *const  WorkArea,  uint32_t const  WorkAreaSize )
+{
+    errnum_t               e;
+    int_fast32_t           count = WorkAreaSize / R_OSPL_DEBUG_WORK_1_SIZE;
+    uint8_t               *work = WorkArea;
+    r_ospl_table_block_t  *thread_index_array;
+    r_ospl_error_t        *error_array;
+    int_fast32_t           index;
+#if R_OSPL_IS_PREEMPTION
+    bool_t                 is_lock = false;
+#endif
+
+#if R_OSPL_IS_PREEMPTION
+    if ( R_OSPL_THREAD_GetCurrentId() != NULL ) {  /* If not interrrupt context */
+        e= R_OSPL_Start_T_Lock();
+        if(e!=0) {
+            goto fin;
+        }
+        is_lock = true;  /* T-Lock to "gs_global_error" */
+    }
+#endif
+
+
+    if ( gs_global_error.ThreadIndexTable.Area != gs_thread_index_table_body ) {
+        e = E_ACCESS_DENIED;
+        goto fin;
+    }
+
+    thread_index_array = (r_ospl_table_block_t *) &work[0];
+    error_array = (r_ospl_error_t *) &thread_index_array[ count ];
+    ASSERT_D( (uint8_t *) &error_array[ count ] <= &work[ WorkAreaSize ],  e=E_FEW_ARRAY; goto fin );
+
+    R_OSPL_TABLE_InitConst( &gs_global_error.ThreadIndexTable,
+                            thread_index_array,  count * sizeof( thread_index_array[0] ), true );
+
+    e= R_OSPL_TABLE_GetIndex( &gs_global_error.ThreadIndexTable,
+                              gs_thread_index_table_body[0].Key, &index, R_OSPL_ALLOCATE_IF_NOT );
+    if(e!=0) {
+        goto fin;
+    }
+
+    gs_global_error.ErrorArray = error_array;
+    gs_global_error.ErrorArray[ index ] = gs_error;
+
+#ifndef R_OSPL_NDEBUG
+    memset( gs_thread_index_table_body, 0xFE, sizeof(gs_thread_index_table_body) );
+    memset( &gs_error, 0xFE, sizeof(gs_error) );
+#endif
+
+    e=0;
+fin:
+#if R_OSPL_IS_PREEMPTION
+    if ( IS( is_lock ) ) {
+        R_OSPL_End_T_Lock();
+    }
+#endif
+#ifndef R_OSPL_NDEBUG
+    if ( e != 0 ) {
+        R_DebugBreak( NULL, e );
+    }
+#endif
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_MODIFY_THREAD_LOCKED_COUNT
+************************************************************************/
+#if R_OSPL_ERROR_BREAK  &&  R_OSPL_IS_PREEMPTION
+void  R_OSPL_MODIFY_THREAD_LOCKED_COUNT( int_fast32_t Plus )
+{
+    r_ospl_error_t  *err;
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+
+    if ( err != NULL ) {
+        err->ThreadLockedCount += Plus;
+    }
+}
+#endif
+
+
+/***********************************************************************
+* Implement: R_OSPL_GET_THREAD_LOCKED_COUNT
+************************************************************************/
+#if R_OSPL_ERROR_BREAK  &&  R_OSPL_IS_PREEMPTION
+int_fast32_t  R_OSPL_GET_THREAD_LOCKED_COUNT(void)
+{
+    int_fast32_t  count;
+    r_ospl_error_t  *err;
+
+    err = R_OSPL_GetCurrentThreadError_Sub( R_OSPL_ALLOCATE_IF_NOT );
+
+    if ( err != NULL ) {
+        count = err->ThreadLockedCount;
+    } else {
+        count = 0;
+    }
+
+    return  count;
+}
+#endif
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/Images/BinaryImage_RZ_A1H.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,64 @@
+#ifndef  BINARYIMAGE_RZ_A1H_H
+#define  BINARYIMAGE_RZ_A1H_H
+
+#include "lcd_panel.h"
+
+#ifdef  __cplusplus
+extern "C" {  /* Start of C Symbol */
+#endif
+
+#if (LCD_VDC5_CH0_PANEL == LCD_CH0_PANEL_VKLCD70RT)
+extern const uint8_t  RGA_Sample_BinaryImage[ 0x0011BC08uL ];
+
+#define  Board_jpg_File                 ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00000000 ))
+#define  Board_wide_jpg_File            ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x000181A8 ))
+#define  TopScrn_jpg_File               ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00036BE0 ))
+#define  TstScrn_jpg_File               ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x000505F0 ))
+#define  CamScrn_jpg_File               ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00070168 ))
+#define  RetBtn_jpg_File                ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0007A998 ))
+#define  AutoBtn_jpg_File               ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0007CDC0 ))
+#define  ManualBtn_jpg_File             ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0007E908 ))
+#define  Usb_jpg_File                   ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x000804C8 ))
+#define  RCA_jpg_File                   ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00081540 ))
+#define  decs_wait_jpg_File             ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00082690 ))
+#define  decs_board_jpg_File            ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00083D98 ))
+#define  decs_swipe_jpg_File            ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00086D50 ))
+#define  decs_swipe_side_jpg_File       ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00089428 ))
+#define  animetion_timing_jpg_File      ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0008CEE0 ))
+#define  Crystal_png_ARGB8888           ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00093304 ))
+#define  Crystal_png_ARGB1555           ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x000A1600 ))
+#define  Crystal_png_ARGB4444           ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x000A8F20 ))
+#define  NoDevice_png_ARGB4444          ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x000B0840 ))
+#define  Crystal_png_File               ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00113660 ))
+#define  CrystalDither_png_File         ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00116C68 ))
+#else
+extern const uint8_t  RGA_Sample_BinaryImage[ 0x000553E0uL ];
+
+#define  Board_jpg_File                 ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00000000 ))
+#define  Board_wide_jpg_File            ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00006170 ))
+#define  TopScrn_jpg_File               ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0000ECD0 ))
+#define  TstScrn_jpg_File               ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00018390 ))
+#define  CamScrn_jpg_File               ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00024F68 ))
+#define  RetBtn_jpg_File                ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00028548 ))
+#define  AutoBtn_jpg_File               ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00029340 ))
+#define  ManualBtn_jpg_File             ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00029DE8 ))
+#define  Usb_jpg_File                   ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0002A888 ))
+#define  RCA_jpg_File                   ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0002B100 ))
+#define  decs_wait_jpg_File             ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0002B998 ))
+#define  decs_board_jpg_File            ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0002C350 ))
+#define  decs_swipe_jpg_File            ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0002D3E8 ))
+#define  decs_swipe_side_jpg_File       ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0002EAC0 ))
+#define  animetion_timing_jpg_File      ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00030D98 ))
+#define  Crystal_png_ARGB8888           ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00033A68 ))
+#define  Crystal_png_ARGB1555           ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00036AA0 ))
+#define  Crystal_png_ARGB4444           ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00038640 ))
+#define  NoDevice_png_ARGB4444          ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x0003A1E0 ))
+#define  Crystal_png_File               ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00052D80 ))
+#define  CrystalDither_png_File         ((const graphics_image_t*)( RGA_Sample_BinaryImage + 0x00053DC4 ))
+#endif
+
+#ifdef  __cplusplus
+ }  /* End of C Symbol */ 
+#endif
+
+#endif /* BINARYIMAGE_RZ_A1H_H */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/Images/BinaryImage_RZ_A1H_50RTA.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,21831 @@
+#include  "r_ospl.h"
+#include "lcd_panel.h"
+#if (LCD_VDC5_CH0_PANEL == LCD_CH0_PANEL_VKLCD50RTA)
+R_OSPL_ALIGNMENT( 0x20,
+const uint8_t  RGA_Sample_BinaryImage[0x000553E0uL] ) =
+{
+	0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60,
+	0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x22, 0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D,
+	0x00, 0x2A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x01, 0x12, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x02, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x04, 0x03, 0x02, 0x02,
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+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
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+	0x0A, 0x0A, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00, 0x92, 0x01, 0x7B, 0x03, 0x01, 0x22, 0x00, 0x02,
+	0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00, 0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+	0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03,
+	0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04,
+	0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81,
+	0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82,
+	0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36,
+	0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
+	0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76,
+	0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95,
+	0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3,
+	0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA,
+	0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
+	0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00,
+	0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4,
+	0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00,
+	0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51,
+	0x07, 0x61, 0x71, 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23,
+	0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18,
+	0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45,
+	0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65,
+	0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84,
+	0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2,
+	0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9,
+	0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7,
+	0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5,
+	0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11,
+	0x00, 0x3F, 0x00, 0xFD, 0xFC, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xAC, 0xE8, 0x75, 0xCF, 0xB4, 0xC8, 0xE9, 0x05, 0xB6, 0xE5, 0x56,
+	0xDB, 0xBB, 0xCC, 0xA7, 0xEB, 0x73, 0xDE, 0xC1, 0xA6, 0xCA, 0x74, 0xF5, 0xDD, 0x70, 0xCB, 0x88,
+	0x57, 0xD5, 0xAB, 0x83, 0xF1, 0x5F, 0x81, 0xBE, 0x24, 0x6B, 0xBF, 0x0D, 0xE1, 0xF0, 0xFF, 0x00,
+	0x86, 0x3C, 0x6D, 0x1F, 0x87, 0xB5, 0xA6, 0xDA, 0xF7, 0x17, 0xDF, 0x67, 0x59, 0xFF, 0x00, 0x8B,
+	0xE6, 0x50, 0xBF, 0x2F, 0xDE, 0xFE, 0xF5, 0x78, 0x59, 0xBE, 0x69, 0x8C, 0xC0, 0xE9, 0x86, 0xC3,
+	0xCA, 0xAB, 0xE5, 0x72, 0xB2, 0xB2, 0xBB, 0x4D, 0x25, 0x1B, 0xB6, 0x95, 0xDD, 0xDB, 0xF4, 0x4F,
+	0xAD, 0x93, 0xEA, 0xC2, 0xD0, 0xA5, 0x5A, 0x4B, 0xDA, 0x4D, 0x45, 0x5D, 0x2B, 0xBB, 0xE9, 0xE7,
+	0xA5, 0xDD, 0x97, 0x97, 0x73, 0xBA, 0x97, 0x56, 0x91, 0x15, 0x99, 0x6D, 0xD1, 0xB6, 0xFA, 0x49,
+	0xFF, 0x00, 0xD8, 0xD5, 0x33, 0xE3, 0x1B, 0x66, 0xB1, 0x6B, 0xE4, 0xB7, 0x56, 0x45, 0x66, 0x56,
+	0xDB, 0x27, 0xF1, 0x2F, 0xFC, 0x06, 0xBC, 0xCF, 0xE0, 0xAF, 0xC0, 0x1F, 0x8A, 0xFF, 0x00, 0x0F,
+	0xBC, 0x51, 0x73, 0xE2, 0xDF, 0x1E, 0x7C, 0x73, 0xD4, 0xFC, 0x40, 0x2E, 0x2D, 0xFC, 0xA5, 0xD2,
+	0x44, 0x2B, 0x1D, 0xAA, 0x37, 0xFC, 0xF4, 0xF9, 0x99, 0x9B, 0x77, 0xFB, 0xAC, 0xBD, 0x6B, 0xBE,
+	0xBE, 0xF0, 0xBE, 0xA1, 0xFD, 0x99, 0x35, 0xB5, 0x84, 0x51, 0xAB, 0x4A, 0xCC, 0xFF, 0x00, 0x7F,
+	0xF8, 0x9A, 0xB8, 0xB2, 0xFC, 0xD3, 0x3E, 0xC5, 0xE0, 0xDD, 0x7C, 0x46, 0x19, 0xD2, 0x95, 0xA5,
+	0xEE, 0x37, 0xCD, 0x2B, 0xAB, 0x72, 0xDA, 0xDA, 0x6B, 0xAE, 0x8D, 0x74, 0x5D, 0xCE, 0x9A, 0xF8,
+	0x5C, 0x0D, 0x3C, 0x47, 0xB3, 0x85, 0x5E, 0x75, 0xA7, 0xBC, 0xAE, 0x97, 0x9E, 0xEA, 0xFF, 0x00,
+	0x32, 0x3B, 0x9F, 0x8A, 0xBA, 0x75, 0xAC, 0x4B, 0x3C, 0x9A, 0x74, 0x9B, 0x19, 0xB0, 0xAC, 0xAF,
+	0xFF, 0x00, 0xD8, 0xD4, 0x53, 0xFC, 0x5F, 0xD2, 0xED, 0xE5, 0x8E, 0x16, 0xD3, 0x24, 0xDD, 0x27,
+	0xDD, 0xF9, 0xFF, 0x00, 0xFB, 0x1A, 0xC5, 0xD5, 0xBE, 0x1A, 0xF8, 0x8E, 0xE2, 0xCA, 0x0B, 0x7B,
+	0x65, 0x8D, 0x42, 0xFC, 0xD2, 0x23, 0x49, 0xFC, 0x55, 0xCE, 0x78, 0xC3, 0xC3, 0x97, 0x5E, 0x1B,
+	0xD4, 0x2D, 0x9F, 0x55, 0xBA, 0xFD, 0xC3, 0x7D, 0xD8, 0x56, 0x4F, 0x99, 0x7F, 0xDA, 0xAF, 0x98,
+	0xCC, 0x78, 0x93, 0x8B, 0x70, 0x34, 0xE5, 0x52, 0x58, 0x7B, 0x45, 0x72, 0xEA, 0xE2, 0xEC, 0xAF,
+	0xBE, 0xBD, 0xBF, 0xAB, 0x1E, 0xC6, 0x17, 0x2C, 0xC9, 0xF1, 0x12, 0x50, 0x8D, 0x4B, 0xB7, 0x7D,
+	0x13, 0xD7, 0xC8, 0xEF, 0x17, 0xE2, 0xF6, 0x9A, 0xF7, 0x2D, 0x66, 0x34, 0xA9, 0xBC, 0xC5, 0xFE,
+	0x1D, 0xC7, 0xFC, 0x2A, 0x38, 0x7E, 0x35, 0x69, 0x53, 0x2C, 0xCC, 0x9A, 0x4C, 0xFF, 0x00, 0xB9,
+	0xFB, 0xFF, 0x00, 0x31, 0xFF, 0x00, 0xE2, 0x6B, 0xC9, 0xDB, 0x59, 0xD3, 0xAD, 0x26, 0x6B, 0xEB,
+	0xFB, 0xD9, 0x59, 0x64, 0xDC, 0x63, 0x93, 0x77, 0x2B, 0xE9, 0x55, 0xA4, 0xD4, 0xE1, 0x8E, 0xDF,
+	0xEC, 0x70, 0xDC, 0xDC, 0x3D, 0xC5, 0xC6, 0xD5, 0x89, 0xA3, 0x6F, 0x9A, 0xBE, 0x72, 0x5E, 0x22,
+	0xF1, 0x03, 0xF8, 0x61, 0x17, 0x66, 0xFA, 0x74, 0x7F, 0x0F, 0x5D, 0x3C, 0xBB, 0xF9, 0x1E, 0x9B,
+	0xE1, 0x9C, 0x0C, 0x55, 0xE5, 0xCD, 0xD3, 0xEF, 0xEB, 0xD0, 0xF5, 0xE6, 0xF8, 0xDD, 0xA4, 0x2D,
+	0x8F, 0xDB, 0xC6, 0x91, 0x70, 0xCB, 0xFE, 0xCB, 0x1C, 0xFF, 0x00, 0xE8, 0x34, 0xAD, 0xF1, 0xB7,
+	0x4A, 0x45, 0x47, 0x3A, 0x2C, 0xF8, 0x93, 0xA7, 0xCD, 0xFF, 0x00, 0xD8, 0xD7, 0xC9, 0xFF, 0x00,
+	0x10, 0xBF, 0x6C, 0x7F, 0x83, 0xBF, 0x0C, 0xFC, 0x6A, 0x9E, 0x01, 0xD7, 0xF5, 0xAB, 0xE5, 0xBF,
+	0xB7, 0xB8, 0x66, 0xD5, 0x16, 0x3B, 0x76, 0x64, 0x8D, 0x76, 0xFC, 0xBB, 0xBF, 0xF1, 0xDA, 0xAD,
+	0xFF, 0x00, 0x0D, 0xE1, 0xFB, 0x3F, 0x4D, 0x32, 0xAA, 0x6B, 0x7A, 0x82, 0xC7, 0xE5, 0x36, 0xE5,
+	0x6B, 0x56, 0xDA, 0xCD, 0xBB, 0xFF, 0x00, 0xDA, 0xAE, 0xCA, 0x7C, 0x55, 0xC7, 0x95, 0xA2, 0xA5,
+	0x0C, 0x3E, 0x8D, 0x2F, 0xB0, 0xFE, 0xF5, 0xE4, 0xF6, 0xF2, 0xF3, 0x38, 0xE7, 0x96, 0xF0, 0xF5,
+	0x29, 0x38, 0xCE, 0xA6, 0xA9, 0xFF, 0x00, 0x31, 0xF6, 0x4D, 0xA7, 0xC5, 0x2B, 0x0B, 0xB3, 0x8F,
+	0xB0, 0xB2, 0xFC, 0xB9, 0xF9, 0xA4, 0xFF, 0x00, 0xEC, 0x6B, 0x42, 0x3F, 0x17, 0x5B, 0x4E, 0x9B,
+	0xD2, 0xDF, 0xFF, 0x00, 0x22, 0x57, 0xCA, 0xBF, 0x02, 0xFF, 0x00, 0x6A, 0x9F, 0x85, 0x7F, 0x18,
+	0xBC, 0x6D, 0xA9, 0x78, 0x2F, 0xC1, 0xFA, 0xAD, 0xC3, 0x4D, 0x6B, 0x6F, 0x1C, 0xFF, 0x00, 0x65,
+	0xBA, 0x46, 0x8D, 0xBC, 0xBD, 0xCC, 0xBB, 0x97, 0x77, 0xFB, 0x55, 0xEE, 0xBA, 0x7E, 0xA0, 0x9A,
+	0x7D, 0xBA, 0xA6, 0xCD, 0xEA, 0xBB, 0x99, 0xBE, 0x6F, 0x9A, 0xBE, 0x93, 0x2B, 0xE2, 0x3C, 0xFA,
+	0xB2, 0x71, 0xC5, 0x51, 0xE5, 0x6B, 0x7B, 0xC5, 0xAD, 0x7E, 0xED, 0xAD, 0xAD, 0xCF, 0x3B, 0x11,
+	0x97, 0xE5, 0xEA, 0x3C, 0xD4, 0xA5, 0x74, 0xFC, 0xC4, 0xF1, 0xC7, 0xED, 0x57, 0xF0, 0x8F, 0xE1,
+	0xC6, 0xB5, 0x0F, 0x86, 0xFC, 0x63, 0xE2, 0x6B, 0x3B, 0x3D, 0x42, 0xE1, 0x91, 0x6D, 0xEC, 0x64,
+	0xB8, 0xFD, 0xE4, 0x8C, 0xCD, 0xB5, 0x70, 0x36, 0xF7, 0x6A, 0xE7, 0x74, 0xDF, 0xDB, 0xE7, 0xE0,
+	0x26, 0xB1, 0xF1, 0x29, 0xBE, 0x11, 0xE9, 0x5E, 0x22, 0xB7, 0xB8, 0xD7, 0xA3, 0xB5, 0x69, 0xE7,
+	0xB1, 0x8E, 0x7F, 0x9A, 0x18, 0xD7, 0xAB, 0x37, 0xCB, 0xF2, 0xD7, 0xE3, 0x37, 0xFC, 0x17, 0x43,
+	0xFE, 0x0A, 0x31, 0xF1, 0xB3, 0xF6, 0x7E, 0xFD, 0xB0, 0x2E, 0xBE, 0x0E, 0x69, 0xB6, 0x7A, 0x1A,
+	0xDB, 0x47, 0x2D, 0x8E, 0xB9, 0x61, 0x79, 0x1B, 0x6E, 0x92, 0x19, 0x17, 0xE5, 0x8F, 0xCC, 0xF9,
+	0x7E, 0x56, 0x5D, 0xBF, 0x76, 0xB8, 0x3F, 0xD8, 0x57, 0xFE, 0x0A, 0xA1, 0xE2, 0xDF, 0x8F, 0xDF,
+	0xB4, 0x55, 0xE7, 0xFC, 0x27, 0x9A, 0x56, 0x8F, 0xA5, 0x6B, 0xD6, 0xFE, 0x19, 0xD4, 0x12, 0xC3,
+	0xC4, 0x16, 0xEA, 0xBE, 0x7D, 0xE4, 0x92, 0x79, 0x7B, 0x63, 0xDB, 0xB7, 0x6B, 0x7C, 0xAB, 0xFF,
+	0x00, 0x8E, 0xD6, 0xD8, 0xCC, 0x77, 0x13, 0x46, 0x8C, 0xF1, 0x34, 0xA7, 0x1F, 0x66, 0xAE, 0xEC,
+	0x96, 0xBA, 0x5F, 0xBA, 0xEB, 0x6F, 0xF8, 0x22, 0xC2, 0xD1, 0xCA, 0x2A, 0x72, 0xD2, 0x94, 0x65,
+	0xCE, 0xDF, 0x7B, 0x2B, 0x3D, 0x3B, 0xF4, 0x67, 0xF4, 0x23, 0x27, 0xC6, 0x3D, 0x29, 0x6D, 0x52,
+	0xED, 0x74, 0xFD, 0xD1, 0xC8, 0xDB, 0x55, 0x96, 0xE3, 0xFF, 0x00, 0xB1, 0xA6, 0xDF, 0x7C, 0x66,
+	0xD3, 0xAC, 0x26, 0x86, 0x19, 0xB4, 0x89, 0x1B, 0xCE, 0xFB, 0xAC, 0xB3, 0x7F, 0xF6, 0x35, 0xF2,
+	0x8F, 0xEC, 0xBF, 0xF1, 0xAB, 0x44, 0xF8, 0xDD, 0xF0, 0x7F, 0xC3, 0xFA, 0xCC, 0x3A, 0x94, 0x93,
+	0x5F, 0x59, 0xC4, 0xB1, 0xEA, 0xD2, 0x2F, 0xCA, 0xBE, 0x72, 0xAF, 0xCD, 0xF2, 0xD7, 0xA7, 0xDD,
+	0x4D, 0x6D, 0x79, 0xAC, 0x43, 0xE6, 0x6E, 0x45, 0xB7, 0xB5, 0xDD, 0xE5, 0xAC, 0xBF, 0x2D, 0x7C,
+	0x04, 0xBC, 0x40, 0xE2, 0xE9, 0xC5, 0xA8, 0xD3, 0x51, 0x77, 0x49, 0x5D, 0x6C, 0xF4, 0x6E, 0xE9,
+	0xAF, 0xCF, 0x63, 0xD7, 0x59, 0x1E, 0x53, 0x19, 0x6B, 0x26, 0xD6, 0xBD, 0x4F, 0x5B, 0x3F, 0x1C,
+	0x34, 0x84, 0xBB, 0xFB, 0x1B, 0x68, 0xB7, 0x0A, 0xDB, 0x73, 0xF3, 0x4A, 0xBC, 0xD4, 0x70, 0xFC,
+	0x7A, 0xD1, 0xA7, 0x92, 0x48, 0x53, 0x44, 0x9F, 0x7C, 0x6D, 0xB5, 0x97, 0xCE, 0x15, 0xE4, 0xB7,
+	0x4F, 0xA6, 0xDC, 0x6A, 0x4D, 0x7E, 0x9B, 0x95, 0x55, 0x57, 0x74, 0x6D, 0x2F, 0xF0, 0xD6, 0x3C,
+	0xDA, 0xB6, 0x8B, 0xA5, 0xB4, 0x9A, 0xA8, 0x79, 0x19, 0x66, 0xB8, 0x65, 0xDA, 0xD3, 0xFF, 0x00,
+	0x15, 0x79, 0xD8, 0xAF, 0x10, 0xB8, 0xD2, 0x84, 0xAF, 0x78, 0xF2, 0xDD, 0xEB, 0x65, 0xAA, 0xFF,
+	0x00, 0xC0, 0x7A, 0x3F, 0xF8, 0x28, 0xEB, 0xA7, 0xC3, 0xB9, 0x4C, 0x97, 0x5B, 0xFA, 0xBD, 0xCF,
+	0x6A, 0x1F, 0xB4, 0x56, 0x86, 0xD6, 0x32, 0x5F, 0xA6, 0x87, 0x36, 0xD8, 0xFE, 0xF2, 0xF9, 0xE3,
+	0x3F, 0xCA, 0xA1, 0xB8, 0xFD, 0xA5, 0x7C, 0x3F, 0x6F, 0x63, 0xFD, 0xA0, 0xFA, 0x14, 0xCD, 0x1E,
+	0xE5, 0x5F, 0xF8, 0xF8, 0x1F, 0xC5, 0xF8, 0x57, 0x88, 0xC1, 0xA8, 0x68, 0x51, 0xE9, 0x73, 0x69,
+	0x53, 0x5C, 0xAB, 0x7D, 0xA2, 0x26, 0x56, 0xDD, 0x71, 0xF3, 0x46, 0xD5, 0x5F, 0x52, 0x93, 0xC3,
+	0x70, 0xE9, 0x4B, 0xA7, 0x4D, 0x74, 0xB2, 0x2F, 0x9A, 0xAD, 0xE6, 0x2D, 0xC7, 0xCC, 0xB5, 0xE4,
+	0x54, 0xF1, 0x23, 0x8F, 0xD5, 0x1E, 0x78, 0xD4, 0x82, 0xD3, 0x5F, 0x76, 0x3A, 0x4B, 0xEE, 0xD9,
+	0xA3, 0xA2, 0x3C, 0x39, 0x92, 0xF3, 0x59, 0xC6, 0x5F, 0x7B, 0x3D, 0xEE, 0x6F, 0xDA, 0x23, 0x46,
+	0x48, 0x63, 0xB8, 0x4D, 0x0E, 0x57, 0x49, 0x3F, 0x89, 0x6E, 0x07, 0xCB, 0xFF, 0x00, 0x8E, 0xD4,
+	0xAD, 0xF1, 0xEB, 0x4D, 0x47, 0x54, 0x4D, 0x09, 0xD9, 0x0A, 0x67, 0xCC, 0x5B, 0x85, 0xDB, 0xFF,
+	0x00, 0xA0, 0xD7, 0xCD, 0x7A, 0xF7, 0x8C, 0xBC, 0x19, 0xE1, 0x38, 0x63, 0xFF, 0x00, 0x84, 0x83,
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+	0x13, 0x69, 0xD6, 0xDE, 0x25, 0xD4, 0x3E, 0xCD, 0x66, 0xDB, 0xB5, 0x26, 0xFB, 0x54, 0xD1, 0x32,
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+	0xD5, 0x3A, 0x75, 0xD5, 0xA7, 0x8A, 0xF5, 0x6F, 0x15, 0xDD, 0x5D, 0x35, 0xAD, 0xC6, 0xE5, 0x5B,
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+	0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60,
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+	0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
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+	0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7,
+	0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5,
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+	0xD1, 0x22, 0x11, 0x86, 0x57, 0x91, 0x91, 0x12, 0x55, 0x66, 0x7D, 0xC9, 0xB5, 0x62, 0x70, 0x3E,
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+	0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2,
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+	0x0B, 0x3E, 0xD5, 0xB3, 0x47, 0xB5, 0xD0, 0xC6, 0xAB, 0xE4, 0xC6, 0xEE, 0x3C, 0xEB, 0x99, 0x66,
+	0x9A, 0x1D, 0xD2, 0x0D, 0xDB, 0x5B, 0x62, 0x43, 0x84, 0x3B, 0x43, 0x2F, 0x9B, 0x2F, 0x24, 0x36,
+	0x07, 0xC8, 0x55, 0xF5, 0x17, 0xFC, 0x15, 0xAB, 0xFE, 0x4E, 0x37, 0x45, 0xFF, 0x00, 0xB1, 0x26,
+	0xDB, 0xFF, 0x00, 0x4B, 0x2F, 0x2B, 0xE5, 0xDA, 0xFE, 0x80, 0xE1, 0x5A, 0x70, 0xA7, 0xC3, 0xF8,
+	0x75, 0x15, 0x6B, 0xC6, 0xFF, 0x00, 0x36, 0xDD, 0xCF, 0xF3, 0xDF, 0xC5, 0x8A, 0xF5, 0xAB, 0xF8,
+	0x87, 0x98, 0x3A, 0x92, 0x6E, 0xD3, 0xB2, 0xBF, 0x44, 0xA2, 0x92, 0x5E, 0x89, 0x05, 0x14, 0x57,
+	0xB4, 0x7C, 0x67, 0xFD, 0x86, 0x7E, 0x2F, 0x7C, 0x0F, 0xF8, 0x4B, 0x67, 0xF1, 0x77, 0xC5, 0x37,
+	0x9A, 0x6C, 0xD6, 0x77, 0x0D, 0x6E, 0xB7, 0x96, 0x56, 0x8D, 0x21, 0x9E, 0xC4, 0xCA, 0x99, 0x1E,
+	0x68, 0x64, 0x0B, 0xC3, 0x61, 0x0E, 0x09, 0xF9, 0x98, 0x75, 0x07, 0x35, 0xEB, 0x57, 0xC6, 0xE1,
+	0x70, 0xB5, 0x21, 0x4E, 0xAC, 0xD2, 0x94, 0xDD, 0xA2, 0x9F, 0x57, 0xD9, 0x7D, 0xE7, 0xC7, 0xE0,
+	0x72, 0x5C, 0xDB, 0x34, 0xC2, 0xD7, 0xC4, 0xE1, 0x68, 0xCA, 0x70, 0xA1, 0x1E, 0x6A, 0x8D, 0x6D,
+	0x18, 0xBB, 0xEA, 0xFE, 0xE7, 0xF2, 0x4D, 0xEC, 0x8F, 0x17, 0xA2, 0xBD, 0x9F, 0xE1, 0x3F, 0xEC,
+	0x5F, 0xE2, 0x3F, 0x8A, 0x3F, 0x09, 0xA3, 0xF8, 0xC9, 0x73, 0xF1, 0x5F, 0xC2, 0x3E, 0x1B, 0xD1,
+	0xE5, 0xBE, 0x7B, 0x45, 0x93, 0xC4, 0x7A, 0x83, 0xDB, 0x81, 0x22, 0xB6, 0x30, 0x58, 0xA1, 0x5E,
+	0x4F, 0x41, 0x9C, 0x9A, 0x4B, 0xEF, 0xD8, 0x6F, 0xE2, 0xE6, 0x93, 0xF1, 0xDF, 0x43, 0xF8, 0x0D,
+	0xAA, 0xEA, 0x7A, 0x3C, 0x77, 0x5E, 0x22, 0xB4, 0x9A, 0xE7, 0x48, 0xD6, 0x62, 0xB8, 0x79, 0x2C,
+	0xA7, 0x8A, 0x38, 0x64, 0x95, 0x88, 0x60, 0x9B, 0xB3, 0x88, 0xC8, 0xC1, 0x5C, 0xE4, 0xA9, 0xE8,
+	0x41, 0xAE, 0x67, 0x9C, 0xE5, 0x71, 0xA9, 0x3A, 0x6E, 0xAA, 0xBC, 0x39, 0xAE, 0xB5, 0xD3, 0x97,
+	0x59, 0x74, 0xD6, 0xCB, 0x57, 0x6B, 0x9E, 0xA4, 0x78, 0x2F, 0x8A, 0x25, 0x86, 0xA3, 0x88, 0x8E,
+	0x16, 0x4E, 0x15, 0x9C, 0x14, 0x1A, 0xB3, 0xBF, 0xB4, 0x76, 0xA7, 0xD6, 0xE9, 0x4D, 0xE9, 0x17,
+	0x2B, 0x26, 0xF4, 0x3C, 0x66, 0xBD, 0x1B, 0xE1, 0x1F, 0xC2, 0x5F, 0x83, 0xBE, 0x3B, 0xF0, 0xCC,
+	0xDA, 0xC7, 0xC4, 0x0F, 0xDA, 0x3F, 0x4F, 0xF0, 0x8D, 0xEC, 0x77, 0xAD, 0x0C, 0x7A, 0x65, 0xD6,
+	0x85, 0x3D, 0xCB, 0x49, 0x18, 0x54, 0x22, 0x5D, 0xD1, 0x90, 0x00, 0x25, 0x99, 0x71, 0xD7, 0xE4,
+	0xF7, 0xA8, 0xFC, 0x53, 0xFB, 0x2F, 0x7C, 0x62, 0xF0, 0xAF, 0xC6, 0xD8, 0xFE, 0x01, 0x5C, 0x78,
+	0x65, 0xAE, 0x35, 0xEB, 0x99, 0xD5, 0x6C, 0x3E, 0xCD, 0x93, 0x0D, 0xD4, 0x47, 0x38, 0x9D, 0x1C,
+	0x81, 0xFB, 0xAC, 0x02, 0x4B, 0x1C, 0x6D, 0xDA, 0xDB, 0xB0, 0x54, 0x81, 0x1F, 0xED, 0x19, 0xFB,
+	0x3D, 0x78, 0xAB, 0xF6, 0x69, 0xF1, 0xD5, 0xBF, 0x80, 0x7C, 0x61, 0xAC, 0x69, 0xF7, 0xD7, 0x57,
+	0x1A, 0x5C, 0x77, 0xCB, 0x36, 0x9A, 0xCE, 0x63, 0x08, 0xF2, 0x48, 0x81, 0x7E, 0x75, 0x53, 0x9C,
+	0xC6, 0x7B, 0x63, 0x04, 0x53, 0xA9, 0x8B, 0xC3, 0x62, 0xB9, 0x28, 0xD1, 0xAF, 0xCB, 0x29, 0xAE,
+	0x68, 0xF2, 0xF2, 0xB6, 0xE3, 0xDF, 0x54, 0xD5, 0xBE, 0x5E, 0x84, 0xE1, 0xB2, 0x8C, 0xCB, 0x29,
+	0xF6, 0xD8, 0xCC, 0x6E, 0x03, 0xDA, 0x52, 0xA3, 0x2F, 0x67, 0x35, 0x53, 0x9E, 0x31, 0x8C, 0xDE,
+	0xC9, 0xB8, 0x4A, 0x12, 0xE6, 0x56, 0xD9, 0x3B, 0x6A, 0xAE, 0xB5, 0x46, 0xB7, 0xC7, 0x5F, 0xD9,
+	0xD3, 0xC3, 0x7F, 0x0A, 0x3C, 0x05, 0xE1, 0xFF, 0x00, 0x89, 0x1E, 0x0C, 0xF8, 0xBD, 0x6B, 0xE2,
+	0xDD, 0x2F, 0xC4, 0x37, 0x77, 0x36, 0xF6, 0xF7, 0x16, 0xBA, 0x4C, 0x96, 0xA1, 0x1A, 0x1D, 0xA1,
+	0xBE, 0xFB, 0x12, 0x79, 0x24, 0x74, 0x1D, 0x3B, 0xD7, 0xD3, 0xDF, 0xF0, 0x48, 0xDF, 0x1F, 0xF8,
+	0x93, 0x5A, 0xF0, 0x1F, 0x8B, 0x3E, 0x1D, 0x6A, 0x57, 0x3E, 0x76, 0x9F, 0xA0, 0xDF, 0x5A, 0xDC,
+	0xE9, 0x7E, 0x63, 0xBB, 0x34, 0x3F, 0x6A, 0x13, 0x79, 0x91, 0x8C, 0xB1, 0x55, 0x8F, 0x74, 0x01,
+	0xC2, 0xA8, 0x1F, 0x3C, 0xB2, 0x31, 0x24, 0xB7, 0x1F, 0x2D, 0xF8, 0xEB, 0xE2, 0x87, 0x84, 0xB5,
+	0xEF, 0xD9, 0x7F, 0xC0, 0x9F, 0x0B, 0x74, 0xEB, 0x99, 0x9B, 0x58, 0xD0, 0x75, 0x6D, 0x4E, 0x7D,
+	0x4A, 0x26, 0x80, 0x84, 0x54, 0x9A, 0x40, 0xD1, 0x90, 0xDD, 0x1B, 0x23, 0xD3, 0xA5, 0x7D, 0x15,
+	0xFF, 0x00, 0x04, 0x78, 0xFF, 0x00, 0x9A, 0x89, 0xFF, 0x00, 0x70, 0x8F, 0xFD, 0xBD, 0xAF, 0x97,
+	0xE2, 0x48, 0x62, 0x25, 0xC2, 0x75, 0xFE, 0xB3, 0x79, 0x4A, 0x33, 0xD1, 0xB4, 0x93, 0xB2, 0xA9,
+	0xCB, 0x17, 0xA2, 0x4B, 0x58, 0xBD, 0xD2, 0xD5, 0x33, 0xF5, 0x2F, 0x0D, 0x6B, 0x65, 0xF4, 0x7C,
+	0x5A, 0xC0, 0xFF, 0x00, 0x66, 0x25, 0x0A, 0x55, 0x69, 0x7B, 0xD1, 0x84, 0xA5, 0x28, 0xA9, 0x3C,
+	0x33, 0x9C, 0xE1, 0x79, 0x4A, 0x52, 0xF7, 0x6A, 0x2D, 0x9C, 0x9B, 0x4D, 0x5B, 0xA1, 0xF6, 0xC5,
+	0x14, 0x51, 0x5F, 0x8C, 0x9F, 0xDA, 0x81, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45,
+	0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45,
+	0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45,
+	0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45,
+	0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45,
+	0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45,
+	0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x07, 0xE7, 0x8F, 0xFC, 0x15, 0xAB, 0xFE, 0x4E, 0x37, 0x45,
+	0xFF, 0x00, 0xB1, 0x26, 0xDB, 0xFF, 0x00, 0x4B, 0x2F, 0x2B, 0xE5, 0xDA, 0xFA, 0x8B, 0xFE, 0x0A,
+	0xD5, 0xFF, 0x00, 0x27, 0x1B, 0xA2, 0xFF, 0x00, 0xD8, 0x93, 0x6D, 0xFF, 0x00, 0xA5, 0x97, 0x95,
+	0xF2, 0xED, 0x7F, 0x41, 0x70, 0xBF, 0xFC, 0x93, 0xF8, 0x7F, 0xF0, 0xFF, 0x00, 0x99, 0xFE, 0x78,
+	0xF8, 0xA5, 0xFF, 0x00, 0x27, 0x0B, 0x31, 0xFF, 0x00, 0xAF, 0x8F, 0xF2, 0x47, 0xAF, 0x7E, 0xC3,
+	0x5F, 0x07, 0x87, 0xC6, 0x5F, 0xDA, 0x33, 0x45, 0xD2, 0xAF, 0xAD, 0x7C, 0xCD, 0x2F, 0x49, 0x7F,
+	0xED, 0x5D, 0x5B, 0x72, 0xFC, 0xBE, 0x4C, 0x24, 0x15, 0x53, 0xEC, 0xD2, 0x18, 0xD0, 0xFB, 0x31,
+	0xF4, 0xAF, 0xAF, 0x34, 0x0F, 0x11, 0x7C, 0x2B, 0xF8, 0xE3, 0xF1, 0x0F, 0xE2, 0x07, 0xC3, 0xED,
+	0x4B, 0xF6, 0x89, 0xF0, 0xFE, 0xBF, 0xA7, 0xFC, 0x43, 0xB3, 0x5B, 0x6D, 0x23, 0xC3, 0xF6, 0x91,
+	0xC9, 0xE6, 0xD8, 0x3C, 0x10, 0x90, 0xAF, 0x19, 0x6F, 0x95, 0x9B, 0x0B, 0xE6, 0x1C, 0x75, 0x64,
+	0x04, 0x57, 0xE7, 0xCF, 0x86, 0x7C, 0x61, 0xE3, 0x4F, 0x09, 0x1B, 0x96, 0xF0, 0x77, 0x8A, 0x35,
+	0x4D, 0x30, 0xDC, 0xC3, 0xB2, 0xF0, 0xE9, 0x97, 0xD2, 0x43, 0xE6, 0xC7, 0xFD, 0xD7, 0xD8, 0x46,
+	0xE5, 0xE7, 0xA1, 0xE2, 0xAB, 0xE9, 0x37, 0xBE, 0x21, 0xF0, 0xF6, 0xAB, 0x1E, 0xAB, 0xA1, 0xDD,
+	0xDE, 0x58, 0xDF, 0x59, 0x9F, 0x36, 0x2B, 0x9B, 0x49, 0x1E, 0x29, 0x60, 0xFF, 0x00, 0x6C, 0x32,
+	0xE0, 0xAF, 0x5E, 0xBC, 0x75, 0xAE, 0x7C, 0xD7, 0x22, 0xAD, 0x99, 0xE2, 0xA5, 0x55, 0xD6, 0xE5,
+	0xB4, 0x52, 0x82, 0x49, 0x3B, 0x34, 0xF9, 0xAE, 0xEE, 0xBF, 0x99, 0x47, 0xE1, 0xB3, 0xB2, 0xB5,
+	0xF5, 0x3D, 0x1E, 0x13, 0xE3, 0xEC, 0x1F, 0x0B, 0xE5, 0x74, 0xB0, 0x91, 0xC1, 0xFB, 0x5E, 0x6A,
+	0x92, 0x9D, 0x67, 0x29, 0x49, 0x73, 0x45, 0xC1, 0xD3, 0x50, 0x8A, 0x8B, 0x49, 0xA5, 0x4E, 0x55,
+	0x34, 0x9A, 0x92, 0xE6, 0x95, 0xED, 0xA1, 0xF6, 0xA7, 0x83, 0xBF, 0xE1, 0x13, 0xF8, 0x1D, 0xFB,
+	0x0A, 0x4D, 0xA2, 0x7C, 0x78, 0xF8, 0x63, 0xFF, 0x00, 0x09, 0x15, 0xA6, 0x93, 0xF1, 0x02, 0x7B,
+	0x1D, 0x4F, 0x49, 0xFB, 0x63, 0x41, 0xB6, 0x45, 0x9C, 0xA9, 0x95, 0x58, 0x0F, 0x9B, 0x6E, 0x09,
+	0x03, 0x80, 0xD9, 0x1C, 0x81, 0xCD, 0x75, 0xFE, 0x20, 0xB5, 0xD7, 0x35, 0x0F, 0xDB, 0xA7, 0xE0,
+	0xE7, 0x8C, 0xB4, 0x7B, 0xDB, 0x6B, 0x8F, 0x03, 0xDF, 0x78, 0x6E, 0xF4, 0x78, 0x48, 0x59, 0xDB,
+	0xEC, 0x48, 0x17, 0xFB, 0x36, 0x66, 0x74, 0x3C, 0x9C, 0x92, 0xA6, 0x26, 0x07, 0x81, 0xB7, 0x0A,
+	0x06, 0x50, 0x93, 0xF1, 0xF7, 0x8B, 0x63, 0xF8, 0x9D, 0xAD, 0xFC, 0x04, 0xD2, 0x7C, 0x73, 0xAC,
+	0x7C, 0x54, 0xF1, 0x26, 0xB1, 0x0E, 0xBD, 0xE2, 0x2B, 0xD8, 0x2E, 0xB4, 0x5B, 0xAB, 0xE9, 0xA6,
+	0x84, 0x3D, 0xB4, 0x70, 0xB0, 0x9C, 0x86, 0x72, 0x19, 0x88, 0x93, 0x19, 0x2B, 0x90, 0x14, 0x73,
+	0x5C, 0xAE, 0x95, 0xF1, 0x47, 0xE2, 0xFC, 0x50, 0xE9, 0xFA, 0x46, 0x89, 0xF1, 0x13, 0xC4, 0x8B,
+	0x1E, 0x94, 0x59, 0xB4, 0x9B, 0x5B, 0x5D, 0x5E, 0xE0, 0x2D, 0x99, 0x28, 0xCA, 0x4C, 0x4A, 0xAD,
+	0xFB, 0xBF, 0x91, 0x9D, 0x4E, 0xD0, 0x3E, 0x56, 0x61, 0xD0, 0x9A, 0xF3, 0x17, 0x0E, 0xD4, 0xC4,
+	0x7B, 0x5A, 0xD1, 0xAA, 0xB9, 0xA4, 0xEB, 0x29, 0x6F, 0xCA, 0xB9, 0xD7, 0x2B, 0xB2, 0x7B, 0x35,
+	0x25, 0xBA, 0xF8, 0x96, 0x97, 0xD8, 0xFA, 0x79, 0xF8, 0x8D, 0x87, 0xCB, 0x7E, 0xAB, 0x84, 0x9E,
+	0x12, 0x4A, 0x95, 0x28, 0xE0, 0xE7, 0x0B, 0x38, 0x73, 0xCB, 0xD8, 0xCD, 0x54, 0x4A, 0x72, 0x8A,
+	0xF7, 0xE3, 0x38, 0x35, 0x68, 0xC9, 0xBE, 0x49, 0xDA, 0x49, 0x27, 0x74, 0x7D, 0x51, 0xF1, 0x33,
+	0xFE, 0x0A, 0x17, 0xAD, 0xF8, 0x3F, 0x56, 0xF1, 0xAF, 0x81, 0x5B, 0xC2, 0x76, 0xF3, 0x78, 0xCB,
+	0x49, 0xF1, 0x56, 0xA5, 0xA4, 0x78, 0x6F, 0xC4, 0xED, 0x6F, 0x19, 0xFB, 0x2E, 0x9A, 0xD7, 0x6E,
+	0x19, 0x4E, 0x79, 0xDE, 0x82, 0x38, 0xD5, 0x40, 0x1B, 0x5B, 0x0A, 0xCD, 0x92, 0x87, 0x7F, 0x21,
+	0xFF, 0x00, 0x05, 0x62, 0xFF, 0x00, 0x93, 0x93, 0xD2, 0xFF, 0x00, 0xEC, 0x4E, 0xB5, 0xFF, 0x00,
+	0xD2, 0x9B, 0xAA, 0xF9, 0xAE, 0x7B, 0xAD, 0x63, 0x5E, 0xD5, 0xA4, 0xBE, 0xB9, 0xB8, 0xB9, 0xBD,
+	0xBE, 0xBB, 0x9D, 0xA5, 0x9A, 0x69, 0x19, 0xA4, 0x9A, 0x69, 0x18, 0xEE, 0x67, 0x24, 0xE5, 0x99,
+	0x89, 0xC9, 0x24, 0xF2, 0x4F, 0x35, 0xDB, 0xFE, 0xD0, 0x3E, 0x1F, 0xF1, 0x4E, 0x8F, 0x79, 0xE1,
+	0x5D, 0x5F, 0xC6, 0x1E, 0x3B, 0xD5, 0xB5, 0xFB, 0xDD, 0x7B, 0xC1, 0xB6, 0xBA, 0x9B, 0x4D, 0xAC,
+	0x4C, 0xF2, 0x4B, 0x6A, 0x24, 0x96, 0x65, 0xFB, 0x38, 0x67, 0x66, 0x25, 0x54, 0xA1, 0x3D, 0xB9,
+	0x63, 0xC0, 0xAF, 0x47, 0x0B, 0x91, 0xE0, 0xB2, 0xDC, 0xCA, 0x85, 0x4A, 0x56, 0x8B, 0xB4, 0xD3,
+	0x5A, 0xFB, 0xCD, 0xA8, 0xED, 0xD9, 0x2B, 0x37, 0x6D, 0xAE, 0xDD, 0x8F, 0x9D, 0xCD, 0x38, 0xF3,
+	0x3C, 0xE2, 0x6E, 0x1B, 0xC7, 0x61, 0xB1, 0x9C, 0xD3, 0x87, 0x3D, 0x29, 0x46, 0x4D, 0xA4, 0xA1,
+	0x18, 0xCA, 0x7A, 0x4B, 0x67, 0x39, 0x4B, 0x9E, 0x31, 0x72, 0xD5, 0xDA, 0x0A, 0xFA, 0x24, 0x79,
+	0xFD, 0x7D, 0xB1, 0xFF, 0x00, 0x04, 0x78, 0xFF, 0x00, 0x9A, 0x89, 0xFF, 0x00, 0x70, 0x8F, 0xFD,
+	0xBD, 0xAF, 0x89, 0xEB, 0xED, 0x8F, 0xF8, 0x23, 0xC7, 0xFC, 0xD4, 0x4F, 0xFB, 0x84, 0x7F, 0xED,
+	0xED, 0x1C, 0x69, 0xFF, 0x00, 0x24, 0xD5, 0x7F, 0xFB, 0x77, 0xFF, 0x00, 0x4B, 0x88, 0xBC, 0x15,
+	0xFF, 0x00, 0x93, 0x99, 0x80, 0xFF, 0x00, 0xB8, 0xBF, 0xFA, 0x66, 0xA1, 0xF6, 0xC5, 0x14, 0x51,
+	0x5F, 0x83, 0x9F, 0xDF, 0x21, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50,
+	0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50,
+	0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50,
+	0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x13,
+	0x81, 0x93, 0x40, 0x05, 0x15, 0xE1, 0x7F, 0x1C, 0x7F, 0xE0, 0xA6, 0xDF, 0xF0, 0x4F, 0xFF, 0x00,
+	0xD9, 0xC0, 0x88, 0xBE, 0x30, 0xFE, 0xD6, 0xBE, 0x0B, 0xD3, 0x6E, 0x3C, 0xC7, 0x43, 0x63, 0x6B,
+	0xAB, 0x2D, 0xF5, 0xD2, 0xB2, 0xFD, 0xE0, 0xD0, 0x5A, 0xF9, 0x92, 0xAE, 0x3D, 0xD4, 0x73, 0xC5,
+	0x7C, 0xE7, 0xE3, 0x3F, 0xF8, 0x39, 0x8F, 0xFE, 0x09, 0x59, 0xE1, 0x5B, 0xC9, 0xAC, 0xF4, 0xAF,
+	0x1F, 0xF8, 0xB3, 0xC4, 0x1E, 0x4C, 0x8C, 0x9E, 0x6E, 0x8B, 0xE0, 0xF9, 0xC2, 0x3E, 0x1B, 0x1B,
+	0x94, 0xDC, 0x18, 0xB2, 0x0F, 0x50, 0x7D, 0x3D, 0xF8, 0xAF, 0x5B, 0x0B, 0x90, 0x67, 0x98, 0xC8,
+	0xA9, 0x51, 0xC3, 0x4E, 0x49, 0xF5, 0x51, 0x76, 0xFB, 0xED, 0x6F, 0xC4, 0xCE, 0x55, 0x69, 0xC5,
+	0xD9, 0xB4, 0x7E, 0x80, 0x51, 0x5F, 0x9A, 0x6D, 0xFF, 0x00, 0x07, 0x54, 0xFF, 0x00, 0xC1, 0x35,
+	0x81, 0xC0, 0xF0, 0x5F, 0xC5, 0x83, 0xEE, 0x3C, 0x2F, 0x65, 0xCF, 0xFE, 0x4F, 0x51, 0xFF, 0x00,
+	0x11, 0x55, 0x7F, 0xC1, 0x35, 0xFF, 0x00, 0xE8, 0x4A, 0xF8, 0xB1, 0xFF, 0x00, 0x84, 0xBD, 0x8F,
+	0xFF, 0x00, 0x27, 0x57, 0xA5, 0xFE, 0xA5, 0xF1, 0x47, 0xFD, 0x02, 0xCB, 0xEF, 0x8F, 0xF9, 0x93,
+	0xF5, 0x8A, 0x3F, 0xCC, 0x7E, 0x96, 0x51, 0x5F, 0x9A, 0x7F, 0xF1, 0x15, 0x57, 0xFC, 0x13, 0x5F,
+	0xFE, 0x84, 0xAF, 0x8B, 0x1F, 0xF8, 0x4B, 0xD8, 0xFF, 0x00, 0xF2, 0x75, 0x1F, 0xF1, 0x15, 0x57,
+	0xFC, 0x13, 0x5F, 0xFE, 0x84, 0xAF, 0x8B, 0x1F, 0xF8, 0x4B, 0xD8, 0xFF, 0x00, 0xF2, 0x75, 0x1F,
+	0xEA, 0x5F, 0x14, 0x7F, 0xD0, 0x2C, 0xBE, 0xF8, 0xFF, 0x00, 0x98, 0x7D, 0x62, 0x8F, 0xF3, 0x1F,
+	0xA5, 0x94, 0x57, 0xE6, 0x9F, 0xFC, 0x45, 0x55, 0xFF, 0x00, 0x04, 0xD7, 0xFF, 0x00, 0xA1, 0x2B,
+	0xE2, 0xC7, 0xFE, 0x12, 0xF6, 0x3F, 0xFC, 0x9D, 0x47, 0xFC, 0x45, 0x55, 0xFF, 0x00, 0x04, 0xD7,
+	0xFF, 0x00, 0xA1, 0x2B, 0xE2, 0xC7, 0xFE, 0x12, 0xF6, 0x3F, 0xFC, 0x9D, 0x47, 0xFA, 0x97, 0xC5,
+	0x1F, 0xF4, 0x0B, 0x2F, 0xBE, 0x3F, 0xE6, 0x1F, 0x58, 0xA3, 0xFC, 0xC7, 0xE9, 0x65, 0x15, 0xF9,
+	0xA7, 0xFF, 0x00, 0x11, 0x55, 0x7F, 0xC1, 0x35, 0xFF, 0x00, 0xE8, 0x4A, 0xF8, 0xB1, 0xFF, 0x00,
+	0x84, 0xBD, 0x8F, 0xFF, 0x00, 0x27, 0x51, 0xFF, 0x00, 0x11, 0x55, 0x7F, 0xC1, 0x35, 0xFF, 0x00,
+	0xE8, 0x4A, 0xF8, 0xB1, 0xFF, 0x00, 0x84, 0xBD, 0x8F, 0xFF, 0x00, 0x27, 0x51, 0xFE, 0xA5, 0xF1,
+	0x47, 0xFD, 0x02, 0xCB, 0xEF, 0x8F, 0xF9, 0x87, 0xD6, 0x28, 0xFF, 0x00, 0x31, 0xFA, 0x59, 0x45,
+	0x7E, 0x7C, 0xF8, 0x1F, 0xFE, 0x0E, 0x6C, 0xFF, 0x00, 0x82, 0x59, 0x78, 0xBA, 0xF6, 0xDE, 0xCB,
+	0x57, 0xF1, 0x7F, 0x8C, 0xBC, 0x39, 0xE7, 0xCC, 0x91, 0x99, 0xB5, 0xCF, 0x08, 0xC8, 0x52, 0x2D,
+	0xDF, 0xC4, 0xC6, 0xD9, 0xE6, 0xC2, 0x8E, 0xF8, 0xCF, 0xE2, 0x39, 0xAF, 0xA0, 0xBE, 0x17, 0x7F,
+	0xC1, 0x50, 0xFF, 0x00, 0x63, 0x1F, 0x8F, 0xEF, 0x05, 0xAF, 0xEC, 0xDF, 0xF1, 0x73, 0x4D, 0xF1,
+	0xFD, 0xEC, 0xCA, 0xCC, 0xDA, 0x46, 0x85, 0xAA, 0x59, 0xDB, 0xEA, 0x11, 0xE3, 0xA7, 0xFA, 0x25,
+	0xFC, 0xF6, 0xF3, 0xB9, 0x6E, 0x70, 0x23, 0x47, 0x3F, 0x2F, 0x38, 0xCA, 0xE7, 0xCE, 0xC5, 0x70,
+	0xFE, 0x79, 0x81, 0x8B, 0x95, 0x7C, 0x34, 0xE3, 0x15, 0xBB, 0xE5, 0x76, 0xFB, 0xED, 0x6F, 0xC4,
+	0xA5, 0x5A, 0x8C, 0xB6, 0x92, 0x3E, 0x84, 0xA2, 0xBE, 0x65, 0xF8, 0x8D, 0xFF, 0x00, 0x05, 0x72,
+	0xFD, 0x8B, 0x7E, 0x04, 0xEA, 0x51, 0x69, 0x3F, 0xB4, 0xEF, 0x88, 0xFC, 0x55, 0xF0, 0xA6, 0x4B,
+	0x89, 0x44, 0x76, 0xD7, 0x1F, 0x11, 0x3C, 0x07, 0xA9, 0xE9, 0xF6, 0x73, 0x12, 0x70, 0x0A, 0xDE,
+	0x79, 0x0D, 0x6B, 0x8C, 0x91, 0xC9, 0x94, 0x0C, 0xF1, 0xD4, 0x30, 0x1E, 0xAD, 0xF0, 0x4B, 0xF6,
+	0xBB, 0xFD, 0x95, 0xFF, 0x00, 0x69, 0x3B, 0x38, 0xEF, 0xBF, 0x67, 0xFF, 0x00, 0xDA, 0x33, 0xC1,
+	0x3E, 0x32, 0x59, 0x97, 0x72, 0x2F, 0x86, 0xFC, 0x4D, 0x6B, 0x79, 0x26, 0x30, 0x4E, 0x4A, 0x46,
+	0xE5, 0x87, 0x00, 0x9E, 0x40, 0xE0, 0x67, 0xA5, 0x79, 0x16, 0x76, 0xB9, 0xA1, 0xE8, 0x94, 0x51,
+	0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x7E, 0x78, 0xFF, 0x00, 0xC1, 0x5A, 0xBF, 0xE4, 0xE3, 0x74,
+	0x5F, 0xFB, 0x12, 0x6D, 0xBF, 0xF4, 0xB2, 0xF2, 0xBE, 0x5D, 0xAF, 0xA8, 0xBF, 0xE0, 0xAD, 0x5F,
+	0xF2, 0x71, 0xBA, 0x2F, 0xFD, 0x89, 0x36, 0xDF, 0xFA, 0x59, 0x79, 0x5F, 0x2E, 0xD7, 0xF4, 0x17,
+	0x0B, 0xFF, 0x00, 0xC9, 0x3F, 0x87, 0xFF, 0x00, 0x0F, 0xF9, 0x9F, 0xE7, 0x8F, 0x8A, 0x5F, 0xF2,
+	0x70, 0xB3, 0x1F, 0xFA, 0xF8, 0xFF, 0x00, 0x24, 0x7A, 0xE7, 0xEC, 0x8F, 0xAF, 0xDE, 0xF8, 0x62,
+	0xEF, 0xE2, 0x16, 0xB9, 0xA6, 0x5E, 0xAD, 0xBD, 0xDD, 0xBF, 0xC3, 0x1D, 0x49, 0xED, 0x26, 0x65,
+	0x53, 0xB6, 0x41, 0x35, 0xB1, 0x52, 0x03, 0x02, 0x37, 0x0E, 0xA3, 0x8E, 0xA3, 0x3D, 0xAB, 0xD4,
+	0xBC, 0x2D, 0xF1, 0xD3, 0xE2, 0x54, 0xC7, 0xE0, 0x26, 0xA7, 0x3F, 0x8E, 0x27, 0x92, 0xF3, 0xC4,
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+	0x81, 0xC6, 0x9F, 0xA6, 0xDB, 0xE8, 0xAB, 0x63, 0xA5, 0xC5, 0x79, 0xA9, 0x1B, 0xA9, 0x61, 0x93,
+	0xFB, 0x4E, 0x0D, 0x41, 0xA7, 0x91, 0xFC, 0xB4, 0x12, 0x96, 0x78, 0x02, 0x6D, 0x0A, 0x8A, 0x14,
+	0xFA, 0x83, 0xBB, 0xCA, 0xE8, 0xA1, 0x65, 0x39, 0x7C, 0x65, 0x7E, 0x4E, 0xA9, 0xEF, 0x2D, 0xD5,
+	0xEC, 0xF7, 0xF3, 0x7F, 0x7B, 0x44, 0xCB, 0x8B, 0xB8, 0x86, 0x70, 0xE5, 0x75, 0xBA, 0x35, 0xA4,
+	0x20, 0x9D, 0x9A, 0x49, 0xA4, 0xD4, 0x53, 0x49, 0xF2, 0xAD, 0x13, 0xDD, 0x27, 0xBA, 0x4C, 0xF6,
+	0x4F, 0x10, 0xFE, 0xD6, 0x49, 0xE2, 0x0D, 0x76, 0x4B, 0xEB, 0x8F, 0x05, 0x5F, 0x36, 0x9B, 0xA8,
+	0xDB, 0xDF, 0xC3, 0xAE, 0x68, 0xF7, 0x1E, 0x22, 0x32, 0x47, 0x20, 0xBB, 0x11, 0xEF, 0x36, 0xCC,
+	0x21, 0x53, 0x6E, 0x41, 0x8D, 0x48, 0x2D, 0xE6, 0x93, 0x80, 0x18, 0xB0, 0x18, 0x3C, 0x1F, 0xC5,
+	0x9F, 0x88, 0x1A, 0x7F, 0xC4, 0x5F, 0x10, 0xD9, 0xEA, 0x5A, 0x3F, 0x87, 0xA5, 0xD2, 0xEC, 0xF4,
+	0xFD, 0x16, 0xCF, 0x4D, 0xB3, 0xB5, 0x9E, 0xF8, 0x5C, 0xC8, 0x23, 0xB7, 0x88, 0x46, 0xAC, 0xD2,
+	0x08, 0xE3, 0x0C, 0xC4, 0x0C, 0x9C, 0x28, 0x15, 0xCB, 0xD1, 0x5A, 0xE1, 0xF2, 0xFC, 0x1E, 0x16,
+	0x4A, 0x54, 0xA3, 0x66, 0x95, 0xB7, 0x7D, 0x7C, 0x9B, 0xB5, 0xFC, 0xF7, 0xE9, 0xB1, 0xCD, 0x98,
+	0x71, 0x16, 0x71, 0x9A, 0x52, 0x95, 0x3C, 0x55, 0x4E, 0x65, 0x26, 0xA4, 0xFD, 0xD8, 0xA7, 0x74,
+	0xAC, 0xB5, 0x51, 0x4D, 0x2F, 0xEE, 0xA6, 0x95, 0xF5, 0xB5, 0xDD, 0xC2, 0xBE, 0xD8, 0xFF, 0x00,
+	0x82, 0x3C, 0x7F, 0xCD, 0x44, 0xFF, 0x00, 0xB8, 0x47, 0xFE, 0xDE, 0xD7, 0xC4, 0xF5, 0xF7, 0x37,
+	0xFC, 0x11, 0xFF, 0x00, 0xC3, 0xBA, 0xCD, 0xB7, 0x87, 0x3C, 0x75, 0xE2, 0xD9, 0xEC, 0xF6, 0xE9,
+	0xF7, 0xD7, 0xD6, 0x16, 0x76, 0xB7, 0x1E, 0x62, 0xFC, 0xF3, 0x40, 0x93, 0xBC, 0xAB, 0xB7, 0x3B,
+	0x86, 0xD5, 0xB8, 0x84, 0xE4, 0x80, 0x0E, 0xFE, 0x09, 0xC1, 0xC7, 0x87, 0xC6, 0x92, 0x8C, 0x78,
+	0x6E, 0xBA, 0x6F, 0x7E, 0x5B, 0x7F, 0xE0, 0x71, 0x67, 0xDD, 0xF8, 0x27, 0x4E, 0xA4, 0xFC, 0x4C,
+	0xC0, 0xB8, 0xA6, 0xD2, 0x55, 0x5B, 0xF2, 0x5E, 0xC6, 0xA2, 0xBB, 0xEC, 0xAE, 0xD2, 0xF5, 0x69,
+	0x75, 0x3E, 0xCA, 0xA2, 0x8A, 0x2B, 0xF0, 0x83, 0xFB, 0xD8, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x2B, 0xF9,
+	0x93, 0xFF, 0x00, 0x83, 0x86, 0x3F, 0x69, 0x9F, 0x14, 0x7C, 0x7E, 0xFF, 0x00, 0x82, 0x96, 0x78,
+	0xD3, 0xC2, 0x17, 0x9A, 0x8C, 0x8D, 0xA1, 0x7C, 0x3D, 0xB8, 0x4D, 0x03, 0x41, 0xB2, 0x69, 0x37,
+	0x2C, 0x2C, 0x91, 0x45, 0xF6, 0xA7, 0x1C, 0x0C, 0x17, 0x9C, 0x3E, 0x47, 0x6D, 0xA3, 0xBE, 0x49,
+	0xFE, 0x9B, 0x2B, 0xF9, 0x35, 0xFF, 0x00, 0x82, 0xB4, 0xE8, 0xBA, 0x86, 0x83, 0xFF, 0x00, 0x05,
+	0x34, 0xF8, 0xEB, 0x63, 0xA9, 0xC3, 0xE5, 0xC9, 0x27, 0xC4, 0xED, 0x5A, 0xE5, 0x57, 0xD6, 0x39,
+	0xAE, 0x1A, 0x68, 0xCF, 0xE2, 0x8E, 0xA7, 0xF1, 0xAF, 0xD3, 0xBC, 0x2E, 0xA1, 0x46, 0xA6, 0x6D,
+	0x5A, 0xAC, 0xAD, 0xCD, 0x18, 0x69, 0xF3, 0x7A, 0xB5, 0xF7, 0x5B, 0xD1, 0xDB, 0xA9, 0xC5, 0x8E,
+	0x6F, 0xD9, 0xA4, 0x7C, 0xF3, 0x5A, 0x7E, 0x11, 0xF0, 0x57, 0x8C, 0xBC, 0x7F, 0xAD, 0x47, 0xE1,
+	0xBF, 0x01, 0xF8, 0x4B, 0x53, 0xD6, 0xF5, 0x19, 0xBF, 0xD5, 0x69, 0xFA, 0x45, 0x84, 0x97, 0x33,
+	0x3F, 0x20, 0x70, 0x91, 0xA9, 0x63, 0xC9, 0x03, 0xA7, 0x52, 0x2B, 0xEB, 0xEF, 0xF8, 0x23, 0x67,
+	0xFC, 0x12, 0x37, 0xC5, 0x9F, 0xF0, 0x53, 0x9F, 0x8B, 0x17, 0x9A, 0x8F, 0x89, 0xB5, 0x8B, 0x8D,
+	0x0B, 0xE1, 0x9F, 0x84, 0xEE, 0x22, 0xFF, 0x00, 0x84, 0xBB, 0x5A, 0xB5, 0x65, 0xFB, 0x55, 0xCC,
+	0x8E, 0x0B, 0x25, 0x8D, 0xA8, 0x60, 0x47, 0x9A, 0xE0, 0x12, 0xD2, 0x10, 0x56, 0x25, 0xF9, 0x88,
+	0x62, 0xC8, 0x8D, 0xFD, 0x18, 0x7E, 0xCB, 0x9F, 0xB1, 0xA7, 0xEC, 0xD1, 0xFB, 0x19, 0x78, 0x12,
+	0x1F, 0x87, 0x9F, 0xB3, 0x87, 0xC2, 0x6D, 0x37, 0xC3, 0x96, 0x31, 0xC7, 0xB6, 0x6B, 0x88, 0x50,
+	0xC9, 0x77, 0x76, 0x78, 0xCB, 0x4D, 0x71, 0x21, 0x69, 0x25, 0x24, 0x8C, 0xFC, 0xCC, 0x40, 0x3D,
+	0x00, 0xAF, 0xBC, 0xE2, 0x5E, 0x38, 0xCB, 0xF8, 0x7E, 0xA3, 0xC3, 0xC6, 0x2E, 0xA5, 0x6B, 0x6A,
+	0x93, 0xB2, 0x8D, 0xF6, 0xE6, 0x7D, 0xDA, 0xD5, 0x24, 0x9B, 0xB6, 0xF6, 0xBA, 0xBF, 0x2D, 0x1C,
+	0x2D, 0x4A, 0xAA, 0xFB, 0x23, 0xF9, 0xC7, 0xF8, 0x3D, 0xFF, 0x00, 0x04, 0x07, 0xFF, 0x00, 0x82,
+	0xAA, 0xFC, 0x64, 0xB6, 0x6D, 0x42, 0xCB, 0xF6, 0x62, 0xBA, 0xF0, 0xED, 0xB0, 0x8D, 0x5D, 0x66,
+	0xF1, 0x86, 0xA9, 0x6F, 0xA6, 0xB3, 0x6E, 0x04, 0x80, 0x22, 0x95, 0xFC, 0xDC, 0xF1, 0xCE, 0x50,
+	0x63, 0x23, 0x38, 0xAF, 0x70, 0xF0, 0x5F, 0xFC, 0x1A, 0x9D, 0xFF, 0x00, 0x05, 0x07, 0xD7, 0xE1,
+	0x32, 0x78, 0xAF, 0xE2, 0x57, 0xC3, 0x4D, 0x05, 0x95, 0xD7, 0xF7, 0x73, 0x6B, 0x17, 0x77, 0x04,
+	0xA9, 0xEA, 0x47, 0x95, 0x6C, 0x46, 0xE1, 0xDC, 0x1C, 0x0E, 0x98, 0x27, 0x9C, 0x7E, 0x89, 0x7F,
+	0xC1, 0x76, 0xBF, 0xE0, 0xB0, 0xFF, 0x00, 0x19, 0xBF, 0xE0, 0x93, 0x70, 0x7C, 0x2D, 0x7F, 0x84,
+	0xFF, 0x00, 0x04, 0xFC, 0x31, 0xE2, 0xF3, 0xF1, 0x0A, 0xF3, 0x55, 0xB7, 0xB8, 0x6F, 0x11, 0x6A,
+	0xD7, 0x16, 0xFF, 0x00, 0x65, 0x6B, 0x48, 0xA0, 0x90, 0x6D, 0x10, 0xA1, 0xC8, 0x61, 0x29, 0xE4,
+	0x9E, 0xA0, 0x0C, 0x77, 0xAF, 0x94, 0x3F, 0x65, 0xBF, 0xF8, 0x38, 0x9F, 0xFE, 0x0A, 0xF5, 0xFB,
+	0x6B, 0x6B, 0x5A, 0xB7, 0x87, 0x7F, 0x65, 0xDF, 0xF8, 0x26, 0x87, 0xC3, 0xBF, 0x17, 0xDE, 0xE8,
+	0x76, 0xB1, 0xDC, 0xEA, 0xD6, 0xF6, 0x3E, 0x32, 0xBA, 0x88, 0xDB, 0xC4, 0xEC, 0x55, 0x18, 0xF9,
+	0xC1, 0x01, 0x05, 0x81, 0x1C, 0x66, 0xBF, 0x3F, 0xA9, 0xE2, 0x37, 0x12, 0xE2, 0x22, 0xEA, 0x52,
+	0xA7, 0x08, 0xC5, 0x69, 0xB3, 0xFC, 0x5B, 0x96, 0xFF, 0x00, 0x25, 0xE8, 0x75, 0xFD, 0x4E, 0x8A,
+	0xD1, 0xB6, 0x71, 0x72, 0x7F, 0xC1, 0xA8, 0x9F, 0xB6, 0xE4, 0xBA, 0x42, 0x78, 0x7E, 0x5F, 0xDA,
+	0xCB, 0xE1, 0xFB, 0x58, 0x47, 0x37, 0x9B, 0x1D, 0x8B, 0x4B, 0xA9, 0x18, 0x56, 0x4C, 0x11, 0xBC,
+	0x27, 0x91, 0xB4, 0x36, 0x09, 0xE7, 0x19, 0xE4, 0xD5, 0x5F, 0xF8, 0x84, 0x9F, 0xF6, 0xC2, 0xFF,
+	0x00, 0xA3, 0x9A, 0xF8, 0x6B, 0xFF, 0x00, 0x7C, 0x6A, 0x1F, 0xFC, 0x8F, 0x5F, 0x53, 0x7F, 0xC3,
+	0xC6, 0x7F, 0xE0, 0xE4, 0x8F, 0xFA, 0x42, 0xCF, 0x83, 0x7F, 0xF0, 0xBE, 0x3F, 0xFC, 0x72, 0xBC,
+	0x8F, 0xF6, 0x84, 0xFF, 0x00, 0x83, 0x8A, 0xBF, 0xE0, 0xAE, 0x3F, 0xB1, 0x56, 0xAD, 0xA3, 0xD8,
+	0x7E, 0xD9, 0x9F, 0xF0, 0x49, 0x5F, 0x0E, 0xF8, 0x2E, 0xDB, 0x5D, 0xBA, 0x96, 0x3D, 0x23, 0x51,
+	0xBA, 0xF1, 0xBC, 0xBE, 0x45, 0xFF, 0x00, 0x94, 0x11, 0xA4, 0x8E, 0x16, 0x89, 0x66, 0x0D, 0x20,
+	0x46, 0xDD, 0x82, 0x41, 0xC7, 0x50, 0x30, 0x6B, 0x9E, 0x3E, 0x20, 0xF1, 0x55, 0x49, 0x28, 0xC6,
+	0x50, 0x6D, 0xFF, 0x00, 0x75, 0x3F, 0xD4, 0x7F, 0x55, 0xA1, 0xE6, 0x79, 0xAF, 0xFC, 0x42, 0x4F,
+	0xFB, 0x61, 0x7F, 0xD1, 0xCD, 0x7C, 0x35, 0xFF, 0x00, 0xBE, 0x35, 0x0F, 0xFE, 0x47, 0xA3, 0xFE,
+	0x21, 0x27, 0xFD, 0xB0, 0xBF, 0xE8, 0xE6, 0xBE, 0x1A, 0xFF, 0x00, 0xDF, 0x1A, 0x87, 0xFF, 0x00,
+	0x23, 0xD7, 0xE8, 0x77, 0xFC, 0x11, 0xDF, 0xFE, 0x0B, 0x83, 0xF0, 0xB3, 0xFE, 0x0A, 0xC2, 0x7C,
+	0x49, 0xE0, 0x51, 0xF0, 0x87, 0x56, 0xF0, 0x07, 0x8F, 0x7C, 0x25, 0x61, 0x6F, 0x7F, 0xAA, 0x78,
+	0x76, 0xFA, 0xFE, 0x3B, 0xEB, 0x7B, 0xAB, 0x19, 0x5C, 0xC6, 0x2E, 0x6D, 0xEE, 0x63, 0x00, 0x10,
+	0x25, 0x52, 0xAD, 0x1B, 0xAA, 0xB2, 0xEE, 0x42, 0x0B, 0x82, 0x4A, 0x9F, 0xB4, 0xE7, 0xED, 0x19,
+	0xFF, 0x00, 0x05, 0xE5, 0xF0, 0x0F, 0xC7, 0x3F, 0x10, 0xF8, 0x5B, 0xF6, 0x68, 0xFF, 0x00, 0x82,
+	0x77, 0xFC, 0x29, 0xF1, 0xDF, 0x81, 0x2D, 0xEF, 0x01, 0xF0, 0xCF, 0x8A, 0x2F, 0x3E, 0x26, 0x2D,
+	0x8D, 0xC5, 0xDD, 0xBB, 0x28, 0x60, 0x26, 0x82, 0x57, 0x46, 0x8E, 0x55, 0x24, 0xA3, 0x60, 0x6D,
+	0x25, 0x72, 0xA4, 0x82, 0x2B, 0x39, 0x78, 0x8B, 0xC5, 0x14, 0xDD, 0xA6, 0xE2, 0x9F, 0x9C, 0x50,
+	0xD6, 0x0E, 0x8B, 0x3F, 0x3C, 0x7F, 0xE2, 0x12, 0x7F, 0xDB, 0x0B, 0xFE, 0x8E, 0x6B, 0xE1, 0xAF,
+	0xFD, 0xF1, 0xA8, 0x7F, 0xF2, 0x3D, 0x1F, 0xF1, 0x09, 0x3F, 0xED, 0x85, 0xFF, 0x00, 0x47, 0x35,
+	0xF0, 0xD7, 0xFE, 0xF8, 0xD4, 0x3F, 0xF9, 0x1E, 0xBE, 0xD2, 0xFF, 0x00, 0x86, 0xBE, 0xFF, 0x00,
+	0x83, 0x96, 0x3F, 0xE9, 0x12, 0x1F, 0x08, 0x7F, 0xF0, 0xF1, 0xDB, 0xFF, 0x00, 0xF1, 0xEA, 0xF9,
+	0x4F, 0xF6, 0x98, 0xFF, 0x00, 0x83, 0x9C, 0xBF, 0xE0, 0xA4, 0xFF, 0x00, 0xB2, 0x2F, 0xC6, 0x4B,
+	0xCF, 0x80, 0x3F, 0x1C, 0x3F, 0x62, 0x4F, 0x83, 0x36, 0x7E, 0x2C, 0xD3, 0x6D, 0x52, 0x7D, 0x53,
+	0x4B, 0xD2, 0xBE, 0x23, 0xCF, 0xA9, 0x7D, 0x87, 0x71, 0x20, 0x47, 0x3C, 0x96, 0x9E, 0x62, 0x45,
+	0x2F, 0x19, 0xF2, 0x9D, 0x83, 0xE3, 0x9D, 0xB8, 0xA2, 0x97, 0x88, 0x9C, 0x51, 0x5A, 0x5C, 0xB0,
+	0x94, 0x5B, 0xFF, 0x00, 0x0A, 0xFF, 0x00, 0x30, 0x78, 0x3A, 0x31, 0xDE, 0xE7, 0x33, 0xFF, 0x00,
+	0x10, 0x93, 0xFE, 0xD8, 0x5F, 0xF4, 0x73, 0x5F, 0x0D, 0x7F, 0xEF, 0x8D, 0x43, 0xFF, 0x00, 0x91,
+	0xE8, 0xFF, 0x00, 0x88, 0x49, 0xFF, 0x00, 0x6C, 0x2F, 0xFA, 0x39, 0xAF, 0x86, 0xBF, 0xF7, 0xC6,
+	0xA1, 0xFF, 0x00, 0xC8, 0xF5, 0xD4, 0x7E, 0xCA, 0xBF, 0xF0, 0x73, 0x57, 0xFC, 0x14, 0xE3, 0xF6,
+	0xCF, 0xF8, 0xF5, 0xA4, 0x7E, 0xCE, 0x9F, 0xB3, 0xE7, 0xFC, 0x13, 0xF3, 0xE1, 0xCE, 0xBF, 0xE2,
+	0x0D, 0x4A, 0xE1, 0x45, 0xE0, 0xB3, 0xF1, 0x1E, 0xA2, 0xD0, 0xE9, 0x56, 0xFC, 0x6E, 0xBA, 0xBB,
+	0x93, 0xCB, 0x0B, 0x04, 0x2A, 0x08, 0x3B, 0x98, 0x82, 0x73, 0x85, 0x06, 0xBF, 0x71, 0x34, 0xFF,
+	0x00, 0xED, 0x0F, 0xB0, 0x41, 0xFD, 0xAB, 0xE4, 0xFD, 0xAB, 0xC9, 0x5F, 0xB4, 0xFD, 0x9F, 0x3E,
+	0x5F, 0x99, 0x8F, 0x9B, 0x6E, 0x79, 0xDB, 0x9C, 0xE3, 0x3C, 0xE2, 0xAA, 0xA7, 0x88, 0x5C, 0x53,
+	0x4A, 0x56, 0x9B, 0x8A, 0x7F, 0xE1, 0x5F, 0xE6, 0x2F, 0xAA, 0xD0, 0xF3, 0x3F, 0x04, 0xFF, 0x00,
+	0xE2, 0x12, 0x7F, 0xDB, 0x0B, 0xFE, 0x8E, 0x6B, 0xE1, 0xAF, 0xFD, 0xF1, 0xA8, 0x7F, 0xF2, 0x3D,
+	0x1F, 0xF1, 0x09, 0x3F, 0xED, 0x85, 0xFF, 0x00, 0x47, 0x35, 0xF0, 0xD7, 0xFE, 0xF8, 0xD4, 0x3F,
+	0xF9, 0x1E, 0xBF, 0x7C, 0xA8, 0xAC, 0xFF, 0x00, 0xE2, 0x23, 0xF1, 0x37, 0xF3, 0x47, 0xFF, 0x00,
+	0x01, 0x43, 0xFA, 0x9D, 0x13, 0xF0, 0x37, 0xFE, 0x21, 0x27, 0xFD, 0xB0, 0xBF, 0xE8, 0xE6, 0xBE,
+	0x1A, 0xFF, 0x00, 0xDF, 0x1A, 0x87, 0xFF, 0x00, 0x23, 0xD5, 0x8D, 0x27, 0xFE, 0x0D, 0x3D, 0xFD,
+	0xB4, 0xF4, 0x2D, 0x56, 0xD7, 0x5C, 0xD1, 0xFF, 0x00, 0x6A, 0x6F, 0x87, 0x36, 0xF7, 0x96, 0x77,
+	0x09, 0x3D, 0xAD, 0xC4, 0x4B, 0xA8, 0x06, 0x8A, 0x44, 0x60, 0xCA, 0xC0, 0xFD, 0x9F, 0xA8, 0x20,
+	0x1A, 0xFD, 0xEA, 0xA2, 0x8F, 0xF8, 0x88, 0xFC, 0x4D, 0xFC, 0xD1, 0xFF, 0x00, 0xC0, 0x50, 0x7D,
+	0x4E, 0x89, 0x9F, 0xE1, 0x58, 0x7C, 0x45, 0x6D, 0xE1, 0x7D, 0x36, 0xDF, 0xC5, 0xD7, 0x56, 0xF3,
+	0xEA, 0xD1, 0xE9, 0xF0, 0xAE, 0xA9, 0x3D, 0xAE, 0x7C, 0xA9, 0x2E, 0x02, 0x0F, 0x31, 0x93, 0x20,
+	0x7C, 0xA5, 0xF2, 0x47, 0x03, 0x8E, 0xC2, 0xBF, 0x0F, 0xBF, 0x6C, 0x4F, 0xF8, 0x35, 0x23, 0xF6,
+	0x97, 0xF8, 0xB5, 0xFB, 0x55, 0x7C, 0x40, 0xF8, 0xB1, 0xFB, 0x39, 0x7C, 0x7E, 0xF8, 0x63, 0xE1,
+	0xBF, 0x05, 0xF8, 0xA7, 0xC5, 0x17, 0x3A, 0xBE, 0x87, 0xE1, 0xFD, 0x6B, 0x4F, 0xBF, 0x33, 0xE9,
+	0xC2, 0xE0, 0xF9, 0xB2, 0xC4, 0x4C, 0x29, 0xB3, 0x6F, 0x9C, 0xD2, 0xB2, 0xE0, 0x9C, 0x2B, 0x01,
+	0x9E, 0x30, 0x3F, 0x74, 0x68, 0xAF, 0x87, 0x8D, 0x5A, 0xD4, 0xE5, 0xCD, 0x4E, 0x4E, 0x2F, 0xCA,
+	0xC7, 0x4F, 0x2C, 0x7A, 0x9F, 0xCF, 0x2F, 0xFC, 0x42, 0x11, 0xFF, 0x00, 0x05, 0x04, 0xFF, 0x00,
+	0xA3, 0xB3, 0xF8, 0x37, 0xFF, 0x00, 0x82, 0xDD, 0x5B, 0xFF, 0x00, 0x88, 0xAF, 0xDA, 0x0F, 0xF8,
+	0x26, 0x9F, 0xC0, 0xBF, 0xDA, 0x7B, 0xF6, 0x65, 0xFD, 0x8F, 0x3C, 0x29, 0xF0, 0x07, 0xF6, 0xB4,
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+	0xA9, 0x69, 0x90, 0x24, 0xBE, 0x65, 0x9D, 0xAC, 0x52, 0x1C, 0x47, 0x71, 0x32, 0xED, 0x2C, 0x54,
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+	0xF2, 0xBF, 0x85, 0xFE, 0x29, 0x96, 0xC3, 0xC7, 0x51, 0xF8, 0x6A, 0x56, 0x76, 0x5D, 0x42, 0x17,
+	0xDA, 0xBD, 0x83, 0x22, 0xEE, 0x0D, 0xFF, 0x00, 0x7C, 0x86, 0x1F, 0x8F, 0xB5, 0x7A, 0xA5, 0x00,
+	0x15, 0x57, 0x53, 0xD6, 0xF4, 0xDD, 0x1D, 0x55, 0xB5, 0x0B, 0x91, 0x1E, 0xEE, 0x11, 0x7A, 0xB3,
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+	0xA9, 0xE7, 0xCD, 0xB9, 0xAD, 0x6F, 0xA4, 0xB7, 0x5D, 0xA0, 0x80, 0xAA, 0x8E, 0x54, 0x01, 0xC9,
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+	0x7F, 0xDF, 0x54, 0x01, 0xEA, 0x1F, 0xF0, 0xB0, 0x74, 0x2F, 0xF9, 0xE7, 0x71, 0xFF, 0x00, 0x7C,
+	0xAF, 0xFF, 0x00, 0x15, 0x49, 0xFF, 0x00, 0x0B, 0x0B, 0x42, 0x07, 0x98, 0xEE, 0x3E, 0xBB, 0x17,
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+	0x56, 0x1F, 0x81, 0xFF, 0x00, 0xF5, 0x55, 0xCA, 0xF1, 0x15, 0xF1, 0x54, 0xDE, 0x11, 0xD4, 0x2D,
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+	0xCE, 0xED, 0x80, 0x2A, 0x4A, 0xF3, 0x3F, 0x8C, 0xBE, 0x23, 0xB9, 0x8B, 0xC5, 0x76, 0xBE, 0x1C,
+	0x32, 0x1F, 0x25, 0x6C, 0x56, 0xE1, 0x51, 0x47, 0x56, 0x67, 0x75, 0xC9, 0xE7, 0x9E, 0x17, 0x8F,
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+	0xCA, 0xFF, 0x00, 0xF1, 0x55, 0xE4, 0xFF, 0x00, 0xDA, 0x52, 0x7F, 0x7D, 0xFF, 0x00, 0xEF, 0x9F,
+	0xFE, 0xBD, 0x7C, 0xB3, 0xFB, 0x59, 0x7F, 0xC1, 0x66, 0x7F, 0x62, 0xFF, 0x00, 0xD9, 0x13, 0xC5,
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+	0x49, 0x1B, 0xA1, 0x8B, 0x71, 0x91, 0x08, 0xF9, 0xD5, 0x43, 0x29, 0x20, 0x1F, 0x7F, 0x7F, 0xC2,
+	0xC1, 0xD0, 0xBF, 0xE7, 0x9D, 0xC7, 0xFD, 0xF2, 0xBF, 0xFC, 0x55, 0x21, 0xF8, 0x83, 0xA1, 0x81,
+	0x9F, 0x2A, 0xE3, 0xFE, 0xF9, 0x5F, 0xFE, 0x2A, 0xBF, 0x1A, 0xFC, 0x3B, 0xFF, 0x00, 0x07, 0x36,
+	0xF8, 0x1E, 0x5F, 0x13, 0x43, 0x0F, 0x8D, 0xBF, 0x64, 0x6F, 0x10, 0xE9, 0xDE, 0x1F, 0x92, 0x42,
+	0x24, 0xD5, 0x34, 0xEF, 0x14, 0xC5, 0x75, 0x74, 0x17, 0x19, 0x05, 0x6D, 0xE4, 0x82, 0x14, 0x62,
+	0x79, 0xE3, 0xCE, 0x18, 0x1C, 0xE4, 0xF4, 0xAF, 0xB1, 0x7F, 0x63, 0x9F, 0xF8, 0x29, 0x7F, 0xEC,
+	0xC3, 0xFB, 0x71, 0x59, 0xCD, 0x17, 0xC1, 0x9F, 0x19, 0x4D, 0x6F, 0xAD, 0x5A, 0xAB, 0x3D, 0xD7,
+	0x85, 0x7C, 0x40, 0x89, 0x6D, 0xA9, 0x47, 0x10, 0x66, 0x1E, 0x68, 0x8D, 0x5D, 0xD6, 0x54, 0xC2,
+	0xE4, 0xB4, 0x6E, 0xE1, 0x43, 0x2E, 0xFD, 0xA5, 0x80, 0xA0, 0x0F, 0xB6, 0x34, 0xDF, 0x17, 0xE8,
+	0x3A, 0xA4, 0xCB, 0x6D, 0x6F, 0x77, 0xB6, 0x56, 0xFB, 0xB1, 0xC8, 0xBB, 0x49, 0xF6, 0xCF, 0x43,
+	0xF8, 0x1A, 0xD4, 0xAF, 0x07, 0x97, 0x54, 0xB8, 0x58, 0xCB, 0x92, 0xC3, 0x68, 0xCF, 0x07, 0xA5,
+	0x7A, 0xFF, 0x00, 0xC3, 0xEF, 0x11, 0x1F, 0x15, 0xF8, 0x37, 0x4F, 0xD7, 0x9B, 0x76, 0xE9, 0xA1,
+	0x22, 0x46, 0x6C, 0x7C, 0xCC, 0xAC, 0x55, 0x8F, 0x1E, 0xA5, 0x49, 0xFC, 0x68, 0x03, 0x66, 0x86,
+	0x3B, 0x46, 0x71, 0x45, 0x72, 0x1F, 0x1A, 0x75, 0xFB, 0x9D, 0x07, 0xC2, 0xB0, 0xFD, 0x9E, 0x5D,
+	0xAB, 0x79, 0x7C, 0xB6, 0xF2, 0xE0, 0x1C, 0x95, 0x28, 0xED, 0x8E, 0xBD, 0xF6, 0xE0, 0xFA, 0x82,
+	0x45, 0x00, 0x6B, 0xDC, 0xF8, 0xE3, 0xC3, 0xD6, 0xE5, 0x84, 0x77, 0x2D, 0x36, 0xDE, 0x0F, 0x92,
+	0xB9, 0x1F, 0x81, 0xE0, 0x1F, 0xC0, 0xD4, 0x43, 0xE2, 0x16, 0x84, 0x46, 0x7C, 0xBB, 0x8F, 0xFB,
+	0xE5, 0x7F, 0xF8, 0xAA, 0xF2, 0xF5, 0x92, 0x7D, 0xBC, 0x3B, 0x52, 0xEF, 0xB8, 0x6E, 0x8E, 0xDF,
+	0x9D, 0x00, 0x7A, 0x87, 0xFC, 0x2C, 0x1D, 0x0B, 0xFE, 0x79, 0xDC, 0x7F, 0xDF, 0x2B, 0xFF, 0x00,
+	0xC5, 0x51, 0xFF, 0x00, 0x0B, 0x07, 0x42, 0xFF, 0x00, 0x9E, 0x77, 0x1F, 0xF7, 0xCA, 0xFF, 0x00,
+	0xF1, 0x55, 0xE5, 0xF9, 0xB8, 0xFE, 0xFB, 0x7F, 0xDF, 0x54, 0x6E, 0xB8, 0x03, 0x25, 0xDB, 0xF3,
+	0xA0, 0x0F, 0x52, 0xB6, 0xF1, 0xEF, 0x87, 0x67, 0x90, 0x47, 0x2C, 0xF2, 0x42, 0x58, 0xE0, 0x79,
+	0xD1, 0xF1, 0xF9, 0x8C, 0xE3, 0xF1, 0xAD, 0x94, 0x75, 0x91, 0x16, 0x44, 0x60, 0xCA, 0xC3, 0x2A,
+	0xC0, 0xF5, 0xAF, 0x13, 0x32, 0x4E, 0x47, 0x0E, 0xD5, 0xDA, 0xFC, 0x12, 0xF1, 0x43, 0xEB, 0x36,
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+	0x89, 0xE2, 0x6B, 0x79, 0x2C, 0x77, 0x6B, 0xDE, 0x2C, 0xB1, 0x9B, 0xFB, 0x53, 0xC4, 0x1A, 0x4B,
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+	0xD5, 0x7E, 0x28, 0xFE, 0xD0, 0x9F, 0x10, 0xB5, 0xEF, 0x14, 0x78, 0xB7, 0x50, 0x9F, 0x6E, 0xAB,
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+	0x58, 0xC6, 0x16, 0x35, 0x50, 0xAA, 0x14, 0x28, 0x00, 0x03, 0xFA, 0xD0, 0xFF, 0x00, 0x82, 0x5B,
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+	0xF0, 0xC7, 0x58, 0xF0, 0xFF, 0x00, 0x86, 0xFC, 0x1B, 0xE2, 0x3B, 0x6D, 0x2B, 0x4B, 0xBA, 0xF1,
+	0x15, 0xC4, 0x5F, 0x6C, 0xD5, 0x04, 0x96, 0x89, 0x33, 0xCD, 0x24, 0x11, 0x6E, 0x4B, 0x60, 0xB2,
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+	0x87, 0xFB, 0x42, 0x7D, 0x63, 0x5D, 0x22, 0xFB, 0x4B, 0x8C, 0x69, 0xBB, 0x8C, 0xF6, 0xBA, 0x73,
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+	0xFF, 0x00, 0xC2, 0x05, 0xE1, 0xDE, 0x78, 0x52, 0x7C, 0xDC, 0x13, 0xFF, 0x00, 0x7D, 0x57, 0xD2,
+	0xBF, 0x1F, 0x7F, 0x61, 0xAF, 0x87, 0xDF, 0xB4, 0x6F, 0xC5, 0x18, 0x7E, 0x23, 0xF8, 0xE3, 0xC4,
+	0xFA, 0xA4, 0x51, 0xC1, 0xA5, 0xC7, 0x64, 0xBA, 0x7D, 0x8E, 0xC4, 0x56, 0xD8, 0xEE, 0xFB, 0xB7,
+	0x10, 0x4E, 0x4E, 0xFC, 0x74, 0xED, 0x4E, 0xF0, 0xCF, 0xFC, 0x13, 0xCB, 0xF6, 0x52, 0xF0, 0xDA,
+	0x2E, 0x7E, 0x1B, 0x7F, 0x68, 0x48, 0xBF, 0xF2, 0xDB, 0x53, 0xBF, 0x9A, 0x46, 0x23, 0xDC, 0x2B,
+	0x2A, 0x9F, 0xA6, 0x08, 0xA0, 0x0C, 0x6F, 0xD8, 0x93, 0xF6, 0xBA, 0xF1, 0xEF, 0xED, 0x31, 0x63,
+	0xE2, 0xCB, 0x9F, 0x17, 0xE8, 0x5A, 0x6D, 0x83, 0x68, 0x3F, 0x67, 0xFB, 0x3A, 0xD9, 0xAB, 0x61,
+	0xFC, 0xC5, 0x90, 0x92, 0xDB, 0x8F, 0x62, 0x82, 0xBC, 0x02, 0xDF, 0xFE, 0x0A, 0xD3, 0xF1, 0xD2,
+	0x58, 0x15, 0xCF, 0xC3, 0xEF, 0x0E, 0xE4, 0xA8, 0x3F, 0x37, 0x9B, 0xCE, 0x47, 0xFB, 0xDF, 0x51,
+	0xF8, 0x57, 0xDC, 0xBE, 0x04, 0xF8, 0x53, 0xF0, 0xE3, 0xE1, 0x9D, 0xAC, 0xF6, 0x3E, 0x00, 0xF0,
+	0x46, 0x99, 0xA3, 0xC7, 0x75, 0x8F, 0xB4, 0x2E, 0x9F, 0x66, 0x91, 0xF9, 0xB8, 0x1C, 0x6E, 0xC0,
+	0xF9, 0x88, 0xC9, 0xEB, 0x9A, 0xB1, 0x6B, 0xF0, 0xE3, 0xE1, 0xF5, 0x9C, 0x7E, 0x4D, 0xB7, 0x80,
+	0xF4, 0x58, 0xD4, 0x74, 0x54, 0xD3, 0x62, 0xC0, 0xFF, 0x00, 0xC7, 0x68, 0x03, 0xE1, 0x53, 0xFF,
+	0x00, 0x05, 0x66, 0xF8, 0xE6, 0x47, 0x1E, 0x00, 0xF0, 0xF7, 0xFE, 0x45, 0xE3, 0x27, 0x19, 0xEA,
+	0x7D, 0x6B, 0xDD, 0xBF, 0x68, 0xAF, 0xDB, 0x17, 0xC7, 0x7F, 0x08, 0x3F, 0x67, 0x7F, 0x01, 0x7C,
+	0x5E, 0xD0, 0x3C, 0x3F, 0xA6, 0xDC, 0x5F, 0x78, 0xAA, 0xCE, 0xD6, 0x6B, 0xCB, 0x7B, 0xAD, 0xFE,
+	0x5C, 0x5E, 0x6D, 0xAA, 0xCC, 0x76, 0xE0, 0x83, 0xC1, 0x6C, 0x73, 0xDA, 0xBD, 0xDA, 0x6F, 0x87,
+	0xBE, 0x02, 0x9D, 0x36, 0x4D, 0xE0, 0x5D, 0x19, 0xC7, 0x5D, 0xAD, 0xA6, 0x44, 0x47, 0xFE, 0x83,
+	0x55, 0xFC, 0x4D, 0xF0, 0xC7, 0xE1, 0xEF, 0x8D, 0x74, 0x58, 0x7C, 0x3B, 0xE2, 0xCF, 0x04, 0xE9,
+	0x3A, 0x85, 0x8D, 0xBE, 0x05, 0xB5, 0xAD, 0xED, 0x8C, 0x72, 0x24, 0x20, 0x2E, 0xD1, 0xB0, 0x63,
+	0xE5, 0xC0, 0xE0, 0x63, 0xB5, 0x00, 0x7C, 0x34, 0x7F, 0xE0, 0xAD, 0x9F, 0x1C, 0x03, 0x63, 0xFE,
+	0x10, 0x2F, 0x0E, 0xFF, 0x00, 0xE4, 0x5F, 0xFE, 0x2A, 0xBD, 0x1F, 0xF6, 0x50, 0xFF, 0x00, 0x82,
+	0x83, 0x7C, 0x50, 0xF8, 0xF5, 0xF1, 0xB7, 0x4D, 0xF8, 0x69, 0xE2, 0x5F, 0x0A, 0xE8, 0xF6, 0xB6,
+	0x97, 0x76, 0xD3, 0xCB, 0x24, 0xD6, 0x7E, 0x67, 0x99, 0xF2, 0x21, 0x20, 0x0C, 0x93, 0x5E, 0xB7,
+	0xE2, 0x5F, 0xD8, 0x23, 0xF6, 0x52, 0xF1, 0x2A, 0xB0, 0x93, 0xE1, 0x3D, 0xBD, 0x9B, 0xC9, 0xC1,
+	0x9B, 0x4F, 0xBB, 0x9A, 0x12, 0x3E, 0x80, 0x3E, 0xDF, 0xD0, 0xFD, 0x2B, 0x27, 0xE1, 0x27, 0xEC,
+	0x01, 0xF0, 0xA3, 0xE0, 0x87, 0xC5, 0x5B, 0x3F, 0x8A, 0x7F, 0x0F, 0xF5, 0xED, 0x62, 0x39, 0x2D,
+	0x21, 0x9A, 0x2F, 0xEC, 0xFB, 0xC9, 0x12, 0x58, 0xDC, 0x48, 0xA5, 0x4F, 0xCC, 0x02, 0x91, 0x40,
+	0x1E, 0x49, 0xFB, 0x42, 0xFF, 0x00, 0xC1, 0x49, 0x7E, 0x2D, 0x7C, 0x21, 0xF8, 0xD5, 0xE2, 0x2F,
+	0x87, 0x5A, 0x2F, 0x84, 0xF4, 0x2B, 0x8B, 0x3D, 0x27, 0x50, 0x30, 0x5B, 0xCD, 0x74, 0x64, 0xF3,
+	0x19, 0x76, 0xA9, 0xC9, 0xC1, 0x03, 0xA9, 0xAE, 0x37, 0xFE, 0x1E, 0xD9, 0xF1, 0xCC, 0xF4, 0xF0,
+	0x0F, 0x87, 0x7F, 0xF2, 0x2F, 0xFF, 0x00, 0x15, 0x5A, 0xDF, 0xB5, 0xDF, 0xEC, 0x0D, 0xF1, 0xFB,
+	0xC6, 0xBF, 0x17, 0xBC, 0x45, 0xF1, 0x5B, 0xC0, 0x36, 0xDA, 0x76, 0xB1, 0x65, 0xAA, 0x5E, 0x7D,
+	0xA1, 0x6C, 0x21, 0xBE, 0xF2, 0x6E, 0x53, 0xE4, 0x51, 0xB7, 0x0F, 0x84, 0x3D, 0x3B, 0x35, 0x7C,
+	0xAF, 0xE3, 0x3F, 0x00, 0x78, 0xE7, 0xE1, 0xCE, 0xB1, 0xFD, 0x87, 0xE3, 0xEF, 0x08, 0x6A, 0x5A,
+	0x3D, 0xE7, 0x51, 0x0E, 0xA5, 0x68, 0xF1, 0xB4, 0x83, 0xD5, 0x4B, 0x01, 0xB8, 0x7B, 0xAE, 0x41,
+	0xA0, 0x0F, 0xD1, 0x2F, 0x85, 0xBF, 0xB5, 0xBF, 0x8F, 0xBC, 0x6D, 0xFB, 0x1C, 0x78, 0x93, 0xF6,
+	0x8A, 0xD5, 0x34, 0x4D, 0x3E, 0x3D, 0x53, 0x45, 0x8E, 0xF9, 0xA1, 0xB4, 0x8D, 0x5B, 0xC9, 0x7F,
+	0x24, 0x02, 0x33, 0xCE, 0x7D, 0x6B, 0xE7, 0xF3, 0xFF, 0x00, 0x05, 0x6C, 0xF8, 0xE3, 0x8C, 0x7F,
+	0xC2, 0x03, 0xE1, 0xDF, 0x7F, 0xF5, 0xBC, 0x7F, 0xE3, 0xD5, 0xD5, 0x7E, 0xCF, 0xF8, 0x1F, 0xF0,
+	0x4B, 0x3F, 0x1F, 0x06, 0x38, 0xFD, 0xCE, 0xB1, 0xF7, 0xB8, 0xFE, 0x11, 0xFE, 0x22, 0xBE, 0x2B,
+	0x6F, 0xBF, 0xFD, 0x3B, 0x8F, 0xAF, 0xA5, 0x00, 0x7D, 0x65, 0xA4, 0xFF, 0x00, 0xC1, 0x57, 0xFE,
+	0x36, 0xEA, 0x3A, 0xAD, 0xB5, 0x84, 0x9E, 0x06, 0xF0, 0xFA, 0xAC, 0xD7, 0x08, 0x8C, 0xCB, 0xE6,
+	0xE4, 0x02, 0xC0, 0x71, 0xC9, 0xAF, 0x68, 0xFD, 0xB8, 0x7F, 0x6C, 0xEF, 0x88, 0x7F, 0xB3, 0x0F,
+	0x8C, 0x34, 0x5F, 0x0F, 0xF8, 0x47, 0xC3, 0x9A, 0x5D, 0xF4, 0x3A, 0x96, 0x9A, 0xD7, 0x12, 0xB5,
+	0xF6, 0xFD, 0xC8, 0xC2, 0x42, 0xB8, 0x1B, 0x48, 0xE3, 0x02, 0xBF, 0x3C, 0xFC, 0x32, 0xA7, 0xFE,
+	0x12, 0x3B, 0x1E, 0x3F, 0xE5, 0xF2, 0x2F, 0xFD, 0x0C, 0x57, 0xD5, 0xDF, 0xF0, 0x57, 0x62, 0x1B,
+	0xE2, 0x6F, 0x84, 0xF6, 0xF3, 0xFF, 0x00, 0x12, 0x19, 0x3A, 0x7F, 0xD7, 0x63, 0x40, 0x19, 0xBF,
+	0xF0, 0xF6, 0xDF, 0x8E, 0x5F, 0xF4, 0x20, 0x78, 0x7B, 0xFF, 0x00, 0x22, 0xFF, 0x00, 0xF1, 0x55,
+	0xED, 0xFF, 0x00, 0xB0, 0xDF, 0xED, 0xA3, 0xF1, 0x17, 0xF6, 0x9F, 0xF1, 0x9E, 0xBD, 0xE1, 0xCF,
+	0x17, 0xF8, 0x73, 0x4B, 0xB1, 0x8B, 0x4B, 0xD3, 0x61, 0xB8, 0x86, 0x4B, 0x1D, 0xE4, 0xB3, 0x34,
+	0x85, 0x4E, 0x77, 0x1E, 0x9C, 0x57, 0xE7, 0x36, 0x08, 0xEA, 0x2B, 0xEB, 0xAF, 0xF8, 0x24, 0x28,
+	0x23, 0xE2, 0x9F, 0x8C, 0x32, 0x3F, 0xE6, 0x03, 0x6F, 0xFF, 0x00, 0xA3, 0x9A, 0x80, 0x23, 0xD7,
+	0xBF, 0xE0, 0xAB, 0x7F, 0x1B, 0x74, 0x9D, 0x76, 0xFB, 0x4A, 0x87, 0xC0, 0xBE, 0x1F, 0x68, 0xED,
+	0x6F, 0x25, 0x85, 0x59, 0xBC, 0xDD, 0xC4, 0x2B, 0x95, 0x04, 0xE1, 0xB1, 0xDA, 0xAA, 0x0F, 0xF8,
+	0x2B, 0x67, 0xC7, 0x0E, 0xBF, 0xF0, 0x80, 0xF8, 0x77, 0x81, 0xD3, 0xF7, 0xBC, 0xFF, 0x00, 0xE3,
+	0xD5, 0xF3, 0x3F, 0x8D, 0x3F, 0xE4, 0x72, 0xD6, 0x00, 0xFF, 0x00, 0xA0, 0xA5, 0xC7, 0xFE, 0x8D,
+	0x7A, 0xCC, 0xCE, 0xDE, 0x58, 0xE3, 0xEB, 0x40, 0x1F, 0xA4, 0xDF, 0x13, 0x7F, 0x6B, 0xDF, 0x1E,
+	0x78, 0x2B, 0xF6, 0x37, 0xF0, 0xDF, 0xED, 0x13, 0xA6, 0xE8, 0x5A, 0x74, 0x9A, 0xA6, 0xB3, 0xF6,
+	0x4F, 0x3E, 0xD2, 0x65, 0x6F, 0x25, 0x7C, 0xD2, 0xD9, 0xC6, 0x0E, 0x7B, 0x7E, 0xB5, 0xE0, 0x87,
+	0xFE, 0x0A, 0xD9, 0xF1, 0xC7, 0xB7, 0x80, 0x7C, 0x3B, 0xFF, 0x00, 0x91, 0x7F, 0xF8, 0xAA, 0xE8,
+	0xFE, 0x3F, 0x02, 0x7F, 0xE0, 0x97, 0x1E, 0x03, 0xC0, 0xEF, 0xA6, 0xFF, 0x00, 0xE8, 0x4F, 0x5F,
+	0x18, 0x80, 0x7D, 0x28, 0x03, 0xED, 0xEF, 0xD9, 0xEB, 0xFE, 0x0A, 0x49, 0xF1, 0x77, 0xE2, 0xF7,
+	0xC6, 0x7F, 0x0F, 0xFC, 0x37, 0xD6, 0xFC, 0x1D, 0xA1, 0xDB, 0xDA, 0xEA, 0xD7, 0xC2, 0x19, 0xA6,
+	0xB7, 0xF3, 0x37, 0xAA, 0xE0, 0x9E, 0x32, 0x48, 0xCF, 0x15, 0xA5, 0xFB, 0x57, 0xFF, 0x00, 0xC1,
+	0x42, 0x3E, 0x2A, 0x7C, 0x03, 0xF8, 0xE7, 0xAB, 0x7C, 0x30, 0xF0, 0xDF, 0x84, 0xF4, 0x7B, 0xCB,
+	0x3B, 0x18, 0x6D, 0x9E, 0x29, 0xAF, 0x37, 0xF9, 0x84, 0xC9, 0x0A, 0x39, 0xCE, 0xD2, 0x07, 0x56,
+	0xAF, 0x98, 0xFF, 0x00, 0x62, 0x2C, 0x8F, 0xDA, 0xAF, 0xC1, 0x44, 0x8F, 0xF9, 0x8C, 0x2F, 0xFE,
+	0x82, 0xD5, 0xD0, 0xFF, 0x00, 0xC1, 0x48, 0xF9, 0xFD, 0xAF, 0xBC, 0x45, 0x81, 0xFF, 0x00, 0x2E,
+	0xB6, 0x3F, 0xFA, 0x4B, 0x15, 0x00, 0x76, 0xBF, 0xF0, 0xF6, 0xCF, 0x8E, 0x20, 0x12, 0x3C, 0x03,
+	0xE1, 0xDF, 0xBA, 0x71, 0xBB, 0xCE, 0xFF, 0x00, 0xE2, 0xAB, 0xE8, 0x0F, 0xD9, 0xA7, 0xF6, 0xB9,
+	0xF1, 0xDF, 0xC6, 0xAF, 0x80, 0x3E, 0x34, 0xF8, 0xAF, 0xAF, 0xE8, 0x3A, 0x7D, 0xAD, 0xE7, 0x86,
+	0xD6, 0xE8, 0xDA, 0xC3, 0x67, 0xBB, 0xCB, 0x7F, 0x2E, 0xD3, 0xCE, 0x1B, 0xB7, 0x1C, 0xF5, 0xF4,
+	0xAF, 0xCD, 0x52, 0x1B, 0x1F, 0x76, 0xBE, 0xD4, 0xFD, 0x80, 0x4E, 0x7F, 0x62, 0xBF, 0x8B, 0x1F,
+	0xF5, 0xC7, 0x50, 0xED, 0xFF, 0x00, 0x50, 0xDA, 0x00, 0xE5, 0x47, 0xFC, 0x15, 0xAB, 0xE3, 0x9E,
+	0xD5, 0xCF, 0x80, 0xFC, 0x3B, 0xD3, 0xE6, 0xDB, 0xE6, 0xFF, 0x00, 0x8D, 0x1F, 0xF0, 0xF6, 0xDF,
+	0x8E, 0x5D, 0x47, 0x80, 0x3C, 0x3A, 0x7F, 0xEF, 0xEF, 0xFF, 0x00, 0x15, 0x5F, 0x2A, 0xAE, 0x70,
+	0x17, 0xBE, 0x3F, 0xAD, 0x07, 0xE5, 0xFB, 0xD4, 0x01, 0xFA, 0x1B, 0xE2, 0x6F, 0xDB, 0x83, 0xE2,
+	0x3E, 0x8D, 0xFB, 0x1B, 0x68, 0x3F, 0xB4, 0x5D, 0xB7, 0x87, 0x74, 0xB6, 0xD5, 0x35, 0x4D, 0x71,
+	0xAC, 0xE5, 0xB3, 0x75, 0x7F, 0x29, 0x50, 0x4B, 0x32, 0x82, 0x39, 0xCF, 0x48, 0xC7, 0xE7, 0x5E,
+	0x38, 0x7F, 0xE0, 0xAD, 0x9F, 0x1C, 0x31, 0xFF, 0x00, 0x22, 0x0F, 0x87, 0x7B, 0x7F, 0xCF, 0x6F,
+	0x4F, 0xF7, 0xAA, 0x1F, 0x1E, 0x1C, 0xFF, 0x00, 0xC1, 0x2C, 0x7C, 0x17, 0x8F, 0xFA, 0x1B, 0x24,
+	0xFF, 0x00, 0xD1, 0xF7, 0x55, 0xF2, 0xDF, 0xCC, 0x4E, 0x07, 0xB7, 0xF2, 0x14, 0x01, 0xF5, 0xB7,
+	0x87, 0xBF, 0xE0, 0xAB, 0x3F, 0x1B, 0x75, 0x9D, 0x7A, 0xC7, 0x4A, 0x9F, 0xC0, 0xDE, 0x1F, 0x58,
+	0xEE, 0xAF, 0x23, 0x8A, 0x46, 0x5F, 0x37, 0x20, 0x33, 0x80, 0x48, 0xE4, 0xFA, 0xD7, 0xAA, 0xFE,
+	0xD9, 0x9F, 0xB7, 0x1F, 0xC4, 0x9F, 0xD9, 0xC7, 0xC7, 0x5A, 0x2F, 0x86, 0xBC, 0x2B, 0xE1, 0xBD,
+	0x2A, 0xF2, 0x1D, 0x4B, 0x43, 0x5B, 0xD9, 0x9A, 0xF5, 0x5F, 0x2A, 0xEC, 0xE4, 0x60, 0x6D, 0x3D,
+	0x30, 0x2B, 0xE0, 0x8F, 0x04, 0x10, 0x3C, 0x6B, 0xA4, 0x29, 0x3F, 0xF3, 0x13, 0xB7, 0xFF, 0x00,
+	0xD1, 0x8B, 0x5F, 0x47, 0xFF, 0x00, 0xC1, 0x54, 0xC6, 0x7E, 0x2E, 0xF8, 0x57, 0x3F, 0xF4, 0x27,
+	0xC7, 0xFF, 0x00, 0xA3, 0x9A, 0x80, 0x27, 0x3F, 0xF0, 0x56, 0xBF, 0x8E, 0x04, 0xE3, 0xFE, 0x10,
+	0x2F, 0x0E, 0xFE, 0x1E, 0x77, 0xFF, 0x00, 0x15, 0x5E, 0x9D, 0xFB, 0x22, 0xFE, 0xDF, 0xFF, 0x00,
+	0x14, 0x3F, 0x68, 0x1F, 0x8D, 0x96, 0x3F, 0x0D, 0xFC, 0x4F, 0xE1, 0x4D, 0x1E, 0xD2, 0xCE, 0xE6,
+	0xCE, 0xE2, 0x56, 0x9A, 0xCC, 0xC9, 0xE6, 0x2B, 0x24, 0x65, 0xC0, 0xE7, 0x23, 0xB5, 0x7C, 0x0E,
+	0xA0, 0xE3, 0xA7, 0xA5, 0x7D, 0x01, 0xFF, 0x00, 0x04, 0xCB, 0x60, 0x7F, 0x6B, 0x0D, 0x2C, 0x03,
+	0xC8, 0xD3, 0x6F, 0x73, 0xFF, 0x00, 0x7E, 0x4D, 0x00, 0x7E, 0x9A, 0x0E, 0x94, 0x50, 0x3A, 0x51,
+	0x40, 0x05, 0x14, 0x51, 0x40, 0x1F, 0x1B, 0xFF, 0x00, 0xC1, 0x42, 0xFF, 0x00, 0x65, 0xCF, 0x8D,
+	0xFF, 0x00, 0x1D, 0xFE, 0x2D, 0x69, 0x3E, 0x22, 0xF8, 0x61, 0xE1, 0x25, 0xD4, 0x2D, 0x6C, 0xF4,
+	0x31, 0x6F, 0x71, 0x33, 0x5E, 0x47, 0x0E, 0xD9, 0x3C, 0xE7, 0x6C, 0x7C, 0xCC, 0x09, 0xE3, 0xDA,
+	0xBC, 0x0B, 0xFE, 0x1D, 0xD3, 0xFB, 0x5D, 0x30, 0xFF, 0x00, 0x92, 0x67, 0x1F, 0xE3, 0xAA, 0xDB,
+	0xFF, 0x00, 0xF1, 0x55, 0xEE, 0x7F, 0xF0, 0x51, 0xAF, 0xDA, 0x4F, 0xE3, 0x97, 0xC1, 0x5F, 0x8B,
+	0xBA, 0x3E, 0x81, 0xF0, 0xC3, 0xE2, 0x0C, 0xFA, 0x4D, 0x9D, 0xD6, 0x86, 0xB3, 0xDC, 0x43, 0x15,
+	0x8D, 0xB4, 0xBB, 0xE4, 0xF3, 0x9D, 0x43, 0x66, 0x68, 0xDC, 0x8E, 0x3D, 0x08, 0xAF, 0x9F, 0x47,
+	0xED, 0xF7, 0xFB, 0x60, 0x63, 0x9F, 0x8D, 0xB7, 0x9F, 0xF8, 0x2B, 0xB2, 0xFF, 0x00, 0xE3, 0x14,
+	0x01, 0xED, 0x9F, 0xB0, 0xEF, 0xEC, 0x7F, 0xFB, 0x41, 0xFC, 0x1D, 0xFD, 0xA0, 0xEC, 0x7C, 0x6B,
+	0xF1, 0x07, 0xC1, 0x91, 0xD8, 0xE9, 0xB0, 0xD8, 0xDD, 0x47, 0x24, 0xCB, 0xA8, 0x47, 0x29, 0x05,
+	0xA2, 0x2A, 0xA3, 0x6A, 0xB6, 0x79, 0x27, 0xD3, 0x15, 0xC8, 0xFE, 0xD0, 0x1F, 0xB0, 0xCF, 0xED,
+	0x37, 0xE3, 0xEF, 0x8E, 0x5E, 0x2E, 0xF1, 0xAF, 0x85, 0x7C, 0x02, 0x97, 0x1A, 0x6E, 0xA9, 0xE2,
+	0x1B, 0xAB, 0x8B, 0x39, 0xBF, 0xB4, 0xA2, 0x43, 0x24, 0x6D, 0x21, 0x20, 0xE0, 0xB7, 0xF3, 0xAE,
+	0x93, 0xF6, 0x11, 0xFD, 0xAB, 0xBF, 0x68, 0x6F, 0x8B, 0x5F, 0xB4, 0x3E, 0x9F, 0xE0, 0xCF, 0x88,
+	0x9F, 0x13, 0xAE, 0x35, 0x3D, 0x2E, 0x6B, 0x3B, 0xA9, 0x24, 0xB3, 0x93, 0x4F, 0xB6, 0x8C, 0x16,
+	0x48, 0xB7, 0x29, 0xDD, 0x1C, 0x6A, 0x78, 0x6C, 0x9A, 0xE3, 0xFF, 0x00, 0x68, 0x8F, 0xDB, 0x43,
+	0xF6, 0xA0, 0xF0, 0x3F, 0xC7, 0xAF, 0x18, 0x78, 0x4B, 0xC2, 0xBF, 0x16, 0xAE, 0x6C, 0xF4, 0xDD,
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+	0xF2, 0x45, 0xA5, 0xC0, 0xB7, 0x91, 0xC9, 0xE6, 0xB1, 0xB4, 0x99, 0x31, 0xB8, 0x36, 0x07, 0xCC,
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+	0x3F, 0xC5, 0x1F, 0x80, 0x5F, 0x13, 0xBC, 0x59, 0xE3, 0xFF, 0x00, 0x1D, 0xCD, 0xAA, 0x6A, 0x3A,
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+	0x59, 0x22, 0x0A, 0xC3, 0x0C, 0xDD, 0x88, 0xF4, 0xAF, 0x30, 0xFD, 0x95, 0x7F, 0x6D, 0xCF, 0xDA,
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+	0xE1, 0x0E, 0x7A, 0x23, 0x73, 0xED, 0x5E, 0x73, 0xF1, 0xDB, 0xF6, 0x14, 0xFD, 0xA7, 0xFC, 0x6B,
+	0xF1, 0xB3, 0xC5, 0x9E, 0x2D, 0xF0, 0xF7, 0x80, 0x63, 0xB8, 0xD3, 0xF5, 0x2F, 0x10, 0x5D, 0x5C,
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+	0xF0, 0xD2, 0xEB, 0x53, 0x3E, 0x83, 0xE1, 0x9D, 0x3E, 0xCA, 0xD0, 0x97, 0xB5, 0xDE, 0x7C, 0xBF,
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+	0xEC, 0xB1, 0xA7, 0xFE, 0xCE, 0xBF, 0x17, 0xCC, 0x3A, 0x94, 0x31, 0xCD, 0x2C, 0xB7, 0xF1, 0xD8,
+	0xC8, 0xD1, 0xAB, 0xEE, 0xB8, 0x69, 0x95, 0x37, 0x70, 0xDC, 0x6E, 0x00, 0x91, 0x83, 0xC5, 0x7B,
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+	0xDD, 0x3F, 0x47, 0xB6, 0xFE, 0x24, 0xB2, 0xB6, 0x58, 0xCB, 0xFB, 0xB3, 0x0F, 0x99, 0xCF, 0xBB,
+	0x12, 0x6B, 0x77, 0x04, 0x7C, 0xD9, 0xED, 0x4E, 0xA2, 0x80, 0x3F, 0x22, 0x7F, 0x68, 0x4F, 0xF8,
+	0x3B, 0x0B, 0xE1, 0xA7, 0xEC, 0xFD, 0xF1, 0xE3, 0xC6, 0x5F, 0x03, 0x6F, 0xFF, 0x00, 0x63, 0x8F,
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+	0xBC, 0x46, 0xB9, 0x9D, 0x49, 0x29, 0x58, 0xF4, 0x23, 0x87, 0xA4, 0xE3, 0x73, 0xF7, 0x97, 0xFE,
+	0x23, 0x23, 0xF8, 0x53, 0xFF, 0x00, 0x46, 0x3D, 0xE2, 0x6F, 0xFC, 0x2A, 0xED, 0xBF, 0xF8, 0xDD,
+	0x1F, 0xF1, 0x19, 0x1F, 0xC2, 0x9F, 0xFA, 0x31, 0xEF, 0x13, 0x7F, 0xE1, 0x57, 0x6D, 0xFF, 0x00,
+	0xC6, 0xEB, 0xF0, 0x6A, 0x8A, 0x5E, 0xD2, 0x5D, 0xCA, 0xFA, 0xBD, 0x1E, 0xDF, 0x89, 0xFB, 0xCB,
+	0xFF, 0x00, 0x11, 0x91, 0xFC, 0x29, 0xFF, 0x00, 0xA3, 0x1E, 0xF1, 0x37, 0xFE, 0x15, 0x76, 0xDF,
+	0xFC, 0x6E, 0x8F, 0xF8, 0x8C, 0x8F, 0xE1, 0x4F, 0xFD, 0x18, 0xF7, 0x89, 0xBF, 0xF0, 0xAB, 0xB6,
+	0xFF, 0x00, 0xE3, 0x75, 0xF8, 0x35, 0x45, 0x1E, 0xD2, 0x5D, 0xC3, 0xEA, 0xF4, 0x7B, 0x7E, 0x27,
+	0xEF, 0x2F, 0xFC, 0x46, 0x45, 0xF0, 0xA3, 0xFE, 0x8C, 0x77, 0xC4, 0xDF, 0xF8, 0x55, 0xDB, 0x7F,
+	0xF1, 0xBA, 0x64, 0xDF, 0xF0, 0x79, 0x37, 0xC2, 0xA8, 0xE1, 0x69, 0x07, 0xEC, 0x39, 0xE2, 0x6F,
+	0x95, 0x73, 0xFF, 0x00, 0x23, 0x5D, 0xB7, 0xFF, 0x00, 0x1B, 0xAF, 0xC1, 0xDA, 0x8E, 0xEB, 0xFE,
+	0x3D, 0x64, 0xFF, 0x00, 0xAE, 0x67, 0xF9, 0x53, 0x55, 0x24, 0x1F, 0x57, 0xA3, 0xD1, 0x1F, 0xDB,
+	0x57, 0xC2, 0x1F, 0x1E, 0xC3, 0xF1, 0x63, 0xE1, 0x3F, 0x86, 0x7E, 0x29, 0xDB, 0xE9, 0x72, 0x59,
+	0xA7, 0x89, 0x3C, 0x3F, 0x67, 0xAA, 0x45, 0x6B, 0x2C, 0x81, 0xDA, 0x05, 0x9E, 0x15, 0x94, 0x46,
+	0x48, 0x18, 0x25, 0x77, 0xE3, 0x38, 0xAD, 0x0F, 0x13, 0x78, 0x43, 0xC3, 0x3E, 0x36, 0xD1, 0x64,
+	0xF0, 0xFF, 0x00, 0x8C, 0x3C, 0x3B, 0x63, 0xAA, 0xD8, 0xCB, 0xFE, 0xB6, 0xCF, 0x50, 0xB6, 0x49,
+	0xA3, 0x6F, 0x7D, 0xAE, 0x08, 0xC8, 0xFA, 0x0A, 0xE3, 0x7F, 0x63, 0x6F, 0xF9, 0x34, 0x6F, 0x85,
+	0xBF, 0xF6, 0x4E, 0xF4, 0x6F, 0xFD, 0x21, 0x86, 0xBD, 0x22, 0xBA, 0x3E, 0xC9, 0xE6, 0xBE, 0xA8,
+	0xF2, 0xDF, 0x11, 0x7E, 0xCC, 0x7E, 0x12, 0xB1, 0xFD, 0x9F, 0xBC, 0x51, 0xF0, 0x2B, 0xE1, 0x55,
+	0x94, 0x5A, 0x2D, 0xA7, 0x88, 0x2D, 0x6E, 0xD6, 0xDD, 0x64, 0x77, 0x92, 0x3B, 0x79, 0xA6, 0x4C,
+	0x33, 0x0D, 0xEC, 0xCC, 0x14, 0xFA, 0x67, 0x8E, 0xC0, 0x57, 0xC2, 0xFA, 0xB7, 0xFC, 0x13, 0x83,
+	0xF6, 0xB2, 0xD3, 0xB5, 0x19, 0x2C, 0xED, 0xFC, 0x11, 0x67, 0x78, 0x8B, 0x23, 0x15, 0xB8, 0xB5,
+	0xD5, 0x23, 0xF2, 0xE4, 0xF7, 0x01, 0xC8, 0x61, 0xF8, 0x8A, 0xFD, 0x3A, 0xA6, 0xC8, 0xBB, 0xC6,
+	0xD2, 0xB9, 0xFF, 0x00, 0x78, 0xF0, 0x69, 0x81, 0xF9, 0x93, 0xA3, 0x7F, 0xC1, 0x3E, 0x3F, 0x6B,
+	0x0B, 0x0D, 0x62, 0xD2, 0xFA, 0xE3, 0xE1, 0xBC, 0x6B, 0x1C, 0x57, 0x51, 0xBB, 0x15, 0xD5, 0x20,
+	0x27, 0x01, 0x81, 0x38, 0x01, 0xB9, 0xAF, 0x7F, 0xFF, 0x00, 0x82, 0x8A, 0x7E, 0xCC, 0xBF, 0x1A,
+	0x3E, 0x3D, 0x78, 0xEF, 0xC3, 0xDA, 0xD7, 0xC3, 0x0F, 0x0A, 0xC7, 0xA9, 0x5B, 0xD8, 0xE9, 0x12,
+	0x41, 0x73, 0x23, 0x5F, 0x47, 0x1E, 0xD7, 0x32, 0x96, 0xC6, 0x1C, 0x8C, 0xF1, 0xE8, 0x2B, 0xD7,
+	0x7E, 0x3C, 0xFC, 0x32, 0xFD, 0xA3, 0xB5, 0x99, 0xD7, 0xC4, 0x5F, 0x02, 0xFE, 0x39, 0x5D, 0xE9,
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+	0x99, 0x23, 0x38, 0xEC, 0x58, 0xF7, 0xE4, 0x74, 0x3E, 0x33, 0xFF, 0x00, 0x05, 0x1F, 0xFD, 0xA3,
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+	0xB3, 0xF6, 0xB8, 0x1C, 0x7F, 0xC2, 0xB5, 0x87, 0x1F, 0xF6, 0x15, 0xB7, 0xFF, 0x00, 0xE2, 0xAB,
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+	0xE3, 0x6F, 0x17, 0x78, 0x12, 0x3B, 0x5D, 0x37, 0x4E, 0xD4, 0x44, 0xB7, 0x73, 0xAE, 0xA5, 0x0B,
+	0x6C, 0x5D, 0xA4, 0x67, 0x0A, 0x72, 0x7F, 0x0C, 0xD6, 0xBF, 0xED, 0xAF, 0xFB, 0x1E, 0x7E, 0xD0,
+	0x9F, 0x17, 0xFF, 0x00, 0x68, 0xBD, 0x63, 0xC7, 0x7E, 0x03, 0xF0, 0x64, 0x77, 0x9A, 0x5D, 0xD5,
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+	0x72, 0xDA, 0x36, 0x6E, 0xFF, 0x00, 0x36, 0xB4, 0x3D, 0xDE, 0x1E, 0xCB, 0x31, 0x1C, 0x45, 0x88,
+	0x74, 0x70, 0xED, 0x26, 0x95, 0xFD, 0xEF, 0xF8, 0x17, 0x3E, 0x74, 0x3F, 0xF0, 0x4E, 0xBF, 0xDA,
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+	0x34, 0xB6, 0xBA, 0xA6, 0xB9, 0x1D, 0xE2, 0xE9, 0xB6, 0xAB, 0x73, 0x1B, 0xAC, 0xA5, 0xEC, 0xBC,
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+	0x79, 0x8C, 0xEE, 0x1F, 0x12, 0x2F, 0x38, 0xE7, 0xFE, 0x3D, 0xA1, 0xFF, 0x00, 0xE2, 0x6B, 0xD9,
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+	0x27, 0x9E, 0x9D, 0x71, 0xE1, 0x43, 0xFE, 0x09, 0xD5, 0xFB, 0x5D, 0x1E, 0xBF, 0x0D, 0x23, 0xFF,
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+	0xB0, 0x07, 0x86, 0xBE, 0x32, 0xD8, 0xFC, 0x42, 0x9A, 0x3F, 0x13, 0x5F, 0xF8, 0x95, 0xE1, 0xBC,
+	0xD5, 0x56, 0xC6, 0xD8, 0xB4, 0x91, 0xF9, 0xB7, 0x09, 0x8D, 0x86, 0x3F, 0x2C, 0x7C, 0xA8, 0xA3,
+	0xEE, 0xE7, 0x8E, 0xB5, 0xE0, 0x43, 0xF6, 0xFB, 0xFD, 0xB0, 0x02, 0xE3, 0xFE, 0x17, 0x6D, 0xE7,
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+	0xB2, 0xD2, 0xBC, 0x4F, 0xA6, 0xEA, 0x17, 0x9F, 0x0E, 0x61, 0x8E, 0x18, 0x6F, 0xE1, 0x92, 0x46,
+	0xFE, 0xD4, 0x83, 0x85, 0x0E, 0x09, 0x38, 0x0D, 0xCF, 0x1D, 0xAB, 0xD9, 0xFF, 0x00, 0x6F, 0x5F,
+	0xD9, 0x6B, 0xE3, 0x8F, 0xC7, 0x2F, 0x88, 0x9E, 0x1F, 0xD7, 0xFE, 0x19, 0xF8, 0x41, 0x6F, 0xED,
+	0x6C, 0xBC, 0x37, 0x1D, 0xB5, 0xC4, 0xA6, 0xF9, 0x22, 0xDB, 0x20, 0x91, 0xCE, 0x3E, 0x66, 0x04,
+	0xF1, 0xEC, 0x07, 0xE3, 0x5E, 0x19, 0xE1, 0x5F, 0xDB, 0xB7, 0xF6, 0xB6, 0xD4, 0xBC, 0x53, 0xA7,
+	0xD8, 0xDE, 0x7C, 0x69, 0xBC, 0x68, 0x66, 0xBE, 0x8A, 0x39, 0x10, 0xE9, 0x56, 0x7F, 0x3A, 0x99,
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+	0xE3, 0x9F, 0xC1, 0x5F, 0x89, 0x3E, 0x1D, 0xD0, 0xBE, 0x18, 0xFC, 0x43, 0xB8, 0xD2, 0x6C, 0xEE,
+	0xBC, 0x33, 0x1C, 0xF7, 0x11, 0xC7, 0x63, 0x6D, 0x27, 0x99, 0x27, 0x98, 0xC3, 0x77, 0xEF, 0x63,
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+	0xF8, 0x69, 0x17, 0x5F, 0xE2, 0xD5, 0xAD, 0xFF, 0x00, 0xF8, 0xAA, 0xF5, 0xCF, 0xD8, 0x73, 0xF6,
+	0x40, 0xFD, 0xA0, 0xFE, 0x0F, 0x7E, 0xD0, 0x76, 0x3E, 0x36, 0xF8, 0x81, 0xE0, 0xD8, 0xEC, 0x74,
+	0xD8, 0x74, 0xFB, 0xA8, 0xE4, 0x99, 0x75, 0x08, 0xE4, 0x21, 0x9A, 0x22, 0xAB, 0xF2, 0xA9, 0x3D,
+	0xCE, 0x3D, 0x2B, 0xC4, 0xFF, 0x00, 0xE1, 0xBE, 0xBF, 0x6C, 0x02, 0x33, 0xFF, 0x00, 0x0B, 0xAE,
+	0xF3, 0xA7, 0xFD, 0x02, 0xEC, 0xBF, 0xF8, 0xC5, 0x7B, 0x1F, 0xEC, 0x25, 0xFB, 0x56, 0xFE, 0xD0,
+	0xDF, 0x16, 0xBF, 0x68, 0x7D, 0x3F, 0xC1, 0xBF, 0x10, 0xFE, 0x27, 0x4F, 0xA9, 0x69, 0x73, 0x59,
+	0x5D, 0x49, 0x25, 0x94, 0xBA, 0x7D, 0xB4, 0x79, 0x65, 0x87, 0x70, 0x3B, 0xA3, 0x8D, 0x5B, 0xEF,
+	0x64, 0xD0, 0x07, 0xDE, 0x39, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x03, 0xF3, 0xD7, 0xFE,
+	0x0A, 0xDA, 0x73, 0xF1, 0xD3, 0xC3, 0xF8, 0xFF, 0x00, 0xA1, 0x65, 0x7F, 0xF4, 0xA1, 0xEB, 0xE5,
+	0x5A, 0xFD, 0x24, 0xFD, 0xAE, 0xF4, 0x0F, 0xD8, 0x9B, 0x57, 0xF8, 0x85, 0x63, 0x73, 0xFB, 0x4E,
+	0xEA, 0xD2, 0x5B, 0xEA, 0xAB, 0xA4, 0xED, 0xD3, 0xD5, 0x35, 0x0B, 0x98, 0x87, 0xD9, 0xFC, 0xD7,
+	0xCF, 0xFA, 0xA2, 0x07, 0x2D, 0x9E, 0xB5, 0xE5, 0x27, 0xC1, 0x5F, 0xF0, 0x48, 0xEE, 0xFE, 0x26,
+	0x98, 0xFB, 0xFF, 0x00, 0x6C, 0x5F, 0xF3, 0xFF, 0x00, 0x8F, 0x50, 0x07, 0x98, 0xFF, 0x00, 0xC1,
+	0x33, 0x41, 0xFF, 0x00, 0x86, 0xAE, 0xD2, 0xF8, 0xFF, 0x00, 0x98, 0x6D, 0xF7, 0x4F, 0xFA, 0xE0,
+	0x6B, 0x81, 0xFD, 0xAD, 0x39, 0xFD, 0xA7, 0x7C, 0x7C, 0x47, 0xFD, 0x0D, 0x57, 0x9F, 0xFA, 0x36,
+	0xBE, 0xCC, 0xFD, 0x99, 0x3C, 0x39, 0xFF, 0x00, 0x04, 0xFF, 0x00, 0xD2, 0xBE, 0x2E, 0x5A, 0x5E,
+	0xFE, 0xCF, 0x7A, 0xDC, 0x93, 0x78, 0x91, 0x6D, 0x6E, 0x3E, 0xCA, 0xBF, 0xDA, 0x17, 0x52, 0x82,
+	0x9E, 0x59, 0xDF, 0xC4, 0x9C, 0x7D, 0xDF, 0x5A, 0xE7, 0xFE, 0x2A, 0xF8, 0x4B, 0xFE, 0x09, 0x9B,
+	0x77, 0xF1, 0x37, 0xC4, 0x17, 0x5F, 0x14, 0xBC, 0x43, 0x34, 0x3E, 0x23, 0x97, 0x58, 0xB8, 0x6D,
+	0x6A, 0x3F, 0xED, 0x4B, 0xC4, 0x02, 0xE3, 0x79, 0xDF, 0xF2, 0xA1, 0xDA, 0x3D, 0x38, 0xE2, 0x80,
+	0x3E, 0x11, 0x00, 0x93, 0x8A, 0xFB, 0x13, 0xFE, 0x09, 0xED, 0xFF, 0x00, 0x26, 0xC3, 0xF1, 0x90,
+	0xE3, 0xAE, 0x91, 0x27, 0xFE, 0x90, 0xDC, 0x55, 0xA1, 0xE0, 0xBF, 0xF8, 0x24, 0x6F, 0x6F, 0x12,
+	0xCB, 0xF8, 0xEB, 0x17, 0xFF, 0x00, 0xFC, 0x55, 0x7B, 0x07, 0xEC, 0xF9, 0xA2, 0x7E, 0xC7, 0xBA,
+	0x77, 0xC2, 0xBF, 0x1B, 0x5A, 0xFC, 0x07, 0xD5, 0x64, 0x93, 0x41, 0x9A, 0xCD, 0xC7, 0x89, 0x9D,
+	0xAE, 0xA7, 0x93, 0x6C, 0x7F, 0x67, 0x97, 0x24, 0x17, 0xE4, 0x7E, 0xEF, 0x7F, 0xDD, 0xE4, 0x7D,
+	0x68, 0x03, 0xF3, 0x3D, 0x3E, 0xE2, 0xF1, 0xDB, 0xFA, 0x0A, 0x70, 0xEB, 0x5F, 0x67, 0x2F, 0x82,
+	0xFF, 0x00, 0xE0, 0x91, 0xFE, 0x5A, 0xA8, 0xF1, 0x34, 0xC1, 0x42, 0x80, 0x14, 0xEB, 0x57, 0xFC,
+	0x7B, 0x7D, 0xEF, 0xF3, 0x9A, 0x3F, 0xE1, 0x09, 0xFF, 0x00, 0x82, 0x47, 0x0E, 0x9E, 0x24, 0x97,
+	0xFF, 0x00, 0x07, 0x17, 0xDF, 0xFC, 0x55, 0x00, 0x61, 0x7E, 0xD2, 0xFC, 0x7F, 0xC1, 0x29, 0xFE,
+	0x1E, 0xE4, 0x7F, 0xCC, 0x7A, 0xD7, 0xFF, 0x00, 0x6F, 0x6B, 0xE2, 0x25, 0x07, 0x00, 0x60, 0xFD,
+	0xDF, 0x4A, 0xFD, 0x4E, 0xF8, 0xAB, 0xE1, 0xFF, 0x00, 0xD8, 0xB6, 0xFB, 0xF6, 0x4B, 0xF0, 0xDE,
+	0x8B, 0xE3, 0xCF, 0x11, 0xCF, 0x6B, 0xF0, 0xDD, 0x35, 0x08, 0x8E, 0x8B, 0x75, 0x1D, 0xDC, 0xCA,
+	0xC6, 0x6F, 0xDF, 0xED, 0x05, 0xB0, 0x5C, 0xF5, 0x97, 0x82, 0x31, 0xC6, 0x7D, 0x2B, 0xC2, 0x7F,
+	0xE1, 0x5C, 0xFF, 0x00, 0xC1, 0x1E, 0x07, 0x03, 0xE2, 0x5E, 0xA5, 0xF2, 0xF1, 0xFF, 0x00, 0x21,
+	0x5B, 0xAF, 0xFE, 0x22, 0xB9, 0x6A, 0x47, 0xDF, 0xB9, 0xA4, 0x79, 0xAC, 0x7C, 0xF3, 0xFB, 0x13,
+	0x7C, 0xDF, 0xB5, 0xB7, 0xC3, 0xF1, 0xBB, 0xFE, 0x66, 0x28, 0xC7, 0xFE, 0x38, 0xF5, 0x73, 0xFE,
+	0x0A, 0xB3, 0xCF, 0xED, 0xCD, 0xE2, 0xEC, 0x7F, 0xCF, 0xAE, 0x9B, 0xCF, 0xFD, 0xB8, 0xC3, 0x5F,
+	0x53, 0x7C, 0x0C, 0xF0, 0x37, 0xFC, 0x12, 0xF7, 0x4D, 0xF8, 0xC3, 0xE1, 0xDB, 0xFF, 0x00, 0x84,
+	0x7E, 0x3D, 0xD4, 0x2E, 0xBC, 0x4D, 0x16, 0xA4, 0x1B, 0x45, 0xB7, 0x93, 0x52, 0xB8, 0x65, 0x79,
+	0xF6, 0xB6, 0x01, 0x0C, 0xA0, 0x74, 0xCF, 0x7A, 0x97, 0xF6, 0xB3, 0xF0, 0x47, 0xFC, 0x13, 0x1B,
+	0x5A, 0xF8, 0xF3, 0xAC, 0xEA, 0x5F, 0xB4, 0x77, 0x8E, 0x6F, 0x2C, 0xBC, 0x5D, 0x24, 0x56, 0xA3,
+	0x52, 0xB7, 0x8B, 0x50, 0xB9, 0x8D, 0x42, 0x88, 0x13, 0xCA, 0x38, 0x55, 0x23, 0xFD, 0x5E, 0xDE,
+	0xFD, 0xEB, 0xD0, 0xCB, 0x65, 0xEC, 0x6A, 0xB7, 0xBF, 0xA1, 0xC3, 0x8F, 0x8F, 0xB6, 0xA6, 0x95,
+	0xED, 0xEA, 0x7E, 0x65, 0x15, 0x66, 0x04, 0x28, 0xEC, 0x7F, 0x95, 0x7D, 0xF3, 0xFF, 0x00, 0x04,
+	0xAC, 0x38, 0xFD, 0x90, 0x3E, 0x33, 0x0C, 0x8F, 0xBC, 0xFF, 0x00, 0xC5, 0xFF, 0x00, 0x4E, 0x26,
+	0xAA, 0x3F, 0xC3, 0x1F, 0xF8, 0x22, 0x8C, 0x88, 0xCA, 0x3E, 0x26, 0x6A, 0x43, 0xDC, 0x6A, 0xD7,
+	0x99, 0x1F, 0xF8, 0xE5, 0x7D, 0x09, 0xFB, 0x24, 0x78, 0x6B, 0xF6, 0x24, 0xD0, 0xFE, 0x10, 0x78,
+	0xD2, 0xCF, 0xF6, 0x77, 0xF1, 0x3D, 0xC5, 0xF7, 0x85, 0xEE, 0x18, 0x9F, 0x15, 0x49, 0x35, 0xD4,
+	0xEF, 0xB0, 0xF9, 0x07, 0x3B, 0x59, 0xD4, 0x30, 0xFD, 0xDE, 0x4F, 0x1F, 0xFD, 0x6A, 0xF4, 0x31,
+	0x78, 0x88, 0xD4, 0xA2, 0xE3, 0xCA, 0xD6, 0xBD, 0x4E, 0x3C, 0x1D, 0x0F, 0x67, 0x59, 0x3E, 0x64,
+	0xF7, 0xEA, 0x7E, 0x71, 0xC0, 0x0F, 0x92, 0x8D, 0xFE, 0xC8, 0xFE, 0x42, 0xA6, 0xB3, 0xFF, 0x00,
+	0x8F, 0xA8, 0xFF, 0x00, 0xEB, 0xA2, 0xFF, 0x00, 0x3A, 0xFB, 0x29, 0x7C, 0x17, 0xFF, 0x00, 0x04,
+	0x90, 0x68, 0x94, 0xB7, 0x89, 0xE6, 0xFC, 0x75, 0x8B, 0xFF, 0x00, 0x4F, 0x76, 0xE2, 0x9F, 0x0F,
+	0x83, 0x3F, 0xE0, 0x92, 0x2B, 0x2A, 0xB4, 0x5E, 0x24, 0x9B, 0x70, 0x39, 0x1F, 0xF1, 0x38, 0xBF,
+	0xFF, 0x00, 0xE2, 0xBF, 0xFA, 0xD5, 0xE4, 0x9E, 0xB1, 0x53, 0xFE, 0x0A, 0x96, 0xCB, 0xFF, 0x00,
+	0x08, 0x07, 0xC2, 0x76, 0xCF, 0xFC, 0xC3, 0x6E, 0xBF, 0xF4, 0x55, 0xA5, 0x7C, 0xC3, 0xF0, 0x87,
+	0xE0, 0xD7, 0xC4, 0x1F, 0x8E, 0x5E, 0x30, 0x87, 0xC1, 0x3F, 0x0F, 0x34, 0x39, 0x2E, 0xAE, 0xA4,
+	0xE6, 0x69, 0xB1, 0x88, 0xAD, 0xA3, 0x24, 0x83, 0x24, 0x8F, 0xD1, 0x57, 0xAF, 0xD7, 0x9C, 0x03,
+	0xD2, 0xBE, 0xBA, 0xFF, 0x00, 0x82, 0xB2, 0x7E, 0xD2, 0x1F, 0xB0, 0x6F, 0xEC, 0xB5, 0xFB, 0x3D,
+	0x68, 0x7F, 0x14, 0xFF, 0x00, 0x6A, 0xD6, 0xBE, 0xD5, 0x1A, 0xD2, 0xC2, 0x75, 0xF8, 0x7F, 0xE1,
+	0xBD, 0x23, 0x51, 0x9A, 0x2B, 0xDD, 0x6A, 0x62, 0x90, 0x8F, 0x22, 0x2D, 0xAC, 0xB8, 0xFF, 0x00,
+	0x96, 0x5B, 0xA4, 0x72, 0x02, 0x0C, 0xB1, 0x3C, 0x62, 0xBF, 0x9C, 0xDF, 0x17, 0x7F, 0xC1, 0x56,
+	0x7F, 0x6E, 0xAD, 0x4F, 0xC6, 0xFA, 0xCF, 0x89, 0xFE, 0x16, 0x7E, 0xD1, 0x5E, 0x34, 0xF8, 0x73,
+	0xA4, 0xEA, 0x97, 0x9E, 0x7D, 0xAF, 0x85, 0x7C, 0x0B, 0xE3, 0x0B, 0xEB, 0x3B, 0x1B, 0x18, 0xBA,
+	0x47, 0x1A, 0xEC, 0x91, 0x4C, 0xC4, 0x28, 0xC7, 0x98, 0xFF, 0x00, 0x33, 0xE3, 0x3C, 0x0C, 0x01,
+	0x9C, 0xAA, 0x72, 0x9B, 0x53, 0xA3, 0x2A, 0x9A, 0x9F, 0xD4, 0xE7, 0xEC, 0xA3, 0xFB, 0x1C, 0xFC,
+	0x3F, 0xFD, 0x98, 0xB4, 0xA3, 0x7D, 0x66, 0xC3, 0x52, 0xF1, 0x25, 0xED, 0xB8, 0x4D, 0x4B, 0x5A,
+	0x90, 0x63, 0xE5, 0xE0, 0x98, 0xE2, 0x5F, 0xE0, 0x4C, 0x81, 0xEE, 0xDB, 0x41, 0x3D, 0x00, 0x1E,
+	0xC6, 0x08, 0xFE, 0xF5, 0x7F, 0x1E, 0x47, 0xFE, 0x0A, 0xB1, 0xFF, 0x00, 0x05, 0x34, 0x3C, 0xFF,
+	0x00, 0xC3, 0xC0, 0xBE, 0x32, 0x7B, 0xFF, 0x00, 0xC5, 0xC6, 0xD4, 0x86, 0x7F, 0xF2, 0x3D, 0x1F,
+	0xF0, 0xF5, 0x8F, 0xF8, 0x29, 0x9F, 0xFD, 0x24, 0x07, 0xE3, 0x27, 0xFE, 0x1C, 0x8D, 0x4B, 0xFF,
+	0x00, 0x8F, 0x54, 0xFB, 0x43, 0x4F, 0xAA, 0xCB, 0xB9, 0xFD, 0x86, 0xB3, 0xAA, 0x8C, 0x93, 0x4A,
+	0x3E, 0x63, 0x91, 0xF4, 0xAF, 0xE3, 0xC7, 0xFE, 0x1E, 0xAF, 0xFF, 0x00, 0x05, 0x33, 0x63, 0xF3,
+	0x7F, 0xC1, 0x40, 0xBE, 0x32, 0x63, 0xBF, 0xFC, 0x5C, 0x8D, 0x4B, 0xFF, 0x00, 0x8F, 0x57, 0xEB,
+	0xDF, 0xFC, 0x1A, 0x97, 0xFB, 0x56, 0xFE, 0xD3, 0xBF, 0xB4, 0xCE, 0xB7, 0xF1, 0x92, 0x3F, 0xDA,
+	0x27, 0xF6, 0x84, 0xF1, 0x97, 0x8E, 0x57, 0x49, 0xB5, 0xD1, 0xCE, 0x96, 0xBE, 0x2C, 0xF1, 0x25,
+	0xCE, 0xA0, 0x2D, 0x4B, 0xB5, 0xC8, 0x73, 0x17, 0x9E, 0xED, 0xB3, 0x76, 0xD1, 0x9C, 0x63, 0x35,
+	0x51, 0xA9, 0xCC, 0xEC, 0x67, 0x2C, 0x3C, 0xA1, 0x1E, 0x66, 0xCF, 0xD9, 0x3A, 0x39, 0xF4, 0xAE,
+	0x7F, 0xE2, 0x27, 0xC5, 0x1F, 0x87, 0x5F, 0x08, 0xF4, 0x28, 0x7C, 0x4F, 0xF1, 0x3B, 0xC6, 0x9A,
+	0x7E, 0x83, 0xA7, 0xCF, 0xA8, 0x5B, 0xD8, 0xC3, 0x7B, 0xAA, 0x5D, 0x2C, 0x31, 0xC9, 0x73, 0x3C,
+	0x82, 0x38, 0x61, 0x0C, 0xC4, 0x0D, 0xEE, 0xEC, 0x15, 0x57, 0xA9, 0x24, 0x01, 0x56, 0x63, 0xF1,
+	0xC7, 0x84, 0x2E, 0xEE, 0x75, 0x6B, 0x0B, 0x7F, 0x11, 0xD9, 0xC9, 0x26, 0x82, 0xCA, 0x35, 0xC8,
+	0xC5, 0xD2, 0x66, 0xC0, 0xB4, 0x42, 0x65, 0xF3, 0xB9, 0xF9, 0x33, 0x1B, 0x2B, 0xF3, 0x8F, 0x94,
+	0x83, 0xD0, 0xD6, 0x86, 0x27, 0xF1, 0xED, 0xFF, 0x00, 0x05, 0x26, 0xFF, 0x00, 0x94, 0x81, 0xFC,
+	0x6A, 0x39, 0xFF, 0x00, 0x9A, 0x9D, 0xAD, 0x13, 0xED, 0xFE, 0x96, 0xFC, 0xD7, 0x89, 0xFF, 0x00,
+	0xF1, 0x39, 0xAF, 0xEA, 0xBE, 0x0F, 0xF8, 0x23, 0xB7, 0xFC, 0x11, 0x6B, 0xF6, 0xBE, 0xBD, 0xD4,
+	0xBF, 0x68, 0xED, 0x17, 0xF6, 0x7F, 0xF0, 0xCF, 0x8D, 0x9F, 0xC5, 0x5A, 0xB5, 0xD5, 0xF5, 0xF7,
+	0x89, 0xB4, 0x8F, 0x16, 0xEA, 0x13, 0x43, 0x7B, 0x76, 0xD2, 0xB7, 0x9E, 0xC0, 0xC3, 0x77, 0xE5,
+	0x83, 0xE6, 0x06, 0x05, 0x40, 0x18, 0x3C, 0x71, 0x5F, 0x23, 0x78, 0x37, 0xFE, 0x08, 0xF1, 0xFF,
+	0x00, 0x04, 0xE2, 0xD5, 0x7F, 0xE0, 0xB8, 0xDE, 0x2E, 0xFD, 0x93, 0xF5, 0x1F, 0xD9, 0x92, 0xC2,
+	0x4F, 0x87, 0xFA, 0x7F, 0xEC, 0xFB, 0x0F, 0x88, 0xAC, 0xBC, 0x3B, 0xFD, 0xBD, 0xA8, 0xEC, 0x8B,
+	0x53, 0x6D, 0x52, 0xD6, 0x16, 0xB8, 0xF3, 0x3E, 0xD1, 0xE6, 0x12, 0x63, 0x91, 0x97, 0x69, 0x62,
+	0xA3, 0x3D, 0x3A, 0x11, 0xCE, 0xE9, 0xC8, 0xF4, 0x23, 0x88, 0x8D, 0xAD, 0x6D, 0x8F, 0xC0, 0x92,
+	0x71, 0xD6, 0x8A, 0xFE, 0xAE, 0x1B, 0xFE, 0x0D, 0xE0, 0xFF, 0x00, 0x82, 0x38, 0x2A, 0xE5, 0xBF,
+	0x62, 0xCD, 0x2F, 0xAF, 0xFD, 0x0C, 0xDA, 0xB7, 0xFF, 0x00, 0x25, 0xD7, 0x2B, 0x6F, 0xFF, 0x00,
+	0x04, 0x53, 0xFF, 0x00, 0x82, 0x03, 0xDC, 0x78, 0xDB, 0xFE, 0x15, 0xA5, 0xBF, 0xC0, 0x6F, 0x02,
+	0xC9, 0xE2, 0x45, 0x62, 0xAD, 0xE1, 0xD8, 0xFE, 0x22, 0x5F, 0x35, 0xF0, 0x60, 0x37, 0x11, 0xE4,
+	0x0B, 0xEF, 0x33, 0x38, 0xE7, 0x1B, 0x7A, 0x73, 0x47, 0xB3, 0x90, 0x7D, 0x6A, 0x9F, 0x63, 0xF9,
+	0x71, 0x3C, 0x0C, 0x9A, 0x2B, 0xFA, 0x86, 0xBE, 0xFF, 0x00, 0x82, 0x36, 0x7F, 0xC1, 0xBE, 0x5A,
+	0x6F, 0x8C, 0x3F, 0xE1, 0x5E, 0xEA, 0x1F, 0x06, 0x3E, 0x1D, 0xDB, 0xF8, 0x83, 0xED, 0x89, 0x69,
+	0xFD, 0x87, 0x37, 0xC4, 0xAB, 0xC5, 0xBC, 0xF3, 0xDC, 0x8D, 0x91, 0x79, 0x26, 0xFF, 0x00, 0x7F,
+	0x98, 0xC5, 0x97, 0x0B, 0x8D, 0xC7, 0x70, 0xC0, 0xE4, 0x56, 0xA7, 0x8D, 0x7F, 0xE0, 0x86, 0x3F,
+	0xF0, 0x42, 0x5F, 0x86, 0xCD, 0x67, 0x17, 0xC4, 0x1F, 0xD9, 0xB7, 0xC1, 0xFA, 0x0B, 0x6A, 0x53,
+	0x88, 0x74, 0xF5, 0xD6, 0x7C, 0x79, 0xA8, 0xDA, 0x9B, 0x99, 0x09, 0xC0, 0x48, 0xFC, 0xCB, 0xD1,
+	0xBD, 0x89, 0x23, 0x81, 0x93, 0xCD, 0x1C, 0x92, 0x0F, 0xAD, 0x53, 0xEC, 0x7F, 0x2C, 0xB5, 0x1D,
+	0xD9, 0x02, 0xD6, 0x42, 0x7F, 0xE7, 0x9B, 0x7F, 0x2A, 0xFE, 0xA8, 0x64, 0xFF, 0x00, 0x82, 0x12,
+	0xFF, 0x00, 0xC1, 0x0C, 0xE3, 0xD4, 0x35, 0x0D, 0x21, 0xFF, 0x00, 0x65, 0xEF, 0x0A, 0xAD, 0xD6,
+	0x91, 0x6A, 0xB7, 0x5A, 0xB5, 0xAF, 0xFC, 0x26, 0xFA, 0x90, 0x92, 0xC6, 0x06, 0x04, 0xAC, 0xB3,
+	0x29, 0xBD, 0xCC, 0x48, 0x40, 0x38, 0x66, 0xC0, 0x38, 0x3C, 0xF0, 0x6A, 0xDD, 0xEF, 0xFC, 0x1B,
+	0xFF, 0x00, 0xFF, 0x00, 0x04, 0x55, 0xB6, 0x5B, 0x78, 0xEF, 0x3F, 0x63, 0xED, 0x0E, 0x31, 0x7D,
+	0x32, 0xC3, 0x6F, 0xE7, 0x78, 0xBB, 0x54, 0x5F, 0x3D, 0x98, 0x1C, 0x22, 0x66, 0xF0, 0x16, 0x24,
+	0x03, 0x80, 0xB9, 0x3C, 0x7A, 0x66, 0x88, 0xC2, 0x40, 0xF1, 0x30, 0xEC, 0x7D, 0x39, 0xFB, 0x1B,
+	0x91, 0xFF, 0x00, 0x0C, 0x8F, 0xF0, 0xB4, 0x67, 0xFE, 0x69, 0xDE, 0x8D, 0xFF, 0x00, 0xA4, 0x30,
+	0xD7, 0xA4, 0x13, 0x8E, 0xB5, 0xCF, 0xF8, 0x2A, 0xC3, 0xC1, 0xBE, 0x08, 0xD2, 0xB4, 0xDF, 0x85,
+	0xBE, 0x16, 0x6B, 0x6B, 0x48, 0x74, 0x8D, 0x1E, 0x18, 0xB4, 0xED, 0x29, 0x6E, 0x37, 0x49, 0x15,
+	0x94, 0x4A, 0xB1, 0x46, 0x42, 0xB3, 0x33, 0x94, 0x00, 0x05, 0xDE, 0x49, 0xC9, 0x18, 0xCE, 0x6B,
+	0xA0, 0x23, 0x23, 0x15, 0xD0, 0x70, 0xF9, 0x81, 0x38, 0xEB, 0x48, 0x19, 0x4F, 0x43, 0x5F, 0x98,
+	0xDF, 0xF0, 0x74, 0xEF, 0xED, 0x11, 0xF1, 0xE7, 0xF6, 0x6B, 0xFD, 0x8B, 0xFE, 0x1E, 0x78, 0xBB,
+	0xF6, 0x7C, 0xF8, 0xCF, 0xE2, 0x8F, 0x04, 0x6A, 0x97, 0xDF, 0x15, 0xE0, 0xB2, 0xBC, 0xD4, 0xBC,
+	0x2B, 0xAE, 0x4F, 0x61, 0x3C, 0xF6, 0xC7, 0x4B, 0xD4, 0x64, 0x30, 0xB4, 0x90, 0xB2, 0xB3, 0x21,
+	0x78, 0xD1, 0x8A, 0x93, 0x82, 0x51, 0x4F, 0x50, 0x2B, 0xF0, 0xA9, 0x7F, 0xE0, 0xAA, 0xFF, 0x00,
+	0xF0, 0x53, 0x5F, 0xE2, 0xFF, 0x00, 0x82, 0x81, 0x7C, 0x64, 0xFA, 0x7F, 0xC2, 0xC8, 0xD4, 0xB8,
+	0xFF, 0x00, 0xC8, 0xD5, 0x9C, 0xAA, 0x72, 0xBB, 0x1A, 0x53, 0xA1, 0x2A, 0x91, 0xB9, 0xFD, 0x87,
+	0xEE, 0xE7, 0x23, 0x6D, 0x79, 0xBF, 0xED, 0x0D, 0xFB, 0x33, 0xFC, 0x33, 0xFD, 0xA3, 0xFC, 0x30,
+	0xDA, 0x17, 0x8D, 0xF4, 0xFF, 0x00, 0x2E, 0xF2, 0x14, 0x23, 0x4C, 0xD5, 0xAD, 0xD4, 0x7D, 0xA2,
+	0xCD, 0x88, 0xED, 0xD4, 0x3A, 0xF5, 0xCA, 0x11, 0x82, 0x3D, 0x0E, 0x18, 0x7F, 0x27, 0x3F, 0xF0,
+	0xF5, 0x7F, 0xF8, 0x29, 0xAF, 0xFD, 0x24, 0x0F, 0xE3, 0x27, 0xFE, 0x1C, 0x8D, 0x4B, 0xFF, 0x00,
+	0x8F, 0x50, 0x7F, 0xE0, 0xAA, 0xFF, 0x00, 0xF0, 0x53, 0x52, 0xB8, 0x1F, 0xF0, 0x50, 0x2F, 0x8C,
+	0x9F, 0xF8, 0x72, 0x35, 0x2E, 0x7F, 0xF2, 0x35, 0x4F, 0xB4, 0x34, 0xFA, 0xAC, 0xCF, 0xDA, 0x2F,
+	0xDA, 0x33, 0xF6, 0x6B, 0xF8, 0x89, 0xFB, 0x37, 0xF8, 0xB1, 0xB4, 0x6F, 0x18, 0xDB, 0x7D, 0xA2,
+	0xC2, 0xE2, 0x42, 0x74, 0xDD, 0x6A, 0xDF, 0x2D, 0x0D, 0xDA, 0xF6, 0xE4, 0xFD, 0xD7, 0xC0, 0xFB,
+	0xA4, 0xE7, 0x8C, 0x0C, 0xE3, 0x35, 0xEE, 0x9F, 0xF0, 0x48, 0x7C, 0xA7, 0xC5, 0x3F, 0x18, 0x17,
+	0x0C, 0xBF, 0xF1, 0x21, 0xB7, 0x1F, 0x30, 0xFF, 0x00, 0xA6, 0xE7, 0xFC, 0x7F, 0x0A, 0xFE, 0x78,
+	0xEE, 0x3F, 0xE0, 0xA8, 0x9F, 0xF0, 0x51, 0x5D, 0x4E, 0x68, 0x7F, 0xE1, 0x25, 0xFD, 0xB5, 0x7E,
+	0x26, 0x6B, 0x96, 0xB0, 0xDC, 0x24, 0xD2, 0x69, 0x7E, 0x20, 0xF1, 0x95, 0xED, 0xF5, 0x9C, 0xEC,
+	0xA7, 0x85, 0x92, 0x09, 0xA5, 0x68, 0xD9, 0x7D, 0x55, 0x81, 0x07, 0xD8, 0xE0, 0x8F, 0xDF, 0x9F,
+	0xF8, 0x20, 0xA7, 0xED, 0xCB, 0xFB, 0x19, 0x7E, 0xD8, 0x7E, 0x06, 0xBE, 0xD4, 0xBE, 0x17, 0x78,
+	0x65, 0xBC, 0x23, 0xF1, 0x5A, 0xD7, 0x4A, 0x8A, 0x3F, 0x1C, 0x78, 0x46, 0x4D, 0x5A, 0x7B, 0x88,
+	0xDE, 0x35, 0x71, 0x8B, 0xAB, 0x33, 0x2B, 0x12, 0xF0, 0x33, 0x60, 0xF5, 0x2F, 0x11, 0x7D, 0x8E,
+	0x48, 0x0A, 0xEF, 0xA4, 0x6A, 0x29, 0x19, 0xD4, 0xA3, 0x3A, 0x68, 0xF9, 0xF7, 0xC6, 0x9F, 0xF2,
+	0x38, 0xEB, 0x1F, 0xF6, 0x14, 0xB8, 0xFF, 0x00, 0xD1, 0xAF, 0x59, 0x84, 0x16, 0x18, 0x51, 0x9E,
+	0x0F, 0xF2, 0xAF, 0xB6, 0x35, 0xAF, 0x07, 0xFF, 0x00, 0xC1, 0x28, 0x65, 0xD5, 0xEF, 0x65, 0xD6,
+	0x3C, 0x51, 0x31, 0xBA, 0x92, 0xF2, 0x46, 0xBC, 0xFF, 0x00, 0x89, 0xB5, 0xF2, 0xE2, 0x5D, 0xE7,
+	0x77, 0x00, 0x81, 0xD7, 0x3D, 0x2A, 0xA9, 0xF0, 0x47, 0xFC, 0x12, 0x35, 0xC6, 0xD3, 0xE2, 0x59,
+	0x39, 0xFF, 0x00, 0xA8, 0xC5, 0xF7, 0xFF, 0x00, 0x15, 0x54, 0x63, 0xEA, 0x73, 0x7F, 0xB6, 0x46,
+	0x0F, 0xFC, 0x12, 0x9B, 0xE1, 0xD8, 0xCF, 0xFC, 0xBE, 0x69, 0xD9, 0xE7, 0xA7, 0xCB, 0x2D, 0x7E,
+	0x7E, 0x80, 0x4F, 0x41, 0x5F, 0xAE, 0xBF, 0x1C, 0xFC, 0x3D, 0xFB, 0x12, 0xEA, 0x5F, 0xB2, 0x47,
+	0x86, 0xF4, 0x9F, 0x8A, 0x3E, 0x22, 0xB8, 0xB5, 0xF8, 0x6F, 0x1D, 0xC5, 0xBF, 0xF6, 0x1D, 0xC4,
+	0x37, 0x73, 0xA3, 0x3B, 0x61, 0xFC, 0xA0, 0x59, 0x41, 0x73, 0x91, 0xBB, 0xEF, 0x7A, 0x73, 0xD2,
+	0xBE, 0x76, 0x5F, 0x86, 0x3F, 0xF0, 0x45, 0x45, 0x25, 0x4F, 0xC4, 0xDD, 0x4B, 0xE5, 0x00, 0x7F,
+	0xC8, 0x5A, 0xF3, 0x93, 0xFF, 0x00, 0x7C, 0x57, 0xAD, 0x81, 0xC4, 0x7B, 0x1A, 0x3A, 0xC5, 0xF5,
+	0xE8, 0x78, 0xF8, 0xCA, 0x3E, 0xD2, 0xB5, 0xF9, 0x92, 0xDB, 0x76, 0x7C, 0xDB, 0xFB, 0x09, 0x29,
+	0xFF, 0x00, 0x86, 0xC1, 0xF8, 0x77, 0x91, 0xFF, 0x00, 0x33, 0x35, 0xBF, 0xFE, 0x85, 0x5F, 0x64,
+	0xFE, 0xD5, 0xE0, 0x8F, 0x8F, 0x5A, 0xD3, 0x1F, 0xFA, 0x63, 0xFF, 0x00, 0xA2, 0xC5, 0x41, 0xF0,
+	0x07, 0xC0, 0x1F, 0xF0, 0x4A, 0x1D, 0x3B, 0xE3, 0x37, 0x86, 0xF5, 0x0F, 0x83, 0x5E, 0x3D, 0xBE,
+	0xBA, 0xF1, 0x44, 0x3A, 0xA4, 0x6F, 0xA1, 0xDB, 0xC9, 0xA9, 0x5D, 0x3A, 0xBD, 0xC6, 0x7E, 0x51,
+	0x86, 0x50, 0xA7, 0x9F, 0x52, 0x05, 0x7B, 0x37, 0xC6, 0x2F, 0x0F, 0xFE, 0xCA, 0x77, 0xBF, 0x10,
+	0xEF, 0xAE, 0x7E, 0x22, 0x78, 0x8E, 0xE2, 0x0D, 0x61, 0x9A, 0x33, 0x77, 0x0C, 0x33, 0x48, 0xAA,
+	0x3F, 0x76, 0xB8, 0xE0, 0x03, 0xDB, 0xDE, 0xBF, 0x05, 0xFA, 0x42, 0xE4, 0x72, 0xE2, 0x8E, 0x19,
+	0xA5, 0x42, 0x15, 0xA1, 0x49, 0xA9, 0x27, 0xCD, 0x51, 0xA8, 0xA7, 0xE4, 0x9B, 0xBE, 0xA7, 0xDD,
+	0x70, 0x06, 0x32, 0x39, 0x56, 0x63, 0x2A, 0x8E, 0x32, 0x9A, 0xE5, 0xB7, 0xB8, 0xAE, 0xCF, 0x96,
+	0x58, 0x7A, 0x57, 0xD0, 0x5F, 0xB3, 0xA0, 0xCF, 0xEC, 0xB9, 0xF1, 0x3D, 0x7F, 0x8B, 0xFB, 0x37,
+	0x50, 0x1F, 0xF9, 0x20, 0x69, 0x83, 0xC2, 0xBF, 0xB0, 0xF7, 0xDE, 0x5F, 0x17, 0xDE, 0xEE, 0xFF,
+	0x00, 0xAF, 0x89, 0x7F, 0xF8, 0x8A, 0xF4, 0x9F, 0x85, 0x5A, 0x37, 0xEC, 0xF1, 0x61, 0xF0, 0xA3,
+	0xC5, 0x16, 0xBE, 0x11, 0xD4, 0xEE, 0x2E, 0x3C, 0x3D, 0x25, 0xBD, 0xC7, 0xFC, 0x24, 0x12, 0x4D,
+	0x34, 0x9B, 0x96, 0x33, 0x6F, 0xFB, 0xC0, 0x0E, 0x01, 0xFF, 0x00, 0x57, 0x9E, 0x9C, 0xD7, 0xE1,
+	0x5E, 0x0B, 0xF8, 0x7F, 0x5B, 0x87, 0xF8, 0xDE, 0x9E, 0x2E, 0x58, 0xDA, 0x15, 0x52, 0x8C, 0x97,
+	0x2C, 0x26, 0x9C, 0xB5, 0x5B, 0xA5, 0x6D, 0x97, 0x53, 0xED, 0xF8, 0xB7, 0x3F, 0x8E, 0x61, 0x93,
+	0xBA, 0x2A, 0x8C, 0xE3, 0xEF, 0x27, 0x79, 0x46, 0xCB, 0x4F, 0x3B, 0x9F, 0x96, 0x63, 0xFD, 0x5A,
+	0xB6, 0xDE, 0xAB, 0xFD, 0x68, 0x07, 0x07, 0x35, 0xF6, 0x70, 0xF0, 0x67, 0xFC, 0x12, 0x3D, 0x86,
+	0x7F, 0xE1, 0x26, 0x9B, 0xA7, 0xFD, 0x06, 0x2F, 0xFF, 0x00, 0xAB, 0x71, 0xF4, 0xF6, 0xA0, 0x78,
+	0x2B, 0xFE, 0x09, 0x1D, 0x91, 0xB3, 0xC4, 0xD2, 0xF5, 0xC7, 0xCD, 0xAD, 0x5F, 0xFF, 0x00, 0xF1,
+	0x55, 0xFD, 0xB2, 0x7E, 0x4C, 0x72, 0xBE, 0x3E, 0xE3, 0xFE, 0x09, 0x65, 0xE0, 0xD5, 0x3D, 0x7F,
+	0xE1, 0x2C, 0x93, 0xFF, 0x00, 0x47, 0xDD, 0x57, 0xCB, 0x7D, 0xFE, 0xEF, 0xA7, 0xF2, 0xAF, 0xD1,
+	0xDD, 0x77, 0xC3, 0xFF, 0x00, 0xB1, 0x34, 0x9F, 0xB2, 0xC6, 0x8F, 0xA3, 0xEB, 0x7A, 0xB4, 0x8B,
+	0xF0, 0xDE, 0x1D, 0x79, 0xBF, 0xB2, 0xE6, 0x5B, 0xDB, 0x90, 0x5A, 0x7D, 0xD2, 0xF5, 0x61, 0xFB,
+	0xCE, 0x1F, 0xCC, 0xEB, 0xC7, 0xE6, 0x33, 0xE6, 0x07, 0xC1, 0x5F, 0xF0, 0x48, 0xF3, 0xF7, 0xBC,
+	0x51, 0x31, 0xFF, 0x00, 0xB8, 0xD5, 0xFF, 0x00, 0xFF, 0x00, 0x15, 0xFE, 0x73, 0x40, 0x1F, 0x23,
+	0xF8, 0x23, 0x71, 0xF1, 0x9E, 0x92, 0x7F, 0xEA, 0x25, 0x07, 0xFE, 0x8C, 0x5A, 0xFA, 0x33, 0xFE,
+	0x0A, 0xA6, 0x7F, 0xE2, 0xEF, 0x78, 0x57, 0xAF, 0xFC, 0x8A, 0x31, 0x76, 0xFF, 0x00, 0xA6, 0xCD,
+	0x5D, 0xB6, 0x8D, 0xE0, 0xEF, 0xF8, 0x25, 0x14, 0x5A, 0xCD, 0x9B, 0xE8, 0x7E, 0x23, 0x95, 0xAE,
+	0xC5, 0xD4, 0x66, 0xDB, 0xFE, 0x26, 0xD7, 0xAD, 0xFB, 0xCD, 0xC3, 0x6F, 0x52, 0x7B, 0xE2, 0xBD,
+	0x13, 0xF6, 0xA6, 0xD0, 0x3F, 0x62, 0x4D, 0x5B, 0xC5, 0xDA, 0x3D, 0xCF, 0xED, 0x31, 0xAB, 0xC9,
+	0x6F, 0xA9, 0xAE, 0x83, 0x1A, 0xE9, 0xCA, 0xBA, 0x85, 0xCC, 0x7F, 0xE8, 0xFE, 0x63, 0xF6, 0x8C,
+	0xE0, 0xE5, 0xBF, 0x1E, 0x3D, 0x28, 0x03, 0xF3, 0x8D, 0x7A, 0x7E, 0x55, 0xF4, 0x07, 0xFC, 0x13,
+	0x37, 0x23, 0xF6, 0xAF, 0xD2, 0x7F, 0xEC, 0x1B, 0x7B, 0xFF, 0x00, 0xA2, 0x4D, 0x7A, 0x77, 0xFC,
+	0x21, 0x5F, 0xF0, 0x48, 0xFC, 0xE7, 0xFE, 0x12, 0x69, 0xB3, 0xFF, 0x00, 0x61, 0x9B, 0xFF, 0x00,
+	0xFE, 0x2A, 0xBD, 0x07, 0xF6, 0x64, 0xF0, 0xEF, 0xFC, 0x13, 0xFB, 0x4C, 0xF8, 0xB9, 0x69, 0x79,
+	0xFB, 0x3E, 0x6B, 0x72, 0x4D, 0xE2, 0x41, 0x67, 0x38, 0xB7, 0x56, 0xBE, 0xB9, 0x94, 0x79, 0x7E,
+	0x59, 0xDF, 0xC4, 0x99, 0x5C, 0xED, 0xF5, 0xFE, 0x74, 0x01, 0xF5, 0x28, 0xE9, 0x45, 0x02, 0x8A,
+	0x00, 0x28, 0xA2, 0x8A, 0x00, 0xFC, 0xF5, 0xFF, 0x00, 0x82, 0xB5, 0x7C, 0xBF, 0x1D, 0x3C, 0x3E,
+	0x73, 0xFF, 0x00, 0x32, 0xD0, 0xF5, 0xFF, 0x00, 0x9F, 0x87, 0xF7, 0xAF, 0x95, 0x41, 0x6C, 0x7D,
+	0xEF, 0xD4, 0xD7, 0xDA, 0x5F, 0xF0, 0x53, 0x1F, 0x82, 0x9F, 0x17, 0x7E, 0x26, 0xFC, 0x64, 0xD1,
+	0x75, 0x5F, 0x87, 0xBF, 0x0D, 0xB5, 0x8D, 0x6A, 0xDE, 0xDF, 0xC3, 0xEB, 0x14, 0xD3, 0x69, 0xD6,
+	0x2F, 0x2A, 0xA3, 0xF9, 0xCE, 0x76, 0x92, 0x07, 0xA1, 0xAF, 0x9B, 0xC7, 0xEC, 0x95, 0xFB, 0x4D,
+	0xE3, 0xFE, 0x48, 0x47, 0x8A, 0x7F, 0xF0, 0x4F, 0x2F, 0xF8, 0x50, 0x07, 0x7D, 0xFF, 0x00, 0x04,
+	0xCC, 0xCF, 0xFC, 0x35, 0x86, 0x96, 0x58, 0x9F, 0xF9, 0x05, 0xDF, 0x73, 0xB8, 0xFF, 0x00, 0xCF,
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+	0xCF, 0xFD, 0xB5, 0xAF, 0x6E, 0xFF, 0x00, 0x82, 0x7F, 0x7C, 0x01, 0xF8, 0xDB, 0xF0, 0xFB, 0xF6,
+	0x92, 0xD3, 0x7C, 0x4D, 0xE3, 0x7F, 0x85, 0xBA, 0xE6, 0x93, 0xA7, 0xC7, 0x61, 0x79, 0x1B, 0xDD,
+	0xDF, 0xE9, 0xEF, 0x1A, 0x06, 0x68, 0x48, 0x51, 0x92, 0x3B, 0x9A, 0xE2, 0x7F, 0x69, 0x7F, 0xD9,
+	0xA3, 0xF6, 0x81, 0xF1, 0x47, 0xED, 0x09, 0xE3, 0x4F, 0x11, 0x78, 0x77, 0xE0, 0xE7, 0x88, 0xAF,
+	0xAC, 0x2F, 0xBC, 0x49, 0x75, 0x35, 0x9D, 0xE5, 0xAE, 0x97, 0x23, 0xC7, 0x34, 0x6D, 0x27, 0x0C,
+	0xAC, 0x06, 0x08, 0x34, 0x01, 0xE0, 0xB9, 0x7E, 0xCF, 0xFF, 0x00, 0x8F, 0x1A, 0xFB, 0x13, 0xFE,
+	0x09, 0xEC, 0x3F, 0xE3, 0x17, 0xFE, 0x32, 0x0D, 0xC7, 0xFE, 0x41, 0x32, 0xF7, 0x3F, 0xF3, 0xE5,
+	0x71, 0xEF, 0x5F, 0x3F, 0xFF, 0x00, 0xC3, 0x26, 0x7E, 0xD3, 0x7F, 0xF4, 0x41, 0xBC, 0x51, 0xFF,
+	0x00, 0x82, 0x79, 0x7F, 0xC2, 0xBE, 0xA4, 0xFD, 0x88, 0xBE, 0x0F, 0x7C, 0x53, 0xF0, 0x2F, 0xEC,
+	0xF5, 0xF1, 0x53, 0xC3, 0xFE, 0x32, 0xF0, 0x0E, 0xA9, 0xA5, 0xDF, 0x6A, 0x9A, 0x5C, 0x8B, 0xA6,
+	0xDA, 0xDE, 0xD9, 0xB4, 0x6F, 0x70, 0xC6, 0xD2, 0x74, 0x01, 0x41, 0xEA, 0x77, 0x30, 0x18, 0xF5,
+	0x34, 0x01, 0xF0, 0xBA, 0x12, 0x51, 0x42, 0x9F, 0xD7, 0xD8, 0x51, 0xF3, 0x1E, 0x37, 0x7F, 0xE3,
+	0xC7, 0x9A, 0xF4, 0x24, 0xFD, 0x92, 0xBF, 0x69, 0xC0, 0xAB, 0xFF, 0x00, 0x16, 0x1F, 0xC5, 0x3F,
+	0xF8, 0x27, 0x97, 0xD0, 0x7B, 0x53, 0x97, 0xF6, 0x4A, 0xFD, 0xA6, 0xF7, 0x2F, 0xFC, 0x58, 0x7F,
+	0x14, 0xFF, 0x00, 0xE0, 0x9E, 0x5F, 0xF0, 0xA0, 0x0F, 0x6C, 0xFD, 0xA6, 0x37, 0x7F, 0xC3, 0xA9,
+	0xFE, 0x1E, 0xED, 0x63, 0xFF, 0x00, 0x21, 0xDB, 0x51, 0xDF, 0x8F, 0xF8, 0xFD, 0xF7, 0xAF, 0x88,
+	0xC7, 0x45, 0xC9, 0x3F, 0x74, 0x73, 0xF8, 0x57, 0xE8, 0x17, 0xED, 0x0B, 0xF0, 0x73, 0xE2, 0xBE,
+	0xB1, 0xFF, 0x00, 0x04, 0xDB, 0xF0, 0x3F, 0xC3, 0x9D, 0x1F, 0xE1, 0xCE, 0xB5, 0x79, 0xAF, 0x58,
+	0xEB, 0x50, 0x3D, 0xE6, 0x8F, 0x6B, 0xA7, 0x49, 0x25, 0xC4, 0x2A, 0xBF, 0x6B, 0xCB, 0x32, 0x28,
+	0x24, 0x01, 0xB9, 0x79, 0xE9, 0xF3, 0x0F, 0x51, 0x5F, 0x1F, 0x2F, 0xEC, 0x99, 0xFB, 0x50, 0xED,
+	0x1F, 0xF1, 0x8F, 0x3E, 0x34, 0xFB, 0xA3, 0xFE, 0x65, 0xBB, 0x9F, 0xFE, 0x22, 0xB9, 0x6A, 0xF3,
+	0x4A, 0xA6, 0x86, 0xB0, 0x68, 0xD1, 0xFD, 0x89, 0x09, 0x1F, 0xB5, 0xBF, 0xC3, 0xF3, 0xB9, 0xBF,
+	0xE4, 0x61, 0x4F, 0xE2, 0xFF, 0x00, 0x61, 0xEA, 0xE7, 0xFC, 0x15, 0x67, 0xFE, 0x4F, 0x93, 0xC5,
+	0xC0, 0x7F, 0xCF, 0xAE, 0x9B, 0xD0, 0x63, 0xFE, 0x5C, 0x61, 0xAE, 0xA3, 0xF6, 0x44, 0xFD, 0x9B,
+	0x3F, 0x68, 0x5F, 0x0B, 0x7E, 0xD3, 0xBE, 0x08, 0xF1, 0x17, 0x89, 0x7E, 0x08, 0x78, 0xAA, 0xC2,
+	0xC2, 0xCF, 0x5C, 0x49, 0x2E, 0xAF, 0x2F, 0x34, 0x1B, 0x88, 0xE2, 0x85, 0x36, 0x3F, 0xCC, 0xCC,
+	0x53, 0x0A, 0x3D, 0xCD, 0x5A, 0xFF, 0x00, 0x82, 0x94, 0xFE, 0xCE, 0x9F, 0x1F, 0x3E, 0x20, 0x7E,
+	0xD8, 0xFE, 0x28, 0xF1, 0x4F, 0x81, 0x7E, 0x0C, 0x78, 0xA3, 0x58, 0xD3, 0x2E, 0x2D, 0x74, 0xF1,
+	0x0E, 0xA1, 0xA6, 0x68, 0x73, 0xCF, 0x0B, 0x95, 0xB3, 0x89, 0x48, 0x0E, 0x8A, 0x41, 0x21, 0x94,
+	0x83, 0xCF, 0x6A, 0xF4, 0x32, 0x9B, 0x46, 0xB3, 0xE6, 0xD0, 0xF3, 0xB3, 0x28, 0xCA, 0x54, 0xD5,
+	0xB5, 0x3E, 0x43, 0x04, 0x29, 0xCE, 0x4F, 0xD7, 0x3D, 0x2B, 0xEF, 0x8F, 0xF8, 0x25, 0x6F, 0x3F,
+	0xB2, 0x17, 0xC6, 0x5D, 0xAD, 0xF2, 0xAB, 0x37, 0x3B, 0x70, 0x4F, 0xFA, 0x13, 0x7A, 0x1A, 0xF9,
+	0x31, 0xBF, 0x64, 0x0F, 0xDA, 0xAF, 0x69, 0x3F, 0xF0, 0xCE, 0x1E, 0x37, 0xE8, 0x77, 0x1F, 0xF8,
+	0x46, 0x6E, 0xB8, 0xE3, 0xFD, 0xCA, 0xFB, 0x5F, 0xFE, 0x09, 0xB3, 0xF0, 0x6B, 0xE2, 0xD7, 0x81,
+	0x3F, 0x65, 0xEF, 0x8A, 0xDE, 0x18, 0xF1, 0xAF, 0xC3, 0x5D, 0x73, 0x48, 0xD4, 0x35, 0x49, 0x18,
+	0x69, 0xB6, 0x5A, 0x96, 0x97, 0x2C, 0x12, 0x5C, 0xFF, 0x00, 0xA1, 0x95, 0xF9, 0x15, 0xD4, 0x16,
+	0xE4, 0xE3, 0x8E, 0xA7, 0x8A, 0xF5, 0xB1, 0xD5, 0x21, 0x2C, 0x3B, 0x49, 0xAE, 0x87, 0x9F, 0x81,
+	0xA7, 0x52, 0x35, 0xD5, 0xD7, 0x73, 0xE3, 0x98, 0x8E, 0x61, 0x5C, 0x1C, 0x7C, 0xA3, 0xBF, 0xB5,
+	0x73, 0x3F, 0x19, 0x3E, 0x34, 0x78, 0x23, 0xE0, 0x0F, 0xC3, 0xEB, 0xDF, 0x8A, 0x3F, 0x10, 0x75,
+	0x0F, 0x26, 0xC3, 0x4F, 0x00, 0xC7, 0x1A, 0x37, 0xEF, 0x2E, 0x65, 0xCF, 0xC9, 0x0C, 0x63, 0xF8,
+	0x99, 0x88, 0xC0, 0xED, 0xD4, 0x9E, 0x01, 0x35, 0xEB, 0xDA, 0xD7, 0xEC, 0xD5, 0xF1, 0xFF, 0x00,
+	0xC2, 0x7E, 0x1D, 0xBA, 0xF1, 0x37, 0x89, 0xBE, 0x0F, 0xF8, 0x8B, 0x4F, 0xD3, 0xF4, 0xDB, 0x36,
+	0xB9, 0xBF, 0xBC, 0xBA, 0xD3, 0x64, 0x8E, 0x3B, 0x78, 0x51, 0x37, 0x3C, 0x8E, 0xC4, 0x7C, 0xAA,
+	0xA0, 0x12, 0x4F, 0x6C, 0x1F, 0x4C, 0x57, 0xE3, 0x07, 0xED, 0xDF, 0xFB, 0x5C, 0x6A, 0x5F, 0xB5,
+	0x17, 0xC4, 0xE6, 0x8F, 0x45, 0xBB, 0x91, 0x3C, 0x23, 0xA1, 0xCC, 0xD0, 0xE8, 0x36, 0x8B, 0xF7,
+	0x65, 0x23, 0x86, 0xBA, 0x71, 0xD3, 0x73, 0x71, 0xB7, 0xFB, 0xA8, 0x14, 0x0E, 0xE6, 0xBC, 0x1A,
+	0x92, 0xE5, 0x5A, 0x1F, 0x45, 0x46, 0x9F, 0xB4, 0x91, 0x4F, 0xF6, 0xEA, 0xFD, 0xBA, 0x7E, 0x38,
+	0x7F, 0xC1, 0x40, 0xFE, 0x38, 0xDC, 0xFC, 0x69, 0xF8, 0xD3, 0xAB, 0x1F, 0xDD, 0xDB, 0xAD, 0x9F,
+	0x87, 0x74, 0x1B, 0x79, 0x19, 0x6D, 0x74, 0x5D, 0x3D, 0x3E, 0x54, 0xB6, 0x89, 0x4F, 0xB2, 0xE5,
+	0xDB, 0x00, 0xBB, 0x96, 0x62, 0x70, 0x70, 0x3C, 0x60, 0xB0, 0x27, 0x23, 0xD4, 0xFB, 0x01, 0xEC,
+	0x07, 0x61, 0x8C, 0x71, 0xDA, 0xBE, 0x8C, 0xFD, 0x9F, 0x7F, 0xE0, 0x92, 0x9F, 0xF0, 0x50, 0xDF,
+	0xDA, 0x9B, 0xE1, 0x75, 0x9F, 0xC6, 0xAF, 0x80, 0xDF, 0xB3, 0x56, 0xA9, 0xE2, 0x2F, 0x0C, 0xEA,
+	0x53, 0x4A, 0x96, 0x7A, 0xB5, 0xAE, 0xA5, 0x66, 0x89, 0x23, 0xC6, 0xE5, 0x24, 0x5D, 0xB2, 0xCC,
+	0xAC, 0x30, 0xCA, 0x7A, 0x81, 0x9E, 0xD9, 0xAE, 0xD4, 0xFF, 0x00, 0xC1, 0x03, 0xFF, 0x00, 0xE0,
+	0xAD, 0xAA, 0x32, 0x7F, 0x63, 0x4D, 0x73, 0xFF, 0x00, 0x06, 0xDA, 0x77, 0xFF, 0x00, 0x24, 0xD7,
+	0x3B, 0x52, 0x96, 0xB6, 0x3B, 0xA3, 0x2A, 0x71, 0x8D, 0xAE, 0x7C, 0x7D, 0x45, 0x7D, 0x45, 0xF1,
+	0x53, 0xFE, 0x08, 0xC3, 0xFF, 0x00, 0x05, 0x32, 0xF8, 0x27, 0xF0, 0xDF, 0x5A, 0xF8, 0xB9, 0xF1,
+	0x43, 0xF6, 0x57, 0xD5, 0xF4, 0x9F, 0x0E, 0xF8, 0x77, 0x4E, 0x92, 0xFF, 0x00, 0x5A, 0xD4, 0xA6,
+	0xD4, 0xEC, 0x5D, 0x6D, 0xAD, 0xE3, 0x19, 0x77, 0x2A, 0x93, 0xB3, 0x10, 0x07, 0x60, 0x09, 0xF4,
+	0x15, 0xF2, 0xEE, 0x08, 0xEA, 0xB8, 0xFE, 0xB4, 0x9A, 0x6B, 0x72, 0xE3, 0x28, 0xCB, 0x60, 0xAF,
+	0xDB, 0xAF, 0xF8, 0x33, 0x73, 0xFE, 0x43, 0xDF, 0x1D, 0x3F, 0xEB, 0xCF, 0x44, 0xFF, 0x00, 0xD0,
+	0xEE, 0xEB, 0xF1, 0x16, 0xBF, 0x6D, 0xBF, 0xE0, 0xCE, 0x4B, 0xBB, 0x6B, 0x4D, 0x7B, 0xE3, 0xA3,
+	0xDC, 0xDC, 0x24, 0x63, 0xEC, 0x7A, 0x27, 0x2E, 0xD8, 0xFE, 0x3B, 0xAA, 0xAA, 0x7F, 0x11, 0x86,
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+	0x96, 0xB2, 0x4D, 0x2D, 0x57, 0x76, 0x8F, 0xD1, 0x78, 0xDB, 0x1D, 0x82, 0xC4, 0x64, 0x72, 0x8D,
+	0x2A, 0x91, 0x93, 0xE6, 0x5A, 0x26, 0x9B, 0xDF, 0xC8, 0xFC, 0xE5, 0x8C, 0xB0, 0x8D, 0x57, 0x77,
+	0x6E, 0x9F, 0x89, 0xA5, 0x05, 0xC1, 0xC8, 0x3D, 0xFD, 0x6B, 0xD0, 0x53, 0xF6, 0x4B, 0xFD, 0xA6,
+	0xCA, 0x82, 0x3E, 0x04, 0x78, 0xA7, 0xA7, 0xFD, 0x01, 0xE5, 0xFF, 0x00, 0x0A, 0x51, 0xFB, 0x25,
+	0xFE, 0xD3, 0x99, 0x1F, 0xF1, 0x62, 0x3C, 0x51, 0xF7, 0xBB, 0xE8, 0xF2, 0xFF, 0x00, 0x85, 0x7F,
+	0xA0, 0x9F, 0x64, 0xFC, 0x4C, 0xF6, 0x0F, 0x1E, 0x2F, 0xFC, 0x6A, 0xCB, 0xC1, 0xA4, 0x9F, 0xF9,
+	0x9B, 0x24, 0xDB, 0xD7, 0xFE, 0x7B, 0xDD, 0x7B, 0xD7, 0xCB, 0x99, 0x6C, 0xF0, 0xDE, 0x9D, 0xFD,
+	0xAB, 0xEC, 0xCF, 0x19, 0x7C, 0x13, 0xF8, 0xBD, 0x7B, 0xFF, 0x00, 0x04, 0xE6, 0xF0, 0xAF, 0xC3,
+	0x7B, 0x4F, 0x86, 0xDA, 0xCC, 0x9A, 0xFD, 0xAF, 0x89, 0xA4, 0x9A, 0xE3, 0x47, 0x5B, 0x07, 0xFB,
+	0x44, 0x69, 0xE7, 0x5C, 0x1D, 0xCC, 0x98, 0xC8, 0x18, 0x65, 0x3F, 0x88, 0xAF, 0x9D, 0x7F, 0xE1,
+	0x92, 0xFF, 0x00, 0x69, 0xBC, 0xFF, 0x00, 0xC9, 0x08, 0xF1, 0x4F, 0xFE, 0x09, 0xE5, 0xF4, 0xFA,
+	0x50, 0x07, 0x23, 0xE0, 0x72, 0xDF, 0xF0, 0x9A, 0x69, 0x19, 0x6F, 0xF9, 0x8A, 0x5B, 0xFF, 0x00,
+	0x11, 0xE3, 0xF7, 0x8B, 0x5F, 0x47, 0x7F, 0xC1, 0x54, 0x86, 0x3E, 0x2E, 0x78, 0x54, 0x96, 0xF9,
+	0xBF, 0xE1, 0x10, 0x8F, 0xD7, 0xFE, 0x7B, 0x3F, 0xBD, 0x79, 0x8F, 0x83, 0xFF, 0x00, 0x65, 0x3F,
+	0xDA, 0x52, 0xD3, 0xC5, 0x7A, 0x6D, 0xE5, 0xDF, 0xC0, 0xEF, 0x13, 0x43, 0x14, 0x37, 0xF0, 0xBC,
+	0xB2, 0x4D, 0xA4, 0xCA, 0xAA, 0xAA, 0x1C, 0x12, 0x73, 0x8F, 0x4A, 0xF7, 0x6F, 0xF8, 0x28, 0xEF,
+	0xC1, 0x2F, 0x8B, 0xDF, 0x12, 0xFE, 0x27, 0xF8, 0x6F, 0x52, 0xF0, 0x07, 0xC3, 0x6D, 0x6B, 0x58,
+	0xB7, 0xB7, 0xF0, 0xBC, 0x70, 0xDC, 0x4B, 0xA7, 0xE9, 0xEF, 0x22, 0xA3, 0xF9, 0xAC, 0xDB, 0x5B,
+	0x68, 0xE0, 0xE0, 0x8A, 0x00, 0xF8, 0xD5, 0x4B, 0xF1, 0xF3, 0x7A, 0x7F, 0x15, 0x7D, 0x01, 0xFF,
+	0x00, 0x04, 0xCB, 0x27, 0xFE, 0x1A, 0xC3, 0x49, 0x04, 0xFF, 0x00, 0xCC, 0x2E, 0xFB, 0xF8, 0x8F,
+	0xFC, 0xF1, 0x35, 0xC0, 0x8F, 0xD9, 0x2B, 0xF6, 0x9B, 0x23, 0x03, 0xE0, 0x37, 0x8A, 0x3B, 0x7F,
+	0xCC, 0x1E, 0x5F, 0xF0, 0xAF, 0x6D, 0xFF, 0x00, 0x82, 0x7E, 0x7C, 0x01, 0xF8, 0xD9, 0xF0, 0xFF,
+	0x00, 0xF6, 0x93, 0xD3, 0x7C, 0x4F, 0xE3, 0x7F, 0x85, 0x9A, 0xE6, 0x93, 0xA7, 0xC7, 0x63, 0x76,
+	0x8F, 0x77, 0xA8, 0x69, 0xEF, 0x12, 0x2B, 0x34, 0x4C, 0x14, 0x12, 0x47, 0xE1, 0xF5, 0x34, 0x01,
+	0xFA, 0x0A, 0x28, 0xA0, 0x74, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x3E, 0x47, 0xFD, 0xBD, 0x3F,
+	0x6B, 0xEF, 0x8C, 0x1F, 0xB3, 0xBF, 0xC5, 0x3D, 0x2F, 0xC2, 0xDF, 0x0E, 0xEE, 0xB4, 0xF8, 0xED,
+	0x6F, 0xB4, 0x55, 0xB9, 0x9F, 0xED, 0x9A, 0x7A, 0xCA, 0xDE, 0x67, 0x9C, 0xCB, 0x90, 0x73, 0xE8,
+	0x3D, 0x2B, 0xC3, 0x47, 0xFC, 0x15, 0x0B, 0xF6, 0xA3, 0xC7, 0x1A, 0x96, 0x8A, 0x3D, 0xBF, 0xB2,
+	0x57, 0x8F, 0xD6, 0xBA, 0x0F, 0xF8, 0x2B, 0x69, 0xC7, 0xC7, 0x4F, 0x0F, 0xB1, 0xE3, 0xFE, 0x29,
+	0x91, 0xC9, 0xFF, 0x00, 0xAE, 0xEF, 0x5F, 0x2A, 0xD0, 0x07, 0xDC, 0x5F, 0xB1, 0x97, 0xED, 0xC1,
+	0xF1, 0xC7, 0xE3, 0xA7, 0xC7, 0x5B, 0x1F, 0x87, 0xDE, 0x3B, 0xBB, 0xD2, 0xDF, 0x4E, 0x9E, 0xCE,
+	0xE2, 0x59, 0x16, 0xDB, 0x4F, 0x11, 0xB9, 0x64, 0x8C, 0xB2, 0xFC, 0xC0, 0xF1, 0x82, 0x33, 0x5C,
+	0x9F, 0xC7, 0x7F, 0xF8, 0x28, 0x6F, 0xED, 0x0F, 0xF0, 0xEB, 0xE3, 0x47, 0x8A, 0xBC, 0x07, 0xE1,
+	0xDB, 0xFD, 0x25, 0x6C, 0x34, 0x7D, 0x7A, 0xE6, 0xD6, 0xCD, 0x66, 0xD3, 0x15, 0x9F, 0xCB, 0x59,
+	0x30, 0x32, 0xD9, 0xE4, 0xFE, 0x55, 0xC4, 0xFF, 0x00, 0xC1, 0x33, 0x3E, 0x6F, 0xDA, 0xBF, 0x4A,
+	0xDA, 0x7F, 0xE6, 0x1B, 0x7D, 0xFF, 0x00, 0xA2, 0x4D, 0x70, 0x3F, 0xB5, 0xA9, 0xFF, 0x00, 0x8C,
+	0x9E, 0xF1, 0xF2, 0x9E, 0x3F, 0xE2, 0xAA, 0xBC, 0xEB, 0xFF, 0x00, 0x5D, 0x33, 0x40, 0x1E, 0x93,
+	0xFF, 0x00, 0x0F, 0x41, 0xFD, 0xA8, 0xFF, 0x00, 0x8B, 0x52, 0xD1, 0x7F, 0xF0, 0x52, 0xBF, 0xE3,
+	0x5F, 0x41, 0xFE, 0xCA, 0x1F, 0xB5, 0x5F, 0xC5, 0x6F, 0x8C, 0xFF, 0x00, 0x04, 0xFE, 0x22, 0x78,
+	0xEB, 0xC6, 0xB3, 0xD8, 0x3D, 0xF7, 0x86, 0xF4, 0xF9, 0x24, 0xD3, 0x7E, 0xCB, 0x66, 0x23, 0x55,
+	0x61, 0x6D, 0x2C, 0x9F, 0x30, 0x07, 0xE6, 0xCB, 0x22, 0x9C, 0x57, 0xE7, 0x8D, 0x7D, 0x89, 0xFF,
+	0x00, 0x04, 0xF4, 0x05, 0xBF, 0x66, 0x2F, 0x8C, 0x9B, 0x46, 0x73, 0xA4, 0xC9, 0x8C, 0x77, 0xFF,
+	0x00, 0x42, 0xB8, 0xA0, 0x0E, 0x15, 0x7F, 0xE0, 0xA8, 0x3F, 0xB5, 0x13, 0x2A, 0xBF, 0xF6, 0x96,
+	0x89, 0xB8, 0x8E, 0x71, 0xA4, 0x2F, 0xA0, 0xF7, 0xFE, 0xBD, 0xA9, 0xDF, 0xF0, 0xF4, 0x2F, 0xDA,
+	0x8F, 0xBE, 0xA1, 0xA2, 0xB7, 0xB7, 0xF6, 0x4A, 0xFF, 0x00, 0x8D, 0x7C, 0xE3, 0x19, 0x05, 0x17,
+	0x1F, 0xDD, 0x1F, 0xC8, 0x53, 0x81, 0x00, 0xF3, 0x40, 0x1F, 0x7E, 0xFC, 0x6F, 0xFD, 0xAD, 0x7E,
+	0x32, 0x78, 0x2F, 0xF6, 0x13, 0xF0, 0x9F, 0xC7, 0xEF, 0x0D, 0xEA, 0x56, 0x10, 0xF8, 0x8B, 0x58,
+	0xD5, 0xA1, 0x86, 0xF2, 0x66, 0xD3, 0xD5, 0xA2, 0x65, 0x61, 0x73, 0x9C, 0x46, 0xD9, 0x00, 0xFE,
+	0xE9, 0x39, 0xEB, 0xC1, 0xF5, 0xAF, 0x99, 0x3F, 0xE1, 0xEA, 0xDF, 0xB6, 0x1E, 0xEF, 0x97, 0xC5,
+	0x9A, 0x3F, 0xDE, 0x3F, 0xF3, 0x01, 0x87, 0xA7, 0xE5, 0x5E, 0xA1, 0xFB, 0x4B, 0x83, 0xFF, 0x00,
+	0x0E, 0xA7, 0xF8, 0x7A, 0x08, 0xFF, 0x00, 0x98, 0xED, 0xB7, 0xF2, 0xBD, 0xAF, 0x88, 0x42, 0xB2,
+	0xF3, 0x8E, 0xD5, 0xCB, 0x5A, 0x52, 0x8C, 0xF4, 0x34, 0x85, 0x9A, 0x3E, 0xC8, 0xFD, 0x9A, 0x3F,
+	0xE0, 0xA3, 0x7F, 0xB5, 0x0F, 0xC5, 0x1F, 0x8F, 0xBE, 0x13, 0xF8, 0x79, 0xE2, 0xFF, 0x00, 0x11,
+	0xE9, 0x73, 0x69, 0x7A, 0xC6, 0xAC, 0xB6, 0xF7, 0x91, 0xC3, 0xA2, 0xC4, 0x8C, 0x50, 0xA3, 0x1E,
+	0x18, 0x0E, 0x0E, 0x45, 0x7A, 0x17, 0xED, 0x91, 0xFB, 0x72, 0x7C, 0x74, 0xF8, 0x1B, 0xF1, 0xF3,
+	0x52, 0xF8, 0x75, 0xE0, 0x8B, 0xBD, 0x2D, 0x34, 0xDB, 0x5B, 0x3B, 0x59, 0x61, 0x5B, 0x8D, 0x3C,
+	0x49, 0x20, 0x69, 0x23, 0x0E, 0xF9, 0x63, 0xEE, 0x6B, 0xE4, 0x7F, 0xD8, 0x90, 0xEE, 0xFD, 0xAD,
+	0xBE, 0x1F, 0x9F, 0xFA, 0x98, 0x13, 0xFF, 0x00, 0x45, 0xBD, 0x7A, 0xAF, 0xFC, 0x14, 0xB0, 0xE7,
+	0xF6, 0xB9, 0xD6, 0xB1, 0xFF, 0x00, 0x40, 0xCB, 0x0F, 0xFD, 0x27, 0x5A, 0xD3, 0x0F, 0xCD, 0x25,
+	0xA9, 0x33, 0xB2, 0x34, 0x0F, 0xFC, 0x15, 0x07, 0xF6, 0xA2, 0x3C, 0x0D, 0x43, 0x45, 0xEA, 0x3F,
+	0xE6, 0x12, 0xBE, 0xB5, 0xF4, 0x4F, 0xEC, 0xAB, 0xFB, 0x52, 0x7C, 0x52, 0xF8, 0xC3, 0xFB, 0x3F,
+	0x78, 0xE3, 0xE2, 0x5F, 0x8C, 0xEE, 0x2C, 0x5F, 0x50, 0xF0, 0xFC, 0x92, 0x8D, 0x38, 0xDB, 0xD9,
+	0xAC, 0x6A, 0x36, 0xDB, 0x89, 0x01, 0x61, 0x93, 0x93, 0xB8, 0xFB, 0x57, 0xE7, 0x58, 0x04, 0x9E,
+	0x07, 0x71, 0xFC, 0xEB, 0xE8, 0xEF, 0x83, 0xFF, 0x00, 0xB4, 0x57, 0x81, 0x7F, 0x65, 0x5F, 0xF8,
+	0x26, 0x5F, 0xC7, 0x0F, 0x8E, 0x1F, 0x10, 0x2E, 0x96, 0x3B, 0x1D, 0x1D, 0x65, 0x58, 0x21, 0x6E,
+	0xB7, 0x57, 0x52, 0xDA, 0xA4, 0x50, 0x5B, 0xAE, 0x7A, 0xB3, 0xCA, 0xE8, 0x98, 0xEB, 0xF3, 0x63,
+	0xBD, 0x6D, 0xB6, 0xA4, 0xFB, 0xDB, 0x23, 0xF3, 0xE7, 0xFE, 0x0B, 0x75, 0xFF, 0x00, 0x05, 0x9F,
+	0xFD, 0xA2, 0x3E, 0x25, 0x7C, 0x33, 0xB8, 0xFD, 0x89, 0x74, 0xFF, 0x00, 0x15, 0x58, 0xC3, 0x0E,
+	0xBD, 0x6F, 0x1C, 0xDE, 0x38, 0x9F, 0x49, 0xB2, 0x58, 0x64, 0x6B, 0x53, 0x86, 0x4B, 0x2D, 0xFC,
+	0x90, 0x25, 0x18, 0x69, 0x00, 0xC6, 0xE8, 0xF6, 0x2E, 0x40, 0x76, 0xAF, 0xC9, 0xBC, 0x16, 0x6C,
+	0x93, 0xCF, 0x3F, 0x33, 0x65, 0xBF, 0x99, 0xCF, 0xE3, 0xDF, 0xB8, 0xEE, 0x75, 0x3C, 0x6D, 0xE3,
+	0x5F, 0x10, 0x7C, 0x46, 0xF1, 0x86, 0xA5, 0xE3, 0xCF, 0x15, 0xDF, 0xB5, 0xCE, 0xA5, 0xAB, 0x5D,
+	0xB5, 0xCD, 0xE4, 0xCC, 0xD9, 0xCB, 0xB7, 0xCD, 0xC7, 0xB7, 0xCD, 0x80, 0x3B, 0x00, 0x3E, 0x95,
+	0x96, 0x08, 0xAE, 0x57, 0x2E, 0x69, 0x1E, 0xA5, 0x3A, 0x7E, 0xCE, 0x36, 0x3F, 0xA6, 0x4F, 0xF8,
+	0x37, 0x30, 0x15, 0xFF, 0x00, 0x82, 0x4B, 0xFC, 0x3F, 0x56, 0x4F, 0xF9, 0x89, 0x6A, 0xFD, 0x94,
+	0xFF, 0x00, 0xCB, 0xEC, 0x9D, 0xF0, 0x0D, 0x7D, 0xC9, 0x8F, 0x71, 0xFF, 0x00, 0x7C, 0x0A, 0xF8,
+	0x77, 0xFE, 0x0D, 0xCE, 0xE7, 0xFE, 0x09, 0x35, 0xF0, 0xFC, 0x8F, 0xFA, 0x09, 0x6A, 0xC7, 0xEB,
+	0xFE, 0x9B, 0x25, 0x7D, 0xC5, 0x5D, 0x70, 0xF8, 0x51, 0xE7, 0xCE, 0xFE, 0xD1, 0x9F, 0x3C, 0xFF,
+	0x00, 0xC1, 0x5B, 0x5B, 0x3F, 0xF0, 0x4C, 0x4F, 0x8F, 0x00, 0x1D, 0xBF, 0xF1, 0x6C, 0xF5, 0x2E,
+	0x76, 0xFF, 0x00, 0xD3, 0x3F, 0xAD, 0x7F, 0x27, 0xA7, 0x1B, 0x8B, 0x63, 0xAF, 0x7C, 0xE7, 0xB9,
+	0xAF, 0xEB, 0x0B, 0xFE, 0x0A, 0xD6, 0x18, 0xFF, 0x00, 0xC1, 0x31, 0x7E, 0x3C, 0x00, 0x3F, 0xE6,
+	0x99, 0xEA, 0x5F, 0xFA, 0x2E, 0xBF, 0x93, 0xDC, 0x63, 0xBF, 0xB7, 0xEB, 0x59, 0x57, 0xF8, 0x8E,
+	0xCC, 0x2F, 0xC2, 0xFD, 0x41, 0x89, 0xC7, 0x1E, 0x87, 0xF9, 0x57, 0xEC, 0xE7, 0xFC, 0x1A, 0x28,
+	0x7F, 0xE2, 0x71, 0xF1, 0xC1, 0x80, 0xE7, 0xEC, 0x3A, 0x2F, 0xFE, 0x87, 0x73, 0x5F, 0x8C, 0x63,
+	0x93, 0xB4, 0x7D, 0x3F, 0x4A, 0xFD, 0x9C, 0xFF, 0x00, 0x83, 0x44, 0xC1, 0x3A, 0xAF, 0xC7, 0x22,
+	0x01, 0xF9, 0x6C, 0xF4, 0x50, 0x7D, 0xBE, 0x7B, 0x8A, 0xCE, 0x8F, 0xF1, 0x03, 0x11, 0xFC, 0x33,
+	0xF6, 0xB7, 0x79, 0x27, 0x9F, 0x53, 0xFE, 0x7A, 0x52, 0x12, 0x48, 0x2A, 0x0E, 0x32, 0xA7, 0xAF,
+	0x23, 0xA7, 0xA6, 0x30, 0x7E, 0x87, 0x8F, 0xCA, 0x8C, 0x10, 0x72, 0x47, 0x53, 0x41, 0xF4, 0xF5,
+	0xE0, 0x7B, 0xD7, 0x61, 0xE7, 0x9F, 0xC9, 0xFF, 0x00, 0xFC, 0x15, 0xD7, 0x07, 0xFE, 0x0A, 0x8B,
+	0xF1, 0xFB, 0x8E, 0x9F, 0x16, 0x35, 0xAF, 0xC3, 0xFD, 0x25, 0x87, 0xBF, 0xA1, 0xE4, 0x60, 0xE4,
+	0xE6, 0xBE, 0x77, 0x19, 0xEB, 0xB8, 0xFF, 0x00, 0x87, 0xF9, 0xE3, 0x9E, 0xFD, 0xEB, 0xE8, 0x8F,
+	0xF8, 0x2B, 0xA7, 0x1F, 0xF0, 0x54, 0x7F, 0xDA, 0x00, 0xE0, 0xE3, 0xFE, 0x16, 0xC6, 0xB3, 0xCE,
+	0x3F, 0xE9, 0xE9, 0xEB, 0xE7, 0x7D, 0xC3, 0xD6, 0xB8, 0x64, 0xF9, 0x64, 0x7A, 0xD4, 0xFE, 0x14,
+	0x7D, 0x45, 0xFF, 0x00, 0x04, 0x52, 0x0C, 0xDF, 0xF0, 0x55, 0x6F, 0x81, 0xEA, 0x7B, 0xF8, 0xD1,
+	0x7F, 0xF4, 0x44, 0xD5, 0xFD, 0x53, 0x02, 0x41, 0xE0, 0xF5, 0xE7, 0xDF, 0xF9, 0x7F, 0x20, 0x2B,
+	0xF9, 0x59, 0xFF, 0x00, 0x82, 0x28, 0xBA, 0x8F, 0xF8, 0x2A, 0xC7, 0xC0, 0xFC, 0x9E, 0xBE, 0x34,
+	0x40, 0x3D, 0xFF, 0x00, 0x71, 0x2D, 0x7F, 0x54, 0xC3, 0x81, 0xCF, 0x1C, 0x63, 0x9F, 0x6E, 0x0D,
+	0x74, 0x50, 0xF8, 0x4E, 0x3C, 0x57, 0xC4, 0x19, 0x24, 0x60, 0xFE, 0x5B, 0x7F, 0xFD, 0x5F, 0xCE,
+	0xBF, 0x0B, 0x7F, 0xE0, 0xEE, 0x8F, 0xF9, 0x2F, 0x9F, 0x04, 0xD8, 0x81, 0xFF, 0x00, 0x22, 0x5E,
+	0xAF, 0xBB, 0x8E, 0xA7, 0xED, 0x90, 0x73, 0xDB, 0x3F, 0x96, 0x45, 0x7E, 0xE9, 0x06, 0xC1, 0xC6,
+	0x3B, 0x57, 0xE1, 0x6F, 0xFC, 0x1D, 0xD1, 0xC7, 0xC7, 0xCF, 0x82, 0x29, 0x9F, 0x9B, 0xFE, 0x10,
+	0xAD, 0x5F, 0x8F, 0xFB, 0x7D, 0x86, 0x9D, 0x6B, 0xA8, 0x19, 0xE1, 0xFF, 0x00, 0x8C, 0x7E, 0x45,
+	0x7F, 0xC0, 0xC7, 0xFD, 0xF3, 0x51, 0x5F, 0x1F, 0xF4, 0x39, 0x7F, 0xEB, 0x9B, 0x7C, 0xD8, 0xED,
+	0xB4, 0xE7, 0xF3, 0x1C, 0x7E, 0x35, 0x25, 0x47, 0x7A, 0xAC, 0x6C, 0xE5, 0xC2, 0x9F, 0xF5, 0x6C,
+	0x3A, 0x7A, 0x8C, 0x57, 0x21, 0xE8, 0x9F, 0xD8, 0x57, 0xEC, 0x92, 0xCD, 0xFF, 0x00, 0x0C, 0xAB,
+	0xF0, 0xD4, 0x2E, 0x7F, 0xE4, 0x42, 0xD2, 0x3B, 0xFF, 0x00, 0xD3, 0x94, 0x5C, 0x77, 0xC8, 0x1D,
+	0xBA, 0x63, 0x9E, 0x39, 0xAF, 0x42, 0x05, 0xBA, 0x1F, 0x6F, 0xE7, 0x5E, 0x77, 0xFB, 0x23, 0xFF,
+	0x00, 0xC9, 0xAB, 0x7C, 0x34, 0xFF, 0x00, 0xB1, 0x07, 0x48, 0xFF, 0x00, 0xD2, 0x38, 0xAB, 0xD1,
+	0x0F, 0xA1, 0x3E, 0xF5, 0xDF, 0x1B, 0xD9, 0x1E, 0x54, 0xBE, 0x23, 0xF2, 0xC7, 0xFE, 0x0E, 0xD1,
+	0xE7, 0xF6, 0x19, 0xF8, 0x6F, 0x9F, 0xFA, 0x2B, 0xF0, 0x8F, 0xFC, 0xA4, 0xEA, 0x35, 0xF8, 0x0E,
+	0x7E, 0xE2, 0xFF, 0x00, 0x9E, 0xC2, 0xBF, 0x7E, 0x3F, 0xE0, 0xED, 0x0F, 0xF9, 0x31, 0xAF, 0x86,
+	0xE3, 0x3D, 0x7E, 0x30, 0x43, 0x8F, 0xC7, 0x48, 0xD4, 0x6B, 0xF0, 0x1B, 0x93, 0x18, 0x18, 0x3E,
+	0xFC, 0x74, 0xFF, 0x00, 0x38, 0xAE, 0x6A, 0xDF, 0x11, 0xE8, 0x61, 0x7F, 0x82, 0x21, 0xF6, 0x0B,
+	0xED, 0xB8, 0x71, 0x5F, 0xAD, 0xFF, 0x00, 0xB0, 0xD7, 0xEC, 0xB7, 0xFB, 0x24, 0x5F, 0x7E, 0xC0,
+	0x5F, 0x0A, 0xFE, 0x23, 0xF8, 0xD7, 0xF6, 0x55, 0xF0, 0x3F, 0x89, 0x7C, 0x41, 0xE2, 0x48, 0x35,
+	0x59, 0x75, 0x6D, 0x6B, 0xC4, 0x1A, 0x6B, 0xCF, 0x71, 0x3F, 0x95, 0x7C, 0xF1, 0x46, 0xA4, 0x87,
+	0x50, 0x36, 0xA0, 0xC7, 0x03, 0x06, 0xBF, 0x24, 0x30, 0x7A, 0xED, 0x6F, 0x53, 0xF2, 0x9E, 0x2B,
+	0xF6, 0x93, 0xF6, 0x1F, 0x23, 0xFE, 0x1D, 0x9D, 0xF0, 0x34, 0x82, 0x3F, 0xE3, 0xCF, 0x5C, 0x1D,
+	0x7A, 0xFF, 0x00, 0xC4, 0xCE, 0x5A, 0x9A, 0x68, 0x9C, 0x44, 0xA5, 0x1A, 0x6A, 0xC6, 0x81, 0xFD,
+	0x9A, 0xBF, 0x62, 0xA3, 0xFF, 0x00, 0x36, 0x3B, 0xF0, 0xB3, 0xAF, 0xFD, 0x00, 0x64, 0xFF, 0x00,
+	0xE3, 0xB4, 0xFF, 0x00, 0x88, 0xBF, 0xB1, 0x6F, 0xEC, 0x45, 0xE2, 0x7F, 0xD8, 0xB3, 0xE3, 0xF7,
+	0x8D, 0xAC, 0xBF, 0x63, 0xBF, 0x87, 0xFA, 0x46, 0xB7, 0xE0, 0xDF, 0x86, 0xD3, 0x6A, 0x9E, 0x1D,
+	0xD5, 0x34, 0x7D, 0x2E, 0x48, 0x66, 0xB5, 0xB8, 0xF3, 0x36, 0x87, 0x0D, 0xE6, 0x1E, 0x71, 0x9E,
+	0xDD, 0xEB, 0xA5, 0x1C, 0x9E, 0x0D, 0x74, 0x5A, 0xCE, 0x47, 0xEC, 0x0F, 0xFB, 0x53, 0x13, 0xFF,
+	0x00, 0x44, 0x76, 0x4F, 0xFD, 0x1D, 0x5B, 0x4A, 0x31, 0xE5, 0x38, 0xE3, 0x2A, 0x9C, 0xCB, 0x53,
+	0xF0, 0x00, 0xEE, 0x23, 0x86, 0x39, 0xF5, 0xCE, 0x33, 0xF5, 0xC7, 0x5F, 0xF0, 0xAF, 0xD0, 0xBF,
+	0xF8, 0x21, 0xE7, 0xFC, 0x15, 0xB3, 0xE3, 0x77, 0xEC, 0x69, 0xE2, 0x1B, 0xAF, 0xD9, 0x76, 0xC7,
+	0xC5, 0x16, 0xEB, 0xE1, 0x2F, 0x17, 0x5F, 0x9B, 0x9D, 0x2E, 0xDF, 0x54, 0xB7, 0x13, 0x25, 0x86,
+	0xA4, 0x54, 0x02, 0x23, 0xC9, 0xC2, 0x09, 0x82, 0x85, 0x20, 0x60, 0x16, 0x55, 0x3D, 0x72, 0x4F,
+	0xE7, 0xA8, 0xE4, 0x64, 0x7C, 0xDC, 0x63, 0x8A, 0x92, 0xDA, 0xE6, 0xE6, 0xC6, 0xE2, 0x3B, 0xEB,
+	0x39, 0xE4, 0x86, 0x68, 0x64, 0x57, 0x86, 0x68, 0x8E, 0xD7, 0x8E, 0x40, 0x7E, 0x56, 0x53, 0xD8,
+	0x86, 0xC1, 0x07, 0xA8, 0xED, 0xCD, 0x72, 0xC6, 0x5C, 0xAC, 0xF4, 0xAA, 0x41, 0x4A, 0x2D, 0x1F,
+	0xD7, 0x67, 0xC5, 0x6F, 0xDA, 0x9B, 0xE2, 0xAF, 0x84, 0x7F, 0x62, 0x2F, 0x0B, 0xFC, 0x7A, 0xD2,
+	0xE6, 0xB0, 0x1E, 0x22, 0xD5, 0x0D, 0x9F, 0xDB, 0x19, 0xEC, 0xC3, 0xC5, 0x99, 0x09, 0x0D, 0x84,
+	0x3F, 0x77, 0xEE, 0xFE, 0x95, 0xF3, 0xB8, 0xFF, 0x00, 0x82, 0xA1, 0x7E, 0xD4, 0x3F, 0xF4, 0x11,
+	0xD1, 0x7D, 0x7F, 0xE4, 0x12, 0xB5, 0xC0, 0xFE, 0xCC, 0x5F, 0xB6, 0x87, 0x86, 0xBF, 0x6D, 0x4F,
+	0xF8, 0x22, 0x47, 0x83, 0xF5, 0xBB, 0x5B, 0xC8, 0xFF, 0x00, 0xE1, 0x24, 0xF0, 0x7E, 0xB9, 0x67,
+	0xE1, 0xEF, 0x18, 0xD9, 0xEE, 0x1B, 0xA2, 0xBC, 0xB7, 0xCB, 0x09, 0x80, 0xFE, 0xE4, 0xD1, 0x32,
+	0x4A, 0x0F, 0x4C, 0x99, 0x10, 0x12, 0x63, 0x6C, 0x79, 0x8A, 0x90, 0x38, 0xCF, 0xF0, 0xD7, 0x62,
+	0x68, 0xF2, 0xE4, 0xB9, 0x64, 0xD5, 0x8F, 0xB1, 0x3F, 0x66, 0xDF, 0xF8, 0x28, 0x0F, 0xED, 0x03,
+	0xF1, 0x4F, 0xE3, 0x8F, 0x86, 0xFC, 0x01, 0xE2, 0x9B, 0xCD, 0x25, 0xB4, 0xFD, 0x4F, 0x50, 0x10,
+	0xDD, 0x08, 0x74, 0xD0, 0x8E, 0x57, 0x69, 0x3C, 0x37, 0x63, 0x5E, 0x91, 0xF1, 0xFF, 0x00, 0xF6,
+	0x96, 0xF8, 0xAD, 0xE0, 0x3F, 0x8A, 0xDA, 0x97, 0x85, 0xBC, 0x39, 0xAA, 0xDA, 0xC5, 0x69, 0x6D,
+	0xE5, 0x88, 0x63, 0x92, 0xCD, 0x19, 0xB9, 0x45, 0x6E, 0x49, 0xCE, 0x79, 0x26, 0xBE, 0x47, 0xFD,
+	0x89, 0x3F, 0xE4, 0xEA, 0xBC, 0x17, 0x9F, 0xFA, 0x0B, 0xAF, 0xFE, 0x82, 0xD5, 0xEF, 0x1F, 0xB5,
+	0x9E, 0x0F, 0xC7, 0x9D, 0x6B, 0x1F, 0xDE, 0x87, 0xFF, 0x00, 0x45, 0x2D, 0x7E, 0x03, 0xF4, 0x86,
+	0xCE, 0xB3, 0x4C, 0x8F, 0x84, 0x69, 0xD7, 0xC0, 0x55, 0x74, 0xE7, 0xCE, 0x95, 0xD3, 0x69, 0xD9,
+	0xA3, 0xEC, 0x38, 0x1B, 0x07, 0x85, 0xCC, 0x33, 0x67, 0x0A, 0xD0, 0x52, 0x8F, 0x2B, 0x76, 0x6A,
+	0xEB, 0xA1, 0x70, 0xFE, 0xD9, 0x1F, 0x1C, 0xFE, 0xE9, 0xD7, 0xAC, 0x7F, 0x1D, 0x3E, 0x3F, 0xF0,
+	0xAF, 0x5C, 0xF8, 0x33, 0xF1, 0xCF, 0xE2, 0x17, 0x8B, 0x7E, 0x05, 0xF8, 0xD3, 0xC7, 0x5A, 0xE5,
+	0xE5, 0xBC, 0xDA, 0x86, 0x85, 0x69, 0x75, 0x36, 0x9E, 0xCB, 0x66, 0x11, 0x55, 0xA3, 0xB5, 0xF3,
+	0x57, 0x2A, 0x0E, 0x0F, 0xCF, 0xFA, 0x57, 0xCA, 0x25, 0x18, 0x92, 0x6B, 0xDF, 0xBF, 0x67, 0x60,
+	0x47, 0xEC, 0xB5, 0xF1, 0x38, 0x10, 0x7E, 0x6D, 0x2F, 0x50, 0xED, 0xFF, 0x00, 0x4E, 0x15, 0xF8,
+	0x5F, 0x81, 0x7C, 0x69, 0xC5, 0x19, 0xD7, 0x1E, 0xD2, 0xC3, 0x63, 0x71, 0x53, 0x9C, 0x1C, 0x64,
+	0xDA, 0x6D, 0xB5, 0xA2, 0xD3, 0x43, 0xEC, 0xB8, 0xCB, 0x25, 0xCA, 0xF0, 0x79, 0x1B, 0xAB, 0x42,
+	0x94, 0x63, 0x2E, 0x65, 0xAA, 0x56, 0x76, 0x6C, 0xF0, 0x54, 0xFF, 0x00, 0x82, 0xA1, 0x7E, 0xD4,
+	0x6C, 0xA2, 0x43, 0x7D, 0xA2, 0xAB, 0x30, 0xCB, 0x7F, 0xC4, 0xA5, 0x3F, 0x2E, 0xBD, 0xB9, 0xEF,
+	0xDE, 0x97, 0xFE, 0x1E, 0x83, 0xFB, 0x51, 0x9E, 0x4E, 0xA5, 0xA2, 0x9F, 0x6F, 0xEC, 0x95, 0xFE,
+	0x79, 0xE2, 0xBE, 0x74, 0x03, 0xE5, 0x51, 0xFE, 0xCF, 0xF5, 0xA0, 0x10, 0x1B, 0x93, 0x5F, 0xDE,
+	0x47, 0xE3, 0x67, 0xDE, 0xDE, 0x28, 0xFD, 0xAF, 0xFE, 0x30, 0x68, 0xBF, 0xB1, 0x2F, 0x87, 0xFF,
+	0x00, 0x68, 0x4B, 0x2B, 0x8D, 0x3D, 0x7C, 0x43, 0xAA, 0xF8, 0x85, 0xAD, 0xAE, 0xE4, 0x6D, 0x3D,
+	0x4C, 0x46, 0x31, 0x24, 0xB1, 0xF0, 0x99, 0xE0, 0xED, 0x8D, 0x7B, 0x9E, 0xE6, 0xBC, 0x50, 0x7F,
+	0xC1, 0x50, 0x7F, 0x6A, 0x25, 0xE5, 0x75, 0x1D, 0x17, 0xFF, 0x00, 0x05, 0x0B, 0xE8, 0x3D, 0xFF,
+	0x00, 0xCE, 0x2B, 0x67, 0xC7, 0xA7, 0xFE, 0x35, 0x65, 0xE0, 0xDE, 0x1B, 0x8F, 0x16, 0x48, 0x7E,
+	0xE9, 0xFF, 0x00, 0x9E, 0xF7, 0x3F, 0xE3, 0x5F, 0x2D, 0x82, 0x08, 0xE0, 0xFF, 0x00, 0x9C, 0x50,
+	0x07, 0xD3, 0x3E, 0x1A, 0xFF, 0x00, 0x82, 0x99, 0xFE, 0xD3, 0x5A, 0xAF, 0x88, 0x6C, 0x74, 0xDB,
+	0xAD, 0x47, 0x46, 0x68, 0xEE, 0x2F, 0x22, 0x8A, 0x42, 0x34, 0x95, 0xFB, 0xAC, 0xE0, 0x1E, 0xFE,
+	0xF5, 0xEB, 0x7F, 0xB6, 0xF7, 0xED, 0x7D, 0xF1, 0x87, 0xF6, 0x76, 0xF1, 0xEE, 0x87, 0xE1, 0x7F,
+	0x87, 0x97, 0x7A, 0x7C, 0x76, 0xB7, 0xDE, 0x1D, 0x8E, 0xEA, 0xE3, 0xED, 0x76, 0x2B, 0x2B, 0x17,
+	0xF3, 0x19, 0x78, 0x24, 0xF4, 0xC0, 0xF4, 0xE4, 0xD7, 0xC3, 0xFE, 0x07, 0x39, 0xF1, 0xA6, 0x92,
+	0x33, 0xFF, 0x00, 0x31, 0x2B, 0x7F, 0xFD, 0x18, 0xB5, 0xF4, 0x77, 0xFC, 0x15, 0x54, 0x91, 0xF1,
+	0x73, 0xC2, 0xA4, 0x83, 0xFF, 0x00, 0x22, 0x8C, 0x7D, 0xBF, 0xE9, 0xAB, 0x50, 0x06, 0x38, 0xFF,
+	0x00, 0x82, 0xA0, 0xFE, 0xD4, 0x64, 0x63, 0xFB, 0x4B, 0x45, 0xC6, 0x3F, 0xE8, 0x12, 0xBF, 0xE3,
+	0x5E, 0xAF, 0xFB, 0x18, 0x7E, 0xDC, 0x1F, 0x1C, 0x7E, 0x3A, 0xFC, 0x76, 0xB0, 0xF8, 0x7D, 0xE3,
+	0xAB, 0xCD, 0x2D, 0xB4, 0xDB, 0x8B, 0x3B, 0x99, 0xA5, 0x5B, 0x5D, 0x3C, 0x46, 0xC5, 0x92, 0x32,
+	0xC3, 0xE6, 0x07, 0x8E, 0x70, 0x6B, 0xE1, 0xE1, 0xD7, 0xF1, 0xAF, 0xA0, 0x3F, 0xE0, 0x99, 0x58,
+	0x6F, 0xDA, 0xBB, 0x49, 0x20, 0xE7, 0xFE, 0x25, 0xB7, 0xDF, 0xFA, 0x24, 0xD0, 0x07, 0xE9, 0x98,
+	0x34, 0xB4, 0x0F, 0xBB, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x7C, 0xE3, 0xFB, 0x59, 0xFC, 0x0B,
+	0xFD, 0x98, 0x7E, 0x2A, 0x7C, 0x43, 0xB1, 0xD6, 0xFE, 0x38, 0xFC, 0x63, 0xB5, 0xF0, 0xDE, 0xA1,
+	0x6B, 0xA6, 0x88, 0x6D, 0x6D, 0x66, 0xD6, 0xAD, 0xED, 0x7C, 0xD8, 0x8C, 0xAC, 0x77, 0x62, 0x5C,
+	0x13, 0xCF, 0xA5, 0x79, 0x68, 0xFD, 0x8E, 0x7F, 0xE0, 0x9E, 0x38, 0xE7, 0xF6, 0xA6, 0xD3, 0x7F,
+	0xF0, 0xAC, 0xB2, 0xFF, 0x00, 0x1A, 0xE5, 0x7F, 0xE0, 0xAD, 0x45, 0x97, 0xE3, 0xAE, 0x82, 0x47,
+	0x0D, 0xFF, 0x00, 0x08, 0xCE, 0x57, 0x6F, 0xFD, 0x76, 0x7E, 0xB5, 0xF2, 0xB8, 0x23, 0x18, 0x5E,
+	0x9D, 0xBF, 0xC9, 0xA0, 0x0F, 0xD1, 0x0F, 0xD9, 0x9F, 0xF6, 0x74, 0xFD, 0x91, 0x7E, 0x1C, 0xFC,
+	0x59, 0xB5, 0xF1, 0x57, 0xC1, 0xFF, 0x00, 0x8E, 0xB6, 0xBA, 0xF6, 0xB3, 0x0D, 0xAC, 0xE9, 0x0E,
+	0x9D, 0x0F, 0x88, 0x2D, 0xAE, 0x4B, 0x2B, 0xA6, 0xD6, 0x3B, 0x23, 0x24, 0xF0, 0xA3, 0x3D, 0x2B,
+	0x9F, 0xF8, 0xA9, 0xFB, 0x2D, 0x7E, 0xC3, 0xFE, 0x2A, 0xF8, 0x9D, 0xE2, 0x1F, 0x12, 0x78, 0xF3,
+	0xF6, 0x8B, 0xB3, 0xD3, 0x75, 0x8D, 0x43, 0x58, 0xB8, 0x9B, 0x52, 0xD3, 0xE4, 0xF1, 0x2D, 0xA4,
+	0x2D, 0x6F, 0x31, 0x93, 0xE6, 0x42, 0x8E, 0x77, 0x0C, 0x1E, 0xC6, 0xBC, 0x37, 0xFE, 0x09, 0x9B,
+	0xCF, 0xED, 0x5F, 0xA5, 0xE4, 0xFF, 0x00, 0xCC, 0x36, 0xFB, 0x69, 0xF4, 0xFD, 0xC1, 0xE9, 0x5C,
+	0x0F, 0xED, 0x64, 0x47, 0xFC, 0x34, 0xE7, 0x8F, 0x81, 0xFF, 0x00, 0xA1, 0xAA, 0xEF, 0x72, 0xF6,
+	0xE2, 0x43, 0x8E, 0x98, 0xEF, 0x40, 0x1F, 0x49, 0x7F, 0xC3, 0x1D, 0x7F, 0xC1, 0x3C, 0x57, 0x9F,
+	0xF8, 0x6A, 0x6D, 0x37, 0xFF, 0x00, 0x0A, 0xCB, 0x2F, 0xF1, 0xAF, 0x5E, 0xFD, 0x9F, 0x7E, 0x0A,
+	0xFE, 0xCE, 0x7F, 0x0F, 0xBE, 0x15, 0xF8, 0xD3, 0xC3, 0xFF, 0x00, 0x0A, 0xFE, 0x2C, 0xDB, 0xEB,
+	0x9A, 0x4E, 0xAD, 0x65, 0x22, 0x6B, 0x97, 0xF0, 0xEA, 0xD0, 0x5C, 0x2D, 0x9C, 0x62, 0xDE, 0x44,
+	0xDC, 0x5A, 0x32, 0x42, 0x7C, 0xA5, 0x9B, 0x27, 0xD2, 0xBF, 0x33, 0xF2, 0x3D, 0x3F, 0x95, 0x7D,
+	0x83, 0xFF, 0x00, 0x04, 0xF6, 0xC8, 0xFD, 0x98, 0x7E, 0x31, 0x1F, 0x97, 0x3F, 0xD9, 0x32, 0x73,
+	0x8E, 0xB8, 0xB2, 0xB8, 0xEB, 0xFC, 0xE8, 0x03, 0x41, 0x3F, 0x63, 0x9F, 0xF8, 0x27, 0x9A, 0xA2,
+	0xC4, 0x7F, 0x6A, 0x7D, 0x3F, 0xE5, 0xE3, 0x9F, 0x17, 0x59, 0x7A, 0x0E, 0xD9, 0xA5, 0x3F, 0xB1,
+	0xDF, 0xFC, 0x13, 0xD1, 0x06, 0xE1, 0xFB, 0x53, 0xE9, 0xB9, 0x1C, 0xF1, 0xE2, 0xEB, 0x21, 0x9C,
+	0x73, 0xFD, 0xEA, 0xF8, 0xAE, 0x32, 0x3C, 0xB5, 0x03, 0x3C, 0x2F, 0xCB, 0xBB, 0xB7, 0xAF, 0xB7,
+	0xA7, 0x6A, 0x5D, 0xE7, 0xA8, 0x3D, 0xF3, 0xF5, 0xF6, 0xA0, 0x0F, 0xD2, 0x0F, 0x8B, 0xDF, 0x02,
+	0xBF, 0x66, 0x9D, 0x77, 0xF6, 0x49, 0xF0, 0xEF, 0xC2, 0xBF, 0x14, 0x7C, 0x6B, 0x87, 0x4B, 0xF0,
+	0x6E, 0x9F, 0xA9, 0x42, 0xDA, 0x5F, 0x89, 0x3F, 0xB4, 0x20, 0x2B, 0x75, 0x28, 0x13, 0xED, 0x4F,
+	0x30, 0xFC, 0x8D, 0x9D, 0xF2, 0x74, 0xE7, 0xE4, 0xF4, 0x15, 0xE0, 0x9F, 0xF0, 0xC5, 0xBF, 0xF0,
+	0x4E, 0xB6, 0x6C, 0xFF, 0x00, 0xC3, 0x68, 0xDB, 0xF3, 0xDB, 0xFB, 0x62, 0xCF, 0xFC, 0x2A, 0xDF,
+	0xED, 0x2C, 0x00, 0xFF, 0x00, 0x82, 0x54, 0x7C, 0x3D, 0x00, 0xE1, 0x7F, 0xB7, 0x6D, 0x87, 0xCB,
+	0xFF, 0x00, 0x6F, 0xB5, 0xF1, 0x10, 0xE5, 0x41, 0x55, 0xFE, 0x11, 0xF8, 0x71, 0x5C, 0xF5, 0x5A,
+	0x52, 0xD4, 0xD2, 0x27, 0xDF, 0xDF, 0x01, 0xBF, 0x65, 0x1F, 0xD8, 0x6B, 0xC1, 0x9F, 0x19, 0xFC,
+	0x37, 0xE2, 0xAF, 0x00, 0x7E, 0xD5, 0xB0, 0x6A, 0xDA, 0xD5, 0x86, 0xA6, 0xB2, 0xE9, 0xBA, 0x6A,
+	0xEA, 0x96, 0xAE, 0x6E, 0x24, 0x0A, 0xDF, 0x2E, 0x14, 0x64, 0xF1, 0x9A, 0xEF, 0xBF, 0x69, 0x3F,
+	0xD9, 0xCF, 0xF6, 0x42, 0xF8, 0x8D, 0xF1, 0x72, 0xF7, 0xC5, 0x9F, 0x18, 0x3E, 0x3C, 0x59, 0xE8,
+	0x7A, 0xE4, 0xF6, 0xB6, 0xEB, 0x36, 0x9B, 0x71, 0xAF, 0x5A, 0xDB, 0xB2, 0x22, 0xC6, 0x15, 0x4E,
+	0xC7, 0xC3, 0x72, 0x05, 0x7C, 0x29, 0xFB, 0x13, 0x03, 0xFF, 0x00, 0x0D, 0x6B, 0xF0, 0xFF, 0x00,
+	0x03, 0xFE, 0x66, 0x05, 0xFF, 0x00, 0xD1, 0x6F, 0x5E, 0xAF, 0xFF, 0x00, 0x05, 0x2C, 0x18, 0xFD,
+	0xAE, 0x75, 0xAD, 0xBF, 0xF4, 0x0D, 0xB0, 0xF4, 0xE7, 0xF7, 0x02, 0xAE, 0x8B, 0x44, 0xC8, 0xF5,
+	0x67, 0xFD, 0x8E, 0x7F, 0xE0, 0x9E, 0x85, 0x7F, 0xE4, 0xE9, 0x74, 0xD2, 0x7B, 0x7F, 0xC5, 0x5D,
+	0x65, 0xFF, 0x00, 0xC5, 0x57, 0x96, 0xFE, 0xDB, 0x7F, 0xF0, 0x4B, 0x6F, 0x82, 0x7F, 0xB5, 0xBF,
+	0xC0, 0x9D, 0x27, 0xF6, 0x7B, 0xF0, 0x27, 0xED, 0x41, 0xE2, 0x0B, 0x0F, 0x05, 0xAF, 0x89, 0x3F,
+	0xE1, 0x21, 0xD5, 0x1F, 0x43, 0x6B, 0x5B, 0xE8, 0xF5, 0x5B, 0xB4, 0x87, 0xC8, 0x81, 0x1A, 0x4E,
+	0x9B, 0x22, 0xC4, 0xAD, 0x81, 0x9F, 0x9D, 0xD5, 0xBA, 0xA0, 0xAF, 0x07, 0xD3, 0x2C, 0x2F, 0x75,
+	0x8D, 0x4A, 0xDF, 0x49, 0xD3, 0x93, 0x75, 0xC5, 0xD5, 0xC2, 0xC3, 0x0A, 0xFA, 0xBB, 0x1C, 0x2F,
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+	0x08, 0xA8, 0xFD, 0xC9, 0x23, 0xFA, 0x0F, 0x87, 0x38, 0xBB, 0x0F, 0x9A, 0x54, 0x86, 0x0E, 0x30,
+	0x69, 0xF2, 0xEE, 0xFC, 0x92, 0x3E, 0xBE, 0xA2, 0x8A, 0x2B, 0xD4, 0x3E, 0xE4, 0x28, 0xA2, 0x8A,
+	0x00, 0xF0, 0x7F, 0xF8, 0x28, 0xEF, 0xFC, 0x9B, 0x05, 0xE7, 0xFD, 0x85, 0x2C, 0xFF, 0x00, 0xF4,
+	0x68, 0xAF, 0xCF, 0x17, 0xEB, 0x5F, 0xA1, 0xDF, 0xF0, 0x51, 0xDF, 0xF9, 0x36, 0x0B, 0xCF, 0xFB,
+	0x0A, 0x59, 0xFF, 0x00, 0xE8, 0xD1, 0x5F, 0x9E, 0x2F, 0xD6, 0xBF, 0x25, 0xE3, 0x4F, 0xF9, 0x1A,
+	0x7F, 0xDB, 0xA8, 0xFE, 0xA7, 0xF0, 0x6F, 0xFE, 0x49, 0x99, 0x7F, 0x89, 0x8D, 0xA2, 0x8A, 0x2B,
+	0xE4, 0x4F, 0xD7, 0x42, 0xAD, 0x68, 0x7F, 0xF2, 0x19, 0xB5, 0xFF, 0x00, 0xAF, 0x88, 0xFF, 0x00,
+	0xF4, 0x21, 0x55, 0x6A, 0xD6, 0x87, 0xFF, 0x00, 0x21, 0x9B, 0x5F, 0xFA, 0xF8, 0x8F, 0xFF, 0x00,
+	0x42, 0x15, 0xE8, 0x65, 0x3F, 0xF2, 0x34, 0xC3, 0xFF, 0x00, 0x8E, 0x3F, 0xFA, 0x52, 0x3E, 0x77,
+	0x8B, 0xFF, 0x00, 0xE4, 0x95, 0xC7, 0x7F, 0xD7, 0x9A, 0x9F, 0xFA, 0x4B, 0x3A, 0x19, 0x7E, 0xF3,
+	0x7F, 0xBD, 0x4C, 0x0C, 0x40, 0xC6, 0x69, 0xF2, 0xFD, 0xE6, 0xFF, 0x00, 0x7A, 0x9B, 0xE9, 0x9A,
+	0xFF, 0x00, 0x4E, 0x30, 0x3F, 0xEE, 0x74, 0xFF, 0x00, 0xC2, 0xBF, 0x24, 0x7F, 0xCC, 0x5E, 0x75,
+	0xFF, 0x00, 0x23, 0x8A, 0xFF, 0x00, 0xE3, 0x97, 0xE6, 0x28, 0x6F, 0xDD, 0xFB, 0x75, 0x3E, 0xDC,
+	0xD7, 0xD4, 0x5F, 0xB0, 0x85, 0xCF, 0x88, 0xFC, 0x61, 0xE1, 0x7D, 0x5B, 0xC1, 0x3A, 0x36, 0x89,
+	0x7F, 0xA8, 0x4D, 0xA5, 0xDC, 0x0B, 0xA8, 0xE3, 0xB2, 0xB5, 0x79, 0x99, 0x61, 0x90, 0x73, 0xC2,
+	0x03, 0x80, 0x1D, 0x49, 0xFA, 0xC9, 0xEF, 0x5F, 0x2E, 0xAE, 0x07, 0x3E, 0x87, 0xF3, 0xAF, 0xA5,
+	0xBF, 0xE0, 0x96, 0x5F, 0xB5, 0x4F, 0x8A, 0x3F, 0x65, 0x0F, 0xDA, 0x45, 0xBC, 0x4D, 0xE1, 0xBD,
+	0x32, 0xD6, 0xF9, 0x75, 0xCD, 0x16, 0x7D, 0x36, 0xEA, 0xCE, 0xF2, 0x46, 0x11, 0xB2, 0x92, 0x92,
+	0xAB, 0x71, 0xCE, 0xE0, 0xF1, 0x0F, 0xC3, 0x35, 0xF2, 0xFC, 0x7D, 0x97, 0xFF, 0x00, 0x68, 0xF0,
+	0xDD, 0x54, 0x95, 0xDC, 0x57, 0x32, 0xF9, 0x7F, 0xC0, 0x3E, 0x8B, 0x80, 0x33, 0x2F, 0xEC, 0xEE,
+	0x26, 0xA4, 0xDB, 0xB2, 0x93, 0xE5, 0x7F, 0x33, 0xED, 0x8F, 0xD8, 0xCF, 0xE1, 0xEF, 0xC4, 0x1D,
+	0x2B, 0xF6, 0x9E, 0xF0, 0x6E, 0xA1, 0xAA, 0x78, 0x0B, 0x5C, 0xB5, 0xB7, 0x87, 0x56, 0x06, 0x69,
+	0xAE, 0xB4, 0x89, 0xE3, 0x44, 0x1B, 0x1B, 0x92, 0xCC, 0xA0, 0x0F, 0xC6, 0xBD, 0xAB, 0xF6, 0xAB,
+	0xD1, 0xB5, 0x9B, 0x9F, 0x8E, 0xDA, 0xCD, 0xD5, 0xBE, 0x8F, 0x77, 0x24, 0x6D, 0xE4, 0xED, 0x92,
+	0x3B, 0x57, 0x65, 0x6F, 0xDD, 0x2F, 0x42, 0x06, 0x0D, 0x5E, 0xF8, 0x07, 0xFF, 0x00, 0x05, 0x26,
+	0xF8, 0x85, 0xF1, 0x7F, 0xE3, 0x1E, 0x81, 0xF0, 0xDB, 0x55, 0xF8, 0x73, 0xA2, 0xDA, 0xC1, 0xAB,
+	0x5F, 0x79, 0x32, 0xDC, 0x41, 0x71, 0x2B, 0x3C, 0x63, 0x04, 0xE5, 0x73, 0xC6, 0x7F, 0xC6, 0xBB,
+	0xCF, 0x8D, 0xBF, 0xB5, 0x5F, 0x8C, 0x7E, 0x1C, 0xFC, 0x4C, 0xD4, 0x7C, 0x21, 0xA6, 0xF8, 0x6B,
+	0x4D, 0xB8, 0x86, 0xD7, 0x66, 0xC9, 0xA7, 0xDF, 0xBD, 0xB7, 0x22, 0x9E, 0x70, 0x6B, 0xFC, 0xE1,
+	0xF1, 0xE3, 0x03, 0x90, 0xE3, 0x78, 0x5E, 0x10, 0xCD, 0xB1, 0x12, 0xA3, 0x4F, 0x9D, 0x3E, 0x65,
+	0x1E, 0x67, 0x7B, 0x68, 0xAC, 0x9A, 0x3F, 0xB7, 0x38, 0x3E, 0xA6, 0x3A, 0x8E, 0x64, 0xE5, 0x84,
+	0xA6, 0xA7, 0x2E, 0x57, 0xA3, 0x76, 0xD3, 0x43, 0xE7, 0x03, 0xE1, 0xBF, 0x11, 0xB0, 0x3B, 0x74,
+	0x0B, 0xEF, 0xFC, 0x05, 0x7F, 0xF0, 0xAF, 0x7B, 0xFD, 0x9E, 0x34, 0x9D, 0x56, 0x3F, 0xD9, 0x8F,
+	0xE2, 0x55, 0x94, 0xBA, 0x4D, 0xD2, 0xCF, 0x36, 0x9F, 0x7E, 0x20, 0x85, 0xA0, 0x70, 0xF2, 0x13,
+	0x65, 0x80, 0x14, 0x63, 0x24, 0x93, 0xC7, 0x15, 0x90, 0xDF, 0xB7, 0x27, 0xC4, 0x12, 0xB8, 0x1E,
+	0x0F, 0xD1, 0xBE, 0x5F, 0x51, 0x2F, 0xFF, 0x00, 0x14, 0x2B, 0xD3, 0xBE, 0x12, 0xFE, 0xD0, 0x7E,
+	0x22, 0xF1, 0xA7, 0xC1, 0xEF, 0x17, 0x7C, 0x42, 0xBF, 0xD0, 0xEC, 0x61, 0xB9, 0xF0, 0xF5, 0xAD,
+	0xC4, 0xF6, 0xF6, 0xF6, 0xFB, 0xD6, 0x39, 0x1A, 0x3B, 0x7F, 0x34, 0x6E, 0xE7, 0x38, 0xC8, 0x03,
+	0xE9, 0x5F, 0x8B, 0x78, 0x2F, 0x94, 0x70, 0x2E, 0x0F, 0x8D, 0xA9, 0xD4, 0xCB, 0x31, 0xF2, 0xAB,
+	0x57, 0x96, 0x56, 0x8B, 0x83, 0x49, 0xAB, 0x6A, 0xEF, 0x7E, 0x87, 0xD6, 0x71, 0x6E, 0x33, 0x3C,
+	0xAD, 0x94, 0xB8, 0xE2, 0xB0, 0xEA, 0x11, 0xBA, 0xD5, 0x4A, 0xFD, 0x74, 0x56, 0x3F, 0x36, 0x13,
+	0xE1, 0x8F, 0xC4, 0xE6, 0x8D, 0x48, 0xF8, 0x67, 0xE2, 0x3F, 0xBB, 0x9F, 0xF9, 0x00, 0xDC, 0xFF,
+	0x00, 0xF1, 0x14, 0x7F, 0xC2, 0xAF, 0xF8, 0x9D, 0x9C, 0xFF, 0x00, 0xC2, 0xB4, 0xF1, 0x17, 0xFE,
+	0x08, 0xEE, 0x3F, 0xF8, 0x8A, 0xFA, 0x62, 0x2F, 0xF8, 0x2B, 0x8F, 0xC5, 0x70, 0x83, 0x77, 0xC2,
+	0x6F, 0x0F, 0x0E, 0xFF, 0x00, 0xF1, 0xF5, 0x37, 0xE3, 0xFA, 0xE6, 0x94, 0xFF, 0x00, 0xC1, 0x5C,
+	0x7E, 0x2A, 0x92, 0x00, 0xF8, 0x4F, 0xE1, 0xDF, 0xFC, 0x08, 0x9B, 0x8F, 0x7A, 0xFE, 0xDB, 0x3F,
+	0x27, 0x13, 0xC7, 0x3E, 0x11, 0xF1, 0x6C, 0xBF, 0xF0, 0x4C, 0x8F, 0x08, 0xF8, 0x76, 0x2F, 0x0A,
+	0xEA, 0x8D, 0xA8, 0xC3, 0xE2, 0xB7, 0x69, 0x74, 0xF5, 0xD3, 0xE5, 0x33, 0xA0, 0xF3, 0xAE, 0x4E,
+	0x5A, 0x30, 0xBB, 0x80, 0xC6, 0x3A, 0x8E, 0xE2, 0xBE, 0x67, 0x1F, 0x0B, 0xBE, 0x27, 0xFF, 0x00,
+	0xD1, 0x34, 0xF1, 0x17, 0xFE, 0x08, 0xEE, 0x3D, 0x3F, 0xDC, 0xAF, 0xBC, 0x3C, 0x43, 0xFB, 0x6D,
+	0x78, 0xD3, 0x42, 0xFD, 0x90, 0xF4, 0x3F, 0xDA, 0x56, 0x0F, 0x05, 0x69, 0x6D, 0xA8, 0x6A, 0xDA,
+	0xEB, 0xDB, 0x49, 0xA6, 0xB4, 0xB2, 0x79, 0x11, 0x00, 0xD2, 0xC7, 0xC1, 0xCE, 0xE2, 0x71, 0x1F,
+	0x71, 0xDC, 0xD7, 0x93, 0x8F, 0xF8, 0x2B, 0x97, 0xC5, 0x6E, 0xFF, 0x00, 0x0A, 0x3C, 0x3B, 0xFF,
+	0x00, 0x81, 0x13, 0x71, 0x40, 0x1F, 0x3D, 0xF8, 0x2F, 0xE1, 0x97, 0xC4, 0xB8, 0x7C, 0x63, 0xA5,
+	0xC9, 0x2F, 0xC3, 0x7F, 0x10, 0xAA, 0xAE, 0xA3, 0x09, 0x66, 0x6D, 0x0E, 0xE0, 0x00, 0x3C, 0xC5,
+	0xE7, 0xEE, 0x57, 0xD0, 0x5F, 0xF0, 0x53, 0xBF, 0x08, 0x78, 0xBF, 0xC4, 0x3F, 0x16, 0x7C, 0x2F,
+	0x3F, 0x87, 0xFC, 0x27, 0xAA, 0x6A, 0x11, 0xC7, 0xE1, 0x18, 0x96, 0x49, 0x2C, 0x34, 0xF9, 0x66,
+	0x54, 0x6F, 0x39, 0xF8, 0x62, 0x8A, 0x70, 0x7D, 0x8E, 0x2A, 0xEE, 0x89, 0xFF, 0x00, 0x05, 0x5D,
+	0xF8, 0xA5, 0xAD, 0xEB, 0xD6, 0x1A, 0x3C, 0xBF, 0x0B, 0x3C, 0x3E, 0xB1, 0xDD, 0x5E, 0x45, 0x1B,
+	0xB2, 0xDC, 0x4D, 0x90, 0x0B, 0x80, 0x6B, 0xD3, 0x7F, 0x6B, 0xAF, 0xDB, 0x73, 0xC7, 0x1F, 0xB3,
+	0x1F, 0x8D, 0x34, 0x5F, 0x0A, 0xF8, 0x7B, 0xC1, 0x9A, 0x5E, 0xA7, 0x1E, 0xA1, 0xA0, 0x47, 0x77,
+	0x34, 0xD7, 0xD2, 0xC8, 0xAC, 0xAD, 0xBD, 0x97, 0x03, 0x69, 0x3C, 0x71, 0xED, 0xCD, 0x00, 0x7C,
+	0x1E, 0xBF, 0x0B, 0xBE, 0x27, 0xF5, 0x3F, 0x0D, 0x3C, 0x45, 0xDB, 0xFE, 0x60, 0x77, 0x1F, 0xFC,
+	0x45, 0x7B, 0xC7, 0xFC, 0x13, 0x8B, 0xC0, 0xFE, 0x38, 0xD0, 0x7F, 0x6A, 0x0D, 0x33, 0x51, 0xD7,
+	0x7C, 0x15, 0xAC, 0x58, 0xDB, 0xA6, 0x9B, 0x7C, 0xAF, 0x71, 0x79, 0xA5, 0xCD, 0x12, 0x29, 0x30,
+	0x1C, 0x02, 0xCC, 0xA0, 0x0F, 0xCF, 0xAD, 0x74, 0x3F, 0xF0, 0xF7, 0x2F, 0x8A, 0x98, 0xE7, 0xE1,
+	0x4F, 0x87, 0xBF, 0xDE, 0xFB, 0x44, 0xD5, 0xE8, 0xFF, 0x00, 0xB2, 0x87, 0xFC, 0x14, 0x03, 0xC7,
+	0xDF, 0xB4, 0x37, 0xC6, 0x9B, 0x3F, 0x86, 0xFA, 0xFF, 0x00, 0x80, 0xB4, 0x7D, 0x3E, 0xDE, 0xE6,
+	0xCA, 0xE6, 0x56, 0xB8, 0xB3, 0x9A, 0x46, 0x75, 0x29, 0x19, 0x61, 0x8D, 0xDC, 0x76, 0xC7, 0xD2,
+	0x80, 0x3E, 0xB8, 0x1D, 0x7A, 0xD1, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14, 0x01, 0xF9, 0xEB, 0xFF,
+	0x00, 0x05, 0x6C, 0x23, 0xFE, 0x17, 0xA7, 0x87, 0xC9, 0x6C, 0x7F, 0xC5, 0x32, 0xBD, 0x78, 0xFF,
+	0x00, 0x97, 0x87, 0xAF, 0x95, 0x40, 0x20, 0x72, 0xA7, 0xF2, 0xAF, 0xD2, 0x3F, 0xDB, 0x03, 0xF6,
+	0x35, 0xF0, 0xCF, 0xED, 0x1D, 0xF1, 0x0B, 0x4F, 0xF1, 0x66, 0xB3, 0xF1, 0xA6, 0xDF, 0xC3, 0x72,
+	0x58, 0xE9, 0x6B, 0x6C, 0xB6, 0xB2, 0x69, 0xF1, 0xCC, 0x65, 0x5F, 0x35, 0xDF, 0x77, 0xCD, 0x2A,
+	0x77, 0x38, 0xE8, 0x6B, 0xC9, 0xBF, 0xE1, 0xD5, 0x3F, 0x0E, 0xC7, 0x5F, 0xDA, 0xB2, 0xC7, 0xFF,
+	0x00, 0x04, 0xB0, 0x7F, 0xF2, 0x55, 0x00, 0x79, 0xAF, 0xFC, 0x13, 0x34, 0xFF, 0x00, 0xC6, 0x57,
+	0xE9, 0x63, 0xD3, 0x4D, 0xBD, 0xCA, 0xF7, 0xFF, 0x00, 0x50, 0x6B, 0x81, 0xFD, 0xAD, 0x30, 0x7F,
+	0x69, 0xDF, 0x1F, 0x00, 0x46, 0x7F, 0xE1, 0x2A, 0xBC, 0xE0, 0x1F, 0xFA, 0x6B, 0x5F, 0x65, 0xFE,
+	0xCB, 0xBF, 0xB0, 0x97, 0x84, 0xFE, 0x03, 0x7C, 0x5B, 0xB4, 0xF8, 0x85, 0xA4, 0x7C, 0x79, 0xB7,
+	0xF1, 0x04, 0xD6, 0xF6, 0xF3, 0xC6, 0xBA, 0x64, 0x3A, 0x6C, 0x51, 0x17, 0x0F, 0x19, 0x42, 0xD9,
+	0x59, 0xDC, 0xF0, 0x0E, 0x7A, 0x57, 0x3D, 0xF1, 0x6B, 0xFE, 0x09, 0xC3, 0xE0, 0xAF, 0x89, 0x3F,
+	0x14, 0x7C, 0x45, 0xE3, 0xDB, 0xDF, 0xDA, 0x46, 0xD7, 0x4D, 0x93, 0x58, 0xD6, 0x2E, 0x2E, 0xA5,
+	0xD3, 0xDF, 0x4B, 0x86, 0x43, 0x6E, 0xCE, 0xE5, 0x8A, 0x96, 0x33, 0xA9, 0x38, 0xC7, 0xA0, 0xA0,
+	0x0F, 0x84, 0xF0, 0x7D, 0x2B, 0xEC, 0x3F, 0xF8, 0x27, 0xA9, 0x07, 0xF6, 0x61, 0xF8, 0xC8, 0x54,
+	0xE4, 0x1D, 0x26, 0x5E, 0x47, 0xFD, 0x79, 0x5C, 0x54, 0xFF, 0x00, 0xF0, 0xEA, 0xBF, 0x87, 0x83,
+	0x91, 0xFB, 0x56, 0xD8, 0xFF, 0x00, 0xE0, 0x96, 0x0F, 0xFE, 0x4A, 0xAF, 0x64, 0xFD, 0x9E, 0x3F,
+	0x64, 0x9F, 0x0F, 0x7C, 0x16, 0xF8, 0x4F, 0xE3, 0x6F, 0x01, 0x69, 0x9F, 0x17, 0x61, 0xD7, 0x21,
+	0xF1, 0x35, 0x8B, 0xC3, 0x71, 0xA8, 0x47, 0x67, 0x1C, 0x62, 0xC7, 0x30, 0x4B, 0x1E, 0x48, 0x59,
+	0x58, 0x1E, 0x1C, 0x9E, 0x48, 0xE9, 0x40, 0x1F, 0x99, 0xE9, 0xCA, 0x2E, 0xD3, 0x9E, 0x3F, 0x87,
+	0x9E, 0xC2, 0x9D, 0x9D, 0xBF, 0x33, 0x70, 0x3D, 0x4D, 0x7D, 0x94, 0x3F, 0xE0, 0x95, 0x5F, 0x0F,
+	0xF6, 0xE1, 0xBF, 0x6A, 0xDB, 0x3F, 0x6D, 0xDA, 0x2C, 0x1C, 0x76, 0xC7, 0xFC, 0x7C, 0xFB, 0x51,
+	0xFF, 0x00, 0x0E, 0xAB, 0xF8, 0x7C, 0xA7, 0x29, 0xFB, 0x56, 0xD8, 0xFE, 0x1A, 0x24, 0x1C, 0x7F,
+	0xE4, 0xD5, 0x00, 0x63, 0x7E, 0xD2, 0xD9, 0xFF, 0x00, 0x87, 0x54, 0x7C, 0x3D, 0x18, 0xFF, 0x00,
+	0x98, 0xF5, 0xB7, 0xFE, 0xDE, 0xD7, 0xC4, 0x4A, 0x0E, 0xD1, 0xF2, 0x9E, 0x9E, 0x95, 0xFA, 0x9F,
+	0xF1, 0x63, 0xF6, 0x3B, 0xF0, 0xF7, 0x8F, 0x3F, 0x64, 0x8F, 0x0E, 0xFE, 0xCF, 0x53, 0xFC, 0x6A,
+	0xB5, 0xD3, 0x6C, 0xF4, 0x7D, 0x4A, 0x39, 0xE3, 0xF1, 0x24, 0xDA, 0x72, 0x4B, 0x1D, 0xCE, 0x3E,
+	0xD1, 0xF2, 0x04, 0xF3, 0xD0, 0x02, 0x7C, 0xD3, 0xC8, 0x73, 0xF7, 0x7A, 0x1C, 0xE4, 0x78, 0x30,
+	0xFF, 0x00, 0x82, 0x47, 0xF8, 0x15, 0xB0, 0xE7, 0xF6, 0xCD, 0xD1, 0xFE, 0x6E, 0x7F, 0xE4, 0x5D,
+	0x8B, 0xDB, 0xFE, 0x9F, 0xAB, 0x9E, 0xB5, 0x37, 0x29, 0x68, 0x69, 0x19, 0x1F, 0x3D, 0xFE, 0xC4,
+	0xC0, 0x8F, 0xDA, 0xD7, 0xC0, 0x04, 0xAF, 0xFC, 0xCC, 0x09, 0xDB, 0xFD, 0x87, 0xAF, 0x55, 0xFF,
+	0x00, 0x82, 0x96, 0x73, 0xFB, 0x5C, 0xEB, 0x01, 0x4F, 0xFC, 0xC3, 0x6C, 0x3F, 0x1F, 0xDC, 0x2D,
+	0x7A, 0xDF, 0xC0, 0x8F, 0xF8, 0x26, 0x87, 0x83, 0xFE, 0x14, 0x7C, 0x64, 0xF0, 0xE7, 0xC4, 0x8B,
+	0x3F, 0xDA, 0xAF, 0x4B, 0xD5, 0xE6, 0xD1, 0xF5, 0x25, 0xB8, 0x8F, 0x4B, 0x8F, 0x44, 0x8E, 0x36,
+	0xB9, 0x6D, 0xAC, 0x36, 0x06, 0xFB, 0x63, 0xE0, 0xF3, 0xFD, 0xD6, 0xFA, 0x57, 0x65, 0xFB, 0x4D,
+	0xFE, 0xC2, 0x1E, 0x15, 0xF8, 0xF3, 0xF1, 0x7A, 0xFB, 0xE2, 0x3E, 0xA9, 0xF1, 0xE2, 0xD7, 0x43,
+	0xB8, 0xBA, 0xB7, 0xB6, 0x8A, 0x4D, 0x2D, 0xB4, 0xD8, 0xE5, 0x28, 0x23, 0x8C, 0x28, 0x3B, 0x9A,
+	0x74, 0x3C, 0x81, 0x9F, 0xBA, 0x3E, 0x94, 0xE1, 0xEE, 0xC5, 0xEA, 0x4C, 0xBD, 0xE9, 0x1C, 0x27,
+	0xEC, 0x8B, 0xA3, 0x2E, 0x8F, 0xF0, 0x17, 0x48, 0x70, 0x98, 0x6B, 0xE9, 0x67, 0xBA, 0x7E, 0x3F,
+	0xBC, 0xFB, 0x57, 0xFF, 0x00, 0x1C, 0x55, 0xAF, 0x4B, 0xC7, 0x7A, 0xF9, 0x02, 0xEB, 0xFE, 0x0B,
+	0x0F, 0xFF, 0x00, 0x04, 0xC8, 0xFD, 0x9D, 0x2F, 0xEE, 0x7E, 0x01, 0x78, 0x83, 0xF6, 0x92, 0x95,
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+	0x5E, 0xF0, 0xAE, 0x9B, 0x7E, 0xD1, 0xD8, 0xEA, 0x0B, 0x3C, 0x5E, 0x54, 0xEB, 0x2C, 0x63, 0x86,
+	0x12, 0x47, 0x84, 0x6E, 0xEC, 0xA0, 0x7A, 0x62, 0xBE, 0x8F, 0xFD, 0x91, 0x3F, 0x6B, 0xBF, 0xD8,
+	0x7B, 0xC0, 0x9E, 0x18, 0xFD, 0x9F, 0xB5, 0x4F, 0xDA, 0x0B, 0x53, 0xF8, 0xB1, 0x63, 0xE2, 0x2F,
+	0x80, 0x9F, 0x11, 0xAE, 0x3C, 0x47, 0x67, 0x61, 0xE0, 0xBF, 0x07, 0xE9, 0xB7, 0xF6, 0x5A, 0xE4,
+	0x6D, 0x7F, 0x67, 0x76, 0x91, 0xBC, 0xF7, 0x3A, 0x95, 0xBC, 0x90, 0xB6, 0x6D, 0x76, 0x1D, 0xB1,
+	0xB6, 0x37, 0x6E, 0x05, 0xB9, 0x51, 0x11, 0xE5, 0x34, 0x93, 0xAA, 0x73, 0xBF, 0xB3, 0xFF, 0x00,
+	0xEC, 0x05, 0xFB, 0x38, 0xF8, 0xC3, 0xE1, 0x7E, 0x83, 0xE3, 0xFF, 0x00, 0xDA, 0x37, 0xF6, 0x9D,
+	0xF1, 0x67, 0x86, 0x2E, 0xFC, 0x65, 0xF1, 0x82, 0xEB, 0xE1, 0xFF, 0x00, 0x85, 0xEC, 0x3C, 0x2B,
+	0xF0, 0xF6, 0x0D, 0x5D, 0x65, 0xBC, 0x84, 0x5B, 0x6E, 0x9E, 0x77, 0x96, 0xFE, 0x02, 0x91, 0x93,
+	0x75, 0x18, 0x00, 0x07, 0x2A, 0x15, 0x8E, 0x4F, 0x19, 0xD2, 0xFF, 0x00, 0x82, 0x69, 0x7C, 0x32,
+	0x9B, 0xE0, 0x87, 0xFC, 0x17, 0x37, 0xE1, 0x9F, 0xC1, 0x9B, 0xED, 0x66, 0x3D, 0x42, 0x4F, 0x08,
+	0x7C, 0x70, 0x9B, 0x45, 0x92, 0xFE, 0x28, 0xCC, 0x69, 0x73, 0xF6, 0x49, 0x67, 0x83, 0xCC, 0x08,
+	0x49, 0xDA, 0x09, 0x42, 0xC0, 0x64, 0xE0, 0x36, 0x0F, 0x4A, 0x9B, 0xE0, 0x07, 0xED, 0x79, 0xFB,
+	0x15, 0x4D, 0xF0, 0x83, 0xC1, 0x7E, 0x0F, 0xFD, 0xA3, 0x35, 0x7F, 0x8A, 0x9A, 0x2E, 0xA5, 0xE0,
+	0x5F, 0x8F, 0xD7, 0x9F, 0x11, 0x74, 0xD3, 0xE0, 0x7F, 0x0B, 0xE9, 0xBA, 0x95, 0xBE, 0xA1, 0x0C,
+	0xDF, 0x62, 0x2B, 0x6D, 0x2B, 0x5D, 0x5F, 0xDB, 0xB4, 0x2C, 0x0D, 0xA3, 0x02, 0xCA, 0xB2, 0x02,
+	0x24, 0xE3, 0xEE, 0xE0, 0xC9, 0xFF, 0x00, 0x04, 0xF0, 0xF8, 0x97, 0xA5, 0xFC, 0x6C, 0xFF, 0x00,
+	0x82, 0xF4, 0x78, 0x07, 0xE3, 0x0E, 0x8B, 0xA7, 0x4D, 0x6B, 0x63, 0xE2, 0xFF, 0x00, 0x8F, 0x57,
+	0x7A, 0xD5, 0xAD, 0xA5, 0xE6, 0x3C, 0xC8, 0x62, 0xBA, 0xB8, 0xBA, 0x9D, 0x11, 0xF0, 0x4A, 0xEE,
+	0x0A, 0xE1, 0x4E, 0x33, 0x82, 0x38, 0x24, 0x56, 0x86, 0x3E, 0xF7, 0x2B, 0xB9, 0xE3, 0xFF, 0x00,
+	0xB4, 0xD7, 0xEC, 0xDD, 0xFB, 0x41, 0xDF, 0xFE, 0xD1, 0xBE, 0x3E, 0xBB, 0xB2, 0xF8, 0x17, 0xE2,
+	0xE9, 0xA3, 0x93, 0xC6, 0x7A, 0x9B, 0x47, 0x24, 0x5E, 0x1B, 0xB9, 0x65, 0x65, 0x37, 0x72, 0x90,
+	0x41, 0x09, 0xDC, 0x72, 0x3D, 0x47, 0x35, 0xC2, 0xCF, 0xFB, 0x31, 0xFE, 0xD1, 0xDE, 0x44, 0x83,
+	0xFE, 0x14, 0x1F, 0x8C, 0xB9, 0x8D, 0x87, 0xFC, 0x8B, 0x37, 0x5E, 0x9F, 0xEE, 0x57, 0xD3, 0x9F,
+	0xB4, 0x3F, 0xFC, 0x16, 0x43, 0xFE, 0x0A, 0x97, 0xE1, 0xAF, 0x8F, 0x5E, 0x36, 0xF0, 0xEF, 0x87,
+	0x7F, 0x6E, 0x7F, 0x88, 0x16, 0x7A, 0x7E, 0x9F, 0xE2, 0xDD, 0x4A, 0xDA, 0xC6, 0xDE, 0x1B, 0xE8,
+	0xB6, 0x43, 0x0C, 0x77, 0x52, 0x2A, 0xC6, 0x3F, 0x77, 0xD8, 0x00, 0x3B, 0xF0, 0x07, 0x35, 0xC5,
+	0xCF, 0xFF, 0x00, 0x05, 0xAF, 0xFF, 0x00, 0x82, 0xB2, 0x45, 0x04, 0x92, 0x2F, 0xED, 0xF3, 0xF1,
+	0x0B, 0xE5, 0x52, 0x77, 0x7F, 0x68, 0x43, 0xF2, 0xFB, 0xFF, 0x00, 0xAB, 0xA9, 0xBF, 0x62, 0xE3,
+	0xED, 0x39, 0x74, 0xFD, 0x4F, 0xD7, 0xAF, 0xF8, 0x27, 0x08, 0xBD, 0x6F, 0x8D, 0x7F, 0x0B, 0x4E,
+	0xA1, 0x14, 0xD1, 0xCE, 0x12, 0xD4, 0x4B, 0x1D, 0xC2, 0xE1, 0x83, 0x8B, 0x7F, 0x99, 0x48, 0x23,
+	0x20, 0x82, 0x30, 0x7B, 0x83, 0xC1, 0xAF, 0xA3, 0xBF, 0x6A, 0xF8, 0xD0, 0x7C, 0x78, 0xD6, 0x9E,
+	0x50, 0x3A, 0xC3, 0xD7, 0x07, 0xFE, 0x59, 0x2E, 0x6B, 0xE7, 0xBF, 0xF8, 0x27, 0xA5, 0xD7, 0x89,
+	0x35, 0xAF, 0x8E, 0xFF, 0x00, 0x0D, 0x7C, 0x41, 0xE2, 0x5B, 0xBB, 0xAB, 0xCB, 0xEB, 0xE9, 0x2D,
+	0xEE, 0x2F, 0xEF, 0xAE, 0xBE, 0xFC, 0xF3, 0x3C, 0x1B, 0x9A, 0x46, 0x38, 0xC1, 0x66, 0x62, 0xC4,
+	0xE3, 0xDB, 0x8A, 0xD7, 0xFF, 0x00, 0x82, 0x86, 0x6A, 0x5A, 0xB4, 0x3F, 0xB5, 0xDF, 0x8A, 0xA1,
+	0xB4, 0xBF, 0xB8, 0x54, 0x56, 0xB7, 0xC2, 0xC3, 0x3B, 0x05, 0x1F, 0xB8, 0x4F, 0x43, 0x5F, 0x9E,
+	0xF8, 0x9D, 0xC0, 0xF8, 0xAE, 0x3D, 0xC8, 0xE3, 0x80, 0xA3, 0x5F, 0xD9, 0x35, 0x25, 0x2E, 0x6F,
+	0x45, 0xB6, 0xE8, 0xF4, 0x78, 0x6F, 0x34, 0xA7, 0x94, 0xE6, 0x0E, 0xB4, 0xE1, 0xCD, 0x75, 0x6B,
+	0x5F, 0xAD, 0xCE, 0x9B, 0x64, 0x2C, 0x5B, 0xE5, 0x52, 0x3A, 0x1C, 0x2F, 0xAF, 0x1E, 0xB5, 0xF4,
+	0x0F, 0xEC, 0xE9, 0x81, 0xFB, 0x2E, 0xFC, 0x4F, 0x39, 0xC3, 0x7F, 0x66, 0xEA, 0x05, 0xB9, 0xE9,
+	0xFF, 0x00, 0x12, 0xFF, 0x00, 0xF1, 0xCF, 0x7A, 0xFC, 0xEF, 0x1A, 0x9E, 0xBE, 0xE0, 0xA9, 0xD4,
+	0xEF, 0x31, 0x8E, 0x73, 0x71, 0x27, 0xF8, 0x9A, 0xFB, 0x53, 0xFE, 0x09, 0xE3, 0x3D, 0xED, 0xEF,
+	0xEC, 0x75, 0xF1, 0x82, 0x4B, 0xAB, 0x89, 0xE6, 0x3B, 0x6F, 0x96, 0x36, 0x99, 0x8B, 0x1F, 0xF9,
+	0x06, 0x0E, 0x07, 0xE2, 0x4D, 0x7E, 0x79, 0xE1, 0xDF, 0x82, 0x39, 0x87, 0x05, 0x71, 0x24, 0x33,
+	0x3A, 0xB8, 0xEF, 0x6A, 0xA2, 0x9A, 0xE5, 0xB3, 0xEA, 0xBB, 0xDD, 0x9F, 0x41, 0xC4, 0x7C, 0x55,
+	0x47, 0x36, 0xCB, 0x5D, 0x08, 0xD2, 0xE5, 0x6D, 0xA7, 0x7B, 0xF6, 0xF9, 0x1F, 0x1B, 0x20, 0xDA,
+	0x8A, 0x47, 0x19, 0x5C, 0xFA, 0x7E, 0x1F, 0x87, 0xD7, 0xBD, 0x2A, 0x92, 0x48, 0xC9, 0x27, 0x9C,
+	0xF3, 0x52, 0x25, 0xAD, 0xCB, 0x22, 0x85, 0xB7, 0x90, 0xF1, 0xFF, 0x00, 0x3C, 0xCF, 0xAD, 0x28,
+	0xB3, 0xBB, 0x07, 0x26, 0xD6, 0x4F, 0xFB, 0xF6, 0x6B, 0xFA, 0x3C, 0xFC, 0xEC, 0xFA, 0x7B, 0xC7,
+	0xA0, 0xFF, 0x00, 0xC3, 0xAB, 0xFC, 0x1A, 0x9C, 0xFF, 0x00, 0xC8, 0xD9, 0x20, 0xDD, 0xD7, 0x3F,
+	0xBF, 0xBA, 0xE3, 0xAF, 0xD3, 0xF2, 0xAF, 0x97, 0x13, 0x72, 0x8C, 0x29, 0xC7, 0xB2, 0xF1, 0xDB,
+	0xE8, 0x3F, 0xAD, 0x7D, 0x4F, 0xE3, 0xE8, 0xA5, 0x6F, 0xF8, 0x25, 0xA7, 0x83, 0x62, 0x58, 0x9B,
+	0x72, 0xF8, 0xAD, 0xF7, 0x2E, 0xDE, 0x57, 0xF7, 0xF7, 0x5D, 0xBF, 0xCF, 0x6A, 0xF9, 0x73, 0xEC,
+	0x97, 0x67, 0xEE, 0xDB, 0x48, 0x7F, 0xE0, 0x27, 0xD2, 0x80, 0x34, 0xBC, 0x0C, 0xCE, 0xBE, 0x35,
+	0xD2, 0x08, 0x76, 0xCF, 0xF6, 0x94, 0x3C, 0x6E, 0x3F, 0xF3, 0xD0, 0x57, 0xD1, 0x5F, 0xF0, 0x55,
+	0x30, 0x5B, 0xE2, 0xE7, 0x85, 0x14, 0x8C, 0x7F, 0xC5, 0x23, 0x19, 0xC6, 0xDF, 0xFA, 0x6C, 0xFC,
+	0xF7, 0xFA, 0x74, 0xAF, 0x9E, 0x3C, 0x0D, 0x6D, 0x74, 0x9E, 0x36, 0xD2, 0x0B, 0xDB, 0x48, 0x3F,
+	0xE2, 0x67, 0x6F, 0xC9, 0x8C, 0xFF, 0x00, 0xCF, 0x45, 0xAF, 0xA2, 0xFF, 0x00, 0xE0, 0xA9, 0xF0,
+	0xCB, 0x2F, 0xC5, 0xBF, 0x0A, 0xB4, 0x71, 0x33, 0x2F, 0xFC, 0x22, 0x31, 0x72, 0xA3, 0x39, 0xFD,
+	0xEB, 0xF7, 0xFF, 0x00, 0x39, 0xEB, 0x40, 0x1F, 0x2D, 0xA9, 0x6C, 0x63, 0x71, 0xFC, 0x0F, 0xFF,
+	0x00, 0xAA, 0xBE, 0x80, 0xFF, 0x00, 0x82, 0x66, 0x16, 0x3F, 0xB5, 0x6E, 0x96, 0x8C, 0xEC, 0x57,
+	0xFB, 0x36, 0xF0, 0xE3, 0x77, 0x4F, 0xDC, 0x35, 0x78, 0x18, 0xB3, 0xBC, 0xC7, 0x16, 0xB2, 0x76,
+	0xE8, 0x86, 0xBD, 0xFB, 0xFE, 0x09, 0xA3, 0x0C, 0xD1, 0x7E, 0xD5, 0x9A, 0x69, 0x96, 0x07, 0x5F,
+	0xF8, 0x96, 0x5E, 0xF2, 0xD1, 0x91, 0xFF, 0x00, 0x2C, 0x0D, 0x00, 0x7E, 0x99, 0x03, 0x9A, 0x28,
+	0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x07, 0xCD, 0x7F, 0xB6, 0x07, 0xED, 0x91, 0xA1, 0xFE, 0xCD,
+	0x9F, 0x11, 0x2C, 0x7C, 0x2F, 0xA9, 0x7C, 0x24, 0xB7, 0xF1, 0x13, 0x5F, 0x69, 0x6B, 0x76, 0xB7,
+	0x53, 0x5D, 0x24, 0x66, 0x2F, 0xDE, 0x3A, 0xEC, 0xE6, 0x36, 0xCF, 0x4C, 0xFE, 0x35, 0xE4, 0xE3,
+	0xFE, 0x0A, 0xA3, 0xE0, 0xE2, 0x3F, 0xE4, 0xD8, 0x34, 0xF3, 0xEF, 0xFD, 0xA1, 0x1F, 0xFF, 0x00,
+	0x18, 0xAC, 0x1F, 0xF8, 0x2B, 0x6B, 0x0F, 0xF8, 0x5E, 0xBE, 0x1F, 0xE7, 0xFE, 0x65, 0x91, 0xFF,
+	0x00, 0xA5, 0x0F, 0x5F, 0x2A, 0xD0, 0x07, 0xE8, 0x57, 0xEC, 0xBF, 0xFB, 0x75, 0x78, 0x77, 0xE3,
+	0xC7, 0xC5, 0xEB, 0x4F, 0x87, 0xBA, 0x5F, 0xC1, 0x0B, 0x3D, 0x0E, 0x6B, 0x8B, 0x59, 0xE6, 0x1A,
+	0x84, 0x37, 0x48, 0xCC, 0xA2, 0x34, 0xDD, 0xB4, 0x01, 0x12, 0xF5, 0xE9, 0xD6, 0xB9, 0xBF, 0x8A,
+	0xBF, 0xF0, 0x51, 0xEF, 0x0C, 0x7C, 0x37, 0xF8, 0x97, 0xAF, 0xF8, 0x0A, 0xEB, 0xF6, 0x7C, 0xB3,
+	0xD4, 0x24, 0xD2, 0x75, 0x69, 0xED, 0x64, 0xBE, 0x6B, 0xE4, 0x56, 0x9C, 0xA3, 0xE3, 0x71, 0x1E,
+	0x51, 0xEB, 0xF5, 0x35, 0xE3, 0x3F, 0xF0, 0x4C, 0xD3, 0xFF, 0x00, 0x19, 0x61, 0xA5, 0xE4, 0xFF,
+	0x00, 0xCC, 0x2E, 0xFB, 0xAF, 0xFD, 0x70, 0x6A, 0xF3, 0xDF, 0xDA, 0xA4, 0xE7, 0xF6, 0x94, 0xF1,
+	0xD0, 0xCF, 0xFC, 0xCC, 0xF7, 0x5F, 0xFA, 0x1D, 0x2F, 0xB4, 0x0B, 0xE1, 0xB9, 0xF4, 0x50, 0xFF,
+	0x00, 0x82, 0xA9, 0x78, 0x38, 0xF0, 0x3F, 0x66, 0x0D, 0x3C, 0x7B, 0xFF, 0x00, 0x68, 0x47, 0xFF,
+	0x00, 0xC6, 0x2B, 0xD8, 0xBF, 0x67, 0xBF, 0xDA, 0xD3, 0x45, 0xF8, 0xCF, 0xF0, 0x9B, 0xC6, 0xDE,
+	0x3D, 0xD3, 0x7E, 0x14, 0x5B, 0x68, 0xD1, 0x78, 0x6A, 0xD1, 0xA4, 0x9A, 0xC6, 0x1B, 0x84, 0x61,
+	0x77, 0xFB, 0x97, 0x93, 0x04, 0x88, 0xD4, 0x7F, 0x06, 0xDE, 0x87, 0xAD, 0x7E, 0x6A, 0x93, 0x81,
+	0x93, 0x5F, 0x60, 0x7F, 0xC1, 0x3F, 0xBF, 0xE4, 0xD7, 0xFE, 0x31, 0x2E, 0x79, 0xFE, 0xCF, 0x6E,
+	0xFF, 0x00, 0xF4, 0xE9, 0x71, 0x44, 0xB6, 0x08, 0xFC, 0x56, 0x2C, 0x2F, 0xFC, 0x15, 0x53, 0xC2,
+	0x05, 0x46, 0x7F, 0x66, 0x3B, 0x0F, 0x5C, 0x7F, 0x69, 0x47, 0xFF, 0x00, 0xC6, 0x28, 0x3F, 0xF0,
+	0x54, 0xFF, 0x00, 0x06, 0x30, 0xC3, 0x7E, 0xCC, 0x1A, 0x7F, 0xFE, 0x0C, 0x22, 0xFF, 0x00, 0xE3,
+	0x15, 0xF1, 0xAC, 0x67, 0x74, 0x6A, 0x47, 0xF7, 0x7F, 0xA0, 0xA7, 0x53, 0x03, 0xF4, 0x63, 0xE3,
+	0x07, 0xED, 0x6F, 0xA3, 0xF8, 0x4B, 0xF6, 0x4A, 0xF0, 0xCF, 0xC7, 0x99, 0x7E, 0x0F, 0xD8, 0xDE,
+	0xDB, 0xEB, 0x57, 0xD1, 0xC5, 0x0E, 0x83, 0x3C, 0xCB, 0xE5, 0xDB, 0x13, 0xE6, 0x8D, 0xC0, 0xF9,
+	0x78, 0xC8, 0xF2, 0xFD, 0x07, 0xDE, 0x3C, 0xD7, 0x80, 0x8F, 0xF8, 0x2A, 0x1F, 0x84, 0xD5, 0xB8,
+	0xFD, 0x96, 0xF4, 0x3F, 0x4F, 0xF8, 0xFA, 0x4F, 0xFE, 0x33, 0x5A, 0x7F, 0xB4, 0x91, 0x27, 0xFE,
+	0x09, 0x7F, 0xF0, 0xDD, 0x01, 0x1F, 0xF2, 0x16, 0x83, 0xBF, 0xFB, 0x57, 0x55, 0xF1, 0x71, 0x23,
+	0xAE, 0x6B, 0xE0, 0xB8, 0x8B, 0x34, 0xC5, 0xE0, 0xF1, 0xFE, 0xCE, 0x93, 0xB2, 0xB2, 0xE8, 0xBA,
+	0xFC, 0x8F, 0xE8, 0x6F, 0x0C, 0x38, 0x47, 0x25, 0xCF, 0x38, 0x79, 0xD7, 0xC5, 0xC1, 0xCA, 0x5C,
+	0xED, 0x5D, 0x49, 0xAD, 0x15, 0xAD, 0xA2, 0x69, 0x1F, 0x75, 0x7C, 0x08, 0xFF, 0x00, 0x82, 0x86,
+	0x78, 0x67, 0xE2, 0x3F, 0xC6, 0x3F, 0x0E, 0xF8, 0x12, 0xDF, 0xF6, 0x77, 0xD1, 0xF4, 0xD9, 0x35,
+	0x5D, 0x44, 0x40, 0xBA, 0x84, 0x33, 0xA3, 0x3C, 0x04, 0xAB, 0x1D, 0xC3, 0xF7, 0x43, 0xD3, 0xD6,
+	0xBD, 0x07, 0xF6, 0x9C, 0xFD, 0xBB, 0x7C, 0x3B, 0xF0, 0x1F, 0xE3, 0x1D, 0xF7, 0xC3, 0x9D, 0x43,
+	0xE0, 0x7D, 0xA6, 0xB9, 0x35, 0xAD, 0xBD, 0xB4, 0xBF, 0xDA, 0x12, 0x5E, 0x24, 0x6C, 0xFE, 0x64,
+	0x61, 0xB1, 0x83, 0x13, 0x74, 0xCE, 0x3A, 0xD7, 0xC3, 0xFF, 0x00, 0xB1, 0xA9, 0x1F, 0xF0, 0xD4,
+	0xDE, 0x06, 0xF9, 0x80, 0xFF, 0x00, 0x89, 0xE0, 0xFF, 0x00, 0xD1, 0x6F, 0x5E, 0xA9, 0xFF, 0x00,
+	0x05, 0x2A, 0xC9, 0xFD, 0xAC, 0xB5, 0xB6, 0xF9, 0xBF, 0xE4, 0x17, 0xA7, 0xED, 0x6D, 0xBF, 0xF4,
+	0xC0, 0x7E, 0xB5, 0xEC, 0xF0, 0xDE, 0x32, 0xBE, 0x33, 0x0B, 0x39, 0x56, 0x77, 0xB3, 0xE8, 0xAD,
+	0xD3, 0xD0, 0xF8, 0xBF, 0x15, 0x32, 0x4C, 0xBF, 0x21, 0xCE, 0x29, 0x51, 0xC2, 0x26, 0xA3, 0x28,
+	0x5D, 0xDD, 0xB7, 0xAD, 0xFB, 0xBB, 0x9F, 0xCF, 0xFF, 0x00, 0xED, 0xD7, 0x75, 0x15, 0xF7, 0xED,
+	0xA5, 0xF1, 0x63, 0x53, 0xB4, 0xD2, 0x85, 0x8D, 0xBD, 0xEF, 0xC4, 0x4D, 0x62, 0xEA, 0xD6, 0xCD,
+	0x64, 0xDC, 0xB0, 0x43, 0x2D, 0xE4, 0xB2, 0x46, 0x80, 0x80, 0x01, 0xC2, 0x30, 0x19, 0xC5, 0x79,
+	0x34, 0xD0, 0xAD, 0xC4, 0x12, 0x5B, 0x39, 0xC2, 0xC8, 0xA5, 0x4F, 0xE3, 0x5E, 0xFF, 0x00, 0xFF,
+	0x00, 0x05, 0x37, 0xF0, 0xB1, 0xF0, 0xB7, 0xED, 0x9B, 0xE2, 0xA6, 0x8E, 0x3D, 0xB0, 0xEA, 0x89,
+	0x69, 0xA8, 0x5B, 0x8C, 0x71, 0x89, 0x2D, 0xE3, 0x0E, 0x47, 0xD6, 0x54, 0x90, 0xFE, 0x35, 0xE0,
+	0x55, 0xED, 0x4B, 0x73, 0xE0, 0xE3, 0xEF, 0x53, 0x47, 0xAF, 0x7E, 0xDB, 0x5F, 0xB6, 0x17, 0x8C,
+	0xBF, 0x6E, 0x3F, 0x8D, 0x71, 0xFC, 0x70, 0xF1, 0xDF, 0x84, 0x74, 0xBD, 0x16, 0xFE, 0x3F, 0x0D,
+	0xE9, 0xBA, 0x38, 0xB3, 0xD2, 0x24, 0x91, 0xA1, 0x68, 0xEC, 0xED, 0x92, 0xDD, 0x1C, 0x99, 0x09,
+	0x6D, 0xCC, 0xA8, 0x09, 0xE4, 0x8C, 0x93, 0x8C, 0x57, 0x90, 0x86, 0x00, 0xE7, 0xF1, 0xA2, 0x8A,
+	0x91, 0xA5, 0xCB, 0xB1, 0xF5, 0x87, 0x83, 0x3F, 0x61, 0x3F, 0x85, 0x5E, 0x21, 0xFF, 0x00, 0x82,
+	0x6B, 0x78, 0x27, 0xF6, 0xC5, 0xB9, 0xD7, 0xB5, 0x85, 0xF1, 0x27, 0x89, 0x3F, 0x68, 0x88, 0x3C,
+	0x05, 0x79, 0x63, 0x1C, 0x88, 0x2D, 0x23, 0xD3, 0xDE, 0xD2, 0x69, 0x4C, 0xA8, 0xBB, 0x77, 0x09,
+	0x77, 0x46, 0xBC, 0x92, 0x47, 0x5E, 0x0D, 0x7A, 0xD7, 0xC6, 0x4F, 0xF8, 0x25, 0x07, 0xC0, 0x2F,
+	0x87, 0xBE, 0x3C, 0xFD, 0xB8, 0x7C, 0x3D, 0xA1, 0xF8, 0xA7, 0xC4, 0x6D, 0x0F, 0xEC, 0xDB, 0xA2,
+	0xE8, 0x17, 0x9E, 0x07, 0x6B, 0x8B, 0x88, 0xD9, 0xAE, 0x9E, 0xF9, 0x98, 0x48, 0x2E, 0xF0, 0x80,
+	0x38, 0x01, 0x46, 0x36, 0x2A, 0x77, 0xEB, 0x5A, 0x5F, 0x0A, 0xFF, 0x00, 0xE5, 0x04, 0x5F, 0x0A,
+	0x3F, 0xEC, 0xF7, 0x6C, 0xFF, 0x00, 0xF4, 0xDD, 0x77, 0x5F, 0x47, 0x7E, 0xD4, 0x1F, 0xF2, 0x56,
+	0xFF, 0x00, 0xE0, 0xAD, 0x1F, 0xF6, 0x2A, 0xF8, 0x33, 0xFF, 0x00, 0x43, 0x7A, 0xBE, 0x54, 0x61,
+	0x29, 0x49, 0x7F, 0x5E, 0x87, 0x81, 0xFC, 0x19, 0xFF, 0x00, 0x82, 0x36, 0xFE, 0xCE, 0x3F, 0x10,
+	0xBF, 0x6D, 0x7F, 0xD9, 0x9F, 0xF6, 0x74, 0xD5, 0xBC, 0x63, 0xE2, 0x88, 0xF4, 0x5F, 0x8C, 0xDF,
+	0x02, 0x57, 0xC6, 0xBE, 0x22, 0xB8, 0x8E, 0xF2, 0x2F, 0xB4, 0x5B, 0xDF, 0x1B, 0x36, 0x98, 0x47,
+	0x09, 0x31, 0xE0, 0x45, 0xBD, 0x47, 0xCA, 0x72, 0x71, 0x9E, 0x45, 0x78, 0x8F, 0xC1, 0xBF, 0xD8,
+	0x07, 0xE1, 0x1F, 0xC4, 0x5F, 0xD8, 0xFB, 0xE0, 0x0F, 0xC7, 0xCD, 0x63, 0x5D, 0xD6, 0xA3, 0xD5,
+	0xFE, 0x29, 0x7E, 0xD1, 0x96, 0xFE, 0x00, 0xD7, 0xA1, 0x8E, 0x64, 0xF2, 0x62, 0xD3, 0xDE, 0x4B,
+	0x55, 0x32, 0xC4, 0xA5, 0x49, 0x59, 0xBF, 0x7F, 0x26, 0x0B, 0x33, 0x2E, 0x76, 0xF0, 0x31, 0x5F,
+	0xA5, 0x1F, 0xB2, 0xDF, 0xFC, 0xA5, 0x63, 0xF6, 0x09, 0xFF, 0x00, 0xB3, 0x41, 0x8F, 0xFF, 0x00,
+	0x4D, 0xB2, 0x57, 0xC9, 0xBF, 0xB2, 0xDF, 0xFC, 0xA3, 0x2B, 0xF6, 0x35, 0xFF, 0x00, 0xB3, 0xE4,
+	0xB3, 0xFF, 0x00, 0xD2, 0x8D, 0x3E, 0x99, 0x3E, 0xD2, 0x5A, 0x1C, 0x0F, 0xC6, 0x9F, 0xF8, 0x25,
+	0xBF, 0xC0, 0xCF, 0x87, 0x5A, 0x1F, 0xED, 0xA9, 0xA9, 0xE8, 0xFE, 0x2C, 0xF1, 0x1C, 0xD2, 0x7E,
+	0xCE, 0x5A, 0xF6, 0x97, 0x63, 0xE0, 0xF5, 0x9E, 0xE2, 0x33, 0xF6, 0xD8, 0xEE, 0xAE, 0x56, 0x29,
+	0x1A, 0xE8, 0xED, 0xCB, 0xB0, 0x56, 0xE3, 0x6E, 0xDC, 0x11, 0x5D, 0x26, 0x8F, 0xFF, 0x00, 0x04,
+	0x89, 0xFD, 0x9E, 0x2F, 0xBF, 0x6D, 0x4F, 0x86, 0x5F, 0xB3, 0xAC, 0xDE, 0x2B, 0xF1, 0x31, 0xD1,
+	0xFC, 0x67, 0xFB, 0x21, 0xC3, 0xF1, 0x53, 0x50, 0xBA, 0x17, 0x51, 0x09, 0xE1, 0xD5, 0xDE, 0xD6,
+	0xF2, 0x5F, 0x29, 0x09, 0x42, 0x3C, 0x8C, 0xDB, 0xC7, 0xF2, 0x90, 0x5B, 0x1B, 0xB9, 0x19, 0xAF,
+	0x72, 0xFD, 0xAA, 0x7F, 0xE4, 0x57, 0xFF, 0x00, 0x82, 0xAC, 0x7F, 0xD8, 0xE1, 0xE1, 0xEF, 0xFD,
+	0x2D, 0x8E, 0xBB, 0x9F, 0x0D, 0xFF, 0x00, 0xCA, 0x55, 0x3E, 0x01, 0xFF, 0x00, 0xDA, 0x33, 0xAC,
+	0xFF, 0x00, 0xF4, 0xDD, 0xA9, 0xD0, 0xE3, 0x64, 0x83, 0xDA, 0x4C, 0xF8, 0x6B, 0xE1, 0x7F, 0xFC,
+	0x13, 0x47, 0xE0, 0xA7, 0x8D, 0xFF, 0x00, 0x66, 0xEF, 0xD9, 0x5F, 0xE3, 0x16, 0xA3, 0xE2, 0x5D,
+	0x76, 0x3D, 0x43, 0xE3, 0x87, 0xC6, 0x9D, 0x4B, 0xC2, 0x5E, 0x26, 0x82, 0x39, 0xA3, 0xF2, 0xED,
+	0x6C, 0x6D, 0xEE, 0xA6, 0x86, 0x37, 0x80, 0x32, 0x31, 0x59, 0x30, 0x8A, 0x58, 0xB1, 0x60, 0x79,
+	0xC0, 0x14, 0xDF, 0x8B, 0xDF, 0xF0, 0x4D, 0xFF, 0x00, 0x82, 0xFF, 0x00, 0x0C, 0xBE, 0x0A, 0x7E,
+	0xD9, 0x5F, 0x14, 0x74, 0x7F, 0x10, 0x6B, 0xD3, 0x5F, 0x7E, 0xCE, 0x7F, 0x16, 0xB4, 0xEF, 0x0E,
+	0xF8, 0x36, 0x19, 0xEE, 0x90, 0xC7, 0x79, 0x6B, 0x2E, 0xA7, 0x35, 0xA3, 0x35, 0xC0, 0x08, 0x09,
+	0x93, 0x64, 0x4A, 0x77, 0x2B, 0x28, 0xCE, 0x6B, 0xE8, 0xDF, 0xD9, 0xF8, 0x13, 0xFB, 0x0A, 0xFF,
+	0x00, 0xC1, 0x3B, 0xF1, 0xFF, 0x00, 0x47, 0x4D, 0xAE, 0xFF, 0x00, 0xE9, 0xC6, 0xE2, 0xAB, 0x7E,
+	0xD4, 0xDF, 0xF2, 0x69, 0x5F, 0xF0, 0x54, 0xCE, 0x3F, 0xE6, 0xE2, 0xB4, 0x6F, 0xFD, 0x3F, 0xDD,
+	0x50, 0x1C, 0xD2, 0x37, 0x3F, 0x6C, 0xAF, 0xD8, 0x67, 0xE1, 0x97, 0xED, 0xA9, 0xFF, 0x00, 0x05,
+	0x65, 0xF1, 0x16, 0x9F, 0xF1, 0x2F, 0x5E, 0xD5, 0xAC, 0x52, 0xEB, 0xF6, 0x51, 0xD3, 0xFC, 0x74,
+	0x5B, 0x49, 0x95, 0x17, 0x1A, 0x85, 0x9E, 0x93, 0x6D, 0x14, 0x71, 0x8D, 0xEA, 0xC7, 0xC9, 0x22,
+	0x25, 0xDC, 0xB9, 0xDC, 0x79, 0xC1, 0x1D, 0xFE, 0x65, 0xF8, 0x51, 0xFF, 0x00, 0x04, 0xD1, 0xF8,
+	0x23, 0xE3, 0x3F, 0x06, 0x7E, 0xC3, 0xBE, 0x22, 0xD5, 0x3C, 0x45, 0xE2, 0x04, 0x9B, 0xF6, 0x94,
+	0xF1, 0x86, 0xAD, 0xA5, 0x78, 0xD5, 0x61, 0xBA, 0x8D, 0x56, 0xD2, 0x1B, 0x5B, 0xFB, 0x1B, 0x78,
+	0xCD, 0xB0, 0x28, 0x4A, 0x31, 0x4B, 0x89, 0x32, 0x5C, 0xBF, 0xF0, 0xE3, 0x15, 0xFA, 0x0D, 0x39,
+	0xCF, 0xFC, 0x15, 0xCB, 0x56, 0xFF, 0x00, 0xB3, 0x00, 0xFF, 0x00, 0xDC, 0x7C, 0x75, 0xE0, 0xBF,
+	0xB3, 0xD1, 0x27, 0xE1, 0x77, 0xFC, 0x12, 0x54, 0x7F, 0xD5, 0x4C, 0xF1, 0x1F, 0xFE, 0x9D, 0xF4,
+	0x9A, 0x39, 0x7D, 0xD2, 0x63, 0x39, 0x28, 0x9E, 0x49, 0xE0, 0x3F, 0x84, 0x7E, 0x17, 0xFD, 0x8F,
+	0xFF, 0x00, 0x61, 0x3F, 0xDB, 0x73, 0xC7, 0xBE, 0x04, 0x37, 0x5A, 0x85, 0xC4, 0x3F, 0x10, 0x23,
+	0xF8, 0x39, 0x0A, 0x6A, 0x97, 0x19, 0x54, 0xD1, 0xE6, 0xB8, 0x49, 0x0D, 0xD7, 0xC8, 0x06, 0xEB,
+	0x95, 0x68, 0x86, 0xD3, 0x90, 0x9C, 0xF2, 0x3B, 0x8F, 0x8C, 0xFF, 0x00, 0x62, 0xE6, 0xCF, 0xED,
+	0x8B, 0xF0, 0x94, 0xFF, 0x00, 0xD5, 0x4C, 0xD0, 0x3A, 0x93, 0xC7, 0xFC, 0x4C, 0x60, 0xE9, 0xFA,
+	0xFB, 0xFE, 0x00, 0x57, 0xDE, 0xBF, 0x1E, 0xBF, 0xE5, 0x1B, 0x1F, 0xB7, 0x07, 0xFD, 0x9E, 0x4D,
+	0x9F, 0xFE, 0x8D, 0x6A, 0xF8, 0x27, 0xF6, 0x2D, 0xFF, 0x00, 0x93, 0xC6, 0xF8, 0x4B, 0xFF, 0x00,
+	0x65, 0x33, 0x40, 0xFF, 0x00, 0xD3, 0x8C, 0x15, 0x3F, 0x0D, 0x8D, 0xA1, 0x76, 0x9B, 0x3D, 0x47,
+	0xFE, 0x0B, 0x41, 0xB7, 0xFE, 0x1E, 0xB9, 0xF1, 0xF3, 0x3F, 0xF4, 0x50, 0xEE, 0x7F, 0xF4, 0x5C,
+	0x55, 0xE9, 0x3E, 0x06, 0xB3, 0xB6, 0xBE, 0xFF, 0x00, 0x83, 0x7D, 0xFC, 0x5C, 0xB2, 0x96, 0x56,
+	0xFF, 0x00, 0x86, 0x9D, 0xD1, 0x63, 0xFC, 0x1B, 0x4C, 0x9D, 0x7F, 0x96, 0x7F, 0xCF, 0x15, 0xE6,
+	0xBF, 0xF0, 0x5A, 0x1F, 0xF9, 0x4A, 0xE7, 0xC7, 0xCF, 0xFB, 0x28, 0x57, 0x3F, 0xFA, 0x2E, 0x3A,
+	0xF4, 0xEF, 0x87, 0x99, 0xFF, 0x00, 0x88, 0x7F, 0x3C, 0x5B, 0xFF, 0x00, 0x67, 0x45, 0xA0, 0xFF,
+	0x00, 0xE9, 0xBA, 0xE2, 0x88, 0xFC, 0x4C, 0xA9, 0x69, 0x04, 0x77, 0xDF, 0x1C, 0xBF, 0xE0, 0x8F,
+	0x5F, 0xB3, 0x9F, 0xC3, 0x4F, 0xDA, 0xB7, 0xF6, 0xB1, 0xF8, 0x15, 0xA2, 0xF8, 0xBF, 0xC5, 0x12,
+	0xE9, 0x7F, 0x02, 0xFE, 0x0E, 0xD9, 0xF8, 0xB3, 0xC2, 0xB7, 0x17, 0x17, 0x51, 0x34, 0xD7, 0x57,
+	0x93, 0xC3, 0x6C, 0xEC, 0x97, 0x04, 0x22, 0x86, 0x40, 0x66, 0x60, 0x02, 0x85, 0x38, 0x0B, 0xC9,
+	0xC1, 0xA7, 0x7E, 0xCF, 0x1F, 0xF0, 0x4A, 0x3F, 0x80, 0x5A, 0xEF, 0xED, 0x19, 0xFB, 0x11, 0xE8,
+	0x57, 0x9E, 0x2C, 0xF1, 0x30, 0x87, 0xE3, 0xA7, 0x82, 0x6E, 0x3C, 0x57, 0xE2, 0xA6, 0x4B, 0xA8,
+	0x77, 0x5B, 0x5D, 0x5A, 0x14, 0x92, 0x24, 0xB7, 0x3E, 0x5E, 0x11, 0x09, 0xEB, 0x90, 0xC7, 0xDF,
+	0xBD, 0x7D, 0x63, 0xFB, 0x5A, 0x67, 0xFE, 0x1E, 0x35, 0xFF, 0x00, 0x05, 0x1C, 0x27, 0xFE, 0x8D,
+	0x87, 0x4A, 0xFF, 0x00, 0xD2, 0x6B, 0x1A, 0xCD, 0xFD, 0x97, 0xCE, 0x3F, 0x6A, 0x9F, 0xF8, 0x25,
+	0xB9, 0xFF, 0x00, 0xAA, 0x17, 0xAB, 0xFF, 0x00, 0xE8, 0xB4, 0xAD, 0x39, 0x4C, 0x65, 0x29, 0x7F,
+	0x5E, 0x87, 0xC7, 0xDF, 0xB4, 0x57, 0xC2, 0xBF, 0x09, 0x7E, 0xDF, 0x5F, 0x05, 0x7C, 0x41, 0xFF,
+	0x00, 0x05, 0x4A, 0xF8, 0x87, 0x0D, 0xC6, 0x87, 0xE3, 0x2F, 0x1A, 0x7E, 0xD6, 0x16, 0x7F, 0x0F,
+	0xEF, 0xB4, 0x3D, 0x16, 0xE8, 0x9D, 0x36, 0x0D, 0x37, 0xEC, 0x1A, 0x78, 0xF3, 0x51, 0x64, 0x06,
+	0x41, 0x36, 0x64, 0x63, 0xBB, 0x76, 0xDE, 0x83, 0x6F, 0x61, 0x37, 0xC6, 0x3F, 0xF8, 0x24, 0xCF,
+	0xC0, 0x1F, 0x87, 0x5F, 0x14, 0xBF, 0x6D, 0x2F, 0x05, 0x68, 0xFE, 0x2A, 0xF1, 0x24, 0xD6, 0xBF,
+	0xB3, 0xAF, 0x81, 0x6C, 0xF5, 0xAF, 0x07, 0xC9, 0x71, 0x73, 0x11, 0x92, 0xF2, 0xE2, 0x58, 0x62,
+	0x67, 0x5B, 0xA2, 0x10, 0x07, 0x4C, 0xB1, 0xFB, 0x81, 0x4E, 0x3B, 0x9A, 0xDE, 0xF8, 0x35, 0xFF,
+	0x00, 0x28, 0x5B, 0xD3, 0x3F, 0xED, 0x21, 0x16, 0x7F, 0xFA, 0x43, 0xA5, 0xD7, 0xD0, 0xFF, 0x00,
+	0xB5, 0x1F, 0xFC, 0x9C, 0x17, 0xFC, 0x15, 0x4F, 0xFE, 0xC9, 0x16, 0x9B, 0xFF, 0x00, 0xA4, 0xF0,
+	0x52, 0xD0, 0x23, 0x29, 0x5C, 0xF9, 0x93, 0xC1, 0x5F, 0xF0, 0x48, 0xEF, 0xD9, 0xF7, 0xC5, 0x3F,
+	0xB5, 0xF7, 0xEC, 0xCD, 0xF0, 0x02, 0xEF, 0xC5, 0x9E, 0x25, 0x5D, 0x27, 0xE3, 0x27, 0xEC, 0xFF,
+	0x00, 0x2F, 0x8E, 0xBC, 0x49, 0x73, 0x1D, 0xE4, 0x42, 0x68, 0x35, 0x01, 0x61, 0xA9, 0x5C, 0xF9,
+	0x70, 0x1F, 0x28, 0x85, 0x88, 0xB5, 0x9C, 0x4B, 0x86, 0x0C, 0x71, 0xBB, 0xA6, 0x41, 0xAF, 0x33,
+	0xF0, 0xDF, 0xFC, 0x13, 0xCF, 0xE1, 0x0E, 0xB1, 0xFB, 0x0D, 0xFC, 0x29, 0xFD, 0xA5, 0x6E, 0x3C,
+	0x47, 0xAD, 0x7F, 0x6D, 0x78, 0xEF, 0xF6, 0x91, 0x9B, 0xE1, 0xFE, 0xAD, 0x69, 0xE7, 0x2F, 0xD9,
+	0xE2, 0xD3, 0x90, 0xCD, 0x89, 0x63, 0x18, 0x2C, 0x26, 0xF9, 0x06, 0x49, 0x62, 0xBC, 0x7D, 0xDE,
+	0xD5, 0xF7, 0xBF, 0xC1, 0xF1, 0x8F, 0xF8, 0x29, 0x8F, 0xEC, 0x11, 0xFF, 0x00, 0x66, 0x5F, 0x37,
+	0xFE, 0x99, 0xF5, 0xDA, 0xF0, 0x3F, 0x03, 0x7F, 0xCA, 0x24, 0x7F, 0x67, 0x3F, 0xFB, 0x3E, 0x7B,
+	0xBF, 0xE7, 0x75, 0x4A, 0x31, 0x1C, 0x65, 0x2B, 0x9E, 0x6D, 0xF1, 0x87, 0xFE, 0x09, 0x6B, 0xF0,
+	0x23, 0xE1, 0xFD, 0xBF, 0xED, 0xD1, 0x73, 0xA2, 0xF8, 0x9F, 0xC4, 0x6D, 0xFF, 0x00, 0x0C, 0xCF,
+	0xA9, 0xE8, 0x10, 0x78, 0x21, 0x67, 0xBA, 0x8D, 0x8D, 0xE2, 0xDF, 0x5C, 0xF9, 0x52, 0x7D, 0xA8,
+	0x84, 0x01, 0xF0, 0xA3, 0x00, 0x20, 0x41, 0xEB, 0x9A, 0xED, 0x3E, 0x1B, 0x7F, 0xC1, 0x1A, 0xFF,
+	0x00, 0x67, 0x4F, 0x18, 0x7E, 0xDD, 0x3F, 0x08, 0x7F, 0x66, 0x6D, 0x43, 0xC6, 0xBE, 0x2A, 0x8F,
+	0x43, 0xF8, 0x81, 0xFB, 0x38, 0xC3, 0xF1, 0x03, 0x56, 0xBA, 0x86, 0xEA, 0x2F, 0xB4, 0x47, 0xA8,
+	0x3D, 0x87, 0xDA, 0x3C, 0xA8, 0xC9, 0x8C, 0x81, 0x16, 0xFC, 0xF0, 0x72, 0x70, 0x7A, 0x8A, 0xF6,
+	0x5F, 0xDA, 0x77, 0xFE, 0x41, 0xDF, 0xF0, 0x57, 0x1F, 0xFB, 0x0E, 0x78, 0x2F, 0xFF, 0x00, 0x4B,
+	0xCD, 0x7A, 0xBF, 0xC0, 0x93, 0x8F, 0xF8, 0x2B, 0xB7, 0xEC, 0xCB, 0xFF, 0x00, 0x66, 0x31, 0x6B,
+	0xFF, 0x00, 0xA6, 0x71, 0x47, 0x28, 0xBD, 0xA4, 0xCF, 0xCE, 0x1F, 0x83, 0x1F, 0xF0, 0x4F, 0x0F,
+	0x83, 0x9F, 0x11, 0xFF, 0x00, 0x67, 0x9F, 0xD9, 0x3F, 0xE2, 0xBE, 0xB1, 0xAE, 0xEB, 0x51, 0x6A,
+	0x1F, 0x1D, 0x3E, 0x3F, 0x27, 0x81, 0xFC, 0x56, 0xB0, 0xCE, 0x9E, 0x4D, 0xB5, 0x83, 0x5F, 0x59,
+	0xC1, 0xBE, 0xDD, 0x19, 0x58, 0xAC, 0x85, 0x6E, 0x24, 0xE5, 0x8B, 0x0D, 0xC4, 0x1C, 0x0C, 0x56,
+	0xE7, 0xC6, 0x0F, 0xF8, 0x26, 0x47, 0xC1, 0x0F, 0x87, 0x7F, 0x0A, 0xFF, 0x00, 0x6C, 0x5F, 0x1C,
+	0x68, 0xFE, 0x28, 0xF1, 0x04, 0x97, 0x5F, 0xB3, 0xDF, 0xC4, 0xAD, 0x3B, 0xC3, 0xDE, 0x11, 0x5B,
+	0x89, 0xA3, 0x65, 0xBB, 0xB7, 0x9E, 0xE5, 0xA3, 0x66, 0xB9, 0xC0, 0x05, 0x9C, 0x28, 0x18, 0x2A,
+	0x53, 0x07, 0x3D, 0x45, 0x7B, 0x07, 0xEC, 0xAB, 0xFF, 0x00, 0x26, 0x53, 0xFF, 0x00, 0x04, 0xE5,
+	0xFF, 0x00, 0xB3, 0xCA, 0xB7, 0xFF, 0x00, 0xD3, 0xB6, 0x97, 0x5D, 0x77, 0xED, 0x43, 0xFF, 0x00,
+	0x26, 0xEB, 0xFF, 0x00, 0x05, 0x3F, 0xFF, 0x00, 0xB2, 0xF3, 0xA3, 0x7F, 0xE9, 0x73, 0xD0, 0x1E,
+	0xD2, 0x57, 0xFE, 0xBB, 0x9F, 0x0B, 0xFF, 0x00, 0xC1, 0x4E, 0xFF, 0x00, 0x64, 0x4F, 0x87, 0x7F,
+	0xB1, 0x8F, 0xC6, 0x4F, 0x03, 0xFC, 0x3E, 0xF8, 0x6B, 0xAA, 0xEA, 0x97, 0x96, 0xBE, 0x24, 0xF8,
+	0x37, 0xE1, 0xCF, 0x15, 0xDE, 0xCB, 0xAB, 0x4C, 0xB2, 0x4A, 0x97, 0x77, 0xF1, 0xCC, 0xD2, 0xC6,
+	0x0A, 0xAA, 0x8F, 0x2D, 0x4C, 0x63, 0x68, 0xC6, 0x46, 0x4E, 0x49, 0xAF, 0x2F, 0xFD, 0x94, 0xFF,
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+	0x00, 0x27, 0x83, 0xE2, 0xA6, 0x3F, 0xDD, 0xB4, 0xFF, 0x00, 0xD2, 0x74, 0xAE, 0xBB, 0x73, 0x6E,
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+	0x6F, 0x8C, 0x5F, 0x03, 0xBC, 0x6D, 0xF1, 0x3A, 0xC3, 0xE1, 0x36, 0x9F, 0xA1, 0xC5, 0xE1, 0xA6,
+	0xB8, 0x33, 0x69, 0x76, 0x2C, 0x9B, 0x2F, 0x76, 0x5A, 0x89, 0xFE, 0x63, 0xB0, 0x75, 0x07, 0x6F,
+	0x22, 0xBF, 0x30, 0x41, 0xC9, 0xF9, 0x7F, 0x4A, 0xFB, 0x73, 0xFE, 0x09, 0xCB, 0xF2, 0xFE, 0xC6,
+	0xDF, 0x18, 0x83, 0x0C, 0x7C, 0xB7, 0xBD, 0x7F, 0xEC, 0x16, 0x28, 0xE5, 0x8A, 0x35, 0xAD, 0x4E,
+	0x31, 0xA7, 0x72, 0x45, 0xFF, 0x00, 0x82, 0xA9, 0x78, 0x43, 0x0A, 0xAD, 0xFB, 0x30, 0x69, 0xFD,
+	0x3A, 0x7F, 0x69, 0x47, 0xEB, 0xFF, 0x00, 0x5C, 0x28, 0x1F, 0xF0, 0x55, 0x1F, 0x06, 0xFF, 0x00,
+	0xD1, 0xAF, 0x69, 0xFF, 0x00, 0xF8, 0x32, 0x88, 0x7F, 0xED, 0xBD, 0x7C, 0x6C, 0xBC, 0xAA, 0xB0,
+	0xE8, 0x53, 0x3F, 0xA9, 0xA5, 0x4C, 0x93, 0xC0, 0x27, 0xBF, 0x02, 0x99, 0xC8, 0x7E, 0x8D, 0x78,
+	0x83, 0xF6, 0xC5, 0xD0, 0xB4, 0x3F, 0xD9, 0x53, 0x45, 0xFD, 0xA2, 0x8F, 0xC2, 0x4B, 0x5B, 0x8B,
+	0x7D, 0x5B, 0x5B, 0x6B, 0x65, 0xF0, 0xFF, 0x00, 0xDA, 0x54, 0x47, 0x01, 0x0D, 0x2C, 0x7B, 0x83,
+	0x79, 0x64, 0x67, 0x31, 0x67, 0xEE, 0x8F, 0xBC, 0x6B, 0xCB, 0x7F, 0xE1, 0xEA, 0x5E, 0x10, 0xCE,
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+	0x1F, 0xF0, 0x4B, 0x1F, 0x06, 0x8C, 0xFD, 0xDF, 0x16, 0x49, 0xFF, 0x00, 0xA3, 0xEE, 0x85, 0x7C,
+	0xB6, 0x01, 0xEA, 0x3D, 0xBF, 0x95, 0x00, 0x7D, 0xA5, 0xA2, 0x7F, 0xC1, 0x4F, 0xFC, 0x1F, 0xAC,
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+	0xEE, 0x96, 0xEA, 0x4B, 0xB4, 0x8C, 0xC4, 0x37, 0x32, 0xED, 0xE6, 0x36, 0xCF, 0x4C, 0xD7, 0xE7,
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+	0xFD, 0xA1, 0x1F, 0x1F, 0xF9, 0x02, 0xBD, 0x0B, 0xF6, 0x5E, 0xFD, 0xBA, 0x7C, 0x39, 0xF1, 0xE7,
+	0xE2, 0xFD, 0x9F, 0xC3, 0xDD, 0x33, 0xE0, 0x8D, 0x9E, 0x87, 0x35, 0xC5, 0xAC, 0xF3, 0x7F, 0x68,
+	0x45, 0x74, 0x8C, 0xC8, 0x11, 0x0B, 0x6D, 0xC0, 0x8D, 0x4F, 0x3D, 0x2B, 0xF3, 0xD5, 0x7A, 0x7E,
+	0x55, 0xF4, 0x07, 0xFC, 0x13, 0x37, 0xFE, 0x4E, 0xBB, 0x4B, 0xFF, 0x00, 0xB0, 0x5D, 0xF7, 0xFE,
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+	0x89, 0xFC, 0x4F, 0xAB, 0x7E, 0xD4, 0x7A, 0x65, 0xA6, 0xA5, 0xE2, 0x4D, 0x42, 0xE2, 0x23, 0xA6,
+	0xDE, 0xEE, 0x86, 0x7B, 0xD7, 0x74, 0x6C, 0x40, 0x71, 0xF2, 0x93, 0x8E, 0x0D, 0x70, 0x1F, 0xB5,
+	0x0F, 0x8B, 0xBC, 0x59, 0x67, 0xFB, 0x47, 0xF8, 0xE6, 0xDE, 0xD3, 0xC5, 0x5A, 0x94, 0x71, 0xAF,
+	0x89, 0xAE, 0xD6, 0x38, 0xE3, 0xBE, 0x91, 0x51, 0x17, 0x7F, 0x40, 0x03, 0x7A, 0xFB, 0x77, 0xA0,
+	0x23, 0xF0, 0x9E, 0xD3, 0xFF, 0x00, 0x0E, 0x87, 0xF8, 0xA6, 0x17, 0x71, 0xF8, 0xB9, 0xE1, 0xFF,
+	0x00, 0xFC, 0x17, 0xCD, 0xFE, 0x35, 0xED, 0x5F, 0xB3, 0x8F, 0xEC, 0x6D, 0xE2, 0x9F, 0x81, 0x3F,
+	0x08, 0xBC, 0x75, 0xF0, 0xEF, 0x5A, 0xF1, 0x96, 0x9F, 0x7D, 0x37, 0x8A, 0xAD, 0x5E, 0x1B, 0x7B,
+	0x8B, 0x3B, 0x79, 0x11, 0x60, 0x3E, 0x44, 0x91, 0xE5, 0x83, 0x1C, 0x91, 0x97, 0xCF, 0x15, 0xF9,
+	0xE2, 0x3C, 0x6F, 0xE3, 0x45, 0x3B, 0x87, 0x8B, 0xB5, 0x4E, 0x3F, 0xEA, 0x21, 0x27, 0xF8, 0xD7,
+	0xD6, 0xDF, 0xB0, 0x66, 0xBB, 0xAF, 0x6A, 0x5F, 0xB3, 0x3F, 0xC5, 0xEB, 0x8D, 0x4B, 0x5D, 0xBC,
+	0xB8, 0x92, 0x1D, 0x31, 0xBC, 0xB9, 0x2E, 0x2E, 0x9E, 0x46, 0x8B, 0xFD, 0x0E, 0x7C, 0x95, 0x24,
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+	0x17, 0xF4, 0x16, 0xDA, 0x32, 0x4F, 0xD8, 0x27, 0xE5, 0x8F, 0x04, 0xFE, 0x82, 0x95, 0xBF, 0xE0,
+	0x91, 0x3F, 0x14, 0x50, 0x65, 0xFE, 0x2D, 0xF8, 0x7F, 0x1F, 0xF6, 0x0F, 0x9F, 0xD3, 0xEB, 0x5F,
+	0x2C, 0xC5, 0xE3, 0x6F, 0x1A, 0x79, 0x4A, 0x3F, 0xE1, 0x30, 0xD5, 0xBE, 0xE8, 0x2D, 0xBB, 0x51,
+	0x97, 0x93, 0xFF, 0x00, 0x7D, 0x1F, 0xF2, 0x69, 0xCB, 0xE3, 0x7F, 0x1A, 0x29, 0xE3, 0xC5, 0xFA,
+	0xA7, 0xFB, 0x5B, 0x75, 0x29, 0x46, 0x79, 0xF5, 0xC8, 0xC5, 0x00, 0x7D, 0xFF, 0x00, 0xF1, 0x83,
+	0xF6, 0x2F, 0xF1, 0x97, 0x8D, 0x3F, 0x64, 0x2F, 0x0C, 0x7E, 0xCE, 0xFA, 0x77, 0x8C, 0x74, 0xD8,
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+	0xE4, 0x1C, 0xC8, 0x3A, 0xFA, 0x1A, 0xF9, 0xEF, 0xFE, 0x1D, 0x17, 0xF1, 0x95, 0xDB, 0x0B, 0xF1,
+	0x4B, 0xC3, 0xFE, 0xBF, 0xEA, 0xA5, 0xF4, 0xFA, 0xD7, 0x4B, 0xFB, 0x4A, 0xEA, 0xDA, 0xD3, 0xFF,
+	0x00, 0xC1, 0x31, 0xFE, 0x1F, 0x5F, 0x3E, 0xB1, 0x74, 0xD3, 0xC9, 0xAB, 0x42, 0x24, 0xBA, 0x69,
+	0x98, 0xC8, 0xFC, 0xDD, 0x8E, 0x58, 0xF2, 0x78, 0xF5, 0xF4, 0xAF, 0x8C, 0xBF, 0xB7, 0x75, 0xB2,
+	0x73, 0xFD, 0xB1, 0x79, 0xED, 0xFE, 0x94, 0xE7, 0x8A, 0xF8, 0x6E, 0x21, 0xC4, 0x65, 0xD4, 0xF1,
+	0xDC, 0xB5, 0xE9, 0x39, 0x4A, 0xCB, 0x54, 0xED, 0xF8, 0x1F, 0xBF, 0xF8, 0x67, 0x96, 0xF1, 0x4E,
+	0x2B, 0x87, 0xE5, 0x3C, 0xBF, 0x19, 0x1A, 0x50, 0xE7, 0x7E, 0xEB, 0x87, 0x36, 0xBA, 0x6B, 0x7B,
+	0xAF, 0xB8, 0xFB, 0x5F, 0xE0, 0x27, 0xFC, 0x13, 0x1B, 0xE2, 0x97, 0xC3, 0x0F, 0x8C, 0xBE, 0x1D,
+	0xF8, 0x85, 0xAB, 0xFC, 0x46, 0xD0, 0xEE, 0x2D, 0x74, 0x8D, 0x44, 0x4F, 0x35, 0xBD, 0xBC, 0x72,
+	0x07, 0x91, 0x42, 0xB0, 0xC0, 0xF7, 0xE6, 0xBB, 0xCF, 0xDA, 0xA3, 0xFE, 0x09, 0xED, 0xE3, 0xBF,
+	0xDA, 0x0B, 0xE3, 0x2D, 0xF7, 0xC5, 0x1D, 0x03, 0xE2, 0x16, 0x93, 0xA7, 0xC3, 0x73, 0x6B, 0x6F,
+	0x0A, 0xDA, 0xDE, 0x59, 0xCA, 0xCF, 0x94, 0x8C, 0x2E, 0x72, 0xA7, 0x04, 0x1A, 0xF8, 0xDF, 0xF6,
+	0x38, 0xD6, 0xB5, 0x99, 0x3F, 0x6A, 0x5F, 0x03, 0x23, 0xEA, 0xF7, 0x4C, 0xAD, 0xAE, 0x28, 0x65,
+	0x6B, 0x87, 0xC3, 0x0D, 0x8F, 0xC7, 0x5F, 0xE7, 0x91, 0x5E, 0xAD, 0xFF, 0x00, 0x05, 0x19, 0xF1,
+	0x3F, 0x8A, 0x34, 0x8F, 0xDA, 0xAF, 0x58, 0xB4, 0xD2, 0xFC, 0x47, 0x7D, 0x6B, 0x1F, 0xF6, 0x6D,
+	0x93, 0x08, 0x6D, 0xEF, 0x24, 0x45, 0x04, 0xC0, 0xA4, 0xF0, 0xA4, 0x0C, 0x93, 0x9A, 0xF5, 0xB8,
+	0x6A, 0xB6, 0x16, 0xA6, 0x1A, 0x4E, 0x84, 0x1C, 0x52, 0x7A, 0xDD, 0xDF, 0xA1, 0xF1, 0xDE, 0x28,
+	0x60, 0xF3, 0x9C, 0x1E, 0x71, 0x4A, 0x19, 0x85, 0x75, 0x56, 0x5C, 0x97, 0x4D, 0x45, 0x46, 0xCA,
+	0xFB, 0x59, 0x37, 0x73, 0xF3, 0x37, 0xFE, 0x0E, 0x41, 0xFD, 0x80, 0x3C, 0x69, 0xFB, 0x26, 0xF8,
+	0xDF, 0xE1, 0xA7, 0xC5, 0xAD, 0x73, 0x5F, 0xB1, 0xD5, 0xAD, 0x7C, 0x51, 0xA6, 0xDE, 0x68, 0xF2,
+	0xDD, 0x58, 0x5B, 0xC8, 0x8B, 0x04, 0xB6, 0xB2, 0x2C, 0xB0, 0xA3, 0x6E, 0xEE, 0xE9, 0x71, 0x29,
+	0xFA, 0x42, 0x7D, 0x2B, 0xF3, 0x36, 0xBF, 0x56, 0xFF, 0x00, 0xE0, 0xAB, 0x9E, 0x12, 0xF1, 0x0F,
+	0xC5, 0xAF, 0xD9, 0x3A, 0xFB, 0x55, 0xBC, 0xD5, 0xAF, 0x2F, 0x6E, 0x3C, 0x2B, 0xA8, 0x43, 0xAA,
+	0xDB, 0xA5, 0xC5, 0xC3, 0xCB, 0xB5, 0x07, 0xEE, 0xA4, 0xC0, 0x62, 0x70, 0x7C, 0xB9, 0x1C, 0x57,
+	0xE5, 0x22, 0xF2, 0x33, 0xFA, 0x9A, 0xF6, 0x67, 0xF1, 0x1F, 0x07, 0x87, 0x95, 0xE9, 0xD8, 0x28,
+	0xA2, 0x8A, 0x93, 0x63, 0xF4, 0x73, 0xE1, 0x5F, 0xFC, 0xA0, 0x8B, 0xE1, 0x47, 0xFD, 0x9E, 0xED,
+	0x9F, 0xFE, 0x9B, 0xAE, 0xEB, 0xE8, 0xEF, 0xDA, 0x83, 0xFE, 0x4A, 0xDF, 0xFC, 0x15, 0xA3, 0xFE,
+	0xC5, 0x5F, 0x06, 0x7F, 0xE8, 0x6F, 0x5F, 0x38, 0xFC, 0x2B, 0xFF, 0x00, 0x94, 0x11, 0x7C, 0x28,
+	0xFF, 0x00, 0xB3, 0xDD, 0xB3, 0xFF, 0x00, 0xD3, 0x75, 0xDD, 0x7D, 0x1D, 0xFB, 0x50, 0x7F, 0xC9,
+	0x5B, 0xFF, 0x00, 0x82, 0xB4, 0x7F, 0xD8, 0xAB, 0xE0, 0xCF, 0xFD, 0x0D, 0xEB, 0x43, 0x96, 0x5F,
+	0xD7, 0xE0, 0x77, 0xDF, 0xB2, 0xDF, 0xFC, 0xA5, 0x63, 0xF6, 0x09, 0xFF, 0x00, 0xB3, 0x41, 0x8F,
+	0xFF, 0x00, 0x4D, 0xB2, 0x57, 0xC9, 0xBF, 0xB2, 0xDF, 0xFC, 0xA3, 0x2B, 0xF6, 0x35, 0xFF, 0x00,
+	0xB3, 0xE4, 0xB3, 0xFF, 0x00, 0xD2, 0x8D, 0x3E, 0xBE, 0xB2, 0xFD, 0x96, 0xFF, 0x00, 0xE5, 0x2B,
+	0x1F, 0xB0, 0x4F, 0xFD, 0x9A, 0x0C, 0x7F, 0xFA, 0x6D, 0x92, 0xBE, 0x4D, 0xFD, 0x96, 0xFF, 0x00,
+	0xE5, 0x19, 0x5F, 0xB1, 0xAF, 0xFD, 0x9F, 0x25, 0x9F, 0xFE, 0x94, 0x69, 0xF4, 0x19, 0xF6, 0x3D,
+	0x63, 0xF6, 0xA8, 0xFF, 0x00, 0x91, 0x53, 0xFE, 0x0A, 0xB1, 0xFF, 0x00, 0x63, 0x8F, 0x87, 0xFF,
+	0x00, 0xF4, 0xB5, 0x2B, 0xBA, 0xF0, 0xEF, 0xFC, 0xA5, 0x53, 0xE0, 0x17, 0xFD, 0xA3, 0x36, 0xCF,
+	0xFF, 0x00, 0x4D, 0xFA, 0x9D, 0x70, 0xBF, 0xB5, 0x47, 0xFC, 0x8A, 0x9F, 0xF0, 0x55, 0x8F, 0xFB,
+	0x1C, 0x7C, 0x3F, 0xFF, 0x00, 0xA5, 0xA9, 0x5D, 0xD7, 0x87, 0x7F, 0xE5, 0x2A, 0x9F, 0x00, 0xBF,
+	0xED, 0x19, 0xB6, 0x7F, 0xFA, 0x6F, 0xD4, 0xEA, 0x9F, 0x40, 0xED, 0xE8, 0x79, 0x27, 0xEC, 0xFC,
+	0x09, 0xFD, 0x85, 0x7F, 0xE0, 0x9D, 0xF8, 0xFF, 0x00, 0xA3, 0xA6, 0xD7, 0x7F, 0xF4, 0xE3, 0x71,
+	0x55, 0xFF, 0x00, 0x6A, 0x4C, 0xFF, 0x00, 0xC3, 0x23, 0xFF, 0x00, 0xC1, 0x53, 0x06, 0x3F, 0xE6,
+	0xE2, 0xB4, 0x6F, 0xFD, 0x3F, 0xDD, 0x55, 0x8F, 0xD9, 0xF8, 0x13, 0xFB, 0x0A, 0xFF, 0x00, 0xC1,
+	0x3B, 0xF1, 0xFF, 0x00, 0x47, 0x4D, 0xAE, 0xFF, 0x00, 0xE9, 0xC6, 0xE2, 0xAB, 0xFE, 0xD4, 0x99,
+	0xFF, 0x00, 0x86, 0x47, 0xFF, 0x00, 0x82, 0xA6, 0x0C, 0x7F, 0xCD, 0xC5, 0x68, 0xDF, 0xFA, 0x7F,
+	0xBA, 0xA9, 0x2A, 0x5F, 0xAA, 0x3E, 0x86, 0x9F, 0xFE, 0x52, 0xE5, 0xAB, 0x7F, 0xD9, 0x80, 0x7F,
+	0xEE, 0x3E, 0x3A, 0xF0, 0x6F, 0xD9, 0xEF, 0x3F, 0xF0, 0xAB, 0xBF, 0xE0, 0x92, 0xBF, 0xF6, 0x52,
+	0xFC, 0x47, 0xFF, 0x00, 0xA7, 0x7D, 0x2A, 0xBD, 0xE6, 0x7F, 0xF9, 0x4B, 0x96, 0xAD, 0xFF, 0x00,
+	0x66, 0x01, 0xFF, 0x00, 0xB8, 0xF8, 0xEB, 0xC1, 0x7F, 0x67, 0xC2, 0x7F, 0xE1, 0x56, 0x7F, 0xC1,
+	0x25, 0xBF, 0xEC, 0xA6, 0x78, 0x8B, 0xFF, 0x00, 0x4E, 0xFA, 0x4D, 0x54, 0x76, 0x27, 0x53, 0x8D,
+	0xF8, 0xF2, 0x73, 0xFF, 0x00, 0x04, 0xD8, 0xFD, 0xB8, 0x00, 0xFF, 0x00, 0xA3, 0xCA, 0xB1, 0xFF,
+	0x00, 0xD0, 0xDA, 0xBE, 0x14, 0xFD, 0x8D, 0x74, 0x5D, 0x66, 0xCF, 0xF6, 0xC8, 0xF8, 0x55, 0x15,
+	0xDE, 0x91, 0x75, 0x13, 0x5B, 0xFC, 0x44, 0xD0, 0x67, 0x9D, 0x64, 0xB7, 0x65, 0x31, 0xC4, 0x2F,
+	0xE0, 0x26, 0x46, 0xC8, 0xF9, 0x54, 0x0F, 0xE2, 0x3C, 0x57, 0xDE, 0x5F, 0x19, 0x71, 0xFF, 0x00,
+	0x0E, 0xEB, 0xFD, 0xB6, 0x94, 0x81, 0xFF, 0x00, 0x27, 0xA5, 0xA7, 0x8E, 0x7F, 0xEB, 0xA9, 0xAF,
+	0xA3, 0xFE, 0x25, 0x8D, 0x9F, 0xF0, 0x51, 0x1F, 0xDA, 0xC1, 0x01, 0x23, 0xFE, 0x35, 0xCB, 0x21,
+	0xF9, 0x78, 0x3C, 0x69, 0x11, 0x63, 0xA6, 0x3D, 0x7A, 0x67, 0x8E, 0xC4, 0x54, 0xBE, 0x86, 0x91,
+	0x97, 0x2C, 0x5A, 0x3F, 0x33, 0x3F, 0xE0, 0xB2, 0xBA, 0x5E, 0xA7, 0x7F, 0xFF, 0x00, 0x05, 0x56,
+	0xF8, 0xE5, 0x3D, 0x8E, 0x9D, 0x71, 0x34, 0x77, 0xDF, 0x10, 0x2E, 0x5A, 0xC6, 0x48, 0x61, 0x66,
+	0x5B, 0x91, 0xE5, 0xC7, 0x93, 0x19, 0x03, 0x0F, 0x8E, 0xFB, 0x73, 0x8E, 0x33, 0xD4, 0x57, 0xA4,
+	0x7C, 0x3F, 0x49, 0x21, 0xFF, 0x00, 0x82, 0x00, 0x78, 0xCA, 0x29, 0x91, 0x95, 0x93, 0xF6, 0xA4,
+	0xD0, 0x55, 0xD5, 0x86, 0x19, 0x48, 0xD3, 0xEE, 0x32, 0x08, 0xED, 0x5F, 0x58, 0xFE, 0xC7, 0x6B,
+	0xBB, 0xC7, 0x3F, 0xF0, 0x4A, 0xD5, 0x1D, 0x1A, 0xCF, 0xC5, 0x59, 0x5E, 0x7B, 0x4B, 0xA9, 0x7B,
+	0xFF, 0x00, 0x5F, 0x5E, 0xDC, 0x57, 0x83, 0xFC, 0x63, 0x5D, 0xBF, 0xF0, 0x49, 0xBF, 0x8F, 0x88,
+	0x07, 0x0B, 0xFB, 0x73, 0x28, 0xEB, 0xD3, 0xFE, 0x3F, 0x86, 0x07, 0xE0, 0x05, 0x54, 0x57, 0xBC,
+	0xC7, 0xCD, 0xCD, 0x14, 0x7D, 0x6D, 0xFB, 0x59, 0x9C, 0xFF, 0x00, 0xC1, 0x46, 0x7F, 0xE0, 0xA3,
+	0x83, 0xFE, 0xAD, 0x87, 0x4A, 0xFF, 0x00, 0xD2, 0x6B, 0x1A, 0xCD, 0xFD, 0x97, 0xCF, 0xFC, 0x65,
+	0x47, 0xFC, 0x12, 0xE3, 0xFE, 0xC8, 0x56, 0xAF, 0xFF, 0x00, 0xA2, 0xD2, 0xB4, 0xFF, 0x00, 0x6B,
+	0x5F, 0xF9, 0x48, 0xCF, 0xFC, 0x14, 0x77, 0xFE, 0xCD, 0x87, 0x49, 0xFF, 0x00, 0xD2, 0x6B, 0x1A,
+	0xCC, 0xFD, 0x97, 0xFF, 0x00, 0xE4, 0xEA, 0x3F, 0xE0, 0x97, 0x1F, 0xF6, 0x42, 0xB5, 0x7F, 0xFD,
+	0x16, 0x94, 0x48, 0xCF, 0xFA, 0xFC, 0x0F, 0x98, 0xBE, 0x0D, 0x7F, 0xCA, 0x16, 0xF4, 0xCF, 0xFB,
+	0x48, 0x45, 0x9F, 0xFE, 0x90, 0xE9, 0x75, 0xF4, 0x3F, 0xED, 0x47, 0xFF, 0x00, 0x27, 0x05, 0xFF,
+	0x00, 0x05, 0x53, 0xFF, 0x00, 0xB2, 0x45, 0xA6, 0xFF, 0x00, 0xE9, 0x3C, 0x15, 0xF3, 0xC7, 0xC1,
+	0xAF, 0xF9, 0x42, 0xD6, 0x9B, 0xFF, 0x00, 0x69, 0x06, 0xB3, 0xFF, 0x00, 0xD2, 0x1D, 0x2E, 0xBE,
+	0x87, 0xFD, 0xA8, 0xFF, 0x00, 0xE4, 0xE0, 0xBF, 0xE0, 0xAA, 0x7F, 0xF6, 0x48, 0xB4, 0xDF, 0xFD,
+	0x27, 0x82, 0x9F, 0xBC, 0x3F, 0xF3, 0x34, 0x3E, 0x0F, 0x8C, 0x7F, 0xC1, 0x4C, 0x7F, 0x60, 0x7F,
+	0xFB, 0x32, 0xF9, 0xBF, 0xF4, 0xCF, 0xAE, 0xD7, 0x81, 0xF8, 0x1B, 0xFE, 0x51, 0x23, 0xFB, 0x39,
+	0xFF, 0x00, 0xD9, 0xF3, 0xDD, 0xFF, 0x00, 0x3B, 0xAA, 0xF7, 0xBF, 0x83, 0xC3, 0x1F, 0xF0, 0x53,
+	0x2F, 0xD8, 0x20, 0x7F, 0xD5, 0x97, 0xCD, 0xFF, 0x00, 0xA6, 0x7D, 0x76, 0xBC, 0x13, 0xC0, 0xDF,
+	0xF2, 0x89, 0x1F, 0xD9, 0xCF, 0xFE, 0xCF, 0x9E, 0xEF, 0xF9, 0xDD, 0x52, 0x88, 0x47, 0xE2, 0x3D,
+	0x43, 0xF6, 0x9D, 0xFF, 0x00, 0x90, 0x77, 0xFC, 0x15, 0xC7, 0xFE, 0xC3, 0x9E, 0x0B, 0xFF, 0x00,
+	0xD2, 0xF3, 0x5E, 0xAF, 0xF0, 0x2F, 0xFE, 0x52, 0xED, 0xFB, 0x32, 0xFF, 0x00, 0xD9, 0x8B, 0xDA,
+	0x7F, 0xE9, 0x9C, 0x57, 0x94, 0x7E, 0xD3, 0xBF, 0xF2, 0x0E, 0xFF, 0x00, 0x82, 0xB8, 0xFF, 0x00,
+	0xD8, 0x73, 0xC1, 0x7F, 0xFA, 0x5E, 0x6B, 0xD5, 0xFE, 0x05, 0xFF, 0x00, 0xCA, 0x5D, 0xBF, 0x66,
+	0x5F, 0xFB, 0x31, 0x7B, 0x4F, 0xFD, 0x33, 0x8A, 0x7E, 0xF1, 0x2B, 0xFA, 0xFC, 0x0F, 0x97, 0x7F,
+	0x65, 0x5F, 0xF9, 0x32, 0x9F, 0xF8, 0x27, 0x2F, 0xFD, 0x9E, 0x55, 0xBF, 0xFE, 0x9D, 0xB4, 0xBA,
+	0xEB, 0xBF, 0x6A, 0x1F, 0xF9, 0x37, 0x5F, 0xF8, 0x29, 0xFF, 0x00, 0xFD, 0x97, 0x9D, 0x1B, 0xFF,
+	0x00, 0x4B, 0x9E, 0xB9, 0x1F, 0xD9, 0x57, 0xFE, 0x4C, 0xA7, 0xFE, 0x09, 0xCB, 0xFF, 0x00, 0x67,
+	0x95, 0x6F, 0xFF, 0x00, 0xA7, 0x6D, 0x2E, 0xBA, 0xEF, 0xDA, 0x87, 0xFE, 0x4D, 0xD7, 0xFE, 0x0A,
+	0x7F, 0xFF, 0x00, 0x65, 0xE7, 0x46, 0xFF, 0x00, 0xD2, 0xE7, 0xA5, 0xF6, 0x4D, 0x3E, 0xD1, 0xF3,
+	0x67, 0xFC, 0x17, 0xE7, 0xFE, 0x4E, 0x8F, 0xE1, 0x47, 0xFD, 0x9B, 0x07, 0x81, 0xFF, 0x00, 0xF4,
+	0x4D, 0xD5, 0x7C, 0x35, 0x5F, 0x72, 0xFF, 0x00, 0xC1, 0x7E, 0x7F, 0xE4, 0xE8, 0xFE, 0x14, 0x7F,
+	0xD9, 0xB0, 0x78, 0x1F, 0xFF, 0x00, 0x44, 0xDD, 0x57, 0xC3, 0x55, 0x94, 0xB7, 0x37, 0x87, 0xC2,
+	0x80, 0xE3, 0x23, 0x3F, 0xE7, 0x8A, 0xFB, 0x4B, 0xFE, 0x08, 0x37, 0xFB, 0x1E, 0x78, 0xAF, 0xF6,
+	0xC6, 0xFD, 0xBC, 0xAC, 0xFC, 0x39, 0xE1, 0xDD, 0x46, 0xDE, 0xCD, 0x3C, 0x2B, 0xE1, 0xDB, 0xCD,
+	0x72, 0xF2, 0xEA, 0xF2, 0x16, 0x68, 0xE3, 0x55, 0xD9, 0x6F, 0x1F, 0xDD, 0xE7, 0x3E, 0x6D, 0xC4,
+	0x7D, 0x33, 0x8E, 0xBE, 0xF5, 0xF1, 0x7A, 0xFD, 0xE0, 0x39, 0xE4, 0xE3, 0x81, 0x5F, 0xA2, 0x1F,
+	0xF0, 0x45, 0x7F, 0x03, 0x6B, 0x5E, 0x13, 0xF8, 0x7F, 0xE2, 0xDF, 0x8C, 0xD6, 0xB7, 0xB7, 0x56,
+	0x92, 0x6B, 0xB7, 0xD1, 0xE9, 0x76, 0x73, 0x5B, 0x4E, 0xD1, 0xB3, 0xC1, 0x00, 0xDF, 0x21, 0x05,
+	0x48, 0xCA, 0xB4, 0x8E, 0xAA, 0x7F, 0xDA, 0x83, 0xDA, 0x9C, 0x3E, 0x24, 0x2A, 0xCE, 0xD4, 0xD9,
+	0xFB, 0x65, 0xF0, 0x0F, 0xFE, 0x09, 0xA7, 0xF1, 0x0B, 0xE0, 0xFF, 0x00, 0xC6, 0x0D, 0x07, 0xE2,
+	0x56, 0xAD, 0xF1, 0x2F, 0x47, 0xBC, 0xB7, 0xD2, 0x2F, 0x44, 0xF3, 0x5B, 0x41, 0x6B, 0x2A, 0xBB,
+	0x8C, 0x1E, 0x01, 0x6E, 0x2A, 0x1F, 0xDA, 0xA7, 0xFE, 0x09, 0xBF, 0xF1, 0x3F, 0xE3, 0xCF, 0xC7,
+	0x4D, 0x6B, 0xE2, 0x8F, 0x87, 0x7C, 0x77, 0xA2, 0xD9, 0x5A, 0xEA, 0x5E, 0x40, 0x8E, 0xDE, 0xF2,
+	0x39, 0x4B, 0xA6, 0xC8, 0x95, 0x0F, 0x2A, 0x31, 0xD4, 0x57, 0x80, 0xFE, 0xC6, 0x5E, 0x2C, 0xF1,
+	0x55, 0xF7, 0xED, 0x43, 0xE0, 0xDB, 0x4B, 0xDF, 0x13, 0xEA, 0x13, 0x47, 0x26, 0xAC, 0xA2, 0x48,
+	0xE4, 0xBE, 0x95, 0x95, 0x86, 0xD3, 0xD4, 0x16, 0xC6, 0x29, 0xBF, 0xF0, 0x51, 0x7D, 0x5F, 0x56,
+	0xB6, 0xFD, 0xAF, 0x3C, 0x51, 0x0D, 0xBE, 0xA3, 0x71, 0x1A, 0x2A, 0xDA, 0x05, 0x58, 0xE7, 0x20,
+	0x2F, 0xFA, 0x3A, 0x13, 0xF4, 0xC9, 0xAE, 0xA3, 0x86, 0x8C, 0x65, 0x29, 0x68, 0xCE, 0xF8, 0xFF,
+	0x00, 0xC1, 0x1F, 0x7E, 0x35, 0xAF, 0x5F, 0x8A, 0x3E, 0x1B, 0xF4, 0xFF, 0x00, 0x53, 0x3F, 0xF8,
+	0x1A, 0xFA, 0x0B, 0xF6, 0x56, 0xFD, 0x8E, 0x7C, 0x69, 0xF0, 0x1F, 0xE0, 0x57, 0x8E, 0x3E, 0x15,
+	0x78, 0x83, 0xC5, 0xBA, 0x6D, 0xD5, 0xD7, 0x8A, 0x1A, 0xE3, 0xEC, 0xF7, 0x36, 0x71, 0xBF, 0x95,
+	0x6D, 0xBE, 0xCC, 0x40, 0x37, 0x6E, 0xC1, 0xEB, 0xF3, 0x57, 0xE6, 0x79, 0xD7, 0x75, 0xB2, 0x33,
+	0xFD, 0xAD, 0x75, 0xC1, 0xC8, 0xFF, 0x00, 0x48, 0x6E, 0xB5, 0xF6, 0xC7, 0xFC, 0x13, 0xAB, 0x51,
+	0xD4, 0xAE, 0x3F, 0x63, 0xCF, 0x8B, 0x97, 0x92, 0x6A, 0x53, 0xB4, 0xD0, 0xFD, 0xB3, 0xCA, 0x91,
+	0xA6, 0x62, 0xD1, 0xE3, 0x4C, 0x52, 0x08, 0x24, 0x9C, 0x73, 0xCF, 0x18, 0xA0, 0xD2, 0xAC, 0x66,
+	0xA9, 0xEA, 0xCC, 0xB4, 0xFF, 0x00, 0x82, 0x44, 0x7C, 0x52, 0x23, 0x60, 0xF8, 0xBF, 0xA0, 0x95,
+	0x1C, 0xAE, 0x6C, 0x66, 0x39, 0x07, 0xFF, 0x00, 0xD4, 0x7F, 0x3A, 0x71, 0xFF, 0x00, 0x82, 0x43,
+	0x7C, 0x53, 0x51, 0xBB, 0xFE, 0x16, 0xE6, 0x81, 0xC7, 0x3C, 0x69, 0xF3, 0x67, 0x8E, 0x47, 0xEB,
+	0x5F, 0x2D, 0x8F, 0x1C, 0x78, 0xD1, 0x91, 0x7C, 0xCF, 0x19, 0x6A, 0xCC, 0xDC, 0x96, 0x2D, 0xA8,
+	0xCB, 0xEB, 0xFE, 0xF5, 0x1F, 0xF0, 0x9A, 0xF8, 0xD7, 0x05, 0x57, 0xC6, 0x3A, 0xA0, 0xC8, 0xC7,
+	0xFC, 0x84, 0x25, 0xFE, 0x86, 0x83, 0x94, 0xFB, 0xEF, 0xC4, 0x3F, 0xB1, 0x0F, 0x8C, 0x75, 0xFF,
+	0x00, 0xD9, 0x1B, 0x43, 0xFD, 0x9A, 0x60, 0xF1, 0xC6, 0x97, 0x16, 0xA1, 0xA4, 0xEB, 0xB2, 0x5D,
+	0x49, 0xAA, 0x0B, 0x59, 0x3C, 0x97, 0x53, 0x24, 0xCF, 0xB7, 0x19, 0xCE, 0x4A, 0xCA, 0x17, 0xEA,
+	0xA6, 0xBC, 0xA0, 0x7F, 0xC1, 0x21, 0xBE, 0x29, 0x13, 0xBB, 0xFE, 0x16, 0xE6, 0x83, 0xE9, 0xFF,
+	0x00, 0x1E, 0x13, 0xF4, 0x1C, 0x0F, 0xD0, 0x0A, 0xAB, 0xE3, 0xED, 0x7F, 0x5E, 0x1F, 0xF0, 0x4C,
+	0x7F, 0x08, 0xEB, 0x6B, 0xAD, 0xDE, 0xA5, 0xE4, 0xDE, 0x2A, 0x75, 0x92, 0xF1, 0x6E, 0x9F, 0xCD,
+	0x65, 0xF3, 0xEE, 0x46, 0xDD, 0xDB, 0xB3, 0x8C, 0x63, 0xBF, 0x6A, 0xF9, 0x97, 0xFE, 0x13, 0x7F,
+	0x1A, 0x30, 0xC1, 0xF1, 0x7E, 0xA9, 0x8F, 0xF6, 0xB5, 0x19, 0x7F, 0xF8, 0xA3, 0x40, 0x1F, 0x57,
+	0xE8, 0x3F, 0xF0, 0x49, 0xBF, 0x89, 0xDA, 0x26, 0xBB, 0x63, 0xAA, 0xCD, 0xF1, 0x5F, 0x41, 0x75,
+	0xB5, 0xBB, 0x8A, 0x56, 0x55, 0xB1, 0x9C, 0x16, 0x0A, 0xC0, 0xE3, 0x39, 0xEB, 0xC5, 0x7A, 0x6F,
+	0xED, 0x77, 0xFB, 0x0F, 0x78, 0xCF, 0xF6, 0x98, 0xF1, 0xAE, 0x91, 0xE2, 0xCF, 0x0D, 0xF8, 0xE7,
+	0x4D, 0xD2, 0xE3, 0xD3, 0x74, 0x38, 0xED, 0x5A, 0x1B, 0xDB, 0x59, 0x59, 0xA4, 0x70, 0xE5, 0xC3,
+	0x8D, 0xA7, 0xA0, 0xCE, 0x3E, 0xB5, 0xF0, 0xBF, 0x82, 0x7C, 0x6B, 0xE3, 0x47, 0xF1, 0x7E, 0x93,
+	0x1B, 0x78, 0xC3, 0x56, 0x0A, 0x75, 0x08, 0x47, 0xFC, 0x84, 0x65, 0xC0, 0xFD, 0xE2, 0xF6, 0xCE,
+	0x0F, 0xE3, 0x5F, 0x41, 0x7F, 0xC1, 0x4F, 0xB5, 0xED, 0x77, 0x47, 0xF8, 0xB3, 0xE1, 0x78, 0xB4,
+	0xAD, 0x6A, 0xFA, 0xCD, 0x5B, 0xC2, 0x71, 0xBC, 0x91, 0xDB, 0xDD, 0xBA, 0x06, 0x6F, 0x35, 0xFE,
+	0x63, 0x82, 0x39, 0xFC, 0x0D, 0x00, 0x5E, 0xFF, 0x00, 0x87, 0x42, 0xFC, 0x51, 0x51, 0x81, 0xF1,
+	0x77, 0xC3, 0xFB, 0x57, 0xA6, 0x74, 0xF9, 0xFA, 0x57, 0xA3, 0x7E, 0xCA, 0x5F, 0xF0, 0x4F, 0xAF,
+	0x1C, 0xFE, 0xCF, 0x1F, 0x19, 0x2D, 0x7E, 0x25, 0x6B, 0x9F, 0x10, 0x74, 0x9D, 0x42, 0xDE, 0xDA,
+	0xCA, 0xE2, 0x26, 0xB6, 0xB3, 0xB5, 0x95, 0x5D, 0x8B, 0xA3, 0x20, 0x39, 0x63, 0x8E, 0xF9, 0xFC,
+	0x2B, 0xE1, 0x5F, 0xF8, 0x4D, 0xBC, 0x66, 0xDC, 0xB7, 0x8C, 0x35, 0x4F, 0x5F, 0xF9, 0x09, 0x4B,
+	0xD7, 0xF3, 0xAF, 0x7A, 0xFF, 0x00, 0x82, 0x6F, 0x78, 0x9B, 0xC4, 0xFA, 0xAF, 0xED, 0x4B, 0xA6,
+	0x5A, 0xEA, 0x5E, 0x23, 0xD4, 0x2E, 0x23, 0xFE, 0xCD, 0xBD, 0xDD, 0x0D, 0xC5, 0xE4, 0x8C, 0x8D,
+	0xFB, 0x82, 0x7E, 0xE9, 0x38, 0xEB, 0xCD, 0x00, 0x7E, 0x93, 0x03, 0x45, 0x1C, 0xD1, 0x40, 0x05,
+	0x14, 0x51, 0x40, 0x1F, 0x9E, 0x7F, 0xF0, 0x56, 0xB7, 0x51, 0xF1, 0xE3, 0x41, 0x05, 0x80, 0xFF,
+	0x00, 0x8A, 0x64, 0x75, 0x3F, 0xF4, 0xF0, 0xF5, 0xF2, 0xBA, 0x90, 0x54, 0x10, 0xC3, 0xF3, 0xAF,
+	0xD2, 0x6F, 0xDA, 0xEB, 0xF6, 0x8C, 0xFD, 0x9D, 0x3E, 0x0D, 0x7C, 0x45, 0xD3, 0xF4, 0x3F, 0x8C,
+	0xBF, 0x05, 0x64, 0xF1, 0x35, 0xF5, 0xD6, 0x96, 0xB3, 0xDB, 0x5E, 0x47, 0xA4, 0xDA, 0x5C, 0x79,
+	0x31, 0x79, 0x8C, 0xA5, 0x33, 0x33, 0xA9, 0x1C, 0x8C, 0xF1, 0x9A, 0xF2, 0xB1, 0xFB, 0x78, 0x7E,
+	0xC2, 0x8C, 0x3E, 0x6F, 0xD9, 0x2E, 0xE0, 0xFF, 0x00, 0xB5, 0xFF, 0x00, 0x08, 0xD6, 0x97, 0xFF,
+	0x00, 0xC7, 0x68, 0x03, 0xCB, 0x3F, 0xE0, 0x99, 0xCC, 0xBF, 0xF0, 0xD6, 0x1A, 0x52, 0xEE, 0xE7,
+	0xFB, 0x2E, 0xFB, 0x81, 0xFF, 0x00, 0x5C, 0x4D, 0x79, 0xEF, 0xED, 0x53, 0x24, 0x6D, 0xFB, 0x4A,
+	0x78, 0xE9, 0x84, 0xAB, 0xFF, 0x00, 0x23, 0x45, 0xDF, 0xF1, 0x0F, 0xF9, 0xE9, 0x5F, 0x69, 0xFE,
+	0xCC, 0x7F, 0xB5, 0x37, 0xEC, 0xB5, 0xF1, 0x57, 0xE2, 0xCD, 0xAF, 0x83, 0xFE, 0x15, 0xFC, 0x01,
+	0x93, 0xC3, 0xFA, 0xC4, 0xF6, 0xF7, 0x12, 0xC5, 0xA9, 0x36, 0x87, 0x63, 0x06, 0xC5, 0x58, 0xF2,
+	0xE3, 0x74, 0x32, 0x16, 0xE5, 0x46, 0x3A, 0x7D, 0x6B, 0x9D, 0xF8, 0xA3, 0xFB, 0x64, 0xFE, 0xC7,
+	0x9E, 0x0C, 0xF8, 0x97, 0xAF, 0xF8, 0x5F, 0xC6, 0x7F, 0xB3, 0x5C, 0xDA, 0x9E, 0xAD, 0xA7, 0xEA,
+	0xD3, 0xC1, 0xA8, 0x6A, 0x0B, 0xA0, 0xE9, 0xF2, 0x7D, 0xA6, 0x55, 0x7C, 0x17, 0xDD, 0x24, 0xA1,
+	0x8E, 0x7D, 0xC6, 0x6A, 0x7E, 0xD0, 0x2D, 0xB6, 0x3E, 0x11, 0xE3, 0xD4, 0x7E, 0x75, 0xF5, 0xF7,
+	0xFC, 0x13, 0xFA, 0x44, 0xFF, 0x00, 0x86, 0x5D, 0xF8, 0xC8, 0x55, 0xC7, 0xFC, 0x83, 0x1C, 0x7D,
+	0x3F, 0xD0, 0xE7, 0xFF, 0x00, 0x1A, 0xD2, 0x3F, 0xB7, 0x8F, 0xEC, 0x29, 0xD0, 0x7E, 0xC9, 0x77,
+	0x1F, 0xF8, 0x4C, 0xE9, 0x7F, 0xFC, 0x76, 0xBD, 0x83, 0xF6, 0x7F, 0xF8, 0xFD, 0xF0, 0x03, 0xE2,
+	0x47, 0xC2, 0x7F, 0x1A, 0x78, 0xA3, 0xE1, 0x97, 0xC1, 0xF6, 0xD0, 0xB4, 0xBD, 0x0E, 0xCD, 0x9B,
+	0x58, 0xB1, 0x3A, 0x5D, 0xAC, 0x1F, 0x6D, 0x51, 0x04, 0x8D, 0xB4, 0x2C, 0x4E, 0x55, 0xBE, 0x45,
+	0x65, 0xF9, 0xB1, 0xD6, 0x9C, 0xB6, 0x05, 0xF1, 0x2D, 0x0F, 0xCC, 0xD8, 0x9D, 0x0A, 0x29, 0x59,
+	0x17, 0x95, 0xCF, 0xDE, 0xF6, 0x14, 0xE0, 0xC0, 0x1C, 0xE6, 0xBE, 0xD0, 0x8F, 0xF6, 0xEE, 0xFD,
+	0x84, 0xC4, 0x63, 0x6F, 0xEC, 0x9B, 0x71, 0x8F, 0xEE, 0xFF, 0x00, 0xC2, 0x37, 0xA6, 0x7A, 0x0F,
+	0xFA, 0x6D, 0xF5, 0xA1, 0xBF, 0x6E, 0xEF, 0xD8, 0x51, 0xB0, 0x07, 0xEC, 0x97, 0x37, 0xDE, 0x07,
+	0xE6, 0xF0, 0xCE, 0x96, 0x7A, 0x72, 0x3F, 0xE5, 0xAF, 0xAD, 0x30, 0x39, 0xBF, 0xDA, 0x45, 0xD4,
+	0xFF, 0x00, 0xC1, 0x2E, 0xFE, 0x1C, 0xE1, 0xFF, 0x00, 0xE6, 0x2B, 0x09, 0x18, 0xEF, 0xCD, 0xD1,
+	0xCD, 0x7C, 0x5E, 0x19, 0x78, 0x0C, 0xEB, 0x9C, 0x7F, 0x78, 0x57, 0xEA, 0x0F, 0xC6, 0x4F, 0x8F,
+	0xDF, 0xB3, 0xA6, 0x8F, 0xFB, 0x26, 0xF8, 0x73, 0xE2, 0x97, 0x8A, 0x3E, 0x06, 0xAE, 0xA9, 0xE1,
+	0x3D, 0x4E, 0xFA, 0x34, 0xD2, 0xFC, 0x37, 0x26, 0x97, 0x68, 0xDF, 0x66, 0x73, 0xE6, 0xE1, 0xFC,
+	0xB6, 0x6F, 0x2D, 0x48, 0xD9, 0x20, 0xCA, 0x9C, 0xFC, 0xFE, 0xE6, 0xBE, 0x7E, 0xFF, 0x00, 0x86,
+	0xD4, 0xFD, 0x81, 0x55, 0xB8, 0xFD, 0x8A, 0xE1, 0xFF, 0x00, 0xC2, 0x7F, 0x4C, 0xFF, 0x00, 0xE2,
+	0xEB, 0xE1, 0xF8, 0x83, 0x07, 0x86, 0xC4, 0x63, 0xAF, 0x52, 0xB2, 0x83, 0xB2, 0xD1, 0xA7, 0xFA,
+	0x1F, 0xBF, 0x78, 0x6B, 0x9F, 0xE6, 0xF9, 0x6F, 0x0F, 0xBA, 0x58, 0x6C, 0x0C, 0xEB, 0x47, 0x9D,
+	0xBE, 0x68, 0xB4, 0x95, 0xF4, 0xD3, 0x5D, 0x74, 0x3C, 0x2F, 0xF6, 0x37, 0x2B, 0xFF, 0x00, 0x0D,
+	0x51, 0xE0, 0x5D, 0x8E, 0x33, 0xFD, 0xB8, 0x3B, 0xFF, 0x00, 0xD3, 0x37, 0xAF, 0x52, 0xFF, 0x00,
+	0x82, 0x94, 0xB0, 0x3F, 0xB5, 0xB6, 0xB5, 0x93, 0xFF, 0x00, 0x30, 0xBB, 0x0E, 0xBF, 0xF5, 0xEE,
+	0xB5, 0xEA, 0x1F, 0x02, 0x3F, 0x6B, 0x4F, 0xD8, 0xBF, 0xC5, 0x9F, 0x18, 0x74, 0x0F, 0x0C, 0xF8,
+	0x1B, 0xF6, 0x4E, 0x87, 0x46, 0xD6, 0x2F, 0xAF, 0xFC, 0xAB, 0x0D, 0x55, 0x74, 0x1D, 0x3E, 0x3F,
+	0xB3, 0x49, 0xB5, 0x8E, 0xFD, 0xD1, 0xBE, 0xE1, 0xC0, 0x3D, 0x32, 0x6B, 0xD0, 0xBF, 0x69, 0x4F,
+	0xDA, 0xA3, 0xF6, 0x58, 0xF8, 0x53, 0xF1, 0x72, 0xF7, 0xC1, 0xBF, 0x14, 0xBF, 0x67, 0xD9, 0xB5,
+	0xFD, 0x62, 0xDE, 0xD6, 0x07, 0x9B, 0x52, 0x8F, 0x45, 0xB0, 0x9B, 0x7A, 0xBA, 0x06, 0x41, 0xBA,
+	0x57, 0x56, 0xE0, 0x71, 0xD2, 0xBD, 0x5E, 0x1C, 0xC3, 0xD1, 0xC3, 0xE1, 0x65, 0x1A, 0x75, 0x14,
+	0xD5, 0xEF, 0x74, 0x9F, 0xEA, 0x7C, 0x77, 0x89, 0xD9, 0x96, 0x3B, 0x34, 0xCD, 0xA9, 0x54, 0xC5,
+	0xE1, 0xA5, 0x45, 0xA8, 0x5A, 0xD2, 0x69, 0xB7, 0xAE, 0xFA, 0x1F, 0x9C, 0x7E, 0x2B, 0xF0, 0xE6,
+	0x93, 0xE3, 0x1F, 0x0B, 0xEA, 0x5E, 0x12, 0xD7, 0x55, 0x5A, 0xCB, 0x54, 0xB1, 0x9A, 0xD6, 0xE9,
+	0x58, 0xF5, 0x8E, 0x44, 0x2A, 0x7F, 0x11, 0x9C, 0x8F, 0x70, 0x2B, 0xF1, 0x47, 0xE2, 0x7F, 0x80,
+	0x35, 0x8F, 0x85, 0x9F, 0x11, 0x35, 0xAF, 0x87, 0x5A, 0xE4, 0x3B, 0x6E, 0xB4, 0x5D, 0x4A, 0x6B,
+	0x49, 0x72, 0x3E, 0xF6, 0xC7, 0x2A, 0x1B, 0xE8, 0x40, 0xC8, 0xF6, 0xC5, 0x7F, 0x51, 0xD2, 0x7E,
+	0xDD, 0xFF, 0x00, 0xB0, 0xA9, 0x8C, 0x85, 0xFD, 0x92, 0xE7, 0xFA, 0x37, 0x86, 0xB4, 0xBE, 0x7F,
+	0xF2, 0x29, 0xFD, 0x39, 0xF4, 0xAF, 0xC8, 0x7F, 0xF8, 0x38, 0x9F, 0xE0, 0xAF, 0xC3, 0x9F, 0x1A,
+	0xF8, 0xE7, 0x45, 0xFD, 0xBF, 0xBF, 0x67, 0x6F, 0x86, 0x17, 0x5E, 0x1F, 0xF0, 0xBE, 0xBF, 0x3A,
+	0xF8, 0x63, 0xC6, 0x56, 0x6D, 0x63, 0x04, 0x29, 0x0E, 0xB1, 0x04, 0x01, 0xE0, 0xB8, 0xDB, 0x03,
+	0xB2, 0xE2, 0x6B, 0x6C, 0x47, 0x9E, 0x3E, 0x6B, 0x4E, 0x70, 0x64, 0x00, 0xFB, 0xD5, 0x23, 0xA5,
+	0xCF, 0xCE, 0xF0, 0xB5, 0x2D, 0x2B, 0x33, 0xF3, 0x2E, 0x8A, 0x28, 0x07, 0x07, 0x3C, 0xF5, 0x1D,
+	0x3E, 0xBF, 0xE1, 0x58, 0x1D, 0xE7, 0xE8, 0xE7, 0xC2, 0xA5, 0x27, 0xFE, 0x08, 0x47, 0xF0, 0xA0,
+	0x28, 0xFF, 0x00, 0x9B, 0xDC, 0xB3, 0x3F, 0xF9, 0x4E, 0xBB, 0xFF, 0x00, 0x3E, 0xD5, 0xF4, 0x87,
+	0xED, 0x42, 0x40, 0xF8, 0xB5, 0xFF, 0x00, 0x05, 0x68, 0x24, 0xFF, 0x00, 0xCC, 0xA7, 0xE0, 0xB3,
+	0xFF, 0x00, 0x8F, 0x3D, 0x7E, 0x52, 0x68, 0xFF, 0x00, 0xB6, 0x3F, 0xC7, 0xCD, 0x0F, 0xF6, 0x76,
+	0xD1, 0xFF, 0x00, 0x65, 0x7D, 0x3B, 0xC4, 0xD6, 0x69, 0xE0, 0xBD, 0x03, 0xE2, 0x02, 0x78, 0xCF,
+	0x4C, 0xD3, 0xDB, 0x49, 0x81, 0xA4, 0x4D, 0x61, 0x62, 0x78, 0x84, 0xE6, 0x56, 0x42, 0xEC, 0xBB,
+	0x24, 0x71, 0xE5, 0x92, 0x54, 0xE7, 0x24, 0x70, 0x2B, 0xA9, 0xF1, 0x7F, 0xFC, 0x14, 0xAB, 0xF6,
+	0xB6, 0xF1, 0xBE, 0xB3, 0xF1, 0x9F, 0x5F, 0xD7, 0xBC, 0x71, 0xA7, 0xC9, 0x75, 0xF1, 0xF6, 0xCA,
+	0xC6, 0xD7, 0xE2, 0x53, 0x47, 0xA0, 0xDB, 0x2A, 0xDE, 0xC5, 0x67, 0x9F, 0xB3, 0x88, 0x80, 0x4F,
+	0xF4, 0x6D, 0xB9, 0xE7, 0xCB, 0xC6, 0x7A, 0xF5, 0xAA, 0xE6, 0x31, 0x95, 0x39, 0x48, 0xFD, 0x6F,
+	0xFD, 0x97, 0x3E, 0x5F, 0xF8, 0x2A, 0xD7, 0xEC, 0x12, 0x08, 0xFF, 0x00, 0x9B, 0x41, 0x4F, 0xFD,
+	0x36, 0xC9, 0x5F, 0x26, 0x7E, 0xCB, 0x4A, 0x5B, 0xFE, 0x09, 0x95, 0xFB, 0x1A, 0xED, 0x1B, 0xBF,
+	0xE3, 0x39, 0x2C, 0xFE, 0xEF, 0x3F, 0xF2, 0xF1, 0xA7, 0xD7, 0xCC, 0x7F, 0x0B, 0x3F, 0xE0, 0xA6,
+	0x7F, 0xB7, 0x25, 0xB7, 0xED, 0x01, 0xF0, 0xC3, 0xE2, 0x9F, 0x81, 0x3C, 0x79, 0xA5, 0xC7, 0xE2,
+	0xFF, 0x00, 0x86, 0xFE, 0x0D, 0x1E, 0x0F, 0xF0, 0x15, 0xD4, 0xDE, 0x1F, 0xB3, 0x64, 0xB3, 0xD2,
+	0xC4, 0x46, 0x3F, 0x25, 0xD5, 0xD0, 0xAC, 0xAD, 0xE5, 0x96, 0x02, 0x47, 0xCB, 0x7A, 0x92, 0x6A,
+	0xF7, 0x84, 0x75, 0xBF, 0xDB, 0x97, 0xC0, 0xFF, 0x00, 0x0A, 0x7C, 0x0D, 0xF0, 0x63, 0xC3, 0xBA,
+	0xD6, 0x87, 0x16, 0x81, 0xF0, 0xE3, 0xE2, 0x02, 0xF8, 0xD3, 0xC2, 0x96, 0xB2, 0x43, 0x6C, 0xEF,
+	0x6F, 0xAC, 0x2B, 0x46, 0xC2, 0x67, 0x90, 0xAE, 0xE9, 0x57, 0x30, 0xA6, 0x23, 0x63, 0xB4, 0x6D,
+	0x1C, 0x55, 0x5F, 0x9B, 0x64, 0x66, 0xE1, 0xCB, 0xBB, 0x3E, 0xE6, 0xFD, 0xAA, 0x9D, 0x07, 0x85,
+	0x7F, 0xE0, 0xAB, 0x0D, 0xBC, 0x63, 0xFE, 0x13, 0x0F, 0x0F, 0xF3, 0x9E, 0x9F, 0xE9, 0xA9, 0xFE,
+	0x7D, 0xEB, 0xBA, 0xF0, 0xE8, 0xC7, 0xFC, 0x15, 0x4F, 0xE0, 0x19, 0x3D, 0x17, 0xFE, 0x09, 0x9F,
+	0x68, 0x09, 0xED, 0xC6, 0x9D, 0xA9, 0xFF, 0x00, 0x88, 0xAF, 0xCF, 0x9F, 0x17, 0x7C, 0x5E, 0xFF,
+	0x00, 0x82, 0x87, 0xF8, 0xE2, 0xCF, 0xE2, 0xFE, 0x9F, 0xE2, 0x3F, 0x16, 0x68, 0x73, 0x45, 0xF1,
+	0xDA, 0xF2, 0xDA, 0xEF, 0xE2, 0x67, 0x97, 0x69, 0x68, 0xA7, 0x50, 0x96, 0xDD, 0x83, 0xC4, 0x63,
+	0xC2, 0x8F, 0xB3, 0xFC, 0xCB, 0xC8, 0x8B, 0x68, 0x39, 0xE7, 0x70, 0x24, 0x56, 0x85, 0xAF, 0xED,
+	0x09, 0xFF, 0x00, 0x05, 0x24, 0xB2, 0xF8, 0xC3, 0xE1, 0xBF, 0x8E, 0xD0, 0x78, 0xB7, 0xC3, 0xBF,
+	0xF0, 0x92, 0x78, 0x4F, 0xE1, 0x4A, 0x7C, 0x39, 0xD1, 0x6E, 0x8E, 0x9B, 0x64, 0xD1, 0xC5, 0xE1,
+	0xE4, 0x8E, 0x68, 0xC5, 0xB1, 0x42, 0x9B, 0x5D, 0xF6, 0x4F, 0x20, 0xF3, 0x58, 0x6F, 0xF9, 0xB9,
+	0x27, 0x03, 0x06, 0xBA, 0x13, 0x65, 0xA6, 0xA7, 0xD3, 0x7F, 0xB3, 0xEF, 0xCF, 0xFB, 0x0B, 0x7F,
+	0xC1, 0x3B, 0xC2, 0x7C, 0xC7, 0xFE, 0x1A, 0xA3, 0x5D, 0x1F, 0x2F, 0x3F, 0xF3, 0x11, 0xB8, 0xAA,
+	0xDF, 0xB5, 0x29, 0xDD, 0xFB, 0x24, 0xFF, 0x00, 0xC1, 0x53, 0x31, 0xFF, 0x00, 0x47, 0x15, 0xA3,
+	0x7F, 0xE9, 0xFE, 0xEA, 0xBE, 0x51, 0xF0, 0xD7, 0xC4, 0x3F, 0xF8, 0x28, 0x07, 0x84, 0xBE, 0x1E,
+	0x7C, 0x31, 0xF8, 0x5B, 0xA3, 0x78, 0x97, 0x41, 0x1A, 0x3F, 0xC1, 0xFF, 0x00, 0x18, 0x5C, 0x78,
+	0x9F, 0xC0, 0xB6, 0xF2, 0xDA, 0xDA, 0x48, 0xD6, 0x9A, 0x94, 0xD2, 0xB4, 0xB2, 0x4A, 0xF2, 0x32,
+	0x16, 0x9C, 0x6F, 0x66, 0x21, 0x1F, 0x2A, 0x3A, 0x63, 0x14, 0xDF, 0x17, 0xF8, 0xFB, 0xF6, 0xFA,
+	0xF1, 0xBF, 0x83, 0x7E, 0x2F, 0x78, 0x07, 0xC4, 0xBE, 0x23, 0xD1, 0x66, 0xD2, 0xFE, 0x39, 0x78,
+	0x9A, 0xDF, 0xC4, 0x3F, 0x11, 0xA1, 0x5B, 0x6B, 0x45, 0x7B, 0xFD, 0x42, 0x1B, 0x96, 0xB9, 0x49,
+	0x23, 0x60, 0xA0, 0xDB, 0x81, 0x2B, 0xB3, 0x6D, 0x8C, 0x85, 0xC1, 0xC0, 0x1D, 0x45, 0x1E, 0xF0,
+	0x4A, 0x3E, 0x67, 0xE9, 0xC4, 0xAD, 0xFF, 0x00, 0x1B, 0x72, 0xD5, 0x83, 0x1F, 0xF9, 0xC7, 0xF9,
+	0xFF, 0x00, 0xD3, 0x7C, 0x75, 0xE0, 0xBF, 0xB3, 0xDE, 0x3F, 0xE1, 0x55, 0xFF, 0x00, 0xC1, 0x25,
+	0x77, 0x7F, 0xD1, 0x4C, 0xF1, 0x17, 0xFE, 0x9D, 0xF4, 0xAA, 0xF3, 0x5D, 0x13, 0x44, 0xFF, 0x00,
+	0x82, 0xCA, 0xF8, 0x8F, 0xE2, 0x6C, 0x7F, 0xB5, 0x06, 0x99, 0xE2, 0xAF, 0x07, 0x37, 0x88, 0x35,
+	0x4F, 0x85, 0xEB, 0xE0, 0xB1, 0x78, 0xD1, 0xE9, 0xCA, 0xAD, 0xA0, 0xB4, 0x2A, 0x9E, 0x47, 0x97,
+	0xE5, 0x85, 0x0F, 0xB0, 0x7F, 0xAC, 0xC0, 0x71, 0x9E, 0xBD, 0x6B, 0x1F, 0xC3, 0x7F, 0xB3, 0xC7,
+	0xFC, 0x15, 0xB7, 0xC2, 0x5A, 0x3F, 0xC1, 0x7D, 0x07, 0x41, 0xD4, 0xBC, 0x21, 0x1D, 0xB7, 0xC0,
+	0x1D, 0x52, 0xEF, 0x51, 0xF8, 0x62, 0xB2, 0x5C, 0x59, 0x31, 0xD3, 0xEE, 0x27, 0x9A, 0x19, 0xE4,
+	0x69, 0x8E, 0xDD, 0xD7, 0x59, 0x92, 0x08, 0xD8, 0x79, 0xA5, 0xB1, 0xB7, 0x18, 0xC1, 0xAA, 0x5C,
+	0xDD, 0x83, 0xDD, 0xEE, 0x76, 0xDF, 0x19, 0xF8, 0xFF, 0x00, 0x82, 0x75, 0xFE, 0xDB, 0x8F, 0x9E,
+	0x3F, 0xE1, 0xB4, 0xB4, 0xF3, 0xF4, 0xFD, 0xED, 0x7D, 0x25, 0xF1, 0x3F, 0xE5, 0xFF, 0x00, 0x82,
+	0x8A, 0x7E, 0xD6, 0x4C, 0x7A, 0x2F, 0xFC, 0x13, 0x92, 0x4D, 0xDE, 0xDF, 0xF1, 0x28, 0x87, 0xAF,
+	0xA5, 0x7C, 0x5B, 0xE2, 0x0F, 0xD9, 0x6F, 0xFE, 0x0A, 0xB5, 0xE2, 0x5F, 0x86, 0x7E, 0x3E, 0xF8,
+	0x41, 0xAB, 0x6A, 0x1E, 0x13, 0x93, 0x42, 0xF8, 0x95, 0xE3, 0xA8, 0xFC, 0x61, 0xE2, 0xCB, 0x75,
+	0xBA, 0xB2, 0x56, 0xB8, 0xD5, 0xD0, 0xE5, 0x66, 0x47, 0x09, 0xBA, 0x25, 0xCE, 0x7F, 0x76, 0x84,
+	0x27, 0x3D, 0x07, 0x35, 0xD4, 0x6A, 0xBF, 0x0F, 0xFF, 0x00, 0xE0, 0xB3, 0x3A, 0xE7, 0xC5, 0x1F,
+	0x18, 0xFC, 0x60, 0xD4, 0x3C, 0x47, 0xE0, 0xC6, 0xD7, 0xBC, 0x79, 0xF0, 0xC4, 0xFC, 0x3E, 0xF1,
+	0x25, 0xD6, 0xCD, 0x34, 0x2C, 0xFA, 0x09, 0x8C, 0x44, 0x60, 0x44, 0xF2, 0xCA, 0xC4, 0xDE, 0x5A,
+	0xA8, 0xF3, 0x14, 0x6F, 0xF7, 0xE4, 0xD0, 0xB9, 0xBB, 0x02, 0xE5, 0xEE, 0x7B, 0x87, 0xEC, 0x6C,
+	0xA4, 0x78, 0xEF, 0xFE, 0x09, 0x57, 0xFE, 0xCD, 0x97, 0x8B, 0x0F, 0xFE, 0x44, 0xD4, 0xAB, 0xC1,
+	0x7E, 0x33, 0x71, 0xFF, 0x00, 0x04, 0x9C, 0xF8, 0xFC, 0xA4, 0x73, 0xFF, 0x00, 0x0D, 0xD0, 0x3F,
+	0xF6, 0xFE, 0xAB, 0xF8, 0x23, 0xE0, 0x9F, 0xFC, 0x16, 0x03, 0xE1, 0xD5, 0xDF, 0xC1, 0xED, 0x43,
+	0xC2, 0x5A, 0xE7, 0x83, 0xE0, 0x9B, 0xE0, 0x3C, 0x57, 0x91, 0xFC, 0x35, 0x69, 0x24, 0xB1, 0x90,
+	0xD8, 0x8B, 0xA3, 0x29, 0x9F, 0xCC, 0xDC, 0xA7, 0xED, 0x19, 0x33, 0x3E, 0x3C, 0xCD, 0xD8, 0xCF,
+	0x18, 0xC5, 0x73, 0xBA, 0xE7, 0xEC, 0x83, 0xFF, 0x00, 0x05, 0x4C, 0xF1, 0x17, 0xC1, 0xAF, 0x11,
+	0xFC, 0x02, 0xD5, 0xAE, 0xFC, 0x29, 0x27, 0x85, 0xFC, 0x57, 0xF1, 0x09, 0xBC, 0x6B, 0xAD, 0x59,
+	0x8B, 0xEB, 0x35, 0x79, 0x75, 0x70, 0x24, 0xC4, 0xA2, 0x40, 0xBB, 0x91, 0x7F, 0x7A, 0xFF, 0x00,
+	0xBB, 0x5F, 0x97, 0x9E, 0x47, 0x14, 0xAD, 0x2E, 0xC1, 0xEE, 0xAE, 0xA7, 0xDB, 0xDF, 0xB5, 0xC1,
+	0x03, 0xFE, 0x0A, 0x39, 0xFF, 0x00, 0x05, 0x1C, 0xDD, 0xC7, 0xFC, 0x63, 0x0E, 0x92, 0x7E, 0x6E,
+	0x3F, 0xE5, 0xD6, 0xC6, 0xB3, 0xBF, 0x65, 0xF2, 0x47, 0xED, 0x4D, 0xFF, 0x00, 0x04, 0xB8, 0x24,
+	0x71, 0xFF, 0x00, 0x0A, 0x2F, 0x57, 0xFF, 0x00, 0xD1, 0x49, 0xFD, 0x39, 0xFA, 0x67, 0xD0, 0xD7,
+	0xCC, 0xBE, 0x33, 0xF0, 0x0F, 0xFC, 0x16, 0x6F, 0xC7, 0xBF, 0x14, 0x7E, 0x27, 0x7C, 0x62, 0xF1,
+	0x27, 0x89, 0xBC, 0x1B, 0x36, 0xBD, 0xF1, 0x87, 0xC2, 0x70, 0xF8, 0x6F, 0xC7, 0x97, 0x11, 0xFF,
+	0x00, 0x67, 0xC6, 0x97, 0x9A, 0x74, 0x4B, 0x1A, 0x2A, 0x46, 0x8A, 0x98, 0x81, 0xB6, 0xC4, 0x9F,
+	0x3A, 0x00, 0xC7, 0x1C, 0x90, 0x4E, 0x6A, 0x0F, 0x0B, 0x7C, 0x3A, 0xFF, 0x00, 0x82, 0xC8, 0x7C,
+	0x3B, 0xF1, 0x4F, 0xC2, 0x7F, 0x88, 0x9A, 0x17, 0x88, 0xBC, 0x1B, 0x1E, 0xA1, 0xF0, 0x37, 0xC3,
+	0x77, 0x1A, 0x37, 0xC3, 0xD9, 0x65, 0x6B, 0x09, 0x16, 0xC6, 0xC6, 0x55, 0x1E, 0x64, 0x52, 0x2B,
+	0x29, 0xFB, 0x41, 0x21, 0x7E, 0xF4, 0x85, 0x88, 0x38, 0xE7, 0xB8, 0x7C, 0xB2, 0xEC, 0x0F, 0x97,
+	0xBF, 0xF5, 0x62, 0x4F, 0x83, 0x5C, 0x7F, 0xC1, 0x17, 0x34, 0xD0, 0x47, 0xFC, 0xE4, 0x22, 0xCB,
+	0x8F, 0xFB, 0x71, 0xD3, 0x2B, 0xE8, 0x8F, 0xDA, 0x8C, 0x0F, 0xF8, 0x68, 0x3F, 0xF8, 0x2A, 0x92,
+	0x93, 0xF3, 0x7F, 0xC2, 0xA2, 0xD3, 0x46, 0xDE, 0xFF, 0x00, 0xF1, 0xEF, 0x05, 0x78, 0xAF, 0x86,
+	0xFF, 0x00, 0xE0, 0x92, 0x7F, 0xF0, 0x5A, 0xFD, 0x0F, 0xE0, 0x2C, 0x1F, 0xB3, 0xAE, 0x8C, 0x7C,
+	0x0B, 0x1F, 0x84, 0xD7, 0xE2, 0x44, 0x3E, 0x3E, 0x8E, 0xCD, 0xB5, 0xBB, 0x03, 0x2F, 0xF6, 0xDA,
+	0x45, 0x0C, 0x69, 0x3F, 0x9D, 0xB7, 0x7E, 0xC0, 0x90, 0xC6, 0x3C, 0xB3, 0x94, 0xE3, 0xA5, 0x75,
+	0x1E, 0x2D, 0xFF, 0x00, 0x82, 0x75, 0x7F, 0xC1, 0x7B, 0xBC, 0x73, 0xE2, 0x5F, 0x8B, 0xDE, 0x2D,
+	0xF1, 0x1E, 0xA3, 0xF0, 0xFE, 0x6B, 0xEF, 0x8E, 0x9A, 0x1C, 0x3A, 0x57, 0xC4, 0x89, 0x16, 0xFF,
+	0x00, 0x4C, 0x8D, 0x6F, 0xAD, 0x62, 0x55, 0x58, 0xD2, 0x34, 0x08, 0x56, 0x02, 0x02, 0x8F, 0x9A,
+	0x20, 0xA4, 0x9E, 0x73, 0x9A, 0x3D, 0xEE, 0xC1, 0xEE, 0xF3, 0x6E, 0x7A, 0x97, 0xC1, 0xF5, 0xC7,
+	0xFC, 0x14, 0xCB, 0xF6, 0x08, 0x19, 0xFF, 0x00, 0x9B, 0x2F, 0x9B, 0xEB, 0xFF, 0x00, 0x20, 0x7D,
+	0x76, 0xBC, 0x07, 0xC1, 0x04, 0x7F, 0xC3, 0xA4, 0x3F, 0x67, 0x4C, 0x9E, 0x9F, 0xB7, 0x35, 0xDE,
+	0x7D, 0xB9, 0xBA, 0xAE, 0xCB, 0x43, 0xFF, 0x00, 0x82, 0x7C, 0x7F, 0xC1, 0x7C, 0x3C, 0x37, 0xF1,
+	0x5B, 0xE1, 0xCF, 0xC6, 0xAD, 0x26, 0xFF, 0x00, 0xE1, 0xFC, 0x7E, 0x20, 0xF8, 0x53, 0xE0, 0x56,
+	0xF0, 0x87, 0x82, 0xEE, 0x9F, 0x50, 0xD3, 0x19, 0x6D, 0x74, 0x93, 0x0D, 0xC4, 0x1E, 0x4B, 0xA3,
+	0x21, 0x59, 0x9F, 0xCB, 0xB9, 0x94, 0x19, 0x1C, 0x16, 0xCB, 0x03, 0xB8, 0x91, 0x5C, 0xDE, 0x9D,
+	0xFF, 0x00, 0x04, 0xA2, 0xFF, 0x00, 0x82, 0xDE, 0xE9, 0x7F, 0x06, 0x3C, 0x2F, 0xF0, 0x06, 0xD6,
+	0x5F, 0x02, 0xAF, 0x85, 0xFC, 0x1B, 0xF1, 0x09, 0xFC, 0x6F, 0xA0, 0x59, 0xFF, 0x00, 0x6D, 0x58,
+	0x19, 0x21, 0xD6, 0x9C, 0xBE, 0xE9, 0x9A, 0x4C, 0x6E, 0x95, 0x7F, 0x78, 0xDF, 0x23, 0x1D, 0x80,
+	0x71, 0xB7, 0xA6, 0x17, 0xBD, 0xB5, 0x87, 0x1E, 0x5B, 0xDE, 0xE7, 0xA2, 0x7E, 0xD3, 0x60, 0x9D,
+	0x37, 0xFE, 0x0A, 0xE3, 0xB4, 0x16, 0xFF, 0x00, 0x89, 0xF7, 0x82, 0xC7, 0xCA, 0x33, 0xFF, 0x00,
+	0x2F, 0xE7, 0xFC, 0xFF, 0x00, 0xFA, 0xAB, 0xD5, 0xBE, 0x06, 0x71, 0xFF, 0x00, 0x05, 0x74, 0xFD,
+	0x99, 0x64, 0x3F, 0x77, 0xFE, 0x18, 0x5E, 0xD7, 0xE6, 0xED, 0xFF, 0x00, 0x20, 0x71, 0xFA, 0x57,
+	0xCF, 0x7E, 0x2C, 0xFF, 0x00, 0x82, 0x6B, 0x7F, 0xC1, 0x77, 0xBC, 0x6F, 0x0F, 0xC6, 0x8B, 0x6F,
+	0x10, 0xDF, 0x78, 0x06, 0x55, 0xFD, 0xA0, 0x2E, 0x2C, 0x66, 0xF8, 0x9D, 0xE5, 0xEA, 0x9A, 0x6A,
+	0x7D, 0xBD, 0xAD, 0x24, 0xF3, 0x20, 0xF2, 0xB0, 0xB9, 0xB5, 0xC3, 0x7C, 0xC7, 0xCA, 0xC0, 0x6C,
+	0xF3, 0xCD, 0x75, 0xBF, 0x0E, 0x7F, 0xE0, 0x9C, 0xFF, 0x00, 0xF0, 0x70, 0xF8, 0xF8, 0xCD, 0xE1,
+	0x9F, 0xDA, 0x33, 0xC1, 0xBA, 0xA7, 0xC3, 0x94, 0xF1, 0x47, 0x80, 0xFC, 0x07, 0x1F, 0x81, 0xFC,
+	0x3F, 0x7A, 0xD7, 0x9A, 0x5B, 0x2D, 0xBE, 0x8E, 0xB6, 0xEB, 0x12, 0xC2, 0xD1, 0x94, 0xDB, 0x23,
+	0x6C, 0xE3, 0x7B, 0x65, 0xB9, 0xEB, 0x4B, 0xDE, 0x25, 0x72, 0xF7, 0x3C, 0xD3, 0xF6, 0x55, 0x27,
+	0xFE, 0x18, 0xA7, 0xFE, 0x09, 0xCC, 0x3F, 0xEA, 0xF2, 0xA0, 0x1F, 0x5C, 0x6A, 0xDA, 0x5E, 0x7F,
+	0xAF, 0xE4, 0x6B, 0xAE, 0xFD, 0xA8, 0xFE, 0x5F, 0xD9, 0xD7, 0xFE, 0x0A, 0x80, 0x58, 0x63, 0x1F,
+	0x1E, 0x34, 0x62, 0x4B, 0x74, 0x03, 0xED, 0xAE, 0x73, 0x49, 0xE1, 0x0F, 0xF8, 0x22, 0x37, 0xFC,
+	0x17, 0xB7, 0xC0, 0xDE, 0x02, 0xF8, 0x5F, 0xF0, 0xD7, 0xC3, 0x56, 0xFE, 0x01, 0x87, 0x49, 0xF8,
+	0x3B, 0xE3, 0xA5, 0xF1, 0x77, 0x80, 0xE1, 0x93, 0x5B, 0xB1, 0x95, 0xAD, 0x35, 0x61, 0x34, 0x33,
+	0x09, 0xE4, 0x72, 0xA0, 0xCE, 0x04, 0x90, 0x46, 0x76, 0x3E, 0x57, 0xE5, 0xE9, 0x83, 0x5A, 0x1E,
+	0x2F, 0xFF, 0x00, 0x82, 0x35, 0x7F, 0xC1, 0xC0, 0x5E, 0x36, 0xF0, 0xCF, 0xC5, 0xAF, 0x07, 0xF8,
+	0x8B, 0xFE, 0x15, 0xF4, 0x9A, 0x7F, 0xC6, 0xEF, 0x12, 0x41, 0xAE, 0xFC, 0x45, 0x86, 0x1D, 0x5B,
+	0x4E, 0x43, 0x7B, 0x79, 0x0C, 0xBE, 0x64, 0x6F, 0x1B, 0x2C, 0x6A, 0x6D, 0xC6, 0xEE, 0x4A, 0xC7,
+	0xB4, 0x1E, 0xF9, 0x15, 0x5E, 0xF3, 0x1F, 0xBB, 0x7D, 0xD1, 0xF2, 0xF7, 0xFC, 0x17, 0xED, 0x1C,
+	0x7E, 0xD4, 0x5F, 0x09, 0xCB, 0x29, 0xE7, 0xF6, 0x61, 0xF0, 0x48, 0xCF, 0xB8, 0x86, 0xE7, 0x3F,
+	0xCC, 0x57, 0xC3, 0x35, 0xFA, 0xB7, 0xFB, 0x47, 0x7F, 0xC1, 0x00, 0xFF, 0x00, 0xE0, 0xB8, 0x9F,
+	0xB5, 0x8F, 0x8C, 0x34, 0x7F, 0x1D, 0x7C, 0x6D, 0xD3, 0x3C, 0x09, 0xA8, 0x6A, 0x5A, 0x0F, 0x84,
+	0xAC, 0x3C, 0x35, 0xA6, 0xCD, 0x6B, 0xE2, 0x2B, 0x2B, 0x70, 0x9A, 0x75, 0x98, 0x71, 0x6F, 0x11,
+	0x11, 0x22, 0x86, 0x2A, 0x24, 0x6F, 0x9C, 0x8D, 0xCD, 0x9E, 0x73, 0x81, 0x5C, 0x01, 0xFF, 0x00,
+	0x83, 0x58, 0xFF, 0x00, 0xE0, 0xAC, 0x4B, 0xCF, 0xFC, 0x22, 0x1E, 0x0D, 0xEB, 0x8F, 0xF9, 0x1C,
+	0xA0, 0xAC, 0xDC, 0x65, 0x7D, 0x8D, 0xA3, 0x52, 0x9C, 0x63, 0x6B, 0x9F, 0x9C, 0xD6, 0xD6, 0xD7,
+	0x37, 0xD7, 0x51, 0x58, 0xD9, 0x40, 0xD2, 0xDC, 0x4D, 0x2A, 0xC7, 0x6F, 0x0A, 0x1F, 0x99, 0xE4,
+	0x66, 0x01, 0x54, 0x7B, 0x92, 0x40, 0x1E, 0xE4, 0x57, 0xEC, 0xFF, 0x00, 0xEC, 0xD3, 0xF0, 0xA2,
+	0xD7, 0xE0, 0x7F, 0xC0, 0x8F, 0x0B, 0x7C, 0x2E, 0x84, 0x22, 0xC9, 0xA6, 0xE9, 0x69, 0xF6, 0xC2,
+	0xBF, 0x28, 0x7B, 0x87, 0x25, 0xE6, 0x6C, 0x1F, 0x59, 0x5A, 0x43, 0xED, 0x9C, 0x57, 0x9E, 0xFE,
+	0xC8, 0x5F, 0xF0, 0x42, 0x0F, 0xDA, 0x13, 0xF6, 0x1B, 0xFD, 0xA6, 0xFC, 0x1F, 0xFB, 0x4B, 0x7E,
+	0xDF, 0xBE, 0x03, 0xD1, 0xEF, 0xBE, 0x1E, 0xF8, 0x67, 0x54, 0x17, 0x57, 0x1A, 0x5F, 0x87, 0xF5,
+	0x8B, 0x6D, 0x42, 0x6B, 0xDB, 0xC0, 0x3F, 0xD1, 0xE2, 0x68, 0x5D, 0xD1, 0x4C, 0x5E, 0x61, 0x56,
+	0x62, 0x4F, 0x45, 0xE0, 0x13, 0x8A, 0xFD, 0x4C, 0x1F, 0xB7, 0x6F, 0xEC, 0x28, 0xB9, 0x27, 0xF6,
+	0x4A, 0x99, 0x72, 0x72, 0xDB, 0x3C, 0x33, 0xA5, 0xE0, 0xFF, 0x00, 0xE4, 0x51, 0xCF, 0xF9, 0xEF,
+	0x5B, 0x53, 0x8F, 0x2E, 0xA7, 0x3E, 0x22, 0xA7, 0x35, 0x92, 0x67, 0x81, 0xFE, 0xC4, 0x84, 0x0F,
+	0xDA, 0xA7, 0xC1, 0x39, 0x23, 0xFE, 0x43, 0x0B, 0xFC, 0x5F, 0xEC, 0xB5, 0x4D, 0xFF, 0x00, 0x05,
+	0x1D, 0x65, 0x1F, 0xB6, 0x0F, 0x8A, 0x86, 0xE1, 0xF7, 0x6D, 0x78, 0xCF, 0xFD, 0x3B, 0xA5, 0x7D,
+	0x45, 0xF0, 0x37, 0xF6, 0xC0, 0xFD, 0x90, 0xBC, 0x7B, 0xF1, 0x67, 0x44, 0xF0, 0x8F, 0x80, 0xBF,
+	0x67, 0x09, 0xF4, 0x7D, 0x5E, 0xFE, 0xF3, 0xCA, 0xB1, 0xD4, 0x9B, 0x41, 0xD3, 0xE2, 0x10, 0x3E,
+	0x0F, 0xCD, 0xBA, 0x39, 0x4B, 0x0F, 0xC0, 0x13, 0x55, 0x7F, 0x69, 0xCF, 0xDA, 0xA7, 0xF6, 0x40,
+	0xF8, 0x6F, 0xF1, 0xA7, 0x58, 0xF0, 0x77, 0xC5, 0x1F, 0xD9, 0x62, 0x1F, 0x11, 0xEB, 0x96, 0xBE,
+	0x4F, 0xDB, 0x35, 0x86, 0xD0, 0xF4, 0xF9, 0xBC, 0xED, 0xD1, 0x86, 0x5F, 0x9E, 0x66, 0xDE, 0x70,
+	0x0E, 0x39, 0x1D, 0xAB, 0x43, 0x3A, 0x12, 0x94, 0x64, 0xEC, 0x8F, 0xCF, 0x42, 0xCA, 0x3A, 0x9A,
+	0xFB, 0x73, 0xFE, 0x09, 0xCC, 0xEA, 0x9F, 0xB1, 0x9F, 0xC6, 0x2D, 0xE7, 0xA2, 0xDF, 0x73, 0xFF,
+	0x00, 0x70, 0xC1, 0x59, 0xC7, 0xF6, 0xE2, 0xFF, 0x00, 0x82, 0x7F, 0x8F, 0xBB, 0xFB, 0x10, 0x5B,
+	0x83, 0xD3, 0xFE, 0x45, 0x9D, 0x27, 0xFF, 0x00, 0x8A, 0xAF, 0x79, 0xFD, 0x98, 0xBE, 0x39, 0x7E,
+	0xCF, 0xDF, 0x10, 0xBE, 0x08, 0x78, 0xD3, 0xC6, 0x9F, 0x0A, 0xFE, 0x09, 0x47, 0xE1, 0x9D, 0x0F,
+	0x45, 0x69, 0xBF, 0xB6, 0xB4, 0x98, 0x74, 0xBB, 0x48, 0x7E, 0xDC, 0x12, 0xD4, 0x48, 0xFF, 0x00,
+	0x24, 0x27, 0x63, 0x6E, 0x8B, 0x09, 0xF3, 0x62, 0x83, 0x4A, 0xD2, 0x97, 0xB3, 0xD9, 0x9F, 0x9A,
+	0x4A, 0xC8, 0xC1, 0x70, 0xEB, 0xF7, 0x7F, 0xBC, 0x3D, 0x69, 0xCB, 0x80, 0xC0, 0x66, 0xBE, 0xD0,
+	0x4F, 0xDB, 0xBF, 0xF6, 0x15, 0x0A, 0x3F, 0xE3, 0x12, 0xEE, 0x39, 0x1F, 0xF4, 0x2D, 0x69, 0x7F,
+	0xFC, 0x77, 0xFC, 0xE2, 0x86, 0xFD, 0xBB, 0xBF, 0x61, 0x36, 0x18, 0x1F, 0xB2, 0x54, 0xC7, 0xFD,
+	0xEF, 0x0C, 0xE9, 0x7F, 0xFC, 0x76, 0x83, 0x94, 0xE3, 0xFC, 0x7B, 0x2C, 0x4D, 0xFF, 0x00, 0x04,
+	0xB2, 0xF0, 0x5B, 0x89, 0x17, 0x6F, 0xFC, 0x25, 0xAF, 0xF3, 0x6E, 0xE0, 0xFF, 0x00, 0xA4, 0x5D,
+	0x57, 0xCB, 0xEA, 0x54, 0xF4, 0x75, 0xE8, 0x3F, 0x88, 0x7A, 0x0A, 0xFD, 0x1F, 0xF1, 0x07, 0xED,
+	0x1D, 0xFB, 0x3A, 0x69, 0xFF, 0x00, 0xB2, 0xCE, 0x8B, 0xF1, 0x87, 0x52, 0xF8, 0x27, 0x25, 0xC7,
+	0x83, 0xEF, 0xB5, 0xC6, 0x87, 0x4F, 0xF0, 0xD8, 0xD2, 0xAC, 0xCB, 0x41, 0x26, 0xE9, 0x54, 0xB7,
+	0x94, 0x5C, 0x46, 0x3E, 0x64, 0x66, 0xE1, 0x89, 0xF9, 0xAB, 0xCC, 0x0F, 0xED, 0xDF, 0xFB, 0x0A,
+	0x15, 0xC3, 0x7E, 0xC9, 0xD7, 0x0D, 0xFF, 0x00, 0x72, 0xD6, 0x99, 0xC7, 0x1F, 0xF5, 0xDB, 0xEB,
+	0x40, 0x1F, 0x21, 0xF8, 0x20, 0xA8, 0xF1, 0xA6, 0x91, 0xB9, 0x97, 0x9D, 0x52, 0xDF, 0x1F, 0x37,
+	0xFD, 0x34, 0x5A, 0xFA, 0x2F, 0xFE, 0x0A, 0xA2, 0xE9, 0xFF, 0x00, 0x0B, 0x83, 0xC2, 0xC0, 0xB2,
+	0xFF, 0x00, 0xC8, 0x9F, 0x11, 0xFF, 0x00, 0xC8, 0xCF, 0x5D, 0xDE, 0x89, 0xFB, 0x71, 0xFE, 0xC3,
+	0xDA, 0x8E, 0xBD, 0x6B, 0x69, 0x63, 0xFB, 0x29, 0xCB, 0x0C, 0xF3, 0x5C, 0x24, 0x50, 0xCC, 0xDE,
+	0x1B, 0xD3, 0x06, 0xC6, 0x67, 0x00, 0x36, 0x44, 0xB9, 0x18, 0x21, 0x4F, 0x1C, 0xD7, 0xA2, 0x7E,
+	0xD4, 0xDF, 0xB4, 0x6F, 0xEC, 0xE9, 0xF0, 0x73, 0xC6, 0x5A, 0x3E, 0x8B, 0xF1, 0x8F, 0xE0, 0xA4,
+	0x9E, 0x24, 0xBE, 0xBA, 0xD0, 0xE2, 0xB8, 0xB3, 0xBA, 0x8F, 0x49, 0xB3, 0x9F, 0xC9, 0x8B, 0x7B,
+	0x2E, 0xCF, 0xDF, 0x3A, 0x95, 0xE4, 0x67, 0x03, 0x22, 0x80, 0xF3, 0x3F, 0x38, 0x54, 0x8C, 0x67,
+	0x72, 0xF6, 0xFE, 0x2A, 0xF7, 0xFF, 0x00, 0xF8, 0x26, 0x6B, 0x28, 0xFD, 0xAC, 0x74, 0x95, 0xDC,
+	0xBF, 0xF2, 0x0B, 0xBD, 0x3F, 0x7B, 0xFE, 0x98, 0x9A, 0xF5, 0x11, 0xFB, 0x77, 0xFE, 0xC2, 0x7B,
+	0x79, 0xFD, 0x92, 0xEE, 0x0F, 0xFB, 0x5F, 0xF0, 0x8D, 0x69, 0x9F, 0xFC, 0x7A, 0xBD, 0x03, 0xF6,
+	0x61, 0xFD, 0xA9, 0xBF, 0x65, 0x9F, 0x8A, 0xDF, 0x16, 0xAD, 0x7C, 0x1F, 0xF0, 0xAF, 0xE0, 0x04,
+	0x9E, 0x1F, 0xD6, 0x2E, 0x2D, 0xEE, 0x25, 0x87, 0x52, 0x6D, 0x16, 0xC6, 0x0D, 0x8A, 0xA9, 0x96,
+	0x1B, 0xE1, 0x90, 0xB7, 0xCC, 0xA3, 0x1C, 0x03, 0xEF, 0x40, 0x1F, 0x52, 0x0E, 0x94, 0x51, 0xDF,
+	0xA5, 0x14, 0x00, 0x51, 0x45, 0x14, 0x01, 0xF9, 0xEB, 0xFF, 0x00, 0x05, 0x6C, 0x20, 0xFC, 0x76,
+	0xF0, 0xF8, 0x07, 0xFE, 0x65, 0xA0, 0x31, 0xFF, 0x00, 0x6D, 0xDE, 0xBE, 0x55, 0x0A, 0xC0, 0x60,
+	0xA9, 0xFC, 0xAB, 0xEF, 0xEF, 0xDB, 0xCB, 0xF6, 0x37, 0xF8, 0xC1, 0xFB, 0x47, 0xFC, 0x4F, 0xD3,
+	0x3C, 0x4D, 0xF0, 0xF6, 0x4D, 0x27, 0xEC, 0xB6, 0x3A, 0x2F, 0xD9, 0x66, 0xFE, 0xD0, 0xBE, 0x68,
+	0xC8, 0x63, 0x2B, 0xB7, 0x03, 0x6B, 0x67, 0x8A, 0xF1, 0x1F, 0xF8, 0x75, 0x7F, 0xED, 0x43, 0xE9,
+	0xE1, 0xBF, 0xFC, 0x1C, 0x37, 0xFF, 0x00, 0x1A, 0xA0, 0x0C, 0xEF, 0xF8, 0x26, 0x77, 0xFC, 0x9D,
+	0x7E, 0x97, 0xFF, 0x00, 0x60, 0xBB, 0xEF, 0xFD, 0x10, 0xD5, 0xE7, 0xFF, 0x00, 0xB5, 0x50, 0x2D,
+	0xFB, 0x4A, 0xF8, 0xEC, 0x2F, 0x38, 0xF1, 0x3D, 0xD6, 0x71, 0xCE, 0x3F, 0x79, 0x5F, 0x51, 0xFE,
+	0xC7, 0x1F, 0xB0, 0xC7, 0xC7, 0x0F, 0x80, 0x7F, 0x1C, 0xAC, 0xFE, 0x22, 0xF8, 0xE3, 0xFB, 0x1F,
+	0xFB, 0x3E, 0xDE, 0xC6, 0xE6, 0x39, 0x3E, 0xC3, 0xA8, 0x19, 0x24, 0xDC, 0xF1, 0x15, 0x5C, 0x03,
+	0x1A, 0xF7, 0xEB, 0xCD, 0x72, 0x9F, 0x1B, 0xBF, 0xE0, 0x9C, 0xBF, 0xB4, 0x37, 0xC4, 0x8F, 0x8C,
+	0x5E, 0x26, 0xF1, 0xEF, 0x87, 0x1F, 0x40, 0x6B, 0x0D, 0x5B, 0x5D, 0xB8, 0xBA, 0xB3, 0x37, 0x3A,
+	0xA3, 0x24, 0x9B, 0x19, 0x8E, 0x32, 0x3C, 0xB6, 0xC7, 0x1E, 0xF4, 0xBB, 0x07, 0x4B, 0x1F, 0x24,
+	0x60, 0x8E, 0xA2, 0xBE, 0xC0, 0xFF, 0x00, 0x82, 0x7E, 0xF3, 0xFB, 0x2F, 0xFC, 0x62, 0x53, 0xFF,
+	0x00, 0x40, 0xD6, 0xEB, 0xFF, 0x00, 0x5E, 0x77, 0x15, 0xC7, 0xFF, 0x00, 0xC3, 0xAC, 0xBF, 0x6A,
+	0x0F, 0xEF, 0x78, 0x73, 0xFF, 0x00, 0x07, 0x0D, 0xFF, 0x00, 0xC6, 0xAB, 0xDE, 0xBF, 0x65, 0x8F,
+	0xD9, 0x3F, 0xE2, 0xB7, 0xC1, 0x4F, 0x82, 0x7F, 0x10, 0x7C, 0x09, 0xE3, 0x33, 0xA6, 0xAD, 0xF7,
+	0x89, 0x6C, 0xDA, 0x3D, 0x37, 0xEC, 0x77, 0xC6, 0x45, 0x0D, 0xF6, 0x69, 0x53, 0xE7, 0x3B, 0x57,
+	0x1F, 0x33, 0x0E, 0xD4, 0xF7, 0xB8, 0x2F, 0x8B, 0x53, 0xF3, 0xCE, 0x2C, 0xB4, 0x4A, 0xEA, 0x32,
+	0xBB, 0x7A, 0x8F, 0xA0, 0xA7, 0x60, 0xFA, 0x7F, 0xF5, 0xEB, 0xE8, 0xE8, 0xFF, 0x00, 0xE0, 0x95,
+	0xDF, 0xB5, 0x00, 0x01, 0x73, 0xE1, 0xAF, 0x95, 0x42, 0xF1, 0xAC, 0x36, 0x78, 0xF5, 0xFD, 0xD7,
+	0xF5, 0xA7, 0x1F, 0xF8, 0x25, 0x8F, 0xED, 0x40, 0x06, 0x4F, 0xFC, 0x23, 0xBF, 0xF8, 0x38, 0x6F,
+	0xFE, 0x34, 0x68, 0x03, 0x73, 0xF6, 0x93, 0xC1, 0xFF, 0x00, 0x82, 0x5E, 0x7C, 0x39, 0x00, 0xFF,
+	0x00, 0xCC, 0x5A, 0x0F, 0xFD, 0x0A, 0xEA, 0xBE, 0x2F, 0xAF, 0xD1, 0xEF, 0x8D, 0x7F, 0xB2, 0x3F,
+	0xC5, 0xEF, 0x17, 0x7E, 0xC5, 0x1E, 0x11, 0xF8, 0x0F, 0xA2, 0x41, 0xA7, 0x49, 0xAF, 0xE8, 0x7A,
+	0x84, 0x52, 0xDF, 0x2B, 0x5F, 0x6D, 0x80, 0x20, 0x33, 0xE4, 0xA3, 0x11, 0xCE, 0x3C, 0xC4, 0xED,
+	0xDF, 0xDA, 0xBE, 0x6C, 0x1F, 0xF0, 0x4B, 0x8F, 0xDA, 0xB0, 0x60, 0x36, 0x99, 0xA1, 0x9E, 0x3A,
+	0xFF, 0x00, 0x6B, 0x0F, 0xF0, 0xAF, 0xCF, 0xF8, 0x97, 0x2F, 0xC6, 0xE2, 0xB3, 0x0E, 0x6A, 0x50,
+	0x6D, 0x59, 0x74, 0x67, 0xF4, 0x77, 0x85, 0x5C, 0x4D, 0x90, 0xE5, 0x3C, 0x38, 0xE8, 0xE3, 0x71,
+	0x11, 0x84, 0xB9, 0xDB, 0xB3, 0x76, 0x7D, 0x3A, 0x1C, 0x07, 0xEC, 0x6B, 0xFF, 0x00, 0x27, 0x4D,
+	0xE0, 0x72, 0x47, 0xFC, 0xC7, 0x07, 0xFE, 0x80, 0xF5, 0xEA, 0x7F, 0xF0, 0x52, 0xA1, 0x9F, 0xDA,
+	0xDB, 0x59, 0x03, 0xFE, 0x81, 0x76, 0x1F, 0xFA, 0x20, 0x57, 0x43, 0xFB, 0x3A, 0x7F, 0xC1, 0x3B,
+	0xFF, 0x00, 0x68, 0xEF, 0x86, 0xDF, 0x1C, 0xBC, 0x31, 0xE3, 0xEF, 0x12, 0xE9, 0xBA, 0x3A, 0xD8,
+	0x69, 0x7A, 0x9F, 0x9F, 0x74, 0xD0, 0xEA, 0x6A, 0xEC, 0xA9, 0xB1, 0x86, 0x40, 0xC7, 0x3D, 0x6B,
+	0xD0, 0xBF, 0x6C, 0x5F, 0xD8, 0x63, 0xE3, 0x77, 0xC7, 0x6F, 0x8E, 0xDA, 0x87, 0xC4, 0x7F, 0x04,
+	0x4B, 0xA2, 0xFF, 0x00, 0x66, 0xDE, 0x58, 0xDA, 0xC5, 0x1F, 0xDB, 0x35, 0x36, 0x8D, 0xC1, 0x8E,
+	0x2D, 0xA7, 0xE5, 0x08, 0x7F, 0x9D, 0x7A, 0xDC, 0x33, 0x87, 0xA9, 0x81, 0xC2, 0xC9, 0x56, 0x5C,
+	0xAD, 0xBE, 0xBE, 0x87, 0xC3, 0xF8, 0xB1, 0x9B, 0x65, 0xB9, 0xC6, 0x71, 0x46, 0xAE, 0x0A, 0xA2,
+	0x9C, 0x54, 0x2C, 0xDC, 0x5D, 0xEC, 0xEF, 0xD4, 0xF8, 0x84, 0x07, 0xC6, 0x47, 0xCB, 0xD0, 0xEE,
+	0x23, 0x81, 0x83, 0xDF, 0xDA, 0xBD, 0xFB, 0xC0, 0x7F, 0xB2, 0xFF, 0x00, 0x82, 0x3F, 0x6C, 0x2F,
+	0xF8, 0x25, 0xEF, 0xC6, 0xEF, 0x82, 0x1E, 0x35, 0xB4, 0x5F, 0x27, 0x50, 0x69, 0x2E, 0x34, 0xBB,
+	0xA6, 0x19, 0x36, 0x77, 0xD0, 0x5B, 0x2C, 0xB6, 0xF3, 0xA1, 0xE9, 0xB9, 0x65, 0x51, 0xCF, 0x70,
+	0x48, 0xEF, 0x5A, 0x1F, 0xF0, 0xEB, 0x7F, 0xDA, 0x6C, 0x73, 0xE6, 0xF8, 0x6F, 0x3F, 0xC2, 0xDF,
+	0xDB, 0x0F, 0xC7, 0xBF, 0xFA, 0xBA, 0xFA, 0x23, 0xF6, 0x56, 0xFD, 0x96, 0x7E, 0x28, 0x7C, 0x20,
+	0xF8, 0x03, 0xE3, 0x8F, 0x86, 0xDE, 0x2F, 0x7D, 0x31, 0xB5, 0x2F, 0x11, 0x34, 0xDF, 0xD9, 0xFF,
+	0x00, 0x64, 0xBC, 0x32, 0x46, 0x03, 0xDB, 0x08, 0xC6, 0xE2, 0x54, 0x63, 0x93, 0xE9, 0xD0, 0x57,
+	0xD3, 0x2A, 0xB4, 0x67, 0xA4, 0x64, 0x8F, 0xCA, 0xD7, 0x34, 0x75, 0x3F, 0x91, 0xBF, 0x13, 0xF8,
+	0x67, 0x5B, 0xF0, 0x6F, 0x88, 0xEF, 0xBC, 0x27, 0xE2, 0x5B, 0x26, 0xB7, 0xD4, 0x74, 0xDB, 0x97,
+	0xB7, 0xBE, 0xB7, 0x65, 0xC7, 0x97, 0x2A, 0xB1, 0x0C, 0x3D, 0xBA, 0x7E, 0x5B, 0x7D, 0xEA, 0x8D,
+	0x7E, 0xA9, 0x7F, 0xC1, 0x72, 0x7F, 0xE0, 0x8C, 0x9F, 0xB4, 0x1F, 0xC0, 0xFF, 0x00, 0x05, 0x7F,
+	0xC3, 0x6F, 0x41, 0xA0, 0x69, 0xF7, 0x5A, 0x5D, 0xAB, 0x41, 0x67, 0xE3, 0x88, 0xF4, 0x5B, 0xA6,
+	0x95, 0xAD, 0xF7, 0x7C, 0x90, 0xDF, 0xB2, 0x6D, 0x1F, 0x21, 0x21, 0x62, 0x91, 0xB9, 0x20, 0x98,
+	0x8E, 0x30, 0x5C, 0x8F, 0xCA, 0xDC, 0xED, 0xE5, 0xBD, 0xC0, 0xE7, 0xAE, 0x2B, 0x19, 0x47, 0x95,
+	0x9E, 0x95, 0x39, 0xF3, 0xC5, 0x05, 0x14, 0x6E, 0x1E, 0xB4, 0x67, 0x3D, 0x2A, 0x4D, 0x0E, 0xBB,
+	0xE0, 0x36, 0x7F, 0xE1, 0x71, 0xF8, 0x77, 0xFE, 0xC2, 0x1F, 0xFB, 0x23, 0x57, 0xD8, 0xCC, 0x3E,
+	0x6F, 0xBB, 0x5F, 0x1C, 0xFC, 0x06, 0x07, 0xFE, 0x17, 0x17, 0x87, 0x8E, 0x3F, 0xE5, 0xFB, 0xFF,
+	0x00, 0x64, 0x6A, 0xFB, 0x1D, 0xCF, 0xCD, 0x8C, 0xD6, 0xD4, 0xBE, 0x16, 0x70, 0xE2, 0x7E, 0x24,
+	0x25, 0x14, 0x50, 0x3E, 0x61, 0xB8, 0x2E, 0x41, 0xEE, 0x2B, 0x63, 0x10, 0xA4, 0x20, 0x60, 0xE3,
+	0x8A, 0x76, 0xC7, 0xFE, 0xE9, 0xFC, 0xA9, 0x19, 0x5B, 0x18, 0x2A, 0x68, 0x03, 0xEF, 0x2F, 0x84,
+	0x78, 0xFF, 0x00, 0x85, 0x59, 0xE1, 0xD3, 0x81, 0xFF, 0x00, 0x20, 0x6B, 0x7E, 0xDF, 0xEC, 0x0A,
+	0xE8, 0xAB, 0x9D, 0xF8, 0x46, 0x4F, 0xFC, 0x2A, 0xBF, 0x0E, 0x8C, 0x7F, 0xCC, 0x1E, 0xDF, 0xFF,
+	0x00, 0x45, 0x8A, 0xE8, 0xAA, 0xA2, 0x66, 0x14, 0x51, 0x45, 0x50, 0x05, 0x14, 0x51, 0x40, 0x05,
+	0x57, 0xD5, 0x78, 0xD2, 0xAE, 0xB2, 0x3F, 0xE5, 0xDE, 0x4F, 0xFD, 0x04, 0xD5, 0x8A, 0xAF, 0xAB,
+	0x2B, 0x1D, 0x2A, 0xE3, 0x8F, 0xF9, 0x77, 0x7F, 0xFD, 0x04, 0xD5, 0x44, 0x0F, 0xBE, 0xB4, 0xD2,
+	0xDF, 0xD9, 0xB6, 0xE4, 0x7F, 0xCF, 0x05, 0xFE, 0x2F, 0xF6, 0x47, 0xB5, 0x4C, 0x0B, 0x67, 0xE6,
+	0x1F, 0x99, 0xA8, 0x74, 0xD5, 0x61, 0xA6, 0xDA, 0xE5, 0x4F, 0xFC, 0x7B, 0xA7, 0x51, 0xED, 0x53,
+	0x56, 0x20, 0x04, 0xFF, 0x00, 0x75, 0x7F, 0x2A, 0x15, 0x9F, 0xBF, 0xFE, 0x85, 0xFF, 0x00, 0xD6,
+	0xA3, 0x27, 0x38, 0xC1, 0xFC, 0xBD, 0xB3, 0x46, 0x08, 0xEA, 0x28, 0x00, 0x2C, 0x71, 0xC9, 0xAF,
+	0x4C, 0xFD, 0x9F, 0x89, 0xFE, 0xCA, 0xD5, 0x07, 0xA5, 0xF2, 0x60, 0xFF, 0x00, 0xDB, 0x25, 0xAF,
+	0x33, 0xAF, 0x4B, 0xFD, 0x9F, 0x88, 0xFE, 0xCA, 0xD5, 0x06, 0xE1, 0xFF, 0x00, 0x1F, 0xC9, 0xDF,
+	0xFE, 0x99, 0x2D, 0x00, 0x7A, 0x0D, 0x14, 0x51, 0x40, 0x05, 0x47, 0x75, 0x34, 0x56, 0x91, 0x34,
+	0xF7, 0x0E, 0xB1, 0xAA, 0xA9, 0x66, 0x77, 0x60, 0x02, 0x80, 0x09, 0x27, 0x3D, 0xA9, 0xEC, 0xCA,
+	0xA3, 0x2D, 0xEA, 0x07, 0xEB, 0x5E, 0x59, 0xFB, 0x56, 0x78, 0x7B, 0xE3, 0x37, 0xC4, 0x2F, 0x86,
+	0x17, 0xDF, 0x0E, 0x3E, 0x09, 0x2D, 0xAC, 0x77, 0xFA, 0xA6, 0x22, 0xBE, 0xBE, 0xBD, 0xBB, 0x30,
+	0xA4, 0x56, 0xA4, 0x90, 0xEA, 0xAC, 0x15, 0x89, 0x66, 0x03, 0x6E, 0x00, 0xE9, 0x9C, 0x91, 0xDC,
+	0x03, 0xC8, 0xFF, 0x00, 0xE0, 0xA1, 0x3E, 0x2B, 0xD1, 0xBC, 0x77, 0xFB, 0x1D, 0xC3, 0xE3, 0xBD,
+	0x0E, 0x6F, 0x32, 0xCB, 0x54, 0xF1, 0x05, 0xAC, 0x96, 0x52, 0x6D, 0x3C, 0xC2, 0x1D, 0xC2, 0x9F,
+	0x6D, 0xDC, 0xBF, 0x3C, 0xFC, 0xD8, 0xEC, 0x2B, 0xF3, 0xFC, 0xE4, 0xF6, 0xE9, 0x5F, 0xA2, 0xDF,
+	0x15, 0x7F, 0x65, 0x5F, 0x8A, 0x3E, 0x2E, 0xFD, 0x89, 0xBC, 0x2F, 0xFB, 0x3D, 0x69, 0x13, 0x69,
+	0xA3, 0x5E, 0xD1, 0xD6, 0xCD, 0x6E, 0xA4, 0x9A, 0xF0, 0xAC, 0x1F, 0xBA, 0xC9, 0x62, 0x1B, 0x69,
+	0xCF, 0xDE, 0x1D, 0xBF, 0x1E, 0xC7, 0xE7, 0x71, 0xFF, 0x00, 0x04, 0xB6, 0xFD, 0xA6, 0x8F, 0xCC,
+	0x24, 0xF0, 0xDF, 0x3C, 0xE3, 0xFB, 0x61, 0xF8, 0xFF, 0x00, 0xC8, 0x75, 0x12, 0xAD, 0x4E, 0x9B,
+	0xB4, 0x9A, 0x03, 0x85, 0xFD, 0x89, 0x1B, 0x6F, 0xED, 0x55, 0xE0, 0xAC, 0x9C, 0x7F, 0xC4, 0xE1,
+	0x7A, 0xF7, 0xF9, 0x5A, 0xA6, 0xFF, 0x00, 0x82, 0x8E, 0xFF, 0x00, 0xC9, 0xE1, 0x78, 0xA8, 0x67,
+	0xF8, 0x6D, 0x3F, 0xF4, 0x99, 0x2B, 0xDA, 0xFF, 0x00, 0x66, 0xDF, 0xF8, 0x27, 0xBF, 0xC7, 0xEF,
+	0x85, 0x7F, 0x1C, 0x3C, 0x3B, 0xE3, 0xFF, 0x00, 0x13, 0xCB, 0xA1, 0x7F, 0x67, 0xE9, 0x97, 0xE2,
+	0x6B, 0xB5, 0xB5, 0xD5, 0x59, 0xDC, 0xA6, 0x0F, 0x45, 0xF2, 0xC6, 0x79, 0xC7, 0x19, 0xA5, 0xFD,
+	0xAF, 0xBF, 0x60, 0x3F, 0xDA, 0x0F, 0xE3, 0x67, 0xED, 0x05, 0xAE, 0x7C, 0x48, 0xF0, 0x4D, 0x9E,
+	0x92, 0xDA, 0x5E, 0xA0, 0x20, 0xFB, 0x3B, 0x5D, 0x6A, 0x81, 0x1F, 0xE4, 0x85, 0x14, 0xFC, 0xB8,
+	0xE3, 0x90, 0x68, 0xA7, 0x52, 0x13, 0xD6, 0x2E, 0xE7, 0x45, 0x17, 0xCB, 0x2B, 0xB3, 0xE2, 0x1A,
+	0xFB, 0x73, 0xFE, 0x09, 0xCE, 0xD8, 0xFD, 0x8C, 0xFE, 0x31, 0x12, 0x3E, 0xF2, 0xDF, 0x11, 0xEF,
+	0xFF, 0x00, 0x12, 0xB1, 0xFE, 0x15, 0xE6, 0xBF, 0xF0, 0xEA, 0xBF, 0xDA, 0xB8, 0x73, 0xFD, 0x9B,
+	0xA0, 0xFF, 0x00, 0xE0, 0xE8, 0x7F, 0xF1, 0x35, 0xF4, 0x97, 0xEC, 0x83, 0xFB, 0x28, 0x7C, 0x59,
+	0xF8, 0x2F, 0xFB, 0x3D, 0x7C, 0x40, 0xF8, 0x6D, 0xE3, 0x7B, 0x5D, 0x3D, 0x75, 0x4F, 0x12, 0x35,
+	0xC0, 0xD3, 0x56, 0xDE, 0xF3, 0xCC, 0x43, 0xBE, 0xCC, 0x42, 0x37, 0x10, 0x3E, 0x5F, 0x98, 0x9F,
+	0xE7, 0xD3, 0x9A, 0xB3, 0x4A, 0xD5, 0x23, 0x2A, 0x76, 0xB9, 0xF9, 0xE6, 0xA4, 0x15, 0x50, 0xA7,
+	0xB7, 0xF9, 0xFE, 0x74, 0xE0, 0x1F, 0x39, 0x0A, 0x7F, 0x2A, 0xFA, 0x39, 0x7F, 0xE0, 0x96, 0x1F,
+	0xB5, 0x1A, 0x46, 0xB1, 0xB3, 0xF8, 0x6D, 0x82, 0x80, 0xAB, 0xFF, 0x00, 0x13, 0x89, 0x3F, 0xAC,
+	0x74, 0x7F, 0xC3, 0xAC, 0x7F, 0x6A, 0x1F, 0xBD, 0xFF, 0x00, 0x14, 0xEF, 0xB7, 0xFC, 0x4E, 0x1B,
+	0x83, 0xEB, 0xCC, 0x54, 0x1C, 0x66, 0xA7, 0x8F, 0xF0, 0x3F, 0xE0, 0x95, 0xFE, 0x0C, 0x2C, 0x7F,
+	0xE6, 0x6B, 0x90, 0xFF, 0x00, 0xE4, 0xC5, 0xCD, 0x7C, 0xB6, 0x15, 0x87, 0x25, 0x7D, 0x3F, 0x95,
+	0x7D, 0xF1, 0xE2, 0x6F, 0xD8, 0xEF, 0xE3, 0x16, 0xB5, 0xFB, 0x14, 0x78, 0x7F, 0xF6, 0x76, 0xB3,
+	0x97, 0x4B, 0xFE, 0xDE, 0xD2, 0xBC, 0x44, 0xD7, 0x37, 0x1B, 0xAF, 0x19, 0x60, 0x29, 0xBE, 0x69,
+	0x46, 0x1B, 0x69, 0xE7, 0x6C, 0x83, 0xB7, 0xAF, 0xBD, 0x78, 0xBA, 0x7F, 0xC1, 0x2C, 0x3F, 0x6A,
+	0x10, 0xB9, 0xFF, 0x00, 0x8A, 0x6B, 0xAE, 0x78, 0xD6, 0x1B, 0x1F, 0xFA, 0x2A, 0x80, 0x3C, 0x0F,
+	0xC1, 0x0A, 0xC7, 0xC6, 0x7A, 0x47, 0x1F, 0xF3, 0x14, 0xB7, 0xFF, 0x00, 0xD1, 0x8B, 0x5F, 0x47,
+	0x7F, 0xC1, 0x55, 0x08, 0x3F, 0x17, 0xFC, 0x2A, 0x14, 0xFC, 0xDF, 0xF0, 0x88, 0xC6, 0x3F, 0xF2,
+	0x2B, 0x54, 0x3E, 0x1C, 0xFF, 0x00, 0x82, 0x61, 0xFE, 0xD3, 0x3A, 0x3F, 0x88, 0x6C, 0x35, 0x6B,
+	0xA3, 0xE1, 0xEF, 0x2E, 0xDA, 0xF6, 0x29, 0x64, 0xDB, 0xAB, 0x31, 0x3B, 0x55, 0xC1, 0x3F, 0xF2,
+	0xCF, 0xD0, 0x71, 0xC8, 0xAF, 0x58, 0xFD, 0xB6, 0xBF, 0x63, 0x8F, 0x8C, 0x7F, 0xB4, 0x77, 0x8E,
+	0x74, 0x3F, 0x12, 0xFC, 0x3E, 0x6D, 0x23, 0xEC, 0xD6, 0x3E, 0x1B, 0x4B, 0x59, 0x85, 0xF5, 0xF3,
+	0x45, 0x87, 0xF3, 0x19, 0xB8, 0xF9, 0x5B, 0x3F, 0xA6, 0x3B, 0xF3, 0x40, 0x1F, 0x05, 0x85, 0x61,
+	0xC6, 0xDF, 0x4A, 0xF7, 0xFF, 0x00, 0xF8, 0x26, 0x68, 0x3F, 0xF0, 0xD5, 0xDA, 0x57, 0xFD, 0x82,
+	0xAF, 0xB9, 0xFF, 0x00, 0xB6, 0x0D, 0x5A, 0x2D, 0xFF, 0x00, 0x04, 0xB1, 0xFD, 0xA8, 0x57, 0x91,
+	0xFF, 0x00, 0x08, 0xE7, 0xE1, 0xAC, 0x37, 0xFF, 0x00, 0x1A, 0xAF, 0x52, 0xFD, 0x8E, 0x7F, 0x61,
+	0x7F, 0x8E, 0x3F, 0x01, 0x3E, 0x39, 0x5A, 0x7C, 0x44, 0xF1, 0xC7, 0xF6, 0x3F, 0xF6, 0x75, 0xBD,
+	0x85, 0xD4, 0x52, 0x7D, 0x87, 0x50, 0x32, 0x49, 0xB9, 0xE3, 0x2A, 0xBB, 0x57, 0xCB, 0x5E, 0x33,
+	0xD7, 0x9C, 0xD0, 0x07, 0xDA, 0x59, 0xE6, 0x8A, 0x4E, 0xD4, 0xB4, 0x00, 0x51, 0x45, 0x14, 0x01,
+	0xF0, 0xCF, 0xFC, 0x14, 0xDB, 0xE3, 0x07, 0xC5, 0x4F, 0x87, 0x1F, 0x19, 0x74, 0x5D, 0x2F, 0xC0,
+	0x5F, 0x10, 0xB5, 0x6D, 0x26, 0xDE, 0xE3, 0xC3, 0xFE, 0x6C, 0xD0, 0x69, 0xF7, 0x8D, 0x1A, 0xBB,
+	0x19, 0x9C, 0x64, 0x81, 0xDF, 0x15, 0xF3, 0x6F, 0xFC, 0x35, 0x17, 0xED, 0x16, 0x7E, 0x63, 0xF1,
+	0xAF, 0xC4, 0x5F, 0xF8, 0x32, 0x6A, 0xF6, 0xFF, 0x00, 0xF8, 0x2B, 0x6F, 0xFC, 0x97, 0x5F, 0x0F,
+	0x8F, 0x5F, 0x0C, 0x8F, 0xFD, 0x1E, 0xF5, 0xF2, 0xA5, 0x00, 0x7D, 0x51, 0xFF, 0x00, 0x04, 0xFA,
+	0xF8, 0xE1, 0xF1, 0x87, 0xC7, 0x9F, 0xB4, 0xB6, 0x9D, 0xE1, 0xDF, 0x1A, 0xFC, 0x4B, 0xD6, 0x35,
+	0x4B, 0x16, 0xD3, 0xEF, 0x1D, 0xAD, 0x6F, 0x2F, 0x59, 0xE3, 0x24, 0x42, 0x48, 0x38, 0xF6, 0x35,
+	0xC4, 0xFE, 0xD2, 0x3F, 0xB4, 0x4F, 0xC7, 0x8F, 0x0E, 0xFC, 0x7E, 0xF1, 0x96, 0x83, 0xA0, 0xFC,
+	0x5C, 0xD7, 0xAC, 0xEC, 0xAD, 0x7C, 0x47, 0x75, 0x1D, 0xB5, 0xAD, 0xBE, 0xA0, 0xCB, 0x1C, 0x48,
+	0x1F, 0x01, 0x54, 0x76, 0x15, 0x77, 0xFE, 0x09, 0x9B, 0xFF, 0x00, 0x27, 0x5D, 0xA5, 0x91, 0xCF,
+	0xFC, 0x4B, 0x2F, 0x87, 0x1F, 0xF5, 0xC1, 0xAB, 0xCF, 0xBF, 0x6A, 0x9C, 0x1F, 0xDA, 0x57, 0xC7,
+	0x5B, 0x48, 0x3F, 0xF1, 0x53, 0x5D, 0x1E, 0x0F, 0xFD, 0x34, 0xA0, 0x7D, 0x3E, 0xE1, 0xA3, 0xF6,
+	0xA2, 0xFD, 0xA3, 0x01, 0xCF, 0xFC, 0x2E, 0xAF, 0x11, 0x7F, 0xE0, 0xC5, 0xAB, 0xEA, 0x2F, 0xD8,
+	0x8F, 0xE2, 0xB7, 0xC4, 0xBF, 0x19, 0xFE, 0xCE, 0x7F, 0x15, 0x3C, 0x41, 0xE2, 0xEF, 0x1C, 0xEA,
+	0x7A, 0x95, 0xF6, 0x9B, 0xA7, 0x33, 0x58, 0xDD, 0x5E, 0x5D, 0x33, 0x3C, 0x0D, 0xF6, 0x59, 0x8E,
+	0x54, 0xE7, 0x83, 0x90, 0x0F, 0xE1, 0x5F, 0x10, 0xD7, 0xD8, 0x1F, 0xF0, 0x4F, 0xDC, 0x1F, 0xD9,
+	0x7B, 0xE3, 0x10, 0x2D, 0xF7, 0xB4, 0xD6, 0xC1, 0xCF, 0x1F, 0xF1, 0xE7, 0x3F, 0x7F, 0xC6, 0x94,
+	0xB6, 0x1C, 0x7E, 0x24, 0x7C, 0xF4, 0x9F, 0xB5, 0x1F, 0xED, 0x18, 0x51, 0x47, 0xFC, 0x2E, 0xDF,
+	0x12, 0x7D, 0xD1, 0xF7, 0xB5, 0x37, 0x34, 0xBF, 0xF0, 0xD4, 0x3F, 0xB4, 0x68, 0xE5, 0x7E, 0x35,
+	0xF8, 0x88, 0x1E, 0x3A, 0x6A, 0x4D, 0xEB, 0x5C, 0x0A, 0x7F, 0xAB, 0x56, 0x1F, 0xDD, 0xFE, 0x82,
+	0x9D, 0xDF, 0x1B, 0xBD, 0xA9, 0x92, 0x7D, 0x99, 0xFB, 0x43, 0x7C, 0x55, 0xF8, 0x93, 0xA6, 0x7F,
+	0xC1, 0x39, 0xBC, 0x09, 0xE3, 0x7D, 0x37, 0xC7, 0x7A, 0xA4, 0x3A, 0xC5, 0xEE, 0xA7, 0x10, 0xBA,
+	0xD4, 0xA1, 0xBC, 0x75, 0x9A, 0x65, 0x26, 0xE7, 0x86, 0x60, 0x79, 0x1F, 0x2A, 0xFE, 0x42, 0xBE,
+	0x47, 0x3F, 0xB4, 0x8F, 0xED, 0x02, 0x7A, 0xFC, 0x68, 0xF1, 0x1F, 0xD3, 0xFB, 0x5A, 0x4F, 0x5A,
+	0xFA, 0x63, 0xF6, 0x94, 0x2A, 0x3F, 0xE0, 0x97, 0xBF, 0x0E, 0x49, 0xED, 0xAA, 0xC3, 0xFF, 0x00,
+	0xA1, 0x5D, 0x57, 0xC5, 0xE4, 0xF3, 0x8C, 0xFB, 0x57, 0xE7, 0x7C, 0x51, 0x88, 0xC4, 0x53, 0xCC,
+	0xBF, 0x77, 0x26, 0xB4, 0x5B, 0x33, 0xFA, 0x73, 0xC2, 0x1C, 0xB7, 0x2E, 0xC5, 0xF0, 0xBC, 0xA7,
+	0x5E, 0x94, 0x65, 0x2E, 0x77, 0xAC, 0x92, 0x6F, 0xA7, 0x56, 0x8F, 0x79, 0xFD, 0x93, 0x7E, 0x3C,
+	0xFC, 0x6A, 0xF1, 0x07, 0xED, 0x2B, 0xE0, 0xDD, 0x1B, 0x5D, 0xF8, 0xAD, 0xAF, 0x5E, 0x59, 0xCF,
+	0xAC, 0x04, 0xB8, 0xB5, 0xB9, 0xD4, 0x9D, 0xE3, 0x91, 0x76, 0x37, 0x04, 0x13, 0xD2, 0xBE, 0x91,
+	0xFD, 0xA7, 0xFE, 0x24, 0x78, 0xF7, 0x40, 0xF8, 0xD7, 0xAC, 0x69, 0x5A, 0x1F, 0x8B, 0xF5, 0x0B,
+	0x5B, 0x78, 0xD6, 0xDF, 0xCB, 0x86, 0x1B, 0xA6, 0x55, 0x5C, 0xC0, 0x84, 0xE0, 0x67, 0xD4, 0xD7,
+	0xC8, 0x3F, 0xB1, 0xA0, 0x6F, 0xF8, 0x6A, 0x8F, 0x02, 0xE1, 0x7F, 0xE6, 0x38, 0x3F, 0xF4, 0x07,
+	0xAF, 0xA9, 0x3F, 0x6B, 0x36, 0xCF, 0xC7, 0xBD, 0x71, 0x87, 0xF7, 0x6D, 0x87, 0xFE, 0x4B, 0xC7,
+	0x5F, 0x8A, 0x78, 0xC7, 0x99, 0x66, 0x98, 0x7E, 0x01, 0x8D, 0x5A, 0x35, 0x65, 0x19, 0x7B, 0x54,
+	0xAE, 0x9B, 0x4E, 0xD6, 0xDA, 0xFD, 0x8E, 0x7E, 0x26, 0xCB, 0xF2, 0xFA, 0x7C, 0x6B, 0x46, 0x94,
+	0x29, 0xC5, 0x47, 0xD9, 0x36, 0xD2, 0x4A, 0xD7, 0xE6, 0xED, 0x63, 0x9B, 0x5F, 0x8B, 0xFF, 0x00,
+	0x15, 0x09, 0xC7, 0xFC, 0x2C, 0x1D, 0x58, 0x7F, 0xDB, 0xF3, 0x9F, 0xEB, 0x5E, 0xD5, 0xFB, 0x3F,
+	0xF8, 0xE3, 0xC5, 0xFA, 0xBF, 0xC0, 0x5F, 0x88, 0x1A, 0xDE, 0xA3, 0xE2, 0x7B, 0xE9, 0xAF, 0x2C,
+	0x6C, 0x66, 0x7B, 0x3B, 0x89, 0xAE, 0x19, 0x9A, 0x26, 0x16, 0xC4, 0x82, 0x39, 0xE3, 0x9A, 0xF9,
+	0xC7, 0xE5, 0x03, 0x71, 0x75, 0xFF, 0x00, 0xBE, 0xAB, 0xDE, 0xBF, 0x66, 0xE5, 0x2B, 0xFB, 0x39,
+	0x7C, 0x4B, 0xC8, 0xFF, 0x00, 0x98, 0x74, 0xDF, 0xFA, 0x4A, 0xD5, 0xF9, 0x4F, 0x80, 0x99, 0xE6,
+	0x79, 0x8E, 0xF1, 0x0A, 0x8D, 0x2C, 0x45, 0x79, 0xCE, 0x1C, 0xB2, 0xBA, 0x94, 0x9B, 0x4E, 0xCB,
+	0xB3, 0x67, 0xCC, 0xF1, 0xB6, 0x0B, 0x07, 0x47, 0x22, 0x94, 0xA9, 0x53, 0x8A, 0x6A, 0x4B, 0x54,
+	0x92, 0x7A, 0xB3, 0xE2, 0x7F, 0x16, 0xFC, 0x6E, 0xF8, 0xC1, 0xF1, 0x17, 0xC1, 0xBA, 0x87, 0x80,
+	0x7C, 0x7B, 0xF1, 0x33, 0x56, 0xD5, 0xB4, 0x5D, 0x67, 0x4F, 0x7B, 0x3D, 0x53, 0x4B, 0xD4, 0x2E,
+	0x4C, 0x96, 0xF7, 0x70, 0x48, 0x9B, 0x5E, 0x29, 0x10, 0xF0, 0x51, 0x94, 0x95, 0x23, 0xB8, 0x26,
+	0xBD, 0x2F, 0xF6, 0x43, 0xFF, 0x00, 0x82, 0x2D, 0xFF, 0x00, 0xC1, 0x1A, 0xBF, 0x69, 0x5F, 0x86,
+	0x30, 0xEB, 0x72, 0x7E, 0xCC, 0x51, 0xC3, 0xAF, 0x69, 0xFB, 0x60, 0xD7, 0xAC, 0x3F, 0xE1, 0x26,
+	0xBD, 0xDD, 0x1C, 0x80, 0x61, 0x65, 0xC7, 0x9B, 0xF7, 0x1F, 0x07, 0x69, 0xF6, 0x65, 0x24, 0x95,
+	0x35, 0xE1, 0x70, 0x61, 0xA2, 0x8F, 0xD3, 0xCB, 0x03, 0xF4, 0xAE, 0xDF, 0xE0, 0x1F, 0xC6, 0xBF,
+	0x18, 0xFC, 0x04, 0xF8, 0x93, 0x63, 0xE3, 0xDF, 0x07, 0x5D, 0x2A, 0xC8, 0x24, 0x58, 0xB5, 0x0B,
+	0x59, 0x18, 0xF9, 0x57, 0x96, 0xE4, 0x80, 0xD0, 0xBF, 0xAF, 0xA8, 0x3F, 0xC2, 0xDC, 0x8F, 0xBC,
+	0xD8, 0xFF, 0x00, 0x40, 0xF9, 0x62, 0xCF, 0xC4, 0xF9, 0xA5, 0x1D, 0x8F, 0xA5, 0x07, 0xFC, 0x1B,
+	0x85, 0xFF, 0x00, 0x04, 0x82, 0x3D, 0x3F, 0x65, 0xDF, 0xFC, 0xB8, 0xAF, 0x7F, 0xF8, 0xED, 0x39,
+	0x7F, 0xE0, 0xDC, 0x1F, 0xF8, 0x24, 0x1A, 0xF3, 0xFF, 0x00, 0x0C, 0xB7, 0xFF, 0x00, 0x97, 0x25,
+	0xEF, 0xFF, 0x00, 0x1D, 0xAF, 0xB6, 0xB4, 0x2D, 0x49, 0x75, 0x8D, 0x22, 0xD7, 0x57, 0x48, 0x9A,
+	0x35, 0xBA, 0xB7, 0x8E, 0x65, 0x56, 0xEA, 0xBB, 0x90, 0x1C, 0x7E, 0x19, 0xAB, 0x94, 0xB9, 0x62,
+	0x3F, 0x69, 0x3E, 0xE7, 0xC4, 0x7A, 0x17, 0xFC, 0x1B, 0xBB, 0xFF, 0x00, 0x04, 0x96, 0xF0, 0xD6,
+	0xB3, 0x6F, 0xE2, 0x0D, 0x17, 0xF6, 0x64, 0xF2, 0x6E, 0xAD, 0x64, 0xDF, 0x0C, 0x9F, 0xF0, 0x91,
+	0x5E, 0x9D, 0xAD, 0x82, 0x3B, 0xCB, 0xEF, 0x5D, 0xA7, 0xFC, 0x39, 0x6F, 0xFE, 0x09, 0xCE, 0x5B,
+	0x9F, 0x80, 0xFF, 0x00, 0xF9, 0x5A, 0xBA, 0xFF, 0x00, 0xE3, 0x95, 0xF5, 0x45, 0x15, 0x6B, 0xDD,
+	0xD2, 0xC4, 0x73, 0x73, 0x6E, 0xCF, 0x95, 0x8F, 0xFC, 0x11, 0x6F, 0xFE, 0x09, 0xCF, 0x9E, 0x7E,
+	0x03, 0x64, 0x7A, 0x1D, 0x6A, 0xEF, 0xFA, 0x49, 0x5F, 0x91, 0xDF, 0xF0, 0x72, 0xCF, 0xC1, 0x0F,
+	0x87, 0x1F, 0xB0, 0x1F, 0xC4, 0xEF, 0x84, 0x7A, 0x17, 0xEC, 0xB1, 0xA2, 0x1F, 0x0D, 0xDA, 0xF8,
+	0xA3, 0x41, 0xD6, 0x6E, 0x35, 0xA8, 0xFC, 0xF7, 0xB8, 0xFB, 0x44, 0x90, 0x4D, 0x66, 0xB1, 0xB6,
+	0x65, 0x2C, 0x46, 0x16, 0x56, 0x1C, 0x1C, 0x73, 0x5F, 0xD0, 0xD1, 0x65, 0x51, 0x96, 0x35, 0xF8,
+	0x27, 0xFF, 0x00, 0x07, 0x93, 0x71, 0xF1, 0x97, 0xE0, 0x19, 0x3D, 0xFC, 0x33, 0xE2, 0x2C, 0x7B,
+	0xFF, 0x00, 0xA4, 0x69, 0xD5, 0x15, 0x3E, 0x13, 0x6A, 0x3A, 0xD4, 0x47, 0xE4, 0xDF, 0xFC, 0x34,
+	0xB7, 0xC6, 0x6F, 0xFA, 0x1B, 0x8F, 0xFE, 0x03, 0xA7, 0xF8, 0x52, 0xFF, 0x00, 0xC3, 0x4B, 0xFC,
+	0x66, 0xFF, 0x00, 0xA1, 0xB5, 0xBF, 0xF0, 0x1E, 0x3F, 0xF0, 0xAE, 0x0A, 0x8A, 0xC2, 0xF2, 0x3D,
+	0x0F, 0x67, 0x1E, 0xC7, 0xBD, 0x68, 0xFF, 0x00, 0xF0, 0x53, 0x1F, 0xDB, 0x3F, 0x42, 0xD2, 0xAD,
+	0xF4, 0x5D, 0x33, 0xE2, 0xDB, 0x47, 0x6F, 0x6B, 0x0A, 0xC5, 0x0C, 0x7F, 0xD9, 0xB0, 0x9D, 0xAA,
+	0xA0, 0x01, 0xD5, 0x6A, 0xC7, 0xFC, 0x3D, 0x1B, 0xF6, 0xDD, 0xFF, 0x00, 0xA2, 0xC4, 0x7F, 0xF0,
+	0x57, 0x07, 0xFF, 0x00, 0x13, 0x5F, 0x3E, 0xD1, 0x45, 0xE5, 0xDC, 0x5E, 0xCE, 0x1D, 0x8F, 0xA0,
+	0xBF, 0xE1, 0xE8, 0xDF, 0xB6, 0xEF, 0xFD, 0x16, 0x23, 0xFF, 0x00, 0x82, 0xB8, 0x3F, 0xF8, 0x9A,
+	0x3F, 0xE1, 0xE8, 0xDF, 0xB6, 0xEF, 0xFD, 0x16, 0x23, 0xFF, 0x00, 0x82, 0xB8, 0x3F, 0xF8, 0x9A,
+	0xF9, 0xF6, 0x8C, 0x1D, 0xDB, 0x71, 0xF3, 0x7F, 0x77, 0xB8, 0xA3, 0x9A, 0x5D, 0xC7, 0xEC, 0xE9,
+	0xF6, 0x3E, 0x82, 0xFF, 0x00, 0x87, 0xA3, 0x7E, 0xDB, 0xBF, 0xF4, 0x58, 0x8F, 0xFE, 0x0A, 0xE0,
+	0xFF, 0x00, 0xE2, 0x68, 0xFF, 0x00, 0x87, 0xA3, 0x7E, 0xDB, 0xBF, 0xF4, 0x58, 0x8F, 0xFE, 0x0A,
+	0xE0, 0xFF, 0x00, 0xE2, 0x6B, 0xE7, 0xD2, 0x0A, 0x8F, 0x9B, 0x8C, 0xF4, 0xCF, 0x7A, 0x08, 0x23,
+	0xA8, 0xA3, 0x9A, 0x7D, 0xC3, 0xD9, 0xD3, 0xEC, 0x7D, 0x05, 0xFF, 0x00, 0x0F, 0x46, 0xFD, 0xB7,
+	0x7F, 0xE8, 0xB1, 0x1F, 0xFC, 0x15, 0xC1, 0xFF, 0x00, 0xC4, 0xD3, 0x66, 0xFF, 0x00, 0x82, 0xA0,
+	0xFE, 0xDB, 0x37, 0x11, 0x34, 0x13, 0x7C, 0x5E, 0x66, 0x47, 0x52, 0xAE, 0xBF, 0xD9, 0x76, 0xFC,
+	0x82, 0x39, 0x1C, 0xA7, 0xA5, 0x7C, 0xFF, 0x00, 0x45, 0x1C, 0xD2, 0x0F, 0x67, 0x4F, 0xB1, 0xF5,
+	0xEC, 0x7F, 0xF0, 0x5D, 0xCF, 0xF8, 0x2A, 0x24, 0x48, 0xB1, 0x27, 0xED, 0x20, 0xDB, 0x55, 0x76,
+	0xA8, 0xFE, 0xC3, 0xB4, 0xC7, 0x4F, 0xFA, 0xE7, 0x4F, 0xFF, 0x00, 0x87, 0xF0, 0x7F, 0xC1, 0x51,
+	0xBF, 0xE8, 0xE3, 0x9B, 0xFF, 0x00, 0x04, 0x76, 0x9F, 0xFC, 0x45, 0x7C, 0x7F, 0x45, 0x2E, 0x69,
+	0x07, 0xB3, 0x87, 0x63, 0xF5, 0xFB, 0xFE, 0x08, 0x5B, 0xFF, 0x00, 0x05, 0x42, 0xFD, 0xB6, 0xFF,
+	0x00, 0x6C, 0x2F, 0xF8, 0x29, 0x17, 0x83, 0xFE, 0x02, 0x7E, 0xD0, 0x9F, 0x17, 0xCE, 0xBD, 0xE1,
+	0x7D, 0x53, 0x4D, 0xD5, 0xA5, 0xBE, 0xD2, 0xDB, 0x4D, 0x82, 0x11, 0x23, 0x43, 0xA7, 0xCF, 0x34,
+	0x67, 0x7C, 0x6A, 0x18, 0x61, 0xD1, 0x5B, 0xDF, 0x15, 0xFB, 0xD8, 0xBF, 0x0B, 0x3C, 0x10, 0x4E,
+	0x5B, 0x44, 0xFF, 0x00, 0xC8, 0xAD, 0xFD, 0x0F, 0xFF, 0x00, 0x5A, 0xBF, 0x99, 0x3F, 0xF8, 0x36,
+	0x49, 0xB6, 0xFF, 0x00, 0xC1, 0x61, 0xBE, 0x1F, 0xFF, 0x00, 0xD8, 0x1F, 0x5E, 0xFF, 0x00, 0xD3,
+	0x55, 0xCD, 0x7F, 0x51, 0xA1, 0x81, 0xF9, 0x73, 0xEF, 0x5B, 0xD3, 0x6D, 0xC4, 0xE1, 0xC4, 0x47,
+	0x96, 0xA6, 0x87, 0x3C, 0xDF, 0x0A, 0xBC, 0x08, 0x46, 0x3F, 0xB1, 0x7E, 0xBF, 0xBE, 0x7F, 0xF1,
+	0xAD, 0x2D, 0x03, 0xC2, 0xFA, 0x2F, 0x86, 0x23, 0x9A, 0x3D, 0x16, 0xD3, 0xCA, 0x59, 0xE4, 0x0F,
+	0x2F, 0xCC, 0x4E, 0xE2, 0x14, 0x0C, 0xF2, 0x7D, 0x05, 0x68, 0x51, 0x5A, 0x1C, 0xE1, 0x43, 0x10,
+	0xBC, 0xB7, 0x1F, 0x5A, 0x09, 0xC7, 0x5A, 0x6B, 0x13, 0x8D, 0xAB, 0xFC, 0xBA, 0xFB, 0x50, 0x07,
+	0x1D, 0xF1, 0xE3, 0xE3, 0x5F, 0x85, 0x3E, 0x01, 0xFC, 0x37, 0xBE, 0xF8, 0x8B, 0xE2, 0xC9, 0xB3,
+	0x1D, 0xA8, 0xDB, 0x6B, 0x6A, 0xAC, 0x16, 0x4B, 0xA9, 0xC8, 0xF9, 0x22, 0x5C, 0xF7, 0x27, 0xA9,
+	0xEC, 0xB9, 0x3C, 0xE3, 0x07, 0xF3, 0x2B, 0xC4, 0x7F, 0xB5, 0xD7, 0xED, 0x17, 0xE2, 0x4F, 0x13,
+	0x6A, 0x1E, 0x23, 0x5F, 0x8A, 0xFA, 0xC5, 0x8B, 0x6A, 0x37, 0x0D, 0x70, 0xF6, 0xD6, 0x57, 0x4D,
+	0x1C, 0x70, 0xEE, 0xE3, 0x62, 0x0E, 0xCA, 0xA0, 0x05, 0x03, 0xAE, 0x00, 0xCF, 0x41, 0x5A, 0xDF,
+	0xB6, 0x4F, 0xED, 0x25, 0xE2, 0x7F, 0xDA, 0x17, 0xE2, 0x7D, 0xD4, 0x77, 0x8C, 0xD6, 0xBA, 0x2E,
+	0x8B, 0x75, 0x35, 0xB6, 0x8F, 0xA6, 0xEF, 0xCE, 0xCC, 0x1C, 0x34, 0xCF, 0xCE, 0x0C, 0x8C, 0x70,
+	0x7F, 0xD9, 0x1F, 0x28, 0xE0, 0x66, 0xBC, 0x87, 0x8E, 0x80, 0x7F, 0x11, 0x3D, 0x7A, 0xF0, 0x3F,
+	0xC0, 0xD0, 0x07, 0xE8, 0x46, 0xBD, 0xE3, 0xEF, 0x1B, 0xB7, 0xEC, 0x3B, 0xE0, 0x6F, 0x17, 0x0F,
+	0x15, 0xDF, 0x8D, 0x52, 0xFA, 0xCE, 0xD4, 0xDD, 0x5F, 0x7D, 0xA5, 0xBC, 0xD9, 0x49, 0x56, 0xCE,
+	0x5B, 0x3E, 0xC3, 0xF2, 0xAF, 0x1F, 0x3F, 0x17, 0xFE, 0x29, 0xF5, 0x5F, 0x88, 0x5A, 0xBF, 0x38,
+	0xE3, 0xED, 0xCF, 0xC7, 0x5F, 0x7F, 0xA5, 0x7A, 0x4E, 0xB8, 0x7F, 0xE3, 0x5F, 0x5F, 0x0E, 0xDB,
+	0x1F, 0xF2, 0xE3, 0x68, 0x77, 0x0F, 0xA3, 0x1A, 0xF1, 0x32, 0x08, 0x3C, 0xF1, 0xDB, 0xF4, 0xAF,
+	0xE0, 0xAF, 0xA4, 0x36, 0x75, 0x9D, 0xE0, 0x78, 0xEA, 0x54, 0xF0, 0x95, 0xEA, 0x42, 0x3C, 0x91,
+	0xD2, 0x32, 0x69, 0x7D, 0xC9, 0x9F, 0xB4, 0x70, 0x1E, 0x07, 0x07, 0x5F, 0x25, 0xE6, 0xAB, 0x08,
+	0xB7, 0xCC, 0xF7, 0x49, 0xB3, 0xD3, 0x3E, 0x06, 0xFC, 0x4F, 0xF8, 0x8B, 0xAA, 0x7C, 0x5B, 0xF0,
+	0xFE, 0x9F, 0xAA, 0x78, 0xE3, 0x52, 0x9E, 0x19, 0xB5, 0x38, 0xD6, 0x58, 0x66, 0xBA, 0x76, 0x57,
+	0x19, 0xE8, 0x46, 0x79, 0xAF, 0x30, 0xFD, 0xBD, 0x7E, 0x39, 0x7C, 0x64, 0xF0, 0x7F, 0xED, 0x4F,
+	0xE2, 0x4F, 0x0F, 0x78, 0x57, 0xE2, 0x86, 0xB9, 0xA7, 0xD8, 0xDB, 0xAD, 0xAF, 0x93, 0x67, 0x6B,
+	0xA8, 0x3C, 0x71, 0xC6, 0x4C, 0x08, 0x4E, 0x14, 0x1F, 0x5A, 0xEC, 0xBE, 0x00, 0xAE, 0x7E, 0x33,
+	0xF8, 0x6C, 0x13, 0xD7, 0x54, 0x8F, 0xF9, 0xD7, 0x91, 0xFF, 0x00, 0xC1, 0x46, 0x82, 0x8F, 0xDA,
+	0xFF, 0x00, 0xC5, 0x44, 0x11, 0xFF, 0x00, 0x2E, 0x9D, 0xFF, 0x00, 0xE9, 0xD9, 0x2B, 0xF6, 0x1F,
+	0xA3, 0x46, 0x61, 0x98, 0x66, 0x1C, 0x35, 0x8A, 0x9E, 0x2E, 0xA4, 0xA6, 0xD4, 0xD5, 0x9C, 0x9B,
+	0x6F, 0x6F, 0x3B, 0xD8, 0xF9, 0xAE, 0x38, 0xC3, 0xE1, 0xE8, 0xE6, 0xD0, 0x54, 0xE2, 0x97, 0xBB,
+	0xB2, 0x49, 0x2D, 0xCE, 0x20, 0xFE, 0xD3, 0x3F, 0xB4, 0x30, 0x3C, 0x7C, 0x68, 0xF1, 0x1F, 0xD3,
+	0xFB, 0x5A, 0x4E, 0x6B, 0xEB, 0xFF, 0x00, 0xD8, 0x23, 0xE2, 0x7F, 0xC4, 0x5F, 0x17, 0x7E, 0xC9,
+	0xBF, 0x15, 0x3C, 0x49, 0xE2, 0x7F, 0x1B, 0xEA, 0x5A, 0x85, 0xFE, 0x9B, 0xF6, 0xC3, 0x63, 0x79,
+	0x79, 0x70, 0xCF, 0x24, 0x1B, 0x74, 0xE5, 0x71, 0xB4, 0x93, 0xD9, 0xB9, 0xAF, 0x81, 0xF2, 0x07,
+	0x24, 0xF7, 0xAF, 0xB7, 0x3F, 0xE0, 0x9C, 0x7C, 0xFE, 0xC6, 0x9F, 0x18, 0x87, 0xFB, 0x37, 0xBF,
+	0xFA, 0x6B, 0x15, 0xFD, 0x28, 0x7C, 0x45, 0x68, 0xA5, 0x4F, 0x63, 0xE7, 0x64, 0xFD, 0xA8, 0x3F,
+	0x68, 0xC0, 0xAB, 0x9F, 0x8D, 0x7E, 0x22, 0xFF, 0x00, 0xC1, 0x83, 0x52, 0x8F, 0xDA, 0x87, 0xF6,
+	0x8C, 0x27, 0x8F, 0x8D, 0x7E, 0x22, 0xF5, 0xFF, 0x00, 0x90, 0x93, 0x7A, 0xD7, 0x06, 0xBC, 0xC4,
+	0xAE, 0x28, 0x1D, 0x68, 0x38, 0xCF, 0xB1, 0xBC, 0x67, 0xF1, 0x7B, 0xE2, 0xA5, 0x8F, 0xFC, 0x13,
+	0x93, 0xC2, 0xBF, 0x10, 0xEC, 0xFE, 0x20, 0x6A, 0xF0, 0xEB, 0x97, 0x3E, 0x26, 0x78, 0xAE, 0x35,
+	0x55, 0xBC, 0x61, 0x3C, 0xA8, 0x26, 0xB8, 0x5C, 0x16, 0xCF, 0xA2, 0xA8, 0xFC, 0x2B, 0xE7, 0x5F,
+	0xF8, 0x6A, 0x2F, 0xDA, 0x31, 0x8F, 0xCD, 0xF1, 0xAF, 0xC4, 0x7F, 0xF0, 0x2D, 0x49, 0xCD, 0x7B,
+	0x47, 0x8F, 0x78, 0xFF, 0x00, 0x82, 0x58, 0xF8, 0x37, 0x3F, 0xF4, 0x35, 0xBF, 0xD3, 0xFD, 0x7D,
+	0xCD, 0x7C, 0xB7, 0xC8, 0xE7, 0xE9, 0xFC, 0xA8, 0x03, 0xD3, 0x7C, 0x21, 0xFB, 0x4C, 0xFE, 0xD0,
+	0xD7, 0x9E, 0x2C, 0xD2, 0xED, 0x2E, 0x7E, 0x32, 0x78, 0x82, 0x48, 0x66, 0xD4, 0x21, 0x49, 0x21,
+	0x6D, 0x45, 0xB0, 0xC0, 0xB8, 0x18, 0x3F, 0x5A, 0xF7, 0x8F, 0xF8, 0x29, 0x07, 0xC6, 0x1F, 0x8A,
+	0xBF, 0x0E, 0xBE, 0x27, 0xF8, 0x73, 0x4E, 0xF0, 0x27, 0xC4, 0x3D, 0x63, 0x49, 0xB7, 0xB8, 0xF0,
+	0xAC, 0x73, 0x4D, 0x0D, 0x8D, 0xEB, 0x46, 0xAE, 0xFE, 0x63, 0x0D, 0xC7, 0x9E, 0x4D, 0x7C, 0x9D,
+	0xE0, 0x7E, 0x7C, 0x69, 0xA4, 0xE3, 0xFE, 0x82, 0x56, 0xFF, 0x00, 0xFA, 0x31, 0x6B, 0xE8, 0xEF,
+	0xF8, 0x2A, 0xA7, 0xFC, 0x95, 0xEF, 0x0A, 0x0C, 0x72, 0x7C, 0x23, 0x1F, 0x5F, 0xFA, 0xEA, 0xD4,
+	0x01, 0xE3, 0x27, 0xF6, 0xA1, 0xFD, 0xA2, 0xCF, 0x5F, 0x8D, 0x7E, 0x22, 0xFC, 0x75, 0x26, 0xAF,
+	0x6D, 0xFF, 0x00, 0x82, 0x7D, 0xFC, 0x70, 0xF8, 0xC3, 0xE3, 0xCF, 0xDA, 0x5B, 0x4E, 0xF0, 0xEF,
+	0x8D, 0x3E, 0x25, 0xEB, 0x3A, 0xA5, 0x8B, 0x69, 0xD7, 0x8E, 0xD6, 0xB7, 0xB7, 0x8C, 0xF1, 0x92,
+	0x21, 0x27, 0x38, 0xFA, 0x8C, 0xFE, 0x15, 0xF2, 0xB0, 0xCE, 0x07, 0x1F, 0xC3, 0x5E, 0xFF, 0x00,
+	0xFF, 0x00, 0x04, 0xCE, 0x3F, 0xF1, 0x95, 0xBA, 0x59, 0x1C, 0xFF, 0x00, 0xC4, 0xB2, 0xFB, 0xFF,
+	0x00, 0x44, 0x1A, 0x00, 0xFD, 0x35, 0xA2, 0x8C, 0xF7, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x3E,
+	0x6C, 0xFD, 0xB0, 0x3C, 0x5F, 0xFB, 0x18, 0x78, 0x73, 0xE2, 0x1D, 0x8D, 0xAF, 0xED, 0x25, 0xE0,
+	0x6B, 0x8D, 0x53, 0x55, 0x93, 0x4B, 0x56, 0xB2, 0x9A, 0xDE, 0xDE, 0x56, 0x09, 0x6F, 0xE6, 0xB7,
+	0xCA, 0x76, 0x48, 0x83, 0x3B, 0xF2, 0x79, 0x06, 0xBC, 0x99, 0x7E, 0x29, 0x7F, 0xC1, 0x28, 0x36,
+	0xFF, 0x00, 0xC9, 0x1B, 0xBE, 0xFF, 0x00, 0xC0, 0x29, 0xFF, 0x00, 0xF8, 0xFD, 0x60, 0xFF, 0x00,
+	0xC1, 0x5B, 0x08, 0x1F, 0x1D, 0xBC, 0x3E, 0x7A, 0x7F, 0xC5, 0x34, 0xBD, 0xF1, 0xFF, 0x00, 0x2F,
+	0x0F, 0x5F, 0x2B, 0x0C, 0xE3, 0x85, 0xA0, 0x0F, 0xD0, 0x9F, 0xD9, 0x7B, 0xC7, 0x3F, 0xB0, 0x6E,
+	0xBB, 0xF1, 0x76, 0xD6, 0xC7, 0xE0, 0x2F, 0xC3, 0xBB, 0xAD, 0x3B, 0xC4, 0x8D, 0x6B, 0x39, 0xB5,
+	0xBA, 0xB8, 0xB7, 0x99, 0x42, 0xC6, 0x13, 0xE7, 0x19, 0x69, 0x98, 0x0C, 0xA6, 0x47, 0x4A, 0xE7,
+	0x3E, 0x2B, 0x7C, 0x44, 0xFF, 0x00, 0x82, 0x6D, 0xE9, 0xBF, 0x13, 0x7C, 0x41, 0x61, 0xF1, 0x27,
+	0xE1, 0x5D, 0xE5, 0xDE, 0xBD, 0x0E, 0xAB, 0x3A, 0xEB, 0x17, 0x11, 0xDA, 0xCE, 0xCB, 0x25, 0xC6,
+	0xFF, 0x00, 0x9D, 0x81, 0x13, 0x00, 0x72, 0x7D, 0x14, 0x57, 0x8C, 0x7F, 0xC1, 0x33, 0xB1, 0xFF,
+	0x00, 0x0D, 0x5B, 0xA5, 0xF4, 0xE3, 0x4C, 0xBE, 0xFF, 0x00, 0xD1, 0x06, 0xBC, 0xF7, 0xF6, 0xA9,
+	0xC7, 0xFC, 0x34, 0xB7, 0x8E, 0xB9, 0xFF, 0x00, 0x99, 0xA2, 0xEF, 0xBF, 0xFD, 0x34, 0xA5, 0xAD,
+	0xF5, 0x61, 0xFF, 0x00, 0x00, 0xFA, 0x28, 0xFC, 0x53, 0xFF, 0x00, 0x82, 0x51, 0x8E, 0x53, 0xE0,
+	0xF6, 0xA0, 0x1B, 0xB1, 0xFB, 0x1C, 0xFC, 0x7F, 0xE4, 0x7A, 0xF6, 0x2F, 0xD9, 0xE7, 0xC5, 0x7F,
+	0xB2, 0x16, 0xB3, 0xF0, 0x9B, 0xC6, 0xD7, 0xBF, 0x05, 0x3C, 0x15, 0x35, 0x87, 0x87, 0xED, 0xEC,
+	0xDB, 0xFE, 0x12, 0x8B, 0x69, 0xA2, 0x91, 0x5A, 0xE2, 0x3F, 0x22, 0x43, 0x81, 0xBA, 0x46, 0x27,
+	0xF7, 0x7B, 0xC7, 0x04, 0x75, 0xEB, 0x5F, 0x9A, 0xC7, 0x38, 0xFB, 0xB5, 0xF5, 0xFF, 0x00, 0xFC,
+	0x13, 0xFF, 0x00, 0x69, 0xFD, 0x97, 0x7E, 0x31, 0x11, 0xFF, 0x00, 0x40, 0xD7, 0xED, 0xFF, 0x00,
+	0x4E, 0x73, 0xD1, 0x2D, 0x80, 0xB0, 0xBF, 0x14, 0xFF, 0x00, 0xE0, 0x94, 0x67, 0x05, 0xBE, 0x0E,
+	0x5F, 0xFD, 0x7E, 0xC7, 0x3F, 0xA0, 0xC0, 0xFF, 0x00, 0x5F, 0xE9, 0x43, 0x7C, 0x52, 0xFF, 0x00,
+	0x82, 0x52, 0x11, 0xB5, 0x3E, 0x0F, 0xEA, 0x0B, 0x93, 0xFF, 0x00, 0x3E, 0x77, 0x03, 0xFF, 0x00,
+	0x6E, 0x2B, 0xE3, 0x68, 0xBE, 0xE2, 0x90, 0x01, 0xE3, 0xD7, 0x3D, 0x85, 0x3B, 0x38, 0x20, 0xB0,
+	0x03, 0x9A, 0x60, 0x7E, 0x8B, 0xFC, 0x62, 0xF1, 0x97, 0xEC, 0x7B, 0xA7, 0xFE, 0xC9, 0x3E, 0x1A,
+	0xD7, 0xFC, 0x61, 0xF0, 0xFA, 0xEE, 0xF3, 0xE1, 0xF5, 0xC5, 0xF2, 0x2E, 0x89, 0xA5, 0x5A, 0xC6,
+	0xE2, 0x48, 0x64, 0x22, 0x6D, 0xA4, 0xAF, 0x9A, 0xA4, 0x0C, 0x89, 0x3F, 0x88, 0xFD, 0xE1, 0xC7,
+	0x71, 0xE0, 0x03, 0xE2, 0xEF, 0xFC, 0x12, 0xB3, 0xAF, 0xFC, 0x28, 0x3D, 0x73, 0x9E, 0x7F, 0xD5,
+	0x3F, 0x3F, 0xF9, 0x33, 0x5A, 0x9F, 0xB4, 0x9E, 0x07, 0xFC, 0x12, 0xF3, 0xE1, 0xCF, 0x1F, 0xF3,
+	0x16, 0x83, 0xFF, 0x00, 0x42, 0xBA, 0xAF, 0x8B, 0x83, 0xF6, 0x2D, 0xFC, 0x22, 0xBE, 0x13, 0x88,
+	0x73, 0x39, 0x60, 0xF1, 0xDC, 0x9E, 0xCE, 0x32, 0xD1, 0x6A, 0xD5, 0xCF, 0xE8, 0x0F, 0x0C, 0xF8,
+	0x56, 0x96, 0x75, 0xC3, 0xEE, 0xBC, 0xB1, 0x35, 0x69, 0xBE, 0x76, 0xAD, 0x09, 0xB8, 0xC7, 0x4B,
+	0x74, 0x5D, 0x7B, 0x9F, 0x76, 0x7C, 0x09, 0xF8, 0x9D, 0xFF, 0x00, 0x04, 0xE3, 0xD5, 0x7E, 0x30,
+	0x78, 0x77, 0x4D, 0xF8, 0x67, 0xF0, 0x67, 0x57, 0xB1, 0xF1, 0x0C, 0xDA, 0x8A, 0xAE, 0x95, 0x79,
+	0x71, 0x13, 0x6C, 0x8A, 0x5D, 0xAD, 0x86, 0x39, 0x9D, 0x86, 0x31, 0x9F, 0xE1, 0x3F, 0x4A, 0xF6,
+	0x0F, 0x8D, 0x3E, 0x2D, 0xFD, 0x97, 0xF4, 0x9F, 0x88, 0xF7, 0xD6, 0x7F, 0x10, 0xFC, 0x07, 0x7D,
+	0x7D, 0xAC, 0x2C, 0x70, 0xFD, 0xAA, 0xE6, 0xDD, 0x0E, 0xD6, 0xCC, 0x6A, 0x54, 0x0F, 0xDE, 0xAF,
+	0x45, 0xDB, 0xD8, 0x0A, 0xFC, 0xFF, 0x00, 0xFD, 0x8D, 0x48, 0x6F, 0xDA, 0x93, 0xC0, 0xEA, 0xC7,
+	0xFE, 0x63, 0x83, 0xFF, 0x00, 0x40, 0x7A, 0xFA, 0x93, 0xF6, 0xB5, 0xC2, 0xFC, 0x7B, 0xD6, 0x94,
+	0x1F, 0xE0, 0xB6, 0xFF, 0x00, 0xD2, 0x74, 0xAF, 0xC9, 0xBC, 0x55, 0xE2, 0xAA, 0xB9, 0x4F, 0x05,
+	0xAC, 0x54, 0x70, 0xF4, 0xA6, 0xFD, 0xA2, 0x5C, 0xB2, 0x8A, 0x71, 0xDA, 0xF7, 0xB3, 0xEA, 0x63,
+	0xC4, 0x1C, 0x2F, 0x4B, 0x07, 0xC5, 0x94, 0xF0, 0xAB, 0x11, 0x56, 0x57, 0xA6, 0xE5, 0xCC, 0xE4,
+	0xDC, 0xB7, 0x5A, 0x26, 0xFA, 0x79, 0x1D, 0x81, 0xF1, 0xF7, 0xEC, 0x54, 0x39, 0x1F, 0x0B, 0xB5,
+	0x45, 0xEB, 0xFF, 0x00, 0x2C, 0xDB, 0xD3, 0xFE, 0xBB, 0x57, 0xA4, 0xFC, 0x26, 0xF1, 0x17, 0xC0,
+	0x0D, 0x47, 0xE1, 0x87, 0x8A, 0x2F, 0xFC, 0x21, 0xE1, 0x1B, 0xAB, 0x3D, 0x0E, 0x1B, 0x79, 0x0E,
+	0xB9, 0x6F, 0x32, 0xB6, 0xE9, 0x93, 0xCA, 0x25, 0xB0, 0x37, 0xB1, 0xFB, 0xB9, 0xEF, 0x5F, 0x1F,
+	0xE4, 0x1E, 0xDF, 0xAD, 0x7B, 0xCF, 0xEC, 0xDE, 0x49, 0xFD, 0x9C, 0x7E, 0x25, 0xEE, 0xED, 0x61,
+	0x3E, 0x3F, 0xF0, 0x14, 0xD7, 0xE6, 0xBE, 0x0B, 0xF1, 0xFE, 0x23, 0x3F, 0xE3, 0x8A, 0x58, 0x5A,
+	0x98, 0x3A, 0x34, 0xD3, 0x8C, 0x9F, 0x34, 0x29, 0xA8, 0xCB, 0x45, 0xD1, 0xAE, 0x9D, 0xD1, 0xF3,
+	0xFC, 0x59, 0x90, 0xD3, 0xC0, 0x64, 0xF2, 0xAB, 0x1A, 0xD3, 0x95, 0x9A, 0x56, 0x94, 0x9B, 0x5A,
+	0xBE, 0xC7, 0x0F, 0x17, 0xC5, 0x3F, 0xF8, 0x25, 0x09, 0x45, 0x6F, 0xF8, 0x53, 0x77, 0xF8, 0x2B,
+	0xF2, 0x8F, 0xB1, 0x4F, 0xC7, 0xFE, 0x47, 0xA9, 0x13, 0xE2, 0x97, 0xFC, 0x12, 0x9D, 0xA4, 0x8C,
+	0xC1, 0xF0, 0x7E, 0xFD, 0x5B, 0x70, 0xDA, 0xDF, 0x63, 0xB8, 0xFE, 0x97, 0x15, 0xF1, 0x9D, 0xBE,
+	0x04, 0x6B, 0x80, 0x0F, 0xC8, 0x3D, 0xFB, 0x54, 0xD6, 0xD9, 0xFB, 0x4C, 0x79, 0x5F, 0xF9, 0x68,
+	0xBF, 0xCE, 0xBF, 0xB7, 0x8F, 0xC9, 0x4F, 0xD5, 0x3F, 0x8B, 0xFF, 0x00, 0xB4, 0xAF, 0xC1, 0xEF,
+	0xD9, 0xE3, 0x49, 0xF0, 0xEE, 0xA5, 0xE3, 0x47, 0xD4, 0xE1, 0xB7, 0xD5, 0xAC, 0x59, 0x74, 0x75,
+	0xB1, 0x80, 0xC9, 0xFB, 0x94, 0x58, 0xC9, 0x0C, 0x0B, 0x00, 0x0E, 0x1A, 0x3E, 0xB9, 0x3E, 0x87,
+	0xAD, 0x59, 0xF0, 0x5F, 0xED, 0x59, 0xF0, 0x9B, 0xE2, 0x0E, 0x89, 0x1F, 0x89, 0x3C, 0x1D, 0xA8,
+	0xDC, 0x5E, 0x5A, 0xCA, 0x3E, 0x6D, 0xB6, 0xE7, 0x7C, 0x6D, 0xFD, 0xC6, 0x5C, 0xE4, 0x35, 0x7C,
+	0xCB, 0xFF, 0x00, 0x05, 0x4A, 0x5C, 0xF8, 0x0B, 0xE1, 0x48, 0x1F, 0xF4, 0x0D, 0xBA, 0xF9, 0x7F,
+	0xED, 0x95, 0xA5, 0x7C, 0xBB, 0xF0, 0xCB, 0xE2, 0x97, 0x8B, 0xBE, 0x13, 0xF8, 0x81, 0x75, 0xFF,
+	0x00, 0x0B, 0xDF, 0x6D, 0x56, 0x3F, 0xE9, 0x96, 0x72, 0x64, 0xC5, 0x70, 0xBC, 0x70, 0xCB, 0xEB,
+	0xC0, 0xC1, 0x1C, 0x8A, 0xF9, 0x3E, 0x32, 0xA5, 0xC4, 0xF3, 0xC8, 0xEA, 0x4B, 0x20, 0x9C, 0x56,
+	0x26, 0x3A, 0xC5, 0x4D, 0x5D, 0x4A, 0xDD, 0x1D, 0x9A, 0xB5, 0xFA, 0x33, 0xAB, 0x0A, 0xF0, 0xDE,
+	0xD9, 0x7B, 0x6B, 0xB8, 0xF9, 0x69, 0x63, 0xF5, 0x50, 0x7C, 0x75, 0xF0, 0xAB, 0x7F, 0xCB, 0xBD,
+	0xCF, 0xFD, 0xF9, 0xFF, 0x00, 0xEB, 0xD2, 0xFF, 0x00, 0xC2, 0xF2, 0xF0, 0xA0, 0xEB, 0x05, 0xD7,
+	0xFE, 0x03, 0xD7, 0xCD, 0x5F, 0x06, 0xFE, 0x39, 0x78, 0x47, 0xE3, 0x26, 0x95, 0xE7, 0xE9, 0x2E,
+	0x6D, 0xF5, 0x08, 0x57, 0x37, 0x9A, 0x5D, 0xC1, 0xCC, 0x91, 0x1F, 0x50, 0x7F, 0x8D, 0x7D, 0xC7,
+	0x4C, 0xE3, 0xBD, 0x76, 0xC3, 0xEF, 0x2E, 0xD5, 0x5E, 0x47, 0x18, 0x1D, 0x7D, 0xEB, 0xF8, 0x1B,
+	0x88, 0x3E, 0x92, 0x1E, 0x32, 0x70, 0xBE, 0x65, 0x3C, 0x0E, 0x65, 0x46, 0x14, 0xEA, 0x45, 0xD9,
+	0xA7, 0x07, 0xF7, 0xAD, 0x6C, 0xD3, 0xE8, 0xD1, 0xF6, 0xB4, 0x38, 0x7F, 0x29, 0xC4, 0xD3, 0x53,
+	0xA7, 0x26, 0xD3, 0xF3, 0xFF, 0x00, 0x80, 0x7A, 0xF1, 0xF8, 0xE9, 0xE1, 0x7C, 0x7F, 0xAA, 0xB9,
+	0x1F, 0xF6, 0xEF, 0x5F, 0x97, 0x3F, 0xF0, 0x70, 0xA7, 0xFC, 0x13, 0xD3, 0xF6, 0x81, 0xFF, 0x00,
+	0x82, 0x9C, 0x7C, 0x40, 0xF8, 0x5B, 0xE2, 0x6F, 0xD9, 0xBA, 0x6F, 0x0F, 0xC7, 0x6F, 0xE0, 0xFD,
+	0x1F, 0x56, 0xB5, 0xD5, 0x97, 0xC4, 0x7A, 0xA4, 0x96, 0xAC, 0x64, 0xB8, 0x96, 0xD1, 0xE3, 0x28,
+	0x16, 0x19, 0x37, 0x8C, 0x42, 0xF9, 0x24, 0x8C, 0x63, 0xDE, 0xBE, 0xE6, 0xDE, 0x18, 0x7C, 0xAA,
+	0xB4, 0x70, 0x4F, 0x22, 0xBC, 0x48, 0x7D, 0x2D, 0x3C, 0x4A, 0x8B, 0xF7, 0xA3, 0x49, 0xFA, 0xC5,
+	0xFE, 0x8D, 0x1D, 0x31, 0xE1, 0x8C, 0x04, 0x65, 0x7D, 0x7E, 0xFF, 0x00, 0xF8, 0x07, 0xE0, 0x5F,
+	0xFC, 0x43, 0x5F, 0xFF, 0x00, 0x05, 0x18, 0xFF, 0x00, 0x9F, 0xEF, 0x87, 0x7F, 0xF8, 0x54, 0xCF,
+	0xFF, 0x00, 0xC8, 0xB4, 0x7F, 0xC4, 0x35, 0xFF, 0x00, 0xF0, 0x51, 0x9F, 0xF9, 0xFF, 0x00, 0xF8,
+	0x77, 0xFF, 0x00, 0x85, 0x44, 0xFF, 0x00, 0xFC, 0x8B, 0x5F, 0xBE, 0xBB, 0x9B, 0x39, 0xCD, 0x1B,
+	0x9B, 0xFB, 0x9F, 0xF8, 0xF5, 0x69, 0xFF, 0x00, 0x13, 0x71, 0xE2, 0x27, 0xFC, 0xFA, 0xA3, 0xFF,
+	0x00, 0x80, 0xCB, 0xFF, 0x00, 0x93, 0x37, 0xFF, 0x00, 0x57, 0xF0, 0x7E, 0x7F, 0x7A, 0xFF, 0x00,
+	0x23, 0xF0, 0x2B, 0xFE, 0x21, 0xAF, 0xFF, 0x00, 0x82, 0x8C, 0xFF, 0x00, 0xCF, 0xFF, 0x00, 0xC3,
+	0xBF, 0xFC, 0x2A, 0x27, 0xFF, 0x00, 0xE4, 0x5A, 0x3F, 0xE2, 0x1B, 0x0F, 0xF8, 0x28, 0xD7, 0xFC,
+	0xFF, 0x00, 0xFC, 0x3A, 0xFF, 0x00, 0xC2, 0xA2, 0x7F, 0xFE, 0x45, 0xAF, 0xDF, 0x5D, 0xCD, 0xFD,
+	0xCF, 0xFC, 0x7A, 0x82, 0xC7, 0xB7, 0xF3, 0xA3, 0xFE, 0x26, 0xE3, 0xC4, 0x4F, 0xF9, 0xF5, 0x47,
+	0xFF, 0x00, 0x01, 0x97, 0xFF, 0x00, 0x24, 0x2F, 0xF5, 0x7F, 0x07, 0xE7, 0xF7, 0xAF, 0xF2, 0x3F,
+	0x9D, 0xFF, 0x00, 0x8D, 0xBF, 0xF0, 0x41, 0x4F, 0xDB, 0xAB, 0xE0, 0x07, 0xC2, 0xFD, 0x5B, 0xE2,
+	0xE7, 0x8E, 0xEF, 0xBC, 0x0C, 0x74, 0xAD, 0x16, 0xDD, 0x66, 0xBB, 0x5B, 0x1F, 0x11, 0x4D, 0x24,
+	0xC5, 0x4B, 0xAA, 0x7C, 0x8A, 0x6D, 0x80, 0x63, 0x96, 0x1D, 0x48, 0x15, 0xF3, 0x30, 0xFD, 0x9C,
+	0xBE, 0x21, 0x85, 0xC0, 0x6D, 0x3B, 0xEF, 0x7D, 0xDF, 0xB4, 0xB7, 0x1F, 0xF8, 0xEF, 0xF4, 0xAF,
+	0xE8, 0xEB, 0xFE, 0x0A, 0x82, 0xCC, 0x3F, 0x61, 0xAF, 0x1F, 0x64, 0x65, 0x7F, 0xB3, 0x23, 0xFF,
+	0x00, 0xD1, 0xF1, 0xD7, 0xE1, 0xDB, 0xB7, 0xCD, 0x90, 0x6B, 0xFA, 0x4B, 0xC2, 0x1F, 0x17, 0x38,
+	0x93, 0x8E, 0x32, 0x1A, 0x98, 0xDC, 0x74, 0x60, 0xA4, 0xA4, 0xE2, 0xB9, 0x53, 0x4A, 0xD6, 0xF3,
+	0x6F, 0x53, 0xFA, 0x13, 0xC1, 0xDF, 0x05, 0x78, 0x4B, 0x8D, 0x72, 0x9C, 0x46, 0x23, 0x30, 0x73,
+	0xE6, 0x84, 0xF9, 0x55, 0x9A, 0x5A, 0x59, 0x3D, 0x74, 0x3C, 0x27, 0xFE, 0x19, 0xCF, 0xE2, 0x28,
+	0x1F, 0x23, 0x69, 0xFF, 0x00, 0xF8, 0x14, 0xC3, 0x91, 0xC8, 0xCE, 0x17, 0xD7, 0x15, 0xEF, 0xDF,
+	0xB3, 0x3F, 0xFC, 0x11, 0x3F, 0xF6, 0xCD, 0xFD, 0xAC, 0x3C, 0x01, 0x37, 0xC4, 0x9F, 0x85, 0x57,
+	0x3E, 0x0C, 0x5D, 0x36, 0x1D, 0x46, 0x4B, 0x36, 0x4D, 0x53, 0x5D, 0x92, 0x19, 0x44, 0x88, 0xA8,
+	0xCC, 0x42, 0xAD, 0xBB, 0x0D, 0xA7, 0x78, 0xEF, 0xDA, 0xAB, 0xB3, 0x12, 0x71, 0xB7, 0xFC, 0xE2,
+	0xBF, 0x5D, 0xBF, 0xE0, 0x87, 0xA5, 0x87, 0xEC, 0x91, 0x7C, 0xBB, 0x7F, 0xE6, 0x6D, 0xBB, 0xFF,
+	0x00, 0xD1, 0x70, 0xD7, 0x77, 0x8A, 0x9E, 0x29, 0x71, 0x17, 0x05, 0x70, 0xAC, 0xB3, 0x0C, 0x12,
+	0x83, 0x9A, 0x92, 0x56, 0x92, 0x6D, 0x59, 0xBD, 0x76, 0x69, 0xDF, 0xE6, 0x7A, 0x3E, 0x2C, 0x78,
+	0x1B, 0xC1, 0xBC, 0x1B, 0xC3, 0x6B, 0x19, 0x80, 0x73, 0x73, 0x73, 0x8C, 0x7D, 0xE6, 0x9A, 0xB3,
+	0xBD, 0xF4, 0xB7, 0x91, 0xF9, 0xAF, 0xFF, 0x00, 0x10, 0xD8, 0x7F, 0xC1, 0x46, 0x4F, 0x22, 0xFF,
+	0x00, 0xE1, 0xDF, 0xFE, 0x15, 0x13, 0xFF, 0x00, 0xF2, 0x2D, 0x1F, 0xF1, 0x0D, 0x87, 0xFC, 0x14,
+	0x6B, 0xFE, 0x7F, 0xFE, 0x1D, 0x7F, 0xE1, 0x51, 0x3F, 0xFF, 0x00, 0x22, 0xD7, 0xEF, 0xAE, 0xF6,
+	0xA3, 0x73, 0x7F, 0x73, 0xFF, 0x00, 0x1E, 0xAF, 0xE5, 0xFF, 0x00, 0xF8, 0x9B, 0x8F, 0x10, 0xBF,
+	0xE7, 0xCD, 0x1F, 0xFC, 0x06, 0x5F, 0xFC, 0x99, 0xFC, 0xD5, 0xFE, 0xAE, 0xE0, 0xFC, 0xFE, 0xF5,
+	0xFE, 0x47, 0xE0, 0x57, 0xFC, 0x43, 0x5F, 0xFF, 0x00, 0x05, 0x18, 0xFF, 0x00, 0xA0, 0x87, 0xC3,
+	0xBF, 0xFC, 0x2A, 0x27, 0xFF, 0x00, 0xE4, 0x5A, 0x3F, 0xE2, 0x1B, 0x0F, 0xF8, 0x28, 0xD0, 0xFF,
+	0x00, 0x97, 0xEF, 0x87, 0x7F, 0xF8, 0x54, 0x4F, 0xFF, 0x00, 0xC8, 0xB5, 0xFB, 0xEB, 0xB9, 0xBF,
+	0xB9, 0xFF, 0x00, 0x8F, 0x52, 0x86, 0x27, 0xA2, 0xD1, 0xFF, 0x00, 0x13, 0x71, 0xE2, 0x22, 0xFF,
+	0x00, 0x97, 0x54, 0x7F, 0xF0, 0x19, 0x7F, 0xF2, 0x63, 0xFF, 0x00, 0x57, 0xF0, 0x7D, 0xDF, 0xDE,
+	0xBF, 0xC8, 0xFC, 0xAF, 0xFF, 0x00, 0x82, 0x33, 0xFF, 0x00, 0xC1, 0x1D, 0xFF, 0x00, 0x6B, 0xEF,
+	0xD8, 0x43, 0xFE, 0x0A, 0x01, 0xE1, 0x5F, 0xDA, 0x57, 0xE3, 0x75, 0xDF, 0x83, 0xDB, 0xC3, 0xBA,
+	0x36, 0x9F, 0xAA, 0x41, 0x78, 0xBA, 0x2E, 0xB5, 0x2D, 0xC5, 0xC6, 0xEB, 0x8B, 0x19, 0xA0, 0x8C,
+	0xAA, 0x34, 0x08, 0x08, 0xDF, 0x22, 0xE7, 0x2D, 0xC0, 0xCF, 0x19, 0xC5, 0x7E, 0xD6, 0x27, 0xC7,
+	0x3F, 0x09, 0xF5, 0x16, 0xF7, 0x3F, 0x4F, 0x24, 0x71, 0x5E, 0x42, 0x4E, 0x4E, 0x68, 0x04, 0x83,
+	0xD2, 0xB3, 0x9F, 0xD2, 0xDB, 0xC4, 0xC9, 0x4B, 0xDD, 0x54, 0x97, 0xFD, 0xBA, 0xFF, 0x00, 0x56,
+	0xCC, 0x27, 0xC3, 0x38, 0x19, 0xCA, 0xFA, 0xFD, 0xFF, 0x00, 0xF0, 0x0F, 0x60, 0xFF, 0x00, 0x85,
+	0xE7, 0xE1, 0x4F, 0xF9, 0xE1, 0x75, 0xFF, 0x00, 0x80, 0xF4, 0x37, 0xC7, 0x5F, 0x0A, 0x0F, 0xBB,
+	0x6F, 0x73, 0xFF, 0x00, 0x01, 0x87, 0xFF, 0x00, 0xAF, 0x5E, 0x43, 0xBB, 0x77, 0x03, 0x6D, 0x73,
+	0xBF, 0x12, 0x7E, 0x28, 0x78, 0x43, 0xE1, 0x5E, 0x80, 0xDA, 0xEF, 0x8B, 0xB5, 0x45, 0x88, 0x6D,
+	0x3F, 0x67, 0xB5, 0x55, 0xDD, 0x35, 0xC1, 0xF4, 0x54, 0x3D, 0x47, 0xA9, 0x38, 0x03, 0xD7, 0x38,
+	0x07, 0xD2, 0xC9, 0xFE, 0x93, 0x7E, 0x30, 0x67, 0xB8, 0xE8, 0x61, 0x30, 0x14, 0x61, 0x52, 0x72,
+	0x76, 0x4A, 0x30, 0x6D, 0xB7, 0xF2, 0x30, 0xAD, 0xC3, 0xB9, 0x5E, 0x1E, 0x9B, 0x9D, 0x49, 0x34,
+	0x97, 0x9F, 0xFC, 0x03, 0xDD, 0x35, 0xAF, 0xDA, 0x47, 0xE1, 0xCF, 0x86, 0xF4, 0x99, 0xB5, 0xDF,
+	0x12, 0xDF, 0x49, 0x61, 0x63, 0x6E, 0xBB, 0xAE, 0x2E, 0xAE, 0x57, 0x6A, 0xA8, 0xFC, 0xF2, 0x4F,
+	0xB0, 0xC9, 0x3D, 0x00, 0x27, 0x8A, 0xCD, 0xF8, 0x15, 0xFB, 0x59, 0xFC, 0x23, 0xFD, 0xA3, 0x75,
+	0xAD, 0x43, 0x42, 0xF8, 0x6F, 0x73, 0xA9, 0x35, 0xD6, 0x9B, 0x6A, 0x26, 0xB8, 0xFB, 0x75, 0x91,
+	0x84, 0x04, 0x67, 0x2A, 0x31, 0xF3, 0x02, 0x4E, 0x47, 0x20, 0x80, 0x40, 0x23, 0x38, 0xAF, 0xCD,
+	0xCF, 0x8D, 0x3F, 0x1D, 0x7C, 0x57, 0xF1, 0x97, 0x57, 0xF3, 0x75, 0x15, 0x36, 0xBA, 0x5C, 0x2C,
+	0x7E, 0xC5, 0xA5, 0xAB, 0x96, 0x54, 0xE0, 0xE1, 0x9F, 0x3C, 0x48, 0xDC, 0xF7, 0xFB, 0xBD, 0xB3,
+	0x5F, 0x41, 0x7F, 0xC1, 0x21, 0xC6, 0xEF, 0x8A, 0x3E, 0x31, 0xC1, 0xFF, 0x00, 0x98, 0x1D, 0xB8,
+	0x62, 0x79, 0x24, 0xF9, 0xC7, 0x9A, 0xFE, 0xF4, 0xF0, 0xFD, 0x71, 0x94, 0xF2, 0x38, 0x56, 0xE2,
+	0x59, 0x41, 0xE2, 0x27, 0xAF, 0x2C, 0x15, 0x94, 0x55, 0xB6, 0x7A, 0xBB, 0xBE, 0xE7, 0xC5, 0x63,
+	0xBE, 0xA9, 0x1A, 0xCD, 0x61, 0xD3, 0xB2, 0xEE, 0xF7, 0x36, 0x75, 0xBF, 0x89, 0xFF, 0x00, 0xF0,
+	0x4B, 0x48, 0xB5, 0xAB, 0xD8, 0x75, 0x6F, 0x84, 0x17, 0xCF, 0x72, 0xB7, 0x52, 0x0B, 0xA6, 0x5B,
+	0x39, 0xF0, 0xD2, 0x87, 0x21, 0x8F, 0xFA, 0xF1, 0xDC, 0x13, 0xF8, 0xD5, 0x56, 0xF8, 0xA5, 0xFF,
+	0x00, 0x04, 0xA3, 0x23, 0xE5, 0xF8, 0x3D, 0xA8, 0x2F, 0xFD, 0xB9, 0xDC, 0x7A, 0x74, 0xE2, 0xE3,
+	0xB8, 0xE2, 0xBE, 0x4B, 0xF1, 0xA1, 0xFF, 0x00, 0x8A, 0xD3, 0x58, 0xC6, 0xDF, 0xF9, 0x0A, 0xDC,
+	0x71, 0xFF, 0x00, 0x6D, 0x5A, 0xB2, 0xD8, 0xF1, 0xF3, 0x00, 0x2B, 0xEE, 0x8E, 0x33, 0xF5, 0x03,
+	0x5E, 0xF1, 0x1F, 0xEC, 0xE9, 0x17, 0xEC, 0xDB, 0xE1, 0xBD, 0x68, 0xF8, 0x4A, 0xEA, 0x6F, 0x05,
+	0xCD, 0x0C, 0x3F, 0xD8, 0xBA, 0x6C, 0x71, 0x36, 0xF8, 0xA3, 0x20, 0xEC, 0x18, 0x32, 0x02, 0x00,
+	0x00, 0xF5, 0x27, 0xAD, 0x79, 0xE7, 0xFC, 0x27, 0xDF, 0xB1, 0x49, 0x19, 0xFF, 0x00, 0x85, 0x5B,
+	0xA9, 0xFF, 0x00, 0xDF, 0xB6, 0x1F, 0xFB, 0x5A, 0xAA, 0x6B, 0x6B, 0x8F, 0xF8, 0x27, 0xE7, 0xC3,
+	0xB6, 0x1F, 0xF3, 0xE7, 0x69, 0xFF, 0x00, 0xB3, 0xD7, 0x89, 0x06, 0xFA, 0xFD, 0xD1, 0xFC, 0x5E,
+	0xD5, 0xFC, 0x5D, 0xE3, 0x97, 0x1D, 0xE2, 0x32, 0x0E, 0x32, 0x78, 0x58, 0x61, 0x28, 0xD4, 0x5C,
+	0x91, 0x77, 0x9D, 0x35, 0x29, 0x6B, 0xE6, 0xFA, 0x1F, 0xAB, 0x70, 0x7E, 0x47, 0x0C, 0xC3, 0x29,
+	0xF6, 0xAE, 0xB4, 0xE3, 0xEF, 0x3D, 0x23, 0x26, 0x97, 0xDC, 0x7D, 0x2B, 0xF0, 0xD7, 0xC6, 0xBF,
+	0xB2, 0x8D, 0xE7, 0x8F, 0x74, 0x9B, 0x4F, 0x07, 0x7C, 0x3B, 0xD4, 0x6D, 0xB5, 0x39, 0x2F, 0x51,
+	0x6C, 0xA6, 0x99, 0x5B, 0x6A, 0x49, 0x9E, 0x09, 0xCC, 0xA7, 0xA7, 0xD0, 0xD7, 0x21, 0xFB, 0x4E,
+	0xFC, 0x4B, 0xFF, 0x00, 0x82, 0x7B, 0x78, 0x7F, 0xE3, 0x5E, 0xAF, 0xA6, 0x7C, 0x72, 0xF8, 0x41,
+	0xAB, 0x6A, 0x9E, 0x26, 0x8D, 0x61, 0x1A, 0x85, 0xF5, 0xAC, 0x2E, 0xCB, 0x27, 0xEE, 0x94, 0xA6,
+	0x08, 0xB9, 0x41, 0xC2, 0xED, 0x1F, 0x74, 0x57, 0x11, 0xF0, 0x03, 0x9F, 0x8C, 0xFE, 0x1B, 0x20,
+	0x7F, 0xCC, 0x52, 0x3E, 0xFE, 0xF5, 0xE4, 0xBF, 0xF0, 0x51, 0xCC, 0x7F, 0xC3, 0x5F, 0xF8, 0xA7,
+	0x3F, 0xF4, 0xEB, 0xFF, 0x00, 0xA4, 0xD1, 0xD7, 0xEA, 0x5F, 0x47, 0xFE, 0x24, 0xAB, 0xC4, 0x9C,
+	0x3F, 0x88, 0xAD, 0x3A, 0x34, 0xE9, 0x38, 0xCD, 0x2B, 0x53, 0x8A, 0x8C, 0x5E, 0x97, 0xBB, 0x4B,
+	0x77, 0xE6, 0x78, 0x3C, 0x5B, 0x96, 0x47, 0x2F, 0xCC, 0xA3, 0x4E, 0x35, 0x25, 0x2B, 0xC6, 0xF7,
+	0x93, 0x6D, 0xEF, 0xB5, 0xCF, 0x53, 0x3F, 0x19, 0x7F, 0xE0, 0x93, 0x67, 0xE5, 0xFF, 0x00, 0x85,
+	0x03, 0xAF, 0x7F, 0xE0, 0x33, 0xFF, 0x00, 0xF2, 0x5D, 0x7B, 0xE7, 0xEC, 0xBB, 0xE3, 0x0F, 0xD9,
+	0x1F, 0xC4, 0x5F, 0x03, 0xBC, 0x6D, 0xAA, 0x7C, 0x11, 0xF0, 0x0D, 0xE6, 0x97, 0xE1, 0x7B, 0x56,
+	0xB8, 0x1E, 0x26, 0xB3, 0xBA, 0x8D, 0xC3, 0xDC, 0x01, 0x6A, 0x19, 0xF0, 0x0C, 0xAE, 0x4F, 0xEE,
+	0x7E, 0x5E, 0x18, 0x7D, 0x2B, 0xF2, 0xFB, 0x3D, 0xF3, 0x5F, 0x6E, 0x7F, 0xC1, 0x39, 0x41, 0xFF,
+	0x00, 0x86, 0x33, 0xF8, 0xC5, 0xFF, 0x00, 0x6F, 0xDF, 0xFA, 0x6B, 0x5A, 0xFD, 0xFC, 0xF9, 0x1A,
+	0xD1, 0xE5, 0x8E, 0xEC, 0x7C, 0x7F, 0x14, 0xFF, 0x00, 0xE0, 0x94, 0x3B, 0x7F, 0xE4, 0x8D, 0xDF,
+	0x7A, 0x7F, 0xC7, 0x8D, 0xC7, 0xFF, 0x00, 0x1F, 0xA5, 0x3F, 0x14, 0xBF, 0xE0, 0x94, 0x7D, 0x63,
+	0xF8, 0x39, 0x7F, 0xBB, 0xB7, 0xFA, 0x14, 0xFF, 0x00, 0xFC, 0x7E, 0xBE, 0x37, 0x8F, 0x01, 0x57,
+	0x6B, 0x06, 0xF9, 0x69, 0x7B, 0x8C, 0xAF, 0xF1, 0x50, 0x72, 0x9F, 0xA3, 0x3A, 0xEF, 0x8C, 0x3F,
+	0x63, 0x08, 0x7F, 0x65, 0x5D, 0x1B, 0xC4, 0x7A, 0xC7, 0x81, 0x6E, 0x64, 0xF8, 0x77, 0x26, 0xB8,
+	0xCB, 0xA4, 0x69, 0x7F, 0x67, 0x94, 0xC9, 0x1D, 0xC6, 0xE9, 0x41, 0x62, 0x3C, 0xDD, 0xDF, 0x7C,
+	0x4A, 0x79, 0x6F, 0xE2, 0xE9, 0x5E, 0x58, 0xBF, 0x14, 0xFF, 0x00, 0xE0, 0x94, 0x38, 0xF9, 0xBE,
+	0x0D, 0xDF, 0x2F, 0xFD, 0xB8, 0xCF, 0xCF, 0x03, 0xFE, 0x9B, 0xD7, 0x39, 0xE3, 0xFD, 0xA7, 0xFE,
+	0x09, 0x63, 0xE0, 0xD2, 0x3F, 0xE8, 0x6C, 0x93, 0x9F, 0xFB, 0x6F, 0x75, 0x5F, 0x2D, 0xA6, 0x40,
+	0xC8, 0x03, 0xB7, 0xF2, 0xA0, 0x0F, 0xB4, 0xB4, 0x4F, 0x89, 0xBF, 0xF0, 0x4B, 0x59, 0xF5, 0xCB,
+	0x38, 0x34, 0x7F, 0x84, 0x77, 0xCB, 0x74, 0xD7, 0x51, 0xAD, 0xB6, 0xEB, 0x3B, 0x8C, 0x09, 0x0B,
+	0x0D, 0xA7, 0xFE, 0x3E, 0x3D, 0x71, 0x5E, 0x8F, 0xFB, 0x55, 0xF8, 0xC7, 0xF6, 0x2D, 0xF0, 0xEF,
+	0x8C, 0x34, 0x7B, 0x6F, 0xDA, 0x37, 0xC0, 0xD7, 0x1A, 0xB6, 0xA7, 0x26, 0x87, 0x13, 0x58, 0xCD,
+	0x0D, 0xBC, 0xAD, 0xB6, 0xDB, 0x7B, 0x7C, 0xA7, 0x6C, 0xAB, 0xCE, 0xEC, 0x9E, 0x73, 0x5F, 0x9F,
+	0x9E, 0x06, 0x23, 0xFE, 0x13, 0x6D, 0x27, 0x70, 0x1F, 0xF2, 0x12, 0xB7, 0xFF, 0x00, 0xD1, 0x8B,
+	0x5F, 0x45, 0xFF, 0x00, 0xC1, 0x54, 0xC0, 0xFF, 0x00, 0x85, 0xBB, 0xE1, 0x5C, 0x8C, 0x7F, 0xC5,
+	0x23, 0x17, 0xFE, 0x8D, 0x7A, 0x00, 0xE9, 0xD7, 0xE2, 0x9F, 0xFC, 0x12, 0x83, 0x67, 0x1F, 0x07,
+	0x2F, 0x87, 0xCB, 0xFF, 0x00, 0x3E, 0x53, 0xFF, 0x00, 0xF1, 0xFA, 0xF4, 0x2F, 0xD9, 0x7B, 0xC7,
+	0x3F, 0xB0, 0x66, 0xBD, 0xF1, 0x7A, 0xD3, 0x4F, 0xF8, 0x0B, 0xF0, 0xEE, 0xEB, 0x4F, 0xF1, 0x23,
+	0x5B, 0x4E, 0x6D, 0x6E, 0xA6, 0xB7, 0x99, 0x42, 0x46, 0x13, 0xE7, 0x19, 0x69, 0x98, 0x7D, 0xCC,
+	0x8E, 0x95, 0xF9, 0xEE, 0x99, 0xE3, 0x81, 0xDB, 0x9A, 0xF7, 0xEF, 0xF8, 0x26, 0x76, 0x0F, 0xED,
+	0x59, 0xA5, 0x9F, 0xFA, 0x85, 0xDF, 0x7F, 0xE8, 0x83, 0x40, 0x1F, 0xA6, 0x83, 0xDE, 0x8A, 0x39,
+	0xCD, 0x14, 0x00, 0x51, 0x45, 0x14, 0x01, 0xF1, 0xA7, 0xFC, 0x14, 0x3B, 0xF6, 0x61, 0xF8, 0xD9,
+	0xF1, 0xC7, 0xE2, 0xD6, 0x93, 0xE2, 0x4F, 0x86, 0x5E, 0x10, 0xFE, 0xD0, 0xB5, 0xB4, 0xD0, 0xC5,
+	0xBD, 0xC4, 0x9F, 0x6A, 0x8E, 0x2D, 0xAF, 0xE7, 0x3B, 0x63, 0xE6, 0x60, 0x7A, 0x73, 0xD2, 0xBC,
+	0x00, 0xFF, 0x00, 0xC1, 0x3C, 0x7F, 0x6B, 0x7C, 0xF1, 0xF0, 0xAF, 0xFF, 0x00, 0x2A, 0x90, 0x7F,
+	0x8D, 0x7B, 0xDF, 0xFC, 0x14, 0x53, 0xF6, 0x97, 0xF8, 0xE5, 0xF0, 0x43, 0xE2, 0xEE, 0x8F, 0xA0,
+	0x7C, 0x2D, 0xF8, 0x81, 0x36, 0x91, 0x67, 0x79, 0xA1, 0xAC, 0xF7, 0x30, 0xC7, 0x63, 0x6D, 0x36,
+	0xF9, 0x3C, 0xE7, 0x50, 0xD9, 0x9A, 0x37, 0x23, 0x8F, 0x42, 0x2B, 0xE7, 0xC1, 0xFF, 0x00, 0x05,
+	0x02, 0xFD, 0xB0, 0xF1, 0x9F, 0xF8, 0x5D, 0x77, 0x1F, 0xF8, 0x29, 0xB1, 0xFF, 0x00, 0xE3, 0x14,
+	0x01, 0xED, 0x1F, 0xB0, 0xE7, 0xEC, 0x8B, 0xFB, 0x40, 0xFC, 0x21, 0xFD, 0xA0, 0x2C, 0x3C, 0x6D,
+	0xE3, 0xFF, 0x00, 0x04, 0x7D, 0x87, 0x4D, 0x86, 0xC6, 0xEA, 0x29, 0x24, 0xFB, 0x74, 0x72, 0x6D,
+	0x66, 0x88, 0xAA, 0xFC, 0xAA, 0xD9, 0xE4, 0x9F, 0x4C, 0x57, 0x1F, 0xF1, 0xFB, 0xF6, 0x1D, 0xFD,
+	0xA6, 0x7C, 0x6D, 0xF1, 0xB7, 0xC5, 0x9E, 0x2F, 0xF0, 0xC7, 0xC3, 0xDF, 0xB5, 0x69, 0xBA, 0x9E,
+	0xBD, 0x73, 0x71, 0x67, 0x3F, 0xF6, 0x84, 0x4B, 0xE6, 0x46, 0xCE, 0x48, 0x38, 0xDD, 0x9F, 0xCC,
+	0x57, 0x55, 0xFB, 0x0A, 0x7E, 0xD6, 0x7F, 0xB4, 0x47, 0xC5, 0xBF, 0xDA, 0x17, 0x4F, 0xF0, 0x57,
+	0xC4, 0x3F, 0x89, 0x53, 0x6A, 0x5A, 0x64, 0xD6, 0x17, 0x72, 0x49, 0x6B, 0x26, 0x9F, 0x6D, 0x18,
+	0x2E, 0x91, 0x6E, 0x53, 0xBA, 0x38, 0xD4, 0xFD, 0xE0, 0x4D, 0x72, 0x1F, 0xB4, 0x3F, 0xED, 0xAD,
+	0xFB, 0x51, 0x78, 0x17, 0xE3, 0xBF, 0x8C, 0x3C, 0x1D, 0xE1, 0x4F, 0x8B, 0x13, 0xD9, 0xE9, 0xBA,
+	0x6F, 0x88, 0x6E, 0xAD, 0xEC, 0x2D, 0x17, 0x4B, 0xB3, 0x61, 0x14, 0x6B, 0x21, 0xC2, 0xEE, 0x68,
+	0x4B, 0x1F, 0xC4, 0x9A, 0x00, 0xE5, 0x07, 0xFC, 0x13, 0xC7, 0xF6, 0xB7, 0x07, 0x3F, 0xF0, 0xAA,
+	0xFF, 0x00, 0xF2, 0xA9, 0x07, 0xF8, 0xD7, 0xD1, 0xFF, 0x00, 0xB2, 0x0F, 0xEC, 0xDF, 0xF1, 0x8F,
+	0xE1, 0x6F, 0xC0, 0x4F, 0x89, 0x5E, 0x0F, 0xF1, 0xCF, 0x85, 0xBE, 0xC9, 0x7F, 0xAF, 0x58, 0x32,
+	0x69, 0x71, 0xFD, 0xA9, 0x24, 0xF3, 0x58, 0xDA, 0xCA, 0x98, 0xC8, 0x6C, 0x2F, 0xCC, 0xC0, 0x73,
+	0x8E, 0xB5, 0xF3, 0x48, 0xFF, 0x00, 0x82, 0x80, 0xFE, 0xD8, 0x44, 0xE1, 0xBE, 0x34, 0xDC, 0x11,
+	0xDC, 0x7F, 0x64, 0xD8, 0xFF, 0x00, 0xF1, 0x8A, 0xFA, 0x57, 0xF6, 0x37, 0xFD, 0xA1, 0xFE, 0x34,
+	0xFC, 0x54, 0xF8, 0x07, 0xF1, 0x3B, 0xC5, 0x9E, 0x3E, 0xF1, 0xCC, 0x9A, 0x96, 0xA1, 0xA1, 0xE9,
+	0xB2, 0x3E, 0x97, 0x70, 0xD6, 0x70, 0x46, 0x61, 0x61, 0x69, 0x33, 0xE4, 0x04, 0x40, 0xA7, 0xE7,
+	0x50, 0x79, 0x1D, 0xA8, 0x03, 0xE7, 0x11, 0xFF, 0x00, 0x04, 0xF2, 0xFD, 0xAE, 0x36, 0x2A, 0x1F,
+	0x85, 0xD9, 0xDB, 0xFF, 0x00, 0x51, 0x48, 0x7D, 0x3F, 0xDE, 0x34, 0x2F, 0xFC, 0x13, 0xCB, 0xF6,
+	0xB6, 0x5E, 0xBF, 0x0B, 0xB6, 0xF6, 0xDD, 0xFD, 0xAB, 0x08, 0xC7, 0xBF, 0xDE, 0xAA, 0xE9, 0xFF,
+	0x00, 0x05, 0x03, 0xFD, 0xB1, 0x0A, 0x29, 0x3F, 0x1B, 0x2E, 0x0B, 0x77, 0xFF, 0x00, 0x89, 0x3D,
+	0x88, 0xF4, 0xFF, 0x00, 0xA6, 0x1F, 0xCF, 0x9A, 0x70, 0xFF, 0x00, 0x82, 0x80, 0xFE, 0xD8, 0x45,
+	0x86, 0xEF, 0x8D, 0x57, 0x1D, 0x7F, 0xE8, 0x11, 0x63, 0xFF, 0x00, 0xC6, 0x3D, 0x28, 0x03, 0xE8,
+	0x3F, 0x8F, 0x1F, 0xB3, 0x5F, 0xC6, 0xCF, 0x12, 0x7E, 0xC1, 0x5E, 0x0B, 0xF8, 0x41, 0xA0, 0xF8,
+	0x32, 0x4B, 0xAF, 0x11, 0x69, 0x5A, 0x94, 0x52, 0x5F, 0x69, 0xF1, 0xDD, 0x46, 0x0A, 0x28, 0x37,
+	0x19, 0x3B, 0x8B, 0x6D, 0x3F, 0x7D, 0x7A, 0x1E, 0xF5, 0xF2, 0xD7, 0xFC, 0x3B, 0xEF, 0xF6, 0xC1,
+	0x07, 0x27, 0xE0, 0xED, 0xC7, 0x4C, 0x7F, 0xC8, 0x4A, 0xDF, 0xFF, 0x00, 0x8E, 0x57, 0xD7, 0x3F,
+	0x13, 0xFF, 0x00, 0x68, 0x8F, 0x8D, 0x3A, 0x07, 0xFC, 0x13, 0xFF, 0x00, 0xC2, 0x9F, 0x19, 0x34,
+	0x9F, 0x1C, 0xC9, 0x0F, 0x89, 0xB5, 0x0B, 0xC8, 0x52, 0xF3, 0x54, 0x5B, 0x38, 0x18, 0xCA, 0x19,
+	0xAE, 0x01, 0x05, 0x1A, 0x32, 0x80, 0x1D, 0x89, 0xD0, 0x67, 0x8F, 0xAE, 0x7E, 0x66, 0x3F, 0xB7,
+	0xF7, 0xED, 0x7E, 0x78, 0x1F, 0x1A, 0x2E, 0x31, 0xFF, 0x00, 0x60, 0x7B, 0x1E, 0x3F, 0xF2, 0x05,
+	0x78, 0x79, 0x86, 0x43, 0x85, 0xCC, 0xAB, 0xFB, 0x5A, 0x8D, 0xA7, 0x6B, 0x68, 0x7E, 0x81, 0xC2,
+	0xFE, 0x22, 0xE7, 0x1C, 0x2B, 0x97, 0xBC, 0x26, 0x16, 0x11, 0x71, 0xBB, 0x77, 0x92, 0x6D, 0xEB,
+	0x6B, 0xEC, 0xD2, 0xE9, 0xD8, 0xDC, 0xFD, 0x98, 0xBF, 0x62, 0x4F, 0xDA, 0x87, 0xC1, 0x3F, 0xB4,
+	0x07, 0x84, 0xFC, 0x61, 0xE2, 0x9F, 0x85, 0xF3, 0x59, 0xE9, 0xBA, 0x7E, 0xAC, 0x25, 0xBC, 0xBA,
+	0x6B, 0xE8, 0x18, 0x46, 0x9B, 0x18, 0x67, 0x01, 0xC9, 0x3D, 0x47, 0x40, 0x6B, 0xE8, 0x0F, 0xDA,
+	0x3B, 0xE0, 0x17, 0xC5, 0xCF, 0x19, 0xFC, 0x60, 0xD5, 0x3C, 0x49, 0xE1, 0xAF, 0x06, 0xC9, 0x75,
+	0x65, 0x70, 0xB6, 0xE2, 0x2B, 0x85, 0x9A, 0x30, 0x1F, 0x6C, 0x28, 0xA7, 0x86, 0x60, 0x78, 0x20,
+	0x8E, 0x95, 0xE4, 0x7F, 0xB2, 0xA7, 0xED, 0x99, 0xFB, 0x4D, 0x7C, 0x42, 0xFD, 0xA2, 0xBC, 0x27,
+	0xE0, 0x9F, 0x19, 0x7C, 0x56, 0x9A, 0xFB, 0x4B, 0xD4, 0xB5, 0x26, 0x8A, 0xF2, 0xCD, 0xB4, 0xBB,
+	0x48, 0xFC, 0xD4, 0xF2, 0xA4, 0x6C, 0x6E, 0x48, 0x83, 0x0E, 0x54, 0x74, 0x22, 0xB7, 0xBF, 0x6E,
+	0x5F, 0xDA, 0xD3, 0xF6, 0x8A, 0xF8, 0x4B, 0xFB, 0x46, 0x6A, 0x9E, 0x08, 0xF8, 0x79, 0xF1, 0x2E,
+	0x6D, 0x33, 0x4B, 0xB7, 0xB1, 0xB3, 0x92, 0x1B, 0x48, 0xF4, 0xFB, 0x59, 0x02, 0xB3, 0xC2, 0x19,
+	0x8E, 0xE9, 0x22, 0x66, 0xE4, 0xFB, 0xD7, 0xC8, 0xF1, 0x57, 0x86, 0x59, 0x37, 0x15, 0x64, 0xAB,
+	0x2D, 0xC4, 0x4E, 0x51, 0x87, 0x32, 0x95, 0xD3, 0x57, 0xBA, 0x56, 0xEA, 0x99, 0x38, 0xFF, 0x00,
+	0x10, 0x73, 0x7C, 0xC7, 0x36, 0x86, 0x61, 0x52, 0x31, 0x53, 0x8C, 0x5C, 0x52, 0x49, 0xDA, 0xCD,
+	0xDF, 0xBE, 0xE4, 0xC3, 0xF6, 0x5A, 0xF8, 0xF0, 0xDF, 0x77, 0xE1, 0xFC, 0xDF, 0xF8, 0x11, 0x0F,
+	0xFF, 0x00, 0x17, 0x5E, 0xBB, 0xF0, 0x37, 0xE0, 0xE7, 0xC4, 0x9F, 0x0C, 0xFC, 0x12, 0xF1, 0xC7,
+	0x85, 0x35, 0xCF, 0x0D, 0xB5, 0xBE, 0xA1, 0xAC, 0x59, 0xC8, 0x9A, 0x7C, 0x32, 0x4A, 0x9F, 0xBD,
+	0x63, 0x6E, 0x54, 0x74, 0x6C, 0x0E, 0x78, 0xE4, 0x8A, 0xF8, 0xF9, 0xBF, 0x6F, 0xEF, 0xDB, 0x07,
+	0x1B, 0x7F, 0xE1, 0x74, 0xDC, 0x37, 0xD7, 0x48, 0xB1, 0xFF, 0x00, 0xE3, 0x15, 0xF5, 0x07, 0xEC,
+	0x73, 0xFB, 0x41, 0x7C, 0x62, 0xF8, 0x9B, 0xFB, 0x35, 0xFC, 0x41, 0xF1, 0xD7, 0x8E, 0x3C, 0x71,
+	0x26, 0xA1, 0xAA, 0xE8, 0xD2, 0x4E, 0x34, 0xDB, 0xC6, 0xB3, 0xB7, 0x8C, 0xC2, 0x16, 0xD4, 0x3A,
+	0xFC, 0xB1, 0x46, 0x8A, 0x79, 0xE7, 0xE6, 0x04, 0xD7, 0xCD, 0xF0, 0x67, 0x81, 0xBC, 0x37, 0xC1,
+	0x39, 0xE4, 0x33, 0x3C, 0x25, 0x59, 0xCA, 0x71, 0x4D, 0x25, 0x26, 0x9A, 0xD7, 0x47, 0xB2, 0x47,
+	0x9D, 0x9B, 0xF1, 0x8E, 0x63, 0x9C, 0xE0, 0xDE, 0x1E, 0xB4, 0x62, 0x93, 0x69, 0xE8, 0x9D, 0xF4,
+	0xF9, 0x9F, 0x32, 0xC5, 0xFF, 0x00, 0x04, 0xF1, 0xFD, 0xAD, 0xD6, 0x15, 0x46, 0xF8, 0x5F, 0x9F,
+	0x94, 0x71, 0xFD, 0xA9, 0x0F, 0x1C, 0x7A, 0x6E, 0x35, 0x2D, 0xBF, 0xFC, 0x13, 0xD3, 0xF6, 0xB5,
+	0x8E, 0xE2, 0x37, 0x7F, 0x85, 0xD8, 0x0B, 0x22, 0x92, 0x7F, 0xB4, 0xA0, 0x3D, 0xFF, 0x00, 0xDE,
+	0x15, 0x4A, 0x2F, 0xF8, 0x28, 0x1F, 0xED, 0x8A, 0xD1, 0xA9, 0x6F, 0x8D, 0x77, 0x1C, 0xAE, 0x7F,
+	0xE4, 0x0F, 0x63, 0xE8, 0x3F, 0xE9, 0x85, 0x4D, 0x6D, 0xFB, 0x7F, 0xFE, 0xD8, 0x4F, 0x71, 0x1C,
+	0x6F, 0xF1, 0xAE, 0xE3, 0xE6, 0x60, 0x3F, 0xE4, 0x11, 0x63, 0xEB, 0xFF, 0x00, 0x5C, 0x2B, 0xF6,
+	0xE3, 0xE4, 0x8F, 0xA6, 0xBF, 0x6F, 0x9F, 0xD9, 0xBF, 0xE3, 0x17, 0xC6, 0x7F, 0x09, 0x7C, 0x3F,
+	0xD2, 0xFE, 0x1C, 0xF8, 0x57, 0xFB, 0x42, 0x6D, 0x0E, 0xCE, 0xE2, 0x3D, 0x49, 0x7E, 0xD5, 0x1A,
+	0x79, 0x2C, 0xD1, 0xDB, 0x01, 0xCB, 0x1E, 0x72, 0x51, 0xBA, 0x67, 0xA5, 0x7C, 0xD2, 0xBF, 0xF0,
+	0x4F, 0x1F, 0xDA, 0xDF, 0x3B, 0x87, 0xC2, 0xDF, 0xFC, 0xA9, 0xC1, 0xFE, 0x35, 0xF4, 0x87, 0xED,
+	0xFB, 0xFB, 0x43, 0xFC, 0x67, 0xF8, 0x37, 0xE1, 0x1F, 0x87, 0xBA, 0xA7, 0xC3, 0x3F, 0x1C, 0xCD,
+	0xA5, 0x5C, 0x6B, 0x56, 0x37, 0x0F, 0xAA, 0x32, 0x59, 0xDB, 0xC9, 0xE7, 0x95, 0x8E, 0xD8, 0xAF,
+	0xFA, 0xC8, 0xDB, 0x18, 0x2E, 0xFD, 0x30, 0x39, 0xAF, 0x9A, 0x47, 0xFC, 0x14, 0x0F, 0xF6, 0xC3,
+	0x23, 0x0D, 0xF1, 0xAA, 0xE3, 0xDB, 0xFE, 0x24, 0xF6, 0x3F, 0xFC, 0x62, 0x80, 0x3D, 0xD3, 0xF6,
+	0x0A, 0xFD, 0x90, 0xFE, 0x35, 0x7C, 0x24, 0xF8, 0xC9, 0x7D, 0xE2, 0x2F, 0x8A, 0x9E, 0x03, 0x8E,
+	0xCF, 0x4B, 0x9F, 0xC3, 0xB3, 0x5A, 0xAC, 0x92, 0x5D, 0x45, 0x2E, 0x64, 0x69, 0x61, 0x60, 0xBF,
+	0x29, 0x27, 0xA2, 0x13, 0x9F, 0x6A, 0xF4, 0x0B, 0x3F, 0x06, 0xFC, 0x76, 0xFF, 0x00, 0x84, 0xF7,
+	0x5B, 0xD2, 0x35, 0x8F, 0x85, 0x86, 0x1D, 0x16, 0x2D, 0x52, 0xE3, 0xFB, 0x17, 0x56, 0xB5, 0xBD,
+	0x8B, 0xF7, 0xB6, 0xBB, 0xFF, 0x00, 0x77, 0xBD, 0x37, 0xE4, 0x1D, 0xB8, 0xC6, 0x07, 0x6F, 0x7A,
+	0xE0, 0x7F, 0xE0, 0x9E, 0xBF, 0xB5, 0x27, 0xC7, 0xEF, 0x8D, 0x3F, 0x1C, 0x6E, 0xBC, 0x23, 0xF1,
+	0x3F, 0xE2, 0x1C, 0xDA, 0xAE, 0x9F, 0x17, 0x87, 0xAE, 0x2E, 0x52, 0xDE, 0x4B, 0x1B, 0x68, 0xB6,
+	0xCA, 0xB2, 0xC2, 0xA1, 0xB3, 0x14, 0x4A, 0xDC, 0x07, 0x61, 0x8C, 0xE3, 0x9A, 0xF3, 0x5F, 0x8F,
+	0xDF, 0xB6, 0xE7, 0xED, 0x49, 0xE1, 0x0F, 0x8D, 0xDE, 0x2D, 0xF0, 0xA7, 0x86, 0xBE, 0x2D, 0x5C,
+	0x5A, 0xE9, 0xFA, 0x6F, 0x88, 0x6E, 0xAD, 0xEC, 0x6D, 0xC6, 0x97, 0x66, 0xDE, 0x54, 0x6B, 0x2B,
+	0x05, 0x5C, 0xB4, 0x24, 0xB6, 0x06, 0x07, 0xCC, 0x49, 0xF7, 0xAF, 0xCE, 0x78, 0xFB, 0xC2, 0xEE,
+	0x13, 0xF1, 0x17, 0x00, 0xE8, 0x66, 0x54, 0x57, 0x3D, 0xAD, 0x19, 0xC7, 0x49, 0x2F, 0x9F, 0x55,
+	0xEB, 0xA1, 0xDD, 0x81, 0xCC, 0xB1, 0x18, 0x1A, 0x9C, 0xD4, 0xDF, 0xCB, 0xA1, 0xF4, 0x65, 0xC5,
+	0xB4, 0xF6, 0xD3, 0xB5, 0xAD, 0xD4, 0x0F, 0x1C, 0xCB, 0xF7, 0xE3, 0x65, 0xDA, 0x57, 0x1E, 0xD5,
+	0x19, 0x61, 0xB7, 0x21, 0x7A, 0xF2, 0xBE, 0xF5, 0xF1, 0xEC, 0xFF, 0x00, 0xB6, 0xCF, 0xED, 0x31,
+	0xA9, 0xDD, 0xC3, 0x77, 0xAF, 0x7C, 0x42, 0x8F, 0x50, 0x58, 0x5C, 0x1F, 0x2A, 0xEB, 0x47, 0xB4,
+	0x01, 0xBE, 0xAD, 0x1C, 0x2A, 0xE4, 0x7D, 0x19, 0x4F, 0xBF, 0x63, 0xF5, 0x17, 0x80, 0x3C, 0x6C,
+	0xBE, 0x21, 0xFD, 0x9C, 0xEC, 0x7F, 0x68, 0x6F, 0x15, 0xB5, 0xBE, 0x97, 0x63, 0x34, 0x92, 0xC5,
+	0x7A, 0xAA, 0xCC, 0xCB, 0x0B, 0x24, 0xED, 0x08, 0x6E, 0x9F, 0x75, 0xB6, 0x83, 0xD3, 0x8C, 0xF3,
+	0x9E, 0xA3, 0xFC, 0xFF, 0x00, 0xF1, 0x0F, 0xE8, 0xC3, 0xC6, 0x5C, 0x2B, 0x52, 0x78, 0x8C, 0xAE,
+	0x3F, 0x59, 0xA0, 0xB6, 0x71, 0xF8, 0x92, 0xF3, 0x8E, 0xEF, 0xD5, 0x5C, 0xFB, 0x9C, 0xBF, 0x88,
+	0xB0, 0xB8, 0x8B, 0x46, 0xA7, 0xBB, 0x2F, 0x3D, 0xBE, 0xF3, 0xA0, 0xC1, 0x53, 0xC8, 0xA0, 0x7B,
+	0xD5, 0x5D, 0x17, 0x5D, 0xD0, 0xFC, 0x47, 0x60, 0x35, 0x2F, 0x0F, 0x6A, 0xF6, 0xF7, 0xD6, 0xFC,
+	0x6D, 0xB8, 0xB5, 0x98, 0x3A, 0xF3, 0xEB, 0x83, 0xC7, 0xE3, 0x56, 0xB0, 0x77, 0x6C, 0x23, 0xE6,
+	0xFE, 0xE9, 0xAF, 0xE6, 0xBC, 0x66, 0x5F, 0x8D, 0xCB, 0xEB, 0x3A, 0x58, 0x9A, 0x6E, 0x12, 0x5A,
+	0x34, 0xD3, 0x4F, 0xF1, 0x3E, 0x86, 0x35, 0x23, 0x52, 0x3C, 0xD1, 0x77, 0x41, 0x45, 0x00, 0x12,
+	0x32, 0x05, 0x07, 0x8E, 0xB5, 0xC2, 0x68, 0x78, 0x0F, 0xFC, 0x15, 0x0F, 0xFE, 0x4C, 0x5F, 0xC7,
+	0xDF, 0xF6, 0x0B, 0x8F, 0xFF, 0x00, 0x47, 0xC7, 0x5F, 0x87, 0x35, 0xFB, 0x8D, 0xFF, 0x00, 0x05,
+	0x42, 0x53, 0xFF, 0x00, 0x0C, 0x31, 0xE3, 0xE3, 0xFF, 0x00, 0x50, 0xB8, 0xFF, 0x00, 0xF4, 0x7C,
+	0x75, 0xF8, 0x76, 0xCA, 0x41, 0x3C, 0x57, 0xF7, 0x57, 0xD1, 0xAF, 0xFE, 0x48, 0xFA, 0xBF, 0xF5,
+	0xF1, 0xFE, 0x48, 0xFE, 0xC6, 0xFA, 0x36, 0xFF, 0x00, 0xC8, 0x83, 0x17, 0xFF, 0x00, 0x5F, 0x17,
+	0xFE, 0x92, 0x86, 0xFF, 0x00, 0x0F, 0xFC, 0x07, 0xFA, 0x57, 0xEB, 0xD7, 0xFC, 0x10, 0xFB, 0xFE,
+	0x4D, 0x22, 0xFB, 0xFE, 0xC6, 0xEB, 0xCF, 0xFD, 0x02, 0x1A, 0xFC, 0x85, 0xE4, 0x9C, 0x01, 0x5F,
+	0xAF, 0x3F, 0xF0, 0x43, 0xDE, 0x7F, 0x64, 0x9B, 0xF3, 0xFF, 0x00, 0x53, 0x75, 0xE7, 0xFE, 0x8B,
+	0x86, 0xBD, 0x6F, 0xA4, 0x27, 0xFC, 0x9B, 0xF9, 0xFF, 0x00, 0x8E, 0x3F, 0x99, 0xEC, 0x7D, 0x21,
+	0xBF, 0xE4, 0x89, 0x87, 0xFD, 0x7D, 0x8F, 0xE4, 0xCF, 0xB2, 0xE8, 0xA2, 0x82, 0x71, 0xD6, 0xBF,
+	0x80, 0x65, 0xB9, 0xFC, 0x42, 0x14, 0x51, 0x83, 0x9C, 0x62, 0xA3, 0xBC, 0xBD, 0xB1, 0xD2, 0xED,
+	0x1F, 0x51, 0xD4, 0xEF, 0x22, 0xB7, 0xB7, 0x8F, 0xFD, 0x64, 0xF3, 0x48, 0x15, 0x17, 0xEA, 0x4F,
+	0x15, 0xD5, 0x86, 0xC1, 0xE2, 0x31, 0x95, 0x15, 0x3A, 0x30, 0x72, 0x6F, 0x64, 0x95, 0xD9, 0x12,
+	0xA9, 0x18, 0xEA, 0xD9, 0x28, 0x19, 0x3B, 0x48, 0xFA, 0x71, 0x4B, 0x12, 0x34, 0x8E, 0xA8, 0x88,
+	0xCC, 0xCD, 0xF7, 0x55, 0x7F, 0x8B, 0xE9, 0xEB, 0x59, 0xB3, 0xF8, 0x86, 0xC6, 0xEB, 0xE0, 0xBF,
+	0x88, 0xFE, 0x36, 0xF8, 0x46, 0xF2, 0xD7, 0x54, 0xD3, 0x74, 0x1B, 0x5B, 0x99, 0x37, 0x43, 0x31,
+	0x02, 0x79, 0x21, 0x5C, 0x94, 0x0D, 0x8E, 0x39, 0xC7, 0x38, 0x23, 0xD2, 0xBE, 0x51, 0xBA, 0xFD,
+	0xB6, 0xFF, 0x00, 0x68, 0x44, 0xD6, 0x24, 0xD5, 0x7C, 0x35, 0xE2, 0x8B, 0x5D, 0x1D, 0x5B, 0x02,
+	0x3B, 0x7B, 0x5D, 0x26, 0xDE, 0x61, 0x1A, 0x8E, 0x9F, 0x34, 0xF1, 0xBB, 0x13, 0xEE, 0x36, 0x8F,
+	0x6A, 0xFE, 0x83, 0xF0, 0xFB, 0xE8, 0xD9, 0xC7, 0x3C, 0x61, 0x52, 0x15, 0xB1, 0x70, 0xFA, 0xB5,
+	0x07, 0x66, 0xE5, 0x35, 0xEF, 0x35, 0xE5, 0x1D, 0xEF, 0xEB, 0x63, 0xC2, 0xC7, 0x71, 0x16, 0x0F,
+	0x0A, 0x9A, 0x8B, 0xE6, 0x97, 0x91, 0xF5, 0xC7, 0x8D, 0x3C, 0x29, 0xF1, 0xD2, 0xDA, 0xDE, 0xDE,
+	0x2F, 0x87, 0xBF, 0x0A, 0xA4, 0xD4, 0xA4, 0xB8, 0x2A, 0x64, 0x9E, 0xE2, 0xEA, 0x38, 0xA2, 0x85,
+	0x33, 0xF3, 0x12, 0xA5, 0x83, 0x31, 0xC7, 0x41, 0x8E, 0xBF, 0x4A, 0xE5, 0x7F, 0x6F, 0xBF, 0xD9,
+	0x33, 0xE2, 0xB7, 0xC5, 0x4F, 0x15, 0x78, 0x72, 0x7F, 0x83, 0x5E, 0x0A, 0x5B, 0xDB, 0x2D, 0x37,
+	0x49, 0x78, 0xA6, 0x61, 0x73, 0x1C, 0x62, 0x39, 0x4C, 0xA4, 0xF4, 0x73, 0x92, 0x48, 0xFE, 0x95,
+	0xE0, 0x7A, 0x07, 0xED, 0xED, 0xFB, 0x5D, 0x5C, 0xEB, 0x36, 0x76, 0x37, 0x1F, 0x18, 0xEE, 0x1A,
+	0x39, 0xAF, 0x23, 0x59, 0x07, 0xF6, 0x4D, 0x8F, 0x2A, 0x58, 0x67, 0xA4, 0x19, 0x1F, 0x87, 0x35,
+	0xF4, 0x37, 0xFC, 0x14, 0x77, 0xF6, 0x90, 0xF8, 0xDF, 0xF0, 0x37, 0xC7, 0x5E, 0x1D, 0xD1, 0xFE,
+	0x15, 0x78, 0xF6, 0x6D, 0x26, 0xDA, 0xFB, 0x48, 0x92, 0x6B, 0xA8, 0xD6, 0xC6, 0xDE, 0x5D, 0xF2,
+	0x09, 0x48, 0xDD, 0x99, 0x63, 0x7C, 0x71, 0xE9, 0x81, 0x5F, 0xE8, 0x1F, 0x87, 0x7E, 0x0F, 0xF0,
+	0x8F, 0x87, 0x38, 0x35, 0x1C, 0x15, 0x25, 0x3A, 0xAD, 0x7B, 0xD5, 0x25, 0xAC, 0x9F, 0xA6, 0x9A,
+	0x2F, 0x24, 0x7C, 0x2E, 0x61, 0x9A, 0x62, 0xB1, 0xF2, 0xBC, 0xDE, 0x9D, 0x96, 0xC7, 0xCE, 0xE7,
+	0xFE, 0x09, 0xE7, 0xFB, 0x5B, 0x7F, 0xD1, 0x2C, 0xE9, 0xBB, 0x69, 0x3A, 0x9C, 0x19, 0xFE, 0x75,
+	0xF4, 0x5F, 0xFC, 0x13, 0x8F, 0xF6, 0x65, 0xF8, 0xD1, 0xF0, 0x2B, 0xC7, 0xDE, 0x25, 0xD6, 0xBE,
+	0x27, 0xF8, 0x4B, 0xFB, 0x36, 0xDA, 0xFF, 0x00, 0x47, 0x86, 0x2B, 0x57, 0xFB, 0x54, 0x72, 0x79,
+	0x8E, 0x25, 0x2C, 0x46, 0x10, 0x9C, 0x60, 0x7A, 0xD7, 0xCD, 0x9F, 0xF0, 0xF0, 0x1F, 0xDB, 0x0F,
+	0x38, 0xFF, 0x00, 0x85, 0xD7, 0x71, 0xFF, 0x00, 0x82, 0x9B, 0x1F, 0xFE, 0x31, 0x5F, 0x47, 0x7F,
+	0xC1, 0x37, 0xBF, 0x69, 0x1F, 0x8D, 0xFF, 0x00, 0x1C, 0xBC, 0x7D, 0xE2, 0x5D, 0x1B, 0xE2, 0x9F,
+	0x8E, 0xE4, 0xD5, 0xED, 0xEC, 0x74, 0x78, 0x26, 0xB5, 0x8D, 0xAC, 0x6D, 0xE2, 0xF2, 0xE4, 0x32,
+	0xB0, 0x66, 0xCC, 0x51, 0x29, 0x39, 0xF4, 0x24, 0x8F, 0x6E, 0x95, 0xFA, 0xB7, 0x9B, 0x3C, 0xD3,
+	0xC2, 0x3C, 0x51, 0xFB, 0x00, 0x7E, 0xD5, 0x9A, 0x9F, 0x89, 0x75, 0x2B, 0xFB, 0x3F, 0x86, 0x9E,
+	0x64, 0x53, 0xEA, 0x13, 0x4B, 0x13, 0x7F, 0x6A, 0x43, 0xF7, 0x5A, 0x46, 0x23, 0x8D, 0xDC, 0x70,
+	0x7E, 0xB5, 0x43, 0xFE, 0x1D, 0xE5, 0xFB, 0x5B, 0x2F, 0xFC, 0xD2, 0xFD, 0xBF, 0xED, 0x7F, 0x6A,
+	0xC2, 0x31, 0xFF, 0x00, 0x8F, 0x54, 0xFE, 0x28, 0xFD, 0xBD, 0x7F, 0x6B, 0xAD, 0x3B, 0xC4, 0xDA,
+	0x96, 0x9F, 0x67, 0xF1, 0x92, 0xE2, 0x38, 0x6D, 0xEF, 0xE6, 0x8E, 0x35, 0xFE, 0xC9, 0xB2, 0x3B,
+	0x54, 0x48, 0xC0, 0x0C, 0x98, 0x49, 0x3C, 0x01, 0xD4, 0xD5, 0x11, 0xFF, 0x00, 0x05, 0x00, 0xFD,
+	0xB1, 0x09, 0xFF, 0x00, 0x92, 0xD7, 0x71, 0xFF, 0x00, 0x82, 0x7B, 0x13, 0xFF, 0x00, 0xB4, 0x28,
+	0x03, 0xEB, 0x8D, 0x67, 0xE0, 0xA7, 0xC5, 0x0F, 0xF8, 0x63, 0xCF, 0x05, 0xFC, 0x30, 0x87, 0xC3,
+	0x4D, 0x26, 0xB9, 0xA5, 0xDB, 0xDB, 0xAD, 0xFD, 0x9A, 0xCC, 0x84, 0xC6, 0x53, 0x76, 0xEF, 0x98,
+	0xB6, 0x0E, 0x32, 0x3A, 0x13, 0x5E, 0x53, 0xFF, 0x00, 0x0C, 0xB3, 0xF1, 0xE4, 0x63, 0xFE, 0x28,
+	0x1B, 0x8F, 0xBB, 0xFF, 0x00, 0x3F, 0x10, 0xFF, 0x00, 0xF1, 0x75, 0xDD, 0xFC, 0x60, 0xFD, 0xA1,
+	0x3E, 0x31, 0x78, 0x67, 0xF6, 0x03, 0xF0, 0x8F, 0xC6, 0x3D, 0x0B, 0xC6, 0xD2, 0x5B, 0xF8, 0x93,
+	0x52, 0xFB, 0x0F, 0xDB, 0x35, 0x4F, 0xB2, 0xC0, 0xED, 0x2F, 0x98, 0xCD, 0xBB, 0xE5, 0x68, 0xD9,
+	0x07, 0x41, 0xD0, 0x0A, 0xF9, 0x89, 0xBF, 0xE0, 0xA0, 0x3F, 0xB6, 0x0B, 0x7F, 0xCD, 0x68, 0xB8,
+	0xFF, 0x00, 0xC1, 0x3D, 0x8F, 0xFF, 0x00, 0x18, 0xAF, 0xC5, 0xF8, 0xDF, 0xC1, 0x3E, 0x1D, 0xE3,
+	0xAC, 0xE7, 0xFB, 0x47, 0x1B, 0x52, 0x71, 0x9F, 0x2A, 0x8D, 0xA2, 0xD2, 0x56, 0x5B, 0x6E, 0x9B,
+	0x3E, 0xAB, 0x27, 0xE2, 0xEC, 0xC3, 0x26, 0xC1, 0xFB, 0x0A, 0x31, 0x8B, 0x8D, 0xEF, 0xAA, 0x77,
+	0xD7, 0xE6, 0x7D, 0x0F, 0xF0, 0x6F, 0xF6, 0x75, 0xF8, 0xC9, 0xE1, 0xDF, 0x8A, 0x3A, 0x1E, 0xB9,
+	0xAD, 0xF8, 0x2A, 0x68, 0x6D, 0x6D, 0x75, 0x08, 0xE4, 0xB8, 0x99, 0xA7, 0x8B, 0x08, 0xA0, 0xF2,
+	0x78, 0x72, 0x6B, 0xCE, 0xFF, 0x00, 0x6D, 0x9F, 0xD8, 0xEB, 0xF6, 0x93, 0xF8, 0xA7, 0xFB, 0x4B,
+	0x78, 0x83, 0xC7, 0x3E, 0x03, 0xF8, 0x67, 0x3E, 0xA1, 0xA5, 0xDE, 0x2D, 0xB7, 0xD9, 0xAF, 0x21,
+	0xBC, 0x81, 0x43, 0xED, 0x85, 0x54, 0xF0, 0xCE, 0x0F, 0x04, 0x11, 0xC8, 0xA6, 0x7E, 0xCA, 0xFF,
+	0x00, 0xB6, 0x67, 0xED, 0x37, 0xF1, 0x0B, 0xF6, 0x81, 0xF0, 0xBF, 0x82, 0xFC, 0x63, 0xF1, 0x56,
+	0x7B, 0xED, 0x33, 0x50, 0xD4, 0x96, 0x2B, 0xCB, 0x56, 0xD2, 0xED, 0x10, 0x4A, 0xBB, 0x4F, 0x1B,
+	0x92, 0x25, 0x61, 0xF8, 0x11, 0x5B, 0x1F, 0xB6, 0xF7, 0xED, 0x73, 0xFB, 0x46, 0x7C, 0x25, 0xFD,
+	0xA4, 0x35, 0xAF, 0x03, 0x7C, 0x3B, 0xF8, 0x9D, 0x36, 0x9B, 0xA4, 0xDA, 0xDB, 0xDA, 0xB4, 0x16,
+	0x6B, 0xA7, 0xDA, 0xC9, 0xB0, 0xBD, 0xBC, 0x6E, 0xDF, 0x34, 0x91, 0x33, 0x1C, 0xB3, 0x13, 0xF7,
+	0xAB, 0xEA, 0xB8, 0x07, 0xC3, 0xFC, 0xAF, 0xC3, 0xDC, 0x05, 0x4C, 0x26, 0x06, 0x52, 0x94, 0x65,
+	0x2E, 0x66, 0xE4, 0xD3, 0x77, 0xB5, 0xB4, 0xB2, 0x5A, 0x1C, 0x19, 0xBE, 0x7D, 0x8A, 0xCE, 0x71,
+	0x51, 0xAD, 0x59, 0x24, 0xE2, 0xAC, 0xAD, 0xF7, 0x9E, 0x24, 0xDF, 0xF0, 0x4F, 0x7F, 0xDB, 0x0F,
+	0x1F, 0xF2, 0x46, 0xEF, 0x3F, 0x1D, 0x42, 0xD8, 0xFF, 0x00, 0xED, 0x4A, 0xFA, 0xAF, 0xF6, 0x22,
+	0xFD, 0x9D, 0xFE, 0x32, 0x7C, 0x2E, 0xFD, 0x99, 0x3E, 0x25, 0x78, 0x0F, 0xC7, 0xBE, 0x0A, 0x93,
+	0x4F, 0xD5, 0x35, 0xE6, 0xBB, 0x1A, 0x5D, 0xAC, 0x93, 0xC6, 0xC6, 0x6D, 0xFA, 0x7A, 0xC6, 0xBC,
+	0xAB, 0x10, 0x32, 0xE3, 0x6F, 0x24, 0x57, 0xCD, 0x07, 0xFE, 0x0A, 0x05, 0xFB, 0x61, 0xE3, 0xE6,
+	0xF8, 0xD7, 0x70, 0xDF, 0x5D, 0x1E, 0xC7, 0xFF, 0x00, 0x8C, 0x7F, 0x2C, 0x57, 0xD4, 0x9F, 0xB1,
+	0xE7, 0xED, 0x03, 0xF1, 0x8B, 0xE2, 0x67, 0xEC, 0xBF, 0xF1, 0x0B, 0xE2, 0x07, 0x8E, 0xBC, 0x6D,
+	0x26, 0xA1, 0xAC, 0x68, 0xAB, 0x78, 0x74, 0xDB, 0xD7, 0xB3, 0x82, 0x33, 0x6F, 0xB2, 0xC4, 0x48,
+	0xBF, 0x2C, 0x71, 0xAA, 0xB6, 0x1F, 0x2D, 0xF3, 0x03, 0x5F, 0x7C, 0x79, 0x13, 0xAB, 0x2A, 0x8A,
+	0xCC, 0xF9, 0x8C, 0x7F, 0xC1, 0x3C, 0xBF, 0x6B, 0x7D, 0x8A, 0xA7, 0xE1, 0x70, 0xF9, 0x47, 0x6D,
+	0x52, 0x1F, 0x4F, 0xF7, 0x8D, 0x0B, 0xFF, 0x00, 0x04, 0xF2, 0xFD, 0xAD, 0x54, 0xE7, 0xFE, 0x15,
+	0x7E, 0x3F, 0xEE, 0x29, 0x0F, 0xF4, 0x6A, 0xAE, 0x3F, 0xE0, 0xA0, 0x5F, 0xB6, 0x11, 0x45, 0x3F,
+	0xF0, 0xBA, 0xAE, 0x33, 0xB7, 0xE6, 0xFF, 0x00, 0x89, 0x3D, 0x8F, 0xF4, 0x83, 0xEB, 0xF9, 0xD2,
+	0x8F, 0xF8, 0x28, 0x07, 0xED, 0x86, 0x78, 0x3F, 0x1A, 0xAE, 0x3F, 0xF0, 0x51, 0x63, 0xFF, 0x00,
+	0xC6, 0x28, 0x33, 0x3E, 0x80, 0xF1, 0x7F, 0xEC, 0xBF, 0xF1, 0xB3, 0x55, 0xFD, 0x82, 0x7C, 0x37,
+	0xF0, 0x56, 0xC7, 0xC2, 0x1B, 0xFC, 0x4B, 0xA7, 0xF8, 0x92, 0x4B, 0x8B, 0xAD, 0x3F, 0xED, 0x51,
+	0x8D, 0xB1, 0x99, 0x6E, 0x1F, 0x3B, 0xF7, 0x6D, 0x3F, 0x2B, 0xA9, 0xC0, 0x24, 0xF3, 0xD3, 0x83,
+	0x8F, 0x07, 0x6F, 0xF8, 0x27, 0x8F, 0xED, 0x6E, 0xE7, 0x27, 0xE1, 0x77, 0xE3, 0xFD, 0xA9, 0x0F,
+	0xFF, 0x00, 0x15, 0x5E, 0xE7, 0xE2, 0xFF, 0x00, 0xDA, 0x67, 0xE3, 0x96, 0x95, 0xFB, 0x02, 0x78,
+	0x6F, 0xE3, 0x45, 0x87, 0x8F, 0xE6, 0x8F, 0xC5, 0x17, 0xFE, 0x24, 0x78, 0x2E, 0xF5, 0x7F, 0xB0,
+	0xDB, 0x66, 0x48, 0xC4, 0xB3, 0xA0, 0x1B, 0x0C, 0x66, 0x31, 0x95, 0x55, 0x1C, 0x2F, 0x6E, 0xB5,
+	0xE0, 0x7F, 0xF0, 0xF0, 0x2F, 0xDB, 0x0F, 0x1C, 0x7C, 0x6A, 0xB9, 0xFF, 0x00, 0xC1, 0x3D, 0x97,
+	0xA7, 0xFD, 0x70, 0xC5, 0x00, 0x6C, 0xF8, 0x53, 0xF6, 0x01, 0xFD, 0xAB, 0xB4, 0xBF, 0x12, 0xE9,
+	0xF7, 0xF7, 0x7F, 0x0D, 0x3C, 0xB8, 0xE0, 0xBE, 0x86, 0x49, 0x1B, 0xFB, 0x52, 0x13, 0xF2, 0x87,
+	0x04, 0xFF, 0x00, 0x10, 0xEC, 0x2B, 0xD9, 0xBF, 0x6F, 0x7F, 0xD9, 0x77, 0xE3, 0x77, 0xC6, 0xFF,
+	0x00, 0x88, 0x7E, 0x1E, 0xF1, 0x07, 0xC3, 0x3F, 0x07, 0xFF, 0x00, 0x68, 0x5A, 0xD9, 0xF8, 0x6E,
+	0x3B, 0x6B, 0x87, 0xFB, 0x52, 0x45, 0xB6, 0x4F, 0x31, 0xCE, 0xDC, 0x31, 0x07, 0xA7, 0xB7, 0xE3,
+	0x9A, 0xF1, 0x2F, 0x0A, 0x7E, 0xDE, 0x9F, 0xB5, 0xC6, 0xA3, 0xE2, 0x8D, 0x36, 0xC2, 0xFB, 0xE3,
+	0x24, 0xF2, 0x43, 0x3E, 0xA1, 0x0C, 0x72, 0xA3, 0x69, 0x36, 0x63, 0x7A, 0x99, 0x14, 0x11, 0x91,
+	0x00, 0x23, 0x8D, 0xDE, 0xB5, 0xED, 0x3F, 0xB7, 0xEF, 0xED, 0x35, 0xF1, 0xD7, 0xE0, 0x97, 0xC4,
+	0x6F, 0x0E, 0xE8, 0x5F, 0x0B, 0x7E, 0x20, 0xCD, 0xA4, 0xDA, 0x5E, 0x78, 0x66, 0x2B, 0x8B, 0xA8,
+	0x96, 0xC6, 0xDA, 0x5F, 0x32, 0x4F, 0x31, 0x86, 0xEC, 0xCB, 0x1B, 0x6D, 0xFC, 0x31, 0x40, 0x1E,
+	0x18, 0xDF, 0xF0, 0x4F, 0x1F, 0xDA, 0xDC, 0xFF, 0x00, 0xCD, 0x2D, 0xEF, 0xFF, 0x00, 0x41, 0x48,
+	0x7F, 0xF8, 0xAA, 0xF6, 0x0F, 0xD8, 0x6B, 0xF6, 0x45, 0xFD, 0xA0, 0x7E, 0x10, 0xFE, 0xD0, 0x36,
+	0x1E, 0x36, 0xF1, 0xFF, 0x00, 0x82, 0x3E, 0xC3, 0xA6, 0xC3, 0xA7, 0xDD, 0x47, 0x24, 0xDF, 0xDA,
+	0x11, 0x49, 0xB5, 0x9A, 0x12, 0xAB, 0xC0, 0x6C, 0xF5, 0x38, 0xE9, 0xDE, 0xBC, 0x5C, 0x7F, 0xC1,
+	0x40, 0xBF, 0x6C, 0x20, 0x32, 0x3E, 0x34, 0xDC, 0xF6, 0xFF, 0x00, 0x98, 0x45, 0x8F, 0xFF, 0x00,
+	0x18, 0xAF, 0x64, 0xFD, 0x84, 0xFF, 0x00, 0x6B, 0x4F, 0xDA, 0x23, 0xE2, 0xDF, 0xED, 0x0F, 0xA7,
+	0xF8, 0x2B, 0xE2, 0x1F, 0xC4, 0xB9, 0xB5, 0x3D, 0x2E, 0x6B, 0x1B, 0xB9, 0x24, 0xB5, 0x7D, 0x3E,
+	0xDA, 0x30, 0x59, 0x62, 0xDC, 0xA7, 0x74, 0x71, 0xAB, 0x75, 0x19, 0xA0, 0x0F, 0xBB, 0x86, 0x7D,
+	0x28, 0xA0, 0x7D, 0xDE, 0x68, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x0F, 0xCF, 0x6F, 0xF8, 0x2B, 0x67,
+	0xFC, 0x97, 0x5D, 0x00, 0xFA, 0x78, 0x64, 0x7F, 0xE8, 0xF7, 0xAF, 0x95, 0x2B, 0xF4, 0x63, 0xF6,
+	0xD6, 0xFD, 0x87, 0xFC, 0x79, 0xFB, 0x4D, 0xFC, 0x46, 0xD2, 0xFC, 0x69, 0xE1, 0x4F, 0x17, 0xE9,
+	0x3A, 0x6C, 0x7A, 0x7E, 0x97, 0xF6, 0x56, 0x8E, 0xFC, 0x4B, 0xB9, 0x9C, 0x48, 0xCE, 0x1B, 0xE4,
+	0x53, 0xC7, 0xCD, 0x8A, 0xF1, 0xC5, 0xFF, 0x00, 0x82, 0x44, 0xFC, 0x61, 0x5E, 0x17, 0xE2, 0x8F,
+	0x86, 0xF1, 0xDB, 0x8B, 0x9F, 0xFE, 0x22, 0x80, 0x38, 0xAF, 0xF8, 0x26, 0x69, 0x03, 0xF6, 0xAE,
+	0xD2, 0x89, 0x3F, 0xF3, 0x0C, 0xBE, 0xEB, 0xFF, 0x00, 0x5C, 0x5A, 0xB8, 0x1F, 0xDA, 0xD3, 0x9F,
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+	0x4F, 0xBF, 0x89, 0x5F, 0xB3, 0xDF, 0xC6, 0x4B, 0x5F, 0x89, 0x7A, 0xF7, 0x8C, 0xF4, 0x5D, 0x42,
+	0xDA, 0xDE, 0xCE, 0xE2, 0x16, 0xB5, 0xB3, 0x69, 0x95, 0xD8, 0xBC, 0x65, 0x47, 0x2C, 0x80, 0x77,
+	0xAE, 0x73, 0xE3, 0x37, 0xFC, 0x13, 0x0F, 0xE2, 0x9F, 0xC4, 0xDF, 0x8B, 0x7E, 0x24, 0xF8, 0x89,
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+	0xA7, 0x2B, 0x8A, 0xA1, 0xFF, 0x00, 0x0E, 0x8A, 0xF8, 0xC6, 0x0E, 0x47, 0xC5, 0x0F, 0x0D, 0x7E,
+	0x57, 0x3F, 0xFC, 0x45, 0x7B, 0x77, 0xEC, 0xCF, 0xFB, 0x1A, 0x78, 0xEF, 0xE0, 0x6F, 0xC2, 0x5F,
+	0x1C, 0x7C, 0x3A, 0xD7, 0x7C, 0x4F, 0xA4, 0xDF, 0x5C, 0x78, 0xB2, 0xD1, 0xE0, 0xB6, 0xB8, 0xB5,
+	0x69, 0x42, 0x5B, 0xEE, 0xB7, 0x96, 0x3C, 0xB0, 0x65, 0x04, 0xF3, 0x27, 0x6F, 0x4A, 0x00, 0xFC,
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+	0x12, 0xA0, 0x4F, 0xF8, 0x5A, 0x1E, 0x1B, 0xE3, 0x9F, 0xBB, 0x71, 0xC9, 0x3D, 0x4F, 0xDC, 0xF6,
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+	0xC4, 0x50, 0x06, 0xA7, 0xC6, 0x73, 0x8F, 0xF8, 0x25, 0x8F, 0x82, 0x46, 0x7F, 0xE6, 0x25, 0x6F,
+	0xFF, 0x00, 0xA1, 0xDD, 0x57, 0xC6, 0xF9, 0x19, 0xC0, 0x35, 0xFA, 0x4B, 0xE3, 0xCF, 0xD8, 0xE3,
+	0xC7, 0x9E, 0x2D, 0xFD, 0x90, 0xFC, 0x3F, 0xFB, 0x38, 0xDA, 0x78, 0x9F, 0x4B, 0x87, 0x50, 0xD1,
+	0xEE, 0xA2, 0x96, 0x5D, 0x4A, 0x46, 0x97, 0xC9, 0x70, 0xAD, 0x31, 0x20, 0x00, 0xB9, 0xCF, 0xEF,
+	0x3D, 0x3B, 0x57, 0x87, 0x2F, 0xFC, 0x12, 0x2F, 0xE3, 0x16, 0x39, 0xF8, 0x9D, 0xE1, 0xA5, 0xE0,
+	0x71, 0xB6, 0xE3, 0xF1, 0xFE, 0x0A, 0x00, 0xF1, 0xFF, 0x00, 0xD8, 0x83, 0xFE, 0x4E, 0xD3, 0xC0,
+	0xBF, 0xF6, 0x18, 0x6F, 0xFD, 0x11, 0x2D, 0x75, 0x1F, 0xF0, 0x52, 0xD0, 0x7F, 0xE1, 0xAD, 0xF5,
+	0xA3, 0x83, 0xFF, 0x00, 0x20, 0xCB, 0x0E, 0xDF, 0xF4, 0xC0, 0x57, 0xB3, 0x7C, 0x04, 0xFF, 0x00,
+	0x82, 0x69, 0xFC, 0x54, 0xF8, 0x41, 0xF1, 0x93, 0xC3, 0xFF, 0x00, 0x13, 0xB5, 0x3F, 0x1E, 0xE8,
+	0x17, 0x96, 0xFA, 0x2D, 0xEB, 0x4F, 0x25, 0xAD, 0xBF, 0x9E, 0x1E, 0x51, 0xE5, 0xBA, 0x80, 0x0B,
+	0x26, 0x07, 0x2C, 0x0F, 0xE1, 0x5A, 0xFF, 0x00, 0xB5, 0x67, 0xFC, 0x13, 0xDB, 0xE2, 0x5F, 0xED,
+	0x07, 0xF1, 0xB2, 0xFB, 0xE2, 0x8E, 0x87, 0xE3, 0x5D, 0x0F, 0x4F, 0xB6, 0xBA, 0xB3, 0xB7, 0x85,
+	0x6D, 0xAE, 0xDA, 0x66, 0x75, 0x31, 0xA0, 0x52, 0x72, 0xB1, 0xE3, 0x9C, 0x7A, 0xD0, 0x07, 0xC0,
+	0xD5, 0xF6, 0x7F, 0xFC, 0x13, 0xF8, 0xEC, 0xFD, 0x8F, 0x3E, 0x2B, 0x06, 0xED, 0x25, 0xC6, 0x7F,
+	0xF0, 0x04, 0x56, 0x23, 0x7F, 0xC1, 0x22, 0xBE, 0x31, 0x6D, 0xC2, 0xFC, 0x50, 0xF0, 0xDF, 0xA7,
+	0xDD, 0xB8, 0xE3, 0xFF, 0x00, 0x1C, 0xAF, 0x75, 0xFD, 0x9B, 0xFF, 0x00, 0x64, 0x1F, 0x1F, 0xFC,
+	0x11, 0xF8, 0x1F, 0xE3, 0x0F, 0x85, 0x7A, 0xB7, 0x89, 0x34, 0x9B, 0xEB, 0x9F, 0x12, 0xBC, 0xA6,
+	0xDA, 0xE6, 0xDD, 0xA5, 0x11, 0xC3, 0xBE, 0xDC, 0x45, 0xF3, 0x6E, 0x5C, 0x9E, 0x99, 0xE2, 0x80,
+	0x3F, 0x35, 0x22, 0x04, 0x46, 0x80, 0x8F, 0xE1, 0xC7, 0xE8, 0x2A, 0x6B, 0x3F, 0xF8, 0xFA, 0x8F,
+	0xFE, 0xBA, 0x2F, 0xF3, 0xAF, 0xAB, 0xE2, 0xFF, 0x00, 0x82, 0x43, 0xFC, 0x63, 0x8E, 0x35, 0x8F,
+	0xFE, 0x16, 0x7F, 0x86, 0x70, 0xAB, 0x8E, 0x97, 0x3F, 0xFC, 0x45, 0x3E, 0x2F, 0xF8, 0x24, 0x77,
+	0xC6, 0x38, 0xE4, 0x59, 0x3F, 0xE1, 0x66, 0xF8, 0x65, 0xB6, 0xB6, 0x71, 0xB6, 0xE3, 0xFA, 0xC7,
+	0x40, 0x1A, 0x1F, 0xF0, 0x54, 0xC6, 0x03, 0xC0, 0x5F, 0x0A, 0x01, 0xFF, 0x00, 0xA0, 0x6D, 0xD8,
+	0xFC, 0xA2, 0xB3, 0xFF, 0x00, 0x1A, 0xF8, 0xE4, 0x1C, 0xF4, 0xAF, 0xD2, 0x3F, 0xDA, 0xF7, 0xF6,
+	0x35, 0xF1, 0xFF, 0x00, 0xED, 0x1D, 0xE1, 0xCF, 0x06, 0xE8, 0x9E, 0x1F, 0xF1, 0x36, 0x8F, 0xA7,
+	0x37, 0x86, 0x6D, 0x66, 0x8A, 0xE2, 0x4B, 0xC6, 0x95, 0x84, 0xC5, 0xD2, 0x15, 0x1B, 0x76, 0xA7,
+	0x00, 0x79, 0x47, 0xAF, 0xAD, 0x78, 0x80, 0xFF, 0x00, 0x82, 0x44, 0xFC, 0x63, 0x1F, 0xF3, 0x53,
+	0xFC, 0x33, 0xFF, 0x00, 0x7C, 0xDC, 0xFF, 0x00, 0xF1, 0x14, 0x01, 0x8B, 0xFF, 0x00, 0x04, 0xA3,
+	0x3F, 0xF1, 0x92, 0xF7, 0xE4, 0x7F, 0xD0, 0xA9, 0x75, 0xFF, 0x00, 0xA3, 0xAD, 0xEB, 0xC8, 0x7F,
+	0x6A, 0x20, 0xDF, 0xF0, 0xD2, 0x1E, 0x3B, 0x24, 0x7F, 0xCC, 0xD9, 0x7D, 0xFF, 0x00, 0xA3, 0x9A,
+	0xBE, 0xCF, 0xFD, 0x8E, 0x7F, 0x61, 0x1F, 0x88, 0xDF, 0xB3, 0x4F, 0xC5, 0x3B, 0x8F, 0x88, 0x1E,
+	0x20, 0xF1, 0x6E, 0x8B, 0xA9, 0x5B, 0xCD, 0xA3, 0xCD, 0x66, 0xB6, 0xF6, 0x6D, 0x32, 0xB8, 0x66,
+	0x92, 0x27, 0x0D, 0x96, 0x4C, 0x63, 0xF7, 0x7F, 0xAD, 0x71, 0x3F, 0x16, 0xFF, 0x00, 0xE0, 0x98,
+	0x1F, 0x15, 0xBE, 0x23, 0x7C, 0x54, 0xF1, 0x17, 0x8F, 0xB4, 0xFF, 0x00, 0x88, 0x3E, 0x1F, 0xB7,
+	0xB7, 0xD6, 0xB5, 0x8B, 0x8B, 0xD8, 0x6D, 0xE6, 0xF3, 0x8B, 0xC4, 0xB2, 0x48, 0x58, 0x29, 0x2B,
+	0x1F, 0x3C, 0x1F, 0xD2, 0x80, 0x3E, 0x2A, 0xAF, 0xB2, 0xF4, 0xEC, 0x1F, 0xF8, 0x24, 0x5B, 0x32,
+	0xFF, 0x00, 0xCF, 0xDC, 0xFF, 0x00, 0xFA, 0x71, 0x7A, 0xC8, 0x6F, 0xF8, 0x24, 0x5F, 0xC6, 0x25,
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+	0xED, 0x7F, 0x63, 0xCF, 0x1D, 0xDA, 0xFE, 0xC5, 0xFF, 0x00, 0xF0, 0xCC, 0x03, 0xC4, 0x9A, 0x4B,
+	0x6A, 0x06, 0x69, 0x1B, 0xFB, 0x4F, 0xCC, 0x97, 0xC9, 0x01, 0xAE, 0x9A, 0x6C, 0xED, 0xDB, 0x9E,
+	0x03, 0x01, 0xF8, 0x51, 0xBE, 0xE0, 0x7E, 0x74, 0x78, 0x77, 0xC5, 0x9E, 0x26, 0xF0, 0x9D, 0xF2,
+	0xDF, 0xF8, 0x67, 0xC4, 0x17, 0x96, 0x12, 0xAF, 0xF1, 0xDA, 0x5C, 0x32, 0xF6, 0x1E, 0x84, 0x64,
+	0x7B, 0x7F, 0xFA, 0x8F, 0xB7, 0x7C, 0x0B, 0xFD, 0xAB, 0x3E, 0x29, 0xEB, 0xDE, 0x37, 0xD1, 0x7C,
+	0x03, 0xE2, 0x87, 0xB1, 0xD4, 0x60, 0xD4, 0xF5, 0x28, 0x6D, 0x5A, 0xF1, 0xED, 0xC2, 0x5C, 0x45,
+	0xBD, 0x82, 0xEF, 0x06, 0x3D, 0xAA, 0x71, 0x9C, 0xF2, 0xB9, 0x38, 0xEA, 0x6B, 0xB6, 0x6F, 0xF8,
+	0x24, 0x6F, 0xC6, 0x23, 0xD7, 0xE2, 0x7F, 0x86, 0xBE, 0x9B, 0x6E, 0x3A, 0xFF, 0x00, 0xDF, 0x15,
+	0xB7, 0xF0, 0xD7, 0xFE, 0x09, 0x6B, 0xF1, 0x5F, 0xC0, 0xDF, 0x10, 0xB4, 0x4F, 0x19, 0x5E, 0x7C,
+	0x42, 0xF0, 0xF4, 0xF0, 0xE9, 0x7A, 0xA4, 0x37, 0x52, 0x43, 0x1F, 0x9F, 0xB9, 0xD5, 0x1C, 0x31,
+	0x51, 0x98, 0xF1, 0x92, 0x06, 0x3F, 0x1A, 0xF8, 0x9E, 0x22, 0xF0, 0xE7, 0x82, 0xF8, 0xB2, 0x9D,
+	0xB3, 0x3C, 0x14, 0x2A, 0x3F, 0xE6, 0xE5, 0x4A, 0x5F, 0x26, 0xAC, 0xD7, 0xDE, 0x76, 0x61, 0xF1,
+	0xD8, 0xCC, 0x2F, 0xF0, 0xE6, 0xD7, 0xCF, 0x4F, 0xB8, 0xE9, 0x7E, 0x3D, 0xFC, 0x5E, 0xF0, 0x2F,
+	0xEC, 0xF7, 0xF1, 0x12, 0x3F, 0x87, 0xDE, 0x37, 0xB8, 0xBC, 0x32, 0x4F, 0xA7, 0xC7, 0x79, 0x1D,
+	0xD5, 0xBD, 0x91, 0x78, 0xC2, 0x3B, 0x3A, 0x80, 0x46, 0x49, 0xC8, 0x28, 0x7B, 0x77, 0xFA, 0x56,
+	0x7E, 0x8B, 0xFB, 0x44, 0xFC, 0x14, 0xD7, 0x94, 0x7D, 0x8F, 0xE2, 0x25, 0x8A, 0x33, 0x7D, 0xD8,
+	0xEE, 0xA4, 0xF2, 0x98, 0xFE, 0x0C, 0x06, 0x2B, 0xA6, 0xFD, 0xB0, 0xFF, 0x00, 0x61, 0x1F, 0x89,
+	0x1F, 0xB4, 0xB7, 0xC5, 0x4B, 0x7F, 0x1F, 0xE8, 0x3E, 0x2F, 0xD1, 0x74, 0xDB, 0x78, 0x74, 0x78,
+	0x6C, 0xFE, 0xCF, 0x78, 0xD2, 0xB3, 0xEE, 0x47, 0x91, 0x8B, 0x65, 0x53, 0xA1, 0xDE, 0x3B, 0xF6,
+	0xAF, 0x28, 0x1F, 0xF0, 0x48, 0xDF, 0x8C, 0x7D, 0x47, 0xC5, 0x0F, 0x0D, 0x67, 0xFD, 0xD9, 0xFD,
+	0x3F, 0xEB, 0x9D, 0x7E, 0x13, 0x9D, 0xFD, 0x12, 0x7C, 0x3D, 0xCC, 0x64, 0xE7, 0x84, 0xA9, 0x52,
+	0x83, 0x7D, 0x13, 0x4D, 0x7C, 0xAE, 0x9B, 0xFC, 0x4F, 0x63, 0x0F, 0xC4, 0xF8, 0xEA, 0x6A, 0xD3,
+	0x4A, 0x5E, 0xA6, 0x17, 0xFC, 0x14, 0x6E, 0xE6, 0xDB, 0xC6, 0x7F, 0xB0, 0xBF, 0xC4, 0x0F, 0xF8,
+	0x44, 0x6E, 0x63, 0xD5, 0x9A, 0x3D, 0x36, 0x20, 0xEB, 0xA6, 0xB0, 0xB8, 0x60, 0x4C, 0xE9, 0x81,
+	0x84, 0xC9, 0xCF, 0x07, 0xF2, 0xAF, 0xC4, 0x59, 0xAC, 0x6E, 0xE2, 0x93, 0x6C, 0x96, 0xB3, 0x2F,
+	0xFB, 0xD1, 0x9A, 0xFE, 0x92, 0xBF, 0x63, 0xAF, 0xD8, 0xE3, 0xC6, 0x3F, 0xB3, 0x66, 0x9D, 0xE2,
+	0x8B, 0x0F, 0x15, 0x6B, 0x9A, 0x3E, 0xAC, 0x35, 0xEF, 0xB3, 0xF9, 0x2B, 0x6B, 0xE6, 0x62, 0x3F,
+	0x2C, 0x48, 0x32, 0xC1, 0xD4, 0x03, 0x9D, 0xE3, 0xF2, 0xAF, 0x02, 0x8B, 0xFE, 0x08, 0xF1, 0xF1,
+	0x48, 0x42, 0x91, 0x4B, 0xE3, 0xDF, 0x09, 0x92, 0xAA, 0x07, 0xFA, 0x99, 0xCF, 0xE3, 0xFE, 0xAE,
+	0xBE, 0xCF, 0xC3, 0xFF, 0x00, 0x04, 0xF0, 0xFC, 0x03, 0x95, 0xCF, 0x05, 0x47, 0x14, 0xEA, 0x27,
+	0x2E, 0x6B, 0xB8, 0xD9, 0xAF, 0x2D, 0x19, 0xFB, 0xA7, 0x86, 0x7F, 0x48, 0x49, 0x70, 0x0E, 0x02,
+	0xAE, 0x16, 0x78, 0x2F, 0x68, 0xAA, 0x4B, 0x9A, 0xEA, 0x56, 0xB5, 0x95, 0xAD, 0xB1, 0xF8, 0x63,
+	0x1D, 0x95, 0xD3, 0x33, 0x08, 0xAD, 0xA4, 0x63, 0x8E, 0xD1, 0x9F, 0xF0, 0xAF, 0xD6, 0xFF, 0x00,
+	0xF8, 0x22, 0xC3, 0xA7, 0x86, 0x7F, 0x63, 0xFB, 0xCB, 0xBF, 0x14, 0x4A, 0x34, 0xD4, 0x93, 0xC5,
+	0xD7, 0x3E, 0x5B, 0x6A, 0x07, 0xC9, 0x0E, 0x0C, 0x50, 0xE0, 0xA9, 0x7C, 0x67, 0x3E, 0xD5, 0xEC,
+	0x5F, 0xF0, 0xE7, 0x7F, 0x89, 0xEB, 0xF7, 0x7C, 0x79, 0xE1, 0x2C, 0xFF, 0x00, 0xD7, 0xAC, 0xDF,
+	0xFC, 0x45, 0x7B, 0x97, 0xC7, 0xCF, 0xD8, 0xAF, 0xC6, 0x5F, 0x16, 0x7E, 0x00, 0x78, 0x2F, 0xE1,
+	0x0E, 0x85, 0xAE, 0xE8, 0xBA, 0x7D, 0xD7, 0x86, 0x6D, 0xED, 0xA3, 0xBC, 0xBB, 0x9B, 0xCC, 0xF2,
+	0xEE, 0x1A, 0x3B, 0x65, 0x89, 0x9D, 0x42, 0xA6, 0x72, 0x48, 0xCF, 0x23, 0xA5, 0x75, 0xF1, 0xE7,
+	0x83, 0xB4, 0x78, 0xE3, 0x22, 0x79, 0x6D, 0x5C, 0x53, 0x82, 0x6E, 0x2E, 0xEA, 0x29, 0xBD, 0x3A,
+	0x6A, 0xD7, 0xEA, 0x76, 0x78, 0x8D, 0xF4, 0x8E, 0x7C, 0x75, 0x92, 0xC7, 0x2F, 0x8E, 0x07, 0xD9,
+	0xA5, 0x25, 0x2B, 0xF3, 0xDF, 0x6B, 0xE9, 0x6B, 0x75, 0xBF, 0x73, 0x8B, 0xD6, 0x3E, 0x3D, 0x7C,
+	0x1B, 0xD0, 0x81, 0xFE, 0xD1, 0xF8, 0x87, 0xA6, 0xE5, 0x5B, 0x0D, 0x1C, 0x77, 0x01, 0x89, 0xFC,
+	0x17, 0x39, 0xA6, 0xFC, 0x25, 0xF8, 0xEB, 0xF0, 0xE7, 0xE3, 0x3F, 0xC4, 0xCB, 0x5F, 0x86, 0x5E,
+	0x06, 0xBE, 0xB8, 0x9E, 0xEE, 0xEA, 0x19, 0x24, 0x4B, 0xA9, 0x2C, 0xDA, 0x38, 0x54, 0x22, 0xE4,
+	0x8C, 0x9C, 0x37, 0xE4, 0x2B, 0x8B, 0xFF, 0x00, 0x87, 0x45, 0xFC, 0x63, 0x0D, 0x91, 0xF1, 0x33,
+	0xC3, 0x3F, 0x95, 0xC7, 0xFF, 0x00, 0x1B, 0xAF, 0x44, 0xFD, 0x96, 0xBF, 0xE0, 0x9E, 0x7F, 0x13,
+	0x7E, 0x00, 0x7C, 0x65, 0xD3, 0xFE, 0x26, 0xEB, 0x9E, 0x37, 0xD0, 0xF5, 0x0B, 0x5B, 0x3B, 0x79,
+	0xA3, 0x6B, 0x5B, 0x7F, 0x38, 0x48, 0x4B, 0xA6, 0x01, 0x05, 0x93, 0x1C, 0x1A, 0xFC, 0xE7, 0x26,
+	0xFA, 0x23, 0x70, 0x0E, 0x06, 0x4A, 0x58, 0xBA, 0xB5, 0x2A, 0xF9, 0x5D, 0x24, 0xFE, 0xED, 0x7E,
+	0xE6, 0x8F, 0xC0, 0x6B, 0x71, 0x3E, 0x36, 0xA7, 0xC2, 0x92, 0xFC, 0x4F, 0x1F, 0xFD, 0xA6, 0x7F,
+	0x69, 0xCF, 0x88, 0x5F, 0x0C, 0xBE, 0x29, 0xEB, 0x9F, 0x0B, 0x3C, 0x23, 0x63, 0x63, 0x6E, 0xBA,
+	0x3D, 0xD7, 0xD9, 0xFF, 0x00, 0xB4, 0xA5, 0x87, 0xCD, 0x9A, 0x53, 0xB5, 0x5B, 0x70, 0x07, 0x6A,
+	0x27, 0x2D, 0xD0, 0x87, 0xCE, 0x3A, 0xD7, 0x80, 0xF8, 0xBF, 0xE2, 0x1F, 0x8E, 0x7C, 0x79, 0x75,
+	0xF6, 0xCF, 0x17, 0xF8, 0xB2, 0xF3, 0x50, 0x7C, 0x93, 0xFB, 0xE9, 0x89, 0x45, 0x1F, 0xEC, 0xA8,
+	0xC2, 0xA8, 0xF6, 0x00, 0x0F, 0x6A, 0xFB, 0x27, 0xE3, 0xEF, 0xFC, 0x13, 0x57, 0xE2, 0x87, 0xC6,
+	0x0F, 0x8C, 0x7A, 0xFF, 0x00, 0xC4, 0xCD, 0x2F, 0xC7, 0xBA, 0x0D, 0x9D, 0xBE, 0xAD, 0x7B, 0xE7,
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+	0x7F, 0xE5, 0x8E, 0xAC, 0x7B, 0x7F, 0x71, 0x6B, 0xE2, 0xA0, 0x1F, 0x19, 0x23, 0xB0, 0xAF, 0xD2,
+	0xCF, 0x87, 0x1F, 0xB2, 0x1F, 0x8E, 0xFC, 0x13, 0xFB, 0x21, 0x78, 0x8B, 0xF6, 0x71, 0xBC, 0xF1,
+	0x36, 0x95, 0x36, 0xA1, 0xAD, 0x43, 0x79, 0x1C, 0x7A, 0x9C, 0x2D, 0x28, 0x8A, 0x31, 0x30, 0x00,
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+	0xA7, 0x1D, 0xB8, 0xAF, 0xD2, 0x7F, 0x89, 0x1F, 0xB1, 0xE7, 0x8F, 0x3C, 0x6F, 0xFB, 0x21, 0xF8,
+	0x7F, 0xF6, 0x6F, 0xB1, 0xF1, 0x1E, 0x93, 0x6F, 0x7D, 0xA3, 0xFD, 0x97, 0xCE, 0xD4, 0x99, 0xE5,
+	0xF2, 0x64, 0x11, 0x16, 0x3C, 0x00, 0x9B, 0xBB, 0x8A, 0xF0, 0xC3, 0xFF, 0x00, 0x04, 0x8B, 0xF8,
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+	0x3B, 0x49, 0xEB, 0x40, 0x1F, 0x05, 0x57, 0xDA, 0x9F, 0xB0, 0x1B, 0x85, 0xFD, 0x8B, 0x7E, 0x2C,
+	0x0C, 0xFF, 0x00, 0xCB, 0x1D, 0x43, 0xFF, 0x00, 0x4D, 0xBF, 0xFD, 0x6A, 0xE7, 0xCF, 0xFC, 0x12,
+	0x2B, 0xE3, 0x16, 0x31, 0xFF, 0x00, 0x0B, 0x3F, 0xC3, 0x5E, 0x9D, 0x2E, 0x78, 0xFF, 0x00, 0xC7,
+	0x2B, 0xDE, 0x3F, 0x66, 0xCF, 0xD9, 0x0F, 0xC7, 0xBF, 0x04, 0xBE, 0x04, 0x78, 0xC3, 0xE1, 0x2E,
+	0xAD, 0xE2, 0x4D, 0x2A, 0xF2, 0xEB, 0xC4, 0x8B, 0x72, 0x2D, 0x6E, 0xED, 0x5E, 0x51, 0x1C, 0x1E,
+	0x65, 0xB7, 0x92, 0x0B, 0x06, 0x5C, 0x9E, 0x70, 0xDC, 0x50, 0x07, 0xE6, 0x9A, 0x10, 0x51, 0x4E,
+	0x7F, 0x87, 0x34, 0x57, 0xD6, 0x89, 0xFF, 0x00, 0x04, 0x8B, 0xF8, 0xC4, 0xAA, 0xA8, 0x3E, 0x28,
+	0x78, 0x6F, 0x0A, 0x3F, 0xBB, 0x71, 0xFF, 0x00, 0xC4, 0x7A, 0xE7, 0xF3, 0xA1, 0xBF, 0xE0, 0x91,
+	0x7F, 0x18, 0xBA, 0x7F, 0xC2, 0xCF, 0xF0, 0xD7, 0xDD, 0x23, 0xA5, 0xCF, 0x07, 0x1C, 0x1F, 0xB9,
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+	0xBA, 0x2F, 0xEC, 0xE1, 0x0F, 0x8B, 0xB4, 0x94, 0xD4, 0xB4, 0xBD, 0x69, 0xAF, 0x24, 0xD4, 0x19,
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+	0x12, 0xB7, 0xFF, 0x00, 0xD1, 0x8B, 0x5F, 0x47, 0x7F, 0xC1, 0x55, 0x3F, 0xE4, 0xAE, 0xF8, 0x5B,
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+	0x2A, 0xAC, 0x09, 0x03, 0xE4, 0xEB, 0xC5, 0x7A, 0x97, 0xED, 0x8F, 0xFB, 0x0B, 0xF8, 0xFF, 0x00,
+	0xF6, 0x90, 0xF1, 0xB6, 0x8B, 0xE2, 0xCF, 0x0B, 0x78, 0xBB, 0x49, 0xD3, 0xD3, 0x4B, 0xD1, 0x56,
+	0xCD, 0xA1, 0xBE, 0x12, 0xEE, 0x69, 0x15, 0xD9, 0x83, 0x0D, 0x80, 0xF1, 0xCF, 0xB1, 0xA0, 0x0F,
+	0xCE, 0xDE, 0xFF, 0x00, 0x8D, 0x7D, 0x01, 0xFF, 0x00, 0x04, 0xCC, 0x38, 0xFD, 0xAB, 0xF4, 0x92,
+	0x7F, 0xE8, 0x1B, 0x7D, 0xFF, 0x00, 0xA2, 0x4D, 0x76, 0x9F, 0xF0, 0xE8, 0x8F, 0x8C, 0x0A, 0x30,
+	0xBF, 0x14, 0x3C, 0x37, 0x81, 0xF7, 0x7F, 0xE3, 0xE7, 0xFF, 0x00, 0x88, 0xAF, 0x48, 0xFD, 0x94,
+	0x3F, 0xE0, 0x9F, 0x7F, 0x12, 0x7F, 0x67, 0xCF, 0x8C, 0x96, 0xBF, 0x13, 0x35, 0xFF, 0x00, 0x1A,
+	0xE8, 0x9A, 0x85, 0xB5, 0xBD, 0x9C, 0xF1, 0x1B, 0x7B, 0x2F, 0x38, 0x3B, 0x17, 0x8C, 0xA8, 0x3F,
+	0x32, 0x81, 0x81, 0x9F, 0x5E, 0xD4, 0x01, 0xF5, 0xC0, 0x3C, 0x51, 0x40, 0xA2, 0x80, 0x3F, 0xFF,
+	0xD9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46,
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+	0xFF, 0xDB, 0x00, 0x43, 0x00, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x02,
+	0x02, 0x02, 0x02, 0x02, 0x04, 0x03, 0x02, 0x02, 0x02, 0x02, 0x05, 0x04, 0x04, 0x03, 0x04, 0x06,
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+	0x06, 0x08, 0x0B, 0x08, 0x09, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x06, 0x08, 0x0B, 0x0C, 0x0B, 0x0A,
+	0x0C, 0x09, 0x0A, 0x0A, 0x0A, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+	0x05, 0x03, 0x03, 0x05, 0x0A, 0x07, 0x06, 0x07, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x01,
+	0x10, 0x01, 0xE0, 0x03, 0x01, 0x22, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00,
+	0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4,
+	0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00,
+	0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13,
+	0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15,
+	0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25,
+	0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46,
+	0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66,
+	0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86,
+	0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4,
+	0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2,
+	0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9,
+	0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5,
+	0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00, 0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+	0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04,
+	0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00, 0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11,
+	0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, 0x13, 0x22, 0x32, 0x81, 0x08,
+	0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A,
+	0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35,
+	0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55,
+	0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75,
+	0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93,
+	0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA,
+	0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8,
+	0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6,
+	0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00,
+	0x0C, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3F, 0x00, 0xFD, 0xFC, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
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+	0xA0, 0x06, 0x80, 0x08, 0xC9, 0xA4, 0x65, 0xE3, 0x8A, 0x7D, 0x14, 0x00, 0x99, 0x3E, 0x94, 0x64,
+	0xFA, 0x52, 0xD1, 0x40, 0x0C, 0xDB, 0xC6, 0x54, 0x7E, 0x94, 0xA5, 0x33, 0xC1, 0xA7, 0x51, 0x40,
+	0x0D, 0xC6, 0x47, 0x06, 0x8E, 0x33, 0x82, 0x29, 0xD4, 0x8E, 0x0B, 0x0C, 0x0A, 0x00, 0x5A, 0x28,
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+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x05, 0x39, 0x19, 0xA2, 0x81, 0xD2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
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+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x9B, 0x2C, 0x89, 0x0C, 0x6D, 0x34, 0xAD, 0xB5,
+	0x55, 0x49, 0x66, 0xF4, 0x14, 0x00, 0xEA, 0x2B, 0xE5, 0x5F, 0x8D, 0x7F, 0xF0, 0x59, 0x4F, 0xD8,
+	0x6B, 0xE1, 0x26, 0xAD, 0x71, 0xE1, 0x2F, 0x0B, 0x78, 0xF2, 0xFB, 0xE2, 0x47, 0x88, 0xED, 0xE4,
+	0x78, 0x9F, 0xC3, 0xBF, 0x0C, 0x74, 0xFF, 0x00, 0xED, 0x89, 0x56, 0x65, 0xFF, 0x00, 0x96, 0x72,
+	0x4E, 0x8C, 0x2D, 0x60, 0x6C, 0xF0, 0x56, 0x59, 0x90, 0x83, 0xD4, 0x0A, 0xF0, 0xFF, 0x00, 0x17,
+	0xFF, 0x00, 0xC1, 0x60, 0xFF, 0x00, 0x6C, 0xAF, 0x1A, 0x45, 0x24, 0x9F, 0x04, 0x3F, 0x62, 0xFF,
+	0x00, 0x0F, 0xF8, 0x4F, 0x4F, 0xC3, 0x18, 0x3C, 0x41, 0xF1, 0x43, 0xC5, 0xCC, 0xDD, 0xB8, 0x0D,
+	0x69, 0x6A, 0x88, 0xAA, 0xDE, 0xDF, 0x69, 0x23, 0xB6, 0x47, 0x5A, 0x00, 0xFD, 0x1A, 0xA2, 0xBF,
+	0x20, 0xFC, 0x6D, 0xFB, 0x78, 0xFE, 0xDF, 0x1E, 0x27, 0x76, 0x5F, 0x16, 0xFF, 0x00, 0xC1, 0x44,
+	0xBC, 0x0B, 0xE1, 0x15, 0x6C, 0xF9, 0x96, 0x7F, 0x0D, 0xFC, 0x23, 0x67, 0x3B, 0x10, 0x7A, 0xA0,
+	0x7B, 0x91, 0x7C, 0xE0, 0x8E, 0x99, 0x1B, 0x48, 0x3D, 0x08, 0x35, 0xE6, 0xBE, 0x2C, 0xF8, 0xEA,
+	0x7C, 0x4A, 0x59, 0xBE, 0x24, 0x7F, 0xC1, 0x45, 0xBE, 0x39, 0xEB, 0x68, 0xCA, 0x44, 0x91, 0xE8,
+	0x7E, 0x24, 0xBD, 0xD2, 0xE3, 0x91, 0xBF, 0xBB, 0xB6, 0xD0, 0xDA, 0xAE, 0x0F, 0x4E, 0xDF, 0x51,
+	0xD6, 0xA9, 0x45, 0xB2, 0x25, 0x3E, 0x53, 0xF7, 0x15, 0xC8, 0x08, 0xC4, 0x9E, 0xD5, 0x95, 0xA9,
+	0x78, 0xB7, 0xC2, 0x9A, 0x48, 0x23, 0x54, 0xF1, 0x5E, 0x9F, 0x6A, 0xC3, 0xAF, 0xDA, 0xAF, 0xA3,
+	0x8F, 0x1F, 0x99, 0x15, 0xF8, 0x33, 0xAA, 0x6B, 0x7F, 0xB2, 0x5E, 0xA8, 0x1B, 0xFE, 0x12, 0x93,
+	0xF1, 0x47, 0xC5, 0x99, 0xE1, 0xDB, 0xC4, 0x3E, 0x2C, 0xB8, 0xBB, 0x2E, 0x3B, 0x83, 0xF6, 0x8B,
+	0xE9, 0x33, 0x9F, 0x73, 0x59, 0x2C, 0x9F, 0xB0, 0x34, 0x4E, 0xB2, 0xC5, 0xFB, 0x26, 0x5B, 0xDD,
+	0x32, 0x9C, 0xA9, 0xD5, 0x2E, 0xAD, 0xF7, 0x67, 0xFE, 0xF9, 0x93, 0xF9, 0xD5, 0x46, 0x99, 0x3E,
+	0xD4, 0xFD, 0xDA, 0xD5, 0x7F, 0x68, 0xEF, 0xD9, 0xE3, 0xC3, 0xEE, 0x20, 0xF1, 0x0F, 0xC7, 0x8F,
+	0x07, 0xD9, 0xC9, 0x9C, 0x7F, 0xA5, 0x78, 0x92, 0xDA, 0x3C, 0x7E, 0x72, 0x57, 0x37, 0xA8, 0x7E,
+	0xDD, 0xFF, 0x00, 0xB0, 0xEE, 0x95, 0x3C, 0xB0, 0xDF, 0xFE, 0xD8, 0x7F, 0x0A, 0xAD, 0xDE, 0x15,
+	0x26, 0xE1, 0x6E, 0x3E, 0x21, 0x69, 0xD1, 0xB2, 0xA8, 0xEA, 0x79, 0x9A, 0xBF, 0x14, 0xE2, 0xF1,
+	0xBF, 0xEC, 0x81, 0xA7, 0x0D, 0x9A, 0x77, 0xEC, 0x63, 0xE1, 0xF5, 0x5F, 0xEF, 0x7D, 0xAA, 0x3E,
+	0x3F, 0x2B, 0x7A, 0xB3, 0x0F, 0xC6, 0x9F, 0xD9, 0xE7, 0x4C, 0x18, 0xD2, 0x7F, 0x64, 0x3F, 0x0F,
+	0xAE, 0x3E, 0xEB, 0x35, 0xD7, 0x00, 0xFF, 0x00, 0xE0, 0x38, 0xFE, 0x62, 0xAB, 0xD9, 0x07, 0xB5,
+	0x3F, 0x64, 0x1F, 0xFE, 0x0A, 0x43, 0xFF, 0x00, 0x04, 0xF3, 0x07, 0x03, 0xF6, 0xE7, 0xF8, 0x45,
+	0xFF, 0x00, 0x87, 0x23, 0x4D, 0xFF, 0x00, 0xE3, 0xF5, 0x52, 0xEF, 0xFE, 0x0A, 0x79, 0xFF, 0x00,
+	0x04, 0xDD, 0xB1, 0x70, 0x97, 0x9F, 0xB7, 0x4F, 0xC2, 0x25, 0x7C, 0xF1, 0x9F, 0x88, 0x1A, 0x7F,
+	0x5F, 0xFB, 0xFB, 0x5F, 0x8F, 0xAD, 0xFB, 0x43, 0xFC, 0x27, 0x55, 0xDC, 0x9F, 0xB2, 0xB7, 0x85,
+	0x55, 0x87, 0x2A, 0xDF, 0x6A, 0xE9, 0xF9, 0x20, 0xFE, 0x74, 0xB0, 0xFE, 0xD2, 0x9F, 0x0E, 0x54,
+	0x6E, 0x4F, 0xD9, 0x9F, 0xC2, 0xBB, 0x87, 0x2B, 0xFE, 0x93, 0x21, 0xFD, 0x28, 0xF6, 0x42, 0xF6,
+	0xA7, 0xEB, 0xEF, 0xFC, 0x3D, 0x2F, 0xFE, 0x09, 0xB9, 0xFF, 0x00, 0x47, 0xE1, 0xF0, 0x8B, 0xFF,
+	0x00, 0x0B, 0xEB, 0x1F, 0xFE, 0x3B, 0x47, 0xFC, 0x3D, 0x2B, 0xFE, 0x09, 0xB9, 0xFF, 0x00, 0x47,
+	0xE1, 0xF0, 0x8B, 0xFF, 0x00, 0x0B, 0xEB, 0x1F, 0xFE, 0x3B, 0x5F, 0x90, 0xCD, 0xFB, 0x4F, 0xF8,
+	0x23, 0x69, 0xC7, 0xEC, 0xCF, 0xE1, 0x5F, 0xFC, 0x89, 0x51, 0x7F, 0xC3, 0x50, 0xF8, 0x2F, 0xFE,
+	0x8D, 0x9B, 0xC2, 0xBF, 0xF7, 0xD4, 0x83, 0xFC, 0x7F, 0x91, 0xA3, 0xD9, 0x07, 0xB5, 0x3F, 0x60,
+	0x62, 0xFF, 0x00, 0x82, 0xA1, 0xFF, 0x00, 0xC1, 0x38, 0x27, 0x95, 0x60, 0x4F, 0xDB, 0xBB, 0xE1,
+	0x16, 0xE7, 0x60, 0xAB, 0xFF, 0x00, 0x17, 0x02, 0xC0, 0x75, 0xFF, 0x00, 0xB6, 0xB5, 0x74, 0x7F,
+	0xC1, 0x47, 0xFF, 0x00, 0xE0, 0x9E, 0x24, 0xE3, 0xFE, 0x1B, 0x9F, 0xE1, 0x1F, 0xFE, 0x1C, 0x9D,
+	0x37, 0xFF, 0x00, 0x8F, 0xD7, 0xE3, 0x8B, 0x7E, 0xD4, 0x3E, 0x06, 0x71, 0xB1, 0xFF, 0x00, 0x66,
+	0x5F, 0x0A, 0xB2, 0x9E, 0x19, 0x7E, 0xD5, 0x27, 0x3F, 0xF9, 0x0E, 0xA3, 0x5F, 0xDA, 0x4B, 0xE1,
+	0xA1, 0x38, 0x7F, 0xD9, 0x4F, 0xC2, 0xBB, 0x7B, 0xFF, 0x00, 0xA5, 0x49, 0xFD, 0x63, 0xA3, 0xD9,
+	0x0F, 0xDA, 0x9F, 0xB2, 0xDA, 0x77, 0xFC, 0x14, 0x3B, 0xF6, 0x08, 0xD5, 0xEE, 0x1E, 0x0D, 0x37,
+	0xF6, 0xDE, 0xF8, 0x43, 0x26, 0xCE, 0xCB, 0xF1, 0x23, 0x4D, 0x24, 0xFF, 0x00, 0xE4, 0xC5, 0x6B,
+	0x69, 0x9F, 0xB6, 0xCF, 0xEC, 0x61, 0xAD, 0xCC, 0xD0, 0x68, 0x7F, 0xB5, 0xB7, 0xC3, 0x1B, 0xB9,
+	0x17, 0xFD, 0x67, 0xD9, 0xBC, 0x79, 0xA7, 0xC9, 0x8F, 0xCA, 0x7A, 0xFC, 0x51, 0x9F, 0xF6, 0x88,
+	0xF8, 0x41, 0x30, 0xF2, 0xA6, 0xFD, 0x94, 0xBC, 0x2A, 0xC8, 0xDC, 0x32, 0xFD, 0xAB, 0xA8, 0x3F,
+	0xF6, 0xC8, 0xFF, 0x00, 0x2A, 0xA5, 0x37, 0xC6, 0x8F, 0x80, 0x04, 0xE0, 0xFE, 0xC7, 0xDE, 0x17,
+	0x61, 0xDD, 0x56, 0xEB, 0x93, 0xF9, 0xDB, 0xD1, 0xEC, 0x83, 0xDA, 0x9F, 0xBB, 0x16, 0x1F, 0xB4,
+	0x67, 0xEC, 0xF5, 0xAC, 0x28, 0xFE, 0xC7, 0xF8, 0xEF, 0xE0, 0xDB, 0xBD, 0xDC, 0x2F, 0xD9, 0x7C,
+	0x53, 0x68, 0xF9, 0xFF, 0x00, 0xBE, 0x64, 0x35, 0xBB, 0xA5, 0xF8, 0xEB, 0xC1, 0x3A, 0xC0, 0x55,
+	0xD1, 0xBC, 0x5D, 0xA6, 0xDE, 0x33, 0x36, 0x11, 0x6D, 0x75, 0x04, 0x97, 0x24, 0xF4, 0x1C, 0x1A,
+	0xFC, 0x01, 0x9B, 0xC7, 0xDF, 0xB2, 0xB6, 0xA6, 0x73, 0xA9, 0x7E, 0xC5, 0xDE, 0x1F, 0xDC, 0x7F,
+	0xE9, 0xEA, 0x2F, 0xEB, 0x6F, 0x55, 0xDF, 0xFE, 0x18, 0x87, 0x50, 0x91, 0x5F, 0x52, 0xFD, 0x8D,
+	0x2C, 0x22, 0x6C, 0xFF, 0x00, 0xAC, 0xB2, 0xBA, 0xB7, 0xCA, 0x7B, 0x8F, 0xF4, 0x71, 0xC8, 0xFA,
+	0xD1, 0xEC, 0x85, 0xED, 0x4F, 0xE8, 0x72, 0x27, 0x56, 0xE7, 0x15, 0x25, 0x7F, 0x3D, 0xF6, 0x77,
+	0xFF, 0x00, 0xB1, 0x8E, 0x96, 0x33, 0xA5, 0x7C, 0x36, 0xF1, 0xB6, 0x8F, 0xB7, 0x95, 0x3A, 0x2E,
+	0xB8, 0xD0, 0x14, 0xF7, 0x53, 0x1C, 0xF1, 0x60, 0x8E, 0xC7, 0x8C, 0x1A, 0xDF, 0xD0, 0xBE, 0x2B,
+	0xFC, 0x3D, 0xD2, 0x5D, 0x1F, 0xC0, 0x9F, 0xB5, 0x27, 0xED, 0x19, 0xE1, 0x75, 0x56, 0x05, 0x21,
+	0xB0, 0xF8, 0x8D, 0xA8, 0xF9, 0x60, 0x83, 0xC6, 0x51, 0x6F, 0xD8, 0x30, 0xFF, 0x00, 0x64, 0xA9,
+	0x07, 0xA6, 0x0F, 0x4A, 0xCE, 0x54, 0x87, 0xED, 0x4F, 0xDF, 0x1A, 0x2B, 0xF1, 0x27, 0xC3, 0x9F,
+	0xB6, 0x57, 0xED, 0x0D, 0xE1, 0xB6, 0x48, 0xFC, 0x03, 0xFF, 0x00, 0x05, 0x4C, 0xF8, 0x81, 0xA7,
+	0xE1, 0x87, 0x97, 0x07, 0x8B, 0xBC, 0x37, 0x6D, 0xAA, 0x6E, 0x3D, 0x83, 0x35, 0xD5, 0x84, 0xCD,
+	0x8F, 0x5F, 0x9C, 0x1C, 0x77, 0x1D, 0x6B, 0xD5, 0x7C, 0x09, 0xFF, 0x00, 0x05, 0x3B, 0xFF, 0x00,
+	0x82, 0x89, 0x78, 0x7F, 0xCB, 0x83, 0x4E, 0xF8, 0xE1, 0xF0, 0x37, 0xE2, 0x3A, 0xF9, 0x8B, 0x9B,
+	0x5D, 0x53, 0x48, 0x93, 0x4C, 0xBE, 0x90, 0x67, 0xBB, 0x5B, 0x5D, 0x2A, 0xA1, 0x3D, 0x37, 0x18,
+	0x08, 0x1D, 0x76, 0x9C, 0x62, 0xA7, 0x97, 0x94, 0xB8, 0xCB, 0x98, 0xFD, 0x61, 0xA2, 0xBF, 0x3D,
+	0xFC, 0x2F, 0xFF, 0x00, 0x05, 0xB8, 0xF8, 0x97, 0xE1, 0x15, 0x5B, 0x6F, 0xDA, 0x4F, 0xF6, 0x10,
+	0xF1, 0x45, 0x9F, 0xCC, 0x01, 0xD5, 0x3E, 0x1C, 0xEB, 0x96, 0xFA, 0xDC, 0x05, 0x73, 0xCC, 0x9E,
+	0x54, 0xEB, 0x6B, 0x30, 0x50, 0x39, 0xDA, 0x8B, 0x23, 0x11, 0xD3, 0x27, 0x15, 0xF4, 0x97, 0xEC,
+	0xEF, 0xFF, 0x00, 0x05, 0x2B, 0xFD, 0x8A, 0x3F, 0x6A, 0x0D, 0x62, 0x3F, 0x0A, 0xFC, 0x2D, 0xF8,
+	0xF3, 0xA3, 0x8F, 0x10, 0x4D, 0xB4, 0x27, 0x84, 0xF5, 0xE3, 0x26, 0x97, 0xAB, 0xEE, 0x3D, 0x57,
+	0xEC, 0x77, 0x8B, 0x1C, 0xAF, 0x83, 0xC6, 0x63, 0x0E, 0xA4, 0xF4, 0x34, 0x14, 0x7B, 0xB5, 0x14,
+	0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14,
+	0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14,
+	0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14,
+	0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14,
+	0x57, 0x94, 0xFE, 0xDB, 0x1F, 0xB5, 0xB7, 0xC3, 0xEF, 0xD8, 0x7F, 0xF6, 0x6B, 0xF1, 0x37, 0xED,
+	0x23, 0xF1, 0x26, 0x29, 0x6E, 0x2C, 0x74, 0x1B, 0x2C, 0xDA, 0xE9, 0xB6, 0xB2, 0x2A, 0xCF, 0xA8,
+	0xDE, 0x48, 0xC2, 0x3B, 0x7B, 0x48, 0xCB, 0x0C, 0x06, 0x96, 0x57, 0x44, 0xDC, 0x78, 0x5D, 0xD9,
+	0x39, 0x00, 0xD0, 0x07, 0x1F, 0xFB, 0x77, 0xFF, 0x00, 0xC1, 0x46, 0xBE, 0x0B, 0xFE, 0xC3, 0xBE,
+	0x18, 0xD3, 0x2D, 0x75, 0xB4, 0xBA, 0xF1, 0x27, 0x8E, 0x3C, 0x51, 0xB9, 0x3C, 0x13, 0xF0, 0xFF,
+	0x00, 0x43, 0x65, 0xFB, 0x7E, 0xB4, 0xEB, 0xD5, 0xF2, 0x43, 0x2D, 0xBD, 0xB2, 0x9E, 0x5E, 0xE1,
+	0xC1, 0x55, 0x5C, 0xED, 0x0E, 0xD8, 0x5A, 0xFC, 0xB1, 0xFD, 0xA8, 0xBF, 0x6A, 0xFF, 0x00, 0x8B,
+	0xDF, 0xB4, 0xBD, 0xDC, 0xD7, 0x5F, 0xB6, 0x7F, 0xC4, 0xC6, 0x6D, 0x2E, 0x69, 0x37, 0xDB, 0xFC,
+	0x18, 0xF0, 0x3D, 0xE1, 0xB4, 0xD0, 0xED, 0x46, 0x7A, 0x5F, 0xCC, 0x33, 0x25, 0xFC, 0xDB, 0x78,
+	0x61, 0x28, 0x91, 0x0F, 0x20, 0x42, 0x80, 0xE6, 0xBC, 0x5B, 0xC6, 0x5F, 0x18, 0xFE, 0x2C, 0x78,
+	0x9B, 0xC6, 0x5A, 0xC7, 0xC7, 0xAF, 0x8C, 0xFE, 0x23, 0x83, 0x56, 0xF8, 0xB9, 0xE3, 0xE8, 0x56,
+	0xE7, 0x5E, 0xD4, 0xBC, 0xB6, 0x68, 0xFC, 0x3D, 0xA7, 0x30, 0x63, 0x6F, 0xA6, 0x58, 0xA3, 0xE4,
+	0x41, 0x00, 0x8E, 0x41, 0xF2, 0x0C, 0x90, 0xBB, 0x99, 0xB7, 0x4B, 0xB9, 0xC7, 0x9F, 0x5D, 0xEA,
+	0x97, 0x37, 0x17, 0x72, 0x5F, 0x5C, 0x5E, 0xFD, 0xA6, 0x79, 0x01, 0xF3, 0x1A, 0xB6, 0xA7, 0x1E,
+	0x63, 0x1A, 0x93, 0xE5, 0x3D, 0x58, 0x7E, 0xD1, 0x5A, 0xB6, 0x97, 0xA5, 0xFF, 0x00, 0x62, 0xFC,
+	0x2F, 0xD2, 0x2C, 0x7C, 0x2B, 0xA3, 0xC0, 0xA6, 0x1B, 0x78, 0xF4, 0x5B, 0x75, 0x89, 0x94, 0x74,
+	0xE6, 0x46, 0x67, 0x97, 0xF1, 0x4D, 0x83, 0xD1, 0x6B, 0x8F, 0xF1, 0x0F, 0xC4, 0x2D, 0x67, 0xC4,
+	0x13, 0x79, 0xFE, 0x20, 0xD6, 0xAE, 0x35, 0x29, 0x3A, 0xAC, 0xD7, 0x37, 0x0F, 0x21, 0x07, 0xD7,
+	0x2F, 0xCD, 0x71, 0xED, 0x7D, 0xF2, 0x9F, 0xA5, 0x55, 0x9E, 0xED, 0xE4, 0xF9, 0x23, 0x4D, 0xCC,
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+	0xEA, 0x19, 0xBC, 0x47, 0xCD, 0x73, 0x77, 0xFE, 0x21, 0xB1, 0xD0, 0xAD, 0x53, 0x5A, 0xF1, 0x05,
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+	0x0F, 0xFB, 0x0B, 0x71, 0x12, 0x49, 0x0D, 0xD0, 0xFF, 0x00, 0x69, 0xD6, 0xD8, 0xAF, 0x76, 0xEF,
+	0x55, 0x47, 0xC2, 0x3F, 0x8D, 0x62, 0xE9, 0xCF, 0xFC, 0x2B, 0xB8, 0x9F, 0x83, 0xF3, 0x41, 0xE2,
+	0x8D, 0x12, 0x64, 0x93, 0xFD, 0xA5, 0x11, 0xDE, 0xB6, 0xD3, 0xE8, 0x59, 0x55, 0x87, 0xA8, 0x35,
+	0xDA, 0x55, 0x79, 0xBA, 0x54, 0x4A, 0x3C, 0xC5, 0xC6, 0xA1, 0xCA, 0x7F, 0xC2, 0xA5, 0xF8, 0xD9,
+	0xFF, 0x00, 0x44, 0xD2, 0xEF, 0xFF, 0x00, 0x0A, 0x0D, 0x2B, 0xFF, 0x00, 0x93, 0x28, 0xFF, 0x00,
+	0x85, 0x49, 0xF1, 0xB0, 0xF1, 0xFF, 0x00, 0x0A, 0xD2, 0xEF, 0xFF, 0x00, 0x0A, 0x0D, 0x2B, 0xFF,
+	0x00, 0x93, 0x2B, 0xA7, 0xA0, 0x36, 0xC3, 0xBB, 0xD3, 0x9A, 0x9F, 0x64, 0x57, 0xB7, 0xE5, 0x39,
+	0x73, 0xF0, 0x73, 0xE3, 0x53, 0x8D, 0xA3, 0xE1, 0x95, 0xCF, 0x3C, 0x7C, 0xDE, 0x20, 0xD2, 0xF1,
+	0xFA, 0x5E, 0x1F, 0xE5, 0x4A, 0x9F, 0x03, 0xFE, 0x36, 0x79, 0x67, 0xFE, 0x2D, 0x9B, 0x7D, 0xDF,
+	0xE1, 0xF1, 0x06, 0x9D, 0x9F, 0xFD, 0x28, 0xAE, 0xBA, 0x1B, 0xEE, 0x29, 0xFF, 0x00, 0x6E, 0xA3,
+	0xD9, 0x07, 0xB6, 0xE6, 0x38, 0xA1, 0xF0, 0x3F, 0xE3, 0x58, 0x39, 0xFF, 0x00, 0x85, 0x67, 0x73,
+	0xFF, 0x00, 0x02, 0xD7, 0xB4, 0xE2, 0x3F, 0xF4, 0xA2, 0x9F, 0xFF, 0x00, 0x0A, 0x5B, 0xE3, 0x61,
+	0xE3, 0xFE, 0x15, 0x9B, 0x7F, 0xC0, 0x75, 0x6D, 0x3B, 0x3F, 0xFA, 0x51, 0x5D, 0x93, 0x5E, 0xE5,
+	0x71, 0x55, 0xA5, 0x9B, 0x2D, 0x8A, 0x3D, 0x90, 0x7B, 0x43, 0x96, 0x7F, 0x82, 0x1F, 0x1A, 0xCA,
+	0x11, 0xFF, 0x00, 0x0A, 0xB6, 0xE9, 0xF8, 0xFB, 0xA7, 0x56, 0xD3, 0xBE, 0x6F, 0x6F, 0xF8, 0xF8,
+	0x35, 0x02, 0xFC, 0x0C, 0xF8, 0xCD, 0x21, 0x11, 0xDC, 0x78, 0x6F, 0x4F, 0xB0, 0x8D, 0xB8, 0x92,
+	0xEE, 0xFB, 0xC5, 0x5A, 0x42, 0x88, 0x57, 0xB8, 0x2A, 0x2F, 0x16, 0x42, 0x07, 0xA2, 0x2B, 0x31,
+	0xEC, 0x09, 0xC0, 0xAE, 0xBC, 0xF4, 0xA8, 0xEA, 0xA3, 0x4C, 0x3D, 0xA1, 0x93, 0xA7, 0x7C, 0x1B,
+	0xF0, 0xB6, 0x8C, 0x9E, 0x6F, 0x8E, 0x7C, 0x49, 0x26, 0xB8, 0xD1, 0xFC, 0xCD, 0xA2, 0xE8, 0x72,
+	0x5C, 0xC5, 0x66, 0x71, 0xDE, 0x4B, 0xE9, 0x11, 0x26, 0xC7, 0xAA, 0x41, 0x14, 0x47, 0x1F, 0x76,
+	0xE5, 0x8E, 0x2B, 0xA2, 0xBD, 0xBC, 0x5B, 0xC3, 0x09, 0x92, 0x2B, 0x7B, 0x58, 0x21, 0x87, 0xCB,
+	0xB2, 0xD3, 0x6D, 0x6D, 0xFC, 0x9B, 0x7B, 0x55, 0xC7, 0x1E, 0x5A, 0x2A, 0xA0, 0x0C, 0x7B, 0xA0,
+	0xDE, 0x7F, 0x89, 0x9B, 0xAD, 0x53, 0x1D, 0x6A, 0x41, 0xD6, 0xAB, 0x97, 0x94, 0xC6, 0xA4, 0xB9,
+	0x84, 0x7F, 0xB8, 0x7E, 0x94, 0x90, 0x9C, 0x0C, 0xD3, 0xA7, 0xA8, 0xE9, 0xFB, 0xC6, 0x65, 0xC8,
+	0x66, 0xCF, 0x15, 0x20, 0xEB, 0x55, 0xED, 0xBA, 0xAF, 0xFB, 0xC2, 0xAE, 0x51, 0xEF, 0x00, 0x51,
+	0x45, 0x14, 0x7B, 0xC0, 0x14, 0x51, 0x45, 0x1E, 0xF0, 0x12, 0x43, 0xD2, 0xAD, 0x42, 0x32, 0x31,
+	0x55, 0x61, 0xE9, 0x56, 0xAD, 0xD5, 0xA4, 0x21, 0x10, 0xE1, 0x9B, 0x01, 0x4F, 0xA5, 0x1A, 0x95,
+	0x12, 0xC4, 0x76, 0xF9, 0x5C, 0x56, 0x96, 0x91, 0xA6, 0xB4, 0xF2, 0x24, 0x4A, 0x17, 0x73, 0x30,
+	0x51, 0xBB, 0xA7, 0x5E, 0xF4, 0xCF, 0x0C, 0x68, 0x7A, 0xAE, 0xBB, 0x7D, 0xF6, 0x4D, 0x1B, 0x4C,
+	0x49, 0xA4, 0x56, 0x1E, 0x74, 0xD2, 0x36, 0xD5, 0x41, 0xDC, 0x93, 0xD8, 0x0F, 0x5A, 0xFA, 0x3B,
+	0xF6, 0x14, 0xFD, 0x84, 0xBC, 0x79, 0xFB, 0x67, 0xFC, 0x55, 0x1F, 0x08, 0x3C, 0x0D, 0x7D, 0x79,
+	0x0F, 0x85, 0x74, 0x99, 0x15, 0x7E, 0x23, 0xF8, 0xEA, 0x2B, 0x70, 0xB0, 0xD9, 0xDB, 0xE7, 0x77,
+	0xF6, 0x7D, 0xA9, 0xE8, 0x6F, 0x64, 0x5D, 0xCB, 0xD8, 0x43, 0x91, 0x27, 0xCA, 0x04, 0x6B, 0x32,
+	0x94, 0xF9, 0x62, 0x6D, 0x4E, 0x3C, 0xC7, 0xDA, 0xBF, 0xF0, 0x6F, 0x1F, 0xEC, 0xBB, 0x1F, 0x86,
+	0x7C, 0x29, 0xE2, 0xDF, 0xDA, 0xF3, 0x53, 0xD3, 0xBC, 0xB5, 0xF1, 0x6C, 0x9F, 0xD8, 0x1E, 0x0F,
+	0x91, 0x8E, 0x5E, 0x4D, 0x36, 0xCA, 0x66, 0x37, 0x37, 0x5F, 0xEE, 0xCD, 0x74, 0x4A, 0x7F, 0xDB,
+	0x98, 0x6F, 0xF9, 0x69, 0x5F, 0xA6, 0x15, 0x8F, 0xF0, 0xF7, 0xC0, 0x5E, 0x11, 0xF8, 0x59, 0xE0,
+	0x7D, 0x27, 0xE1, 0xC7, 0x80, 0x7C, 0x3D, 0x6B, 0xA4, 0xE8, 0x9A, 0x1D, 0x84, 0x56, 0x3A, 0x4E,
+	0x99, 0x63, 0x1E, 0xD8, 0xAD, 0x6D, 0xE2, 0x40, 0x91, 0xC6, 0xA3, 0xD0, 0x28, 0x03, 0xDE, 0xB6,
+	0x2B, 0x99, 0xBB, 0x9D, 0x69, 0x5B, 0x40, 0xA2, 0x8A, 0x29, 0x0C, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0xE5, 0x7E, 0x31, 0x7C, 0x18, 0xF8, 0x69, 0xF1, 0xEB, 0xC0, 0x5A, 0x87, 0xC3,
+	0x3F, 0x8B, 0x9E, 0x0C, 0xB1, 0xF1, 0x0E, 0x83, 0xA9, 0xC2, 0x12, 0xEF, 0x49, 0xD4, 0x63, 0xCC,
+	0x6C, 0xC0, 0xE5, 0x64, 0x56, 0x18, 0x78, 0xA4, 0x53, 0xCA, 0xC8, 0x84, 0x32, 0x10, 0x19, 0x48,
+	0x20, 0x1A, 0xFC, 0xBC, 0xFD, 0xA9, 0xFF, 0x00, 0xE0, 0x88, 0x3F, 0x1D, 0x7E, 0x13, 0x5C, 0xDE,
+	0x78, 0x8B, 0xF6, 0x56, 0xD4, 0xE1, 0xF8, 0x91, 0xE1, 0x1D, 0xEF, 0x33, 0x78, 0x07, 0xC4, 0xD7,
+	0x10, 0x41, 0xAB, 0x5A, 0x8E, 0xA5, 0x6D, 0x6E, 0x65, 0xDB, 0x05, 0xC2, 0xA8, 0xE8, 0x25, 0xF2,
+	0xDC, 0x70, 0x32, 0xFD, 0xFF, 0x00, 0x5B, 0x68, 0xA0, 0x99, 0x45, 0x48, 0xFE, 0x68, 0x7C, 0x77,
+	0xF0, 0x7F, 0x41, 0xD0, 0xFC, 0x61, 0x71, 0xF0, 0xEF, 0xC7, 0x9A, 0x26, 0xB5, 0xF0, 0xEF, 0xC5,
+	0x28, 0x4B, 0x49, 0xA0, 0xF8, 0x96, 0xC2, 0x58, 0xA6, 0x61, 0xEB, 0x1A, 0xCA, 0x16, 0x57, 0x4F,
+	0xFA, 0x68, 0x19, 0x93, 0x1C, 0xA8, 0x3C, 0x57, 0x3F, 0xA8, 0xFE, 0xCF, 0x9E, 0x2F, 0x44, 0x67,
+	0xF0, 0xFB, 0xE9, 0x7A, 0xAC, 0x61, 0x49, 0x2D, 0x05, 0xE2, 0xA4, 0x84, 0x7B, 0xAC, 0x9D, 0x7E,
+	0x95, 0xFD, 0x2C, 0xFC, 0x50, 0xF8, 0x3B, 0xF0, 0xA7, 0xE3, 0x4F, 0x85, 0xE6, 0xF0, 0x67, 0xC5,
+	0xFF, 0x00, 0x86, 0xBA, 0x0F, 0x8A, 0xB4, 0x89, 0xB7, 0x19, 0x34, 0xBF, 0x11, 0x69, 0x51, 0x5E,
+	0x40, 0xC4, 0x8C, 0x13, 0xB2, 0x55, 0x60, 0x3E, 0xA0, 0x57, 0xCA, 0x5F, 0x15, 0xFF, 0x00, 0xE0,
+	0x84, 0x9F, 0xB0, 0x67, 0x8E, 0xEE, 0x9F, 0x53, 0xF0, 0x06, 0x97, 0xE2, 0xCF, 0x87, 0x57, 0xCF,
+	0x92, 0xB7, 0x1E, 0x0C, 0xF1, 0x3C, 0x8B, 0x0A, 0x9E, 0xCA, 0xB6, 0xB7, 0x82, 0xE2, 0xDD, 0x17,
+	0x3D, 0xA3, 0x8E, 0x3F, 0x62, 0x3A, 0xD6, 0x91, 0x9F, 0x29, 0x8C, 0xA8, 0x73, 0x1F, 0x85, 0xFA,
+	0x9F, 0xC2, 0xEF, 0x88, 0x9A, 0x51, 0x26, 0x5F, 0x05, 0x5F, 0x2A, 0xAF, 0x2C, 0xD6, 0xB6, 0x26,
+	0x50, 0x07, 0xAF, 0xC9, 0xC7, 0xE7, 0x58, 0x3A, 0x85, 0xB5, 0xE5, 0x8B, 0xF9, 0x5A, 0x84, 0x97,
+	0x10, 0x37, 0x4F, 0x2E, 0xE6, 0xDF, 0xCB, 0x27, 0xDB, 0x15, 0xFA, 0x31, 0xFF, 0x00, 0x05, 0x0C,
+	0xFD, 0x9B, 0xBE, 0x1D, 0xFF, 0x00, 0xC1, 0x27, 0xAD, 0x3C, 0x2F, 0xE2, 0xFF, 0x00, 0x1C, 0x7C,
+	0x6C, 0xF1, 0x27, 0x8B, 0x3C, 0x37, 0xE2, 0x09, 0x6F, 0xE3, 0x01, 0xFC, 0x35, 0x03, 0x5D, 0x58,
+	0x88, 0x5A, 0xDC, 0xE1, 0xA4, 0x13, 0x04, 0x93, 0x22, 0x7E, 0x82, 0x35, 0xCE, 0xCA, 0xF9, 0xAF,
+	0xC5, 0xFF, 0x00, 0xF0, 0x50, 0xFF, 0x00, 0xD8, 0xA6, 0xDA, 0xFB, 0xFB, 0x2A, 0xD2, 0xFB, 0xC4,
+	0xD7, 0x91, 0xC6, 0x91, 0x86, 0x9D, 0xB4, 0x02, 0x91, 0x01, 0xF7, 0x8A, 0x32, 0x97, 0x2C, 0x4F,
+	0xB0, 0x05, 0x4F, 0xA1, 0x15, 0xA4, 0x6A, 0x19, 0xCA, 0x8F, 0x29, 0xF3, 0x9D, 0x07, 0xA5, 0x7B,
+	0xB7, 0xFC, 0x36, 0x57, 0xFC, 0x13, 0xEF, 0xC4, 0xBF, 0x36, 0xA7, 0xAD, 0xE9, 0xB6, 0xA5, 0xBA,
+	0x8D, 0x53, 0xC2, 0xC7, 0x70, 0xFF, 0x00, 0xC8, 0x75, 0x34, 0x3F, 0x1B, 0x3F, 0xE0, 0x9C, 0x7A,
+	0xBF, 0xEE, 0xE1, 0xF1, 0xE7, 0x85, 0x55, 0xDF, 0xE5, 0x46, 0xFE, 0xCF, 0x92, 0x1C, 0x13, 0xD3,
+	0xAA, 0x0C, 0x7E, 0x63, 0xEA, 0x2A, 0xB9, 0xB9, 0x89, 0xF6, 0x47, 0xCF, 0xF4, 0x57, 0xD1, 0x30,
+	0xEA, 0x7F, 0xB0, 0x2E, 0xA6, 0x32, 0x9F, 0x12, 0xBC, 0x2A, 0xCC, 0x7E, 0xEA, 0xFF, 0x00, 0x6C,
+	0x79, 0x79, 0xF6, 0xC7, 0x99, 0x56, 0x61, 0xF0, 0xBF, 0xEC, 0x35, 0x7F, 0xFB, 0xC8, 0x7C, 0x73,
+	0xE1, 0x6D, 0xFF, 0x00, 0xC3, 0xB7, 0xC4, 0x18, 0x39, 0xED, 0xCF, 0x99, 0x4F, 0x51, 0x72, 0xF2,
+	0x9F, 0x36, 0xD1, 0x5F, 0x4B, 0x7F, 0xC2, 0xAD, 0xFD, 0x8E, 0xEF, 0xFF, 0x00, 0x7B, 0x1F, 0x8E,
+	0x74, 0x1D, 0xC3, 0x91, 0xB7, 0xC5, 0x5C, 0xFF, 0x00, 0xE8, 0xCA, 0x6C, 0xBF, 0x09, 0x3F, 0x65,
+	0x06, 0x8D, 0x84, 0x3E, 0x37, 0xD2, 0xD9, 0xB6, 0x9D, 0xAB, 0xFF, 0x00, 0x09, 0x57, 0x53, 0xFF,
+	0x00, 0x7F, 0x28, 0xD4, 0x47, 0xCD, 0x78, 0xCF, 0x14, 0xA2, 0x2C, 0x1C, 0xD7, 0xD1, 0xB0, 0x7C,
+	0x1B, 0xFD, 0x9B, 0x5C, 0xED, 0x7F, 0x13, 0x69, 0x5B, 0x4F, 0x0D, 0xFF, 0x00, 0x15, 0x57, 0xFF,
+	0x00, 0x6C, 0xA9, 0xFF, 0x00, 0xE1, 0x47, 0x7E, 0xCB, 0xBF, 0xF4, 0x34, 0xE9, 0x4B, 0xFE, 0xD7,
+	0xFC, 0x25, 0x5D, 0x3F, 0xF2, 0x25, 0x1A, 0x81, 0xF3, 0x75, 0x07, 0xA5, 0x7D, 0x24, 0xBF, 0x03,
+	0xFF, 0x00, 0x65, 0xDC, 0xFF, 0x00, 0xC8, 0xF5, 0xA4, 0xFF, 0x00, 0xE1, 0x51, 0x9F, 0xD3, 0xCC,
+	0xA9, 0x3F, 0xE1, 0x48, 0x7E, 0xCB, 0x83, 0x99, 0x3C, 0x6F, 0xA5, 0x32, 0xFF, 0x00, 0x12, 0xFF,
+	0x00, 0xC2, 0x41, 0x8C, 0x8F, 0xAF, 0x99, 0x46, 0xA0, 0x7C, 0xCB, 0x4A, 0xA3, 0x2C, 0x07, 0xBD,
+	0x7D, 0x32, 0xBF, 0x05, 0x7F, 0x64, 0x85, 0x39, 0x3E, 0x2A, 0xD2, 0x17, 0xFD, 0xA6, 0xF1, 0x4E,
+	0x40, 0xF7, 0x3F, 0xBC, 0xE9, 0x56, 0x3F, 0xE1, 0x51, 0x7E, 0xCC, 0x96, 0xF0, 0xB4, 0xFA, 0x76,
+	0xB3, 0xA6, 0xDF, 0x2A, 0x29, 0x6D, 0xB6, 0xBA, 0xF3, 0x30, 0x6C, 0x76, 0xC2, 0xB9, 0x27, 0xF0,
+	0x04, 0xFA, 0x03, 0x46, 0xA3, 0xE5, 0xE6, 0x3E, 0x6E, 0xB3, 0x83, 0x8A, 0x9F, 0xC8, 0xF7, 0xAF,
+	0xA0, 0xAF, 0xBE, 0x08, 0x59, 0x5A, 0x5F, 0xA2, 0xE8, 0x7F, 0xB1, 0xC7, 0xC4, 0xCD, 0x5F, 0xCE,
+	0x87, 0x7D, 0xAC, 0xBA, 0x5F, 0x82, 0xF5, 0xC9, 0x92, 0x55, 0xC7, 0x0C, 0xA6, 0x08, 0x88, 0x75,
+	0xFF, 0x00, 0x6B, 0x15, 0x7B, 0x4B, 0xFD, 0x9E, 0x7E, 0x28, 0x6A, 0x4C, 0xA7, 0x4C, 0xFF, 0x00,
+	0x82, 0x6E, 0x7C, 0x5D, 0xB9, 0xCB, 0x7D, 0xE6, 0xF8, 0x57, 0xAD, 0x20, 0x1F, 0x56, 0x96, 0xDF,
+	0x9F, 0xC7, 0x8A, 0x5C, 0xFC, 0xA5, 0xC6, 0x99, 0xF3, 0x7F, 0x91, 0xEF, 0x47, 0x91, 0xEF, 0x5F,
+	0x5C, 0x69, 0x1F, 0xB1, 0x17, 0xED, 0x61, 0xAF, 0xA8, 0x9B, 0xC3, 0x3F, 0xF0, 0x4D, 0x3F, 0x17,
+	0x28, 0xFE, 0x13, 0xA9, 0x78, 0x7E, 0x3B, 0x46, 0x1F, 0xF8, 0x12, 0xF1, 0x63, 0xF1, 0xAE, 0xC3,
+	0xC3, 0x5F, 0xF0, 0x4E, 0x2F, 0xF8, 0x29, 0x2E, 0xA7, 0xB4, 0x68, 0xBF, 0xF0, 0x4F, 0x5B, 0x5D,
+	0x22, 0x16, 0x60, 0x24, 0xBC, 0xD5, 0xBC, 0x47, 0xA1, 0xC0, 0x42, 0xF7, 0x62, 0x91, 0x5D, 0x34,
+	0x87, 0x1D, 0x70, 0x55, 0x89, 0xF4, 0x3D, 0x2A, 0x65, 0x50, 0xAF, 0x64, 0x7C, 0x3B, 0x6F, 0x68,
+	0xF3, 0x91, 0x0C, 0x51, 0x33, 0xB3, 0x7C, 0xAA, 0x91, 0xA9, 0x2C, 0xC4, 0xF6, 0x03, 0xD6, 0xB6,
+	0x34, 0xCF, 0x85, 0xFE, 0x3D, 0xD5, 0xB0, 0xBA, 0x6F, 0x85, 0xB5, 0x36, 0x56, 0x38, 0xDA, 0xF6,
+	0xEC, 0xAA, 0x7E, 0xA5, 0xBE, 0x50, 0x3D, 0xCF, 0x1E, 0xB5, 0xFA, 0x19, 0xE1, 0xAF, 0xF8, 0x23,
+	0xDF, 0xFC, 0x15, 0x0B, 0xC4, 0x61, 0x5E, 0xF2, 0x3F, 0x84, 0xDE, 0x15, 0xB7, 0xDC, 0x36, 0x2D,
+	0xD7, 0x89, 0xAF, 0x25, 0x99, 0x72, 0x7A, 0xEC, 0xB6, 0xB2, 0x64, 0xE3, 0xAE, 0x0B, 0x01, 0xEE,
+	0x2B, 0xD2, 0xBC, 0x25, 0xFF, 0x00, 0x06, 0xFF, 0x00, 0xFC, 0x61, 0xD7, 0xFC, 0xB9, 0xFE, 0x30,
+	0xFE, 0xDA, 0xF6, 0x90, 0x47, 0xB8, 0x1B, 0x8D, 0x37, 0xC2, 0x3E, 0x09, 0xC1, 0xEB, 0xC8, 0x5B,
+	0x9B, 0x8B, 0x83, 0xCF, 0xA3, 0x18, 0xB8, 0x3C, 0xE0, 0xF4, 0xA9, 0xF6, 0xA1, 0xEC, 0x8F, 0xCC,
+	0x9D, 0x37, 0xE0, 0x1F, 0x8B, 0x11, 0x77, 0x6A, 0xB7, 0x76, 0x1A, 0x78, 0x1C, 0xB4, 0x37, 0x77,
+	0x49, 0xCF, 0xB7, 0xC9, 0xC5, 0x6F, 0x78, 0x2B, 0xE1, 0xBF, 0x86, 0x75, 0x2F, 0x16, 0xC7, 0xE0,
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+	0xA7, 0x9A, 0x5C, 0xF4, 0xDF, 0x1C, 0x4B, 0x3C, 0x9B, 0x01, 0xEA, 0xC5, 0x55, 0x31, 0xD7, 0x8A,
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+	0x28, 0xFF, 0x00, 0xE7, 0xA3, 0xB9, 0xE3, 0x6F, 0x72, 0x71, 0x40, 0x1F, 0xB0, 0xBF, 0xF0, 0x68,
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+	0xF0, 0x55, 0x0F, 0xD9, 0xE2, 0x79, 0xB4, 0x8F, 0xDA, 0x5B, 0xF6, 0x32, 0xF8, 0x91, 0xA0, 0xC3,
+	0x6C, 0x0C, 0x32, 0xEA, 0xB7, 0x3E, 0x15, 0x9E, 0xF3, 0x4E, 0xDB, 0x8C, 0x16, 0x17, 0xD6, 0x89,
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+	0xDC, 0x49, 0xA7, 0xE9, 0xD6, 0xBA, 0x4D, 0x9E, 0xA0, 0xA0, 0x81, 0xF6, 0x58, 0xA3, 0x84, 0x8F,
+	0xEF, 0x6E, 0xC6, 0x24, 0x0D, 0xFA, 0xE6, 0xBF, 0xB0, 0xF7, 0x0C, 0x50, 0x85, 0x38, 0x38, 0xE0,
+	0xD7, 0x1B, 0xE3, 0xAF, 0xD9, 0xFF, 0x00, 0xE0, 0x47, 0xC5, 0x15, 0x91, 0x3E, 0x29, 0xFC, 0x19,
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+	0xFF, 0x00, 0x82, 0x45, 0xFF, 0x00, 0xC1, 0x2C, 0xBC, 0x44, 0xF7, 0x12, 0xEB, 0x5F, 0xF0, 0x4E,
+	0x3F, 0x82, 0x0F, 0x25, 0xC0, 0x22, 0x69, 0xAD, 0xFE, 0x18, 0xE9, 0x71, 0xC8, 0xD9, 0x18, 0x27,
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+	0x10, 0x9F, 0x39, 0xFF, 0x00, 0x82, 0x73, 0x7C, 0x29, 0x5C, 0x73, 0x96, 0xF0, 0x9D, 0xBE, 0x05,
+	0x00, 0x7F, 0x34, 0x6B, 0xFB, 0x64, 0x78, 0xD5, 0xCE, 0xC9, 0x07, 0xCA, 0xDC, 0x37, 0xFA, 0xCE,
+	0x9F, 0x8D, 0x25, 0xC7, 0xED, 0x71, 0xE2, 0x64, 0x1B, 0xD3, 0xEF, 0x0E, 0x56, 0xBF, 0xA5, 0x3B,
+	0xCF, 0xF8, 0x21, 0x7F, 0xFC, 0x12, 0x0B, 0x51, 0x3E, 0x63, 0x7F, 0xC1, 0x3D, 0x3E, 0x18, 0x6D,
+	0xFE, 0x2F, 0xB2, 0xE8, 0x2B, 0x17, 0xE8, 0x98, 0xA8, 0x4F, 0xFC, 0x10, 0x77, 0xFE, 0x08, 0xF1,
+	0xFC, 0x3F, 0xF0, 0x4F, 0x7F, 0x87, 0xF9, 0xED, 0xFF, 0x00, 0x12, 0xD9, 0x3F, 0xF8, 0xBA, 0x00,
+	0xFE, 0x6A, 0xBF, 0xE1, 0xB1, 0x3C, 0x66, 0x78, 0x7D, 0xDB, 0x7F, 0x8B, 0x68, 0xE7, 0xF9, 0x8A,
+	0xA9, 0x77, 0xFB, 0x5D, 0x6B, 0xF2, 0xB7, 0x97, 0x34, 0x77, 0x6C, 0x8D, 0xC3, 0x2F, 0xDB, 0xEE,
+	0xE2, 0xC8, 0xF4, 0xFD, 0xDC, 0xA3, 0xF9, 0xD7, 0xF4, 0xD5, 0x6B, 0xFF, 0x00, 0x04, 0x39, 0xFF,
+	0x00, 0x82, 0x44, 0x58, 0x45, 0xE5, 0xAF, 0xFC, 0x13, 0xD7, 0xE1, 0x83, 0x67, 0x8F, 0xF4, 0x9F,
+	0x0E, 0x45, 0x27, 0xEA, 0xF9, 0x35, 0xB5, 0xA3, 0x7F, 0xC1, 0x1E, 0x7F, 0xE0, 0x94, 0x9A, 0x0A,
+	0xAC, 0x5A, 0x77, 0xFC, 0x13, 0x93, 0xE0, 0x8B, 0x73, 0xCF, 0xDB, 0x3E, 0x1B, 0x69, 0xB7, 0x39,
+	0xFF, 0x00, 0xBF, 0xB1, 0x1A, 0x00, 0xFE, 0x5A, 0x6F, 0xBF, 0x6C, 0x58, 0xB4, 0xC0, 0x7C, 0xF7,
+	0xBA, 0x81, 0x17, 0x97, 0x8C, 0xEB, 0xD7, 0x47, 0x23, 0xB8, 0xC4, 0x93, 0x9C, 0xFE, 0x47, 0xE8,
+	0x6A, 0xFF, 0x00, 0x80, 0xFF, 0x00, 0x6A, 0x5B, 0xDF, 0x13, 0xF8, 0x9D, 0x7F, 0xE1, 0x59, 0xFC,
+	0x2E, 0x5D, 0x6B, 0x5B, 0x74, 0xC4, 0x69, 0xA0, 0xE9, 0x2D, 0x79, 0x75, 0x26, 0x7A, 0x2E, 0x2D,
+	0xC1, 0x76, 0x24, 0xF1, 0x82, 0x0E, 0x4F, 0x63, 0x5F, 0xD6, 0x2F, 0x84, 0x3F, 0x61, 0x7F, 0xD8,
+	0x9B, 0xE1, 0xBF, 0x96, 0xBF, 0x0F, 0x7F, 0x63, 0x7F, 0x85, 0x7A, 0x1F, 0x96, 0xC1, 0xA3, 0x3A,
+	0x37, 0xC3, 0xED, 0x36, 0xD4, 0xA1, 0x07, 0x82, 0x3C, 0xA8, 0x06, 0x08, 0xED, 0xD2, 0xBD, 0x1F,
+	0x44, 0xD0, 0x3C, 0x33, 0xA1, 0x45, 0xF6, 0x2F, 0x0E, 0xE8, 0x76, 0x3A, 0x7A, 0x2F, 0xFC, 0xB1,
+	0xB3, 0xB7, 0x48, 0xC7, 0xE4, 0x98, 0xA0, 0x0F, 0xE6, 0x3B, 0xE0, 0xDF, 0xEC, 0xE7, 0xFF, 0x00,
+	0x05, 0x89, 0xFD, 0xA7, 0x0C, 0x70, 0x7C, 0x20, 0xFD, 0x85, 0xFC, 0x6F, 0x6B, 0x66, 0xCC, 0xA1,
+	0xF5, 0x4F, 0x16, 0x69, 0x3F, 0xF0, 0x8F, 0x59, 0xC6, 0xA7, 0xF8, 0xFC, 0xDD, 0x4D, 0xAD, 0xFC,
+	0xC5, 0x19, 0xC9, 0xF2, 0xB7, 0xB6, 0x07, 0x00, 0x9C, 0x0A, 0xFD, 0x44, 0xFF, 0x00, 0x82, 0x5A,
+	0xFF, 0x00, 0xC1, 0x02, 0x6E, 0xBE, 0x00, 0xFC, 0x47, 0xD0, 0xFF, 0x00, 0x6A, 0xFF, 0x00, 0xDB,
+	0xF7, 0xC6, 0xD6, 0x7E, 0x3A, 0xF8, 0x9B, 0xA3, 0x5C, 0x8B, 0xCF, 0x0A, 0xF8, 0x67, 0x4B, 0xCB,
+	0xE8, 0x3E, 0x17, 0xB8, 0x1F, 0x76, 0xE1, 0x0B, 0x80, 0xF7, 0x97, 0x68, 0x46, 0xF5, 0x99, 0xD5,
+	0x23, 0x89, 0x98, 0x32, 0xA3, 0xCA, 0xAB, 0x30, 0xFD, 0x3E, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x3F, 0xFF, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46,
+	0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60, 0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x22,
+	0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D, 0x00, 0x2A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01,
+	0x01, 0x12, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xFF, 0xDB, 0x00, 0x43, 0x00, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x02,
+	0x02, 0x02, 0x02, 0x02, 0x04, 0x03, 0x02, 0x02, 0x02, 0x02, 0x05, 0x04, 0x04, 0x03, 0x04, 0x06,
+	0x05, 0x06, 0x06, 0x06, 0x05, 0x06, 0x06, 0x06, 0x07, 0x09, 0x08, 0x06, 0x07, 0x09, 0x07, 0x06,
+	0x06, 0x08, 0x0B, 0x08, 0x09, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x06, 0x08, 0x0B, 0x0C, 0x0B, 0x0A,
+	0x0C, 0x09, 0x0A, 0x0A, 0x0A, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+	0x05, 0x03, 0x03, 0x05, 0x0A, 0x07, 0x06, 0x07, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00,
+	0x2A, 0x00, 0x6A, 0x03, 0x01, 0x22, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00,
+	0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4,
+	0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00,
+	0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13,
+	0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15,
+	0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25,
+	0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46,
+	0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66,
+	0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86,
+	0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4,
+	0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2,
+	0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9,
+	0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5,
+	0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00, 0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+	0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04,
+	0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00, 0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11,
+	0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, 0x13, 0x22, 0x32, 0x81, 0x08,
+	0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A,
+	0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35,
+	0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55,
+	0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75,
+	0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93,
+	0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA,
+	0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8,
+	0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6,
+	0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00,
+	0x0C, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3F, 0x00, 0xF2, 0xFF, 0x00, 0xF8, 0x2D,
+	0xA7, 0xFC, 0x16, 0xCB, 0xF6, 0xB8, 0xF8, 0xA3, 0xFB, 0x63, 0xF8, 0xBF, 0xE0, 0xA7, 0xEC, 0xFB,
+	0xF1, 0xBB, 0xC4, 0x1E, 0x07, 0xF0, 0x37, 0x80, 0x35, 0xEB, 0xAD, 0x0E, 0xD2, 0xDF, 0xC2, 0xBA,
+	0x9C, 0x96, 0x53, 0x6A, 0x37, 0x56, 0xB2, 0x98, 0xA7, 0xB9, 0x9A, 0x68, 0x8A, 0xBB, 0xEE, 0x91,
+	0x1F, 0x6A, 0x93, 0xB5, 0x54, 0x28, 0x03, 0x71, 0x66, 0x6F, 0x8C, 0x7F, 0xE1, 0xE3, 0x1F, 0xF0,
+	0x50, 0x5F, 0xFA, 0x3D, 0xEF, 0x8B, 0x5F, 0xF8, 0x5F, 0x5F, 0xFF, 0x00, 0xF1, 0xDA, 0xC5, 0xFD,
+	0xB3, 0x6E, 0xCE, 0xA3, 0xFB, 0x66, 0x7C, 0x63, 0xBB, 0x6F, 0xE2, 0xF8, 0xB9, 0xE2, 0x81, 0xF9,
+	0x6A, 0xF7, 0x23, 0xFA, 0x57, 0x9A, 0x17, 0x19, 0xC2, 0x8C, 0xFA, 0x50, 0x6D, 0x18, 0xC7, 0x96,
+	0xE7, 0xB2, 0xFF, 0x00, 0xC3, 0xC6, 0x3F, 0xE0, 0xA0, 0xBD, 0x3F, 0xE1, 0xB7, 0xBE, 0x2D, 0x7F,
+	0xE1, 0x7D, 0x7F, 0xFF, 0x00, 0xC7, 0x68, 0xFF, 0x00, 0x87, 0x8B, 0xFF, 0x00, 0xC1, 0x41, 0xB3,
+	0x8F, 0xF8, 0x6D, 0xEF, 0x8B, 0x5F, 0xF8, 0x5F, 0x5F, 0xFF, 0x00, 0xF1, 0xDA, 0xE5, 0xFF, 0x00,
+	0x66, 0xCF, 0xD9, 0x7F, 0xF6, 0x86, 0xFD, 0xB0, 0xFE, 0x27, 0xDB, 0xFC, 0x1A, 0xFD, 0x99, 0x3E,
+	0x12, 0x6A, 0xFE, 0x30, 0xF1, 0x15, 0xC1, 0x0F, 0x25, 0x9E, 0x97, 0x6E, 0x3C, 0xAB, 0x38, 0xB3,
+	0x83, 0x3D, 0xCC, 0xCC, 0x56, 0x1B, 0x58, 0x41, 0x20, 0x79, 0x92, 0xBA, 0x2E, 0x48, 0x03, 0x25,
+	0x80, 0x3E, 0xD9, 0xFB, 0x27, 0x7F, 0xC1, 0x20, 0x3F, 0x6A, 0x8F, 0xDB, 0x03, 0xF6, 0xB2, 0xF8,
+	0x91, 0xFB, 0x17, 0xFC, 0x39, 0xF1, 0x2F, 0x81, 0xF4, 0xDF, 0x18, 0x7C, 0x2A, 0x6B, 0xD8, 0xFC,
+	0x51, 0x2F, 0x88, 0x35, 0x6B, 0xA8, 0xEC, 0xE4, 0x92, 0xD6, 0xF4, 0x59, 0x4A, 0x20, 0x96, 0x0B,
+	0x59, 0x1A, 0x4F, 0xDE, 0xF4, 0x25, 0x14, 0x15, 0x19, 0xEA, 0x70, 0x42, 0xBD, 0xC3, 0xCE, 0xC7,
+	0xFC, 0x14, 0x5F, 0xFE, 0x0A, 0x0A, 0x4E, 0x0F, 0xED, 0xBD, 0xF1, 0x6B, 0xFF, 0x00, 0x0B, 0xEB,
+	0xFF, 0x00, 0xFE, 0x3B, 0x47, 0xFC, 0x3C, 0x5B, 0xFE, 0x0A, 0x0A, 0x5B, 0x03, 0xF6, 0xDF, 0xF8,
+	0xB5, 0xFF, 0x00, 0x85, 0xF5, 0xFF, 0x00, 0xFF, 0x00, 0x1D, 0xAF, 0xAF, 0x7E, 0x26, 0x7F, 0xC1,
+	0xAA, 0xFF, 0x00, 0xF0, 0x55, 0x1F, 0x00, 0x78, 0x5E, 0xE3, 0xC4, 0x9E, 0x1D, 0x97, 0xE1, 0x87,
+	0x8B, 0xA6, 0xB6, 0x85, 0xA4, 0xFE, 0xC5, 0xF0, 0xE7, 0x8B, 0xAE, 0x12, 0xF2, 0xE0, 0x80, 0x4E,
+	0xD8, 0x96, 0xF2, 0xD2, 0x08, 0x99, 0xB8, 0xE8, 0xD2, 0xAF, 0x6C, 0x67, 0x9A, 0xFC, 0xFC, 0xF8,
+	0x7D, 0xF0, 0xC3, 0xC7, 0x3F, 0x13, 0xBE, 0x2B, 0x68, 0x7F, 0x04, 0xBC, 0x27, 0xE1, 0xBB, 0x89,
+	0x3C, 0x4F, 0xE2, 0x2F, 0x11, 0x5A, 0xE8, 0x5A, 0x7E, 0x93, 0x71, 0x19, 0x8E, 0x5F, 0xB7, 0x4F,
+	0x70, 0x2D, 0xD2, 0x17, 0x0C, 0xB9, 0x42, 0x24, 0x6D, 0xAD, 0xB9, 0x7E, 0x5C, 0x12, 0x47, 0xCA,
+	0x68, 0x0F, 0xDD, 0x9E, 0x8C, 0x3F, 0xE0, 0xA2, 0xFF, 0x00, 0xF0, 0x50, 0x63, 0xF7, 0x7F, 0x6D,
+	0xEF, 0x8B, 0x47, 0xFE, 0xE7, 0xEB, 0xFF, 0x00, 0xFE, 0x3B, 0x47, 0xFC, 0x3C, 0x5F, 0xFE, 0x0A,
+	0x07, 0x80, 0x47, 0xED, 0xC1, 0xF1, 0x67, 0x9F, 0xFA, 0x9F, 0xAF, 0xFF, 0x00, 0xF8, 0xED, 0x7D,
+	0x15, 0xFB, 0x6E, 0x7F, 0xC1, 0xBC, 0x3F, 0xB7, 0x5F, 0xEC, 0x1B, 0xFB, 0x3A, 0x6B, 0xBF, 0xB5,
+	0x17, 0xC5, 0x7F, 0x16, 0x7C, 0x37, 0xD7, 0x3C, 0x37, 0xE1, 0xBB, 0x8B, 0x44, 0xD5, 0xA0, 0xF0,
+	0x9E, 0xB3, 0x7D, 0x3D, 0xE4, 0x51, 0xCF, 0x70, 0x96, 0xEB, 0x3E, 0xCB, 0x8B, 0x38, 0x54, 0xC6,
+	0xAF, 0x22, 0x6E, 0x21, 0x81, 0x50, 0x73, 0xB4, 0x85, 0x24, 0x7C, 0x97, 0xFB, 0x35, 0xFE, 0xCC,
+	0xBF, 0x1E, 0x3F, 0x6C, 0x2F, 0x8C, 0x7A, 0x5F, 0xC0, 0x2F, 0xD9, 0xBF, 0xE1, 0xE5, 0xE7, 0x89,
+	0xBC, 0x53, 0xAA, 0xAB, 0xC9, 0x0D, 0x95, 0xB9, 0x58, 0xE3, 0x86, 0x14, 0x00, 0xC9, 0x71, 0x71,
+	0x33, 0xE2, 0x38, 0x21, 0x41, 0x8C, 0xC8, 0xE5, 0x57, 0x2C, 0xAA, 0x32, 0xEC, 0x8A, 0xC0, 0x5A,
+	0x07, 0x54, 0x7F, 0xE0, 0xA3, 0x1F, 0xF0, 0x50, 0x35, 0xEB, 0xFB, 0x70, 0xFC, 0x59, 0xFF, 0x00,
+	0xC2, 0xFA, 0xFF, 0x00, 0xFF, 0x00, 0x8E, 0xD3, 0xBF, 0xE1, 0xE2, 0xDF, 0xF0, 0x50, 0x3E, 0x9F,
+	0xF0, 0xDC, 0x1F, 0x16, 0xBF, 0xF0, 0xBE, 0xBF, 0xFF, 0x00, 0xE3, 0xB5, 0xF7, 0x0F, 0x88, 0xBF,
+	0xE0, 0xD2, 0xAF, 0xF8, 0x28, 0xB6, 0x89, 0xF0, 0xFA, 0x6F, 0x16, 0x69, 0xDF, 0x18, 0xBE, 0x12,
+	0x5F, 0xEA, 0xF6, 0xD6, 0x6D, 0x34, 0x9E, 0x1D, 0x8B, 0x58, 0xD4, 0x23, 0xDE, 0x55, 0x77, 0x79,
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+	0xD3, 0x2F, 0xD9, 0x6B, 0x5B, 0xFD, 0xA0, 0x3F, 0x6F, 0x0F, 0x8A, 0x7F, 0xB6, 0xE7, 0xEC, 0x9F,
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+	0xA1, 0xF5, 0x7F, 0xDA, 0x9B, 0xE2, 0x06, 0x9B, 0xE3, 0x75, 0xF1, 0x1C, 0xBE, 0x76, 0x85, 0xFD,
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+	0x00, 0xBA, 0x36, 0xEF, 0x19, 0x07, 0xA1, 0x05, 0xB2, 0x6B, 0xF6, 0x73, 0xFE, 0x08, 0xD5, 0xE0,
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+	0x6A, 0xB7, 0x1F, 0x0D, 0x74, 0x68, 0x2F, 0xD7, 0x51, 0x20, 0x95, 0xB8, 0x7B, 0xDF, 0xB5, 0x32,
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+	0x00, 0x82, 0xE4, 0x7E, 0xCA, 0xDF, 0x04, 0x3F, 0xE0, 0x82, 0x7E, 0x28, 0xFF, 0x00, 0x82, 0x59,
+	0xF8, 0xB7, 0xE1, 0xF7, 0xC4, 0x0B, 0xAF, 0x88, 0x1A, 0xE7, 0x83, 0xFC, 0x55, 0xA5, 0xDA, 0xEB,
+	0x7A, 0x7E, 0x9F, 0x62, 0xFA, 0x3A, 0xCD, 0xA9, 0xDC, 0x5D, 0x49, 0x03, 0x3C, 0xAF, 0x76, 0xB3,
+	0x05, 0x55, 0x9D, 0x77, 0xE2, 0x12, 0xC0, 0x83, 0xB4, 0x37, 0x06, 0x80, 0xD7, 0xB1, 0xF6, 0xDF,
+	0xFC, 0x1D, 0x23, 0xE3, 0x4F, 0x8F, 0x1F, 0xB2, 0xEF, 0xEC, 0x81, 0xF0, 0xCB, 0xF6, 0x47, 0xFD,
+	0x9D, 0xFE, 0x18, 0x27, 0x85, 0x7F, 0x67, 0xFD, 0x4A, 0x11, 0xA4, 0xF8, 0x83, 0x56, 0xD0, 0x24,
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+	0x99, 0xBE, 0xD2, 0xF1, 0x6C, 0x25, 0x16, 0x37, 0x59, 0xFF, 0x00, 0x06, 0xCE, 0xA1, 0x0E, 0xE2,
+	0xC5, 0xF6, 0x96, 0xFB, 0xCA, 0x0E, 0x7F, 0x5E, 0x33, 0xF5, 0xEF, 0xE9, 0x9C, 0xD7, 0xE9, 0xF7,
+	0xEC, 0x4F, 0xFF, 0x00, 0x07, 0x18, 0x7E, 0xCC, 0xD7, 0x5F, 0xF0, 0x4E, 0x2D, 0x4B, 0xFE, 0x09,
+	0xD9, 0xFF, 0x00, 0x05, 0x64, 0xF8, 0x27, 0xE3, 0x8F, 0x89, 0x7A, 0x5A, 0x69, 0xBF, 0xD8, 0x7A,
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+	0xDD, 0x40, 0xD1, 0xDD, 0xDA, 0x32, 0xC6, 0x21, 0xB9, 0x8C, 0xB3, 0x10, 0x91, 0x39, 0x2B, 0x2C,
+	0x65, 0xE4, 0xFC, 0xA6, 0xF1, 0xDE, 0xAB, 0xE0, 0x7B, 0x6F, 0x1A, 0xEB, 0x16, 0xBF, 0x0C, 0xB5,
+	0x7D, 0x62, 0xFB, 0xC3, 0x49, 0xAA, 0x5C, 0x2F, 0x87, 0x6F, 0x3C, 0x43, 0x63, 0x15, 0xB5, 0xFC,
+	0xB6, 0x3E, 0x61, 0xF2, 0x1A, 0xE6, 0x18, 0x5D, 0xE2, 0x49, 0xCC, 0x7B, 0x77, 0x88, 0xDD, 0xD4,
+	0x3E, 0x76, 0xB1, 0x5C, 0x1A, 0x07, 0x13, 0x65, 0xF5, 0x18, 0x42, 0x31, 0x32, 0xF6, 0xAF, 0xEB,
+	0x73, 0xFE, 0x09, 0x7B, 0x2C, 0x92, 0xFF, 0x00, 0xC1, 0x33, 0xFF, 0x00, 0x67, 0x79, 0x4C, 0xFF,
+	0x00, 0x7B, 0xE0, 0x5F, 0x84, 0x4F, 0x5F, 0xFA, 0x83, 0x5A, 0x57, 0xF1, 0xE7, 0x26, 0xB9, 0xF2,
+	0x30, 0x32, 0x9F, 0xBB, 0x5F, 0xD8, 0xDF, 0xFC, 0x13, 0x1A, 0xD8, 0x59, 0x7F, 0xC1, 0x36, 0x7F,
+	0x67, 0xBB, 0x36, 0x58, 0xF3, 0x0F, 0xC0, 0xFF, 0x00, 0x09, 0xA1, 0xC9, 0x1D, 0xB4, 0x7B, 0x51,
+	0x40, 0xE5, 0x23, 0xF9, 0x70, 0xFF, 0x00, 0x82, 0xE5, 0x7E, 0xCA, 0x7F, 0x16, 0x7F, 0x63, 0xCF,
+	0xF8, 0x29, 0x7F, 0xC5, 0x8D, 0x07, 0xE2, 0x0E, 0x81, 0x75, 0x06, 0x9B, 0xE2, 0x7F, 0x19, 0x6A,
+	0x1E, 0x23, 0xF0, 0xCE, 0xA6, 0xD0, 0x7E, 0xE6, 0xFE, 0xC6, 0xFA, 0xE5, 0xEE, 0x11, 0xD1, 0xBE,
+	0xE9, 0xC1, 0x90, 0xAB, 0x00, 0x49, 0x57, 0x56, 0x07, 0x90, 0x45, 0x7C, 0x86, 0x75, 0xC7, 0xFE,
+	0xFD, 0x7F, 0x72, 0x9F, 0xB5, 0x4F, 0xC0, 0x6F, 0x81, 0xBF, 0x1B, 0xFC, 0x04, 0xD6, 0xDF, 0x1A,
+	0x3E, 0x0C, 0x78, 0x4F, 0xC5, 0xF1, 0xD8, 0x48, 0x8D, 0x63, 0x1F, 0x8A, 0x3C, 0x3B, 0x6D, 0xA8,
+	0x2D, 0xBB, 0x34, 0x80, 0x13, 0x18, 0x9D, 0x1B, 0x61, 0x20, 0x0C, 0xE3, 0x19, 0xC5, 0x7C, 0xDF,
+	0xFF, 0x00, 0x0C, 0x03, 0xFB, 0x08, 0x7F, 0xD1, 0x94, 0x7C, 0x23, 0xFF, 0x00, 0xC3, 0x6F, 0xA5,
+	0xFF, 0x00, 0xF1, 0x8A, 0x08, 0xBB, 0x3F, 0x8F, 0xB1, 0xAD, 0xB2, 0xF2, 0x1E, 0x8F, 0xED, 0xC6,
+	0x03, 0x86, 0xAF, 0xEC, 0x13, 0xFE, 0x18, 0x07, 0xF6, 0x10, 0xFF, 0x00, 0xA3, 0x28, 0xF8, 0x47,
+	0xFF, 0x00, 0x86, 0xDF, 0x4B, 0xFF, 0x00, 0xE3, 0x14, 0x7F, 0xC3, 0x00, 0xFE, 0xC2, 0x1F, 0xF4,
+	0x65, 0x1F, 0x08, 0xFF, 0x00, 0xF0, 0xDB, 0xE9, 0x7F, 0xFC, 0x62, 0x81, 0xF3, 0x33, 0xF8, 0xFA,
+	0xFE, 0xDB, 0x6C, 0x7D, 0xFA, 0x5F, 0xED, 0xC6, 0x1F, 0xC7, 0x5F, 0xD8, 0x27, 0xFC, 0x30, 0x0F,
+	0xEC, 0x21, 0xFF, 0x00, 0x46, 0x51, 0xF0, 0x8F, 0xFF, 0x00, 0x0D, 0xBE, 0x97, 0xFF, 0x00, 0xC6,
+	0x28, 0xFF, 0x00, 0x86, 0x01, 0xFD, 0x84, 0x3F, 0xE8, 0xCA, 0x3E, 0x11, 0xFF, 0x00, 0xE1, 0xB7,
+	0xD2, 0xFF, 0x00, 0xF8, 0xC5, 0x01, 0xCC, 0xCF, 0xE3, 0xE8, 0x6B, 0x8E, 0x3A, 0x3D, 0x1F, 0xDB,
+	0x8D, 0xFD, 0xEA, 0xFE, 0xC1, 0x7F, 0xE1, 0x80, 0x7F, 0x61, 0x0F, 0xFA, 0x32, 0x8F, 0x84, 0x7F,
+	0xF8, 0x6D, 0xF4, 0xBF, 0xFE, 0x31, 0x47, 0xFC, 0x30, 0x0F, 0xEC, 0x21, 0xFF, 0x00, 0x46, 0x51,
+	0xF0, 0x8F, 0xFF, 0x00, 0x0D, 0xBE, 0x97, 0xFF, 0x00, 0xC6, 0x28, 0x0E, 0x66, 0x7F, 0x1F, 0x7F,
+	0xDB, 0x8F, 0xFD, 0xFA, 0x4F, 0xED, 0xB6, 0xFE, 0xF5, 0x7F, 0x60, 0xBF, 0xF0, 0xC0, 0x3F, 0xB0,
+	0x87, 0xFD, 0x19, 0x47, 0xC2, 0x3F, 0xFC, 0x36, 0xFA, 0x5F, 0xFF, 0x00, 0x18, 0xA3, 0xFE, 0x18,
+	0x07, 0xF6, 0x10, 0xFF, 0x00, 0xA3, 0x28, 0xF8, 0x47, 0xFF, 0x00, 0x86, 0xDF, 0x4B, 0xFF, 0x00,
+	0xE3, 0x14, 0x07, 0x33, 0x3F, 0x8F, 0xBF, 0xED, 0xC7, 0xE9, 0xBE, 0x8F, 0xED, 0xC6, 0x27, 0x96,
+	0xCD, 0x7F, 0x60, 0x9F, 0xF0, 0xC0, 0x3F, 0xB0, 0x87, 0xFD, 0x19, 0x47, 0xC2, 0x3F, 0xFC, 0x36,
+	0xFA, 0x5F, 0xFF, 0x00, 0x18, 0xA6, 0xCD, 0xFB, 0x01, 0xFE, 0xC2, 0x2B, 0x13, 0x32, 0xFE, 0xC5,
+	0x3F, 0x09, 0x01, 0x0A, 0x70, 0x7F, 0xE1, 0x5B, 0xE9, 0x7F, 0xFC, 0x62, 0x80, 0xE6, 0x67, 0xF2,
+	0x45, 0xF0, 0x6B, 0xE1, 0xA7, 0xC4, 0xCF, 0xDA, 0x0B, 0xE2, 0x5E, 0x8B, 0xF0, 0x73, 0xE1, 0x0F,
+	0x85, 0x2F, 0xB5, 0xBF, 0x10, 0xF8, 0x83, 0x50, 0x86, 0xC7, 0x4D, 0xD3, 0xB4, 0xFB, 0x73, 0x24,
+	0x92, 0xC8, 0xEC, 0x14, 0x60, 0x28, 0x27, 0xA9, 0xF4, 0xAF, 0xED, 0xD3, 0xF6, 0x5D, 0xF8, 0x13,
+	0x3F, 0xC0, 0xFF, 0x00, 0xD9, 0x9B, 0xE1, 0xD7, 0xC1, 0x5D, 0x66, 0xF1, 0x66, 0xBC, 0xF0, 0x7F,
+	0x81, 0x74, 0x8D, 0x12, 0xEE, 0x68, 0x26, 0xF9, 0x1E, 0x4B, 0x4B, 0x28, 0xA0, 0x66, 0x5E, 0x3A,
+	0x13, 0x19, 0xC7, 0xB5, 0x70, 0xFF, 0x00, 0xB2, 0x2F, 0xEC, 0xAD, 0xFB, 0x30, 0x7C, 0x24, 0xF1,
+	0x6E, 0xA5, 0xE2, 0xEF, 0x85, 0x3F, 0xB3, 0x87, 0x80, 0xBC, 0x33, 0xAB, 0x47, 0x6A, 0x91, 0xA6,
+	0xA9, 0xE1, 0xEF, 0x07, 0xD9, 0x59, 0x5C, 0x2A, 0x30, 0x21, 0x94, 0x49, 0x0C, 0x4A, 0xC0, 0x11,
+	0xC1, 0x19, 0xC1, 0xAF, 0xA1, 0xE8, 0x24, 0xFF, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60,
+	0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x22, 0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D,
+	0x00, 0x2A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x01, 0x12, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x02, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x04, 0x03, 0x02, 0x02,
+	0x02, 0x02, 0x05, 0x04, 0x04, 0x03, 0x04, 0x06, 0x05, 0x06, 0x06, 0x06, 0x05, 0x06, 0x06, 0x06,
+	0x07, 0x09, 0x08, 0x06, 0x07, 0x09, 0x07, 0x06, 0x06, 0x08, 0x0B, 0x08, 0x09, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x06, 0x08, 0x0B, 0x0C, 0x0B, 0x0A, 0x0C, 0x09, 0x0A, 0x0A, 0x0A, 0xFF, 0xDB, 0x00,
+	0x43, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x05, 0x03, 0x03, 0x05, 0x0A, 0x07, 0x06, 0x07,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00, 0x38, 0x00, 0x37, 0x03, 0x01, 0x22, 0x00, 0x02,
+	0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00, 0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+	0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03,
+	0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04,
+	0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81,
+	0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82,
+	0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36,
+	0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
+	0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76,
+	0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95,
+	0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3,
+	0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA,
+	0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
+	0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00,
+	0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4,
+	0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00,
+	0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51,
+	0x07, 0x61, 0x71, 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23,
+	0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18,
+	0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45,
+	0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65,
+	0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84,
+	0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2,
+	0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9,
+	0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7,
+	0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5,
+	0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11,
+	0x00, 0x3F, 0x00, 0xF5, 0x4F, 0xD9, 0x4F, 0xF6, 0x55, 0xD7, 0x3F, 0xE0, 0xE0, 0xAD, 0x7B, 0xE2,
+	0x77, 0xED, 0xA7, 0xFB, 0x67, 0xFE, 0xD3, 0x5E, 0x3C, 0xD0, 0x3E, 0x1C, 0x68, 0x1E, 0x3C, 0xBD,
+	0xF0, 0xBF, 0x80, 0x7E, 0x1F, 0xF8, 0x27, 0x56, 0x4B, 0x08, 0xE2, 0x86, 0xD8, 0x43, 0x30, 0xB8,
+	0x9C, 0xC9, 0x14, 0xAA, 0xC3, 0x65, 0xCA, 0x2A, 0xA6, 0xC3, 0x27, 0x9B, 0xE6, 0xE6, 0x42, 0xA5,
+	0x50, 0xFA, 0x84, 0xFF, 0x00, 0xF0, 0x6C, 0xE7, 0xFC, 0x13, 0x70, 0x73, 0x6B, 0xF1, 0x6B, 0xE3,
+	0xA4, 0x83, 0x3F, 0xF2, 0xD3, 0xC7, 0x56, 0x4B, 0x91, 0xEB, 0xFF, 0x00, 0x1E, 0x06, 0xB0, 0xBF,
+	0xE0, 0xDC, 0x6D, 0x5E, 0xE6, 0xCF, 0xFE, 0x09, 0xF5, 0xAC, 0x69, 0x71, 0xBB, 0x79, 0x77, 0x5F,
+	0x1D, 0x7C, 0x48, 0xCC, 0xA3, 0xA1, 0x65, 0xB4, 0xD2, 0xC0, 0x3F, 0x80, 0x76, 0x1F, 0x8D, 0x7E,
+	0x84, 0xF9, 0x52, 0x91, 0x9E, 0x6B, 0xA2, 0xA5, 0x49, 0x42, 0x6E, 0x31, 0x7A, 0x1C, 0xB4, 0xE8,
+	0xD2, 0xAB, 0x49, 0x4A, 0x4A, 0xF7, 0x3E, 0x0F, 0x1F, 0xF0, 0x6C, 0xEF, 0xFC, 0x13, 0x97, 0xFE,
+	0x8A, 0xAF, 0xC7, 0x0F, 0xFC, 0x2F, 0xAC, 0xFF, 0x00, 0xF9, 0x5F, 0x47, 0xFC, 0x43, 0x3B, 0xFF,
+	0x00, 0x04, 0xE5, 0xFF, 0x00, 0xA2, 0xAB, 0xF1, 0xC3, 0xFF, 0x00, 0x0B, 0xEB, 0x3F, 0xFE, 0x57,
+	0xD7, 0xD1, 0x5F, 0x10, 0x3F, 0xE0, 0xA1, 0xBF, 0xB0, 0xA7, 0xC2, 0xCD, 0x7E, 0x6F, 0x0A, 0xFC,
+	0x42, 0xFD, 0xAE, 0xFE, 0x1F, 0xE9, 0x7A, 0x95, 0xB4, 0x9E, 0x5D, 0xCD, 0x8D, 0xC7, 0x8A, 0x2D,
+	0xCC, 0x90, 0xBF, 0xF7, 0x1D, 0x55, 0x8E, 0xD6, 0xFF, 0x00, 0x64, 0xE0, 0xFB, 0x56, 0x0B, 0x7F,
+	0xC1, 0x56, 0x7F, 0xE0, 0x9B, 0x48, 0x3E, 0x7F, 0xDB, 0x5F, 0xE1, 0xEA, 0xFF, 0x00, 0xB4, 0xDE,
+	0x20, 0x8C, 0x01, 0x53, 0xCD, 0x88, 0xF3, 0x23, 0xD8, 0xE0, 0x57, 0x45, 0xF7, 0x9E, 0x27, 0xFF,
+	0x00, 0x10, 0xCE, 0xFF, 0x00, 0xC1, 0x39, 0xBF, 0xE8, 0xAA, 0xFC, 0x70, 0xFF, 0x00, 0xC2, 0xFA,
+	0xCF, 0xFF, 0x00, 0x95, 0xF5, 0x35, 0x9F, 0xFC, 0x1B, 0x35, 0xFF, 0x00, 0x04, 0xD6, 0x9A, 0x41,
+	0x15, 0xEF, 0xC6, 0x0F, 0x8E, 0x90, 0x6E, 0xFF, 0x00, 0x96, 0x9F, 0xF0, 0x9C, 0x59, 0x32, 0x8F,
+	0xA9, 0xFB, 0x06, 0x7F, 0x4A, 0xE6, 0xFF, 0x00, 0xE0, 0x9D, 0xDF, 0xF0, 0x5E, 0xCF, 0x84, 0x3F,
+	0xB4, 0x6E, 0xAF, 0x1F, 0xC1, 0xBF, 0xDA, 0x88, 0x69, 0x7E, 0x05, 0xF1, 0x93, 0x6A, 0x0D, 0x67,
+	0xA3, 0xEB, 0x91, 0xDC, 0x18, 0xF4, 0x7F, 0x10, 0x7E, 0xF0, 0x22, 0x14, 0xF3, 0x4E, 0xFB, 0x29,
+	0xDC, 0xB0, 0x02, 0x09, 0x4B, 0x06, 0xEA, 0x92, 0x36, 0xE0, 0xA3, 0xF4, 0x2A, 0x45, 0x73, 0x6F,
+	0xE6, 0x21, 0xDC, 0x0A, 0xE4, 0x1E, 0xA0, 0xD1, 0x29, 0x56, 0xA7, 0x2B, 0x36, 0x5D, 0x18, 0xE1,
+	0x6B, 0x46, 0xF0, 0x49, 0x9F, 0x99, 0x1F, 0x19, 0xB4, 0xDF, 0x1C, 0x7F, 0xC1, 0xB8, 0x7F, 0xB5,
+	0x6F, 0xC3, 0xBB, 0x9F, 0x85, 0x1F, 0xB4, 0x07, 0x8B, 0xBC, 0x7D, 0xF0, 0x43, 0xE2, 0xD6, 0x9F,
+	0xAB, 0x41, 0x7D, 0xE1, 0x4F, 0x1B, 0x5F, 0x0B, 0xFB, 0x8D, 0x22, 0xE6, 0xC6, 0xDE, 0x39, 0x15,
+	0xE3, 0x78, 0xD6, 0x35, 0x75, 0x69, 0x6E, 0x22, 0x29, 0xE5, 0xAC, 0x65, 0x57, 0xCF, 0x12, 0x19,
+	0x32, 0xAD, 0x45, 0x62, 0x7F, 0xC1, 0xCC, 0xFE, 0x22, 0x9F, 0xC4, 0x3E, 0x1E, 0xFD, 0x9B, 0x4D,
+	0xC2, 0x9D, 0xD6, 0x7E, 0x22, 0xF1, 0x7D, 0xB2, 0xB3, 0x31, 0x25, 0x94, 0x5A, 0x69, 0xCC, 0x3F,
+	0x20, 0xD8, 0x1E, 0xC0, 0x51, 0x5D, 0xB4, 0x69, 0xFB, 0x5A, 0x6A, 0x4F, 0xFA, 0xD4, 0xE3, 0xAD,
+	0x51, 0x52, 0xAC, 0xE2, 0xBF, 0xAD, 0x11, 0xE9, 0x3F, 0xF0, 0x6E, 0x0C, 0x1E, 0x7F, 0xEC, 0x2F,
+	0xA8, 0x2E, 0x33, 0x8F, 0x8E, 0x1E, 0x25, 0xE3, 0xFE, 0xDD, 0x34, 0x7A, 0xF2, 0xBF, 0xF8, 0x39,
+	0x1F, 0xF6, 0xFD, 0xF8, 0x8D, 0xE0, 0xFF, 0x00, 0x18, 0x69, 0xFF, 0x00, 0xB0, 0x47, 0xC2, 0xBD,
+	0x62, 0xE3, 0x4B, 0xD3, 0x2F, 0x3C, 0x2F, 0x0E, 0xB3, 0xE3, 0xED, 0x43, 0x4F, 0xBD, 0xF2, 0x65,
+	0xBD, 0x8E, 0xE6, 0x59, 0xE1, 0x87, 0x4B, 0x66, 0x1F, 0x76, 0x26, 0x8E, 0x19, 0x24, 0x95, 0x7A,
+	0xB8, 0x96, 0x15, 0x1D, 0x4E, 0x7D, 0x63, 0xFE, 0x0D, 0xB8, 0x75, 0x4F, 0xD8, 0x6B, 0x52, 0x2C,
+	0xDF, 0xF3, 0x5C, 0x3C, 0x49, 0xFF, 0x00, 0xA4, 0x9A, 0x3D, 0x7D, 0xAB, 0xF1, 0x57, 0xF6, 0x23,
+	0xFD, 0x8D, 0x7E, 0x38, 0x78, 0xE6, 0x5F, 0x89, 0xBF, 0x18, 0xBF, 0x66, 0xEF, 0x06, 0xF8, 0x9B,
+	0xC4, 0x13, 0x5B, 0xA5, 0xBC, 0xDA, 0xC6, 0xB5, 0xA0, 0xC3, 0x71, 0x70, 0xD1, 0x22, 0x95, 0x54,
+	0x2C, 0xE0, 0x9C, 0x05, 0x38, 0x1E, 0xD5, 0xCC, 0xE6, 0xA8, 0xE2, 0x9C, 0xAD, 0xB3, 0x3A, 0x3D,
+	0x8C, 0xAB, 0x60, 0x95, 0x38, 0x3E, 0x8B, 0xEE, 0x3F, 0x9E, 0x1F, 0xD9, 0x33, 0xFE, 0x09, 0x27,
+	0xFB, 0x76, 0x7E, 0xD7, 0xFF, 0x00, 0x0C, 0x57, 0xE2, 0xCF, 0xC0, 0x1F, 0x84, 0x96, 0xAD, 0xE1,
+	0x99, 0x2E, 0xBC, 0xAD, 0x3F, 0x50, 0xD4, 0xB5, 0xCB, 0x7B, 0x18, 0x6E, 0xF6, 0x13, 0x1B, 0x98,
+	0x56, 0x4F, 0x99, 0x80, 0xF9, 0xB2, 0xDE, 0xA3, 0xD6, 0xBD, 0x4A, 0x4F, 0xF8, 0x37, 0x9B, 0xFE,
+	0x0A, 0x9C, 0x4E, 0x57, 0xE1, 0x77, 0x87, 0x7E, 0xAB, 0xE3, 0x7B, 0x3C, 0x8F, 0xA6, 0x7B, 0xD7,
+	0xF4, 0x05, 0xE0, 0xEF, 0x0E, 0x7C, 0x2F, 0xF8, 0x43, 0xE1, 0xAD, 0x17, 0xE1, 0x6F, 0x81, 0x34,
+	0xAD, 0x27, 0xC3, 0xBA, 0x55, 0xA4, 0x06, 0xD7, 0x41, 0xD0, 0x74, 0xF8, 0xA3, 0xB7, 0x89, 0x23,
+	0x45, 0xDC, 0x52, 0x18, 0x86, 0x33, 0x81, 0x96, 0x38, 0x19, 0xEA, 0x4F, 0x73, 0x5B, 0x9E, 0x7D,
+	0xB7, 0xFC, 0xF6, 0xFD, 0x2B, 0x7F, 0xED, 0x3C, 0x45, 0xF4, 0xB1, 0x8C, 0x72, 0x9C, 0x32, 0x8D,
+	0x9D, 0xCF, 0xE5, 0x9F, 0xF6, 0x3B, 0xFD, 0x80, 0x7F, 0x68, 0xAF, 0xDB, 0x9F, 0xE2, 0x9D, 0xD7,
+	0xC2, 0x5F, 0x82, 0x3E, 0x02, 0xFB, 0x50, 0xD2, 0xAF, 0x16, 0x0F, 0x16, 0x6B, 0x1A, 0xA4, 0x8F,
+	0x1E, 0x99, 0xA4, 0x07, 0x24, 0x31, 0x9E, 0x5D, 0xAC, 0x10, 0x82, 0xA4, 0x8B, 0x58, 0xC1, 0x62,
+	0x06, 0x40, 0x39, 0xC5, 0x7F, 0x44, 0xFF, 0x00, 0xB0, 0x2F, 0xEC, 0x7D, 0xE2, 0x2F, 0xD8, 0xB7,
+	0xF6, 0x5C, 0xD2, 0x3E, 0x04, 0x78, 0xA7, 0xE3, 0x86, 0xB9, 0xE3, 0xEB, 0xDD, 0x3D, 0x59, 0xE5,
+	0xD5, 0x35, 0x85, 0x55, 0x8A, 0xD8, 0xB0, 0x1F, 0xE8, 0xD6, 0x91, 0xFC, 0xCF, 0x15, 0xB2, 0x63,
+	0x08, 0x8F, 0x24, 0x8C, 0x3E, 0x63, 0xBB, 0xE6, 0xC0, 0xF4, 0x4F, 0x87, 0xBE, 0x05, 0xF8, 0x1B,
+	0xFB, 0x37, 0x78, 0x07, 0x4F, 0xF8, 0x73, 0xF0, 0xE7, 0x42, 0xD0, 0xFC, 0x1F, 0xE1, 0xDB, 0x59,
+	0x19, 0x34, 0xFD, 0x32, 0xCD, 0x63, 0xB5, 0x80, 0x3B, 0x12, 0xED, 0x80, 0x48, 0xDC, 0xC7, 0xE6,
+	0x62, 0x79, 0x27, 0x92, 0x6B, 0xA4, 0xD3, 0x7C, 0x49, 0xE1, 0xDD, 0x6E, 0xDA, 0xE1, 0xB4, 0x4D,
+	0x76, 0xD6, 0xF0, 0x42, 0xC5, 0x26, 0xFB, 0x2D, 0xC2, 0xC9, 0xE5, 0xBE, 0x33, 0xB5, 0xB6, 0x93,
+	0x83, 0x83, 0x9C, 0x1E, 0x6B, 0x0C, 0x46, 0x2A, 0xA6, 0x21, 0xEA, 0x74, 0x61, 0x70, 0x74, 0xF0,
+	0xB1, 0xB4, 0x4F, 0xC8, 0x6F, 0xF8, 0x39, 0x3E, 0x3F, 0x2B, 0x45, 0xFD, 0x9F, 0x53, 0xFE, 0xA7,
+	0x0F, 0x18, 0xFF, 0x00, 0xE9, 0x0E, 0x99, 0x45, 0x49, 0xFF, 0x00, 0x07, 0x2B, 0x3A, 0xBE, 0x93,
+	0xFB, 0x3E, 0x95, 0x3F, 0xF3, 0x38, 0x78, 0xC7, 0xFF, 0x00, 0x48, 0x74, 0xCA, 0x2B, 0xBB, 0x0B,
+	0xFE, 0xEE, 0xBE, 0x7F, 0x99, 0xC7, 0x8A, 0xFF, 0x00, 0x78, 0x97, 0xCB, 0xF2, 0x47, 0x7B, 0xFF,
+	0x00, 0x06, 0xF4, 0xEA, 0xEB, 0xA5, 0x7E, 0xC2, 0xB7, 0x79, 0x7D, 0xBE, 0x67, 0xC7, 0x0F, 0x13,
+	0x7E, 0x96, 0x9A, 0x3F, 0xF8, 0xD7, 0xAE, 0xFF, 0x00, 0xC1, 0x4C, 0x3F, 0xE0, 0xB0, 0x3F, 0x0D,
+	0xFF, 0x00, 0xE0, 0x9F, 0x1A, 0x6D, 0x97, 0x84, 0x13, 0xC2, 0x1A, 0x97, 0x89, 0x3C, 0x75, 0xE2,
+	0x0D, 0x32, 0x5B, 0xBD, 0x07, 0x4C, 0xFB, 0x3C, 0x90, 0xE9, 0xF0, 0x46, 0xA4, 0xA0, 0xB8, 0xBA,
+	0xBA, 0x2B, 0xB7, 0x67, 0x98, 0x36, 0xF9, 0x51, 0x6F, 0x95, 0x89, 0x00, 0x88, 0xD5, 0xBC, 0xD5,
+	0xF9, 0xD7, 0xFE, 0x08, 0xAC, 0xBE, 0x2B, 0xF0, 0xF7, 0xFC, 0x13, 0x43, 0x50, 0xF8, 0xA7, 0xA4,
+	0x5B, 0xAC, 0xDA, 0x5E, 0x83, 0xF1, 0xF3, 0xC4, 0x51, 0xEB, 0x6A, 0x99, 0xF3, 0x22, 0x8E, 0x6B,
+	0x3D, 0x27, 0x6C, 0xD8, 0xC7, 0x28, 0xAD, 0x1E, 0xD6, 0xEA, 0x47, 0x98, 0xA7, 0x18, 0x0C, 0x47,
+	0xD3, 0x5F, 0x19, 0x74, 0x2F, 0xD9, 0xB3, 0xF6, 0xB2, 0xF8, 0x65, 0x27, 0xC3, 0xBF, 0x8D, 0xDE,
+	0x1D, 0xD1, 0x7C, 0x49, 0xA2, 0xDD, 0x2E, 0xF5, 0xB7, 0xBF, 0x5F, 0xDE, 0x5B, 0x49, 0xB4, 0xA8,
+	0x9A, 0x09, 0x46, 0x24, 0x82, 0x50, 0x18, 0xE2, 0x48, 0xD9, 0x5C, 0x64, 0xE0, 0xF2, 0x6B, 0xCD,
+	0x93, 0x8F, 0xB7, 0x6E, 0x5B, 0x5C, 0xEE, 0xA2, 0xA4, 0xF0, 0x69, 0x47, 0x7B, 0x1F, 0x8E, 0x3E,
+	0x1B, 0xFF, 0x00, 0x82, 0xB4, 0x7E, 0xD4, 0xED, 0xFB, 0x6A, 0xE9, 0x7F, 0xB7, 0x37, 0x8F, 0x7C,
+	0x45, 0x6F, 0xE3, 0x4D, 0x73, 0xC3, 0xB0, 0x5D, 0xDB, 0xE9, 0x1E, 0x19, 0xD4, 0x2E, 0xA5, 0x8F,
+	0x4A, 0xD3, 0xA1, 0xBA, 0xB6, 0x6B, 0x79, 0x16, 0xDA, 0xDE, 0x32, 0x0C, 0x58, 0x0C, 0x0B, 0x3F,
+	0x56, 0xC6, 0x4E, 0x6B, 0xE9, 0x65, 0xFF, 0x00, 0x83, 0x9E, 0xFF, 0x00, 0x6A, 0x5C, 0xF3, 0xFB,
+	0x38, 0x78, 0x08, 0x7B, 0xFD, 0xB2, 0xF8, 0xE3, 0xF0, 0xDD, 0xCD, 0x50, 0xD2, 0xBF, 0xE0, 0x8A,
+	0xBE, 0x06, 0xF0, 0x8F, 0xED, 0x7F, 0xA3, 0xFF, 0x00, 0x6A, 0x78, 0xA1, 0x7C, 0x5F, 0xF0, 0x4F,
+	0x50, 0x86, 0xF0, 0xEA, 0x11, 0xB6, 0xBE, 0xD6, 0x5A, 0xBE, 0x95, 0x2F, 0x93, 0x2B, 0x41, 0x1C,
+	0xEC, 0x8C, 0x9F, 0x68, 0x88, 0x48, 0x21, 0x0B, 0x2C, 0x24, 0x48, 0x58, 0x91, 0x24, 0x7B, 0x01,
+	0x73, 0xF4, 0x29, 0xFF, 0x00, 0x82, 0x3E, 0xFF, 0x00, 0xC1, 0x2D, 0xF1, 0x81, 0xE0, 0xAD, 0x51,
+	0xBF, 0xBD, 0xBB, 0xC7, 0xBA, 0x9F, 0x4F, 0xC2, 0x7A, 0xEF, 0xA9, 0x53, 0x2F, 0x7B, 0x23, 0xCF,
+	0xA7, 0x87, 0xCD, 0x23, 0xBC, 0xD1, 0xF9, 0xC1, 0xFF, 0x00, 0x05, 0x01, 0xFF, 0x00, 0x82, 0x9D,
+	0x7E, 0xD1, 0x5F, 0xF0, 0x51, 0x7D, 0x57, 0x41, 0x93, 0xE2, 0x46, 0x9B, 0xA3, 0xE9, 0x1A, 0x5F,
+	0x86, 0xC4, 0xCD, 0xA3, 0x78, 0x77, 0x41, 0x8E, 0x66, 0x88, 0x5D, 0x4C, 0xBE, 0x5B, 0xCA, 0xC2,
+	0x42, 0x5A, 0x79, 0xB6, 0x05, 0xD8, 0x31, 0xC0, 0x69, 0x40, 0xC0, 0x66, 0xCF, 0xEA, 0xEF, 0xFC,
+	0x10, 0x6B, 0xF6, 0x63, 0xF1, 0x8F, 0xEC, 0x95, 0xFB, 0x1E, 0x6A, 0xDE, 0x21, 0xF8, 0x99, 0xA6,
+	0xCB, 0xA6, 0xEB, 0xDF, 0x11, 0xBC, 0x49, 0x26, 0xBC, 0xDA, 0x5D, 0xC2, 0x94, 0x9A, 0xCE, 0xCC,
+	0x5B, 0xC5, 0x05, 0xBA, 0x4C, 0x9D, 0x16, 0x47, 0xF2, 0xE5, 0xB8, 0x2A, 0x3E, 0xE8, 0xB9, 0x54,
+	0x38, 0x28, 0x40, 0x6F, 0xC1, 0x8F, 0xD8, 0x1F, 0xFE, 0x09, 0xD1, 0xF0, 0x17, 0xC4, 0x76, 0xBE,
+	0x31, 0xF0, 0x27, 0xC1, 0x8D, 0x06, 0x7D, 0x62, 0xC2, 0x44, 0x93, 0x4F, 0xD4, 0xF5, 0xEB, 0xC9,
+	0xB5, 0x39, 0x6D, 0x1D, 0x3E, 0xE3, 0xC3, 0xF6, 0xB7, 0x91, 0x62, 0x75, 0xE7, 0x0E, 0x81, 0x58,
+	0x64, 0xF3, 0xCD, 0x7B, 0x5F, 0x8D, 0x3E, 0x3F, 0xF8, 0x57, 0xC2, 0xFA, 0x2C, 0xD7, 0xD3, 0xEB,
+	0xB0, 0xB3, 0x05, 0x21, 0x56, 0x36, 0x24, 0xF4, 0xF6, 0x06, 0xB9, 0xB1, 0x18, 0x8A, 0x75, 0x29,
+	0xA8, 0x41, 0x59, 0x23, 0xAB, 0x0B, 0x85, 0xA9, 0x4E, 0xA3, 0xA9, 0x52, 0x57, 0x6C, 0xF8, 0x87,
+	0xFE, 0x0E, 0x32, 0xBB, 0x17, 0xDE, 0x10, 0xFD, 0x9D, 0xEE, 0xD5, 0xF7, 0x79, 0x9E, 0x30, 0xF1,
+	0x91, 0xFF, 0x00, 0xC9, 0x3D, 0x30, 0x51, 0x55, 0xFF, 0x00, 0xE0, 0xE0, 0xFF, 0x00, 0x0D, 0xF8,
+	0xAB, 0xC3, 0xDF, 0x05, 0x7F, 0x65, 0x69, 0x7C, 0x71, 0xA2, 0xDC, 0xE9, 0xBA, 0xB6, 0xA5, 0xAD,
+	0x78, 0xCA, 0xFA, 0xF3, 0x4F, 0xBC, 0x5D, 0xB2, 0x5B, 0x89, 0x21, 0xB1, 0xF2, 0x95, 0x97, 0xEF,
+	0x23, 0x79, 0x42, 0x32, 0xC8, 0xDF, 0x32, 0xB1, 0x60, 0xC1, 0x48, 0x2A, 0x0A, 0xEC, 0xC2, 0xFF,
+	0x00, 0xBB, 0xAF, 0x9F, 0xE6, 0x73, 0xE2, 0xBF, 0xDE, 0x25, 0xF2, 0xFC, 0x91, 0xBF, 0xF0, 0x1F,
+	0xE3, 0x6A, 0xFF, 0x00, 0xC1, 0x0E, 0xA7, 0xF8, 0xAD, 0xFB, 0x0A, 0xFE, 0xDE, 0x1F, 0xB3, 0x97,
+	0xC4, 0x3D, 0x73, 0xE1, 0xB7, 0x88, 0x3C, 0x65, 0x7D, 0xE2, 0x1F, 0x04, 0xF8, 0xEB, 0xE1, 0xFE,
+	0x9A, 0xB7, 0x90, 0xDD, 0xDB, 0x5D, 0x2C, 0x36, 0xC6, 0xD6, 0x74, 0x92, 0x48, 0x80, 0x42, 0x96,
+	0xF1, 0x90, 0xC4, 0xB3, 0x19, 0x3C, 0xE0, 0xC0, 0xAE, 0x08, 0xE5, 0xFC, 0x45, 0xFF, 0x00, 0x05,
+	0x31, 0xFF, 0x00, 0x82, 0x3E, 0xEA, 0x6F, 0x23, 0x78, 0x6F, 0x41, 0xFD, 0xA7, 0x34, 0x30, 0xCC,
+	0x59, 0x52, 0xCF, 0xC2, 0x7A, 0x7C, 0xAA, 0xBE, 0xC0, 0x4D, 0x78, 0xD8, 0x1E, 0xDD, 0x07, 0xA5,
+	0x14, 0x57, 0x1C, 0x29, 0xC6, 0xB3, 0xBC, 0xBA, 0x95, 0x3C, 0x45, 0x4A, 0x3E, 0xEC, 0x7A, 0x1C,
+	0x9D, 0xEF, 0xED, 0xFF, 0x00, 0xFF, 0x00, 0x04, 0xD3, 0x99, 0xF7, 0x69, 0xFF, 0x00, 0x17, 0xFF,
+	0x00, 0x6B, 0x0B, 0x5F, 0xF6, 0x47, 0xC3, 0x8D, 0x05, 0xF1, 0xF4, 0xCC, 0xF5, 0x59, 0x7F, 0x6F,
+	0x7F, 0xF8, 0x27, 0x38, 0x7D, 0xC7, 0xE3, 0xC7, 0xED, 0x61, 0xFF, 0x00, 0x86, 0xBF, 0xC3, 0xFF,
+	0x00, 0xFC, 0x7E, 0x8A, 0x2B, 0xB3, 0xEA, 0x74, 0x7C, 0xC9, 0xFA, 0xE5, 0x63, 0x43, 0x4E, 0xFF,
+	0x00, 0x82, 0x83, 0x7F, 0xC1, 0x30, 0xED, 0x99, 0x4E, 0xA3, 0xF1, 0x33, 0xF6, 0xAE, 0xBC, 0x55,
+	0x6C, 0x95, 0x93, 0xE1, 0xDE, 0x84, 0xB9, 0xFF, 0x00, 0xBE, 0x67, 0xAE, 0xF3, 0xC0, 0x5F, 0xF0,
+	0x55, 0x2F, 0xF8, 0x23, 0x4F, 0x83, 0x75, 0x6B, 0x7D, 0x73, 0x56, 0xF8, 0x75, 0xFB, 0x49, 0x6B,
+	0xD7, 0x56, 0xCC, 0x1A, 0x17, 0xD5, 0x3C, 0x2B, 0x63, 0xB5, 0x58, 0x32, 0xB2, 0xB8, 0x44, 0xBD,
+	0x55, 0x0C, 0xA5, 0x46, 0x1B, 0x19, 0x1C, 0xE0, 0xF2, 0x72, 0x51, 0x4B, 0xEA, 0x74, 0x47, 0xF5,
+	0xCA, 0xC7, 0x47, 0xE3, 0xFB, 0x1F, 0x18, 0xFF, 0x00, 0xC1, 0xC3, 0xDF, 0xB5, 0x27, 0xC3, 0xBD,
+	0x2B, 0xE0, 0xC7, 0xC0, 0x2F, 0x19, 0x78, 0x1F, 0xE0, 0x6F, 0xC2, 0x3D, 0x3F, 0x56, 0xB8, 0xBE,
+	0xF1, 0x6F, 0x8F, 0xAD, 0x7E, 0xC7, 0x75, 0xAC, 0x5E, 0x5F, 0x5B, 0x46, 0x8A, 0xA8, 0xAA, 0xF2,
+	0x2A, 0xA2, 0xBC, 0x28, 0x13, 0xCB, 0x69, 0x4B, 0x62, 0x73, 0x20, 0x8F, 0x6A, 0x80, 0x51, 0x45,
+	0x70, 0x4E, 0xA4, 0xA9, 0xCB, 0x96, 0x3B, 0x23, 0xBE, 0x14, 0xE3, 0x52, 0x3C, 0xD2, 0xDD, 0x9F,
+	0xFF, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46,
+	0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60, 0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x22,
+	0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D, 0x00, 0x2A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01,
+	0x01, 0x12, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xFF, 0xDB, 0x00, 0x43, 0x00, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x02,
+	0x02, 0x02, 0x02, 0x02, 0x04, 0x03, 0x02, 0x02, 0x02, 0x02, 0x05, 0x04, 0x04, 0x03, 0x04, 0x06,
+	0x05, 0x06, 0x06, 0x06, 0x05, 0x06, 0x06, 0x06, 0x07, 0x09, 0x08, 0x06, 0x07, 0x09, 0x07, 0x06,
+	0x06, 0x08, 0x0B, 0x08, 0x09, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x06, 0x08, 0x0B, 0x0C, 0x0B, 0x0A,
+	0x0C, 0x09, 0x0A, 0x0A, 0x0A, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+	0x05, 0x03, 0x03, 0x05, 0x0A, 0x07, 0x06, 0x07, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00,
+	0x38, 0x00, 0x37, 0x03, 0x01, 0x22, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00,
+	0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4,
+	0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00,
+	0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13,
+	0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15,
+	0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25,
+	0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46,
+	0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66,
+	0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86,
+	0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4,
+	0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2,
+	0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9,
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+	0xFC, 0x54, 0x2C, 0xFE, 0x32, 0x78, 0x83, 0xC7, 0x97, 0xBE, 0x23, 0xD2, 0x3F, 0xB3, 0xB5, 0x1F,
+	0x0E, 0xE9, 0x3A, 0x7D, 0x8A, 0xC3, 0x70, 0xC6, 0x73, 0x25, 0xB4, 0xFA, 0x84, 0xB2, 0x99, 0x01,
+	0x40, 0x02, 0xFF, 0x00, 0xA5, 0xA0, 0x5C, 0x33, 0x67, 0x0D, 0x90, 0xBF, 0xC5, 0xA1, 0xE3, 0x4F,
+	0x8F, 0xFE, 0x15, 0xF0, 0xBE, 0x8B, 0x35, 0xF4, 0xFA, 0xEC, 0x2C, 0xC1, 0x48, 0x55, 0x8D, 0x89,
+	0x3D, 0x3D, 0x81, 0xA9, 0xC4, 0x4A, 0x32, 0xA8, 0x9A, 0xED, 0x1F, 0xC2, 0x29, 0x0E, 0x9C, 0x79,
+	0x63, 0x6F, 0x37, 0xF8, 0xB6, 0x7C, 0x43, 0xFF, 0x00, 0x07, 0x19, 0x5D, 0x8B, 0xEF, 0x08, 0x7E,
+	0xCE, 0xF7, 0x6A, 0xFB, 0xBC, 0xCF, 0x18, 0x78, 0xC8, 0xFF, 0x00, 0xE4, 0x9E, 0x98, 0x28, 0xAA,
+	0xFF, 0x00, 0xF0, 0x70, 0x7F, 0x86, 0xFC, 0x55, 0xE1, 0xEF, 0x82, 0xBF, 0xB2, 0xB4, 0xBE, 0x38,
+	0xD1, 0x6E, 0x74, 0xDD, 0x5B, 0x52, 0xD6, 0xBC, 0x65, 0x7D, 0x79, 0xA7, 0xDE, 0x2E, 0xD9, 0x2D,
+	0xC4, 0x90, 0xD8, 0xF9, 0x4A, 0xCB, 0xF7, 0x91, 0xBC, 0xA1, 0x19, 0x64, 0x6F, 0x99, 0x58, 0xB0,
+	0x60, 0xA4, 0x15, 0x05, 0x7A, 0x58, 0x5F, 0xF7, 0x75, 0xF3, 0xFC, 0xCF, 0x2F, 0x15, 0xFE, 0xF1,
+	0x2F, 0x97, 0xE4, 0x8D, 0xFF, 0x00, 0x80, 0xFF, 0x00, 0x1B, 0x57, 0xFE, 0x08, 0x75, 0x3F, 0xC5,
+	0x6F, 0xD8, 0x57, 0xF6, 0xF0, 0xFD, 0x9C, 0xBE, 0x21, 0xEB, 0x9F, 0x0D, 0xBC, 0x41, 0xE3, 0x2B,
+	0xEF, 0x10, 0xF8, 0x27, 0xC7, 0x5F, 0x0F, 0xF4, 0xD5, 0xBC, 0x86, 0xEE, 0xDA, 0xE9, 0x61, 0xB6,
+	0x36, 0xB3, 0xA4, 0x92, 0x44, 0x02, 0x14, 0xB7, 0x8C, 0x86, 0x25, 0x98, 0xC9, 0xE7, 0x06, 0x05,
+	0x70, 0x47, 0x2F, 0xE2, 0x2F, 0xF8, 0x29, 0x8F, 0xFC, 0x11, 0xF7, 0x53, 0x79, 0x1B, 0xC3, 0x7A,
+	0x0F, 0xED, 0x39, 0xA1, 0x86, 0x62, 0xCA, 0x96, 0x7E, 0x13, 0xD3, 0xE5, 0x55, 0xF6, 0x02, 0x6B,
+	0xC6, 0xC0, 0xF6, 0xE8, 0x3D, 0x28, 0xA2, 0xB8, 0xE1, 0x4E, 0x35, 0x9D, 0xE5, 0xD4, 0xA9, 0xE2,
+	0x2A, 0x51, 0xF7, 0x63, 0xD0, 0xE4, 0xEF, 0x7F, 0x6F, 0xFF, 0x00, 0xF8, 0x26, 0x9C, 0xCF, 0xBB,
+	0x4F, 0xF8, 0xBF, 0xFB, 0x58, 0x5A, 0xFF, 0x00, 0xB2, 0x3E, 0x1C, 0x68, 0x2F, 0x8F, 0xA6, 0x67,
+	0xAA, 0xCB, 0xFB, 0x7B, 0xFF, 0x00, 0xC1, 0x39, 0xC3, 0xEE, 0x3F, 0x1E, 0x3F, 0x6B, 0x0F, 0xFC,
+	0x35, 0xFE, 0x1F, 0xFF, 0x00, 0xE3, 0xF4, 0x51, 0x5D, 0x9F, 0x53, 0xA3, 0xE6, 0x4F, 0xD7, 0x2B,
+	0x1A, 0x1A, 0x77, 0xFC, 0x14, 0x1B, 0xFE, 0x09, 0x87, 0x6C, 0xCA, 0x75, 0x1F, 0x89, 0x9F, 0xB5,
+	0x75, 0xE2, 0xAB, 0x64, 0xAC, 0x9F, 0x0E, 0xF4, 0x25, 0xCF, 0xFD, 0xF3, 0x3D, 0x77, 0x9E, 0x02,
+	0xFF, 0x00, 0x82, 0xA9, 0x7F, 0xC1, 0x1A, 0x7C, 0x1B, 0xAB, 0x5B, 0xEB, 0x9A, 0xB7, 0xC3, 0xAF,
+	0xDA, 0x4B, 0x5E, 0xBA, 0xB6, 0x60, 0xD0, 0xBE, 0xA9, 0xE1, 0x5B, 0x1D, 0xAA, 0xC1, 0x95, 0x95,
+	0xC2, 0x25, 0xEA, 0xA8, 0x65, 0x2A, 0x30, 0xD8, 0xC8, 0xE7, 0x07, 0x93, 0x92, 0x8A, 0x5F, 0x53,
+	0xA2, 0x3F, 0xAE, 0x56, 0x3A, 0x3F, 0x1F, 0xD8, 0xF8, 0xC7, 0xFE, 0x0E, 0x1E, 0xFD, 0xA9, 0x3E,
+	0x1D, 0xE9, 0x5F, 0x06, 0x3E, 0x01, 0x78, 0xCB, 0xC0, 0xFF, 0x00, 0x03, 0x7E, 0x11, 0xE9, 0xFA,
+	0xB5, 0xC5, 0xF7, 0x8B, 0x7C, 0x7D, 0x6B, 0xF6, 0x3B, 0xAD, 0x62, 0xF2, 0xFA, 0xDA, 0x34, 0x55,
+	0x45, 0x57, 0x91, 0x55, 0x15, 0xE1, 0x40, 0x9E, 0x5B, 0x4A, 0x5B, 0x13, 0x99, 0x04, 0x7B, 0x54,
+	0x02, 0x8A, 0x2B, 0x82, 0x75, 0x25, 0x4E, 0x5C, 0xB1, 0xD9, 0x1D, 0xF0, 0xA7, 0x1A, 0x91, 0xE6,
+	0x96, 0xEC, 0xFF, 0xD9, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46,
+	0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60, 0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x46,
+	0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D, 0x00, 0x2A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x04,
+	0x01, 0x12, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x51, 0x10, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x51, 0x11, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x51, 0x12, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02,
+	0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x04, 0x03, 0x02, 0x02, 0x02, 0x02, 0x05, 0x04,
+	0x04, 0x03, 0x04, 0x06, 0x05, 0x06, 0x06, 0x06, 0x05, 0x06, 0x06, 0x06, 0x07, 0x09, 0x08, 0x06,
+	0x07, 0x09, 0x07, 0x06, 0x06, 0x08, 0x0B, 0x08, 0x09, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x06, 0x08,
+	0x0B, 0x0C, 0x0B, 0x0A, 0x0C, 0x09, 0x0A, 0x0A, 0x0A, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x02, 0x02,
+	0x02, 0x02, 0x02, 0x02, 0x05, 0x03, 0x03, 0x05, 0x0A, 0x07, 0x06, 0x07, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF, 0xC0,
+	0x00, 0x11, 0x08, 0x00, 0x49, 0x00, 0x26, 0x03, 0x01, 0x22, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11,
+	0x01, 0xFF, 0xC4, 0x00, 0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
+	0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, 0x05,
+	0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21,
+	0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1, 0x08, 0x23,
+	0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17,
+	0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A,
+	0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A,
+	0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A,
+	0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99,
+	0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7,
+	0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5,
+	0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF1,
+	0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00, 0x1F, 0x01, 0x00, 0x03,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x11, 0x00,
+	0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00, 0x01, 0x02, 0x77, 0x00,
+	0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, 0x13,
+	0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0, 0x15,
+	0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, 0x27,
+	0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
+	0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
+	0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88,
+	0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6,
+	0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4,
+	0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE2,
+	0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9,
+	0xFA, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3F, 0x00, 0xFC,
+	0xAD, 0xFD, 0x93, 0xFF, 0x00, 0xE0, 0x9B, 0xDF, 0x16, 0xBF, 0xE0, 0xA7, 0x5F, 0xB6, 0xF7, 0xC4,
+	0x6F, 0xD9, 0xF3, 0xE0, 0x9F, 0xC4, 0x9F, 0x01, 0x78, 0x4F, 0x51, 0xD1, 0x17, 0x57, 0xD7, 0xA4,
+	0xBE, 0xF8, 0x83, 0xAC, 0x5C, 0x58, 0xD8, 0xB5, 0xB4, 0x5A, 0x9C, 0x36, 0xC6, 0x18, 0xDE, 0x0B,
+	0x79, 0xD8, 0xCA, 0x5A, 0xEA, 0x36, 0x0A, 0x50, 0x02, 0xA8, 0xE7, 0x70, 0x20, 0x03, 0xE0, 0x3F,
+	0xB4, 0x17, 0xC1, 0x8F, 0x10, 0xFE, 0xCE, 0x3F, 0x1D, 0xBC, 0x65, 0xFB, 0x3F, 0x78, 0xBB, 0x5B,
+	0xD2, 0x75, 0x2D, 0x57, 0xC1, 0x1E, 0x28, 0xBF, 0xD0, 0xB5, 0x2D, 0x43, 0x41, 0xB9, 0x79, 0xAC,
+	0xAE, 0x67, 0xB4, 0xB8, 0x78, 0x1E, 0x58, 0x24, 0x74, 0x46, 0x78, 0x99, 0x90, 0x95, 0x66, 0x45,
+	0x25, 0x48, 0x25, 0x41, 0xE2, 0xBB, 0x4D, 0x1B, 0xC7, 0x77, 0xBF, 0x0D, 0xBF, 0x6D, 0xED, 0x53,
+	0xC5, 0xFA, 0x6F, 0xC0, 0xFF, 0x00, 0x0D, 0xFC, 0x48, 0xBA, 0x87, 0xC6, 0xDA, 0x9C, 0x16, 0x7E,
+	0x07, 0xF1, 0x76, 0x93, 0x73, 0x7F, 0x61, 0xAB, 0x4D, 0x3C, 0xB3, 0xC1, 0x1C, 0x6F, 0x6F, 0x6D,
+	0x2C, 0x52, 0xCA, 0xC1, 0xE5, 0x56, 0x45, 0x47, 0x07, 0xCC, 0x58, 0xFE, 0xF0, 0xCA, 0x9D, 0xAB,
+	0x3F, 0xF8, 0x25, 0x57, 0xFC, 0x15, 0x03, 0x56, 0xB3, 0x5D, 0x4F, 0x4D, 0xFF, 0x00, 0x82, 0x6F,
+	0xFC, 0x78, 0x9A, 0xDE, 0x45, 0x0D, 0x1C, 0xB0, 0xFC, 0x21, 0xD6, 0x99, 0x5D, 0x4F, 0x42, 0xA4,
+	0x5B, 0x7C, 0xC3, 0xE9, 0x40, 0x1E, 0xB5, 0xFF, 0x00, 0x05, 0x1A, 0xFF, 0x00, 0x82, 0x14, 0x7E,
+	0xD2, 0xDF, 0xF0, 0x4C, 0xBF, 0x80, 0x9A, 0x3F, 0xED, 0x0D, 0xF1, 0x8B, 0xE3, 0xFF, 0x00, 0xC1,
+	0xCF, 0x15, 0x69, 0x1A, 0xD7, 0x8A, 0x6D, 0xF4, 0x1B, 0x5D, 0x3F, 0xE1, 0xEF, 0x8A, 0x6F, 0x6F,
+	0xAF, 0x63, 0x9E, 0x6B, 0x5B, 0xAB, 0x95, 0x95, 0xD2, 0x7B, 0x28, 0x15, 0x61, 0x09, 0x6A, 0xEA,
+	0x58, 0x39, 0x21, 0x9D, 0x06, 0xD2, 0x09, 0x23, 0xFA, 0xA4, 0xFF, 0x00, 0x82, 0x4D, 0x8C, 0x7F,
+	0xC1, 0x2C, 0xFF, 0x00, 0x66, 0xB2, 0x4F, 0xFC, 0xD0, 0x1F, 0x06, 0xFF, 0x00, 0xE9, 0x8E, 0xCE,
+	0xBF, 0x8D, 0x8F, 0xDA, 0x6B, 0xFE, 0x16, 0x67, 0x85, 0x20, 0xF0, 0x9F, 0xC1, 0x7F, 0x8B, 0xDF,
+	0xB2, 0x8D, 0x87, 0xC2, 0xDD, 0x7B, 0xC2, 0x1A, 0x1F, 0xD9, 0xEE, 0x56, 0x4F, 0x09, 0xDF, 0x69,
+	0x3A, 0xB6, 0xB6, 0xAE, 0xE4, 0xAD, 0xDE, 0xA0, 0x97, 0x72, 0x13, 0x2C, 0xBF, 0x2B, 0x2A, 0xBA,
+	0x24, 0x6B, 0x8C, 0x8C, 0x1C, 0x57, 0xF6, 0x4F, 0xFF, 0x00, 0x04, 0x9D, 0xFF, 0x00, 0x94, 0x59,
+	0x7E, 0xCD, 0x5F, 0xF6, 0x40, 0x3C, 0x1B, 0xFF, 0x00, 0xA6, 0x3B, 0x3A, 0x00, 0xFA, 0x02, 0x8A,
+	0x28, 0xA0, 0x0F, 0xE6, 0x93, 0xE2, 0xFF, 0x00, 0xFC, 0x1C, 0x5D, 0xFB, 0x1A, 0xFF, 0x00, 0xC1,
+	0x3D, 0xB5, 0x2D, 0x53, 0xE1, 0x37, 0xFC, 0x10, 0xA7, 0xF6, 0x2E, 0xF0, 0x8C, 0x2B, 0x74, 0x65,
+	0x1E, 0x22, 0xF8, 0xDD, 0xF1, 0x07, 0x47, 0x9D, 0xF5, 0x1F, 0x11, 0x4D, 0x24, 0xB2, 0xC9, 0x2B,
+	0xA4, 0x45, 0xA3, 0xBA, 0x78, 0xF7, 0x94, 0x9A, 0x36, 0xB9, 0x95, 0x51, 0x0B, 0x34, 0x6B, 0x67,
+	0x12, 0x22, 0xE7, 0xE5, 0xE3, 0xFF, 0x00, 0x07, 0x46, 0xFF, 0x00, 0xC1, 0x75, 0x73, 0x91, 0xFB,
+	0x71, 0x01, 0xFF, 0x00, 0x74, 0xCF, 0xC3, 0x1C, 0xFF, 0x00, 0xE5, 0x36, 0xBF, 0x3F, 0xCF, 0x5A,
+	0x28, 0x03, 0xF5, 0xB3, 0xE0, 0x6F, 0xFC, 0x1D, 0x4F, 0xF1, 0x37, 0xE2, 0x8F, 0x83, 0x6D, 0x7F,
+	0x67, 0x7F, 0xF8, 0x2B, 0xDF, 0xEC, 0x9D, 0xE0, 0x3F, 0xDA, 0x23, 0xE1, 0xDD, 0xDD, 0xD2, 0x7F,
+	0x6B, 0xDF, 0xCB, 0xA0, 0xDB, 0x59, 0x6B, 0x10, 0x6E, 0x94, 0x87, 0xBD, 0x48, 0x82, 0x7D, 0x8A,
+	0x59, 0xA1, 0x86, 0x49, 0x04, 0x2B, 0x1C, 0x76, 0x8F, 0xB8, 0x2F, 0xFA, 0x42, 0x12, 0x5E, 0xBF,
+	0xA4, 0x0F, 0xD8, 0x9F, 0xC4, 0xDF, 0xB3, 0xB7, 0x8B, 0x7F, 0x64, 0x3F, 0x86, 0x9A, 0xC7, 0xEC,
+	0x8B, 0x23, 0x37, 0xC2, 0xD5, 0xF0, 0x46, 0x9B, 0x6D, 0xF0, 0xFD, 0x5B, 0xED, 0x3B, 0xA2, 0xD2,
+	0x60, 0xB7, 0x48, 0x6D, 0xA2, 0x6F, 0xB5, 0x13, 0x3E, 0xE4, 0x8E, 0x35, 0x42, 0x65, 0x25, 0xC9,
+	0x53, 0xB8, 0x93, 0x92, 0x7F, 0x85, 0x3A, 0xFE, 0xD1, 0x3F, 0xE0, 0x82, 0xFF, 0x00, 0xF2, 0x87,
+	0x4F, 0xD9, 0xE7, 0xFE, 0xC9, 0xCD, 0xAF, 0xFE, 0x84, 0xF4, 0x01, 0xF5, 0xC5, 0x14, 0x51, 0x40,
+	0x1F, 0xC0, 0x19, 0xEB, 0x45, 0x7E, 0xC5, 0x7F, 0xC1, 0x70, 0xFF, 0x00, 0xE0, 0xD8, 0x1F, 0x87,
+	0xDF, 0xF0, 0x4D, 0xAF, 0xD9, 0x8F, 0x5C, 0xFD, 0xB3, 0xBF, 0x67, 0xAF, 0xDA, 0x7F, 0x5A, 0xD6,
+	0xFC, 0x2D, 0xA1, 0xEA, 0x3A, 0x7D, 0xA5, 0xDF, 0x83, 0xFC, 0x69, 0xA4, 0xC4, 0xDA, 0x82, 0x8B,
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+	0xF0, 0xBB, 0x8E, 0xF2, 0x40, 0x53, 0xF8, 0xEB, 0x40, 0x05, 0x7F, 0x68, 0x9F, 0xF0, 0x41, 0x7F,
+	0xF9, 0x43, 0xA7, 0xEC, 0xF3, 0xFF, 0x00, 0x64, 0xE6, 0xD7, 0xFF, 0x00, 0x42, 0x7A, 0xFE, 0x6F,
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+	0xF6, 0x82, 0x6F, 0x02, 0x78, 0x77, 0xE1, 0xA3, 0x68, 0xB2, 0x6B, 0x4B, 0x65, 0xA0, 0xFD, 0xBA,
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+	0x98, 0x4B, 0xB5, 0x9A, 0x3F, 0xDD, 0x48, 0x37, 0x63, 0xFA, 0xB5, 0xFD, 0x92, 0x7F, 0x66, 0x5F,
+	0x01, 0xFE, 0xC6, 0x9F, 0xB3, 0x67, 0x83, 0x7F, 0x65, 0xBF, 0x85, 0xFA, 0xAE, 0xAD, 0x7D, 0xE1,
+	0xFF, 0x00, 0x03, 0xE8, 0x71, 0xE9, 0x7A, 0x4D, 0xE6, 0xBD, 0x71, 0x14, 0xB7, 0x93, 0x44, 0x99,
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+	0x95, 0x83, 0x29, 0x68, 0xE5, 0x56, 0x52, 0x43, 0x00, 0x46, 0x47, 0x04, 0x64, 0x57, 0xF3, 0x43,
+	0xFF, 0x00, 0x05, 0x50, 0xF8, 0x51, 0xF0, 0xBB, 0xC2, 0xFF, 0x00, 0xF0, 0x75, 0xFF, 0x00, 0xC2,
+	0x9F, 0x86, 0x5E, 0x1B, 0xF8, 0x6D, 0xA0, 0x69, 0xFE, 0x1B, 0xBA, 0xF8, 0xA1, 0xF0, 0xCE, 0x2B,
+	0x8F, 0x0F, 0xD8, 0xE8, 0xF0, 0x43, 0x63, 0x2C, 0x73, 0x5D, 0x69, 0xE2, 0x54, 0x68, 0x15, 0x44,
+	0x6C, 0xAE, 0x19, 0xB7, 0x02, 0xB8, 0x6C, 0x9C, 0xE7, 0x35, 0xFD, 0x3A, 0x57, 0xF3, 0x59, 0xFF,
+	0x00, 0x05, 0x6E, 0x5C, 0x7F, 0xC1, 0xDE, 0xDF, 0x08, 0x49, 0xEF, 0xF1, 0x57, 0xE1, 0x69, 0xFF,
+	0x00, 0xC9, 0xBD, 0x3A, 0x80, 0x3F, 0xA2, 0xDF, 0x87, 0x9F, 0x05, 0x7E, 0x0F, 0x7C, 0x20, 0x17,
+	0x83, 0xE1, 0x27, 0xC2, 0x8F, 0x0C, 0xF8, 0x5B, 0xFB, 0x43, 0xCB, 0xFE, 0xD0, 0xFF, 0x00, 0x84,
+	0x77, 0x41, 0xB7, 0xB2, 0xFB, 0x4F, 0x97, 0xBB, 0x67, 0x99, 0xE4, 0xA2, 0xEF, 0xDB, 0xBD, 0xF1,
+	0x9C, 0xE3, 0x7B, 0x63, 0x19, 0x39, 0xF3, 0x8F, 0xDB, 0x77, 0xFE, 0x0A, 0x2F, 0xFB, 0x19, 0x7F,
+	0xC1, 0x39, 0xFC, 0x0B, 0x67, 0xF1, 0x07, 0xF6, 0xC3, 0xF8, 0xE9, 0xA5, 0xF8, 0x46, 0xD7, 0x54,
+	0x92, 0x48, 0xF4, 0x5B, 0x19, 0x52, 0x5B, 0x9D, 0x43, 0x54, 0x78, 0xF6, 0x79, 0x82, 0xDA, 0xD2,
+	0xDD, 0x1E, 0x69, 0x82, 0x19, 0x23, 0x0E, 0xEA, 0x9B, 0x23, 0xF3, 0x53, 0x7B, 0x20, 0x60, 0x4F,
+	0xB6, 0xD7, 0xF2, 0xDB, 0x27, 0xC0, 0xDF, 0x19, 0xFF, 0x00, 0xC1, 0xC2, 0xDF, 0xF0, 0x72, 0x07,
+	0xC4, 0x4F, 0x85, 0x5F, 0x1A, 0x7E, 0x2A, 0x5F, 0x41, 0xE0, 0x7F, 0x0C, 0xF8, 0x83, 0x5C, 0xB7,
+	0x6B, 0x9D, 0x2E, 0x52, 0xB3, 0x59, 0x78, 0x4F, 0x46, 0xBB, 0x7B, 0x5B, 0x5B, 0x5B, 0x14, 0x97,
+	0xCC, 0x48, 0xA4, 0x9A, 0x47, 0x89, 0x9C, 0xE3, 0x60, 0x92, 0xEE, 0xE6, 0x7D, 0x85, 0x8F, 0x96,
+	0xC0, 0x1F, 0xBC, 0x9F, 0xF0, 0x4E, 0x2F, 0xF8, 0x2D, 0x27, 0xEC, 0x19, 0xFF, 0x00, 0x05, 0x4D,
+	0xD6, 0x3C, 0x4D, 0xE1, 0x2F, 0xD9, 0x5B, 0xE2, 0x1D, 0xF3, 0x78, 0x87, 0xC2, 0xAA, 0x2E, 0x35,
+	0x0F, 0x0C, 0xF8, 0x9B, 0x4D, 0x36, 0x17, 0xD3, 0xD8, 0x96, 0x54, 0x17, 0xF0, 0x46, 0x59, 0xBC,
+	0xEB, 0x71, 0x23, 0x08, 0xD9, 0x94, 0xEE, 0x89, 0xDA, 0x31, 0x22, 0xC7, 0xE6, 0xC2, 0x64, 0x2B,
+	0xB4, 0xFD, 0x88, 0x3F, 0xE0, 0x98, 0xFF, 0x00, 0xB0, 0xD7, 0xFC, 0x13, 0x87, 0x47, 0xD6, 0xF4,
+	0x6F, 0xD8, 0xCB, 0xE0, 0x1D, 0x8F, 0x83, 0x47, 0x89, 0x27, 0x8A, 0x5D, 0x7A, 0xF3, 0xFB, 0x4A,
+	0xF2, 0xFE, 0xEA, 0xF4, 0xC4, 0xBB, 0x63, 0x56, 0xB8, 0xBC, 0x9A, 0x59, 0x44, 0x6B, 0x96, 0x2B,
+	0x10, 0x61, 0x1A, 0xB3, 0xBB, 0x05, 0x05, 0xD8, 0x92, 0x80, 0x3D, 0xEA, 0xBF, 0x13, 0x7F, 0xE0,
+	0xEA, 0x7F, 0xF8, 0x23, 0xA7, 0xED, 0x25, 0xFB, 0x47, 0x78, 0xDB, 0xC2, 0x3F, 0xF0, 0x51, 0xFF,
+	0x00, 0xD8, 0x9B, 0xC3, 0x3A, 0xD7, 0x88, 0x3C, 0x5F, 0xE1, 0x1D, 0x16, 0x1D, 0x23, 0xC5, 0x5E,
+	0x1B, 0xF0, 0xBC, 0x7F, 0xF1, 0x33, 0x10, 0x5B, 0x5C, 0x4B, 0x73, 0x67, 0xAA, 0xD9, 0x24, 0x4A,
+	0x26, 0x9E, 0x78, 0xE4, 0x99, 0xE3, 0x75, 0x46, 0x79, 0x76, 0x2D, 0xB1, 0x8D, 0x36, 0xC5, 0x21,
+	0x1F, 0xB6, 0x54, 0x50, 0x07, 0xF3, 0x0F, 0x2F, 0xFC, 0x1D, 0xEB, 0xFF, 0x00, 0x05, 0x58, 0xD6,
+	0xBE, 0x0C, 0x45, 0xFB, 0x34, 0xE9, 0xFF, 0x00, 0x05, 0x3C, 0x1E, 0xDF, 0x15, 0xAE, 0x21, 0x1E,
+	0x1F, 0x3E, 0x38, 0xB6, 0xD0, 0x2E, 0x8E, 0xA9, 0x25, 0xD1, 0x43, 0x6C, 0x26, 0x4D, 0x35, 0x58,
+	0x42, 0xBA, 0x89, 0x98, 0x87, 0xC0, 0x43, 0x0F, 0x9B, 0x95, 0x5B, 0x50, 0xA4, 0x20, 0xFB, 0x97,
+	0xFE, 0x0D, 0x56, 0xFF, 0x00, 0x82, 0x31, 0xFC, 0x73, 0xFD, 0x8A, 0x2D, 0x3C, 0x55, 0xFB, 0x76,
+	0xFE, 0xD7, 0x7E, 0x1D, 0xD4, 0xBC, 0x3B, 0xE3, 0xAF, 0x1F, 0x78, 0x7D, 0x74, 0x6F, 0x0E, 0x78,
+	0x47, 0x54, 0xDD, 0x1D, 0xEE, 0x9D, 0xA4, 0x49, 0x3C, 0x57, 0x77, 0x13, 0xDF, 0x46, 0xC7, 0x29,
+	0x71, 0x3C, 0xD0, 0x5B, 0x62, 0x17, 0x0B, 0x24, 0x2B, 0x03, 0x6F, 0xF9, 0xA5, 0x29, 0x1F, 0xEC,
+	0x8C, 0x7F, 0xEA, 0xD7, 0xFD, 0xDA, 0x75, 0x00, 0x14, 0x51, 0x45, 0x00, 0x7F, 0xFF, 0xD9, 0x00,
+	0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60,
+	0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x46, 0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D,
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+	0x00, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02,
+	0x04, 0x03, 0x02, 0x02, 0x02, 0x02, 0x05, 0x04, 0x04, 0x03, 0x04, 0x06, 0x05, 0x06, 0x06, 0x06,
+	0x05, 0x06, 0x06, 0x06, 0x07, 0x09, 0x08, 0x06, 0x07, 0x09, 0x07, 0x06, 0x06, 0x08, 0x0B, 0x08,
+	0x09, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x06, 0x08, 0x0B, 0x0C, 0x0B, 0x0A, 0x0C, 0x09, 0x0A, 0x0A,
+	0x0A, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x05, 0x03, 0x03, 0x05,
+	0x0A, 0x07, 0x06, 0x07, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00, 0x16, 0x00, 0x6F, 0x03,
+	0x01, 0x22, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00, 0x1F, 0x00, 0x00, 0x01,
+	0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x10, 0x00,
+	0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01,
+	0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22,
+	0x71, 0x14, 0x32, 0x81, 0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24,
+	0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29,
+	0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A,
+	0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A,
+	0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A,
+	0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8,
+	0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6,
+	0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3,
+	0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9,
+	0xFA, 0xFF, 0xC4, 0x00, 0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09,
+	0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07,
+	0x05, 0x04, 0x04, 0x00, 0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31,
+	0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1,
+	0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1,
+	0x25, 0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39,
+	0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
+	0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
+	0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
+	0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5,
+	0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3,
+	0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA,
+	0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00,
+	0x02, 0x11, 0x03, 0x11, 0x00, 0x3F, 0x00, 0xFD, 0xFC, 0xA2, 0xBE, 0x14, 0xFD, 0xB0, 0x7F, 0x63,
+	0x6F, 0xF8, 0x2B, 0xB7, 0xC5, 0x3F, 0xDA, 0x1F, 0x5F, 0xF1, 0xCF, 0xEC, 0xE5, 0xFB, 0x74, 0x69,
+	0x3E, 0x1B, 0xF0, 0x55, 0xE9, 0xB7, 0xFE, 0xC2, 0xF0, 0xFC, 0xDA, 0x95, 0xD5, 0x8B, 0xE9, 0xE8,
+	0xB0, 0x22, 0xBC, 0x65, 0x20, 0xB4, 0x95, 0x5C, 0x99, 0x44, 0x8F, 0xE6, 0x17, 0x2C, 0x77, 0xE3,
+	0x0A, 0x00, 0x03, 0xCC, 0xFF, 0x00, 0xE1, 0xDE, 0xBF, 0xF0, 0x5E, 0x2F, 0xFA, 0x48, 0xE6, 0x89,
+	0xFF, 0x00, 0x85, 0x66, 0xA3, 0xFF, 0x00, 0xCA, 0xEA, 0x00, 0xFD, 0x37, 0xAA, 0x73, 0x78, 0x83,
+	0x41, 0xB6, 0xD4, 0x46, 0x91, 0x71, 0xAD, 0xD9, 0xC7, 0x76, 0xCB, 0xB9, 0x6D, 0x5E, 0xE5, 0x44,
+	0x85, 0x70, 0x4E, 0x76, 0xE7, 0x38, 0xC0, 0x27, 0xA7, 0x40, 0x6B, 0xF3, 0x50, 0xFF, 0x00, 0xC1,
+	0x3D, 0x3F, 0xE0, 0xBC, 0x5D, 0xBF, 0xE0, 0xA3, 0x9A, 0x27, 0xFE, 0x15, 0x9A, 0x8F, 0xFF, 0x00,
+	0x2B, 0xAB, 0xD5, 0x74, 0x9F, 0xD9, 0xEB, 0xF6, 0x8B, 0xD1, 0x7E, 0x1E, 0x0F, 0x00, 0x7C, 0x43,
+	0xF0, 0xA6, 0xA9, 0xE2, 0x2F, 0x1C, 0x0B, 0x7B, 0x5F, 0xB7, 0x78, 0xAA, 0xDE, 0x67, 0x9A, 0x0B,
+	0xF9, 0xA3, 0x8A, 0x0F, 0x3E, 0x75, 0xB8, 0x60, 0xBC, 0x48, 0x62, 0x99, 0x80, 0x7D, 0x8E, 0x7C,
+	0xC0, 0x0A, 0x86, 0x6D, 0xB5, 0xF0, 0xBC, 0x75, 0xC5, 0x99, 0xA7, 0x09, 0xE1, 0xA8, 0x55, 0xC1,
+	0x60, 0x65, 0x8A, 0x75, 0x24, 0xD3, 0x51, 0xE6, 0xD2, 0xC9, 0x59, 0x7B, 0xB0, 0x9F, 0xBD, 0x2D,
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+	0xFC, 0x4C, 0xF8, 0x85, 0xF1, 0x23, 0xFB, 0x73, 0x5E, 0xF1, 0x2B, 0x7C, 0x4E, 0xD5, 0x46, 0xA9,
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+	0x15, 0xFB, 0x7D, 0x7C, 0x7D, 0xF8, 0x13, 0xFF, 0x00, 0x04, 0x77, 0xF1, 0xF4, 0x73, 0x41, 0xE1,
+	0xFF, 0x00, 0x03, 0xFC, 0x4D, 0xD6, 0x9E, 0xEA, 0xC5, 0xA4, 0x91, 0x65, 0xD3, 0xED, 0x67, 0x92,
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+	0xFF, 0x00, 0xB5, 0x47, 0xFC, 0x1C, 0x5B, 0xFB, 0x42, 0xFC, 0x40, 0xFD, 0x85, 0xFE, 0x06, 0x7F,
+	0xC1, 0x3F, 0xFF, 0x00, 0x63, 0x4F, 0x8E, 0x7E, 0x22, 0x4F, 0x88, 0xDA, 0xA7, 0x84, 0xF4, 0x78,
+	0x3E, 0x2A, 0x7C, 0x5E, 0xBF, 0xF1, 0x4C, 0x96, 0x7A, 0x93, 0x6A, 0x92, 0x15, 0x1F, 0x61, 0x8F,
+	0x52, 0xBA, 0x74, 0x68, 0x58, 0x31, 0x46, 0x9E, 0xF5, 0xA5, 0x50, 0x3E, 0xE6, 0xF0, 0xA2, 0x52,
+	0x7F, 0x6E, 0x7F, 0xE0, 0x92, 0x5F, 0xB0, 0x47, 0xC7, 0x5F, 0xD8, 0xB7, 0xE0, 0x45, 0xBC, 0xFF,
+	0x00, 0xB5, 0x97, 0xED, 0x85, 0xF1, 0x1F, 0xE3, 0x0F, 0xC4, 0xFD, 0x76, 0xD9, 0x65, 0xF1, 0x2E,
+	0xA7, 0xE2, 0xDF, 0x88, 0x7A, 0xAE, 0xAB, 0xA6, 0x69, 0x84, 0x80, 0xDF, 0x63, 0xB0, 0xB7, 0xBB,
+	0x9D, 0xA3, 0x54, 0x8C, 0xF0, 0x6E, 0x0A, 0x09, 0x65, 0x25, 0x89, 0x28, 0x85, 0x62, 0x4F, 0xC3,
+	0x3F, 0x8B, 0x1F, 0xF0, 0x6F, 0x5F, 0xC3, 0xBD, 0x3B, 0xFE, 0x0D, 0xFF, 0x00, 0xF0, 0x7F, 0xFC,
+	0x14, 0x57, 0xE0, 0x9E, 0xA5, 0xAD, 0xEB, 0x7F, 0x13, 0x97, 0x4A, 0x8B, 0xC6, 0x5E, 0x32, 0xF3,
+	0xA5, 0xC5, 0xBC, 0x9A, 0x14, 0xC3, 0x12, 0x5B, 0x41, 0x6E, 0x38, 0x5F, 0xB2, 0x26, 0xD9, 0xCC,
+	0xA4, 0x97, 0x70, 0xB7, 0x24, 0xE0, 0x18, 0xA3, 0x8B, 0xF4, 0xAF, 0xFE, 0x0D, 0xB4, 0xFF, 0x00,
+	0x82, 0xA3, 0xDC, 0x7F, 0xC1, 0x45, 0xFF, 0x00, 0x61, 0x0D, 0x47, 0xF6, 0x4E, 0xF8, 0x89, 0xF1,
+	0x3A, 0x4B, 0x5F, 0x8C, 0x1F, 0x0E, 0x74, 0x17, 0xD2, 0x64, 0xD4, 0xA5, 0xBA, 0x2D, 0x7D, 0x7D,
+	0xA4, 0xB4, 0x66, 0x2B, 0x3D, 0x55, 0x79, 0x56, 0x91, 0xE1, 0x25, 0x61, 0x95, 0x83, 0x16, 0xDF,
+	0x1C, 0x6E, 0xEC, 0x1A, 0x75, 0xCE, 0xED, 0x47, 0xF7, 0xF1, 0x8E, 0xB5, 0x23, 0x2B, 0xCB, 0xD2,
+	0xDF, 0x67, 0xB2, 0x4F, 0x4D, 0x37, 0xF9, 0x3B, 0xE1, 0x2F, 0x86, 0x8C, 0x9E, 0x90, 0x7A, 0x2F,
+	0x5B, 0xEF, 0x2F, 0x5D, 0xFE, 0x6B, 0xCA, 0xDF, 0xAA, 0xE3, 0x8E, 0x8D, 0x5F, 0xCE, 0x6F, 0xFC,
+	0x1C, 0x5D, 0xFB, 0x59, 0xFE, 0xD7, 0xDE, 0x0A, 0xFF, 0x00, 0x82, 0xD5, 0xF8, 0x67, 0xF6, 0x74,
+	0xF8, 0x63, 0xFF, 0x00, 0x05, 0x06, 0xF8, 0x95, 0xF0, 0x6F, 0xC1, 0x7E, 0x20, 0xD0, 0x7C, 0x37,
+	0x6D, 0xA9, 0x5E, 0x68, 0x3F, 0x10, 0x75, 0x0D, 0x37, 0x4B, 0xD2, 0x16, 0xEA, 0xEA, 0x58, 0xA7,
+	0xD4, 0x64, 0x86, 0x1B, 0xA8, 0x22, 0x21, 0x10, 0xEF, 0x76, 0x66, 0x4C, 0x88, 0xF9, 0x70, 0x06,
+	0x47, 0xE9, 0x57, 0xFC, 0x13, 0xB3, 0xFE, 0x08, 0xF3, 0xFB, 0x71, 0xFE, 0xC6, 0x7F, 0xB4, 0xB5,
+	0xAF, 0xC7, 0x1F, 0x8E, 0xFF, 0x00, 0xF0, 0x5A, 0x6F, 0x8A, 0xDF, 0x1C, 0x3C, 0x3B, 0x06, 0x93,
+	0x75, 0x69, 0x27, 0x80, 0x7C, 0x5D, 0x16, 0xA6, 0xB6, 0x52, 0xC9, 0x2A, 0x80, 0x93, 0x93, 0x71,
+	0xAC, 0x5D, 0x47, 0xBA, 0x3C, 0x64, 0x7E, 0xEB, 0x3C, 0xF0, 0x57, 0xBF, 0xE5, 0x3F, 0xFC, 0x1C,
+	0x45, 0xF0, 0xF3, 0xC2, 0x1F, 0x16, 0xBF, 0xE0, 0xE3, 0xDF, 0x85, 0xBF, 0x0A, 0x7E, 0x22, 0x68,
+	0xFF, 0x00, 0xDA, 0x1A, 0x17, 0x89, 0x57, 0xC1, 0x7A, 0x56, 0xB9, 0x61, 0xF6, 0x89, 0x21, 0xFB,
+	0x4D, 0xA5, 0xC6, 0xA4, 0xF1, 0x4B, 0x1E, 0xF8, 0xD9, 0x5D, 0x37, 0x46, 0xEC, 0xBB, 0x95, 0x95,
+	0x86, 0x72, 0x08, 0x20, 0x11, 0xC7, 0x18, 0xF3, 0x63, 0xA8, 0x45, 0x6B, 0x7B, 0xDD, 0x7C, 0xBA,
+	0x9D, 0x1C, 0xDC, 0xB4, 0x6A, 0xB7, 0xD1, 0x2B, 0x3F, 0x9A, 0x38, 0x7F, 0x8F, 0x1F, 0xB5, 0xF7,
+	0xED, 0xB7, 0xFF, 0x00, 0x04, 0xCA, 0xFD, 0xBF, 0xBE, 0x16, 0xF8, 0x7F, 0xF6, 0x57, 0xFF, 0x00,
+	0x82, 0xEB, 0x78, 0x97, 0xF6, 0xB7, 0xB5, 0xD4, 0x8D, 0x95, 0xCD, 0xFD, 0xA4, 0x3E, 0x2E, 0xBC,
+	0xD6, 0x74, 0x99, 0xA5, 0x9E, 0xF2, 0x4B, 0x77, 0xD2, 0xAE, 0x2D, 0x7F, 0xB4, 0x6F, 0xED, 0xE5,
+	0x79, 0x23, 0x51, 0x83, 0x1C, 0x82, 0x74, 0x32, 0x86, 0x51, 0x13, 0x08, 0xA4, 0x6F, 0xD6, 0x6F,
+	0xF8, 0x2A, 0x47, 0xFC, 0x12, 0xF3, 0xF6, 0xAF, 0xF8, 0xCB, 0xF1, 0x57, 0xC5, 0x7F, 0xB6, 0x7E,
+	0x87, 0xFF, 0x00, 0x05, 0xE5, 0xF8, 0x95, 0xFB, 0x39, 0xFC, 0x3B, 0xB4, 0xD0, 0x6D, 0xEE, 0x35,
+	0x0F, 0x0B, 0xE8, 0xEF, 0xA9, 0x47, 0xA5, 0xE8, 0xD1, 0xDB, 0x5B, 0x2A, 0xCD, 0x39, 0x78, 0x75,
+	0xAB, 0x58, 0xC1, 0x76, 0x52, 0xE7, 0x10, 0xA9, 0x25, 0xB1, 0xF3, 0x1E, 0x4F, 0xE5, 0x7F, 0xED,
+	0x3B, 0xF0, 0xB2, 0xF3, 0xFE, 0x0D, 0x9F, 0xFF, 0x00, 0x82, 0xD8, 0x78, 0x7B, 0xE2, 0x9F, 0x80,
+	0x3E, 0x13, 0xE9, 0x1A, 0xCF, 0xC1, 0x9F, 0x12, 0x6A, 0x30, 0xEA, 0xFE, 0x18, 0x8F, 0xC4, 0x5A,
+	0x1D, 0xAE, 0xA9, 0x75, 0x6F, 0xA4, 0x39, 0xF2, 0xEF, 0x6D, 0x6C, 0xEE, 0xEE, 0x51, 0xEE, 0x2D,
+	0x2E, 0xED, 0x5A, 0x57, 0x09, 0x2C, 0x72, 0xAC, 0x8E, 0x9F, 0x67, 0xF3, 0x9A, 0x45, 0x91, 0xD5,
+	0x99, 0xFF, 0x00, 0x07, 0x1E, 0xFF, 0x00, 0xC1, 0x6C, 0x75, 0x4F, 0xDB, 0x8F, 0xF6, 0x88, 0x8F,
+	0xF6, 0x2F, 0xF8, 0x75, 0xE3, 0x7B, 0xCD, 0x1F, 0xE0, 0x07, 0x86, 0xF5, 0x4B, 0x19, 0xB5, 0x6D,
+	0x5B, 0xC3, 0x4A, 0x97, 0x97, 0x1E, 0x2B, 0x66, 0x48, 0xA6, 0xFB, 0x7F, 0x97, 0xE7, 0x45, 0x1C,
+	0xF0, 0x44, 0xAF, 0xBA, 0xDE, 0xDD, 0xA5, 0x45, 0x76, 0x51, 0x24, 0x8E, 0xAC, 0x63, 0x10, 0x5C,
+	0xFF, 0x00, 0x79, 0x87, 0xA7, 0xCA, 0xEF, 0x26, 0xE5, 0xAB, 0xD3, 0x97, 0x6B, 0xA6, 0xBB, 0x2E,
+	0x9D, 0xC9, 0xA7, 0x06, 0xB1, 0x12, 0x93, 0xD2, 0x3C, 0xB1, 0xF3, 0xE6, 0xEB, 0x75, 0xE6, 0x4D,
+	0xFF, 0x00, 0x04, 0x75, 0x9F, 0xFE, 0x0A, 0xC5, 0xFF, 0x00, 0x05, 0x00, 0xFF, 0x00, 0x82, 0x8F,
+	0x59, 0x78, 0x7B, 0xE0, 0x5F, 0xFC, 0x14, 0xBF, 0xF6, 0x82, 0xF1, 0x87, 0xC1, 0xAF, 0x87, 0x5E,
+	0x2E, 0xB3, 0xD4, 0xFC, 0x5D, 0xE3, 0x6F, 0x18, 0x78, 0xE3, 0x58, 0xB5, 0xB5, 0xBD, 0xD2, 0xE1,
+	0xB8, 0xF3, 0x12, 0x09, 0xEC, 0x5B, 0x51, 0x99, 0x7C, 0xCB, 0xC1, 0x13, 0xC6, 0xB6, 0xE6, 0x49,
+	0x0E, 0xC6, 0x66, 0x7C, 0x2A, 0x3E, 0x3F, 0x64, 0xDF, 0xE2, 0xD7, 0xC5, 0x7F, 0x8D, 0xFF, 0x00,
+	0xF0, 0x5F, 0x88, 0x3E, 0x0A, 0xF8, 0x43, 0xE2, 0x5E, 0xBF, 0x67, 0xF0, 0xFF, 0x00, 0xE0, 0xAF,
+	0xC0, 0x96, 0xD5, 0x3C, 0x59, 0xA0, 0xE9, 0xFA, 0xD4, 0xF0, 0x58, 0x6A, 0x5A, 0xEE, 0xAB, 0x77,
+	0xE5, 0xDB, 0x2D, 0xDD, 0xBA, 0x3A, 0xA5, 0xC1, 0x4B, 0x55, 0x32, 0x46, 0x64, 0x12, 0x08, 0xCF,
+	0x2B, 0xB5, 0x89, 0x35, 0xF1, 0x2F, 0xFC, 0x13, 0x43, 0xFE, 0x0E, 0x33, 0xFF, 0x00, 0x82, 0x26,
+	0xFE, 0xC6, 0xFF, 0x00, 0x0A, 0xBC, 0x0F, 0xFB, 0x0E, 0x7E, 0xCB, 0x3F, 0xB3, 0x47, 0xC7, 0x6D,
+	0x36, 0xCA, 0x6D, 0x4E, 0xDA, 0xC7, 0xFB, 0x53, 0x53, 0xF0, 0xDE, 0x8B, 0xE6, 0xEA, 0x9A, 0x95,
+	0xCC, 0x91, 0xC5, 0x26, 0xA1, 0x7B, 0x2A, 0xEA, 0xC4, 0xB4, 0x92, 0x39, 0x52, 0xC4, 0x2E, 0x11,
+	0x02, 0xA4, 0x68, 0xA8, 0x88, 0x8B, 0xED, 0x5F, 0xB0, 0x7F, 0xED, 0x2F, 0xE1, 0xDF, 0x84, 0xBF,
+	0x04, 0x3F, 0x6E, 0x9F, 0xF8, 0x2D, 0x4F, 0x8E, 0x2D, 0x23, 0x9E, 0xCB, 0xC4, 0x5F, 0x13, 0x35,
+	0x75, 0xF0, 0xD0, 0x69, 0x76, 0xFF, 0x00, 0x69, 0x69, 0x3A, 0x04, 0x1F, 0x60, 0xD2, 0xE2, 0x0D,
+	0x81, 0xB7, 0xCD, 0x99, 0x9E, 0x21, 0xF2, 0x82, 0x0B, 0x02, 0x77, 0x13, 0x57, 0x5A, 0xA2, 0xA6,
+	0xAE, 0xB5, 0x85, 0x38, 0xB7, 0x77, 0xA5, 0xE4, 0xEC, 0x97, 0xE3, 0x7B, 0x23, 0x28, 0xC6, 0x55,
+	0x2F, 0x7D, 0x25, 0x36, 0x92, 0x5D, 0x95, 0xEE, 0xFE, 0x76, 0xDD, 0x9F, 0x09, 0x7F, 0xC1, 0x77,
+	0xBF, 0xE0, 0xA1, 0xDF, 0xF0, 0x50, 0x4F, 0xDA, 0x37, 0xFE, 0x0A, 0x9B, 0xF1, 0x03, 0xF6, 0x7E,
+	0xFF, 0x00, 0x82, 0x7A, 0xFE, 0xD2, 0xFF, 0x00, 0x10, 0xBC, 0x3B, 0xE1, 0xCF, 0x82, 0x3E, 0x02,
+	0xBE, 0x9F, 0xC4, 0x56, 0xDF, 0x0F, 0x7C, 0x71, 0x79, 0xA5, 0xDB, 0xB9, 0xD3, 0x6D, 0xA4, 0xBC,
+	0xD5, 0x6E, 0xA6, 0xFB, 0x1C, 0xA9, 0xE6, 0x49, 0x13, 0x1F, 0xB2, 0xE1, 0xB2, 0x43, 0xC2, 0x14,
+	0x63, 0x26, 0xBF, 0x56, 0xBF, 0xE0, 0x80, 0x5F, 0xB7, 0xB6, 0xA7, 0xFB, 0x63, 0x7F, 0xC1, 0x26,
+	0xBC, 0x27, 0xF1, 0x7B, 0xE2, 0x4F, 0x8A, 0xAF, 0xB5, 0xEF, 0x15, 0xF8, 0x26, 0xD6, 0xEF, 0xC3,
+	0xFE, 0x35, 0xBE, 0xBC, 0xBB, 0x37, 0x37, 0x97, 0x37, 0x56, 0x0A, 0x0A, 0x4B, 0x2C, 0x92, 0x36,
+	0xE9, 0x66, 0x96, 0xD5, 0xAD, 0xA5, 0x67, 0x73, 0x96, 0x79, 0x18, 0x92, 0x79, 0x35, 0xFC, 0xFE,
+	0x7F, 0xC1, 0x2E, 0x3E, 0x02, 0xFF, 0x00, 0xC1, 0x74, 0xFE, 0x3D, 0x78, 0x93, 0xE2, 0x57, 0xED,
+	0x99, 0xFF, 0x00, 0x04, 0xD0, 0xF0, 0x2F, 0xF6, 0xE5, 0xC7, 0x8B, 0x6E, 0x35, 0x2F, 0x0E, 0x7C,
+	0x42, 0xF1, 0x36, 0xA1, 0x37, 0x86, 0x8A, 0xDF, 0x9B, 0xC6, 0x8A, 0xF2, 0xF2, 0xD4, 0xC7, 0xAD,
+	0xBE, 0x1B, 0x79, 0x78, 0x9D, 0xDA, 0x24, 0xE8, 0x40, 0xDD, 0xC9, 0x15, 0xF6, 0x17, 0xFC, 0x1A,
+	0x5D, 0xF1, 0xBB, 0xC7, 0xBF, 0xB1, 0xD7, 0xFC, 0x14, 0x23, 0xE2, 0xCF, 0xFC, 0x13, 0x37, 0xF6,
+	0x87, 0xB1, 0x7F, 0x0F, 0xEB, 0x5E, 0x20, 0xB7, 0x9B, 0x6E, 0x87, 0x7D, 0x77, 0x1B, 0x34, 0x1A,
+	0xFE, 0x94, 0xEE, 0xB3, 0xDB, 0xC6, 0x63, 0x66, 0x47, 0x66, 0xB7, 0x69, 0xDF, 0x72, 0x33, 0x2B,
+	0x2D, 0xA2, 0xB2, 0x92, 0x30, 0x4D, 0x61, 0x68, 0xF2, 0xD0, 0x74, 0x1B, 0xF7, 0x9C, 0x79, 0xB5,
+	0xDF, 0x9B, 0x77, 0xF8, 0x32, 0xB1, 0x72, 0x8B, 0xAB, 0xED, 0x62, 0xBD, 0xD8, 0xC9, 0x2D, 0x36,
+	0xE5, 0xDB, 0x5F, 0x3B, 0xEA, 0x70, 0x9F, 0xF0, 0x5A, 0x9F, 0xF8, 0x2E, 0xF7, 0xFC, 0x14, 0xAB,
+	0xF6, 0x98, 0xD0, 0xBC, 0x13, 0xF1, 0x33, 0xF6, 0x7C, 0xF8, 0x7D, 0xF1, 0x5F, 0xF6, 0x71, 0xF8,
+	0x21, 0xA8, 0x6A, 0x77, 0x1F, 0xF0, 0x84, 0xF8, 0x9A, 0x3D, 0x62, 0xEF, 0x46, 0xD5, 0xFC, 0x70,
+	0xE1, 0x03, 0x7D, 0xA5, 0xE6, 0xB7, 0x78, 0xF7, 0x5A, 0xAC, 0x32, 0x26, 0xD8, 0xA0, 0x69, 0x60,
+	0x0E, 0xEE, 0x5A, 0x79, 0x98, 0x46, 0x22, 0xFD, 0x4B, 0xFF, 0x00, 0x82, 0xF6, 0x7C, 0x6E, 0xF8,
+	0xD3, 0xF0, 0x7B, 0xFE, 0x08, 0x45, 0xA9, 0x7C, 0x5E, 0xF8, 0x4B, 0xF1, 0x77, 0xC5, 0x1E, 0x16,
+	0xF1, 0x64, 0x76, 0x3E, 0x15, 0x68, 0xBC, 0x51, 0xE1, 0xCF, 0x10, 0x5C, 0x58, 0xEA, 0x2A, 0x65,
+	0xBB, 0xB3, 0x12, 0x91, 0x73, 0x0B, 0xAC, 0xB9, 0x70, 0xCC, 0x1B, 0xE6, 0xF9, 0x83, 0x10, 0x72,
+	0x09, 0xAF, 0x91, 0xFF, 0x00, 0xE0, 0xF7, 0x00, 0x07, 0xC3, 0x2F, 0xD9, 0xFF, 0x00, 0xCC, 0x6F,
+	0x97, 0xFE, 0x12, 0x4D, 0x73, 0xF0, 0xFD, 0xC5, 0xA5, 0x7D, 0x25, 0xFF, 0x00, 0x07, 0x1A, 0x67,
+	0xFE, 0x21, 0xDD, 0xD5, 0x3F, 0xEC, 0x1D, 0xE0, 0xFF, 0x00, 0xFD, 0x2D, 0xB2, 0xAE, 0x35, 0x2E,
+	0x6C, 0xB6, 0x5A, 0x6A, 0xAA, 0x25, 0xE7, 0xD3, 0xF3, 0x3A, 0xA2, 0xBF, 0xE1, 0x42, 0x9F, 0x67,
+	0x16, 0xFC, 0xB7, 0x3E, 0x7B, 0xFF, 0x00, 0x82, 0x3D, 0x7F, 0xC1, 0xC4, 0xDF, 0xB1, 0x47, 0xC2,
+	0x3F, 0xF8, 0x26, 0x5D, 0xAF, 0xC3, 0x4F, 0xDB, 0xD7, 0xF6, 0xF8, 0xF1, 0x45, 0xD7, 0xC6, 0x05,
+	0xB8, 0xD6, 0x8D, 0xC5, 0xC7, 0x89, 0xB4, 0xBF, 0x11, 0xEB, 0x9A, 0x86, 0xC9, 0x26, 0x90, 0xDA,
+	0xE6, 0xF9, 0x2D, 0xA6, 0x53, 0x84, 0x29, 0xB4, 0x79, 0xBF, 0x20, 0xC6, 0x76, 0xE3, 0x03, 0x2F,
+	0xFE, 0x0C, 0xF8, 0xFD, 0xAE, 0xFF, 0x00, 0x6A, 0xFF, 0x00, 0xDA, 0x6B, 0xE3, 0x27, 0xC6, 0xBD,
+	0x3F, 0xF6, 0x8C, 0xFD, 0xA7, 0xFE, 0x22, 0x7C, 0x41, 0xB4, 0xD2, 0xBC, 0x39, 0xA4, 0xCB, 0xA4,
+	0xDB, 0xF8, 0xDF, 0xC6, 0xB7, 0xFA, 0xAC, 0x76, 0x6E, 0xF7, 0x17, 0x01, 0x9A, 0x25, 0xBA, 0x95,
+	0xC4, 0x65, 0x80, 0x00, 0x95, 0xC6, 0x70, 0x33, 0x9C, 0x56, 0x5F, 0xFC, 0x10, 0xAB, 0xFE, 0x08,
+	0x8F, 0xFF, 0x00, 0x04, 0xC1, 0xFD, 0xB1, 0xFF, 0x00, 0xE0, 0x91, 0xF6, 0x3F, 0xB4, 0xEF, 0xED,
+	0x1F, 0xFB, 0x33, 0x7F, 0xC2, 0x49, 0xE3, 0x89, 0x6E, 0x75, 0xF4, 0x93, 0x5C, 0xFF, 0x00, 0x84,
+	0xCF, 0x5A, 0xB3, 0xDC, 0x2D, 0xA6, 0x91, 0x61, 0x1E, 0x4D, 0xAD, 0xEC, 0x70, 0xFC, 0xAA, 0xA3,
+	0xF8, 0x39, 0xC7, 0x39, 0xE4, 0x9E, 0x43, 0xFE, 0x0C, 0x8A, 0x54, 0x4F, 0x8E, 0x5F, 0x1F, 0x12,
+	0x3E, 0x83, 0xC2, 0xFA, 0x2E, 0x3F, 0xF0, 0x26, 0xE6, 0xBD, 0x25, 0x18, 0xFD, 0x72, 0xAA, 0x96,
+	0xEA, 0x1D, 0x36, 0xF2, 0xB1, 0xC3, 0x2F, 0xF7, 0x28, 0xB8, 0xED, 0xCE, 0xBD, 0x6F, 0x7F, 0xC8,
+	0xFE, 0x88, 0xEA, 0x1D, 0x4B, 0x52, 0xD3, 0xF4, 0x6D, 0x3A, 0xE3, 0x58, 0xD5, 0xEF, 0xA1, 0xB5,
+	0xB4, 0xB5, 0x85, 0xA6, 0xBA, 0xBA, 0xB8, 0x90, 0x24, 0x70, 0xC6, 0xA0, 0xB3, 0x3B, 0x31, 0xE1,
+	0x54, 0x00, 0x49, 0x27, 0x80, 0x05, 0x7E, 0x6D, 0xFE, 0xDF, 0xDA, 0xAE, 0xAB, 0xFF, 0x00, 0x04,
+	0xE9, 0xFD, 0xA5, 0xBC, 0x4D, 0xF1, 0xAE, 0xFF, 0x00, 0xE2, 0x0F, 0xC5, 0x8F, 0x13, 0xF8, 0x2F,
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+	0xDF, 0x8D, 0x74, 0xBF, 0x0E, 0x7C, 0x27, 0xBF, 0xF8, 0x2D, 0xE2, 0x4F, 0x0B, 0x69, 0xFE, 0x36,
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+	0x96, 0x53, 0x51, 0x4B, 0xED, 0x28, 0xD4, 0x50, 0x6D, 0x69, 0xAF, 0x2C, 0x5A, 0x9C, 0xB4, 0xD9,
+	0x6B, 0xCA, 0x9D, 0xD7, 0xD6, 0xBF, 0x07, 0x3E, 0x32, 0x7C, 0x30, 0xFD, 0xA0, 0xBE, 0x19, 0xE8,
+	0xFF, 0x00, 0x18, 0xFE, 0x0D, 0x78, 0xCA, 0xD3, 0xC4, 0x1E, 0x1A, 0xD7, 0xAD, 0x7C, 0xFD, 0x2F,
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+	0xD5, 0x5E, 0x37, 0x46, 0x47, 0x55, 0x65, 0x2A, 0x0A, 0xF9, 0xB7, 0xFE, 0x08, 0xCB, 0xA0, 0xEB,
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+	0x7D, 0x71, 0x45, 0x14, 0x54, 0x94, 0x14, 0x51, 0x45, 0x00, 0x14, 0xD7, 0xE9, 0x45, 0x14, 0xA5,
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+	0x00, 0x97, 0x8C, 0x69, 0xFF, 0x00, 0x51, 0x47, 0xFC, 0xB4, 0x5F, 0xF3, 0xDA, 0x8A, 0x2A, 0xA3,
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+	0xA2, 0x8F, 0xB6, 0x8A, 0x7F, 0x0B, 0x05, 0xEB, 0xFF, 0x00, 0x01, 0xA7, 0xAF, 0x7F, 0xAD, 0x14,
+	0x54, 0xF5, 0xF9, 0xB0, 0x5F, 0x08, 0x8D, 0xD6, 0x98, 0xDF, 0xFB, 0x3D, 0x14, 0x51, 0x53, 0xE0,
+	0x7F, 0xD7, 0x60, 0xFB, 0x48, 0x72, 0xFF, 0x00, 0xAD, 0x3F, 0x4A, 0x69, 0xFB, 0xA3, 0xFD, 0xEA,
+	0x28, 0xAD, 0x3F, 0xE5, 0xE2, 0x33, 0xFB, 0x2C, 0x57, 0xFF, 0x00, 0x58, 0x7F, 0xDD, 0xA5, 0x3F,
+	0x71, 0x3E, 0xA2, 0x8A, 0x2B, 0x1F, 0xB1, 0x2F, 0x5F, 0xF2, 0x34, 0xFB, 0x6B, 0xD0, 0x23, 0xFB,
+	0x8D, 0xF5, 0xA0, 0x7F, 0xAC, 0x5F, 0xF7, 0x68, 0xA2, 0xB6, 0xFF, 0x00, 0x97, 0x8F, 0xD0, 0x9F,
+	0xB2, 0x87, 0xD1, 0x45, 0x14, 0x14, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x7F, 0xFF,
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+	0x01, 0x11, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00, 0x1F, 0x00, 0x00, 0x01,
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+	0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01,
+	0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22,
+	0x71, 0x14, 0x32, 0x81, 0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24,
+	0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29,
+	0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A,
+	0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A,
+	0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A,
+	0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8,
+	0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6,
+	0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3,
+	0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9,
+	0xFA, 0xFF, 0xC4, 0x00, 0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
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+	0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07,
+	0x05, 0x04, 0x04, 0x00, 0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31,
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+	0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1,
+	0x25, 0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39,
+	0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
+	0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
+	0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
+	0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5,
+	0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3,
+	0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA,
+	0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00,
+	0x02, 0x11, 0x03, 0x11, 0x00, 0x3F, 0x00, 0xFB, 0x3B, 0xE1, 0xD7, 0xC6, 0x6F, 0x8F, 0xDF, 0x1E,
+	0xB5, 0xDF, 0xDA, 0x33, 0x57, 0xB3, 0xFD, 0xA0, 0x62, 0xF0, 0x26, 0x8D, 0xF0, 0x87, 0xC4, 0x7A,
+	0x8D, 0x9D, 0x8D, 0xAD, 0xDF, 0x85, 0x34, 0xAB, 0x8B, 0x43, 0x6F, 0x0C, 0x97, 0x06, 0x24, 0x92,
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+	0xCA, 0x72, 0x6C, 0x04, 0x32, 0xD8, 0x3C, 0x1F, 0xB4, 0x78, 0x98, 0x27, 0x27, 0xCF, 0x24, 0xEE,
+	0xDD, 0xBD, 0xD4, 0xB4, 0xF3, 0x3C, 0xC8, 0x54, 0x9D, 0x5C, 0x4D, 0x58, 0x73, 0x72, 0xC6, 0x2E,
+	0xDA, 0x5B, 0xAF, 0xAF, 0x62, 0xE7, 0xC3, 0x8F, 0xDB, 0x1F, 0xC7, 0xFF, 0x00, 0x1E, 0xBC, 0x45,
+	0xFB, 0x11, 0xF8, 0x83, 0x54, 0xD5, 0x6F, 0xF4, 0x79, 0xFC, 0x75, 0x77, 0xE2, 0x6B, 0x7F, 0x10,
+	0x58, 0xE9, 0xF3, 0xC9, 0x6B, 0x67, 0xAC, 0xFD, 0x93, 0xCB, 0x86, 0x17, 0x9A, 0x15, 0x6D, 0xAF,
+	0x9D, 0x9E, 0x60, 0x0C, 0x08, 0x56, 0x91, 0xB6, 0x85, 0x06, 0x9E, 0x23, 0x85, 0x30, 0x38, 0x1A,
+	0x79, 0xD5, 0x1A, 0x70, 0xE6, 0xF6, 0x11, 0xA6, 0xE0, 0xE5, 0xAC, 0xA2, 0xE4, 0xF5, 0xD7, 0x4E,
+	0xF6, 0xF4, 0x39, 0xE9, 0xE3, 0x2A, 0x54, 0xA1, 0x19, 0x29, 0x6B, 0xCF, 0x6B, 0xAE, 0xA9, 0x69,
+	0xF8, 0x9E, 0xE7, 0xF1, 0x27, 0xFE, 0x0A, 0xE1, 0xE0, 0x2F, 0x00, 0xF8, 0x8F, 0xC4, 0x50, 0x5A,
+	0x78, 0x37, 0xE2, 0xBF, 0x8B, 0x3C, 0x3B, 0xE1, 0x1B, 0xC7, 0xD3, 0xF5, 0xBF, 0x14, 0xE8, 0x3E,
+	0x1D, 0x17, 0x3A, 0x16, 0x97, 0x3C, 0x6D, 0xB6, 0x64, 0x96, 0xE1, 0xE5, 0x43, 0x98, 0xF2, 0x0B,
+	0x15, 0x42, 0x30, 0x41, 0x52, 0xD9, 0x15, 0xF2, 0x58, 0x3E, 0x02, 0xC7, 0x62, 0x23, 0x49, 0x4A,
+	0xA5, 0x3A, 0x75, 0x2A, 0x24, 0xE1, 0x4E, 0x53, 0xB4, 0xE4, 0xBA, 0x59, 0x25, 0x6D, 0x76, 0x57,
+	0x68, 0xF4, 0x6A, 0x62, 0xA3, 0x19, 0x38, 0x42, 0x2E, 0x5C, 0xBB, 0xDB, 0xA7, 0xF5, 0xE4, 0x76,
+	0x1F, 0x17, 0xFF, 0x00, 0x6F, 0x9D, 0x2F, 0xE1, 0x99, 0xF0, 0xEC, 0x9A, 0x1F, 0xC3, 0x8F, 0x8B,
+	0xFF, 0x00, 0x13, 0x6C, 0x3C, 0x4D, 0xA4, 0x43, 0xAE, 0x5A, 0xDF, 0xF8, 0x2F, 0xC3, 0x7F, 0xDA,
+	0x36, 0x91, 0xDB, 0x4D, 0x9F, 0x24, 0xC8, 0xEF, 0x24, 0x7B, 0x59, 0xD5, 0x4B, 0x05, 0xE4, 0x81,
+	0x82, 0x71, 0x91, 0x9F, 0x2F, 0x07, 0xC3, 0x75, 0x2B, 0x4A, 0x70, 0xAD, 0x88, 0xA7, 0x41, 0xC2,
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+	0x25, 0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39,
+	0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
+	0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
+	0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
+	0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5,
+	0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3,
+	0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA,
+	0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00,
+	0x02, 0x11, 0x03, 0x11, 0x00, 0x3F, 0x00, 0xFD, 0xFC, 0xA0, 0x0F, 0x8E, 0x7F, 0x6E, 0x7F, 0x8F,
+	0x9F, 0x12, 0x3C, 0x67, 0xFB, 0x5C, 0x78, 0x37, 0xE0, 0x07, 0xC2, 0xBF, 0x16, 0x7F, 0xC2, 0xB7,
+	0xBB, 0xBB, 0xF0, 0xEC, 0xFE, 0x3A, 0xF1, 0x7F, 0x8B, 0x53, 0x4E, 0xB7, 0xBF, 0xBE, 0xB4, 0xD2,
+	0xA3, 0xBA, 0x8E, 0xCE, 0x0B, 0x2D, 0x3E, 0x2B, 0x84, 0x92, 0x0F, 0xB4, 0xDC, 0x4E, 0xF2, 0x6E,
+	0x96, 0x64, 0x2B, 0x0C, 0x70, 0x96, 0x50, 0xEC, 0xC1, 0x47, 0xCF, 0x71, 0x2E, 0x78, 0xB2, 0xAC,
+	0x27, 0xD6, 0x39, 0x79, 0x9B, 0x76, 0x49, 0xF7, 0xEE, 0x76, 0xE0, 0x70, 0x6F, 0x11, 0x53, 0x91,
+	0xBB, 0x23, 0x82, 0x93, 0xFE, 0x09, 0xC9, 0xE2, 0x39, 0xE5, 0x79, 0x1F, 0xF6, 0xB7, 0xFD, 0xB1,
+	0x83, 0x48, 0xC5, 0x88, 0x5F, 0x19, 0x69, 0x2A, 0xB9, 0x3E, 0x8A, 0x34, 0xAC, 0x01, 0xEC, 0x38,
+	0x15, 0xF9, 0xDA, 0xF1, 0x2F, 0x1E, 0x96, 0xB4, 0xA1, 0xF8, 0xFF, 0x00, 0x99, 0xED, 0xFF, 0x00,
+	0xAB, 0xD0, 0xE9, 0x3F, 0xC3, 0xFE, 0x08, 0x9F, 0xF0, 0xED, 0xFF, 0x00, 0x10, 0xFF, 0x00, 0xD1,
+	0xDC, 0x7E, 0xD9, 0x1F, 0xF8, 0x5A, 0x69, 0x3F, 0xFC, 0xAA, 0xA3, 0xFE, 0x22, 0x66, 0x3F, 0xFE,
+	0x7D, 0x43, 0xF1, 0xFF, 0x00, 0x30, 0xFF, 0x00, 0x57, 0xA3, 0xFC, 0xEF, 0xEE, 0xFF, 0x00, 0x82,
+	0x1F, 0xF0, 0xED, 0xFF, 0x00, 0x10, 0xFF, 0x00, 0xD1, 0xDC, 0x7E, 0xD9, 0x1F, 0xF8, 0x5A, 0x69,
+	0x3F, 0xFC, 0xAA, 0xA3, 0xFE, 0x22, 0x66, 0x3F, 0xFE, 0x7D, 0x43, 0xF1, 0xFF, 0x00, 0x30, 0xFF,
+	0x00, 0x57, 0xA3, 0xFC, 0xEF, 0xEE, 0xFF, 0x00, 0x82, 0x1F, 0xF0, 0xED, 0xFF, 0x00, 0x10, 0xFF,
+	0x00, 0xD1, 0xDC, 0x7E, 0xD9, 0x1F, 0xF8, 0x5A, 0x69, 0x3F, 0xFC, 0xAA, 0xA3, 0xFE, 0x22, 0x66,
+	0x3F, 0xFE, 0x7D, 0x43, 0xF1, 0xFF, 0x00, 0x30, 0xFF, 0x00, 0x57, 0xA3, 0xFC, 0xEF, 0xEE, 0xFF,
+	0x00, 0x82, 0x1F, 0xF0, 0xED, 0xFF, 0x00, 0x10, 0xFF, 0x00, 0xD1, 0xDC, 0x7E, 0xD9, 0x1F, 0xF8,
+	0x5A, 0x69, 0x3F, 0xFC, 0xAA, 0xA3, 0xFE, 0x22, 0x66, 0x3F, 0xFE, 0x7D, 0x43, 0xF1, 0xFF, 0x00,
+	0x30, 0xFF, 0x00, 0x57, 0xA3, 0xFC, 0xEF, 0xEE, 0xFF, 0x00, 0x82, 0x1F, 0xF0, 0xED, 0xFF, 0x00,
+	0x10, 0xFF, 0x00, 0xD1, 0xDC, 0x7E, 0xD9, 0x1F, 0xF8, 0x5A, 0x69, 0x3F, 0xFC, 0xAA, 0xA3, 0xFE,
+	0x22, 0x66, 0x3F, 0xFE, 0x7D, 0x43, 0xF1, 0xFF, 0x00, 0x30, 0xFF, 0x00, 0x57, 0xA3, 0xFC, 0xEF,
+	0xEE, 0xFF, 0x00, 0x82, 0x1F, 0xF0, 0xED, 0xFF, 0x00, 0x10, 0xFF, 0x00, 0xD1, 0xDC, 0x7E, 0xD9,
+	0x1F, 0xF8, 0x5A, 0x69, 0x3F, 0xFC, 0xAA, 0xA3, 0xFE, 0x22, 0x66, 0x3F, 0xFE, 0x7D, 0x43, 0xF1,
+	0xFF, 0x00, 0x30, 0xFF, 0x00, 0x57, 0xA3, 0xFC, 0xEF, 0xEE, 0xFF, 0x00, 0x82, 0x1F, 0xF0, 0xED,
+	0xFF, 0x00, 0x10, 0xFF, 0x00, 0xD1, 0xDC, 0x7E, 0xD9, 0x1F, 0xF8, 0x5A, 0x69, 0x3F, 0xFC, 0xAA,
+	0xA3, 0xFE, 0x22, 0x66, 0x3F, 0xFE, 0x7D, 0x43, 0xF1, 0xFF, 0x00, 0x30, 0xFF, 0x00, 0x57, 0xA3,
+	0xFC, 0xEF, 0xEE, 0xFF, 0x00, 0x82, 0x4B, 0x69, 0xFF, 0x00, 0x04, 0xFC, 0xF1, 0xAF, 0x86, 0xA5,
+	0xFB, 0x76, 0x89, 0xFB, 0x5E, 0x7E, 0xD6, 0x10, 0xEA, 0xF6, 0xEA, 0x5A, 0xD2, 0x4D, 0x57, 0x5F,
+	0xD1, 0x75, 0x5B, 0x28, 0xE5, 0xC7, 0xCA, 0xD2, 0xDA, 0xC9, 0xA5, 0x84, 0x99, 0x01, 0xC6, 0x50,
+	0x91, 0x91, 0x91, 0x91, 0xD6, 0x9C, 0x7C, 0x4A, 0xC7, 0xB7, 0xFC, 0x18, 0x3F, 0xBF, 0xFC, 0xC3,
+	0xFD, 0x5E, 0x8F, 0x59, 0xBF, 0xB8, 0xF6, 0xCF, 0xF8, 0x26, 0x2F, 0xED, 0x33, 0xE2, 0xEF, 0xDA,
+	0x1F, 0xE1, 0x17, 0x8C, 0xB4, 0xAF, 0x88, 0x0D, 0xA6, 0xDE, 0x78, 0xEB, 0xE1, 0x27, 0x8C, 0xAF,
+	0xBC, 0x07, 0xAD, 0x6A, 0xDA, 0x7D, 0xBF, 0xD9, 0x6D, 0x7C, 0x41, 0x25, 0xB4, 0x56, 0xF7, 0x10,
+	0xEA, 0x09, 0x06, 0x5B, 0xC8, 0x33, 0xDB, 0x5D, 0xDB, 0xBB, 0xC4, 0x19, 0x95, 0x24, 0x32, 0x05,
+	0x3B, 0x70, 0x07, 0xEA, 0xB9, 0x76, 0x3A, 0x18, 0xCC, 0x2D, 0x3C, 0x4D, 0x35, 0x65, 0x35, 0x7B,
+	0x1F, 0x39, 0x5A, 0x97, 0xB3, 0x9B, 0x87, 0x63, 0xE9, 0x32, 0x70, 0x2B, 0xBC, 0xC8, 0xFC, 0xF8,
+	0xD6, 0x7C, 0x7B, 0xF1, 0x27, 0xFE, 0x0A, 0x2D, 0xFB, 0x41, 0x7C, 0x5D, 0xD3, 0xF4, 0x3F, 0x8B,
+	0xDE, 0x32, 0xF8, 0x45, 0xF0, 0x97, 0xE1, 0x57, 0x89, 0xE6, 0xF0, 0x14, 0x36, 0xBE, 0x08, 0x8E,
+	0xC6, 0x0D, 0x73, 0xC4, 0x1A, 0xAD, 0xAC, 0x36, 0xF3, 0x5E, 0x5D, 0xCD, 0x7D, 0x75, 0x6F, 0x39,
+	0x82, 0x14, 0x7B, 0x8F, 0x21, 0x21, 0x85, 0x01, 0x6F, 0x29, 0x9D, 0x9F, 0xA2, 0xD7, 0xC2, 0x71,
+	0x4F, 0x18, 0x4B, 0x2C, 0xC4, 0x2C, 0x25, 0x0A, 0x6A, 0x52, 0xB7, 0x33, 0x6F, 0x64, 0x9F, 0x43,
+	0xD7, 0xCB, 0xB2, 0xC5, 0x89, 0x8B, 0x94, 0xA5, 0x6B, 0x0F, 0xFF, 0x00, 0x87, 0x70, 0x78, 0x80,
+	0xFF, 0x00, 0xCD, 0xDC, 0x7E, 0xD9, 0x3F, 0xF8, 0x5A, 0x69, 0x3F, 0xFC, 0xAA, 0xAF, 0x95, 0xFF,
+	0x00, 0x88, 0x97, 0x8E, 0xE9, 0x4A, 0x0F, 0xEF, 0xFF, 0x00, 0x33, 0xD0, 0xFF, 0x00, 0x57, 0xA3,
+	0xFC, 0xFF, 0x00, 0x87, 0xFC, 0x10, 0xFF, 0x00, 0x87, 0x6F, 0xF8, 0x87, 0xFE, 0x8E, 0xE3, 0xF6,
+	0xC8, 0xFF, 0x00, 0xC2, 0xD3, 0x49, 0xFF, 0x00, 0xE5, 0x55, 0x1F, 0xF1, 0x13, 0x31, 0xFF, 0x00,
+	0xF3, 0xEA, 0x1F, 0x8F, 0xF9, 0x8F, 0xFD, 0x5E, 0x8F, 0xF3, 0xBF, 0xBB, 0xFE, 0x08, 0x7F, 0xC3,
+	0xB7, 0xFC, 0x43, 0xFF, 0x00, 0x47, 0x71, 0xFB, 0x64, 0x7F, 0xE1, 0x69, 0xA4, 0xFF, 0x00, 0xF2,
+	0xAA, 0x8F, 0xF8, 0x89, 0x98, 0xFF, 0x00, 0xF9, 0xF5, 0x0F, 0xC7, 0xFC, 0xC3, 0xFD, 0x5E, 0x8F,
+	0xF3, 0xBF, 0xBB, 0xFE, 0x08, 0x7F, 0xC3, 0xB7, 0xFC, 0x43, 0xFF, 0x00, 0x47, 0x71, 0xFB, 0x64,
+	0x7F, 0xE1, 0x69, 0xA4, 0xFF, 0x00, 0xF2, 0xAA, 0x8F, 0xF8, 0x89, 0x98, 0xFF, 0x00, 0xF9, 0xF5,
+	0x0F, 0xC7, 0xFC, 0xC3, 0xFD, 0x5E, 0x8F, 0xF3, 0xBF, 0xBB, 0xFE, 0x08, 0x7F, 0xC3, 0xB7, 0xFC,
+	0x43, 0xFF, 0x00, 0x47, 0x71, 0xFB, 0x64, 0x7F, 0xE1, 0x69, 0xA4, 0xFF, 0x00, 0xF2, 0xAA, 0x8F,
+	0xF8, 0x89, 0x98, 0xFF, 0x00, 0xF9, 0xF5, 0x0F, 0xC7, 0xFC, 0xC3, 0xFD, 0x5E, 0x8F, 0xF3, 0xBF,
+	0xBB, 0xFE, 0x08, 0x7F, 0xC3, 0xB7, 0xFC, 0x43, 0xFF, 0x00, 0x47, 0x71, 0xFB, 0x64, 0x7F, 0xE1,
+	0x69, 0xA4, 0xFF, 0x00, 0xF2, 0xAA, 0x8F, 0xF8, 0x89, 0x98, 0xFF, 0x00, 0xF9, 0xF5, 0x0F, 0xC7,
+	0xFC, 0xC3, 0xFD, 0x5E, 0x8F, 0xF3, 0xBF, 0xBB, 0xFE, 0x08, 0x7F, 0xC3, 0xB7, 0xFC, 0x43, 0xFF,
+	0x00, 0x47, 0x71, 0xFB, 0x64, 0x7F, 0xE1, 0x69, 0xA4, 0xFF, 0x00, 0xF2, 0xAA, 0x8F, 0xF8, 0x89,
+	0x98, 0xFF, 0x00, 0xF9, 0xF5, 0x0F, 0xC7, 0xFC, 0xC3, 0xFD, 0x5E, 0x8F, 0xF3, 0xBF, 0xBB, 0xFE,
+	0x08, 0x7F, 0xC3, 0xB7, 0xFC, 0x43, 0xFF, 0x00, 0x47, 0x71, 0xFB, 0x64, 0x7F, 0xE1, 0x69, 0xA4,
+	0xFF, 0x00, 0xF2, 0xAA, 0x9A, 0xF1, 0x33, 0x1F, 0xFF, 0x00, 0x3E, 0x61, 0xF8, 0xFF, 0x00, 0x98,
+	0xBF, 0xD5, 0xD8, 0xFF, 0x00, 0x3B, 0xFB, 0xBF, 0xE0, 0x99, 0xDE, 0x38, 0xFD, 0x99, 0x7E, 0x37,
+	0xFE, 0xCC, 0x5E, 0x01, 0xD5, 0xFC, 0x5F, 0xF0, 0xA3, 0xF6, 0x98, 0xF8, 0xC3, 0xE2, 0xFF, 0x00,
+	0x13, 0x68, 0x30, 0x3E, 0xA4, 0x3C, 0x3D, 0xF1, 0x3A, 0xE7, 0x4B, 0xD7, 0xB4, 0x3F, 0x10, 0xC7,
+	0x0A, 0x34, 0x86, 0xC5, 0xCC, 0x56, 0x56, 0xF3, 0xDA, 0x99, 0x76, 0x84, 0x13, 0xC5, 0x32, 0x94,
+	0xCF, 0x20, 0x8C, 0xD7, 0x56, 0x03, 0xC4, 0x7A, 0xD3, 0xC4, 0x42, 0x96, 0x2A, 0x94, 0x54, 0x64,
+	0xD2, 0xBA, 0x6E, 0xFA, 0xE8, 0x8C, 0xAB, 0x64, 0x31, 0xA7, 0x4E, 0x52, 0x52, 0x6D, 0xA3, 0xED,
+	0x9F, 0xD9, 0x87, 0xE3, 0x9D, 0x87, 0xED, 0x3F, 0xFB, 0x38, 0x78, 0x03, 0xE2, 0x46, 0x97, 0x67,
+	0x73, 0xA7, 0xE9, 0xDE, 0x3F, 0xF0, 0xEE, 0x9F, 0xE2, 0x2B, 0x6B, 0x4B, 0x82, 0x1A, 0x6B, 0x58,
+	0xEE, 0xED, 0xA3, 0x9D, 0x62, 0x72, 0x38, 0x2C, 0xA1, 0xF6, 0x92, 0x38, 0x24, 0x71, 0x5F, 0xAC,
+	0xB5, 0x6D, 0x19, 0xF3, 0x9D, 0x11, 0x7F, 0xE3, 0xBF, 0xC5, 0xFD, 0x23, 0xF6, 0x7B, 0xF8, 0x25,
+	0xE3, 0x0F, 0x1F, 0x78, 0x83, 0xED, 0x3F, 0xD8, 0x5E, 0x06, 0xD0, 0xEF, 0x7C, 0x41, 0xA9, 0x7D,
+	0x9D, 0x3C, 0xC9, 0xBE, 0xCD, 0x69, 0x6E, 0xF3, 0xCB, 0xB1, 0x72, 0x37, 0x36, 0xC8, 0xDB, 0x03,
+	0x23, 0x27, 0x1C, 0xD0, 0x9A, 0x7B, 0x8F, 0xA3, 0xB1, 0xF0, 0x67, 0xC2, 0x6F, 0x82, 0xBF, 0x1B,
+	0x7F, 0x6D, 0x6F, 0x84, 0x5E, 0x1E, 0xF8, 0x8D, 0xF1, 0x3B, 0xF6, 0x8A, 0xF8, 0xB9, 0xF0, 0xF7,
+	0x51, 0xF1, 0xAD, 0x9C, 0x3E, 0x20, 0xB0, 0xF0, 0xA7, 0xC3, 0x3B, 0xAD, 0x33, 0x46, 0xD3, 0x3C,
+	0x33, 0x67, 0x77, 0x12, 0x4D, 0x05, 0x8C, 0x93, 0x4D, 0x63, 0x3D, 0xC5, 0xDC, 0xD1, 0xA3, 0xA8,
+	0x92, 0x59, 0x24, 0x00, 0xBE, 0xE0, 0xAB, 0xB5, 0x41, 0x3F, 0x96, 0xE6, 0xDE, 0x21, 0x57, 0xA1,
+	0x8A, 0x9D, 0x0C, 0x2D, 0x38, 0xB5, 0x17, 0x6B, 0xB6, 0xF5, 0xB7, 0x5B, 0x68, 0x7D, 0x0E, 0x1B,
+	0x24, 0x55, 0x69, 0x29, 0xB9, 0x34, 0xDF, 0x91, 0xB9, 0xFF, 0x00, 0x0E, 0xDF, 0xF1, 0x0F, 0xFD,
+	0x1D, 0xC7, 0xED, 0x91, 0xFF, 0x00, 0x85, 0xA6, 0x93, 0xFF, 0x00, 0xCA, 0xAA, 0xF3, 0x5F, 0x89,
+	0x78, 0xEF, 0xF9, 0xF3, 0x0F, 0xC7, 0xFC, 0xCD, 0xFF, 0x00, 0xD5, 0xE8, 0xFF, 0x00, 0x3B, 0xFB,
+	0xBF, 0xE0, 0x87, 0xFC, 0x3B, 0x7F, 0xC4, 0x3F, 0xF4, 0x77, 0x1F, 0xB6, 0x47, 0xFE, 0x16, 0x9A,
+	0x4F, 0xFF, 0x00, 0x2A, 0xA8, 0xFF, 0x00, 0x88, 0x99, 0x8F, 0xFF, 0x00, 0x9F, 0x50, 0xFC, 0x7F,
+	0xCC, 0x3F, 0xD5, 0xE8, 0xFF, 0x00, 0x3B, 0xFB, 0xBF, 0xE0, 0x87, 0xFC, 0x3B, 0x7F, 0xC4, 0x3F,
+	0xF4, 0x77, 0x1F, 0xB6, 0x47, 0xFE, 0x16, 0x9A, 0x4F, 0xFF, 0x00, 0x2A, 0xA8, 0xFF, 0x00, 0x88,
+	0x99, 0x8F, 0xFF, 0x00, 0x9F, 0x50, 0xFC, 0x7F, 0xCC, 0x3F, 0xD5, 0xE8, 0xFF, 0x00, 0x3B, 0xFB,
+	0xBF, 0xE0, 0x87, 0xFC, 0x3B, 0x7F, 0xC4, 0x3F, 0xF4, 0x77, 0x1F, 0xB6, 0x47, 0xFE, 0x16, 0x9A,
+	0x4F, 0xFF, 0x00, 0x2A, 0xA8, 0xFF, 0x00, 0x88, 0x99, 0x8F, 0xFF, 0x00, 0x9F, 0x50, 0xFC, 0x7F,
+	0xCC, 0x3F, 0xD5, 0xE8, 0xFF, 0x00, 0x3B, 0xFB, 0xBF, 0xE0, 0x87, 0xFC, 0x3B, 0x7F, 0xC4, 0x3F,
+	0xF4, 0x77, 0x1F, 0xB6, 0x47, 0xFE, 0x16, 0x9A, 0x4F, 0xFF, 0x00, 0x2A, 0xA8, 0xFF, 0x00, 0x88,
+	0x99, 0x8F, 0xFF, 0x00, 0x9F, 0x50, 0xFC, 0x7F, 0xCC, 0x3F, 0xD5, 0xE8, 0xFF, 0x00, 0x3B, 0xFB,
+	0xBF, 0xE0, 0x87, 0xFC, 0x3B, 0x7F, 0xC4, 0x3F, 0xF4, 0x77, 0x1F, 0xB6, 0x47, 0xFE, 0x16, 0x9A,
+	0x4F, 0xFF, 0x00, 0x2A, 0xA8, 0xFF, 0x00, 0x88, 0x99, 0x8F, 0xFF, 0x00, 0x9F, 0x50, 0xFC, 0x7F,
+	0xCC, 0x3F, 0xD5, 0xE8, 0xFF, 0x00, 0x3B, 0xFB, 0xBF, 0xE0, 0x87, 0xFC, 0x3B, 0x7F, 0xC4, 0x3F,
+	0xF4, 0x77, 0x1F, 0xB6, 0x47, 0xFE, 0x16, 0x9A, 0x4F, 0xFF, 0x00, 0x2A, 0xA8, 0xFF, 0x00, 0x88,
+	0x99, 0x8F, 0xFF, 0x00, 0x9F, 0x50, 0xFC, 0x7F, 0xCC, 0x3F, 0xD5, 0xE8, 0xFF, 0x00, 0x3B, 0xFB,
+	0xBF, 0xE0, 0x81, 0xFF, 0x00, 0x82, 0x6F, 0xF8, 0x87, 0xFE, 0x8E, 0xE3, 0xF6, 0xC9, 0xFC, 0x3C,
+	0x69, 0xA5, 0x7F, 0xF2, 0xAA, 0x9C, 0x7C, 0x4B, 0xC7, 0xB7, 0x67, 0x4A, 0x1F, 0x8F, 0xF9, 0x87,
+	0xFA, 0xBD, 0x1F, 0xE7, 0xFC, 0x3F, 0xE0, 0x95, 0x4F, 0x89, 0xFE, 0x2A, 0xFF, 0x00, 0xC1, 0x38,
+	0xFE, 0x2E, 0x7C, 0x2D, 0xB8, 0xB8, 0xF8, 0xBD, 0xE3, 0xBF, 0x8C, 0xBF, 0x09, 0x7C, 0x7B, 0xE2,
+	0xFD, 0x37, 0xC0, 0x9A, 0xCE, 0x93, 0xE3, 0x88, 0xF4, 0xFB, 0xBD, 0x6F, 0x44, 0xBB, 0xD5, 0x25,
+	0x30, 0x5A, 0x6A, 0x56, 0xDA, 0x85, 0xB4, 0x16, 0xCC, 0xF1, 0xAD, 0xC9, 0x82, 0x29, 0x20, 0x95,
+	0x24, 0x01, 0x25, 0x76, 0x52, 0x08, 0xE3, 0xE9, 0xB8, 0x5F, 0x8C, 0x6A, 0x66, 0x58, 0x97, 0x86,
+	0xC4, 0x52, 0x51, 0x6D, 0x37, 0x16, 0x9E, 0xE9, 0x74, 0x3C, 0xFC, 0xC3, 0x2A, 0x58, 0x68, 0x29,
+	0xA9, 0x5C, 0xFD, 0x0D, 0x5F, 0x7A, 0xFB, 0xE3, 0xC7, 0x3C, 0x0B, 0xFE, 0x0A, 0x4B, 0xFB, 0x54,
+	0x6B, 0xBF, 0xB2, 0x77, 0xEC, 0xD0, 0x75, 0x4F, 0x06, 0xD8, 0x69, 0x3A, 0x9F, 0xC4, 0x2F, 0x17,
+	0x6B, 0x9A, 0x67, 0x83, 0x3C, 0x1F, 0x6D, 0xAA, 0xBB, 0xA6, 0x9E, 0xFA, 0xBE, 0xA7, 0x74, 0x96,
+	0xB6, 0xF2, 0x5C, 0x94, 0x05, 0xFC, 0x88, 0xB7, 0xB4, 0xCE, 0x17, 0x96, 0x58, 0x4A, 0x82, 0x0B,
+	0x02, 0x39, 0xB1, 0x18, 0x8A, 0x74, 0x69, 0x4A, 0xAD, 0x47, 0xA4, 0x53, 0x7F, 0x24, 0xAF, 0x62,
+	0xA1, 0x07, 0x29, 0x28, 0xAE, 0xA7, 0xCF, 0xB3, 0xFE, 0xC1, 0x5F, 0x10, 0xFC, 0x65, 0x1C, 0x37,
+	0xFE, 0x2D, 0xFD, 0xAF, 0xFF, 0x00, 0x69, 0xDB, 0x9F, 0x10, 0xC9, 0x12, 0xAD, 0xEC, 0xBE, 0x1B,
+	0xD4, 0xB4, 0x5F, 0x0F, 0x69, 0x72, 0x38, 0x1C, 0x98, 0x6C, 0xA3, 0xD3, 0x5C, 0x42, 0xBE, 0xC5,
+	0xDD, 0xBD, 0x59, 0x8F, 0x35, 0xF9, 0x44, 0xBC, 0x4A, 0xC6, 0xDE, 0xF0, 0xA3, 0x14, 0xBA, 0x5E,
+	0xF7, 0xB7, 0x99, 0xF4, 0xAB, 0x87, 0xE3, 0x65, 0xEF, 0x3F, 0xB9, 0x7F, 0x99, 0x1F, 0xFC, 0x3B,
+	0x83, 0xC4, 0x27, 0xFE, 0x6E, 0xE3, 0xF6, 0xC8, 0xFF, 0x00, 0xC2, 0xD3, 0x49, 0xFF, 0x00, 0xE5,
+	0x55, 0x66, 0xFC, 0x4B, 0xC7, 0xAF, 0xF9, 0x73, 0x0F, 0xC7, 0xFC, 0xC3, 0xFD, 0x5E, 0x8F, 0xF3,
+	0xBF, 0xBB, 0xFE, 0x08, 0x7F, 0xC3, 0xB7, 0xFC, 0x43, 0xFF, 0x00, 0x47, 0x71, 0xFB, 0x64, 0x7F,
+	0xE1, 0x69, 0xA4, 0xFF, 0x00, 0xF2, 0xAA, 0x97, 0xFC, 0x44, 0xCC, 0x7F, 0xFC, 0xFA, 0x87, 0xE3,
+	0xFE, 0x63, 0xFF, 0x00, 0x57, 0xA3, 0xFC, 0xEF, 0xEE, 0xFF, 0x00, 0x82, 0x1F, 0xF0, 0xED, 0xFF,
+	0x00, 0x10, 0xFF, 0x00, 0xD1, 0xDC, 0x7E, 0xD9, 0x1F, 0xF8, 0x5A, 0x69, 0x3F, 0xFC, 0xAA, 0xA3,
+	0xFE, 0x22, 0x66, 0x3F, 0xFE, 0x7D, 0x43, 0xF1, 0xFF, 0x00, 0x30, 0xFF, 0x00, 0x57, 0xA3, 0xFC,
+	0xEF, 0xEE, 0xFF, 0x00, 0x82, 0x1F, 0xF0, 0xED, 0xFF, 0x00, 0x10, 0xFF, 0x00, 0xD1, 0xDC, 0x7E,
+	0xD9, 0x1F, 0xF8, 0x5A, 0x69, 0x3F, 0xFC, 0xAA, 0xA3, 0xFE, 0x22, 0x66, 0x3F, 0xFE, 0x7D, 0x43,
+	0xF1, 0xFF, 0x00, 0x30, 0xFF, 0x00, 0x57, 0xA3, 0xFC, 0xEF, 0xEE, 0xFF, 0x00, 0x82, 0x1F, 0xF0,
+	0xED, 0xFF, 0x00, 0x10, 0xFF, 0x00, 0xD1, 0xDC, 0x7E, 0xD9, 0x1F, 0xF8, 0x5A, 0x69, 0x3F, 0xFC,
+	0xAA, 0xA3, 0xFE, 0x22, 0x66, 0x3F, 0xFE, 0x7D, 0x43, 0xF1, 0xFF, 0x00, 0x30, 0xFF, 0x00, 0x57,
+	0xA3, 0xFC, 0xEF, 0xEE, 0xFF, 0x00, 0x82, 0x1F, 0xF0, 0xED, 0xFF, 0x00, 0x10, 0xFF, 0x00, 0xD1,
+	0xDC, 0x7E, 0xD9, 0x1F, 0xF8, 0x5A, 0x69, 0x3F, 0xFC, 0xAA, 0xA3, 0xFE, 0x22, 0x66, 0x3F, 0xFE,
+	0x7D, 0x43, 0xF1, 0xFF, 0x00, 0x30, 0xFF, 0x00, 0x57, 0xA3, 0xFC, 0xEF, 0xEE, 0xFF, 0x00, 0x82,
+	0x1F, 0xF0, 0xED, 0xFF, 0x00, 0x10, 0xFF, 0x00, 0xD1, 0xDC, 0x7E, 0xD9, 0x1F, 0xF8, 0x5A, 0x69,
+	0x3F, 0xFC, 0xAA, 0xA3, 0xFE, 0x22, 0x66, 0x3F, 0xFE, 0x7D, 0x43, 0xF1, 0xFF, 0x00, 0x30, 0xFF,
+	0x00, 0x57, 0xA3, 0xFC, 0xEF, 0xEE, 0xFF, 0x00, 0x82, 0x07, 0xFE, 0x09, 0xC1, 0xE2, 0x1C, 0x7F,
+	0xC9, 0xDB, 0xFE, 0xD9, 0x27, 0xE9, 0xE3, 0x5D, 0x27, 0xFF, 0x00, 0x95, 0x54, 0xE3, 0xE2, 0x5E,
+	0x39, 0xB4, 0x9D, 0x28, 0x7E, 0x3F, 0xE6, 0x2F, 0xF5, 0x7A, 0x1D, 0x67, 0xF8, 0x7F, 0xC1, 0x3B,
+	0x6F, 0xD9, 0x0F, 0xE2, 0x77, 0xC5, 0x2F, 0x81, 0xDF, 0xB6, 0x82, 0x7C, 0x12, 0xF1, 0xFF, 0x00,
+	0x8D, 0xAF, 0x7E, 0x2A, 0x78, 0x4F, 0xC5, 0x7E, 0x13, 0xBC, 0xF1, 0x4F, 0x83, 0xBC, 0x4D, 0xAB,
+	0xD9, 0x5A, 0x5A, 0x6B, 0xBA, 0x7B, 0xE9, 0xD7, 0x36, 0x76, 0xB7, 0x9A, 0x6D, 0xE1, 0xB5, 0x8E,
+	0x38, 0x6E, 0x86, 0xCB, 0xEB, 0x49, 0xA3, 0xB8, 0xF2, 0xA2, 0x7C, 0x99, 0x95, 0xC3, 0xFC, 0xAC,
+	0x3E, 0xE7, 0x84, 0xF8, 0x8D, 0xE6, 0xF8, 0x79, 0xCE, 0x70, 0xE4, 0x9C, 0x1A, 0xBA, 0x5B, 0x59,
+	0xEC, 0xFF, 0x00, 0x03, 0xC8, 0xCC, 0x30, 0x3F, 0x56, 0x9D, 0x93, 0xBA, 0x67, 0xD9, 0xD5, 0xF5,
+	0x67, 0x9E, 0x7C, 0x87, 0xFB, 0x7C, 0xFC, 0x79, 0xF8, 0x93, 0xA9, 0x7E, 0xD2, 0x7F, 0x0D, 0x7E,
+	0x05, 0x7C, 0x2A, 0xF1, 0x25, 0xBF, 0x80, 0x35, 0x4F, 0x17, 0x69, 0x3A, 0x97, 0x8B, 0xBC, 0x49,
+	0xE2, 0xE3, 0x61, 0x0E, 0xA3, 0x7B, 0xA4, 0x69, 0x16, 0x12, 0xDA, 0x5B, 0x8B, 0x7B, 0x1B, 0x69,
+	0xD1, 0xE0, 0x6B, 0x8B, 0x8B, 0x8B, 0xC8, 0x90, 0xCB, 0x30, 0x2B, 0x0C, 0x69, 0x23, 0x08, 0xE4,
+	0x62, 0xA1, 0x7E, 0x7B, 0x88, 0xF3, 0xAF, 0xEC, 0xBC, 0x0B, 0xC5, 0x28, 0x73, 0x36, 0xED, 0x15,
+	0xD1, 0xBF, 0xF8, 0x63, 0xB3, 0x05, 0x84, 0xFA, 0xC5, 0x4E, 0x43, 0xCE, 0x66, 0xFF, 0x00, 0x82,
+	0x73, 0xF8, 0x8E, 0xEA, 0x67, 0x95, 0xFF, 0x00, 0x6B, 0x7F, 0xDB, 0x14, 0x3C, 0xAC, 0x5D, 0xB6,
+	0x78, 0xC7, 0x48, 0x45, 0xC9, 0x39, 0xE1, 0x46, 0x95, 0x85, 0x1E, 0x80, 0x70, 0x3B, 0x57, 0xE7,
+	0x8F, 0xC4, 0xBC, 0x7A, 0xFF, 0x00, 0x97, 0x50, 0xFC, 0x7F, 0xCC, 0xF7, 0x1F, 0x0F, 0x46, 0xFF,
+	0x00, 0x1B, 0xFB, 0xBF, 0xE0, 0x8D, 0xFF, 0x00, 0x87, 0x6F, 0xF8, 0x87, 0xFE, 0x8E, 0xE3, 0xF6,
+	0xC8, 0xFF, 0x00, 0xC2, 0xD3, 0x49, 0xFF, 0x00, 0xE5, 0x55, 0x2F, 0xF8, 0x89, 0x98, 0xFF, 0x00,
+	0xF9, 0xF5, 0x0F, 0xC7, 0xFC, 0xC3, 0xFD, 0x5E, 0x8F, 0xF3, 0xBF, 0xBB, 0xFE, 0x08, 0x7F, 0xC3,
+	0xB7, 0xFC, 0x43, 0xFF, 0x00, 0x47, 0x71, 0xFB, 0x64, 0x7F, 0xE1, 0x69, 0xA4, 0xFF, 0x00, 0xF2,
+	0xAA, 0x8F, 0xF8, 0x89, 0x98, 0xFF, 0x00, 0xF9, 0xF5, 0x0F, 0xC7, 0xFC, 0xC3, 0xFD, 0x5E, 0x8F,
+	0xF3, 0xBF, 0xBB, 0xFE, 0x08, 0x7F, 0xC3, 0xB7, 0xFC, 0x43, 0xFF, 0x00, 0x47, 0x71, 0xFB, 0x64,
+	0x7F, 0xE1, 0x69, 0xA4, 0xFF, 0x00, 0xF2, 0xAA, 0x8F, 0xF8, 0x89, 0x98, 0xFF, 0x00, 0xF9, 0xF5,
+	0x0F, 0xC7, 0xFC, 0xC3, 0xFD, 0x5E, 0x8F, 0xF3, 0xBF, 0xBB, 0xFE, 0x08, 0x7F, 0xC3, 0xB7, 0xFC,
+	0x43, 0xFF, 0x00, 0x47, 0x71, 0xFB, 0x64, 0x7F, 0xE1, 0x69, 0xA4, 0xFF, 0x00, 0xF2, 0xAA, 0x8F,
+	0xF8, 0x89, 0x98, 0xFF, 0x00, 0xF9, 0xF5, 0x0F, 0xC7, 0xFC, 0xC3, 0xFD, 0x5E, 0x8F, 0xF3, 0xBF,
+	0xBB, 0xFE, 0x08, 0x7F, 0xC3, 0xB7, 0xFC, 0x43, 0xFF, 0x00, 0x47, 0x71, 0xFB, 0x64, 0x7F, 0xE1,
+	0x69, 0xA4, 0xFF, 0x00, 0xF2, 0xAA, 0x8F, 0xF8, 0x89, 0x98, 0xFF, 0x00, 0xF9, 0xF5, 0x0F, 0xC7,
+	0xFC, 0xC3, 0xFD, 0x5E, 0x8F, 0xF3, 0xBF, 0xBB, 0xFE, 0x08, 0x7F, 0xC3, 0xB7, 0xFC, 0x43, 0xFF,
+	0x00, 0x47, 0x71, 0xFB, 0x64, 0x7F, 0xE1, 0x69, 0xA4, 0xFF, 0x00, 0xF2, 0xAA, 0x8F, 0xF8, 0x89,
+	0x98, 0xFF, 0x00, 0xF9, 0xF5, 0x0F, 0xC7, 0xFC, 0xC3, 0xFD, 0x5E, 0x8F, 0xF3, 0xBF, 0xBB, 0xFE,
+	0x08, 0x7F, 0xC3, 0xB7, 0xFC, 0x43, 0xFF, 0x00, 0x47, 0x71, 0xFB, 0x64, 0x7F, 0xE1, 0x69, 0xA4,
+	0xFF, 0x00, 0xF2, 0xAA, 0x8F, 0xF8, 0x89, 0x98, 0xFF, 0x00, 0xF9, 0xF5, 0x0F, 0xC7, 0xFC, 0xC3,
+	0xFD, 0x5E, 0x8F, 0xF3, 0xBF, 0xBB, 0xFE, 0x09, 0x36, 0x9F, 0xFF, 0x00, 0x04, 0xFB, 0xF1, 0x87,
+	0x86, 0xEF, 0x12, 0xFF, 0x00, 0x4A, 0xFD, 0xAE, 0xBF, 0x6B, 0x44, 0xD4, 0xAD, 0x7E, 0x7B, 0x66,
+	0xD4, 0xBC, 0x45, 0xA2, 0xEA, 0x56, 0x8B, 0x27, 0xF0, 0x99, 0x6D, 0xA5, 0xD2, 0xB6, 0x4C, 0x99,
+	0xEA, 0x8D, 0xC1, 0xE9, 0xC7, 0x5A, 0x3F, 0xE2, 0x25, 0xE3, 0xDB, 0x5F, 0xB9, 0x87, 0xE3, 0xFE,
+	0x61, 0xFE, 0xAF, 0x47, 0xAC, 0xDF, 0xDC, 0x7B, 0x17, 0xFC, 0x13, 0x37, 0xF6, 0x93, 0xF1, 0xBF,
+	0xC6, 0x5F, 0x0B, 0xFC, 0x43, 0xF0, 0x5F, 0xC4, 0xE9, 0xF4, 0xAD, 0x53, 0xE2, 0x0F, 0xC1, 0x9F,
+	0x15, 0x3F, 0x85, 0x35, 0x2D, 0x73, 0x4C, 0xB7, 0xFB, 0x25, 0xAF, 0x89, 0xE0, 0x6B, 0x4B, 0x6B,
+	0xDB, 0x3D, 0x47, 0xEC, 0xFC, 0x8B, 0x69, 0x65, 0xB6, 0xBB, 0x8C, 0x4B, 0x02, 0xB3, 0x22, 0x4A,
+	0x92, 0x6D, 0x3B, 0x59, 0x55, 0x7F, 0x54, 0xCA, 0xB1, 0xF0, 0xC6, 0xE1, 0x69, 0xE2, 0xA9, 0xA6,
+	0x94, 0xD5, 0xEC, 0xFA, 0x1F, 0x3B, 0x88, 0xA4, 0xE9, 0xD4, 0x74, 0xFB, 0x1F, 0x4E, 0x57, 0xA2,
+	0x62, 0x14, 0x01, 0xF0, 0xBF, 0xC5, 0x5F, 0xF9, 0x4E, 0xBA, 0x7F, 0xD9, 0x06, 0x4F, 0xFD, 0x48,
+	0x5E, 0xBF, 0x3C, 0xF1, 0x1F, 0xFD, 0xC2, 0x93, 0xFE, 0xFA, 0xFC, 0x99, 0xEE, 0xE4, 0x0B, 0xF7,
+	0xD2, 0xF4, 0x3D, 0xFC, 0x0E, 0x3B, 0xFE, 0x75, 0xF8, 0xAA, 0xEE, 0x7D, 0x7D, 0x85, 0xC7, 0xD6,
+	0x98, 0x58, 0x42, 0xBF, 0x5A, 0x17, 0xF5, 0xA9, 0x2F, 0x45, 0x73, 0x81, 0x9F, 0xF6, 0xA6, 0xF8,
+	0x73, 0x6B, 0xA9, 0x6B, 0xB6, 0x72, 0xF8, 0xD7, 0xC3, 0x91, 0xDC, 0xF8, 0x6A, 0x39, 0xE5, 0xD4,
+	0x91, 0xAF, 0x50, 0x1B, 0x65, 0x82, 0x58, 0xA0, 0x9F, 0xBF, 0xCC, 0x62, 0x9A, 0x68, 0x61, 0x90,
+	0x2E, 0x4C, 0x72, 0xCD, 0x1C, 0x6D, 0xB5, 0xDD, 0x54, 0xF7, 0xC7, 0x2B, 0xC6, 0x4A, 0x30, 0xA9,
+	0xEC, 0xDA, 0x52, 0xB5, 0xBC, 0xEF, 0xB7, 0x5D, 0x2F, 0xD2, 0xF6, 0x4F, 0xA5, 0xCE, 0x67, 0x8B,
+	0xA4, 0xA4, 0xE0, 0x9E, 0xAA, 0xFF, 0x00, 0x86, 0xAF, 0xEE, 0x5B, 0x95, 0x61, 0xFD, 0xAF, 0xBE,
+	0x18, 0xCD, 0x1E, 0x98, 0xC3, 0xC7, 0x1E, 0x1F, 0x1F, 0xDA, 0xF7, 0x17, 0x16, 0x96, 0xC8, 0xF7,
+	0x41, 0x24, 0xF3, 0x6D, 0xEE, 0xA3, 0xB4, 0xB8, 0x57, 0x46, 0xC1, 0x8F, 0xCA, 0xB9, 0x9A, 0x28,
+	0x5C, 0xC8, 0x14, 0x2C, 0x92, 0xC6, 0xA7, 0x05, 0xD4, 0x1A, 0xFE, 0xC7, 0xC7, 0x5D, 0xA7, 0x4A,
+	0x49, 0xA4, 0x9E, 0x96, 0x76, 0x4F, 0x54, 0xDB, 0xBD, 0x9D, 0xFA, 0x59, 0xDE, 0xDA, 0xD9, 0x92,
+	0xF1, 0xB4, 0xB9, 0x79, 0xEF, 0xA5, 0xED, 0xE9, 0x6D, 0xEF, 0xD4, 0xDD, 0xF0, 0xCF, 0xC7, 0x0F,
+	0x08, 0x78, 0xCF, 0xC7, 0x5A, 0x87, 0x86, 0x34, 0xAF, 0x11, 0xE9, 0x37, 0xFA, 0xFE, 0x95, 0xE7,
+	0x1B, 0x9B, 0x18, 0x6E, 0x15, 0xA5, 0x4F, 0x22, 0x51, 0x0D, 0xC6, 0x07, 0xF1, 0x79, 0x33, 0x32,
+	0xC5, 0x2E, 0xDC, 0xF9, 0x52, 0x30, 0x47, 0xDA, 0xC4, 0x0A, 0xC6, 0xA6, 0x06, 0xBC, 0x69, 0x46,
+	0xB3, 0x83, 0x51, 0x6E, 0xD7, 0xD2, 0xDA, 0xFE, 0x3A, 0xF4, 0xB9, 0xA2, 0xAF, 0x07, 0x2E, 0x44,
+	0xF5, 0xFE, 0x9F, 0xE4, 0x75, 0x6A, 0x32, 0x39, 0xAE, 0x46, 0xDE, 0xFB, 0x1D, 0x09, 0x0B, 0x8F,
+	0xAD, 0x03, 0xB0, 0x9B, 0x7E, 0xBF, 0x9D, 0x16, 0xBE, 0x82, 0x3C, 0x73, 0xFE, 0x08, 0xFF, 0x00,
+	0xCF, 0x89, 0x3F, 0x6B, 0x2F, 0xFB, 0x2E, 0xFA, 0x8F, 0xFE, 0x98, 0x74, 0x2A, 0xFE, 0x89, 0xE1,
+	0x55, 0xFF, 0x00, 0x09, 0x14, 0x3F, 0xC3, 0xFA, 0x9F, 0x01, 0x98, 0xFF, 0x00, 0xBC, 0xCD, 0x79,
+	0x9F, 0x66, 0x1E, 0xD5, 0xF4, 0x67, 0x19, 0xF9, 0xD9, 0xFF, 0x00, 0x04, 0xB4, 0xE7, 0x5A, 0xFD,
+	0xAA, 0xFD, 0xBF, 0x68, 0xBF, 0x17, 0x8F, 0xD2, 0xCA, 0xBF, 0x0D, 0xF1, 0x0D, 0xFF, 0x00, 0xC2,
+	0xB7, 0xFD, 0xBB, 0x1F, 0xCD, 0x9F, 0x5B, 0x90, 0xAB, 0xD1, 0x92, 0xF3, 0x3E, 0xAA, 0xC7, 0xD6,
+	0xBE, 0x19, 0xE9, 0xA2, 0x3D, 0xE0, 0xC5, 0x2D, 0x42, 0xC7, 0x29, 0xF1, 0x67, 0xE2, 0xFE, 0x97,
+	0xF0, 0x6E, 0xD3, 0x43, 0x9F, 0x55, 0x8E, 0xED, 0xE2, 0xD7, 0xB5, 0x68, 0xF4, 0x78, 0x5A, 0x10,
+	0x84, 0x43, 0x23, 0xC5, 0x2C, 0xA1, 0xE4, 0x2E, 0xCA, 0x02, 0x05, 0x85, 0xB2, 0x41, 0x27, 0x24,
+	0x71, 0x8C, 0xE3, 0xAF, 0x07, 0x85, 0x78, 0x8A, 0x9E, 0xCD, 0x3F, 0xE9, 0xB4, 0x95, 0xBC, 0xEE,
+	0xF4, 0xEE, 0xCE, 0x7C, 0x45, 0x75, 0x4A, 0x0E, 0x4D, 0x6C, 0xAE, 0x73, 0xDE, 0x18, 0xFD, 0xB2,
+	0x3E, 0x18, 0x78, 0xAF, 0x5F, 0x8B, 0x48, 0xB6, 0xF1, 0xC7, 0x86, 0xD7, 0x57, 0x7B, 0x55, 0xBB,
+	0x6B, 0x49, 0x2F, 0xE2, 0x0F, 0x12, 0x1B, 0x34, 0xBE, 0xC1, 0x60, 0xC5, 0x37, 0x0B, 0x49, 0x16,
+	0x72, 0x03, 0x1F, 0xDD, 0x1F, 0x33, 0x94, 0x1B, 0xAB, 0x6A, 0xD9, 0x56, 0x2E, 0x9D, 0x39, 0x56,
+	0xE4, 0x7C, 0x89, 0xB5, 0x7E, 0x9A, 0x3E, 0x5E, 0xF7, 0x5E, 0xF6, 0x8F, 0x4D, 0x19, 0x9C, 0x31,
+	0x70, 0x94, 0x94, 0x1F, 0xC4, 0xED, 0xF7, 0xB5, 0x7B, 0x0F, 0xB7, 0xFD, 0xB0, 0x3E, 0x18, 0x5E,
+	0x78, 0x4A, 0x3D, 0x76, 0x0F, 0x1B, 0xE8, 0x37, 0x3A, 0x5C, 0xB7, 0x82, 0xC1, 0x25, 0x82, 0xE3,
+	0xCD, 0x67, 0x9C, 0xDA, 0x7D, 0xB8, 0x46, 0x11, 0x72, 0xE4, 0x9B, 0x3F, 0xF4, 0x91, 0x81, 0xCC,
+	0x1F, 0xBD, 0x19, 0x8F, 0xE6, 0xA6, 0xF2, 0x7C, 0x6F, 0x3F, 0xB1, 0x74, 0xE4, 0xA7, 0x6B, 0xD9,
+	0xDB, 0x65, 0xA3, 0x7B, 0xDA, 0xD7, 0xD3, 0x7B, 0xDF, 0x40, 0xFA, 0xED, 0x17, 0x17, 0x25, 0x2D,
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+	0xD3, 0xB5, 0xE5, 0x37, 0x4E, 0x2F, 0x87, 0xDA, 0x76, 0x3E, 0x9E, 0x90, 0x36, 0xC1, 0x00, 0x75,
+	0x72, 0xC3, 0xCB, 0x23, 0x07, 0xA2, 0x87, 0x10, 0x52, 0xA7, 0x59, 0x57, 0xF6, 0x6D, 0xCE, 0x52,
+	0x84, 0xA5, 0xAA, 0xB3, 0x71, 0x8C, 0xA1, 0xA6, 0x9A, 0x5D, 0x4A, 0xFD, 0x6C, 0xC5, 0x5B, 0x2E,
+	0x75, 0x61, 0xEC, 0x9B, 0xB2, 0x49, 0xC5, 0x7A, 0x3B, 0x7E, 0x3A, 0x1F, 0x5B, 0xC6, 0xA1, 0x50,
+	0x01, 0xD0, 0x57, 0xCB, 0x34, 0xA3, 0x68, 0xC5, 0x59, 0x2D, 0x0F, 0x5E, 0x2B, 0x7B, 0x8E, 0x3C,
+	0x52, 0xB5, 0xC6, 0xCF, 0x1C, 0x97, 0xFE, 0x52, 0xD5, 0xF0, 0x48, 0x7A, 0x7C, 0x36, 0xF1, 0xC7,
+	0xFE, 0x97, 0xF8, 0x5E, 0xBF, 0x5A, 0xF0, 0xC3, 0xE0, 0xC4, 0xFF, 0x00, 0xDB, 0x9F, 0xA9, 0xF2,
+	0xFC, 0x45, 0xBD, 0x3F, 0x99, 0xF6, 0x5D, 0x7E, 0xA4, 0x7C, 0xE1, 0xF1, 0x37, 0xED, 0x02, 0x73,
+	0xFF, 0x00, 0x05, 0xAA, 0xF8, 0x77, 0xFF, 0x00, 0x64, 0x4F, 0xC4, 0x7F, 0xFA, 0x7D, 0xD0, 0xEB,
+	0xF3, 0xFF, 0x00, 0x11, 0xAF, 0xFD, 0x97, 0x49, 0xFF, 0x00, 0xD3, 0xC5, 0x6F, 0xFC, 0x05, 0x9E,
+	0xCE, 0x43, 0xFE, 0xF0, 0xED, 0xDB, 0xF5, 0x3D, 0xC1, 0x47, 0xCA, 0x3E, 0x95, 0xF8, 0x9A, 0x77,
+	0x49, 0xA3, 0xEC, 0xD9, 0xF3, 0xDF, 0xC6, 0x3F, 0xD8, 0x2A, 0x0F, 0x8A, 0xBF, 0xB4, 0xE7, 0xFC,
+	0x2C, 0x44, 0xF1, 0x18, 0xB7, 0x86, 0xFA, 0xCF, 0x47, 0xB2, 0xD5, 0xB4, 0x5B, 0xC8, 0xF5, 0x09,
+	0x6D, 0xAF, 0x23, 0xD3, 0x6F, 0x2E, 0x6E, 0x62, 0x29, 0xF6, 0x5D, 0x42, 0xD6, 0x30, 0xCD, 0xF6,
+	0xA9, 0x14, 0xFD, 0xA6, 0x2B, 0xA5, 0x52, 0x91, 0xB2, 0xA2, 0xFE, 0xF1, 0x65, 0xFA, 0x2C, 0xB7,
+	0x3C, 0xFA, 0xAE, 0x1B, 0xD8, 0x3A, 0x77, 0xB4, 0x9C, 0x93, 0xB2, 0xD1, 0xD9, 0x2E, 0xA9, 0xDA,
+	0xD6, 0xD1, 0xAB, 0x33, 0xCB, 0xC6, 0x60, 0x3D, 0xB5, 0x4E, 0x74, 0xDA, 0xBA, 0xB3, 0xB3, 0xB6,
+	0x97, 0xBF, 0xF4, 0xB6, 0x3C, 0xE6, 0x6F, 0xF8, 0x25, 0x3E, 0xAF, 0xAC, 0x78, 0x96, 0xFF, 0x00,
+	0x56, 0xD5, 0xBE, 0x27, 0x59, 0xEB, 0x77, 0xF7, 0xDA, 0x3C, 0x5A, 0x54, 0x97, 0x37, 0xFE, 0x1D,
+	0xBC, 0xBC, 0xBB, 0xB9, 0x68, 0x75, 0x6B, 0x2D, 0x4A, 0x39, 0xA6, 0x9A, 0x6D, 0x4D, 0xD9, 0x08,
+	0x7B, 0x47, 0xDA, 0xB6, 0x26, 0xC9, 0x60, 0x96, 0x7F, 0x3A, 0xD8, 0x5B, 0x15, 0x2A, 0xDE, 0x84,
+	0x38, 0x9A, 0x14, 0xE8, 0xC6, 0x9D, 0x3A, 0x36, 0x49, 0xA7, 0x65, 0x65, 0xB4, 0x25, 0x17, 0x6D,
+	0x35, 0xBF, 0x35, 0xDB, 0x77, 0x6E, 0xD6, 0x77, 0x47, 0x3D, 0x4C, 0xAE, 0x52, 0x9B, 0x9F, 0x35,
+	0xB7, 0xF4, 0x77, 0x71, 0x7F, 0x2B, 0x5B, 0x45, 0xFA, 0xD8, 0xD7, 0x93, 0xFE, 0x09, 0x83, 0x75,
+	0xAA, 0xF8, 0x9B, 0x46, 0xD4, 0x35, 0xDF, 0x88, 0xF7, 0xFE, 0x29, 0x48, 0x2D, 0x2C, 0x6C, 0xF5,
+	0x78, 0x35, 0x44, 0xD5, 0xE5, 0x5D, 0x45, 0x2C, 0xF5, 0x5B, 0xCD, 0x42, 0x0F, 0x2C, 0x8D, 0x58,
+	0x1C, 0xA2, 0xDE, 0xB4, 0x01, 0xAF, 0x85, 0xFC, 0x81, 0x6D, 0xE0, 0x72, 0xEC, 0xFE, 0x71, 0x9B,
+	0x35, 0xC4, 0x90, 0x8D, 0x39, 0x42, 0x9D, 0x14, 0x95, 0xDB, 0x8E, 0x8A, 0xEB, 0x9A, 0x3C, 0xB2,
+	0x7B, 0x3E, 0x5B, 0xF6, 0x8B, 0x5F, 0x70, 0x7F, 0x65, 0xC9, 0xEF, 0x26, 0xD7, 0xAF, 0xCD, 0x7A,
+	0xEB, 0xDC, 0xEE, 0x3E, 0x28, 0x7E, 0xC2, 0x56, 0x3E, 0x39, 0xD4, 0x3C, 0x26, 0xFA, 0x6F, 0x8B,
+	0x3C, 0x47, 0x67, 0x6D, 0xE1, 0x9D, 0x4E, 0xC3, 0x54, 0x2B, 0xAD, 0xEA, 0x3A, 0x87, 0x89, 0x2E,
+	0xAE, 0x4D, 0xB6, 0xB9, 0xA3, 0xEA, 0xBB, 0x05, 0xCD, 0xED, 0xDB, 0xCB, 0x1A, 0x30, 0xD2, 0x7C,
+	0xA0, 0xA1, 0x8A, 0xA1, 0xB8, 0x32, 0x05, 0x3B, 0x4A, 0xBF, 0x1E, 0x17, 0x3E, 0x70, 0x84, 0xE1,
+	0x52, 0x29, 0xF3, 0x45, 0xC7, 0x44, 0xA3, 0xBC, 0x5A, 0xD5, 0x2D, 0xF7, 0xBF, 0xE1, 0xE6, 0xB5,
+	0xA9, 0x96, 0x29, 0x49, 0x34, 0xF6, 0xE6, 0xD3, 0xFC, 0x4A, 0xCF, 0xFE, 0x00, 0xCD, 0x23, 0xF6,
+	0x10, 0xB4, 0xD1, 0xFE, 0x1D, 0x6B, 0x9A, 0x52, 0x78, 0xB7, 0xC4, 0x1F, 0xDB, 0x3A, 0x8E, 0xBD,
+	0xAC, 0x6B, 0xF6, 0x37, 0x62, 0xF6, 0xF9, 0x34, 0xAB, 0x39, 0xAF, 0x7C, 0x41, 0x75, 0xAE, 0x40,
+	0x26, 0xD2, 0x45, 0xD8, 0xB4, 0xBA, 0x68, 0x26, 0xB8, 0x58, 0xDA, 0x47, 0x55, 0x92, 0x64, 0x88,
+	0x0D, 0xD1, 0x29, 0x55, 0x8F, 0x08, 0x67, 0x72, 0x8A, 0xA4, 0xA1, 0x05, 0xCB, 0x18, 0x42, 0x2E,
+	0xEA, 0xF2, 0xF7, 0x62, 0xA2, 0xFD, 0xED, 0xD5, 0xD6, 0xBE, 0x5F, 0x7D, 0xEE, 0x19, 0x72, 0x8B,
+	0x73, 0xEA, 0xDC, 0x9F, 0x97, 0xBD, 0xF9, 0xD8, 0xE4, 0x3E, 0x21, 0xFF, 0x00, 0xC1, 0x38, 0xFC,
+	0x43, 0xE3, 0xA9, 0xBC, 0x75, 0xAB, 0xC7, 0xF1, 0x2B, 0x4A, 0xB0, 0xF1, 0x7F, 0xC4, 0x9D, 0x33,
+	0xC4, 0x7A, 0x3E, 0xBB, 0x7C, 0x7C, 0x24, 0xF3, 0x58, 0x0B, 0x7D, 0x63, 0x4E, 0xD0, 0xF4, 0xF2,
+	0xD6, 0x96, 0xA6, 0xFC, 0x3C, 0x32, 0xC3, 0x0E, 0x81, 0x64, 0x55, 0xA5, 0x9E, 0x75, 0x77, 0x92,
+	0x72, 0xC9, 0x86, 0x44, 0x4E, 0xF8, 0xE7, 0xB4, 0x2D, 0x1A, 0x0A, 0x93, 0x74, 0xE3, 0xCA, 0xD6,
+	0xBA, 0xDE, 0x12, 0x72, 0x49, 0xBE, 0xCF, 0x99, 0xDD, 0x99, 0x7F, 0x67, 0x4B, 0x9F, 0xDA, 0xDF,
+	0xDE, 0xB5, 0xBF, 0xAF, 0xCC, 0xF7, 0x0F, 0x83, 0xDF, 0x06, 0x6E, 0x3E, 0x13, 0x78, 0xCF, 0xE2,
+	0x2E, 0xA2, 0xDA, 0xD4, 0x1A, 0x95, 0x8F, 0x8E, 0x3C, 0x40, 0xBA, 0xFD, 0xBD, 0xA8, 0xB0, 0x30,
+	0x4D, 0xA6, 0x39, 0xB1, 0xB6, 0xB5, 0x92, 0x37, 0x94, 0xCA, 0xC2, 0x60, 0xC6, 0xD8, 0x3A, 0x91,
+	0x1C, 0x65, 0x43, 0x95, 0x3B, 0xF1, 0xBA, 0xBC, 0x8C, 0xC3, 0x18, 0xB1, 0x2A, 0x2E, 0xD6, 0x6B,
+	0x9B, 0xFF, 0x00, 0x26, 0x9C, 0xE7, 0xFF, 0x00, 0xB7, 0xDB, 0xE4, 0x76, 0x61, 0xA8, 0xBA, 0x5A,
+	0x77, 0xB7, 0xE1, 0x15, 0x1F, 0xD0, 0xEF, 0x97, 0x9C, 0x57, 0x9B, 0x17, 0xD8, 0xEC, 0x67, 0x8D,
+	0xFF, 0x00, 0xC1, 0x2F, 0x07, 0xFC, 0x65, 0x1F, 0xED, 0x87, 0xFF, 0x00, 0x65, 0x1F, 0x4C, 0xFF,
+	0x00, 0xD4, 0x63, 0x47, 0xAF, 0xE8, 0x3E, 0x0E, 0x56, 0xC9, 0xB0, 0xF7, 0xED, 0xFA, 0xB3, 0xE0,
+	0xB3, 0x3F, 0xF7, 0xA9, 0xFA, 0x9F, 0x66, 0x57, 0xD4, 0x1C, 0x21, 0x40, 0x1F, 0x0E, 0xFE, 0xDE,
+	0x9E, 0x1F, 0xD7, 0xFF, 0x00, 0x66, 0xBF, 0xDB, 0xA3, 0xC2, 0xBF, 0xB4, 0x4C, 0x7E, 0x18, 0xF1,
+	0x1F, 0x8C, 0x7E, 0x1F, 0xCB, 0xE0, 0x99, 0xFC, 0x05, 0xE2, 0xD8, 0xFC, 0x3D, 0xA7, 0xC9, 0xA8,
+	0xEA, 0x7E, 0x18, 0x5F, 0xB7, 0xC7, 0x7B, 0x6D, 0xAA, 0x0B, 0x48, 0x43, 0x4D, 0x73, 0x6C, 0x0F,
+	0x9F, 0x1C, 0xE2, 0x25, 0x2F, 0x12, 0xEC, 0x90, 0x2B, 0xA8, 0x60, 0x3E, 0x5B, 0x8B, 0x72, 0x4A,
+	0xB9, 0x9E, 0x0D, 0x52, 0xA0, 0xD7, 0x34, 0x5A, 0x6A, 0xE7, 0xA1, 0x96, 0x62, 0xE3, 0x87, 0xAA,
+	0xE5, 0x2D, 0x9A, 0x39, 0x5F, 0xF8, 0x7C, 0xC7, 0xEC, 0xF6, 0x3A, 0x78, 0x9B, 0xC6, 0x47, 0xDC,
+	0x7C, 0x39, 0xF1, 0x37, 0xFF, 0x00, 0x2B, 0xEB, 0xF2, 0xA5, 0xC0, 0xD9, 0xCF, 0x5A, 0x5F, 0x8A,
+	0x3E, 0x95, 0xE7, 0x78, 0x55, 0xBB, 0x0F, 0xF8, 0x7C, 0xCF, 0xEC, 0xF7, 0xFF, 0x00, 0x43, 0x2F,
+	0x8C, 0xFF, 0x00, 0xF0, 0xDC, 0x78, 0x9B, 0xFF, 0x00, 0x95, 0xF4, 0x7F, 0xA8, 0xB9, 0xCF, 0xFC,
+	0xFA, 0xFC, 0x50, 0x7F, 0x6E, 0x61, 0x3F, 0x98, 0x0F, 0xFC, 0x16, 0x67, 0xF6, 0x7B, 0xFF, 0x00,
+	0xA1, 0x97, 0xC6, 0x7F, 0xF8, 0x6E, 0x3C, 0x4D, 0xFF, 0x00, 0xCA, 0xFA, 0x7F, 0xEA, 0x36, 0x73,
+	0xFF, 0x00, 0x3E, 0xBF, 0x14, 0x2F, 0xED, 0xCC, 0x27, 0xF3, 0x07, 0xFC, 0x3E, 0x67, 0xF6, 0x7B,
+	0xFF, 0x00, 0xA1, 0x97, 0xC6, 0x79, 0xFF, 0x00, 0xB2, 0x71, 0xE2, 0x6F, 0xFE, 0x57, 0xD2, 0x5C,
+	0x0B, 0x9C, 0x2F, 0xF9, 0x75, 0xFF, 0x00, 0x93, 0x20, 0xFE, 0xDC, 0xC2, 0x7F, 0x30, 0x87, 0xFE,
+	0x0B, 0x31, 0xFB, 0x3D, 0xE3, 0xFE, 0x46, 0x5F, 0x1A, 0x7F, 0xE1, 0xB8, 0xF1, 0x37, 0xFF, 0x00,
+	0x2B, 0xE9, 0xFF, 0x00, 0xA8, 0xB9, 0xC7, 0xFC, 0xFA, 0x5F, 0x7A, 0xFF, 0x00, 0x30, 0xFE, 0xDC,
+	0xC2, 0xDF, 0x59, 0x0B, 0xFF, 0x00, 0x0F, 0x99, 0xFD, 0x9E, 0xFF, 0x00, 0xE8, 0x65, 0xF1, 0x9F,
+	0xFE, 0x1B, 0x8F, 0x13, 0x7F, 0xF2, 0xBE, 0x8F, 0xF5, 0x1B, 0x3A, 0x5B, 0x53, 0xFC, 0x57, 0xF9,
+	0x87, 0xF6, 0xDE, 0x13, 0xF9, 0x83, 0xFE, 0x1F, 0x33, 0xFB, 0x3D, 0xFF, 0x00, 0xD0, 0xCB, 0xE3,
+	0x3F, 0xFC, 0x37, 0x1E, 0x26, 0xFF, 0x00, 0xE5, 0x7D, 0x2F, 0xF5, 0x17, 0x38, 0xFF, 0x00, 0x9F,
+	0x5F, 0x8A, 0x05, 0x9D, 0xE1, 0x17, 0xDA, 0x0F, 0xF8, 0x7C, 0xCF, 0xEC, 0xF7, 0xFF, 0x00, 0x43,
+	0x2F, 0x8C, 0xFF, 0x00, 0xF0, 0xDC, 0x78, 0x9B, 0xFF, 0x00, 0x95, 0xF4, 0x7F, 0xA8, 0xB9, 0xCF,
+	0xFC, 0xFA, 0xFC, 0x50, 0xFF, 0x00, 0xB7, 0x30, 0x9F, 0xCC, 0x2A, 0xFF, 0x00, 0xC1, 0x64, 0xBE,
+	0x03, 0x5E, 0x30, 0x86, 0xC3, 0x57, 0xF8, 0x81, 0xAA, 0x5F, 0xCA, 0x76, 0x5B, 0x59, 0x59, 0xFC,
+	0x34, 0xF1, 0x2C, 0x97, 0x37, 0x92, 0x1E, 0x16, 0x28, 0x94, 0xD8, 0x00, 0xCE, 0xC7, 0x0A, 0x01,
+	0x20, 0x12, 0x47, 0x22, 0xAA, 0x1C, 0x09, 0x9C, 0x39, 0x24, 0xE0, 0x97, 0x9B, 0x6A, 0xDF, 0x81,
+	0x32, 0xCE, 0xF0, 0xD6, 0xF7, 0x5D, 0xD9, 0xEB, 0x9F, 0xF0, 0x48, 0xEF, 0x83, 0xDE, 0x32, 0xF0,
+	0x1F, 0xC2, 0x3F, 0x88, 0xFE, 0x31, 0xF1, 0xCF, 0x87, 0x6E, 0xBC, 0x19, 0xAC, 0x7C, 0x67, 0xF8,
+	0x85, 0xA8, 0xF8, 0xEE, 0x0F, 0x0E, 0xDE, 0x3A, 0x35, 0xFE, 0x87, 0x65, 0x35, 0xB5, 0x9D, 0x9D,
+	0xAC, 0x37, 0x61, 0x0B, 0x22, 0x5C, 0xB4, 0x16, 0x31, 0xCB, 0x22, 0x2B, 0x1D, 0x8D, 0x31, 0x43,
+	0x86, 0x52, 0xA3, 0xF6, 0x9C, 0xA7, 0x01, 0xF5, 0x3C, 0x1D, 0x2C, 0x2A, 0x7F, 0x0A, 0xB7, 0xCC,
+	0xF9, 0x2C, 0x4D, 0x5F, 0x69, 0x5A, 0x53, 0x5D, 0x59, 0xF5, 0x79, 0x19, 0xAF, 0x4C, 0xC4, 0xFC,
+	0xD1, 0xB0, 0xF8, 0x81, 0x6F, 0xFF, 0x00, 0x04, 0xAC, 0xFD, 0xA3, 0x7E, 0x37, 0x69, 0x3F, 0x12,
+	0xBC, 0x3F, 0xE3, 0x5B, 0x5F, 0x87, 0xDF, 0x15, 0x3C, 0x77, 0x79, 0xF1, 0x0F, 0xC3, 0x3E, 0x33,
+	0xD2, 0xBC, 0x3D, 0x7B, 0xAE, 0xE9, 0x92, 0xCB, 0x7F, 0x6F, 0x6A, 0x2E, 0xB4, 0xCB, 0x9F, 0xB1,
+	0x43, 0x2C, 0xB6, 0xD7, 0x31, 0xCF, 0x04, 0xAD, 0x18, 0x91, 0x36, 0x49, 0x11, 0xC8, 0x7C, 0xA1,
+	0x07, 0xF3, 0x5E, 0x33, 0xE1, 0x4C, 0x56, 0x3F, 0x15, 0x1C, 0x5E, 0x11, 0x5F, 0x4B, 0x49, 0x5F,
+	0x5D, 0x36, 0xB7, 0x4F, 0xC4, 0xF7, 0x72, 0x9C, 0xC6, 0x9D, 0x08, 0xB8, 0x54, 0x3A, 0x2F, 0xF8,
+	0x7C, 0xD7, 0xEC, 0xF7, 0xFF, 0x00, 0x43, 0x2F, 0x8C, 0xCF, 0xFD, 0xD3, 0x8F, 0x13, 0x7F, 0xF2,
+	0xBE, 0xBE, 0x2D, 0x70, 0x36, 0x74, 0xD2, 0x72, 0xA5, 0x67, 0xEA, 0x8F, 0x63, 0xFB, 0x6F, 0x0A,
+	0xB7, 0x61, 0xFF, 0x00, 0x0F, 0x99, 0xFD, 0x9E, 0xFF, 0x00, 0xE8, 0x65, 0xF1, 0x9F, 0xFE, 0x1B,
+	0x8F, 0x13, 0x7F, 0xF2, 0xBE, 0x9F, 0xFA, 0x8D, 0x9C, 0xFF, 0x00, 0xCF, 0xAF, 0xC5, 0x07, 0xF6,
+	0xE6, 0x13, 0xF9, 0x80, 0xFF, 0x00, 0xC1, 0x66, 0x7F, 0x67, 0xBF, 0xFA, 0x19, 0x7C, 0x67, 0xFF,
+	0x00, 0x86, 0xE3, 0xC4, 0xDF, 0xFC, 0xAF, 0xA5, 0xFE, 0xA2, 0xE7, 0x1F, 0xF3, 0xEB, 0xF1, 0x5F,
+	0xE6, 0x2F, 0xED, 0xCC, 0x27, 0x71, 0x07, 0xFC, 0x16, 0x63, 0xF6, 0x7B, 0x1F, 0xF3, 0x33, 0x78,
+	0xCF, 0xFF, 0x00, 0x0D, 0xC7, 0x89, 0xBF, 0xF9, 0x5F, 0x42, 0xE0, 0x5C, 0xE7, 0xFE, 0x7D, 0x7F,
+	0xE4, 0xC8, 0x4F, 0x3B, 0xC2, 0x77, 0x17, 0xFE, 0x1F, 0x33, 0xFB, 0x3D, 0xFF, 0x00, 0xD0, 0xCD,
+	0xE3, 0x3F, 0xFC, 0x37, 0x1E, 0x25, 0xFF, 0x00, 0xE5, 0x7D, 0x1F, 0xEA, 0x36, 0x73, 0xD2, 0x8A,
+	0xFB, 0xD7, 0xF9, 0x87, 0xF6, 0xDE, 0x13, 0xB8, 0x1F, 0xF8, 0x2C, 0xC7, 0xEC, 0xF6, 0x47, 0xFC,
+	0x8C, 0xBE, 0x33, 0x3F, 0xF7, 0x4E, 0x3C, 0x4D, 0xFF, 0x00, 0xCA, 0xFA, 0x3F, 0xD4, 0x5C, 0xE3,
+	0xFE, 0x7D, 0x7E, 0x28, 0x7F, 0xDB, 0x98, 0x4E, 0xE1, 0xFF, 0x00, 0x0F, 0x99, 0xFD, 0x9E, 0xFF,
+	0x00, 0xE8, 0x65, 0xF1, 0x9F, 0xFE, 0x1B, 0x8F, 0x13, 0x7F, 0xF2, 0xBE, 0x8F, 0xF5, 0x1B, 0x39,
+	0xFF, 0x00, 0x9F, 0x5F, 0x8A, 0x1F, 0xF6, 0xE6, 0x13, 0xF9, 0x83, 0xFE, 0x1F, 0x33, 0xFB, 0x3D,
+	0xFF, 0x00, 0xD0, 0xCB, 0xE3, 0x3F, 0xFC, 0x37, 0x1E, 0x26, 0xFF, 0x00, 0xE5, 0x7D, 0x1F, 0xEA,
+	0x36, 0x73, 0xFF, 0x00, 0x3E, 0xBF, 0x15, 0xFE, 0x61, 0xFD, 0xB9, 0x84, 0xEE, 0x62, 0xFC, 0x46,
+	0xFF, 0x00, 0x82, 0xA3, 0xF8, 0x4B, 0xE3, 0x5F, 0xC3, 0xFD, 0x6F, 0xC2, 0xDF, 0x04, 0x7C, 0x3D,
+	0xF1, 0x03, 0xE2, 0x97, 0xC4, 0xBD, 0x76, 0xC6, 0x5B, 0x1D, 0x1B, 0x45, 0x8B, 0xC1, 0x7A, 0xCE,
+	0x97, 0x6C, 0xB3, 0x4A, 0xBE, 0x5A, 0xDC, 0x5E, 0x5D, 0xDE, 0x5B, 0x41, 0x05, 0xBD, 0xA4, 0x6C,
+	0xEA, 0xD2, 0x48, 0xD2, 0x03, 0xB4, 0x10, 0xB9, 0x62, 0x05, 0x77, 0xE5, 0x7C, 0x07, 0x99, 0x4B,
+	0x13, 0x4E, 0x58, 0x88, 0xA8, 0xC1, 0x34, 0xDE, 0xBD, 0x9D, 0xFA, 0x7A, 0x1C, 0xF8, 0xAC, 0xEB,
+	0x0F, 0x2A, 0x52, 0x8C, 0x1E, 0xAC, 0xFB, 0x67, 0xF6, 0x31, 0xF8, 0x0F, 0x71, 0xFB, 0x2E, 0x7E,
+	0xC8, 0x7F, 0x0B, 0xFE, 0x1A, 0xDD, 0x5F, 0xC3, 0xAA, 0xDD, 0xF8, 0x03, 0xC2, 0x9A, 0x5F, 0x87,
+	0x67, 0xBC, 0x89, 0x0A, 0x47, 0x75, 0x25, 0xA5, 0xA4, 0x50, 0x34, 0x8A, 0xA7, 0x90, 0xAC, 0xC8,
+	0x48, 0x07, 0x90, 0x08, 0xAF, 0xDB, 0x9D, 0xDF, 0xDE, 0x7C, 0x8A, 0x5D, 0xCD, 0x0F, 0xDA, 0x93,
+	0xE0, 0x7C, 0x3F, 0xB4, 0xC7, 0xEC, 0xCD, 0xF1, 0x17, 0xE1, 0xBD, 0xC5, 0xF4, 0x9A, 0x5D, 0xBF,
+	0xC4, 0x1F, 0x0C, 0x6A, 0x7E, 0x1A, 0x92, 0xF2, 0x34, 0x0E, 0xF6, 0x8B, 0x79, 0x69, 0x2D, 0xB1,
+	0x94, 0x29, 0xE1, 0x8A, 0x89, 0x0B, 0x63, 0xBE, 0x28, 0x4B, 0x5B, 0xB0, 0x77, 0xB6, 0x87, 0xC0,
+	0xDF, 0x03, 0x3F, 0xE0, 0xA3, 0x3A, 0x07, 0xEC, 0xAF, 0xF0, 0x67, 0xC2, 0x9F, 0x0E, 0x7E, 0x3D,
+	0xF8, 0x77, 0xC7, 0xBF, 0x0D, 0x3E, 0x25, 0xF8, 0x1B, 0x47, 0xB4, 0xD0, 0xB5, 0x3B, 0x4F, 0xF8,
+	0x43, 0xB5, 0x6D, 0x5B, 0x4E, 0xD5, 0xDA, 0xD6, 0x04, 0x83, 0xFB, 0x42, 0xC2, 0xF2, 0xC6, 0xDA,
+	0x68, 0x26, 0xB5, 0x9C, 0xC6, 0x59, 0x70, 0xC1, 0x90, 0xEE, 0x46, 0x19, 0x4C, 0x9F, 0xC5, 0xB3,
+	0xAE, 0x07, 0xCC, 0x5E, 0x32, 0x73, 0xC3, 0x41, 0x4A, 0x12, 0x6D, 0xAD, 0x57, 0x5F, 0x5B, 0x1F,
+	0x57, 0x82, 0xCE, 0x28, 0x42, 0x92, 0x85, 0x47, 0xAA, 0x3A, 0xAF, 0xF8, 0x7C, 0xD7, 0xEC, 0xF7,
+	0xFF, 0x00, 0x43, 0x2F, 0x8C, 0xFF, 0x00, 0xF0, 0xDC, 0x78, 0x9B, 0xFF, 0x00, 0x95, 0xF5, 0xE6,
+	0x7F, 0xA8, 0xB9, 0xCF, 0xFC, 0xFA, 0xFC, 0x51, 0xD7, 0xFD, 0xB9, 0x84, 0xEE, 0x1F, 0xF0, 0xF9,
+	0x9F, 0xD9, 0xEF, 0xFE, 0x86, 0x5F, 0x19, 0xFF, 0x00, 0xE1, 0xB8, 0xF1, 0x37, 0xFF, 0x00, 0x2B,
+	0xE9, 0x7F, 0xA8, 0xB9, 0xCF, 0xFC, 0xFB, 0xFC, 0x50, 0x9E, 0x79, 0x84, 0xFE, 0x60, 0x3F, 0xF0,
+	0x59, 0x9F, 0xD9, 0xEF, 0xFE, 0x86, 0x5F, 0x19, 0xFF, 0x00, 0xE1, 0xB8, 0xF1, 0x37, 0xFF, 0x00,
+	0x2B, 0xE8, 0x5C, 0x0B, 0x9C, 0x2F, 0xF9, 0x75, 0xF8, 0xA0, 0xFE, 0xDC, 0xC2, 0xFF, 0x00, 0x30,
+	0x9F, 0xF0, 0xF9, 0x7F, 0xD9, 0xEF, 0xFE, 0x86, 0x6F, 0x1A, 0x7F, 0xE1, 0xB9, 0xF1, 0x37, 0xFF,
+	0x00, 0x2B, 0xE9, 0x7F, 0xA8, 0xB9, 0xCF, 0xFC, 0xFA, 0x5F, 0x7A, 0xFF, 0x00, 0x30, 0xFE, 0xDC,
+	0xC2, 0x7F, 0x30, 0xBF, 0xF0, 0xF9, 0x8F, 0xD9, 0xEF, 0xFE, 0x86, 0x5F, 0x19, 0xFF, 0x00, 0xE1,
+	0xB8, 0xF1, 0x37, 0xFF, 0x00, 0x2B, 0xEA, 0x97, 0x03, 0x67, 0x2B, 0x6A, 0x5F, 0xF9, 0x32, 0x0F,
+	0xED, 0xBC, 0x27, 0xF3, 0x07, 0xFC, 0x3E, 0x63, 0xF6, 0x7B, 0xFF, 0x00, 0xA1, 0x97, 0xC6, 0x7F,
+	0xF8, 0x6E, 0x3C, 0x4D, 0xFF, 0x00, 0xCA, 0xFA, 0x9F, 0xF5, 0x17, 0x38, 0xD5, 0x7B, 0x2F, 0xC5,
+	0x0B, 0xFB, 0x6F, 0x09, 0xFC, 0xC1, 0xFF, 0x00, 0x0F, 0x99, 0xFD, 0x9E, 0xFF, 0x00, 0xE8, 0x65,
+	0xF1, 0x9F, 0xFE, 0x1B, 0x8F, 0x13, 0x7F, 0xF2, 0xBE, 0xAB, 0xFD, 0x46, 0xCE, 0x7F, 0xE7, 0xD7,
+	0xE2, 0x81, 0x67, 0x78, 0x44, 0xAD, 0xCC, 0x07, 0xFE, 0x0B, 0x33, 0xFB, 0x3D, 0xE3, 0xFE, 0x46,
+	0x5F, 0x19, 0xFF, 0x00, 0xE1, 0xB8, 0xF1, 0x37, 0xFF, 0x00, 0x2B, 0xE9, 0x3E, 0x06, 0xCE, 0x6C,
+	0xED, 0x4B, 0xF1, 0x5F, 0xE6, 0x3F, 0xED, 0xBC, 0x2B, 0xD9, 0x9C, 0xD7, 0x8A, 0xFE, 0x33, 0x8F,
+	0xF8, 0x2A, 0x17, 0xC5, 0xDF, 0x83, 0xBE, 0x12, 0xF8, 0x3F, 0xA0, 0xF8, 0xC3, 0x50, 0xF0, 0x8F,
+	0x84, 0x7E, 0x21, 0x68, 0xDE, 0x39, 0xF1, 0x97, 0x8D, 0x35, 0x7F, 0x0C, 0x5F, 0x68, 0xDA, 0x4E,
+	0x95, 0x6D, 0xA4, 0x4F, 0xF6, 0xD8, 0xEC, 0x21, 0x37, 0xA9, 0x04, 0x93, 0xDE, 0x5C, 0x5C, 0x25,
+	0xBA, 0x05, 0x89, 0x24, 0x11, 0xC7, 0x23, 0xBB, 0x60, 0x72, 0x3E, 0xC7, 0x83, 0x78, 0x4F, 0x17,
+	0x82, 0xC5, 0xBC, 0x66, 0x31, 0x72, 0xD9, 0x34, 0x95, 0xEE, 0xEE, 0xFD, 0x34, 0xB5, 0xBC, 0xCF,
+	0x27, 0x35, 0xCC, 0xA9, 0xD7, 0x82, 0xA7, 0x4C, 0xFD, 0x30, 0x51, 0x81, 0x5F, 0xA6, 0x9E, 0x09,
+	0xF3, 0x57, 0xFC, 0x15, 0x5B, 0xF6, 0x7B, 0xF1, 0x57, 0xC7, 0xAF, 0xD9, 0x97, 0x4D, 0xBB, 0xF0,
+	0x2E, 0x99, 0x16, 0xBF, 0xE3, 0x7F, 0x86, 0x9E, 0x2E, 0xD1, 0x3E, 0x20, 0x68, 0x5A, 0x2C, 0xB7,
+	0x6B, 0x67, 0x1E, 0xBB, 0x71, 0xA5, 0xDE, 0xC7, 0x70, 0xD6, 0x26, 0x66, 0x05, 0x63, 0x69, 0xA1,
+	0x13, 0x46, 0x8C, 0xC3, 0x68, 0x91, 0x90, 0x92, 0x06, 0x48, 0xE4, 0xC6, 0xE1, 0x96, 0x23, 0x0F,
+	0x3A, 0x2F, 0xED, 0x26, 0xBE, 0xF4, 0x69, 0x4A, 0x7C, 0x93, 0x52, 0xEC, 0x78, 0x2D, 0xAF, 0xFC,
+	0x16, 0x43, 0xE0, 0x95, 0x95, 0xAC, 0x31, 0x78, 0x81, 0xBE, 0x27, 0xF8, 0x3F, 0x5C, 0x11, 0xA9,
+	0xBD, 0xD0, 0xF5, 0xAF, 0x86, 0x9E, 0x22, 0x8F, 0x51, 0xD2, 0xA5, 0x23, 0x2D, 0x04, 0xEB, 0x1D,
+	0x94, 0x91, 0x89, 0x14, 0xF0, 0x76, 0x3B, 0x2F, 0x19, 0x0C, 0x46, 0x0D, 0x7E, 0x21, 0x53, 0x80,
+	0xB3, 0x78, 0x4B, 0x92, 0x30, 0x52, 0x4B, 0xAA, 0x7A, 0x7E, 0x36, 0x7F, 0x81, 0xF5, 0xD0, 0xCF,
+	0x70, 0xDC, 0xAB, 0x99, 0xB4, 0xC9, 0x3F, 0xE1, 0xF3, 0x3F, 0xB3, 0xDF, 0xFD, 0x0C, 0xBE, 0x33,
+	0xFF, 0x00, 0xC3, 0x71, 0xE2, 0x6F, 0xFE, 0x57, 0xD6, 0x6F, 0x81, 0xB3, 0x9B, 0x69, 0x4B, 0xF1,
+	0x45, 0x7F, 0x6E, 0x61, 0x3B, 0x87, 0xFC, 0x3E, 0x67, 0xF6, 0x7B, 0xFF, 0x00, 0xA1, 0x97, 0xC6,
+	0x7F, 0xF8, 0x6E, 0x3C, 0x4D, 0xFF, 0x00, 0xCA, 0xFA, 0x25, 0xC0, 0x99, 0xC3, 0x77, 0xF6, 0x5F,
+	0x8A, 0xFF, 0x00, 0x30, 0xFE, 0xDC, 0xC2, 0x7F, 0x30, 0x1F, 0xF8, 0x2C, 0xCF, 0xEC, 0xF7, 0xFF,
+	0x00, 0x43, 0x2F, 0x8C, 0xFF, 0x00, 0xF0, 0xDC, 0x78, 0x9B, 0xFF, 0x00, 0x95, 0xF4, 0x7F, 0xA8,
+	0xB9, 0xC5, 0xF5, 0xA5, 0xF8, 0xAF, 0xF3, 0x0F, 0xED, 0xCC, 0x27, 0x71, 0x07, 0xFC, 0x16, 0x63,
+	0xF6, 0x7C, 0xFF, 0x00, 0xA1, 0x9B, 0xC6, 0x9F, 0xF8, 0x6E, 0x3C, 0x4D, 0xFF, 0x00, 0xCA, 0xFA,
+	0x3F, 0xD4, 0x5C, 0xE3, 0xFE, 0x7D, 0x2F, 0xBD, 0x7F, 0x98, 0xBF, 0xB6, 0xF0, 0x9D, 0xC5, 0xFF,
+	0x00, 0x87, 0xCC, 0xFE, 0xCF, 0x7F, 0xF4, 0x32, 0xF8, 0xCF, 0xFF, 0x00, 0x0D, 0xC7, 0x89, 0xBF,
+	0xF9, 0x5F, 0x4F, 0xFD, 0x46, 0xCE, 0xB9, 0x6C, 0xA9, 0xFE, 0x2B, 0xFC, 0xC3, 0xFB, 0x6F, 0x0B,
+	0xD2, 0x41, 0xFF, 0x00, 0x0F, 0x99, 0xFD, 0x9E, 0xFF, 0x00, 0xE8, 0x65, 0xF1, 0x9F, 0xFE, 0x1B,
+	0x8F, 0x13, 0x7F, 0xF2, 0xBE, 0xA5, 0xF0, 0x26, 0x71, 0xD2, 0x92, 0xFB, 0xD7, 0xF9, 0x8F, 0xFB,
+	0x73, 0x09, 0xFC, 0xC1, 0xFF, 0x00, 0x0F, 0x99, 0xFD, 0x9E, 0xFF, 0x00, 0xE8, 0x65, 0xF1, 0x9F,
+	0xFE, 0x1B, 0x8F, 0x13, 0x7F, 0xF2, 0xBE, 0x9F, 0xFA, 0x8B, 0x9C, 0x2F, 0xF9, 0x75, 0xF8, 0xAF,
+	0xF3, 0x05, 0x9E, 0x61, 0x3F, 0x98, 0x46, 0xFF, 0x00, 0x82, 0xCC, 0xFE, 0xCF, 0x78, 0x3F, 0xF1,
+	0x52, 0xF8, 0xCC, 0x7F, 0xDD, 0x38, 0xF1, 0x37, 0xFF, 0x00, 0x2B, 0xE8, 0xFF, 0x00, 0x51, 0xB3,
+	0x84, 0xD3, 0xF6, 0x5B, 0x79, 0xAF, 0xF3, 0x1F, 0xF6, 0xDE, 0x15, 0xEC, 0xCE, 0x83, 0xF6, 0x38,
+	0xF1, 0x5E, 0xB5, 0xFB, 0x68, 0xFE, 0xDF, 0xD6, 0x3F, 0x17, 0x74, 0x4F, 0x0A, 0xF8, 0x97, 0x43,
+	0xF8, 0x3F, 0xF0, 0xE7, 0xC1, 0x5A, 0x9F, 0x86, 0xB4, 0x6D, 0x73, 0xC4, 0x3A, 0x4D, 0xC6, 0x8F,
+	0x73, 0xE3, 0x0D, 0x4B, 0x55, 0xBA, 0xD3, 0x2E, 0x26, 0x96, 0xCE, 0xD6, 0xE1, 0x56, 0x76, 0xB1,
+	0x82, 0x1D, 0x3A, 0x35, 0xF3, 0xE5, 0x8E, 0x2D, 0xF2, 0xCC, 0xCA, 0x81, 0xD6, 0x36, 0x61, 0xFA,
+	0x57, 0x05, 0xF0, 0xFD, 0x7C, 0xAE, 0x8D, 0x59, 0x62, 0x6D, 0xCF, 0x51, 0xAD, 0x13, 0xBD, 0x94,
+	0x76, 0xE9, 0xBF, 0x7F, 0xCC, 0xF9, 0xFC, 0xD7, 0x1B, 0x1C, 0x44, 0xE3, 0xC9, 0xB2, 0xB9, 0xF7,
+	0x6D, 0x7D, 0xA1, 0xE5, 0x1F, 0x14, 0x7F, 0xC1, 0x44, 0x34, 0x1F, 0x12, 0x7C, 0x07, 0xFD, 0xAE,
+	0xBE, 0x19, 0xFE, 0xD0, 0x76, 0x3E, 0x15, 0xD7, 0xFC, 0x69, 0xE0, 0xBD, 0x0F, 0xC3, 0x5A, 0xAF,
+	0x81, 0xBC, 0x61, 0x6D, 0xE1, 0xEB, 0x39, 0x35, 0x0D, 0x5F, 0x43, 0xB6, 0xBE, 0xBB, 0xB0, 0xBA,
+	0x83, 0x54, 0x8A, 0xCE, 0x35, 0x32, 0x5D, 0x5B, 0xC5, 0x2D, 0x91, 0x49, 0xD6, 0x2C, 0xCB, 0x1A,
+	0x4A, 0x24, 0x58, 0xE4, 0x54, 0x70, 0xBF, 0x31, 0xC5, 0x79, 0x2D, 0x5C, 0xD3, 0x2F, 0xF6, 0x14,
+	0x5F, 0xBF, 0x19, 0x29, 0x45, 0x3D, 0x35, 0x4A, 0xDF, 0x93, 0x3B, 0xF2, 0xEC, 0x52, 0xC3, 0xD6,
+	0x73, 0x96, 0xD6, 0x38, 0xA1, 0xFF, 0x00, 0x05, 0x9A, 0xFD, 0x9E, 0xC8, 0xE3, 0xC4, 0xDE, 0x32,
+	0x23, 0xD4, 0x7C, 0x39, 0xF1, 0x37, 0x3F, 0xF9, 0x4F, 0xAF, 0xCA, 0x5F, 0x03, 0x67, 0x3F, 0xF3,
+	0xEB, 0xF1, 0x47, 0xD2, 0xFF, 0x00, 0x6D, 0xE1, 0x56, 0xEF, 0xFA, 0xFB, 0xC3, 0xFE, 0x1F, 0x33,
+	0xFB, 0x3D, 0xFF, 0x00, 0xD0, 0xCB, 0xE3, 0x3F, 0xFC, 0x37, 0x1E, 0x26, 0xFF, 0x00, 0xE5, 0x7D,
+	0x27, 0xC0, 0xB9, 0xC3, 0xFF, 0x00, 0x97, 0x5F, 0x8A, 0xFF, 0x00, 0x30, 0x79, 0xE6, 0x13, 0xF9,
+	0x83, 0xFE, 0x1F, 0x33, 0xFB, 0x3D, 0xFF, 0x00, 0xD0, 0xCD, 0xE3, 0x4F, 0xFC, 0x37, 0x1E, 0x26,
+	0xFF, 0x00, 0xE5, 0x7D, 0x2F, 0xF5, 0x13, 0x38, 0x5B, 0x52, 0x5F, 0x7A, 0xFF, 0x00, 0x31, 0x7F,
+	0x6D, 0xE1, 0x3B, 0x89, 0xFF, 0x00, 0x0F, 0x98, 0xFD, 0x9E, 0xF3, 0xFF, 0x00, 0x23, 0x37, 0x8C,
+	0xFF, 0x00, 0xF0, 0xDC, 0x78, 0x9B, 0xFF, 0x00, 0x95, 0xF4, 0xFF, 0x00, 0xD4, 0x5C, 0xE1, 0x24,
+	0x95, 0x2D, 0xBC, 0xD7, 0xF9, 0x87, 0xF6, 0xDE, 0x13, 0xB8, 0xBF, 0xF0, 0xF9, 0x9F, 0xD9, 0xEC,
+	0x7F, 0xCC, 0xCB, 0xE3, 0x3F, 0xFC, 0x37, 0x1E, 0x26, 0xFF, 0x00, 0xE5, 0x7D, 0x0B, 0x81, 0xB3,
+	0x9F, 0xF9, 0xF5, 0xF8, 0xA1, 0xAC, 0xF3, 0x09, 0xFC, 0xC1, 0xFF, 0x00, 0x0F, 0x99, 0xFD, 0x9E,
+	0xFF, 0x00, 0xE8, 0x65, 0xF1, 0x9F, 0xFE, 0x1B, 0x8F, 0x13, 0x7F, 0xF2, 0xBE, 0x9B, 0xE0, 0x6C,
+	0xE9, 0xBE, 0x6F, 0x67, 0xAD, 0xDF, 0x55, 0xB7, 0xDE, 0x2F, 0xED, 0xBC, 0x27, 0xF3, 0x07, 0xFC,
+	0x3E, 0x67, 0xF6, 0x7B, 0xFF, 0x00, 0xA1, 0x97, 0xC6, 0x7F, 0xF8, 0x6E, 0x3C, 0x4D, 0xFF, 0x00,
+	0xCA, 0xFA, 0x4B, 0x81, 0x73, 0x84, 0xEE, 0xA9, 0x7E, 0x2B, 0xFC, 0xC3, 0xFB, 0x6F, 0x09, 0x7F,
+	0x88, 0x3F, 0xE1, 0xF3, 0x3F, 0xB3, 0xD9, 0x1C, 0xF8, 0x97, 0xC6, 0x7F, 0xF8, 0x6E, 0x3C, 0x4D,
+	0xFF, 0x00, 0xCA, 0xFA, 0x3F, 0xD4, 0x5C, 0xE2, 0xD6, 0x54, 0xBF, 0x15, 0xFE, 0x63, 0xFE, 0xDC,
+	0xC2, 0x7F, 0x30, 0xE8, 0x7F, 0xE0, 0xB2, 0x1F, 0x00, 0xAE, 0xE5, 0x48, 0x6D, 0x75, 0xCF, 0x1D,
+	0xDE, 0x5C, 0xCA, 0x42, 0x43, 0x6F, 0x6F, 0xF0, 0xD7, 0xC4, 0xCF, 0x35, 0xC3, 0x9E, 0x15, 0x11,
+	0x7E, 0xC1, 0xCB, 0x31, 0xE0, 0x0F, 0x53, 0x4E, 0x3C, 0x0B, 0x9D, 0x37, 0xCA, 0xA9, 0x6F, 0xE6,
+	0xB4, 0x14, 0xB3, 0xBC, 0x33, 0x5E, 0xEB, 0x6C, 0xF5, 0x6F, 0xF8, 0x25, 0x37, 0xC2, 0xCF, 0x18,
+	0xE9, 0x9A, 0x3F, 0xC5, 0x6F, 0x8A, 0x1E, 0x37, 0xF0, 0xCD, 0xF7, 0x81, 0x75, 0x0F, 0x8D, 0xDE,
+	0x31, 0xFF, 0x00, 0x84, 0x97, 0x4E, 0xF0, 0xC6, 0xA2, 0x47, 0xF6, 0x9E, 0x8D, 0xA6, 0x43, 0xA7,
+	0xDA, 0x69, 0xF6, 0x82, 0xF9, 0x57, 0x2B, 0x15, 0xDC, 0xA9, 0x69, 0xE7, 0xBC, 0x2A, 0xCD, 0xE5,
+	0x79, 0xAA, 0x8C, 0xDB, 0xD5, 0xD5, 0x7F, 0x67, 0xC9, 0x32, 0xFF, 0x00, 0xA8, 0x60, 0x69, 0x61,
+	0x1B, 0xBB, 0x8A, 0xB3, 0xF5, 0xBD, 0xF4, 0xF2, 0x3E, 0x4F, 0x15, 0x55, 0x55, 0xAB, 0x2A, 0x8B,
+	0xA9, 0xF5, 0xA5, 0x7A, 0xC6, 0x01, 0x40, 0x0D, 0x23, 0x2C, 0x41, 0xE4, 0x1A, 0x95, 0xD4, 0x4C,
+	0x6A, 0x9C, 0x0A, 0xA4, 0x85, 0x15, 0xA0, 0xB9, 0x3E, 0xA6, 0x81, 0xD8, 0x32, 0x7D, 0x4D, 0x01,
+	0x60, 0xC9, 0xF5, 0x34, 0x05, 0x83, 0x27, 0xD4, 0xD0, 0x16, 0x0C, 0x9F, 0x53, 0x40, 0x58, 0x32,
+	0x7D, 0x4D, 0x01, 0x60, 0xC9, 0xF5, 0x34, 0x05, 0x84, 0xC9, 0x34, 0xD0, 0xEC, 0x3A, 0x2F, 0xBB,
+	0xF9, 0xFF, 0x00, 0x3A, 0x96, 0x24, 0x3A, 0x98, 0xC6, 0x3F, 0xDF, 0xFC, 0x29, 0x45, 0xEA, 0xC1,
+	0x20, 0x63, 0x8C, 0x7D, 0x29, 0x47, 0xA8, 0x58, 0x32, 0x7D, 0x4D, 0x50, 0xAC, 0x19, 0x3E, 0xA6,
+	0x80, 0xB0, 0x64, 0xFA, 0x9A, 0x02, 0xC1, 0x93, 0xEA, 0x68, 0x0B, 0x06, 0x4F, 0xA9, 0xA0, 0x2C,
+	0x19, 0x3E, 0xA6, 0x80, 0xB0, 0x99, 0x3E, 0xB4, 0x0E, 0xC1, 0x8F, 0x94, 0x9E, 0xFC, 0x54, 0x49,
+	0x2B, 0xA0, 0x63, 0xD7, 0xEE, 0xD5, 0x80, 0x37, 0x4A, 0x00, 0x8C, 0xF0, 0xFC, 0x71, 0x9A, 0x49,
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+	0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF,
+	0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF,
+	0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF,
+	0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF,
+	0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE1, 0xC8, 0xFF, 0xED, 0xD3, 0xB1, 0xFF,
+	0xCA, 0x7E, 0x16, 0xFF, 0xBE, 0x71, 0x08, 0xFF, 0x9B, 0x5B, 0x05, 0xFF, 0x96, 0x57, 0x04, 0xBC,
+	0x25, 0x17, 0x02, 0x0F, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x72, 0x43, 0x05, 0x3E, 0x9B, 0x5C, 0x07, 0xF9,
+	0xAE, 0x68, 0x09, 0xFF, 0xC7, 0x77, 0x08, 0xFF, 0xD5, 0x99, 0x45, 0xFF, 0xEF, 0xDB, 0xBE, 0xFF,
+	0xEF, 0xDB, 0xBD, 0xFF, 0xEF, 0xDA, 0xBD, 0xFF, 0xEF, 0xDA, 0xBD, 0xFF, 0xF0, 0xDC, 0xBD, 0xFF,
+	0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF,
+	0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF,
+	0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF,
+	0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF,
+	0xF0, 0xDB, 0xBD, 0xFF, 0xEF, 0xDA, 0xBD, 0xFF, 0xEF, 0xDA, 0xBD, 0xFF, 0xEF, 0xDB, 0xBD, 0xFF,
+	0xEE, 0xD7, 0xB6, 0xFF, 0xCB, 0x82, 0x1B, 0xFF, 0xC4, 0x77, 0x0B, 0xFF, 0x9E, 0x5E, 0x07, 0xFF,
+	0x96, 0x5A, 0x04, 0xEA, 0x51, 0x2C, 0x06, 0x1B, 0x05, 0x03, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x0C, 0x07, 0x01, 0x06, 0x72, 0x43, 0x06, 0x40, 0x9E, 0x5E, 0x08, 0xFF, 0xB8, 0x6E, 0x0A, 0xFF,
+	0xC9, 0x7A, 0x0B, 0xFF, 0xD5, 0x97, 0x3F, 0xFF, 0xEF, 0xD8, 0xB8, 0xFF, 0xED, 0xD5, 0xB2, 0xFF,
+	0xED, 0xD5, 0xB2, 0xFF, 0xED, 0xD6, 0xB3, 0xFF, 0xED, 0xD6, 0xB3, 0xFF, 0xEE, 0xD6, 0xB3, 0xFF,
+	0xEE, 0xD6, 0xB3, 0xFF, 0xEE, 0xD6, 0xB3, 0xFF, 0xEE, 0xD7, 0xB3, 0xFF, 0xEE, 0xD7, 0xB3, 0xFF,
+	0xEE, 0xD7, 0xB3, 0xFF, 0xEE, 0xD7, 0xB3, 0xFF, 0xEE, 0xD7, 0xB3, 0xFF, 0xEE, 0xD7, 0xB3, 0xFF,
+	0xEE, 0xD7, 0xB3, 0xFF, 0xEE, 0xD7, 0xB3, 0xFF, 0xEE, 0xD7, 0xB3, 0xFF, 0xEE, 0xD7, 0xB3, 0xFF,
+	0xEE, 0xD7, 0xB3, 0xFF, 0xEE, 0xD7, 0xB3, 0xFF, 0xEE, 0xD6, 0xB3, 0xFF, 0xEE, 0xD6, 0xB3, 0xFF,
+	0xEE, 0xD6, 0xB3, 0xFF, 0xED, 0xD6, 0xB3, 0xFF, 0xED, 0xD6, 0xB2, 0xFF, 0xED, 0xD5, 0xB2, 0xFF,
+	0xED, 0xD5, 0xB2, 0xFF, 0xED, 0xD2, 0xAD, 0xFF, 0xCE, 0x86, 0x21, 0xFF, 0xC9, 0x7A, 0x0C, 0xFF,
+	0xA8, 0x65, 0x09, 0xFF, 0x98, 0x5C, 0x07, 0xDB, 0x00, 0x00, 0x00, 0x07, 0x06, 0x03, 0x01, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+	0x29, 0x18, 0x03, 0x1B, 0x9C, 0x5F, 0x09, 0xEB, 0xAF, 0x6B, 0x0B, 0xFF, 0xCA, 0x7D, 0x0D, 0xFF,
+	0xCC, 0x82, 0x17, 0xFF, 0xED, 0xD3, 0xAE, 0xFF, 0xEC, 0xD0, 0xA8, 0xFF, 0xEC, 0xD0, 0xA8, 0xFF,
+	0xEC, 0xD1, 0xA8, 0xFF, 0xEC, 0xD1, 0xA8, 0xFF, 0xEC, 0xD1, 0xA8, 0xFF, 0xEC, 0xD1, 0xA8, 0xFF,
+	0xED, 0xD2, 0xAA, 0xFF, 0xED, 0xD2, 0xA9, 0xFF, 0xED, 0xD2, 0xA9, 0xFF, 0xED, 0xD2, 0xA9, 0xFF,
+	0xED, 0xD2, 0xA9, 0xFF, 0xED, 0xD2, 0xA9, 0xFF, 0xED, 0xD2, 0xA9, 0xFF, 0xED, 0xD2, 0xA9, 0xFF,
+	0xED, 0xD2, 0xA9, 0xFF, 0xED, 0xD2, 0xA9, 0xFF, 0xED, 0xD2, 0xA9, 0xFF, 0xED, 0xD2, 0xA9, 0xFF,
+	0xED, 0xD2, 0xA9, 0xFF, 0xED, 0xD2, 0xA9, 0xFF, 0xED, 0xD2, 0xA9, 0xFF, 0xED, 0xD2, 0xA9, 0xFF,
+	0xEC, 0xD1, 0xA8, 0xFF, 0xEC, 0xD1, 0xA8, 0xFF, 0xEC, 0xD1, 0xA8, 0xFF, 0xEC, 0xD1, 0xA8, 0xFF,
+	0xEC, 0xD0, 0xA8, 0xFF, 0xEC, 0xD0, 0xA7, 0xFF, 0xE5, 0xC0, 0x89, 0xFF, 0xCA, 0x7C, 0x0C, 0xFF,
+	0xCB, 0x7D, 0x0E, 0xFF, 0xA4, 0x63, 0x0A, 0xFF, 0x9A, 0x5B, 0x08, 0xC7, 0x00, 0x00, 0x00, 0x0E,
+	0x14, 0x0C, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x02, 0x00, 0x02, 0x13, 0x0B, 0x01, 0x14,
+	0x9C, 0x60, 0x0B, 0xE6, 0xAE, 0x6A, 0x0B, 0xFF, 0xCC, 0x7F, 0x0F, 0xFF, 0xCB, 0x7F, 0x0F, 0xFF,
+	0xE3, 0xBB, 0x7E, 0xFF, 0xEA, 0xCB, 0x9D, 0xFF, 0xEA, 0xCB, 0x9D, 0xFF, 0xEA, 0xCC, 0x9E, 0xFF,
+	0xEA, 0xCC, 0x9E, 0xFF, 0xEA, 0xCC, 0x9E, 0xFF, 0xEA, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9F, 0xFF,
+	0xEB, 0xCD, 0x9F, 0xFF, 0xEB, 0xCD, 0x9F, 0xFF, 0xEB, 0xCD, 0x9F, 0xFF, 0xEB, 0xCD, 0x9F, 0xFF,
+	0xEB, 0xCE, 0x9F, 0xFF, 0xEB, 0xCE, 0x9F, 0xFF, 0xEB, 0xCE, 0x9F, 0xFF, 0xEB, 0xCE, 0x9F, 0xFF,
+	0xEB, 0xCE, 0x9F, 0xFF, 0xEB, 0xCE, 0x9F, 0xFF, 0xEB, 0xCE, 0x9F, 0xFF, 0xEB, 0xCE, 0x9F, 0xFF,
+	0xEB, 0xCD, 0x9F, 0xFF, 0xEB, 0xCD, 0x9F, 0xFF, 0xEB, 0xCD, 0x9F, 0xFF, 0xEB, 0xCD, 0x9F, 0xFF,
+	0xEA, 0xCD, 0x9F, 0xFF, 0xEA, 0xCD, 0x9E, 0xFF, 0xEA, 0xCC, 0x9E, 0xFF, 0xEA, 0xCC, 0x9E, 0xFF,
+	0xEA, 0xCB, 0x9D, 0xFF, 0xEA, 0xCB, 0x9D, 0xFF, 0xEA, 0xCD, 0xA0, 0xFF, 0xD9, 0xA2, 0x50, 0xFF,
+	0xCB, 0x7E, 0x0D, 0xFF, 0xC7, 0x7B, 0x0E, 0xFF, 0xA0, 0x62, 0x0A, 0xFF, 0x8C, 0x55, 0x09, 0x84,
+	0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x93, 0x5A, 0x08, 0x9E,
+	0xA6, 0x67, 0x0B, 0xFF, 0xCA, 0x7E, 0x0F, 0xFF, 0xCC, 0x80, 0x10, 0xFF, 0xD1, 0x8C, 0x23, 0xFF,
+	0xE8, 0xC8, 0x96, 0xFF, 0xE8, 0xC7, 0x94, 0xFF, 0xE8, 0xC7, 0x94, 0xFF, 0xE8, 0xC7, 0x94, 0xFF,
+	0xE8, 0xC8, 0x95, 0xFF, 0xEA, 0xC8, 0x95, 0xFF, 0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC9, 0x95, 0xFF,
+	0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC9, 0x96, 0xFF, 0xE9, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF,
+	0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF,
+	0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF,
+	0xEA, 0xCA, 0x96, 0xFF, 0xE9, 0xCA, 0x96, 0xFF, 0xE9, 0xC9, 0x96, 0xFF, 0xE9, 0xC9, 0x95, 0xFF,
+	0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC8, 0x95, 0xFF, 0xE9, 0xC8, 0x95, 0xFF, 0xE8, 0xC8, 0x95, 0xFF,
+	0xE8, 0xC7, 0x94, 0xFF, 0xE8, 0xC7, 0x94, 0xFF, 0xE7, 0xC7, 0x94, 0xFF, 0xE7, 0xC5, 0x91, 0xFF,
+	0xCE, 0x85, 0x17, 0xFF, 0xCC, 0x80, 0x10, 0xFF, 0xC3, 0x7A, 0x0F, 0xFF, 0xA3, 0x65, 0x0B, 0xFF,
+	0x7E, 0x4B, 0x06, 0x59, 0x08, 0x05, 0x01, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x05, 0x03, 0x00, 0x07, 0x5F, 0x3A, 0x07, 0x3E, 0xA7, 0x68, 0x0C, 0xFF,
+	0xC9, 0x7E, 0x11, 0xFF, 0xCD, 0x82, 0x12, 0xFF, 0xCD, 0x83, 0x11, 0xFF, 0xE1, 0xB4, 0x6F, 0xFF,
+	0xE6, 0xC3, 0x8B, 0xFF, 0xE6, 0xC3, 0x8A, 0xFF, 0xE7, 0xC3, 0x8A, 0xFF, 0xE7, 0xC4, 0x8B, 0xFF,
+	0xE7, 0xC4, 0x8B, 0xFF, 0xE7, 0xC5, 0x8B, 0xFF, 0xE8, 0xC5, 0x8C, 0xFF, 0xE8, 0xC6, 0x8C, 0xFF,
+	0xE8, 0xC6, 0x8C, 0xFF, 0xE8, 0xC6, 0x8C, 0xFF, 0xE8, 0xC5, 0x8C, 0xFF, 0xE8, 0xC7, 0x8D, 0xFF,
+	0xE9, 0xC7, 0x8D, 0xFF, 0xE9, 0xC7, 0x8D, 0xFF, 0xE9, 0xC7, 0x8D, 0xFF, 0xE9, 0xC7, 0x8D, 0xFF,
+	0xE9, 0xC7, 0x8D, 0xFF, 0xE9, 0xC7, 0x8D, 0xFF, 0xE9, 0xC7, 0x8D, 0xFF, 0xE9, 0xC7, 0x8D, 0xFF,
+	0xE8, 0xC6, 0x8C, 0xFF, 0xE8, 0xC6, 0x8C, 0xFF, 0xE8, 0xC6, 0x8C, 0xFF, 0xE8, 0xC6, 0x8C, 0xFF,
+	0xE8, 0xC5, 0x8C, 0xFF, 0xE8, 0xC5, 0x8C, 0xFF, 0xE7, 0xC5, 0x8B, 0xFF, 0xE7, 0xC3, 0x8B, 0xFF,
+	0xE7, 0xC4, 0x8B, 0xFF, 0xE7, 0xC3, 0x8A, 0xFF, 0xE6, 0xC3, 0x8A, 0xFF, 0xE6, 0xC2, 0x8A, 0xFF,
+	0xD5, 0x94, 0x32, 0xFF, 0xCD, 0x83, 0x12, 0xFF, 0xCD, 0x82, 0x11, 0xFF, 0xB2, 0x6F, 0x0E, 0xFF,
+	0x9D, 0x61, 0x0B, 0xD6, 0x00, 0x00, 0x00, 0x0F, 0x01, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x10, 0x99, 0x60, 0x0C, 0xBC, 0xAE, 0x6D, 0x0F, 0xFF,
+	0xCE, 0x84, 0x13, 0xFF, 0xCF, 0x85, 0x14, 0xFF, 0xD1, 0x8A, 0x1C, 0xFF, 0xE6, 0xBE, 0x7E, 0xFF,
+	0xE6, 0xBF, 0x81, 0xFF, 0xE6, 0xC0, 0x81, 0xFF, 0xE7, 0xC0, 0x82, 0xFF, 0xE7, 0xC1, 0x83, 0xFF,
+	0xE7, 0xC1, 0x83, 0xFF, 0xE7, 0xC2, 0x83, 0xFF, 0xE8, 0xC2, 0x83, 0xFF, 0xE8, 0xC2, 0x84, 0xFF,
+	0xE8, 0xC3, 0x84, 0xFF, 0xE8, 0xC3, 0x84, 0xFF, 0xE8, 0xC3, 0x84, 0xFF, 0xE8, 0xC3, 0x84, 0xFF,
+	0xE9, 0xC4, 0x85, 0xFF, 0xE9, 0xC4, 0x85, 0xFF, 0xE9, 0xC4, 0x85, 0xFF, 0xE9, 0xC4, 0x85, 0xFF,
+	0xE9, 0xC4, 0x85, 0xFF, 0xE9, 0xC4, 0x85, 0xFF, 0xE9, 0xC4, 0x85, 0xFF, 0xE8, 0xC4, 0x84, 0xFF,
+	0xE8, 0xC4, 0x84, 0xFF, 0xE8, 0xC3, 0x84, 0xFF, 0xE8, 0xC3, 0x84, 0xFF, 0xE8, 0xC3, 0x84, 0xFF,
+	0xE8, 0xC2, 0x84, 0xFF, 0xE8, 0xC2, 0x83, 0xFF, 0xE7, 0xC1, 0x83, 0xFF, 0xE7, 0xC1, 0x83, 0xFF,
+	0xE7, 0xC1, 0x82, 0xFF, 0xE6, 0xC0, 0x81, 0xFF, 0xE6, 0xC0, 0x81, 0xFF, 0xE6, 0xBF, 0x81, 0xFF,
+	0xE0, 0xAE, 0x62, 0xFF, 0xCE, 0x83, 0x10, 0xFF, 0xCE, 0x85, 0x13, 0xFF, 0xCE, 0x84, 0x11, 0xFF,
+	0xA9, 0x69, 0x0D, 0xFF, 0x84, 0x52, 0x09, 0x7E, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x09, 0x5F, 0x3C, 0x08, 0x4C, 0xA7, 0x6A, 0x0E, 0xFF, 0xCC, 0x83, 0x12, 0xFF,
+	0xD0, 0x86, 0x15, 0xFF, 0xD0, 0x88, 0x15, 0xFF, 0xD3, 0x8F, 0x22, 0xFF, 0xE4, 0xBA, 0x76, 0xFF,
+	0xE5, 0xBB, 0x77, 0xFF, 0xE5, 0xBC, 0x78, 0xFF, 0xE5, 0xBD, 0x78, 0xFF, 0xE5, 0xBD, 0x79, 0xFF,
+	0xE6, 0xBE, 0x79, 0xFF, 0xE6, 0xBE, 0x79, 0xFF, 0xE7, 0xBE, 0x7A, 0xFF, 0xE7, 0xBF, 0x7A, 0xFF,
+	0xE7, 0xC0, 0x7A, 0xFF, 0xE7, 0xC0, 0x7A, 0xFF, 0xE7, 0xC0, 0x7A, 0xFF, 0xE7, 0xC1, 0x7A, 0xFF,
+	0xE8, 0xC1, 0x7B, 0xFF, 0xE8, 0xC1, 0x7B, 0xFF, 0xE8, 0xC1, 0x7B, 0xFF, 0xE8, 0xC1, 0x7B, 0xFF,
+	0xE8, 0xC1, 0x7B, 0xFF, 0xE8, 0xC1, 0x7B, 0xFF, 0xE8, 0xC1, 0x7B, 0xFF, 0xE8, 0xC1, 0x7B, 0xFF,
+	0xE7, 0xC1, 0x7A, 0xFF, 0xE7, 0xC0, 0x7A, 0xFF, 0xE7, 0xC0, 0x7A, 0xFF, 0xE7, 0xBF, 0x7A, 0xFF,
+	0xE7, 0xBF, 0x7A, 0xFF, 0xE7, 0xBF, 0x79, 0xFF, 0xE6, 0xBE, 0x79, 0xFF, 0xE6, 0xBE, 0x79, 0xFF,
+	0xE5, 0xBC, 0x78, 0xFF, 0xE5, 0xBD, 0x78, 0xFF, 0xE5, 0xBC, 0x78, 0xFF, 0xE4, 0xBB, 0x77, 0xFF,
+	0xE2, 0xB6, 0x6D, 0xFF, 0xCF, 0x85, 0x11, 0xFF, 0xD0, 0x87, 0x15, 0xFF, 0xCF, 0x86, 0x14, 0xFF,
+	0xBB, 0x78, 0x10, 0xFF, 0xA4, 0x68, 0x0D, 0xED, 0x17, 0x0F, 0x02, 0x1F, 0x05, 0x03, 0x00, 0x04,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+	0x0D, 0x08, 0x02, 0x1A, 0xA4, 0x68, 0x0D, 0xE4, 0xBA, 0x77, 0x11, 0xFF, 0xD0, 0x87, 0x16, 0xFF,
+	0xD0, 0x89, 0x16, 0xFF, 0xD1, 0x8A, 0x17, 0xFF, 0xD5, 0x93, 0x27, 0xFF, 0xE4, 0xB7, 0x6E, 0xFF,
+	0xE4, 0xB8, 0x6E, 0xFF, 0xE4, 0xB9, 0x6F, 0xFF, 0xE5, 0xB9, 0x70, 0xFF, 0xE5, 0xBA, 0x70, 0xFF,
+	0xE6, 0xBB, 0x71, 0xFF, 0xE6, 0xBB, 0x71, 0xFF, 0xE6, 0xBC, 0x72, 0xFF, 0xE6, 0xBC, 0x72, 0xFF,
+	0xE7, 0xBD, 0x72, 0xFF, 0xE7, 0xBD, 0x72, 0xFF, 0xE7, 0xBD, 0x73, 0xFF, 0xE7, 0xBE, 0x73, 0xFF,
+	0xE7, 0xBE, 0x73, 0xFF, 0xE7, 0xBE, 0x73, 0xFF, 0xE7, 0xBE, 0x73, 0xFF, 0xE7, 0xBF, 0x73, 0xFF,
+	0xE7, 0xBF, 0x73, 0xFF, 0xE7, 0xBE, 0x73, 0xFF, 0xE7, 0xBE, 0x73, 0xFF, 0xE7, 0xBE, 0x73, 0xFF,
+	0xE7, 0xBE, 0x73, 0xFF, 0xE7, 0xBD, 0x73, 0xFF, 0xE7, 0xBD, 0x72, 0xFF, 0xE6, 0xBD, 0x72, 0xFF,
+	0xE6, 0xBC, 0x72, 0xFF, 0xE6, 0xBB, 0x72, 0xFF, 0xE6, 0xBB, 0x71, 0xFF, 0xE5, 0xBA, 0x71, 0xFF,
+	0xE5, 0xBA, 0x70, 0xFF, 0xE4, 0xB9, 0x70, 0xFF, 0xE4, 0xB9, 0x6F, 0xFF, 0xE4, 0xB8, 0x6E, 0xFF,
+	0xE4, 0xB9, 0x73, 0xFF, 0xD1, 0x8A, 0x14, 0xFF, 0xD1, 0x8A, 0x17, 0xFF, 0xD0, 0x88, 0x16, 0xFF,
+	0xD0, 0x87, 0x15, 0xFF, 0xAB, 0x6D, 0x0F, 0xFF, 0x7D, 0x4F, 0x0B, 0x73, 0x00, 0x00, 0x00, 0x0B,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09,
+	0x30, 0x1E, 0x04, 0x36, 0xA9, 0x6C, 0x10, 0xFB, 0xCA, 0x84, 0x15, 0xFF, 0xD1, 0x8A, 0x17, 0xFF,
+	0xD2, 0x8C, 0x18, 0xFF, 0xD3, 0x8D, 0x19, 0xFF, 0xD7, 0x95, 0x27, 0xFF, 0xE2, 0xB4, 0x64, 0xFF,
+	0xE3, 0xB5, 0x66, 0xFF, 0xE3, 0xB5, 0x67, 0xFF, 0xE4, 0xB6, 0x67, 0xFF, 0xE4, 0xB8, 0x67, 0xFF,
+	0xE5, 0xB8, 0x68, 0xFF, 0xE5, 0xB9, 0x69, 0xFF, 0xE5, 0xBA, 0x69, 0xFF, 0xE5, 0xBA, 0x69, 0xFF,
+	0xE6, 0xBA, 0x69, 0xFF, 0xE6, 0xBB, 0x6A, 0xFF, 0xE6, 0xBB, 0x69, 0xFF, 0xE6, 0xBB, 0x6B, 0xFF,
+	0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF,
+	0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF, 0xE6, 0xBB, 0x6B, 0xFF,
+	0xE6, 0xBB, 0x6A, 0xFF, 0xE6, 0xBB, 0x6A, 0xFF, 0xE6, 0xBA, 0x6A, 0xFF, 0xE5, 0xBA, 0x69, 0xFF,
+	0xE5, 0xBA, 0x69, 0xFF, 0xE5, 0xB9, 0x69, 0xFF, 0xE5, 0xB8, 0x68, 0xFF, 0xE5, 0xB8, 0x68, 0xFF,
+	0xE4, 0xB7, 0x67, 0xFF, 0xE3, 0xB6, 0x67, 0xFF, 0xE3, 0xB5, 0x66, 0xFF, 0xE3, 0xB5, 0x66, 0xFF,
+	0xE3, 0xB5, 0x69, 0xFF, 0xD3, 0x8C, 0x16, 0xFF, 0xD3, 0x8D, 0x19, 0xFF, 0xD2, 0x8B, 0x17, 0xFF,
+	0xD2, 0x8A, 0x17, 0xFF, 0xC1, 0x7D, 0x14, 0xFF, 0xA4, 0x6A, 0x0C, 0xF4, 0x00, 0x00, 0x00, 0x16,
+	0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+	0x8B, 0x59, 0x0E, 0x9D, 0xB0, 0x71, 0x12, 0xFF, 0xD3, 0x8C, 0x17, 0xFF, 0xD3, 0x8D, 0x19, 0xFF,
+	0xD4, 0x8E, 0x1A, 0xFF, 0xD4, 0x8F, 0x1B, 0xFF, 0xD6, 0x95, 0x24, 0xFF, 0xE1, 0xB1, 0x5C, 0xFF,
+	0xE2, 0xB1, 0x5D, 0xFF, 0xE3, 0xB3, 0x5D, 0xFF, 0xE3, 0xB4, 0x5E, 0xFF, 0xE3, 0xB4, 0x5F, 0xFF,
+	0xE3, 0xB5, 0x5F, 0xFF, 0xE4, 0xB6, 0x60, 0xFF, 0xE5, 0xB6, 0x60, 0xFF, 0xE5, 0xB7, 0x60, 0xFF,
+	0xE5, 0xB7, 0x61, 0xFF, 0xE6, 0xB8, 0x61, 0xFF, 0xE6, 0xB9, 0x62, 0xFF, 0xE6, 0xB9, 0x62, 0xFF,
+	0xE6, 0xB9, 0x62, 0xFF, 0xE6, 0xB9, 0x62, 0xFF, 0xE6, 0xB9, 0x62, 0xFF, 0xE6, 0xB9, 0x63, 0xFF,
+	0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x62, 0xFF, 0xE6, 0xB9, 0x62, 0xFF, 0xE6, 0xB9, 0x62, 0xFF,
+	0xE6, 0xB9, 0x62, 0xFF, 0xE6, 0xB8, 0x62, 0xFF, 0xE6, 0xB8, 0x61, 0xFF, 0xE5, 0xB7, 0x61, 0xFF,
+	0xE5, 0xB6, 0x60, 0xFF, 0xE4, 0xB6, 0x60, 0xFF, 0xE4, 0xB6, 0x60, 0xFF, 0xE3, 0xB5, 0x5F, 0xFF,
+	0xE3, 0xB4, 0x5E, 0xFF, 0xE3, 0xB4, 0x5E, 0xFF, 0xE3, 0xB2, 0x5D, 0xFF, 0xE2, 0xB1, 0x5D, 0xFF,
+	0xE1, 0xAE, 0x57, 0xFF, 0xD4, 0x8F, 0x18, 0xFF, 0xD4, 0x8F, 0x1B, 0xFF, 0xD3, 0x8E, 0x1A, 0xFF,
+	0xD2, 0x8C, 0x18, 0xFF, 0xCD, 0x87, 0x17, 0xFF, 0xAF, 0x71, 0x12, 0xFF, 0x64, 0x42, 0x0A, 0x57,
+	0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x1D,
+	0xA6, 0x6E, 0x10, 0xF4, 0xC1, 0x7F, 0x16, 0xFF, 0xD4, 0x8E, 0x1A, 0xFF, 0xD4, 0x8F, 0x1B, 0xFF,
+	0xD5, 0x91, 0x1B, 0xFF, 0xD6, 0x92, 0x1D, 0xFF, 0xD7, 0x96, 0x21, 0xFF, 0xE1, 0xAE, 0x53, 0xFF,
+	0xE2, 0xAF, 0x54, 0xFF, 0xE2, 0xB0, 0x55, 0xFF, 0xE2, 0xB1, 0x56, 0xFF, 0xE3, 0xB2, 0x56, 0xFF,
+	0xE3, 0xB3, 0x57, 0xFF, 0xE4, 0xB3, 0x57, 0xFF, 0xE4, 0xB4, 0x58, 0xFF, 0xE5, 0xB5, 0x58, 0xFF,
+	0xE5, 0xB6, 0x59, 0xFF, 0xE5, 0xB6, 0x59, 0xFF, 0xE5, 0xB7, 0x59, 0xFF, 0xE5, 0xB6, 0x59, 0xFF,
+	0xE6, 0xB6, 0x5A, 0xFF, 0xE6, 0xB6, 0x5A, 0xFF, 0xE6, 0xB6, 0x5A, 0xFF, 0xE6, 0xB7, 0x5A, 0xFF,
+	0xE6, 0xB7, 0x5A, 0xFF, 0xE6, 0xB6, 0x5A, 0xFF, 0xE6, 0xB6, 0x5A, 0xFF, 0xE5, 0xB6, 0x5A, 0xFF,
+	0xE5, 0xB6, 0x59, 0xFF, 0xE5, 0xB6, 0x59, 0xFF, 0xE5, 0xB6, 0x59, 0xFF, 0xE5, 0xB5, 0x59, 0xFF,
+	0xE5, 0xB5, 0x58, 0xFF, 0xE4, 0xB3, 0x58, 0xFF, 0xE4, 0xB4, 0x57, 0xFF, 0xE3, 0xB2, 0x56, 0xFF,
+	0xE3, 0xB2, 0x56, 0xFF, 0xE2, 0xB0, 0x56, 0xFF, 0xE1, 0xB0, 0x54, 0xFF, 0xE2, 0xAE, 0x54, 0xFF,
+	0xDE, 0xA7, 0x45, 0xFF, 0xD6, 0x92, 0x1B, 0xFF, 0xD5, 0x92, 0x1C, 0xFF, 0xD5, 0x90, 0x1C, 0xFF,
+	0xD4, 0x8E, 0x1A, 0xFF, 0xD2, 0x8C, 0x19, 0xFF, 0xB0, 0x73, 0x13, 0xFF, 0x82, 0x53, 0x0C, 0x8D,
+	0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x3C, 0x28, 0x07, 0x48,
+	0xB3, 0x75, 0x13, 0xFF, 0xD0, 0x8B, 0x19, 0xFF, 0xD5, 0x90, 0x1B, 0xFF, 0xD5, 0x91, 0x1C, 0xFF,
+	0xD6, 0x93, 0x1D, 0xFF, 0xD7, 0x95, 0x1F, 0xFF, 0xD8, 0x96, 0x1F, 0xFF, 0xDF, 0xA8, 0x44, 0xFF,
+	0xE1, 0xAE, 0x4C, 0xFF, 0xE1, 0xAE, 0x4C, 0xFF, 0xE2, 0xAF, 0x4D, 0xFF, 0xE3, 0xB0, 0x4E, 0xFF,
+	0xE3, 0xB1, 0x4F, 0xFF, 0xE4, 0xB2, 0x50, 0xFF, 0xE4, 0xB3, 0x50, 0xFF, 0xE4, 0xB3, 0x50, 0xFF,
+	0xE4, 0xB3, 0x50, 0xFF, 0xE5, 0xB4, 0x51, 0xFF, 0xE5, 0xB5, 0x52, 0xFF, 0xE5, 0xB5, 0x52, 0xFF,
+	0xE6, 0xB6, 0x52, 0xFF, 0xE6, 0xB6, 0x52, 0xFF, 0xE6, 0xB6, 0x52, 0xFF, 0xE6, 0xB6, 0x52, 0xFF,
+	0xE6, 0xB6, 0x52, 0xFF, 0xE6, 0xB6, 0x52, 0xFF, 0xE6, 0xB6, 0x52, 0xFF, 0xE5, 0xB5, 0x52, 0xFF,
+	0xE5, 0xB5, 0x52, 0xFF, 0xE5, 0xB5, 0x51, 0xFF, 0xE5, 0xB4, 0x51, 0xFF, 0xE4, 0xB3, 0x50, 0xFF,
+	0xE4, 0xB3, 0x50, 0xFF, 0xE4, 0xB3, 0x50, 0xFF, 0xE4, 0xB1, 0x50, 0xFF, 0xE3, 0xB1, 0x4F, 0xFF,
+	0xE2, 0xAF, 0x4E, 0xFF, 0xE2, 0xAF, 0x4D, 0xFF, 0xE1, 0xAE, 0x4C, 0xFF, 0xE0, 0xAD, 0x4C, 0xFF,
+	0xDA, 0x9D, 0x2B, 0xFF, 0xD8, 0x96, 0x1F, 0xFF, 0xD7, 0x94, 0x1E, 0xFF, 0xD6, 0x92, 0x1D, 0xFF,
+	0xD5, 0x91, 0x1C, 0xFF, 0xD5, 0x8F, 0x1B, 0xFF, 0xBC, 0x7D, 0x15, 0xFF, 0x9F, 0x68, 0x11, 0xD0,
+	0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x68, 0x45, 0x0B, 0x71,
+	0xB5, 0x77, 0x14, 0xFF, 0xD3, 0x8F, 0x1B, 0xFF, 0xD6, 0x92, 0x1D, 0xFF, 0xD7, 0x94, 0x1E, 0xFF,
+	0xD8, 0x96, 0x20, 0xFF, 0xD9, 0x97, 0x20, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xDB, 0x9C, 0x27, 0xFF,
+	0xE1, 0xAB, 0x45, 0xFF, 0xE1, 0xAC, 0x45, 0xFF, 0xE2, 0xAD, 0x46, 0xFF, 0xE3, 0xAD, 0x46, 0xFF,
+	0xE3, 0xAF, 0x46, 0xFF, 0xE4, 0xAF, 0x47, 0xFF, 0xE4, 0xB1, 0x48, 0xFF, 0xE4, 0xB2, 0x48, 0xFF,
+	0xE4, 0xB2, 0x49, 0xFF, 0xE5, 0xB3, 0x49, 0xFF, 0xE5, 0xB3, 0x4A, 0xFF, 0xE5, 0xB3, 0x4A, 0xFF,
+	0xE5, 0xB3, 0x4A, 0xFF, 0xE6, 0xB3, 0x4B, 0xFF, 0xE6, 0xB4, 0x4B, 0xFF, 0xE6, 0xB4, 0x4B, 0xFF,
+	0xE6, 0xB4, 0x4B, 0xFF, 0xE6, 0xB4, 0x4B, 0xFF, 0xE6, 0xB3, 0x4B, 0xFF, 0xE5, 0xB3, 0x4A, 0xFF,
+	0xE5, 0xB3, 0x4A, 0xFF, 0xE5, 0xB3, 0x4A, 0xFF, 0xE5, 0xB3, 0x49, 0xFF, 0xE4, 0xB2, 0x49, 0xFF,
+	0xE4, 0xB1, 0x48, 0xFF, 0xE4, 0xB0, 0x48, 0xFF, 0xE3, 0xAF, 0x47, 0xFF, 0xE3, 0xAE, 0x46, 0xFF,
+	0xE2, 0xAD, 0x46, 0xFF, 0xE2, 0xAD, 0x45, 0xFF, 0xE1, 0xAB, 0x44, 0xFF, 0xE0, 0xAA, 0x42, 0xFF,
+	0xDA, 0x9B, 0x24, 0xFF, 0xD9, 0x98, 0x21, 0xFF, 0xD9, 0x97, 0x20, 0xFF, 0xD8, 0x95, 0x1F, 0xFF,
+	0xD6, 0x93, 0x1D, 0xFF, 0xD6, 0x92, 0x1D, 0xFF, 0xCF, 0x8B, 0x1A, 0xFF, 0xAD, 0x72, 0x12, 0xFB,
+	0x00, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x7C, 0x52, 0x0D, 0x8D,
+	0xB7, 0x7A, 0x15, 0xFF, 0xD7, 0x93, 0x1D, 0xFF, 0xD7, 0x95, 0x1F, 0xFF, 0xD8, 0x97, 0x20, 0xFF,
+	0xDA, 0x98, 0x21, 0xFF, 0xDA, 0x9A, 0x22, 0xFF, 0xDB, 0x9B, 0x24, 0xFF, 0xDB, 0x9D, 0x24, 0xFF,
+	0xE0, 0xA7, 0x39, 0xFF, 0xE1, 0xAB, 0x3F, 0xFF, 0xE2, 0xAB, 0x3F, 0xFF, 0xE3, 0xAD, 0x40, 0xFF,
+	0xE3, 0xAF, 0x41, 0xFF, 0xE4, 0xAF, 0x41, 0xFF, 0xE4, 0xB0, 0x42, 0xFF, 0xE5, 0xB0, 0x43, 0xFF,
+	0xE5, 0xB1, 0x43, 0xFF, 0xE5, 0xB2, 0x44, 0xFF, 0xE5, 0xB2, 0x44, 0xFF, 0xE5, 0xB3, 0x44, 0xFF,
+	0xE6, 0xB3, 0x45, 0xFF, 0xE7, 0xB3, 0x45, 0xFF, 0xE7, 0xB4, 0x45, 0xFF, 0xE7, 0xB5, 0x45, 0xFF,
+	0xE7, 0xB4, 0x45, 0xFF, 0xE7, 0xB3, 0x45, 0xFF, 0xE7, 0xB3, 0x45, 0xFF, 0xE6, 0xB4, 0x45, 0xFF,
+	0xE5, 0xB2, 0x44, 0xFF, 0xE5, 0xB2, 0x44, 0xFF, 0xE5, 0xB1, 0x43, 0xFF, 0xE5, 0xB1, 0x43, 0xFF,
+	0xE5, 0xB0, 0x43, 0xFF, 0xE4, 0xB0, 0x42, 0xFF, 0xE3, 0xAF, 0x41, 0xFF, 0xE3, 0xAE, 0x41, 0xFF,
+	0xE2, 0xAD, 0x40, 0xFF, 0xE1, 0xAB, 0x3F, 0xFF, 0xE1, 0xAA, 0x3F, 0xFF, 0xDF, 0xA4, 0x32, 0xFF,
+	0xDC, 0x9C, 0x23, 0xFF, 0xDA, 0x9B, 0x23, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xD9, 0x98, 0x21, 0xFF,
+	0xD8, 0x96, 0x1F, 0xFF, 0xD7, 0x94, 0x1E, 0xFF, 0xD7, 0x93, 0x1D, 0xFF, 0xB7, 0x7A, 0x15, 0xFF,
+	0x0A, 0x05, 0x01, 0x45, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x25, 0x91, 0x62, 0x12, 0xB2,
+	0xBD, 0x81, 0x19, 0xFF, 0xD8, 0x96, 0x1F, 0xFF, 0xD9, 0x97, 0x20, 0xFF, 0xD9, 0x9A, 0x21, 0xFF,
+	0xDA, 0x9A, 0x23, 0xFF, 0xDC, 0x9D, 0x24, 0xFF, 0xDC, 0x9F, 0x25, 0xFF, 0xDD, 0xA0, 0x26, 0xFF,
+	0xDE, 0xA2, 0x2A, 0xFF, 0xE2, 0xAC, 0x3D, 0xFF, 0xE3, 0xAD, 0x3D, 0xFF, 0xE3, 0xAD, 0x3D, 0xFF,
+	0xE4, 0xAF, 0x3F, 0xFF, 0xE5, 0xAF, 0x40, 0xFF, 0xE5, 0xB1, 0x40, 0xFF, 0xE6, 0xB2, 0x41, 0xFF,
+	0xE6, 0xB2, 0x42, 0xFF, 0xE7, 0xB3, 0x41, 0xFF, 0xE7, 0xB4, 0x43, 0xFF, 0xE7, 0xB4, 0x43, 0xFF,
+	0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF,
+	0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB4, 0x43, 0xFF,
+	0xE7, 0xB4, 0x43, 0xFF, 0xE7, 0xB4, 0x43, 0xFF, 0xE6, 0xB3, 0x42, 0xFF, 0xE6, 0xB2, 0x41, 0xFF,
+	0xE6, 0xB1, 0x41, 0xFF, 0xE5, 0xB0, 0x40, 0xFF, 0xE4, 0xAF, 0x3F, 0xFF, 0xE4, 0xAE, 0x3E, 0xFF,
+	0xE3, 0xAD, 0x3D, 0xFF, 0xE3, 0xAC, 0x3D, 0xFF, 0xE1, 0xA9, 0x38, 0xFF, 0xDE, 0xA0, 0x27, 0xFF,
+	0xDD, 0xA0, 0x26, 0xFF, 0xDC, 0x9E, 0x25, 0xFF, 0xDB, 0x9C, 0x23, 0xFF, 0xDA, 0x9A, 0x22, 0xFF,
+	0xD9, 0x98, 0x21, 0xFF, 0xD8, 0x96, 0x20, 0xFF, 0xD8, 0x95, 0x1F, 0xFF, 0xBB, 0x7F, 0x17, 0xFF,
+	0x5F, 0x3F, 0x0B, 0x74, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x2B, 0x9A, 0x69, 0x13, 0xC5,
+	0xC5, 0x86, 0x1A, 0xFF, 0xD9, 0x98, 0x21, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xDB, 0x9B, 0x23, 0xFF,
+	0xDC, 0x9E, 0x25, 0xFF, 0xDD, 0x9F, 0x25, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDF, 0xA3, 0x28, 0xFF,
+	0xE0, 0xA4, 0x29, 0xFF, 0xE2, 0xA9, 0x30, 0xFF, 0xE3, 0xAE, 0x3B, 0xFF, 0xE4, 0xAF, 0x3D, 0xFF,
+	0xE5, 0xAF, 0x3D, 0xFF, 0xE5, 0xB1, 0x3E, 0xFF, 0xE6, 0xB2, 0x3E, 0xFF, 0xE6, 0xB3, 0x3E, 0xFF,
+	0xE7, 0xB4, 0x3F, 0xFF, 0xE8, 0xB5, 0x40, 0xFF, 0xE8, 0xB5, 0x40, 0xFF, 0xE8, 0xB6, 0x40, 0xFF,
+	0xE9, 0xB6, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF,
+	0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB6, 0x41, 0xFF, 0xE8, 0xB6, 0x41, 0xFF,
+	0xE8, 0xB5, 0x40, 0xFF, 0xE8, 0xB5, 0x40, 0xFF, 0xE7, 0xB4, 0x3F, 0xFF, 0xE7, 0xB3, 0x3F, 0xFF,
+	0xE6, 0xB3, 0x3E, 0xFF, 0xE6, 0xB1, 0x3E, 0xFF, 0xE5, 0xB0, 0x3D, 0xFF, 0xE5, 0xAF, 0x3D, 0xFF,
+	0xE4, 0xAE, 0x3C, 0xFF, 0xE3, 0xAD, 0x3B, 0xFF, 0xE1, 0xA7, 0x2C, 0xFF, 0xE0, 0xA4, 0x29, 0xFF,
+	0xDE, 0xA2, 0x28, 0xFF, 0xDE, 0xA0, 0x26, 0xFF, 0xDD, 0x9F, 0x25, 0xFF, 0xDB, 0x9C, 0x24, 0xFF,
+	0xDA, 0x9A, 0x22, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xD9, 0x98, 0x20, 0xFF, 0xC0, 0x82, 0x18, 0xFF,
+	0x76, 0x50, 0x0E, 0x8D, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x31, 0x9D, 0x6B, 0x15, 0xCA,
+	0xC7, 0x8A, 0x1C, 0xFF, 0xDB, 0x9A, 0x23, 0xFF, 0xDB, 0x9C, 0x23, 0xFF, 0xDD, 0x9E, 0x25, 0xFF,
+	0xDE, 0x9F, 0x27, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xE0, 0xA4, 0x29, 0xFF, 0xE1, 0xA5, 0x2A, 0xFF,
+	0xE1, 0xA6, 0x2B, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF, 0xE3, 0xAC, 0x34, 0xFF, 0xE6, 0xB1, 0x3C, 0xFF,
+	0xE6, 0xB2, 0x3D, 0xFF, 0xE7, 0xB3, 0x3D, 0xFF, 0xE8, 0xB4, 0x3E, 0xFF, 0xE8, 0xB5, 0x40, 0xFF,
+	0xE9, 0xB6, 0x40, 0xFF, 0xE9, 0xB7, 0x40, 0xFF, 0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF,
+	0xE9, 0xB8, 0x41, 0xFF, 0xEA, 0xB8, 0x42, 0xFF, 0xEA, 0xB9, 0x42, 0xFF, 0xEA, 0xB9, 0x42, 0xFF,
+	0xEA, 0xB9, 0x42, 0xFF, 0xEA, 0xB8, 0x42, 0xFF, 0xEA, 0xB8, 0x42, 0xFF, 0xE9, 0xB8, 0x41, 0xFF,
+	0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x40, 0xFF, 0xE9, 0xB7, 0x40, 0xFF, 0xE9, 0xB6, 0x40, 0xFF,
+	0xE8, 0xB4, 0x3F, 0xFF, 0xE8, 0xB4, 0x3F, 0xFF, 0xE7, 0xB2, 0x3D, 0xFF, 0xE6, 0xB1, 0x3C, 0xFF,
+	0xE6, 0xB0, 0x3B, 0xFF, 0xE3, 0xAA, 0x2F, 0xFF, 0xE2, 0xA7, 0x2B, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF,
+	0xE0, 0xA5, 0x2A, 0xFF, 0xDF, 0xA3, 0x28, 0xFF, 0xDE, 0xA0, 0x27, 0xFF, 0xDD, 0x9F, 0x26, 0xFF,
+	0xDC, 0x9D, 0x24, 0xFF, 0xDB, 0x9B, 0x23, 0xFF, 0xDA, 0x9A, 0x22, 0xFF, 0xC2, 0x85, 0x1A, 0xFF,
+	0x79, 0x52, 0x10, 0x95, 0x00, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x34, 0x9F, 0x6D, 0x14, 0xCF,
+	0xCA, 0x8D, 0x1E, 0xFF, 0xDB, 0x9C, 0x24, 0xFF, 0xDD, 0x9E, 0x25, 0xFF, 0xDD, 0xA1, 0x26, 0xFF,
+	0xDE, 0xA2, 0x28, 0xFF, 0xE0, 0xA4, 0x29, 0xFF, 0xE0, 0xA6, 0x2B, 0xFF, 0xE1, 0xA8, 0x2C, 0xFF,
+	0xE2, 0xA9, 0x2D, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE6, 0xAF, 0x35, 0xFF,
+	0xE7, 0xB3, 0x3B, 0xFF, 0xE7, 0xB4, 0x3C, 0xFF, 0xE8, 0xB5, 0x3D, 0xFF, 0xE9, 0xB7, 0x3E, 0xFF,
+	0xE9, 0xB7, 0x3F, 0xFF, 0xE9, 0xB8, 0x3F, 0xFF, 0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB9, 0x40, 0xFF,
+	0xEA, 0xB9, 0x40, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF,
+	0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEA, 0xB9, 0x40, 0xFF,
+	0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB8, 0x40, 0xFF, 0xE9, 0xB8, 0x3F, 0xFF, 0xE9, 0xB7, 0x3F, 0xFF,
+	0xE8, 0xB6, 0x3E, 0xFF, 0xE8, 0xB5, 0x3D, 0xFF, 0xE7, 0xB4, 0x3C, 0xFF, 0xE6, 0xB2, 0x3A, 0xFF,
+	0xE5, 0xAE, 0x30, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE2, 0xA9, 0x2C, 0xFF,
+	0xE1, 0xA7, 0x2B, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF, 0xDF, 0xA3, 0x29, 0xFF, 0xDE, 0xA2, 0x27, 0xFF,
+	0xDD, 0x9F, 0x26, 0xFF, 0xDC, 0x9D, 0x25, 0xFF, 0xDC, 0x9C, 0x24, 0xFF, 0xC3, 0x87, 0x1B, 0xFF,
+	0x77, 0x51, 0x10, 0x98, 0x00, 0x00, 0x00, 0x2A, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x37, 0x9F, 0x6E, 0x16, 0xCC,
+	0xC9, 0x8E, 0x1F, 0xFF, 0xDD, 0x9F, 0x25, 0xFF, 0xDD, 0xA0, 0x26, 0xFF, 0xDF, 0xA2, 0x28, 0xFF,
+	0xE0, 0xA5, 0x2A, 0xFF, 0xE1, 0xA7, 0x2B, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF,
+	0xE4, 0xAC, 0x2F, 0xFF, 0xE5, 0xAD, 0x30, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE7, 0xB1, 0x32, 0xFF,
+	0xE7, 0xB2, 0x34, 0xFF, 0xE9, 0xB5, 0x3A, 0xFF, 0xEA, 0xB7, 0x3D, 0xFF, 0xEA, 0xB9, 0x3D, 0xFF,
+	0xEB, 0xB9, 0x3E, 0xFF, 0xEB, 0xBA, 0x3F, 0xFF, 0xEC, 0xBB, 0x3F, 0xFF, 0xEC, 0xBC, 0x40, 0xFF,
+	0xEC, 0xBC, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF,
+	0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF,
+	0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBB, 0x3F, 0xFF, 0xEB, 0xBA, 0x3E, 0xFF, 0xEB, 0xB9, 0x3E, 0xFF,
+	0xEA, 0xB8, 0x3D, 0xFF, 0xE9, 0xB7, 0x3C, 0xFF, 0xE8, 0xB4, 0x37, 0xFF, 0xE7, 0xB2, 0x33, 0xFF,
+	0xE6, 0xB0, 0x32, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE5, 0xAD, 0x30, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF,
+	0xE2, 0xA9, 0x2D, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xDF, 0xA3, 0x29, 0xFF,
+	0xDF, 0xA1, 0x27, 0xFF, 0xDD, 0xA0, 0x26, 0xFF, 0xDD, 0x9E, 0x25, 0xFF, 0xC5, 0x88, 0x1D, 0xFF,
+	0x78, 0x54, 0x12, 0x98, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x38, 0x94, 0x67, 0x16, 0xBC,
+	0xC7, 0x8D, 0x1F, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDF, 0xA2, 0x28, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF,
+	0xE2, 0xA6, 0x2C, 0xFF, 0xE2, 0xA9, 0x2C, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE5, 0xAD, 0x2F, 0xFF,
+	0xE5, 0xAE, 0x30, 0xFF, 0xE6, 0xB0, 0x32, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE8, 0xB3, 0x34, 0xFF,
+	0xE9, 0xB5, 0x35, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xEB, 0xB8, 0x38, 0xFF, 0xEB, 0xBA, 0x3C, 0xFF,
+	0xED, 0xBC, 0x3D, 0xFF, 0xED, 0xBC, 0x3E, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBD, 0x3F, 0xFF,
+	0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x41, 0xFF, 0xED, 0xBF, 0x41, 0xFF,
+	0xED, 0xBF, 0x41, 0xFF, 0xED, 0xBE, 0x41, 0xFF, 0xED, 0xBF, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xED, 0xBD, 0x3F, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBC, 0x3E, 0xFF, 0xEC, 0xBB, 0x3D, 0xFF,
+	0xEB, 0xB9, 0x3B, 0xFF, 0xEA, 0xB7, 0x37, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB4, 0x34, 0xFF,
+	0xE8, 0xB3, 0x34, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE5, 0xAE, 0x30, 0xFF,
+	0xE4, 0xAC, 0x2F, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF,
+	0xE0, 0xA4, 0x29, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDE, 0xA1, 0x26, 0xFF, 0xC6, 0x8A, 0x1D, 0xFF,
+	0x5E, 0x41, 0x0E, 0x85, 0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x38, 0x7C, 0x57, 0x12, 0xA2,
+	0xC4, 0x8A, 0x1E, 0xFF, 0xE0, 0xA3, 0x28, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF,
+	0xE2, 0xA9, 0x2D, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE5, 0xAD, 0x30, 0xFF, 0xE5, 0xAF, 0x31, 0xFF,
+	0xE7, 0xB1, 0x32, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE8, 0xB4, 0x34, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xEA, 0xB7, 0x37, 0xFF, 0xEB, 0xB9, 0x37, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xEC, 0xBB, 0x39, 0xFF,
+	0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBD, 0x3F, 0xFF, 0xED, 0xBE, 0x41, 0xFF, 0xED, 0xC0, 0x43, 0xFF,
+	0xED, 0xBF, 0x44, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x46, 0xFF,
+	0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xBF, 0x45, 0xFF, 0xED, 0xBF, 0x43, 0xFF,
+	0xED, 0xBF, 0x42, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBC, 0x3A, 0xFF,
+	0xEC, 0xBB, 0x39, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEA, 0xB6, 0x36, 0xFF,
+	0xE9, 0xB5, 0x35, 0xFF, 0xE8, 0xB4, 0x34, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE6, 0xB0, 0x31, 0xFF,
+	0xE5, 0xAE, 0x31, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE2, 0xA8, 0x2D, 0xFF,
+	0xE1, 0xA6, 0x2B, 0xFF, 0xE0, 0xA4, 0x29, 0xFF, 0xE0, 0xA3, 0x28, 0xFF, 0xC6, 0x8B, 0x1E, 0xFF,
+	0x1B, 0x12, 0x03, 0x64, 0x00, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x35, 0x61, 0x45, 0x0E, 0x8C,
+	0xC7, 0x8C, 0x20, 0xFF, 0xDF, 0xA4, 0x29, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF,
+	0xE4, 0xAB, 0x2E, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE7, 0xB1, 0x33, 0xFF,
+	0xE8, 0xB3, 0x34, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xEB, 0xB9, 0x38, 0xFF,
+	0xEC, 0xBA, 0x38, 0xFF, 0xED, 0xBB, 0x39, 0xFF, 0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBE, 0x3F, 0xFF,
+	0xEE, 0xBE, 0x41, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x46, 0xFF,
+	0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC1, 0x4A, 0xFF, 0xEE, 0xC1, 0x4A, 0xFF, 0xEE, 0xC1, 0x4A, 0xFF,
+	0xEE, 0xC1, 0x4A, 0xFF, 0xEE, 0xC1, 0x4A, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC0, 0x48, 0xFF,
+	0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xBF, 0x44, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xBE, 0x40, 0xFF,
+	0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBC, 0x3A, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xEC, 0xBA, 0x38, 0xFF,
+	0xEB, 0xB8, 0x37, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE8, 0xB3, 0x33, 0xFF,
+	0xE7, 0xB0, 0x32, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE4, 0xAD, 0x2F, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF,
+	0xE2, 0xA8, 0x2D, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xDD, 0xA1, 0x28, 0xFF, 0xBE, 0x86, 0x1D, 0xFF,
+	0x00, 0x00, 0x00, 0x4C, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x2E, 0x38, 0x28, 0x09, 0x72,
+	0xC8, 0x8E, 0x20, 0xFF, 0xDE, 0xA4, 0x2A, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF,
+	0xE5, 0xAE, 0x30, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE9, 0xB4, 0x35, 0xFF,
+	0xE9, 0xB5, 0x35, 0xFF, 0xEA, 0xB7, 0x37, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xED, 0xBA, 0x39, 0xFF,
+	0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBE, 0x3E, 0xFF, 0xEE, 0xBF, 0x41, 0xFF, 0xEE, 0xC0, 0x45, 0xFF,
+	0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC3, 0x4D, 0xFF,
+	0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC4, 0x50, 0xFF,
+	0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC4, 0x4F, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF,
+	0xEF, 0xC2, 0x4D, 0xFF, 0xEF, 0xC2, 0x4B, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC0, 0x46, 0xFF,
+	0xEE, 0xBF, 0x44, 0xFF, 0xEE, 0xBE, 0x40, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBB, 0x3A, 0xFF,
+	0xEC, 0xBB, 0x39, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xE8, 0xB3, 0x34, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE4, 0xAD, 0x2F, 0xFF,
+	0xE3, 0xAA, 0x2D, 0xFF, 0xE2, 0xA8, 0x2D, 0xFF, 0xD1, 0x98, 0x24, 0xFF, 0xAE, 0x7B, 0x1C, 0xE3,
+	0x00, 0x00, 0x00, 0x4A, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x51,
+	0xC4, 0x8C, 0x20, 0xFE, 0xD9, 0x9F, 0x28, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE5, 0xAE, 0x30, 0xFF,
+	0xE6, 0xAF, 0x31, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB6, 0x35, 0xFF,
+	0xEB, 0xB8, 0x37, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xED, 0xBB, 0x3A, 0xFF, 0xED, 0xBD, 0x3D, 0xFF,
+	0xEE, 0xBE, 0x41, 0xFF, 0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC2, 0x4B, 0xFF,
+	0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC4, 0x54, 0xFF,
+	0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC6, 0x56, 0xFF, 0xEF, 0xC6, 0x57, 0xFF, 0xEF, 0xC6, 0x57, 0xFF,
+	0xEF, 0xC6, 0x57, 0xFF, 0xEF, 0xC6, 0x57, 0xFF, 0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC5, 0x55, 0xFF,
+	0xEF, 0xC4, 0x53, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF,
+	0xEE, 0xC1, 0x4A, 0xFF, 0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xED, 0xBC, 0x3C, 0xFF, 0xED, 0xBB, 0x39, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB7, 0x36, 0xFF,
+	0xE9, 0xB5, 0x35, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE6, 0xAF, 0x31, 0xFF,
+	0xE4, 0xAC, 0x2F, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xC9, 0x91, 0x22, 0xFF, 0x84, 0x5F, 0x16, 0xB2,
+	0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x48,
+	0x92, 0x69, 0x18, 0xC6, 0xCE, 0x95, 0x24, 0xFF, 0xE6, 0xAE, 0x30, 0xFF, 0xE6, 0xAF, 0x31, 0xFF,
+	0xE7, 0xB2, 0x33, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB6, 0x35, 0xFF, 0xEB, 0xB8, 0x37, 0xFF,
+	0xEC, 0xBA, 0x39, 0xFF, 0xED, 0xBD, 0x3B, 0xFF, 0xED, 0xBE, 0x3F, 0xFF, 0xEE, 0xBF, 0x43, 0xFF,
+	0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xC1, 0x4A, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC4, 0x51, 0xFF,
+	0xEF, 0xC4, 0x54, 0xFF, 0xF0, 0xC5, 0x56, 0xFF, 0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF,
+	0xF0, 0xC7, 0x5C, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF,
+	0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF,
+	0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC6, 0x57, 0xFF, 0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC4, 0x53, 0xFF,
+	0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC2, 0x4D, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC0, 0x46, 0xFF,
+	0xEE, 0xBE, 0x41, 0xFF, 0xED, 0xBE, 0x3D, 0xFF, 0xED, 0xBC, 0x3A, 0xFF, 0xEB, 0xB9, 0x38, 0xFF,
+	0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB5, 0x36, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE7, 0xB1, 0x32, 0xFF,
+	0xE6, 0xAE, 0x31, 0xFF, 0xE1, 0xA9, 0x2E, 0xFF, 0xCB, 0x93, 0x23, 0xFF, 0x55, 0x3B, 0x0E, 0x8C,
+	0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x3F,
+	0x24, 0x1A, 0x06, 0x7A, 0xCA, 0x92, 0x23, 0xFF, 0xE3, 0xAC, 0x2F, 0xFF, 0xE7, 0xB1, 0x33, 0xFF,
+	0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB6, 0x35, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEC, 0xBA, 0x39, 0xFF,
+	0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBE, 0x3F, 0xFF, 0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xC1, 0x48, 0xFF,
+	0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC5, 0x53, 0xFF, 0xF0, 0xC6, 0x57, 0xFF,
+	0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC9, 0x5F, 0xFF, 0xF1, 0xC9, 0x61, 0xFF,
+	0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xCB, 0x64, 0xFF,
+	0xF1, 0xCB, 0x64, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xCA, 0x62, 0xFF,
+	0xF1, 0xC9, 0x60, 0xFF, 0xF0, 0xC9, 0x5E, 0xFF, 0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC7, 0x59, 0xFF,
+	0xF0, 0xC6, 0x56, 0xFF, 0xEF, 0xC4, 0x53, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC2, 0x4B, 0xFF,
+	0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBC, 0x3A, 0xFF,
+	0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE8, 0xB3, 0x33, 0xFF,
+	0xE7, 0xB1, 0x32, 0xFF, 0xDD, 0xA6, 0x2C, 0xFF, 0xC8, 0x90, 0x23, 0xFF, 0x00, 0x00, 0x00, 0x5F,
+	0x00, 0x00, 0x00, 0x2F, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x30,
+	0x08, 0x06, 0x01, 0x63, 0xC1, 0x8D, 0x23, 0xF3, 0xDB, 0xA4, 0x2C, 0xFF, 0xE8, 0xB3, 0x34, 0xFF,
+	0xE9, 0xB5, 0x35, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xED, 0xBD, 0x3B, 0xFF,
+	0xED, 0xBE, 0x3F, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC2, 0x49, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF,
+	0xEF, 0xC4, 0x52, 0xFF, 0xF0, 0xC6, 0x55, 0xFF, 0xF0, 0xC6, 0x59, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF,
+	0xF1, 0xC9, 0x60, 0xFF, 0xF1, 0xC9, 0x62, 0xFF, 0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCC, 0x67, 0xFF,
+	0xF2, 0xCC, 0x69, 0xFF, 0xF2, 0xCD, 0x6A, 0xFF, 0xF2, 0xCC, 0x6B, 0xFF, 0xF2, 0xCC, 0x6C, 0xFF,
+	0xF2, 0xCC, 0x6B, 0xFF, 0xF2, 0xCD, 0x6B, 0xFF, 0xF2, 0xCD, 0x69, 0xFF, 0xF1, 0xCC, 0x69, 0xFF,
+	0xF1, 0xCB, 0x67, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xF0, 0xC8, 0x5F, 0xFF,
+	0xF0, 0xC7, 0x5C, 0xFF, 0xF0, 0xC6, 0x58, 0xFF, 0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC3, 0x50, 0xFF,
+	0xEF, 0xC3, 0x4C, 0xFF, 0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xED, 0xBD, 0x3E, 0xFF,
+	0xED, 0xBB, 0x3A, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xE8, 0xB3, 0x33, 0xFF, 0xD2, 0x99, 0x27, 0xFF, 0x7E, 0x5D, 0x17, 0xB9, 0x00, 0x00, 0x00, 0x4E,
+	0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x20,
+	0x00, 0x00, 0x00, 0x50, 0x6E, 0x4F, 0x13, 0xAD, 0xD3, 0x9A, 0x27, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xEA, 0xB7, 0x37, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC2, 0x4A, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC4, 0x53, 0xFF,
+	0xF0, 0xC6, 0x58, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC9, 0x5F, 0xFF, 0xF1, 0xCA, 0x63, 0xFF,
+	0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCC, 0x69, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF,
+	0xF2, 0xCE, 0x70, 0xFF, 0xF2, 0xCE, 0x71, 0xFF, 0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xCF, 0x73, 0xFF,
+	0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xCE, 0x71, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF,
+	0xF2, 0xCD, 0x6D, 0xFF, 0xF1, 0xCD, 0x6B, 0xFF, 0xF1, 0xCB, 0x68, 0xFF, 0xF1, 0xCB, 0x65, 0xFF,
+	0xF1, 0xC9, 0x61, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC5, 0x56, 0xFF,
+	0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC3, 0x4C, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xBF, 0x42, 0xFF,
+	0xED, 0xBE, 0x3D, 0xFF, 0xED, 0xBB, 0x3A, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB6, 0x36, 0xFF,
+	0xDF, 0xA9, 0x2F, 0xFF, 0xC8, 0x92, 0x25, 0xFA, 0x0C, 0x09, 0x02, 0x73, 0x01, 0x00, 0x00, 0x40,
+	0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12,
+	0x00, 0x00, 0x00, 0x3A, 0x00, 0x00, 0x00, 0x68, 0xB2, 0x83, 0x22, 0xE8, 0xDA, 0xA3, 0x2C, 0xFF,
+	0xEC, 0xBA, 0x38, 0xFF, 0xED, 0xBB, 0x3A, 0xFF, 0xED, 0xBD, 0x3F, 0xFF, 0xEE, 0xBF, 0x44, 0xFF,
+	0xEE, 0xC2, 0x49, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC5, 0x53, 0xFF, 0xF0, 0xC7, 0x58, 0xFF,
+	0xF0, 0xC7, 0x5C, 0xFF, 0xF1, 0xC9, 0x61, 0xFF, 0xF1, 0xCB, 0x64, 0xFF, 0xF1, 0xCC, 0x69, 0xFF,
+	0xF2, 0xCD, 0x6C, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xD0, 0x74, 0xFF,
+	0xF3, 0xD0, 0x76, 0xFF, 0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD2, 0x79, 0xFF,
+	0xF3, 0xD2, 0x79, 0xFF, 0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD1, 0x78, 0xFF, 0xF2, 0xD0, 0x75, 0xFF,
+	0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF, 0xF1, 0xCD, 0x6B, 0xFF,
+	0xF1, 0xCC, 0x67, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF0, 0xC8, 0x5F, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF,
+	0xF0, 0xC6, 0x57, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC3, 0x4C, 0xFF, 0xEE, 0xC1, 0x48, 0xFF,
+	0xEE, 0xBE, 0x42, 0xFF, 0xED, 0xBD, 0x3C, 0xFF, 0xEC, 0xBB, 0x39, 0xFF, 0xEC, 0xBA, 0x38, 0xFF,
+	0xD8, 0xA0, 0x2A, 0xFF, 0x89, 0x64, 0x18, 0xC4, 0x00, 0x00, 0x00, 0x5B, 0x00, 0x00, 0x00, 0x2B,
+	0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x54, 0x4F, 0x39, 0x0E, 0x9F, 0xD9, 0xA1, 0x2A, 0xFF,
+	0xEC, 0xB9, 0x38, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xC1, 0x48, 0xFF,
+	0xEF, 0xC2, 0x4E, 0xFF, 0xEF, 0xC4, 0x53, 0xFF, 0xF0, 0xC6, 0x58, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF,
+	0xF1, 0xC9, 0x61, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCC, 0x6A, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF,
+	0xF2, 0xCF, 0x72, 0xFF, 0xF3, 0xD1, 0x76, 0xFF, 0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF,
+	0xF3, 0xD3, 0x7D, 0xFF, 0xF3, 0xD4, 0x7E, 0xFF, 0xF3, 0xD4, 0x7F, 0xFF, 0xF4, 0xD4, 0x80, 0xFF,
+	0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD4, 0x7F, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF, 0xF3, 0xD3, 0x7C, 0xFF,
+	0xF3, 0xD2, 0x7A, 0xFF, 0xF3, 0xD0, 0x77, 0xFF, 0xF2, 0xD0, 0x74, 0xFF, 0xF2, 0xCE, 0x70, 0xFF,
+	0xF2, 0xCD, 0x6D, 0xFF, 0xF1, 0xCC, 0x69, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF0, 0xC9, 0x60, 0xFF,
+	0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC5, 0x56, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC1, 0x4B, 0xFF,
+	0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xBE, 0x40, 0xFF, 0xED, 0xBD, 0x3B, 0xFF, 0xE0, 0xAB, 0x31, 0xFF,
+	0xC3, 0x90, 0x25, 0xF5, 0x00, 0x00, 0x00, 0x72, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x19,
+	0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x00, 0x00, 0x66, 0xAC, 0x7F, 0x20, 0xE2,
+	0xDC, 0xA7, 0x2E, 0xFF, 0xEE, 0xBE, 0x40, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF,
+	0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC6, 0x57, 0xFF, 0xF0, 0xC7, 0x5C, 0xFF, 0xF1, 0xC9, 0x61, 0xFF,
+	0xF1, 0xCB, 0x67, 0xFF, 0xF1, 0xCC, 0x6B, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xD0, 0x74, 0xFF,
+	0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD3, 0x7F, 0xFF, 0xF3, 0xD4, 0x81, 0xFF,
+	0xF4, 0xD5, 0x84, 0xFF, 0xF4, 0xD5, 0x85, 0xFF, 0xF4, 0xD6, 0x87, 0xFF, 0xF4, 0xD6, 0x87, 0xFF,
+	0xF4, 0xD6, 0x87, 0xFF, 0xF4, 0xD5, 0x86, 0xFF, 0xF4, 0xD5, 0x84, 0xFF, 0xF3, 0xD4, 0x83, 0xFF,
+	0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF, 0xF3, 0xD2, 0x7A, 0xFF, 0xF3, 0xD0, 0x76, 0xFF,
+	0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF, 0xF1, 0xCC, 0x6A, 0xFF, 0xF1, 0xCA, 0x64, 0xFF,
+	0xF0, 0xC8, 0x5F, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF, 0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF,
+	0xEE, 0xC2, 0x4A, 0xFF, 0xEE, 0xBF, 0x44, 0xFF, 0xEB, 0xBB, 0x3D, 0xFF, 0xDA, 0xA2, 0x2C, 0xFF,
+	0x6E, 0x51, 0x13, 0xB1, 0x00, 0x00, 0x00, 0x5B, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x0A,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x4E, 0x11, 0x0D, 0x04, 0x83,
+	0xD1, 0x9C, 0x2A, 0xFA, 0xE1, 0xAF, 0x37, 0xFF, 0xEF, 0xC2, 0x4A, 0xFF, 0xEF, 0xC4, 0x50, 0xFF,
+	0xF0, 0xC5, 0x56, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF, 0xF1, 0xC9, 0x61, 0xFF, 0xF1, 0xCB, 0x66, 0xFF,
+	0xF1, 0xCC, 0x6B, 0xFF, 0xF2, 0xCE, 0x70, 0xFF, 0xF2, 0xD0, 0x74, 0xFF, 0xF3, 0xD1, 0x79, 0xFF,
+	0xF3, 0xD3, 0x7D, 0xFF, 0xF4, 0xD4, 0x82, 0xFF, 0xF4, 0xD6, 0x85, 0xFF, 0xF4, 0xD6, 0x87, 0xFF,
+	0xF4, 0xD7, 0x8A, 0xFF, 0xF5, 0xD8, 0x8C, 0xFF, 0xF5, 0xD8, 0x8D, 0xFF, 0xF5, 0xD9, 0x8E, 0xFF,
+	0xF5, 0xD8, 0x8D, 0xFF, 0xF5, 0xD8, 0x8D, 0xFF, 0xF4, 0xD8, 0x8B, 0xFF, 0xF4, 0xD7, 0x89, 0xFF,
+	0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD5, 0x84, 0xFF, 0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF,
+	0xF3, 0xD1, 0x77, 0xFF, 0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF, 0xF1, 0xCC, 0x69, 0xFF,
+	0xF1, 0xCA, 0x64, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC7, 0x59, 0xFF, 0xEF, 0xC4, 0x53, 0xFF,
+	0xEF, 0xC2, 0x4E, 0xFF, 0xEE, 0xC1, 0x47, 0xFF, 0xD9, 0xA2, 0x2C, 0xFF, 0xA1, 0x77, 0x20, 0xDD,
+	0x00, 0x00, 0x00, 0x6D, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x5E,
+	0x22, 0x1A, 0x06, 0x99, 0xD3, 0x9E, 0x2B, 0xFE, 0xE6, 0xB5, 0x40, 0xFF, 0xEF, 0xC5, 0x53, 0xFF,
+	0xF0, 0xC7, 0x58, 0xFF, 0xF0, 0xC9, 0x5F, 0xFF, 0xF1, 0xCB, 0x64, 0xFF, 0xF2, 0xCC, 0x69, 0xFF,
+	0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xD0, 0x74, 0xFF, 0xF3, 0xD1, 0x7A, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF,
+	0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD6, 0x87, 0xFF, 0xF4, 0xD7, 0x8A, 0xFF, 0xF5, 0xD9, 0x8D, 0xFF,
+	0xF5, 0xDA, 0x90, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xDA, 0x94, 0xFF, 0xF5, 0xDB, 0x94, 0xFF,
+	0xF5, 0xDB, 0x94, 0xFF, 0xF5, 0xDA, 0x93, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF,
+	0xF5, 0xD8, 0x8C, 0xFF, 0xF4, 0xD7, 0x88, 0xFF, 0xF4, 0xD6, 0x85, 0xFF, 0xF3, 0xD4, 0x81, 0xFF,
+	0xF3, 0xD2, 0x7D, 0xFF, 0xF3, 0xD1, 0x78, 0xFF, 0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF,
+	0xF1, 0xCC, 0x67, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC6, 0x56, 0xFF,
+	0xF0, 0xC6, 0x53, 0xFF, 0xE0, 0xAD, 0x35, 0xFF, 0xC6, 0x95, 0x27, 0xF5, 0x02, 0x02, 0x01, 0x82,
+	0x01, 0x01, 0x00, 0x51, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x6D, 0x60, 0x4A, 0x14, 0xB8, 0xDF, 0xA9, 0x2E, 0xFF, 0xEC, 0xBF, 0x4E, 0xFF,
+	0xF0, 0xC9, 0x5D, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xCC, 0x69, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF,
+	0xF2, 0xD0, 0x74, 0xFF, 0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD3, 0x7D, 0xFF, 0xF4, 0xD5, 0x83, 0xFF,
+	0xF4, 0xD7, 0x88, 0xFF, 0xF4, 0xD8, 0x8C, 0xFF, 0xF5, 0xD9, 0x90, 0xFF, 0xF5, 0xDA, 0x94, 0xFF,
+	0xF5, 0xDB, 0x97, 0xFF, 0xF6, 0xDC, 0x99, 0xFF, 0xF6, 0xDD, 0x9A, 0xFF, 0xF6, 0xDD, 0x9B, 0xFF,
+	0xF6, 0xDD, 0x9B, 0xFF, 0xF6, 0xDD, 0x99, 0xFF, 0xF5, 0xDC, 0x98, 0xFF, 0xF5, 0xDB, 0x96, 0xFF,
+	0xF5, 0xDA, 0x93, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF, 0xF4, 0xD8, 0x8B, 0xFF, 0xF4, 0xD6, 0x86, 0xFF,
+	0xF3, 0xD4, 0x81, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD1, 0x76, 0xFF, 0xF2, 0xCF, 0x72, 0xFF,
+	0xF2, 0xCD, 0x6C, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xC9, 0x60, 0xFF, 0xF0, 0xC8, 0x5B, 0xFF,
+	0xE3, 0xB3, 0x3D, 0xFF, 0xD0, 0x9C, 0x29, 0xFA, 0x00, 0x00, 0x00, 0x8F, 0x00, 0x00, 0x00, 0x5E,
+	0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x47, 0x00, 0x00, 0x00, 0x76, 0x6F, 0x53, 0x16, 0xC4, 0xDC, 0xA7, 0x2E, 0xFF,
+	0xEA, 0xBE, 0x4F, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF2, 0xCD, 0x6B, 0xFF, 0xF2, 0xCF, 0x71, 0xFF,
+	0xF2, 0xD1, 0x77, 0xFF, 0xF3, 0xD3, 0x7D, 0xFF, 0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD7, 0x88, 0xFF,
+	0xF5, 0xD8, 0x8E, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xDC, 0x96, 0xFF, 0xF6, 0xDC, 0x9A, 0xFF,
+	0xF6, 0xDE, 0x9D, 0xFF, 0xF6, 0xDF, 0x9F, 0xFF, 0xF6, 0xDF, 0xA1, 0xFF, 0xF6, 0xDF, 0xA2, 0xFF,
+	0xF6, 0xDF, 0xA1, 0xFF, 0xF6, 0xDF, 0xA1, 0xFF, 0xF6, 0xDE, 0x9E, 0xFF, 0xF6, 0xDD, 0x9C, 0xFF,
+	0xF6, 0xDC, 0x98, 0xFF, 0xF5, 0xDB, 0x94, 0xFF, 0xF5, 0xD9, 0x90, 0xFF, 0xF4, 0xD8, 0x8C, 0xFF,
+	0xF4, 0xD6, 0x85, 0xFF, 0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF, 0xF2, 0xD0, 0x74, 0xFF,
+	0xF2, 0xCE, 0x6F, 0xFF, 0xF1, 0xCC, 0x69, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xE3, 0xB0, 0x3B, 0xFF,
+	0xE0, 0xAA, 0x2F, 0xFF, 0x36, 0x2A, 0x0B, 0xA7, 0x00, 0x00, 0x00, 0x69, 0x00, 0x00, 0x00, 0x3B,
+	0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0D,
+	0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x4E, 0x00, 0x00, 0x00, 0x7C, 0x41, 0x32, 0x0D, 0xB5,
+	0xDE, 0xAA, 0x2F, 0xFF, 0xE6, 0xB8, 0x46, 0xFF, 0xF3, 0xCF, 0x71, 0xFF, 0xF3, 0xD0, 0x75, 0xFF,
+	0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD4, 0x81, 0xFF, 0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD8, 0x8C, 0xFF,
+	0xF5, 0xDA, 0x91, 0xFF, 0xF6, 0xDC, 0x96, 0xFF, 0xF6, 0xDD, 0x9C, 0xFF, 0xF6, 0xDF, 0xA0, 0xFF,
+	0xF7, 0xE0, 0xA3, 0xFF, 0xF7, 0xE1, 0xA6, 0xFF, 0xF7, 0xE2, 0xA7, 0xFF, 0xF7, 0xE2, 0xA8, 0xFF,
+	0xF7, 0xE2, 0xA8, 0xFF, 0xF7, 0xE1, 0xA7, 0xFF, 0xF7, 0xE0, 0xA5, 0xFF, 0xF6, 0xDF, 0xA2, 0xFF,
+	0xF6, 0xDE, 0x9E, 0xFF, 0xF6, 0xDD, 0x9A, 0xFF, 0xF5, 0xDB, 0x95, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF,
+	0xF4, 0xD7, 0x8A, 0xFF, 0xF4, 0xD5, 0x85, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF, 0xF3, 0xD1, 0x78, 0xFF,
+	0xF2, 0xCF, 0x73, 0xFF, 0xF1, 0xCD, 0x6B, 0xFF, 0xE3, 0xB1, 0x38, 0xFF, 0xD1, 0xA0, 0x2D, 0xF9,
+	0x1E, 0x17, 0x06, 0xA0, 0x00, 0x00, 0x00, 0x6D, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, 0x1E,
+	0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x7B,
+	0x36, 0x2B, 0x0C, 0xAE, 0xCD, 0x9E, 0x2C, 0xF7, 0xE7, 0xB6, 0x40, 0xFF, 0xF1, 0xCC, 0x6D, 0xFF,
+	0xF4, 0xD4, 0x81, 0xFF, 0xF4, 0xD5, 0x84, 0xFF, 0xF4, 0xD7, 0x8A, 0xFF, 0xF5, 0xD9, 0x90, 0xFF,
+	0xF5, 0xDC, 0x96, 0xFF, 0xF6, 0xDD, 0x9C, 0xFF, 0xF6, 0xDF, 0xA0, 0xFF, 0xF7, 0xE1, 0xA5, 0xFF,
+	0xF7, 0xE1, 0xA9, 0xFF, 0xF7, 0xE3, 0xAC, 0xFF, 0xF8, 0xE3, 0xAE, 0xFF, 0xF8, 0xE4, 0xB1, 0xFF,
+	0xF8, 0xE4, 0xB0, 0xFF, 0xF7, 0xE3, 0xAD, 0xFF, 0xF7, 0xE2, 0xAB, 0xFF, 0xF7, 0xE2, 0xA7, 0xFF,
+	0xF7, 0xE0, 0xA3, 0xFF, 0xF6, 0xDE, 0x9F, 0xFF, 0xF6, 0xDD, 0x99, 0xFF, 0xF5, 0xDA, 0x94, 0xFF,
+	0xF5, 0xD8, 0x8D, 0xFF, 0xF4, 0xD7, 0x87, 0xFF, 0xF3, 0xD4, 0x82, 0xFF, 0xF3, 0xD3, 0x7D, 0xFF,
+	0xED, 0xC7, 0x61, 0xFF, 0xE8, 0xB5, 0x37, 0xFF, 0xAE, 0x86, 0x25, 0xE5, 0x00, 0x00, 0x00, 0x95,
+	0x00, 0x00, 0x00, 0x6E, 0x00, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x0A,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x4D,
+	0x01, 0x01, 0x00, 0x77, 0x07, 0x06, 0x02, 0x9A, 0xC2, 0x96, 0x2A, 0xEF, 0xE1, 0xAE, 0x30, 0xFF,
+	0xEA, 0xBF, 0x51, 0xFF, 0xF3, 0xD5, 0x83, 0xFF, 0xF5, 0xD9, 0x8E, 0xFF, 0xF5, 0xDB, 0x93, 0xFF,
+	0xF6, 0xDC, 0x99, 0xFF, 0xF6, 0xDE, 0x9F, 0xFF, 0xF7, 0xE0, 0xA5, 0xFF, 0xF7, 0xE2, 0xA9, 0xFF,
+	0xF8, 0xE4, 0xAF, 0xFF, 0xF8, 0xE6, 0xB5, 0xFF, 0xF9, 0xE8, 0xBB, 0xFF, 0xF9, 0xE8, 0xBE, 0xFF,
+	0xF9, 0xE8, 0xBD, 0xFF, 0xF9, 0xE7, 0xB9, 0xFF, 0xF8, 0xE4, 0xB1, 0xFF, 0xF7, 0xE3, 0xAD, 0xFF,
+	0xF7, 0xE2, 0xA7, 0xFF, 0xF7, 0xDF, 0xA2, 0xFF, 0xF6, 0xDD, 0x9D, 0xFF, 0xF5, 0xDC, 0x97, 0xFF,
+	0xF5, 0xDA, 0x91, 0xFF, 0xF4, 0xD7, 0x8B, 0xFF, 0xF2, 0xD1, 0x79, 0xFF, 0xE7, 0xB6, 0x3E, 0xFF,
+	0xDD, 0xAB, 0x31, 0xFC, 0x7F, 0x63, 0x1C, 0xD0, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00, 0x00, 0x69,
+	0x00, 0x00, 0x00, 0x42, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x27,
+	0x00, 0x00, 0x00, 0x46, 0x00, 0x00, 0x00, 0x6A, 0x00, 0x00, 0x00, 0x8B, 0x28, 0x1F, 0x08, 0xB1,
+	0xC0, 0x93, 0x29, 0xF1, 0xE9, 0xB6, 0x39, 0xFF, 0xEC, 0xC2, 0x59, 0xFF, 0xF5, 0xDA, 0x92, 0xFF,
+	0xF7, 0xDF, 0xA0, 0xFF, 0xF7, 0xE0, 0xA3, 0xFF, 0xF7, 0xE1, 0xA8, 0xFF, 0xF8, 0xE3, 0xAE, 0xFF,
+	0xF9, 0xE6, 0xB7, 0xFF, 0xFA, 0xEA, 0xC2, 0xFF, 0xFA, 0xED, 0xCA, 0xFF, 0xFB, 0xEE, 0xCF, 0xFF,
+	0xFA, 0xEE, 0xCD, 0xFF, 0xFA, 0xEC, 0xC7, 0xFF, 0xF9, 0xE9, 0xBE, 0xFF, 0xF8, 0xE4, 0xB2, 0xFF,
+	0xF7, 0xE3, 0xAC, 0xFF, 0xF7, 0xE1, 0xA6, 0xFF, 0xF6, 0xE0, 0xA2, 0xFF, 0xF7, 0xDF, 0x9F, 0xFF,
+	0xF3, 0xD4, 0x83, 0xFF, 0xE7, 0xB8, 0x43, 0xFF, 0xEF, 0xBA, 0x38, 0xFF, 0x91, 0x71, 0x21, 0xDC,
+	0x16, 0x11, 0x05, 0xA5, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x5F, 0x00, 0x00, 0x00, 0x3B,
+	0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x0C,
+	0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x5B, 0x00, 0x00, 0x00, 0x79,
+	0x00, 0x00, 0x00, 0x92, 0x5A, 0x46, 0x15, 0xC1, 0xC0, 0x95, 0x2B, 0xF0, 0xEB, 0xB7, 0x32, 0xFF,
+	0xED, 0xBF, 0x49, 0xFF, 0xEE, 0xC9, 0x69, 0xFF, 0xF4, 0xD9, 0x90, 0xFF, 0xF8, 0xE6, 0xB6, 0xFF,
+	0xFA, 0xEC, 0xC8, 0xFF, 0xFB, 0xF0, 0xD4, 0xFF, 0xFC, 0xF4, 0xDE, 0xFF, 0xFD, 0xF6, 0xE4, 0xFF,
+	0xFC, 0xF5, 0xE2, 0xFF, 0xFC, 0xF3, 0xDA, 0xFF, 0xFB, 0xEF, 0xCF, 0xFF, 0xFA, 0xEB, 0xC4, 0xFF,
+	0xF7, 0xE2, 0xA9, 0xFF, 0xF2, 0xD4, 0x84, 0xFF, 0xED, 0xC5, 0x5E, 0xFF, 0xED, 0xBC, 0x3E, 0xFF,
+	0xE8, 0xB2, 0x2F, 0xFF, 0xA9, 0x84, 0x27, 0xE5, 0x2A, 0x21, 0x09, 0xAE, 0x00, 0x00, 0x00, 0x89,
+	0x00, 0x00, 0x00, 0x71, 0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x19,
+	0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x2E, 0x00, 0x00, 0x00, 0x49,
+	0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 0x7D, 0x00, 0x00, 0x00, 0x91, 0x12, 0x0F, 0x05, 0xAC,
+	0x9A, 0x7A, 0x25, 0xDF, 0xD4, 0xA7, 0x33, 0xF5, 0xE0, 0xB0, 0x32, 0xFC, 0xEA, 0xB6, 0x30, 0xFF,
+	0xEE, 0xC2, 0x4F, 0xFF, 0xF2, 0xCE, 0x70, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD3, 0x7F, 0xFF,
+	0xF3, 0xD4, 0x7F, 0xFF, 0xF2, 0xD2, 0x7B, 0xFF, 0xF0, 0xC9, 0x62, 0xFF, 0xEB, 0xBA, 0x39, 0xFF,
+	0xE8, 0xB5, 0x31, 0xFF, 0xDD, 0xAE, 0x33, 0xFB, 0xD4, 0xA7, 0x33, 0xF4, 0x77, 0x5D, 0x1B, 0xD0,
+	0x00, 0x00, 0x00, 0x9E, 0x00, 0x00, 0x00, 0x8B, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, 0x5C,
+	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x05,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x1D,
+	0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x4C, 0x00, 0x00, 0x00, 0x63, 0x00, 0x00, 0x00, 0x76,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0xCC, 0xFF, 0xBA, 0xFF, 0xAA, 0xFF, 0x99, 0xFF, 0x87, 0xFE,
+	0x76, 0xFE, 0x55, 0xFE, 0x44, 0xFE, 0x43, 0xFE, 0x33, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x33, 0xFE, 0x43, 0xFE, 0x44, 0xFE, 0x55, 0xFE, 0x76, 0xFE, 0x87, 0xFE,
+	0x99, 0xFF, 0xAA, 0xFF, 0xBA, 0xFF, 0xCC, 0xFF, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0xCC, 0xFF, 0xAA, 0xFF, 0x77, 0xFE, 0x55, 0xFE,
+	0x21, 0xFE, 0x00, 0xFE, 0x10, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x21, 0xFE, 0x21, 0xFE, 0x21, 0xFE,
+	0x22, 0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x21, 0xFE,
+	0x21, 0xFE, 0x21, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0x10, 0xFE, 0x00, 0xFE, 0x21, 0xFE, 0x55, 0xFE,
+	0x77, 0xFE, 0xAA, 0xFF, 0xCC, 0xFF, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0xBB, 0xFF,
+	0x98, 0xFE, 0x66, 0xFE, 0x22, 0xFE, 0x00, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x21, 0xFE, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE,
+	0x21, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0x00, 0xFE, 0x22, 0xFE, 0x66, 0xFE, 0x98, 0xFE, 0xBB, 0xFF,
+	0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0xBB, 0xFF, 0x88, 0xFF, 0x43, 0xFE, 0x10, 0xFE, 0x11, 0xFE,
+	0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0x11, 0xFE,
+	0x10, 0xFE, 0x43, 0xFE, 0x88, 0xFF, 0xBB, 0xFF, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF,
+	0x99, 0xFF, 0x44, 0xFE, 0x11, 0xFE, 0x11, 0xFE, 0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0x11, 0xFE, 0x11, 0xFE, 0x44, 0xFE, 0x99, 0xFF, 0xDD, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x88, 0xFF, 0x21, 0xFE, 0x10, 0xFE,
+	0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0x10, 0xFE,
+	0x21, 0xFE, 0x88, 0xFF, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xDD, 0xFF, 0x88, 0xFF, 0x21, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x88, 0xFF, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0xAA, 0xFF,
+	0x43, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0x43, 0xFE, 0xAA, 0xFF,
+	0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x76, 0xFE, 0x11, 0xFE, 0x21, 0xFE,
+	0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE,
+	0x11, 0xFE, 0x76, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x44, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0x44, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xAA, 0xFF, 0x22, 0xFE, 0x11, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x11, 0xFE, 0x22, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF, 0x11, 0xFE,
+	0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0x11, 0xFE,
+	0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x21, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x32, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xCC, 0xFF, 0x43, 0xFE, 0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x10, 0xFE, 0x43, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x66, 0xFF,
+	0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x10, 0xFE, 0x66, 0xFF,
+	0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF, 0x00, 0xFE, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0x00, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x43, 0xFE, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x11, 0xFE, 0x43, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFF, 0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x10, 0xFE, 0x88, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xDD, 0xFF, 0x43, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x43, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF,
+	0x00, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x00, 0xFE, 0x99, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x55, 0xFE, 0x11, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE,
+	0x55, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x21, 0xFE, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x21, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF,
+	0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0xCC, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x00, 0xFE,
+	0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x00, 0xFE,
+	0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x10, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x87, 0xFE, 0x87, 0xFE, 0x77, 0xFE, 0x66, 0xFE, 0x55, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0x00, 0xFE,
+	0x00, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0x11, 0xFE,
+	0x00, 0xFE, 0x21, 0xFE, 0x44, 0xFE, 0x88, 0xFE, 0xAA, 0xFF, 0xCC, 0xFF, 0xDD, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xEE, 0xFF, 0xDD, 0xFF, 0xAA, 0xFF, 0x98, 0xFE, 0x55, 0xFE, 0x22, 0xFE, 0x10, 0xFE, 0x11, 0xFE,
+	0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x11, 0xFE, 0x00, 0xFE, 0x44, 0xFE, 0x87, 0xFE, 0xBB, 0xFF,
+	0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0xBB, 0xFF,
+	0x88, 0xFE, 0x44, 0xFE, 0x10, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0x10, 0xFE, 0x21, 0xFE, 0x77, 0xFE, 0xBB, 0xFF, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0xBB, 0xFF, 0x77, 0xFE, 0x21, 0xFE, 0x00, 0xFE, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x55, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x10, 0xFE, 0x10, 0xFE, 0x77, 0xFE,
+	0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x87, 0xFE,
+	0x11, 0xFE, 0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x55, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x88, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x00, 0xFE, 0x55, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xBB, 0xFF, 0x55, 0xFE, 0x00, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF,
+	0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x10, 0xFE, 0x87, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x88, 0xFE, 0x11, 0xFE, 0x11, 0xFE, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xBA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x10, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0x21, 0xFE,
+	0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x32, 0xFE,
+	0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE,
+	0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x43, 0xFE, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0x22, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xBA, 0xFF, 0x32, 0xFE, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE,
+	0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x77, 0xFE, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x77, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x22, 0xFE, 0x00, 0xFE, 0x87, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE, 0x00, 0xFE, 0x22, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE,
+	0x44, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x55, 0xFE, 0x10, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x10, 0xFE, 0xAA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF,
+	0x11, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x66, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0x55, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xEE, 0xAF, 0x66, 0xFE, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x00, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x22, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x77, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x77, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x22, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x77, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0x98, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x10, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0x98, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x98, 0xFE, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF,
+	0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0x99, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF,
+	0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xAA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0x99, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xCC, 0xFF, 0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFF, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xDD, 0xFF, 0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0x88, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x10, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x00, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x11, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x10, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFF, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x11, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x76, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x10, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x66, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF,
+	0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x66, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xBA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x99, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x76, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x66, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x76, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xEE, 0xAF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x00, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x98, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x98, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0x98, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xBA, 0xFF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x66, 0xFE, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x55, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x11, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x55, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF,
+	0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x10, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x10, 0xFE,
+	0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xDD, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE,
+	0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE,
+	0x55, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF,
+	0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x22, 0xFE,
+	0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x10, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x98, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF,
+	0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE,
+	0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x77, 0xFE, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0x77, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x10, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x10, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x10, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x44, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x10, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x77, 0xFE, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x77, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x55, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x11, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF,
+	0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x10, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x43, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x98, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x43, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x10, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x22, 0xFE, 0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x22, 0xFE, 0x11, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x87, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x22, 0xFE, 0x11, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x98, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x10, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x43, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x22, 0xFE, 0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x00, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x55, 0xFE, 0x22, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x11, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x11, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x00, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF,
+	0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0xEE, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE,
+	0x55, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xBA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE,
+	0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xAA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE,
+	0x21, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x66, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x22, 0xFE, 0x21, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xEE, 0xAF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x33, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x44, 0xFE,
+	0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xCC, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x77, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE,
+	0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xBA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF,
+	0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0x88, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xEE, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF,
+	0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFF, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0x55, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF,
+	0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x33, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x55, 0xFE, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x66, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x99, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x22, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x77, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x99, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x99, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE,
+	0x33, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xAA, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00,
+	0xEE, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x98, 0xFE, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x22, 0xFE, 0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xDD, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xEE, 0xFF, 0x00, 0x00,
+	0xDD, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x98, 0xFE, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xEE, 0xAF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xDD, 0xFF, 0x00, 0x00,
+	0xBB, 0xFF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xBB, 0xFF, 0x00, 0x00,
+	0xAA, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE, 0x10, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x33, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x44, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xAA, 0xFF, 0x00, 0x00,
+	0x99, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x66, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE, 0x10, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x77, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x99, 0xFF, 0x00, 0x00,
+	0x88, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE,
+	0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x44, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x98, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFE, 0x00, 0x00,
+	0x77, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x87, 0xFE, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x44, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x77, 0xFE, 0x00, 0x00,
+	0x66, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x87, 0xFE, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0x44, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xBB, 0xFF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x66, 0xFE, 0x00, 0x00,
+	0x44, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x77, 0xFE, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x44, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xDD, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x44, 0xFE, 0x00, 0x00,
+	0x43, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x77, 0xFE, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x44, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x43, 0xFE, 0x00, 0x00,
+	0x33, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x77, 0xFE, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x55, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x33, 0xFE, 0x00, 0x00,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x77, 0xFE, 0x11, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x55, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xEE, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0x00,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x77, 0xFE, 0x11, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x55, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xEE, 0xAF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0x00,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE,
+	0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x55, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xEE, 0xAF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0x00,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x66, 0xFE, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x55, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xEE, 0xAF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0x00,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x66, 0xFE, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0x66, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xEE, 0xAF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0x00,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x66, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xEE, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0x00,
+	0x33, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x66, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xEE, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x33, 0xFE, 0x00, 0x00,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x55, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x66, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x43, 0xFE, 0x00, 0x00,
+	0x44, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x55, 0xFE, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x66, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xDD, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x44, 0xFE, 0x00, 0x00,
+	0x66, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x55, 0xFE, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0x76, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xBB, 0xFF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x66, 0xFE, 0x00, 0x00,
+	0x77, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x55, 0xFE,
+	0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0x77, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x77, 0xFE, 0x00, 0x00,
+	0x88, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x55, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0x77, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x98, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFE, 0x00, 0x00,
+	0x99, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x66, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x55, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE,
+	0x77, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x77, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x99, 0xFF, 0x00, 0x00,
+	0xAA, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x44, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x10, 0xFE, 0x77, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x44, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xAA, 0xFF, 0x00, 0x00,
+	0xBB, 0xFF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x44, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x10, 0xFE, 0x77, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xBB, 0xFF, 0x00, 0x00,
+	0xDD, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x44, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0x87, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xEE, 0xAF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xDD, 0xFF, 0x00, 0x00,
+	0xEE, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x44, 0xFE, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0x88, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xDD, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xEE, 0xFF, 0x00, 0x00,
+	0xFF, 0x0F, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x99, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x44, 0xFE, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0x88, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xAA, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x66, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x33, 0xFE,
+	0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0x88, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x77, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0x55, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x33, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0x88, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x43, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x55, 0xFE, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0x88, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xEE, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x43, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE,
+	0x98, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF,
+	0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFF, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xBA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x43, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x10, 0xFE, 0x98, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF,
+	0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xCC, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x77, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x33, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0x98, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE,
+	0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xEE, 0xAF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x44, 0xFE,
+	0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x22, 0xFE, 0x22, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x32, 0xFE, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x66, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE,
+	0x44, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x32, 0xFE,
+	0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0x99, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x00, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF,
+	0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xAA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xEE, 0xAF, 0x22, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x43, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x22, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xEE, 0xAF, 0x11, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x00, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x55, 0xFE, 0x22, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x77, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x77, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x76, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x43, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x21, 0xFE, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x22, 0xFE, 0x43, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x10, 0xFE,
+	0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x43, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF,
+	0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xBB, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x10, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x33, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xDD, 0xFF, 0x11, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x44, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x11, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x76, 0xFE, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xDD, 0xFF, 0x11, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x00, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x76, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x10, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x33, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x44, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x10, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x10, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xBB, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x10, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x76, 0xFE, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0x76, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x10, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF,
+	0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE,
+	0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x10, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFF,
+	0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE,
+	0x55, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF,
+	0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF,
+	0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x10, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xDD, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x44, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x10, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x44, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xBA, 0xFF, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x55, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0x66, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0x98, 0xFE, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x88, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xEE, 0xAF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x55, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x76, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0x87, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF,
+	0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xAA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xBB, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x66, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xBB, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x22, 0xFE, 0x66, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x10, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFF, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x66, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x10, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x10, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x77, 0xFE, 0x21, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0x77, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x11, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF,
+	0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE,
+	0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF,
+	0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xAA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xAA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xAA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0x87, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xAA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x11, 0xFE, 0x55, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x76, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x21, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x98, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x76, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0x55, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xEE, 0xAF, 0x66, 0xFE, 0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0xAA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF,
+	0x11, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x66, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE,
+	0x44, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0x55, 0xFE, 0x10, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBB, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x22, 0xFE, 0x00, 0xFE, 0x87, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x88, 0xFE, 0x00, 0xFE, 0x22, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x00, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x77, 0xFE, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x11, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x77, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x33, 0xFE, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0x32, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xBA, 0xFF, 0x32, 0xFE, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE,
+	0x33, 0xFE, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x10, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0x22, 0xFE,
+	0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x32, 0xFE,
+	0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE,
+	0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF,
+	0x10, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x11, 0xFE, 0x88, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x98, 0xFE, 0x21, 0xFE, 0x11, 0xFE, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x10, 0xFE, 0xAA, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0x88, 0xFF, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x00, 0xFE, 0x55, 0xFE, 0xBB, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xCC, 0xFF, 0x66, 0xFE, 0x00, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x88, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0x44, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x87, 0xFE,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x22, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x10, 0xFE, 0x21, 0xFE, 0x77, 0xFE, 0xBB, 0xFF, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0xBB, 0xFF, 0x77, 0xFE, 0x21, 0xFE, 0x00, 0xFE, 0x21, 0xFE,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0xEE, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xFF, 0xBB, 0xFF,
+	0x88, 0xFE, 0x44, 0xFE, 0x10, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x00, 0xFE, 0x21, 0xFE, 0x55, 0xFE, 0x88, 0xFE, 0xAA, 0xFF, 0xCC, 0xFF, 0xEE, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xEE, 0xFF, 0xCC, 0xFF, 0xAA, 0xFF, 0x88, 0xFE, 0x55, 0xFE, 0x22, 0xFE, 0x00, 0xFE, 0x11, 0xFE,
+	0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x00, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0x00, 0xFE, 0x00, 0xFE,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF, 0x00, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x00, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x00, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x00, 0xFE,
+	0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF,
+	0x11, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x11, 0xFE, 0xCC, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xEE, 0xFF, 0x33, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x33, 0xFE, 0xEE, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0x66, 0xFE, 0x11, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x44, 0xFE, 0x11, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE,
+	0x44, 0xFE, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF,
+	0x00, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
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+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
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+	0x32, 0xFE, 0x21, 0xFE, 0x33, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF, 0x00, 0xFE, 0x21, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
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+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE,
+	0x00, 0xFE, 0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0x66, 0xFF,
+	0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x10, 0xFE, 0x66, 0xFF,
+	0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xCC, 0xFF, 0x43, 0xFE, 0x10, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x10, 0xFE, 0x43, 0xFE, 0xCC, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x32, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x11, 0xFE, 0x32, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xAA, 0xFF, 0x21, 0xFE, 0x21, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x21, 0xFE, 0x21, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x99, 0xFF, 0x11, 0xFE,
+	0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0x11, 0xFE,
+	0x99, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xAA, 0xFF, 0x22, 0xFE, 0x11, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x11, 0xFE, 0x22, 0xFE, 0xAA, 0xFF, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xBA, 0xFF, 0x44, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0x44, 0xFE, 0xBA, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0x76, 0xFE, 0x11, 0xFE, 0x21, 0xFE,
+	0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE,
+	0x11, 0xFE, 0x76, 0xFE, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0xAA, 0xFF,
+	0x43, 0xFE, 0x00, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x21, 0xFE, 0x00, 0xFE, 0x44, 0xFE, 0xAA, 0xFF,
+	0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xDD, 0xFF, 0x88, 0xFF, 0x21, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x88, 0xFF, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xCC, 0xFF, 0x88, 0xFF, 0x21, 0xFE, 0x10, 0xFE,
+	0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0x10, 0xFE,
+	0x21, 0xFE, 0x88, 0xFF, 0xCC, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF,
+	0x99, 0xFF, 0x44, 0xFE, 0x11, 0xFE, 0x11, 0xFE, 0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0x11, 0xFE, 0x11, 0xFE, 0x44, 0xFE, 0x99, 0xFF, 0xDD, 0xFF,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0xBB, 0xFF, 0x88, 0xFF, 0x43, 0xFE, 0x11, 0xFE, 0x11, 0xFE,
+	0x21, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x21, 0xFE, 0x11, 0xFE,
+	0x11, 0xFE, 0x43, 0xFE, 0x88, 0xFF, 0xBB, 0xFF, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0xBB, 0xFF,
+	0x99, 0xFF, 0x66, 0xFE, 0x22, 0xFE, 0x10, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x21, 0xFE, 0x22, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE,
+	0x21, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0x10, 0xFE, 0x22, 0xFE, 0x66, 0xFE, 0x99, 0xFF, 0xBB, 0xFF,
+	0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xEE, 0xAF, 0xCC, 0xFF, 0xAA, 0xFF, 0x77, 0xFE, 0x55, 0xFE,
+	0x21, 0xFE, 0x00, 0xFE, 0x10, 0xFE, 0x10, 0xFE, 0x21, 0xFE, 0x21, 0xFE, 0x21, 0xFE, 0x21, 0xFE,
+	0x22, 0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x22, 0xFE, 0x21, 0xFE,
+	0x21, 0xFE, 0x21, 0xFE, 0x21, 0xFE, 0x10, 0xFE, 0x10, 0xFE, 0x00, 0xFE, 0x21, 0xFE, 0x55, 0xFE,
+	0x77, 0xFE, 0xAA, 0xFF, 0xCC, 0xFF, 0xEE, 0xAF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xDD, 0xFF, 0xCC, 0xFF, 0xBA, 0xFF, 0xAA, 0xFF, 0x99, 0xFF, 0x87, 0xFE,
+	0x76, 0xFE, 0x55, 0xFE, 0x44, 0xFE, 0x43, 0xFE, 0x33, 0xFE, 0x32, 0xFE, 0x32, 0xFE, 0x32, 0xFE,
+	0x32, 0xFE, 0x32, 0xFE, 0x33, 0xFE, 0x43, 0xFE, 0x44, 0xFE, 0x55, 0xFE, 0x76, 0xFE, 0x87, 0xFE,
+	0x99, 0xFF, 0xAA, 0xFF, 0xBA, 0xFF, 0xCC, 0xFF, 0xDD, 0xFF, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F,
+	0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0xFF, 0x0F, 0x00, 0x00,
+	0x89, 0x50, 0x4E, 0x47, 0x0D, 0x0A, 0x1A, 0x0A, 0x00, 0x00, 0x00, 0x0D, 0x49, 0x48, 0x44, 0x52,
+	0x00, 0x00, 0x00, 0x37, 0x00, 0x00, 0x00, 0x37, 0x08, 0x06, 0x00, 0x00, 0x00, 0xA8, 0xDB, 0xD2,
+	0x46, 0x00, 0x00, 0x00, 0x06, 0x62, 0x4B, 0x47, 0x44, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0xA0,
+	0xBD, 0xA7, 0x93, 0x00, 0x00, 0x0F, 0xF6, 0x49, 0x44, 0x41, 0x54, 0x68, 0xDE, 0xDD, 0x9A, 0x7B,
+	0x90, 0x1C, 0x57, 0x75, 0xC6, 0x7F, 0xE7, 0xDC, 0xEE, 0x99, 0xD9, 0xD9, 0x9D, 0x5D, 0xAD, 0x9E,
+	0x96, 0x25, 0xCB, 0x92, 0x11, 0xC6, 0x0A, 0x76, 0x4C, 0x0C, 0xC4, 0xD8, 0x08, 0x1C, 0xEC, 0x60,
+	0x2A, 0x95, 0x14, 0xAE, 0x24, 0x50, 0x21, 0xA6, 0x8A, 0x54, 0x2A, 0x40, 0x08, 0x54, 0x92, 0x2A,
+	0x42, 0x25, 0x21, 0x21, 0x24, 0x54, 0x8A, 0xBC, 0x29, 0x5E, 0x15, 0x42, 0x12, 0xA8, 0x22, 0x81,
+	0x90, 0x3F, 0xFC, 0x0F, 0x26, 0x8E, 0xA9, 0xC2, 0xBC, 0x5C, 0x24, 0xF8, 0x41, 0x62, 0xFC, 0x20,
+	0x92, 0xB1, 0xAD, 0x87, 0x6D, 0x69, 0x57, 0xD2, 0x4A, 0xAB, 0x7D, 0xCC, 0xEE, 0x3C, 0xBA, 0xFB,
+	0x9E, 0xFC, 0x71, 0x6F, 0xCF, 0xF4, 0xAC, 0x56, 0xD8, 0xC6, 0x36, 0xA1, 0xA2, 0xAA, 0xAB, 0xE9,
+	0x7B, 0x77, 0xA6, 0xBB, 0xBF, 0xFB, 0x7D, 0xE7, 0x3B, 0xE7, 0xDE, 0x6E, 0xF8, 0x7F, 0xFC, 0x4F,
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+	0xA0, 0x84, 0x13, 0x85, 0x21, 0x84, 0xA4, 0x23, 0x69, 0x84, 0x30, 0x8E, 0xC0, 0x0D, 0x88, 0x33,
+	0xA4, 0x92, 0xD3, 0xD1, 0x61, 0xE9, 0xD1, 0xD4, 0x20, 0x7D, 0x84, 0x04, 0x3B, 0x5C, 0x90, 0x10,
+	0x79, 0xA5, 0x56, 0xC3, 0x91, 0xA9, 0xB8, 0xF7, 0x81, 0x2D, 0xAB, 0x8B, 0x1F, 0x7D, 0xF4, 0xCF,
+	0x7F, 0xE4, 0x25, 0xBF, 0xE3, 0xB6, 0x27, 0x9F, 0x06, 0x3E, 0x09, 0x3C, 0x34, 0x32, 0x7B, 0xFB,
+	0xA4, 0x8E, 0x8D, 0xAF, 0x11, 0xD4, 0xED, 0x28, 0x6B, 0xA4, 0xBF, 0x72, 0xA1, 0xBF, 0xFC, 0xC7,
+	0xBF, 0x79, 0xA1, 0x7F, 0xDE, 0x77, 0xDD, 0x78, 0xA5, 0x0D, 0x8A, 0x2D, 0x09, 0x4F, 0x2F, 0x7A,
+	0x66, 0x2A, 0xA4, 0xA1, 0x05, 0x12, 0x06, 0x02, 0x8A, 0xC1, 0x13, 0x2C, 0x3A, 0x74, 0x3B, 0x70,
+	0x18, 0xA6, 0xA4, 0x41, 0x47, 0x94, 0xE4, 0x44, 0xE1, 0x92, 0xB4, 0x2F, 0x69, 0x34, 0x40, 0xE7,
+	0x9E, 0xA8, 0xF1, 0x18, 0x3C, 0xAD, 0x16, 0x04, 0x76, 0x60, 0xBB, 0xF6, 0x48, 0xED, 0x58, 0x9B,
+	0x81, 0x8F, 0x5D, 0xA8, 0x79, 0xF0, 0x91, 0x2B, 0xFE, 0xE2, 0xFF, 0xFC, 0xAD, 0xFB, 0x1E, 0xFE,
+	0xF7, 0xFF, 0xEC, 0x3D, 0xC0, 0x27, 0x46, 0x8B, 0x5D, 0x04, 0x1E, 0x1D, 0xE7, 0xF4, 0x75, 0xE9,
+	0x43, 0x39, 0x33, 0x1E, 0xCB, 0x9F, 0x05, 0x9E, 0x03, 0x9C, 0x8D, 0x6E, 0xBD, 0xFD, 0xD6, 0x3B,
+	0xDE, 0xF0, 0xD6, 0x57, 0xE6, 0xB7, 0xBC, 0x20, 0x7B, 0xF6, 0x64, 0xE0, 0x5B, 0x6E, 0x4C, 0x98,
+	0x46, 0x2D, 0x13, 0x0F, 0xCA, 0x8C, 0x20, 0x72, 0x14, 0x13, 0x43, 0xDE, 0xEC, 0x88, 0xE2, 0x62,
+	0xFC, 0xD8, 0x80, 0x76, 0x8E, 0x93, 0x38, 0x66, 0x7D, 0x72, 0x82, 0x27, 0xC1, 0x93, 0xB0, 0x45,
+	0xB1, 0xD2, 0xF1, 0xE8, 0xD5, 0x1D, 0x7F, 0xB4, 0xDB, 0xB1, 0x1B, 0x16, 0x5C, 0x7D, 0xEF, 0xDB,
+	0xEF, 0xBF, 0xF0, 0xEB, 0xBF, 0xF0, 0xE1, 0x6E, 0xF9, 0xD8, 0x43, 0x23, 0x71, 0x7C, 0x76, 0xD4,
+	0x8F, 0x17, 0xF6, 0x3D, 0x21, 0x5F, 0xBF, 0x26, 0x1B, 0x19, 0x7B, 0x15, 0xCE, 0x8E, 0x8D, 0x18,
+	0x77, 0x8E, 0x80, 0xCF, 0x1E, 0xBE, 0xFC, 0x07, 0x9E, 0x7D, 0xF8, 0x7D, 0x3F, 0xF4, 0xBC, 0xE2,
+	0xD6, 0xE7, 0xCF, 0xA7, 0x53, 0xCB, 0xD9, 0xD2, 0xF3, 0xAD, 0x49, 0xC0, 0x37, 0x07, 0x8E, 0x6C,
+	0x16, 0x73, 0x83, 0x24, 0x88, 0xB4, 0x24, 0xCE, 0x23, 0xD6, 0xB2, 0x0E, 0x23, 0x5C, 0x5B, 0xB3,
+	0x6D, 0x52, 0xCE, 0xBB, 0x86, 0xCF, 0x2F, 0x77, 0x7C, 0xA6, 0x11, 0x1E, 0x58, 0x19, 0x76, 0x6D,
+	0x4B, 0x75, 0xCF, 0x47, 0xCE, 0x5D, 0x79, 0xC7, 0x4F, 0x7D, 0xE2, 0xE4, 0x91, 0xCF, 0x7C, 0x66,
+	0x8C, 0xBB, 0xF7, 0x8F, 0xC4, 0xF1, 0x05, 0xE0, 0xB1, 0x53, 0x05, 0xF2, 0x54, 0xF4, 0x7E, 0xC5,
+	0xC0, 0xF5, 0xA3, 0x4C, 0xBB, 0x11, 0xB8, 0x09, 0xB8, 0x19, 0x48, 0xA5, 0x98, 0xDE, 0xF6, 0x9C,
+	0x37, 0xFC, 0xE2, 0xED, 0xD3, 0xBB, 0x9E, 0x7D, 0xCB, 0x49, 0x76, 0x73, 0xE2, 0x4C, 0x62, 0x9E,
+	0xBB, 0x50, 0x0E, 0x30, 0x4C, 0x16, 0x86, 0x5C, 0x3D, 0xF4, 0xCA, 0xA0, 0x70, 0xA9, 0x12, 0x3E,
+	0xB5, 0xDB, 0xB0, 0xEC, 0x27, 0x98, 0x76, 0x35, 0xCC, 0xDA, 0xA6, 0xFD, 0xFC, 0x7B, 0xDF, 0xF6,
+	0xE0, 0x17, 0x7E, 0xE3, 0x97, 0x3E, 0x36, 0xBA, 0xDD, 0x66, 0xA4, 0xF8, 0x8B, 0x23, 0xB0, 0x2B,
+	0x8F, 0x0F, 0xD2, 0x4F, 0x65, 0xD7, 0xDE, 0xC1, 0x58, 0xCC, 0xBD, 0x7E, 0x7C, 0xBE, 0x79, 0x3C,
+	0x84, 0xB8, 0x51, 0x8C, 0x9D, 0x05, 0xF9, 0xC4, 0x12, 0xA5, 0x87, 0xB3, 0xEF, 0xF8, 0xF6, 0xB3,
+	0xF9, 0xCD, 0x2F, 0x9B, 0x04, 0x81, 0x09, 0xF7, 0x9D, 0x0E, 0x00, 0x22, 0xA2, 0x47, 0xC7, 0x27,
+	0xFF, 0xE3, 0xFD, 0x97, 0x96, 0xE7, 0xEE, 0xEB, 0xB4, 0x6F, 0xAF, 0xBA, 0x6A, 0xBB, 0x1C, 0x5D,
+	0xED, 0xC2, 0x08, 0xE2, 0xDC, 0xF8, 0xF7, 0xB9, 0x6B, 0xA8, 0x5E, 0xFF, 0x7F, 0x81, 0x3B, 0xBD,
+	0x0E, 0xAF, 0x01, 0x39, 0x1D, 0xCB, 0x1F, 0xE5, 0xE8, 0xB2, 0xE9, 0x18, 0x2B, 0x4F, 0xEB, 0xDE,
+	0x76, 0x54, 0x11, 0xFD, 0xE8, 0x5A, 0xC3, 0x68, 0xA1, 0x53, 0xD2, 0x3A, 0x1A, 0x2D, 0xB4, 0x01,
+	0x2E, 0x8F, 0xF7, 0xCD, 0x37, 0x42, 0xA7, 0x6C, 0x3C, 0xBA, 0xEA, 0xC1, 0x08, 0xD2, 0x8C, 0x7B,
+	0xD3, 0x8E, 0x00, 0xB3, 0x6B, 0x56, 0x5E, 0x46, 0xEB, 0x98, 0x51, 0x2C, 0x6C, 0xC7, 0x90, 0xF3,
+	0xF8, 0xE7, 0x6F, 0xC8, 0x1E, 0xE7, 0xD9, 0x38, 0xF6, 0x29, 0x48, 0x19, 0x01, 0xF6, 0xD7, 0xDC,
+	0x4F, 0xAF, 0x66, 0x04, 0xB3, 0xFA, 0x5A, 0xDD, 0xEE, 0xAF, 0xAE, 0x81, 0xFB, 0x71, 0xDD, 0x48,
+	0x5F, 0x6C, 0xCC, 0xFB, 0xD2, 0xFB, 0xF0, 0x54, 0x7E, 0xF4, 0xFF, 0x01, 0xEA, 0x26, 0x7E, 0xAE,
+	0x7F, 0xD7, 0xC3, 0x8E, 0x00, 0x00, 0x00, 0x00, 0x49, 0x45, 0x4E, 0x44, 0xAE, 0x42, 0x60, 0x82,
+};
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/Images/BinaryImage_RZ_A1H_70RT.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,72650 @@
+#include  "r_ospl.h"
+#include "lcd_panel.h"
+#if (LCD_VDC5_CH0_PANEL == LCD_CH0_PANEL_VKLCD70RT)
+R_OSPL_ALIGNMENT( 0x20,
+const uint8_t  RGA_Sample_BinaryImage[0x0011BC08uL] ) =
+{
+	0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60,
+	0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x22, 0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D,
+	0x00, 0x2A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x01, 0x12, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x02, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x04, 0x03, 0x02, 0x02,
+	0x02, 0x02, 0x05, 0x04, 0x04, 0x03, 0x04, 0x06, 0x05, 0x06, 0x06, 0x06, 0x05, 0x06, 0x06, 0x06,
+	0x07, 0x09, 0x08, 0x06, 0x07, 0x09, 0x07, 0x06, 0x06, 0x08, 0x0B, 0x08, 0x09, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x06, 0x08, 0x0B, 0x0C, 0x0B, 0x0A, 0x0C, 0x09, 0x0A, 0x0A, 0x0A, 0xFF, 0xDB, 0x00,
+	0x43, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x05, 0x03, 0x03, 0x05, 0x0A, 0x07, 0x06, 0x07,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x01, 0x42, 0x02, 0x06, 0x03, 0x01, 0x22, 0x00, 0x02,
+	0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00, 0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+	0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03,
+	0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04,
+	0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81,
+	0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82,
+	0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36,
+	0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
+	0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76,
+	0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95,
+	0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3,
+	0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA,
+	0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
+	0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00,
+	0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4,
+	0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00,
+	0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51,
+	0x07, 0x61, 0x71, 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23,
+	0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18,
+	0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45,
+	0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65,
+	0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84,
+	0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2,
+	0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9,
+	0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7,
+	0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5,
+	0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11,
+	0x00, 0x3F, 0x00, 0xFD, 0xFC, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x01, 0xB3, 0x12, 0x23,
+	0x24, 0x0F, 0xA5, 0x7C, 0xBB, 0xF1, 0x33, 0xF6, 0xD4, 0xF1, 0xC7, 0x81, 0xED, 0xA3, 0x9A, 0xDA,
+	0xD7, 0x4D, 0xDF, 0x2C, 0x87, 0xF7, 0x77, 0x16, 0x6F, 0xF2, 0xAF, 0x5F, 0xF9, 0xEB, 0xCF, 0x5F,
+	0x6A, 0xFA, 0x8A, 0x43, 0xF2, 0x57, 0xE4, 0xF7, 0xED, 0x21, 0xF1, 0x51, 0x75, 0x4B, 0xA9, 0x50,
+	0x07, 0x8C, 0x69, 0xEF, 0x28, 0x95, 0x5F, 0xB6, 0xD6, 0x6C, 0xFE, 0x95, 0xF8, 0x9F, 0x8C, 0xDC,
+	0x43, 0xC4, 0xB9, 0x1E, 0x17, 0x05, 0x0C, 0xA2, 0xA3, 0x83, 0xAD, 0x29, 0x46, 0x4D, 0x25, 0x7D,
+	0x12, 0x71, 0xB3, 0x7B, 0x3B, 0xB6, 0x7D, 0x67, 0x09, 0xE5, 0x78, 0x5C, 0xCA, 0xBD, 0x4F, 0x6F,
+	0x1B, 0xA8, 0xA4, 0xFE, 0xFB, 0x9F, 0x42, 0x9F, 0xF8, 0x29, 0x47, 0xC4, 0xA1, 0xD6, 0xD3, 0x42,
+	0xFF, 0x00, 0xC0, 0x39, 0x3F, 0xF8, 0xED, 0x09, 0xFF, 0x00, 0x05, 0x28, 0xF8, 0x9D, 0x9C, 0xFF,
+	0x00, 0x67, 0x68, 0x38, 0xF5, 0xFB, 0x1C, 0xBF, 0xFC, 0x76, 0xBE, 0x42, 0xF8, 0x27, 0xFB, 0x2A,
+	0xFC, 0x6F, 0xFD, 0xA3, 0x34, 0x16, 0xF8, 0x8D, 0x77, 0xAF, 0x5C, 0x68, 0xFA, 0x0C, 0x8E, 0xC2,
+	0xCF, 0xC9, 0xC7, 0x99, 0x3A, 0x7E, 0x3F, 0xC3, 0x59, 0x3F, 0x14, 0xFF, 0x00, 0x67, 0xEF, 0x1B,
+	0xFC, 0x25, 0xDD, 0x73, 0xE1, 0xCF, 0x17, 0x5F, 0x47, 0x24, 0x3F, 0x79, 0xA6, 0x63, 0x22, 0xB6,
+	0x0F, 0x7E, 0x80, 0x0F, 0xCE, 0xBE, 0x3F, 0x0B, 0x94, 0x78, 0xAD, 0x5B, 0x02, 0xB1, 0x12, 0xCD,
+	0x2A, 0x26, 0xD6, 0x8B, 0x75, 0xF7, 0xF5, 0xF5, 0x49, 0xAE, 0xD7, 0x3E, 0xA2, 0x58, 0x3E, 0x19,
+	0x8D, 0x67, 0x45, 0xD3, 0x8F, 0x32, 0xFC, 0x0F, 0xB5, 0xA4, 0xFF, 0x00, 0x82, 0x98, 0x7C, 0x4A,
+	0x48, 0xCC, 0xBF, 0xD9, 0x3E, 0x1E, 0xDA, 0xBC, 0x33, 0x1B, 0x39, 0xBF, 0xF8, 0xED, 0x47, 0x6B,
+	0xFF, 0x00, 0x05, 0x2B, 0xF8, 0xB3, 0xAA, 0x4B, 0x24, 0x3A, 0x76, 0x81, 0xE1, 0xF9, 0x4C, 0x6D,
+	0x86, 0x3F, 0x65, 0x98, 0x01, 0xC7, 0xFD, 0x75, 0xAF, 0x83, 0xBC, 0x33, 0xF1, 0x13, 0x51, 0xD7,
+	0xFC, 0x3D, 0x79, 0x7A, 0x57, 0xCB, 0xBC, 0xD3, 0x26, 0x11, 0x6A, 0xD6, 0xE3, 0xA2, 0x86, 0xE9,
+	0x28, 0x1E, 0x84, 0x90, 0x3F, 0x1A, 0xF5, 0x2F, 0xD9, 0x2A, 0xE3, 0xFB, 0x73, 0x56, 0x9A, 0x1D,
+	0x46, 0x08, 0xE4, 0x5F, 0xED, 0x68, 0x90, 0x28, 0xF9, 0x81, 0x05, 0x06, 0x33, 0xF8, 0xF6, 0xEF,
+	0xD2, 0xBE, 0x36, 0xB7, 0x12, 0x78, 0x89, 0x83, 0xC6, 0x7D, 0x56, 0xBE, 0x63, 0x51, 0x49, 0x34,
+	0xB7, 0x56, 0xD5, 0xA4, 0x9E, 0xDB, 0x6A, 0x7B, 0xB9, 0x7F, 0x0C, 0xF0, 0xEE, 0x2B, 0x99, 0xCA,
+	0x9A, 0x69, 0x45, 0xBB, 0x6C, 0xF4, 0x3E, 0xD0, 0xD1, 0x7F, 0x6B, 0x9F, 0xDA, 0x1F, 0xC4, 0x56,
+	0x16, 0xBA, 0xA6, 0x99, 0xA2, 0xF8, 0x51, 0xD6, 0x6B, 0x36, 0x9A, 0x4D, 0xD6, 0xF3, 0xFE, 0xE1,
+	0x81, 0xC0, 0x8C, 0xE2, 0x5F, 0xBE, 0x4E, 0x31, 0xEC, 0x6B, 0x2F, 0xC3, 0x1F, 0xB7, 0x3F, 0xC7,
+	0x8F, 0x15, 0xEA, 0x72, 0xE9, 0x10, 0x68, 0x9E, 0x17, 0xB6, 0x9A, 0x38, 0xD9, 0x82, 0xDC, 0x5A,
+	0x4E, 0x9B, 0x98, 0x1C, 0x6C, 0x19, 0x98, 0xE5, 0x89, 0xE3, 0xB7, 0x5A, 0xF8, 0xDF, 0xE2, 0x27,
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+	0x8C, 0xA5, 0x29, 0xE9, 0x1D, 0xF4, 0x3A, 0xA3, 0x96, 0xE3, 0x24, 0xD2, 0xE5, 0xDC, 0xF4, 0xAA,
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+	0x5A, 0xC7, 0xDA, 0x6E, 0x57, 0xFE, 0x79, 0xDC, 0x57, 0x93, 0xFE, 0xBE, 0xE4, 0xAE, 0x37, 0x8A,
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+	0x7D, 0xA9, 0x45, 0x78, 0xFE, 0x97, 0xF1, 0x1A, 0x4B, 0xC8, 0x57, 0x66, 0xA4, 0xCD, 0x23, 0x2E,
+	0xE6, 0x5F, 0x36, 0xB4, 0x26, 0xF1, 0x46, 0xAB, 0x1D, 0xBF, 0x9D, 0xF6, 0x96, 0xFF, 0x00, 0xBF,
+	0xB5, 0xD4, 0xB8, 0xC7, 0x29, 0x71, 0xBA, 0xBF, 0xEA, 0x72, 0x4B, 0x27, 0xC6, 0x46, 0x56, 0x68,
+	0xF5, 0x0A, 0x2B, 0xC8, 0xF4, 0xFF, 0x00, 0x1F, 0x6A, 0x57, 0xD2, 0x32, 0x7D, 0xA6, 0x45, 0xDA,
+	0xDB, 0x7F, 0xD6, 0xD4, 0x9A, 0xF7, 0x8B, 0xB5, 0xBD, 0x3E, 0xCC, 0xDC, 0xC3, 0x72, 0xDF, 0x77,
+	0x77, 0xCC, 0xD5, 0x8B, 0xE3, 0x8C, 0x99, 0x61, 0x1E, 0x21, 0x73, 0x38, 0xAF, 0x2D, 0x7F, 0x32,
+	0x96, 0x4B, 0x8D, 0x75, 0x14, 0x2C, 0xAE, 0xFC, 0xCF, 0x58, 0xA2, 0xBC, 0x57, 0x47, 0xF8, 0x91,
+	0xAF, 0x5F, 0x40, 0xAE, 0xF7, 0x92, 0x0F, 0xF6, 0x7C, 0xD6, 0xA7, 0xEA, 0xFF, 0x00, 0x10, 0xBC,
+	0x49, 0xA6, 0xC7, 0xE7, 0x25, 0xC4, 0x8C, 0xBF, 0xF5, 0xD5, 0xAB, 0xCD, 0x97, 0x89, 0x9C, 0x3F,
+	0x1C, 0x3F, 0xB6, 0xE5, 0x9D, 0xBD, 0x3F, 0xE0, 0x9B, 0xFF, 0x00, 0xAB, 0xB9, 0x87, 0x3F, 0x2E,
+	0x9F, 0x79, 0xEC, 0xF4, 0x57, 0x8D, 0xE9, 0xFF, 0x00, 0x10, 0xB5, 0xEB, 0xC8, 0xD7, 0x7D, 0xE4,
+	0x81, 0xBF, 0xBB, 0xE6, 0xB5, 0x51, 0xD5, 0xBE, 0x27, 0x78, 0x93, 0x4B, 0xB8, 0x54, 0x9A, 0xEE,
+	0x46, 0x56, 0xF9, 0x7F, 0xD6, 0xB5, 0x4D, 0x7F, 0x13, 0xB8, 0x7B, 0x0F, 0x45, 0x55, 0x6A, 0x4D,
+	0x3B, 0x6C, 0xB6, 0xBF, 0x7D, 0x47, 0x1E, 0x1C, 0xC7, 0xCA, 0x4D, 0x69, 0xF7, 0x9E, 0xE5, 0x45,
+	0x78, 0xB5, 0xBF, 0xC4, 0x2D, 0x7A, 0xE7, 0x6A, 0x25, 0xFC, 0x9B, 0xBE, 0xF7, 0xFA, 0xE6, 0xAC,
+	0xAD, 0x53, 0xE2, 0xD7, 0x89, 0xF4, 0xFD, 0x41, 0x2C, 0xDE, 0xF2, 0x4F, 0x9B, 0xF8, 0xBC, 0xD6,
+	0xAC, 0x71, 0x1E, 0x2A, 0xF0, 0xEE, 0x1A, 0x2A, 0x52, 0x8C, 0xEC, 0xDA, 0x57, 0x49, 0x6E, 0xFE,
+	0x65, 0xC7, 0x86, 0x73, 0x09, 0xBB, 0x2B, 0x7D, 0xE7, 0xBF, 0x51, 0x5E, 0x27, 0x1F, 0xC4, 0x2F,
+	0x10, 0xDC, 0x5B, 0xEF, 0x87, 0x52, 0x91, 0x64, 0xFF, 0x00, 0xAE, 0xAD, 0x58, 0xD1, 0xFC, 0x64,
+	0xF1, 0x22, 0xDE, 0xBD, 0x84, 0x97, 0xF2, 0x6E, 0x8F, 0xF8, 0xBC, 0xD6, 0xAC, 0xF1, 0x1E, 0x2C,
+	0x70, 0xEE, 0x1A, 0x50, 0x53, 0x8C, 0xFD, 0xED, 0x9D, 0x97, 0xF9, 0x95, 0x0E, 0x17, 0xCC, 0x2A,
+	0x5E, 0xCD, 0x68, 0x7D, 0x0B, 0x45, 0x78, 0x3C, 0x3F, 0x12, 0xBC, 0x4F, 0x34, 0x2F, 0x32, 0x6A,
+	0xB3, 0x7C, 0xBF, 0xF4, 0xD5, 0xAB, 0x27, 0x4F, 0xF8, 0xD9, 0xE2, 0x4B, 0xAD, 0x41, 0xED, 0x9F,
+	0x52, 0x99, 0x56, 0x36, 0xDA, 0xCD, 0xE6, 0xB5, 0x73, 0x56, 0xF1, 0x8B, 0x86, 0xA8, 0xCA, 0x11,
+	0x94, 0x27, 0xEF, 0x3D, 0x34, 0x5F, 0xE6, 0x54, 0x78, 0x53, 0x32, 0x95, 0xEC, 0xD6, 0x9E, 0x67,
+	0xD1, 0xD4, 0x57, 0x87, 0xCF, 0xF1, 0x03, 0xC4, 0x33, 0x59, 0xFD, 0xA6, 0xCF, 0x58, 0x93, 0xEE,
+	0xFF, 0x00, 0xCF, 0x56, 0xAC, 0xBB, 0x3F, 0x8A, 0x9E, 0x2C, 0xF3, 0xB6, 0x5E, 0x6A, 0x53, 0x2A,
+	0xFF, 0x00, 0xD7, 0x56, 0xFF, 0x00, 0xE2, 0xAB, 0x7C, 0x47, 0x8B, 0x19, 0x0E, 0x1E, 0xA2, 0x8B,
+	0xA7, 0x36, 0x9F, 0x55, 0xCB, 0x6F, 0xCC, 0x54, 0xF8, 0x5F, 0x30, 0xA9, 0x16, 0xEE, 0xB4, 0xE9,
+	0xD4, 0xFA, 0x12, 0x8A, 0xF1, 0x2B, 0xEF, 0x1E, 0x78, 0x94, 0xD9, 0xFD, 0xA6, 0xCB, 0x59, 0x91,
+	0x9B, 0x6F, 0xDD, 0xF3, 0x5A, 0xAB, 0x59, 0xFC, 0x42, 0xF1, 0x53, 0x46, 0xAF, 0x73, 0xAA, 0xCC,
+	0xBB, 0xBF, 0xE9, 0xAB, 0x55, 0x56, 0xF1, 0x53, 0x24, 0xA3, 0x52, 0xCE, 0x94, 0xED, 0xDF, 0xDD,
+	0xB7, 0xE6, 0x28, 0xF0, 0xCE, 0x3A, 0x51, 0xBF, 0x32, 0xFC, 0x7F, 0xC8, 0xF7, 0x6A, 0x2B, 0xC3,
+	0x75, 0x4F, 0x19, 0x78, 0xCE, 0xD6, 0xC5, 0xAF, 0x21, 0xD5, 0xA6, 0x60, 0xBF, 0xF4, 0xD5, 0xAB,
+	0x8F, 0xBB, 0xF8, 0xF1, 0xE3, 0x3B, 0x7B, 0xB6, 0x87, 0xFB, 0x56, 0x45, 0xDB, 0xFF, 0x00, 0x4D,
+	0x5B, 0xFF, 0x00, 0x8A, 0xAF, 0x2F, 0x30, 0xF1, 0xA3, 0x23, 0xCB, 0x9A, 0xF6, 0x98, 0x5A, 0xAE,
+	0xFD, 0x94, 0x7F, 0xF9, 0x23, 0xA3, 0x0F, 0xC2, 0x38, 0xEC, 0x47, 0xC3, 0x38, 0xFE, 0x3F, 0xE4,
+	0x7D, 0x45, 0x45, 0x7C, 0xA8, 0xDF, 0xB4, 0x17, 0x8D, 0x33, 0xB1, 0xF5, 0x69, 0x95, 0xB7, 0x7F,
+	0xCF, 0x46, 0xA7, 0x37, 0xED, 0x01, 0xE3, 0x4D, 0xBF, 0xF2, 0x18, 0x9B, 0xFD, 0xA6, 0xDC, 0xD5,
+	0xE4, 0xFF, 0x00, 0xC4, 0xC0, 0x70, 0xCB, 0xDB, 0x0B, 0x5B, 0xEE, 0x8F, 0xFF, 0x00, 0x24, 0x75,
+	0xFF, 0x00, 0xA8, 0x79, 0xAF, 0x59, 0xC7, 0xEF, 0x7F, 0xE4, 0x7D, 0x53, 0x45, 0x7C, 0xBB, 0xA3,
+	0x7C, 0x72, 0xF1, 0x9D, 0xF4, 0x9F, 0x3E, 0xB1, 0x33, 0x0D, 0xDB, 0x7F, 0xD6, 0xB5, 0x74, 0xD6,
+	0x3F, 0x15, 0xB5, 0x87, 0xDB, 0x04, 0xDA, 0xC4, 0xCA, 0xCD, 0xFF, 0x00, 0x4D, 0x9A, 0xBD, 0xAC,
+	0xB7, 0xC6, 0x6C, 0x83, 0x30, 0xA7, 0xED, 0x1D, 0x19, 0xC1, 0x3D, 0xB9, 0xB9, 0x55, 0xFF, 0x00,
+	0x13, 0x96, 0xB7, 0x07, 0xE6, 0x14, 0x65, 0x6E, 0x68, 0xBF, 0x4B, 0x9E, 0xF9, 0x45, 0x7C, 0xF3,
+	0xAE, 0xFC, 0x58, 0xF1, 0x56, 0x8F, 0x32, 0x04, 0xD7, 0xAE, 0x19, 0x64, 0xF9, 0x7F, 0xD7, 0xB5,
+	0x25, 0xA7, 0xC5, 0xFF, 0x00, 0x11, 0x4F, 0x32, 0x86, 0xF1, 0x0D, 0xD2, 0xEE, 0xFB, 0xBF, 0xE9,
+	0x0D, 0x5B, 0xFF, 0x00, 0xC4, 0x60, 0xE1, 0xEF, 0x6D, 0xEC, 0xDD, 0x39, 0x27, 0x7B, 0x6B, 0x6F,
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+	0xA2, 0x9D, 0x4D, 0x66, 0xCF, 0x02, 0x98, 0x11, 0xB6, 0xCD, 0xB5, 0x46, 0xEB, 0x52, 0x78, 0x59,
+	0xB6, 0x5B, 0x33, 0x7F, 0xBB, 0x57, 0x99, 0xBE, 0x5D, 0xFB, 0x29, 0xAD, 0xF7, 0x7E, 0xE5, 0x65,
+	0x2E, 0x69, 0x6C, 0xEC, 0x05, 0x15, 0xBB, 0xBC, 0x92, 0x3D, 0xFF, 0x00, 0x62, 0x65, 0xAF, 0x9C,
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+	0xE7, 0x54, 0xB8, 0xF2, 0x96, 0x6F, 0xF9, 0x67, 0x1F, 0xFB, 0xD5, 0xF4, 0xC4, 0xD2, 0x79, 0x76,
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+	0xB2, 0x08, 0xD0, 0xFE, 0xD2, 0x85, 0x4A, 0xCA, 0xF0, 0x8E, 0xAD, 0x77, 0xF2, 0x3E, 0x99, 0x87,
+	0xC7, 0x3F, 0xDB, 0x1A, 0x1C, 0x37, 0x2B, 0xF7, 0xA4, 0x5F, 0x9B, 0x6D, 0x3A, 0x3F, 0x1B, 0x18,
+	0x6C, 0xF6, 0x61, 0x7E, 0x5A, 0xF3, 0xBF, 0x86, 0x7A, 0xD3, 0xFF, 0x00, 0xC2, 0x0B, 0x67, 0xF6,
+	0x97, 0x59, 0x25, 0x68, 0x97, 0xE6, 0xA7, 0xF8, 0x83, 0x5A, 0x99, 0x6E, 0x16, 0x14, 0xFF, 0x00,
+	0x80, 0xED, 0xAF, 0xE7, 0x6C, 0xDB, 0x0B, 0x9C, 0x65, 0x38, 0xA9, 0x3A, 0x95, 0x53, 0x69, 0x24,
+	0xEC, 0x7E, 0xBD, 0x1C, 0x46, 0x5B, 0x5A, 0x8F, 0x3D, 0x28, 0xBB, 0x3D, 0x52, 0x67, 0x51, 0xA9,
+	0x78, 0x82, 0xE6, 0xF0, 0xB4, 0xF1, 0x3E, 0xE5, 0x5F, 0xBD, 0x53, 0xD8, 0xF8, 0xEA, 0x67, 0xB3,
+	0x5B, 0x6B, 0x6B, 0x66, 0x66, 0x5F, 0xFC, 0x7A, 0xB2, 0xD6, 0x37, 0xD3, 0xFC, 0x2E, 0xAF, 0x37,
+	0xDF, 0x91, 0x77, 0x7C, 0xDF, 0xE7, 0xFD, 0xAA, 0xEA, 0x3E, 0x07, 0xF8, 0x5D, 0x35, 0x0D, 0x42,
+	0x37, 0x9A, 0xD9, 0x5F, 0x77, 0xCE, 0xDB, 0xA8, 0xC9, 0x69, 0x63, 0x31, 0x19, 0xAC, 0x30, 0xF4,
+	0x65, 0x69, 0xD4, 0xB5, 0xDF, 0x6B, 0xB3, 0xCD, 0xCC, 0xB1, 0x54, 0xFE, 0xA9, 0x29, 0xCD, 0x69,
+	0x1D, 0x91, 0x1F, 0x85, 0xF4, 0xFD, 0x6F, 0x50, 0xD5, 0x23, 0x9A, 0xE7, 0x4D, 0x93, 0xCB, 0xDD,
+	0xB9, 0x99, 0x97, 0xE5, 0xFF, 0x00, 0xBE, 0xAB, 0xCE, 0x7F, 0xE0, 0xA1, 0x5E, 0x2A, 0xD1, 0xFC,
+	0x35, 0xF0, 0xE5, 0xB4, 0x78, 0x5F, 0xCB, 0x9A, 0x65, 0xDA, 0xAA, 0xBF, 0x2F, 0xCD, 0x5F, 0x58,
+	0xF8, 0x82, 0xC7, 0x4D, 0xD2, 0xEC, 0x7F, 0xD4, 0xAA, 0x2A, 0xAD, 0x7E, 0x6E, 0xFF, 0x00, 0xC1,
+	0x43, 0x3C, 0x71, 0x0E, 0xB5, 0xF1, 0x09, 0x74, 0x44, 0xB9, 0x56, 0x58, 0x7E, 0xF2, 0xEE, 0xFB,
+	0xDF, 0xDD, 0xAF, 0xDC, 0x32, 0x6E, 0x11, 0xA7, 0x93, 0xD4, 0x6A, 0xA4, 0xFD, 0xA4, 0xA4, 0xD3,
+	0xBB, 0x4B, 0x4B, 0x76, 0xDF, 0xF3, 0x3F, 0x3E, 0xCC, 0x38, 0x82, 0x78, 0xAA, 0x7C, 0x94, 0xD7,
+	0x2F, 0x4B, 0x5C, 0xF9, 0xB3, 0x4B, 0xB3, 0x8E, 0x2B, 0xC7, 0x99, 0xD5, 0xB7, 0xC8, 0xDF, 0x7B,
+	0x77, 0xCC, 0xDF, 0xF0, 0x26, 0xAD, 0x58, 0x61, 0x4D, 0xED, 0x37, 0x9D, 0xB5, 0x7E, 0xF7, 0xF9,
+	0xFF, 0x00, 0x66, 0xA8, 0x6E, 0xFB, 0x2C, 0x6B, 0xB3, 0xFD, 0xDD, 0xD5, 0xA1, 0x6F, 0x33, 0xC9,
+	0x0E, 0xFD, 0x9F, 0x2D, 0x7D, 0xD4, 0xB9, 0x76, 0x47, 0xCB, 0x7D, 0xAB, 0x97, 0x95, 0xD1, 0xB6,
+	0xFF, 0x00, 0x79, 0x57, 0xFB, 0xDF, 0xEF, 0x51, 0x6B, 0xB2, 0x46, 0xD8, 0xEE, 0xCD, 0xB5, 0x7F,
+	0x89, 0xBE, 0x5A, 0x8D, 0xA6, 0xDD, 0x1E, 0xC7, 0xFB, 0xB1, 0xAB, 0x7F, 0x7A, 0x88, 0xA6, 0xFD,
+	0xE6, 0xC7, 0x76, 0xDB, 0xB9, 0x77, 0x35, 0x1C, 0xBE, 0xE9, 0x9A, 0x97, 0xBC, 0x71, 0xDE, 0x30,
+	0xF1, 0x34, 0xDE, 0x15, 0xF8, 0x95, 0xE1, 0x97, 0xB0, 0xF9, 0xA4, 0x5D, 0x4A, 0x37, 0x55, 0xDD,
+	0xFD, 0xDF, 0xFF, 0x00, 0x66, 0xBF, 0x4B, 0xFE, 0x03, 0xFE, 0xD4, 0x5A, 0x26, 0xBD, 0x6F, 0x67,
+	0xA2, 0x5F, 0xBE, 0xD9, 0x95, 0x55, 0x36, 0xEE, 0xDC, 0xDF, 0x2A, 0xD7, 0xE5, 0x4F, 0x8A, 0x35,
+	0xA8, 0x75, 0x8F, 0xDA, 0x2B, 0x49, 0xB3, 0x99, 0x19, 0xED, 0x6C, 0x5B, 0x7D, 0xC2, 0xAF, 0xF0,
+	0xFF, 0x00, 0xB5, 0x5E, 0xD9, 0xF0, 0x57, 0xE2, 0x56, 0xA1, 0xAF, 0x7E, 0xD3, 0x91, 0xE9, 0x5E,
+	0x1E, 0xF3, 0x24, 0xB7, 0x8D, 0x57, 0x72, 0xC2, 0xAD, 0xB7, 0xFB, 0xBB, 0x9B, 0xE6, 0xAF, 0x97,
+	0xCF, 0xA3, 0x5E, 0xAC, 0x94, 0xA8, 0xB5, 0x19, 0x6D, 0xDE, 0xFF, 0x00, 0x23, 0xE8, 0x32, 0xB9,
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+	0xA7, 0x81, 0xC4, 0xAB, 0xA5, 0x0D, 0x6D, 0xB7, 0x4F, 0x43, 0x07, 0x5E, 0xF1, 0x06, 0xBD, 0x0F,
+	0xC4, 0x26, 0xF1, 0x0D, 0xFE, 0x95, 0xFB, 0xE5, 0xF9, 0x1E, 0x1F, 0xE2, 0xAD, 0xDD, 0x2B, 0xFB,
+	0x7A, 0xE3, 0xC5, 0x92, 0x78, 0xB3, 0xC3, 0x71, 0x32, 0xCD, 0xE4, 0x6D, 0x96, 0xD5, 0x5B, 0xE5,
+	0xFF, 0x00, 0xD0, 0x69, 0x75, 0x0F, 0x15, 0x69, 0xBA, 0xF7, 0x89, 0xFF, 0x00, 0xB6, 0x0D, 0xB2,
+	0xFF, 0x00, 0x0F, 0xCA, 0xAB, 0x4D, 0xD3, 0xB5, 0x35, 0xF0, 0xFF, 0x00, 0x8F, 0x1B, 0xC7, 0x3A,
+	0x5D, 0xE4, 0xD1, 0xC2, 0xD6, 0xFB, 0x2E, 0x2C, 0xD9, 0x7E, 0x5F, 0xF7, 0xAB, 0x9B, 0x07, 0x8A,
+	0xA6, 0xF1, 0x13, 0x6E, 0xB3, 0x4B, 0x9B, 0x7B, 0x7B, 0xD6, 0xFE, 0x65, 0xFE, 0x47, 0x6D, 0x4C,
+	0x0D, 0x68, 0xD3, 0x5C, 0x90, 0xD5, 0xAD, 0x57, 0x4B, 0xF6, 0x39, 0x5B, 0x8D, 0x7B, 0xC4, 0x36,
+	0x9F, 0x10, 0x64, 0xF1, 0x25, 0xDE, 0x8E, 0xDF, 0x68, 0x69, 0x36, 0xB4, 0x3B, 0x6B, 0xA8, 0xF0,
+	0xFF, 0x00, 0xFC, 0x24, 0xF0, 0xF8, 0x9A, 0xEB, 0xC5, 0x5E, 0x18, 0xB3, 0x91, 0xA4, 0x9A, 0xDD,
+	0x7C, 0xDB, 0x5F, 0xE1, 0xFF, 0x00, 0xD0, 0x69, 0x97, 0x9E, 0x2E, 0xB1, 0xD7, 0x3C, 0x54, 0x75,
+	0xEF, 0xB1, 0xAE, 0xD6, 0x6D, 0xCC, 0xAA, 0xB4, 0xCD, 0x0F, 0x54, 0x7F, 0x0A, 0xFC, 0x44, 0xB8,
+	0xF1, 0xAE, 0x8F, 0xA8, 0xCC, 0xD6, 0xF7, 0x16, 0xEA, 0x92, 0xD8, 0xB2, 0xFE, 0xED, 0x5B, 0xFB,
+	0xCB, 0xF2, 0xD5, 0xE0, 0x31, 0x38, 0x5A, 0x75, 0xA5, 0x2A, 0xB8, 0x87, 0x18, 0xF3, 0xBD, 0x6C,
+	0xD4, 0xAC, 0xFE, 0xD2, 0xB8, 0xEB, 0x65, 0xD5, 0xD5, 0x35, 0xC9, 0x4E, 0xED, 0xAD, 0x6E, 0xF4,
+	0xBF, 0x63, 0x99, 0xD2, 0xF5, 0x8F, 0x10, 0xE9, 0x7E, 0x3C, 0xBA, 0xF1, 0x55, 0xCE, 0x8E, 0xDF,
+	0x69, 0x9A, 0x56, 0xF3, 0x61, 0xDB, 0xF3, 0x2B, 0x56, 0xC7, 0x88, 0x7E, 0x12, 0xFC, 0x4B, 0xF8,
+	0xED, 0xE2, 0x5F, 0x85, 0xDE, 0x2D, 0xF0, 0x36, 0x8B, 0x0C, 0x8D, 0xE0, 0xBF, 0x8D, 0xDA, 0x7F,
+	0x88, 0x35, 0xC5, 0x92, 0xE1, 0x62, 0x6B, 0x7D, 0x35, 0x6C, 0x6F, 0x21, 0x9D, 0xBE, 0x6F, 0xBD,
+	0xFE, 0xB5, 0x7E, 0x55, 0xF9, 0x9B, 0x75, 0x69, 0xB7, 0x8A, 0x61, 0x7F, 0x14, 0x4B, 0xE2, 0x1B,
+	0x9D, 0x2B, 0x0B, 0x23, 0x7D, 0xDD, 0xB5, 0xE4, 0xBF, 0xB6, 0x1F, 0xFC, 0x14, 0xC7, 0x56, 0xFF,
+	0x00, 0x82, 0x71, 0x69, 0x1E, 0x18, 0xF8, 0x91, 0x69, 0xF0, 0x92, 0xE3, 0x5C, 0xD1, 0x3C, 0x51,
+	0xE2, 0xD8, 0xEC, 0x3C, 0x43, 0x78, 0xBB, 0xB6, 0xE9, 0x76, 0x2A, 0xBE, 0x64, 0xF2, 0x2A, 0xAB,
+	0x7E, 0xF2, 0x6F, 0x27, 0xCC, 0x65, 0x5F, 0xBB, 0xFB, 0xB6, 0xDD, 0x5F, 0x61, 0xE1, 0x76, 0x2E,
+	0x8C, 0xB8, 0xA2, 0x14, 0x63, 0x51, 0xC9, 0x37, 0x3D, 0x12, 0xD5, 0xAE, 0x56, 0xD4, 0xBE, 0x7F,
+	0xF0, 0x7A, 0x1E, 0x17, 0x16, 0x65, 0xD2, 0xA7, 0x93, 0x4E, 0x7C, 0xB6, 0xB2, 0x5F, 0x7B, 0x69,
+	0x34, 0xBE, 0x4C, 0xFB, 0x96, 0x48, 0xE6, 0x5F, 0x92, 0x68, 0xF6, 0x32, 0xB7, 0xF7, 0xB7, 0x53,
+	0x61, 0x54, 0x5A, 0xF8, 0x96, 0xE3, 0xFE, 0x0B, 0xE5, 0xFB, 0x0A, 0xF8, 0x9A, 0xF2, 0xCF, 0x5B,
+	0xF0, 0x1F, 0x8F, 0x35, 0x2D, 0x53, 0x46, 0x99, 0x72, 0xD3, 0x47, 0xE1, 0x99, 0x3C, 0xC9, 0x3F,
+	0xDD, 0x6F, 0x33, 0xE5, 0xFF, 0x00, 0x75, 0x97, 0xEF, 0x56, 0x94, 0x7F, 0xF0, 0x5D, 0x0F, 0xD8,
+	0x91, 0x55, 0xDF, 0xFE, 0x2A, 0xC6, 0x55, 0x6D, 0xBB, 0x97, 0xC3, 0xCD, 0xFF, 0x00, 0xC5, 0x57,
+	0xF4, 0xF4, 0xAB, 0x53, 0xE6, 0x69, 0xDD, 0x7A, 0xA6, 0x7E, 0x6B, 0x18, 0xCA, 0x49, 0x1F, 0x67,
+	0x4D, 0x0F, 0xDB, 0x23, 0x44, 0x79, 0x99, 0x15, 0x5B, 0x3F, 0x2F, 0xF1, 0x51, 0x6B, 0x6D, 0x1D,
+	0x8F, 0xCF, 0xE7, 0x34, 0x9F, 0xED, 0x32, 0xFC, 0xDF, 0xF7, 0xD5, 0x7C, 0x6E, 0xBF, 0xF0, 0x5D,
+	0x2F, 0xD8, 0xC1, 0xA2, 0xF3, 0xA1, 0xD2, 0xBC, 0x60, 0xEB, 0xFD, 0xEF, 0xEC, 0x1D, 0xBF, 0xFB,
+	0x35, 0x45, 0x75, 0xFF, 0x00, 0x05, 0xD3, 0xFD, 0x8C, 0xED, 0xF7, 0x79, 0xD6, 0x7E, 0x28, 0x87,
+	0x6A, 0xEE, 0xFF, 0x00, 0x48, 0xD2, 0xE3, 0x8F, 0xFF, 0x00, 0x42, 0x92, 0xB2, 0xF6, 0xD8, 0x59,
+	0x54, 0xE6, 0xEB, 0xE8, 0xFF, 0x00, 0x2D, 0x8B, 0xF6, 0x55, 0xB6, 0xB1, 0xF6, 0x94, 0xCC, 0x97,
+	0x50, 0xBD, 0xB4, 0xCF, 0xB5, 0x24, 0x5D, 0xBF, 0x2D, 0x66, 0x7F, 0x66, 0xCD, 0x1C, 0x8D, 0x34,
+	0xC9, 0xE6, 0x6E, 0xF9, 0x55, 0xA3, 0xFF, 0x00, 0xE2, 0x6B, 0xE7, 0x9F, 0x0E, 0xFF, 0x00, 0xC1,
+	0x4B, 0xBC, 0x0D, 0xE3, 0x0D, 0x0E, 0xCF, 0xC4, 0x9E, 0x11, 0xFD, 0x9E, 0xFE, 0x2A, 0x6A, 0xB6,
+	0x1A, 0x85, 0xAA, 0xCF, 0x67, 0x7D, 0xA7, 0xF8, 0x36, 0x49, 0x62, 0xB8, 0x8D, 0x97, 0x72, 0xB4,
+	0x72, 0x2B, 0x6D, 0x65, 0x65, 0xDB, 0xF3, 0x2D, 0x6A, 0xF8, 0x8B, 0xF6, 0xEE, 0xFF, 0x00, 0x84,
+	0x6A, 0xEA, 0x3B, 0x3D, 0x63, 0xF6, 0x59, 0xF8, 0xA8, 0xAF, 0x24, 0x5B, 0xD7, 0xC9, 0xF0, 0xCF,
+	0x9E, 0xAA, 0xBF, 0xC4, 0xCC, 0xD1, 0xB3, 0x2A, 0xED, 0xF9, 0x77, 0x6E, 0xA5, 0x57, 0xEA, 0xF8,
+	0x8D, 0x5D, 0xFD, 0x6C, 0xFF, 0x00, 0xC8, 0x71, 0x84, 0xA3, 0xB1, 0xEE, 0x72, 0x5A, 0xDF, 0xDD,
+	0x2A, 0x42, 0xE8, 0xAB, 0xE5, 0xCB, 0xBB, 0xCC, 0x5F, 0xEE, 0xD6, 0x96, 0xDF, 0xDD, 0xFF, 0x00,
+	0x79, 0xB6, 0xFD, 0xEA, 0xF9, 0xD6, 0x3F, 0xF8, 0x28, 0x2E, 0xE8, 0xBE, 0xD3, 0xFF, 0x00, 0x0C,
+	0x9D, 0xF1, 0x7B, 0xEC, 0xFF, 0x00, 0x7B, 0xCE, 0x6F, 0x05, 0x4C, 0xAB, 0xF7, 0x7F, 0xBD, 0xFC,
+	0x3F, 0xFD, 0x95, 0x4D, 0x67, 0xFB, 0x7F, 0x5C, 0xDD, 0x5A, 0xC7, 0x79, 0x6D, 0xFB, 0x22, 0xFC,
+	0x5E, 0x92, 0x19, 0x17, 0x72, 0xCD, 0x0F, 0x82, 0xEE, 0x24, 0x5F, 0xFB, 0xE9, 0x57, 0xFC, 0xFF,
+	0x00, 0xC0, 0x6A, 0xA8, 0xFB, 0x1A, 0x72, 0x6E, 0xED, 0xB7, 0xE4, 0xDE, 0xDB, 0x6C, 0x83, 0xD9,
+	0x4D, 0xEC, 0xBF, 0x23, 0xDA, 0x2E, 0xAC, 0x25, 0x58, 0xDA, 0x69, 0x93, 0xEE, 0xFC, 0xCC, 0xDE,
+	0x56, 0xD5, 0xDB, 0xFF, 0x00, 0x7C, 0xD4, 0xDA, 0x5D, 0xC3, 0xC9, 0x0B, 0x26, 0xFD, 0xDB, 0x7E,
+	0x5F, 0xF5, 0x5B, 0x6B, 0xC2, 0xA4, 0xFF, 0x00, 0x82, 0x80, 0xEB, 0x0D, 0x1E, 0xF4, 0xFD, 0x8B,
+	0x7E, 0x32, 0x36, 0xEF, 0xE1, 0x6F, 0x05, 0xDC, 0x2B, 0x7F, 0xDF, 0x3B, 0x6A, 0xB5, 0xD7, 0xFC,
+	0x14, 0x0B, 0x5B, 0xB5, 0x91, 0xA1, 0x4F, 0xD8, 0x93, 0xE3, 0x33, 0x36, 0xED, 0xBF, 0x2F, 0x81,
+	0x6E, 0xB6, 0xFF, 0x00, 0xBD, 0xF7, 0x6B, 0x3A, 0x74, 0xE1, 0x4E, 0xA7, 0x34, 0x6F, 0xF7, 0x4B,
+	0xFA, 0xFC, 0xC6, 0xE9, 0xD4, 0xB5, 0x9A, 0xFC, 0x51, 0xF4, 0x37, 0x99, 0xEB, 0xF2, 0xD1, 0x25,
+	0xC2, 0x7F, 0x7E, 0xBE, 0x75, 0xFF, 0x00, 0x86, 0xFA, 0xF1, 0x05, 0xC3, 0x6C, 0x87, 0xF6, 0x30,
+	0xF8, 0xC4, 0xBF, 0xF4, 0xD2, 0x4F, 0x04, 0x5C, 0x2A, 0xFF, 0x00, 0xE3, 0xCA, 0xB5, 0xE2, 0xBF,
+	0x11, 0x3F, 0xE0, 0xB0, 0x1F, 0xB4, 0x3F, 0x87, 0x7C, 0x6D, 0x7F, 0xE1, 0xEF, 0x03, 0xFF, 0x00,
+	0xC1, 0x1D, 0xBF, 0x68, 0x2F, 0x12, 0x69, 0x76, 0xB7, 0x1E, 0x55, 0xAE, 0xB9, 0xFF, 0x00, 0x08,
+	0xCD, 0xE5, 0x9F, 0xDB, 0x15, 0x7E, 0xF4, 0x8B, 0x17, 0xD8, 0xE4, 0xDA, 0xBB, 0xBE, 0xEE, 0xE6,
+	0xF9, 0x97, 0xE6, 0xF9, 0x7E, 0xED, 0x75, 0xC7, 0x9E, 0x5F, 0x0A, 0x7F, 0x73, 0xFF, 0x00, 0x22,
+	0x25, 0x4E, 0x51, 0x57, 0x92, 0xFB, 0xB5, 0x3E, 0xEA, 0x9E, 0x67, 0x6F, 0xEE, 0xB7, 0xFB, 0xB5,
+	0x4A, 0xE2, 0x67, 0x40, 0xD5, 0xF0, 0x34, 0x7F, 0xF0, 0x58, 0xCF, 0xDA, 0xB9, 0xB6, 0xBF, 0xFC,
+	0x39, 0x4B, 0xF6, 0x82, 0x46, 0xDD, 0xF3, 0x2A, 0xE9, 0xB7, 0x0C, 0xBF, 0xFA, 0x43, 0x53, 0x2F,
+	0xFC, 0x16, 0x1B, 0xF6, 0xA2, 0x79, 0x36, 0x5D, 0x7F, 0xC1, 0x16, 0x3F, 0x68, 0x45, 0xF9, 0x7E,
+	0x6D, 0xBA, 0x34, 0xDF, 0xFC, 0x87, 0x44, 0xA9, 0xD5, 0x94, 0x75, 0x8B, 0xFB, 0x83, 0x95, 0xF2,
+	0xDD, 0x27, 0xF7, 0x1F, 0x76, 0x33, 0xFD, 0xED, 0x9B, 0xA9, 0x8B, 0xF7, 0x96, 0xBE, 0x18, 0xFF,
+	0x00, 0x87, 0xBE, 0x7E, 0xD3, 0x2A, 0xCD, 0xE7, 0x7F, 0xC1, 0x19, 0xFF, 0x00, 0x68, 0x2D, 0xBF,
+	0x7B, 0x6F, 0xF6, 0x4C, 0xDF, 0xFC, 0x8B, 0x53, 0xE9, 0xDF, 0xF0, 0x57, 0x0F, 0xDA, 0x4E, 0xF9,
+	0x9B, 0xC9, 0xFF, 0x00, 0x82, 0x36, 0xFE, 0xD0, 0x0B, 0xB5, 0x7E, 0x66, 0x93, 0x49, 0x68, 0xF7,
+	0x7F, 0xBB, 0xE6, 0x5B, 0xAE, 0xEA, 0x71, 0xA7, 0x53, 0x7E, 0x57, 0xF7, 0x30, 0x77, 0xDC, 0xFB,
+	0x8E, 0xDF, 0xEE, 0xFC, 0xEF, 0xFF, 0x00, 0x01, 0x6A, 0xF3, 0x9F, 0xD9, 0xE6, 0xE2, 0x4F, 0x04,
+	0xFF, 0x00, 0xC1, 0x47, 0x3C, 0x49, 0xA2, 0x6F, 0xD9, 0x6B, 0xE3, 0x6F, 0x87, 0x4B, 0x75, 0x1C,
+	0x7F, 0xDE, 0xB8, 0xD3, 0xEE, 0xA3, 0x56, 0x6F, 0xFB, 0xE6, 0xFF, 0x00, 0xFF, 0x00, 0x42, 0xAF,
+	0x9A, 0xED, 0xFF, 0x00, 0xE0, 0xAD, 0x1F, 0xB4, 0x6C, 0x91, 0xB7, 0xFC, 0x69, 0xE7, 0xF6, 0x80,
+	0x4F, 0xEE, 0xFF, 0x00, 0xC4, 0x8E, 0x46, 0xFF, 0x00, 0xDB, 0x7A, 0xD4, 0xFD, 0x9A, 0xBF, 0x6A,
+	0xAF, 0x8D, 0x3F, 0x1E, 0xFF, 0x00, 0x6F, 0x7F, 0x86, 0xBE, 0x39, 0xF1, 0x6F, 0xEC, 0x27, 0xF1,
+	0x43, 0xE1, 0x9E, 0x97, 0xA5, 0xE9, 0xFA, 0xB5, 0xAE, 0xB1, 0xAF, 0xF8, 0xC3, 0x4F, 0x68, 0xAC,
+	0xD6, 0xDE, 0x6B, 0x36, 0xDA, 0xAC, 0xFE, 0x5A, 0xED, 0x66, 0x9B, 0xC9, 0xFF, 0x00, 0xBF, 0x35,
+	0xDF, 0x85, 0xBD, 0x3A, 0x8A, 0xE9, 0xAD, 0x56, 0xE9, 0xF7, 0x5E, 0x47, 0x1E, 0x2A, 0x9C, 0xA5,
+	0x49, 0xB6, 0x7E, 0xA0, 0x51, 0x59, 0x77, 0xBE, 0x29, 0xD0, 0x6C, 0x74, 0xB5, 0xD6, 0x1F, 0x52,
+	0x85, 0xED, 0xE4, 0x2A, 0x21, 0x92, 0x19, 0x15, 0xBC, 0xD6, 0xFE, 0xEA, 0xFF, 0x00, 0x78, 0xD6,
+	0x85, 0xBC, 0xC9, 0x75, 0x02, 0x5C, 0x44, 0x7E, 0x47, 0x55, 0x65, 0xAF, 0xA4, 0xBA, 0x67, 0x92,
+	0x49, 0x45, 0x14, 0x53, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0xCF,
+	0xF1, 0x1E, 0xBF, 0xA7, 0xF8, 0x67, 0xC3, 0xF7, 0x9E, 0x24, 0xD5, 0x26, 0x58, 0xED, 0xAC, 0x6D,
+	0x5A, 0x69, 0xD9, 0xBB, 0x2A, 0xAE, 0x6A, 0x65, 0x25, 0x15, 0x76, 0x05, 0x14, 0xF8, 0x91, 0xE0,
+	0x59, 0xBC, 0x5F, 0x37, 0xC3, 0xF8, 0x3C, 0x59, 0x62, 0xDA, 0xDC, 0x36, 0xFE, 0x7C, 0xBA, 0x52,
+	0xDC, 0x2F, 0x9E, 0xB1, 0xFF, 0x00, 0x7B, 0x6D, 0x54, 0xD4, 0xFC, 0x5D, 0x7B, 0x6B, 0x76, 0xF6,
+	0xF8, 0xF2, 0xD9, 0x7F, 0xE5, 0x9E, 0xDA, 0xF9, 0x7B, 0xFE, 0x09, 0xA9, 0x0E, 0xAB, 0xF1, 0xB3,
+	0xE2, 0x0F, 0xC4, 0x2F, 0xDB, 0x3B, 0xC4, 0x89, 0xBE, 0x1F, 0x12, 0x6B, 0x0D, 0xA7, 0x78, 0x65,
+	0x9B, 0xF8, 0x6C, 0x6D, 0xDB, 0x6B, 0x32, 0xFF, 0x00, 0xB2, 0xD2, 0x6E, 0xFF, 0x00, 0xBF, 0x75,
+	0xF4, 0x26, 0xB9, 0x76, 0x97, 0x7A, 0xE4, 0xF3, 0x4D, 0xB7, 0xEF, 0x7C, 0xAB, 0x58, 0xE2, 0xA5,
+	0x52, 0x84, 0x62, 0x9E, 0xEF, 0x56, 0xBB, 0x75, 0xB7, 0xCB, 0x44, 0xFC, 0xCC, 0xF0, 0x75, 0x3E,
+	0xB5, 0x4F, 0xDA, 0x74, 0x77, 0xB7, 0xA5, 0xEC, 0x9F, 0xCE, 0xD7, 0x5E, 0x56, 0x37, 0x2D, 0xFC,
+	0x5F, 0xA9, 0x32, 0xAE, 0xF6, 0x5F, 0xFB, 0xE2, 0x8D, 0x47, 0x55, 0x6D, 0x56, 0xD7, 0xFD, 0x2E,
+	0x35, 0x31, 0xC2, 0xDB, 0xDA, 0xB9, 0xF8, 0xEE, 0x37, 0x42, 0xD2, 0x79, 0x8A, 0x15, 0x6A, 0x65,
+	0xD6, 0xB4, 0xD8, 0xEC, 0x5A, 0xC2, 0xFE, 0xE6, 0xDD, 0x91, 0x9B, 0x73, 0x2B, 0x35, 0x73, 0xBA,
+	0xF1, 0x94, 0x6C, 0xCE, 0x87, 0x09, 0x44, 0xD6, 0x4F, 0x1E, 0x68, 0x96, 0xB1, 0xAA, 0x4D, 0x7F,
+	0x0A, 0x2A, 0xFC, 0xBF, 0x34, 0xAB, 0x57, 0xB4, 0xBF, 0x1B, 0x69, 0x5A, 0xB3, 0x7F, 0xA0, 0x5E,
+	0x43, 0x32, 0xFF, 0x00, 0xD3, 0x39, 0x95, 0xAB, 0x8B, 0xBC, 0x87, 0xE1, 0x75, 0xF2, 0xAF, 0xDB,
+	0xE1, 0xD3, 0x59, 0x7F, 0xDE, 0x5A, 0xD4, 0xF0, 0x7E, 0x93, 0xE0, 0x9B, 0x79, 0x1A, 0xE7, 0xC2,
+	0xB6, 0x76, 0xA8, 0xBF, 0x75, 0xBE, 0xCE, 0xB4, 0x53, 0xAD, 0x55, 0xCD, 0x2B, 0xAB, 0x79, 0x5E,
+	0xE6, 0x6F, 0x73, 0xB4, 0x87, 0x50, 0x79, 0x7A, 0x25, 0x5B, 0x56, 0xDD, 0xDA, 0xB3, 0xAC, 0xD0,
+	0xED, 0xE2, 0xAF, 0x42, 0xDB, 0xB9, 0xAE, 0xE8, 0x81, 0x25, 0x14, 0x51, 0x54, 0x07, 0x09, 0xF1,
+	0xA7, 0xE2, 0x86, 0xB7, 0xF0, 0x83, 0xC3, 0x77, 0x1E, 0x38, 0xB7, 0xF0, 0x26, 0xA1, 0xAF, 0x69,
+	0xB6, 0x76, 0xED, 0x2D, 0xF4, 0x3A, 0x4E, 0xD3, 0x73, 0x1A, 0xAF, 0xF1, 0x2A, 0x37, 0xFA, 0xCA,
+	0xF2, 0x4F, 0xD9, 0x1B, 0xFE, 0x0A, 0x6D, 0xF0, 0x33, 0xF6, 0xC4, 0xF8, 0x81, 0x7D, 0xF0, 0xDB,
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+	0x7A, 0xDF, 0xF4, 0x3D, 0xDB, 0xC2, 0xDA, 0xDD, 0xD6, 0xBF, 0xE1, 0xFD, 0x3F, 0x57, 0xBD, 0xD1,
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+	0x58, 0xFE, 0xCB, 0xBF, 0xB5, 0x87, 0xC4, 0x96, 0xF8, 0xA9, 0xF1, 0x5E, 0xFF, 0x00, 0xC7, 0xC9,
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+	0x18, 0xFF, 0x00, 0xC1, 0x35, 0xAC, 0x63, 0x58, 0xEF, 0xFE, 0x09, 0xEB, 0x1A, 0xA3, 0x7F, 0x14,
+	0x9A, 0xA7, 0xC4, 0x1D, 0x6A, 0x76, 0x6F, 0xF7, 0xB7, 0x5E, 0x57, 0xAB, 0x7E, 0xD8, 0xDF, 0xB6,
+	0x17, 0x88, 0x7F, 0x64, 0xDD, 0x1F, 0x4D, 0xD6, 0xF4, 0x7F, 0xD9, 0x5F, 0xE2, 0x37, 0xC4, 0xBB,
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+	0xA6, 0x56, 0xDA, 0xDF, 0xEC, 0xAB, 0x7D, 0xDA, 0xF9, 0x96, 0xEB, 0xFE, 0x0E, 0x17, 0xFD, 0x9A,
+	0x74, 0x16, 0xD9, 0xF1, 0x23, 0xF6, 0x5A, 0xF8, 0xF9, 0xE1, 0x76, 0xFF, 0x00, 0x96, 0xBF, 0xDB,
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+	0xCF, 0x5A, 0xB2, 0xFF, 0x00, 0x82, 0x3C, 0xFF, 0x00, 0xC1, 0x31, 0xF4, 0x66, 0xFD, 0xCF, 0xEC,
+	0x5B, 0xE0, 0xFB, 0x96, 0xFF, 0x00, 0xA8, 0x94, 0x53, 0x5D, 0x2F, 0xFE, 0x46, 0x91, 0xAB, 0xAF,
+	0xF0, 0x4F, 0xEC, 0x03, 0xFB, 0x0F, 0x7C, 0x31, 0xBE, 0xFE, 0xD5, 0xF8, 0x7B, 0xFB, 0x24, 0x7C,
+	0x39, 0xD1, 0x6E, 0x55, 0x59, 0x3E, 0xD5, 0x63, 0xE0, 0xFB, 0x35, 0x97, 0x6B, 0x2E, 0xD6, 0x5F,
+	0x33, 0xCB, 0xDD, 0xF3, 0x57, 0xCF, 0x56, 0x7F, 0xF0, 0x71, 0xB7, 0xFC, 0x12, 0xEE, 0xF1, 0xF6,
+	0x6B, 0x1F, 0x12, 0xFC, 0x49, 0xA4, 0xBF, 0xF1, 0x47, 0xAA, 0x78, 0x36, 0xF2, 0x36, 0x5F, 0xFB,
+	0xE5, 0x5A, 0xBA, 0x8F, 0x0C, 0xFF, 0x00, 0xC1, 0x76, 0x3F, 0xE0, 0x95, 0x1E, 0x2C, 0x91, 0x52,
+	0xCF, 0xF6, 0xBD, 0xD1, 0x6D, 0x99, 0xBF, 0x87, 0x52, 0xB0, 0xBC, 0xB6, 0xFF, 0x00, 0xD1, 0x90,
+	0xAD, 0x73, 0x4B, 0xEB, 0x10, 0xF7, 0x6A, 0xC6, 0x7F, 0x35, 0x2F, 0xF2, 0x09, 0xFD, 0x62, 0x5F,
+	0x69, 0xEB, 0xE6, 0xDF, 0xEA, 0x7D, 0x5D, 0xA9, 0x68, 0xF6, 0x1A, 0xD5, 0x83, 0xE9, 0xBA, 0xDC,
+	0x2B, 0x7D, 0x6D, 0x23, 0xAB, 0xB5, 0xBD, 0xE2, 0xF9, 0xB1, 0xB3, 0x2F, 0xDD, 0x6D, 0xAD, 0xFC,
+	0x54, 0xCD, 0x2F, 0xC3, 0x7E, 0x1A, 0xD2, 0xE6, 0x4F, 0xB0, 0x68, 0x16, 0x76, 0xFB, 0x7F, 0x8A,
+	0x1B, 0x75, 0x5A, 0xF1, 0xCF, 0x09, 0xFF, 0x00, 0xC1, 0x4A, 0x3F, 0x60, 0xCF, 0x1C, 0x5B, 0xA5,
+	0xC7, 0x86, 0x3F, 0x6A, 0xEF, 0x04, 0xDD, 0x47, 0x23, 0xAA, 0xAB, 0x7F, 0x6E, 0x47, 0x1E, 0xE6,
+	0x6F, 0xE1, 0xDA, 0xDB, 0x6B, 0xAD, 0xD2, 0x7F, 0x6B, 0x2F, 0xD9, 0x8F, 0x56, 0xB8, 0xD9, 0x61,
+	0xFB, 0x42, 0x78, 0x36, 0x46, 0x8D, 0x77, 0xB2, 0xAF, 0x88, 0xED, 0xF7, 0x2A, 0xFF, 0x00, 0xDF,
+	0x55, 0xE9, 0x61, 0x71, 0xB8, 0x4D, 0x22, 0xE4, 0x93, 0xF3, 0xD0, 0xF1, 0xB1, 0x38, 0x5C, 0x65,
+	0xFE, 0x16, 0xD7, 0xA3, 0xFF, 0x00, 0x23, 0xDA, 0x7C, 0x1D, 0xE4, 0xC7, 0x70, 0xD1, 0x3E, 0xDD,
+	0xB2, 0x7C, 0x8D, 0xFE, 0xEB, 0x56, 0x67, 0xEC, 0xF0, 0xE3, 0x4C, 0xD1, 0x7F, 0xE1, 0x1A, 0x57,
+	0x6F, 0x2F, 0x4F, 0x59, 0x2C, 0x95, 0x5B, 0xF8, 0x5A, 0xDE, 0x66, 0x87, 0x6D, 0x54, 0xF8, 0x7B,
+	0xE3, 0xEF, 0x06, 0x78, 0x93, 0x51, 0x86, 0x1F, 0x0D, 0xF8, 0xB7, 0x4D, 0xBF, 0xF3, 0xB6, 0xB4,
+	0x6B, 0x67, 0x7F, 0x1C, 0xBB, 0xBF, 0xEF, 0x96, 0xAB, 0x1E, 0x14, 0x57, 0xD0, 0xFE, 0x32, 0x6B,
+	0xBA, 0x6F, 0x9C, 0x7C, 0x99, 0x2F, 0xD6, 0xE6, 0x24, 0x09, 0xB4, 0x05, 0xB8, 0x85, 0x77, 0x7F,
+	0xBD, 0xFB, 0xE5, 0x66, 0xDD, 0x57, 0x0A, 0x8A, 0x55, 0x94, 0xA2, 0xEF, 0x69, 0x5B, 0x47, 0x7D,
+	0xD7, 0xF9, 0xA4, 0x69, 0xCB, 0x28, 0xE1, 0xDC, 0x5A, 0xB6, 0x89, 0xD9, 0xE9, 0xB3, 0xB7, 0xEA,
+	0x7A, 0x85, 0x14, 0x51, 0x5E, 0xA1, 0xC6, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x79,
+	0x7F, 0xED, 0x8B, 0xF1, 0xD3, 0x48, 0xFD, 0x9B, 0xBF, 0x66, 0xFF, 0x00, 0x16, 0x7C, 0x5F, 0xD5,
+	0x5D, 0x7F, 0xE2, 0x53, 0xA4, 0xCC, 0xF6, 0xEB, 0xBB, 0x1E, 0x64, 0xDB, 0x7E, 0x55, 0xAF, 0x03,
+	0xFF, 0x00, 0x82, 0x33, 0xFC, 0x21, 0xD6, 0x7C, 0x0B, 0xFB, 0x25, 0x37, 0xC6, 0xFF, 0x00, 0x1E,
+	0xC2, 0xDF, 0xF0, 0x93, 0xFC, 0x4E, 0xD5, 0x2E, 0x3C, 0x49, 0xA9, 0x4B, 0x32, 0xED, 0x65, 0x86,
+	0x66, 0x6F, 0xB3, 0x2F, 0xFD, 0xF9, 0xDB, 0x27, 0xFD, 0xB6, 0x6A, 0xF3, 0x9F, 0xF8, 0x2C, 0x97,
+	0x8A, 0xB5, 0x8F, 0xDA, 0x07, 0xE2, 0xE7, 0xC2, 0xDF, 0xF8, 0x27, 0x4F, 0x82, 0xAF, 0xE4, 0x49,
+	0xBC, 0x6F, 0xAF, 0x43, 0x73, 0xE2, 0x66, 0xB7, 0xCF, 0x99, 0x0E, 0x9B, 0x1B, 0x6E, 0x95, 0xB8,
+	0xFF, 0x00, 0xA6, 0x6B, 0x23, 0x7C, 0xDF, 0xF3, 0xCE, 0xBE, 0xE1, 0xB9, 0xD0, 0xF4, 0xEF, 0x0E,
+	0x78, 0x0A, 0xD7, 0xC0, 0x5E, 0x1D, 0xB6, 0x86, 0xC6, 0xDE, 0xD6, 0xCE, 0x1B, 0x5B, 0x7B, 0x58,
+	0xBE, 0x55, 0x86, 0xDD, 0x40, 0x5D, 0x8B, 0xF4, 0x55, 0xDB, 0x44, 0x7D, 0xCC, 0x2C, 0xEA, 0xF5,
+	0x9B, 0xE5, 0x5F, 0xE1, 0x8D, 0xAF, 0xF7, 0xCA, 0xCB, 0x4B, 0xFC, 0x0C, 0xE0, 0xF7, 0xAB, 0x63,
+	0x9F, 0x6A, 0x6B, 0xEF, 0x93, 0xFF, 0x00, 0x25, 0xDF, 0xB9, 0xC9, 0xDA, 0xFC, 0x50, 0xF0, 0xDD,
+	0xD1, 0x92, 0xE6, 0x14, 0xBE, 0x92, 0x3F, 0x35, 0x97, 0xED, 0x0B, 0x66, 0xDB, 0x64, 0x6F, 0xF6,
+	0x69, 0xF7, 0x1F, 0x11, 0xB4, 0xAF, 0x2F, 0x74, 0x3A, 0x16, 0xB0, 0xFF, 0x00, 0x2E, 0xEF, 0xDD,
+	0xE9, 0xB2, 0x7D, 0xDA, 0xE3, 0x7F, 0x68, 0xAF, 0x0E, 0xFC, 0x66, 0xF1, 0x5C, 0x9E, 0x1C, 0xF0,
+	0xC7, 0xC1, 0xFD, 0xB6, 0x16, 0xB0, 0xEB, 0x76, 0xF3, 0xEB, 0x9A, 0x92, 0xDC, 0x2C, 0x6C, 0xB6,
+	0xAB, 0xF7, 0xA3, 0x55, 0xFF, 0x00, 0x6B, 0xEE, 0xD7, 0xA0, 0x5D, 0x6A, 0xDA, 0xF7, 0x87, 0xEC,
+	0x5E, 0xCF, 0x4D, 0xF0, 0xC4, 0xDA, 0xA3, 0xAC, 0x71, 0xAF, 0x9D, 0xF6, 0xA8, 0xE3, 0xDD, 0xB5,
+	0x7F, 0xDA, 0xAF, 0x26, 0x56, 0x8D, 0x36, 0xD4, 0xF5, 0x4E, 0xDF, 0x0B, 0x7D, 0x13, 0xBE, 0x9F,
+	0xD6, 0x87, 0x7C, 0x65, 0x55, 0xCA, 0xD2, 0x5A, 0x77, 0xEF, 0xFD, 0x69, 0xF7, 0x99, 0x3F, 0xF0,
+	0xB0, 0xAF, 0xE4, 0x5D, 0xF6, 0x1F, 0x0E, 0xB5, 0xEB, 0x8F, 0xEE, 0xFF, 0x00, 0xA2, 0xAC, 0x7F,
+	0xFA, 0x13, 0x2D, 0x46, 0xBE, 0x36, 0xF8, 0x95, 0x75, 0x32, 0xFF, 0x00, 0x67, 0xFC, 0x19, 0xBC,
+	0x55, 0xFE, 0x16, 0xBA, 0xD5, 0x2D, 0xE2, 0xFF, 0x00, 0xD9, 0x9A, 0xAD, 0xAF, 0x8C, 0x3C, 0x66,
+	0xB6, 0xFE, 0x73, 0xFC, 0x2E, 0xBA, 0xFF, 0x00, 0x76, 0x3D, 0x4A, 0x16, 0x6F, 0xFD, 0x0A, 0x96,
+	0x4F, 0x1D, 0x78, 0x86, 0x35, 0x59, 0x9F, 0xE1, 0xBE, 0xB5, 0xFD, 0xE6, 0xF2, 0xDA, 0x36, 0xDB,
+	0xFF, 0x00, 0x8F, 0x56, 0x1E, 0xD3, 0xF9, 0xAA, 0x4D, 0x7A, 0x42, 0xDF, 0x9C, 0x07, 0xCA, 0xE5,
+	0xAD, 0xCD, 0x7F, 0x0A, 0xDF, 0xF8, 0xB7, 0x50, 0x59, 0x3F, 0xE1, 0x2A, 0xF0, 0xAC, 0x7A, 0x6B,
+	0x2F, 0xFA, 0xAF, 0x2E, 0xFD, 0x67, 0xDD, 0xFF, 0x00, 0x8E, 0xAD, 0x6F, 0xC3, 0xB6, 0xB2, 0x6C,
+	0xF5, 0x27, 0xB8, 0xB7, 0x8E, 0xE7, 0xC9, 0x92, 0x3F, 0x31, 0x77, 0x79, 0x73, 0x2E, 0xD6, 0x5F,
+	0xF7, 0xAA, 0xF5, 0xBC, 0xD3, 0x32, 0xB7, 0xF0, 0xD7, 0xA7, 0x0D, 0x22, 0x95, 0xEF, 0xEA, 0x23,
+	0x4E, 0x16, 0xDC, 0xDF, 0x73, 0xEE, 0xD5, 0x98, 0xD7, 0xE6, 0xFB, 0x95, 0x42, 0xD5, 0xA4, 0x91,
+	0x94, 0x38, 0xF9, 0x6A, 0xED, 0xBF, 0xDE, 0xE3, 0xEE, 0xD6, 0x91, 0x02, 0xE4, 0x7C, 0xAA, 0xD7,
+	0xC8, 0xDF, 0xF0, 0x5A, 0xFF, 0x00, 0x8A, 0x5A, 0xD7, 0xC3, 0x6F, 0xD8, 0x83, 0x57, 0xB0, 0xD1,
+	0x21, 0x98, 0xBF, 0x88, 0x2F, 0x63, 0xD3, 0xAE, 0x26, 0x85, 0x37, 0x79, 0x70, 0xB0, 0x2C, 0xF9,
+	0xFF, 0x00, 0x7B, 0x6E, 0xDF, 0xF8, 0x15, 0x7D, 0x79, 0x0F, 0xDD, 0xAF, 0x87, 0xBF, 0xE0, 0xB6,
+	0x5F, 0x17, 0xB4, 0x3F, 0x0F, 0x7C, 0x05, 0xB5, 0xF8, 0x7D, 0xA9, 0x69, 0x91, 0xDE, 0x7F, 0x69,
+	0x6B, 0x96, 0xAF, 0xF6, 0x56, 0xFF, 0x00, 0x96, 0xCB, 0x1C, 0x8B, 0x21, 0x56, 0xFF, 0x00, 0x65,
+	0xB6, 0xED, 0xFF, 0x00, 0x81, 0x57, 0x9B, 0x9C, 0xCE, 0x31, 0xC0, 0xF2, 0xC9, 0xE8, 0xE5, 0x14,
+	0xFC, 0xD7, 0x32, 0x72, 0x5E, 0x8E, 0x29, 0xA7, 0xE4, 0xCD, 0x29, 0xC5, 0xCE, 0x56, 0x5D, 0x9F,
+	0xFC, 0x05, 0xF3, 0x67, 0xCA, 0xBF, 0x12, 0x96, 0xF3, 0xF6, 0x6B, 0xFF, 0x00, 0x82, 0x4E, 0xF8,
+	0x1F, 0xE0, 0xB5, 0x84, 0x3F, 0x67, 0xD6, 0xBC, 0x74, 0xAD, 0xAB, 0x6B, 0x2C, 0xDF, 0x2C, 0x8D,
+	0xE7, 0x36, 0xEF, 0x9B, 0xFE, 0x03, 0xB5, 0x6B, 0xF3, 0x47, 0xF6, 0x90, 0xD6, 0xB5, 0xAF, 0x87,
+	0xFF, 0x00, 0x0F, 0x6E, 0x6E, 0x66, 0xB9, 0xDB, 0x35, 0xF3, 0x2A, 0x5B, 0xC8, 0xAD, 0xFE, 0xD7,
+	0xCD, 0xFF, 0x00, 0xA0, 0xD7, 0xD4, 0xDF, 0xB7, 0x37, 0xED, 0x95, 0xAF, 0x7E, 0xD3, 0x1E, 0x28,
+	0xB3, 0xD6, 0xFF, 0x00, 0xB3, 0x63, 0xD2, 0xEC, 0xEC, 0x6D, 0x63, 0xB5, 0xB3, 0xD3, 0xED, 0xDB,
+	0x72, 0xC2, 0xAA, 0xAA, 0xBF, 0xFA, 0x12, 0xD7, 0xC7, 0xBF, 0x18, 0x7C, 0x2B, 0xE3, 0x0F, 0x8D,
+	0x5F, 0x11, 0xB4, 0x7F, 0x87, 0x5A, 0x55, 0xE6, 0xE6, 0x55, 0x57, 0x68, 0xD9, 0x5B, 0xE5, 0xDD,
+	0xFE, 0xCA, 0xFF, 0x00, 0x0F, 0xDD, 0xAF, 0xCC, 0xBE, 0xB5, 0x8D, 0xCF, 0x33, 0xAA, 0xD8, 0x86,
+	0xBF, 0x75, 0xCD, 0xA2, 0x6B, 0x5E, 0x48, 0xAB, 0x2F, 0x4E, 0xFF, 0x00, 0x33, 0xEC, 0xA8, 0xE1,
+	0x30, 0xF9, 0x7E, 0x5D, 0x18, 0x3B, 0xF3, 0xBD, 0xF5, 0xEA, 0xD9, 0xFA, 0x3D, 0xFF, 0x00, 0x04,
+	0x79, 0xD4, 0xA2, 0xFD, 0xA0, 0x3E, 0x0C, 0xEC, 0xF1, 0x22, 0x79, 0xD7, 0x5A, 0x5A, 0xEC, 0xDB,
+	0x24, 0xBB, 0x9A, 0x49, 0x3F, 0x87, 0xFE, 0xF9, 0xAF, 0xAF, 0x7E, 0x32, 0x7E, 0xC6, 0xDE, 0x1E,
+	0xF1, 0x47, 0x81, 0x7C, 0x3F, 0xE0, 0xCB, 0x4B, 0x96, 0xD3, 0xEE, 0x6F, 0x2E, 0x17, 0xFB, 0x52,
+	0x38, 0xFE, 0xF3, 0x7C, 0xCC, 0xCD, 0xFF, 0x00, 0x8E, 0xD7, 0xCF, 0x9F, 0xF0, 0x6F, 0xBF, 0xC0,
+	0x9F, 0x10, 0xFC, 0x31, 0xF0, 0xDF, 0x8A, 0xAF, 0x3C, 0x61, 0x67, 0xBA, 0x1F, 0xB4, 0x42, 0xB6,
+	0x37, 0x5B, 0xB7, 0x2B, 0x2E, 0xE9, 0x17, 0xFF, 0x00, 0x42, 0xAF, 0xB5, 0xFC, 0x7D, 0xF1, 0x1B,
+	0xC3, 0x1A, 0x7F, 0xC7, 0x8F, 0xB3, 0x6B, 0x17, 0x91, 0xC3, 0x1E, 0x9F, 0xA3, 0x48, 0xB1, 0x79,
+	0x8D, 0xB5, 0x5A, 0x66, 0x65, 0x5D, 0xAB, 0xFE, 0xD7, 0xDE, 0xFF, 0x00, 0xC7, 0x6B, 0xDB, 0x9E,
+	0x41, 0x96, 0xC3, 0x07, 0x4F, 0x11, 0xEC, 0xE3, 0x19, 0xCD, 0xA5, 0x7B, 0x5A, 0xC9, 0x37, 0x26,
+	0xFD, 0x6C, 0xAC, 0x70, 0x56, 0xCD, 0x31, 0x15, 0xB1, 0x4E, 0x93, 0x6D, 0xC6, 0x2A, 0xFE, 0xAE,
+	0xD6, 0x5F, 0x2B, 0x9E, 0x79, 0xFB, 0x2E, 0xFE, 0xCB, 0xD6, 0x7F, 0x06, 0xFC, 0x5D, 0xA9, 0x78,
+	0xA9, 0xF5, 0x56, 0xBC, 0x86, 0x1B, 0x35, 0xB5, 0xB5, 0xF3, 0x17, 0xEE, 0xAA, 0xFC, 0xCD, 0x5D,
+	0x67, 0xC4, 0x0D, 0x57, 0xCA, 0xD1, 0xDB, 0xCB, 0xFB, 0xD7, 0x53, 0xB7, 0xFC, 0x0A, 0xBA, 0x1D,
+	0x0B, 0xC6, 0x7A, 0x57, 0x89, 0x7C, 0x0E, 0xD3, 0x68, 0x37, 0x4A, 0xE5, 0x97, 0x6C, 0xCD, 0x1B,
+	0x7D, 0xD6, 0xFE, 0x2F, 0xFD, 0x9A, 0xB0, 0xA1, 0xD2, 0xB4, 0xAF, 0x11, 0xC5, 0x1F, 0xDB, 0x2E,
+	0x7F, 0xE3, 0xDE, 0x2D, 0xAD, 0x0F, 0xDE, 0xDA, 0xDF, 0xFC, 0x4D, 0x7C, 0x36, 0x7F, 0x1A, 0xD5,
+	0xB9, 0x30, 0xB4, 0xA4, 0x9B, 0xE5, 0xBA, 0x7B, 0x5F, 0x99, 0xFB, 0xD6, 0xF4, 0x5D, 0x3C, 0xCF,
+	0xA3, 0xC1, 0xAF, 0xF6, 0x57, 0x55, 0x47, 0xE2, 0x76, 0xF4, 0xB6, 0x8A, 0xFF, 0x00, 0x32, 0xEF,
+	0xC3, 0x3B, 0xD7, 0xD6, 0x7C, 0x37, 0x25, 0x84, 0x90, 0xAA, 0x7D, 0x87, 0x6F, 0x93, 0x27, 0xF0,
+	0xB6, 0xEA, 0xC6, 0xF1, 0x16, 0x9F, 0xA6, 0xEB, 0x3F, 0x12, 0xAC, 0x34, 0xA7, 0xDD, 0x1A, 0x34,
+	0xAA, 0xB3, 0x34, 0x75, 0xD0, 0x78, 0x46, 0x38, 0x7C, 0x35, 0xA5, 0xDC, 0x69, 0xAF, 0xFE, 0xB2,
+	0x4B, 0x86, 0x95, 0x99, 0xBF, 0xBA, 0xB5, 0x57, 0xE0, 0x7E, 0x8B, 0x73, 0xE3, 0x0F, 0x8A, 0x97,
+	0x1A, 0xDC, 0x33, 0x5B, 0xB2, 0xD9, 0xBE, 0xED, 0xB3, 0x7F, 0x15, 0x79, 0x91, 0xA3, 0x3C, 0xCB,
+	0x11, 0x81, 0xC0, 0xB5, 0xCD, 0x29, 0x4A, 0x3C, 0xDA, 0x6C, 0xA3, 0xAB, 0xD3, 0x4D, 0x93, 0xB3,
+	0xD4, 0xC2, 0xB7, 0x36, 0x17, 0x0B, 0x5A, 0xA4, 0x9D, 0xAC, 0x9D, 0xBE, 0x7A, 0x1E, 0xBD, 0xE2,
+	0x59, 0x9E, 0xDF, 0x4B, 0xB3, 0xD1, 0x34, 0xD7, 0x92, 0xFD, 0xA3, 0x8B, 0x72, 0xC2, 0xBF, 0x2E,
+	0xE5, 0x5F, 0xBC, 0xAD, 0x5F, 0x97, 0xBF, 0xB6, 0xA7, 0xC4, 0x0D, 0x3B, 0xC6, 0x1F, 0x1D, 0x35,
+	0x44, 0x4D, 0x1E, 0x6D, 0x35, 0xAC, 0x5B, 0xCA, 0xF2, 0xEF, 0x25, 0xDD, 0xBB, 0x6F, 0xF7, 0x7E,
+	0x66, 0xAF, 0xBE, 0x3F, 0x6B, 0x2F, 0xDA, 0x1B, 0xE1, 0x17, 0xC1, 0x1D, 0x16, 0xF2, 0xFF, 0x00,
+	0xE2, 0x77, 0xC5, 0x48, 0x7C, 0x3C, 0xF2, 0x59, 0xCD, 0xFD, 0x9A, 0xB6, 0xED, 0xFB, 0xC6, 0x99,
+	0x63, 0x6F, 0x95, 0x7F, 0xBD, 0xF7, 0x6B, 0xF9, 0x7E, 0xFD, 0xA8, 0xBF, 0x6C, 0x2F, 0x8C, 0xDE,
+	0x38, 0xF8, 0xF5, 0xE2, 0x7F, 0x10, 0xE8, 0xFF, 0x00, 0x12, 0x35, 0x29, 0x2D, 0xA6, 0xD5, 0x26,
+	0x6B, 0x5B, 0x89, 0x9B, 0x6B, 0xC9, 0x1E, 0xEF, 0x95, 0xBF, 0xEF, 0x9A, 0xFD, 0xC6, 0x8E, 0x33,
+	0x0F, 0x53, 0x31, 0x74, 0xE2, 0xD3, 0x70, 0x4E, 0xF6, 0x69, 0xF2, 0xDA, 0xC9, 0x27, 0xAB, 0x69,
+	0xB5, 0xAA, 0x4D, 0xEA, 0xBA, 0x1F, 0x9D, 0xBC, 0x3D, 0x4A, 0xBA, 0xAE, 0xBD, 0x7F, 0xCB, 0x73,
+	0xF4, 0xC7, 0x50, 0xBE, 0x86, 0x4B, 0x7F, 0x26, 0x1B, 0xC8, 0x51, 0xD7, 0x6E, 0xD6, 0x69, 0x7E,
+	0xEF, 0xF9, 0xFF, 0x00, 0x3F, 0xC5, 0x55, 0xED, 0xAE, 0x21, 0x86, 0xC5, 0x61, 0x7B, 0xC8, 0x7F,
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+	0x5F, 0xBA, 0xDB, 0x7C, 0xB5, 0xFE, 0xED, 0x7D, 0x2F, 0x6F, 0xFF, 0x00, 0x04, 0xBF, 0xF8, 0x15,
+	0x6E, 0x55, 0xF5, 0x8F, 0x8B, 0x5F, 0x17, 0xB5, 0x26, 0x5F, 0xF9, 0xFE, 0xF8, 0xB5, 0xAC, 0x37,
+	0xFE, 0x83, 0x70, 0xB5, 0x72, 0x1F, 0xF8, 0x27, 0x0F, 0xEC, 0xBB, 0x66, 0xA3, 0xED, 0x3A, 0x6F,
+	0x8A, 0xAF, 0xFF, 0x00, 0xEC, 0x25, 0xE3, 0xCD, 0x52, 0xE7, 0x77, 0xFB, 0xDE, 0x65, 0xC5, 0x76,
+	0xD3, 0xE2, 0x87, 0x4A, 0x2D, 0x38, 0x36, 0x9A, 0x6A, 0xD7, 0xEF, 0xF3, 0x39, 0x9F, 0x0F, 0xD3,
+	0xE6, 0x4E, 0x15, 0xE4, 0xAC, 0xD3, 0xD2, 0x36, 0xFF, 0x00, 0xDB, 0x97, 0xF5, 0xB9, 0xF8, 0x37,
+	0xFB, 0x3F, 0xFF, 0x00, 0xC1, 0x0E, 0x7F, 0x6A, 0x5F, 0xDA, 0x93, 0xC6, 0x17, 0x3A, 0xAF, 0xC1,
+	0x0B, 0xFF, 0x00, 0xEC, 0xFF, 0x00, 0x03, 0x43, 0xE2, 0x0B, 0x5B, 0x0D, 0x47, 0x52, 0xBA, 0xBC,
+	0x6F, 0x3E, 0xCD, 0xA6, 0x8D, 0x64, 0x69, 0x3C, 0xBF, 0x97, 0x74, 0x6A, 0xBB, 0xBE, 0x6F, 0xF7,
+	0x56, 0xBF, 0x60, 0xFF, 0x00, 0x67, 0xDF, 0xF8, 0x23, 0xFF, 0x00, 0xFC, 0x13, 0x27, 0xFE, 0x09,
+	0xAF, 0xF0, 0xC9, 0xBE, 0x27, 0xFE, 0xD0, 0xF6, 0xDA, 0x1E, 0xAF, 0xF6, 0x78, 0x95, 0xB5, 0x2F,
+	0x16, 0x7C, 0x50, 0x92, 0x3B, 0xBF, 0xB5, 0x48, 0xAA, 0xCD, 0xE5, 0xC1, 0x69, 0x26, 0xE5, 0xFE,
+	0xF6, 0xD8, 0xE3, 0x56, 0x6F, 0xF7, 0xAB, 0xEA, 0xBF, 0x86, 0x3F, 0x0D, 0x7C, 0x13, 0xF0, 0x53,
+	0x4B, 0x93, 0x47, 0xF8, 0x57, 0xE1, 0xBB, 0x5D, 0x16, 0xD6, 0x6F, 0x2F, 0xCD, 0x86, 0xD5, 0x7E,
+	0x56, 0xF2, 0xFF, 0x00, 0xD5, 0xEE, 0xDD, 0xFD, 0xDD, 0xCD, 0x4E, 0xF1, 0x8F, 0xC3, 0xCF, 0x02,
+	0xFC, 0x4C, 0xD4, 0xE3, 0xD6, 0xBE, 0x22, 0x78, 0x3F, 0x4D, 0xD7, 0xAE, 0xA1, 0xF9, 0x6D, 0xE4,
+	0xD6, 0x34, 0xF8, 0xEE, 0x3C, 0x95, 0xFE, 0xEA, 0x79, 0x8A, 0xDB, 0x7F, 0xE0, 0x35, 0xE5, 0x53,
+	0xCC, 0xA8, 0xD4, 0xA8, 0xA5, 0x59, 0xBF, 0x48, 0xD9, 0x75, 0xD2, 0xEF, 0xBD, 0xAD, 0xDC, 0xF5,
+	0x96, 0x1F, 0x96, 0x7B, 0xB4, 0xBB, 0xAD, 0x1B, 0xFF, 0x00, 0x2F, 0xEB, 0x46, 0x7E, 0x1D, 0x7F,
+	0xC1, 0x38, 0x7C, 0x77, 0xF0, 0x43, 0xC3, 0x3F, 0xF0, 0x5E, 0x67, 0xD5, 0x3E, 0x03, 0xE9, 0x4C,
+	0x3E, 0x1F, 0x6B, 0x1A, 0xCE, 0xA8, 0x9E, 0x12, 0x8D, 0x6D, 0xD9, 0x62, 0xD3, 0xE4, 0x9A, 0xD5,
+	0xA4, 0x8B, 0x62, 0xAF, 0xCA, 0xBB, 0x5B, 0x74, 0x6B, 0xFE, 0xCB, 0x57, 0xEF, 0x9E, 0xB5, 0x7B,
+	0x77, 0xA4, 0xF8, 0xEB, 0x45, 0xD4, 0x35, 0x2B, 0x3D, 0x8D, 0xA9, 0x69, 0x3E, 0x74, 0x8C, 0xBF,
+	0x79, 0x66, 0x86, 0x45, 0x6D, 0xBF, 0xF7, 0xCB, 0xD6, 0x06, 0x83, 0xE0, 0x3F, 0x87, 0xBE, 0x1B,
+	0x9A, 0x39, 0xB4, 0x7F, 0x01, 0xE8, 0xF6, 0x4D, 0x0B, 0x7E, 0xE9, 0xAD, 0x74, 0xB8, 0xE3, 0x65,
+	0xFF, 0x00, 0x77, 0x6A, 0xD3, 0xFF, 0x00, 0x68, 0x1D, 0x7D, 0x75, 0x2F, 0x07, 0x69, 0x7A, 0x2F,
+	0x83, 0xB5, 0x3F, 0xF8, 0xAA, 0xAE, 0xAE, 0x3E, 0xCD, 0xA4, 0xDB, 0x5A, 0xC9, 0xFB, 0xF8, 0xFC,
+	0xCD, 0xAA, 0xD2, 0x32, 0xFF, 0x00, 0xCF, 0x35, 0x51, 0xF3, 0x6E, 0xFF, 0x00, 0x65, 0x7F, 0x8A,
+	0xBD, 0x09, 0x56, 0xA3, 0x8B, 0x93, 0x74, 0xFE, 0x26, 0x93, 0xF9, 0xAB, 0x7E, 0x9F, 0xD6, 0xA7,
+	0x24, 0xD5, 0x49, 0xD6, 0x6E, 0x69, 0xD9, 0xDF, 0xCF, 0xBB, 0xBE, 0x9B, 0x25, 0xD7, 0xCB, 0xD0,
+	0xF7, 0x6D, 0xC3, 0xD6, 0x8A, 0x8A, 0xC6, 0x19, 0x2D, 0xEC, 0xA2, 0x82, 0x57, 0xDC, 0xC9, 0x18,
+	0x0C, 0xDE, 0xBC, 0x51, 0x5E, 0xA1, 0xE6, 0x92, 0xD1, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14, 0x00,
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+	0xD5, 0x60, 0xFC, 0x47, 0xF0, 0x26, 0x95, 0xF1, 0x37, 0xC0, 0xBA, 0xA7, 0x80, 0xB5, 0xBB, 0x8B,
+	0x98, 0x6C, 0xF5, 0x6B, 0x36, 0xB7, 0xB8, 0x96, 0xCE, 0x5F, 0x2E, 0x55, 0x56, 0xFE, 0xEB, 0x76,
+	0xAC, 0xEA, 0xCA, 0xA4, 0x69, 0xB7, 0x05, 0x77, 0x67, 0x6F, 0x5E, 0x80, 0x7E, 0x7D, 0xFF, 0x00,
+	0xC1, 0x34, 0xED, 0x66, 0xFD, 0xAF, 0x3F, 0xE0, 0xA1, 0x7F, 0x18, 0x7F, 0x6E, 0xFF, 0x00, 0x10,
+	0xC6, 0xF2, 0x68, 0xFE, 0x1A, 0x7F, 0xF8, 0x44, 0xBC, 0x1F, 0x34, 0x87, 0x31, 0xB3, 0x6E, 0xF3,
+	0x2E, 0x5E, 0x3F, 0xE1, 0xF9, 0x55, 0x61, 0xDD, 0xFF, 0x00, 0x5F, 0x15, 0xF7, 0x76, 0xA3, 0x70,
+	0xF7, 0xD7, 0xCF, 0x72, 0xFB, 0xBE, 0x66, 0xFB, 0xBF, 0xDD, 0xAF, 0x07, 0xF8, 0x2B, 0x6F, 0xFB,
+	0x2B, 0x7F, 0xC1, 0x33, 0x3E, 0x1A, 0x43, 0xFB, 0x35, 0x6B, 0x7F, 0x18, 0x74, 0x9D, 0x32, 0x43,
+	0x7D, 0x79, 0xA8, 0xC3, 0x2E, 0xA4, 0xFE, 0x54, 0xD7, 0x11, 0xCD, 0x33, 0x49, 0xBE, 0x4F, 0xBD,
+	0xF3, 0x7C, 0xCB, 0x1E, 0xEF, 0xE2, 0xF2, 0xD6, 0xB7, 0x64, 0xFD, 0xBB, 0x3F, 0x63, 0x35, 0x7F,
+	0x9F, 0xF6, 0x99, 0xF0, 0xBF, 0xCD, 0xF7, 0x76, 0xDE, 0x6E, 0xAE, 0x1C, 0x56, 0x61, 0x81, 0x8C,
+	0x61, 0x47, 0xDA, 0x45, 0x28, 0x45, 0x47, 0x59, 0x2B, 0xDD, 0x2F, 0x79, 0xBD, 0x77, 0x72, 0xBB,
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+	0x49, 0x2F, 0x44, 0x8F, 0x52, 0x93, 0xE5, 0x93, 0x66, 0xFA, 0x26, 0x6F, 0x26, 0x3F, 0x39, 0xA6,
+	0xF9, 0x7E, 0xEF, 0xCD, 0xF7, 0x6B, 0xC9, 0x6E, 0xBF, 0x6E, 0xEF, 0xD8, 0xAA, 0x15, 0x52, 0xFF,
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+	0xDF, 0xFF, 0x00, 0x04, 0xF7, 0xD4, 0xB4, 0x8D, 0x3E, 0xEB, 0x5E, 0xF8, 0xDE, 0xBA, 0x9B, 0x69,
+	0xB2, 0x48, 0xD6, 0xF6, 0x5A, 0x3C, 0xD3, 0x7E, 0xF1, 0xA4, 0x5F, 0xBC, 0xCA, 0xBB, 0x77, 0x7C,
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+	0x49, 0x74, 0xD1, 0xAC, 0x71, 0xFC, 0xAB, 0x1E, 0xD5, 0xDA, 0xBF, 0xEB, 0x1B, 0xFC, 0xAA, 0xD6,
+	0x78, 0x5C, 0xE6, 0x95, 0x49, 0x5A, 0xB3, 0x8C, 0x57, 0x7E, 0x6F, 0xF3, 0x8A, 0xFC, 0xC5, 0x2A,
+	0x15, 0xBE, 0xCC, 0x1F, 0xDC, 0x7D, 0xD4, 0xAA, 0x8B, 0x1E, 0xFD, 0x9F, 0xEF, 0x7F, 0xBD, 0x4A,
+	0xB2, 0x24, 0x9B, 0x93, 0x7F, 0xFB, 0xD5, 0xF3, 0xF5, 0xE7, 0xFC, 0x15, 0x1B, 0xF6, 0x1B, 0xB4,
+	0x8D, 0x3F, 0xE2, 0xF7, 0xDA, 0xCC, 0xAC, 0xDF, 0x37, 0x97, 0x6B, 0x23, 0x6D, 0xFF, 0x00, 0x7B,
+	0xE5, 0xA8, 0x21, 0xFF, 0x00, 0x82, 0xA6, 0x7E, 0xC3, 0x6A, 0xCC, 0xE9, 0xF1, 0x83, 0xE5, 0x5F,
+	0x9B, 0x77, 0xF6, 0x6C, 0xDF, 0x37, 0xFE, 0x3B, 0x5D, 0xD2, 0xCD, 0xB2, 0xCF, 0xF9, 0xFD, 0x1F,
+	0xBD, 0x11, 0xF5, 0x7C, 0x47, 0xF2, 0xBF, 0xB9, 0xFF, 0x00, 0x91, 0xF4, 0x8D, 0xBC, 0x89, 0x1F,
+	0xC8, 0x3E, 0x6A, 0xB9, 0x0D, 0xE2, 0xAB, 0xFF, 0x00, 0x76, 0xBE, 0x66, 0x93, 0xFE, 0x0A, 0xA9,
+	0xFB, 0x0F, 0x5B, 0xC2, 0xB3, 0x27, 0xC5, 0xFD, 0xCA, 0xDF, 0x77, 0x6D, 0x84, 0xDF, 0x37, 0xFE,
+	0x3B, 0x48, 0xBF, 0xF0, 0x55, 0x8F, 0xD8, 0x7F, 0x72, 0xCD, 0xFF, 0x00, 0x0B, 0x6A, 0x46, 0x58,
+	0xD9, 0x5B, 0x6F, 0xF6, 0x6C, 0xDF, 0x37, 0xFE, 0x3B, 0xFE, 0xCD, 0x0B, 0x37, 0xCA, 0xE3, 0xFF,
+	0x00, 0x2F, 0xA3, 0xF7, 0xA0, 0xFA, 0xBE, 0x23, 0xF9, 0x1F, 0xDC, 0xCF, 0x4C, 0xFD, 0xA3, 0x3F,
+	0x6F, 0x9F, 0xD9, 0x23, 0xF6, 0x48, 0x7F, 0xB0, 0xFE, 0xD0, 0x9F, 0x1C, 0x74, 0x3F, 0x0E, 0xEA,
+	0x0D, 0x66, 0xD7, 0x56, 0xFA, 0x55, 0xD5, 0xD6, 0xEB, 0xB9, 0xA3, 0x5F, 0xE2, 0x58, 0x97, 0xE6,
+	0x6E, 0x95, 0xF8, 0xB9, 0xFB, 0x62, 0x7F, 0xC1, 0x4F, 0xBF, 0xE1, 0xE1, 0x5E, 0x3C, 0xF1, 0x17,
+	0x8D, 0xBC, 0x0B, 0xA3, 0xFD, 0x87, 0xC2, 0x3E, 0x15, 0x97, 0xC8, 0xD0, 0x6D, 0xEE, 0x97, 0xF7,
+	0xF7, 0x8C, 0xCB, 0xBB, 0xCE, 0x6F, 0x9B, 0xF8, 0xBE, 0x5F, 0x97, 0xF8, 0x6A, 0xEF, 0xED, 0x65,
+	0xFF, 0x00, 0x05, 0x1D, 0xFF, 0x00, 0x82, 0x6F, 0xFE, 0xD2, 0x5F, 0x18, 0xFC, 0x41, 0xF1, 0x2F,
+	0xE2, 0x5F, 0xC1, 0xCD, 0x53, 0xC4, 0x37, 0xD7, 0x57, 0x0D, 0x6F, 0x6F, 0x7D, 0xA8, 0x69, 0xAA,
+	0xCD, 0x1C, 0x31, 0xFC, 0xB1, 0xAC, 0x7F, 0xBE, 0xF9, 0x57, 0xE5, 0x6F, 0xFB, 0xEA, 0xBE, 0x5D,
+	0x8F, 0xF6, 0x9A, 0xF0, 0xA7, 0x89, 0x3C, 0x4D, 0x37, 0x80, 0xBC, 0x01, 0xE0, 0x9D, 0x0F, 0x4A,
+	0xD0, 0xF5, 0x0D, 0x52, 0xE2, 0x5B, 0x58, 0xED, 0xEC, 0x3C, 0xA9, 0xD5, 0x55, 0x59, 0xA3, 0x59,
+	0x24, 0xFE, 0x2F, 0x97, 0x77, 0xFB, 0xBB, 0x7F, 0xDD, 0xAF, 0x27, 0x36, 0xA7, 0x89, 0xA9, 0x97,
+	0xCB, 0x13, 0x52, 0xA6, 0xC9, 0xB8, 0xC6, 0x29, 0xA4, 0xAF, 0xA5, 0xE5, 0x7D, 0x5C, 0x92, 0xF4,
+	0x8A, 0x77, 0xD2, 0xF6, 0x6B, 0xAB, 0x27, 0x97, 0xB4, 0xCC, 0x23, 0x4E, 0x50, 0xD2, 0xFB, 0xBD,
+	0xB4, 0xDB, 0xF1, 0xB1, 0xCB, 0xE8, 0x1A, 0xB7, 0xC4, 0x2B, 0xCD, 0x61, 0x6D, 0xBC, 0x49, 0x34,
+	0x29, 0x6F, 0x24, 0xBF, 0x75, 0xBF, 0xBB, 0xBB, 0xE6, 0x6A, 0xF4, 0x2F, 0xD9, 0xBF, 0x43, 0x7D,
+	0x73, 0xC6, 0x5E, 0x22, 0xF8, 0xB5, 0x2F, 0x97, 0x70, 0xB0, 0xBF, 0xD9, 0xF4, 0xD6, 0x5F, 0xBB,
+	0xB9, 0xBE, 0x55, 0xFF, 0x00, 0x96, 0x7B, 0x7F, 0xF1, 0xEA, 0xE6, 0xF5, 0xDF, 0x10, 0x5B, 0xE9,
+	0x3A, 0x3E, 0xA9, 0xAE, 0x22, 0x42, 0xAF, 0x1D, 0xBB, 0x45, 0x13, 0x37, 0xFC, 0xF4, 0x93, 0x72,
+	0xFF, 0x00, 0xF1, 0x55, 0xED, 0x7F, 0xB2, 0x7F, 0xC3, 0xF4, 0xD3, 0x7C, 0x2B, 0xE1, 0xED, 0x2A,
+	0xE6, 0x3B, 0x55, 0x92, 0xF2, 0xE9, 0xAF, 0xDB, 0xF8, 0x59, 0x95, 0x7E, 0xEF, 0xDE, 0xDB, 0xFC,
+	0x4C, 0xBF, 0x75, 0xAB, 0xC7, 0xCB, 0x39, 0xA1, 0x81, 0x75, 0x1A, 0xB3, 0x96, 0x87, 0xD0, 0x63,
+	0x14, 0x56, 0x25, 0x42, 0xF7, 0x4A, 0xEF, 0xE7, 0xD0, 0xFB, 0x8F, 0xF6, 0x3A, 0xF8, 0xAD, 0x79,
+	0xF0, 0xDE, 0xC7, 0x43, 0xF0, 0x4D, 0x9D, 0xFC, 0x30, 0xAE, 0xB5, 0x79, 0x0D, 0x94, 0x5E, 0x73,
+	0x2E, 0xD6, 0xDB, 0xFE, 0xEC, 0x8D, 0xF7, 0x9B, 0xFF, 0x00, 0x42, 0xAF, 0x61, 0xFD, 0xA8, 0x7F,
+	0xE0, 0x99, 0xF7, 0x9F, 0xB4, 0x87, 0x8A, 0x93, 0xE2, 0x46, 0x89, 0xF1, 0xCB, 0x58, 0xF0, 0xFC,
+	0xD1, 0xC4, 0xAD, 0x24, 0x76, 0x77, 0x1B, 0x95, 0xBF, 0x8B, 0xFF, 0x00, 0x65, 0x5A, 0xF9, 0x23,
+	0xC6, 0x1E, 0x37, 0xBF, 0xF0, 0x9F, 0xC6, 0x6F, 0x03, 0xF8, 0x0F, 0x4D, 0xB0, 0x9A, 0xFA, 0x6D,
+	0x3E, 0xE2, 0x37, 0x68, 0x6C, 0xD5, 0xA4, 0x66, 0xDD, 0xB7, 0x73, 0x7F, 0xAC, 0x6F, 0xBB, 0xFF,
+	0x00, 0xB2, 0xD7, 0xDE, 0xDE, 0x24, 0xF8, 0xE5, 0xAC, 0x78, 0x3F, 0xC2, 0xA9, 0x0F, 0xFC, 0x22,
+	0x57, 0x5F, 0x69, 0x6B, 0x75, 0xDD, 0x0C, 0xDF, 0xBB, 0xFB, 0xDF, 0x77, 0xFC, 0xFF, 0x00, 0xB3,
+	0x5D, 0x18, 0x7C, 0x46, 0x17, 0x19, 0x42, 0xA5, 0x1C, 0x42, 0x6D, 0x41, 0xE8, 0xEF, 0x25, 0x67,
+	0x6E, 0x8D, 0x2D, 0x3A, 0x9E, 0x4E, 0x32, 0x8B, 0xA5, 0x38, 0x55, 0xA7, 0xD7, 0x7D, 0x37, 0x1F,
+	0xFB, 0x36, 0xFC, 0x1B, 0xF0, 0x97, 0xC2, 0xBF, 0x86, 0x29, 0xE1, 0x2B, 0x9D, 0x6E, 0xE2, 0xFE,
+	0xE2, 0x15, 0x65, 0xBA, 0xD4, 0x24, 0x97, 0x77, 0xDA, 0xA4, 0xFE, 0xF3, 0x52, 0x68, 0x2A, 0xF0,
+	0xEB, 0x1A, 0xB4, 0xCC, 0x9B, 0x15, 0x6E, 0x16, 0x25, 0x8F, 0xFD, 0x95, 0xF9, 0xAB, 0x17, 0xC4,
+	0x9F, 0x1B, 0xAD, 0x3C, 0x2B, 0xE2, 0x4F, 0x87, 0xFE, 0x06, 0xF0, 0xC6, 0x99, 0x1C, 0xD7, 0x1E,
+	0x32, 0xB8, 0x5F, 0xB6, 0x5B, 0xF9, 0xBF, 0xF1, 0xEE, 0xBB, 0x77, 0x48, 0xD5, 0xDD, 0x78, 0xC3,
+	0xC3, 0x67, 0x4D, 0x81, 0x2F, 0xED, 0x9F, 0xCB, 0xBA, 0xDB, 0xFB, 0xCD, 0xBF, 0x75, 0xBF, 0xE0,
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+	0xBC, 0x6D, 0xE2, 0x6D, 0x4B, 0x54, 0xB9, 0x59, 0xD7, 0x47, 0xF0, 0xDE, 0xA8, 0xB3, 0xAD, 0xD5,
+	0xBB, 0x43, 0x25, 0xAB, 0x33, 0xD9, 0x49, 0x7D, 0x1F, 0x97, 0x6F, 0x1E, 0xF4, 0x92, 0x49, 0x16,
+	0x1F, 0x2F, 0x72, 0xC7, 0xF3, 0x33, 0x36, 0xD6, 0xF6, 0x6C, 0x1E, 0xEC, 0x6A, 0x7A, 0xFA, 0xFE,
+	0x3B, 0x6F, 0xFF, 0x00, 0x0C, 0x99, 0xE7, 0x37, 0x7F, 0xB3, 0x2F, 0xC0, 0x4F, 0x03, 0xEA, 0xFA,
+	0xD7, 0x85, 0x3C, 0x2D, 0xFF, 0x00, 0x04, 0xD8, 0xF0, 0xEE, 0xA1, 0xA9, 0x5B, 0xDF, 0x5C, 0x4B,
+	0xA2, 0x6A, 0x50, 0xFC, 0x39, 0xB5, 0xBE, 0xB5, 0x5D, 0x3D, 0x63, 0x8D, 0xA0, 0x9A, 0x5B, 0x9B,
+	0xFB, 0x88, 0x56, 0x79, 0xA5, 0x93, 0x72, 0xF9, 0x30, 0xCC, 0xB2, 0x47, 0xFC, 0x51, 0xED, 0x8F,
+	0xCC, 0x6F, 0x7C, 0xD0, 0xBF, 0x66, 0xBF, 0x80, 0xBA, 0xB7, 0x85, 0x6C, 0xED, 0xBC, 0x45, 0xFB,
+	0x36, 0x78, 0x2F, 0x4F, 0xB8, 0xBA, 0xB1, 0x85, 0xF5, 0x2D, 0x2F, 0xFE, 0x11, 0xDB, 0x19, 0x16,
+	0xD6, 0x66, 0x8D, 0x59, 0xE1, 0xDC, 0xB1, 0xED, 0x6D, 0xAD, 0xB9, 0x77, 0x2F, 0xCA, 0xDB, 0x6B,
+	0xC8, 0x7C, 0x75, 0x33, 0x78, 0x2B, 0x5A, 0xD0, 0xA0, 0xF0, 0xCF, 0x8B, 0xFC, 0x5B, 0x0E, 0xA3,
+	0xE2, 0x6F, 0x0F, 0xD9, 0xFF, 0x00, 0xC2, 0x41, 0x67, 0x67, 0xA7, 0xE8, 0xE6, 0xF6, 0xEE, 0x1D,
+	0x37, 0x6C, 0x2B, 0x1F, 0xDA, 0x75, 0x5B, 0xA8, 0xED, 0x6D, 0xD7, 0x74, 0x8D, 0xE7, 0x5B, 0xED,
+	0x99, 0x9B, 0xCC, 0x93, 0x6A, 0xC7, 0xB9, 0x99, 0xBD, 0x83, 0xF6, 0x5E, 0xD6, 0x3C, 0x2B, 0x7F,
+	0xF0, 0xBD, 0x3C, 0x3B, 0xE1, 0x5D, 0x53, 0x50, 0xBC, 0x1E, 0x1F, 0xBF, 0x9B, 0x4F, 0xBF, 0x93,
+	0x52, 0x96, 0xC6, 0x47, 0x5B, 0x8F, 0x96, 0x66, 0x8F, 0x75, 0x83, 0x35, 0xAA, 0xAA, 0xAC, 0xCB,
+	0xB6, 0x38, 0x5B, 0x6C, 0x6B, 0xB6, 0x3F, 0x97, 0xCB, 0x65, 0x5A, 0xEA, 0xBC, 0xCC, 0x6A, 0xA9,
+	0xC6, 0x0A, 0x49, 0xFE, 0x77, 0xED, 0xDF, 0x6B, 0xAD, 0x0F, 0xCF, 0x4F, 0xF8, 0x2A, 0x87, 0xFC,
+	0x12, 0x87, 0xC3, 0x1F, 0x08, 0x7E, 0x1F, 0xEA, 0x9F, 0x1F, 0xBF, 0x65, 0xED, 0x07, 0xEC, 0x3A,
+	0x2E, 0x9F, 0x33, 0x5E, 0x78, 0x9B, 0xC2, 0xF6, 0xAB, 0xFB, 0xBB, 0x58, 0x5B, 0xEF, 0xDC, 0x5B,
+	0x2A, 0xFD, 0xD8, 0xD5, 0xBE, 0x66, 0x8F, 0xEE, 0xAA, 0xFC, 0xCB, 0xB7, 0x6E, 0xDA, 0xFC, 0xA0,
+	0xBE, 0xD4, 0xAD, 0x35, 0x4F, 0x88, 0x1A, 0x7C, 0x29, 0xB9, 0xE5, 0x8E, 0x59, 0x1D, 0x95, 0x5F,
+	0x73, 0x2F, 0xEE, 0xDA, 0xBF, 0xAA, 0xCD, 0x73, 0x47, 0xB0, 0xD7, 0x34, 0x7B, 0xAD, 0x1F, 0x55,
+	0xB3, 0x8E, 0xE2, 0xD6, 0xEA, 0xD6, 0x48, 0xAE, 0x2D, 0xE6, 0x5D, 0xCB, 0x24, 0x6C, 0xBB, 0x59,
+	0x59, 0x7F, 0xBA, 0xD5, 0xFC, 0xA0, 0xF8, 0xF2, 0xC7, 0x4A, 0xF0, 0x27, 0xED, 0x5D, 0xE2, 0x7F,
+	0x06, 0x69, 0x57, 0xFF, 0x00, 0x68, 0xB0, 0xD0, 0xFC, 0x41, 0xA9, 0x58, 0x5A, 0xB2, 0xCB, 0xF7,
+	0xA3, 0x86, 0xE2, 0x48, 0xE3, 0xDC, 0xDF, 0xEE, 0xC6, 0xB5, 0xF0, 0x5C, 0x41, 0xC3, 0xB8, 0x7A,
+	0x78, 0xC5, 0x8D, 0xA2, 0xAD, 0x74, 0xD3, 0x4B, 0x6B, 0xAE, 0xAB, 0xFC, 0xBF, 0xCC, 0xFA, 0x6C,
+	0x9F, 0x38, 0xAD, 0x53, 0x06, 0xF0, 0xF5, 0x35, 0xE5, 0x6B, 0x5E, 0xB6, 0x77, 0xDF, 0xE6, 0xB7,
+	0xFF, 0x00, 0x23, 0xF4, 0xE3, 0xF6, 0x21, 0xD7, 0xBE, 0x2E, 0xFC, 0x37, 0xFD, 0x85, 0xF5, 0xCF,
+	0x1E, 0x7C, 0x19, 0xF1, 0xCE, 0x97, 0xE0, 0xFD, 0x5B, 0x50, 0xF1, 0x44, 0x7A, 0x77, 0xF6, 0xF5,
+	0xF6, 0x9A, 0xB7, 0x31, 0xC7, 0xF2, 0xAB, 0x2C, 0x2C, 0xAC, 0xBF, 0x2E, 0xE5, 0x56, 0xDB, 0xBB,
+	0xF8, 0x9A, 0x9F, 0x7D, 0xFB, 0x48, 0x7F, 0xC1, 0x46, 0xBC, 0x32, 0x93, 0x5C, 0xDC, 0xFE, 0xDD,
+	0x5E, 0x11, 0x6F, 0x2F, 0x73, 0x7C, 0xBE, 0x1C, 0x85, 0xDA, 0x4F, 0xFB, 0xE9, 0xB7, 0x7F, 0xE8,
+	0x35, 0xE7, 0x1A, 0x5F, 0x8E, 0x2C, 0xF4, 0xBF, 0xF8, 0x24, 0x04, 0xDA, 0x6A, 0x6A, 0x52, 0x47,
+	0x25, 0xD7, 0xC6, 0x2F, 0xB3, 0xB4, 0x2C, 0xDF, 0x76, 0x38, 0xED, 0x77, 0x7C, 0xCB, 0xFD, 0xD5,
+	0xFB, 0xD5, 0xE5, 0x3F, 0xB2, 0x0D, 0x97, 0x84, 0xBE, 0x25, 0x7C, 0x5A, 0x86, 0xDB, 0xC5, 0xBA,
+	0x8A, 0xB6, 0x95, 0x0C, 0xB1, 0xAC, 0xAB, 0x0B, 0x2E, 0xD6, 0x55, 0x92, 0x3F, 0x97, 0x77, 0xCB,
+	0xF7, 0xAB, 0xC9, 0x96, 0x75, 0x5B, 0x2F, 0xA9, 0x47, 0x0D, 0x1A, 0x6A, 0x51, 0x71, 0xE6, 0x6D,
+	0xF4, 0x77, 0x6B, 0xB3, 0xEC, 0xBE, 0xF3, 0xAA, 0x38, 0x0A, 0x55, 0x30, 0xF3, 0xC4, 0xCA, 0x76,
+	0x7C, 0xCD, 0x25, 0x65, 0xAD, 0x8E, 0xDF, 0xE2, 0x37, 0xFC, 0x16, 0x33, 0xF6, 0xB7, 0xF8, 0x67,
+	0xAA, 0x3E, 0x95, 0xE2, 0xAF, 0xDB, 0x4A, 0xD7, 0xED, 0x11, 0xC5, 0xB9, 0xA3, 0xB1, 0xF0, 0x5C,
+	0x6D, 0xFF, 0x00, 0x8F, 0x6D, 0xAE, 0x41, 0xBF, 0xE0, 0xBC, 0x9F, 0xB4, 0x8B, 0x47, 0xE7, 0x7F,
+	0xC3, 0x65, 0xDC, 0x3A, 0xED, 0xF9, 0x97, 0xFE, 0x10, 0x15, 0x5D, 0xBF, 0xF8, 0xED, 0x7C, 0xDB,
+	0xFF, 0x00, 0x05, 0x50, 0xD3, 0xFE, 0x17, 0x78, 0x1F, 0xF6, 0xA4, 0xF1, 0x0E, 0x95, 0xF0, 0xC6,
+	0x65, 0x6D, 0x2A, 0x16, 0x8D, 0xAC, 0xD5, 0x9B, 0x73, 0x49, 0x1F, 0x96, 0xBF, 0x33, 0x7F, 0xE3,
+	0xD5, 0xF2, 0xF6, 0x97, 0xE2, 0xED, 0x35, 0xA1, 0xBC, 0x9B, 0x62, 0xFE, 0xEE, 0xDF, 0xE5, 0x56,
+	0x55, 0xF9, 0xBF, 0x78, 0xBF, 0xE7, 0xFE, 0xFA, 0xAF, 0xD1, 0xB0, 0xD8, 0x5A, 0x38, 0x8C, 0x34,
+	0x67, 0xCB, 0xBA, 0x4F, 0x44, 0xBB, 0x2F, 0x23, 0xE5, 0x6A, 0xE3, 0x6A, 0xD3, 0xA8, 0xE3, 0x75,
+	0xA7, 0x92, 0x3F, 0x4B, 0x21, 0xFF, 0x00, 0x82, 0xF2, 0x7E, 0xD2, 0x77, 0x1B, 0x61, 0x9B, 0xF6,
+	0xC6, 0xBA, 0x4F, 0xE2, 0x96, 0x4F, 0xF8, 0x42, 0x17, 0xE5, 0xFF, 0x00, 0xC7, 0x7F, 0xD9, 0xFF,
+	0x00, 0xC7, 0xA9, 0x26, 0xFF, 0x00, 0x82, 0xEB, 0x7E, 0xD1, 0xB7, 0x0A, 0xE3, 0xFE, 0x1B, 0x27,
+	0x50, 0x55, 0xDD, 0xF2, 0xF9, 0x7E, 0x05, 0x5F, 0xBB, 0xFC, 0x3F, 0xC3, 0x5F, 0x9A, 0x3A, 0x5F,
+	0x8C, 0xA1, 0x92, 0xFA, 0x38, 0xA1, 0x45, 0x67, 0x5D, 0xDF, 0xC3, 0xBB, 0xE5, 0xFF, 0x00, 0x7B,
+	0xFC, 0xFD, 0xDA, 0xAC, 0xBE, 0x2C, 0xD6, 0x35, 0xED, 0x42, 0x3D, 0x1F, 0x41, 0xB3, 0x92, 0xE2,
+	0xE2, 0xE3, 0xE5, 0x8A, 0x18, 0x7E, 0xF3, 0x7C, 0xBB, 0xAA, 0xFF, 0x00, 0xB3, 0x70, 0xF7, 0xF8,
+	0x7F, 0x2F, 0xF2, 0x33, 0xFA, 0xFE, 0x23, 0x9B, 0x7F, 0xC0, 0xFD, 0x2F, 0x6F, 0xF8, 0x2E, 0x4F,
+	0xED, 0x17, 0xE6, 0x3B, 0xCD, 0xFB, 0x64, 0xEA, 0xC8, 0x9B, 0x77, 0x7C, 0xBE, 0x05, 0xFF, 0x00,
+	0xBE, 0xBF, 0x86, 0x9D, 0x6F, 0xFF, 0x00, 0x05, 0xBC, 0xFD, 0xA0, 0x66, 0x99, 0x5E, 0xE7, 0xF6,
+	0xD2, 0xD5, 0x17, 0x77, 0xFA, 0xBD, 0xDE, 0x0D, 0x5F, 0xFE, 0x26, 0xBF, 0x31, 0xD7, 0x58, 0xF1,
+	0x0A, 0xD8, 0xC3, 0xA8, 0x25, 0xCD, 0xBF, 0xFA, 0x46, 0xD6, 0xF2, 0xE3, 0xB8, 0x56, 0xDD, 0xFD,
+	0xD6, 0xFF, 0x00, 0x66, 0x8D, 0x33, 0xC7, 0x17, 0x90, 0xCC, 0xD0, 0xDF, 0xA4, 0x6A, 0xD1, 0xB6,
+	0xDF, 0xBD, 0xFC, 0x5F, 0xC5, 0xFF, 0x00, 0x02, 0xFF, 0x00, 0xE2, 0xAA, 0xFF, 0x00, 0xB2, 0xF0,
+	0xB2, 0x8F, 0xC0, 0xBE, 0x56, 0xFF, 0x00, 0x21, 0xAC, 0xC3, 0x11, 0x1D, 0x5B, 0x3F, 0x4D, 0xBF,
+	0xE1, 0xF7, 0x5F, 0x1D, 0x59, 0x7C, 0xE9, 0xBF, 0x6E, 0x1B, 0xE8, 0xDB, 0xFB, 0xBF, 0xF0, 0x87,
+	0xFC, 0xBF, 0x7B, 0xF8, 0x7E, 0x5A, 0x6C, 0x9F, 0xF0, 0x5B, 0x6F, 0x8D, 0x96, 0xF6, 0xDE, 0x77,
+	0xFC, 0x37, 0x55, 0xE4, 0x8E, 0xBF, 0x37, 0x92, 0xDE, 0x0F, 0x68, 0xF7, 0x7F, 0xC0, 0xB6, 0xD7,
+	0xE6, 0xEC, 0x7E, 0x32, 0x59, 0xB4, 0x7B, 0xCD, 0x4A, 0xCF, 0x4D, 0x8E, 0xE2, 0x4B, 0x1B, 0x56,
+	0xB8, 0xBA, 0x66, 0x6D, 0xBB, 0x55, 0x5B, 0xE6, 0xFF, 0x00, 0xD9, 0x6B, 0xA6, 0xFD, 0x97, 0xFE,
+	0x16, 0xFC, 0x48, 0xFD, 0xAC, 0x3C, 0x54, 0xBA, 0x3F, 0x83, 0xF4, 0x1D, 0x3F, 0x4B, 0xD3, 0x61,
+	0x9A, 0x34, 0xBF, 0xD7, 0x2F, 0x9B, 0x6C, 0x16, 0xBB, 0x99, 0x55, 0x77, 0x7F, 0x7B, 0xE6, 0xDB,
+	0x4A, 0x59, 0x66, 0x06, 0x10, 0xE6, 0x71, 0x49, 0x7A, 0x2F, 0xF2, 0x2B, 0xEB, 0xD8, 0x99, 0x7C,
+	0x32, 0xFC, 0x8F, 0xBA, 0x35, 0xAF, 0xF8, 0x2E, 0x37, 0xC7, 0xEB, 0x52, 0xAF, 0x67, 0xFB, 0x63,
+	0x6A, 0x97, 0x3F, 0x2F, 0xCC, 0xAB, 0xE1, 0x7D, 0xBF, 0xFB, 0x2D, 0x73, 0xF3, 0x7F, 0xC1, 0x79,
+	0xFF, 0x00, 0x68, 0xA8, 0xF6, 0xA4, 0xFF, 0x00, 0xB4, 0xE6, 0xB8, 0xDF, 0x37, 0xCC, 0xBF, 0xD8,
+	0x31, 0xFC, 0xB5, 0xF1, 0xCF, 0x8C, 0xBC, 0x37, 0xE0, 0x2F, 0x86, 0xFF, 0x00, 0x12, 0x35, 0xCF,
+	0x86, 0xFE, 0x27, 0xF1, 0xCC, 0x6D, 0x75, 0xA0, 0xEA, 0xD7, 0x16, 0x52, 0xCD, 0x6F, 0xA5, 0xB4,
+	0x91, 0xC8, 0xD1, 0xFC, 0xBB, 0x97, 0xE6, 0xDD, 0xFC, 0x35, 0x89, 0x6F, 0xF0, 0xF7, 0xE0, 0xE6,
+	0xB5, 0x33, 0xFD, 0x83, 0xE3, 0x35, 0xAC, 0x2C, 0xDB, 0x9B, 0xCB, 0x9B, 0x4B, 0x99, 0x77, 0x53,
+	0x8E, 0x55, 0x80, 0xFB, 0x50, 0xFC, 0x3F, 0xE0, 0x0B, 0xFB, 0x43, 0x15, 0x09, 0x59, 0x48, 0xFB,
+	0x96, 0xD7, 0xFE, 0x0B, 0xB1, 0xF1, 0xD2, 0xE1, 0x95, 0x2E, 0x7F, 0x6A, 0x5D, 0x72, 0xDB, 0xFE,
+	0x9A, 0x2E, 0x82, 0xAD, 0xBB, 0xFB, 0xDF, 0x2E, 0xD6, 0xAF, 0x44, 0xF8, 0x03, 0xFF, 0x00, 0x05,
+	0x3E, 0xF8, 0xF7, 0xFB, 0x42, 0x78, 0xF2, 0xD7, 0xC0, 0xDE, 0x1B, 0xFD, 0xBE, 0x6E, 0x34, 0xDB,
+	0xFB, 0xCB, 0x85, 0x8A, 0xCE, 0x3B, 0xED, 0x07, 0xCB, 0x59, 0x19, 0x9B, 0x6A, 0xAF, 0xDD, 0xF9,
+	0x9A, 0xBF, 0x35, 0xF5, 0x8F, 0x84, 0x3E, 0x00, 0xD2, 0x62, 0x85, 0xEF, 0x3E, 0x39, 0x78, 0x75,
+	0x56, 0x6F, 0xBB, 0x1B, 0x45, 0x71, 0xF2, 0xED, 0xDB, 0xF7, 0xBE, 0x5A, 0xE8, 0xFC, 0x03, 0xA7,
+	0xF8, 0x1B, 0xC0, 0x1A, 0xA5, 0xB7, 0x8B, 0xF4, 0x7F, 0x8F, 0xDE, 0x13, 0xB5, 0xD4, 0x2C, 0x65,
+	0x5B, 0x8B, 0x09, 0x21, 0xB7, 0x9A, 0x59, 0x16, 0x45, 0x6D, 0xCA, 0xDF, 0xC3, 0xF3, 0x7C, 0xB5,
+	0x32, 0xCA, 0x72, 0xFA, 0x77, 0x70, 0x82, 0xBF, 0xA2, 0xFF, 0x00, 0x22, 0xA5, 0x8E, 0xC6, 0x4A,
+	0x37, 0x8C, 0xBE, 0xEF, 0xF8, 0x37, 0x3F, 0x6F, 0x2E, 0x7E, 0x13, 0xFF, 0x00, 0xC1, 0x4E, 0x26,
+	0x55, 0xFF, 0x00, 0x8C, 0xF9, 0x8D, 0x56, 0x45, 0xFB, 0xAB, 0xA3, 0x47, 0xB9, 0x6B, 0xEB, 0xDF,
+	0xF8, 0x26, 0x87, 0xC4, 0x66, 0xF0, 0x3F, 0x84, 0xEE, 0xBE, 0x18, 0xFE, 0xD2, 0xFF, 0x00, 0xB4,
+	0x06, 0x97, 0xAF, 0xFC, 0x44, 0xB8, 0xD4, 0xA4, 0x9E, 0xDE, 0xE2, 0xF9, 0x56, 0x09, 0x64, 0xB3,
+	0xDA, 0xAB, 0x1E, 0xCD, 0xDF, 0x2F, 0xDE, 0xDD, 0xF2, 0xAD, 0x7E, 0x67, 0xFF, 0x00, 0xC1, 0x31,
+	0xFE, 0x2C, 0x7E, 0xD9, 0xFF, 0x00, 0x1A, 0x61, 0x8F, 0xE2, 0xBF, 0xC4, 0xEF, 0x8B, 0x5A, 0x6E,
+	0xBD, 0xE1, 0x19, 0xA5, 0x92, 0x2F, 0x2D, 0xAC, 0x3C, 0xA9, 0x24, 0xDA, 0xBF, 0x2C, 0x91, 0xB2,
+	0xFF, 0x00, 0xB5, 0xB7, 0xE5, 0x6A, 0xE4, 0x7E, 0x3B, 0x7C, 0x6A, 0xF8, 0xAF, 0x67, 0xFF, 0x00,
+	0x05, 0x6A, 0xF0, 0xFE, 0x83, 0xF0, 0xD3, 0x5F, 0x58, 0xDF, 0xFB, 0x26, 0xDE, 0xDE, 0x5B, 0x7B,
+	0xAF, 0x9A, 0x38, 0xE3, 0x69, 0x1B, 0x73, 0x7F, 0xBD, 0xB6, 0x8A, 0x74, 0xF0, 0xF8, 0x4E, 0x6A,
+	0xD0, 0x82, 0xBC, 0x57, 0x4D, 0x2F, 0xD3, 0xB7, 0xE8, 0x63, 0x52, 0xB6, 0x23, 0x14, 0xBD, 0x9C,
+	0xE5, 0x75, 0xBF, 0xDC, 0x7F, 0x45, 0x14, 0x56, 0x2F, 0xC3, 0xE5, 0xB8, 0x4F, 0x01, 0x68, 0x89,
+	0xAA, 0x13, 0xF6, 0xA1, 0xA4, 0xDB, 0x7D, 0xA3, 0x77, 0x5D, 0xFE, 0x52, 0xEE, 0xFD, 0x68, 0xAF,
+	0xA0, 0x3C, 0xB3, 0x6A, 0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02,
+	0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0xB0, 0xFC, 0x7D, 0xE3, 0xDF, 0x0A, 0x7C, 0x33,
+	0xF0, 0x8D, 0xF7, 0x8E, 0x7C, 0x6D, 0xAA, 0x47, 0x63, 0xA5, 0x69, 0xB0, 0xB4, 0xB7, 0xD7, 0x93,
+	0x7D, 0xC8, 0x63, 0xFE, 0xF3, 0x7B, 0x56, 0xE5, 0x73, 0x3F, 0x17, 0xBC, 0x11, 0xA7, 0xFC, 0x48,
+	0xF8, 0x5B, 0xE2, 0x0F, 0x00, 0x6A, 0x50, 0x2C, 0x90, 0xEB, 0x1A, 0x3D, 0xC5, 0xA3, 0xA3, 0x7F,
+	0x16, 0xE8, 0xD9, 0x6B, 0x1C, 0x44, 0xAA, 0xC7, 0x0F, 0x37, 0x4F, 0xE2, 0x49, 0xDA, 0xFD, 0xFA,
+	0x01, 0xF9, 0xB3, 0xF1, 0x03, 0x5E, 0xF8, 0x21, 0xFF, 0x00, 0x05, 0x3C, 0xF1, 0xBD, 0xEF, 0xC6,
+	0xAF, 0x0F, 0x78, 0x32, 0xDE, 0xE6, 0xC3, 0x4F, 0x95, 0xB4, 0xEB, 0x39, 0xB5, 0x26, 0x6F, 0x32,
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+	0xF6, 0xDC, 0xED, 0xF2, 0x5F, 0x73, 0x6D, 0xFB, 0xB5, 0x93, 0xA9, 0x78, 0x46, 0x1D, 0x43, 0xC5,
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+	0xA3, 0xB5, 0xBA, 0xF3, 0x3F, 0x8A, 0x78, 0xBE, 0xEC, 0x8C, 0xBF, 0xC3, 0xBB, 0xEE, 0xEE, 0x6F,
+	0xEF, 0x57, 0xC4, 0xBE, 0x13, 0xFF, 0x00, 0x82, 0xE0, 0x69, 0x57, 0x9F, 0xE8, 0xDE, 0x24, 0xF8,
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+	0xC1, 0x6D, 0xBC, 0x17, 0x66, 0xBB, 0x2D, 0xBE, 0x09, 0xEA, 0xCF, 0x27, 0xF7, 0x7E, 0xD9, 0x0E,
+	0xDF, 0xFD, 0x0A, 0xBE, 0x82, 0x39, 0x96, 0x5F, 0x38, 0xFB, 0xB5, 0x13, 0x38, 0x23, 0x83, 0xC6,
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+	0xFC, 0xAB, 0x5F, 0x98, 0xFF, 0x00, 0x15, 0x3F, 0xE0, 0xBF, 0xDE, 0x21, 0xD2, 0xAC, 0xEE, 0x13,
+	0xC1, 0xFF, 0x00, 0x06, 0x96, 0xDD, 0xD7, 0xE5, 0xFF, 0x00, 0x4C, 0xBC, 0x56, 0x6F, 0xF7, 0xBE,
+	0x5A, 0xF8, 0xDF, 0xE3, 0xB7, 0xFC, 0x17, 0x03, 0xF6, 0xC7, 0xF8, 0xAC, 0xD3, 0x68, 0x9E, 0x1E,
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+	0xAB, 0x54, 0x78, 0xA3, 0x66, 0xF3, 0x3C, 0xCD, 0xD7, 0x52, 0x6D, 0xFE, 0x2F, 0x95, 0xBF, 0xDA,
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+	0x33, 0x79, 0xD1, 0xFD, 0xE6, 0xFF, 0x00, 0xD9, 0xAB, 0x93, 0xF8, 0x6B, 0xE1, 0x7B, 0x6F, 0x15,
+	0x7E, 0xD5, 0x17, 0xFA, 0x27, 0x93, 0x32, 0x42, 0xDA, 0xB5, 0xE3, 0xEE, 0x8F, 0xEF, 0x37, 0xFA,
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+	0x45, 0x88, 0xC1, 0xE2, 0x27, 0x74, 0x9C, 0x79, 0x2F, 0x6E, 0xCA, 0xEE, 0xEF, 0xD4, 0xF7, 0x32,
+	0xBC, 0xB6, 0x8E, 0x22, 0x8B, 0x4D, 0xD9, 0xA6, 0xB5, 0xEE, 0xEC, 0xED, 0xF9, 0x1A, 0x8B, 0xE2,
+	0x4F, 0x1E, 0x78, 0x5F, 0xF6, 0x4D, 0xF1, 0x0F, 0xC3, 0xDD, 0x51, 0xEE, 0x21, 0xB3, 0xB5, 0xD5,
+	0x2E, 0x35, 0x2B, 0x3F, 0x32, 0x5F, 0x95, 0xA4, 0x93, 0xCB, 0x8D, 0x64, 0x55, 0xFE, 0x2F, 0xF5,
+	0x6D, 0xFF, 0x00, 0x8F, 0x57, 0x96, 0xFE, 0xCB, 0x5F, 0x12, 0xEF, 0xED, 0xE1, 0xBF, 0xD0, 0x66,
+	0xB9, 0x99, 0x66, 0xBC, 0xD4, 0x21, 0x89, 0xA6, 0x66, 0xF9, 0xB6, 0xEE, 0xF9, 0xBF, 0xF1, 0xDA,
+	0xEF, 0x7E, 0x3C, 0x35, 0xB7, 0x84, 0x7E, 0x1C, 0xF8, 0xC2, 0xC3, 0xCE, 0x65, 0x99, 0x6E, 0xA1,
+	0x55, 0x91, 0x9B, 0xE6, 0xDA, 0xD2, 0x2D, 0x78, 0x57, 0xEC, 0xC3, 0x33, 0xC9, 0xF1, 0x42, 0xDE,
+	0xEA, 0xF1, 0xE4, 0xDA, 0xB7, 0x4C, 0xF2, 0xFC, 0xDB, 0x97, 0xE5, 0xFF, 0x00, 0x2C, 0xBB, 0xAB,
+	0x97, 0x2A, 0x8F, 0xD7, 0xF2, 0xFC, 0x4E, 0x22, 0xDD, 0x62, 0xD7, 0xCA, 0x31, 0x7F, 0xA9, 0xD7,
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+	0xB7, 0xC0, 0x5F, 0x8A, 0xFF, 0x00, 0xF0, 0x97, 0x2F, 0x88, 0x6C, 0xFC, 0x3D, 0x71, 0x71, 0x67,
+	0x75, 0xA6, 0xDB, 0xAA, 0xDC, 0x46, 0xDB, 0x97, 0x76, 0xDF, 0xF7, 0xBE, 0x5A, 0xF9, 0x67, 0x5A,
+	0xB0, 0xD5, 0x7C, 0x17, 0x75, 0x73, 0xA0, 0xEB, 0x16, 0x72, 0x5A, 0xDE, 0x79, 0x4B, 0xFB, 0x99,
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+	0xBD, 0x86, 0x9B, 0x73, 0xBF, 0xCE, 0xB2, 0x85, 0xD5, 0xB7, 0xFD, 0xE6, 0xF2, 0xD7, 0xFF, 0x00,
+	0x8A, 0xAF, 0xCF, 0x7F, 0xDA, 0x5A, 0x4D, 0xDE, 0x2E, 0xB0, 0x85, 0xD1, 0x9A, 0x48, 0xEC, 0x36,
+	0xDC, 0x6E, 0xFE, 0x16, 0x59, 0x3E, 0xEF, 0xFB, 0x3F, 0xC3, 0xFF, 0x00, 0x8E, 0xD7, 0xD9, 0x64,
+	0x98, 0xCA, 0x98, 0x8A, 0x30, 0x84, 0x92, 0xDB, 0xA1, 0xF3, 0x18, 0xEC, 0x3C, 0x69, 0xDE, 0x5E,
+	0x67, 0x0F, 0xA4, 0xF8, 0x9B, 0x52, 0xD1, 0x66, 0x77, 0xB3, 0xB9, 0xDA, 0xDB, 0x76, 0xD7, 0x71,
+	0xFB, 0x36, 0xF8, 0x87, 0x47, 0x8F, 0xE2, 0xE4, 0x3F, 0xF0, 0x92, 0x78, 0xAA, 0x3D, 0x26, 0x1B,
+	0xAB, 0x0B, 0xC8, 0x17, 0x50, 0x9A, 0x26, 0x65, 0x86, 0x49, 0x2D, 0xD9, 0x55, 0xAB, 0xCC, 0x66,
+	0xFF, 0x00, 0x47, 0x6D, 0x9F, 0x79, 0x3F, 0xBC, 0xD5, 0x5F, 0xED, 0x05, 0x59, 0x53, 0x3B, 0x5B,
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+	0x2F, 0xD9, 0xDF, 0xC1, 0xFE, 0x09, 0xF0, 0x1D, 0xBD, 0xCE, 0x8F, 0xF1, 0xCB, 0xC3, 0x37, 0x9A,
+	0x84, 0x2B, 0xB6, 0x5B, 0x3F, 0x33, 0xCB, 0x69, 0x37, 0x7F, 0xB5, 0xFE, 0xCD, 0x7C, 0xFB, 0xAC,
+	0x6A, 0x1B, 0x75, 0x09, 0x11, 0x66, 0x8D, 0xDD, 0x5B, 0xFD, 0x64, 0x6D, 0xB9, 0x59, 0xBF, 0x8B,
+	0x6F, 0xFD, 0xF3, 0x58, 0xB2, 0x6A, 0x13, 0x7C, 0xDB, 0xDD, 0xB6, 0xB5, 0x46, 0xD3, 0x7C, 0xDB,
+	0xFF, 0x00, 0xBB, 0xF7, 0x6A, 0x29, 0xD2, 0x94, 0x57, 0xBD, 0x2B, 0xFC, 0x92, 0xFC, 0x82, 0xA4,
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+	0x76, 0xD1, 0xA1, 0xDB, 0x1A, 0xFD, 0xE6, 0xFF, 0x00, 0x4A, 0x8F, 0x77, 0xCB, 0xFE, 0xEE, 0xEA,
+	0xE9, 0xFE, 0x06, 0xFE, 0xD6, 0xDE, 0x36, 0xF8, 0x03, 0xF0, 0xFE, 0xFF, 0x00, 0xC1, 0xFE, 0x0F,
+	0xF0, 0xF6, 0xCB, 0x9B, 0xCD, 0x46, 0x1B, 0xAF, 0xB7, 0x4D, 0xBB, 0xE5, 0xF2, 0xDB, 0x72, 0xFE,
+	0xED, 0x7E, 0xF7, 0xCD, 0xB5, 0xAB, 0xC7, 0x34, 0x9D, 0x6B, 0x56, 0xD1, 0x6E, 0xA3, 0xBF, 0xD3,
+	0x6F, 0x24, 0xB7, 0x91, 0x7E, 0xEB, 0x2F, 0xF0, 0xFF, 0x00, 0xF1, 0x55, 0xD2, 0x5A, 0xFC, 0x72,
+	0xF8, 0x9D, 0x6E, 0xAC, 0xFF, 0x00, 0xDB, 0xCA, 0xEA, 0xBF, 0x37, 0xEF, 0x2D, 0xE3, 0x6F, 0xFD,
+	0x96, 0x95, 0x4A, 0x2E, 0x4A, 0xDC, 0xA9, 0xAB, 0xDF, 0x5B, 0xEF, 0xF7, 0x1A, 0x52, 0xA8, 0xA9,
+	0xAB, 0xA7, 0x66, 0x2F, 0x8C, 0x3E, 0x21, 0x5E, 0x78, 0xC7, 0xC4, 0x17, 0xDE, 0x2B, 0xD5, 0x61,
+	0x9A, 0x4D, 0x43, 0x50, 0xBA, 0x92, 0xE2, 0xF2, 0x66, 0x6F, 0xBD, 0x33, 0x36, 0xE6, 0x6F, 0xFB,
+	0xEA, 0xB2, 0x21, 0xF1, 0x01, 0x58, 0xFC, 0xE7, 0xF3, 0x06, 0xDF, 0x97, 0xE5, 0x6A, 0xE8, 0x23,
+	0xFD, 0xA1, 0x3C, 0x7F, 0x26, 0xE4, 0x74, 0xD3, 0x5D, 0x5B, 0xE5, 0xDA, 0xDA, 0x5C, 0x35, 0x6A,
+	0xCF, 0xE3, 0xC6, 0xBD, 0x6F, 0x70, 0x93, 0x4D, 0xE1, 0x5F, 0x0E, 0xDC, 0x3F, 0xFD, 0x34, 0xD2,
+	0x63, 0x66, 0x6A, 0x5F, 0xBE, 0xEB, 0x1F, 0xC7, 0xFE, 0x01, 0x1F, 0xBB, 0x94, 0xAE, 0xDF, 0xE0,
+	0x72, 0x77, 0xDA, 0x87, 0xF6, 0x93, 0x7F, 0xC7, 0xCF, 0xF0, 0xFC, 0xAA, 0xCA, 0xD5, 0xA1, 0xE1,
+	0xFF, 0x00, 0x0A, 0xF8, 0x87, 0x52, 0x96, 0x33, 0xA6, 0xE8, 0xF3, 0x4C, 0xCC, 0xDF, 0x2F, 0x97,
+	0x6E, 0xCD, 0xFD, 0xDF, 0xEE, 0xD7, 0x5D, 0x6F, 0xF1, 0xCA, 0xDA, 0xF0, 0x2F, 0xDB, 0x3E, 0x1B,
+	0xF8, 0x5D, 0xA4, 0xFB, 0xBF, 0xBB, 0xD3, 0x59, 0x7F, 0xF4, 0x16, 0xFF, 0x00, 0x3B, 0xAB, 0xE9,
+	0x5F, 0xD8, 0x17, 0xE1, 0xFE, 0x89, 0xFB, 0x51, 0xFC, 0x60, 0xB5, 0xF8, 0x6F, 0xE2, 0x1F, 0x87,
+	0xED, 0xE1, 0xDB, 0x59, 0x2D, 0xE4, 0x95, 0xAF, 0xAC, 0x7C, 0xE8, 0xB6, 0xAA, 0xAF, 0xF0, 0xEE,
+	0x6D, 0xB5, 0x12, 0xAD, 0x2A, 0x71, 0xBC, 0xE3, 0x65, 0xEA, 0x8D, 0x79, 0x63, 0x24, 0xB9, 0x59,
+	0xFA, 0x37, 0xFF, 0x00, 0x04, 0xC1, 0xD3, 0xAC, 0xFC, 0x07, 0xFB, 0x15, 0xF8, 0x53, 0x41, 0xB9,
+	0x7F, 0x26, 0xE7, 0xEC, 0xB2, 0x4D, 0x71, 0x0B, 0x2B, 0x2B, 0x6E, 0x69, 0x1A, 0xBC, 0x0B, 0xE0,
+	0x7D, 0xE3, 0xFC, 0x50, 0xFF, 0x00, 0x82, 0xD2, 0x6A, 0x13, 0x6F, 0x66, 0x4B, 0x39, 0x63, 0xB7,
+	0x8B, 0x6F, 0xCD, 0xFC, 0x2B, 0xFF, 0x00, 0xB3, 0x35, 0x7D, 0x4B, 0xE1, 0xBF, 0x84, 0x36, 0xFF,
+	0x00, 0x04, 0xFC, 0x37, 0x6D, 0xA3, 0xA7, 0xC4, 0x8F, 0x10, 0x6B, 0x90, 0xE9, 0x3A, 0x7C, 0x96,
+	0x7A, 0x4C, 0x3A, 0xD5, 0xD2, 0xB4, 0x5A, 0x7C, 0x2C, 0xDB, 0x9A, 0x38, 0xD5, 0x55, 0x57, 0xE6,
+	0x65, 0x5F, 0x99, 0xBE, 0x6F, 0x96, 0xBE, 0x5F, 0xFF, 0x00, 0x82, 0x38, 0xD9, 0xDB, 0x7C, 0x4E,
+	0xFF, 0x00, 0x82, 0xB4, 0x6B, 0x9A, 0xC3, 0xF9, 0x8C, 0xDF, 0xF0, 0x98, 0x46, 0xAC, 0xDF, 0x79,
+	0x7C, 0xBF, 0xB4, 0x46, 0xBF, 0xF7, 0xCF, 0xCB, 0xFF, 0x00, 0xA0, 0xD7, 0x95, 0x53, 0x97, 0xEA,
+	0xF2, 0x8C, 0x6E, 0xD3, 0x71, 0x5F, 0xF9, 0x31, 0xD4, 0xA3, 0x2A, 0x74, 0x5B, 0x95, 0xAF, 0x6F,
+	0xF8, 0x3E, 0x47, 0xF4, 0xA9, 0x0C, 0x6B, 0x0C, 0x4B, 0x14, 0x51, 0xE1, 0x54, 0x60, 0x0A, 0x2A,
+	0x4A, 0x2B, 0xE8, 0x4F, 0x24, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A,
+	0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0xB3, 0x75, 0xCF, 0x11, 0xE9, 0xDA, 0x0A, 0x2B, 0xDF,
+	0xB3, 0x7C, 0xDF, 0xDD, 0xAC, 0x71, 0x18, 0x8A, 0x18, 0x5A, 0x2E, 0xAD, 0x69, 0x28, 0xC5, 0x6E,
+	0xDB, 0xB2, 0x45, 0x46, 0x32, 0xA9, 0x25, 0x18, 0xAB, 0xB3, 0x4A, 0x8A, 0xE4, 0x62, 0xF8, 0xBD,
+	0xE1, 0x49, 0x84, 0x8D, 0x12, 0xDD, 0x30, 0x85, 0xB6, 0xBB, 0x79, 0x4B, 0xFF, 0x00, 0xC5, 0x54,
+	0xDF, 0xF0, 0xB4, 0x3C, 0x3D, 0xFF, 0x00, 0x3C, 0xAE, 0x3F, 0xEF, 0x85, 0xFF, 0x00, 0xE2, 0xAB,
+	0xC6, 0xFF, 0x00, 0x5A, 0x78, 0x77, 0xFE, 0x82, 0xA1, 0xFF, 0x00, 0x81, 0x23, 0xA3, 0xEA, 0x58,
+	0xCF, 0xE4, 0x67, 0xE4, 0x17, 0xC7, 0x0F, 0x87, 0x3E, 0x21, 0xFD, 0x9B, 0xFF, 0x00, 0xE0, 0xB5,
+	0x9A, 0xF4, 0xDA, 0x3E, 0x89, 0x78, 0x9A, 0x2F, 0x8C, 0xB4, 0xF5, 0xBC, 0xF3, 0xA1, 0xB7, 0x6F,
+	0x29, 0xA4, 0x6D, 0xBF, 0x79, 0xBE, 0xEA, 0xFD, 0xE9, 0x1A, 0xBD, 0xDF, 0xF6, 0xC0, 0xF8, 0xD4,
+	0x9F, 0x09, 0xFE, 0x08, 0xDC, 0xEB, 0x69, 0x2C, 0x69, 0x73, 0x75, 0x16, 0xC8, 0x99, 0x9B, 0xEE,
+	0xEE, 0x5F, 0xE1, 0xAF, 0xBA, 0xBC, 0x43, 0x77, 0xF0, 0xB7, 0xC4, 0xD3, 0xBD, 0xDE, 0xB9, 0xE0,
+	0xE8, 0x6F, 0x2E, 0x19, 0x15, 0x5A, 0x69, 0xA1, 0x5D, 0xEC, 0xAB, 0xF7, 0x57, 0x77, 0xDE, 0xAF,
+	0x97, 0xBF, 0x6F, 0xFF, 0x00, 0xF8, 0x27, 0xB7, 0x81, 0x3F, 0x6C, 0xDF, 0x0F, 0x69, 0xBA, 0x27,
+	0x84, 0xFC, 0x4F, 0xFF, 0x00, 0x08, 0x8B, 0x59, 0xBE, 0xE9, 0x66, 0x5B, 0x76, 0x9F, 0xCC, 0xFF,
+	0x00, 0x75, 0x77, 0x57, 0xC6, 0x66, 0xD9, 0xB6, 0x5F, 0x47, 0x24, 0xAB, 0x87, 0xC0, 0xE2, 0xA1,
+	0x39, 0xC9, 0xB4, 0xB5, 0xB3, 0x4A, 0x52, 0xF9, 0xDF, 0x95, 0x3E, 0xEA, 0xF6, 0xE9, 0x73, 0xD8,
+	0xC2, 0x46, 0x55, 0x31, 0x54, 0x9E, 0x22, 0x0D, 0x46, 0x36, 0xBB, 0xEF, 0x6D, 0xBF, 0x43, 0xF1,
+	0x93, 0xE2, 0x97, 0xC6, 0x47, 0xBE, 0xB3, 0xFB, 0x34, 0x3A, 0xC3, 0x3F, 0xDB, 0xA5, 0xFF, 0x00,
+	0x48, 0x6F, 0xF9, 0xE7, 0xBB, 0xEF, 0x57, 0xAF, 0x78, 0x77, 0xF6, 0x86, 0xF0, 0xC7, 0xC1, 0xDF,
+	0x08, 0xE9, 0xBA, 0x97, 0xC3, 0x4F, 0x18, 0x69, 0x71, 0xC7, 0xAB, 0x58, 0x43, 0x65, 0xAF, 0x79,
+	0xD2, 0xAA, 0xC9, 0x0F, 0xCC, 0xBE, 0x64, 0x9F, 0xFE, 0xD5, 0x7B, 0x64, 0xDF, 0xF0, 0x6C, 0xAD,
+	0x86, 0xA9, 0x79, 0x1F, 0xF6, 0x97, 0xED, 0x99, 0xA9, 0x43, 0x6E, 0xDB, 0xBE, 0xD0, 0xB6, 0xBE,
+	0x1F, 0x56, 0x65, 0xFF, 0x00, 0x77, 0x73, 0x56, 0x36, 0xB9, 0xFF, 0x00, 0x06, 0xB2, 0x7F, 0x6C,
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+	0x36, 0x81, 0xE3, 0x1B, 0x89, 0xAE, 0x24, 0x7D, 0x63, 0x4F, 0x9A, 0xFE, 0xD6, 0xFA, 0xDD, 0x76,
+	0xAA, 0xC7, 0x27, 0x98, 0xD2, 0x5B, 0xCB, 0x1F, 0xF1, 0x7C, 0xD0, 0x6E, 0x56, 0x5F, 0xBB, 0xFD,
+	0xDF, 0xE2, 0xAF, 0xCD, 0xCF, 0x07, 0xF8, 0x81, 0xF4, 0xBF, 0x1D, 0x69, 0xD7, 0x73, 0x3E, 0xDF,
+	0xB3, 0xDD, 0x2B, 0xFC, 0xAD, 0xF2, 0xB7, 0xF1, 0x7D, 0xDA, 0xFD, 0xA8, 0xF1, 0xFC, 0xC5, 0xAD,
+	0x3C, 0x07, 0xAF, 0x24, 0x2B, 0xF2, 0xE9, 0x37, 0x56, 0xEB, 0xB5, 0x77, 0x6E, 0xDB, 0x24, 0x9F,
+	0xFC, 0x72, 0xBF, 0x2A, 0xF1, 0x53, 0x17, 0x5B, 0x2F, 0xC5, 0x61, 0x3D, 0x9B, 0xB7, 0x3C, 0x2A,
+	0x27, 0xFF, 0x00, 0x81, 0xD1, 0x8F, 0xE5, 0x52, 0x47, 0xD8, 0xF0, 0x4E, 0x0A, 0x8E, 0x32, 0x9D,
+	0x7E, 0x7F, 0xB3, 0x28, 0x35, 0xEB, 0x69, 0xBF, 0xD0, 0xFC, 0xBE, 0xFD, 0xBB, 0xA4, 0x4D, 0x0F,
+	0x4B, 0xF1, 0x45, 0x9D, 0xB6, 0xD8, 0xE3, 0x6D, 0x7A, 0xDE, 0x26, 0xDB, 0xF3, 0x6D, 0x5F, 0x2D,
+	0x5B, 0x6D, 0x7C, 0xA9, 0xE1, 0xBF, 0x8B, 0xDA, 0x9F, 0x84, 0xE3, 0xBA, 0x87, 0xC3, 0x76, 0x56,
+	0xE8, 0xBF, 0x76, 0xEB, 0x52, 0xBA, 0x66, 0x5F, 0x95, 0xBF, 0x87, 0x6A, 0xD7, 0xD4, 0x1F, 0xB7,
+	0xF4, 0xD6, 0xDA, 0xF7, 0x84, 0x7C, 0x49, 0x79, 0x0A, 0x2B, 0x49, 0x27, 0x8C, 0x99, 0x15, 0x7F,
+	0xD9, 0x8E, 0xDD, 0x55, 0xB6, 0xFF, 0x00, 0xBA, 0xCD, 0x5F, 0x27, 0xFC, 0x17, 0xF0, 0x8C, 0x7E,
+	0x39, 0xBE, 0xBE, 0xF0, 0x96, 0xA5, 0xAF, 0x68, 0xFA, 0x5D, 0xBC, 0x92, 0xAC, 0xB7, 0x57, 0x5A,
+	0xC6, 0xA4, 0xB0, 0x6D, 0xDB, 0xF2, 0xED, 0x45, 0x6D, 0xBB, 0x9B, 0xFE, 0xF9, 0xFB, 0xD5, 0xFA,
+	0x97, 0x04, 0xD3, 0x8D, 0x3E, 0x1F, 0xBC, 0xFB, 0xAB, 0xFF, 0x00, 0xE0, 0x30, 0x4F, 0xF2, 0x3E,
+	0x3B, 0x89, 0xA3, 0x1F, 0xED, 0x6B, 0x74, 0xD7, 0xFF, 0x00, 0x4A, 0x66, 0xE7, 0xC5, 0x4F, 0x1F,
+	0xFC, 0x78, 0xF0, 0x9D, 0xC6, 0x97, 0x73, 0xE2, 0x1D, 0x7A, 0xE9, 0xE1, 0xBE, 0xB7, 0x59, 0x74,
+	0xD9, 0x26, 0xB8, 0x69, 0x51, 0xA3, 0x55, 0xDB, 0xFB, 0xBD, 0xDF, 0x77, 0x6E, 0xDA, 0xF2, 0xDF,
+	0x11, 0x78, 0xBB, 0x58, 0xF1, 0x66, 0xA5, 0x71, 0xAD, 0xEB, 0x77, 0x9E, 0x74, 0xDE, 0x52, 0xA6,
+	0xEF, 0xE1, 0xAF, 0x62, 0xFD, 0xB6, 0xFC, 0x7F, 0xE0, 0xFD, 0x57, 0x56, 0xF0, 0xC7, 0xC3, 0xDF,
+	0x03, 0x6B, 0xD6, 0xFA, 0x94, 0x3E, 0x1B, 0xD1, 0xB6, 0x5E, 0x5C, 0x69, 0xF7, 0x4B, 0x34, 0x4B,
+	0x24, 0x8C, 0xAD, 0xE5, 0xAB, 0xAF, 0xCA, 0xDB, 0x55, 0x57, 0x76, 0xDD, 0xCB, 0xF3, 0x37, 0xCC,
+	0xDF, 0x35, 0x79, 0x6F, 0xC2, 0x7F, 0x83, 0xFE, 0x3F, 0xF8, 0xE5, 0xAC, 0x5D, 0x78, 0x6F, 0xE1,
+	0xBF, 0x87, 0xA4, 0xBF, 0xBA, 0xB5, 0xB5, 0x6B, 0xAB, 0x88, 0xE3, 0x7F, 0xF5, 0x70, 0xAB, 0x2A,
+	0xB4, 0x8C, 0xDF, 0xDD, 0x5D, 0xCB, 0x5F, 0x5B, 0x97, 0x4B, 0xFD, 0x8E, 0x35, 0x6B, 0x45, 0x41,
+	0xEB, 0xD2, 0xDA, 0x5D, 0xDB, 0xEF, 0x56, 0x67, 0x85, 0x8A, 0x84, 0x63, 0x55, 0xC2, 0x12, 0x6D,
+	0x69, 0xBF, 0xA2, 0xBF, 0xE2, 0x72, 0x57, 0x77, 0x5F, 0xBC, 0xF2, 0x76, 0x6D, 0xF9, 0x7F, 0x89,
+	0x7F, 0x8A, 0xAB, 0x35, 0xC7, 0xDE, 0xFB, 0xBF, 0xF0, 0x25, 0xFB, 0xBF, 0xE7, 0x6D, 0x7B, 0x11,
+	0xFD, 0x87, 0xFF, 0x00, 0x68, 0x46, 0x91, 0xB7, 0xF8, 0x3D, 0x77, 0xAF, 0xF7, 0xAF, 0x23, 0xFF,
+	0x00, 0xE2, 0xAB, 0x97, 0xF8, 0x8D, 0xFB, 0x38, 0x7C, 0x4E, 0xF8, 0x5F, 0xA2, 0xB7, 0x88, 0xBC,
+	0x5D, 0xE1, 0xBF, 0xB3, 0xD9, 0xAC, 0xAA, 0x8D, 0x32, 0xDC, 0x47, 0x27, 0xFE, 0x82, 0xD5, 0xE8,
+	0x46, 0xBD, 0x19, 0x35, 0x15, 0x25, 0x7F, 0x53, 0x97, 0xD9, 0xCB, 0x53, 0x82, 0x69, 0xBC, 0xC5,
+	0x5D, 0xE9, 0xB5, 0xA9, 0x56, 0xF1, 0xD5, 0x55, 0x11, 0x37, 0x1D, 0xDF, 0xF7, 0xD5, 0x47, 0xF2,
+	0x36, 0xDF, 0xF6, 0x7E, 0x6F, 0x97, 0xEE, 0xD0, 0xCA, 0xA1, 0x7E, 0xFF, 0x00, 0xCB, 0xFC, 0x3B,
+	0xAB, 0xA0, 0x8B, 0x13, 0x34, 0x88, 0xCC, 0xBB, 0x21, 0xDA, 0xAB, 0x4C, 0xDD, 0xB9, 0x99, 0xF6,
+	0x2D, 0x44, 0x32, 0xBF, 0xFE, 0xCD, 0x49, 0x1F, 0xCB, 0xFF, 0x00, 0xC4, 0xD2, 0x6E, 0xC2, 0x1D,
+	0x1C, 0x84, 0x32, 0xFF, 0x00, 0x0E, 0xEF, 0xEE, 0xAD, 0x5B, 0xDB, 0xE6, 0x22, 0xA2, 0x7D, 0xD5,
+	0xF9, 0x76, 0xED, 0xFF, 0x00, 0xC7, 0xAA, 0x18, 0x57, 0x74, 0xCD, 0xF2, 0x2E, 0xD5, 0xF9, 0xB7,
+	0x7F, 0xB3, 0x52, 0xAB, 0x21, 0x91, 0x5D, 0xFE, 0xEE, 0xCD, 0xDF, 0x33, 0x7F, 0x0D, 0x26, 0x11,
+	0x89, 0x6B, 0x47, 0xBE, 0x9B, 0x4B, 0xD4, 0xAD, 0xF5, 0x5B, 0x09, 0x9A, 0x39, 0xAD, 0xE5, 0x57,
+	0x8E, 0x45, 0xFB, 0xD1, 0xED, 0x6D, 0xDB, 0xBF, 0xBB, 0x5F, 0x79, 0xFF, 0x00, 0xC1, 0x36, 0x3E,
+	0x20, 0x78, 0xCF, 0xE3, 0x77, 0xC4, 0x0D, 0x42, 0x6F, 0x88, 0xBE, 0x2A, 0x9B, 0x56, 0x5B, 0x3B,
+	0x0D, 0xD6, 0xB1, 0xDC, 0x37, 0x90, 0xB0, 0xB6, 0xE5, 0x5D, 0xDF, 0xBB, 0xFB, 0xCD, 0x5F, 0x03,
+	0x46, 0xBE, 0x73, 0x6C, 0xD9, 0xB5, 0xB6, 0xEE, 0xDC, 0xDF, 0x35, 0x7D, 0xC1, 0xFF, 0x00, 0x04,
+	0x9F, 0xD3, 0xAE, 0x6D, 0x6E, 0x35, 0xBF, 0x10, 0xA5, 0xB6, 0xD8, 0xFE, 0xCF, 0x1C, 0x5E, 0x66,
+	0xDF, 0x97, 0x76, 0xEF, 0xFE, 0xC6, 0xBC, 0xFC, 0xC6, 0x30, 0xF6, 0x3C, 0xED, 0x6A, 0xAC, 0x76,
+	0x60, 0xFF, 0x00, 0x8C, 0xA3, 0xDC, 0xFD, 0x18, 0xF1, 0xC7, 0xC4, 0x8B, 0xCF, 0xF8, 0x45, 0x6E,
+	0x3E, 0xD3, 0x73, 0xFF, 0x00, 0x2E, 0xAC, 0xAC, 0xCD, 0xB9, 0xB7, 0x7C, 0xBF, 0xDE, 0xFF, 0x00,
+	0x3F, 0x76, 0xBC, 0xB3, 0xFE, 0x0D, 0x9F, 0xF0, 0xEB, 0x78, 0xBF, 0xF6, 0xFE, 0xD5, 0xFC, 0x41,
+	0x2A, 0x6E, 0x8D, 0x75, 0x8B, 0xCB, 0x97, 0x93, 0x6F, 0xFC, 0xF3, 0x8E, 0xE2, 0x45, 0xFF, 0x00,
+	0xC7, 0x95, 0x6B, 0x2B, 0xE2, 0x67, 0x8D, 0x26, 0xB1, 0xF0, 0xB6, 0xA5, 0x37, 0x9B, 0x1E, 0xC8,
+	0xEC, 0xD9, 0xF6, 0xFF, 0x00, 0x12, 0xED, 0x5F, 0x9B, 0x75, 0x7A, 0xBF, 0xFC, 0x1A, 0x63, 0xE1,
+	0xC8, 0xB5, 0x6F, 0x8B, 0xBE, 0x20, 0xF1, 0x62, 0x26, 0xFD, 0xBA, 0x5D, 0xE5, 0xCC, 0x92, 0x6D,
+	0xF9, 0xB7, 0x33, 0x43, 0x1F, 0xFE, 0xD5, 0x6A, 0xF3, 0x68, 0xCB, 0x9B, 0x91, 0x7F, 0x79, 0x7F,
+	0x99, 0xDF, 0x8A, 0xB4, 0x68, 0xCA, 0x3E, 0x47, 0xEF, 0x7D, 0x14, 0x51, 0x5F, 0x48, 0x78, 0x01,
+	0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x26, 0xE5, 0xF5, 0xA3, 0x72, 0xFA, 0xD0,
+	0x02, 0xD1, 0x49, 0xB9, 0x7D, 0x68, 0xDC, 0xBE, 0xB4, 0x00, 0xB5, 0xE4, 0xBF, 0x12, 0xBC, 0x43,
+	0x36, 0xA5, 0xA9, 0x4C, 0x2D, 0x8A, 0xBA, 0xC6, 0xDE, 0x5C, 0x4B, 0x5E, 0xB1, 0x24, 0x69, 0x2C,
+	0x6C, 0x8D, 0xF7, 0x59, 0x71, 0x5F, 0x90, 0xBF, 0xB4, 0x56, 0xB1, 0xFF, 0x00, 0x05, 0x2A, 0xF0,
+	0xFF, 0x00, 0xED, 0x63, 0x27, 0xEC, 0xFF, 0x00, 0xE1, 0xCF, 0x12, 0xDC, 0x09, 0xAF, 0x3E, 0xD5,
+	0xA8, 0xE9, 0x32, 0x36, 0xA9, 0x0E, 0xD6, 0xB1, 0x85, 0x97, 0x6C, 0xCD, 0x1C, 0x6C, 0xD2, 0x46,
+	0xBF, 0x32, 0xAA, 0xB3, 0x2A, 0xEE, 0x66, 0xDB, 0x5F, 0x94, 0xF8, 0xA9, 0x98, 0x66, 0x78, 0x5C,
+	0x1D, 0x0A, 0x18, 0x7A, 0x2E, 0x74, 0xE7, 0xCE, 0xE7, 0x24, 0xEC, 0xA3, 0xCA, 0xA3, 0x64, 0xDF,
+	0x9F, 0x33, 0x6B, 0xFC, 0x2C, 0xFA, 0x2E, 0x1E, 0xC1, 0xD1, 0xC5, 0x56, 0x9C, 0xA7, 0x51, 0x45,
+	0xC5, 0x2B, 0x27, 0xD6, 0xF7, 0xBD, 0xBD, 0x2D, 0xAF, 0xA9, 0xFA, 0x15, 0x0D, 0xAA, 0x69, 0xF6,
+	0x6B, 0x0B, 0xFE, 0xF3, 0x6F, 0xCA, 0xDB, 0x57, 0xEF, 0x54, 0xB0, 0x8F, 0x97, 0xE4, 0x87, 0x62,
+	0xFF, 0x00, 0x76, 0xBE, 0x09, 0xD3, 0xFC, 0x23, 0xFF, 0x00, 0x05, 0x77, 0xBA, 0xB7, 0xFB, 0x32,
+	0x78, 0xCB, 0x49, 0xDD, 0xB7, 0xF8, 0xAF, 0x37, 0x37, 0xFE, 0x3D, 0x1D, 0x6D, 0xE9, 0xBE, 0x0B,
+	0xFF, 0x00, 0x82, 0xBD, 0x43, 0x0F, 0xEF, 0xBC, 0x67, 0xE1, 0xF5, 0x5D, 0xBF, 0x76, 0x4B, 0xA6,
+	0xDD, 0xFF, 0x00, 0xA2, 0xEB, 0xF0, 0x79, 0xE7, 0x75, 0x27, 0x2E, 0x65, 0x87, 0x76, 0x5A, 0x68,
+	0xD3, 0xFC, 0x6D, 0xFA, 0x9F, 0x54, 0xB2, 0xBA, 0x6F, 0x7C, 0x44, 0x3F, 0x1F, 0xF2, 0x3E, 0xE1,
+	0x8E, 0x37, 0xA9, 0x63, 0x86, 0xBE, 0x1F, 0x5F, 0x03, 0xFF, 0x00, 0xC1, 0x5B, 0xA5, 0x5D, 0xEF,
+	0xE3, 0xED, 0x05, 0x5D, 0xBF, 0xBB, 0x78, 0xDF, 0xFC, 0x6E, 0xB9, 0xDF, 0x8B, 0x53, 0x7F, 0xC1,
+	0x4E, 0xBE, 0x0B, 0xF8, 0x06, 0xFF, 0x00, 0xE2, 0x2F, 0x8D, 0xBE, 0x2A, 0x69, 0xAD, 0x63, 0xA7,
+	0xC4, 0xD2, 0xDC, 0x2D, 0xBD, 0xE4, 0x9E, 0x66, 0xDF, 0x9B, 0xFD, 0x9F, 0xF7, 0x6A, 0x1F, 0x11,
+	0x4A, 0x8C, 0x39, 0xA5, 0x86, 0x69, 0x2E, 0xAE, 0x56, 0x5F, 0x7D, 0x8A, 0x8E, 0x4F, 0x4E, 0x72,
+	0x51, 0x8E, 0x22, 0x0D, 0xBF, 0x53, 0xF4, 0x13, 0xC9, 0x8D, 0x8E, 0xD7, 0x4A, 0x77, 0x93, 0xF3,
+	0xD7, 0xE3, 0x46, 0x85, 0xFF, 0x00, 0x05, 0x5E, 0xF8, 0xFB, 0xA8, 0xA2, 0xDC, 0xC9, 0xF1, 0x6E,
+	0xF1, 0x93, 0xF8, 0x96, 0x49, 0x77, 0x7F, 0x17, 0xFC, 0x06, 0xBA, 0x7B, 0x0F, 0xF8, 0x2A, 0x37,
+	0xC6, 0xC3, 0x1A, 0x25, 0xE7, 0xC5, 0x4B, 0xAC, 0xFD, 0xD6, 0xF9, 0xBF, 0xEF, 0xAA, 0xD6, 0xB7,
+	0x11, 0x62, 0xA8, 0x4B, 0xDE, 0xC1, 0x4B, 0xFF, 0x00, 0x02, 0x5F, 0xE4, 0x6E, 0xB8, 0x76, 0xA3,
+	0xFF, 0x00, 0x97, 0xD1, 0xFC, 0x4F, 0xD7, 0x25, 0x8F, 0x6A, 0xAD, 0x7C, 0xAB, 0xFF, 0x00, 0x05,
+	0x68, 0xF8, 0xE9, 0x7F, 0xF0, 0xCB, 0xE0, 0xAE, 0x93, 0xE0, 0x3F, 0x0F, 0x5C, 0xB4, 0x7A, 0x87,
+	0x89, 0x35, 0x68, 0xD9, 0x9A, 0x3F, 0xBC, 0xB6, 0xF0, 0xB2, 0xC8, 0xDF, 0xF8, 0xF7, 0x97, 0x5F,
+	0x24, 0x27, 0xFC, 0x14, 0xCB, 0xE3, 0xED, 0xCC, 0x3B, 0xEC, 0xFE, 0x28, 0xDC, 0x33, 0x7F, 0x77,
+	0xCD, 0x8E, 0xBB, 0x0F, 0xD9, 0x32, 0xD3, 0xC6, 0x5F, 0xB6, 0xFF, 0x00, 0xED, 0x9F, 0xE0, 0x9D,
+	0x7B, 0xE2, 0x9E, 0xB7, 0x36, 0xA9, 0x63, 0xE1, 0x56, 0x93, 0x5A, 0xD4, 0xDA, 0xE9, 0xB7, 0x47,
+	0x15, 0xBD, 0x9B, 0x47, 0x24, 0x7F, 0x2F, 0xF7, 0x5A, 0x66, 0x89, 0x76, 0xFF, 0x00, 0xB5, 0x5D,
+	0x79, 0x56, 0x69, 0x5F, 0x89, 0xB3, 0x2A, 0x39, 0x5C, 0x68, 0xBA, 0x5E, 0xD2, 0x49, 0x39, 0x36,
+	0x9D, 0xA3, 0x17, 0xCD, 0x27, 0x6F, 0xF0, 0xC5, 0xF6, 0xD2, 0xE5, 0x47, 0x29, 0xFE, 0xCB, 0x97,
+	0xD7, 0x2A, 0xD4, 0x52, 0x8C, 0x13, 0x95, 0x95, 0xF7, 0x5B, 0x6F, 0xE6, 0x62, 0xFF, 0x00, 0xC1,
+	0xC2, 0xDF, 0xF0, 0x55, 0x9F, 0x8C, 0xDF, 0x01, 0x0F, 0xC3, 0xCF, 0xD8, 0xBF, 0xC1, 0xB0, 0xDB,
+	0xDA, 0xEB, 0x1E, 0x30, 0xF0, 0xCD, 0xBE, 0xA1, 0xE3, 0xC5, 0x8E, 0x6F, 0x2D, 0xE3, 0x9A, 0x4D,
+	0xAB, 0x1D, 0xBE, 0xE6, 0x56, 0xDB, 0x1E, 0xE5, 0x6D, 0xDF, 0xDE, 0xF9, 0x7F, 0xE0, 0x5F, 0x96,
+	0xFE, 0x19, 0x6F, 0xB3, 0xDA, 0xEA, 0x9A, 0xE6, 0xA5, 0xAB, 0xD8, 0xC9, 0x73, 0x26, 0xA5, 0xB1,
+	0x95, 0x9D, 0x64, 0x92, 0x4D, 0xCB, 0xBB, 0xCC, 0x55, 0x6F, 0xE1, 0xFF, 0x00, 0x6B, 0x6F, 0xF7,
+	0x6B, 0xEA, 0x7F, 0xDA, 0xBB, 0xC4, 0x1A, 0x27, 0xED, 0xAD, 0xFF, 0x00, 0x05, 0x2A, 0xFD, 0xA1,
+	0x3F, 0x69, 0xFF, 0x00, 0x12, 0x45, 0x6F, 0x79, 0xE1, 0xBF, 0x86, 0x7A, 0x72, 0xF8, 0x53, 0xC2,
+	0x50, 0xC9, 0xF3, 0x7D, 0xAB, 0x54, 0x91, 0x9A, 0xDE, 0x39, 0x95, 0xBE, 0xEF, 0xEE, 0xFC, 0xBB,
+	0xBB, 0x8F, 0xFB, 0x62, 0xAB, 0x5F, 0x35, 0xF8, 0xCB, 0xC1, 0xDA, 0xF7, 0xC3, 0xDF, 0x88, 0xBE,
+	0x19, 0xF0, 0xAF, 0x81, 0xA1, 0x8E, 0x4D, 0x5F, 0x56, 0xB8, 0x92, 0x08, 0xB7, 0x4A, 0xAD, 0xB5,
+	0x99, 0x7C, 0xB6, 0xFF, 0x00, 0x79, 0xB7, 0x33, 0x57, 0xEC, 0x39, 0x8F, 0x2E, 0x61, 0x88, 0xA3,
+	0x45, 0x73, 0x7B, 0x5A, 0xE9, 0xD4, 0x6E, 0xED, 0xB5, 0x16, 0xDB, 0xA6, 0x9A, 0x7B, 0x5A, 0x09,
+	0x5D, 0x24, 0xAF, 0x7B, 0xEE, 0xDB, 0x3C, 0x6C, 0x95, 0x4B, 0x0B, 0x85, 0xAD, 0x89, 0xB2, 0xB4,
+	0x1D, 0x97, 0x66, 0xF4, 0xBD, 0xBB, 0xEA, 0xED, 0xFF, 0x00, 0x0C, 0x24, 0x9E, 0x2A, 0xF0, 0x7E,
+	0xA4, 0xB1, 0xE9, 0xB7, 0x57, 0x51, 0xEF, 0xB8, 0x5D, 0x9B, 0x7E, 0xCA, 0xBB, 0x5B, 0x76, 0xEF,
+	0xF6, 0x69, 0xDE, 0x07, 0xD1, 0x2C, 0x3E, 0x1B, 0x9B, 0xAF, 0xF8, 0x44, 0xAF, 0x2E, 0xA1, 0x5B,
+	0xE9, 0x55, 0xEE, 0x2D, 0xD7, 0xE6, 0x59, 0x15, 0x7E, 0xEB, 0x6D, 0xDB, 0xF7, 0xBE, 0x66, 0xFF,
+	0x00, 0xBE, 0x9A, 0xBB, 0x1F, 0x06, 0x7E, 0xCD, 0x3F, 0x11, 0x75, 0x6F, 0x8B, 0x56, 0xBF, 0x0E,
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+	0xF9, 0xB7, 0x11, 0xC9, 0xF2, 0xB7, 0xCB, 0xF7, 0xA9, 0x7C, 0x4C, 0xDF, 0x68, 0xD6, 0x2D, 0xDD,
+	0x11, 0x42, 0xFF, 0x00, 0x64, 0xDA, 0xB6, 0xD6, 0xFF, 0x00, 0x77, 0x75, 0x61, 0x4E, 0x55, 0x29,
+	0xE0, 0xE5, 0x26, 0xBE, 0x24, 0xAD, 0x7F, 0x34, 0xD7, 0xE6, 0x6B, 0x09, 0x54, 0xF6, 0x8D, 0xBD,
+	0x52, 0x4D, 0x2F, 0xBD, 0x7F, 0x98, 0xDB, 0x3D, 0x59, 0x2E, 0xEE, 0x2D, 0xE6, 0xBC, 0x9A, 0x4B,
+	0x69, 0x2D, 0xD5, 0x56, 0x2B, 0xC5, 0x5F, 0x9A, 0x3F, 0xE2, 0x5F, 0xF7, 0x96, 0x9B, 0x75, 0x0D,
+	0xBE, 0xA9, 0xA7, 0xCF, 0xAA, 0xC2, 0xF2, 0x46, 0xD6, 0x77, 0x11, 0xA2, 0xC9, 0x1A, 0xED, 0x59,
+	0xB7, 0x7C, 0xAD, 0xFE, 0xED, 0x56, 0x8E, 0xD7, 0xE6, 0xD9, 0x9D, 0xBF, 0xC3, 0x53, 0xBD, 0xCA,
+	0x45, 0xA1, 0xCD, 0xA5, 0x59, 0x5B, 0x6E, 0x92, 0x69, 0x55, 0xD9, 0x9A, 0x5D, 0xAB, 0xFE, 0xCF,
+	0xCB, 0xFD, 0xEA, 0xCA, 0x9D, 0x48, 0xCA, 0x9B, 0xE7, 0xEC, 0xFE, 0x6E, 0xDA, 0x7C, 0xD3, 0xB3,
+	0xBF, 0x96, 0xBE, 0x5B, 0x51, 0xA9, 0x56, 0x2F, 0x97, 0xF1, 0x37, 0x35, 0x08, 0x52, 0xCE, 0xE2,
+	0xDA, 0x1D, 0xBB, 0x59, 0x7C, 0x47, 0x70, 0x9B, 0x7F, 0x8B, 0xFD, 0x5C, 0x75, 0x87, 0x79, 0x24,
+	0xCB, 0xA2, 0xEF, 0xD9, 0x26, 0xDF, 0xEC, 0xDB, 0x75, 0x56, 0xFF, 0x00, 0x6B, 0xCE, 0xAD, 0xED,
+	0x5D, 0x52, 0x7D, 0x56, 0xCD, 0x10, 0x7C, 0xB2, 0x78, 0xAA, 0xE9, 0x59, 0x76, 0xED, 0xFE, 0x18,
+	0xEB, 0x9D, 0xBA, 0x4D, 0xDA, 0x1C, 0x6E, 0xE3, 0x6A, 0xB6, 0x87, 0x6E, 0x76, 0xAC, 0x5B, 0xBE,
+	0x6F, 0xB4, 0x6D, 0xFB, 0xB5, 0xDF, 0x99, 0x53, 0x97, 0xB5, 0x9A, 0x8E, 0xDF, 0xFD, 0xAC, 0x7F,
+	0xCC, 0xF4, 0x28, 0xCF, 0xF7, 0x6A, 0xFF, 0x00, 0xD6, 0xAD, 0x12, 0x2B, 0x3B, 0xEA, 0x67, 0x7A,
+	0x36, 0xDF, 0xED, 0x88, 0xD5, 0x99, 0x7F, 0xEB, 0x9B, 0x55, 0x58, 0xE6, 0xF2, 0xEC, 0xD2, 0x5F,
+	0x3B, 0x0A, 0xB0, 0x5E, 0x6E, 0x6F, 0xEE, 0xFC, 0xAD, 0x57, 0x2E, 0xA2, 0x48, 0x75, 0x79, 0x9D,
+	0x26, 0x55, 0xDB, 0xAC, 0x5B, 0xED, 0x65, 0xFF, 0x00, 0xAE, 0x6D, 0x58, 0x3E, 0x27, 0xD9, 0x0F,
+	0x87, 0xA6, 0xB6, 0x7B, 0x96, 0x45, 0xFB, 0x2E, 0xA5, 0xB9, 0x97, 0xFB, 0xBE, 0x5D, 0x71, 0xC6,
+	0x31, 0xA3, 0x2B, 0xB5, 0xB3, 0x7F, 0x86, 0xDF, 0x91, 0xB7, 0x3F, 0x3E, 0xDD, 0x7F, 0xF9, 0x23,
+	0xE4, 0x7F, 0xDA, 0x3B, 0xC5, 0x9A, 0x97, 0x8D, 0x3E, 0x1D, 0xF8, 0x6F, 0xC6, 0x1A, 0xBE, 0x95,
+	0x25, 0x9C, 0x9A, 0xC6, 0x9B, 0x6F, 0x7B, 0xF6, 0x59, 0x1B, 0xFD, 0x5F, 0x9D, 0x0A, 0xC9, 0xF2,
+	0xFF, 0x00, 0xB2, 0xDB, 0xB7, 0x2F, 0xF1, 0x6D, 0x6A, 0xF9, 0x47, 0xC6, 0x17, 0x89, 0x0E, 0xA1,
+	0xF2, 0x3C, 0x6A, 0xCD, 0xB5, 0xBE, 0xF7, 0xDE, 0xFF, 0x00, 0x7B, 0xFF, 0x00, 0x89, 0xAF, 0xB8,
+	0x3F, 0x6A, 0x4B, 0x7F, 0x0A, 0xF8, 0x83, 0xF6, 0x7B, 0xF0, 0xDE, 0xBD, 0xA0, 0xCD, 0x1B, 0x5B,
+	0x5B, 0xF8, 0x7E, 0xCF, 0x4E, 0x65, 0x87, 0xE6, 0xFB, 0x3D, 0xC5, 0xAC, 0x6B, 0x0F, 0x96, 0xDB,
+	0x7E, 0xEF, 0xCB, 0x1A, 0xB7, 0xFB, 0xAD, 0xFE, 0xCB, 0x6D, 0xF8, 0x1F, 0xC6, 0x53, 0x2C, 0x57,
+	0x92, 0x27, 0x9D, 0xF3, 0x6E, 0xFE, 0x2A, 0xFE, 0xA0, 0xC3, 0x47, 0xD8, 0x25, 0x4D, 0xAD, 0x12,
+	0xD3, 0xD3, 0xA7, 0xE0, 0x7E, 0x5F, 0x2A, 0x91, 0xAD, 0x4D, 0x49, 0x3F, 0x5F, 0x51, 0xAD, 0x7C,
+	0xF0, 0xEE, 0xBF, 0x77, 0xF9, 0x96, 0x55, 0x6D, 0xAD, 0xF7, 0xBF, 0xBC, 0xD5, 0x93, 0xAD, 0x5E,
+	0x3C, 0x96, 0xBB, 0xFE, 0xD9, 0xB5, 0xA3, 0x89, 0x57, 0xFF, 0x00, 0x1D, 0x87, 0xFF, 0x00, 0x89,
+	0x6A, 0x87, 0x56, 0xD4, 0x90, 0xDA, 0xDB, 0xC3, 0x66, 0xF2, 0x6F, 0xF9, 0x96, 0xE3, 0xE6, 0xF9,
+	0x77, 0x6E, 0xFB, 0xCB, 0xFF, 0x00, 0x01, 0x6A, 0xE7, 0x35, 0x4D, 0x66, 0x65, 0x57, 0xDF, 0x32,
+	0xAA, 0xED, 0xFB, 0xAD, 0xFD, 0xDA, 0xFA, 0x3C, 0x2F, 0xBC, 0xAC, 0x72, 0xD4, 0xDE, 0xE5, 0x6F,
+	0x14, 0x5D, 0xF9, 0x8B, 0x25, 0x84, 0x77, 0xFB, 0x57, 0xF8, 0x5B, 0xEE, 0xB5, 0x79, 0xA7, 0x8A,
+	0x26, 0xB6, 0x55, 0x93, 0x67, 0xCD, 0xF2, 0xB7, 0xCC, 0xDF, 0x33, 0x2D, 0x74, 0xFE, 0x22, 0xD4,
+	0x1F, 0xED, 0x8D, 0xE4, 0x7C, 0xAA, 0xB1, 0x7F, 0xBA, 0xCD, 0xFF, 0x00, 0x01, 0xFF, 0x00, 0x7A,
+	0xBC, 0xEF, 0xC6, 0xFA, 0xB2, 0x43, 0xE6, 0x49, 0xF6, 0x9D, 0xEC, 0xDF, 0x2F, 0xCA, 0xBF, 0xFA,
+	0x0D, 0x7B, 0xD8, 0x48, 0x5A, 0x49, 0x23, 0x8A, 0xAC, 0xB7, 0xB9, 0x8B, 0x0E, 0xB8, 0xFA, 0x7E,
+	0xAC, 0xB7, 0x36, 0x76, 0xCD, 0x75, 0x34, 0x31, 0xF9, 0xEB, 0x6E, 0xBF, 0x36, 0xE5, 0x8D, 0x7C,
+	0xC6, 0xDD, 0xFF, 0x00, 0x01, 0x5A, 0xFD, 0x50, 0xF8, 0x5F, 0xFF, 0x00, 0x05, 0x06, 0xF0, 0x1F,
+	0xC4, 0x4F, 0xD9, 0xCB, 0xC3, 0x1F, 0xDB, 0x73, 0xCD, 0x6D, 0xE2, 0x0D, 0x26, 0xCA, 0xE2, 0x5B,
+	0xC8, 0x64, 0x6F, 0xF5, 0x8D, 0xE4, 0xC2, 0xDF, 0x2F, 0xDD, 0xFB, 0xCD, 0xBA, 0xBF, 0x2B, 0xFE,
+	0x18, 0xEA, 0x0E, 0x7C, 0x5D, 0x26, 0xB1, 0x78, 0x8C, 0xB0, 0xC3, 0x6E, 0xC8, 0xCB, 0xF2, 0xFE,
+	0xF1, 0xA4, 0x5D, 0xAB, 0x1F, 0xFE, 0xCD, 0xFE, 0xEA, 0xB7, 0xF7, 0x6B, 0xD9, 0xBC, 0x2B, 0xA4,
+	0xCD, 0x6B, 0xE1, 0x15, 0xBF, 0x0E, 0xA9, 0xB7, 0x52, 0x92, 0x05, 0x68, 0xFF, 0x00, 0xBA, 0xCA,
+	0xDB, 0x7F, 0xF1, 0xD5, 0xAF, 0x98, 0xF1, 0x07, 0x87, 0x70, 0x79, 0xCE, 0x0A, 0x9C, 0xEB, 0xDD,
+	0x4A, 0x0D, 0xA4, 0xD7, 0xAC, 0x64, 0xD7, 0x6B, 0x5E, 0x2B, 0xEE, 0x47, 0xB9, 0xC2, 0x79, 0x95,
+	0x6C, 0x0E, 0x2A, 0x71, 0xA6, 0xF7, 0x49, 0xBF, 0xC5, 0x7E, 0x4D, 0x9E, 0x87, 0xAC, 0x69, 0x3E,
+	0x1F, 0xF8, 0xC9, 0xFB, 0x2F, 0xF8, 0xDB, 0xC7, 0xFE, 0x21, 0xD5, 0x61, 0xB7, 0xBF, 0x59, 0x66,
+	0xD4, 0xB4, 0xD8, 0x64, 0x6F, 0x9A, 0xE1, 0xA4, 0xBC, 0x55, 0xDB, 0x1F, 0xFB, 0x5E, 0x5B, 0x6E,
+	0xFF, 0x00, 0x80, 0xD7, 0xE7, 0x76, 0xA9, 0xA8, 0x5F, 0xAE, 0xA1, 0x36, 0xFB, 0xC6, 0xF3, 0x23,
+	0x97, 0xE5, 0xFE, 0xF5, 0x7D, 0xF3, 0xE2, 0x0D, 0x1F, 0x58, 0xD5, 0xBF, 0x66, 0x5F, 0x08, 0xBF,
+	0xC1, 0xBB, 0xCB, 0x1F, 0x11, 0x2E, 0xB9, 0xA5, 0xC9, 0x07, 0x8A, 0xAC, 0x76, 0xFD, 0x8E, 0xEB,
+	0xC3, 0xFA, 0x85, 0xBC, 0x93, 0x5B, 0xB2, 0xFE, 0xF1, 0xB6, 0xCD, 0x1C, 0x91, 0xAC, 0x73, 0x2C,
+	0x8A, 0xDF, 0xC4, 0xCA, 0xCA, 0xAC, 0xBF, 0x37, 0xC2, 0xDE, 0x3C, 0xD0, 0x3C, 0x4B, 0xA7, 0xF8,
+	0x9A, 0xE3, 0x47, 0xD6, 0xA4, 0x9A, 0xE1, 0xAD, 0xDB, 0x6A, 0xCD, 0xE7, 0x79, 0xAA, 0xCB, 0xF7,
+	0x97, 0xE7, 0x5F, 0x97, 0xE6, 0xDC, 0xB5, 0xF5, 0xBC, 0x29, 0x4E, 0x58, 0x58, 0xD7, 0xA0, 0xEC,
+	0xA2, 0xA5, 0xEE, 0xDA, 0x49, 0xE8, 0xD7, 0x55, 0xBA, 0xB7, 0x66, 0x78, 0x59, 0xE4, 0xBD, 0xB5,
+	0x48, 0x54, 0xD6, 0xED, 0x6B, 0xA7, 0x5E, 0xB6, 0xEE, 0x73, 0xF3, 0x5E, 0x4D, 0x71, 0x23, 0x4C,
+	0xEF, 0xB9, 0xD9, 0xB7, 0x6E, 0xAF, 0x44, 0xFD, 0x9E, 0x7C, 0x71, 0xE2, 0xDF, 0x02, 0xDC, 0x6B,
+	0x97, 0x9E, 0x1B, 0xD6, 0xE6, 0xB5, 0x7B, 0xED, 0x27, 0xEC, 0x57, 0x57, 0x10, 0xCA, 0xCA, 0xCD,
+	0x0B, 0x4D, 0x1B, 0x6D, 0xFF, 0x00, 0xBE, 0xA3, 0x5F, 0xFB, 0xE6, 0xB8, 0x26, 0xD2, 0x2F, 0xD6,
+	0x1F, 0x3B, 0xEC, 0xD2, 0x6D, 0x66, 0x5F, 0x9B, 0xCA, 0x6A, 0xEE, 0x7E, 0x11, 0xF8, 0x77, 0x55,
+	0x87, 0x4F, 0xBF, 0xB9, 0x9A, 0xCE, 0x44, 0x59, 0x19, 0x52, 0x29, 0x1A, 0x2D, 0xBF, 0xDE, 0xDD,
+	0xF3, 0x57, 0xD4, 0x62, 0xEA, 0x47, 0xEA, 0xCD, 0xAF, 0x2F, 0xCD, 0x1E, 0x2E, 0x19, 0x73, 0x57,
+	0x8A, 0x91, 0xD0, 0x6B, 0x9F, 0x13, 0xBC, 0x73, 0x77, 0x2B, 0x43, 0x79, 0xE2, 0x7D, 0x41, 0xD5,
+	0x7E, 0x5D, 0xCD, 0x2B, 0x6D, 0xAE, 0x77, 0xE2, 0x07, 0x8D, 0xBC, 0x49, 0xA8, 0x78, 0x42, 0xE3,
+	0x4A, 0xD5, 0x6E, 0xE6, 0x92, 0x19, 0x15, 0x51, 0x56, 0x49, 0x59, 0x95, 0x76, 0xB6, 0xEF, 0xEF,
+	0x7F, 0xB3, 0xB6, 0xB6, 0x75, 0x2D, 0x1E, 0xE6, 0x18, 0xD6, 0xF2, 0xE5, 0x3F, 0x72, 0xDF, 0xF2,
+	0xD1, 0xBF, 0xF4, 0x1A, 0xA1, 0x79, 0xE0, 0xBB, 0xCF, 0x1B, 0x49, 0x6D, 0xE1, 0x8B, 0x0B, 0x95,
+	0xB3, 0x59, 0x37, 0x3B, 0xDD, 0x5C, 0x2F, 0xC8, 0xBB, 0x57, 0x77, 0xCD, 0xFE, 0xCE, 0xDA, 0xE2,
+	0xA2, 0xE5, 0xCC, 0x9C, 0xBB, 0x9D, 0x15, 0x95, 0x3D, 0x6D, 0xD4, 0xF2, 0xC5, 0x6F, 0xBA, 0xFF,
+	0x00, 0x79, 0x7F, 0xBA, 0xD4, 0xAF, 0xF7, 0x5B, 0x7B, 0xFF, 0x00, 0xBD, 0x5E, 0x8D, 0xE3, 0x0F,
+	0xD9, 0xD7, 0x55, 0xF0, 0xB7, 0x86, 0x64, 0xF1, 0x0C, 0x3E, 0x3E, 0xF0, 0xDE, 0xA4, 0x90, 0xB6,
+	0xD9, 0x6C, 0xF4, 0xFB, 0xF6, 0x6B, 0x9F, 0xBC, 0xBF, 0x76, 0x36, 0x5F, 0xF6, 0x96, 0xB8, 0x19,
+	0x34, 0x9D, 0x4A, 0x15, 0x57, 0x9A, 0xC2, 0x45, 0x5F, 0xF7, 0x76, 0xD7, 0xB1, 0x09, 0xC6, 0xB6,
+	0xB1, 0xFE, 0xBE, 0xF3, 0xCE, 0x71, 0x70, 0xDC, 0xAD, 0xE6, 0x7C, 0xDF, 0x71, 0x97, 0x75, 0x4A,
+	0xAB, 0xB7, 0x73, 0xEF, 0x6F, 0xF6, 0xAB, 0x7B, 0x50, 0xF8, 0x75, 0xAA, 0x68, 0xF6, 0x16, 0x37,
+	0xF7, 0xF6, 0xCD, 0x23, 0x5F, 0x5A, 0xAC, 0xD1, 0x47, 0x1C, 0xAA, 0xAC, 0xAA, 0xCD, 0xB5, 0x77,
+	0x7D, 0xEF, 0xEE, 0xD7, 0xA2, 0xEA, 0xDF, 0xB3, 0x0E, 0x9B, 0xE1, 0xDF, 0x82, 0x09, 0xF1, 0x3B,
+	0x55, 0xF1, 0x8E, 0x9E, 0xFA, 0xC4, 0x97, 0x16, 0xAA, 0xBE, 0x1B, 0xB7, 0x9D, 0x9E, 0x55, 0x86,
+	0x68, 0xD9, 0x96, 0x46, 0x75, 0xF9, 0x55, 0xB6, 0xAE, 0xED, 0xBF, 0x37, 0xDE, 0x5F, 0x9A, 0xA2,
+	0x55, 0x61, 0x1F, 0xC8, 0xA8, 0xD3, 0x6D, 0xD8, 0xF1, 0xEB, 0x52, 0xFF, 0x00, 0x71, 0x3E, 0x5A,
+	0xEA, 0x3E, 0x16, 0xE9, 0xBA, 0x6E, 0xB7, 0xE3, 0xAD, 0x37, 0x4A, 0xD6, 0x21, 0xDF, 0x6B, 0x75,
+	0x71, 0xB2, 0x58, 0xD5, 0xBE, 0x6F, 0x9A, 0xB3, 0xDB, 0x45, 0xB8, 0xB3, 0x5F, 0x93, 0x44, 0xDD,
+	0xF7, 0x77, 0x6E, 0x95, 0xBF, 0xFB, 0x1F, 0xF6, 0x6B, 0x63, 0xC0, 0xF3, 0x4A, 0xDE, 0x28, 0xB0,
+	0x29, 0xA3, 0xC3, 0x6C, 0x61, 0xBA, 0x8D, 0x9E, 0x65, 0x59, 0x17, 0x6A, 0xF9, 0x8B, 0xFD, 0xE6,
+	0xA3, 0xDA, 0x5D, 0x03, 0xA6, 0x7D, 0x13, 0x63, 0xFB, 0x3D, 0xF8, 0x07, 0x4B, 0xD4, 0x60, 0xB9,
+	0x87, 0xC3, 0xD1, 0xC8, 0xD6, 0xB2, 0xEE, 0x5F, 0xB5, 0x2A, 0xC8, 0xAD, 0xFE, 0xF2, 0xB7, 0xCA,
+	0xD5, 0xDA, 0xF8, 0x47, 0x52, 0xF1, 0x97, 0xC3, 0xFB, 0x5B, 0x8B, 0x3F, 0x87, 0x9A, 0xC4, 0x3A,
+	0x2D, 0xBD, 0xD6, 0xDF, 0xB4, 0x5B, 0xD8, 0xD9, 0xC7, 0x1C, 0x6D, 0xF2, 0xB6, 0xDF, 0x95, 0x56,
+	0xB6, 0x6F, 0x34, 0xD4, 0xB8, 0xD3, 0xE1, 0xD4, 0xA1, 0x87, 0x73, 0x4D, 0x6E, 0xAE, 0xCC, 0xBF,
+	0xDE, 0x65, 0xDC, 0xD5, 0x0D, 0xB5, 0x8F, 0xD8, 0xE1, 0x74, 0x78, 0x77, 0x3F, 0xCA, 0xDF, 0xC5,
+	0xFD, 0xDF, 0xE1, 0xFF, 0x00, 0xC7, 0xAB, 0x37, 0x15, 0x2D, 0xD5, 0xCC, 0xA3, 0x52, 0x54, 0xF5,
+	0xB9, 0x81, 0xAE, 0xFC, 0x6A, 0xF8, 0xA9, 0x6A, 0xD7, 0x5E, 0x15, 0xF1, 0x26, 0xBD, 0xF6, 0xFB,
+	0x3D, 0x4A, 0xC2, 0xE2, 0xDD, 0x7C, 0xEF, 0x97, 0xCB, 0x93, 0x6B, 0x6D, 0x6D, 0xD5, 0xFA, 0xB9,
+	0xFF, 0x00, 0x06, 0x87, 0xF8, 0x21, 0xED, 0xFE, 0x1E, 0xF8, 0xCB, 0xC6, 0x6F, 0x12, 0xAF, 0x97,
+	0x63, 0x1D, 0xAF, 0xF1, 0x6E, 0xFD, 0xE5, 0xC3, 0x7F, 0xF2, 0x35, 0x7E, 0x4A, 0xFC, 0x5C, 0xD2,
+	0xD2, 0xDF, 0x4D, 0xB3, 0xD6, 0x12, 0x1F, 0x9E, 0xDE, 0xF1, 0x7E, 0x65, 0xFF, 0x00, 0xBE, 0x76,
+	0xD7, 0xEE, 0x8F, 0xFC, 0x1A, 0xD9, 0xE0, 0x04, 0xF0, 0xCF, 0xEC, 0x6B, 0xE2, 0x6F, 0x12, 0x2E,
+	0xEF, 0xF8, 0x99, 0x78, 0x82, 0x38, 0xBE, 0xF7, 0xCB, 0xFB, 0xB5, 0x92, 0x6E, 0x3F, 0xBB, 0xFF,
+	0x00, 0x1F, 0x35, 0xCF, 0x2A, 0x71, 0xF6, 0xF4, 0xB9, 0x55, 0xB5, 0x7B, 0x7A, 0x33, 0xAB, 0xDA,
+	0xCA, 0x78, 0x69, 0x5D, 0xF6, 0x3F, 0x4F, 0xE8, 0xA2, 0x8A, 0xF5, 0x0E, 0x12, 0x9E, 0xB5, 0xAD,
+	0xE9, 0xBE, 0x1E, 0xD2, 0x67, 0xD6, 0xF5, 0x8B, 0x85, 0x86, 0xDE, 0xDE, 0x3D, 0xF3, 0x48, 0xDF,
+	0xC2, 0xB5, 0xE2, 0x3F, 0x13, 0x7C, 0x47, 0xFB, 0x5B, 0x78, 0xAB, 0x5C, 0x48, 0x7E, 0x1A, 0x6A,
+	0x1E, 0x1D, 0xF0, 0xB6, 0x93, 0x1B, 0x37, 0x9C, 0xBA, 0xA5, 0x8C, 0xD7, 0x57, 0xD3, 0x2E, 0xDF,
+	0xBD, 0xF2, 0xB4, 0x6B, 0x1B, 0x6E, 0xFE, 0x1F, 0x9A, 0xBD, 0x17, 0xC5, 0xDE, 0x2C, 0xD0, 0xA0,
+	0xF8, 0x89, 0xA4, 0xF8, 0x37, 0x58, 0xBE, 0x86, 0x28, 0xD7, 0x4F, 0xB8, 0xD5, 0x65, 0x59, 0xD9,
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+	0xA7, 0xDA, 0xF8, 0x82, 0x1D, 0x3A, 0xE6, 0x19, 0xA1, 0xB3, 0xB7, 0xD8, 0xCD, 0x1F, 0x9B, 0x23,
+	0x33, 0x33, 0x2E, 0xDF, 0x9B, 0xEE, 0xFF, 0x00, 0x77, 0x72, 0xFF, 0x00, 0x7B, 0xFD, 0xDA, 0x82,
+	0xEB, 0x5C, 0x79, 0x19, 0x1E, 0x1B, 0x55, 0x8D, 0xA1, 0xF3, 0x3F, 0x77, 0x22, 0xF9, 0x8D, 0xFC,
+	0x3B, 0xB7, 0x37, 0xF1, 0x7C, 0xBB, 0x77, 0x7F, 0xBB, 0x5E, 0x6F, 0x27, 0xC7, 0x8B, 0xFF, 0x00,
+	0xED, 0x8F, 0x06, 0x68, 0x89, 0xFB, 0x3F, 0x7C, 0x4A, 0xFB, 0x67, 0xC4, 0x88, 0xD6, 0x6F, 0x00,
+	0xD8, 0xAF, 0x85, 0x7F, 0x79, 0xAD, 0x5B, 0xB6, 0xD6, 0x56, 0xB6, 0xFD, 0xE7, 0xEF, 0xBE, 0x56,
+	0x5F, 0xBB, 0xFD, 0xEA, 0x48, 0xFE, 0x3F, 0x5B, 0x7F, 0x67, 0xF8, 0xDB, 0x5B, 0xFF, 0x00, 0x85,
+	0x4B, 0xF1, 0x0A, 0xE2, 0xDB, 0xE1, 0xBD, 0xD2, 0xC1, 0xE3, 0xE5, 0x87, 0xC2, 0x53, 0x34, 0x7A,
+	0x2C, 0xCD, 0x24, 0x91, 0xED, 0x9F, 0xE6, 0x55, 0x85, 0xB7, 0x44, 0xCB, 0xFB, 0xCD, 0xBF, 0xEA,
+	0xDB, 0xEF, 0x6D, 0xA3, 0xFD, 0x9D, 0x49, 0xBB, 0xAF, 0xEB, 0x4F, 0xC1, 0x8A, 0x54, 0xEA, 0x47,
+	0x54, 0x8E, 0xF6, 0xDD, 0xE6, 0x69, 0x24, 0x7B, 0x9B, 0xCD, 0xEF, 0x0A, 0xB3, 0xB4, 0xD3, 0x5C,
+	0x7E, 0xF2, 0x46, 0xDD, 0xF7, 0x9B, 0xFB, 0xCD, 0x4B, 0x1C, 0x78, 0x55, 0x87, 0xED, 0x2D, 0xF2,
+	0xFC, 0xCD, 0xFF, 0x00, 0x2D, 0x3F, 0xBB, 0xFD, 0xDA, 0xE0, 0x6D, 0x7E, 0x3C, 0x6A, 0xB3, 0x5E,
+	0x78, 0x26, 0xC1, 0x3F, 0x67, 0xBF, 0x89, 0x4F, 0x73, 0xF1, 0x22, 0x0D, 0xFE, 0x05, 0x55, 0xF0,
+	0x97, 0xCD, 0xAE, 0x2C, 0x8C, 0xBB, 0x64, 0x81, 0x56, 0x4D, 0xD3, 0x7D, 0xE5, 0xF9, 0x97, 0xFB,
+	0xD4, 0xDB, 0x7F, 0xDA, 0x22, 0x6B, 0xE5, 0xF1, 0xB4, 0xDF, 0xF0, 0xA2, 0xBE, 0x26, 0x32, 0x7C,
+	0x3F, 0xFF, 0x00, 0x91, 0xDE, 0x48, 0xFC, 0x27, 0xB6, 0x3F, 0x0F, 0xFE, 0xF1, 0xA3, 0xDD, 0x76,
+	0xDB, 0xBF, 0x73, 0x1F, 0xEE, 0xA4, 0x5F, 0x9B, 0x6F, 0xDD, 0x66, 0xFE, 0x16, 0x56, 0xD3, 0xDA,
+	0x52, 0x8C, 0x77, 0x5F, 0xD6, 0x9F, 0x98, 0x95, 0x39, 0x38, 0xDD, 0xA3, 0xBC, 0x4F, 0xB4, 0xBD,
+	0xD3, 0x09, 0xF7, 0x26, 0xE9, 0x76, 0xAA, 0xAB, 0x7F, 0x0E, 0xDF, 0xBD, 0xFF, 0x00, 0xB3, 0x7F,
+	0xDF, 0x35, 0x66, 0xD7, 0x50, 0x7B, 0x38, 0x64, 0xB3, 0x17, 0x2C, 0xD6, 0xFB, 0xD5, 0xB6, 0xB3,
+	0x7D, 0xDF, 0x99, 0xBF, 0xD9, 0xFF, 0x00, 0x76, 0xBC, 0xE1, 0x7F, 0x68, 0x0D, 0x4A, 0x69, 0xBC,
+	0x17, 0xBF, 0xE0, 0x57, 0xC4, 0x85, 0x6F, 0x88, 0xD2, 0xEC, 0xF0, 0x45, 0xC4, 0x9E, 0x0F, 0x65,
+	0xFE, 0xDE, 0xFB, 0xBF, 0x35, 0xA3, 0x33, 0x6D, 0x9B, 0x76, 0xE8, 0xFE, 0xEE, 0xEF, 0xBC, 0xB5,
+	0x1D, 0xC7, 0xC7, 0xCF, 0xB7, 0x4D, 0xE3, 0x64, 0x7F, 0x81, 0x5F, 0x14, 0x36, 0xFC, 0x3B, 0x56,
+	0x5F, 0x1D, 0x2F, 0xFC, 0x21, 0x73, 0x6E, 0xF0, 0xFA, 0xAB, 0x49, 0xFF, 0x00, 0x1F, 0x6C, 0xBF,
+	0xF1, 0xED, 0xFE, 0xAE, 0x4F, 0xF5, 0x9F, 0xDD, 0x6F, 0xEE, 0xB5, 0x4F, 0x3D, 0x3E, 0xAF, 0xFA,
+	0xFF, 0x00, 0x80, 0x11, 0xA3, 0x53, 0xB1, 0xEA, 0x33, 0x6B, 0xE9, 0x7B, 0x6E, 0x96, 0xCE, 0x8B,
+	0x6E, 0xD1, 0xB2, 0xAB, 0x49, 0x23, 0x6E, 0xF9, 0x96, 0x3F, 0xBA, 0xBF, 0xDD, 0x5F, 0xBD, 0x4C,
+	0xD3, 0xB5, 0x6F, 0xB3, 0xDE, 0xCD, 0xA9, 0x3C, 0x30, 0xEF, 0x99, 0x95, 0xA5, 0xB7, 0xFE, 0xF7,
+	0xF1, 0x7F, 0xDF, 0x3B, 0x95, 0x7E, 0xF5, 0x79, 0x6E, 0xA1, 0xFB, 0x41, 0x43, 0x0A, 0xF8, 0x36,
+	0x6B, 0x6F, 0x83, 0xFF, 0x00, 0x12, 0x26, 0x87, 0xE2, 0x14, 0xAB, 0x6F, 0xE0, 0x39, 0xA1, 0xF0,
+	0x5D, 0xC2, 0xC7, 0xE2, 0x09, 0x37, 0x2C, 0x7B, 0x6D, 0x3E, 0xEF, 0x9C, 0xDF, 0xBC, 0x55, 0xF9,
+	0x77, 0x37, 0xCD, 0x44, 0x9F, 0x1E, 0x2F, 0x24, 0xD5, 0xBC, 0x61, 0xA1, 0x0F, 0x80, 0x3F, 0x13,
+	0xBE, 0xD9, 0xF0, 0xF6, 0x26, 0xBA, 0xF1, 0xBD, 0xBA, 0xF8, 0x16, 0xE3, 0xCC, 0xD0, 0x63, 0x55,
+	0xDD, 0x24, 0x97, 0x6B, 0xF7, 0xAD, 0x95, 0x57, 0xE6, 0xF9, 0xB6, 0xFC, 0xBF, 0x7A, 0xA5, 0xCA,
+	0x8E, 0xCD, 0xA2, 0x95, 0x3A, 0xC9, 0x2B, 0x26, 0x7A, 0x25, 0xC4, 0xD3, 0xDC, 0x5D, 0x4D, 0xBF,
+	0xEF, 0x5D, 0x4A, 0xCD, 0xB7, 0x76, 0xED, 0xD2, 0x33, 0x7F, 0xBD, 0xFD, 0xEF, 0x97, 0xEF, 0x52,
+	0x5A, 0xDB, 0x95, 0x86, 0x42, 0xE8, 0xDB, 0xA1, 0x8B, 0x7A, 0xB4, 0x9F, 0x2A, 0xB6, 0xD5, 0xFB,
+	0xBF, 0xDD, 0xFB, 0xBF, 0xFD, 0x8F, 0xF0, 0xD7, 0x99, 0x43, 0xFB, 0x4B, 0xD8, 0x43, 0xA2, 0xF8,
+	0x4F, 0xC4, 0x8F, 0xF0, 0x5B, 0xE2, 0x34, 0x36, 0x7E, 0x3E, 0xB8, 0x6B, 0x5F, 0x03, 0xDE, 0x7F,
+	0xC2, 0x17, 0x70, 0xD1, 0xEB, 0x97, 0x1B, 0x96, 0x35, 0x8E, 0xC9, 0xBF, 0xE5, 0xE5, 0xBC, 0xC6,
+	0x55, 0xF9, 0x7E, 0xF3, 0x35, 0x58, 0x83, 0xE3, 0xA6, 0xA1, 0x6B, 0xE2, 0xEF, 0x14, 0x68, 0x37,
+	0x9F, 0xB3, 0xF7, 0xC4, 0xC7, 0xD5, 0x3C, 0x0B, 0x61, 0x25, 0xD7, 0x8B, 0x74, 0xD6, 0xF0, 0x1D,
+	0xD7, 0x99, 0xA1, 0xDB, 0xF9, 0x7F, 0x34, 0x97, 0x31, 0xAE, 0xD6, 0x85, 0x57, 0xE6, 0x6D, 0xD2,
+	0x6D, 0xFF, 0x00, 0x57, 0xFD, 0xDA, 0xAE, 0x68, 0xD9, 0xEA, 0x4A, 0xA3, 0x55, 0xD9, 0xA4, 0xF5,
+	0x3B, 0x4D, 0x7A, 0xEA, 0x18, 0xFC, 0x3F, 0x79, 0x34, 0xC9, 0xFB, 0xE8, 0x56, 0x6D, 0xDE, 0x63,
+	0x2E, 0xD6, 0x8D, 0x57, 0xE5, 0x6D, 0xDF, 0xF7, 0xD7, 0xFD, 0xF3, 0xFD, 0xDA, 0x87, 0xFE, 0x09,
+	0x89, 0x61, 0x6D, 0x37, 0x82, 0xF5, 0x4D, 0x63, 0xC9, 0xB8, 0x4B, 0x8B, 0xED, 0x4A, 0x38, 0xA2,
+	0x59, 0x2D, 0xF6, 0xC7, 0x35, 0xBA, 0xAD, 0xBF, 0xEF, 0x15, 0xBF, 0x8B, 0xE6, 0x89, 0xBF, 0xBB,
+	0xFF, 0x00, 0x02, 0xFE, 0x1F, 0x1D, 0xF8, 0xC9, 0xFB, 0x50, 0x68, 0xF1, 0xFC, 0x0F, 0x87, 0xC7,
+	0x97, 0x3E, 0x00, 0xF1, 0xB6, 0x9F, 0xE1, 0xEF, 0x17, 0x5B, 0xDD, 0x59, 0xF8, 0x5F, 0xC4, 0x5A,
+	0x97, 0x85, 0xEE, 0x2D, 0xAC, 0x75, 0x29, 0x95, 0x7C, 0xB9, 0x15, 0x27, 0x65, 0xF2, 0xDB, 0x6B,
+	0x7D, 0xEF, 0x99, 0xB6, 0xD7, 0xD5, 0x1F, 0xF0, 0x4E, 0x1D, 0x5B, 0x4D, 0xFF, 0x00, 0x85, 0x47,
+	0x6E, 0xF7, 0x9A, 0x53, 0x5F, 0x5C, 0x5D, 0x5C, 0x79, 0xD6, 0xB7, 0x92, 0x37, 0xFA, 0x9B, 0x5F,
+	0x32, 0x4D, 0xB6, 0xFF, 0x00, 0x2F, 0xFB, 0x3E, 0x5F, 0xCC, 0xBF, 0xDD, 0xDB, 0xF2, 0xEE, 0xF9,
+	0x7F, 0x3B, 0xF1, 0x22, 0xB3, 0x8E, 0x4E, 0x92, 0xB7, 0x5F, 0xBF, 0xB7, 0xAE, 0xBD, 0x4F, 0xAE,
+	0xE1, 0x3A, 0x7C, 0xB8, 0xA9, 0xCE, 0x4A, 0xDF, 0xF0, 0x53, 0x57, 0xF4, 0x3E, 0xBB, 0xF0, 0xAC,
+	0x68, 0x23, 0x8D, 0x3E, 0x53, 0xB5, 0x57, 0xF8, 0xBE, 0x6D, 0xB5, 0xD2, 0x42, 0x90, 0xC6, 0xDF,
+	0xB9, 0xFF, 0x00, 0xD0, 0xBE, 0xED, 0x43, 0xE0, 0x5F, 0x0E, 0xE9, 0x5A, 0x9E, 0x87, 0x1D, 0x8D,
+	0xB6, 0xA4, 0xAD, 0xAB, 0x7C, 0xCB, 0xF6, 0x79, 0xAE, 0x3C, 0xBD, 0xDF, 0x2A, 0xF9, 0x6B, 0x1E,
+	0xE5, 0xDA, 0xCC, 0xCD, 0xBB, 0xEF, 0x32, 0xFF, 0x00, 0xB3, 0xBA, 0xBA, 0xBD, 0x3F, 0x4E, 0x7B,
+	0x3F, 0x10, 0xDA, 0xE8, 0x96, 0x09, 0x1C, 0x32, 0x5F, 0x5C, 0x2A, 0x5A, 0xCD, 0x71, 0xFE, 0xB5,
+	0x55, 0x5A, 0x38, 0xDA, 0x46, 0x89, 0xBE, 0xEB, 0x2C, 0x92, 0x6D, 0xDB, 0xF3, 0x7C, 0xAB, 0xBB,
+	0xF8, 0xAB, 0xF9, 0x1B, 0x1B, 0x82, 0xC5, 0x56, 0xA9, 0x75, 0x1B, 0xA7, 0x6B, 0x35, 0xAE, 0xFD,
+	0x3D, 0x75, 0x49, 0xF6, 0xBA, 0xBD, 0x8F, 0xD2, 0xB0, 0xF1, 0xE6, 0x8F, 0x32, 0x6B, 0x4B, 0xBF,
+	0xBB, 0x7F, 0xF3, 0xF4, 0xD4, 0xE7, 0xAE, 0x2C, 0x6F, 0xE3, 0x5D, 0xEF, 0x63, 0x22, 0xEE, 0x5D,
+	0xCB, 0xFB, 0xA6, 0xFB, 0xB5, 0x77, 0xC3, 0xB1, 0x43, 0x26, 0xB1, 0x6C, 0x9A, 0xC4, 0xD2, 0x5B,
+	0x42, 0xB2, 0xAF, 0x9B, 0x37, 0xD9, 0xD9, 0xBE, 0x5A, 0x35, 0xD4, 0xB7, 0x9A, 0xFE, 0xF6, 0x4D,
+	0xEB, 0x33, 0x5A, 0xCB, 0xB1, 0xAE, 0x35, 0x0B, 0xA9, 0x1A, 0x5B, 0xA6, 0xF9, 0xBE, 0xEA, 0xAE,
+	0xE6, 0xF9, 0x76, 0xFC, 0xCD, 0xFC, 0x35, 0x1D, 0xE7, 0x84, 0x35, 0x4F, 0xEC, 0xD8, 0xF5, 0x17,
+	0xD2, 0xB4, 0xF9, 0x2D, 0xE6, 0xE1, 0x26, 0x8E, 0xFA, 0x46, 0x5D, 0xDF, 0xDD, 0xF9, 0x7E, 0xEB,
+	0x7F, 0xB3, 0xF7, 0xAB, 0xE6, 0xA5, 0x2A, 0xD4, 0x25, 0xED, 0x95, 0x36, 0xE2, 0xB5, 0xD7, 0x6B,
+	0x5F, 0x76, 0xEE, 0xB4, 0x76, 0xF2, 0xF5, 0x3D, 0x7A, 0x78, 0x3A, 0x35, 0x23, 0xCB, 0xCD, 0xAB,
+	0xD2, 0xD7, 0xD6, 0xFF, 0x00, 0xF8, 0x0B, 0x33, 0x7E, 0x20, 0xEA, 0x13, 0x6B, 0xFE, 0x29, 0xBC,
+	0xD5, 0x74, 0xBB, 0x5B, 0x86, 0x5B, 0x8B, 0x86, 0x6D, 0xDE, 0x43, 0x2E, 0xDF, 0x99, 0x9B, 0xF8,
+	0xBF, 0xDE, 0xAC, 0x7B, 0x5D, 0x06, 0xFE, 0xEA, 0x46, 0x4B, 0x9D, 0xB6, 0xB0, 0xC6, 0xBF, 0x34,
+	0xD7, 0x0B, 0xB7, 0xFF, 0x00, 0xDA, 0xFB, 0xBF, 0x76, 0xB4, 0xAF, 0x34, 0xA5, 0x87, 0x57, 0x87,
+	0x48, 0x7B, 0x7D, 0x22, 0x3B, 0xBB, 0xB8, 0x24, 0x9A, 0xCE, 0xCE, 0x6D, 0x46, 0x45, 0x96, 0x68,
+	0xD3, 0xEF, 0xB2, 0xAF, 0xF1, 0x6D, 0xDC, 0xBB, 0x9B, 0x6F, 0xF1, 0x55, 0xCD, 0x37, 0x40, 0x8E,
+	0x5D, 0x76, 0xC2, 0xCF, 0x58, 0xD0, 0xAC, 0xDA, 0x3B, 0xEB, 0xC5, 0xB7, 0xDD, 0x6F, 0x75, 0x23,
+	0x3A, 0xB3, 0x32, 0xAE, 0xEF, 0x99, 0x76, 0xFC, 0xBB, 0xAB, 0xE7, 0xF9, 0x6B, 0x66, 0x19, 0x82,
+	0x5B, 0xCA, 0x6F, 0x4D, 0x52, 0xBB, 0x7D, 0x7A, 0xE8, 0x75, 0xD5, 0xC2, 0x53, 0xA3, 0x19, 0x54,
+	0x96, 0x89, 0x6A, 0xF7, 0xFF, 0x00, 0xE4, 0x6E, 0x66, 0x47, 0xAC, 0x69, 0x5A, 0x2C, 0x8B, 0x6D,
+	0xA2, 0x23, 0x3C, 0xCD, 0xF3, 0x35, 0xF4, 0xDF, 0x7B, 0xFE, 0x02, 0xBF, 0xC3, 0xFF, 0x00, 0xA1,
+	0x53, 0x3F, 0xB3, 0xF5, 0x5B, 0xED, 0xB7, 0xF3, 0x42, 0xCA, 0xAD, 0xF3, 0x2D, 0xC5, 0xC7, 0xCB,
+	0x1B, 0x2E, 0xEF, 0xBD, 0xBB, 0xF8, 0xBF, 0xE0, 0x3B, 0xA8, 0xF1, 0xD6, 0x87, 0x0E, 0x93, 0xAC,
+	0x5C, 0x5B, 0x69, 0xBB, 0x99, 0x61, 0x95, 0xA2, 0x6D, 0xCD, 0xF7, 0x7E, 0xEF, 0xFF, 0x00, 0x15,
+	0x55, 0xAC, 0xE0, 0xF1, 0x26, 0xA9, 0xA7, 0x2F, 0xF6, 0x96, 0xAB, 0x71, 0x1E, 0x97, 0x1B, 0x32,
+	0x5B, 0xC9, 0x70, 0xCC, 0xC8, 0xBF, 0xDE, 0x58, 0xD7, 0xF8, 0x9B, 0xE6, 0xFF, 0x00, 0xC7, 0xBE,
+	0x6D, 0xB5, 0xA5, 0x1F, 0x6D, 0x1A, 0x8E, 0x94, 0xD3, 0xD2, 0xD6, 0xB6, 0xDD, 0x37, 0xF2, 0xDD,
+	0x7A, 0xDB, 0xB9, 0xE7, 0xBB, 0x3A, 0x9C, 0x8F, 0x65, 0x7D, 0x11, 0xDE, 0xF8, 0x66, 0xED, 0x2C,
+	0xAD, 0x7E, 0xD9, 0x73, 0x03, 0x34, 0x76, 0x3A, 0x0C, 0x96, 0xB6, 0xAA, 0xDF, 0xEB, 0x2E, 0x99,
+	0xA4, 0x66, 0xDC, 0xAB, 0xFC, 0x2B, 0xF3, 0x37, 0xFE, 0x3B, 0x57, 0xF4, 0x4D, 0x4A, 0xF2, 0x5D,
+	0x5B, 0x4D, 0xB1, 0xB8, 0x78, 0x5D, 0x75, 0x48, 0x9B, 0xCA, 0x5B, 0x76, 0xDD, 0xE5, 0xED, 0xFE,
+	0x26, 0xFF, 0x00, 0x65, 0x76, 0xB6, 0xEF, 0xEE, 0xED, 0x66, 0xFE, 0x1D, 0xB5, 0xC8, 0x5B, 0xDA,
+	0xD9, 0xEA, 0x11, 0x0B, 0x1B, 0x3B, 0x7B, 0x78, 0x5E, 0xC6, 0xCE, 0x69, 0xEE, 0x2F, 0x2E, 0x13,
+	0xCC, 0x96, 0xE1, 0x55, 0x57, 0xF8, 0x99, 0xB6, 0xFC, 0xDB, 0xBE, 0xEA, 0xFD, 0xDD, 0xAB, 0x5A,
+	0xFE, 0x1A, 0xD5, 0x34, 0xBD, 0x2E, 0x5B, 0x7B, 0xFD, 0x47, 0x52, 0xB3, 0x91, 0xA1, 0xB0, 0x91,
+	0x2C, 0xEC, 0xED, 0xEE, 0x3C, 0xC9, 0x23, 0xF3, 0x19, 0x99, 0xB7, 0x7F, 0x79, 0xBF, 0x78, 0xFF,
+	0x00, 0x2F, 0xFB, 0x4B, 0xF7, 0x76, 0xED, 0xAF, 0xB0, 0xA6, 0xE3, 0x3A, 0x70, 0xA9, 0x89, 0x57,
+	0x8C, 0x6C, 0x95, 0xAF, 0xF7, 0x3B, 0x3B, 0xB6, 0xF6, 0xDA, 0xCA, 0xDB, 0x75, 0x2E, 0x9C, 0xAC,
+	0xB9, 0x28, 0x3B, 0x37, 0x7B, 0xED, 0xBE, 0x8B, 0xAF, 0x45, 0xF8, 0xDF, 0x73, 0x4F, 0x51, 0x89,
+	0x2F, 0x3C, 0x71, 0x6D, 0x60, 0xEA, 0xAC, 0x8D, 0xA5, 0xDD, 0x33, 0x42, 0xDF, 0x75, 0xBF, 0xD1,
+	0xE4, 0xFB, 0xD5, 0x9B, 0x6B, 0x6A, 0x8D, 0xE1, 0xA6, 0xB3, 0x77, 0xDB, 0xE6, 0x5E, 0x5A, 0xF9,
+	0xBB, 0x9B, 0x6B, 0x7F, 0xAB, 0xBA, 0xDD, 0xFF, 0x00, 0x02, 0xA9, 0x06, 0xB3, 0x61, 0xA8, 0x78,
+	0xB6, 0xFA, 0xE2, 0xCE, 0x65, 0x3E, 0x5E, 0x83, 0x75, 0xF3, 0x32, 0xB7, 0xCB, 0xFE, 0x8F, 0x32,
+	0xFF, 0x00, 0xEC, 0xDF, 0xC5, 0x4D, 0x53, 0x0A, 0xE8, 0xB0, 0xDB, 0x3C, 0xF1, 0xA7, 0x99, 0x7D,
+	0x0E, 0xD5, 0xF3, 0x57, 0x73, 0x2A, 0xC7, 0x22, 0xB7, 0xCB, 0xFE, 0xF4, 0x8B, 0x5D, 0xD8, 0x28,
+	0xAF, 0xA9, 0xC6, 0xFD, 0x1C, 0xF5, 0x7E, 0x6D, 0x24, 0x63, 0x8C, 0xE6, 0x96, 0x2A, 0x49, 0x7E,
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+	0x6A, 0xCB, 0xB9, 0x96, 0x45, 0xF9, 0x9E, 0x45, 0x5F, 0xE2, 0x56, 0x6D, 0xCD, 0xB5, 0x7E, 0xEA,
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+	0xBE, 0x12, 0x85, 0xBF, 0xDA, 0xFF, 0x00, 0x90, 0x82, 0xD7, 0x65, 0x39, 0x54, 0xC4, 0xE0, 0xE5,
+	0x56, 0x7A, 0xE9, 0x3F, 0x5D, 0x14, 0x56, 0xBF, 0xE6, 0x7A, 0x55, 0x1D, 0x3A, 0x55, 0x54, 0x23,
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+	0x7C, 0xC9, 0x1B, 0xFD, 0x9D, 0xDF, 0x75, 0x7F, 0xE0, 0x55, 0xC7, 0xF8, 0xAB, 0xF6, 0x94, 0xF1,
+	0x3E, 0xBD, 0x0B, 0xC3, 0x0D, 0x9D, 0xC3, 0xB7, 0xFC, 0xF4, 0xBA, 0xBA, 0x66, 0xDB, 0x5C, 0x5E,
+	0xA1, 0xAD, 0x5C, 0xF8, 0x8A, 0x62, 0xDE, 0x20, 0xD7, 0x9A, 0x45, 0xDB, 0xF2, 0xDB, 0xC2, 0xBB,
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+	0x95, 0xA7, 0xB3, 0x34, 0xAB, 0xBB, 0x74, 0x7B, 0xBF, 0xBC, 0xDF, 0xDE, 0x6F, 0xF3, 0xF2, 0xAF,
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+	0xF3, 0x5B, 0xE5, 0xFE, 0x1D, 0xAA, 0xBB, 0x7E, 0xF5, 0x79, 0x7C, 0x51, 0x1C, 0x0F, 0xD4, 0xE3,
+	0x4E, 0x6E, 0xCE, 0xEE, 0xDD, 0xEF, 0xCA, 0xFB, 0x7E, 0x37, 0xF5, 0x3D, 0x0C, 0x8A, 0x38, 0xC5,
+	0x8B, 0x75, 0x69, 0xAD, 0x34, 0xBF, 0x6B, 0x5D, 0x77, 0xD8, 0xEB, 0xBE, 0x19, 0x78, 0x86, 0xCF,
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+	0x5F, 0x87, 0xFE, 0x1D, 0x5B, 0xAA, 0x4F, 0x79, 0xAA, 0xAF, 0xDA, 0x19, 0xB7, 0x4A, 0xB3, 0x5A,
+	0xEF, 0xDB, 0xFE, 0x77, 0x57, 0x11, 0x3E, 0xB5, 0x61, 0xA6, 0x98, 0xFC, 0x3D, 0xF6, 0xC8, 0xD5,
+	0xE3, 0x66, 0x58, 0xA3, 0x85, 0xBE, 0x66, 0xDD, 0xF3, 0x7D, 0xDF, 0xF7, 0x9B, 0xFC, 0xEE, 0xAA,
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+	0xFF, 0x00, 0x7C, 0xD4, 0x5E, 0x28, 0xFD, 0x94, 0x75, 0xEB, 0x1D, 0xD6, 0x7A, 0xAE, 0xB1, 0x25,
+	0x9D, 0xC3, 0x36, 0xFB, 0x88, 0x59, 0x7C, 0xBF, 0x2D, 0x99, 0x57, 0xE5, 0xAF, 0xAB, 0xBF, 0xE0,
+	0x85, 0x9F, 0x13, 0x3C, 0x49, 0xE1, 0x9F, 0x18, 0x78, 0xE7, 0xC0, 0x3E, 0x1B, 0xF0, 0x33, 0x6B,
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+	0xCB, 0xF9, 0x5B, 0xEF, 0x79, 0x8B, 0xFE, 0x56, 0xBE, 0x78, 0xFF, 0x00, 0x82, 0x86, 0x7C, 0x5E,
+	0xF1, 0x87, 0x87, 0x7F, 0x6A, 0x4D, 0x7B, 0x4D, 0xD4, 0xF4, 0x7B, 0x8D, 0x2E, 0x46, 0x58, 0xCF,
+	0xD8, 0xEE, 0x97, 0xCB, 0x92, 0x3F, 0xF8, 0x0F, 0xFB, 0xCA, 0xDF, 0x7A, 0xBE, 0xB7, 0x86, 0xB0,
+	0xB3, 0xA7, 0x85, 0x93, 0x8B, 0xBE, 0xA7, 0xCA, 0xE7, 0xD8, 0x8F, 0x69, 0x98, 0x72, 0xF2, 0xE9,
+	0x14, 0xB5, 0xEF, 0x73, 0x3B, 0xC3, 0x3F, 0xB2, 0x5E, 0x89, 0x6F, 0xE0, 0x5B, 0xCD, 0x7B, 0xC5,
+	0x5A, 0xC2, 0xDC, 0xA5, 0xAC, 0xBB, 0x62, 0x8F, 0xEF, 0x7F, 0xBB, 0xFF, 0x00, 0xB3, 0x56, 0x3D,
+	0xBF, 0xC0, 0x1F, 0x04, 0xFD, 0xA1, 0x3E, 0x46, 0xF2, 0xDB, 0xE5, 0xFE, 0x1A, 0xE6, 0x6C, 0xFF,
+	0x00, 0x68, 0x8D, 0x62, 0x3F, 0x01, 0xEA, 0x5A, 0x6C, 0xD7, 0x9F, 0xC4, 0xAC, 0xB1, 0xB3, 0x7F,
+	0xBB, 0xBA, 0xB0, 0xB4, 0xBF, 0x8D, 0x5A, 0xAF, 0x9F, 0xBE, 0x6B, 0x96, 0xDB, 0xFC, 0x4B, 0xBB,
+	0x6F, 0xFE, 0x3D, 0x5F, 0x51, 0x18, 0xD6, 0xEE, 0x7C, 0xFC, 0xE5, 0x4E, 0xF6, 0x91, 0xE8, 0xF2,
+	0x7E, 0xCA, 0xFE, 0x03, 0xBE, 0x65, 0x74, 0xBF, 0xDA, 0xAB, 0xF7, 0x97, 0xE5, 0xF9, 0x7E, 0x5D,
+	0xD5, 0x15, 0xD7, 0xEC, 0x8D, 0xE0, 0xF8, 0xD9, 0x7C, 0xED, 0x6D, 0x76, 0xC8, 0xBF, 0x79, 0x57,
+	0xFF, 0x00, 0x1E, 0xAE, 0x33, 0xFE, 0x17, 0x66, 0xAB, 0x1D, 0xE2, 0xFD, 0x9A, 0xF1, 0x5D, 0x7C,
+	0xDF, 0xBB, 0xF3, 0x7F, 0xEC, 0xD5, 0x63, 0xC4, 0x1F, 0xB4, 0x26, 0xB1, 0x79, 0x0B, 0x59, 0xDE,
+	0x6D, 0x77, 0x56, 0xF9, 0x64, 0x5F, 0xEE, 0xFF, 0x00, 0x77, 0xFC, 0xFF, 0x00, 0xEC, 0xD4, 0x3F,
+	0x6D, 0xDC, 0x7C, 0xF4, 0xF6, 0xB1, 0xBD, 0xA8, 0x7E, 0xC8, 0x7E, 0x15, 0x32, 0x32, 0x58, 0x78,
+	0x9D, 0x5E, 0x3D, 0xBB, 0x77, 0x7D, 0xEF, 0xF3, 0xFC, 0x54, 0x2F, 0xEC, 0x7B, 0xE1, 0xEB, 0x88,
+	0x5A, 0x3F, 0xED, 0xEF, 0xBB, 0xF2, 0xAE, 0xEF, 0xE1, 0xAE, 0x2A, 0x2F, 0x8F, 0x1E, 0x21, 0xB5,
+	0x59, 0x1E, 0x1B, 0x9F, 0x99, 0x93, 0xEE, 0xB7, 0xF0, 0xD3, 0xED, 0x7E, 0x3F, 0x78, 0x91, 0x55,
+	0xBC, 0xEB, 0x8F, 0x97, 0xEE, 0xBE, 0xD6, 0xDB, 0xB7, 0xFD, 0x9A, 0xAE, 0x5A, 0xFF, 0x00, 0x65,
+	0x8F, 0xF7, 0x76, 0x2C, 0xF8, 0xCB, 0xF6, 0x7F, 0xD1, 0xFC, 0x3B, 0xAD, 0x26, 0x89, 0xF6, 0x0B,
+	0xC9, 0x37, 0x2F, 0xFC, 0x7C, 0x47, 0xF3, 0x2B, 0x33, 0x7F, 0x0D, 0x6E, 0xE8, 0x5F, 0xB2, 0x0D,
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+	0xB6, 0x5F, 0xB5, 0x5D, 0x5C, 0x49, 0x27, 0xDE, 0xFF, 0x00, 0x9E, 0x71, 0xB3, 0x6D, 0x5F, 0xBD,
+	0xF7, 0x56, 0xBE, 0xDC, 0xFF, 0x00, 0x82, 0x61, 0xFC, 0x56, 0xD0, 0x74, 0xFF, 0x00, 0xD8, 0x7F,
+	0xC0, 0x7E, 0x04, 0xBE, 0xBF, 0x6B, 0xCD, 0x4A, 0xFA, 0xD6, 0xFA, 0x76, 0xBA, 0x86, 0x48, 0x76,
+	0xE9, 0xF1, 0xC3, 0x71, 0x23, 0x25, 0xBC, 0xAA, 0xD2, 0x79, 0xDB, 0xA4, 0xDD, 0xB5, 0x76, 0xAB,
+	0x2A, 0xFF, 0x00, 0x7B, 0x6D, 0x7E, 0x70, 0xFC, 0x60, 0xFD, 0xAE, 0x3E, 0x09, 0xF8, 0x9B, 0xE1,
+	0xED, 0xF7, 0x86, 0x3C, 0x3D, 0xE3, 0x38, 0xDE, 0xEE, 0xF2, 0xC1, 0x56, 0xDE, 0x15, 0x56, 0xF9,
+	0x99, 0x9B, 0xEE, 0xFC, 0xDF, 0x77, 0xFD, 0xDA, 0xFB, 0x13, 0xFE, 0x08, 0xCF, 0xE1, 0x5F, 0x85,
+	0x7A, 0x97, 0xC2, 0xF9, 0x2F, 0xFE, 0x37, 0xFC, 0x42, 0xB7, 0xD0, 0xDE, 0xC7, 0x49, 0x92, 0xE3,
+	0x4D, 0xFE, 0xD2, 0xD5, 0xA3, 0xB3, 0xF3, 0x1B, 0xCE, 0xF9, 0x76, 0xAC, 0x9F, 0xEB, 0x3F, 0x76,
+	0xAD, 0xF2, 0xAF, 0xDD, 0xDD, 0xBB, 0xFB, 0xB5, 0xF0, 0xBE, 0x22, 0x64, 0x75, 0x33, 0xFC, 0x9E,
+	0x18, 0x48, 0xC6, 0xF2, 0xE6, 0xE6, 0x8D, 0xF4, 0xB3, 0x49, 0xBB, 0xFD, 0xDA, 0x33, 0xE9, 0xB8,
+	0x67, 0x1B, 0xFD, 0x9F, 0x5E, 0xA5, 0x59, 0xAB, 0xAB, 0x5A, 0xDE, 0xB6, 0x5D, 0x35, 0x76, 0x6E,
+	0xF6, 0xDB, 0xBE, 0xC7, 0xDF, 0x56, 0x5E, 0x28, 0xD1, 0xA1, 0xF0, 0x96, 0x89, 0xE0, 0xC8, 0xE4,
+	0x69, 0x22, 0xD4, 0x2D, 0xEF, 0xAE, 0x6E, 0xB5, 0x68, 0xDA, 0x3F, 0x22, 0xCE, 0x4F, 0x32, 0x3D,
+	0xB0, 0xB2, 0xB4, 0x8B, 0x26, 0xE6, 0x55, 0xDC, 0xBB, 0x55, 0x97, 0xEF, 0x7C, 0xD5, 0xA9, 0x71,
+	0xE1, 0xC6, 0xB7, 0xB3, 0x87, 0x55, 0xD2, 0xEE, 0x5A, 0xE6, 0x3B, 0x85, 0xCA, 0xC8, 0xBF, 0x2E,
+	0xE5, 0xFF, 0x00, 0x67, 0xFB, 0xD5, 0xE3, 0xBE, 0x0F, 0xF1, 0xF7, 0xC0, 0xDD, 0x37, 0xE1, 0x2E,
+	0xA9, 0xF1, 0x23, 0xC4, 0x3E, 0x36, 0xB1, 0xB6, 0xBA, 0x87, 0x49, 0x59, 0xAC, 0x2C, 0xF5, 0x0D,
+	0x5A, 0x3B, 0x36, 0x92, 0x6F, 0x25, 0x99, 0xA3, 0xFD, 0xE7, 0xFA, 0xFF, 0x00, 0xE1, 0x5D, 0xB1,
+	0xFF, 0x00, 0xEC, 0xD5, 0xEB, 0x1F, 0x04, 0xB5, 0xBD, 0x3F, 0xC4, 0x3E, 0x05, 0xBF, 0xD4, 0xB4,
+	0xAB, 0x9F, 0x36, 0x09, 0x2E, 0xAD, 0x5A, 0x1F, 0xF6, 0x59, 0xA1, 0x99, 0x9B, 0xE5, 0xFE, 0xF7,
+	0xCA, 0xBF, 0xF7, 0xCD, 0x7F, 0x2C, 0xE7, 0x19, 0x06, 0x33, 0x0F, 0x49, 0x63, 0x6A, 0xAE, 0x58,
+	0x4E, 0x2E, 0xDE, 0xB4, 0xED, 0x16, 0x9F, 0x66, 0xED, 0xA7, 0xDE, 0x7E, 0x95, 0x83, 0xC6, 0x50,
+	0xC4, 0x4A, 0x38, 0x59, 0x24, 0xDC, 0x74, 0xBA, 0x7F, 0xCD, 0xAD, 0xFB, 0x7A, 0x89, 0x6F, 0x26,
+	0xDD, 0x0F, 0x5C, 0x9B, 0xF8, 0x7C, 0xAB, 0x55, 0x5D, 0xBF, 0xF5, 0xDB, 0x76, 0xD5, 0xFF, 0x00,
+	0xBE, 0x6B, 0x6E, 0xF8, 0x7F, 0xC4, 0xD9, 0x2D, 0x11, 0x9B, 0xE6, 0xF1, 0x06, 0x9B, 0x16, 0xD5,
+	0xFF, 0x00, 0xA6, 0x76, 0xFB, 0x7F, 0xF6, 0x6A, 0xE6, 0x34, 0xD9, 0x9D, 0xBC, 0x23, 0xAD, 0x79,
+	0x9B, 0xBE, 0x6B, 0xCB, 0x54, 0xF9, 0x5B, 0xFE, 0x9A, 0x5C, 0x37, 0xFE, 0xCB, 0x5D, 0x55, 0xC2,
+	0xEE, 0xF1, 0x42, 0x23, 0xED, 0xF9, 0xBC, 0x69, 0x0A, 0xED, 0xFF, 0x00, 0x76, 0x35, 0xAF, 0x37,
+	0x07, 0x26, 0xA9, 0x45, 0x3E, 0xCB, 0xF1, 0x72, 0x7F, 0xA9, 0xD0, 0xB9, 0x61, 0xCC, 0xB7, 0xB5,
+	0xFF, 0x00, 0xAF, 0xC0, 0xCA, 0xD4, 0x19, 0x26, 0xB1, 0xB7, 0xFF, 0x00, 0xA6, 0xDE, 0x20, 0xBC,
+	0x76, 0x6D, 0xBF, 0xEC, 0xC7, 0xFF, 0x00, 0xC5, 0x55, 0x8F, 0xB7, 0x47, 0x71, 0xE3, 0x4B, 0x5D,
+	0x2A, 0x0B, 0x46, 0x56, 0x5F, 0x16, 0xC9, 0x3D, 0xC4, 0xD3, 0x49, 0xF2, 0xB3, 0x35, 0xC6, 0xDF,
+	0x97, 0xFE, 0x03, 0xB6, 0xB3, 0xD9, 0x61, 0x9B, 0x49, 0xD2, 0xD2, 0xF1, 0xE4, 0x8E, 0x39, 0xB5,
+	0xCB, 0xCF, 0x35, 0x95, 0x77, 0x32, 0xAB, 0x2C, 0x3B, 0xAA, 0xCD, 0x85, 0xED, 0xF5, 0xD7, 0xC4,
+	0x4B, 0x18, 0xE6, 0xBB, 0xF3, 0x16, 0xCB, 0x51, 0x86, 0x05, 0x56, 0xDA, 0xBF, 0x76, 0x45, 0x56,
+	0x66, 0xFF, 0x00, 0xBE, 0x68, 0xA7, 0x5A, 0x4A, 0xB4, 0x17, 0x4B, 0xC6, 0xFF, 0x00, 0x72, 0xD3,
+	0xFA, 0xF3, 0x7D, 0x09, 0xAD, 0x2F, 0xDD, 0xC9, 0xFA, 0xAE, 0xFB, 0xB9, 0x2F, 0xCA, 0xEE, 0xFE,
+	0x43, 0xFC, 0x40, 0xEF, 0xFF, 0x00, 0x08, 0xFD, 0xE3, 0xEC, 0x66, 0x6F, 0xEC, 0xB5, 0xF9, 0x63,
+	0xFF, 0x00, 0x6B, 0x54, 0x91, 0xAB, 0x85, 0xF8, 0xB1, 0x6F, 0x0D, 0xBD, 0xAF, 0x87, 0x9F, 0x7C,
+	0x8D, 0x34, 0xCB, 0x71, 0x32, 0x48, 0xDF, 0x2C, 0x7B, 0x95, 0xBC, 0xB5, 0x56, 0xFF, 0x00, 0xBE,
+	0x5A, 0xBB, 0x2D, 0x57, 0x54, 0xB0, 0xB5, 0x7B, 0x7D, 0x1F, 0x59, 0xB6, 0x99, 0xAD, 0xAF, 0xB4,
+	0x85, 0xDD, 0x25, 0xAB, 0x7E, 0xF2, 0x16, 0x5B, 0xA9, 0xA4, 0x56, 0x5F, 0xEF, 0x57, 0xCE, 0xFF,
+	0x00, 0xB6, 0xFF, 0x00, 0xED, 0x59, 0xE0, 0x9F, 0xD9, 0x9F, 0xC4, 0xBE, 0x1B, 0xBF, 0xF8, 0x91,
+	0xAB, 0xC3, 0x3E, 0x83, 0x26, 0x93, 0x37, 0x95, 0x36, 0x8B, 0x67, 0x24, 0x92, 0xDB, 0xC8, 0xB2,
+	0x47, 0xB5, 0x9E, 0x3F, 0xBD, 0xFB, 0xCF, 0x33, 0xE6, 0xFE, 0xEB, 0x2D, 0x7E, 0x91, 0xE1, 0xC4,
+	0x68, 0xD4, 0xE2, 0xEC, 0x33, 0x6A, 0xED, 0x46, 0x49, 0x7A, 0xF2, 0xC9, 0xFE, 0x4C, 0xF1, 0x38,
+	0xB2, 0x1C, 0xF8, 0x0A, 0xF1, 0x5B, 0xAB, 0x7F, 0xE9, 0x51, 0x3D, 0xAB, 0xC2, 0x7A, 0x5C, 0x31,
+	0xC6, 0xB7, 0x77, 0xF6, 0xD6, 0xAE, 0xEC, 0xCA, 0xAC, 0xDB, 0xB6, 0xFF, 0x00, 0xDF, 0x35, 0xD5,
+	0xF8, 0x77, 0x50, 0x45, 0xBC, 0xB8, 0xB6, 0x7D, 0x11, 0x63, 0xF2, 0xEE, 0x36, 0xAB, 0x2F, 0xFC,
+	0xB4, 0xAF, 0xCF, 0x2B, 0x7F, 0xF8, 0x2D, 0x9F, 0xEC, 0x9D, 0xF6, 0xCD, 0x89, 0xE3, 0x9B, 0xE8,
+	0xE3, 0x8D, 0xBE, 0x5F, 0x33, 0x4B, 0x99, 0x7E, 0x6F, 0xFB, 0xE6, 0xBA, 0xAD, 0x3F, 0xFE, 0x0B,
+	0xB1, 0xFB, 0x1F, 0xE9, 0xB0, 0xEC, 0x87, 0xC6, 0xDF, 0x3F, 0xDE, 0x95, 0x9A, 0xC2, 0x45, 0xDD,
+	0xFF, 0x00, 0x8E, 0xD7, 0xF5, 0x5D, 0x1A, 0x75, 0x74, 0x69, 0x1F, 0x8F, 0xD4, 0xA3, 0x2E, 0x5D,
+	0x53, 0x3E, 0xBA, 0xFD, 0xA5, 0x35, 0x88, 0x74, 0xDF, 0x86, 0xFA, 0x85, 0xE5, 0xBF, 0x92, 0x8B,
+	0x1D, 0x9C, 0x8C, 0xCA, 0xCD, 0xF7, 0xBE, 0x5D, 0xCB, 0xB7, 0xFE, 0x04, 0xB5, 0x97, 0xE0, 0xFB,
+	0x77, 0xD6, 0xB4, 0xDD, 0x13, 0x55, 0xB6, 0x7B, 0x59, 0x2E, 0xB5, 0x46, 0x5B, 0x3B, 0x59, 0x26,
+	0x6D, 0xB1, 0x46, 0xCA, 0xAB, 0xBA, 0x4D, 0xBF, 0xDE, 0x66, 0x6D, 0xDF, 0xDD, 0x5A, 0xFC, 0xD4,
+	0xFD, 0xB9, 0x3F, 0xE0, 0xB0, 0xDF, 0x0F, 0x7E, 0x26, 0x78, 0x17, 0xFE, 0x11, 0x8F, 0x84, 0x5E,
+	0x30, 0x93, 0x54, 0xD4, 0xB5, 0x86, 0x6B, 0x7D, 0xCB, 0x13, 0x45, 0x1D, 0x8C, 0x6C, 0xBB, 0x59,
+	0xBE, 0x6F, 0xBC, 0xDB, 0x6B, 0xEC, 0x3F, 0x02, 0x7C, 0x40, 0xD5, 0x7E, 0x1C, 0xFE, 0xCB, 0xFA,
+	0x27, 0x88, 0x74, 0xDB, 0x05, 0xD6, 0xB5, 0x06, 0xD2, 0xE6, 0xBA, 0xD2, 0x6D, 0x6F, 0x25, 0x65,
+	0x81, 0x6E, 0xB7, 0x49, 0x0A, 0xAC, 0x9B, 0x7E, 0x6D, 0xAD, 0xE5, 0x2E, 0xEF, 0xF7, 0xAB, 0xF1,
+	0xFF, 0x00, 0x17, 0x32, 0x19, 0x67, 0x12, 0xC1, 0xCB, 0x6B, 0x49, 0xC7, 0xB6, 0x92, 0x71, 0x4E,
+	0xEF, 0x7B, 0x7D, 0xFE, 0x8C, 0xFB, 0x5E, 0x0B, 0xA9, 0x52, 0x8D, 0x1A, 0xEA, 0xDB, 0x45, 0xCB,
+	0x5F, 0xEE, 0xAE, 0x97, 0xF5, 0xEB, 0x63, 0xEA, 0xAF, 0x1C, 0xFC, 0x3F, 0xBA, 0xF8, 0x0F, 0x75,
+	0xE1, 0xFF, 0x00, 0x16, 0xDE, 0x78, 0x92, 0x4F, 0xED, 0x8B, 0xC6, 0x8E, 0xF6, 0xD6, 0xEA, 0x14,
+	0x59, 0x5A, 0x36, 0x5D, 0xAC, 0xBB, 0x91, 0xBE, 0x5D, 0xAB, 0xF2, 0xD6, 0x0F, 0xC4, 0x2F, 0x85,
+	0x3E, 0x36, 0xF1, 0x2A, 0x69, 0xBE, 0x30, 0xF1, 0x4F, 0xC6, 0x8F, 0x11, 0x5C, 0x45, 0xAF, 0x5B,
+	0xFD, 0xBE, 0xD6, 0x39, 0x2E, 0xB6, 0xC4, 0xAC, 0xDF, 0x32, 0xB6, 0xDF, 0xBA, 0xAD, 0xF3, 0x7F,
+	0xE3, 0xBF, 0xEC, 0xD7, 0xCC, 0xFF, 0x00, 0xB4, 0x6F, 0x8D, 0xFF, 0x00, 0x61, 0x8F, 0x18, 0xAF,
+	0x83, 0xF5, 0x2F, 0x1E, 0x7E, 0xD8, 0x7E, 0x24, 0xBA, 0xD7, 0x2D, 0xFC, 0x2B, 0x6B, 0xFF, 0x00,
+	0x09, 0x1D, 0xBD, 0xBF, 0xC5, 0x4B, 0xA9, 0x23, 0xB3, 0xBE, 0xF2, 0xE3, 0xF3, 0xE1, 0x8E, 0x3D,
+	0xCC, 0xB0, 0xED, 0x6F, 0x97, 0xCB, 0x5D, 0xBB, 0x76, 0xD7, 0x1F, 0xF1, 0xD3, 0xE2, 0x37, 0xC0,
+	0xAF, 0x0B, 0xFC, 0x29, 0xF8, 0x7B, 0xAD, 0xFE, 0xCB, 0xBF, 0xB4, 0x9F, 0x89, 0xBC, 0x51, 0xAA,
+	0xC7, 0xAC, 0xB5, 0xAE, 0xA5, 0xA3, 0xDD, 0x78, 0xFA, 0x4B, 0xC8, 0xAD, 0xED, 0x7C, 0xC9, 0x9B,
+	0x6A, 0xC7, 0x36, 0xE8, 0xE3, 0x6D, 0xAB, 0xF2, 0xFF, 0x00, 0xF6, 0x55, 0xE7, 0x63, 0x38, 0x46,
+	0x9E, 0x53, 0x96, 0xE2, 0x70, 0xD9, 0x36, 0x26, 0xB5, 0x17, 0xCA, 0x9C, 0x7D, 0xE7, 0xC9, 0xCD,
+	0xEE, 0xDD, 0xBD, 0x6C, 0xEE, 0xAE, 0x92, 0xE9, 0xB6, 0x88, 0xF5, 0xA8, 0x66, 0x91, 0xC5, 0xE2,
+	0x29, 0xBC, 0x55, 0x28, 0x4D, 0x5E, 0xCF, 0xDD, 0xB3, 0xB6, 0xB6, 0x57, 0xBB, 0x6B, 0xD6, 0xC6,
+	0x1F, 0xED, 0xA9, 0x27, 0x8C, 0x3C, 0x1F, 0xE2, 0xEF, 0x12, 0x78, 0x56, 0x1F, 0x10, 0xDF, 0x46,
+	0x35, 0x4B, 0x0B, 0xAD, 0x4A, 0xEA, 0xFA, 0x47, 0x64, 0x93, 0x50, 0xB8, 0x92, 0x4F, 0x32, 0x49,
+	0xA4, 0x6D, 0xDF, 0xBC, 0x6F, 0x33, 0xFB, 0xCC, 0xDF, 0x33, 0x6E, 0xFB, 0xCD, 0x5F, 0x22, 0xE8,
+	0x3A, 0xD7, 0x88, 0x74, 0x99, 0x9F, 0x58, 0xD1, 0x3C, 0x5B, 0xAC, 0x5B, 0x5F, 0x32, 0xB3, 0x4B,
+	0x71, 0x6B, 0xAA, 0x49, 0x1C, 0x8D, 0xBB, 0xFB, 0xCD, 0xB9, 0x5B, 0xE6, 0x56, 0xF9, 0xAB, 0xEC,
+	0x2F, 0xF8, 0x29, 0x97, 0x8D, 0x7C, 0x31, 0xA7, 0x5E, 0x78, 0x3F, 0xC6, 0xDA, 0xED, 0xF3, 0x59,
+	0xCD, 0x37, 0x83, 0x6F, 0xA2, 0xBC, 0xB7, 0xD4, 0x15, 0x56, 0x08, 0x63, 0xDB, 0x1E, 0xCD, 0xD2,
+	0xEE, 0xDA, 0xD2, 0x33, 0x6E, 0x5D, 0xBB, 0x7F, 0x87, 0x75, 0x7C, 0x29, 0xA5, 0xFC, 0x5E, 0xF8,
+	0x49, 0x0C, 0xCB, 0x34, 0xDE, 0x36, 0xB1, 0x6D, 0xCB, 0xFF, 0x00, 0x3F, 0x5F, 0x7B, 0x77, 0xF9,
+	0x6F, 0x9A, 0xBE, 0xF3, 0xC3, 0x4A, 0x98, 0xAA, 0xFC, 0x17, 0x85, 0x9E, 0x25, 0xF3, 0xD4, 0x5C,
+	0xDC, 0xD2, 0xD2, 0xEE, 0x4A, 0x72, 0x4E, 0x4D, 0xA6, 0xED, 0x27, 0xBB, 0xD6, 0xE9, 0xB6, 0x7C,
+	0xDF, 0x16, 0x61, 0xE9, 0xE1, 0x38, 0x82, 0xB5, 0x3A, 0x29, 0xC6, 0x3E, 0xEB, 0x4B, 0x5D, 0x2F,
+	0x14, 0xED, 0xAE, 0xE8, 0xE9, 0xEE, 0xA1, 0xD4, 0xAD, 0x35, 0x24, 0xBC, 0xB3, 0xF1, 0x56, 0xB4,
+	0xBA, 0xAB, 0x5E, 0x46, 0xEB, 0x75, 0x1D, 0xFC, 0x8B, 0x26, 0xDF, 0xEF, 0x6E, 0x56, 0xDD, 0xB9,
+	0x59, 0x76, 0xAF, 0xCD, 0xFC, 0x3F, 0xEC, 0xD7, 0x2B, 0xF1, 0x16, 0xCF, 0xC7, 0x3A, 0x5C, 0x50,
+	0xFF, 0x00, 0x66, 0x78, 0xB7, 0x5A, 0x86, 0xEA, 0x48, 0x95, 0xDA, 0x6B, 0x8B, 0xC9, 0xB7, 0x46,
+	0xCA, 0xCD, 0xBB, 0xCB, 0x6D, 0xDF, 0xDD, 0xDB, 0xFF, 0x00, 0x7D, 0x55, 0xEB, 0x7F, 0x8D, 0x5F,
+	0x0A, 0xE1, 0x91, 0x26, 0x4F, 0x1B, 0x58, 0xB3, 0xAA, 0xFD, 0xEF, 0xB4, 0x2F, 0xFC, 0x0A, 0xA4,
+	0xBC, 0xF8, 0xD1, 0xF0, 0xAF, 0x5A, 0xB7, 0x67, 0xD5, 0x7C, 0x55, 0x67, 0x74, 0xEA, 0xAC, 0xB1,
+	0x79, 0xD7, 0x8B, 0xB7, 0xFF, 0x00, 0x42, 0xAF, 0xB4, 0xF6, 0x51, 0x6E, 0xCE, 0x37, 0x5B, 0xBD,
+	0x16, 0xFF, 0x00, 0x71, 0xE0, 0xC6, 0x5C, 0xBB, 0x3F, 0xC4, 0x97, 0xE1, 0x9F, 0xC4, 0xEF, 0x19,
+	0xE9, 0xBF, 0xB4, 0x27, 0xC3, 0xBD, 0x7B, 0xC7, 0xFE, 0x20, 0xD7, 0x35, 0xE8, 0x57, 0x54, 0x92,
+	0xDF, 0x54, 0xFE, 0xD6, 0xD4, 0xA6, 0xBC, 0xFB, 0x44, 0x6D, 0x0C, 0x8B, 0xF7, 0x59, 0xBE, 0x6D,
+	0xBF, 0x2B, 0x7F, 0xC0, 0x6B, 0xEC, 0xBF, 0x8C, 0x1A, 0x66, 0x86, 0x57, 0x4B, 0xD6, 0xFC, 0x1F,
+	0x66, 0xB6, 0xBA, 0x4E, 0xA9, 0x63, 0x1C, 0xE9, 0x6E, 0xB1, 0xB2, 0x3A, 0xC9, 0xB7, 0x6E, 0xD6,
+	0x8D, 0xBF, 0xD5, 0xED, 0xFE, 0xEF, 0xFB, 0x4D, 0x5F, 0x9C, 0xBF, 0x13, 0xBC, 0x59, 0xE0, 0xFD,
+	0x5A, 0xE3, 0x43, 0xB3, 0xD1, 0xF5, 0xB8, 0x6E, 0x9A, 0x3D, 0x72, 0x36, 0x6B, 0x7B, 0x7B, 0xAF,
+	0x9B, 0x6E, 0xEA, 0xFD, 0x0C, 0xFD, 0x9F, 0xBE, 0x12, 0xFC, 0x3E, 0xFF, 0x00, 0x86, 0x69, 0xB0,
+	0xF8, 0xA9, 0x79, 0x0F, 0xFC, 0x4E, 0xB5, 0x0F, 0x10, 0x49, 0x61, 0xFD, 0x87, 0xAB, 0x6B, 0x3B,
+	0x60, 0x8E, 0x35, 0x99, 0x97, 0x72, 0xC8, 0xAD, 0xF3, 0x36, 0xD5, 0xFF, 0x00, 0xD9, 0x6B, 0xF1,
+	0x0F, 0x16, 0x38, 0x56, 0xB6, 0x3B, 0x34, 0xA7, 0x9A, 0x61, 0xEF, 0xCD, 0x1A, 0x4D, 0x4A, 0x3A,
+	0x59, 0xA8, 0xB6, 0xF9, 0xB5, 0x6A, 0xED, 0x27, 0x65, 0x65, 0x73, 0xEE, 0x38, 0x77, 0x30, 0xA4,
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+	0xFF, 0x00, 0x60, 0x68, 0xFF, 0x00, 0xB3, 0xD7, 0xEF, 0x36, 0xE9, 0x3F, 0xD9, 0x65, 0x55, 0xFF,
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+	0x1A, 0xE5, 0xB8, 0x7C, 0xDA, 0xA6, 0x94, 0xAF, 0x52, 0x95, 0x9D, 0xF5, 0xD7, 0x47, 0x24, 0x92,
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+	0x79, 0x8B, 0xE6, 0x97, 0x66, 0x66, 0xFB, 0xB5, 0x25, 0xBD, 0xC3, 0xC3, 0x32, 0x22, 0x23, 0x7C,
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+	0x3D, 0x26, 0xD7, 0x6F, 0xF7, 0x7C, 0xBB, 0x38, 0x57, 0xFF, 0x00, 0x65, 0xAF, 0xE3, 0x6F, 0xF6,
+	0x45, 0xF0, 0xFD, 0xFF, 0x00, 0x8D, 0x3F, 0x68, 0x8F, 0x0A, 0xF8, 0x7B, 0x4C, 0xB6, 0x6B, 0x89,
+	0xAF, 0x35, 0xC8, 0x62, 0x82, 0x35, 0xFE, 0x26, 0x66, 0xDA, 0xBF, 0xF8, 0xF7, 0xFE, 0x85, 0x5F,
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+	0x89, 0x7F, 0xD9, 0x55, 0xDA, 0x2B, 0x35, 0x1F, 0xDF, 0x3F, 0x44, 0x12, 0xB7, 0x2A, 0x2C, 0xD1,
+	0x45, 0x15, 0xB1, 0x98, 0x51, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14, 0x00,
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+	0x7C, 0x14, 0xD3, 0xEF, 0xFC, 0xBB, 0xCF, 0x18, 0x6A, 0x1B, 0xEF, 0x16, 0x37, 0xC3, 0x0B, 0x3B,
+	0x76, 0x56, 0xE7, 0xD9, 0xA6, 0x68, 0x7F, 0xEF, 0x86, 0xAF, 0xC3, 0xCF, 0xDA, 0x73, 0xE2, 0x05,
+	0x9D, 0xBF, 0x8E, 0x2F, 0x2D, 0xBE, 0xD3, 0x1A, 0xB3, 0x2A, 0xEE, 0x65, 0x6F, 0xE2, 0x68, 0xFE,
+	0x6F, 0xFD, 0x0A, 0xBE, 0xD1, 0xFF, 0x00, 0x82, 0xAE, 0x7E, 0xD2, 0x36, 0xBF, 0x1E, 0x7F, 0x6B,
+	0xCD, 0x7E, 0x2D, 0x3F, 0x5D, 0x87, 0xFB, 0x17, 0x45, 0x7F, 0xEC, 0x5D, 0x2E, 0xE3, 0xCD, 0x5F,
+	0x2D, 0xA1, 0xB7, 0xDD, 0xE6, 0x32, 0xB7, 0xDD, 0x6D, 0xD3, 0x79, 0xCC, 0xBF, 0xEF, 0x2D, 0x7E,
+	0x74, 0x7E, 0xD2, 0xD7, 0x9E, 0x1B, 0xB5, 0xD6, 0x61, 0xB3, 0xD1, 0xB5, 0x8F, 0xB6, 0x5C, 0x48,
+	0xDB, 0x6E, 0xA3, 0xF3, 0x7C, 0xCF, 0x2F, 0xFE, 0x04, 0xBF, 0xFA, 0x0D, 0x7F, 0x33, 0x66, 0x15,
+	0x9F, 0x11, 0x71, 0xC5, 0x6C, 0x53, 0x6E, 0x54, 0xD7, 0xB9, 0x0B, 0x6D, 0xCB, 0x1D, 0x2F, 0x7E,
+	0xCD, 0xDE, 0x5E, 0xB2, 0x3F, 0x4C, 0xCB, 0x69, 0xC7, 0x05, 0x92, 0xC6, 0x1D, 0x5E, 0xAF, 0xD5,
+	0xFF, 0x00, 0x92, 0xB2, 0xF9, 0x1C, 0xC6, 0xB5, 0xF1, 0xB2, 0xDA, 0xC4, 0xBC, 0x30, 0xDB, 0x5C,
+	0x5E, 0x49, 0xF6, 0x75, 0x7F, 0x2E, 0xC6, 0x36, 0x93, 0x77, 0xFD, 0xF3, 0xF2, 0xAF, 0xF0, 0xFD,
+	0xEA, 0xE0, 0xBE, 0x31, 0x7C, 0x45, 0xD5, 0xFE, 0x24, 0x78, 0x67, 0xFB, 0x06, 0xD3, 0xC1, 0x9A,
+	0xB4, 0x32, 0x34, 0xEB, 0xBA, 0x6B, 0xAB, 0x5D, 0xBF, 0xBB, 0xFE, 0x25, 0xFF, 0x00, 0xC7, 0x7F,
+	0xF4, 0x2A, 0xB3, 0x1F, 0x80, 0x75, 0xED, 0x72, 0x39, 0xA6, 0xFE, 0xCC, 0x92, 0x37, 0x66, 0xDC,
+	0xAD, 0x22, 0xED, 0x5F, 0xF6, 0xBE, 0xF7, 0xFB, 0xD5, 0x53, 0x52, 0xF8, 0x3B, 0xE2, 0x18, 0xA3,
+	0x57, 0x16, 0x11, 0xFF, 0x00, 0x77, 0xCB, 0xFE, 0x16, 0xAF, 0xB5, 0xC1, 0xD2, 0xC9, 0xF0, 0x75,
+	0xE3, 0x53, 0x4E, 0x78, 0xBE, 0xFD, 0x7F, 0x23, 0x8E, 0xAA, 0xC5, 0xC9, 0x7C, 0x3A, 0x3F, 0x23,
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+	0xD0, 0x75, 0x2D, 0x61, 0xF5, 0x0B, 0xA8, 0xA1, 0x5F, 0x99, 0x61, 0xF2, 0x59, 0xFF, 0x00, 0xEF,
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+	0x89, 0xC5, 0xDC, 0x40, 0xFF, 0x00, 0xD5, 0xF6, 0x95, 0x19, 0x42, 0x57, 0xB2, 0x69, 0xC9, 0x37,
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+	0xF0, 0xCC, 0xBF, 0x63, 0xF1, 0x04, 0x76, 0x6A, 0xAA, 0xB7, 0x90, 0xFF, 0x00, 0xCF, 0x4D, 0xBF,
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+	0xD2, 0x6D, 0x55, 0x6F, 0x95, 0x7E, 0x55, 0xAF, 0x2D, 0xF0, 0xFF, 0x00, 0xC2, 0x5F, 0x05, 0x78,
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+	0x9A, 0x3B, 0xAD, 0xD1, 0xCD, 0xE5, 0xC7, 0xFB, 0xB8, 0xFE, 0x6F, 0xBC, 0xDE, 0x66, 0xD6, 0xDD,
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+	0xB5, 0x55, 0xBF, 0x76, 0xBB, 0x5B, 0xFB, 0xAD, 0xBA, 0xB8, 0xCD, 0x63, 0xF6, 0x90, 0x12, 0x17,
+	0x79, 0xB5, 0x8D, 0x9F, 0xC2, 0xD1, 0xAD, 0xAA, 0xFF, 0x00, 0x7B, 0xEF, 0x2F, 0xF9, 0xFF, 0x00,
+	0xD0, 0x6B, 0xD2, 0x7E, 0x21, 0x7E, 0xDE, 0x1E, 0x00, 0xF1, 0x07, 0x84, 0xF4, 0x9F, 0x0A, 0xF8,
+	0x4A, 0xC2, 0xE2, 0xCD, 0x6C, 0xFE, 0xCF, 0xBA, 0x66, 0xB5, 0x58, 0xDA, 0x1F, 0x2D, 0x7E, 0x65,
+	0xF9, 0x77, 0x6E, 0x66, 0x6D, 0xDF, 0x36, 0xD5, 0xFE, 0x1A, 0xEA, 0xC2, 0xE1, 0xF3, 0x3A, 0x90,
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+	0xD6, 0x23, 0x35, 0xCA, 0xEA, 0xF2, 0x45, 0xDD, 0xDB, 0x4D, 0x7B, 0x6B, 0xE7, 0xD6, 0xF6, 0x39,
+	0x3F, 0x02, 0x7E, 0xC4, 0xDA, 0x0F, 0xC3, 0xEF, 0x0D, 0x5D, 0x78, 0x27, 0xE1, 0xBF, 0xC1, 0x2B,
+	0xED, 0x2F, 0x52, 0xF1, 0x04, 0xB0, 0xDA, 0xEA, 0x5E, 0x24, 0xD6, 0xB5, 0xE8, 0xE7, 0x68, 0xED,
+	0x77, 0x2B, 0x48, 0xAA, 0xAB, 0xF7, 0x77, 0x7F, 0x9D, 0xD5, 0xE8, 0xED, 0xF0, 0x57, 0xE2, 0x0F,
+	0x85, 0xFE, 0x2A, 0x5B, 0x78, 0xE7, 0xC1, 0xFE, 0x09, 0xFE, 0xD2, 0xB1, 0xD2, 0x74, 0xD9, 0xB4,
+	0x95, 0xD3, 0x5A, 0xE3, 0xCA, 0x59, 0xAC, 0x64, 0x87, 0xC9, 0x6D, 0xB2, 0x7F, 0x0B, 0x6D, 0x66,
+	0xDA, 0xD5, 0xE5, 0xBF, 0x11, 0x3F, 0x6A, 0x88, 0xFC, 0x75, 0xE3, 0x2D, 0x43, 0xC4, 0xD0, 0xEA,
+	0xBF, 0x66, 0x82, 0x69, 0x77, 0x45, 0x6A, 0xD0, 0x7C, 0xCA, 0xBB, 0x76, 0xAA, 0xD7, 0xA3, 0xFC,
+	0x23, 0xFD, 0xBB, 0x3E, 0x11, 0x78, 0x37, 0xE1, 0x4C, 0xDE, 0x15, 0xD6, 0x34, 0xEB, 0xA9, 0xB5,
+	0x4B, 0x89, 0x6E, 0x16, 0xEA, 0x66, 0xB7, 0x5D, 0xCC, 0xB2, 0x7D, 0xD9, 0x15, 0xB7, 0x7D, 0xD5,
+	0x5F, 0xE1, 0x6F, 0xEE, 0xD6, 0xB1, 0xA3, 0x9C, 0x63, 0xAB, 0x4F, 0xDB, 0xF3, 0xDB, 0x57, 0xCC,
+	0xEE, 0xDC, 0xB4, 0xE5, 0x49, 0xA6, 0xBA, 0xAE, 0xCF, 0x4B, 0xE8, 0x67, 0x1C, 0xD3, 0x26, 0xA3,
+	0x87, 0x5C, 0xB4, 0xDB, 0x6E, 0xCA, 0xDD, 0xBA, 0xBB, 0x34, 0xFA, 0x3E, 0xBD, 0x46, 0xFE, 0xCF,
+	0x3F, 0xB0, 0xFF, 0x00, 0x86, 0x3E, 0x01, 0xFC, 0x50, 0xB6, 0xF8, 0xD3, 0xF0, 0x8B, 0xF6, 0x72,
+	0xBC, 0xB7, 0xD7, 0xAD, 0x59, 0xA5, 0xD1, 0xF5, 0x6F, 0x15, 0x6B, 0xCB, 0x75, 0x06, 0x93, 0x33,
+	0x6E, 0x5F, 0x32, 0x28, 0x23, 0xF9, 0x64, 0x91, 0x57, 0xEE, 0xB3, 0x7D, 0xDF, 0xBD, 0x5F, 0x42,
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+	0xC3, 0xAB, 0xDC, 0x5E, 0x4C, 0xAA, 0xDE, 0x75, 0xD2, 0xCD, 0xE7, 0x6E, 0x7F, 0x9B, 0xEE, 0xEE,
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+	0x72, 0xFF, 0x00, 0xF6, 0x35, 0x1F, 0xFC, 0x22, 0x3F, 0x0F, 0x66, 0xFB, 0x74, 0x29, 0x6D, 0x6A,
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+	0xD3, 0xE1, 0xFB, 0x6F, 0xD8, 0x4F, 0xC7, 0x9A, 0x1E, 0x8B, 0xE2, 0x58, 0x6F, 0x37, 0x78, 0x89,
+	0xB5, 0x0B, 0x08, 0xEE, 0x66, 0x65, 0xDB, 0xF3, 0x6D, 0x0D, 0x1C, 0x8A, 0xAD, 0xE6, 0x7C, 0xDB,
+	0x99, 0x7E, 0x65, 0xFB, 0xAC, 0xB5, 0xEE, 0x9A, 0xE7, 0xC3, 0xFF, 0x00, 0x01, 0xE9, 0xF1, 0xE9,
+	0xF6, 0x6F, 0x6D, 0x6A, 0xE9, 0x25, 0xC2, 0xA4, 0xAB, 0xB9, 0x7E, 0xEF, 0xFD, 0xF3, 0x47, 0x88,
+	0x3C, 0x1B, 0xF0, 0x4F, 0x47, 0xD6, 0x2D, 0x74, 0xD4, 0xD1, 0xEC, 0xF6, 0xDC, 0x2C, 0x8C, 0xD2,
+	0x2E, 0xDD, 0xBF, 0x2A, 0xFF, 0x00, 0xBB, 0xFE, 0xF5, 0x7A, 0xF1, 0xE0, 0xEC, 0xD2, 0x9E, 0x3A,
+	0xAE, 0x36, 0xB4, 0xE8, 0xDD, 0x35, 0xEE, 0xB5, 0x75, 0x79, 0x6B, 0xF0, 0xB5, 0x66, 0xB5, 0xB7,
+	0x91, 0x34, 0xF3, 0xBC, 0x1A, 0xA3, 0x4E, 0x85, 0x28, 0xC9, 0xA5, 0x77, 0x77, 0xD6, 0xC9, 0xAF,
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+	0xA7, 0xE6, 0xD1, 0xAE, 0xFE, 0x27, 0x47, 0x3E, 0xDB, 0xA9, 0xB4, 0x38, 0x36, 0x2B, 0x2F, 0x98,
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+	0x7B, 0x95, 0x7E, 0x6D, 0xBF, 0xEE, 0xD7, 0x5B, 0x37, 0x87, 0xBE, 0x14, 0x6A, 0x5A, 0x3E, 0xB9,
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+	0xD3, 0xE5, 0x6F, 0x6F, 0x99, 0x77, 0x2F, 0xF1, 0x7F, 0x77, 0xFF, 0x00, 0x65, 0xAF, 0x36, 0x5C,
+	0x3F, 0x8E, 0xCD, 0xB1, 0xDF, 0x5B, 0x84, 0xE9, 0x5A, 0x11, 0x72, 0x69, 0x59, 0x2E, 0x54, 0xDA,
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+	0xB0, 0xDC, 0x5F, 0x82, 0x95, 0xF7, 0x9A, 0x8B, 0xFF, 0x00, 0xB7, 0xBD, 0xDF, 0xD4, 0xF3, 0x73,
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+	0x3F, 0x2D, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x39, 0x3F, 0x8C, 0xDE, 0x00, 0xB5, 0xF8, 0xA5, 0xF0, 0xAB, 0xC4, 0x1F, 0x0F, 0xEE,
+	0x61, 0x56, 0xFE, 0xD6, 0xD2, 0xE6, 0x86, 0x25, 0x7E, 0x9E, 0x66, 0xDF, 0x90, 0xFF, 0x00, 0xDF,
+	0x5B, 0x6B, 0xF2, 0x13, 0xE2, 0x17, 0xFC, 0x13, 0x57, 0xF6, 0xEB, 0xD4, 0xBC, 0xEF, 0x27, 0xF6,
+	0x6B, 0xD4, 0x99, 0x63, 0xDD, 0xF3, 0x5B, 0xEB, 0x56, 0x32, 0x2B, 0x7F, 0x77, 0x6F, 0xFA, 0x46,
+	0xEF, 0xFC, 0x76, 0xBF, 0x69, 0xE8, 0xAF, 0x8B, 0xE2, 0x8E, 0x06, 0xCA, 0x78, 0xAE, 0xBD, 0x3A,
+	0xD8, 0xA9, 0x4A, 0x32, 0x82, 0x69, 0x38, 0xB4, 0xAE, 0x9B, 0xBE, 0xB7, 0x8B, 0xD9, 0xDE, 0xD6,
+	0xB6, 0xEC, 0xF5, 0x32, 0xFC, 0xD7, 0x11, 0x96, 0xA6, 0xA9, 0xA4, 0xEF, 0xDF, 0xFE, 0x1C, 0xFE,
+	0x7D, 0xFC, 0x49, 0xFF, 0x00, 0x04, 0xB4, 0xFF, 0x00, 0x82, 0x83, 0x48, 0xD2, 0x1B, 0x6F, 0xD9,
+	0x67, 0xC4, 0xCE, 0xA3, 0xEE, 0xAA, 0xBD, 0xBB, 0x6E, 0xFF, 0x00, 0xC8, 0xD5, 0xC2, 0xF8, 0x93,
+	0xFE, 0x09, 0x83, 0xFF, 0x00, 0x05, 0x18, 0xD3, 0x20, 0x5B, 0x89, 0xBF, 0x64, 0x1F, 0x1B, 0xC8,
+	0x37, 0x6C, 0xC5, 0xAD, 0x9A, 0xCE, 0xCD, 0xFF, 0x00, 0x01, 0x8D, 0x9B, 0x6F, 0x4F, 0xF7, 0x6B,
+	0xFA, 0x42, 0xA2, 0xBC, 0x7A, 0x1E, 0x17, 0xE5, 0x18, 0x75, 0x68, 0xD6, 0x9B, 0xF5, 0xE5, 0xFF,
+	0x00, 0x24, 0x77, 0x4B, 0x89, 0x31, 0x52, 0xDE, 0x11, 0xFC, 0x7F, 0xCC, 0xFE, 0x66, 0x24, 0xFF,
+	0x00, 0x82, 0x6C, 0x7F, 0xC1, 0x44, 0xD9, 0xBE, 0x4F, 0xD8, 0xDF, 0xE2, 0x50, 0x55, 0xDC, 0xAB,
+	0xB7, 0xC3, 0x93, 0x2F, 0xFC, 0x0A, 0xB0, 0x75, 0xBF, 0xF8, 0x27, 0x2F, 0xFC, 0x14, 0x7F, 0x4D,
+	0x8D, 0x2D, 0x9F, 0xF6, 0x2F, 0xF8, 0xA1, 0xB9, 0xBE, 0xEF, 0xD9, 0xFC, 0x27, 0x79, 0x3A, 0xFF,
+	0x00, 0xDF, 0x51, 0xC6, 0xDB, 0x7E, 0x6F, 0xEF, 0x57, 0xF5, 0x0B, 0x45, 0x7A, 0x94, 0x78, 0x17,
+	0x2F, 0xA3, 0xB5, 0x49, 0x3F, 0x54, 0x8C, 0x65, 0x9E, 0x57, 0x96, 0xF1, 0x5F, 0x89, 0xFC, 0xB8,
+	0xC5, 0xFF, 0x00, 0x04, 0xF4, 0xFF, 0x00, 0x82, 0x8C, 0xA2, 0xED, 0x97, 0xF6, 0x2E, 0xF8, 0xB0,
+	0x15, 0x55, 0xBE, 0xEF, 0x82, 0x75, 0x2F, 0xF8, 0x0F, 0xFC, 0xB1, 0xAA, 0xB7, 0xDF, 0xB0, 0xA7,
+	0xFC, 0x14, 0x2E, 0x28, 0xFC, 0xAB, 0x8F, 0xD8, 0xC3, 0xE2, 0xF2, 0xBF, 0x46, 0xDB, 0xF0, 0xFB,
+	0x52, 0x6D, 0xAB, 0xFF, 0x00, 0x80, 0xF5, 0xFD, 0x4C, 0x51, 0x5A, 0xC7, 0x82, 0xF0, 0x4A, 0x57,
+	0xE7, 0x7F, 0x72, 0x25, 0xE7, 0x55, 0xBF, 0x95, 0x1F, 0xCA, 0x94, 0x9F, 0xB0, 0x8F, 0xED, 0xF9,
+	0x37, 0xC8, 0xFF, 0x00, 0xB1, 0x3F, 0xC6, 0x0D, 0xED, 0xFC, 0x4D, 0xF0, 0xDF, 0x54, 0xFF, 0x00,
+	0xE4, 0x7A, 0xCD, 0x5F, 0xD9, 0x07, 0xF6, 0xD2, 0x66, 0x59, 0x1F, 0xF6, 0x51, 0xF8, 0x9D, 0x1B,
+	0x7F, 0x7B, 0xFE, 0x10, 0x3D, 0x49, 0xBF, 0xF6, 0x8D, 0x7F, 0x57, 0xF4, 0x56, 0xFF, 0x00, 0xEA,
+	0x96, 0x17, 0xF9, 0xDF, 0xDC, 0x88, 0xFE, 0xD7, 0xA9, 0xFC, 0xA8, 0xFE, 0x4E, 0xEF, 0x3F, 0x64,
+	0xDF, 0xDB, 0x12, 0xC6, 0xDD, 0x6F, 0xF5, 0x0F, 0xD9, 0x6B, 0xE2, 0x74, 0x68, 0xBF, 0x7A, 0x49,
+	0xBC, 0x0B, 0xA8, 0x2A, 0xAF, 0xCD, 0xB7, 0xEF, 0x34, 0x3F, 0xED, 0x2D, 0x64, 0xCD, 0xFB, 0x34,
+	0xFE, 0xD4, 0x5F, 0x22, 0x7F, 0xC3, 0x3C, 0x7C, 0x42, 0xDD, 0xF3, 0x6E, 0xDB, 0xE0, 0xDB, 0xEF,
+	0xFE, 0x33, 0x5F, 0xD6, 0xD5, 0x15, 0x4B, 0x85, 0x70, 0xEB, 0xFE, 0x5E, 0x3F, 0xBB, 0xFE, 0x08,
+	0xBF, 0xB5, 0x6A, 0x7F, 0x2A, 0xFB, 0xCF, 0xE4, 0xA5, 0x7E, 0x01, 0x7E, 0xD2, 0x1A, 0x0C, 0x49,
+	0xFD, 0xB1, 0xF0, 0x27, 0xC7, 0x16, 0xDE, 0x66, 0xEF, 0xF8, 0xF8, 0xF0, 0xA5, 0xE2, 0xEE, 0xFF,
+	0x00, 0xBE, 0xA3, 0xA9, 0x63, 0xF8, 0x47, 0xF1, 0xED, 0x57, 0x7F, 0xFC, 0x29, 0xFF, 0x00, 0x18,
+	0x33, 0x7C, 0xDF, 0x37, 0xFC, 0x23, 0xB7, 0x4A, 0xDF, 0xFA, 0x2E, 0xBF, 0xAD, 0x1A, 0x2B, 0x19,
+	0xF0, 0x8E, 0x1E, 0x6E, 0xFE, 0xD1, 0xFD, 0xDF, 0xF0, 0x4A, 0x8E, 0x6D, 0x28, 0xAB, 0x72, 0x7E,
+	0x27, 0xF2, 0x53, 0x37, 0xC3, 0xDF, 0x8C, 0x9A, 0x6C, 0x89, 0x0D, 0xFF, 0x00, 0xC3, 0x7F, 0x13,
+	0x5B, 0xCD, 0xB5, 0xBE, 0x59, 0xB4, 0x6B, 0x85, 0x6F, 0xBD, 0xF7, 0xB6, 0xED, 0xA4, 0x8F, 0xC2,
+	0x3F, 0x16, 0xA3, 0x55, 0x0F, 0xE0, 0x6F, 0x10, 0x33, 0xB2, 0xFC, 0xBF, 0xF1, 0x26, 0x99, 0xBE,
+	0x5F, 0xFB, 0xE6, 0xBF, 0xAD, 0x72, 0x03, 0x75, 0xA4, 0xC1, 0xF4, 0xFD, 0x6B, 0x1F, 0xF5, 0x2E,
+	0x87, 0x35, 0xFD, 0xAB, 0xFF, 0x00, 0xC0, 0x57, 0xF9, 0x87, 0xF6, 0xC4, 0xFF, 0x00, 0x97, 0xF1,
+	0xFF, 0x00, 0x80, 0x7F, 0x24, 0x4D, 0x6B, 0xE3, 0x68, 0x65, 0x64, 0x9B, 0x41, 0xD5, 0x92, 0x4D,
+	0xDB, 0x59, 0x7E, 0xC1, 0x22, 0xFC, 0xDF, 0xED, 0x2E, 0xDA, 0x99, 0x57, 0xC6, 0x71, 0xED, 0x79,
+	0xB4, 0x4D, 0x53, 0x6E, 0xDD, 0xBB, 0x9A, 0xCE, 0x4F, 0xFE, 0x26, 0xBF, 0xAD, 0x46, 0xB5, 0x85,
+	0xBA, 0xAD, 0x1F, 0x64, 0xB7, 0xFF, 0x00, 0x9E, 0x42, 0xB3, 0x7C, 0x15, 0x4D, 0xFF, 0x00, 0xCB,
+	0xEF, 0xFC, 0x95, 0x7F, 0x99, 0x7F, 0xDB, 0x52, 0xB5, 0xB9, 0x3F, 0x1F, 0xF8, 0x07, 0xF2, 0x43,
+	0x16, 0xBD, 0x7F, 0xF2, 0xEC, 0x9E, 0x45, 0xDB, 0xFE, 0xF7, 0xDD, 0xFF, 0x00, 0xD9, 0x7F, 0xCF,
+	0xFB, 0xD5, 0x62, 0x4F, 0x17, 0x5C, 0xD9, 0xC6, 0xBF, 0x6F, 0xBF, 0x68, 0x53, 0x72, 0xAB, 0x49,
+	0x37, 0xCB, 0xF3, 0x7F, 0xBC, 0xD5, 0xFD, 0x69, 0x7F, 0x66, 0x58, 0xFF, 0x00, 0xCF, 0xBA, 0xD2,
+	0x36, 0x95, 0xA6, 0xBA, 0xED, 0x6B, 0x38, 0xCA, 0xD6, 0x6F, 0x81, 0xE2, 0xE3, 0x6F, 0x6D, 0xFF,
+	0x00, 0x92, 0x2F, 0xFE, 0x48, 0xD1, 0x67, 0x8D, 0x7D, 0x8F, 0xC7, 0xFE, 0x01, 0xFC, 0x98, 0x47,
+	0xF1, 0x1F, 0x4D, 0x69, 0x15, 0xFF, 0x00, 0xE1, 0x21, 0xB7, 0xDD, 0xFC, 0x2A, 0xB7, 0x0B, 0xF7,
+	0x7F, 0xEF, 0xAA, 0xB9, 0x6F, 0xF1, 0x1A, 0xCC, 0x4E, 0xD3, 0x49, 0xE2, 0x18, 0x5D, 0x55, 0xBE,
+	0xF7, 0xDA, 0x17, 0xFF, 0x00, 0x8A, 0xAF, 0xEB, 0x0B, 0xFB, 0x17, 0x4B, 0xFF, 0x00, 0x9F, 0x18,
+	0xFF, 0x00, 0xEF, 0x9A, 0xA1, 0xA9, 0xF8, 0x1F, 0xC1, 0x9A, 0xE3, 0xA3, 0xEB, 0x9E, 0x14, 0xD3,
+	0x6F, 0x0C, 0x65, 0x84, 0x4D, 0x75, 0x65, 0x1C, 0xBB, 0x37, 0x7D, 0xE0, 0x37, 0x2F, 0x1D, 0x2B,
+	0x9E, 0xA7, 0x87, 0xF4, 0xEA, 0x7F, 0xCB, 0xFF, 0x00, 0xFC, 0x97, 0xFF, 0x00, 0xB6, 0x2E, 0x39,
+	0xFF, 0x00, 0x2F, 0xD8, 0x7F, 0xF8, 0x17, 0xFC, 0x03, 0xF9, 0x58, 0x8F, 0xE2, 0x6F, 0x96, 0xBB,
+	0x1F, 0xC4, 0x31, 0xEE, 0xFB, 0xAB, 0xB6, 0x55, 0xFB, 0xDF, 0xF7, 0xD5, 0x58, 0x87, 0xE2, 0x74,
+	0xD2, 0x46, 0xCE, 0x35, 0xB5, 0x6D, 0xAD, 0xB7, 0xFD, 0x6A, 0xEE, 0xFB, 0xDF, 0xED, 0x57, 0xF5,
+	0x33, 0xFF, 0x00, 0x0A, 0xAF, 0xE1, 0x8F, 0xFD, 0x13, 0x8D, 0x07, 0xFF, 0x00, 0x05, 0x30, 0xFF,
+	0x00, 0xF1, 0x35, 0x99, 0xA9, 0x7C, 0x00, 0xF8, 0x17, 0xAC, 0x5D, 0x7D, 0xB7, 0x57, 0xF8, 0x2F,
+	0xE1, 0x4B, 0x99, 0xB6, 0xED, 0xF3, 0xAE, 0x3C, 0x39, 0x6B, 0x23, 0x6D, 0xF4, 0xCB, 0x25, 0x71,
+	0xCB, 0xC3, 0x5A, 0x4F, 0xFE, 0x5F, 0x2F, 0xFC, 0x03, 0xFF, 0x00, 0xB6, 0x37, 0x5C, 0x49, 0xFD,
+	0xC7, 0xFF, 0x00, 0x81, 0x7F, 0xC0, 0x3F, 0x97, 0x9F, 0xF8, 0x58, 0x53, 0x36, 0xC9, 0x1F, 0x55,
+	0x5D, 0xCB, 0xF2, 0xAA, 0xF9, 0xBF, 0xDE, 0xA7, 0x37, 0x8D, 0x2E, 0xE4, 0x2B, 0xBE, 0xFD, 0x95,
+	0xBF, 0xD9, 0x6D, 0xDF, 0x2F, 0xFB, 0x35, 0xFD, 0x3F, 0x7F, 0xC3, 0x34, 0xFE, 0xCE, 0xDF, 0xF4,
+	0x41, 0x3C, 0x17, 0xFF, 0x00, 0x84, 0xB5, 0xA7, 0xFF, 0x00, 0x1B, 0xAC, 0x99, 0x3F, 0x63, 0x0F,
+	0xD8, 0xFA, 0x59, 0x1A, 0x59, 0xBF, 0x65, 0x1F, 0x86, 0xCC, 0xD2, 0x36, 0xE6, 0x66, 0xF0, 0x2E,
+	0x9F, 0x96, 0x6F, 0xFB, 0xF3, 0x53, 0xFF, 0x00, 0x10, 0xDE, 0x5A, 0x5A, 0xBA, 0xFF, 0x00, 0xC0,
+	0x7F, 0xE0, 0x8B, 0xFD, 0x62, 0x84, 0xB7, 0x83, 0xFB, 0xFF, 0x00, 0xE0, 0x1F, 0xCC, 0xBF, 0xFC,
+	0x26, 0xD7, 0x8B, 0xB7, 0x7D, 0xE3, 0x33, 0xFD, 0xD5, 0x55, 0xFF, 0x00, 0x3F, 0xED, 0x51, 0x2F,
+	0x8C, 0x35, 0x26, 0xF9, 0xDE, 0x69, 0x3F, 0x85, 0x55, 0x5B, 0x76, 0xD6, 0xAF, 0xE9, 0x8E, 0xE3,
+	0xF6, 0x27, 0xFD, 0x8D, 0x2F, 0x20, 0x92, 0xD6, 0xEF, 0xF6, 0x48, 0xF8, 0x67, 0x24, 0x72, 0x2E,
+	0xD9, 0x23, 0x93, 0xC0, 0x3A, 0x73, 0x2B, 0x0F, 0x71, 0xE4, 0xD6, 0x62, 0xFF, 0x00, 0xC1, 0x3B,
+	0xBF, 0x60, 0x15, 0xFB, 0xBF, 0xB0, 0xBF, 0xC1, 0xE5, 0xFF, 0x00, 0xBA, 0x63, 0xA5, 0x7F, 0xF2,
+	0x3D, 0x0B, 0xC3, 0xAA, 0x9F, 0xF3, 0xF6, 0x3F, 0xF8, 0x0B, 0x1A, 0xE2, 0x0A, 0x5D, 0x60, 0xFE,
+	0xF3, 0xF9, 0xAD, 0x9B, 0xC4, 0xF7, 0x9E, 0x67, 0x9D, 0x33, 0xC8, 0xCB, 0xBB, 0x6F, 0xDD, 0xF9,
+	0x7F, 0xDE, 0xF9, 0x69, 0xBF, 0xF0, 0x98, 0x5E, 0x79, 0x6C, 0xF3, 0x4C, 0xDB, 0x97, 0xFD, 0xEF,
+	0x9A, 0xBF, 0xA5, 0x19, 0xBF, 0xE0, 0x9D, 0x7F, 0xF0, 0x4F, 0xF9, 0x53, 0x63, 0x7E, 0xC3, 0x7F,
+	0x08, 0x47, 0xFB, 0x9F, 0x0D, 0x74, 0xB5, 0x3F, 0xA4, 0x14, 0xCF, 0xF8, 0x77, 0x07, 0xFC, 0x13,
+	0xF7, 0xFE, 0x8C, 0x8B, 0xE1, 0x4F, 0xFE, 0x1B, 0xFD, 0x3F, 0xFF, 0x00, 0x8C, 0xD5, 0x7F, 0xC4,
+	0x3B, 0xA9, 0xFF, 0x00, 0x3F, 0x63, 0xF7, 0x31, 0x7F, 0xAC, 0x14, 0xFF, 0x00, 0x91, 0x9F, 0xCD,
+	0x8C, 0x9E, 0x2A, 0xB9, 0x68, 0x56, 0x19, 0x66, 0x93, 0xE5, 0x97, 0x72, 0xB6, 0xDF, 0x95, 0x69,
+	0x61, 0xF1, 0x65, 0xC9, 0x56, 0xDF, 0x34, 0x8A, 0xBB, 0x7E, 0x5F, 0xF6, 0x7F, 0xF6, 0x6A, 0xFE,
+	0x90, 0xB5, 0x1F, 0xF8, 0x26, 0x57, 0xFC, 0x13, 0xCF, 0x54, 0x71, 0x35, 0xCF, 0xEC, 0x59, 0xF0,
+	0xCD, 0x19, 0x57, 0x03, 0xEC, 0xFE, 0x0F, 0xB5, 0x84, 0x7E, 0x51, 0xC6, 0xB5, 0x5F, 0xFE, 0x1D,
+	0x69, 0xFF, 0x00, 0x04, 0xE6, 0xFF, 0x00, 0xA3, 0x2E, 0xF8, 0x77, 0xF7, 0x71, 0xFF, 0x00, 0x22,
+	0xDC, 0x3F, 0xFC, 0x4D, 0x4F, 0xFC, 0x43, 0xBA, 0xDF, 0xF3, 0xF2, 0x1F, 0x73, 0x1F, 0xF6, 0xFD,
+	0x1F, 0xE5, 0x7F, 0x87, 0xF9, 0x9F, 0xCE, 0x24, 0x9E, 0x34, 0xB9, 0x03, 0x7A, 0x5C, 0x36, 0xD5,
+	0xDB, 0xFE, 0x7F, 0xCF, 0xFE, 0x3B, 0x53, 0x49, 0xE3, 0x6B, 0xF6, 0xB5, 0x64, 0x17, 0x3B, 0xBE,
+	0x7D, 0xD1, 0x2E, 0xDF, 0x97, 0xFC, 0xEE, 0xAF, 0xE8, 0x8E, 0xF7, 0xFE, 0x09, 0x1F, 0xFF, 0x00,
+	0x04, 0xD8, 0xBD, 0x95, 0xA6, 0xB8, 0xFD, 0x8D, 0xBC, 0x16, 0xBB, 0xBF, 0xE5, 0x9C, 0x36, 0x2D,
+	0x1A, 0x7F, 0xDF, 0x2A, 0xC1, 0x45, 0x33, 0xFE, 0x1D, 0x07, 0xFF, 0x00, 0x04, 0xD1, 0xD9, 0xB3,
+	0xFE, 0x18, 0xEF, 0xC2, 0x7B, 0x7F, 0xEB, 0x8C, 0xDF, 0xFC, 0x72, 0xA3, 0xFE, 0x21, 0xDD, 0x6E,
+	0xB5, 0x21, 0xF7, 0x3F, 0xF2, 0x0F, 0xF5, 0x82, 0x9F, 0xF2, 0xBF, 0xC3, 0xFC, 0xCF, 0xE7, 0x77,
+	0xFE, 0x13, 0x8B, 0xF6, 0x6D, 0xF3, 0x5E, 0x6E, 0x55, 0x7F, 0xEE, 0xEE, 0xDD, 0x53, 0x7F, 0xC2,
+	0x61, 0x79, 0x22, 0x94, 0x9A, 0xE7, 0x72, 0xAF, 0xCF, 0xB5, 0xBF, 0xBD, 0xFE, 0xCD, 0x7F, 0x41,
+	0x87, 0xFE, 0x08, 0xB9, 0xFF, 0x00, 0x04, 0xC2, 0x62, 0x58, 0xFE, 0xC9, 0x9A, 0x3F, 0xCD, 0xD7,
+	0xFE, 0x26, 0xD7, 0xFF, 0x00, 0xFC, 0x91, 0x44, 0xBF, 0xF0, 0x45, 0xFF, 0x00, 0xF8, 0x26, 0x39,
+	0x8B, 0xC8, 0x1F, 0xB2, 0x86, 0x9A, 0xAB, 0xFF, 0x00, 0x4C, 0xF5, 0x8D, 0x45, 0x4F, 0xE6, 0xB7,
+	0x14, 0xBF, 0xE2, 0x1D, 0xE2, 0x3A, 0x4E, 0x1F, 0x73, 0xFF, 0x00, 0x20, 0x59, 0xF5, 0x15, 0x2B,
+	0xDA, 0x5F, 0x87, 0xF9, 0x9F, 0xCF, 0xB5, 0xCF, 0x8C, 0x26, 0x93, 0xE7, 0x7B, 0x95, 0x66, 0x8F,
+	0xE6, 0xF9, 0xBF, 0xEF, 0x95, 0xFF, 0x00, 0x6A, 0xAC, 0xAF, 0x8E, 0x2E, 0x7C, 0xB5, 0x47, 0xB9,
+	0x66, 0x55, 0xF9, 0xB7, 0x35, 0x7E, 0xFD, 0xFF, 0x00, 0xC3, 0x94, 0xFF, 0x00, 0xE0, 0x98, 0xFD,
+	0x7F, 0xE1, 0x95, 0x6C, 0x7E, 0x9F, 0xF0, 0x90, 0xEA, 0x9F, 0xFC, 0x95, 0x51, 0x5D, 0xFF, 0x00,
+	0xC1, 0x14, 0x3F, 0xE0, 0x99, 0x57, 0x51, 0xAC, 0x7F, 0xF0, 0xCC, 0x56, 0xF1, 0xED, 0x6D, 0xDB,
+	0xA1, 0xF1, 0x36, 0xA8, 0xA7, 0xFF, 0x00, 0x4A, 0xBA, 0x56, 0x12, 0xF0, 0xEB, 0x1B, 0x28, 0xDB,
+	0xDA, 0x43, 0xF1, 0xFF, 0x00, 0x22, 0xFF, 0x00, 0xD6, 0x0A, 0x3F, 0xCA, 0xFF, 0x00, 0x0F, 0xF3,
+	0x3F, 0x03, 0x65, 0xF1, 0xA4, 0xD2, 0x6E, 0xFD, 0xF3, 0x32, 0xB7, 0xF1, 0x33, 0x7F, 0x9D, 0xB4,
+	0x9F, 0xF0, 0x98, 0x5E, 0x6D, 0x67, 0x6B, 0x99, 0x15, 0x77, 0x6E, 0xDB, 0xBB, 0x6A, 0xFF, 0x00,
+	0x9F, 0x9A, 0xBF, 0x7B, 0x4F, 0xFC, 0x11, 0x07, 0xFE, 0x09, 0x93, 0xF2, 0xEC, 0xFD, 0x9B, 0xD5,
+	0x76, 0xFF, 0x00, 0x77, 0xC5, 0x1A, 0xA7, 0xFF, 0x00, 0x25, 0x55, 0x5B, 0xCF, 0xF8, 0x21, 0xA7,
+	0xFC, 0x13, 0x2A, 0xF6, 0x75, 0x9B, 0xFE, 0x19, 0xF2, 0xE2, 0x2D, 0xAB, 0x8D, 0xB0, 0xF8, 0xBB,
+	0x56, 0x51, 0xFF, 0x00, 0xA5, 0x55, 0x2B, 0xC3, 0xBC, 0xD1, 0x6D, 0x38, 0x5B, 0xD6, 0x5F, 0xFC,
+	0x89, 0x7F, 0xEB, 0x06, 0x17, 0x76, 0xA5, 0xF8, 0x7F, 0x99, 0xF8, 0x3F, 0x1F, 0x8E, 0xAF, 0xFE,
+	0x54, 0x4B, 0xC9, 0x19, 0x3E, 0xF2, 0xFE, 0xF5, 0x97, 0xFC, 0xFF, 0x00, 0xBD, 0x52, 0x43, 0xE3,
+	0xED, 0x57, 0x1E, 0x72, 0x6A, 0x57, 0x0A, 0xBB, 0x7E, 0x5D, 0xD2, 0xB2, 0xD7, 0xEE, 0xBF, 0xFC,
+	0x38, 0x9F, 0xFE, 0x09, 0x97, 0xB7, 0x67, 0xFC, 0x28, 0x4B, 0xDF, 0xFC, 0x2C, 0xB5, 0x6F, 0xFE,
+	0x4A, 0xAA, 0x53, 0xFF, 0x00, 0xC1, 0x03, 0xFF, 0x00, 0xE0, 0x99, 0x52, 0xDC, 0x34, 0xCB, 0xF0,
+	0x5F, 0x58, 0x8F, 0x73, 0x6E, 0xDB, 0x1F, 0x8E, 0x75, 0x65, 0x03, 0xFF, 0x00, 0x26, 0xAA, 0xFF,
+	0x00, 0xE2, 0x1F, 0xE6, 0xD1, 0x7A, 0x4E, 0x1F, 0x7C, 0xBF, 0xF9, 0x11, 0xAE, 0x20, 0xC2, 0xDE,
+	0xFE, 0xF7, 0xDD, 0xFF, 0x00, 0x04, 0xFC, 0x3F, 0x87, 0xE2, 0x46, 0xAA, 0xBF, 0x7F, 0x52, 0x91,
+	0x97, 0x6F, 0xCC, 0xCD, 0x2B, 0x55, 0xD8, 0x7E, 0x22, 0xDE, 0x6E, 0x59, 0x9F, 0x52, 0x91, 0x7E,
+	0x56, 0x46, 0xFD, 0xEF, 0xDE, 0xFE, 0x2F, 0xEF, 0x7C, 0xB5, 0xFB, 0x62, 0xBF, 0xF0, 0x40, 0xAF,
+	0xF8, 0x26, 0x54, 0x7F, 0x77, 0xE0, 0xD6, 0xB5, 0xFF, 0x00, 0x85, 0xD6, 0xAD, 0xFF, 0x00, 0xC9,
+	0x55, 0x47, 0xFE, 0x21, 0xF5, 0xFF, 0x00, 0x82, 0x71, 0x6D, 0x54, 0x1E, 0x13, 0xF1, 0x72, 0xAA,
+	0xFF, 0x00, 0x0A, 0xF8, 0xD2, 0xEB, 0xFF, 0x00, 0x8A, 0xAE, 0x7A, 0x9E, 0x1E, 0x67, 0x32, 0xF8,
+	0x6A, 0x47, 0xFF, 0x00, 0x02, 0x97, 0xF9, 0x1A, 0x47, 0x88, 0xB0, 0x5D, 0xA5, 0xF7, 0x2F, 0xF3,
+	0x3F, 0x19, 0x61, 0xF8, 0x91, 0xA9, 0x47, 0x27, 0xFC, 0x84, 0xA4, 0xDA, 0xAB, 0xB7, 0xFD, 0x6B,
+	0x7F, 0xBB, 0xFD, 0xEA, 0x92, 0x3F, 0x8A, 0x1A, 0xAC, 0x6D, 0xBE, 0x3D, 0x62, 0xE1, 0x9B, 0xE6,
+	0x5F, 0x9A, 0x56, 0xF9, 0x7F, 0xCE, 0xEA, 0xFD, 0x94, 0xBA, 0xFF, 0x00, 0x83, 0x7D, 0x3F, 0xE0,
+	0x9D, 0xB3, 0xDB, 0x34, 0x50, 0xE8, 0x3E, 0x33, 0xB7, 0x91, 0xBE, 0xEC, 0xD1, 0xF8, 0xD2, 0xE4,
+	0xB2, 0xFF, 0x00, 0xDF, 0x7B, 0x97, 0xFF, 0x00, 0x1D, 0xAA, 0x23, 0xFE, 0x0D, 0xDE, 0xFF, 0x00,
+	0x82, 0x7E, 0xAB, 0x6F, 0x5B, 0xEF, 0x88, 0x4B, 0xF3, 0x67, 0xFE, 0x46, 0xC5, 0xFF, 0x00, 0xE3,
+	0x35, 0xC1, 0x53, 0xC3, 0x3C, 0xE6, 0xA3, 0xD6, 0x70, 0x7F, 0xF6, 0xF3, 0xFF, 0x00, 0x23, 0x4F,
+	0xF5, 0x8F, 0x03, 0xFD, 0xEF, 0xBB, 0xFE, 0x09, 0xF8, 0xF2, 0xBF, 0x14, 0x35, 0x89, 0x24, 0x5F,
+	0xF8, 0x9C, 0x5C, 0x2E, 0xEF, 0xFA, 0x78, 0x65, 0xFF, 0x00, 0xC7, 0x69, 0xCB, 0xF1, 0x53, 0x5B,
+	0xDD, 0xB1, 0x35, 0xBB, 0x8D, 0xAB, 0xF7, 0x95, 0x6E, 0x1A, 0xBF, 0x5E, 0x2F, 0x7F, 0xE0, 0xDD,
+	0x0F, 0xD8, 0x1A, 0xE6, 0x25, 0x86, 0xC7, 0xC4, 0xBF, 0x12, 0xAC, 0x76, 0xFD, 0xE6, 0xB5, 0xF1,
+	0x44, 0x2D, 0xBB, 0xFE, 0xFE, 0x5A, 0xB7, 0xE9, 0x55, 0xA3, 0xFF, 0x00, 0x83, 0x6F, 0xBF, 0x61,
+	0x68, 0xBE, 0xE7, 0xC4, 0x6F, 0x8A, 0x9F, 0xF8, 0x51, 0xD8, 0xFF, 0x00, 0xF2, 0x0D, 0x63, 0xFF,
+	0x00, 0x10, 0xB7, 0x35, 0x52, 0x4F, 0xDC, 0xFB, 0xDF, 0xF9, 0x15, 0xFE, 0xB1, 0xE0, 0x6D, 0xD7,
+	0xEE, 0xFF, 0x00, 0x82, 0x7E, 0x46, 0xB7, 0xC5, 0x2D, 0x66, 0x69, 0x17, 0xFE, 0x2A, 0x1B, 0x86,
+	0xDA, 0xDB, 0xB6, 0xB5, 0xC3, 0x6D, 0xFF, 0x00, 0xBE, 0x77, 0x55, 0xC8, 0x7E, 0x30, 0x6B, 0xD1,
+	0xFE, 0xEF, 0xFB, 0x7A, 0xEB, 0x11, 0xB7, 0xFC, 0xFC, 0x35, 0x7E, 0xAD, 0xDE, 0x7F, 0xC1, 0xB7,
+	0x1F, 0xB1, 0x65, 0xC5, 0xCA, 0xCD, 0x6B, 0xF1, 0xA3, 0xE2, 0xFD, 0x9A, 0x2A, 0xA8, 0xF2, 0x6D,
+	0xF5, 0xCD, 0x25, 0x94, 0x9F, 0xEF, 0x66, 0x4D, 0x31, 0x9B, 0xFF, 0x00, 0x1E, 0xED, 0x51, 0x8F,
+	0xF8, 0x36, 0xAB, 0xF6, 0x31, 0x55, 0xDA, 0xBF, 0x1E, 0x7E, 0x32, 0x2F, 0xFD, 0xC6, 0xB4, 0x6F,
+	0xFE, 0x54, 0xD6, 0x75, 0x3C, 0x2F, 0xCD, 0xA7, 0xA4, 0x94, 0x1A, 0xF5, 0xFF, 0x00, 0x80, 0x35,
+	0xC4, 0x58, 0x2D, 0xDB, 0x7F, 0x71, 0xF9, 0x77, 0x63, 0xF1, 0xBB, 0xC4, 0x2A, 0xCB, 0xE7, 0x6B,
+	0xD7, 0x1F, 0x7B, 0xE5, 0x5F, 0xB4, 0x37, 0xFF, 0x00, 0x15, 0xFE, 0x77, 0x56, 0xB2, 0xFC, 0x7E,
+	0xD6, 0x21, 0x85, 0xAD, 0xD3, 0x5F, 0x99, 0x1F, 0xFE, 0x5A, 0xB2, 0xB3, 0x6D, 0x5F, 0xFC, 0x7A,
+	0xBF, 0x4A, 0x3F, 0xE2, 0x1A, 0xCF, 0xD9, 0x2D, 0x5F, 0xFD, 0x1F, 0xF6, 0x82, 0xF8, 0xB0, 0x13,
+	0xF8, 0x56, 0x6B, 0xDD, 0x25, 0xDB, 0xF1, 0x3F, 0xD9, 0xEB, 0xBB, 0xF2, 0xA7, 0x1F, 0xF8, 0x36,
+	0xCF, 0xF6, 0x53, 0x28, 0x54, 0xFE, 0xD1, 0x5F, 0x15, 0x3F, 0xF0, 0x2B, 0x4B, 0xFF, 0x00, 0xE4,
+	0x1A, 0xF3, 0xAA, 0xF8, 0x3F, 0x98, 0x54, 0xDE, 0x10, 0xFB, 0xD7, 0xF9, 0x1B, 0xD3, 0xE2, 0x8C,
+	0x14, 0x7E, 0xD3, 0xFB, 0x8F, 0xCC, 0xD9, 0x3E, 0x3E, 0x6B, 0xD7, 0x2C, 0xCB, 0xFD, 0xBD, 0x37,
+	0xCB, 0xF3, 0x33, 0x2C, 0xFF, 0x00, 0xFD, 0x95, 0x39, 0x7E, 0x3C, 0x78, 0x81, 0xBE, 0x47, 0xF1,
+	0x05, 0xD2, 0x8F, 0xBD, 0xB7, 0xED, 0x0D, 0xFF, 0x00, 0xC5, 0x7F, 0x76, 0xBF, 0x47, 0x3F, 0xE2,
+	0x1A, 0x8F, 0x80, 0xF9, 0x6F, 0xF8, 0xCA, 0x4F, 0x1E, 0x7C, 0xCB, 0xF3, 0x66, 0xCE, 0xC7, 0xFF,
+	0x00, 0x8D, 0xD4, 0x77, 0x3F, 0xF0, 0x6D, 0x6F, 0xC1, 0x73, 0x6E, 0x7F, 0xB3, 0x7F, 0x6A, 0x6F,
+	0x1A, 0x47, 0x36, 0xED, 0xCB, 0x25, 0xC6, 0x99, 0x67, 0x22, 0x8F, 0x9B, 0x9F, 0x95, 0x55, 0x7F,
+	0xF4, 0x2A, 0xC5, 0xF8, 0x3D, 0x9A, 0x46, 0x36, 0x8C, 0x21, 0xFF, 0x00, 0x81, 0x23, 0x6F, 0xF5,
+	0xAB, 0x02, 0xF4, 0x73, 0x7F, 0x73, 0x3F, 0x3B, 0x65, 0xF8, 0xFF, 0x00, 0xE2, 0x1F, 0x27, 0xC9,
+	0x7F, 0x10, 0xDC, 0x2B, 0x37, 0xF7, 0xA5, 0x6F, 0xFE, 0x2A, 0xA2, 0x93, 0xE3, 0xE7, 0x89, 0xDE,
+	0x43, 0xFF, 0x00, 0x15, 0x1D, 0xD2, 0xEE, 0xF9, 0xB7, 0x2D, 0xC3, 0x7C, 0xD5, 0xFA, 0x14, 0xDF,
+	0xF0, 0x6D, 0x47, 0xC3, 0xF2, 0xA7, 0x67, 0xED, 0x77, 0xE2, 0x45, 0x6D, 0xBB, 0x77, 0x7F, 0xC2,
+	0x37, 0x6F, 0xFF, 0x00, 0xC7, 0x2A, 0xA6, 0xA3, 0xFF, 0x00, 0x06, 0xD2, 0x78, 0x69, 0xD9, 0x64,
+	0xD1, 0xBF, 0x6C, 0x6D, 0x56, 0x13, 0xB4, 0xF9, 0x9F, 0x6C, 0xF0, 0x64, 0x73, 0x6E, 0xF4, 0xDB,
+	0xB6, 0xEA, 0x3D, 0xB5, 0x8C, 0x7C, 0x1D, 0xCD, 0xA9, 0xAD, 0x29, 0xC7, 0xFF, 0x00, 0x02, 0x41,
+	0xFE, 0xB4, 0x65, 0xFF, 0x00, 0xCE, 0xFE, 0xE6, 0x7C, 0x10, 0x3F, 0x68, 0x3F, 0x13, 0xC9, 0x1F,
+	0x92, 0x3C, 0x43, 0x74, 0x42, 0xFC, 0xAB, 0xBA, 0xE1, 0xA9, 0x3F, 0xE1, 0xA1, 0x7C, 0x54, 0x8B,
+	0xB3, 0xFE, 0x12, 0x1B, 0xA5, 0xDC, 0xDF, 0x2A, 0xFD, 0xA1, 0xAB, 0xEF, 0x06, 0xFF, 0x00, 0x83,
+	0x67, 0xAC, 0xF3, 0x9F, 0xF8, 0x6D, 0x3B, 0xAF, 0xBD, 0xBB, 0xFE, 0x44, 0x15, 0xFF, 0x00, 0xE4,
+	0xEA, 0xAD, 0x75, 0xFF, 0x00, 0x06, 0xCE, 0x4F, 0x23, 0x7F, 0xA3, 0x7E, 0xDB, 0xD2, 0x2A, 0xFF,
+	0x00, 0xD3, 0x4F, 0x87, 0x3B, 0xBF, 0xF7, 0x21, 0x51, 0xFF, 0x00, 0x10, 0x6F, 0x34, 0xEB, 0x46,
+	0x1F, 0xF8, 0x14, 0x4A, 0x5C, 0x51, 0x80, 0xB7, 0xF1, 0x1F, 0xDC, 0xFF, 0x00, 0xC8, 0xF8, 0x8A,
+	0xDB, 0xF6, 0x8C, 0xF1, 0x50, 0xDA, 0x9F, 0xF0, 0x91, 0xDE, 0x32, 0xED, 0xFB, 0xBF, 0x68, 0x6F,
+	0xFE, 0x2A, 0xAC, 0x47, 0xFB, 0x4C, 0x78, 0xB6, 0x1D, 0xBF, 0xF1, 0x50, 0xDE, 0x7C, 0xCB, 0xF2,
+	0xED, 0x99, 0xB6, 0xFF, 0x00, 0x9F, 0xFE, 0x26, 0xBE, 0xD0, 0x1F, 0xF0, 0x6C, 0xC6, 0xA0, 0x0E,
+	0x53, 0xF6, 0xE7, 0x91, 0x7F, 0xDD, 0xF8, 0x73, 0xFF, 0x00, 0xDF, 0x0A, 0xA7, 0x73, 0xFF, 0x00,
+	0x06, 0xCE, 0x78, 0xED, 0xA6, 0x63, 0x6F, 0xFB, 0x70, 0x59, 0xF9, 0x65, 0xFE, 0x5D, 0xDF, 0x0F,
+	0x58, 0x36, 0xDF, 0xFC, 0x0E, 0xFB, 0xD5, 0x95, 0x4F, 0x06, 0x33, 0x17, 0x2D, 0x68, 0x41, 0xFC,
+	0xE2, 0x1F, 0xEB, 0x46, 0x0F, 0xA4, 0xDF, 0xDC, 0xFF, 0x00, 0xC8, 0xF9, 0x1E, 0x3F, 0xDA, 0xAB,
+	0xC5, 0x56, 0xAA, 0xA9, 0xFD, 0xBD, 0x74, 0xBB, 0xBF, 0x89, 0x65, 0x6F, 0xEF, 0x7F, 0xBD, 0xFE,
+	0xED, 0x47, 0x27, 0xED, 0x91, 0xE3, 0x0B, 0x36, 0xF9, 0x35, 0xEB, 0x8D, 0xDB, 0xBE, 0xEF, 0x99,
+	0xB9, 0xAB, 0xEB, 0x4B, 0x9F, 0xF8, 0x36, 0x67, 0xE2, 0x51, 0x80, 0xB4, 0x3F, 0xB7, 0x1E, 0x9E,
+	0xF2, 0x2A, 0xFE, 0xEB, 0xCE, 0xF8, 0x7A, 0xDB, 0x7F, 0xF4, 0xBA, 0xB3, 0x57, 0xFE, 0x0D, 0x92,
+	0xF8, 0xDC, 0xDB, 0xBC, 0xEF, 0xDB, 0x6F, 0x41, 0x65, 0x66, 0xFB, 0xAB, 0xE0, 0x59, 0xBF, 0xF9,
+	0x32, 0xA2, 0x3E, 0x09, 0x62, 0x2F, 0xEF, 0xE1, 0xE0, 0xFE, 0x71, 0x2B, 0xFD, 0x6C, 0xC3, 0x72,
+	0xE9, 0x51, 0xFD, 0xCC, 0xF9, 0x57, 0xFE, 0x1B, 0x53, 0xC6, 0x7F, 0xC1, 0xAC, 0x5C, 0x32, 0xFF,
+	0x00, 0x0A, 0xB4, 0xAD, 0x51, 0xBF, 0xED, 0xA9, 0xE3, 0x9F, 0x38, 0xEC, 0xD7, 0xAE, 0x15, 0x95,
+	0xB7, 0x7D, 0xED, 0xDB, 0x6B, 0xEA, 0x8B, 0xAF, 0xF8, 0x36, 0x43, 0xE3, 0x84, 0x70, 0xB3, 0x58,
+	0xFE, 0xDA, 0x5E, 0x1F, 0x79, 0x19, 0xB7, 0x7E, 0xFB, 0xC1, 0x13, 0x05, 0xFF, 0x00, 0xD2, 0xAF,
+	0xA5, 0x56, 0x6F, 0xF8, 0x36, 0x3B, 0xF6, 0x84, 0x93, 0xEF, 0xFE, 0xD8, 0xDE, 0x15, 0xFF, 0x00,
+	0xC2, 0x36, 0xE3, 0xFF, 0x00, 0x92, 0xAB, 0x7F, 0xF8, 0x82, 0xF6, 0xDF, 0x0B, 0x17, 0xF3, 0x46,
+	0x72, 0xE2, 0x9A, 0x72, 0xDA, 0xAF, 0xE1, 0xFF, 0x00, 0x00, 0xF9, 0x69, 0xBF, 0x6C, 0xEF, 0x88,
+	0x4A, 0xAC, 0xFF, 0x00, 0xF0, 0x90, 0xDE, 0x2F, 0xCC, 0xBF, 0xF2, 0xD5, 0xBE, 0xED, 0x36, 0x3F,
+	0xDB, 0x53, 0xC7, 0xB0, 0xFF, 0x00, 0xCC, 0xC7, 0x74, 0xDF, 0xF0, 0x25, 0xAF, 0xA8, 0x35, 0x0F,
+	0xF8, 0x36, 0x5F, 0xF6, 0x95, 0x50, 0x86, 0xCB, 0xF6, 0xB2, 0xF0, 0x65, 0xC3, 0x7C, 0xDE, 0x67,
+	0x9D, 0xE1, 0x9B, 0xA8, 0x76, 0xFF, 0x00, 0x77, 0x6E, 0x24, 0x93, 0xDE, 0xA1, 0xFF, 0x00, 0x88,
+	0x66, 0x3F, 0x69, 0xDE, 0x4F, 0xFC, 0x35, 0x0F, 0x81, 0x77, 0x7F, 0x7B, 0xFB, 0x1A, 0xF2, 0x87,
+	0xE0, 0xD7, 0xFD, 0x42, 0x2F, 0xBE, 0x3F, 0xE6, 0x4A, 0xE2, 0x6A, 0x6A, 0x57, 0x55, 0x7F, 0x07,
+	0xFE, 0x47, 0xCD, 0x70, 0xFE, 0xDB, 0x5E, 0x3C, 0x86, 0x65, 0x99, 0x7C, 0x49, 0x74, 0xAE, 0xAC,
+	0xAC, 0xAD, 0xBB, 0xFC, 0xFF, 0x00, 0xB3, 0x53, 0x6A, 0x5F, 0xB7, 0x67, 0xC4, 0xBD, 0x6A, 0x56,
+	0xBF, 0xD4, 0x7C, 0x55, 0x75, 0x33, 0x6D, 0xDB, 0xB7, 0x62, 0xFD, 0xD5, 0xFE, 0xEF, 0xCB, 0x5F,
+	0x40, 0xDF, 0x7F, 0xC1, 0xB4, 0x7F, 0xB5, 0xF2, 0xCD, 0xE5, 0x58, 0x7E, 0xD1, 0xBF, 0x0F, 0x6E,
+	0x22, 0xDB, 0xFE, 0xBA, 0xE2, 0x1B, 0xF4, 0x93, 0x77, 0xFB, 0xBE, 0x4B, 0x7F, 0xE8, 0x55, 0x13,
+	0x7F, 0xC1, 0xB4, 0xFF, 0x00, 0xB6, 0x5B, 0x6D, 0x4F, 0xF8, 0x68, 0x1F, 0x86, 0xA1, 0x57, 0xFB,
+	0xAB, 0xA8, 0x7F, 0xF2, 0x3F, 0xF9, 0xDB, 0x4F, 0xFE, 0x21, 0x0D, 0x48, 0xC1, 0xD2, 0x58, 0x5F,
+	0x75, 0xBB, 0xB5, 0x78, 0xDB, 0x4D, 0xBA, 0x95, 0xFE, 0xB3, 0x51, 0xE6, 0xBB, 0xAA, 0xBE, 0xEF,
+	0xF8, 0x07, 0xCF, 0xB1, 0xFE, 0xDD, 0x1F, 0x14, 0x6C, 0x64, 0x64, 0xD3, 0x7C, 0x61, 0x7D, 0x6E,
+	0xB2, 0x7D, 0xE5, 0x8E, 0x5D, 0xBB, 0xBE, 0x5A, 0x85, 0xBF, 0x6E, 0x1F, 0x89, 0x66, 0x37, 0xCF,
+	0x8C, 0x2F, 0x1B, 0x74, 0x9B, 0x9B, 0x74, 0xBF, 0x79, 0xBF, 0xDA, 0xAF, 0x76, 0x7F, 0xF8, 0x36,
+	0xCB, 0xF6, 0xF5, 0x06, 0x45, 0x87, 0xE3, 0x27, 0xC2, 0x72, 0xBF, 0x36, 0xD6, 0x6D, 0x53, 0x54,
+	0x5F, 0xFC, 0x77, 0xFB, 0x3F, 0xFF, 0x00, 0x8A, 0xA8, 0xEE, 0x7F, 0xE0, 0xDB, 0x3F, 0xDB, 0xEC,
+	0x44, 0x44, 0x1F, 0x17, 0x3E, 0x11, 0xC8, 0xEA, 0xAD, 0xB5, 0x64, 0xD6, 0x35, 0x55, 0xCB, 0x7F,
+	0x0F, 0xCD, 0xFD, 0x9E, 0xD5, 0xBC, 0x3C, 0x29, 0xC4, 0x46, 0x9A, 0x82, 0xC3, 0x68, 0xB6, 0x57,
+	0xD1, 0x5F, 0x7D, 0x2E, 0x4B, 0xE2, 0x4C, 0x3B, 0xD7, 0xDA, 0x2F, 0xEB, 0xE4, 0x78, 0x8D, 0xC7,
+	0xED, 0xF5, 0xF1, 0x8E, 0xE1, 0xA3, 0x9A, 0x6F, 0x1E, 0x6A, 0x12, 0x3C, 0x2D, 0xBA, 0x26, 0x6B,
+	0x8D, 0xDE, 0x5B, 0x55, 0x7D, 0x43, 0xF6, 0xF4, 0xF8, 0xCD, 0xA8, 0x5D, 0x47, 0xA8, 0x5E, 0x78,
+	0xE6, 0xF9, 0xE4, 0x8F, 0xE5, 0x8B, 0x74, 0xBF, 0x34, 0x7F, 0xC2, 0xDB, 0x7F, 0xBB, 0x5E, 0xD4,
+	0x9F, 0xF0, 0x6D, 0xEF, 0xFC, 0x14, 0x80, 0x6D, 0x1F, 0xF0, 0xB1, 0x7E, 0x0C, 0x6D, 0x5E, 0x3F,
+	0xE4, 0x6A, 0xD6, 0x3F, 0xF9, 0x4F, 0x51, 0x5C, 0x7F, 0xC1, 0xB8, 0x7F, 0xF0, 0x52, 0x1B, 0x18,
+	0x1A, 0x6B, 0x4F, 0x1B, 0x7C, 0x1E, 0xB9, 0x3B, 0xB7, 0x2D, 0xBC, 0x3E, 0x2D, 0xD5, 0x15, 0xB7,
+	0x7F, 0x7B, 0xF7, 0x9A, 0x4A, 0xAF, 0x7A, 0xE8, 0x7E, 0x1B, 0xE3, 0xDC, 0x5A, 0x74, 0x64, 0xEF,
+	0xFD, 0xEF, 0xBB, 0xAF, 0x42, 0x16, 0x7D, 0x43, 0xFE, 0x7E, 0x2F, 0xBB, 0xFE, 0x01, 0xE2, 0x96,
+	0xFF, 0x00, 0xB6, 0xF7, 0xC5, 0x11, 0x1C, 0xD6, 0xDF, 0xF0, 0x98, 0x5C, 0x2A, 0xCD, 0xFE, 0xBB,
+	0x6B, 0x7C, 0xB2, 0x7C, 0xCD, 0xF7, 0xAA, 0xCE, 0xA1, 0xFB, 0x7A, 0x7C, 0x63, 0xBB, 0xD2, 0xD7,
+	0x4A, 0x9F, 0xC7, 0x37, 0xDF, 0x66, 0x65, 0xDB, 0xE4, 0xB3, 0x6D, 0xDA, 0xBF, 0xC3, 0xFE, 0xF2,
+	0xD7, 0xA9, 0xFF, 0x00, 0xC4, 0x39, 0xFF, 0x00, 0xF0, 0x53, 0x1D, 0xAC, 0x3F, 0xB5, 0x7E, 0x16,
+	0xFF, 0x00, 0xB2, 0xBF, 0xF0, 0x97, 0xDE, 0x7F, 0xF2, 0x0D, 0x55, 0xBF, 0xFF, 0x00, 0x83, 0x79,
+	0x3F, 0xE0, 0xA7, 0x5A, 0x76, 0x3C, 0x9B, 0x3F, 0x87, 0x77, 0xDE, 0x62, 0xFD, 0xEB, 0x2F, 0x1A,
+	0x48, 0xBE, 0x5F, 0xFB, 0xDE, 0x6D, 0xAA, 0xFF, 0x00, 0xE3, 0xBF, 0xDD, 0xA9, 0xA7, 0xE1, 0x9D,
+	0x7A, 0x2E, 0xF0, 0xC3, 0x35, 0x75, 0x67, 0xD2, 0xEB, 0x7E, 0xE6, 0x9F, 0xEB, 0x05, 0x29, 0x7F,
+	0xCB, 0xD4, 0x79, 0x5D, 0x9F, 0xED, 0xDD, 0xF1, 0x8F, 0x4A, 0xBC, 0x5B, 0xCB, 0x3F, 0x1B, 0x5D,
+	0x46, 0xEA, 0xBB, 0x15, 0xB6, 0xFF, 0x00, 0x0F, 0xF7, 0x7F, 0xBB, 0xFF, 0x00, 0xED, 0x54, 0xD0,
+	0xFE, 0xDF, 0x9F, 0x1A, 0x6D, 0xEF, 0xA6, 0xD6, 0x2D, 0xBC, 0x6D, 0x74, 0xB7, 0x53, 0x7C, 0xB2,
+	0xCD, 0xBB, 0xEF, 0x7F, 0xB2, 0xDF, 0xDE, 0xFF, 0x00, 0xBE, 0x7F, 0xE0, 0x35, 0xE8, 0x69, 0xFF,
+	0x00, 0x06, 0xFA, 0xFF, 0x00, 0xC1, 0x50, 0xFE, 0x62, 0xFE, 0x15, 0xF0, 0x46, 0xE6, 0xFB, 0xCD,
+	0xFF, 0x00, 0x09, 0x8A, 0xFF, 0x00, 0xF1, 0xBA, 0xA9, 0x73, 0xFF, 0x00, 0x04, 0x0D, 0xFF, 0x00,
+	0x82, 0xA2, 0x69, 0x77, 0x8D, 0x0C, 0x3F, 0x0B, 0x3C, 0x37, 0x7C, 0xBB, 0x72, 0xB3, 0x5A, 0xF8,
+	0xD2, 0xDB, 0xC9, 0xFF, 0x00, 0xBE, 0x64, 0x65, 0x6D, 0xDF, 0xF0, 0x1A, 0x17, 0x87, 0x38, 0xA8,
+	0xDA, 0xD8, 0x69, 0x68, 0xEF, 0xD7, 0x7E, 0xFE, 0xA2, 0x96, 0x7D, 0x4E, 0x5B, 0xD5, 0x5F, 0x81,
+	0xC7, 0xC3, 0xFB, 0x78, 0x7C, 0x63, 0xBE, 0xBA, 0x9A, 0xF2, 0xFF, 0x00, 0xC6, 0xB7, 0x52, 0x3D,
+	0xC4, 0x4A, 0x8D, 0x23, 0x36, 0xED, 0xD1, 0xFF, 0x00, 0x0A, 0xFF, 0x00, 0xE3, 0xD5, 0x7E, 0xFB,
+	0xF6, 0xFC, 0xF8, 0xAF, 0x79, 0xA4, 0xB6, 0x8B, 0x37, 0x8C, 0x24, 0x6B, 0x75, 0x5D, 0xDE, 0x5B,
+	0x2A, 0xFC, 0xDF, 0xEF, 0x7C, 0xBB, 0xAB, 0x6B, 0xFE, 0x1C, 0x3D, 0xFF, 0x00, 0x05, 0x4E, 0xDD,
+	0xBB, 0xFE, 0x14, 0xA6, 0x8B, 0xFF, 0x00, 0x85, 0xA6, 0x9F, 0xFF, 0x00, 0xC7, 0x2A, 0x9C, 0xFF,
+	0x00, 0xF0, 0x44, 0x8F, 0xF8, 0x2B, 0x04, 0x73, 0xB4, 0x11, 0xFE, 0xCB, 0xAB, 0x26, 0xDE, 0x3C,
+	0xE8, 0xFC, 0x6D, 0xA1, 0xAA, 0xB7, 0xFB, 0xBF, 0xE9, 0xCA, 0xDF, 0xF7, 0xD2, 0xFF, 0x00, 0x0D,
+	0x73, 0xD6, 0xF0, 0xE3, 0x1D, 0x29, 0x39, 0x3A, 0x13, 0xD7, 0x7D, 0xFF, 0x00, 0x11, 0xC7, 0x3A,
+	0xC3, 0xF2, 0xAF, 0xDE, 0x47, 0x4F, 0x43, 0x22, 0xC7, 0xF6, 0xFB, 0xF8, 0xCD, 0xA4, 0xDA, 0xB6,
+	0x9B, 0xA6, 0xF8, 0xC1, 0xA1, 0xB7, 0x93, 0xEF, 0x2A, 0xAA, 0xFC, 0xDF, 0xEC, 0xEE, 0xDB, 0xBA,
+	0x8F, 0xF8, 0x6E, 0xEF, 0x8A, 0x2B, 0xA7, 0xC7, 0x61, 0x73, 0xE2, 0x1D, 0xF6, 0xF1, 0xFC, 0xD1,
+	0x47, 0xB3, 0xEE, 0xB5, 0x6B, 0x4B, 0xFF, 0x00, 0x04, 0x4B, 0xFF, 0x00, 0x82, 0xAE, 0xE1, 0x99,
+	0xFF, 0x00, 0x65, 0x86, 0xF9, 0x7F, 0xEA, 0x74, 0xD0, 0xDB, 0x77, 0xFE, 0x4F, 0x7D, 0xDF, 0xF6,
+	0x6A, 0x15, 0xFF, 0x00, 0x82, 0x28, 0x7F, 0xC1, 0x56, 0x7C, 0xE5, 0x67, 0xFD, 0x94, 0x66, 0x75,
+	0xFE, 0xF3, 0x78, 0xC3, 0x43, 0xFF, 0x00, 0xE4, 0xEA, 0xCA, 0x5E, 0x1C, 0xE2, 0xAB, 0x53, 0x54,
+	0xEA, 0x61, 0xA6, 0xE2, 0x95, 0xAD, 0x67, 0x6B, 0x76, 0x2D, 0x67, 0x94, 0xB9, 0xAE, 0xAA, 0x2F,
+	0xBC, 0xCC, 0x9B, 0xF6, 0xF0, 0xF1, 0xDC, 0x28, 0xBB, 0x35, 0x58, 0xD7, 0xFE, 0xFA, 0xF9, 0x69,
+	0xEB, 0xFB, 0x78, 0x78, 0xE5, 0x60, 0xD8, 0xF7, 0xF1, 0xB7, 0xCD, 0xB7, 0x77, 0x94, 0xDF, 0x77,
+	0xFE, 0xFA, 0xA9, 0xB5, 0x0F, 0xF8, 0x22, 0xD7, 0xFC, 0x15, 0x66, 0xD6, 0x16, 0xBA, 0x7F, 0xD9,
+	0x36, 0xF1, 0x95, 0x78, 0xDB, 0x0F, 0x8B, 0x74, 0x59, 0x19, 0xBF, 0xE0, 0x2B, 0x79, 0xBA, 0xA8,
+	0x4D, 0xFF, 0x00, 0x04, 0x6D, 0xFF, 0x00, 0x82, 0xA9, 0xB3, 0x6F, 0x4F, 0xD9, 0x17, 0x56, 0x65,
+	0xFE, 0x1F, 0xF8, 0x9F, 0x69, 0x6A, 0xCB, 0xFF, 0x00, 0x93, 0x95, 0xCF, 0xFF, 0x00, 0x10, 0x9B,
+	0x0E, 0xE3, 0x67, 0x82, 0x7F, 0xF8, 0x09, 0x6B, 0x88, 0x3B, 0xD5, 0x5F, 0x79, 0x6A, 0x2F, 0xF8,
+	0x28, 0x77, 0xC5, 0x7D, 0x0D, 0x64, 0xB3, 0xD1, 0x3C, 0x42, 0xD1, 0xA4, 0xCD, 0xFB, 0xD5, 0x8D,
+	0x59, 0x7E, 0xED, 0x5D, 0x6F, 0xF8, 0x29, 0x97, 0xC6, 0x3F, 0xB1, 0x7F, 0x66, 0xCD, 0xAC, 0x5A,
+	0xC8, 0x9F, 0x79, 0x7C, 0xCB, 0x7D, 0xDB, 0x7F, 0xEF, 0x96, 0xAC, 0x0D, 0x43, 0xFE, 0x09, 0x07,
+	0xFF, 0x00, 0x05, 0x43, 0xD3, 0x7C, 0xB3, 0x37, 0xEC, 0x7B, 0xE2, 0x07, 0xDE, 0xBF, 0x2F, 0xD9,
+	0xF5, 0x5D, 0x3E, 0x46, 0x4F, 0xFB, 0xE6, 0xE1, 0xBF, 0xD9, 0xAA, 0xDF, 0xF0, 0xE9, 0x5F, 0xF8,
+	0x29, 0xE9, 0xDA, 0x9F, 0xF0, 0xC6, 0xFE, 0x28, 0xDA, 0xAB, 0xF2, 0xFF, 0x00, 0xA4, 0x59, 0xFC,
+	0xBF, 0xF9, 0x31, 0x5E, 0x8E, 0x1F, 0x80, 0x71, 0x18, 0x5A, 0x2A, 0x95, 0x3C, 0x3C, 0xD4, 0x56,
+	0x96, 0x57, 0xB7, 0xDD, 0xB1, 0x94, 0xB3, 0x8A, 0x75, 0x25, 0xCC, 0xEA, 0x45, 0xFD, 0xDF, 0xA9,
+	0xD3, 0x5D, 0x7F, 0xC1, 0x49, 0xBE, 0x31, 0xEA, 0x16, 0x6B, 0x67, 0x73, 0xAA, 0xDB, 0xA5, 0xBB,
+	0x7C, 0xDF, 0xBB, 0xB7, 0xD8, 0xDF, 0x2F, 0xFB, 0x5B, 0xBE, 0x5F, 0xF8, 0x0D, 0x3A, 0x4F, 0xF8,
+	0x29, 0xF7, 0xC7, 0xB5, 0xB3, 0x7B, 0x6B, 0x3D, 0x7A, 0x16, 0x49, 0x3E, 0xF6, 0xDB, 0x7F, 0x9A,
+	0x45, 0xFF, 0x00, 0x6B, 0xE6, 0xFF, 0x00, 0xE2, 0x6B, 0x8B, 0xD4, 0x3F, 0xE0, 0x95, 0x5F, 0xF0,
+	0x53, 0x2B, 0x3B, 0xA5, 0xB7, 0x9B, 0xF6, 0x2B, 0xF1, 0x83, 0x9D, 0xBB, 0xB7, 0x5B, 0xC5, 0x6E,
+	0xEB, 0xFF, 0x00, 0x7D, 0x2C, 0x9F, 0x7A, 0xA0, 0x93, 0xFE, 0x09, 0x6F, 0xFF, 0x00, 0x05, 0x2F,
+	0x66, 0x67, 0xFF, 0x00, 0x86, 0x2A, 0xF1, 0xC7, 0xFE, 0x01, 0xC3, 0xFF, 0x00, 0xC7, 0x2B, 0x68,
+	0xF0, 0x5E, 0x32, 0x15, 0x2E, 0xA8, 0xCF, 0xB6, 0xCF, 0x63, 0x2F, 0xED, 0x4A, 0x32, 0xF8, 0xA5,
+	0x17, 0xF3, 0x47, 0x77, 0x6F, 0xFF, 0x00, 0x05, 0x40, 0xF8, 0xF1, 0x0D, 0x9A, 0x5B, 0x4D, 0xAD,
+	0x43, 0x34, 0x71, 0xFC, 0xDE, 0x5C, 0xD1, 0x37, 0xCD, 0xFE, 0xF7, 0xCD, 0x59, 0xF7, 0xDF, 0xF0,
+	0x50, 0x4F, 0x89, 0x1E, 0x20, 0xBA, 0x5B, 0xCD, 0x6E, 0x68, 0x58, 0xED, 0xDA, 0xAB, 0xB5, 0xBF,
+	0x76, 0xBF, 0xDD, 0x5A, 0xE2, 0x2E, 0x3F, 0xE0, 0x9A, 0x9F, 0xF0, 0x52, 0x28, 0x25, 0xFB, 0x34,
+	0x9F, 0xB1, 0x2F, 0xC4, 0x2D, 0xDD, 0x25, 0xF2, 0xF4, 0x16, 0x65, 0xFF, 0x00, 0xBE, 0x97, 0xE5,
+	0x6A, 0x92, 0x1F, 0xF8, 0x26, 0xAF, 0xFC, 0x14, 0x5B, 0x6E, 0xD4, 0xFD, 0x8B, 0x3E, 0x22, 0x7F,
+	0x77, 0xE6, 0xD0, 0x64, 0x5F, 0x96, 0xB3, 0xC7, 0x70, 0x3D, 0x5C, 0x75, 0x15, 0x4A, 0xB5, 0x09,
+	0x49, 0x76, 0xB3, 0x1D, 0x3C, 0xCA, 0x10, 0x9F, 0x3C, 0x67, 0x14, 0xFD, 0x57, 0xF9, 0x9E, 0x81,
+	0xA5, 0xFE, 0xDB, 0x5A, 0xC2, 0xAE, 0xFB, 0x93, 0x1E, 0xE5, 0xDB, 0xBB, 0xFD, 0xEA, 0xD7, 0x93,
+	0xF6, 0xDA, 0xF3, 0x17, 0x7F, 0xCB, 0xFE, 0xCF, 0xCD, 0xF7, 0xBF, 0xCE, 0xEA, 0xF2, 0x18, 0xFF,
+	0x00, 0xE0, 0x9E, 0x3F, 0xB7, 0xFF, 0x00, 0xFD, 0x19, 0x87, 0xC4, 0xCF, 0xEE, 0xED, 0x6F, 0x06,
+	0xDD, 0x7F, 0xF1, 0xBA, 0xB0, 0xBF, 0xF0, 0x4F, 0x3F, 0xDB, 0xFE, 0xDE, 0x3F, 0xB4, 0x3F, 0xEC,
+	0x73, 0xF1, 0x31, 0x7C, 0xB5, 0xDC, 0xDB, 0x7C, 0x1F, 0x75, 0xFC, 0x3F, 0xDD, 0x55, 0x8E, 0xBE,
+	0x62, 0xB7, 0x84, 0xB8, 0x49, 0x7B, 0xCB, 0x0D, 0x25, 0xF2, 0x67, 0x7C, 0x33, 0xD9, 0x72, 0xD9,
+	0xCD, 0x7D, 0xE8, 0xF5, 0x55, 0xFD, 0xB3, 0xBE, 0xD7, 0xF7, 0x1D, 0x7E, 0xF2, 0xFD, 0xE6, 0xA8,
+	0x66, 0xFD, 0xB0, 0x26, 0x66, 0xDE, 0xF0, 0xC2, 0xAB, 0xBB, 0xEE, 0xEE, 0xAF, 0x2C, 0xB7, 0xFD,
+	0x83, 0x7F, 0x6E, 0xA5, 0x8F, 0x67, 0xFC, 0x31, 0xFF, 0x00, 0xC5, 0x25, 0xFF, 0x00, 0x6B, 0xFE,
+	0x10, 0x3D, 0x43, 0x6F, 0xFE, 0x89, 0xA7, 0x5C, 0x7E, 0xC3, 0x7F, 0xB7, 0x0D, 0xBD, 0xBB, 0x5C,
+	0xDC, 0xFE, 0xC8, 0x5F, 0x15, 0x95, 0x55, 0x57, 0x77, 0x97, 0xF0, 0xEF, 0x52, 0x66, 0x5F, 0xF8,
+	0x0A, 0xC2, 0xDF, 0xEC, 0xD7, 0x22, 0xF0, 0xAE, 0x1C, 0xDA, 0x61, 0xA7, 0xFF, 0x00, 0x80, 0xB2,
+	0xFF, 0x00, 0xB6, 0x97, 0xF3, 0xAF, 0xBD, 0x1E, 0x95, 0xFF, 0x00, 0x0D, 0x78, 0x92, 0x48, 0xDF,
+	0xB9, 0x8D, 0x97, 0x6E, 0xC7, 0x66, 0x66, 0xF9, 0x9B, 0xFE, 0xF9, 0xAC, 0x9D, 0x43, 0xE3, 0x26,
+	0x81, 0xE2, 0x5D, 0x49, 0xB5, 0x5B, 0x94, 0xDA, 0xCC, 0xBF, 0x32, 0xAF, 0xCD, 0xBB, 0xE5, 0xFF,
+	0x00, 0x3F, 0xF7, 0xD5, 0x70, 0x56, 0xFF, 0x00, 0xB1, 0x7F, 0xED, 0xAA, 0xAA, 0xBF, 0xF1, 0x88,
+	0x5F, 0x16, 0xBF, 0xE0, 0x5F, 0x0C, 0x75, 0x6F, 0xFE, 0x47, 0xAB, 0x6B, 0xFB, 0x1F, 0xFE, 0xD8,
+	0x7A, 0x4C, 0x26, 0xEF, 0x55, 0xFD, 0x95, 0x3E, 0x29, 0x5B, 0x42, 0xAD, 0xF3, 0x4D, 0x37, 0xC3,
+	0x9D, 0x52, 0x38, 0xD7, 0xFE, 0x04, 0xD6, 0xEB, 0xFC, 0x55, 0x5F, 0xF1, 0x0C, 0xEA, 0x50, 0xD6,
+	0x96, 0x1E, 0x69, 0xF9, 0x45, 0x87, 0xF6, 0xAD, 0x39, 0xAF, 0x7A, 0x6B, 0xEF, 0x5F, 0xE6, 0x7A,
+	0x06, 0x9B, 0xE3, 0x2F, 0x0D, 0xDE, 0x32, 0xC2, 0x8E, 0xAA, 0xAD, 0xB5, 0x5B, 0x74, 0x7B, 0xBE,
+	0x5F, 0xFD, 0x97, 0xF8, 0xAB, 0xB5, 0xF8, 0x58, 0x1F, 0xC4, 0xFF, 0x00, 0x16, 0xBC, 0x23, 0xE1,
+	0xEF, 0x0E, 0xDE, 0x34, 0x77, 0xDA, 0x87, 0x8A, 0x34, 0xD8, 0x6D, 0xE4, 0x8D, 0xB7, 0x34, 0x72,
+	0x35, 0xC4, 0x6A, 0xAD, 0xFF, 0x00, 0x7D, 0x32, 0xD7, 0x8D, 0x68, 0xFF, 0x00, 0xB3, 0xBF, 0xED,
+	0x33, 0x6E, 0xCA, 0xEF, 0xFB, 0x3D, 0xF8, 0xFB, 0xEE, 0xFC, 0xCB, 0xFF, 0x00, 0x08, 0x5E, 0xA1,
+	0xFF, 0x00, 0xA0, 0xF9, 0x35, 0xF4, 0xF7, 0xFC, 0x13, 0x1F, 0xF6, 0x6B, 0xF8, 0xD5, 0xAB, 0xFE,
+	0xDB, 0x9E, 0x01, 0xB8, 0xF8, 0x85, 0xF0, 0xAB, 0xC5, 0x9A, 0x6E, 0x93, 0xA6, 0x6A, 0x92, 0x6A,
+	0x57, 0x57, 0x9A, 0xB7, 0x87, 0x6E, 0xAD, 0xE0, 0x8D, 0xAD, 0x6D, 0xE6, 0x9A, 0x2F, 0xDE, 0x49,
+	0x1A, 0xAF, 0xCD, 0x32, 0x44, 0xBF, 0x7B, 0xF8, 0xBF, 0x8A, 0xBB, 0xB8, 0x7B, 0x80, 0x73, 0x6A,
+	0x3C, 0x45, 0x85, 0xAB, 0x3A, 0x53, 0x50, 0x8C, 0xE2, 0xDB, 0x6B, 0xB3, 0xBE, 0xE6, 0x38, 0xCC,
+	0xD3, 0x0F, 0xF5, 0x39, 0xF2, 0xC9, 0x5E, 0xCF, 0xF2, 0x3F, 0x6E, 0x28, 0xA2, 0x8A, 0xFE, 0xB6,
+	0x3F, 0x2F, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x23, 0xA2,
+	0x8A, 0x28, 0x01, 0xFB, 0x17, 0xFB, 0xA3, 0xF2, 0xA4, 0xF2, 0xE3, 0xFF, 0x00, 0x9E, 0x6B, 0xF9,
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+	0xFF, 0x00, 0xDF, 0x34, 0x51, 0x40, 0x07, 0x95, 0x17, 0xFC, 0xF2, 0x5F, 0xFB, 0xE6, 0x9A, 0x91,
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+	0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60,
+	0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x22, 0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D,
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+	0x07, 0x09, 0x08, 0x06, 0x07, 0x09, 0x07, 0x06, 0x06, 0x08, 0x0B, 0x08, 0x09, 0x0A, 0x0A, 0x0A,
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+	0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
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+	0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04,
+	0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81,
+	0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82,
+	0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36,
+	0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
+	0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76,
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+	0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3,
+	0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA,
+	0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
+	0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00,
+	0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00,
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+	0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18,
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+	0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2,
+	0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9,
+	0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7,
+	0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5,
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+	0xCB, 0x19, 0x5A, 0xC2, 0x70, 0x55, 0xB3, 0xC5, 0x32, 0x11, 0xB6, 0x2F, 0x90, 0xFC, 0xB5, 0x23,
+	0x2E, 0x2A, 0x35, 0x54, 0x8C, 0x6C, 0x4A, 0x56, 0x43, 0x6A, 0x3B, 0xB2, 0x4F, 0xDE, 0x51, 0xFB,
+	0xCA, 0x6D, 0x14, 0x0B, 0xDD, 0xEE, 0x3B, 0xF7, 0x94, 0xD9, 0x59, 0x95, 0x79, 0xA2, 0x83, 0xD3,
+	0x9A, 0x03, 0x7D, 0x98, 0xD5, 0x8D, 0x05, 0x1F, 0x2E, 0xEF, 0xDD, 0xA5, 0x49, 0xB3, 0x6F, 0xDD,
+	0xA8, 0xC7, 0xCB, 0x37, 0xFB, 0x34, 0x73, 0x04, 0xA5, 0x2D, 0x07, 0x10, 0xDB, 0x83, 0xD3, 0x5A,
+	0x34, 0x2D, 0xCD, 0x48, 0x4E, 0x3F, 0x8E, 0xA3, 0xF9, 0x8A, 0x96, 0xA9, 0x8A, 0xE6, 0xEA, 0x39,
+	0x47, 0x9A, 0x23, 0xB7, 0x6C, 0x18, 0xA6, 0x97, 0xDA, 0x57, 0x6A, 0x53, 0x94, 0xEE, 0x5D, 0xED,
+	0xF7, 0xA8, 0xCB, 0x3E, 0xDC, 0x1A, 0x2F, 0xCB, 0xA2, 0xD4, 0x71, 0xF7, 0x5D, 0x9F, 0xDC, 0x2E,
+	0x0A, 0x1A, 0x36, 0xEE, 0x19, 0x6A, 0x46, 0x4D, 0xDD, 0x1A, 0x80, 0xD8, 0x5D, 0x94, 0x6B, 0x25,
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+	0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2,
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+	0x8A, 0x67, 0x6E, 0x69, 0xEC, 0x70, 0xB9, 0xA8, 0x8C, 0xEA, 0x17, 0x24, 0x60, 0x77, 0xF6, 0xA0,
+	0x4F, 0xDD, 0xD4, 0x73, 0x2E, 0xE5, 0xDC, 0x7E, 0x6F, 0xAD, 0x34, 0x36, 0xD0, 0x14, 0x7F, 0xE3,
+	0xBD, 0xFD, 0xF1, 0x5F, 0x3D, 0xFE, 0xD0, 0xBF, 0xF0, 0x51, 0x5F, 0x84, 0xFF, 0x00, 0x06, 0xF5,
+	0x0B, 0xCF, 0x08, 0xF8, 0x56, 0xDA, 0x6F, 0x12, 0x6B, 0xD6, 0x93, 0x34, 0x57, 0x16, 0xB6, 0xB2,
+	0x79, 0x56, 0xF6, 0xF2, 0x29, 0x5D, 0xC9, 0x24, 0xE4, 0x11, 0xB8, 0x02, 0xDC, 0x46, 0xB2, 0x10,
+	0xC8, 0xCA, 0xFB, 0x08, 0xAF, 0x96, 0xFC, 0x67, 0xFF, 0x00, 0x05, 0x23, 0xFD, 0xA8, 0x3C, 0x5A,
+	0x90, 0x47, 0xA7, 0x6B, 0x9A, 0x5E, 0x82, 0xB0, 0xEE, 0x12, 0x2E, 0x8F, 0xA4, 0x83, 0xE7, 0x67,
+	0x6E, 0x37, 0x7D, 0xA0, 0xCA, 0x46, 0x30, 0x71, 0xB7, 0x6F, 0xDE, 0xE7, 0x3C, 0x63, 0xE8, 0xF2,
+	0xDE, 0x15, 0xCE, 0x33, 0x1A, 0x6A, 0x70, 0x87, 0x2C, 0x5F, 0x56, 0xEC, 0x7E, 0x69, 0xC4, 0x7E,
+	0x2D, 0x70, 0x7F, 0x0E, 0xD5, 0x95, 0x0A, 0xB5, 0x7D, 0xA5, 0x48, 0xEF, 0x18, 0x6B, 0x67, 0xD9,
+	0xBD, 0x8F, 0xD2, 0x86, 0x96, 0x35, 0x6F, 0x98, 0xF4, 0xEB, 0x55, 0x8E, 0xAB, 0x63, 0xBB, 0x63,
+	0x6A, 0x11, 0x8D, 0xBD, 0x41, 0x61, 0x5F, 0x92, 0x8D, 0xFB, 0x40, 0x7C, 0x7A, 0x61, 0x83, 0xF1,
+	0xBF, 0xC6, 0x1F, 0xF8, 0x52, 0xDD, 0x7F, 0xF1, 0xCE, 0x7F, 0x1A, 0xE4, 0x47, 0x07, 0x81, 0x8F,
+	0x4C, 0x76, 0xF6, 0xAF, 0xA3, 0xA5, 0xE1, 0xEE, 0x2D, 0xFC, 0x75, 0xA2, 0xBD, 0x13, 0x3F, 0x38,
+	0xC4, 0xFD, 0x21, 0xB2, 0xDB, 0xAF, 0x63, 0x82, 0x93, 0xEF, 0x79, 0x23, 0xF5, 0xCB, 0x5D, 0xF8,
+	0xFD, 0xF0, 0x3B, 0xC3, 0x3A, 0xBC, 0xDA, 0x07, 0x89, 0xBE, 0x2F, 0x78, 0x6F, 0x4E, 0xBE, 0xB7,
+	0xDA, 0x2E, 0x2C, 0xEF, 0xB5, 0xAB, 0x78, 0x66, 0x8F, 0x2A, 0x18, 0x6E, 0x56, 0x60, 0xC3, 0x2A,
+	0x41, 0x1C, 0x74, 0x20, 0xF4, 0x35, 0x54, 0xFE, 0xD3, 0xBF, 0xB3, 0x81, 0xE3, 0xFE, 0x17, 0xC7,
+	0x84, 0xBF, 0x1F, 0x11, 0x5B, 0x7F, 0xF1, 0x75, 0xF9, 0x2E, 0x38, 0x18, 0x14, 0x57, 0x64, 0x7C,
+	0x38, 0xC2, 0xCB, 0xE2, 0xAE, 0xEF, 0xE4, 0x8F, 0x12, 0xA7, 0xD2, 0x2B, 0x34, 0xE6, 0xFD, 0xDE,
+	0x0A, 0x16, 0xE9, 0xEF, 0x3B, 0xDB, 0xCC, 0xFD, 0x4C, 0xF1, 0x7F, 0xED, 0xBF, 0xFB, 0x2E, 0xF8,
+	0x25, 0xAD, 0xD7, 0x51, 0xF8, 0xBF, 0xA5, 0x5D, 0x7D, 0xA4, 0x31, 0x8F, 0xFB, 0x1E, 0x46, 0xBE,
+	0x03, 0x18, 0xCE, 0xE3, 0x6E, 0xAF, 0xB3, 0xEF, 0x0C, 0x6E, 0xC6, 0xEE, 0x71, 0x9C, 0x1C, 0x61,
+	0x8F, 0xF8, 0x28, 0xBF, 0xEC, 0x9A, 0x06, 0x07, 0xC4, 0x89, 0xBF, 0xF0, 0x4B, 0x79, 0xFF, 0x00,
+	0xC6, 0x6B, 0xF3, 0x3C, 0x93, 0x9C, 0xFE, 0x34, 0x57, 0x44, 0x3C, 0x3D, 0xCB, 0xE3, 0x1B, 0x4A,
+	0xA4, 0xBF, 0x03, 0xCF, 0xAD, 0xF4, 0x84, 0xE2, 0x29, 0x54, 0xBC, 0x30, 0xF4, 0xE2, 0xBB, 0x6A,
+	0xFF, 0x00, 0x13, 0xF4, 0xC7, 0xFE, 0x1E, 0x31, 0xFB, 0x26, 0xFF, 0x00, 0xD1, 0x48, 0x97, 0xFF,
+	0x00, 0x04, 0xB7, 0x9F, 0xFC, 0x66, 0x8F, 0xF8, 0x78, 0xC7, 0xEC, 0x9B, 0xFF, 0x00, 0x45, 0x22,
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+	0x96, 0x49, 0x57, 0x8E, 0xA7, 0x9A, 0x42, 0x52, 0xF6, 0x4E, 0x9B, 0x8A, 0xD3, 0x5B, 0xB8, 0x72,
+	0xED, 0xEA, 0x33, 0xF6, 0x7C, 0x00, 0x7C, 0x79, 0xF0, 0x3A, 0xA8, 0xC7, 0xFC, 0x55, 0xFA, 0x6F,
+	0xFE, 0x95, 0xC7, 0x5E, 0xBB, 0xF1, 0xBC, 0x05, 0xFF, 0x00, 0x82, 0x95, 0xDA, 0x8C, 0xFF, 0x00,
+	0xCC, 0xE5, 0xA0, 0xFF, 0x00, 0xE8, 0x36, 0x75, 0xE0, 0x9E, 0x10, 0xF1, 0x36, 0xA1, 0xE0, 0xAF,
+	0x16, 0x69, 0x7E, 0x32, 0xD2, 0x63, 0x89, 0xAE, 0xB4, 0x9D, 0x46, 0x0B, 0xDB, 0x55, 0x9D, 0x49,
+	0x46, 0x92, 0x29, 0x03, 0xA8, 0x60, 0x08, 0x24, 0x65, 0x46, 0x70, 0x41, 0xC7, 0x71, 0x5B, 0xBE,
+	0x37, 0xF8, 0xD5, 0xE3, 0x5F, 0x1C, 0x7C, 0x5D, 0x7F, 0x8D, 0xD7, 0x6D, 0x6B, 0x67, 0xAE, 0x1B,
+	0xCB, 0x6B, 0xB8, 0x9A, 0xCA, 0xDF, 0xF7, 0x51, 0x4D, 0x02, 0xC6, 0x23, 0x65, 0x49, 0x0B, 0xE7,
+	0x1E, 0x5A, 0x92, 0x18, 0x90, 0x4E, 0x7B, 0x71, 0x5E, 0x96, 0x3B, 0x2D, 0xC4, 0x56, 0xCC, 0x3D,
+	0xAC, 0x12, 0xE5, 0xF6, 0x72, 0x8E, 0xFD, 0x5E, 0xC7, 0xCF, 0x64, 0x5C, 0x45, 0x96, 0xE0, 0x72,
+	0x3F, 0xAA, 0x55, 0x6F, 0x9F, 0xEB, 0x10, 0xA9, 0xB5, 0xD7, 0x2C, 0x77, 0xF9, 0xF9, 0x1E, 0xD1,
+	0xFF, 0x00, 0x05, 0x52, 0x4F, 0xF8, 0xC8, 0x9D, 0x2C, 0x32, 0xF5, 0xF0, 0x7D, 0xB9, 0xE3, 0x9C,
+	0x7F, 0xA4, 0xDC, 0x8E, 0x9F, 0xA6, 0x78, 0xFD, 0x38, 0xEA, 0x3F, 0x64, 0xAF, 0x05, 0xEB, 0x5F,
+	0x04, 0x3F, 0x65, 0x6F, 0x88, 0x7F, 0x19, 0xBC, 0x6D, 0x07, 0xD8, 0x53, 0x5E, 0xD2, 0x08, 0xD1,
+	0xEC, 0x75, 0x08, 0xC4, 0x7E, 0x7A, 0x47, 0x14, 0xA2, 0x17, 0x04, 0x9C, 0x91, 0x2C, 0x93, 0x94,
+	0x50, 0x54, 0x13, 0x80, 0xC3, 0x70, 0x91, 0x4D, 0x72, 0xA9, 0xFF, 0x00, 0x05, 0x45, 0xF8, 0xE5,
+	0x24, 0x4C, 0xBA, 0x87, 0x82, 0xFC, 0x27, 0x34, 0x81, 0x71, 0x03, 0x8B, 0x39, 0xD7, 0x6F, 0xFB,
+	0xC0, 0xCE, 0x73, 0xF8, 0x11, 0x5E, 0x63, 0xF1, 0xEB, 0xF6, 0xA5, 0xF8, 0xB1, 0xFB, 0x45, 0x49,
+	0x67, 0x0F, 0x8E, 0xEF, 0xAD, 0x60, 0xB1, 0xB1, 0xF9, 0xAD, 0xB4, 0xAD, 0x2E, 0x26, 0x8A, 0xDC,
+	0x49, 0x8C, 0x79, 0xA5, 0x59, 0x98, 0xB3, 0xE3, 0x80, 0x49, 0x3B, 0x41, 0x6D, 0xA0, 0x6E, 0x6C,
+	0xF8, 0x94, 0x72, 0x9C, 0xF2, 0xAE, 0x06, 0x96, 0x5F, 0x56, 0x11, 0x84, 0x22, 0xD5, 0xE5, 0x7B,
+	0xB6, 0x93, 0xBE, 0x88, 0xFB, 0x6C, 0x7F, 0x15, 0x70, 0x5E, 0x17, 0x3D, 0xC5, 0xE7, 0xD8, 0x4A,
+	0xD3, 0xA9, 0x5E, 0xAC, 0x5A, 0x8D, 0x37, 0x1E, 0x55, 0x17, 0x25, 0x6B, 0xB7, 0xE4, 0x7D, 0x13,
+	0xFB, 0x13, 0x6B, 0xDE, 0x2F, 0xF1, 0x37, 0xEC, 0x71, 0xE2, 0xEF, 0x07, 0xFC, 0x24, 0xD6, 0xAD,
+	0xB4, 0xFF, 0x00, 0x17, 0x69, 0x7A, 0x94, 0xB3, 0x69, 0xE2, 0x38, 0xA1, 0x96, 0x49, 0x72, 0xB1,
+	0xCA, 0x81, 0x96, 0x5F, 0x90, 0x79, 0xBB, 0x64, 0x84, 0x33, 0x70, 0xA0, 0x67, 0xAA, 0x57, 0x8A,
+	0xDC, 0x7E, 0xD6, 0x9F, 0xB6, 0x3E, 0x95, 0xE2, 0x31, 0xE1, 0x6B, 0xAF, 0x15, 0xEA, 0x36, 0xBA,
+	0xBF, 0xDA, 0x56, 0x15, 0xD3, 0x66, 0xF0, 0xCD, 0xB2, 0xDC, 0x79, 0x8D, 0x8D, 0xA9, 0xE5, 0x9B,
+	0x7D, 0xDB, 0x8E, 0x46, 0x17, 0x19, 0x24, 0x80, 0x33, 0x9E, 0x7C, 0xFB, 0xE1, 0x57, 0xC5, 0x7F,
+	0x1B, 0x7C, 0x18, 0xF1, 0xAD, 0xAF, 0x8F, 0x3C, 0x07, 0xAA, 0xFD, 0x9A, 0xF6, 0xDF, 0xE5, 0x91,
+	0x58, 0x66, 0x3B, 0x98, 0x89, 0x05, 0xA1, 0x91, 0x78, 0xDC, 0x8C, 0x47, 0x23, 0x20, 0x82, 0x03,
+	0x29, 0x0C, 0x01, 0x1E, 0xDF, 0x37, 0xFC, 0x15, 0x0B, 0xE3, 0x8C, 0xD0, 0x29, 0xFF, 0x00, 0x84,
+	0x2F, 0xC2, 0x3F, 0x6A, 0x07, 0x2D, 0x30, 0xB1, 0xB8, 0xDA, 0x47, 0xB2, 0xF9, 0xF9, 0xCF, 0x4E,
+	0x73, 0x55, 0x5B, 0x25, 0xC6, 0x61, 0xB1, 0xD5, 0x2A, 0x52, 0xA3, 0x1A, 0xB0, 0xA8, 0xEE, 0xB9,
+	0x9D, 0x9A, 0x7D, 0xBD, 0x0E, 0x7C, 0x2F, 0x18, 0xE4, 0xD9, 0x9E, 0x4B, 0x86, 0xA5, 0x89, 0xC6,
+	0x54, 0xC3, 0x55, 0xA0, 0xB9, 0x5F, 0x24, 0x6F, 0x19, 0x2B, 0xDE, 0xFE, 0x4D, 0x19, 0xDF, 0x06,
+	0xBE, 0x25, 0x7C, 0x48, 0xBC, 0xFD, 0xB6, 0xBC, 0x21, 0xAD, 0xFE, 0xD1, 0x3A, 0x84, 0xB1, 0xEA,
+	0xF0, 0xB2, 0xD9, 0x15, 0xBC, 0xB2, 0x8E, 0x19, 0x22, 0xFB, 0x45, 0xAC, 0xBE, 0x44, 0x6C, 0x91,
+	0xA2, 0xE1, 0x8B, 0x5C, 0x28, 0xF9, 0x94, 0x11, 0xBC, 0xEE, 0x23, 0x69, 0x03, 0x0F, 0xF6, 0xEC,
+	0xF8, 0x69, 0xE2, 0xAF, 0x01, 0xFE, 0xD0, 0xFA, 0xD6, 0xAF, 0xAC, 0xD8, 0x5D, 0x9D, 0x3F, 0x5E,
+	0xB9, 0x37, 0xBA, 0x3E, 0xA1, 0x2A, 0xEE, 0x8E, 0xE1, 0x59, 0x54, 0xC8, 0xAA, 0xC3, 0x80, 0x63,
+	0x62, 0x57, 0x69, 0x21, 0x82, 0x85, 0x38, 0x01, 0x97, 0x3E, 0x67, 0xF1, 0x17, 0xC7, 0xFE, 0x25,
+	0xF8, 0xA5, 0xE3, 0x5D, 0x43, 0xC7, 0xDE, 0x2F, 0xB9, 0x8E, 0x6D, 0x43, 0x52, 0x94, 0x3C, 0xED,
+	0x14, 0x21, 0x11, 0x76, 0xA8, 0x45, 0x55, 0x51, 0xD8, 0x20, 0x0B, 0xCE, 0x49, 0x03, 0x92, 0x4E,
+	0x49, 0xF5, 0xCF, 0x04, 0x7F, 0xC1, 0x44, 0xBF, 0x68, 0x8F, 0x07, 0x78, 0x72, 0x1F, 0x0D, 0xDE,
+	0x4F, 0xA3, 0xEB, 0xCB, 0x6F, 0x81, 0x0D, 0xE6, 0xBD, 0x67, 0x24, 0xB7, 0x01, 0x02, 0x85, 0x08,
+	0x5D, 0x24, 0x4D, 0xFD, 0x33, 0xB9, 0xF7, 0x39, 0x24, 0x96, 0x63, 0x5D, 0xAF, 0x2D, 0xCD, 0x30,
+	0x98, 0xAA, 0x78, 0xAC, 0x25, 0x38, 0xDF, 0x93, 0x96, 0x51, 0xBD, 0x92, 0xEB, 0xA3, 0x3C, 0x9A,
+	0x3C, 0x45, 0xC3, 0x79, 0xA6, 0x59, 0x88, 0xCA, 0xF3, 0x3A, 0xD5, 0x14, 0x7D, 0xA7, 0xB4, 0x85,
+	0x5B, 0x73, 0x49, 0xDF, 0x47, 0xCC, 0xBB, 0xB4, 0x74, 0x9E, 0x0C, 0x0C, 0xFF, 0x00, 0xF0, 0x4C,
+	0x3F, 0x16, 0x67, 0xB7, 0x89, 0xE2, 0xDC, 0xA7, 0xB1, 0xFB, 0x55, 0xA1, 0xFF, 0x00, 0xEB, 0xD7,
+	0xCC, 0xB5, 0xED, 0x5F, 0x17, 0xBF, 0x6E, 0xDF, 0x8B, 0xFF, 0x00, 0x1A, 0x7E, 0x1E, 0x5E, 0xFC,
+	0x34, 0xF1, 0x4E, 0x81, 0xE1, 0xCB, 0x7D, 0x3E, 0xF9, 0xA2, 0x33, 0x49, 0xA7, 0xD8, 0xCC, 0x92,
+	0x8F, 0x2E, 0x54, 0x90, 0x60, 0xB4, 0xCC, 0x3E, 0xF2, 0x0C, 0xF0, 0x78, 0xFC, 0xEB, 0xC5, 0x6B,
+	0xBB, 0x21, 0xC2, 0x63, 0x30, 0xDE, 0xDA, 0x78, 0x98, 0xA8, 0xCA, 0x72, 0xE6, 0xB2, 0x77, 0xE8,
+	0x78, 0x7C, 0x71, 0x9A, 0xE4, 0xF9, 0x87, 0xD5, 0x28, 0xE5, 0xB5, 0x1C, 0xE1, 0x46, 0x9A, 0x85,
+	0xDA, 0xB3, 0xBA, 0x7D, 0x82, 0x8A, 0x28, 0xAF, 0xA0, 0x3E, 0x0C, 0x2B, 0xE9, 0x6F, 0xF8, 0x25,
+	0x6F, 0xFC, 0x9C, 0x5E, 0xA9, 0xFF, 0x00, 0x62, 0x7D, 0xD7, 0xFE, 0x94, 0x5B, 0x57, 0xCD, 0x35,
+	0xF4, 0xB7, 0xFC, 0x12, 0xB7, 0xFE, 0x4E, 0x2F, 0x54, 0xFF, 0x00, 0xB1, 0x3E, 0xEB, 0xFF, 0x00,
+	0x4A, 0x2D, 0xAB, 0xC0, 0xE2, 0x8F, 0xF9, 0x10, 0xD7, 0xF4, 0xFD, 0x51, 0xF7, 0xDE, 0x17, 0xFF,
+	0x00, 0xC9, 0x79, 0x81, 0xFF, 0x00, 0x1F, 0xE8, 0xCF, 0xD0, 0xEB, 0x7F, 0xB9, 0x52, 0x54, 0x76,
+	0xFF, 0x00, 0x72, 0xA4, 0xAF, 0xC0, 0xBA, 0xB3, 0xFD, 0x00, 0x87, 0xC2, 0x82, 0x8A, 0x28, 0xA0,
+	0xA0, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x33, 0x40, 0x05, 0x14, 0x51, 0x9A, 0x00, 0x09, 0xC7, 0x34, 0x02, 0x71, 0x41,
+	0x3C, 0x75, 0xA8, 0x5E, 0xE6, 0x38, 0x46, 0xF9, 0x25, 0x03, 0xD4, 0x92, 0x06, 0x3F, 0x5A, 0x40,
+	0x3E, 0x42, 0x4A, 0xE0, 0x91, 0xF8, 0x52, 0x07, 0x3B, 0x30, 0x3B, 0x57, 0x2B, 0xF1, 0x2B, 0xE3,
+	0x57, 0xC3, 0x1F, 0x85, 0x1E, 0x1F, 0x93, 0xC4, 0xFE, 0x3E, 0xF1, 0x7D, 0x8E, 0x9F, 0x67, 0x1F,
+	0xDE, 0x92, 0x49, 0x86, 0x7D, 0x7A, 0x57, 0xCB, 0x9F, 0x1B, 0xFF, 0x00, 0xE0, 0xBA, 0xBF, 0xF0,
+	0x4F, 0xFF, 0x00, 0x83, 0xBE, 0x1E, 0xBA, 0xD4, 0x63, 0xF8, 0xB7, 0x0E, 0xA1, 0x7D, 0x0F, 0xCB,
+	0x1D, 0x94, 0x70, 0xB7, 0xCC, 0xDE, 0x99, 0xFA, 0xD7, 0x5E, 0x1F, 0x2F, 0xC7, 0x62, 0x6A, 0x28,
+	0xD3, 0x83, 0x77, 0xF2, 0x26, 0x55, 0x22, 0xBA, 0x9F, 0x66, 0x19, 0x18, 0x0F, 0x9D, 0x85, 0x0C,
+	0x48, 0x1F, 0x77, 0xAF, 0x4D, 0xB5, 0xF8, 0xF1, 0xE3, 0x2F, 0xF8, 0x3A, 0xE7, 0xC1, 0x1A, 0x5D,
+	0xDF, 0x95, 0xE1, 0x0F, 0x82, 0x76, 0xBA, 0x8C, 0x0C, 0xCC, 0xAB, 0x70, 0xD7, 0xEC, 0x84, 0x8E,
+	0xC7, 0x15, 0xF3, 0xD7, 0x8D, 0xFF, 0x00, 0xE0, 0xE8, 0xEF, 0xDA, 0x6B, 0x5A, 0xB9, 0xBA, 0xB4,
+	0xF0, 0xEF, 0xC3, 0x18, 0xF4, 0xD8, 0x64, 0x91, 0x8D, 0xAD, 0xC2, 0x5F, 0x67, 0x6A, 0xF6, 0x03,
+	0x26, 0xBE, 0x9A, 0x87, 0x00, 0x71, 0x26, 0x21, 0x73, 0x7B, 0x1E, 0x54, 0x73, 0xCB, 0x15, 0x46,
+	0x3A, 0x1F, 0xD0, 0x6E, 0x7F, 0x84, 0x83, 0xF2, 0xFF, 0x00, 0x16, 0xDA, 0x14, 0xEE, 0x19, 0x1F,
+	0x87, 0x3D, 0x6B, 0xF9, 0xA5, 0xF1, 0x27, 0xFC, 0x1C, 0x41, 0xFB, 0x79, 0xEB, 0x53, 0x47, 0x36,
+	0x9F, 0xE2, 0xEB, 0xCD, 0x3F, 0xE5, 0x61, 0xB6, 0x39, 0x83, 0x7E, 0x3D, 0x3B, 0x57, 0x25, 0x2F,
+	0xFC, 0x17, 0x87, 0xFE, 0x0A, 0x4F, 0x2B, 0x6E, 0x8F, 0xE3, 0xE6, 0xB0, 0xB9, 0x24, 0xA8, 0xDE,
+	0xBC, 0x57, 0xA5, 0x4F, 0xC3, 0x3C, 0xF2, 0xA6, 0xF2, 0x8A, 0xF5, 0x0F, 0xAD, 0xD3, 0x3F, 0xA8,
+	0x7C, 0xF3, 0x8A, 0x30, 0x6B, 0xF9, 0x73, 0xFF, 0x00, 0x87, 0xEF, 0xFF, 0x00, 0xC1, 0x4A, 0xF1,
+	0x81, 0xFB, 0x40, 0xEB, 0x1B, 0xBF, 0xDE, 0x14, 0xBF, 0xF0, 0xFD, 0xCF, 0xF8, 0x29, 0x56, 0x39,
+	0xFD, 0xA0, 0xB5, 0x6F, 0xFB, 0xE9, 0x6A, 0xBF, 0xE2, 0x17, 0xE7, 0x0B, 0xED, 0xC7, 0xEF, 0x60,
+	0xB1, 0x94, 0x9E, 0x87, 0xF5, 0x1B, 0xB9, 0xBD, 0x68, 0xDC, 0xDE, 0xB5, 0xFC, 0xB9, 0x9F, 0xF8,
+	0x2E, 0xE7, 0xFC, 0x14, 0xA7, 0xB7, 0xED, 0x05, 0xAC, 0x7F, 0xDF, 0x4B, 0x49, 0xFF, 0x00, 0x0F,
+	0xDD, 0xFF, 0x00, 0x82, 0x94, 0xF4, 0x3F, 0xB4, 0x1E, 0xAF, 0xF9, 0xAD, 0x0B, 0xC2, 0xFC, 0xE1,
+	0xFF, 0x00, 0xCB, 0xC8, 0xFD, 0xEC, 0x3E, 0xB7, 0x46, 0xF6, 0x3F, 0xA8, 0xDD, 0xCD, 0xEB, 0x46,
+	0xE6, 0xF5, 0xAF, 0xE5, 0xCB, 0xFE, 0x1F, 0xB9, 0xFF, 0x00, 0x05, 0x29, 0xEF, 0xFB, 0x41, 0xEA,
+	0xFF, 0x00, 0x9A, 0xD0, 0x7F, 0xE0, 0xBB, 0x9F, 0xF0, 0x52, 0xA5, 0xE0, 0xFE, 0xD0, 0x5A, 0xC7,
+	0xE9, 0x4F, 0xFE, 0x21, 0x7E, 0x75, 0xFC, 0xF1, 0xFB, 0xD8, 0x7D, 0x6E, 0x89, 0xFD, 0x46, 0xEE,
+	0x6F, 0x5A, 0x4D, 0xEC, 0x38, 0x2D, 0x5F, 0xCB, 0x97, 0xFC, 0x3F, 0x77, 0xFE, 0x0A, 0x52, 0x1F,
+	0x6F, 0xFC, 0x34, 0x1E, 0xAF, 0xD3, 0xD4, 0x52, 0xFF, 0x00, 0xC3, 0xF7, 0x3F, 0xE0, 0xA5, 0x79,
+	0xE7, 0xF6, 0x83, 0xD5, 0xBF, 0xEF, 0xA5, 0xA5, 0xFF, 0x00, 0x10, 0xC3, 0x38, 0xEB, 0x38, 0xFD,
+	0xEC, 0x3E, 0xB7, 0x48, 0xFE, 0xA3, 0x77, 0x37, 0xAD, 0x1B, 0x9B, 0xD6, 0xBF, 0x97, 0x3F, 0xF8,
+	0x7E, 0xEF, 0xFC, 0x14, 0xAB, 0xFE, 0x8E, 0x0F, 0x57, 0x1F, 0xF0, 0x25, 0xA4, 0xFF, 0x00, 0x87,
+	0xEE, 0x7F, 0xC1, 0x4A, 0x3B, 0x7E, 0xD0, 0xBA, 0xB7, 0xFD, 0xF4, 0xB4, 0xFF, 0x00, 0xE2, 0x18,
+	0x67, 0x3B, 0xF3, 0xC7, 0xEF, 0x60, 0xF1, 0x94, 0xF7, 0x3F, 0xA8, 0xDD, 0xCD, 0xEB, 0x46, 0xE6,
+	0xF5, 0xAF, 0xE5, 0xCB, 0xFE, 0x1F, 0xB9, 0xFF, 0x00, 0x05, 0x2A, 0x1D, 0x7F, 0x68, 0x3D, 0x5F,
+	0xFE, 0xFA, 0x5A, 0x5F, 0xF8, 0x7E, 0xE7, 0xFC, 0x14, 0xA3, 0xFE, 0x8E, 0x0B, 0x58, 0xFF, 0x00,
+	0xBE, 0x96, 0x9F, 0xFC, 0x42, 0xFC, 0xE2, 0xFF, 0x00, 0xC4, 0x8F, 0xDE, 0xC3, 0xEB, 0x74, 0xF7,
+	0x3F, 0xA8, 0xBD, 0xCD, 0xEB, 0x4B, 0xB9, 0xBD, 0x6B, 0xF9, 0x72, 0x1F, 0xF0, 0x5D, 0xCF, 0xF8,
+	0x29, 0x57, 0xFD, 0x1C, 0x16, 0xAF, 0xFF, 0x00, 0x7D, 0x2D, 0x27, 0xFC, 0x3F, 0x77, 0xFE, 0x0A,
+	0x53, 0x8C, 0x8F, 0xDA, 0x0F, 0x57, 0xFC, 0xD6, 0x8F, 0xF8, 0x85, 0xF9, 0xC7, 0xF3, 0xC7, 0xEF,
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+	0xBB, 0xFF, 0x00, 0x05, 0x28, 0xEF, 0xFB, 0x41, 0xEB, 0x1F, 0xA5, 0x2F, 0xFC, 0x3F, 0x73, 0xFE,
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+	0xCB, 0xAD, 0xBD, 0x9D, 0xC7, 0xCD, 0xF6, 0x66, 0x1B, 0x59, 0x4E, 0x0F, 0xB9, 0xAF, 0x53, 0x25,
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+	0xF9, 0xE3, 0xFE, 0x0B, 0x85, 0xFF, 0x00, 0x05, 0xB4, 0xD7, 0x3E, 0x3F, 0xF8, 0x9A, 0xEF, 0xF6,
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+	0xA4, 0x66, 0xCC, 0x8C, 0xCD, 0x9D, 0xC6, 0x94, 0x03, 0x33, 0x34, 0xB2, 0xCB, 0x9D, 0xDF, 0x79,
+	0x8F, 0x56, 0xE7, 0x34, 0x03, 0x24, 0x8D, 0xF6, 0x8D, 0xB8, 0x54, 0xF5, 0xAF, 0xE9, 0x7C, 0x9F,
+	0x29, 0xC1, 0xE4, 0xB8, 0x78, 0xD0, 0xC3, 0xC2, 0xC9, 0x2B, 0x3E, 0xEF, 0xBB, 0x3C, 0x99, 0xD6,
+	0x95, 0x47, 0xA8, 0x16, 0x66, 0xF9, 0xC9, 0xF9, 0xBA, 0x71, 0xDA, 0x90, 0x00, 0x1B, 0x78, 0x1C,
+	0xFA, 0xD0, 0x48, 0x3F, 0x36, 0x73, 0x9F, 0x4A, 0x3E, 0xB5, 0xE9, 0xB8, 0xC2, 0x8B, 0xBB, 0x7A,
+	0x33, 0x19, 0x79, 0x06, 0x24, 0x39, 0x28, 0x37, 0x13, 0xDE, 0xBD, 0xA3, 0xF6, 0x21, 0xFD, 0x88,
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+	0xED, 0x55, 0xCE, 0xD4, 0x5E, 0xA6, 0xBC, 0x5C, 0x64, 0x9D, 0xBB, 0xF6, 0xA9, 0xE0, 0xD7, 0xDB,
+	0xDF, 0xF0, 0x42, 0x0F, 0xDA, 0x8B, 0xE1, 0x77, 0xEC, 0x81, 0xFB, 0x54, 0xFF, 0x00, 0xC2, 0xD4,
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+	0x76, 0x55, 0x19, 0x4D, 0x55, 0x57, 0xD8, 0xE8, 0xBF, 0x68, 0xEF, 0xF8, 0x37, 0xC3, 0xF6, 0x8B,
+	0xFD, 0x9C, 0x7E, 0x11, 0xEA, 0x9F, 0x17, 0xFC, 0x43, 0xE2, 0xD9, 0x26, 0xD3, 0x74, 0x5B, 0x6F,
+	0xB4, 0x5F, 0x36, 0xC1, 0xF2, 0x26, 0x6B, 0xE9, 0x3F, 0xF8, 0x37, 0xCF, 0xF6, 0x18, 0xFD, 0x85,
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+	0xA3, 0xF0, 0xFD, 0xCE, 0x47, 0xD9, 0xF6, 0x10, 0x45, 0xC1, 0x39, 0xE4, 0x77, 0xFA, 0xD7, 0xBF,
+	0x7F, 0xC1, 0x46, 0x3F, 0xE0, 0xAF, 0x9F, 0xB1, 0x97, 0xC5, 0xDF, 0xD9, 0x17, 0xC6, 0x5F, 0x08,
+	0xFC, 0x19, 0xE3, 0x45, 0xBE, 0xBF, 0xD7, 0x34, 0xCF, 0x22, 0xDD, 0x23, 0xB8, 0x5E, 0x1B, 0x70,
+	0x20, 0x9F, 0xC8, 0x57, 0xE2, 0x17, 0xEC, 0xAD, 0xFB, 0x59, 0x7C, 0x52, 0xFD, 0x8D, 0x3E, 0x35,
+	0xDB, 0xFC, 0x51, 0xF8, 0x4B, 0xE2, 0x29, 0xAD, 0xC5, 0xBD, 0xEA, 0x9B, 0xAB, 0x58, 0xE5, 0x3E,
+	0x54, 0x91, 0x03, 0xB8, 0xA9, 0x5C, 0x80, 0x73, 0x8E, 0xF5, 0xF0, 0xD8, 0x59, 0xF1, 0x1F, 0x11,
+	0x70, 0xAD, 0x58, 0xE2, 0x2F, 0x4E, 0xAA, 0x7A, 0x35, 0xA3, 0x6B, 0xB1, 0xD9, 0x53, 0xD8, 0x51,
+	0xAC, 0x9A, 0x77, 0x4C, 0xFD, 0x94, 0xFF, 0x00, 0x82, 0xEB, 0x7F, 0xC1, 0x4F, 0x7F, 0x69, 0xEF,
+	0xD8, 0x66, 0xE3, 0x4B, 0xF8, 0x2D, 0xF0, 0x53, 0xC0, 0x93, 0xF8, 0x77, 0x4D, 0xD5, 0xB4, 0xF9,
+	0x63, 0xD3, 0xFC, 0x41, 0x0E, 0x1D, 0x1A, 0x35, 0x38, 0x21, 0x46, 0x0E, 0xD3, 0x83, 0x5E, 0x6F,
+	0xFF, 0x00, 0x06, 0xAD, 0x6A, 0xF7, 0x9E, 0x37, 0xF8, 0xB3, 0xF1, 0x67, 0xE2, 0x47, 0x8A, 0x6E,
+	0x3E, 0xD5, 0xAE, 0xEA, 0x9A, 0x6D, 0xBB, 0xEA, 0x37, 0xAE, 0x72, 0xCD, 0xFB, 0xEC, 0xF3, 0xE9,
+	0x5E, 0xBD, 0xE1, 0xAF, 0xDB, 0x2B, 0xF6, 0x16, 0xFF, 0x00, 0x82, 0xDE, 0xFC, 0x06, 0xFF, 0x00,
+	0x85, 0x35, 0xF1, 0x5E, 0x7B, 0x5F, 0x0F, 0xF8, 0xD1, 0x2C, 0xF6, 0x42, 0xDA, 0xA3, 0xA4, 0x2F,
+	0x24, 0xC0, 0x72, 0x61, 0xEA, 0x42, 0x93, 0xE9, 0x5F, 0x31, 0xFE, 0xC6, 0xBE, 0x28, 0xF8, 0xBF,
+	0xFF, 0x00, 0x04, 0x16, 0xFD, 0xAA, 0xB5, 0x8F, 0x0A, 0x7C, 0x77, 0xF8, 0x79, 0x7D, 0x73, 0xF0,
+	0xFF, 0x00, 0xC5, 0xD2, 0x47, 0x6D, 0x6F, 0xE2, 0x48, 0x6D, 0x71, 0x01, 0x40, 0xDB, 0xB7, 0x07,
+	0x6E, 0xB8, 0x15, 0xE3, 0x53, 0xA1, 0x45, 0xF0, 0x7D, 0x7C, 0xB5, 0x52, 0xE4, 0xC5, 0x5D, 0x5E,
+	0xFB, 0xCA, 0xCF, 0x74, 0xFA, 0x91, 0xED, 0x25, 0xF5, 0xDE, 0x69, 0x6B, 0x0E, 0x9E, 0x47, 0xD8,
+	0x9F, 0xF0, 0x59, 0xEF, 0xD9, 0xBF, 0xF6, 0x24, 0xF8, 0xF3, 0xF1, 0x37, 0x46, 0x5F, 0xDA, 0x93,
+	0xF6, 0xA4, 0x8F, 0xC0, 0xF7, 0x30, 0xE9, 0x6A, 0x2D, 0x74, 0xF9, 0xA1, 0x90, 0xF9, 0x8A, 0x0F,
+	0x0F, 0xF2, 0xF1, 0x5F, 0x12, 0x9F, 0xF8, 0x26, 0xFF, 0x00, 0xFC, 0x11, 0xC8, 0x21, 0x8E, 0x3F,
+	0xF8, 0x28, 0x4D, 0xA7, 0xCA, 0xAD, 0x85, 0xFB, 0x24, 0xBC, 0xF1, 0xD3, 0xAF, 0x7A, 0xFA, 0xB3,
+	0xFE, 0x0A, 0x09, 0xF0, 0x4B, 0xF6, 0x06, 0xFF, 0x00, 0x82, 0xC3, 0x68, 0x9A, 0x3F, 0xC4, 0x7D,
+	0x37, 0xF6, 0xAA, 0xF0, 0xFE, 0x83, 0x7D, 0xA7, 0xC3, 0x1C, 0x4B, 0xF6, 0xCD, 0x69, 0x62, 0x6F,
+	0x2C, 0x1D, 0xC5, 0x48, 0x19, 0xE7, 0xF4, 0xAF, 0x9B, 0xAD, 0xFF, 0x00, 0xE0, 0x83, 0xDF, 0xB1,
+	0xA1, 0x18, 0x5F, 0xDB, 0x9B, 0xC1, 0x61, 0x54, 0x75, 0x6F, 0x10, 0x8E, 0x78, 0xAF, 0x3F, 0x26,
+	0xC3, 0xE0, 0x30, 0xD8, 0x35, 0x1C, 0x45, 0x4A, 0xB0, 0x92, 0xF8, 0x92, 0x8E, 0x9F, 0x2D, 0x0E,
+	0x98, 0xD4, 0xA9, 0x27, 0x75, 0x6B, 0x1F, 0x37, 0xFE, 0xC8, 0x5F, 0x0F, 0x7E, 0x1A, 0xFC, 0x30,
+	0xFF, 0x00, 0x82, 0xB6, 0xF8, 0x17, 0xC2, 0x5F, 0x07, 0xFC, 0x5E, 0xBA, 0xF7, 0x87, 0xE3, 0xD7,
+	0xED, 0x7E, 0xCF, 0xA9, 0xAE, 0xE0, 0xB2, 0xFC, 0xDE, 0xFC, 0x8E, 0x2B, 0xF5, 0xC7, 0xFE, 0x0A,
+	0x13, 0xFF, 0x00, 0x05, 0x45, 0xF1, 0x27, 0xEC, 0x1B, 0xFF, 0x00, 0x05, 0x02, 0xF8, 0x77, 0xE0,
+	0xAF, 0x19, 0xB3, 0xB7, 0xC3, 0x7F, 0x11, 0x78, 0x76, 0x43, 0xAA, 0xB6, 0x40, 0x58, 0xEE, 0x8B,
+	0x94, 0x46, 0xF7, 0x23, 0xAD, 0x7E, 0x5E, 0x27, 0xC1, 0x5F, 0xD9, 0xD3, 0xFE, 0x09, 0xD1, 0xFF,
+	0x00, 0x05, 0x19, 0xF8, 0x6F, 0x63, 0xE0, 0xFF, 0x00, 0x8B, 0xB6, 0x1E, 0x28, 0x86, 0x1F, 0x10,
+	0xDA, 0xCD, 0xA8, 0x6A, 0xDA, 0x7E, 0xA1, 0xE7, 0x5B, 0xC3, 0x19, 0xEE, 0x4F, 0x60, 0x3B, 0xD7,
+	0x77, 0xFF, 0x00, 0x07, 0x2D, 0x7E, 0xD0, 0xDF, 0x09, 0xBF, 0x68, 0x4F, 0x89, 0xFE, 0x0F, 0xD4,
+	0x3E, 0x15, 0x78, 0xB6, 0xD7, 0x52, 0x5D, 0x3F, 0x47, 0x78, 0xEE, 0x24, 0xB6, 0x94, 0x3E, 0x18,
+	0xBB, 0x73, 0xC7, 0x42, 0x33, 0x5F, 0x5B, 0x9B, 0x64, 0xB8, 0x7E, 0x23, 0xCE, 0xB0, 0x51, 0xE4,
+	0x72, 0xA3, 0xEC, 0xA5, 0x66, 0xF4, 0xB3, 0xB2, 0xB5, 0xFB, 0x33, 0x38, 0xD6, 0xF6, 0x6A, 0x51,
+	0x96, 0xF7, 0x3F, 0x42, 0xBF, 0xE0, 0xA9, 0x5F, 0xF0, 0x4D, 0x1F, 0x83, 0xDF, 0xF0, 0x55, 0x1F,
+	0x80, 0xF6, 0xBF, 0x18, 0xBE, 0x0B, 0x5E, 0xD9, 0x4B, 0xE2, 0x2B, 0x7B, 0x37, 0xB9, 0xD0, 0xF5,
+	0x4B, 0x38, 0xD4, 0xFD, 0xB3, 0x38, 0x21, 0x49, 0xF5, 0x15, 0xF3, 0x7F, 0xFC, 0x11, 0x93, 0xE1,
+	0x9F, 0x8C, 0xFE, 0x0F, 0xFF, 0x00, 0xC1, 0x38, 0x7E, 0x36, 0xFC, 0x3F, 0xF1, 0xE6, 0x95, 0x25,
+	0xAE, 0xA1, 0xA4, 0xDA, 0xEA, 0xD0, 0x3A, 0xCD, 0x19, 0x1B, 0x8A, 0x29, 0x1B, 0xB2, 0x45, 0x78,
+	0x2F, 0xFC, 0x10, 0xE3, 0xFE, 0x0B, 0x27, 0xFF, 0x00, 0x0C, 0xBA, 0xD2, 0x7E, 0xCF, 0xFF, 0x00,
+	0xB4, 0x07, 0x88, 0x25, 0xB8, 0xF0, 0xB3, 0xEC, 0x4D, 0x1A, 0xF2, 0xE2, 0x4C, 0x9B, 0x63, 0xB8,
+	0x64, 0xB3, 0x67, 0xF9, 0x01, 0x5F, 0xA9, 0xFF, 0x00, 0xB5, 0x67, 0xED, 0x8D, 0xFB, 0x18, 0x58,
+	0x7E, 0xCA, 0x1E, 0x34, 0x9F, 0xC1, 0x7F, 0x15, 0x3C, 0x2B, 0xF6, 0x8D, 0x73, 0xC3, 0x37, 0x4B,
+	0x0C, 0x3A, 0x6D, 0xC4, 0x7E, 0x64, 0x8D, 0x2C, 0x67, 0x96, 0x0B, 0xDF, 0x3D, 0x73, 0x5F, 0x15,
+	0x8B, 0xC2, 0x67, 0xB9, 0x65, 0x58, 0xE5, 0x92, 0x8B, 0x9D, 0x3E, 0x65, 0xC8, 0xF7, 0xB6, 0xA8,
+	0x7C, 0xD4, 0xDA, 0xBC, 0xBE, 0x67, 0xCD, 0xDF, 0xF0, 0x6C, 0x36, 0xD7, 0xF8, 0x27, 0xF1, 0x20,
+	0x18, 0x63, 0x46, 0x5F, 0x12, 0xC6, 0x17, 0x81, 0xCF, 0x0F, 0xCE, 0xEC, 0x56, 0x47, 0xFC, 0x15,
+	0x97, 0xF6, 0x45, 0xFD, 0x83, 0x3E, 0x34, 0x7E, 0xD4, 0xD7, 0x9E, 0x29, 0xFD, 0xA6, 0xBF, 0x6D,
+	0x28, 0xBC, 0x2B, 0xA9, 0x34, 0x11, 0x08, 0xBC, 0x3B, 0x2C, 0x12, 0x37, 0x91, 0xC6, 0x03, 0x70,
+	0x7B, 0xD7, 0xCA, 0xFF, 0x00, 0xF0, 0x43, 0xAF, 0xF8, 0x2A, 0x8F, 0x81, 0x3F, 0x63, 0x0F, 0x11,
+	0xF8, 0xB3, 0xE1, 0xA7, 0xC5, 0x99, 0xE3, 0x1A, 0x0E, 0xB9, 0xAC, 0xF9, 0xF1, 0xDD, 0x23, 0x05,
+	0x0B, 0x8D, 0xC0, 0x36, 0x49, 0xC7, 0x7E, 0x7F, 0xA5, 0x7D, 0x27, 0xFB, 0x79, 0x7E, 0xC2, 0xDF,
+	0xB0, 0x4F, 0xFC, 0x15, 0x0F, 0xE2, 0x55, 0xAF, 0xED, 0x51, 0xA2, 0x7E, 0xD8, 0x7E, 0x19, 0xD1,
+	0xAE, 0xAF, 0x23, 0x8E, 0x39, 0xED, 0xAF, 0x35, 0xD4, 0x4E, 0x11, 0x70, 0x01, 0x5D, 0xD5, 0xD1,
+	0x8A, 0xCA, 0x56, 0x0F, 0x8A, 0x25, 0x3C, 0xC1, 0xCE, 0x34, 0xDA, 0xBA, 0x94, 0x55, 0xDD, 0xED,
+	0xB6, 0xC6, 0xB4, 0xEA, 0x46, 0xA4, 0x6C, 0x8F, 0x9C, 0xB5, 0xEF, 0xF8, 0x27, 0x4F, 0xFC, 0x11,
+	0xEA, 0xC7, 0xC3, 0x57, 0xDA, 0xA6, 0x9B, 0xFB, 0x7F, 0x5A, 0xDC, 0x5D, 0x43, 0x6A, 0xEF, 0x04,
+	0x22, 0xDA, 0x50, 0x64, 0x60, 0xA4, 0x85, 0xEB, 0xDC, 0xF1, 0x5F, 0x3C, 0x7F, 0xC1, 0x3D, 0xBF,
+	0x6F, 0xCD, 0x0B, 0xFE, 0x09, 0xB7, 0xFB, 0x5C, 0x6A, 0x5E, 0x26, 0xF0, 0xED, 0x9B, 0x78, 0x83,
+	0xC2, 0x73, 0x5D, 0x11, 0x33, 0xAC, 0x9B, 0x3C, 0xD5, 0x20, 0xA8, 0x70, 0x4E, 0x48, 0xC5, 0x7D,
+	0x4D, 0x75, 0xFF, 0x00, 0x04, 0x23, 0xFD, 0x8D, 0x61, 0xB6, 0x7B, 0xB6, 0xFD, 0xB8, 0x7C, 0x1B,
+	0x22, 0xC3, 0x19, 0x2D, 0x0C, 0x7E, 0x20, 0x1B, 0x9F, 0x1C, 0xE0, 0x7B, 0xD7, 0xCE, 0xBF, 0x0E,
+	0xFF, 0x00, 0xE0, 0x9B, 0x5F, 0xB3, 0xAF, 0xC4, 0x5F, 0xDA, 0x72, 0xEB, 0xE0, 0xE2, 0xFC, 0x78,
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+	0x59, 0x00, 0xF5, 0xEC, 0x2B, 0xF9, 0x43, 0xFD, 0xA9, 0xBE, 0x33, 0xF8, 0x8F, 0xF6, 0x83, 0xFD,
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+	0x6D, 0x3D, 0x7F, 0xD1, 0xC5, 0x20, 0xFF, 0x00, 0x83, 0x7F, 0xFF, 0x00, 0xE0, 0xA0, 0x7F, 0xF4,
+	0x4A, 0xB5, 0x4F, 0xFC, 0x07, 0xAF, 0x52, 0x1C, 0x55, 0x93, 0xC6, 0xCB, 0xDA, 0xC3, 0xF0, 0x25,
+	0xD1, 0x93, 0xDD, 0x1F, 0x14, 0x49, 0xA9, 0x5F, 0xCB, 0x7A, 0xBA, 0x8D, 0xC6, 0xA1, 0x23, 0x5C,
+	0x2F, 0x49, 0x99, 0x8E, 0xE3, 0x8C, 0xFF, 0x00, 0x8D, 0x3A, 0xFB, 0x52, 0xD4, 0x35, 0x49, 0x96,
+	0xE3, 0x50, 0xD4, 0x24, 0x99, 0xD7, 0x3B, 0x4B, 0xB1, 0x38, 0xCF, 0x6A, 0xFB, 0x5B, 0xFE, 0x21,
+	0xFC, 0xFF, 0x00, 0x82, 0x82, 0x7F, 0xD1, 0x2C, 0xD4, 0xBF, 0xEF, 0xCD, 0x23, 0x7F, 0xC1, 0xBF,
+	0x9F, 0xF0, 0x50, 0x5C, 0xE3, 0xFE, 0x15, 0x66, 0xA5, 0xFF, 0x00, 0x7E, 0x6B, 0x39, 0x71, 0x3E,
+	0x47, 0x08, 0xFF, 0x00, 0x1E, 0x3F, 0x26, 0x83, 0xEA, 0xF2, 0x96, 0xE8, 0xF8, 0x8E, 0x48, 0xE0,
+	0x91, 0x59, 0x5A, 0x20, 0x37, 0x1C, 0xB6, 0x09, 0xAB, 0x8B, 0xE2, 0x1D, 0x7D, 0x6D, 0xFE, 0xC6,
+	0x9A, 0xC4, 0xDE, 0x4F, 0x96, 0x13, 0xCB, 0xF3, 0x0E, 0x36, 0xFA, 0x7E, 0x35, 0xF6, 0x8F, 0xFC,
+	0x43, 0xF5, 0xFF, 0x00, 0x05, 0x04, 0xFF, 0x00, 0xA2, 0x5B, 0xAA, 0x7F, 0xDF, 0x9A, 0x3F, 0xE2,
+	0x1F, 0xBF, 0xF8, 0x28, 0x28, 0x18, 0x1F, 0x0A, 0xF5, 0x4F, 0xFB, 0xF3, 0x59, 0xC7, 0x8A, 0x32,
+	0x15, 0x4F, 0x96, 0x35, 0xA3, 0xAF, 0xA1, 0x4A, 0x85, 0x4B, 0x68, 0x7C, 0x43, 0x24, 0x10, 0xC9,
+	0x1F, 0x94, 0xEB, 0xF2, 0xFA, 0x02, 0x6A, 0xCD, 0xA6, 0xAF, 0xAA, 0xE9, 0xF0, 0x7D, 0x97, 0x4C,
+	0xD5, 0x66, 0xB7, 0x87, 0x39, 0xF2, 0x52, 0x43, 0x8A, 0xFB, 0x54, 0x7F, 0xC1, 0xBF, 0x9F, 0xF0,
+	0x50, 0x6C, 0xFF, 0x00, 0xC9, 0x29, 0xD4, 0xFF, 0x00, 0xEF, 0xCD, 0x07, 0xFE, 0x0D, 0xFB, 0xFF,
+	0x00, 0x82, 0x82, 0x9E, 0xBF, 0x0A, 0x35, 0x4F, 0xFB, 0xF0, 0x2A, 0xA3, 0xC4, 0x9C, 0x3F, 0x1F,
+	0x79, 0xD6, 0x8B, 0x7E, 0x76, 0x65, 0x7B, 0x1A, 0x91, 0x47, 0xC6, 0x3F, 0xF0, 0x92, 0x78, 0x93,
+	0x2A, 0xC3, 0x5E, 0x9C, 0x32, 0xF2, 0x18, 0x31, 0xA8, 0xED, 0xB5, 0xCD, 0x72, 0xCD, 0xE5, 0x96,
+	0xDB, 0x57, 0x95, 0x1A, 0x63, 0x99, 0x99, 0x58, 0xE5, 0xF8, 0xC7, 0x35, 0xF6, 0x97, 0xFC, 0x43,
+	0xF7, 0xFF, 0x00, 0x05, 0x05, 0xFF, 0x00, 0xA2, 0x53, 0xAA, 0x7F, 0xDF, 0x81, 0x47, 0xFC, 0x43,
+	0xFB, 0xFF, 0x00, 0x05, 0x04, 0xFF, 0x00, 0xA2, 0x55, 0xA9, 0xFF, 0x00, 0xDF, 0x8A, 0xBF, 0xF5,
+	0xB3, 0x25, 0x96, 0xD5, 0x60, 0xBE, 0xE3, 0x1F, 0x67, 0x2E, 0xC7, 0xC5, 0xED, 0xE2, 0x5F, 0x12,
+	0x30, 0xD8, 0xBA, 0xEC, 0xFB, 0x7B, 0x81, 0x21, 0xA5, 0x6F, 0x12, 0x78, 0x88, 0xAB, 0x06, 0xD6,
+	0xE6, 0x2A, 0x57, 0x1B, 0x77, 0x1C, 0x62, 0xBE, 0xCF, 0x1F, 0xF0, 0x6F, 0xF7, 0xFC, 0x14, 0x0F,
+	0xA0, 0xF8, 0x57, 0xAA, 0x7F, 0xE0, 0x3D, 0x07, 0xFE, 0x0D, 0xFC, 0xFF, 0x00, 0x82, 0x82, 0x7F,
+	0xD1, 0x2C, 0xD4, 0xBF, 0xEF, 0xCD, 0x37, 0xC5, 0x99, 0x24, 0xA1, 0xCB, 0xED, 0x61, 0xF8, 0x15,
+	0x1A, 0x33, 0x4E, 0xE9, 0x1F, 0x13, 0xE9, 0xD7, 0xD7, 0xBA, 0x3C, 0x52, 0x47, 0xA2, 0xDD, 0xBD,
+	0xB2, 0xC9, 0x8F, 0x3C, 0x47, 0xFC, 0x60, 0x7A, 0xD3, 0x6E, 0xEE, 0xA5, 0xD4, 0x2F, 0x3E, 0xDD,
+	0x7B, 0x3B, 0x49, 0x2E, 0xCD, 0xA1, 0xDB, 0x3C, 0x0A, 0xFB, 0x68, 0x7F, 0xC1, 0x00, 0x7F, 0xE0,
+	0xA0, 0xA0, 0x60, 0x7C, 0x2A, 0xD5, 0x3F, 0xF0, 0x1E, 0x90, 0xFF, 0x00, 0xC1, 0xBF, 0xFF, 0x00,
+	0xF0, 0x50, 0x43, 0xD7, 0xE1, 0x56, 0xA9, 0xFF, 0x00, 0x80, 0xF5, 0x9C, 0xB8, 0x9F, 0x25, 0xB2,
+	0xB5, 0x68, 0x7E, 0x03, 0x74, 0xEA, 0x37, 0x76, 0x8F, 0x8C, 0x22, 0xF1, 0x16, 0xB9, 0x0A, 0xAC,
+	0x51, 0xEB, 0x13, 0x04, 0x8F, 0xFD, 0x5A, 0x6F, 0x38, 0x1C, 0x62, 0x8F, 0xF8, 0x48, 0x7C, 0x45,
+	0xB4, 0xA9, 0xD7, 0x27, 0x3E, 0x9F, 0x39, 0xE3, 0xE9, 0x5F, 0x68, 0x7F, 0xC4, 0x3F, 0xDF, 0xF0,
+	0x50, 0x4F, 0xFA, 0x25, 0x5A, 0x97, 0xFD, 0xF8, 0xA4, 0x1F, 0xF0, 0x6F, 0xFF, 0x00, 0xFC, 0x14,
+	0x0C, 0xF1, 0xFF, 0x00, 0x0A, 0xA7, 0x54, 0xFF, 0x00, 0xC0, 0x7A, 0x71, 0xE2, 0xAC, 0x9A, 0x31,
+	0xE5, 0xF6, 0xB0, 0xB7, 0xC8, 0x1D, 0x3A, 0x92, 0xDD, 0x1F, 0x18, 0x9F, 0x14, 0x78, 0xA5, 0x8A,
+	0xEE, 0xF1, 0x05, 0xD7, 0xCB, 0xC7, 0xFA, 0xD3, 0x48, 0xFE, 0x22, 0xF1, 0x0B, 0x92, 0xCD, 0xAD,
+	0xCD, 0xCF, 0xFB, 0x66, 0xBE, 0xD0, 0xFF, 0x00, 0x88, 0x7F, 0x3F, 0xE0, 0xA0, 0x9F, 0xF4, 0x4A,
+	0xF5, 0x2F, 0xFB, 0xF3, 0x47, 0xFC, 0x43, 0xF9, 0xFF, 0x00, 0x05, 0x03, 0xEF, 0xF0, 0xAF, 0x52,
+	0xFF, 0x00, 0xBF, 0x35, 0xA7, 0xFA, 0xDD, 0x91, 0xAD, 0x7D, 0xAC, 0x3E, 0xE4, 0x2F, 0x63, 0x29,
+	0x1F, 0x14, 0xEA, 0x17, 0xDA, 0x86, 0xB1, 0x02, 0x5B, 0xEA, 0xD7, 0xB2, 0x4F, 0x1C, 0x6D, 0xB9,
+	0x23, 0x79, 0x0E, 0x01, 0xA8, 0x53, 0x6A, 0x74, 0x40, 0x7B, 0x0C, 0xF6, 0xAF, 0xB7, 0x3F, 0xE2,
+	0x1F, 0xCF, 0xF8, 0x28, 0x0F, 0xFD, 0x12, 0xDD, 0x4B, 0xFE, 0xFC, 0xD1, 0xFF, 0x00, 0x10, 0xFE,
+	0x7F, 0xC1, 0x40, 0x7F, 0xE8, 0x97, 0x6A, 0x5F, 0xF7, 0xE6, 0xB1, 0x9F, 0x14, 0x70, 0xFD, 0x49,
+	0x5D, 0xD6, 0x8F, 0xE0, 0x8A, 0x8E, 0x1E, 0x71, 0xD8, 0xF8, 0x8F, 0x27, 0x23, 0x9E, 0x07, 0xF0,
+	0xD1, 0x5F, 0x6E, 0x7F, 0xC4, 0x3F, 0x9F, 0xF0, 0x50, 0x1F, 0xFA, 0x25, 0xDA, 0x97, 0xFD, 0xF9,
+	0xA3, 0xFE, 0x21, 0xFC, 0xFF, 0x00, 0x82, 0x80, 0xFF, 0x00, 0xD1, 0x2E, 0xD4, 0xBF, 0xEF, 0xCD,
+	0x4C, 0xB8, 0x9B, 0x21, 0x94, 0xB9, 0xBD, 0xB2, 0xFB, 0xD1, 0x5E, 0xC6, 0xA1, 0xF1, 0x1D, 0x28,
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+	0x73, 0xF0, 0x9F, 0x58, 0x67, 0x9B, 0x4F, 0xBD, 0xD1, 0xDB, 0x4E, 0x9D, 0xA4, 0x5F, 0x99, 0xE3,
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+	0x0D, 0xBD, 0xFF, 0x00, 0x82, 0x6E, 0x5C, 0xB4, 0xD3, 0x5E, 0x7C, 0x31, 0xB4, 0xB8, 0x9A, 0x79,
+	0x0B, 0xC9, 0x2C, 0xD6, 0x68, 0x58, 0xB1, 0xCF, 0x5F, 0x9B, 0xAF, 0x35, 0x09, 0xFF, 0x00, 0x83,
+	0x6C, 0xBF, 0xE0, 0x9A, 0x0B, 0x1A, 0xA4, 0x9F, 0x0A, 0x2C, 0x78, 0xEF, 0xF6, 0x14, 0xC9, 0xFF,
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+	0xF6, 0xE3, 0xFE, 0x15, 0x26, 0x9F, 0xFF, 0x00, 0x80, 0x29, 0xFE, 0x35, 0xFA, 0x05, 0xBD, 0xFF,
+	0x00, 0x81, 0xB7, 0x7F, 0x74, 0x67, 0x93, 0x41, 0x97, 0x0C, 0x03, 0xE0, 0x03, 0xDC, 0xF7, 0xCD,
+	0x47, 0x37, 0x36, 0xA1, 0xB6, 0xE7, 0xE7, 0xE9, 0xFF, 0x00, 0x83, 0x6B, 0x7F, 0xE0, 0x99, 0xCA,
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+	0x04, 0xCA, 0xFB, 0xCF, 0xF0, 0x87, 0x4F, 0x7F, 0x50, 0xDA, 0x7A, 0x72, 0x3F, 0x06, 0xAF, 0xD0,
+	0x28, 0xE4, 0x12, 0x10, 0xC8, 0x78, 0xF7, 0x1F, 0xE7, 0xDE, 0xA4, 0x74, 0x24, 0x75, 0xE2, 0xAB,
+	0x98, 0x0F, 0x19, 0xFD, 0x8D, 0x7F, 0x61, 0xDF, 0x83, 0x5F, 0xB0, 0xEF, 0x83, 0xAF, 0xBC, 0x07,
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+	0x03, 0x1D, 0xAB, 0xDA, 0x2A, 0x30, 0x30, 0x72, 0xBC, 0x7F, 0xB2, 0x29, 0xC1, 0x98, 0xF0, 0x28,
+	0x01, 0xC7, 0x3D, 0xA8, 0xA6, 0x79, 0xBF, 0xE4, 0x73, 0x8A, 0xF9, 0x5F, 0xF6, 0xB1, 0xFF, 0x00,
+	0x82, 0x98, 0xDC, 0x7C, 0x2F, 0xF8, 0xE0, 0xDF, 0xB1, 0x77, 0xEC, 0x97, 0xFB, 0x3F, 0xEB, 0xBF,
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+	0x82, 0xEA, 0xF8, 0xDB, 0xDA, 0x09, 0x0C, 0x91, 0xDD, 0x4E, 0x91, 0x32, 0xC9, 0x3C, 0xC2, 0x76,
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+	0x9F, 0x2F, 0x82, 0xD3, 0x7E, 0xCD, 0xFF, 0x00, 0xF0, 0x52, 0x7F, 0x8B, 0x9E, 0x1D, 0xFD, 0xA6,
+	0xBC, 0x35, 0xFF, 0x00, 0x04, 0xF6, 0xFF, 0x00, 0x82, 0x8B, 0xFC, 0x10, 0xB3, 0xF0, 0x5F, 0xC6,
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+	0xC3, 0x6A, 0xB9, 0x9E, 0x7B, 0x46, 0x63, 0xF6, 0xAB, 0x13, 0x80, 0xED, 0xE4, 0xDD, 0xC6, 0xBB,
+	0x42, 0xE0, 0x48, 0xE4, 0xA8, 0x3F, 0xCE, 0x9F, 0xFC, 0x10, 0x87, 0xC7, 0x1F, 0xF0, 0x5B, 0x6D,
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+	0x61, 0x9F, 0x81, 0x7A, 0x05, 0xAF, 0xFC, 0x15, 0xDF, 0xE1, 0x9F, 0xC3, 0xAD, 0x6B, 0xE2, 0x77,
+	0x86, 0x7E, 0x22, 0x7C, 0x7A, 0xF8, 0x6F, 0xE1, 0x4D, 0x53, 0xC6, 0xBF, 0xB4, 0x67, 0xC5, 0xAB,
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+	0xEF, 0x10, 0xF8, 0x3B, 0x46, 0xF0, 0x8F, 0x80, 0x56, 0x4D, 0x67, 0xC2, 0x3F, 0x03, 0x7F, 0xB4,
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+	0xB8, 0x3F, 0xE0, 0xB0, 0x7F, 0xF0, 0x46, 0x6F, 0x08, 0xE9, 0x1E, 0x3B, 0xF0, 0x5C, 0x1A, 0xD6,
+	0xA5, 0xF0, 0x2B, 0xC4, 0x1A, 0xB5, 0xE4, 0x1A, 0x75, 0x8F, 0x89, 0xF4, 0x29, 0xEF, 0x3C, 0x19,
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+	0xB3, 0x9C, 0x2E, 0xD4, 0x16, 0xCD, 0xBD, 0x99, 0xC4, 0x53, 0xB6, 0xF2, 0xDF, 0x7A, 0xFF, 0x00,
+	0xC1, 0x4D, 0xFF, 0x00, 0x6C, 0x7F, 0x14, 0x7E, 0xDA, 0xFF, 0x00, 0xB1, 0x2F, 0x8C, 0xBC, 0x5D,
+	0xAA, 0x78, 0xDA, 0xDB, 0xF6, 0x77, 0xFD, 0x91, 0x8F, 0x86, 0xEF, 0x2C, 0xF4, 0x7F, 0x10, 0x78,
+	0xA3, 0x4A, 0x4B, 0x6F, 0x15, 0x7C, 0x5B, 0xBC, 0x58, 0x1C, 0xD9, 0x59, 0xE8, 0xB6, 0x12, 0xAB,
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+	0xF2, 0xA7, 0xC6, 0x3F, 0xB1, 0xE7, 0xFC, 0x11, 0xCB, 0xF6, 0xB6, 0xFD, 0x8C, 0xEC, 0xFE, 0x3A,
+	0xFE, 0xC8, 0x1F, 0xB6, 0x14, 0xDF, 0x0A, 0x3E, 0x30, 0x78, 0x73, 0xC3, 0x56, 0x50, 0xF8, 0xB3,
+	0xE0, 0xCF, 0xC4, 0x6B, 0x79, 0xEE, 0x07, 0x88, 0xF5, 0x55, 0x45, 0x89, 0x86, 0x91, 0xF6, 0x71,
+	0x34, 0xF2, 0xC9, 0x71, 0x3F, 0x31, 0xA4, 0x5E, 0x78, 0xF9, 0xD4, 0x34, 0x76, 0xE3, 0x7E, 0xD0,
+	0x0F, 0x9F, 0xBF, 0xE0, 0xA0, 0x5F, 0xF0, 0x48, 0x6F, 0xDB, 0xB7, 0xFE, 0x09, 0xA5, 0xAF, 0xB5,
+	0xB7, 0xED, 0x2F, 0xF0, 0x76, 0xE2, 0x3F, 0x0E, 0xCD, 0x71, 0xE5, 0x69, 0x7E, 0x3C, 0xD0, 0x58,
+	0xDE, 0xE8, 0x7A, 0x8F, 0xF7, 0x4A, 0x5C, 0xA2, 0xFE, 0xE9, 0x9B, 0xB4, 0x73, 0x2C, 0x52, 0x9C,
+	0x13, 0xB3, 0x1C, 0xD7, 0xCC, 0xEC, 0x9B, 0x7A, 0xE7, 0xE9, 0x5F, 0xA6, 0xFF, 0x00, 0x04, 0xFF,
+	0x00, 0xE0, 0xA0, 0xFF, 0x00, 0xF0, 0x5A, 0x3F, 0xF8, 0x21, 0xF6, 0x83, 0xA2, 0xFC, 0x14, 0xFD,
+	0xAE, 0xFE, 0x01, 0xEB, 0x7A, 0xEF, 0xC2, 0x0F, 0x11, 0xE9, 0x70, 0x08, 0xFE, 0x18, 0xFC, 0x68,
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+	0x88, 0x15, 0x36, 0xC4, 0xB2, 0x44, 0xD9, 0xF3, 0x2D, 0xB3, 0x90, 0x7D, 0x02, 0xE7, 0xF6, 0x26,
+	0xFF, 0x00, 0x82, 0x2A, 0x7F, 0xC1, 0x69, 0xFC, 0xEF, 0x10, 0x7F, 0xC1, 0x3A, 0x3E, 0x32, 0xC3,
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+	0x00, 0xC2, 0xE9, 0xF8, 0x48, 0x72, 0x07, 0xC4, 0x1D, 0x2F, 0xFF, 0x00, 0x02, 0x85, 0x35, 0x86,
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+	0x6B, 0x7F, 0x10, 0x78, 0x7F, 0x54, 0x8F, 0x65, 0xEE, 0x9D, 0x70, 0xCC, 0xAB, 0x22, 0xE7, 0x3D,
+	0x54, 0x83, 0xD7, 0x9E, 0xB5, 0xA9, 0xFF, 0x00, 0x0B, 0xAF, 0xE1, 0x41, 0x6D, 0xAB, 0xF1, 0x13,
+	0x49, 0xFA, 0x0B, 0xB1, 0x4E, 0x5F, 0x8D, 0x3F, 0x09, 0x4B, 0x67, 0xFE, 0x16, 0x1E, 0x97, 0x9F,
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+	0xA6, 0xED, 0x19, 0x24, 0x7C, 0xA7, 0xA0, 0x7F, 0xC1, 0xBC, 0xDF, 0xF0, 0x48, 0x0F, 0x0A, 0xEB,
+	0x96, 0x3E, 0x25, 0xD0, 0xFF, 0x00, 0x63, 0x9D, 0x1A, 0x0B, 0xCD, 0x36, 0xE9, 0x2E, 0x6C, 0xA5,
+	0xFB, 0x65, 0xC1, 0xF2, 0xE4, 0x52, 0x08, 0x38, 0x32, 0x73, 0xC8, 0x07, 0x9A, 0xFB, 0x07, 0xC3,
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+	0x56, 0xD0, 0xA9, 0xE1, 0x10, 0x74, 0x1F, 0x85, 0x65, 0x7F, 0xC2, 0xEA, 0xF8, 0x4E, 0x46, 0x5B,
+	0xE2, 0x16, 0x97, 0xFF, 0x00, 0x81, 0x42, 0x83, 0xF1, 0xAB, 0xE1, 0x29, 0xF9, 0x0F, 0xC4, 0x0D,
+	0x2C, 0xFB, 0x7D, 0xA8, 0x55, 0x7B, 0x1C, 0x57, 0x2F, 0x23, 0x83, 0xB7, 0xA0, 0xAF, 0x47, 0x9B,
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+	0x7E, 0xD4, 0xDF, 0x05, 0x2C, 0x7C, 0x58, 0xBA, 0x4C, 0xCD, 0x2E, 0x9F, 0xF6, 0xB9, 0xA4, 0x5F,
+	0x25, 0x88, 0xC1, 0x23, 0x61, 0x1D, 0x45, 0x70, 0xFF, 0x00, 0x01, 0xFF, 0x00, 0xE0, 0x89, 0xBF,
+	0xF0, 0x4C, 0xFF, 0x00, 0xD9, 0x83, 0xE2, 0x1C, 0x1F, 0x16, 0x7E, 0x06, 0xFE, 0xCC, 0xBA, 0x56,
+	0x87, 0xE2, 0x0B, 0x78, 0xCA, 0x43, 0xA8, 0x43, 0x71, 0x2B, 0x32, 0xA9, 0xC6, 0x40, 0x0C, 0xC4,
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+	0xFF, 0x00, 0xC5, 0x5F, 0x88, 0xD2, 0x0B, 0x4B, 0x36, 0xB3, 0xE0, 0xF9, 0xB6, 0xB0, 0x33, 0x2C,
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+	0x91, 0xFE, 0xD3, 0x9F, 0xB6, 0xFF, 0x00, 0x8D, 0x34, 0x9F, 0xD9, 0xAF, 0xE0, 0xBD, 0x9C, 0x82,
+	0x5D, 0x53, 0xC5, 0x9F, 0x14, 0x18, 0xD8, 0xEA, 0x17, 0x16, 0xE0, 0x9F, 0xF8, 0xF5, 0xB2, 0x9B,
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+	0x3E, 0x0B, 0x41, 0xFB, 0x48, 0xFC, 0x6C, 0xB3, 0x0E, 0x92, 0x7C, 0x71, 0xF8, 0x99, 0x66, 0xDF,
+	0xD8, 0xFA, 0x55, 0xD2, 0xEF, 0x42, 0xFA, 0x7D, 0xB0, 0x54, 0x2C, 0x06, 0x58, 0x06, 0x80, 0x47,
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+	0x61, 0x6B, 0xFD, 0x2A, 0xF2, 0xDE, 0xEA, 0xD6, 0x6F, 0xDA, 0x43, 0x47, 0x92, 0x0B, 0x8B, 0x69,
+	0x96, 0x48, 0xA4, 0x5F, 0xF8, 0x46, 0x35, 0xB2, 0x19, 0x59, 0x72, 0x08, 0xF4, 0x23, 0x83, 0x5F,
+	0x1B, 0x7C, 0x17, 0xD4, 0x2D, 0xF5, 0x0F, 0xF8, 0x22, 0x77, 0xEC, 0x65, 0xA8, 0x5A, 0x48, 0x7C,
+	0xBB, 0x8F, 0xDB, 0xBB, 0x4A, 0x96, 0x2F, 0x94, 0x86, 0x20, 0xFC, 0x47, 0xD5, 0xD8, 0x60, 0x76,
+	0x38, 0xE7, 0xDB, 0x14, 0x01, 0xE8, 0x7F, 0xB1, 0xB6, 0x83, 0xFF, 0x00, 0x04, 0xBC, 0xF8, 0x5D,
+	0xA0, 0x6A, 0x5F, 0xF0, 0x5B, 0xBF, 0xDB, 0x27, 0xF6, 0xA3, 0xF0, 0x07, 0xC5, 0xCF, 0x8C, 0x1A,
+	0xE6, 0xA5, 0xE5, 0x37, 0x88, 0xB4, 0x4F, 0x0F, 0xAD, 0x9C, 0x7E, 0x1F, 0xD4, 0xA5, 0x1B, 0xA2,
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+	0xFF, 0x00, 0x19, 0x3F, 0xE0, 0xAB, 0x3E, 0x1C, 0xF1, 0x2F, 0x85, 0x7E, 0x1C, 0x5E, 0x2C, 0x9A,
+	0x9F, 0xC2, 0xFF, 0x00, 0xD8, 0x8F, 0xC2, 0x2E, 0x6E, 0xBC, 0x53, 0xE3, 0xD8, 0xED, 0xF3, 0x34,
+	0x5A, 0x8F, 0x8A, 0x0D, 0xB1, 0x26, 0xDA, 0xD5, 0x02, 0x2C, 0xA6, 0xD0, 0xB0, 0x82, 0x22, 0xB8,
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+	0xCB, 0x78, 0x83, 0xE2, 0x87, 0xED, 0x15, 0xE2, 0xCF, 0x0E, 0xDC, 0x78, 0xBB, 0x59, 0xF0, 0xF6,
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+	0x10, 0xD9, 0xC4, 0x23, 0xB7, 0x85, 0x22, 0x0D, 0x22, 0xC9, 0x83, 0x90, 0x0F, 0xCE, 0x1F, 0xD8,
+	0xCF, 0xF6, 0xA1, 0xFD, 0x80, 0x3F, 0x6F, 0x2F, 0x83, 0x51, 0xFF, 0x00, 0xC1, 0x3F, 0x3F, 0x68,
+	0x4F, 0xF8, 0x25, 0x7F, 0x8A, 0x7C, 0x49, 0xE3, 0xC8, 0x75, 0x1D, 0x76, 0xF3, 0xE1, 0x1F, 0x8A,
+	0xBE, 0x07, 0xDC, 0xA2, 0xEB, 0xA9, 0x26, 0xA1, 0xA8, 0x5D, 0x5E, 0xA5, 0x95, 0xC6, 0xE4, 0x8E,
+	0x31, 0x6F, 0x0B, 0x5C, 0x84, 0x12, 0xCC, 0xB2, 0xDB, 0xA4, 0x49, 0xBD, 0xA2, 0x8F, 0x61, 0x63,
+	0xD8, 0x7C, 0x5D, 0xFF, 0x00, 0x82, 0x2E, 0x7F, 0xC1, 0x55, 0x3F, 0xE0, 0x85, 0xDF, 0x02, 0xAC,
+	0xBF, 0xE0, 0xA4, 0xBF, 0x06, 0xBF, 0x6C, 0x4F, 0x0F, 0xF8, 0x37, 0x56, 0xB3, 0x8D, 0x7F, 0xE1,
+	0x2F, 0xF0, 0xF5, 0x87, 0x89, 0x92, 0x1B, 0x8B, 0x01, 0x23, 0xE6, 0x0B, 0x22, 0xD3, 0xA8, 0xB4,
+	0xD7, 0x0F, 0x45, 0x78, 0x42, 0x7C, 0xD2, 0x0F, 0xDD, 0xC5, 0x22, 0xFC, 0xE3, 0xF5, 0x23, 0xF6,
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+	0xFB, 0x00, 0xAB, 0xFE, 0xD2, 0x3F, 0x1A, 0x3E, 0x35, 0x4D, 0x34, 0xFA, 0x64, 0xDE, 0x0D, 0xB8,
+	0xB6, 0xD4, 0xFC, 0x53, 0xE3, 0x7B, 0xC6, 0x98, 0xF9, 0xF7, 0x17, 0x93, 0x20, 0x48, 0xF4, 0xAB,
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+	0x00, 0xF0, 0x57, 0x0F, 0x8F, 0x5A, 0x5F, 0x84, 0xFE, 0x18, 0xFC, 0x52, 0xF1, 0x0F, 0xED, 0xAA,
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+	0x1D, 0x2F, 0xFE, 0x0A, 0xD3, 0xFF, 0x00, 0x04, 0xBA, 0xFF, 0x00, 0x82, 0xB8, 0x59, 0xC1, 0xF0,
+	0xFF, 0x00, 0xFE, 0x0B, 0x61, 0xFB, 0x33, 0x41, 0xE0, 0x3F, 0x88, 0x2D, 0x67, 0x1D, 0xA6, 0x99,
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+	0xAF, 0xDA, 0x8F, 0xE0, 0x2F, 0xC3, 0xFF, 0x00, 0xF8, 0x69, 0x7F, 0xD8, 0xEB, 0xC6, 0x3A, 0x4F,
+	0xED, 0x21, 0xF0, 0x62, 0xEA, 0x16, 0xB9, 0xB1, 0xF1, 0xC7, 0xC3, 0x2D, 0xB7, 0x57, 0x50, 0xC0,
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+	0x1E, 0x08, 0x1E, 0xDD, 0xF0, 0x32, 0xF3, 0xC0, 0xBF, 0xF0, 0x5F, 0xAF, 0xD9, 0xCA, 0xCF, 0xF6,
+	0x5C, 0xF0, 0x97, 0xFC, 0x12, 0xAA, 0x1B, 0x3F, 0xDA, 0x0B, 0xC1, 0xFA, 0x16, 0x9B, 0xA3, 0x69,
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+	0x43, 0x80, 0x51, 0xDF, 0xB5, 0xF7, 0xEC, 0x4B, 0xFB, 0x7B, 0x7F, 0xC1, 0xB0, 0xFE, 0x32, 0xF0,
+	0x7F, 0xC5, 0xDF, 0xD9, 0x3F, 0xFE, 0x0A, 0x2F, 0xA3, 0xEA, 0x71, 0x78, 0xBA, 0x7B, 0x78, 0xA6,
+	0xF0, 0x1C, 0x72, 0x34, 0x17, 0x9A, 0xC5, 0xDA, 0xAC, 0x62, 0xE0, 0xC9, 0xA2, 0xC8, 0x65, 0x8E,
+	0xF2, 0xD3, 0x7A, 0xEC, 0x17, 0x0A, 0x7C, 0xC8, 0xFC, 0xC4, 0x4C, 0xAB, 0xED, 0x76, 0x00, 0xFC,
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+	0x58, 0x1C, 0x60, 0xE7, 0xBE, 0x6B, 0xEB, 0x9F, 0xF8, 0x27, 0x77, 0xFC, 0x11, 0x0B, 0xF6, 0xF2,
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+	0xF7, 0x6A, 0x7F, 0x13, 0x7C, 0x6A, 0xC6, 0xC3, 0x46, 0xB7, 0x89, 0x79, 0x76, 0x8D, 0xDC, 0x6F,
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+	0x7F, 0xF0, 0x48, 0x7F, 0x8F, 0x36, 0xEB, 0xFB, 0x4F, 0xFE, 0xDC, 0x1F, 0xF0, 0x46, 0xCD, 0x07,
+	0xC4, 0x1F, 0xB4, 0x26, 0x91, 0x6E, 0xC2, 0xDE, 0x4F, 0x0A, 0xA4, 0x36, 0xFE, 0x15, 0xF1, 0x4D,
+	0xC9, 0x51, 0x8B, 0x8D, 0x4E, 0x09, 0xA5, 0xC8, 0x20, 0xA8, 0x00, 0x49, 0x0D, 0xEB, 0x6D, 0xC8,
+	0xDE, 0x46, 0x14, 0x62, 0xF8, 0x27, 0xF6, 0x9D, 0xFF, 0x00, 0x82, 0x8C, 0x7F, 0xC1, 0xCA, 0x5F,
+	0xB4, 0xEE, 0x9F, 0xFB, 0x1D, 0xF8, 0xCB, 0xF6, 0xB5, 0xF0, 0x67, 0xC1, 0x1F, 0x01, 0xCF, 0x69,
+	0xE7, 0x69, 0x5F, 0x0E, 0xEC, 0xEE, 0xA5, 0xD3, 0x34, 0xFB, 0xBB, 0x34, 0x2D, 0xFB, 0xAB, 0x4B,
+	0x35, 0x61, 0x26, 0xB3, 0x70, 0x88, 0x85, 0x84, 0x72, 0x48, 0x15, 0x56, 0x37, 0x75, 0x11, 0x80,
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+	0x16, 0x1F, 0xDB, 0x2B, 0xF6, 0x84, 0xD2, 0xD8, 0x0F, 0xF8, 0x4A, 0xB5, 0x5C, 0x41, 0xE0, 0xFD,
+	0x0A, 0xEB, 0xE5, 0x3B, 0xA0, 0x45, 0xF3, 0x22, 0x9C, 0xA7, 0xDE, 0x05, 0x3E, 0xD2, 0xFB, 0x95,
+	0x94, 0x4F, 0x09, 0x25, 0x56, 0x87, 0xEC, 0xFF, 0x00, 0xF0, 0xAB, 0xFE, 0x0A, 0xB3, 0xFF, 0x00,
+	0x07, 0x56, 0xF8, 0xFF, 0x00, 0x5C, 0xD4, 0xFE, 0x31, 0x7E, 0xD8, 0xFE, 0x17, 0xF0, 0xE7, 0x82,
+	0xFC, 0x15, 0x75, 0xE6, 0x9F, 0x0D, 0xFD, 0xA0, 0x47, 0x69, 0xA6, 0x4E, 0xD1, 0xFE, 0xE8, 0xDB,
+	0x68, 0xF6, 0xEE, 0x25, 0x97, 0x21, 0xD9, 0x3E, 0xD9, 0x70, 0xC4, 0x85, 0xF3, 0x14, 0x4A, 0xC4,
+	0x14, 0x3E, 0x99, 0xE3, 0x2F, 0xF8, 0x27, 0x0F, 0xC2, 0x8F, 0xF8, 0x37, 0x3F, 0x50, 0xF1, 0x77,
+	0xC7, 0xEF, 0xDA, 0xA3, 0xFE, 0x09, 0xF9, 0x7B, 0xFB, 0x4E, 0x59, 0xAD, 0xF4, 0x2D, 0xF0, 0x97,
+	0xE2, 0x44, 0x9A, 0x82, 0x1F, 0x0E, 0xE9, 0x6C, 0x4F, 0xCB, 0x16, 0xB1, 0xA6, 0xB4, 0x4D, 0xF6,
+	0x2B, 0x85, 0x70, 0x9B, 0x66, 0x26, 0xE6, 0x39, 0x4E, 0x04, 0x7E, 0x53, 0x03, 0x9E, 0x27, 0xFE,
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+	0xB1, 0xFB, 0x3A, 0xFC, 0x4C, 0xB8, 0xF8, 0xAF, 0xA8, 0xF8, 0x9B, 0xC1, 0xBF, 0xB5, 0x97, 0xC3,
+	0xBD, 0x12, 0x44, 0xF0, 0xF7, 0x86, 0x6F, 0x75, 0x59, 0x92, 0x61, 0xE1, 0xCD, 0x67, 0x7E, 0xF8,
+	0xFF, 0x00, 0xB2, 0x9E, 0x70, 0xC5, 0x6D, 0xEE, 0xA4, 0x78, 0x99, 0x65, 0x6C, 0xB4, 0x47, 0x74,
+	0x8E, 0x01, 0x57, 0x5A, 0xF0, 0xD7, 0xEC, 0xB9, 0xFF, 0x00, 0x06, 0xFA, 0xFC, 0x30, 0x93, 0xC2,
+	0x1F, 0xB4, 0xFF, 0x00, 0xFC, 0x12, 0xF3, 0xC4, 0x1E, 0x34, 0xFD, 0xA6, 0xF5, 0x18, 0xAF, 0xAC,
+	0xF4, 0x8F, 0x1C, 0xF8, 0xCB, 0x5A, 0x8E, 0xFB, 0xC1, 0x46, 0xD9, 0x86, 0xC4, 0xD4, 0x74, 0x89,
+	0x56, 0x35, 0x56, 0x3B, 0x4E, 0xEF, 0x25, 0xE0, 0x5B, 0xA8, 0x88, 0x2A, 0xD2, 0xC6, 0x1C, 0x16,
+	0xF6, 0x7F, 0xF8, 0x23, 0x07, 0xED, 0x13, 0xE0, 0x3F, 0x11, 0xFC, 0x29, 0xF8, 0x77, 0x77, 0xFF,
+	0x00, 0x04, 0xFB, 0xF1, 0x72, 0x7C, 0x0F, 0xFD, 0xA1, 0xAC, 0x34, 0x18, 0xB4, 0x9D, 0x7B, 0xE1,
+	0x97, 0x8E, 0xF7, 0xA7, 0x82, 0x7F, 0x68, 0x05, 0xD3, 0xA2, 0x11, 0x49, 0x24, 0x33, 0x95, 0x09,
+	0x06, 0xA8, 0x13, 0x05, 0xA6, 0x87, 0x6C, 0xD1, 0xBC, 0x98, 0x71, 0x3C, 0x7B, 0xA4, 0xAF, 0xD0,
+	0x7B, 0xDF, 0xDA, 0x33, 0xE0, 0x7F, 0xED, 0x51, 0xE1, 0xF9, 0x7F, 0xE0, 0x9A, 0xBF, 0xF0, 0x5C,
+	0xAF, 0x81, 0xDE, 0x11, 0xD0, 0x7C, 0x49, 0xAC, 0x68, 0xED, 0x79, 0xE1, 0xFF, 0x00, 0x17, 0x34,
+	0xD8, 0xF0, 0x5F, 0x8F, 0x2D, 0xD1, 0x37, 0x7F, 0x69, 0x68, 0x1A, 0xA3, 0xB0, 0x6B, 0x4B, 0xB4,
+	0x4C, 0x48, 0xD6, 0xEC, 0xE9, 0x3C, 0x41, 0x81, 0x56, 0x91, 0x09, 0x23, 0xE6, 0xBF, 0xD9, 0x4B,
+	0xE2, 0x97, 0xC0, 0x9F, 0x8E, 0xDF, 0x1F, 0x7C, 0x3F, 0xFF, 0x00, 0x04, 0x59, 0xF1, 0x97, 0xDA,
+	0x3F, 0x68, 0xCF, 0xD9, 0xA7, 0x5D, 0xD3, 0x35, 0x25, 0xF8, 0x25, 0xF1, 0xC3, 0x51, 0xD0, 0x26,
+	0xD3, 0xB5, 0x1D, 0x07, 0x52, 0xD2, 0x6D, 0xDE, 0x7B, 0x8B, 0x4B, 0x6D, 0x5E, 0x24, 0x8E, 0x1D,
+	0x4E, 0x4B, 0x75, 0xD8, 0x12, 0xFE, 0xCF, 0xCA, 0x91, 0x19, 0xC0, 0x73, 0x28, 0x63, 0x80, 0x0F,
+	0x74, 0xF8, 0xF7, 0x0F, 0xFC, 0x13, 0x2B, 0xFE, 0x0B, 0x2F, 0xF0, 0x87, 0x58, 0x9B, 0xF6, 0xC9,
+	0xD0, 0x57, 0xE0, 0x4F, 0xC6, 0xCF, 0x82, 0x70, 0x9B, 0xFD, 0x71, 0xBC, 0x6F, 0x2D, 0xAD, 0x86,
+	0xBF, 0xF0, 0xFE, 0x58, 0x5B, 0x70, 0xBB, 0xF3, 0x2E, 0x31, 0x06, 0xA7, 0xA4, 0x19, 0x48, 0x65,
+	0x90, 0x87, 0xB4, 0x98, 0x10, 0x7E, 0x47, 0x23, 0x1E, 0x3F, 0xFB, 0x31, 0x7C, 0x4E, 0xF0, 0xBF,
+	0xFC, 0x15, 0x92, 0x5F, 0x19, 0x78, 0x17, 0xC6, 0x9A, 0x9B, 0x68, 0x7F, 0x1D, 0xBF, 0x67, 0x1F,
+	0x0E, 0xC5, 0xAB, 0x7C, 0x22, 0xFD, 0xAB, 0x3E, 0x12, 0xE8, 0x73, 0x68, 0x7F, 0xF0, 0x94, 0xE8,
+	0xE5, 0xA7, 0x8A, 0x0B, 0xA8, 0x6C, 0xAE, 0x22, 0x51, 0x25, 0xA4, 0x8F, 0x6F, 0x24, 0x32, 0xDA,
+	0x95, 0x9A, 0xCE, 0x4D, 0xD2, 0x18, 0x0A, 0x8C, 0x11, 0xCE, 0xF8, 0x1F, 0xE1, 0x76, 0x89, 0xFB,
+	0x46, 0x7C, 0x7F, 0xFD, 0x9D, 0xFE, 0x17, 0xFE, 0xD8, 0x10, 0xD9, 0x7C, 0x62, 0x6F, 0x85, 0x9F,
+	0xB6, 0x77, 0xC4, 0x2F, 0x85, 0xFA, 0x77, 0x8A, 0x3E, 0x21, 0x68, 0xF6, 0xB7, 0x9A, 0xBE, 0xB1,
+	0xA0, 0x69, 0x3A, 0x1D, 0xDD, 0xC6, 0x9F, 0x16, 0xA5, 0x37, 0x96, 0xBF, 0x6D, 0x74, 0x9A, 0x38,
+	0xE4, 0x76, 0x71, 0x89, 0x1D, 0x15, 0xD9, 0x49, 0x24, 0x9F, 0xB5, 0x13, 0x4D, 0xD3, 0xF4, 0xBF,
+	0xF8, 0x2C, 0xEF, 0xC6, 0x2B, 0x4D, 0x2F, 0x4F, 0x86, 0xDE, 0x08, 0xFF, 0x00, 0x63, 0x7F, 0x0E,
+	0x24, 0x70, 0xDB, 0xC6, 0x11, 0x55, 0x57, 0x5A, 0xD7, 0x55, 0x54, 0x01, 0x80, 0x00, 0x55, 0x0A,
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+	0x19, 0x18, 0x34, 0xD2, 0x99, 0xEA, 0xC6, 0x9D, 0x45, 0x00, 0x79, 0x97, 0xED, 0x49, 0xFB, 0x1B,
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+	0x78, 0x23, 0xC4, 0x5F, 0x0E, 0xFE, 0x33, 0xF8, 0xEB, 0xE1, 0xDF, 0x8B, 0x35, 0x6D, 0x2F, 0x53,
+	0xF8, 0x2B, 0xF1, 0x0B, 0x54, 0x7D, 0x2F, 0xC5, 0x3E, 0x1D, 0xF0, 0x75, 0x94, 0x46, 0x44, 0xBB,
+	0xF0, 0xE5, 0xCC, 0x9B, 0xE3, 0x8A, 0x29, 0x15, 0x9F, 0xCC, 0x43, 0x02, 0xA4, 0xA1, 0x39, 0x97,
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+	0x21, 0xF8, 0x1E, 0xED, 0xDB, 0xC2, 0x3F, 0x0E, 0xAC, 0xAE, 0xED, 0xD6, 0x5B, 0x3D, 0x77, 0xC4,
+	0xD7, 0x4E, 0x8A, 0x8D, 0x32, 0xC5, 0x32, 0xEE, 0x9E, 0xE9, 0x70, 0x8D, 0x2B, 0x47, 0x6F, 0x0B,
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+	0x1F, 0x2A, 0xC1, 0x92, 0x05, 0x5F, 0x99, 0x7A, 0x4F, 0x05, 0x7C, 0x3B, 0xF1, 0x27, 0xEC, 0xE9,
+	0xFF, 0x00, 0x04, 0x62, 0xFD, 0x89, 0x7C, 0x31, 0xFB, 0x51, 0xF8, 0x66, 0xE3, 0xC0, 0xB7, 0xDA,
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+	0xC5, 0x3A, 0xC6, 0xA5, 0x6A, 0xF7, 0x19, 0x7C, 0x44, 0xDE, 0x4C, 0xD0, 0x48, 0xCA, 0xC4, 0x14,
+	0xDD, 0x87, 0x0A, 0x41, 0x03, 0xD1, 0xBC, 0x4D, 0x16, 0x9F, 0xFB, 0x38, 0x7E, 0xD1, 0xDA, 0x0F,
+	0xC4, 0x4F, 0xDA, 0x64, 0xBF, 0xED, 0x69, 0xFB, 0x76, 0x6A, 0x5A, 0x64, 0x93, 0xFC, 0x3D, 0xF8,
+	0x57, 0xE1, 0x1F, 0xF4, 0x7F, 0x0F, 0xFC, 0x39, 0xB5, 0x97, 0x6E, 0x4D, 0xBC, 0x72, 0x66, 0x1D,
+	0x22, 0xCD, 0x72, 0xAA, 0xFA, 0x9D, 0xD8, 0xFB, 0x4D, 0xC0, 0x4C, 0xA0, 0xC9, 0x65, 0xAE, 0x87,
+	0xE2, 0xF7, 0xC0, 0x4F, 0xD9, 0xCF, 0xF6, 0x7C, 0xD3, 0x21, 0xFD, 0xB7, 0xBF, 0xE0, 0xBC, 0x5E,
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+	0x24, 0x9A, 0x96, 0x8F, 0xA6, 0x1B, 0xCD, 0xA8, 0xFA, 0x2F, 0x86, 0xF4, 0x46, 0x05, 0xEF, 0xAE,
+	0x25, 0x06, 0x34, 0x96, 0xF2, 0x58, 0xCC, 0xAE, 0x00, 0x2E, 0xD1, 0x20, 0x34, 0x01, 0x95, 0xFF,
+	0x00, 0x05, 0x95, 0xBC, 0xB7, 0xD4, 0xBF, 0x69, 0xCF, 0x89, 0x03, 0x4E, 0xB8, 0x59, 0xBC, 0x9F,
+	0xF8, 0x26, 0xAF, 0xC5, 0xCB, 0x87, 0x68, 0xDB, 0xE5, 0x11, 0xBC, 0xBA, 0x7A, 0xA3, 0x83, 0xD1,
+	0x81, 0x61, 0x8E, 0x09, 0x3F, 0x86, 0x09, 0xEB, 0x3C, 0x1D, 0x6D, 0x71, 0x6F, 0xFB, 0x72, 0xFF,
+	0x00, 0xC1, 0x3D, 0x3C, 0x3D, 0x6B, 0x10, 0x9A, 0x1D, 0x3F, 0xF6, 0x6D, 0xF1, 0x54, 0xB2, 0x4D,
+	0xD0, 0xED, 0x1A, 0x4E, 0x83, 0x10, 0x38, 0x39, 0xEA, 0x58, 0x71, 0xD4, 0x67, 0xA9, 0x1D, 0x3E,
+	0x33, 0xD6, 0x7F, 0x66, 0x3D, 0x43, 0xF6, 0x60, 0xF0, 0xBF, 0xC5, 0x7D, 0x43, 0x5F, 0xF0, 0xD6,
+	0xBB, 0xE1, 0xAF, 0x1F, 0x7C, 0x7C, 0xF8, 0x13, 0xE2, 0x3F, 0x85, 0xFF, 0x00, 0xB3, 0x37, 0xEC,
+	0x61, 0xA0, 0x6B, 0xF7, 0x3E, 0x2A, 0xD5, 0xFC, 0x35, 0xA5, 0xEB, 0x42, 0x26, 0x92, 0xF6, 0xEE,
+	0x69, 0x24, 0x6F, 0xEC, 0xF8, 0x04, 0xF0, 0x07, 0x91, 0x01, 0x5B, 0x4B, 0x55, 0xF3, 0x17, 0xCC,
+	0x67, 0xCA, 0x8F, 0xB0, 0xBE, 0x20, 0x78, 0xFB, 0xE1, 0xFF, 0x00, 0xEC, 0xCF, 0xFF, 0x00, 0x05,
+	0x3A, 0xFD, 0x87, 0x7E, 0x1D, 0x7C, 0x78, 0xF8, 0x85, 0xA0, 0xF8, 0x5F, 0x54, 0xD3, 0x7F, 0x67,
+	0xDF, 0x14, 0x68, 0x77, 0x51, 0xEA, 0xFA, 0xC4, 0x10, 0xC6, 0x9A, 0x83, 0xC1, 0xA1, 0xC5, 0x1D,
+	0xB8, 0x91, 0x9C, 0x29, 0x69, 0x1E, 0xDA, 0x74, 0x8F, 0x9F, 0x9D, 0x94, 0x85, 0x2C, 0x70, 0x28,
+	0x03, 0xE7, 0x6F, 0xDA, 0x8A, 0xD9, 0x3E, 0x06, 0xFE, 0xD7, 0xFF, 0x00, 0xB7, 0x6D, 0x8F, 0xC0,
+	0x1B, 0xA6, 0xF8, 0x79, 0xAA, 0x78, 0xC3, 0xE2, 0x27, 0xC0, 0xBF, 0x0B, 0x49, 0xE2, 0x2F, 0x04,
+	0xDA, 0xC3, 0x63, 0xA8, 0xD9, 0xDA, 0x6B, 0x78, 0x87, 0x53, 0x36, 0xD3, 0xAA, 0x6E, 0xB7, 0x96,
+	0x64, 0x79, 0x18, 0xCA, 0x98, 0x6F, 0x30, 0x89, 0x33, 0xBF, 0xE6, 0xAD, 0xDF, 0xDB, 0x6F, 0xE2,
+	0x0F, 0x85, 0x7F, 0x63, 0xFF, 0x00, 0x8C, 0x63, 0xFE, 0x09, 0x57, 0xF0, 0x5B, 0xC1, 0xDE, 0x24,
+	0xF8, 0x37, 0xFB, 0x2D, 0x78, 0x57, 0xC1, 0x76, 0x3A, 0xFF, 0x00, 0xED, 0x0D, 0xF1, 0x53, 0xE1,
+	0x87, 0x87, 0x64, 0xD6, 0x75, 0xFB, 0x88, 0xB5, 0x36, 0xB9, 0x85, 0x56, 0xFA, 0xE0, 0x6F, 0x9E,
+	0xCE, 0x29, 0x96, 0xD6, 0x56, 0xB8, 0xD4, 0x82, 0x5C, 0xDC, 0x61, 0x40, 0xCC, 0x6A, 0x72, 0x72,
+	0xFF, 0x00, 0x6B, 0xDB, 0x88, 0x66, 0xFD, 0xBB, 0xBF, 0x6B, 0x49, 0xEE, 0x25, 0x52, 0xDF, 0xF0,
+	0xD4, 0xDF, 0xB3, 0x5D, 0xBD, 0xBF, 0xCD, 0xD6, 0x31, 0x15, 0x8C, 0xA1, 0x47, 0xE3, 0x24, 0x8D,
+	0xEB, 0xC9, 0xF4, 0xAF, 0xB7, 0xBE, 0x01, 0x44, 0x92, 0x7F, 0xC1, 0x70, 0x3F, 0x68, 0xF1, 0x22,
+	0xE7, 0xFE, 0x2C, 0x9F, 0xC3, 0xE1, 0x83, 0xDC, 0x1B, 0x9D, 0x72, 0x80, 0x3C, 0xA3, 0xC1, 0x9F,
+	0xB5, 0xEF, 0xEC, 0xF9, 0xF0, 0x87, 0xE1, 0xBE, 0x9F, 0xFB, 0x00, 0x7F, 0xC1, 0x01, 0x7E, 0x17,
+	0x78, 0x23, 0xC4, 0xD7, 0x9A, 0x6E, 0x85, 0x1D, 0xF6, 0xAD, 0xE3, 0x6B, 0x6B, 0xA2, 0x7C, 0x19,
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+	0xA9, 0xE5, 0x2B, 0xAB, 0xF9, 0x0D, 0x75, 0x6C, 0xC9, 0x2C, 0x90, 0x92, 0xA3, 0x31, 0xB9, 0x65,
+	0x07, 0x90, 0x03, 0x61, 0x87, 0x2B, 0xFF, 0x00, 0x05, 0x2A, 0xF8, 0x13, 0x27, 0xC2, 0xDF, 0xF8,
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+	0x6F, 0x2E, 0xC3, 0x7E, 0x42, 0x82, 0xEE, 0x59, 0x89, 0xDC, 0xCC, 0x72, 0x01, 0xF3, 0x0F, 0xC1,
+	0x29, 0xAD, 0xBC, 0x03, 0xF1, 0x1B, 0xC5, 0x9F, 0xB3, 0xAF, 0xFC, 0x12, 0x19, 0x7F, 0xE1, 0x73,
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+	0x40, 0x9B, 0x8F, 0x36, 0x06, 0xBA, 0x8F, 0x02, 0xF2, 0xEA, 0x2F, 0x94, 0xC1, 0xA4, 0x5A, 0xE2,
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+	0x24, 0x8B, 0xE6, 0x57, 0xCF, 0xBF, 0x07, 0xFF, 0x00, 0x6B, 0x8F, 0x1A, 0x7E, 0xCA, 0x9F, 0x00,
+	0x7E, 0x1D, 0x7E, 0xCB, 0x5F, 0xB1, 0x5F, 0xFC, 0x14, 0xD3, 0xE1, 0x4A, 0xFC, 0x0B, 0xF1, 0x96,
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+	0xC5, 0xDC, 0x51, 0xCA, 0xB2, 0xBA, 0xEF, 0x13, 0x02, 0xAF, 0x5E, 0xA3, 0xFB, 0x36, 0x7C, 0x2D,
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+	0xF0, 0x1F, 0xCA, 0x8F, 0x83, 0xFF, 0x00, 0xE2, 0x1D, 0x5F, 0xD8, 0x13, 0xA1, 0x87, 0xC4, 0x9F,
+	0xF8, 0x1C, 0x3F, 0xF8, 0x9A, 0x3F, 0xE2, 0x1D, 0x4F, 0xD8, 0x1C, 0x72, 0x60, 0xF1, 0x16, 0x3F,
+	0xEB, 0xF8, 0x7F, 0xF1, 0x35, 0xF7, 0x84, 0x77, 0x76, 0xD2, 0x1D, 0xA9, 0x3C, 0x6C, 0x7A, 0x32,
+	0xAB, 0x29, 0xC1, 0xFC, 0xEA, 0x47, 0x65, 0x5C, 0x02, 0x83, 0xA7, 0xA5, 0x5F, 0xF6, 0xC6, 0x69,
+	0x17, 0x65, 0x55, 0xEA, 0x1F, 0xD9, 0xB8, 0x19, 0x7F, 0xCB, 0xB4, 0x7C, 0x16, 0xBF, 0xF0, 0x6E,
+	0xB7, 0xEC, 0x08, 0x7E, 0x6F, 0x2F, 0xC4, 0x5B, 0x7F, 0xEB, 0xFB, 0xFF, 0x00, 0xB1, 0xA0, 0xFF,
+	0x00, 0xC1, 0xBA, 0xFF, 0x00, 0xB0, 0x28, 0x70, 0xDE, 0x4F, 0x88, 0xB8, 0x39, 0xFF, 0x00, 0x8F,
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+	0x78, 0x86, 0x94, 0x23, 0x9C, 0xD7, 0x8D, 0x25, 0x65, 0x7D, 0x0F, 0xA8, 0xC1, 0xCB, 0xFD, 0x92,
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+	0xC1, 0xE0, 0x30, 0xA1, 0x9C, 0x2F, 0x53, 0x54, 0xDB, 0x51, 0xD3, 0x51, 0x48, 0x3A, 0x95, 0xBA,
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+	0x25, 0xE4, 0x32, 0xB6, 0xE8, 0xE7, 0x8D, 0x97, 0xF8, 0x76, 0xB6, 0x7F, 0x95, 0x7E, 0x54, 0xA9,
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+	0xE5, 0xD0, 0x04, 0x2A, 0xC4, 0x6E, 0xA5, 0xDC, 0xC4, 0x63, 0x15, 0x1F, 0x99, 0xBA, 0x4F, 0x2D,
+	0x89, 0xFC, 0x29, 0xC1, 0x76, 0xBF, 0xDE, 0xA2, 0xDE, 0xE8, 0x00, 0xC1, 0x5C, 0xE6, 0x81, 0xEF,
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+	0xE5, 0x39, 0xA1, 0xD8, 0x12, 0xB8, 0x3F, 0x8D, 0x31, 0xB3, 0xE6, 0x6D, 0x0D, 0xF2, 0xD5, 0x2B,
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+	0x69, 0xD4, 0x8D, 0xE1, 0xB8, 0x68, 0xDC, 0x2B, 0x0F, 0x30, 0xA9, 0xD8, 0x7B, 0x0A, 0xFC, 0x35,
+	0xFF, 0x00, 0x82, 0xB3, 0x7E, 0xD9, 0x7F, 0xF0, 0x50, 0x4F, 0xD9, 0x1F, 0xF6, 0xAE, 0xD6, 0xF4,
+	0x6B, 0x4F, 0x8B, 0x36, 0xE3, 0x42, 0xD5, 0x2E, 0x8B, 0x68, 0xB1, 0x25, 0xA9, 0x50, 0xB1, 0x81,
+	0xD3, 0xDF, 0x9A, 0xFD, 0xD0, 0xDC, 0xBB, 0x76, 0x86, 0xC0, 0xAF, 0xCD, 0x7F, 0xF8, 0x38, 0xAB,
+	0xF6, 0x3F, 0x1F, 0x18, 0x3F, 0x67, 0x98, 0xBF, 0x68, 0x7D, 0x12, 0xD5, 0x1E, 0xF3, 0xC1, 0x30,
+	0xB9, 0x91, 0x23, 0x5F, 0xDE, 0x4A, 0xB2, 0x38, 0xFC, 0xF1, 0x5E, 0xEF, 0x0E, 0xD4, 0xC1, 0xAC,
+	0xD2, 0x1E, 0xDD, 0x5E, 0x32, 0xD0, 0xF3, 0xF3, 0x0A, 0x75, 0x27, 0x47, 0xF7, 0x7B, 0xA3, 0xF3,
+	0x9F, 0xE0, 0x3F, 0xFC, 0x16, 0x2B, 0xF6, 0xD0, 0xB1, 0xF8, 0xE9, 0xE1, 0x3B, 0x8F, 0x1B, 0xFC,
+	0x4E, 0xB7, 0x6D, 0x05, 0x75, 0x68, 0x8E, 0xA8, 0xAD, 0x0E, 0x33, 0x1F, 0x1B, 0xB9, 0xFA, 0x66,
+	0xBF, 0xA1, 0xCF, 0x85, 0xFE, 0x33, 0xB5, 0xF8, 0x93, 0xF0, 0xFB, 0x46, 0xF1, 0xE6, 0x9D, 0x3A,
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+	0x5D, 0x4B, 0x6D, 0xE5, 0x12, 0x55, 0x9B, 0xFD, 0x67, 0xF0, 0x94, 0xE7, 0x9E, 0xB5, 0xFD, 0x0E,
+	0xFF, 0x00, 0xC1, 0x04, 0xBF, 0x6A, 0x89, 0x3F, 0x68, 0xAF, 0xD8, 0xEE, 0x3D, 0x02, 0xEE, 0xEB,
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+	0xD2, 0xC7, 0x56, 0xC4, 0x63, 0xB2, 0x98, 0xCA, 0x1F, 0x33, 0xE2, 0xF5, 0xB7, 0xF2, 0xD4, 0x5B,
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+	0xC0, 0x7D, 0x73, 0xFE, 0x0A, 0x67, 0xF1, 0xE7, 0xF6, 0x8D, 0x5F, 0x0E, 0xDE, 0x26, 0x87, 0x25,
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+	0x5F, 0x55, 0x60, 0x41, 0xFD, 0x0D, 0x71, 0xE3, 0xB0, 0xFF, 0x00, 0x59, 0xC3, 0xB8, 0xFC, 0xD7,
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+	0x13, 0x47, 0x51, 0xF8, 0xE9, 0xE0, 0xDF, 0x88, 0xBE, 0x25, 0x9F, 0x4A, 0xBA, 0xBC, 0xB4, 0x10,
+	0x59, 0x5B, 0xC2, 0xD9, 0x0C, 0xC1, 0xD8, 0x71, 0xF5, 0x06, 0xB9, 0xBF, 0x84, 0x5F, 0xF0, 0x4D,
+	0xFD, 0x37, 0xF6, 0xB6, 0xFD, 0x84, 0x3E, 0x23, 0x7E, 0xDB, 0x57, 0x7F, 0x6C, 0x93, 0x57, 0x5F,
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+	0xBD, 0x4B, 0x4D, 0xF2, 0xFC, 0xB9, 0x01, 0x19, 0x63, 0xCB, 0x0E, 0x87, 0xAF, 0x15, 0xFA, 0xFB,
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+	0xFD, 0x94, 0xFE, 0x26, 0x68, 0x5F, 0x66, 0xD6, 0xFC, 0x49, 0xA4, 0xDD, 0x35, 0xE5, 0x8D, 0xC2,
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+	0x24, 0xD5, 0xFF, 0x00, 0x53, 0xF1, 0x93, 0xFE, 0x1E, 0x9D, 0x6D, 0xE2, 0xCF, 0xF8, 0x21, 0x96,
+	0xB9, 0xFB, 0x18, 0xCD, 0xE2, 0x19, 0xAD, 0xFC, 0x45, 0xA0, 0xDD, 0x58, 0x58, 0xE9, 0x76, 0xEA,
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+	0xFC, 0x15, 0x13, 0x4D, 0xFD, 0xA4, 0xEE, 0xB4, 0x7D, 0x03, 0xF6, 0x4C, 0xF1, 0x15, 0xD7, 0x84,
+	0xE1, 0xF1, 0x14, 0x66, 0x1D, 0x73, 0x74, 0x62, 0xDE, 0x5B, 0x61, 0x27, 0xDE, 0xFB, 0xD9, 0x38,
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+	0xD6, 0x8F, 0x33, 0x43, 0xA4, 0xDD, 0xDD, 0xD8, 0xEA, 0x17, 0x97, 0x51, 0xB0, 0x05, 0x24, 0x17,
+	0x21, 0xDC, 0x71, 0x8E, 0xC2, 0xB2, 0xBF, 0x6B, 0xAF, 0x8C, 0xBE, 0x11, 0xFF, 0x00, 0x82, 0xCF,
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+	0x09, 0xA4, 0x65, 0xDC, 0xA1, 0x84, 0x5E, 0x9C, 0xF3, 0x91, 0x5F, 0xA5, 0x1F, 0xF0, 0x73, 0x1F,
+	0xFC, 0x13, 0x77, 0xE2, 0xEF, 0xED, 0xA5, 0xFB, 0x37, 0x69, 0xBE, 0x29, 0xFD, 0x9B, 0x3E, 0x15,
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+	0x18, 0xD8, 0xFF, 0x00, 0x6C, 0x2A, 0x6E, 0xBB, 0x2E, 0x87, 0x25, 0x70, 0xC7, 0x18, 0xAE, 0x3C,
+	0x96, 0x8D, 0x3F, 0x6D, 0xC9, 0x88, 0x7E, 0xED, 0x3B, 0xB8, 0xFE, 0x87, 0x5E, 0x75, 0x5A, 0x12,
+	0xC2, 0xC2, 0xAD, 0x05, 0x7A, 0x92, 0xB2, 0x97, 0xE5, 0xA1, 0xF3, 0xBF, 0xEC, 0x99, 0xF1, 0x2E,
+	0xC3, 0xFE, 0x08, 0x7D, 0xFF, 0x00, 0x05, 0x5F, 0xD4, 0x3C, 0x19, 0xA8, 0x5E, 0x5D, 0x5B, 0xE8,
+	0xDA, 0xB4, 0x30, 0xDA, 0x5E, 0x4D, 0x34, 0x7B, 0x36, 0x42, 0xCC, 0x70, 0x08, 0xE3, 0x8C, 0x83,
+	0x5A, 0x9F, 0xF0, 0x4E, 0xEF, 0x86, 0xF7, 0x5F, 0xF0, 0x50, 0xFF, 0x00, 0xF8, 0x2F, 0x7F, 0x89,
+	0xBE, 0x21, 0xFD, 0xA2, 0x4B, 0xFF, 0x00, 0x0F, 0xC7, 0xAD, 0xDF, 0x6A, 0x36, 0x77, 0xB2, 0x7C,
+	0xCA, 0x23, 0x46, 0x56, 0x8C, 0x0E, 0xDD, 0xAB, 0xE9, 0xBF, 0xF8, 0x39, 0x63, 0xFE, 0x08, 0xDB,
+	0xFB, 0x5C, 0x7E, 0xD4, 0x5F, 0xB4, 0xC5, 0x9F, 0xED, 0x0D, 0xFB, 0x24, 0xFC, 0x0E, 0xD5, 0x3C,
+	0x5D, 0x3E, 0xA5, 0x6B, 0x05, 0xAE, 0xA1, 0x6F, 0xA3, 0x84, 0x0F, 0x06, 0xC4, 0x3F, 0x31, 0xDC,
+	0xC3, 0xB9, 0xF5, 0xAF, 0x75, 0xFF, 0x00, 0x83, 0x61, 0xBF, 0xE0, 0x97, 0xBF, 0x1C, 0xFF, 0x00,
+	0x62, 0xFF, 0x00, 0x01, 0xF8, 0xA3, 0xC7, 0x7F, 0xB5, 0x4F, 0xC2, 0x3B, 0xDF, 0x0A, 0xF8, 0xBA,
+	0xEB, 0x53, 0x09, 0xA6, 0xDB, 0xEA, 0x1B, 0x7C, 0xCF, 0x20, 0xA7, 0xCC, 0x72, 0x09, 0xFE, 0x75,
+	0xDD, 0x95, 0xE2, 0x69, 0xD5, 0x53, 0xC4, 0xD6, 0x56, 0x9C, 0x6F, 0xCB, 0x73, 0x1C, 0xDE, 0x94,
+	0x23, 0x18, 0xD3, 0xA0, 0xEE, 0xA6, 0xA3, 0xCD, 0xF2, 0xDF, 0xEE, 0x3D, 0xDB, 0xFE, 0x0E, 0x1B,
+	0xFD, 0x97, 0x24, 0xF8, 0xF7, 0xFF, 0x00, 0x04, 0xDB, 0xF1, 0x85, 0xC6, 0x94, 0x8A, 0xFA, 0x97,
+	0x87, 0x74, 0xAF, 0x37, 0x4F, 0x46, 0xC0, 0x0D, 0x82, 0xA3, 0xB8, 0xE3, 0x8A, 0xFC, 0x4C, 0xFD,
+	0x91, 0xBF, 0xE0, 0xA4, 0x3A, 0x77, 0xEC, 0xE1, 0xFF, 0x00, 0x04, 0x88, 0xF1, 0xA7, 0xEC, 0xA9,
+	0xA9, 0xF8, 0xBA, 0xEA, 0x3D, 0x7F, 0x55, 0xD6, 0x2F, 0xA0, 0x8A, 0xC6, 0x36, 0xCE, 0xD5, 0x92,
+	0x32, 0xA0, 0x7D, 0x0F, 0x35, 0xFD, 0x42, 0x7C, 0x70, 0xF8, 0x53, 0xA0, 0x7C, 0x6A, 0xF8, 0x57,
+	0xAD, 0xFC, 0x2F, 0xF1, 0x2C, 0x2B, 0x25, 0x9E, 0xAF, 0x62, 0xD0, 0x4C, 0xAD, 0xD0, 0x82, 0x38,
+	0x1F, 0x9D, 0x7F, 0x2B, 0x1E, 0x36, 0xFF, 0x00, 0x83, 0x7E, 0xFF, 0x00, 0xE0, 0xA9, 0x57, 0xDF,
+	0xB5, 0x76, 0xA3, 0x69, 0xA4, 0xFE, 0xC8, 0xDE, 0x24, 0x6F, 0x09, 0xCD, 0xE3, 0x29, 0x85, 0xAE,
+	0xB1, 0xFB, 0xB1, 0x6E, 0x2C, 0xCC, 0xEC, 0x04, 0xBF, 0x7B, 0x38, 0x08, 0x73, 0xD3, 0xA5, 0x79,
+	0x18, 0x7A, 0x7F, 0xED, 0xCE, 0x94, 0xDF, 0xEE, 0xE6, 0xD3, 0x7E, 0x6E, 0xFA, 0xFD, 0xC7, 0x75,
+	0x4A, 0x94, 0x65, 0x94, 0xEB, 0xFC, 0x48, 0x7C, 0x3E, 0x86, 0x6F, 0xC7, 0x2F, 0xF8, 0x26, 0x66,
+	0x99, 0xF0, 0x6B, 0xFE, 0x09, 0xD1, 0xF0, 0xD3, 0xF6, 0xDC, 0xD2, 0x21, 0xBB, 0x8F, 0x50, 0xBA,
+	0xB5, 0xB5, 0xBC, 0xBE, 0xDF, 0x6E, 0x42, 0xB3, 0x99, 0x41, 0x04, 0xB6, 0x3D, 0x45, 0x77, 0xBF,
+	0xF0, 0x55, 0xFF, 0x00, 0xF8, 0x29, 0x72, 0xFE, 0xDF, 0x3F, 0xB0, 0x57, 0xC1, 0x1F, 0x87, 0xDE,
+	0x1C, 0xD4, 0xA6, 0x97, 0x5E, 0xD3, 0xF5, 0x29, 0xAD, 0xB5, 0x6D, 0x36, 0x33, 0x97, 0xDA, 0xB1,
+	0x05, 0x4C, 0x8E, 0xF9, 0xC5, 0x7E, 0xD7, 0x7E, 0xD5, 0x3F, 0xF0, 0x4D, 0x8F, 0x10, 0xFC, 0x52,
+	0xFF, 0x00, 0x82, 0x38, 0xD8, 0xFE, 0xC4, 0x9A, 0x4E, 0x8D, 0xF6, 0xAD, 0x77, 0x49, 0xD1, 0x2D,
+	0xE3, 0xB5, 0x8D, 0x54, 0x6E, 0x33, 0xC4, 0x77, 0x60, 0x7D, 0x4F, 0x1E, 0x99, 0xAF, 0xC5, 0x2F,
+	0xF8, 0x27, 0x77, 0xFC, 0x10, 0x33, 0xFE, 0x0A, 0x47, 0xA3, 0xFE, 0xDB, 0x3E, 0x0B, 0xD6, 0x7E,
+	0x3C, 0xFE, 0xC9, 0xFE, 0x20, 0xD1, 0x7C, 0x0F, 0xA7, 0xF8, 0x91, 0x65, 0xD5, 0xB5, 0x2D, 0x4B,
+	0xCB, 0x30, 0x0B, 0x71, 0xFC, 0x5C, 0x39, 0xE0, 0xE3, 0xD3, 0xA5, 0x7A, 0xB4, 0xEA, 0x61, 0xF1,
+	0x19, 0xC4, 0xE8, 0xD4, 0x8F, 0xEE, 0xD5, 0xAD, 0xDA, 0xDD, 0x3E, 0x67, 0x0D, 0xA3, 0x1C, 0xA2,
+	0x96, 0x22, 0x1F, 0xC5, 0x5C, 0xD7, 0xF9, 0x9F, 0xBD, 0xDF, 0xF0, 0x46, 0x2F, 0xD9, 0x9E, 0xC7,
+	0xF6, 0x5F, 0xFD, 0x84, 0x3C, 0x13, 0xA1, 0xA1, 0xF2, 0xE5, 0xD5, 0x34, 0x5B, 0x6D, 0x46, 0xFC,
+	0x49, 0xF2, 0xEC, 0x95, 0xE3, 0x1B, 0x81, 0xF4, 0xE9, 0x5F, 0x4A, 0x41, 0xF1, 0x5B, 0xE1, 0x8D,
+	0xE6, 0xBB, 0xFF, 0x00, 0x08, 0xCD, 0xB7, 0xC4, 0x6F, 0x0F, 0xCD, 0xA8, 0x86, 0xC7, 0xD8, 0x23,
+	0xD6, 0x20, 0x33, 0x0F, 0x51, 0xE5, 0xEF, 0xDD, 0x9C, 0xFF, 0x00, 0xB3, 0x54, 0xF5, 0xAF, 0x07,
+	0xCB, 0xA5, 0x7C, 0x20, 0x9F, 0xC0, 0xBE, 0x0F, 0x41, 0x01, 0x83, 0x45, 0x7B, 0x3D, 0x3F, 0x6A,
+	0xF4, 0x22, 0x3D, 0xA9, 0xC7, 0xD6, 0xBF, 0x9F, 0xBF, 0xD9, 0xD3, 0xFE, 0x09, 0x45, 0xFF, 0x00,
+	0x05, 0x47, 0xF0, 0xAF, 0xFC, 0x16, 0x96, 0xDF, 0xE3, 0xD7, 0x8B, 0x3E, 0x0A, 0xF8, 0xA6, 0xDF,
+	0xC2, 0x29, 0xE2, 0x39, 0x6E, 0x64, 0xF1, 0x84, 0x97, 0x41, 0xAD, 0x5A, 0x06, 0x43, 0xB4, 0x7D,
+	0xFC, 0xE0, 0x1E, 0x76, 0xED, 0xC7, 0x15, 0xC9, 0x1A, 0xD3, 0xC7, 0x67, 0x4E, 0x84, 0xD7, 0x2C,
+	0x56, 0xD2, 0xE8, 0x63, 0x46, 0x8C, 0x70, 0xD9, 0x7B, 0xA9, 0x7B, 0xCB, 0x7B, 0x77, 0x3F, 0x6D,
+	0xFF, 0x00, 0xE0, 0xA4, 0x7F, 0x02, 0xF4, 0x1F, 0x8F, 0x9F, 0xB2, 0x2F, 0x8C, 0x3C, 0x3D, 0xAA,
+	0x5A, 0x2C, 0xB7, 0x16, 0xBA, 0x34, 0xD3, 0xE9, 0xB2, 0x2A, 0xE4, 0xA4, 0xC1, 0x4F, 0x4A, 0xFE,
+	0x61, 0xB5, 0x6D, 0x12, 0xF3, 0xC2, 0xBA, 0xDD, 0xE7, 0x85, 0xEF, 0xD1, 0x96, 0x4D, 0x3E, 0x63,
+	0x0C, 0xDC, 0x60, 0x86, 0x1B, 0x85, 0x7F, 0x5C, 0x31, 0x68, 0x31, 0xEA, 0x5E, 0x19, 0xFE, 0xC0,
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+	0x48, 0xD3, 0x6A, 0x22, 0xAB, 0x7F, 0x7A, 0x91, 0xB5, 0x6D, 0xDC, 0x7F, 0x15, 0x00, 0x77, 0xBF,
+	0xF0, 0xB0, 0x6D, 0x7F, 0xE8, 0x19, 0x25, 0x1F, 0xF0, 0xB0, 0x6D, 0x7F, 0xE8, 0x19, 0x25, 0x70,
+	0x6B, 0xAC, 0x3A, 0xFF, 0x00, 0x1D, 0x1F, 0xDA, 0xCF, 0xBB, 0xEF, 0xD0, 0x07, 0x79, 0xFF, 0x00,
+	0x0B, 0x06, 0xD7, 0xFE, 0x81, 0x92, 0x51, 0xFF, 0x00, 0x0B, 0x06, 0xD7, 0xFE, 0x81, 0x92, 0x57,
+	0x0B, 0x1E, 0xA5, 0x79, 0x33, 0x24, 0x36, 0xB6, 0xD2, 0x4D, 0x23, 0x7F, 0x0C, 0x7F, 0xC5, 0x4D,
+	0x93, 0x58, 0x78, 0xCB, 0x23, 0xBF, 0xCC, 0xBF, 0x2B, 0x2F, 0xF7, 0x5A, 0x80, 0x3B, 0xCF, 0xF8,
+	0x58, 0x36, 0xBF, 0xF4, 0x0C, 0x92, 0x8F, 0xF8, 0x58, 0x36, 0xBF, 0xF4, 0x0C, 0x92, 0xB8, 0x3F,
+	0xED, 0x97, 0xDB, 0xBF, 0x7D, 0x1F, 0xDB, 0x0E, 0xDC, 0x6F, 0xF9, 0xA8, 0x03, 0xBA, 0x8F, 0xE2,
+	0x25, 0x9B, 0xBE, 0x7E, 0xC0, 0xDB, 0x7F, 0xBD, 0x5A, 0x36, 0x3E, 0x2C, 0xD0, 0xAF, 0xDB, 0x64,
+	0x3A, 0x82, 0xAC, 0x9F, 0xDD, 0x6A, 0xF3, 0x46, 0xD5, 0xB7, 0x37, 0xF7, 0x7F, 0xD9, 0xA8, 0xFE,
+	0xD9, 0x0A, 0xC9, 0xE7, 0xA7, 0xC8, 0xDF, 0xDE, 0x5A, 0x00, 0xF6, 0x18, 0xE4, 0x47, 0x5C, 0xC4,
+	0xF9, 0xA5, 0x5D, 0xFF, 0x00, 0xC5, 0x5C, 0x2F, 0x80, 0x3C, 0x71, 0x24, 0xB7, 0xFF, 0x00, 0xD9,
+	0x5A, 0xAD, 0xC2, 0xAA, 0x32, 0xFE, 0xE5, 0x9B, 0xF8, 0xAB, 0xB8, 0xDC, 0xF8, 0xC6, 0x3E, 0x7A,
+	0x00, 0x7A, 0x7D, 0xDA, 0x5A, 0x44, 0xFB, 0xB4, 0xB4, 0x00, 0x51, 0x45, 0x01, 0x81, 0xE9, 0x40,
+	0x0C, 0x91, 0xC2, 0x32, 0xE5, 0xF1, 0x55, 0xAF, 0xB5, 0x9B, 0x0D, 0x35, 0x37, 0xDE, 0x4C, 0xB1,
+	0xD6, 0x5F, 0x8E, 0x7C, 0x5B, 0x6D, 0xE1, 0x9B, 0x25, 0x51, 0xB4, 0xDC, 0x4D, 0xF2, 0xC1, 0xED,
+	0x5E, 0x41, 0xF1, 0x17, 0xE3, 0x77, 0xC3, 0x1F, 0x85, 0xF6, 0x70, 0xF8, 0x93, 0xE3, 0xAF, 0xC5,
+	0x9D, 0x1F, 0xC2, 0x76, 0x37, 0x52, 0xEC, 0xB5, 0xBE, 0xF1, 0x05, 0xD2, 0xC5, 0x04, 0xD2, 0x7F,
+	0x75, 0x59, 0xA8, 0x03, 0xD8, 0x6E, 0x3C, 0x71, 0x61, 0x0C, 0x7E, 0x74, 0x50, 0xB4, 0x8B, 0xFD,
+	0xE5, 0xA8, 0x7F, 0xE1, 0x60, 0xDB, 0x7F, 0xD0, 0x3D, 0xAB, 0xE7, 0xF6, 0xFD, 0xB7, 0xBF, 0x62,
+	0x76, 0x6D, 0xFF, 0x00, 0xF0, 0xDA, 0x5F, 0x0F, 0xD1, 0x57, 0xEF, 0x46, 0xBA, 0xB4, 0x7F, 0xFC,
+	0x55, 0x37, 0xFE, 0x1B, 0x7B, 0xF6, 0x21, 0x5F, 0xF9, 0xBD, 0x5F, 0x87, 0xFF, 0x00, 0xF8, 0x36,
+	0x8F, 0xFF, 0x00, 0x8A, 0xA0, 0x0F, 0xA0, 0xBF, 0xE1, 0x60, 0xDA, 0xFF, 0x00, 0xD0, 0x32, 0x4A,
+	0x3F, 0xE1, 0x60, 0xDA, 0xFF, 0x00, 0xD0, 0x32, 0x4A, 0xF9, 0xFF, 0x00, 0xFE, 0x1B, 0x83, 0xF6,
+	0x25, 0xFF, 0x00, 0xA3, 0xD5, 0xF8, 0x7F, 0xFF, 0x00, 0x83, 0x68, 0xFF, 0x00, 0xF8, 0xAA, 0x3F,
+	0xE1, 0xB8, 0x3F, 0x62, 0x5F, 0xFA, 0x3D, 0x5F, 0x87, 0xFF, 0x00, 0xF8, 0x36, 0x8F, 0xFF, 0x00,
+	0x8A, 0xA0, 0x0F, 0xA0, 0x3F, 0xE1, 0x60, 0xDA, 0xFF, 0x00, 0xD0, 0x32, 0x4A, 0x3F, 0xE1, 0x60,
+	0xDA, 0xFF, 0x00, 0xD0, 0x32, 0x4A, 0xF9, 0xFF, 0x00, 0xFE, 0x1B, 0x8B, 0xF6, 0x24, 0x55, 0xFF,
+	0x00, 0x93, 0xD2, 0xF8, 0x7F, 0xFF, 0x00, 0x83, 0x68, 0xFF, 0x00, 0xF8, 0xAA, 0x1B, 0xF6, 0xE2,
+	0xFD, 0x89, 0xD5, 0x55, 0xFF, 0x00, 0xE1, 0xB5, 0xBE, 0x1F, 0xAA, 0xB7, 0xCD, 0xFF, 0x00, 0x21,
+	0x68, 0xFE, 0x5F, 0xFC, 0x7A, 0x80, 0x3E, 0x80, 0xFF, 0x00, 0x85, 0x83, 0x6B, 0xFF, 0x00, 0x40,
+	0xC9, 0x28, 0x9B, 0xE2, 0x0D, 0xBC, 0x63, 0x29, 0xA7, 0x3C, 0x9F, 0xEE, 0xD7, 0x98, 0xF8, 0x4B,
+	0xE2, 0x77, 0x82, 0xBE, 0x20, 0xF8, 0x72, 0x1F, 0x1A, 0x7C, 0x37, 0xF1, 0xDE, 0x9F, 0xE2, 0x4D,
+	0x12, 0xE1, 0xB6, 0xDA, 0xEB, 0x5A, 0x3D, 0xC7, 0x99, 0x6F, 0x23, 0x7F, 0x12, 0xAB, 0x2D, 0x69,
+	0x0D, 0x61, 0xC7, 0xF1, 0xD0, 0x07, 0xA0, 0x58, 0xF8, 0xF7, 0x4D, 0x98, 0xE2, 0xF6, 0x26, 0xB7,
+	0xFF, 0x00, 0x7A, 0xB5, 0x2C, 0xF5, 0x9D, 0x37, 0x52, 0xE2, 0xCE, 0xE1, 0x5E, 0xBC, 0xAE, 0x4B,
+	0xC4, 0x9F, 0xFD, 0x73, 0x6E, 0xA4, 0xB5, 0xD7, 0xAE, 0x74, 0x76, 0x6B, 0x9B, 0x49, 0xB6, 0xB2,
+	0xB7, 0xCA, 0xBF, 0xC3, 0x40, 0x1E, 0xBC, 0x55, 0x25, 0x1F, 0x3F, 0xF0, 0xD3, 0x93, 0xEE, 0xD6,
+	0x37, 0x84, 0x7C, 0x4D, 0x17, 0x89, 0xB4, 0xA4, 0x99, 0x5D, 0x7C, 0xE5, 0xFF, 0x00, 0x5E, 0xBF,
+	0xDD, 0xAD, 0x94, 0xFB, 0xB4, 0x00, 0xB4, 0x51, 0x45, 0x00, 0x14, 0x8C, 0xDB, 0x7B, 0x52, 0xD2,
+	0x30, 0xDC, 0x31, 0x40, 0x0C, 0x79, 0x39, 0xFB, 0x9F, 0x2F, 0xF7, 0xAB, 0x36, 0xEF, 0xC5, 0x5A,
+	0x25, 0xAC, 0x9F, 0x66, 0x4B, 0x95, 0x92, 0x4F, 0xEE, 0xAD, 0x72, 0x1E, 0x35, 0xF1, 0xDC, 0xD7,
+	0xBA, 0x83, 0xE9, 0xBA, 0x53, 0xB2, 0x5B, 0xDB, 0xB6, 0xCB, 0x86, 0x5F, 0xE2, 0x6A, 0xC3, 0x87,
+	0x52, 0xFB, 0x3E, 0xE4, 0x7F, 0x98, 0xB7, 0xDD, 0x93, 0xF8, 0xA8, 0x03, 0xBF, 0xB8, 0xF8, 0x83,
+	0x69, 0x0B, 0x6C, 0xFB, 0x1B, 0x35, 0x0B, 0xF1, 0x06, 0xCD, 0x97, 0xE4, 0xB4, 0x6A, 0xE0, 0xFF,
+	0x00, 0xB5, 0x1C, 0xFD, 0xF3, 0x4D, 0x3A, 0xA6, 0xDA, 0x00, 0xEF, 0x3F, 0xE1, 0x60, 0xDA, 0xFF,
+	0x00, 0xD0, 0x32, 0x4A, 0x3F, 0xE1, 0x60, 0xDA, 0xFF, 0x00, 0xD0, 0x32, 0x4A, 0xE0, 0xFF, 0x00,
+	0xB5, 0xDF, 0xFB, 0xED, 0xFF, 0x00, 0x7D, 0x51, 0xFD, 0xAE, 0xFF, 0x00, 0xDF, 0x6F, 0xFB, 0xEA,
+	0x80, 0x3B, 0xCF, 0xF8, 0x58, 0x36, 0xBF, 0xF4, 0x0C, 0x92, 0x8F, 0xF8, 0x58, 0x36, 0xBF, 0xF4,
+	0x0C, 0x92, 0xB8, 0x3F, 0xED, 0xB6, 0xFE, 0xFB, 0x51, 0xFD, 0xB8, 0xFE, 0xAD, 0x40, 0x1D, 0xF7,
+	0xFC, 0x27, 0xF6, 0x7B, 0x7E, 0x7B, 0x16, 0xA6, 0x7F, 0xC2, 0xC4, 0xB6, 0xDD, 0xFF, 0x00, 0x1E,
+	0x0D, 0x5C, 0x21, 0xD6, 0x37, 0x51, 0xFD, 0xAD, 0xEF, 0x40, 0x1E, 0x8D, 0x67, 0xE3, 0x2D, 0x06,
+	0xE7, 0x6F, 0x9D, 0x2F, 0x92, 0xED, 0xFC, 0x2D, 0x5A, 0xCB, 0x22, 0x4F, 0x18, 0x78, 0x65, 0x56,
+	0x5F, 0xEF, 0x57, 0x8F, 0xC9, 0x78, 0x92, 0x2E, 0xFD, 0x9F, 0x37, 0xF7, 0xAB, 0x5B, 0xC2, 0xBE,
+	0x38, 0xB9, 0xD3, 0x35, 0x48, 0xED, 0x66, 0xB9, 0xDD, 0x6C, 0xDF, 0x7B, 0x77, 0xF0, 0xD0, 0x07,
+	0xA6, 0x29, 0x66, 0xFB, 0xCB, 0x4E, 0xA8, 0xED, 0xE5, 0x17, 0x08, 0xB3, 0x23, 0x6E, 0x56, 0xE5,
+	0x6A, 0x4A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x08, 0x0D, 0xD6, 0x93, 0x24, 0x8F, 0x94, 0xD0, 0xFF,
+	0x00, 0x76, 0xB3, 0xBC, 0x41, 0xAF, 0x5A, 0xF8, 0x6B, 0x4B, 0x93, 0x55, 0xBC, 0x1F, 0xBA, 0x8F,
+	0xF8, 0x57, 0xEF, 0x6E, 0xA0, 0x0B, 0x57, 0x77, 0xF6, 0x76, 0x31, 0xB4, 0xD7, 0x77, 0x2A, 0x8A,
+	0xBF, 0x7B, 0x75, 0x66, 0xDD, 0x78, 0xDB, 0x4A, 0x8D, 0x77, 0xDB, 0x7E, 0xFB, 0xFD, 0xDA, 0xF3,
+	0xBD, 0x4B, 0xC5, 0x1A, 0x96, 0xB9, 0x70, 0xB7, 0x97, 0xEF, 0xB5, 0x77, 0x7C, 0xB1, 0xAF, 0xDD,
+	0xDB, 0x47, 0xF6, 0xC6, 0xD5, 0xF9, 0x11, 0x54, 0x50, 0x07, 0x72, 0xBF, 0x10, 0xEC, 0xD9, 0xBE,
+	0x7D, 0x39, 0xA9, 0x7F, 0xE1, 0x60, 0xDA, 0xFF, 0x00, 0xD0, 0x32, 0x4A, 0xE1, 0x17, 0x54, 0x7D,
+	0xD4, 0x8D, 0xAC, 0xBF, 0xDC, 0x42, 0xCD, 0x27, 0xF7, 0x56, 0x80, 0x3B, 0xCF, 0xF8, 0x58, 0x36,
+	0xBF, 0xF4, 0x0C, 0x92, 0x8F, 0xF8, 0x58, 0x36, 0xBF, 0xF4, 0x0C, 0x92, 0xB8, 0x2F, 0xED, 0xCD,
+	0xE3, 0x7F, 0xCC, 0xA2, 0x91, 0xBC, 0x44, 0xAB, 0x23, 0x27, 0x9D, 0xFF, 0x00, 0x8F, 0x50, 0x07,
+	0x7D, 0xFF, 0x00, 0x0B, 0x06, 0xD7, 0xFE, 0x81, 0x92, 0x51, 0xFF, 0x00, 0x0B, 0x06, 0xD7, 0xFE,
+	0x81, 0x92, 0x57, 0x04, 0xBA, 0xF2, 0x48, 0xBF, 0x24, 0xDF, 0xEF, 0xAE, 0xEA, 0x23, 0xD6, 0x9E,
+	0x4F, 0xB9, 0xB9, 0x7F, 0xDE, 0xA0, 0x0E, 0xF5, 0xBE, 0x21, 0x5B, 0x9F, 0xF9, 0x86, 0xC9, 0x4E,
+	0xB7, 0xF1, 0xF5, 0x84, 0xD2, 0x6C, 0xB8, 0xB4, 0x68, 0xE3, 0xFF, 0x00, 0x9E, 0x8D, 0x5C, 0x0B,
+	0x6B, 0x0F, 0xFC, 0x6F, 0xBD, 0x57, 0xEF, 0x2A, 0xFF, 0x00, 0x0D, 0x35, 0xB5, 0x27, 0xDD, 0xF3,
+	0xC9, 0xB9, 0x5B, 0xF8, 0x68, 0x03, 0xD4, 0xB4, 0xFF, 0x00, 0x10, 0x68, 0xB7, 0xCD, 0xB2, 0xCE,
+	0xFD, 0x5B, 0xFD, 0x9A, 0xBC, 0xBD, 0xFE, 0x5D, 0xB5, 0xE3, 0xAB, 0xAA, 0x79, 0x13, 0x2C, 0xD6,
+	0x7F, 0xBA, 0x65, 0xFE, 0xED, 0x77, 0x1E, 0x00, 0xF1, 0x9C, 0xBA, 0xF4, 0x32, 0x58, 0xDE, 0x32,
+	0xF9, 0xEB, 0xFE, 0xAB, 0xFD, 0xA5, 0xA0, 0x0E, 0xB2, 0x8A, 0x4D, 0xDD, 0x28, 0x56, 0xDD, 0xDA,
+	0x80, 0x16, 0x8A, 0x29, 0x19, 0xB6, 0x8C, 0xD0, 0x02, 0xD3, 0x77, 0x3E, 0xEC, 0x52, 0x34, 0x98,
+	0x65, 0x46, 0x5F, 0xBD, 0x5C, 0x87, 0x8F, 0xFC, 0x6F, 0x36, 0x99, 0x21, 0xF0, 0xFE, 0x95, 0xB7,
+	0xED, 0x4C, 0x9B, 0xA6, 0x7F, 0xEE, 0xC7, 0xED, 0x40, 0x1D, 0x1D, 0xFF, 0x00, 0x88, 0xF4, 0x7D,
+	0x36, 0x4F, 0x26, 0xF2, 0xF9, 0x51, 0xFF, 0x00, 0xBB, 0x59, 0x97, 0xDE, 0x3C, 0xB3, 0xB7, 0xE3,
+	0xEC, 0x8D, 0x22, 0xFF, 0x00, 0x79, 0x6B, 0xCF, 0xE3, 0xD4, 0x93, 0x3B, 0xE6, 0xFD, 0xF7, 0xFB,
+	0x52, 0x7D, 0xEA, 0x73, 0x6A, 0xDD, 0xFF, 0x00, 0xF1, 0xDA, 0x00, 0xEF, 0x17, 0xE2, 0x25, 0xB3,
+	0x0C, 0xFF, 0x00, 0x67, 0x49, 0x47, 0xFC, 0x2C, 0x1B, 0x5F, 0xFA, 0x06, 0x49, 0x5C, 0x12, 0xEA,
+	0x9B, 0x5B, 0xEF, 0xD2, 0xB6, 0xB0, 0xED, 0xFC, 0x74, 0x01, 0xDE, 0x7F, 0xC2, 0xC1, 0xB5, 0xFF,
+	0x00, 0xA0, 0x64, 0x94, 0x7F, 0xC2, 0xC1, 0xB5, 0xFF, 0x00, 0xA0, 0x64, 0x95, 0xC1, 0xFF, 0x00,
+	0x6D, 0x3E, 0xDF, 0xBE, 0xD4, 0xBF, 0xDB, 0x52, 0x7F, 0xB5, 0x40, 0x1D, 0xDF, 0xFC, 0x2C, 0x1B,
+	0x5F, 0xFA, 0x06, 0x49, 0x47, 0xFC, 0x2C, 0x1B, 0x5F, 0xFA, 0x06, 0x49, 0x5C, 0x22, 0xEB, 0x6E,
+	0xDD, 0x5D, 0xBF, 0xEF, 0xAA, 0x4F, 0xED, 0x77, 0xFE, 0xFB, 0x7F, 0xDF, 0x54, 0x01, 0xDD, 0x3F,
+	0xC4, 0x3B, 0x65, 0x6D, 0x9F, 0xD9, 0xCD, 0x9A, 0xB1, 0x6B, 0xE3, 0x9D, 0x12, 0xE3, 0xE4, 0xBC,
+	0x7F, 0xB3, 0xB7, 0xFB, 0x55, 0xE7, 0xAD, 0xAC, 0x6E, 0x5F, 0xFD, 0x9A, 0x9B, 0x25, 0xEC, 0x33,
+	0x2F, 0xEF, 0x91, 0x5A, 0x80, 0x3D, 0x6A, 0xDA, 0xFA, 0xD2, 0xF1, 0x43, 0xDB, 0x5D, 0xAB, 0xAB,
+	0x7D, 0xDD, 0xB5, 0x3F, 0xCF, 0xBF, 0xFD, 0x9A, 0xF2, 0x6D, 0x2F, 0xC5, 0x97, 0x9A, 0x2C, 0xCA,
+	0xF6, 0xCF, 0xB9, 0x37, 0x7C, 0xDB, 0xBF, 0x86, 0xBD, 0x3B, 0x4B, 0xD4, 0xED, 0xF5, 0x4B, 0x18,
+	0xEF, 0xAD, 0xA6, 0x57, 0x8D, 0x97, 0xE6, 0x65, 0xFE, 0xF5, 0x00, 0x5B, 0xFE, 0x3F, 0xC2, 0x96,
+	0x9B, 0x19, 0x73, 0xF7, 0xC5, 0x3A, 0x80, 0x0A, 0x28, 0xA4, 0xCE, 0xD1, 0xF3, 0x9A, 0x00, 0x1F,
+	0xEE, 0xD5, 0x76, 0xB8, 0x58, 0x62, 0xDE, 0xFF, 0x00, 0x77, 0xFB, 0xD4, 0xFB, 0xDB, 0xB8, 0x6C,
+	0xAD, 0x9E, 0xF2, 0xE5, 0xF6, 0xC7, 0x1A, 0xE5, 0xAB, 0xCC, 0x35, 0xFF, 0x00, 0x1C, 0x5D, 0x6B,
+	0x72, 0x97, 0x8A, 0x49, 0x23, 0xB5, 0x66, 0xFF, 0x00, 0x47, 0x55, 0xFB, 0xDF, 0xF0, 0x2A, 0x5C,
+	0xD1, 0x8E, 0xE2, 0x72, 0xE5, 0xE9, 0x73, 0xBD, 0x9F, 0xC5, 0xFA, 0x42, 0xC9, 0xE4, 0xC3, 0x3A,
+	0xC8, 0xDF, 0xDD, 0x5A, 0xA6, 0xDE, 0x3F, 0xB7, 0x56, 0x64, 0xFB, 0x13, 0x7C, 0xB5, 0xC1, 0xAE,
+	0xA9, 0xE4, 0xC2, 0x88, 0x9B, 0x77, 0x7F, 0x13, 0x2F, 0xDE, 0xA4, 0x93, 0x5A, 0x48, 0xD7, 0xF7,
+	0xB3, 0x6C, 0xDB, 0xFC, 0x4C, 0xDF, 0x7A, 0x9A, 0xA3, 0x19, 0x6A, 0x98, 0xE3, 0xEF, 0x2B, 0x9D,
+	0xDA, 0xFC, 0x41, 0x84, 0xFF, 0x00, 0xCC, 0x39, 0xA8, 0xFF, 0x00, 0x84, 0xFE, 0x1D, 0xD8, 0xFE,
+	0xCE, 0x6A, 0xE3, 0xE1, 0x83, 0xC4, 0xD3, 0xC6, 0xB7, 0x10, 0xF8, 0x72, 0xF1, 0xE3, 0x93, 0xE6,
+	0x8E, 0x45, 0x5F, 0xBD, 0x52, 0x2D, 0x97, 0x8B, 0xC3, 0x37, 0x9B, 0xE1, 0x6B, 0xE6, 0x5F, 0xF6,
+	0x56, 0xAF, 0xD9, 0xBB, 0x69, 0x24, 0x28, 0xBA, 0x72, 0x95, 0xAE, 0xD5, 0x8E, 0xBB, 0xFE, 0x13,
+	0xEB, 0x6F, 0xFA, 0x06, 0xB5, 0x1F, 0xF0, 0x9F, 0xDB, 0xF4, 0xFE, 0xCF, 0x6A, 0xE2, 0xEE, 0x9B,
+	0xC4, 0x76, 0x51, 0xBD, 0xE5, 0xF6, 0x85, 0x79, 0x0D, 0xBA, 0xFD, 0xE9, 0x24, 0x5F, 0xBB, 0xFE,
+	0xF5, 0x56, 0x5D, 0x77, 0x7C, 0x4A, 0xC9, 0x36, 0xFD, 0xDF, 0xDD, 0xA8, 0x74, 0xE5, 0x1E, 0xA2,
+	0xE6, 0x8C, 0xA5, 0xEE, 0xB3, 0xBD, 0xFF, 0x00, 0x84, 0xFE, 0xDF, 0xFE, 0x81, 0xCD, 0x4E, 0x5F,
+	0x1F, 0xDB, 0x6C, 0x2F, 0xF6, 0x16, 0x5F, 0xF6, 0x6B, 0x81, 0x5D, 0x61, 0xD9, 0xBF, 0x8B, 0x6D,
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+	0x78, 0x77, 0x4B, 0x56, 0xDE, 0xCD, 0x1C, 0xBE, 0x5F, 0xDB, 0x36, 0xFD, 0xEF, 0xF7, 0xAB, 0xAA,
+	0xF8, 0x43, 0xFF, 0x00, 0x05, 0x0E, 0xF8, 0x1F, 0xFF, 0x00, 0x05, 0x04, 0xBF, 0xB7, 0xFD, 0x94,
+	0xB5, 0x5F, 0x06, 0x43, 0xAD, 0x68, 0xBE, 0x1F, 0xB7, 0xF3, 0xB5, 0x6F, 0xED, 0xC8, 0xD5, 0xA3,
+	0xBA, 0xDA, 0xBF, 0x75, 0x77, 0x7D, 0xEA, 0xFC, 0xDE, 0xFD, 0xA9, 0xBF, 0x68, 0xEF, 0x1E, 0x7E,
+	0xD0, 0x1E, 0x32, 0xBA, 0xD5, 0x6E, 0x74, 0x76, 0xD3, 0x7C, 0x3D, 0xB9, 0xA2, 0xD3, 0x7C, 0x37,
+	0x0B, 0x7C, 0xB0, 0xAA, 0xFF, 0x00, 0xCB, 0x6F, 0xF8, 0x15, 0x79, 0xC7, 0xC2, 0xDF, 0x16, 0xFC,
+	0x72, 0xF0, 0xAF, 0x89, 0x9F, 0x58, 0xFD, 0x9B, 0xEC, 0xE4, 0x9B, 0x5A, 0x5D, 0xAA, 0xD6, 0xF1,
+	0xFC, 0xBE, 0x5F, 0xCD, 0xF7, 0x99, 0xAB, 0xEE, 0x31, 0xDC, 0x37, 0x85, 0xCD, 0xF0, 0x52, 0x52,
+	0x4A, 0x12, 0x8A, 0xBC, 0x7C, 0xCF, 0x33, 0x86, 0x71, 0xD8, 0xAC, 0xA6, 0xA4, 0x54, 0xAA, 0x36,
+	0x9B, 0xD5, 0xB3, 0xC2, 0xFF, 0x00, 0xE0, 0xAE, 0x9F, 0xF0, 0x4E, 0x5F, 0x89, 0xBF, 0xB2, 0x3F,
+	0xC7, 0x5F, 0x14, 0xFC, 0x4A, 0x93, 0xC3, 0xD6, 0x36, 0x3E, 0x09, 0xD7, 0xBC, 0x41, 0x2C, 0xDE,
+	0x1D, 0x6D, 0x3F, 0xFD, 0x5C, 0x11, 0xB3, 0x6E, 0x58, 0x7F, 0xD9, 0x6F, 0xF6, 0x6B, 0xCD, 0xFF,
+	0x00, 0xE0, 0x9B, 0x7F, 0xB4, 0x45, 0xAF, 0xEC, 0xE5, 0xFB, 0x54, 0xE8, 0x7E, 0x3B, 0xF1, 0x3E,
+	0xB1, 0x75, 0x63, 0xA1, 0xAA, 0xB7, 0xF6, 0x95, 0xBA, 0xCC, 0xCB, 0x15, 0xD3, 0x6D, 0xF9, 0x77,
+	0xAD, 0x7F, 0x43, 0xDF, 0x13, 0x7F, 0x65, 0x4F, 0x83, 0xBF, 0xB7, 0xBF, 0xFC, 0x13, 0x36, 0xE3,
+	0xE0, 0x27, 0x8C, 0xE7, 0x8F, 0x5C, 0xF1, 0x0B, 0x78, 0x7D, 0xB5, 0x9B, 0xAD, 0x6B, 0xFE, 0x5A,
+	0x5A, 0xEB, 0xCA, 0xBB, 0x92, 0xD5, 0x5B, 0xFD, 0xEA, 0xFC, 0x0F, 0xFD, 0x8C, 0xBF, 0xE0, 0x9B,
+	0xFF, 0x00, 0xB4, 0x27, 0xC7, 0x5F, 0xDB, 0xAF, 0x43, 0xFD, 0x90, 0x3C, 0x75, 0xF0, 0xE6, 0xE2,
+	0x3B, 0xF5, 0xBC, 0x66, 0xD5, 0xAD, 0xCF, 0xDD, 0xB7, 0x8E, 0x36, 0xE7, 0x7B, 0x2F, 0xDD, 0xFF,
+	0x00, 0x81, 0x57, 0xE3, 0x75, 0x3D, 0xA6, 0x16, 0xB3, 0xA7, 0x38, 0xD9, 0xC5, 0xEA, 0xBB, 0x9F,
+	0xB5, 0xE1, 0xB1, 0x14, 0xB1, 0x51, 0xF6, 0x8B, 0x63, 0xFA, 0x73, 0xFD, 0x88, 0xFE, 0x27, 0x68,
+	0xFF, 0x00, 0x1A, 0xBF, 0x64, 0x7D, 0x0F, 0xE2, 0x6E, 0x8F, 0x73, 0x24, 0xD6, 0xDA, 0x94, 0xB2,
+	0x6D, 0xFE, 0xEE, 0xDF, 0xE1, 0xAF, 0x5D, 0xFD, 0x9A, 0xD7, 0xCB, 0xF1, 0xC6, 0xAC, 0x89, 0xF7,
+	0x7E, 0xCF, 0xF2, 0xFF, 0x00, 0xDF, 0x55, 0xCD, 0xFC, 0x0D, 0xF8, 0x07, 0xE1, 0x8F, 0xD9, 0x9B,
+	0xE0, 0x6E, 0x93, 0xF0, 0x1F, 0xC1, 0x36, 0x6B, 0x6F, 0xA6, 0xE8, 0xB0, 0x2A, 0xC5, 0xFE, 0xD4,
+	0xDF, 0xC5, 0x5D, 0x47, 0xEC, 0xEE, 0xBB, 0x7C, 0x77, 0xAA, 0x7F, 0xD7, 0x1A, 0xE7, 0x94, 0x95,
+	0x49, 0x73, 0xA5, 0x63, 0x77, 0x38, 0xCF, 0x64, 0x7B, 0x42, 0x1D, 0xB1, 0xAD, 0x3A, 0x9B, 0xB7,
+	0xE5, 0x51, 0x4E, 0xA0, 0x41, 0x45, 0x14, 0x50, 0x07, 0x9D, 0xFE, 0xD2, 0xCB, 0xBB, 0xE1, 0xE8,
+	0x1F, 0xF4, 0xFD, 0x1D, 0x72, 0x3E, 0x0F, 0xB3, 0xFF, 0x00, 0x47, 0x7F, 0xF8, 0x0D, 0x76, 0x1F,
+	0xB4, 0x87, 0xCD, 0xE0, 0x05, 0xFF, 0x00, 0xAF, 0xC8, 0xEB, 0x9B, 0xF0, 0x7C, 0x2E, 0xD6, 0xFF,
+	0x00, 0xEF, 0x2A, 0xD0, 0x05, 0xE6, 0xB3, 0xFB, 0xB4, 0xEF, 0xB2, 0xED, 0x6F, 0xB9, 0xBA, 0xAF,
+	0x79, 0x32, 0x37, 0xFC, 0x06, 0xBC, 0xBF, 0xF6, 0xA1, 0xFD, 0xAD, 0xFF, 0x00, 0x66, 0x4F, 0xD8,
+	0xDF, 0xC1, 0x96, 0x3F, 0x10, 0xFF, 0x00, 0x6A, 0xAF, 0x8B, 0x50, 0xF8, 0x43, 0x43, 0xD4, 0xAE,
+	0xBE, 0xCF, 0x65, 0x70, 0xCD, 0xFB, 0xE6, 0x93, 0xFE, 0xB9, 0xED, 0x66, 0xDB, 0xFE, 0xD6, 0xDA,
+	0x00, 0xF4, 0x05, 0xB5, 0x45, 0x6F, 0x25, 0x36, 0xED, 0x6F, 0xF9, 0x69, 0xFC, 0x5B, 0xAB, 0xE4,
+	0x7F, 0xF8, 0x29, 0x67, 0xFC, 0x12, 0xC6, 0x6F, 0xF8, 0x29, 0x57, 0x8E, 0x3C, 0x23, 0x73, 0xE3,
+	0x8F, 0x8B, 0x5A, 0xD6, 0x89, 0xE1, 0xEF, 0x0D, 0xAF, 0x95, 0x75, 0xE0, 0xFD, 0x36, 0x56, 0x5B,
+	0x1D, 0x61, 0x99, 0xBE, 0x59, 0x27, 0x5F, 0xE2, 0x65, 0xAE, 0xC3, 0xFE, 0x09, 0x67, 0xFF, 0x00,
+	0x05, 0x0B, 0x7F, 0xF8, 0x29, 0x5F, 0x81, 0xBE, 0x24, 0x7C, 0x42, 0x87, 0xE1, 0xA3, 0x68, 0x3E,
+	0x1D, 0xF0, 0x7F, 0x8B, 0x9B, 0x49, 0xF0, 0x96, 0xB1, 0x1F, 0xCC, 0xDA, 0xF5, 0xAF, 0xCD, 0xB6,
+	0xE8, 0xAF, 0xFB, 0x5F, 0x2F, 0xFD, 0xF5, 0x5F, 0x4B, 0xDA, 0xDA, 0xDF, 0xBE, 0xA5, 0x6B, 0xBE,
+	0x1B, 0x85, 0xF2, 0xEE, 0x23, 0xFF, 0x00, 0x97, 0x76, 0xFE, 0xF5, 0x00, 0x7F, 0x35, 0xDF, 0xB7,
+	0x37, 0xEC, 0xFB, 0xA0, 0xFE, 0xC7, 0x3F, 0xB5, 0x9E, 0xB5, 0xFB, 0x2D, 0x78, 0x63, 0x5B, 0x9A,
+	0xF2, 0xDF, 0x41, 0xB5, 0x8E, 0x55, 0x9A, 0x46, 0xF9, 0x95, 0x5B, 0xF8, 0x5A, 0xBD, 0x2B, 0xFE,
+	0x09, 0x97, 0xFB, 0x0D, 0xF8, 0x23, 0xFE, 0x0A, 0x1D, 0xF1, 0x63, 0xC4, 0x5F, 0x05, 0xBC, 0x6F,
+	0xAC, 0x4D, 0x6D, 0x6B, 0xA6, 0xE9, 0x3F, 0x6A, 0x97, 0xEC, 0xED, 0xFE, 0xB1, 0x7F, 0xBA, 0xD5,
+	0x93, 0xFF, 0x00, 0x05, 0xB2, 0x91, 0x2C, 0xFF, 0x00, 0xE0, 0xAF, 0xDF, 0x14, 0x1B, 0x6B, 0x6D,
+	0x6D, 0x26, 0xDF, 0xE5, 0x6F, 0xBD, 0xF7, 0x56, 0xBE, 0x88, 0xFF, 0x00, 0x83, 0x64, 0x0A, 0x5C,
+	0xFE, 0xD7, 0x1E, 0x3C, 0xBA, 0x4B, 0x66, 0x3F, 0xF1, 0x4B, 0xED, 0xF9, 0x57, 0x75, 0x00, 0x7E,
+	0xA6, 0x7E, 0xCE, 0x7F, 0x0A, 0x6F, 0xFE, 0x07, 0xFC, 0x23, 0xD1, 0x3E, 0x09, 0xBB, 0xAB, 0xE9,
+	0x7A, 0x0D, 0xAA, 0xDB, 0xE9, 0x32, 0x2F, 0xDE, 0x58, 0x56, 0xBB, 0xAF, 0xB2, 0xEE, 0x66, 0x4F,
+	0x95, 0xDD, 0x7F, 0x8A, 0xAF, 0xE9, 0x56, 0x8F, 0x2C, 0xF6, 0xF6, 0x33, 0xD9, 0xDC, 0x46, 0x97,
+	0x0C, 0xB1, 0x79, 0x9F, 0x67, 0x6F, 0x96, 0xBE, 0x08, 0x8B, 0xFE, 0x0B, 0xD3, 0xFB, 0x3A, 0x7C,
+	0x3A, 0xFD, 0xAD, 0xFE, 0x2C, 0x7E, 0xCB, 0x9F, 0xB5, 0xC5, 0x93, 0x7C, 0x3E, 0xB6, 0xF8, 0x6F,
+	0xE2, 0x0B, 0x7D, 0x2B, 0xC3, 0xBA, 0xB5, 0xBA, 0xB4, 0x92, 0x78, 0x81, 0xA6, 0x6D, 0xA1, 0xA4,
+	0x5D, 0xBF, 0x2D, 0x00, 0x7D, 0xD7, 0xF6, 0x48, 0xE9, 0x1A, 0xD5, 0x14, 0x7C, 0x95, 0x36, 0x9F,
+	0x71, 0x6D, 0x7D, 0xA7, 0xDB, 0x6A, 0x56, 0x17, 0x90, 0xDC, 0xDB, 0x5E, 0x59, 0xC7, 0x75, 0x6B,
+	0x75, 0x6A, 0xDE, 0x64, 0x52, 0x43, 0x27, 0xDD, 0xDA, 0xD5, 0x61, 0xAD, 0x5D, 0xBE, 0x72, 0x7F,
+	0x86, 0x80, 0x3C, 0xDF, 0xE2, 0x75, 0xBE, 0x2C, 0xDE, 0xBD, 0xA3, 0xE1, 0x28, 0xC7, 0xC3, 0x9D,
+	0x24, 0x7F, 0xD3, 0xBD, 0x79, 0x2F, 0xC5, 0x08, 0x76, 0xE9, 0xF2, 0x3D, 0x7A, 0xE7, 0xC2, 0x3F,
+	0xF9, 0x27, 0xBA, 0x5F, 0xFD, 0x7B, 0xD0, 0x07, 0x4D, 0x45, 0x14, 0x50, 0x01, 0x48, 0xFF, 0x00,
+	0x76, 0x96, 0x91, 0xFE, 0xED, 0x00, 0x78, 0x27, 0xC4, 0xD8, 0x7C, 0xCF, 0x8C, 0xBA, 0x87, 0xFD,
+	0x7B, 0xC7, 0x5F, 0x96, 0xFF, 0x00, 0xF0, 0x78, 0x3C, 0x5B, 0x3F, 0xE0, 0x9E, 0x9F, 0x08, 0xC7,
+	0xFD, 0x4F, 0x13, 0x0F, 0xFC, 0x87, 0x25, 0x7E, 0xA8, 0x7C, 0x44, 0x8C, 0xB7, 0xC6, 0x4B, 0xF7,
+	0x4F, 0xF9, 0xF7, 0x8E, 0xBF, 0x2D, 0xFF, 0x00, 0xE0, 0xF1, 0x25, 0xC7, 0xFC, 0x13, 0xCF, 0xE1,
+	0x1B, 0xFF, 0x00, 0xD4, 0xF5, 0x37, 0xFE, 0x89, 0x6A, 0x00, 0xFE, 0x71, 0x6F, 0xFF, 0x00, 0xE3,
+	0xF2, 0x4F, 0xF7, 0xAA, 0x1A, 0x9A, 0xF3, 0x3F, 0x6A, 0x93, 0x3D, 0x77, 0x54, 0x34, 0x00, 0x54,
+	0x81, 0x1F, 0xEE, 0x8E, 0x8B, 0xCE, 0xEF, 0x4A, 0x21, 0x5D, 0xCE, 0x33, 0xB7, 0xFE, 0x04, 0xDB,
+	0x6B, 0xF4, 0x63, 0xFE, 0x08, 0xB3, 0xFF, 0x00, 0x04, 0x64, 0x8B, 0xF6, 0xC7, 0xFB, 0x67, 0xED,
+	0x9B, 0xFB, 0x5C, 0xEB, 0xF1, 0x78, 0x13, 0xF6, 0x6D, 0xF8, 0x7E, 0xD2, 0x5F, 0x78, 0x93, 0xC5,
+	0x3A, 0xC4, 0x8B, 0x07, 0xF6, 0xC7, 0x93, 0xB5, 0x9E, 0xD2, 0x26, 0x6F, 0xE1, 0xFE, 0x16, 0x93,
+	0xB6, 0xED, 0xAB, 0xB9, 0x99, 0x56, 0x80, 0x3E, 0x05, 0xB6, 0xF8, 0x79, 0xE3, 0x5B, 0xDF, 0x08,
+	0x5D, 0x7C, 0x40, 0xB2, 0xF0, 0x9E, 0xA3, 0x2F, 0x87, 0xEC, 0x6E, 0xE3, 0xB5, 0xBE, 0xF1, 0x04,
+	0x56, 0x72, 0x1B, 0x3B, 0x79, 0xDB, 0x6E, 0xD8, 0xDE, 0x4D, 0xBB, 0x55, 0xBE, 0x65, 0xF9, 0x7E,
+	0xF5, 0x7D, 0x37, 0xFF, 0x00, 0x04, 0xF0, 0xFF, 0x00, 0x82, 0x36, 0x7E, 0xD8, 0xFF, 0x00, 0xF0,
+	0x52, 0x3F, 0x0A, 0x78, 0x97, 0xC7, 0xFF, 0x00, 0x03, 0x34, 0x5D, 0x2F, 0x4A, 0xF0, 0xEF, 0x86,
+	0x6D, 0x58, 0xEA, 0x5E, 0x22, 0xF1, 0x45, 0xD7, 0xD9, 0x2C, 0xE5, 0x6D, 0xA4, 0x95, 0x8D, 0xD9,
+	0x7E, 0x6F, 0x97, 0xFB, 0xBF, 0x76, 0xBF, 0x41, 0x7E, 0x16, 0x7E, 0xCE, 0x96, 0xFF, 0x00, 0xF0,
+	0x5A, 0x9F, 0x8A, 0x1A, 0xCF, 0xC1, 0x7F, 0xD8, 0x67, 0xE1, 0x64, 0x7F, 0x01, 0xFF, 0x00, 0x61,
+	0x3F, 0x07, 0x78, 0x82, 0x3B, 0xDF, 0x15, 0x5D, 0xB2, 0x79, 0x1F, 0xF0, 0x93, 0x5E, 0x5B, 0xB7,
+	0xCD, 0x75, 0xBA, 0x4D, 0xCD, 0xE6, 0x32, 0xA8, 0xDA, 0xBB, 0xBF, 0x76, 0xBF, 0x7B, 0xE6, 0xFB,
+	0xBE, 0x95, 0xF1, 0xFF, 0x00, 0xE2, 0xF7, 0x88, 0x7F, 0x6F, 0xEF, 0x1C, 0xE8, 0x3F, 0xF0, 0x45,
+	0x0F, 0xF8, 0x23, 0x5E, 0x84, 0xDE, 0x1B, 0xF8, 0x37, 0xE0, 0xBB, 0x88, 0x6D, 0xFE, 0x23, 0x78,
+	0xDB, 0x4D, 0x56, 0x86, 0x13, 0x0C, 0x6D, 0xB6, 0x55, 0xF3, 0x57, 0xEF, 0x6E, 0xDB, 0xF7, 0xBF,
+	0x8A, 0x80, 0x3D, 0x53, 0xFE, 0x08, 0x01, 0xFB, 0x74, 0x7E, 0xCA, 0xBF, 0x06, 0x3F, 0x66, 0x4B,
+	0x7F, 0xF8, 0x26, 0xBF, 0xC4, 0x8F, 0x8C, 0xBA, 0x1E, 0x97, 0xE3, 0xEF, 0x00, 0xEB, 0x37, 0x93,
+	0xEB, 0x1A, 0xA5, 0xC5, 0xF2, 0xFF, 0x00, 0x66, 0x4D, 0xBA, 0x46, 0xF9, 0x62, 0x99, 0xB6, 0xAB,
+	0x6D, 0xFB, 0xB5, 0xFA, 0x6D, 0xE0, 0xFF, 0x00, 0x10, 0xF8, 0x2F, 0xE2, 0x16, 0x90, 0x7C, 0x41,
+	0xF0, 0xE3, 0xC6, 0x7A, 0x6F, 0x8A, 0xB4, 0xD5, 0x6D, 0x92, 0x6A, 0xBE, 0x1F, 0xB8, 0x59, 0xE0,
+	0x8D, 0xBF, 0xBB, 0xB9, 0x59, 0xBE, 0x6A, 0xFE, 0x46, 0x7F, 0xE0, 0xB1, 0xBF, 0xB3, 0xD7, 0xC0,
+	0xAF, 0xD9, 0x57, 0xF6, 0xFA, 0xF1, 0x67, 0xC0, 0xBF, 0xD9, 0xE3, 0x50, 0x5B, 0x9F, 0x0D, 0xE8,
+	0x16, 0x36, 0xB1, 0x7D, 0xA2, 0xD6, 0xF7, 0xCE, 0x59, 0x6E, 0xBC, 0xBF, 0xDF, 0x36, 0xFF, 0x00,
+	0xE2, 0xF9, 0xB3, 0x55, 0x7F, 0x60, 0xCF, 0xF8, 0x2B, 0x3F, 0xED, 0x99, 0xFF, 0x00, 0x04, 0xFF,
+	0x00, 0xD4, 0xB4, 0x6D, 0x3B, 0xE0, 0x97, 0xC5, 0x3B, 0xF8, 0xFC, 0x21, 0x61, 0xE2, 0x08, 0xF5,
+	0x3D, 0x53, 0xC0, 0xCD, 0x37, 0xFA, 0x2E, 0xAF, 0xF3, 0x2E, 0xF8, 0xE4, 0xF9, 0x7E, 0xEB, 0x7F,
+	0xB3, 0x40, 0x1F, 0xD7, 0xE2, 0xDB, 0xDB, 0x3A, 0xFC, 0x8E, 0xDF, 0xEC, 0xB2, 0xFF, 0x00, 0x15,
+	0x47, 0xA8, 0x5B, 0xED, 0xB5, 0x7F, 0x93, 0x6B, 0x57, 0x84, 0xFF, 0x00, 0xC1, 0x38, 0x3F, 0xE0,
+	0xA6, 0x9F, 0x00, 0xFF, 0x00, 0xE0, 0xA7, 0x9F, 0x05, 0xED, 0xFE, 0x2F, 0xFC, 0x21, 0xBC, 0x5B,
+	0x5D, 0x62, 0x18, 0x63, 0x4F, 0x14, 0x78, 0x44, 0xB6, 0xE9, 0xB4, 0x9B, 0xAD, 0xAB, 0x98, 0xD5,
+	0x7F, 0x89, 0x7F, 0x8B, 0x75, 0x7D, 0x09, 0xAA, 0x42, 0xFF, 0x00, 0x67, 0x6F, 0xE2, 0x66, 0xA0,
+	0x0E, 0x1F, 0xE1, 0xFC, 0x7E, 0x5F, 0xC6, 0x6D, 0x37, 0xFE, 0xBA, 0x57, 0xD0, 0xC9, 0xD5, 0xBF,
+	0xDE, 0xAF, 0x00, 0xF0, 0x64, 0x7B, 0x3E, 0x32, 0xE9, 0x83, 0xA6, 0xD9, 0x6B, 0xDF, 0xD7, 0xA9,
+	0xA0, 0x07, 0x51, 0x45, 0x14, 0x00, 0x56, 0x1F, 0xC4, 0x7F, 0xF9, 0x11, 0x75, 0x6F, 0xFA, 0xF3,
+	0x6A, 0xDC, 0xAC, 0x3F, 0x88, 0xA7, 0x3E, 0x08, 0xD5, 0x87, 0xFD, 0x39, 0xB5, 0x00, 0x78, 0x9F,
+	0xC3, 0x5B, 0x52, 0xDA, 0x7D, 0xBF, 0xFB, 0xB5, 0xD9, 0x3D, 0xA2, 0x2A, 0xEF, 0x74, 0xF9, 0x6B,
+	0x99, 0xF8, 0x6B, 0x6E, 0xFF, 0x00, 0x61, 0xB7, 0x1F, 0xEC, 0xD4, 0x3F, 0xB4, 0x9F, 0xED, 0x19,
+	0xF0, 0x6B, 0xF6, 0x47, 0xF8, 0x2F, 0xAC, 0x7E, 0xD0, 0xDF, 0x1F, 0xFC, 0x5F, 0x0E, 0x87, 0xE1,
+	0x9D, 0x06, 0x06, 0x76, 0x92, 0x67, 0xDB, 0x2D, 0xE5, 0xC2, 0xFD, 0xC8, 0x63, 0x5F, 0xE2, 0xDD,
+	0xF7, 0x68, 0x03, 0x37, 0xF6, 0x98, 0xFD, 0xA5, 0x3E, 0x07, 0x7E, 0xC7, 0x3F, 0x04, 0x75, 0x8F,
+	0xDA, 0x1F, 0xF6, 0x84, 0xF1, 0x0A, 0xE9, 0xBE, 0x1B, 0xD2, 0xED, 0x59, 0xED, 0xED, 0xD5, 0xB6,
+	0xDC, 0xEA, 0x52, 0x6D, 0xF9, 0x63, 0xB6, 0x5D, 0xDF, 0x33, 0x57, 0x90, 0x7F, 0xC1, 0x21, 0xFF,
+	0x00, 0x6E, 0x4F, 0x1E, 0x7F, 0xC1, 0x47, 0xFF, 0x00, 0x64, 0xAD, 0x53, 0xF6, 0x98, 0xF1, 0xE7,
+	0x86, 0xED, 0x74, 0xDF, 0xF8, 0xAB, 0xEE, 0x2C, 0xB4, 0x1B, 0x7B, 0x7F, 0xBD, 0xFD, 0x9E, 0xAD,
+	0xFB, 0xBD, 0xFF, 0x00, 0xF4, 0xD2, 0xBF, 0x9F, 0xCF, 0xF8, 0x29, 0x2F, 0xFC, 0x14, 0xF3, 0xE3,
+	0xA7, 0xFC, 0x14, 0xFB, 0xE3, 0x31, 0xF8, 0x95, 0xF1, 0x1D, 0xA6, 0xD0, 0xBC, 0x1B, 0xA3, 0xC9,
+	0x22, 0x78, 0x27, 0xE1, 0xE4, 0x32, 0x37, 0x95, 0xA7, 0xAA, 0xA7, 0xCB, 0x74, 0xDF, 0x2F, 0xCC,
+	0xD2, 0x57, 0xEC, 0x97, 0xFC, 0x1A, 0xCE, 0xD2, 0x4D, 0xFF, 0x00, 0x04, 0x95, 0x57, 0x48, 0x77,
+	0x33, 0x78, 0xDE, 0xE1, 0xBF, 0xF1, 0xE5, 0xA0, 0x0F, 0xD1, 0x27, 0xB7, 0xFF, 0x00, 0x62, 0x93,
+	0xCA, 0x6F, 0xEE, 0x54, 0x91, 0xB4, 0xCC, 0xCD, 0xF2, 0x7D, 0xDF, 0xBD, 0x48, 0x64, 0x40, 0xAA,
+	0xF3, 0x6A, 0x5A, 0x7D, 0x9A, 0xB7, 0xDD, 0xFE, 0xD0, 0xBA, 0x58, 0x3C, 0xCF, 0xF7, 0x77, 0x7D,
+	0xEA, 0x00, 0x6B, 0x5B, 0xBA, 0xF0, 0x29, 0xAD, 0x1F, 0xFB, 0x15, 0x22, 0x18, 0xCA, 0xEF, 0xB6,
+	0xD6, 0x34, 0xFB, 0xDF, 0xEF, 0x7F, 0x67, 0xDD, 0x2C, 0xBE, 0x5F, 0xFB, 0xDB, 0x7E, 0xED, 0x48,
+	0xAD, 0x36, 0x76, 0x79, 0x35, 0x31, 0x03, 0xE5, 0xBF, 0xF8, 0x2B, 0x77, 0xED, 0xCB, 0xE3, 0xFF,
+	0x00, 0xF8, 0x27, 0x2F, 0xEC, 0xA7, 0xA4, 0xFE, 0xD3, 0xBE, 0x00, 0xF0, 0xF5, 0x9E, 0xA4, 0xED,
+	0xE2, 0xFB, 0x7D, 0x37, 0x5E, 0xB5, 0xBE, 0xE9, 0xFD, 0x9E, 0xCD, 0xB6, 0x46, 0x45, 0xFF, 0x00,
+	0x9E, 0x9B, 0x6B, 0xD8, 0xBF, 0x67, 0xBF, 0xDA, 0x1B, 0xE0, 0x87, 0xED, 0x5F, 0xF0, 0xBB, 0x4D,
+	0xF8, 0xDF, 0xF0, 0x07, 0xC5, 0x96, 0xBA, 0xC6, 0x83, 0x79, 0x6B, 0x1B, 0x5D, 0x5A, 0xC3, 0x2A,
+	0xB4, 0xFA, 0x5C, 0x8C, 0xBB, 0x9A, 0x3B, 0x95, 0xDD, 0xF2, 0xB5, 0x7C, 0x53, 0xFF, 0x00, 0x07,
+	0x4A, 0x4C, 0xD6, 0xFF, 0x00, 0xF0, 0x49, 0xF5, 0xBD, 0x9A, 0x1D, 0xD2, 0x43, 0xE3, 0x9B, 0x76,
+	0x89, 0x7F, 0xE0, 0x55, 0xF8, 0xE3, 0xFF, 0x00, 0x04, 0xC5, 0xFF, 0x00, 0x82, 0x97, 0xFC, 0x57,
+	0xFF, 0x00, 0x82, 0x61, 0x7E, 0xD1, 0x1F, 0xF0, 0xB3, 0x3C, 0x03, 0xF6, 0x8D, 0x43, 0xC0, 0xFE,
+	0x22, 0x68, 0xFF, 0x00, 0xE1, 0x60, 0x78, 0x22, 0x49, 0xB7, 0x47, 0xA8, 0x2E, 0xDF, 0x9A, 0xE9,
+	0x7F, 0xBA, 0xD1, 0xAB, 0x53, 0x96, 0xC0, 0x7F, 0x53, 0x4D, 0x67, 0x0B, 0x2F, 0xC9, 0xF7, 0x7F,
+	0x86, 0xB0, 0x7C, 0x71, 0x6F, 0xFF, 0x00, 0x12, 0xF7, 0xFF, 0x00, 0x76, 0xA9, 0xFE, 0xCD, 0xFF,
+	0x00, 0xB4, 0x47, 0xC1, 0x9F, 0xDA, 0xE3, 0xE0, 0xAE, 0x93, 0xFB, 0x43, 0xFE, 0xCF, 0x7E, 0x2A,
+	0x87, 0x5A, 0xF0, 0xAE, 0xB8, 0xBB, 0xA2, 0x92, 0x36, 0xDC, 0xF6, 0xB3, 0x7F, 0x14, 0x32, 0x2F,
+	0xF0, 0xED, 0xFB, 0xB5, 0xB1, 0xE3, 0x6B, 0x77, 0xFB, 0x0C, 0x9B, 0xFF, 0x00, 0xBB, 0x44, 0x76,
+	0x03, 0x73, 0xF6, 0x5E, 0xFF, 0x00, 0x91, 0x2A, 0xEB, 0xFE, 0xBF, 0x1A, 0xBD, 0x3A, 0xBC, 0xCF,
+	0xF6, 0x63, 0x50, 0xBE, 0x0D, 0xBC, 0x4F, 0xFA, 0x7D, 0x6A, 0xF4, 0xCA, 0x60, 0x14, 0x51, 0x45,
+	0x00, 0x23, 0xFD, 0xDA, 0xF1, 0xEF, 0xDA, 0x4A, 0x3F, 0x33, 0xC5, 0x3A, 0x0F, 0xFB, 0xAD, 0xFC,
+	0xEB, 0xD8, 0x5F, 0xEE, 0xD7, 0x91, 0xFE, 0xD0, 0xEA, 0xF2, 0x78, 0xA7, 0x43, 0xD9, 0xF7, 0x76,
+	0xB5, 0x00, 0x66, 0x68, 0x76, 0x6F, 0xF6, 0x05, 0xD9, 0x57, 0x8D, 0xAD, 0x8C, 0x45, 0xA7, 0xD6,
+	0xAE, 0xE1, 0xB5, 0xD3, 0xE1, 0x46, 0x7B, 0xEB, 0xEB, 0x86, 0xDA, 0x90, 0x2E, 0xDF, 0xBC, 0xCD,
+	0xFC, 0x35, 0x27, 0x87, 0xE1, 0x46, 0xD3, 0xD1, 0xD1, 0x3E, 0x5A, 0xF9, 0x07, 0xFE, 0x0B, 0xB3,
+	0xFB, 0x56, 0x78, 0x93, 0xF6, 0x49, 0xFD, 0x86, 0xE6, 0x7F, 0x0B, 0x68, 0x2B, 0xAA, 0xAF, 0xC4,
+	0x4B, 0x86, 0xD1, 0x35, 0x48, 0xD6, 0x4D, 0xB2, 0x5A, 0xC6, 0xDF, 0xF2, 0xD1, 0x68, 0x03, 0xF2,
+	0x67, 0xFE, 0x0B, 0x09, 0xFB, 0x74, 0x7C, 0x62, 0xFD, 0xAD, 0xBF, 0x6A, 0x0F, 0x10, 0x78, 0x33,
+	0xC6, 0x7E, 0x2D, 0xB7, 0x4F, 0x04, 0xF8, 0x26, 0xFD, 0xAC, 0xB4, 0x1D, 0x2F, 0x49, 0xB8, 0xDD,
+	0xA7, 0xEA, 0x11, 0xAB, 0x7C, 0xB7, 0x4D, 0xB7, 0xEF, 0x35, 0x76, 0x7F, 0xF0, 0x49, 0xBF, 0xF8,
+	0x23, 0xBE, 0xA1, 0xFF, 0x00, 0x05, 0x08, 0xD4, 0x7F, 0xE1, 0x65, 0xFC, 0x56, 0xBC, 0xD4, 0xB4,
+	0x3F, 0x87, 0x9A, 0x3D, 0xD4, 0x72, 0xDD, 0x6A, 0x0A, 0xAC, 0xB2, 0xEA, 0x52, 0x2F, 0xDD, 0x58,
+	0xBF, 0xBC, 0xBF, 0xDE, 0xAF, 0x9A, 0xBF, 0x63, 0x3F, 0xD9, 0x87, 0xC7, 0x9F, 0xB5, 0x57, 0xED,
+	0x09, 0xE1, 0xFF, 0x00, 0x80, 0x9F, 0x0D, 0x3C, 0x26, 0xDA, 0xE1, 0x92, 0xE9, 0x5F, 0x56, 0xB5,
+	0x92, 0x5F, 0xBB, 0xA7, 0xEE, 0xFD, 0xE4, 0x9B, 0xAB, 0xFA, 0x70, 0xF8, 0x37, 0xF0, 0x7F, 0xC3,
+	0x1F, 0x00, 0xFE, 0x13, 0xF8, 0x7F, 0xE0, 0x9F, 0xC3, 0xD8, 0x63, 0x8F, 0x43, 0xF0, 0xDD, 0x9A,
+	0xC5, 0x66, 0xB1, 0xAE, 0xDF, 0x2D, 0xB6, 0xFC, 0xDB, 0xBF, 0xBD, 0xF3, 0x50, 0x04, 0x7F, 0x0A,
+	0x3E, 0x12, 0x7C, 0x2E, 0xF8, 0x15, 0xA5, 0x8D, 0x07, 0xE0, 0xEF, 0xC3, 0xED, 0x3F, 0xC3, 0x4A,
+	0xB6, 0xB1, 0xDB, 0xDC, 0x5E, 0x69, 0xB6, 0xEA, 0xAF, 0x78, 0xAB, 0xF7, 0x59, 0xFE, 0x5F, 0xBD,
+	0x5D, 0x4C, 0xDF, 0xDA, 0x53, 0x6D, 0x9A, 0x4B, 0xF6, 0x99, 0x9B, 0xE5, 0x69, 0x1A, 0x85, 0x7B,
+	0x9B, 0x79, 0x36, 0x3F, 0xEF, 0x12, 0x4F, 0xBC, 0xDF, 0xDD, 0xA4, 0xCC, 0xD1, 0xAB, 0x25, 0xB4,
+	0x7B, 0x51, 0xBF, 0x86, 0x80, 0x1D, 0x0D, 0xE5, 0xFE, 0x9B, 0xBA, 0x6B, 0x6B, 0xF9, 0x23, 0xFE,
+	0x1D, 0xAB, 0xB7, 0xE6, 0xAF, 0x39, 0xFD, 0xA6, 0x3F, 0x65, 0xEF, 0x83, 0xDF, 0xB5, 0xEF, 0x81,
+	0x5F, 0xC0, 0x1F, 0x1C, 0xBC, 0x3D, 0x0D, 0xEB, 0x32, 0xB0, 0xB0, 0xD7, 0xA4, 0x89, 0x7E, 0xD5,
+	0xA6, 0xAB, 0x7F, 0x0C, 0x4D, 0xB7, 0xE5, 0xAF, 0x45, 0xF9, 0xD9, 0x55, 0x26, 0x4D, 0xDB, 0x7E,
+	0xED, 0x2C, 0x8D, 0x35, 0xD4, 0x2F, 0xBE, 0x1F, 0xF8, 0x15, 0x00, 0x7F, 0x3A, 0xBF, 0xF0, 0x55,
+	0x8F, 0xF8, 0x25, 0x97, 0x8C, 0xFF, 0x00, 0xE0, 0x9F, 0xBF, 0x10, 0x21, 0xBF, 0xD1, 0x24, 0xFE,
+	0xD4, 0xF0, 0x0F, 0x88, 0xA5, 0xDB, 0xE1, 0xDB, 0xA6, 0xF9, 0xA7, 0xF3, 0x3F, 0x8B, 0xCC, 0xAF,
+	0x4A, 0xFF, 0x00, 0x82, 0x35, 0xFF, 0x00, 0xC1, 0x51, 0xBC, 0x61, 0xFB, 0x3F, 0xF8, 0xE7, 0xC3,
+	0xDF, 0xB2, 0x8F, 0x8B, 0x61, 0xFB, 0x67, 0x87, 0xBC, 0x4D, 0xAB, 0x2D, 0x9D, 0x84, 0xD3, 0x7C,
+	0xD2, 0x43, 0x33, 0x37, 0xFE, 0x83, 0x5F, 0xB1, 0x5F, 0xB6, 0x17, 0xEC, 0x7F, 0xE0, 0xCF, 0xDB,
+	0x6F, 0xE0, 0x5E, 0xB1, 0xF0, 0x37, 0xC6, 0xD7, 0x8B, 0x67, 0x79, 0x75, 0x67, 0x23, 0x68, 0x3E,
+	0x20, 0xDB, 0xB9, 0xB4, 0xB6, 0x55, 0xFB, 0xCB, 0x5F, 0xCC, 0xB7, 0x8D, 0x34, 0x1D, 0x63, 0xE0,
+	0x7F, 0xC6, 0x4D, 0x5B, 0xC3, 0x1E, 0x18, 0xF1, 0x27, 0x9D, 0xAB, 0x78, 0x3F, 0x5E, 0x6B, 0x3B,
+	0x3D, 0x71, 0x7E, 0xF3, 0x49, 0x1C, 0x9F, 0xEB, 0xBF, 0xF1, 0xDA, 0x00, 0xFE, 0xA8, 0xEE, 0xB4,
+	0xF4, 0xB3, 0xBA, 0x92, 0xC2, 0x29, 0x99, 0xC4, 0x7B, 0x77, 0x48, 0xBF, 0x77, 0xEE, 0xD7, 0x1F,
+	0xE3, 0x08, 0xF6, 0xEB, 0xD6, 0x2F, 0xB1, 0xB6, 0xFD, 0xAA, 0x3F, 0x9B, 0xFB, 0xDF, 0x35, 0x79,
+	0xCF, 0xFC, 0x13, 0x1F, 0xF6, 0xAA, 0xF0, 0x97, 0xED, 0x7D, 0xFB, 0x22, 0xF8, 0x7F, 0xC5, 0x5E,
+	0x15, 0xF1, 0x0B, 0x6A, 0x9A, 0x87, 0x86, 0xED, 0x63, 0xB0, 0xF1, 0x55, 0xE4, 0x8B, 0xF3, 0x49,
+	0x79, 0xB5, 0x77, 0x57, 0xA8, 0x78, 0xE1, 0x5F, 0xFB, 0x6A, 0xCD, 0xDB, 0xE5, 0x5F, 0xB5, 0x47,
+	0xB6, 0x3F, 0xEE, 0xD0, 0x07, 0xD1, 0x16, 0x1F, 0xF1, 0xED, 0x0F, 0xFD, 0x71, 0x5A, 0x9D, 0x5B,
+	0x77, 0x6A, 0x8A, 0xCB, 0xFE, 0x3D, 0x62, 0xFF, 0x00, 0xAE, 0x6B, 0x52, 0xAA, 0xED, 0xA0, 0x05,
+	0xA2, 0x8A, 0x28, 0x01, 0xAD, 0xF7, 0x3F, 0xE0, 0x35, 0xF3, 0x87, 0x87, 0xED, 0xCB, 0xF8, 0x8B,
+	0x50, 0x7F, 0xFA, 0x89, 0x49, 0xFF, 0x00, 0xA1, 0x57, 0xD1, 0xEC, 0x71, 0x9F, 0xF7, 0x6B, 0xE7,
+	0xBF, 0x0B, 0xC2, 0xED, 0xE2, 0x2B, 0xFD, 0x89, 0xFF, 0x00, 0x31, 0x29, 0x3F, 0xF4, 0x2A, 0x00,
+	0xEB, 0x96, 0xD5, 0x36, 0xEF, 0xD9, 0x4E, 0xFB, 0x2A, 0x63, 0xEE, 0x55, 0xAF, 0x2D, 0xD5, 0x7E,
+	0x75, 0xA2, 0x48, 0x66, 0xF2, 0xF7, 0xA5, 0xB4, 0x92, 0x7F, 0xD7, 0x35, 0xDD, 0x40, 0x15, 0x5A,
+	0xC5, 0x24, 0x5D, 0xE8, 0xFF, 0x00, 0xBE, 0xFE, 0x05, 0x6F, 0xBB, 0x52, 0x2D, 0x95, 0xCD, 0xD6,
+	0xD8, 0x6C, 0xED, 0x24, 0x9A, 0x65, 0xFF, 0x00, 0x5A, 0xB6, 0xFF, 0x00, 0x33, 0x57, 0x95, 0xFE,
+	0xD6, 0x1F, 0xB7, 0x07, 0xEC, 0x93, 0xFB, 0x0A, 0x78, 0x4B, 0x4D, 0xF1, 0x97, 0xED, 0x6B, 0xF1,
+	0x76, 0xD7, 0xC3, 0xBA, 0x5E, 0xB3, 0x33, 0x47, 0xA6, 0x35, 0xA4, 0x9E, 0x6C, 0xAD, 0x22, 0xFC,
+	0xDB, 0x4A, 0x2A, 0xEE, 0xAF, 0xC4, 0x1F, 0xF8, 0x29, 0x87, 0xFC, 0x1D, 0x63, 0xF1, 0xBB, 0xE2,
+	0xD4, 0x7F, 0xF0, 0xAB, 0xFF, 0x00, 0x61, 0xAB, 0x49, 0x3C, 0x07, 0x6B, 0xA4, 0xEB, 0x12, 0x6D,
+	0xF1, 0xF5, 0x9C, 0xDF, 0xE9, 0x3A, 0xA5, 0xBA, 0xAE, 0xD5, 0x5D, 0x8C, 0xBF, 0x2A, 0xB5, 0x00,
+	0x7E, 0xC7, 0x7E, 0xDB, 0x5F, 0xF0, 0x53, 0xAF, 0xD8, 0xAF, 0xF6, 0x06, 0xF0, 0x35, 0xBF, 0x8E,
+	0xBE, 0x35, 0xFC, 0x47, 0xB7, 0xD5, 0x24, 0x9B, 0x5B, 0x8F, 0x4A, 0x4F, 0x0D, 0x78, 0x76, 0xE9,
+	0x65, 0xD4, 0x61, 0xB8, 0x6F, 0xEF, 0xC6, 0xAD, 0xB9, 0x55, 0x7F, 0x8A, 0xBD, 0xBB, 0xE1, 0xCF,
+	0x8C, 0xB4, 0x7F, 0x8A, 0x3E, 0x03, 0xD2, 0xBE, 0x28, 0xF8, 0x71, 0x1A, 0x3D, 0x3F, 0x58, 0xB5,
+	0x59, 0xAC, 0x23, 0x93, 0xEF, 0x32, 0xB2, 0xEE, 0xF9, 0xAB, 0xF8, 0xAB, 0x4F, 0x89, 0x9E, 0x39,
+	0xF8, 0xBB, 0xFB, 0x40, 0x58, 0x7C, 0x4A, 0xF8, 0x89, 0xE2, 0x4B, 0x8D, 0x63, 0x5E, 0xD6, 0x3C,
+	0x4F, 0x0D, 0xC6, 0xA5, 0xA8, 0x5E, 0x36, 0xF6, 0x9A, 0x46, 0x99, 0x7E, 0x6A, 0xFE, 0xC9, 0x7F,
+	0x63, 0x9F, 0xB4, 0x49, 0xFB, 0x28, 0xF8, 0x0F, 0xED, 0x3C, 0xB2, 0xE9, 0x31, 0xFF, 0x00, 0xE8,
+	0xBA, 0x00, 0xF4, 0x1F, 0x2D, 0x1B, 0xEE, 0x23, 0x2B, 0x7F, 0x17, 0xF7, 0x69, 0xCD, 0x0C, 0x3B,
+	0x59, 0xE6, 0x75, 0xD9, 0xB7, 0xE5, 0x6A, 0xB0, 0xA2, 0xE2, 0x60, 0xCB, 0x24, 0xD0, 0xD9, 0xAC,
+	0x6A, 0xCF, 0xE6, 0x5F, 0x37, 0x95, 0x1B, 0x2A, 0xFD, 0xEF, 0x99, 0xAB, 0xF3, 0xAB, 0xF6, 0xF5,
+	0xFF, 0x00, 0x83, 0x96, 0x7F, 0x61, 0x6F, 0xD9, 0x0B, 0x4D, 0xBA, 0xD3, 0x7E, 0x08, 0x5E, 0x47,
+	0xF1, 0x13, 0xC6, 0xDA, 0x6E, 0xA9, 0x25, 0x96, 0xA9, 0xE1, 0x3F, 0x99, 0x60, 0x86, 0x45, 0xF9,
+	0x59, 0xBC, 0xCD, 0xBF, 0xDE, 0xA0, 0x0F, 0xBF, 0xBC, 0x4B, 0xAA, 0x78, 0x5B, 0xC0, 0xDA, 0x50,
+	0xD7, 0xFE, 0x22, 0x78, 0xA6, 0xC7, 0xC3, 0x7A, 0x5C, 0x8D, 0x85, 0xD4, 0xB5, 0x8B, 0x85, 0x8A,
+	0x0D, 0xCD, 0xF7, 0x57, 0x73, 0x35, 0x7C, 0xF1, 0xFB, 0x39, 0x7F, 0xC1, 0x52, 0x7F, 0x64, 0xAF,
+	0xDA, 0xB7, 0xF6, 0x99, 0xF1, 0x67, 0xEC, 0xA5, 0xF0, 0x22, 0xFA, 0xFB, 0x54, 0xD7, 0xBC, 0x17,
+	0x71, 0xE5, 0x6B, 0x1A, 0xC4, 0x7F, 0x35, 0x8D, 0xD3, 0x7F, 0x7A, 0x09, 0x3F, 0x89, 0x7E, 0x56,
+	0xAF, 0xE6, 0x87, 0xF6, 0xF5, 0xFF, 0x00, 0x82, 0xC3, 0x7E, 0xDA, 0x1F, 0xF0, 0x50, 0x0D, 0x5B,
+	0x58, 0xD1, 0xFE, 0x29, 0xFC, 0x55, 0xD4, 0x2D, 0xFC, 0x15, 0xA8, 0x6B, 0x0F, 0x79, 0x63, 0xE0,
+	0x7B, 0x7B, 0x8C, 0x5B, 0x69, 0xEB, 0xBB, 0xE5, 0x8D, 0x4E, 0xDF, 0x9A, 0xBE, 0xE2, 0xFF, 0x00,
+	0x83, 0x41, 0x9A, 0x69, 0x3F, 0x68, 0x6F, 0x16, 0xF9, 0x2F, 0xF3, 0x6D, 0x8D, 0xB6, 0xB7, 0xDE,
+	0xFB, 0xBF, 0xDE, 0xA0, 0x0F, 0xDF, 0xEF, 0x11, 0x42, 0x9F, 0x63, 0x64, 0x44, 0xC3, 0x2E, 0xE5,
+	0x75, 0xA8, 0x3F, 0x66, 0xB8, 0xF6, 0x78, 0xD7, 0x55, 0x1F, 0xF4, 0xC2, 0xB5, 0xFC, 0x51, 0x6F,
+	0xF2, 0xCC, 0xFF, 0x00, 0x7B, 0xE6, 0x6F, 0xDE, 0x56, 0x6F, 0xEC, 0xEA, 0xA5, 0x7C, 0x73, 0xAA,
+	0x7F, 0xD7, 0x0A, 0x00, 0xF6, 0x84, 0xE9, 0x4E, 0xA4, 0x4F, 0xBB, 0x4B, 0x40, 0x05, 0x14, 0x51,
+	0x40, 0x1E, 0x77, 0xFB, 0x4A, 0xAE, 0xFF, 0x00, 0x87, 0x1B, 0x7F, 0xE9, 0xF6, 0x3A, 0xE5, 0x7C,
+	0x0B, 0x63, 0xBA, 0x6B, 0x35, 0x98, 0xEF, 0x5F, 0xB5, 0x42, 0xBE, 0x5B, 0x7F, 0x12, 0xEE, 0x5A,
+	0xEB, 0x3F, 0x68, 0xF5, 0x2D, 0xF0, 0xF5, 0x78, 0xDC, 0x7E, 0xD9, 0x1D, 0x60, 0x7C, 0x3E, 0x8D,
+	0xD6, 0xEA, 0xDE, 0x57, 0xF9, 0x99, 0x6E, 0xA1, 0xF9, 0x7F, 0xBB, 0xF3, 0x2D, 0x27, 0xD1, 0xF9,
+	0x8D, 0x4E, 0x34, 0xEF, 0x26, 0xAF, 0xA7, 0xF4, 0xCF, 0xC9, 0x2D, 0x6B, 0xF6, 0x6A, 0xF8, 0xB3,
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+	0xB9, 0xC7, 0x8E, 0xF5, 0x4F, 0xFA, 0xE1, 0x5E, 0x54, 0xA7, 0x17, 0x51, 0xC6, 0x3D, 0x0F, 0x43,
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+	0x96, 0x80, 0x3E, 0x63, 0xFF, 0x00, 0x82, 0xA6, 0xFF, 0x00, 0xC1, 0x5F, 0x3E, 0x19, 0x7F, 0xC1,
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+	0x7A, 0x5C, 0x3A, 0x6C, 0x81, 0x7E, 0xCB, 0x22, 0xFD, 0xD6, 0x6F, 0xF8, 0x13, 0x2F, 0xCB, 0x5F,
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+	0xB4, 0xB1, 0x5D, 0xDE, 0x5A, 0xF9, 0x5F, 0x77, 0xCC, 0xFE, 0xF3, 0x57, 0xF4, 0x9F, 0xFB, 0x61,
+	0xFE, 0xC6, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x6E, 0x0F, 0x83, 0xFA, 0xC7, 0xC1, 0xDF, 0x8E, 0x3E,
+	0x1F, 0x55, 0x8E, 0xFA, 0xD5, 0x92, 0xC3, 0xC5, 0x70, 0xA2, 0xFD, 0xB3, 0x46, 0x93, 0xF8, 0x5A,
+	0x0F, 0x97, 0x75, 0x7F, 0x3E, 0x5F, 0xB6, 0xD7, 0xFC, 0x12, 0xCF, 0xF6, 0xC0, 0xFF, 0x00, 0x82,
+	0x7C, 0x68, 0x2D, 0xE2, 0x4F, 0x8D, 0x3E, 0x1B, 0x6D, 0x6B, 0xC3, 0xD3, 0x6A, 0xCD, 0x67, 0xE1,
+	0xCD, 0x53, 0x45, 0x5F, 0x39, 0x96, 0xC5, 0x7F, 0xD5, 0xDC, 0x5D, 0xB2, 0xFD, 0xDD, 0xCB, 0xF7,
+	0xA8, 0x02, 0x5F, 0xD9, 0x5B, 0xFE, 0x0A, 0x7B, 0xFB, 0x6B, 0xFE, 0xC2, 0xDF, 0x0F, 0xF5, 0x0F,
+	0x86, 0x9F, 0xB2, 0xC7, 0x89, 0xB4, 0x5B, 0x1D, 0x27, 0x52, 0xBD, 0xFB, 0x54, 0x90, 0xEA, 0x10,
+	0xEE, 0xDB, 0x27, 0xFB, 0x3F, 0xDD, 0xAF, 0x40, 0x3F, 0xF0, 0x70, 0x8F, 0xFC, 0x16, 0x8D, 0xB0,
+	0x22, 0xF8, 0x95, 0xE0, 0xBC, 0xAB, 0x65, 0x77, 0x59, 0x2F, 0xCD, 0x5E, 0x79, 0xFB, 0x10, 0x7F,
+	0xC1, 0x30, 0x3F, 0x6B, 0xDF, 0xF8, 0x28, 0x97, 0xC3, 0x9D, 0x4F, 0xE2, 0x87, 0xEC, 0xCF, 0x16,
+	0x87, 0x36, 0x95, 0xA2, 0xEA, 0x1F, 0x63, 0xBA, 0x6D, 0x4A, 0xE1, 0x57, 0xCC, 0x93, 0xFE, 0x99,
+	0xFF, 0x00, 0x79, 0x6B, 0xD9, 0x97, 0xFE, 0x0D, 0xBC, 0xFF, 0x00, 0x82, 0xA9, 0xCC, 0xEA, 0xF3,
+	0x69, 0x7E, 0x15, 0x46, 0x66, 0xC2, 0xED, 0xBA, 0x5F, 0x96, 0x80, 0x3E, 0x4D, 0xF8, 0xCB, 0xFB,
+	0x41, 0xFC, 0x6B, 0xFD, 0xA5, 0xBE, 0x35, 0xEA, 0x7F, 0xB4, 0x47, 0xC7, 0xDD, 0x6B, 0x4F, 0xBC,
+	0xF1, 0xA6, 0xBB, 0x6E, 0xB6, 0xDA, 0xB5, 0xC6, 0x9B, 0x0E, 0xDB, 0x6F, 0x2D, 0x7E, 0xEA, 0xAA,
+	0xD7, 0x49, 0xFB, 0x35, 0xFE, 0xDC, 0x9F, 0xB5, 0xC7, 0xEC, 0x3F, 0xE2, 0xED, 0x4F, 0xC7, 0x7F,
+	0xB1, 0xF7, 0x88, 0xB4, 0x5B, 0x1D, 0x6B, 0x56, 0xB3, 0xFB, 0x3E, 0xA8, 0xDA, 0xED, 0xBA, 0xCD,
+	0x14, 0x90, 0xFF, 0x00, 0xB2, 0xAD, 0xFC, 0x55, 0xCC, 0xFE, 0xD3, 0x7F, 0xB3, 0xF7, 0xC5, 0xAF,
+	0xD9, 0x13, 0xE3, 0xA6, 0xA5, 0xFB, 0x34, 0xFC, 0x62, 0x8B, 0x4F, 0x1E, 0x24, 0xD0, 0xED, 0xD6,
+	0x7D, 0x52, 0x4D, 0x3E, 0x5D, 0xD1, 0x79, 0x6D, 0xF7, 0x76, 0xB5, 0x7A, 0x07, 0xEC, 0x7D, 0xFF,
+	0x00, 0x04, 0xDB, 0xFD, 0xAC, 0x3F, 0x6F, 0x9D, 0x1A, 0xE7, 0x53, 0xFD, 0x99, 0xEC, 0x74, 0x79,
+	0xBE, 0xC2, 0xDB, 0x6E, 0x1B, 0x54, 0x9B, 0x6A, 0xED, 0xA0, 0x0F, 0x40, 0x5F, 0xF8, 0x38, 0x2B,
+	0xFE, 0x0B, 0xA6, 0xB3, 0x2C, 0xD0, 0xFC, 0x5A, 0xF0, 0x0A, 0xB4, 0x6D, 0xBD, 0x56, 0x4D, 0x2E,
+	0x36, 0x5F, 0xF7, 0x59, 0x7F, 0x8A, 0xBE, 0x67, 0xF8, 0x81, 0xE3, 0xEF, 0x1C, 0x7C, 0x73, 0xF8,
+	0xB1, 0xE2, 0xAF, 0xDA, 0x1B, 0xE3, 0xBB, 0xE9, 0xBA, 0xB7, 0x8D, 0xFC, 0x70, 0xDB, 0xFC, 0x51,
+	0x71, 0x1D, 0xBA, 0xB5, 0xB7, 0x99, 0xB7, 0x6E, 0xE8, 0x17, 0xF8, 0x59, 0x6B, 0xEC, 0x48, 0xFF,
+	0x00, 0xE0, 0xDC, 0x6F, 0xF8, 0x2A, 0xF4, 0xD3, 0xA5, 0xAC, 0x5A, 0x2F, 0x84, 0xD5, 0x9A, 0x4C,
+	0x33, 0x49, 0x74, 0xAA, 0xAB, 0x5F, 0x1C, 0xFC, 0x76, 0xF8, 0x7B, 0xE2, 0xAF, 0xD9, 0x97, 0xE3,
+	0x67, 0x89, 0xFE, 0x02, 0x7C, 0x5A, 0x9A, 0xCE, 0xDF, 0xC4, 0x1E, 0x13, 0x97, 0xCA, 0xD6, 0x56,
+	0xDE, 0x5F, 0xDD, 0x79, 0x9F, 0xDD, 0x8F, 0xFB, 0xCD, 0x40, 0x1F, 0x6D, 0xFF, 0x00, 0xC1, 0x2C,
+	0xBF, 0xE0, 0xB9, 0x3E, 0x32, 0xFF, 0x00, 0x82, 0x7C, 0x7C, 0x21, 0x93, 0xE0, 0x2F, 0xC7, 0xED,
+	0x1F, 0x52, 0xF8, 0x81, 0xE0, 0x7D, 0x36, 0xE3, 0x7F, 0x83, 0xE2, 0x8D, 0xBC, 0xCD, 0x4A, 0xDD,
+	0x99, 0xBE, 0x6F, 0x36, 0x4F, 0xE2, 0x8D, 0x7F, 0xBB, 0x5F, 0xB7, 0x7F, 0xB3, 0x37, 0xED, 0x33,
+	0xF0, 0x33, 0xF6, 0xBA, 0xF8, 0x47, 0x63, 0xF1, 0xD7, 0xE0, 0x07, 0xC4, 0x4B, 0x1F, 0x12, 0xE8,
+	0xDA, 0x84, 0x6A, 0xB7, 0x57, 0x1A, 0x7C, 0x9F, 0x2D, 0x8D, 0xC6, 0xD5, 0xDD, 0x6B, 0x27, 0xFB,
+	0x4A, 0xDF, 0x2F, 0xFC, 0x06, 0xBF, 0x04, 0x3F, 0x61, 0xFF, 0x00, 0xF8, 0x22, 0x2F, 0xED, 0x67,
+	0xFB, 0x67, 0x68, 0xFE, 0x0B, 0xF8, 0xC7, 0xE2, 0xAB, 0x65, 0xF0, 0x97, 0xC1, 0x8F, 0x12, 0x5E,
+	0x6D, 0xF1, 0x05, 0xF4, 0xDF, 0xBA, 0xD6, 0xAD, 0xE1, 0x56, 0xFB, 0xD1, 0xC7, 0xF7, 0xB6, 0xB7,
+	0xF7, 0xAB, 0xF7, 0xAF, 0xF6, 0x65, 0xFD, 0x9C, 0x3E, 0x02, 0xFE, 0xC8, 0x7F, 0x09, 0x6C, 0xBE,
+	0x0A, 0x7E, 0xCE, 0x9F, 0x0F, 0xAC, 0xFC, 0x3D, 0xE1, 0xAB, 0x3D, 0xA1, 0x60, 0xB3, 0x5D, 0xBF,
+	0x6F, 0x9B, 0xFE, 0x7E, 0x65, 0xFF, 0x00, 0xA6, 0x8D, 0xFC, 0x54, 0x01, 0x73, 0xE2, 0x8F, 0xFC,
+	0x78, 0xC9, 0x5E, 0xAD, 0xF0, 0x9B, 0xFE, 0x49, 0xEE, 0x93, 0xFF, 0x00, 0x5E, 0xD5, 0xE4, 0xBF,
+	0x14, 0xA4, 0xC5, 0x8C, 0x88, 0xFB, 0x6B, 0xD6, 0xBE, 0x13, 0x9F, 0xF8, 0xB7, 0x5A, 0x3F, 0xFD,
+	0x7B, 0xFF, 0x00, 0x8D, 0x00, 0x74, 0x94, 0x51, 0x45, 0x00, 0x14, 0x8F, 0xF7, 0x69, 0x69, 0x1F,
+	0xEE, 0xD0, 0x07, 0x87, 0x78, 0xF3, 0xFE, 0x4B, 0x06, 0xA1, 0xFF, 0x00, 0x5E, 0xEB, 0x5F, 0x96,
+	0xFF, 0x00, 0xF0, 0x78, 0xA7, 0xFC, 0xA3, 0xC7, 0xE1, 0x1F, 0xFD, 0x8F, 0x33, 0x7F, 0xE8, 0x96,
+	0xAF, 0xD4, 0x7F, 0x88, 0x2F, 0xB7, 0xE2, 0xEE, 0xA1, 0xFF, 0x00, 0x5C, 0x56, 0xBF, 0x2D, 0xBF,
+	0xE0, 0xF1, 0x26, 0xDD, 0xFF, 0x00, 0x04, 0xF1, 0xF8, 0x49, 0xFF, 0x00, 0x63, 0xCC, 0xDF, 0xFA,
+	0x25, 0xA8, 0x03, 0xF9, 0xC5, 0xBB, 0xFF, 0x00, 0x8F, 0xB9, 0x3F, 0x87, 0xE6, 0xA8, 0xC0, 0x18,
+	0xDC, 0x8D, 0xCF, 0xF7, 0x6A, 0x5B, 0xCF, 0x9A, 0xEE, 0x4D, 0xDF, 0xDE, 0xA6, 0x7C, 0xD9, 0xDA,
+	0x89, 0xB7, 0x6F, 0xF1, 0x50, 0x07, 0xD4, 0x5F, 0xF0, 0x4A, 0x9F, 0xD8, 0xBB, 0x41, 0xFD, 0xAF,
+	0x7F, 0x6A, 0x3D, 0x16, 0xC7, 0xE3, 0x1E, 0x8B, 0xAA, 0x47, 0xF0, 0x87, 0xC3, 0xB3, 0x7D, 0xB7,
+	0xE2, 0xDF, 0x8A, 0xAD, 0x5B, 0xC9, 0x83, 0x40, 0xD3, 0xD5, 0x24, 0x6F, 0x32, 0x69, 0x7F, 0xE5,
+	0x9A, 0xB3, 0x2A, 0xC7, 0xFF, 0x00, 0x02, 0xFF, 0x00, 0x66, 0xBF, 0x55, 0x3C, 0x45, 0xA8, 0xF8,
+	0xD7, 0xFE, 0x0B, 0xEB, 0xF1, 0x5D, 0x3F, 0x65, 0xFF, 0x00, 0xD9, 0xDA, 0x4F, 0xF8, 0x54, 0x3F,
+	0xB0, 0x3F, 0xC0, 0x89, 0x96, 0x2D, 0x73, 0x5D, 0xB5, 0x3F, 0x62, 0x83, 0x5E, 0x8E, 0xDB, 0xFE,
+	0x5A, 0x6E, 0x6D, 0xAA, 0xCC, 0xDB, 0x4B, 0x2A, 0xB7, 0xFA, 0xB5, 0x66, 0x95, 0xB7, 0x48, 0xD5,
+	0xF9, 0xEB, 0xFF, 0x00, 0x04, 0x5E, 0xFD, 0x82, 0xFF, 0x00, 0x6C, 0x7F, 0xF8, 0x28, 0x2F, 0x8E,
+	0x3C, 0x45, 0xF0, 0x1B, 0xE1, 0x07, 0xC4, 0x4D, 0x5F, 0xC1, 0xFF, 0x00, 0x0A, 0x75, 0x98, 0xAD,
+	0xDB, 0xE3, 0x06, 0xB0, 0xB7, 0x4D, 0x0D, 0x9D, 0xDD, 0x8C, 0x52, 0xB4, 0x9E, 0x5B, 0x1F, 0xF9,
+	0x68, 0xDF, 0xEC, 0xEE, 0xFF, 0x00, 0x7A, 0xBF, 0x45, 0xBF, 0x6A, 0xFF, 0x00, 0x8A, 0x89, 0xF1,
+	0xEE, 0x0D, 0x1F, 0xFE, 0x0D, 0xF5, 0xFF, 0x00, 0x82, 0x2F, 0xF8, 0x5B, 0x1E, 0x02, 0xD3, 0xA2,
+	0x5B, 0x1F, 0x89, 0xDE, 0x32, 0xB1, 0x5F, 0x32, 0x19, 0x63, 0xDC, 0xBE, 0x7E, 0xF9, 0x7F, 0x89,
+	0x9B, 0x6E, 0xE6, 0x6D, 0xDF, 0x35, 0x00, 0x73, 0x7F, 0x14, 0xFF, 0x00, 0x69, 0x0F, 0x8F, 0x7F,
+	0xF0, 0x52, 0x9F, 0x14, 0x5B, 0x7F, 0xC1, 0x30, 0x7F, 0xE0, 0x89, 0x1F, 0x0F, 0xAE, 0xBC, 0x0F,
+	0xFB, 0x2C, 0x78, 0x26, 0x58, 0xF4, 0x3F, 0x17, 0x78, 0xEB, 0x49, 0xB2, 0xF2, 0xA2, 0xD5, 0x37,
+	0x37, 0xEF, 0x26, 0x69, 0x7E, 0xF7, 0x96, 0xDB, 0x77, 0x2F, 0xF1, 0x49, 0xFE, 0xB1, 0xB6, 0xAE,
+	0xDA, 0xED, 0xBF, 0x68, 0x7F, 0x8D, 0xBE, 0x15, 0xFF, 0x00, 0x82, 0x77, 0xF8, 0x2F, 0xC3, 0xBF,
+	0xF0, 0x46, 0x0F, 0xF8, 0x23, 0x76, 0x89, 0x1F, 0x89, 0x3E, 0x2F, 0x78, 0xD2, 0x58, 0xAD, 0x7C,
+	0x7D, 0xE3, 0x8D, 0x36, 0x2F, 0x3A, 0x7B, 0x4F, 0x39, 0xB6, 0xCA, 0xCF, 0x22, 0xFF, 0x00, 0xBC,
+	0x7E, 0x66, 0x6A, 0xD0, 0xF8, 0xDF, 0xFB, 0x5E, 0xF8, 0x2F, 0xFE, 0x08, 0xA1, 0xF0, 0x97, 0x4A,
+	0xFF, 0x00, 0x82, 0x42, 0x7F, 0xC1, 0x2B, 0xFC, 0x20, 0xBF, 0x13, 0x3E, 0x32, 0x78, 0xCE, 0x36,
+	0xB5, 0xD5, 0x26, 0xB3, 0xDD, 0x72, 0xBA, 0x7E, 0xA1, 0x70, 0xBE, 0x5F, 0x9C, 0xCA, 0xBF, 0x7A,
+	0x4F, 0xDE, 0x7D, 0xD6, 0xF9, 0x57, 0x6F, 0xCD, 0xB7, 0x6D, 0x72, 0x7E, 0x1E, 0x8B, 0xC1, 0x3F,
+	0xF0, 0x6E, 0x3F, 0xC0, 0xD6, 0xF0, 0xAE, 0x94, 0x61, 0xF8, 0xB9, 0xFB, 0x79, 0xFC, 0x7A, 0x58,
+	0xD5, 0xB4, 0xBB, 0x56, 0xFB, 0x52, 0xF8, 0x7F, 0xED, 0x2E, 0xDB, 0x7E, 0xEF, 0xCC, 0xDF, 0x33,
+	0x37, 0xFB, 0x53, 0x49, 0xFD, 0xD8, 0xD7, 0xE6, 0x00, 0xFC, 0x9A, 0xFF, 0x00, 0x82, 0xAB, 0x7E,
+	0xC6, 0x7A, 0xB7, 0xEC, 0x21, 0xFB, 0x69, 0xF8, 0x8B, 0xF6, 0x74, 0xD7, 0x3C, 0x7B, 0x27, 0x88,
+	0xF5, 0x2B, 0x0B, 0x1B, 0x5B, 0xDD, 0x4F, 0x55, 0x9A, 0x40, 0xEC, 0xF7, 0x13, 0x47, 0xE6, 0x48,
+	0xAC, 0xDF, 0xEC, 0xB5, 0x7C, 0xD8, 0x8C, 0xE8, 0x37, 0xA3, 0x7C, 0xDB, 0xBF, 0xE0, 0x55, 0xEF,
+	0xBF, 0xF0, 0x52, 0x1F, 0x81, 0xDF, 0xB5, 0xA7, 0xEC, 0xFB, 0xFB, 0x57, 0x6B, 0xDE, 0x09, 0xFD,
+	0xB6, 0x35, 0x19, 0x2F, 0x7E, 0x24, 0x5E, 0x5B, 0x5B, 0xEA, 0xDA, 0xF5, 0xC4, 0xD7, 0xDE, 0x7B,
+	0x6D, 0xBA, 0x8F, 0xCC, 0x55, 0xDD, 0xFF, 0x00, 0x02, 0xFE, 0x1A, 0xF0, 0x25, 0xFB, 0xEA, 0xD1,
+	0xFF, 0x00, 0xDF, 0x34, 0x01, 0xF4, 0x4F, 0xFC, 0x13, 0x57, 0xF6, 0xFC, 0xF8, 0xD7, 0xFF, 0x00,
+	0x04, 0xE7, 0xFD, 0xA8, 0x34, 0x3F, 0x8E, 0xDF, 0x06, 0xBC, 0x4F, 0x15, 0x87, 0x99, 0x71, 0x1D,
+	0xA7, 0x88, 0xAC, 0xEE, 0xA3, 0xF3, 0x2D, 0x6E, 0xB4, 0xF6, 0x64, 0xF3, 0x43, 0xC7, 0xD3, 0x76,
+	0xDD, 0xDB, 0x5B, 0xF8, 0x5A, 0xBF, 0xAF, 0x9F, 0x82, 0x5F, 0x1C, 0xBE, 0x1E, 0xFE, 0xD2, 0x9F,
+	0x03, 0xB4, 0x1F, 0x8E, 0xBF, 0x08, 0xAF, 0xE3, 0xB8, 0xF0, 0xEF, 0x89, 0xAC, 0xE3, 0xB8, 0xB0,
+	0x99, 0x7F, 0xBD, 0xB7, 0x73, 0xFF, 0x00, 0xE3, 0xD5, 0xFC, 0x40, 0xAB, 0x92, 0xCD, 0x09, 0x19,
+	0x69, 0x3E, 0x4F, 0xF7, 0x7E, 0x6A, 0xFE, 0x99, 0xBF, 0xE0, 0xD5, 0xEF, 0xDB, 0x7B, 0xC5, 0x5F,
+	0xB4, 0xBF, 0xEC, 0x1F, 0xAA, 0x7E, 0xCE, 0x7E, 0x21, 0xF0, 0x75, 0x9D, 0x8D, 0xAF, 0xC1, 0x58,
+	0x61, 0xB3, 0xD2, 0xF5, 0x0B, 0x56, 0x6D, 0xD7, 0xD1, 0xC9, 0xB9, 0xBF, 0x79, 0xFE, 0xD7, 0xCC,
+	0xD4, 0x01, 0xFA, 0x21, 0xE1, 0x16, 0x79, 0xBE, 0x32, 0x69, 0xAE, 0x8B, 0xF7, 0x64, 0xFF, 0x00,
+	0xBE, 0xAB, 0xDF, 0x55, 0xB3, 0x5E, 0x01, 0xE0, 0xE9, 0xB7, 0x7C, 0x64, 0xD3, 0xE1, 0xDE, 0xDB,
+	0xD9, 0xBE, 0x65, 0x5F, 0xE1, 0xAF, 0x7F, 0x55, 0xDB, 0x40, 0x0B, 0x45, 0x14, 0x50, 0x01, 0x58,
+	0x7F, 0x11, 0x59, 0x47, 0x81, 0xF5, 0x4D, 0xE3, 0x2B, 0xF6, 0x56, 0xAD, 0xCA, 0xC3, 0xF8, 0x8C,
+	0xD8, 0xF0, 0x3E, 0xAD, 0xBB, 0xFE, 0x7C, 0xDA, 0x80, 0x3E, 0x6E, 0xF1, 0xA7, 0xED, 0x0B, 0xF0,
+	0x3F, 0xF6, 0x4F, 0xF8, 0x37, 0x7B, 0xF1, 0xBF, 0xF6, 0x80, 0xF1, 0xC5, 0xBE, 0x87, 0xE1, 0x7D,
+	0x36, 0xD5, 0x9F, 0xED, 0x17, 0x4D, 0xFF, 0x00, 0x1F, 0xB3, 0x2E, 0xEF, 0xF4, 0x54, 0xFF, 0x00,
+	0xA6, 0x8D, 0x5F, 0xCE, 0x2F, 0xFC, 0x15, 0x6F, 0xFE, 0x0A, 0x89, 0xF1, 0x5B, 0xFE, 0x0A, 0x93,
+	0xF1, 0xE5, 0x7C, 0x6B, 0xAF, 0x35, 0xD6, 0x8D, 0xF0, 0xE7, 0xC3, 0xB2, 0xC9, 0x07, 0x81, 0x7C,
+	0x1F, 0xBB, 0x68, 0xF2, 0x77, 0x7F, 0xAC, 0xBB, 0x5F, 0xF9, 0x68, 0xCD, 0xB7, 0xE5, 0x6A, 0xFE,
+	0x8E, 0xBC, 0x5D, 0xF0, 0x1F, 0xE0, 0xAF, 0xED, 0x3F, 0xF0, 0x6A, 0xF3, 0xE0, 0xBF, 0xED, 0x01,
+	0xE0, 0x4B, 0x3D, 0x7F, 0xC2, 0xBA, 0x9D, 0xAB, 0x23, 0x5A, 0xDE, 0x2E, 0xEF, 0xB1, 0x48, 0xDB,
+	0xBF, 0xD2, 0x93, 0xFE, 0x9A, 0x2F, 0xDE, 0xAF, 0xE7, 0x33, 0xFE, 0x0A, 0xBF, 0xFF, 0x00, 0x04,
+	0xAC, 0xF8, 0xA1, 0xFF, 0x00, 0x04, 0xBA, 0xF8, 0xD4, 0xBA, 0x0E, 0xA2, 0x6F, 0x35, 0xCF, 0x86,
+	0x9E, 0x22, 0x99, 0xA5, 0xF0, 0x1F, 0x8B, 0xB6, 0xEE, 0xF2, 0xE1, 0x6F, 0xF9, 0x67, 0x76, 0xDF,
+	0xF2, 0xCD, 0xBF, 0xBB, 0x40, 0x1F, 0x2D, 0x47, 0x27, 0x99, 0x23, 0x3F, 0xFD, 0x32, 0x6F, 0xF8,
+	0x0F, 0xCB, 0x5F, 0xD1, 0x1F, 0xFC, 0x1A, 0xBB, 0xFF, 0x00, 0x28, 0x91, 0x43, 0xB1, 0x9B, 0xFE,
+	0x2B, 0x4B, 0x8F, 0x95, 0x7F, 0xDE, 0x5A, 0xFE, 0x77, 0x21, 0x8F, 0xCB, 0xDD, 0xFF, 0x00, 0x5C,
+	0xDB, 0x6F, 0xFB, 0x5F, 0x2D, 0x7F, 0x43, 0xFF, 0x00, 0xF0, 0x6A, 0xFC, 0x8E, 0xBF, 0xF0, 0x49,
+	0x34, 0x74, 0xF9, 0x5B, 0xFE, 0x13, 0x7B, 0x8F, 0xFD, 0x09, 0x6A, 0x2E, 0xC0, 0xFD, 0x08, 0xF1,
+	0xEF, 0x8C, 0x34, 0xDF, 0x02, 0x78, 0x1F, 0xC4, 0x1F, 0x11, 0xFC, 0x43, 0x67, 0x24, 0xDA, 0x7F,
+	0x86, 0x74, 0x69, 0xB5, 0x0B, 0xEB, 0x38, 0x7F, 0xD6, 0x5C, 0x43, 0x1A, 0xB3, 0x32, 0xAF, 0xFB,
+	0x5F, 0x2D, 0x7F, 0x30, 0x7F, 0xF0, 0x53, 0xAF, 0xF8, 0x2B, 0x8F, 0xC7, 0x2F, 0xF8, 0x29, 0x27,
+	0xC7, 0x45, 0xF8, 0x8B, 0xA1, 0x78, 0xA3, 0x5A, 0xF0, 0x7F, 0x81, 0xFC, 0x39, 0x71, 0x25, 0xAF,
+	0x80, 0xF4, 0x3D, 0x1E, 0xF1, 0xA0, 0x9A, 0x38, 0xD5, 0xB6, 0xB7, 0xDA, 0x76, 0xFD, 0xE6, 0xAF,
+	0xE9, 0xB3, 0xE2, 0xCF, 0x86, 0x75, 0x5F, 0x1F, 0xFC, 0x1D, 0xF1, 0x97, 0xC3, 0xAF, 0x0C, 0x4D,
+	0x1F, 0xF6, 0xA7, 0x89, 0x3C, 0x39, 0x71, 0xA6, 0xE9, 0xCD, 0x71, 0xF2, 0xC7, 0xF6, 0x89, 0x23,
+	0x65, 0x5D, 0xDF, 0xEC, 0xFC, 0xD5, 0xFC, 0x8B, 0xFE, 0xD1, 0x9F, 0xB3, 0x9F, 0xC5, 0x9F, 0xD8,
+	0xC7, 0xE3, 0x36, 0xB5, 0xFB, 0x3E, 0x7E, 0xD0, 0xDA, 0x3F, 0xF6, 0x3F, 0x88, 0xB4, 0x3D, 0x4A,
+	0x6F, 0x36, 0x6B, 0x8F, 0x92, 0xD6, 0xF9, 0x64, 0x93, 0x72, 0xB4, 0x0D, 0xFF, 0x00, 0x2D, 0x16,
+	0x9F, 0x30, 0x1E, 0xF1, 0xFF, 0x00, 0x04, 0xC6, 0xFF, 0x00, 0x82, 0xB6, 0xFC, 0x74, 0xFF, 0x00,
+	0x82, 0x69, 0x7C, 0x70, 0x6F, 0x88, 0x9A, 0xC7, 0x8B, 0xB5, 0xAF, 0x18, 0x78, 0x0F, 0x5F, 0x9E,
+	0x38, 0x7C, 0x7D, 0xA1, 0xEB, 0x17, 0x8D, 0x3C, 0xF3, 0x46, 0xCD, 0xB5, 0x7E, 0xCD, 0xBB, 0xEE,
+	0xB5, 0x7F, 0x4F, 0xDE, 0x07, 0xF1, 0x7E, 0x9B, 0xF1, 0x27, 0xC0, 0xBE, 0x1F, 0xF8, 0x8B, 0xA0,
+	0xD9, 0xC9, 0x6B, 0xA7, 0xF8, 0x8B, 0x46, 0x87, 0x54, 0xD3, 0x6D, 0x66, 0xFF, 0x00, 0x59, 0x0C,
+	0x32, 0x2A, 0xB2, 0xC6, 0xDF, 0xED, 0x7C, 0xD5, 0xFC, 0x82, 0xFE, 0xCE, 0xDF, 0xB3, 0xC7, 0xC5,
+	0x7F, 0xDB, 0x23, 0xE3, 0x56, 0x83, 0xFB, 0x3A, 0xFE, 0xCE, 0xBA, 0x17, 0xF6, 0xE7, 0x89, 0xB5,
+	0xCD, 0x46, 0x16, 0x4B, 0x88, 0xFF, 0x00, 0x79, 0x6B, 0xA7, 0xAC, 0x6D, 0xB9, 0x9A, 0x76, 0xFE,
+	0x15, 0xAF, 0xEB, 0xB3, 0xE1, 0x3F, 0x87, 0x35, 0x3F, 0x03, 0x7C, 0x1F, 0xF0, 0x6F, 0xC3, 0xBF,
+	0x12, 0x4F, 0x1F, 0xF6, 0xA7, 0x86, 0x7C, 0x3B, 0x6F, 0xA6, 0xEA, 0xCD, 0x0F, 0xFA, 0xBF, 0x3A,
+	0x38, 0xD5, 0x5B, 0x6F, 0xFB, 0x3F, 0x2D, 0x11, 0x03, 0xE0, 0x9F, 0xF8, 0x3A, 0x7B, 0xE6, 0xFF,
+	0x00, 0x82, 0x49, 0x36, 0xEF, 0xFA, 0x1D, 0x2D, 0xFF, 0x00, 0xF4, 0x26, 0xAF, 0xE7, 0x7A, 0x46,
+	0xFD, 0xF2, 0x67, 0xFE, 0x79, 0x2F, 0xFC, 0x0B, 0xE5, 0xAF, 0xE8, 0x7F, 0xFE, 0x0E, 0xA0, 0x7C,
+	0xFF, 0x00, 0xC1, 0x25, 0xD8, 0xA7, 0xFD, 0x0E, 0x90, 0xED, 0xFF, 0x00, 0xBE, 0xAB, 0xF9, 0xE0,
+	0x66, 0xF3, 0x24, 0x4F, 0x9F, 0xE5, 0x58, 0x95, 0x99, 0xBF, 0xBB, 0xF2, 0xD3, 0x96, 0xC0, 0x7D,
+	0x47, 0xFF, 0x00, 0x04, 0xA2, 0xFF, 0x00, 0x82, 0xA6, 0xFC, 0x56, 0xFF, 0x00, 0x82, 0x5C, 0xFC,
+	0x6F, 0x6F, 0x13, 0xE8, 0x89, 0x75, 0xAE, 0x7C, 0x37, 0xF1, 0x04, 0xAB, 0x17, 0x8E, 0xBC, 0x1E,
+	0xAD, 0xBB, 0x6C, 0x3B, 0xBF, 0xD6, 0x5A, 0x2F, 0xFC, 0xB3, 0x65, 0xFE, 0x2A, 0xFE, 0x92, 0x3E,
+	0x18, 0x7E, 0xD1, 0x3F, 0x03, 0xBF, 0x6B, 0x0F, 0x82, 0x7A, 0x7F, 0xC7, 0x1F, 0xD9, 0xF7, 0xC6,
+	0xD6, 0xFE, 0x20, 0xF0, 0xBE, 0xA5, 0x1A, 0x94, 0x9A, 0xCD, 0xFF, 0x00, 0xE3, 0xCA, 0x66, 0x5F,
+	0xF8, 0xF6, 0x7F, 0xFA, 0x68, 0xBF, 0x76, 0xBF, 0x9B, 0xBF, 0xF8, 0x24, 0xE7, 0xFC, 0x12, 0xB3,
+	0xE2, 0xB7, 0xFC, 0x15, 0x1B, 0xE3, 0x3B, 0x68, 0x9A, 0x73, 0xDD, 0x68, 0x7F, 0x0B, 0xBC, 0x3F,
+	0x3A, 0xCB, 0xE3, 0x9F, 0x18, 0x46, 0xBB, 0x7C, 0xC8, 0xD7, 0xE6, 0xF2, 0xED, 0x1B, 0xFE, 0x5A,
+	0x37, 0xF7, 0xAB, 0xFA, 0x44, 0xF8, 0x6D, 0xF0, 0x13, 0xE0, 0xAF, 0xEC, 0xBB, 0xF0, 0x5A, 0xC3,
+	0xE0, 0x8F, 0xEC, 0xF5, 0xE0, 0x7B, 0x3F, 0x0E, 0xF8, 0x5B, 0x4C, 0xB7, 0x54, 0x8E, 0xDA, 0xCD,
+	0x76, 0xFD, 0xB6, 0x45, 0x55, 0xFF, 0x00, 0x49, 0x7F, 0xFA, 0x68, 0xDF, 0x79, 0xA8, 0x5B, 0x01,
+	0xEA, 0x3F, 0xB3, 0x4B, 0x2B, 0x78, 0x4A, 0xF3, 0x62, 0x6D, 0x5F, 0xB6, 0xB5, 0x7A, 0x4D, 0x79,
+	0xAF, 0xEC, 0xCA, 0xC8, 0xDE, 0x0E, 0xBC, 0xD9, 0xFF, 0x00, 0x3F, 0xAD, 0x5E, 0x95, 0x4C, 0x02,
+	0x8A, 0x28, 0xA0, 0x06, 0xC8, 0x37, 0x21, 0x18, 0xAF, 0x27, 0xFD, 0xA0, 0xD5, 0x24, 0xF1, 0x4E,
+	0x87, 0xBA, 0x4C, 0x36, 0xD6, 0xDA, 0xB5, 0xEB, 0x12, 0xAE, 0x50, 0xE1, 0xF6, 0xD7, 0x92, 0x7E,
+	0xD0, 0xEE, 0x9F, 0xF0, 0x92, 0xE8, 0x3F, 0x27, 0xCC, 0xCA, 0xDF, 0x35, 0x00, 0x5D, 0xF0, 0xAE,
+	0x97, 0x79, 0xAA, 0x69, 0xEB, 0xF6, 0x0B, 0x6D, 0xEC, 0xAC, 0xBB, 0x97, 0x72, 0xAE, 0xDF, 0x9A,
+	0xBF, 0x15, 0xFF, 0x00, 0xE0, 0xE6, 0xDF, 0x1F, 0x78, 0xB6, 0xC7, 0xF6, 0xA9, 0xD2, 0xFE, 0x14,
+	0x25, 0xCC, 0xD1, 0xE9, 0x2B, 0xA1, 0xC7, 0x79, 0x15, 0xAB, 0x4B, 0xBA, 0x36, 0x66, 0xFE, 0x25,
+	0x5F, 0xEF, 0x57, 0xE8, 0x6F, 0xFC, 0x14, 0xCB, 0xE1, 0x67, 0xC4, 0xFF, 0x00, 0x88, 0x7F, 0xB2,
+	0x06, 0xA9, 0xE3, 0x5F, 0x82, 0xDF, 0x15, 0xFC, 0x41, 0xE1, 0x9F, 0x15, 0x78, 0x46, 0xDD, 0xAE,
+	0x74, 0x9B, 0x7D, 0x05, 0x9B, 0x76, 0xA8, 0xDF, 0xDD, 0x91, 0x56, 0xBF, 0x9E, 0x3F, 0x8D, 0x1F,
+	0x10, 0x3E, 0x3F, 0x7C, 0x44, 0xF1, 0x93, 0x6B, 0x9F, 0xB4, 0x9F, 0x8E, 0x75, 0x8D, 0x6F, 0xC4,
+	0x50, 0xC5, 0xE5, 0x4B, 0x26, 0xB1, 0xBB, 0xCD, 0x87, 0xFD, 0x9F, 0x9A, 0x80, 0x3E, 0xDD, 0xFF,
+	0x00, 0x83, 0x66, 0xAC, 0x2F, 0xAE, 0x3F, 0xE0, 0xA4, 0x57, 0x37, 0x96, 0x30, 0xFC, 0xAB, 0xE1,
+	0x29, 0xBC, 0xE6, 0xDD, 0xB7, 0xE5, 0xDB, 0x5F, 0xBC, 0x97, 0x16, 0x37, 0x5A, 0x64, 0x8D, 0x0E,
+	0xA5, 0x6D, 0xE5, 0xC9, 0x23, 0x36, 0xD6, 0xDC, 0xAC, 0xBF, 0x7A, 0xBF, 0x93, 0x1F, 0x87, 0x5F,
+	0x17, 0x3E, 0x30, 0x7C, 0x17, 0xF1, 0x22, 0xF8, 0xB7, 0xE0, 0x9F, 0xC4, 0x5D, 0x4B, 0xC3, 0xBA,
+	0xF4, 0x91, 0x79, 0x56, 0xF7, 0x1A, 0x6B, 0x6D, 0x96, 0xE3, 0xFE, 0x99, 0xAF, 0xF7, 0xB7, 0x57,
+	0xF4, 0x4F, 0xFF, 0x00, 0x04, 0x90, 0xF8, 0x6B, 0xF1, 0x0B, 0xC1, 0x3F, 0xB2, 0x16, 0x95, 0xF1,
+	0x37, 0xE2, 0xEF, 0xC5, 0x3F, 0x13, 0x78, 0x9B, 0xC4, 0x5E, 0x3A, 0xB7, 0x5B, 0xAD, 0x4A, 0xD3,
+	0xC4, 0xDB, 0xB7, 0xE9, 0x2D, 0xFD, 0xD8, 0xD5, 0xBE, 0xED, 0x00, 0x7D, 0x43, 0x18, 0xDB, 0x0F,
+	0xCF, 0xF2, 0xB3, 0x7D, 0xDD, 0xD4, 0x7F, 0xBF, 0xF7, 0xA9, 0x8D, 0x22, 0x37, 0xEE, 0x67, 0x3F,
+	0x3D, 0x2F, 0x9C, 0x89, 0xC6, 0xFA, 0x00, 0x75, 0x12, 0x6C, 0xCA, 0xF9, 0xC8, 0xCD, 0xFE, 0xED,
+	0x47, 0xF6, 0x88, 0x7F, 0xBF, 0x4A, 0xB7, 0x29, 0x1F, 0xC8, 0xEF, 0xB9, 0x9B, 0xEE, 0xD0, 0x04,
+	0xF6, 0xB2, 0x7D, 0x9E, 0xE2, 0x44, 0x78, 0x5B, 0x64, 0x96, 0xB2, 0x27, 0xFB, 0xBB, 0x97, 0x6D,
+	0x7F, 0x33, 0x3F, 0xF0, 0x53, 0x7F, 0xD9, 0xD6, 0xC3, 0xF6, 0x75, 0xFD, 0xB3, 0x3C, 0x4F, 0xE1,
+	0xBD, 0x1E, 0xF5, 0xA4, 0xB7, 0xD5, 0xB5, 0x29, 0x35, 0x26, 0x66, 0x6F, 0xBA, 0xCC, 0xDB, 0xAB,
+	0xFA, 0x62, 0xB7, 0x64, 0x9A, 0xE1, 0x91, 0x26, 0xFD, 0xE2, 0xDB, 0xC8, 0xED, 0xFD, 0xDF, 0x95,
+	0x6B, 0xF9, 0xAA, 0xFF, 0x00, 0x82, 0xAA, 0x7C, 0x60, 0xB6, 0xF8, 0xC1, 0xFB, 0x6C, 0xF8, 0x8A,
+	0xFE, 0xC2, 0x65, 0x78, 0xF4, 0xFB, 0xC9, 0x2C, 0xD9, 0xA3, 0x7F, 0x97, 0x72, 0xB5, 0x00, 0x7E,
+	0x97, 0xFF, 0x00, 0xC1, 0xB0, 0x71, 0xDB, 0x5A, 0xFE, 0xC3, 0xFE, 0x39, 0xD9, 0x6C, 0xA8, 0xAD,
+	0xE2, 0xAF, 0x9B, 0x6A, 0x7D, 0xEA, 0xFB, 0x9B, 0xC7, 0x8B, 0xFF, 0x00, 0x13, 0xCB, 0x50, 0x3F,
+	0xE7, 0xE9, 0x6B, 0xE1, 0x5F, 0xF8, 0x36, 0x1F, 0x50, 0xB3, 0xBA, 0xFD, 0x86, 0xFC, 0x75, 0x0C,
+	0x37, 0x31, 0xBB, 0x47, 0xE2, 0xAD, 0xAD, 0xB5, 0xBE, 0xED, 0x7D, 0xD1, 0xE3, 0xA9, 0x8B, 0x6B,
+	0x16, 0x69, 0xFF, 0x00, 0x4F, 0x4B, 0xFF, 0x00, 0xA1, 0x50, 0x07, 0xD1, 0x16, 0x5F, 0xF1, 0xEB,
+	0x17, 0xFD, 0x73, 0x5A, 0x9A, 0xAB, 0xD8, 0x7F, 0xC7, 0xB4, 0x3F, 0xF5, 0xC5, 0x6A, 0xC5, 0x00,
+	0x14, 0x51, 0x45, 0x00, 0x35, 0xBA, 0xB7, 0xFB, 0xB5, 0xF3, 0xFF, 0x00, 0x84, 0xD8, 0xAF, 0x88,
+	0xAF, 0xE4, 0x4F, 0xFA, 0x09, 0x49, 0x5F, 0x40, 0x3F, 0x7F, 0xF7, 0x6B, 0xE7, 0xBF, 0x0B, 0xB6,
+	0xEF, 0x12, 0x5F, 0xA6, 0xFF, 0x00, 0xF9, 0x89, 0x49, 0x40, 0x16, 0x3E, 0x3E, 0x7E, 0xD2, 0x9F,
+	0xB3, 0xE7, 0xEC, 0xBB, 0xF0, 0xF6, 0x6F, 0x89, 0x1F, 0xB4, 0x97, 0xC5, 0xFD, 0x2F, 0xC1, 0x1A,
+	0x0A, 0xCD, 0xE5, 0xC5, 0xA9, 0x6B, 0x0D, 0xB6, 0x39, 0xA6, 0xFF, 0x00, 0x9E, 0x6B, 0xFE, 0xD5,
+	0x7E, 0x33, 0xFF, 0x00, 0xC1, 0x49, 0xFF, 0x00, 0xE0, 0xED, 0x3D, 0x4E, 0xC6, 0xFE, 0xE3, 0xE1,
+	0xCF, 0xFC, 0x13, 0x9B, 0xC3, 0x3F, 0xD9, 0x37, 0x9A, 0x7C, 0xCD, 0x6F, 0x7F, 0xE2, 0xCD, 0x6A,
+	0x38, 0xE7, 0xB6, 0xBF, 0x5F, 0xF9, 0xE9, 0x04, 0x7B, 0xBF, 0xF4, 0x2A, 0xFD, 0x92, 0xFD, 0xA2,
+	0xFF, 0x00, 0x67, 0x5F, 0x80, 0x7F, 0xB5, 0x77, 0xC3, 0x6B, 0xAF, 0x84, 0xDF, 0xB4, 0x5F, 0xC2,
+	0xAD, 0x2F, 0xC5, 0xDA, 0x0C, 0xF1, 0xB0, 0x4B, 0x3D, 0x51, 0x77, 0x2D, 0xBC, 0xDF, 0xC3, 0x32,
+	0xFF, 0x00, 0xB4, 0xB5, 0xF8, 0xB3, 0xFF, 0x00, 0x05, 0x06, 0xFF, 0x00, 0x83, 0x48, 0x75, 0x6D,
+	0x3D, 0x17, 0xC5, 0xFF, 0x00, 0xF0, 0x4E, 0x6F, 0x1B, 0xB6, 0xBC, 0x76, 0xCD, 0x73, 0xAC, 0x68,
+	0x7E, 0x24, 0xB8, 0x48, 0x52, 0xD9, 0x71, 0xBB, 0xCB, 0x85, 0xB6, 0xFC, 0xDF, 0xEC, 0xD0, 0x07,
+	0xE3, 0x6F, 0xC7, 0xBF, 0xDA, 0x4F, 0xE3, 0x37, 0xED, 0x2F, 0xE3, 0x9B, 0xEF, 0x88, 0x9F, 0x1A,
+	0xFC, 0x7F, 0xA8, 0x6B, 0x9A, 0x95, 0xE5, 0xC3, 0x4A, 0xC9, 0x77, 0x70, 0xCD, 0x04, 0x2C, 0xDF,
+	0xF3, 0xCA, 0x3D, 0xDB, 0x63, 0xFF, 0x00, 0x80, 0xD7, 0x0B, 0x1C, 0xEE, 0xBB, 0x86, 0xDF, 0x95,
+	0xBE, 0xF2, 0xD7, 0x61, 0xF1, 0x5B, 0xE0, 0x47, 0xC5, 0xEF, 0x82, 0x9A, 0xD5, 0xC6, 0x83, 0xF1,
+	0x57, 0xE1, 0xB6, 0xB5, 0xA1, 0xCD, 0x6F, 0x79, 0x25, 0xB3, 0x4F, 0xA8, 0xE9, 0xF2, 0x45, 0x0C,
+	0x92, 0x2B, 0x73, 0xB2, 0x46, 0x5D, 0xAD, 0xFF, 0x00, 0x01, 0xAE, 0x37, 0xCB, 0x29, 0xDD, 0xB1,
+	0xFD, 0xE5, 0xE9, 0x40, 0x1B, 0xBF, 0x0D, 0xA7, 0x82, 0xDF, 0xE2, 0x26, 0x81, 0x34, 0xEF, 0xE5,
+	0xC6, 0xBA, 0xD5, 0xBB, 0x33, 0x37, 0xF0, 0xAF, 0x98, 0xB5, 0xFD, 0x38, 0xF8, 0x9F, 0xFE, 0x0B,
+	0xEB, 0xFF, 0x00, 0x04, 0xF2, 0xFD, 0x86, 0xBF, 0x63, 0xAF, 0x09, 0x59, 0x3F, 0x8E, 0xED, 0xFE,
+	0x25, 0x78, 0x92, 0xCF, 0x49, 0x8E, 0x09, 0xFC, 0x27, 0xE1, 0xD9, 0x95, 0x6E, 0x6C, 0x6E, 0x36,
+	0xAE, 0xDF, 0x31, 0x9B, 0xF8, 0x6B, 0xF9, 0x8E, 0xF8, 0x6B, 0x14, 0x33, 0x7C, 0x40, 0xF0, 0xFC,
+	0x53, 0x26, 0xE5, 0x6D, 0x72, 0xDD, 0x59, 0x4F, 0xF1, 0x2F, 0x99, 0x1D, 0x7F, 0x4B, 0xFE, 0x3E,
+	0xFF, 0x00, 0x83, 0x7D, 0x7F, 0xE0, 0x9E, 0xDF, 0xB7, 0xD7, 0xEC, 0xE9, 0xE0, 0x3F, 0x1E, 0xDD,
+	0xF8, 0x7D, 0x7E, 0x18, 0xF8, 0x86, 0x1F, 0x0F, 0xAF, 0xDB, 0x35, 0x4F, 0x0A, 0xC2, 0xBB, 0xF5,
+	0x6B, 0x8F, 0x2F, 0xE5, 0x69, 0xB7, 0x50, 0x07, 0xE3, 0xAF, 0xFC, 0x14, 0x0B, 0xFE, 0x0E, 0x0E,
+	0xFD, 0xBC, 0xFF, 0x00, 0x6E, 0xCD, 0x2A, 0xE7, 0xE1, 0xE6, 0xA5, 0xE3, 0x94, 0xF0, 0xDF, 0x82,
+	0xBE, 0xD6, 0xCD, 0xA5, 0xE9, 0xBA, 0x2A, 0x7D, 0x9E, 0xF2, 0x38, 0xFF, 0x00, 0x85, 0x64, 0x9A,
+	0x36, 0xDC, 0xDF, 0x2F, 0xCB, 0x5F, 0x0A, 0xDD, 0x5D, 0xCF, 0x77, 0x3B, 0x4F, 0x34, 0xCD, 0x24,
+	0xCC, 0xCC, 0xED, 0x34, 0x8F, 0xB9, 0xDD, 0xB3, 0x9C, 0x96, 0xF5, 0xAF, 0xB5, 0xBF, 0xE0, 0xA1,
+	0xBF, 0xF0, 0x41, 0xEF, 0xDB, 0x8F, 0xF6, 0x05, 0xB9, 0x8B, 0xC4, 0x3E, 0x24, 0xF8, 0x7B, 0x27,
+	0x88, 0xBC, 0x31, 0xA9, 0x5E, 0xC8, 0x9A, 0x25, 0xEF, 0x87, 0x95, 0xAE, 0x6E, 0x1A, 0x15, 0xFB,
+	0xAD, 0x2C, 0x71, 0xAB, 0x32, 0x7C, 0xB8, 0xAF, 0x8A, 0xB5, 0x0D, 0x3A, 0xF7, 0x4B, 0xBC, 0x92,
+	0xC3, 0x51, 0xB3, 0x96, 0xDE, 0xEA, 0x17, 0xD9, 0x2D, 0xAC, 0xF1, 0x32, 0xC8, 0x8D, 0xFE, 0xD2,
+	0xB5, 0x00, 0x56, 0x57, 0x2D, 0x30, 0x76, 0xFB, 0xDB, 0xAB, 0xF6, 0x47, 0xFE, 0x0C, 0xFC, 0xFF,
+	0x00, 0x93, 0x8D, 0xF1, 0x67, 0xFD, 0x72, 0x8F, 0xFF, 0x00, 0x41, 0xAF, 0xC6, 0xE5, 0x56, 0x59,
+	0x97, 0x7F, 0xDE, 0xDD, 0x5F, 0xB2, 0x1F, 0xF0, 0x67, 0xFC, 0x9E, 0x5F, 0xED, 0x19, 0xE2, 0xC3,
+	0xFF, 0x00, 0x4C, 0xA3, 0xFF, 0x00, 0xD0, 0x68, 0x03, 0xFA, 0x14, 0xF1, 0x16, 0xFF, 0x00, 0xB2,
+	0xCD, 0xFE, 0xF3, 0x7F, 0xE8, 0x55, 0x99, 0xFB, 0x3C, 0x7F, 0xC8, 0xF9, 0xAB, 0x7F, 0xD7, 0x0F,
+	0xFD, 0x9A, 0xB4, 0x7C, 0x41, 0x31, 0x6B, 0x59, 0xBF, 0xDE, 0x6A, 0xCD, 0xFD, 0x9D, 0x5C, 0xB7,
+	0x8F, 0x35, 0x6F, 0xFA, 0xF7, 0xFF, 0x00, 0xD9, 0xA8, 0x03, 0xD9, 0xD3, 0xEE, 0xD2, 0xD3, 0x57,
+	0xE6, 0x50, 0x69, 0xD4, 0x00, 0x51, 0x45, 0x14, 0x01, 0xE7, 0xDF, 0xB4, 0x6F, 0xFC, 0x88, 0x0B,
+	0xFF, 0x00, 0x5F, 0x91, 0xD6, 0x07, 0x81, 0xFE, 0x59, 0x2D, 0xAE, 0x5B, 0xE5, 0x55, 0xB8, 0x8D,
+	0xBF, 0xE0, 0x3B, 0xAB, 0xA0, 0xFD, 0xA3, 0xFF, 0x00, 0xE4, 0x42, 0x1F, 0xF5, 0xF9, 0x1D, 0x73,
+	0x3E, 0x0D, 0x99, 0x1A, 0xC5, 0xD1, 0xDD, 0xB7, 0x32, 0xAD, 0x4C, 0xA4, 0xD4, 0x6C, 0xBA, 0x84,
+	0x74, 0xA8, 0xA4, 0xF6, 0x49, 0x9F, 0x84, 0xFF, 0x00, 0xF0, 0x53, 0xDF, 0x1B, 0x7C, 0x41, 0xFD,
+	0x87, 0xBF, 0xE0, 0xE3, 0x8D, 0x27, 0xF6, 0xD3, 0xF8, 0x8B, 0xE1, 0xED, 0x6B, 0x41, 0xF8, 0x7F,
+	0xA9, 0x5E, 0x5A, 0xC5, 0x0E, 0xB5, 0x0E, 0xE4, 0xB6, 0xD6, 0x60, 0xF2, 0x5A, 0x39, 0x21, 0x66,
+	0xFE, 0x25, 0xE7, 0xE6, 0x5F, 0xF6, 0x56, 0xBE, 0xAA, 0xF8, 0xB5, 0xFB, 0x14, 0x9F, 0xD9, 0xD3,
+	0xC6, 0xF3, 0x7E, 0xD2, 0x1F, 0x02, 0x34, 0xF9, 0xA5, 0xF8, 0x5F, 0xE3, 0xF6, 0xFE, 0xDF, 0xFF,
+	0x00, 0x84, 0x7D, 0xBE, 0x6B, 0x8B, 0x3B, 0x89, 0xBE, 0x66, 0xB8, 0x6F, 0xFA, 0x67, 0xF3, 0x57,
+	0xB9, 0x7F, 0xC1, 0x72, 0xFF, 0x00, 0xE0, 0x94, 0x9A, 0x87, 0xFC, 0x15, 0x7F, 0xF6, 0x6F, 0xD3,
+	0x7C, 0x33, 0xE0, 0x9F, 0x1C, 0x49, 0xA7, 0xF8, 0xEF, 0xC0, 0x10, 0xDC, 0x5D, 0xF8, 0x27, 0x4B,
+	0x90, 0x85, 0xB5, 0xD5, 0x24, 0x68, 0xD5, 0x5E, 0x39, 0x59, 0x97, 0xE5, 0xDC, 0xAB, 0xB5, 0x5A,
+	0xBE, 0x63, 0xFF, 0x00, 0x82, 0x3E, 0xFF, 0x00, 0xC1, 0x5B, 0xAF, 0xFC, 0x7D, 0xA1, 0x6A, 0xBF,
+	0xF0, 0x4F, 0x5F, 0xDB, 0xEB, 0x43, 0xFE, 0xC2, 0xF8, 0x91, 0xF0, 0xFE, 0xCD, 0xB4, 0xDB, 0x3B,
+	0x1D, 0x52, 0x1F, 0x2E, 0x4D, 0x4E, 0x38, 0x7E, 0x5F, 0xB3, 0x85, 0x6F, 0xBD, 0xFC, 0x3F, 0xF7,
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+	0xA8, 0x0B, 0x7B, 0xC9, 0xB6, 0xBE, 0x9B, 0x0A, 0xED, 0xD3, 0x63, 0x8F, 0xE5, 0xDA, 0xBF, 0xED,
+	0x2F, 0xF1, 0x54, 0x9E, 0x32, 0xF8, 0x9D, 0xF0, 0x1F, 0xC6, 0x5F, 0x1D, 0x1F, 0xC1, 0xFF, 0x00,
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+	0x9A, 0x3B, 0x88, 0xEF, 0x19, 0xB7, 0xE9, 0x3A, 0x4A, 0xFC, 0xBF, 0x67, 0x5F, 0xFA, 0x68, 0xB5,
+	0xFD, 0x6F, 0x86, 0xE3, 0x3E, 0x1B, 0xAD, 0x96, 0xAC, 0xCB, 0x0B, 0x57, 0xDA, 0x45, 0xE8, 0x91,
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+	0x4A, 0xF0, 0x6D, 0x9C, 0xBB, 0xED, 0xE1, 0x6F, 0x95, 0xB5, 0x66, 0xFE, 0xED, 0x7D, 0xF5, 0x62,
+	0xD6, 0x7A, 0x45, 0x85, 0xAE, 0x95, 0x0C, 0x36, 0xF6, 0xD6, 0xD6, 0xB6, 0xEB, 0x6F, 0x65, 0x1C,
+	0x71, 0x2A, 0xB2, 0xC6, 0xBF, 0x75, 0x59, 0xAB, 0x9C, 0xD3, 0xEE, 0xA1, 0xB3, 0x86, 0x1D, 0x2A,
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+	0xAB, 0x42, 0x59, 0x96, 0x64, 0x69, 0x1F, 0xF8, 0x76, 0xFF, 0x00, 0x0D, 0x7E, 0x75, 0x9A, 0x66,
+	0xD8, 0x8C, 0xD3, 0x19, 0x2A, 0xD5, 0x5F, 0x92, 0xF2, 0x47, 0xE8, 0x59, 0x76, 0x57, 0x4F, 0x2D,
+	0xC3, 0xAA, 0x50, 0xFB, 0xFB, 0x9B, 0x8D, 0x7C, 0xF1, 0xB7, 0x92, 0x1F, 0x6E, 0xEF, 0x9B, 0x75,
+	0x3E, 0x3D, 0x4B, 0xCB, 0xF9, 0x11, 0xEB, 0x9A, 0xBA, 0xD5, 0x5F, 0x6A, 0xA4, 0x8F, 0xB9, 0x7F,
+	0xBC, 0xB4, 0xB6, 0xFA, 0xA6, 0xD5, 0xF9, 0xDF, 0xE6, 0xAF, 0x28, 0xF5, 0xE3, 0xEE, 0xC4, 0xD9,
+	0xD7, 0xB5, 0x6D, 0xBA, 0x79, 0xF9, 0xFE, 0xF2, 0xD3, 0x7F, 0x66, 0x39, 0xBE, 0xD1, 0xE3, 0x5D,
+	0x51, 0xFF, 0x00, 0xE9, 0x85, 0x73, 0x9E, 0x22, 0xD5, 0x8A, 0x58, 0xB1, 0xDF, 0xFC, 0x35, 0xB7,
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+	0xD3, 0xA9, 0xA0, 0x64, 0x0A, 0x75, 0x00, 0x14, 0x51, 0x45, 0x00, 0x79, 0xBF, 0xED, 0x3B, 0x3F,
+	0x93, 0xF0, 0xDF, 0x7F, 0xFD, 0x3F, 0x47, 0x5C, 0x4F, 0x83, 0xB5, 0x6D, 0xB6, 0xBB, 0x3C, 0xCF,
+	0xE1, 0x5A, 0xEB, 0x3F, 0x6B, 0x7B, 0x8F, 0xB3, 0xFC, 0x2E, 0xDF, 0xFF, 0x00, 0x4F, 0xD1, 0xD7,
+	0x97, 0xF8, 0x3F, 0x56, 0xFF, 0x00, 0x45, 0xFB, 0xFF, 0x00, 0xC3, 0x40, 0x1D, 0xF7, 0xF6, 0xB3,
+	0xFF, 0x00, 0xCF, 0x4A, 0xA1, 0xE2, 0x5D, 0x2B, 0xC2, 0x7E, 0x3D, 0xF0, 0xB6, 0xA9, 0xE0, 0x0F,
+	0x88, 0x9E, 0x1E, 0xB7, 0xD6, 0x7C, 0x3B, 0xAE, 0x5A, 0xB5, 0xAE, 0xB9, 0xA5, 0xDE, 0x45, 0xE6,
+	0x7D, 0xA2, 0x16, 0x5D, 0xBB, 0x57, 0xFB, 0xBF, 0x7A, 0xB2, 0xFF, 0x00, 0xB5, 0x57, 0xFB, 0xF4,
+	0x9F, 0xDA, 0x88, 0x7E, 0xFE, 0xE6, 0x5F, 0xF6, 0x68, 0x03, 0xC5, 0xBF, 0xE0, 0x9E, 0x1F, 0xF0,
+	0x4F, 0x9F, 0x04, 0xFF, 0x00, 0xC1, 0x39, 0xFC, 0x3B, 0xE3, 0xAF, 0x01, 0xF8, 0x03, 0xC6, 0x12,
+	0x6A, 0x1A, 0x1F, 0x8B, 0x3C, 0x46, 0xDA, 0xA7, 0x87, 0x34, 0xD8, 0xD9, 0x97, 0xFB, 0x0E, 0xDF,
+	0x76, 0xEF, 0xB2, 0xB7, 0xF7, 0xAB, 0xE9, 0x0B, 0x5D, 0x7A, 0xE6, 0x1B, 0x88, 0x64, 0x77, 0xB8,
+	0xFF, 0x00, 0x5A, 0xBB, 0x99, 0x59, 0x9B, 0x77, 0xCD, 0x5C, 0xD2, 0xEA, 0xC9, 0x0A, 0xB6, 0xCD,
+	0xBE, 0x5A, 0xFC, 0xCC, 0xDF, 0xC4, 0xCB, 0xFD, 0xDA, 0xFC, 0xD6, 0xFF, 0x00, 0x82, 0xD9, 0xFF,
+	0x00, 0xC1, 0x49, 0xFF, 0x00, 0xE0, 0xA9, 0x9F, 0xF0, 0x4F, 0xAF, 0x19, 0x78, 0x73, 0xC4, 0xBF,
+	0xB3, 0x0E, 0x99, 0xA5, 0xCD, 0xF0, 0xFF, 0x00, 0x54, 0xB5, 0xF3, 0x6F, 0x35, 0x6B, 0xCD, 0x2F,
+	0xCF, 0x8E, 0xD2, 0x6D, 0xCB, 0xB6, 0x39, 0x5B, 0x72, 0xED, 0xFF, 0x00, 0xEC, 0x68, 0x03, 0xE0,
+	0x2F, 0xF8, 0x2E, 0x8E, 0xAF, 0x36, 0xA5, 0xFF, 0x00, 0x05, 0x6C, 0xF8, 0x8A, 0xE8, 0x92, 0x47,
+	0x1A, 0xE9, 0x70, 0xF9, 0xAB, 0x23, 0x36, 0xE6, 0xF9, 0x6B, 0xEE, 0x8F, 0xF8, 0x35, 0xC7, 0x52,
+	0x73, 0xE0, 0x1F, 0x11, 0x24, 0x33, 0x4C, 0x9F, 0x33, 0x6D, 0xF2, 0xF7, 0x7F, 0xEC, 0xB5, 0xF8,
+	0xF9, 0xF1, 0xEF, 0xF6, 0x96, 0xF8, 0xCB, 0xFB, 0x5A, 0xFC, 0x74, 0xD5, 0xFF, 0x00, 0x68, 0xCF,
+	0x8F, 0xF7, 0x36, 0x92, 0xF8, 0xC3, 0x5C, 0x81, 0x52, 0xF2, 0x6B, 0x08, 0xF6, 0xDB, 0xB4, 0x7F,
+	0xC3, 0xB5, 0x6B, 0xD0, 0xFF, 0x00, 0x64, 0xFF, 0x00, 0xF8, 0x2A, 0xFF, 0x00, 0xED, 0xBF, 0xFF,
+	0x00, 0x04, 0xDF, 0xD1, 0x6F, 0xA5, 0xFD, 0x97, 0xB5, 0x0D, 0x05, 0x74, 0x6B, 0xAF, 0xF8, 0xFE,
+	0x87, 0x52, 0xB2, 0x59, 0x65, 0xDD, 0xBB, 0xFD, 0xEA, 0x00, 0xFE, 0xA8, 0x2C, 0x75, 0x99, 0xAC,
+	0xEF, 0xAD, 0x6F, 0x1E, 0xE6, 0xE2, 0x34, 0xB7, 0x95, 0x5E, 0x5D, 0xCC, 0xCB, 0xE6, 0x2A, 0xFF,
+	0x00, 0x0D, 0x7C, 0x0F, 0x1F, 0xFC, 0x10, 0x57, 0xF6, 0x7B, 0xF1, 0xA7, 0xED, 0xC5, 0xE3, 0xFF,
+	0x00, 0xDA, 0xF7, 0xF6, 0x87, 0xF1, 0x87, 0xFC, 0x26, 0xDA, 0x57, 0x8E, 0x35, 0x78, 0xF5, 0x2D,
+	0x37, 0xC2, 0xAC, 0xDB, 0x7F, 0xB3, 0x66, 0x8D, 0xB7, 0x2E, 0xE6, 0xFE, 0x2A, 0xF5, 0x2F, 0xF8,
+	0x26, 0x8F, 0xC4, 0xCF, 0xDB, 0xBF, 0xE2, 0x67, 0xEC, 0xD1, 0xA3, 0xFC, 0x62, 0xFD, 0xBC, 0xBC,
+	0x4F, 0xE1, 0xBD, 0x63, 0x53, 0xF1, 0x95, 0xB2, 0xEA, 0x3E, 0x15, 0xFF, 0x00, 0x84, 0x6E, 0x1D,
+	0xB1, 0xDA, 0xD8, 0xB7, 0xFC, 0xB3, 0x97, 0xFD, 0xAA, 0xFA, 0x09, 0x75, 0x04, 0x8F, 0xE5, 0xDE,
+	0xBF, 0xBC, 0xFB, 0xAC, 0xB4, 0x01, 0xBB, 0x6B, 0x35, 0xB5, 0xAC, 0x36, 0xF6, 0x96, 0xD0, 0xC7,
+	0x6F, 0x6F, 0x67, 0x6E, 0xB6, 0xF6, 0xB6, 0xB6, 0xEB, 0xE5, 0xC5, 0x1C, 0x2B, 0xF7, 0x57, 0x6A,
+	0xFC, 0xB5, 0x64, 0x6A, 0xDB, 0x6B, 0x9B, 0xFE, 0xD4, 0x1F, 0xDF, 0xA3, 0xFB, 0x59, 0x53, 0xEF,
+	0x50, 0x06, 0x6F, 0xC4, 0xED, 0x5B, 0x75, 0xAB, 0x57, 0xB9, 0x7C, 0x21, 0xFF, 0x00, 0x92, 0x71,
+	0xA3, 0xFF, 0x00, 0xD7, 0xBF, 0xF5, 0x35, 0xF3, 0x6F, 0xC4, 0x0D, 0x59, 0x24, 0x55, 0x4F, 0xEF,
+	0x35, 0x7D, 0x25, 0xF0, 0x9F, 0x8F, 0x87, 0x7A, 0x4F, 0xFD, 0x7A, 0xD0, 0x07, 0x4A, 0xA3, 0x68,
+	0xC5, 0x2D, 0x14, 0x50, 0x01, 0x49, 0xFC, 0x1F, 0x85, 0x0C, 0xDB, 0x7B, 0x52, 0x33, 0x7C, 0xCB,
+	0x40, 0x1F, 0x3D, 0xFC, 0x53, 0xD4, 0x3E, 0xCF, 0xF1, 0x93, 0x50, 0x41, 0x26, 0x0F, 0x92, 0xBF,
+	0x2D, 0x7C, 0x0D, 0xFF, 0x00, 0x07, 0x2E, 0x7E, 0xC9, 0x5F, 0xB4, 0xB7, 0xED, 0xB3, 0xFB, 0x18,
+	0x7C, 0x34, 0xF8, 0x6B, 0xFB, 0x2E, 0xFC, 0x2B, 0xBA, 0xF1, 0x76, 0xAD, 0xA2, 0xF8, 0xAA, 0x4B,
+	0xCD, 0x5E, 0xC6, 0xC5, 0x97, 0xCE, 0x86, 0x16, 0x8D, 0x95, 0x59, 0x77, 0x32, 0xAF, 0xDE, 0x65,
+	0xAF, 0xB8, 0x7E, 0x35, 0xEA, 0x1E, 0x5F, 0xC7, 0x1D, 0x4A, 0x12, 0x76, 0xFF, 0x00, 0xA3, 0xC7,
+	0x5A, 0xDA, 0x7F, 0x88, 0x2F, 0x2C, 0xE1, 0x44, 0xB0, 0xD4, 0xA6, 0xB7, 0x65, 0x5F, 0xBD, 0x0B,
+	0x6D, 0x66, 0xA0, 0x0F, 0xE5, 0x82, 0x7F, 0xF8, 0x20, 0x37, 0xFC, 0x15, 0xC5, 0xA4, 0x32, 0xBF,
+	0xEC, 0x61, 0xAC, 0xB1, 0x66, 0xFB, 0xCB, 0x24, 0x7F, 0xFC, 0x72, 0x8F, 0xF8, 0x70, 0x2F, 0xFC,
+	0x15, 0xCF, 0xCD, 0x30, 0xA7, 0xEC, 0x69, 0xAD, 0x33, 0x49, 0xFB, 0xBF, 0x95, 0xA3, 0xFB, 0xCD,
+	0xFF, 0x00, 0x02, 0xAF, 0xEA, 0xA5, 0x7C, 0x6D, 0xE2, 0x1D, 0xCC, 0xFF, 0x00, 0xF0, 0x92, 0x6A,
+	0x19, 0xDB, 0xFF, 0x00, 0x3F, 0x14, 0x47, 0xE3, 0x2F, 0x10, 0xC7, 0x1A, 0xBA, 0x78, 0x9E, 0xFB,
+	0x67, 0xDE, 0xDD, 0xF6, 0x8F, 0xE2, 0xA0, 0x0F, 0xE7, 0x97, 0xC5, 0xBF, 0xB7, 0x07, 0xC6, 0xDF,
+	0xD8, 0x37, 0xF6, 0x1C, 0xF0, 0x3F, 0xFC, 0x12, 0x1B, 0x5D, 0xB7, 0x9B, 0xE0, 0xBF, 0x8E, 0x2F,
+	0x35, 0xF9, 0x9B, 0xE2, 0x7F, 0x89, 0x9A, 0xDF, 0x6C, 0xF6, 0xDA, 0x7C, 0x92, 0x36, 0xDD, 0xCE,
+	0x9F, 0x79, 0xB6, 0x9A, 0xF5, 0x0F, 0x15, 0xFF, 0x00, 0xC1, 0x4F, 0x7F, 0x60, 0x9F, 0xF8, 0x25,
+	0x47, 0xEC, 0x69, 0x07, 0xC0, 0x1F, 0xF8, 0x25, 0x97, 0xC5, 0x08, 0x7C, 0x5D, 0xF1, 0x03, 0xC7,
+	0x6B, 0xE4, 0xF8, 0xD3, 0xE2, 0x34, 0xD0, 0xFE, 0xFF, 0x00, 0x4F, 0x91, 0xBE, 0xFD, 0xD6, 0xEF,
+	0xBD, 0xFC, 0x4D, 0x5D, 0x77, 0xFC, 0x1D, 0xCB, 0xF0, 0x36, 0x7F, 0x10, 0x78, 0x23, 0xE1, 0x8F,
+	0xC7, 0x8F, 0x05, 0xFC, 0x38, 0xB9, 0xD4, 0x2F, 0x15, 0xAE, 0x17, 0xC6, 0x1E, 0x24, 0xB6, 0xB4,
+	0x69, 0x1A, 0x15, 0xDB, 0xB6, 0x35, 0x9E, 0x45, 0xFE, 0x1F, 0xF7, 0xAB, 0xF0, 0x96, 0x66, 0x85,
+	0xA5, 0x26, 0x15, 0x54, 0x5D, 0xDF, 0x79, 0x77, 0x50, 0x07, 0xED, 0x37, 0xEC, 0xED, 0xFB, 0x7F,
+	0xFF, 0x00, 0xC1, 0x38, 0xFF, 0x00, 0xE0, 0x8F, 0xDF, 0xB2, 0x9E, 0xBD, 0xFB, 0x44, 0xFE, 0xCF,
+	0x9F, 0x19, 0x6D, 0x7E, 0x3A, 0xFE, 0xD4, 0x5F, 0x10, 0x23, 0x68, 0xEF, 0xF5, 0x4D, 0x5A, 0xDF,
+	0x3F, 0xD9, 0x13, 0x49, 0xB9, 0x9A, 0x6D, 0xCC, 0xBB, 0xB6, 0xAE, 0xEF, 0xE1, 0x6F, 0x9B, 0xEE,
+	0xFD, 0xDF, 0xBD, 0xCE, 0xFE, 0xC4, 0xFF, 0x00, 0xB7, 0x97, 0xEC, 0x2D, 0xFB, 0x15, 0xFC, 0x10,
+	0xF1, 0x37, 0xFC, 0x15, 0x67, 0xE3, 0x9F, 0xC7, 0x0B, 0x7F, 0x8E, 0x9F, 0xB6, 0x27, 0x8D, 0x64,
+	0x91, 0xB4, 0x2F, 0x0C, 0xEA, 0x44, 0xBF, 0xFC, 0x23, 0x12, 0x4B, 0xFF, 0x00, 0x2D, 0x1B, 0xCC,
+	0xFB, 0xBB, 0x77, 0x1D, 0xCC, 0xBF, 0x75, 0x57, 0x6A, 0xAA, 0xFD, 0xEA, 0xFC, 0x7A, 0x32, 0x04,
+	0xF9, 0xE3, 0x45, 0x56, 0x56, 0xFB, 0xCA, 0xCD, 0xBA, 0x90, 0x3A, 0xAF, 0x0B, 0x16, 0xDD, 0xBF,
+	0xC5, 0xF3, 0x66, 0x80, 0x3D, 0x0B, 0xF6, 0x9D, 0xFD, 0xA5, 0x7E, 0x32, 0xFE, 0xD7, 0x9F, 0x1A,
+	0x35, 0xAF, 0x8F, 0xDF, 0x1E, 0xFC, 0x63, 0x26, 0xB9, 0xE2, 0x8F, 0x10, 0xCF, 0xE7, 0x5E, 0x5E,
+	0xBE, 0xD5, 0x55, 0x5F, 0xE1, 0x85, 0x57, 0xF8, 0x55, 0x3E, 0xEA, 0xAD, 0x79, 0xB9, 0x04, 0x1C,
+	0x54, 0x8C, 0x37, 0x7C, 0xE9, 0xB8, 0x0A, 0x8E, 0x80, 0x24, 0x83, 0xFD, 0x7C, 0x7F, 0xEF, 0xAD,
+	0x7E, 0xF8, 0x7F, 0xC1, 0x9A, 0x97, 0x4F, 0x6D, 0xF0, 0x67, 0xF6, 0x80, 0xC3, 0xFF, 0x00, 0xCB,
+	0xC5, 0x9F, 0xCB, 0xFF, 0x00, 0x6C, 0xEB, 0xF0, 0x46, 0x24, 0x95, 0xB7, 0x4C, 0x8A, 0xD9, 0x8D,
+	0x77, 0xFC, 0xBF, 0xC3, 0xF3, 0x57, 0xF4, 0xE9, 0xFF, 0x00, 0x06, 0xEF, 0xFE, 0xCB, 0x1F, 0x08,
+	0x7F, 0x66, 0xEF, 0xF8, 0x26, 0xD7, 0x86, 0xFE, 0x3B, 0x7C, 0x34, 0xD4, 0x6F, 0xAE, 0x35, 0xAF,
+	0x8B, 0xD6, 0x0B, 0x2F, 0x8D, 0x3E, 0xD8, 0xDB, 0x91, 0x64, 0x8F, 0xEE, 0xAC, 0x4B, 0xFC, 0x2A,
+	0xB4, 0x01, 0xF7, 0x8F, 0xC3, 0x3B, 0x85, 0x93, 0xE3, 0x56, 0x9A, 0x97, 0x33, 0xEC, 0x7D, 0xDF,
+	0x2F, 0xFD, 0x34, 0xAF, 0xA3, 0xD1, 0x95, 0xB3, 0xB3, 0xFB, 0xD5, 0xF3, 0x0F, 0xC1, 0x6B, 0x88,
+	0x6F, 0x3E, 0x32, 0x59, 0x23, 0x8D, 0xCD, 0x0C, 0xBF, 0x2B, 0x7F, 0x76, 0xBE, 0x9E, 0x5E, 0xA6,
+	0x80, 0x1D, 0x45, 0x14, 0x50, 0x01, 0x58, 0x3F, 0x13, 0x1F, 0x67, 0x80, 0x75, 0x77, 0x4F, 0xF9,
+	0xF3, 0x6A, 0xDE, 0xAE, 0x7B, 0xE2, 0xA3, 0x6C, 0xF8, 0x77, 0xAC, 0xBF, 0xFD, 0x38, 0xB5, 0x00,
+	0x78, 0x67, 0xC3, 0x5D, 0x53, 0xFD, 0x0E, 0xDF, 0xF8, 0xBE, 0x5A, 0x67, 0xED, 0x05, 0xF0, 0x57,
+	0xE0, 0xFF, 0x00, 0xED, 0x49, 0xF0, 0x87, 0x58, 0xF8, 0x03, 0xF1, 0xEF, 0xC2, 0x50, 0xEB, 0x7E,
+	0x15, 0xD7, 0x22, 0x65, 0xB8, 0xB7, 0x99, 0x77, 0x49, 0x6F, 0x37, 0xF0, 0xCD, 0x1B, 0x7F, 0x0E,
+	0xDF, 0xBD, 0x58, 0x1F, 0x0D, 0xF5, 0x4D, 0xD6, 0xB1, 0xFC, 0xFF, 0x00, 0x32, 0xAD, 0x76, 0x11,
+	0xEA, 0x9E, 0x62, 0xB4, 0x8E, 0xEB, 0xB7, 0xFD, 0xAA, 0x00, 0xFE, 0x65, 0xBF, 0xE0, 0xA7, 0x7F,
+	0xF0, 0x4C, 0xBF, 0x8A, 0xDF, 0xF0, 0x4C, 0x8F, 0x8D, 0x4B, 0xE0, 0xBF, 0x16, 0x49, 0x36, 0xB9,
+	0xE0, 0x7D, 0x7E, 0xE2, 0x43, 0xE0, 0x4F, 0x19, 0x47, 0x1E, 0xE8, 0xEE, 0xD7, 0xFE, 0x7D, 0xDB,
+	0xFB, 0xBE, 0x5F, 0xDD, 0xAF, 0xD7, 0xBF, 0xF8, 0x35, 0xE6, 0xF2, 0x5B, 0x1F, 0xF8, 0x24, 0xFB,
+	0xA4, 0xCF, 0xF7, 0x7C, 0x6F, 0x32, 0xFC, 0xBF, 0xC2, 0xDB, 0xAB, 0xEB, 0x6F, 0xDA, 0x23, 0xE0,
+	0x3F, 0xC1, 0x5F, 0xDA, 0xDB, 0xE0, 0xBE, 0xB5, 0xF0, 0x07, 0xF6, 0x87, 0xF0, 0xDC, 0x7A, 0x97,
+	0x87, 0xB5, 0x6B, 0x59, 0x22, 0x59, 0x36, 0xEE, 0xB9, 0xD3, 0x64, 0xDB, 0xFB, 0xB9, 0x2D, 0x9B,
+	0xFE, 0x59, 0xFC, 0xD5, 0xE4, 0x7F, 0xF0, 0x49, 0xBF, 0xD8, 0xB3, 0xC7, 0xBF, 0xF0, 0x4E, 0x2F,
+	0xD9, 0x3B, 0x52, 0xFD, 0x99, 0x3C, 0x6F, 0xE2, 0xDB, 0x3D, 0x62, 0x56, 0xF1, 0x84, 0xDA, 0x8E,
+	0x83, 0x79, 0x6F, 0xF7, 0x57, 0x4D, 0x66, 0xFD, 0xDC, 0x72, 0x7F, 0xD3, 0x4D, 0xB4, 0x01, 0xF5,
+	0x94, 0xD7, 0xCF, 0x24, 0x7B, 0x37, 0xEE, 0x69, 0x3F, 0xBA, 0xDF, 0xC3, 0x5E, 0x39, 0xFB, 0x57,
+	0xFE, 0xC1, 0x9F, 0xB1, 0x77, 0xED, 0xD1, 0xAC, 0x68, 0x7A, 0xC7, 0xED, 0x61, 0xF0, 0x72, 0x1F,
+	0x13, 0x5C, 0x78, 0x5E, 0x1F, 0x2B, 0x47, 0xBA, 0x85, 0xFC, 0xA9, 0x21, 0x5F, 0xEE, 0xC8, 0xDF,
+	0xF2, 0xD2, 0xBD, 0x15, 0xB5, 0xA8, 0x77, 0x6C, 0x4D, 0xDB, 0xBF, 0x8E, 0x9B, 0xFD, 0xAC, 0x8C,
+	0x8C, 0xEF, 0xFE, 0xAD, 0x7F, 0x87, 0xF8, 0x9A, 0x80, 0x3C, 0xFF, 0x00, 0xF6, 0x55, 0xFD, 0x84,
+	0xFF, 0x00, 0x63, 0x4F, 0xD8, 0x6E, 0xFF, 0x00, 0x58, 0xD6, 0x3F, 0x64, 0xEF, 0x83, 0x30, 0xF8,
+	0x66, 0xE7, 0xC4, 0x91, 0x79, 0x5A, 0xDD, 0xD4, 0x9F, 0xBC, 0x92, 0x65, 0x5F, 0xF9, 0xE6, 0xDF,
+	0xC3, 0x5E, 0xC2, 0xB7, 0x8E, 0xD2, 0x18, 0x77, 0xED, 0x68, 0xD7, 0xF8, 0xAB, 0x9D, 0x9B, 0x57,
+	0x73, 0xB7, 0xC9, 0xFF, 0x00, 0x57, 0xFD, 0xDF, 0xEE, 0xD3, 0x2C, 0xF5, 0x4F, 0x99, 0xBC, 0xED,
+	0xDB, 0xBF, 0x85, 0xA8, 0x03, 0xE1, 0x6F, 0xF8, 0x3A, 0x1A, 0xE8, 0xDE, 0x7F, 0xC1, 0x27, 0xD2,
+	0x17, 0x9B, 0x7B, 0xB7, 0x8D, 0xE1, 0x55, 0xFF, 0x00, 0xBE, 0xAB, 0xF2, 0x2F, 0xFE, 0x09, 0x89,
+	0xFF, 0x00, 0x04, 0xBF, 0xF8, 0x9D, 0xFF, 0x00, 0x05, 0x3D, 0xF8, 0xBD, 0x37, 0x85, 0x7C, 0x3D,
+	0x34, 0xDE, 0x1F, 0xF0, 0x3F, 0x87, 0xE5, 0x8F, 0xFE, 0x13, 0x4F, 0x15, 0x49, 0x16, 0xD8, 0xE1,
+	0x5F, 0xE2, 0xB7, 0x5F, 0xEF, 0x6E, 0xFB, 0xB5, 0xFB, 0x9D, 0xFF, 0x00, 0x05, 0x62, 0xFD, 0x8A,
+	0xFC, 0x79, 0xFF, 0x00, 0x05, 0x18, 0xFD, 0x93, 0x74, 0xCF, 0xD9, 0xAB, 0xC0, 0x7E, 0x2A, 0xB3,
+	0xD2, 0x59, 0x7C, 0x61, 0x0E, 0xA3, 0xE2, 0x0B, 0xAB, 0xAF, 0xF9, 0x69, 0xA7, 0xAB, 0x7E, 0xF1,
+	0x63, 0xFF, 0x00, 0xA6, 0x9B, 0x6B, 0xD5, 0xFF, 0x00, 0x67, 0x9F, 0x81, 0x1F, 0x07, 0x3F, 0x64,
+	0xFF, 0x00, 0x84, 0xFA, 0x3F, 0xC0, 0x9F, 0xD9, 0xEF, 0xC3, 0x6B, 0xA5, 0xF8, 0x77, 0x47, 0xB3,
+	0x58, 0x9A, 0x66, 0x5D, 0xB3, 0xEA, 0x12, 0x6D, 0xF9, 0x9A, 0x76, 0xFF, 0x00, 0x96, 0x9F, 0x35,
+	0x00, 0x75, 0x7F, 0xB3, 0xDF, 0xC0, 0xEF, 0x83, 0x9F, 0xB2, 0x8F, 0xC1, 0x7D, 0x13, 0xF6, 0x7B,
+	0xFD, 0x9E, 0xFC, 0x25, 0x1E, 0x87, 0xE1, 0x3D, 0x05, 0x7F, 0xD1, 0xED, 0xE3, 0x5F, 0xDE, 0x5C,
+	0x4D, 0xFF, 0x00, 0x2D, 0x26, 0x91, 0xBF, 0x8B, 0x77, 0xDE, 0xAD, 0x9F, 0x1D, 0x6A, 0x8E, 0xD6,
+	0x32, 0x7C, 0xFF, 0x00, 0xC3, 0x55, 0x6D, 0xF5, 0x47, 0x58, 0xF6, 0x3B, 0xFD, 0xDA, 0xC1, 0xF1,
+	0xB6, 0xAD, 0xBB, 0x4F, 0x7F, 0x9E, 0x80, 0x3D, 0x63, 0xF6, 0x58, 0x91, 0xE4, 0xF0, 0x35, 0xD3,
+	0xBF, 0xFC, 0xFE, 0x35, 0x7A, 0x85, 0x79, 0x77, 0xEC, 0xA7, 0xFF, 0x00, 0x24, 0xF2, 0x49, 0x3F,
+	0xBD, 0x75, 0x5E, 0xA3, 0x40, 0x05, 0x14, 0x51, 0x40, 0x08, 0xFF, 0x00, 0x76, 0xBC, 0x6B, 0xF6,
+	0x98, 0xBA, 0xFB, 0x2F, 0x8A, 0xFC, 0x3D, 0xFE, 0xEB, 0x57, 0xB2, 0xBF, 0xDD, 0xAF, 0x08, 0xFD,
+	0xAD, 0xEE, 0x8C, 0x1E, 0x29, 0xF0, 0xEF, 0xFB, 0x92, 0x7F, 0xE8, 0x54, 0x01, 0x37, 0x87, 0xF5,
+	0xA7, 0x8E, 0xCD, 0x5D, 0x3C, 0xB6, 0xFE, 0x1D, 0xB2, 0x2E, 0xE5, 0x65, 0xFF, 0x00, 0x76, 0xBF,
+	0x26, 0xFF, 0x00, 0xE0, 0xBD, 0x9F, 0xF0, 0x4C, 0x2D, 0x7A, 0xE3, 0x5E, 0x93, 0xF6, 0xEA, 0xFD,
+	0x9F, 0xAC, 0x3E, 0xDF, 0x62, 0xD6, 0xFE, 0x57, 0x89, 0xBC, 0x1F, 0x67, 0x17, 0xFC, 0x78, 0xAF,
+	0xF1, 0x5E, 0x7C, 0xB5, 0xFA, 0x85, 0xE1, 0xFD, 0x61, 0x1B, 0x4D, 0x5D, 0xEE, 0xAB, 0xFE, 0xD5,
+	0x5B, 0x9A, 0xFA, 0xCF, 0x50, 0xB5, 0x93, 0x49, 0xBF, 0xB0, 0x86, 0xE6, 0xDA, 0x4F, 0x96, 0xE2,
+	0xD6, 0xE1, 0x77, 0x47, 0x70, 0xBF, 0xDD, 0x6F, 0xEF, 0x2D, 0x00, 0x7E, 0x3B, 0x7F, 0xC1, 0x04,
+	0xFF, 0x00, 0xE0, 0x9D, 0xFE, 0x06, 0xF8, 0xF9, 0xE3, 0x4F, 0xF8, 0x6B, 0x4F, 0x8C, 0xDE, 0x1E,
+	0x93, 0x58, 0xF0, 0xC7, 0x87, 0xEE, 0x36, 0xE9, 0x7A, 0x5D, 0xE5, 0xBF, 0x95, 0xB6, 0xF1, 0x7E,
+	0xEC, 0x9B, 0x5B, 0xEF, 0x57, 0xED, 0x74, 0x9A, 0xB5, 0xCD, 0xC4, 0x9E, 0x74, 0xC9, 0x1A, 0xB6,
+	0xD5, 0x4D, 0xB0, 0xAE, 0xD4, 0x55, 0x5F, 0xBB, 0xB5, 0x6B, 0x8F, 0xD1, 0x6C, 0xFC, 0x2B, 0xE1,
+	0x7B, 0x56, 0xB3, 0xF0, 0x97, 0x84, 0xB4, 0xFD, 0x12, 0xCD, 0x9B, 0xE6, 0xD3, 0xF4, 0x9B, 0x75,
+	0x8A, 0x26, 0x6F, 0xEF, 0x6D, 0x5A, 0xBD, 0xFD, 0xAF, 0xFF, 0x00, 0x4D, 0x28, 0x03, 0x7D, 0xAF,
+	0x9C, 0xB7, 0xDE, 0xA6, 0x7F, 0x68, 0xBD, 0x61, 0x7F, 0x6A, 0xAF, 0xF7, 0xE9, 0x24, 0xD6, 0x11,
+	0x57, 0x7E, 0xFA, 0x00, 0xE8, 0x3E, 0xDD, 0xFE, 0xDD, 0x0B, 0x7D, 0xE6, 0x48, 0xBE, 0x4C, 0xDF,
+	0x32, 0xFF, 0x00, 0x0D, 0x72, 0xEB, 0xAB, 0x3D, 0xD4, 0x9B, 0x2C, 0xDF, 0x7B, 0xB7, 0xF0, 0xAB,
+	0x55, 0x2F, 0x1B, 0x7C, 0x4A, 0xF0, 0x1F, 0xC2, 0xBD, 0x25, 0xF5, 0xEF, 0x8B, 0xBE, 0x36, 0xB1,
+	0xF0, 0xBD, 0xBD, 0xBD, 0xAB, 0x5C, 0x2D, 0xC6, 0xA5, 0x2A, 0xAA, 0xDC, 0x2A, 0xFF, 0x00, 0xCB,
+	0x35, 0xFF, 0x00, 0x69, 0xA8, 0x02, 0x1F, 0xDA, 0x53, 0xF6, 0x90, 0xD3, 0x7F, 0x65, 0x3F, 0x80,
+	0x9E, 0x26, 0xFD, 0xA0, 0xB5, 0x8D, 0x36, 0x3B, 0xF5, 0xD0, 0x6C, 0x24, 0xDD, 0xA5, 0xC9, 0x36,
+	0xD6, 0xBA, 0xDC, 0xBB, 0x7E, 0x5F, 0xEF, 0x57, 0xF3, 0x19, 0xE3, 0xCF, 0x15, 0x5C, 0xFC, 0x54,
+	0xF8, 0xA7, 0xE2, 0x0F, 0x1C, 0xF8, 0x57, 0xC3, 0x72, 0x35, 0xF7, 0x89, 0xB5, 0x99, 0x2F, 0xEC,
+	0xF4, 0xBF, 0xBC, 0xDB, 0xA4, 0x6F, 0xF5, 0x7F, 0xF8, 0xF5, 0x7D, 0x57, 0xFF, 0x00, 0x05, 0x5A,
+	0xFF, 0x00, 0x82, 0xAA, 0x78, 0xA3, 0xF6, 0xF5, 0xF1, 0xDC, 0x7E, 0x09, 0xF8, 0x75, 0x25, 0xE6,
+	0x93, 0xF0, 0xFF, 0x00, 0xC3, 0x77, 0x52, 0x26, 0x97, 0x66, 0xAD, 0xB6, 0x4B, 0xE6, 0x5F, 0xBC,
+	0xD2, 0xFF, 0x00, 0x79, 0x69, 0x9F, 0xF0, 0x48, 0xDF, 0xD8, 0x87, 0xE2, 0x2F, 0xED, 0x2D, 0xF1,
+	0xC7, 0xC3, 0xFF, 0x00, 0x1B, 0x3C, 0x29, 0x35, 0x9A, 0x78, 0x63, 0xC1, 0x7A, 0xB2, 0xDE, 0x6A,
+	0x5A, 0x95, 0xD2, 0xFF, 0x00, 0xA3, 0x5E, 0x32, 0xB7, 0xCD, 0x6E, 0xBF, 0xED, 0x50, 0x07, 0xEB,
+	0x07, 0xFC, 0x12, 0x57, 0xF6, 0x53, 0xF0, 0xF7, 0xEC, 0x7B, 0xFB, 0x1B, 0xE8, 0xFA, 0x56, 0x89,
+	0x6C, 0xD0, 0xDF, 0x78, 0xDA, 0x28, 0xF5, 0x6D, 0x7A, 0xD6, 0x4F, 0xBD, 0x6F, 0x70, 0xDF, 0xC3,
+	0x5E, 0xD7, 0xE2, 0xCD, 0x40, 0xDD, 0x78, 0x9A, 0xCE, 0x1F, 0xBB, 0xFE, 0x95, 0x1D, 0x4F, 0x79,
+	0xE2, 0x0B, 0x3B, 0xCD, 0x49, 0xEF, 0xF4, 0xDB, 0x6F, 0xB3, 0x43, 0x26, 0xDD, 0xB6, 0xF1, 0xFC,
+	0xAB, 0x1F, 0xCB, 0xFC, 0x35, 0x81, 0x75, 0x7D, 0xF6, 0x8F, 0x1B, 0xE9, 0xF0, 0xEF, 0xDD, 0xFE,
+	0x90, 0xB4, 0x01, 0xF5, 0x9D, 0x90, 0xFF, 0x00, 0x44, 0xB7, 0x73, 0xFF, 0x00, 0x3C, 0xD7, 0xFF,
+	0x00, 0x41, 0xA9, 0xD5, 0x76, 0xD4, 0x56, 0x7F, 0xF1, 0xEB, 0x0F, 0xFD, 0x73, 0x5A, 0x9A, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x18, 0xFF, 0x00, 0x77, 0xFE, 0x03, 0x5F, 0x34, 0x68, 0x3A, 0x91, 0x8F,
+	0xC5, 0x1A, 0x97, 0xFD, 0x84, 0xA4, 0xFF, 0x00, 0xD0, 0xAB, 0xE9, 0x69, 0x78, 0x46, 0xCF, 0xF7,
+	0x5A, 0xBE, 0x49, 0xD2, 0xF5, 0x4F, 0x2F, 0xC6, 0x1A, 0xA2, 0x7F, 0xD4, 0x52, 0x4A, 0x00, 0xF5,
+	0x39, 0x35, 0x42, 0xCA, 0xBC, 0xD2, 0x36, 0xA8, 0xFB, 0xBF, 0xD7, 0x32, 0xAF, 0xF1, 0x6D, 0x6D,
+	0xB5, 0xCE, 0xB6, 0xA8, 0x9B, 0x57, 0xE7, 0xA7, 0x7F, 0x6A, 0x21, 0x65, 0xF9, 0xE8, 0x03, 0x9A,
+	0xFD, 0xA7, 0x3F, 0x65, 0x4F, 0xD9, 0x7F, 0xF6, 0xD5, 0xF0, 0x7D, 0x97, 0xC3, 0xEF, 0xDA, 0xAF,
+	0xE1, 0x0E, 0x9F, 0xE2, 0x6D, 0x07, 0x4D, 0x91, 0xA4, 0xB0, 0xB7, 0x82, 0xDF, 0xCA, 0x78, 0x64,
+	0x6F, 0xE2, 0xDD, 0x5F, 0x8A, 0xDF, 0xB7, 0xC7, 0xFC, 0x1A, 0x7B, 0xF1, 0x3B, 0xC0, 0xDA, 0x0D,
+	0xD7, 0xC4, 0xDF, 0xD8, 0xB7, 0xE2, 0x0A, 0x78, 0xCA, 0xE3, 0x50, 0xD6, 0xA4, 0x36, 0x3F, 0x0F,
+	0x23, 0x8B, 0x6C, 0xD6, 0x76, 0xCC, 0xCC, 0xCA, 0xA2, 0x4D, 0xDF, 0x36, 0xDA, 0xFD, 0xD0, 0x6D,
+	0x53, 0xCC, 0x5F, 0xBF, 0xB7, 0x6F, 0xF0, 0xD2, 0xDA, 0x6B, 0xD3, 0x69, 0xB7, 0x0D, 0x73, 0x65,
+	0x79, 0x25, 0xBC, 0x8C, 0xBB, 0x56, 0x6B, 0x76, 0xDA, 0xD4, 0x01, 0xFC, 0x6B, 0x6A, 0xDF, 0x04,
+	0xFE, 0x27, 0xFC, 0x02, 0xFD, 0xA2, 0x74, 0xCF, 0x85, 0xDF, 0x17, 0xFC, 0x17, 0x7B, 0xA0, 0xEB,
+	0xDA, 0x6F, 0x89, 0x6D, 0xE0, 0xBE, 0xB1, 0xBD, 0x87, 0x6F, 0x96, 0xDE, 0x72, 0xFF, 0x00, 0x17,
+	0xF1, 0x57, 0xF6, 0x01, 0xFB, 0x24, 0xDE, 0x3A, 0xFE, 0xCB, 0xBE, 0x0B, 0xB2, 0x85, 0xFE, 0x68,
+	0xF4, 0x98, 0xF6, 0x37, 0xF7, 0xBF, 0x77, 0x5C, 0x6F, 0xED, 0x35, 0xFB, 0x1B, 0xFE, 0xCB, 0x5F,
+	0xB6, 0x17, 0x83, 0x17, 0xC0, 0xDF, 0x1C, 0xBE, 0x17, 0xE9, 0xBB, 0x63, 0xD4, 0x56, 0xFF, 0x00,
+	0xFE, 0x12, 0x0B, 0x3B, 0x55, 0x5D, 0x41, 0xAE, 0x17, 0xFB, 0xD2, 0x7D, 0xEA, 0xF4, 0x2F, 0x03,
+	0xE8, 0x7A, 0x3F, 0xC3, 0x1F, 0x05, 0xE9, 0x7E, 0x03, 0xF0, 0xC3, 0xB3, 0xE9, 0xFA, 0x4D, 0xBF,
+	0x91, 0x61, 0xE6, 0x7D, 0xEF, 0x2F, 0xFD, 0xAA, 0x00, 0xEE, 0x20, 0xD5, 0xDA, 0xD6, 0x64, 0xB8,
+	0x8A, 0x1B, 0x5B, 0x96, 0xDA, 0xC1, 0xA3, 0xBE, 0x8F, 0xCD, 0x55, 0x56, 0xFB, 0xDB, 0x77, 0x7D,
+	0xDA, 0xFC, 0xFC, 0xFF, 0x00, 0x82, 0x83, 0x7F, 0xC1, 0xBB, 0x1F, 0xB1, 0x57, 0xED, 0xC8, 0xDF,
+	0xDB, 0xFF, 0x00, 0x0C, 0x62, 0xB7, 0xF8, 0x63, 0xE3, 0x4B, 0xED, 0x51, 0xAF, 0x35, 0xCF, 0x15,
+	0xAA, 0x6E, 0x8A, 0xEF, 0x77, 0xF0, 0xF9, 0x7B, 0xB6, 0xD7, 0xDB, 0x30, 0xEA, 0x89, 0x1B, 0x7F,
+	0x13, 0x7F, 0x79, 0x7F, 0x8A, 0xAC, 0x49, 0xA8, 0x42, 0xD2, 0x6D, 0x77, 0x57, 0x8F, 0x6F, 0xDD,
+	0x6F, 0xE1, 0xA0, 0x0F, 0xE5, 0x73, 0xF6, 0xFC, 0xFF, 0x00, 0x82, 0x24, 0x7E, 0xD9, 0xDF, 0xB0,
+	0x8E, 0xB9, 0xAD, 0x78, 0x87, 0x5A, 0xF8, 0x7B, 0x79, 0xE2, 0x1F, 0x01, 0x69, 0xBA, 0x97, 0x93,
+	0x67, 0xE3, 0x6B, 0x1B, 0x7C, 0xC7, 0x79, 0x1F, 0xF7, 0xBC, 0xBD, 0xDB, 0xAB, 0xEC, 0x1F, 0xF8,
+	0x34, 0x62, 0x63, 0x65, 0xFB, 0x40, 0xF8, 0xC5, 0x8C, 0x5F, 0x36, 0xC5, 0x1E, 0x5B, 0x7C, 0xAD,
+	0xF7, 0x6B, 0xF7, 0x63, 0x5D, 0xBC, 0xB1, 0xD6, 0xED, 0x63, 0xD2, 0x7C, 0x53, 0xA4, 0x5A, 0xEB,
+	0x5A, 0x7A, 0xB6, 0x53, 0x4B, 0xD5, 0x17, 0xCC, 0xB5, 0x6F, 0xFB, 0x67, 0x5E, 0x43, 0xF0, 0x97,
+	0xF6, 0x17, 0xFD, 0x98, 0x3E, 0x07, 0xFC, 0x7A, 0xD6, 0xFF, 0x00, 0x69, 0x3F, 0x85, 0x3E, 0x12,
+	0xFE, 0xC4, 0xF1, 0x16, 0xBD, 0x2E, 0xFD, 0x4A, 0xC7, 0x4F, 0x8B, 0xCB, 0xB5, 0x56, 0xFF, 0x00,
+	0xA6, 0x6B, 0x40, 0x1E, 0xFD, 0xE2, 0x2D, 0x5D, 0x3E, 0xC3, 0x27, 0xF0, 0xB6, 0xE6, 0xF9, 0x69,
+	0x3F, 0x65, 0xEB, 0x8F, 0xB4, 0x78, 0xD3, 0x56, 0x7F, 0xFA, 0x77, 0xFF, 0x00, 0xD9, 0xAB, 0x9C,
+	0xF1, 0x16, 0xB4, 0x8D, 0x6A, 0xD3, 0x7F, 0x7B, 0x71, 0xAD, 0xCF, 0xD9, 0x1E, 0x63, 0x71, 0xE2,
+	0x2D, 0x56, 0x5F, 0xFA, 0x63, 0xFF, 0x00, 0xB3, 0x50, 0x07, 0xBC, 0x46, 0xBF, 0x2A, 0x9A, 0x75,
+	0x35, 0x3A, 0x53, 0xA8, 0x00, 0xA2, 0x8A, 0x4D, 0xDF, 0x2E, 0x68, 0x03, 0xCE, 0x3F, 0x69, 0xD9,
+	0xBC, 0x9F, 0x87, 0x21, 0xFF, 0x00, 0xE9, 0xF2, 0x3A, 0xE2, 0xFC, 0x23, 0xAA, 0x37, 0xD9, 0x7E,
+	0xFF, 0x00, 0xF0, 0xD7, 0x55, 0xFB, 0x5A, 0x5D, 0x1B, 0x7F, 0x85, 0x9E, 0x67, 0xFD, 0x3F, 0x47,
+	0x5E, 0x63, 0xE1, 0x1D, 0x56, 0x36, 0xB5, 0xE5, 0xFF, 0x00, 0x86, 0x80, 0x3B, 0xA6, 0xD4, 0xBC,
+	0xC5, 0xFB, 0xEC, 0xBF, 0xED, 0x2B, 0x6D, 0x6A, 0xF8, 0xAB, 0xFE, 0x0A, 0x93, 0xFF, 0x00, 0x04,
+	0x62, 0xF0, 0x0F, 0xFC, 0x14, 0x97, 0xC7, 0xFE, 0x15, 0xF8, 0xF7, 0xF0, 0xE7, 0xE2, 0x34, 0x3F,
+	0x0A, 0xBE, 0x2F, 0x78, 0x76, 0xF1, 0x5E, 0xE3, 0xE2, 0x15, 0x9C, 0x38, 0x4B, 0xAB, 0x78, 0xF7,
+	0x6C, 0x8E, 0x44, 0x56, 0x5D, 0xCC, 0xBF, 0xDE, 0xFF, 0x00, 0x7B, 0xF8, 0x59, 0x96, 0xBE, 0xB4,
+	0xFE, 0xD5, 0x5F, 0xEF, 0xD3, 0x1B, 0x51, 0x85, 0xA6, 0xD9, 0xF7, 0xB7, 0x7D, 0xE5, 0x92, 0x80,
+	0x3F, 0x2E, 0x7F, 0x66, 0xBF, 0xDA, 0x13, 0xFE, 0x0B, 0xE3, 0xFB, 0x01, 0x78, 0x8B, 0xC7, 0x1E,
+	0x0B, 0xF8, 0xBF, 0xFB, 0x18, 0x6A, 0x1F, 0xB4, 0x3E, 0x95, 0xA5, 0xEA, 0x2C, 0xDA, 0x2F, 0x8D,
+	0x9A, 0xE1, 0x63, 0xFB, 0x45, 0x9A, 0xFF, 0x00, 0xCB, 0x48, 0xFF, 0x00, 0xD9, 0xDA, 0xAA, 0xDF,
+	0x77, 0xFE, 0xFA, 0xFB, 0xD5, 0x8F, 0x7B, 0xFF, 0x00, 0x07, 0x8D, 0xF8, 0xDB, 0x41, 0xF1, 0x34,
+	0xFE, 0x04, 0xF1, 0x1F, 0xFC, 0x13, 0x9E, 0xFA, 0xDB, 0xC4, 0x11, 0xDC, 0xFD, 0x95, 0x34, 0x9F,
+	0xED, 0x26, 0x59, 0x56, 0x6D, 0xDB, 0x44, 0x7B, 0x76, 0xEE, 0x6F, 0x9B, 0xFB, 0xB5, 0xFA, 0xD3,
+	0x1F, 0x8B, 0xB5, 0xA8, 0x61, 0xFB, 0x1C, 0x3A, 0xF5, 0xE2, 0xC6, 0xAB, 0xB3, 0xEC, 0xFF, 0x00,
+	0x68, 0xFD, 0xDB, 0x2F, 0xF7, 0x76, 0xD7, 0x2D, 0x75, 0xF0, 0xD3, 0xE0, 0x3D, 0xF5, 0xE7, 0xF6,
+	0xAD, 0xCF, 0xEC, 0xF7, 0xE0, 0xD9, 0xAF, 0xA4, 0x97, 0xCC, 0x6D, 0x4A, 0x6D, 0x2D, 0x5A, 0x7F,
+	0x33, 0xFB, 0xDB, 0xB6, 0xFD, 0xEA, 0x5C, 0xC9, 0x6E, 0x35, 0x0E, 0x73, 0xF3, 0xD7, 0xE3, 0x0F,
+	0xC7, 0x2F, 0xF8, 0x2F, 0x47, 0xFC, 0x14, 0x83, 0xE2, 0x57, 0x80, 0x7E, 0x17, 0x7C, 0x34, 0xFD,
+	0x96, 0x75, 0x2F, 0xD9, 0x5F, 0x43, 0xBD, 0x86, 0xE2, 0xEF, 0xC4, 0xDF, 0x11, 0x26, 0xB8, 0x59,
+	0xD6, 0x6B, 0x36, 0x8F, 0x76, 0xD6, 0xFF, 0x00, 0x67, 0x6A, 0xFD, 0xDF, 0xF6, 0xBE, 0xF5, 0x7E,
+	0x4C, 0xFC, 0x15, 0xF1, 0xEF, 0xC6, 0x2F, 0x84, 0xFE, 0x27, 0xF8, 0x91, 0xF0, 0x81, 0xBE, 0x34,
+	0xDD, 0x6A, 0x9A, 0x06, 0x9F, 0xE3, 0x9B, 0xCB, 0x7D, 0x4A, 0x18, 0xEE, 0xB6, 0xFF, 0x00, 0x68,
+	0x5D, 0x2C, 0x8C, 0xAD, 0x75, 0xFF, 0x00, 0x02, 0xDB, 0x5F, 0xD4, 0xD4, 0x7E, 0x30, 0xD6, 0x82,
+	0xF9, 0x33, 0xEB, 0x97, 0x53, 0x43, 0xE5, 0x34, 0x3E, 0x4B, 0x49, 0xBA, 0x3F, 0x2D, 0x97, 0x6B,
+	0x2E, 0xDF, 0xF7, 0x6B, 0xF9, 0xFB, 0xFF, 0x00, 0x82, 0xE0, 0xFF, 0x00, 0xC1, 0x1E, 0x7C, 0x77,
+	0xFB, 0x18, 0xFC, 0x41, 0xD4, 0x3F, 0x6D, 0x9F, 0xD9, 0x16, 0xC7, 0x50, 0xD6, 0x7E, 0x18, 0xEB,
+	0xB7, 0xD2, 0x5D, 0x6B, 0xFA, 0x48, 0x2D, 0x25, 0xCE, 0x93, 0x74, 0xDB, 0x9A, 0x59, 0x65, 0x55,
+	0xFF, 0x00, 0x96, 0x2C, 0xCD, 0xF7, 0xAB, 0xD8, 0xC8, 0x73, 0x0F, 0xEC, 0xBC, 0xC2, 0x15, 0xEB,
+	0x2B, 0xC5, 0x74, 0xED, 0xE6, 0x78, 0xD9, 0xF6, 0x0E, 0xA6, 0x6D, 0x96, 0x54, 0xC3, 0x50, 0x76,
+	0x6D, 0x6F, 0xDF, 0xCB, 0xE6, 0x72, 0x9E, 0x05, 0xF8, 0x85, 0x79, 0xA7, 0x47, 0x0D, 0xE5, 0xB5,
+	0xCB, 0x6F, 0x6F, 0x95, 0x77, 0x36, 0xEF, 0x31, 0x7F, 0xBA, 0xD5, 0xE6, 0x9F, 0xB5, 0xF7, 0xEC,
+	0xD4, 0x3E, 0x22, 0x08, 0xBE, 0x35, 0xFC, 0x2B, 0x93, 0xFB, 0x23, 0x53, 0xD3, 0x19, 0x66, 0xBA,
+	0xB7, 0xB6, 0xF9, 0x64, 0x17, 0x0B, 0xF3, 0x2C, 0x8A, 0xDF, 0xC3, 0xF3, 0x7C, 0xD5, 0xC8, 0x7C,
+	0x0E, 0xF8, 0xDB, 0xA6, 0xF8, 0xCB, 0x4F, 0x5B, 0xAB, 0x19, 0x3C, 0xB9, 0x62, 0xF9, 0x5A, 0x39,
+	0xBF, 0x89, 0xBF, 0xBC, 0xB5, 0xEE, 0xDE, 0x10, 0xF1, 0x8A, 0x49, 0x17, 0x93, 0x0B, 0xAC, 0x92,
+	0xC9, 0xC4, 0x8B, 0x27, 0xDD, 0x91, 0x6B, 0xFA, 0x3D, 0x7F, 0x65, 0xF1, 0x5E, 0x4F, 0xEC, 0xB1,
+	0x4F, 0x9E, 0x32, 0x4A, 0xCD, 0x6F, 0x7E, 0x9F, 0x73, 0xD4, 0xFE, 0x60, 0x9D, 0x3C, 0xE3, 0x83,
+	0x73, 0xBF, 0xAC, 0x61, 0x17, 0x24, 0xE2, 0xF5, 0x4F, 0x66, 0xBA, 0xAE, 0xCE, 0xE8, 0xFB, 0xEF,
+	0xFE, 0x08, 0x35, 0xFF, 0x00, 0x05, 0xDB, 0x1F, 0xB5, 0x25, 0xAD, 0x97, 0xEC, 0x43, 0xFB, 0x6C,
+	0xEB, 0x70, 0xE9, 0xFF, 0x00, 0x13, 0x34, 0x98, 0x16, 0xDF, 0xC2, 0x7E, 0x2A, 0xBA, 0x75, 0x8F,
+	0xFE, 0x12, 0x55, 0x5D, 0xCA, 0xB6, 0xB2, 0x7C, 0xBF, 0x2B, 0xAA, 0xAF, 0xDE, 0xFE, 0x2A, 0xFD,
+	0x52, 0xFE, 0xD2, 0x9A, 0xDE, 0xE1, 0xAC, 0xAE, 0x5F, 0xF7, 0x90, 0xB6, 0xC9, 0x57, 0xF8, 0x55,
+	0xBF, 0xDE, 0xFE, 0x2A, 0xFE, 0x50, 0xFF, 0x00, 0x6B, 0x5F, 0xD9, 0xDE, 0xFD, 0x2F, 0x57, 0xE3,
+	0x3F, 0xC2, 0x3B, 0xC9, 0x34, 0xFD, 0x5B, 0x4B, 0x65, 0xB8, 0xF3, 0x2C, 0xA5, 0x68, 0xE5, 0x8D,
+	0x97, 0x73, 0x6E, 0x46, 0x5F, 0xBB, 0x5F, 0xBD, 0xDF, 0xF0, 0x45, 0x8F, 0xDB, 0x8B, 0xC5, 0xBF,
+	0xB7, 0x6F, 0xFC, 0x13, 0xDF, 0x43, 0xF8, 0xC5, 0xE3, 0x9B, 0x6F, 0x2F, 0x54, 0xF0, 0xDD, 0xC2,
+	0xF8, 0x7A, 0xE1, 0x99, 0xB7, 0x3D, 0xC3, 0x43, 0xF2, 0xF9, 0xCC, 0xDF, 0xC4, 0xCD, 0x5F, 0xCF,
+	0x3C, 0x49, 0xC3, 0xF8, 0xCE, 0x1B, 0xCC, 0x1E, 0x1E, 0xAF, 0x5F, 0x86, 0x5D, 0xD1, 0xFD, 0x2F,
+	0xC3, 0x7C, 0x43, 0x81, 0xE2, 0x3C, 0xAE, 0x18, 0x9C, 0x3A, 0xF2, 0x94, 0x7B, 0x33, 0xE9, 0xAF,
+	0x89, 0xDA, 0xA6, 0xEB, 0x59, 0x13, 0xFB, 0xCD, 0x5E, 0xE1, 0xF0, 0x88, 0x93, 0xF0, 0xE7, 0x48,
+	0xFF, 0x00, 0xAF, 0x7A, 0xF9, 0xB7, 0xC7, 0xDA, 0xA7, 0x9C, 0xCA, 0x9B, 0xFE, 0xF3, 0x57, 0xD2,
+	0x9F, 0x09, 0xD5, 0x7F, 0xE1, 0x5E, 0x68, 0xFF, 0x00, 0xF5, 0xEB, 0x5F, 0x3F, 0x78, 0xA4, 0x93,
+	0x5E, 0xBE, 0xA7, 0xD1, 0x49, 0xCA, 0x51, 0xE6, 0x7F, 0x2F, 0x43, 0xA6, 0xA2, 0x8A, 0x28, 0x24,
+	0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x8C, 0xFF, 0x00, 0xAC,
+	0x6F, 0xEE, 0xED, 0xAF, 0x87, 0xF4, 0xBF, 0x10, 0x79, 0x7E, 0x3C, 0xD6, 0xEC, 0xEE, 0x5F, 0x74,
+	0x9F, 0xDA, 0xD2, 0x7F, 0xBA, 0xAB, 0xBA, 0xBE, 0xDE, 0x94, 0x3A, 0xEF, 0x7F, 0xBD, 0xF2, 0xFC,
+	0xAB, 0x5F, 0x9B, 0x1E, 0x3A, 0xBD, 0xF1, 0x67, 0xC2, 0x6F, 0x8E, 0x5A, 0xC7, 0x82, 0xBC, 0x6B,
+	0x0B, 0x5B, 0x5D, 0x5F, 0x5E, 0x49, 0x79, 0x6E, 0xAD, 0xFC, 0x50, 0xB3, 0x7C, 0xAD, 0xBA, 0x88,
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+	0xF8, 0x77, 0x66, 0xB9, 0xBF, 0xED, 0x67, 0x71, 0x9D, 0xF4, 0x7F, 0x6A, 0x39, 0xFF, 0x00, 0x96,
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+	0xB6, 0x9F, 0x93, 0xE5, 0xDD, 0xF7, 0xAA, 0x1F, 0xED, 0x87, 0xFE, 0xF2, 0xD7, 0x3B, 0x36, 0xA5,
+	0x33, 0x37, 0xFF, 0x00, 0x65, 0x51, 0xB5, 0xF3, 0xE7, 0x3F, 0xFB, 0x35, 0x00, 0x74, 0x92, 0x6A,
+	0x88, 0xDF, 0x7E, 0x95, 0xF5, 0x82, 0xDC, 0x3B, 0xB5, 0x73, 0x1F, 0xDA, 0x93, 0x2F, 0xF1, 0xD1,
+	0xFD, 0xA7, 0x37, 0xFC, 0xF4, 0x5A, 0x00, 0xE9, 0xD7, 0x58, 0x45, 0x6D, 0xFB, 0xDB, 0x75, 0x73,
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+	0x0D, 0xBF, 0x9C, 0xF3, 0x2A, 0xAC, 0x7F, 0x7A, 0xBC, 0x8F, 0xE3, 0xDF, 0xC5, 0x67, 0xD3, 0xF4,
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+	0xBE, 0x83, 0xAD, 0x43, 0x36, 0x9E, 0x8F, 0xFF, 0x00, 0x3D, 0x3F, 0xE5, 0x9F, 0xF7, 0x6A, 0xEA,
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+	0xAA, 0x6A, 0x51, 0xB1, 0x93, 0x52, 0xD3, 0xDB, 0xE6, 0xB7, 0xF9, 0xB6, 0xFC, 0xB5, 0xF2, 0x2F,
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+	0xE1, 0x8F, 0xFC, 0x12, 0x1F, 0xF6, 0x15, 0xF0, 0x2F, 0x87, 0xF4, 0xB8, 0xB5, 0xEF, 0x86, 0x32,
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+	0x93, 0xAF, 0x6B, 0x7A, 0x3C, 0x9E, 0x1B, 0xF8, 0x6B, 0xA8, 0x5C, 0x2A, 0xEA, 0xDA, 0xF5, 0xC2,
+	0xEC, 0xBE, 0xB5, 0x8D, 0x7F, 0xE7, 0x9A, 0xFF, 0x00, 0xB5, 0x5F, 0xB7, 0x3F, 0x06, 0xFE, 0x0E,
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+	0x22, 0xF8, 0x87, 0xFB, 0x5C, 0x68, 0xBE, 0x12, 0xD5, 0x6D, 0x9A, 0x6D, 0x3E, 0x4B, 0x49, 0x25,
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+	0xAD, 0xFB, 0xBF, 0xEF, 0x57, 0xE6, 0xCF, 0x8D, 0x2F, 0xBC, 0x5F, 0xF0, 0x97, 0xE3, 0xAE, 0xAD,
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+	0x6D, 0x43, 0xE5, 0xFF, 0x00, 0xEC, 0xA8, 0x03, 0xA6, 0xFE, 0xD8, 0x4F, 0xEF, 0x51, 0xFD, 0xB6,
+	0xBF, 0xDF, 0x6A, 0xE6, 0x7F, 0xB4, 0xBF, 0xDA, 0xA3, 0xFB, 0x4D, 0xFF, 0x00, 0xE7, 0xA5, 0x00,
+	0x76, 0x11, 0xEA, 0x46, 0x48, 0xD5, 0xDF, 0x6B, 0x53, 0x26, 0xD4, 0x92, 0x2F, 0xB9, 0xB5, 0x5A,
+	0xB9, 0xA8, 0xF5, 0x97, 0xDA, 0xBF, 0xFC, 0x55, 0x36, 0x4D, 0x51, 0xDA, 0x80, 0x3A, 0x15, 0xD5,
+	0xB6, 0xB7, 0x9D, 0xBF, 0x6B, 0xFF, 0x00, 0x7A, 0x85, 0xD5, 0x11, 0x43, 0x7C, 0xFF, 0x00, 0x7A,
+	0xB9, 0xA5, 0xD4, 0x1D, 0xBF, 0x8F, 0x6D, 0x0D, 0xA9, 0xBA, 0xFF, 0x00, 0x1D, 0x00, 0x74, 0xBF,
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+	0x52, 0x75, 0xEF, 0xB9, 0xA9, 0xAD, 0xA9, 0x6D, 0x56, 0x91, 0xFE, 0x5D, 0xBF, 0xED, 0x50, 0x06,
+	0xC7, 0x89, 0x35, 0x64, 0x86, 0xC7, 0x7B, 0xCD, 0xFE, 0xEA, 0xFF, 0x00, 0x7A, 0xBB, 0x2F, 0xD8,
+	0x92, 0xEF, 0xED, 0x7A, 0xC6, 0xAB, 0x29, 0x9B, 0x73, 0x32, 0xFD, 0xDA, 0xF9, 0xF7, 0xE2, 0x57,
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+	0x98, 0xAB, 0x6F, 0xAE, 0x7C, 0x0A, 0x9B, 0xC7, 0x37, 0x31, 0x33, 0x5F, 0x5D, 0x6A, 0x93, 0x44,
+	0xF7, 0x12, 0x2E, 0xDF, 0x95, 0x76, 0xFC, 0xB4, 0x01, 0xF4, 0xBC, 0x2A, 0xEA, 0xBF, 0x3F, 0x5A,
+	0x7D, 0x32, 0x35, 0x65, 0xC6, 0xFF, 0x00, 0x98, 0xFF, 0x00, 0x7A, 0x9F, 0x40, 0x08, 0xFF, 0x00,
+	0x76, 0x9A, 0x37, 0xB2, 0x95, 0x6E, 0x0D, 0x39, 0xFE, 0xED, 0x33, 0x1F, 0x2E, 0xFF, 0x00, 0xBC,
+	0xCB, 0x40, 0x1E, 0x3F, 0xFB, 0x6A, 0xDD, 0x7D, 0x83, 0xE0, 0xAF, 0xDA, 0x59, 0xF6, 0xED, 0xD4,
+	0xA3, 0x1F, 0xFA, 0x15, 0x78, 0xCF, 0x84, 0x75, 0x88, 0x5A, 0xCF, 0xCE, 0x86, 0x6F, 0x99, 0x76,
+	0xFC, 0xAD, 0x5E, 0xB9, 0xFB, 0x76, 0xF8, 0x47, 0xC6, 0x5E, 0x31, 0xF8, 0x05, 0x77, 0x67, 0xE0,
+	0x6B, 0x36, 0x9A, 0xEE, 0xD2, 0xE1, 0x6F, 0x2E, 0x15, 0x5B, 0xE6, 0x10, 0xC7, 0xB9, 0x9A, 0xBE,
+	0x46, 0xF8, 0x37, 0xF1, 0x5A, 0xC3, 0x56, 0xB3, 0xF3, 0xA6, 0x46, 0x92, 0x3D, 0xDB, 0x3F, 0xBA,
+	0xCA, 0xCB, 0x40, 0x1E, 0xF2, 0xDA, 0xB6, 0x1F, 0xCE, 0x93, 0xE5, 0x66, 0xFB, 0xAA, 0xBF, 0x76,
+	0x91, 0xB5, 0x8F, 0x9B, 0x7E, 0xFF, 0x00, 0x9A, 0xB9, 0x88, 0x75, 0x69, 0xA4, 0x85, 0xF6, 0x5E,
+	0x2B, 0x23, 0x2F, 0xEE, 0xBF, 0xD9, 0xA1, 0x75, 0x49, 0x95, 0x55, 0x37, 0xD0, 0x07, 0x4D, 0xFD,
+	0xB0, 0x9B, 0xBE, 0xF7, 0x34, 0xE8, 0x75, 0x94, 0x76, 0xFD, 0xE3, 0xEE, 0xAE, 0x57, 0xFB, 0x45,
+	0xFF, 0x00, 0xBF, 0x52, 0xDB, 0xEA, 0x8E, 0xAD, 0xF7, 0xD6, 0xAA, 0x2E, 0x09, 0x3E, 0x60, 0xEA,
+	0x75, 0xBF, 0xDA, 0x90, 0xAA, 0xEC, 0x43, 0x85, 0xAA, 0x7A, 0xB3, 0x68, 0xFA, 0xB6, 0x9B, 0x7F,
+	0xE1, 0xBF, 0x10, 0xE8, 0xD0, 0xEA, 0x9A, 0x46, 0xB1, 0x6A, 0xD6, 0xFA, 0xB6, 0x93, 0x74, 0xAA,
+	0xD1, 0x5F, 0x42, 0xCB, 0xB7, 0xCB, 0x6D, 0xD5, 0x8B, 0xFD, 0xB1, 0xFE, 0xD2, 0xD4, 0x37, 0x1A,
+	0xA4, 0xD3, 0x4D, 0xB1, 0x13, 0x7A, 0xFF, 0x00, 0x15, 0x42, 0xE6, 0xE5, 0xD3, 0x7E, 0xFF, 0x00,
+	0xA0, 0xAD, 0xEC, 0xE5, 0x7B, 0x68, 0x7E, 0x12, 0xFF, 0x00, 0xC1, 0x64, 0x3F, 0xE0, 0x91, 0x3E,
+	0x2A, 0xFD, 0x82, 0x3E, 0x22, 0xDC, 0x7E, 0xD6, 0x5F, 0xB2, 0xB6, 0x9D, 0x75, 0xA9, 0x7C, 0x27,
+	0xD5, 0xAF, 0xB3, 0xA9, 0x5A, 0xD9, 0xC5, 0x93, 0xA0, 0xDD, 0x33, 0x6E, 0x68, 0x02, 0xAF, 0xFC,
+	0xB1, 0x5F, 0xEF, 0x7F, 0x95, 0xF0, 0x9F, 0x82, 0xDF, 0x1D, 0xB4, 0x1F, 0x13, 0xE9, 0xF2, 0x5D,
+	0xD8, 0xDD, 0xAB, 0x5C, 0x5B, 0xAA, 0xF9, 0xF1, 0xEE, 0xFF, 0x00, 0xD0, 0x6B, 0xFA, 0x43, 0xD7,
+	0x34, 0xFD, 0x1F, 0xC5, 0xDE, 0x1B, 0xD5, 0x3C, 0x1F, 0xE2, 0xAB, 0x0B, 0x7B, 0xFD, 0x2B, 0x58,
+	0xB2, 0x6B, 0x3D, 0x4B, 0x4F, 0xBA, 0x8B, 0xCC, 0x8D, 0xAD, 0xDB, 0xEF, 0x6D, 0x5F, 0xEF, 0x7F,
+	0xB5, 0x5F, 0x98, 0x5F, 0xB4, 0x2F, 0xFC, 0x1B, 0x3F, 0xE0, 0x9F, 0x1A, 0xFC, 0x48, 0x5F, 0x16,
+	0xFE, 0xC8, 0x3F, 0x1B, 0x6D, 0xBE, 0x1E, 0xE9, 0x89, 0xBB, 0x76, 0x97, 0xA9, 0x33, 0x48, 0xC7,
+	0x77, 0xF7, 0x7E, 0x6A, 0xFA, 0x5E, 0x1E, 0xE2, 0xCC, 0x67, 0x0E, 0xD4, 0xBD, 0x3F, 0x7A, 0x3F,
+	0x69, 0x3E, 0x9D, 0x34, 0xF3, 0x3E, 0x6B, 0x89, 0x38, 0x4F, 0x07, 0xC4, 0x94, 0x5B, 0x9B, 0x51,
+	0x9F, 0xD9, 0x7D, 0xFD, 0x7C, 0xAC, 0x7C, 0x23, 0xF1, 0x53, 0xF6, 0x80, 0xD1, 0x34, 0x5F, 0x0A,
+	0xDE, 0x47, 0x3D, 0xD2, 0xA7, 0xEE, 0x19, 0x55, 0xA4, 0x6F, 0xBC, 0xCC, 0xBF, 0x76, 0xBF, 0x56,
+	0x3F, 0xE0, 0xD8, 0xE6, 0xD6, 0x34, 0xBF, 0xF8, 0x25, 0xBD, 0xFC, 0x7A, 0xAE, 0x99, 0x71, 0x67,
+	0xF6, 0x8F, 0x1F, 0x4D, 0x3C, 0x4B, 0x75, 0x1B, 0x46, 0xD3, 0x46, 0xCD, 0xFE, 0xB2, 0x3F, 0xEF,
+	0x2F, 0xFB, 0x55, 0xF3, 0xDF, 0xC2, 0x4F, 0xF8, 0x36, 0x1E, 0xFF, 0x00, 0x44, 0xF8, 0xCD, 0xA1,
+	0x78, 0xC7, 0xF6, 0x86, 0xFD, 0xA8, 0xB4, 0xBF, 0x18, 0x78, 0x4F, 0x4D, 0xBC, 0x5B, 0x8D, 0x67,
+	0xC3, 0xF6, 0xA8, 0xC9, 0x36, 0xA0, 0xAB, 0xF7, 0x63, 0x56, 0xDD, 0xF7, 0x6B, 0xF5, 0x41, 0x6E,
+	0x74, 0x1F, 0x07, 0xE8, 0x76, 0x3A, 0x27, 0x86, 0xF4, 0x7B, 0x3D, 0x2F, 0x49, 0xD2, 0x6D, 0x56,
+	0xCF, 0x4B, 0xD3, 0xEC, 0xE2, 0x58, 0x96, 0x3B, 0x75, 0xFB, 0xAA, 0xCA, 0xBF, 0xC5, 0xFE, 0xD5,
+	0x69, 0xC6, 0x1C, 0x4F, 0x88, 0xE2, 0x6A, 0xD4, 0xE5, 0xCB, 0x65, 0x1F, 0x87, 0xBF, 0x41, 0x70,
+	0x9F, 0x0A, 0xE1, 0xF8, 0x53, 0x0B, 0x52, 0x30, 0x95, 0xE5, 0x37, 0xEF, 0x7C, 0xBB, 0x7D, 0xE4,
+	0xDE, 0x3A, 0xD6, 0xA1, 0x8E, 0xEA, 0x38, 0xA1, 0x99, 0x99, 0x9A, 0x5F, 0xF8, 0x0D, 0x7D, 0x71,
+	0xF0, 0x82, 0x6F, 0x37, 0xE1, 0xD6, 0x8E, 0x73, 0xFF, 0x00, 0x2E, 0xBF, 0x35, 0x7E, 0x74, 0xF8,
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+	0xAF, 0xA4, 0x4F, 0xE2, 0xA0, 0x0E, 0x1F, 0x5A, 0xFD, 0xA8, 0x2D, 0xED, 0x63, 0x69, 0xAF, 0x2F,
+	0xFE, 0xCF, 0x1A, 0xFD, 0xE9, 0xA4, 0x6F, 0x95, 0x6B, 0x89, 0x9B, 0xC5, 0xDE, 0x27, 0xF8, 0xE1,
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+	0x51, 0xF6, 0x7F, 0xF9, 0x69, 0xF3, 0x7F, 0x7A, 0xBE, 0xAC, 0xF0, 0xAF, 0xFC, 0x11, 0x93, 0xC3,
+	0x76, 0x36, 0xAF, 0x65, 0xE2, 0xAF, 0x1C, 0xCD, 0xAB, 0x5B, 0xC8, 0xBB, 0x65, 0x86, 0x6F, 0xE2,
+	0xAF, 0x6B, 0xF8, 0x63, 0xFF, 0x00, 0x04, 0xFF, 0x00, 0xF8, 0x5D, 0xF0, 0xE7, 0x43, 0xB6, 0xD1,
+	0x2D, 0xAC, 0xE3, 0xF2, 0xAC, 0xFF, 0x00, 0xE3, 0xCE, 0x1D, 0xBF, 0xEA, 0xFF, 0x00, 0xE0, 0x54,
+	0x01, 0xD1, 0xFE, 0xCA, 0xFE, 0x05, 0xF8, 0x3B, 0xF0, 0x63, 0xE1, 0xED, 0x97, 0xC3, 0xEF, 0x84,
+	0xF6, 0xED, 0xF6, 0x7B, 0x78, 0xB3, 0x79, 0x7B, 0x75, 0xF3, 0x4F, 0x71, 0x27, 0xF1, 0x6E, 0x6F,
+	0xE2, 0xAF, 0x5C, 0xB6, 0xB8, 0x8A, 0xE1, 0x77, 0xC3, 0xF7, 0x6B, 0x9F, 0xF0, 0xDF, 0xC3, 0xAD,
+	0x13, 0xC3, 0xB1, 0x47, 0x0D, 0xB4, 0x2A, 0xAF, 0x1F, 0xF1, 0x2F, 0xF1, 0x57, 0x45, 0x6F, 0x14,
+	0x71, 0xAF, 0xC9, 0x16, 0xCF, 0xF6, 0x68, 0x02, 0x4A, 0x28, 0xA4, 0x7F, 0xBB, 0x40, 0x0B, 0x54,
+	0xF5, 0x2D, 0x5A, 0xD3, 0x4F, 0xB7, 0x79, 0xE6, 0x93, 0x1B, 0x57, 0xEF, 0x55, 0xB6, 0x38, 0x5E,
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+	0xC6, 0x3F, 0xB3, 0x2F, 0x83, 0xFC, 0x69, 0x14, 0x90, 0xEA, 0xB0, 0xA9, 0xF3, 0x17, 0x1E, 0x63,
+	0x7C, 0xD5, 0xE0, 0xFE, 0x30, 0xFF, 0x00, 0x82, 0x4B, 0x7C, 0x34, 0xD6, 0xAF, 0x9B, 0x52, 0xD1,
+	0x26, 0xFB, 0x2D, 0xCC, 0x9F, 0x76, 0x65, 0xFE, 0x1A, 0x00, 0xF9, 0xAE, 0x1F, 0xDA, 0x51, 0x24,
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+	0xAB, 0xD1, 0xFC, 0x4F, 0xFF, 0x00, 0x04, 0x4F, 0xD6, 0x2F, 0x5D, 0xE6, 0xD1, 0x3E, 0x2A, 0xDC,
+	0x5B, 0xEE, 0xFE, 0x15, 0xAE, 0x1F, 0x50, 0xFF, 0x00, 0x82, 0x10, 0x7C, 0x5D, 0xB9, 0x69, 0x24,
+	0xB4, 0xFD, 0xA2, 0x35, 0x08, 0x59, 0xBE, 0xEA, 0xAB, 0x50, 0x05, 0x18, 0xFF, 0x00, 0x68, 0x2B,
+	0xF6, 0x6D, 0xE9, 0xBA, 0xA4, 0x97, 0xF6, 0x82, 0xD4, 0x91, 0x7E, 0xE3, 0x56, 0x4D, 0xE7, 0xFC,
+	0x10, 0x43, 0xF6, 0x90, 0x7F, 0xF8, 0xF6, 0xFD, 0xA5, 0xEF, 0x97, 0xFE, 0x07, 0x54, 0x9B, 0xFE,
+	0x08, 0x23, 0xFB, 0x54, 0x6D, 0x6D, 0x9F, 0xB4, 0xD5, 0xF7, 0xFD, 0xFC, 0xA0, 0x0E, 0x91, 0x7F,
+	0x68, 0x0D, 0x55, 0x97, 0xF8, 0xA8, 0x93, 0xF6, 0x82, 0xD4, 0xA3, 0x5C, 0x6F, 0x6A, 0xE7, 0x13,
+	0xFE, 0x08, 0x21, 0xFB, 0x54, 0x67, 0xE7, 0xFD, 0xA7, 0x2F, 0xBF, 0xEF, 0xED, 0x5E, 0xB2, 0xFF,
+	0x00, 0x82, 0x07, 0xFE, 0xD1, 0xA3, 0xFE, 0x3F, 0x3F, 0x69, 0x9B, 0xE6, 0xFF, 0x00, 0x81, 0x50,
+	0x05, 0xF9, 0xFF, 0x00, 0x68, 0xAB, 0x9B, 0x55, 0xF3, 0x26, 0x46, 0x7F, 0xF7, 0x6A, 0x2F, 0xF8,
+	0x69, 0x47, 0x58, 0xFC, 0xE7, 0x2D, 0x1A, 0xFF, 0x00, 0xB5, 0x5A, 0x9A, 0x5F, 0xFC, 0x10, 0x97,
+	0xE3, 0x35, 0xAC, 0x4A, 0x97, 0x9F, 0xB4, 0x3D, 0xF3, 0xFF, 0x00, 0xC0, 0xAB, 0xB2, 0xD0, 0x7F,
+	0xE0, 0x88, 0x7A, 0xF5, 0xAC, 0x51, 0xBE, 0xBD, 0xF1, 0xBE, 0xFA, 0xE7, 0x6F, 0xDE, 0x56, 0xA0,
+	0x0F, 0x1A, 0xF1, 0x47, 0xED, 0x39, 0x0D, 0xD7, 0xFC, 0x4B, 0x6D, 0xB5, 0x55, 0xFB, 0x55, 0xC2,
+	0xFE, 0xEA, 0xD5, 0x5B, 0xE6, 0x93, 0xFD, 0xDA, 0xEC, 0x7F, 0x61, 0xDF, 0x85, 0x3E, 0x0D, 0xF8,
+	0xE1, 0xF1, 0x2E, 0x1F, 0x8A, 0x9F, 0x1C, 0x25, 0xBC, 0x5D, 0x1B, 0x45, 0xBB, 0xCE, 0x93, 0xA3,
+	0xCA, 0xED, 0xBA, 0x6B, 0xA5, 0x6F, 0xF9, 0x6A, 0xBF, 0xC5, 0x1D, 0x7B, 0xF7, 0x82, 0xFF, 0x00,
+	0xE0, 0x90, 0xBF, 0x0A, 0xFC, 0x33, 0xAA, 0x58, 0xEB, 0xDA, 0xC5, 0xFF, 0x00, 0xDB, 0xAE, 0xB4,
+	0xD6, 0xDD, 0x6F, 0x75, 0x27, 0xDE, 0xAF, 0x76, 0xF0, 0x7F, 0xEC, 0xB5, 0xE0, 0x6F, 0x08, 0xCC,
+	0xB7, 0x76, 0x1A, 0x74, 0x7B, 0xDB, 0xEF, 0x6D, 0xFF, 0x00, 0xD0, 0xA8, 0x03, 0xBF, 0xF0, 0xFE,
+	0xAD, 0xA5, 0xCF, 0x61, 0x18, 0xB0, 0x8E, 0x38, 0x61, 0x54, 0x55, 0x8E, 0x14, 0x4D, 0xAA, 0x8B,
+	0xFD, 0xD1, 0x5A, 0xCA, 0xDB, 0xBB, 0x55, 0x0D, 0x37, 0xC3, 0xB6, 0x1A, 0x5D, 0xBA, 0xDB, 0xDB,
+	0x26, 0xD5, 0x5A, 0xBC, 0x36, 0xAF, 0xCA, 0x28, 0x01, 0xD4, 0x51, 0x45, 0x00, 0x36, 0x46, 0x48,
+	0xD3, 0x7B, 0x9D, 0xAB, 0x5C, 0x7F, 0xC5, 0x38, 0xBC, 0x1F, 0xE2, 0x5F, 0x0D, 0x5D, 0x78, 0x4F,
+	0xC4, 0xEB, 0x0C, 0xD6, 0x77, 0xD6, 0xEC, 0x8D, 0x1C, 0x9F, 0x34, 0x7B, 0xBF, 0xBC, 0xD5, 0xD7,
+	0xCD, 0x1A, 0xCC, 0x9B, 0x24, 0x3F, 0x2F, 0xF1, 0x56, 0x0F, 0x88, 0xFC, 0x09, 0xA5, 0x78, 0x82,
+	0x3F, 0x26, 0xE5, 0x36, 0xAF, 0x45, 0xDB, 0x40, 0x1F, 0x93, 0x9F, 0x13, 0x35, 0x0B, 0xCF, 0x80,
+	0x3F, 0x18, 0xB5, 0x2F, 0x04, 0xD9, 0xEA, 0x4D, 0xFD, 0x9B, 0x0C, 0xAC, 0xF6, 0xFA, 0x83, 0x3F,
+	0xEE, 0x99, 0x5B, 0xF8, 0x56, 0xB6, 0x34, 0x7F, 0xDA, 0x71, 0x24, 0x85, 0x56, 0x1B, 0xF5, 0x9A,
+	0x35, 0xFB, 0xD2, 0x2B, 0x57, 0xDD, 0xBF, 0x14, 0x3F, 0x60, 0x9F, 0x85, 0xDF, 0x13, 0x2D, 0x9A,
+	0xCF, 0x58, 0xD2, 0xE3, 0x92, 0x3F, 0xE1, 0x56, 0xFE, 0x1A, 0xF1, 0x6F, 0x11, 0x7F, 0xC1, 0x1C,
+	0x7C, 0x2B, 0x71, 0x0C, 0x96, 0xFE, 0x1B, 0xF1, 0x54, 0x96, 0x09, 0x27, 0xDD, 0x8E, 0x3F, 0xE1,
+	0xA0, 0x0F, 0x0D, 0xFF, 0x00, 0x86, 0x92, 0xFE, 0x38, 0x64, 0x69, 0x13, 0xEE, 0xFC, 0xB5, 0x22,
+	0xFE, 0xD1, 0x17, 0x2C, 0xDF, 0x26, 0xEA, 0xEA, 0x7C, 0x45, 0xFF, 0x00, 0x04, 0x38, 0xF1, 0xE5,
+	0xE4, 0x7E, 0x46, 0x83, 0xF1, 0xBE, 0xF2, 0xD5, 0x59, 0xBE, 0xF2, 0xB5, 0x72, 0xDA, 0xBF, 0xFC,
+	0x10, 0x57, 0xE3, 0x94, 0x9F, 0xF1, 0xE1, 0xFB, 0x48, 0x5F, 0x0F, 0xF8, 0x15, 0x00, 0x49, 0x17,
+	0xC7, 0xEB, 0xF1, 0xFD, 0xEA, 0x6B, 0x7E, 0xD0, 0x17, 0x93, 0x7C, 0x8E, 0x8D, 0xB7, 0xFB, 0xB5,
+	0x8B, 0x27, 0xFC, 0x10, 0x47, 0xF6, 0x9B, 0xFF, 0x00, 0x96, 0x3F, 0xB4, 0xCD, 0xF6, 0xDF, 0xFA,
+	0xEB, 0x55, 0xDB, 0xFE, 0x08, 0x23, 0xFB, 0x54, 0x30, 0xF9, 0x3F, 0x69, 0x6B, 0xE5, 0xFF, 0x00,
+	0xB6, 0xB4, 0x01, 0xD1, 0x7F, 0xC2, 0xFA, 0xBC, 0x8F, 0xFE, 0x58, 0xF3, 0xFD, 0xED, 0xB4, 0x37,
+	0xED, 0x0D, 0x7E, 0xAB, 0xB3, 0xC9, 0x93, 0xE5, 0xAC, 0x3B, 0x5F, 0xF8, 0x20, 0x7F, 0xED, 0x45,
+	0xBB, 0xFD, 0x23, 0xF6, 0x9C, 0xBE, 0xFF, 0x00, 0xBF, 0xB5, 0xA7, 0x61, 0xFF, 0x00, 0x04, 0x16,
+	0xFD, 0xA1, 0x23, 0x65, 0xFB, 0x4F, 0xED, 0x39, 0xA8, 0x37, 0xF7, 0x97, 0x75, 0x00, 0x3D, 0xBF,
+	0x68, 0xFB, 0x98, 0xD5, 0x51, 0xFC, 0xC5, 0xDB, 0xFC, 0x55, 0x5E, 0xFF, 0x00, 0xF6, 0x9C, 0x4B,
+	0x58, 0xF7, 0xCD, 0x24, 0x8B, 0xBB, 0xE5, 0x56, 0xFF, 0x00, 0x6A, 0xBA, 0xAD, 0x07, 0xFE, 0x08,
+	0x5F, 0xF1, 0x3A, 0xD6, 0x45, 0xFE, 0xD5, 0xF8, 0xFF, 0x00, 0x7D, 0x32, 0xFF, 0x00, 0xB5, 0x5D,
+	0xE7, 0x84, 0xFF, 0x00, 0xE0, 0x8B, 0xD1, 0xE9, 0x17, 0x0B, 0x3E, 0xBD, 0xF1, 0x46, 0xE3, 0x50,
+	0x4F, 0xE2, 0x86, 0x4F, 0xE1, 0xA0, 0x0F, 0x97, 0x7C, 0x69, 0xF1, 0xE3, 0x55, 0xF1, 0x83, 0x25,
+	0x9F, 0x86, 0x2E, 0x26, 0xBF, 0x69, 0xA6, 0xF2, 0x3C, 0xEB, 0x3F, 0x9A, 0x38, 0x64, 0x6F, 0xF9,
+	0xE9, 0x5F, 0x7B, 0x7E, 0xC0, 0x3F, 0x06, 0xFE, 0x13, 0x7C, 0x0C, 0xF0, 0x24, 0x7A, 0xC5, 0xB4,
+	0xF2, 0x6A, 0x3E, 0x2A, 0xD7, 0x36, 0xCF, 0xAF, 0x5F, 0x5C, 0x36, 0xEF, 0x21, 0xBF, 0xBB, 0x17,
+	0xF7, 0x56, 0xAC, 0xFC, 0x28, 0xFF, 0x00, 0x82, 0x67, 0xFC, 0x25, 0xF8, 0x5B, 0x69, 0x35, 0x9E,
+	0x8F, 0x67, 0x1E, 0xCB, 0x89, 0xBC, 0xDB, 0x8D, 0xDF, 0x37, 0x98, 0xDF, 0xDE, 0xAF, 0x6B, 0xF0,
+	0x8F, 0xC1, 0x9F, 0x0A, 0xF8, 0x46, 0xDD, 0x2D, 0xB4, 0xDB, 0x65, 0x45, 0x8F, 0xEE, 0xED, 0xFE,
+	0x2A, 0x00, 0xEB, 0x2D, 0x6F, 0x2D, 0xEE, 0x95, 0x4C, 0x47, 0xEF, 0x7F, 0x7A, 0xA7, 0xFE, 0x3F,
+	0xC2, 0xA2, 0x86, 0xD6, 0x18, 0x14, 0x08, 0x57, 0xEE, 0xD4, 0x8A, 0xBF, 0xC4, 0x68, 0x01, 0xD4,
+	0x51, 0x4D, 0x6C, 0xAA, 0xFC, 0xB4, 0x01, 0x15, 0xC5, 0xD5, 0xBD, 0xBF, 0xEF, 0x66, 0x7D, 0xAA,
+	0xB5, 0xF2, 0x97, 0xFC, 0x14, 0x4B, 0xE1, 0xEF, 0x84, 0xBE, 0x21, 0xFC, 0x3C, 0x93, 0xC7, 0x9A,
+	0x65, 0xCC, 0x2B, 0xAD, 0x68, 0xEB, 0xBD, 0x66, 0x8F, 0xFD, 0x6C, 0x8A, 0xBF, 0xF2, 0xCE, 0xBE,
+	0xAC, 0xB8, 0xB2, 0x8E, 0x75, 0xD8, 0xEB, 0xB9, 0x7F, 0x8A, 0xB8, 0x9F, 0x19, 0x7C, 0x07, 0xF0,
+	0x97, 0x8B, 0xA3, 0x78, 0x6F, 0x2D, 0x17, 0x63, 0x7C, 0xCC, 0xB4, 0x01, 0xF9, 0x55, 0xE0, 0x7F,
+	0xDA, 0x1A, 0xF3, 0x47, 0x8D, 0x2C, 0xF5, 0x5B, 0xFF, 0x00, 0xB2, 0x49, 0xFF, 0x00, 0x3C, 0x6E,
+	0x3E, 0x56, 0xAE, 0xD6, 0xDB, 0xF6, 0x96, 0x79, 0x17, 0xE7, 0xBA, 0xF9, 0x3F, 0xF4, 0x2A, 0xFA,
+	0xB3, 0xE2, 0x47, 0xFC, 0x12, 0xD3, 0xE1, 0x2F, 0x8F, 0x6F, 0x5B, 0x54, 0x7B, 0x74, 0x8E, 0x66,
+	0xFF, 0x00, 0x55, 0x22, 0xFC, 0xBB, 0x6B, 0xCB, 0x7C, 0x55, 0xFF, 0x00, 0x04, 0x5E, 0xB8, 0xD5,
+	0x19, 0xA4, 0xD1, 0xFE, 0x26, 0x5C, 0x5B, 0x37, 0xFC, 0xB2, 0x55, 0xFE, 0x1A, 0x00, 0xF2, 0xB5,
+	0xFD, 0xA3, 0xA6, 0xDD, 0xF3, 0xA4, 0x8B, 0x4E, 0x4F, 0xDA, 0x12, 0xF2, 0x46, 0xFD, 0xCE, 0xEA,
+	0xD8, 0xD6, 0x3F, 0xE0, 0x85, 0x1F, 0x15, 0xEE, 0x77, 0x7D, 0x8F, 0xF6, 0x87, 0xBE, 0x5A, 0xE6,
+	0xAF, 0xBF, 0xE0, 0x82, 0x3F, 0xB4, 0x33, 0x3E, 0xFB, 0x3F, 0xDA, 0x52, 0xF9, 0x7F, 0xE0, 0x54,
+	0x01, 0xA3, 0xFF, 0x00, 0x0B, 0xFB, 0x52, 0x5D, 0xDF, 0x7A, 0x97, 0xFE, 0x1A, 0x0B, 0x51, 0x6E,
+	0xCD, 0x5C, 0xF4, 0xDF, 0xF0, 0x41, 0x2F, 0xDA, 0x91, 0x9B, 0xE4, 0xFD, 0xA6, 0xAF, 0xB6, 0xFF,
+	0x00, 0xBF, 0x51, 0xAF, 0xFC, 0x10, 0x4B, 0xF6, 0xA7, 0x5F, 0xF9, 0xB9, 0xAB, 0xEF, 0xFB, 0xEA,
+	0x80, 0x3A, 0x46, 0xFD, 0xA0, 0x35, 0x2D, 0xBF, 0xC4, 0xB5, 0x14, 0x9F, 0xB4, 0x55, 0xE4, 0x68,
+	0xCE, 0xE8, 0xCC, 0xD5, 0x99, 0x6B, 0xFF, 0x00, 0x04, 0x0C, 0xFD, 0xA4, 0xF7, 0x6F, 0xB9, 0xFD,
+	0xA7, 0x2F, 0xB7, 0x7F, 0xBD, 0x5B, 0x5A, 0x5F, 0xFC, 0x10, 0x7F, 0xE3, 0x65, 0xBA, 0xE6, 0xF3,
+	0xF6, 0x8D, 0xBE, 0x7F, 0xF8, 0x15, 0x00, 0x55, 0x8F, 0xF6, 0x90, 0xB9, 0xFE, 0x34, 0x91, 0x56,
+	0xB2, 0x75, 0xEF, 0xDA, 0xAA, 0xC2, 0xC6, 0xDE, 0x43, 0x7F, 0xAA, 0x2D, 0xB2, 0x33, 0x6C, 0x59,
+	0x24, 0x6F, 0x97, 0x77, 0xF7, 0x6B, 0xD3, 0x3C, 0x37, 0xFF, 0x00, 0x04, 0x39, 0xF1, 0xA5, 0xBC,
+	0x6D, 0xFD, 0xB7, 0xF1, 0xFA, 0xF9, 0xAB, 0xD1, 0x3C, 0x33, 0xFF, 0x00, 0x04, 0x6E, 0xF8, 0x79,
+	0x15, 0x8C, 0x76, 0x3E, 0x39, 0xD7, 0xE4, 0xD5, 0x61, 0x8D, 0x95, 0xDD, 0x66, 0xFE, 0x26, 0x5F,
+	0xBA, 0xD4, 0x01, 0xF2, 0xEF, 0xC1, 0xCF, 0x08, 0x37, 0xED, 0x35, 0xF1, 0x6E, 0xDF, 0xC1, 0xFE,
+	0x3D, 0xBE, 0xBE, 0xD3, 0x7C, 0x37, 0x6F, 0x22, 0xCB, 0xAF, 0x4D, 0x1B, 0xB2, 0xBC, 0xD1, 0xFD,
+	0xE5, 0xF2, 0x9A, 0xBF, 0x54, 0x7E, 0x18, 0x9F, 0x02, 0xF8, 0x7F, 0xC3, 0x36, 0x7E, 0x1B, 0xF0,
+	0x25, 0x9C, 0x76, 0xDA, 0x6D, 0x8C, 0x0B, 0x0D, 0xAD, 0xBC, 0x69, 0xB7, 0x2A, 0xAA, 0xBF, 0x33,
+	0x7F, 0xB5, 0x5C, 0x37, 0x82, 0xFF, 0x00, 0x63, 0x3F, 0x87, 0x9E, 0x11, 0x8E, 0x17, 0x86, 0xCE,
+	0x36, 0x92, 0x15, 0x54, 0x59, 0x36, 0xFF, 0x00, 0x0A, 0xFD, 0xDA, 0xF5, 0x0D, 0x17, 0xC2, 0x3A,
+	0x6F, 0x87, 0xE3, 0x57, 0xB3, 0xB7, 0x5D, 0xFB, 0x76, 0xD0, 0x06, 0xC4, 0x2C, 0x8C, 0xBF, 0x23,
+	0xEE, 0xA7, 0x54, 0x70, 0x47, 0x1A, 0x67, 0x60, 0xC1, 0xFE, 0x2A, 0x92, 0x80, 0x0A, 0x6B, 0x2E,
+	0x39, 0x14, 0xAC, 0xBB, 0xA8, 0x7F, 0xBB, 0x40, 0x19, 0x1E, 0x22, 0xD5, 0xB4, 0xAB, 0x3B, 0x66,
+	0x8B, 0x53, 0xFB, 0x92, 0xAE, 0xC9, 0x97, 0xF8, 0x4A, 0xD7, 0xE6, 0x4F, 0xED, 0xA9, 0xE1, 0xBB,
+	0x3F, 0x80, 0xFF, 0x00, 0x1A, 0x1B, 0x5D, 0xF0, 0x1E, 0xE6, 0xD3, 0x75, 0x66, 0x69, 0x7C, 0x9B,
+	0x5F, 0xF5, 0x56, 0xFF, 0x00, 0xEF, 0x57, 0xE9, 0xC6, 0xB9, 0xE1, 0x9B, 0x3D, 0x6A, 0xDD, 0x92,
+	0xE1, 0xBE, 0xF5, 0x79, 0x77, 0xC4, 0x4F, 0xD8, 0xE7, 0xC0, 0x7E, 0x3F, 0xB3, 0x92, 0xD6, 0xFE,
+	0x15, 0x65, 0x9B, 0xEF, 0x79, 0x94, 0x01, 0xF9, 0xE1, 0xE1, 0x9F, 0xDA, 0x69, 0x3E, 0xCB, 0x1A,
+	0x43, 0xAA, 0xC7, 0x33, 0x2F, 0xFA, 0xD8, 0xD5, 0xBE, 0x68, 0xFF, 0x00, 0xDE, 0xAD, 0xCF, 0xF8,
+	0x69, 0x27, 0x93, 0xFD, 0x4B, 0xEF, 0xFF, 0x00, 0x76, 0xBE, 0x81, 0xF1, 0x57, 0xFC, 0x12, 0x07,
+	0xC0, 0x1A, 0x85, 0xD4, 0x8F, 0xE1, 0x5D, 0x55, 0xB4, 0xD6, 0x93, 0xFE, 0x3E, 0x1A, 0x3F, 0xF9,
+	0x69, 0x5E, 0x71, 0xE2, 0x5F, 0xF8, 0x22, 0x07, 0x8B, 0x2E, 0x43, 0x1D, 0x03, 0xE3, 0x4D, 0xD4,
+	0x1B, 0xBF, 0x87, 0xFB, 0xB4, 0x01, 0xC4, 0x2F, 0xED, 0x11, 0x33, 0x7F, 0x7B, 0x77, 0xF7, 0x69,
+	0xE3, 0xF6, 0x80, 0xBF, 0xEB, 0xB2, 0x4A, 0x93, 0x56, 0xFF, 0x00, 0x82, 0x0D, 0xFC, 0x66, 0xB8,
+	0x56, 0x7B, 0x0F, 0xDA, 0x2A, 0xFA, 0x37, 0xFF, 0x00, 0x7A, 0xB1, 0x26, 0xFF, 0x00, 0x82, 0x0A,
+	0x7E, 0xD3, 0x7B, 0x98, 0xC3, 0xFB, 0x4D, 0x5F, 0x7F, 0xDF, 0x54, 0x9C, 0x53, 0xDC, 0x0D, 0xA6,
+	0xFD, 0xA0, 0xEF, 0xD9, 0x7E, 0x44, 0x6A, 0x23, 0xF8, 0xF9, 0xAA, 0xC9, 0xB6, 0x68, 0xF7, 0x2E,
+	0xDF, 0xFC, 0x7A, 0xB9, 0xA9, 0x7F, 0xE0, 0x82, 0x1F, 0xB5, 0x3E, 0xEF, 0xDD, 0xFE, 0xD3, 0x57,
+	0xDF, 0xF7, 0xDD, 0x3E, 0xDB, 0xFE, 0x08, 0x1B, 0xFB, 0x52, 0x7D, 0xF9, 0x7F, 0x6A, 0x2D, 0x40,
+	0x7F, 0xB3, 0xBA, 0x9E, 0xEA, 0xC3, 0xE6, 0x67, 0x43, 0x27, 0xED, 0x09, 0x7E, 0xAC, 0xC2, 0x44,
+	0x6F, 0x9A, 0xAB, 0xDC, 0x7E, 0xD0, 0xD7, 0x30, 0xAA, 0xA3, 0xDB, 0x36, 0xE6, 0xFB, 0x8D, 0xFC,
+	0x55, 0x5F, 0x4F, 0xFF, 0x00, 0x82, 0x08, 0x7E, 0xD0, 0x91, 0xC8, 0xBF, 0x6C, 0xFD, 0xA7, 0x35,
+	0x06, 0xFF, 0x00, 0x81, 0x57, 0x45, 0xA5, 0xFF, 0x00, 0xC1, 0x09, 0xBE, 0x2E, 0xDB, 0x48, 0x8F,
+	0x79, 0xFB, 0x45, 0x5F, 0x49, 0xB7, 0xFB, 0xCD, 0x44, 0x7D, 0xD5, 0x64, 0x2B, 0x7B, 0xD7, 0x30,
+	0x6E, 0x3F, 0x68, 0xC8, 0x63, 0x85, 0x5D, 0xE1, 0xDA, 0xCB, 0xFE, 0xC7, 0xCD, 0x5C, 0x87, 0x8C,
+	0xBF, 0x69, 0x17, 0xD5, 0xED, 0x6E, 0x2D, 0xB4, 0xAB, 0xC9, 0x2F, 0xE4, 0x85, 0x77, 0x5D, 0x58,
+	0xD9, 0xB6, 0xE9, 0x56, 0x3F, 0xEF, 0x57, 0xD0, 0x9E, 0x1A, 0xFF, 0x00, 0x82, 0x27, 0xDE, 0x58,
+	0x5C, 0x47, 0x3E, 0xB7, 0xF1, 0x9E, 0xF2, 0xE1, 0x97, 0xEF, 0x46, 0xDF, 0xC5, 0x5E, 0xA9, 0xF0,
+	0xC7, 0xFE, 0x09, 0x61, 0xF0, 0xAB, 0xE1, 0xE7, 0x88, 0x1B, 0xC4, 0x70, 0xAA, 0xFD, 0xAE, 0x68,
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+	0x89, 0xF0, 0x4F, 0xEC, 0xF3, 0xE0, 0xCF, 0x03, 0xAF, 0x93, 0xA3, 0xD8, 0x2A, 0xC3, 0xFC, 0x2B,
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+	0xFE, 0xFA, 0xA3, 0x69, 0xFE, 0xF5, 0x3A, 0x8A, 0x00, 0x68, 0x40, 0x1F, 0x75, 0x26, 0xCD, 0xD9,
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+	0x5B, 0x1F, 0xC3, 0x4E, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x11, 0xFE, 0xED, 0x18, 0xF9, 0x7E,
+	0x7A, 0x5A, 0x28, 0x01, 0xAC, 0x8A, 0xDD, 0x68, 0xF2, 0xE3, 0xF3, 0x37, 0xFF, 0x00, 0x15, 0x3A,
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+	0x67, 0xFB, 0x4D, 0xF9, 0xD1, 0xB3, 0xFD, 0xA6, 0xFC, 0xE9, 0xD4, 0x50, 0x02, 0x6D, 0xFF, 0x00,
+	0x68, 0xD3, 0x56, 0x3F, 0xF6, 0xDA, 0x9F, 0x45, 0x00, 0x31, 0xA3, 0x0C, 0xDB, 0xDE, 0x9D, 0xB1,
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+	0x14, 0x00, 0x9B, 0x17, 0xD2, 0x96, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x01, 0x18, 0x6E, 0x18,
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+	0x6B, 0xF3, 0xF3, 0x53, 0xA8, 0xA0, 0x06, 0x79, 0x65, 0x97, 0xEF, 0xB5, 0x3B, 0x6F, 0xFB, 0x46,
+	0x96, 0x8A, 0x00, 0x6E, 0xCF, 0xF6, 0x9B, 0xF3, 0xA4, 0xD8, 0xDB, 0xBE, 0xFB, 0x53, 0xE8, 0xA0,
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+	0x50, 0x02, 0x6D, 0xFF, 0x00, 0x68, 0xD2, 0x6C, 0xF9, 0xBE, 0xFB, 0x53, 0xA8, 0xA0, 0x06, 0xEC,
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+	0x02, 0x6D, 0xFF, 0x00, 0x68, 0xD2, 0x18, 0xF7, 0x7F, 0x1B, 0x53, 0xA8, 0xA0, 0x06, 0xB2, 0x06,
+	0x5D, 0x9D, 0xA8, 0x54, 0xDA, 0x9B, 0x33, 0x4E, 0xA2, 0x80, 0x1A, 0xD1, 0xFC, 0xDB, 0xC5, 0x2A,
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+	0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51,
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+	0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x1F, 0xFF, 0xD9,
+	0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60,
+	0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x22, 0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D,
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+	0x07, 0x09, 0x08, 0x06, 0x07, 0x09, 0x07, 0x06, 0x06, 0x08, 0x0B, 0x08, 0x09, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x06, 0x08, 0x0B, 0x0C, 0x0B, 0x0A, 0x0C, 0x09, 0x0A, 0x0A, 0x0A, 0xFF, 0xDB, 0x00,
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+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
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+	0x0A, 0x0A, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x02, 0x58, 0x04, 0x00, 0x03, 0x01, 0x22, 0x00, 0x02,
+	0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00, 0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+	0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03,
+	0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04,
+	0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81,
+	0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82,
+	0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36,
+	0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
+	0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76,
+	0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95,
+	0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3,
+	0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA,
+	0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
+	0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00,
+	0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4,
+	0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00,
+	0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51,
+	0x07, 0x61, 0x71, 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23,
+	0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18,
+	0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45,
+	0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65,
+	0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84,
+	0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2,
+	0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9,
+	0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7,
+	0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5,
+	0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11,
+	0x00, 0x3F, 0x00, 0xFD, 0xFC, 0xA2, 0x8A, 0x0F, 0x4A, 0x00, 0xC1, 0xF1, 0x87, 0xC5, 0x2F, 0x86,
+	0x5F, 0x0F, 0x64, 0x82, 0x1F, 0x1F, 0x7C, 0x45, 0xD0, 0x74, 0x37, 0xBA, 0x56, 0x6B, 0x65, 0xD6,
+	0x35, 0x78, 0x6D, 0x8C, 0xC1, 0x7A, 0x95, 0x12, 0x30, 0xDD, 0x8C, 0x8C, 0xE3, 0xA6, 0x6B, 0x1F,
+	0xFE, 0x1A, 0x5F, 0xF6, 0x71, 0xFF, 0x00, 0xA3, 0x80, 0xF0, 0x4F, 0xFE, 0x15, 0x56, 0x7F, 0xFC,
+	0x72, 0xBE, 0x4A, 0xFF, 0x00, 0x82, 0xBE, 0xFF, 0x00, 0xC8, 0xC9, 0xE0, 0x7F, 0xFA, 0xF2, 0xBE,
+	0xFF, 0x00, 0xD1, 0x91, 0xD7, 0xC6, 0xD4, 0x01, 0xFA, 0xFD, 0xFF, 0x00, 0x0D, 0x2F, 0xFB, 0x38,
+	0xFF, 0x00, 0xD1, 0xC0, 0x78, 0x27, 0xFF, 0x00, 0x0A, 0xAB, 0x3F, 0xFE, 0x39, 0x47, 0xFC, 0x34,
+	0xBF, 0xEC, 0xE3, 0xFF, 0x00, 0x47, 0x01, 0xE0, 0x9F, 0xFC, 0x2A, 0xAC, 0xFF, 0x00, 0xF8, 0xE5,
+	0x7E, 0x40, 0xD1, 0x40, 0x1F, 0xAF, 0xDF, 0xF0, 0xD2, 0xFF, 0x00, 0xB3, 0x8F, 0xFD, 0x1C, 0x07,
+	0x82, 0x7F, 0xF0, 0xAA, 0xB3, 0xFF, 0x00, 0xE3, 0x95, 0xAD, 0xE1, 0x1F, 0x8B, 0x7F, 0x0A, 0xBC,
+	0x7F, 0x7B, 0x2E, 0x9B, 0xE0, 0x3F, 0x89, 0xBE, 0x1F, 0xD6, 0xEE, 0x21, 0x87, 0xCD, 0x9A, 0xDF,
+	0x48, 0xD6, 0xA0, 0xB9, 0x78, 0xE3, 0xC8, 0x1B, 0xD9, 0x63, 0x72, 0x42, 0xE4, 0x81, 0x93, 0xC6,
+	0x4D, 0x7E, 0x35, 0x8E, 0xB5, 0xF5, 0x77, 0xFC, 0x12, 0x4B, 0xFE, 0x4B, 0x3F, 0x89, 0xBF, 0xEC,
+	0x53, 0x5F, 0xFD, 0x29, 0x8A, 0x80, 0x3E, 0xF1, 0xF1, 0x6F, 0x8E, 0xBC, 0x13, 0xE0, 0x1D, 0x39,
+	0x35, 0x8F, 0x1D, 0xF8, 0xC7, 0x4A, 0xD1, 0x6C, 0xE4, 0x9C, 0x43, 0x1D, 0xD6, 0xAD, 0xA8, 0x45,
+	0x6D, 0x1B, 0x48, 0x41, 0x21, 0x03, 0x48, 0xC0, 0x16, 0x21, 0x58, 0xE3, 0x39, 0xC0, 0x3E, 0x95,
+	0xCF, 0x7F, 0xC3, 0x4B, 0xFE, 0xCE, 0x3F, 0xF4, 0x70, 0x1E, 0x09, 0xFF, 0x00, 0xC2, 0xAA, 0xCF,
+	0xFF, 0x00, 0x8E, 0x57, 0x87, 0x7F, 0xC1, 0x5A, 0x3F, 0xE4, 0xDD, 0x34, 0x8F, 0xFB, 0x1D, 0xAD,
+	0xFF, 0x00, 0xF4, 0x92, 0xEA, 0xBF, 0x3C, 0xA8, 0x03, 0xF5, 0xFB, 0xFE, 0x1A, 0x5F, 0xF6, 0x71,
+	0xFF, 0x00, 0xA3, 0x80, 0xF0, 0x4F, 0xFE, 0x15, 0x56, 0x7F, 0xFC, 0x72, 0x8F, 0xF8, 0x69, 0x7F,
+	0xD9, 0xC7, 0xFE, 0x8E, 0x03, 0xC1, 0x3F, 0xF8, 0x55, 0x59, 0xFF, 0x00, 0xF1, 0xCA, 0xFC, 0x81,
+	0xA2, 0x80, 0x3F, 0x5F, 0xBF, 0xE1, 0xA5, 0xFF, 0x00, 0x67, 0x1F, 0xFA, 0x38, 0x0F, 0x04, 0xFF,
+	0x00, 0xE1, 0x55, 0x67, 0xFF, 0x00, 0xC7, 0x2A, 0xFF, 0x00, 0x86, 0xBE, 0x36, 0xFC, 0x19, 0xF1,
+	0x9E, 0xAF, 0x1F, 0x87, 0xFC, 0x1F, 0xF1, 0x73, 0xC3, 0x1A, 0xB5, 0xFC, 0xAA, 0xCD, 0x15, 0x8E,
+	0x9B, 0xAF, 0xDB, 0xCF, 0x33, 0x85, 0x19, 0x62, 0x11, 0x1C, 0xB1, 0x00, 0x72, 0x78, 0xE0, 0x57,
+	0xE3, 0x95, 0x7B, 0xD7, 0xFC, 0x13, 0x63, 0xFE, 0x4E, 0xE7, 0x41, 0xFF, 0x00, 0xB0, 0x7E, 0xA1,
+	0xFF, 0x00, 0xA4, 0xEF, 0x40, 0x1F, 0xA5, 0x9E, 0x22, 0xF1, 0x47, 0x86, 0xBC, 0x21, 0xA3, 0x4D,
+	0xE2, 0x2F, 0x16, 0xF8, 0x86, 0xC7, 0x4B, 0xD3, 0xED, 0xF6, 0xFD, 0xA2, 0xFB, 0x51, 0xBB, 0x48,
+	0x21, 0x8B, 0x73, 0x05, 0x5D, 0xCE, 0xE4, 0x2A, 0xE5, 0x88, 0x03, 0x27, 0x92, 0x40, 0xEF, 0x5C,
+	0xBF, 0xFC, 0x34, 0xBF, 0xEC, 0xE3, 0xFF, 0x00, 0x47, 0x01, 0xE0, 0x9F, 0xFC, 0x2A, 0xAC, 0xFF,
+	0x00, 0xF8, 0xE5, 0x70, 0x7F, 0xF0, 0x51, 0x1F, 0xF9, 0x33, 0xAF, 0x18, 0x7F, 0xB9, 0xA7, 0xFF,
+	0x00, 0xE9, 0x7D, 0xBD, 0x7E, 0x5E, 0xD0, 0x07, 0xEB, 0xF7, 0xFC, 0x34, 0xBF, 0xEC, 0xE3, 0xFF,
+	0x00, 0x47, 0x01, 0xE0, 0x9F, 0xFC, 0x2A, 0xAC, 0xFF, 0x00, 0xF8, 0xE5, 0x1F, 0xF0, 0xD2, 0xFF,
+	0x00, 0xB3, 0x8F, 0xFD, 0x1C, 0x07, 0x82, 0x7F, 0xF0, 0xAA, 0xB3, 0xFF, 0x00, 0xE3, 0x95, 0xF9,
+	0x03, 0x45, 0x00, 0x7E, 0xBF, 0x7F, 0xC3, 0x4B, 0xFE, 0xCE, 0x3F, 0xF4, 0x70, 0x1E, 0x09, 0xFF,
+	0x00, 0xC2, 0xAA, 0xCF, 0xFF, 0x00, 0x8E, 0x55, 0x8D, 0x23, 0xF6, 0x80, 0xF8, 0x0F, 0xAF, 0xEA,
+	0x76, 0xFA, 0x26, 0x83, 0xF1, 0xB3, 0xC2, 0x37, 0xD7, 0x97, 0x53, 0x2C, 0x56, 0xB6, 0x76, 0x7E,
+	0x24, 0xB5, 0x92, 0x59, 0xA4, 0x3D, 0x15, 0x55, 0x64, 0x25, 0x98, 0xF6, 0x00, 0x66, 0xBF, 0x1E,
+	0x6B, 0xD1, 0x3F, 0x64, 0xAF, 0xF9, 0x39, 0xCF, 0x00, 0xFF, 0x00, 0xD8, 0xD5, 0x69, 0xFF, 0x00,
+	0xA1, 0x0A, 0x00, 0xFD, 0x6A, 0xBE, 0xD4, 0x2C, 0x34, 0xCB, 0x29, 0xB5, 0x2D, 0x4A, 0xFA, 0x1B,
+	0x7B, 0x7B, 0x78, 0x9A, 0x5B, 0x8B, 0x89, 0xE4, 0x08, 0x91, 0xA2, 0x8C, 0xB3, 0x33, 0x1E, 0x00,
+	0x00, 0x64, 0x93, 0xC0, 0xAE, 0x3F, 0xFE, 0x1A, 0x5F, 0xF6, 0x71, 0xFF, 0x00, 0xA3, 0x80, 0xF0,
+	0x4F, 0xFE, 0x15, 0x56, 0x7F, 0xFC, 0x72, 0xA7, 0xF8, 0xDB, 0xFF, 0x00, 0x24, 0x63, 0xC5, 0x9F,
+	0xF6, 0x2B, 0xEA, 0x1F, 0xFA, 0x21, 0xEB, 0xF1, 0xEA, 0x80, 0x3F, 0x5F, 0xBF, 0xE1, 0xA5, 0xFF,
+	0x00, 0x67, 0x1F, 0xFA, 0x38, 0x0F, 0x04, 0xFF, 0x00, 0xE1, 0x55, 0x67, 0xFF, 0x00, 0xC7, 0x28,
+	0xFF, 0x00, 0x86, 0x97, 0xFD, 0x9C, 0x7F, 0xE8, 0xE0, 0x3C, 0x13, 0xFF, 0x00, 0x85, 0x55, 0x9F,
+	0xFF, 0x00, 0x1C, 0xAF, 0xC8, 0x1A, 0x28, 0x03, 0xF5, 0xFB, 0xFE, 0x1A, 0x5F, 0xF6, 0x71, 0xFF,
+	0x00, 0xA3, 0x80, 0xF0, 0x4F, 0xFE, 0x15, 0x56, 0x7F, 0xFC, 0x72, 0xB4, 0xBC, 0x2B, 0xF1, 0x97,
+	0xE1, 0x07, 0x8E, 0xF5, 0x33, 0xA2, 0x78, 0x23, 0xE2, 0xAF, 0x86, 0xF5, 0x9B, 0xC1, 0x13, 0x4A,
+	0x6C, 0xF4, 0xAD, 0x72, 0xDE, 0xE2, 0x50, 0x80, 0x80, 0x5B, 0x6C, 0x6E, 0x4E, 0x01, 0x23, 0x27,
+	0x18, 0x19, 0x1E, 0xB5, 0xF8, 0xDF, 0x5F, 0x49, 0x7F, 0xC1, 0x2B, 0x7F, 0xE4, 0xE6, 0xA7, 0xFF,
+	0x00, 0xB1, 0x5A, 0xFB, 0xFF, 0x00, 0x46, 0xDB, 0xD0, 0x07, 0xE8, 0x97, 0x89, 0x7C, 0x59, 0xE1,
+	0x6F, 0x05, 0xE9, 0x12, 0x6B, 0xFE, 0x31, 0xF1, 0x2E, 0x9F, 0xA4, 0xD8, 0x44, 0xCA, 0xB2, 0xDF,
+	0x6A, 0x57, 0x89, 0x04, 0x28, 0x58, 0xE0, 0x02, 0xEE, 0x42, 0x8C, 0x9E, 0x07, 0x3C, 0x9A, 0xE6,
+	0x7F, 0xE1, 0xA5, 0xFF, 0x00, 0x67, 0x1F, 0xFA, 0x38, 0x0F, 0x04, 0xFF, 0x00, 0xE1, 0x55, 0x67,
+	0xFF, 0x00, 0xC7, 0x2B, 0xCD, 0xBF, 0xE0, 0xA5, 0x5F, 0xF2, 0x69, 0x5A, 0xF7, 0xFD, 0x7E, 0xD8,
+	0xFF, 0x00, 0xE9, 0x42, 0xD7, 0xE6, 0x55, 0x00, 0x7E, 0xBF, 0x7F, 0xC3, 0x4B, 0xFE, 0xCE, 0x3F,
+	0xF4, 0x70, 0x1E, 0x09, 0xFF, 0x00, 0xC2, 0xAA, 0xCF, 0xFF, 0x00, 0x8E, 0x51, 0xFF, 0x00, 0x0D,
+	0x2F, 0xFB, 0x38, 0xFF, 0x00, 0xD1, 0xC0, 0x78, 0x27, 0xFF, 0x00, 0x0A, 0xAB, 0x3F, 0xFE, 0x39,
+	0x5F, 0x90, 0x34, 0x50, 0x07, 0xEB, 0xF7, 0xFC, 0x34, 0xBF, 0xEC, 0xE3, 0xFF, 0x00, 0x47, 0x01,
+	0xE0, 0x9F, 0xFC, 0x2A, 0xAC, 0xFF, 0x00, 0xF8, 0xE5, 0x6E, 0x78, 0x3F, 0xE2, 0x4F, 0xC3, 0xBF,
+	0x88, 0x51, 0xCF, 0x37, 0x80, 0x7C, 0x7B, 0xA2, 0xEB, 0x89, 0x6A, 0xCA, 0xB7, 0x4D, 0xA3, 0xEA,
+	0x90, 0xDC, 0x88, 0x4B, 0x02, 0x40, 0x63, 0x1B, 0x1D, 0xA4, 0x80, 0x71, 0x9E, 0xB8, 0x3E, 0x95,
+	0xF8, 0xCB, 0x5F, 0x71, 0xFF, 0x00, 0xC1, 0x20, 0xFF, 0x00, 0xE4, 0x5B, 0xF1, 0xD7, 0xFD, 0x7F,
+	0xD8, 0xFF, 0x00, 0xE8, 0xAB, 0x8A, 0x00, 0xFA, 0xDF, 0xC5, 0xFF, 0x00, 0x12, 0x3E, 0x1D, 0xFC,
+	0x3C, 0x8A, 0xDE, 0x5F, 0x1F, 0xF8, 0xF7, 0x45, 0xD0, 0xD6, 0xE8, 0xB2, 0xDA, 0xB6, 0xB1, 0xAA,
+	0x43, 0x6A, 0x26, 0x2A, 0x06, 0x42, 0xF9, 0x8C, 0x37, 0x63, 0x23, 0x38, 0xE9, 0x9A, 0xC3, 0xFF,
+	0x00, 0x86, 0x97, 0xFD, 0x9C, 0x7F, 0xE8, 0xE0, 0x3C, 0x13, 0xFF, 0x00, 0x85, 0x55, 0x9F, 0xFF,
+	0x00, 0x1C, 0xAF, 0x99, 0x7F, 0xE0, 0xB0, 0x1F, 0xF2, 0x00, 0xF0, 0x2F, 0xFD, 0x7E, 0xDF, 0x7F,
+	0xE8, 0x11, 0xD7, 0xC3, 0x74, 0x01, 0xFA, 0xFD, 0xFF, 0x00, 0x0D, 0x2F, 0xFB, 0x38, 0xFF, 0x00,
+	0xD1, 0xC0, 0x78, 0x27, 0xFF, 0x00, 0x0A, 0xAB, 0x3F, 0xFE, 0x39, 0x47, 0xFC, 0x34, 0xBF, 0xEC,
+	0xE3, 0xFF, 0x00, 0x47, 0x01, 0xE0, 0x9F, 0xFC, 0x2A, 0xAC, 0xFF, 0x00, 0xF8, 0xE5, 0x7E, 0x40,
+	0xD1, 0x40, 0x1F, 0xAF, 0xDF, 0xF0, 0xD2, 0xFF, 0x00, 0xB3, 0x8F, 0xFD, 0x1C, 0x07, 0x82, 0x7F,
+	0xF0, 0xAA, 0xB3, 0xFF, 0x00, 0xE3, 0x95, 0xD2, 0xF8, 0x73, 0xC5, 0x9E, 0x16, 0xF1, 0xA6, 0x8C,
+	0xBE, 0x20, 0xF0, 0x77, 0x89, 0x74, 0xFD, 0x5A, 0xC2, 0x52, 0xCB, 0x1D, 0xF6, 0x99, 0x78, 0x93,
+	0xC2, 0xE5, 0x4E, 0x08, 0x0E, 0x84, 0xA9, 0x20, 0xF0, 0x79, 0xE0, 0xD7, 0xE2, 0xE5, 0x7E, 0x9A,
+	0x7F, 0xC1, 0x35, 0x7F, 0xE4, 0xD1, 0xF4, 0x3F, 0xFA, 0xFE, 0xBF, 0xFF, 0x00, 0xD2, 0x96, 0xA0,
+	0x0F, 0x5C, 0xF1, 0x5F, 0xC6, 0x5F, 0x84, 0x1E, 0x04, 0xD4, 0xFF, 0x00, 0xB1, 0x7C, 0x71, 0xF1,
+	0x57, 0xC3, 0x7A, 0x35, 0xE1, 0x88, 0x4A, 0x2D, 0x35, 0x6D, 0x72, 0xDE, 0xDE, 0x53, 0x19, 0x24,
+	0x06, 0xDB, 0x23, 0x83, 0x83, 0x83, 0xCE, 0x31, 0xC5, 0x66, 0xFF, 0x00, 0xC3, 0x4B, 0xFE, 0xCE,
+	0x3F, 0xF4, 0x70, 0x1E, 0x09, 0xFF, 0x00, 0xC2, 0xAA, 0xCF, 0xFF, 0x00, 0x8E, 0x57, 0xC2, 0x7F,
+	0xF0, 0x55, 0x7F, 0xF9, 0x39, 0x68, 0xBF, 0xEC, 0x55, 0xB5, 0xFF, 0x00, 0xD1, 0x93, 0x57, 0xCD,
+	0xA7, 0xAD, 0x00, 0x7E, 0xBF, 0x7F, 0xC3, 0x4B, 0xFE, 0xCE, 0x3F, 0xF4, 0x70, 0x1E, 0x09, 0xFF,
+	0x00, 0xC2, 0xAA, 0xCF, 0xFF, 0x00, 0x8E, 0x51, 0xFF, 0x00, 0x0D, 0x2F, 0xFB, 0x38, 0xFF, 0x00,
+	0xD1, 0xC0, 0x78, 0x27, 0xFF, 0x00, 0x0A, 0xAB, 0x3F, 0xFE, 0x39, 0x5F, 0x90, 0x34, 0x50, 0x07,
+	0xEB, 0xF7, 0xFC, 0x34, 0xC7, 0xEC, 0xE1, 0xFF, 0x00, 0x47, 0x01, 0xE0, 0x9F, 0xFC, 0x2A, 0xEC,
+	0xFF, 0x00, 0xF8, 0xE5, 0x76, 0x16, 0x3A, 0x85, 0x8E, 0xA7, 0x65, 0x0E, 0xA5, 0xA6, 0xDE, 0xC3,
+	0x71, 0x6F, 0x71, 0x12, 0xCB, 0x6F, 0x71, 0x04, 0x81, 0xD2, 0x54, 0x61, 0x95, 0x65, 0x61, 0xC1,
+	0x04, 0x10, 0x41, 0x1C, 0x11, 0x5F, 0x89, 0xEF, 0xFC, 0x5F, 0xEF, 0x7F, 0xEC, 0xAB, 0x5F, 0xB1,
+	0x5F, 0x03, 0xFF, 0x00, 0xE4, 0x8A, 0xF8, 0x3F, 0xFE, 0xC5, 0x7D, 0x3F, 0xFF, 0x00, 0x49, 0xA3,
+	0xA0, 0x03, 0x5A, 0xF8, 0xF7, 0xF0, 0x33, 0xC3, 0x5A, 0xB4, 0xFA, 0x0F, 0x88, 0xFE, 0x34, 0x78,
+	0x4F, 0x4F, 0xBE, 0xB5, 0x93, 0x65, 0xCD, 0x95, 0xEF, 0x88, 0xAD, 0x62, 0x9A, 0x26, 0xFE, 0xEB,
+	0x23, 0x38, 0x65, 0x3E, 0xC4, 0x55, 0x5F, 0xF8, 0x69, 0x8F, 0xD9, 0xC3, 0xFE, 0x8E, 0x03, 0xC1,
+	0x3F, 0xF8, 0x55, 0xD9, 0xFF, 0x00, 0xF1, 0xCA, 0xFC, 0xD3, 0xFD, 0xB4, 0xFF, 0x00, 0xE4, 0xEB,
+	0xBC, 0x6D, 0xFF, 0x00, 0x61, 0xC3, 0xFF, 0x00, 0xA0, 0xAD, 0x79, 0x62, 0x7D, 0xC1, 0xF4, 0xA0,
+	0x0F, 0xD7, 0xFF, 0x00, 0xF8, 0x69, 0x7F, 0xD9, 0xC7, 0xFE, 0x8E, 0x03, 0xC1, 0x3F, 0xF8, 0x55,
+	0x59, 0xFF, 0x00, 0xF1, 0xCA, 0x3F, 0xE1, 0xA5, 0xFF, 0x00, 0x67, 0x1F, 0xFA, 0x38, 0x0F, 0x04,
+	0xFF, 0x00, 0xE1, 0x55, 0x67, 0xFF, 0x00, 0xC7, 0x2B, 0xF2, 0x06, 0x8A, 0x00, 0xFD, 0x81, 0xB6,
+	0xFD, 0xA3, 0xBF, 0x67, 0xAB, 0xDB, 0x98, 0xEC, 0xEC, 0xFE, 0x3C, 0x78, 0x32, 0x69, 0xA6, 0x90,
+	0x24, 0x31, 0x47, 0xE2, 0x8B, 0x46, 0x67, 0x62, 0x70, 0x14, 0x01, 0x26, 0x49, 0x27, 0x8C, 0x0E,
+	0xF5, 0xD7, 0x29, 0xC1, 0x52, 0x7D, 0x7F, 0xA1, 0xAF, 0xC6, 0xCF, 0x86, 0xBF, 0xF2, 0x51, 0xBC,
+	0x39, 0xFF, 0x00, 0x61, 0xAB, 0x5F, 0xFD, 0x29, 0x4A, 0xFD, 0x92, 0x3F, 0x70, 0x7F, 0x9E, 0xC6,
+	0x80, 0x38, 0xFF, 0x00, 0xF8, 0x69, 0x7F, 0xD9, 0xC7, 0xFE, 0x8E, 0x03, 0xC1, 0x3F, 0xF8, 0x55,
+	0x59, 0xFF, 0x00, 0xF1, 0xCA, 0x3F, 0xE1, 0xA5, 0xFF, 0x00, 0x67, 0x1F, 0xFA, 0x38, 0x0F, 0x04,
+	0xFF, 0x00, 0xE1, 0x55, 0x67, 0xFF, 0x00, 0xC7, 0x2B, 0xF2, 0x06, 0x8A, 0x00, 0xFD, 0x7E, 0xFF,
+	0x00, 0x86, 0x97, 0xFD, 0x9C, 0x7F, 0xE8, 0xE0, 0x3C, 0x13, 0xFF, 0x00, 0x85, 0x55, 0x9F, 0xFF,
+	0x00, 0x1C, 0xA3, 0xFE, 0x1A, 0x5F, 0xF6, 0x71, 0xFF, 0x00, 0xA3, 0x80, 0xF0, 0x4F, 0xFE, 0x15,
+	0x56, 0x7F, 0xFC, 0x72, 0xBF, 0x20, 0x68, 0xA0, 0x0F, 0xD8, 0xBF, 0x0E, 0xFC, 0x72, 0xF8, 0x29,
+	0xE3, 0x0D, 0x66, 0x1F, 0x0E, 0x78, 0x4B, 0xE3, 0x07, 0x85, 0xB5, 0x4D, 0x42, 0xE3, 0x77, 0xD9,
+	0xEC, 0x74, 0xEF, 0x10, 0x5B, 0x4F, 0x34, 0xBB, 0x54, 0xB3, 0x6D, 0x44, 0x72, 0xCD, 0x85, 0x05,
+	0x8E, 0x07, 0x00, 0x13, 0xD0, 0x56, 0xEE, 0xB3, 0xAE, 0xE8, 0x9E, 0x19, 0xD3, 0x2E, 0x35, 0xEF,
+	0x12, 0x6B, 0x16, 0xBA, 0x7D, 0x8D, 0xAC, 0x7B, 0xEE, 0x6F, 0x2F, 0xAE, 0x16, 0x28, 0xA2, 0x5F,
+	0xEF, 0x33, 0xB1, 0x0A, 0xA3, 0xDC, 0x9A, 0xFC, 0xC3, 0xFF, 0x00, 0x82, 0x76, 0x7F, 0xC9, 0xE4,
+	0x78, 0x37, 0xFD, 0xDD, 0x4B, 0xFF, 0x00, 0x4D, 0xD7, 0x35, 0xF7, 0x97, 0xED, 0xAF, 0xFF, 0x00,
+	0x26, 0xAF, 0xE3, 0x8F, 0xFB, 0x01, 0xBF, 0xF3, 0x14, 0x01, 0xD0, 0x7F, 0xC3, 0x4B, 0xFE, 0xCE,
+	0x3F, 0xF4, 0x70, 0x1E, 0x09, 0xFF, 0x00, 0xC2, 0xAA, 0xCF, 0xFF, 0x00, 0x8E, 0x51, 0xFF, 0x00,
+	0x0D, 0x2F, 0xFB, 0x38, 0xFF, 0x00, 0xD1, 0xC0, 0x78, 0x27, 0xFF, 0x00, 0x0A, 0xAB, 0x3F, 0xFE,
+	0x39, 0x5F, 0x90, 0x34, 0x50, 0x07, 0xEB, 0xF7, 0xFC, 0x34, 0xBF, 0xEC, 0xE3, 0xFF, 0x00, 0x47,
+	0x01, 0xE0, 0x9F, 0xFC, 0x2A, 0xAC, 0xFF, 0x00, 0xF8, 0xE5, 0x1F, 0xF0, 0xD2, 0xFF, 0x00, 0xB3,
+	0x8F, 0xFD, 0x1C, 0x07, 0x82, 0x7F, 0xF0, 0xAA, 0xB3, 0xFF, 0x00, 0xE3, 0x95, 0xF9, 0x03, 0x45,
+	0x00, 0x7E, 0xCA, 0xF8, 0x43, 0xE2, 0xBF, 0xC2, 0xEF, 0x88, 0x37, 0x33, 0x59, 0xF8, 0x0B, 0xE2,
+	0x4E, 0x81, 0xAE, 0x4D, 0x6F, 0x18, 0x7B, 0x88, 0xB4, 0x7D, 0x62, 0x0B, 0x96, 0x89, 0x49, 0xC6,
+	0xE6, 0x11, 0xB1, 0x20, 0x67, 0xB9, 0xAB, 0x7E, 0x2E, 0xF1, 0xD7, 0x82, 0x7C, 0x01, 0xA7, 0x47,
+	0xAC, 0x78, 0xEF, 0xC6, 0x3A, 0x5E, 0x89, 0x67, 0x24, 0xE2, 0x18, 0xEE, 0xB5, 0x7D, 0x42, 0x3B,
+	0x68, 0xDE, 0x42, 0x0B, 0x04, 0x0D, 0x23, 0x00, 0x58, 0x85, 0x63, 0x8C, 0xE7, 0x00, 0x9E, 0xD5,
+	0xF0, 0xCF, 0xFC, 0x12, 0x2B, 0xFE, 0x4A, 0x2F, 0x8C, 0x3F, 0xEC, 0x03, 0x17, 0xFE, 0x8E, 0x35,
+	0xEB, 0x9F, 0xF0, 0x55, 0x2D, 0x03, 0x5C, 0xF1, 0x2F, 0xC0, 0x0D, 0x1F, 0x4D, 0xF0, 0xE6, 0x91,
+	0x73, 0x7B, 0x76, 0x7C, 0x65, 0x01, 0x5B, 0x7B, 0x58, 0x64, 0x95, 0x98, 0x7D, 0x96, 0xEF, 0x3C,
+	0x25, 0x00, 0x7B, 0x47, 0xFC, 0x34, 0xC7, 0xEC, 0xE3, 0xFF, 0x00, 0x47, 0x01, 0xE0, 0x9F, 0xFC,
+	0x2A, 0xEC, 0xFF, 0x00, 0xF8, 0xE5, 0x1F, 0xF0, 0xD2, 0xFF, 0x00, 0xB3, 0x8F, 0xFD, 0x1C, 0x07,
+	0x82, 0x7F, 0xF0, 0xAA, 0xB3, 0xFF, 0x00, 0xE3, 0x95, 0xF9, 0x61, 0x69, 0xF0, 0x0F, 0xE3, 0xBE,
+	0xA7, 0x31, 0x8B, 0x4F, 0xF8, 0x23, 0xE3, 0x09, 0xBE, 0x5D, 0xC1, 0x63, 0xF0, 0xED, 0xEB, 0xFF,
+	0x00, 0xEC, 0x86, 0xAC, 0x8F, 0xD9, 0xAF, 0xF6, 0x8A, 0x61, 0xB9, 0xBE, 0x00, 0x78, 0xDB, 0x3D,
+	0xFF, 0x00, 0xE2, 0x97, 0xBD, 0xFF, 0x00, 0xE2, 0x28, 0x03, 0xF5, 0x1B, 0xFE, 0x1A, 0x5F, 0xF6,
+	0x71, 0xFF, 0x00, 0xA3, 0x80, 0xF0, 0x4F, 0xFE, 0x15, 0x56, 0x7F, 0xFC, 0x72, 0x8F, 0xF8, 0x69,
+	0x7F, 0xD9, 0xC7, 0xFE, 0x8E, 0x03, 0xC1, 0x3F, 0xF8, 0x55, 0x59, 0xFF, 0x00, 0xF1, 0xCA, 0xFC,
+	0xB9, 0xFF, 0x00, 0x86, 0x6A, 0xFD, 0xA2, 0x7F, 0xE8, 0x80, 0xF8, 0xD7, 0xFF, 0x00, 0x09, 0x7B,
+	0xDF, 0xFE, 0x22, 0xAB, 0x5F, 0x7E, 0xCF, 0x3F, 0x1F, 0x34, 0xF3, 0x9D, 0x43, 0xE0, 0x77, 0x8B,
+	0xE1, 0xDD, 0xF7, 0x5A, 0x4F, 0x0C, 0xDC, 0xAF, 0xF3, 0x4A, 0x00, 0xFD, 0x6D, 0xF0, 0xAF, 0x8E,
+	0x7C, 0x15, 0xE3, 0xFD, 0x3D, 0xF5, 0x9F, 0x02, 0x78, 0xC3, 0x4B, 0xD6, 0xEC, 0xE3, 0x9F, 0xC9,
+	0x92, 0xEB, 0x48, 0xD4, 0x23, 0xB9, 0x8D, 0x24, 0x0A, 0x18, 0xA1, 0x68, 0xD8, 0x80, 0xC0, 0x32,
+	0x9C, 0x67, 0x38, 0x60, 0x7B, 0x8A, 0xAF, 0xE2, 0xEF, 0x8A, 0xDF, 0x0B, 0xFE, 0x1E, 0xCF, 0x0D,
+	0x97, 0x8F, 0xFE, 0x24, 0x68, 0x1A, 0x1C, 0xD7, 0x11, 0xEF, 0xB7, 0x87, 0x58, 0xD6, 0x20, 0xB6,
+	0x69, 0x14, 0x1C, 0x16, 0x51, 0x23, 0x02, 0x46, 0x7B, 0x8A, 0xF0, 0x3F, 0xF8, 0x25, 0xA7, 0x87,
+	0xF5, 0xDF, 0x0C, 0x7C, 0x03, 0xD6, 0xB4, 0x9F, 0x13, 0x68, 0x77, 0x5A, 0x7D, 0xE7, 0xFC, 0x26,
+	0x97, 0x07, 0xEC, 0xB7, 0xD6, 0xE6, 0x19, 0x0A, 0xFD, 0x8E, 0xD3, 0x9D, 0xA7, 0x93, 0xF8, 0xD7,
+	0x91, 0xFF, 0x00, 0xC1, 0x5E, 0x7F, 0xE4, 0xA2, 0x78, 0x3F, 0x8F, 0xF9, 0x80, 0xCB, 0xD4, 0x63,
+	0xFE, 0x5A, 0x9A, 0x00, 0xFB, 0x0B, 0xFE, 0x1A, 0x5F, 0xF6, 0x71, 0xFF, 0x00, 0xA3, 0x80, 0xF0,
+	0x4F, 0xFE, 0x15, 0x56, 0x7F, 0xFC, 0x72, 0x8F, 0xF8, 0x69, 0x7F, 0xD9, 0xC7, 0xFE, 0x8E, 0x03,
+	0xC1, 0x3F, 0xF8, 0x55, 0x59, 0xFF, 0x00, 0xF1, 0xCA, 0xFC, 0x81, 0xA2, 0x80, 0x3F, 0x5F, 0xBF,
+	0xE1, 0xA5, 0xFF, 0x00, 0x67, 0x1F, 0xFA, 0x38, 0x0F, 0x04, 0xFF, 0x00, 0xE1, 0x55, 0x67, 0xFF,
+	0x00, 0xC7, 0x28, 0xFF, 0x00, 0x86, 0x97, 0xFD, 0x9C, 0x7F, 0xE8, 0xE0, 0x3C, 0x13, 0xFF, 0x00,
+	0x85, 0x55, 0x9F, 0xFF, 0x00, 0x1C, 0xAF, 0xC8, 0x1A, 0x28, 0x03, 0xF6, 0x93, 0x4A, 0xD7, 0x74,
+	0x4F, 0x12, 0xE9, 0x70, 0xEB, 0xDE, 0x1C, 0xD6, 0x2D, 0x75, 0x0B, 0x1B, 0xA8, 0x77, 0xDB, 0x5E,
+	0x58, 0xDC, 0x2C, 0xB0, 0xCC, 0xBC, 0xFC, 0xCA, 0xEA, 0x4A, 0xB0, 0xF7, 0x06, 0xB1, 0xBC, 0x47,
+	0xF1, 0xCB, 0xE0, 0xA7, 0x83, 0xB5, 0x99, 0xBC, 0x3B, 0xE2, 0xEF, 0x8C, 0x1E, 0x16, 0xD2, 0xB5,
+	0x0B, 0x6D, 0xBF, 0x68, 0xB1, 0xD4, 0xBC, 0x41, 0x6D, 0x04, 0xD1, 0x6E, 0x50, 0xEB, 0xB9, 0x1D,
+	0xC3, 0x2E, 0x54, 0x86, 0x19, 0x1C, 0x82, 0x0F, 0x43, 0x5C, 0x87, 0xEC, 0x5B, 0xFF, 0x00, 0x26,
+	0xA9, 0xE0, 0x8F, 0xFB, 0x00, 0xAF, 0xFE, 0x84, 0xD5, 0xF0, 0x7F, 0xFC, 0x14, 0x6F, 0xFE, 0x4F,
+	0x1B, 0xC6, 0x5F, 0xF7, 0x0F, 0xFF, 0x00, 0xD3, 0x6D, 0xBD, 0x00, 0x7E, 0x89, 0x7F, 0xC3, 0x4B,
+	0xFE, 0xCE, 0x3F, 0xF4, 0x70, 0x1E, 0x09, 0xFF, 0x00, 0xC2, 0xAA, 0xCF, 0xFF, 0x00, 0x8E, 0x51,
+	0xFF, 0x00, 0x0D, 0x2F, 0xFB, 0x38, 0xFF, 0x00, 0xD1, 0xC0, 0x78, 0x27, 0xFF, 0x00, 0x0A, 0xAB,
+	0x3F, 0xFE, 0x39, 0x5F, 0x90, 0x27, 0xAD, 0x14, 0x01, 0xFA, 0xFD, 0xFF, 0x00, 0x0D, 0x2F, 0xFB,
+	0x38, 0xFF, 0x00, 0xD1, 0xC0, 0x78, 0x27, 0xFF, 0x00, 0x0A, 0xAB, 0x3F, 0xFE, 0x39, 0x47, 0xFC,
+	0x34, 0xBF, 0xEC, 0xE3, 0xFF, 0x00, 0x47, 0x01, 0xE0, 0x9F, 0xFC, 0x2A, 0xAC, 0xFF, 0x00, 0xF8,
+	0xE5, 0x7E, 0x40, 0xD2, 0xAF, 0x53, 0xFE, 0xF2, 0xFF, 0x00, 0x4A, 0x00, 0xFD, 0xB1, 0x46, 0x5D,
+	0x83, 0xE6, 0xED, 0x5C, 0x7D, 0xF7, 0xED, 0x13, 0xFB, 0x3F, 0x69, 0x97, 0xB3, 0x69, 0xBA, 0x97,
+	0xC7, 0x4F, 0x06, 0xDB, 0xDC, 0x5B, 0xCA, 0xD1, 0x5C, 0x5B, 0xCF, 0xE2, 0x6B, 0x44, 0x78, 0x9D,
+	0x4E, 0x19, 0x59, 0x4C, 0x99, 0x04, 0x10, 0x41, 0x07, 0x90, 0x6B, 0xAB, 0x8B, 0xEE, 0x9F, 0xF3,
+	0xEB, 0x5F, 0x8F, 0x5F, 0x1C, 0x3F, 0xE4, 0xB5, 0x78, 0xC3, 0xFE, 0xC6, 0x8D, 0x43, 0xFF, 0x00,
+	0x4A, 0x64, 0xA0, 0x0F, 0xD5, 0x6F, 0xF8, 0x69, 0x7F, 0xD9, 0xC7, 0xFE, 0x8E, 0x03, 0xC1, 0x3F,
+	0xF8, 0x55, 0x59, 0xFF, 0x00, 0xF1, 0xCA, 0x3F, 0xE1, 0xA5, 0xFF, 0x00, 0x67, 0x1F, 0xFA, 0x38,
+	0x0F, 0x04, 0xFF, 0x00, 0xE1, 0x55, 0x67, 0xFF, 0x00, 0xC7, 0x2B, 0xF2, 0x06, 0x8A, 0x00, 0xFD,
+	0x7E, 0xFF, 0x00, 0x86, 0x97, 0xFD, 0x9C, 0x7F, 0xE8, 0xE0, 0x3C, 0x13, 0xFF, 0x00, 0x85, 0x55,
+	0x9F, 0xFF, 0x00, 0x1C, 0xAB, 0x1A, 0x47, 0xED, 0x01, 0xF0, 0x1F, 0x5F, 0xD4, 0xED, 0xF4, 0x4D,
+	0x07, 0xE3, 0x67, 0x84, 0x6F, 0xAF, 0x2E, 0xA6, 0x58, 0xAD, 0x6C, 0xEC, 0xFC, 0x49, 0x6B, 0x24,
+	0xB3, 0x48, 0x7A, 0x2A, 0xAA, 0xC8, 0x4B, 0x31, 0xEC, 0x00, 0xCD, 0x7E, 0x3C, 0xD7, 0xA2, 0x7E,
+	0xC9, 0x5F, 0xF2, 0x73, 0x9E, 0x01, 0xFF, 0x00, 0xB1, 0xAA, 0xD3, 0xFF, 0x00, 0x42, 0x14, 0x01,
+	0xFA, 0xD5, 0x7D, 0xA8, 0x58, 0x69, 0x96, 0x53, 0x6A, 0x5A, 0x95, 0xF4, 0x36, 0xF6, 0xF6, 0xF1,
+	0x34, 0xB7, 0x17, 0x13, 0xC8, 0x11, 0x23, 0x45, 0x19, 0x66, 0x66, 0x3C, 0x00, 0x00, 0xC9, 0x27,
+	0x81, 0x5C, 0x7F, 0xFC, 0x34, 0xBF, 0xEC, 0xE3, 0xFF, 0x00, 0x47, 0x01, 0xE0, 0x9F, 0xFC, 0x2A,
+	0xAC, 0xFF, 0x00, 0xF8, 0xE5, 0x4F, 0xF1, 0xB7, 0xFE, 0x48, 0xC7, 0x8B, 0x3F, 0xEC, 0x57, 0xD4,
+	0x3F, 0xF4, 0x43, 0xD7, 0xE3, 0xD5, 0x00, 0x7E, 0xBF, 0x7F, 0xC3, 0x4B, 0xFE, 0xCE, 0x3F, 0xF4,
+	0x70, 0x1E, 0x09, 0xFF, 0x00, 0xC2, 0xAA, 0xCF, 0xFF, 0x00, 0x8E, 0x51, 0xFF, 0x00, 0x0D, 0x2F,
+	0xFB, 0x38, 0xFF, 0x00, 0xD1, 0xC0, 0x78, 0x27, 0xFF, 0x00, 0x0A, 0xAB, 0x3F, 0xFE, 0x39, 0x5F,
+	0x90, 0x34, 0x50, 0x07, 0xEB, 0xF7, 0xFC, 0x34, 0xBF, 0xEC, 0xE3, 0xFF, 0x00, 0x47, 0x01, 0xE0,
+	0x9F, 0xFC, 0x2A, 0xAC, 0xFF, 0x00, 0xF8, 0xE5, 0x68, 0x78, 0x67, 0xE3, 0x27, 0xC2, 0x1F, 0x1D,
+	0xDF, 0xB6, 0x87, 0xE0, 0x7F, 0x8A, 0xBE, 0x1B, 0xD6, 0x6F, 0x44, 0x2D, 0x29, 0xB3, 0xD2, 0x75,
+	0xCB, 0x7B, 0x89, 0x42, 0x02, 0x01, 0x6D, 0x91, 0xB9, 0x38, 0x04, 0x8C, 0x9C, 0x60, 0x64, 0x7A,
+	0xD7, 0xE3, 0x8D, 0x7D, 0x25, 0xFF, 0x00, 0x04, 0xAD, 0xFF, 0x00, 0x93, 0x9A, 0x9F, 0xFE, 0xC5,
+	0x6B, 0xEF, 0xFD, 0x1B, 0x6F, 0x40, 0x1F, 0xA2, 0x5E, 0x25, 0xF1, 0x67, 0x85, 0xBC, 0x17, 0xA4,
+	0x49, 0xAF, 0xF8, 0xC7, 0xC4, 0xBA, 0x7E, 0x93, 0x61, 0x13, 0x2A, 0xCB, 0x7D, 0xA9, 0x5E, 0x24,
+	0x10, 0xA1, 0x63, 0x80, 0x0B, 0xB9, 0x0A, 0x32, 0x78, 0x1C, 0xF2, 0x6B, 0x99, 0xFF, 0x00, 0x86,
+	0x97, 0xFD, 0x9C, 0x7F, 0xE8, 0xE0, 0x3C, 0x13, 0xFF, 0x00, 0x85, 0x55, 0x9F, 0xFF, 0x00, 0x1C,
+	0xAF, 0x36, 0xFF, 0x00, 0x82, 0x95, 0x7F, 0xC9, 0xA5, 0x6B, 0xDF, 0xF5, 0xFB, 0x63, 0xFF, 0x00,
+	0xA5, 0x0B, 0x5F, 0x99, 0x54, 0x01, 0xFA, 0xFD, 0xFF, 0x00, 0x0D, 0x2F, 0xFB, 0x38, 0xFF, 0x00,
+	0xD1, 0xC0, 0x78, 0x27, 0xFF, 0x00, 0x0A, 0xAB, 0x3F, 0xFE, 0x39, 0x47, 0xFC, 0x34, 0xBF, 0xEC,
+	0xE3, 0xFF, 0x00, 0x47, 0x01, 0xE0, 0x9F, 0xFC, 0x2A, 0xAC, 0xFF, 0x00, 0xF8, 0xE5, 0x7E, 0x40,
+	0xD1, 0x40, 0x1F, 0xAF, 0xDF, 0xF0, 0xD2, 0xFF, 0x00, 0xB3, 0x8F, 0xFD, 0x1C, 0x07, 0x82, 0x7F,
+	0xF0, 0xAA, 0xB3, 0xFF, 0x00, 0xE3, 0x95, 0xB9, 0xE0, 0xFF, 0x00, 0x89, 0x3F, 0x0E, 0xFE, 0x21,
+	0x47, 0x3C, 0xDE, 0x01, 0xF1, 0xEE, 0x8B, 0xAE, 0x25, 0xAB, 0x2A, 0xDD, 0x36, 0x8F, 0xAA, 0x43,
+	0x72, 0x21, 0x2C, 0x09, 0x01, 0x8C, 0x6C, 0x76, 0x92, 0x01, 0xC6, 0x7A, 0xE0, 0xFA, 0x57, 0xE3,
+	0x2D, 0x7D, 0xC7, 0xFF, 0x00, 0x04, 0x83, 0xFF, 0x00, 0x91, 0x6F, 0xC7, 0x5F, 0xF5, 0xFF, 0x00,
+	0x63, 0xFF, 0x00, 0xA2, 0xAE, 0x28, 0x03, 0xEB, 0x7F, 0x18, 0x7C, 0x48, 0xF8, 0x77, 0xF0, 0xF2,
+	0x3B, 0x79, 0x7C, 0x7F, 0xE3, 0xDD, 0x17, 0x43, 0x5B, 0xA6, 0x65, 0xB5, 0x6D, 0x63, 0x54, 0x86,
+	0xD4, 0x4C, 0x57, 0xA8, 0x5F, 0x31, 0x86, 0xEC, 0x64, 0x67, 0x1D, 0x33, 0x58, 0x7F, 0xF0, 0xD2,
+	0xFF, 0x00, 0xB3, 0x8F, 0xFD, 0x1C, 0x07, 0x82, 0x7F, 0xF0, 0xAA, 0xB3, 0xFF, 0x00, 0xE3, 0x95,
+	0xF3, 0x2F, 0xFC, 0x16, 0x03, 0xFE, 0x40, 0x1E, 0x05, 0xFF, 0x00, 0xAF, 0xDB, 0xEF, 0xFD, 0x02,
+	0x3A, 0xF8, 0x6E, 0x80, 0x3F, 0x5F, 0xBF, 0xE1, 0xA5, 0xFF, 0x00, 0x67, 0x1F, 0xFA, 0x38, 0x0F,
+	0x04, 0xFF, 0x00, 0xE1, 0x55, 0x67, 0xFF, 0x00, 0xC7, 0x28, 0xFF, 0x00, 0x86, 0x97, 0xFD, 0x9C,
+	0x7F, 0xE8, 0xE0, 0x3C, 0x13, 0xFF, 0x00, 0x85, 0x55, 0x9F, 0xFF, 0x00, 0x1C, 0xAF, 0xC8, 0x1A,
+	0x28, 0x03, 0xF5, 0xFB, 0xFE, 0x1A, 0x5F, 0xF6, 0x71, 0xFF, 0x00, 0xA3, 0x80, 0xF0, 0x4F, 0xFE,
+	0x15, 0x56, 0x7F, 0xFC, 0x72, 0xBA, 0x6F, 0x0D, 0x78, 0xB7, 0xC2, 0xBE, 0x34, 0xD2, 0x23, 0xF1,
+	0x07, 0x83, 0xBC, 0x4B, 0xA7, 0xEA, 0xD6, 0x12, 0xB3, 0x2C, 0x77, 0xDA, 0x6D, 0xE2, 0x4F, 0x0B,
+	0x95, 0x38, 0x60, 0x1D, 0x09, 0x52, 0x41, 0xE0, 0xF3, 0xC1, 0xAF, 0xC5, 0xBA, 0xFD, 0x34, 0xFF,
+	0x00, 0x82, 0x6A, 0xFF, 0x00, 0xC9, 0xA3, 0xE8, 0x7F, 0xF5, 0xFD, 0x7F, 0xFF, 0x00, 0xA5, 0x2D,
+	0x40, 0x1E, 0xB9, 0xE2, 0xBF, 0x8C, 0xBF, 0x08, 0x3C, 0x09, 0xA9, 0xFF, 0x00, 0x62, 0xF8, 0xE3,
+	0xE2, 0xAF, 0x86, 0xF4, 0x6B, 0xC3, 0x10, 0x94, 0x5A, 0x6A, 0xDA, 0xE5, 0xBD, 0xBC, 0xA6, 0x32,
+	0x48, 0x0D, 0xB6, 0x47, 0x07, 0x07, 0x07, 0x9C, 0x63, 0x8A, 0xCD, 0xFF, 0x00, 0x86, 0x97, 0xFD,
+	0x9C, 0x7F, 0xE8, 0xE0, 0x3C, 0x13, 0xFF, 0x00, 0x85, 0x55, 0x9F, 0xFF, 0x00, 0x1C, 0xAF, 0x84,
+	0xFF, 0x00, 0xE0, 0xAA, 0xFF, 0x00, 0xF2, 0x72, 0xD1, 0x7F, 0xD8, 0xAB, 0x6B, 0xFF, 0x00, 0xA3,
+	0x26, 0xAF, 0x9B, 0x4F, 0x5A, 0x00, 0xFD, 0x7E, 0xFF, 0x00, 0x86, 0x97, 0xFD, 0x9C, 0x7F, 0xE8,
+	0xE0, 0x3C, 0x13, 0xFF, 0x00, 0x85, 0x55, 0x9F, 0xFF, 0x00, 0x1C, 0xA3, 0xFE, 0x1A, 0x5F, 0xF6,
+	0x71, 0xFF, 0x00, 0xA3, 0x80, 0xF0, 0x4F, 0xFE, 0x15, 0x56, 0x7F, 0xFC, 0x72, 0xBF, 0x20, 0x68,
+	0xA0, 0x0F, 0xD7, 0xEF, 0xF8, 0x69, 0x8F, 0xD9, 0xC3, 0xFE, 0x8E, 0x03, 0xC1, 0x3F, 0xF8, 0x55,
+	0xD9, 0xFF, 0x00, 0xF1, 0xCA, 0xEC, 0x2C, 0xAF, 0xEC, 0x75, 0x4B, 0x18, 0x75, 0x2D, 0x32, 0xF6,
+	0x1B, 0x8B, 0x7B, 0x88, 0x56, 0x5B, 0x7B, 0x88, 0x24, 0x0E, 0x92, 0xA3, 0x0C, 0xAB, 0x2B, 0x0E,
+	0x08, 0x20, 0x82, 0x08, 0xE0, 0x8A, 0xFC, 0x4F, 0x7F, 0xE2, 0xFF, 0x00, 0x7B, 0xFF, 0x00, 0x65,
+	0x5A, 0xFD, 0x8A, 0xF8, 0x1F, 0xFF, 0x00, 0x24, 0x57, 0xC1, 0xFF, 0x00, 0xF6, 0x2B, 0xE9, 0xFF,
+	0x00, 0xFA, 0x4D, 0x1D, 0x00, 0x1A, 0xD7, 0xC7, 0xBF, 0x81, 0x9E, 0x1A, 0xD5, 0xA7, 0xD0, 0x7C,
+	0x47, 0xF1, 0xA3, 0xC2, 0x7A, 0x7D, 0xF5, 0xAC, 0x9B, 0x2E, 0x6C, 0xAF, 0x7C, 0x45, 0x6B, 0x14,
+	0xD1, 0x37, 0xF7, 0x59, 0x19, 0xC3, 0x29, 0xF6, 0x22, 0xAA, 0xFF, 0x00, 0xC3, 0x4C, 0x7E, 0xCE,
+	0x1F, 0xF4, 0x70, 0x1E, 0x09, 0xFF, 0x00, 0xC2, 0xAE, 0xCF, 0xFF, 0x00, 0x8E, 0x57, 0xE6, 0x9F,
+	0xED, 0xA7, 0xFF, 0x00, 0x27, 0x5D, 0xE3, 0x6F, 0xFB, 0x0E, 0x1F, 0xFD, 0x05, 0x6B, 0xCB, 0x13,
+	0xEE, 0x0F, 0xA5, 0x00, 0x7E, 0xBF, 0xFF, 0x00, 0xC3, 0x4B, 0xFE, 0xCE, 0x3F, 0xF4, 0x70, 0x1E,
+	0x09, 0xFF, 0x00, 0xC2, 0xAA, 0xCF, 0xFF, 0x00, 0x8E, 0x51, 0xFF, 0x00, 0x0D, 0x2F, 0xFB, 0x38,
+	0xFF, 0x00, 0xD1, 0xC0, 0x78, 0x27, 0xFF, 0x00, 0x0A, 0xAB, 0x3F, 0xFE, 0x39, 0x5F, 0x90, 0x34,
+	0x50, 0x07, 0xEB, 0xF7, 0xFC, 0x34, 0xBF, 0xEC, 0xE3, 0xFF, 0x00, 0x47, 0x01, 0xE0, 0x9F, 0xFC,
+	0x2A, 0xAC, 0xFF, 0x00, 0xF8, 0xE5, 0x6F, 0x78, 0x43, 0xE2, 0x1F, 0x80, 0x7E, 0x21, 0x5B, 0x4D,
+	0x7B, 0xE0, 0x1F, 0x1C, 0x68, 0xFA, 0xE4, 0x36, 0xF2, 0x04, 0xB8, 0x9B, 0x47, 0xD4, 0xA2, 0xB9,
+	0x58, 0x98, 0x8C, 0x85, 0x63, 0x1B, 0x10, 0xA7, 0x1C, 0xE0, 0xD7, 0xE3, 0x1D, 0x7D, 0xE9, 0xFF,
+	0x00, 0x04, 0x85, 0xFF, 0x00, 0x92, 0x6B, 0xE3, 0x0F, 0xFB, 0x0E, 0x41, 0xFF, 0x00, 0xA2, 0x68,
+	0x03, 0xE9, 0xCF, 0x15, 0x7C, 0x64, 0xF8, 0x43, 0xE0, 0x5D, 0x4C, 0x68, 0x9E, 0x37, 0xF8, 0xAB,
+	0xE1, 0xBD, 0x1A, 0xF1, 0xA2, 0x12, 0xAD, 0x9E, 0xAB, 0xAE, 0x5B, 0xDB, 0xCA, 0x50, 0xE7, 0x0D,
+	0xB6, 0x47, 0x07, 0x07, 0x07, 0x9C, 0x63, 0x8A, 0xCD, 0xFF, 0x00, 0x86, 0x97, 0xFD, 0x9C, 0x7F,
+	0xE8, 0xE0, 0x3C, 0x13, 0xFF, 0x00, 0x85, 0x55, 0x9F, 0xFF, 0x00, 0x1C, 0xAF, 0x85, 0x3F, 0xE0,
+	0xAA, 0x3F, 0xF2, 0x73, 0x36, 0xFF, 0x00, 0xF6, 0x2C, 0x5A, 0xFF, 0x00, 0xE8, 0x72, 0xD7, 0xCD,
+	0x94, 0x01, 0xFA, 0xFD, 0xFF, 0x00, 0x0D, 0x2F, 0xFB, 0x38, 0xFF, 0x00, 0xD1, 0xC0, 0x78, 0x27,
+	0xFF, 0x00, 0x0A, 0xAB, 0x3F, 0xFE, 0x39, 0x47, 0xFC, 0x34, 0xBF, 0xEC, 0xE3, 0xFF, 0x00, 0x47,
+	0x01, 0xE0, 0x9F, 0xFC, 0x2A, 0xAC, 0xFF, 0x00, 0xF8, 0xE5, 0x7E, 0x40, 0xD1, 0x40, 0x1F, 0xAF,
+	0xDF, 0xF0, 0xD2, 0xFF, 0x00, 0xB3, 0x8F, 0xFD, 0x1C, 0x07, 0x82, 0x7F, 0xF0, 0xAA, 0xB3, 0xFF,
+	0x00, 0xE3, 0x95, 0xB9, 0xE0, 0xFF, 0x00, 0x88, 0xFF, 0x00, 0x0F, 0x3E, 0x21, 0x47, 0x71, 0x37,
+	0x80, 0x3C, 0x79, 0xA2, 0xEB, 0x89, 0x6A, 0xCA, 0xB7, 0x4D, 0xA3, 0xEA, 0x90, 0xDD, 0x08, 0x4B,
+	0x67, 0x68, 0x6F, 0x2D, 0x8E, 0xD2, 0x70, 0x71, 0x9E, 0xB8, 0xAF, 0xC6, 0x5E, 0xDF, 0x85, 0x7D,
+	0xD1, 0xFF, 0x00, 0x04, 0x80, 0xFF, 0x00, 0x91, 0x73, 0xC7, 0xDF, 0xF6, 0x10, 0xB0, 0xFF, 0x00,
+	0xD1, 0x73, 0x50, 0x07, 0xD5, 0x1E, 0x2A, 0xF8, 0xC9, 0xF0, 0x87, 0xC0, 0xBA, 0x98, 0xD1, 0x3C,
+	0x6F, 0xF1, 0x57, 0xC3, 0x7A, 0x35, 0xE3, 0x44, 0x25, 0x5B, 0x3D, 0x57, 0x5C, 0xB7, 0xB7, 0x94,
+	0xA1, 0xCE, 0x1B, 0x6C, 0x8E, 0x0E, 0x0E, 0x0F, 0x38, 0xC7, 0x15, 0x9B, 0xFF, 0x00, 0x0D, 0x2F,
+	0xFB, 0x38, 0xFF, 0x00, 0xD1, 0xC0, 0x78, 0x27, 0xFF, 0x00, 0x0A, 0xAB, 0x3F, 0xFE, 0x39, 0x5F,
+	0x0A, 0x7F, 0xC1, 0x54, 0x7F, 0xE4, 0xE6, 0x6D, 0xFF, 0x00, 0xEC, 0x58, 0xB5, 0xFF, 0x00, 0xD0,
+	0xE5, 0xAF, 0x9B, 0x28, 0x03, 0xF5, 0xFB, 0xFE, 0x1A, 0x5F, 0xF6, 0x71, 0xFF, 0x00, 0xA3, 0x80,
+	0xF0, 0x4F, 0xFE, 0x15, 0x56, 0x7F, 0xFC, 0x72, 0x8F, 0xF8, 0x69, 0x7F, 0xD9, 0xC7, 0xFE, 0x8E,
+	0x03, 0xC1, 0x3F, 0xF8, 0x55, 0x59, 0xFF, 0x00, 0xF1, 0xCA, 0xFC, 0x81, 0xA2, 0x80, 0x3F, 0x5F,
+	0xBF, 0xE1, 0xA5, 0xFF, 0x00, 0x67, 0x1F, 0xFA, 0x38, 0x0F, 0x04, 0xFF, 0x00, 0xE1, 0x55, 0x67,
+	0xFF, 0x00, 0xC7, 0x2B, 0x73, 0xC1, 0xFF, 0x00, 0x12, 0x3E, 0x1E, 0x7C, 0x42, 0x8E, 0xE2, 0x6F,
+	0x00, 0xF8, 0xF7, 0x45, 0xD7, 0x16, 0xD5, 0x95, 0x6E, 0x9B, 0x47, 0xD5, 0x21, 0xB9, 0x10, 0xB3,
+	0x67, 0x68, 0x6F, 0x2D, 0x8E, 0xD2, 0x70, 0x71, 0x9E, 0xB8, 0xAF, 0xC6, 0x5E, 0xDF, 0x85, 0x7D,
+	0xCD, 0xFF, 0x00, 0x04, 0x83, 0xFF, 0x00, 0x91, 0x7F, 0xC7, 0x7F, 0xF6, 0x12, 0xD3, 0xFF, 0x00,
+	0xF4, 0x5C, 0xB4, 0x01, 0xF6, 0x70, 0x20, 0xF2, 0x0D, 0x14, 0xC8, 0x3F, 0xD5, 0xFE, 0x34, 0xFA,
+	0x00, 0x28, 0x3D, 0x28, 0xA0, 0xF4, 0xA0, 0x0F, 0x85, 0x7F, 0xE0, 0xAF, 0xD8, 0x1E, 0x24, 0xF0,
+	0x3E, 0x0F, 0xFC, 0xB8, 0xDF, 0x7F, 0xE8, 0x71, 0xD7, 0xC6, 0xB5, 0xF6, 0x4F, 0xFC, 0x15, 0xF7,
+	0xFE, 0x46, 0x4F, 0x03, 0xFF, 0x00, 0xD7, 0x95, 0xF7, 0xFE, 0x8C, 0x8E, 0xBE, 0x36, 0xA0, 0x02,
+	0x8A, 0x28, 0xA0, 0x00, 0x75, 0xAF, 0xAB, 0xBF, 0xE0, 0x92, 0x5F, 0xF2, 0x59, 0xFC, 0x4D, 0xFF,
+	0x00, 0x62, 0x9A, 0xFF, 0x00, 0xE9, 0x4C, 0x55, 0xF2, 0x88, 0xEB, 0x5F, 0x57, 0x7F, 0xC1, 0x24,
+	0xBF, 0xE4, 0xB3, 0xF8, 0x9B, 0xFE, 0xC5, 0x35, 0xFF, 0x00, 0xD2, 0x98, 0xA8, 0x03, 0xD7, 0xFF,
+	0x00, 0xE0, 0xAD, 0x1F, 0xF2, 0x6E, 0x9A, 0x47, 0xFD, 0x8E, 0xD6, 0xFF, 0x00, 0xFA, 0x49, 0x75,
+	0x5F, 0x9E, 0x55, 0xFA, 0x1B, 0xFF, 0x00, 0x05, 0x68, 0xFF, 0x00, 0x93, 0x74, 0xD2, 0x3F, 0xEC,
+	0x76, 0xB7, 0xFF, 0x00, 0xD2, 0x4B, 0xAA, 0xFC, 0xF2, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0xBD,
+	0xEB, 0xFE, 0x09, 0xB1, 0xFF, 0x00, 0x27, 0x73, 0xA0, 0xFF, 0x00, 0xD8, 0x3F, 0x50, 0xFF, 0x00,
+	0xD2, 0x77, 0xAF, 0x05, 0xAF, 0x7A, 0xFF, 0x00, 0x82, 0x6C, 0x7F, 0xC9, 0xDC, 0xE8, 0x3F, 0xF6,
+	0x0F, 0xD4, 0x3F, 0xF4, 0x9D, 0xE8, 0x03, 0xEC, 0x8F, 0xF8, 0x28, 0x8F, 0xFC, 0x99, 0xD7, 0x8C,
+	0x3F, 0xDC, 0xD3, 0xFF, 0x00, 0xF4, 0xBE, 0xDE, 0xBF, 0x2F, 0x6B, 0xF5, 0x0B, 0xFE, 0x0A, 0x23,
+	0xFF, 0x00, 0x26, 0x75, 0xE3, 0x0F, 0xF7, 0x34, 0xFF, 0x00, 0xFD, 0x2F, 0xB7, 0xAF, 0xCB, 0xDA,
+	0x00, 0x28, 0xA2, 0x8A, 0x00, 0x2B, 0xD1, 0x3F, 0x64, 0xAF, 0xF9, 0x39, 0xCF, 0x00, 0xFF, 0x00,
+	0xD8, 0xD5, 0x69, 0xFF, 0x00, 0xA1, 0x0A, 0xF3, 0xBA, 0xF4, 0x4F, 0xD9, 0x2B, 0xFE, 0x4E, 0x73,
+	0xC0, 0x3F, 0xF6, 0x35, 0x5A, 0x7F, 0xE8, 0x42, 0x80, 0x3F, 0x50, 0x7E, 0x36, 0xFF, 0x00, 0xC9,
+	0x18, 0xF1, 0x67, 0xFD, 0x8A, 0xFA, 0x87, 0xFE, 0x88, 0x7A, 0xFC, 0x7A, 0xAF, 0xD8, 0x5F, 0x8D,
+	0xBF, 0xF2, 0x46, 0x3C, 0x59, 0xFF, 0x00, 0x62, 0xBE, 0xA1, 0xFF, 0x00, 0xA2, 0x1E, 0xBF, 0x1E,
+	0xA8, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xAF, 0xA4, 0xBF, 0xE0, 0x95, 0xBF, 0xF2, 0x73, 0x53, 0xFF,
+	0x00, 0xD8, 0xAD, 0x7D, 0xFF, 0x00, 0xA3, 0x6D, 0xEB, 0xE6, 0xDA, 0xFA, 0x4B, 0xFE, 0x09, 0x5B,
+	0xFF, 0x00, 0x27, 0x35, 0x3F, 0xFD, 0x8A, 0xD7, 0xDF, 0xFA, 0x36, 0xDE, 0x80, 0x3E, 0xA3, 0xFF,
+	0x00, 0x82, 0x95, 0x7F, 0xC9, 0xA5, 0x6B, 0xDF, 0xF5, 0xFB, 0x63, 0xFF, 0x00, 0xA5, 0x0B, 0x5F,
+	0x99, 0x55, 0xFA, 0x6B, 0xFF, 0x00, 0x05, 0x2A, 0xFF, 0x00, 0x93, 0x4A, 0xD7, 0xBF, 0xEB, 0xF6,
+	0xC7, 0xFF, 0x00, 0x4A, 0x16, 0xBF, 0x32, 0xA8, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xAF, 0xB8, 0xFF,
+	0x00, 0xE0, 0x90, 0x7F, 0xF2, 0x2D, 0xF8, 0xEB, 0xFE, 0xBF, 0xEC, 0x7F, 0xF4, 0x55, 0xC5, 0x7C,
+	0x39, 0x5F, 0x71, 0xFF, 0x00, 0xC1, 0x20, 0xFF, 0x00, 0xE4, 0x5B, 0xF1, 0xD7, 0xFD, 0x7F, 0xD8,
+	0xFF, 0x00, 0xE8, 0xAB, 0x8A, 0x00, 0x5F, 0xF8, 0x2C, 0x07, 0xFC, 0x80, 0x3C, 0x0B, 0xFF, 0x00,
+	0x5F, 0xB7, 0xDF, 0xFA, 0x04, 0x75, 0xF0, 0xDD, 0x7D, 0xC9, 0xFF, 0x00, 0x05, 0x80, 0xFF, 0x00,
+	0x90, 0x07, 0x81, 0x7F, 0xEB, 0xF6, 0xFB, 0xFF, 0x00, 0x40, 0x8E, 0xBE, 0x1B, 0xA0, 0x02, 0x8A,
+	0x28, 0xA0, 0x02, 0xBF, 0x4D, 0x3F, 0xE0, 0x9A, 0xBF, 0xF2, 0x68, 0xFA, 0x1F, 0xFD, 0x7F, 0x5F,
+	0xFF, 0x00, 0xE9, 0x4B, 0x57, 0xE6, 0x5D, 0x7E, 0x9A, 0x7F, 0xC1, 0x35, 0x7F, 0xE4, 0xD1, 0xF4,
+	0x3F, 0xFA, 0xFE, 0xBF, 0xFF, 0x00, 0xD2, 0x96, 0xA0, 0x0F, 0x97, 0x7F, 0xE0, 0xAA, 0xFF, 0x00,
+	0xF2, 0x72, 0xD1, 0x7F, 0xD8, 0xAB, 0x6B, 0xFF, 0x00, 0xA3, 0x26, 0xAF, 0x9B, 0x4F, 0x5A, 0xFA,
+	0x4B, 0xFE, 0x0A, 0xAF, 0xFF, 0x00, 0x27, 0x2D, 0x17, 0xFD, 0x8A, 0xB6, 0xBF, 0xFA, 0x32, 0x6A,
+	0xF9, 0xB4, 0xF5, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x06, 0xBF, 0xF1, 0x7F, 0xBD, 0xFF, 0x00, 0xB2,
+	0xAD, 0x7E, 0xC5, 0x7C, 0x0F, 0xFF, 0x00, 0x92, 0x2B, 0xE0, 0xFF, 0x00, 0xFB, 0x15, 0xF4, 0xFF,
+	0x00, 0xFD, 0x26, 0x8E, 0xBF, 0x1D, 0x5F, 0xF8, 0xBF, 0xDE, 0xFF, 0x00, 0xD9, 0x56, 0xBF, 0x62,
+	0xBE, 0x07, 0xFF, 0x00, 0xC9, 0x15, 0xF0, 0x7F, 0xFD, 0x8A, 0xFA, 0x7F, 0xFE, 0x93, 0x47, 0x40,
+	0x1F, 0x99, 0x3F, 0xB6, 0x9F, 0xFC, 0x9D, 0x77, 0x8D, 0xBF, 0xEC, 0x38, 0x7F, 0xF4, 0x15, 0xAF,
+	0x2C, 0x4F, 0xB8, 0x3E, 0x95, 0xEA, 0x7F, 0xB6, 0x9F, 0xFC, 0x9D, 0x77, 0x8D, 0xBF, 0xEC, 0x38,
+	0x7F, 0xF4, 0x15, 0xAF, 0x2C, 0x4F, 0xB8, 0x3E, 0x94, 0x00, 0xB4, 0x51, 0x45, 0x00, 0x6E, 0x7C,
+	0x35, 0xFF, 0x00, 0x92, 0x8D, 0xE1, 0xCF, 0xFB, 0x0D, 0x5A, 0xFF, 0x00, 0xE9, 0x4A, 0x57, 0xEC,
+	0x91, 0xFB, 0x83, 0xFC, 0xF6, 0x35, 0xF8, 0xDB, 0xF0, 0xD7, 0xFE, 0x4A, 0x37, 0x87, 0x3F, 0xEC,
+	0x35, 0x6B, 0xFF, 0x00, 0xA5, 0x29, 0x5F, 0xB2, 0x47, 0xEE, 0x0F, 0xF3, 0xD8, 0xD0, 0x07, 0xE2,
+	0x8D, 0x14, 0x53, 0x92, 0x27, 0x96, 0x68, 0xED, 0xED, 0x62, 0xF3, 0x1D, 0x8E, 0x11, 0x63, 0x8F,
+	0x74, 0x8C, 0xC7, 0xB0, 0xA0, 0x06, 0xD1, 0x5E, 0xBD, 0xF0, 0xBF, 0xF6, 0x14, 0xFD, 0xA5, 0x7E,
+	0x29, 0xAC, 0x37, 0x76, 0x3F, 0x0F, 0x66, 0xD2, 0xEC, 0x64, 0xDB, 0xB7, 0x52, 0xF1, 0x03, 0x0B,
+	0x54, 0x2A, 0x7A, 0x32, 0xA1, 0x21, 0xA4, 0x04, 0x72, 0x08, 0x56, 0x04, 0x77, 0x35, 0xF4, 0x57,
+	0xC3, 0x5F, 0xF8, 0x24, 0x97, 0x84, 0x74, 0xAF, 0x2A, 0xFF, 0x00, 0xE2, 0xDF, 0xC4, 0x8B, 0xED,
+	0x52, 0x4C, 0x82, 0xF6, 0x1A, 0x2D, 0xA8, 0xB7, 0x80, 0x37, 0x71, 0xB9, 0xC4, 0x8E, 0x47, 0xBA,
+	0xAC, 0x7C, 0x7A, 0x50, 0x07, 0x81, 0xFF, 0x00, 0xC1, 0x3B, 0x3F, 0xE4, 0xF2, 0x3C, 0x1B, 0xFE,
+	0xEE, 0xA5, 0xFF, 0x00, 0xA6, 0xEB, 0x9A, 0xFB, 0xFF, 0x00, 0xF6, 0xAA, 0xF0, 0xBF, 0x89, 0x3C,
+	0x6B, 0xFB, 0x3D, 0xF8, 0xB3, 0xC2, 0xBE, 0x0E, 0xD3, 0xDA, 0xEB, 0x51, 0xD4, 0x34, 0xB6, 0x8A,
+	0xCE, 0xDD, 0x24, 0x44, 0x2D, 0x26, 0xEE, 0x79, 0x6E, 0x3F, 0x3A, 0x4F, 0x85, 0xDF, 0xB2, 0xFF,
+	0x00, 0xC0, 0x9F, 0x83, 0xB3, 0xC5, 0x7F, 0xE0, 0x2F, 0x86, 0x9A, 0x7D, 0xAD, 0xF5, 0xBE, 0x56,
+	0x3D, 0x52, 0x65, 0x37, 0x17, 0x48, 0x0F, 0x5F, 0xDE, 0x4C, 0x4B, 0x28, 0x3F, 0xEC, 0x9A, 0xF4,
+	0x54, 0x00, 0x20, 0x03, 0xD3, 0xFB, 0xD9, 0xFD, 0x68, 0x03, 0xF3, 0x83, 0xC1, 0x5F, 0xF0, 0x4B,
+	0x6F, 0xDA, 0x53, 0xC4, 0xBB, 0x66, 0xF1, 0x21, 0xD0, 0xFC, 0x3E, 0x84, 0xE5, 0xBF, 0xB4, 0x2F,
+	0x9E, 0x69, 0xB6, 0xFB, 0x0B, 0x70, 0x53, 0x3F, 0x56, 0x5F, 0xC2, 0xBD, 0x53, 0xC2, 0x3F, 0xF0,
+	0x48, 0x8F, 0x0B, 0xC1, 0xB6, 0x4F, 0x1B, 0x7C, 0x5F, 0xD4, 0x2E, 0x33, 0xCC, 0x90, 0xE9, 0x3A,
+	0x6A, 0x40, 0x7E, 0x9B, 0xE4, 0x69, 0x33, 0xF5, 0xC7, 0x35, 0xF6, 0x65, 0x14, 0x01, 0xF3, 0xFF,
+	0x00, 0x86, 0x3F, 0xE0, 0x9A, 0x1F, 0xB2, 0x97, 0x86, 0xE3, 0x43, 0x7D, 0xE1, 0x4D, 0x53, 0x58,
+	0x65, 0xE0, 0x36, 0xA9, 0xAD, 0x4A, 0xB9, 0x3E, 0xA5, 0x60, 0x31, 0x29, 0x3F, 0x51, 0x5D, 0xD6,
+	0x83, 0xFB, 0x28, 0xFE, 0xCD, 0xDE, 0x17, 0x58, 0xDB, 0x49, 0xF8, 0x17, 0xE1, 0x9F, 0x31, 0x17,
+	0x1E, 0x65, 0xD6, 0x95, 0x15, 0xC4, 0x83, 0xFE, 0x07, 0x29, 0x2D, 0xFA, 0x93, 0x5E, 0x8D, 0x45,
+	0x00, 0x67, 0x78, 0x77, 0xC3, 0x1E, 0x1B, 0xF0, 0xC5, 0xAF, 0x91, 0xE1, 0xDF, 0x0E, 0xD9, 0xE9,
+	0xF1, 0x95, 0xE2, 0x3B, 0x3B, 0x54, 0x8D, 0x40, 0xF4, 0xF9, 0x6B, 0x44, 0x74, 0xA2, 0x8A, 0x00,
+	0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x2A, 0x9E, 0xAF, 0xA2, 0x68, 0x5A, 0xD5, 0xB9,
+	0xB6, 0xD6, 0xF4, 0x3B, 0x6B, 0xD8, 0xCF, 0x54, 0xBC, 0xB7, 0x59, 0x17, 0xF2, 0x7A, 0xB9, 0x45,
+	0x00, 0x70, 0x1A, 0xDF, 0xEC, 0xC7, 0xFB, 0x3C, 0x78, 0xB0, 0xB4, 0x9A, 0xBF, 0xC1, 0x1F, 0x0B,
+	0xC9, 0xBB, 0x20, 0xC8, 0xBA, 0x2C, 0x29, 0x27, 0xD7, 0x7C, 0x7C, 0x8A, 0xE1, 0xBC, 0x49, 0xFF,
+	0x00, 0x04, 0xE1, 0xFD, 0x93, 0xF5, 0xD4, 0x26, 0xDB, 0xC0, 0x17, 0x3A, 0x5C, 0x8C, 0xB8, 0xF3,
+	0xF4, 0xDD, 0x5A, 0x60, 0x47, 0xD0, 0x39, 0x65, 0x1F, 0x80, 0x03, 0xDA, 0xBD, 0xE2, 0x8A, 0x00,
+	0xF8, 0xFF, 0x00, 0xC5, 0xFF, 0x00, 0xF0, 0x48, 0x9F, 0x87, 0xD7, 0xC1, 0xA4, 0xF0, 0x3F, 0xC5,
+	0x9D, 0x6B, 0x4F, 0xF9, 0x72, 0xB1, 0x6A, 0x96, 0xF0, 0xDD, 0x2E, 0xEF, 0x4D, 0xC8, 0x23, 0x61,
+	0xF8, 0x86, 0x3F, 0x5A, 0xF2, 0xBF, 0x19, 0x7F, 0xC1, 0x2A, 0xBF, 0x68, 0x2F, 0x0F, 0xAB, 0xDC,
+	0x78, 0x5F, 0xC4, 0x1A, 0x16, 0xBB, 0x1A, 0x2F, 0xCB, 0x0C, 0x77, 0x0F, 0x6F, 0x33, 0xFB, 0xFE,
+	0xF4, 0x08, 0xC1, 0x3E, 0xEE, 0x2B, 0xF4, 0x52, 0x8A, 0x00, 0xF3, 0xDF, 0xD9, 0x77, 0xC1, 0xDE,
+	0x22, 0xF0, 0x2F, 0xEC, 0xFF, 0x00, 0xE1, 0x6F, 0x05, 0xF8, 0xC7, 0x4C, 0xFB, 0x26, 0xA1, 0xA7,
+	0xE9, 0x6B, 0x6F, 0x7D, 0x67, 0xE6, 0x23, 0xEC, 0x7C, 0x9C, 0x8D, 0xC8, 0x59, 0x4F, 0x3D, 0xD4,
+	0x90, 0x7B, 0x12, 0x39, 0xAF, 0xCF, 0xCF, 0xF8, 0x28, 0xC9, 0xDD, 0xFB, 0x62, 0x78, 0xC8, 0xE3,
+	0xB6, 0x9F, 0xFF, 0x00, 0xA6, 0xDB, 0x7A, 0xFD, 0x45, 0xAE, 0x1F, 0xE2, 0x2F, 0xEC, 0xF3, 0xF0,
+	0x5F, 0xE2, 0xDB, 0x4D, 0x27, 0xC4, 0x3F, 0x86, 0x7A, 0x4E, 0xA1, 0x34, 0xDF, 0x24, 0x97, 0xD2,
+	0x5A, 0xAA, 0xCE, 0x14, 0x74, 0x02, 0x55, 0x0A, 0xE3, 0xF0, 0x26, 0x80, 0x3F, 0x21, 0xCF, 0x5A,
+	0x2B, 0xEF, 0xEF, 0x89, 0x7F, 0xF0, 0x4A, 0x1F, 0x85, 0x3A, 0xF2, 0xB5, 0xEF, 0xC3, 0x0F, 0x19,
+	0x6A, 0x9A, 0x05, 0xC9, 0xDC, 0x63, 0xB3, 0xBC, 0xFF, 0x00, 0x4C, 0xB6, 0xFA, 0x10, 0x4A, 0xCA,
+	0xA3, 0xB6, 0xEF, 0x31, 0x8F, 0xB1, 0xAF, 0x9D, 0xBE, 0x2A, 0xFF, 0x00, 0xC1, 0x3B, 0x7F, 0x69,
+	0x5F, 0x86, 0x30, 0xC9, 0x7D, 0x6F, 0xE1, 0x7B, 0x7F, 0x11, 0xD8, 0xC7, 0x96, 0xFB, 0x5F, 0x87,
+	0x66, 0x32, 0xB2, 0x2F, 0xBC, 0x52, 0x95, 0x90, 0x9C, 0x7A, 0x2B, 0xFD, 0x4D, 0x00, 0x78, 0x55,
+	0x2A, 0xF5, 0x3F, 0xEF, 0x2F, 0xF4, 0xA7, 0xDF, 0xE9, 0xFA, 0x8E, 0x97, 0x7F, 0x26, 0x97, 0xAB,
+	0x58, 0x4D, 0x6B, 0x71, 0x0B, 0x11, 0x24, 0x17, 0x90, 0x98, 0xDD, 0x58, 0x1E, 0x43, 0x29, 0x00,
+	0xA9, 0x07, 0xAA, 0x90, 0x08, 0x3C, 0x60, 0x54, 0x68, 0x49, 0xE4, 0x81, 0xF7, 0x97, 0xEE, 0xF4,
+	0xED, 0x40, 0x1F, 0xB5, 0xB1, 0x7D, 0xD3, 0xFE, 0x7D, 0x6B, 0xF1, 0xEB, 0xE3, 0x87, 0xFC, 0x96,
+	0xAF, 0x18, 0x7F, 0xD8, 0xD1, 0xA8, 0x7F, 0xE9, 0x4C, 0x95, 0xFB, 0x0B, 0x17, 0xDD, 0x3F, 0xE7,
+	0xD6, 0xBF, 0x1E, 0xBE, 0x38, 0x7F, 0xC9, 0x6A, 0xF1, 0x87, 0xFD, 0x8D, 0x1A, 0x87, 0xFE, 0x94,
+	0xC9, 0x40, 0x1C, 0xBD, 0x14, 0x51, 0x40, 0x05, 0x7A, 0x27, 0xEC, 0x95, 0xFF, 0x00, 0x27, 0x39,
+	0xE0, 0x1F, 0xFB, 0x1A, 0xAD, 0x3F, 0xF4, 0x21, 0x5E, 0x77, 0x5E, 0x89, 0xFB, 0x25, 0x7F, 0xC9,
+	0xCE, 0x78, 0x07, 0xFE, 0xC6, 0xAB, 0x4F, 0xFD, 0x08, 0x50, 0x07, 0xEA, 0x0F, 0xC6, 0xDF, 0xF9,
+	0x23, 0x1E, 0x2C, 0xFF, 0x00, 0xB1, 0x5F, 0x50, 0xFF, 0x00, 0xD1, 0x0F, 0x5F, 0x8F, 0x55, 0xFB,
+	0x0B, 0xF1, 0xB7, 0xFE, 0x48, 0xC7, 0x8B, 0x3F, 0xEC, 0x57, 0xD4, 0x3F, 0xF4, 0x43, 0xD7, 0xE3,
+	0xD5, 0x00, 0x14, 0x51, 0x45, 0x00, 0x15, 0xF4, 0x97, 0xFC, 0x12, 0xB7, 0xFE, 0x4E, 0x6A, 0x7F,
+	0xFB, 0x15, 0xAF, 0xBF, 0xF4, 0x6D, 0xBD, 0x7C, 0xDB, 0x5F, 0x49, 0x7F, 0xC1, 0x2B, 0x7F, 0xE4,
+	0xE6, 0xA7, 0xFF, 0x00, 0xB1, 0x5A, 0xFB, 0xFF, 0x00, 0x46, 0xDB, 0xD0, 0x07, 0xD4, 0x7F, 0xF0,
+	0x52, 0xAF, 0xF9, 0x34, 0xAD, 0x7B, 0xFE, 0xBF, 0x6C, 0x7F, 0xF4, 0xA1, 0x6B, 0xF3, 0x2A, 0xBF,
+	0x4D, 0x7F, 0xE0, 0xA5, 0x5F, 0xF2, 0x69, 0x5A, 0xF7, 0xFD, 0x7E, 0xD8, 0xFF, 0x00, 0xE9, 0x42,
+	0xD7, 0xE6, 0x55, 0x00, 0x14, 0x51, 0x45, 0x00, 0x15, 0xF7, 0x1F, 0xFC, 0x12, 0x0F, 0xFE, 0x45,
+	0xBF, 0x1D, 0x7F, 0xD7, 0xFD, 0x8F, 0xFE, 0x8A, 0xB8, 0xAF, 0x87, 0x2B, 0xEE, 0x3F, 0xF8, 0x24,
+	0x1F, 0xFC, 0x8B, 0x7E, 0x3A, 0xFF, 0x00, 0xAF, 0xFB, 0x1F, 0xFD, 0x15, 0x71, 0x40, 0x0B, 0xFF,
+	0x00, 0x05, 0x80, 0xFF, 0x00, 0x90, 0x07, 0x81, 0x7F, 0xEB, 0xF6, 0xFB, 0xFF, 0x00, 0x40, 0x8E,
+	0xBE, 0x1B, 0xAF, 0xB9, 0x3F, 0xE0, 0xB0, 0x1F, 0xF2, 0x00, 0xF0, 0x2F, 0xFD, 0x7E, 0xDF, 0x7F,
+	0xE8, 0x11, 0xD7, 0xC3, 0x74, 0x00, 0x51, 0x45, 0x14, 0x00, 0x57, 0xE9, 0xA7, 0xFC, 0x13, 0x57,
+	0xFE, 0x4D, 0x1F, 0x43, 0xFF, 0x00, 0xAF, 0xEB, 0xFF, 0x00, 0xFD, 0x29, 0x6A, 0xFC, 0xCB, 0xAF,
+	0xD3, 0x4F, 0xF8, 0x26, 0xAF, 0xFC, 0x9A, 0x3E, 0x87, 0xFF, 0x00, 0x5F, 0xD7, 0xFF, 0x00, 0xFA,
+	0x52, 0xD4, 0x01, 0xF2, 0xEF, 0xFC, 0x15, 0x5F, 0xFE, 0x4E, 0x5A, 0x2F, 0xFB, 0x15, 0x6D, 0x7F,
+	0xF4, 0x64, 0xD5, 0xF3, 0x69, 0xEB, 0x5F, 0x49, 0x7F, 0xC1, 0x55, 0xFF, 0x00, 0xE4, 0xE5, 0xA2,
+	0xFF, 0x00, 0xB1, 0x56, 0xD7, 0xFF, 0x00, 0x46, 0x4D, 0x5F, 0x36, 0x9E, 0xB4, 0x00, 0x51, 0x45,
+	0x14, 0x00, 0xD7, 0xFE, 0x2F, 0xF7, 0xBF, 0xF6, 0x55, 0xAF, 0xD8, 0xAF, 0x81, 0xFF, 0x00, 0xF2,
+	0x45, 0x7C, 0x1F, 0xFF, 0x00, 0x62, 0xBE, 0x9F, 0xFF, 0x00, 0xA4, 0xD1, 0xD7, 0xE3, 0xAB, 0xFF,
+	0x00, 0x17, 0xFB, 0xDF, 0xFB, 0x2A, 0xD7, 0xEC, 0x57, 0xC0, 0xFF, 0x00, 0xF9, 0x22, 0xBE, 0x0F,
+	0xFF, 0x00, 0xB1, 0x5F, 0x4F, 0xFF, 0x00, 0xD2, 0x68, 0xE8, 0x03, 0xF3, 0x27, 0xF6, 0xD3, 0xFF,
+	0x00, 0x93, 0xAE, 0xF1, 0xB7, 0xFD, 0x87, 0x0F, 0xFE, 0x82, 0xB5, 0xE5, 0x89, 0xF7, 0x07, 0xD2,
+	0xBD, 0x4F, 0xF6, 0xD3, 0xFF, 0x00, 0x93, 0xAE, 0xF1, 0xB7, 0xFD, 0x87, 0x0F, 0xFE, 0x82, 0xB5,
+	0xE5, 0x89, 0xF7, 0x07, 0xD2, 0x80, 0x16, 0x8A, 0x28, 0xA0, 0x02, 0xBE, 0xF4, 0xFF, 0x00, 0x82,
+	0x42, 0xFF, 0x00, 0xC9, 0x35, 0xF1, 0x87, 0xFD, 0x87, 0x20, 0xFF, 0x00, 0xD1, 0x35, 0xF0, 0x5D,
+	0x7D, 0xE9, 0xFF, 0x00, 0x04, 0x85, 0xFF, 0x00, 0x92, 0x6B, 0xE3, 0x0F, 0xFB, 0x0E, 0x41, 0xFF,
+	0x00, 0xA2, 0x68, 0x03, 0xC7, 0xBF, 0xE0, 0xAA, 0x3F, 0xF2, 0x73, 0x36, 0xFF, 0x00, 0xF6, 0x2C,
+	0x5A, 0xFF, 0x00, 0xE8, 0x72, 0xD7, 0xCD, 0x95, 0xF4, 0x9F, 0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66,
+	0xDF, 0xFE, 0xC5, 0x8B, 0x5F, 0xFD, 0x0E, 0x5A, 0xF9, 0xB2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0E,
+	0xDF, 0x85, 0x7D, 0xD1, 0xFF, 0x00, 0x04, 0x80, 0xFF, 0x00, 0x91, 0x73, 0xC7, 0xDF, 0xF6, 0x10,
+	0xB0, 0xFF, 0x00, 0xD1, 0x73, 0x57, 0xC2, 0xFD, 0xBF, 0x0A, 0xFB, 0xA3, 0xFE, 0x09, 0x01, 0xFF,
+	0x00, 0x22, 0xE7, 0x8F, 0xBF, 0xEC, 0x21, 0x61, 0xFF, 0x00, 0xA2, 0xE6, 0xA0, 0x0F, 0x2A, 0xFF,
+	0x00, 0x82, 0xA8, 0xFF, 0x00, 0xC9, 0xCC, 0xDB, 0xFF, 0x00, 0xD8, 0xB1, 0x6B, 0xFF, 0x00, 0xA1,
+	0xCB, 0x5F, 0x36, 0x57, 0xD2, 0x7F, 0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B, 0x7F, 0xFB, 0x16, 0x2D,
+	0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x3B, 0x7E, 0x15, 0xF7, 0x37,
+	0xFC, 0x12, 0x0F, 0xFE, 0x45, 0xFF, 0x00, 0x1D, 0xFF, 0x00, 0xD8, 0x4B, 0x4F, 0xFF, 0x00, 0xD1,
+	0x72, 0xD7, 0xC3, 0x3D, 0xBF, 0x0A, 0xFB, 0x9B, 0xFE, 0x09, 0x07, 0xFF, 0x00, 0x22, 0xFF, 0x00,
+	0x8E, 0xFF, 0x00, 0xEC, 0x25, 0xA7, 0xFF, 0x00, 0xE8, 0xB9, 0x68, 0x03, 0xEC, 0xB8, 0x3F, 0xD5,
+	0xFE, 0x34, 0xFA, 0x64, 0x1F, 0xEA, 0xFF, 0x00, 0x1A, 0x7D, 0x00, 0x14, 0x1E, 0x94, 0x50, 0xC7,
+	0xE5, 0x34, 0x01, 0xF0, 0xA7, 0xFC, 0x15, 0xF7, 0xFE, 0x46, 0x4F, 0x03, 0xFF, 0x00, 0xD7, 0x95,
+	0xF7, 0xFE, 0x8C, 0x8E, 0xBE, 0x36, 0xAF, 0xD1, 0x2F, 0xDB, 0xE3, 0xF6, 0x55, 0xF8, 0xA3, 0xFB,
+	0x4E, 0x6B, 0xDE, 0x1A, 0x9B, 0xE1, 0xD5, 0xCE, 0x96, 0xA3, 0x45, 0xB6, 0xB9, 0x5B, 0xA5, 0xD4,
+	0xAE, 0x4C, 0x7F, 0xEB, 0x5A, 0x32, 0xB8, 0xF9, 0x09, 0xFE, 0x0A, 0xF0, 0x1F, 0xF8, 0x75, 0x5F,
+	0xED, 0x3D, 0xFF, 0x00, 0x3F, 0x9E, 0x15, 0xFF, 0x00, 0xC1, 0xA4, 0xBF, 0xFC, 0x45, 0x00, 0x7C,
+	0xD7, 0x45, 0x7D, 0x29, 0xFF, 0x00, 0x0E, 0xAB, 0xFD, 0xA7, 0xBF, 0xE7, 0xF3, 0xC2, 0xBF, 0xF8,
+	0x34, 0x97, 0xFF, 0x00, 0x88, 0xA3, 0xFE, 0x1D, 0x57, 0xFB, 0x4F, 0x7F, 0xCF, 0xE7, 0x85, 0x7F,
+	0xF0, 0x69, 0x2F, 0xFF, 0x00, 0x11, 0x40, 0x1F, 0x35, 0x8E, 0xB5, 0xF5, 0x77, 0xFC, 0x12, 0x4B,
+	0xFE, 0x4B, 0x3F, 0x89, 0xBF, 0xEC, 0x53, 0x5F, 0xFD, 0x29, 0x8A, 0xB1, 0x0F, 0xFC, 0x12, 0xB3,
+	0xF6, 0x9F, 0x03, 0x3F, 0x6D, 0xF0, 0xB7, 0xE1, 0xAA, 0x4B, 0xFF, 0x00, 0xC4, 0x57, 0xB8, 0xFE,
+	0xC2, 0x9F, 0xB1, 0xC7, 0xC5, 0xAF, 0xD9, 0xBF, 0xE2, 0x3E, 0xB1, 0xE2, 0x9F, 0x88, 0x37, 0x3A,
+	0x3C, 0xB6, 0xF7, 0xDA, 0x4B, 0x5A, 0x47, 0xFD, 0x9B, 0x74, 0xF2, 0x30, 0x3E, 0x74, 0x52, 0x73,
+	0xB9, 0x07, 0xA5, 0x00, 0x59, 0xFF, 0x00, 0x82, 0xB4, 0x7F, 0xC9, 0xBA, 0x69, 0x1F, 0xF6, 0x3B,
+	0x5B, 0xFF, 0x00, 0xE9, 0x25, 0xD5, 0x7E, 0x79, 0x57, 0xEA, 0x07, 0xED, 0xE1, 0xFB, 0x3F, 0xF8,
+	0xE3, 0xF6, 0x8C, 0xF8, 0x4F, 0xA6, 0xF8, 0x1F, 0xE1, 0xEB, 0xD8, 0xC7, 0x79, 0x6B, 0xE2, 0x38,
+	0x6F, 0x24, 0x6D, 0x42, 0x6D, 0x91, 0x98, 0xD2, 0xDE, 0x74, 0x3F, 0xC2, 0x7F, 0xE7, 0xB0, 0xAF,
+	0x94, 0xFF, 0x00, 0xE1, 0xD5, 0x7F, 0xB4, 0xF7, 0xFC, 0xFE, 0x78, 0x57, 0xFF, 0x00, 0x06, 0x92,
+	0xFF, 0x00, 0xF1, 0x14, 0x01, 0xF3, 0x5D, 0x15, 0xF4, 0xA7, 0xFC, 0x3A, 0xAF, 0xF6, 0x9E, 0xFF,
+	0x00, 0x9F, 0xCF, 0x0A, 0xFF, 0x00, 0xE0, 0xD2, 0x5F, 0xFE, 0x22, 0x8F, 0xF8, 0x75, 0x5F, 0xED,
+	0x3D, 0xFF, 0x00, 0x3F, 0x9E, 0x15, 0xFF, 0x00, 0xC1, 0xA4, 0xBF, 0xFC, 0x45, 0x00, 0x7C, 0xD7,
+	0x5E, 0xF5, 0xFF, 0x00, 0x04, 0xD8, 0xFF, 0x00, 0x93, 0xB9, 0xD0, 0x7F, 0xEC, 0x1F, 0xA8, 0x7F,
+	0xE9, 0x3B, 0xD6, 0xD7, 0xFC, 0x3A, 0xAF, 0xF6, 0x9E, 0xFF, 0x00, 0x9F, 0xCF, 0x0A, 0xFF, 0x00,
+	0xE0, 0xD2, 0x5F, 0xFE, 0x22, 0xBD, 0x33, 0xF6, 0x43, 0xFD, 0x83, 0x7E, 0x37, 0xFC, 0x0B, 0xF8,
+	0xED, 0xA6, 0xFC, 0x47, 0xF1, 0xB5, 0xE6, 0x85, 0x25, 0x95, 0x9D, 0xAC, 0xE9, 0x22, 0xD8, 0xDF,
+	0x3B, 0xC9, 0xFB, 0xCB, 0x77, 0x4F, 0xE2, 0x4A, 0x00, 0xF6, 0x2F, 0xF8, 0x28, 0x8F, 0xFC, 0x99,
+	0xD7, 0x8C, 0x3F, 0xDC, 0xD3, 0xFF, 0x00, 0xF4, 0xBE, 0xDE, 0xBF, 0x2F, 0x6B, 0xF5, 0x8F, 0xF6,
+	0xBB, 0xF8, 0x55, 0xE2, 0x4F, 0x8D, 0x7F, 0xB3, 0xEE, 0xBD, 0xF0, 0xCF, 0xC1, 0x86, 0xDD, 0x35,
+	0x2D, 0x4B, 0xEC, 0xBF, 0x65, 0x6B, 0xC9, 0x36, 0x27, 0xC9, 0x77, 0x0C, 0xC7, 0x3C, 0x1E, 0xD1,
+	0x9E, 0xD5, 0xF1, 0x78, 0xFF, 0x00, 0x82, 0x55, 0xFE, 0xD3, 0xB8, 0xE2, 0xF7, 0xC2, 0xBF, 0xF8,
+	0x33, 0x93, 0xFF, 0x00, 0x88, 0xA0, 0x0F, 0x9B, 0x28, 0xAF, 0xA5, 0x3F, 0xE1, 0xD5, 0x7F, 0xB4,
+	0xF7, 0xFC, 0xFE, 0x78, 0x57, 0xFF, 0x00, 0x06, 0x92, 0xFF, 0x00, 0xF1, 0x14, 0x7F, 0xC3, 0xAA,
+	0xFF, 0x00, 0x69, 0xEF, 0xF9, 0xFC, 0xF0, 0xAF, 0xFE, 0x0D, 0x25, 0xFF, 0x00, 0xE2, 0x28, 0x03,
+	0xE6, 0xBA, 0xF4, 0x4F, 0xD9, 0x2B, 0xFE, 0x4E, 0x73, 0xC0, 0x3F, 0xF6, 0x35, 0x5A, 0x7F, 0xE8,
+	0x42, 0xBD, 0x43, 0xFE, 0x1D, 0x57, 0xFB, 0x4F, 0x7F, 0xCF, 0xE7, 0x85, 0x7F, 0xF0, 0x69, 0x2F,
+	0xFF, 0x00, 0x11, 0x5D, 0x57, 0xC0, 0xCF, 0xF8, 0x27, 0x1F, 0xED, 0x07, 0xF0, 0xE3, 0xE3, 0x27,
+	0x86, 0x3C, 0x79, 0xE2, 0x2B, 0xEF, 0x0E, 0xB5, 0x9E, 0x91, 0xAC, 0x5B, 0xDD, 0xCC, 0x96, 0xFA,
+	0x84, 0x8D, 0x26, 0xD8, 0xE5, 0x07, 0x8C, 0xA7, 0xBD, 0x00, 0x7D, 0x8F, 0xF1, 0xB7, 0xFE, 0x48,
+	0xC7, 0x8B, 0x3F, 0xEC, 0x57, 0xD4, 0x3F, 0xF4, 0x43, 0xD7, 0xE3, 0xD5, 0x7E, 0xC7, 0xFC, 0x4A,
+	0xF0, 0xFD, 0xD7, 0x8A, 0xFE, 0x1A, 0xEB, 0x9E, 0x18, 0xD3, 0x16, 0x31, 0x71, 0xA9, 0x68, 0xB7,
+	0x56, 0xD0, 0x34, 0xCF, 0xB5, 0x43, 0xC9, 0x0B, 0x46, 0x32, 0x7D, 0x3E, 0x6A, 0xF8, 0x13, 0xFE,
+	0x1D, 0x59, 0xFB, 0x4F, 0xF7, 0xBC, 0xF0, 0xB7, 0xE3, 0xA9, 0x48, 0x3F, 0xF6, 0x4A, 0x00, 0xF9,
+	0xAE, 0x8A, 0xFA, 0x53, 0xFE, 0x1D, 0x57, 0xFB, 0x4F, 0x7F, 0xCF, 0xE7, 0x85, 0x7F, 0xF0, 0x69,
+	0x2F, 0xFF, 0x00, 0x11, 0x47, 0xFC, 0x3A, 0xAF, 0xF6, 0x9E, 0xFF, 0x00, 0x9F, 0xCF, 0x0A, 0xFF,
+	0x00, 0xE0, 0xD2, 0x5F, 0xFE, 0x22, 0x95, 0xC0, 0xF9, 0xAE, 0xBE, 0x92, 0xFF, 0x00, 0x82, 0x56,
+	0xFF, 0x00, 0xC9, 0xCD, 0x4F, 0xFF, 0x00, 0x62, 0xB5, 0xF7, 0xFE, 0x8D, 0xB7, 0xA7, 0x7F, 0xC3,
+	0xAA, 0xFF, 0x00, 0x69, 0xEF, 0xF9, 0xFC, 0xF0, 0xAF, 0xFE, 0x0D, 0x25, 0xFF, 0x00, 0xE2, 0x2B,
+	0xD7, 0xBF, 0x62, 0x4F, 0xD8, 0x93, 0xE3, 0x4F, 0xEC, 0xEF, 0xF1, 0x9A, 0x6F, 0x1E, 0xF8, 0xEE,
+	0xE3, 0x45, 0x92, 0xCA, 0x4D, 0x16, 0x5B, 0x35, 0x5D, 0x3E, 0xF1, 0xE4, 0x6D, 0xCD, 0x22, 0x37,
+	0x42, 0x9F, 0xEC, 0x53, 0xD0, 0x0F, 0x43, 0xFF, 0x00, 0x82, 0x95, 0x7F, 0xC9, 0xA5, 0x6B, 0xDF,
+	0xF5, 0xFB, 0x63, 0xFF, 0x00, 0xA5, 0x0B, 0x5F, 0x99, 0x55, 0xFA, 0xB5, 0xFB, 0x5E, 0xFC, 0x1F,
+	0xF1, 0x7F, 0xC7, 0x2F, 0x80, 0xFA, 0x9F, 0xC3, 0x8F, 0x07, 0x3D, 0xA2, 0x5F, 0x5E, 0x5C, 0x5B,
+	0x49, 0x6F, 0xF6, 0xE9, 0xB6, 0x27, 0xEE, 0xE5, 0x49, 0x0E, 0x7E, 0x4F, 0xF6, 0x6B, 0xE3, 0x81,
+	0xFF, 0x00, 0x04, 0xAC, 0xFD, 0xA7, 0x08, 0xCA, 0x5E, 0x78, 0x57, 0x6F, 0x6D, 0xBA, 0x9C, 0x98,
+	0xFD, 0x12, 0x80, 0x3E, 0x6C, 0xA2, 0xBE, 0x94, 0xFF, 0x00, 0x87, 0x55, 0xFE, 0xD3, 0xDF, 0xF3,
+	0xF9, 0xE1, 0x5F, 0xFC, 0x1A, 0x4B, 0xFF, 0x00, 0xC4, 0x51, 0xFF, 0x00, 0x0E, 0xAB, 0xFD, 0xA7,
+	0xBF, 0xE7, 0xF3, 0xC2, 0xBF, 0xF8, 0x34, 0x97, 0xFF, 0x00, 0x88, 0xA0, 0x0F, 0x9A, 0xEB, 0xEE,
+	0x3F, 0xF8, 0x24, 0x1F, 0xFC, 0x8B, 0x7E, 0x3A, 0xFF, 0x00, 0xAF, 0xFB, 0x1F, 0xFD, 0x15, 0x71,
+	0x5E, 0x61, 0xFF, 0x00, 0x0E, 0xAB, 0xFD, 0xA7, 0xBF, 0xE7, 0xF3, 0xC2, 0xBF, 0xF8, 0x34, 0x97,
+	0xFF, 0x00, 0x88, 0xAF, 0xA4, 0xBF, 0x60, 0x4F, 0xD9, 0x8F, 0xE2, 0x47, 0xEC, 0xD3, 0xA5, 0xF8,
+	0x9A, 0xCF, 0xE2, 0x3C, 0xDA, 0x6B, 0x49, 0xAB, 0x5D, 0x5A, 0xBD, 0xAF, 0xF6, 0x6C, 0xE6, 0x41,
+	0x88, 0xC3, 0xA9, 0xCE, 0x7F, 0xDE, 0xA0, 0x0F, 0x3D, 0xFF, 0x00, 0x82, 0xC0, 0x7F, 0xC8, 0x03,
+	0xC0, 0xBF, 0xF5, 0xFB, 0x7D, 0xFF, 0x00, 0xA0, 0x47, 0x5F, 0x0D, 0xD7, 0xE9, 0x3F, 0xED, 0xED,
+	0xFB, 0x31, 0xFC, 0x47, 0xFD, 0xA6, 0xB4, 0x8F, 0x0E, 0x58, 0xFC, 0x3C, 0x7D, 0x36, 0x36, 0xD2,
+	0x6E, 0xAE, 0x24, 0xB8, 0x6D, 0x4A, 0x67, 0x8F, 0x2B, 0x22, 0xC6, 0x06, 0x30, 0x87, 0xFB, 0x95,
+	0xF3, 0x67, 0xFC, 0x3A, 0xB3, 0xF6, 0x9E, 0x3C, 0xFD, 0xB7, 0xC2, 0xBF, 0xF8, 0x34, 0x97, 0xFF,
+	0x00, 0x88, 0xA0, 0x0F, 0x9A, 0xE8, 0xAF, 0xA5, 0x3F, 0xE1, 0xD5, 0x7F, 0xB4, 0xF7, 0xFC, 0xFE,
+	0x78, 0x57, 0xFF, 0x00, 0x06, 0x92, 0xFF, 0x00, 0xF1, 0x14, 0x7F, 0xC3, 0xAA, 0xFF, 0x00, 0x69,
+	0xEF, 0xF9, 0xFC, 0xF0, 0xAF, 0xFE, 0x0D, 0x25, 0xFF, 0x00, 0xE2, 0x28, 0x03, 0xE6, 0xBA, 0xFD,
+	0x34, 0xFF, 0x00, 0x82, 0x6A, 0xFF, 0x00, 0xC9, 0xA3, 0xE8, 0x7F, 0xF5, 0xFD, 0x7F, 0xFF, 0x00,
+	0xA5, 0x2D, 0x5F, 0x2F, 0xFF, 0x00, 0xC3, 0xAA, 0xFF, 0x00, 0x69, 0xEF, 0xF9, 0xFC, 0xF0, 0xAF,
+	0xFE, 0x0D, 0x25, 0xFF, 0x00, 0xE2, 0x2B, 0xEC, 0x8F, 0xD8, 0xF7, 0xE1, 0x07, 0x8A, 0xBE, 0x07,
+	0x7C, 0x09, 0xD3, 0x7E, 0x1A, 0xF8, 0xE5, 0xAD, 0x5B, 0x50, 0xB3, 0xBA, 0xB8, 0x79, 0xBE, 0xC3,
+	0x31, 0x74, 0x2B, 0x24, 0xCC, 0xCB, 0xD4, 0x7B, 0xD0, 0x07, 0xC6, 0xBF, 0xF0, 0x55, 0x7F, 0xF9,
+	0x39, 0x68, 0xBF, 0xEC, 0x55, 0xB5, 0xFF, 0x00, 0xD1, 0x93, 0x57, 0xCD, 0xA7, 0xAD, 0x7D, 0xE9,
+	0xFB, 0x6E, 0xFE, 0xC4, 0xDF, 0x18, 0xFF, 0x00, 0x68, 0x3F, 0x8C, 0x91, 0xF8, 0xFB, 0xC0, 0xF7,
+	0x5A, 0x2A, 0x59, 0xC5, 0xA3, 0xDB, 0xDB, 0xB7, 0xF6, 0x95, 0xD3, 0xA3, 0x6F, 0x8A, 0x49, 0x9B,
+	0x8F, 0x90, 0xFF, 0x00, 0xCF, 0x4A, 0xF1, 0xF1, 0xFF, 0x00, 0x04, 0xAB, 0xFD, 0xA7, 0xF1, 0xCD,
+	0xEF, 0x85, 0xBF, 0xF0, 0x69, 0x2F, 0xFF, 0x00, 0x11, 0x40, 0x1F, 0x35, 0xD1, 0x5F, 0x4A, 0x7F,
+	0xC3, 0xAA, 0xFF, 0x00, 0x69, 0xEF, 0xF9, 0xFC, 0xF0, 0xAF, 0xFE, 0x0D, 0x25, 0xFF, 0x00, 0xE2,
+	0x28, 0xFF, 0x00, 0x87, 0x55, 0xFE, 0xD3, 0xDF, 0xF3, 0xF9, 0xE1, 0x5F, 0xFC, 0x1A, 0x4B, 0xFF,
+	0x00, 0xC4, 0x50, 0x07, 0xCD, 0x2F, 0xFC, 0x5F, 0xEF, 0x7F, 0xEC, 0xAB, 0x5F, 0xB1, 0x5F, 0x03,
+	0xFF, 0x00, 0xE4, 0x8A, 0xF8, 0x3F, 0xFE, 0xC5, 0x7D, 0x3F, 0xFF, 0x00, 0x49, 0xA3, 0xAF, 0x82,
+	0xC7, 0xFC, 0x12, 0xBF, 0xF6, 0x9B, 0x8D, 0xF7, 0x9B, 0xDF, 0x0B, 0xE7, 0xE5, 0x2D, 0xFF, 0x00,
+	0x13, 0x49, 0x7E, 0xE8, 0x3F, 0xF5, 0xCA, 0xBF, 0x40, 0x3E, 0x19, 0xF8, 0x7A, 0xFF, 0x00, 0xC2,
+	0x3F, 0x0D, 0xFC, 0x3F, 0xE1, 0x4D, 0x54, 0xC6, 0x6E, 0xB4, 0xBD, 0x0E, 0xD2, 0xD2, 0xE0, 0xC2,
+	0xC5, 0x90, 0xC9, 0x1C, 0x2A, 0x8D, 0xB4, 0x90, 0x32, 0x32, 0x0E, 0x0E, 0x07, 0x14, 0x01, 0xF9,
+	0x7B, 0xFB, 0x69, 0xFF, 0x00, 0xC9, 0xD7, 0x78, 0xDB, 0xFE, 0xC3, 0x87, 0xFF, 0x00, 0x41, 0x5A,
+	0xF2, 0xC4, 0xFB, 0x83, 0xE9, 0x5F, 0x63, 0xFE, 0xD1, 0xDF, 0xF0, 0x4E, 0xEF, 0x8F, 0x7F, 0x14,
+	0xBE, 0x38, 0xF8, 0x9B, 0xE2, 0x37, 0x85, 0xAF, 0x7C, 0x3A, 0xB6, 0x5A, 0xA6, 0xA5, 0xF6, 0x9B,
+	0x31, 0x75, 0xA9, 0x48, 0xAC, 0x00, 0x5C, 0x7C, 0xC0, 0x44, 0x70, 0x7D, 0x46, 0x4F, 0x35, 0xC6,
+	0x9F, 0xF8, 0x25, 0x57, 0xED, 0x3A, 0x38, 0x5B, 0xCF, 0x0A, 0xE3, 0xB7, 0xFC, 0x4D, 0x25, 0xFF,
+	0x00, 0xE3, 0x74, 0x01, 0xF3, 0x5D, 0x15, 0xF4, 0xA7, 0xFC, 0x3A, 0xAF, 0xF6, 0x9E, 0xFF, 0x00,
+	0x9F, 0xCF, 0x0A, 0xFF, 0x00, 0xE0, 0xD2, 0x5F, 0xFE, 0x22, 0x95, 0x7F, 0xE0, 0x95, 0x3F, 0xB4,
+	0xBB, 0x38, 0x49, 0x75, 0x1F, 0x0A, 0x8C, 0xFF, 0x00, 0x13, 0x6A, 0x92, 0xE1, 0x7F, 0xF2, 0x5C,
+	0xFF, 0x00, 0x33, 0x40, 0x1E, 0x0D, 0xF0, 0xD7, 0xFE, 0x4A, 0x37, 0x87, 0x3F, 0xEC, 0x35, 0x6B,
+	0xFF, 0x00, 0xA5, 0x29, 0x5F, 0xB1, 0xCC, 0xCD, 0x82, 0xC0, 0x2E, 0xE0, 0xD8, 0x5D, 0xCD, 0xB7,
+	0x77, 0x1C, 0x0F, 0xCE, 0xBE, 0x4D, 0xFD, 0x9F, 0x3F, 0xE0, 0x97, 0x9E, 0x12, 0xF0, 0x3D, 0xF5,
+	0xA7, 0x8C, 0xFE, 0x32, 0x78, 0x8E, 0x4D, 0x5B, 0x54, 0xB3, 0x9A, 0x39, 0x60, 0xB0, 0xD3, 0x64,
+	0x30, 0xDA, 0x43, 0x22, 0x9C, 0x83, 0xBC, 0x81, 0x24, 0x84, 0x1F, 0xFA, 0xE6, 0xA7, 0xD0, 0xD7,
+	0xD6, 0xD1, 0x9C, 0xC6, 0xA7, 0xFD, 0x9A, 0x00, 0xF8, 0x67, 0xE0, 0xC7, 0xFC, 0x12, 0x77, 0x5A,
+	0xB8, 0x30, 0x6A, 0xDF, 0x1B, 0x7C, 0x72, 0xB6, 0xB0, 0xED, 0x0C, 0x74, 0x9D, 0x0D, 0x4B, 0x4C,
+	0xC3, 0xFB, 0xAF, 0x24, 0x80, 0xC6, 0xBD, 0xB3, 0xB6, 0x27, 0x6F, 0xF6, 0xC7, 0x5A, 0xFA, 0x93,
+	0xE1, 0x07, 0xEC, 0xCB, 0xF0, 0x4B, 0xE0, 0x94, 0x51, 0xC9, 0xE0, 0x1F, 0x87, 0x36, 0x56, 0xF7,
+	0x51, 0xAF, 0x3A, 0x94, 0xCA, 0x6E, 0x2E, 0x88, 0xF5, 0xF3, 0xE5, 0x25, 0x87, 0xFB, 0xAA, 0x48,
+	0xF4, 0xAF, 0x44, 0xA2, 0x80, 0x11, 0x3E, 0xE0, 0xFA, 0x52, 0xD1, 0x45, 0x00, 0x14, 0x51, 0x5F,
+	0xCF, 0x47, 0xFC, 0x17, 0xE7, 0xFE, 0x0A, 0x7B, 0xFB, 0x7E, 0x7E, 0xCC, 0x9F, 0xF0, 0x53, 0xEF,
+	0x1A, 0xFC, 0x20, 0xF8, 0x0D, 0xFB, 0x53, 0x78, 0x9B, 0xC2, 0xFE, 0x19, 0xB1, 0xD2, 0x74, 0x79,
+	0x6D, 0x74, 0x5D, 0x2E, 0x68, 0xC4, 0x31, 0xB4, 0xD6, 0x10, 0x3C, 0x8F, 0xCA, 0x13, 0x92, 0xC4,
+	0xF7, 0xA4, 0xE5, 0x14, 0x8D, 0x29, 0xD3, 0x75, 0x25, 0x64, 0x7F, 0x42, 0xF4, 0x57, 0xF2, 0x3B,
+	0xFF, 0x00, 0x0F, 0xC2, 0xFF, 0x00, 0x82, 0xB3, 0x37, 0x23, 0xF6, 0xE9, 0xF1, 0xC7, 0xFC, 0x0A,
+	0xE6, 0x2F, 0xFE, 0x37, 0x47, 0xFC, 0x3F, 0x07, 0xFE, 0x0A, 0xCD, 0xFF, 0x00, 0x47, 0xD5, 0xE3,
+	0x8F, 0xFC, 0x0A, 0x8B, 0xFF, 0x00, 0x8D, 0xD4, 0x7B, 0x58, 0x9B, 0x7D, 0x52, 0xA1, 0xFD, 0x71,
+	0x51, 0x5F, 0xC8, 0xEF, 0xFC, 0x3F, 0x07, 0xFE, 0x0A, 0xCD, 0xFF, 0x00, 0x47, 0xD5, 0xE3, 0x8F,
+	0xFC, 0x0A, 0x8B, 0xFF, 0x00, 0x8D, 0xD1, 0xFF, 0x00, 0x0F, 0xC1, 0xFF, 0x00, 0x82, 0xB3, 0x7F,
+	0xD1, 0xF5, 0x78, 0xE3, 0xFF, 0x00, 0x02, 0xA2, 0xFF, 0x00, 0xE3, 0x74, 0x7B, 0x58, 0x87, 0xD4,
+	0xEA, 0x1F, 0xD7, 0x15, 0x15, 0xFC, 0x8E, 0xFF, 0x00, 0xC3, 0xF0, 0x7F, 0xE0, 0xAC, 0xDF, 0xF4,
+	0x7D, 0x5E, 0x38, 0xFF, 0x00, 0xC0, 0xA8, 0xBF, 0xF8, 0xDD, 0x1F, 0xF0, 0xFC, 0x1F, 0xF8, 0x2B,
+	0x37, 0xFD, 0x1F, 0x57, 0x8E, 0x3F, 0xF0, 0x2A, 0x2F, 0xFE, 0x37, 0x47, 0xB5, 0x88, 0x7D, 0x4E,
+	0xA1, 0xFD, 0x71, 0x51, 0x5F, 0xC8, 0xEF, 0xFC, 0x3F, 0x07, 0xFE, 0x0A, 0xCD, 0xFF, 0x00, 0x47,
+	0xD5, 0xE3, 0x8F, 0xFC, 0x0A, 0x8B, 0xFF, 0x00, 0x8D, 0xD1, 0xFF, 0x00, 0x0F, 0xC1, 0xFF, 0x00,
+	0x82, 0xB3, 0x7F, 0xD1, 0xF5, 0x78, 0xE3, 0xFF, 0x00, 0x02, 0xA2, 0xFF, 0x00, 0xE3, 0x74, 0x7B,
+	0x58, 0x87, 0xD4, 0xEA, 0x1F, 0xD7, 0x15, 0x15, 0xFC, 0x8E, 0xFF, 0x00, 0xC3, 0xF0, 0x7F, 0xE0,
+	0xAC, 0xDF, 0xF4, 0x7D, 0x5E, 0x38, 0xFF, 0x00, 0xC0, 0xA8, 0xBF, 0xF8, 0xDD, 0x1F, 0xF0, 0xFC,
+	0x1F, 0xF8, 0x2B, 0x37, 0xFD, 0x1F, 0x57, 0x8E, 0x3F, 0xF0, 0x2A, 0x2F, 0xFE, 0x37, 0x47, 0xB5,
+	0x88, 0x7D, 0x4E, 0xA1, 0xFD, 0x71, 0x51, 0x5F, 0xC8, 0xEF, 0xFC, 0x3F, 0x07, 0xFE, 0x0A, 0xCD,
+	0xFF, 0x00, 0x47, 0xD5, 0xE3, 0x8F, 0xFC, 0x0A, 0x8B, 0xFF, 0x00, 0x8D, 0xD1, 0xFF, 0x00, 0x0F,
+	0xC1, 0xFF, 0x00, 0x82, 0xB3, 0x7F, 0xD1, 0xF5, 0x78, 0xE3, 0xFF, 0x00, 0x02, 0xA2, 0xFF, 0x00,
+	0xE3, 0x74, 0x7B, 0x58, 0x87, 0xD4, 0xEA, 0x1F, 0xD7, 0x15, 0x15, 0xFC, 0x8E, 0xFF, 0x00, 0xC3,
+	0xF0, 0x7F, 0xE0, 0xAC, 0xDF, 0xF4, 0x7D, 0x5E, 0x38, 0xFF, 0x00, 0xC0, 0xA8, 0xBF, 0xF8, 0xDD,
+	0x1F, 0xF0, 0xFC, 0x1F, 0xF8, 0x2B, 0x37, 0xFD, 0x1F, 0x57, 0x8E, 0x3F, 0xF0, 0x2A, 0x2F, 0xFE,
+	0x37, 0x47, 0xB5, 0x88, 0x7D, 0x4E, 0xA1, 0xFD, 0x71, 0x51, 0x5F, 0xC8, 0xEF, 0xFC, 0x3F, 0x07,
+	0xFE, 0x0A, 0xCD, 0xFF, 0x00, 0x47, 0xD5, 0xE3, 0x8F, 0xFC, 0x0A, 0x8B, 0xFF, 0x00, 0x8D, 0xD1,
+	0xFF, 0x00, 0x0F, 0xC1, 0xFF, 0x00, 0x82, 0xB3, 0x7F, 0xD1, 0xF5, 0x78, 0xE3, 0xFF, 0x00, 0x02,
+	0xA2, 0xFF, 0x00, 0xE3, 0x74, 0x7B, 0x58, 0x87, 0xD4, 0xEA, 0x1F, 0xD7, 0x15, 0x15, 0xFC, 0x8E,
+	0xA7, 0xFC, 0x16, 0xF7, 0xFE, 0x0A, 0xCA, 0xED, 0x98, 0xFF, 0x00, 0x6E, 0x5F, 0x1C, 0x3B, 0x2F,
+	0x29, 0xFE, 0x91, 0x16, 0x5D, 0xF3, 0xC7, 0xFC, 0xB3, 0xFB, 0xB9, 0xF9, 0x4D, 0x7F, 0x5C, 0x11,
+	0x7F, 0xAA, 0x5C, 0x36, 0xEF, 0x97, 0xEF, 0x7A, 0xD5, 0x46, 0x4A, 0x46, 0x35, 0x29, 0xCA, 0x9D,
+	0xAE, 0x3A, 0x8A, 0x28, 0xAA, 0x33, 0x39, 0x1F, 0x89, 0xBF, 0x03, 0xBE, 0x14, 0x7C, 0x63, 0xB2,
+	0x6B, 0x1F, 0x88, 0xFE, 0x01, 0xD3, 0x75, 0x4C, 0xA9, 0x58, 0xEE, 0x2E, 0x2C, 0xC7, 0xDA, 0x22,
+	0xF7, 0x49, 0x87, 0xCC, 0x9F, 0x85, 0x7C, 0xB3, 0xF1, 0x93, 0xFE, 0x09, 0x41, 0xA6, 0xCC, 0x66,
+	0xD5, 0xBE, 0x0A, 0x78, 0xEE, 0x4B, 0x26, 0x0A, 0x5D, 0x74, 0xAD, 0x6B, 0x33, 0x2B, 0x37, 0x5C,
+	0x24, 0xC3, 0x07, 0xEE, 0x8C, 0x61, 0x90, 0x9F, 0x56, 0x27, 0x26, 0xBE, 0xD4, 0xA2, 0x80, 0x23,
+	0x83, 0x22, 0x3C, 0x10, 0x3F, 0x0F, 0xC6, 0xBF, 0x1E, 0xFE, 0x38, 0x7F, 0xC9, 0x6A, 0xF1, 0x87,
+	0xFD, 0x8D, 0x1A, 0x87, 0xFE, 0x94, 0xC9, 0x5F, 0xB0, 0xCF, 0xB5, 0xD5, 0x94, 0xAE, 0x7E, 0x5C,
+	0x32, 0xFA, 0x83, 0x5F, 0x33, 0x7E, 0xD1, 0x1F, 0xF0, 0x4D, 0x4F, 0x86, 0x5F, 0x16, 0xB5, 0x4B,
+	0xDF, 0x18, 0x7C, 0x3F, 0xD6, 0x26, 0xF0, 0xEE, 0xBD, 0x7B, 0x34, 0x93, 0xCE, 0xAE, 0xAD, 0x35,
+	0x9D, 0xD4, 0xAC, 0xC5, 0x98, 0xBA, 0xE4, 0x32, 0x31, 0x62, 0x49, 0x65, 0x63, 0xFE, 0xEF, 0x6A,
+	0x00, 0xFC, 0xEA, 0xA2, 0xBE, 0x98, 0xB8, 0xFF, 0x00, 0x82, 0x54, 0xFE, 0xD3, 0x22, 0x4D, 0x91,
+	0x6A, 0xDE, 0x15, 0x65, 0x1C, 0x2B, 0x2E, 0xA9, 0x37, 0x23, 0xD7, 0x98, 0xB3, 0xF9, 0xF3, 0x51,
+	0x9F, 0xF8, 0x25, 0x5F, 0xED, 0x3D, 0x9F, 0xF8, 0xFD, 0xF0, 0xAF, 0xFE, 0x0D, 0x25, 0xFF, 0x00,
+	0xE3, 0x74, 0x01, 0xF3, 0x5D, 0x7A, 0x27, 0xEC, 0x95, 0xFF, 0x00, 0x27, 0x39, 0xE0, 0x1F, 0xFB,
+	0x1A, 0xAD, 0x3F, 0xF4, 0x21, 0x5E, 0xA1, 0xFF, 0x00, 0x0E, 0xAB, 0xFD, 0xA7, 0xBF, 0xE7, 0xF3,
+	0xC2, 0xBF, 0xF8, 0x34, 0x97, 0xFF, 0x00, 0x88, 0xAE, 0xAB, 0xE0, 0x67, 0xFC, 0x13, 0x8F, 0xF6,
+	0x83, 0xF8, 0x71, 0xF1, 0x93, 0xC3, 0x1E, 0x3C, 0xF1, 0x15, 0xF7, 0x87, 0x5A, 0xCF, 0x48, 0xD6,
+	0x2D, 0xEE, 0xE6, 0x4B, 0x7D, 0x42, 0x46, 0x93, 0x6C, 0x72, 0x83, 0xC6, 0x53, 0xDE, 0x80, 0x3E,
+	0xC7, 0xF8, 0xDB, 0xFF, 0x00, 0x24, 0x63, 0xC5, 0x9F, 0xF6, 0x2B, 0xEA, 0x1F, 0xFA, 0x21, 0xEB,
+	0xF1, 0xEA, 0xBF, 0x63, 0xFE, 0x25, 0x78, 0x7E, 0xEB, 0xC5, 0x7F, 0x0D, 0x35, 0xCF, 0x0B, 0xE9,
+	0x8B, 0x18, 0xB8, 0xD4, 0xB4, 0x5B, 0xAB, 0x78, 0x1A, 0x66, 0xDA, 0xA1, 0xE4, 0x85, 0xA3, 0x19,
+	0x38, 0xE9, 0xF3, 0x57, 0xC0, 0x9F, 0xF0, 0xEA, 0xCF, 0xDA, 0x7F, 0xBD, 0xE7, 0x85, 0xBF, 0x1D,
+	0x4A, 0x41, 0xFF, 0x00, 0xB2, 0x50, 0x07, 0xCD, 0x74, 0x57, 0xD2, 0x9F, 0xF0, 0xEA, 0xBF, 0xDA,
+	0x7B, 0xFE, 0x7F, 0x3C, 0x2B, 0xFF, 0x00, 0x83, 0x49, 0x7F, 0xF8, 0x8A, 0x3F, 0xE1, 0xD5, 0x7F,
+	0xB4, 0xF7, 0xFC, 0xFE, 0x78, 0x57, 0xFF, 0x00, 0x06, 0x92, 0xFF, 0x00, 0xF1, 0x14, 0x01, 0xF3,
+	0x5D, 0x7D, 0x25, 0xFF, 0x00, 0x04, 0xAD, 0xFF, 0x00, 0x93, 0x9A, 0x9F, 0xFE, 0xC5, 0x6B, 0xEF,
+	0xFD, 0x1B, 0x6F, 0x4E, 0xFF, 0x00, 0x87, 0x55, 0xFE, 0xD3, 0xDF, 0xF3, 0xF9, 0xE1, 0x5F, 0xFC,
+	0x1A, 0x4B, 0xFF, 0x00, 0xC4, 0x57, 0xAF, 0x7E, 0xC4, 0x9F, 0xB1, 0x27, 0xC6, 0x9F, 0xD9, 0xDF,
+	0xE3, 0x2C, 0xDE, 0x3D, 0xF1, 0xDC, 0xFA, 0x2C, 0x96, 0x32, 0x68, 0xB2, 0xD9, 0xAA, 0xE9, 0xF7,
+	0x8F, 0x23, 0x6E, 0x69, 0x11, 0xBA, 0x14, 0xFF, 0x00, 0x62, 0x80, 0x3D, 0x0F, 0xFE, 0x0A, 0x55,
+	0xFF, 0x00, 0x26, 0x95, 0xAF, 0x7F, 0xD7, 0xED, 0x8F, 0xFE, 0x94, 0x2D, 0x7E, 0x65, 0x57, 0xEA,
+	0xDF, 0xED, 0x7B, 0xF0, 0x83, 0xC5, 0xFF, 0x00, 0x1C, 0xFE, 0x03, 0x6A, 0x7F, 0x0E, 0x3C, 0x1C,
+	0xF6, 0x69, 0x7D, 0x79, 0x71, 0x6D, 0x25, 0xBF, 0xDB, 0xA6, 0xD8, 0x9F, 0xBB, 0x95, 0x24, 0x39,
+	0xF9, 0x3F, 0xD9, 0xAF, 0x8D, 0xD7, 0xFE, 0x09, 0x59, 0xFB, 0x4E, 0x11, 0x94, 0xBC, 0xF0, 0xAE,
+	0xDE, 0xDB, 0x75, 0x49, 0x3F, 0xA2, 0x50, 0x07, 0xCD, 0x94, 0x57, 0xD2, 0x9F, 0xF0, 0xEA, 0xBF,
+	0xDA, 0x7B, 0xFE, 0x7F, 0x3C, 0x2B, 0xFF, 0x00, 0x83, 0x49, 0x7F, 0xF8, 0x8A, 0x3F, 0xE1, 0xD5,
+	0x7F, 0xB4, 0xF7, 0xFC, 0xFE, 0x78, 0x57, 0xFF, 0x00, 0x06, 0x92, 0xFF, 0x00, 0xF1, 0x14, 0x01,
+	0xF3, 0x5D, 0x7D, 0xC7, 0xFF, 0x00, 0x04, 0x83, 0xFF, 0x00, 0x91, 0x6F, 0xC7, 0x5F, 0xF5, 0xFF,
+	0x00, 0x63, 0xFF, 0x00, 0xA2, 0xAE, 0x2B, 0xCC, 0x3F, 0xE1, 0xD5, 0x7F, 0xB4, 0xF7, 0xFC, 0xFE,
+	0x78, 0x57, 0xFF, 0x00, 0x06, 0x92, 0xFF, 0x00, 0xF1, 0x15, 0xF4, 0x97, 0xEC, 0x09, 0xFB, 0x31,
+	0xFC, 0x48, 0xFD, 0x9A, 0x74, 0xBF, 0x13, 0x59, 0xFC, 0x46, 0x9B, 0x4D, 0x69, 0x35, 0x6B, 0xAB,
+	0x57, 0xB5, 0xFE, 0xCD, 0x9C, 0xB8, 0xC4, 0x6A, 0xEA, 0x73, 0x9F, 0xF7, 0xA8, 0x03, 0xCF, 0x7F,
+	0xE0, 0xB0, 0x1F, 0xF2, 0x00, 0xF0, 0x2F, 0xFD, 0x7E, 0xDF, 0x7F, 0xE8, 0x11, 0xD7, 0xC3, 0x75,
+	0xFA, 0x4F, 0xFB, 0x7B, 0x7E, 0xCC, 0x7F, 0x11, 0xFF, 0x00, 0x69, 0xAD, 0x23, 0xC3, 0x96, 0x3F,
+	0x0E, 0xDB, 0x4D, 0x8D, 0xB4, 0x9B, 0xAB, 0x89, 0x2E, 0x1B, 0x52, 0x99, 0xE3, 0xCA, 0xC8, 0x23,
+	0x03, 0x18, 0x43, 0xFD, 0xCA, 0xF9, 0xB3, 0xFE, 0x1D, 0x59, 0xFB, 0x4F, 0x1E, 0x7E, 0xDB, 0xE1,
+	0x5F, 0xFC, 0x1A, 0x4B, 0xFF, 0x00, 0xC4, 0x50, 0x07, 0xCD, 0x74, 0x57, 0xD2, 0x9F, 0xF0, 0xEA,
+	0xBF, 0xDA, 0x7B, 0xFE, 0x7F, 0x3C, 0x2B, 0xFF, 0x00, 0x83, 0x49, 0x7F, 0xF8, 0x8A, 0x3F, 0xE1,
+	0xD5, 0x7F, 0xB4, 0xF7, 0xFC, 0xFE, 0x78, 0x57, 0xFF, 0x00, 0x06, 0x92, 0xFF, 0x00, 0xF1, 0x14,
+	0x01, 0xF3, 0x5D, 0x7E, 0x9A, 0x7F, 0xC1, 0x35, 0x4F, 0xFC, 0x62, 0x3E, 0x87, 0xFF, 0x00, 0x5F,
+	0xD7, 0xFF, 0x00, 0xFA, 0x52, 0xD5, 0xF2, 0xFF, 0x00, 0xFC, 0x3A, 0xAF, 0xF6, 0x9E, 0xFF, 0x00,
+	0x9F, 0xCF, 0x0A, 0xFF, 0x00, 0xE0, 0xD2, 0x5F, 0xFE, 0x22, 0xBE, 0xC7, 0xFD, 0x8F, 0xBE, 0x10,
+	0x78, 0xAB, 0xE0, 0x77, 0xC0, 0x9D, 0x37, 0xE1, 0xAF, 0x8E, 0x5A, 0xD5, 0xB5, 0x0B, 0x3B, 0xAB,
+	0x87, 0x97, 0xEC, 0x33, 0x17, 0x42, 0xB2, 0x4C, 0xCC, 0xBD, 0x47, 0xBD, 0x3B, 0x58, 0x3D, 0x4F,
+	0x8D, 0xBF, 0xE0, 0xAA, 0xFF, 0x00, 0xF2, 0x72, 0xD1, 0x7F, 0xD8, 0xAB, 0x6B, 0xFF, 0x00, 0xA3,
+	0x26, 0xAF, 0x9B, 0x4F, 0x5A, 0xFB, 0xCF, 0xF6, 0xDC, 0xFD, 0x89, 0xBE, 0x31, 0xFE, 0xD0, 0x7F,
+	0x19, 0x23, 0xF1, 0xEF, 0x81, 0xEE, 0xB4, 0x54, 0xB3, 0x8B, 0x47, 0xB7, 0xB7, 0x6F, 0xED, 0x2B,
+	0xA7, 0x46, 0xDF, 0x14, 0x93, 0x37, 0x1F, 0x21, 0xC7, 0xFA, 0xCF, 0x5A, 0xF1, 0xFF, 0x00, 0xF8,
+	0x75, 0x67, 0xED, 0x3E, 0x07, 0xCD, 0x7B, 0xE1, 0x6F, 0xFC, 0x1A, 0x4B, 0xFF, 0x00, 0xC4, 0x52,
+	0xD3, 0xB8, 0x1F, 0x36, 0x51, 0x5F, 0x49, 0xFF, 0x00, 0xC3, 0xAB, 0x7F, 0x69, 0xEF, 0xF9, 0xFC,
+	0xF0, 0xB7, 0xFE, 0x0D, 0x25, 0xFF, 0x00, 0xE2, 0x28, 0xFF, 0x00, 0x87, 0x56, 0x7E, 0xD3, 0xDF,
+	0xF3, 0xF9, 0xE1, 0x6F, 0xFC, 0x1A, 0x4B, 0xFF, 0x00, 0xC4, 0x50, 0x07, 0xCD, 0x4F, 0xFC, 0x5F,
+	0xEF, 0x7F, 0xEC, 0xAB, 0x5F, 0xB1, 0x5F, 0x03, 0xFF, 0x00, 0xE4, 0x8A, 0xF8, 0x3F, 0xFE, 0xC5,
+	0x7D, 0x3F, 0xFF, 0x00, 0x49, 0xA3, 0xAF, 0x82, 0xBF, 0xE1, 0xD6, 0x1F, 0xB4, 0xD4, 0x4F, 0xBC,
+	0xDF, 0x78, 0x5F, 0x76, 0x54, 0xB7, 0xFC, 0x4D, 0x25, 0xE8, 0x0F, 0xFD, 0x72, 0xAF, 0xD0, 0x1F,
+	0x86, 0x5E, 0x1E, 0xBE, 0xF0, 0x97, 0xC3, 0x8F, 0x0F, 0xF8, 0x53, 0x54, 0x31, 0x9B, 0xAD, 0x2F,
+	0x43, 0xB4, 0xB4, 0xB8, 0x30, 0xB1, 0x64, 0x32, 0x47, 0x0A, 0xA3, 0x6D, 0x24, 0x02, 0x46, 0x41,
+	0xC7, 0x03, 0x8A, 0x03, 0x73, 0xF2, 0xF7, 0xF6, 0xD3, 0xFF, 0x00, 0x93, 0xAE, 0xF1, 0xB7, 0xFD,
+	0x87, 0x0F, 0xFE, 0x82, 0xB5, 0xE5, 0x89, 0xF7, 0x07, 0xD2, 0xBE, 0xC7, 0xFD, 0xA3, 0xBF, 0xE0,
+	0x9D, 0xDF, 0x1E, 0xFE, 0x29, 0xFC, 0x71, 0xF1, 0x37, 0xC4, 0x6F, 0x0A, 0xDE, 0xF8, 0x75, 0x6C,
+	0xB5, 0x4D, 0x4B, 0xED, 0x36, 0x62, 0xEB, 0x52, 0x91, 0x58, 0x00, 0xB8, 0xF9, 0x80, 0x88, 0xE0,
+	0xF3, 0xCF, 0x27, 0x9A, 0xE3, 0x4F, 0xFC, 0x12, 0xAB, 0xF6, 0x9D, 0x1C, 0x2D, 0xE7, 0x85, 0x71,
+	0xDB, 0xFE, 0x26, 0x92, 0xFF, 0x00, 0xF1, 0xBA, 0x00, 0xF9, 0xAE, 0x8A, 0xFA, 0x53, 0xFE, 0x1D,
+	0x57, 0xFB, 0x4F, 0x7F, 0xCF, 0xE7, 0x85, 0x7F, 0xF0, 0x69, 0x2F, 0xFF, 0x00, 0x11, 0x47, 0xFC,
+	0x3A, 0xAF, 0xF6, 0x9E, 0xFF, 0x00, 0x9F, 0xCF, 0x0A, 0xFF, 0x00, 0xE0, 0xD2, 0x5F, 0xFE, 0x22,
+	0x80, 0x3E, 0x6B, 0xAF, 0xBD, 0x3F, 0xE0, 0x90, 0xBF, 0xF2, 0x4D, 0x7C, 0x61, 0xFF, 0x00, 0x61,
+	0xC8, 0x3F, 0xF4, 0x4D, 0x78, 0xFF, 0x00, 0xFC, 0x3A, 0xAF, 0xF6, 0x9E, 0xFF, 0x00, 0x9F, 0xCF,
+	0x0A, 0xFF, 0x00, 0xE0, 0xD2, 0x5F, 0xFE, 0x22, 0xBE, 0x9B, 0xFD, 0x81, 0x7F, 0x67, 0x8F, 0x1F,
+	0x7E, 0xCD, 0xBE, 0x17, 0xF1, 0x27, 0x86, 0x7E, 0x21, 0x4B, 0x61, 0x25, 0xD5, 0xF5, 0xF4, 0x17,
+	0x51, 0xFF, 0x00, 0x67, 0x4C, 0x64, 0x50, 0xBB, 0x19, 0x3D, 0x33, 0xFC, 0x3E, 0x94, 0x01, 0xF3,
+	0x1F, 0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B, 0x5F, 0xFD, 0x0E, 0x5A, 0xF9,
+	0xB2, 0xBE, 0xEF, 0xFD, 0xB6, 0x3F, 0x62, 0x9F, 0x8C, 0xDF, 0xB4, 0x77, 0xC6, 0xA4, 0xF1, 0xD7,
+	0x80, 0x6E, 0xF4, 0x55, 0xB3, 0x83, 0x46, 0x86, 0xCA, 0x41, 0xA8, 0x5E, 0x14, 0x6F, 0x31, 0x1E,
+	0x46, 0x3D, 0x13, 0x3F, 0xC7, 0x5E, 0x49, 0xFF, 0x00, 0x0E, 0xAB, 0xFD, 0xA7, 0xBF, 0xE7, 0xF3,
+	0xC2, 0xBF, 0xF8, 0x34, 0x97, 0xFF, 0x00, 0x88, 0xA0, 0x0F, 0x9A, 0xE8, 0xAF, 0xA5, 0x3F, 0xE1,
+	0xD5, 0x7F, 0xB4, 0xF7, 0xFC, 0xFE, 0x78, 0x57, 0xFF, 0x00, 0x06, 0x92, 0xFF, 0x00, 0xF1, 0x14,
+	0x7F, 0xC3, 0xAA, 0xFF, 0x00, 0x69, 0xEF, 0xF9, 0xFC, 0xF0, 0xAF, 0xFE, 0x0D, 0x25, 0xFF, 0x00,
+	0xE2, 0x28, 0x03, 0xE6, 0xBE, 0xDF, 0x85, 0x7D, 0xD1, 0xFF, 0x00, 0x04, 0x80, 0xFF, 0x00, 0x91,
+	0x73, 0xC7, 0xDF, 0xF6, 0x10, 0xB0, 0xFF, 0x00, 0xD1, 0x73, 0x57, 0x95, 0xAF, 0xFC, 0x12, 0xB7,
+	0xF6, 0x9E, 0x57, 0x53, 0xF6, 0xEF, 0x0B, 0x8F, 0x98, 0x72, 0x35, 0x49, 0x7D, 0x7F, 0xDC, 0xAF,
+	0xA5, 0x7F, 0x60, 0x0F, 0xD9, 0x8F, 0xE2, 0x1F, 0xEC, 0xCF, 0xA1, 0xF8, 0x9E, 0xCF, 0xE2, 0x1C,
+	0xFA, 0x6C, 0x93, 0x6A, 0xD3, 0xDA, 0xBD, 0xB9, 0xD2, 0xE6, 0x69, 0x17, 0x6C, 0x42, 0x55, 0x39,
+	0xCA, 0x83, 0x9F, 0x98, 0x7A, 0xD0, 0x07, 0xCD, 0x3F, 0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B, 0x7F,
+	0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0xFB, 0xBF, 0xF6, 0xD8, 0xFD, 0x8A, 0x7E,
+	0x33, 0x7E, 0xD1, 0xDF, 0x1A, 0x93, 0xC7, 0x5E, 0x01, 0xBB, 0xD1, 0x56, 0xCE, 0x0D, 0x1A, 0x1B,
+	0x29, 0x06, 0xA1, 0x78, 0x51, 0xBC, 0xC4, 0x79, 0x18, 0xF4, 0x4C, 0xFF, 0x00, 0x1D, 0x79, 0x27,
+	0xFC, 0x3A, 0xAF, 0xF6, 0x9E, 0xFF, 0x00, 0x9F, 0xCF, 0x0A, 0xFF, 0x00, 0xE0, 0xD2, 0x5F, 0xFE,
+	0x22, 0x80, 0x3E, 0x6B, 0xA2, 0xBE, 0x94, 0xFF, 0x00, 0x87, 0x55, 0xFE, 0xD3, 0xDF, 0xF3, 0xF9,
+	0xE1, 0x5F, 0xFC, 0x1A, 0x4B, 0xFF, 0x00, 0xC4, 0x51, 0xFF, 0x00, 0x0E, 0xAB, 0xFD, 0xA7, 0xBF,
+	0xE7, 0xF3, 0xC2, 0xBF, 0xF8, 0x34, 0x97, 0xFF, 0x00, 0x88, 0xA0, 0x0F, 0x9A, 0xFB, 0x7E, 0x15,
+	0xF7, 0x37, 0xFC, 0x12, 0x0F, 0xFE, 0x45, 0xFF, 0x00, 0x1D, 0xFF, 0x00, 0xD8, 0x4B, 0x4F, 0xFF,
+	0x00, 0xD1, 0x72, 0xD7, 0x96, 0xAF, 0xFC, 0x12, 0xB7, 0xF6, 0x9E, 0x57, 0x53, 0xF6, 0xEF, 0x0B,
+	0x8F, 0x98, 0x72, 0x35, 0x49, 0x7D, 0x7F, 0xDC, 0xAF, 0xA4, 0xBF, 0x60, 0x5F, 0xD9, 0x83, 0xE2,
+	0x37, 0xEC, 0xD7, 0xA5, 0x78, 0x8B, 0x4F, 0xF8, 0x89, 0x36, 0x99, 0x2B, 0xEA, 0xF7, 0x16, 0xCD,
+	0x09, 0xD3, 0x2E, 0x1A, 0x40, 0x3C, 0xB5, 0x99, 0x79, 0xCA, 0x0F, 0xEF, 0x7A, 0xD0, 0x07, 0xD1,
+	0x70, 0x7F, 0xAB, 0xFC, 0x69, 0xF4, 0xC8, 0x00, 0xC3, 0x30, 0x5C, 0x6E, 0x6E, 0x79, 0xFC, 0x3F,
+	0xA5, 0x3E, 0x80, 0x0A, 0x47, 0x1B, 0x94, 0xA9, 0xEE, 0x29, 0x69, 0x1C, 0x06, 0x42, 0xA4, 0x76,
+	0xA0, 0x0F, 0x30, 0xF8, 0xCD, 0xFB, 0x4C, 0x7C, 0x23, 0xFD, 0x9E, 0x75, 0x9B, 0x38, 0x3E, 0x2A,
+	0x78, 0x82, 0x5D, 0x3F, 0xFB, 0x4E, 0xD7, 0x7D, 0xA2, 0xC3, 0x63, 0x2C, 0xD9, 0xF2, 0xDF, 0x0C,
+	0x3E, 0x41, 0x8F, 0xE3, 0x51, 0xD2, 0xB8, 0xFF, 0x00, 0xF8, 0x79, 0x67, 0xEC, 0x87, 0xFF, 0x00,
+	0x43, 0xDE, 0xA1, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x37, 0x5E, 0x27, 0xFF, 0x00, 0x05, 0x7B,
+	0x05, 0x7C, 0x43, 0xE0, 0x50, 0xC7, 0x27, 0xEC, 0x37, 0xDC, 0xFF, 0x00, 0xC0, 0xE3, 0xAF, 0x8D,
+	0xE8, 0x03, 0xF4, 0xD3, 0xFE, 0x1E, 0x59, 0xFB, 0x21, 0xFF, 0x00, 0xD0, 0xF7, 0xA8, 0x7F, 0xE0,
+	0x86, 0xE3, 0xFF, 0x00, 0x8D, 0xD1, 0xFF, 0x00, 0x0F, 0x2C, 0xFD, 0x90, 0xFF, 0x00, 0xE8, 0x7B,
+	0xD4, 0x3F, 0xF0, 0x43, 0x71, 0xFF, 0x00, 0xC6, 0xEB, 0xF3, 0x2E, 0x8A, 0x00, 0xFD, 0x34, 0x7F,
+	0xF8, 0x29, 0x5F, 0xEC, 0x8A, 0xC8, 0x42, 0xF8, 0xEE, 0xFF, 0x00, 0x38, 0xE3, 0xFE, 0x24, 0x57,
+	0x23, 0xF9, 0x47, 0x9F, 0xCA, 0xBA, 0xFF, 0x00, 0x83, 0x1F, 0xB5, 0x7F, 0xC1, 0x3F, 0x8F, 0xDA,
+	0xFD, 0xCF, 0x86, 0x7E, 0x16, 0x78, 0x92, 0xE6, 0xF6, 0xEA, 0xC6, 0xD3, 0xED, 0x37, 0x0B, 0x36,
+	0x9B, 0x34, 0x3B, 0x61, 0x12, 0x04, 0x07, 0x32, 0x20, 0x27, 0x93, 0x5F, 0x93, 0x83, 0xAD, 0x7D,
+	0x61, 0xFF, 0x00, 0x04, 0x8F, 0xFF, 0x00, 0x92, 0xD5, 0xE2, 0x5F, 0xFB, 0x15, 0x57, 0xFF, 0x00,
+	0x4A, 0x62, 0xA0, 0x0F, 0xB3, 0x3E, 0x34, 0x7C, 0x6E, 0xF8, 0x7B, 0xF0, 0x17, 0xC3, 0x96, 0xFE,
+	0x31, 0xF8, 0x97, 0xAD, 0x3D, 0x8E, 0x9F, 0x71, 0x7C, 0x2C, 0xD6, 0x58, 0xED, 0xDE, 0x6F, 0xDE,
+	0x98, 0xE4, 0x90, 0x64, 0x27, 0x23, 0x88, 0xDE, 0xBC, 0xDF, 0xFE, 0x1E, 0x59, 0xFB, 0x21, 0xFF,
+	0x00, 0xD0, 0xF7, 0xA8, 0x7F, 0xE0, 0x86, 0xE3, 0xFF, 0x00, 0x8D, 0xD7, 0x31, 0xFF, 0x00, 0x05,
+	0x65, 0xFF, 0x00, 0x93, 0x71, 0xD1, 0xFF, 0x00, 0xEC, 0x73, 0xB5, 0xFF, 0x00, 0xD2, 0x5B, 0xDA,
+	0xFC, 0xF2, 0xA0, 0x0F, 0xD3, 0x4F, 0xF8, 0x79, 0x67, 0xEC, 0x87, 0xFF, 0x00, 0x43, 0xDE, 0xA1,
+	0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x37, 0x47, 0xFC, 0x3C, 0xB3, 0xF6, 0x43, 0xFF, 0x00, 0xA1,
+	0xEF, 0x50, 0xFF, 0x00, 0xC1, 0x0D, 0xC7, 0xFF, 0x00, 0x1B, 0xAF, 0xCC, 0xBA, 0x28, 0x03, 0xF4,
+	0xD3, 0xFE, 0x1E, 0x59, 0xFB, 0x21, 0xFF, 0x00, 0xD0, 0xF7, 0xA8, 0x7F, 0xE0, 0x86, 0xE3, 0xFF,
+	0x00, 0x8D, 0xD6, 0xFF, 0x00, 0xC2, 0xBF, 0xDB, 0x4F, 0xF6, 0x7D, 0xF8, 0xCB, 0xE3, 0x1B, 0x6F,
+	0x87, 0xBF, 0x0F, 0x3C, 0x57, 0x75, 0x77, 0xAA, 0xDD, 0x47, 0x23, 0xC3, 0x0C, 0x9A, 0x5D, 0xC4,
+	0x43, 0x08, 0x9B, 0xDF, 0xE7, 0x95, 0x2B, 0xF2, 0xB2, 0xBD, 0xEB, 0xFE, 0x09, 0xB1, 0xFF, 0x00,
+	0x27, 0x73, 0xA0, 0xFF, 0x00, 0xD8, 0x3F, 0x50, 0xFF, 0x00, 0xD2, 0x77, 0xA0, 0x0F, 0xD1, 0x2F,
+	0x8A, 0x3F, 0x12, 0x3C, 0x29, 0xF0, 0x93, 0xC1, 0x97, 0x7F, 0x10, 0x7C, 0x6F, 0xA8, 0xB5, 0xAE,
+	0x97, 0xA7, 0xB4, 0x42, 0xEA, 0x68, 0xE2, 0x69, 0x08, 0x12, 0x4A, 0x91, 0x2E, 0x55, 0x79, 0xFB,
+	0xCE, 0xBD, 0x2B, 0xC9, 0xD3, 0xFE, 0x0A, 0x5B, 0xFB, 0x21, 0x95, 0x07, 0xFE, 0x13, 0xEB, 0xE6,
+	0xE3, 0xEF, 0x2E, 0x83, 0x71, 0xCF, 0xFE, 0x39, 0x57, 0xFF, 0x00, 0xE0, 0xA2, 0x3F, 0xF2, 0x67,
+	0x7E, 0x31, 0xFF, 0x00, 0x72, 0xCB, 0xFF, 0x00, 0x4E, 0x16, 0xB5, 0xF9, 0x79, 0x40, 0x1F, 0xA6,
+	0x9F, 0xF0, 0xF2, 0xCF, 0xD9, 0x0F, 0xFE, 0x87, 0xBD, 0x43, 0xFF, 0x00, 0x04, 0x37, 0x1F, 0xFC,
+	0x6E, 0x8F, 0xF8, 0x79, 0x67, 0xEC, 0x87, 0xFF, 0x00, 0x43, 0xDE, 0xA1, 0xFF, 0x00, 0x82, 0x1B,
+	0x8F, 0xFE, 0x37, 0x5F, 0x99, 0x74, 0x50, 0x07, 0xE9, 0xA7, 0xFC, 0x3C, 0xB3, 0xF6, 0x43, 0xFF,
+	0x00, 0xA1, 0xEF, 0x50, 0xFF, 0x00, 0xC1, 0x0D, 0xC7, 0xFF, 0x00, 0x1B, 0xAD, 0x0F, 0x06, 0x7E,
+	0xDF, 0x3F, 0xB3, 0x2F, 0x8F, 0x7C, 0x57, 0xA7, 0xF8, 0x2B, 0xC2, 0xDE, 0x32, 0xBC, 0x9F, 0x52,
+	0xD5, 0xAF, 0x23, 0xB7, 0xB2, 0x85, 0xB4, 0x7B, 0x95, 0x0D, 0x2B, 0x92, 0x17, 0xE6, 0x74, 0xDA,
+	0x38, 0x1F, 0x4A, 0xFC, 0xBB, 0xAF, 0x44, 0xFD, 0x92, 0xBF, 0xE4, 0xE7, 0x3C, 0x03, 0xFF, 0x00,
+	0x63, 0x55, 0xA7, 0xFE, 0x84, 0x28, 0x03, 0xF5, 0x53, 0xC6, 0xBE, 0x29, 0xD1, 0xFC, 0x0B, 0xE0,
+	0xFD, 0x4F, 0xC6, 0x9E, 0x24, 0x9D, 0xA3, 0xB0, 0xD1, 0xB4, 0xE9, 0xAF, 0xAF, 0xA4, 0x8D, 0x77,
+	0x30, 0x86, 0x18, 0xD9, 0xE4, 0xC2, 0xF7, 0xF9, 0x55, 0xAB, 0xC1, 0xD7, 0xFE, 0x0A, 0xB1, 0xFB,
+	0x1F, 0x2A, 0x80, 0xDE, 0x24, 0xD6, 0x33, 0x8E, 0x7F, 0xE2, 0x43, 0x27, 0xF4, 0xAF, 0x52, 0xFD,
+	0xA9, 0xBF, 0xE4, 0xD9, 0x3E, 0x22, 0xFF, 0x00, 0xD8, 0x8B, 0xAB, 0xFF, 0x00, 0xE9, 0x04, 0xF5,
+	0xF8, 0xC3, 0x58, 0xD4, 0x9B, 0x8D, 0xAC, 0x5C, 0x22, 0x8F, 0xD4, 0xDF, 0xF8, 0x7A, 0xC7, 0xEC,
+	0x79, 0xFF, 0x00, 0x43, 0x26, 0xB1, 0xFF, 0x00, 0x82, 0x19, 0x68, 0xFF, 0x00, 0x87, 0xAC, 0xFE,
+	0xC7, 0x9F, 0xF4, 0x32, 0x6B, 0x1F, 0xF8, 0x21, 0x96, 0xBF, 0x2C, 0xA8, 0xAC, 0xBD, 0xB5, 0x42,
+	0xF9, 0x22, 0x7E, 0xA6, 0x7F, 0xC3, 0xD5, 0xFF, 0x00, 0x63, 0xDC, 0xFF, 0x00, 0xC8, 0xCB, 0xAC,
+	0x7F, 0xE0, 0x86, 0x5A, 0xE9, 0xFE, 0x0D, 0xFE, 0xDE, 0x7F, 0xB3, 0xB7, 0xC7, 0xBF, 0x1D, 0x47,
+	0xF0, 0xE7, 0xE1, 0xCE, 0xB7, 0xA8, 0x4D, 0xAA, 0x4D, 0x1C, 0x92, 0x47, 0x15, 0xCE, 0x9B, 0x24,
+	0x20, 0xAA, 0x2E, 0xF2, 0x73, 0xF8, 0xD7, 0xE4, 0x65, 0x7D, 0x19, 0xFF, 0x00, 0x04, 0xAA, 0xFF,
+	0x00, 0x93, 0xC5, 0xD2, 0xBF, 0xEC, 0x0F, 0x7F, 0xFF, 0x00, 0xA2, 0x1A, 0xAA, 0x35, 0xA5, 0x29,
+	0x22, 0x65, 0x15, 0x63, 0xF4, 0x5F, 0xE3, 0xAF, 0xC7, 0xDF, 0x86, 0x5F, 0xB3, 0x97, 0x80, 0xE4,
+	0xF8, 0x8B, 0xF1, 0x4B, 0x50, 0x9A, 0xD7, 0x49, 0x8E, 0xEA, 0x3B, 0x57, 0x96, 0xDE, 0xD6, 0x49,
+	0x98, 0xB3, 0x8F, 0x94, 0x61, 0x79, 0xAF, 0x1B, 0x3F, 0xF0, 0x57, 0x7F, 0xD8, 0xC9, 0x3E, 0x46,
+	0xF1, 0x56, 0xB9, 0x95, 0xE0, 0xFF, 0x00, 0xC5, 0x3F, 0x37, 0xF5, 0x15, 0x4B, 0xFE, 0x0B, 0x14,
+	0x7F, 0xE3, 0x0E, 0x66, 0xFF, 0x00, 0xB1, 0x9A, 0xCB, 0xF9, 0x4B, 0x5F, 0x94, 0x27, 0xAD, 0x7B,
+	0x78, 0x3C, 0x1D, 0x3A, 0xD4, 0xB9, 0x99, 0xE3, 0xE2, 0xF1, 0x95, 0x28, 0xD4, 0xB2, 0x3F, 0x5B,
+	0x3F, 0xE1, 0xEF, 0x3F, 0xB1, 0x7F, 0xFD, 0x0D, 0x7A, 0xE7, 0xFE, 0x08, 0x25, 0xA3, 0xFE, 0x1E,
+	0xF1, 0xFB, 0x17, 0xFF, 0x00, 0xD0, 0xD7, 0xAE, 0x7F, 0xE0, 0x82, 0x5A, 0xFC, 0x93, 0xA2, 0xBA,
+	0xBF, 0xB3, 0x30, 0xFE, 0x7F, 0x79, 0xCF, 0xFD, 0xA3, 0x88, 0xF2, 0x3F, 0x5A, 0xFF, 0x00, 0xE1,
+	0xEF, 0x3F, 0xB1, 0x87, 0x6F, 0x15, 0xEB, 0x7F, 0xF8, 0x20, 0x96, 0xBD, 0x1F, 0xF6, 0x73, 0xFD,
+	0xAE, 0xFE, 0x0B, 0x7E, 0xD4, 0xF2, 0x6B, 0x43, 0xE1, 0x16, 0xB1, 0x79, 0x75, 0xFD, 0x87, 0x25,
+	0xB8, 0xD4, 0xBE, 0xD7, 0x62, 0xF0, 0x32, 0x89, 0xFC, 0xCF, 0x2F, 0x19, 0xF7, 0x49, 0x2B, 0xF1,
+	0x36, 0xBF, 0x40, 0x3F, 0xE0, 0x85, 0xBF, 0x7F, 0xE2, 0x8F, 0xFB, 0xDA, 0x2F, 0xFE, 0x81, 0x7F,
+	0x5C, 0xF8, 0xAC, 0x15, 0x1A, 0x34, 0x79, 0x91, 0xB6, 0x1B, 0x1B, 0x56, 0xA5, 0x64, 0x99, 0xF6,
+	0x4F, 0xC6, 0xBF, 0xDA, 0x1B, 0xE1, 0x5F, 0xEC, 0xFB, 0x6B, 0xA7, 0xDF, 0x7C, 0x52, 0xD6, 0xE5,
+	0xB0, 0x8F, 0x53, 0x69, 0x23, 0xB2, 0x64, 0xB6, 0x92, 0x6D, 0xCD, 0x1A, 0x82, 0xDF, 0x77, 0x9E,
+	0x8F, 0x5C, 0x17, 0xFC, 0x3C, 0xAF, 0xF6, 0x45, 0x5F, 0x95, 0xFC, 0x77, 0x7F, 0xB8, 0x7D, 0xEF,
+	0xF8, 0x90, 0xDC, 0x7F, 0xF1, 0x15, 0xE5, 0xFF, 0x00, 0xF0, 0x58, 0x2F, 0xF9, 0x00, 0xF8, 0x17,
+	0xFE, 0xBF, 0xAF, 0xBF, 0xF4, 0x08, 0xEB, 0xE1, 0xBA, 0xF2, 0xCF, 0x58, 0xFD, 0x34, 0xFF, 0x00,
+	0x87, 0x96, 0x7E, 0xC8, 0x7F, 0xF4, 0x3D, 0xEA, 0x1F, 0xF8, 0x21, 0xB8, 0xFF, 0x00, 0xE3, 0x74,
+	0x7F, 0xC3, 0xCB, 0x3F, 0x64, 0x3F, 0xFA, 0x1E, 0xF5, 0x0F, 0xFC, 0x10, 0xDC, 0x7F, 0xF1, 0xBA,
+	0xFC, 0xCB, 0xA2, 0x80, 0x3F, 0x4D, 0x3F, 0xE1, 0xE5, 0x9F, 0xB2, 0x1F, 0xFD, 0x0F, 0x7A, 0x87,
+	0xFE, 0x08, 0x6E, 0x3F, 0xF8, 0xDD, 0x7A, 0xB7, 0xC2, 0xBF, 0x8A, 0xDE, 0x08, 0xF8, 0xD1, 0xE0,
+	0xD8, 0x7C, 0x7D, 0xE0, 0x0B, 0xF9, 0x2E, 0xF4, 0xCB, 0x99, 0x24, 0x5B, 0x79, 0xE5, 0xB7, 0x31,
+	0xFC, 0xD1, 0xB6, 0xD6, 0x04, 0x1E, 0x47, 0x23, 0xBD, 0x7E, 0x3A, 0xD7, 0xE9, 0xA7, 0xFC, 0x13,
+	0x57, 0xFE, 0x4D, 0x1F, 0x43, 0xFF, 0x00, 0xAF, 0xEB, 0xFF, 0x00, 0xFD, 0x29, 0x6A, 0x00, 0xE9,
+	0xBE, 0x2E, 0xFE, 0xD8, 0x5F, 0x01, 0xFE, 0x05, 0xF8, 0xB9, 0x7C, 0x17, 0xF1, 0x1F, 0xC4, 0xF7,
+	0x16, 0x7A, 0xA4, 0x90, 0xC5, 0x32, 0xDB, 0xC5, 0xA7, 0x4F, 0x3F, 0xC9, 0x23, 0x91, 0x9C, 0xAA,
+	0x6D, 0x1F, 0x72, 0xB9, 0x94, 0xFF, 0x00, 0x82, 0x96, 0x7E, 0xC8, 0x61, 0x00, 0x3E, 0x3C, 0xD4,
+	0x3A, 0x7F, 0xD0, 0x0A, 0xE0, 0xFF, 0x00, 0xED, 0x3A, 0xF9, 0x77, 0xFE, 0x0A, 0xAF, 0xFF, 0x00,
+	0x27, 0x2D, 0x17, 0xFD, 0x8A, 0xB6, 0xBF, 0xFA, 0x32, 0x6A, 0xF9, 0xB4, 0xF5, 0xA0, 0x0F, 0xD3,
+	0x4F, 0xF8, 0x79, 0x67, 0xEC, 0x87, 0xFF, 0x00, 0x43, 0xDE, 0xA1, 0xFF, 0x00, 0x82, 0x1B, 0x8F,
+	0xFE, 0x37, 0x47, 0xFC, 0x3C, 0xB3, 0xF6, 0x43, 0xFF, 0x00, 0xA1, 0xEF, 0x50, 0xFF, 0x00, 0xC1,
+	0x0D, 0xC7, 0xFF, 0x00, 0x1B, 0xAF, 0xCC, 0xBA, 0x28, 0x03, 0xF4, 0xD9, 0x3F, 0xE0, 0xA5, 0x3F,
+	0xB2, 0x34, 0x92, 0x04, 0x8F, 0xC7, 0x97, 0xD9, 0xDC, 0x02, 0xFF, 0x00, 0xC4, 0x86, 0xE3, 0xA9,
+	0xFF, 0x00, 0x80, 0x57, 0xB7, 0x78, 0x7B, 0x5D, 0xD3, 0x7C, 0x51, 0xA0, 0x58, 0xF8, 0x97, 0x46,
+	0x9D, 0xA5, 0xB3, 0xD4, 0x6C, 0xE2, 0xBA, 0xB5, 0x91, 0xA3, 0x2A, 0x5E, 0x39, 0x10, 0x32, 0x92,
+	0x08, 0x04, 0x64, 0x11, 0xC1, 0x19, 0x15, 0xF8, 0xB2, 0xFF, 0x00, 0xC5, 0xFE, 0xF7, 0xFE, 0xCA,
+	0xB5, 0xFB, 0x15, 0xF0, 0x3F, 0xFE, 0x48, 0xAF, 0x83, 0xFF, 0x00, 0xEC, 0x57, 0xD3, 0xFF, 0x00,
+	0xF4, 0x9A, 0x3A, 0x00, 0xE0, 0xFC, 0x75, 0xFB, 0x78, 0xFE, 0xCD, 0x7F, 0x0D, 0xFC, 0x67, 0x7D,
+	0xE0, 0x3F, 0x16, 0x78, 0xC6, 0xEA, 0xDF, 0x51, 0xD2, 0xEE, 0xBC, 0x8B, 0xC8, 0x57, 0x49, 0x9D,
+	0x80, 0x63, 0x9E, 0x32, 0x13, 0x07, 0x9E, 0xE2, 0xA1, 0xF0, 0x6F, 0xED, 0xE5, 0xFB, 0x3B, 0xFC,
+	0x45, 0xF1, 0x04, 0x3E, 0x16, 0xF0, 0x46, 0xB3, 0xAB, 0x6A, 0x9A, 0x95, 0xCB, 0x01, 0x1D, 0xA5,
+	0x9F, 0x87, 0x6E, 0xA4, 0x76, 0x07, 0xBB, 0x6D, 0x4F, 0x91, 0x47, 0xF7, 0x9B, 0x8C, 0x57, 0x82,
+	0xF8, 0xC7, 0xF6, 0x06, 0xF8, 0x87, 0xFB, 0x42, 0x7E, 0xD4, 0xBE, 0x31, 0xF1, 0x8E, 0xBF, 0x31,
+	0xD0, 0x3C, 0x2F, 0x26, 0xB4, 0xC2, 0x3B, 0xC9, 0xBE, 0x6B, 0x9B, 0xCC, 0x0E, 0x44, 0x09, 0x91,
+	0x80, 0x7F, 0xBD, 0x95, 0xF5, 0xF9, 0xAB, 0xEA, 0xAF, 0x83, 0x9F, 0x01, 0xFE, 0x15, 0xFC, 0x07,
+	0xD1, 0x06, 0x83, 0xF0, 0xD7, 0xC2, 0xB1, 0xD9, 0xEE, 0x5F, 0xF4, 0xCB, 0xC9, 0x3E, 0x6B, 0xAB,
+	0xB3, 0x9E, 0xB2, 0xCA, 0xD8, 0x63, 0xD3, 0x21, 0x70, 0x14, 0x7F, 0x08, 0x02, 0x80, 0x3B, 0x88,
+	0x0B, 0x98, 0x50, 0xC8, 0xA4, 0x36, 0xD1, 0xB8, 0x36, 0x32, 0x0E, 0x3D, 0xA9, 0xD4, 0x89, 0x9D,
+	0x83, 0x39, 0xE9, 0xDC, 0x52, 0xD0, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45,
+	0x14, 0x50, 0x01, 0x5F, 0xCB, 0x8F, 0xFC, 0x1C, 0xE1, 0x91, 0xFF, 0x00, 0x05, 0x84, 0xF1, 0xF8,
+	0xFF, 0x00, 0xA8, 0x16, 0x81, 0xFF, 0x00, 0xA6, 0xDB, 0x7A, 0xFE, 0xA3, 0xAB, 0xF9, 0x72, 0xFF,
+	0x00, 0x83, 0x9C, 0x7F, 0xE5, 0x30, 0xBF, 0x10, 0x3F, 0xEC, 0x05, 0xE1, 0xFF, 0x00, 0xFD, 0x36,
+	0xDB, 0xD6, 0x75, 0x6D, 0xCA, 0x74, 0xE1, 0x1F, 0xEF, 0x59, 0xF0, 0x05, 0x14, 0x51, 0x5C, 0xE8,
+	0xEF, 0x0A, 0x28, 0xA2, 0x80, 0xD0, 0x28, 0xA2, 0x8A, 0x03, 0x40, 0xA2, 0x8A, 0x28, 0x0D, 0x02,
+	0x8A, 0x28, 0xA0, 0x34, 0x0A, 0x28, 0xA2, 0x80, 0xD0, 0x28, 0xA2, 0x8A, 0x03, 0x40, 0xA2, 0x8A,
+	0x28, 0x0D, 0x01, 0x7A, 0x9F, 0xC3, 0xF9, 0x1A, 0xFE, 0xE2, 0xD4, 0x61, 0x40, 0xAF, 0xE1, 0xD1,
+	0x7A, 0x9F, 0xC3, 0xF9, 0x1A, 0xFE, 0xE3, 0x17, 0xEE, 0xD6, 0xD4, 0x7E, 0x13, 0x8F, 0x15, 0xD0,
+	0x28, 0xA2, 0x8A, 0xD8, 0xE3, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x6B, 0xE5,
+	0x23, 0x2C, 0xA9, 0x9F, 0xF6, 0x3D, 0x69, 0xD4, 0x50, 0x07, 0x93, 0x7C, 0x4B, 0xFD, 0xB3, 0xBE,
+	0x05, 0x7C, 0x1B, 0xD7, 0xFF, 0x00, 0xE1, 0x17, 0xF8, 0x8D, 0xA8, 0xEA, 0xDA, 0x55, 0xE0, 0x66,
+	0xF2, 0xD6, 0x6F, 0x0F, 0xDD, 0x14, 0x93, 0x07, 0x04, 0xA3, 0xAA, 0x10, 0xCB, 0xE8, 0x47, 0x04,
+	0x74, 0xAC, 0xCF, 0x06, 0x7E, 0xDF, 0x3F, 0xB3, 0x27, 0x8F, 0x7C, 0x55, 0xA7, 0xF8, 0x2B, 0xC2,
+	0xDE, 0x31, 0xBC, 0x9B, 0x52, 0xD5, 0xAF, 0x23, 0xB7, 0xB2, 0x85, 0xB4, 0x7B, 0x95, 0x06, 0x47,
+	0x24, 0x28, 0xDD, 0x22, 0x60, 0x70, 0x2B, 0xD2, 0xBE, 0x24, 0x7C, 0x34, 0xF0, 0x27, 0xC5, 0x8F,
+	0x0D, 0xCB, 0xE1, 0x2F, 0x88, 0x7E, 0x1B, 0xB5, 0xD4, 0xF4, 0xF9, 0xB7, 0x06, 0x8A, 0xE6, 0x3C,
+	0xF9, 0x6D, 0xD9, 0x93, 0x3C, 0xAB, 0x7F, 0xB4, 0x2B, 0xE5, 0x19, 0x3F, 0xE0, 0x9D, 0x7E, 0x22,
+	0xF8, 0x3D, 0xFB, 0x42, 0xF8, 0x5F, 0xE2, 0x47, 0xC2, 0xCB, 0xFF, 0x00, 0xED, 0x1F, 0x0D, 0xDA,
+	0xF8, 0x8A, 0xD6, 0xE2, 0xF2, 0xCA, 0xE2, 0x65, 0x17, 0x9A, 0x74, 0x7E, 0x60, 0xC9, 0xF9, 0xBE,
+	0x59, 0xD3, 0x3D, 0xF1, 0xBB, 0x1F, 0xC2, 0xC7, 0xE6, 0xA0, 0x0F, 0xAF, 0xB5, 0xFD, 0x67, 0x4D,
+	0xF0, 0xD6, 0x8B, 0x77, 0xE2, 0x1D, 0x5D, 0x99, 0x6D, 0x74, 0xEB, 0x69, 0x27, 0xBC, 0x68, 0xF9,
+	0x2A, 0x88, 0x9E, 0x63, 0x1C, 0x77, 0xE1, 0x6B, 0xC5, 0x53, 0xFE, 0x0A, 0x59, 0xFB, 0x21, 0x84,
+	0x51, 0xFF, 0x00, 0x09, 0xDD, 0xF7, 0x4E, 0xDA, 0x14, 0xE7, 0xF9, 0x26, 0x3F, 0x2E, 0x2B, 0xD4,
+	0x3E, 0x35, 0x60, 0x7C, 0x14, 0xF1, 0x60, 0x0D, 0xBB, 0xFE, 0x29, 0x6B, 0xFF, 0x00, 0x9B, 0x9E,
+	0x7F, 0x70, 0xFE, 0xB5, 0xF8, 0xF7, 0x40, 0x1F, 0xA6, 0x9F, 0xF0, 0xF2, 0xCF, 0xD9, 0x0F, 0xFE,
+	0x87, 0xBD, 0x43, 0xFF, 0x00, 0x04, 0x37, 0x1F, 0xFC, 0x6E, 0x8F, 0xF8, 0x79, 0x67, 0xEC, 0x87,
+	0xFF, 0x00, 0x43, 0xDE, 0xA1, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x37, 0x5F, 0x99, 0x74, 0x50,
+	0x07, 0xE9, 0xA7, 0xFC, 0x3C, 0xB3, 0xF6, 0x43, 0xFF, 0x00, 0xA1, 0xEF, 0x50, 0xFF, 0x00, 0xC1,
+	0x0D, 0xC7, 0xFF, 0x00, 0x1B, 0xAE, 0x9F, 0xE1, 0x07, 0xED, 0x83, 0xF0, 0x23, 0xE3, 0xAF, 0x8B,
+	0x0F, 0x83, 0x7E, 0x1C, 0xF8, 0x96, 0xE2, 0xF2, 0xF9, 0x6D, 0x24, 0xBA, 0x68, 0x64, 0xD2, 0xE6,
+	0x87, 0x10, 0xAB, 0x6D, 0x27, 0x2E, 0x07, 0x76, 0xAF, 0xCA, 0x4A, 0xFA, 0x4B, 0xFE, 0x09, 0x5B,
+	0xFF, 0x00, 0x27, 0x35, 0x3F, 0xFD, 0x8A, 0xD7, 0xDF, 0xFA, 0x36, 0xDE, 0x80, 0x3E, 0xF4, 0xF8,
+	0xAD, 0xF1, 0x43, 0xC1, 0xDF, 0x07, 0x7C, 0x1B, 0x3F, 0x8F, 0x7E, 0x21, 0x5F, 0xC9, 0x6B, 0xA5,
+	0xDA, 0xC9, 0x1A, 0x49, 0x34, 0x70, 0xBC, 0xA4, 0x33, 0xBE, 0xC1, 0xC2, 0x7F, 0xBD, 0x5E, 0x5A,
+	0xBF, 0xF0, 0x52, 0xCF, 0xD9, 0x10, 0x28, 0x0D, 0xE3, 0xDB, 0xF2, 0x7B, 0x91, 0xA0, 0xDC, 0x73,
+	0xFF, 0x00, 0x8E, 0x52, 0xFF, 0x00, 0xC1, 0x4A, 0xBF, 0xE4, 0xD2, 0xB5, 0xEF, 0xFA, 0xFD, 0xB1,
+	0xFF, 0x00, 0xD2, 0x85, 0xAF, 0xCC, 0xAA, 0x00, 0xFD, 0x34, 0xFF, 0x00, 0x87, 0x96, 0x7E, 0xC8,
+	0x7F, 0xF4, 0x3D, 0xEA, 0x1F, 0xF8, 0x21, 0xB8, 0xFF, 0x00, 0xE3, 0x74, 0x7F, 0xC3, 0xCB, 0x3F,
+	0x64, 0x3F, 0xFA, 0x1E, 0xF5, 0x0F, 0xFC, 0x10, 0xDC, 0x7F, 0xF1, 0xBA, 0xFC, 0xCB, 0xA2, 0x80,
+	0x3F, 0x4D, 0x3F, 0xE1, 0xE5, 0x9F, 0xB2, 0x1F, 0xFD, 0x0F, 0x7A, 0x87, 0xFE, 0x08, 0x6E, 0x3F,
+	0xF8, 0xDD, 0x77, 0xDF, 0x05, 0x3F, 0x68, 0x8F, 0x84, 0xDF, 0xB4, 0x1C, 0x3A, 0x85, 0xF7, 0xC3,
+	0x0D, 0x72, 0x6B, 0xD8, 0xF4, 0xB9, 0x11, 0x2F, 0x1A, 0x6B, 0x19, 0x21, 0xD8, 0xCE, 0x37, 0xAF,
+	0xDF, 0x1E, 0x8B, 0x5F, 0x91, 0xB5, 0xF7, 0x1F, 0xFC, 0x12, 0x0F, 0xFE, 0x45, 0xBF, 0x1D, 0x7F,
+	0xD7, 0xFD, 0x8F, 0xFE, 0x8A, 0xB8, 0xA0, 0x0F, 0x77, 0xFD, 0xA3, 0xFF, 0x00, 0x6B, 0xDF, 0x83,
+	0x3F, 0xB2, 0xD8, 0xD2, 0x47, 0xC5, 0xED, 0x5E, 0xF6, 0xCD, 0xFC, 0x40, 0xB7, 0x3F, 0xD9, 0xBF,
+	0x64, 0xB1, 0x69, 0xC1, 0x30, 0x79, 0x7B, 0xF3, 0xB7, 0xFE, 0xBA, 0xA5, 0x79, 0xBA, 0xFF, 0x00,
+	0xC1, 0x5E, 0x3F, 0x62, 0xE0, 0xB8, 0x5F, 0x15, 0xEB, 0x5B, 0x7B, 0x6D, 0xD0, 0x25, 0xC7, 0xF2,
+	0xAF, 0x17, 0xFF, 0x00, 0x82, 0xEB, 0xFF, 0x00, 0xAC, 0xF8, 0x5B, 0xFE, 0xEE, 0xB7, 0xFC, 0xF4,
+	0xFA, 0xFC, 0xFD, 0xAF, 0x53, 0x0B, 0x81, 0xA7, 0x5A, 0x8F, 0x33, 0x3C, 0x9C, 0x46, 0x32, 0xAD,
+	0x3A, 0xDC, 0xA8, 0xFD, 0x6C, 0xFF, 0x00, 0x87, 0xBC, 0xFE, 0xC5, 0xFF, 0x00, 0xF4, 0x35, 0xEB,
+	0x9F, 0xF8, 0x20, 0x96, 0x8F, 0xF8, 0x7B, 0xC7, 0xEC, 0x5F, 0xFF, 0x00, 0x43, 0x5E, 0xB9, 0xFF,
+	0x00, 0x82, 0x09, 0x6B, 0xF2, 0x4E, 0x8A, 0xE8, 0xFE, 0xCC, 0xC3, 0xF9, 0xFD, 0xE6, 0x3F, 0xDA,
+	0x55, 0xFC, 0x8F, 0xD6, 0xBF, 0xF8, 0x7B, 0xCF, 0xEC, 0x61, 0x9F, 0xF9, 0x1A, 0xF5, 0xBF, 0xFC,
+	0x10, 0x4B, 0x5E, 0xCF, 0xF0, 0x27, 0xE3, 0xD7, 0xC3, 0x9F, 0xDA, 0x33, 0xC0, 0xB1, 0xFC, 0x49,
+	0xF8, 0x61, 0xA8, 0xDC, 0x5C, 0x69, 0x92, 0x5E, 0x4B, 0x6F, 0x1C, 0x97, 0x56, 0xE6, 0x16, 0xF3,
+	0x10, 0xE1, 0x86, 0xD3, 0xEF, 0x5F, 0x85, 0xB5, 0xFA, 0xB7, 0xFF, 0x00, 0x04, 0x78, 0xFF, 0x00,
+	0x93, 0x39, 0x4F, 0xFB, 0x19, 0x75, 0x0F, 0xFD, 0xA5, 0x5C, 0xB8, 0xBC, 0x1D, 0x2C, 0x3D, 0x2B,
+	0xC7, 0xB9, 0xD1, 0x84, 0xC5, 0xD4, 0xAD, 0x57, 0x95, 0x9E, 0xC7, 0xF1, 0x0F, 0xF6, 0x99, 0xF8,
+	0x61, 0xF0, 0xD7, 0xC4, 0x92, 0x78, 0x5B, 0xC4, 0x77, 0x97, 0x82, 0xEE, 0x18, 0x56, 0x59, 0x84,
+	0x36, 0x1B, 0x94, 0x23, 0x74, 0xC9, 0xAC, 0x43, 0xFB, 0x6C, 0xFC, 0x11, 0x53, 0x8F, 0xB6, 0x6A,
+	0x5F, 0xF0, 0x1D, 0x3D, 0xB1, 0xFC, 0xEB, 0xC3, 0xBF, 0x6C, 0xFF, 0x00, 0xF9, 0x2F, 0xBA, 0x8F,
+	0xFD, 0x7B, 0x5A, 0x7F, 0xE8, 0x15, 0xE5, 0x23, 0xA5, 0x7F, 0x0A, 0xF1, 0xB7, 0xD2, 0x1B, 0x8D,
+	0xB8, 0x73, 0x8A, 0xB1, 0x99, 0x66, 0x12, 0x9D, 0x2F, 0x67, 0x46, 0xA4, 0xA3, 0x17, 0x28, 0xC9,
+	0xB6, 0x95, 0xB7, 0x7C, 0xDB, 0x9F, 0xB7, 0x64, 0xFC, 0x0B, 0x94, 0xE6, 0x19, 0x5D, 0x1C, 0x45,
+	0x59, 0x4A, 0xF2, 0x49, 0xE8, 0xD7, 0x5F, 0x91, 0xF6, 0x3F, 0xFC, 0x36, 0xDF, 0xC1, 0x1E, 0xF7,
+	0x9A, 0x9F, 0xFE, 0x00, 0x37, 0xF8, 0xD1, 0xFF, 0x00, 0x0D, 0xB7, 0xF0, 0x43, 0xFE, 0x7F, 0x35,
+	0x3F, 0xFC, 0x17, 0xB7, 0xFF, 0x00, 0x15, 0x5F, 0x1C, 0x51, 0x5F, 0x29, 0xFF, 0x00, 0x13, 0x41,
+	0xE2, 0x07, 0xFC, 0xFA, 0xA1, 0xFF, 0x00, 0x80, 0xCB, 0xFF, 0x00, 0x93, 0x3D, 0x4F, 0xF8, 0x87,
+	0x39, 0x1F, 0xF3, 0x4B, 0xEF, 0x5F, 0xE4, 0x7D, 0x93, 0xFF, 0x00, 0x0D, 0xA9, 0xF0, 0x34, 0x8D,
+	0xDF, 0x6E, 0xD4, 0x3F, 0xF0, 0x5E, 0xDF, 0xE3, 0x5E, 0xAB, 0xE1, 0xBD, 0x7B, 0x4F, 0xF1, 0x3F,
+	0x87, 0xEC, 0x7C, 0x45, 0xA4, 0xB3, 0x35, 0xAD, 0xFD, 0x9C, 0x77, 0x16, 0xEC, 0xEB, 0xB4, 0x94,
+	0x74, 0x0C, 0xB9, 0x1D, 0x8E, 0x08, 0xAF, 0xCE, 0x1A, 0xFD, 0x04, 0xF8, 0x25, 0xFF, 0x00, 0x24,
+	0x6F, 0xC2, 0x7F, 0xF6, 0x2D, 0xD9, 0x7F, 0xE8, 0x84, 0xAF, 0xDC, 0xBC, 0x0E, 0xF1, 0x6B, 0x89,
+	0x3C, 0x46, 0xCD, 0x31, 0x78, 0x6C, 0xCE, 0x14, 0xE2, 0xA9, 0x42, 0x32, 0x5C, 0x89, 0xA6, 0xDB,
+	0x95, 0x9D, 0xEF, 0x27, 0xA5, 0x8F, 0x8D, 0xE3, 0x0E, 0x19, 0xC0, 0x64, 0x38, 0x7A, 0x33, 0xC3,
+	0xB9, 0x37, 0x26, 0xD3, 0xBD, 0xBA, 0x5B, 0xB2, 0x47, 0x07, 0xE3, 0x9F, 0xDB, 0xC7, 0xF6, 0x6B,
+	0xF8, 0x6F, 0xE3, 0x2B, 0xEF, 0x01, 0xF8, 0xB3, 0xC6, 0x37, 0x56, 0xDA, 0x8E, 0x97, 0x75, 0xE4,
+	0x5E, 0x42, 0xBA, 0x4C, 0xEC, 0x03, 0x1C, 0xF1, 0x90, 0x98, 0x3C, 0xF7, 0x1C, 0x56, 0x3A, 0xFF,
+	0x00, 0xC1, 0x4B, 0x7F, 0x64, 0x42, 0x32, 0xDE, 0x3B, 0xBF, 0xCF, 0xFD, 0x80, 0x6E, 0x3F, 0xF8,
+	0xDD, 0x7C, 0x3B, 0xFB, 0x69, 0xFF, 0x00, 0xC9, 0xD7, 0x78, 0xDB, 0xFE, 0xC3, 0x87, 0xFF, 0x00,
+	0x41, 0x5A, 0xF2, 0xC4, 0xFB, 0x83, 0xE9, 0x5F, 0xD2, 0x27, 0xC1, 0x9F, 0xA6, 0xBF, 0xF0, 0xF2,
+	0xCF, 0xD9, 0x0F, 0xFE, 0x87, 0xBD, 0x43, 0xFF, 0x00, 0x04, 0x37, 0x1F, 0xFC, 0x6E, 0x8F, 0xF8,
+	0x79, 0x67, 0xEC, 0x87, 0xFF, 0x00, 0x43, 0xDE, 0xA1, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x37,
+	0x5F, 0x99, 0x74, 0x50, 0x07, 0xE9, 0xA7, 0xFC, 0x3C, 0xB3, 0xF6, 0x43, 0xFF, 0x00, 0xA1, 0xEF,
+	0x50, 0xFF, 0x00, 0xC1, 0x0D, 0xC7, 0xFF, 0x00, 0x1B, 0xAE, 0xF3, 0xE0, 0x7F, 0xC7, 0x9F, 0x86,
+	0x5F, 0xB4, 0x2A, 0x6B, 0x1E, 0x23, 0xF8, 0x61, 0xAC, 0x4D, 0x7F, 0x6B, 0x65, 0xE4, 0x5A, 0xDC,
+	0x79, 0xF6, 0x6F, 0x0E, 0x1F, 0xF7, 0x8E, 0x06, 0x24, 0x1C, 0xF0, 0xDD, 0x71, 0x5F, 0x91, 0xF5,
+	0xF7, 0x9F, 0xFC, 0x12, 0x25, 0x77, 0xFC, 0x32, 0xF1, 0x92, 0x8F, 0xFA, 0x0E, 0x41, 0x8F, 0x6F,
+	0xDC, 0xD0, 0x07, 0xB1, 0xFC, 0x54, 0xFD, 0xAF, 0xFE, 0x05, 0xFC, 0x06, 0xF1, 0x94, 0xDE, 0x0E,
+	0xF8, 0x9D, 0xE2, 0xAB, 0x8B, 0x3B, 0xE9, 0x22, 0x8E, 0xE6, 0x38, 0x62, 0xD3, 0x67, 0x97, 0x31,
+	0xBA, 0x91, 0xD5, 0x41, 0x1D, 0x51, 0xAB, 0x9D, 0xFF, 0x00, 0x87, 0x96, 0x7E, 0xC8, 0x7F, 0xF4,
+	0x3D, 0xEA, 0x1F, 0xF8, 0x21, 0xB8, 0xFF, 0x00, 0xE3, 0x75, 0xF2, 0xF7, 0xFC, 0x15, 0x47, 0xFE,
+	0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B, 0x5F, 0xFD, 0x0E, 0x5A, 0xF9, 0xB2, 0x80, 0x3F, 0x4D, 0x3F,
+	0xE1, 0xE5, 0x9F, 0xB2, 0x1F, 0xFD, 0x0F, 0x7A, 0x87, 0xFE, 0x08, 0x6E, 0x3F, 0xF8, 0xDD, 0x1F,
+	0xF0, 0xF2, 0xCF, 0xD9, 0x0F, 0xFE, 0x87, 0xBD, 0x43, 0xFF, 0x00, 0x04, 0x37, 0x1F, 0xFC, 0x6E,
+	0xBF, 0x32, 0xE8, 0xA0, 0x0F, 0xD3, 0x47, 0xFF, 0x00, 0x82, 0x94, 0xFE, 0xC8, 0x72, 0x8F, 0x2F,
+	0xFE, 0x13, 0xCB, 0xFF, 0x00, 0x98, 0x8C, 0xFF, 0x00, 0xC4, 0x8E, 0xE8, 0x71, 0x9E, 0x7E, 0xEC,
+	0x79, 0xAF, 0x40, 0xF8, 0x25, 0xFB, 0x44, 0xFC, 0x2A, 0xFD, 0xA2, 0x2C, 0x35, 0x3B, 0xCF, 0x85,
+	0xDA, 0xC4, 0xD7, 0xF1, 0xE9, 0x8D, 0x0A, 0x5E, 0x19, 0xEC, 0x64, 0x83, 0x0D, 0x22, 0x96, 0x51,
+	0x89, 0x14, 0x13, 0x90, 0xBD, 0x6B, 0xF2, 0x2F, 0xB7, 0xE1, 0x5F, 0x73, 0x7F, 0xC1, 0x21, 0x17,
+	0x7F, 0x86, 0x7C, 0x7C, 0xA3, 0xFE, 0x82, 0x16, 0x18, 0xF6, 0xFD, 0xDC, 0xD4, 0x01, 0xEE, 0x1F,
+	0x15, 0x3F, 0x6B, 0xFF, 0x00, 0x81, 0x7F, 0x01, 0xBC, 0x65, 0x37, 0x83, 0xBE, 0x27, 0x78, 0xAA,
+	0xE2, 0xCE, 0xFA, 0x48, 0xA3, 0xB9, 0x8E, 0x18, 0xB4, 0xD9, 0xE5, 0xCC, 0x6E, 0xA4, 0x75, 0x50,
+	0x47, 0x54, 0x6A, 0xE7, 0x7F, 0xE1, 0xE5, 0x9F, 0xB2, 0x1F, 0xFD, 0x0F, 0x7A, 0x87, 0xFE, 0x08,
+	0x6E, 0x3F, 0xF8, 0xDD, 0x7C, 0xBD, 0xFF, 0x00, 0x05, 0x51, 0xFF, 0x00, 0x93, 0x99, 0xB7, 0xFF,
+	0x00, 0xB1, 0x62, 0xD7, 0xFF, 0x00, 0x43, 0x96, 0xBE, 0x6C, 0xA0, 0x0F, 0xD3, 0x4F, 0xF8, 0x79,
+	0x67, 0xEC, 0x87, 0xFF, 0x00, 0x43, 0xDE, 0xA1, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x37, 0x47,
+	0xFC, 0x3C, 0xB3, 0xF6, 0x43, 0xFF, 0x00, 0xA1, 0xEF, 0x50, 0xFF, 0x00, 0xC1, 0x0D, 0xC7, 0xFF,
+	0x00, 0x1B, 0xAF, 0xCC, 0xBA, 0x28, 0x03, 0xF4, 0xD1, 0xFF, 0x00, 0xE0, 0xA5, 0x3F, 0xB2, 0x1C,
+	0xA3, 0xCB, 0xFF, 0x00, 0x84, 0xF2, 0xFF, 0x00, 0xE6, 0x23, 0x3F, 0xF1, 0x23, 0xBA, 0x1C, 0x67,
+	0x9F, 0xBB, 0x1E, 0x6B, 0xBE, 0xF8, 0x23, 0xFB, 0x45, 0xFC, 0x2C, 0xFD, 0xA1, 0xAD, 0xEF, 0xEF,
+	0x7E, 0x16, 0x6B, 0x93, 0xDE, 0xC7, 0xA5, 0xBC, 0x4B, 0x7C, 0xD3, 0x58, 0xC9, 0x06, 0xD6, 0x91,
+	0x49, 0x5E, 0x24, 0x50, 0x4F, 0x02, 0xBF, 0x23, 0x7B, 0x7E, 0x15, 0xF7, 0x37, 0xFC, 0x12, 0x0F,
+	0xFE, 0x45, 0xDF, 0x1E, 0x7F, 0xD8, 0x42, 0xC7, 0xFF, 0x00, 0x45, 0xCD, 0x40, 0x1F, 0x65, 0x5B,
+	0xED, 0x2A, 0xC5, 0x71, 0xF7, 0xBB, 0x36, 0x7B, 0x54, 0x95, 0x1C, 0x1F, 0xC5, 0xFE, 0xF0, 0xFF,
+	0x00, 0xD0, 0x45, 0x49, 0x40, 0x05, 0x07, 0xA5, 0x14, 0x1E, 0x94, 0x01, 0xF0, 0xA7, 0xFC, 0x15,
+	0xF7, 0xFE, 0x46, 0x4F, 0x03, 0xFF, 0x00, 0xD7, 0x95, 0xF7, 0xFE, 0x8C, 0x8E, 0xBE, 0x36, 0xAF,
+	0xB2, 0x7F, 0xE0, 0xAF, 0xBF, 0xF2, 0x32, 0x78, 0x1F, 0xFE, 0xBC, 0xAF, 0xBF, 0xF4, 0x64, 0x75,
+	0xF1, 0xB5, 0x00, 0x14, 0x51, 0x45, 0x00, 0x03, 0xAD, 0x7D, 0x61, 0xFF, 0x00, 0x04, 0x8F, 0xFF,
+	0x00, 0x92, 0xD5, 0xE2, 0x5F, 0xFB, 0x15, 0x57, 0xFF, 0x00, 0x4A, 0x62, 0xAF, 0x93, 0xC7, 0x5A,
+	0xFA, 0xC3, 0xFE, 0x09, 0x1F, 0xFF, 0x00, 0x25, 0xAB, 0xC4, 0xBF, 0xF6, 0x2A, 0xAF, 0xFE, 0x94,
+	0xC5, 0x40, 0x1E, 0xBB, 0xFF, 0x00, 0x05, 0x65, 0xFF, 0x00, 0x93, 0x71, 0xD1, 0xFF, 0x00, 0xEC,
+	0x73, 0xB5, 0xFF, 0x00, 0xD2, 0x5B, 0xDA, 0xFC, 0xF2, 0xAF, 0xD0, 0xDF, 0xF8, 0x2B, 0x2F, 0xFC,
+	0x9B, 0x8E, 0x8F, 0xFF, 0x00, 0x63, 0x9D, 0xAF, 0xFE, 0x92, 0xDE, 0xD7, 0xE7, 0x95, 0x24, 0x01,
+	0x45, 0x14, 0x53, 0x00, 0xAF, 0x7A, 0xFF, 0x00, 0x82, 0x6C, 0x7F, 0xC9, 0xDC, 0xE8, 0x3F, 0xF6,
+	0x0F, 0xD4, 0x3F, 0xF4, 0x9D, 0xEB, 0xC1, 0x6B, 0xDE, 0xBF, 0xE0, 0x9B, 0x1F, 0xF2, 0x77, 0x3A,
+	0x0F, 0xFD, 0x83, 0xF5, 0x0F, 0xFD, 0x27, 0x7A, 0x00, 0xFB, 0x27, 0xFE, 0x0A, 0x23, 0xFF, 0x00,
+	0x26, 0x77, 0xE3, 0x1F, 0xF7, 0x2C, 0xBF, 0xF4, 0xE1, 0x6B, 0x5F, 0x97, 0x95, 0xFA, 0x87, 0xFF,
+	0x00, 0x05, 0x11, 0xFF, 0x00, 0x93, 0x3B, 0xF1, 0x8F, 0xFB, 0x96, 0x5F, 0xFA, 0x70, 0xB5, 0xAF,
+	0xCB, 0xCA, 0x48, 0x02, 0x8A, 0x28, 0xA6, 0x01, 0x5E, 0x89, 0xFB, 0x25, 0x7F, 0xC9, 0xCE, 0x78,
+	0x07, 0xFE, 0xC6, 0xAB, 0x4F, 0xFD, 0x08, 0x57, 0x9D, 0xD7, 0xA2, 0x7E, 0xC9, 0x5F, 0xF2, 0x73,
+	0x9E, 0x01, 0xFF, 0x00, 0xB1, 0xAA, 0xD3, 0xFF, 0x00, 0x42, 0x14, 0x01, 0xFA, 0x5D, 0xFB, 0x53,
+	0x7F, 0xC9, 0xB2, 0x7C, 0x45, 0xFF, 0x00, 0xB1, 0x17, 0x57, 0xFF, 0x00, 0xD2, 0x09, 0xEB, 0xF1,
+	0x86, 0xBF, 0x67, 0xBF, 0x6A, 0x6F, 0xF9, 0x36, 0x4F, 0x88, 0xBF, 0xF6, 0x22, 0xEA, 0xFF, 0x00,
+	0xFA, 0x41, 0x3D, 0x7E, 0x30, 0xD7, 0x3D, 0x6E, 0x86, 0x94, 0xC2, 0x8A, 0x28, 0xAE, 0x73, 0x40,
+	0xAF, 0xA3, 0x3F, 0xE0, 0x95, 0x5F, 0xF2, 0x78, 0xBA, 0x57, 0xFD, 0x81, 0xEF, 0xFF, 0x00, 0xF4,
+	0x43, 0x57, 0xCE, 0x75, 0xF4, 0x67, 0xFC, 0x12, 0xAB, 0xFE, 0x4F, 0x17, 0x4A, 0xFF, 0x00, 0xB0,
+	0x3D, 0xFF, 0x00, 0xFE, 0x88, 0x6A, 0xAA, 0x7F, 0x12, 0x26, 0x5F, 0x09, 0xF5, 0x37, 0xFC, 0x16,
+	0x28, 0xFF, 0x00, 0xC6, 0x1C, 0xCD, 0xFF, 0x00, 0x63, 0x35, 0x97, 0xF2, 0x96, 0xBF, 0x28, 0x4F,
+	0x5A, 0xFD, 0x5E, 0xFF, 0x00, 0x82, 0xC5, 0x1F, 0xF8, 0xC3, 0x99, 0xBF, 0xEC, 0x66, 0xB2, 0xFE,
+	0x52, 0xD7, 0xE5, 0x09, 0xEB, 0x5F, 0x55, 0x96, 0xFF, 0x00, 0xBB, 0xFC, 0xCF, 0x9A, 0xCC, 0x3F,
+	0x8C, 0xFD, 0x10, 0x51, 0x45, 0x15, 0xE8, 0x1C, 0x41, 0x5F, 0xA0, 0x1F, 0xF0, 0x42, 0xDF, 0xBF,
+	0xF1, 0x47, 0xFD, 0xED, 0x17, 0xFF, 0x00, 0x40, 0xBF, 0xAF, 0xCF, 0xFA, 0xFD, 0x00, 0xFF, 0x00,
+	0x82, 0x16, 0xFD, 0xFF, 0x00, 0x8A, 0x3F, 0xEF, 0x68, 0xBF, 0xFA, 0x05, 0xFD, 0x71, 0xE3, 0xFF,
+	0x00, 0xDD, 0xD9, 0xD7, 0x81, 0xFF, 0x00, 0x78, 0x47, 0x79, 0xFF, 0x00, 0x05, 0x82, 0xFF, 0x00,
+	0x90, 0x0F, 0x81, 0x7F, 0xEB, 0xFA, 0xFB, 0xFF, 0x00, 0x40, 0x8E, 0xBE, 0x1B, 0xAF, 0xB9, 0x3F,
+	0xE0, 0xB0, 0x5F, 0xF2, 0x01, 0xF0, 0x2F, 0xFD, 0x7F, 0x5F, 0x7F, 0xE8, 0x11, 0xD7, 0xC3, 0x75,
+	0xF3, 0xE7, 0xD0, 0x85, 0x14, 0x51, 0x40, 0x05, 0x7E, 0x9A, 0x7F, 0xC1, 0x35, 0x7F, 0xE4, 0xD1,
+	0xF4, 0x3F, 0xFA, 0xFE, 0xBF, 0xFF, 0x00, 0xD2, 0x96, 0xAF, 0xCC, 0xBA, 0xFD, 0x34, 0xFF, 0x00,
+	0x82, 0x6A, 0xFF, 0x00, 0xC9, 0xA3, 0xE8, 0x7F, 0xF5, 0xFD, 0x7F, 0xFF, 0x00, 0xA5, 0x2D, 0x40,
+	0x1F, 0x2E, 0xFF, 0x00, 0xC1, 0x55, 0xFF, 0x00, 0xE4, 0xE5, 0xA2, 0xFF, 0x00, 0xB1, 0x56, 0xD7,
+	0xFF, 0x00, 0x46, 0x4D, 0x5F, 0x36, 0x9E, 0xB5, 0xF4, 0x97, 0xFC, 0x15, 0x5F, 0xFE, 0x4E, 0x5A,
+	0x2F, 0xFB, 0x15, 0x6D, 0x7F, 0xF4, 0x64, 0xD5, 0xF3, 0x69, 0xEB, 0x40, 0x05, 0x14, 0x57, 0xA0,
+	0x7E, 0xCF, 0xDF, 0xB3, 0x67, 0xC4, 0x5F, 0xDA, 0x3F, 0xC5, 0xAB, 0xA1, 0xF8, 0x43, 0x4B, 0x64,
+	0xB1, 0x85, 0x97, 0xFB, 0x4B, 0x58, 0xB9, 0x8F, 0x16, 0xB6, 0x89, 0xDF, 0x2F, 0xFC, 0x4F, 0xE8,
+	0xB4, 0x01, 0xC9, 0x78, 0x43, 0xC1, 0xFE, 0x2B, 0xF1, 0xF7, 0x88, 0xAD, 0x7C, 0x23, 0xE0, 0xAD,
+	0x0A, 0xEB, 0x51, 0xD4, 0x2E, 0xE4, 0xFF, 0x00, 0x47, 0xB3, 0xB2, 0x8F, 0x7B, 0x3F, 0x4C, 0xB6,
+	0x3F, 0x80, 0x0E, 0xED, 0x5F, 0xB0, 0x3F, 0x0C, 0xB4, 0x1D, 0x4B, 0xC2, 0xDF, 0x0D, 0xBC, 0x3D,
+	0xE1, 0x8D, 0x61, 0x54, 0x5E, 0x69, 0xBA, 0x1D, 0xA5, 0xAD, 0xD0, 0x49, 0x37, 0x01, 0x24, 0x70,
+	0xAA, 0x36, 0x0F, 0x71, 0x90, 0x79, 0xEF, 0x5C, 0x77, 0xEC, 0xE5, 0xFB, 0x2F, 0xFC, 0x32, 0xFD,
+	0x9B, 0x7C, 0x3F, 0xFD, 0x9B, 0xE0, 0xED, 0x38, 0xCF, 0xA8, 0x4E, 0xBF, 0xF1, 0x34, 0xD6, 0xEF,
+	0x13, 0x37, 0x17, 0x6D, 0x8E, 0x99, 0xFE, 0x15, 0x07, 0xA2, 0x76, 0xE9, 0x5E, 0x98, 0x99, 0x0A,
+	0x01, 0x23, 0xA7, 0x61, 0x40, 0x0B, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14,
+	0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x5F, 0xCB, 0x97, 0xFC, 0x1C, 0xE3,
+	0xFF, 0x00, 0x29, 0x85, 0xF8, 0x81, 0xFF, 0x00, 0x60, 0x2F, 0x0F, 0xFF, 0x00, 0xE9, 0xB6, 0xDE,
+	0xBF, 0xA8, 0xDA, 0xFE, 0x5C, 0xBF, 0xE0, 0xE7, 0x1F, 0xF9, 0x4C, 0x2F, 0xC4, 0x0F, 0xFB, 0x01,
+	0x78, 0x7F, 0xFF, 0x00, 0x4D, 0xB6, 0xF5, 0x9D, 0x5F, 0x84, 0xE8, 0xC1, 0xFF, 0x00, 0x19, 0x9F,
+	0x00, 0x51, 0x45, 0x15, 0xCE, 0x7A, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45,
+	0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45,
+	0x14, 0x50, 0x00, 0xBD, 0x4F, 0xE1, 0xFC, 0x8D, 0x7F, 0x71, 0x83, 0xA5, 0x7F, 0x0E, 0x6B, 0xD4,
+	0xFE, 0x1F, 0xC8, 0xD7, 0xF7, 0x18, 0xBF, 0x76, 0xB6, 0xA3, 0xF0, 0x9C, 0x78, 0xAF, 0xB2, 0x14,
+	0x51, 0x45, 0x6C, 0x71, 0x85, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40,
+	0x05, 0x14, 0x51, 0x40, 0x18, 0x9F, 0x11, 0xFC, 0x3D, 0x37, 0x8A, 0xFC, 0x01, 0xAE, 0x78, 0x56,
+	0xD5, 0xE3, 0x59, 0xB5, 0x5D, 0x22, 0xEA, 0xCE, 0x33, 0x23, 0x6D, 0x5D, 0xD2, 0x42, 0xC8, 0xB9,
+	0xFF, 0x00, 0xBE, 0xAB, 0xF2, 0x3B, 0xE2, 0xA7, 0xC2, 0x4F, 0x88, 0x3F, 0x05, 0x7C, 0x53, 0x37,
+	0x83, 0xBE, 0x21, 0xE8, 0xB2, 0xD9, 0x5D, 0x46, 0x73, 0x1D, 0xC3, 0x45, 0x94, 0xB8, 0x5C, 0xE3,
+	0x72, 0x1F, 0xF9, 0x6A, 0xA7, 0xA8, 0xFE, 0xE8, 0xAF, 0xD8, 0xCA, 0xE3, 0x7E, 0x34, 0x7C, 0x11,
+	0xF8, 0x79, 0xF1, 0xDF, 0xC2, 0x52, 0x78, 0x33, 0xE2, 0x2E, 0x83, 0x1D, 0xED, 0xBB, 0x31, 0x30,
+	0xCC, 0xA7, 0x6C, 0xB6, 0xAF, 0xC7, 0xCF, 0x1B, 0xFF, 0x00, 0x09, 0xC7, 0x51, 0xDE, 0x80, 0x3F,
+	0x20, 0x4E, 0x73, 0xCE, 0x7F, 0x17, 0xDD, 0xFA, 0xF7, 0xFA, 0xF7, 0xA2, 0xBD, 0x83, 0xF6, 0xA6,
+	0xFD, 0x8E, 0xBE, 0x21, 0x7E, 0xCC, 0xFA, 0xAF, 0xF6, 0x84, 0xC5, 0xF5, 0x4F, 0x0D, 0xDC, 0x48,
+	0x7F, 0xB3, 0xF5, 0xD8, 0xE3, 0xDA, 0x15, 0x89, 0xFF, 0x00, 0x57, 0x3A, 0x7F, 0xCB, 0x26, 0x1F,
+	0xDE, 0xEE, 0x6B, 0xC7, 0xC0, 0x0A, 0x36, 0x8A, 0x00, 0x2B, 0xE9, 0x2F, 0xF8, 0x25, 0x6F, 0xFC,
+	0x9C, 0xD4, 0xFF, 0x00, 0xF6, 0x2B, 0x5F, 0x7F, 0xE8, 0xDB, 0x7A, 0xF9, 0xB6, 0xBE, 0x92, 0xFF,
+	0x00, 0x82, 0x56, 0xFF, 0x00, 0xC9, 0xCD, 0x4F, 0xFF, 0x00, 0x62, 0xB5, 0xF7, 0xFE, 0x8D, 0xB7,
+	0xA0, 0x0F, 0xA8, 0xFF, 0x00, 0xE0, 0xA5, 0x5F, 0xF2, 0x69, 0x5A, 0xF7, 0xFD, 0x7E, 0xD8, 0xFF,
+	0x00, 0xE9, 0x42, 0xD7, 0xE6, 0x55, 0x7E, 0x9A, 0xFF, 0x00, 0xC1, 0x4A, 0xBF, 0xE4, 0xD2, 0xB5,
+	0xEF, 0xFA, 0xFD, 0xB1, 0xFF, 0x00, 0xD2, 0x85, 0xAF, 0xCC, 0xAA, 0x00, 0x28, 0xA2, 0x8A, 0x00,
+	0x2B, 0xEE, 0x3F, 0xF8, 0x24, 0x1F, 0xFC, 0x8B, 0x7E, 0x3A, 0xFF, 0x00, 0xAF, 0xFB, 0x1F, 0xFD,
+	0x15, 0x71, 0x5F, 0x0E, 0x57, 0xDC, 0x7F, 0xF0, 0x48, 0x3F, 0xF9, 0x16, 0xFC, 0x75, 0xFF, 0x00,
+	0x5F, 0xF6, 0x3F, 0xFA, 0x2A, 0xE2, 0x80, 0x38, 0x6F, 0xF8, 0x2E, 0xBF, 0xFA, 0xCF, 0x85, 0xBF,
+	0xEE, 0xEB, 0x7F, 0xCF, 0x4F, 0xAF, 0xCF, 0xDA, 0xFD, 0x02, 0xFF, 0x00, 0x82, 0xEB, 0xFF, 0x00,
+	0xAC, 0xF8, 0x5B, 0xFE, 0xEE, 0xB7, 0xFC, 0xF4, 0xFA, 0xFC, 0xFD, 0xAF, 0xA0, 0xCB, 0xFF, 0x00,
+	0xDD, 0x8F, 0x9E, 0xC6, 0xFF, 0x00, 0xBD, 0x30, 0xA2, 0x8A, 0x2B, 0xB0, 0xE4, 0x0A, 0xFD, 0x5B,
+	0xFF, 0x00, 0x82, 0x3C, 0x7F, 0xC9, 0x9C, 0xA7, 0xFD, 0x8C, 0xBA, 0x87, 0xFE, 0xD2, 0xAF, 0xCA,
+	0x4A, 0xFD, 0x5B, 0xFF, 0x00, 0x82, 0x3C, 0x7F, 0xC9, 0x9C, 0xA7, 0xFD, 0x8C, 0xBA, 0x87, 0xFE,
+	0xD2, 0xAE, 0x0C, 0xCB, 0xF8, 0x3F, 0x34, 0x77, 0x65, 0xDF, 0xEF, 0x1F, 0x23, 0x96, 0xFD, 0xB3,
+	0xFF, 0x00, 0xE4, 0xBE, 0xEA, 0x3F, 0xF5, 0xED, 0x69, 0xFF, 0x00, 0xA0, 0x57, 0x94, 0x8E, 0x95,
+	0xEA, 0xDF, 0xB6, 0x7F, 0xFC, 0x97, 0xDD, 0x47, 0xFE, 0xBD, 0xAD, 0x3F, 0xF4, 0x0A, 0xF2, 0x91,
+	0xD2, 0xBF, 0xC9, 0x1F, 0x15, 0xBF, 0xE4, 0xE2, 0xE6, 0x7F, 0xF5, 0xF6, 0x5F, 0xA1, 0xFD, 0x5D,
+	0xC3, 0x3F, 0xF2, 0x4F, 0xE1, 0xBF, 0xC0, 0x82, 0x8A, 0x28, 0xAF, 0xCF, 0x0F, 0x70, 0x2B, 0xF4,
+	0x13, 0xE0, 0x97, 0xFC, 0x91, 0xBF, 0x09, 0xFF, 0x00, 0xD8, 0xB7, 0x65, 0xFF, 0x00, 0xA2, 0x12,
+	0xBF, 0x3E, 0xEB, 0xF4, 0x13, 0xE0, 0x97, 0xFC, 0x91, 0xBF, 0x09, 0xFF, 0x00, 0xD8, 0xB7, 0x65,
+	0xFF, 0x00, 0xA2, 0x12, 0xBF, 0xAC, 0xBE, 0x89, 0xFF, 0x00, 0xF2, 0x50, 0x66, 0x5F, 0xF5, 0xEA,
+	0x1F, 0xFA, 0x59, 0xF9, 0x8F, 0x89, 0x9F, 0xEE, 0x78, 0x7F, 0xF1, 0x3F, 0xC9, 0x1F, 0x99, 0x3F,
+	0xB6, 0x9F, 0xFC, 0x9D, 0x77, 0x8D, 0xBF, 0xEC, 0x38, 0x7F, 0xF4, 0x15, 0xAF, 0x2C, 0x4F, 0xB8,
+	0x3E, 0x95, 0xEA, 0x7F, 0xB6, 0x9F, 0xFC, 0x9D, 0x77, 0x8D, 0xBF, 0xEC, 0x38, 0x7F, 0xF4, 0x15,
+	0xAF, 0x2C, 0x4F, 0xB8, 0x3E, 0x95, 0xFD, 0xC4, 0x7E, 0x42, 0x2D, 0x14, 0x51, 0x40, 0x05, 0x7D,
+	0xE9, 0xFF, 0x00, 0x04, 0x85, 0xFF, 0x00, 0x92, 0x6B, 0xE3, 0x0F, 0xFB, 0x0E, 0x41, 0xFF, 0x00,
+	0xA2, 0x6B, 0xE0, 0xBA, 0xFB, 0xD3, 0xFE, 0x09, 0x0B, 0xFF, 0x00, 0x24, 0xD7, 0xC6, 0x1F, 0xF6,
+	0x1C, 0x83, 0xFF, 0x00, 0x44, 0xD0, 0x07, 0x8F, 0x7F, 0xC1, 0x54, 0x7F, 0xE4, 0xE6, 0x6D, 0xFF,
+	0x00, 0xEC, 0x58, 0xB5, 0xFF, 0x00, 0xD0, 0xE5, 0xAF, 0x9B, 0x2B, 0xE9, 0x3F, 0xF8, 0x2A, 0x8F,
+	0xFC, 0x9C, 0xCD, 0xBF, 0xFD, 0x8B, 0x16, 0xBF, 0xFA, 0x1C, 0xB5, 0xF3, 0x65, 0x00, 0x14, 0x51,
+	0x45, 0x00, 0x1D, 0xBF, 0x0A, 0xFB, 0xA3, 0xFE, 0x09, 0x01, 0xFF, 0x00, 0x22, 0xE7, 0x8F, 0xBF,
+	0xEC, 0x21, 0x61, 0xFF, 0x00, 0xA2, 0xE6, 0xAF, 0x85, 0xFB, 0x7E, 0x15, 0xF7, 0x47, 0xFC, 0x12,
+	0x03, 0xFE, 0x45, 0xCF, 0x1F, 0x7F, 0xD8, 0x42, 0xC3, 0xFF, 0x00, 0x45, 0xCD, 0x40, 0x1E, 0x55,
+	0xFF, 0x00, 0x05, 0x51, 0xFF, 0x00, 0x93, 0x99, 0xB7, 0xFF, 0x00, 0xB1, 0x62, 0xD7, 0xFF, 0x00,
+	0x43, 0x96, 0xBE, 0x6C, 0xAF, 0xA4, 0xFF, 0x00, 0xE0, 0xAA, 0x3F, 0xF2, 0x73, 0x36, 0xFF, 0x00,
+	0xF6, 0x2C, 0x5A, 0xFF, 0x00, 0xE8, 0x72, 0xD7, 0xCD, 0x94, 0x00, 0x51, 0x45, 0x14, 0x00, 0x76,
+	0xFC, 0x2B, 0xEE, 0x6F, 0xF8, 0x24, 0x1F, 0xFC, 0x8B, 0xBE, 0x3C, 0xFF, 0x00, 0xB0, 0x85, 0x8F,
+	0xFE, 0x8B, 0x9A, 0xBE, 0x19, 0xED, 0xF8, 0x57, 0xDC, 0xDF, 0xF0, 0x48, 0x3F, 0xF9, 0x17, 0x7C,
+	0x79, 0xFF, 0x00, 0x61, 0x0B, 0x1F, 0xFD, 0x17, 0x35, 0x00, 0x7D, 0x95, 0x07, 0xF1, 0x7F, 0xBC,
+	0x3F, 0xF4, 0x11, 0x52, 0x54, 0x70, 0x7F, 0x17, 0xFB, 0xC3, 0xFF, 0x00, 0x41, 0x15, 0x25, 0x00,
+	0x14, 0x1E, 0x94, 0x50, 0x7A, 0x50, 0x07, 0xC2, 0x9F, 0xF0, 0x57, 0xDF, 0xF9, 0x19, 0x3C, 0x0F,
+	0xFF, 0x00, 0x5E, 0x57, 0xDF, 0xFA, 0x32, 0x3A, 0xF8, 0xDA, 0xBF, 0x57, 0x7E, 0x39, 0x7E, 0xCC,
+	0x1F, 0x0B, 0xBF, 0x69, 0x2D, 0x72, 0xC6, 0x5F, 0x89, 0xD6, 0x57, 0xB2, 0x3E, 0x8F, 0x6B, 0xB2,
+	0xD5, 0x6C, 0x2F, 0x8C, 0x7B, 0x7C, 0xD7, 0xCB, 0x67, 0xFE, 0xF8, 0x5A, 0xE3, 0x3F, 0xE1, 0xD7,
+	0xFF, 0x00, 0xB2, 0xB7, 0xFD, 0x01, 0xF5, 0xCF, 0xFC, 0x1D, 0x3D, 0x00, 0x7E, 0x6A, 0xD1, 0x5F,
+	0xA5, 0x5F, 0xF0, 0xEB, 0xFF, 0x00, 0xD9, 0x5B, 0xFE, 0x80, 0xFA, 0xE7, 0xFE, 0x0E, 0x9E, 0x8F,
+	0xF8, 0x75, 0xFF, 0x00, 0xEC, 0xAD, 0xFF, 0x00, 0x40, 0x7D, 0x73, 0xFF, 0x00, 0x07, 0x4F, 0x40,
+	0x1F, 0x9A, 0xA3, 0xAD, 0x7D, 0x61, 0xFF, 0x00, 0x04, 0x8F, 0xFF, 0x00, 0x92, 0xD5, 0xE2, 0x5F,
+	0xFB, 0x15, 0x57, 0xFF, 0x00, 0x4A, 0x62, 0xAF, 0x79, 0x3F, 0xF0, 0x4B, 0xFF, 0x00, 0xD9, 0x57,
+	0x1C, 0xE8, 0xFA, 0xE7, 0xFE, 0x0E, 0x9E, 0xBB, 0x3F, 0x81, 0xFF, 0x00, 0xB2, 0x1F, 0xC1, 0xFF,
+	0x00, 0xD9, 0xE7, 0xC4, 0x57, 0x9E, 0x26, 0xF8, 0x69, 0xA7, 0xEA, 0x10, 0xDD, 0xDE, 0xD9, 0xFD,
+	0x9A, 0xE1, 0xAF, 0x6F, 0x8C, 0x80, 0xA1, 0x90, 0x3F, 0x1E, 0xBF, 0x30, 0x14, 0x01, 0xE6, 0x1F,
+	0xF0, 0x56, 0x5F, 0xF9, 0x37, 0x1D, 0x1F, 0xFE, 0xC7, 0x3B, 0x5F, 0xFD, 0x25, 0xBD, 0xAF, 0xCF,
+	0x2A, 0xFD, 0x76, 0xF8, 0xE5, 0xF0, 0x23, 0xC0, 0xFF, 0x00, 0xB4, 0x27, 0x86, 0x60, 0xF0, 0x6F,
+	0xC4, 0x2B, 0x7B, 0x89, 0x34, 0xFB, 0x5D, 0x41, 0x6F, 0x55, 0x6C, 0xEE, 0x84, 0x72, 0x19, 0xC4,
+	0x6F, 0x18, 0x3D, 0x3F, 0xBB, 0x23, 0x77, 0xAF, 0x33, 0xFF, 0x00, 0x87, 0x5F, 0xFE, 0xCA, 0xDF,
+	0xF4, 0x07, 0xD7, 0x3F, 0xF0, 0x74, 0xF4, 0x01, 0xF9, 0xAB, 0x45, 0x7E, 0x95, 0x7F, 0xC3, 0xAF,
+	0xFF, 0x00, 0x65, 0x6F, 0xFA, 0x03, 0xEB, 0x9F, 0xF8, 0x3A, 0x7A, 0x3F, 0xE1, 0xD7, 0xFF, 0x00,
+	0xB2, 0xB7, 0xFD, 0x01, 0xF5, 0xCF, 0xFC, 0x1D, 0x3D, 0x00, 0x7E, 0x6A, 0xD7, 0xBD, 0x7F, 0xC1,
+	0x36, 0x3F, 0xE4, 0xEE, 0x74, 0x1F, 0xFB, 0x07, 0xEA, 0x1F, 0xFA, 0x4E, 0xF5, 0xF5, 0x87, 0xFC,
+	0x3A, 0xFF, 0x00, 0xF6, 0x56, 0xFF, 0x00, 0xA0, 0x3E, 0xB9, 0xFF, 0x00, 0x83, 0xA7, 0xAE, 0x87,
+	0xE1, 0x2F, 0xEC, 0x37, 0xF0, 0x23, 0xE0, 0x97, 0x8E, 0xAD, 0xBE, 0x20, 0xF8, 0x0B, 0x4C, 0xD5,
+	0x23, 0xD4, 0xAD, 0x63, 0x91, 0x21, 0x92, 0xEB, 0x52, 0x67, 0x4D, 0xAE, 0x9B, 0x1B, 0xFF, 0x00,
+	0x1D, 0xA0, 0x0A, 0xFF, 0x00, 0xF0, 0x51, 0x1F, 0xF9, 0x33, 0xBF, 0x18, 0xFF, 0x00, 0xB9, 0x65,
+	0xFF, 0x00, 0xA7, 0x0B, 0x5A, 0xFC, 0xBC, 0xAF, 0xD8, 0x7F, 0x8B, 0x1F, 0x0B, 0xFC, 0x39, 0xF1,
+	0x97, 0xC0, 0xF7, 0x9F, 0x0D, 0xFC, 0x67, 0x1C, 0x8D, 0xA6, 0xEA, 0x1E, 0x49, 0xBE, 0x5B, 0x79,
+	0x84, 0x72, 0x37, 0x97, 0x2A, 0xCA, 0x80, 0x70, 0x7F, 0x8D, 0x17, 0xB8, 0xAF, 0x20, 0x8F, 0xFE,
+	0x09, 0x7F, 0xFB, 0x2B, 0xEC, 0x5C, 0xE8, 0xFA, 0xF7, 0xDD, 0xFE, 0x2D, 0x65, 0xE8, 0x03, 0xF3,
+	0x5E, 0x8A, 0xFD, 0x2A, 0xFF, 0x00, 0x87, 0x5F, 0xFE, 0xCA, 0xDF, 0xF4, 0x07, 0xD7, 0x3F, 0xF0,
+	0x74, 0xF4, 0x7F, 0xC3, 0xAF, 0xFF, 0x00, 0x65, 0x6F, 0xFA, 0x03, 0xEB, 0x9F, 0xF8, 0x3A, 0x7A,
+	0x00, 0xFC, 0xD5, 0xAF, 0x44, 0xFD, 0x92, 0xBF, 0xE4, 0xE7, 0x3C, 0x03, 0xFF, 0x00, 0x63, 0x55,
+	0xA7, 0xFE, 0x84, 0x2B, 0xEE, 0x6F, 0xF8, 0x75, 0xFF, 0x00, 0xEC, 0xAD, 0xFF, 0x00, 0x40, 0x7D,
+	0x73, 0xFF, 0x00, 0x07, 0x4F, 0x5A, 0x3E, 0x0A, 0xFF, 0x00, 0x82, 0x79, 0xFE, 0xCE, 0x5F, 0x0F,
+	0x3C, 0x63, 0xA6, 0xF8, 0xDF, 0xC3, 0x3A, 0x4E, 0xAE, 0xBA, 0x86, 0x97, 0x79, 0x1D, 0xCD, 0x9C,
+	0x93, 0x6A, 0x8C, 0xE8, 0x24, 0x42, 0x48, 0xCF, 0xE2, 0x68, 0x03, 0xB7, 0xFD, 0xA9, 0xBF, 0xE4,
+	0xD9, 0x3E, 0x22, 0xFF, 0x00, 0xD8, 0x8B, 0xAB, 0xFF, 0x00, 0xE9, 0x04, 0xF5, 0xF8, 0xC3, 0x5F,
+	0xB7, 0xDF, 0x10, 0xBC, 0x23, 0xA7, 0xF8, 0xFF, 0x00, 0xC0, 0xDA, 0xC7, 0x81, 0x75, 0xD9, 0x1D,
+	0x6C, 0xF5, 0xAD, 0x26, 0xE2, 0xC2, 0xFA, 0x48, 0x24, 0x0B, 0x20, 0xB7, 0x9A, 0x36, 0x49, 0x36,
+	0x1D, 0xAD, 0x96, 0xDA, 0xC7, 0xB5, 0x7C, 0xE2, 0xBF, 0xF0, 0x47, 0xEF, 0xD9, 0x71, 0x94, 0x30,
+	0xF1, 0x27, 0x8D, 0xB9, 0x19, 0xF9, 0xF5, 0x48, 0x33, 0xF8, 0xE6, 0xDB, 0x39, 0xFA, 0xD6, 0x35,
+	0x23, 0x29, 0x59, 0x22, 0xE3, 0x25, 0x1D, 0xCF, 0xCC, 0xFA, 0x2B, 0xF4, 0xC7, 0xFE, 0x1C, 0xFB,
+	0xFB, 0x2E, 0xFF, 0x00, 0xD0, 0xC7, 0xE3, 0x4F, 0xFC, 0x1A, 0x5B, 0xFF, 0x00, 0xF2, 0x35, 0x1F,
+	0xF0, 0xE7, 0xDF, 0xD9, 0x77, 0xFE, 0x86, 0x3F, 0x1A, 0x7F, 0xE0, 0xD2, 0xDF, 0xFF, 0x00, 0x91,
+	0xAB, 0x1F, 0x65, 0x32, 0xF9, 0xA2, 0x7E, 0x67, 0x57, 0xD1, 0x9F, 0xF0, 0x4A, 0xAF, 0xF9, 0x3C,
+	0x5D, 0x2B, 0xFE, 0xC0, 0xF7, 0xFF, 0x00, 0xFA, 0x21, 0xAB, 0xEA, 0x5F, 0xF8, 0x73, 0xEF, 0xEC,
+	0xBB, 0xFF, 0x00, 0x43, 0x1F, 0x8D, 0x3F, 0xF0, 0x69, 0x6F, 0xFF, 0x00, 0xC8, 0xD5, 0xD8, 0x7C,
+	0x06, 0xFF, 0x00, 0x82, 0x79, 0xFC, 0x0E, 0xFD, 0x9D, 0x7E, 0x22, 0xC7, 0xF1, 0x37, 0xC0, 0x9A,
+	0xBF, 0x88, 0xA7, 0xD4, 0xED, 0xE1, 0x92, 0x28, 0xC6, 0xA5, 0x7B, 0x0C, 0x91, 0x05, 0x74, 0x08,
+	0x78, 0x48, 0x50, 0xE7, 0x8F, 0x5A, 0xA8, 0x53, 0x92, 0x92, 0xB9, 0x32, 0x94, 0x79, 0x4E, 0x43,
+	0xFE, 0x0B, 0x14, 0x7F, 0xE3, 0x0E, 0x66, 0xFF, 0x00, 0xB1, 0x9A, 0xCB, 0xF9, 0x4B, 0x5F, 0x94,
+	0x27, 0xAD, 0x7E, 0xE2, 0x7E, 0xD1, 0x3F, 0xB3, 0xB7, 0x80, 0x7F, 0x69, 0xBF, 0x87, 0x2D, 0xF0,
+	0xB7, 0xE2, 0x1D, 0xC5, 0xFC, 0x3A, 0x63, 0xDE, 0x45, 0x72, 0xCD, 0xA6, 0xCE, 0x89, 0x36, 0xE4,
+	0x62, 0x07, 0xFA, 0xC4, 0x71, 0xB7, 0xF0, 0xAF, 0x09, 0x5F, 0xF8, 0x22, 0xDF, 0xEC, 0x9D, 0xB7,
+	0xE6, 0xF1, 0x27, 0x8D, 0xB3, 0xDF, 0x1A, 0xCD, 0xB8, 0xFE, 0x56, 0xD5, 0xEE, 0x61, 0x31, 0x94,
+	0x68, 0x51, 0xE5, 0x91, 0xE3, 0xE2, 0xB0, 0x75, 0xAB, 0x54, 0xE6, 0x8E, 0xC7, 0xE5, 0x8D, 0x15,
+	0xFA, 0x9D, 0xFF, 0x00, 0x0E, 0x5B, 0xFD, 0x93, 0x3F, 0xE8, 0x63, 0xF1, 0xC7, 0xFE, 0x0E, 0xAD,
+	0xFF, 0x00, 0xF9, 0x1A, 0x8F, 0xF8, 0x72, 0xDF, 0xEC, 0x99, 0xFF, 0x00, 0x43, 0x1F, 0x8E, 0x3F,
+	0xF0, 0x75, 0x6F, 0xFF, 0x00, 0xC8, 0xD5, 0xD5, 0xFD, 0xA5, 0x87, 0xF3, 0x39, 0x7F, 0xB3, 0xF1,
+	0x1E, 0x47, 0xE5, 0x8D, 0x7E, 0x80, 0x7F, 0xC1, 0x0B, 0x7E, 0xFF, 0x00, 0xC5, 0x1F, 0xF7, 0xB4,
+	0x5F, 0xFD, 0x02, 0xFE, 0xBD, 0x3B, 0xFE, 0x1C, 0xB9, 0xFB, 0x26, 0x7F, 0xD0, 0xC9, 0xE3, 0x7F,
+	0xFC, 0x1D, 0x5B, 0xFF, 0x00, 0xF2, 0x35, 0x7A, 0xB7, 0xEC, 0xBD, 0xFB, 0x16, 0xFC, 0x27, 0xFD,
+	0x90, 0xE5, 0xD7, 0x3F, 0xE1, 0x57, 0xEA, 0x5A, 0xE5, 0xC0, 0xF1, 0x01, 0xB5, 0xFB, 0x77, 0xF6,
+	0xBD, 0xDC, 0x32, 0x32, 0xF9, 0x1E, 0x60, 0x4D, 0x9E, 0x5C, 0x48, 0x7F, 0xE5, 0xB3, 0xE7, 0x35,
+	0xCF, 0x8A, 0xC7, 0x51, 0xAD, 0x4B, 0x95, 0x1D, 0x18, 0x6C, 0x15, 0x6A, 0x55, 0x54, 0x99, 0xE2,
+	0xFF, 0x00, 0xF0, 0x58, 0x2F, 0xF9, 0x00, 0xF8, 0x17, 0xFE, 0xBF, 0xAF, 0xBF, 0xF4, 0x08, 0xEB,
+	0xE1, 0xBA, 0xFD, 0x6B, 0xF8, 0xF3, 0xFB, 0x37, 0x7C, 0x33, 0xFD, 0xA3, 0x6C, 0xB4, 0xDD, 0x3F,
+	0xE2, 0x64, 0x17, 0x72, 0xAE, 0x98, 0xD2, 0x49, 0x6B, 0xF6, 0x3B, 0xA3, 0x1E, 0x5A, 0x45, 0x01,
+	0xBF, 0x44, 0xAF, 0x3D, 0x1F, 0xF0, 0x4B, 0xFF, 0x00, 0xD9, 0x58, 0x0C, 0x7F, 0x63, 0x6B, 0xBF,
+	0xF8, 0x3A, 0x7A, 0xF2, 0xCF, 0x58, 0xFC, 0xD6, 0xA2, 0xBF, 0x4A, 0xBF, 0xE1, 0xD7, 0xFF, 0x00,
+	0xB2, 0xB7, 0xFD, 0x01, 0xF5, 0xCF, 0xFC, 0x1D, 0x3D, 0x1F, 0xF0, 0xEB, 0xFF, 0x00, 0xD9, 0x5B,
+	0xFE, 0x80, 0xFA, 0xE7, 0xFE, 0x0E, 0x9E, 0x80, 0x3F, 0x35, 0x6B, 0xF4, 0xD3, 0xFE, 0x09, 0xAB,
+	0xFF, 0x00, 0x26, 0x8F, 0xA1, 0xFF, 0x00, 0xD7, 0xF5, 0xFF, 0x00, 0xFE, 0x94, 0xB5, 0x55, 0xFF,
+	0x00, 0x87, 0x5F, 0xFE, 0xCA, 0xDF, 0xF4, 0x07, 0xD7, 0x3F, 0xF0, 0x74, 0xF5, 0xEB, 0x9F, 0x09,
+	0xBE, 0x12, 0x78, 0x4F, 0xE0, 0x9F, 0x81, 0xA1, 0xF8, 0x77, 0xE0, 0x4B, 0x69, 0xA2, 0xD3, 0xED,
+	0x5E, 0x56, 0x83, 0xED, 0x33, 0xF9, 0x8F, 0xBA, 0x46, 0xDC, 0x79, 0x3D, 0x68, 0x03, 0xE0, 0xBF,
+	0xF8, 0x2A, 0xBF, 0xFC, 0x9C, 0xB4, 0x5F, 0xF6, 0x2A, 0xDA, 0xFF, 0x00, 0xE8, 0xC9, 0xAB, 0xE6,
+	0xD3, 0xD6, 0xBF, 0x54, 0xBE, 0x36, 0x7E, 0xC6, 0x9F, 0x04, 0xBE, 0x3D, 0x78, 0xD2, 0x3F, 0x1B,
+	0x7C, 0x41, 0xD3, 0xF5, 0x09, 0x75, 0x05, 0xB4, 0x8E, 0xDD, 0x1A, 0xCF, 0x50, 0x68, 0xC0, 0x8E,
+	0x39, 0x09, 0xE7, 0xFE, 0xFB, 0xAF, 0xCA, 0x9F, 0xF8, 0x2D, 0xEF, 0xED, 0x6D, 0xFB, 0x16, 0xFF,
+	0x00, 0xC1, 0x3C, 0xE1, 0x93, 0xF6, 0x76, 0xFD, 0x9A, 0x74, 0xAB, 0xAF, 0x12, 0x7C, 0x60, 0xBC,
+	0x85, 0x5A, 0xF1, 0xA6, 0xD7, 0xA4, 0x96, 0xD7, 0xC2, 0x91, 0xBA, 0xFE, 0xEE, 0x69, 0xB1, 0xF7,
+	0xAE, 0x99, 0x7F, 0xD5, 0xC2, 0x9F, 0x70, 0x7E, 0xF2, 0x41, 0xB4, 0x85, 0x96, 0x5C, 0xB9, 0x56,
+	0xA5, 0x42, 0x2E, 0xA4, 0xAC, 0x8F, 0x74, 0xFD, 0x91, 0x3F, 0x62, 0xAF, 0x17, 0xFE, 0xD2, 0x1A,
+	0xB4, 0x7E, 0x22, 0xD5, 0x84, 0xBA, 0x4F, 0x84, 0x6D, 0xE7, 0xC5, 0xE6, 0xA6, 0x63, 0x1B, 0xEE,
+	0x99, 0x4F, 0x31, 0x5B, 0x02, 0x08, 0x66, 0xFE, 0xF9, 0x20, 0xA0, 0xE7, 0x76, 0xF6, 0xFD, 0xDA,
+	0xFE, 0x90, 0x7C, 0x38, 0xF8, 0x6F, 0xE0, 0xBF, 0x85, 0x3E, 0x16, 0xB6, 0xF0, 0x67, 0xC3, 0xFD,
+	0x0A, 0x1D, 0x3F, 0x4E, 0xB5, 0x41, 0xE5, 0x43, 0x1E, 0x49, 0x76, 0xC6, 0x0B, 0x33, 0x9C, 0x96,
+	0x63, 0xDD, 0x8F, 0x24, 0xF3, 0x5F, 0xC5, 0x07, 0x88, 0xFC, 0x4B, 0xAD, 0xF8, 0xC3, 0x56, 0xBA,
+	0xF1, 0x2F, 0x8B, 0xB5, 0x89, 0xB5, 0x0D, 0x42, 0xFA, 0x4D, 0xF7, 0xD7, 0x97, 0x93, 0x6E, 0x92,
+	0x46, 0x27, 0x39, 0xC7, 0x6C, 0x9E, 0xD5, 0x49, 0xB3, 0xB8, 0xE5, 0x4A, 0xFF, 0x00, 0xB2, 0xDD,
+	0x45, 0x67, 0xED, 0xBC, 0x8E, 0xAF, 0xAA, 0xF9, 0x9F, 0xDC, 0x58, 0x20, 0x0A, 0x5C, 0xD7, 0xF0,
+	0xE7, 0x45, 0x1E, 0xDB, 0xC8, 0x3E, 0xAB, 0xE6, 0x7F, 0x71, 0x99, 0xA3, 0x35, 0xFC, 0x39, 0xD1,
+	0x47, 0xB6, 0xF2, 0x0F, 0xAA, 0xF9, 0x9F, 0xDC, 0x66, 0x68, 0xCD, 0x7F, 0x0E, 0x74, 0x51, 0xED,
+	0xBC, 0x83, 0xEA, 0xBE, 0x67, 0xF7, 0x19, 0x9A, 0x2B, 0xF8, 0x73, 0xAF, 0xDE, 0x0F, 0xF8, 0x33,
+	0x6B, 0xFE, 0x49, 0xA7, 0xC7, 0xAF, 0xFB, 0x18, 0x34, 0x0F, 0xFD, 0x27, 0xBF, 0xAA, 0x8D, 0x4E,
+	0x67, 0x63, 0x3A, 0x94, 0x3D, 0x9C, 0x6F, 0x73, 0xF6, 0xB2, 0x8A, 0x0F, 0x5A, 0x2B, 0x43, 0x9C,
+	0x28, 0xA2, 0x8A, 0x35, 0x0F, 0x40, 0xAF, 0xE5, 0xCB, 0xFE, 0x0E, 0x71, 0xFF, 0x00, 0x94, 0xC2,
+	0xFC, 0x40, 0xFF, 0x00, 0xB0, 0x17, 0x87, 0xFF, 0x00, 0xF4, 0xDB, 0x6F, 0x5F, 0xD4, 0x6D, 0x78,
+	0x0F, 0xC7, 0x4F, 0xF8, 0x25, 0xF7, 0xEC, 0x09, 0xFB, 0x4B, 0xFC, 0x4A, 0xBC, 0xF8, 0xC5, 0xF1,
+	0xF3, 0xF6, 0x58, 0xF0, 0xBF, 0x8A, 0xBC, 0x4F, 0x7D, 0x1C, 0x31, 0xDD, 0x6B, 0x3A, 0xA5, 0xBC,
+	0x8D, 0x34, 0xB1, 0xC2, 0xBB, 0x22, 0x4E, 0x1C, 0x70, 0xAA, 0x00, 0xE9, 0x51, 0x38, 0xF3, 0x46,
+	0xC8, 0xD2, 0x8D, 0x48, 0xD3, 0x97, 0x33, 0x3F, 0x8F, 0x1A, 0x2B, 0xFA, 0xDE, 0x4F, 0xF8, 0x21,
+	0xE7, 0xFC, 0x12, 0x60, 0x22, 0x81, 0xFB, 0x0B, 0x78, 0x17, 0xA7, 0xF0, 0xDA, 0xCB, 0x8F, 0xFD,
+	0x19, 0x51, 0xCD, 0xFF, 0x00, 0x04, 0x41, 0xFF, 0x00, 0x82, 0x4E, 0xEE, 0x65, 0xFF, 0x00, 0x86,
+	0x16, 0xF0, 0x38, 0x56, 0x50, 0x0F, 0xFA, 0x2C, 0xBF, 0x77, 0x38, 0xC7, 0xFA, 0xCE, 0xA7, 0x71,
+	0xC7, 0xD2, 0xB2, 0xF6, 0x52, 0xE5, 0x3A, 0xBE, 0xB7, 0x4C, 0xFE, 0x49, 0x68, 0xAF, 0xD2, 0xAF,
+	0xF8, 0x36, 0x3F, 0xF6, 0x4A, 0xFD, 0x9C, 0x7F, 0x6C, 0x0F, 0xDA, 0xD7, 0xE2, 0x07, 0x81, 0xFF,
+	0x00, 0x69, 0x8F, 0x83, 0xBA, 0x37, 0x8D, 0x34, 0x9D, 0x37, 0xE1, 0xE9, 0xBE, 0xB1, 0xD3, 0xB5,
+	0xB8, 0x5D, 0xE0, 0x8A, 0xE0, 0x5F, 0x5A, 0xAE, 0xF0, 0x33, 0xC3, 0x61, 0xDF, 0x8A, 0xFD, 0xB4,
+	0x5F, 0xF8, 0x21, 0xF7, 0xFC, 0x12, 0x68, 0x8D, 0xC7, 0xF6, 0x17, 0xF0, 0x33, 0x7F, 0xDB, 0xA4,
+	0x83, 0x3F, 0xF8, 0xFD, 0x25, 0x4E, 0x4C, 0xB9, 0x62, 0x21, 0x19, 0x59, 0x9F, 0xC9, 0x0D, 0x15,
+	0xFD, 0x70, 0x7F, 0xC3, 0x8F, 0xBF, 0xE0, 0x93, 0x1F, 0xF4, 0x62, 0x9E, 0x05, 0xFF, 0x00, 0xC0,
+	0x59, 0x7F, 0xF8, 0xE5, 0x1F, 0xF0, 0xE3, 0xDF, 0xF8, 0x24, 0xC7, 0xFD, 0x18, 0xA7, 0x81, 0x7F,
+	0xF0, 0x16, 0x5F, 0xFE, 0x2E, 0x9F, 0xB3, 0x91, 0x1F, 0x5B, 0xA6, 0x7F, 0x23, 0xF4, 0x57, 0xF5,
+	0xBF, 0xFF, 0x00, 0x0E, 0x3D, 0xFF, 0x00, 0x82, 0x4C, 0xFF, 0x00, 0xD1, 0x8A, 0xF8, 0x17, 0xFF,
+	0x00, 0x01, 0x65, 0xFF, 0x00, 0xE3, 0x94, 0x7F, 0xC3, 0x8F, 0x7F, 0xE0, 0x93, 0x3F, 0xF4, 0x62,
+	0xBE, 0x05, 0xFF, 0x00, 0xC0, 0x59, 0x7F, 0xF8, 0xE5, 0x1E, 0xCD, 0x87, 0xD6, 0xA0, 0x7F, 0x24,
+	0x14, 0x57, 0xF5, 0xC1, 0xFF, 0x00, 0x0E, 0x3E, 0xFF, 0x00, 0x82, 0x4C, 0x7F, 0xD1, 0x8A, 0x78,
+	0x17, 0xFF, 0x00, 0x01, 0x65, 0xFF, 0x00, 0xE3, 0x94, 0x7F, 0xC3, 0x8F, 0xBF, 0xE0, 0x93, 0x1F,
+	0xF4, 0x62, 0x9E, 0x05, 0xFF, 0x00, 0xC0, 0x59, 0x7F, 0xF8, 0xE5, 0x1E, 0xCE, 0x41, 0xF5, 0xAA,
+	0x7D, 0x99, 0xFC, 0x8F, 0xD1, 0x5F, 0xD6, 0xFF, 0x00, 0xFC, 0x38, 0xF7, 0xFE, 0x09, 0x33, 0xFF,
+	0x00, 0x46, 0x2B, 0xE0, 0x5F, 0xFC, 0x05, 0x97, 0xFF, 0x00, 0x8E, 0x52, 0x7F, 0xC3, 0x8F, 0x7F,
+	0xE0, 0x93, 0x5F, 0xF4, 0x62, 0xDE, 0x05, 0xFF, 0x00, 0xC0, 0x59, 0x7F, 0xF8, 0xE5, 0x1E, 0xCE,
+	0x41, 0xF5, 0xA8, 0x1F, 0xC9, 0x0D, 0x15, 0xFD, 0x6F, 0xFF, 0x00, 0xC3, 0x8F, 0x7F, 0xE0, 0x93,
+	0x3F, 0xF4, 0x62, 0xDE, 0x06, 0xFF, 0x00, 0xC0, 0x59, 0x7F, 0xF8, 0xBA, 0x3F, 0xE1, 0xC7, 0xBF,
+	0xF0, 0x49, 0x9F, 0xFA, 0x31, 0x6F, 0x03, 0x7F, 0xE0, 0x2C, 0xBF, 0xFC, 0x5D, 0x1E, 0xCE, 0x41,
+	0xF5, 0xBA, 0x67, 0xF2, 0x41, 0x45, 0x7F, 0x5C, 0x1F, 0xF0, 0xE3, 0xDF, 0xF8, 0x24, 0xC7, 0xFD,
+	0x18, 0xA7, 0x81, 0x7F, 0xF0, 0x16, 0x5F, 0xFE, 0x2E, 0x8F, 0xF8, 0x71, 0xEF, 0xFC, 0x12, 0x63,
+	0xFE, 0x8C, 0x53, 0xC0, 0xBF, 0xF8, 0x0B, 0x2F, 0xFF, 0x00, 0x17, 0x47, 0xB3, 0x90, 0x7D, 0x72,
+	0x99, 0xFC, 0x8F, 0xAF, 0x53, 0xF8, 0x7F, 0x23, 0x5F, 0xDC, 0x60, 0xE9, 0x5F, 0x27, 0x37, 0xFC,
+	0x11, 0x0B, 0xFE, 0x09, 0x3A, 0xB3, 0x6D, 0x1F, 0xB0, 0x9F, 0x81, 0x7E, 0x65, 0x03, 0x3F, 0x63,
+	0x97, 0x01, 0x77, 0x0C, 0xE7, 0xF7, 0x9D, 0x49, 0xCE, 0x3E, 0x95, 0xF5, 0x7C, 0x5B, 0xBC, 0xB5,
+	0xDE, 0x41, 0x6D, 0xA3, 0x25, 0x54, 0x80, 0x7F, 0x0E, 0xD5, 0xA5, 0x38, 0xCA, 0x3A, 0x18, 0x56,
+	0xAA, 0xAA, 0x58, 0x75, 0x14, 0x51, 0x5A, 0x18, 0x05, 0x14, 0x51, 0x40, 0x06, 0x68, 0xC8, 0xF5,
+	0xAF, 0xC8, 0xAF, 0xF8, 0x3C, 0x2B, 0xFE, 0x4C, 0x9F, 0xE1, 0x8F, 0xFD, 0x95, 0x41, 0xFF, 0x00,
+	0xA6, 0xCB, 0xBA, 0xFE, 0x7A, 0x2B, 0x39, 0x54, 0xE5, 0x95, 0x8E, 0xAA, 0x78, 0x7F, 0x69, 0x1E,
+	0x6B, 0x9F, 0xDC, 0x66, 0x47, 0xAD, 0x19, 0xAF, 0xE1, 0xCE, 0x8A, 0x9F, 0x6D, 0xE4, 0x57, 0xD5,
+	0x7C, 0xCF, 0xEE, 0x33, 0x34, 0x66, 0xBF, 0x87, 0x3A, 0x28, 0xF6, 0xDE, 0x41, 0xF5, 0x5F, 0x33,
+	0xFB, 0x8C, 0xCD, 0x19, 0xAF, 0xE1, 0xCE, 0x8A, 0x3D, 0xB7, 0x90, 0x7D, 0x57, 0xCC, 0xFE, 0xDE,
+	0xBC, 0x43, 0xE1, 0xED, 0x17, 0xC4, 0xDA, 0x5D, 0xC6, 0x83, 0xE2, 0x0D, 0x3A, 0x1B, 0xCB, 0x3B,
+	0xB8, 0x5A, 0x3B, 0x8B, 0x6B, 0xA8, 0xFC, 0xC4, 0x95, 0x49, 0x19, 0x05, 0x3F, 0x8B, 0x1D, 0x8F,
+	0x6A, 0xFC, 0xFA, 0xFD, 0xB3, 0x3F, 0x60, 0x2D, 0x6F, 0xE0, 0xF1, 0xB8, 0xF8, 0x8D, 0xF0, 0x86,
+	0xD2, 0xE2, 0xFB, 0xC2, 0xBF, 0x7A, 0xEA, 0xC5, 0x57, 0x75, 0xC6, 0x96, 0x49, 0xCF, 0x0D, 0xFC,
+	0x71, 0x76, 0x0F, 0xFC, 0x03, 0x8A, 0xFE, 0x62, 0xA9, 0xD1, 0x5D, 0x5D, 0x59, 0x49, 0x1D, 0xCD,
+	0x95, 0xD4, 0x91, 0x4D, 0x11, 0xF3, 0x92, 0xE2, 0x39, 0x36, 0xC9, 0x13, 0x2B, 0x7C, 0xA4, 0x51,
+	0xED, 0xBC, 0x83, 0xEA, 0xBE, 0x67, 0xEE, 0xD6, 0x41, 0xE5, 0x71, 0x8F, 0xF6, 0x45, 0x7D, 0x25,
+	0xFF, 0x00, 0x04, 0xAD, 0xFF, 0x00, 0x93, 0x9A, 0x9F, 0xFE, 0xC5, 0x6B, 0xEF, 0xFD, 0x1B, 0x6F,
+	0x5F, 0x01, 0xFF, 0x00, 0xC1, 0x13, 0x7F, 0xE0, 0xA0, 0xFF, 0x00, 0xB2, 0x9F, 0xC7, 0x0D, 0x76,
+	0xC7, 0xF6, 0x52, 0xFF, 0x00, 0x82, 0x82, 0x5E, 0x5D, 0x69, 0x7E, 0x26, 0xBE, 0xBD, 0x5B, 0x4F,
+	0x05, 0xF8, 0xF0, 0x6A, 0x82, 0xDE, 0xCF, 0x50, 0x66, 0x5C, 0xAD, 0x9D, 0xE1, 0x3C, 0x43, 0x75,
+	0xD0, 0x47, 0x37, 0xDD, 0x98, 0x7E, 0xEC, 0xE1, 0x86, 0x66, 0xFD, 0xBC, 0xF8, 0x25, 0xFB, 0x17,
+	0xFC, 0x13, 0xF8, 0x0F, 0xE2, 0xF6, 0xF1, 0xBF, 0xC3, 0xDD, 0x37, 0x51, 0x86, 0xFA, 0x4B, 0x36,
+	0xB5, 0x90, 0x5D, 0xEA, 0x46, 0x55, 0x11, 0x33, 0x23, 0x90, 0x01, 0xED, 0x95, 0xEF, 0x5A, 0x46,
+	0x4A, 0x4B, 0x43, 0x96, 0xA4, 0x25, 0x4E, 0x56, 0x66, 0x17, 0xFC, 0x14, 0xAB, 0xFE, 0x4D, 0x2B,
+	0x5E, 0xFF, 0x00, 0xAF, 0xDB, 0x1F, 0xFD, 0x28, 0x5A, 0xFC, 0xCA, 0xAF, 0xD8, 0x6F, 0x8B, 0xBF,
+	0x0A, 0x3C, 0x27, 0xF1, 0xA7, 0xC0, 0xD3, 0x78, 0x03, 0xC7, 0xD1, 0xCC, 0xDA, 0x7D, 0xD4, 0xB1,
+	0xBC, 0xEB, 0x6B, 0x3F, 0x96, 0x49, 0x8D, 0xC3, 0x8E, 0x7F, 0xE0, 0x35, 0xE4, 0x4B, 0xFF, 0x00,
+	0x04, 0xBE, 0xFD, 0x95, 0xC2, 0x80, 0xDA, 0x3E, 0xB9, 0xFF, 0x00, 0x83, 0x97, 0xAA, 0x24, 0xFC,
+	0xD6, 0xA2, 0xBF, 0x4A, 0xBF, 0xE1, 0xD7, 0xFF, 0x00, 0xB2, 0xB7, 0xFD, 0x01, 0xF5, 0xCF, 0xFC,
+	0x1D, 0x3D, 0x1F, 0xF0, 0xEB, 0xFF, 0x00, 0xD9, 0x5B, 0xFE, 0x80, 0xFA, 0xE7, 0xFE, 0x0E, 0x9E,
+	0x80, 0x3F, 0x35, 0x6B, 0xEE, 0x3F, 0xF8, 0x24, 0x1F, 0xFC, 0x8B, 0x7E, 0x3A, 0xFF, 0x00, 0xAF,
+	0xFB, 0x1F, 0xFD, 0x15, 0x71, 0x5E, 0x8F, 0xFF, 0x00, 0x0E, 0xBF, 0xFD, 0x95, 0xBF, 0xE8, 0x0F,
+	0xAE, 0x7F, 0xE0, 0xE9, 0xEB, 0xD0, 0xBE, 0x04, 0xFE, 0xCD, 0xBF, 0x0C, 0x3F, 0x67, 0x18, 0x75,
+	0x2D, 0x3B, 0xE1, 0xCD, 0xAD, 0xE4, 0x71, 0xEA, 0xF3, 0x23, 0xDD, 0xFD, 0xB2, 0xF4, 0xC8, 0x7E,
+	0x45, 0xDA, 0xB8, 0xFF, 0x00, 0xBE, 0xA8, 0x03, 0xE3, 0xDF, 0xF8, 0x2E, 0xBF, 0xFA, 0xCF, 0x85,
+	0xBF, 0xEE, 0xEB, 0x7F, 0xCF, 0x4F, 0xAF, 0xCF, 0xDA, 0xFD, 0xA4, 0xFD, 0xA9, 0xFF, 0x00, 0x62,
+	0xFF, 0x00, 0x85, 0x1F, 0xB5, 0xD9, 0xD0, 0x7F, 0xE1, 0x68, 0x6A, 0x7A, 0xD4, 0x2D, 0xE1, 0xF5,
+	0xBA, 0xFB, 0x0A, 0xE9, 0x57, 0x89, 0x16, 0x5A, 0x6F, 0x28, 0xB1, 0x7D, 0xF1, 0xB8, 0xEB, 0x0A,
+	0x63, 0x8A, 0xF2, 0x74, 0xFF, 0x00, 0x82, 0x2D, 0xFE, 0xC9, 0xA1, 0x14, 0x7F, 0xC2, 0x49, 0xE3,
+	0x8F, 0xBB, 0xFC, 0x5A, 0xD5, 0xBE, 0x7F, 0xF4, 0x9A, 0xBD, 0x4C, 0x2E, 0x36, 0x8D, 0x1A, 0x2A,
+	0x2C, 0xF2, 0x71, 0x18, 0x3A, 0xD5, 0x6B, 0x39, 0x2B, 0x1F, 0x96, 0x74, 0x57, 0xEA, 0x77, 0xFC,
+	0x39, 0x6F, 0xF6, 0x4C, 0xFF, 0x00, 0xA1, 0x8F, 0xC6, 0xFF, 0x00, 0xF8, 0x3A, 0xB7, 0xFF, 0x00,
+	0xE4, 0x6A, 0x3F, 0xE1, 0xCB, 0x7F, 0xB2, 0x67, 0xFD, 0x0C, 0x7E, 0x38, 0xFF, 0x00, 0xC1, 0xD5,
+	0xBF, 0xFF, 0x00, 0x23, 0x57, 0x47, 0xF6, 0x96, 0x1C, 0xE7, 0xFE, 0xCF, 0xC4, 0x79, 0x1F, 0x96,
+	0x35, 0xFA, 0xB7, 0xFF, 0x00, 0x04, 0x78, 0xFF, 0x00, 0x93, 0x39, 0x4F, 0xFB, 0x19, 0x75, 0x0F,
+	0xFD, 0xA5, 0x54, 0xBF, 0xE1, 0xCB, 0x7F, 0xB2, 0x67, 0xFD, 0x0C, 0x9E, 0x37, 0xFF, 0x00, 0xC1,
+	0xD5, 0xBF, 0xFF, 0x00, 0x23, 0x57, 0xBC, 0xFE, 0xCE, 0x7F, 0xB3, 0xA7, 0x80, 0xFF, 0x00, 0x66,
+	0x2F, 0x87, 0x91, 0xFC, 0x30, 0xF8, 0x79, 0x75, 0xA8, 0x4D, 0xA7, 0xC7, 0x7D, 0x35, 0xD0, 0x7D,
+	0x4A, 0xE8, 0x49, 0x36, 0xE7, 0x6C, 0x9C, 0xE0, 0x01, 0x8F, 0xA0, 0x03, 0xDA, 0xB9, 0x71, 0x58,
+	0xCA, 0x58, 0x8A, 0x56, 0x8F, 0x73, 0xAB, 0x07, 0x83, 0xAD, 0x46, 0xA7, 0x34, 0x8F, 0x9A, 0xBF,
+	0x6C, 0xFF, 0x00, 0xF9, 0x2F, 0xBA, 0x8F, 0xFD, 0x7B, 0x5A, 0x7F, 0xE8, 0x15, 0xE5, 0x23, 0xA5,
+	0x7D, 0xAF, 0xF1, 0x3F, 0xF6, 0x54, 0xF8, 0x7F, 0xF1, 0x5B, 0xC5, 0x13, 0x78, 0xB7, 0xC4, 0x5A,
+	0xAE, 0xA9, 0x0D, 0xD4, 0xF0, 0xA4, 0x53, 0x2D, 0x8D, 0xC2, 0x22, 0x95, 0x5F, 0xBB, 0xC6, 0xC3,
+	0xFC, 0xEB, 0x9F, 0x3F, 0xB0, 0x77, 0xC2, 0x69, 0x1B, 0x79, 0xF1, 0x16, 0xBC, 0xBB, 0xB9, 0xC7,
+	0xDA, 0x60, 0xE3, 0xF3, 0x80, 0xFF, 0x00, 0x33, 0x5F, 0xC1, 0x5C, 0x71, 0xE0, 0x17, 0x1D, 0x71,
+	0x07, 0x17, 0x63, 0x33, 0x2C, 0x2F, 0xB3, 0xF6, 0x75, 0x66, 0xE5, 0x1B, 0xCA, 0xCE, 0xCE, 0xDB,
+	0xAB, 0x1F, 0xB9, 0x64, 0xFC, 0x71, 0x92, 0xE0, 0x32, 0xBA, 0x38, 0x7A, 0x9C, 0xDC, 0xD1, 0x8A,
+	0x4F, 0x45, 0xBA, 0xF9, 0x9F, 0x24, 0x51, 0x5F, 0x5B, 0xFF, 0x00, 0xC3, 0x05, 0xFC, 0x24, 0xFF,
+	0x00, 0xA1, 0x97, 0x5E, 0xFF, 0x00, 0xC0, 0x88, 0x3F, 0xF8, 0xC5, 0x1F, 0xF0, 0xC1, 0x7F, 0x09,
+	0x3F, 0xE8, 0x65, 0xD7, 0xBF, 0xF0, 0x22, 0x0F, 0xFE, 0x31, 0x5F, 0x29, 0xFF, 0x00, 0x12, 0xCF,
+	0xE2, 0x37, 0x6A, 0x7F, 0xF8, 0x1F, 0xFC, 0x03, 0xD3, 0xFF, 0x00, 0x88, 0x87, 0x90, 0xF6, 0x9F,
+	0xDC, 0xBF, 0xCC, 0xF9, 0x22, 0xBF, 0x41, 0x3E, 0x09, 0x7F, 0xC9, 0x1B, 0xF0, 0x9F, 0xFD, 0x8B,
+	0x76, 0x5F, 0xFA, 0x21, 0x2B, 0xCC, 0x4F, 0xEC, 0x19, 0xF0, 0x93, 0x9F, 0xF8, 0x9F, 0xEB, 0xFF,
+	0x00, 0xF8, 0x19, 0x0F, 0xFF, 0x00, 0x1A, 0xAF, 0x66, 0xF0, 0xAF, 0x87, 0xEC, 0xFC, 0x27, 0xE1,
+	0x8D, 0x3B, 0xC2, 0xFA, 0x74, 0x92, 0x35, 0xBE, 0x9B, 0x63, 0x0D, 0xAC, 0x2D, 0x33, 0x02, 0xE5,
+	0x23, 0x40, 0xA0, 0x92, 0x00, 0x04, 0xE0, 0x73, 0x80, 0x2B, 0xF7, 0x6F, 0x02, 0x7C, 0x2B, 0xE2,
+	0x8F, 0x0F, 0x73, 0x6C, 0x66, 0x23, 0x35, 0x50, 0xE5, 0xAB, 0x08, 0xC6, 0x3C, 0xAE, 0xFA, 0xA9,
+	0x5D, 0xDF, 0x45, 0xD0, 0xF8, 0xDE, 0x32, 0xE2, 0x4C, 0xBF, 0x3E, 0xC3, 0xD2, 0x86, 0x1A, 0xFE,
+	0xEB, 0x6D, 0xDD, 0x5B, 0x74, 0xBC, 0xD9, 0xF9, 0x63, 0xFB, 0x69, 0xFF, 0x00, 0xC9, 0xD7, 0x78,
+	0xDB, 0xFE, 0xC3, 0x87, 0xFF, 0x00, 0x41, 0x5A, 0xF2, 0xC4, 0xFB, 0x83, 0xE9, 0x5F, 0xA8, 0x5F,
+	0x11, 0x7F, 0xE0, 0x9F, 0xBF, 0xB3, 0x9F, 0xC4, 0xFF, 0x00, 0x1A, 0x6A, 0x5E, 0x3D, 0xF1, 0x6E,
+	0x9D, 0xAA, 0x36, 0xA1, 0xA9, 0xDD, 0x0B, 0x8B, 0xD6, 0x83, 0x56, 0x91, 0x14, 0x9E, 0x7A, 0x01,
+	0xD0, 0x64, 0xF4, 0xED, 0x58, 0xEB, 0xFF, 0x00, 0x04, 0xBE, 0xFD, 0x95, 0x82, 0xE0, 0xE9, 0x1A,
+	0xE7, 0xFE, 0x0E, 0xA4, 0xAF, 0xE9, 0x83, 0xE0, 0x0F, 0xCD, 0x6A, 0x2B, 0xF4, 0xAB, 0xFE, 0x1D,
+	0x7F, 0xFB, 0x2B, 0x7F, 0xD0, 0x1F, 0x5C, 0xFF, 0x00, 0xC1, 0xD3, 0xD1, 0xFF, 0x00, 0x0E, 0xBF,
+	0xFD, 0x95, 0xBF, 0xE8, 0x0F, 0xAE, 0x7F, 0xE0, 0xE9, 0xE8, 0x03, 0xF3, 0x56, 0xBE, 0xF4, 0xFF,
+	0x00, 0x82, 0x42, 0xFF, 0x00, 0xC9, 0x35, 0xF1, 0x87, 0xFD, 0x87, 0x20, 0xFF, 0x00, 0xD1, 0x35,
+	0xDB, 0x7F, 0xC3, 0xAF, 0xFF, 0x00, 0x65, 0x6F, 0xFA, 0x03, 0xEB, 0x9F, 0xF8, 0x3A, 0x7A, 0xF4,
+	0x2F, 0x80, 0x7F, 0xB3, 0xFF, 0x00, 0xC3, 0xCF, 0xD9, 0xDD, 0x35, 0x9F, 0x0C, 0x7C, 0x36, 0xB4,
+	0xBA, 0x8E, 0xDE, 0xF0, 0xC1, 0x75, 0x22, 0x5D, 0xDD, 0x79, 0x8C, 0x5F, 0x12, 0x28, 0xE7, 0xB7,
+	0xDD, 0xA0, 0x0F, 0x89, 0xBF, 0xE0, 0xAA, 0x3F, 0xF2, 0x73, 0x36, 0xFF, 0x00, 0xF6, 0x2C, 0x5A,
+	0xFF, 0x00, 0xE8, 0x72, 0xD7, 0xCD, 0x95, 0xFA, 0x9B, 0xF1, 0x77, 0xF6, 0x37, 0xF8, 0x2D, 0xFB,
+	0x43, 0x78, 0xE6, 0x6F, 0x1B, 0xFC, 0x46, 0xB1, 0xD4, 0x66, 0xBE, 0x86, 0x18, 0xEC, 0xD5, 0xAC,
+	0x75, 0x03, 0x1A, 0x88, 0xD1, 0x4B, 0x0C, 0x81, 0xFE, 0xD3, 0xB5, 0x73, 0x9F, 0xF0, 0xEB, 0xFF,
+	0x00, 0xD9, 0x5B, 0xFE, 0x80, 0xFA, 0xE7, 0xFE, 0x0E, 0x9E, 0x80, 0x3F, 0x35, 0x68, 0xAF, 0xD2,
+	0xAF, 0xF8, 0x75, 0xFF, 0x00, 0xEC, 0xAD, 0xFF, 0x00, 0x40, 0x7D, 0x73, 0xFF, 0x00, 0x07, 0x4F,
+	0x47, 0xFC, 0x3A, 0xFF, 0x00, 0xF6, 0x56, 0xFF, 0x00, 0xA0, 0x3E, 0xB9, 0xFF, 0x00, 0x83, 0xA7,
+	0xA0, 0x0F, 0xCD, 0x5E, 0xDF, 0x85, 0x7D, 0xD1, 0xFF, 0x00, 0x04, 0x80, 0xFF, 0x00, 0x91, 0x73,
+	0xC7, 0xDF, 0xF6, 0x10, 0xB0, 0xFF, 0x00, 0xD1, 0x73, 0x57, 0xA0, 0x9F, 0xF8, 0x26, 0x07, 0xEC,
+	0xAC, 0xBF, 0x37, 0xF6, 0x3E, 0xB9, 0xC7, 0x3F, 0xF2, 0x1A, 0x7A, 0xF4, 0x6F, 0x80, 0x7F, 0xB3,
+	0x67, 0xC3, 0x3F, 0xD9, 0xC7, 0x4F, 0xD5, 0x2C, 0x3E, 0x18, 0xD8, 0xDE, 0x43, 0x1E, 0xA8, 0xF0,
+	0xBD, 0xCA, 0xDE, 0xDD, 0x19, 0x0B, 0x34, 0x6A, 0xC1, 0x70, 0x4F, 0x4F, 0xBC, 0x68, 0x03, 0xE2,
+	0x3F, 0xF8, 0x2A, 0x8F, 0xFC, 0x9C, 0xCD, 0xBF, 0xFD, 0x8B, 0x16, 0xBF, 0xFA, 0x1C, 0xB5, 0xF3,
+	0x65, 0x7E, 0xA6, 0xFC, 0x5D, 0xFD, 0x8D, 0xFE, 0x0B, 0x7E, 0xD0, 0xDE, 0x39, 0x9B, 0xC6, 0xFF,
+	0x00, 0x11, 0xAC, 0x75, 0x19, 0xAF, 0xA1, 0x86, 0x3B, 0x35, 0x6B, 0x1D, 0x40, 0xC6, 0xA2, 0x34,
+	0x52, 0xC3, 0x20, 0x7F, 0xB4, 0xED, 0x5C, 0xE7, 0xFC, 0x3A, 0xFF, 0x00, 0xF6, 0x56, 0xFF, 0x00,
+	0xA0, 0x3E, 0xB9, 0xFF, 0x00, 0x83, 0xA7, 0xA0, 0x0F, 0xCD, 0x5A, 0x2B, 0xF4, 0xAB, 0xFE, 0x1D,
+	0x7F, 0xFB, 0x2B, 0x7F, 0xD0, 0x1F, 0x5C, 0xFF, 0x00, 0xC1, 0xD3, 0xD1, 0xFF, 0x00, 0x0E, 0xBF,
+	0xFD, 0x95, 0xBF, 0xE8, 0x0F, 0xAE, 0x7F, 0xE0, 0xE9, 0xE8, 0x03, 0xF3, 0x57, 0xB7, 0xE1, 0x5F,
+	0x73, 0x7F, 0xC1, 0x20, 0xFF, 0x00, 0xE4, 0x5D, 0xF1, 0xE7, 0xFD, 0x84, 0x2C, 0x7F, 0xF4, 0x5C,
+	0xD5, 0xE8, 0x67, 0xFE, 0x09, 0x81, 0xFB, 0x2B, 0x2F, 0xCD, 0xFD, 0x8F, 0xAE, 0x71, 0xCF, 0xFC,
+	0x86, 0x9E, 0xBD, 0x0F, 0xE0, 0x3F, 0xEC, 0xD5, 0xF0, 0xD3, 0xF6, 0x72, 0xB4, 0xD4, 0x2C, 0x7E,
+	0x18, 0xD9, 0x5E, 0x41, 0x1E, 0xA7, 0x24, 0x4D, 0x74, 0x2F, 0x6E, 0x8C, 0xA4, 0x98, 0xD4, 0x85,
+	0xC6, 0x7D, 0x89, 0xA0, 0x0F, 0x44, 0x83, 0xF8, 0xBF, 0xDE, 0x1F, 0xFA, 0x08, 0xA9, 0x2A, 0x2B,
+	0x4F, 0xB8, 0xC0, 0x05, 0xC6, 0xE3, 0x8D, 0xAD, 0xFC, 0xF8, 0xE0, 0xE7, 0xEB, 0x52, 0xD0, 0x01,
+	0x4D, 0x90, 0x91, 0x1B, 0x10, 0x3F, 0x86, 0x9D, 0x48, 0xE3, 0x28, 0x46, 0x3B, 0x50, 0x07, 0xCC,
+	0xDF, 0xB7, 0x67, 0xED, 0x6D, 0xF1, 0x1F, 0xF6, 0x5E, 0xF1, 0x1F, 0x87, 0xA2, 0xF0, 0x0E, 0x91,
+	0xA2, 0x5E, 0x7F, 0x6D, 0x5A, 0xCC, 0xF7, 0x7F, 0xDB, 0x16, 0xF3, 0x36, 0x3C, 0xA2, 0xA0, 0x63,
+	0x64, 0xA9, 0xCF, 0xCF, 0x5E, 0x0F, 0xFF, 0x00, 0x0F, 0x67, 0xFD, 0xA2, 0x3F, 0xE8, 0x4C, 0xF0,
+	0x5F, 0xFE, 0x00, 0xDE, 0xFF, 0x00, 0xF2, 0x4D, 0x74, 0xDF, 0xF0, 0x57, 0xB1, 0xB7, 0xC4, 0x5E,
+	0x05, 0x5F, 0x4B, 0x1B, 0xEF, 0xFD, 0x0E, 0x3A, 0xF8, 0xDE, 0x80, 0x3E, 0xA2, 0xFF, 0x00, 0x87,
+	0xB3, 0xFE, 0xD1, 0x1F, 0xF4, 0x26, 0x78, 0x2F, 0xFF, 0x00, 0x00, 0x6F, 0x7F, 0xF9, 0x26, 0x8F,
+	0xF8, 0x7B, 0x3F, 0xED, 0x11, 0xFF, 0x00, 0x42, 0x67, 0x82, 0xFF, 0x00, 0xF0, 0x06, 0xF7, 0xFF,
+	0x00, 0x92, 0x6B, 0xE5, 0xDA, 0x28, 0x03, 0xEA, 0x26, 0xFF, 0x00, 0x82, 0xB3, 0x7E, 0xD1, 0x05,
+	0x70, 0x3C, 0x17, 0xE0, 0xCF, 0xF8, 0x0D, 0x85, 0xE9, 0x3F, 0xFA, 0x52, 0x3F, 0x98, 0xAF, 0x68,
+	0xFD, 0x86, 0xBF, 0x6D, 0x1F, 0x8A, 0x9F, 0xB4, 0xCF, 0x8F, 0xF5, 0x8F, 0x09, 0x78, 0xEF, 0x46,
+	0xD0, 0x2C, 0xA0, 0xD3, 0xF4, 0x9F, 0xB5, 0xC6, 0xDA, 0x2C, 0x33, 0x47, 0x21, 0x3E, 0x64, 0x71,
+	0xFC, 0xDE, 0x64, 0xD2, 0x7A, 0xD7, 0xE7, 0xA8, 0xEB, 0x5F, 0x58, 0x7F, 0xC1, 0x23, 0xFF, 0x00,
+	0xE4, 0xB5, 0x78, 0x97, 0xFE, 0xC5, 0x55, 0xFF, 0x00, 0xD2, 0x98, 0xA8, 0x03, 0xE9, 0x3F, 0xDB,
+	0x7F, 0xF6, 0x82, 0xF1, 0xA7, 0xEC, 0xD5, 0xF0, 0xC3, 0x4F, 0xF1, 0xDF, 0x80, 0xEC, 0x34, 0xDB,
+	0xAB, 0xAB, 0x9F, 0x10, 0x43, 0x62, 0xD0, 0xEA, 0x90, 0xC8, 0xF0, 0x14, 0x78, 0xA6, 0x91, 0x8F,
+	0xC9, 0x22, 0x73, 0x98, 0xAB, 0xE5, 0xEF, 0xF8, 0x7B, 0x3F, 0xED, 0x11, 0xFF, 0x00, 0x42, 0x67,
+	0x82, 0xFF, 0x00, 0xF0, 0x06, 0xF7, 0xFF, 0x00, 0x92, 0x6B, 0xDA, 0xFF, 0x00, 0xE0, 0xAC, 0xBF,
+	0xF2, 0x6E, 0x3A, 0x3F, 0xFD, 0x8E, 0x76, 0xBF, 0xFA, 0x4B, 0x7B, 0x5F, 0x9E, 0x54, 0xA2, 0x07,
+	0xD4, 0x5F, 0xF0, 0xF6, 0x7F, 0xDA, 0x23, 0xFE, 0x84, 0xCF, 0x05, 0xFF, 0x00, 0xE0, 0x0D, 0xEF,
+	0xFF, 0x00, 0x24, 0xD1, 0xFF, 0x00, 0x0F, 0x67, 0xFD, 0xA2, 0x3F, 0xE8, 0x4C, 0xF0, 0x5F, 0xFE,
+	0x00, 0xDE, 0xFF, 0x00, 0xF2, 0x4D, 0x7C, 0xBB, 0x45, 0x30, 0x3E, 0xA2, 0xFF, 0x00, 0x87, 0xB3,
+	0xFE, 0xD1, 0x1F, 0xF4, 0x26, 0x78, 0x2F, 0xFF, 0x00, 0x00, 0x6F, 0x7F, 0xF9, 0x26, 0xBD, 0x1B,
+	0xF6, 0x46, 0xFD, 0xBF, 0xBE, 0x33, 0x7C, 0x7B, 0xF8, 0xE5, 0xA7, 0xFC, 0x32, 0xF1, 0x87, 0x87,
+	0x7C, 0x35, 0x6B, 0x65, 0x79, 0x6B, 0x71, 0x23, 0xC9, 0xA6, 0xDA, 0xDC, 0x47, 0x71, 0xFB, 0xB8,
+	0x9D, 0xFF, 0x00, 0x8E, 0xE2, 0x4A, 0xF8, 0x5E, 0xBD, 0xEB, 0xFE, 0x09, 0xB1, 0xFF, 0x00, 0x27,
+	0x73, 0xA0, 0xFF, 0x00, 0xD8, 0x3F, 0x50, 0xFF, 0x00, 0xD2, 0x77, 0xA0, 0x0F, 0xBA, 0xBF, 0x6A,
+	0xFF, 0x00, 0x8A, 0x9E, 0x23, 0xF8, 0x1D, 0xF0, 0x27, 0x5C, 0xF8, 0xA1, 0xE1, 0x28, 0x6D, 0x6E,
+	0x2F, 0xF4, 0xB5, 0xB6, 0x30, 0xC7, 0x7D, 0x1B, 0xBC, 0x4E, 0xD2, 0x5C, 0xC5, 0x09, 0xDF, 0xB1,
+	0xD3, 0xF8, 0x64, 0x15, 0xF1, 0xEF, 0xFC, 0x3D, 0x9F, 0xF6, 0x89, 0xEF, 0xE0, 0xBF, 0x04, 0xFF,
+	0x00, 0xC0, 0x6C, 0x6F, 0x31, 0xFF, 0x00, 0xA5, 0x35, 0xF5, 0x0F, 0xFC, 0x14, 0x47, 0xFE, 0x4C,
+	0xEF, 0xC6, 0x3F, 0xEE, 0x59, 0x7F, 0xE9, 0xC2, 0xD6, 0xBF, 0x2F, 0x29, 0x20, 0x3E, 0xA2, 0xFF,
+	0x00, 0x87, 0xB3, 0xFE, 0xD1, 0x1F, 0xF4, 0x26, 0x78, 0x2F, 0xFF, 0x00, 0x00, 0x6F, 0x7F, 0xF9,
+	0x26, 0x8F, 0xF8, 0x7B, 0x3F, 0xED, 0x11, 0xFF, 0x00, 0x42, 0x67, 0x82, 0xFF, 0x00, 0xF0, 0x06,
+	0xF7, 0xFF, 0x00, 0x92, 0x6B, 0xE5, 0xDA, 0x29, 0x81, 0xF5, 0x17, 0xFC, 0x3D, 0x9F, 0xF6, 0x88,
+	0xFF, 0x00, 0xA1, 0x33, 0xC1, 0x7F, 0xF8, 0x03, 0x7B, 0xFF, 0x00, 0xC9, 0x35, 0xD3, 0x7C, 0x10,
+	0xFF, 0x00, 0x82, 0x95, 0xFC, 0x77, 0xF8, 0x99, 0xF1, 0x8F, 0xC3, 0x7F, 0x0F, 0xB5, 0xCF, 0x0B,
+	0x78, 0x4E, 0xDE, 0xCF, 0x5A, 0xD5, 0xE2, 0xB4, 0x9A, 0x5B, 0x6B, 0x3B, 0x94, 0x98, 0x07, 0x75,
+	0x1F, 0x29, 0x7B, 0x96, 0xF4, 0xF4, 0x1F, 0x4A, 0xF8, 0xDE, 0xBD, 0x13, 0xF6, 0x4A, 0xFF, 0x00,
+	0x93, 0x9C, 0xF0, 0x0F, 0xFD, 0x8D, 0x56, 0x9F, 0xFA, 0x10, 0xA0, 0x0F, 0xD3, 0xCF, 0x8E, 0x1E,
+	0x2D, 0xD5, 0xBE, 0x1E, 0x7C, 0x1B, 0xF1, 0x57, 0x8F, 0xFC, 0x3C, 0xB1, 0xCB, 0x7D, 0xA1, 0xF8,
+	0x6E, 0xFB, 0x50, 0xB5, 0x4B, 0x85, 0x66, 0x56, 0x92, 0x0B, 0x79, 0x25, 0x45, 0x7D, 0xAC, 0xA7,
+	0x6E, 0x57, 0x1D, 0x7F, 0x1A, 0xF8, 0x14, 0x7F, 0xC1, 0x63, 0xBF, 0x69, 0xA0, 0x30, 0xBE, 0x03,
+	0xF0, 0x16, 0x3B, 0x6D, 0xD3, 0x2F, 0x48, 0xFC, 0x3F, 0xD3, 0x2B, 0xEE, 0xCF, 0xDA, 0x9B, 0xFE,
+	0x4D, 0x93, 0xE2, 0x2F, 0xFD, 0x88, 0xBA, 0xBF, 0xFE, 0x90, 0x4F, 0x5F, 0x8C, 0x35, 0xCF, 0x56,
+	0x52, 0x8D, 0x9A, 0x2E, 0x31, 0x52, 0xDC, 0xFA, 0xCB, 0xFE, 0x1F, 0x1F, 0xFB, 0x4E, 0x7F, 0xD0,
+	0x89, 0xE0, 0x3F, 0xFC, 0x15, 0xDE, 0xFF, 0x00, 0xF2, 0x65, 0x1F, 0xF0, 0xF8, 0xFF, 0x00, 0xDA,
+	0x73, 0xFE, 0x84, 0x4F, 0x01, 0xFF, 0x00, 0xE0, 0xAE, 0xF7, 0xFF, 0x00, 0x93, 0x2B, 0xE4, 0xDA,
+	0x2B, 0x2F, 0x69, 0x53, 0xB9, 0x7C, 0xB1, 0x3E, 0xB2, 0xFF, 0x00, 0x87, 0xC7, 0xFE, 0xD3, 0x9F,
+	0xF4, 0x22, 0x78, 0x0F, 0xFF, 0x00, 0x05, 0x77, 0xBF, 0xFC, 0x99, 0x5E, 0xAD, 0xFB, 0x17, 0xFF,
+	0x00, 0xC1, 0x44, 0xFE, 0x37, 0x7E, 0xD1, 0xFF, 0x00, 0x1D, 0xEC, 0x7E, 0x16, 0xF8, 0xD3, 0xC3,
+	0x3E, 0x15, 0xB4, 0xB0, 0xBB, 0xB0, 0xBA, 0x9A, 0x49, 0xB4, 0xBB, 0x2B, 0x98, 0xEE, 0x10, 0xC6,
+	0xA1, 0xC7, 0x32, 0x5C, 0xB8, 0xDA, 0x73, 0xE9, 0x5F, 0x9E, 0xF5, 0xF4, 0x67, 0xFC, 0x12, 0xAB,
+	0xFE, 0x4F, 0x17, 0x4A, 0xFF, 0x00, 0xB0, 0x3D, 0xFF, 0x00, 0xFE, 0x88, 0x6A, 0x70, 0xA9, 0x51,
+	0xC9, 0x5D, 0x84, 0xA3, 0x15, 0x1D, 0x8F, 0xB7, 0xFF, 0x00, 0x6F, 0x4F, 0xDA, 0x33, 0xC7, 0x3F,
+	0xB2, 0xD7, 0xC0, 0xB6, 0xF8, 0xAD, 0xE0, 0x0D, 0x27, 0x4B, 0xBC, 0xD4, 0x17, 0x56, 0xB7, 0xB4,
+	0xFB, 0x3E, 0xB1, 0x04, 0xD2, 0x41, 0xB5, 0xC3, 0x9D, 0xD8, 0x8E, 0x44, 0x39, 0xFC, 0x6B, 0xE2,
+	0xC1, 0xFF, 0x00, 0x05, 0xAF, 0xFD, 0xAA, 0x00, 0xC1, 0xF0, 0x37, 0xC3, 0xEF, 0xFC, 0x15, 0xDE,
+	0xFF, 0x00, 0xF2, 0x65, 0x7D, 0x35, 0xFF, 0x00, 0x05, 0x8A, 0x3F, 0xF1, 0x87, 0x33, 0x7F, 0xD8,
+	0xCD, 0x65, 0xFC, 0xA5, 0xAF, 0xCA, 0x13, 0xD6, 0xBE, 0x8B, 0x03, 0x87, 0xA5, 0x56, 0x8F, 0x34,
+	0xD5, 0xCF, 0x07, 0x1D, 0x88, 0xAB, 0x4E, 0xA7, 0x2C, 0x1D, 0x8F, 0xB1, 0x3F, 0xE1, 0xF6, 0x3F,
+	0xB5, 0x47, 0xFD, 0x08, 0xDF, 0x0F, 0x7F, 0xF0, 0x57, 0x7B, 0xFF, 0x00, 0xC9, 0x94, 0x7F, 0xC3,
+	0xEC, 0x7F, 0x6A, 0x8F, 0xFA, 0x11, 0x7E, 0x1E, 0xFF, 0x00, 0xE0, 0xAE, 0xF7, 0xFF, 0x00, 0x93,
+	0x2B, 0xE3, 0xBA, 0x2B, 0xB3, 0xEA, 0x78, 0x6F, 0xE5, 0x39, 0x3E, 0xB9, 0x88, 0xFE, 0x66, 0x7D,
+	0x89, 0xFF, 0x00, 0x0F, 0xAF, 0xFD, 0xAA, 0x3F, 0xE8, 0x47, 0xF8, 0x7F, 0xFF, 0x00, 0x82, 0xBB,
+	0xDF, 0xFE, 0x4C, 0xAF, 0xA6, 0xBF, 0xE0, 0x9C, 0x1F, 0xB6, 0xBF, 0xC5, 0x6F, 0xDB, 0x0E, 0x7F,
+	0x1A, 0x1F, 0x89, 0x7A, 0x0F, 0x87, 0xAC, 0x4F, 0x87, 0xFF, 0x00, 0xB3, 0xD6, 0xC5, 0x74, 0x5B,
+	0x49, 0x50, 0x31, 0xB8, 0x17, 0x24, 0xB3, 0xF9, 0x92, 0xB9, 0xEB, 0x02, 0xE3, 0x15, 0xF9, 0x43,
+	0x5F, 0xA0, 0x1F, 0xF0, 0x42, 0xDF, 0xBF, 0xF1, 0x47, 0xFD, 0xED, 0x17, 0xFF, 0x00, 0x40, 0xBF,
+	0xAE, 0x7C, 0x66, 0x1E, 0x8D, 0x3A, 0x0E, 0x51, 0x5A, 0x9D, 0x18, 0x4C, 0x45, 0x6A, 0x95, 0xD2,
+	0x94, 0xB4, 0x3E, 0x83, 0xFD, 0xBA, 0xFF, 0x00, 0x6A, 0x9F, 0x88, 0x7F, 0xB3, 0x0E, 0x95, 0xE1,
+	0xAD, 0x4B, 0xC0, 0x3A, 0x5E, 0x91, 0x78, 0xDA, 0xC5, 0xC4, 0xF1, 0xDD, 0x7F, 0x6C, 0x5B, 0xCC,
+	0xFB, 0x44, 0x61, 0x08, 0xC7, 0x96, 0xE8, 0x7F, 0xE5, 0xA5, 0x7C, 0xEC, 0xBF, 0xF0, 0x56, 0x7F,
+	0xDA, 0x27, 0x68, 0xCF, 0x83, 0x3C, 0x17, 0xFF, 0x00, 0x80, 0x37, 0xBF, 0xFC, 0x93, 0x5E, 0x85,
+	0xFF, 0x00, 0x05, 0x82, 0xFF, 0x00, 0x90, 0x0F, 0x81, 0x7F, 0xEB, 0xFA, 0xFB, 0xFF, 0x00, 0x40,
+	0x8E, 0xBE, 0x1B, 0xAF, 0x14, 0xF6, 0xCF, 0xA8, 0xBF, 0xE1, 0xEC, 0xFF, 0x00, 0xB4, 0x47, 0xFD,
+	0x09, 0x9E, 0x0B, 0xFF, 0x00, 0xC0, 0x1B, 0xDF, 0xFE, 0x49, 0xA3, 0xFE, 0x1E, 0xCF, 0xFB, 0x44,
+	0x7F, 0xD0, 0x99, 0xE0, 0xBF, 0xFC, 0x01, 0xBD, 0xFF, 0x00, 0xE4, 0x9A, 0xF9, 0x76, 0x8A, 0x00,
+	0xFA, 0x8B, 0xFE, 0x1E, 0xCF, 0xFB, 0x44, 0x7F, 0xD0, 0x99, 0xE0, 0xBF, 0xFC, 0x01, 0xBD, 0xFF,
+	0x00, 0xE4, 0x9A, 0xFA, 0xFF, 0x00, 0xF6, 0x45, 0xF8, 0xC3, 0xE2, 0x6F, 0x8F, 0x5F, 0x03, 0xF4,
+	0xDF, 0x89, 0xBE, 0x30, 0xB0, 0xB1, 0xB7, 0xBE, 0xBC, 0xB8, 0xB9, 0x49, 0x21, 0xD3, 0x77, 0x79,
+	0x3B, 0x63, 0x99, 0x94, 0x10, 0x18, 0x92, 0x0F, 0x1D, 0x09, 0x27, 0xD4, 0x9E, 0xB5, 0xF9, 0x3D,
+	0x5D, 0x27, 0xED, 0x75, 0xFF, 0x00, 0x05, 0xAB, 0xF0, 0xFF, 0x00, 0xFC, 0x13, 0x7F, 0xF6, 0x01,
+	0xD0, 0x3E, 0x0D, 0x7C, 0x13, 0xBF, 0xB4, 0xBF, 0xF8, 0xD1, 0xE2, 0x88, 0x35, 0x06, 0xD3, 0x63,
+	0x92, 0x21, 0x34, 0x7E, 0x1D, 0xB2, 0x6B, 0x9B, 0x80, 0x35, 0x09, 0x54, 0xF0, 0xEF, 0x95, 0x22,
+	0x28, 0x0F, 0xDE, 0x7F, 0xDE, 0x37, 0xEE, 0xF6, 0xAC, 0xAA, 0xF6, 0x5A, 0x95, 0x18, 0xCA, 0x6E,
+	0xC8, 0xE9, 0xBF, 0xE0, 0xBB, 0x3F, 0xF0, 0x5E, 0x0F, 0x1A, 0xFE, 0xC2, 0x9E, 0x36, 0xD4, 0xBF,
+	0x65, 0xBF, 0xD9, 0xA3, 0x53, 0xF0, 0xE5, 0xEF, 0x8C, 0x6F, 0x34, 0x18, 0xC5, 0xE6, 0xAF, 0xF6,
+	0x69, 0x2E, 0x27, 0xF0, 0xC4, 0xB3, 0x13, 0xB9, 0xDC, 0x89, 0x56, 0x33, 0x70, 0x22, 0x31, 0xC8,
+	0x90, 0x95, 0x2C, 0x03, 0x6E, 0x6F, 0x94, 0x00, 0xFF, 0x00, 0xCF, 0x3F, 0x89, 0x7C, 0x49, 0xE2,
+	0x1F, 0x1A, 0x6B, 0xF7, 0x9E, 0x2B, 0xF1, 0x8E, 0xB1, 0x77, 0xA8, 0x6A, 0x9A, 0xA5, 0xDC, 0x97,
+	0x7A, 0x96, 0xA1, 0x7F, 0x70, 0x66, 0x9E, 0xE6, 0xE2, 0x46, 0x2F, 0x24, 0xB2, 0x48, 0x79, 0x77,
+	0x66, 0x25, 0x8B, 0x1E, 0x49, 0x24, 0xF7, 0xA3, 0xC4, 0xDE, 0x24, 0xD7, 0xFC, 0x69, 0xE2, 0x0B,
+	0xCF, 0x15, 0xF8, 0xBB, 0x5B, 0xBB, 0xD4, 0xB5, 0x2D, 0x52, 0xF2, 0x4B, 0xBD, 0x47, 0x52, 0xD4,
+	0x2E, 0x0C, 0xB3, 0xDD, 0xCF, 0x23, 0x17, 0x92, 0x59, 0x1C, 0xFD, 0xF7, 0x66, 0x25, 0x99, 0x8F,
+	0x52, 0x49, 0xAA, 0x24, 0x00, 0x70, 0x2B, 0x9A, 0x52, 0xE6, 0x3D, 0x2A, 0x74, 0xE3, 0x4E, 0x3A,
+	0x01, 0x00, 0x1C, 0x0A, 0x28, 0xA2, 0xA4, 0xD0, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00,
+	0x28, 0xA2, 0x8A, 0x00, 0x2B, 0xF7, 0x83, 0xFE, 0x0C, 0xDA, 0xFF, 0x00, 0x92, 0x69, 0xF1, 0xEB,
+	0xFE, 0xC6, 0x0D, 0x03, 0xFF, 0x00, 0x49, 0xEF, 0xEB, 0xF0, 0x7E, 0xBF, 0x78, 0x3F, 0xE0, 0xCD,
+	0xAF, 0xF9, 0x26, 0x9F, 0x1E, 0xBF, 0xEC, 0x60, 0xD0, 0x3F, 0xF4, 0x9E, 0xFE, 0xB4, 0xA7, 0xF1,
+	0x1C, 0xF8, 0x9F, 0xE1, 0x9F, 0xB5, 0x87, 0xAD, 0x47, 0x23, 0x2F, 0x2A, 0xC8, 0xC7, 0x03, 0x2C,
+	0xA9, 0xDD, 0x4E, 0x7F, 0xC2, 0xA4, 0x3D, 0x69, 0xB2, 0x67, 0x2B, 0xFE, 0xF0, 0xFE, 0x75, 0xD0,
+	0x79, 0xE7, 0xC5, 0x1F, 0xB2, 0x57, 0xFC, 0x16, 0xEF, 0xF6, 0x68, 0xFD, 0xB0, 0x3F, 0x6D, 0xDF,
+	0x15, 0x7E, 0xC2, 0xBE, 0x18, 0xF0, 0x67, 0x89, 0x34, 0x1F, 0x15, 0xF8, 0x5E, 0xE3, 0x56, 0xB7,
+	0x5B, 0xCD, 0x69, 0x6D, 0xFE, 0xC9, 0xAA, 0xCD, 0x61, 0x38, 0x86, 0x74, 0x83, 0xCB, 0x95, 0x9F,
+	0x71, 0x50, 0xF2, 0x2E, 0xE5, 0x07, 0xCB, 0x8D, 0xF2, 0x01, 0xE2, 0xBD, 0xA3, 0xE2, 0x37, 0xED,
+	0xD3, 0xF0, 0x43, 0xE1, 0xCF, 0xED, 0x9D, 0xE0, 0x3F, 0xD8, 0x47, 0xC4, 0x77, 0x5A, 0xA0, 0xF1,
+	0xC7, 0xC4, 0x6F, 0x0F, 0x5F, 0xEA, 0xDA, 0x0C, 0x71, 0xE9, 0xC6, 0x4B, 0x5F, 0x22, 0xD5, 0x24,
+	0x91, 0xD6, 0x47, 0x3F, 0x75, 0xA4, 0x8E, 0x0B, 0xA6, 0x19, 0xFF, 0x00, 0x9F, 0x6C, 0x1F, 0x99,
+	0xD0, 0x3F, 0xF3, 0xC9, 0x63, 0xE1, 0x8F, 0x8A, 0x5F, 0x02, 0xBF, 0x69, 0x1F, 0x8D, 0x3F, 0xF0,
+	0x55, 0x3F, 0x83, 0xCB, 0x79, 0x73, 0xA8, 0x7C, 0x04, 0xFD, 0xA9, 0xB6, 0xEB, 0xDA, 0x75, 0xBC,
+	0x9B, 0x52, 0xE3, 0x49, 0xBF, 0xD4, 0x6F, 0xD2, 0x51, 0x21, 0xFE, 0x05, 0x76, 0x41, 0x6A, 0xDF,
+	0xDE, 0x8E, 0xFD, 0x6B, 0xF4, 0xCB, 0xE3, 0x4F, 0xC4, 0xDF, 0x08, 0x7C, 0x66, 0xFF, 0x00, 0x83,
+	0x8D, 0x3F, 0x62, 0xAF, 0x8B, 0xFF, 0x00, 0x0F, 0xF5, 0x58, 0xEF, 0xB4, 0x1F, 0x13, 0xFC, 0x0F,
+	0xD5, 0xB5, 0x4D, 0x1E, 0xED, 0x06, 0x3C, 0xCB, 0x6B, 0x8D, 0x27, 0x5B, 0x9A, 0x27, 0xC7, 0x6C,
+	0xA3, 0xA9, 0xAC, 0xE3, 0x27, 0xCB, 0xA9, 0xBD, 0x4A, 0x76, 0xB3, 0x47, 0xE9, 0x97, 0xC5, 0x9F,
+	0x89, 0x9E, 0x0A, 0xF8, 0x2D, 0xF0, 0xD7, 0x5D, 0xF8, 0xBB, 0xF1, 0x1B, 0xC4, 0x50, 0xE9, 0x9A,
+	0x0F, 0x86, 0xF4, 0x99, 0xF5, 0x2D, 0x5E, 0xFA, 0xE9, 0xBE, 0x5B, 0x6B, 0x58, 0xA2, 0x2E, 0xEE,
+	0x47, 0xF1, 0x90, 0xAA, 0xC4, 0x0F, 0x53, 0x5F, 0x1E, 0x7E, 0xC0, 0x1F, 0xF0, 0x5E, 0xDF, 0xD8,
+	0xB7, 0xFE, 0x0A, 0x23, 0xF1, 0xBE, 0xFB, 0xF6, 0x79, 0xF8, 0x5D, 0x61, 0xE2, 0xAF, 0x0E, 0xF8,
+	0x89, 0x6D, 0xE6, 0xBB, 0xD0, 0xAD, 0xFC, 0x59, 0xA7, 0xC5, 0x07, 0xF6, 0xE4, 0x50, 0x8D, 0xD2,
+	0x7D, 0x97, 0x64, 0x8D, 0xF3, 0xAC, 0x6A, 0x65, 0xF2, 0xD9, 0x43, 0x14, 0x47, 0x62, 0x06, 0xC7,
+	0x03, 0xC9, 0xBF, 0xE0, 0xE4, 0x5F, 0x8A, 0x9F, 0x12, 0xBC, 0x7F, 0xA7, 0x7C, 0x15, 0xFF, 0x00,
+	0x82, 0x61, 0x7C, 0x26, 0xD4, 0x24, 0xD3, 0xEF, 0xBF, 0x68, 0x4F, 0x1D, 0x43, 0x67, 0xAD, 0xEB,
+	0x3E, 0x63, 0x28, 0xB6, 0xB1, 0xB6, 0xB8, 0xB3, 0x40, 0x1B, 0xD6, 0x33, 0x35, 0xC2, 0x4B, 0x27,
+	0xFB, 0x16, 0xC4, 0x7F, 0x1D, 0x71, 0x9F, 0xF0, 0x5D, 0x4F, 0xD8, 0xCB, 0xC3, 0xDF, 0xB0, 0xFF,
+	0x00, 0xEC, 0xD3, 0xF0, 0x43, 0xF6, 0xE6, 0xFD, 0x8E, 0xB4, 0xB8, 0x74, 0x3F, 0x11, 0x7E, 0xCB,
+	0xBA, 0x86, 0x95, 0xA5, 0x5A, 0xB4, 0x11, 0xC7, 0x19, 0xBF, 0xD1, 0x9A, 0x55, 0x8A, 0x28, 0xAE,
+	0x49, 0xFF, 0x00, 0x5A, 0xC2, 0xE5, 0x93, 0x20, 0xFD, 0xF5, 0xBF, 0xBA, 0x6E, 0xF4, 0xE5, 0x2E,
+	0xA8, 0x51, 0x8C, 0x6D, 0x67, 0xBB, 0x3F, 0x5D, 0x63, 0x05, 0x63, 0x55, 0x23, 0xA2, 0xF6, 0xA2,
+	0x4E, 0x9C, 0x7A, 0x1F, 0xE9, 0x5C, 0xE7, 0xC1, 0x9F, 0x88, 0xF6, 0x1F, 0x18, 0xFE, 0x0F, 0xF8,
+	0x53, 0xE2, 0xEE, 0x95, 0x63, 0x25, 0xAD, 0xAF, 0x8A, 0xBC, 0x37, 0x63, 0xAC, 0x5B, 0xDA, 0xC8,
+	0xC1, 0x9A, 0x18, 0xEE, 0x6D, 0xD2, 0x65, 0x42, 0x47, 0x04, 0x80, 0xE0, 0x7E, 0x15, 0xD2, 0x3F,
+	0x4F, 0xC0, 0xFF, 0x00, 0x31, 0x57, 0xAF, 0x2D, 0xCC, 0xED, 0x69, 0x59, 0x1F, 0xCF, 0x27, 0xFC,
+	0x19, 0xF7, 0xFF, 0x00, 0x27, 0xC3, 0xF1, 0x3B, 0xFE, 0xC9, 0x4B, 0x7F, 0xE9, 0xC6, 0xCA, 0xBF,
+	0xA1, 0xC2, 0x72, 0x73, 0x5F, 0xCF, 0x1F, 0xFC, 0x19, 0xF7, 0xFF, 0x00, 0x27, 0xC3, 0xF1, 0x3B,
+	0xFE, 0xC9, 0x4B, 0x7F, 0xE9, 0xC6, 0xCA, 0xBF, 0xA1, 0xC3, 0xD6, 0xB3, 0xA7, 0xF0, 0x9A, 0xD7,
+	0xBF, 0xB4, 0x0A, 0xA9, 0x73, 0x24, 0x56, 0xA2, 0x4B, 0xBB, 0x89, 0x82, 0x47, 0x19, 0xF3, 0x1D,
+	0xE4, 0x93, 0x6A, 0xA2, 0x8E, 0xBC, 0xFA, 0x7C, 0xA5, 0x8D, 0x5B, 0xAC, 0xCF, 0x12, 0x68, 0xDA,
+	0x5F, 0x89, 0x74, 0x5B, 0xEF, 0x0F, 0x6B, 0x56, 0x11, 0xDC, 0xD9, 0xDF, 0x5A, 0xCB, 0x05, 0xED,
+	0xAB, 0x7F, 0xCB, 0x78, 0xDD, 0x0A, 0x3A, 0x1F, 0xAA, 0x30, 0x1F, 0x88, 0xAD, 0x0C, 0x2E, 0x7C,
+	0x43, 0xE2, 0xFF, 0x00, 0xF8, 0x39, 0x17, 0xFE, 0x09, 0x07, 0xE0, 0xCF, 0x11, 0x5C, 0xF8, 0x72,
+	0x7F, 0xDA, 0x7E, 0xE7, 0x52, 0x92, 0xD6, 0x67, 0x8E, 0x6B, 0xAD, 0x17, 0xC1, 0xBA, 0xB4, 0xF6,
+	0xE5, 0x95, 0x88, 0x3B, 0x64, 0x16, 0xE5, 0x24, 0x5C, 0x8E, 0x19, 0x49, 0x52, 0x39, 0x04, 0x82,
+	0x0D, 0x7D, 0x01, 0xFB, 0x1C, 0x7F, 0xC1, 0x40, 0x7F, 0x64, 0xDF, 0xF8, 0x28, 0x0F, 0x84, 0xB5,
+	0x1F, 0x19, 0xFE, 0xCA, 0x3F, 0x18, 0x6D, 0x7C, 0x4B, 0x6B, 0xA4, 0xC9, 0x0C, 0x5A, 0xC4, 0x31,
+	0xD8, 0xCF, 0x6D, 0x71, 0xA6, 0xBC, 0xA2, 0x4F, 0x2C, 0x4B, 0x14, 0xF1, 0xC6, 0xF1, 0x92, 0x23,
+	0x7C, 0x31, 0x05, 0x58, 0x27, 0x04, 0x8A, 0xFC, 0xA9, 0xFD, 0x91, 0xFE, 0x14, 0xFC, 0x1F, 0xFF,
+	0x00, 0x82, 0x3D, 0x7F, 0xC1, 0x41, 0xEE, 0xBF, 0xE0, 0x9C, 0xFF, 0x00, 0xB7, 0x87, 0xC0, 0x9F,
+	0x04, 0xF8, 0x9B, 0xE1, 0x5F, 0xC4, 0xDD, 0x58, 0xDF, 0xFC, 0x16, 0xF8, 0xAD, 0xE2, 0x6F, 0x06,
+	0xD9, 0x5D, 0x49, 0x15, 0xC3, 0xBA, 0xC4, 0x96, 0x93, 0xDC, 0xCB, 0x09, 0x93, 0x38, 0x30, 0xC2,
+	0xEB, 0x93, 0xE4, 0xC8, 0xA9, 0x2E, 0x52, 0x29, 0x9A, 0x43, 0xFA, 0x87, 0xFB, 0x3C, 0x7F, 0xC1,
+	0x39, 0xFF, 0x00, 0x64, 0xAF, 0xD9, 0x3F, 0xE3, 0xAF, 0x8E, 0x3F, 0x68, 0x3F, 0xD9, 0xE3, 0xE1,
+	0xBA, 0xF8, 0x5F, 0x5A, 0xF8, 0x85, 0x0D, 0x9C, 0x1A, 0xDE, 0x9B, 0xA3, 0xCA, 0x62, 0xD3, 0x13,
+	0xC9, 0x2C, 0xFF, 0x00, 0xE8, 0xF6, 0x88, 0x04, 0x70, 0x6F, 0x24, 0x3B, 0x32, 0x8D, 0xA4, 0xA8,
+	0xC0, 0x03, 0x70, 0x79, 0x8F, 0x31, 0xAC, 0x95, 0x35, 0x13, 0x97, 0xFD, 0xB2, 0x3F, 0xE0, 0xB2,
+	0x1F, 0xB0, 0x27, 0xEC, 0x13, 0xF1, 0x4E, 0xDB, 0xE0, 0xB7, 0xED, 0x2D, 0xF1, 0x62, 0xFB, 0x45,
+	0xF1, 0x35, 0xC6, 0x91, 0x16, 0xA6, 0x9A, 0x6D, 0x8F, 0x86, 0x6F, 0x6F, 0x7C, 0xBB, 0x69, 0x1A,
+	0x45, 0x46, 0x2D, 0x04, 0x45, 0x57, 0x26, 0x27, 0xEB, 0x5C, 0x1F, 0xC3, 0x1F, 0xF8, 0x38, 0x9B,
+	0xFE, 0x09, 0x47, 0xF1, 0x97, 0xE2, 0x46, 0x87, 0xF0, 0xB3, 0xC1, 0x5F, 0xB4, 0x06, 0xA5, 0xFD,
+	0xB5, 0xE2, 0x4D, 0x52, 0x0D, 0x37, 0x48, 0x8E, 0xF3, 0xC1, 0xFA, 0x8C, 0x31, 0xB5, 0xD4, 0xCE,
+	0x16, 0x25, 0x79, 0x1A, 0x2D, 0x8B, 0xB9, 0x99, 0x71, 0xBB, 0xD7, 0x9A, 0xF7, 0xCF, 0xDB, 0x57,
+	0xE0, 0x2F, 0xC0, 0xFF, 0x00, 0x8B, 0x1F, 0x01, 0xFC, 0x65, 0xE2, 0x7F, 0x89, 0xDF, 0x07, 0xBC,
+	0x2D, 0xE2, 0x2D, 0x47, 0x4C, 0xF0, 0x5E, 0xAB, 0xFD, 0x97, 0xA9, 0x6B, 0x9E, 0x1E, 0xB7, 0xBC,
+	0x9A, 0xD3, 0xFD, 0x12, 0x43, 0xBA, 0x16, 0x95, 0x0B, 0x47, 0x83, 0xD0, 0xA9, 0xCD, 0x7C, 0x3F,
+	0xFF, 0x00, 0x06, 0xBD, 0xFC, 0x05, 0xF8, 0x1F, 0xE2, 0x1F, 0xF8, 0x26, 0xFF, 0x00, 0x87, 0xFE,
+	0x2F, 0x6B, 0xDF, 0x06, 0x7C, 0x2B, 0x75, 0xE2, 0xCB, 0x5F, 0x1B, 0xEA, 0xFF, 0x00, 0x65, 0xF1,
+	0x25, 0xCF, 0x87, 0x6D, 0xDB, 0x50, 0x87, 0x6B, 0xAA, 0xA8, 0x4B, 0x86, 0x8F, 0xCD, 0x00, 0x0E,
+	0xC3, 0x8A, 0x8B, 0xCB, 0x9A, 0xC0, 0xA3, 0x0F, 0x66, 0xDE, 0xBF, 0x79, 0xFA, 0x95, 0x1E, 0xE1,
+	0x12, 0xEF, 0x1C, 0xED, 0xE7, 0x15, 0xF2, 0x4F, 0xED, 0x5D, 0xFF, 0x00, 0x05, 0xB8, 0xFF, 0x00,
+	0x82, 0x6C, 0x7E, 0xC6, 0x5F, 0x16, 0x6E, 0xBE, 0x07, 0xFC, 0x74, 0xFD, 0xA0, 0x0D, 0xBF, 0x8B,
+	0x2C, 0x42, 0xB6, 0xA1, 0xA3, 0xE8, 0xFA, 0x0D, 0xEE, 0xA0, 0x6C, 0xF7, 0x8C, 0xA2, 0x4D, 0x24,
+	0x11, 0x34, 0x68, 0xCC, 0x39, 0xD8, 0x58, 0x30, 0x3C, 0x1A, 0x93, 0xFE, 0x0B, 0x2F, 0xFB, 0x7B,
+	0x6B, 0xBF, 0xF0, 0x4E, 0x9F, 0xD8, 0x4B, 0xC4, 0x3F, 0x1E, 0xBC, 0x0B, 0xA5, 0x2D, 0xD7, 0x8A,
+	0x2F, 0x2E, 0xED, 0xF4, 0x2F, 0x0B, 0x4B, 0x75, 0x6F, 0xE6, 0xC3, 0x6F, 0x7D, 0x72, 0x1C, 0xA5,
+	0xCC, 0xB1, 0xFF, 0x00, 0x1A, 0x44, 0xA9, 0x2C, 0x9B, 0x7F, 0x8D, 0xD0, 0x27, 0xF1, 0xD7, 0x93,
+	0xFF, 0x00, 0xC1, 0x25, 0xFF, 0x00, 0xE0, 0x8C, 0xFF, 0x00, 0x0B, 0x3E, 0x00, 0x7C, 0x00, 0x9F,
+	0xE2, 0x47, 0xED, 0x9B, 0xF0, 0xEB, 0xC3, 0xFF, 0x00, 0x12, 0x7E, 0x2F, 0x7C, 0x4D, 0x91, 0x75,
+	0xDF, 0x1D, 0x6A, 0xDE, 0x34, 0xD2, 0xE1, 0xD5, 0x5E, 0xCA, 0x69, 0xBF, 0x7B, 0xF6, 0x35, 0x7B,
+	0x95, 0x7C, 0x95, 0x67, 0x2D, 0x34, 0xA0, 0x62, 0x59, 0x73, 0x9C, 0xAA, 0x46, 0x05, 0x4A, 0x4F,
+	0x61, 0x46, 0x31, 0xB5, 0xD9, 0xF6, 0x07, 0xEC, 0xC5, 0xFB, 0x4E, 0x7C, 0x1F, 0xFD, 0xAF, 0xBE,
+	0x09, 0x68, 0x7F, 0xB4, 0x17, 0xC0, 0x1F, 0x16, 0x36, 0xB5, 0xE1, 0x5D, 0x7A, 0x37, 0x6D, 0x37,
+	0x50, 0xFB, 0x24, 0x90, 0xC8, 0xCD, 0x1C, 0xAD, 0x14, 0x8A, 0xD1, 0xCC, 0x9B, 0xD1, 0x95, 0xA2,
+	0x75, 0x3B, 0xBA, 0x95, 0xE3, 0xB5, 0x79, 0xBF, 0xEC, 0x51, 0xFF, 0x00, 0x05, 0x51, 0xFD, 0x8B,
+	0x7F, 0xE0, 0xA1, 0xFA, 0xA7, 0x88, 0xB4, 0x2F, 0xD9, 0x5B, 0xE2, 0xA4, 0xDA, 0xF5, 0xE7, 0x85,
+	0x6D, 0x60, 0xB8, 0xD6, 0x6D, 0xAE, 0xB4, 0x4B, 0xAB, 0x37, 0x54, 0x95, 0xA4, 0x11, 0x34, 0x6B,
+	0x71, 0x1A, 0xF9, 0xBF, 0x32, 0x1C, 0xED, 0x24, 0x03, 0xB0, 0x7F, 0x1D, 0x7D, 0x01, 0xE1, 0x8F,
+	0x0E, 0xF8, 0x6F, 0xC1, 0xBE, 0x1D, 0xB4, 0xF0, 0xBF, 0x84, 0x34, 0x1B, 0x3D, 0x33, 0x4B, 0xB0,
+	0xB6, 0x58, 0x2C, 0x74, 0xCB, 0x0B, 0x75, 0x86, 0x2B, 0x78, 0x95, 0x55, 0x51, 0x12, 0x35, 0x00,
+	0x22, 0xAA, 0x80, 0x02, 0x80, 0x00, 0x00, 0x00, 0x06, 0x2B, 0xF9, 0x78, 0xFF, 0x00, 0x82, 0x33,
+	0xFC, 0x4C, 0xF1, 0xAF, 0xFC, 0x13, 0xEF, 0xE2, 0xE7, 0xC2, 0xDF, 0xF8, 0x28, 0x7E, 0xB3, 0xA9,
+	0xC9, 0x17, 0xC3, 0x6F, 0x16, 0x7C, 0x4A, 0xD5, 0x7E, 0x18, 0xFC, 0x40, 0xB8, 0x41, 0xB6, 0x2B,
+	0x1B, 0x76, 0xB3, 0xD3, 0xEE, 0x56, 0x59, 0x4F, 0xB3, 0x5D, 0xAD, 0xC8, 0xF6, 0xD3, 0x64, 0xA1,
+	0xBE, 0x5D, 0x02, 0x30, 0xE6, 0x8B, 0x3F, 0xA4, 0xF8, 0xFF, 0x00, 0x69, 0xDF, 0x81, 0x57, 0xDF,
+	0xB4, 0x85, 0xD7, 0xEC, 0x97, 0x6B, 0xF1, 0x4B, 0x4D, 0x7F, 0x88, 0x16, 0xBE, 0x18, 0x8F, 0x5F,
+	0x9B, 0xC2, 0xE9, 0xBF, 0xCF, 0x36, 0x0F, 0x27, 0x96, 0x24, 0x2D, 0xF7, 0x49, 0xE0, 0x66, 0x3C,
+	0xF9, 0x9B, 0x18, 0x49, 0xF7, 0x48, 0xAF, 0x42, 0x72, 0x90, 0xAB, 0x3B, 0x48, 0x02, 0xB7, 0x0C,
+	0xDB, 0x82, 0x6C, 0xE3, 0x27, 0x3E, 0xFC, 0xB3, 0x1F, 0x6A, 0xFC, 0xCE, 0xF0, 0x76, 0x7F, 0xE2,
+	0x2A, 0xDF, 0x13, 0xE4, 0x63, 0xFE, 0x31, 0xCE, 0x1F, 0xFD, 0x19, 0x6D, 0x5F, 0x4C, 0xFF, 0x00,
+	0xC1, 0x66, 0x3F, 0x69, 0x9F, 0xF8, 0x64, 0xEF, 0xF8, 0x26, 0x7F, 0xC5, 0xBF, 0x8B, 0x56, 0xB7,
+	0xEB, 0x6B, 0xA9, 0x3F, 0x85, 0x64, 0xD2, 0x34, 0x39, 0xBC, 0xCF, 0x9E, 0x3B, 0xCB, 0xE6, 0x16,
+	0x51, 0xCA, 0x83, 0xB9, 0x8B, 0xCE, 0x33, 0x63, 0xFE, 0x99, 0xD3, 0xE6, 0xF7, 0x6E, 0x4F, 0x2B,
+	0xE6, 0xB2, 0x3D, 0x33, 0xF6, 0x63, 0xFD, 0xAD, 0x7F, 0x67, 0xAF, 0xDB, 0x2F, 0xC0, 0x97, 0xDF,
+	0x12, 0x3F, 0x66, 0xDF, 0x8A, 0x3A, 0x77, 0x8B, 0x34, 0x4D, 0x3B, 0x5E, 0xBC, 0xD1, 0xAF, 0x6F,
+	0xF4, 0xF8, 0xDC, 0x2C, 0x57, 0x90, 0x30, 0xDC, 0x9B, 0x5B, 0xE6, 0xC1, 0x56, 0x49, 0x14, 0x8F,
+	0x96, 0x48, 0xA5, 0x47, 0x5F, 0x94, 0x8A, 0xD0, 0xFD, 0xA4, 0xFF, 0x00, 0x68, 0xBF, 0x83, 0x5F,
+	0xB2, 0x8F, 0xC2, 0x1D, 0x6B, 0xE3, 0xD7, 0xC7, 0xBF, 0x1E, 0x5B, 0xF8, 0x77, 0xC2, 0xFA, 0x22,
+	0xC6, 0x6F, 0xB5, 0x6B, 0xA8, 0x24, 0x95, 0x50, 0xCB, 0x28, 0x8D, 0x14, 0x2C, 0x7F, 0x33, 0xE5,
+	0x99, 0x7E, 0x45, 0xE7, 0xB9, 0xE2, 0xBF, 0x20, 0xBF, 0xE0, 0xD6, 0xED, 0x73, 0xE2, 0x57, 0xEC,
+	0xBB, 0xFB, 0x4A, 0xFC, 0x4A, 0xFD, 0x83, 0x7E, 0x35, 0x58, 0xB6, 0x99, 0x7D, 0xE2, 0xAF, 0x87,
+	0xFA, 0x07, 0xC4, 0x0F, 0x0F, 0x5A, 0x48, 0xE0, 0x00, 0x92, 0xDB, 0x41, 0x33, 0x8E, 0x79, 0x69,
+	0x8C, 0x1A, 0x8D, 0xA8, 0x92, 0x31, 0xF7, 0x0D, 0xB4, 0x83, 0xB5, 0x7D, 0x8B, 0xFF, 0x00, 0x07,
+	0x37, 0x1C, 0xFF, 0x00, 0xC1, 0x1F, 0x3C, 0x78, 0x7F, 0xEA, 0x39, 0xE1, 0xFE, 0xDF, 0xF5, 0x15,
+	0xB6, 0xA1, 0x48, 0xA7, 0x0E, 0x59, 0x24, 0x7D, 0xE9, 0xA0, 0xEB, 0x7A, 0x4F, 0x89, 0xB4, 0x3B,
+	0x3F, 0x11, 0xE8, 0x37, 0xD1, 0xDD, 0x58, 0xEA, 0x16, 0xB1, 0xDC, 0xD9, 0x5D, 0x44, 0xD9, 0x59,
+	0xA1, 0x75, 0x0C, 0x8E, 0x0F, 0xA1, 0x52, 0x0F, 0xE3, 0x56, 0xAB, 0x85, 0xFD, 0x97, 0xFF, 0x00,
+	0xE4, 0xDA, 0x7E, 0x1D, 0xFF, 0x00, 0xD8, 0x8B, 0xA4, 0xFF, 0x00, 0xE9, 0x1C, 0x55, 0xDD, 0x55,
+	0x23, 0x37, 0x60, 0xA2, 0x8A, 0x28, 0x03, 0xF2, 0x2B, 0xFE, 0x0F, 0x0A, 0xFF, 0x00, 0x93, 0x27,
+	0xF8, 0x63, 0xFF, 0x00, 0x65, 0x50, 0x7F, 0xE9, 0xB2, 0xEE, 0xBF, 0x9E, 0x8A, 0xFE, 0x85, 0xFF,
+	0x00, 0xE0, 0xF0, 0xAF, 0xF9, 0x32, 0x7F, 0x86, 0x3F, 0xF6, 0x55, 0x07, 0xFE, 0x9B, 0x2E, 0xEB,
+	0xF9, 0xE8, 0xAE, 0x7A, 0x9F, 0x19, 0xEA, 0x61, 0xBF, 0x82, 0x82, 0x8A, 0x28, 0xAC, 0xCD, 0x02,
+	0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x03, 0x2C, 0x5B, 0xCB, 0x3B,
+	0xB6, 0xED, 0x1B, 0x19, 0x79, 0x61, 0xB9, 0xBE, 0xF6, 0x3F, 0x80, 0xAB, 0x0E, 0x1A, 0xBF, 0x6F,
+	0xFF, 0x00, 0xE0, 0x81, 0x7F, 0xF0, 0x5F, 0x4F, 0x17, 0xF8, 0x8B, 0xC4, 0xDE, 0x17, 0xFD, 0x86,
+	0x7F, 0x6D, 0x3F, 0x1B, 0xD9, 0xBC, 0x6F, 0x07, 0xD8, 0x3C, 0x0B, 0xE3, 0x6D, 0x5D, 0x58, 0x5C,
+	0xDD, 0x4F, 0x98, 0x85, 0xB5, 0x85, 0xE5, 0xC2, 0xBA, 0xA8, 0x3C, 0x18, 0x52, 0x53, 0x19, 0xF3,
+	0x19, 0xE2, 0x4D, 0xC7, 0xF8, 0xFF, 0x00, 0x10, 0x29, 0xCA, 0x42, 0xE2, 0x44, 0x24, 0x15, 0x2D,
+	0xB4, 0x46, 0xCE, 0xAE, 0x0E, 0x06, 0x17, 0x31, 0xF2, 0x87, 0x70, 0xDE, 0x1A, 0xAA, 0x32, 0xE5,
+	0x64, 0x4E, 0x9C, 0x6A, 0x46, 0xCC, 0xFE, 0xCE, 0x3F, 0x6B, 0x7F, 0x8C, 0x5E, 0x28, 0xF8, 0x09,
+	0xF0, 0x27, 0x50, 0xF8, 0x95, 0xE1, 0x1B, 0x2B, 0x39, 0xAF, 0xED, 0x2E, 0x6D, 0xE3, 0x8A, 0x1D,
+	0x46, 0x32, 0xF1, 0xE2, 0x49, 0x55, 0x0E, 0xED, 0x8C, 0xBF, 0xDE, 0xF5, 0xAF, 0x90, 0xD7, 0xFE,
+	0x0A, 0xCF, 0xFB, 0x43, 0xED, 0x1F, 0xF1, 0x45, 0xF8, 0x27, 0xFE, 0x03, 0x63, 0x79, 0x8F, 0xFD,
+	0x29, 0xAF, 0x86, 0x3F, 0xE0, 0x9E, 0x7F, 0xF0, 0x5B, 0xDD, 0x53, 0xF6, 0x95, 0xFD, 0x90, 0x2F,
+	0xFF, 0x00, 0x60, 0xFF, 0x00, 0xDA, 0xBF, 0xC4, 0x37, 0x17, 0xFE, 0x3E, 0xD2, 0xD6, 0xD1, 0xFC,
+	0x13, 0xE3, 0x1B, 0xAB, 0x88, 0xCC, 0xBE, 0x20, 0xB5, 0x8A, 0xE2, 0x33, 0xF6, 0x69, 0x4C, 0x9D,
+	0x6E, 0xE2, 0x4D, 0xDB, 0x26, 0x6C, 0x2C, 0xD1, 0xC5, 0x29, 0x7D, 0xAF, 0x19, 0x69, 0xBD, 0x14,
+	0x74, 0xFE, 0x1F, 0xFB, 0x67, 0x9D, 0xBF, 0x86, 0x7B, 0x57, 0x44, 0x64, 0xA4, 0xB4, 0x3C, 0xD9,
+	0xD3, 0x95, 0x39, 0x59, 0x9F, 0x51, 0x7F, 0xC3, 0xD9, 0xFF, 0x00, 0x68, 0x8F, 0xFA, 0x13, 0x3C,
+	0x17, 0xFF, 0x00, 0x80, 0x37, 0xBF, 0xFC, 0x93, 0x47, 0xFC, 0x3D, 0x9F, 0xF6, 0x88, 0xFF, 0x00,
+	0xA1, 0x33, 0xC1, 0x7F, 0xF8, 0x03, 0x7B, 0xFF, 0x00, 0xC9, 0x35, 0xF2, 0xED, 0x15, 0x44, 0x1F,
+	0x51, 0x7F, 0xC3, 0xD9, 0xFF, 0x00, 0x68, 0x8F, 0xFA, 0x13, 0x3C, 0x17, 0xFF, 0x00, 0x80, 0x37,
+	0xBF, 0xFC, 0x93, 0x5F, 0x45, 0x7E, 0xC2, 0x9F, 0xB5, 0x3F, 0xC4, 0x4F, 0xDA, 0x83, 0x4C, 0xF1,
+	0x15, 0xF7, 0x8E, 0xF4, 0x9D, 0x1E, 0xCD, 0xB4, 0x7B, 0xAB, 0x68, 0xED, 0xD7, 0x46, 0xB7, 0x95,
+	0x15, 0xB7, 0xAB, 0xB1, 0xDD, 0xE6, 0x4A, 0xE7, 0x3F, 0x25, 0x7E, 0x69, 0xD7, 0xDC, 0x7F, 0xF0,
+	0x48, 0x3F, 0xF9, 0x16, 0xFC, 0x75, 0xFF, 0x00, 0x5F, 0xF6, 0x3F, 0xFA, 0x2A, 0xE2, 0x80, 0x3A,
+	0x3F, 0xF8, 0x29, 0x2F, 0xED, 0xAB, 0xF1, 0x5B, 0xF6, 0x3F, 0x6F, 0x06, 0x9F, 0x86, 0xDA, 0x07,
+	0x87, 0xEF, 0xD7, 0xC4, 0x2B, 0xA8, 0x35, 0xE2, 0xEB, 0x36, 0xB3, 0x4A, 0x50, 0x5B, 0x9B, 0x6C,
+	0x18, 0xFC, 0xB9, 0xA3, 0x3D, 0x27, 0x6C, 0xFD, 0x3B, 0x57, 0xCC, 0xA3, 0xFE, 0x0B, 0x59, 0xFB,
+	0x54, 0xC7, 0xF2, 0x3F, 0x81, 0xFE, 0x1E, 0xEE, 0x5E, 0x0E, 0xDD, 0x2A, 0xF7, 0x19, 0xFF, 0x00,
+	0xC0, 0xCA, 0xEF, 0xBF, 0xE0, 0xBA, 0xFF, 0x00, 0xEB, 0x3E, 0x16, 0xFF, 0x00, 0xBB, 0xAD, 0xFF,
+	0x00, 0x3D, 0x3E, 0xBF, 0x3F, 0x6B, 0xDA, 0xC1, 0xE1, 0xA8, 0xD5, 0xC3, 0xF3, 0x49, 0x6A, 0x78,
+	0xB8, 0xAC, 0x45, 0x6A, 0x78, 0x87, 0x18, 0xC9, 0xD8, 0xFB, 0x13, 0xFE, 0x1F, 0x63, 0xFB, 0x54,
+	0x7F, 0xD0, 0x8D, 0xF0, 0xF7, 0xFF, 0x00, 0x05, 0x77, 0xBF, 0xFC, 0x99, 0x47, 0xFC, 0x3E, 0xC7,
+	0xF6, 0xA8, 0xFF, 0x00, 0xA1, 0x17, 0xE1, 0xEF, 0xFE, 0x0A, 0xEF, 0x7F, 0xF9, 0x32, 0xBE, 0x3B,
+	0xA2, 0xBA, 0x3E, 0xA7, 0x86, 0xFE, 0x53, 0x9B, 0xEB, 0x98, 0x8F, 0xE6, 0x67, 0xD8, 0x9F, 0xF0,
+	0xFB, 0x0F, 0xDA, 0xA0, 0xFF, 0x00, 0xCC, 0x8F, 0xF0, 0xFF, 0x00, 0xFF, 0x00, 0x05, 0x77, 0xBF,
+	0xFC, 0x99, 0x5F, 0x68, 0xFE, 0xC1, 0x9F, 0xB4, 0x67, 0x8F, 0x3F, 0x6A, 0x4F, 0x81, 0xA3, 0xE2,
+	0xB7, 0xC4, 0x3D, 0x3B, 0x49, 0xB6, 0xBC, 0xFE, 0xD6, 0xB9, 0xB5, 0x36, 0xFA, 0x3C, 0x32, 0xA4,
+	0x01, 0x62, 0x28, 0x55, 0xBF, 0x79, 0x2B, 0x9C, 0xF3, 0x5F, 0x8D, 0x55, 0xFA, 0xB7, 0xFF, 0x00,
+	0x04, 0x78, 0xFF, 0x00, 0x93, 0x39, 0x4F, 0xFB, 0x19, 0x75, 0x0F, 0xFD, 0xA5, 0x5C, 0x98, 0xEC,
+	0x3D, 0x2A, 0x34, 0xAF, 0x05, 0x63, 0xAF, 0x03, 0x5E, 0xAD, 0x5A, 0xD6, 0x9B, 0xBE, 0x87, 0x43,
+	0xF1, 0xFF, 0x00, 0xF6, 0xA8, 0xF8, 0x91, 0xF0, 0xA7, 0xE2, 0x45, 0xC7, 0x83, 0xB4, 0x2D, 0x37,
+	0x48, 0x9A, 0xDE, 0x08, 0x63, 0x93, 0xCD, 0xBD, 0xB7, 0x98, 0xBF, 0xCC, 0x3A, 0x65, 0x64, 0x19,
+	0xFC, 0x85, 0x71, 0x3F, 0xF0, 0xDD, 0x7F, 0x18, 0x07, 0x07, 0x46, 0xF0, 0xFF, 0x00, 0xE3, 0x6B,
+	0x3F, 0xFF, 0x00, 0x1F, 0xAC, 0xBF, 0xDB, 0x3F, 0xFE, 0x4B, 0xEE, 0xA3, 0xFF, 0x00, 0x5E, 0xD6,
+	0x9F, 0xFA, 0x05, 0x79, 0x48, 0xE9, 0x5F, 0xE6, 0xBF, 0x88, 0x5E, 0x29, 0x71, 0xEE, 0x53, 0xC6,
+	0xF8, 0xFC, 0x26, 0x17, 0x1F, 0x38, 0xD3, 0xA7, 0x56, 0x4A, 0x29, 0x3D, 0x12, 0xD3, 0x45, 0xA1,
+	0xFD, 0x17, 0x90, 0xF0, 0xD6, 0x47, 0x8A, 0xC9, 0xA8, 0x56, 0xAB, 0x41, 0x39, 0x4A, 0x29, 0xB7,
+	0xAE, 0xBF, 0x89, 0xED, 0x5F, 0xF0, 0xDD, 0x9F, 0x18, 0x3F, 0xE8, 0x0D, 0xE1, 0xEF, 0xFC, 0x05,
+	0x9B, 0xFF, 0x00, 0x8F, 0xD1, 0xFF, 0x00, 0x0D, 0xD9, 0xF1, 0x83, 0xFE, 0x80, 0xDE, 0x1E, 0xFF,
+	0x00, 0xC0, 0x59, 0xBF, 0xF8, 0xFD, 0x78, 0xAD, 0x15, 0xF1, 0x7F, 0xF1, 0x19, 0x3C, 0x49, 0xFF,
+	0x00, 0xA1, 0x95, 0x4F, 0xBD, 0x7F, 0x91, 0xEB, 0x7F, 0xAA, 0x3C, 0x3B, 0xFF, 0x00, 0x40, 0xEB,
+	0xEF, 0x7F, 0xE6, 0x7B, 0x57, 0xFC, 0x37, 0x67, 0xC6, 0x0F, 0xFA, 0x03, 0x78, 0x7B, 0xFF, 0x00,
+	0x01, 0x66, 0xFF, 0x00, 0xE3, 0xF5, 0xF5, 0x47, 0xC3, 0x9D, 0x7E, 0xF7, 0xC5, 0x7F, 0x0F, 0xF4,
+	0x3F, 0x14, 0x6A, 0x49, 0x1A, 0xDC, 0x6A, 0x3A, 0x4D, 0xBD, 0xCC, 0xCB, 0x0A, 0x90, 0x81, 0x9E,
+	0x25, 0x62, 0x14, 0x12, 0x4E, 0x32, 0x78, 0xC9, 0x27, 0xDC, 0xD7, 0xE7, 0x6D, 0x7E, 0x82, 0x7C,
+	0x12, 0xFF, 0x00, 0x92, 0x37, 0xE1, 0x3F, 0xFB, 0x16, 0xEC, 0xBF, 0xF4, 0x42, 0x57, 0xF4, 0x77,
+	0xD1, 0xC7, 0x8D, 0xB8, 0xA3, 0x8B, 0x33, 0xAC, 0x7D, 0x2C, 0xD7, 0x13, 0x2A, 0xB1, 0x85, 0x38,
+	0xB8, 0xA9, 0x3D, 0x9B, 0x95, 0x9B, 0x5A, 0x1F, 0x03, 0xC7, 0x99, 0x3E, 0x5B, 0x95, 0xE1, 0x68,
+	0x4B, 0x0D, 0x4D, 0x45, 0xC9, 0xB4, 0xED, 0x7E, 0xC8, 0xF9, 0x2F, 0xF6, 0x83, 0xFF, 0x00, 0x82,
+	0x90, 0xFC, 0x71, 0xF8, 0x4D, 0xF1, 0xB3, 0xC4, 0x5F, 0x0E, 0x3C, 0x3B, 0xE1, 0x7F, 0x0A, 0xDC,
+	0x59, 0xE9, 0x5A, 0x91, 0xB6, 0xB5, 0x97, 0x50, 0xB1, 0xBA, 0x32, 0xB0, 0xDB, 0xBB, 0xAA, 0xCE,
+	0x01, 0x38, 0xEE, 0x00, 0x1E, 0xD5, 0xC6, 0xFF, 0x00, 0xC3, 0xD9, 0xFF, 0x00, 0x68, 0x73, 0xC8,
+	0xF0, 0x57, 0x82, 0xC7, 0xB3, 0x58, 0xDE, 0xE7, 0xFF, 0x00, 0x4A, 0x6B, 0xCB, 0xFF, 0x00, 0x6D,
+	0x3F, 0xF9, 0x3A, 0xEF, 0x1B, 0x7F, 0xD8, 0x70, 0xFF, 0x00, 0xE8, 0x2B, 0x5E, 0x58, 0x9F, 0x70,
+	0x7D, 0x2B, 0xFA, 0xDC, 0xFC, 0xD0, 0xFA, 0x8F, 0xFE, 0x1E, 0xCF, 0xFB, 0x44, 0x7F, 0xD0, 0x99,
+	0xE0, 0xBF, 0xFC, 0x01, 0xBD, 0xFF, 0x00, 0xE4, 0x9A, 0x3F, 0xE1, 0xEC, 0xFF, 0x00, 0xB4, 0x47,
+	0xFD, 0x09, 0x9E, 0x0B, 0xFF, 0x00, 0xC0, 0x1B, 0xDF, 0xFE, 0x49, 0xAF, 0x97, 0x68, 0xA0, 0x0F,
+	0xA8, 0xBF, 0xE1, 0xEC, 0xFF, 0x00, 0xB4, 0x47, 0xFD, 0x09, 0x9E, 0x0B, 0xFF, 0x00, 0xC0, 0x1B,
+	0xDF, 0xFE, 0x49, 0xAF, 0xA4, 0xBF, 0x61, 0x2F, 0xDA, 0x4F, 0xC7, 0x9F, 0xB4, 0xC7, 0x87, 0x7C,
+	0x49, 0xE2, 0xAF, 0x1D, 0x69, 0x3A, 0x4D, 0x9D, 0xCE, 0x9F, 0x7B, 0x6F, 0x69, 0x0A, 0xE9, 0x10,
+	0x4A, 0xA8, 0x57, 0x6B, 0x3E, 0x48, 0x79, 0x1C, 0x93, 0xF3, 0x7B, 0x7F, 0x87, 0xE6, 0x5D, 0x7D,
+	0xE9, 0xFF, 0x00, 0x04, 0x88, 0x5D, 0xFF, 0x00, 0x0C, 0xBC, 0x62, 0xA7, 0xFE, 0x83, 0x90, 0x75,
+	0x1F, 0xF4, 0xC6, 0x80, 0x24, 0xFD, 0xB2, 0xFF, 0x00, 0x6E, 0x2F, 0x8A, 0xFF, 0x00, 0xB3, 0x67,
+	0xC6, 0x7F, 0xF8, 0x40, 0xFC, 0x0B, 0xA0, 0x78, 0x76, 0xEA, 0xCE, 0x7D, 0x2E, 0x2B, 0xD9, 0x1B,
+	0x56, 0xB6, 0x9D, 0xA4, 0x0E, 0xEC, 0xCB, 0xC7, 0x97, 0x32, 0xFF, 0x00, 0x73, 0xD2, 0xBC, 0xA7,
+	0xFE, 0x1E, 0xCF, 0xFB, 0x44, 0x7F, 0xD0, 0x99, 0xE0, 0xBF, 0xFC, 0x01, 0xBD, 0xFF, 0x00, 0xE4,
+	0x9A, 0xA1, 0xFF, 0x00, 0x05, 0x51, 0xFF, 0x00, 0x93, 0x99, 0xB7, 0xFF, 0x00, 0xB1, 0x62, 0xD7,
+	0xFF, 0x00, 0x43, 0x96, 0xBE, 0x6C, 0xA0, 0x0F, 0xA8, 0xBF, 0xE1, 0xEC, 0xFF, 0x00, 0xB4, 0x47,
+	0xFD, 0x09, 0x9E, 0x0B, 0xFF, 0x00, 0xC0, 0x1B, 0xDF, 0xFE, 0x49, 0xA3, 0xFE, 0x1E, 0xCF, 0xFB,
+	0x44, 0x7F, 0xD0, 0x99, 0xE0, 0xBF, 0xFC, 0x01, 0xBD, 0xFF, 0x00, 0xE4, 0x9A, 0xF9, 0x76, 0x8A,
+	0x00, 0xFA, 0x86, 0x4F, 0xF8, 0x2B, 0x2F, 0xED, 0x12, 0xC9, 0xB5, 0x7C, 0x17, 0xE0, 0xCF, 0xF8,
+	0x0E, 0x9F, 0x7A, 0x7F, 0xF6, 0xE8, 0x7F, 0x3F, 0xF0, 0xAF, 0xA3, 0xFF, 0x00, 0x60, 0xCF, 0xDA,
+	0x9F, 0xE2, 0x0F, 0xED, 0x3D, 0xA1, 0x78, 0x9B, 0x50, 0xF1, 0xE6, 0x97, 0xA2, 0xDA, 0x4D, 0xA3,
+	0xDD, 0xDB, 0x47, 0x6E, 0xBA, 0x2C, 0x32, 0x2A, 0x91, 0x2F, 0x98, 0xC4, 0xB0, 0x79, 0x24, 0x39,
+	0xF9, 0x47, 0x7A, 0xFC, 0xCF, 0xED, 0xF8, 0x57, 0xDC, 0xDF, 0xF0, 0x48, 0x35, 0xDF, 0xE1, 0xAF,
+	0x1F, 0x29, 0xFF, 0x00, 0xA0, 0x85, 0x87, 0x51, 0xFF, 0x00, 0x4C, 0xE6, 0xA0, 0x0D, 0x2F, 0xDB,
+	0x2F, 0xF6, 0xE2, 0xF8, 0xAF, 0xFB, 0x36, 0x7C, 0x67, 0xFF, 0x00, 0x84, 0x0F, 0xC0, 0xBA, 0x07,
+	0x87, 0x6E, 0xAC, 0xE7, 0xD2, 0xE2, 0xBD, 0x91, 0xB5, 0x6B, 0x69, 0xDA, 0x40, 0xEE, 0xCC, 0xBC,
+	0x79, 0x73, 0x2F, 0xF7, 0x3D, 0x2B, 0xCA, 0x7F, 0xE1, 0xEC, 0xFF, 0x00, 0xB4, 0x47, 0xFD, 0x09,
+	0x9E, 0x0B, 0xFF, 0x00, 0xC0, 0x1B, 0xDF, 0xFE, 0x49, 0xAA, 0x1F, 0xF0, 0x55, 0x1F, 0xF9, 0x39,
+	0x9B, 0x7F, 0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0x00, 0xFA, 0x8B, 0xFE, 0x1E,
+	0xCF, 0xFB, 0x44, 0x7F, 0xD0, 0x99, 0xE0, 0xBF, 0xFC, 0x01, 0xBD, 0xFF, 0x00, 0xE4, 0x9A, 0x3F,
+	0xE1, 0xEC, 0xFF, 0x00, 0xB4, 0x47, 0xFD, 0x09, 0x9E, 0x0B, 0xFF, 0x00, 0xC0, 0x1B, 0xDF, 0xFE,
+	0x49, 0xAF, 0x97, 0x68, 0xA0, 0x0F, 0xA8, 0x64, 0xFF, 0x00, 0x82, 0xB2, 0xFE, 0xD1, 0x2C, 0x9B,
+	0x57, 0xC1, 0x7E, 0x0C, 0xFF, 0x00, 0x80, 0xE9, 0xF7, 0xA7, 0xFF, 0x00, 0x6E, 0x87, 0xF3, 0xFF,
+	0x00, 0x0A, 0xFA, 0x2F, 0xF6, 0x10, 0xFD, 0xA9, 0x7E, 0x21, 0xFE, 0xD4, 0x1A, 0x4F, 0x88, 0xB5,
+	0x0F, 0x1E, 0xE9, 0xBA, 0x35, 0x9C, 0x9A, 0x3D, 0xD5, 0xBC, 0x70, 0xAE, 0x8B, 0x1C, 0x88, 0xA7,
+	0xCC, 0x12, 0x37, 0xCC, 0x1E, 0x49, 0x3F, 0xBB, 0x5F, 0x9A, 0x7D, 0xBF, 0x0A, 0xFB, 0x9B, 0xFE,
+	0x09, 0x07, 0xFF, 0x00, 0x22, 0xEF, 0x8F, 0x3F, 0xEC, 0x21, 0x63, 0xFF, 0x00, 0xA2, 0xE6, 0xA0,
+	0x0F, 0xB2, 0x2C, 0xF0, 0x11, 0x95, 0x7E, 0xE8, 0x6C, 0x2E, 0x33, 0x8C, 0x60, 0x63, 0x1C, 0x9E,
+	0x31, 0xE9, 0x53, 0x54, 0x70, 0x7F, 0x17, 0xFB, 0xC3, 0xFF, 0x00, 0x41, 0x15, 0x25, 0x00, 0x14,
+	0x1E, 0x94, 0x50, 0x7A, 0x50, 0x07, 0xC2, 0x9F, 0xF0, 0x57, 0xDF, 0xF9, 0x19, 0x3C, 0x0F, 0xFF,
+	0x00, 0x5E, 0x57, 0xDF, 0xFA, 0x32, 0x3A, 0xF8, 0xDA, 0xBE, 0xC9, 0xFF, 0x00, 0x82, 0xBE, 0xFF,
+	0x00, 0xC8, 0xC9, 0xE0, 0x7F, 0xFA, 0xF2, 0xBE, 0xFF, 0x00, 0xD1, 0x91, 0xD7, 0xC6, 0xD4, 0x00,
+	0x51, 0x45, 0x14, 0x00, 0x0E, 0xB5, 0xF5, 0x87, 0xFC, 0x12, 0x3F, 0xFE, 0x4B, 0x57, 0x89, 0x7F,
+	0xEC, 0x55, 0x5F, 0xFD, 0x29, 0x8A, 0xBE, 0x4F, 0x1D, 0x6B, 0xEB, 0x0F, 0xF8, 0x24, 0x7F, 0xFC,
+	0x96, 0xAF, 0x12, 0xFF, 0x00, 0xD8, 0xAA, 0xBF, 0xFA, 0x53, 0x15, 0x00, 0x7A, 0xEF, 0xFC, 0x15,
+	0x97, 0xFE, 0x4D, 0xC7, 0x47, 0xFF, 0x00, 0xB1, 0xCE, 0xD7, 0xFF, 0x00, 0x49, 0x6F, 0x6B, 0xF3,
+	0xCA, 0xBF, 0x43, 0x7F, 0xE0, 0xAC, 0xBF, 0xF2, 0x6E, 0x3A, 0x3F, 0xFD, 0x8E, 0x76, 0xBF, 0xFA,
+	0x4B, 0x7B, 0x5F, 0x9E, 0x54, 0x90, 0x05, 0x14, 0x51, 0x4C, 0x02, 0xBD, 0xEB, 0xFE, 0x09, 0xB1,
+	0xFF, 0x00, 0x27, 0x73, 0xA0, 0xFF, 0x00, 0xD8, 0x3F, 0x50, 0xFF, 0x00, 0xD2, 0x77, 0xAF, 0x05,
+	0xAF, 0x7A, 0xFF, 0x00, 0x82, 0x6C, 0x7F, 0xC9, 0xDC, 0xE8, 0x3F, 0xF6, 0x0F, 0xD4, 0x3F, 0xF4,
+	0x9D, 0xE8, 0x03, 0xEC, 0x9F, 0xF8, 0x28, 0x8F, 0xFC, 0x99, 0xDF, 0x8C, 0x7F, 0xDC, 0xB2, 0xFF,
+	0x00, 0xD3, 0x85, 0xAD, 0x7E, 0x5E, 0x57, 0xEA, 0x1F, 0xFC, 0x14, 0x47, 0xFE, 0x4C, 0xEF, 0xC6,
+	0x3F, 0xEE, 0x59, 0x7F, 0xE9, 0xC2, 0xD6, 0xBF, 0x2F, 0x29, 0x20, 0x0A, 0x28, 0xA2, 0x98, 0x05,
+	0x7A, 0x27, 0xEC, 0x95, 0xFF, 0x00, 0x27, 0x39, 0xE0, 0x1F, 0xFB, 0x1A, 0xAD, 0x3F, 0xF4, 0x21,
+	0x5E, 0x77, 0x5E, 0x89, 0xFB, 0x25, 0x7F, 0xC9, 0xCE, 0x78, 0x07, 0xFE, 0xC6, 0xAB, 0x4F, 0xFD,
+	0x08, 0x50, 0x07, 0xE9, 0x77, 0xED, 0x4D, 0xFF, 0x00, 0x26, 0xC9, 0xF1, 0x17, 0xFE, 0xC4, 0x5D,
+	0x5F, 0xFF, 0x00, 0x48, 0x27, 0xAF, 0xC6, 0x1A, 0xFD, 0x9E, 0xFD, 0xA9, 0xBF, 0xE4, 0xD9, 0x3E,
+	0x22, 0xFF, 0x00, 0xD8, 0x8B, 0xAB, 0xFF, 0x00, 0xE9, 0x04, 0xF5, 0xF8, 0xC3, 0x5C, 0xF5, 0xBA,
+	0x1A, 0x53, 0x0A, 0x28, 0xA2, 0xB9, 0xCD, 0x02, 0xBE, 0x8C, 0xFF, 0x00, 0x82, 0x55, 0x7F, 0xC9,
+	0xE2, 0xE9, 0x5F, 0xF6, 0x07, 0xBF, 0xFF, 0x00, 0xD1, 0x0D, 0x5F, 0x39, 0xD7, 0xD1, 0x9F, 0xF0,
+	0x4A, 0xAF, 0xF9, 0x3C, 0x5D, 0x2B, 0xFE, 0xC0, 0xF7, 0xFF, 0x00, 0xFA, 0x21, 0xAA, 0xA9, 0xFC,
+	0x48, 0x99, 0x7C, 0x27, 0xD4, 0xDF, 0xF0, 0x58, 0xA3, 0xFF, 0x00, 0x18, 0x73, 0x37, 0xFD, 0x8C,
+	0xD6, 0x5F, 0xCA, 0x5A, 0xFC, 0xA1, 0x3D, 0x6B, 0xF5, 0x7B, 0xFE, 0x0B, 0x14, 0x7F, 0xE3, 0x0E,
+	0x66, 0xFF, 0x00, 0xB1, 0x9A, 0xCB, 0xF9, 0x4B, 0x5F, 0x94, 0x27, 0xAD, 0x7D, 0x56, 0x5B, 0xFE,
+	0xEF, 0xF3, 0x3E, 0x6B, 0x30, 0xFE, 0x33, 0xF4, 0x41, 0x45, 0x14, 0x57, 0xA0, 0x71, 0x05, 0x7E,
+	0x80, 0x7F, 0xC1, 0x0B, 0x7E, 0xFF, 0x00, 0xC5, 0x1F, 0xF7, 0xB4, 0x5F, 0xFD, 0x02, 0xFE, 0xBF,
+	0x3F, 0xEB, 0xF4, 0x03, 0xFE, 0x08, 0x5B, 0xF7, 0xFE, 0x28, 0xFF, 0x00, 0xBD, 0xA2, 0xFF, 0x00,
+	0xE8, 0x17, 0xF5, 0xC7, 0x8F, 0xFF, 0x00, 0x77, 0x67, 0x5E, 0x07, 0xFD, 0xE1, 0x1D, 0xE7, 0xFC,
+	0x16, 0x0B, 0xFE, 0x40, 0x3E, 0x05, 0xFF, 0x00, 0xAF, 0xEB, 0xEF, 0xFD, 0x02, 0x3A, 0xF8, 0x6E,
+	0xBE, 0xE4, 0xFF, 0x00, 0x82, 0xC1, 0x7F, 0xC8, 0x07, 0xC0, 0xBF, 0xF5, 0xFD, 0x7D, 0xFF, 0x00,
+	0xA0, 0x47, 0x5F, 0x0D, 0xD7, 0xCF, 0x9F, 0x42, 0x14, 0x51, 0x5C, 0xCF, 0xC6, 0x1F, 0x8A, 0xDE,
+	0x09, 0xF8, 0x29, 0xF0, 0xEF, 0x53, 0xF8, 0x99, 0xF1, 0x0F, 0x53, 0x92, 0xD7, 0x4B, 0xD2, 0xED,
+	0xD9, 0xA6, 0x92, 0x26, 0xDB, 0x3C, 0x84, 0x8F, 0x96, 0x28, 0x7F, 0xBF, 0x29, 0x6C, 0x04, 0xFE,
+	0xE9, 0xDD, 0x44, 0xBD, 0xD5, 0x70, 0x49, 0xC9, 0xD9, 0x1C, 0x77, 0xED, 0x7F, 0xFB, 0x55, 0xF8,
+	0x63, 0xF6, 0x54, 0xF8, 0x66, 0xDE, 0x28, 0xBF, 0x8A, 0xD6, 0xFB, 0x5A, 0xD4, 0x19, 0xAD, 0xFC,
+	0x3F, 0xA4, 0xCD, 0x27, 0xFC, 0x7D, 0x4B, 0xB7, 0x1B, 0xDC, 0x77, 0x86, 0x33, 0xFE, 0xB1, 0xBA,
+	0x80, 0x15, 0x7A, 0xBC, 0x55, 0xF9, 0x23, 0xE3, 0x7F, 0x1E, 0xF8, 0xBF, 0xE2, 0x57, 0x8C, 0x2F,
+	0x7E, 0x20, 0xF8, 0xE7, 0x55, 0xBB, 0xD5, 0x35, 0x8D, 0x52, 0xE4, 0x5C, 0xDD, 0xDC, 0x5C, 0x36,
+	0x24, 0x96, 0x40, 0x30, 0xA0, 0x27, 0xF0, 0xA2, 0x83, 0xC0, 0xEC, 0x38, 0xAE, 0x87, 0xF6, 0x8D,
+	0xFD, 0xA0, 0x3C, 0x6F, 0xFB, 0x4C, 0x7C, 0x52, 0xBF, 0xF8, 0x95, 0xE3, 0x5F, 0x2E, 0x09, 0x2E,
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+	0x82, 0x47, 0x9D, 0x62, 0xD4, 0x6F, 0x70, 0x60, 0x86, 0xF3, 0x23, 0x95, 0xFF, 0x00, 0x51, 0x9C,
+	0x0D, 0x95, 0xFA, 0x05, 0xFF, 0x00, 0x07, 0x37, 0xB0, 0x8B, 0xFE, 0x08, 0xEF, 0xF1, 0x02, 0x40,
+	0x55, 0x54, 0x6B, 0x9A, 0x01, 0xCB, 0x3E, 0xC5, 0x45, 0x1A, 0xB5, 0xB6, 0x49, 0xAF, 0xAA, 0xBF,
+	0x6A, 0xDF, 0xD9, 0x0F, 0xF6, 0x77, 0xFD, 0xB4, 0xFE, 0x1D, 0xDB, 0xFC, 0x2E, 0xFD, 0xA4, 0x7E,
+	0x1B, 0xDB, 0x78, 0x9B, 0x45, 0xB2, 0xD7, 0x2D, 0x75, 0x7B, 0x3B, 0x59, 0x66, 0x96, 0x36, 0x86,
+	0xEA, 0xDC, 0xE5, 0x64, 0x47, 0x8B, 0xE7, 0x01, 0x91, 0xE4, 0x8D, 0x94, 0x70, 0xD1, 0xCC, 0xEA,
+	0x7E, 0xFD, 0x3B, 0xF6, 0xC7, 0xFD, 0x90, 0xFE, 0x0F, 0x7E, 0xDC, 0x3F, 0x00, 0xB5, 0x2F, 0xD9,
+	0xCF, 0xE3, 0xB5, 0x8D, 0xF5, 0xC7, 0x86, 0xB5, 0x7B, 0x8B, 0x59, 0xEE, 0xE1, 0xB0, 0xBC, 0x36,
+	0xF2, 0xEE, 0x82, 0x55, 0x96, 0x3C, 0x38, 0xE9, 0xF3, 0xA2, 0xD5, 0x28, 0xF6, 0x14, 0xA4, 0x9C,
+	0x93, 0x31, 0x7F, 0x66, 0xCF, 0xDA, 0x57, 0xF6, 0x73, 0xD3, 0xFF, 0x00, 0x67, 0x5F, 0x00, 0xD8,
+	0x5F, 0x7C, 0x7C, 0xF0, 0x5C, 0x13, 0x41, 0xE0, 0xAD, 0x2A, 0x39, 0xA0, 0x9B, 0xC5, 0x56, 0x88,
+	0xF1, 0xB0, 0xB4, 0x88, 0x15, 0x65, 0x67, 0x04, 0x10, 0x78, 0x20, 0xF2, 0x0F, 0x5A, 0xF5, 0xAF,
+	0x0E, 0xF8, 0xAF, 0xC2, 0xFE, 0x33, 0xD2, 0x63, 0xF1, 0x17, 0x85, 0x75, 0xDB, 0x1D, 0x53, 0x4F,
+	0xB8, 0xDE, 0x61, 0xBE, 0xB1, 0xB9, 0x59, 0xE1, 0x95, 0x54, 0xE1, 0xB0, 0xEA, 0x71, 0xD7, 0xB8,
+	0xE2, 0xBF, 0x3D, 0xD3, 0xFE, 0x0D, 0x61, 0xFF, 0x00, 0x82, 0x4C, 0x6C, 0x5F, 0xF8, 0xA3, 0x7C,
+	0x71, 0xD3, 0xA3, 0x78, 0xCA, 0x52, 0x7F, 0x3D, 0x86, 0xBE, 0xC0, 0xFD, 0x90, 0x3F, 0x63, 0xAF,
+	0x80, 0xDF, 0xB0, 0x8F, 0xC1, 0x3B, 0x4F, 0xD9, 0xF3, 0xF6, 0x72, 0xF0, 0xC5, 0xC6, 0x9D, 0xE1,
+	0xCB, 0x2B, 0xA9, 0xEE, 0x96, 0x2B, 0xCD, 0x42, 0x49, 0xE7, 0x9E, 0xE2, 0x57, 0xDC, 0xEF, 0x24,
+	0x92, 0x10, 0x4E, 0xE6, 0xC0, 0x00, 0x00, 0xBC, 0x70, 0x31, 0x9A, 0x23, 0xD8, 0x89, 0x7B, 0x3E,
+	0x8C, 0xF5, 0xD5, 0x1B, 0x54, 0x0C, 0x93, 0xC7, 0x53, 0x4B, 0x48, 0x80, 0xAA, 0x2A, 0x92, 0x4E,
+	0x07, 0x56, 0xEF, 0x4B, 0x54, 0x49, 0xF9, 0x15, 0xFF, 0x00, 0x07, 0x85, 0x7F, 0xC9, 0x93, 0xFC,
+	0x31, 0xFF, 0x00, 0xB2, 0xA8, 0x3F, 0xF4, 0xD9, 0x77, 0x5F, 0xCF, 0x45, 0x7F, 0x42, 0xFF, 0x00,
+	0xF0, 0x78, 0x57, 0xFC, 0x99, 0x3F, 0xC3, 0x1F, 0xFB, 0x2A, 0x83, 0xFF, 0x00, 0x4D, 0x97, 0x75,
+	0xFC, 0xF4, 0x57, 0x3D, 0x4F, 0x8C, 0xF5, 0x30, 0xDF, 0xC1, 0x41, 0x45, 0x14, 0x56, 0x66, 0x81,
+	0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x04,
+	0xDA, 0x6E, 0xA7, 0x7B, 0xA4, 0xEA, 0x30, 0xEA, 0xFA, 0x64, 0xF2, 0xDB, 0xDC, 0x5A, 0x5C, 0x47,
+	0x34, 0x37, 0x16, 0xFD, 0x62, 0x91, 0x0F, 0xCA, 0xD5, 0xFA, 0x99, 0xFB, 0x00, 0x7E, 0xDA, 0xB0,
+	0xFE, 0xD3, 0x1E, 0x08, 0x6F, 0x09, 0x78, 0xE7, 0x53, 0x85, 0x7C, 0x71, 0xA2, 0xDA, 0xFF, 0x00,
+	0xC4, 0xC0, 0x4A, 0xDB, 0x46, 0xA3, 0x0F, 0x00, 0x5E, 0xE7, 0xB0, 0x1F, 0xF2, 0xD3, 0xFB, 0x92,
+	0x13, 0x27, 0xF1, 0x57, 0xE5, 0x6D, 0x6E, 0xFC, 0x36, 0xF8, 0x89, 0xE3, 0x0F, 0x85, 0x3E, 0x38,
+	0xD2, 0xFE, 0x21, 0xF8, 0x0B, 0x54, 0x92, 0xC7, 0x56, 0xD2, 0xAE, 0x44, 0x96, 0xF3, 0x2C, 0xDD,
+	0x0E, 0x79, 0x46, 0xF6, 0x75, 0xFE, 0x75, 0x51, 0x97, 0x2B, 0xB9, 0x9D, 0x5A, 0x7E, 0xD2, 0x99,
+	0xFB, 0x80, 0xD8, 0xDC, 0x76, 0x86, 0xC6, 0x7F, 0xE5, 0xA2, 0xE1, 0xBF, 0x11, 0xD8, 0xD2, 0x57,
+	0x9B, 0xFE, 0xCB, 0x7F, 0xB4, 0x7F, 0x85, 0xBF, 0x6A, 0x1F, 0x85, 0x56, 0x9F, 0x10, 0xFC, 0x37,
+	0x1C, 0x71, 0xDF, 0x71, 0x06, 0xB5, 0xA3, 0xB1, 0xE6, 0xD2, 0xED, 0x46, 0x3C, 0xAF, 0xFA, 0xE6,
+	0xFC, 0xB2, 0xFB, 0x62, 0xBD, 0x23, 0x8E, 0xCC, 0x5B, 0xFD, 0xA3, 0xDE, 0xBA, 0x96, 0xAA, 0xE7,
+	0x96, 0xE2, 0xE2, 0xEC, 0xC2, 0xBE, 0xE3, 0xFF, 0x00, 0x82, 0x41, 0xFF, 0x00, 0xC8, 0xB7, 0xE3,
+	0xAF, 0xFA, 0xFF, 0x00, 0xB1, 0xFF, 0x00, 0xD1, 0x57, 0x15, 0xF0, 0xE5, 0x7D, 0xC7, 0xFF, 0x00,
+	0x04, 0x83, 0xFF, 0x00, 0x91, 0x6F, 0xC7, 0x5F, 0xF5, 0xFF, 0x00, 0x63, 0xFF, 0x00, 0xA2, 0xAE,
+	0x28, 0x03, 0x86, 0xFF, 0x00, 0x82, 0xEB, 0xFF, 0x00, 0xAC, 0xF8, 0x5B, 0xFE, 0xEE, 0xB7, 0xFC,
+	0xF4, 0xFA, 0xFC, 0xFD, 0xAF, 0xD0, 0x2F, 0xF8, 0x2E, 0xBF, 0xFA, 0xCF, 0x85, 0xBF, 0xEE, 0xEB,
+	0x7F, 0xCF, 0x4F, 0xAF, 0xCF, 0xDA, 0xFA, 0x0C, 0xBF, 0xFD, 0xD8, 0xF9, 0xEC, 0x6F, 0xFB, 0xD3,
+	0x0A, 0x28, 0xA2, 0xBB, 0x0E, 0x40, 0xAF, 0xD5, 0xBF, 0xF8, 0x23, 0xC7, 0xFC, 0x99, 0xCA, 0x7F,
+	0xD8, 0xCB, 0xA8, 0x7F, 0xED, 0x2A, 0xFC, 0xA4, 0xAF, 0xD5, 0xBF, 0xF8, 0x23, 0xC7, 0xFC, 0x99,
+	0xCA, 0x7F, 0xD8, 0xCB, 0xA8, 0x7F, 0xED, 0x2A, 0xE0, 0xCC, 0xBF, 0x83, 0xF3, 0x47, 0x76, 0x5D,
+	0xFE, 0xF1, 0xF2, 0x39, 0x6F, 0xDB, 0x3F, 0xFE, 0x4B, 0xEE, 0xA3, 0xFF, 0x00, 0x5E, 0xD6, 0x9F,
+	0xFA, 0x05, 0x79, 0x48, 0xE9, 0x5E, 0xAD, 0xFB, 0x67, 0xFF, 0x00, 0xC9, 0x7D, 0xD4, 0x7F, 0xEB,
+	0xDA, 0xD3, 0xFF, 0x00, 0x40, 0xAF, 0x29, 0x1D, 0x2B, 0xFC, 0x91, 0xF1, 0x5B, 0xFE, 0x4E, 0x2E,
+	0x67, 0xFF, 0x00, 0x5F, 0x65, 0xFA, 0x1F, 0xD5, 0xDC, 0x33, 0xFF, 0x00, 0x24, 0xFE, 0x1B, 0xFC,
+	0x08, 0x28, 0xA2, 0x8A, 0xFC, 0xF0, 0xF7, 0x02, 0xBF, 0x41, 0x3E, 0x09, 0x7F, 0xC9, 0x1B, 0xF0,
+	0x9F, 0xFD, 0x8B, 0x76, 0x5F, 0xFA, 0x21, 0x2B, 0xF3, 0xEE, 0xBF, 0x41, 0x3E, 0x09, 0x7F, 0xC9,
+	0x1B, 0xF0, 0x9F, 0xFD, 0x8B, 0x76, 0x5F, 0xFA, 0x21, 0x2B, 0xFA, 0xCB, 0xE8, 0x9F, 0xFF, 0x00,
+	0x25, 0x06, 0x65, 0xFF, 0x00, 0x5E, 0xA1, 0xFF, 0x00, 0xA5, 0x9F, 0x98, 0xF8, 0x99, 0xFE, 0xE7,
+	0x87, 0xFF, 0x00, 0x13, 0xFC, 0x91, 0xF9, 0x93, 0xFB, 0x69, 0xFF, 0x00, 0xC9, 0xD7, 0x78, 0xDB,
+	0xFE, 0xC3, 0x87, 0xFF, 0x00, 0x41, 0x5A, 0xF2, 0xC4, 0xFB, 0x83, 0xE9, 0x5E, 0xA7, 0xFB, 0x69,
+	0xFF, 0x00, 0xC9, 0xD7, 0x78, 0xDB, 0xFE, 0xC3, 0x87, 0xFF, 0x00, 0x41, 0x5A, 0xF2, 0xC4, 0xFB,
+	0x83, 0xE9, 0x5F, 0xDC, 0x47, 0xE4, 0x22, 0xD1, 0x45, 0x14, 0x00, 0x57, 0xDE, 0x9F, 0xF0, 0x48,
+	0x5F, 0xF9, 0x26, 0xBE, 0x30, 0xFF, 0x00, 0xB0, 0xE4, 0x1F, 0xFA, 0x26, 0xBE, 0x0B, 0xAF, 0xBD,
+	0x3F, 0xE0, 0x90, 0xBF, 0xF2, 0x4D, 0x7C, 0x61, 0xFF, 0x00, 0x61, 0xC8, 0x3F, 0xF4, 0x4D, 0x00,
+	0x78, 0xF7, 0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B, 0x5F, 0xFD, 0x0E, 0x5A,
+	0xF9, 0xB2, 0xBE, 0x93, 0xFF, 0x00, 0x82, 0xA8, 0xFF, 0x00, 0xC9, 0xCC, 0xDB, 0xFF, 0x00, 0xD8,
+	0xB1, 0x6B, 0xFF, 0x00, 0xA1, 0xCB, 0x5F, 0x36, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0xDB, 0xF0,
+	0xAF, 0xBA, 0x3F, 0xE0, 0x90, 0x1F, 0xF2, 0x2E, 0x78, 0xFB, 0xFE, 0xC2, 0x16, 0x1F, 0xFA, 0x2E,
+	0x6A, 0xF8, 0x5F, 0xB7, 0xE1, 0x5F, 0x74, 0x7F, 0xC1, 0x20, 0x3F, 0xE4, 0x5C, 0xF1, 0xF7, 0xFD,
+	0x84, 0x2C, 0x3F, 0xF4, 0x5C, 0xD4, 0x01, 0xE5, 0x5F, 0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B, 0x7F,
+	0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0xFA, 0x4F, 0xFE, 0x0A, 0xA3, 0xFF, 0x00,
+	0x27, 0x33, 0x6F, 0xFF, 0x00, 0x62, 0xC5, 0xAF, 0xFE, 0x87, 0x2D, 0x7C, 0xD9, 0x40, 0x05, 0x14,
+	0x51, 0x40, 0x07, 0x6F, 0xC2, 0xBE, 0xE6, 0xFF, 0x00, 0x82, 0x41, 0xFF, 0x00, 0xC8, 0xBB, 0xE3,
+	0xCF, 0xFB, 0x08, 0x58, 0xFF, 0x00, 0xE8, 0xB9, 0xAB, 0xE1, 0x9E, 0xDF, 0x85, 0x7D, 0xCD, 0xFF,
+	0x00, 0x04, 0x83, 0xFF, 0x00, 0x91, 0x77, 0xC7, 0x9F, 0xF6, 0x10, 0xB1, 0xFF, 0x00, 0xD1, 0x73,
+	0x50, 0x07, 0xD9, 0x50, 0x7F, 0x17, 0xFB, 0xC3, 0xFF, 0x00, 0x41, 0x15, 0x25, 0x47, 0x07, 0xF1,
+	0x7F, 0xBC, 0x3F, 0xF4, 0x11, 0x52, 0x50, 0x01, 0x41, 0xE4, 0x62, 0x8A, 0x0F, 0x4A, 0x00, 0xF8,
+	0x6F, 0xFE, 0x0A, 0xEB, 0xA6, 0xEA, 0x1A, 0x8F, 0x89, 0x3C, 0x0E, 0x34, 0xFD, 0x3E, 0x5B, 0x82,
+	0xB6, 0x37, 0xD9, 0xF2, 0xED, 0xCB, 0x6D, 0xF9, 0xE1, 0xF4, 0xAF, 0x8E, 0xBF, 0xE1, 0x1B, 0xF1,
+	0x27, 0xFD, 0x00, 0xAF, 0x7F, 0xF0, 0x16, 0x5A, 0xFD, 0x99, 0x80, 0xE7, 0x5D, 0xB8, 0x3F, 0xF4,
+	0xE7, 0x6F, 0xFF, 0x00, 0xA1, 0x4B, 0x57, 0x28, 0x03, 0xF1, 0x6B, 0xFE, 0x11, 0xBF, 0x12, 0x7F,
+	0xD0, 0x0A, 0xF7, 0xFF, 0x00, 0x01, 0x65, 0xA3, 0xFE, 0x11, 0xBF, 0x12, 0x7F, 0xD0, 0x0A, 0xF7,
+	0xFF, 0x00, 0x01, 0x65, 0xAF, 0xDA, 0x5A, 0x28, 0x03, 0xF1, 0x6D, 0x3C, 0x35, 0xE2, 0x4D, 0xEB,
+	0x9D, 0x06, 0xFB, 0xAF, 0xFC, 0xFA, 0xC9, 0xFD, 0x6B, 0xEA, 0xCF, 0xF8, 0x24, 0xDE, 0x97, 0xAA,
+	0x69, 0xBF, 0x19, 0xFC, 0x44, 0x6F, 0xF4, 0xC9, 0xAD, 0x83, 0x78, 0x54, 0x6D, 0xF3, 0xA3, 0xFB,
+	0xDF, 0xE9, 0x31, 0x57, 0xDF, 0x14, 0x50, 0x07, 0xCB, 0xFF, 0x00, 0xF0, 0x55, 0xCB, 0x3B, 0xBB,
+	0xFF, 0x00, 0xD9, 0xE3, 0x46, 0xB7, 0xB2, 0xB3, 0x79, 0xE4, 0xFF, 0x00, 0x84, 0xCE, 0xD4, 0xF9,
+	0x71, 0xC5, 0xBC, 0x9F, 0xF4, 0x5B, 0xDE, 0xD5, 0xF9, 0xF5, 0xFF, 0x00, 0x08, 0xDF, 0x89, 0x3F,
+	0xE8, 0x05, 0x7B, 0xFF, 0x00, 0x80, 0xB2, 0xD7, 0xED, 0x23, 0x6C, 0xF3, 0x31, 0x8C, 0xB0, 0x5F,
+	0xBD, 0xB7, 0xB7, 0xD6, 0x96, 0x80, 0x3F, 0x16, 0xBF, 0xE1, 0x1B, 0xF1, 0x27, 0xFD, 0x00, 0xAF,
+	0x7F, 0xF0, 0x16, 0x5A, 0x3F, 0xE1, 0x1B, 0xF1, 0x27, 0xFD, 0x00, 0xAF, 0x7F, 0xF0, 0x16, 0x5A,
+	0xFD, 0xA5, 0xA2, 0x80, 0x3F, 0x16, 0xBF, 0xE1, 0x1B, 0xF1, 0x27, 0xFD, 0x00, 0xAF, 0x7F, 0xF0,
+	0x16, 0x5A, 0xF7, 0x9F, 0xF8, 0x27, 0x16, 0x8D, 0xAC, 0x69, 0xFF, 0x00, 0xB5, 0xA6, 0x83, 0x3D,
+	0xE6, 0x8F, 0x71, 0x6E, 0x9F, 0x61, 0xD4, 0x3F, 0x79, 0x34, 0x7F, 0xF4, 0xEE, 0xF5, 0xFA, 0x59,
+	0x45, 0x00, 0x78, 0xA7, 0xFC, 0x14, 0x32, 0x09, 0xAE, 0x7F, 0x64, 0x0F, 0x17, 0xC1, 0x6F, 0x03,
+	0x48, 0xEC, 0xB6, 0x21, 0x63, 0x54, 0xDC, 0x4F, 0xFC, 0x4C, 0x6D, 0x7B, 0x57, 0xE6, 0x31, 0xF0,
+	0xD7, 0x89, 0x01, 0xC7, 0xF6, 0x05, 0xE2, 0xFB, 0x7D, 0x96, 0x4E, 0x3F, 0x2A, 0xFD, 0xA3, 0x7D,
+	0x99, 0x50, 0xC3, 0x2D, 0xD5, 0x78, 0xCE, 0x38, 0xF5, 0xA5, 0xA0, 0x0F, 0xC5, 0xAF, 0xF8, 0x46,
+	0xFC, 0x49, 0xFF, 0x00, 0x40, 0x2B, 0xDF, 0xFC, 0x05, 0x96, 0x8F, 0xF8, 0x46, 0xFC, 0x49, 0xFF,
+	0x00, 0x40, 0x2B, 0xDF, 0xFC, 0x05, 0x96, 0xBF, 0x69, 0x68, 0xA0, 0x0F, 0xC5, 0xAF, 0xF8, 0x46,
+	0xFC, 0x49, 0xFF, 0x00, 0x40, 0x2B, 0xDF, 0xFC, 0x05, 0x96, 0xBD, 0x17, 0xF6, 0x50, 0xD0, 0x75,
+	0xCB, 0x4F, 0xDA, 0x57, 0xC0, 0x77, 0x17, 0x3A, 0x1D, 0xD4, 0x71, 0x8F, 0x15, 0x59, 0xEE, 0x96,
+	0x58, 0xCE, 0x07, 0xCC, 0x3D, 0x6B, 0xF5, 0x82, 0x8A, 0x00, 0xE0, 0x7F, 0x6A, 0x63, 0x9F, 0xD9,
+	0x97, 0xE2, 0x29, 0xCF, 0xFC, 0xC8, 0xBA, 0xBF, 0xFE, 0x90, 0x4F, 0x5F, 0x8C, 0x35, 0xFB, 0xB3,
+	0x73, 0x1C, 0x12, 0xC0, 0x61, 0xB9, 0x8D, 0x5D, 0x1F, 0x82, 0x8C, 0xBB, 0x81, 0xFC, 0x2A, 0x9A,
+	0xF8, 0x57, 0xC3, 0x0A, 0xA1, 0x7F, 0xE1, 0x1B, 0xB1, 0xE3, 0xFE, 0x9D, 0x52, 0xB2, 0xA9, 0x05,
+	0x2B, 0x6A, 0x54, 0x65, 0xCA, 0x7E, 0x19, 0x51, 0x5F, 0xB9, 0xBF, 0xF0, 0x8B, 0xF8, 0x67, 0xFE,
+	0x85, 0x9B, 0x1F, 0xFC, 0x05, 0x4A, 0x3F, 0xE1, 0x17, 0xF0, 0xCF, 0xFD, 0x0B, 0x36, 0x3F, 0xF8,
+	0x0A, 0x95, 0x1E, 0xC5, 0x77, 0x2B, 0x9F, 0xC8, 0xFC, 0x32, 0xAF, 0xA3, 0x3F, 0xE0, 0x95, 0x5F,
+	0xF2, 0x78, 0xBA, 0x57, 0xFD, 0x81, 0xEF, 0xFF, 0x00, 0xF4, 0x43, 0x57, 0xEA, 0x0F, 0xFC, 0x22,
+	0xFE, 0x18, 0xFF, 0x00, 0xA1, 0x6A, 0xCB, 0xFF, 0x00, 0x01, 0x52, 0x9D, 0x6B, 0xA1, 0x68, 0x7A,
+	0x6C, 0xDF, 0x68, 0xB2, 0xD2, 0x6D, 0xA1, 0x66, 0x3F, 0x7A, 0x2B, 0x70, 0xBF, 0xCA, 0x9C, 0x68,
+	0xF2, 0xB4, 0xEE, 0x29, 0x4B, 0x99, 0x1F, 0x31, 0x7F, 0xC1, 0x62, 0x8F, 0xFC, 0x61, 0xCC, 0xDF,
+	0xF6, 0x33, 0x59, 0x7F, 0x29, 0x6B, 0xF2, 0x84, 0xF5, 0xAF, 0xE8, 0x0A, 0xFB, 0x4F, 0xB3, 0xBF,
+	0x83, 0xEC, 0xB7, 0xD6, 0xB1, 0xCD, 0x1E, 0x72, 0x56, 0x68, 0xF7, 0x8A, 0xA6, 0x3C, 0x23, 0xE1,
+	0x50, 0x30, 0xBE, 0x1C, 0xD3, 0x7F, 0xF0, 0x01, 0x2B, 0xD5, 0xC3, 0x63, 0x56, 0x1E, 0x9F, 0x25,
+	0xAE, 0x79, 0x98, 0x8C, 0x0F, 0xB7, 0x9F, 0x37, 0x35, 0xBE, 0x47, 0xE0, 0x4D, 0x15, 0xFB, 0xED,
+	0xFF, 0x00, 0x08, 0x97, 0x85, 0xBF, 0xE8, 0x5C, 0xD3, 0x3F, 0xF0, 0x5E, 0x94, 0x7F, 0xC2, 0x25,
+	0xE1, 0x6F, 0xFA, 0x17, 0x34, 0xCF, 0xFC, 0x17, 0xA5, 0x74, 0x7F, 0x6A, 0x2F, 0xE5, 0xFC, 0x4C,
+	0x7F, 0xB2, 0xDF, 0xF3, 0x7E, 0x07, 0xE0, 0x4D, 0x7E, 0x80, 0x7F, 0xC1, 0x0B, 0x7E, 0xFF, 0x00,
+	0xC5, 0x1F, 0xF7, 0xB4, 0x5F, 0xFD, 0x02, 0xFE, 0xBE, 0xF6, 0xFF, 0x00, 0x84, 0x4B, 0xC2, 0xDF,
+	0xF4, 0x2E, 0x69, 0x9F, 0xF8, 0x2F, 0x4A, 0xB1, 0xA7, 0xE9, 0x1A, 0x4E, 0x97, 0xB9, 0x74, 0xDB,
+	0x0B, 0x7B, 0x7F, 0x33, 0xEF, 0x0B, 0x7B, 0x70, 0x99, 0xFC, 0xAB, 0x1C, 0x46, 0x3D, 0x56, 0xA7,
+	0xC9, 0x6B, 0x1B, 0x50, 0xC0, 0xFB, 0x1A, 0x9C, 0xDC, 0xD7, 0x3E, 0x45, 0xFF, 0x00, 0x82, 0xBA,
+	0xE9, 0xFA, 0x86, 0xA3, 0xE1, 0xFF, 0x00, 0x03, 0xFF, 0x00, 0x67, 0xD9, 0x49, 0x36, 0xDB, 0xEB,
+	0xED, 0xCB, 0x14, 0x7B, 0xCF, 0xDC, 0x8E, 0xBE, 0x1F, 0x3E, 0x1B, 0xF1, 0x26, 0x78, 0xD0, 0x6F,
+	0x7F, 0xF0, 0x16, 0x4F, 0xE9, 0x5F, 0xB4, 0x80, 0xE4, 0x67, 0x14, 0x57, 0x9F, 0xD3, 0x43, 0xD0,
+	0x3F, 0x16, 0x6E, 0x34, 0x1D, 0x76, 0xDA, 0x07, 0x9E, 0xE3, 0x45, 0xBC, 0x8E, 0x35, 0x52, 0x66,
+	0x79, 0x21, 0x95, 0x63, 0x18, 0x4D, 0xFB, 0x8F, 0xFB, 0xAB, 0x5F, 0x94, 0xBF, 0xF0, 0x50, 0xBF,
+	0xDB, 0x16, 0x6F, 0xDA, 0x4F, 0xE2, 0x38, 0xF0, 0x97, 0x83, 0xAF, 0xE7, 0x3E, 0x0B, 0xF0, 0xE5,
+	0xDE, 0xDD, 0x37, 0xCB, 0x62, 0x3F, 0xB4, 0x67, 0xE4, 0x3D, 0xEE, 0x4F, 0x20, 0x92, 0x36, 0x47,
+	0xFD, 0xC8, 0xB7, 0xBF, 0xFC, 0xB5, 0xAF, 0xD7, 0x0F, 0xF8, 0x3A, 0x33, 0xFE, 0x0A, 0xB9, 0x77,
+	0xF0, 0x8B, 0xC1, 0x4D, 0xFF, 0x00, 0x04, 0xEC, 0xF8, 0x15, 0xE2, 0x69, 0x23, 0xF1, 0x27, 0x8A,
+	0xAC, 0x16, 0x7F, 0x89, 0x17, 0xD6, 0x6C, 0x37, 0x69, 0xFA, 0x4B, 0x00, 0xD1, 0xD8, 0xE3, 0xFB,
+	0xF7, 0x3C, 0x19, 0x07, 0xFC, 0xFB, 0xE1, 0x7F, 0xE5, 0xE2, 0xBF, 0x00, 0xFE, 0x5F, 0xE0, 0x27,
+	0x1D, 0xB2, 0xD9, 0xFD, 0x7B, 0xD6, 0x35, 0x25, 0xD0, 0xEC, 0xC3, 0xD2, 0xB7, 0xBC, 0x03, 0x81,
+	0x8D, 0xCA, 0xDF, 0xED, 0x2A, 0xE0, 0x1F, 0xA0, 0xAD, 0xAF, 0x87, 0x3F, 0x0D, 0x7C, 0x7D, 0xF1,
+	0x7F, 0xC7, 0x3A, 0x6F, 0xC3, 0x4F, 0x85, 0xDE, 0x11, 0xD4, 0x35, 0xDF, 0x10, 0x6A, 0xD7, 0x3F,
+	0x67, 0xD2, 0xF4, 0x8D, 0x2A, 0xD9, 0xA7, 0xB8, 0xBD, 0x98, 0x8D, 0xC1, 0x55, 0x23, 0xE4, 0xE1,
+	0x6B, 0x16, 0xBE, 0x9D, 0xFF, 0x00, 0x82, 0x31, 0x7F, 0xCA, 0x53, 0x3E, 0x09, 0xFF, 0x00, 0xD8,
+	0xE7, 0x0F, 0xFE, 0x8A, 0x96, 0xB2, 0xB6, 0xA9, 0x1D, 0x6F, 0xDD, 0x4C, 0xA2, 0xBF, 0xF0, 0x48,
+	0x4F, 0xF8, 0x2A, 0x21, 0x5C, 0x8F, 0xD8, 0x0F, 0xE2, 0xA7, 0xE3, 0xE0, 0xDB, 0x8F, 0xFE, 0x22,
+	0x97, 0xFE, 0x1D, 0x07, 0xFF, 0x00, 0x05, 0x45, 0xFF, 0x00, 0xA3, 0x03, 0xF8, 0xA9, 0xFF, 0x00,
+	0x84, 0x6D, 0xC7, 0xFF, 0x00, 0x11, 0x5F, 0xD5, 0xDF, 0x99, 0x30, 0xE0, 0x4A, 0xD4, 0x79, 0x93,
+	0x7F, 0xCF, 0x57, 0xAE, 0x9F, 0x63, 0x13, 0x8B, 0xEB, 0x75, 0x0F, 0xE5, 0x13, 0xFE, 0x1D, 0x07,
+	0xFF, 0x00, 0x05, 0x45, 0xFF, 0x00, 0xA3, 0x03, 0xF8, 0xA9, 0xFF, 0x00, 0x84, 0x6D, 0xC7, 0xFF,
+	0x00, 0x11, 0x47, 0xFC, 0x3A, 0x0F, 0xFE, 0x0A, 0x8B, 0xFF, 0x00, 0x46, 0x07, 0xF1, 0x53, 0xFF,
+	0x00, 0x08, 0xDB, 0x8F, 0xFE, 0x22, 0xBF, 0xAB, 0xBF, 0x32, 0x6F, 0xF9, 0xEA, 0xF4, 0x79, 0x93,
+	0x7F, 0xCF, 0x57, 0xA3, 0xD8, 0xC4, 0x3E, 0xB9, 0x50, 0xFE, 0x51, 0x3F, 0xE1, 0xD0, 0x7F, 0xF0,
+	0x54, 0x5F, 0xFA, 0x30, 0x3F, 0x8A, 0x9F, 0xF8, 0x46, 0xDC, 0x7F, 0xF1, 0x15, 0xE7, 0x7F, 0x1F,
+	0xFF, 0x00, 0x63, 0x3F, 0xDA, 0xAB, 0xF6, 0x56, 0xB4, 0xD3, 0x6F, 0xFF, 0x00, 0x69, 0x4F, 0xD9,
+	0xEB, 0xC5, 0xDE, 0x09, 0xB7, 0xD7, 0x24, 0x9A, 0x3D, 0x26, 0x6F, 0x12, 0x68, 0xB3, 0x5A, 0x2D,
+	0xDB, 0xC4, 0x80, 0xCA, 0xB1, 0xF9, 0x9C, 0x12, 0x15, 0xE3, 0xCD, 0x7F, 0x5F, 0xFE, 0x64, 0xDF,
+	0xF3, 0xD5, 0xEB, 0xF1, 0xD3, 0xFE, 0x0E, 0xEE, 0x24, 0xFC, 0x3F, 0xF8, 0x12, 0x49, 0xFF, 0x00,
+	0x98, 0xF6, 0xB9, 0xFF, 0x00, 0xA2, 0xAC, 0xAB, 0x39, 0x51, 0x51, 0x8D, 0xCD, 0x29, 0xE2, 0x27,
+	0x52, 0x49, 0x33, 0xF1, 0x01, 0x8B, 0x16, 0x25, 0xBA, 0xE7, 0x9C, 0x52, 0x52, 0x27, 0xDC, 0x1F,
+	0x4A, 0x5A, 0xC4, 0xEA, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0xFD, 0xE0, 0xFF, 0x00, 0x83, 0x36, 0xBF,
+	0xE4, 0x9A, 0x7C, 0x7A, 0xFF, 0x00, 0xB1, 0x83, 0x40, 0xFF, 0x00, 0xD2, 0x7B, 0xFA, 0xFC, 0x1F,
+	0xAF, 0xDC, 0x1F, 0xF8, 0x34, 0x56, 0x4C, 0x7C, 0x35, 0xF8, 0xDE, 0x33, 0xFF, 0x00, 0x31, 0xAD,
+	0x13, 0xFF, 0x00, 0x45, 0x5E, 0x56, 0x94, 0xB5, 0x9D, 0x8E, 0x7C, 0x47, 0xF0, 0xCF, 0xDC, 0xB3,
+	0xD6, 0x8A, 0xF3, 0xEF, 0x32, 0x6E, 0xD2, 0xBD, 0x1E, 0x64, 0xDF, 0xF3, 0xD5, 0xEB, 0xAB, 0x94,
+	0xF3, 0xCF, 0x41, 0xA2, 0xBC, 0xFB, 0xCC, 0x9B, 0xFE, 0x7A, 0xBD, 0x1E, 0x64, 0xDF, 0xF3, 0xD5,
+	0xE8, 0xE5, 0x03, 0xD0, 0x68, 0xC8, 0x1D, 0x4D, 0x79, 0xF7, 0x99, 0x37, 0xFC, 0xF5, 0x7A, 0xFE,
+	0x7C, 0xBF, 0xE0, 0xEC, 0x32, 0x4F, 0xFC, 0x14, 0x3F, 0xC1, 0x64, 0x9F, 0xF9, 0xA2, 0xFA, 0x77,
+	0xFE, 0x9D, 0xF5, 0x6A, 0x89, 0x7B, 0xB1, 0xB9, 0xA5, 0x3A, 0x6A, 0xA4, 0xAC, 0x7F, 0x49, 0xD9,
+	0xCF, 0x4A, 0x47, 0x3C, 0x7E, 0x07, 0xFA, 0x57, 0xF0, 0xE9, 0x45, 0x65, 0xED, 0xB4, 0xB5, 0x8E,
+	0x8F, 0xAA, 0xEB, 0xB9, 0xFA, 0xE1, 0xFF, 0x00, 0x06, 0x7D, 0xFF, 0x00, 0xC9, 0xF0, 0xFC, 0x4E,
+	0xFF, 0x00, 0xB2, 0x52, 0xDF, 0xFA, 0x71, 0xB2, 0xAF, 0xE8, 0x70, 0xF5, 0xAF, 0xE1, 0xCE, 0x8A,
+	0x98, 0xD4, 0xE5, 0x56, 0x34, 0xA9, 0x87, 0xE7, 0x95, 0xEE, 0x7F, 0x71, 0x99, 0xC7, 0x5A, 0x2B,
+	0xF8, 0x73, 0xAF, 0xE9, 0xE3, 0xFE, 0x0D, 0xE1, 0x96, 0x51, 0xFF, 0x00, 0x04, 0x7C, 0xF8, 0x3E,
+	0x04, 0xB2, 0x7D, 0xED, 0x7F, 0xA7, 0xFD, 0x8C, 0x3A, 0x8D, 0x6B, 0x4E, 0x5C, 0xDA, 0x1C, 0xF5,
+	0x28, 0x7B, 0x38, 0xDE, 0xE7, 0xE8, 0xA5, 0x19, 0x15, 0xE7, 0xAB, 0x2C, 0xDB, 0x47, 0xEF, 0x5F,
+	0xA5, 0x2F, 0x99, 0x37, 0xFC, 0xF5, 0x7A, 0xD7, 0x94, 0xE7, 0xD4, 0xF4, 0x1A, 0x2B, 0xCF, 0xBC,
+	0xC9, 0xBF, 0xE7, 0xAB, 0xD1, 0xE6, 0x4D, 0xFF, 0x00, 0x3D, 0x5E, 0x8E, 0x50, 0x3D, 0x06, 0x8C,
+	0xD7, 0x9F, 0x79, 0x93, 0x7F, 0xCF, 0x57, 0xAF, 0xE4, 0x7B, 0xFE, 0x0A, 0x48, 0x49, 0xFF, 0x00,
+	0x82, 0x89, 0xFC, 0x7C, 0x24, 0xFF, 0x00, 0xCD, 0x6A, 0xF1, 0x57, 0xFE, 0x9D, 0xEE, 0xAB, 0x3A,
+	0x92, 0xE4, 0x8D, 0xCD, 0xA9, 0xD3, 0x75, 0x1D, 0xAE, 0x7F, 0x64, 0x59, 0x1E, 0xB4, 0x64, 0x7A,
+	0xD7, 0xF0, 0xE7, 0x45, 0x67, 0xED, 0x7C, 0x8D, 0xBE, 0xAB, 0xD6, 0xE7, 0xF7, 0x19, 0x91, 0xEB,
+	0x46, 0x47, 0xAD, 0x7F, 0x0E, 0x74, 0x51, 0xED, 0x7C, 0x83, 0xEA, 0x9E, 0x67, 0xF7, 0x19, 0x45,
+	0x7F, 0x0E, 0xA3, 0xAF, 0xF9, 0xF4, 0x5A, 0xFE, 0xD2, 0x04, 0x93, 0x01, 0x81, 0x2B, 0x56, 0x94,
+	0xE5, 0xCF, 0xB1, 0x8D, 0x5A, 0x3E, 0xCA, 0xDA, 0x9E, 0x85, 0x45, 0x79, 0xF7, 0x99, 0x37, 0xFC,
+	0xF5, 0x7A, 0x3C, 0xC9, 0xBF, 0xE7, 0xAB, 0xD6, 0x9C, 0xA6, 0x3A, 0x9E, 0x83, 0x45, 0x79, 0xF7,
+	0x99, 0x37, 0xFC, 0xF5, 0x7A, 0x3C, 0xC9, 0xBF, 0xE7, 0xAB, 0xD1, 0xCA, 0x07, 0xE6, 0x5F, 0xFC,
+	0x1E, 0x15, 0xFF, 0x00, 0x26, 0x4F, 0xF0, 0xC7, 0xFE, 0xCA, 0xA0, 0xFF, 0x00, 0xD3, 0x65, 0xDD,
+	0x7F, 0x3D, 0x15, 0xFB, 0xE9, 0xFF, 0x00, 0x07, 0x67, 0xCC, 0x7F, 0xE1, 0x8C, 0x3E, 0x1B, 0xE4,
+	0xFF, 0x00, 0xCD, 0x4F, 0x5F, 0xFD, 0x20, 0xBA, 0xAF, 0xC0, 0xBC, 0xE7, 0x9A, 0xE5, 0xAD, 0xEE,
+	0xCC, 0xF5, 0x30, 0xBF, 0xC1, 0x41, 0x45, 0x14, 0x56, 0x66, 0x81, 0x45, 0x14, 0x50, 0x01, 0x45,
+	0x7A, 0xF7, 0xEC, 0xA1, 0xFB, 0x08, 0xFE, 0xD6, 0x9F, 0xB7, 0x06, 0xA3, 0xAD, 0x69, 0x9F, 0xB2,
+	0x97, 0xC1, 0x7B, 0xDF, 0x18, 0x5C, 0xF8, 0x76, 0xDE, 0xDE, 0x5D, 0x5A, 0x3B, 0x3B, 0xCB, 0x58,
+	0x4D, 0xA2, 0xCC, 0xD2, 0x08, 0x9B, 0x37, 0x0C, 0x83, 0x96, 0x49, 0x3B, 0xD7, 0xB5, 0x7F, 0xC4,
+	0x3F, 0x7F, 0xF0, 0x58, 0x78, 0xC6, 0xC4, 0xFD, 0x88, 0x75, 0xCD, 0xAB, 0xC0, 0x2D, 0xAF, 0x69,
+	0x59, 0xFC, 0x71, 0x73, 0x8A, 0x7C, 0xB2, 0x26, 0x55, 0x23, 0x17, 0x66, 0x7C, 0x6F, 0x45, 0x7D,
+	0x91, 0xFF, 0x00, 0x10, 0xFF, 0x00, 0x7F, 0xC1, 0x62, 0x7F, 0xE8, 0xC8, 0x75, 0xAF, 0xFC, 0x1F,
+	0x69, 0x5F, 0xFC, 0x93, 0x47, 0xFC, 0x43, 0xFD, 0xFF, 0x00, 0x05, 0x89, 0xFF, 0x00, 0xA3, 0x21,
+	0xD6, 0xBF, 0xF0, 0x7D, 0xA5, 0x7F, 0xF2, 0x4D, 0x1C, 0xB2, 0xEC, 0x2F, 0x69, 0x4F, 0xB9, 0xF1,
+	0xBD, 0x15, 0xF6, 0x47, 0xFC, 0x43, 0xFD, 0xFF, 0x00, 0x05, 0x89, 0xFF, 0x00, 0xA3, 0x21, 0xD6,
+	0xBF, 0xF0, 0x7D, 0xA5, 0x7F, 0xF2, 0x4D, 0x1F, 0xF1, 0x0F, 0xF7, 0xFC, 0x16, 0x27, 0xFE, 0x8C,
+	0x87, 0x5A, 0xFF, 0x00, 0xC1, 0xF6, 0x95, 0xFF, 0x00, 0xC9, 0x34, 0x72, 0xCB, 0xB0, 0x7B, 0x4A,
+	0x7D, 0xCF, 0x8D, 0xE8, 0xAE, 0xCB, 0xE3, 0xFF, 0x00, 0xEC, 0xFF, 0x00, 0xF1, 0x8B, 0xF6, 0x5B,
+	0xF8, 0xB7, 0xAC, 0x7C, 0x09, 0xF8, 0xF3, 0xE0, 0x39, 0xBC, 0x3F, 0xE2, 0xED, 0x15, 0x60, 0xFE,
+	0xD7, 0xD0, 0xEE, 0x6E, 0xE0, 0x95, 0xA2, 0x33, 0xC3, 0x14, 0xD1, 0x8F, 0xF4, 0x72, 0x57, 0xE6,
+	0x86, 0x58, 0x9B, 0x92, 0x7E, 0xA6, 0xB8, 0xD2, 0x41, 0x39, 0x0D, 0xBB, 0xFD, 0xA2, 0x07, 0x3E,
+	0xFC, 0x71, 0x4B, 0xAD, 0x8B, 0xE6, 0xEC, 0x7A, 0xB7, 0xEC, 0x7D, 0xFB, 0x4E, 0x6B, 0x9F, 0xB2,
+	0xEF, 0xC5, 0xBB, 0x7F, 0x18, 0x45, 0x1C, 0xD7, 0x5A, 0x1D, 0xE2, 0x8B, 0x6F, 0x12, 0x69, 0xB1,
+	0x75, 0xBA, 0xB5, 0x2D, 0x8F, 0x31, 0x3F, 0xE9, 0xBC, 0x67, 0xFD, 0x5F, 0x6C, 0x86, 0x1D, 0x1E,
+	0x4A, 0xFD, 0x82, 0xF0, 0x85, 0xCF, 0xFC, 0x2C, 0x5F, 0x0D, 0xE9, 0xDE, 0x34, 0xF0, 0x82, 0xDC,
+	0x6A, 0x7A, 0x66, 0xAD, 0x6C, 0xB7, 0x1A, 0x6D, 0xF5, 0x9D, 0xBC, 0x86, 0x39, 0x91, 0xD4, 0x38,
+	0x6C, 0xF7, 0xC8, 0x39, 0xFC, 0x6B, 0xF0, 0x9E, 0xBF, 0x5E, 0x3F, 0xE0, 0xD8, 0x3F, 0xF8, 0x2A,
+	0xDC, 0xBF, 0x05, 0xFE, 0x24, 0xC7, 0xFF, 0x00, 0x04, 0xF0, 0xF8, 0xD9, 0xAE, 0xEC, 0xF0, 0xBF,
+	0x8C, 0x35, 0x27, 0x9B, 0xE1, 0xEE, 0xA1, 0x74, 0xDF, 0x2E, 0x95, 0xAD, 0x49, 0xF7, 0xAC, 0x80,
+	0xFF, 0x00, 0x9E, 0x57, 0x43, 0x94, 0x1F, 0xF3, 0xF3, 0xF2, 0xFF, 0x00, 0xCB, 0xC5, 0x69, 0x09,
+	0x72, 0xCA, 0xCD, 0x9C, 0xD8, 0x8A, 0x5C, 0xD1, 0xBA, 0x3D, 0xB8, 0x78, 0x6F, 0xC4, 0x58, 0xF9,
+	0x34, 0x0B, 0xC5, 0x5F, 0xE1, 0x55, 0xB5, 0x97, 0x02, 0xBE, 0xE0, 0xFF, 0x00, 0x82, 0x45, 0xE9,
+	0xDA, 0x86, 0x9B, 0xE1, 0xFF, 0x00, 0x1B, 0xAE, 0xA5, 0x61, 0x25, 0xBB, 0x35, 0xF5, 0x89, 0x55,
+	0x9A, 0x12, 0xA5, 0xBF, 0x75, 0x37, 0x3C, 0xD7, 0xD8, 0x91, 0xFF, 0x00, 0xAB, 0x5C, 0x1F, 0xE1,
+	0xFE, 0xF6, 0x7F, 0x5A, 0x75, 0x74, 0x1C, 0x07, 0xE7, 0xCF, 0xFC, 0x17, 0x5B, 0x3B, 0xFE, 0x16,
+	0xE4, 0x7F, 0x0E, 0xB7, 0xFC, 0xF4, 0xFA, 0xFC, 0xFD, 0xAF, 0xDF, 0xCB, 0xFD, 0x23, 0x4A, 0xD5,
+	0x0E, 0x75, 0x3D, 0x32, 0x1B, 0x8F, 0x2F, 0xEE, 0x9B, 0x8B, 0x74, 0x70, 0x33, 0xF5, 0xA8, 0x47,
+	0x84, 0x3C, 0x2C, 0xA3, 0x6F, 0xFC, 0x23, 0x9A, 0x5F, 0x1C, 0x7F, 0xC8, 0x3D, 0x2B, 0xD0, 0xC3,
+	0xE3, 0xD5, 0x0A, 0x7C, 0x96, 0xBF, 0xCC, 0xF3, 0xEB, 0x60, 0x7D, 0xB5, 0x5E, 0x7E, 0x6F, 0xC0,
+	0xFC, 0x09, 0xA2, 0xBF, 0x7D, 0xBF, 0xE1, 0x12, 0xF0, 0xB7, 0xFD, 0x0B, 0x9A, 0x67, 0xFE, 0x0B,
+	0xD2, 0x8F, 0xF8, 0x44, 0xBC, 0x2D, 0xFF, 0x00, 0x42, 0xE6, 0x99, 0xFF, 0x00, 0x82, 0xF4, 0xAD,
+	0xBF, 0xB5, 0x17, 0xF2, 0xFE, 0x26, 0x3F, 0xD9, 0x72, 0xFE, 0x6F, 0xC0, 0xFC, 0x09, 0xAF, 0xD5,
+	0xBF, 0xF8, 0x23, 0xC7, 0xFC, 0x99, 0xCA, 0x7F, 0xD8, 0xCB, 0xA8, 0x7F, 0xED, 0x2A, 0xFA, 0x6F,
+	0xFE, 0x11, 0x2F, 0x0B, 0x7F, 0xD0, 0xB9, 0xA6, 0x7F, 0xE0, 0xBD, 0x2A, 0xDD, 0xA6, 0x9F, 0x63,
+	0x61, 0x07, 0xD9, 0x6C, 0xED, 0xA1, 0x86, 0x2D, 0xDB, 0x84, 0x70, 0xAE, 0xD1, 0x9F, 0xA7, 0x6A,
+	0xE7, 0xC5, 0x63, 0x96, 0x22, 0x9F, 0x2D, 0xAC, 0x6F, 0x87, 0xC0, 0xFD, 0x5E, 0xA7, 0x37, 0x35,
+	0xFE, 0x47, 0xC6, 0x1F, 0xB6, 0x7F, 0xFC, 0x97, 0xDD, 0x47, 0xFE, 0xBD, 0xAD, 0x3F, 0xF4, 0x0A,
+	0xF2, 0x91, 0xD2, 0xBF, 0x47, 0xEE, 0xB4, 0xFD, 0x36, 0xE2, 0x4F, 0x32, 0xEA, 0xD2, 0x16, 0x6E,
+	0xBF, 0xBC, 0x8E, 0x90, 0x69, 0x1A, 0x11, 0x1F, 0x36, 0x9D, 0x6B, 0x9F, 0xFA, 0xE6, 0xB5, 0xFC,
+	0x7B, 0xC5, 0xDF, 0x47, 0x29, 0x71, 0x1F, 0x12, 0x62, 0xB3, 0x3F, 0xED, 0x38, 0xC3, 0xDB, 0x4D,
+	0xCF, 0x97, 0x92, 0xED, 0x5E, 0xDA, 0x5F, 0x99, 0x7E, 0x47, 0xEB, 0x39, 0x5F, 0x1F, 0x2C, 0xBF,
+	0x2F, 0xA7, 0x86, 0xFA, 0xBF, 0x37, 0x22, 0x4A, 0xFC, 0xDB, 0xDB, 0xCA, 0xC7, 0xE7, 0x0D, 0x15,
+	0xFA, 0x3D, 0xFD, 0x91, 0xA2, 0x76, 0xD3, 0x6D, 0x7F, 0xEF, 0xDA, 0xD1, 0xFD, 0x91, 0xA2, 0xFF,
+	0x00, 0xD0, 0x36, 0xD7, 0xFE, 0xFD, 0xAD, 0x7C, 0xEF, 0xFC, 0x4A, 0xAC, 0xBF, 0xE8, 0x6D, 0x1F,
+	0xFC, 0x17, 0xFF, 0x00, 0xDB, 0x9E, 0x87, 0xFC, 0x44, 0xA8, 0xFF, 0x00, 0xD0, 0x37, 0xFE, 0x4D,
+	0xFF, 0x00, 0x00, 0xFC, 0xE1, 0xAF, 0xD0, 0x4F, 0x82, 0x5F, 0xF2, 0x46, 0xFC, 0x27, 0xFF, 0x00,
+	0x62, 0xDD, 0x97, 0xFE, 0x88, 0x4A, 0xDA, 0x6D, 0x23, 0x42, 0xEA, 0x74, 0xEB, 0x5F, 0xFB, 0xF6,
+	0xB5, 0x72, 0x34, 0x8D, 0x23, 0x58, 0xE2, 0x45, 0x55, 0x55, 0xC2, 0xAA, 0xF4, 0x02, 0xBF, 0x5E,
+	0xF0, 0x87, 0xC2, 0x1F, 0xF8, 0x86, 0xB9, 0x86, 0x27, 0x13, 0xF5, 0xC5, 0x5F, 0xDA, 0xC2, 0x31,
+	0xB2, 0x8F, 0x2D, 0xAC, 0xEF, 0x7B, 0xF3, 0x3B, 0x9F, 0x2B, 0xC5, 0x1C, 0x54, 0xB8, 0x82, 0x85,
+	0x2A, 0x7E, 0xCB, 0x93, 0x95, 0xB7, 0xBD, 0xEF, 0x7F, 0x92, 0x3F, 0x2B, 0x7F, 0x6C, 0xDD, 0x07,
+	0x59, 0xBB, 0xFD, 0xA9, 0xFC, 0x6D, 0x25, 0xB6, 0x8B, 0x78, 0xCA, 0xDA, 0xF1, 0x2A, 0xCB, 0x6F,
+	0x21, 0x0D, 0xF2, 0xA7, 0x20, 0x8A, 0xF2, 0xE1, 0xE1, 0xAF, 0x12, 0xA8, 0xDA, 0x74, 0x1B, 0xDF,
+	0xFC, 0x05, 0x96, 0xBF, 0x69, 0x68, 0xAF, 0xDE, 0x0F, 0x8F, 0x3F, 0x16, 0xBF, 0xE1, 0x1B, 0xF1,
+	0x27, 0xFD, 0x00, 0xAF, 0x7F, 0xF0, 0x16, 0x5A, 0x3F, 0xE1, 0x1B, 0xF1, 0x27, 0xFD, 0x00, 0xAF,
+	0x7F, 0xF0, 0x16, 0x5A, 0xFD, 0xA5, 0xA2, 0x80, 0x3F, 0x16, 0xBF, 0xE1, 0x1B, 0xF1, 0x27, 0xFD,
+	0x00, 0xAF, 0x7F, 0xF0, 0x16, 0x5A, 0xFB, 0xBF, 0xFE, 0x09, 0x1F, 0xA7, 0xDF, 0x69, 0xFF, 0x00,
+	0x0D, 0xFC, 0x60, 0x97, 0xD6, 0x32, 0x5B, 0xB3, 0x6B, 0x90, 0x10, 0xB2, 0x21, 0x5C, 0xFE, 0xE0,
+	0x73, 0xCD, 0x7D, 0x6D, 0x54, 0x60, 0x38, 0xF1, 0x15, 0xF1, 0xC7, 0xFC, 0xB8, 0x5B, 0x7F, 0xE8,
+	0x53, 0x50, 0x07, 0xE7, 0xCF, 0xFC, 0x15, 0x2B, 0x48, 0xD5, 0x6F, 0xFF, 0x00, 0x69, 0x88, 0x65,
+	0xB0, 0xD3, 0x27, 0xB8, 0x55, 0xF0, 0xC5, 0xAE, 0x5E, 0x3B, 0x62, 0xD8, 0xFD, 0xE4, 0xDD, 0xC7,
+	0x35, 0xF3, 0x77, 0xFC, 0x23, 0x7E, 0x24, 0xFF, 0x00, 0xA0, 0x15, 0xEF, 0xFE, 0x02, 0xCB, 0x5F,
+	0xB3, 0x5A, 0x77, 0xFC, 0x7F, 0x6A, 0x1F, 0xF5, 0xF8, 0xBF, 0xFA, 0x26, 0x3A, 0xB7, 0x40, 0x1F,
+	0x8B, 0x5F, 0xF0, 0x8D, 0xF8, 0x93, 0xFE, 0x80, 0x57, 0xBF, 0xF8, 0x0B, 0x2D, 0x1F, 0xF0, 0x8D,
+	0xF8, 0x93, 0xFE, 0x80, 0x57, 0xBF, 0xF8, 0x0B, 0x2D, 0x7E, 0xD2, 0xD1, 0x40, 0x1F, 0x8B, 0x63,
+	0xC3, 0x5E, 0x24, 0x39, 0x07, 0x40, 0xBE, 0x3F, 0x29, 0xE0, 0x5B, 0xC8, 0x3B, 0x7B, 0xF1, 0x5F,
+	0x71, 0x7F, 0xC1, 0x23, 0x34, 0xFB, 0xFD, 0x3F, 0xC3, 0xFE, 0x3C, 0x8A, 0xFE, 0xC2, 0x4B, 0x76,
+	0xFB, 0x75, 0x81, 0x0B, 0x22, 0xE0, 0x9F, 0xDD, 0xCD, 0x5F, 0x61, 0x50, 0x4E, 0x23, 0x63, 0x8E,
+	0xD4, 0x01, 0xF9, 0xD7, 0xFF, 0x00, 0x05, 0x4A, 0xD2, 0x35, 0x5B, 0xFF, 0x00, 0xDA, 0x62, 0x19,
+	0x6C, 0x34, 0xC9, 0xEE, 0x15, 0x7C, 0x31, 0x6B, 0x97, 0x8E, 0xD8, 0xB6, 0x3F, 0x79, 0x37, 0x71,
+	0xCD, 0x7C, 0xDD, 0xFF, 0x00, 0x08, 0xDF, 0x89, 0x3F, 0xE8, 0x05, 0x7B, 0xFF, 0x00, 0x80, 0xB2,
+	0xD7, 0xEC, 0xD6, 0x9D, 0xFF, 0x00, 0x1F, 0xDA, 0x87, 0xFD, 0x7E, 0x2F, 0xFE, 0x89, 0x8E, 0xAD,
+	0xD0, 0x07, 0xE2, 0xD7, 0xFC, 0x23, 0x7E, 0x24, 0xFF, 0x00, 0xA0, 0x15, 0xEF, 0xFE, 0x02, 0xCB,
+	0x47, 0xFC, 0x23, 0x7E, 0x24, 0xFF, 0x00, 0xA0, 0x15, 0xEF, 0xFE, 0x02, 0xCB, 0x5F, 0xB4, 0xB4,
+	0x50, 0x07, 0xE2, 0xD8, 0xF0, 0xD7, 0x89, 0x0E, 0x41, 0xD0, 0x2F, 0x8F, 0xCA, 0x78, 0x16, 0xF2,
+	0x0E, 0xDE, 0xFC, 0x57, 0xDC, 0x1F, 0xF0, 0x49, 0x0B, 0x0D, 0x43, 0x4E, 0xD0, 0x3C, 0x77, 0x15,
+	0xFD, 0x84, 0x96, 0xEC, 0xD7, 0xF6, 0x38, 0x59, 0x13, 0x04, 0xFE, 0xEE, 0x6A, 0xFB, 0x12, 0x8A,
+	0x00, 0x20, 0xFE, 0x2F, 0xF7, 0x87, 0xFE, 0x82, 0x2A, 0x4A, 0x6A, 0x11, 0xC8, 0x07, 0xA1, 0xE7,
+	0x8A, 0x75, 0x00, 0x14, 0x37, 0xDD, 0xA2, 0x86, 0xE9, 0xD6, 0x80, 0x3E, 0x21, 0xFF, 0x00, 0x82,
+	0xB2, 0x78, 0x9B, 0xC4, 0x7E, 0x1B, 0xF1, 0x17, 0x82, 0x53, 0xC3, 0xFE, 0x20, 0xD4, 0x2C, 0x4C,
+	0xD6, 0x37, 0xBB, 0xDA, 0xCA, 0xF1, 0xE3, 0xDC, 0x03, 0xC3, 0xD4, 0x03, 0xFD, 0x6B, 0xE4, 0x5F,
+	0xF8, 0x59, 0x5F, 0x11, 0x7F, 0xE8, 0xA0, 0x6B, 0x9F, 0xF8, 0x34, 0x97, 0xFF, 0x00, 0x8B, 0xAF,
+	0xAB, 0x7F, 0xE0, 0xAF, 0xBC, 0x78, 0x8F, 0xC0, 0xC3, 0xFE, 0x9C, 0xAF, 0xBF, 0xF4, 0x38, 0xEB,
+	0xE3, 0x6A, 0x00, 0xDC, 0xFF, 0x00, 0x85, 0x95, 0xF1, 0x17, 0xFE, 0x8A, 0x06, 0xB9, 0xFF, 0x00,
+	0x83, 0x49, 0x7F, 0xF8, 0xBA, 0x3F, 0xE1, 0x65, 0x7C, 0x45, 0xFF, 0x00, 0xA2, 0x81, 0xAE, 0x7F,
+	0xE0, 0xD2, 0x5F, 0xFE, 0x2E, 0xB0, 0xE8, 0xA0, 0x0D, 0xCF, 0xF8, 0x59, 0x5F, 0x11, 0xBF, 0xE8,
+	0x7F, 0xD7, 0x0F, 0xB1, 0xD5, 0x25, 0xE7, 0xFF, 0x00, 0x1F, 0xAF, 0xA8, 0x7F, 0xE0, 0x95, 0x3E,
+	0x2C, 0xF1, 0x3F, 0x88, 0x7E, 0x30, 0x78, 0x82, 0xD7, 0x5F, 0xF1, 0x56, 0xA5, 0x7C, 0x23, 0xF0,
+	0xE9, 0x68, 0xE3, 0xBE, 0xBC, 0x79, 0x15, 0x0F, 0x9F, 0x17, 0x23, 0x35, 0xF2, 0x10, 0xEB, 0x5F,
+	0x58, 0x7F, 0xC1, 0x23, 0xFF, 0x00, 0xE4, 0xB5, 0x78, 0x97, 0xFE, 0xC5, 0x55, 0xFF, 0x00, 0xD2,
+	0x98, 0xA8, 0x03, 0xD9, 0xBF, 0xE0, 0xAA, 0x7A, 0xEE, 0xB1, 0xE1, 0xEF, 0xD9, 0xFF, 0x00, 0x45,
+	0xBC, 0xD0, 0xB5, 0x7B, 0xCB, 0x2B, 0x86, 0xF1, 0x84, 0x0B, 0xE7, 0xD9, 0xCE, 0x63, 0x6E, 0x6D,
+	0x2E, 0xBB, 0x8A, 0xF8, 0x17, 0xFE, 0x16, 0x57, 0xC4, 0x5F, 0xFA, 0x28, 0x1A, 0xE7, 0xFE, 0x0D,
+	0x25, 0xFF, 0x00, 0xE2, 0xEB, 0xEF, 0x1F, 0xF8, 0x2B, 0x2F, 0xFC, 0x9B, 0x8E, 0x8F, 0xFF, 0x00,
+	0x63, 0x9D, 0xAF, 0xFE, 0x92, 0xDE, 0xD7, 0xE7, 0x95, 0x00, 0x6E, 0x7F, 0xC2, 0xCA, 0xF8, 0x8B,
+	0xFF, 0x00, 0x45, 0x03, 0x5C, 0xFF, 0x00, 0xC1, 0xA4, 0xBF, 0xFC, 0x5D, 0x1F, 0xF0, 0xB2, 0xBE,
+	0x22, 0xFF, 0x00, 0xD1, 0x40, 0xD7, 0x3F, 0xF0, 0x69, 0x2F, 0xFF, 0x00, 0x17, 0x58, 0x74, 0x50,
+	0x06, 0xE7, 0xFC, 0x2C, 0xAF, 0x88, 0xBF, 0xF4, 0x50, 0x35, 0xCF, 0xFC, 0x1A, 0x4B, 0xFF, 0x00,
+	0xC5, 0xD7, 0xB7, 0x7F, 0xC1, 0x3B, 0x3C, 0x6B, 0xE3, 0x0D, 0x6F, 0xF6, 0xA8, 0xD1, 0x74, 0xDD,
+	0x73, 0xC5, 0xFA, 0xAD, 0xDC, 0x2F, 0x6B, 0x79, 0xFE, 0x8B, 0x75, 0xA8, 0x3B, 0xC7, 0xFF, 0x00,
+	0x1E, 0xEF, 0x5F, 0x3A, 0xD7, 0xBD, 0x7F, 0xC1, 0x36, 0x3F, 0xE4, 0xEE, 0x74, 0x1F, 0xFB, 0x07,
+	0xEA, 0x1F, 0xFA, 0x4E, 0xF4, 0x01, 0xF6, 0x77, 0xFC, 0x14, 0x13, 0x54, 0xBF, 0xD1, 0x7F, 0x64,
+	0x7F, 0x15, 0x6A, 0x5A, 0x6D, 0xFC, 0xF6, 0xF7, 0x11, 0xB5, 0x86, 0xCB, 0x8B, 0x69, 0x0A, 0x32,
+	0x9F, 0xB7, 0x40, 0x38, 0x23, 0xA5, 0x7E, 0x69, 0x0F, 0x89, 0x5F, 0x11, 0xC8, 0xCB, 0x7C, 0x42,
+	0xD7, 0x89, 0xEE, 0x5B, 0x54, 0x97, 0x27, 0xFF, 0x00, 0x1F, 0xAF, 0xD2, 0x8F, 0xF8, 0x28, 0x8F,
+	0xFC, 0x99, 0xDF, 0x8C, 0x7F, 0xDC, 0xB2, 0xFF, 0x00, 0xD3, 0x85, 0xAD, 0x7E, 0x5E, 0x50, 0x06,
+	0xE7, 0xFC, 0x2C, 0xAF, 0x88, 0xBF, 0xF4, 0x50, 0x35, 0xCF, 0xFC, 0x1A, 0x4B, 0xFF, 0x00, 0xC5,
+	0xD1, 0xFF, 0x00, 0x0B, 0x2B, 0xE2, 0x2F, 0xFD, 0x14, 0x0D, 0x73, 0xFF, 0x00, 0x06, 0x92, 0xFF,
+	0x00, 0xF1, 0x75, 0x87, 0x45, 0x00, 0x6E, 0x7F, 0xC2, 0xCA, 0xF8, 0x8B, 0xFF, 0x00, 0x45, 0x03,
+	0x5C, 0xFF, 0x00, 0xC1, 0xA4, 0xBF, 0xFC, 0x5D, 0x77, 0x9F, 0xB2, 0xC7, 0xC4, 0x0F, 0x1C, 0xDF,
+	0xFE, 0xD1, 0xDE, 0x0B, 0xB1, 0xD4, 0xFC, 0x71, 0xAC, 0x4D, 0x04, 0xBE, 0x23, 0xB5, 0x56, 0xB7,
+	0x97, 0x51, 0x76, 0x8D, 0xFF, 0x00, 0x78, 0x3A, 0x8A, 0xF2, 0x7A, 0xF4, 0x4F, 0xD9, 0x2B, 0xFE,
+	0x4E, 0x73, 0xC0, 0x3F, 0xF6, 0x35, 0x5A, 0x7F, 0xE8, 0x42, 0x80, 0x3F, 0x4C, 0x3F, 0x6A, 0x16,
+	0x78, 0x3F, 0x66, 0x7F, 0x88, 0x4E, 0x92, 0x32, 0xB2, 0xF8, 0x1F, 0x55, 0xDA, 0xC9, 0xFC, 0x3F,
+	0xE8, 0x92, 0x57, 0xE3, 0x38, 0xD5, 0x75, 0x46, 0x1B, 0x8E, 0xA7, 0x70, 0x7F, 0xED, 0xA5, 0x7E,
+	0xCB, 0x7E, 0xD4, 0xDF, 0xF2, 0x6C, 0x9F, 0x11, 0x7F, 0xEC, 0x45, 0xD5, 0xFF, 0x00, 0xF4, 0x82,
+	0x7A, 0xFC, 0x61, 0xAE, 0x7A, 0xCD, 0xE9, 0x63, 0x48, 0x16, 0x3F, 0xB4, 0xF5, 0x4F, 0xFA, 0x09,
+	0x4F, 0xFF, 0x00, 0x7F, 0x68, 0xFE, 0xD3, 0xD5, 0x3F, 0xE8, 0x25, 0x3F, 0xFD, 0xFD, 0xAA, 0xF4,
+	0x57, 0x39, 0xA1, 0x63, 0xFB, 0x4F, 0x54, 0xFF, 0x00, 0xA0, 0x94, 0xFF, 0x00, 0xF7, 0xF6, 0xBE,
+	0x8A, 0xFF, 0x00, 0x82, 0x5A, 0x6A, 0x57, 0xF2, 0xFE, 0xD7, 0xDA, 0x5C, 0x17, 0x37, 0xB3, 0xBC,
+	0x67, 0x47, 0xBE, 0xFF, 0x00, 0x59, 0x27, 0x1F, 0xEA, 0x5A, 0xBE, 0x6D, 0xAF, 0xA3, 0x3F, 0xE0,
+	0x95, 0x5F, 0xF2, 0x78, 0xBA, 0x57, 0xFD, 0x81, 0xEF, 0xFF, 0x00, 0xF4, 0x43, 0x55, 0x43, 0x59,
+	0xA2, 0x65, 0xF0, 0x9F, 0x6D, 0x7F, 0xC1, 0x45, 0xF5, 0x6D, 0x57, 0x44, 0xFD, 0x94, 0xF5, 0xED,
+	0x4B, 0x46, 0xD4, 0x26, 0xB5, 0xB8, 0x8E, 0xEA, 0xC8, 0x79, 0xD6, 0xD7, 0x0C, 0x8C, 0x14, 0xDC,
+	0xA7, 0xF7, 0x6B, 0xF3, 0x84, 0x7C, 0x48, 0xF8, 0x8A, 0x9F, 0x27, 0xFC, 0x2C, 0x2D, 0x74, 0xE3,
+	0x8C, 0xFF, 0x00, 0x6A, 0x4B, 0xFF, 0x00, 0xC5, 0xD7, 0xE8, 0xCF, 0xFC, 0x14, 0xAB, 0xFE, 0x4D,
+	0x2B, 0x5E, 0xFF, 0x00, 0xAF, 0xDB, 0x1F, 0xFD, 0x28, 0x5A, 0xFC, 0xCA, 0xAE, 0xED, 0x0C, 0x4D,
+	0xCF, 0xF8, 0x59, 0x5F, 0x11, 0x7F, 0xE8, 0xA0, 0x6B, 0x9F, 0xF8, 0x34, 0x97, 0xFF, 0x00, 0x8B,
+	0xA3, 0xFE, 0x16, 0x57, 0xC4, 0x5F, 0xFA, 0x28, 0x1A, 0xE7, 0xFE, 0x0D, 0x25, 0xFF, 0x00, 0xE2,
+	0xEB, 0x0E, 0x8A, 0x34, 0x0F, 0x78, 0xDC, 0xFF, 0x00, 0x85, 0x95, 0xF1, 0x17, 0xFE, 0x8A, 0x06,
+	0xB9, 0xFF, 0x00, 0x83, 0x49, 0x7F, 0xF8, 0xBA, 0xFB, 0x53, 0xFE, 0x09, 0x35, 0xE2, 0x3D, 0x7F,
+	0xC4, 0x3A, 0x17, 0x8D, 0xA5, 0xF1, 0x0E, 0xBF, 0x79, 0x7F, 0x24, 0x17, 0xD6, 0x22, 0x26, 0xBC,
+	0xB8, 0x2E, 0x54, 0x18, 0xE6, 0xE0, 0x66, 0xBE, 0x0F, 0xAF, 0xB8, 0xFF, 0x00, 0xE0, 0x90, 0x7F,
+	0xF2, 0x2D, 0xF8, 0xEB, 0xFE, 0xBF, 0xEC, 0x7F, 0xF4, 0x55, 0xC5, 0x1A, 0x01, 0x7B, 0xFE, 0x0A,
+	0xC7, 0xE2, 0x1D, 0x7F, 0xC3, 0xBA, 0x07, 0x82, 0x5F, 0xC3, 0x9A, 0xE5, 0xF5, 0x8C, 0x93, 0x5E,
+	0x5F, 0x2B, 0xFD, 0x8E, 0xE1, 0xA3, 0x66, 0x51, 0x1C, 0x7F, 0xDD, 0xAF, 0xCE, 0x8F, 0xDA, 0x63,
+	0xF6, 0xC8, 0xF1, 0x27, 0xEC, 0xD9, 0xF0, 0x77, 0x54, 0xF8, 0xA1, 0xAE, 0xFC, 0x40, 0xD6, 0x24,
+	0x92, 0x0F, 0xDC, 0x69, 0x5A, 0x7C, 0xDA, 0xA4, 0xBF, 0xE9, 0x97, 0xAE, 0xBF, 0xBB, 0x89, 0xBE,
+	0x7E, 0x98, 0xF9, 0xDF, 0xFE, 0x99, 0x6E, 0xAF, 0xD0, 0xAF, 0xF8, 0x2B, 0xE4, 0x8B, 0x1F, 0x87,
+	0xBC, 0x0F, 0x23, 0x91, 0x85, 0xBD, 0xD4, 0x18, 0xE6, 0x4D, 0xAB, 0xB4, 0x2D, 0xB6, 0x49, 0xFA,
+	0x57, 0xF3, 0x9D, 0xFF, 0x00, 0x05, 0x2B, 0xFD, 0xA7, 0xA4, 0xF8, 0xE7, 0xF1, 0xA1, 0xBC, 0x0F,
+	0xE1, 0xBD, 0x47, 0xCD, 0xF0, 0xE7, 0x84, 0x64, 0x92, 0xC6, 0xC7, 0x73, 0x6E, 0x4B, 0xCB, 0xC2,
+	0xC7, 0xCF, 0xB8, 0x3E, 0xA0, 0x30, 0x31, 0xAF, 0xB0, 0xC7, 0xF1, 0xD4, 0x4E, 0x4E, 0x31, 0x36,
+	0xA1, 0x4F, 0xDA, 0x54, 0xD4, 0xF0, 0x8F, 0x88, 0x1F, 0x10, 0x3C, 0x5B, 0xF1, 0x37, 0xC7, 0x1A,
+	0x9F, 0xC4, 0x6F, 0x88, 0x1A, 0xCD, 0xF6, 0xAF, 0xAD, 0x6A, 0xFA, 0x83, 0x5F, 0x6A, 0x97, 0x97,
+	0xD7, 0x05, 0xE6, 0x9D, 0x89, 0x39, 0xEB, 0xD8, 0x12, 0x6B, 0x1C, 0x2E, 0xC1, 0xB3, 0x7E, 0xEC,
+	0x71, 0xB8, 0x77, 0xF7, 0xA3, 0x2B, 0xFC, 0x39, 0xC7, 0x6D, 0xDD, 0x68, 0xAE, 0x6D, 0xF5, 0x3D,
+	0x2D, 0xB4, 0x0A, 0xFA, 0x77, 0xFE, 0x08, 0xC5, 0xFF, 0x00, 0x29, 0x4C, 0xF8, 0x27, 0xFF, 0x00,
+	0x63, 0x9C, 0x3F, 0xFA, 0x2A, 0x5A, 0xF9, 0x8A, 0xBE, 0x9D, 0xFF, 0x00, 0x82, 0x31, 0x7F, 0xCA,
+	0x53, 0x3E, 0x09, 0xFF, 0x00, 0xD8, 0xE7, 0x0F, 0xFE, 0x8A, 0x96, 0xAB, 0xED, 0x44, 0x99, 0x7C,
+	0x2C, 0xFE, 0xAA, 0xCF, 0x5A, 0x28, 0x3D, 0x68, 0xAE, 0xE3, 0xC9, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0xFC, 0x76, 0xFF, 0x00, 0x83, 0xBB, 0x7F, 0xE4, 0x9F, 0x7C, 0x09, 0xFF, 0x00, 0xB0, 0xEE, 0xB9,
+	0xFF, 0x00, 0xA2, 0xAC, 0xAB, 0xF6, 0x26, 0xBF, 0x1D, 0xBF, 0xE0, 0xEE, 0xDF, 0xF9, 0x27, 0xDF,
+	0x02, 0x7F, 0xEC, 0x3B, 0xAE, 0x7F, 0xE8, 0xAB, 0x2A, 0xCE, 0xA7, 0xF0, 0xCD, 0xA8, 0x7F, 0x11,
+	0x1F, 0x87, 0xE9, 0xF7, 0x07, 0xD2, 0x96, 0x91, 0x3E, 0xE0, 0xFA, 0x52, 0xD7, 0x19, 0xE9, 0x05,
+	0x14, 0x51, 0x40, 0x05, 0x7E, 0xE0, 0xFF, 0x00, 0xC1, 0xA2, 0x9F, 0xF2, 0x4D, 0x7E, 0x37, 0x7F,
+	0xD8, 0x6F, 0x45, 0xFF, 0x00, 0xD1, 0x37, 0x95, 0xF8, 0x7D, 0x5F, 0xB8, 0x3F, 0xF0, 0x68, 0xA7,
+	0xFC, 0x93, 0x5F, 0x8D, 0xDF, 0xF6, 0x1B, 0xD1, 0x7F, 0xF4, 0x4D, 0xE5, 0x69, 0x47, 0xF8, 0x87,
+	0x3E, 0x23, 0xF8, 0x67, 0xEC, 0x3D, 0x14, 0x51, 0x5D, 0x87, 0x9E, 0x14, 0x51, 0x45, 0x00, 0x15,
+	0xFC, 0xF8, 0xFF, 0x00, 0xC1, 0xD8, 0x3F, 0xF2, 0x91, 0x0F, 0x06, 0x7F, 0xD9, 0x17, 0xD3, 0xBF,
+	0xF4, 0xEF, 0xAB, 0x57, 0xF4, 0x1D, 0x5F, 0xCF, 0x8F, 0xFC, 0x1D, 0x83, 0xFF, 0x00, 0x29, 0x10,
+	0xF0, 0x67, 0xFD, 0x91, 0x7D, 0x3B, 0xFF, 0x00, 0x4E, 0xFA, 0xB5, 0x63, 0x57, 0xE0, 0x47, 0x46,
+	0x1B, 0xF8, 0x87, 0xE6, 0x2D, 0x14, 0x51, 0x5C, 0xA7, 0xA0, 0x14, 0x51, 0x45, 0x00, 0x15, 0xFD,
+	0x3A, 0xFF, 0x00, 0xC1, 0xBC, 0xBF, 0xF2, 0x87, 0xFF, 0x00, 0x84, 0x1F, 0x5D, 0x7B, 0xFF, 0x00,
+	0x52, 0x1D, 0x46, 0xBF, 0x98, 0xAA, 0xFE, 0x9D, 0x7F, 0xE0, 0xDE, 0x5F, 0xF9, 0x43, 0xFF, 0x00,
+	0xC2, 0x0F, 0xAE, 0xBD, 0xFF, 0x00, 0xA9, 0x0E, 0xA3, 0x5B, 0x51, 0xF8, 0x8E, 0x6C, 0x4F, 0xF0,
+	0xD1, 0xF6, 0x98, 0xE9, 0x45, 0x03, 0xA5, 0x15, 0xD4, 0x70, 0x05, 0x14, 0x51, 0x40, 0x05, 0x7F,
+	0x24, 0x1F, 0xF0, 0x52, 0x3F, 0xF9, 0x48, 0x97, 0xC7, 0xCF, 0xFB, 0x2D, 0x3E, 0x29, 0xFF, 0x00,
+	0xD3, 0xBD, 0xD5, 0x7F, 0x5B, 0xF5, 0xFC, 0x90, 0x7F, 0xC1, 0x48, 0xFF, 0x00, 0xE5, 0x22, 0x5F,
+	0x1F, 0x3F, 0xEC, 0xB4, 0xF8, 0xA7, 0xFF, 0x00, 0x4E, 0xF7, 0x55, 0xCF, 0x5F, 0xE1, 0x47, 0x66,
+	0x17, 0xE2, 0x67, 0x8B, 0x51, 0x45, 0x15, 0xCE, 0x76, 0x05, 0x14, 0x51, 0x40, 0x0D, 0x3F, 0x7F,
+	0xF1, 0xFE, 0x82, 0xBF, 0xB4, 0xA3, 0xD6, 0xBF, 0x8B, 0x53, 0xF7, 0xFF, 0x00, 0x1F, 0xE8, 0x2B,
+	0xFB, 0x4A, 0x3D, 0x6B, 0xA3, 0x0E, 0x71, 0xE2, 0xBA, 0x05, 0x14, 0x51, 0x5D, 0x07, 0x18, 0x51,
+	0x45, 0x14, 0x01, 0xF9, 0x57, 0xFF, 0x00, 0x07, 0x68, 0x7F, 0xC9, 0x97, 0xFC, 0x35, 0xFF, 0x00,
+	0xB2, 0x9C, 0x9F, 0xFA, 0x43, 0x75, 0x5F, 0x81, 0x63, 0xA5, 0x7E, 0xFA, 0x7F, 0xC1, 0xDA, 0x1F,
+	0xF2, 0x65, 0xFF, 0x00, 0x0D, 0x7F, 0xEC, 0xA7, 0x27, 0xFE, 0x90, 0xDD, 0x57, 0xE0, 0x58, 0xE9,
+	0x5C, 0x75, 0xFE, 0x33, 0xD3, 0xC2, 0xFF, 0x00, 0x05, 0x05, 0x14, 0x51, 0x59, 0x9A, 0x85, 0x14,
+	0x51, 0x40, 0x1F, 0xB0, 0x3F, 0xF0, 0x6A, 0x3C, 0xB7, 0x10, 0xE8, 0xBF, 0xB5, 0x25, 0xC5, 0xB1,
+	0x64, 0x68, 0xFC, 0x03, 0xA7, 0xB4, 0x72, 0xAB, 0x6D, 0x74, 0x60, 0x9A, 0x8F, 0x22, 0xBD, 0xD9,
+	0x7E, 0x25, 0xFC, 0x46, 0x2A, 0x09, 0xF8, 0x85, 0xAE, 0x37, 0xBF, 0xF6, 0x9C, 0x83, 0x3F, 0x93,
+	0xD7, 0x84, 0x7F, 0xC1, 0xA8, 0xFF, 0x00, 0xF2, 0x01, 0xFD, 0xAA, 0x7F, 0xEC, 0x9E, 0xE9, 0xFF,
+	0x00, 0xFA, 0x06, 0xA3, 0x5E, 0xB8, 0x3A, 0x57, 0x4D, 0x3D, 0xAE, 0x79, 0xF8, 0x8F, 0xE2, 0x1B,
+	0x9F, 0xF0, 0xB2, 0xBE, 0x22, 0xFF, 0x00, 0xD1, 0x40, 0xD7, 0x3F, 0xF0, 0x69, 0x2F, 0xFF, 0x00,
+	0x17, 0x47, 0xFC, 0x2C, 0xAF, 0x88, 0xBF, 0xF4, 0x50, 0x35, 0xCF, 0xFC, 0x1A, 0x4B, 0xFF, 0x00,
+	0xC5, 0xD6, 0x1D, 0x15, 0x67, 0x39, 0xB9, 0xFF, 0x00, 0x0B, 0x2B, 0xE2, 0x2F, 0xFD, 0x14, 0x0D,
+	0x73, 0xFF, 0x00, 0x06, 0x92, 0xFF, 0x00, 0xF1, 0x75, 0xF4, 0x47, 0xFC, 0x13, 0x07, 0xC6, 0x3E,
+	0x2D, 0xF1, 0x07, 0xED, 0x21, 0x75, 0x65, 0xAE, 0x78, 0xAF, 0x53, 0xBE, 0x85, 0x7C, 0x3B, 0x74,
+	0x56, 0x1B, 0xAB, 0xC7, 0x70, 0x0E, 0xFB, 0x6E, 0x6B, 0xE5, 0xBA, 0xFA, 0x4B, 0xFE, 0x09, 0x5B,
+	0xFF, 0x00, 0x27, 0x35, 0x3F, 0xFD, 0x8A, 0xD7, 0xDF, 0xFA, 0x36, 0xDE, 0x80, 0x3F, 0x1C, 0xFF,
+	0x00, 0xE0, 0xE4, 0x4D, 0xDF, 0xF0, 0xF9, 0xFF, 0x00, 0x8C, 0xDB, 0x8F, 0xFD, 0x0B, 0xBF, 0xFA,
+	0x8F, 0x69, 0x75, 0xF0, 0xED, 0x7D, 0xC5, 0xFF, 0x00, 0x07, 0x23, 0x7F, 0xCA, 0x68, 0x7E, 0x33,
+	0x7F, 0xDC, 0xBB, 0xFF, 0x00, 0xA8, 0xF6, 0x97, 0x5F, 0x0E, 0xD7, 0x24, 0xBE, 0x23, 0xD5, 0xA3,
+	0xFC, 0x24, 0x15, 0x35, 0xA5, 0xE5, 0xD6, 0x9D, 0x77, 0x1E, 0xA3, 0xA6, 0x5D, 0x3D, 0xB5, 0xC5,
+	0xBB, 0x46, 0xD6, 0xF3, 0x47, 0x26, 0xD9, 0x22, 0x98, 0x30, 0x75, 0x71, 0xF8, 0xD4, 0x34, 0x52,
+	0x2C, 0xFD, 0x84, 0xFD, 0x82, 0xBF, 0x6E, 0xFF, 0x00, 0x88, 0x5F, 0xB4, 0xE7, 0xC1, 0x98, 0xE7,
+	0xD6, 0x7E, 0x25, 0x6B, 0x2D, 0xE2, 0x6D, 0x08, 0x25, 0x87, 0x88, 0x21, 0x8F, 0x54, 0x93, 0x73,
+	0xB6, 0xD1, 0xE5, 0x5C, 0xF0, 0xFD, 0x65, 0x51, 0x95, 0xFF, 0x00, 0x6E, 0x39, 0xAB, 0xF5, 0x23,
+	0xFE, 0x09, 0x35, 0xE2, 0x6D, 0x7B, 0xC4, 0x9A, 0x17, 0x8D, 0xAE, 0x35, 0xFD, 0x7A, 0xF2, 0xF9,
+	0xE1, 0xBE, 0xB1, 0xF2, 0x4D, 0xE5, 0xC1, 0x72, 0x8A, 0x63, 0x9B, 0x81, 0x9A, 0xFE, 0x61, 0xFF,
+	0x00, 0x63, 0x9F, 0xDA, 0x37, 0x51, 0xFD, 0x99, 0x3E, 0x38, 0x69, 0xFE, 0x3A, 0x5B, 0x99, 0x8E,
+	0x93, 0x74, 0x16, 0xCB, 0xC4, 0x56, 0xF0, 0xFF, 0x00, 0xCB, 0x4B, 0x37, 0x6C, 0x17, 0x1F, 0xF4,
+	0xD6, 0x36, 0xFD, 0xE4, 0x7E, 0xF1, 0xB0, 0xFE, 0x3A, 0xFE, 0x99, 0x3F, 0xE0, 0x8E, 0x3A, 0xA6,
+	0x9D, 0xAE, 0x78, 0x2B, 0xC6, 0x5A, 0xD6, 0x91, 0x73, 0x0C, 0xD6, 0x97, 0x97, 0x1A, 0x74, 0xF6,
+	0xB3, 0x5B, 0xFF, 0x00, 0xAB, 0x92, 0x36, 0x86, 0x76, 0x56, 0x5F, 0xF6, 0x48, 0x20, 0x8F, 0x6A,
+	0xEA, 0xA7, 0x2E, 0x68, 0xD8, 0xF3, 0xEB, 0xD3, 0xE5, 0x9D, 0xCD, 0x5F, 0xF8, 0x2B, 0x1F, 0x88,
+	0x75, 0xFF, 0x00, 0x0E, 0xE8, 0x1E, 0x09, 0x7F, 0x0E, 0x6B, 0x97, 0xD6, 0x32, 0x4D, 0x79, 0x7C,
+	0xAF, 0xF6, 0x3B, 0x86, 0x8D, 0x99, 0x44, 0x71, 0xFF, 0x00, 0x76, 0xBE, 0x29, 0x5F, 0x89, 0x7F,
+	0x11, 0x48, 0xC8, 0xF8, 0x81, 0xAF, 0x7F, 0xC0, 0xB5, 0x49, 0x73, 0xFF, 0x00, 0xA1, 0xD7, 0xD9,
+	0x3F, 0xF0, 0x58, 0x0F, 0xF9, 0x00, 0x78, 0x17, 0xFE, 0xBF, 0x6F, 0xBF, 0xF4, 0x08, 0xEB, 0xE1,
+	0xBA, 0xAD, 0x0E, 0x73, 0x73, 0xFE, 0x16, 0x57, 0xC4, 0x5F, 0xFA, 0x28, 0x1A, 0xE7, 0xFE, 0x0D,
+	0x25, 0xFF, 0x00, 0xE2, 0xE8, 0xFF, 0x00, 0x85, 0x95, 0xF1, 0x17, 0xFE, 0x8A, 0x06, 0xB9, 0xFF,
+	0x00, 0x83, 0x49, 0x7F, 0xF8, 0xBA, 0xC3, 0xA2, 0x8D, 0x03, 0xDE, 0x37, 0x3F, 0xE1, 0x65, 0x7C,
+	0x45, 0xFF, 0x00, 0xA2, 0x81, 0xAE, 0x7F, 0xE0, 0xD2, 0x5F, 0xFE, 0x2E, 0xBF, 0x48, 0x3F, 0xE0,
+	0x9D, 0x7A, 0xAE, 0xAB, 0xAC, 0xFE, 0xCA, 0xBA, 0x0D, 0xFE, 0xAD, 0xAA, 0xCD, 0x77, 0x70, 0xF7,
+	0x97, 0xC0, 0xCF, 0x75, 0x31, 0x77, 0xC0, 0xBA, 0x7E, 0x39, 0xCD, 0x7E, 0x61, 0xD7, 0xE9, 0xA7,
+	0xFC, 0x13, 0x57, 0xFE, 0x4D, 0x1F, 0x43, 0xFF, 0x00, 0xAF, 0xEB, 0xFF, 0x00, 0xFD, 0x29, 0x6A,
+	0x34, 0x03, 0xC9, 0x7F, 0x6C, 0xDB, 0x97, 0x1F, 0x1D, 0xAF, 0xC0, 0x99, 0xFF, 0x00, 0xE3, 0xCE,
+	0xDB, 0xA7, 0xFB, 0xB5, 0xE5, 0xA6, 0x59, 0x89, 0xCF, 0x9B, 0x25, 0x7A, 0x97, 0xED, 0x9B, 0xFF,
+	0x00, 0x25, 0xF3, 0x50, 0xFF, 0x00, 0xAF, 0x5B, 0x4F, 0xFD, 0x17, 0x5E, 0x52, 0x3A, 0x57, 0xF9,
+	0x71, 0xE2, 0x86, 0x3B, 0x1B, 0x4B, 0xC4, 0x2C, 0xC6, 0x31, 0xA9, 0x24, 0x95, 0x59, 0x69, 0x77,
+	0x6E, 0x9D, 0x0F, 0xE8, 0xCE, 0x1B, 0xA3, 0x42, 0x59, 0x0E, 0x1E, 0x5C, 0xAA, 0xFC, 0x8B, 0xA2,
+	0xFF, 0x00, 0x21, 0xFE, 0x64, 0xDF, 0xF3, 0xD5, 0xE8, 0xF3, 0x26, 0xFF, 0x00, 0x9E, 0xAF, 0x4C,
+	0xA2, 0xBE, 0x03, 0xFB, 0x4F, 0x30, 0xFF, 0x00, 0x9F, 0xB2, 0xFB, 0xDF, 0xF9, 0x9E, 0xE7, 0xB1,
+	0xA3, 0xFC, 0xAB, 0xEE, 0x5F, 0xE4, 0x49, 0xF6, 0x89, 0x87, 0x1E, 0x73, 0x57, 0xE8, 0x07, 0xC1,
+	0x32, 0x5B, 0xE0, 0xDF, 0x85, 0x49, 0x3D, 0x7C, 0x39, 0x65, 0xCF, 0xFD, 0xB0, 0x4A, 0xFC, 0xFB,
+	0xAF, 0xD0, 0x4F, 0x82, 0x5F, 0xF2, 0x46, 0xFC, 0x27, 0xFF, 0x00, 0x62, 0xDD, 0x97, 0xFE, 0x88,
+	0x4A, 0xFE, 0xAC, 0xFA, 0x2A, 0xE2, 0xB1, 0x18, 0x8C, 0xFF, 0x00, 0x31, 0x55, 0x66, 0xDF, 0xEE,
+	0xA1, 0xBB, 0x6F, 0xED, 0xF9, 0x9F, 0x9A, 0x78, 0x95, 0x1A, 0x70, 0xC1, 0xE1, 0xF9, 0x55, 0xBD,
+	0xE7, 0xF9, 0x23, 0xF3, 0x77, 0xF6, 0xC8, 0xF1, 0xE7, 0x8E, 0xAC, 0x3F, 0x6A, 0x2F, 0x1A, 0x69,
+	0xBA, 0x6F, 0x8D, 0x75, 0x4B, 0x78, 0x63, 0xD7, 0x08, 0x58, 0x60, 0xD4, 0xA4, 0x50, 0x14, 0x2A,
+	0x60, 0x00, 0x3A, 0x0F, 0x6A, 0xF3, 0x35, 0xF8, 0x97, 0xF1, 0x14, 0xA8, 0x3F, 0xF0, 0xB0, 0x35,
+	0xCE, 0x9F, 0xF4, 0x14, 0x97, 0xFF, 0x00, 0x8B, 0xAE, 0xE3, 0xF6, 0xD3, 0xFF, 0x00, 0x93, 0xAE,
+	0xF1, 0xB7, 0xFD, 0x87, 0x0F, 0xFE, 0x82, 0xB5, 0xE5, 0x89, 0xF7, 0x07, 0xD2, 0xBF, 0xB6, 0x8F,
+	0xC8, 0x8D, 0xDF, 0xF8, 0x59, 0x5F, 0x11, 0x7F, 0xE8, 0xA0, 0x6B, 0x9F, 0xF8, 0x34, 0x97, 0xFF,
+	0x00, 0x8B, 0xA3, 0xFE, 0x16, 0x57, 0xC4, 0x5F, 0xFA, 0x28, 0x1A, 0xE7, 0xFE, 0x0D, 0x25, 0xFF,
+	0x00, 0xE2, 0xEB, 0x0E, 0x8A, 0x00, 0xDC, 0xFF, 0x00, 0x85, 0x95, 0xF1, 0x17, 0xFE, 0x8A, 0x06,
+	0xB9, 0xFF, 0x00, 0x83, 0x49, 0x7F, 0xF8, 0xBA, 0xFB, 0x8B, 0xFE, 0x09, 0x3D, 0xAF, 0x6B, 0x9E,
+	0x21, 0xF8, 0x79, 0xE3, 0x0B, 0xAD, 0x77, 0x5B, 0xBC, 0xBE, 0x91, 0x75, 0x88, 0x11, 0x64, 0xBC,
+	0xB8, 0xF3, 0x19, 0x47, 0x94, 0x78, 0x19, 0x3F, 0xD6, 0xBE, 0x01, 0xAF, 0xBD, 0x3F, 0xE0, 0x90,
+	0xD9, 0x3F, 0x0D, 0x3C, 0x62, 0x01, 0xC7, 0xFC, 0x4F, 0x20, 0xFF, 0x00, 0xD1, 0x34, 0x01, 0xE5,
+	0xFF, 0x00, 0xF0, 0x53, 0xBF, 0x18, 0x78, 0xB3, 0x40, 0xFD, 0xA4, 0xA1, 0xB0, 0xD0, 0xBC, 0x51,
+	0xA9, 0xD8, 0xC6, 0xDE, 0x1B, 0xB5, 0x67, 0x8E, 0xCE, 0xFE, 0x44, 0x56, 0xFD, 0xE4, 0xDD, 0x40,
+	0x23, 0xF9, 0xD7, 0xCE, 0xFF, 0x00, 0xF0, 0xB2, 0xBE, 0x22, 0xFF, 0x00, 0xD1, 0x40, 0xD7, 0x3F,
+	0xF0, 0x69, 0x2F, 0xFF, 0x00, 0x17, 0x5E, 0xEF, 0xFF, 0x00, 0x05, 0x51, 0xFF, 0x00, 0x93, 0x99,
+	0xB7, 0xFF, 0x00, 0xB1, 0x62, 0xD7, 0xFF, 0x00, 0x43, 0x96, 0xBE, 0x6C, 0xA0, 0x0D, 0xCF, 0xF8,
+	0x59, 0x5F, 0x11, 0x7F, 0xE8, 0xA0, 0x6B, 0x9F, 0xF8, 0x34, 0x97, 0xFF, 0x00, 0x8B, 0xA3, 0xFE,
+	0x16, 0x57, 0xC4, 0x5F, 0xFA, 0x28, 0x1A, 0xE7, 0xFE, 0x0D, 0x25, 0xFF, 0x00, 0xE2, 0xEB, 0x0E,
+	0x8A, 0x00, 0xDB, 0x3F, 0x12, 0xBE, 0x23, 0x63, 0x8F, 0x1F, 0xEB, 0x87, 0xEB, 0xAA, 0x49, 0xFF,
+	0x00, 0xC5, 0x9F, 0xE5, 0x5F, 0x6C, 0x7F, 0xC1, 0x26, 0x3C, 0x47, 0xAE, 0xF8, 0x8F, 0xC3, 0x1E,
+	0x36, 0x7D, 0x7F, 0xC4, 0x37, 0xFA, 0x84, 0x91, 0xDE, 0x58, 0xAA, 0xBD, 0xF5, 0xC1, 0x91, 0x93,
+	0x2B, 0x37, 0x03, 0x3D, 0xAB, 0xE0, 0xCE, 0xDF, 0x85, 0x7D, 0xCF, 0xFF, 0x00, 0x04, 0x81, 0xC9,
+	0xF0, 0xDF, 0x8F, 0x80, 0x38, 0xFF, 0x00, 0x89, 0x85, 0x87, 0xFE, 0x8B, 0x9A, 0x80, 0x3C, 0xF3,
+	0xFE, 0x0A, 0x77, 0xE3, 0x0F, 0x16, 0x68, 0x1F, 0xB4, 0x94, 0x36, 0x1A, 0x17, 0x8A, 0x35, 0x3B,
+	0x18, 0xDB, 0xC3, 0x76, 0xAC, 0xF1, 0xD9, 0xDF, 0xC8, 0x8A, 0xDF, 0xBC, 0x9B, 0xA8, 0x04, 0x7F,
+	0x3A, 0xF9, 0xDF, 0xFE, 0x16, 0x57, 0xC4, 0x5F, 0xFA, 0x28, 0x1A, 0xE7, 0xFE, 0x0D, 0x25, 0xFF,
+	0x00, 0xE2, 0xEB, 0xDD, 0xFF, 0x00, 0xE0, 0xAA, 0x3F, 0xF2, 0x73, 0x36, 0xFF, 0x00, 0xF6, 0x2C,
+	0x5A, 0xFF, 0x00, 0xE8, 0x72, 0xD7, 0xCD, 0x94, 0x01, 0xB9, 0xFF, 0x00, 0x0B, 0x2B, 0xE2, 0x2F,
+	0xFD, 0x14, 0x0D, 0x73, 0xFF, 0x00, 0x06, 0x92, 0xFF, 0x00, 0xF1, 0x74, 0x7F, 0xC2, 0xCA, 0xF8,
+	0x8B, 0xFF, 0x00, 0x45, 0x03, 0x5C, 0xFF, 0x00, 0xC1, 0xA4, 0xBF, 0xFC, 0x5D, 0x61, 0xD1, 0x40,
+	0x1B, 0x67, 0xE2, 0x57, 0xC4, 0x6C, 0x71, 0xE3, 0xFD, 0x70, 0xFD, 0x75, 0x49, 0x3F, 0xF8, 0xB3,
+	0xFC, 0xAB, 0xED, 0x5F, 0xF8, 0x24, 0xD7, 0x88, 0xF5, 0xEF, 0x11, 0xE8, 0x1E, 0x33, 0x93, 0x5E,
+	0xF1, 0x1D, 0xF6, 0xA1, 0x24, 0x37, 0x76, 0x5B, 0x64, 0xBF, 0xBA, 0x69, 0x0A, 0x7C, 0xB2, 0xF0,
+	0x33, 0x5F, 0x07, 0xF6, 0xFC, 0x2B, 0xEE, 0x6F, 0xF8, 0x24, 0x1F, 0xFC, 0x8B, 0xBE, 0x3C, 0xFF,
+	0x00, 0xB0, 0x85, 0x8F, 0xFE, 0x8B, 0x9A, 0x80, 0x3E, 0xCC, 0x8B, 0x85, 0xC0, 0x14, 0xEA, 0x8E,
+	0x0F, 0xE2, 0xFF, 0x00, 0x78, 0x7F, 0xE8, 0x22, 0xA4, 0xA0, 0x02, 0x83, 0xD2, 0x8A, 0x0F, 0x4A,
+	0x00, 0xF8, 0x53, 0xFE, 0x0A, 0xFB, 0xFF, 0x00, 0x23, 0x27, 0x81, 0xFF, 0x00, 0xEB, 0xCA, 0xFB,
+	0xFF, 0x00, 0x46, 0x47, 0x5F, 0x1B, 0x57, 0xD9, 0x3F, 0xF0, 0x57, 0xDF, 0xF9, 0x19, 0x3C, 0x0F,
+	0xFF, 0x00, 0x5E, 0x57, 0xDF, 0xFA, 0x32, 0x3A, 0xF8, 0xDA, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x01,
+	0xD6, 0xBE, 0xB0, 0xFF, 0x00, 0x82, 0x47, 0xFF, 0x00, 0xC9, 0x6A, 0xF1, 0x2F, 0xFD, 0x8A, 0xAB,
+	0xFF, 0x00, 0xA5, 0x31, 0x57, 0xC9, 0xE3, 0xAD, 0x7D, 0x61, 0xFF, 0x00, 0x04, 0x8F, 0xFF, 0x00,
+	0x92, 0xD5, 0xE2, 0x5F, 0xFB, 0x15, 0x57, 0xFF, 0x00, 0x4A, 0x62, 0xA0, 0x0F, 0x5D, 0xFF, 0x00,
+	0x82, 0xB2, 0xFF, 0x00, 0xC9, 0xB8, 0xE8, 0xFF, 0x00, 0xF6, 0x39, 0xDA, 0xFF, 0x00, 0xE9, 0x2D,
+	0xED, 0x7E, 0x79, 0x57, 0xE8, 0x6F, 0xFC, 0x15, 0x97, 0xFE, 0x4D, 0xC7, 0x47, 0xFF, 0x00, 0xB1,
+	0xCE, 0xD7, 0xFF, 0x00, 0x49, 0x6F, 0x6B, 0xF3, 0xCA, 0x94, 0x40, 0x28, 0xA2, 0x8A, 0x60, 0x15,
+	0xEF, 0x5F, 0xF0, 0x4D, 0x8F, 0xF9, 0x3B, 0x9D, 0x07, 0xFE, 0xC1, 0xFA, 0x87, 0xFE, 0x93, 0xBD,
+	0x78, 0x2D, 0x7B, 0xD7, 0xFC, 0x13, 0x63, 0xFE, 0x4E, 0xE7, 0x41, 0xFF, 0x00, 0xB0, 0x7E, 0xA1,
+	0xFF, 0x00, 0xA4, 0xEF, 0x40, 0x1F, 0x64, 0xFF, 0x00, 0xC1, 0x44, 0x7F, 0xE4, 0xCE, 0xFC, 0x63,
+	0xFE, 0xE5, 0x97, 0xFE, 0x9C, 0x2D, 0x6B, 0xF2, 0xF2, 0xBF, 0x50, 0xFF, 0x00, 0xE0, 0xA2, 0x3F,
+	0xF2, 0x67, 0x7E, 0x31, 0xFF, 0x00, 0x72, 0xCB, 0xFF, 0x00, 0x4E, 0x16, 0xB5, 0xF9, 0x79, 0x49,
+	0x00, 0x51, 0x45, 0x14, 0xC0, 0x2B, 0xD1, 0x3F, 0x64, 0xAF, 0xF9, 0x39, 0xCF, 0x00, 0xFF, 0x00,
+	0xD8, 0xD5, 0x69, 0xFF, 0x00, 0xA1, 0x0A, 0xF3, 0xBA, 0xF4, 0x4F, 0xD9, 0x2B, 0xFE, 0x4E, 0x73,
+	0xC0, 0x3F, 0xF6, 0x35, 0x5A, 0x7F, 0xE8, 0x42, 0x80, 0x3F, 0x4B, 0xBF, 0x6A, 0x6F, 0xF9, 0x36,
+	0x4F, 0x88, 0xBF, 0xF6, 0x22, 0xEA, 0xFF, 0x00, 0xFA, 0x41, 0x3D, 0x7E, 0x30, 0xD7, 0xEC, 0xF7,
+	0xED, 0x4D, 0xFF, 0x00, 0x26, 0xC9, 0xF1, 0x17, 0xFE, 0xC4, 0x5D, 0x5F, 0xFF, 0x00, 0x48, 0x27,
+	0xAF, 0xC6, 0x1A, 0xE6, 0xAC, 0xF6, 0x34, 0xA6, 0x14, 0x51, 0x45, 0x62, 0x68, 0x15, 0xF4, 0x67,
+	0xFC, 0x12, 0xAB, 0xFE, 0x4F, 0x17, 0x4A, 0xFF, 0x00, 0xB0, 0x3D, 0xFF, 0x00, 0xFE, 0x88, 0x6A,
+	0xF9, 0xCE, 0xBE, 0x8C, 0xFF, 0x00, 0x82, 0x55, 0xFF, 0x00, 0xC9, 0xE2, 0xE9, 0x5F, 0xF6, 0x07,
+	0xBF, 0xFF, 0x00, 0xD1, 0x0D, 0x4E, 0x17, 0xE7, 0x44, 0xCA, 0xFC, 0xA7, 0xDA, 0xBF, 0xF0, 0x52,
+	0xAF, 0xF9, 0x34, 0xAD, 0x7B, 0xFE, 0xBF, 0x6C, 0x7F, 0xF4, 0xA1, 0x6B, 0xF3, 0x2A, 0xBF, 0x4D,
+	0x7F, 0xE0, 0xA5, 0x5F, 0xF2, 0x69, 0x5A, 0xF7, 0xFD, 0x7E, 0xD8, 0xFF, 0x00, 0xE9, 0x42, 0xD7,
+	0xE6, 0x55, 0x77, 0x18, 0x85, 0x14, 0x51, 0x40, 0x05, 0x7D, 0xC7, 0xFF, 0x00, 0x04, 0x83, 0xFF,
+	0x00, 0x91, 0x6F, 0xC7, 0x5F, 0xF5, 0xFF, 0x00, 0x63, 0xFF, 0x00, 0xA2, 0xAE, 0x2B, 0xE1, 0xCA,
+	0xFB, 0x83, 0xFE, 0x09, 0x12, 0xFE, 0x4F, 0x85, 0xBC, 0x7B, 0x23, 0xB2, 0x86, 0x5B, 0xEB, 0x0F,
+	0xDE, 0x37, 0x65, 0xF2, 0xE6, 0x20, 0x9F, 0x60, 0x4B, 0x51, 0xD2, 0xE1, 0xAE, 0xE7, 0x80, 0xFF,
+	0x00, 0xC1, 0xD2, 0x7F, 0xB4, 0xD5, 0xBF, 0xEC, 0xF1, 0xFB, 0x37, 0x78, 0x3B, 0x4C, 0xD0, 0x35,
+	0x26, 0x8B, 0xC5, 0x1E, 0x2A, 0xBE, 0xD4, 0xEC, 0x74, 0x45, 0x8F, 0xFD, 0x64, 0x51, 0x79, 0x76,
+	0xCB, 0x75, 0x70, 0xBE, 0xE9, 0x1B, 0x80, 0xBF, 0xED, 0xC8, 0x95, 0xFC, 0xE0, 0x9F, 0x66, 0xCF,
+	0xBF, 0xAD, 0x7D, 0x8D, 0xFF, 0x00, 0x05, 0xCE, 0xFD, 0xBF, 0x8F, 0xFC, 0x14, 0x13, 0xF6, 0xF7,
+	0xF1, 0x27, 0x8D, 0x7C, 0x39, 0xAB, 0xCB, 0x37, 0x81, 0xBC, 0x1F, 0xBF, 0xC3, 0xBE, 0x06, 0x8E,
+	0x25, 0xDC, 0x92, 0xD9, 0xC1, 0x23, 0x2C, 0xB7, 0x2A, 0x3B, 0xBC, 0xF3, 0x19, 0x25, 0x1F, 0xDF,
+	0x85, 0xA0, 0x8F, 0xF8, 0x6B, 0xE3, 0x93, 0x90, 0x70, 0x4A, 0xFF, 0x00, 0xC0, 0x5B, 0x23, 0xF0,
+	0x3D, 0xEB, 0x9E, 0x72, 0xE6, 0x7A, 0x9E, 0x96, 0x1E, 0x1C, 0xB4, 0xF5, 0x0A, 0x28, 0xA2, 0xA2,
+	0xC6, 0xC1, 0x5F, 0x4E, 0xFF, 0x00, 0xC1, 0x18, 0xBF, 0xE5, 0x29, 0x9F, 0x04, 0xFF, 0x00, 0xEC,
+	0x73, 0x87, 0xFF, 0x00, 0x45, 0x4B, 0x5F, 0x31, 0x57, 0xD3, 0xBF, 0xF0, 0x46, 0x2F, 0xF9, 0x4A,
+	0x67, 0xC1, 0x3F, 0xFB, 0x1C, 0xE1, 0xFF, 0x00, 0xD1, 0x52, 0xD0, 0xBE, 0x25, 0x72, 0x67, 0xF0,
+	0xB3, 0xFA, 0xAB, 0x3D, 0x68, 0xA0, 0xF5, 0xA2, 0xBB, 0xCF, 0x27, 0xE6, 0x14, 0x51, 0x45, 0x01,
+	0xF3, 0x0A, 0xFC, 0x76, 0xFF, 0x00, 0x83, 0xBB, 0x7F, 0xE4, 0x9F, 0x7C, 0x09, 0xFF, 0x00, 0xB0,
+	0xEE, 0xB9, 0xFF, 0x00, 0xA2, 0xAC, 0xAB, 0xF6, 0x26, 0xBF, 0x1D, 0xBF, 0xE0, 0xEE, 0xDF, 0xF9,
+	0x27, 0xDF, 0x02, 0x7F, 0xEC, 0x3B, 0xAE, 0x7F, 0xE8, 0xAB, 0x2A, 0xCE, 0xA7, 0xF0, 0xCD, 0xA8,
+	0x7F, 0x11, 0x59, 0x9F, 0x87, 0xE9, 0xF7, 0x07, 0xD2, 0x96, 0x91, 0x3E, 0xE0, 0xFA, 0x52, 0xD7,
+	0x19, 0xEA, 0x58, 0x28, 0xA2, 0x8A, 0x05, 0x6F, 0x30, 0xAF, 0xDC, 0x1F, 0xF8, 0x34, 0x53, 0xFE,
+	0x49, 0xAF, 0xC6, 0xEF, 0xFB, 0x0D, 0xE8, 0xBF, 0xFA, 0x26, 0xF2, 0xBF, 0x0F, 0xAB, 0xF7, 0x07,
+	0xFE, 0x0D, 0x14, 0xFF, 0x00, 0x92, 0x6B, 0xF1, 0xBB, 0xFE, 0xC3, 0x7A, 0x2F, 0xFE, 0x89, 0xBC,
+	0xAD, 0x28, 0xFF, 0x00, 0x13, 0x4D, 0x4E, 0x6C, 0x47, 0xF0, 0x5B, 0x47, 0xEC, 0x3D, 0x14, 0x51,
+	0x5D, 0xDC, 0xA7, 0x9E, 0x14, 0x51, 0x45, 0x16, 0x00, 0xAF, 0xE7, 0xC7, 0xFE, 0x0E, 0xC1, 0xFF,
+	0x00, 0x94, 0x88, 0x78, 0x33, 0xFE, 0xC8, 0xBE, 0x9D, 0xFF, 0x00, 0xA7, 0x7D, 0x5A, 0xBF, 0xA0,
+	0xEA, 0xFE, 0x7C, 0x7F, 0xE0, 0xEC, 0x1F, 0xF9, 0x48, 0x87, 0x83, 0x3F, 0xEC, 0x8B, 0xE9, 0xDF,
+	0xFA, 0x77, 0xD5, 0xAB, 0x0A, 0xDF, 0x09, 0xD1, 0x87, 0xFE, 0x21, 0xF9, 0x8B, 0x45, 0x14, 0x57,
+	0x1D, 0xD1, 0xE8, 0x6A, 0x14, 0x51, 0x45, 0x17, 0x41, 0xA8, 0x57, 0xF4, 0xEB, 0xFF, 0x00, 0x06,
+	0xF2, 0xFF, 0x00, 0xCA, 0x1F, 0xFE, 0x10, 0x7D, 0x75, 0xEF, 0xFD, 0x48, 0x75, 0x1A, 0xFE, 0x62,
+	0xAB, 0xFA, 0x75, 0xFF, 0x00, 0x83, 0x79, 0x7F, 0xE5, 0x0F, 0xFF, 0x00, 0x08, 0x3E, 0xBA, 0xF7,
+	0xFE, 0xA4, 0x3A, 0x8D, 0x6F, 0x42, 0xDC, 0xE7, 0x2E, 0x27, 0xF8, 0x68, 0xFB, 0x4C, 0x74, 0xA2,
+	0x81, 0xD2, 0x8A, 0xEA, 0xB7, 0x43, 0x87, 0xCC, 0x28, 0xA2, 0x8A, 0x00, 0x2B, 0xF9, 0x20, 0xFF,
+	0x00, 0x82, 0x91, 0xFF, 0x00, 0xCA, 0x44, 0xBE, 0x3E, 0x7F, 0xD9, 0x69, 0xF1, 0x4F, 0xFE, 0x9D,
+	0xEE, 0xAB, 0xFA, 0xDF, 0xAF, 0xE4, 0x83, 0xFE, 0x0A, 0x47, 0xFF, 0x00, 0x29, 0x12, 0xF8, 0xF9,
+	0xFF, 0x00, 0x65, 0xA7, 0xC5, 0x3F, 0xFA, 0x77, 0xBA, 0xAE, 0x7A, 0xFF, 0x00, 0x0A, 0x3A, 0xF0,
+	0xBA, 0xC9, 0x9E, 0x2D, 0x45, 0x14, 0x57, 0x39, 0xDA, 0x14, 0x51, 0x45, 0x00, 0x34, 0xFD, 0xFF,
+	0x00, 0xC7, 0xFA, 0x0A, 0xFE, 0xD2, 0x8F, 0x5A, 0xFE, 0x2D, 0x4F, 0xDF, 0xFC, 0x7F, 0xA0, 0xAF,
+	0xED, 0x28, 0xF5, 0xAE, 0x8C, 0x3A, 0x38, 0xF1, 0x57, 0xD0, 0x28, 0xA2, 0x8A, 0xE8, 0x38, 0xC2,
+	0x8A, 0x28, 0xA0, 0x0F, 0xCA, 0xBF, 0xF8, 0x3B, 0x43, 0xFE, 0x4C, 0xBF, 0xE1, 0xAF, 0xFD, 0x94,
+	0xE4, 0xFF, 0x00, 0xD2, 0x1B, 0xAA, 0xFC, 0x0B, 0x1D, 0x2B, 0xF7, 0xD3, 0xFE, 0x0E, 0xD0, 0xFF,
+	0x00, 0x93, 0x2F, 0xF8, 0x6B, 0xFF, 0x00, 0x65, 0x39, 0x3F, 0xF4, 0x86, 0xEA, 0xBF, 0x02, 0xC7,
+	0x4A, 0xE4, 0xAC, 0xAF, 0x2B, 0x9E, 0x96, 0x1B, 0x99, 0x51, 0x41, 0x45, 0x14, 0x56, 0x5F, 0x23,
+	0x6D, 0x02, 0x8A, 0x28, 0xA3, 0xE4, 0x1A, 0x1F, 0xB0, 0x1F, 0xF0, 0x6A, 0x3F, 0xFC, 0x80, 0x7F,
+	0x6A, 0x9F, 0xFB, 0x27, 0xBA, 0x7F, 0xFE, 0x81, 0xA8, 0xD7, 0xAE, 0x0E, 0x95, 0xE4, 0x7F, 0xF0,
+	0x6A, 0x46, 0x7F, 0xB0, 0x7F, 0x6A, 0x9F, 0xFB, 0x27, 0xDA, 0x7F, 0xFE, 0x81, 0xA8, 0xD7, 0xAE,
+	0x0E, 0x95, 0xD3, 0x4F, 0xE1, 0x3C, 0xFC, 0x47, 0xF1, 0x58, 0x51, 0x45, 0x15, 0x67, 0x3D, 0xD0,
+	0x57, 0xD2, 0x5F, 0xF0, 0x4A, 0xDF, 0xF9, 0x39, 0xA9, 0xFF, 0x00, 0xEC, 0x56, 0xBE, 0xFF, 0x00,
+	0xD1, 0xB6, 0xF5, 0xF3, 0x6D, 0x7D, 0x25, 0xFF, 0x00, 0x04, 0xAD, 0xFF, 0x00, 0x93, 0x9A, 0x9F,
+	0xFE, 0xC5, 0x6B, 0xEF, 0xFD, 0x1B, 0x6F, 0x40, 0x5D, 0x1F, 0x8E, 0x7F, 0xF0, 0x72, 0x37, 0xFC,
+	0xA6, 0x87, 0xE3, 0x37, 0xFD, 0xCB, 0xBF, 0xFA, 0x8F, 0x69, 0x75, 0xF0, 0xED, 0x7D, 0xC5, 0xFF,
+	0x00, 0x07, 0x22, 0xFF, 0x00, 0xCA, 0x68, 0x3E, 0x33, 0x73, 0xFF, 0x00, 0x42, 0xEF, 0xFE, 0xA3,
+	0xDA, 0x5D, 0x7C, 0x3B, 0x5C, 0x92, 0xF8, 0xBC, 0xCF, 0x56, 0x97, 0xF0, 0x90, 0x51, 0x45, 0x14,
+	0x8B, 0xD4, 0x2B, 0xF7, 0xBB, 0xFE, 0x0D, 0x26, 0xFD, 0xAF, 0xF4, 0x7F, 0x1A, 0x78, 0x13, 0xC7,
+	0x9F, 0xB2, 0x77, 0x8B, 0xF5, 0xD8, 0xBF, 0xE1, 0x22, 0xF0, 0xF5, 0xBD, 0x96, 0xA5, 0xE1, 0xF8,
+	0x2E, 0x9F, 0xF7, 0x97, 0x9A, 0x4E, 0xF9, 0x52, 0x50, 0xBE, 0xD6, 0xF2, 0x3C, 0x60, 0xFF, 0x00,
+	0xB3, 0x71, 0x0D, 0x7E, 0x08, 0xD7, 0xB0, 0x7E, 0xC0, 0xFF, 0x00, 0xB5, 0xF7, 0x8C, 0xBF, 0x60,
+	0xFF, 0x00, 0xDA, 0xE3, 0xC1, 0x5F, 0xB5, 0x07, 0x83, 0x4C, 0xF3, 0x37, 0x86, 0xF5, 0x60, 0xDA,
+	0xB6, 0x99, 0x0B, 0x60, 0x6A, 0x1A, 0x7C, 0xA8, 0x63, 0xB9, 0xB6, 0xCF, 0x63, 0x2C, 0x25, 0xD1,
+	0x4F, 0xF0, 0xCA, 0x55, 0xFF, 0x00, 0x86, 0x9C, 0x25, 0xCB, 0x2B, 0x23, 0x2A, 0xD4, 0xF9, 0xE9,
+	0x9F, 0xD2, 0xFF, 0x00, 0xFC, 0x15, 0xF4, 0x6D, 0xF0, 0xEF, 0x80, 0xD7, 0x2D, 0xC5, 0xE5, 0xF7,
+	0xDE, 0xEB, 0xFE, 0xAE, 0x3E, 0xBE, 0xF5, 0xF0, 0xE5, 0x7D, 0x91, 0xFF, 0x00, 0x05, 0x2F, 0xF8,
+	0x89, 0xE0, 0xDF, 0x8B, 0x5F, 0x05, 0xBE, 0x14, 0xFC, 0x56, 0xF0, 0x06, 0xB3, 0x0E, 0xA5, 0xE1,
+	0xFF, 0x00, 0x11, 0x5A, 0xC9, 0xA9, 0x68, 0xF7, 0xD0, 0x0C, 0x2C, 0xF6, 0xF3, 0xDB, 0x41, 0x2C,
+	0x52, 0x01, 0xD8, 0x32, 0x3A, 0x9F, 0xC6, 0xBE, 0x37, 0x39, 0xCF, 0x26, 0xBA, 0xF5, 0xEC, 0x79,
+	0x81, 0x45, 0x14, 0x50, 0x01, 0x5F, 0xA6, 0x9F, 0xF0, 0x4D, 0x5F, 0xF9, 0x34, 0x7D, 0x0F, 0xFE,
+	0xBF, 0xAF, 0xFF, 0x00, 0xF4, 0xA5, 0xAB, 0xF3, 0x2E, 0xBF, 0x4D, 0x3F, 0xE0, 0x9A, 0xBF, 0xF2,
+	0x68, 0xFA, 0x1F, 0xFD, 0x7F, 0x5F, 0xFF, 0x00, 0xE9, 0x4B, 0x50, 0x07, 0x92, 0xFE, 0xD9, 0xBF,
+	0xF2, 0x5F, 0x35, 0x0F, 0xFA, 0xF5, 0xB4, 0xFF, 0x00, 0xD1, 0x75, 0xE5, 0x23, 0xA5, 0x7A, 0xB7,
+	0xED, 0x98, 0x4F, 0xFC, 0x2F, 0xBD, 0x43, 0xFE, 0xBD, 0x6D, 0x3F, 0xF4, 0x5D, 0x79, 0x48, 0xFB,
+	0xA2, 0xBF, 0xCA, 0xEF, 0x15, 0x7F, 0xE4, 0xE1, 0xE6, 0x6E, 0xFF, 0x00, 0xF2, 0xF6, 0x5F, 0xA1,
+	0xFD, 0x1F, 0xC3, 0x3F, 0xF2, 0x4F, 0xE1, 0x9F, 0xF7, 0x50, 0x51, 0x45, 0x15, 0xF9, 0xE1, 0xEE,
+	0x85, 0x7E, 0x82, 0x7C, 0x12, 0xFF, 0x00, 0x92, 0x37, 0xE1, 0x3F, 0xFB, 0x16, 0xEC, 0xBF, 0xF4,
+	0x42, 0x57, 0xE7, 0xDF, 0xD4, 0x57, 0xE8, 0x27, 0xC1, 0x2F, 0xF9, 0x23, 0x9E, 0x13, 0x3F, 0xF5,
+	0x2D, 0xD8, 0xFF, 0x00, 0xE8, 0x84, 0xAF, 0xEB, 0x2F, 0xA2, 0x7E, 0x9C, 0x41, 0x99, 0x7F, 0xD7,
+	0xA8, 0x7F, 0xE9, 0x67, 0xE6, 0x3E, 0x25, 0xFF, 0x00, 0xB9, 0xE1, 0xFF, 0x00, 0xC5, 0x2F, 0xC9,
+	0x1F, 0x99, 0x3F, 0xB6, 0x9F, 0xFC, 0x9D, 0x77, 0x8D, 0xBF, 0xEC, 0x38, 0x7F, 0xF4, 0x15, 0xAF,
+	0x2C, 0x4F, 0xB8, 0x3E, 0x95, 0xEA, 0x7F, 0xB6, 0x9F, 0xFC, 0x9D, 0x77, 0x8D, 0xBF, 0xEC, 0x38,
+	0x7F, 0xF4, 0x15, 0xAF, 0x2C, 0x4F, 0xB8, 0x3E, 0x95, 0xFD, 0xC4, 0x7E, 0x42, 0x2D, 0x14, 0x51,
+	0x40, 0x05, 0x7D, 0xE9, 0xFF, 0x00, 0x04, 0x85, 0xFF, 0x00, 0x92, 0x6B, 0xE3, 0x0F, 0xFB, 0x0E,
+	0x41, 0xFF, 0x00, 0xA2, 0x6B, 0xE0, 0xBA, 0xFB, 0xD3, 0xFE, 0x09, 0x0B, 0xFF, 0x00, 0x24, 0xD7,
+	0xC6, 0x1F, 0xF6, 0x1C, 0x83, 0xFF, 0x00, 0x44, 0xD0, 0x07, 0x8F, 0x7F, 0xC1, 0x54, 0x7F, 0xE4,
+	0xE6, 0x6D, 0xFF, 0x00, 0xEC, 0x58, 0xB5, 0xFF, 0x00, 0xD0, 0xE5, 0xAF, 0x9B, 0x2B, 0xE9, 0x3F,
+	0xF8, 0x2A, 0x8F, 0xFC, 0x9C, 0xCD, 0xBF, 0xFD, 0x8B, 0x16, 0xBF, 0xFA, 0x1C, 0xB5, 0xF3, 0x65,
+	0x00, 0x14, 0x51, 0x45, 0x00, 0x1D, 0xBF, 0x0A, 0xFB, 0xA3, 0xFE, 0x09, 0x01, 0xFF, 0x00, 0x22,
+	0xE7, 0x8F, 0xBF, 0xEC, 0x21, 0x61, 0xFF, 0x00, 0xA2, 0xE6, 0xAF, 0x85, 0xFB, 0x7E, 0x15, 0xF7,
+	0x47, 0xFC, 0x12, 0x03, 0xFE, 0x45, 0xCF, 0x1F, 0x7F, 0xD8, 0x42, 0xC3, 0xFF, 0x00, 0x45, 0xCD,
+	0x40, 0x1E, 0x55, 0xFF, 0x00, 0x05, 0x51, 0xFF, 0x00, 0x93, 0x99, 0xB7, 0xFF, 0x00, 0xB1, 0x62,
+	0xD7, 0xFF, 0x00, 0x43, 0x96, 0xBE, 0x6C, 0xAF, 0xA4, 0xFF, 0x00, 0xE0, 0xAA, 0x3F, 0xF2, 0x73,
+	0x36, 0xFF, 0x00, 0xF6, 0x2C, 0x5A, 0xFF, 0x00, 0xE8, 0x72, 0xD7, 0xCD, 0x94, 0x00, 0x51, 0x45,
+	0x14, 0x00, 0x76, 0xFC, 0x2B, 0xEE, 0x6F, 0xF8, 0x24, 0x1F, 0xFC, 0x8B, 0xBE, 0x3C, 0xFF, 0x00,
+	0xB0, 0x85, 0x8F, 0xFE, 0x8B, 0x9A, 0xBE, 0x19, 0xED, 0xF8, 0x57, 0xDC, 0xDF, 0xF0, 0x48, 0x3F,
+	0xF9, 0x17, 0x7C, 0x79, 0xFF, 0x00, 0x61, 0x0B, 0x1F, 0xFD, 0x17, 0x35, 0x00, 0x7D, 0x95, 0x07,
+	0xF1, 0x7F, 0xBC, 0x3F, 0xF4, 0x11, 0x52, 0x54, 0x70, 0x7F, 0x17, 0xFB, 0xC3, 0xFF, 0x00, 0x41,
+	0x15, 0x25, 0x00, 0x14, 0x8E, 0x70, 0x84, 0xFB, 0x52, 0xD2, 0x38, 0x2C, 0x85, 0x41, 0xED, 0x40,
+	0x1F, 0x33, 0x7E, 0xDD, 0x7F, 0xB2, 0x5F, 0xC4, 0x6F, 0xDA, 0x8F, 0xC4, 0x5E, 0x1E, 0x9B, 0xE1,
+	0xFE, 0xB1, 0xA1, 0xD9, 0x8D, 0x16, 0xD6, 0x65, 0xBA, 0x3A, 0xC5, 0xC4, 0xCA, 0x0F, 0x9A, 0x54,
+	0x8C, 0x79, 0x71, 0x3F, 0xF7, 0x2B, 0xC1, 0xFF, 0x00, 0xE1, 0xD3, 0x1F, 0xB4, 0x4F, 0xFD, 0x0E,
+	0x9E, 0x0A, 0xFF, 0x00, 0xC0, 0xDB, 0xDF, 0xFE, 0x47, 0xAF, 0xB0, 0xBE, 0x33, 0xFE, 0xD3, 0x5F,
+	0x09, 0x3F, 0x67, 0xAD, 0x6A, 0xCE, 0x2F, 0x8A, 0xDE, 0x21, 0x9B, 0x4F, 0x3A, 0xA5, 0xB1, 0x7B,
+	0x55, 0x8E, 0xC6, 0x69, 0xB7, 0x79, 0x6F, 0x86, 0x19, 0x40, 0x7F, 0xBE, 0xB5, 0xC7, 0xFF, 0x00,
+	0xC3, 0xCB, 0x3F, 0x64, 0x3F, 0xFA, 0x1E, 0xF5, 0x0F, 0xFC, 0x10, 0xDC, 0x7F, 0xF1, 0xBA, 0x00,
+	0xF9, 0xB7, 0xFE, 0x1D, 0x31, 0xFB, 0x44, 0xFF, 0x00, 0xD0, 0xE9, 0xE0, 0xAF, 0xFC, 0x0D, 0xBD,
+	0xFF, 0x00, 0xE4, 0x7A, 0x3F, 0xE1, 0xD3, 0x1F, 0xB4, 0x4F, 0xFD, 0x0E, 0x9E, 0x0A, 0xFF, 0x00,
+	0xC0, 0xDB, 0xDF, 0xFE, 0x47, 0xAF, 0xA4, 0xBF, 0xE1, 0xE5, 0x9F, 0xB2, 0x1F, 0xFD, 0x0F, 0x7A,
+	0x87, 0xFE, 0x08, 0x6E, 0x3F, 0xF8, 0xDD, 0x1F, 0xF0, 0xF2, 0xCF, 0xD9, 0x0F, 0xFE, 0x87, 0xBD,
+	0x43, 0xFF, 0x00, 0x04, 0x37, 0x1F, 0xFC, 0x6E, 0x80, 0x3E, 0x6D, 0x3F, 0xF0, 0x49, 0x9F, 0xDA,
+	0x28, 0x0C, 0x8F, 0x1A, 0x78, 0x2F, 0xFE, 0x03, 0x7D, 0x7A, 0x0F, 0xFE, 0x93, 0x1F, 0xE4, 0x6B,
+	0xDA, 0x3F, 0x61, 0x8F, 0xD8, 0xBB, 0xE2, 0xA7, 0xEC, 0xCB, 0xF1, 0x0B, 0x58, 0xF1, 0x6F, 0x8E,
+	0xF5, 0xBF, 0x0F, 0xDE, 0x41, 0x7F, 0xA4, 0xFD, 0x92, 0x31, 0xA3, 0xDC, 0x4D, 0x23, 0x86, 0xF3,
+	0x23, 0x93, 0xE6, 0x2F, 0x04, 0x7E, 0x95, 0xD5, 0x3F, 0xFC, 0x14, 0xAF, 0xF6, 0x45, 0x64, 0x21,
+	0x7C, 0x77, 0x7F, 0x9C, 0x71, 0xFF, 0x00, 0x12, 0x2B, 0x91, 0xFC, 0xA3, 0xCF, 0xE5, 0x5D, 0x7F,
+	0xC1, 0x8F, 0xDA, 0xBB, 0xE0, 0xA7, 0xC7, 0xED, 0x7A, 0xEB, 0xC3, 0x1F, 0x0A, 0xFC, 0x49, 0x73,
+	0x7B, 0x75, 0x63, 0x69, 0xF6, 0x9B, 0x85, 0x9B, 0x4D, 0x9A, 0x10, 0xB1, 0x09, 0x02, 0x03, 0x99,
+	0x10, 0x67, 0x93, 0x40, 0x18, 0x7F, 0xB7, 0x0F, 0xEC, 0xF3, 0xE3, 0x3F, 0xDA, 0x4F, 0xE1, 0x56,
+	0x9F, 0xE0, 0x5F, 0x02, 0xEA, 0x5A, 0x6D, 0xB5, 0xE5, 0xAF, 0x88, 0xA1, 0xBD, 0xF3, 0x35, 0x67,
+	0x74, 0x88, 0x46, 0xB0, 0xCF, 0x1B, 0x0F, 0x91, 0x1C, 0x9F, 0xF5, 0xAB, 0xDA, 0xBE, 0x5A, 0xFF,
+	0x00, 0x87, 0x4C, 0x7E, 0xD1, 0x3F, 0xF4, 0x3A, 0x78, 0x2B, 0xFF, 0x00, 0x03, 0x6F, 0x7F, 0xF9,
+	0x1E, 0xBE, 0xDA, 0xF8, 0xD1, 0xF1, 0xBF, 0xE1, 0xF7, 0xC0, 0x5F, 0x0D, 0xDB, 0xF8, 0xC7, 0xE2,
+	0x6E, 0xB3, 0x25, 0x8D, 0x85, 0xCD, 0xE8, 0xB3, 0x59, 0xE3, 0xB7, 0x79, 0x87, 0x9A, 0x63, 0x92,
+	0x40, 0x30, 0x9C, 0x8E, 0x23, 0x7A, 0xF3, 0x7F, 0xF8, 0x79, 0x67, 0xEC, 0x87, 0xFF, 0x00, 0x43,
+	0xDE, 0xA1, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x37, 0x49, 0x01, 0xF3, 0x6F, 0xFC, 0x3A, 0x63,
+	0xF6, 0x89, 0xFF, 0x00, 0xA1, 0xD3, 0xC1, 0x5F, 0xF8, 0x1B, 0x7B, 0xFF, 0x00, 0xC8, 0xF4, 0x7F,
+	0xC3, 0xA6, 0x3F, 0x68, 0x9F, 0xFA, 0x1D, 0x3C, 0x15, 0xFF, 0x00, 0x81, 0xB7, 0xBF, 0xFC, 0x8F,
+	0x5F, 0x49, 0x7F, 0xC3, 0xCB, 0x3F, 0x64, 0x3F, 0xFA, 0x1E, 0xF5, 0x0F, 0xFC, 0x10, 0xDC, 0x7F,
+	0xF1, 0xBA, 0x3F, 0xE1, 0xE5, 0x9F, 0xB2, 0x1F, 0xFD, 0x0F, 0x7A, 0x87, 0xFE, 0x08, 0x6E, 0x3F,
+	0xF8, 0xDD, 0x30, 0x3E, 0x6D, 0xFF, 0x00, 0x87, 0x4C, 0x7E, 0xD1, 0x3F, 0xF4, 0x3A, 0x78, 0x2B,
+	0xFF, 0x00, 0x03, 0x6F, 0x7F, 0xF9, 0x1E, 0xBD, 0x1B, 0xF6, 0x46, 0xFD, 0x80, 0x7E, 0x33, 0x7C,
+	0x04, 0xF8, 0xE7, 0xA7, 0xFC, 0x4D, 0xF1, 0x87, 0x88, 0xBC, 0x33, 0x75, 0x65, 0x67, 0x6B, 0x71,
+	0x1B, 0xC7, 0xA6, 0xDD, 0x5C, 0x49, 0x3F, 0xEF, 0x22, 0x74, 0xFE, 0x3B, 0x78, 0xEB, 0xD3, 0x3F,
+	0xE1, 0xE5, 0x9F, 0xB2, 0x1F, 0xFD, 0x0F, 0x7A, 0x87, 0xFE, 0x08, 0x6E, 0x3F, 0xF8, 0xDD, 0x6F,
+	0xFC, 0x2B, 0xFD, 0xB4, 0xFF, 0x00, 0x67, 0xDF, 0x8C, 0xBE, 0x31, 0xB6, 0xF8, 0x7B, 0xF0, 0xF3,
+	0xC5, 0x77, 0x57, 0x7A, 0xAD, 0xD4, 0x72, 0x3C, 0x30, 0xC9, 0xA5, 0xDC, 0x44, 0x30, 0x89, 0xBD,
+	0xFE, 0x79, 0x52, 0x80, 0x35, 0x7F, 0x6A, 0xEF, 0x84, 0xFE, 0x21, 0xF8, 0xE3, 0xF0, 0x13, 0x5F,
+	0xF8, 0x63, 0xE1, 0x5B, 0xAB, 0x48, 0x75, 0x0D, 0x51, 0x6D, 0xBE, 0xCA, 0xF7, 0xEC, 0xCB, 0x12,
+	0x34, 0x77, 0x30, 0xCC, 0x49, 0x65, 0x56, 0x38, 0xC4, 0x67, 0xA0, 0x35, 0xF1, 0xCF, 0xFC, 0x3A,
+	0x63, 0xF6, 0x8A, 0xEF, 0xE3, 0x5F, 0x04, 0xFF, 0x00, 0xC0, 0x6F, 0x6F, 0x71, 0xFF, 0x00, 0xA4,
+	0xD5, 0xF7, 0x57, 0xC5, 0x0F, 0x89, 0x3E, 0x16, 0xF8, 0x47, 0xE0, 0xAB, 0xBF, 0x88, 0x3E, 0x39,
+	0xBF, 0x92, 0xDB, 0x4B, 0xD3, 0xDE, 0x25, 0xBA, 0x9E, 0x38, 0x5A, 0x4D, 0x82, 0x49, 0x12, 0x25,
+	0xCA, 0xAF, 0x3F, 0x79, 0xD7, 0xA5, 0x79, 0x3A, 0x7F, 0xC1, 0x4B, 0x7F, 0x64, 0x32, 0xA0, 0xFF,
+	0x00, 0xC2, 0x7D, 0x7C, 0xDC, 0x7D, 0xE5, 0xD0, 0x6E, 0x39, 0xFF, 0x00, 0xC7, 0x28, 0x03, 0xE6,
+	0xDF, 0xF8, 0x74, 0xC7, 0xED, 0x13, 0xFF, 0x00, 0x43, 0xA7, 0x82, 0xBF, 0xF0, 0x36, 0xF7, 0xFF,
+	0x00, 0x91, 0xE8, 0xFF, 0x00, 0x87, 0x4C, 0x7E, 0xD1, 0x3F, 0xF4, 0x3A, 0x78, 0x2B, 0xFF, 0x00,
+	0x03, 0x6F, 0x7F, 0xF9, 0x1E, 0xBE, 0x92, 0xFF, 0x00, 0x87, 0x96, 0x7E, 0xC8, 0x7F, 0xF4, 0x3D,
+	0xEA, 0x1F, 0xF8, 0x21, 0xB8, 0xFF, 0x00, 0xE3, 0x74, 0x7F, 0xC3, 0xCB, 0x3F, 0x64, 0x3F, 0xFA,
+	0x1E, 0xF5, 0x0F, 0xFC, 0x10, 0xDC, 0x7F, 0xF1, 0xBA, 0x00, 0xF9, 0xB7, 0xFE, 0x1D, 0x31, 0xFB,
+	0x44, 0xFF, 0x00, 0xD0, 0xE9, 0xE0, 0xAF, 0xFC, 0x0D, 0xBD, 0xFF, 0x00, 0xE4, 0x7A, 0xE9, 0xBE,
+	0x08, 0x7F, 0xC1, 0x35, 0x3E, 0x3C, 0x7C, 0x33, 0xF8, 0xC9, 0xE1, 0xBF, 0x88, 0x1A, 0xE7, 0x8A,
+	0x7C, 0x27, 0x71, 0x69, 0xA2, 0xEA, 0xD0, 0xDD, 0xCD, 0x15, 0xAD, 0xE5, 0xCB, 0xCC, 0x44, 0x6E,
+	0xA7, 0xE5, 0x0F, 0x6C, 0xBE, 0xBE, 0xA7, 0xEB, 0x5E, 0xD9, 0xFF, 0x00, 0x0F, 0x2C, 0xFD, 0x90,
+	0xFF, 0x00, 0xE8, 0x7B, 0xD4, 0x3F, 0xF0, 0x43, 0x71, 0xFF, 0x00, 0xC6, 0xEB, 0x43, 0xC1, 0x9F,
+	0xB7, 0xCF, 0xEC, 0xCB, 0xE3, 0xDF, 0x15, 0xE9, 0xFE, 0x0A, 0xF0, 0xB7, 0x8C, 0xAF, 0x27, 0xD4,
+	0xB5, 0x6B, 0xC8, 0xED, 0xEC, 0xA1, 0x6D, 0x1E, 0xE5, 0x43, 0x4A, 0xE4, 0x85, 0xF9, 0x9D, 0x36,
+	0x8E, 0x07, 0xD2, 0x80, 0x3B, 0xEF, 0x8E, 0x9E, 0x16, 0xD6, 0x7C, 0x77, 0xF0, 0x4F, 0xC5, 0xFE,
+	0x0B, 0xF0, 0xDA, 0xAF, 0xF6, 0x86, 0xB1, 0xE1, 0x6D, 0x42, 0xCA, 0xC5, 0x26, 0x6D, 0xAA, 0x66,
+	0x96, 0xDA, 0x48, 0xE3, 0xCB, 0x76, 0xF9, 0x99, 0x7E, 0x95, 0xF9, 0xCF, 0xFF, 0x00, 0x0E, 0x9E,
+	0xFD, 0xAE, 0x10, 0x6D, 0x1A, 0x2E, 0x89, 0xC7, 0x1F, 0xF2, 0x19, 0x4A, 0xFD, 0x2D, 0xF1, 0xBF,
+	0x8A, 0xF4, 0xBF, 0x00, 0xF8, 0x2F, 0x56, 0xF1, 0xBF, 0x88, 0xDA, 0x4F, 0xB0, 0xE8, 0xBA, 0x6C,
+	0xD7, 0xF7, 0xBE, 0x4A, 0xEE, 0x7F, 0x26, 0x28, 0xD9, 0xDF, 0x0B, 0xDF, 0xE5, 0x0D, 0x5F, 0x3E,
+	0x27, 0xFC, 0x15, 0xA7, 0xF6, 0x4C, 0xF2, 0xD4, 0x34, 0xFE, 0x22, 0xCE, 0xDE, 0x7F, 0xE2, 0x4B,
+	0xFF, 0x00, 0xD9, 0xD6, 0x53, 0x8C, 0x77, 0x65, 0x46, 0xE7, 0xCA, 0x9F, 0xF0, 0xEA, 0x2F, 0xDA,
+	0xE3, 0xFE, 0x80, 0xBA, 0x27, 0xFE, 0x0E, 0x12, 0x8F, 0xF8, 0x75, 0x17, 0xED, 0x71, 0xFF, 0x00,
+	0x40, 0x5D, 0x13, 0xFF, 0x00, 0x07, 0x09, 0x5F, 0x56, 0xFF, 0x00, 0xC3, 0xDA, 0x7F, 0x64, 0xAF,
+	0xF9, 0xF8, 0xF1, 0x17, 0xFE, 0x09, 0x7F, 0xFB, 0x65, 0x1F, 0xF0, 0xF6, 0x9F, 0xD9, 0x2B, 0xFE,
+	0x7E, 0x3C, 0x45, 0xFF, 0x00, 0x82, 0x5F, 0xFE, 0xD9, 0x59, 0xF2, 0xD0, 0x2A, 0xF2, 0x3E, 0x52,
+	0xFF, 0x00, 0x87, 0x51, 0x7E, 0xD7, 0x1F, 0xF4, 0x05, 0xD1, 0x3F, 0xF0, 0x70, 0x95, 0xEB, 0xFF,
+	0x00, 0xB0, 0xAF, 0xEC, 0x17, 0xFB, 0x40, 0xFC, 0x02, 0xFD, 0xA1, 0xAC, 0xBE, 0x24, 0x7C, 0x43,
+	0xB0, 0xD2, 0x61, 0xD3, 0x6D, 0x74, 0xEB, 0xA8, 0xDC, 0xDA, 0xEA, 0x9E, 0x73, 0x6E, 0x91, 0x42,
+	0x8E, 0x3F, 0x0A, 0xF4, 0xEF, 0xF8, 0x7B, 0x4F, 0xEC, 0x95, 0xFF, 0x00, 0x3F, 0x1E, 0x22, 0xFF,
+	0x00, 0xC1, 0x2F, 0xFF, 0x00, 0x6C, 0xAE, 0xAB, 0xE0, 0x8F, 0xED, 0xFB, 0xF0, 0x0F, 0xF6, 0x82,
+	0xF8, 0x83, 0x17, 0xC3, 0x3F, 0x87, 0xB7, 0x3A, 0xC7, 0xF6, 0x9D, 0xC4, 0x32, 0x4B, 0x17, 0xDB,
+	0xF4, 0xBF, 0x25, 0x76, 0xA2, 0x87, 0x3C, 0xE4, 0xF1, 0xCD, 0x38, 0xC6, 0x97, 0x40, 0x94, 0xA5,
+	0xCA, 0x74, 0x1F, 0xB5, 0xD7, 0xC1, 0xDF, 0x14, 0xFC, 0x7B, 0xF8, 0x19, 0xA9, 0x7C, 0x34, 0xF0,
+	0x95, 0xE5, 0x8C, 0x3A, 0x85, 0xDD, 0xD5, 0xBC, 0x91, 0xCD, 0x7F, 0x23, 0x24, 0x43, 0xCB, 0x95,
+	0x5C, 0xE7, 0x62, 0xB9, 0xFE, 0x1F, 0x4A, 0xF9, 0x05, 0x7F, 0xE0, 0x93, 0x1F, 0xB4, 0x4E, 0xDE,
+	0x3C, 0x6B, 0xE0, 0x9F, 0xF8, 0x0D, 0xED, 0xE6, 0x3F, 0xF4, 0x9A, 0xBE, 0xE5, 0xF8, 0xB1, 0xF1,
+	0x47, 0xC1, 0x9F, 0x07, 0xFC, 0x1D, 0x71, 0xE3, 0xFF, 0x00, 0x1F, 0xEA, 0x12, 0x5B, 0x69, 0x36,
+	0xB2, 0x46, 0x92, 0x4D, 0x1C, 0x2F, 0x2E, 0x1A, 0x47, 0xD8, 0x38, 0x4F, 0xF7, 0xAB, 0xCB, 0x17,
+	0xFE, 0x0A, 0x59, 0xFB, 0x22, 0x05, 0x01, 0xBC, 0x7B, 0x7E, 0x4F, 0x72, 0x34, 0x1B, 0x8E, 0x7F,
+	0xF1, 0xCA, 0xE8, 0x33, 0x3E, 0x6D, 0xFF, 0x00, 0x87, 0x4C, 0x7E, 0xD1, 0x3F, 0xF4, 0x3A, 0x78,
+	0x2B, 0xFF, 0x00, 0x03, 0x6F, 0x7F, 0xF9, 0x1E, 0x8F, 0xF8, 0x74, 0xC7, 0xED, 0x13, 0xFF, 0x00,
+	0x43, 0xA7, 0x82, 0xBF, 0xF0, 0x36, 0xF7, 0xFF, 0x00, 0x91, 0xEB, 0xE9, 0x2F, 0xF8, 0x79, 0x67,
+	0xEC, 0x87, 0xFF, 0x00, 0x43, 0xDE, 0xA1, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x37, 0x47, 0xFC,
+	0x3C, 0xB3, 0xF6, 0x43, 0xFF, 0x00, 0xA1, 0xEF, 0x50, 0xFF, 0x00, 0xC1, 0x0D, 0xC7, 0xFF, 0x00,
+	0x1B, 0xA0, 0x0F, 0x9B, 0x7F, 0xE1, 0xD3, 0x3F, 0xB4, 0x4E, 0x71, 0xFF, 0x00, 0x09, 0xA7, 0x82,
+	0xBF, 0xF0, 0x3A, 0xF7, 0xFF, 0x00, 0x91, 0xEB, 0x2B, 0xF6, 0x94, 0xFD, 0x9C, 0x3F, 0x6E, 0x0F,
+	0xD9, 0x93, 0xF6, 0x00, 0xF8, 0xA9, 0xF0, 0xAF, 0xF6, 0x76, 0xF0, 0xEE, 0x9B, 0xE2, 0x6F, 0x88,
+	0x1F, 0x12, 0xBE, 0xCF, 0xA3, 0xE9, 0xAD, 0xA0, 0xEB, 0x70, 0xDB, 0xAE, 0x9B, 0x65, 0x24, 0x72,
+	0x45, 0x77, 0x78, 0xEF, 0x7C, 0x60, 0x5C, 0x8B, 0x72, 0x63, 0x5D, 0x87, 0xCC, 0xF3, 0x24, 0x42,
+	0x38, 0x4A, 0xFA, 0xA4, 0x7F, 0xC1, 0x4A, 0x3F, 0x64, 0x99, 0x58, 0x2C, 0x7E, 0x3C, 0xBF, 0xFF,
+	0x00, 0xC1, 0x0D, 0xC7, 0xFF, 0x00, 0x11, 0x51, 0xF8, 0xCB, 0xE2, 0x66, 0x8F, 0xF1, 0x3A, 0x7B,
+	0x3F, 0x12, 0xF8, 0x72, 0xEA, 0x49, 0x34, 0xD9, 0xAC, 0xD2, 0x5B, 0x16, 0x92, 0x32, 0x9E, 0x60,
+	0x70, 0x08, 0x6D, 0xA7, 0x91, 0x90, 0x47, 0x07, 0x91, 0x5F, 0x8D, 0x78, 0xDD, 0xE2, 0x75, 0x4F,
+	0x0B, 0x78, 0x47, 0xFB, 0x42, 0x84, 0x63, 0x3C, 0x44, 0xE4, 0xA1, 0x4E, 0x33, 0xBD, 0x9B, 0xDE,
+	0x4E, 0xC9, 0xA7, 0x64, 0xBB, 0x34, 0x7A, 0xD9, 0x3E, 0x5D, 0xFD, 0xA1, 0x8C, 0xE5, 0xE8, 0xB5,
+	0x67, 0xF3, 0x5E, 0x7F, 0xE0, 0x82, 0xDF, 0xF0, 0x55, 0x8C, 0xF3, 0xFB, 0x2D, 0xAA, 0xFF, 0x00,
+	0xB3, 0xFF, 0x00, 0x09, 0xD6, 0x89, 0xC7, 0xE7, 0x78, 0x4F, 0xEA, 0x7E, 0xA6, 0x8F, 0xF8, 0x70,
+	0xBF, 0xFC, 0x15, 0x63, 0xFE, 0x8D, 0x75, 0x7F, 0xF0, 0xBA, 0xD0, 0xFF, 0x00, 0xF9, 0x32, 0xBF,
+	0xA3, 0x62, 0x0A, 0x9D, 0xA4, 0x51, 0x5F, 0xC6, 0x9F, 0xF1, 0x39, 0x1E, 0x23, 0xFF, 0x00, 0xD0,
+	0x26, 0x17, 0xFF, 0x00, 0x01, 0xAB, 0xFF, 0x00, 0xCB, 0x4F, 0xB5, 0x5C, 0x3B, 0x83, 0xFE, 0x66,
+	0x7F, 0x39, 0x3F, 0xF0, 0xE1, 0x7F, 0xF8, 0x2A, 0xC7, 0xFD, 0x1A, 0xEA, 0xFF, 0x00, 0xE1, 0x75,
+	0xA1, 0xFF, 0x00, 0xF2, 0x65, 0x1F, 0xF0, 0xE1, 0x7F, 0xF8, 0x2A, 0xC7, 0xFD, 0x1A, 0xEA, 0xFF,
+	0x00, 0xE1, 0x75, 0xA1, 0xFF, 0x00, 0xF2, 0x65, 0x7F, 0x46, 0xD4, 0x51, 0xFF, 0x00, 0x13, 0x91,
+	0xE2, 0x3F, 0xFD, 0x01, 0xE1, 0xBF, 0xF0, 0x1A, 0xBF, 0xFC, 0xB4, 0x7F, 0xEA, 0xE6, 0x0F, 0xF9,
+	0xA5, 0xF7, 0x9F, 0xCE, 0x4F, 0xFC, 0x38, 0x5B, 0xFE, 0x0A, 0xB1, 0xDB, 0xF6, 0x5C, 0x5F, 0xFC,
+	0x2E, 0xB4, 0x3F, 0xFE, 0x4C, 0xAF, 0x5A, 0xFD, 0x83, 0xFF, 0x00, 0xE0, 0x99, 0x1F, 0xB7, 0x47,
+	0xEC, 0x3D, 0xFB, 0x63, 0x7C, 0x37, 0xFD, 0xAA, 0xFF, 0x00, 0x69, 0x7F, 0x81, 0x0D, 0xA0, 0xF8,
+	0x23, 0xC1, 0xFE, 0x29, 0x86, 0xEB, 0xC4, 0x1A, 0xB4, 0x7E, 0x24, 0xD2, 0xAF, 0x3E, 0xCD, 0x16,
+	0x0C, 0x6A, 0x7C, 0xAB, 0x7B, 0xB3, 0x23, 0x65, 0x9E, 0x2E, 0x88, 0xDF, 0x8D, 0x7E, 0xEE, 0x57,
+	0x8A, 0xFF, 0x00, 0xC1, 0x40, 0xFF, 0x00, 0xE4, 0xD4, 0x7C, 0x45, 0xFF, 0x00, 0x5F, 0x16, 0x7F,
+	0xFA, 0x57, 0x0D, 0x7E, 0x8D, 0xE1, 0x1F, 0xD2, 0x6B, 0x8D, 0xB8, 0xF3, 0xC4, 0xAC, 0xAB, 0x87,
+	0xB1, 0xD8, 0x6A, 0x11, 0xA3, 0x8A, 0xAD, 0x1A, 0x73, 0x70, 0x8D, 0x45, 0x25, 0x17, 0xBF, 0x2D,
+	0xEA, 0x34, 0x9F, 0x6B, 0xA6, 0x7C, 0xA7, 0x1B, 0x61, 0xA3, 0xC3, 0xBC, 0x27, 0x8D, 0xCC, 0xB0,
+	0xED, 0xB9, 0xD1, 0xA7, 0x29, 0x25, 0x2D, 0x53, 0x6B, 0xBE, 0xCF, 0xF1, 0x3B, 0xA3, 0xFF, 0x00,
+	0x05, 0x43, 0xFD, 0x8D, 0x14, 0xED, 0xFF, 0x00, 0x85, 0x89, 0x7D, 0xFF, 0x00, 0x84, 0xFD, 0xE8,
+	0xFD, 0x3C, 0xBE, 0x29, 0x3F, 0xE1, 0xE8, 0x9F, 0xB1, 0xA7, 0xFD, 0x14, 0x4B, 0xEF, 0xFC, 0x10,
+	0xDE, 0xFF, 0x00, 0xF1, 0x15, 0xF9, 0x58, 0x7A, 0xD1, 0x5F, 0xEC, 0x6F, 0xFC, 0x41, 0xCE, 0x17,
+	0xFF, 0x00, 0x9F, 0x95, 0x7F, 0xF0, 0x28, 0xFF, 0x00, 0xF2, 0x27, 0xF0, 0x2F, 0xFC, 0x4C, 0x47,
+	0x1B, 0x2D, 0x3D, 0x95, 0x1F, 0xFC, 0x06, 0x5F, 0xFC, 0x91, 0xFA, 0xA7, 0xFF, 0x00, 0x0F, 0x44,
+	0xFD, 0x8D, 0x3F, 0xE8, 0xA2, 0x5F, 0x7F, 0xE0, 0x86, 0xF7, 0xFF, 0x00, 0x88, 0xA3, 0xFE, 0x1E,
+	0x89, 0xFB, 0x1A, 0x7F, 0xD1, 0x44, 0xBE, 0xFF, 0x00, 0xC1, 0x0D, 0xEF, 0xFF, 0x00, 0x11, 0x5F,
+	0x95, 0x94, 0x51, 0xFF, 0x00, 0x10, 0x73, 0x85, 0xFF, 0x00, 0xE7, 0xE5, 0x5F, 0xFC, 0x0A, 0x3F,
+	0xFC, 0x88, 0xFF, 0x00, 0xE2, 0x62, 0x38, 0xDB, 0xFE, 0x7D, 0x51, 0xFF, 0x00, 0xC0, 0x65, 0xFF,
+	0x00, 0xC9, 0x1F, 0xAA, 0x7F, 0xF0, 0xF4, 0x4F, 0xD8, 0xD3, 0xFE, 0x8A, 0x25, 0xF7, 0xFE, 0x08,
+	0x6F, 0x7F, 0xF8, 0x8A, 0xFC, 0xE0, 0xFF, 0x00, 0x83, 0x88, 0x7C, 0x75, 0xA3, 0xFE, 0xDF, 0x5E,
+	0x12, 0xF8, 0x55, 0xA3, 0x7E, 0xCA, 0xD1, 0x5C, 0xF8, 0x86, 0x6F, 0x0D, 0xEA, 0x9A, 0xB4, 0xDA,
+	0xC2, 0xC9, 0x19, 0xB1, 0xF2, 0x16, 0x58, 0xAD, 0x44, 0x67, 0xFD, 0x21, 0x90, 0x36, 0x4A, 0x49,
+	0xCD, 0x71, 0x74, 0x54, 0x4B, 0xC1, 0xAE, 0x19, 0x94, 0x6D, 0xED, 0x6A, 0xFF, 0x00, 0xE0, 0x51,
+	0xFF, 0x00, 0xE4, 0x4A, 0x87, 0xD2, 0x2F, 0x8D, 0xA3, 0x35, 0x27, 0x4A, 0x8B, 0xB7, 0xF7, 0x65,
+	0xFA, 0x49, 0x1F, 0x9D, 0x63, 0xF6, 0x11, 0xFD, 0xAA, 0x13, 0xE4, 0x3F, 0x09, 0xF1, 0xB7, 0x8C,
+	0x7F, 0x6D, 0x59, 0xF1, 0xF9, 0x5C, 0xD1, 0xFF, 0x00, 0x0C, 0x27, 0xFB, 0x53, 0xFF, 0x00, 0xD1,
+	0x28, 0xFF, 0x00, 0xCA, 0xD5, 0xA7, 0xFF, 0x00, 0x24, 0xD7, 0xE8, 0xA5, 0x15, 0xCF, 0xFF, 0x00,
+	0x10, 0x47, 0x85, 0xFF, 0x00, 0xE7, 0xED, 0x5F, 0xBE, 0x3F, 0xFC, 0x89, 0xD7, 0xFF, 0x00, 0x13,
+	0x2B, 0xC6, 0xDF, 0xF4, 0x0F, 0x43, 0xFF, 0x00, 0x01, 0x97, 0xFF, 0x00, 0x26, 0x7E, 0x75, 0xFF,
+	0x00, 0xC3, 0x09, 0xFE, 0xD4, 0xFF, 0x00, 0xF4, 0x4A, 0x3F, 0xF2, 0xB5, 0x69, 0xFF, 0x00, 0xC9,
+	0x34, 0x7F, 0xC3, 0x09, 0xFE, 0xD4, 0xFF, 0x00, 0xF4, 0x4A, 0x3F, 0xF2, 0xB5, 0x69, 0xFF, 0x00,
+	0xC9, 0x35, 0xFA, 0x29, 0x45, 0x1F, 0xF1, 0x04, 0x78, 0x5F, 0xFE, 0x7E, 0xD5, 0xFF, 0x00, 0xC0,
+	0xA3, 0xFF, 0x00, 0xC8, 0x87, 0xFC, 0x4C, 0xAF, 0x1B, 0x7F, 0xD0, 0x3D, 0x0F, 0xFC, 0x06, 0x5F,
+	0xFC, 0x99, 0xF9, 0xD7, 0xFF, 0x00, 0x0C, 0x27, 0xFB, 0x53, 0xFF, 0x00, 0xD1, 0x28, 0xFF, 0x00,
+	0xCA, 0xD5, 0xA7, 0xFF, 0x00, 0x24, 0xD7, 0xEB, 0x47, 0xFC, 0x1B, 0x5B, 0x63, 0xAC, 0xFE, 0xC8,
+	0x7E, 0x02, 0xF8, 0xB1, 0x61, 0xF1, 0xFF, 0x00, 0x47, 0x9B, 0x45, 0x6D, 0x73, 0x56, 0xD2, 0xA4,
+	0xD2, 0xE3, 0x8E, 0x55, 0xBB, 0xF3, 0xA3, 0x8A, 0x2B, 0x8F, 0x33, 0xFE, 0x3D, 0x59, 0xC2, 0xE1,
+	0xE5, 0x5E, 0x1B, 0x9F, 0x5A, 0xF2, 0xBA, 0xF7, 0x5F, 0xD9, 0x2B, 0xFE, 0x45, 0xED, 0x53, 0xFE,
+	0xC2, 0x11, 0xFF, 0x00, 0xE8, 0x35, 0xF8, 0x8F, 0xD2, 0x13, 0x87, 0x30, 0x7E, 0x13, 0xF8, 0x63,
+	0x88, 0xE2, 0x2C, 0xA6, 0x72, 0x9D, 0x6A, 0x72, 0x84, 0x52, 0xA9, 0x67, 0x1F, 0x79, 0xD9, 0xDD,
+	0x45, 0x45, 0xE8, 0xB6, 0xD5, 0x1F, 0x77, 0xE1, 0xE7, 0x8D, 0x9C, 0x4F, 0xC6, 0x5C, 0x51, 0x4B,
+	0x2C, 0xC6, 0x51, 0xA5, 0x18, 0x49, 0x49, 0xB7, 0x18, 0xC9, 0x3D, 0x17, 0x9C, 0x9F, 0xE4, 0x7E,
+	0x8B, 0xFF, 0x00, 0xC3, 0x5E, 0xFC, 0x0D, 0x6F, 0x9B, 0xFE, 0x12, 0x7B, 0x83, 0xEE, 0x74, 0xB9,
+	0x79, 0xFD, 0x07, 0xF2, 0x14, 0x7F, 0xC3, 0x5E, 0x7C, 0x0D, 0xFF, 0x00, 0xA1, 0x96, 0xE3, 0xFF,
+	0x00, 0x05, 0x72, 0xD7, 0xC7, 0xC9, 0xF7, 0x07, 0xD2, 0x96, 0xBF, 0xCE, 0x7F, 0xF8, 0x99, 0x8E,
+	0x3A, 0xFF, 0x00, 0x9F, 0x34, 0x7F, 0xF0, 0x19, 0x7F, 0xF2, 0x47, 0xF4, 0x77, 0x31, 0xF6, 0x07,
+	0xFC, 0x35, 0xE7, 0xC0, 0xDF, 0xFA, 0x19, 0x6E, 0x3F, 0xF0, 0x57, 0x2D, 0x1F, 0xF0, 0xD7, 0x9F,
+	0x03, 0x7F, 0xE8, 0x65, 0xB8, 0xFF, 0x00, 0xC1, 0x5C, 0xB5, 0xF1, 0xFD, 0x14, 0x7F, 0xC4, 0xCC,
+	0x71, 0xD7, 0xFC, 0xF9, 0xA3, 0xFF, 0x00, 0x80, 0xCB, 0xFF, 0x00, 0x92, 0x0E, 0x63, 0xEC, 0x0F,
+	0xF8, 0x6B, 0xCF, 0x81, 0xBF, 0xF4, 0x32, 0xDC, 0x7F, 0xE0, 0xAE, 0x5A, 0xFC, 0x7D, 0xFF, 0x00,
+	0x83, 0x82, 0x3F, 0x65, 0xCF, 0x8F, 0x3F, 0xB7, 0x47, 0xED, 0x93, 0xE1, 0x9F, 0x8B, 0x5F, 0xB3,
+	0x1F, 0x81, 0x24, 0xF1, 0x16, 0x83, 0xA7, 0xFC, 0x31, 0xB2, 0xD1, 0xEE, 0xAF, 0xA4, 0xD5, 0x2C,
+	0xEC, 0xF6, 0xDD, 0xA6, 0xA5, 0xA8, 0x4C, 0xC9, 0xE5, 0xDD, 0xDC, 0x44, 0xC3, 0x11, 0xDC, 0xC6,
+	0x37, 0x2A, 0xB7, 0xD4, 0xD7, 0xD8, 0x54, 0x51, 0x1F, 0xA4, 0xC7, 0x1C, 0x73, 0x5E, 0x54, 0x28,
+	0x3F, 0xFB, 0x76, 0x5F, 0xFC, 0x99, 0x50, 0xA9, 0x28, 0x4A, 0xE8, 0xFC, 0x51, 0x3F, 0xF0, 0x48,
+	0xFF, 0x00, 0xF8, 0x28, 0x41, 0x39, 0xFF, 0x00, 0x85, 0x04, 0xAB, 0xFE, 0xCF, 0xFC, 0x26, 0x1A,
+	0x63, 0x63, 0xF1, 0xFB, 0x58, 0xCF, 0xD7, 0x02, 0x8F, 0xF8, 0x74, 0x77, 0xFC, 0x14, 0x23, 0xFE,
+	0x88, 0x28, 0xFF, 0x00, 0xC2, 0xBB, 0x4C, 0xFF, 0x00, 0xE4, 0xCA, 0xFD, 0xAE, 0xA2, 0xAB, 0xFE,
+	0x26, 0x67, 0x8D, 0xBF, 0xE8, 0x1B, 0x0F, 0xFF, 0x00, 0x80, 0xCF, 0xFF, 0x00, 0x93, 0x37, 0xFA,
+	0xE5, 0x63, 0xF1, 0x47, 0xFE, 0x1D, 0x1D, 0xFF, 0x00, 0x05, 0x08, 0xFF, 0x00, 0xA2, 0x0A, 0x3F,
+	0xF0, 0xAE, 0xD3, 0x3F, 0xF9, 0x32, 0x8F, 0xF8, 0x74, 0x77, 0xFC, 0x14, 0x23, 0xFE, 0x88, 0x28,
+	0xFF, 0x00, 0xC2, 0xBB, 0x4C, 0xFF, 0x00, 0xE4, 0xCA, 0xFD, 0xAE, 0xA2, 0x8F, 0xF8, 0x99, 0x8E,
+	0x36, 0xFF, 0x00, 0xA0, 0x6C, 0x3F, 0xFE, 0x03, 0x3F, 0xFE, 0x4C, 0x3E, 0xB9, 0x5B, 0xB9, 0xF8,
+	0xA3, 0xFF, 0x00, 0x0E, 0x8E, 0xFF, 0x00, 0x82, 0x83, 0xFF, 0x00, 0xD1, 0x06, 0x5F, 0xFC, 0x2B,
+	0xB4, 0xCF, 0xFE, 0x4C, 0xAF, 0xDD, 0x2F, 0xF8, 0x23, 0x97, 0x8C, 0x74, 0xDF, 0xD9, 0x2B, 0xFE,
+	0x09, 0xBF, 0xF0, 0xEF, 0xE0, 0x1F, 0xC7, 0x7F, 0x3B, 0x45, 0xF1, 0x6F, 0x87, 0x53, 0x58, 0x6D,
+	0x5B, 0x4D, 0x55, 0x13, 0x88, 0x3C, 0xDD, 0x5E, 0xFA, 0xEA, 0x26, 0xF3, 0xA0, 0x2D, 0x0B, 0x66,
+	0x19, 0xA2, 0xE3, 0x25, 0xBD, 0xC9, 0xE6, 0xB9, 0xBA, 0x29, 0x3F, 0xA4, 0xC7, 0x1C, 0x7D, 0x9A,
+	0x14, 0x17, 0xFD, 0xBB, 0x3F, 0xFE, 0x4C, 0xCE, 0xA6, 0x22, 0xA5, 0x48, 0xD9, 0x9F, 0x60, 0x1F,
+	0xDA, 0xE7, 0xE0, 0x62, 0x1D, 0x8B, 0xE2, 0x3B, 0x80, 0x17, 0x80, 0x3F, 0xB2, 0xA6, 0xE3, 0xF3,
+	0xE7, 0xF3, 0xE6, 0x85, 0xFD, 0xAE, 0x3E, 0x06, 0xB1, 0x2B, 0xFF, 0x00, 0x09, 0x25, 0xC7, 0xAF,
+	0xFC, 0x82, 0xE5, 0xAF, 0x8F, 0xE8, 0xAD, 0xF0, 0x9F, 0x49, 0x2E, 0x3A, 0xC4, 0x62, 0x21, 0x4E,
+	0x54, 0xA8, 0xDA, 0x52, 0x8A, 0x76, 0x8C, 0xB6, 0x6D, 0x2B, 0x7C, 0x44, 0xD1, 0xFD, 0xE5, 0x68,
+	0x41, 0xEC, 0xD9, 0xF6, 0x00, 0xFD, 0xAF, 0xBE, 0x07, 0x01, 0x8F, 0xF8, 0x49, 0x2E, 0x3F, 0xF0,
+	0x56, 0xFF, 0x00, 0xFC, 0x45, 0x1F, 0xF0, 0xD7, 0xDF, 0x03, 0x7F, 0xE8, 0x64, 0xB8, 0xFF, 0x00,
+	0xC1, 0x5B, 0xFF, 0x00, 0xF1, 0xBA, 0xF8, 0xEC, 0xF5, 0xA2, 0xBF, 0xBB, 0x30, 0x91, 0x8D, 0x6C,
+	0x2D, 0x3A, 0x92, 0x5A, 0xCA, 0x29, 0xFD, 0xE9, 0x33, 0xF7, 0x6A, 0x5E, 0x1A, 0xE4, 0x35, 0x29,
+	0x46, 0x4E, 0x73, 0xBB, 0x49, 0xEE, 0xBF, 0xF9, 0x13, 0xEC, 0x4F, 0xF8, 0x6B, 0xEF, 0x81, 0xBF,
+	0xF4, 0x32, 0x5C, 0x7F, 0xE0, 0xAD, 0xFF, 0x00, 0xF8, 0xDD, 0x7F, 0x3B, 0xFF, 0x00, 0xB6, 0xC7,
+	0xFC, 0x13, 0x5B, 0xF6, 0xD8, 0xF8, 0xC3, 0xFB, 0x65, 0xFC, 0x5C, 0xF8, 0xB7, 0xF0, 0xFB, 0xE0,
+	0x9F, 0xDB, 0xB4, 0x0F, 0x14, 0xFC, 0x4E, 0xD7, 0xB5, 0x7D, 0x0E, 0xF9, 0xBC, 0x43, 0xA6, 0xC4,
+	0x6E, 0x2C, 0xEE, 0x75, 0x19, 0xE6, 0x86, 0x4D, 0x8F, 0x3A, 0xB2, 0x6E, 0x8D, 0xD4, 0xED, 0x60,
+	0x18, 0x67, 0x04, 0x03, 0xC5, 0x7E, 0xAE, 0x51, 0x5A, 0xCB, 0x0B, 0x4E, 0x4B, 0x53, 0x6A, 0x7E,
+	0x1A, 0xE4, 0x54, 0xDB, 0x6A, 0x73, 0xFB, 0xD7, 0xFF, 0x00, 0x22, 0x7E, 0x2A, 0xFF, 0x00, 0xC3,
+	0xA4, 0x3F, 0xE0, 0xA0, 0xFF, 0x00, 0xF4, 0x6F, 0xDF, 0xF9, 0x74, 0x69, 0x5F, 0xFC, 0x93, 0x47,
+	0xFC, 0x3A, 0x43, 0xFE, 0x0A, 0x0F, 0xFF, 0x00, 0x46, 0xFD, 0xFF, 0x00, 0x97, 0x46, 0x95, 0xFF,
+	0x00, 0xC9, 0x35, 0xFB, 0x55, 0x45, 0x47, 0xD4, 0xA9, 0x17, 0xFF, 0x00, 0x10, 0xE7, 0x25, 0xFF,
+	0x00, 0x9F, 0x93, 0xFB, 0xE3, 0xFF, 0x00, 0xC8, 0x9F, 0x8A, 0xBF, 0xF0, 0xE9, 0x0F, 0xF8, 0x28,
+	0x3F, 0xFD, 0x1B, 0xF7, 0xFE, 0x5D, 0x1A, 0x57, 0xFF, 0x00, 0x24, 0xD1, 0xFF, 0x00, 0x0E, 0x90,
+	0xFF, 0x00, 0x82, 0x83, 0xFF, 0x00, 0xD1, 0xBF, 0x7F, 0xE5, 0xD1, 0xA5, 0x7F, 0xF2, 0x4D, 0x7E,
+	0xD5, 0x51, 0x47, 0xD4, 0xA9, 0x07, 0xFC, 0x43, 0x9C, 0x9B, 0xFE, 0x7E, 0x4F, 0xEF, 0x8F, 0xFF,
+	0x00, 0x22, 0x7E, 0x2B, 0x8F, 0xF8, 0x24, 0x9F, 0xFC, 0x14, 0x27, 0x70, 0xD9, 0xF0, 0x03, 0x6B,
+	0x95, 0xCA, 0xB7, 0xFC, 0x25, 0x5A, 0x38, 0xC1, 0xC9, 0x50, 0xD9, 0xFB, 0x4E, 0xE6, 0xDB, 0x8F,
+	0xBA, 0xBF, 0x35, 0x7F, 0x4D, 0x9F, 0xF0, 0xD7, 0xDF, 0x02, 0xFF, 0x00, 0x83, 0xC4, 0x53, 0x05,
+	0xFE, 0x10, 0x34, 0xD7, 0x6C, 0x7E, 0x3B, 0x5B, 0x3F, 0x5C, 0x9F, 0xA9, 0xEB, 0x5F, 0x1D, 0xD1,
+	0x55, 0x1C, 0x2D, 0x38, 0xA2, 0x25, 0xE1, 0xAE, 0x47, 0x3B, 0x5E, 0x73, 0xFB, 0xD7, 0xFF, 0x00,
+	0x22, 0x7D, 0x89, 0xFF, 0x00, 0x0D, 0x7D, 0xF0, 0x37, 0xFE, 0x86, 0x4B, 0x8F, 0xFC, 0x15, 0xBF,
+	0xFF, 0x00, 0x1B, 0xA3, 0xFE, 0x1A, 0xFB, 0xE0, 0x6F, 0xFD, 0x0C, 0x97, 0x1F, 0xF8, 0x2B, 0x7F,
+	0xFE, 0x37, 0x5F, 0x1D, 0xD1, 0x5A, 0x7B, 0x0A, 0x64, 0xFF, 0x00, 0xC4, 0x32, 0xC8, 0x7F, 0x9E,
+	0x7F, 0x7A, 0xFF, 0x00, 0xE4, 0x4F, 0xB1, 0x3F, 0xE1, 0xAF, 0xBE, 0x06, 0xFF, 0x00, 0xD0, 0xC9,
+	0x71, 0xFF, 0x00, 0x82, 0xB7, 0xFF, 0x00, 0xE3, 0x74, 0x7F, 0xC3, 0x5F, 0x7C, 0x0D, 0xFF, 0x00,
+	0xA1, 0x92, 0xE3, 0xFF, 0x00, 0x05, 0x6F, 0xFF, 0x00, 0xC6, 0xEB, 0xE3, 0xBA, 0x28, 0xF6, 0x14,
+	0xC5, 0xFF, 0x00, 0x10, 0xCB, 0x21, 0xFE, 0x79, 0xFD, 0xEB, 0xFF, 0x00, 0x91, 0x3C, 0xC7, 0xFE,
+	0x0E, 0x4A, 0xD4, 0x57, 0xF6, 0xAB, 0xFD, 0x90, 0x7C, 0x2B, 0x61, 0xF0, 0x42, 0xDA, 0x4D, 0x66,
+	0x4F, 0x0B, 0xF8, 0xD9, 0x35, 0x3D, 0x79, 0x64, 0x92, 0x2B, 0x5F, 0xB2, 0xD9, 0xFD, 0x92, 0x78,
+	0x8B, 0x6E, 0xB8, 0x74, 0xDD, 0x97, 0x9D, 0x3E, 0x54, 0xE6, 0xBF, 0x10, 0x4F, 0xC0, 0xCF, 0x8A,
+	0x39, 0xFD, 0xEF, 0x85, 0xF7, 0x37, 0xF1, 0x37, 0xDB, 0xA1, 0x5C, 0x9F, 0xA1, 0x90, 0x91, 0xF4,
+	0x24, 0x9F, 0x73, 0x5F, 0xB7, 0x9F, 0xB6, 0xA7, 0xFC, 0x9A, 0xEF, 0x8B, 0xBF, 0xEC, 0x1C, 0xBF,
+	0xFA, 0x3A, 0x2A, 0xFC, 0xC7, 0x5F, 0xBB, 0xF8, 0x57, 0xC2, 0xF1, 0x26, 0x6D, 0x88, 0xCA, 0xF1,
+	0x91, 0xA7, 0x49, 0x26, 0x9A, 0xBE, 0xA8, 0xFD, 0x97, 0xC3, 0x9F, 0xA3, 0xBF, 0x06, 0x71, 0x56,
+	0x57, 0x52, 0xBE, 0x26, 0xB5, 0x68, 0xB8, 0xCA, 0xD6, 0x8C, 0xA0, 0x93, 0xD2, 0xF7, 0xD6, 0x0C,
+	0xF9, 0xEF, 0xFE, 0x14, 0x5F, 0xC4, 0xEF, 0xFA, 0x15, 0x7F, 0xF2, 0xA1, 0x6F, 0xFF, 0x00, 0xC5,
+	0xD1, 0xFF, 0x00, 0x0A, 0x2F, 0xE2, 0x7F, 0xFD, 0x0A, 0x9F, 0xF9, 0x50, 0xB7, 0xFF, 0x00, 0xE2,
+	0xEB, 0xE8, 0x4A, 0x2B, 0xE7, 0x7F, 0xD6, 0xAC, 0xC3, 0xB4, 0x7E, 0xE7, 0xFE, 0x67, 0xE8, 0x7F,
+	0xF1, 0x29, 0xFE, 0x1F, 0xFF, 0x00, 0xD0, 0x56, 0x23, 0xFF, 0x00, 0x02, 0xA7, 0xFF, 0x00, 0xCA,
+	0xCF, 0x9E, 0xFF, 0x00, 0xE1, 0x45, 0xFC, 0x4F, 0xFF, 0x00, 0xA1, 0x53, 0xFF, 0x00, 0x2A, 0x16,
+	0xFF, 0x00, 0xFC, 0x5D, 0x1F, 0xF0, 0xA2, 0xFE, 0x27, 0xFF, 0x00, 0xD0, 0xA9, 0xFF, 0x00, 0x95,
+	0x0B, 0x7F, 0xFE, 0x2E, 0xBE, 0x84, 0xA2, 0x8F, 0xF5, 0xAB, 0x31, 0xED, 0x1F, 0xB9, 0xFF, 0x00,
+	0x98, 0x7F, 0xC4, 0xA7, 0xF8, 0x7F, 0xFF, 0x00, 0x41, 0x58, 0x9F, 0xFC, 0x0A, 0x9F, 0xFF, 0x00,
+	0x2B, 0x3E, 0x98, 0xFF, 0x00, 0x82, 0x00, 0xFE, 0xD1, 0x3F, 0x0B, 0x3F, 0x62, 0x0B, 0x2F, 0x8E,
+	0x9A, 0x6F, 0xED, 0x2F, 0xAD, 0xCD, 0xE1, 0xDF, 0xF8, 0x4F, 0x7C, 0x25, 0x63, 0xA7, 0xF8, 0x76,
+	0x48, 0xEC, 0xA4, 0xBD, 0x59, 0x66, 0x8F, 0xED, 0x88, 0xC5, 0xC5, 0xBA, 0xB9, 0x50, 0x1A, 0x78,
+	0xF9, 0xAF, 0x66, 0x7F, 0xDA, 0x53, 0xF6, 0x55, 0x0D, 0x8F, 0xF8, 0x69, 0x7D, 0x05, 0xBD, 0xC6,
+	0x87, 0xAD, 0x7F, 0xF2, 0xBC, 0xFF, 0x00, 0x33, 0xF5, 0x35, 0xF0, 0x0D, 0x15, 0xA4, 0x78, 0xBB,
+	0x32, 0x8F, 0xD9, 0x8F, 0xDC, 0xFF, 0x00, 0xCC, 0x99, 0x7D, 0x12, 0xFC, 0x3A, 0x93, 0xBC, 0xAB,
+	0xD7, 0x7F, 0xF6, 0xF4, 0x3F, 0x48, 0x23, 0xEF, 0xEF, 0xF8, 0x69, 0x4F, 0xD9, 0x57, 0xFE, 0x8E,
+	0x5B, 0x41, 0xFF, 0x00, 0xC1, 0x16, 0xB5, 0xFF, 0x00, 0xCA, 0xEA, 0x3F, 0xE1, 0xA5, 0x3F, 0x65,
+	0x5F, 0xFA, 0x39, 0x6D, 0x07, 0xFF, 0x00, 0x04, 0x5A, 0xD7, 0xFF, 0x00, 0x2B, 0xAB, 0xE0, 0x1A,
+	0x28, 0xFF, 0x00, 0x5B, 0xB3, 0x2E, 0xD1, 0xFB, 0x83, 0xFE, 0x25, 0x2B, 0xC3, 0x7F, 0xF9, 0xFD,
+	0x88, 0xFF, 0x00, 0xC0, 0xE3, 0xFF, 0x00, 0xC8, 0x1F, 0x7F, 0x7F, 0xC3, 0x4A, 0x7E, 0xCA, 0xBF,
+	0xF4, 0x72, 0xDA, 0x0F, 0xFE, 0x08, 0xB5, 0xAF, 0xFE, 0x57, 0x57, 0xAD, 0xFE, 0xC5, 0xDF, 0xF0,
+	0x50, 0xDF, 0xD8, 0x9F, 0xF6, 0x72, 0xF8, 0xBF, 0x27, 0x8F, 0xBC, 0x6B, 0xF1, 0xFE, 0xCE, 0xEA,
+	0xCE, 0x4D, 0x1E, 0x5B, 0x44, 0x8F, 0x4B, 0xF0, 0xDE, 0xB3, 0x24, 0xBB, 0x9A, 0x44, 0x7C, 0x9F,
+	0x32, 0xC9, 0x06, 0x3E, 0x4F, 0x5A, 0xFC, 0xA6, 0xA2, 0x8F, 0xF5, 0xBB, 0x32, 0xFE, 0x58, 0xFD,
+	0xDF, 0xF0, 0x43, 0xFE, 0x25, 0x2B, 0xC3, 0x7F, 0xF9, 0xFD, 0x88, 0xFF, 0x00, 0xC0, 0xE3, 0xFF,
+	0x00, 0xC8, 0x1D, 0x47, 0xFC, 0x16, 0x4E, 0xF2, 0x4F, 0xDB, 0x43, 0xFE, 0x0A, 0x3B, 0xF1, 0x2B,
+	0xF6, 0x9C, 0xFD, 0x9F, 0xAC, 0x64, 0xD7, 0x3C, 0x1D, 0xAE, 0x4D, 0xA2, 0xA5, 0x8E, 0xA5, 0x3E,
+	0x2D, 0x1A, 0x66, 0x8F, 0x45, 0xB6, 0xB7, 0x65, 0x11, 0xCC, 0xC2, 0x41, 0x89, 0x2D, 0x64, 0xE7,
+	0x00, 0x7B, 0x0A, 0xF9, 0x77, 0xFE, 0x19, 0xCB, 0xE3, 0x3F, 0x7F, 0x07, 0x7D, 0x73, 0xA9, 0x5B,
+	0x9F, 0xD7, 0x7F, 0x35, 0xF5, 0x07, 0x85, 0x3F, 0xE4, 0x56, 0xD4, 0x7F, 0xEC, 0x21, 0x67, 0xFF,
+	0x00, 0xA2, 0xEE, 0x29, 0xEB, 0xDF, 0xE9, 0x5F, 0xD3, 0x5E, 0x1D, 0xF0, 0x1E, 0x53, 0xC5, 0xDC,
+	0x2B, 0x4B, 0x33, 0xC6, 0x4E, 0x71, 0x9C, 0xDB, 0xBA, 0x8B, 0x49, 0x2B, 0x3E, 0x97, 0x4D, 0xFE,
+	0x27, 0xF9, 0x8B, 0xF4, 0x84, 0xE2, 0x0C, 0x57, 0x84, 0xBE, 0x29, 0x63, 0x38, 0x63, 0x28, 0x84,
+	0x67, 0x42, 0x8F, 0x2F, 0x2B, 0xA9, 0x77, 0x3F, 0x79, 0x5D, 0xDD, 0xC5, 0xC5, 0x3F, 0xB8, 0xF9,
+	0x73, 0xFE, 0x19, 0xCF, 0xE3, 0x37, 0xFD, 0x09, 0xDF, 0xF9, 0x50, 0xB7, 0xFF, 0x00, 0xE3, 0x94,
+	0x7F, 0xC3, 0x39, 0xFC, 0x66, 0xFF, 0x00, 0xA1, 0x3B, 0xFF, 0x00, 0x2A, 0x16, 0xFF, 0x00, 0xFC,
+	0x72, 0xBE, 0xA2, 0xA2, 0xBE, 0xDB, 0xFE, 0x20, 0xEF, 0x0D, 0x7F, 0xCF, 0xDA, 0xBF, 0xF8, 0x14,
+	0x7F, 0xF9, 0x13, 0xF1, 0x2F, 0xF8, 0x8D, 0x5C, 0x4D, 0xFF, 0x00, 0x3E, 0xA9, 0x7D, 0xD2, 0xFF,
+	0x00, 0xE4, 0x8F, 0x97, 0x7F, 0xE1, 0x9C, 0xFE, 0x33, 0x7F, 0xD0, 0x9D, 0xFF, 0x00, 0x95, 0x0B,
+	0x7F, 0xFE, 0x39, 0x47, 0xFC, 0x33, 0x9F, 0xC6, 0x6F, 0xFA, 0x13, 0xBF, 0xF2, 0xA1, 0x6F, 0xFF,
+	0x00, 0xC7, 0x2B, 0xEA, 0x2A, 0x28, 0xFF, 0x00, 0x88, 0x3B, 0xC3, 0x5F, 0xF3, 0xF6, 0xAF, 0xFE,
+	0x05, 0x1F, 0xFE, 0x44, 0x5F, 0xF1, 0x1A, 0x78, 0x9B, 0xFE, 0x7D, 0x52, 0xFB, 0xA5, 0xFF, 0x00,
+	0xC9, 0x1F, 0x6E, 0xFF, 0x00, 0xC1, 0x17, 0x2D, 0x3E, 0x3D, 0xFE, 0xD6, 0xBF, 0xB2, 0x6D, 0xBF,
+	0xEC, 0x4D, 0xE2, 0x7B, 0xDD, 0x2F, 0x4F, 0xD6, 0xBE, 0x13, 0xEA, 0x57, 0x9A, 0x8F, 0x87, 0xE4,
+	0xF1, 0x06, 0xA8, 0x71, 0x79, 0xA2, 0x5E, 0xEC, 0xFD, 0xC2, 0x88, 0x15, 0xDB, 0x16, 0xD7, 0x3B,
+	0x98, 0x97, 0xF9, 0x76, 0x5C, 0xC3, 0xB7, 0x8C, 0x57, 0xD9, 0x23, 0xFE, 0x09, 0x35, 0xFB, 0x44,
+	0xB7, 0x27, 0xC6, 0x9E, 0x0C, 0xE7, 0x9F, 0x9A, 0xFE, 0xF4, 0x9F, 0xC4, 0x9B, 0x7C, 0x9A, 0xFC,
+	0xC3, 0xFD, 0x80, 0x3F, 0x69, 0xAB, 0xCF, 0xD9, 0x1F, 0xF6, 0xAF, 0xF0, 0x87, 0xC6, 0x85, 0x92,
+	0x4F, 0xEC, 0xFB, 0x4B, 0xF1, 0x69, 0xE2, 0x28, 0xA2, 0x5C, 0x99, 0xF4, 0xD9, 0xC6, 0xC9, 0x94,
+	0x2F, 0xF1, 0x14, 0x5C, 0xCA, 0x3F, 0xDB, 0x8C, 0x57, 0xEE, 0x55, 0xBF, 0xFC, 0x14, 0xBB, 0xF6,
+	0x41, 0x96, 0x18, 0xE5, 0x8B, 0xC7, 0xD7, 0xAC, 0xAC, 0xA0, 0xAB, 0x26, 0x87, 0x39, 0x52, 0x31,
+	0xC1, 0x18, 0x4C, 0x63, 0xE9, 0xC5, 0x7E, 0x5F, 0xC6, 0xFC, 0x27, 0x1E, 0x17, 0xC7, 0xC2, 0x14,
+	0x6F, 0x2A, 0x53, 0x57, 0x8B, 0x93, 0xBB, 0xBA, 0xDD, 0x5F, 0xC8, 0xFD, 0x47, 0x81, 0xF8, 0xB2,
+	0x5C, 0x55, 0x81, 0x9C, 0xEB, 0x28, 0xC6, 0xAC, 0x1D, 0xA4, 0xA2, 0xAC, 0xAC, 0xF6, 0x69, 0x5F,
+	0xA9, 0xF3, 0x8F, 0xFC, 0x3A, 0x63, 0xF6, 0x89, 0xFF, 0x00, 0xA1, 0xD3, 0xC1, 0x5F, 0xF8, 0x1B,
+	0x7B, 0xFF, 0x00, 0xC8, 0xF4, 0x7F, 0xC3, 0xA6, 0x3F, 0x68, 0x9F, 0xFA, 0x1D, 0x3C, 0x15, 0xFF,
+	0x00, 0x81, 0xB7, 0xBF, 0xFC, 0x8F, 0x5F, 0x49, 0x0F, 0xF8, 0x29, 0x67, 0xEC, 0x87, 0xFF, 0x00,
+	0x43, 0xDE, 0xA1, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x37, 0x47, 0xFC, 0x3C, 0xB3, 0xF6, 0x43,
+	0xFF, 0x00, 0xA1, 0xEF, 0x50, 0xFF, 0x00, 0xC1, 0x0D, 0xC7, 0xFF, 0x00, 0x1B, 0xAF, 0x89, 0x3E,
+	0xDC, 0xF9, 0xB7, 0xFE, 0x1D, 0x31, 0xFB, 0x44, 0xFF, 0x00, 0xD0, 0xE9, 0xE0, 0xAF, 0xFC, 0x0D,
+	0xBD, 0xFF, 0x00, 0xE4, 0x7A, 0xFA, 0xFF, 0x00, 0xF6, 0x45, 0xF8, 0x3D, 0xE2, 0x6F, 0x80, 0xBF,
+	0x03, 0xF4, 0xDF, 0x86, 0x5E, 0x31, 0xD4, 0x2C, 0x6E, 0x2F, 0xAC, 0xEE, 0x2E, 0x5E, 0x49, 0xB4,
+	0xDD, 0xDE, 0x4E, 0xD9, 0x26, 0x66, 0x00, 0x16, 0x00, 0x93, 0xCF, 0x52, 0x01, 0xF5, 0x03, 0xA5,
+	0x72, 0x5F, 0xF0, 0xF2, 0xCF, 0xD9, 0x0F, 0xFE, 0x87, 0xBD, 0x43, 0xFF, 0x00, 0x04, 0x37, 0x1F,
+	0xFC, 0x6E, 0xBD, 0x5B, 0xE1, 0x5F, 0xC5, 0x6F, 0x04, 0x7C, 0x68, 0xF0, 0x6C, 0x3E, 0x3E, 0xF0,
+	0x05, 0xFC, 0x97, 0x7A, 0x65, 0xCC, 0x92, 0x2D, 0xBC, 0xF2, 0xDB, 0x98, 0xFE, 0x68, 0xDB, 0x6B,
+	0x02, 0x0F, 0x23, 0x91, 0xDE, 0x80, 0x3C, 0x3B, 0xF6, 0x8D, 0xFD, 0x9A, 0xBE, 0x28, 0x7C, 0x4D,
+	0xF8, 0xA3, 0x75, 0xE2, 0xAF, 0x0C, 0x5B, 0xD9, 0xBD, 0xAC, 0xF6, 0xD0, 0xC7, 0x10, 0xB8, 0xBA,
+	0x28, 0xDB, 0x95, 0x7E, 0x6A, 0xE1, 0x87, 0xEC, 0x55, 0xF1, 0xC4, 0x8C, 0xC7, 0xA6, 0x69, 0xBB,
+	0x7A, 0xAE, 0x35, 0x0C, 0xF1, 0x5F, 0x40, 0x7C, 0x4B, 0xFD, 0xA8, 0xBE, 0x1B, 0x7C, 0x30, 0xF1,
+	0x34, 0xFE, 0x15, 0xF1, 0x54, 0x7A, 0x87, 0xDA, 0xAD, 0xE2, 0x59, 0x65, 0x36, 0xB6, 0xBB, 0x95,
+	0x15, 0xBE, 0xEF, 0x3B, 0xC6, 0x7F, 0x2A, 0xC5, 0x3F, 0xB6, 0xF7, 0xC1, 0x55, 0x3B, 0x5C, 0x6A,
+	0xFB, 0xBF, 0x88, 0x7D, 0x87, 0xFF, 0x00, 0xB3, 0xAF, 0xE5, 0x9E, 0x29, 0xE0, 0x3F, 0x04, 0x73,
+	0x0E, 0x20, 0xC4, 0xE2, 0x33, 0x3C, 0xCB, 0x93, 0x11, 0x29, 0xB7, 0x38, 0xFB, 0x58, 0xAB, 0x4B,
+	0xB5, 0xAC, 0x7E, 0x89, 0x96, 0x67, 0x9C, 0x65, 0x87, 0xC0, 0xD3, 0x86, 0x1B, 0x0F, 0x78, 0x24,
+	0x92, 0x7C, 0x8D, 0xDD, 0x77, 0xDC, 0xF1, 0x9F, 0xF8, 0x62, 0x9F, 0x8E, 0x83, 0x8F, 0xEC, 0xCD,
+	0x3F, 0xFF, 0x00, 0x03, 0x8D, 0x1F, 0xF0, 0xC5, 0x5F, 0x1C, 0xFF, 0x00, 0xE8, 0x19, 0xA7, 0xFF,
+	0x00, 0xE0, 0x71, 0xAF, 0x66, 0xFF, 0x00, 0x86, 0xDF, 0xF8, 0x25, 0xE9, 0xAC, 0x7F, 0xE0, 0x0F,
+	0xFF, 0x00, 0x67, 0x47, 0xFC, 0x36, 0xFF, 0x00, 0xC1, 0x2F, 0x4D, 0x63, 0xFF, 0x00, 0x00, 0x7F,
+	0xFB, 0x3A, 0xF9, 0xFF, 0x00, 0xF8, 0x86, 0xBF, 0x47, 0x9F, 0xFA, 0x1B, 0x7F, 0xE5, 0x68, 0xFF,
+	0x00, 0x91, 0xDF, 0xFE, 0xB1, 0x71, 0xD7, 0xFD, 0x03, 0x7F, 0xE4, 0x8F, 0xFC, 0xCF, 0x19, 0xFF,
+	0x00, 0x86, 0x2A, 0xF8, 0xE7, 0xFF, 0x00, 0x40, 0xDD, 0x3F, 0xFF, 0x00, 0x03, 0x8D, 0x7D, 0x65,
+	0xF0, 0xD7, 0x43, 0xBF, 0xF0, 0xCF, 0xC3, 0xCD, 0x07, 0xC3, 0x5A, 0xA2, 0xAA, 0xDD, 0x69, 0xFA,
+	0x35, 0xB5, 0xBD, 0xC0, 0x46, 0xCA, 0x87, 0x48, 0x95, 0x58, 0x03, 0xDC, 0x64, 0x1A, 0xF3, 0x1F,
+	0xF8, 0x6D, 0xFF, 0x00, 0x82, 0x79, 0xE3, 0xFB, 0x63, 0xFF, 0x00, 0x00, 0x7F, 0xFB, 0x3A, 0xF5,
+	0xEF, 0x0C, 0x6B, 0xD6, 0x1E, 0x28, 0xF0, 0xE6, 0x9F, 0xE2, 0x6D, 0x2F, 0x77, 0xD9, 0xB5, 0x0B,
+	0x38, 0xEE, 0x6D, 0xFC, 0xC5, 0xDA, 0xDB, 0x1D, 0x03, 0x0C, 0x8E, 0xC7, 0x06, 0xBF, 0x56, 0xF0,
+	0xA7, 0x85, 0xBC, 0x34, 0xC8, 0x73, 0x0C, 0x4D, 0x4E, 0x18, 0xC5, 0xFB, 0x79, 0xCA, 0x11, 0x53,
+	0x5C, 0xF1, 0x95, 0xA2, 0x9D, 0xD3, 0xD1, 0x2B, 0x5D, 0xF5, 0x3E, 0x6B, 0x89, 0xB3, 0x4E, 0x20,
+	0xC7, 0xD1, 0xA7, 0x1C, 0xCA, 0x97, 0x24, 0x53, 0x7C, 0xBE, 0xED, 0xB5, 0xFB, 0xCF, 0x8C, 0x7F,
+	0x68, 0x3F, 0xF8, 0x26, 0xF7, 0xC7, 0x1F, 0x8B, 0x1F, 0x1A, 0xFC, 0x45, 0xF1, 0x1B, 0xC3, 0xBE,
+	0x29, 0xF0, 0xAD, 0xBD, 0x9E, 0xAB, 0xA9, 0x1B, 0x9B, 0x58, 0xB5, 0x0B, 0xEB, 0xA1, 0x2A, 0xAE,
+	0xDD, 0xBD, 0x16, 0x02, 0x01, 0xC7, 0x60, 0x48, 0xF7, 0x35, 0xC6, 0xFF, 0x00, 0xC3, 0xA5, 0xFF,
+	0x00, 0x68, 0x81, 0xC2, 0xF8, 0xD7, 0xC1, 0x67, 0xFD, 0xEB, 0xEB, 0xDC, 0xFF, 0x00, 0xE9, 0x3D,
+	0x7D, 0x55, 0xE3, 0x9F, 0xDB, 0xCB, 0xF6, 0x6A, 0xF8, 0x6F, 0xE3, 0x2B, 0xEF, 0x01, 0xF8, 0xAF,
+	0xC6, 0x57, 0x56, 0xFA, 0x8E, 0x99, 0x75, 0xE4, 0xDE, 0x42, 0xBA, 0x4C, 0xEC, 0x03, 0x1C, 0xF1,
+	0x90, 0x98, 0x3C, 0xF7, 0x15, 0x8E, 0xBF, 0xF0, 0x52, 0xDF, 0xD9, 0x10, 0x8C, 0xB7, 0x8E, 0xEF,
+	0xF3, 0xFF, 0x00, 0x60, 0x1B, 0x8F, 0xFE, 0x37, 0x5F, 0xB8, 0x1F, 0x22, 0x7C, 0xDB, 0xFF, 0x00,
+	0x0E, 0x98, 0xFD, 0xA2, 0x7F, 0xE8, 0x74, 0xF0, 0x57, 0xFE, 0x06, 0xDE, 0xFF, 0x00, 0xF2, 0x3D,
+	0x1F, 0xF0, 0xE9, 0x8F, 0xDA, 0x27, 0xFE, 0x87, 0x4F, 0x05, 0x7F, 0xE0, 0x6D, 0xEF, 0xFF, 0x00,
+	0x23, 0xD7, 0xD2, 0x5F, 0xF0, 0xF2, 0xCF, 0xD9, 0x0F, 0xFE, 0x87, 0xBD, 0x43, 0xFF, 0x00, 0x04,
+	0x37, 0x1F, 0xFC, 0x6E, 0x8F, 0xF8, 0x79, 0x67, 0xEC, 0x87, 0xFF, 0x00, 0x43, 0xDE, 0xA1, 0xFF,
+	0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x37, 0x40, 0x1F, 0x36, 0xFF, 0x00, 0xC3, 0xA6, 0x3F, 0x68, 0x9F,
+	0xFA, 0x1D, 0x3C, 0x15, 0xFF, 0x00, 0x81, 0xB7, 0xBF, 0xFC, 0x8F, 0x5F, 0x49, 0x7E, 0xC2, 0x5F,
+	0xB3, 0x7F, 0x8E, 0xBF, 0x66, 0x3F, 0x0E, 0xF8, 0x93, 0xC2, 0xFE, 0x3D, 0xD5, 0xF4, 0x8B, 0xCB,
+	0x8B, 0xFB, 0xCB, 0x7B, 0xB8, 0x9F, 0x49, 0x9A, 0x56, 0x40, 0xBB, 0x59, 0x30, 0x7C, 0xC8, 0xD0,
+	0xE7, 0xE5, 0xF7, 0xA3, 0xFE, 0x1E, 0x59, 0xFB, 0x21, 0xFF, 0x00, 0xD0, 0xF7, 0xA8, 0x7F, 0xE0,
+	0x86, 0xE3, 0xFF, 0x00, 0x8D, 0xD7, 0x79, 0xF0, 0x3B, 0xE3, 0xD7, 0xC3, 0x4F, 0xDA, 0x0D, 0x75,
+	0x7F, 0x12, 0xFC, 0x2E, 0xD6, 0xA6, 0xBE, 0xB6, 0xB1, 0x30, 0x5B, 0x4E, 0xD3, 0x5A, 0x49, 0x06,
+	0x24, 0x1E, 0x63, 0x81, 0x87, 0xC7, 0x66, 0xEA, 0x28, 0x03, 0xC1, 0xFF, 0x00, 0x6C, 0xBF, 0xD8,
+	0x77, 0xE2, 0xC7, 0xED, 0x29, 0xF1, 0x9F, 0xFE, 0x13, 0xCF, 0x02, 0xEB, 0xFE, 0x1D, 0xB4, 0xB3,
+	0x83, 0x4B, 0x8A, 0xCA, 0x45, 0xD5, 0xAE, 0x67, 0x57, 0x2E, 0x8C, 0xCD, 0xC7, 0x97, 0x0B, 0x7F,
+	0x7F, 0xD6, 0xBC, 0xA7, 0xFE, 0x1D, 0x31, 0xFB, 0x44, 0xFF, 0x00, 0xD0, 0xE9, 0xE0, 0xAF, 0xFC,
+	0x0D, 0xBD, 0xFF, 0x00, 0xE4, 0x7A, 0xFA, 0xD3, 0xE2, 0xA7, 0xED, 0x7F, 0xF0, 0x2F, 0xE0, 0x37,
+	0x8C, 0xA6, 0xF0, 0x77, 0xC4, 0xEF, 0x15, 0x5C, 0x59, 0xDF, 0x49, 0x14, 0x77, 0x31, 0xC3, 0x16,
+	0x9B, 0x3C, 0xB9, 0x8D, 0xD4, 0x8E, 0xAA, 0x08, 0xEA, 0x8D, 0x5C, 0xEF, 0xFC, 0x3C, 0xB3, 0xF6,
+	0x43, 0xFF, 0x00, 0xA1, 0xEF, 0x50, 0xFF, 0x00, 0xC1, 0x0D, 0xC7, 0xFF, 0x00, 0x1B, 0xA0, 0x0F,
+	0x9B, 0x7F, 0xE1, 0xD3, 0x1F, 0xB4, 0x4F, 0xFD, 0x0E, 0x9E, 0x0A, 0xFF, 0x00, 0xC0, 0xDB, 0xDF,
+	0xFE, 0x47, 0xA3, 0xFE, 0x1D, 0x31, 0xFB, 0x44, 0xFF, 0x00, 0xD0, 0xE9, 0xE0, 0xAF, 0xFC, 0x0D,
+	0xBD, 0xFF, 0x00, 0xE4, 0x7A, 0xFA, 0x4B, 0xFE, 0x1E, 0x59, 0xFB, 0x21, 0xFF, 0x00, 0xD0, 0xF7,
+	0xA8, 0x7F, 0xE0, 0x86, 0xE3, 0xFF, 0x00, 0x8D, 0xD1, 0xFF, 0x00, 0x0F, 0x2C, 0xFD, 0x90, 0xFF,
+	0x00, 0xE8, 0x7B, 0xD4, 0x3F, 0xF0, 0x43, 0x71, 0xFF, 0x00, 0xC6, 0xE8, 0x03, 0xE6, 0xC7, 0xFF,
+	0x00, 0x82, 0x4D, 0x7E, 0xD1, 0x4A, 0xBB, 0x97, 0xC6, 0xBE, 0x0B, 0xFF, 0x00, 0x80, 0xEA, 0x17,
+	0xA3, 0xF5, 0xFB, 0x29, 0xFE, 0x5F, 0xE3, 0x5F, 0x47, 0xFE, 0xC1, 0x9F, 0xB2, 0xDF, 0x8F, 0xFF,
+	0x00, 0x65, 0xED, 0x0B, 0xC4, 0xD6, 0x5E, 0x3E, 0xD5, 0x74, 0x5B, 0xA9, 0x75, 0x7B, 0xAB, 0x79,
+	0x20, 0x7D, 0x1E, 0x69, 0x19, 0x00, 0x8C, 0x48, 0xA4, 0x31, 0x78, 0xD0, 0xE7, 0xE6, 0x1D, 0xAA,
+	0x47, 0xFF, 0x00, 0x82, 0x94, 0xFE, 0xC8, 0x72, 0x8F, 0x2F, 0xFE, 0x13, 0xCB, 0xFF, 0x00, 0x98,
+	0x8C, 0xFF, 0x00, 0xC4, 0x8E, 0xE8, 0x71, 0x9E, 0x7E, 0xEC, 0x79, 0xAF, 0x40, 0xF8, 0x23, 0xFB,
+	0x45, 0xFC, 0x2C, 0xFD, 0xA1, 0xAC, 0x75, 0x2B, 0xDF, 0x85, 0x7A, 0xD4, 0xD7, 0xC9, 0xA5, 0xB4,
+	0x2B, 0x78, 0xD3, 0x59, 0xC9, 0x6F, 0x87, 0x70, 0x59, 0x47, 0xCE, 0x01, 0x39, 0x0B, 0xD6, 0x80,
+	0x3C, 0x0F, 0xF6, 0xCB, 0xFD, 0x87, 0x7E, 0x2C, 0x7E, 0xD2, 0x9F, 0x19, 0xFF, 0x00, 0xE1, 0x3C,
+	0xF0, 0x2E, 0xBF, 0xE1, 0xDB, 0x4B, 0x38, 0x34, 0xB8, 0xAC, 0xA4, 0x5D, 0x5A, 0xE6, 0x75, 0x72,
+	0xE8, 0xCC, 0xDC, 0x79, 0x70, 0xB7, 0xF7, 0xFD, 0x6B, 0xCA, 0x7F, 0xE1, 0xD3, 0x1F, 0xB4, 0x4F,
+	0xFD, 0x0E, 0x9E, 0x0A, 0xFF, 0x00, 0xC0, 0xDB, 0xDF, 0xFE, 0x47, 0xAF, 0xAD, 0x3E, 0x2A, 0x7E,
+	0xD7, 0xFF, 0x00, 0x02, 0xFE, 0x03, 0x78, 0xCA, 0x6F, 0x07, 0x7C, 0x4E, 0xF1, 0x55, 0xC5, 0x9D,
+	0xF4, 0x91, 0x47, 0x73, 0x1C, 0x31, 0x69, 0xB3, 0xCB, 0x98, 0xDD, 0x48, 0xEA, 0xA0, 0x8E, 0xA8,
+	0xD5, 0xCE, 0xFF, 0x00, 0xC3, 0xCB, 0x3F, 0x64, 0x3F, 0xFA, 0x1E, 0xF5, 0x0F, 0xFC, 0x10, 0xDC,
+	0x7F, 0xF1, 0xBA, 0x00, 0xF9, 0xB7, 0xFE, 0x1D, 0x31, 0xFB, 0x44, 0xFF, 0x00, 0xD0, 0xE9, 0xE0,
+	0xAF, 0xFC, 0x0D, 0xBD, 0xFF, 0x00, 0xE4, 0x7A, 0x3F, 0xE1, 0xD3, 0x1F, 0xB4, 0x4F, 0xFD, 0x0E,
+	0x9E, 0x0A, 0xFF, 0x00, 0xC0, 0xDB, 0xDF, 0xFE, 0x47, 0xAF, 0xA4, 0xBF, 0xE1, 0xE5, 0x9F, 0xB2,
+	0x1F, 0xFD, 0x0F, 0x7A, 0x87, 0xFE, 0x08, 0x6E, 0x3F, 0xF8, 0xDD, 0x1F, 0xF0, 0xF2, 0xCF, 0xD9,
+	0x0F, 0xFE, 0x87, 0xBD, 0x43, 0xFF, 0x00, 0x04, 0x37, 0x1F, 0xFC, 0x6E, 0x80, 0x3E, 0x6C, 0x7F,
+	0xF8, 0x24, 0xD7, 0xED, 0x14, 0xAB, 0xB9, 0x7C, 0x6B, 0xE0, 0xBF, 0xF8, 0x0E, 0xA1, 0x7A, 0x3F,
+	0x5F, 0xB2, 0x9F, 0xE5, 0xFE, 0x35, 0xF4, 0x5F, 0xEC, 0x1D, 0xFB, 0x2D, 0x7C, 0x42, 0xFD, 0x98,
+	0x34, 0xAF, 0x11, 0x69, 0xFE, 0x3E, 0xD5, 0x34, 0x5B, 0xC6, 0xD6, 0x2E, 0xA0, 0x78, 0x5B, 0x45,
+	0x9A, 0x46, 0x51, 0xE5, 0x89, 0x14, 0xEE, 0x2F, 0x12, 0x73, 0xF3, 0x55, 0x87, 0xFF, 0x00, 0x82,
+	0x94, 0xFE, 0xC8, 0x72, 0x8F, 0x2F, 0xFE, 0x13, 0xCB, 0xFF, 0x00, 0x98, 0x8C, 0xFF, 0x00, 0xC4,
+	0x8E, 0xE8, 0x71, 0x9E, 0x7E, 0xEC, 0x79, 0xAE, 0xFB, 0xE0, 0x9F, 0xED, 0x17, 0xF0, 0xBB, 0xF6,
+	0x86, 0xB6, 0xD4, 0x2F, 0xBE, 0x15, 0xEB, 0x93, 0xDE, 0xC7, 0xA5, 0xBC, 0x4B, 0x7A, 0xD3, 0x58,
+	0xC9, 0x06, 0xD6, 0x91, 0x49, 0x5E, 0x24, 0x50, 0x4F, 0x02, 0x80, 0x3B, 0xEB, 0x70, 0xC1, 0x58,
+	0xB3, 0x67, 0x2D, 0x9E, 0x57, 0x1D, 0x85, 0x49, 0x51, 0xC1, 0x8D, 0xBB, 0xB3, 0xD4, 0xF3, 0xF3,
+	0x67, 0xB5, 0x49, 0x40, 0x05, 0x23, 0x80, 0xC8, 0x54, 0x8E, 0xD4, 0xB4, 0x1E, 0x94, 0x01, 0xF0,
+	0x9F, 0xFC, 0x15, 0xEC, 0x15, 0xF1, 0x0F, 0x81, 0x43, 0x1C, 0x9F, 0xB0, 0xDF, 0x73, 0xFF, 0x00,
+	0x03, 0x8E, 0xBE, 0x37, 0xAF, 0xB2, 0x7F, 0xE0, 0xAF, 0xBF, 0xF2, 0x32, 0x78, 0x1F, 0xFE, 0xBC,
+	0xAF, 0xBF, 0xF4, 0x64, 0x75, 0xF1, 0xB5, 0x00, 0x14, 0x51, 0x45, 0x00, 0x03, 0xAD, 0x7D, 0x61,
+	0xFF, 0x00, 0x04, 0x8F, 0xFF, 0x00, 0x92, 0xD5, 0xE2, 0x5F, 0xFB, 0x15, 0x57, 0xFF, 0x00, 0x4A,
+	0x62, 0xAF, 0x93, 0xC7, 0x5A, 0xFA, 0xC3, 0xFE, 0x09, 0x1F, 0xFF, 0x00, 0x25, 0xAB, 0xC4, 0xBF,
+	0xF6, 0x2A, 0xAF, 0xFE, 0x94, 0xC5, 0x40, 0x1E, 0xBB, 0xFF, 0x00, 0x05, 0x65, 0xFF, 0x00, 0x93,
+	0x71, 0xD1, 0xFF, 0x00, 0xEC, 0x73, 0xB5, 0xFF, 0x00, 0xD2, 0x5B, 0xDA, 0xFC, 0xF2, 0xAF, 0xD0,
+	0xDF, 0xF8, 0x2B, 0x2F, 0xFC, 0x9B, 0x8E, 0x8F, 0xFF, 0x00, 0x63, 0x9D, 0xAF, 0xFE, 0x92, 0xDE,
+	0xD7, 0xE7, 0x95, 0x24, 0x01, 0x45, 0x14, 0x53, 0x00, 0xAF, 0x7A, 0xFF, 0x00, 0x82, 0x6C, 0x7F,
+	0xC9, 0xDC, 0xE8, 0x3F, 0xF6, 0x0F, 0xD4, 0x3F, 0xF4, 0x9D, 0xEB, 0xC1, 0x6B, 0xDE, 0xBF, 0xE0,
+	0x9B, 0x1F, 0xF2, 0x77, 0x3A, 0x0F, 0xFD, 0x83, 0xF5, 0x0F, 0xFD, 0x27, 0x7A, 0x00, 0xFB, 0x27,
+	0xFE, 0x0A, 0x23, 0xFF, 0x00, 0x26, 0x77, 0xE3, 0x1F, 0xF7, 0x2C, 0xBF, 0xF4, 0xE1, 0x6B, 0x5F,
+	0x97, 0x95, 0xFA, 0x87, 0xFF, 0x00, 0x05, 0x11, 0xFF, 0x00, 0x93, 0x3B, 0xF1, 0x8F, 0xFB, 0x96,
+	0x5F, 0xFA, 0x70, 0xB5, 0xAF, 0xCB, 0xCA, 0x48, 0x02, 0x8A, 0x28, 0xA6, 0x01, 0x5E, 0x89, 0xFB,
+	0x25, 0x7F, 0xC9, 0xCE, 0x78, 0x07, 0xFE, 0xC6, 0xAB, 0x4F, 0xFD, 0x08, 0x57, 0x9D, 0xD7, 0xA2,
+	0x7E, 0xC9, 0x5F, 0xF2, 0x73, 0x9E, 0x01, 0xFF, 0x00, 0xB1, 0xAA, 0xD3, 0xFF, 0x00, 0x42, 0x14,
+	0x01, 0xFA, 0x5D, 0xFB, 0x53, 0x7F, 0xC9, 0xB2, 0x7C, 0x45, 0xFF, 0x00, 0xB1, 0x17, 0x57, 0xFF,
+	0x00, 0xD2, 0x09, 0xEB, 0xF1, 0x86, 0xBF, 0x67, 0xBF, 0x6A, 0x6F, 0xF9, 0x36, 0x4F, 0x88, 0xBF,
+	0xF6, 0x22, 0xEA, 0xFF, 0x00, 0xFA, 0x41, 0x3D, 0x7E, 0x30, 0xD7, 0x3D, 0x6E, 0x86, 0x94, 0xC2,
+	0x8A, 0x28, 0xAE, 0x6E, 0x54, 0x68, 0x15, 0xF4, 0x67, 0xFC, 0x12, 0xAB, 0xFE, 0x4F, 0x17, 0x4A,
+	0xFF, 0x00, 0xB0, 0x3D, 0xFF, 0x00, 0xFE, 0x88, 0x6A, 0xF9, 0xCE, 0xBE, 0x8C, 0xFF, 0x00, 0x82,
+	0x55, 0x7F, 0xC9, 0xE2, 0xE9, 0x5F, 0xF6, 0x07, 0xBF, 0xFF, 0x00, 0xD1, 0x0D, 0x57, 0x4F, 0xE3,
+	0x56, 0x26, 0x5A, 0x44, 0xFB, 0x57, 0xFE, 0x0A, 0x55, 0xFF, 0x00, 0x26, 0x95, 0xAF, 0x7F, 0xD7,
+	0xED, 0x8F, 0xFE, 0x94, 0x2D, 0x7E, 0x65, 0x57, 0xE9, 0xAF, 0xFC, 0x14, 0xAB, 0xFE, 0x4D, 0x2B,
+	0x5E, 0xFF, 0x00, 0xAF, 0xDB, 0x1F, 0xFD, 0x28, 0x5A, 0xFC, 0xCA, 0xAE, 0xE3, 0x10, 0xA2, 0x8A,
+	0x29, 0x5F, 0x77, 0xD8, 0x0E, 0x93, 0xE1, 0x07, 0x81, 0xE5, 0xF8, 0x91, 0xF1, 0x27, 0x49, 0xF0,
+	0x78, 0x8F, 0x74, 0x37, 0x17, 0x4B, 0xF6, 0xBF, 0xFA, 0xE2, 0xA7, 0x7B, 0xFF, 0x00, 0xE3, 0xBB,
+	0xAB, 0xEF, 0x28, 0x62, 0x8A, 0x18, 0x96, 0x38, 0x53, 0x08, 0xAA, 0x15, 0x07, 0xA0, 0x15, 0xF3,
+	0x9F, 0xEC, 0x25, 0xE0, 0x3C, 0x9D, 0x63, 0xE2, 0x5D, 0xCC, 0x5C, 0x8C, 0x58, 0x59, 0xFD, 0x47,
+	0xCF, 0x27, 0xE8, 0x52, 0xBE, 0x8F, 0x0C, 0xAB, 0x94, 0x5E, 0x9D, 0xAB, 0xFC, 0xC3, 0xFA, 0x58,
+	0x71, 0x9B, 0xCF, 0xB8, 0xFB, 0xFB, 0x2A, 0x94, 0xEF, 0x4F, 0x08, 0x94, 0x5A, 0xE9, 0xCE, 0xF5,
+	0x97, 0xCD, 0x68, 0xBD, 0x0F, 0xD1, 0xB8, 0x63, 0x0B, 0xEC, 0x70, 0x7E, 0xD1, 0xAD, 0x67, 0xF9,
+	0x09, 0x45, 0x14, 0x57, 0xF2, 0xA1, 0xF4, 0xC1, 0x45, 0x14, 0x50, 0x01, 0x5E, 0x2B, 0xFF, 0x00,
+	0x05, 0x03, 0xFF, 0x00, 0x93, 0x51, 0xF1, 0x17, 0xFD, 0x7C, 0x59, 0xFF, 0x00, 0xE9, 0x5C, 0x35,
+	0xED, 0x55, 0xE2, 0xBF, 0xF0, 0x50, 0x3F, 0xF9, 0x35, 0x1F, 0x11, 0x7F, 0xD7, 0xC5, 0x9F, 0xFE,
+	0x95, 0xC3, 0x5F, 0xB8, 0xFD, 0x1B, 0x3F, 0xE4, 0xFB, 0xF0, 0xF7, 0xFD, 0x84, 0xC3, 0xF5, 0x3F,
+	0x3D, 0xF1, 0x53, 0xFE, 0x4D, 0xD6, 0x69, 0xFF, 0x00, 0x5E, 0xA5, 0xFA, 0x1F, 0x9C, 0xA7, 0xAD,
+	0x14, 0x1E, 0xB4, 0x57, 0xFD, 0x39, 0x9F, 0xE4, 0x08, 0x51, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14,
+	0x00, 0x51, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14, 0x00, 0x57, 0xBA, 0xFE, 0xC9, 0x5F, 0xF2, 0x2F,
+	0x6A, 0x9F, 0xF6, 0x10, 0x8F, 0xFF, 0x00, 0x41, 0xAF, 0x0A, 0xAF, 0x75, 0xFD, 0x92, 0xBF, 0xE4,
+	0x5E, 0xD5, 0x3F, 0xEC, 0x21, 0x1F, 0xFE, 0x83, 0x5F, 0xC9, 0xBF, 0x4D, 0x5F, 0xF9, 0x30, 0x78,
+	0xCF, 0xFA, 0xF9, 0x4B, 0xFF, 0x00, 0x4A, 0x3F, 0x60, 0xF0, 0x3F, 0xFE, 0x4E, 0x15, 0x0F, 0xF0,
+	0xCF, 0xF2, 0x3D, 0x59, 0x3E, 0xE0, 0xFA, 0x52, 0xD2, 0x27, 0xDC, 0x1F, 0x4A, 0x5A, 0xFF, 0x00,
+	0x0F, 0x4F, 0xEF, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00,
+	0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x2B, 0xBB, 0x2D, 0xFF, 0x00, 0x7E,
+	0xA3, 0xFE, 0x28, 0xFF, 0x00, 0xE9, 0x48, 0xD7, 0x0B, 0xFE, 0xF5, 0x4F, 0xD5, 0x7E, 0x68, 0x8C,
+	0xF5, 0xA2, 0x83, 0xD6, 0x8A, 0xFF, 0x00, 0x5C, 0xB2, 0xFF, 0x00, 0xF9, 0x17, 0xD1, 0xFF, 0x00,
+	0x0C, 0x7F, 0x24, 0x7F, 0x5C, 0xE1, 0xFF, 0x00, 0xDD, 0xE1, 0xE8, 0xBF, 0x20, 0xA2, 0x8A, 0x2B,
+	0xB0, 0xD8, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0xF2, 0xFF, 0x00, 0xDB, 0x53, 0xFE, 0x4D, 0x77, 0xC5, 0xDF,
+	0xF6, 0x0E, 0x5F, 0xFD, 0x1D, 0x15, 0x7E, 0x63, 0xAF, 0xDD, 0xFC, 0x2B, 0xF4, 0xE3, 0xF6, 0xD4,
+	0xFF, 0x00, 0x93, 0x5D, 0xF1, 0x77, 0xFD, 0x83, 0x97, 0xFF, 0x00, 0x47, 0x45, 0x5F, 0x98, 0xEB,
+	0xF7, 0x7F, 0x0A, 0xFC, 0xB3, 0x8D, 0xBF, 0xE4, 0x65, 0x4F, 0xFC, 0x3F, 0xA9, 0xFD, 0x39, 0xE0,
+	0x8F, 0xFC, 0x88, 0xAB, 0xFF, 0x00, 0xD7, 0xCF, 0xD0, 0x28, 0xA2, 0x8A, 0xF8, 0xA3, 0xF6, 0x80,
+	0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x03,
+	0xA6, 0xF0, 0xA7, 0xFC, 0x8A, 0xDA, 0x8F, 0xFD, 0x84, 0x2C, 0xFF, 0x00, 0xF4, 0x5D, 0xC5, 0x3D,
+	0x7B, 0xFD, 0x29, 0x9E, 0x14, 0xFF, 0x00, 0x91, 0x5B, 0x51, 0xFF, 0x00, 0xB0, 0x85, 0x9F, 0xFE,
+	0x8B, 0xB8, 0xA7, 0xAF, 0x7F, 0xA5, 0x7F, 0x7D, 0x78, 0x25, 0xFF, 0x00, 0x26, 0xEF, 0x0D, 0xEB,
+	0x2F, 0xCC, 0xFF, 0x00, 0x00, 0xFE, 0x9A, 0xDF, 0xF2, 0x91, 0x19, 0xA7, 0xA5, 0x3F, 0xFD, 0x24,
+	0x4A, 0x28, 0xA2, 0xBF, 0x5A, 0x3F, 0x93, 0xC2, 0x8A, 0x28, 0xA0, 0x07, 0x65, 0x63, 0x71, 0x2A,
+	0x7D, 0xEA, 0xFA, 0xFB, 0xF6, 0x5D, 0xF1, 0xC8, 0xF1, 0x9F, 0xC2, 0x8B, 0x18, 0x66, 0x6F, 0xF4,
+	0xAD, 0x1D, 0xBE, 0xC1, 0x71, 0xF4, 0x51, 0xBA, 0x2F, 0xFC, 0x77, 0x15, 0xF2, 0x08, 0x40, 0x4E,
+	0xDC, 0xF6, 0xCD, 0x7B, 0x07, 0xEC, 0x73, 0xE3, 0x46, 0xD0, 0xBE, 0x22, 0x4B, 0xE1, 0x6B, 0xB9,
+	0x7F, 0x71, 0xAC, 0xDB, 0x85, 0x8F, 0xFE, 0xBA, 0x44, 0x37, 0x0F, 0xFC, 0x74, 0xC9, 0x5F, 0x03,
+	0xE2, 0x3E, 0x4F, 0xFD, 0xA9, 0xC3, 0x73, 0x94, 0x55, 0xE5, 0x4D, 0xF3, 0x2F, 0xD5, 0x1F, 0xA1,
+	0x78, 0x6F, 0x9D, 0x7F, 0x65, 0x71, 0x25, 0x38, 0x49, 0xDA, 0x35, 0x57, 0x23, 0xFD, 0x3F, 0x13,
+	0xEA, 0x2C, 0x96, 0xF9, 0x9A, 0x8A, 0x0A, 0x94, 0xF9, 0x09, 0xE9, 0xC5, 0x15, 0xFC, 0xBA, 0x7F,
+	0x53, 0x05, 0x7E, 0x9A, 0x7F, 0xC1, 0x35, 0x7F, 0xE4, 0xD1, 0xF4, 0x3F, 0xFA, 0xFE, 0xBF, 0xFF,
+	0x00, 0xD2, 0x96, 0xAF, 0xCC, 0xBA, 0xFD, 0x34, 0xFF, 0x00, 0x82, 0x6A, 0xFF, 0x00, 0xC9, 0xA3,
+	0xE8, 0x7F, 0xF5, 0xFD, 0x7F, 0xFF, 0x00, 0xA5, 0x2D, 0x40, 0x1E, 0x49, 0xFB, 0x66, 0x0C, 0x7C,
+	0x7B, 0xD4, 0x07, 0xFD, 0x3A, 0xDA, 0x7F, 0xE8, 0x15, 0xE5, 0x40, 0x1C, 0x57, 0xAB, 0x7E, 0xD9,
+	0xBF, 0xF2, 0x5F, 0x35, 0x0F, 0xFA, 0xF5, 0xB4, 0xFF, 0x00, 0xD1, 0x75, 0xE5, 0x23, 0xA5, 0x7F,
+	0x95, 0xBE, 0x2A, 0x7F, 0xC9, 0xC4, 0xCC, 0xFF, 0x00, 0xEB, 0xEC, 0xBF, 0x43, 0xFA, 0x43, 0x86,
+	0x7F, 0xE4, 0x41, 0x87, 0xFF, 0x00, 0x02, 0x0A, 0x28, 0xA2, 0xBF, 0x3D, 0x3D, 0xC0, 0x00, 0x93,
+	0xC5, 0x7E, 0x82, 0x7C, 0x12, 0xC7, 0xFC, 0x29, 0xAF, 0x0A, 0x0F, 0xFA, 0x97, 0x2C, 0xBF, 0xF4,
+	0x42, 0x57, 0xE7, 0xDD, 0x7E, 0x82, 0x7C, 0x12, 0xFF, 0x00, 0x92, 0x37, 0xE1, 0x3F, 0xFB, 0x16,
+	0xEC, 0xBF, 0xF4, 0x42, 0x57, 0xF5, 0x97, 0xD1, 0x3F, 0x5E, 0x20, 0xCC, 0xBF, 0xEB, 0xD4, 0x3F,
+	0xF4, 0xB3, 0xF3, 0x1F, 0x13, 0x3F, 0xDC, 0xF0, 0xDF, 0xE2, 0x7F, 0x92, 0x3F, 0x32, 0x7F, 0x6D,
+	0x3E, 0x3F, 0x6A, 0xEF, 0x1B, 0x0F, 0xFA, 0x8E, 0x1F, 0xFD, 0x05, 0x6B, 0xCB, 0x13, 0xEE, 0x0F,
+	0xA5, 0x7A, 0x9F, 0xED, 0xA7, 0xFF, 0x00, 0x27, 0x5D, 0xE3, 0x6F, 0xFB, 0x0E, 0x1F, 0xFD, 0x05,
+	0x6B, 0xCB, 0x13, 0xEE, 0x0F, 0xA5, 0x7F, 0x71, 0x1F, 0x90, 0x8B, 0x45, 0x14, 0x50, 0x01, 0x5F,
+	0x79, 0xFF, 0x00, 0xC1, 0x22, 0x57, 0x7F, 0xC3, 0x2F, 0x19, 0x28, 0xFF, 0x00, 0xA0, 0xE4, 0x18,
+	0xF6, 0xFD, 0xCD, 0x7C, 0x19, 0x5F, 0x7A, 0x7F, 0xC1, 0x21, 0x7F, 0xE4, 0x9A, 0xF8, 0xC3, 0xFE,
+	0xC3, 0x90, 0x7F, 0xE8, 0x9A, 0x00, 0xF1, 0xEF, 0xF8, 0x2A, 0x8F, 0xFC, 0x9C, 0xCD, 0xBF, 0xFD,
+	0x8B, 0x16, 0xBF, 0xFA, 0x1C, 0xB5, 0xF3, 0x65, 0x7D, 0x27, 0xFF, 0x00, 0x05, 0x51, 0xFF, 0x00,
+	0x93, 0x99, 0xB7, 0xFF, 0x00, 0xB1, 0x62, 0xD7, 0xFF, 0x00, 0x43, 0x96, 0xBE, 0x6C, 0xA0, 0x02,
+	0x8A, 0x28, 0xA0, 0x03, 0xB7, 0xE1, 0x5F, 0x73, 0x7F, 0xC1, 0x21, 0x17, 0x7F, 0x86, 0x7C, 0x7C,
+	0xA3, 0xFE, 0x82, 0x16, 0x18, 0xF6, 0xFD, 0xDC, 0xD5, 0xF0, 0xCF, 0x6F, 0xC2, 0xBE, 0xE8, 0xFF,
+	0x00, 0x82, 0x40, 0x7F, 0xC8, 0xB9, 0xE3, 0xEF, 0xFB, 0x08, 0x58, 0x7F, 0xE8, 0xB9, 0xA8, 0x03,
+	0xCA, 0xBF, 0xE0, 0xAA, 0x3F, 0xF2, 0x73, 0x36, 0xFF, 0x00, 0xF6, 0x2C, 0x5A, 0xFF, 0x00, 0xE8,
+	0x72, 0xD7, 0xCD, 0x95, 0xF4, 0x9F, 0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B,
+	0x5F, 0xFD, 0x0E, 0x5A, 0xF9, 0xB2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0E, 0xDF, 0x85, 0x7D, 0xCD,
+	0xFF, 0x00, 0x04, 0x83, 0xFF, 0x00, 0x91, 0x77, 0xC7, 0x9F, 0xF6, 0x10, 0xB1, 0xFF, 0x00, 0xD1,
+	0x73, 0x57, 0xC3, 0x3D, 0xBF, 0x0A, 0xFB, 0x9B, 0xFE, 0x09, 0x07, 0xFF, 0x00, 0x22, 0xEF, 0x8F,
+	0x3F, 0xEC, 0x21, 0x63, 0xFF, 0x00, 0xA2, 0xE6, 0xA0, 0x0F, 0xB2, 0xA0, 0xFE, 0x2F, 0xF7, 0x87,
+	0xFE, 0x82, 0x2A, 0x4A, 0x8E, 0x0F, 0xE2, 0xFF, 0x00, 0x78, 0x7F, 0xE8, 0x22, 0xA4, 0xA0, 0x02,
+	0x83, 0xD2, 0x8A, 0x0F, 0x4A, 0x00, 0xF8, 0x53, 0xFE, 0x0A, 0xFB, 0xFF, 0x00, 0x23, 0x27, 0x81,
+	0xFF, 0x00, 0xEB, 0xCA, 0xFB, 0xFF, 0x00, 0x46, 0x47, 0x5F, 0x1B, 0x57, 0xD9, 0x3F, 0xF0, 0x57,
+	0xDF, 0xF9, 0x19, 0x3C, 0x0F, 0xFF, 0x00, 0x5E, 0x57, 0xDF, 0xFA, 0x32, 0x3A, 0xF8, 0xDA, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x01, 0xD6, 0xBE, 0xB0, 0xFF, 0x00, 0x82, 0x47, 0xFF, 0x00, 0xC9, 0x6A,
+	0xF1, 0x2F, 0xFD, 0x8A, 0xAB, 0xFF, 0x00, 0xA5, 0x31, 0x57, 0xC9, 0xE3, 0xAD, 0x7D, 0x61, 0xFF,
+	0x00, 0x04, 0x8F, 0xFF, 0x00, 0x92, 0xD5, 0xE2, 0x5F, 0xFB, 0x15, 0x57, 0xFF, 0x00, 0x4A, 0x62,
+	0xA0, 0x0F, 0x5D, 0xFF, 0x00, 0x82, 0xB2, 0xFF, 0x00, 0xC9, 0xB8, 0xE8, 0xFF, 0x00, 0xF6, 0x39,
+	0xDA, 0xFF, 0x00, 0xE9, 0x2D, 0xED, 0x7E, 0x79, 0x57, 0xE8, 0x6F, 0xFC, 0x15, 0x97, 0xFE, 0x4D,
+	0xC7, 0x47, 0xFF, 0x00, 0xB1, 0xCE, 0xD7, 0xFF, 0x00, 0x49, 0x6F, 0x6B, 0xF3, 0xCA, 0x92, 0x00,
+	0xA2, 0x8A, 0x29, 0x80, 0x57, 0xBD, 0x7F, 0xC1, 0x36, 0x3F, 0xE4, 0xEE, 0x74, 0x1F, 0xFB, 0x07,
+	0xEA, 0x1F, 0xFA, 0x4E, 0xF5, 0xE0, 0xB5, 0xEF, 0x5F, 0xF0, 0x4D, 0x8F, 0xF9, 0x3B, 0x9D, 0x07,
+	0xFE, 0xC1, 0xFA, 0x87, 0xFE, 0x93, 0xBD, 0x00, 0x7D, 0x93, 0xFF, 0x00, 0x05, 0x11, 0xFF, 0x00,
+	0x93, 0x3B, 0xF1, 0x8F, 0xFB, 0x96, 0x5F, 0xFA, 0x70, 0xB5, 0xAF, 0xCB, 0xCA, 0xFD, 0x43, 0xFF,
+	0x00, 0x82, 0x88, 0xFF, 0x00, 0xC9, 0x9D, 0xF8, 0xC7, 0xFD, 0xCB, 0x2F, 0xFD, 0x38, 0x5A, 0xD7,
+	0xE5, 0xE5, 0x24, 0x01, 0x45, 0x14, 0x53, 0x00, 0xAF, 0x44, 0xFD, 0x92, 0xBF, 0xE4, 0xE7, 0x3C,
+	0x03, 0xFF, 0x00, 0x63, 0x55, 0xA7, 0xFE, 0x84, 0x2B, 0xCE, 0xEB, 0xD1, 0x3F, 0x64, 0xAF, 0xF9,
+	0x39, 0xCF, 0x00, 0xFF, 0x00, 0xD8, 0xD5, 0x69, 0xFF, 0x00, 0xA1, 0x0A, 0x00, 0xFD, 0x2E, 0xFD,
+	0xA9, 0xBF, 0xE4, 0xD9, 0x3E, 0x22, 0xFF, 0x00, 0xD8, 0x8B, 0xAB, 0xFF, 0x00, 0xE9, 0x04, 0xF5,
+	0xF8, 0xC3, 0x5F, 0xB3, 0xDF, 0xB5, 0x37, 0xFC, 0x9B, 0x27, 0xC4, 0x5F, 0xFB, 0x11, 0x75, 0x7F,
+	0xFD, 0x20, 0x9E, 0xBF, 0x18, 0x6B, 0x9E, 0xB7, 0x4B, 0x9A, 0x53, 0x0A, 0x28, 0xA2, 0xB9, 0xAE,
+	0x8D, 0x02, 0xBE, 0x8C, 0xFF, 0x00, 0x82, 0x55, 0x7F, 0xC9, 0xE2, 0xE9, 0x5F, 0xF6, 0x07, 0xBF,
+	0xFF, 0x00, 0xD1, 0x0D, 0x5F, 0x39, 0xD7, 0xD1, 0x9F, 0xF0, 0x4A, 0xAF, 0xF9, 0x3C, 0x5D, 0x2B,
+	0xFE, 0xC0, 0xF7, 0xFF, 0x00, 0xFA, 0x21, 0xAA, 0xE9, 0xFC, 0x6A, 0xC4, 0xCB, 0xE1, 0x3E, 0xD5,
+	0xFF, 0x00, 0x82, 0x95, 0x7F, 0xC9, 0xA5, 0x6B, 0xDF, 0xF5, 0xFB, 0x63, 0xFF, 0x00, 0xA5, 0x0B,
+	0x5F, 0x99, 0x55, 0xFA, 0x6B, 0xFF, 0x00, 0x05, 0x2A, 0xFF, 0x00, 0x93, 0x4A, 0xD7, 0xBF, 0xEB,
+	0xF6, 0xC7, 0xFF, 0x00, 0x4A, 0x16, 0xBF, 0x32, 0xAB, 0xB8, 0xC4, 0x28, 0xFD, 0xE0, 0x21, 0x91,
+	0x33, 0xB5, 0x4C, 0x8C, 0x9E, 0xA7, 0x76, 0xD5, 0xA2, 0xBA, 0x8F, 0x82, 0x7E, 0x10, 0x1E, 0x3D,
+	0xF8, 0xB1, 0xA0, 0xF8, 0x62, 0x58, 0xF7, 0x43, 0x36, 0xA0, 0xA6, 0xE3, 0xFE, 0xB8, 0x28, 0xF3,
+	0x25, 0xFF, 0x00, 0xC7, 0x10, 0xD7, 0x97, 0x9E, 0x66, 0x94, 0x72, 0x3C, 0x9B, 0x11, 0x8F, 0xAC,
+	0xEC, 0xA9, 0x42, 0x52, 0xF9, 0xC5, 0x5C, 0xD6, 0x8D, 0x39, 0x56, 0xAC, 0xA2, 0x95, 0xEE, 0xD2,
+	0x3E, 0xC2, 0xF8, 0x19, 0xE0, 0x94, 0xF0, 0x37, 0xC2, 0x5D, 0x17, 0xC3, 0x8E, 0x9B, 0x65, 0xFB,
+	0x08, 0x92, 0xF1, 0x7D, 0x26, 0x94, 0x07, 0x71, 0xF9, 0x93, 0x5D, 0x71, 0xFD, 0xE3, 0x79, 0xA2,
+	0x80, 0x49, 0x19, 0x2B, 0x8F, 0x6F, 0x4A, 0x2B, 0xFC, 0x45, 0xE2, 0x0C, 0xE3, 0x11, 0x9F, 0x67,
+	0x98, 0x9C, 0xC6, 0xB3, 0xBC, 0xAA, 0xCE, 0x53, 0x6D, 0xF9, 0xB6, 0xFF, 0x00, 0x23, 0xF6, 0x1C,
+	0x3D, 0x18, 0xD0, 0xA5, 0x18, 0x2E, 0x8A, 0xC1, 0x45, 0x14, 0x57, 0x8A, 0x6C, 0x14, 0x51, 0x45,
+	0x00, 0x15, 0xE2, 0xBF, 0xF0, 0x50, 0x3F, 0xF9, 0x35, 0x1F, 0x11, 0x7F, 0xD7, 0xC5, 0x9F, 0xFE,
+	0x95, 0xC3, 0x5E, 0xD5, 0x5E, 0x2B, 0xFF, 0x00, 0x05, 0x03, 0xFF, 0x00, 0x93, 0x51, 0xF1, 0x17,
+	0xFD, 0x7C, 0x59, 0xFF, 0x00, 0xE9, 0x5C, 0x35, 0xFB, 0x8F, 0xD1, 0xB3, 0xFE, 0x4F, 0xBF, 0x0F,
+	0x7F, 0xD8, 0x4C, 0x3F, 0x53, 0xF3, 0xDF, 0x15, 0x3F, 0xE4, 0xDD, 0x66, 0x9F, 0xF5, 0xEA, 0x5F,
+	0xA1, 0xF9, 0xCA, 0x7A, 0xD1, 0x41, 0xEB, 0x45, 0x7F, 0xD3, 0x99, 0xFE, 0x40, 0x85, 0x14, 0x51,
+	0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x7B, 0xAF,
+	0xEC, 0x95, 0xFF, 0x00, 0x22, 0xF6, 0xA9, 0xFF, 0x00, 0x61, 0x08, 0xFF, 0x00, 0xF4, 0x1A, 0xF0,
+	0xAA, 0xF7, 0x5F, 0xD9, 0x2B, 0xFE, 0x45, 0xED, 0x53, 0xFE, 0xC2, 0x11, 0xFF, 0x00, 0xE8, 0x35,
+	0xFC, 0x9B, 0xF4, 0xD5, 0xFF, 0x00, 0x93, 0x07, 0x8C, 0xFF, 0x00, 0xAF, 0x94, 0xBF, 0xF4, 0xA3,
+	0xF6, 0x0F, 0x03, 0xFF, 0x00, 0xE4, 0xE1, 0x50, 0xFF, 0x00, 0x0C, 0xFF, 0x00, 0x23, 0xD5, 0x93,
+	0xEE, 0x0F, 0xA5, 0x2D, 0x22, 0x7D, 0xC1, 0xF4, 0xA5, 0xAF, 0xF0, 0xF4, 0xFE, 0xF0, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0xBB, 0xB2, 0xD5, 0xFE, 0xDF, 0x4B, 0xCA, 0x71, 0xFC, 0xD1, 0xB6,
+	0x19, 0x5B, 0x15, 0x4E, 0xFD, 0xD7, 0xE6, 0x88, 0xCF, 0x5A, 0x28, 0x3D, 0x68, 0xAF, 0xF5, 0xCB,
+	0x2F, 0xFF, 0x00, 0x91, 0x7D, 0x1F, 0xF0, 0xC7, 0xF2, 0x47, 0xF5, 0xBE, 0x19, 0xFF, 0x00, 0xB3,
+	0xC2, 0xFD, 0x97, 0xE4, 0x14, 0x51, 0x45, 0x76, 0x68, 0xB7, 0x37, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x3C,
+	0xBF, 0xF6, 0xD4, 0xFF, 0x00, 0x93, 0x5D, 0xF1, 0x77, 0xFD, 0x83, 0x97, 0xFF, 0x00, 0x47, 0x45,
+	0x5F, 0x98, 0xEB, 0xF7, 0x7F, 0x0A, 0xFD, 0x38, 0xFD, 0xB5, 0x3F, 0xE4, 0xD7, 0x7C, 0x5D, 0xFF,
+	0x00, 0x60, 0xE5, 0xFF, 0x00, 0xD1, 0xD1, 0x57, 0xE6, 0x3A, 0xFD, 0xDF, 0xC2, 0xBF, 0x2C, 0xE3,
+	0x6F, 0xF9, 0x19, 0x53, 0xFF, 0x00, 0x0F, 0xEA, 0x7F, 0x4E, 0x78, 0x23, 0xFF, 0x00, 0x22, 0x2A,
+	0xFF, 0x00, 0xF5, 0xF3, 0xF4, 0x0A, 0x28, 0xA2, 0xBE, 0x28, 0xFD, 0xA0, 0x28, 0xA2, 0x8A, 0x00,
+	0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0xE9, 0xBC, 0x29, 0xFF,
+	0x00, 0x22, 0xB6, 0xA3, 0xFF, 0x00, 0x61, 0x0B, 0x3F, 0xFD, 0x17, 0x71, 0x4F, 0x5E, 0xFF, 0x00,
+	0x4A, 0x67, 0x85, 0x3F, 0xE4, 0x56, 0xD4, 0x7F, 0xEC, 0x21, 0x67, 0xFF, 0x00, 0xA2, 0xEE, 0x29,
+	0xEB, 0xDF, 0xE9, 0x5F, 0xDF, 0x5E, 0x09, 0x7F, 0xC9, 0xBB, 0xC3, 0x7A, 0xCB, 0xF3, 0x3F, 0xC0,
+	0x3F, 0xA6, 0xB7, 0xFC, 0xA4, 0x46, 0x69, 0xE9, 0x4F, 0xFF, 0x00, 0x49, 0x12, 0x8A, 0x28, 0xAF,
+	0xD6, 0x8F, 0xE4, 0xF0, 0xA2, 0x8A, 0x28, 0x01, 0xDC, 0x85, 0xCD, 0x69, 0x78, 0x67, 0xC4, 0x37,
+	0xBE, 0x16, 0xF1, 0x0D, 0x8F, 0x89, 0xAD, 0xA4, 0xF2, 0xE6, 0xD3, 0xEE, 0xA2, 0xB8, 0x53, 0xEE,
+	0x84, 0x11, 0xFF, 0x00, 0x8E, 0x9A, 0xCB, 0xC9, 0xE9, 0x45, 0x63, 0x5A, 0x8D, 0x3A, 0xF4, 0x65,
+	0x4A, 0x6B, 0x49, 0x26, 0x9F, 0xCC, 0xDF, 0x0F, 0x5E, 0x58, 0x7A, 0xD1, 0xAB, 0x0D, 0xE2, 0xD3,
+	0x5F, 0x23, 0xEF, 0xCD, 0x2B, 0x53, 0xB5, 0xD6, 0xB4, 0xBB, 0x6D, 0x62, 0xC5, 0xB7, 0x43, 0x77,
+	0x6E, 0x93, 0x42, 0xDE, 0xAA, 0xCA, 0x18, 0x7E, 0x86, 0xAC, 0x57, 0x9C, 0x7E, 0xCA, 0x3E, 0x2E,
+	0x93, 0xC4, 0x7F, 0x08, 0x34, 0xFB, 0x69, 0x66, 0xDD, 0x71, 0xA5, 0xDC, 0x3D, 0x8B, 0x2F, 0xA6,
+	0xDF, 0x9E, 0x2F, 0xFC, 0x72, 0x41, 0x5E, 0x8E, 0x0A, 0x91, 0x94, 0xFB, 0xBF, 0xC3, 0x5F, 0xC7,
+	0x19, 0xC6, 0x06, 0x59, 0x6E, 0x69, 0x5B, 0x0A, 0xFE, 0xC4, 0x9A, 0xF9, 0x74, 0xFC, 0x0F, 0xEC,
+	0xFC, 0x9B, 0x1D, 0x1C, 0xCB, 0x2A, 0xA1, 0x8A, 0x5F, 0x6E, 0x29, 0xFC, 0xFA, 0xFE, 0x21, 0x5F,
+	0xA6, 0x9F, 0xF0, 0x4D, 0x5F, 0xF9, 0x34, 0x7D, 0x0F, 0xFE, 0xBF, 0xAF, 0xFF, 0x00, 0xF4, 0xA5,
+	0xAB, 0xF3, 0x2E, 0xBF, 0x4D, 0x3F, 0xE0, 0x9A, 0xBF, 0xF2, 0x68, 0xFA, 0x1F, 0xFD, 0x7F, 0x5F,
+	0xFF, 0x00, 0xE9, 0x4B, 0x57, 0x98, 0x7A, 0x47, 0x92, 0xFE, 0xD9, 0xBF, 0xF2, 0x5F, 0x35, 0x0F,
+	0xFA, 0xF5, 0xB4, 0xFF, 0x00, 0xD1, 0x75, 0xE5, 0x23, 0xA5, 0x7A, 0xB7, 0xED, 0x98, 0x7F, 0xE2,
+	0xFD, 0xEA, 0x04, 0x1F, 0xF9, 0x75, 0xB4, 0xFF, 0x00, 0xD0, 0x2B, 0xCA, 0x47, 0x4E, 0x6B, 0xFC,
+	0xAD, 0xF1, 0x53, 0xFE, 0x4E, 0x26, 0x67, 0x7F, 0xF9, 0xFB, 0x2F, 0xD0, 0xFE, 0x8F, 0xE1, 0x9F,
+	0xF9, 0x10, 0x61, 0xFF, 0x00, 0xC0, 0x82, 0x8A, 0x28, 0xAF, 0xCF, 0x6C, 0x7B, 0xA1, 0x5F, 0xA0,
+	0x9F, 0x04, 0xBF, 0xE4, 0x8D, 0xF8, 0x4F, 0xFE, 0xC5, 0xBB, 0x2F, 0xFD, 0x10, 0x95, 0xF9, 0xF7,
+	0xD6, 0xBF, 0x41, 0x3E, 0x09, 0x7F, 0xC9, 0x1C, 0xF0, 0x9F, 0xFD, 0x8B, 0x96, 0x5F, 0xFA, 0x21,
+	0x2B, 0xFA, 0xCB, 0xE8, 0x9F, 0xA7, 0x10, 0x66, 0x3F, 0xF5, 0xEA, 0x1F, 0xFA, 0x59, 0xF9, 0x8F,
+	0x89, 0x9F, 0xEE, 0x78, 0x7F, 0xF1, 0x4B, 0xF2, 0x47, 0xE6, 0x4F, 0xED, 0xA7, 0xFF, 0x00, 0x27,
+	0x5D, 0xE3, 0x6F, 0xFB, 0x0E, 0x1F, 0xFD, 0x05, 0x6B, 0xCB, 0x13, 0xEE, 0x0F, 0xA5, 0x7A, 0x9F,
+	0xED, 0xA7, 0xFF, 0x00, 0x27, 0x5D, 0xE3, 0x6F, 0xFB, 0x0E, 0x1F, 0xFD, 0x05, 0x6B, 0xCB, 0x13,
+	0xEE, 0x0F, 0xA5, 0x7F, 0x71, 0x1F, 0x90, 0x8B, 0x45, 0x14, 0x50, 0x01, 0x5F, 0x7A, 0x7F, 0xC1,
+	0x21, 0x7F, 0xE4, 0x9A, 0xF8, 0xC3, 0xFE, 0xC3, 0x90, 0x7F, 0xE8, 0x9A, 0xF8, 0x2E, 0xBE, 0xF4,
+	0xFF, 0x00, 0x82, 0x42, 0xFF, 0x00, 0xC9, 0x35, 0xF1, 0x87, 0xFD, 0x87, 0x20, 0xFF, 0x00, 0xD1,
+	0x34, 0x01, 0xE3, 0xDF, 0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B, 0x7F, 0xFB, 0x16, 0x2D, 0x7F, 0xF4,
+	0x39, 0x6B, 0xE6, 0xCA, 0xFA, 0x4F, 0xFE, 0x0A, 0xA3, 0xFF, 0x00, 0x27, 0x33, 0x6F, 0xFF, 0x00,
+	0x62, 0xC5, 0xAF, 0xFE, 0x87, 0x2D, 0x7C, 0xD9, 0x40, 0x05, 0x14, 0x51, 0x40, 0x07, 0x6F, 0xC2,
+	0xBE, 0xE8, 0xFF, 0x00, 0x82, 0x40, 0x7F, 0xC8, 0xB9, 0xE3, 0xEF, 0xFB, 0x08, 0x58, 0x7F, 0xE8,
+	0xB9, 0xAB, 0xE1, 0x7E, 0xDF, 0x85, 0x7D, 0xD1, 0xFF, 0x00, 0x04, 0x80, 0xFF, 0x00, 0x91, 0x73,
+	0xC7, 0xDF, 0xF6, 0x10, 0xB0, 0xFF, 0x00, 0xD1, 0x73, 0x50, 0x07, 0x95, 0x7F, 0xC1, 0x54, 0x7F,
+	0xE4, 0xE6, 0x6D, 0xFF, 0x00, 0xEC, 0x58, 0xB5, 0xFF, 0x00, 0xD0, 0xE5, 0xAF, 0x9B, 0x2B, 0xE9,
+	0x3F, 0xF8, 0x2A, 0x8F, 0xFC, 0x9C, 0xCD, 0xBF, 0xFD, 0x8B, 0x16, 0xBF, 0xFA, 0x1C, 0xB5, 0xF3,
+	0x65, 0x00, 0x14, 0x51, 0x45, 0x00, 0x1D, 0xBF, 0x0A, 0xFB, 0x9B, 0xFE, 0x09, 0x07, 0xFF, 0x00,
+	0x22, 0xEF, 0x8F, 0x3F, 0xEC, 0x21, 0x63, 0xFF, 0x00, 0xA2, 0xE6, 0xAF, 0x86, 0x7B, 0x7E, 0x15,
+	0xF7, 0x37, 0xFC, 0x12, 0x0F, 0xFE, 0x45, 0xDF, 0x1E, 0x7F, 0xD8, 0x42, 0xC7, 0xFF, 0x00, 0x45,
+	0xCD, 0x40, 0x1F, 0x65, 0x41, 0xFC, 0x5F, 0xEF, 0x0F, 0xFD, 0x04, 0x54, 0x95, 0x1C, 0x1F, 0xC5,
+	0xFE, 0xF0, 0xFF, 0x00, 0xD0, 0x45, 0x49, 0x40, 0x05, 0x07, 0xA5, 0x14, 0xD9, 0x09, 0x11, 0xB1,
+	0x03, 0xF8, 0x68, 0x03, 0xCA, 0xBE, 0x39, 0x7E, 0xCC, 0x1F, 0x0B, 0xBF, 0x69, 0x2D, 0x72, 0xC6,
+	0x5F, 0x89, 0xD6, 0x57, 0xB2, 0x3E, 0x8F, 0x6B, 0xB2, 0xD5, 0x6C, 0x2F, 0x8C, 0x7B, 0x7C, 0xD7,
+	0xCB, 0x67, 0xFE, 0xF8, 0x5A, 0xE3, 0x3F, 0xE1, 0xD7, 0xFF, 0x00, 0xB2, 0xB7, 0xFD, 0x01, 0xF5,
+	0xCF, 0xFC, 0x1D, 0x3D, 0x67, 0xFE, 0xDD, 0x9F, 0xB5, 0xB7, 0xC4, 0x7F, 0xD9, 0x7B, 0xC4, 0x7E,
+	0x1E, 0x8B, 0xC0, 0x3A, 0x46, 0x89, 0x79, 0xFD, 0xB5, 0x6B, 0x33, 0xDD, 0xFF, 0x00, 0x6C, 0x5B,
+	0xCC, 0xD8, 0xF2, 0x8A, 0x81, 0x8D, 0x92, 0xA7, 0x3F, 0x3D, 0x78, 0x3F, 0xFC, 0x3D, 0x9F, 0xF6,
+	0x88, 0xFF, 0x00, 0xA1, 0x33, 0xC1, 0x7F, 0xF8, 0x03, 0x7B, 0xFF, 0x00, 0xC9, 0x34, 0x01, 0xF4,
+	0x47, 0xFC, 0x3A, 0xFF, 0x00, 0xF6, 0x56, 0xFF, 0x00, 0xA0, 0x3E, 0xB9, 0xFF, 0x00, 0x83, 0xA7,
+	0xA3, 0xFE, 0x1D, 0x7F, 0xFB, 0x2B, 0x7F, 0xD0, 0x1F, 0x5C, 0xFF, 0x00, 0xC1, 0xD3, 0xD7, 0xCE,
+	0xFF, 0x00, 0xF0, 0xF6, 0x7F, 0xDA, 0x23, 0xFE, 0x84, 0xCF, 0x05, 0xFF, 0x00, 0xE0, 0x0D, 0xEF,
+	0xFF, 0x00, 0x24, 0xD1, 0xFF, 0x00, 0x0F, 0x67, 0xFD, 0xA2, 0x3F, 0xE8, 0x4C, 0xF0, 0x5F, 0xFE,
+	0x00, 0xDE, 0xFF, 0x00, 0xF2, 0x4D, 0x00, 0x7D, 0x0E, 0x7F, 0xE0, 0x97, 0xFF, 0x00, 0xB2, 0xAE,
+	0x39, 0xD1, 0xF5, 0xCF, 0xFC, 0x1D, 0x3D, 0x76, 0x7F, 0x03, 0xFF, 0x00, 0x64, 0x3F, 0x83, 0xFF,
+	0x00, 0xB3, 0xCF, 0x88, 0xAF, 0x3C, 0x4D, 0xF0, 0xD3, 0x4F, 0xD4, 0x21, 0xBB, 0xBD, 0xB3, 0xFB,
+	0x35, 0xC3, 0x5E, 0xDF, 0x19, 0x01, 0x43, 0x20, 0x7E, 0x3D, 0x7E, 0x60, 0x2B, 0xE4, 0x56, 0xFF,
+	0x00, 0x82, 0xB3, 0x7E, 0xD1, 0x05, 0x70, 0x3C, 0x17, 0xE0, 0xCF, 0xF8, 0x0D, 0x85, 0xE9, 0x3F,
+	0xFA, 0x52, 0x3F, 0x98, 0xAF, 0x68, 0xFD, 0x86, 0x3F, 0x6D, 0x2F, 0x8A, 0x9F, 0xB4, 0xC7, 0xC4,
+	0x2D, 0x5F, 0xC2, 0x9E, 0x3B, 0xD1, 0x3C, 0x3F, 0x67, 0x06, 0x9F, 0xA5, 0x7D, 0xAE, 0x33, 0xA3,
+	0xC3, 0x34, 0x72, 0x13, 0xE6, 0x47, 0x1F, 0xCD, 0xBE, 0x79, 0x3D, 0x68, 0x03, 0xDB, 0x3E, 0x39,
+	0x7C, 0x08, 0xF0, 0x3F, 0xED, 0x09, 0xE1, 0x98, 0x3C, 0x1B, 0xF1, 0x0A, 0xDE, 0xE2, 0x4D, 0x3E,
+	0xD7, 0x50, 0x5B, 0xD5, 0x5B, 0x3B, 0xA1, 0x1C, 0x86, 0x71, 0x1B, 0xC6, 0x0F, 0x4F, 0xEE, 0xC8,
+	0xDD, 0xEB, 0xCC, 0xFF, 0x00, 0xE1, 0xD7, 0xFF, 0x00, 0xB2, 0xB7, 0xFD, 0x01, 0xF5, 0xCF, 0xFC,
+	0x1D, 0x3D, 0x6E, 0x7E, 0xDC, 0x3F, 0xB4, 0x37, 0x8B, 0xFF, 0x00, 0x66, 0xCF, 0x85, 0x7A, 0x7F,
+	0x8E, 0xBC, 0x07, 0xA7, 0xE9, 0xB7, 0x57, 0xD7, 0x5E, 0x22, 0x86, 0xC5, 0xA3, 0xD5, 0xA1, 0x76,
+	0x87, 0xCB, 0x68, 0x67, 0x91, 0xBE, 0xE3, 0xA1, 0xCE, 0x63, 0x1D, 0xEB, 0xE5, 0xBF, 0xF8, 0x7B,
+	0x3F, 0xED, 0x11, 0xFF, 0x00, 0x42, 0x67, 0x82, 0xFF, 0x00, 0xF0, 0x06, 0xF7, 0xFF, 0x00, 0x92,
+	0x69, 0x20, 0x3E, 0x88, 0xFF, 0x00, 0x87, 0x5F, 0xFE, 0xCA, 0xDF, 0xF4, 0x07, 0xD7, 0x3F, 0xF0,
+	0x74, 0xF4, 0x7F, 0xC3, 0xAF, 0xFF, 0x00, 0x65, 0x6F, 0xFA, 0x03, 0xEB, 0x9F, 0xF8, 0x3A, 0x7A,
+	0xF9, 0xDF, 0xFE, 0x1E, 0xCF, 0xFB, 0x44, 0x7F, 0xD0, 0x99, 0xE0, 0xBF, 0xFC, 0x01, 0xBD, 0xFF,
+	0x00, 0xE4, 0x9A, 0x3F, 0xE1, 0xEC, 0xFF, 0x00, 0xB4, 0x47, 0xFD, 0x09, 0x9E, 0x0B, 0xFF, 0x00,
+	0xC0, 0x1B, 0xDF, 0xFE, 0x49, 0xA6, 0x07, 0xD1, 0x1F, 0xF0, 0xEB, 0xFF, 0x00, 0xD9, 0x5B, 0xFE,
+	0x80, 0xFA, 0xE7, 0xFE, 0x0E, 0x9E, 0xBA, 0x1F, 0x84, 0xBF, 0xB0, 0xDF, 0xC0, 0x8F, 0x82, 0x5E,
+	0x3A, 0xB6, 0xF8, 0x83, 0xE0, 0x2D, 0x33, 0x54, 0x8F, 0x52, 0xB5, 0x8E, 0x44, 0x86, 0x4B, 0xAD,
+	0x49, 0x9D, 0x36, 0xBA, 0x6C, 0x6F, 0xFC, 0x76, 0xBE, 0x56, 0xFF, 0x00, 0x87, 0xB3, 0xFE, 0xD1,
+	0x1F, 0xF4, 0x26, 0x78, 0x2F, 0xFF, 0x00, 0x00, 0x6F, 0x7F, 0xF9, 0x26, 0xBD, 0x1B, 0xF6, 0x46,
+	0xFD, 0xBF, 0xBE, 0x33, 0x7C, 0x7B, 0xF8, 0xE5, 0xA7, 0xFC, 0x32, 0xF1, 0x87, 0x87, 0x7C, 0x35,
+	0x6B, 0x65, 0x79, 0x6B, 0x71, 0x23, 0xC9, 0xA6, 0xDA, 0xDC, 0x47, 0x71, 0xFB, 0xB8, 0x9D, 0xFF,
+	0x00, 0x8E, 0xE2, 0x4A, 0x00, 0xFA, 0x7F, 0xE2, 0xC7, 0xC2, 0xFF, 0x00, 0x0E, 0x7C, 0x65, 0xF0,
+	0x3D, 0xE7, 0xC3, 0x7F, 0x19, 0xC7, 0x23, 0x69, 0xBA, 0x87, 0x92, 0x6F, 0x96, 0xDE, 0x61, 0x1C,
+	0x8D, 0xE5, 0xCA, 0xB2, 0xA0, 0x1C, 0x1F, 0xE3, 0x45, 0xEE, 0x2B, 0xC8, 0x23, 0xFF, 0x00, 0x82,
+	0x5F, 0xFE, 0xCA, 0xFB, 0x17, 0x3A, 0x3E, 0xBD, 0xF7, 0x7F, 0x8B, 0x59, 0x7A, 0xF4, 0x0F, 0xDA,
+	0xC3, 0xE2, 0xCE, 0xBB, 0xF0, 0x3F, 0xE0, 0x2E, 0xBF, 0xF1, 0x3F, 0xC2, 0x96, 0xB6, 0x93, 0x6A,
+	0x5A, 0x5F, 0xD9, 0xBE, 0xCB, 0x1D, 0xF4, 0x6C, 0xF1, 0x16, 0x96, 0xE6, 0x28, 0x8E, 0xED, 0xAC,
+	0xA7, 0xEE, 0xBF, 0xA8, 0xAF, 0x8E, 0x7F, 0xE1, 0xEC, 0xFF, 0x00, 0xB4, 0x4F, 0x7F, 0x05, 0xF8,
+	0x27, 0xFE, 0x03, 0x63, 0x79, 0x8F, 0xFD, 0x29, 0xA0, 0x0F, 0xA2, 0x3F, 0xE1, 0xD7, 0xFF, 0x00,
+	0xB2, 0xB7, 0xFD, 0x01, 0xF5, 0xCF, 0xFC, 0x1D, 0x3D, 0x1F, 0xF0, 0xEB, 0xFF, 0x00, 0xD9, 0x5B,
+	0xFE, 0x80, 0xFA, 0xE7, 0xFE, 0x0E, 0x9E, 0xBE, 0x77, 0xFF, 0x00, 0x87, 0xB3, 0xFE, 0xD1, 0x1F,
+	0xF4, 0x26, 0x78, 0x2F, 0xFF, 0x00, 0x00, 0x6F, 0x7F, 0xF9, 0x26, 0x8F, 0xF8, 0x7B, 0x3F, 0xED,
+	0x11, 0xFF, 0x00, 0x42, 0x67, 0x82, 0xFF, 0x00, 0xF0, 0x06, 0xF7, 0xFF, 0x00, 0x92, 0x68, 0x03,
+	0xE8, 0x8F, 0xF8, 0x75, 0xFF, 0x00, 0xEC, 0xAD, 0xFF, 0x00, 0x40, 0x7D, 0x73, 0xFF, 0x00, 0x07,
+	0x4F, 0x5A, 0x3E, 0x0A, 0xFF, 0x00, 0x82, 0x79, 0xFE, 0xCE, 0x5F, 0x0F, 0x3C, 0x63, 0xA6, 0xF8,
+	0xDF, 0xC3, 0x3A, 0x4E, 0xAE, 0xBA, 0x86, 0x97, 0x79, 0x1D, 0xCD, 0x9C, 0x93, 0x6A, 0x8C, 0xE8,
+	0x24, 0x42, 0x48, 0xCF, 0xE2, 0x6B, 0xE6, 0x6F, 0xF8, 0x7B, 0x3F, 0xED, 0x11, 0xFF, 0x00, 0x42,
+	0x67, 0x82, 0xFF, 0x00, 0xF0, 0x06, 0xF7, 0xFF, 0x00, 0x92, 0x6B, 0xA6, 0xF8, 0x21, 0xFF, 0x00,
+	0x05, 0x2B, 0xF8, 0xEF, 0xF1, 0x33, 0xE3, 0x1F, 0x86, 0xFE, 0x1F, 0x6B, 0x9E, 0x16, 0xF0, 0x9D,
+	0xBD, 0x9E, 0xB5, 0xAB, 0xC5, 0x69, 0x34, 0xB6, 0xD6, 0x77, 0x29, 0x30, 0x0E, 0xEA, 0x3E, 0x52,
+	0xF7, 0x2D, 0xE9, 0xE8, 0x3E, 0x94, 0x01, 0xF6, 0x57, 0xC4, 0x2F, 0x08, 0xE9, 0xFE, 0x3F, 0xF0,
+	0x36, 0xB1, 0xE0, 0x5D, 0x76, 0x47, 0x5B, 0x3D, 0x6B, 0x49, 0xB8, 0xB0, 0xBE, 0x92, 0x09, 0x02,
+	0xC8, 0x2D, 0xE6, 0x8D, 0x92, 0x4D, 0x87, 0x6B, 0x65, 0xB6, 0xB1, 0xED, 0x5F, 0x38, 0x8F, 0xF8,
+	0x24, 0x07, 0xEC, 0xB8, 0x50, 0x32, 0xF8, 0x93, 0xC6, 0xC7, 0x23, 0x3F, 0x3E, 0xA9, 0x6F, 0xBB,
+	0xF1, 0xCD, 0xB6, 0x73, 0x5E, 0xFF, 0x00, 0xF1, 0xC3, 0xC5, 0xFA, 0x97, 0x80, 0x3E, 0x0C, 0x78,
+	0xB3, 0xC7, 0x5A, 0x02, 0xA3, 0x5F, 0xE8, 0xBE, 0x17, 0xBE, 0xBF, 0xB1, 0x59, 0x97, 0x72, 0x99,
+	0xA2, 0xB7, 0x91, 0xE3, 0xDD, 0xED, 0xB9, 0x6B, 0xF3, 0xCF, 0xFE, 0x1E, 0xEF, 0xFB, 0x56, 0x8E,
+	0x06, 0x9B, 0xE1, 0x3F, 0xFC, 0x13, 0xC8, 0x7F, 0x51, 0x70, 0x33, 0xF9, 0x0F, 0xA0, 0xAC, 0x6A,
+	0x38, 0xF3, 0x6A, 0x54, 0x79, 0xBA, 0x1F, 0x47, 0x0F, 0xF8, 0x23, 0xEF, 0xEC, 0xBA, 0x47, 0xFC,
+	0x8C, 0x7E, 0x34, 0xFF, 0x00, 0xC1, 0xA5, 0xBF, 0xFF, 0x00, 0x23, 0x51, 0xFF, 0x00, 0x0E, 0x7D,
+	0xFD, 0x97, 0x7F, 0xE8, 0x63, 0xF1, 0xA7, 0xFE, 0x0D, 0x2D, 0xFF, 0x00, 0xF9, 0x1A, 0xBE, 0x71,
+	0xFF, 0x00, 0x87, 0xBC, 0x7E, 0xD5, 0xDF, 0xF4, 0x0E, 0xF0, 0x97, 0xFE, 0x09, 0x65, 0xFF, 0x00,
+	0xE4, 0x9A, 0x3F, 0xE1, 0xEF, 0x1F, 0xB5, 0x77, 0xFD, 0x03, 0xBC, 0x25, 0xFF, 0x00, 0x82, 0x59,
+	0x7F, 0xF9, 0x26, 0xA3, 0x9A, 0x89, 0x56, 0x91, 0xF4, 0x77, 0xFC, 0x39, 0xF7, 0xF6, 0x5D, 0xFF,
+	0x00, 0xA1, 0x8F, 0xC6, 0x9F, 0xF8, 0x34, 0xB7, 0xFF, 0x00, 0xE4, 0x6A, 0xEC, 0x3E, 0x03, 0xFF,
+	0x00, 0xC1, 0x3C, 0xFE, 0x07, 0x7E, 0xCE, 0xBF, 0x11, 0x63, 0xF8, 0x9B, 0xE0, 0x4D, 0x5F, 0xC4,
+	0x53, 0xEA, 0x70, 0x41, 0x24, 0x51, 0x8D, 0x4A, 0xF6, 0x19, 0x22, 0x0A, 0xE8, 0x10, 0xF0, 0x90,
+	0xA1, 0xCF, 0x1E, 0xB5, 0xF2, 0x0F, 0xFC, 0x3D, 0xE3, 0xF6, 0xAE, 0xFF, 0x00, 0xA0, 0x77, 0x84,
+	0xBF, 0xF0, 0x4B, 0x2F, 0xFF, 0x00, 0x24, 0xD7, 0xAD, 0xFE, 0xC4, 0xDF, 0xF0, 0x50, 0x3F, 0x8E,
+	0xDF, 0xB4, 0x37, 0xC7, 0xBB, 0x1F, 0x86, 0x7E, 0x3E, 0xD3, 0xB4, 0x18, 0xF4, 0xDB, 0xAD, 0x3E,
+	0xEA, 0x69, 0x1A, 0xC7, 0x4D, 0x74, 0x90, 0xB4, 0x6A, 0x1C, 0x63, 0xF7, 0xCF, 0xEB, 0xE9, 0x4E,
+	0x32, 0xA5, 0xF6, 0x42, 0x51, 0x9A, 0x8D, 0xD9, 0xF5, 0xA7, 0xC5, 0xCF, 0x84, 0xDE, 0x11, 0xF8,
+	0xCF, 0xE0, 0x59, 0xBE, 0x1F, 0xF8, 0xEA, 0x39, 0x9B, 0x4D, 0xBA, 0x92, 0x36, 0x99, 0x6D, 0x67,
+	0xF2, 0xC9, 0xF2, 0xDC, 0x3A, 0xF3, 0xFF, 0x00, 0x01, 0xAF, 0x22, 0x5F, 0xF8, 0x25, 0xF7, 0xEC,
+	0xAE, 0x14, 0x06, 0xD1, 0xF5, 0xCF, 0xFC, 0x1C, 0xBD, 0x76, 0xDF, 0xB5, 0xCF, 0xC6, 0x4F, 0x14,
+	0x7C, 0x07, 0xF8, 0x17, 0xA8, 0xFC, 0x4D, 0xF0, 0x85, 0xA5, 0x9C, 0xF7, 0xF6, 0xB7, 0x56, 0xE9,
+	0x14, 0x3A, 0x84, 0x2C, 0xD1, 0x91, 0x24, 0xAA, 0x87, 0x21, 0x59, 0x08, 0xFB, 0xDE, 0xB5, 0xF2,
+	0x12, 0xFF, 0x00, 0xC1, 0x59, 0xFF, 0x00, 0x68, 0x7D, 0xA3, 0xFE, 0x28, 0xBF, 0x04, 0xFF, 0x00,
+	0xC0, 0x6C, 0x6F, 0x31, 0xFF, 0x00, 0xA5, 0x35, 0xD0, 0x66, 0x7D, 0x11, 0xFF, 0x00, 0x0E, 0xBF,
+	0xFD, 0x95, 0xBF, 0xE8, 0x0F, 0xAE, 0x7F, 0xE0, 0xE9, 0xEB, 0x1F, 0x55, 0xFD, 0x91, 0x7E, 0x04,
+	0x7E, 0xCF, 0xFA, 0xBD, 0xBF, 0x89, 0x7C, 0x03, 0xA5, 0xEA, 0x4B, 0xA9, 0x49, 0xE6, 0x46, 0xB2,
+	0x5D, 0xDF, 0x19, 0x82, 0xC6, 0x57, 0xE6, 0xE0, 0xFB, 0xD7, 0x87, 0xFF, 0x00, 0xC3, 0xD9, 0xFF,
+	0x00, 0x68, 0x8F, 0xFA, 0x13, 0x3C, 0x17, 0xFF, 0x00, 0x80, 0x37, 0xBF, 0xFC, 0x93, 0x5E, 0xAD,
+	0xF0, 0xC3, 0xE3, 0x67, 0xC4, 0x0F, 0xDA, 0x03, 0xC1, 0x16, 0xBF, 0x10, 0x3C, 0x7B, 0xA6, 0x69,
+	0x56, 0x97, 0x17, 0x12, 0x4D, 0x15, 0x9C, 0x3A, 0x45, 0xBC, 0xA9, 0x0B, 0x46, 0xAD, 0x8C, 0x9F,
+	0x32, 0x57, 0xF9, 0xB7, 0xE7, 0xB5, 0x7F, 0x3F, 0xFD, 0x25, 0xF8, 0x8B, 0xFB, 0x07, 0xC2, 0x9C,
+	0x5C, 0x63, 0x2B, 0x4A, 0xBB, 0x8D, 0x25, 0xDE, 0xD2, 0x7E, 0xF5, 0xBC, 0xD2, 0x3D, 0xBE, 0x1E,
+	0xA3, 0xED, 0xB3, 0x48, 0x5F, 0x65, 0xAF, 0xDC, 0x74, 0x05, 0x4A, 0x9D, 0xA4, 0xF4, 0xE3, 0xA6,
+	0x28, 0xA0, 0x9C, 0x9C, 0xD1, 0x5F, 0xE4, 0xBB, 0xDC, 0xFD, 0x45, 0x6C, 0x14, 0x51, 0x45, 0x00,
+	0x14, 0x51, 0x45, 0x00, 0x15, 0xE2, 0xBF, 0xF0, 0x50, 0x3F, 0xF9, 0x35, 0x1F, 0x11, 0x7F, 0xD7,
+	0xC5, 0x9F, 0xFE, 0x95, 0xC3, 0x5E, 0xD5, 0x5E, 0x2B, 0xFF, 0x00, 0x05, 0x03, 0xFF, 0x00, 0x93,
+	0x51, 0xF1, 0x17, 0xFD, 0x7C, 0x59, 0xFF, 0x00, 0xE9, 0x5C, 0x35, 0xFB, 0x8F, 0xD1, 0xB3, 0xFE,
+	0x4F, 0xBF, 0x0F, 0x7F, 0xD8, 0x4C, 0x3F, 0x53, 0xF3, 0xDF, 0x15, 0x3F, 0xE4, 0xDD, 0x66, 0x9F,
+	0xF5, 0xEA, 0x5F, 0xA1, 0xF9, 0xCA, 0x7A, 0xD1, 0x41, 0xEB, 0x45, 0x7F, 0xD3, 0x99, 0xFE, 0x40,
+	0x85, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40,
+	0x05, 0x7B, 0xAF, 0xEC, 0x95, 0xFF, 0x00, 0x22, 0xF6, 0xA9, 0xFF, 0x00, 0x61, 0x08, 0xFF, 0x00,
+	0xF4, 0x1A, 0xF0, 0xAA, 0xF7, 0x5F, 0xD9, 0x2B, 0xFE, 0x45, 0xED, 0x53, 0xFE, 0xC2, 0x11, 0xFF,
+	0x00, 0xE8, 0x35, 0xFC, 0x9B, 0xF4, 0xD5, 0xFF, 0x00, 0x93, 0x07, 0x8C, 0xFF, 0x00, 0xAF, 0x94,
+	0xBF, 0xF4, 0xA3, 0xF6, 0x0F, 0x03, 0xFF, 0x00, 0xE4, 0xE1, 0x50, 0xFF, 0x00, 0x0C, 0xFF, 0x00,
+	0x23, 0xD5, 0x93, 0xEE, 0x0F, 0xA5, 0x2D, 0x22, 0x7D, 0xC1, 0xF4, 0xA5, 0xAF, 0xF0, 0xF4, 0xFE,
+	0xF0, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2,
+	0x80, 0x0F, 0xC2, 0xBC, 0x73, 0xE3, 0x17, 0xFC, 0x14, 0x1F, 0xF6, 0x46, 0xF8, 0x03, 0xE3, 0xCB,
+	0xAF, 0x86, 0x7F, 0x15, 0xFE, 0x30, 0x0D, 0x17, 0x5F, 0xB5, 0x8A, 0x07, 0xBA, 0xB4, 0xFE, 0xC1,
+	0xD4, 0xA6, 0xF2, 0xC4, 0x88, 0x1A, 0x23, 0xBA, 0xDA, 0x02, 0x9F, 0x32, 0x91, 0xD4, 0x9F, 0xA9,
+	0xAF, 0x63, 0xAF, 0xC6, 0x5F, 0xF8, 0x2C, 0x8F, 0xFC, 0x9F, 0x87, 0x89, 0xBF, 0xEC, 0x17, 0xA6,
+	0xFF, 0x00, 0xE9, 0x0A, 0x57, 0xEA, 0xDE, 0x10, 0xF0, 0x5E, 0x53, 0xC7, 0x5C, 0x45, 0x3C, 0xBF,
+	0x30, 0x94, 0xE3, 0x08, 0xC1, 0xC9, 0x38, 0x34, 0x9D, 0xD3, 0x5B, 0xB7, 0x19, 0x69, 0xA9, 0xB6,
+	0x1E, 0x9F, 0xB4, 0x9D, 0x99, 0xFA, 0x18, 0x7F, 0xE0, 0xAD, 0x7F, 0xF0, 0x4F, 0x82, 0x72, 0x9F,
+	0x1F, 0x02, 0x8E, 0xCB, 0xFF, 0x00, 0x08, 0xA6, 0xA8, 0x71, 0xED, 0x9F, 0xB2, 0x73, 0x5E, 0x81,
+	0xFB, 0x32, 0x7E, 0xD9, 0xFF, 0x00, 0xB3, 0x37, 0xED, 0x87, 0xF1, 0x82, 0xC7, 0xE0, 0x27, 0xEC,
+	0xEB, 0xF1, 0x31, 0x7C, 0x41, 0xE2, 0xCD, 0x4E, 0xD6, 0x79, 0xAD, 0x74, 0xBF, 0xEC, 0x7B, 0xEB,
+	0x53, 0x34, 0x70, 0xC6, 0xF2, 0x49, 0xFB, 0xCB, 0x88, 0x12, 0x31, 0x84, 0x56, 0xE0, 0xD7, 0xE0,
+	0x93, 0xFD, 0xF3, 0xF5, 0xAF, 0xBF, 0x7F, 0xE0, 0xD9, 0x0F, 0xF9, 0x4C, 0x1F, 0x80, 0x7F, 0xEC,
+	0x03, 0xE2, 0x0F, 0xFD, 0x35, 0x4F, 0x5F, 0xD2, 0xF8, 0x7F, 0xA3, 0x8F, 0x04, 0xD1, 0xAD, 0x1A,
+	0x91, 0xAF, 0x5E, 0xF1, 0x69, 0xAB, 0xCA, 0x0D, 0x5D, 0x34, 0xF6, 0xE4, 0x3A, 0xBE, 0xAF, 0x0A,
+	0x3F, 0xBC, 0x8E, 0xEB, 0x53, 0xEE, 0x9F, 0xDA, 0x6B, 0xF6, 0xD0, 0xFD, 0x9B, 0xBF, 0x63, 0xEF,
+	0x8B, 0x97, 0xBF, 0x02, 0x7F, 0x68, 0xFF, 0x00, 0x89, 0x47, 0xC3, 0x7E, 0x2E, 0xD2, 0xE1, 0x82,
+	0xE2, 0xEB, 0x4B, 0x6D, 0x2E, 0xEE, 0xEB, 0xC9, 0x8E, 0x6B, 0x75, 0x9A, 0x36, 0xF3, 0x6D, 0xAD,
+	0xE5, 0x84, 0xE5, 0x5B, 0xEE, 0xEE, 0x53, 0xF4, 0xAE, 0x08, 0xFF, 0x00, 0xC1, 0x5B, 0xBF, 0xE0,
+	0x9E, 0xC0, 0xE1, 0x7E, 0x3F, 0xE0, 0x76, 0x1F, 0xF0, 0x8A, 0xEA, 0xA3, 0x1F, 0x87, 0xD9, 0xF8,
+	0xAF, 0x95, 0xFF, 0x00, 0xE0, 0xE7, 0x4F, 0xF9, 0x4C, 0x27, 0x8F, 0x7F, 0xEC, 0x07, 0xA0, 0xFF,
+	0x00, 0xE9, 0xB6, 0xDE, 0xBF, 0x3F, 0x47, 0x4A, 0xFE, 0x87, 0xA7, 0x89, 0xA9, 0x42, 0x94, 0x69,
+	0x27, 0xA4, 0x52, 0x5F, 0x72, 0xB1, 0xFA, 0x45, 0x1F, 0x11, 0x73, 0xA8, 0xD1, 0x8A, 0x50, 0x86,
+	0x89, 0x2D, 0xA5, 0xFF, 0x00, 0xC9, 0x1F, 0xB5, 0x2F, 0xFF, 0x00, 0x05, 0x70, 0xFF, 0x00, 0x82,
+	0x7C, 0xF3, 0xFF, 0x00, 0x19, 0x03, 0xC3, 0x73, 0x9F, 0xF8, 0x45, 0xF5, 0x61, 0xD3, 0x68, 0x65,
+	0xDC, 0x6D, 0xBC, 0xB1, 0xB8, 0x05, 0xFB, 0xD5, 0xF4, 0x79, 0xCE, 0x79, 0xFF, 0x00, 0xD0, 0x71,
+	0xFA, 0x60, 0x63, 0xF2, 0x1F, 0x41, 0x5F, 0xCE, 0x47, 0xA7, 0xFB, 0xA7, 0xF9, 0x35, 0x7F, 0x47,
+	0x0F, 0xF7, 0xCF, 0xD6, 0xBB, 0xB0, 0xD5, 0xAA, 0x56, 0xBF, 0x31, 0xF7, 0x1C, 0x23, 0xC4, 0x78,
+	0xDC, 0xFB, 0xDA, 0xFB, 0x78, 0xC5, 0x5A, 0xDB, 0x27, 0xD7, 0xD5, 0xB1, 0x28, 0xA2, 0x8A, 0xEA,
+	0x3E, 0xD0, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0xF2, 0xFF, 0x00, 0xDB, 0x53, 0xFE, 0x4D, 0x77, 0xC5, 0xDF, 0xF6, 0x0E, 0x5F, 0xFD,
+	0x1D, 0x15, 0x7E, 0x63, 0xAF, 0xDD, 0xFC, 0x2B, 0xF4, 0xE3, 0xF6, 0xD4, 0xFF, 0x00, 0x93, 0x5D,
+	0xF1, 0x77, 0xFD, 0x83, 0x97, 0xFF, 0x00, 0x47, 0x45, 0x5F, 0x98, 0xEB, 0xF7, 0x7F, 0x0A, 0xFC,
+	0xB3, 0x8D, 0xBF, 0xE4, 0x65, 0x4F, 0xFC, 0x3F, 0xA9, 0xFD, 0x39, 0xE0, 0x8F, 0xFC, 0x88, 0xAB,
+	0xFF, 0x00, 0xD7, 0xCF, 0xD0, 0x28, 0xA2, 0x8A, 0xF8, 0xA3, 0xF6, 0x80, 0xA2, 0x8A, 0x28, 0x00,
+	0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x03, 0xA6, 0xF0, 0xA7, 0xFC,
+	0x8A, 0xDA, 0x8F, 0xFD, 0x84, 0x2C, 0xFF, 0x00, 0xF4, 0x5D, 0xC5, 0x3D, 0x7B, 0xFD, 0x29, 0x9E,
+	0x14, 0xFF, 0x00, 0x91, 0x5B, 0x51, 0xFF, 0x00, 0xB0, 0x85, 0x9F, 0xFE, 0x8B, 0xB8, 0xA7, 0xAF,
+	0x7F, 0xA5, 0x7F, 0x7D, 0x78, 0x25, 0xFF, 0x00, 0x26, 0xEF, 0x0D, 0xEB, 0x2F, 0xCC, 0xFF, 0x00,
+	0x00, 0xFE, 0x9A, 0xDF, 0xF2, 0x91, 0x19, 0xA7, 0xA5, 0x3F, 0xFD, 0x24, 0x4A, 0x28, 0xA2, 0xBF,
+	0x5A, 0x3F, 0x93, 0xC2, 0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x0F, 0xBB, 0x3F, 0xE0, 0x85,
+	0xDE, 0x01, 0xF8, 0x51, 0xF1, 0xCB, 0xE3, 0x57, 0x8A, 0xFE, 0x0E, 0xFC, 0x52, 0xB0, 0xBA, 0x99,
+	0x9F, 0xC3, 0xF1, 0xEA, 0xDA, 0x30, 0xB6, 0xBA, 0x30, 0x9D, 0xF6, 0xD3, 0x2A, 0x4C, 0x99, 0xF7,
+	0xFB, 0x44, 0x4D, 0xFF, 0x00, 0x00, 0xAF, 0xD4, 0x08, 0xBF, 0xE0, 0x97, 0xFF, 0x00, 0xB2, 0x9A,
+	0xC4, 0xA1, 0x34, 0xAD, 0x71, 0x94, 0x2F, 0x0D, 0xFD, 0xB4, 0xFC, 0xD7, 0xE1, 0xAF, 0xEC, 0x2B,
+	0xFB, 0x41, 0x78, 0xAB, 0xF6, 0x62, 0xFD, 0xA8, 0xBC, 0x2B, 0xF1, 0x6F, 0xC2, 0x31, 0xDA, 0xC9,
+	0x75, 0x0D, 0xC4, 0x96, 0xAF, 0x0E, 0xA1, 0x1B, 0xBD, 0xBC, 0xB0, 0xCF, 0x04, 0x90, 0x1F, 0x33,
+	0xCB, 0x91, 0x0F, 0x0C, 0xD9, 0x1C, 0xFF, 0x00, 0x05, 0x7E, 0xA2, 0x7F, 0xC3, 0xD9, 0xBF, 0x68,
+	0x91, 0xC3, 0x78, 0x37, 0xC1, 0x27, 0xDC, 0x58, 0xDE, 0xF3, 0xFF, 0x00, 0x93, 0x35, 0xFC, 0xD3,
+	0xE2, 0x96, 0x01, 0xE1, 0x78, 0x91, 0xD6, 0x4B, 0x4A, 0x91, 0x4F, 0xE6, 0xB4, 0x67, 0xF4, 0xDF,
+	0x85, 0x78, 0xF7, 0x89, 0xE1, 0xAF, 0x63, 0x27, 0xAD, 0x39, 0x35, 0xF2, 0x7A, 0xA3, 0xE8, 0x8F,
+	0xF8, 0x75, 0xFF, 0x00, 0xEC, 0xAB, 0xFF, 0x00, 0x40, 0x7D, 0x73, 0xFF, 0x00, 0x07, 0x4F, 0x5E,
+	0xB9, 0xF0, 0x9B, 0xE1, 0x27, 0x84, 0xFE, 0x09, 0xF8, 0x1A, 0x1F, 0x87, 0x7E, 0x04, 0xB6, 0x9A,
+	0x2D, 0x3E, 0xD5, 0xE5, 0x68, 0x3E, 0xD3, 0x3F, 0x98, 0xFB, 0xA4, 0x6D, 0xC7, 0x93, 0xD6, 0xBE,
+	0x1B, 0xFF, 0x00, 0x87, 0xB3, 0xFE, 0xD1, 0x1F, 0xF4, 0x26, 0x78, 0x2F, 0xFF, 0x00, 0x00, 0x6F,
+	0x7F, 0xF9, 0x26, 0xBE, 0xBF, 0xFD, 0x91, 0x7E, 0x30, 0xF8, 0x9B, 0xE3, 0xD7, 0xC0, 0xFD, 0x37,
+	0xE2, 0x6F, 0x8C, 0x2C, 0x2C, 0x6D, 0xEF, 0xAF, 0x2E, 0x2E, 0x52, 0x48, 0x74, 0xDD, 0xDE, 0x4E,
+	0xD8, 0xE6, 0x65, 0x04, 0x06, 0x24, 0x83, 0xC7, 0x42, 0x49, 0xF5, 0x27, 0xAD, 0x7E, 0x6A, 0x7E,
+	0x9A, 0x45, 0xF1, 0x43, 0xF6, 0x53, 0xF8, 0x79, 0xF1, 0x5B, 0xC4, 0xF3, 0xF8, 0xB7, 0xC4, 0x1A,
+	0x9E, 0xAD, 0x0D, 0xCC, 0xF1, 0x2C, 0x73, 0x2D, 0x9D, 0xC2, 0x2A, 0x95, 0x5F, 0xBB, 0x91, 0xB0,
+	0xFF, 0x00, 0x3A, 0xE7, 0x9B, 0xF6, 0x0E, 0xF8, 0x4E, 0xED, 0xBD, 0xBC, 0x47, 0xAF, 0x29, 0x6E,
+	0x71, 0xF6, 0x88, 0x38, 0xF6, 0xE6, 0x13, 0xFC, 0xCF, 0xD4, 0xD6, 0x17, 0xED, 0x07, 0xFB, 0x50,
+	0xFC, 0x4D, 0xF8, 0x5D, 0xF1, 0x3A, 0xEB, 0xC1, 0xFE, 0x1A, 0x87, 0x4B, 0x6B, 0x78, 0x2D, 0xE3,
+	0x96, 0x36, 0xBC, 0xB7, 0x72, 0xEC, 0x58, 0x73, 0xFC, 0x7F, 0xD2, 0xB8, 0x91, 0xFB, 0x73, 0x7C,
+	0x6B, 0xC6, 0x12, 0x2D, 0x17, 0x18, 0xC0, 0xFF, 0x00, 0x41, 0x7C, 0xFF, 0x00, 0xE8, 0xDA, 0xFE,
+	0x56, 0xE2, 0x8E, 0x32, 0xF0, 0x2F, 0x07, 0xC4, 0x18, 0x9C, 0x3E, 0x6B, 0x80, 0x72, 0xC4, 0x46,
+	0x6D, 0x4E, 0x5E, 0xCD, 0x3B, 0xCB, 0xAE, 0xB7, 0xD4, 0xFD, 0x13, 0x2D, 0xCA, 0x78, 0xD2, 0xAE,
+	0x06, 0x9C, 0xF0, 0xD5, 0xED, 0x06, 0x93, 0x4B, 0x9E, 0xDA, 0x7D, 0xC7, 0xA9, 0xFF, 0x00, 0xC3,
+	0x05, 0xFC, 0x24, 0xFF, 0x00, 0xA1, 0x97, 0x5E, 0xFF, 0x00, 0xC0, 0x88, 0x3F, 0xF8, 0xC5, 0x1F,
+	0xF0, 0xC1, 0x7F, 0x09, 0x3F, 0xE8, 0x65, 0xD7, 0xBF, 0xF0, 0x22, 0x0F, 0xFE, 0x31, 0x5E, 0x59,
+	0xFF, 0x00, 0x0D, 0xCB, 0xF1, 0xB3, 0xFE, 0x78, 0xE8, 0xBF, 0xF8, 0x2F, 0x7F, 0xFE, 0x3B, 0x47,
+	0xFC, 0x37, 0x2F, 0xC6, 0xCF, 0xF9, 0xE3, 0xA2, 0xFF, 0x00, 0xE0, 0xBD, 0xFF, 0x00, 0xF8, 0xED,
+	0x78, 0x3F, 0xEB, 0xE7, 0xD1, 0xC7, 0xFE, 0x85, 0xDF, 0xF9, 0x4B, 0xFE, 0x09, 0xDB, 0xFD, 0x87,
+	0xC7, 0xDF, 0xF4, 0x11, 0xFF, 0x00, 0x93, 0xB3, 0xD4, 0x8F, 0xEC, 0x17, 0xF0, 0x8F, 0xB6, 0xBF,
+	0xE2, 0x0F, 0xFC, 0x0C, 0x87, 0xFF, 0x00, 0x8D, 0x57, 0xB3, 0x78, 0x57, 0x40, 0xB3, 0xF0, 0x97,
+	0x86, 0x34, 0xDF, 0x0B, 0x69, 0xCF, 0x23, 0x5B, 0xE9, 0xB6, 0x31, 0x5A, 0xC0, 0xD3, 0x30, 0x2E,
+	0x51, 0x10, 0x28, 0x2C, 0x40, 0x00, 0x9C, 0x0E, 0x78, 0x1C, 0xD7, 0xC9, 0x1F, 0xF0, 0xDC, 0xDF,
+	0x1B, 0x08, 0xC7, 0x93, 0xA2, 0xFF, 0x00, 0xE0, 0x03, 0xFF, 0x00, 0xF1, 0xDA, 0xFA, 0xAF, 0xE1,
+	0xBE, 0xBD, 0x7B, 0xE2, 0x9F, 0x87, 0xDA, 0x17, 0x89, 0xB5, 0x30, 0x82, 0xE7, 0x51, 0xD1, 0xED,
+	0xAE, 0x6E, 0x04, 0x4B, 0x85, 0xDE, 0xF1, 0x2B, 0x36, 0x06, 0x4E, 0x06, 0x4F, 0xA9, 0xAF, 0xD5,
+	0xFC, 0x28, 0xE2, 0x2F, 0x0C, 0x73, 0xAC, 0xC3, 0x13, 0x0E, 0x17, 0xC3, 0x7B, 0x1A, 0x91, 0x84,
+	0x5C, 0xDF, 0x22, 0x8D, 0xE3, 0x7D, 0x35, 0xBB, 0xBE, 0xA7, 0xCD, 0xF1, 0x26, 0x03, 0x88, 0xB0,
+	0x74, 0x69, 0xBC, 0xCE, 0xA7, 0x34, 0x5B, 0x7C, 0xBE, 0xF5, 0xF5, 0xB1, 0xE5, 0x9F, 0x11, 0x7F,
+	0xE0, 0x9F, 0xBF, 0xB3, 0x9F, 0xC4, 0xFF, 0x00, 0x1A, 0x6A, 0x5E, 0x3E, 0xF1, 0x6E, 0x9D, 0xAA,
+	0x36, 0xA1, 0xA9, 0xDD, 0x0B, 0x8B, 0xD6, 0x83, 0x57, 0x91, 0x14, 0xB7, 0x3D, 0x00, 0xE8, 0x32,
+	0x7A, 0x76, 0xAC, 0x75, 0xFF, 0x00, 0x82, 0x5F, 0x7E, 0xCA, 0xC1, 0x70, 0x74, 0x8D, 0x73, 0xFF,
+	0x00, 0x07, 0x52, 0x57, 0x95, 0x7E, 0xD0, 0x7F, 0xF0, 0x52, 0x0F, 0x8E, 0x3F, 0x09, 0xBE, 0x35,
+	0xF8, 0x8B, 0xE1, 0xC7, 0x87, 0x7C, 0x2F, 0xE1, 0x5B, 0x8B, 0x3D, 0x2B, 0x52, 0x36, 0xD6, 0xB2,
+	0xEA, 0x16, 0x37, 0x46, 0x56, 0x5D, 0xBB, 0xBA, 0xAC, 0xE0, 0x13, 0x8E, 0xE0, 0x01, 0xED, 0x5C,
+	0x6F, 0xFC, 0x3D, 0x9F, 0xF6, 0x87, 0x3C, 0x8F, 0x05, 0x78, 0x2C, 0x7B, 0x35, 0x8D, 0xEE, 0x7F,
+	0xF4, 0xA6, 0xBF, 0x70, 0x3E, 0x48, 0xFA, 0x23, 0xFE, 0x1D, 0x7F, 0xFB, 0x2B, 0x7F, 0xD0, 0x1F,
+	0x5C, 0xFF, 0x00, 0xC1, 0xD3, 0xD1, 0xFF, 0x00, 0x0E, 0xBF, 0xFD, 0x95, 0xBF, 0xE8, 0x0F, 0xAE,
+	0x7F, 0xE0, 0xE9, 0xEB, 0xE7, 0x7F, 0xF8, 0x7B, 0x3F, 0xED, 0x11, 0xFF, 0x00, 0x42, 0x67, 0x82,
+	0xFF, 0x00, 0xF0, 0x06, 0xF7, 0xFF, 0x00, 0x92, 0x68, 0xFF, 0x00, 0x87, 0xB3, 0xFE, 0xD1, 0x1F,
+	0xF4, 0x26, 0x78, 0x2F, 0xFF, 0x00, 0x00, 0x6F, 0x7F, 0xF9, 0x26, 0x80, 0x3E, 0x88, 0xFF, 0x00,
+	0x87, 0x5F, 0xFE, 0xCA, 0xDF, 0xF4, 0x07, 0xD7, 0x3F, 0xF0, 0x74, 0xF5, 0xE8, 0x5F, 0x00, 0xFF,
+	0x00, 0x67, 0xFF, 0x00, 0x87, 0x9F, 0xB3, 0xBA, 0x6B, 0x3E, 0x18, 0xF8, 0x6D, 0x69, 0x75, 0x1D,
+	0xBD, 0xE1, 0x82, 0xEA, 0x44, 0xBB, 0xBA, 0xF3, 0x18, 0xBE, 0x24, 0x51, 0xCF, 0x6F, 0xBB, 0x5F,
+	0x1A, 0xFF, 0x00, 0xC3, 0xD9, 0xFF, 0x00, 0x68, 0x8F, 0xFA, 0x13, 0x3C, 0x17, 0xFF, 0x00, 0x80,
+	0x37, 0xBF, 0xFC, 0x93, 0x5F, 0x49, 0x7E, 0xC2, 0x5F, 0xB4, 0x9F, 0x8F, 0x3F, 0x69, 0x8F, 0x0E,
+	0xF8, 0x93, 0xC5, 0x5E, 0x3A, 0xD2, 0x74, 0x9B, 0x3B, 0x9D, 0x3E, 0xF6, 0xDE, 0xD2, 0x15, 0xD2,
+	0x20, 0x95, 0x50, 0xAE, 0xD6, 0x7C, 0x90, 0xF2, 0x39, 0x27, 0xE6, 0xF6, 0xFF, 0x00, 0x00, 0x0D,
+	0x9F, 0x8B, 0xBF, 0xB1, 0xBF, 0xC1, 0x6F, 0xDA, 0x1B, 0xC7, 0x33, 0x78, 0xDF, 0xE2, 0x35, 0x8E,
+	0xA3, 0x35, 0xF4, 0x30, 0xC7, 0x66, 0xAD, 0x63, 0xA8, 0x18, 0xD4, 0x46, 0x8A, 0x58, 0x64, 0x0F,
+	0xF6, 0x9D, 0xAB, 0x9C, 0xFF, 0x00, 0x87, 0x5F, 0xFE, 0xCA, 0xDF, 0xF4, 0x07, 0xD7, 0x3F, 0xF0,
+	0x74, 0xF5, 0xC6, 0xFE, 0xD9, 0x7F, 0xB7, 0x17, 0xC5, 0x7F, 0xD9, 0xB3, 0xE3, 0x3F, 0xFC, 0x20,
+	0x7E, 0x05, 0xD0, 0x3C, 0x3B, 0x75, 0x67, 0x3E, 0x97, 0x15, 0xEC, 0x8D, 0xAB, 0x5B, 0x4E, 0xD2,
+	0x07, 0x76, 0x65, 0xE3, 0xCB, 0x99, 0x7F, 0xB9, 0xE9, 0x5E, 0x53, 0xFF, 0x00, 0x0F, 0x67, 0xFD,
+	0xA2, 0x3F, 0xE8, 0x4C, 0xF0, 0x5F, 0xFE, 0x00, 0xDE, 0xFF, 0x00, 0xF2, 0x4D, 0x00, 0x7D, 0x11,
+	0xFF, 0x00, 0x0E, 0xBF, 0xFD, 0x95, 0xBF, 0xE8, 0x0F, 0xAE, 0x7F, 0xE0, 0xE9, 0xE8, 0xFF, 0x00,
+	0x87, 0x5F, 0xFE, 0xCA, 0xDF, 0xF4, 0x07, 0xD7, 0x3F, 0xF0, 0x74, 0xF5, 0xF3, 0xBF, 0xFC, 0x3D,
+	0x9F, 0xF6, 0x88, 0xFF, 0x00, 0xA1, 0x33, 0xC1, 0x7F, 0xF8, 0x03, 0x7B, 0xFF, 0x00, 0xC9, 0x34,
+	0x7F, 0xC3, 0xD9, 0xFF, 0x00, 0x68, 0x8F, 0xFA, 0x13, 0x3C, 0x17, 0xFF, 0x00, 0x80, 0x37, 0xBF,
+	0xFC, 0x93, 0x40, 0x1F, 0x43, 0x9F, 0xF8, 0x26, 0x07, 0xEC, 0xAC, 0xBF, 0x37, 0xF6, 0x3E, 0xB9,
+	0xC7, 0x3F, 0xF2, 0x1A, 0x7A, 0xF4, 0x6F, 0x80, 0x7F, 0xB3, 0x67, 0xC3, 0x3F, 0xD9, 0xC7, 0x4F,
+	0xD5, 0x2C, 0x3E, 0x18, 0xD8, 0xDE, 0x43, 0x1E, 0xA8, 0xF0, 0xBD, 0xCA, 0xDE, 0xDD, 0x19, 0x0B,
+	0x34, 0x6A, 0xC1, 0x70, 0x4F, 0x4F, 0xBC, 0x6B, 0xE3, 0x19, 0x3F, 0xE0, 0xAC, 0xBF, 0xB4, 0x4B,
+	0x26, 0xD5, 0xF0, 0x5F, 0x83, 0x3F, 0xE0, 0x3A, 0x7D, 0xE9, 0xFF, 0x00, 0xDB, 0xA1, 0xFC, 0xFF,
+	0x00, 0xC2, 0xBE, 0x8F, 0xFD, 0x83, 0x3F, 0x6A, 0x7F, 0x88, 0x3F, 0xB4, 0xF6, 0x85, 0xE2, 0x6D,
+	0x43, 0xC7, 0x9A, 0x5E, 0x8B, 0x69, 0x36, 0x8F, 0x77, 0x6D, 0x1D, 0xBA, 0xE8, 0xB0, 0xC8, 0xAA,
+	0x44, 0xBE, 0x63, 0x12, 0xC1, 0xE4, 0x90, 0xE7, 0xE5, 0x1D, 0xE8, 0x03, 0x77, 0xE2, 0xEF, 0xEC,
+	0x6F, 0xF0, 0x5B, 0xF6, 0x86, 0xF1, 0xCC, 0xDE, 0x37, 0xF8, 0x8D, 0x63, 0xA8, 0xCD, 0x7D, 0x0C,
+	0x31, 0xD9, 0xAB, 0x58, 0xEA, 0x06, 0x35, 0x11, 0xA2, 0x96, 0x19, 0x03, 0xFD, 0xA7, 0x6A, 0xE7,
+	0x3F, 0xE1, 0xD7, 0xFF, 0x00, 0xB2, 0xB7, 0xFD, 0x01, 0xF5, 0xCF, 0xFC, 0x1D, 0x3D, 0x71, 0xBF,
+	0xB6, 0x5F, 0xED, 0xC5, 0xF1, 0x5F, 0xF6, 0x6C, 0xF8, 0xCF, 0xFF, 0x00, 0x08, 0x1F, 0x81, 0x74,
+	0x0F, 0x0E, 0xDD, 0x59, 0xCF, 0xA5, 0xC5, 0x7B, 0x23, 0x6A, 0xD6, 0xD3, 0xB4, 0x81, 0xDD, 0x99,
+	0x78, 0xF2, 0xE6, 0x5F, 0xEE, 0x7A, 0x57, 0x94, 0xFF, 0x00, 0xC3, 0xD9, 0xFF, 0x00, 0x68, 0x8F,
+	0xFA, 0x13, 0x3C, 0x17, 0xFF, 0x00, 0x80, 0x37, 0xBF, 0xFC, 0x93, 0x40, 0x1F, 0x44, 0x7F, 0xC3,
+	0xAF, 0xFF, 0x00, 0x65, 0x6F, 0xFA, 0x03, 0xEB, 0x9F, 0xF8, 0x3A, 0x7A, 0x3F, 0xE1, 0xD7, 0xFF,
+	0x00, 0xB2, 0xB7, 0xFD, 0x01, 0xF5, 0xCF, 0xFC, 0x1D, 0x3D, 0x7C, 0xEF, 0xFF, 0x00, 0x0F, 0x67,
+	0xFD, 0xA2, 0x3F, 0xE8, 0x4C, 0xF0, 0x5F, 0xFE, 0x00, 0xDE, 0xFF, 0x00, 0xF2, 0x4D, 0x1F, 0xF0,
+	0xF6, 0x7F, 0xDA, 0x23, 0xFE, 0x84, 0xCF, 0x05, 0xFF, 0x00, 0xE0, 0x0D, 0xEF, 0xFF, 0x00, 0x24,
+	0xD0, 0x07, 0xD0, 0xE7, 0xFE, 0x09, 0x81, 0xFB, 0x2B, 0x2F, 0xCD, 0xFD, 0x8F, 0xAE, 0x71, 0xCF,
+	0xFC, 0x86, 0x9E, 0xBD, 0x0F, 0xE0, 0x3F, 0xEC, 0xD5, 0xF0, 0xD3, 0xF6, 0x72, 0xB4, 0xD4, 0x2C,
+	0x7E, 0x18, 0xD9, 0x5E, 0x41, 0x1E, 0xA7, 0x24, 0x4D, 0x74, 0x2F, 0x6E, 0x8C, 0xA4, 0x98, 0xD4,
+	0x85, 0xC6, 0x7D, 0x89, 0xAF, 0x8D, 0x24, 0xFF, 0x00, 0x82, 0xB2, 0xFE, 0xD1, 0x2C, 0x9B, 0x57,
+	0xC1, 0x7E, 0x0C, 0xFF, 0x00, 0x80, 0xE9, 0xF7, 0xA7, 0xFF, 0x00, 0x6E, 0x87, 0xF3, 0xFF, 0x00,
+	0x0A, 0xFA, 0x33, 0xF6, 0x0D, 0xFD, 0xA9, 0xBE, 0x21, 0x7E, 0xD3, 0xFA, 0x57, 0x88, 0xB5, 0x0F,
+	0x1F, 0x69, 0x7A, 0x2D, 0xAB, 0xE8, 0xF7, 0x50, 0x47, 0x0A, 0x68, 0xB1, 0xCB, 0x1A, 0x9F, 0x30,
+	0x48, 0xDF, 0x30, 0x79, 0x5F, 0xFB, 0xB4, 0x01, 0xF4, 0x15, 0xA7, 0xDC, 0x60, 0x02, 0xE3, 0x71,
+	0xC6, 0xD6, 0xFE, 0x7C, 0x70, 0x73, 0xF5, 0xA9, 0x6A, 0x3B, 0x62, 0xA6, 0x3D, 0xC9, 0xDC, 0xFA,
+	0x54, 0x94, 0x00, 0x52, 0x38, 0xCA, 0x11, 0x8E, 0xD4, 0xB4, 0x1E, 0x94, 0x01, 0xF0, 0x9F, 0xFC,
+	0x15, 0xEC, 0x6D, 0xF1, 0x17, 0x81, 0x57, 0xD2, 0xC6, 0xFB, 0xFF, 0x00, 0x43, 0x8E, 0xBE, 0x37,
+	0xAF, 0xB2, 0x7F, 0xE0, 0xAF, 0xBF, 0xF2, 0x32, 0x78, 0x1F, 0xFE, 0xBC, 0xAF, 0xBF, 0xF4, 0x64,
+	0x75, 0xF1, 0xB5, 0x00, 0x14, 0x51, 0x45, 0x00, 0x03, 0xAD, 0x7D, 0x61, 0xFF, 0x00, 0x04, 0x8F,
+	0xFF, 0x00, 0x92, 0xD5, 0xE2, 0x5F, 0xFB, 0x15, 0x57, 0xFF, 0x00, 0x4A, 0x62, 0xAF, 0x93, 0xC7,
+	0x5A, 0xFA, 0xC3, 0xFE, 0x09, 0x1F, 0xFF, 0x00, 0x25, 0xAB, 0xC4, 0xBF, 0xF6, 0x2A, 0xAF, 0xFE,
+	0x94, 0xC5, 0x40, 0x1E, 0xBB, 0xFF, 0x00, 0x05, 0x65, 0xFF, 0x00, 0x93, 0x71, 0xD1, 0xFF, 0x00,
+	0xEC, 0x73, 0xB5, 0xFF, 0x00, 0xD2, 0x5B, 0xDA, 0xFC, 0xF2, 0xAF, 0xD0, 0xDF, 0xF8, 0x2B, 0x2F,
+	0xFC, 0x9B, 0x8E, 0x8F, 0xFF, 0x00, 0x63, 0x9D, 0xAF, 0xFE, 0x92, 0xDE, 0xD7, 0xE7, 0x95, 0x28,
+	0x80, 0x51, 0x45, 0x14, 0xC0, 0x2B, 0xDE, 0xBF, 0xE0, 0x9B, 0x1F, 0xF2, 0x77, 0x3A, 0x0F, 0xFD,
+	0x83, 0xF5, 0x0F, 0xFD, 0x27, 0x7A, 0xF0, 0x5A, 0xF7, 0xAF, 0xF8, 0x26, 0xC7, 0xFC, 0x9D, 0xCE,
+	0x83, 0xFF, 0x00, 0x60, 0xFD, 0x43, 0xFF, 0x00, 0x49, 0xDE, 0x80, 0x3E, 0xC9, 0xFF, 0x00, 0x82,
+	0x88, 0xFF, 0x00, 0xC9, 0x9D, 0xF8, 0xC7, 0xFD, 0xCB, 0x2F, 0xFD, 0x38, 0x5A, 0xD7, 0xE5, 0xE5,
+	0x7E, 0xA1, 0xFF, 0x00, 0xC1, 0x44, 0x7F, 0xE4, 0xCE, 0xFC, 0x63, 0xFE, 0xE5, 0x97, 0xFE, 0x9C,
+	0x2D, 0x6B, 0xF2, 0xF2, 0x92, 0x00, 0xA2, 0x8A, 0x29, 0x80, 0x57, 0xA2, 0x7E, 0xC9, 0x5F, 0xF2,
+	0x73, 0x9E, 0x01, 0xFF, 0x00, 0xB1, 0xAA, 0xD3, 0xFF, 0x00, 0x42, 0x15, 0xE7, 0x75, 0xE8, 0x9F,
+	0xB2, 0x57, 0xFC, 0x9C, 0xE7, 0x80, 0x7F, 0xEC, 0x6A, 0xB4, 0xFF, 0x00, 0xD0, 0x85, 0x00, 0x7E,
+	0x97, 0x7E, 0xD4, 0xDF, 0xF2, 0x6C, 0x9F, 0x11, 0x7F, 0xEC, 0x45, 0xD5, 0xFF, 0x00, 0xF4, 0x82,
+	0x7A, 0xFC, 0x61, 0xAF, 0xD9, 0xEF, 0xDA, 0x9B, 0xFE, 0x4D, 0x93, 0xE2, 0x2F, 0xFD, 0x88, 0xBA,
+	0xBF, 0xFE, 0x90, 0x4F, 0x5F, 0x8C, 0x35, 0xCD, 0x59, 0x6C, 0x69, 0x4C, 0x28, 0xA2, 0x8A, 0xC6,
+	0xE6, 0x9A, 0x85, 0x7D, 0x19, 0xFF, 0x00, 0x04, 0xAA, 0xFF, 0x00, 0x93, 0xC5, 0xD2, 0xBF, 0xEC,
+	0x0F, 0x7F, 0xFF, 0x00, 0xA2, 0x1A, 0xBE, 0x73, 0xAF, 0xA3, 0x3F, 0xE0, 0x95, 0x5F, 0xF2, 0x78,
+	0xBA, 0x57, 0xFD, 0x81, 0xEF, 0xFF, 0x00, 0xF4, 0x43, 0x53, 0xA6, 0xDF, 0x3A, 0x26, 0x6D, 0xF2,
+	0x9F, 0x6A, 0xFF, 0x00, 0xC1, 0x4A, 0xBF, 0xE4, 0xD2, 0xB5, 0xEF, 0xFA, 0xFD, 0xB1, 0xFF, 0x00,
+	0xD2, 0x85, 0xAF, 0xCC, 0xAA, 0xFD, 0x35, 0xFF, 0x00, 0x82, 0x95, 0x7F, 0xC9, 0xA5, 0x6B, 0xDF,
+	0xF5, 0xFB, 0x63, 0xFF, 0x00, 0xA5, 0x0B, 0x5F, 0x99, 0x55, 0xDC, 0x62, 0x05, 0x53, 0x3B, 0x9F,
+	0xFB, 0x9B, 0xDB, 0xEA, 0x1B, 0x6A, 0xD7, 0xDE, 0x9F, 0x08, 0x3C, 0x3E, 0x3C, 0x2F, 0xF0, 0xA3,
+	0xC3, 0xFA, 0x03, 0xFF, 0x00, 0xAC, 0x8B, 0x4A, 0x85, 0x6E, 0x3F, 0xEB, 0xAC, 0x88, 0xAC, 0xDF,
+	0xA9, 0x35, 0xF0, 0xDF, 0x85, 0xB4, 0xA1, 0xAE, 0xF8, 0x9B, 0x4E, 0xD0, 0xD9, 0xF7, 0x7D, 0xBA,
+	0xF2, 0x2B, 0x7D, 0xBE, 0x9B, 0x9C, 0x0F, 0xFD, 0x9A, 0xBF, 0x42, 0x0C, 0x7E, 0x49, 0xF2, 0x40,
+	0xFB, 0xBC, 0x57, 0xF0, 0xBF, 0xD3, 0x43, 0x3B, 0xE5, 0xC2, 0x65, 0x79, 0x5A, 0x7B, 0xCA, 0x75,
+	0x1A, 0xF2, 0x4B, 0x95, 0x7E, 0x27, 0xDA, 0x70, 0x8D, 0x1B, 0xD4, 0xA9, 0x51, 0xF9, 0x20, 0x63,
+	0x96, 0x26, 0x8A, 0x28, 0xAF, 0xF3, 0xFD, 0xEA, 0xEE, 0x7D, 0xC0, 0x51, 0x45, 0x14, 0x00, 0x51,
+	0x45, 0x14, 0x00, 0x57, 0x8A, 0xFF, 0x00, 0xC1, 0x40, 0xFF, 0x00, 0xE4, 0xD4, 0x7C, 0x45, 0xFF,
+	0x00, 0x5F, 0x16, 0x7F, 0xFA, 0x57, 0x0D, 0x7B, 0x55, 0x78, 0xAF, 0xFC, 0x14, 0x0F, 0xFE, 0x4D,
+	0x47, 0xC4, 0x5F, 0xF5, 0xF1, 0x67, 0xFF, 0x00, 0xA5, 0x70, 0xD7, 0xEE, 0x3F, 0x46, 0xCF, 0xF9,
+	0x3E, 0xFC, 0x3D, 0xFF, 0x00, 0x61, 0x30, 0xFD, 0x4F, 0xCF, 0x7C, 0x54, 0xFF, 0x00, 0x93, 0x75,
+	0x9A, 0x7F, 0xD7, 0xA9, 0x7E, 0x87, 0xE7, 0x29, 0xEB, 0x45, 0x07, 0xAD, 0x15, 0xFF, 0x00, 0x4E,
+	0x67, 0xF9, 0x02, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x15, 0xEE, 0xBF, 0xB2, 0x57, 0xFC, 0x8B, 0xDA, 0xA7, 0xFD, 0x84, 0x23, 0xFF,
+	0x00, 0xD0, 0x6B, 0xC2, 0xAB, 0xDD, 0x7F, 0x64, 0xAF, 0xF9, 0x17, 0xB5, 0x4F, 0xFB, 0x08, 0x47,
+	0xFF, 0x00, 0xA0, 0xD7, 0xF2, 0x6F, 0xD3, 0x57, 0xFE, 0x4C, 0x1E, 0x33, 0xFE, 0xBE, 0x52, 0xFF,
+	0x00, 0xD2, 0x8F, 0xD8, 0x3C, 0x0F, 0xFF, 0x00, 0x93, 0x85, 0x43, 0xFC, 0x33, 0xFC, 0x8F, 0x56,
+	0x4F, 0xB8, 0x3E, 0x94, 0xB4, 0x89, 0xF7, 0x07, 0xD2, 0x96, 0xBF, 0xC3, 0xD3, 0xFB, 0xC0, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x2B,
+	0xF1, 0x97, 0xFE, 0x0B, 0x23, 0xFF, 0x00, 0x27, 0xE1, 0xE2, 0x6F, 0xFB, 0x05, 0xE9, 0xBF, 0xFA,
+	0x42, 0x95, 0xFB, 0x35, 0x5F, 0x8C, 0xBF, 0xF0, 0x59, 0x1F, 0xF9, 0x3F, 0x0F, 0x13, 0x7F, 0xD8,
+	0x2F, 0x4D, 0xFF, 0x00, 0xD2, 0x14, 0xAF, 0xE8, 0x4F, 0xA3, 0x6F, 0xFC, 0x97, 0x15, 0x7F, 0xEB,
+	0xD4, 0xBF, 0x34, 0x75, 0xE0, 0xFF, 0x00, 0x8A, 0x7C, 0xBC, 0xFF, 0x00, 0x7C, 0xFD, 0x6B, 0xEF,
+	0xDF, 0xF8, 0x36, 0x43, 0xFE, 0x53, 0x07, 0xE0, 0x1F, 0xFB, 0x00, 0xF8, 0x83, 0xFF, 0x00, 0x4D,
+	0x53, 0xD7, 0xC0, 0x4F, 0xF7, 0xCF, 0xD6, 0xBE, 0xFD, 0xFF, 0x00, 0x83, 0x64, 0x3F, 0xE5, 0x30,
+	0x7E, 0x01, 0xFF, 0x00, 0xB0, 0x0F, 0x88, 0x3F, 0xF4, 0xD5, 0x3D, 0x7F, 0x74, 0xC3, 0x73, 0xB2,
+	0xB7, 0xF0, 0xE4, 0x49, 0xFF, 0x00, 0x07, 0x3A, 0x7F, 0xCA, 0x61, 0x3C, 0x7B, 0xFF, 0x00, 0x60,
+	0x3D, 0x07, 0xFF, 0x00, 0x4D, 0xB6, 0xF5, 0xF9, 0xFA, 0x3A, 0x57, 0xE8, 0x17, 0xFC, 0x1C, 0xE9,
+	0xFF, 0x00, 0x29, 0x84, 0xF1, 0xEF, 0xFD, 0x80, 0xF4, 0x1F, 0xFD, 0x36, 0xDB, 0xD7, 0xE7, 0xE8,
+	0xE9, 0x4A, 0x5F, 0x11, 0x54, 0xFF, 0x00, 0x83, 0x11, 0x7D, 0x3F, 0xDD, 0x3F, 0xC9, 0xAB, 0xFA,
+	0x38, 0x7F, 0xBE, 0x7E, 0xB5, 0xFC, 0xE3, 0xFA, 0x7F, 0xBA, 0x7F, 0x93, 0x57, 0xF4, 0x70, 0xFF,
+	0x00, 0x7C, 0xFD, 0x6B, 0xD1, 0xC0, 0xED, 0x23, 0xF5, 0x7F, 0x0D, 0xB6, 0xAF, 0xF2, 0x12, 0x8A,
+	0x28, 0xAE, 0xF3, 0xF5, 0x40, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x03, 0xCB, 0xFF, 0x00, 0x6D, 0x4F, 0xF9, 0x35, 0xDF, 0x17, 0x7F, 0xD8,
+	0x39, 0x7F, 0xF4, 0x74, 0x55, 0xF9, 0x8E, 0xBF, 0x77, 0xF0, 0xAF, 0xD3, 0x8F, 0xDB, 0x53, 0xFE,
+	0x4D, 0x77, 0xC5, 0xDF, 0xF6, 0x0E, 0x5F, 0xFD, 0x1D, 0x15, 0x7E, 0x63, 0xAF, 0xDD, 0xFC, 0x2B,
+	0xF2, 0xCE, 0x36, 0xFF, 0x00, 0x91, 0x95, 0x3F, 0xF0, 0xFE, 0xA7, 0xF4, 0xE7, 0x82, 0x3F, 0xF2,
+	0x22, 0xAF, 0xFF, 0x00, 0x5F, 0x3F, 0x40, 0xA2, 0x8A, 0x2B, 0xE2, 0x8F, 0xDA, 0x02, 0x8A, 0x28,
+	0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x0E, 0x9B, 0xC2,
+	0x9F, 0xF2, 0x2B, 0x6A, 0x3F, 0xF6, 0x10, 0xB3, 0xFF, 0x00, 0xD1, 0x77, 0x14, 0xF5, 0xEF, 0xF4,
+	0xA6, 0x78, 0x53, 0xFE, 0x45, 0x6D, 0x47, 0xFE, 0xC2, 0x16, 0x7F, 0xFA, 0x2E, 0xE2, 0x9E, 0xBD,
+	0xFE, 0x95, 0xFD, 0xF5, 0xE0, 0x97, 0xFC, 0x9B, 0xBC, 0x37, 0xAC, 0xBF, 0x33, 0xFC, 0x03, 0xFA,
+	0x6B, 0x7F, 0xCA, 0x44, 0x66, 0x9E, 0x94, 0xFF, 0x00, 0xF4, 0x91, 0x28, 0xA2, 0x8A, 0xFD, 0x68,
+	0xFE, 0x4F, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x2D, 0xE9, 0xF7, 0x73, 0x69, 0xD7,
+	0xB0, 0xEA, 0x36, 0xDF, 0xEB, 0x21, 0x99, 0x5E, 0x3F, 0xF7, 0x80, 0x5F, 0xE9, 0x5F, 0x78, 0xE9,
+	0x5A, 0x9C, 0x3A, 0xCE, 0x99, 0x6F, 0xAC, 0x5B, 0xFF, 0x00, 0xAB, 0xBB, 0xB7, 0x49, 0xA3, 0xFF,
+	0x00, 0x75, 0x94, 0x30, 0xFE, 0x75, 0xF0, 0x20, 0xF4, 0xCF, 0xBD, 0x7D, 0xA3, 0xFB, 0x3E, 0xEB,
+	0x9F, 0xDB, 0x7F, 0x06, 0x3C, 0x3B, 0x77, 0xFF, 0x00, 0x3C, 0x6C, 0x16, 0x2F, 0xFB, 0xF1, 0x27,
+	0x97, 0xFD, 0x2B, 0xF1, 0x9F, 0x18, 0x30, 0xB7, 0xC0, 0xE1, 0xF1, 0x09, 0x7C, 0x2D, 0xC5, 0xFA,
+	0x35, 0xFE, 0x67, 0xED, 0x1E, 0x0F, 0x63, 0x39, 0x71, 0xD8, 0x8C, 0x33, 0xD9, 0xA5, 0x2F, 0x9A,
+	0x7F, 0xE4, 0x76, 0x55, 0xFA, 0x69, 0xFF, 0x00, 0x04, 0xD5, 0xFF, 0x00, 0x93, 0x47, 0xD0, 0xFF,
+	0x00, 0xEB, 0xFA, 0xFF, 0x00, 0xFF, 0x00, 0x4A, 0x5A, 0xBF, 0x32, 0xCA, 0xED, 0xF9, 0x7D, 0x38,
+	0xAF, 0xD3, 0x4F, 0xF8, 0x26, 0xAF, 0xFC, 0x9A, 0x3E, 0x87, 0xFF, 0x00, 0x5F, 0xD7, 0xFF, 0x00,
+	0xFA, 0x52, 0xD5, 0xF8, 0x29, 0xFD, 0x00, 0x79, 0x2F, 0xED, 0x9B, 0xFF, 0x00, 0x25, 0xF3, 0x50,
+	0xFF, 0x00, 0xAF, 0x5B, 0x4F, 0xFD, 0x17, 0x5E, 0x52, 0x31, 0x8E, 0x2B, 0xD5, 0xBF, 0x6C, 0xDF,
+	0xF9, 0x2F, 0x9A, 0x87, 0xFD, 0x7A, 0xDA, 0x7F, 0xE8, 0xBA, 0xF2, 0x91, 0xD2, 0xBF, 0xCA, 0xEF,
+	0x15, 0x3F, 0xE4, 0xE2, 0x66, 0x6B, 0xFE, 0x9E, 0xCB, 0xF4, 0x3F, 0xA4, 0x38, 0x67, 0x4E, 0x1F,
+	0xC3, 0x5B, 0xF9, 0x17, 0xE2, 0x14, 0x51, 0x45, 0x7E, 0x7B, 0x73, 0xDC, 0x0E, 0xDD, 0x2B, 0xF4,
+	0x13, 0xE0, 0x90, 0xC7, 0xC1, 0xCF, 0x09, 0x9C, 0xFF, 0x00, 0xCC, 0xB9, 0x65, 0xFF, 0x00, 0xA2,
+	0x12, 0xBF, 0x3E, 0xEB, 0xF4, 0x13, 0xE0, 0x97, 0xFC, 0x91, 0xBF, 0x09, 0xFF, 0x00, 0xD8, 0xB7,
+	0x65, 0xFF, 0x00, 0xA2, 0x12, 0xBF, 0xAC, 0x7E, 0x89, 0xFF, 0x00, 0xF2, 0x50, 0x66, 0x3F, 0xF5,
+	0xEA, 0x1F, 0xFA, 0x59, 0xF9, 0x8F, 0x89, 0x7F, 0xEE, 0x78, 0x7F, 0xF1, 0x4B, 0xF2, 0x47, 0xE6,
+	0x4F, 0xED, 0xA7, 0xFF, 0x00, 0x27, 0x5D, 0xE3, 0x6F, 0xFB, 0x0E, 0x1F, 0xFD, 0x05, 0x6B, 0xCB,
+	0x13, 0xEE, 0x0F, 0xA5, 0x7A, 0x9F, 0xED, 0xA7, 0xFF, 0x00, 0x27, 0x5D, 0xE3, 0x6F, 0xFB, 0x0E,
+	0x1F, 0xFD, 0x05, 0x6B, 0xCB, 0x13, 0xEE, 0x0F, 0xA5, 0x7F, 0x71, 0x1F, 0x90, 0x8B, 0x45, 0x14,
+	0x50, 0x01, 0x5F, 0x7A, 0x7F, 0xC1, 0x22, 0x17, 0x7F, 0xC3, 0x2F, 0x18, 0xA9, 0xFF, 0x00, 0xA0,
+	0xE4, 0x1D, 0x47, 0xFD, 0x31, 0xAF, 0x82, 0xEB, 0xEF, 0x4F, 0xF8, 0x24, 0x2F, 0xFC, 0x93, 0x5F,
+	0x18, 0x7F, 0xD8, 0x72, 0x0F, 0xFD, 0x13, 0x40, 0x1E, 0x3D, 0xFF, 0x00, 0x05, 0x51, 0xFF, 0x00,
+	0x93, 0x99, 0xB7, 0xFF, 0x00, 0xB1, 0x62, 0xD7, 0xFF, 0x00, 0x43, 0x96, 0xBE, 0x6C, 0xAF, 0xA4,
+	0xFF, 0x00, 0xE0, 0xAA, 0x3F, 0xF2, 0x73, 0x36, 0xFF, 0x00, 0xF6, 0x2C, 0x5A, 0xFF, 0x00, 0xE8,
+	0x72, 0xD7, 0xCD, 0x94, 0x00, 0x51, 0x45, 0x14, 0x00, 0x76, 0xFC, 0x2B, 0xEE, 0x6F, 0xF8, 0x24,
+	0x1A, 0xEF, 0xF0, 0xD7, 0x8F, 0x94, 0xFF, 0x00, 0xD0, 0x42, 0xC3, 0xA8, 0xFF, 0x00, 0xA6, 0x73,
+	0x57, 0xC3, 0x3D, 0xBF, 0x0A, 0xFB, 0xA3, 0xFE, 0x09, 0x01, 0xFF, 0x00, 0x22, 0xE7, 0x8F, 0xBF,
+	0xEC, 0x21, 0x61, 0xFF, 0x00, 0xA2, 0xE6, 0xA0, 0x0F, 0x2A, 0xFF, 0x00, 0x82, 0xA8, 0xFF, 0x00,
+	0xC9, 0xCC, 0xDB, 0xFF, 0x00, 0xD8, 0xB1, 0x6B, 0xFF, 0x00, 0xA1, 0xCB, 0x5F, 0x36, 0x57, 0xD2,
+	0x7F, 0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B, 0x7F, 0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6,
+	0xCA, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x3B, 0x7E, 0x15, 0xF7, 0x37, 0xFC, 0x12, 0x0F, 0xFE, 0x45,
+	0xDF, 0x1E, 0x7F, 0xD8, 0x42, 0xC7, 0xFF, 0x00, 0x45, 0xCD, 0x5F, 0x0C, 0xF6, 0xFC, 0x2B, 0xEE,
+	0x6F, 0xF8, 0x24, 0x1F, 0xFC, 0x8B, 0xBE, 0x3C, 0xFF, 0x00, 0xB0, 0x85, 0x8F, 0xFE, 0x8B, 0x9A,
+	0x80, 0x3E, 0xCA, 0x83, 0xF8, 0xBF, 0xDE, 0x1F, 0xFA, 0x08, 0xA9, 0x2A, 0x38, 0x3F, 0x8B, 0xFD,
+	0xE1, 0xFF, 0x00, 0xA0, 0x8A, 0x92, 0x80, 0x0A, 0x0F, 0x4A, 0x28, 0x3C, 0x8C, 0x50, 0x07, 0xC2,
+	0x9F, 0xF0, 0x57, 0xDF, 0xF9, 0x19, 0x3C, 0x0F, 0xFF, 0x00, 0x5E, 0x57, 0xDF, 0xFA, 0x32, 0x3A,
+	0xF8, 0xDA, 0xBE, 0xD0, 0xFF, 0x00, 0x82, 0xBA, 0xE9, 0xBA, 0x86, 0xA3, 0xE2, 0x4F, 0x03, 0x8D,
+	0x3F, 0x4F, 0x96, 0xE0, 0xAD, 0x8D, 0xF6, 0x7C, 0xBB, 0x72, 0xDB, 0x7E, 0x78, 0x7D, 0x2B, 0xE3,
+	0xAF, 0xF8, 0x46, 0xFC, 0x49, 0xFF, 0x00, 0x40, 0x2B, 0xDF, 0xFC, 0x05, 0x96, 0x80, 0x2A, 0x51,
+	0x56, 0xFF, 0x00, 0xE1, 0x1B, 0xF1, 0x27, 0xFD, 0x00, 0xAF, 0x7F, 0xF0, 0x16, 0x5A, 0x3F, 0xE1,
+	0x1B, 0xF1, 0x27, 0xFD, 0x00, 0xAF, 0x7F, 0xF0, 0x16, 0x5A, 0x00, 0xA8, 0x3A, 0xD7, 0xD6, 0x1F,
+	0xF0, 0x48, 0xFF, 0x00, 0xF9, 0x2D, 0x5E, 0x25, 0xFF, 0x00, 0xB1, 0x55, 0x7F, 0xF4, 0xA6, 0x2A,
+	0xF9, 0x6D, 0x3C, 0x35, 0xE2, 0x4D, 0xEB, 0x9D, 0x06, 0xFB, 0xAF, 0xFC, 0xFA, 0xC9, 0xFD, 0x6B,
+	0xEA, 0xCF, 0xF8, 0x24, 0xDE, 0x97, 0xAA, 0x69, 0xBF, 0x19, 0xFC, 0x44, 0x6F, 0xF4, 0xC9, 0xAD,
+	0x83, 0x78, 0x54, 0x6D, 0xF3, 0xA3, 0xFB, 0xDF, 0xE9, 0x31, 0x50, 0x07, 0xAA, 0xFF, 0x00, 0xC1,
+	0x59, 0x7F, 0xE4, 0xDC, 0x74, 0x7F, 0xFB, 0x1C, 0xED, 0x7F, 0xF4, 0x96, 0xF6, 0xBF, 0x3C, 0xAB,
+	0xF4, 0x43, 0xFE, 0x0A, 0xB9, 0x65, 0x77, 0x7F, 0xFB, 0x3C, 0x68, 0xD6, 0xF6, 0x56, 0x6F, 0x71,
+	0x27, 0xFC, 0x26, 0x76, 0xA7, 0xCB, 0x8E, 0x2D, 0xE4, 0xFF, 0x00, 0xA2, 0xDE, 0xF6, 0xAF, 0xCF,
+	0xAF, 0xF8, 0x46, 0xFC, 0x49, 0xFF, 0x00, 0x40, 0x2B, 0xDF, 0xFC, 0x05, 0x96, 0x92, 0x02, 0xA5,
+	0x15, 0x6F, 0xFE, 0x11, 0xBF, 0x12, 0x7F, 0xD0, 0x0A, 0xF7, 0xFF, 0x00, 0x01, 0x65, 0xA3, 0xFE,
+	0x11, 0xBF, 0x12, 0x7F, 0xD0, 0x0A, 0xF7, 0xFF, 0x00, 0x01, 0x65, 0xA6, 0x05, 0x4A, 0xF7, 0xAF,
+	0xF8, 0x26, 0xC7, 0xFC, 0x9D, 0xCE, 0x83, 0xFF, 0x00, 0x60, 0xFD, 0x43, 0xFF, 0x00, 0x49, 0xDE,
+	0xBC, 0x43, 0xFE, 0x11, 0xBF, 0x12, 0x7F, 0xD0, 0x0A, 0xF7, 0xFF, 0x00, 0x01, 0x65, 0xAF, 0x79,
+	0xFF, 0x00, 0x82, 0x71, 0x68, 0xDA, 0xC6, 0x9F, 0xFB, 0x5A, 0x68, 0x33, 0xDE, 0x68, 0xF7, 0x16,
+	0xE9, 0xF6, 0x1D, 0x43, 0xF7, 0x93, 0x47, 0xFF, 0x00, 0x4E, 0xEF, 0x40, 0x1F, 0x5F, 0xFF, 0x00,
+	0xC1, 0x44, 0x7F, 0xE4, 0xCE, 0xFC, 0x63, 0xFE, 0xE5, 0x97, 0xFE, 0x9C, 0x2D, 0x6B, 0xF2, 0xF2,
+	0xBF, 0x51, 0x7F, 0xE0, 0xA1, 0x90, 0x4D, 0x73, 0xFB, 0x20, 0x78, 0xBE, 0x0B, 0x78, 0x1A, 0x47,
+	0x65, 0xB1, 0xDB, 0x1A, 0xA6, 0xE2, 0x7F, 0xE2, 0x63, 0x6B, 0xDA, 0xBF, 0x31, 0x8F, 0x86, 0xBC,
+	0x48, 0x0E, 0x3F, 0xB0, 0x2F, 0x17, 0xDB, 0xEC, 0xB2, 0x71, 0xF9, 0x52, 0x40, 0x53, 0xA2, 0xAD,
+	0xFF, 0x00, 0xC2, 0x37, 0xE2, 0x4F, 0xFA, 0x01, 0x5E, 0xFF, 0x00, 0xE0, 0x2C, 0xB4, 0x7F, 0xC2,
+	0x37, 0xE2, 0x4F, 0xFA, 0x01, 0x5E, 0xFF, 0x00, 0xE0, 0x2C, 0xB4, 0xC0, 0xA9, 0x5E, 0x89, 0xFB,
+	0x25, 0x7F, 0xC9, 0xCE, 0x78, 0x07, 0xFE, 0xC6, 0xAB, 0x4F, 0xFD, 0x08, 0x57, 0x0D, 0xFF, 0x00,
+	0x08, 0xDF, 0x89, 0x3F, 0xE8, 0x05, 0x7B, 0xFF, 0x00, 0x80, 0xB2, 0xD7, 0xA2, 0xFE, 0xCA, 0x1A,
+	0x0E, 0xB9, 0x69, 0xFB, 0x4A, 0xF8, 0x0E, 0xE2, 0xE7, 0x43, 0xBA, 0x8E, 0x31, 0xE2, 0xAB, 0x3D,
+	0xD2, 0xCB, 0x19, 0xC0, 0xF9, 0x87, 0xAD, 0x00, 0x7E, 0x91, 0x7E, 0xD4, 0xDF, 0xF2, 0x6C, 0x9F,
+	0x11, 0x7F, 0xEC, 0x45, 0xD5, 0xFF, 0x00, 0xF4, 0x82, 0x7A, 0xFC, 0x61, 0xAF, 0xD9, 0xEF, 0xDA,
+	0x98, 0xE7, 0xF6, 0x65, 0xF8, 0x8A, 0x73, 0xFF, 0x00, 0x32, 0x2E, 0xB1, 0xFF, 0x00, 0xA4, 0x13,
+	0xD7, 0xE3, 0x0D, 0x73, 0xD6, 0xBE, 0x86, 0x94, 0xC2, 0x8A, 0x28, 0xAE, 0x73, 0x4B, 0x85, 0x7D,
+	0x19, 0xFF, 0x00, 0x04, 0xAA, 0xFF, 0x00, 0x93, 0xC5, 0xD2, 0xBF, 0xEC, 0x0F, 0x7F, 0xFF, 0x00,
+	0xA2, 0x1A, 0xBE, 0x73, 0xAF, 0xA3, 0x3F, 0xE0, 0x95, 0x7F, 0xF2, 0x78, 0xBA, 0x57, 0xFD, 0x81,
+	0xEF, 0xFF, 0x00, 0xF4, 0x43, 0x55, 0x43, 0x49, 0xA2, 0x65, 0xF0, 0x9F, 0x6A, 0xFF, 0x00, 0xC1,
+	0x4A, 0xBF, 0xE4, 0xD2, 0xB5, 0xEF, 0xFA, 0xFD, 0xB1, 0xFF, 0x00, 0xD2, 0x85, 0xAF, 0xCC, 0xAA,
+	0xFD, 0x38, 0xFF, 0x00, 0x82, 0x92, 0x5B, 0x4D, 0x77, 0xFB, 0x26, 0xEB, 0xB0, 0x5A, 0xDB, 0xC9,
+	0x2C, 0x8D, 0x7D, 0x63, 0x85, 0x8E, 0x3D, 0xDF, 0xF2, 0xF0, 0x95, 0xF9, 0xA5, 0xFF, 0x00, 0x08,
+	0xD7, 0x89, 0x57, 0x83, 0xA1, 0x5E, 0xFF, 0x00, 0xE0, 0x2C, 0x9F, 0xD2, 0xBB, 0x8C, 0x4E, 0xBF,
+	0xF6, 0x68, 0xD2, 0x3F, 0xB6, 0xBE, 0x3A, 0x78, 0x76, 0xCB, 0xFB, 0x97, 0x9E, 0x77, 0xFD, 0xFB,
+	0x8D, 0xE4, 0xFF, 0x00, 0xD9, 0x6B, 0xED, 0xED, 0xFE, 0x61, 0xDF, 0x8F, 0xBD, 0xCD, 0x7C, 0x99,
+	0xFB, 0x1B, 0x78, 0x63, 0x56, 0x4F, 0x8C, 0x27, 0x52, 0xD4, 0x34, 0x9B, 0x98, 0x62, 0xB1, 0xD2,
+	0x2E, 0x27, 0x56, 0x92, 0xDC, 0xAF, 0xCD, 0xFB, 0xB4, 0xEF, 0xFE, 0xFD, 0x7D, 0x67, 0x82, 0x07,
+	0x27, 0xA5, 0x7F, 0x99, 0x9F, 0x4C, 0x0C, 0xC3, 0xEB, 0x3E, 0x23, 0x51, 0xC2, 0x5F, 0xF8, 0x54,
+	0x63, 0xFF, 0x00, 0x93, 0xBB, 0x9F, 0xA2, 0x70, 0x9D, 0x3E, 0x5C, 0xBD, 0xC9, 0xF5, 0x7F, 0x90,
+	0x51, 0x45, 0x15, 0xFC, 0x97, 0xCA, 0x7D, 0x40, 0x51, 0x45, 0x14, 0x58, 0x02, 0x8A, 0x28, 0xA2,
+	0xC1, 0xA8, 0x57, 0x8A, 0xFF, 0x00, 0xC1, 0x40, 0xFF, 0x00, 0xE4, 0xD4, 0xBC, 0x45, 0xFF, 0x00,
+	0x5F, 0x16, 0x7F, 0xFA, 0x57, 0x0D, 0x7B, 0x51, 0x19, 0x18, 0x0F, 0xCD, 0x78, 0xAF, 0xFC, 0x14,
+	0x0F, 0xFE, 0x4D, 0x4B, 0xC4, 0x5C, 0x7F, 0xCB, 0xC5, 0x9F, 0xFE, 0x95, 0xC3, 0x5F, 0xB8, 0xFD,
+	0x1B, 0x55, 0xBC, 0x76, 0xE1, 0xE7, 0xFF, 0x00, 0x51, 0x30, 0xFD, 0x4F, 0xCF, 0x7C, 0x55, 0xFF,
+	0x00, 0x93, 0x75, 0x9A, 0x7F, 0xD7, 0x99, 0x1F, 0x9C, 0xA7, 0xAD, 0x14, 0x37, 0x5A, 0x2B, 0xFE,
+	0x9C, 0xF9, 0x4F, 0xF2, 0x04, 0x28, 0xA2, 0x8A, 0x2C, 0x01, 0x45, 0x14, 0x51, 0x60, 0x0A, 0x28,
+	0xA2, 0x8B, 0x00, 0x51, 0x45, 0x14, 0x58, 0x02, 0xBD, 0xD7, 0xF6, 0x4A, 0xFF, 0x00, 0x91, 0x7B,
+	0x54, 0xFF, 0x00, 0xB0, 0x84, 0x7F, 0xFA, 0x0D, 0x78, 0x66, 0x06, 0xCC, 0xFB, 0xD7, 0xBA, 0x7E,
+	0xC9, 0x7C, 0x78, 0x7B, 0x54, 0xFF, 0x00, 0xB0, 0x84, 0x7F, 0xFA, 0x05, 0x7F, 0x27, 0x7D, 0x35,
+	0x3F, 0xE4, 0xC2, 0x63, 0x17, 0xFD, 0x3C, 0xA5, 0xFF, 0x00, 0xA5, 0x33, 0xF6, 0x0F, 0x03, 0xFF,
+	0x00, 0xE4, 0xE0, 0xD0, 0xFF, 0x00, 0x0C, 0xFF, 0x00, 0x24, 0x7A, 0xAA, 0x7D, 0xC1, 0xF4, 0xA5,
+	0xA4, 0x5F, 0xBA, 0x38, 0xED, 0x4B, 0x5F, 0xE1, 0xD9, 0xFD, 0xE0, 0x14, 0x51, 0x45, 0x01, 0xA8,
+	0x51, 0x45, 0x14, 0xC3, 0x50, 0xA2, 0x8A, 0x29, 0x06, 0xA1, 0x45, 0x14, 0x50, 0x1A, 0x85, 0x7E,
+	0x32, 0xFF, 0x00, 0xC1, 0x64, 0x7F, 0xE4, 0xFC, 0x3C, 0x4D, 0xFF, 0x00, 0x60, 0xBD, 0x37, 0xFF,
+	0x00, 0x48, 0x52, 0xBF, 0x66, 0xAB, 0xF1, 0x97, 0xFE, 0x0B, 0x22, 0x7F, 0xE3, 0x3C, 0x3C, 0x4D,
+	0xFF, 0x00, 0x60, 0xCD, 0x37, 0xFF, 0x00, 0x48, 0x52, 0xBF, 0xA1, 0xBE, 0x8D, 0xBF, 0xF2, 0x5B,
+	0xD5, 0x7F, 0xF4, 0xEA, 0x5F, 0x9A, 0x3A, 0xF0, 0x7F, 0xC4, 0xD0, 0xF9, 0x79, 0xFE, 0xF9, 0xFA,
+	0xD7, 0xDF, 0xBF, 0xF0, 0x6C, 0x87, 0xFC, 0xA6, 0x0F, 0xC0, 0x3F, 0xF6, 0x01, 0xF1, 0x07, 0xFE,
+	0x9A, 0xA7, 0xAF, 0x80, 0x9F, 0xEF, 0x9F, 0xAD, 0x7D, 0xFB, 0xFF, 0x00, 0x06, 0xC8, 0x7F, 0xCA,
+	0x60, 0xFC, 0x03, 0xFF, 0x00, 0x60, 0x1F, 0x10, 0x7F, 0xE9, 0xAA, 0x7A, 0xFE, 0xE8, 0x87, 0xC4,
+	0x76, 0x56, 0xFE, 0x1C, 0x89, 0x3F, 0xE0, 0xE7, 0x4F, 0xF9, 0x4C, 0x27, 0x8F, 0x7F, 0xEC, 0x07,
+	0xA0, 0xFF, 0x00, 0xE9, 0xB6, 0xDE, 0xBF, 0x3F, 0x47, 0x4A, 0xFD, 0x02, 0xFF, 0x00, 0x83, 0x9D,
+	0x3F, 0xE5, 0x30, 0x9E, 0x3D, 0xFF, 0x00, 0xB0, 0x1E, 0x83, 0xFF, 0x00, 0xA6, 0xDB, 0x7A, 0xFC,
+	0xFD, 0x1D, 0x2A, 0x65, 0xF1, 0x15, 0x4F, 0xF8, 0x31, 0x17, 0xD3, 0xFD, 0xD3, 0xFC, 0x9A, 0xBF,
+	0xA3, 0x87, 0xFB, 0xE7, 0xEB, 0x5F, 0xCE, 0x3F, 0xA7, 0xFB, 0xA7, 0xF9, 0x35, 0x7F, 0x47, 0x0F,
+	0xF7, 0xCF, 0xD6, 0xBD, 0x1C, 0x06, 0xA9, 0xD8, 0xFD, 0x5F, 0xC3, 0x5D, 0x63, 0x5E, 0xDE, 0x42,
+	0x51, 0x45, 0x15, 0xDF, 0xA9, 0xFA, 0xA5, 0xD0, 0x51, 0x45, 0x14, 0x05, 0xD0, 0x51, 0x45, 0x14,
+	0xAE, 0x1E, 0x41, 0x45, 0x14, 0x53, 0x0B, 0xA0, 0xA2, 0x8A, 0x28, 0x0B, 0xA3, 0xCB, 0xFF, 0x00,
+	0x6D, 0x4F, 0xF9, 0x35, 0xDF, 0x17, 0x7F, 0xD8, 0x39, 0x7F, 0xF4, 0x74, 0x55, 0xF9, 0x8E, 0xBF,
+	0x77, 0xF0, 0xAF, 0xD3, 0x8F, 0xDB, 0x53, 0xFE, 0x4D, 0x77, 0xC5, 0xDF, 0xF6, 0x0F, 0x5F, 0xFD,
+	0x1D, 0x1D, 0x7E, 0x63, 0xAF, 0x20, 0x02, 0x6B, 0xF2, 0xBE, 0x38, 0xF7, 0x73, 0x2A, 0x7F, 0xE1,
+	0xFD, 0x4F, 0xE9, 0xAF, 0x04, 0xDD, 0xB2, 0x1A, 0xFF, 0x00, 0xE3, 0xFD, 0x02, 0x8A, 0x71, 0xDA,
+	0x0E, 0x31, 0x49, 0x95, 0xFE, 0xED, 0x7C, 0x59, 0xFB, 0x55, 0x84, 0xA2, 0x97, 0x2B, 0xFD, 0xDA,
+	0x32, 0xBF, 0xDD, 0xA0, 0x04, 0xA2, 0x97, 0x2B, 0xFD, 0xDA, 0x32, 0xBF, 0xDD, 0xA0, 0x04, 0xA2,
+	0x97, 0x2B, 0xFD, 0xDA, 0x32, 0xBF, 0xDD, 0xA0, 0x04, 0xA2, 0x97, 0x2B, 0xFD, 0xDA, 0x32, 0xBF,
+	0xDD, 0xA0, 0x0E, 0x97, 0xC2, 0x9F, 0xF2, 0x2B, 0x6A, 0x3F, 0xF6, 0x10, 0xB3, 0xFF, 0x00, 0xD1,
+	0x77, 0x14, 0xF5, 0xFE, 0x94, 0x9E, 0x13, 0xFF, 0x00, 0x91, 0x5F, 0x51, 0x38, 0xFF, 0x00, 0x98,
+	0x85, 0x9F, 0xFE, 0x8B, 0xB8, 0xA7, 0x0D, 0xDB, 0x4B, 0x8A, 0xFE, 0xFA, 0xF0, 0x4B, 0xFE, 0x4D,
+	0xDE, 0x17, 0xD6, 0x5F, 0x99, 0xFE, 0x01, 0xFD, 0x35, 0x97, 0xFC, 0x74, 0x3E, 0x6A, 0xFC, 0xA9,
+	0xFF, 0x00, 0xE9, 0x23, 0x68, 0xA3, 0xEB, 0x45, 0x7E, 0xB4, 0x7F, 0x28, 0xF2, 0x85, 0x18, 0x23,
+	0xA8, 0xA3, 0x9E, 0xC6, 0x94, 0x96, 0xEE, 0x68, 0xD3, 0x51, 0x09, 0x45, 0x14, 0x50, 0x16, 0x15,
+	0x79, 0x38, 0xAF, 0xAB, 0x3F, 0x63, 0x2D, 0x4D, 0xEE, 0xFE, 0x14, 0xB5, 0x81, 0xFF, 0x00, 0x97,
+	0x1D, 0x62, 0x68, 0xFF, 0x00, 0x35, 0x8A, 0x6F, 0xFD, 0x9A, 0xBE, 0x54, 0x0C, 0xC3, 0x91, 0x5F,
+	0x49, 0x7E, 0xC1, 0xC9, 0xAA, 0x6A, 0xBA, 0x67, 0x88, 0xB4, 0x8D, 0x3E, 0xCA, 0xE2, 0x6F, 0x26,
+	0xE2, 0xD2, 0x56, 0x11, 0xC7, 0xBB, 0xFD, 0x68, 0x95, 0x7F, 0xF6, 0x95, 0x7E, 0x79, 0xE2, 0x75,
+	0x15, 0x5F, 0x85, 0x64, 0xDA, 0xF8, 0x65, 0x17, 0xF2, 0x3F, 0x44, 0xF0, 0xBF, 0x10, 0xE8, 0xF1,
+	0x54, 0x17, 0xF3, 0x46, 0x4B, 0xE7, 0xA1, 0xEE, 0x00, 0x6D, 0x1B, 0x7D, 0x2B, 0xF4, 0xD3, 0xFE,
+	0x09, 0xAB, 0xFF, 0x00, 0x26, 0x8F, 0xA1, 0xFF, 0x00, 0xD7, 0xF5, 0xFF, 0x00, 0xFE, 0x94, 0xB5,
+	0x7E, 0x6A, 0x8F, 0x0D, 0x78, 0x94, 0x0C, 0x1D, 0x02, 0xF8, 0x7B, 0x7D, 0x96, 0x4E, 0x3F, 0x2A,
+	0xFD, 0x2E, 0xFF, 0x00, 0x82, 0x6F, 0x59, 0xDC, 0xD9, 0xFE, 0xC9, 0xDA, 0x0D, 0xB5, 0xD5, 0xB4,
+	0x90, 0xC9, 0xF6, 0xDB, 0xE6, 0xDB, 0x20, 0x23, 0xFE, 0x5E, 0x9F, 0xD6, 0xBF, 0x98, 0x8F, 0xEA,
+	0x33, 0xC8, 0x7F, 0x6C, 0xDF, 0xF9, 0x2F, 0x9A, 0x87, 0xFD, 0x7A, 0xDA, 0x7F, 0xE8, 0xBA, 0xF2,
+	0x91, 0xD2, 0xBD, 0x57, 0xF6, 0xCC, 0x62, 0xDF, 0x1E, 0xB5, 0x06, 0x23, 0xFE, 0x5D, 0x6D, 0x3F,
+	0xF4, 0x5D, 0x79, 0x50, 0xE9, 0x5F, 0xE5, 0x9F, 0x8A, 0x98, 0x7A, 0xD2, 0xF1, 0x13, 0x32, 0x7C,
+	0xAF, 0xF8, 0xB2, 0xE8, 0xFC, 0x8F, 0xE8, 0xDE, 0x19, 0xA9, 0x4F, 0xFB, 0x07, 0x0E, 0xAF, 0xAF,
+	0x22, 0x0A, 0x28, 0xA2, 0xBF, 0x3E, 0xFA, 0xB6, 0x23, 0xF9, 0x1F, 0xDC, 0xCF, 0x73, 0xDA, 0x53,
+	0xFE, 0x65, 0xF7, 0x85, 0x7E, 0x82, 0x7C, 0x12, 0xFF, 0x00, 0x92, 0x37, 0xE1, 0x3F, 0xFB, 0x16,
+	0xEC, 0xBF, 0xF4, 0x42, 0x57, 0xE7, 0xDD, 0x7E, 0x82, 0x7C, 0x12, 0xFF, 0x00, 0x92, 0x37, 0xE1,
+	0x4F, 0xFB, 0x16, 0xEC, 0xBF, 0xF4, 0x42, 0x57, 0xF5, 0x7F, 0xD1, 0x4A, 0x95, 0x4A, 0x59, 0xFE,
+	0x62, 0xE7, 0x16, 0xBF, 0x75, 0x0D, 0xD3, 0xFE, 0x73, 0xF3, 0x2F, 0x12, 0xA5, 0x09, 0x60, 0xF0,
+	0xE9, 0x3F, 0xB4, 0xFF, 0x00, 0x24, 0x7E, 0x64, 0xFE, 0xDA, 0x7F, 0xF2, 0x75, 0xDE, 0x36, 0xFF,
+	0x00, 0xB0, 0xE1, 0xFF, 0x00, 0xD0, 0x56, 0xBC, 0xB1, 0x3E, 0xE0, 0xFA, 0x57, 0xAE, 0xFE, 0xD9,
+	0x9A, 0x0E, 0xB3, 0x75, 0xFB, 0x53, 0xF8, 0xD9, 0xED, 0x74, 0x5B, 0xC6, 0x56, 0xD7, 0x89, 0x56,
+	0x5B, 0x69, 0x08, 0x3F, 0x2A, 0x72, 0x31, 0x5E, 0x5C, 0x3C, 0x35, 0xE2, 0x55, 0x1B, 0x4E, 0x83,
+	0x7B, 0xFF, 0x00, 0x80, 0xB2, 0xD7, 0xF6, 0xF1, 0xF9, 0x19, 0x52, 0x8A, 0xB7, 0xFF, 0x00, 0x08,
+	0xDF, 0x89, 0x3F, 0xE8, 0x05, 0x7B, 0xFF, 0x00, 0x80, 0xB2, 0xD1, 0xFF, 0x00, 0x08, 0xDF, 0x89,
+	0x3F, 0xE8, 0x05, 0x7B, 0xFF, 0x00, 0x80, 0xB2, 0xD0, 0x05, 0x4A, 0xFB, 0xD3, 0xFE, 0x09, 0x0B,
+	0xFF, 0x00, 0x24, 0xD7, 0xC6, 0x1F, 0xF6, 0x1C, 0x83, 0xFF, 0x00, 0x44, 0xD7, 0xC2, 0xDF, 0xF0,
+	0x8D, 0xF8, 0x93, 0xFE, 0x80, 0x57, 0xBF, 0xF8, 0x0B, 0x2D, 0x7D, 0xDF, 0xFF, 0x00, 0x04, 0x8F,
+	0xD3, 0xEF, 0xB4, 0xFF, 0x00, 0x86, 0xFE, 0x30, 0x4B, 0xEB, 0x19, 0x2D, 0xD9, 0xB5, 0xC8, 0x08,
+	0x59, 0x10, 0xAE, 0x7F, 0x70, 0x39, 0xE6, 0x80, 0x3C, 0x63, 0xFE, 0x0A, 0xA3, 0xFF, 0x00, 0x27,
+	0x33, 0x6F, 0xFF, 0x00, 0x62, 0xC5, 0xAF, 0xFE, 0x87, 0x2D, 0x7C, 0xD9, 0x5F, 0x4E, 0x7F, 0xC1,
+	0x52, 0xB4, 0x8D, 0x56, 0xFF, 0x00, 0xF6, 0x98, 0x86, 0x5B, 0x0D, 0x32, 0x7B, 0x85, 0x5F, 0x0C,
+	0x5A, 0xE5, 0xE3, 0xB6, 0x2D, 0x8F, 0xDE, 0x4D, 0xDC, 0x73, 0x5F, 0x37, 0x7F, 0xC2, 0x37, 0xE2,
+	0x4F, 0xFA, 0x01, 0x5E, 0xFF, 0x00, 0xE0, 0x2C, 0xB4, 0x01, 0x52, 0x8A, 0xB7, 0xFF, 0x00, 0x08,
+	0xDF, 0x89, 0x3F, 0xE8, 0x05, 0x7B, 0xFF, 0x00, 0x80, 0xB2, 0xD1, 0xFF, 0x00, 0x08, 0xDF, 0x89,
+	0x3F, 0xE8, 0x05, 0x7B, 0xFF, 0x00, 0x80, 0xB2, 0xD0, 0x05, 0x4E, 0xDF, 0x85, 0x7D, 0xD1, 0xFF,
+	0x00, 0x04, 0x80, 0xFF, 0x00, 0x91, 0x73, 0xC7, 0xDF, 0xF6, 0x10, 0xB0, 0xFF, 0x00, 0xD1, 0x73,
+	0x57, 0xC4, 0x63, 0xC3, 0x5E, 0x24, 0x39, 0x07, 0x40, 0xBE, 0x3F, 0x29, 0xE0, 0x5B, 0xC8, 0x3B,
+	0x7B, 0xF1, 0x5F, 0x71, 0x7F, 0xC1, 0x23, 0x34, 0xFB, 0xFD, 0x3F, 0xC3, 0xFE, 0x3C, 0x8A, 0xFE,
+	0xC2, 0x4B, 0x76, 0xFB, 0x75, 0x81, 0x0B, 0x22, 0xE0, 0x9F, 0xDD, 0xCD, 0x40, 0x1E, 0x49, 0xFF,
+	0x00, 0x05, 0x51, 0xFF, 0x00, 0x93, 0x99, 0xB7, 0xFF, 0x00, 0xB1, 0x62, 0xD7, 0xFF, 0x00, 0x43,
+	0x96, 0xBE, 0x6C, 0xAF, 0xA7, 0x3F, 0xE0, 0xA9, 0x5A, 0x46, 0xAB, 0x7F, 0xFB, 0x4C, 0x43, 0x2D,
+	0x86, 0x99, 0x3D, 0xC2, 0xAF, 0x86, 0x2D, 0x72, 0xF1, 0xDB, 0x16, 0xC7, 0xEF, 0x26, 0xEE, 0x39,
+	0xAF, 0x9B, 0xBF, 0xE1, 0x1B, 0xF1, 0x27, 0xFD, 0x00, 0xAF, 0x7F, 0xF0, 0x16, 0x5A, 0x00, 0xA9,
+	0x45, 0x5B, 0xFF, 0x00, 0x84, 0x6F, 0xC4, 0x9F, 0xF4, 0x02, 0xBD, 0xFF, 0x00, 0xC0, 0x59, 0x68,
+	0xFF, 0x00, 0x84, 0x6F, 0xC4, 0x9F, 0xF4, 0x02, 0xBD, 0xFF, 0x00, 0xC0, 0x59, 0x68, 0x02, 0xA7,
+	0x6F, 0xC2, 0xBE, 0xE6, 0xFF, 0x00, 0x82, 0x41, 0xFF, 0x00, 0xC8, 0xBB, 0xE3, 0xCF, 0xFB, 0x08,
+	0x58, 0xFF, 0x00, 0xE8, 0xB9, 0xAB, 0xE2, 0x51, 0xE1, 0xAF, 0x12, 0x1C, 0x83, 0xA0, 0x5F, 0x1F,
+	0x94, 0xF0, 0x2D, 0xE4, 0x1D, 0xBD, 0xF8, 0xAF, 0xB8, 0x3F, 0xE0, 0x92, 0x16, 0x1A, 0x86, 0x9D,
+	0xA0, 0x78, 0xEE, 0x2B, 0xFB, 0x09, 0x2D, 0xD9, 0xAF, 0xEC, 0x70, 0xB2, 0x26, 0x09, 0xFD, 0xDC,
+	0xD4, 0x01, 0xF6, 0x24, 0x1F, 0xC5, 0xFE, 0xF0, 0xFF, 0x00, 0xD0, 0x45, 0x49, 0x51, 0xC1, 0xFC,
+	0x5F, 0xEF, 0x0F, 0xFD, 0x04, 0x54, 0x94, 0x00, 0x50, 0x7A, 0x51, 0x41, 0xE9, 0x40, 0x19, 0xF0,
+	0x1C, 0xEB, 0xB7, 0x07, 0xFE, 0x9C, 0xED, 0xFF, 0x00, 0xF4, 0x29, 0x6A, 0xE5, 0x7C, 0x3F, 0xFF,
+	0x00, 0x05, 0x73, 0xD4, 0xB5, 0x1D, 0x3B, 0xC4, 0x5E, 0x06, 0xFB, 0x06, 0xA1, 0x2D, 0xB9, 0x36,
+	0x37, 0xC1, 0xBC, 0xBB, 0x82, 0xBB, 0xBE, 0x78, 0x7D, 0x2B, 0xE3, 0xAF, 0xF8, 0x49, 0x7C, 0x49,
+	0xFF, 0x00, 0x41, 0xDB, 0xDF, 0xFC, 0x0A, 0x96, 0x80, 0x3F, 0x69, 0x68, 0xAF, 0xC5, 0xAF, 0xF8,
+	0x49, 0x7C, 0x49, 0xFF, 0x00, 0x41, 0xDB, 0xDF, 0xFC, 0x0A, 0x96, 0x8F, 0xF8, 0x49, 0x7C, 0x49,
+	0xFF, 0x00, 0x41, 0xDB, 0xDF, 0xFC, 0x0A, 0x96, 0x80, 0x3F, 0x69, 0x68, 0xAF, 0xC5, 0xB5, 0xF1,
+	0x2F, 0x89, 0x37, 0x0F, 0xF8, 0x9F, 0x5F, 0x75, 0xED, 0x73, 0x27, 0xF5, 0xAF, 0xAB, 0x3F, 0xE0,
+	0x93, 0x7A, 0xAE, 0xA9, 0xA9, 0x7C, 0x68, 0xF1, 0x18, 0xBE, 0xD4, 0xEE, 0x2E, 0x42, 0xF8, 0x58,
+	0x6D, 0x13, 0x3F, 0x4F, 0xF4, 0x88, 0xA8, 0x03, 0xEF, 0x8A, 0x2B, 0xE5, 0xFF, 0x00, 0xF8, 0x2A,
+	0xE5, 0xED, 0xDD, 0x87, 0xEC, 0xF1, 0xA3, 0x5C, 0x59, 0x5E, 0x3D, 0xBC, 0x9F, 0xF0, 0x99, 0xDA,
+	0x8F, 0x32, 0x39, 0x36, 0x11, 0xFE, 0x8B, 0x7B, 0xDE, 0xBF, 0x3E, 0xBF, 0xE1, 0x25, 0xF1, 0x27,
+	0xFD, 0x07, 0x6F, 0x7F, 0xF0, 0x2A, 0x5A, 0x00, 0xFD, 0xA5, 0xA2, 0xBF, 0x16, 0xBF, 0xE1, 0x25,
+	0xF1, 0x27, 0xFD, 0x07, 0x6F, 0x7F, 0xF0, 0x2A, 0x5A, 0x3F, 0xE1, 0x25, 0xF1, 0x27, 0xFD, 0x07,
+	0x6F, 0x7F, 0xF0, 0x2A, 0x5A, 0x00, 0xFD, 0xA5, 0xA2, 0xBF, 0x16, 0xBF, 0xE1, 0x25, 0xF1, 0x27,
+	0xFD, 0x07, 0x6F, 0x7F, 0xF0, 0x2A, 0x5A, 0xF7, 0x9F, 0xF8, 0x27, 0x0E, 0xB5, 0xAC, 0x6A, 0x1F,
+	0xB5, 0xA6, 0x83, 0x0D, 0xE6, 0xAF, 0x75, 0x70, 0x9F, 0x61, 0xBF, 0xFD, 0xDC, 0xD2, 0x7F, 0xD3,
+	0xBB, 0xD0, 0x07, 0xE9, 0x65, 0x15, 0xE2, 0x9F, 0xF0, 0x50, 0xC9, 0xE6, 0xB6, 0xFD, 0x90, 0x3C,
+	0x5F, 0x3D, 0xBC, 0xCD, 0x1B, 0xAA, 0xD8, 0x95, 0x91, 0x5F, 0x69, 0x5F, 0xF8, 0x98, 0xDA, 0xF7,
+	0xAF, 0xCC, 0x63, 0xE2, 0x5F, 0x12, 0x13, 0x9F, 0xED, 0xFB, 0xC6, 0xFF, 0x00, 0x6B, 0xED, 0x52,
+	0x73, 0xF9, 0x50, 0x07, 0xED, 0x25, 0x15, 0xF8, 0xB5, 0xFF, 0x00, 0x09, 0x2F, 0x89, 0x3F, 0xE8,
+	0x3B, 0x7B, 0xFF, 0x00, 0x81, 0x52, 0xD1, 0xFF, 0x00, 0x09, 0x2F, 0x89, 0x3F, 0xE8, 0x3B, 0x7B,
+	0xFF, 0x00, 0x81, 0x52, 0xD0, 0x07, 0xED, 0x2D, 0x15, 0xF8, 0xB5, 0xFF, 0x00, 0x09, 0x2F, 0x89,
+	0x3F, 0xE8, 0x3B, 0x7B, 0xFF, 0x00, 0x81, 0x52, 0xD7, 0xA2, 0x7E, 0xCA, 0x1A, 0xFE, 0xB9, 0x77,
+	0xFB, 0x4A, 0xF8, 0x12, 0xDE, 0xE3, 0x5C, 0xBC, 0x91, 0x0F, 0x8A, 0x2D, 0x37, 0x47, 0x24, 0x84,
+	0x83, 0xF3, 0x8F, 0x5A, 0x00, 0xFD, 0x61, 0xA2, 0xB8, 0x1F, 0xDA, 0x9F, 0xFE, 0x4D, 0x97, 0xE2,
+	0x37, 0x1F, 0xF3, 0x22, 0xEB, 0x1F, 0xFA, 0x41, 0x3D, 0x7E, 0x30, 0xD6, 0x73, 0xA9, 0xCB, 0x6D,
+	0x0A, 0x8C, 0x6E, 0x8F, 0xDD, 0xCA, 0x2B, 0xF0, 0x8E, 0x8A, 0xCF, 0xDB, 0xAE, 0xC5, 0xF2, 0xBE,
+	0xE7, 0xEE, 0xE5, 0x19, 0xAF, 0xC2, 0x3A, 0xFA, 0x03, 0xFE, 0x09, 0x8D, 0xFF, 0x00, 0x27, 0x93,
+	0xE1, 0xAF, 0xFA, 0xF5, 0xD4, 0x7F, 0xF4, 0x8A, 0x5A, 0x16, 0x22, 0xF6, 0x56, 0x1C, 0x69, 0xB9,
+	0x69, 0x7E, 0xFF, 0x00, 0x81, 0xFA, 0xB9, 0x45, 0x78, 0x3F, 0xFC, 0x14, 0x8E, 0xE6, 0x6B, 0x4F,
+	0xD9, 0x2F, 0x5C, 0xB8, 0xB5, 0xB8, 0x92, 0x29, 0x16, 0xF6, 0xC7, 0x0D, 0x1C, 0x9B, 0x7F, 0xE5,
+	0xE1, 0x2B, 0xF3, 0x4B, 0xFE, 0x12, 0x6F, 0x12, 0xB7, 0x27, 0x5D, 0xBD, 0xFF, 0x00, 0xC0, 0xA9,
+	0x3F, 0xA5, 0x74, 0x18, 0x9F, 0x5D, 0xFF, 0x00, 0xC1, 0x6E, 0x3F, 0xE0, 0xA6, 0x1A, 0x2F, 0xFC,
+	0x13, 0x5F, 0xE1, 0xFF, 0x00, 0x82, 0x3C, 0x4F, 0xAE, 0xFC, 0x30, 0x9B, 0xC5, 0x51, 0xF8, 0xAB,
+	0x5A, 0xBC, 0xB6, 0x5D, 0x3E, 0xD7, 0x54, 0x5B, 0x49, 0xA3, 0x30, 0xC2, 0x0F, 0x9C, 0x19, 0xA3,
+	0x7E, 0x06, 0xFD, 0xBD, 0x3A, 0xC8, 0x95, 0xF9, 0xDE, 0x7F, 0xE0, 0xE9, 0xDF, 0x01, 0x13, 0x9F,
+	0xF8, 0x63, 0x5D, 0x5F, 0xFE, 0x03, 0xE3, 0x38, 0x88, 0xFC, 0xFE, 0xCD, 0x5F, 0x33, 0x7F, 0xC1,
+	0x6E, 0x3C, 0x41, 0xAA, 0xDE, 0x59, 0x7C, 0x35, 0xB1, 0xD4, 0x75, 0x09, 0x6E, 0x22, 0x92, 0x4D,
+	0x62, 0x65, 0xF3, 0x2E, 0x0B, 0x6D, 0x64, 0x16, 0x49, 0xD0, 0xFF, 0x00, 0xBD, 0x5F, 0x03, 0x60,
+	0xAF, 0xCA, 0xD5, 0xF8, 0xFF, 0x00, 0x18, 0x78, 0x2B, 0xE1, 0xEF, 0x1B, 0x67, 0x52, 0xCD, 0x33,
+	0x7C, 0x33, 0xA9, 0x5A, 0x49, 0x45, 0xBF, 0x69, 0x35, 0xA4, 0x76, 0x56, 0x8C, 0x92, 0xD3, 0xD0,
+	0xFA, 0x2C, 0xBF, 0x32, 0xC5, 0xE0, 0xF0, 0xCA, 0x14, 0x9D, 0x95, 0xCF, 0xD9, 0x2F, 0xF8, 0x8A,
+	0x77, 0xC0, 0x5F, 0xF4, 0x66, 0xBA, 0xC7, 0xFE, 0x16, 0x51, 0x7F, 0xF2, 0x35, 0x1F, 0xF1, 0x14,
+	0xEF, 0x80, 0xBF, 0xE8, 0xCD, 0x75, 0x8F, 0xFC, 0x2C, 0xA2, 0xFF, 0x00, 0xE4, 0x6A, 0xFC, 0x6D,
+	0xA2, 0xBE, 0x5F, 0xFE, 0x25, 0x9F, 0xC1, 0xFF, 0x00, 0xFA, 0x01, 0x7F, 0xF8, 0x32, 0xA7, 0xFF,
+	0x00, 0x24, 0x76, 0x7F, 0x6D, 0xE6, 0x1F, 0xCC, 0x7E, 0xE3, 0xFE, 0xCD, 0x7F, 0xF0, 0x71, 0xBF,
+	0x81, 0xFF, 0x00, 0x68, 0xCF, 0xDA, 0x27, 0xC0, 0x1F, 0xB3, 0xDD, 0x9F, 0xEC, 0xA7, 0xAB, 0x69,
+	0x73, 0x78, 0xEB, 0xC6, 0xFA, 0x5F, 0x87, 0x17, 0x51, 0x9B, 0xC5, 0x91, 0x48, 0xB6, 0x86, 0xF6,
+	0xEE, 0x38, 0x3C, 0xCF, 0x2F, 0xEC, 0xFF, 0x00, 0x36, 0xDF, 0x33, 0xCC, 0xF7, 0xDB, 0x5F, 0x45,
+	0xFF, 0x00, 0xC1, 0x5F, 0x3F, 0xE0, 0xA8, 0x7E, 0x11, 0xFF, 0x00, 0x82, 0x53, 0x7C, 0x46, 0xF0,
+	0x7F, 0xC3, 0xFD, 0x5B, 0xE0, 0xC6, 0xA5, 0xE3, 0x27, 0xF1, 0x66, 0x87, 0x36, 0xA3, 0xF6, 0x9B,
+	0x7D, 0x71, 0x2C, 0xFE, 0xCD, 0xE5, 0x4A, 0x53, 0x91, 0xE4, 0x49, 0x9C, 0xFF, 0x00, 0xBA, 0x3E,
+	0x95, 0xF8, 0x3B, 0xFF, 0x00, 0x04, 0xCA, 0xFF, 0x00, 0x94, 0x93, 0x7E, 0xCF, 0x7F, 0xF6, 0x5C,
+	0xBC, 0x23, 0xFF, 0x00, 0xA7, 0x8B, 0x4A, 0xFD, 0x1C, 0xFF, 0x00, 0x83, 0xC5, 0xFF, 0x00, 0xE4,
+	0xE3, 0xFE, 0x0D, 0xFF, 0x00, 0xD8, 0x85, 0xA8, 0x7F, 0xE9, 0x6A, 0xD7, 0x65, 0x3F, 0xA3, 0x7F,
+	0x84, 0x1F, 0x55, 0x95, 0x2F, 0xEC, 0xFD, 0xDD, 0xEF, 0xCF, 0x3B, 0xAF, 0x24, 0xF9, 0xAF, 0x6F,
+	0x99, 0xCE, 0xF3, 0xAC, 0xC6, 0x58, 0x88, 0xBE, 0x72, 0x66, 0xFF, 0x00, 0x83, 0xA7, 0x7C, 0x04,
+	0x0E, 0x3F, 0xE1, 0x8D, 0x35, 0x8F, 0xFC, 0x2C, 0xA2, 0xFF, 0x00, 0xE4, 0x51, 0xFC, 0x87, 0xD0,
+	0x51, 0xFF, 0x00, 0x11, 0x4E, 0xF8, 0x0B, 0xFE, 0x8C, 0xD7, 0x58, 0xFF, 0x00, 0xC2, 0xCA, 0x2F,
+	0xFE, 0x46, 0xAF, 0xC6, 0xD3, 0xD6, 0x8A, 0xE3, 0xFF, 0x00, 0x89, 0x67, 0xF0, 0x7D, 0xEB, 0xF5,
+	0x17, 0xFF, 0x00, 0x83, 0x2A, 0x7F, 0xF2, 0x47, 0x47, 0xF6, 0xDE, 0x61, 0xFC, 0xC7, 0xEC, 0x97,
+	0xFC, 0x45, 0x3B, 0xE0, 0x2F, 0xFA, 0x33, 0x5D, 0x63, 0xFF, 0x00, 0x0B, 0x28, 0xBF, 0xF9, 0x1E,
+	0xB8, 0x3F, 0xDA, 0x33, 0xFE, 0x0E, 0x43, 0xF0, 0x97, 0xC7, 0x0F, 0x85, 0x17, 0xDF, 0x0E, 0xAC,
+	0x3F, 0x65, 0x8D, 0x4F, 0x4D, 0x92, 0xEA, 0xE6, 0xDD, 0xCD, 0xD4, 0xDE, 0x2C, 0x49, 0x7E, 0x58,
+	0xE5, 0x57, 0xDB, 0x8F, 0xB3, 0x7F, 0xB3, 0x5F, 0x95, 0x34, 0x57, 0xBD, 0xC3, 0x3E, 0x05, 0xF8,
+	0x6B, 0xC1, 0xF9, 0xF6, 0x1F, 0x39, 0xCA, 0xF0, 0x8E, 0x18, 0x8A, 0x12, 0x53, 0x84, 0x9D, 0x49,
+	0xCA, 0xD2, 0x5B, 0x3B, 0x39, 0x34, 0xFE, 0x67, 0x9F, 0x9B, 0xD7, 0xA9, 0x9D, 0xE5, 0xB5, 0x70,
+	0x38, 0xB7, 0xCD, 0x4E, 0xA2, 0xE5, 0x92, 0xDA, 0xE9, 0xF4, 0xBA, 0xD5, 0x7D, 0xE7, 0xD8, 0xC7,
+	0xFE, 0x0A, 0x8D, 0xA1, 0xE7, 0x8F, 0x84, 0x17, 0x63, 0xDB, 0xFB, 0x6A, 0x3E, 0x3F, 0xF2, 0x18,
+	0xFE, 0x42, 0x93, 0xFE, 0x1E, 0x8D, 0xA2, 0x7F, 0xD1, 0x22, 0xBB, 0xFF, 0x00, 0xC1, 0xD4, 0x5F,
+	0xFC, 0x45, 0x7C, 0x75, 0x45, 0x7F, 0x52, 0x7F, 0xC4, 0x56, 0xE3, 0x8E, 0x98, 0x85, 0xFF, 0x00,
+	0x80, 0x43, 0xFF, 0x00, 0x91, 0x3F, 0x1A, 0xFF, 0x00, 0x88, 0x11, 0xE1, 0x9F, 0x36, 0xB8, 0x47,
+	0xFF, 0x00, 0x83, 0x27, 0xFE, 0x67, 0xD8, 0xBF, 0xF0, 0xF4, 0x6D, 0x13, 0xFE, 0x89, 0x15, 0xDF,
+	0xFE, 0x0E, 0xA2, 0xFF, 0x00, 0xE2, 0x28, 0xFF, 0x00, 0x87, 0xA3, 0x68, 0x9F, 0xF4, 0x48, 0xAE,
+	0xFF, 0x00, 0xF0, 0x75, 0x17, 0xFF, 0x00, 0x11, 0x5F, 0x1D, 0x51, 0x47, 0xFC, 0x45, 0x6E, 0x38,
+	0xFF, 0x00, 0xA0, 0x85, 0xFF, 0x00, 0x80, 0x43, 0xFF, 0x00, 0x91, 0x13, 0xF0, 0x23, 0xC3, 0x35,
+	0x67, 0xF5, 0x47, 0xFF, 0x00, 0x83, 0x27, 0xFE, 0x67, 0xD8, 0xBF, 0xF0, 0xF4, 0x6D, 0x13, 0xFE,
+	0x89, 0x15, 0xDF, 0xFE, 0x0E, 0xA2, 0xFF, 0x00, 0xE2, 0x28, 0xFF, 0x00, 0x87, 0xA3, 0x68, 0x9F,
+	0xF4, 0x48, 0xAE, 0xFF, 0x00, 0xF0, 0x75, 0x17, 0xFF, 0x00, 0x11, 0x5F, 0x1D, 0x51, 0x47, 0xFC,
+	0x45, 0x6E, 0x38, 0xFF, 0x00, 0xA0, 0x85, 0xFF, 0x00, 0x80, 0x43, 0xFF, 0x00, 0x91, 0x0F, 0xF8,
+	0x81, 0x1E, 0x19, 0xFF, 0x00, 0xD0, 0x23, 0xFF, 0x00, 0xC0, 0xE7, 0xFE, 0x67, 0xD8, 0xBF, 0xF0,
+	0xF4, 0x6D, 0x13, 0xFE, 0x89, 0x15, 0xDF, 0xFE, 0x0E, 0xA2, 0xFF, 0x00, 0xE2, 0x28, 0xFF, 0x00,
+	0x87, 0xA3, 0x68, 0x9F, 0xF4, 0x48, 0xAE, 0xFF, 0x00, 0xF0, 0x75, 0x17, 0xFF, 0x00, 0x11, 0x5F,
+	0x1D, 0x51, 0x47, 0xFC, 0x45, 0x7E, 0x38, 0xFF, 0x00, 0xA0, 0x95, 0xFF, 0x00, 0x80, 0x43, 0xFC,
+	0x83, 0xFE, 0x20, 0x47, 0x86, 0x7F, 0xF4, 0x08, 0xFF, 0x00, 0xF0, 0x64, 0xFF, 0x00, 0xCC, 0xFB,
+	0x17, 0xFE, 0x1E, 0x8D, 0xA2, 0x7F, 0xD1, 0x22, 0xBB, 0xFF, 0x00, 0xC1, 0xD4, 0x5F, 0xFC, 0x45,
+	0x1F, 0xF0, 0xF4, 0x6D, 0x13, 0xFE, 0x89, 0x15, 0xDF, 0xFE, 0x0E, 0xA2, 0xFF, 0x00, 0xE2, 0x2B,
+	0xE3, 0xAA, 0x28, 0xFF, 0x00, 0x88, 0xAD, 0xC7, 0x1F, 0xF4, 0x10, 0xBF, 0xF0, 0x08, 0x7F, 0xF2,
+	0x21, 0xFF, 0x00, 0x10, 0x23, 0xC3, 0x3F, 0xFA, 0x04, 0x7F, 0xF8, 0x32, 0x7F, 0xE6, 0x7D, 0x8B,
+	0xFF, 0x00, 0x0F, 0x46, 0xD1, 0x3F, 0xE8, 0x91, 0x5D, 0xFF, 0x00, 0xE0, 0xEA, 0x2F, 0xFE, 0x22,
+	0xBB, 0xFF, 0x00, 0x83, 0xDF, 0xF0, 0x5A, 0xCF, 0x0B, 0xFC, 0x34, 0xD3, 0x6E, 0xF4, 0xDB, 0x9F,
+	0xD9, 0xEF, 0x50, 0xBD, 0x6B, 0xAB, 0x94, 0x60, 0xCB, 0xE2, 0x24, 0x4C, 0x60, 0x7F, 0xD7, 0xB9,
+	0xFE, 0x66, 0xBF, 0x3E, 0xE8, 0xAF, 0x91, 0xE3, 0x8C, 0xFB, 0x34, 0xF1, 0x17, 0x87, 0xEA, 0x64,
+	0x99, 0xEC, 0xFD, 0xAE, 0x1A, 0x6D, 0x39, 0x45, 0x25, 0x1B, 0xB8, 0xBB, 0xAD, 0x62, 0x93, 0xD3,
+	0xD4, 0xF6, 0x72, 0x1F, 0x09, 0xF8, 0x1F, 0x86, 0xB3, 0x18, 0xE3, 0xF2, 0xFC, 0x3B, 0x85, 0x54,
+	0x9A, 0x4F, 0x9E, 0x4F, 0x7D, 0xF7, 0x6C, 0xFD, 0x31, 0x1F, 0xF0, 0x5F, 0xFF, 0x00, 0x08, 0x11,
+	0x93, 0xFB, 0x32, 0x6A, 0x5F, 0xF8, 0x54, 0x45, 0xFF, 0x00, 0xC8, 0xF4, 0xBF, 0xF0, 0xFF, 0x00,
+	0xEF, 0x07, 0xFF, 0x00, 0xD1, 0xB2, 0xEA, 0x5F, 0xF8, 0x54, 0x45, 0xFF, 0x00, 0xC8, 0xF5, 0xF9,
+	0x9B, 0x45, 0x7E, 0x0B, 0xFF, 0x00, 0x10, 0x1F, 0xC3, 0x3F, 0xFA, 0x04, 0x7F, 0xF8, 0x1C, 0xFF,
+	0x00, 0xCC, 0xFB, 0xFF, 0x00, 0xAA, 0xD1, 0xEC, 0x7E, 0x99, 0x7F, 0xC3, 0xFF, 0x00, 0xBC, 0x1F,
+	0xFF, 0x00, 0x46, 0xCB, 0xA9, 0x7F, 0xE1, 0x51, 0x17, 0xFF, 0x00, 0x23, 0xD1, 0xFF, 0x00, 0x0F,
+	0xFE, 0xF0, 0x7F, 0xFD, 0x1B, 0x2E, 0xA5, 0xFF, 0x00, 0x85, 0x44, 0x5F, 0xFC, 0x8F, 0x5F, 0x99,
+	0xB4, 0x53, 0xFF, 0x00, 0x88, 0x0F, 0xE1, 0x9F, 0xFD, 0x02, 0x3F, 0xFC, 0x0E, 0x7F, 0xE6, 0x3F,
+	0xAB, 0x51, 0xEC, 0x7E, 0x97, 0xBF, 0xFC, 0x17, 0xFB, 0xC2, 0x07, 0x70, 0x93, 0xF6, 0x68, 0xD4,
+	0x94, 0x15, 0x27, 0xCC, 0xFF, 0x00, 0x84, 0x96, 0x2E, 0x38, 0xC6, 0x7F, 0xE3, 0xDB, 0xB6, 0x2B,
+	0xF4, 0x1F, 0xFE, 0x0A, 0x67, 0xF1, 0x07, 0xE1, 0xE7, 0xFC, 0x13, 0xEF, 0xF6, 0x1E, 0xF0, 0x0F,
+	0xED, 0x7D, 0x6B, 0xE1, 0x7D, 0x67, 0xC4, 0x73, 0x78, 0xD7, 0x5C, 0xD2, 0xF4, 0xD9, 0x34, 0x56,
+	0xD5, 0x22, 0x45, 0xB5, 0x17, 0x9A, 0x75, 0xC5, 0xEE, 0xF0, 0xFE, 0x58, 0xDD, 0xB7, 0xEC, 0xFE,
+	0x5E, 0x71, 0xCF, 0x99, 0x5F, 0xCE, 0x4F, 0x7F, 0xF8, 0x09, 0xFE, 0x6B, 0x5F, 0xBF, 0xDF, 0xF0,
+	0x72, 0xDF, 0xFC, 0xA1, 0x0B, 0xE0, 0x2F, 0xFD, 0x8E, 0xDE, 0x17, 0xFF, 0x00, 0xD4, 0x6B, 0x54,
+	0xAE, 0xBC, 0x3F, 0x81, 0xFE, 0x1A, 0xD1, 0xA7, 0x34, 0xB0, 0x57, 0xBA, 0xEB, 0x39, 0xB6, 0xBD,
+	0x1F, 0x35, 0xD7, 0xC8, 0xC2, 0x74, 0x29, 0xC6, 0xA2, 0xD0, 0xF8, 0xCF, 0xFE, 0x1F, 0xFF, 0x00,
+	0xE0, 0xD3, 0xCA, 0x7E, 0xCC, 0x9A, 0x96, 0x3B, 0x7F, 0xC5, 0x51, 0x17, 0xFF, 0x00, 0x23, 0x9F,
+	0xE6, 0x68, 0xFF, 0x00, 0x87, 0xFF, 0x00, 0x78, 0x3F, 0xFE, 0x8D, 0x97, 0x52, 0xFF, 0x00, 0xC2,
+	0xA2, 0x2F, 0xFE, 0x47, 0xAF, 0xCC, 0xDA, 0x2B, 0x8F, 0xFE, 0x20, 0x3F, 0x86, 0x7F, 0xF4, 0x08,
+	0xFF, 0x00, 0xF0, 0x64, 0xFF, 0x00, 0xCC, 0xDF, 0xEA, 0xD4, 0x7B, 0x1F, 0xA6, 0x5F, 0xF0, 0xFF,
+	0x00, 0xEF, 0x07, 0xFF, 0x00, 0xD1, 0xB2, 0xEA, 0x5F, 0xF8, 0x54, 0x45, 0xFF, 0x00, 0xC8, 0xF4,
+	0x7F, 0xC3, 0xFF, 0x00, 0xBC, 0x1F, 0xFF, 0x00, 0x46, 0xCB, 0xA9, 0x7F, 0xE1, 0x51, 0x17, 0xFF,
+	0x00, 0x23, 0xD7, 0xE6, 0x6D, 0x14, 0xFF, 0x00, 0xE2, 0x03, 0xF8, 0x67, 0xFF, 0x00, 0x40, 0x8F,
+	0xFF, 0x00, 0x03, 0x9F, 0xF9, 0x87, 0xD5, 0xA8, 0xF6, 0x3F, 0x65, 0xFF, 0x00, 0xE0, 0x9F, 0x1F,
+	0xF0, 0x55, 0x3F, 0x04, 0x7E, 0xDC, 0x3F, 0xB6, 0x47, 0x81, 0xBF, 0x65, 0x5B, 0xAF, 0x82, 0x7A,
+	0xA6, 0x82, 0xBE, 0x2E, 0xBE, 0xB8, 0xB7, 0xFE, 0xD4, 0x8F, 0xC4, 0x11, 0xCA, 0xD6, 0xDE, 0x5D,
+	0xA4, 0xF7, 0x3F, 0x70, 0xDB, 0x73, 0x9F, 0x26, 0xBE, 0x3B, 0xFF, 0x00, 0x83, 0x82, 0x7E, 0x1C,
+	0xE9, 0x3F, 0x09, 0x3F, 0xE0, 0xA9, 0x7E, 0x38, 0xF0, 0x26, 0x8D, 0x79, 0x34, 0x96, 0xD6, 0x3A,
+	0x4E, 0x8A, 0xCB, 0x71, 0x79, 0x8F, 0x30, 0x96, 0xD2, 0xED, 0xE4, 0xDB, 0xC0, 0x03, 0x3F, 0x37,
+	0x60, 0x3E, 0x83, 0xA5, 0x54, 0xFF, 0x00, 0x83, 0x7E, 0xFF, 0x00, 0xE5, 0x30, 0x9F, 0x04, 0x3F,
+	0xEC, 0x3D, 0x79, 0xFF, 0x00, 0xA6, 0xBB, 0xFA, 0xEC, 0x3F, 0xE0, 0xE6, 0x7F, 0xF9, 0x4C, 0x7F,
+	0xC4, 0x6F, 0xFB, 0x07, 0xF8, 0x7F, 0xFF, 0x00, 0x4C, 0xD6, 0xD5, 0xF5, 0x7C, 0x33, 0xE1, 0xC7,
+	0x09, 0x70, 0x85, 0x69, 0x62, 0x72, 0xCC, 0x3F, 0x25, 0x46, 0xAD, 0xCD, 0xCD, 0x26, 0xED, 0xD5,
+	0x6A, 0xD8, 0xA9, 0xD3, 0x8D, 0x3C, 0x45, 0xA3, 0xD8, 0xF8, 0x1C, 0x67, 0xF8, 0x81, 0xFF, 0x00,
+	0x81, 0x75, 0xAF, 0xBF, 0xBF, 0xE0, 0xD9, 0x0F, 0xF9, 0x4C, 0x1F, 0x80, 0x7F, 0xEC, 0x03, 0xE2,
+	0x0F, 0xFD, 0x35, 0x4F, 0x5F, 0x00, 0x8E, 0x95, 0xF7, 0xF7, 0xFC, 0x1B, 0x21, 0xFF, 0x00, 0x29,
+	0x83, 0xF0, 0x0F, 0xFD, 0x80, 0x7C, 0x41, 0xFF, 0x00, 0xA6, 0xA9, 0xEB, 0xEE, 0x23, 0xF1, 0x17,
+	0x5B, 0xF8, 0x6C, 0x93, 0xFE, 0x0E, 0x74, 0xFF, 0x00, 0x94, 0xC2, 0x78, 0xF7, 0xFE, 0xC0, 0x7A,
+	0x0F, 0xFE, 0x9B, 0x6D, 0xEB, 0xF3, 0xF4, 0x74, 0xAF, 0xD0, 0x2F, 0xF8, 0x39, 0xD3, 0xFE, 0x53,
+	0x09, 0xE3, 0xDF, 0xFB, 0x01, 0xE8, 0x3F, 0xFA, 0x6D, 0xB7, 0xAF, 0xCF, 0xD1, 0xD2, 0xA6, 0x5F,
+	0x11, 0x54, 0xFF, 0x00, 0x83, 0x11, 0xCA, 0xAE, 0xEE, 0xB9, 0xF6, 0x45, 0xFE, 0xFE, 0xD2, 0x4E,
+	0xEC, 0x57, 0xF4, 0x45, 0xFF, 0x00, 0x05, 0x6B, 0xF8, 0xAF, 0xE0, 0x1F, 0xF8, 0x26, 0x67, 0xC1,
+	0x2F, 0x87, 0xBF, 0x18, 0x6D, 0x3C, 0x25, 0xAC, 0x78, 0xA3, 0xFE, 0x13, 0xAB, 0xE7, 0x80, 0x59,
+	0xB6, 0xA1, 0x1C, 0x22, 0xD3, 0x16, 0xA9, 0x2E, 0x72, 0x53, 0xFD, 0xAA, 0xFE, 0x77, 0x0F, 0xDE,
+	0x6F, 0xF3, 0xFC, 0x15, 0xFB, 0xC3, 0xFF, 0x00, 0x07, 0x63, 0x7F, 0xC9, 0x90, 0xFE, 0xCF, 0x5F,
+	0xF6, 0x1E, 0x6F, 0xFD, 0x36, 0xC7, 0x5B, 0x51, 0xA9, 0x2A, 0x69, 0xD8, 0xF4, 0x70, 0x39, 0xDE,
+	0x65, 0x94, 0xE2, 0x2F, 0x85, 0xA9, 0xCB, 0xCC, 0xF5, 0x5D, 0x19, 0xF2, 0x5F, 0xFC, 0x3F, 0xE3,
+	0xC2, 0x0B, 0xF2, 0x9F, 0xD9, 0xAB, 0x52, 0xFF, 0x00, 0xC2, 0xA2, 0x2F, 0xFE, 0x47, 0x3F, 0xCC,
+	0xD1, 0xFF, 0x00, 0x0F, 0xFA, 0xF0, 0x77, 0xFD, 0x1B, 0x4E, 0xA5, 0xFF, 0x00, 0x85, 0x44, 0x5F,
+	0xFC, 0x8D, 0x5F, 0x9A, 0x09, 0xF7, 0x07, 0xD2, 0x96, 0xAB, 0xEB, 0x55, 0xFB, 0x9E, 0xF7, 0xFA,
+	0xEB, 0xC4, 0x5F, 0xF3, 0xF7, 0xFF, 0x00, 0x25, 0x8F, 0xF9, 0x1F, 0xA5, 0xDF, 0xF0, 0xFF, 0x00,
+	0xAF, 0x07, 0x7F, 0xD1, 0xB4, 0xEA, 0x5F, 0xF8, 0x54, 0x45, 0xFF, 0x00, 0xC8, 0xD4, 0x7F, 0xC3,
+	0xFE, 0xBC, 0x1D, 0xFF, 0x00, 0x46, 0xD3, 0xA9, 0x7F, 0xE1, 0x51, 0x17, 0xFF, 0x00, 0x23, 0x57,
+	0xE6, 0x8D, 0x14, 0x7D, 0x6A, 0xBF, 0x70, 0xFF, 0x00, 0x5D, 0xB8, 0x8B, 0xFE, 0x7E, 0xFF, 0x00,
+	0xE4, 0xB1, 0xFF, 0x00, 0x23, 0xF6, 0x83, 0xFE, 0x09, 0xB3, 0xFF, 0x00, 0x05, 0x34, 0xF0, 0x5F,
+	0xED, 0xFD, 0xFB, 0x69, 0x78, 0x2F, 0xF6, 0x48, 0x97, 0xE0, 0xDE, 0xAD, 0xE1, 0xD1, 0xE2, 0xCF,
+	0xED, 0x23, 0xFD, 0xB0, 0xBE, 0x20, 0x8E, 0x5F, 0x23, 0xEC, 0xB6, 0x17, 0x37, 0x78, 0xD9, 0xE5,
+	0x8C, 0xE7, 0xEC, 0xF8, 0xE8, 0x3F, 0xD6, 0xD5, 0xEF, 0xF8, 0x29, 0xD7, 0xFC, 0x14, 0x6B, 0xC1,
+	0x1F, 0xF0, 0x4E, 0xEF, 0xDB, 0x13, 0xC4, 0x1F, 0xB2, 0xA5, 0xB7, 0xC1, 0xFD, 0x5B, 0xC4, 0x9F,
+	0xD8, 0xBA, 0x7E, 0x9F, 0x72, 0xDA, 0xA3, 0xEB, 0xF1, 0x5A, 0xF9, 0xDF, 0x69, 0xB6, 0x5B, 0x8D,
+	0xBB, 0x3E, 0xCE, 0x73, 0x8D, 0xDE, 0xA6, 0xBE, 0x33, 0xFF, 0x00, 0x83, 0x6F, 0x3F, 0xE5, 0x34,
+	0x5F, 0x06, 0x7F, 0xDE, 0xF1, 0x0F, 0xFE, 0xA3, 0x9A, 0x9D, 0x6F, 0xFF, 0x00, 0xC1, 0xCE, 0x7F,
+	0xF2, 0x98, 0x2F, 0x1E, 0x7F, 0xD8, 0x07, 0x40, 0xFF, 0x00, 0xD3, 0x65, 0xBD, 0x6B, 0xF5, 0xAA,
+	0xDC, 0xB7, 0xB9, 0x82, 0xE3, 0x4E, 0x24, 0xFA, 0xE5, 0xFD, 0xB7, 0x4E, 0xC8, 0xEB, 0x47, 0xFC,
+	0x17, 0xEB, 0xC1, 0xFF, 0x00, 0xF4, 0x6D, 0x7A, 0x91, 0xF7, 0xFF, 0x00, 0x84, 0x9E, 0x21, 0x9F,
+	0xFC, 0x96, 0xA3, 0xFE, 0x1F, 0xF5, 0xE0, 0xEF, 0xFA, 0x36, 0x9D, 0x4B, 0xFF, 0x00, 0x0A, 0x88,
+	0xBF, 0xF9, 0x1A, 0xBF, 0x34, 0x47, 0x4A, 0x2B, 0x2F, 0xAD, 0x57, 0xEE, 0x6F, 0xFE, 0xBA, 0xF1,
+	0x17, 0x5A, 0xBF, 0x84, 0x7F, 0xC8, 0xFD, 0x2E, 0xFF, 0x00, 0x87, 0xFD, 0x78, 0x3B, 0xFE, 0x8D,
+	0xA7, 0x52, 0xFF, 0x00, 0xC2, 0xA2, 0x2F, 0xFE, 0x46, 0xA3, 0xFE, 0x1F, 0xF5, 0xE0, 0xEF, 0xFA,
+	0x36, 0x9D, 0x4B, 0xFF, 0x00, 0x0A, 0x88, 0xBF, 0xF9, 0x1A, 0xBF, 0x34, 0x68, 0xA3, 0xEB, 0x55,
+	0xFB, 0x87, 0xFA, 0xED, 0xC4, 0x56, 0x4F, 0xDA, 0xFF, 0x00, 0xE4, 0xB1, 0xFF, 0x00, 0x23, 0xF4,
+	0x0B, 0xE3, 0xB7, 0xFC, 0x16, 0xCF, 0xC3, 0x7F, 0x17, 0xFE, 0x15, 0x6B, 0x5F, 0x0D, 0xAC, 0xFE,
+	0x00, 0x6A, 0x1A, 0x73, 0xEA, 0xD6, 0xE9, 0x12, 0xDD, 0xC9, 0xE2, 0x24, 0x98, 0x43, 0x86, 0x46,
+	0xCE, 0x3C, 0xB1, 0xF7, 0xB6, 0x7A, 0x0A, 0xF9, 0x77, 0xFE, 0x1A, 0x72, 0xD0, 0xF2, 0xDE, 0x0B,
+	0x98, 0x1E, 0xE3, 0xED, 0x5F, 0xFD, 0xAE, 0xBC, 0x7E, 0x8A, 0xF2, 0x71, 0xD9, 0x6E, 0x17, 0x32,
+	0xA8, 0xA7, 0x88, 0x57, 0x69, 0x58, 0xFA, 0xAC, 0x8B, 0xC6, 0xAF, 0x10, 0xB8, 0x6F, 0x0F, 0x2A,
+	0x18, 0x0C, 0x52, 0x8C, 0x64, 0xEE, 0xFD, 0xC8, 0x3D, 0x7E, 0x68, 0xF6, 0x0F, 0xF8, 0x69, 0xBB,
+	0x3F, 0xFA, 0x13, 0x66, 0xFF, 0x00, 0xC0, 0xAF, 0xFE, 0xD7, 0x47, 0xFC, 0x34, 0xDD, 0x9F, 0xFD,
+	0x09, 0xB3, 0x7F, 0xE0, 0x57, 0xFF, 0x00, 0x6B, 0xAF, 0x1F, 0xA2, 0xB8, 0xBF, 0xD5, 0xEC, 0xAF,
+	0xF9, 0x3F, 0x16, 0x7B, 0x7F, 0xF1, 0x31, 0x7E, 0x2B, 0xFF, 0x00, 0xD0, 0x6A, 0xFF, 0x00, 0xC1,
+	0x74, 0xFF, 0x00, 0xF9, 0x13, 0xD8, 0x3F, 0xE1, 0xA6, 0xEC, 0xFF, 0x00, 0xE8, 0x4D, 0x9B, 0xFF,
+	0x00, 0x02, 0xBF, 0xFB, 0x5D, 0x1F, 0xF0, 0xD3, 0x76, 0x7F, 0xF4, 0x26, 0xCD, 0xFF, 0x00, 0x81,
+	0x5F, 0xFD, 0xAE, 0xBC, 0x7E, 0x8A, 0x3F, 0xD5, 0xDC, 0xAF, 0xF9, 0x3F, 0x16, 0x1F, 0xF1, 0x31,
+	0x5E, 0x2B, 0xE9, 0x6C, 0x6A, 0xFF, 0x00, 0xC1, 0x74, 0xFF, 0x00, 0xF9, 0x13, 0xD8, 0x3F, 0xE1,
+	0xA6, 0xEC, 0xFF, 0x00, 0xE8, 0x4D, 0x9B, 0xFF, 0x00, 0x02, 0xBF, 0xFB, 0x5D, 0x1F, 0xF0, 0xD3,
+	0x76, 0x7F, 0xF4, 0x26, 0xCD, 0xFF, 0x00, 0x81, 0x5F, 0xFD, 0xAE, 0xBC, 0x7E, 0x8A, 0x7F, 0xEA,
+	0xEE, 0x57, 0xFC, 0x9F, 0x8B, 0x0F, 0xF8, 0x98, 0xAF, 0x16, 0x2F, 0xFE, 0xFA, 0xBF, 0xF0, 0x5D,
+	0x3F, 0xFE, 0x44, 0xF6, 0x0F, 0xF8, 0x69, 0xBB, 0x3F, 0xFA, 0x13, 0x66, 0xFF, 0x00, 0xC0, 0xAF,
+	0xFE, 0xD7, 0x47, 0xFC, 0x34, 0xDD, 0x9F, 0xFD, 0x09, 0xB3, 0x7F, 0xE0, 0x57, 0xFF, 0x00, 0x6B,
+	0xAF, 0x1F, 0xA2, 0x97, 0xFA, 0xBD, 0x95, 0xFF, 0x00, 0x27, 0xE2, 0xC7, 0xFF, 0x00, 0x13, 0x15,
+	0xE2, 0xBF, 0xFD, 0x06, 0xAF, 0xFC, 0x17, 0x4F, 0xFF, 0x00, 0x91, 0x3D, 0x83, 0xFE, 0x1A, 0x6E,
+	0xCF, 0xFE, 0x84, 0xD9, 0xBF, 0xF0, 0x2B, 0xFF, 0x00, 0xB5, 0xD1, 0xFF, 0x00, 0x0D, 0x37, 0x67,
+	0xFF, 0x00, 0x42, 0x6C, 0xDF, 0xF8, 0x15, 0xFF, 0x00, 0xDA, 0xEB, 0xC7, 0xE8, 0xA7, 0xFE, 0xAE,
+	0xE5, 0x76, 0xBF, 0x27, 0xE2, 0xC1, 0xFD, 0x22, 0xBC, 0x58, 0x56, 0xFF, 0x00, 0x6D, 0x5F, 0xF8,
+	0x2E, 0x9F, 0xFF, 0x00, 0x22, 0x7B, 0x86, 0x93, 0xFB, 0x5F, 0xC1, 0xA5, 0xE9, 0xD7, 0x5A, 0x57,
+	0xFC, 0x21, 0x32, 0x34, 0x77, 0x52, 0x47, 0x23, 0x7F, 0xA7, 0xFF, 0x00, 0x71, 0x5D, 0x7F, 0xB9,
+	0xFE, 0xD5, 0x4E, 0xDF, 0xB6, 0x2E, 0x97, 0x92, 0x07, 0x80, 0x66, 0xDB, 0x9E, 0x3F, 0xD3, 0xBF,
+	0xFB, 0x0A, 0xF0, 0x8A, 0x2B, 0xF4, 0x0C, 0x8F, 0x8B, 0xF3, 0xFE, 0x1C, 0xCB, 0x21, 0x80, 0xC0,
+	0x55, 0xE4, 0xA7, 0x0B, 0xD9, 0x59, 0x3D, 0xFD, 0x6E, 0x7F, 0x3C, 0xF1, 0xCE, 0x4B, 0x97, 0x78,
+	0x8D, 0xC4, 0x95, 0x73, 0xDC, 0xFA, 0x1E, 0xD7, 0x13, 0x52, 0xCA, 0x52, 0xBB, 0x8D, 0xEC, 0xAC,
+	0xB4, 0x8D, 0x97, 0xDC, 0x91, 0xEE, 0xDF, 0xF0, 0xD8, 0x9A, 0x5F, 0xFD, 0x08, 0x13, 0x7F, 0xE0,
+	0x77, 0xFF, 0x00, 0x61, 0x47, 0xFC, 0x36, 0x1E, 0x97, 0xFF, 0x00, 0x42, 0x04, 0xDF, 0xF8, 0x1D,
+	0xFF, 0x00, 0xD8, 0x57, 0x84, 0xD1, 0x5E, 0xC7, 0xFC, 0x44, 0xCE, 0x2F, 0xFF, 0x00, 0x9F, 0xCB,
+	0xFF, 0x00, 0x00, 0x8F, 0xF9, 0x1F, 0x1F, 0xFF, 0x00, 0x10, 0xAF, 0x82, 0x7F, 0xE8, 0x1D, 0xFF,
+	0x00, 0xE0, 0x73, 0xFF, 0x00, 0x33, 0xF4, 0x4B, 0xFE, 0x09, 0x19, 0xE1, 0x0F, 0x01, 0x7F, 0xC1,
+	0x47, 0xFF, 0x00, 0x6C, 0x8B, 0x4F, 0xD9, 0x97, 0xC6, 0xB1, 0x6A, 0xDE, 0x1F, 0xD3, 0xEE, 0xBC,
+	0x3F, 0x7D, 0xA8, 0xB6, 0xA7, 0xA5, 0xDE, 0xC2, 0xF3, 0x46, 0xD0, 0x46, 0x08, 0x5C, 0x49, 0x11,
+	0xC0, 0x35, 0xC8, 0xFF, 0x00, 0xC1, 0x48, 0xB5, 0xBF, 0x08, 0x7E, 0xC4, 0x7F, 0xB6, 0xCF, 0x8F,
+	0xBF, 0x65, 0x7F, 0x0C, 0x68, 0x9A, 0xAE, 0xB1, 0x63, 0xE1, 0x1B, 0xEB, 0x6B, 0x5B, 0x6D, 0x43,
+	0x51, 0xBE, 0x89, 0x67, 0xB9, 0x69, 0x2C, 0xA1, 0xBA, 0x20, 0x85, 0x8F, 0x00, 0x0F, 0x37, 0xB7,
+	0x1E, 0x95, 0xDB, 0x7F, 0xC1, 0xAC, 0x3F, 0xF2, 0x96, 0x3D, 0x27, 0xFE, 0xC4, 0x5D, 0x6B, 0xFF,
+	0x00, 0x45, 0xAD, 0x79, 0x5F, 0xFC, 0x1C, 0x0F, 0xFF, 0x00, 0x29, 0x81, 0xF8, 0xE1, 0xFF, 0x00,
+	0x61, 0xCB, 0x3F, 0xFD, 0x35, 0xD9, 0x52, 0xFF, 0x00, 0x88, 0x91, 0xC6, 0x1E, 0xD3, 0xDA, 0x7D,
+	0x63, 0xE5, 0xCB, 0x1B, 0x7D, 0xD6, 0x05, 0xE1, 0xAF, 0x07, 0xC5, 0xFB, 0x25, 0x87, 0xD3, 0xFC,
+	0x52, 0xBF, 0xDF, 0x73, 0xCB, 0xCF, 0xED, 0x89, 0xA5, 0xB1, 0xCF, 0xFC, 0x20, 0x52, 0x9F, 0x71,
+	0x7D, 0xD7, 0xFF, 0x00, 0x1C, 0xA3, 0xFE, 0x1B, 0x0F, 0x4B, 0xFF, 0x00, 0xA1, 0x02, 0x6F, 0xFC,
+	0x0E, 0xFF, 0x00, 0xEC, 0x2B, 0xC2, 0xE4, 0xFF, 0x00, 0x58, 0xDF, 0xEF, 0x53, 0x69, 0xFF, 0x00,
+	0xC4, 0x4C, 0xE2, 0xFF, 0x00, 0xF9, 0xFC, 0xBF, 0xF0, 0x08, 0xFF, 0x00, 0x90, 0x7F, 0xC4, 0x2B,
+	0xE0, 0x9F, 0xFA, 0x07, 0x7F, 0xF8, 0x1C, 0xFF, 0x00, 0xCC, 0xF7, 0x61, 0xFB, 0x62, 0xE9, 0x80,
+	0x63, 0xFE, 0x10, 0x09, 0xBF, 0xF0, 0x3B, 0xFF, 0x00, 0xB0, 0xAF, 0xD4, 0xCF, 0xF8, 0x35, 0x77,
+	0xF6, 0x91, 0x8B, 0xE2, 0x77, 0xED, 0x27, 0xF1, 0x3F, 0xC0, 0x96, 0xFA, 0x33, 0x59, 0x47, 0xFF,
+	0x00, 0x08, 0x4D, 0xBD, 0xFC, 0xC8, 0xD2, 0x79, 0x99, 0xF2, 0x6E, 0xD5, 0x07, 0xCD, 0xDB, 0xFE,
+	0x3E, 0x3A, 0x57, 0xE1, 0xED, 0x7D, 0x69, 0xFF, 0x00, 0x04, 0x6C, 0xD7, 0x6F, 0x34, 0x4F, 0xDA,
+	0x83, 0x5A, 0xB7, 0xB2, 0xD5, 0x2E, 0xAD, 0x4D, 0xF7, 0x82, 0xAE, 0x06, 0xDB, 0x79, 0x36, 0x2B,
+	0x62, 0xEA, 0xD3, 0xAF, 0xE1, 0xBE, 0xB8, 0xF1, 0xBC, 0x75, 0xC4, 0x99, 0xAE, 0x16, 0x58, 0x4C,
+	0x55, 0x5E, 0x68, 0x4F, 0x46, 0xB9, 0x62, 0xBF, 0x24, 0x76, 0x60, 0x7C, 0x3F, 0xE1, 0x5C, 0x9F,
+	0x14, 0xB1, 0x78, 0x4A, 0x2E, 0x35, 0x23, 0xB3, 0xE6, 0x93, 0xB7, 0xDE, 0xD9, 0xFD, 0x6C, 0x01,
+	0xB4, 0x6D, 0xC5, 0x15, 0xF8, 0xB6, 0x7C, 0x4B, 0xE2, 0x5C, 0xFC, 0xDA, 0xED, 0xE7, 0xFC, 0x06,
+	0xEA, 0x4C, 0x7E, 0x95, 0xFA, 0x59, 0xFF, 0x00, 0x04, 0xDE, 0xBC, 0xB9, 0xBC, 0xFD, 0x93, 0xB4,
+	0x1B, 0x9B, 0xAB, 0x99, 0x26, 0x93, 0xED, 0xB7, 0xCB, 0xBA, 0x42, 0x4F, 0xFC, 0xBD, 0x3F, 0xAD,
+	0x7C, 0xC9, 0xF4, 0x07, 0xB9, 0xB8, 0x83, 0x7F, 0xCF, 0xB7, 0xFE, 0x05, 0x49, 0xFE, 0x86, 0x06,
+	0x09, 0x8F, 0xF4, 0xAF, 0x8B, 0xBF, 0x6C, 0xD0, 0x47, 0xC7, 0xBD, 0x40, 0x31, 0xE7, 0xEC, 0xB6,
+	0x9F, 0xFA, 0x2C, 0x57, 0x95, 0x0E, 0x95, 0xFC, 0xA5, 0xC5, 0x7F, 0x48, 0xFA, 0x3C, 0x35, 0xC4,
+	0x58, 0x9C, 0xAF, 0xFB, 0x2D, 0x4F, 0xD8, 0xCD, 0xC7, 0x9B, 0xDA, 0x25, 0xCD, 0x6B, 0x6B, 0x6F,
+	0x66, 0xED, 0xF7, 0xB3, 0xF4, 0x8C, 0xB3, 0x80, 0x27, 0x98, 0x65, 0xF4, 0xF1, 0x2B, 0x13, 0xCB,
+	0xCE, 0x93, 0xB7, 0x2D, 0xED, 0xF3, 0xE6, 0x47, 0xE9, 0x46, 0x6D, 0x3F, 0xE9, 0x9F, 0xE9, 0x46,
+	0x6D, 0x3F, 0xE9, 0x9F, 0xE9, 0x5F, 0x9A, 0xF4, 0x57, 0xCF, 0x7F, 0xC4, 0xD6, 0x61, 0xFF, 0x00,
+	0xE8, 0x4C, 0xBF, 0xF0, 0x6A, 0xFF, 0x00, 0xE5, 0x67, 0x6F, 0xFC, 0x43, 0x3A, 0x9F, 0xF4, 0x17,
+	0xFF, 0x00, 0x92, 0x7F, 0xF6, 0xC7, 0xE9, 0x47, 0xFA, 0x27, 0x7F, 0x2F, 0xF4, 0xA7, 0x8C, 0x01,
+	0x90, 0x78, 0xAF, 0xCD, 0x4A, 0xFD, 0x04, 0xF8, 0x25, 0xFF, 0x00, 0x24, 0x6F, 0xC2, 0x7F, 0xF6,
+	0x2D, 0xD8, 0xFF, 0x00, 0xE8, 0x84, 0xAF, 0xD6, 0xBC, 0x25, 0xF1, 0x82, 0x9F, 0x89, 0x79, 0x8E,
+	0x27, 0x0D, 0x0C, 0x0A, 0xC3, 0xFB, 0x28, 0x46, 0x57, 0x53, 0xE6, 0xBD, 0xDD, 0xAD, 0xF0, 0xC6,
+	0xDF, 0x89, 0xF3, 0x3C, 0x4B, 0xC2, 0xD2, 0xE1, 0xEA, 0x34, 0xEA, 0x3A, 0xDC, 0xFC, 0xED, 0xAF,
+	0x86, 0xD6, 0xB2, 0xF5, 0x67, 0x51, 0x45, 0x7E, 0x55, 0xFE, 0xD9, 0xBA, 0xF6, 0xB3, 0x6B, 0xFB,
+	0x53, 0xF8, 0xDA, 0x3B, 0x5D, 0x6A, 0xF1, 0x55, 0x75, 0xE2, 0x15, 0x56, 0xE6, 0x40, 0x17, 0xE5,
+	0x4E, 0x00, 0x15, 0xE5, 0xC3, 0xC4, 0xDE, 0x25, 0x61, 0xB8, 0xEB, 0xB7, 0xBF, 0xF8, 0x15, 0x2D,
+	0x7E, 0xE8, 0x7C, 0x81, 0xFB, 0x4B, 0x45, 0x7E, 0x2D, 0x7F, 0xC2, 0x4B, 0xE2, 0x4F, 0xFA, 0x0E,
+	0xDE, 0xFF, 0x00, 0xE0, 0x54, 0xB4, 0x7F, 0xC2, 0x4B, 0xE2, 0x4F, 0xFA, 0x0E, 0xDE, 0xFF, 0x00,
+	0xE0, 0x54, 0xB4, 0x01, 0xFB, 0x4B, 0x54, 0x60, 0x38, 0xF1, 0x15, 0xF1, 0xC7, 0xFC, 0xB8, 0x5B,
+	0x7F, 0xE8, 0x53, 0x57, 0xE3, 0x47, 0xFC, 0x24, 0xBE, 0x24, 0xFF, 0x00, 0xA0, 0xED, 0xEF, 0xFE,
+	0x05, 0x4B, 0x5F, 0x77, 0x7F, 0xC1, 0x24, 0x6F, 0xEF, 0xB5, 0x1F, 0x86, 0xBE, 0x31, 0x6B, 0xEB,
+	0xF9, 0x27, 0x65, 0xD7, 0x20, 0x01, 0xA5, 0x72, 0x71, 0xFB, 0x81, 0xC7, 0x34, 0x01, 0xF5, 0x66,
+	0x9D, 0xFF, 0x00, 0x1F, 0xDA, 0x87, 0xFD, 0x7E, 0x2F, 0xFE, 0x89, 0x8E, 0xAD, 0xD7, 0xE7, 0x5F,
+	0xFC, 0x15, 0x2B, 0x57, 0xD5, 0x6C, 0x3F, 0x69, 0x88, 0x62, 0xB0, 0xD4, 0xE7, 0xB7, 0x56, 0xF0,
+	0xC5, 0xAE, 0x52, 0x3B, 0x92, 0xB9, 0xFD, 0xE4, 0xDD, 0x87, 0x35, 0xF3, 0x77, 0xFC, 0x24, 0xBE,
+	0x24, 0xFF, 0x00, 0xA0, 0xED, 0xEF, 0xFE, 0x05, 0x4B, 0x40, 0x1F, 0xB4, 0xB4, 0x57, 0xE2, 0xD7,
+	0xFC, 0x24, 0xBE, 0x24, 0xFF, 0x00, 0xA0, 0xED, 0xEF, 0xFE, 0x05, 0x4B, 0x47, 0xFC, 0x24, 0xBE,
+	0x24, 0xFF, 0x00, 0xA0, 0xED, 0xEF, 0xFE, 0x05, 0x4B, 0x40, 0x1F, 0xB4, 0xB4, 0x13, 0x88, 0xD8,
+	0xE3, 0xB5, 0x7E, 0x2D, 0xAF, 0x89, 0xBC, 0x46, 0x0E, 0x4E, 0xBF, 0x7C, 0x38, 0xEA, 0xB7, 0x12,
+	0x1F, 0xE7, 0xC5, 0x7D, 0xC3, 0xFF, 0x00, 0x04, 0x8D, 0xBF, 0xBF, 0xD4, 0xBC, 0x37, 0xE3, 0xC9,
+	0x2F, 0xF5, 0x09, 0x6E, 0x1B, 0xED, 0xD6, 0x21, 0x5A, 0x66, 0xC9, 0x1F, 0xBB, 0x9A, 0x80, 0x3E,
+	0xB8, 0xD3, 0xBF, 0xE3, 0xFB, 0x50, 0xFF, 0x00, 0xAF, 0xC5, 0xFF, 0x00, 0xD1, 0x31, 0xD5, 0xBA,
+	0xFC, 0xEB, 0xFF, 0x00, 0x82, 0xA5, 0x6A, 0xFA, 0xAD, 0x87, 0xED, 0x31, 0x0C, 0x56, 0x1A, 0x9C,
+	0xF6, 0xEA, 0xDE, 0x18, 0xB5, 0xCA, 0x47, 0x72, 0x57, 0x3F, 0xBC, 0x9B, 0xB0, 0xE6, 0xBE, 0x6E,
+	0xFF, 0x00, 0x84, 0x97, 0xC4, 0x9F, 0xF4, 0x1D, 0xBD, 0xFF, 0x00, 0xC0, 0xA9, 0x68, 0x03, 0xF6,
+	0x96, 0x8A, 0xFC, 0x5A, 0xFF, 0x00, 0x84, 0x97, 0xC4, 0x9F, 0xF4, 0x1D, 0xBD, 0xFF, 0x00, 0xC0,
+	0xA9, 0x68, 0xFF, 0x00, 0x84, 0x97, 0xC4, 0x9F, 0xF4, 0x1D, 0xBD, 0xFF, 0x00, 0xC0, 0xA9, 0x68,
+	0x03, 0xF6, 0x96, 0x8A, 0xFC, 0x5B, 0x5F, 0x13, 0x78, 0x8C, 0x1C, 0x9D, 0x7E, 0xF8, 0x71, 0xD5,
+	0x6E, 0x24, 0x3F, 0xCF, 0x8A, 0xFB, 0x83, 0xFE, 0x09, 0x1F, 0xA8, 0x6A, 0x1A, 0x8F, 0x87, 0xFC,
+	0x75, 0x2D, 0xFD, 0xFC, 0xD7, 0x0C, 0x2F, 0xAC, 0x70, 0xD3, 0x3E, 0x48, 0xFD, 0xDC, 0xD4, 0x01,
+	0xF6, 0x32, 0x74, 0xA7, 0x54, 0x70, 0x7F, 0x17, 0xFB, 0xC3, 0xFF, 0x00, 0x41, 0x15, 0x25, 0x00,
+	0x14, 0x13, 0x81, 0x9A, 0x28, 0x3D, 0x28, 0x03, 0xE1, 0x4F, 0xF8, 0x2B, 0xEF, 0xFC, 0x8C, 0x7E,
+	0x07, 0xFF, 0x00, 0xAF, 0x2B, 0xEF, 0xFD, 0x19, 0x1D, 0x7C, 0x6D, 0x5F, 0x64, 0xFF, 0x00, 0xC1,
+	0x5F, 0x7F, 0xE4, 0x64, 0xF0, 0x3F, 0xFD, 0x79, 0x5F, 0x7F, 0xE8, 0xC8, 0xEB, 0xE3, 0x6A, 0x00,
+	0x28, 0xA2, 0x8A, 0x00, 0x07, 0x5A, 0xFA, 0xC3, 0xFE, 0x09, 0x1F, 0xFF, 0x00, 0x25, 0xAB, 0xC4,
+	0xBF, 0xF6, 0x2A, 0xAF, 0xFE, 0x94, 0xC5, 0x5F, 0x27, 0x8E, 0xB5, 0xF5, 0x7F, 0xFC, 0x12, 0x44,
+	0xED, 0xF8, 0xD1, 0xE2, 0x66, 0xFF, 0x00, 0xA9, 0x51, 0x7F, 0xF4, 0xA6, 0x2A, 0x00, 0xF5, 0xEF,
+	0xF8, 0x2B, 0x2F, 0xFC, 0x9B, 0x8E, 0x8F, 0xFF, 0x00, 0x63, 0x9D, 0xAF, 0xFE, 0x92, 0xDE, 0xD7,
+	0xE7, 0x95, 0x7E, 0x84, 0x7F, 0xC1, 0x58, 0xA7, 0xF3, 0x7F, 0x67, 0x5D, 0x0F, 0x09, 0xF7, 0xBC,
+	0x65, 0x6E, 0x73, 0xF4, 0xB5, 0xBA, 0xFF, 0x00, 0x1A, 0xFC, 0xF7, 0xA4, 0x83, 0xCC, 0x28, 0xA2,
+	0x8A, 0x60, 0x15, 0xEF, 0x5F, 0xF0, 0x4D, 0x8F, 0xF9, 0x3B, 0x9D, 0x07, 0xFE, 0xC1, 0xFA, 0x87,
+	0xFE, 0x93, 0xBD, 0x78, 0x2D, 0x7B, 0xD7, 0xFC, 0x13, 0x63, 0xFE, 0x4E, 0xE7, 0x41, 0xFF, 0x00,
+	0xB0, 0x7E, 0xA1, 0xFF, 0x00, 0xA4, 0xEF, 0x40, 0x1F, 0x64, 0xFF, 0x00, 0xC1, 0x44, 0x7F, 0xE4,
+	0xCE, 0xFC, 0x63, 0xFE, 0xE5, 0x97, 0xFE, 0x9C, 0x2D, 0x6B, 0xF2, 0xF2, 0xBF, 0x4F, 0x7F, 0xE0,
+	0xA2, 0x17, 0x22, 0x4F, 0xD8, 0xF3, 0xC5, 0xD8, 0x4E, 0xAD, 0x62, 0xBF, 0x4F, 0xF4, 0xE8, 0x0D,
+	0x7E, 0x61, 0x52, 0x41, 0xE6, 0x14, 0x51, 0x45, 0x30, 0x0A, 0xF4, 0x4F, 0xD9, 0x2B, 0xFE, 0x4E,
+	0x73, 0xC0, 0x3F, 0xF6, 0x35, 0x5A, 0x7F, 0xE8, 0x42, 0xBC, 0xEE, 0xBD, 0x13, 0xF6, 0x4A, 0xFF,
+	0x00, 0x93, 0x9C, 0xF0, 0x0F, 0xFD, 0x8D, 0x56, 0x9F, 0xFA, 0x10, 0xA0, 0x0F, 0xD2, 0xEF, 0xDA,
+	0x9B, 0xFE, 0x4D, 0x93, 0xE2, 0x2F, 0xFD, 0x88, 0xBA, 0xBF, 0xFE, 0x90, 0x4F, 0x5F, 0x8C, 0x35,
+	0xFB, 0x37, 0xFB, 0x50, 0x5C, 0x8F, 0xF8, 0x66, 0xCF, 0x88, 0x80, 0x26, 0x76, 0xF8, 0x2B, 0x54,
+	0x1F, 0x9D, 0xA4, 0x82, 0xBF, 0x1A, 0x12, 0x3F, 0x91, 0x78, 0x1D, 0x2B, 0xC8, 0xCC, 0xB3, 0x2C,
+	0x1E, 0x06, 0x51, 0x55, 0xA5, 0x6F, 0x93, 0x7F, 0x92, 0x67, 0xD4, 0x70, 0xFF, 0x00, 0x09, 0xE7,
+	0xBC, 0x49, 0x4A, 0x75, 0x32, 0xFA, 0x5C, 0xEA, 0x0D, 0x29, 0x6A, 0x95, 0xAF, 0xEA, 0xD1, 0x1D,
+	0x15, 0x2F, 0x95, 0xEC, 0x28, 0xF2, 0xBD, 0x85, 0x79, 0x9F, 0xEB, 0x06, 0x53, 0xFF, 0x00, 0x3F,
+	0x3F, 0x09, 0x7F, 0x91, 0xF4, 0x1F, 0xF1, 0x0B, 0xF8, 0xDB, 0xFE, 0x81, 0xBF, 0xF2, 0x78, 0x7F,
+	0xF2, 0x44, 0x55, 0xF4, 0x07, 0xFC, 0x13, 0x1B, 0xFE, 0x4F, 0x27, 0xC3, 0x5F, 0xF5, 0xEB, 0xA8,
+	0xFF, 0x00, 0xE9, 0x14, 0xB5, 0xE0, 0x9E, 0x57, 0xB0, 0xAF, 0xA0, 0xFF, 0x00, 0xE0, 0x97, 0xF6,
+	0x2C, 0xFF, 0x00, 0xB6, 0x26, 0x87, 0x38, 0x97, 0x6F, 0x93, 0xA7, 0x5F, 0x49, 0xB3, 0xD7, 0xF7,
+	0x0E, 0x9F, 0xFB, 0x52, 0xB6, 0xC3, 0xE7, 0x59, 0x76, 0x22, 0xB4, 0x69, 0xD3, 0x9D, 0xDD, 0xD2,
+	0xD9, 0xAD, 0xFD, 0x52, 0x39, 0xF1, 0xBE, 0x1D, 0xF1, 0x76, 0x57, 0x83, 0x9E, 0x33, 0x11, 0x87,
+	0xE5, 0xA7, 0x08, 0xB6, 0xDF, 0x34, 0x74, 0xFB, 0x9B, 0x7F, 0x81, 0xF6, 0xC7, 0xFC, 0x14, 0xA7,
+	0xFE, 0x4D, 0x27, 0x5C, 0xFF, 0x00, 0xAF, 0xCB, 0x1F, 0xFD, 0x28, 0x5A, 0xFC, 0xCB, 0xAF, 0xD3,
+	0x4F, 0xF8, 0x29, 0x4F, 0xFC, 0x9A, 0x4E, 0xB9, 0xFF, 0x00, 0x5F, 0x96, 0x3F, 0xFA, 0x50, 0xB5,
+	0xF9, 0x97, 0x5F, 0x48, 0x7E, 0x7E, 0x7C, 0x07, 0xFF, 0x00, 0x05, 0xA8, 0xCF, 0xFC, 0x24, 0xFF,
+	0x00, 0x0F, 0x7F, 0xEB, 0xC6, 0xFF, 0x00, 0xFF, 0x00, 0x46, 0xDB, 0xD7, 0xC3, 0xF5, 0xFB, 0xC9,
+	0xA2, 0x7C, 0x45, 0xFF, 0x00, 0x82, 0x3A, 0x78, 0x0A, 0xF6, 0xE9, 0x3F, 0xE0, 0xAA, 0xF6, 0x5A,
+	0x14, 0xF3, 0x5D, 0x43, 0x1F, 0xFC, 0x20, 0xED, 0xAD, 0x78, 0x63, 0x53, 0xBF, 0xC4, 0x60, 0xC9,
+	0xF6, 0xB0, 0x0D, 0x8C, 0x0E, 0x23, 0x1B, 0xFC, 0x9F, 0xF5, 0x9D, 0x7B, 0x56, 0xC0, 0xFD, 0xA1,
+	0xFF, 0x00, 0xE0, 0xCF, 0x72, 0xB9, 0x6D, 0x07, 0xC0, 0xE1, 0xBB, 0xFF, 0x00, 0xC5, 0xAD, 0xF1,
+	0x40, 0xC7, 0xE1, 0xF6, 0x2E, 0x2B, 0x19, 0xC7, 0x53, 0xB2, 0x9D, 0x5E, 0x5A, 0x69, 0x58, 0xFC,
+	0x03, 0xA2, 0xBF, 0x7F, 0x47, 0xED, 0x11, 0xFF, 0x00, 0x06, 0x7A, 0xF7, 0xD0, 0x7C, 0x0F, 0xFF,
+	0x00, 0x86, 0xBF, 0xC5, 0x1F, 0xFC, 0x87, 0x47, 0xFC, 0x34, 0x47, 0xFC, 0x19, 0xE9, 0xFF, 0x00,
+	0x40, 0x1F, 0x03, 0xFF, 0x00, 0xE1, 0xAF, 0xF1, 0x47, 0xFF, 0x00, 0x21, 0xD4, 0xFB, 0x36, 0x6D,
+	0xED, 0x9F, 0xF2, 0xB3, 0xF1, 0xCB, 0xFE, 0x09, 0x95, 0xFF, 0x00, 0x29, 0x26, 0xFD, 0x9E, 0xFF,
+	0x00, 0xEC, 0xB9, 0x78, 0x47, 0xFF, 0x00, 0x4F, 0x16, 0x95, 0xFA, 0x39, 0xFF, 0x00, 0x07, 0x8B,
+	0xFF, 0x00, 0xC9, 0xC7, 0xFC, 0x1B, 0xFF, 0x00, 0xB1, 0x0B, 0x50, 0xFF, 0x00, 0xD2, 0xD5, 0xAF,
+	0xA7, 0x7F, 0x67, 0xCF, 0x8E, 0xFF, 0x00, 0xF0, 0x6B, 0x0E, 0xB1, 0xF1, 0xEB, 0xC1, 0x3A, 0x4F,
+	0xEC, 0xED, 0xA1, 0xF8, 0x2F, 0xFE, 0x13, 0xEB, 0xAF, 0x19, 0x69, 0x71, 0xF8, 0x0A, 0x4B, 0x6F,
+	0x87, 0x1E, 0x21, 0x86, 0x45, 0xD6, 0x9A, 0xED, 0x12, 0xCB, 0x64, 0xB3, 0x5A, 0x2A, 0xC6, 0xDE,
+	0x78, 0x4F, 0x99, 0xD8, 0x27, 0xF7, 0xB0, 0x31, 0x5F, 0x30, 0x7F, 0xC1, 0xE2, 0x83, 0x1F, 0xB4,
+	0x6F, 0xC1, 0xA0, 0x37, 0x7F, 0xC8, 0x83, 0x7F, 0xF7, 0x9B, 0x27, 0xFE, 0x3F, 0x17, 0xA9, 0xEE,
+	0x6A, 0xA3, 0x1B, 0x45, 0x99, 0xC6, 0x7C, 0xD5, 0xA3, 0xA6, 0xC7, 0xE3, 0xA9, 0xEB, 0x45, 0x07,
+	0xAD, 0x15, 0x89, 0xD4, 0x14, 0x51, 0x45, 0x00, 0x7D, 0xA5, 0xFF, 0x00, 0x04, 0x09, 0xFD, 0x94,
+	0xFE, 0x08, 0xFE, 0xD8, 0x7F, 0xF0, 0x51, 0xAD, 0x07, 0xE1, 0x5F, 0xED, 0x09, 0xE0, 0xD1, 0xE2,
+	0x1F, 0x0E, 0x43, 0xE1, 0xED, 0x4B, 0x53, 0x7D, 0x06, 0x4B, 0xA9, 0x23, 0xB7, 0xB9, 0x9E, 0x18,
+	0xC0, 0x88, 0x4A, 0xF1, 0x7C, 0xE5, 0x03, 0x16, 0x7D, 0xA3, 0x80, 0xC3, 0xE6, 0xAF, 0xA5, 0xC7,
+	0xFC, 0x14, 0x87, 0xFE, 0x08, 0x20, 0xDF, 0x10, 0x3F, 0xE1, 0x5F, 0xFF, 0x00, 0xC3, 0x98, 0x55,
+	0x67, 0x1A, 0xC7, 0xF6, 0x7F, 0xDA, 0xBE, 0xDB, 0x0B, 0x6D, 0x7F, 0x3C, 0x44, 0x1D, 0x95, 0x1F,
+	0x70, 0x40, 0x4E, 0x70, 0x70, 0x40, 0xAF, 0x2E, 0xFF, 0x00, 0x83, 0x59, 0x8E, 0x3F, 0xE0, 0xAC,
+	0xBA, 0x4F, 0xFD, 0x89, 0x3A, 0xD7, 0xFE, 0x88, 0x4A, 0xF8, 0x80, 0xFF, 0x00, 0xC9, 0xCA, 0xFF,
+	0x00, 0xDC, 0xF4, 0xBF, 0xFA, 0x5A, 0x6B, 0x48, 0xBB, 0x58, 0xE7, 0x92, 0xE6, 0x93, 0x6C, 0xFA,
+	0x57, 0xFE, 0x0B, 0xE5, 0xFB, 0x27, 0x7C, 0x11, 0xFD, 0x8B, 0xFF, 0x00, 0xE0, 0xA3, 0xBE, 0x23,
+	0xF8, 0x57, 0xFB, 0x3F, 0xF8, 0x4D, 0x7C, 0x3F, 0xE1, 0xA9, 0xB4, 0x5D, 0x37, 0x57, 0xB6, 0xD0,
+	0xCC, 0xCD, 0x25, 0xBD, 0xA3, 0xCD, 0x0B, 0x19, 0x22, 0x84, 0x39, 0x27, 0xCA, 0x67, 0x46, 0x62,
+	0x33, 0xB5, 0x5B, 0xD8, 0x57, 0xDD, 0x5F, 0xB6, 0xA6, 0xA1, 0xFF, 0x00, 0x04, 0x4D, 0xFF, 0x00,
+	0x82, 0x4B, 0x6B, 0x5F, 0x0F, 0xFF, 0x00, 0x66, 0x5F, 0x8A, 0x7F, 0xF0, 0x4C, 0x66, 0xF8, 0x85,
+	0xAB, 0x6A, 0x1F, 0x0D, 0x74, 0xBD, 0x7A, 0x5F, 0x14, 0x36, 0xA8, 0x9F, 0x68, 0x98, 0x4D, 0x2C,
+	0xF0, 0x19, 0x26, 0xCC, 0xA4, 0xEF, 0x79, 0xAD, 0x59, 0x9B, 0x68, 0x09, 0x96, 0x38, 0x18, 0xC5,
+	0x7C, 0xC7, 0xFF, 0x00, 0x07, 0x4D, 0x71, 0xFF, 0x00, 0x05, 0x63, 0xD5, 0xBF, 0xEC, 0x47, 0xD1,
+	0x7F, 0xF4, 0x5B, 0xD6, 0xE7, 0xFC, 0x1D, 0x4F, 0xFF, 0x00, 0x27, 0xC5, 0xF0, 0x97, 0xFE, 0xCD,
+	0xD7, 0x40, 0xFF, 0x00, 0xD3, 0x8E, 0xAF, 0x42, 0xB6, 0xE1, 0x79, 0x4B, 0x95, 0x1D, 0x47, 0xFC,
+	0x14, 0x57, 0xE0, 0xAF, 0xFC, 0x13, 0x9F, 0xF6, 0x93, 0xFF, 0x00, 0x82, 0x38, 0x69, 0xFF, 0x00,
+	0xF0, 0x52, 0x5F, 0xD8, 0xFB, 0xF6, 0x45, 0x8B, 0xE1, 0x2E, 0xA9, 0xA7, 0x7C, 0x4A, 0x8B, 0x46,
+	0x7B, 0x3B, 0x5B, 0xD7, 0x63, 0x77, 0x6A, 0xCE, 0xD0, 0x4B, 0x0C, 0xBB, 0x25, 0xF2, 0xB0, 0xD2,
+	0x18, 0xDC, 0x36, 0x37, 0x0D, 0x9B, 0x7F, 0x8E, 0xBF, 0x31, 0x7E, 0x0C, 0x7C, 0x26, 0xF1, 0x27,
+	0xC7, 0x8F, 0x8C, 0x5E, 0x12, 0xF8, 0x19, 0xE0, 0xA6, 0xB6, 0x5D, 0x6B, 0xC6, 0x9E, 0x24, 0xD3,
+	0xF4, 0x3D, 0x19, 0xAF, 0x26, 0x65, 0x81, 0x2E, 0x6F, 0x2E, 0xBE, 0xCC, 0xAC, 0xE4, 0x6F, 0x75,
+	0x50, 0xF2, 0x0E, 0x15, 0x1B, 0x1E, 0xA6, 0xBF, 0x4B, 0xBF, 0xE7, 0x53, 0x68, 0xFF, 0x00, 0xEC,
+	0xBA, 0x0F, 0xFD, 0x2A, 0xAF, 0xCD, 0x9F, 0xD9, 0xFE, 0xDB, 0xE2, 0xD5, 0xEF, 0xC7, 0x6F, 0x04,
+	0x59, 0xFE, 0xCF, 0xD3, 0x5D, 0xAF, 0x8F, 0x25, 0xF1, 0x6E, 0x9A, 0x3C, 0x15, 0xF6, 0x39, 0x51,
+	0x27, 0x5D, 0x5B, 0xED, 0x71, 0x7D, 0x94, 0xC2, 0xCD, 0xFB, 0xB1, 0x27, 0x9D, 0xE5, 0x6C, 0xF3,
+	0x38, 0xDF, 0xB7, 0x34, 0xA5, 0xF1, 0x15, 0x4E, 0x56, 0xA6, 0xD5, 0xCF, 0xA2, 0x3F, 0xE0, 0xA7,
+	0xBF, 0xF0, 0x47, 0x3F, 0xDA, 0x37, 0xFE, 0x09, 0x5F, 0x67, 0xE0, 0xFD, 0x4B, 0xE3, 0x9F, 0x8E,
+	0x3C, 0x1F, 0xE2, 0x0B, 0x3F, 0x19, 0x35, 0xD4, 0x36, 0x37, 0x1E, 0x17, 0xBC, 0xB9, 0x95, 0xE2,
+	0x9A, 0x0F, 0x29, 0xA6, 0x57, 0x17, 0x16, 0xF1, 0xB6, 0xD0, 0xB2, 0xC7, 0x86, 0x50, 0x3E, 0x83,
+	0xA5, 0x66, 0xFF, 0x00, 0xC1, 0x16, 0x3F, 0x66, 0xBF, 0x84, 0xFF, 0x00, 0xB5, 0xEF, 0xFC, 0x14,
+	0xD7, 0xE1, 0x7F, 0xEC, 0xFF, 0x00, 0xF1, 0xCF, 0xC3, 0xCF, 0xAB, 0xF8, 0x5F, 0x5A, 0xB9, 0xD4,
+	0xE6, 0xD5, 0x34, 0xF1, 0x79, 0x24, 0x62, 0xE3, 0xEC, 0xBA, 0x45, 0xF5, 0xEC, 0x48, 0xD2, 0x27,
+	0xCC, 0x07, 0x9D, 0x0A, 0x6E, 0x53, 0xCB, 0x0F, 0x37, 0x35, 0xE8, 0x9F, 0xF0, 0x59, 0xEF, 0x0D,
+	0xFF, 0x00, 0xC1, 0x68, 0xB4, 0x3B, 0x5F, 0x87, 0xF7, 0x1F, 0xF0, 0x55, 0xDD, 0x6E, 0x4B, 0xEB,
+	0x37, 0x5B, 0xE4, 0xF0, 0x3B, 0x47, 0x75, 0xA3, 0x49, 0x6F, 0x1C, 0xC1, 0x22, 0xFB, 0x40, 0x29,
+	0xA7, 0x10, 0xAC, 0xC0, 0x7D, 0x9F, 0x32, 0x4E, 0xAC, 0x49, 0xE4, 0x66, 0xA1, 0xFF, 0x00, 0x83,
+	0x70, 0x76, 0x9F, 0xF8, 0x2D, 0x17, 0xC1, 0x9F, 0x2C, 0x82, 0xBF, 0xF1, 0x51, 0x6D, 0x2B, 0xDC,
+	0x7F, 0xC2, 0x39, 0xAA, 0x7B, 0x0F, 0xE4, 0x29, 0xDA, 0x3E, 0xD0, 0x39, 0xA5, 0xEC, 0x6F, 0x73,
+	0xE9, 0x4F, 0x8C, 0xFF, 0x00, 0xF0, 0x50, 0xCF, 0xF8, 0x20, 0xCF, 0xC1, 0x6F, 0x8C, 0x3E, 0x2A,
+	0xF8, 0x3F, 0xAA, 0x7F, 0xC1, 0x1A, 0x21, 0xBC, 0xBA, 0xF0, 0x97, 0x89, 0xAF, 0xF4, 0x9B, 0x9B,
+	0xE8, 0x6F, 0x10, 0xC5, 0x24, 0xD6, 0x57, 0x0F, 0x07, 0x9D, 0xB1, 0x9C, 0x32, 0xA1, 0x68, 0xF7,
+	0x00, 0x79, 0x03, 0x83, 0xCD, 0x7C, 0xF3, 0xFF, 0x00, 0x07, 0x0F, 0xFE, 0xC9, 0x3F, 0xB3, 0xC7,
+	0xEC, 0x8F, 0xFB, 0x6E, 0x78, 0x77, 0xC3, 0xFF, 0x00, 0xB3, 0x37, 0xC3, 0xC4, 0xF0, 0xB7, 0x87,
+	0x7C, 0x61, 0xF0, 0xBF, 0x4D, 0xF1, 0x34, 0xFA, 0x0C, 0x13, 0xCB, 0x2D, 0xBD, 0xB5, 0xD4, 0xD7,
+	0x77, 0x96, 0xEE, 0xB0, 0x86, 0x25, 0x51, 0x1A, 0x3B, 0x48, 0x59, 0xC0, 0x38, 0x0D, 0xD3, 0x8A,
+	0xF9, 0x9B, 0xF6, 0xEF, 0xFF, 0x00, 0x93, 0xE3, 0xF8, 0xCD, 0xFF, 0x00, 0x65, 0x5B, 0xC4, 0x5F,
+	0xFA, 0x5F, 0x71, 0x5F, 0x70, 0xFF, 0x00, 0xC1, 0xD5, 0x1F, 0xF2, 0x7B, 0xDF, 0x09, 0x7F, 0xEC,
+	0xDD, 0x74, 0x1F, 0xFD, 0x39, 0xEA, 0xB4, 0xB7, 0x89, 0x3C, 0xAA, 0x33, 0x56, 0x67, 0xB6, 0x7C,
+	0x6C, 0x1F, 0xF0, 0x46, 0xFF, 0x00, 0xF8, 0x25, 0xB7, 0xEC, 0xE1, 0xF0, 0x0F, 0xC3, 0xBF, 0x1B,
+	0xBF, 0xE0, 0x9B, 0xD1, 0xFC, 0x4D, 0xD7, 0xBE, 0x22, 0x7C, 0x29, 0xB1, 0xF1, 0x25, 0xF7, 0x89,
+	0x2E, 0xAF, 0xC7, 0x9C, 0xF7, 0x12, 0xC3, 0x1C, 0x93, 0x99, 0x1E, 0x57, 0xE4, 0x19, 0x1D, 0x8A,
+	0xC6, 0x9F, 0x2A, 0x03, 0x81, 0xC0, 0xAE, 0x47, 0xF6, 0xAB, 0xF8, 0x53, 0xFF, 0x00, 0x04, 0xC5,
+	0xFD, 0xB5, 0x3F, 0xE0, 0x8A, 0xFF, 0x00, 0x12, 0x3F, 0xE0, 0xA1, 0x1F, 0xB2, 0x47, 0xEC, 0x5B,
+	0x37, 0xC1, 0xFD, 0x73, 0xE1, 0x9F, 0x8F, 0xAC, 0x74, 0x3B, 0x39, 0x23, 0xBC, 0x77, 0x92, 0xE3,
+	0xCC, 0xBA, 0xD2, 0x56, 0x73, 0x22, 0xA4, 0xBB, 0x65, 0x8B, 0x66, 0xA4, 0x18, 0x67, 0xF7, 0x82,
+	0x48, 0x38, 0xE2, 0xB8, 0x1F, 0xF8, 0x38, 0xB7, 0xFE, 0x49, 0x9F, 0xEC, 0x73, 0x8F, 0xFA, 0x36,
+	0xFD, 0x3B, 0xFF, 0x00, 0x45, 0x5A, 0xD6, 0xE7, 0xEC, 0xA0, 0x7F, 0xE3, 0x93, 0x7F, 0xDA, 0x80,
+	0x7F, 0xD5, 0x70, 0xB0, 0xFF, 0x00, 0xD2, 0x8F, 0x09, 0x55, 0x69, 0xB1, 0x3C, 0xAD, 0x46, 0x32,
+	0xEE, 0xCF, 0xCA, 0xB1, 0x8C, 0x70, 0xBB, 0x7F, 0xD9, 0xF4, 0xFD, 0x4F, 0xF3, 0x34, 0x51, 0x45,
+	0x64, 0x75, 0x05, 0x14, 0x51, 0x40, 0x07, 0x7F, 0xF8, 0x09, 0xFE, 0x6B, 0x5F, 0xBF, 0xDF, 0xF0,
+	0x72, 0xDF, 0xFC, 0xA1, 0x07, 0xE0, 0x2F, 0xFD, 0x8E, 0xDE, 0x17, 0xFF, 0x00, 0xD4, 0x6B, 0x54,
+	0xAF, 0xC0, 0x1E, 0xFF, 0x00, 0xF0, 0x13, 0xFC, 0xD6, 0xBF, 0xAB, 0x6F, 0xDA, 0xBF, 0xC6, 0x7F,
+	0xF0, 0x4E, 0x3F, 0x03, 0x7F, 0xC1, 0x3C, 0xBE, 0x11, 0x6A, 0xBF, 0xF0, 0x54, 0x2B, 0x3D, 0x26,
+	0x7F, 0x87, 0xF3, 0x5B, 0x68, 0x70, 0x68, 0xF1, 0xEB, 0x5A, 0x0D, 0xF6, 0xA1, 0x17, 0xF6, 0xC1,
+	0xD2, 0x66, 0x68, 0xB1, 0x1D, 0x9C, 0x52, 0x48, 0x1B, 0xC8, 0x4B, 0xAC, 0x12, 0x36, 0xE3, 0x39,
+	0xE7, 0x6D, 0x69, 0x0D, 0x9A, 0x39, 0x6B, 0x69, 0x34, 0xCF, 0xE5, 0x26, 0x8A, 0xFD, 0xFC, 0x5F,
+	0xDA, 0x1F, 0xFE, 0x0C, 0xF6, 0x03, 0x0F, 0xA0, 0xF8, 0x1B, 0x3D, 0xF1, 0xF0, 0xBF, 0xC4, 0xFF,
+	0x00, 0xFC, 0x85, 0x4B, 0xFF, 0x00, 0x0D, 0x11, 0xFF, 0x00, 0x06, 0x7A, 0x7F, 0xD0, 0x07, 0xC0,
+	0xFF, 0x00, 0xF8, 0x6B, 0xFC, 0x51, 0xFF, 0x00, 0xC8, 0x74, 0x7B, 0x33, 0x4F, 0x6C, 0xFF, 0x00,
+	0x95, 0x9F, 0x80, 0x54, 0x57, 0xEF, 0xEF, 0xFC, 0x34, 0x47, 0xFC, 0x19, 0xE9, 0xFF, 0x00, 0x40,
+	0x1F, 0x03, 0xFF, 0x00, 0xE1, 0xAF, 0xF1, 0x47, 0xFF, 0x00, 0x21, 0xD1, 0xFF, 0x00, 0x0D, 0x11,
+	0xFF, 0x00, 0x06, 0x7A, 0x7F, 0xD0, 0x07, 0xC0, 0xFF, 0x00, 0xF8, 0x6B, 0xFC, 0x51, 0xFF, 0x00,
+	0xC8, 0x74, 0x7B, 0x36, 0x1E, 0xD9, 0xFF, 0x00, 0x2B, 0x3F, 0x32, 0xBF, 0xE0, 0xDF, 0xBF, 0xF9,
+	0x4C, 0x27, 0xC1, 0x0F, 0xFB, 0x0F, 0x5E, 0x7F, 0xE9, 0xAE, 0xFE, 0xBB, 0x0F, 0xF8, 0x39, 0x9F,
+	0xFE, 0x53, 0x1F, 0xF1, 0x1B, 0xFE, 0xC1, 0xFE, 0x1F, 0xFF, 0x00, 0xD3, 0x35, 0xB5, 0x7E, 0xAB,
+	0x7E, 0xC4, 0xDF, 0x1A, 0x3F, 0xE0, 0xDA, 0xAF, 0x12, 0x7E, 0xD4, 0xBE, 0x11, 0xD2, 0x3F, 0x61,
+	0xDD, 0x1B, 0xC2, 0x71, 0xFC, 0x52, 0xB8, 0xBC, 0x9C, 0x78, 0x3D, 0xB4, 0xFF, 0x00, 0x01, 0xF8,
+	0x82, 0xD6, 0x51, 0x38, 0xB6, 0x9F, 0xCC, 0xDA, 0xF7, 0x36, 0xA9, 0x10, 0xFD, 0xC7, 0x9F, 0x9C,
+	0x9F, 0xEF, 0x56, 0xB7, 0xFC, 0x14, 0x13, 0xE3, 0x0F, 0xFC, 0x1B, 0xAD, 0xE1, 0x0F, 0xDA, 0xB7,
+	0xC4, 0x3A, 0x1F, 0xFC, 0x14, 0x27, 0x4C, 0xF0, 0xAC, 0xFF, 0x00, 0x15, 0x61, 0x82, 0xCD, 0xB5,
+	0xC7, 0xD5, 0x3C, 0x11, 0xAD, 0x5E, 0xCD, 0xE4, 0x9B, 0x78, 0xBE, 0xCD, 0xBA, 0x6B, 0x3B, 0x56,
+	0x89, 0xC7, 0x93, 0xE4, 0xE1, 0x72, 0x4A, 0xD5, 0x28, 0xDE, 0x26, 0x3E, 0xDB, 0xF7, 0xCA, 0x56,
+	0xE8, 0x7F, 0x33, 0x63, 0xA5, 0x7D, 0xFD, 0xFF, 0x00, 0x06, 0xC8, 0x7F, 0xCA, 0x60, 0xFC, 0x03,
+	0xFF, 0x00, 0x60, 0x1F, 0x10, 0x7F, 0xE9, 0xAA, 0x7A, 0xFB, 0xF5, 0x3F, 0x68, 0x7F, 0xF8, 0x33,
+	0xDC, 0x22, 0x83, 0xA1, 0x78, 0x1F, 0xA7, 0xFD, 0x13, 0x1F, 0x14, 0x7F, 0xF2, 0x1D, 0x7B, 0x67,
+	0xFC, 0x13, 0xD3, 0xE3, 0x17, 0xFC, 0x1B, 0xAF, 0xE2, 0xCF, 0xDA, 0x97, 0x44, 0xD0, 0xFF, 0x00,
+	0xE0, 0x9E, 0x3A, 0x47, 0x85, 0xA1, 0xF8, 0xA9, 0x35, 0xA5, 0xE1, 0xD0, 0xDF, 0x4B, 0xF0, 0x2E,
+	0xBB, 0x63, 0x37, 0x90, 0x21, 0x6F, 0xB4, 0xE2, 0x4B, 0xBB, 0x58, 0xE2, 0x1F, 0xBA, 0xDF, 0x9D,
+	0xC6, 0xA6, 0x34, 0xED, 0x22, 0xA7, 0x57, 0x9A, 0x0D, 0x58, 0xFC, 0x9A, 0xFF, 0x00, 0x83, 0x9D,
+	0x3F, 0xE5, 0x30, 0x9E, 0x3D, 0xFF, 0x00, 0xB0, 0x1E, 0x83, 0xFF, 0x00, 0xA6, 0xDB, 0x7A, 0xFC,
+	0xFD, 0x1D, 0x2B, 0xFA, 0x65, 0xFF, 0x00, 0x82, 0x86, 0xFC, 0x5D, 0xFF, 0x00, 0x83, 0x76, 0xFC,
+	0x21, 0xFB, 0x52, 0x6B, 0x9A, 0x47, 0xFC, 0x14, 0x1F, 0x4B, 0xF0, 0xAC, 0xDF, 0x14, 0xA3, 0xB5,
+	0xB3, 0x7D, 0x69, 0xF5, 0x4F, 0x06, 0x6B, 0x77, 0xD3, 0x18, 0x4D, 0xAA, 0xFD, 0x9B, 0x74, 0xF6,
+	0x96, 0xB2, 0x44, 0x47, 0x91, 0xB7, 0x03, 0x24, 0xD7, 0x8A, 0xC7, 0xFB, 0x44, 0x7F, 0xC1, 0x9E,
+	0xFE, 0x5A, 0xEE, 0xF0, 0xFF, 0x00, 0x81, 0xC1, 0xDB, 0xC8, 0xFF, 0x00, 0x85, 0x5F, 0xE2, 0x81,
+	0x8F, 0xFC, 0x92, 0x1F, 0xC8, 0x51, 0x2A, 0x6F, 0x9B, 0x71, 0xC6, 0xB7, 0x2D, 0x34, 0xAC, 0xCF,
+	0xC0, 0x53, 0xF7, 0x9B, 0xFC, 0xFF, 0x00, 0x05, 0x7E, 0xF0, 0xFF, 0x00, 0xC1, 0xD8, 0xDF, 0xF2,
+	0x64, 0x3F, 0xB3, 0xD7, 0xFD, 0x87, 0x9B, 0xFF, 0x00, 0x4D, 0xB1, 0xD6, 0xB5, 0xCF, 0xED, 0x03,
+	0xFF, 0x00, 0x06, 0x7F, 0x98, 0xC2, 0xA6, 0x83, 0xE0, 0x65, 0x59, 0x32, 0xBB, 0x97, 0xE1, 0x9F,
+	0x89, 0xFB, 0xEE, 0xC7, 0x5B, 0x3C, 0x29, 0xCF, 0x76, 0xE2, 0xBE, 0xD3, 0xFF, 0x00, 0x82, 0x9C,
+	0x7C, 0x44, 0xFF, 0x00, 0x82, 0x4E, 0x78, 0x2F, 0xE1, 0x27, 0x81, 0x75, 0x3F, 0xF8, 0x29, 0xAE,
+	0x9D, 0xA2, 0x49, 0xE1, 0x2B, 0xCB, 0xE0, 0x7C, 0x13, 0x1E, 0xAF, 0xE1, 0x5D, 0x53, 0x50, 0x8C,
+	0x4D, 0xE4, 0x02, 0xC1, 0x23, 0xB2, 0xB7, 0x67, 0x8C, 0xF9, 0x5B, 0x7E, 0xFA, 0x80, 0x3D, 0x06,
+	0x31, 0x55, 0x18, 0xE8, 0xC8, 0x95, 0x5F, 0xDE, 0x45, 0xD9, 0x9F, 0xC9, 0x9A, 0x7D, 0xC1, 0xF4,
+	0xA5, 0xAF, 0xDF, 0xB8, 0x7F, 0x68, 0x7F, 0xF8, 0x33, 0xDC, 0x44, 0xA2, 0x4D, 0x03, 0xC1, 0x3B,
+	0xB6, 0x8D, 0xDB, 0xBE, 0x18, 0x78, 0x9F, 0x39, 0xFC, 0x2C, 0xF1, 0xF9, 0x71, 0x4E, 0xFF, 0x00,
+	0x86, 0x88, 0xFF, 0x00, 0x83, 0x3D, 0x3F, 0xE8, 0x03, 0xE0, 0x7F, 0xFC, 0x35, 0xFE, 0x28, 0xFF,
+	0x00, 0xE4, 0x3A, 0x9F, 0x66, 0xCD, 0xBD, 0xB3, 0xFE, 0x56, 0x7E, 0x01, 0x51, 0x5F, 0xBF, 0xBF,
+	0xF0, 0xD1, 0x1F, 0xF0, 0x67, 0xA7, 0xFD, 0x00, 0x7C, 0x0F, 0xFF, 0x00, 0x86, 0xBF, 0xC5, 0x1F,
+	0xFC, 0x87, 0x47, 0xFC, 0x34, 0x47, 0xFC, 0x19, 0xE9, 0xFF, 0x00, 0x40, 0x1F, 0x03, 0xFF, 0x00,
+	0xE1, 0xAF, 0xF1, 0x47, 0xFF, 0x00, 0x21, 0xD1, 0xEC, 0xD8, 0x7B, 0x67, 0xFC, 0xAC, 0xFC, 0xE4,
+	0xFF, 0x00, 0x83, 0x6F, 0x3F, 0xE5, 0x34, 0x5F, 0x06, 0x7F, 0xDE, 0xF1, 0x0F, 0xFE, 0xA3, 0x9A,
+	0x9D, 0x6F, 0xFF, 0x00, 0xC1, 0xCE, 0x7F, 0xF2, 0x98, 0x2F, 0x1E, 0x7F, 0xD8, 0x07, 0x40, 0xFF,
+	0x00, 0xD3, 0x65, 0xBD, 0x7E, 0xAB, 0x7E, 0xC0, 0xDF, 0x19, 0x7F, 0xE0, 0xDC, 0x2F, 0x16, 0xFE,
+	0xD6, 0xFE, 0x14, 0xD0, 0x3F, 0x60, 0x9D, 0x23, 0xC2, 0xD0, 0xFC, 0x57, 0xB9, 0x6D, 0x40, 0xF8,
+	0x4A, 0x4D, 0x2F, 0xC0, 0x7A, 0xE5, 0x8C, 0xE1, 0x56, 0xC2, 0xE7, 0xED, 0x5B, 0x25, 0xBA, 0xB5,
+	0x8E, 0x24, 0xFF, 0x00, 0x45, 0xFB, 0x46, 0x4C, 0x87, 0xE6, 0x19, 0xC7, 0xF0, 0xD7, 0xE5, 0x47,
+	0xFC, 0x1C, 0xE0, 0x49, 0xFF, 0x00, 0x82, 0xC0, 0x78, 0xF0, 0x96, 0xCF, 0xFC, 0x48, 0x74, 0x0E,
+	0x7D, 0x7F, 0xE2, 0x5B, 0x6F, 0x47, 0xD8, 0x26, 0x9C, 0xB9, 0xB1, 0x37, 0xF2, 0x3E, 0x11, 0xF0,
+	0x66, 0x8F, 0x69, 0xE2, 0x2F, 0x16, 0xE9, 0x3E, 0x1F, 0xBF, 0x9D, 0xA3, 0x83, 0x51, 0xD4, 0xAD,
+	0xED, 0x2E, 0x25, 0x8D, 0x8A, 0x32, 0xC7, 0x24, 0x81, 0x37, 0x8F, 0xEE, 0xE3, 0x2C, 0x9B, 0x97,
+	0xE6, 0xAF, 0xDA, 0xEF, 0xF8, 0x28, 0x17, 0xC4, 0x7F, 0xF8, 0x21, 0x9F, 0xFC, 0x12, 0xFF, 0x00,
+	0xE3, 0xD7, 0xFC, 0x32, 0x5F, 0x8C, 0xFF, 0x00, 0xE0, 0x93, 0x50, 0x78, 0xC2, 0xF3, 0x4D, 0xF0,
+	0xED, 0x8D, 0xCC, 0x9A, 0xD4, 0x1A, 0x92, 0xB4, 0x92, 0x24, 0xAA, 0x18, 0x6F, 0x7B, 0x87, 0xDE,
+	0xCD, 0xEA, 0xC7, 0x92, 0x72, 0x6B, 0xF1, 0x6F, 0xE1, 0x7F, 0xFC, 0x94, 0x9F, 0x0E, 0xFF, 0x00,
+	0xD8, 0x76, 0xC7, 0xFF, 0x00, 0x47, 0xAD, 0x7E, 0x80, 0x7F, 0xC1, 0xD3, 0xD9, 0xFF, 0x00, 0x87,
+	0xB1, 0x6A, 0xDC, 0x7F, 0xCC, 0x8B, 0xA3, 0x7F, 0xE8, 0x96, 0xA9, 0x8F, 0xF0, 0xCA, 0x9C, 0x63,
+	0x2A, 0xC9, 0x33, 0x7B, 0xFE, 0x0A, 0xF3, 0xF0, 0x5F, 0xF6, 0x0A, 0xF8, 0x83, 0xFF, 0x00, 0x04,
+	0xD1, 0xF8, 0x27, 0xFF, 0x00, 0x05, 0x1D, 0xFD, 0x8D, 0xFF, 0x00, 0x66, 0x53, 0xF0, 0xB1, 0xBC,
+	0x75, 0xE3, 0x0D, 0x4B, 0x45, 0x9F, 0x45, 0xB3, 0xBA, 0x12, 0x09, 0x6D, 0x60, 0x92, 0xFA, 0x06,
+	0x79, 0x54, 0x12, 0xBE, 0x60, 0x96, 0xC4, 0xB2, 0xB4, 0x5F, 0x3E, 0x25, 0xF9, 0xF9, 0xCD, 0x74,
+	0x5F, 0xB0, 0x2F, 0xC3, 0x7F, 0xF8, 0x26, 0xCF, 0xEC, 0xB7, 0xFF, 0x00, 0x04, 0x75, 0x87, 0xFE,
+	0x0A, 0x0B, 0xFB, 0x60, 0xFE, 0xC6, 0xA9, 0xF1, 0x6B, 0x56, 0xD7, 0xFE, 0x2A, 0x4D, 0xE1, 0xE6,
+	0x86, 0x7B, 0xC3, 0xBA, 0xD6, 0x24, 0x8E, 0x4F, 0x2B, 0xCA, 0x57, 0x90, 0x45, 0x1C, 0x6A, 0x63,
+	0x72, 0xCF, 0x80, 0xCC, 0xD2, 0x67, 0xBD, 0x73, 0x9F, 0xB6, 0x06, 0x7F, 0xE2, 0x18, 0x1F, 0xD9,
+	0x3B, 0xFE, 0xCA, 0xBE, 0xBD, 0xFF, 0x00, 0xA7, 0x1D, 0x7E, 0xA3, 0xF1, 0x5F, 0xFC, 0xAA, 0xAF,
+	0xE1, 0x7F, 0xFB, 0x38, 0xF7, 0xFF, 0x00, 0xD1, 0x37, 0x55, 0xA7, 0xDA, 0x23, 0xDE, 0xE4, 0x4A,
+	0xFD, 0x4F, 0x7B, 0xFD, 0x98, 0x6E, 0xBF, 0xE0, 0x8B, 0x9F, 0xF0, 0x55, 0x4F, 0x04, 0x7C, 0x62,
+	0xF8, 0x49, 0xF0, 0x87, 0xFE, 0x09, 0x98, 0xDF, 0x0F, 0x35, 0xBF, 0x0A, 0x7C, 0x2B, 0xD4, 0xB5,
+	0xFB, 0x5F, 0x11, 0x7F, 0x6A, 0x2A, 0x5C, 0xDB, 0x4B, 0x12, 0xA7, 0x92, 0x63, 0x92, 0x09, 0x37,
+	0x2C, 0xCB, 0x2C, 0x89, 0x20, 0x57, 0xCA, 0x95, 0x41, 0xBB, 0x72, 0x61, 0x47, 0xE2, 0x79, 0xDA,
+	0x0E, 0x10, 0xAE, 0xDF, 0xE1, 0xDA, 0x00, 0x1F, 0x86, 0x09, 0xFE, 0x66, 0xBF, 0x4D, 0x3F, 0xE0,
+	0xD9, 0x81, 0x9F, 0x88, 0x7F, 0xB4, 0x77, 0xFD, 0x9B, 0x7E, 0xB5, 0xFF, 0x00, 0xA3, 0xA1, 0xAF,
+	0xCE, 0xFF, 0x00, 0x83, 0x93, 0xFC, 0x31, 0xB3, 0xF8, 0xBD, 0xE1, 0x5B, 0x8F, 0x8D, 0xB6, 0x3A,
+	0x8D, 0xC7, 0x83, 0x13, 0xC4, 0x36, 0x6D, 0xE2, 0xEB, 0x6D, 0x1A, 0x41, 0x1D, 0xE4, 0xBA, 0x67,
+	0x9E, 0xBF, 0x6A, 0x16, 0xE4, 0x90, 0x3E, 0xD1, 0xE4, 0x79, 0xBB, 0x3E, 0x75, 0x6D, 0xFB, 0x76,
+	0x63, 0x8A, 0x99, 0x7C, 0x37, 0x2E, 0x9E, 0x92, 0x7A, 0x9C, 0xDD, 0x37, 0x1B, 0x5F, 0x7C, 0xAD,
+	0x85, 0xEA, 0xBF, 0xBC, 0xF2, 0xC7, 0x43, 0x8C, 0x9F, 0x5C, 0x96, 0xC5, 0x7E, 0xC3, 0x3F, 0xC5,
+	0x0F, 0xF8, 0x34, 0x0A, 0x7B, 0x66, 0xB6, 0x87, 0xF6, 0x72, 0xF1, 0xD4, 0x6C, 0xD1, 0x94, 0x5B,
+	0xA8, 0xF5, 0x0F, 0x13, 0x79, 0x91, 0xFC, 0x8D, 0x96, 0x1B, 0xB5, 0x13, 0xDB, 0x77, 0x55, 0x2B,
+	0xFD, 0xEA, 0xFC, 0x8D, 0xF1, 0x73, 0xF8, 0x61, 0xFC, 0x5D, 0xAA, 0xBF, 0x82, 0x63, 0xBB, 0x4D,
+	0x15, 0xB5, 0x29, 0x8E, 0x90, 0xB7, 0xEC, 0x1A, 0x75, 0xB5, 0xDE, 0xFE, 0x50, 0x90, 0x8C, 0x82,
+	0xFB, 0x36, 0xEE, 0xC7, 0x19, 0xCD, 0x47, 0x5B, 0x0F, 0x9F, 0x9A, 0x2D, 0x6C, 0x7E, 0xDD, 0x7F,
+	0xC1, 0x43, 0x1F, 0xFE, 0x08, 0x89, 0xFF, 0x00, 0x04, 0x82, 0xF8, 0x9B, 0xE1, 0x5F, 0xD9, 0x3B,
+	0xE2, 0x2F, 0xFC, 0x13, 0x02, 0x3F, 0x1D, 0xDF, 0x5C, 0x78, 0x16, 0xCF, 0x59, 0xFF, 0x00, 0x84,
+	0x99, 0x75, 0x31, 0xE7, 0x4B, 0x1C, 0x97, 0x37, 0x56, 0xC5, 0xE5, 0xF3, 0x1F, 0x76, 0xF3, 0x2D,
+	0xA3, 0x48, 0xD8, 0x01, 0x32, 0xFC, 0x0C, 0x57, 0x86, 0xFF, 0x00, 0xC1, 0x4F, 0xFE, 0x08, 0x7F,
+	0xC1, 0x3D, 0x3E, 0x38, 0xFF, 0x00, 0xC1, 0x1E, 0x7C, 0x0F, 0xFF, 0x00, 0x05, 0x22, 0xFD, 0x90,
+	0x7F, 0x64, 0xC8, 0xBE, 0x12, 0xEA, 0x5A, 0x8F, 0xC4, 0x87, 0xD1, 0x64, 0xD2, 0xED, 0xEE, 0x8B,
+	0x99, 0x6D, 0x3F, 0xD3, 0x61, 0x92, 0x29, 0xF6, 0xB7, 0x94, 0xC0, 0xC9, 0x6B, 0x1C, 0xA1, 0xBA,
+	0xA7, 0xDD, 0xA8, 0x7F, 0xE0, 0xEF, 0x5F, 0xF9, 0x49, 0x5F, 0x81, 0x7F, 0xEC, 0x88, 0xE9, 0x7F,
+	0xFA, 0x77, 0xD6, 0xA8, 0xF8, 0xB2, 0x4F, 0xFC, 0x42, 0x67, 0xF0, 0xBC, 0x7F, 0xD5, 0x72, 0x9F,
+	0xFF, 0x00, 0x4A, 0xB5, 0x6A, 0xD2, 0x2F, 0xDD, 0x68, 0xCA, 0x31, 0xF7, 0x63, 0x21, 0xFF, 0x00,
+	0xF0, 0x4B, 0xCF, 0x81, 0x7F, 0xF0, 0x4F, 0x2F, 0x82, 0xFF, 0x00, 0xF0, 0x48, 0x5F, 0x1D, 0xFF,
+	0x00, 0xC1, 0x49, 0x3F, 0x6C, 0x6F, 0xD9, 0x51, 0x7E, 0x2E, 0x6A, 0x56, 0x1F, 0x11, 0x07, 0x87,
+	0xD3, 0x49, 0x9A, 0xE8, 0xAF, 0x93, 0x6E, 0xCD, 0x68, 0x91, 0x24, 0x48, 0xF2, 0xF9, 0x2A, 0x4C,
+	0x97, 0x45, 0x9D, 0x88, 0xDF, 0xB7, 0x19, 0xE6, 0xBD, 0xAF, 0xFE, 0x09, 0xFD, 0xE2, 0x1F, 0xF8,
+	0x21, 0xFF, 0x00, 0xFC, 0x15, 0xA3, 0xE2, 0xE6, 0xB5, 0xFB, 0x24, 0xF8, 0x07, 0xFE, 0x09, 0x68,
+	0x3C, 0x0F, 0x7B, 0x75, 0xE0, 0xFB, 0xCD, 0x50, 0x78, 0x99, 0xB5, 0x71, 0xE7, 0x5B, 0xAC, 0x4F,
+	0x14, 0x25, 0xA1, 0x68, 0xA4, 0xDE, 0xB2, 0xA9, 0x99, 0x64, 0x52, 0x7E, 0x56, 0x2A, 0x4E, 0x08,
+	0xE6, 0xBC, 0x47, 0xE1, 0x21, 0x3F, 0xF1, 0x09, 0xC7, 0xC4, 0xEF, 0xFB, 0x2D, 0xF6, 0xFF, 0x00,
+	0xFA, 0x57, 0xA5, 0x56, 0x17, 0xFC, 0x1A, 0x6A, 0x48, 0xFF, 0x00, 0x82, 0xA0, 0x6A, 0x44, 0x7F,
+	0xD1, 0x28, 0xD5, 0xBF, 0xF4, 0xAE, 0xCA, 0x97, 0x64, 0x3E, 0x5F, 0x76, 0x4C, 0xFC, 0xC8, 0x5D,
+	0xFB, 0x47, 0x98, 0x72, 0xDF, 0xC5, 0xF3, 0x67, 0x9F, 0xAE, 0x4F, 0xF3, 0x34, 0x56, 0x8F, 0x84,
+	0xE5, 0xF0, 0xC4, 0x5E, 0x2D, 0xD3, 0x5B, 0xC6, 0xD6, 0xF7, 0x12, 0x68, 0xAB, 0x7F, 0x01, 0xD6,
+	0x23, 0xB4, 0x58, 0x8C, 0xCF, 0x6B, 0xE6, 0x8F, 0x30, 0x47, 0xBB, 0xBE, 0xCC, 0xF5, 0xF9, 0xBF,
+	0xBB, 0x5F, 0xAE, 0x31, 0xFC, 0x4C, 0xFF, 0x00, 0x83, 0x42, 0x12, 0xC1, 0x6D, 0xA6, 0xFD, 0x9D,
+	0x7C, 0x7E, 0xD2, 0x6D, 0xF2, 0xDA, 0xEE, 0x6B, 0xCF, 0x13, 0x2C, 0x85, 0xC2, 0x60, 0x39, 0x07,
+	0x50, 0xC0, 0x73, 0xD4, 0x0D, 0x8A, 0xB9, 0x3C, 0xAA, 0xF4, 0x12, 0xA3, 0x73, 0x57, 0x53, 0x96,
+	0xCA, 0xC7, 0xE3, 0xE9, 0x6D, 0xBF, 0xBC, 0xCB, 0x7C, 0xAC, 0x0F, 0xC9, 0xD5, 0x5B, 0x18, 0xCA,
+	0xFF, 0x00, 0xB5, 0xB4, 0x57, 0xED, 0x7F, 0xED, 0x3B, 0x71, 0xFF, 0x00, 0x04, 0x5B, 0xFF, 0x00,
+	0x82, 0x52, 0xF8, 0x13, 0xE1, 0x07, 0xC2, 0x2F, 0x8B, 0xDF, 0xF0, 0x4D, 0x38, 0xFE, 0x22, 0xEB,
+	0x1E, 0x2A, 0xF8, 0x5B, 0xA6, 0xF8, 0x86, 0xF3, 0xC4, 0xD2, 0x6A, 0x41, 0x27, 0x95, 0xA4, 0xCA,
+	0xCA, 0xD3, 0xB4, 0xCF, 0x9F, 0x9A, 0x54, 0x66, 0x08, 0x83, 0x03, 0x38, 0x03, 0x15, 0xF8, 0xED,
+	0xF1, 0xAA, 0x7F, 0x85, 0x97, 0x3F, 0x19, 0x7C, 0x5B, 0x71, 0xF0, 0x2E, 0xD7, 0x51, 0x83, 0xC1,
+	0x32, 0x78, 0x93, 0x50, 0x6F, 0x06, 0xC3, 0xAC, 0x30, 0x37, 0x71, 0xE9, 0x46, 0xE4, 0x9B, 0x45,
+	0x9C, 0x82, 0xC0, 0xCA, 0x21, 0xF2, 0xC3, 0x60, 0x91, 0xBB, 0x3C, 0x9E, 0xB5, 0xFA, 0x25, 0xFF,
+	0x00, 0x07, 0x34, 0xFF, 0x00, 0xC9, 0x48, 0xFD, 0x9B, 0xFF, 0x00, 0xEC, 0xDC, 0x74, 0x9F, 0xFD,
+	0x1D, 0x3D, 0x38, 0xFC, 0x24, 0x54, 0xD6, 0x51, 0x47, 0x49, 0xFB, 0x7B, 0x7C, 0x39, 0xFF, 0x00,
+	0x82, 0x6A, 0x7E, 0xD3, 0x9F, 0xF0, 0x47, 0x7B, 0x8F, 0xF8, 0x28, 0x17, 0xEC, 0x81, 0xFB, 0x1C,
+	0xAF, 0xC2, 0x5D, 0x67, 0x45, 0xF8, 0xA5, 0x6F, 0xE1, 0xC5, 0x10, 0xDF, 0x3E, 0xE9, 0x23, 0xC4,
+	0x4D, 0x31, 0x9E, 0x25, 0x97, 0x64, 0xA0, 0xF9, 0xA8, 0x40, 0xC7, 0x98, 0xBE, 0x5F, 0x1F, 0x28,
+	0x7A, 0xCB, 0xFF, 0x00, 0x82, 0x35, 0xFE, 0xCF, 0x7F, 0xB0, 0x57, 0x87, 0x3F, 0xE0, 0x9A, 0xFF,
+	0x00, 0x1C, 0xBF, 0xE0, 0xA1, 0x9F, 0xB6, 0x37, 0xEC, 0xD0, 0x9F, 0x13, 0x5B, 0xC0, 0x3E, 0x25,
+	0xB5, 0xD2, 0xA1, 0xD0, 0xEF, 0x2F, 0x54, 0xC5, 0x1D, 0x9B, 0x8B, 0x32, 0xC6, 0x34, 0xF3, 0x76,
+	0x89, 0x37, 0x5D, 0xE5, 0xDA, 0x4F, 0xE1, 0x88, 0x62, 0xB3, 0x7C, 0x28, 0x4F, 0xFC, 0x42, 0xA7,
+	0xE2, 0x91, 0xFF, 0x00, 0x57, 0x19, 0x1F, 0xFE, 0x8B, 0xB3, 0xAD, 0xEF, 0xD8, 0x03, 0xFE, 0x55,
+	0x9C, 0xFD, 0xAF, 0xBF, 0xEC, 0x7A, 0xB3, 0xFE, 0x5A, 0x2D, 0x5F, 0xDA, 0x44, 0x7D, 0x97, 0xEA,
+	0x7B, 0x67, 0xFC, 0x13, 0xEB, 0xE2, 0x3F, 0xFC, 0x10, 0xD3, 0xFE, 0x0A, 0x83, 0xFB, 0x41, 0x2F,
+	0xEC, 0xA3, 0xE1, 0x5F, 0xF8, 0x24, 0xEC, 0x3E, 0x13, 0xBC, 0xD5, 0xB4, 0x3B, 0xEB, 0xC9, 0x35,
+	0x6B, 0xAD, 0x4B, 0xF7, 0x91, 0x24, 0x31, 0xAE, 0xF0, 0xAD, 0x0C, 0xBE, 0x66, 0xE3, 0xB9, 0x7E,
+	0x75, 0xE0, 0x15, 0xC3, 0x57, 0xE2, 0xFF, 0x00, 0xC5, 0xAF, 0x07, 0x5A, 0xFC, 0x3B, 0xF8, 0xA9,
+	0xE2, 0x6F, 0x87, 0xF6, 0x37, 0xB2, 0x5C, 0xC3, 0xA1, 0x78, 0x82, 0xF7, 0x4F, 0x86, 0xE2, 0x6C,
+	0x6E, 0x95, 0x61, 0x9D, 0xE3, 0x0E, 0x70, 0x48, 0xC9, 0x0B, 0x93, 0x82, 0x47, 0x35, 0xF7, 0xE7,
+	0xFC, 0x1A, 0xC3, 0xFF, 0x00, 0x29, 0x65, 0xD2, 0x3F, 0xEC, 0x45, 0xD6, 0xBF, 0xF4, 0x54, 0x55,
+	0xF0, 0xDF, 0xED, 0x37, 0xFF, 0x00, 0x27, 0x25, 0xF1, 0x0B, 0xFE, 0xC7, 0x8D, 0x5B, 0xFF, 0x00,
+	0x4B, 0x25, 0xA9, 0x96, 0xA6, 0x91, 0x56, 0xA9, 0x6B, 0x9F, 0x71, 0x7F, 0xC1, 0xAC, 0x3F, 0xF2,
+	0x96, 0x3D, 0x27, 0xFE, 0xC4, 0x5D, 0x6B, 0xFF, 0x00, 0x45, 0xAD, 0x79, 0x5F, 0xFC, 0x1C, 0x0F,
+	0xFF, 0x00, 0x29, 0x81, 0xF8, 0xE1, 0xFF, 0x00, 0x61, 0xCB, 0x3F, 0xFD, 0x35, 0xD9, 0x57, 0xAA,
+	0xFF, 0x00, 0xC1, 0xAC, 0x1F, 0xF2, 0x96, 0x3D, 0x27, 0xFE, 0xC4, 0x5D, 0x6B, 0xFF, 0x00, 0x45,
+	0xAD, 0x7E, 0x9A, 0xFE, 0xDC, 0x1F, 0x19, 0xFF, 0x00, 0xE0, 0xDA, 0xFF, 0x00, 0x0E, 0x7E, 0xD6,
+	0xDE, 0x31, 0xD0, 0xBF, 0x6D, 0xBD, 0x1B, 0xC2, 0x72, 0x7C, 0x54, 0x86, 0xFA, 0x0F, 0xF8, 0x4B,
+	0x8E, 0xA5, 0xE0, 0x3D, 0x7A, 0xE6, 0x63, 0x2F, 0xD9, 0xA1, 0xF2, 0x4B, 0xCD, 0x6B, 0x6A, 0xD0,
+	0xB0, 0xF2, 0x7C, 0xAE, 0x84, 0x93, 0xEA, 0x7A, 0xD1, 0x6B, 0xC4, 0xCE, 0x52, 0xE5, 0xAE, 0x7F,
+	0x36, 0x32, 0x7F, 0xAC, 0x6F, 0xF7, 0xA9, 0xB5, 0xFB, 0xF8, 0x9F, 0xB4, 0x37, 0xFC, 0x19, 0xE8,
+	0xA8, 0xAB, 0xFD, 0x81, 0xE0, 0x6E, 0x07, 0x6F, 0x85, 0xFE, 0x28, 0xFF, 0x00, 0xE4, 0x3A, 0x5F,
+	0xF8, 0x68, 0x8F, 0xF8, 0x33, 0xD3, 0xFE, 0x80, 0x3E, 0x07, 0xFF, 0x00, 0xC3, 0x5F, 0xE2, 0x8F,
+	0xFE, 0x43, 0xA3, 0xD9, 0x97, 0xED, 0x9F, 0xF2, 0xB3, 0xF0, 0x0A, 0xBE, 0x9E, 0xFF, 0x00, 0x82,
+	0x48, 0xDF, 0x43, 0x6B, 0xFB, 0x5A, 0x7D, 0x92, 0x4F, 0xBD, 0x75, 0xE1, 0x9B, 0xC8, 0x57, 0xF1,
+	0x68, 0x9F, 0xFF, 0x00, 0x64, 0xAF, 0xD5, 0xE3, 0xFB, 0x43, 0xFF, 0x00, 0xC1, 0x9E, 0xBD, 0xB4,
+	0x1F, 0x03, 0xFF, 0x00, 0xE1, 0xAF, 0xF1, 0x47, 0xFF, 0x00, 0x21, 0xD6, 0x67, 0x88, 0xFE, 0x2D,
+	0xFF, 0x00, 0xC1, 0xBF, 0x5E, 0x37, 0x36, 0xBA, 0x27, 0xFC, 0x13, 0x6B, 0x48, 0xF0, 0xCC, 0x3F,
+	0x11, 0xDA, 0xE0, 0x12, 0xDA, 0x3F, 0x82, 0x75, 0x8D, 0x3A, 0x6F, 0xEC, 0xE0, 0x8F, 0xE7, 0xE6,
+	0x5B, 0xDB, 0x54, 0x8D, 0x87, 0xFA, 0xBE, 0x01, 0xDD, 0x44, 0x23, 0x69, 0x2F, 0x22, 0x27, 0x5B,
+	0x9A, 0x2D, 0x58, 0xA5, 0xBC, 0xBF, 0xCE, 0x7F, 0x8B, 0x9A, 0xFD, 0x34, 0xFF, 0x00, 0x82, 0x6A,
+	0xFF, 0x00, 0xC9, 0xA3, 0xE8, 0x7F, 0xF5, 0xFD, 0x7F, 0xFF, 0x00, 0xA5, 0x2D, 0x5F, 0x99, 0x61,
+	0xB7, 0x8D, 0xDE, 0xBC, 0xFD, 0xD2, 0x3F, 0x43, 0xC8, 0xFC, 0x79, 0xAF, 0xD3, 0x4F, 0xF8, 0x26,
+	0xAF, 0xFC, 0x9A, 0x3E, 0x87, 0xFF, 0x00, 0x5F, 0xD7, 0xFF, 0x00, 0xFA, 0x52, 0xD5, 0xD0, 0x70,
+	0x9E, 0x4B, 0xFB, 0x66, 0xFF, 0x00, 0xC9, 0x7C, 0xD4, 0x3F, 0xEB, 0xD6, 0xD3, 0xFF, 0x00, 0x45,
+	0xD7, 0x94, 0x8E, 0x95, 0xAF, 0xFF, 0x00, 0x05, 0x05, 0xF8, 0xCD, 0x77, 0xE0, 0xAF, 0xDA, 0x67,
+	0x59, 0xD0, 0x60, 0xD0, 0xA3, 0xB8, 0xF2, 0xEC, 0xED, 0x5F, 0xCC, 0x37, 0x18, 0xC6, 0x61, 0x5E,
+	0xD5, 0xE2, 0xAF, 0xFB, 0x46, 0xDF, 0xEF, 0x6D, 0xDE, 0x15, 0x8C, 0xFC, 0xDD, 0x7E, 0xD5, 0xD6,
+	0xBF, 0x81, 0x78, 0xEF, 0xC1, 0x3F, 0x10, 0xB3, 0xFE, 0x30, 0xC7, 0x66, 0x18, 0x2C, 0x32, 0x95,
+	0x2A, 0x95, 0x1C, 0xA2, 0xF9, 0xE0, 0xAE, 0x9D, 0xBB, 0xB5, 0xD8, 0xFD, 0xBB, 0x23, 0xE2, 0x9C,
+	0x97, 0x0B, 0x94, 0x50, 0xA1, 0x52, 0xA5, 0xA5, 0x18, 0xAB, 0xE8, 0xF4, 0xB7, 0xC8, 0xF5, 0x3A,
+	0x2B, 0xCA, 0xFF, 0x00, 0xE1, 0xA3, 0xAF, 0xBF, 0xE8, 0x53, 0x8F, 0xFF, 0x00, 0x02, 0xA8, 0xFF,
+	0x00, 0x86, 0x8E, 0xBE, 0xFF, 0x00, 0xA1, 0x4E, 0x3F, 0xFC, 0x0A, 0xAF, 0x92, 0xFF, 0x00, 0x89,
+	0x7B, 0xF1, 0x43, 0xFE, 0x80, 0xD7, 0xFE, 0x0C, 0xA7, 0xFF, 0x00, 0xC9, 0x1E, 0xB7, 0xFA, 0xE1,
+	0x90, 0xFF, 0x00, 0xCF, 0xDF, 0xC2, 0x5F, 0xE4, 0x7A, 0xA5, 0x7E, 0x82, 0x7C, 0x12, 0xFF, 0x00,
+	0x92, 0x37, 0xE1, 0x3F, 0xFB, 0x16, 0xEC, 0xBF, 0xF4, 0x42, 0x57, 0xE5, 0x3F, 0xFC, 0x34, 0x75,
+	0xF7, 0xFD, 0x0A, 0x71, 0xFF, 0x00, 0xE0, 0x55, 0x7E, 0xA7, 0x7E, 0xCE, 0xFA, 0x8B, 0x6A, 0xFF,
+	0x00, 0x00, 0x7C, 0x0F, 0xAB, 0x3C, 0x5E, 0x59, 0xBA, 0xF0, 0x86, 0x9B, 0x31, 0x8F, 0x39, 0xDB,
+	0xBE, 0xD6, 0x36, 0xC7, 0xE1, 0x9A, 0xFE, 0x82, 0xFA, 0x3F, 0xF8, 0x6B, 0xC5, 0xDC, 0x0B, 0x9B,
+	0xE3, 0x6B, 0xE7, 0x14, 0x15, 0x38, 0xD4, 0xA7, 0x18, 0xC5, 0xF3, 0x46, 0x57, 0x6A, 0x57, 0x7F,
+	0x0B, 0x7D, 0x0F, 0x83, 0xE3, 0xAC, 0xEB, 0x2F, 0xCD, 0x70, 0xB4, 0x61, 0x87, 0x9D, 0xDC, 0x64,
+	0xEF, 0xA3, 0x5D, 0x17, 0x74, 0x8F, 0xCD, 0x3F, 0xDB, 0x4F, 0xFE, 0x4E, 0xBB, 0xC6, 0xDF, 0xF6,
+	0x1C, 0x3F, 0xFA, 0x0A, 0xD7, 0x96, 0x27, 0xDC, 0x1F, 0x4A, 0xF5, 0x3F, 0xDB, 0x4F, 0xFE, 0x4E,
+	0xBB, 0xC6, 0xDF, 0xF6, 0x1C, 0x3F, 0xFA, 0x0A, 0xD7, 0x96, 0x27, 0xDC, 0x1F, 0x4A, 0xFE, 0xA5,
+	0x3F, 0x37, 0x16, 0x8A, 0x28, 0xA0, 0x02, 0xBE, 0xF4, 0xFF, 0x00, 0x82, 0x42, 0xFF, 0x00, 0xC9,
+	0x35, 0xF1, 0x87, 0xFD, 0x87, 0x20, 0xFF, 0x00, 0xD1, 0x35, 0xF0, 0x5D, 0x7D, 0xE9, 0xFF, 0x00,
+	0x04, 0x85, 0xFF, 0x00, 0x92, 0x6B, 0xE3, 0x0F, 0xFB, 0x0E, 0x41, 0xFF, 0x00, 0xA2, 0x68, 0x03,
+	0xC7, 0xBF, 0xE0, 0xAA, 0x3F, 0xF2, 0x73, 0x36, 0xFF, 0x00, 0xF6, 0x2C, 0x5A, 0xFF, 0x00, 0xE8,
+	0x72, 0xD7, 0xCD, 0x95, 0xF4, 0x9F, 0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B,
+	0x5F, 0xFD, 0x0E, 0x5A, 0xF9, 0xB2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0E, 0xDF, 0x85, 0x7D, 0xD1,
+	0xFF, 0x00, 0x04, 0x80, 0xFF, 0x00, 0x91, 0x73, 0xC7, 0xDF, 0xF6, 0x10, 0xB0, 0xFF, 0x00, 0xD1,
+	0x73, 0x57, 0xC2, 0xFD, 0xBF, 0x0A, 0xFB, 0xA3, 0xFE, 0x09, 0x01, 0xFF, 0x00, 0x22, 0xE7, 0x8F,
+	0xBF, 0xEC, 0x21, 0x61, 0xFF, 0x00, 0xA2, 0xE6, 0xA0, 0x0F, 0x2A, 0xFF, 0x00, 0x82, 0xA8, 0xFF,
+	0x00, 0xC9, 0xCC, 0xDB, 0xFF, 0x00, 0xD8, 0xB1, 0x6B, 0xFF, 0x00, 0xA1, 0xCB, 0x5F, 0x36, 0x57,
+	0xD2, 0x7F, 0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B, 0x7F, 0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B,
+	0xE6, 0xCA, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x3B, 0x7E, 0x15, 0xF7, 0x37, 0xFC, 0x12, 0x0F, 0xFE,
+	0x45, 0xDF, 0x1E, 0x7F, 0xD8, 0x42, 0xC7, 0xFF, 0x00, 0x45, 0xCD, 0x5F, 0x0C, 0xF6, 0xFC, 0x2B,
+	0xEE, 0x4F, 0xF8, 0x24, 0x44, 0x82, 0x2F, 0x0C, 0xF8, 0xFA, 0x42, 0x3A, 0x6A, 0x16, 0x3F, 0xFA,
+	0x2E, 0x6A, 0x37, 0x03, 0xEC, 0xC8, 0x3F, 0x8B, 0xFD, 0xE1, 0xFF, 0x00, 0xA0, 0x8A, 0x92, 0xA3,
+	0xB6, 0x6D, 0xF1, 0x6F, 0xC7, 0x5E, 0x6A, 0x4A, 0x00, 0x28, 0x3D, 0x28, 0xA4, 0x73, 0x84, 0x27,
+	0xDA, 0x80, 0x3E, 0x15, 0xFF, 0x00, 0x82, 0xBE, 0xFF, 0x00, 0xC8, 0xC9, 0xE0, 0x7F, 0xFA, 0xF2,
+	0xBE, 0xFF, 0x00, 0xD1, 0x91, 0xD7, 0xC6, 0xD5, 0xFA, 0x35, 0xFB, 0x75, 0xFE, 0xC9, 0x7F, 0x11,
+	0xBF, 0x6A, 0x3F, 0x11, 0x78, 0x7A, 0x6F, 0x87, 0xFA, 0xC6, 0x87, 0x66, 0x34, 0x5B, 0x59, 0x96,
+	0xE8, 0xEB, 0x17, 0x13, 0x28, 0x3E, 0x69, 0x52, 0x31, 0xE5, 0xC4, 0xFF, 0x00, 0xDC, 0xAF, 0x07,
+	0xFF, 0x00, 0x87, 0x4C, 0x7E, 0xD1, 0x3F, 0xF4, 0x3A, 0x78, 0x2B, 0xFF, 0x00, 0x03, 0x6F, 0x7F,
+	0xF9, 0x1E, 0x80, 0x3E, 0x5D, 0xA2, 0xBE, 0xA2, 0xFF, 0x00, 0x87, 0x4C, 0x7E, 0xD1, 0x3F, 0xF4,
+	0x3A, 0x78, 0x2B, 0xFF, 0x00, 0x03, 0x6F, 0x7F, 0xF9, 0x1E, 0x8F, 0xF8, 0x74, 0xC7, 0xED, 0x13,
+	0xFF, 0x00, 0x43, 0xA7, 0x82, 0xBF, 0xF0, 0x36, 0xF7, 0xFF, 0x00, 0x91, 0xE8, 0x03, 0xE5, 0xD1,
+	0xD6, 0xBE, 0xAF, 0xFF, 0x00, 0x82, 0x49, 0x7F, 0xC9, 0x68, 0xF1, 0x37, 0xFD, 0x8A, 0x8B, 0xFF,
+	0x00, 0xA5, 0x31, 0x55, 0x23, 0xFF, 0x00, 0x04, 0x99, 0xFD, 0xA2, 0x80, 0xC8, 0xF1, 0xA7, 0x82,
+	0xFF, 0x00, 0xE0, 0x37, 0xD7, 0xA0, 0xFF, 0x00, 0xE9, 0x31, 0xFE, 0x46, 0xBD, 0xA3, 0xF6, 0x1A,
+	0xFD, 0x8B, 0xBE, 0x29, 0xFE, 0xCC, 0xDF, 0x10, 0x35, 0x8F, 0x16, 0xF8, 0xF7, 0x5B, 0xF0, 0xFD,
+	0xE5, 0xBD, 0xFE, 0x93, 0xF6, 0x44, 0x1A, 0x3C, 0xD3, 0x48, 0xE0, 0xF9, 0x91, 0xC9, 0xF3, 0x6F,
+	0x82, 0x3F, 0x4A, 0x00, 0x6F, 0xFC, 0x15, 0x90, 0x8F, 0xF8, 0x67, 0x8D, 0x0C, 0x67, 0xFE, 0x67,
+	0x28, 0x7F, 0xF4, 0x96, 0xE6, 0xBF, 0x3D, 0xEB, 0xF5, 0x0B, 0xF6, 0xDF, 0xFD, 0x9E, 0xBC, 0x63,
+	0xFB, 0x4A, 0x7C, 0x31, 0xD3, 0x7C, 0x0B, 0xE0, 0x4D, 0x4B, 0x4C, 0xB5, 0xBE, 0xB4, 0xD7, 0xE3,
+	0xBD, 0x77, 0xD5, 0xA6, 0x75, 0x87, 0xCB, 0x58, 0xA6, 0x8C, 0xFD, 0xC4, 0x73, 0x9C, 0xC9, 0xE9,
+	0x5F, 0x2F, 0xFF, 0x00, 0xC3, 0xA6, 0x3F, 0x68, 0x9F, 0xFA, 0x1D, 0x3C, 0x15, 0xFF, 0x00, 0x81,
+	0xB7, 0xBF, 0xFC, 0x8F, 0x53, 0x1E, 0xA1, 0xCC, 0xA5, 0x14, 0xD1, 0xF2, 0xED, 0x15, 0xF5, 0x17,
+	0xFC, 0x3A, 0x63, 0xF6, 0x89, 0xFF, 0x00, 0xA1, 0xD3, 0xC1, 0x5F, 0xF8, 0x1B, 0x7B, 0xFF, 0x00,
+	0xC8, 0xF4, 0x7F, 0xC3, 0xA6, 0x3F, 0x68, 0x9F, 0xFA, 0x1D, 0x3C, 0x15, 0xFF, 0x00, 0x81, 0xB7,
+	0xBF, 0xFC, 0x8F, 0x54, 0x07, 0xCB, 0xB5, 0xEF, 0x5F, 0xF0, 0x4D, 0x8F, 0xF9, 0x3B, 0x9D, 0x07,
+	0xFE, 0xC1, 0xFA, 0x87, 0xFE, 0x93, 0xBD, 0x75, 0x1F, 0xF0, 0xE9, 0x8F, 0xDA, 0x27, 0xFE, 0x87,
+	0x4F, 0x05, 0x7F, 0xE0, 0x6D, 0xEF, 0xFF, 0x00, 0x23, 0xD7, 0xA3, 0x7E, 0xC8, 0xDF, 0xB0, 0x0F,
+	0xC6, 0x6F, 0x80, 0x9F, 0x1C, 0xF4, 0xFF, 0x00, 0x89, 0xBE, 0x30, 0xF1, 0x17, 0x86, 0x6E, 0xAC,
+	0xAC, 0xED, 0x6E, 0x23, 0x78, 0xF4, 0xDB, 0xAB, 0x89, 0x27, 0xFD, 0xE4, 0x4E, 0x9F, 0xC7, 0x6F,
+	0x1D, 0x00, 0x7A, 0xAF, 0xFC, 0x14, 0x4C, 0x8F, 0xF8, 0x63, 0xDF, 0x16, 0xF3, 0xFC, 0x76, 0x3F,
+	0xFA, 0x5B, 0x05, 0x7E, 0x61, 0x57, 0xEB, 0x17, 0xED, 0x5F, 0xF0, 0xA3, 0x5E, 0xF8, 0xE5, 0xF0,
+	0x23, 0x5C, 0xF8, 0x5F, 0xE1, 0x3B, 0xAB, 0x3B, 0x7D, 0x47, 0x54, 0x36, 0xE6, 0xD6, 0x4B, 0xE9,
+	0x19, 0x21, 0x1E, 0x5D, 0xC4, 0x52, 0x9D, 0xDB, 0x55, 0x8F, 0x44, 0xEC, 0x0D, 0x7C, 0x7F, 0xFF,
+	0x00, 0x0E, 0x98, 0xFD, 0xA2, 0xBB, 0xF8, 0xD7, 0xC1, 0x3F, 0xF0, 0x1B, 0xDB, 0xDC, 0x7F, 0xE9,
+	0x35, 0x4C, 0x77, 0x7F, 0xD7, 0x44, 0x1C, 0xCA, 0x51, 0x4D, 0x1F, 0x2E, 0xD1, 0x5F, 0x51, 0x7F,
+	0xC3, 0xA6, 0x3F, 0x68, 0x9F, 0xFA, 0x1D, 0x3C, 0x15, 0xFF, 0x00, 0x81, 0xB7, 0xBF, 0xFC, 0x8F,
+	0x47, 0xFC, 0x3A, 0x63, 0xF6, 0x89, 0xFF, 0x00, 0xA1, 0xD3, 0xC1, 0x5F, 0xF8, 0x1B, 0x7B, 0xFF,
+	0x00, 0xC8, 0xF5, 0x40, 0x7C, 0xBB, 0x5E, 0x89, 0xFB, 0x25, 0x7F, 0xC9, 0xCE, 0x78, 0x07, 0xFE,
+	0xC6, 0xAB, 0x4F, 0xFD, 0x08, 0x57, 0xAF, 0x7F, 0xC3, 0xA6, 0x3F, 0x68, 0x9F, 0xFA, 0x1D, 0x3C,
+	0x15, 0xFF, 0x00, 0x81, 0xB7, 0xBF, 0xFC, 0x8F, 0x5D, 0x37, 0xC1, 0x0F, 0xF8, 0x26, 0xA7, 0xC7,
+	0x8F, 0x86, 0x7F, 0x19, 0x3C, 0x37, 0xF1, 0x03, 0x5C, 0xF1, 0x4F, 0x84, 0xEE, 0x2D, 0x34, 0x5D,
+	0x5A, 0x1B, 0xB9, 0xA2, 0xB5, 0xBC, 0xB9, 0x79, 0x88, 0x8D, 0xD4, 0xFC, 0xA1, 0xED, 0x97, 0xD7,
+	0xD4, 0xFD, 0x68, 0x03, 0xEA, 0x6F, 0xDA, 0x8C, 0x8F, 0xF8, 0x66, 0xAF, 0x88, 0x79, 0x3F, 0xF3,
+	0x25, 0x6A, 0x7F, 0xFA, 0x4B, 0x25, 0x7E, 0x36, 0xD7, 0xED, 0x17, 0xC7, 0x4F, 0x0B, 0xEA, 0x7E,
+	0x3A, 0xF8, 0x31, 0xE2, 0xCF, 0x05, 0x78, 0x7D, 0xD2, 0x3B, 0xED, 0x63, 0xC3, 0x77, 0xB6, 0x56,
+	0x0D, 0x33, 0x6D, 0x5F, 0x3A, 0x58, 0x1E, 0x34, 0xDD, 0xFF, 0x00, 0x02, 0x35, 0xF9, 0xEF, 0xFF,
+	0x00, 0x0E, 0x96, 0xFD, 0xA9, 0xB1, 0xFB, 0xBB, 0x8F, 0x0D, 0x15, 0xFE, 0x1F, 0xF8, 0x9A, 0xC8,
+	0x32, 0x3E, 0x9E, 0x59, 0xFE, 0x75, 0xF1, 0x5C, 0x51, 0x80, 0xC6, 0x63, 0x31, 0x14, 0xE5, 0x46,
+	0x0E, 0x49, 0x26, 0x9D, 0x8F, 0xDD, 0xFC, 0x1F, 0xE2, 0x4C, 0x93, 0x23, 0xCB, 0xF1, 0x4B, 0x1D,
+	0x5E, 0x34, 0xDC, 0xA7, 0x1B, 0x5D, 0xA5, 0x74, 0x93, 0xD7, 0xEF, 0x3E, 0x65, 0xA2, 0xBE, 0x9B,
+	0x1F, 0xF0, 0x49, 0x5F, 0xDA, 0xA4, 0x8C, 0xF9, 0xDE, 0x1B, 0xFF, 0x00, 0xC1, 0xB4, 0xBF, 0xFC,
+	0x6A, 0x97, 0xFE, 0x1D, 0x29, 0xFB, 0x54, 0xFF, 0x00, 0xCF, 0x6F, 0x0D, 0xFF, 0x00, 0xE0, 0xDA,
+	0x5F, 0xFE, 0x35, 0x5F, 0x2B, 0xFD, 0x8D, 0x9A, 0xFF, 0x00, 0xCF, 0xA7, 0xF7, 0x1F, 0xB1, 0xFF,
+	0x00, 0xAF, 0xDC, 0x1D, 0xFF, 0x00, 0x41, 0xB0, 0xFB, 0xCF, 0x98, 0xEB, 0xE8, 0x6F, 0xF8, 0x25,
+	0xF6, 0x3F, 0xE1, 0xAE, 0x74, 0x9C, 0x8F, 0xF9, 0x85, 0x5F, 0x7F, 0xE8, 0xA3, 0x5A, 0x83, 0xFE,
+	0x09, 0x2D, 0xFB, 0x54, 0x9F, 0xF9, 0x6B, 0xE1, 0xBF, 0xC7, 0x56, 0x93, 0xFF, 0x00, 0x8D, 0x57,
+	0xAD, 0x7E, 0xC5, 0x3F, 0xB0, 0x27, 0xC7, 0x4F, 0xD9, 0xF7, 0xE3, 0xC5, 0x8F, 0xC4, 0xBF, 0x1E,
+	0x5D, 0x68, 0x6D, 0xA7, 0xDB, 0x58, 0xDC, 0xC5, 0x22, 0xD9, 0xEA, 0x12, 0x49, 0x26, 0xF9, 0x14,
+	0x28, 0xC0, 0x31, 0x8F, 0x4A, 0xEF, 0xCA, 0xF2, 0x8C, 0xCA, 0x9E, 0x63, 0x4A, 0x73, 0xA4, 0xE3,
+	0x66, 0x9B, 0x3E, 0x6F, 0x8B, 0xB8, 0xD3, 0x85, 0x71, 0xDC, 0x33, 0x8B, 0xA1, 0x47, 0x15, 0x09,
+	0x4E, 0x50, 0x69, 0x24, 0xD5, 0xDB, 0xE8, 0x8F, 0x64, 0xFF, 0x00, 0x82, 0x94, 0x7F, 0xC9, 0xA4,
+	0x6B, 0x9F, 0xF5, 0xF9, 0x63, 0xFF, 0x00, 0xA3, 0xD6, 0xBF, 0x32, 0xEB, 0xF5, 0x7B, 0xF6, 0xB7,
+	0xF8, 0x39, 0xE2, 0x8F, 0x8F, 0x3F, 0x02, 0x75, 0x0F, 0x86, 0x7E, 0x10, 0xBB, 0xB3, 0xB7, 0xBF,
+	0xBA, 0xB9, 0xB7, 0x92, 0x29, 0x75, 0x09, 0x19, 0x63, 0x02, 0x39, 0x55, 0xCE, 0xE2, 0x8A, 0xE7,
+	0xF8, 0x7D, 0x2B, 0xE4, 0x35, 0xFF, 0x00, 0x82, 0x4C, 0x7E, 0xD1, 0x3B, 0x78, 0xF1, 0xAF, 0x82,
+	0x7F, 0xE0, 0x37, 0xB7, 0x98, 0xFF, 0x00, 0xD2, 0x6A, 0xFD, 0x40, 0xFE, 0x49, 0x3F, 0x18, 0xFF,
+	0x00, 0xE0, 0xB5, 0x56, 0xB2, 0xFF, 0x00, 0x6E, 0xFC, 0x3F, 0xBE, 0x96, 0x2F, 0xDD, 0x49, 0x63,
+	0xA9, 0xA2, 0xFD, 0x43, 0x5B, 0x57, 0xC3, 0xA4, 0xB1, 0x39, 0x61, 0xCF, 0x7A, 0xFD, 0x4E, 0xFF,
+	0x00, 0x83, 0x8E, 0xBF, 0x62, 0xEF, 0x89, 0xDF, 0xB3, 0x4F, 0x85, 0xFE, 0x13, 0x78, 0x8B, 0xC7,
+	0x3A, 0xDE, 0x89, 0x78, 0xBA, 0x95, 0xFE, 0xB1, 0x67, 0x6B, 0xFD, 0x95, 0x71, 0x3B, 0x28, 0xF9,
+	0x6C, 0x89, 0xF3, 0x7C, 0xD8, 0x90, 0x7F, 0xBB, 0xCD, 0x7E, 0x58, 0x87, 0x59, 0x06, 0xF4, 0xDD,
+	0xB5, 0xB9, 0x1B, 0xFE, 0xF7, 0xE3, 0xEF, 0x5C, 0xB5, 0x22, 0xB9, 0xAE, 0x7A, 0x58, 0x7F, 0xE0,
+	0xA0, 0xA2, 0x8A, 0x2A, 0x74, 0x37, 0xB9, 0xEE, 0x1F, 0xF0, 0x4C, 0xAC, 0xFF, 0x00, 0xC3, 0xC9,
+	0xBF, 0x67, 0xBF, 0xFB, 0x2E, 0x5E, 0x11, 0xFF, 0x00, 0xD3, 0xC5, 0xA5, 0x7E, 0x8D, 0xFF, 0x00,
+	0xC1, 0xE2, 0xBF, 0xF2, 0x71, 0xFF, 0x00, 0x06, 0xFF, 0x00, 0xEC, 0x43, 0xD4, 0x3F, 0xF4, 0xB5,
+	0x6B, 0xF3, 0x93, 0xFE, 0x09, 0x95, 0xFF, 0x00, 0x29, 0x26, 0xFD, 0x9E, 0xFF, 0x00, 0xEC, 0xB9,
+	0x78, 0x47, 0xFF, 0x00, 0x4F, 0x16, 0x95, 0xFA, 0x39, 0xFF, 0x00, 0x07, 0x8B, 0xFF, 0x00, 0xC9,
+	0xC7, 0xFC, 0x1B, 0xFF, 0x00, 0xB1, 0x0B, 0x50, 0xFF, 0x00, 0xD2, 0xD5, 0xAD, 0x21, 0xF0, 0x1C,
+	0xD2, 0xB2, 0xC4, 0x23, 0xF1, 0xCC, 0xF5, 0xA2, 0x83, 0xD6, 0x8A, 0xCC, 0xE8, 0x0A, 0x28, 0xA2,
+	0x80, 0x3E, 0xC6, 0xFF, 0x00, 0x82, 0x14, 0x7E, 0xD8, 0x7F, 0x03, 0xBF, 0x61, 0x9F, 0xF8, 0x28,
+	0x56, 0x85, 0xF1, 0xBB, 0xF6, 0x8D, 0xD6, 0xEF, 0x74, 0xAF, 0x0A, 0x1D, 0x0B, 0x50, 0xD3, 0x2F,
+	0xB5, 0x6B, 0x2D, 0x3A, 0x4B, 0xA1, 0x65, 0x24, 0xF1, 0x8F, 0x29, 0xDE, 0x38, 0x55, 0xA6, 0x29,
+	0x9D, 0xC3, 0xF7, 0x6A, 0xEF, 0xBA, 0x5F, 0xBB, 0x8A, 0xFA, 0x1A, 0x2F, 0xD9, 0xBB, 0xFE, 0x0D,
+	0x95, 0x5F, 0x1E, 0xFF, 0x00, 0xC2, 0xC4, 0x93, 0xFE, 0x0A, 0xB5, 0xF1, 0x49, 0xAE, 0xBF, 0xB6,
+	0x05, 0xFA, 0xC2, 0x7E, 0x1F, 0xEA, 0x41, 0x4B, 0x79, 0xC2, 0x52, 0x98, 0x1A, 0x36, 0xE0, 0xA5,
+	0xC7, 0x38, 0xC7, 0xE1, 0x5F, 0x96, 0x74, 0x55, 0x29, 0x5A, 0x36, 0x33, 0x94, 0x39, 0x9D, 0xEF,
+	0xB9, 0xF6, 0x0F, 0xFC, 0x17, 0x4F, 0xF6, 0xC6, 0xF8, 0x27, 0xFB, 0x75, 0xFF, 0x00, 0xC1, 0x42,
+	0x7C, 0x41, 0xF1, 0xB7, 0xE0, 0x0E, 0xB9, 0x79, 0xA8, 0x78, 0x5B, 0xFB, 0x17, 0x4E, 0xD2, 0x2C,
+	0xF5, 0x8B, 0x8D, 0x36, 0x4B, 0x56, 0xBB, 0x30, 0xC2, 0xDB, 0xAE, 0x16, 0x39, 0x55, 0x1F, 0x6E,
+	0xE9, 0x0E, 0xDD, 0xEA, 0xAD, 0x88, 0xC6, 0x55, 0x4E, 0x40, 0xFB, 0x63, 0xF6, 0xD1, 0xF8, 0xD1,
+	0xFF, 0x00, 0x06, 0xFA, 0x7F, 0xC1, 0x50, 0xFC, 0x47, 0xE0, 0x5F, 0xDA, 0x17, 0xF6, 0x89, 0xFD,
+	0xBD, 0x7C, 0x7D, 0xF0, 0xFF, 0x00, 0xC4, 0xBA, 0x4F, 0xC3, 0x5D, 0x3B, 0x40, 0xBA, 0xF0, 0xDE,
+	0x8F, 0xE0, 0x5D, 0x4A, 0x41, 0x6A, 0xB0, 0x49, 0x71, 0x3B, 0x47, 0x33, 0x9D, 0x2A, 0x74, 0x66,
+	0x49, 0xAE, 0x65, 0x5D, 0xCA, 0xFB, 0x4E, 0xDC, 0x82, 0x46, 0x0D, 0x7E, 0x33, 0x51, 0x42, 0x7A,
+	0xDC, 0x25, 0x4F, 0x44, 0x97, 0x43, 0xF5, 0x23, 0xF6, 0xFC, 0xFD, 0xAD, 0xBF, 0xE0, 0x98, 0x1F,
+	0x09, 0xFF, 0x00, 0xE0, 0x91, 0xDA, 0x6F, 0xFC, 0x13, 0x77, 0xFE, 0x09, 0xF9, 0xFB, 0x45, 0xF8,
+	0x8B, 0xE2, 0x8D, 0xCD, 0xC7, 0xC4, 0x48, 0xF5, 0xDB, 0x8D, 0x4B, 0x5C, 0xF0, 0xD5, 0xD5, 0x92,
+	0xDA, 0x46, 0x1C, 0xBB, 0x89, 0x25, 0x9A, 0xD2, 0xD6, 0x32, 0x19, 0x8A, 0xA0, 0x58, 0x83, 0x3E,
+	0x04, 0x9B, 0x89, 0xE7, 0x3F, 0x9A, 0xFF, 0x00, 0x09, 0xBE, 0x27, 0xF8, 0xAF, 0xE0, 0x87, 0xC5,
+	0x8F, 0x0B, 0xFC, 0x6B, 0xF8, 0x7B, 0xA8, 0x2C, 0x3A, 0xDF, 0x84, 0x7C, 0x41, 0x67, 0xAD, 0xE9,
+	0x17, 0x57, 0x56, 0xA1, 0xD6, 0x39, 0xED, 0x65, 0x13, 0x47, 0x24, 0x88, 0x38, 0x21, 0x5A, 0x25,
+	0x3F, 0xF0, 0x2A, 0xE7, 0xE8, 0xA2, 0x52, 0x52, 0x2A, 0x30, 0x51, 0x8F, 0xA9, 0xF4, 0xF7, 0xFC,
+	0x14, 0x3F, 0xFE, 0x0A, 0xD9, 0xFB, 0x58, 0xFF, 0x00, 0xC1, 0x4D, 0x6C, 0xFC, 0x27, 0x61, 0xFB,
+	0x4B, 0x8F, 0x0C, 0xDA, 0xDA, 0x78, 0x35, 0x6E, 0xA5, 0xD2, 0xED, 0x7C, 0x3F, 0xA2, 0x8B, 0x60,
+	0x65, 0x9F, 0xCA, 0x59, 0x4C, 0xAC, 0xD2, 0x48, 0xC4, 0xED, 0x8A, 0x2C, 0x6D, 0x31, 0x8F, 0x45,
+	0x5E, 0x82, 0x3F, 0xF8, 0x23, 0x97, 0xED, 0x49, 0xF0, 0xB7, 0xF6, 0x2C, 0xFF, 0x00, 0x82, 0x94,
+	0x7C, 0x31, 0xFD, 0xA3, 0xFE, 0x39, 0x5E, 0xDD, 0x59, 0xF8, 0x5F, 0xC3, 0xD7, 0x97, 0xF1, 0x6B,
+	0x57, 0xB6, 0x96, 0x92, 0xDC, 0x49, 0x6D, 0x1D, 0xDE, 0x9B, 0x75, 0x63, 0xE6, 0xED, 0x4D, 0xCC,
+	0x56, 0x36, 0xB8, 0x8E, 0x59, 0x31, 0xBD, 0xFC, 0xA4, 0x7E, 0x09, 0xAF, 0x99, 0x68, 0xA9, 0x8D,
+	0xFA, 0x87, 0x27, 0xBB, 0xCA, 0x8F, 0xD5, 0x8F, 0x8C, 0x1F, 0x02, 0x3F, 0xE0, 0xD9, 0x8F, 0x8C,
+	0xDF, 0x16, 0xBC, 0x51, 0xF1, 0x83, 0x5D, 0xFF, 0x00, 0x82, 0xA7, 0x7C, 0x4A, 0xB6, 0xD4, 0xBC,
+	0x55, 0xE2, 0x4B, 0xCD, 0x6E, 0xEE, 0xCA, 0xDF, 0xC0, 0x1A, 0x97, 0x97, 0x04, 0x97, 0x53, 0x3C,
+	0x92, 0x46, 0x9B, 0xF4, 0x62, 0xDB, 0x3C, 0xC9, 0x08, 0xF9, 0x89, 0x38, 0xEB, 0xCD, 0x78, 0x4F,
+	0xFC, 0x17, 0xE7, 0xF6, 0xD2, 0xFD, 0x9D, 0x7F, 0x6E, 0x2F, 0xDB, 0x3B, 0xC3, 0xBE, 0x34, 0xFD,
+	0x96, 0xFC, 0x5D, 0x7D, 0xE2, 0x1F, 0x0A, 0xF8, 0x4F, 0xE1, 0x86, 0x9D, 0xE1, 0x98, 0xB5, 0xEB,
+	0xED, 0x2D, 0xAD, 0x7E, 0xDB, 0x2C, 0x17, 0x77, 0x97, 0x25, 0xC4, 0x33, 0x24, 0x6F, 0xB3, 0x65,
+	0xDC, 0x6B, 0xB9, 0x91, 0x17, 0xCC, 0x8C, 0xED, 0x51, 0xD2, 0xBE, 0x1D, 0xA2, 0xAB, 0x99, 0x5A,
+	0xC4, 0x46, 0x9D, 0xA5, 0x76, 0xCF, 0xD8, 0x6F, 0x8D, 0x3F, 0x1C, 0xFF, 0x00, 0xE0, 0x84, 0x1F,
+	0xF0, 0x51, 0xCF, 0x80, 0x5F, 0x03, 0x66, 0xFD, 0xAB, 0xBF, 0x6E, 0x2F, 0x1E, 0xFC, 0x3A, 0xF1,
+	0x57, 0xC3, 0x4F, 0x85, 0xFA, 0x7F, 0x86, 0x2F, 0xB4, 0x0D, 0x0F, 0xC1, 0x57, 0xD3, 0x6C, 0x91,
+	0x20, 0x8D, 0x25, 0x66, 0x91, 0x74, 0xFB, 0x94, 0x70, 0x5D, 0x0E, 0xD6, 0x8E, 0x40, 0x4A, 0x90,
+	0x48, 0x19, 0xC5, 0x72, 0xBF, 0xB4, 0xE7, 0xED, 0x59, 0xFF, 0x00, 0x04, 0x90, 0xFD, 0x99, 0xBF,
+	0xE0, 0x8D, 0x1F, 0x12, 0x3F, 0xE0, 0x9E, 0x7F, 0xB0, 0x3F, 0xED, 0x47, 0xE2, 0x8F, 0x89, 0xDA,
+	0xB7, 0xC4, 0x8F, 0x1D, 0x58, 0xEB, 0xD9, 0xF1, 0x0F, 0x86, 0xEF, 0x2C, 0x9B, 0x4E, 0xF2, 0xAE,
+	0x34, 0xC9, 0x66, 0x91, 0x9E, 0xE2, 0xCA, 0xD6, 0x23, 0x06, 0xCD, 0x24, 0x46, 0x02, 0x82, 0xDE,
+	0x64, 0xE6, 0xBF, 0x28, 0xE8, 0xA3, 0x9B, 0xDD, 0x17, 0xB2, 0x00, 0x08, 0x18, 0x21, 0xBF, 0xE0,
+	0x59, 0xCF, 0xEB, 0xCF, 0xE7, 0xCD, 0x14, 0x51, 0x52, 0x6C, 0x14, 0x51, 0x45, 0x00, 0x1D, 0xFF,
+	0x00, 0xE0, 0x27, 0xF9, 0xAD, 0x7E, 0xFF, 0x00, 0x7F, 0xC1, 0xCB, 0x5C, 0x7F, 0xC1, 0x10, 0x7E,
+	0x02, 0xFF, 0x00, 0xD8, 0xEF, 0xE1, 0x7F, 0xFD, 0x46, 0xB5, 0x5A, 0xFC, 0x01, 0xEF, 0xFF, 0x00,
+	0x01, 0x3F, 0xCD, 0x6B, 0xF7, 0xFF, 0x00, 0xFE, 0x0E, 0x5A, 0xFF, 0x00, 0x94, 0x20, 0x7C, 0x05,
+	0xFF, 0x00, 0xB1, 0xDF, 0xC2, 0xDF, 0xFA, 0x8D, 0x6A, 0xB5, 0x4B, 0xE1, 0x67, 0x3D, 0x6F, 0xE2,
+	0x45, 0x9F, 0x80, 0x14, 0x51, 0x45, 0x4F, 0xBA, 0x75, 0x7C, 0xC2, 0x8A, 0x28, 0xA3, 0xDD, 0x26,
+	0xE7, 0xD9, 0x1F, 0xF0, 0x6F, 0xEF, 0xFC, 0xA6, 0x0F, 0xE0, 0x8F, 0xFD, 0x87, 0xAF, 0x7F, 0xF4,
+	0xD5, 0x7F, 0x5D, 0x77, 0xFC, 0x1C, 0xC9, 0xFF, 0x00, 0x29, 0x8E, 0xF8, 0x8D, 0xFF, 0x00, 0x60,
+	0xFF, 0x00, 0x0F, 0xFF, 0x00, 0xE9, 0x9A, 0xDA, 0xB9, 0x1F, 0xF8, 0x37, 0xF0, 0xE3, 0xFE, 0x0B,
+	0x09, 0xF0, 0x44, 0xFF, 0x00, 0xD4, 0x7A, 0xF7, 0xFF, 0x00, 0x4D, 0x57, 0xF5, 0xD7, 0x7F, 0xC1,
+	0xCC, 0xA7, 0x3F, 0xF0, 0x58, 0xEF, 0x88, 0xC7, 0xFE, 0xA1, 0xFE, 0x1F, 0xFF, 0x00, 0xD3, 0x35,
+	0xB5, 0x55, 0x97, 0x29, 0x8B, 0xFF, 0x00, 0x78, 0x3E, 0x09, 0x1D, 0x2B, 0xEF, 0xEF, 0xF8, 0x36,
+	0x47, 0xFE, 0x53, 0x07, 0xE0, 0x1F, 0xFB, 0x00, 0xF8, 0x83, 0xFF, 0x00, 0x4D, 0x73, 0xD7, 0xC0,
+	0x23, 0xA5, 0x7D, 0xFD, 0xFF, 0x00, 0x06, 0xC8, 0x7F, 0xCA, 0x60, 0xFC, 0x03, 0xFF, 0x00, 0x60,
+	0x1F, 0x10, 0x7F, 0xE9, 0xAA, 0x7A, 0x51, 0x4B, 0x98, 0xAA, 0xDF, 0xC3, 0x64, 0x9F, 0xF0, 0x73,
+	0xA7, 0x1F, 0xF0, 0x58, 0x4F, 0x1E, 0x81, 0xFF, 0x00, 0x40, 0x2D, 0x07, 0xFF, 0x00, 0x4D, 0xB6,
+	0xF5, 0xF9, 0xFA, 0x3A, 0x57, 0xE8, 0x17, 0xFC, 0x1C, 0xE9, 0xFF, 0x00, 0x29, 0x84, 0xF1, 0xEF,
+	0xFD, 0x80, 0xF4, 0x1F, 0xFD, 0x36, 0xDB, 0xD7, 0xE7, 0xE8, 0xE9, 0x4A, 0x56, 0xE6, 0x1D, 0x2F,
+	0xE0, 0xA1, 0x4F, 0xDE, 0x6F, 0xF3, 0xFC, 0x15, 0xFB, 0xC3, 0xFF, 0x00, 0x07, 0x63, 0x60, 0x7E,
+	0xC4, 0x5F, 0xB3, 0xD6, 0x3F, 0xE8, 0x3C, 0xDF, 0xFA, 0x6D, 0x8E, 0xBF, 0x07, 0x8F, 0xDE, 0x6F,
+	0xF3, 0xFC, 0x15, 0xFB, 0xC3, 0xFF, 0x00, 0x07, 0x63, 0x7F, 0xC9, 0x91, 0x7E, 0xCF, 0x5F, 0xF6,
+	0x1E, 0x6F, 0xFD, 0x36, 0xC7, 0x55, 0x18, 0xAB, 0x34, 0x65, 0x3F, 0xE3, 0x44, 0xFC, 0x1C, 0x4F,
+	0xB8, 0x3E, 0x94, 0xB4, 0x89, 0xF7, 0x07, 0xD2, 0x96, 0xA7, 0xDD, 0x3A, 0x7E, 0x61, 0x45, 0x14,
+	0x51, 0xEE, 0x8A, 0xE7, 0xDC, 0x5F, 0xF0, 0x6D, 0xDF, 0xFC, 0xA6, 0x8F, 0xE0, 0xBF, 0xFB, 0xDE,
+	0x21, 0xFF, 0x00, 0xD4, 0x73, 0x53, 0xAD, 0xEF, 0xF8, 0x39, 0xC7, 0xFE, 0x53, 0x03, 0xE3, 0xCF,
+	0xFB, 0x00, 0xE8, 0x3F, 0xFA, 0x6D, 0xB7, 0xAC, 0x1F, 0xF8, 0x36, 0xEF, 0xFE, 0x53, 0x47, 0xF0,
+	0x5F, 0xFD, 0xEF, 0x10, 0xFF, 0x00, 0xEA, 0x39, 0xA9, 0xD6, 0xF7, 0xFC, 0x1C, 0xE3, 0xFF, 0x00,
+	0x29, 0x81, 0xF1, 0xE7, 0xFD, 0x80, 0x74, 0x1F, 0xFD, 0x36, 0xDB, 0xD5, 0x7F, 0xCB, 0xB3, 0x1F,
+	0xF9, 0x8A, 0x3E, 0x0E, 0xF0, 0x9E, 0xB1, 0x0F, 0x87, 0x3C, 0x51, 0xA6, 0x78, 0x86, 0xE1, 0x59,
+	0xA3, 0xB1, 0xBE, 0x86, 0xEA, 0x61, 0x9F, 0x9B, 0x62, 0x38, 0x3C, 0x7F, 0x7C, 0xFC, 0xAD, 0x85,
+	0xAF, 0xD8, 0xFF, 0x00, 0xDB, 0xC3, 0xC7, 0x5F, 0xF0, 0x6E, 0xC7, 0xFC, 0x14, 0xBB, 0xE3, 0xB7,
+	0xFC, 0x35, 0x3F, 0xC6, 0x5F, 0xF8, 0x28, 0x9F, 0xC4, 0x2F, 0x09, 0xEB, 0xBA, 0xA6, 0x83, 0x67,
+	0x65, 0x79, 0xE1, 0xED, 0x33, 0xC0, 0x3A, 0x89, 0x5B, 0x55, 0x8E, 0x25, 0xC2, 0x3E, 0x74, 0xA9,
+	0x41, 0x91, 0x7E, 0xE9, 0x28, 0xEC, 0xB9, 0x1C, 0x33, 0x0C, 0x1A, 0xFC, 0x61, 0x1D, 0x28, 0xA2,
+	0x32, 0x51, 0x45, 0xCE, 0x1C, 0xD2, 0xB9, 0xFA, 0x4F, 0xFF, 0x00, 0x05, 0x56, 0xFD, 0xAB, 0x7F,
+	0xE0, 0x9D, 0x03, 0xFE, 0x09, 0xAF, 0xF0, 0x63, 0xFE, 0x09, 0xD5, 0xFB, 0x02, 0x7C, 0x78, 0xF1,
+	0x1F, 0xC4, 0xAB, 0x5F, 0x00, 0xF8, 0xD2, 0xFF, 0x00, 0x59, 0xB8, 0xF1, 0x06, 0xB5, 0xE1, 0xFB,
+	0x9B, 0x16, 0x8E, 0x39, 0x9A, 0xFA, 0x71, 0x1C, 0x9F, 0x69, 0xB6, 0x83, 0x74, 0x86, 0x5B, 0xE6,
+	0x55, 0xD9, 0x1E, 0xCC, 0x45, 0xF3, 0x9D, 0xD5, 0xB7, 0xFB, 0x0D, 0xFE, 0xD3, 0x3F, 0xF0, 0x4A,
+	0xDF, 0x8D, 0xDF, 0xF0, 0x48, 0xD8, 0x7F, 0xE0, 0x9D, 0x7F, 0xB7, 0xDF, 0xED, 0x31, 0xE2, 0x5F,
+	0x86, 0x57, 0x9A, 0x3F, 0xC4, 0xE9, 0x7C, 0x43, 0x6F, 0x71, 0xA2, 0x78, 0x5A, 0xEE, 0xF7, 0xED,
+	0x8A, 0xF1, 0x4B, 0xE5, 0xEC, 0x68, 0xAC, 0xAE, 0x63, 0xF2, 0xB3, 0x2C, 0x9B, 0xFC, 0xC1, 0xF7,
+	0xFA, 0x13, 0xD6, 0xBF, 0x2F, 0x68, 0xA7, 0xCF, 0xEF, 0x5C, 0x9F, 0x60, 0xBD, 0x9A, 0x47, 0xEC,
+	0x87, 0xEC, 0xD3, 0xF1, 0xBB, 0xFE, 0x08, 0x21, 0xFF, 0x00, 0x04, 0xCF, 0xF0, 0x6F, 0xC5, 0xAF,
+	0x89, 0xBF, 0xB3, 0x17, 0xED, 0xEB, 0xF1, 0x0B, 0xE2, 0x07, 0x8A, 0xBC, 0x69, 0xF0, 0xC7, 0x50,
+	0xF0, 0xFD, 0x9F, 0x87, 0xF5, 0x8F, 0x03, 0xDF, 0x40, 0xF3, 0x3C, 0xA6, 0x3F, 0x2C, 0xA3, 0x9D,
+	0x2E, 0xDE, 0x31, 0x28, 0x74, 0x5C, 0x79, 0x8D, 0xF7, 0x7A, 0x0A, 0xFC, 0x6F, 0x38, 0xCF, 0xCA,
+	0x8A, 0xA3, 0xB2, 0xA8, 0x20, 0x0F, 0x61, 0x90, 0x38, 0xFC, 0x05, 0x14, 0x52, 0x72, 0xE6, 0x88,
+	0xE1, 0x4F, 0x96, 0xEC, 0x29, 0x0B, 0x6C, 0x46, 0xC0, 0xDC, 0x57, 0x95, 0x4F, 0x43, 0xB4, 0xED,
+	0x1F, 0x52, 0x43, 0x62, 0x96, 0x8A, 0x93, 0x4F, 0x78, 0xFD, 0xAC, 0xFF, 0x00, 0x82, 0x81, 0x7C,
+	0x77, 0xFF, 0x00, 0x83, 0x7B, 0xBF, 0xE0, 0xAB, 0x3F, 0x14, 0x3C, 0x2F, 0xFB, 0x4C, 0x7C, 0x7D,
+	0xFD, 0xBE, 0xBC, 0x79, 0xE0, 0x5F, 0x10, 0x5A, 0xF8, 0x12, 0xC7, 0x49, 0x9B, 0xC3, 0x7A, 0x2F,
+	0x81, 0xF5, 0x29, 0x12, 0xD6, 0x38, 0xEE, 0x6E, 0xAE, 0x4C, 0x72, 0xC8, 0x74, 0x99, 0xD1, 0xE4,
+	0x59, 0x6E, 0xA5, 0x52, 0xCA, 0xE5, 0x49, 0x19, 0x04, 0x8C, 0x1A, 0xF1, 0x5F, 0xF8, 0x29, 0x5F,
+	0xED, 0x71, 0xFF, 0x00, 0x04, 0xC7, 0xF0, 0x97, 0xFC, 0x12, 0x5B, 0xC1, 0x3F, 0xF0, 0x4D, 0xAF,
+	0xD8, 0x1B, 0xF6, 0x83, 0xF1, 0x17, 0xC4, 0xC1, 0xA4, 0xFC, 0x46, 0x93, 0x5A, 0xBA, 0xD4, 0x35,
+	0xEF, 0x0D, 0x5D, 0x69, 0xF2, 0x5A, 0xC1, 0xB2, 0xF2, 0x69, 0x77, 0xC9, 0x35, 0xA5, 0xAA, 0x3B,
+	0xB4, 0x97, 0x4A, 0xAA, 0x23, 0x56, 0x25, 0x43, 0xEE, 0x3E, 0xBF, 0x97, 0xB4, 0x55, 0xF3, 0x68,
+	0xCC, 0x63, 0x45, 0x46, 0x47, 0xE9, 0xFF, 0x00, 0xFC, 0x13, 0x57, 0xF6, 0xBC, 0xFF, 0x00, 0x82,
+	0x6B, 0xF8, 0xBF, 0xFE, 0x09, 0x3B, 0xE3, 0xAF, 0xF8, 0x26, 0xB7, 0xED, 0xFD, 0xFB, 0x40, 0x78,
+	0x83, 0xE1, 0xBF, 0xF6, 0xA7, 0xC4, 0x28, 0xF5, 0xFB, 0x5D, 0x5B, 0x45, 0xF0, 0xC5, 0xD5, 0xF7,
+	0xDB, 0xAD, 0xC7, 0xD8, 0xE4, 0x45, 0x4F, 0x22, 0xD2, 0xE1, 0x51, 0x84, 0xB6, 0xA4, 0x48, 0xAE,
+	0x80, 0x04, 0x96, 0x3F, 0x29, 0xB7, 0xE4, 0xA7, 0xB2, 0xFE, 0xC0, 0xFF, 0x00, 0x18, 0x7F, 0xE0,
+	0xDE, 0xAF, 0xF8, 0x25, 0x8F, 0xC5, 0xDD, 0x5B, 0xF6, 0xA2, 0xF8, 0x11, 0xFF, 0x00, 0x05, 0x03,
+	0xF8, 0x8D, 0xE3, 0xDF, 0x11, 0x47, 0xE1, 0x1B, 0xDD, 0x2A, 0xDB, 0xC3, 0x3A, 0x97, 0x81, 0x75,
+	0x28, 0xD2, 0xFB, 0xCD, 0x30, 0xCC, 0x91, 0xC5, 0xBB, 0x4C, 0x85, 0x56, 0x57, 0x68, 0x15, 0x15,
+	0x9A, 0x41, 0x1E, 0xE7, 0x6D, 0xD8, 0x3C, 0xD7, 0xE2, 0xDD, 0x14, 0x94, 0xAC, 0x37, 0x43, 0xDE,
+	0xB8, 0x12, 0x09, 0xCA, 0xBA, 0xB0, 0xEC, 0xCB, 0xD0, 0xFB, 0x8A, 0x28, 0xA2, 0xA4, 0xD7, 0x5D,
+	0x87, 0x12, 0xC4, 0x34, 0x66, 0x26, 0x93, 0x76, 0x17, 0x6A, 0x75, 0x65, 0xC6, 0x58, 0x2F, 0xFB,
+	0x5C, 0xD7, 0xEC, 0x67, 0xED, 0x35, 0xF1, 0xB3, 0xFE, 0x08, 0x25, 0xFF, 0x00, 0x05, 0x32, 0xF0,
+	0x87, 0xC2, 0x9F, 0x88, 0x7F, 0xB4, 0xF7, 0xED, 0xE7, 0xE3, 0xAF, 0x87, 0xFE, 0x26, 0xF0, 0x7F,
+	0xC3, 0x1B, 0x0F, 0x0E, 0xDC, 0xF8, 0x7F, 0x4B, 0xF0, 0x4E, 0xA3, 0x30, 0xB6, 0x78, 0x01, 0x92,
+	0x5F, 0x35, 0xD3, 0x4E, 0x99, 0x5C, 0xEF, 0x72, 0x03, 0x2C, 0x9B, 0x4F, 0x50, 0x2B, 0xF1, 0xC6,
+	0x8A, 0xA8, 0xCA, 0xC6, 0x73, 0x83, 0x95, 0x8F, 0xD4, 0x5F, 0xDB, 0x8B, 0xF6, 0x9D, 0xFF, 0x00,
+	0x82, 0x53, 0x7C, 0x1C, 0xFF, 0x00, 0x82, 0x47, 0x4D, 0xFF, 0x00, 0x04, 0xF0, 0xFD, 0x81, 0xBF,
+	0x69, 0x7F, 0x17, 0x7C, 0x4E, 0xBE, 0xD5, 0xBE, 0x28, 0x5B, 0xF8, 0x96, 0x6B, 0x8D, 0x6B, 0xC2,
+	0xF7, 0x76, 0x52, 0x59, 0xED, 0x58, 0xFC, 0xC2, 0xF2, 0xDC, 0x59, 0xDA, 0xA1, 0xE1, 0x53, 0x62,
+	0xA0, 0x67, 0xF3, 0x37, 0x6E, 0x24, 0xD6, 0x57, 0xFC, 0x12, 0x17, 0xF6, 0xC6, 0xFF, 0x00, 0x82,
+	0x75, 0xE8, 0xBF, 0xF0, 0x4E, 0x1F, 0x8D, 0x5F, 0xF0, 0x4F, 0x6F, 0xDB, 0xD7, 0xE3, 0x66, 0xB5,
+	0xF0, 0xF2, 0xCB, 0xE2, 0x17, 0x88, 0xAD, 0x75, 0x3B, 0x6D, 0x7B, 0x48, 0xF0, 0xFD, 0xD5, 0xE7,
+	0x9B, 0x0A, 0xAD, 0xB0, 0x29, 0x0F, 0xD9, 0x6D, 0xA7, 0x31, 0x32, 0x35, 0xA4, 0x64, 0xF9, 0xCA,
+	0x14, 0xF9, 0xDF, 0x28, 0xC6, 0x2B, 0xF3, 0x3E, 0x8A, 0x39, 0xB5, 0xB8, 0x7B, 0x18, 0xF2, 0x72,
+	0xF9, 0xDC, 0xFD, 0x9C, 0xFD, 0x82, 0xBC, 0x79, 0xFF, 0x00, 0x06, 0xE9, 0xFF, 0x00, 0xC1, 0x35,
+	0x7E, 0x3C, 0x7F, 0xC3, 0x54, 0x7C, 0x20, 0xFF, 0x00, 0x82, 0x8C, 0xFC, 0x44, 0xF1, 0x66, 0xBD,
+	0x61, 0xE1, 0xFB, 0xED, 0x3E, 0xCF, 0x42, 0xD5, 0x3C, 0x09, 0xA9, 0xAA, 0x5D, 0xF9, 0xCB, 0xF3,
+	0x22, 0x8F, 0xEC, 0xA8, 0x47, 0x9A, 0x76, 0x0D, 0x9B, 0x9C, 0x22, 0x9C, 0xF4, 0x15, 0xF9, 0x05,
+	0xF1, 0x5B, 0xC6, 0x76, 0xFF, 0x00, 0x11, 0xBE, 0x28, 0xF8, 0x93, 0xE2, 0x15, 0xA5, 0x91, 0xB7,
+	0x87, 0x5E, 0xD7, 0xEF, 0x35, 0x18, 0xAD, 0xDB, 0x19, 0x89, 0x67, 0x9D, 0xE4, 0x09, 0xF2, 0xF1,
+	0xC0, 0x6C, 0x71, 0xC7, 0xA5, 0x60, 0x51, 0x43, 0x95, 0xD1, 0x51, 0x8F, 0x2B, 0x6C, 0xFD, 0x1A,
+	0xFF, 0x00, 0x83, 0x58, 0x72, 0x7F, 0xE0, 0xAC, 0x7A, 0x4E, 0x3F, 0xE8, 0x45, 0xD6, 0xBF, 0xF4,
+	0x5A, 0xD7, 0x95, 0xFF, 0x00, 0xC1, 0xC0, 0xDF, 0xF2, 0x98, 0x0F, 0x8E, 0x1F, 0xF6, 0x1B, 0xB3,
+	0xFF, 0x00, 0xD3, 0x55, 0x95, 0x7A, 0xA7, 0xFC, 0x1A, 0xC3, 0xFF, 0x00, 0x29, 0x63, 0xD2, 0x7F,
+	0xEC, 0x45, 0xD6, 0xBF, 0xF4, 0x5A, 0xD7, 0x95, 0xFF, 0x00, 0xC1, 0xC0, 0xDF, 0xF2, 0x98, 0x0F,
+	0x8E, 0x1F, 0xF6, 0x1B, 0xB3, 0xFF, 0x00, 0xD3, 0x55, 0x95, 0x3F, 0xB2, 0x67, 0xFF, 0x00, 0x2F,
+	0x99, 0xF1, 0xDC, 0x9F, 0xEB, 0x1B, 0xFD, 0xEA, 0x6D, 0x3A, 0x4F, 0xF5, 0x8D, 0xFE, 0xF5, 0x36,
+	0xA3, 0x43, 0x6B, 0x85, 0x7D, 0x41, 0xFF, 0x00, 0x04, 0x90, 0xB5, 0x82, 0xEB, 0xF6, 0xAB, 0x77,
+	0x7F, 0xBD, 0x6F, 0xE1, 0x3B, 0xE2, 0x3F, 0x17, 0x8C, 0x7F, 0xEC, 0xF5, 0xF2, 0xFD, 0x7D, 0xE9,
+	0xFF, 0x00, 0x06, 0xF5, 0xFE, 0xCC, 0x3E, 0x39, 0xFD, 0xA8, 0x3F, 0x6B, 0xEF, 0x15, 0x68, 0x5E,
+	0x06, 0xBB, 0xD1, 0xED, 0xE6, 0xD2, 0x3E, 0x1D, 0xDC, 0xDD, 0x3C, 0x9A, 0xC5, 0xC3, 0xA2, 0x0D,
+	0xF7, 0xD6, 0x11, 0xFC, 0xBE, 0x5A, 0x48, 0x73, 0xC7, 0xA5, 0x55, 0x3F, 0xE2, 0x19, 0xD6, 0x7F,
+	0xBB, 0x3E, 0xE9, 0x6F, 0xBC, 0x7E, 0xB5, 0xFA, 0x67, 0xFF, 0x00, 0x04, 0xD5, 0xFF, 0x00, 0x93,
+	0x47, 0xD0, 0xFF, 0x00, 0xEB, 0xFA, 0xFF, 0x00, 0xFF, 0x00, 0x4A, 0x5A, 0xBE, 0x6D, 0x1F, 0xF0,
+	0x49, 0x9F, 0xDA, 0x25, 0x86, 0xE3, 0xE3, 0x5F, 0x05, 0xFF, 0x00, 0xC0, 0xAF, 0xAF, 0x73, 0xFF,
+	0x00, 0xA4, 0xC3, 0xF9, 0x0A, 0xFA, 0xFF, 0x00, 0xF6, 0x45, 0xF8, 0x3D, 0xE2, 0x6F, 0x80, 0xBF,
+	0x03, 0xF4, 0xDF, 0x86, 0x5E, 0x31, 0xD4, 0x2C, 0x6E, 0x2F, 0xAC, 0xEE, 0x2E, 0x5E, 0x49, 0xB4,
+	0xDD, 0xDE, 0x4E, 0xD9, 0x26, 0x66, 0x00, 0x16, 0x00, 0x93, 0xCF, 0x52, 0x01, 0xF5, 0x03, 0xA5,
+	0x75, 0x1E, 0x59, 0xF0, 0x2F, 0xFC, 0x14, 0xEB, 0xFE, 0x4F, 0x07, 0x5C, 0xFF, 0x00, 0xAF, 0x0B,
+	0x0F, 0xFD, 0x26, 0x5A, 0xF0, 0x01, 0xD2, 0xBE, 0xE8, 0xFD, 0xB4, 0xBF, 0x60, 0xCF, 0x8F, 0x3F,
+	0x1D, 0xBE, 0x3F, 0xEA, 0x5F, 0x12, 0xFC, 0x09, 0xFD, 0x8C, 0x34, 0xFB, 0xAB, 0x5B, 0x75, 0x85,
+	0x75, 0x0D, 0x43, 0xCB, 0x93, 0x74, 0x70, 0x84, 0x3F, 0xC0, 0x7D, 0x2B, 0xCA, 0xD7, 0xFE, 0x09,
+	0x47, 0xFB, 0x56, 0x20, 0xD8, 0x91, 0xF8, 0x77, 0x6A, 0xF0, 0xBF, 0xF1, 0x38, 0xFF, 0x00, 0xED,
+	0x55, 0xCB, 0x4E, 0xA7, 0x2C, 0x2C, 0xFA, 0x7E, 0x27, 0xA1, 0x19, 0xC7, 0x95, 0x6B, 0xD2, 0xC7,
+	0xCD, 0x74, 0x57, 0xD2, 0x9F, 0xF0, 0xEA, 0x5F, 0xDA, 0xBB, 0xFE, 0x79, 0xF8, 0x77, 0xFF, 0x00,
+	0x07, 0x1F, 0xFD, 0xAA, 0x8F, 0xF8, 0x75, 0x2F, 0xED, 0x5D, 0xFF, 0x00, 0x3C, 0xFC, 0x3B, 0xFF,
+	0x00, 0x83, 0x8F, 0xFE, 0xD5, 0x5B, 0x7D, 0x62, 0x3D, 0x9F, 0xDC, 0x57, 0xB4, 0xA7, 0xFD, 0x35,
+	0xFE, 0x67, 0xCD, 0x75, 0xFB, 0x1D, 0xFB, 0x30, 0xFF, 0x00, 0xC9, 0xB5, 0xFC, 0x3C, 0xFF, 0x00,
+	0xB1, 0x1B, 0x49, 0xFF, 0x00, 0xD2, 0x38, 0xAB, 0xE0, 0x53, 0xFF, 0x00, 0x04, 0xA7, 0xFD, 0xAB,
+	0x47, 0x05, 0x3C, 0x3B, 0xFF, 0x00, 0x83, 0x8F, 0xFE, 0xD5, 0x5F, 0xA1, 0xBF, 0x05, 0x3C, 0x2B,
+	0xAB, 0xF8, 0x0F, 0xE0, 0xD7, 0x84, 0xBC, 0x0F, 0xAF, 0x08, 0xFE, 0xDD, 0xA2, 0xF8, 0x66, 0xC2,
+	0xC6, 0xF3, 0xC9, 0x7D, 0xC9, 0xE6, 0xC3, 0x6E, 0x91, 0xBE, 0xD3, 0x81, 0x91, 0xB9, 0x4E, 0x0E,
+	0x06, 0x45, 0x14, 0xEA, 0x46, 0xA3, 0xF7, 0x6F, 0xF3, 0x39, 0xF1, 0x1E, 0xF4, 0x55, 0x99, 0xF9,
+	0x91, 0xFB, 0x69, 0xFF, 0x00, 0xC9, 0xD7, 0x78, 0xDB, 0xFE, 0xC3, 0x87, 0xFF, 0x00, 0x41, 0x5A,
+	0xF2, 0xC4, 0xFB, 0x83, 0xE9, 0x5F, 0x6A, 0xFE, 0xD0, 0x7F, 0xF0, 0x4D, 0xFF, 0x00, 0x8E, 0x3F,
+	0x16, 0x7E, 0x35, 0xF8, 0x8B, 0xE2, 0x3F, 0x87, 0x7C, 0x51, 0xE1, 0x5B, 0x7B, 0x3D, 0x57, 0x52,
+	0x6B, 0x9B, 0x58, 0xB5, 0x0B, 0xEB, 0xA1, 0x2A, 0xAE, 0xDD, 0xBD, 0x16, 0x02, 0x01, 0xC7, 0x60,
+	0x48, 0xF7, 0xAE, 0x37, 0xFE, 0x1D, 0x2F, 0xFB, 0x44, 0x0E, 0x17, 0xC6, 0xBE, 0x0B, 0x3F, 0xEF,
+	0x5F, 0x5E, 0xE7, 0xFF, 0x00, 0x49, 0xEB, 0x43, 0x94, 0xF9, 0x76, 0x8A, 0xFA, 0x8B, 0xFE, 0x1D,
+	0x31, 0xFB, 0x44, 0xFF, 0x00, 0xD0, 0xE9, 0xE0, 0xAF, 0xFC, 0x0D, 0xBD, 0xFF, 0x00, 0xE4, 0x7A,
+	0x3F, 0xE1, 0xD3, 0x1F, 0xB4, 0x4F, 0xFD, 0x0E, 0x9E, 0x0A, 0xFF, 0x00, 0xC0, 0xDB, 0xDF, 0xFE,
+	0x47, 0xA0, 0x0F, 0x97, 0x6B, 0xEF, 0x4F, 0xF8, 0x24, 0x2F, 0xFC, 0x93, 0x5F, 0x18, 0x7F, 0xD8,
+	0x72, 0x0F, 0xFD, 0x13, 0x5E, 0x5B, 0xFF, 0x00, 0x0E, 0x98, 0xFD, 0xA2, 0x7F, 0xE8, 0x74, 0xF0,
+	0x57, 0xFE, 0x06, 0xDE, 0xFF, 0x00, 0xF2, 0x3D, 0x7D, 0x25, 0xFB, 0x09, 0x7E, 0xCD, 0xFE, 0x3A,
+	0xFD, 0x98, 0xFC, 0x3B, 0xE2, 0x4F, 0x0B, 0xF8, 0xF7, 0x57, 0xD2, 0x2F, 0x2E, 0x2F, 0xEF, 0x2D,
+	0xEE, 0xE2, 0x7D, 0x26, 0x69, 0x59, 0x02, 0xED, 0x64, 0xC1, 0xF3, 0x23, 0x43, 0x9F, 0x97, 0xDE,
+	0x80, 0x3E, 0x5E, 0xFF, 0x00, 0x82, 0xA8, 0xFF, 0x00, 0xC9, 0xCC, 0xDB, 0xFF, 0x00, 0xD8, 0xB1,
+	0x6B, 0xFF, 0x00, 0xA1, 0xCB, 0x5F, 0x36, 0x57, 0xDF, 0x1F, 0xB6, 0x5F, 0xEC, 0x3B, 0xF1, 0x63,
+	0xF6, 0x94, 0xF8, 0xCF, 0xFF, 0x00, 0x09, 0xE7, 0x81, 0x75, 0xFF, 0x00, 0x0E, 0xDA, 0x59, 0xC1,
+	0xA5, 0xC5, 0x65, 0x22, 0xEA, 0xD7, 0x33, 0xAB, 0x97, 0x46, 0x66, 0xE3, 0xCB, 0x85, 0xBF, 0xBF,
+	0xEB, 0x5E, 0x53, 0xFF, 0x00, 0x0E, 0x98, 0xFD, 0xA2, 0x7F, 0xE8, 0x74, 0xF0, 0x57, 0xFE, 0x06,
+	0xDE, 0xFF, 0x00, 0xF2, 0x3D, 0x00, 0x7C, 0xBB, 0x45, 0x7D, 0x45, 0xFF, 0x00, 0x0E, 0x98, 0xFD,
+	0xA2, 0x7F, 0xE8, 0x74, 0xF0, 0x57, 0xFE, 0x06, 0xDE, 0xFF, 0x00, 0xF2, 0x3D, 0x1F, 0xF0, 0xE9,
+	0x8F, 0xDA, 0x27, 0xFE, 0x87, 0x4F, 0x05, 0x7F, 0xE0, 0x6D, 0xEF, 0xFF, 0x00, 0x23, 0xD0, 0x07,
+	0xCB, 0xBD, 0xBF, 0x0A, 0xFB, 0xA3, 0xFE, 0x09, 0x01, 0xFF, 0x00, 0x22, 0xE7, 0x8F, 0xBF, 0xEC,
+	0x21, 0x61, 0xFF, 0x00, 0xA2, 0xE6, 0xAF, 0x38, 0x7F, 0xF8, 0x24, 0xD7, 0xED, 0x14, 0xAB, 0xB9,
+	0x7C, 0x6B, 0xE0, 0xBF, 0xF8, 0x0E, 0xA1, 0x7A, 0x3F, 0x5F, 0xB2, 0x9F, 0xE5, 0xFE, 0x35, 0xF4,
+	0x7F, 0xEC, 0x19, 0xFB, 0x2D, 0xF8, 0xFF, 0x00, 0xF6, 0x5E, 0xD0, 0xBC, 0x4D, 0x65, 0xE3, 0xED,
+	0x57, 0x45, 0xBA, 0x97, 0x57, 0xBA, 0xB7, 0x92, 0x07, 0xD1, 0xE6, 0x91, 0x90, 0x08, 0xC4, 0x8A,
+	0x43, 0x17, 0x8D, 0x0E, 0x7E, 0x61, 0xDA, 0x80, 0x3E, 0x62, 0xFF, 0x00, 0x82, 0xA8, 0xFF, 0x00,
+	0xC9, 0xCC, 0xDB, 0xFF, 0x00, 0xD8, 0xB1, 0x6B, 0xFF, 0x00, 0xA1, 0xCB, 0x5F, 0x36, 0x57, 0xDF,
+	0x1F, 0xB6, 0x5F, 0xEC, 0x3B, 0xF1, 0x63, 0xF6, 0x94, 0xF8, 0xCF, 0xFF, 0x00, 0x09, 0xE7, 0x81,
+	0x75, 0xFF, 0x00, 0x0E, 0xDA, 0x59, 0xC1, 0xA5, 0xC5, 0x65, 0x22, 0xEA, 0xD7, 0x33, 0xAB, 0x97,
+	0x46, 0x66, 0xE3, 0xCB, 0x85, 0xBF, 0xBF, 0xEB, 0x5E, 0x53, 0xFF, 0x00, 0x0E, 0x98, 0xFD, 0xA2,
+	0x7F, 0xE8, 0x74, 0xF0, 0x57, 0xFE, 0x06, 0xDE, 0xFF, 0x00, 0xF2, 0x3D, 0x00, 0x7C, 0xBB, 0x45,
+	0x7D, 0x45, 0xFF, 0x00, 0x0E, 0x98, 0xFD, 0xA2, 0x7F, 0xE8, 0x74, 0xF0, 0x57, 0xFE, 0x06, 0xDE,
+	0xFF, 0x00, 0xF2, 0x3D, 0x1F, 0xF0, 0xE9, 0x8F, 0xDA, 0x27, 0xFE, 0x87, 0x4F, 0x05, 0x7F, 0xE0,
+	0x6D, 0xEF, 0xFF, 0x00, 0x23, 0xD0, 0x07, 0xCB, 0xBD, 0xBF, 0x0A, 0xFB, 0x93, 0xFE, 0x09, 0x0F,
+	0xFF, 0x00, 0x22, 0xDF, 0x8F, 0x7F, 0xEC, 0x21, 0x61, 0xFF, 0x00, 0xA2, 0xE6, 0xAF, 0x3C, 0x7F,
+	0xF8, 0x24, 0xD7, 0xED, 0x14, 0xAB, 0xB9, 0x7C, 0x6B, 0xE0, 0xBF, 0xF8, 0x0E, 0xA1, 0x7A, 0x3F,
+	0x5F, 0xB2, 0x9F, 0xE5, 0xFE, 0x35, 0xF4, 0x5F, 0xEC, 0x21, 0xFB, 0x2D, 0x7C, 0x42, 0xFD, 0x98,
+	0x34, 0x8F, 0x11, 0xE9, 0xFE, 0x3E, 0xD5, 0x34, 0x5B, 0xC7, 0xD6, 0x2E, 0xA0, 0x78, 0x5B, 0x46,
+	0x92, 0x47, 0x51, 0xE5, 0x89, 0x17, 0xE6, 0x2F, 0x12, 0x7F, 0x7A, 0x80, 0x67, 0xD0, 0x96, 0xFF,
+	0x00, 0xEA, 0x85, 0x49, 0x51, 0x59, 0x95, 0x31, 0x9D, 0xBF, 0xDE, 0xE7, 0xDB, 0x8A, 0x96, 0x80,
+	0xBD, 0xF5, 0x41, 0x4D, 0x90, 0x12, 0x8C, 0x07, 0xF7, 0x69, 0xD4, 0x1E, 0x9C, 0x8A, 0x00, 0xF2,
+	0x8F, 0x8E, 0x9F, 0xB5, 0x07, 0xC2, 0xDF, 0xD9, 0xBB, 0x5E, 0xB3, 0x8F, 0xE2, 0x6D, 0xDD, 0xF4,
+	0x2D, 0xAC, 0x5A, 0xEF, 0xB5, 0xFB, 0x0D, 0x99, 0x97, 0x88, 0x9F, 0x0D, 0x93, 0xFF, 0x00, 0x03,
+	0x5A, 0xE2, 0xBF, 0xE1, 0xE8, 0x5F, 0xB2, 0xB7, 0xFD, 0x06, 0x75, 0xCF, 0xFC, 0x13, 0xBD, 0x78,
+	0xFF, 0x00, 0xFC, 0x15, 0xEC, 0x30, 0xF1, 0x0F, 0x81, 0x43, 0xB6, 0xE6, 0xFB, 0x0D, 0xF6, 0x5B,
+	0x1D, 0x7E, 0x78, 0xEB, 0xE3, 0x7A, 0x00, 0xFD, 0x28, 0xFF, 0x00, 0x87, 0xA1, 0x7E, 0xCA, 0xDF,
+	0xF4, 0x19, 0xD7, 0x3F, 0xF0, 0x4E, 0xF4, 0x7F, 0xC3, 0xD0, 0xBF, 0x65, 0x6F, 0xFA, 0x0C, 0xEB,
+	0x9F, 0xF8, 0x27, 0x7A, 0xFC, 0xD7, 0xA2, 0x80, 0x3F, 0x4A, 0x0F, 0xFC, 0x15, 0x07, 0xF6, 0x55,
+	0xC7, 0x3A, 0xC6, 0xB7, 0xFF, 0x00, 0x82, 0x67, 0xAE, 0xD3, 0xE0, 0x7F, 0xED, 0x77, 0xF0, 0x7B,
+	0xF6, 0x85, 0xF1, 0x15, 0xE7, 0x86, 0x3E, 0x1B, 0x6A, 0x1A, 0x84, 0xD7, 0x56, 0x76, 0x7F, 0x69,
+	0xB8, 0x5B, 0xCB, 0x13, 0x18, 0x11, 0x87, 0x09, 0xC7, 0xE2, 0x45, 0x7E, 0x51, 0x8E, 0xB5, 0xF5,
+	0x7F, 0xFC, 0x12, 0x47, 0xFE, 0x4B, 0x4F, 0x89, 0xBF, 0xEC, 0x54, 0x5F, 0xFD, 0x29, 0x8A, 0x80,
+	0x3E, 0xC5, 0xF8, 0xDF, 0xF1, 0xEB, 0xE1, 0xF7, 0xEC, 0xF7, 0xE1, 0x9B, 0x7F, 0x16, 0xFC, 0x40,
+	0x9E, 0xEA, 0x3B, 0x3B, 0xAD, 0x40, 0x59, 0xC4, 0xD6, 0x16, 0xFE, 0x6B, 0x79, 0xA6, 0x37, 0x90,
+	0x71, 0xEB, 0xB5, 0x0D, 0x79, 0x9F, 0xFC, 0x3D, 0x0B, 0xF6, 0x56, 0xFF, 0x00, 0xA0, 0xCE, 0xB9,
+	0xFF, 0x00, 0x82, 0x77, 0xAE, 0x7F, 0xFE, 0x0A, 0xCB, 0xFF, 0x00, 0x26, 0xEF, 0xA1, 0xFF, 0x00,
+	0xD8, 0xE5, 0x0F, 0xFE, 0x92, 0xDC, 0xD7, 0xE7, 0xBD, 0x24, 0xC7, 0xD1, 0x1F, 0xA5, 0x1F, 0xF0,
+	0xF4, 0x2F, 0xD9, 0x5B, 0xFE, 0x83, 0x3A, 0xE7, 0xFE, 0x09, 0xDE, 0x8F, 0xF8, 0x7A, 0x17, 0xEC,
+	0xAD, 0xFF, 0x00, 0x41, 0x9D, 0x73, 0xFF, 0x00, 0x04, 0xEF, 0x5F, 0x9A, 0xF4, 0x53, 0x11, 0xFA,
+	0x51, 0xFF, 0x00, 0x0F, 0x42, 0xFD, 0x95, 0xBF, 0xE8, 0x33, 0xAE, 0x7F, 0xE0, 0x9D, 0xEB, 0xA3,
+	0xF8, 0x4B, 0xFB, 0x72, 0x7C, 0x07, 0xF8, 0xD9, 0xE3, 0x9B, 0x6F, 0x87, 0xBE, 0x02, 0xD4, 0xF5,
+	0x39, 0x35, 0x2B, 0xA8, 0xE4, 0x78, 0x63, 0xBA, 0xD3, 0x59, 0x13, 0x6A, 0x26, 0xF6, 0xFF, 0x00,
+	0xC7, 0x6B, 0xF2, 0xD2, 0xBD, 0xEB, 0xFE, 0x09, 0xB1, 0xFF, 0x00, 0x27, 0x73, 0xA0, 0xFF, 0x00,
+	0xD8, 0x3F, 0x50, 0xFF, 0x00, 0xD2, 0x77, 0xA0, 0x0F, 0xD0, 0xBF, 0x8A, 0xFF, 0x00, 0x14, 0xBC,
+	0x25, 0xF0, 0x5F, 0xC1, 0x37, 0xBF, 0x11, 0x3C, 0x67, 0x2C, 0xA9, 0xA7, 0x69, 0xED, 0x08, 0xB9,
+	0x6B, 0x58, 0xBC, 0xC9, 0x07, 0x99, 0x2A, 0xC6, 0xBC, 0x7F, 0xBC, 0xD5, 0xE4, 0x49, 0xFF, 0x00,
+	0x05, 0x41, 0xFD, 0x95, 0xC2, 0x28, 0x3A, 0xC6, 0xB9, 0xD3, 0xF8, 0xB4, 0x77, 0xCD, 0x6B, 0x7F,
+	0xC1, 0x45, 0x3F, 0xE4, 0xCE, 0xFC, 0x5B, 0xFF, 0x00, 0x5D, 0x2C, 0x7F, 0xF4, 0xB6, 0x0A, 0xFC,
+	0xC1, 0xA9, 0x8B, 0xFE, 0xBE, 0x41, 0xD1, 0x1F, 0xA5, 0x1F, 0xF0, 0xF4, 0x2F, 0xD9, 0x5B, 0xFE,
+	0x83, 0x3A, 0xE7, 0xFE, 0x09, 0xDE, 0x8F, 0xF8, 0x7A, 0x17, 0xEC, 0xAD, 0xFF, 0x00, 0x41, 0x9D,
+	0x73, 0xFF, 0x00, 0x04, 0xEF, 0x5F, 0x9A, 0xF4, 0x55, 0x01, 0xFA, 0x51, 0xFF, 0x00, 0x0F, 0x42,
+	0xFD, 0x95, 0xBF, 0xE8, 0x33, 0xAE, 0x7F, 0xE0, 0x9D, 0xEB, 0x4F, 0xC1, 0x5F, 0xF0, 0x50, 0xCF,
+	0xD9, 0xCB, 0xE2, 0x17, 0x8C, 0x34, 0xDF, 0x04, 0xF8, 0x63, 0x56, 0xD5, 0xDB, 0x50, 0xD5, 0x6F,
+	0x23, 0xB6, 0xB3, 0x8E, 0x6D, 0x2D, 0x91, 0x4C, 0x8E, 0x48, 0x19, 0xFC, 0x45, 0x7E, 0x62, 0x57,
+	0xA2, 0x7E, 0xC9, 0x5F, 0xF2, 0x73, 0x9E, 0x01, 0xFF, 0x00, 0xB1, 0xAA, 0xD3, 0xFF, 0x00, 0x42,
+	0x14, 0x01, 0xFA, 0x99, 0xF1, 0x0F, 0xC6, 0x3A, 0x2F, 0xC3, 0xCF, 0x03, 0xEB, 0x1E, 0x3C, 0xF1,
+	0x0A, 0x48, 0xD6, 0x5A, 0x2E, 0x93, 0x71, 0x7F, 0x7C, 0xB6, 0xF1, 0xEE, 0x90, 0xC5, 0x14, 0x65,
+	0xDC, 0x2A, 0xFD, 0x00, 0xE2, 0xBE, 0x70, 0x6F, 0xF8, 0x2B, 0xC7, 0xEC, 0xDA, 0x08, 0x1F, 0xF0,
+	0x8E, 0x78, 0xB7, 0x8F, 0xBD, 0xFF, 0x00, 0x12, 0xA8, 0x7F, 0xAC, 0xE0, 0xFE, 0x60, 0x1A, 0xF6,
+	0xFF, 0x00, 0xDA, 0x93, 0xFE, 0x4D, 0xA3, 0xE2, 0x27, 0xFD, 0x89, 0x3A, 0x9F, 0xFE, 0x92, 0xC9,
+	0x5F, 0x8D, 0x75, 0xF2, 0x5C, 0x41, 0x9C, 0x62, 0xF2, 0xDA, 0xD4, 0xD5, 0x2B, 0x59, 0xA6, 0xF5,
+	0xF5, 0x3F, 0x60, 0xF0, 0xCB, 0x81, 0xB2, 0x7E, 0x2D, 0xC1, 0xE2, 0x2A, 0xE3, 0x5C, 0xAF, 0x4E,
+	0x49, 0x2E, 0x56, 0x96, 0x8D, 0x5F, 0x5D, 0x19, 0xFA, 0x4B, 0xFF, 0x00, 0x0F, 0x7A, 0xFD, 0x9B,
+	0x3B, 0x78, 0x6F, 0xC5, 0x9F, 0xF8, 0x2B, 0x83, 0xFF, 0x00, 0x8F, 0xD1, 0xFF, 0x00, 0x0F, 0x7A,
+	0xFD, 0x9B, 0x3F, 0xE8, 0x5B, 0xF1, 0x67, 0xFE, 0x0A, 0xA0, 0xFF, 0x00, 0xE3, 0xF5, 0xF9, 0xB5,
+	0x45, 0x7C, 0xF7, 0xFA, 0xD9, 0x99, 0xF6, 0x8F, 0xDC, 0x7E, 0x9B, 0xFF, 0x00, 0x10, 0x63, 0x84,
+	0x7B, 0xD4, 0xFF, 0x00, 0xC0, 0x97, 0xFF, 0x00, 0x22, 0x7E, 0x92, 0x7F, 0xC3, 0xDE, 0x3F, 0x66,
+	0xB1, 0xD3, 0xC3, 0x9E, 0x2D, 0xFF, 0x00, 0xC1, 0x54, 0x1F, 0xFC, 0x91, 0x5D, 0x87, 0xC0, 0x7F,
+	0xF8, 0x28, 0x47, 0xC1, 0x4F, 0xDA, 0x0F, 0xE2, 0x34, 0x5F, 0x0D, 0x3C, 0x17, 0xA3, 0xEB, 0xD0,
+	0xEA, 0x37, 0x31, 0x49, 0x24, 0x4D, 0xA9, 0x5A, 0x44, 0x88, 0x55, 0x14, 0x31, 0xE5, 0x25, 0x72,
+	0x3A, 0xFA, 0x57, 0xE5, 0x5D, 0x7D, 0x0F, 0xFF, 0x00, 0x04, 0xBC, 0xFF, 0x00, 0x93, 0xBA, 0xD2,
+	0x7F, 0xEC, 0x15, 0x7D, 0xFF, 0x00, 0xA2, 0x8D, 0x77, 0x65, 0xFC, 0x4D, 0x98, 0x62, 0x31, 0x54,
+	0xE8, 0xCA, 0xD6, 0x6E, 0xCE, 0xCB, 0xFE, 0x09, 0xE1, 0xF1, 0x37, 0x85, 0x3C, 0x31, 0x94, 0x64,
+	0x18, 0x8C, 0x6D, 0x17, 0x3E, 0x6A, 0x71, 0x6D, 0x5E, 0x4A, 0xD7, 0xE9, 0x7B, 0x24, 0x7E, 0x91,
+	0xFC, 0x5C, 0xF8, 0xB1, 0xE1, 0x2F, 0x82, 0xFE, 0x04, 0x9B, 0xE2, 0x07, 0x8F, 0x1E, 0x65, 0xD3,
+	0x6D, 0x64, 0x8D, 0x26, 0x6B, 0x48, 0x7C, 0xC2, 0x3C, 0xC7, 0x08, 0xBF, 0xFA, 0x15, 0x79, 0x0A,
+	0xFF, 0x00, 0xC1, 0x50, 0xBF, 0x65, 0x72, 0xA0, 0x9D, 0x63, 0x5C, 0xFF, 0x00, 0xC1, 0x3B, 0xD5,
+	0xCF, 0xF8, 0x29, 0x4F, 0xFC, 0x9A, 0x46, 0xB9, 0xFF, 0x00, 0x5F, 0x96, 0x3F, 0xFA, 0x50, 0xB5,
+	0xF9, 0x97, 0x5F, 0xA0, 0x1F, 0xCD, 0xC6, 0x2F, 0xFC, 0x1D, 0x2F, 0xFB, 0x4C, 0xFC, 0x16, 0xFD,
+	0xA5, 0x3F, 0x65, 0x4F, 0x87, 0x2D, 0xF0, 0xEB, 0x51, 0xD4, 0x64, 0xBE, 0xD1, 0xFE, 0x22, 0x34,
+	0x73, 0x0B, 0xBD, 0x3C, 0xC6, 0x3C, 0x89, 0xAC, 0x26, 0x2D, 0xFF, 0x00, 0x8F, 0x24, 0x75, 0xF8,
+	0x7B, 0x90, 0x79, 0x15, 0xFA, 0x99, 0xFF, 0x00, 0x05, 0x59, 0xD0, 0xFF, 0x00, 0xB5, 0xFF, 0x00,
+	0x64, 0x2B, 0xEB, 0xFF, 0x00, 0x23, 0x77, 0xF6, 0x56, 0xBB, 0x63, 0x79, 0xBB, 0xD3, 0x32, 0x1B,
+	0x7F, 0xFD, 0xAD, 0x5F, 0x96, 0x78, 0xDB, 0xF2, 0xFA, 0x71, 0x5C, 0xF5, 0x3E, 0x2B, 0x9E, 0x8E,
+	0x1D, 0xFE, 0xEE, 0xC1, 0x45, 0x14, 0x56, 0x66, 0xE7, 0x6D, 0xFB, 0x33, 0x7C, 0x63, 0xFF, 0x00,
+	0x86, 0x73, 0xFD, 0xA4, 0xFE, 0x1E, 0xFE, 0xD0, 0xC7, 0xC3, 0x7F, 0xDB, 0x07, 0xC0, 0x7E, 0x36,
+	0xD2, 0xBC, 0x49, 0xFD, 0x93, 0xF6, 0xBF, 0x27, 0xED, 0xC2, 0xCA, 0xEE, 0x39, 0xFE, 0xCF, 0xBF,
+	0x6B, 0x79, 0x7B, 0xFC, 0xBD, 0xBB, 0xB6, 0x37, 0xDE, 0xEF, 0x5F, 0x48, 0x7F, 0xC1, 0x61, 0x7F,
+	0xE0, 0xAC, 0x47, 0xFE, 0x0A, 0xC9, 0xF1, 0x27, 0xC1, 0x7F, 0x10, 0x5B, 0xE0, 0x07, 0xFC, 0x20,
+	0xBF, 0xF0, 0x8A, 0xE8, 0xB3, 0x69, 0xBF, 0x62, 0x1E, 0x2A, 0xFE, 0xD7, 0xFB, 0x60, 0x96, 0x76,
+	0x60, 0xDB, 0xFE, 0xC9, 0x6D, 0xB3, 0x1F, 0xF0, 0x2F, 0xA9, 0xAF, 0x8E, 0x68, 0xAA, 0xE6, 0xB4,
+	0x6C, 0x4F, 0x2C, 0x6E, 0x98, 0x0C, 0xE3, 0x96, 0xDD, 0xFE, 0xD6, 0x73, 0x9A, 0x28, 0xA2, 0xA4,
+	0xA0, 0xA5, 0xC8, 0x23, 0x63, 0x6E, 0x1F, 0xBA, 0x70, 0xAD, 0xB9, 0x77, 0x26, 0x43, 0x7C, 0xC3,
+	0xCC, 0xE3, 0x20, 0x96, 0xC5, 0x25, 0x0B, 0xD4, 0xFE, 0x1F, 0xC8, 0xD0, 0x4C, 0xBE, 0x16, 0x8F,
+	0xD3, 0xFF, 0x00, 0xF8, 0x2E, 0x47, 0xFC, 0x10, 0xDF, 0xF6, 0x7C, 0xFF, 0x00, 0x82, 0x5A, 0xFE,
+	0xCF, 0x7E, 0x13, 0xF8, 0xCD, 0xF0, 0x8F, 0xE2, 0xB7, 0x8C, 0x3C, 0x43, 0x7D, 0xAF, 0x78, 0xD1,
+	0x74, 0x9B, 0x8B, 0x2F, 0x10, 0x7D, 0x97, 0xC8, 0x8A, 0x1F, 0xB2, 0x4F, 0x3B, 0x30, 0xF2, 0x61,
+	0x46, 0xCE, 0xE8, 0x7B, 0xB1, 0x3E, 0xE7, 0xAD, 0x27, 0xFC, 0x13, 0xFB, 0xFE, 0x08, 0x67, 0xFB,
+	0x3E, 0xFE, 0xD6, 0xBF, 0xF0, 0x4A, 0x8F, 0x17, 0x7E, 0xDE, 0x3E, 0x36, 0xF8, 0xBF, 0xE3, 0x6D,
+	0x37, 0xC4, 0x9E, 0x1E, 0xD3, 0x7C, 0x49, 0x35, 0xAE, 0x93, 0xA3, 0xB5, 0x9F, 0xD8, 0x64, 0x6D,
+	0x3E, 0xDC, 0xCA, 0x9B, 0xBC, 0xDB, 0x77, 0x93, 0xE6, 0x75, 0x3B, 0xB0, 0xF9, 0xF7, 0xAF, 0xB6,
+	0xBF, 0xE0, 0xF0, 0x4F, 0xF9, 0x32, 0x0F, 0x86, 0x3F, 0xF6, 0x56, 0x13, 0xFF, 0x00, 0x4D, 0x97,
+	0xF4, 0xFF, 0x00, 0xF8, 0x22, 0x57, 0xFC, 0xAB, 0x79, 0xF1, 0x33, 0xFE, 0xC0, 0x1E, 0x3B, 0xFF,
+	0x00, 0xD2, 0x29, 0xAB, 0x6E, 0x55, 0xCF, 0x63, 0x9B, 0x9A, 0x5E, 0xC5, 0x3B, 0xF5, 0x3F, 0x2B,
+	0x3F, 0xE0, 0x87, 0xDF, 0xF0, 0x4D, 0xFF, 0x00, 0x85, 0x5F, 0xF0, 0x54, 0x0F, 0xDA, 0xC3, 0xC4,
+	0x1F, 0x01, 0x7E, 0x2E, 0xF8, 0xE7, 0x5E, 0xF0, 0xEE, 0x99, 0xA4, 0xFC, 0x3D, 0xBB, 0xF1, 0x14,
+	0x17, 0xBE, 0x17, 0x68, 0x7C, 0xE3, 0x71, 0x0D, 0xF5, 0x85, 0xB2, 0xA9, 0xF3, 0xA3, 0x91, 0x71,
+	0xB6, 0xE9, 0xFA, 0x28, 0x1F, 0x27, 0x41, 0x5C, 0x7F, 0xED, 0xA7, 0xFB, 0x11, 0xFC, 0x3F, 0xFD,
+	0x99, 0x7F, 0xE0, 0xA7, 0x9A, 0xD7, 0xEC, 0x39, 0xE1, 0x5F, 0x13, 0x6B, 0x17, 0xDE, 0x1B, 0xD3,
+	0x3C, 0x63, 0xA4, 0xE9, 0x11, 0x6B, 0x1A, 0x97, 0x93, 0xF6, 0xD3, 0x0D, 0xDC, 0x76, 0x8D, 0x29,
+	0x3E, 0x54, 0x69, 0x1E, 0x41, 0x97, 0x8C, 0xA1, 0x15, 0xF5, 0xE7, 0xFC, 0x1A, 0x0B, 0xFF, 0x00,
+	0x29, 0x27, 0xF1, 0xB0, 0xFF, 0x00, 0xAA, 0x1F, 0xA9, 0x7F, 0xE9, 0xE3, 0x45, 0xAF, 0x2C, 0xFF,
+	0x00, 0x82, 0xB2, 0x7F, 0xCA, 0xC3, 0x1E, 0x2B, 0xFF, 0x00, 0xB2, 0xAB, 0xE1, 0xAF, 0xFD, 0x27,
+	0xD3, 0xEA, 0x5F, 0xC0, 0x5F, 0x3C, 0xBD, 0xB4, 0xBD, 0x0D, 0xAF, 0xF8, 0x2E, 0xD7, 0xFC, 0x11,
+	0xA3, 0xE0, 0x4F, 0xFC, 0x12, 0xAB, 0xC2, 0xDF, 0x0D, 0xF5, 0xEF, 0x83, 0xBF, 0x14, 0xFC, 0x5D,
+	0xE2, 0x29, 0xBC, 0x67, 0xA9, 0x6A, 0x50, 0x6A, 0x2B, 0xE2, 0x5F, 0xB2, 0x6D, 0xB7, 0x5B, 0x68,
+	0xED, 0xA4, 0x0D, 0x1F, 0x91, 0x04, 0x6D, 0x96, 0xF3, 0x39, 0xC9, 0x27, 0xDE, 0xBA, 0x2F, 0xD9,
+	0x23, 0xFE, 0x08, 0x6B, 0xFB, 0x3E, 0xFE, 0xD0, 0x9F, 0xF0, 0x46, 0x8F, 0x15, 0x7F, 0xC1, 0x47,
+	0xFC, 0x43, 0xF1, 0x63, 0xC6, 0x5A, 0x7F, 0x8A, 0xF4, 0x2F, 0x05, 0xF8, 0xB7, 0x55, 0xB5, 0xD0,
+	0xF4, 0xB6, 0xB3, 0xFB, 0x0B, 0xC9, 0xA5, 0xA5, 0xCB, 0x45, 0x19, 0xF3, 0x62, 0x79, 0x3E, 0x76,
+	0xB6, 0x46, 0x38, 0x70, 0x6B, 0xEA, 0x3F, 0xF8, 0x3C, 0x97, 0xFE, 0x49, 0xAF, 0xC0, 0x5F, 0xFB,
+	0x0F, 0x78, 0x83, 0xFF, 0x00, 0x49, 0xAC, 0x6B, 0xBB, 0xFF, 0x00, 0x82, 0x65, 0x7F, 0xCA, 0xAA,
+	0x3F, 0x11, 0xFF, 0x00, 0xEC, 0x94, 0x7C, 0x4A, 0xFF, 0x00, 0xD1, 0x7A, 0xA5, 0x1C, 0xAB, 0x9B,
+	0xD0, 0x9F, 0x69, 0x2F, 0x62, 0x9F, 0x99, 0xF9, 0x7B, 0xFF, 0x00, 0x04, 0x39, 0xFF, 0x00, 0x82,
+	0x63, 0xFC, 0x22, 0xFF, 0x00, 0x82, 0xA5, 0x7C, 0x7F, 0xF1, 0x77, 0xC1, 0xEF, 0x8B, 0x9F, 0x10,
+	0x3C, 0x41, 0xE1, 0xCB, 0x0D, 0x07, 0xC1, 0x6D, 0xAA, 0xDB, 0xDC, 0xF8, 0x65, 0xA1, 0xF3, 0x1E,
+	0x53, 0x79, 0x04, 0x01, 0x7F, 0x7C, 0x92, 0xAE, 0xDC, 0x4D, 0xC6, 0x06, 0x2B, 0xCF, 0xBF, 0x68,
+	0x0F, 0xD8, 0x93, 0xC0, 0x1F, 0x0A, 0xFF, 0x00, 0xE0, 0xAA, 0xF7, 0x5F, 0xB0, 0x4E, 0x8B, 0xE2,
+	0x7D, 0x62, 0xF3, 0xC3, 0x30, 0xFC, 0x53, 0xD3, 0xFC, 0x2A, 0xBA, 0xA5, 0xC7, 0x95, 0xF6, 0xD7,
+	0xB5, 0xB9, 0xBA, 0xB6, 0x8D, 0x9D, 0xF1, 0x12, 0x45, 0xB8, 0x79, 0xAE, 0x47, 0xC8, 0xC3, 0x3D,
+	0x38, 0xAF, 0xB5, 0xBF, 0xE0, 0xCF, 0xCF, 0xF9, 0x3E, 0x2F, 0x89, 0xDF, 0xF6, 0x4A, 0xFF, 0x00,
+	0xF7, 0x29, 0x67, 0x5E, 0x21, 0xFB, 0x68, 0xFF, 0x00, 0xCA, 0xC8, 0xDA, 0xA7, 0xFD, 0x9C, 0x66,
+	0x87, 0xFF, 0x00, 0xA5, 0xD6, 0x74, 0x9F, 0xC0, 0xBC, 0xCA, 0xF6, 0x92, 0xF6, 0xD2, 0xF4, 0x2E,
+	0xFF, 0x00, 0xC1, 0x7A, 0x3F, 0xE0, 0x8F, 0xDF, 0x04, 0x3F, 0xE0, 0x94, 0xE7, 0xE1, 0x6C, 0x7F,
+	0x07, 0xFE, 0x27, 0x78, 0xB3, 0xC4, 0x5F, 0xF0, 0x9F, 0xAE, 0xBA, 0x9A, 0xA4, 0x9E, 0x25, 0x6B,
+	0x4D, 0xF6, 0xFF, 0x00, 0x62, 0x1A, 0x79, 0x8D, 0xA1, 0xF2, 0x62, 0x8F, 0xA9, 0xBB, 0x90, 0x9F,
+	0xF7, 0x2B, 0xB3, 0xF0, 0xDF, 0xFC, 0x10, 0xE3, 0xF6, 0x7B, 0xD7, 0xFF, 0x00, 0xE0, 0x89, 0x33,
+	0x7F, 0xC1, 0x4F, 0x2E, 0x7E, 0x2C, 0x78, 0xC3, 0xFE, 0x13, 0x04, 0xF0, 0x5D, 0xE6, 0xB0, 0xBE,
+	0x1E, 0x46, 0xB2, 0xFE, 0xC9, 0x79, 0x22, 0xBF, 0x96, 0x1F, 0x24, 0xE6, 0xDD, 0xE5, 0xF2, 0x9B,
+	0x66, 0xE6, 0xF9, 0xC1, 0xDD, 0x5F, 0x43, 0x7F, 0xC1, 0xE6, 0xBF, 0x7B, 0xF6, 0x6F, 0xFF, 0x00,
+	0x77, 0xC6, 0x1F, 0xCF, 0x44, 0xAF, 0x54, 0xF8, 0x7B, 0xFF, 0x00, 0x2A, 0x8B, 0xDC, 0x7F, 0xD9,
+	0x29, 0xD5, 0x3F, 0xF4, 0xF1, 0x3D, 0x5F, 0x24, 0x4C, 0xF9, 0xE5, 0xEC, 0xA3, 0xEA, 0x7E, 0x69,
+	0x7F, 0xC1, 0x0B, 0x7F, 0xE0, 0x95, 0xDF, 0x07, 0xBF, 0xE0, 0xAA, 0x3F, 0x15, 0xFC, 0x77, 0xF0,
+	0xF7, 0xE2, 0xF7, 0xC4, 0x4F, 0x14, 0x78, 0x7E, 0xDF, 0xC2, 0x9E, 0x1D, 0xB4, 0xBF, 0xB3, 0xB8,
+	0xF0, 0xEF, 0x91, 0xE6, 0xCA, 0xD2, 0x4E, 0x50, 0xEE, 0xFB, 0x44, 0x72, 0x0E, 0x7F, 0xDD, 0x1F,
+	0x41, 0x5E, 0x32, 0xDF, 0xB1, 0xEF, 0x81, 0x5B, 0xFE, 0x0A, 0xB9, 0xFF, 0x00, 0x0C, 0x03, 0xFF,
+	0x00, 0x09, 0x16, 0xA6, 0xDE, 0x18, 0xFF, 0x00, 0x86, 0x84, 0x3F, 0x0F, 0x3F, 0xB6, 0x1B, 0xCA,
+	0xFB, 0x61, 0xB1, 0x3A, 0xE0, 0xB0, 0xF3, 0xBE, 0x58, 0xCC, 0x3E, 0x61, 0x8F, 0xE6, 0x3F, 0x2A,
+	0x8C, 0x93, 0x80, 0x07, 0x15, 0xFA, 0x09, 0xFF, 0x00, 0x06, 0x75, 0x7F, 0xC9, 0xC9, 0xFC, 0x64,
+	0xFF, 0x00, 0xB1, 0x16, 0xC7, 0xFF, 0x00, 0x4B, 0x5A, 0xBE, 0x57, 0x97, 0xFE, 0x56, 0x4D, 0xFF,
+	0x00, 0xBB, 0xE4, 0x5F, 0xFD, 0x4C, 0x45, 0x67, 0xF6, 0x53, 0x34, 0xE7, 0x97, 0xB5, 0x97, 0xA1,
+	0xB5, 0xFF, 0x00, 0x05, 0xDB, 0xFF, 0x00, 0x82, 0x4C, 0x7C, 0x15, 0xFF, 0x00, 0x82, 0x54, 0x78,
+	0xB7, 0xE1, 0xAE, 0x87, 0xF0, 0x7B, 0xE2, 0x6F, 0x8A, 0x7C, 0x45, 0x0F, 0x8D, 0x34, 0xFD, 0x46,
+	0xE7, 0x50, 0x9B, 0xC4, 0x9F, 0x65, 0xF3, 0x2D, 0x9A, 0xDA, 0x4B, 0x74, 0x1E, 0x5F, 0xD9, 0xE2,
+	0x89, 0x79, 0xF3, 0xF9, 0xDC, 0x6B, 0xD0, 0x3C, 0x51, 0xFF, 0x00, 0x04, 0x33, 0xFD, 0x9F, 0x74,
+	0x6F, 0xF8, 0x22, 0x3A, 0x7F, 0xC1, 0x4E, 0xED, 0xFE, 0x2C, 0xF8, 0xD3, 0xFE, 0x13, 0x09, 0xBC,
+	0x11, 0x6B, 0xAA, 0xB7, 0x87, 0xCB, 0x59, 0x7F, 0x67, 0x09, 0xE6, 0xBE, 0x8E, 0xDF, 0x68, 0xC5,
+	0xBE, 0xFC, 0x00, 0xF8, 0x1F, 0x3B, 0x71, 0xFC, 0x47, 0xA9, 0xF6, 0xEF, 0xF8, 0x3C, 0x8F, 0xFE,
+	0x4A, 0x47, 0xC0, 0x3F, 0xFB, 0x00, 0x6B, 0xDF, 0xFA, 0x53, 0xA7, 0xD7, 0xB7, 0xFC, 0x45, 0xFF,
+	0x00, 0x95, 0x44, 0xE1, 0xFF, 0x00, 0xB2, 0x55, 0xA6, 0x7F, 0xE9, 0xE2, 0x0A, 0xAE, 0x58, 0xEA,
+	0x4F, 0x34, 0xBD, 0x8C, 0x3D, 0x4F, 0xCF, 0x2F, 0xF8, 0x20, 0xCF, 0xFC, 0x12, 0x0B, 0xE0, 0x7F,
+	0xFC, 0x15, 0x78, 0xFC, 0x52, 0x7F, 0x8C, 0xFF, 0x00, 0x11, 0x7C, 0x4D, 0xE1, 0xF1, 0xE0, 0x63,
+	0xA1, 0x9B, 0x18, 0xFC, 0x36, 0xD6, 0xDF, 0xBF, 0x5B, 0xD6, 0xBF, 0xF3, 0x16, 0x5F, 0x3E, 0x37,
+	0x6C, 0x03, 0x65, 0x16, 0x30, 0x05, 0x78, 0x67, 0xC0, 0x1F, 0xD8, 0x9F, 0xC0, 0x1F, 0x15, 0xFF,
+	0x00, 0xE0, 0xAA, 0xD6, 0x7F, 0xB0, 0x67, 0x88, 0xBC, 0x5B, 0xAD, 0x45, 0xE1, 0xD9, 0xBE, 0x2B,
+	0x6A, 0x1E, 0x16, 0x97, 0x58, 0xB7, 0xF2, 0xFE, 0xDC, 0xF6, 0x76, 0xD7, 0x13, 0x46, 0xAE, 0xDF,
+	0xBB, 0x31, 0xEF, 0x3B, 0x01, 0x39, 0x50, 0x32, 0x4F, 0x03, 0xA5, 0x7E, 0x96, 0x7F, 0xC1, 0x9A,
+	0x1F, 0xEB, 0x3F, 0x68, 0xEF, 0xA7, 0x83, 0xFF, 0x00, 0x9E, 0xBD, 0x5F, 0x1D, 0x7E, 0xC5, 0xFF,
+	0x00, 0xF2, 0xB2, 0x2E, 0x9B, 0xFF, 0x00, 0x67, 0x21, 0xAD, 0xFF, 0x00, 0xE9, 0x65, 0xED, 0x1C,
+	0xB1, 0xB2, 0x65, 0x29, 0x4B, 0x9A, 0x67, 0x33, 0xFF, 0x00, 0x05, 0xCD, 0xFF, 0x00, 0x82, 0x62,
+	0xFC, 0x29, 0xFF, 0x00, 0x82, 0x5B, 0xFE, 0xD0, 0x3E, 0x0F, 0xF8, 0x41, 0xF0, 0x7B, 0xC7, 0xDE,
+	0x25, 0xF1, 0x0D, 0x9F, 0x88, 0xBC, 0x1B, 0xFD, 0xA9, 0x35, 0xD7, 0x89, 0x5A, 0x0F, 0x39, 0x2E,
+	0x0D, 0xD5, 0xC4, 0x22, 0x30, 0xF6, 0xE8, 0x88, 0xAA, 0x04, 0x7B, 0xB9, 0x46, 0xC6, 0x6B, 0xF4,
+	0xDF, 0xFE, 0x0B, 0x03, 0xA6, 0xF8, 0x7B, 0xF6, 0xB2, 0xFF, 0x00, 0x83, 0x6A, 0x3C, 0x0B, 0xFB,
+	0x44, 0x6A, 0x90, 0x5C, 0x68, 0xB3, 0xF8, 0x63, 0x47, 0xF0, 0x5F, 0x8A, 0xF4, 0xCD, 0x32, 0xDE,
+	0xEE, 0x39, 0x23, 0x79, 0x26, 0x58, 0x74, 0x96, 0x86, 0x43, 0xB5, 0x73, 0x17, 0x93, 0xA9, 0x4C,
+	0xDD, 0x07, 0xCC, 0x89, 0xC0, 0xE9, 0x5F, 0x2F, 0xFF, 0x00, 0xC1, 0xE1, 0x3F, 0xF2, 0x7B, 0xBF,
+	0x0C, 0x7F, 0xEC, 0x94, 0xFF, 0x00, 0xEE, 0x4A, 0xF2, 0xBE, 0xAA, 0xFD, 0xB2, 0x49, 0xFF, 0x00,
+	0x88, 0x46, 0x74, 0x5F, 0xFB, 0x25, 0x7E, 0x03, 0xFF, 0x00, 0xD3, 0xCE, 0x91, 0x4F, 0x97, 0xDE,
+	0x66, 0x7E, 0xF4, 0xA3, 0x09, 0x36, 0x7E, 0x7F, 0xFF, 0x00, 0xC1, 0x08, 0xFF, 0x00, 0xE0, 0x8C,
+	0xFF, 0x00, 0x02, 0x7F, 0xE0, 0xAB, 0x3E, 0x12, 0xF8, 0x91, 0xE2, 0x3F, 0x8C, 0x9F, 0x14, 0x3C,
+	0x5F, 0xE1, 0xF9, 0x3C, 0x19, 0xAA, 0xE9, 0xB1, 0x58, 0xC3, 0xE1, 0xC3, 0x6A, 0x16, 0xE1, 0x2E,
+	0x22, 0x9C, 0x9F, 0x33, 0xCE, 0x82, 0x43, 0x82, 0xD0, 0x76, 0xE2, 0xBE, 0x7A, 0xFD, 0x8B, 0x3F,
+	0x62, 0x6F, 0x01, 0x7E, 0xD3, 0x3F, 0xF0, 0x53, 0xDD, 0x17, 0xF6, 0x18, 0xF1, 0x67, 0x8B, 0xB5,
+	0x9D, 0x3F, 0x40, 0xD4, 0xBC, 0x61, 0xAB, 0x68, 0xD3, 0x6B, 0x16, 0x3E, 0x4F, 0xDB, 0x23, 0x8E,
+	0xD5, 0x2E, 0x9D, 0x1D, 0x7F, 0x76, 0xD1, 0xEE, 0x61, 0x6C, 0x0B, 0x65, 0x17, 0x93, 0xF7, 0x47,
+	0x41, 0xFA, 0x95, 0xFF, 0x00, 0x06, 0x6C, 0x7F, 0xC9, 0x34, 0xF8, 0xF5, 0xFF, 0x00, 0x61, 0xAF,
+	0x0F, 0xFF, 0x00, 0xE8, 0x8B, 0xDA, 0xF8, 0x7F, 0xFE, 0x09, 0x31, 0xFF, 0x00, 0x2B, 0x0C, 0x78,
+	0x4F, 0xFE, 0xCA, 0xB7, 0x88, 0xFF, 0x00, 0xF4, 0x9F, 0x54, 0xA5, 0xCB, 0x1E, 0x54, 0x68, 0xA5,
+	0x2B, 0xCD, 0x79, 0x1C, 0x47, 0xFC, 0x17, 0x03, 0xFE, 0x09, 0xBD, 0xF0, 0xA7, 0xFE, 0x09, 0x83,
+	0xFB, 0x58, 0xF8, 0x7F, 0xE0, 0x17, 0xC2, 0x3F, 0x1B, 0xF8, 0x8B, 0x5E, 0xD2, 0x75, 0xAF, 0x87,
+	0x56, 0xFA, 0xF5, 0xC5, 0xFF, 0x00, 0x88, 0xBC, 0x8F, 0xB4, 0x45, 0x34, 0xD7, 0xF7, 0xB6, 0xC5,
+	0x57, 0xEC, 0xD1, 0x44, 0x9B, 0x76, 0x59, 0xC7, 0x8C, 0x83, 0xC5, 0x7B, 0xAF, 0xFC, 0x14, 0x03,
+	0xFE, 0x08, 0x73, 0xFB, 0x3F, 0x7E, 0xC8, 0x7F, 0xF0, 0x4A, 0x4F, 0x09, 0xFE, 0xDF, 0x5E, 0x0E,
+	0xF8, 0xB5, 0xE3, 0x2D, 0x4B, 0xC4, 0x9E, 0x20, 0xD3, 0x7C, 0x37, 0x75, 0x71, 0xA4, 0x6A, 0x5F,
+	0x63, 0xFB, 0x0C, 0x32, 0x6A, 0x10, 0x24, 0xB2, 0x2C, 0x7E, 0x54, 0x28, 0xF8, 0x0C, 0xE4, 0x0D,
+	0xCC, 0x4E, 0x3A, 0x92, 0x79, 0xAD, 0x6F, 0xF8, 0x3B, 0xE3, 0xFE, 0x52, 0x53, 0xE0, 0x7F, 0xFB,
+	0x22, 0x3A, 0x5F, 0xFE, 0x9E, 0x75, 0x7A, 0xFB, 0x17, 0xFE, 0x0B, 0x63, 0xFF, 0x00, 0x2A, 0xDF,
+	0xFC, 0x32, 0xFF, 0x00, 0xB0, 0x37, 0x80, 0xFF, 0x00, 0xF4, 0x8A, 0x1A, 0x39, 0x62, 0x4F, 0x3C,
+	0xB9, 0x60, 0x7C, 0xC1, 0xFF, 0x00, 0x06, 0xB2, 0x7F, 0xC1, 0x3D, 0xBE, 0x1B, 0x7C, 0x72, 0xF8,
+	0x87, 0xA9, 0xFE, 0xDC, 0x5A, 0xCF, 0x8C, 0x35, 0xCB, 0x3F, 0x11, 0x7C, 0x25, 0xF1, 0x72, 0x5A,
+	0xE8, 0x9A, 0x3D, 0x9C, 0xB6, 0xEB, 0x67, 0x72, 0xB7, 0x3A, 0x6C, 0xB1, 0xB1, 0x9C, 0x34, 0x4D,
+	0x21, 0xC7, 0x9D, 0xB8, 0x10, 0xE3, 0x6E, 0xCE, 0x8D, 0x5F, 0x00, 0xFF, 0x00, 0xC1, 0x4B, 0xFF,
+	0x00, 0x6D, 0xE3, 0xFF, 0x00, 0x05, 0x12, 0xFD, 0xB0, 0xBC, 0x45, 0xFB, 0x5A, 0x8F, 0x85, 0xFF,
+	0x00, 0xF0, 0x87, 0x0F, 0x10, 0x5B, 0xD8, 0x5B, 0x7F, 0xC2, 0x3A, 0x75, 0x8F, 0xED, 0x1F, 0x2B,
+	0xEC, 0xD6, 0x50, 0xC1, 0x8F, 0x3F, 0xC8, 0x87, 0x76, 0xFF, 0x00, 0x2B, 0x76, 0xDF, 0x28, 0x6D,
+	0xF5, 0xAF, 0xD8, 0x0F, 0xF8, 0x33, 0xA3, 0xFE, 0x4D, 0xA7, 0xE3, 0x27, 0xFD, 0x8F, 0x1A, 0x77,
+	0xFE, 0x91, 0xD7, 0xE0, 0x18, 0xE9, 0x4B, 0xEC, 0xA2, 0xE2, 0xE5, 0x2A, 0xD2, 0xBF, 0x40, 0xC6,
+	0xDF, 0x97, 0xD3, 0xDF, 0x35, 0xF7, 0xF7, 0xFC, 0x1B, 0x21, 0xFF, 0x00, 0x29, 0x83, 0xF0, 0x0F,
+	0xFD, 0x80, 0x7C, 0x41, 0xFF, 0x00, 0xA6, 0xA9, 0xEB, 0xE0, 0x1A, 0xFB, 0xFB, 0xFE, 0x0D, 0x90,
+	0xFF, 0x00, 0x94, 0xC1, 0xF8, 0x07, 0xFE, 0xC0, 0x3E, 0x20, 0xFF, 0x00, 0xD3, 0x54, 0xF4, 0xA3,
+	0xF1, 0x15, 0x5B, 0xF8, 0x6C, 0x93, 0xFE, 0x0E, 0x74, 0xFF, 0x00, 0x94, 0xC2, 0x78, 0xF7, 0xFE,
+	0xC0, 0x7A, 0x0F, 0xFE, 0x9B, 0x6D, 0xEB, 0xF3, 0xF4, 0x74, 0xAF, 0xD0, 0x2F, 0xF8, 0x39, 0xD3,
+	0xFE, 0x53, 0x09, 0xE3, 0xDF, 0xFB, 0x01, 0xE8, 0x3F, 0xFA, 0x6D, 0xB7, 0xAF, 0xCF, 0xD1, 0xD2,
+	0xA6, 0x5F, 0x11, 0x54, 0xFF, 0x00, 0x83, 0x11, 0x46, 0x08, 0xC6, 0xE7, 0x66, 0xD8, 0xDB, 0xC4,
+	0x7D, 0x97, 0x15, 0xFB, 0xEB, 0xFF, 0x00, 0x07, 0x60, 0xE8, 0xBA, 0x75, 0xDF, 0xFC, 0x13, 0xF3,
+	0xE0, 0x66, 0xB3, 0x6F, 0xE6, 0x79, 0xD6, 0xFE, 0x30, 0x8A, 0xDE, 0xDF, 0x6F, 0xFC, 0xF3, 0x97,
+	0x4B, 0x93, 0x76, 0x7D, 0xF7, 0x47, 0x1D, 0x7E, 0x05, 0x1F, 0xBC, 0xDF, 0xE7, 0xF8, 0x2B, 0xF7,
+	0xEF, 0xFE, 0x0E, 0xB6, 0xFF, 0x00, 0x94, 0x6B, 0xFC, 0x10, 0xFF, 0x00, 0xB1, 0xF2, 0xC7, 0xFF,
+	0x00, 0x4C, 0xD7, 0x95, 0xA4, 0x7E, 0x16, 0x67, 0x3F, 0xE3, 0x44, 0xF9, 0x07, 0xFE, 0x09, 0x6F,
+	0xFF, 0x00, 0x04, 0x38, 0xFD, 0x9F, 0x3F, 0x6E, 0xEF, 0xF8, 0x27, 0x1F, 0x8C, 0xBF, 0x6C, 0xCF,
+	0x1F, 0x7C, 0x5B, 0xF1, 0xA6, 0x8F, 0xAF, 0x78, 0x77, 0x52, 0xD6, 0xE1, 0xB0, 0xD2, 0xF4, 0x16,
+	0xB3, 0xFB, 0x1C, 0x9F, 0x63, 0xB1, 0x8E, 0x78, 0xCB, 0x79, 0x96, 0xED, 0x26, 0x59, 0x9C, 0xEE,
+	0xC3, 0x8A, 0xF9, 0xEB, 0xFE, 0x08, 0xB5, 0xFF, 0x00, 0x04, 0xF3, 0xF8, 0x65, 0xFF, 0x00, 0x05,
+	0x2F, 0xFD, 0xB0, 0x2F, 0x3F, 0x67, 0x3F, 0x8A, 0x3E, 0x35, 0xD7, 0x34, 0x0D, 0x2E, 0xD7, 0xC1,
+	0xB7, 0xBA, 0xB5, 0xBE, 0xA1, 0xE1, 0xDF, 0x27, 0xCE, 0x33, 0x43, 0x3D, 0xBA, 0xAA, 0x9F, 0x3A,
+	0x39, 0x17, 0x1B, 0x6E, 0x3B, 0x00, 0x3D, 0xAB, 0xF5, 0x8F, 0xFE, 0x0D, 0xD0, 0xFF, 0x00, 0x94,
+	0x11, 0xFC, 0x52, 0xFF, 0x00, 0xB0, 0xE7, 0x8A, 0xFF, 0x00, 0xF4, 0xD5, 0x6D, 0x5F, 0x0C, 0x7F,
+	0xC1, 0xA6, 0x1F, 0xF2, 0x94, 0x3B, 0xEF, 0xFB, 0x24, 0xFA, 0xB7, 0xFE, 0x96, 0x69, 0xF5, 0x56,
+	0x8E, 0x9A, 0x6E, 0x4F, 0x34, 0xAD, 0x3D, 0x76, 0x3E, 0x60, 0xFF, 0x00, 0x82, 0x95, 0x7E, 0xC4,
+	0xBE, 0x03, 0xFD, 0x8B, 0x3F, 0xE0, 0xA4, 0x9E, 0x28, 0xFD, 0x8B, 0xBE, 0x1F, 0x78, 0x9F, 0x58,
+	0xD5, 0x74, 0x1D, 0x07, 0x52, 0xD0, 0xE1, 0xB3, 0xD5, 0x35, 0x6F, 0x27, 0xED, 0x72, 0x8B, 0xCD,
+	0x3E, 0xCE, 0xE4, 0xE7, 0xCA, 0x8D, 0x23, 0xF9, 0x1E, 0xE5, 0xB6, 0xE5, 0x08, 0xAF, 0xA6, 0x3F,
+	0xE0, 0xBA, 0x9F, 0xF0, 0x44, 0xEF, 0xD9, 0xFF, 0x00, 0xFE, 0x09, 0x5D, 0xF0, 0x9F, 0xC0, 0x7E,
+	0x3F, 0xF8, 0x3F, 0xF1, 0x57, 0xC6, 0x1E, 0x22, 0xB8, 0xF1, 0x67, 0x88, 0x2E, 0x74, 0xFB, 0xCB,
+	0x6F, 0x12, 0x9B, 0x4F, 0x2D, 0x15, 0x2D, 0xC4, 0x8A, 0x57, 0xC8, 0x82, 0x36, 0xCF, 0xD4, 0x93,
+	0x5C, 0x7F, 0xFC, 0x17, 0xC7, 0xFE, 0x53, 0xD7, 0xF1, 0x1B, 0xFE, 0xC3, 0x9E, 0x12, 0xFF, 0x00,
+	0xD3, 0x16, 0x91, 0x5F, 0xA0, 0x5F, 0xF0, 0x78, 0xB7, 0xFC, 0x9B, 0x67, 0xC1, 0xBF, 0xFB, 0x1E,
+	0xAF, 0x7F, 0xF4, 0x8D, 0x6A, 0x79, 0x16, 0xA8, 0x39, 0xA5, 0xEE, 0x1E, 0x45, 0xFF, 0x00, 0x04,
+	0x40, 0xFF, 0x00, 0x82, 0x7D, 0xFC, 0x18, 0xF8, 0x0B, 0xFB, 0x19, 0x58, 0xFF, 0x00, 0xC1, 0x76,
+	0x6E, 0x7C, 0x49, 0xE2, 0x8D, 0x5B, 0xC6, 0x1F, 0x0D, 0xFC, 0x2F, 0xE3, 0x5D, 0x6B, 0xFE, 0x10,
+	0x85, 0xBC, 0xB7, 0x87, 0x4D, 0xBC, 0x5B, 0x3B, 0x1D, 0x42, 0xD4, 0xC4, 0x5F, 0xEC, 0xF2, 0x4F,
+	0x1B, 0xBC, 0x20, 0x9D, 0xDB, 0xDC, 0x65, 0x87, 0xCA, 0xDF, 0x70, 0x79, 0x17, 0xEC, 0xEB, 0xE0,
+	0x5F, 0x85, 0x7F, 0xF0, 0x72, 0xBF, 0xFC, 0x15, 0xAF, 0xC7, 0x9E, 0x33, 0xF8, 0xC5, 0xA1, 0x78,
+	0x83, 0xE1, 0x7E, 0x9B, 0x2F, 0xC2, 0xE8, 0xF5, 0x98, 0xF4, 0xBF, 0x0C, 0xEB, 0x71, 0x6A, 0x93,
+	0x2C, 0xF6, 0x13, 0x69, 0xDA, 0x70, 0x43, 0x71, 0x3D, 0xAA, 0x2B, 0x86, 0x59, 0xE4, 0x6D, 0xBE,
+	0x4F, 0x1E, 0xB5, 0xF6, 0xA7, 0xFC, 0x13, 0x1F, 0xFE, 0x55, 0x4E, 0xF8, 0x8D, 0xFF, 0x00, 0x64,
+	0x9F, 0xE2, 0x57, 0xFE, 0x8B, 0xD4, 0xEB, 0xE3, 0xAF, 0xF8, 0x34, 0x23, 0xFE, 0x52, 0x51, 0xE3,
+	0x8F, 0xFB, 0x21, 0xFA, 0x97, 0xFE, 0x9E, 0x74, 0x5A, 0x17, 0xC4, 0x88, 0x72, 0x7E, 0xF4, 0xFA,
+	0x9F, 0x21, 0x7E, 0xDA, 0x7F, 0xB1, 0x2F, 0x80, 0x3F, 0x66, 0x7F, 0xF8, 0x29, 0xE6, 0xB5, 0xFB,
+	0x0F, 0x78, 0x5B, 0xC5, 0x3A, 0xC6, 0xA1, 0xE1, 0xBD, 0x37, 0xC6, 0x3A, 0x4E, 0x91, 0x16, 0xB5,
+	0xA9, 0xB4, 0x26, 0xF9, 0xA1, 0xBB, 0x8E, 0xD1, 0xA5, 0x27, 0xCA, 0x8D, 0x63, 0xC8, 0x32, 0xF1,
+	0x94, 0x22, 0xBE, 0x82, 0xFF, 0x00, 0x82, 0xEC, 0xFF, 0x00, 0xC1, 0x1A, 0x7E, 0x04, 0xFF, 0x00,
+	0xC1, 0x2A, 0xFC, 0x2B, 0xF0, 0xDF, 0x5E, 0xF8, 0x3B, 0xF1, 0x4F, 0xC5, 0xDE, 0x21, 0x9B, 0xC6,
+	0x7A, 0x96, 0xA5, 0x06, 0xA2, 0xBE, 0x25, 0x36, 0x9B, 0x6D, 0xD6, 0xDA, 0x3B, 0x69, 0x03, 0x47,
+	0xE4, 0x41, 0x1B, 0x65, 0xBC, 0xCE, 0x72, 0x49, 0xF7, 0xAC, 0x5F, 0xF8, 0x2B, 0x1F, 0xFC, 0xAC,
+	0x2F, 0xE2, 0xAF, 0xFB, 0x2A, 0x9E, 0x1A, 0xFF, 0x00, 0xD2, 0x7D, 0x3E, 0xBE, 0xE0, 0xFF, 0x00,
+	0x83, 0xC9, 0xBF, 0xE4, 0x9B, 0xFC, 0x05, 0xFF, 0x00, 0xB0, 0xEF, 0x88, 0x3F, 0xF4, 0x9A, 0xC6,
+	0x97, 0x2A, 0xD5, 0x15, 0xCF, 0x2F, 0x69, 0x15, 0xDC, 0xF9, 0x73, 0xE0, 0x27, 0xFC, 0x10, 0xE3,
+	0xE0, 0x07, 0xC4, 0xFF, 0x00, 0xF8, 0x22, 0x3E, 0xA1, 0xFF, 0x00, 0x05, 0x40, 0xD5, 0xBE, 0x2A,
+	0xF8, 0xBE, 0xDF, 0xC6, 0x16, 0x7E, 0x0D, 0xF1, 0x16, 0xB3, 0x6F, 0xA0, 0x5A, 0x35, 0xA1, 0xD3,
+	0x7C, 0xED, 0x36, 0xFA, 0xFA, 0xDE, 0x24, 0xF9, 0xA2, 0x79, 0x76, 0xB2, 0xDB, 0x21, 0x7F, 0x9C,
+	0x1D, 0xD5, 0xE5, 0xDF, 0xF0, 0x42, 0xEF, 0xF8, 0x25, 0x67, 0xC1, 0xBF, 0xF8, 0x2A, 0x77, 0xC5,
+	0x7F, 0x1E, 0x7C, 0x3B, 0xF8, 0xB5, 0xF1, 0x03, 0xC4, 0xDE, 0x1D, 0xB6, 0xF0, 0x9F, 0x87, 0xAD,
+	0x2F, 0xAC, 0x66, 0xF0, 0xDF, 0xD9, 0xFC, 0xC7, 0x69, 0x27, 0x28, 0x77, 0x7D, 0xA1, 0x25, 0x18,
+	0xFC, 0x2B, 0xF4, 0xBB, 0xF6, 0x38, 0xFF, 0x00, 0x95, 0x45, 0x35, 0xAF, 0xFB, 0x24, 0xFE, 0x3C,
+	0xFF, 0x00, 0xD3, 0xC6, 0xAF, 0x5F, 0x38, 0xFF, 0x00, 0xC1, 0x9D, 0xBF, 0xF2, 0x72, 0xDF, 0x19,
+	0x7F, 0xEC, 0x45, 0xB1, 0xFF, 0x00, 0xD2, 0xD6, 0xAB, 0xE5, 0x5C, 0xC8, 0x3D, 0xA4, 0xFD, 0x9C,
+	0xBC, 0x99, 0xF9, 0xF1, 0xF1, 0x53, 0xF6, 0x3D, 0xF0, 0x3F, 0x80, 0x7F, 0xE0, 0xA9, 0x1A, 0x87,
+	0xEC, 0x29, 0xA7, 0x78, 0x9B, 0x52, 0x9B, 0xC3, 0xB6, 0xBF, 0x19, 0x61, 0xF0, 0x7C, 0x7A, 0xB4,
+	0xCD, 0x1F, 0xDB, 0x0D, 0x93, 0xEA, 0x09, 0x6A, 0x64, 0xF9, 0x61, 0x10, 0xF9, 0x87, 0x78, 0x27,
+	0x80, 0x32, 0x4E, 0x00, 0x15, 0xEE, 0xDF, 0xF0, 0x5D, 0xAF, 0xF8, 0x24, 0xC7, 0xC1, 0x6F, 0xF8,
+	0x25, 0x47, 0x8B, 0x3E, 0x1A, 0xE8, 0x7F, 0x07, 0xFE, 0x24, 0xF8, 0xA3, 0x5F, 0x87, 0xC6, 0x9A,
+	0x7E, 0xA3, 0x73, 0xA8, 0x49, 0xE2, 0x4F, 0xB3, 0x6F, 0xB5, 0x6B, 0x69, 0x2D, 0xD0, 0x08, 0xFC,
+	0x88, 0xA3, 0x5E, 0x7C, 0xFE, 0x77, 0x13, 0xF5, 0x35, 0x8F, 0xFB, 0x49, 0x7F, 0xCA, 0xC5, 0x9A,
+	0xC7, 0xFD, 0x9D, 0x6D, 0xBF, 0xFE, 0x9E, 0xAD, 0xEB, 0xEC, 0x7F, 0xF8, 0x3C, 0x93, 0xFE, 0x4A,
+	0x57, 0xC0, 0x4F, 0xFB, 0x00, 0xEB, 0xFF, 0x00, 0xFA, 0x53, 0xA7, 0xD4, 0xF2, 0xE8, 0xCB, 0xE7,
+	0x97, 0xB4, 0x8A, 0xEE, 0x8F, 0x13, 0xF0, 0xC7, 0xFC, 0x10, 0xDB, 0xF6, 0x7B, 0xD7, 0x3F, 0xE0,
+	0x88, 0xD2, 0xFF, 0x00, 0xC1, 0x4E, 0x6E, 0x7E, 0x2A, 0xF8, 0xC1, 0x3C, 0x61, 0x1F, 0x82, 0xEF,
+	0x35, 0x74, 0xF0, 0xEA, 0xB5, 0x8F, 0xF6, 0x51, 0x92, 0x2B, 0xF9, 0x61, 0xF2, 0x0F, 0xFA, 0x3B,
+	0xC9, 0xE5, 0x36, 0xCD, 0xCD, 0x87, 0xFB, 0xDD, 0xEB, 0xCF, 0x3F, 0xE0, 0x84, 0x7F, 0xF0, 0x49,
+	0x4F, 0x83, 0x1F, 0xF0, 0x55, 0x8F, 0x15, 0x7C, 0x48, 0xD0, 0x3E, 0x31, 0xFC, 0x49, 0xF1, 0x36,
+	0x85, 0x0F, 0x83, 0x74, 0xDD, 0x36, 0x7B, 0x36, 0xF0, 0xFF, 0x00, 0x91, 0xE6, 0x5D, 0x35, 0xCC,
+	0x97, 0x51, 0x9F, 0x37, 0xED, 0x11, 0xC8, 0x30, 0x3C, 0x9E, 0x3E, 0x51, 0xF4, 0x15, 0xFA, 0x3D,
+	0xF0, 0xF7, 0xFE, 0x55, 0x17, 0xB8, 0xFF, 0x00, 0xB2, 0x53, 0xAA, 0x7F, 0xE9, 0xE2, 0x7A, 0xF0,
+	0xFF, 0x00, 0xF8, 0x33, 0x63, 0xFE, 0x4A, 0x57, 0xC7, 0xAF, 0xFB, 0x02, 0x78, 0x7B, 0xFF, 0x00,
+	0x47, 0x6A, 0x15, 0x7C, 0xAB, 0x99, 0x10, 0xA7, 0x37, 0x09, 0x6A, 0x7E, 0x76, 0xF8, 0x63, 0xF6,
+	0x28, 0xF0, 0x1E, 0xBD, 0xFF, 0x00, 0x05, 0x74, 0x9B, 0xFE, 0x09, 0xF3, 0x2F, 0x8A, 0x75, 0x7F,
+	0xF8, 0x46, 0xE3, 0xF8, 0xEB, 0x77, 0xE0, 0x94, 0xD6, 0x95, 0xA2, 0x17, 0xAD, 0x63, 0x16, 0xA5,
+	0x2D, 0x90, 0x95, 0xB6, 0xC6, 0xD0, 0xF9, 0xA4, 0x46, 0x19, 0xBE, 0x45, 0x1B, 0x89, 0xC2, 0x81,
+	0xC0, 0xF5, 0x5F, 0xF8, 0x2E, 0x9F, 0xFC, 0x12, 0xBF, 0xE0, 0xDF, 0xFC, 0x12, 0xB3, 0xE2, 0xAF,
+	0x80, 0xFC, 0x07, 0xF0, 0x83, 0xE2, 0x27, 0x8A, 0x3C, 0x45, 0x6D, 0xE2, 0x8F, 0x0D, 0xDC, 0xDF,
+	0xDE, 0x4D, 0xE2, 0x86, 0x80, 0xBA, 0x4B, 0x14, 0xE5, 0x17, 0x1F, 0x67, 0x86, 0x35, 0xE9, 0xEB,
+	0x5A, 0x7F, 0x0F, 0xBF, 0xE5, 0x66, 0xC9, 0xFF, 0x00, 0xEC, 0xF1, 0xF5, 0x4F, 0xFD, 0x48, 0x67,
+	0xAF, 0xA3, 0x7F, 0xE0, 0xF1, 0x8F, 0xF9, 0x39, 0x0F, 0x83, 0x7F, 0xF6, 0x21, 0xEA, 0x1F, 0xFA,
+	0x5A, 0xB5, 0x1C, 0xBE, 0xEB, 0x2E, 0x32, 0x94, 0xAA, 0x45, 0x5F, 0x74, 0x79, 0x8F, 0xC7, 0x6F,
+	0xF8, 0x21, 0xA7, 0xEC, 0xFB, 0xF0, 0xA7, 0xFE, 0x08, 0x97, 0xA7, 0xFF, 0x00, 0xC1, 0x4D, 0x34,
+	0x9F, 0x8B, 0x1E, 0x30, 0xB9, 0xF1, 0x75, 0xE7, 0x83, 0x7C, 0x39, 0xAB, 0xCB, 0xA2, 0x5E, 0x35,
+	0x9F, 0xF6, 0x7F, 0x9D, 0xA8, 0xDF, 0x5A, 0x5B, 0x3A, 0xF1, 0x10, 0x93, 0x6A, 0xC7, 0x75, 0x20,
+	0x5F, 0x98, 0x9C, 0x01, 0xC9, 0xEB, 0x5C, 0x5F, 0xFC, 0x10, 0x63, 0xFE, 0x09, 0x05, 0xF0, 0x47,
+	0xFE, 0x0A, 0xBA, 0x3E, 0x28, 0xB7, 0xC6, 0x9F, 0x89, 0x1E, 0x27, 0xD0, 0xBF, 0xE1, 0x06, 0xFE,
+	0xC3, 0x36, 0x23, 0xC3, 0xAD, 0x6D, 0x9B, 0x95, 0xBD, 0x6B, 0xFF, 0x00, 0x30, 0x4B, 0xE7, 0xC6,
+	0xED, 0x80, 0x6C, 0xA2, 0xC6, 0x2B, 0xF4, 0x4B, 0xF6, 0xC9, 0xCF, 0xFC, 0x42, 0x35, 0xA3, 0xFF,
+	0x00, 0xD9, 0x2B, 0xF0, 0x1F, 0xFE, 0x9E, 0xB4, 0x8A, 0xF2, 0x7F, 0xF8, 0x33, 0x27, 0xEE, 0xFE,
+	0xD1, 0xBF, 0xEE, 0x78, 0x3F, 0xFF, 0x00, 0x73, 0xD5, 0x56, 0x8F, 0x32, 0x23, 0xDA, 0x4F, 0xD9,
+	0xC9, 0xF6, 0x67, 0xE6, 0xA7, 0xC0, 0x1F, 0xD8, 0x9F, 0xC0, 0x3F, 0x15, 0xFF, 0x00, 0xE0, 0xAA,
+	0xD6, 0x7F, 0xB0, 0x67, 0x88, 0x7C, 0x5B, 0xAD, 0x45, 0xE1, 0xD9, 0xBE, 0x2B, 0x6A, 0x1E, 0x16,
+	0x97, 0x58, 0xB7, 0xF2, 0xFE, 0xDA, 0xF6, 0x76, 0xD7, 0x13, 0x46, 0xAE, 0xDF, 0xBB, 0x31, 0xEF,
+	0x3B, 0x01, 0x39, 0x50, 0x32, 0x4F, 0x03, 0xA5, 0x7A, 0x07, 0xFC, 0x17, 0x1F, 0xFE, 0x09, 0x8B,
+	0xF0, 0xAF, 0xFE, 0x09, 0x6B, 0xFB, 0x41, 0xF8, 0x43, 0xE0, 0xF7, 0xC1, 0xFF, 0x00, 0x1E, 0xF8,
+	0x93, 0xC4, 0x56, 0x5E, 0x22, 0xF0, 0x8A, 0xEA, 0xF3, 0x5D, 0x78, 0x91, 0xA0, 0x33, 0x47, 0x70,
+	0xD7, 0x93, 0x40, 0x14, 0x7D, 0x9E, 0x08, 0xD7, 0x6E, 0x22, 0xEE, 0x6B, 0xA7, 0xFD, 0x8B, 0xBF,
+	0xE5, 0x64, 0x7D, 0x37, 0xFE, 0xCE, 0x43, 0x5B, 0xFF, 0x00, 0xD2, 0xCB, 0xCA, 0xF7, 0x2F, 0xF8,
+	0x3C, 0x27, 0xFE, 0x4F, 0x77, 0xE1, 0x8F, 0xFD, 0x92, 0x9F, 0xFD, 0xC9, 0x5E, 0x54, 0xF2, 0xFB,
+	0xA5, 0xF3, 0x4B, 0xDA, 0xA5, 0x7E, 0x87, 0x17, 0xFB, 0x5B, 0x7F, 0xC1, 0x0D, 0x3F, 0x67, 0xAF,
+	0x80, 0x1F, 0xF0, 0x46, 0xDF, 0x0A, 0xFF, 0x00, 0xC1, 0x48, 0x7C, 0x29, 0xF1, 0x67, 0xC5, 0xD7,
+	0xDE, 0x28, 0xF1, 0x07, 0x83, 0xBC, 0x27, 0xAC, 0x5D, 0x68, 0x7A, 0x87, 0xD8, 0xFF, 0x00, 0xB3,
+	0xC4, 0xBA, 0xB2, 0xD9, 0x99, 0x11, 0x7C, 0xA8, 0x95, 0xF6, 0x23, 0x4E, 0x42, 0x6E, 0x76, 0x38,
+	0x03, 0x24, 0x9E, 0x4E, 0x6F, 0xFC, 0x10, 0xAB, 0xFE, 0x08, 0xA7, 0xF0, 0x0F, 0xFE, 0x0A, 0x9B,
+	0xF0, 0x97, 0xC7, 0x5F, 0x11, 0x7E, 0x2F, 0xFC, 0x58, 0xF1, 0x97, 0x87, 0xEE, 0xFC, 0x2B, 0xE2,
+	0x3B, 0x6B, 0x2D, 0x36, 0x3F, 0x0C, 0xB5, 0xA6, 0xD9, 0x83, 0xC1, 0xE6, 0x79, 0xB2, 0xFD, 0xA2,
+	0xDD, 0xDB, 0xCC, 0x52, 0x76, 0x8C, 0x3F, 0xDD, 0xAF, 0xBB, 0x7F, 0xE0, 0xA7, 0x3F, 0xF2, 0xAA,
+	0xA7, 0xC3, 0x8F, 0xFB, 0x25, 0x7F, 0x0C, 0xFF, 0x00, 0xF4, 0x5E, 0x97, 0x58, 0x5F, 0xF0, 0x67,
+	0x4F, 0xFC, 0x9B, 0x4F, 0xC6, 0x3F, 0xFB, 0x1E, 0x6C, 0x3F, 0xF4, 0x8A, 0xAA, 0xD1, 0xE6, 0x44,
+	0x7B, 0x49, 0x7B, 0x2B, 0xF9, 0x9F, 0x91, 0x3F, 0xF0, 0x4F, 0xFF, 0x00, 0xD8, 0xF3, 0xC0, 0xDF,
+	0xB5, 0xC7, 0xFC, 0x14, 0x4B, 0xC2, 0x3F, 0xB1, 0xAF, 0x8C, 0x3C, 0x4F, 0xAA, 0x69, 0x7A, 0x1E,
+	0xBD, 0xE2, 0x0B, 0xFD, 0x36, 0xE3, 0x53, 0xD2, 0xBC, 0x9F, 0xB5, 0x42, 0x90, 0x41, 0x73, 0x2A,
+	0xB2, 0x65, 0x5E, 0x3C, 0xB0, 0xB7, 0xE7, 0x2A, 0x3E, 0x82, 0xBB, 0x4F, 0xF8, 0x2D, 0x3F, 0xFC,
+	0x13, 0xD7, 0xE1, 0x8F, 0xFC, 0x13, 0x4B, 0xF6, 0xC4, 0xB3, 0xFD, 0x9C, 0xBE, 0x13, 0x78, 0xDB,
+	0x5C, 0xD7, 0x34, 0x9B, 0xAF, 0x06, 0xD8, 0xEB, 0x2D, 0xA8, 0xEB, 0xDE, 0x47, 0x9E, 0xB2, 0x4D,
+	0x35, 0xD4, 0x5B, 0x3F, 0xD1, 0xE1, 0x8D, 0x31, 0xFB, 0xBE, 0xF5, 0xD5, 0x7F, 0xC1, 0x12, 0xBF,
+	0xE5, 0x39, 0xFF, 0x00, 0x0C, 0x7F, 0xEC, 0x7A, 0xD6, 0x3F, 0xF4, 0x87, 0x51, 0xAF, 0x56, 0xFF,
+	0x00, 0x83, 0xB2, 0xBF, 0xE5, 0x28, 0xD6, 0x3F, 0xF6, 0x49, 0xF4, 0x8F, 0xFD, 0x2B, 0xBE, 0xA8,
+	0xE5, 0xF7, 0x59, 0xA7, 0x34, 0xBD, 0xB4, 0x75, 0xE8, 0x7E, 0x62, 0xAB, 0x16, 0x50, 0xCD, 0xD4,
+	0xF5, 0xE9, 0xFD, 0x38, 0xA2, 0x83, 0xD6, 0x8A, 0x83, 0x63, 0xE8, 0xCF, 0xF8, 0x25, 0xA7, 0xED,
+	0xFD, 0xFF, 0x00, 0x0E, 0xD1, 0xFD, 0xAC, 0x2C, 0xFF, 0x00, 0x69, 0xFF, 0x00, 0xF8, 0x54, 0xDF,
+	0xF0, 0x9A, 0x7D, 0x97, 0x41, 0xBF, 0xD3, 0xFF, 0x00, 0xB0, 0x3F, 0xB7, 0x3F, 0xB3, 0x77, 0xF9,
+	0xE8, 0x06, 0xFF, 0x00, 0x3F, 0xC9, 0x9F, 0xA6, 0x3E, 0xEE, 0xD1, 0xF4, 0x15, 0xCB, 0xFF, 0x00,
+	0xC1, 0x41, 0x3F, 0x6B, 0x2F, 0xF8, 0x6E, 0x8F, 0xDB, 0x0B, 0xC7, 0x1F, 0xB5, 0x80, 0xF0, 0x0F,
+	0xFC, 0x23, 0x5F, 0xF0, 0x99, 0x5E, 0x5B, 0x5D, 0xFF, 0x00, 0xC2, 0x3B, 0xFD, 0xAD, 0xF6, 0xEF,
+	0xB3, 0x79, 0x56, 0xD1, 0x5B, 0x79, 0x7E, 0x77, 0x93, 0x07, 0x9B, 0xBF, 0xC8, 0xDD, 0x8D, 0x87,
+	0x15, 0xE3, 0x74, 0x51, 0xD2, 0xC4, 0xA8, 0xC7, 0x9A, 0xE0, 0x7A, 0xFF, 0x00, 0xAC, 0xDD, 0xFE,
+	0xD7, 0xAF, 0xBF, 0x41, 0xFC, 0x85, 0x14, 0x51, 0x41, 0x41, 0x5F, 0xAA, 0xDF, 0xF0, 0x6A, 0xFF,
+	0x00, 0xC6, 0x4F, 0x85, 0xDF, 0x00, 0x7E, 0x36, 0xFC, 0x59, 0xF8, 0x91, 0xF1, 0x2E, 0x4B, 0xC8,
+	0x56, 0x4F, 0x0B, 0xE9, 0xFA, 0x75, 0x9B, 0x59, 0x69, 0xBE, 0x6E, 0x4C, 0x97, 0x0D, 0x29, 0xCB,
+	0x76, 0xFF, 0x00, 0x51, 0x5F, 0x95, 0x35, 0xFA, 0x0D, 0xFF, 0x00, 0x04, 0x60, 0xD0, 0xBE, 0xC7,
+	0xF0, 0xF7, 0xC7, 0x1E, 0x2E, 0xFF, 0x00, 0x9F, 0xCD, 0x5E, 0xD2, 0xD7, 0xFF, 0x00, 0x01, 0xE2,
+	0x91, 0xFF, 0x00, 0xF6, 0xE6, 0xAE, 0x9E, 0xE6, 0x38, 0x8D, 0x29, 0x9F, 0xBF, 0xC9, 0xFF, 0x00,
+	0x05, 0x40, 0xFD, 0x95, 0x95, 0x02, 0xFF, 0x00, 0x6C, 0xEB, 0x9C, 0x0F, 0xFA, 0x03, 0xB9, 0xAF,
+	0x5E, 0xF8, 0x47, 0xF1, 0x73, 0xC2, 0x7F, 0x1B, 0x3C, 0x0F, 0x0F, 0xC4, 0x6F, 0x01, 0xDC, 0xCD,
+	0x26, 0x9F, 0x74, 0xD2, 0xA4, 0x3F, 0x69, 0x83, 0xCB, 0x7D, 0xD1, 0xB1, 0x56, 0xE0, 0xF4, 0xE9,
+	0x5F, 0x8F, 0x4E, 0x36, 0xB1, 0x5F, 0x43, 0x5F, 0xA6, 0x7F, 0xF0, 0x4D, 0x5F, 0xF9, 0x34, 0x7D,
+	0x0F, 0xFE, 0xBF, 0xAF, 0xFF, 0x00, 0xF4, 0xA5, 0xAB, 0xA4, 0xF3, 0x49, 0x3E, 0x38, 0xFF, 0x00,
+	0xC1, 0x40, 0xBE, 0x09, 0xFE, 0xCF, 0x5F, 0x10, 0xA6, 0xF8, 0x6F, 0xE3, 0xBD, 0x1B, 0xC4, 0x13,
+	0x6A, 0x16, 0xF1, 0xA4, 0xF2, 0x36, 0x9F, 0x67, 0x04, 0x91, 0xF9, 0x6E, 0x3E, 0x53, 0xCC, 0xE0,
+	0xE7, 0x18, 0xEA, 0x05, 0x72, 0x2B, 0xFF, 0x00, 0x05, 0x6F, 0xFD, 0x99, 0x91, 0x42, 0x37, 0x87,
+	0x3C, 0x67, 0x91, 0xC1, 0xDD, 0xA5, 0xDB, 0xE7, 0xF1, 0xFF, 0x00, 0x49, 0xAF, 0x98, 0xFF, 0x00,
+	0xE0, 0xA8, 0xDF, 0xF2, 0x77, 0x7A, 0xA7, 0xFD, 0x82, 0x74, 0xFF, 0x00, 0xFD, 0x14, 0x2B, 0xE7,
+	0x9A, 0x0E, 0xC8, 0xD0, 0x84, 0xA2, 0x99, 0xFA, 0x45, 0xFF, 0x00, 0x0F, 0x71, 0xFD, 0x99, 0x7F,
+	0xE8, 0x5B, 0xF1, 0x97, 0xFE, 0x0A, 0xED, 0xFF, 0x00, 0xF9, 0x26, 0x8F, 0xF8, 0x7B, 0x8F, 0xEC,
+	0xCB, 0xFF, 0x00, 0x42, 0xDF, 0x8C, 0xBF, 0xF0, 0x57, 0x6F, 0xFF, 0x00, 0xC9, 0x35, 0xF9, 0xBB,
+	0x45, 0x05, 0x7B, 0x08, 0x9F, 0xA4, 0x5F, 0xF0, 0xF7, 0x1F, 0xD9, 0x90, 0xF5, 0xF0, 0xDF, 0x8C,
+	0x7F, 0xF0, 0x57, 0x6F, 0xFF, 0x00, 0xC9, 0x35, 0xF4, 0x8F, 0x81, 0xBC, 0x5D, 0xA6, 0x7C, 0x40,
+	0xF0, 0x4E, 0x8F, 0xE3, 0xCD, 0x12, 0x39, 0xA3, 0xB3, 0xD6, 0xF4, 0xBB, 0x7B, 0xFB, 0x44, 0xB8,
+	0x40, 0xB2, 0x2C, 0x53, 0x46, 0xB2, 0x28, 0x60, 0x09, 0x01, 0xB6, 0xB0, 0xC8, 0x04, 0x8C, 0xF7,
+	0x35, 0xF8, 0x99, 0x5F, 0xB1, 0xFF, 0x00, 0xB3, 0x0F, 0xFC, 0x9B, 0x57, 0xC3, 0xCF, 0xFB, 0x11,
+	0xB4, 0x9F, 0xFD, 0x23, 0x8A, 0x83, 0x1A, 0xF4, 0xA3, 0x14, 0x8E, 0x23, 0xE2, 0x2F, 0xFC, 0x14,
+	0x0B, 0xF6, 0x73, 0xF8, 0x61, 0xE3, 0x4D, 0x4B, 0xC0, 0x3E, 0x2D, 0xD4, 0x75, 0x45, 0xD4, 0x34,
+	0xCB, 0xA1, 0x6F, 0x7A, 0xB0, 0x69, 0x32, 0x32, 0x86, 0xF6, 0x23, 0xA8, 0xCF, 0x7E, 0xF5, 0x8E,
+	0x3F, 0xE0, 0xA8, 0x5F, 0xB2, 0xB1, 0x19, 0x3A, 0xC6, 0xB9, 0xFF, 0x00, 0x82, 0x69, 0x2B, 0xE2,
+	0x9F, 0xDB, 0x4F, 0xFE, 0x4E, 0xBB, 0xC6, 0xDF, 0xF6, 0x1C, 0x3F, 0xFA, 0x0A, 0xD7, 0x96, 0x27,
+	0xDC, 0x1F, 0x4A, 0x0E, 0x73, 0xF4, 0xA7, 0xFE, 0x1E, 0x85, 0xFB, 0x2B, 0x7F, 0xD0, 0x67, 0x5C,
+	0xFF, 0x00, 0xC1, 0x3B, 0xD1, 0xFF, 0x00, 0x0F, 0x42, 0xFD, 0x95, 0xBF, 0xE8, 0x33, 0xAE, 0x7F,
+	0xE0, 0x9D, 0xEB, 0xF3, 0x5E, 0x8A, 0x00, 0xFD, 0x28, 0xFF, 0x00, 0x87, 0xA1, 0x7E, 0xCA, 0xDF,
+	0xF4, 0x19, 0xD7, 0x3F, 0xF0, 0x4E, 0xF5, 0xE8, 0x7F, 0x01, 0x3F, 0x68, 0x0F, 0x87, 0xBF, 0xB4,
+	0x4C, 0x7A, 0xC7, 0x8A, 0x3E, 0x1B, 0x5C, 0xDD, 0x4D, 0x6F, 0x66, 0xD6, 0xF6, 0xD3, 0x1B, 0xAB,
+	0x73, 0x0B, 0x6E, 0xF9, 0xDB, 0x1E, 0xBD, 0xEB, 0xF2, 0x52, 0xBE, 0xF4, 0xFF, 0x00, 0x82, 0x44,
+	0x06, 0x3F, 0x0C, 0xBC, 0x64, 0x14, 0xE0, 0xFF, 0x00, 0x6E, 0x43, 0xB4, 0xE3, 0xA1, 0xF2, 0x7A,
+	0xD0, 0x07, 0xAC, 0x7C, 0x5D, 0xFD, 0xB2, 0x3E, 0x0B, 0xFE, 0xCF, 0x3E, 0x39, 0x9B, 0xC1, 0x3F,
+	0x11, 0xAF, 0xF5, 0x18, 0xEF, 0xA6, 0x8A, 0x3B, 0xC5, 0x16, 0x3A, 0x79, 0x91, 0x7C, 0xB7, 0x52,
+	0xA3, 0x24, 0x7F, 0xB4, 0x8D, 0x5C, 0xDF, 0xFC, 0x3D, 0x0B, 0xF6, 0x56, 0xFF, 0x00, 0xA0, 0xCE,
+	0xB9, 0xFF, 0x00, 0x82, 0x77, 0xAF, 0x9A, 0xBF, 0xE0, 0xAA, 0x3F, 0xF2, 0x73, 0x36, 0xFF, 0x00,
+	0xF6, 0x2C, 0x5A, 0xFF, 0x00, 0xE8, 0x72, 0xD7, 0xCD, 0x94, 0x01, 0xFA, 0x51, 0xFF, 0x00, 0x0F,
+	0x42, 0xFD, 0x95, 0xBF, 0xE8, 0x33, 0xAE, 0x7F, 0xE0, 0x9D, 0xE8, 0xFF, 0x00, 0x87, 0xA1, 0x7E,
+	0xCA, 0xDF, 0xF4, 0x19, 0xD7, 0x3F, 0xF0, 0x4E, 0xF5, 0xF9, 0xAF, 0x45, 0x00, 0x7E, 0x94, 0x7F,
+	0xC3, 0xCF, 0xFF, 0x00, 0x65, 0x57, 0xF9, 0x3F, 0xB6, 0x35, 0xBF, 0x9B, 0x8F, 0xF9, 0x03, 0x3D,
+	0x7A, 0x37, 0xC0, 0x5F, 0xDA, 0x4F, 0xE1, 0x9F, 0xED, 0x1D, 0xA7, 0xEA, 0x97, 0xFF, 0x00, 0x0C,
+	0x6F, 0x2F, 0x27, 0x8F, 0x4B, 0x92, 0x15, 0xBA, 0x37, 0x96, 0xE6, 0x13, 0x99, 0x01, 0x65, 0x03,
+	0xF0, 0x53, 0x5F, 0x92, 0x3D, 0xBF, 0x0A, 0xFB, 0x9B, 0xFE, 0x09, 0x06, 0x18, 0xF8, 0x6B, 0xC7,
+	0xC1, 0x4E, 0x0F, 0xF6, 0x85, 0x8E, 0xD3, 0x8E, 0x87, 0xCB, 0x9B, 0x9A, 0x00, 0xF6, 0x6F, 0x8B,
+	0xBF, 0xB6, 0x47, 0xC1, 0x7F, 0xD9, 0xE7, 0xC7, 0x33, 0x78, 0x27, 0xE2, 0x35, 0xFE, 0xA3, 0x1D,
+	0xF4, 0xD1, 0x47, 0x78, 0xA2, 0xC7, 0x4F, 0x32, 0x2F, 0x96, 0xEA, 0x54, 0x64, 0x8F, 0xF6, 0x91,
+	0xAB, 0x9B, 0xFF, 0x00, 0x87, 0xA1, 0x7E, 0xCA, 0xDF, 0xF4, 0x19, 0xD7, 0x3F, 0xF0, 0x4E, 0xF5,
+	0xF3, 0x57, 0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B, 0x5F, 0xFD, 0x0E, 0x5A,
+	0xF9, 0xB2, 0x80, 0x3F, 0x4A, 0x3F, 0xE1, 0xE8, 0x5F, 0xB2, 0xB7, 0xFD, 0x06, 0x75, 0xCF, 0xFC,
+	0x13, 0xBD, 0x1F, 0xF0, 0xF4, 0x2F, 0xD9, 0x5B, 0xFE, 0x83, 0x3A, 0xE7, 0xFE, 0x09, 0xDE, 0xBF,
+	0x35, 0xE8, 0xA0, 0x0F, 0xD2, 0x8F, 0xF8, 0x79, 0xFF, 0x00, 0xEC, 0xAA, 0xFF, 0x00, 0x27, 0xF6,
+	0xC6, 0xB7, 0xF3, 0x71, 0xFF, 0x00, 0x20, 0x67, 0xAF, 0x44, 0xF8, 0x11, 0xFB, 0x4A, 0xFC, 0x30,
+	0xFD, 0xA3, 0xAD, 0x35, 0x1B, 0xDF, 0x86, 0xB7, 0xB7, 0x93, 0x43, 0xA6, 0x49, 0x12, 0xDE, 0x1B,
+	0xCB, 0x33, 0x19, 0x06, 0x45, 0x25, 0x71, 0xF8, 0x03, 0x5F, 0x92, 0x7D, 0xBF, 0x0A, 0xFB, 0x93,
+	0xFE, 0x09, 0x0D, 0xFF, 0x00, 0x22, 0xDF, 0x8F, 0x7F, 0xEC, 0x21, 0x63, 0xFF, 0x00, 0xA2, 0xE6,
+	0xA5, 0x2D, 0x80, 0xFB, 0x2A, 0xC8, 0x83, 0x16, 0x57, 0x6F, 0xDE, 0x3F, 0x77, 0xA6, 0x7B, 0xFE,
+	0xB9, 0xA9, 0xA9, 0xB0, 0x7F, 0xAA, 0x5A, 0x75, 0x30, 0xD7, 0xA8, 0x50, 0x7A, 0x51, 0x41, 0xE9,
+	0x40, 0x1F, 0x0A, 0x7F, 0xC1, 0x5F, 0x7F, 0xE4, 0x64, 0xF0, 0x3F, 0xFD, 0x79, 0x5F, 0x7F, 0xE8,
+	0xC8, 0xEB, 0xE3, 0x6A, 0xFB, 0x27, 0xFE, 0x0A, 0xFB, 0xFF, 0x00, 0x23, 0x27, 0x81, 0xFF, 0x00,
+	0xEB, 0xCA, 0xFB, 0xFF, 0x00, 0x46, 0x47, 0x5F, 0x1B, 0x50, 0x01, 0x45, 0x14, 0x50, 0x00, 0x3A,
+	0xD7, 0xD5, 0xFF, 0x00, 0xF0, 0x49, 0x1F, 0xF9, 0x2D, 0x3E, 0x26, 0xFF, 0x00, 0xB1, 0x51, 0x7F,
+	0xF4, 0xA6, 0x2A, 0xF9, 0x40, 0x75, 0xAF, 0xAB, 0xFF, 0x00, 0xE0, 0x92, 0x3F, 0xF2, 0x5A, 0x7C,
+	0x4D, 0xFF, 0x00, 0x62, 0xA2, 0xFF, 0x00, 0xE9, 0x4C, 0x54, 0x01, 0xEB, 0x3F, 0xF0, 0x56, 0x5F,
+	0xF9, 0x37, 0x7D, 0x0F, 0xFE, 0xC7, 0x28, 0x7F, 0xF4, 0x96, 0xE6, 0xBF, 0x3D, 0xEB, 0xF4, 0x23,
+	0xFE, 0x0A, 0xCB, 0xFF, 0x00, 0x26, 0xEF, 0xA1, 0xFF, 0x00, 0xD8, 0xE5, 0x0F, 0xFE, 0x92, 0xDC,
+	0xD7, 0xE7, 0xBD, 0x4C, 0x7A, 0xFF, 0x00, 0x5D, 0x0A, 0x97, 0x40, 0xA2, 0x8A, 0x2A, 0x89, 0x0A,
+	0xF7, 0xAF, 0xF8, 0x26, 0xC7, 0xFC, 0x9D, 0xCE, 0x83, 0xFF, 0x00, 0x60, 0xFD, 0x43, 0xFF, 0x00,
+	0x49, 0xDE, 0xBC, 0x16, 0xBD, 0xEB, 0xFE, 0x09, 0xB1, 0xFF, 0x00, 0x27, 0x73, 0xA0, 0xFF, 0x00,
+	0xD8, 0x3F, 0x50, 0xFF, 0x00, 0xD2, 0x77, 0xA0, 0x0F, 0xB1, 0x3F, 0xE0, 0xA2, 0x9F, 0xF2, 0x67,
+	0x7E, 0x2D, 0xFF, 0x00, 0xAE, 0x96, 0x3F, 0xFA, 0x5B, 0x05, 0x7E, 0x60, 0xD7, 0xE9, 0xF7, 0xFC,
+	0x14, 0x53, 0xFE, 0x4C, 0xEF, 0xC5, 0xBF, 0xF5, 0xD2, 0xC7, 0xFF, 0x00, 0x4B, 0x60, 0xAF, 0xCC,
+	0x1A, 0x98, 0xFF, 0x00, 0x5F, 0x72, 0x29, 0xEC, 0xBD, 0x02, 0x8A, 0x28, 0xAA, 0x24, 0x2B, 0xD1,
+	0x3F, 0x64, 0xAF, 0xF9, 0x39, 0xCF, 0x00, 0xFF, 0x00, 0xD8, 0xD5, 0x69, 0xFF, 0x00, 0xA1, 0x0A,
+	0xF3, 0xBA, 0xF4, 0x4F, 0xD9, 0x2B, 0xFE, 0x4E, 0x73, 0xC0, 0x3F, 0xF6, 0x35, 0x5A, 0x7F, 0xE8,
+	0x42, 0x80, 0x3F, 0x4B, 0x3F, 0x6A, 0x4F, 0xF9, 0x36, 0x8F, 0x88, 0x9F, 0xF6, 0x24, 0xEA, 0x7F,
+	0xFA, 0x4B, 0x25, 0x7E, 0x35, 0xD7, 0xEC, 0xA7, 0xED, 0x49, 0xFF, 0x00, 0x26, 0xD1, 0xF1, 0x13,
+	0xFE, 0xC4, 0x9D, 0x4F, 0xFF, 0x00, 0x49, 0x64, 0xAF, 0xC6, 0xBA, 0xFC, 0xF7, 0x8C, 0x3F, 0xDE,
+	0x28, 0xFF, 0x00, 0x85, 0xFE, 0x68, 0xFE, 0x92, 0xF0, 0x2F, 0xFE, 0x45, 0x78, 0xCF, 0xF1, 0xC7,
+	0xFF, 0x00, 0x49, 0x61, 0x45, 0x14, 0x57, 0xC6, 0x9F, 0xBB, 0x05, 0x7D, 0x0F, 0xFF, 0x00, 0x04,
+	0xBC, 0xFF, 0x00, 0x93, 0xBA, 0xD2, 0x7F, 0xEC, 0x15, 0x7D, 0xFF, 0x00, 0xA2, 0x8D, 0x7C, 0xF1,
+	0x5F, 0x43, 0xFF, 0x00, 0xC1, 0x2F, 0x3F, 0xE4, 0xEE, 0xB4, 0x9F, 0xFB, 0x05, 0x5F, 0x7F, 0xE8,
+	0xA3, 0x5E, 0x96, 0x4F, 0xFF, 0x00, 0x23, 0x2A, 0x5F, 0xE2, 0x47, 0xC9, 0xF1, 0xD7, 0xFC, 0x91,
+	0xF8, 0xDF, 0xFA, 0xF6, 0xFF, 0x00, 0x43, 0xED, 0x1F, 0xF8, 0x29, 0x4F, 0xFC, 0x9A, 0x4E, 0xB9,
+	0xFF, 0x00, 0x5F, 0x96, 0x3F, 0xFA, 0x50, 0xB5, 0xF9, 0x97, 0x5F, 0xA6, 0x9F, 0xF0, 0x52, 0x9F,
+	0xF9, 0x34, 0x9D, 0x73, 0xFE, 0xBF, 0x2C, 0x7F, 0xF4, 0xA1, 0x6B, 0xF3, 0x2E, 0xBF, 0x62, 0x3F,
+	0x88, 0xCF, 0x2B, 0xFD, 0xB7, 0xFC, 0x2C, 0xDE, 0x30, 0xFD, 0x92, 0xBC, 0x7D, 0xA2, 0xF9, 0x5F,
+	0xEA, 0xF4, 0x09, 0x2E, 0xFF, 0x00, 0xF0, 0x1F, 0x17, 0x3F, 0xFB, 0x4A, 0xBF, 0x1D, 0xC3, 0x16,
+	0xF9, 0x88, 0xEB, 0x5F, 0xB9, 0xBE, 0x2A, 0xD0, 0x6C, 0xFC, 0x59, 0xE1, 0x7D, 0x43, 0xC2, 0xF7,
+	0xA3, 0xFD, 0x1F, 0x52, 0xB3, 0x96, 0xD6, 0x6F, 0xF6, 0x95, 0x91, 0xC3, 0x8F, 0xC9, 0x96, 0xBF,
+	0x0E, 0x35, 0x0D, 0x3E, 0xF3, 0x48, 0xBF, 0x9B, 0x4A, 0xD4, 0x62, 0xD9, 0x71, 0x6B, 0x33, 0x45,
+	0x3A, 0x7F, 0x75, 0xD4, 0xE0, 0x8F, 0xCC, 0x56, 0x35, 0x97, 0xBC, 0x76, 0xE1, 0x76, 0x68, 0x86,
+	0x8A, 0x28, 0xAC, 0x4E, 0xB0, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA1, 0x7A, 0x9F,
+	0xC3, 0xF9, 0x1A, 0x28, 0x5E, 0xA7, 0xF0, 0xFE, 0x46, 0xA9, 0x7C, 0x48, 0x1E, 0xCC, 0xFE, 0x86,
+	0x3F, 0xE0, 0xF0, 0x4F, 0xF9, 0x32, 0x0F, 0x86, 0x3F, 0xF6, 0x56, 0x13, 0xFF, 0x00, 0x4D, 0x97,
+	0xF4, 0xFF, 0x00, 0xF8, 0x22, 0x57, 0xFC, 0xAB, 0x79, 0xF1, 0x33, 0xFE, 0xC0, 0x1E, 0x3B, 0xFF,
+	0x00, 0xD2, 0x29, 0xA9, 0x9F, 0xF0, 0x78, 0x27, 0xFC, 0x99, 0x07, 0xC3, 0x1F, 0xFB, 0x2B, 0x09,
+	0xFF, 0x00, 0xA6, 0xCB, 0xFA, 0x7F, 0xFC, 0x11, 0x2B, 0xFE, 0x55, 0xBC, 0xF8, 0x99, 0xFF, 0x00,
+	0x60, 0x0F, 0x1D, 0xFF, 0x00, 0xE9, 0x14, 0xD5, 0xA3, 0xFE, 0x21, 0xC6, 0xFF, 0x00, 0xDD, 0xFE,
+	0x67, 0xC7, 0x1F, 0xF0, 0x68, 0x2F, 0xFC, 0xA4, 0x9F, 0xC6, 0xDF, 0xF6, 0x43, 0xF5, 0x2F, 0xFD,
+	0x3C, 0x68, 0xB5, 0xE5, 0x9F, 0xF0, 0x56, 0x4F, 0xF9, 0x58, 0x63, 0xC5, 0x7F, 0xF6, 0x55, 0x7C,
+	0x35, 0xFF, 0x00, 0xA4, 0xFA, 0x7D, 0x7A, 0x9F, 0xFC, 0x1A, 0x0B, 0xFF, 0x00, 0x29, 0x27, 0xF1,
+	0xB7, 0xFD, 0x90, 0xFD, 0x4B, 0xFF, 0x00, 0x4F, 0x1A, 0x2D, 0x79, 0x67, 0xFC, 0x15, 0x93, 0xFE,
+	0x56, 0x18, 0xF1, 0x5F, 0xFD, 0x95, 0x5F, 0x0D, 0x7F, 0xE9, 0x3E, 0x9F, 0x53, 0xFF, 0x00, 0x2E,
+	0xD1, 0x5F, 0xF2, 0xFA, 0x5E, 0x87, 0xDB, 0xFF, 0x00, 0xF0, 0x79, 0x2F, 0xFC, 0x93, 0x5F, 0x80,
+	0xBF, 0xF6, 0x1E, 0xF1, 0x07, 0xFE, 0x93, 0x58, 0xD7, 0x77, 0xFF, 0x00, 0x04, 0xC9, 0xFF, 0x00,
+	0x95, 0x54, 0x7E, 0x23, 0xFF, 0x00, 0xD9, 0x28, 0xF8, 0x95, 0xFF, 0x00, 0xA2, 0xF5, 0x4A, 0xE1,
+	0x3F, 0xE0, 0xF2, 0x5F, 0xF9, 0x26, 0xBF, 0x01, 0x7F, 0xEC, 0x3D, 0xE2, 0x0F, 0xFD, 0x26, 0xB1,
+	0xAE, 0xEF, 0xFE, 0x09, 0x93, 0xFF, 0x00, 0x2A, 0xA8, 0xFC, 0x47, 0xFF, 0x00, 0xB2, 0x51, 0xF1,
+	0x2B, 0xFF, 0x00, 0x45, 0xEA, 0x95, 0x4B, 0xE2, 0x66, 0x6B, 0xF8, 0x2B, 0xD4, 0xF9, 0x4B, 0xFE,
+	0x0C, 0xFC, 0xFF, 0x00, 0x93, 0xE2, 0xF8, 0x9D, 0xFF, 0x00, 0x64, 0xAF, 0xFF, 0x00, 0x72, 0x96,
+	0x75, 0xE2, 0x1F, 0xB6, 0x8F, 0xFC, 0xAC, 0x8D, 0xAA, 0x7F, 0xD9, 0xC6, 0x68, 0x7F, 0xFA, 0x5D,
+	0x67, 0x5E, 0xDF, 0xFF, 0x00, 0x06, 0x7E, 0x7F, 0xC9, 0xF1, 0x7C, 0x4E, 0xFF, 0x00, 0xB2, 0x57,
+	0xFF, 0x00, 0xB9, 0x4B, 0x3A, 0xF1, 0x0F, 0xDB, 0x47, 0xFE, 0x56, 0x46, 0xD5, 0x3F, 0xEC, 0xE3,
+	0x34, 0x3F, 0xFD, 0x2E, 0xB3, 0xAC, 0xDF, 0xF0, 0xE3, 0xEA, 0x69, 0xFF, 0x00, 0x2F, 0xA5, 0xE8,
+	0x7D, 0x8D, 0xFF, 0x00, 0x07, 0x9A, 0xFD, 0xEF, 0xD9, 0xBF, 0xFD, 0xDF, 0x18, 0x7F, 0x3D, 0x12,
+	0xBD, 0x53, 0xE1, 0xEF, 0xFC, 0xAA, 0x2F, 0x71, 0xFF, 0x00, 0x64, 0xA7, 0x54, 0xFF, 0x00, 0xD3,
+	0xC4, 0xF5, 0xE5, 0x7F, 0xF0, 0x79, 0xAF, 0xDE, 0xFD, 0x9B, 0xFF, 0x00, 0xDD, 0xF1, 0x87, 0xF3,
+	0xD1, 0x2B, 0xD5, 0x3E, 0x1E, 0xFF, 0x00, 0xCA, 0xA2, 0xF7, 0x1F, 0xF6, 0x4A, 0x75, 0x4F, 0xFD,
+	0x3C, 0x4F, 0x5B, 0x75, 0x66, 0x6B, 0xF8, 0x71, 0xF5, 0x3E, 0x70, 0xFF, 0x00, 0x83, 0x3A, 0xBF,
+	0xE4, 0xE4, 0xFE, 0x32, 0x7F, 0xD8, 0x8B, 0x63, 0xFF, 0x00, 0xA5, 0xAD, 0x5F, 0x2B, 0xCB, 0xFF,
+	0x00, 0x2B, 0x26, 0xFF, 0x00, 0xDD, 0xF2, 0x2F, 0xFE, 0xA6, 0x22, 0xBE, 0xA8, 0xFF, 0x00, 0x83,
+	0x3A, 0xBF, 0xE4, 0xE4, 0xFE, 0x32, 0x7F, 0xD8, 0x8B, 0x63, 0xFF, 0x00, 0xA5, 0xAD, 0x5F, 0x2B,
+	0xCB, 0xFF, 0x00, 0x2B, 0x26, 0xFF, 0x00, 0xDD, 0xF2, 0x2F, 0xFE, 0xA6, 0x22, 0xB1, 0x7F, 0xC3,
+	0x8F, 0xA9, 0xA7, 0xFC, 0xBC, 0x97, 0xA1, 0xF6, 0x47, 0xFC, 0x1E, 0x47, 0xFF, 0x00, 0x25, 0x23,
+	0xE0, 0x1F, 0xFD, 0x80, 0x35, 0xEF, 0xFD, 0x29, 0xD3, 0xEB, 0xDB, 0xFE, 0x22, 0xFF, 0x00, 0xCA,
+	0xA2, 0x70, 0xFF, 0x00, 0xD9, 0x2A, 0xD3, 0x3F, 0xF4, 0xF1, 0x05, 0x78, 0x87, 0xFC, 0x1E, 0x47,
+	0xFF, 0x00, 0x25, 0x23, 0xE0, 0x1F, 0xFD, 0x80, 0x35, 0xEF, 0xFD, 0x29, 0xD3, 0xEB, 0xDB, 0xFE,
+	0x22, 0xFF, 0x00, 0xCA, 0xA2, 0x70, 0xFF, 0x00, 0xD9, 0x2A, 0xD3, 0x3F, 0xF4, 0xF1, 0x05, 0x69,
+	0xD5, 0x92, 0xFF, 0x00, 0x83, 0x0F, 0x53, 0xCA, 0xFF, 0x00, 0xE0, 0xCD, 0x0F, 0xF5, 0x9F, 0xB4,
+	0x77, 0xD3, 0xC1, 0xFF, 0x00, 0xCF, 0x5E, 0xAF, 0x8E, 0xBF, 0x62, 0xFF, 0x00, 0xF9, 0x59, 0x17,
+	0x4D, 0xFF, 0x00, 0xB3, 0x90, 0xD6, 0xFF, 0x00, 0xF4, 0xB2, 0xF6, 0xBE, 0xC5, 0xFF, 0x00, 0x83,
+	0x34, 0x3F, 0xD6, 0x7E, 0xD1, 0xDF, 0x4F, 0x07, 0xFF, 0x00, 0x3D, 0x7A, 0xBE, 0x3A, 0xFD, 0x8B,
+	0xFF, 0x00, 0xE5, 0x64, 0x5D, 0x37, 0xFE, 0xCE, 0x43, 0x5B, 0xFF, 0x00, 0xD2, 0xCB, 0xDA, 0x5F,
+	0x65, 0x14, 0xBE, 0x29, 0x9E, 0xE3, 0xFF, 0x00, 0x07, 0x84, 0xFF, 0x00, 0xC9, 0xEE, 0xFC, 0x31,
+	0xFF, 0x00, 0xB2, 0x53, 0xFF, 0x00, 0xB9, 0x2B, 0xCA, 0xFA, 0xAB, 0xF6, 0xC9, 0xCF, 0xFC, 0x42,
+	0x33, 0xA2, 0xFF, 0x00, 0xD9, 0x2B, 0xF0, 0x1F, 0xFE, 0x9E, 0x74, 0x8A, 0xF9, 0x57, 0xFE, 0x0F,
+	0x09, 0xFF, 0x00, 0x93, 0xDD, 0xF8, 0x63, 0xFF, 0x00, 0x64, 0xA7, 0xFF, 0x00, 0x72, 0x57, 0x95,
+	0xF5, 0x57, 0xED, 0x93, 0x9F, 0xF8, 0x84, 0x67, 0x45, 0xFF, 0x00, 0xB2, 0x57, 0xE0, 0x3F, 0xFD,
+	0x3C, 0xE9, 0x14, 0xFE, 0xD3, 0x27, 0xFE, 0x5C, 0xC3, 0xD4, 0xE1, 0x3F, 0xE0, 0xCD, 0x8F, 0xF9,
+	0x26, 0x9F, 0x1E, 0xBF, 0xEC, 0x35, 0xE1, 0xFF, 0x00, 0xFD, 0x11, 0x7B, 0x5F, 0x0F, 0xFF, 0x00,
+	0xC1, 0x26, 0x3F, 0xE5, 0x61, 0x8F, 0x09, 0xFF, 0x00, 0xD9, 0x56, 0xF1, 0x1F, 0xFE, 0x93, 0xEA,
+	0x95, 0xF7, 0x07, 0xFC, 0x19, 0xB1, 0xFF, 0x00, 0x24, 0xD3, 0xE3, 0xD7, 0xFD, 0x86, 0xBC, 0x3F,
+	0xFF, 0x00, 0xA2, 0x2F, 0x6B, 0xE1, 0xFF, 0x00, 0xF8, 0x24, 0xC7, 0xFC, 0xAC, 0x31, 0xE1, 0x3F,
+	0xFB, 0x2A, 0xDE, 0x23, 0xFF, 0x00, 0xD2, 0x7D, 0x52, 0x97, 0xD9, 0x45, 0x47, 0xE2, 0x9F, 0xA1,
+	0xEA, 0x9F, 0xF0, 0x77, 0xCF, 0xFC, 0xA4, 0xA7, 0xC0, 0xFF, 0x00, 0xF6, 0x44, 0x74, 0xBF, 0xFD,
+	0x3C, 0xEA, 0xF5, 0xF6, 0x2F, 0xFC, 0x16, 0xC7, 0xFE, 0x55, 0xBF, 0xF8, 0x65, 0xFF, 0x00, 0x60,
+	0x6F, 0x01, 0xFF, 0x00, 0xE9, 0x14, 0x35, 0xF1, 0xD7, 0xFC, 0x1D, 0xF3, 0xFF, 0x00, 0x29, 0x29,
+	0xF0, 0x3F, 0xFD, 0x91, 0x1D, 0x2F, 0xFF, 0x00, 0x4F, 0x3A, 0xBD, 0x7D, 0x8B, 0xFF, 0x00, 0x05,
+	0xB1, 0xFF, 0x00, 0x95, 0x6F, 0xFE, 0x19, 0x7F, 0xD8, 0x1B, 0xC0, 0x7F, 0xFA, 0x45, 0x0D, 0x27,
+	0xD4, 0x8F, 0xB3, 0x03, 0x0B, 0xFE, 0x0C, 0xE7, 0xFF, 0x00, 0x93, 0x69, 0xF8, 0xC9, 0xFF, 0x00,
+	0x63, 0xC6, 0x9D, 0xFF, 0x00, 0xA4, 0x75, 0xF8, 0x06, 0x3A, 0x57, 0xEF, 0xE7, 0xFC, 0x19, 0xCF,
+	0xFF, 0x00, 0x26, 0xD3, 0xF1, 0x93, 0xFE, 0xC7, 0x8D, 0x3B, 0xFF, 0x00, 0x48, 0xEB, 0xF0, 0x0C,
+	0x74, 0xA9, 0xFF, 0x00, 0x97, 0x68, 0xD6, 0x9F, 0xF1, 0xA7, 0xF2, 0x0A, 0xFB, 0xFB, 0xFE, 0x0D,
+	0x90, 0xFF, 0x00, 0x94, 0xC1, 0xF8, 0x07, 0xFE, 0xC0, 0x3E, 0x20, 0xFF, 0x00, 0xD3, 0x54, 0xF5,
+	0xF0, 0x0D, 0x7D, 0xFD, 0xFF, 0x00, 0x06, 0xC8, 0x7F, 0xCA, 0x60, 0xFC, 0x03, 0xFF, 0x00, 0x60,
+	0x1F, 0x10, 0x7F, 0xE9, 0xAA, 0x7A, 0x23, 0xF1, 0x17, 0x5B, 0xF8, 0x72, 0x24, 0xFF, 0x00, 0x83,
+	0x9D, 0x3F, 0xE5, 0x30, 0x9E, 0x3D, 0xFF, 0x00, 0xB0, 0x1E, 0x83, 0xFF, 0x00, 0xA6, 0xDB, 0x7A,
+	0xFC, 0xFD, 0x1D, 0x2B, 0xF4, 0x0B, 0xFE, 0x0E, 0x74, 0xFF, 0x00, 0x94, 0xC2, 0x78, 0xF7, 0xFE,
+	0xC0, 0x7A, 0x0F, 0xFE, 0x9B, 0x6D, 0xEB, 0xF3, 0xF4, 0x74, 0xA9, 0x97, 0xC4, 0x55, 0x3F, 0xE0,
+	0xC4, 0x53, 0xF7, 0x9B, 0xFC, 0xFF, 0x00, 0x05, 0x7E, 0xFD, 0xFF, 0x00, 0xC1, 0xD6, 0xDF, 0xF2,
+	0x8D, 0x7F, 0x82, 0x1F, 0xF6, 0x3E, 0x58, 0xFF, 0x00, 0xE9, 0x9A, 0xF2, 0xBF, 0x01, 0x0F, 0xDE,
+	0x6F, 0xF3, 0xFC, 0x15, 0xFB, 0xF7, 0xFF, 0x00, 0x07, 0x5B, 0x7F, 0xCA, 0x35, 0xFE, 0x08, 0x7F,
+	0xD8, 0xF9, 0x63, 0xFF, 0x00, 0xA6, 0x6B, 0xCA, 0xD2, 0x1F, 0x0B, 0x33, 0x9F, 0xF1, 0xA2, 0x74,
+	0x1F, 0xF0, 0x6E, 0x87, 0xFC, 0xA0, 0x8F, 0xE2, 0x97, 0xFD, 0x87, 0x3C, 0x57, 0xFF, 0x00, 0xA6,
+	0xAB, 0x6A, 0xF8, 0x63, 0xFE, 0x0D, 0x30, 0xFF, 0x00, 0x94, 0xA1, 0xDF, 0x7F, 0xD9, 0x27, 0xD5,
+	0xBF, 0xF4, 0xB3, 0x4F, 0xAF, 0xB9, 0xFF, 0x00, 0xE0, 0xDD, 0x0F, 0xF9, 0x41, 0x1F, 0xC5, 0x2F,
+	0xFB, 0x0E, 0x78, 0xAF, 0xFF, 0x00, 0x4D, 0x56, 0xD5, 0xF0, 0xC7, 0xFC, 0x1A, 0x61, 0xFF, 0x00,
+	0x29, 0x43, 0xBE, 0xFF, 0x00, 0xB2, 0x4F, 0xAB, 0x7F, 0xE9, 0x66, 0x9F, 0x55, 0xD6, 0x24, 0x7D,
+	0x9A, 0x87, 0x11, 0xFF, 0x00, 0x05, 0xF1, 0xFF, 0x00, 0x94, 0xF5, 0xFC, 0x46, 0xFF, 0x00, 0xB0,
+	0xE7, 0x84, 0xBF, 0xF4, 0xC5, 0xA4, 0x57, 0xE8, 0x17, 0xFC, 0x1E, 0x2F, 0xFF, 0x00, 0x26, 0xD9,
+	0xF0, 0x6F, 0xFE, 0xC7, 0xAB, 0xDF, 0xFD, 0x23, 0x5A, 0xFC, 0xFD, 0xFF, 0x00, 0x82, 0xF8, 0xFF,
+	0x00, 0xCA, 0x7A, 0xFE, 0x23, 0x7F, 0xD8, 0x73, 0xC2, 0x5F, 0xFA, 0x62, 0xD2, 0x2B, 0xF4, 0x0B,
+	0xFE, 0x0F, 0x17, 0xFF, 0x00, 0x93, 0x6C, 0xF8, 0x37, 0xFF, 0x00, 0x63, 0xD5, 0xEF, 0xFE, 0x91,
+	0xAD, 0x3E, 0xAC, 0x3E, 0xD5, 0x33, 0x6B, 0xFE, 0x09, 0x8F, 0xFF, 0x00, 0x2A, 0xA7, 0x7C, 0x46,
+	0xFF, 0x00, 0xB2, 0x4F, 0xF1, 0x2B, 0xFF, 0x00, 0x45, 0xEA, 0x95, 0xF1, 0xD7, 0xFC, 0x1A, 0x11,
+	0xFF, 0x00, 0x29, 0x28, 0xF1, 0xC7, 0xFD, 0x90, 0xFD, 0x4B, 0xFF, 0x00, 0x4F, 0x3A, 0x2D, 0x7D,
+	0x8B, 0xFF, 0x00, 0x04, 0xC7, 0xFF, 0x00, 0x95, 0x53, 0xBE, 0x23, 0x7F, 0xD9, 0x27, 0xF8, 0x95,
+	0xFF, 0x00, 0xA2, 0xF5, 0x4A, 0xF8, 0xEB, 0xFE, 0x0D, 0x08, 0xFF, 0x00, 0x94, 0x94, 0x78, 0xE3,
+	0xFE, 0xC8, 0x7E, 0xA5, 0xFF, 0x00, 0xA7, 0x9D, 0x16, 0xA7, 0xAC, 0x4C, 0xDF, 0xF0, 0xE7, 0xEA,
+	0x79, 0x57, 0xFC, 0x15, 0x8F, 0xFE, 0x56, 0x17, 0xF1, 0x57, 0xFD, 0x95, 0x4F, 0x0D, 0x7F, 0xE9,
+	0x3E, 0x9F, 0x5F, 0x70, 0x7F, 0xC1, 0xE4, 0xDF, 0xF2, 0x4D, 0xFE, 0x02, 0xFF, 0x00, 0xD8, 0x77,
+	0xC4, 0x1F, 0xFA, 0x4D, 0x63, 0x5F, 0x0F, 0xFF, 0x00, 0xC1, 0x58, 0xFF, 0x00, 0xE5, 0x61, 0x7F,
+	0x15, 0x7F, 0xD9, 0x54, 0xF0, 0xD7, 0xFE, 0x93, 0xE9, 0xF5, 0xF7, 0x07, 0xFC, 0x1E, 0x4D, 0xFF,
+	0x00, 0x24, 0xDF, 0xE0, 0x2F, 0xFD, 0x87, 0x7C, 0x41, 0xFF, 0x00, 0xA4, 0xD6, 0x34, 0xBE, 0xD4,
+	0x8A, 0xFF, 0x00, 0x97, 0xB0, 0x3B, 0xAF, 0xD8, 0xE3, 0xFE, 0x55, 0x14, 0xD6, 0xBF, 0xEC, 0x93,
+	0xF8, 0xF3, 0xFF, 0x00, 0x4F, 0x1A, 0xBD, 0x7C, 0xE3, 0xFF, 0x00, 0x06, 0x76, 0xFF, 0x00, 0xC9,
+	0xCB, 0x7C, 0x65, 0xFF, 0x00, 0xB1, 0x16, 0xC7, 0xFF, 0x00, 0x4B, 0x5A, 0xBE, 0x8E, 0xFD, 0x8E,
+	0x3F, 0xE5, 0x51, 0x4D, 0x6B, 0xFE, 0xC9, 0x3F, 0x8F, 0x3F, 0xF4, 0xF1, 0xAB, 0xD7, 0xCE, 0x3F,
+	0xF0, 0x67, 0x6F, 0xFC, 0x9C, 0xB7, 0xC6, 0x5F, 0xFB, 0x11, 0x6C, 0x7F, 0xF4, 0xB5, 0xAA, 0xBE,
+	0xD4, 0x43, 0xFE, 0x5D, 0xD4, 0xF5, 0x3E, 0x56, 0xFD, 0xA4, 0xBF, 0xE5, 0x62, 0xCD, 0x63, 0xFE,
+	0xCE, 0xB6, 0xDF, 0xFF, 0x00, 0x4F, 0x56, 0xF5, 0xF6, 0x3F, 0xFC, 0x1E, 0x49, 0xFF, 0x00, 0x25,
+	0x2B, 0xE0, 0x27, 0xFD, 0x80, 0x75, 0xFF, 0x00, 0xFD, 0x29, 0xD3, 0xEB, 0xE3, 0x8F, 0xDA, 0x4B,
+	0xFE, 0x56, 0x2C, 0xD6, 0x3F, 0xEC, 0xEB, 0x6D, 0xFF, 0x00, 0xF4, 0xF5, 0x6F, 0x5F, 0x63, 0xFF,
+	0x00, 0xC1, 0xE4, 0x9F, 0xF2, 0x52, 0xBE, 0x02, 0x7F, 0xD8, 0x07, 0x5F, 0xFF, 0x00, 0xD2, 0x9D,
+	0x3E, 0xA6, 0x3F, 0x68, 0xA8, 0xFF, 0x00, 0x16, 0x1E, 0x87, 0xB7, 0xFC, 0x3D, 0xFF, 0x00, 0x95,
+	0x45, 0xEE, 0x3F, 0xEC, 0x94, 0xEA, 0x9F, 0xFA, 0x78, 0x9E, 0xBC, 0x3F, 0xFE, 0x0C, 0xD8, 0xFF,
+	0x00, 0x92, 0x95, 0xF1, 0xEB, 0xFE, 0xC0, 0x9E, 0x1E, 0xFF, 0x00, 0xD1, 0xDA, 0x85, 0x7B, 0x87,
+	0xC3, 0xDF, 0xF9, 0x54, 0x5E, 0xE3, 0xFE, 0xC9, 0x4E, 0xA9, 0xFF, 0x00, 0xA7, 0x89, 0xEB, 0xC3,
+	0xFF, 0x00, 0xE0, 0xCD, 0x8F, 0xF9, 0x29, 0x5F, 0x1E, 0xBF, 0xEC, 0x09, 0xE1, 0xEF, 0xFD, 0x1D,
+	0xA8, 0x56, 0xAB, 0xE2, 0x44, 0xC7, 0xF8, 0x72, 0x3E, 0x55, 0xF8, 0x7D, 0xFF, 0x00, 0x2B, 0x36,
+	0x4F, 0xFF, 0x00, 0x67, 0x8F, 0xAA, 0x7F, 0xEA, 0x43, 0x3D, 0x7D, 0x1B, 0xFF, 0x00, 0x07, 0x8C,
+	0x7F, 0xC9, 0xC8, 0x7C, 0x1B, 0xFF, 0x00, 0xB1, 0x0F, 0x50, 0xFF, 0x00, 0xD2, 0xD5, 0xAF, 0x9C,
+	0xBE, 0x1F, 0x7F, 0xCA, 0xCD, 0x93, 0xFF, 0x00, 0xD9, 0xE3, 0xEA, 0x9F, 0xFA, 0x90, 0xCF, 0x5F,
+	0x46, 0xFF, 0x00, 0xC1, 0xE3, 0x1F, 0xF2, 0x72, 0x1F, 0x06, 0xFF, 0x00, 0xEC, 0x43, 0xD4, 0x3F,
+	0xF4, 0xB5, 0x6A, 0x3A, 0x33, 0x48, 0x7F, 0x12, 0x1E, 0x87, 0xD2, 0x1F, 0xB6, 0x4E, 0x7F, 0xE2,
+	0x11, 0xAD, 0x1F, 0xFE, 0xC9, 0x5F, 0x80, 0xFF, 0x00, 0xF4, 0xF5, 0xA4, 0x57, 0x93, 0xFF, 0x00,
+	0xC1, 0x99, 0x3F, 0x77, 0xF6, 0x8D, 0xFF, 0x00, 0x73, 0xC1, 0xFF, 0x00, 0xFB, 0x9E, 0xAF, 0x58,
+	0xFD, 0xB2, 0x73, 0xFF, 0x00, 0x10, 0x8D, 0x68, 0xFF, 0x00, 0xF6, 0x4A, 0xFC, 0x07, 0xFF, 0x00,
+	0xA7, 0xAD, 0x22, 0xBC, 0x9F, 0xFE, 0x0C, 0xC9, 0xFB, 0xBF, 0xB4, 0x6F, 0xFB, 0x9E, 0x0F, 0xFF,
+	0x00, 0xDC, 0xF5, 0x1F, 0x69, 0x18, 0xFF, 0x00, 0xCB, 0xB9, 0x7A, 0x9F, 0x1D, 0xFE, 0xC5, 0xDF,
+	0xF2, 0xB2, 0x3E, 0x9B, 0xFF, 0x00, 0x67, 0x21, 0xAD, 0xFF, 0x00, 0xE9, 0x65, 0xE5, 0x7B, 0x97,
+	0xFC, 0x1E, 0x13, 0xFF, 0x00, 0x27, 0xBB, 0xF0, 0xC7, 0xFE, 0xC9, 0x4F, 0xFE, 0xE4, 0xAF, 0x2B,
+	0xC3, 0x7F, 0x62, 0xEF, 0xF9, 0x59, 0x1F, 0x4D, 0xFF, 0x00, 0xB3, 0x90, 0xD6, 0xFF, 0x00, 0xF4,
+	0xB2, 0xF2, 0xBD, 0xCB, 0xFE, 0x0F, 0x09, 0xFF, 0x00, 0x93, 0xDD, 0xF8, 0x63, 0xFF, 0x00, 0x64,
+	0xA7, 0xFF, 0x00, 0x72, 0x57, 0x94, 0x7D, 0x93, 0x6F, 0xF9, 0x7F, 0x1F, 0x43, 0xEA, 0x7F, 0xF8,
+	0x29, 0xCF, 0xFC, 0xAA, 0xA9, 0xF0, 0xE3, 0xFE, 0xC9, 0x5F, 0xC3, 0x3F, 0xFD, 0x17, 0xA5, 0xD6,
+	0x17, 0xFC, 0x19, 0xD3, 0xFF, 0x00, 0x26, 0xD3, 0xF1, 0x8F, 0xFE, 0xC7, 0x9B, 0x0F, 0xFD, 0x22,
+	0xAD, 0xDF, 0xF8, 0x29, 0xCF, 0xFC, 0xAA, 0xA9, 0xF0, 0xE3, 0xFE, 0xC9, 0x5F, 0xC3, 0x3F, 0xFD,
+	0x17, 0xA5, 0xD6, 0x17, 0xFC, 0x19, 0xD3, 0xFF, 0x00, 0x26, 0xD3, 0xF1, 0x8F, 0xFE, 0xC7, 0x9B,
+	0x0F, 0xFD, 0x22, 0xA3, 0xED, 0x23, 0x27, 0xFC, 0x1F, 0x99, 0xF9, 0xCF, 0xFF, 0x00, 0x04, 0x4A,
+	0xFF, 0x00, 0x94, 0xE7, 0xFC, 0x31, 0xFF, 0x00, 0xB1, 0xEB, 0x58, 0xFF, 0x00, 0xD2, 0x1D, 0x46,
+	0xBD, 0x5B, 0xFE, 0x0E, 0xCA, 0xFF, 0x00, 0x94, 0xA3, 0x58, 0xFF, 0x00, 0xD9, 0x27, 0xD2, 0x3F,
+	0xF4, 0xAE, 0xFA, 0xBC, 0xA7, 0xFE, 0x08, 0x95, 0xFF, 0x00, 0x29, 0xCF, 0xF8, 0x63, 0xFF, 0x00,
+	0x63, 0xD6, 0xB1, 0xFF, 0x00, 0xA4, 0x3A, 0x8D, 0x7A, 0xB7, 0xFC, 0x1D, 0x95, 0xFF, 0x00, 0x29,
+	0x46, 0xB1, 0xFF, 0x00, 0xB2, 0x4F, 0xA4, 0x7F, 0xE9, 0x5D, 0xF5, 0x4B, 0xF8, 0x4D, 0xBF, 0xE5,
+	0xF4, 0x7D, 0x0F, 0xCC, 0x53, 0xD6, 0x8A, 0x0F, 0x5A, 0x2B, 0x33, 0x70, 0xA2, 0x8A, 0x28, 0x00,
+	0xA2, 0x8A, 0x28, 0x00, 0xAF, 0xD4, 0x4F, 0xF8, 0x24, 0xE7, 0x85, 0x7F, 0xB1, 0x3F, 0x64, 0x78,
+	0x35, 0x3F, 0x23, 0x6F, 0xF6, 0xDF, 0x88, 0x6F, 0x6E, 0xF7, 0x7A, 0xE3, 0x65, 0xBF, 0xFE, 0xD2,
+	0xAF, 0xCB, 0xD2, 0x16, 0x43, 0xE5, 0xBA, 0xE7, 0xEE, 0x86, 0x5F, 0x52, 0x7E, 0xED, 0x7E, 0xC7,
+	0x7E, 0xC6, 0x9E, 0x11, 0x3E, 0x06, 0xFD, 0x96, 0x3C, 0x05, 0xA1, 0xC8, 0x91, 0xAC, 0x83, 0xC3,
+	0xB6, 0xD7, 0x33, 0xAA, 0xF5, 0x12, 0xCE, 0x05, 0xC3, 0x0F, 0xCD, 0xCD, 0x69, 0x49, 0x5D, 0xDC,
+	0xE5, 0xC5, 0x4A, 0xD1, 0x48, 0xF4, 0xC0, 0xDB, 0x86, 0xEF, 0x5E, 0x6B, 0xF4, 0xD3, 0xFE, 0x09,
+	0xAB, 0xFF, 0x00, 0x26, 0x8F, 0xA1, 0xFF, 0x00, 0xD7, 0xF5, 0xFF, 0x00, 0xFE, 0x94, 0xB5, 0x7E,
+	0x65, 0x85, 0x64, 0x1B, 0x1F, 0xEF, 0x0E, 0x0D, 0x7E, 0x9A, 0x7F, 0xC1, 0x35, 0x7F, 0xE4, 0xD1,
+	0xF4, 0x3F, 0xFA, 0xFE, 0xBF, 0xFF, 0x00, 0xD2, 0x96, 0xAE, 0x83, 0x84, 0xF8, 0xE7, 0xFE, 0x0A,
+	0x8D, 0xFF, 0x00, 0x27, 0x77, 0xAA, 0x7F, 0xD8, 0x27, 0x4F, 0xFF, 0x00, 0xD1, 0x42, 0xBE, 0x79,
+	0xAF, 0xA1, 0xBF, 0xE0, 0xA8, 0xDF, 0xF2, 0x77, 0x7A, 0xA7, 0xFD, 0x82, 0x74, 0xFF, 0x00, 0xFD,
+	0x14, 0x2B, 0xE7, 0x9A, 0x0F, 0x4A, 0x9F, 0xC0, 0x82, 0x8A, 0x28, 0xA0, 0xA0, 0xAF, 0xD8, 0xFF,
+	0x00, 0xD9, 0x87, 0xFE, 0x4D, 0xAB, 0xE1, 0xE7, 0xFD, 0x88, 0xDA, 0x4F, 0xFE, 0x91, 0xC5, 0x5F,
+	0x8E, 0x15, 0xFB, 0x1F, 0xFB, 0x30, 0xFF, 0x00, 0xC9, 0xB5, 0x7C, 0x3C, 0xFF, 0x00, 0xB1, 0x1B,
+	0x49, 0xFF, 0x00, 0xD2, 0x38, 0xA8, 0x39, 0xF1, 0x5B, 0x44, 0xFC, 0xDA, 0xFD, 0xB4, 0xFF, 0x00,
+	0xE4, 0xEB, 0xBC, 0x6D, 0xFF, 0x00, 0x61, 0xC3, 0xFF, 0x00, 0xA0, 0xAD, 0x79, 0x62, 0x7D, 0xC1,
+	0xF4, 0xAF, 0x53, 0xFD, 0xB4, 0xFF, 0x00, 0xE4, 0xEB, 0xBC, 0x6D, 0xFF, 0x00, 0x61, 0xC3, 0xFF,
+	0x00, 0xA0, 0xAD, 0x79, 0x62, 0x7D, 0xC1, 0xF4, 0xA0, 0xE3, 0x16, 0x8A, 0x28, 0xA0, 0x02, 0xBE,
+	0xF4, 0xFF, 0x00, 0x82, 0x42, 0xFF, 0x00, 0xC9, 0x35, 0xF1, 0x87, 0xFD, 0x87, 0x20, 0xFF, 0x00,
+	0xD1, 0x35, 0xF0, 0x5D, 0x7D, 0xE9, 0xFF, 0x00, 0x04, 0x85, 0xFF, 0x00, 0x92, 0x6B, 0xE3, 0x0F,
+	0xFB, 0x0E, 0x41, 0xFF, 0x00, 0xA2, 0x68, 0x03, 0xC7, 0xBF, 0xE0, 0xAA, 0x3F, 0xF2, 0x73, 0x36,
+	0xFF, 0x00, 0xF6, 0x2C, 0x5A, 0xFF, 0x00, 0xE8, 0x72, 0xD7, 0xCD, 0x95, 0xF4, 0x9F, 0xFC, 0x15,
+	0x47, 0xFE, 0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B, 0x5F, 0xFD, 0x0E, 0x5A, 0xF9, 0xB2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0E, 0xDF, 0x85, 0x7D, 0xD1, 0xFF, 0x00, 0x04, 0x80, 0xFF, 0x00, 0x91, 0x73,
+	0xC7, 0xDF, 0xF6, 0x10, 0xB0, 0xFF, 0x00, 0xD1, 0x73, 0x57, 0xC2, 0xFD, 0xBF, 0x0A, 0xFB, 0xA3,
+	0xFE, 0x09, 0x01, 0xFF, 0x00, 0x22, 0xE7, 0x8F, 0xBF, 0xEC, 0x21, 0x61, 0xFF, 0x00, 0xA2, 0xE6,
+	0xA0, 0x0F, 0x2A, 0xFF, 0x00, 0x82, 0xA8, 0xFF, 0x00, 0xC9, 0xCC, 0xDB, 0xFF, 0x00, 0xD8, 0xB1,
+	0x6B, 0xFF, 0x00, 0xA1, 0xCB, 0x5F, 0x36, 0x57, 0xD2, 0x7F, 0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B,
+	0x7F, 0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x3B,
+	0x7E, 0x15, 0xF7, 0x27, 0xFC, 0x12, 0x1B, 0xFE, 0x45, 0xBF, 0x1E, 0xFF, 0x00, 0xD8, 0x42, 0xC7,
+	0xFF, 0x00, 0x45, 0xCD, 0x5F, 0x0D, 0xF6, 0xFC, 0x2B, 0xEE, 0x4F, 0xF8, 0x24, 0x37, 0xFC, 0x8B,
+	0x7E, 0x3D, 0xFF, 0x00, 0xB0, 0x85, 0x8F, 0xFE, 0x8B, 0x9A, 0xA6, 0x5F, 0x08, 0x1F, 0x67, 0x41,
+	0xFE, 0xA9, 0x69, 0xD4, 0xD8, 0x3F, 0xD5, 0x2D, 0x3A, 0xA8, 0x02, 0x83, 0xD2, 0x8A, 0x46, 0x20,
+	0x29, 0x2C, 0x78, 0xC5, 0x00, 0x7C, 0x2B, 0xFF, 0x00, 0x05, 0x7D, 0xFF, 0x00, 0x91, 0x93, 0xC0,
+	0xFF, 0x00, 0xF5, 0xE5, 0x7D, 0xFF, 0x00, 0xA3, 0x23, 0xAF, 0x8D, 0xAB, 0xF5, 0x93, 0xE3, 0x37,
+	0xEC, 0xD3, 0xF0, 0x8F, 0xF6, 0x86, 0xD6, 0x6C, 0xDF, 0xE2, 0xB7, 0x86, 0xE5, 0xBE, 0x6D, 0x36,
+	0xD8, 0xAD, 0xA7, 0x95, 0xA8, 0x4D, 0x16, 0xCF, 0x31, 0xF2, 0xDF, 0x73, 0x03, 0xF8, 0x16, 0xB8,
+	0xFF, 0x00, 0xF8, 0x76, 0x9F, 0xEC, 0x87, 0xFF, 0x00, 0x42, 0x26, 0xA1, 0xFF, 0x00, 0x83, 0xEB,
+	0x8F, 0xFE, 0x39, 0x40, 0x1F, 0x99, 0x74, 0x57, 0xE9, 0xA7, 0xFC, 0x3B, 0x4F, 0xF6, 0x43, 0xFF,
+	0x00, 0xA1, 0x13, 0x50, 0xFF, 0x00, 0xC1, 0xF5, 0xC7, 0xFF, 0x00, 0x1C, 0xA3, 0xFE, 0x1D, 0xA7,
+	0xFB, 0x21, 0xFF, 0x00, 0xD0, 0x89, 0xA8, 0x7F, 0xE0, 0xFA, 0xE3, 0xFF, 0x00, 0x8E, 0x50, 0x07,
+	0xE6, 0x58, 0xEB, 0x5F, 0x57, 0xFF, 0x00, 0xC1, 0x24, 0x7F, 0xE4, 0xB4, 0xF8, 0x9B, 0xFE, 0xC5,
+	0x45, 0xFF, 0x00, 0xD2, 0x98, 0xAB, 0xE8, 0x57, 0xFF, 0x00, 0x82, 0x6A, 0x7E, 0xC8, 0xA1, 0x09,
+	0x5F, 0x02, 0x5F, 0xE7, 0x1C, 0x7F, 0xC4, 0xF6, 0xE4, 0xFF, 0x00, 0x29, 0x33, 0xF9, 0x73, 0x5D,
+	0x77, 0xC1, 0xAF, 0xD9, 0x43, 0xE0, 0x9F, 0xC0, 0x1D, 0x76, 0xEB, 0xC4, 0xDF, 0x0B, 0x3C, 0x3B,
+	0x73, 0x63, 0x75, 0x7D, 0x67, 0xF6, 0x6B, 0x86, 0x97, 0x52, 0x9A, 0x6C, 0xC2, 0x5C, 0x38, 0xE2,
+	0x47, 0x38, 0xE4, 0x50, 0x07, 0x92, 0xFF, 0x00, 0xC1, 0x59, 0x7F, 0xE4, 0xDD, 0xF4, 0x3F, 0xFB,
+	0x1C, 0xA1, 0xFF, 0x00, 0xD2, 0x5B, 0x9A, 0xFC, 0xF7, 0xAF, 0xD7, 0x8F, 0x8C, 0xBF, 0x03, 0xFE,
+	0x1D, 0xFC, 0x7B, 0xD0, 0xA0, 0xF0, 0x97, 0xC4, 0xFD, 0x21, 0xAF, 0xEC, 0x6D, 0x6F, 0x7E, 0xD3,
+	0x14, 0x30, 0xDC, 0x3C, 0x3F, 0xBC, 0xD8, 0xE8, 0x09, 0x29, 0xC9, 0xF9, 0x64, 0xAF, 0x3B, 0xFF,
+	0x00, 0x87, 0x69, 0xFE, 0xC8, 0x7F, 0xF4, 0x22, 0x6A, 0x1F, 0xF8, 0x3E, 0xB8, 0xFF, 0x00, 0xE3,
+	0x94, 0x59, 0xC7, 0x72, 0x9B, 0xBA, 0x47, 0xE6, 0x5D, 0x15, 0xFA, 0x69, 0xFF, 0x00, 0x0E, 0xD3,
+	0xFD, 0x90, 0xFF, 0x00, 0xE8, 0x44, 0xD4, 0x3F, 0xF0, 0x7D, 0x71, 0xFF, 0x00, 0xC7, 0x28, 0xFF,
+	0x00, 0x87, 0x69, 0xFE, 0xC8, 0x7F, 0xF4, 0x22, 0x6A, 0x1F, 0xF8, 0x3E, 0xB8, 0xFF, 0x00, 0xE3,
+	0x94, 0x12, 0x7E, 0x65, 0xD7, 0xBD, 0x7F, 0xC1, 0x36, 0x3F, 0xE4, 0xEE, 0x74, 0x1F, 0xFB, 0x07,
+	0xEA, 0x1F, 0xFA, 0x4E, 0xF5, 0xF5, 0xD7, 0xFC, 0x3B, 0x4F, 0xF6, 0x43, 0xFF, 0x00, 0xA1, 0x13,
+	0x50, 0xFF, 0x00, 0xC1, 0xF5, 0xC7, 0xFF, 0x00, 0x1C, 0xAD, 0xFF, 0x00, 0x85, 0x7F, 0xB1, 0x67,
+	0xEC, 0xFB, 0xF0, 0x6B, 0xC6, 0x36, 0xBF, 0x10, 0xBE, 0x1E, 0x78, 0x52, 0xEA, 0xD3, 0x55, 0xB5,
+	0x8E, 0x44, 0x86, 0x69, 0x35, 0x4B, 0x89, 0x46, 0x1D, 0x36, 0x3F, 0xC9, 0x2B, 0xD0, 0x06, 0x57,
+	0xFC, 0x14, 0x53, 0xFE, 0x4C, 0xEF, 0xC5, 0xBF, 0xF5, 0xD2, 0xC7, 0xFF, 0x00, 0x4B, 0x60, 0xAF,
+	0xCC, 0x1A, 0xFD, 0x88, 0xF8, 0xA1, 0xF0, 0xD7, 0xC2, 0x7F, 0x17, 0x7C, 0x23, 0x75, 0xE0, 0x0F,
+	0x1D, 0xD9, 0xB5, 0xDE, 0x97, 0x78, 0xF1, 0x3D, 0xC4, 0x31, 0xCA, 0xD1, 0x96, 0xD8, 0xE8, 0xEB,
+	0x96, 0x5E, 0x7E, 0xF2, 0x76, 0xAF, 0x2B, 0x4F, 0xF8, 0x26, 0x97, 0xEC, 0x86, 0x14, 0x01, 0xE0,
+	0x2B, 0xE5, 0xE3, 0xEE, 0xAE, 0xBD, 0x71, 0xC7, 0xFE, 0x3F, 0x49, 0x45, 0xC7, 0x72, 0x9E, 0xC8,
+	0xFC, 0xCB, 0xA2, 0xBF, 0x4D, 0x3F, 0xE1, 0xDA, 0x7F, 0xB2, 0x1F, 0xFD, 0x08, 0x9A, 0x87, 0xFE,
+	0x0F, 0xAE, 0x3F, 0xF8, 0xE5, 0x1F, 0xF0, 0xED, 0x3F, 0xD9, 0x0F, 0xFE, 0x84, 0x4D, 0x43, 0xFF,
+	0x00, 0x07, 0xD7, 0x1F, 0xFC, 0x72, 0x99, 0x27, 0xE6, 0x5D, 0x7A, 0x27, 0xEC, 0x95, 0xFF, 0x00,
+	0x27, 0x39, 0xE0, 0x1F, 0xFB, 0x1A, 0xAD, 0x3F, 0xF4, 0x21, 0x5F, 0x78, 0x7F, 0xC3, 0xB4, 0xFF,
+	0x00, 0x64, 0x3F, 0xFA, 0x11, 0x35, 0x0F, 0xFC, 0x1F, 0x5C, 0x7F, 0xF1, 0xCA, 0xD0, 0xF0, 0x67,
+	0xEC, 0x0D, 0xFB, 0x32, 0xF8, 0x0B, 0xC5, 0x5A, 0x7F, 0x8D, 0x7C, 0x2D, 0xE0, 0xDB, 0xC8, 0x35,
+	0x2D, 0x26, 0xF5, 0x2E, 0x2C, 0xA6, 0x6D, 0x62, 0xE5, 0x82, 0xCA, 0x84, 0x95, 0xF9, 0x5D, 0xF6,
+	0x9E, 0x0F, 0xD2, 0x80, 0x3A, 0xCF, 0xDA, 0x93, 0xFE, 0x4D, 0xA3, 0xE2, 0x27, 0xFD, 0x89, 0x3A,
+	0x9F, 0xFE, 0x92, 0xC9, 0x5F, 0x8D, 0x75, 0xFB, 0x6F, 0xE3, 0xAF, 0x09, 0xE9, 0x5E, 0x3E, 0xF0,
+	0x86, 0xA7, 0xE0, 0x8F, 0x11, 0xB3, 0x36, 0x9F, 0xAC, 0x69, 0xD2, 0xD9, 0xDE, 0x88, 0x5B, 0x6C,
+	0x82, 0x39, 0x15, 0x95, 0xF0, 0xDD, 0xB8, 0x61, 0x5F, 0x3E, 0x27, 0xFC, 0x12, 0x6F, 0xF6, 0x5B,
+	0x44, 0x55, 0x11, 0x78, 0x88, 0xE0, 0x60, 0xE7, 0x58, 0x3F, 0xFC, 0x4D, 0x7C, 0xAF, 0x10, 0x64,
+	0xB8, 0xAC, 0xCA, 0xA5, 0x39, 0x52, 0x69, 0x59, 0x35, 0xAF, 0xA9, 0xFA, 0xFF, 0x00, 0x86, 0x7C,
+	0x75, 0x93, 0xF0, 0x8E, 0x0F, 0x11, 0x4B, 0x1A, 0xA4, 0xDC, 0xE4, 0x9A, 0xE5, 0x49, 0xEC, 0xAD,
+	0xD5, 0xA3, 0xF3, 0x2E, 0x8A, 0xFD, 0x36, 0xFF, 0x00, 0x87, 0x4E, 0x7E, 0xCB, 0x9D, 0xA1, 0xF1,
+	0x17, 0xFE, 0x0E, 0x0F, 0xFF, 0x00, 0x11, 0x47, 0xFC, 0x3A, 0x73, 0xF6, 0x5C, 0xFF, 0x00, 0x9E,
+	0x3E, 0x22, 0xFF, 0x00, 0xC1, 0xC1, 0xFF, 0x00, 0xE2, 0x2B, 0xE7, 0x7F, 0xD5, 0x1C, 0xCF, 0xBC,
+	0x7E, 0xFF, 0x00, 0xF8, 0x07, 0xE9, 0xBF, 0xF1, 0x1A, 0x38, 0x4F, 0xF9, 0x6A, 0x7F, 0xE0, 0x2B,
+	0xFF, 0x00, 0x92, 0x3F, 0x32, 0x6B, 0xE8, 0x7F, 0xF8, 0x25, 0xE7, 0xFC, 0x9D, 0xD6, 0x93, 0xFF,
+	0x00, 0x60, 0xAB, 0xEF, 0xFD, 0x14, 0x6B, 0xEA, 0xF3, 0xFF, 0x00, 0x04, 0x9D, 0xFD, 0x96, 0x81,
+	0xFF, 0x00, 0x53, 0xE2, 0x2F, 0xFC, 0x1C, 0x1F, 0xFE, 0x22, 0xBA, 0xCF, 0x82, 0x9F, 0xB0, 0x47,
+	0xC0, 0x8F, 0x80, 0x5E, 0x3F, 0x8B, 0xE2, 0x47, 0x80, 0xED, 0xF5, 0x63, 0xA9, 0x5B, 0xC3, 0x24,
+	0x71, 0x9B, 0xCD, 0x40, 0xCA, 0x02, 0xBA, 0x85, 0x3C, 0x7E, 0x15, 0xD9, 0x80, 0xE1, 0x8C, 0xCB,
+	0x0D, 0x8C, 0xA7, 0x52, 0x76, 0xB2, 0x77, 0x7A, 0x9E, 0x17, 0x13, 0x78, 0xAF, 0xC3, 0x39, 0xB6,
+	0x43, 0x88, 0xC1, 0x52, 0x8D, 0x45, 0x2A, 0x91, 0x69, 0x5E, 0x2A, 0xD7, 0xE9, 0xB3, 0x65, 0x5F,
+	0xF8, 0x29, 0x4F, 0xFC, 0x9A, 0x4E, 0xB9, 0xFF, 0x00, 0x5F, 0x96, 0x3F, 0xFA, 0x50, 0xB5, 0xF9,
+	0x97, 0x5F, 0xB0, 0xDF, 0x15, 0x7E, 0x17, 0xF8, 0x33, 0xE3, 0x17, 0x83, 0x26, 0xF0, 0x0F, 0x8F,
+	0xEC, 0x24, 0xBA, 0xD2, 0x6E, 0xA4, 0x8D, 0xE4, 0x86, 0x39, 0x9E, 0x2C, 0xB4, 0x6F, 0xBC, 0x72,
+	0x9C, 0xFF, 0x00, 0x0D, 0x79, 0x6A, 0xFF, 0x00, 0xC1, 0x34, 0xFF, 0x00, 0x64, 0x42, 0xA0, 0xB7,
+	0x80, 0xAF, 0xC1, 0xEE, 0x06, 0xBD, 0x71, 0xC7, 0xFE, 0x3F, 0x5F, 0xA0, 0x1F, 0xCE, 0x07, 0xE6,
+	0x60, 0xDE, 0xEB, 0xF2, 0x2F, 0xF0, 0xB2, 0x2F, 0xFB, 0x40, 0xFD, 0xE1, 0x5F, 0x8E, 0x1F, 0xB6,
+	0xBF, 0x82, 0xBF, 0xE1, 0x5C, 0xFE, 0xD4, 0xFE, 0x3C, 0xD0, 0x3C, 0xA9, 0x11, 0x1B, 0x5D, 0x96,
+	0xFE, 0xD9, 0x1B, 0xA2, 0xC3, 0x3E, 0x67, 0x51, 0xF9, 0x38, 0xAF, 0xEB, 0x0B, 0xFE, 0x1D, 0xA7,
+	0xFB, 0x21, 0xFF, 0x00, 0xD0, 0x89, 0xA8, 0x7F, 0xE0, 0xFA, 0xE3, 0xFF, 0x00, 0x8E, 0x57, 0xE1,
+	0x3F, 0xFC, 0x1D, 0x17, 0xFB, 0x16, 0x78, 0x33, 0xF6, 0x58, 0xFD, 0xAF, 0xBC, 0x0F, 0xE3, 0xBF,
+	0x86, 0x3A, 0x1C, 0xF6, 0x3E, 0x1F, 0xF1, 0xC7, 0x83, 0x30, 0xC2, 0x6B, 0x89, 0x66, 0xDD, 0xA8,
+	0xD8, 0xDC, 0x14, 0x98, 0xEE, 0xC9, 0xC7, 0xEE, 0x27, 0xB2, 0xAC, 0xAA, 0xFC, 0x37, 0x3A, 0x30,
+	0xCF, 0xF7, 0x96, 0x3F, 0x32, 0x19, 0x55, 0x18, 0xA2, 0x7D, 0xD0, 0x70, 0x29, 0x29, 0x17, 0x01,
+	0x40, 0x1E, 0x9E, 0xA4, 0xFF, 0x00, 0x3A, 0x5A, 0xC0, 0xF4, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0x8A,
+	0x28, 0xA0, 0x02, 0x85, 0xEA, 0x7F, 0x0F, 0xE4, 0x68, 0xA1, 0x7A, 0x9F, 0xC3, 0xF9, 0x1A, 0xA5,
+	0xF1, 0x20, 0x7B, 0x33, 0xFA, 0x18, 0xFF, 0x00, 0x83, 0xC1, 0x3F, 0xE4, 0xC8, 0x3E, 0x18, 0xFF,
+	0x00, 0xD9, 0x58, 0x4F, 0xFD, 0x36, 0x5F, 0xD3, 0xFF, 0x00, 0xE0, 0x89, 0x5F, 0xF2, 0xAD, 0xE7,
+	0xC4, 0xCF, 0xFB, 0x00, 0x78, 0xEF, 0xFF, 0x00, 0x48, 0xA6, 0xA6, 0x7F, 0xC1, 0xE0, 0x9F, 0xF2,
+	0x64, 0x1F, 0x0C, 0x7F, 0xEC, 0xAC, 0x27, 0xFE, 0x9B, 0x2F, 0xE9, 0xFF, 0x00, 0xF0, 0x44, 0xAF,
+	0xF9, 0x56, 0xF3, 0xE2, 0x67, 0xFD, 0x80, 0x3C, 0x77, 0xFF, 0x00, 0xA4, 0x53, 0x56, 0x8F, 0xF8,
+	0x87, 0x1B, 0xFF, 0x00, 0x77, 0xF9, 0x9F, 0x1C, 0x7F, 0xC1, 0xA0, 0xBF, 0xF2, 0x92, 0x7F, 0x1B,
+	0x7F, 0xD9, 0x0F, 0xD4, 0xBF, 0xF4, 0xF1, 0xA2, 0xD7, 0x96, 0x7F, 0xC1, 0x59, 0x3F, 0xE5, 0x61,
+	0x8F, 0x15, 0xFF, 0x00, 0xD9, 0x55, 0xF0, 0xD7, 0xFE, 0x93, 0xE9, 0xF5, 0xEA, 0x7F, 0xF0, 0x68,
+	0x2F, 0xFC, 0xA4, 0x9F, 0xC6, 0xDF, 0xF6, 0x43, 0xF5, 0x2F, 0xFD, 0x3C, 0x68, 0xB5, 0xE5, 0x9F,
+	0xF0, 0x56, 0x4F, 0xF9, 0x58, 0x63, 0xC5, 0x7F, 0xF6, 0x55, 0x7C, 0x35, 0xFF, 0x00, 0xA4, 0xFA,
+	0x7D, 0x4F, 0xFC, 0xBB, 0x45, 0x7F, 0xCB, 0xE9, 0x7A, 0x1F, 0x6F, 0xFF, 0x00, 0xC1, 0xE4, 0xBF,
+	0xF2, 0x4D, 0x7E, 0x02, 0xFF, 0x00, 0xD8, 0x7B, 0xC4, 0x1F, 0xFA, 0x4D, 0x63, 0x5D, 0xDF, 0xFC,
+	0x13, 0x27, 0xFE, 0x55, 0x51, 0xF8, 0x8F, 0xFF, 0x00, 0x64, 0xA3, 0xE2, 0x57, 0xFE, 0x8B, 0xD5,
+	0x2B, 0x84, 0xFF, 0x00, 0x83, 0xC9, 0x7F, 0xE4, 0x9A, 0xFC, 0x05, 0xFF, 0x00, 0xB0, 0xF7, 0x88,
+	0x3F, 0xF4, 0x9A, 0xC6, 0xBB, 0xBF, 0xF8, 0x26, 0x4F, 0xFC, 0xAA, 0xA3, 0xF1, 0x1F, 0xFE, 0xC9,
+	0x47, 0xC4, 0xAF, 0xFD, 0x17, 0xAA, 0x55, 0x2F, 0x89, 0x99, 0xAF, 0xE0, 0xAF, 0x53, 0xE5, 0x2F,
+	0xF8, 0x33, 0xF3, 0xFE, 0x4F, 0x8B, 0xE2, 0x77, 0xFD, 0x92, 0xBF, 0xFD, 0xCA, 0x59, 0xD7, 0x88,
+	0x7E, 0xDA, 0x3F, 0xF2, 0xB2, 0x36, 0xA9, 0xFF, 0x00, 0x67, 0x19, 0xA1, 0xFF, 0x00, 0xE9, 0x75,
+	0x9D, 0x7B, 0x7F, 0xFC, 0x19, 0xF9, 0xFF, 0x00, 0x27, 0xC5, 0xF1, 0x3B, 0xFE, 0xC9, 0x5F, 0xFE,
+	0xE5, 0x2C, 0xEB, 0xC4, 0x3F, 0x6D, 0x1F, 0xF9, 0x59, 0x1B, 0x54, 0xFF, 0x00, 0xB3, 0x8C, 0xD0,
+	0xFF, 0x00, 0xF4, 0xBA, 0xCE, 0xB3, 0x7F, 0xC3, 0x8F, 0xA9, 0xA7, 0xFC, 0xBE, 0x97, 0xA1, 0xF6,
+	0x37, 0xFC, 0x1E, 0x6B, 0xF7, 0xBF, 0x66, 0xFF, 0x00, 0xF7, 0x7C, 0x61, 0xFC, 0xF4, 0x4A, 0xF5,
+	0x4F, 0x87, 0xBF, 0xF2, 0xA8, 0xBD, 0xC7, 0xFD, 0x92, 0x9D, 0x53, 0xFF, 0x00, 0x4F, 0x13, 0xD7,
+	0x95, 0xFF, 0x00, 0xC1, 0xE6, 0xBF, 0x7B, 0xF6, 0x6F, 0xFF, 0x00, 0x77, 0xC6, 0x1F, 0xCF, 0x44,
+	0xAF, 0x54, 0xF8, 0x7B, 0xFF, 0x00, 0x2A, 0x8B, 0xDC, 0x7F, 0xD9, 0x29, 0xD5, 0x3F, 0xF4, 0xF1,
+	0x3D, 0x6D, 0xD5, 0x99, 0xAF, 0xE1, 0xC7, 0xD4, 0xF9, 0xC3, 0xFE, 0x0C, 0xEA, 0xFF, 0x00, 0x93,
+	0x93, 0xF8, 0xC9, 0xFF, 0x00, 0x62, 0x2D, 0x8F, 0xFE, 0x96, 0xB5, 0x7C, 0xAF, 0x2F, 0xFC, 0xAC,
+	0x9B, 0xFF, 0x00, 0x77, 0xC8, 0xBF, 0xFA, 0x98, 0x8A, 0xFA, 0xA3, 0xFE, 0x0C, 0xEA, 0xFF, 0x00,
+	0x93, 0x93, 0xF8, 0xC9, 0xFF, 0x00, 0x62, 0x2D, 0x8F, 0xFE, 0x96, 0xB5, 0x7C, 0xAF, 0x2F, 0xFC,
+	0xAC, 0x9B, 0xFF, 0x00, 0x77, 0xC8, 0xBF, 0xFA, 0x98, 0x8A, 0xC5, 0xFF, 0x00, 0x0E, 0x3E, 0xA6,
+	0x9F, 0xF2, 0xF2, 0x5E, 0x87, 0xD9, 0x1F, 0xF0, 0x79, 0x1F, 0xFC, 0x94, 0x8F, 0x80, 0x7F, 0xF6,
+	0x00, 0xD7, 0xBF, 0xF4, 0xA7, 0x4F, 0xAF, 0x6F, 0xF8, 0x8B, 0xFF, 0x00, 0x2A, 0x89, 0xC3, 0xFF,
+	0x00, 0x64, 0xAB, 0x4C, 0xFF, 0x00, 0xD3, 0xC4, 0x15, 0xE2, 0x1F, 0xF0, 0x79, 0x1F, 0xFC, 0x94,
+	0x8F, 0x80, 0x7F, 0xF6, 0x00, 0xD7, 0xBF, 0xF4, 0xA7, 0x4F, 0xAF, 0x6F, 0xF8, 0x8B, 0xFF, 0x00,
+	0x2A, 0x89, 0xC3, 0xFF, 0x00, 0x64, 0xAB, 0x4C, 0xFF, 0x00, 0xD3, 0xC4, 0x15, 0xA7, 0x56, 0x4B,
+	0xFE, 0x0C, 0x3D, 0x4F, 0x2B, 0xFF, 0x00, 0x83, 0x34, 0x3F, 0xD6, 0x7E, 0xD1, 0xDF, 0x4F, 0x07,
+	0xFF, 0x00, 0x3D, 0x7A, 0xBE, 0x3A, 0xFD, 0x8B, 0xFF, 0x00, 0xE5, 0x64, 0x5D, 0x37, 0xFE, 0xCE,
+	0x43, 0x5B, 0xFF, 0x00, 0xD2, 0xCB, 0xDA, 0xFB, 0x17, 0xFE, 0x0C, 0xD0, 0xFF, 0x00, 0x59, 0xFB,
+	0x47, 0x7D, 0x3C, 0x1F, 0xFC, 0xF5, 0xEA, 0xF8, 0xEB, 0xF6, 0x2F, 0xFF, 0x00, 0x95, 0x91, 0x74,
+	0xDF, 0xFB, 0x39, 0x0D, 0x6F, 0xFF, 0x00, 0x4B, 0x2F, 0x69, 0x7D, 0x94, 0x52, 0xF8, 0xA6, 0x7B,
+	0x8F, 0xFC, 0x1E, 0x13, 0xFF, 0x00, 0x27, 0xBB, 0xF0, 0xC7, 0xFE, 0xC9, 0x4F, 0xFE, 0xE4, 0xAF,
+	0x2B, 0xEA, 0xAF, 0xDB, 0x27, 0x3F, 0xF1, 0x08, 0xCE, 0x8B, 0xFF, 0x00, 0x64, 0xAF, 0xC0, 0x7F,
+	0xFA, 0x79, 0xD2, 0x2B, 0xE5, 0x5F, 0xF8, 0x3C, 0x27, 0xFE, 0x4F, 0x77, 0xE1, 0x8F, 0xFD, 0x92,
+	0x9F, 0xFD, 0xC9, 0x5E, 0x57, 0xD5, 0x5F, 0xB6, 0x4E, 0x7F, 0xE2, 0x11, 0x9D, 0x17, 0xFE, 0xC9,
+	0x5F, 0x80, 0xFF, 0x00, 0xF4, 0xF3, 0xA4, 0x53, 0xFB, 0x4C, 0x9F, 0xF9, 0x73, 0x0F, 0x53, 0x84,
+	0xFF, 0x00, 0x83, 0x36, 0x3F, 0xE4, 0x9A, 0x7C, 0x7A, 0xFF, 0x00, 0xB0, 0xD7, 0x87, 0xFF, 0x00,
+	0xF4, 0x45, 0xED, 0x7C, 0x3F, 0xFF, 0x00, 0x04, 0x98, 0xFF, 0x00, 0x95, 0x86, 0x3C, 0x27, 0xFF,
+	0x00, 0x65, 0x5B, 0xC4, 0x7F, 0xFA, 0x4F, 0xAA, 0x57, 0xDC, 0x1F, 0xF0, 0x66, 0xC7, 0xFC, 0x93,
+	0x4F, 0x8F, 0x5F, 0xF6, 0x1A, 0xF0, 0xFF, 0x00, 0xFE, 0x88, 0xBD, 0xAF, 0x87, 0xFF, 0x00, 0xE0,
+	0x93, 0x1F, 0xF2, 0xB0, 0xC7, 0x84, 0xFF, 0x00, 0xEC, 0xAB, 0x78, 0x8F, 0xFF, 0x00, 0x49, 0xF5,
+	0x4A, 0x5F, 0x65, 0x15, 0x1F, 0x8A, 0x7E, 0x87, 0xAA, 0x7F, 0xC1, 0xDF, 0x3F, 0xF2, 0x92, 0x9F,
+	0x03, 0xFF, 0x00, 0xD9, 0x11, 0xD2, 0xFF, 0x00, 0xF4, 0xF3, 0xAB, 0xD7, 0xD8, 0xBF, 0xF0, 0x5B,
+	0x1F, 0xF9, 0x56, 0xFF, 0x00, 0xE1, 0x97, 0xFD, 0x81, 0xBC, 0x07, 0xFF, 0x00, 0xA4, 0x50, 0xD7,
+	0xC7, 0x5F, 0xF0, 0x77, 0xCF, 0xFC, 0xA4, 0xA7, 0xC0, 0xFF, 0x00, 0xF6, 0x44, 0x74, 0xBF, 0xFD,
+	0x3C, 0xEA, 0xF5, 0xF6, 0x2F, 0xFC, 0x16, 0xC7, 0xFE, 0x55, 0xBF, 0xF8, 0x65, 0xFF, 0x00, 0x60,
+	0x6F, 0x01, 0xFF, 0x00, 0xE9, 0x14, 0x34, 0x9F, 0x52, 0x3E, 0xCC, 0x0C, 0x2F, 0xF8, 0x33, 0x9F,
+	0xFE, 0x4D, 0xA7, 0xE3, 0x27, 0xFD, 0x8F, 0x1A, 0x77, 0xFE, 0x91, 0xD7, 0xE0, 0x18, 0xE9, 0x5F,
+	0xBF, 0x9F, 0xF0, 0x67, 0x39, 0xC7, 0xEC, 0xD5, 0xF1, 0x8F, 0xFE, 0xC7, 0x8D, 0x3B, 0xFF, 0x00,
+	0x48, 0xEB, 0xF0, 0x0C, 0x74, 0xA9, 0xFF, 0x00, 0x97, 0x68, 0xD6, 0x9F, 0xF1, 0xA6, 0x15, 0xF7,
+	0xF7, 0xFC, 0x1B, 0x21, 0xFF, 0x00, 0x29, 0x83, 0xF0, 0x0F, 0xFD, 0x80, 0x7C, 0x41, 0xFF, 0x00,
+	0xA6, 0xA9, 0xEB, 0xE0, 0x1A, 0xFB, 0xFB, 0xFE, 0x0D, 0x90, 0x3F, 0xF1, 0xB8, 0x3F, 0x00, 0xFF,
+	0x00, 0xD8, 0x07, 0xC4, 0x1F, 0xFA, 0x6B, 0x9E, 0x88, 0xFC, 0x45, 0xD5, 0xFE, 0x13, 0x24, 0xFF,
+	0x00, 0x83, 0x9D, 0x3F, 0xE5, 0x30, 0x9E, 0x3D, 0xFF, 0x00, 0xB0, 0x1E, 0x83, 0xFF, 0x00, 0xA6,
+	0xDB, 0x7A, 0xFC, 0xFD, 0x1D, 0x2B, 0xF4, 0x0B, 0xFE, 0x0E, 0x74, 0x39, 0xFF, 0x00, 0x82, 0xC2,
+	0x78, 0xF4, 0xFF, 0x00, 0xD4, 0x0B, 0x41, 0xFF, 0x00, 0xD3, 0x6D, 0xBD, 0x7E, 0x7E, 0x8E, 0x94,
+	0xA5, 0x1F, 0x78, 0xAA, 0x7F, 0xC0, 0x42, 0x9F, 0xBC, 0xDF, 0xE7, 0xF8, 0x2B, 0xF7, 0xEF, 0xFE,
+	0x0E, 0xB6, 0xFF, 0x00, 0x94, 0x6B, 0xFC, 0x10, 0xFF, 0x00, 0xB1, 0xF2, 0xC7, 0xFF, 0x00, 0x4C,
+	0xD7, 0x95, 0xF8, 0x08, 0x7E, 0xF3, 0x7F, 0x9F, 0xE0, 0xAF, 0xDF, 0xCF, 0xF8, 0x3A, 0xDC, 0xFF,
+	0x00, 0xC6, 0xB5, 0xBE, 0x08, 0x7F, 0xD8, 0xF9, 0x63, 0xFF, 0x00, 0xA6, 0x6B, 0xCA, 0xB8, 0xE9,
+	0x16, 0x65, 0x53, 0xF8, 0xB1, 0x37, 0xFF, 0x00, 0xE0, 0xDD, 0x0F, 0xF9, 0x41, 0x1F, 0xC5, 0x2F,
+	0xFB, 0x0E, 0x78, 0xAF, 0xFF, 0x00, 0x4D, 0x56, 0xD5, 0xF0, 0xC7, 0xFC, 0x1A, 0x61, 0xFF, 0x00,
+	0x29, 0x43, 0xBE, 0xFF, 0x00, 0xB2, 0x4F, 0xAB, 0x7F, 0xE9, 0x66, 0x9F, 0x5F, 0x73, 0xFF, 0x00,
+	0xC1, 0xBA, 0x1F, 0xF2, 0x82, 0x3F, 0x8A, 0x5F, 0xF6, 0x1C, 0xF1, 0x5F, 0xFE, 0x9A, 0xAD, 0xAB,
+	0xE1, 0x8F, 0xF8, 0x34, 0xC3, 0xFE, 0x52, 0x87, 0x7D, 0xFF, 0x00, 0x64, 0x9F, 0x56, 0xFF, 0x00,
+	0xD2, 0xCD, 0x3E, 0xAB, 0xAC, 0x49, 0xFB, 0x35, 0x0E, 0x23, 0xFE, 0x0B, 0xE3, 0xFF, 0x00, 0x29,
+	0xEB, 0xF8, 0x8D, 0xFF, 0x00, 0x61, 0xCF, 0x09, 0x7F, 0xE9, 0x8B, 0x48, 0xAF, 0xD0, 0x2F, 0xF8,
+	0x3C, 0x5F, 0xFE, 0x4D, 0xB3, 0xE0, 0xDF, 0xFD, 0x8F, 0x57, 0xBF, 0xFA, 0x46, 0xB5, 0xF9, 0xFB,
+	0xFF, 0x00, 0x05, 0xF1, 0xFF, 0x00, 0x94, 0xF5, 0xFC, 0x46, 0xFF, 0x00, 0xB0, 0xE7, 0x84, 0xBF,
+	0xF4, 0xC5, 0xA4, 0x57, 0xE8, 0x17, 0xFC, 0x1E, 0x2F, 0xFF, 0x00, 0x26, 0xD9, 0xF0, 0x6F, 0xFE,
+	0xC7, 0xAB, 0xDF, 0xFD, 0x23, 0x5A, 0x7D, 0x58, 0x7D, 0xAA, 0x66, 0xD7, 0xFC, 0x13, 0x1F, 0xFE,
+	0x55, 0x4E, 0xF8, 0x8D, 0xFF, 0x00, 0x64, 0x9F, 0xE2, 0x57, 0xFE, 0x8B, 0xD5, 0x2B, 0xE3, 0xAF,
+	0xF8, 0x34, 0x23, 0xFE, 0x52, 0x51, 0xE3, 0x8F, 0xFB, 0x21, 0xFA, 0x97, 0xFE, 0x9E, 0x74, 0x5A,
+	0xFB, 0x17, 0xFE, 0x09, 0x8F, 0xFF, 0x00, 0x2A, 0xA7, 0x7C, 0x46, 0xFF, 0x00, 0xB2, 0x4F, 0xF1,
+	0x2B, 0xFF, 0x00, 0x45, 0xEA, 0x95, 0xF1, 0xD7, 0xFC, 0x1A, 0x11, 0xFF, 0x00, 0x29, 0x28, 0xF1,
+	0xC7, 0xFD, 0x90, 0xFD, 0x4B, 0xFF, 0x00, 0x4F, 0x3A, 0x2D, 0x4F, 0x58, 0x99, 0xBF, 0xE1, 0xCF,
+	0xD4, 0xF2, 0xAF, 0xF8, 0x2B, 0x1F, 0xFC, 0xAC, 0x2F, 0xE2, 0xAF, 0xFB, 0x2A, 0x9E, 0x1A, 0xFF,
+	0x00, 0xD2, 0x7D, 0x3E, 0xBE, 0xE0, 0xFF, 0x00, 0x83, 0xC9, 0xBF, 0xE4, 0x9B, 0xFC, 0x05, 0xFF,
+	0x00, 0xB0, 0xEF, 0x88, 0x3F, 0xF4, 0x9A, 0xC6, 0xBE, 0x1F, 0xFF, 0x00, 0x82, 0xB1, 0xFF, 0x00,
+	0xCA, 0xC2, 0xFE, 0x2A, 0xFF, 0x00, 0xB2, 0xA9, 0xE1, 0xAF, 0xFD, 0x27, 0xD3, 0xEB, 0xEE, 0x0F,
+	0xF8, 0x3C, 0x9B, 0xFE, 0x49, 0xBF, 0xC0, 0x5F, 0xFB, 0x0E, 0xF8, 0x83, 0xFF, 0x00, 0x49, 0xAC,
+	0x69, 0x7D, 0xA9, 0x15, 0xFF, 0x00, 0x2F, 0x60, 0x77, 0x5F, 0xB1, 0xC7, 0xFC, 0xAA, 0x29, 0xAD,
+	0x7F, 0xD9, 0x27, 0xF1, 0xE7, 0xFE, 0x9E, 0x35, 0x7A, 0xF9, 0xC7, 0xFE, 0x0C, 0xED, 0xFF, 0x00,
+	0x93, 0x96, 0xF8, 0xCB, 0xFF, 0x00, 0x62, 0x2D, 0x8F, 0xFE, 0x96, 0xB5, 0x7D, 0x1D, 0xFB, 0x1C,
+	0x7F, 0xCA, 0xA2, 0x9A, 0xD7, 0xFD, 0x92, 0x7F, 0x1E, 0x7F, 0xE9, 0xE3, 0x57, 0xAF, 0x9C, 0x7F,
+	0xE0, 0xCE, 0xDF, 0xF9, 0x39, 0x6F, 0x8C, 0xBF, 0xF6, 0x22, 0xD8, 0xFF, 0x00, 0xE9, 0x6B, 0x55,
+	0x7D, 0xA8, 0x87, 0xFC, 0xBB, 0xA9, 0xEA, 0x7C, 0xAD, 0xFB, 0x49, 0x7F, 0xCA, 0xC5, 0x9A, 0xC7,
+	0xFD, 0x9D, 0x6D, 0xBF, 0xFE, 0x9E, 0xAD, 0xEB, 0xEC, 0x7F, 0xF8, 0x3C, 0x93, 0xFE, 0x4A, 0x57,
+	0xC0, 0x4F, 0xFB, 0x00, 0xEB, 0xFF, 0x00, 0xFA, 0x53, 0xA7, 0xD7, 0xC7, 0x1F, 0xB4, 0x97, 0xFC,
+	0xAC, 0x59, 0xAC, 0x7F, 0xD9, 0xD6, 0xDB, 0xFF, 0x00, 0xE9, 0xEA, 0xDE, 0xBE, 0xC7, 0xFF, 0x00,
+	0x83, 0xC9, 0x3F, 0xE4, 0xA5, 0x7C, 0x04, 0xFF, 0x00, 0xB0, 0x0E, 0xBF, 0xFF, 0x00, 0xA5, 0x3A,
+	0x7D, 0x4C, 0x7E, 0xD1, 0x51, 0xFE, 0x2C, 0x3D, 0x0F, 0x6F, 0xF8, 0x7B, 0xFF, 0x00, 0x2A, 0x8B,
+	0xDC, 0x7F, 0xD9, 0x29, 0xD5, 0x3F, 0xF4, 0xF1, 0x3D, 0x78, 0x7F, 0xFC, 0x19, 0xB1, 0xFF, 0x00,
+	0x25, 0x2B, 0xE3, 0xD7, 0xFD, 0x81, 0x3C, 0x3D, 0xFF, 0x00, 0xA3, 0xB5, 0x0A, 0xF7, 0x0F, 0x87,
+	0xBF, 0xF2, 0xA8, 0xBD, 0xC7, 0xFD, 0x92, 0x9D, 0x53, 0xFF, 0x00, 0x4F, 0x13, 0xD7, 0x87, 0xFF,
+	0x00, 0xC1, 0x9B, 0x1F, 0xF2, 0x52, 0xBE, 0x3D, 0x7F, 0xD8, 0x13, 0xC3, 0xDF, 0xFA, 0x3B, 0x50,
+	0xAD, 0x57, 0xC4, 0x89, 0x8F, 0xF0, 0xE4, 0x7C, 0xAB, 0xF0, 0xFB, 0xFE, 0x56, 0x6C, 0x9F, 0xFE,
+	0xCF, 0x1F, 0x54, 0xFF, 0x00, 0xD4, 0x86, 0x7A, 0xFA, 0x37, 0xFE, 0x0F, 0x18, 0xFF, 0x00, 0x93,
+	0x90, 0xF8, 0x37, 0xFF, 0x00, 0x62, 0x1E, 0xA1, 0xFF, 0x00, 0xA5, 0xAB, 0x5F, 0x39, 0x7C, 0x3E,
+	0xFF, 0x00, 0x95, 0x9B, 0x27, 0xFF, 0x00, 0xB3, 0xC7, 0xD5, 0x3F, 0xF5, 0x21, 0x9E, 0xBE, 0x8D,
+	0xFF, 0x00, 0x83, 0xC6, 0x3F, 0xE4, 0xE4, 0x3E, 0x0D, 0xFF, 0x00, 0xD8, 0x87, 0xA8, 0x7F, 0xE9,
+	0x6A, 0xD4, 0x74, 0x66, 0x90, 0xFE, 0x24, 0x3D, 0x0F, 0xA4, 0x3F, 0x6C, 0x9C, 0xFF, 0x00, 0xC4,
+	0x23, 0x5A, 0x3F, 0xFD, 0x92, 0xBF, 0x01, 0xFF, 0x00, 0xE9, 0xEB, 0x48, 0xAF, 0x27, 0xFF, 0x00,
+	0x83, 0x32, 0x7E, 0xEF, 0xED, 0x1B, 0xFE, 0xE7, 0x83, 0xFF, 0x00, 0xF7, 0x3D, 0x5E, 0xB1, 0xFB,
+	0x64, 0xE7, 0xFE, 0x21, 0x1A, 0xD1, 0xFF, 0x00, 0xEC, 0x95, 0xF8, 0x0F, 0xFF, 0x00, 0x4F, 0x5A,
+	0x45, 0x79, 0x3F, 0xFC, 0x19, 0x93, 0xF7, 0x7F, 0x68, 0xDF, 0xF7, 0x3C, 0x1F, 0xFF, 0x00, 0xB9,
+	0xEA, 0x3E, 0xD2, 0x31, 0xFF, 0x00, 0x97, 0x72, 0xF5, 0x3E, 0x3B, 0xFD, 0x8B, 0xBF, 0xE5, 0x64,
+	0x7D, 0x37, 0xFE, 0xCE, 0x43, 0x5B, 0xFF, 0x00, 0xD2, 0xCB, 0xCA, 0xF7, 0x2F, 0xF8, 0x3C, 0x27,
+	0xFE, 0x4F, 0x77, 0xE1, 0x8F, 0xFD, 0x92, 0x9F, 0xFD, 0xC9, 0x5E, 0x57, 0x86, 0xFE, 0xC5, 0xDF,
+	0xF2, 0xB2, 0x3E, 0x9B, 0xFF, 0x00, 0x67, 0x21, 0xAD, 0xFF, 0x00, 0xE9, 0x65, 0xE5, 0x7B, 0x97,
+	0xFC, 0x1E, 0x13, 0xFF, 0x00, 0x27, 0xBB, 0xF0, 0xC7, 0xFE, 0xC9, 0x4F, 0xFE, 0xE4, 0xAF, 0x28,
+	0xFB, 0x26, 0xDF, 0xF2, 0xFE, 0x3E, 0x87, 0xD4, 0xFF, 0x00, 0xF0, 0x53, 0x9F, 0xF9, 0x55, 0x53,
+	0xE1, 0xC7, 0xFD, 0x92, 0xBF, 0x86, 0x7F, 0xFA, 0x2F, 0x4B, 0xAC, 0x2F, 0xF8, 0x33, 0xA7, 0xFE,
+	0x4D, 0xA7, 0xE3, 0x1F, 0xFD, 0x8F, 0x36, 0x1F, 0xFA, 0x45, 0x5B, 0xBF, 0xF0, 0x53, 0x9F, 0xF9,
+	0x55, 0x53, 0xE1, 0xC7, 0xFD, 0x92, 0xBF, 0x86, 0x7F, 0xFA, 0x2F, 0x4B, 0xAC, 0x2F, 0xF8, 0x33,
+	0xA7, 0xFE, 0x4D, 0xA7, 0xE3, 0x1F, 0xFD, 0x8F, 0x36, 0x1F, 0xFA, 0x45, 0x47, 0xDA, 0x46, 0x4F,
+	0xF8, 0x3F, 0x33, 0xF3, 0x9F, 0xFE, 0x08, 0x95, 0xFF, 0x00, 0x29, 0xCF, 0xF8, 0x63, 0xFF, 0x00,
+	0x63, 0xD6, 0xB1, 0xFF, 0x00, 0xA4, 0x3A, 0x8D, 0x7A, 0xB7, 0xFC, 0x1D, 0x95, 0xFF, 0x00, 0x29,
+	0x46, 0xB1, 0xFF, 0x00, 0xB2, 0x4F, 0xA4, 0x7F, 0xE9, 0x5D, 0xF5, 0x79, 0x4F, 0xFC, 0x11, 0x2B,
+	0xFE, 0x53, 0x9F, 0xF0, 0xC7, 0xFE, 0xC7, 0xAD, 0x63, 0xFF, 0x00, 0x48, 0x75, 0x1A, 0xF5, 0x6F,
+	0xF8, 0x3B, 0x2B, 0xFE, 0x52, 0x8D, 0x63, 0xFF, 0x00, 0x64, 0x9F, 0x48, 0xFF, 0x00, 0xD2, 0xBB,
+	0xEA, 0x97, 0xF0, 0x9B, 0x7F, 0xCB, 0xE8, 0xFA, 0x1F, 0x98, 0xA7, 0xAD, 0x14, 0x1E, 0xB4, 0x56,
+	0x66, 0xE1, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x06, 0xA7, 0x82, 0xBC, 0x2F, 0x77, 0xE3,
+	0x6F, 0x18, 0xE9, 0x3E, 0x0C, 0xD3, 0x93, 0xFD, 0x2B, 0x58, 0xD4, 0xED, 0xAC, 0x61, 0xFF, 0x00,
+	0x69, 0xE6, 0x94, 0x46, 0xA3, 0xF3, 0x22, 0xBF, 0x70, 0xB4, 0xDB, 0x0B, 0x4D, 0x2B, 0x4F, 0xB7,
+	0xD2, 0xEC, 0x22, 0xF2, 0xE0, 0xB6, 0x85, 0x62, 0x85, 0x3F, 0xBA, 0x8A, 0x30, 0x07, 0xE4, 0x2B,
+	0xF3, 0xC7, 0xFE, 0x08, 0x23, 0xFB, 0x2D, 0x68, 0xBF, 0xB5, 0xA7, 0xFC, 0x14, 0xEF, 0xC0, 0xBE,
+	0x0B, 0xF1, 0x6E, 0x97, 0x35, 0xDF, 0x87, 0xF4, 0x38, 0x6F, 0xB5, 0xFF, 0x00, 0x10, 0x2C, 0x2C,
+	0xCB, 0xFB, 0x9B, 0x4B, 0x66, 0xF2, 0xBE, 0x64, 0xE4, 0x7F, 0xA4, 0xCD, 0x6C, 0x3F, 0xE0, 0x75,
+	0xFD, 0x24, 0x7F, 0xC3, 0xB5, 0x3F, 0x64, 0x62, 0x72, 0xFE, 0x04, 0xD4, 0x33, 0xFC, 0x5F, 0xF1,
+	0x3E, 0xB8, 0xEB, 0xFF, 0x00, 0x7D, 0xD6, 0xD4, 0x7E, 0x13, 0x8B, 0x15, 0x2F, 0x79, 0x47, 0xB1,
+	0xF9, 0x97, 0x5F, 0xA6, 0x9F, 0xF0, 0x4D, 0x5F, 0xF9, 0x34, 0x7D, 0x0F, 0xFE, 0xBF, 0xAF, 0xFF,
+	0x00, 0xF4, 0xA5, 0xA8, 0xFF, 0x00, 0x87, 0x69, 0xFE, 0xC8, 0x7F, 0xF4, 0x22, 0x6A, 0x1F, 0xF8,
+	0x3E, 0xB8, 0xFF, 0x00, 0xE3, 0x95, 0xEA, 0xDF, 0x0A, 0xFE, 0x15, 0x78, 0x23, 0xE0, 0xBF, 0x83,
+	0x61, 0xF0, 0x0F, 0x80, 0x34, 0xF9, 0x2C, 0xF4, 0xCB, 0x69, 0x24, 0x6B, 0x78, 0x64, 0xB8, 0x32,
+	0x7C, 0xD2, 0x36, 0xE6, 0x24, 0x9E, 0x4F, 0x27, 0xBD, 0x6C, 0x72, 0x1F, 0x9C, 0x7F, 0xF0, 0x54,
+	0x6F, 0xF9, 0x3B, 0xBD, 0x53, 0xFE, 0xC1, 0x3A, 0x7F, 0xFE, 0x8A, 0x15, 0xF3, 0xCD, 0x7E, 0xAE,
+	0x7C, 0x69, 0xFD, 0x83, 0x7E, 0x04, 0xFC, 0x7D, 0xF1, 0xE4, 0xDF, 0x10, 0xFE, 0x21, 0x47, 0xAB,
+	0xB6, 0xA5, 0x71, 0x0C, 0x70, 0x4A, 0xDA, 0x7E, 0xA1, 0xE5, 0xA1, 0x44, 0x5C, 0x2E, 0x46, 0xC3,
+	0x8E, 0x3D, 0xEB, 0x94, 0x5F, 0xF8, 0x25, 0x1F, 0xEC, 0xA4, 0xEA, 0x1C, 0xC5, 0xE2, 0x2E, 0x79,
+	0xE3, 0x58, 0xFF, 0x00, 0xEC, 0x28, 0x3B, 0x23, 0x5E, 0x11, 0x8A, 0x47, 0xE6, 0x75, 0x15, 0xFA,
+	0x65, 0xFF, 0x00, 0x0E, 0xA1, 0xFD, 0x94, 0x7F, 0xE7, 0x9F, 0x88, 0xBF, 0xF0, 0x71, 0xFF, 0x00,
+	0xD8, 0x51, 0xFF, 0x00, 0x0E, 0xA1, 0xFD, 0x94, 0x7F, 0xE7, 0x9F, 0x88, 0xBF, 0xF0, 0x71, 0xFF,
+	0x00, 0xD8, 0x50, 0x3F, 0xAC, 0x53, 0x3F, 0x33, 0x6B, 0xF6, 0x3F, 0xF6, 0x61, 0xFF, 0x00, 0x93,
+	0x6A, 0xF8, 0x79, 0xFF, 0x00, 0x62, 0x36, 0x93, 0xFF, 0x00, 0xA4, 0x71, 0x57, 0x90, 0xFF, 0x00,
+	0xC3, 0xA8, 0xBF, 0x65, 0x1F, 0xF9, 0xE5, 0xE2, 0x3F, 0xFC, 0x1C, 0x7F, 0xF6, 0x15, 0xF4, 0x27,
+	0x82, 0xFC, 0x29, 0xA4, 0xF8, 0x0B, 0xC1, 0xDA, 0x4F, 0x81, 0xB4, 0x11, 0x27, 0xD8, 0x74, 0x5D,
+	0x32, 0xDE, 0xC2, 0xCB, 0xCE, 0x7D, 0xCF, 0xE4, 0xC3, 0x1A, 0xC6, 0x9B, 0x8F, 0x73, 0xB5, 0x46,
+	0x4F, 0x73, 0x41, 0x95, 0x6A, 0x91, 0xA8, 0x95, 0xBA, 0x1F, 0x96, 0x9F, 0xB6, 0x9F, 0xFC, 0x9D,
+	0x77, 0x8D, 0xBF, 0xEC, 0x38, 0x7F, 0xF4, 0x15, 0xAF, 0x2C, 0x4F, 0xB8, 0x3E, 0x95, 0xFA, 0x9B,
+	0xE3, 0xAF, 0xD8, 0x3B, 0xF6, 0x6B, 0xF8, 0x91, 0xE3, 0x3B, 0xEF, 0x1E, 0x78, 0xB3, 0xC1, 0xD7,
+	0x57, 0x1A, 0x8E, 0xA9, 0x75, 0xE7, 0xDE, 0x4C, 0xBA, 0xB4, 0xEA, 0x0B, 0x0C, 0xF3, 0x80, 0xF8,
+	0x1C, 0xF6, 0x15, 0x8E, 0xBF, 0xF0, 0x4D, 0x2F, 0xD9, 0x10, 0x0C, 0x37, 0x81, 0x2F, 0xF3, 0xFF,
+	0x00, 0x61, 0xEB, 0x8F, 0xFE, 0x39, 0x41, 0xCE, 0x7E, 0x65, 0xD1, 0x5F, 0xA6, 0x9F, 0xF0, 0xED,
+	0x3F, 0xD9, 0x0F, 0xFE, 0x84, 0x4D, 0x43, 0xFF, 0x00, 0x07, 0xD7, 0x1F, 0xFC, 0x72, 0x8F, 0xF8,
+	0x76, 0x9F, 0xEC, 0x87, 0xFF, 0x00, 0x42, 0x26, 0xA1, 0xFF, 0x00, 0x83, 0xEB, 0x8F, 0xFE, 0x39,
+	0x40, 0x1F, 0x99, 0x75, 0xF7, 0xA7, 0xFC, 0x12, 0x17, 0xFE, 0x49, 0xAF, 0x8C, 0x3F, 0xEC, 0x39,
+	0x07, 0xFE, 0x89, 0xAF, 0x40, 0xFF, 0x00, 0x87, 0x69, 0xFE, 0xC8, 0x7F, 0xF4, 0x22, 0x6A, 0x1F,
+	0xF8, 0x3E, 0xB8, 0xFF, 0x00, 0xE3, 0x95, 0xDE, 0x7C, 0x0E, 0xF8, 0x0D, 0xF0, 0xCB, 0xF6, 0x7B,
+	0x4D, 0x63, 0xC3, 0x9F, 0x0C, 0x34, 0x49, 0xAC, 0xAD, 0x6F, 0x7C, 0x8B, 0xA9, 0xD2, 0x6B, 0xD9,
+	0x26, 0xDF, 0x27, 0xEF, 0x10, 0x72, 0xF9, 0xC7, 0x0A, 0x3A, 0x50, 0x07, 0xC4, 0x5F, 0xF0, 0x55,
+	0x1F, 0xF9, 0x39, 0x9B, 0x7F, 0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0xFD, 0x56,
+	0xF8, 0xA9, 0xFB, 0x21, 0x7C, 0x0A, 0xF8, 0xF5, 0xE3, 0x29, 0x7C, 0x5D, 0xF1, 0x3B, 0xC2, 0xB7,
+	0x17, 0x97, 0xF0, 0xC5, 0x1D, 0xB4, 0x73, 0x43, 0xA9, 0x4F, 0x16, 0x23, 0x45, 0x27, 0xA2, 0x90,
+	0x3A, 0xC8, 0xD5, 0xCE, 0xFF, 0x00, 0xC3, 0xB4, 0xFF, 0x00, 0x64, 0x3F, 0xFA, 0x11, 0x35, 0x0F,
+	0xFC, 0x1F, 0x5C, 0x7F, 0xF1, 0xCA, 0x00, 0xFC, 0xCB, 0xA2, 0xBF, 0x4D, 0x3F, 0xE1, 0xDA, 0x7F,
+	0xB2, 0x1F, 0xFD, 0x08, 0x9A, 0x87, 0xFE, 0x0F, 0xAE, 0x3F, 0xF8, 0xE5, 0x1F, 0xF0, 0xED, 0x3F,
+	0xD9, 0x0F, 0xFE, 0x84, 0x4D, 0x43, 0xFF, 0x00, 0x07, 0xD7, 0x1F, 0xFC, 0x72, 0x80, 0x3F, 0x32,
+	0xFB, 0x7E, 0x15, 0xF7, 0x47, 0xFC, 0x12, 0x03, 0xFE, 0x45, 0xCF, 0x1F, 0x7F, 0xD8, 0x42, 0xC3,
+	0xFF, 0x00, 0x45, 0xCD, 0x5E, 0x98, 0xFF, 0x00, 0xF0, 0x4D, 0x6F, 0xD9, 0x0E, 0x21, 0xE6, 0x7F,
+	0xC2, 0x07, 0x7F, 0xF2, 0x91, 0x9F, 0xF8, 0x9E, 0x5D, 0x1E, 0x33, 0xCF, 0xDD, 0x93, 0x35, 0xE8,
+	0x1F, 0x04, 0x7F, 0x67, 0x5F, 0x85, 0x7F, 0xB3, 0xBD, 0x8E, 0xA7, 0x67, 0xF0, 0xBB, 0x44, 0x9A,
+	0xCA, 0x3D, 0x4D, 0xA1, 0x7B, 0xC4, 0x9A, 0xFA, 0x49, 0xF7, 0x3C, 0x6A, 0x55, 0x79, 0x76, 0x24,
+	0x70, 0xD4, 0x01, 0xF0, 0xF7, 0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B, 0x5F,
+	0xFD, 0x0E, 0x5A, 0xF9, 0xB2, 0xBF, 0x55, 0xBE, 0x2A, 0x7E, 0xC8, 0x5F, 0x02, 0xBE, 0x3D, 0x78,
+	0xCA, 0x5F, 0x17, 0x7C, 0x4E, 0xF0, 0xAD, 0xC5, 0xE5, 0xFC, 0x31, 0x47, 0x6D, 0x1C, 0xD0, 0xEA,
+	0x53, 0xC5, 0x88, 0xD1, 0x49, 0xE8, 0xA4, 0x0E, 0xB2, 0x35, 0x73, 0xBF, 0xF0, 0xED, 0x3F, 0xD9,
+	0x0F, 0xFE, 0x84, 0x4D, 0x43, 0xFF, 0x00, 0x07, 0xD7, 0x1F, 0xFC, 0x72, 0x80, 0x3F, 0x32, 0xE8,
+	0xAF, 0xD3, 0x4F, 0xF8, 0x76, 0x9F, 0xEC, 0x87, 0xFF, 0x00, 0x42, 0x26, 0xA1, 0xFF, 0x00, 0x83,
+	0xEB, 0x8F, 0xFE, 0x39, 0x47, 0xFC, 0x3B, 0x4F, 0xF6, 0x43, 0xFF, 0x00, 0xA1, 0x13, 0x50, 0xFF,
+	0x00, 0xC1, 0xF5, 0xC7, 0xFF, 0x00, 0x1C, 0xA0, 0x0F, 0xCC, 0xBE, 0xDF, 0x85, 0x7D, 0xC9, 0xFF,
+	0x00, 0x04, 0x86, 0xFF, 0x00, 0x91, 0x6F, 0xC7, 0xBF, 0xF6, 0x10, 0xB1, 0xFF, 0x00, 0xD1, 0x73,
+	0x57, 0xA8, 0x3F, 0xFC, 0x13, 0x5B, 0xF6, 0x43, 0x88, 0x79, 0x9F, 0xF0, 0x81, 0xDF, 0xFC, 0xA4,
+	0x67, 0xFE, 0x27, 0x97, 0x47, 0x8C, 0xF3, 0xF7, 0x64, 0xCD, 0x77, 0xDF, 0x04, 0xFF, 0x00, 0x67,
+	0x4F, 0x85, 0x9F, 0xB3, 0xCD, 0xBD, 0xFD, 0x97, 0xC2, 0xED, 0x1A, 0x7B, 0x18, 0xB5, 0x49, 0x21,
+	0x6B, 0xE5, 0x9A, 0xFA, 0x49, 0xF2, 0xD1, 0x82, 0x17, 0x99, 0x18, 0x91, 0xC1, 0xA5, 0x2D, 0x50,
+	0x1E, 0x81, 0x07, 0xFA, 0xA5, 0xA7, 0x54, 0x36, 0x25, 0xFC, 0x9C, 0x39, 0x5C, 0x86, 0xC1, 0xDA,
+	0xB8, 0x19, 0xC0, 0xCF, 0xEB, 0x9A, 0x9A, 0x98, 0x6F, 0xA8, 0x52, 0x39, 0xDA, 0x85, 0x8F, 0xA5,
+	0x2D, 0x0D, 0xCA, 0x91, 0x40, 0x1F, 0x2E, 0x7E, 0xDE, 0xDF, 0xB5, 0x67, 0xC5, 0x2F, 0xD9, 0x9B,
+	0x5D, 0xF0, 0xCC, 0x5F, 0x0E, 0xE0, 0xD2, 0xA4, 0x1A, 0xDD, 0xAD, 0xCC, 0x97, 0x4D, 0xA8, 0x5A,
+	0x97, 0x07, 0xCA, 0x68, 0xC2, 0x91, 0x87, 0xFF, 0x00, 0x6F, 0xB5, 0x78, 0x17, 0xFC, 0x3D, 0x53,
+	0xF6, 0x9E, 0xFF, 0x00, 0x9F, 0x3F, 0x0A, 0xFF, 0x00, 0xE0, 0xAE, 0x5F, 0xFE, 0x2E, 0xBB, 0x4F,
+	0xF8, 0x2B, 0xE0, 0xDB, 0xE2, 0x2F, 0x03, 0x28, 0xED, 0x63, 0x7D, 0xFF, 0x00, 0xA1, 0xC7, 0x5F,
+	0x1B, 0xD0, 0x07, 0xD2, 0x9F, 0xF0, 0xF5, 0x4F, 0xDA, 0x7B, 0xFE, 0x7C, 0xFC, 0x2B, 0xFF, 0x00,
+	0x82, 0xB9, 0x7F, 0xF8, 0xBA, 0x3F, 0xE1, 0xEA, 0x9F, 0xB4, 0xF7, 0xFC, 0xF9, 0xF8, 0x57, 0xFF,
+	0x00, 0x05, 0x72, 0xFF, 0x00, 0xF1, 0x75, 0xF3, 0x5D, 0x14, 0x01, 0xF4, 0x99, 0xFF, 0x00, 0x82,
+	0xA9, 0xFE, 0xD3, 0xE4, 0x63, 0xEC, 0x5E, 0x16, 0xFC, 0x34, 0xB9, 0x7F, 0xF8, 0xBA, 0xF7, 0x0F,
+	0xD8, 0x57, 0xF6, 0xC8, 0xF8, 0xB7, 0xFB, 0x47, 0xFC, 0x47, 0xD6, 0x3C, 0x2F, 0xF1, 0x02, 0xDB,
+	0x47, 0x8E, 0x0B, 0x1D, 0x25, 0xAE, 0xE3, 0xFE, 0xCD, 0xB4, 0x74, 0x62, 0xDE, 0x74, 0x51, 0xF3,
+	0xB9, 0xCF, 0xAD, 0x7E, 0x7E, 0x0E, 0xB5, 0xF5, 0x7F, 0xFC, 0x12, 0x47, 0xFE, 0x4B, 0x4F, 0x89,
+	0xBF, 0xEC, 0x54, 0x5F, 0xFD, 0x29, 0x8A, 0x80, 0x3E, 0x8D, 0xFD, 0xBB, 0x7E, 0x3F, 0xF8, 0xE3,
+	0xF6, 0x71, 0xF8, 0x57, 0xA5, 0xF8, 0xD7, 0xE1, 0xF4, 0x36, 0x2D, 0x79, 0x79, 0xE2, 0x08, 0xAC,
+	0x59, 0x75, 0x08, 0xB7, 0xA7, 0x96, 0x60, 0x9D, 0xDB, 0x8C, 0x8C, 0x7F, 0xAB, 0x15, 0xF2, 0xBF,
+	0xFC, 0x3D, 0x53, 0xF6, 0x9E, 0xFF, 0x00, 0x9F, 0x3F, 0x0A, 0xFF, 0x00, 0xE0, 0xAE, 0x5F, 0xFE,
+	0x2E, 0xBD, 0xD3, 0xFE, 0x0A, 0xCB, 0xFF, 0x00, 0x26, 0xEF, 0xA1, 0xFF, 0x00, 0xD8, 0xE5, 0x0F,
+	0xFE, 0x92, 0xDC, 0xD7, 0xE7, 0xBD, 0x4C, 0x7A, 0x8E, 0xCA, 0x29, 0x24, 0x7D, 0x29, 0xFF, 0x00,
+	0x0F, 0x54, 0xFD, 0xA7, 0xBF, 0xE7, 0xCF, 0xC2, 0xBF, 0xF8, 0x2B, 0x97, 0xFF, 0x00, 0x8B, 0xA3,
+	0xFE, 0x1E, 0xA9, 0xFB, 0x4F, 0x7F, 0xCF, 0x9F, 0x85, 0x7F, 0xF0, 0x57, 0x2F, 0xFF, 0x00, 0x17,
+	0x5F, 0x35, 0xD1, 0x54, 0x23, 0xE9, 0x4F, 0xF8, 0x7A, 0xA7, 0xED, 0x3D, 0xFF, 0x00, 0x3E, 0x7E,
+	0x15, 0xFF, 0x00, 0xC1, 0x5C, 0xBF, 0xFC, 0x5D, 0x7A, 0x67, 0xEC, 0x87, 0xFB, 0x78, 0xFC, 0x6F,
+	0xF8, 0xE9, 0xF1, 0xDB, 0x4D, 0xF8, 0x71, 0xE3, 0x6B, 0x3D, 0x0A, 0x3B, 0x2B, 0xCB, 0x59, 0xDE,
+	0x46, 0xB1, 0xB1, 0x74, 0x93, 0xF7, 0x76, 0xEE, 0xFF, 0x00, 0xC4, 0xF5, 0xF0, 0xFD, 0x7B, 0xD7,
+	0xFC, 0x13, 0x63, 0xFE, 0x4E, 0xE7, 0x41, 0xFF, 0x00, 0xB0, 0x7E, 0xA1, 0xFF, 0x00, 0xA4, 0xEF,
+	0x40, 0x1F, 0x72, 0xFE, 0xD7, 0x7F, 0x15, 0x7C, 0x4B, 0xF0, 0x4B, 0xF6, 0x7F, 0xD7, 0x3E, 0x27,
+	0x78, 0x36, 0x3B, 0x76, 0xD4, 0xB4, 0xD7, 0xB5, 0x16, 0xC2, 0xF2, 0x3D, 0xD1, 0x96, 0x92, 0xEA,
+	0x28, 0x8E, 0x57, 0x23, 0x3C, 0x39, 0xEF, 0x5F, 0x1A, 0x0F, 0xF8, 0x2A, 0x9F, 0xED, 0x3B, 0x8E,
+	0x2C, 0xBC, 0x2B, 0xFF, 0x00, 0x82, 0xC9, 0x3F, 0xF8, 0xBA, 0xFA, 0xAB, 0xFE, 0x0A, 0x29, 0xFF,
+	0x00, 0x26, 0x77, 0xE2, 0xDF, 0xFA, 0xE9, 0x63, 0xFF, 0x00, 0xA5, 0xB0, 0x57, 0xE6, 0x0D, 0x4C,
+	0x7A, 0xFF, 0x00, 0x5D, 0x10, 0x59, 0x46, 0x2A, 0xC7, 0xD2, 0x9F, 0xF0, 0xF5, 0x4F, 0xDA, 0x7B,
+	0xFE, 0x7C, 0xFC, 0x2B, 0xFF, 0x00, 0x82, 0xB9, 0x7F, 0xF8, 0xBA, 0x3F, 0xE1, 0xEA, 0x9F, 0xB4,
+	0xF7, 0xFC, 0xF9, 0xF8, 0x57, 0xFF, 0x00, 0x05, 0x72, 0xFF, 0x00, 0xF1, 0x75, 0xF3, 0x5D, 0x15,
+	0x40, 0x7D, 0x29, 0xFF, 0x00, 0x0F, 0x54, 0xFD, 0xA7, 0xBF, 0xE7, 0xCF, 0xC2, 0xBF, 0xF8, 0x2B,
+	0x97, 0xFF, 0x00, 0x8B, 0xAE, 0xAB, 0xE0, 0x67, 0xFC, 0x14, 0x73, 0xF6, 0x83, 0xF8, 0x8F, 0xF1,
+	0x93, 0xC3, 0x1E, 0x03, 0xF1, 0x15, 0x8F, 0x87, 0x56, 0xCF, 0x57, 0xD6, 0x2D, 0xED, 0x26, 0x7B,
+	0x7D, 0x3E, 0x45, 0x93, 0x6C, 0x92, 0x81, 0xC6, 0x5F, 0xDA, 0xBE, 0x41, 0xAF, 0x44, 0xFD, 0x92,
+	0xBF, 0xE4, 0xE7, 0x3C, 0x03, 0xFF, 0x00, 0x63, 0x55, 0xA7, 0xFE, 0x84, 0x28, 0x03, 0xF4, 0xE3,
+	0xE3, 0xBF, 0x89, 0xB5, 0x8F, 0x05, 0xFC, 0x0E, 0xF1, 0x77, 0x8C, 0xBC, 0x36, 0xF1, 0xAE, 0xA1,
+	0xA4, 0xF8, 0x62, 0xFA, 0xF2, 0xC9, 0xE6, 0x5F, 0x94, 0x4D, 0x1D, 0xBB, 0xB2, 0x64, 0x77, 0xF9,
+	0x94, 0x71, 0x5F, 0x9C, 0xBF, 0xF0, 0xF4, 0x9F, 0xDA, 0xE1, 0xC6, 0xE8, 0xFC, 0x57, 0xA5, 0x85,
+	0x6E, 0x54, 0x0D, 0x12, 0x1E, 0x07, 0xE3, 0xCF, 0xE7, 0xCD, 0x7E, 0x87, 0x7E, 0xD4, 0x9F, 0xF2,
+	0x6D, 0x1F, 0x11, 0x3F, 0xEC, 0x49, 0xD4, 0xFF, 0x00, 0xF4, 0x96, 0x4A, 0xFC, 0x6B, 0xAF, 0x89,
+	0xE2, 0x9C, 0x76, 0x2B, 0x0B, 0x5A, 0x9A, 0xA3, 0x37, 0x1B, 0xA6, 0xF4, 0xFB, 0x8F, 0xDE, 0xBC,
+	0x1D, 0xE1, 0xFC, 0x97, 0x39, 0xCB, 0x71, 0x52, 0xC7, 0x50, 0x8D, 0x47, 0x19, 0xC6, 0xCE, 0x49,
+	0x36, 0xAE, 0x9D, 0xF7, 0x3E, 0x86, 0xFF, 0x00, 0x87, 0xA3, 0xFE, 0xD7, 0x7F, 0xF4, 0x36, 0x69,
+	0x9F, 0xF8, 0x25, 0x82, 0x8F, 0xF8, 0x7A, 0x3F, 0xED, 0x77, 0xFF, 0x00, 0x43, 0x66, 0x99, 0xFF,
+	0x00, 0x82, 0x48, 0x2B, 0xE7, 0x9A, 0x2B, 0xE4, 0xFF, 0x00, 0xB6, 0x33, 0x5F, 0xF9, 0xFC, 0xCF,
+	0xD9, 0x3F, 0xD4, 0x6E, 0x10, 0xFF, 0x00, 0xA0, 0x2A, 0x7F, 0xF8, 0x0A, 0xFF, 0x00, 0x23, 0xE8,
+	0x61, 0xFF, 0x00, 0x05, 0x47, 0xFD, 0xAE, 0xC7, 0xFC, 0xCD, 0x9A, 0x67, 0xFE, 0x09, 0x20, 0xAF,
+	0x62, 0xFD, 0x85, 0xBF, 0x6E, 0x5F, 0xDA, 0x07, 0xE3, 0x8F, 0xED, 0x05, 0x63, 0xF0, 0xEF, 0xE2,
+	0x1E, 0xBB, 0x63, 0x75, 0xA6, 0xDD, 0x69, 0xF7, 0x32, 0x3A, 0xC3, 0xA7, 0x47, 0x13, 0x07, 0x45,
+	0x0C, 0x39, 0x5F, 0x63, 0x5F, 0x0B, 0xD7, 0xD0, 0xFF, 0x00, 0xF0, 0x4B, 0xCF, 0xF9, 0x3B, 0xAD,
+	0x27, 0xFE, 0xC1, 0x57, 0xDF, 0xFA, 0x28, 0xD7, 0xA1, 0x95, 0xE6, 0x99, 0x85, 0x4C, 0xC2, 0x9C,
+	0x65, 0x55, 0xB4, 0xDD, 0x9A, 0xBE, 0xE7, 0xCC, 0xF1, 0x87, 0x07, 0xF0, 0xBE, 0x0B, 0x85, 0xF1,
+	0x75, 0xE8, 0xE1, 0x21, 0x19, 0xC6, 0x0D, 0xA6, 0xA2, 0x93, 0x4F, 0xA5, 0x8F, 0xBE, 0x7F, 0x6B,
+	0xFF, 0x00, 0x8C, 0x1E, 0x2F, 0xF8, 0x1B, 0xF0, 0x23, 0x54, 0xF8, 0x91, 0xE0, 0xD8, 0xED, 0x1A,
+	0xFA, 0xCE, 0xE2, 0xDA, 0x3B, 0x71, 0x7D, 0x0E, 0xF4, 0xFD, 0xE4, 0xA9, 0x19, 0xCF, 0xCE, 0x3F,
+	0xBD, 0x5F, 0x1B, 0x2F, 0xFC, 0x15, 0x4F, 0xF6, 0x9C, 0x03, 0x09, 0x67, 0xE1, 0x5D, 0xBD, 0xB6,
+	0xE9, 0x72, 0x7F, 0x47, 0xAF, 0xA8, 0x7F, 0xE0, 0xA5, 0x3F, 0xF2, 0x69, 0x1A, 0xE7, 0xFD, 0x7E,
+	0x58, 0xFF, 0x00, 0xE9, 0x42, 0xD7, 0xE6, 0x5D, 0x7E, 0xA4, 0x7F, 0x23, 0xAD, 0x8F, 0xA5, 0x3F,
+	0xE1, 0xEA, 0x9F, 0xB4, 0xF7, 0xFC, 0xF9, 0xF8, 0x57, 0xFF, 0x00, 0x05, 0x72, 0xFF, 0x00, 0xF1,
+	0x75, 0xF0, 0x7F, 0xFC, 0x17, 0xF3, 0xE3, 0xC7, 0xC5, 0x2F, 0xDA, 0xE7, 0xF6, 0x5F, 0xF0, 0xFF,
+	0x00, 0x8B, 0x3C, 0x75, 0xA4, 0xE8, 0xBE, 0x77, 0x80, 0x7C, 0x48, 0xB7, 0x70, 0xDE, 0x69, 0xB6,
+	0x72, 0xA4, 0x90, 0x5B, 0xDD, 0x2F, 0xD9, 0xE4, 0x07, 0xF7, 0xBD, 0x0C, 0xC2, 0xDA, 0xBD, 0x72,
+	0xB9, 0x4F, 0x8E, 0xBF, 0x0E, 0x6D, 0xBE, 0x2D, 0xFC, 0x18, 0xF1, 0x3F, 0xC3, 0x89, 0x47, 0xCD,
+	0xAC, 0x68, 0xF3, 0x41, 0x6E, 0xDF, 0xDD, 0xB9, 0xDA, 0x7C, 0x83, 0xFF, 0x00, 0x01, 0x75, 0x12,
+	0x7F, 0xC0, 0x2A, 0x65, 0xF0, 0x9A, 0x53, 0x92, 0x8D, 0x4B, 0xB3, 0xF1, 0x38, 0x2A, 0xA0, 0xD8,
+	0x88, 0x15, 0x57, 0x85, 0x51, 0x9E, 0x3D, 0xB9, 0x27, 0xF9, 0x9A, 0x2A, 0x4B, 0xAB, 0x59, 0xEC,
+	0x6E, 0x64, 0xB2, 0xB9, 0x8B, 0x64, 0x90, 0xC8, 0x52, 0x44, 0xFE, 0xEB, 0x03, 0x82, 0x3F, 0x3A,
+	0x8E, 0xB9, 0x7A, 0xD8, 0xF5, 0x17, 0x70, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA1,
+	0x7A, 0x9F, 0xC3, 0xF9, 0x1A, 0x28, 0x5E, 0xA7, 0xF0, 0xFE, 0x46, 0xA9, 0x7C, 0x48, 0x1E, 0xCC,
+	0xFE, 0x86, 0x3F, 0xE0, 0xF0, 0x4F, 0xF9, 0x32, 0x0F, 0x86, 0x3F, 0xF6, 0x56, 0x13, 0xFF, 0x00,
+	0x4D, 0x97, 0xF4, 0xFF, 0x00, 0xF8, 0x22, 0x57, 0xFC, 0xAB, 0x79, 0xF1, 0x33, 0xFE, 0xC0, 0x1E,
+	0x3B, 0xFF, 0x00, 0xD2, 0x29, 0xA9, 0x9F, 0xF0, 0x78, 0x27, 0xFC, 0x99, 0x07, 0xC3, 0x1F, 0xFB,
+	0x2B, 0x09, 0xFF, 0x00, 0xA6, 0xCB, 0xFA, 0x7F, 0xFC, 0x11, 0x2B, 0xFE, 0x55, 0xBC, 0xF8, 0x99,
+	0xFF, 0x00, 0x60, 0x0F, 0x1D, 0xFF, 0x00, 0xE9, 0x14, 0xD5, 0xA3, 0xFE, 0x21, 0xC6, 0xFF, 0x00,
+	0xDD, 0xFE, 0x67, 0xC7, 0x1F, 0xF0, 0x68, 0x2F, 0xFC, 0xA4, 0x9F, 0xC6, 0xDF, 0xF6, 0x43, 0xF5,
+	0x2F, 0xFD, 0x3C, 0x68, 0xB5, 0xE5, 0x9F, 0xF0, 0x56, 0x4F, 0xF9, 0x58, 0x63, 0xC5, 0x7F, 0xF6,
+	0x55, 0x7C, 0x35, 0xFF, 0x00, 0xA4, 0xFA, 0x7D, 0x7A, 0x9F, 0xFC, 0x1A, 0x0B, 0xFF, 0x00, 0x29,
+	0x27, 0xF1, 0xB7, 0xFD, 0x90, 0xFD, 0x4B, 0xFF, 0x00, 0x4F, 0x1A, 0x2D, 0x79, 0x67, 0xFC, 0x15,
+	0x93, 0xFE, 0x56, 0x18, 0xF1, 0x5F, 0xFD, 0x95, 0x5F, 0x0D, 0x7F, 0xE9, 0x3E, 0x9F, 0x53, 0xFF,
+	0x00, 0x2E, 0xD1, 0x5F, 0xF2, 0xFA, 0x5E, 0x87, 0xDB, 0xFF, 0x00, 0xF0, 0x79, 0x2F, 0xFC, 0x93,
+	0x5F, 0x80, 0xBF, 0xF6, 0x1E, 0xF1, 0x07, 0xFE, 0x93, 0x58, 0xD7, 0x77, 0xFF, 0x00, 0x04, 0xC9,
+	0xFF, 0x00, 0x95, 0x54, 0x7E, 0x23, 0xFF, 0x00, 0xD9, 0x28, 0xF8, 0x95, 0xFF, 0x00, 0xA2, 0xF5,
+	0x4A, 0xE1, 0x3F, 0xE0, 0xF2, 0x5F, 0xF9, 0x26, 0xBF, 0x01, 0x7F, 0xEC, 0x3D, 0xE2, 0x0F, 0xFD,
+	0x26, 0xB1, 0xAE, 0xEF, 0xFE, 0x09, 0x93, 0xFF, 0x00, 0x2A, 0xA8, 0xFC, 0x47, 0xFF, 0x00, 0xB2,
+	0x51, 0xF1, 0x2B, 0xFF, 0x00, 0x45, 0xEA, 0x95, 0x4B, 0xE2, 0x66, 0x6B, 0xF8, 0x2B, 0xD4, 0xF9,
+	0x4B, 0xFE, 0x0C, 0xFC, 0xFF, 0x00, 0x93, 0xE2, 0xF8, 0x9D, 0xFF, 0x00, 0x64, 0xAF, 0xFF, 0x00,
+	0x72, 0x96, 0x75, 0xE2, 0x1F, 0xB6, 0x8F, 0xFC, 0xAC, 0x8D, 0xAA, 0x7F, 0xD9, 0xC6, 0x68, 0x7F,
+	0xFA, 0x5D, 0x67, 0x5E, 0xDF, 0xFF, 0x00, 0x06, 0x7E, 0x7F, 0xC9, 0xF1, 0x7C, 0x4E, 0xFF, 0x00,
+	0xB2, 0x57, 0xFF, 0x00, 0xB9, 0x4B, 0x3A, 0xF1, 0x0F, 0xDB, 0x47, 0xFE, 0x56, 0x46, 0xD5, 0x3F,
+	0xEC, 0xE3, 0x34, 0x3F, 0xFD, 0x2E, 0xB3, 0xAC, 0xDF, 0xF0, 0xE3, 0xEA, 0x69, 0xFF, 0x00, 0x2F,
+	0xA5, 0xE8, 0x7D, 0x8D, 0xFF, 0x00, 0x07, 0x9A, 0xFD, 0xEF, 0xD9, 0xBF, 0xFD, 0xDF, 0x18, 0x7F,
+	0x3D, 0x12, 0xBD, 0x53, 0xE1, 0xEF, 0xFC, 0xAA, 0x2F, 0x71, 0xFF, 0x00, 0x64, 0xA7, 0x54, 0xFF,
+	0x00, 0xD3, 0xC4, 0xF5, 0xE5, 0x7F, 0xF0, 0x79, 0xAF, 0xDE, 0xFD, 0x9B, 0xFF, 0x00, 0xDD, 0xF1,
+	0x87, 0xF3, 0xD1, 0x2B, 0xD5, 0x3E, 0x1E, 0xFF, 0x00, 0xCA, 0xA2, 0xF7, 0x1F, 0xF6, 0x4A, 0x75,
+	0x4F, 0xFD, 0x3C, 0x4F, 0x5B, 0x75, 0x66, 0x6B, 0xF8, 0x71, 0xF5, 0x3E, 0x70, 0xFF, 0x00, 0x83,
+	0x3A, 0xBF, 0xE4, 0xE4, 0xFE, 0x32, 0x7F, 0xD8, 0x8B, 0x63, 0xFF, 0x00, 0xA5, 0xAD, 0x5F, 0x2B,
+	0xCB, 0xFF, 0x00, 0x2B, 0x26, 0xFF, 0x00, 0xDD, 0xF2, 0x2F, 0xFE, 0xA6, 0x22, 0xBE, 0xA8, 0xFF,
+	0x00, 0x83, 0x3A, 0xBF, 0xE4, 0xE4, 0xFE, 0x32, 0x7F, 0xD8, 0x8B, 0x63, 0xFF, 0x00, 0xA5, 0xAD,
+	0x5F, 0x2B, 0xCB, 0xFF, 0x00, 0x2B, 0x26, 0xFF, 0x00, 0xDD, 0xF2, 0x2F, 0xFE, 0xA6, 0x22, 0xB1,
+	0x7F, 0xC3, 0x8F, 0xA9, 0xA7, 0xFC, 0xBC, 0x97, 0xA1, 0xF6, 0x47, 0xFC, 0x1E, 0x47, 0xFF, 0x00,
+	0x25, 0x23, 0xE0, 0x1F, 0xFD, 0x80, 0x35, 0xEF, 0xFD, 0x29, 0xD3, 0xEB, 0xDB, 0xFE, 0x22, 0xFF,
+	0x00, 0xCA, 0xA2, 0x70, 0xFF, 0x00, 0xD9, 0x2A, 0xD3, 0x3F, 0xF4, 0xF1, 0x05, 0x78, 0x87, 0xFC,
+	0x1E, 0x47, 0xFF, 0x00, 0x25, 0x23, 0xE0, 0x1F, 0xFD, 0x80, 0x35, 0xEF, 0xFD, 0x29, 0xD3, 0xEB,
+	0xDB, 0xFE, 0x22, 0xFF, 0x00, 0xCA, 0xA2, 0x70, 0xFF, 0x00, 0xD9, 0x2A, 0xD3, 0x3F, 0xF4, 0xF1,
+	0x05, 0x69, 0xD5, 0x92, 0xFF, 0x00, 0x83, 0x0F, 0x53, 0xCA, 0xFF, 0x00, 0xE0, 0xCD, 0x0F, 0xF5,
+	0x9F, 0xB4, 0x77, 0xD3, 0xC1, 0xFF, 0x00, 0xCF, 0x5E, 0xAF, 0x8E, 0xBF, 0x62, 0xFF, 0x00, 0xF9,
+	0x59, 0x17, 0x4D, 0xFF, 0x00, 0xB3, 0x90, 0xD6, 0xFF, 0x00, 0xF4, 0xB2, 0xF6, 0xBE, 0xC5, 0xFF,
+	0x00, 0x83, 0x34, 0x3F, 0xD6, 0x7E, 0xD1, 0xDF, 0x4F, 0x07, 0xFF, 0x00, 0x3D, 0x7A, 0xBE, 0x3A,
+	0xFD, 0x8B, 0xFF, 0x00, 0xE5, 0x64, 0x5D, 0x37, 0xFE, 0xCE, 0x43, 0x5B, 0xFF, 0x00, 0xD2, 0xCB,
+	0xDA, 0x5F, 0x65, 0x14, 0xBE, 0x29, 0x9E, 0xE3, 0xFF, 0x00, 0x07, 0x84, 0xFF, 0x00, 0xC9, 0xEE,
+	0xFC, 0x31, 0xFF, 0x00, 0xB2, 0x53, 0xFF, 0x00, 0xB9, 0x2B, 0xCA, 0xFA, 0xAB, 0xF6, 0xC9, 0xCF,
+	0xFC, 0x42, 0x33, 0xA2, 0xFF, 0x00, 0xD9, 0x2B, 0xF0, 0x1F, 0xFE, 0x9E, 0x74, 0x8A, 0xF9, 0x57,
+	0xFE, 0x0F, 0x09, 0xFF, 0x00, 0x93, 0xDD, 0xF8, 0x63, 0xFF, 0x00, 0x64, 0xA7, 0xFF, 0x00, 0x72,
+	0x57, 0x95, 0xF5, 0x57, 0xED, 0x93, 0x9F, 0xF8, 0x84, 0x67, 0x45, 0xFF, 0x00, 0xB2, 0x57, 0xE0,
+	0x3F, 0xFD, 0x3C, 0xE9, 0x14, 0xFE, 0xD3, 0x27, 0xFE, 0x5C, 0xC3, 0xD4, 0xE1, 0x3F, 0xE0, 0xCD,
+	0x8F, 0xF9, 0x26, 0x9F, 0x1E, 0xBF, 0xEC, 0x35, 0xE1, 0xFF, 0x00, 0xFD, 0x11, 0x7B, 0x5F, 0x0F,
+	0xFF, 0x00, 0xC1, 0x26, 0x3F, 0xE5, 0x61, 0x8F, 0x09, 0xFF, 0x00, 0xD9, 0x56, 0xF1, 0x1F, 0xFE,
+	0x93, 0xEA, 0x95, 0xF7, 0x07, 0xFC, 0x19, 0xB1, 0xFF, 0x00, 0x24, 0xD3, 0xE3, 0xD7, 0xFD, 0x86,
+	0xBC, 0x3F, 0xFF, 0x00, 0xA2, 0x2F, 0x6B, 0xE1, 0xFF, 0x00, 0xF8, 0x24, 0xC7, 0xFC, 0xAC, 0x31,
+	0xE1, 0x3F, 0xFB, 0x2A, 0xDE, 0x23, 0xFF, 0x00, 0xD2, 0x7D, 0x52, 0x97, 0xD9, 0x45, 0x47, 0xE2,
+	0x9F, 0xA1, 0xEA, 0x9F, 0xF0, 0x77, 0xCF, 0xFC, 0xA4, 0xA7, 0xC0, 0xFF, 0x00, 0xF6, 0x44, 0x74,
+	0xBF, 0xFD, 0x3C, 0xEA, 0xF5, 0xF6, 0x2F, 0xFC, 0x16, 0xC7, 0xFE, 0x55, 0xBF, 0xF8, 0x65, 0xFF,
+	0x00, 0x60, 0x6F, 0x01, 0xFF, 0x00, 0xE9, 0x14, 0x35, 0xF1, 0xD7, 0xFC, 0x1D, 0xF3, 0xFF, 0x00,
+	0x29, 0x29, 0xF0, 0x3F, 0xFD, 0x91, 0x1D, 0x2F, 0xFF, 0x00, 0x4F, 0x3A, 0xBD, 0x7D, 0x8B, 0xFF,
+	0x00, 0x05, 0xB1, 0xFF, 0x00, 0x95, 0x6F, 0xFE, 0x19, 0x7F, 0xD8, 0x1B, 0xC0, 0x7F, 0xFA, 0x45,
+	0x0D, 0x27, 0xD4, 0x8F, 0xB3, 0x03, 0x07, 0xFE, 0x0C, 0xE9, 0xFF, 0x00, 0x93, 0x6B, 0xF8, 0xC7,
+	0xFF, 0x00, 0x63, 0xC6, 0x9D, 0xFF, 0x00, 0xA4, 0x75, 0xF9, 0x75, 0xFF, 0x00, 0x04, 0x2A, 0xF8,
+	0x1F, 0xF0, 0xAB, 0xF6, 0x90, 0xFF, 0x00, 0x82, 0xA8, 0x7C, 0x2D, 0xF8, 0x35, 0xF1, 0xBF, 0xC0,
+	0x56, 0x3E, 0x25, 0xF0, 0xAE, 0xB4, 0x75, 0xA1, 0xAB, 0x68, 0xBA, 0xA4, 0x7E, 0x64, 0x37, 0x02,
+	0x1D, 0x0A, 0xFE, 0x78, 0x8B, 0x8F, 0x41, 0x2C, 0x20, 0x8F, 0xF7, 0x2B, 0xF5, 0x17, 0xFE, 0x0C,
+	0xE9, 0xFF, 0x00, 0x93, 0x6B, 0xF8, 0xC7, 0xFF, 0x00, 0x63, 0xC6, 0x9D, 0xFF, 0x00, 0xA4, 0x75,
+	0xF9, 0xCD, 0xFF, 0x00, 0x06, 0xDC, 0xFF, 0x00, 0xCA, 0x68, 0xBE, 0x0B, 0xFF, 0x00, 0xBD, 0xE2,
+	0x1F, 0xFD, 0x47, 0x35, 0x3A, 0x71, 0xFE, 0x1A, 0x29, 0x36, 0xA5, 0x3B, 0x1B, 0x9F, 0xF0, 0x71,
+	0xE7, 0xEC, 0xCF, 0xF0, 0x1F, 0xF6, 0x4C, 0xFF, 0x00, 0x82, 0x84, 0x58, 0x7C, 0x2F, 0xFD, 0x9D,
+	0xFE, 0x19, 0xE9, 0x3E, 0x0D, 0xF0, 0xFB, 0xFC, 0x3D, 0xD2, 0xF5, 0x09, 0x34, 0xDD, 0x2E, 0xDF,
+	0x10, 0xFD, 0xA1, 0xAE, 0xAE, 0x95, 0xAE, 0x18, 0x7F, 0xC0, 0x63, 0x1F, 0xF6, 0xCE, 0xBE, 0xE6,
+	0xFF, 0x00, 0x82, 0xA1, 0x7E, 0xCE, 0xFF, 0x00, 0x04, 0xBF, 0xE0, 0x9A, 0xFF, 0x00, 0xF0, 0x4C,
+	0xFF, 0x00, 0x85, 0xDF, 0xB6, 0xCF, 0xEC, 0x2B, 0xF0, 0xBF, 0x4B, 0xF8, 0x67, 0xF1, 0x51, 0xB5,
+	0x6F, 0x0F, 0xDB, 0xC9, 0xE3, 0x2F, 0x0F, 0xDB, 0x95, 0xBC, 0x30, 0xDE, 0x69, 0x53, 0xFD, 0xA9,
+	0x49, 0x72, 0xC3, 0xF7, 0x83, 0xE5, 0xE9, 0x8E, 0x6B, 0xE5, 0x3F, 0xF8, 0x3B, 0x33, 0xFE, 0x52,
+	0x85, 0xA7, 0xFF, 0x00, 0xD9, 0x2B, 0xD2, 0x3F, 0xF4, 0xAA, 0xFA, 0xBE, 0xE3, 0xFF, 0x00, 0x83,
+	0x8B, 0x3F, 0xE5, 0x04, 0xBF, 0x0A, 0xFF, 0x00, 0xEC, 0x60, 0xF0, 0x87, 0xFE, 0x9A, 0xE7, 0xA4,
+	0x26, 0xDB, 0x8C, 0x0E, 0x2F, 0xFE, 0x08, 0xAF, 0xF0, 0x03, 0xE0, 0xE7, 0xFC, 0x15, 0x4F, 0xF6,
+	0x24, 0xF8, 0x95, 0xFB, 0x5E, 0x7F, 0xC1, 0x41, 0x7E, 0x19, 0xE9, 0x3F, 0x14, 0x7E, 0x25, 0x5A,
+	0xF8, 0xFB, 0x50, 0xD2, 0x2D, 0x7C, 0x63, 0xE2, 0x4B, 0x54, 0x17, 0x86, 0xD2, 0xDB, 0x44, 0xD2,
+	0xDE, 0xDE, 0x32, 0x63, 0xDA, 0xA4, 0x46, 0xCE, 0xE1, 0x49, 0x52, 0x7E, 0x6E, 0x6B, 0xF3, 0xF7,
+	0xFE, 0x0D, 0xE0, 0xFD, 0x9D, 0xBE, 0x08, 0xFE, 0xD4, 0x7F, 0xF0, 0x51, 0xFD, 0x37, 0xE1, 0x4F,
+	0xED, 0x01, 0xF0, 0xDB, 0x4D, 0xF1, 0x5F, 0x87, 0x66, 0xF0, 0x8E, 0xA7, 0x74, 0xDA, 0x3E, 0xAD,
+	0x1B, 0xBD, 0xBB, 0xDC, 0x44, 0x80, 0xA1, 0x23, 0x03, 0xE6, 0x0A, 0x79, 0xE0, 0x73, 0xDA, 0xBF,
+	0x4D, 0x7F, 0xE0, 0xD5, 0x4F, 0xF9, 0x44, 0x77, 0xC5, 0x8F, 0xFB, 0x2A, 0xDA, 0xE7, 0xFE, 0x98,
+	0x74, 0x8A, 0xF8, 0x03, 0xFE, 0x0D, 0x5F, 0xFF, 0x00, 0x94, 0xB2, 0x69, 0x3F, 0xF6, 0x22, 0xEB,
+	0x5F, 0xFA, 0x2D, 0x68, 0x97, 0x46, 0x55, 0xE5, 0x1E, 0x7F, 0x23, 0xCC, 0x3F, 0xE0, 0xBF, 0x1F,
+	0x00, 0x3E, 0x0F, 0x7E, 0xCC, 0xDF, 0xF0, 0x53, 0x8F, 0x19, 0x7C, 0x21, 0xF8, 0x0D, 0xE0, 0x0D,
+	0x33, 0xC2, 0xFE, 0x19, 0xB0, 0xD3, 0x74, 0x79, 0xAC, 0xF4, 0x6D, 0x36, 0x22, 0xB0, 0x42, 0xD2,
+	0xE9, 0xF6, 0xCD, 0x23, 0xE3, 0xB3, 0x33, 0x57, 0xE9, 0x87, 0xFC, 0x1D, 0x6E, 0x4B, 0x7F, 0xC1,
+	0x35, 0xFE, 0x08, 0xB1, 0x0C, 0x3F, 0xE2, 0xBC, 0xB1, 0xFB, 0xDD, 0x7F, 0xE4, 0x0D, 0x79, 0xD6,
+	0xBE, 0x02, 0xFF, 0x00, 0x83, 0x9C, 0x7F, 0xE5, 0x30, 0xFE, 0x3F, 0xFF, 0x00, 0xB0, 0x2E, 0x85,
+	0xFF, 0x00, 0xA6, 0xCB, 0x5A, 0xFB, 0xFF, 0x00, 0xFE, 0x0E, 0xB9, 0xFF, 0x00, 0x94, 0x6C, 0xFC,
+	0x11, 0xFF, 0x00, 0xB1, 0xF2, 0xCB, 0xFF, 0x00, 0x4C, 0xD7, 0x94, 0x7D, 0x99, 0x02, 0xD6, 0x50,
+	0x37, 0xBF, 0xE0, 0xDD, 0x0F, 0xF9, 0x41, 0x1F, 0xC5, 0x2F, 0xFB, 0x0E, 0x78, 0xAF, 0xFF, 0x00,
+	0x4D, 0x56, 0xD5, 0xF0, 0xC7, 0xFC, 0x1A, 0x61, 0xFF, 0x00, 0x29, 0x43, 0xBE, 0xFF, 0x00, 0xB2,
+	0x4F, 0xAB, 0x7F, 0xE9, 0x66, 0x9F, 0x5F, 0x73, 0xFF, 0x00, 0xC1, 0xBA, 0x1F, 0xF2, 0x82, 0x3F,
+	0x8A, 0x5F, 0xF6, 0x1C, 0xF1, 0x5F, 0xFE, 0x9A, 0xAD, 0xAB, 0xE1, 0x8F, 0xF8, 0x34, 0xC3, 0xFE,
+	0x52, 0x87, 0x7D, 0xFF, 0x00, 0x64, 0x9F, 0x56, 0xFF, 0x00, 0xD2, 0xCD, 0x3E, 0xAB, 0xAC, 0x43,
+	0xEC, 0xD4, 0x38, 0x8F, 0xF8, 0x2F, 0x8F, 0xFC, 0xA7, 0xAF, 0xE2, 0x37, 0xFD, 0x87, 0x3C, 0x25,
+	0xFF, 0x00, 0xA6, 0x2D, 0x22, 0xBF, 0x40, 0xBF, 0xE0, 0xF1, 0x7F, 0xF9, 0x36, 0xCF, 0x83, 0x7F,
+	0xF6, 0x3D, 0x5E, 0xFF, 0x00, 0xE9, 0x1A, 0xD7, 0xE7, 0xEF, 0xFC, 0x17, 0xC7, 0xFE, 0x53, 0xD7,
+	0xF1, 0x1B, 0xFE, 0xC3, 0x9E, 0x12, 0xFF, 0x00, 0xD3, 0x16, 0x91, 0x5F, 0xA0, 0x5F, 0xF0, 0x78,
+	0xBF, 0xFC, 0x9B, 0x67, 0xC1, 0xBF, 0xFB, 0x1E, 0xAF, 0x7F, 0xF4, 0x8D, 0x69, 0xF5, 0x61, 0xF6,
+	0xA9, 0x9B, 0x5F, 0xF0, 0x4C, 0x7F, 0xF9, 0x55, 0x3B, 0xE2, 0x37, 0xFD, 0x92, 0x7F, 0x89, 0x5F,
+	0xFA, 0x2F, 0x54, 0xAF, 0x8E, 0xBF, 0xE0, 0xD0, 0x8F, 0xF9, 0x49, 0x47, 0x8E, 0x3F, 0xEC, 0x87,
+	0xEA, 0x5F, 0xFA, 0x79, 0xD1, 0x6B, 0xEC, 0x5F, 0xF8, 0x26, 0x3F, 0xFC, 0xAA, 0x9D, 0xF1, 0x1B,
+	0xFE, 0xC9, 0x3F, 0xC4, 0xAF, 0xFD, 0x17, 0xAA, 0x57, 0xC7, 0x5F, 0xF0, 0x68, 0x47, 0xFC, 0xA4,
+	0xA3, 0xC7, 0x1F, 0xF6, 0x43, 0xF5, 0x2F, 0xFD, 0x3C, 0xE8, 0xB5, 0x3D, 0x62, 0x66, 0xFF, 0x00,
+	0x87, 0x3F, 0x53, 0xCA, 0xBF, 0xE0, 0xAC, 0x7F, 0xF2, 0xB0, 0xBF, 0x8A, 0xBF, 0xEC, 0xAA, 0x78,
+	0x6B, 0xFF, 0x00, 0x49, 0xF4, 0xFA, 0xFB, 0x83, 0xFE, 0x0F, 0x26, 0xFF, 0x00, 0x92, 0x6F, 0xF0,
+	0x17, 0xFE, 0xC3, 0xBE, 0x20, 0xFF, 0x00, 0xD2, 0x6B, 0x1A, 0xF8, 0x7F, 0xFE, 0x0A, 0xC7, 0xFF,
+	0x00, 0x2B, 0x0B, 0xF8, 0xAB, 0xFE, 0xCA, 0xA7, 0x86, 0xBF, 0xF4, 0x9F, 0x4F, 0xAF, 0xB8, 0x3F,
+	0xE0, 0xF2, 0x6F, 0xF9, 0x26, 0xFF, 0x00, 0x01, 0x7F, 0xEC, 0x3B, 0xE2, 0x0F, 0xFD, 0x26, 0xB1,
+	0xA5, 0xF6, 0xA4, 0x57, 0xFC, 0xBD, 0x81, 0xDD, 0x7E, 0xC7, 0x1F, 0xF2, 0xA8, 0xA6, 0xB5, 0xFF,
+	0x00, 0x64, 0x9F, 0xC7, 0x9F, 0xFA, 0x78, 0xD5, 0xEB, 0xE7, 0x1F, 0xF8, 0x33, 0xB7, 0xFE, 0x4E,
+	0x5B, 0xE3, 0x2F, 0xFD, 0x88, 0xB6, 0x3F, 0xFA, 0x5A, 0xD5, 0xF4, 0x77, 0xEC, 0x71, 0xFF, 0x00,
+	0x2A, 0x8A, 0x6B, 0x5F, 0xF6, 0x49, 0xFC, 0x79, 0xFF, 0x00, 0xA7, 0x8D, 0x5E, 0xBE, 0x71, 0xFF,
+	0x00, 0x83, 0x3B, 0x7F, 0xE4, 0xE5, 0xBE, 0x32, 0xFF, 0x00, 0xD8, 0x8B, 0x63, 0xFF, 0x00, 0xA5,
+	0xAD, 0x55, 0xF6, 0xA2, 0x1F, 0xF2, 0xEE, 0xA7, 0xA9, 0xF2, 0xB7, 0xED, 0x25, 0xFF, 0x00, 0x2B,
+	0x16, 0x6B, 0x1F, 0xF6, 0x75, 0xB6, 0xFF, 0x00, 0xFA, 0x7A, 0xB7, 0xAF, 0xB1, 0xFF, 0x00, 0xE0,
+	0xF2, 0x4F, 0xF9, 0x29, 0x5F, 0x01, 0x3F, 0xEC, 0x03, 0xAF, 0xFF, 0x00, 0xE9, 0x4E, 0x9F, 0x5F,
+	0x1C, 0x7E, 0xD2, 0x5F, 0xF2, 0xB1, 0x66, 0xB1, 0xFF, 0x00, 0x67, 0x5B, 0x6F, 0xFF, 0x00, 0xA7,
+	0xAB, 0x7A, 0xFB, 0x1F, 0xFE, 0x0F, 0x24, 0xFF, 0x00, 0x92, 0x95, 0xF0, 0x13, 0xFE, 0xC0, 0x3A,
+	0xFF, 0x00, 0xFE, 0x94, 0xE9, 0xF5, 0x31, 0xFB, 0x45, 0x47, 0xF8, 0xB0, 0xF4, 0x3D, 0xBF, 0xE1,
+	0xEF, 0xFC, 0xAA, 0x2F, 0x71, 0xFF, 0x00, 0x64, 0xA7, 0x54, 0xFF, 0x00, 0xD3, 0xC4, 0xF5, 0xE1,
+	0xFF, 0x00, 0xF0, 0x66, 0xC7, 0xFC, 0x94, 0xAF, 0x8F, 0x5F, 0xF6, 0x04, 0xF0, 0xF7, 0xFE, 0x8E,
+	0xD4, 0x2B, 0xDC, 0x3E, 0x1E, 0xFF, 0x00, 0xCA, 0xA2, 0xF7, 0x1F, 0xF6, 0x4A, 0x75, 0x4F, 0xFD,
+	0x3C, 0x4F, 0x5E, 0x1F, 0xFF, 0x00, 0x06, 0x6C, 0x7F, 0xC9, 0x4A, 0xF8, 0xF5, 0xFF, 0x00, 0x60,
+	0x4F, 0x0F, 0x7F, 0xE8, 0xED, 0x42, 0xB5, 0x5F, 0x12, 0x26, 0x3F, 0xC3, 0x91, 0xF2, 0xAF, 0xC3,
+	0xEF, 0xF9, 0x59, 0xB2, 0x7F, 0xFB, 0x3C, 0x7D, 0x53, 0xFF, 0x00, 0x52, 0x19, 0xEB, 0xE8, 0xDF,
+	0xF8, 0x3C, 0x63, 0xFE, 0x4E, 0x43, 0xE0, 0xDF, 0xFD, 0x88, 0x7A, 0x87, 0xFE, 0x96, 0xAD, 0x7C,
+	0xE5, 0xF0, 0xFB, 0xFE, 0x56, 0x6C, 0x9F, 0xFE, 0xCF, 0x1F, 0x54, 0xFF, 0x00, 0xD4, 0x86, 0x7A,
+	0xFA, 0x37, 0xFE, 0x0F, 0x18, 0xFF, 0x00, 0x93, 0x90, 0xF8, 0x37, 0xFF, 0x00, 0x62, 0x1E, 0xA1,
+	0xFF, 0x00, 0xA5, 0xAB, 0x51, 0xD1, 0x9A, 0x43, 0xF8, 0x90, 0xF4, 0x3E, 0x90, 0xFD, 0xB2, 0x73,
+	0xFF, 0x00, 0x10, 0x8D, 0x68, 0xFF, 0x00, 0xF6, 0x4A, 0xFC, 0x07, 0xFF, 0x00, 0xA7, 0xAD, 0x22,
+	0xBC, 0x9F, 0xFE, 0x0C, 0xC9, 0xFB, 0xBF, 0xB4, 0x6F, 0xFB, 0x9E, 0x0F, 0xFF, 0x00, 0xDC, 0xF5,
+	0x7A, 0xC7, 0xED, 0x93, 0x9F, 0xF8, 0x84, 0x6B, 0x47, 0xFF, 0x00, 0xB2, 0x57, 0xE0, 0x3F, 0xFD,
+	0x3D, 0x69, 0x15, 0xE4, 0xFF, 0x00, 0xF0, 0x66, 0x4F, 0xDD, 0xFD, 0xA3, 0x7F, 0xDC, 0xF0, 0x7F,
+	0xFE, 0xE7, 0xA8, 0xFB, 0x48, 0xC7, 0xFE, 0x5D, 0xCB, 0xD4, 0xF8, 0xEF, 0xF6, 0x2E, 0xFF, 0x00,
+	0x95, 0x91, 0xF4, 0xDF, 0xFB, 0x39, 0x0D, 0x6F, 0xFF, 0x00, 0x4B, 0x2F, 0x2B, 0xDC, 0xBF, 0xE0,
+	0xF0, 0x9F, 0xF9, 0x3D, 0xDF, 0x86, 0x3F, 0xF6, 0x4A, 0x7F, 0xF7, 0x25, 0x79, 0x5E, 0x1B, 0xFB,
+	0x17, 0x7F, 0xCA, 0xC8, 0xFA, 0x6F, 0xFD, 0x9C, 0x86, 0xB7, 0xFF, 0x00, 0xA5, 0x97, 0x95, 0xEE,
+	0x5F, 0xF0, 0x78, 0x4F, 0xFC, 0x9E, 0xEF, 0xC3, 0x1F, 0xFB, 0x25, 0x3F, 0xFB, 0x92, 0xBC, 0xA3,
+	0xEC, 0x9B, 0x7F, 0xCB, 0xF8, 0xFA, 0x1F, 0x53, 0xFF, 0x00, 0xC1, 0x4E, 0x7F, 0xE5, 0x55, 0x4F,
+	0x87, 0x1F, 0xF6, 0x4A, 0xFE, 0x19, 0xFF, 0x00, 0xE8, 0xBD, 0x2E, 0xB0, 0xBF, 0xE0, 0xCE, 0x9F,
+	0xF9, 0x36, 0x9F, 0x8C, 0x7F, 0xF6, 0x3C, 0xD8, 0x7F, 0xE9, 0x15, 0x6E, 0xFF, 0x00, 0xC1, 0x4E,
+	0x7F, 0xE5, 0x55, 0x4F, 0x87, 0x1F, 0xF6, 0x4A, 0xFE, 0x19, 0xFF, 0x00, 0xE8, 0xBD, 0x2E, 0xB0,
+	0xBF, 0xE0, 0xCE, 0x9F, 0xF9, 0x36, 0x9F, 0x8C, 0x7F, 0xF6, 0x3C, 0xD8, 0x7F, 0xE9, 0x15, 0x1F,
+	0x69, 0x19, 0x3F, 0xE0, 0xFC, 0xCF, 0xCE, 0x7F, 0xF8, 0x22, 0x57, 0xFC, 0xA7, 0x3F, 0xE1, 0x8F,
+	0xFD, 0x8F, 0x5A, 0xC7, 0xFE, 0x90, 0xEA, 0x35, 0xEA, 0xDF, 0xF0, 0x76, 0x57, 0xFC, 0xA5, 0x1A,
+	0xC7, 0xFE, 0xC9, 0x3E, 0x91, 0xFF, 0x00, 0xA5, 0x77, 0xD5, 0xE5, 0x3F, 0xF0, 0x44, 0xAF, 0xF9,
+	0x4E, 0x7F, 0xC3, 0x1F, 0xFB, 0x1E, 0xB5, 0x8F, 0xFD, 0x21, 0xD4, 0x6B, 0xD5, 0xBF, 0xE0, 0xEC,
+	0xAF, 0xF9, 0x4A, 0x35, 0x8F, 0xFD, 0x92, 0x7D, 0x23, 0xFF, 0x00, 0x4A, 0xEF, 0xAA, 0x5F, 0xC2,
+	0x6D, 0xFF, 0x00, 0x2F, 0xA3, 0xE8, 0x7E, 0x62, 0x9E, 0xB4, 0x50, 0x7A, 0xD1, 0x59, 0x9B, 0x85,
+	0x14, 0x51, 0x40, 0x05, 0x14, 0x52, 0x85, 0x63, 0xB7, 0xE4, 0x6C, 0x33, 0x6D, 0x45, 0x8F, 0xBB,
+	0x50, 0x1A, 0x9F, 0xA4, 0xFF, 0x00, 0xF0, 0x6F, 0x1F, 0xC4, 0x2F, 0x1D, 0x7E, 0xCE, 0x3E, 0x28,
+	0xF8, 0x85, 0xFB, 0x42, 0xF8, 0x27, 0x47, 0xD3, 0x25, 0xBC, 0xBF, 0xD3, 0x6D, 0xFC, 0x3B, 0x6F,
+	0x75, 0xAA, 0x5A, 0x48, 0xE5, 0x63, 0x32, 0xA4, 0xF3, 0x85, 0xC3, 0xF4, 0xCA, 0xDA, 0x57, 0xEA,
+	0x47, 0xFC, 0x3D, 0x53, 0xF6, 0x9D, 0x27, 0x70, 0xB3, 0xF0, 0xB7, 0xFE, 0x0A, 0xE5, 0xFF, 0x00,
+	0xE2, 0xEB, 0xF3, 0xF7, 0xFE, 0x09, 0xEB, 0xF0, 0xB4, 0xFC, 0x2E, 0xFD, 0x92, 0x7C, 0x2F, 0x61,
+	0x71, 0x6C, 0x63, 0xBC, 0xD6, 0x2D, 0xA4, 0xD5, 0xEF, 0x77, 0x75, 0x12, 0x5D, 0x61, 0xA3, 0xFF,
+	0x00, 0xC8, 0x26, 0x2A, 0xF6, 0xE2, 0xCA, 0xC7, 0x72, 0xF4, 0x3C, 0x8A, 0xEA, 0x8A, 0xB4, 0x4F,
+	0x36, 0xB4, 0xB9, 0xAA, 0xE8, 0x7D, 0x29, 0xFF, 0x00, 0x0F, 0x54, 0xFD, 0xA7, 0xBF, 0xE7, 0xCF,
+	0xC2, 0xBF, 0xF8, 0x2B, 0x97, 0xFF, 0x00, 0x8B, 0xAF, 0xB1, 0xFF, 0x00, 0x63, 0xDF, 0x8B, 0xFE,
+	0x2A, 0xF8, 0xE3, 0xF0, 0x27, 0x4D, 0xF8, 0x95, 0xE3, 0x95, 0xB5, 0x5D, 0x42, 0xF2, 0xEA, 0xE1,
+	0x26, 0xFB, 0x0C, 0x05, 0x10, 0x2C, 0x73, 0x32, 0xAF, 0x53, 0xD3, 0x8A, 0xFC, 0xA4, 0xAF, 0xD3,
+	0x4F, 0xF8, 0x26, 0xAF, 0xFC, 0x9A, 0x3E, 0x87, 0xFF, 0x00, 0x5F, 0xD7, 0xFF, 0x00, 0xFA, 0x52,
+	0xD5, 0x46, 0x27, 0x8C, 0xFE, 0xDC, 0x7F, 0xB6, 0xFF, 0x00, 0xED, 0x09, 0xF0, 0x33, 0xF6, 0x82,
+	0xBE, 0xF8, 0x7B, 0xF0, 0xEF, 0x5B, 0xD3, 0xED, 0x74, 0xEB, 0x7B, 0x1B, 0x59, 0x23, 0x5B, 0x8D,
+	0x31, 0x26, 0x26, 0x49, 0x10, 0x33, 0x75, 0xEB, 0xD6, 0xBC, 0x80, 0xFF, 0x00, 0xC1, 0x51, 0x3F,
+	0x6B, 0x92, 0xC4, 0x8F, 0x15, 0xE9, 0x7F, 0xF8, 0x21, 0x83, 0xFA, 0xD2, 0x7F, 0xC1, 0x51, 0xBF,
+	0xE4, 0xEE, 0xF5, 0x4F, 0xFB, 0x04, 0xE9, 0xFF, 0x00, 0xFA, 0x28, 0x57, 0xCF, 0x34, 0x1D, 0xD4,
+	0xE9, 0xC7, 0x91, 0x1F, 0x43, 0x7F, 0xC3, 0xD1, 0x3F, 0x6B, 0xAF, 0xFA, 0x1A, 0xB4, 0xBF, 0xFC,
+	0x10, 0xDB, 0xD1, 0xFF, 0x00, 0x0F, 0x44, 0xFD, 0xAE, 0xBF, 0xE8, 0x6A, 0xD2, 0xFF, 0x00, 0xF0,
+	0x43, 0x6F, 0x5F, 0x3C, 0xD1, 0x41, 0xA7, 0xB3, 0xA7, 0xD8, 0xFA, 0x23, 0xFE, 0x1E, 0x8F, 0xFB,
+	0x5C, 0x8E, 0x3F, 0xE1, 0x29, 0xD2, 0xFF, 0x00, 0xF0, 0x43, 0x1F, 0xF4, 0xAF, 0xD1, 0x8F, 0x81,
+	0xFE, 0x29, 0xD5, 0xFC, 0x73, 0xF0, 0x5B, 0xC2, 0x1E, 0x36, 0xF1, 0x04, 0xAB, 0x25, 0xFE, 0xB1,
+	0xE1, 0x7D, 0x3E, 0xFA, 0xFA, 0x48, 0xE3, 0xDA, 0xAD, 0x34, 0xB6, 0xD1, 0xC8, 0xE4, 0x2F, 0x61,
+	0xB9, 0x8F, 0x1D, 0xAB, 0xF1, 0x7E, 0xBF, 0x63, 0xFF, 0x00, 0x66, 0x1F, 0xF9, 0x36, 0xAF, 0x87,
+	0x9F, 0xF6, 0x23, 0x69, 0x3F, 0xFA, 0x47, 0x15, 0x07, 0x3E, 0x22, 0x11, 0x8D, 0xAC, 0x8F, 0x93,
+	0xBF, 0x68, 0xEF, 0xF8, 0x28, 0x8F, 0xC7, 0xBF, 0x85, 0xBF, 0x1C, 0x7C, 0x4D, 0xF0, 0xE7, 0xC2,
+	0xD6, 0x5E, 0x1D, 0x6B, 0x2D, 0x33, 0x52, 0xFB, 0x35, 0x99, 0xBA, 0xD3, 0x64, 0x66, 0x20, 0xAE,
+	0x7E, 0x62, 0x25, 0x19, 0x3E, 0xBC, 0x0E, 0x6B, 0x8D, 0x3F, 0xF0, 0x55, 0x5F, 0xDA, 0x74, 0xF2,
+	0xB6, 0x7E, 0x15, 0xC7, 0x6F, 0xF8, 0x95, 0xCB, 0xFF, 0x00, 0xC7, 0x2B, 0xCF, 0x7F, 0x6D, 0x3F,
+	0xF9, 0x3A, 0xEF, 0x1B, 0x7F, 0xD8, 0x70, 0xFF, 0x00, 0xE8, 0x2B, 0x5E, 0x58, 0x9F, 0x70, 0x7D,
+	0x28, 0x39, 0x4F, 0xA5, 0x7F, 0xE1, 0xEA, 0x9F, 0xB4, 0xF7, 0xFC, 0xF9, 0xF8, 0x57, 0xFF, 0x00,
+	0x05, 0x72, 0xFF, 0x00, 0xF1, 0x74, 0x7F, 0xC3, 0xD5, 0x3F, 0x69, 0xEF, 0xF9, 0xF3, 0xF0, 0xAF,
+	0xFE, 0x0A, 0xE5, 0xFF, 0x00, 0xE2, 0xEB, 0xE6, 0xBA, 0x28, 0x03, 0xE9, 0x4F, 0xF8, 0x7A, 0xA7,
+	0xED, 0x3D, 0xFF, 0x00, 0x3E, 0x7E, 0x15, 0xFF, 0x00, 0xC1, 0x5C, 0xBF, 0xFC, 0x5D, 0x7D, 0x35,
+	0xFB, 0x03, 0xFE, 0xD1, 0x7E, 0x3E, 0xFD, 0xA3, 0x3C, 0x2B, 0xE2, 0x5F, 0x15, 0x7C, 0x42, 0x8F,
+	0x4F, 0x8E, 0xEA, 0xC2, 0xF6, 0x0B, 0x58, 0xDB, 0x4F, 0x87, 0xCB, 0x5D, 0xBB, 0x59, 0xF2, 0x41,
+	0x3F, 0xED, 0x77, 0x35, 0xF9, 0xA3, 0x5F, 0x7A, 0x7F, 0xC1, 0x21, 0xD7, 0x77, 0xC3, 0x3F, 0x18,
+	0xA9, 0xEF, 0xAE, 0x41, 0xDF, 0xFE, 0x98, 0xD0, 0x04, 0x5F, 0xB6, 0xBF, 0xED, 0xAD, 0xF1, 0x97,
+	0xF6, 0x72, 0xF8, 0xD4, 0x9E, 0x03, 0xF0, 0x0D, 0xA6, 0x8A, 0xD6, 0x73, 0x68, 0xD0, 0xDE, 0xC8,
+	0x75, 0x0B, 0x32, 0xED, 0xE6, 0x3B, 0xC8, 0xA7, 0x18, 0x7C, 0xFF, 0x00, 0x05, 0x79, 0x27, 0xFC,
+	0x3D, 0x53, 0xF6, 0x9E, 0xFF, 0x00, 0x9F, 0x3F, 0x0A, 0xFF, 0x00, 0xE0, 0xAE, 0x5F, 0xFE, 0x2E,
+	0x93, 0xFE, 0x0A, 0xA3, 0xFF, 0x00, 0x27, 0x33, 0x6F, 0xFF, 0x00, 0x62, 0xC5, 0xAF, 0xFE, 0x87,
+	0x2D, 0x7C, 0xD9, 0x40, 0x1F, 0x4A, 0x7F, 0xC3, 0xD5, 0x3F, 0x69, 0xEF, 0xF9, 0xF3, 0xF0, 0xAF,
+	0xFE, 0x0A, 0xE5, 0xFF, 0x00, 0xE2, 0xE8, 0xFF, 0x00, 0x87, 0xAA, 0x7E, 0xD3, 0xDF, 0xF3, 0xE7,
+	0xE1, 0x5F, 0xFC, 0x15, 0xCB, 0xFF, 0x00, 0xC5, 0xD7, 0xCD, 0x74, 0x50, 0x07, 0xD2, 0x8B, 0xFF,
+	0x00, 0x05, 0x52, 0xFD, 0xA7, 0x99, 0xD4, 0x7D, 0x87, 0xC2, 0xE7, 0xE6, 0x1C, 0x0D, 0x2E, 0x5F,
+	0x5F, 0xF7, 0xEB, 0xE9, 0x4F, 0xD8, 0x0F, 0xF6, 0xA0, 0xF8, 0x89, 0xFB, 0x49, 0xE8, 0x3E, 0x28,
+	0xD4, 0x3E, 0x21, 0xC5, 0xA6, 0x43, 0x36, 0x93, 0x35, 0xAA, 0x5B, 0xFF, 0x00, 0x66, 0xC2, 0x63,
+	0x50, 0x25, 0x12, 0xB1, 0x27, 0x73, 0x1F, 0xEE, 0x8F, 0x4A, 0xFC, 0xD7, 0xED, 0xF8, 0x57, 0xDC,
+	0xDF, 0xF0, 0x48, 0x25, 0xDD, 0xE1, 0xAF, 0x1F, 0x29, 0xEF, 0xA8, 0x58, 0x77, 0xFF, 0x00, 0xA6,
+	0x73, 0x50, 0x05, 0x9F, 0xDB, 0x5F, 0xF6, 0xD6, 0xF8, 0xCB, 0xFB, 0x39, 0x7C, 0x6A, 0x4F, 0x01,
+	0xF8, 0x06, 0xD3, 0x45, 0x6B, 0x39, 0xB4, 0x68, 0x6F, 0x64, 0x3A, 0x85, 0x99, 0x76, 0xF3, 0x1D,
+	0xE4, 0x53, 0x8C, 0x3E, 0x7F, 0x82, 0xBC, 0x93, 0xFE, 0x1E, 0xA9, 0xFB, 0x4F, 0x7F, 0xCF, 0x9F,
+	0x85, 0x7F, 0xF0, 0x57, 0x2F, 0xFF, 0x00, 0x17, 0x49, 0xFF, 0x00, 0x05, 0x51, 0xFF, 0x00, 0x93,
+	0x99, 0xB7, 0xFF, 0x00, 0xB1, 0x62, 0xD7, 0xFF, 0x00, 0x43, 0x96, 0xBE, 0x6C, 0xA0, 0x0F, 0xA5,
+	0x3F, 0xE1, 0xEA, 0x9F, 0xB4, 0xF7, 0xFC, 0xF9, 0xF8, 0x57, 0xFF, 0x00, 0x05, 0x72, 0xFF, 0x00,
+	0xF1, 0x74, 0x7F, 0xC3, 0xD5, 0x3F, 0x69, 0xEF, 0xF9, 0xF3, 0xF0, 0xAF, 0xFE, 0x0A, 0xE5, 0xFF,
+	0x00, 0xE2, 0xEB, 0xE6, 0xBA, 0x28, 0x03, 0xE9, 0x45, 0xFF, 0x00, 0x82, 0xA9, 0x7E, 0xD3, 0xCC,
+	0xEA, 0x3E, 0xC3, 0xE1, 0x73, 0xF3, 0x0E, 0x06, 0x97, 0x2F, 0xAF, 0xFB, 0xF5, 0xF4, 0x87, 0xEC,
+	0x0F, 0xFB, 0x4F, 0x7C, 0x47, 0xFD, 0xA5, 0xB4, 0x8F, 0x11, 0xDE, 0xFC, 0x43, 0x83, 0x4B, 0x8D,
+	0xF4, 0x9B, 0x8B, 0x64, 0x85, 0x74, 0xDB, 0x66, 0x40, 0x7C, 0xD5, 0x99, 0xB9, 0xCB, 0x1F, 0xEE,
+	0xFA, 0x57, 0xE6, 0xDF, 0x6F, 0xC2, 0xBE, 0xE4, 0xFF, 0x00, 0x82, 0x43, 0x7F, 0xC8, 0xB7, 0xE3,
+	0xDF, 0xFB, 0x08, 0x58, 0xFF, 0x00, 0xE8, 0xB9, 0xA8, 0x7A, 0x21, 0x3D, 0x8F, 0xB3, 0x2D, 0xBE,
+	0xE1, 0x38, 0xEA, 0xD9, 0x19, 0x3E, 0xD5, 0x25, 0x36, 0x0F, 0xF5, 0x4B, 0x4E, 0xA0, 0x76, 0xB6,
+	0x88, 0x28, 0x3D, 0x28, 0xA0, 0xF4, 0xA0, 0x0F, 0x85, 0x3F, 0xE0, 0xAF, 0xBF, 0xF2, 0x32, 0x78,
+	0x1F, 0xFE, 0xBC, 0xAF, 0xBF, 0xF4, 0x64, 0x75, 0xF1, 0xB5, 0x7D, 0x93, 0xFF, 0x00, 0x05, 0x7D,
+	0xFF, 0x00, 0x91, 0x93, 0xC0, 0xFF, 0x00, 0xF5, 0xE5, 0x7D, 0xFF, 0x00, 0xA3, 0x23, 0xAF, 0x8D,
+	0xA8, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0x1D, 0x6B, 0xEA, 0xFF, 0x00, 0xF8, 0x24, 0x8F, 0xFC, 0x96,
+	0x9F, 0x13, 0x7F, 0xD8, 0xA8, 0xBF, 0xFA, 0x53, 0x15, 0x7C, 0xA0, 0x3A, 0xD7, 0xD5, 0xFF, 0x00,
+	0xF0, 0x49, 0x1F, 0xF9, 0x2D, 0x3E, 0x26, 0xFF, 0x00, 0xB1, 0x51, 0x7F, 0xF4, 0xA6, 0x2A, 0x00,
+	0xF5, 0x9F, 0xF8, 0x2B, 0x29, 0xFF, 0x00, 0x8C, 0x77, 0xD0, 0xFF, 0x00, 0xEC, 0x72, 0x87, 0xFF,
+	0x00, 0x49, 0x6E, 0x6B, 0xF3, 0xDE, 0xBF, 0x42, 0x3F, 0xE0, 0xAC, 0xA3, 0xFE, 0x31, 0xE3, 0x43,
+	0x3F, 0xF5, 0x38, 0xC3, 0xFF, 0x00, 0xA4, 0xB7, 0x35, 0xF9, 0xEF, 0x53, 0x1F, 0xEB, 0xEE, 0x2A,
+	0x5B, 0x20, 0xA2, 0x8A, 0x2A, 0x89, 0x0A, 0xF7, 0xAF, 0xF8, 0x26, 0xC7, 0xFC, 0x9D, 0xCE, 0x83,
+	0xFF, 0x00, 0x60, 0xFD, 0x43, 0xFF, 0x00, 0x49, 0xDE, 0xBC, 0x16, 0xBD, 0xEB, 0xFE, 0x09, 0xB1,
+	0xFF, 0x00, 0x27, 0x73, 0xA0, 0xFF, 0x00, 0xD8, 0x3F, 0x50, 0xFF, 0x00, 0xD2, 0x77, 0xA0, 0x0F,
+	0xB1, 0x3F, 0xE0, 0xA2, 0x87, 0xFE, 0x30, 0xF3, 0xC5, 0xBF, 0xF5, 0xD2, 0xC7, 0xFF, 0x00, 0x4B,
+	0x60, 0xAF, 0xCC, 0x1A, 0xFD, 0x3E, 0xFF, 0x00, 0x82, 0x8A, 0x0F, 0xF8, 0xC3, 0xCF, 0x16, 0x9F,
+	0xFA, 0x69, 0x63, 0xFF, 0x00, 0xA5, 0xB0, 0x57, 0xE6, 0x0D, 0x4C, 0x7F, 0xAF, 0xB8, 0xA7, 0xB2,
+	0xF4, 0x0A, 0x28, 0xA2, 0xA8, 0x90, 0xAF, 0x44, 0xFD, 0x92, 0xBF, 0xE4, 0xE7, 0x3C, 0x03, 0xFF,
+	0x00, 0x63, 0x55, 0xA7, 0xFE, 0x84, 0x2B, 0xCE, 0xEB, 0xD1, 0x3F, 0x64, 0xAF, 0xF9, 0x39, 0xCF,
+	0x00, 0xFF, 0x00, 0xD8, 0xD5, 0x69, 0xFF, 0x00, 0xA1, 0x0A, 0x00, 0xFD, 0x2C, 0xFD, 0xA9, 0x0F,
+	0xFC, 0x63, 0x47, 0xC4, 0x4F, 0xFB, 0x12, 0x75, 0x3F, 0xFD, 0x25, 0x92, 0xBF, 0x1A, 0xEB, 0xF6,
+	0x4F, 0xF6, 0xA4, 0x19, 0xFD, 0x9A, 0x3E, 0x22, 0x7F, 0xD8, 0x95, 0xA9, 0xFF, 0x00, 0xE9, 0x2C,
+	0x95, 0xF8, 0xD9, 0x5F, 0x9E, 0xF1, 0x87, 0xFB, 0xC5, 0x2F, 0xF0, 0xBF, 0xCC, 0xFE, 0x92, 0xF0,
+	0x2F, 0xFE, 0x45, 0x78, 0xCF, 0xF1, 0xC7, 0xFF, 0x00, 0x49, 0x61, 0x45, 0x14, 0x57, 0xC6, 0xEA,
+	0x7E, 0xEF, 0x66, 0x15, 0xF4, 0x3F, 0xFC, 0x12, 0xF3, 0xFE, 0x4E, 0xEB, 0x49, 0xFF, 0x00, 0xB0,
+	0x55, 0xF7, 0xFE, 0x8A, 0x35, 0xF3, 0xC5, 0x7D, 0x0D, 0xFF, 0x00, 0x04, 0xBD, 0x19, 0xFD, 0xAE,
+	0x74, 0x91, 0xFF, 0x00, 0x50, 0xAB, 0xEF, 0xFD, 0x14, 0x6B, 0xD2, 0xCA, 0x3F, 0xE4, 0x65, 0x4B,
+	0xFC, 0x48, 0xF9, 0x2E, 0x3A, 0xFF, 0x00, 0x92, 0x3F, 0x1B, 0xFF, 0x00, 0x5E, 0xE4, 0x7D, 0xA5,
+	0xFF, 0x00, 0x05, 0x29, 0xFF, 0x00, 0x93, 0x49, 0xD7, 0x3F, 0xEB, 0xF2, 0xC7, 0xFF, 0x00, 0x4A,
+	0x16, 0xBF, 0x32, 0xEB, 0xF4, 0xD3, 0xFE, 0x0A, 0x53, 0xFF, 0x00, 0x26, 0x93, 0xAE, 0x7F, 0xD7,
+	0xE5, 0x8F, 0xFE, 0x94, 0x2D, 0x7E, 0x65, 0xD7, 0xEC, 0x47, 0xF1, 0x18, 0x52, 0x49, 0xC8, 0x62,
+	0xE8, 0xA7, 0x6A, 0xE1, 0x91, 0xFB, 0xA9, 0xA5, 0xA2, 0x80, 0x3F, 0x23, 0xFF, 0x00, 0xE0, 0xA1,
+	0x5F, 0x09, 0xFF, 0x00, 0xE1, 0x53, 0x7E, 0xD6, 0x5E, 0x24, 0xD3, 0xA2, 0x8D, 0x96, 0xCB, 0x5A,
+	0xB8, 0xFE, 0xD7, 0xB1, 0x1F, 0xC2, 0xF1, 0xDC, 0x92, 0xEE, 0xA3, 0xD8, 0x4C, 0x25, 0x15, 0xE2,
+	0x7B, 0x8B, 0x7C, 0xC7, 0xBF, 0x35, 0xFA, 0x25, 0xFF, 0x00, 0x05, 0x89, 0xF8, 0x38, 0x75, 0xFF,
+	0x00, 0x86, 0x9A, 0x0F, 0xC6, 0xDD, 0x2A, 0xD8, 0x1B, 0x8F, 0x0F, 0xDD, 0x35, 0x8E, 0xA5, 0x32,
+	0xF5, 0x5B, 0x79, 0xF8, 0x8E, 0x4F, 0xF8, 0x0C, 0xBB, 0x62, 0xFF, 0x00, 0xB6, 0xF5, 0xF9, 0xDB,
+	0x80, 0x38, 0x09, 0xB7, 0xFD, 0x93, 0xDB, 0xDA, 0xB9, 0x65, 0xA4, 0xAE, 0x7A, 0x94, 0x25, 0xCD,
+	0x4D, 0x5C, 0x28, 0xA2, 0x8A, 0x93, 0x40, 0xA2, 0x8A, 0x28, 0x00, 0xA1, 0x7A, 0x9F, 0xC3, 0xF9,
+	0x1A, 0x28, 0x5E, 0xA7, 0xF0, 0xFE, 0x46, 0xA9, 0x7C, 0x48, 0x1E, 0xCC, 0xFE, 0x86, 0x3F, 0xE0,
+	0xF0, 0x4F, 0xF9, 0x32, 0x0F, 0x86, 0x3F, 0xF6, 0x56, 0x13, 0xFF, 0x00, 0x4D, 0x97, 0xF4, 0xFF,
+	0x00, 0xF8, 0x22, 0x57, 0xFC, 0xAB, 0x79, 0xF1, 0x33, 0xFE, 0xC0, 0x1E, 0x3B, 0xFF, 0x00, 0xD2,
+	0x29, 0xA9, 0x9F, 0xF0, 0x78, 0x27, 0xFC, 0x99, 0x07, 0xC3, 0x1F, 0xFB, 0x2B, 0x09, 0xFF, 0x00,
+	0xA6, 0xCB, 0xFA, 0x7F, 0xFC, 0x11, 0x2B, 0xFE, 0x55, 0xBC, 0xF8, 0x99, 0xFF, 0x00, 0x60, 0x0F,
+	0x1D, 0xFF, 0x00, 0xE9, 0x14, 0xD5, 0xA3, 0xFE, 0x21, 0xC6, 0xFF, 0x00, 0xDD, 0xFE, 0x67, 0xC7,
+	0x1F, 0xF0, 0x68, 0x2F, 0xFC, 0xA4, 0x9F, 0xC6, 0xDF, 0xF6, 0x43, 0xF5, 0x2F, 0xFD, 0x3C, 0x68,
+	0xB5, 0xE5, 0x9F, 0xF0, 0x56, 0x4F, 0xF9, 0x58, 0x63, 0xC5, 0x7F, 0xF6, 0x55, 0x7C, 0x35, 0xFF,
+	0x00, 0xA4, 0xFA, 0x7D, 0x7A, 0x9F, 0xFC, 0x1A, 0x0B, 0xFF, 0x00, 0x29, 0x27, 0xF1, 0xB7, 0xFD,
+	0x90, 0xFD, 0x4B, 0xFF, 0x00, 0x4F, 0x1A, 0x2D, 0x79, 0x67, 0xFC, 0x15, 0x93, 0xFE, 0x56, 0x18,
+	0xF1, 0x5F, 0xFD, 0x95, 0x5F, 0x0D, 0x7F, 0xE9, 0x3E, 0x9F, 0x53, 0xFF, 0x00, 0x2E, 0xD1, 0x5F,
+	0xF2, 0xFA, 0x5E, 0x87, 0xDB, 0xFF, 0x00, 0xF0, 0x79, 0x2F, 0xFC, 0x93, 0x5F, 0x80, 0xBF, 0xF6,
+	0x1E, 0xF1, 0x07, 0xFE, 0x93, 0x58, 0xD7, 0x77, 0xFF, 0x00, 0x04, 0xC9, 0xFF, 0x00, 0x95, 0x54,
+	0x7E, 0x23, 0xFF, 0x00, 0xD9, 0x28, 0xF8, 0x95, 0xFF, 0x00, 0xA2, 0xF5, 0x4A, 0xE1, 0x3F, 0xE0,
+	0xF2, 0x5F, 0xF9, 0x26, 0xBF, 0x01, 0x7F, 0xEC, 0x3D, 0xE2, 0x0F, 0xFD, 0x26, 0xB1, 0xAE, 0xEF,
+	0xFE, 0x09, 0x93, 0xFF, 0x00, 0x2A, 0xA8, 0xFC, 0x47, 0xFF, 0x00, 0xB2, 0x51, 0xF1, 0x2B, 0xFF,
+	0x00, 0x45, 0xEA, 0x95, 0x4B, 0xE2, 0x66, 0x6B, 0xF8, 0x2B, 0xD4, 0xF9, 0x4B, 0xFE, 0x0C, 0xFC,
+	0xFF, 0x00, 0x93, 0xE2, 0xF8, 0x9D, 0xFF, 0x00, 0x64, 0xAF, 0xFF, 0x00, 0x72, 0x96, 0x75, 0xE2,
+	0x1F, 0xB6, 0x8F, 0xFC, 0xAC, 0x8D, 0xAA, 0x7F, 0xD9, 0xC6, 0x68, 0x7F, 0xFA, 0x5D, 0x67, 0x5E,
+	0xDF, 0xFF, 0x00, 0x06, 0x7E, 0x7F, 0xC9, 0xF1, 0x7C, 0x4E, 0xFF, 0x00, 0xB2, 0x57, 0xFF, 0x00,
+	0xB9, 0x4B, 0x3A, 0xF1, 0x0F, 0xDB, 0x47, 0xFE, 0x56, 0x46, 0xD5, 0x3F, 0xEC, 0xE3, 0x34, 0x3F,
+	0xFD, 0x2E, 0xB3, 0xAC, 0xDF, 0xF0, 0xE3, 0xEA, 0x69, 0xFF, 0x00, 0x2F, 0xA5, 0xE8, 0x7D, 0x8D,
+	0xFF, 0x00, 0x07, 0x9A, 0xFD, 0xEF, 0xD9, 0xBF, 0xFD, 0xDF, 0x18, 0x7F, 0x3D, 0x12, 0xBD, 0x53,
+	0xE1, 0xEF, 0xFC, 0xAA, 0x2F, 0x71, 0xFF, 0x00, 0x64, 0xA7, 0x54, 0xFF, 0x00, 0xD3, 0xC4, 0xF5,
+	0xE5, 0x7F, 0xF0, 0x79, 0xAF, 0xDE, 0xFD, 0x9B, 0xFF, 0x00, 0xDD, 0xF1, 0x87, 0xF3, 0xD1, 0x2B,
+	0xD5, 0x3E, 0x1E, 0xFF, 0x00, 0xCA, 0xA2, 0xF7, 0x1F, 0xF6, 0x4A, 0x75, 0x4F, 0xFD, 0x3C, 0x4F,
+	0x5B, 0x75, 0x66, 0x6B, 0xF8, 0x71, 0xF5, 0x3E, 0x70, 0xFF, 0x00, 0x83, 0x3A, 0xBF, 0xE4, 0xE4,
+	0xFE, 0x32, 0x7F, 0xD8, 0x8B, 0x63, 0xFF, 0x00, 0xA5, 0xAD, 0x5F, 0x2B, 0xCB, 0xFF, 0x00, 0x2B,
+	0x26, 0xFF, 0x00, 0xDD, 0xF2, 0x2F, 0xFE, 0xA6, 0x22, 0xBE, 0xA8, 0xFF, 0x00, 0x83, 0x3A, 0xBF,
+	0xE4, 0xE4, 0xFE, 0x32, 0x7F, 0xD8, 0x8B, 0x63, 0xFF, 0x00, 0xA5, 0xAD, 0x5F, 0x2B, 0xCB, 0xFF,
+	0x00, 0x2B, 0x26, 0xFF, 0x00, 0xDD, 0xF2, 0x2F, 0xFE, 0xA6, 0x22, 0xB1, 0x7F, 0xC3, 0x8F, 0xA9,
+	0xA7, 0xFC, 0xBC, 0x97, 0xA1, 0xF6, 0x47, 0xFC, 0x1E, 0x47, 0xFF, 0x00, 0x25, 0x23, 0xE0, 0x1F,
+	0xFD, 0x80, 0x35, 0xEF, 0xFD, 0x29, 0xD3, 0xEB, 0xDB, 0xFE, 0x22, 0xFF, 0x00, 0xCA, 0xA2, 0x70,
+	0xFF, 0x00, 0xD9, 0x2A, 0xD3, 0x3F, 0xF4, 0xF1, 0x05, 0x78, 0x87, 0xFC, 0x1E, 0x47, 0xFF, 0x00,
+	0x25, 0x23, 0xE0, 0x1F, 0xFD, 0x80, 0x35, 0xEF, 0xFD, 0x29, 0xD3, 0xEB, 0xDB, 0xFE, 0x22, 0xFF,
+	0x00, 0xCA, 0xA2, 0x70, 0xFF, 0x00, 0xD9, 0x2A, 0xD3, 0x3F, 0xF4, 0xF1, 0x05, 0x69, 0xD5, 0x92,
+	0xFF, 0x00, 0x83, 0x0F, 0x53, 0xCA, 0xFF, 0x00, 0xE0, 0xCD, 0x0F, 0xF5, 0x9F, 0xB4, 0x77, 0xD3,
+	0xC1, 0xFF, 0x00, 0xCF, 0x5E, 0xAF, 0x8E, 0xBF, 0x62, 0xFF, 0x00, 0xF9, 0x59, 0x17, 0x4D, 0xFF,
+	0x00, 0xB3, 0x90, 0xD6, 0xFF, 0x00, 0xF4, 0xB2, 0xF6, 0xBE, 0xC5, 0xFF, 0x00, 0x83, 0x34, 0x3F,
+	0xD6, 0x7E, 0xD1, 0xDF, 0x4F, 0x07, 0xFF, 0x00, 0x3D, 0x7A, 0xBE, 0x3A, 0xFD, 0x8B, 0xFF, 0x00,
+	0xE5, 0x64, 0x5D, 0x37, 0xFE, 0xCE, 0x43, 0x5B, 0xFF, 0x00, 0xD2, 0xCB, 0xDA, 0x5F, 0x65, 0x14,
+	0xBE, 0x29, 0x9E, 0xE3, 0xFF, 0x00, 0x07, 0x84, 0xFF, 0x00, 0xC9, 0xEE, 0xFC, 0x31, 0xFF, 0x00,
+	0xB2, 0x53, 0xFF, 0x00, 0xB9, 0x2B, 0xCA, 0xFA, 0xAB, 0xF6, 0xC9, 0xCF, 0xFC, 0x42, 0x33, 0xA2,
+	0xFF, 0x00, 0xD9, 0x2B, 0xF0, 0x1F, 0xFE, 0x9E, 0x74, 0x8A, 0xF9, 0x57, 0xFE, 0x0F, 0x09, 0xFF,
+	0x00, 0x93, 0xDD, 0xF8, 0x63, 0xFF, 0x00, 0x64, 0xA7, 0xFF, 0x00, 0x72, 0x57, 0x95, 0xF5, 0x57,
+	0xED, 0x93, 0x9F, 0xF8, 0x84, 0x67, 0x45, 0xFF, 0x00, 0xB2, 0x57, 0xE0, 0x3F, 0xFD, 0x3C, 0xE9,
+	0x14, 0xFE, 0xD3, 0x27, 0xFE, 0x5C, 0xC3, 0xD4, 0xE1, 0x3F, 0xE0, 0xCD, 0x8F, 0xF9, 0x26, 0x9F,
+	0x1E, 0xBF, 0xEC, 0x35, 0xE1, 0xFF, 0x00, 0xFD, 0x11, 0x7B, 0x5F, 0x0F, 0xFF, 0x00, 0xC1, 0x26,
+	0x3F, 0xE5, 0x61, 0x8F, 0x09, 0xFF, 0x00, 0xD9, 0x56, 0xF1, 0x1F, 0xFE, 0x93, 0xEA, 0x95, 0xF7,
+	0x07, 0xFC, 0x19, 0xB1, 0xFF, 0x00, 0x24, 0xD3, 0xE3, 0xD7, 0xFD, 0x86, 0xBC, 0x3F, 0xFF, 0x00,
+	0xA2, 0x2F, 0x6B, 0xE1, 0xFF, 0x00, 0xF8, 0x24, 0xC7, 0xFC, 0xAC, 0x31, 0xE1, 0x3F, 0xFB, 0x2A,
+	0xDE, 0x23, 0xFF, 0x00, 0xD2, 0x7D, 0x52, 0x97, 0xD9, 0x45, 0x47, 0xE2, 0x9F, 0xA1, 0xEA, 0x9F,
+	0xF0, 0x77, 0xCF, 0xFC, 0xA4, 0xA7, 0xC0, 0xFF, 0x00, 0xF6, 0x44, 0x74, 0xBF, 0xFD, 0x3C, 0xEA,
+	0xF5, 0xF6, 0x2F, 0xFC, 0x16, 0xC7, 0xFE, 0x55, 0xBF, 0xF8, 0x65, 0xFF, 0x00, 0x60, 0x6F, 0x01,
+	0xFF, 0x00, 0xE9, 0x14, 0x35, 0xF1, 0xD7, 0xFC, 0x1D, 0xF3, 0xFF, 0x00, 0x29, 0x29, 0xF0, 0x3F,
+	0xFD, 0x91, 0x1D, 0x2F, 0xFF, 0x00, 0x4F, 0x3A, 0xBD, 0x7D, 0x8B, 0xFF, 0x00, 0x05, 0xB1, 0xFF,
+	0x00, 0x95, 0x6F, 0xFE, 0x19, 0x7F, 0xD8, 0x1B, 0xC0, 0x7F, 0xFA, 0x45, 0x0D, 0x27, 0xD4, 0x8F,
+	0xB3, 0x03, 0x07, 0xFE, 0x0C, 0xE9, 0xFF, 0x00, 0x93, 0x6B, 0xF8, 0xC7, 0xFF, 0x00, 0x63, 0xC6,
+	0x9D, 0xFF, 0x00, 0xA4, 0x75, 0xF9, 0xCD, 0xFF, 0x00, 0x06, 0xDC, 0xFF, 0x00, 0xCA, 0x68, 0xBE,
+	0x0B, 0xFF, 0x00, 0xBD, 0xE2, 0x1F, 0xFD, 0x47, 0x35, 0x3A, 0xFD, 0x19, 0xFF, 0x00, 0x83, 0x3A,
+	0x7F, 0xE4, 0xDA, 0xFE, 0x31, 0xFF, 0x00, 0xD8, 0xF1, 0xA7, 0x7F, 0xE9, 0x1D, 0x7E, 0x73, 0x7F,
+	0xC1, 0xB7, 0x3F, 0xF2, 0x9A, 0x2F, 0x82, 0xFF, 0x00, 0xEF, 0x78, 0x87, 0xFF, 0x00, 0x51, 0xCD,
+	0x4E, 0x9C, 0x7F, 0x86, 0x87, 0xD6, 0x67, 0xAB, 0x7F, 0xC1, 0xD9, 0x9F, 0xF2, 0x94, 0x2D, 0x3F,
+	0xFE, 0xC9, 0x5E, 0x91, 0xFF, 0x00, 0xA5, 0x57, 0xD5, 0xF7, 0x1F, 0xFC, 0x1C, 0x59, 0xFF, 0x00,
+	0x28, 0x25, 0xF8, 0x57, 0xFF, 0x00, 0x63, 0x07, 0x84, 0x3F, 0xF4, 0xD7, 0x3D, 0x7C, 0x39, 0xFF,
+	0x00, 0x07, 0x66, 0x7F, 0xCA, 0x50, 0xB4, 0xFF, 0x00, 0xFB, 0x25, 0x7A, 0x47, 0xFE, 0x95, 0x5F,
+	0x57, 0xDC, 0x7F, 0xF0, 0x71, 0x67, 0xFC, 0xA0, 0x97, 0xE1, 0x5F, 0xFD, 0x8C, 0x1E, 0x10, 0xFF,
+	0x00, 0xD3, 0x5C, 0xF4, 0xBB, 0x8B, 0xEC, 0xC0, 0x4F, 0xF8, 0x35, 0x4F, 0xFE, 0x51, 0x1D, 0xF1,
+	0x63, 0xFE, 0xCA, 0xB6, 0xB9, 0xFF, 0x00, 0xA6, 0x1D, 0x22, 0xBE, 0x00, 0xFF, 0x00, 0x83, 0x57,
+	0xFF, 0x00, 0xE5, 0x2C, 0x9A, 0x4F, 0xFD, 0x88, 0xBA, 0xD7, 0xFE, 0x8B, 0x5A, 0xFB, 0xFF, 0x00,
+	0xFE, 0x0D, 0x54, 0xFF, 0x00, 0x94, 0x47, 0x7C, 0x58, 0xFF, 0x00, 0xB2, 0xAD, 0xAE, 0x7F, 0xE9,
+	0x87, 0x48, 0xAF, 0x80, 0x3F, 0xE0, 0xD5, 0xFF, 0x00, 0xF9, 0x4B, 0x26, 0x93, 0xFF, 0x00, 0x62,
+	0x2E, 0xB5, 0xFF, 0x00, 0xA2, 0xD6, 0x9B, 0xF8, 0x51, 0x4F, 0x69, 0x98, 0x7F, 0xF0, 0x73, 0x8F,
+	0xFC, 0xA6, 0x1F, 0xC7, 0xFF, 0x00, 0xF6, 0x05, 0xD0, 0xBF, 0xF4, 0xD9, 0x6B, 0x5F, 0x7F, 0xFF,
+	0x00, 0xC1, 0xD7, 0x3F, 0xF2, 0x8D, 0x9F, 0x82, 0x3F, 0xF6, 0x3E, 0x59, 0x7F, 0xE9, 0x9A, 0xF2,
+	0xBE, 0x00, 0xFF, 0x00, 0x83, 0x9C, 0x7F, 0xE5, 0x30, 0xFE, 0x3F, 0xFF, 0x00, 0xB0, 0x2E, 0x85,
+	0xFF, 0x00, 0xA6, 0xCB, 0x5A, 0xFB, 0xFF, 0x00, 0xFE, 0x0E, 0xB9, 0xFF, 0x00, 0x94, 0x6C, 0xFC,
+	0x11, 0xFF, 0x00, 0xB1, 0xF2, 0xCB, 0xFF, 0x00, 0x4C, 0xD7, 0x94, 0xBE, 0xCC, 0x87, 0x1D, 0xE0,
+	0x6F, 0x7F, 0xC1, 0xBA, 0x1F, 0xF2, 0x82, 0x3F, 0x8A, 0x5F, 0xF6, 0x1C, 0xF1, 0x5F, 0xFE, 0x9A,
+	0xAD, 0xAB, 0xE1, 0x8F, 0xF8, 0x34, 0xC3, 0xFE, 0x52, 0x87, 0x7D, 0xFF, 0x00, 0x64, 0x9F, 0x56,
+	0xFF, 0x00, 0xD2, 0xCD, 0x3E, 0xBE, 0xE7, 0xFF, 0x00, 0x83, 0x74, 0x3F, 0xE5, 0x04, 0x7F, 0x14,
+	0xBF, 0xEC, 0x39, 0xE2, 0xBF, 0xFD, 0x35, 0x5B, 0x57, 0xC3, 0x1F, 0xF0, 0x69, 0x87, 0xFC, 0xA5,
+	0x0E, 0xFB, 0xFE, 0xC9, 0x3E, 0xAD, 0xFF, 0x00, 0xA5, 0x9A, 0x7D, 0x57, 0x58, 0x87, 0xD9, 0xA8,
+	0x71, 0x1F, 0xF0, 0x5F, 0x1F, 0xF9, 0x4F, 0x5F, 0xC4, 0x6F, 0xFB, 0x0E, 0x78, 0x4B, 0xFF, 0x00,
+	0x4C, 0x5A, 0x45, 0x7E, 0x81, 0x7F, 0xC1, 0xE2, 0xFF, 0x00, 0xF2, 0x6D, 0x9F, 0x06, 0xFF, 0x00,
+	0xEC, 0x7A, 0xBD, 0xFF, 0x00, 0xD2, 0x35, 0xAF, 0xCF, 0xDF, 0xF8, 0x2F, 0x8F, 0xFC, 0xA7, 0xAF,
+	0xE2, 0x37, 0xFD, 0x87, 0x3C, 0x25, 0xFF, 0x00, 0xA6, 0x2D, 0x22, 0xBF, 0x40, 0xBF, 0xE0, 0xF1,
+	0x7F, 0xF9, 0x36, 0xCF, 0x83, 0x7F, 0xF6, 0x3D, 0x5E, 0xFF, 0x00, 0xE9, 0x1A, 0xD3, 0xEA, 0xC3,
+	0xED, 0x53, 0x36, 0xBF, 0xE0, 0x98, 0xFF, 0x00, 0xF2, 0xAA, 0x77, 0xC4, 0x6F, 0xFB, 0x24, 0xFF,
+	0x00, 0x12, 0xBF, 0xF4, 0x5E, 0xA9, 0x5F, 0x1D, 0x7F, 0xC1, 0xA1, 0x1F, 0xF2, 0x92, 0x8F, 0x1C,
+	0x7F, 0xD9, 0x0F, 0xD4, 0xBF, 0xF4, 0xF3, 0xA2, 0xD7, 0xD8, 0xBF, 0xF0, 0x4C, 0x7F, 0xF9, 0x55,
+	0x3B, 0xE2, 0x37, 0xFD, 0x92, 0x7F, 0x89, 0x5F, 0xFA, 0x2F, 0x54, 0xAF, 0x8E, 0xBF, 0xE0, 0xD0,
+	0x8F, 0xF9, 0x49, 0x47, 0x8E, 0x3F, 0xEC, 0x87, 0xEA, 0x5F, 0xFA, 0x79, 0xD1, 0x6A, 0x7A, 0xC4,
+	0xCD, 0xFF, 0x00, 0x0E, 0x7E, 0xA7, 0x95, 0x7F, 0xC1, 0x58, 0xFF, 0x00, 0xE5, 0x61, 0x7F, 0x15,
+	0x7F, 0xD9, 0x54, 0xF0, 0xD7, 0xFE, 0x93, 0xE9, 0xF5, 0xF7, 0x07, 0xFC, 0x1E, 0x4D, 0xFF, 0x00,
+	0x24, 0xDF, 0xE0, 0x2F, 0xFD, 0x87, 0x7C, 0x41, 0xFF, 0x00, 0xA4, 0xD6, 0x35, 0xF0, 0xFF, 0x00,
+	0xFC, 0x15, 0x8F, 0xFE, 0x56, 0x17, 0xF1, 0x57, 0xFD, 0x95, 0x4F, 0x0D, 0x7F, 0xE9, 0x3E, 0x9F,
+	0x5F, 0x70, 0x7F, 0xC1, 0xE4, 0xDF, 0xF2, 0x4D, 0xFE, 0x02, 0xFF, 0x00, 0xD8, 0x77, 0xC4, 0x1F,
+	0xFA, 0x4D, 0x63, 0x4B, 0xED, 0x48, 0xAF, 0xF9, 0x7B, 0x03, 0xBA, 0xFD, 0x8E, 0x3F, 0xE5, 0x51,
+	0x4D, 0x6B, 0xFE, 0xC9, 0x3F, 0x8F, 0x3F, 0xF4, 0xF1, 0xAB, 0xD7, 0xCE, 0x3F, 0xF0, 0x67, 0x6F,
+	0xFC, 0x9C, 0xB7, 0xC6, 0x5F, 0xFB, 0x11, 0x6C, 0x7F, 0xF4, 0xB5, 0xAB, 0xE8, 0xEF, 0xD8, 0xE3,
+	0xFE, 0x55, 0x14, 0xD6, 0xBF, 0xEC, 0x93, 0xF8, 0xF3, 0xFF, 0x00, 0x4F, 0x1A, 0xBD, 0x7C, 0xE3,
+	0xFF, 0x00, 0x06, 0x76, 0xFF, 0x00, 0xC9, 0xCB, 0x7C, 0x65, 0xFF, 0x00, 0xB1, 0x16, 0xC7, 0xFF,
+	0x00, 0x4B, 0x5A, 0xAB, 0xED, 0x44, 0x3F, 0xE5, 0xDD, 0x4F, 0x53, 0xE5, 0x6F, 0xDA, 0x4B, 0xFE,
+	0x56, 0x2C, 0xD6, 0x3F, 0xEC, 0xEB, 0x6D, 0xFF, 0x00, 0xF4, 0xF5, 0x6F, 0x5F, 0x63, 0xFF, 0x00,
+	0xC1, 0xE4, 0x9F, 0xF2, 0x52, 0xBE, 0x02, 0x7F, 0xD8, 0x07, 0x5F, 0xFF, 0x00, 0xD2, 0x9D, 0x3E,
+	0xBE, 0x38, 0xFD, 0xA4, 0xBF, 0xE5, 0x62, 0xCD, 0x63, 0xFE, 0xCE, 0xB6, 0xDF, 0xFF, 0x00, 0x4F,
+	0x56, 0xF5, 0xF6, 0x3F, 0xFC, 0x1E, 0x49, 0xFF, 0x00, 0x25, 0x2B, 0xE0, 0x27, 0xFD, 0x80, 0x75,
+	0xFF, 0x00, 0xFD, 0x29, 0xD3, 0xEA, 0x63, 0xF6, 0x8A, 0x8F, 0xF1, 0x61, 0xE8, 0x7B, 0x7F, 0xC3,
+	0xDF, 0xF9, 0x54, 0x5E, 0xE3, 0xFE, 0xC9, 0x4E, 0xA9, 0xFF, 0x00, 0xA7, 0x89, 0xEB, 0xC3, 0xFF,
+	0x00, 0xE0, 0xCD, 0x8F, 0xF9, 0x29, 0x5F, 0x1E, 0xBF, 0xEC, 0x09, 0xE1, 0xEF, 0xFD, 0x1D, 0xA8,
+	0x57, 0xB8, 0x7C, 0x3D, 0xFF, 0x00, 0x95, 0x45, 0xEE, 0x3F, 0xEC, 0x94, 0xEA, 0x9F, 0xFA, 0x78,
+	0x9E, 0xBC, 0x3F, 0xFE, 0x0C, 0xD8, 0xFF, 0x00, 0x92, 0x95, 0xF1, 0xEB, 0xFE, 0xC0, 0x9E, 0x1E,
+	0xFF, 0x00, 0xD1, 0xDA, 0x85, 0x6A, 0xBE, 0x24, 0x4C, 0x7F, 0x87, 0x23, 0xE5, 0x5F, 0x87, 0xDF,
+	0xF2, 0xB3, 0x64, 0xFF, 0x00, 0xF6, 0x78, 0xFA, 0xA7, 0xFE, 0xA4, 0x33, 0xD7, 0xD1, 0xBF, 0xF0,
+	0x78, 0xC7, 0xFC, 0x9C, 0x87, 0xC1, 0xBF, 0xFB, 0x10, 0xF5, 0x0F, 0xFD, 0x2D, 0x5A, 0xF9, 0xCB,
+	0xE1, 0xF7, 0xFC, 0xAC, 0xD9, 0x3F, 0xFD, 0x9E, 0x3E, 0xA9, 0xFF, 0x00, 0xA9, 0x0C, 0xF5, 0xF4,
+	0x6F, 0xFC, 0x1E, 0x31, 0xFF, 0x00, 0x27, 0x21, 0xF0, 0x6F, 0xFE, 0xC4, 0x3D, 0x43, 0xFF, 0x00,
+	0x4B, 0x56, 0xA3, 0xA3, 0x34, 0x87, 0xF1, 0x21, 0xE8, 0x7D, 0x21, 0xFB, 0x64, 0xE7, 0xFE, 0x21,
+	0x1A, 0xD1, 0xFF, 0x00, 0xEC, 0x95, 0xF8, 0x0F, 0xFF, 0x00, 0x4F, 0x5A, 0x45, 0x79, 0x3F, 0xFC,
+	0x19, 0x93, 0xF7, 0x7F, 0x68, 0xDF, 0xF7, 0x3C, 0x1F, 0xFF, 0x00, 0xB9, 0xEA, 0xF5, 0x8F, 0xDB,
+	0x27, 0x3F, 0xF1, 0x08, 0xD6, 0x8F, 0xFF, 0x00, 0x64, 0xAF, 0xC0, 0x7F, 0xFA, 0x7A, 0xD2, 0x2B,
+	0xC9, 0xFF, 0x00, 0xE0, 0xCC, 0x9F, 0xBB, 0xFB, 0x46, 0xFF, 0x00, 0xB9, 0xE0, 0xFF, 0x00, 0xFD,
+	0xCF, 0x51, 0xF6, 0x91, 0x8F, 0xFC, 0xBB, 0x97, 0xA9, 0xF1, 0xDF, 0xEC, 0x5D, 0xFF, 0x00, 0x2B,
+	0x23, 0xE9, 0xBF, 0xF6, 0x72, 0x1A, 0xDF, 0xFE, 0x96, 0x5E, 0x57, 0xB9, 0x7F, 0xC1, 0xE1, 0x3F,
+	0xF2, 0x7B, 0xBF, 0x0C, 0x7F, 0xEC, 0x94, 0xFF, 0x00, 0xEE, 0x4A, 0xF2, 0xBC, 0x37, 0xF6, 0x2E,
+	0xFF, 0x00, 0x95, 0x91, 0xF4, 0xDF, 0xFB, 0x39, 0x0D, 0x6F, 0xFF, 0x00, 0x4B, 0x2F, 0x2B, 0xDC,
+	0xBF, 0xE0, 0xF0, 0x9F, 0xF9, 0x3D, 0xDF, 0x86, 0x3F, 0xF6, 0x4A, 0x7F, 0xF7, 0x25, 0x79, 0x47,
+	0xD9, 0x36, 0xFF, 0x00, 0x97, 0xF1, 0xF4, 0x3E, 0xA7, 0xFF, 0x00, 0x82, 0x9C, 0xFF, 0x00, 0xCA,
+	0xAA, 0x9F, 0x0E, 0x3F, 0xEC, 0x95, 0xFC, 0x33, 0xFF, 0x00, 0xD1, 0x7A, 0x5D, 0x61, 0x7F, 0xC1,
+	0x9D, 0x3F, 0xF2, 0x6D, 0x3F, 0x18, 0xFF, 0x00, 0xEC, 0x79, 0xB0, 0xFF, 0x00, 0xD2, 0x2A, 0xDD,
+	0xFF, 0x00, 0x82, 0x9C, 0xFF, 0x00, 0xCA, 0xAA, 0x9F, 0x0E, 0x3F, 0xEC, 0x95, 0xFC, 0x33, 0xFF,
+	0x00, 0xD1, 0x7A, 0x5D, 0x61, 0x7F, 0xC1, 0x9D, 0x3F, 0xF2, 0x6D, 0x3F, 0x18, 0xFF, 0x00, 0xEC,
+	0x79, 0xB0, 0xFF, 0x00, 0xD2, 0x2A, 0x3E, 0xD2, 0x32, 0x7F, 0xC1, 0xF9, 0x9F, 0x9C, 0xFF, 0x00,
+	0xF0, 0x44, 0xAF, 0xF9, 0x4E, 0x7F, 0xC3, 0x1F, 0xFB, 0x1E, 0xB5, 0x8F, 0xFD, 0x21, 0xD4, 0x6B,
+	0xD5, 0xBF, 0xE0, 0xEC, 0xAF, 0xF9, 0x4A, 0x35, 0x8F, 0xFD, 0x92, 0x7D, 0x23, 0xFF, 0x00, 0x4A,
+	0xEF, 0xAB, 0xCA, 0x7F, 0xE0, 0x89, 0x5F, 0xF2, 0x9C, 0xFF, 0x00, 0x86, 0x3F, 0xF6, 0x3D, 0x6B,
+	0x1F, 0xFA, 0x43, 0xA8, 0xD7, 0xAB, 0x7F, 0xC1, 0xD9, 0x5F, 0xF2, 0x94, 0x6B, 0x1F, 0xFB, 0x24,
+	0xFA, 0x47, 0xFE, 0x95, 0xDF, 0x54, 0xBF, 0x84, 0xDB, 0xFE, 0x5F, 0x47, 0xD0, 0xFC, 0xC5, 0x3D,
+	0x68, 0xA0, 0xF5, 0xA2, 0xB3, 0x37, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0xEB, 0xBE, 0x02, 0xFC, 0x30,
+	0xB9, 0xF8, 0xCB, 0xF1, 0x9B, 0xC3, 0x7F, 0x0C, 0xAD, 0xE4, 0xD8, 0xBA, 0xD6, 0xAD, 0x0C, 0x37,
+	0x53, 0x7F, 0xCF, 0x3B, 0x50, 0xC0, 0xCF, 0x37, 0xFD, 0xB3, 0x45, 0x2D, 0xFF, 0x00, 0x00, 0xAE,
+	0x46, 0xBE, 0xCE, 0xFF, 0x00, 0x82, 0x3A, 0xFC, 0x1A, 0xFE, 0xDD, 0xF8, 0x8D, 0xAF, 0x7C, 0x6C,
+	0xD5, 0x2D, 0x0B, 0x5B, 0xE8, 0x56, 0xAB, 0xA7, 0x69, 0xB2, 0x37, 0x41, 0x73, 0x30, 0xDF, 0x23,
+	0x7E, 0x11, 0x62, 0x3F, 0xFB, 0x78, 0xAA, 0x8C, 0x7D, 0xEB, 0x99, 0xD4, 0x97, 0x2D, 0x3B, 0xA3,
+	0xF4, 0x2A, 0xCE, 0xD2, 0xDA, 0xC2, 0xD2, 0x2B, 0x1B, 0x2B, 0x5F, 0x26, 0x18, 0x63, 0x58, 0xE1,
+	0x87, 0xFE, 0x79, 0xA8, 0x18, 0x0B, 0xF8, 0x0E, 0x2A, 0x4A, 0x03, 0x6E, 0xF9, 0xB1, 0x8C, 0xF6,
+	0x14, 0x57, 0x51, 0xE5, 0xF9, 0x85, 0x7E, 0x9A, 0x7F, 0xC1, 0x35, 0x7F, 0xE4, 0xD1, 0xF4, 0x3F,
+	0xFA, 0xFE, 0xBF, 0xFF, 0x00, 0xD2, 0x96, 0xAF, 0xCC, 0xBA, 0xFD, 0x34, 0xFF, 0x00, 0x82, 0x6A,
+	0xFF, 0x00, 0xC9, 0xA3, 0xE8, 0x7F, 0xF5, 0xFD, 0x7F, 0xFF, 0x00, 0xA5, 0x2D, 0x40, 0x1F, 0x1C,
+	0xFF, 0x00, 0xC1, 0x51, 0xBF, 0xE4, 0xEE, 0xF5, 0x4F, 0xFB, 0x04, 0xE9, 0xFF, 0x00, 0xFA, 0x28,
+	0x57, 0xCF, 0x35, 0xF4, 0x37, 0xFC, 0x15, 0x1B, 0xFE, 0x4E, 0xEF, 0x54, 0xFF, 0x00, 0xB0, 0x4E,
+	0x9F, 0xFF, 0x00, 0xA2, 0x85, 0x7C, 0xF3, 0x41, 0xE9, 0x53, 0xF8, 0x10, 0x51, 0x45, 0x14, 0x14,
+	0x15, 0xFB, 0x1F, 0xFB, 0x30, 0xFF, 0x00, 0xC9, 0xB5, 0x7C, 0x3C, 0xFF, 0x00, 0xB1, 0x1B, 0x49,
+	0xFF, 0x00, 0xD2, 0x38, 0xAB, 0xF1, 0xC2, 0xBF, 0x63, 0xFF, 0x00, 0x66, 0x1F, 0xF9, 0x36, 0xAF,
+	0x87, 0x9F, 0xF6, 0x23, 0x69, 0x3F, 0xFA, 0x47, 0x15, 0x07, 0x3E, 0x2B, 0x68, 0x9F, 0x9B, 0x5F,
+	0xB6, 0x9F, 0xFC, 0x9D, 0x77, 0x8D, 0xBF, 0xEC, 0x38, 0x7F, 0xF4, 0x15, 0xAF, 0x2C, 0x4F, 0xB8,
+	0x3E, 0x95, 0xEA, 0x7F, 0xB6, 0x9F, 0xFC, 0x9D, 0x77, 0x8D, 0xBF, 0xEC, 0x38, 0x7F, 0xF4, 0x15,
+	0xAF, 0x2C, 0x4F, 0xB8, 0x3E, 0x94, 0x1C, 0x62, 0xD1, 0x45, 0x14, 0x00, 0x57, 0xDE, 0x9F, 0xF0,
+	0x48, 0x5F, 0xF9, 0x26, 0xBE, 0x30, 0xFF, 0x00, 0xB0, 0xE4, 0x1F, 0xFA, 0x26, 0xBE, 0x0B, 0xAF,
+	0xBD, 0x3F, 0xE0, 0x90, 0xBF, 0xF2, 0x4D, 0x7C, 0x61, 0xFF, 0x00, 0x61, 0xC8, 0x3F, 0xF4, 0x4D,
+	0x00, 0x78, 0xF7, 0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B, 0x5F, 0xFD, 0x0E,
+	0x5A, 0xF9, 0xB2, 0xBE, 0x93, 0xFF, 0x00, 0x82, 0xA8, 0xFF, 0x00, 0xC9, 0xCC, 0xDB, 0xFF, 0x00,
+	0xD8, 0xB1, 0x6B, 0xFF, 0x00, 0xA1, 0xCB, 0x5F, 0x36, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0xDB,
+	0xF0, 0xAF, 0xBA, 0x3F, 0xE0, 0x90, 0x1F, 0xF2, 0x2E, 0x78, 0xFB, 0xFE, 0xC2, 0x16, 0x1F, 0xFA,
+	0x2E, 0x6A, 0xF8, 0x5F, 0xB7, 0xE1, 0x5F, 0x74, 0x7F, 0xC1, 0x20, 0x3F, 0xE4, 0x5C, 0xF1, 0xF7,
+	0xFD, 0x84, 0x2C, 0x3F, 0xF4, 0x5C, 0xD4, 0x01, 0xE5, 0x5F, 0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B,
+	0x7F, 0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0xFA, 0x4F, 0xFE, 0x0A, 0xA3, 0xFF,
+	0x00, 0x27, 0x33, 0x6F, 0xFF, 0x00, 0x62, 0xC5, 0xAF, 0xFE, 0x87, 0x2D, 0x7C, 0xD9, 0x40, 0x05,
+	0x14, 0x51, 0x40, 0x07, 0x6F, 0xC2, 0xBE, 0xE4, 0xFF, 0x00, 0x82, 0x43, 0x7F, 0xC8, 0xB7, 0xE3,
+	0xDF, 0xFB, 0x08, 0x58, 0xFF, 0x00, 0xE8, 0xB9, 0xAB, 0xE1, 0xBE, 0xDF, 0x85, 0x7D, 0xC9, 0xFF,
+	0x00, 0x04, 0x86, 0xFF, 0x00, 0x91, 0x6F, 0xC7, 0xBF, 0xF6, 0x10, 0xB1, 0xFF, 0x00, 0xD1, 0x73,
+	0x54, 0xCB, 0xE1, 0x03, 0xEC, 0xE8, 0x3F, 0xD5, 0x2D, 0x3A, 0x9B, 0x07, 0xFA, 0xA1, 0x4E, 0xAA,
+	0x00, 0xA1, 0xBA, 0x74, 0xA2, 0x86, 0xFB, 0xB4, 0x01, 0xF1, 0x0F, 0xFC, 0x15, 0x9B, 0xC3, 0x1E,
+	0x24, 0xF1, 0x27, 0x88, 0xFC, 0x14, 0xDE, 0x1F, 0xF0, 0xF6, 0xA1, 0x7E, 0xD0, 0xD9, 0x5E, 0xEF,
+	0x5B, 0x2B, 0x37, 0x93, 0x68, 0x2F, 0x0F, 0x52, 0x33, 0x5F, 0x21, 0xFF, 0x00, 0xC2, 0xB3, 0xF8,
+	0x8F, 0xFF, 0x00, 0x44, 0xEB, 0x5C, 0xFF, 0x00, 0xC1, 0x5C, 0xBF, 0xFC, 0x45, 0x7E, 0xC5, 0x40,
+	0x73, 0xAE, 0xDC, 0x1F, 0xFA, 0x73, 0x83, 0xFF, 0x00, 0x42, 0x96, 0xAE, 0x50, 0x07, 0xE3, 0x4F,
+	0xFC, 0x2B, 0x3F, 0x88, 0xFF, 0x00, 0xF4, 0x4E, 0xB5, 0xCF, 0xFC, 0x15, 0xCB, 0xFF, 0x00, 0xC4,
+	0x51, 0xFF, 0x00, 0x0A, 0xCF, 0xE2, 0x3F, 0xFD, 0x13, 0xAD, 0x73, 0xFF, 0x00, 0x05, 0x72, 0xFF,
+	0x00, 0xF1, 0x15, 0xFB, 0x2D, 0x45, 0x00, 0x7E, 0x34, 0xFF, 0x00, 0xC2, 0xB3, 0xF8, 0x8F, 0xFF,
+	0x00, 0x44, 0xF3, 0x5C, 0x5F, 0xF6, 0x8E, 0x97, 0x2F, 0x1F, 0xF8, 0xE5, 0x7D, 0x47, 0xFF, 0x00,
+	0x04, 0xA9, 0xF0, 0xA7, 0x89, 0xBC, 0x3B, 0xF1, 0x87, 0xC4, 0x17, 0x7E, 0x20, 0xF0, 0xAE, 0xA5,
+	0x62, 0xAF, 0xE1, 0xD2, 0xA9, 0x25, 0xF5, 0x9B, 0xC6, 0xAF, 0xFB, 0xF8, 0xB8, 0x19, 0xAF, 0xBC,
+	0xE8, 0x34, 0x01, 0xF3, 0x0F, 0xFC, 0x15, 0x47, 0x41, 0xD6, 0xBC, 0x41, 0xF0, 0x0F, 0x43, 0xB3,
+	0xD0, 0xF4, 0x9B, 0xAB, 0xEB, 0x85, 0xF1, 0x6C, 0x2D, 0xE4, 0x59, 0x5B, 0x99, 0x1F, 0x1F, 0x65,
+	0xB9, 0xEC, 0x2B, 0xE0, 0x7F, 0xF8, 0x56, 0x7F, 0x11, 0xFF, 0x00, 0xE8, 0x9D, 0x6B, 0x9F, 0xF8,
+	0x2B, 0x97, 0xFF, 0x00, 0x88, 0xAF, 0xD9, 0x40, 0xD1, 0xF9, 0xBD, 0x36, 0xB1, 0x5F, 0xBA, 0x4F,
+	0x6F, 0x5C, 0x53, 0xA9, 0x25, 0x61, 0xB9, 0x37, 0xB9, 0xF8, 0xD3, 0xFF, 0x00, 0x0A, 0xCF, 0xE2,
+	0x3F, 0xFD, 0x13, 0xAD, 0x73, 0xFF, 0x00, 0x05, 0x72, 0xFF, 0x00, 0xF1, 0x14, 0x7F, 0xC2, 0xB3,
+	0xF8, 0x8F, 0xFF, 0x00, 0x44, 0xEB, 0x5C, 0xFF, 0x00, 0xC1, 0x5C, 0xBF, 0xFC, 0x45, 0x7E, 0xCB,
+	0x51, 0x4C, 0x47, 0xE3, 0x4F, 0xFC, 0x2B, 0x3F, 0x88, 0xFF, 0x00, 0xF4, 0x4E, 0xB5, 0xCF, 0xFC,
+	0x15, 0xCB, 0xFF, 0x00, 0xC4, 0x57, 0xB8, 0x7F, 0xC1, 0x3A, 0xFC, 0x15, 0xE2, 0xFD, 0x13, 0xF6,
+	0xA8, 0xD1, 0x75, 0x2D, 0x73, 0xC2, 0x1A, 0xAD, 0xA4, 0x29, 0x6B, 0x79, 0xFE, 0x95, 0x75, 0xA7,
+	0xBA, 0x47, 0xFF, 0x00, 0x1E, 0xEF, 0x5F, 0xA4, 0xD4, 0x50, 0x07, 0x89, 0xFF, 0x00, 0xC1, 0x41,
+	0xB4, 0xBB, 0xFD, 0x6B, 0xF6, 0x4A, 0xF1, 0x46, 0x9D, 0xA6, 0xD9, 0x4D, 0x71, 0x3C, 0x92, 0xD8,
+	0xF9, 0x76, 0xF6, 0xF1, 0x97, 0x73, 0xFE, 0x9D, 0x07, 0x40, 0x3A, 0xD7, 0xE6, 0xA8, 0xF8, 0x67,
+	0xF1, 0x27, 0x1F, 0x37, 0xC3, 0x9D, 0x78, 0x1E, 0xFB, 0xB4, 0xB9, 0x33, 0xFF, 0x00, 0xA0, 0x57,
+	0xEC, 0xA1, 0x31, 0xEF, 0x5C, 0xF0, 0xDD, 0x17, 0xB6, 0x78, 0xF4, 0xA7, 0x52, 0x4B, 0x94, 0x6E,
+	0x4D, 0x9F, 0x8D, 0x3F, 0xF0, 0xAC, 0xFE, 0x23, 0xFF, 0x00, 0xD1, 0x3A, 0xD7, 0x3F, 0xF0, 0x57,
+	0x2F, 0xFF, 0x00, 0x11, 0x47, 0xFC, 0x2B, 0x3F, 0x88, 0xFF, 0x00, 0xF4, 0x4E, 0xB5, 0xCF, 0xFC,
+	0x15, 0xCB, 0xFF, 0x00, 0xC4, 0x57, 0xEC, 0xB5, 0x14, 0xC4, 0x7E, 0x34, 0xFF, 0x00, 0xC2, 0xB3,
+	0xF8, 0x8F, 0xFF, 0x00, 0x44, 0xEB, 0x5C, 0xFF, 0x00, 0xC1, 0x5C, 0xBF, 0xFC, 0x45, 0x77, 0xDF,
+	0xB2, 0xC7, 0xC3, 0xFF, 0x00, 0x1C, 0xD8, 0x7E, 0xD1, 0xDE, 0x0B, 0xBD, 0xD5, 0x3C, 0x0D, 0xAC,
+	0x43, 0x04, 0x5E, 0x23, 0xB5, 0x2D, 0x71, 0x2E, 0x9A, 0xEB, 0x1A, 0x7E, 0xF0, 0x75, 0x35, 0xFA,
+	0xB1, 0x45, 0x00, 0x79, 0xFF, 0x00, 0xED, 0x44, 0xAF, 0x71, 0xFB, 0x35, 0x7C, 0x41, 0x58, 0xD5,
+	0x98, 0xB7, 0x83, 0x35, 0x3D, 0xAA, 0xBD, 0x5B, 0xFD, 0x16, 0x4A, 0xFC, 0x73, 0x5D, 0x2B, 0x53,
+	0x55, 0x0A, 0x74, 0xBB, 0x8E, 0x06, 0x39, 0x8E, 0xBF, 0x71, 0xEE, 0xA5, 0xB6, 0x86, 0x16, 0x96,
+	0xE5, 0x95, 0x11, 0x79, 0x67, 0x66, 0xDA, 0x3F, 0x3A, 0xCE, 0x1E, 0x25, 0xF0, 0x97, 0x05, 0x75,
+	0xCB, 0x1F, 0x9B, 0xFE, 0x9B, 0xA5, 0x7C, 0xF6, 0x71, 0x92, 0x53, 0xCC, 0xAA, 0x42, 0x53, 0xA9,
+	0xCB, 0xCA, 0x9A, 0xDA, 0xF7, 0xFC, 0x51, 0xFA, 0x47, 0x03, 0x71, 0xE6, 0x2B, 0x84, 0x70, 0xD5,
+	0xA9, 0x52, 0xC3, 0x7B, 0x5E, 0x76, 0x9D, 0xF9, 0x9A, 0xB5, 0x95, 0xAD, 0xF0, 0xB3, 0xF1, 0x27,
+	0xFB, 0x33, 0x52, 0xFF, 0x00, 0xA0, 0x65, 0xC7, 0xFD, 0xFB, 0xA3, 0xFB, 0x33, 0x52, 0xFF, 0x00,
+	0xA0, 0x65, 0xC7, 0xFD, 0xFB, 0xAF, 0xDB, 0x63, 0xE2, 0x3F, 0x09, 0x7F, 0xD0, 0x76, 0xC7, 0xFE,
+	0xFF, 0x00, 0x47, 0x47, 0xFC, 0x24, 0x7E, 0x12, 0xFF, 0x00, 0xA0, 0xED, 0x8F, 0xFD, 0xFE, 0x8E,
+	0xBC, 0x5F, 0xF5, 0x3F, 0x0F, 0xFF, 0x00, 0x3F, 0xFF, 0x00, 0x0F, 0xF8, 0x27, 0xDD, 0xFF, 0x00,
+	0xC4, 0x6C, 0xCC, 0x3F, 0xE8, 0x5D, 0xFF, 0x00, 0x93, 0x3F, 0xFE, 0x40, 0xFC, 0x49, 0xFE, 0xCC,
+	0xD4, 0xBF, 0xE8, 0x19, 0x71, 0xFF, 0x00, 0x7E, 0xEB, 0xE8, 0x6F, 0xF8, 0x26, 0x16, 0x99, 0x7F,
+	0x0F, 0xED, 0x69, 0xA5, 0xDC, 0xDC, 0x59, 0x5C, 0x24, 0x6B, 0xA4, 0xDE, 0xFF, 0x00, 0xAC, 0x8F,
+	0x8F, 0xF5, 0x46, 0xBF, 0x4C, 0x0F, 0x88, 0xFC, 0x26, 0x38, 0x1A, 0xE5, 0x8F, 0xFE, 0x04, 0x47,
+	0x52, 0x59, 0x6B, 0x1E, 0x1E, 0xBE, 0x97, 0xC9, 0xD3, 0xF5, 0x2B, 0x59, 0x1C, 0x72, 0x44, 0x72,
+	0x06, 0xFE, 0x55, 0xD3, 0x83, 0xE1, 0x9A, 0x38, 0x5C, 0x4C, 0x2A, 0xAA, 0xD7, 0x69, 0xA7, 0x6B,
+	0x6F, 0x6F, 0x99, 0xE5, 0x67, 0xBE, 0x2D, 0x63, 0xB3, 0x8C, 0x9E, 0xB6, 0x0A, 0x58, 0x1E, 0x55,
+	0x52, 0x2E, 0x37, 0xE6, 0x6E, 0xD7, 0xEB, 0x6E, 0x45, 0xF9, 0x9E, 0x37, 0xFF, 0x00, 0x05, 0x16,
+	0xD2, 0x35, 0x5D, 0x6B, 0xF6, 0x52, 0xD7, 0xB4, 0xDD, 0x17, 0x4E, 0x9A, 0xEA, 0xE2, 0x4B, 0xAB,
+	0x13, 0xE4, 0xDA, 0xDB, 0xB3, 0x31, 0x51, 0x72, 0x9E, 0x95, 0xF9, 0xBF, 0xFF, 0x00, 0x0A, 0xDB,
+	0xE2, 0x3B, 0xFC, 0xFF, 0x00, 0xF0, 0xAE, 0x75, 0xDF, 0x9B, 0x9F, 0xF9, 0x05, 0xCB, 0xFF, 0x00,
+	0xC4, 0x57, 0xEC, 0xB0, 0xE9, 0xD2, 0x8A, 0xFB, 0x23, 0xF1, 0x13, 0xF1, 0xA7, 0xFE, 0x15, 0x9F,
+	0xC4, 0x7F, 0xFA, 0x27, 0x5A, 0xE7, 0xFE, 0x0A, 0xE5, 0xFF, 0x00, 0xE2, 0x28, 0xFF, 0x00, 0x85,
+	0x67, 0xF1, 0x1F, 0xFE, 0x89, 0xD6, 0xB9, 0xFF, 0x00, 0x82, 0xB9, 0x7F, 0xF8, 0x8A, 0xFD, 0x96,
+	0xA2, 0x80, 0x3F, 0x11, 0x7E, 0x30, 0xFE, 0xCD, 0x5E, 0x31, 0xF8, 0xC3, 0xF0, 0xB7, 0x5F, 0xF8,
+	0x63, 0xAF, 0xFC, 0x3F, 0xD7, 0x16, 0xD7, 0x5A, 0xD2, 0xE5, 0xB5, 0x69, 0xBF, 0xB2, 0xE5, 0xFD,
+	0xDB, 0x32, 0xE5, 0x26, 0xFF, 0x00, 0xB6, 0x6C, 0x01, 0xFF, 0x00, 0x80, 0x57, 0xE1, 0xFF, 0x00,
+	0x8C, 0x3C, 0x2F, 0xE2, 0x1F, 0x04, 0x78, 0xA3, 0x50, 0xF0, 0x5F, 0x8B, 0x74, 0xE9, 0x2C, 0xF5,
+	0x6D, 0x1E, 0xFA, 0x6B, 0x2D, 0x52, 0xD2, 0x55, 0x2A, 0xD0, 0x5C, 0x44, 0xE6, 0x39, 0x10, 0x83,
+	0xD0, 0x87, 0x52, 0x08, 0xF6, 0xAF, 0xED, 0xEA, 0xBF, 0x9B, 0xFF, 0x00, 0xF8, 0x3A, 0x9F, 0xF6,
+	0x21, 0x97, 0xE0, 0x27, 0xED, 0xA9, 0x63, 0xFB, 0x57, 0xF8, 0x53, 0x47, 0xDB, 0xE1, 0xBF, 0x8B,
+	0x56, 0xFF, 0x00, 0x68, 0xBE, 0xFB, 0x32, 0x6C, 0xF2, 0x75, 0xAB, 0x38, 0xE3, 0x8A, 0x70, 0x5B,
+	0xF8, 0x4C, 0xA9, 0xF6, 0x79, 0x14, 0xFF, 0x00, 0x13, 0x99, 0xAB, 0x1A, 0x91, 0xEA, 0x75, 0x61,
+	0x67, 0xCB, 0x2E, 0x57, 0xD4, 0xFC, 0xB3, 0xA2, 0x82, 0xA5, 0x0E, 0xC3, 0xB7, 0xE5, 0xE3, 0xE5,
+	0x18, 0x1F, 0x85, 0x15, 0x89, 0xDC, 0x14, 0x51, 0x45, 0x00, 0x14, 0x2F, 0x53, 0xF8, 0x7F, 0x23,
+	0x45, 0x05, 0xE3, 0x03, 0x12, 0xB7, 0xF1, 0x00, 0xDD, 0xB6, 0xA1, 0x1C, 0x9C, 0xFF, 0x00, 0x10,
+	0xC0, 0xE5, 0x68, 0x03, 0xFA, 0x18, 0xFF, 0x00, 0x83, 0xC1, 0x3F, 0xE4, 0xC8, 0x3E, 0x18, 0xFF,
+	0x00, 0xD9, 0x58, 0x4F, 0xFD, 0x36, 0x5F, 0xD3, 0xFF, 0x00, 0xE0, 0x89, 0x5F, 0xF2, 0xAD, 0xE7,
+	0xC4, 0xCF, 0xFB, 0x00, 0x78, 0xEF, 0xFF, 0x00, 0x48, 0xA6, 0xAF, 0xC8, 0xCF, 0xDB, 0xB3, 0xFE,
+	0x0B, 0x1F, 0xFB, 0x6B, 0x7F, 0xC1, 0x46, 0xBE, 0x1E, 0xE8, 0x9F, 0x0B, 0xBF, 0x69, 0x6D, 0x77,
+	0xC3, 0xB7, 0x1A, 0x4E, 0x87, 0xAF, 0x26, 0xA9, 0xA7, 0x47, 0xA2, 0xE8, 0x69, 0x6B, 0x28, 0xBA,
+	0x11, 0x3A, 0x60, 0xBF, 0x71, 0xB5, 0xDF, 0x8A, 0x3F, 0x67, 0x6F, 0xF8, 0x2C, 0x57, 0xED, 0x99,
+	0xFB, 0x2F, 0xFE, 0xC9, 0x3A, 0xB7, 0xEC, 0x4F, 0xF0, 0xC3, 0x5C, 0xF0, 0xEC, 0x3E, 0x07, 0xD7,
+	0x2D, 0xF5, 0x1B, 0x7D, 0x42, 0xDE, 0xFB, 0x41, 0x49, 0xAE, 0x1A, 0x1B, 0xE8, 0x9A, 0x2B, 0x8D,
+	0xB2, 0xFF, 0x00, 0x07, 0xCA, 0xC3, 0xE9, 0x5A, 0x73, 0x47, 0x9A, 0xE7, 0x3F, 0xB1, 0xA8, 0xE9,
+	0x72, 0xF9, 0xDC, 0xFA, 0xB3, 0xFE, 0x0D, 0x05, 0xFF, 0x00, 0x94, 0x93, 0xF8, 0xDB, 0xFE, 0xC8,
+	0x7E, 0xA5, 0xFF, 0x00, 0xA7, 0x8D, 0x16, 0xBC, 0xB3, 0xFE, 0x0A, 0xC9, 0xFF, 0x00, 0x2B, 0x0C,
+	0x78, 0xAF, 0xFE, 0xCA, 0xAF, 0x86, 0xBF, 0xF4, 0x9F, 0x4F, 0xAF, 0x9A, 0x3F, 0x61, 0x7F, 0xDB,
+	0xDF, 0xF6, 0x86, 0xFF, 0x00, 0x82, 0x75, 0x7C, 0x5D, 0xD4, 0xBE, 0x36, 0x7E, 0xCD, 0xDA, 0xA6,
+	0x93, 0x6B, 0xAF, 0x6A, 0x9E, 0x1B, 0x9B, 0x45, 0xBC, 0x97, 0x58, 0xD3, 0x23, 0xBA, 0x84, 0xD9,
+	0x4B, 0x71, 0x6F, 0x70, 0xE0, 0x47, 0xD8, 0xEF, 0xB5, 0x4F, 0x9A, 0xB1, 0x7E, 0x39, 0xFE, 0xD7,
+	0xBF, 0x19, 0xBF, 0x68, 0x2F, 0xDA, 0xA2, 0xF7, 0xF6, 0xC7, 0xF8, 0x8F, 0x79, 0xA6, 0xC9, 0xE3,
+	0x4B, 0xED, 0x6A, 0xD3, 0x56, 0xBA, 0xB8, 0xB3, 0xB3, 0x10, 0xC0, 0xB7, 0x36, 0xC9, 0x12, 0xC1,
+	0xB6, 0x21, 0xDB, 0xF7, 0x49, 0x9F, 0xEF, 0x52, 0xE6, 0x8F, 0x2D, 0x87, 0xEC, 0xE5, 0xED, 0x1B,
+	0xEE, 0x7E, 0xC8, 0x7F, 0xC1, 0xE4, 0xBF, 0xF2, 0x4D, 0x7E, 0x02, 0xFF, 0x00, 0xD8, 0x7B, 0xC4,
+	0x1F, 0xFA, 0x4D, 0x63, 0x5D, 0xDF, 0xFC, 0x13, 0x2B, 0xFE, 0x55, 0x51, 0xF8, 0x8F, 0xFF, 0x00,
+	0x64, 0xA3, 0xE2, 0x57, 0xFE, 0x8B, 0xD5, 0x2B, 0xF1, 0xEF, 0xF6, 0xF8, 0xFF, 0x00, 0x82, 0xB2,
+	0x7E, 0xD7, 0x7F, 0xF0, 0x52, 0x6D, 0x23, 0xC3, 0x3A, 0x2F, 0xED, 0x3B, 0xAB, 0xE8, 0x37, 0x96,
+	0xFE, 0x11, 0xBA, 0xB8, 0xB8, 0xD2, 0x5B, 0x49, 0xD0, 0xD2, 0xCB, 0x6B, 0xCD, 0xB0, 0x49, 0x90,
+	0x7A, 0xF0, 0x91, 0xD6, 0x8F, 0xC2, 0x0F, 0xF8, 0x2C, 0x5F, 0xED, 0x9F, 0xF0, 0x47, 0xF6, 0x29,
+	0xD5, 0x7F, 0x60, 0x2F, 0x03, 0x6B, 0xFE, 0x1D, 0x4F, 0x87, 0xBA, 0xD6, 0x83, 0xAB, 0xE9, 0x37,
+	0x90, 0x5D, 0xE8, 0x09, 0x2D, 0xC1, 0xB7, 0xD4, 0xD6, 0x71, 0x73, 0xB6, 0x6F, 0xE1, 0x38, 0x9A,
+	0x4A, 0x7C, 0xCB, 0x98, 0x9F, 0x67, 0x2F, 0x67, 0x6F, 0x33, 0xEC, 0x6F, 0xF8, 0x33, 0xF3, 0xFE,
+	0x4F, 0x8B, 0xE2, 0x77, 0xFD, 0x92, 0xBF, 0xFD, 0xCA, 0x59, 0xD7, 0x88, 0x7E, 0xDA, 0x3F, 0xF2,
+	0xB2, 0x36, 0xA9, 0xFF, 0x00, 0x67, 0x19, 0xA1, 0xFF, 0x00, 0xE9, 0x75, 0x9D, 0x7C, 0xE9, 0xFB,
+	0x08, 0xFF, 0x00, 0xC1, 0x42, 0xFF, 0x00, 0x69, 0x2F, 0xF8, 0x27, 0x27, 0xC4, 0x4D, 0x73, 0xE2,
+	0x87, 0xEC, 0xD5, 0xA9, 0x68, 0xF6, 0xBA, 0xC6, 0xBD, 0xA4, 0x7F, 0x65, 0xEA, 0x4D, 0xAC, 0x69,
+	0x29, 0x77, 0x17, 0xD9, 0xCC, 0x91, 0x49, 0xC2, 0xFA, 0xEE, 0x8E, 0x3F, 0x9B, 0xBD, 0x73, 0x9E,
+	0x3F, 0xFD, 0xAF, 0x7E, 0x32, 0xFC, 0x4A, 0xFD, 0xAD, 0xE4, 0xFD, 0xB6, 0x3C, 0x59, 0x7D, 0xA6,
+	0xC9, 0xE3, 0x89, 0xBC, 0x59, 0x6B, 0xE2, 0x26, 0xB8, 0x87, 0x4F, 0xDB, 0x6C, 0x2F, 0xA0, 0x99,
+	0x27, 0x53, 0xE5, 0x7A, 0x66, 0x25, 0xE3, 0xD2, 0xA7, 0xEC, 0xA4, 0xBA, 0x0F, 0xD9, 0xCB, 0xDA,
+	0x37, 0xDC, 0xFD, 0x74, 0xFF, 0x00, 0x83, 0xCD, 0x4F, 0xCD, 0xFB, 0x37, 0xFF, 0x00, 0xBB, 0xE3,
+	0x0F, 0xE7, 0xA2, 0x57, 0xAA, 0x7C, 0x3D, 0xFF, 0x00, 0x95, 0x45, 0xEE, 0x3F, 0xEC, 0x94, 0xEA,
+	0x9F, 0xFA, 0x78, 0x9E, 0xBF, 0x1C, 0xFF, 0x00, 0x6F, 0xCF, 0xF8, 0x2A, 0x57, 0xED, 0x61, 0xFF,
+	0x00, 0x05, 0x2C, 0x4F, 0x08, 0x7F, 0xC3, 0x52, 0xEA, 0xFA, 0x0D, 0xD7, 0xFC, 0x21, 0x66, 0xFB,
+	0xFB, 0x0F, 0xFB, 0x27, 0x45, 0xFB, 0x22, 0xAA, 0xDE, 0x0B, 0x6F, 0x3C, 0x4B, 0xFD, 0xEE, 0x6D,
+	0x13, 0x06, 0xB6, 0xF4, 0xAF, 0xF8, 0x2C, 0x5F, 0xED, 0xA1, 0xA3, 0x7E, 0xC3, 0x7F, 0xF0, 0xEF,
+	0x0B, 0x3D, 0x73, 0xC3, 0xCB, 0xF0, 0xE5, 0xB4, 0x39, 0xB4, 0xAF, 0xB3, 0xCB, 0xE1, 0xE4, 0x6B,
+	0xB3, 0x6F, 0x25, 0xC9, 0xB9, 0x90, 0x19, 0xFB, 0x36, 0xE6, 0xE4, 0xFA, 0xD5, 0xF3, 0x89, 0x51,
+	0x9F, 0x2A, 0x5D, 0x8F, 0xB8, 0xBF, 0xE0, 0xCE, 0xAF, 0xF9, 0x39, 0x3F, 0x8C, 0x9F, 0xF6, 0x22,
+	0xD8, 0xFF, 0x00, 0xE9, 0x6B, 0x57, 0xCA, 0xF2, 0xFF, 0x00, 0xCA, 0xC9, 0xBF, 0xF7, 0x7C, 0x8B,
+	0xFF, 0x00, 0xA9, 0x88, 0xAF, 0x1A, 0xFD, 0x81, 0xBF, 0xE0, 0xA4, 0x3F, 0xB4, 0xBF, 0xFC, 0x13,
+	0x77, 0xC5, 0xBA, 0xEF, 0x8D, 0x3F, 0x66, 0x7D, 0x43, 0x45, 0xB5, 0xBC, 0xF1, 0x16, 0x9D, 0x15,
+	0x86, 0xA8, 0xDA, 0xCE, 0x96, 0x97, 0x8B, 0xF6, 0x78, 0xE4, 0x32, 0x9C, 0x7A, 0x9C, 0x9E, 0xB5,
+	0xC4, 0xB7, 0xED, 0x53, 0xF1, 0x61, 0x7F, 0x6B, 0x81, 0xFB, 0x6D, 0xC9, 0x7B, 0x68, 0x7C, 0x72,
+	0xBF, 0x12, 0x07, 0x8D, 0x9A, 0xE3, 0xFB, 0x37, 0xFD, 0x1C, 0xEA, 0x9F, 0x6E, 0x6D, 0x41, 0x8F,
+	0x93, 0xD9, 0x3C, 0xEE, 0x8B, 0xD8, 0x71, 0x51, 0xF6, 0x52, 0x5D, 0x0B, 0xF6, 0x72, 0xE6, 0x6D,
+	0x75, 0x3F, 0x58, 0xFF, 0x00, 0xE0, 0xF2, 0x3F, 0xF9, 0x29, 0x1F, 0x00, 0xFF, 0x00, 0xEC, 0x01,
+	0xAF, 0x7F, 0xE9, 0x4E, 0x9F, 0x5E, 0xDF, 0xF1, 0x17, 0xFE, 0x55, 0x13, 0x87, 0xFE, 0xC9, 0x56,
+	0x99, 0xFF, 0x00, 0xA7, 0x88, 0x2B, 0xF1, 0xAB, 0xF6, 0xFE, 0xFF, 0x00, 0x82, 0x9C, 0xFE, 0xD4,
+	0x9F, 0xF0, 0x52, 0x8D, 0x57, 0xC3, 0x3A, 0xE7, 0xED, 0x49, 0xAB, 0x68, 0x37, 0x73, 0xF8, 0x4E,
+	0xDA, 0xEE, 0x1D, 0x27, 0xFB, 0x17, 0x45, 0xFB, 0x18, 0x55, 0x9F, 0xCB, 0x32, 0x0F, 0xF6, 0xBE,
+	0x78, 0x97, 0x9A, 0xE9, 0xB5, 0x6F, 0xF8, 0x2C, 0x5F, 0xED, 0x9D, 0xAB, 0x7E, 0xC3, 0xAB, 0xFF,
+	0x00, 0x04, 0xEE, 0xD4, 0xB5, 0xCF, 0x0D, 0x7F, 0xC2, 0xB5, 0x8B, 0x47, 0xB7, 0xD2, 0xDE, 0x1F,
+	0xEC, 0x08, 0xC5, 0xD7, 0xD9, 0x61, 0xB8, 0x4B, 0x85, 0x1E, 0x69, 0xEA, 0xDE, 0x62, 0xF2, 0x7B,
+	0x9A, 0xAE, 0x6D, 0xEE, 0x4F, 0xB3, 0x93, 0x82, 0x8F, 0x63, 0xF4, 0x6F, 0xFE, 0x0C, 0xD0, 0xFF,
+	0x00, 0x59, 0xFB, 0x47, 0x7D, 0x3C, 0x1F, 0xFC, 0xF5, 0xEA, 0xF8, 0xEB, 0xF6, 0x2F, 0xFF, 0x00,
+	0x95, 0x91, 0x74, 0xDF, 0xFB, 0x39, 0x0D, 0x6F, 0xFF, 0x00, 0x4B, 0x2F, 0x6B, 0xC3, 0x3F, 0x60,
+	0x0F, 0xF8, 0x2A, 0x87, 0xED, 0x61, 0xFF, 0x00, 0x04, 0xD1, 0x87, 0xC5, 0x89, 0xFB, 0x2F, 0xEA,
+	0xFA, 0x1D, 0xA1, 0xF1, 0xA4, 0x76, 0x27, 0x5A, 0xFE, 0xDC, 0xD1, 0xD2, 0xF1, 0xCB, 0x5A, 0x0B,
+	0x9F, 0x27, 0x69, 0xEC, 0x33, 0x73, 0x25, 0x70, 0x5E, 0x02, 0xFD, 0xAF, 0x7E, 0x33, 0x7C, 0x2F,
+	0xFD, 0xAD, 0xD7, 0xF6, 0xD9, 0xF0, 0xBD, 0xEE, 0x9F, 0xFF, 0x00, 0x09, 0xCC, 0x5E, 0x2B, 0xBA,
+	0xF1, 0x22, 0xDC, 0x4F, 0x61, 0xBE, 0xD8, 0xDF, 0x4F, 0x23, 0xBB, 0x91, 0x0F, 0x65, 0xCB, 0x9C,
+	0x2F, 0x61, 0xC5, 0x1C, 0xDA, 0x24, 0x8A, 0xF6, 0x72, 0xBB, 0x6B, 0xA9, 0xFA, 0x43, 0xFF, 0x00,
+	0x07, 0x84, 0xFF, 0x00, 0xC9, 0xEE, 0xFC, 0x31, 0xFF, 0x00, 0xB2, 0x53, 0xFF, 0x00, 0xB9, 0x2B,
+	0xCA, 0xFA, 0xAB, 0xF6, 0xC9, 0x3F, 0xF1, 0xC8, 0xCE, 0x8B, 0xFF, 0x00, 0x64, 0xAF, 0xC0, 0x7F,
+	0xFA, 0x79, 0xD2, 0x6B, 0xF1, 0x63, 0xF6, 0xF0, 0xFF, 0x00, 0x82, 0x88, 0x7E, 0xD2, 0x3F, 0xF0,
+	0x51, 0xAF, 0x88, 0xDA, 0x2F, 0xC5, 0x6F, 0xDA, 0x63, 0x50, 0xD1, 0xEE, 0x35, 0x6D, 0x0F, 0x49,
+	0x5D, 0x2B, 0x4D, 0x6D, 0x17, 0x49, 0xFB, 0x14, 0x62, 0x15, 0x9A, 0x59, 0xFE, 0x65, 0xFE, 0x2F,
+	0x9E, 0x53, 0x5D, 0xA7, 0x8E, 0xBF, 0xE0, 0xB1, 0xDF, 0xB6, 0x8F, 0xC4, 0x7F, 0xD8, 0x5E, 0xDF,
+	0xFE, 0x09, 0xDB, 0xE2, 0x6D, 0x7F, 0xC3, 0x32, 0x7C, 0x37, 0xB7, 0xD1, 0x74, 0xDD, 0x26, 0x1B,
+	0x78, 0x7C, 0x3E, 0x89, 0x74, 0x2D, 0x6C, 0x66, 0xB7, 0x9E, 0xDC, 0x79, 0xBD, 0xDB, 0x7D, 0xBA,
+	0x7C, 0xDD, 0xE8, 0xE6, 0xD5, 0xDC, 0x98, 0xD2, 0x93, 0x8A, 0x8F, 0x63, 0xF4, 0xE3, 0xFE, 0x0C,
+	0xD8, 0xFF, 0x00, 0x92, 0x69, 0xF1, 0xEB, 0xFE, 0xC3, 0x5E, 0x1F, 0xFF, 0x00, 0xD1, 0x17, 0xB5,
+	0xF0, 0xFF, 0x00, 0xFC, 0x12, 0x63, 0xFE, 0x56, 0x18, 0xF0, 0x9F, 0xFD, 0x95, 0x6F, 0x11, 0xFF,
+	0x00, 0xE9, 0x3E, 0xA9, 0x5E, 0x2B, 0xFB, 0x03, 0x7F, 0xC1, 0x59, 0x3F, 0x6B, 0x8F, 0xF8, 0x26,
+	0xC6, 0x8B, 0xE2, 0x5D, 0x1F, 0xF6, 0x61, 0xD5, 0x74, 0x2B, 0x7B, 0x7F, 0x16, 0x5D, 0x5A, 0x4B,
+	0xAD, 0x26, 0xB7, 0xA2, 0xC5, 0x77, 0x27, 0x99, 0x6E, 0xB2, 0x88, 0xB0, 0xDF, 0x49, 0x4D, 0x79,
+	0xCF, 0xC1, 0x0F, 0xDA, 0xEB, 0xE3, 0x0F, 0xEC, 0xF5, 0xFB, 0x54, 0xD9, 0x7E, 0xD8, 0x9F, 0x0D,
+	0xEF, 0xF4, 0xD8, 0xFC, 0x6D, 0x63, 0xAD, 0x5E, 0x6A, 0x76, 0xF3, 0xDC, 0x69, 0xA2, 0x4B, 0x73,
+	0x3D, 0xCC, 0x72, 0x2B, 0x91, 0x10, 0xE8, 0xBF, 0xBC, 0x93, 0x03, 0xB0, 0xE2, 0xA7, 0xDA, 0x47,
+	0x64, 0x52, 0xA7, 0x25, 0x29, 0x3E, 0xE7, 0xE8, 0x27, 0xFC, 0x1D, 0xF3, 0xFF, 0x00, 0x29, 0x29,
+	0xF0, 0x3F, 0xFD, 0x91, 0x1D, 0x2F, 0xFF, 0x00, 0x4F, 0x3A, 0xBD, 0x7D, 0x8B, 0xFF, 0x00, 0x05,
+	0xB1, 0xFF, 0x00, 0x95, 0x6F, 0xFE, 0x19, 0x7F, 0xD8, 0x1B, 0xC0, 0x7F, 0xFA, 0x45, 0x0D, 0x7E,
+	0x27, 0xFE, 0xDD, 0xFF, 0x00, 0xB7, 0xEF, 0xED, 0x0B, 0xFF, 0x00, 0x05, 0x16, 0xF8, 0xB9, 0xA7,
+	0xFC, 0x6C, 0xFD, 0xA5, 0x75, 0x2D, 0x1E, 0xEB, 0x5C, 0xD2, 0xFC, 0x33, 0x1E, 0x8B, 0x6F, 0x26,
+	0x91, 0xA4, 0xFD, 0x92, 0x3F, 0xB0, 0xC7, 0x3D, 0xCC, 0xEB, 0x95, 0xFF, 0x00, 0xAE, 0x97, 0x2F,
+	0x5E, 0x87, 0xFB, 0x44, 0xFF, 0x00, 0xC1, 0x62, 0xBF, 0x6D, 0x3F, 0xDA, 0x7B, 0xF6, 0x4F, 0xD1,
+	0xFF, 0x00, 0x62, 0xCF, 0x8A, 0x9A, 0xCF, 0x87, 0xA6, 0xF0, 0x4E, 0x87, 0x6F, 0xA6, 0xC1, 0x63,
+	0x0D, 0x9E, 0x82, 0x91, 0x5C, 0xA7, 0xD8, 0x10, 0x24, 0x01, 0xA4, 0xFE, 0x2F, 0xDD, 0xAA, 0xFC,
+	0xDD, 0xFA, 0xD1, 0xCC, 0x89, 0x54, 0x65, 0xEE, 0xA7, 0xD0, 0xFD, 0x4F, 0xFF, 0x00, 0x83, 0x3A,
+	0x7F, 0xE4, 0xDA, 0xFE, 0x31, 0xFF, 0x00, 0xD8, 0xF1, 0xA7, 0x7F, 0xE9, 0x1D, 0x7E, 0x73, 0x7F,
+	0xC1, 0xB7, 0x3F, 0xF2, 0x9A, 0x2F, 0x82, 0xFF, 0x00, 0xEF, 0x78, 0x87, 0xFF, 0x00, 0x51, 0xCD,
+	0x4E, 0xBC, 0xEF, 0xF6, 0x07, 0xFF, 0x00, 0x82, 0xB9, 0x7E, 0xD8, 0x1F, 0xF0, 0x4D, 0xFF, 0x00,
+	0x08, 0xEB, 0xDE, 0x09, 0xFD, 0x9A, 0x75, 0x6D, 0x02, 0xDF, 0x4D, 0xF1, 0x36, 0xA9, 0x06, 0xA1,
+	0xAA, 0x43, 0xAB, 0x68, 0x49, 0x72, 0xEF, 0x22, 0x27, 0x90, 0xBB, 0x24, 0xFE, 0x03, 0x80, 0xDF,
+	0x4A, 0xF2, 0x8F, 0xD9, 0x2B, 0xF6, 0xA3, 0xF8, 0xB7, 0xFB, 0x16, 0x7E, 0xD0, 0x3E, 0x1F, 0xFD,
+	0xA5, 0xBE, 0x06, 0xDE, 0x69, 0xF0, 0xF8, 0xB3, 0xC3, 0x6B, 0x79, 0xFD, 0x93, 0x26, 0xA5, 0x63,
+	0xE7, 0x40, 0x1E, 0xE2, 0xD2, 0x6B, 0x39, 0x3C, 0xC8, 0xFB, 0x8F, 0x2A, 0xE1, 0xB6, 0xD0, 0xAA,
+	0x47, 0x95, 0x21, 0xFB, 0x29, 0x7B, 0xCF, 0xB9, 0xF7, 0x8F, 0xFC, 0x1D, 0x99, 0xFF, 0x00, 0x29,
+	0x42, 0xD3, 0xFF, 0x00, 0xEC, 0x95, 0xE9, 0x1F, 0xFA, 0x55, 0x7D, 0x5F, 0x71, 0xFF, 0x00, 0xC1,
+	0xC5, 0x9F, 0xF2, 0x82, 0x5F, 0x85, 0x7F, 0xF6, 0x30, 0x78, 0x43, 0xFF, 0x00, 0x4D, 0x73, 0xD7,
+	0xE2, 0x37, 0xED, 0xB9, 0xFB, 0x74, 0xFC, 0x7A, 0xFF, 0x00, 0x82, 0x83, 0xFC, 0x66, 0x83, 0xE3,
+	0xCF, 0xED, 0x0F, 0xA8, 0x69, 0x57, 0x1E, 0x20, 0xB7, 0xD1, 0xA0, 0xD3, 0x63, 0x9B, 0x4D, 0xD2,
+	0xBE, 0xCB, 0x18, 0xB6, 0x82, 0x59, 0x64, 0x5D, 0xC9, 0xDF, 0xFD, 0x7B, 0x57, 0xA2, 0x7E, 0xD5,
+	0xBF, 0xF0, 0x58, 0x7F, 0xDB, 0x43, 0xF6, 0xCA, 0xFD, 0x9A, 0x34, 0x9F, 0xD9, 0x3B, 0xE3, 0x96,
+	0xB9, 0xE1, 0xE9, 0xFC, 0x1F, 0xA0, 0xC9, 0x67, 0x2D, 0x8C, 0x7A, 0x6E, 0x82, 0x90, 0x5C, 0x06,
+	0xB5, 0x81, 0xED, 0xE2, 0x0F, 0x2F, 0xF1, 0x7E, 0xED, 0x9F, 0x3E, 0xB4, 0x73, 0x21, 0x7B, 0x19,
+	0x7B, 0xAB, 0xB1, 0xFA, 0xE9, 0xFF, 0x00, 0x06, 0xA9, 0xFF, 0x00, 0xCA, 0x23, 0xBE, 0x2C, 0x7F,
+	0xD9, 0x56, 0xD7, 0x3F, 0xF4, 0xC3, 0xA4, 0x57, 0xC0, 0x1F, 0xF0, 0x6A, 0xFF, 0x00, 0xFC, 0xA5,
+	0x93, 0x49, 0xFF, 0x00, 0xB1, 0x17, 0x5A, 0xFF, 0x00, 0xD1, 0x6B, 0x5E, 0x1D, 0xFB, 0x16, 0xFF,
+	0x00, 0xC1, 0x62, 0xBF, 0x6D, 0x4F, 0xD8, 0x0F, 0xE0, 0x7E, 0xB7, 0xFB, 0x3C, 0x7C, 0x01, 0xD6,
+	0xFC, 0x3B, 0x6F, 0xE1, 0xFF, 0x00, 0x10, 0x6B, 0xD7, 0x3A, 0xAE, 0xA7, 0x0E, 0xA1, 0xA0, 0xA5,
+	0xC4, 0xED, 0x71, 0x3D, 0xAD, 0xBD, 0xAB, 0xED, 0x93, 0xF8, 0x3F, 0x77, 0x6F, 0x1F, 0x1D, 0xAB,
+	0xCB, 0xBF, 0x63, 0x1F, 0xDB, 0x4B, 0xE3, 0x7F, 0xEC, 0x17, 0xF1, 0xC2, 0x1F, 0xDA, 0x0B, 0xF6,
+	0x7F, 0xBE, 0xD3, 0x6D, 0xFC, 0x45, 0x6F, 0xA7, 0x5C, 0x58, 0xA4, 0x9A, 0x86, 0x96, 0x97, 0x36,
+	0xE6, 0xDE, 0x65, 0x01, 0xCE, 0xDE, 0xC7, 0x75, 0x1C, 0xF1, 0xD0, 0xAF, 0x65, 0x27, 0x19, 0x79,
+	0x9F, 0x53, 0x7F, 0xC1, 0xCE, 0x27, 0xFE, 0x37, 0x0D, 0xE3, 0xFF, 0x00, 0xFB, 0x02, 0xE8, 0x5F,
+	0xFA, 0x6C, 0xB5, 0xAF, 0xBF, 0xFF, 0x00, 0xE0, 0xEB, 0x9F, 0xF9, 0x46, 0xCF, 0xC1, 0x1F, 0xFB,
+	0x1F, 0x2C, 0xBF, 0xF4, 0xCD, 0x79, 0x5F, 0x8A, 0x3F, 0xB6, 0x27, 0xED, 0x79, 0xF1, 0x97, 0xF6,
+	0xE9, 0xF8, 0xF5, 0xAB, 0x7E, 0xD1, 0x5F, 0x1E, 0xAF, 0x74, 0xEB, 0x8F, 0x12, 0xEB, 0x16, 0xB6,
+	0xB6, 0xD7, 0x93, 0x69, 0xBA, 0x6F, 0xD9, 0xE1, 0x51, 0x04, 0x71, 0xC7, 0x1E, 0x17, 0xF8, 0x7E,
+	0x48, 0xD3, 0x3E, 0xB5, 0xEA, 0x1F, 0xB6, 0xBF, 0xFC, 0x15, 0xF7, 0xF6, 0xC9, 0xFF, 0x00, 0x82,
+	0x80, 0xFC, 0x28, 0xF0, 0xDF, 0xC1, 0x7F, 0xDA, 0x13, 0x5C, 0xF0, 0xFD, 0xC6, 0x83, 0xE1, 0x8D,
+	0x5A, 0x1B, 0xED, 0x1A, 0x3D, 0x23, 0x44, 0x4B, 0x69, 0xC4, 0xF1, 0xC0, 0xD1, 0x00, 0xD2, 0x7F,
+	0x17, 0xC8, 0xCD, 0xC5, 0x1C, 0xCA, 0xCF, 0xCC, 0x5E, 0xCE, 0x5C, 0xD1, 0xF2, 0x3F, 0x5F, 0x3F,
+	0xE0, 0xDD, 0x0F, 0xF9, 0x41, 0x1F, 0xC5, 0x2F, 0xFB, 0x0E, 0x78, 0xAF, 0xFF, 0x00, 0x4D, 0x56,
+	0xD5, 0xF0, 0xC7, 0xFC, 0x1A, 0x61, 0xFF, 0x00, 0x29, 0x43, 0xBE, 0xFF, 0x00, 0xB2, 0x4F, 0xAB,
+	0x7F, 0xE9, 0x66, 0x9F, 0x5F, 0x39, 0xFE, 0xC9, 0xFF, 0x00, 0xF0, 0x58, 0xAF, 0xDB, 0x37, 0xF6,
+	0x30, 0xFD, 0x9B, 0x75, 0x7F, 0xD9, 0x43, 0xE0, 0x96, 0xBB, 0xE1, 0xD8, 0x3C, 0x27, 0xAF, 0x5D,
+	0x5E, 0x4B, 0x7D, 0x6F, 0x7D, 0xA0, 0xA4, 0xD7, 0x0D, 0x2D, 0xDD, 0xBC, 0x70, 0x49, 0xB6, 0x5F,
+	0xE0, 0xFD, 0xDC, 0x7F, 0x85, 0x79, 0xBF, 0xEC, 0x41, 0xFB, 0x72, 0xFC, 0x7B, 0xFF, 0x00, 0x82,
+	0x7C, 0xFC, 0x66, 0x7F, 0x8E, 0xDF, 0xB3, 0x96, 0xA5, 0xA5, 0xDB, 0x78, 0x82, 0x6D, 0x16, 0x6D,
+	0x2D, 0x9B, 0x58, 0xD3, 0x12, 0xEA, 0x1F, 0xB3, 0xCB, 0x22, 0x48, 0xFB, 0x63, 0xEC, 0x77, 0x2A,
+	0xFC, 0xD4, 0xFD, 0xA4, 0x74, 0xF2, 0x1F, 0xB3, 0x97, 0x2C, 0xBC, 0xCF, 0xA7, 0x7F, 0xE0, 0xBE,
+	0x27, 0xFE, 0x37, 0xD7, 0xF1, 0x1B, 0xFE, 0xC3, 0x9E, 0x12, 0xFF, 0x00, 0xD3, 0x16, 0x91, 0x5F,
+	0xA0, 0x5F, 0xF0, 0x78, 0xBF, 0xFC, 0x9B, 0x67, 0xC1, 0xBF, 0xFB, 0x1E, 0xAF, 0x7F, 0xF4, 0x8D,
+	0x6B, 0xF1, 0x3F, 0xF6, 0x98, 0xFD, 0xAE, 0xFE, 0x32, 0xFE, 0xD7, 0x3F, 0xB4, 0xDE, 0xA7, 0xFB,
+	0x58, 0xFC, 0x5A, 0xBA, 0xD3, 0x6E, 0xBC, 0x61, 0xAD, 0xDD, 0x58, 0xCB, 0x79, 0x36, 0x9B, 0x65,
+	0xE4, 0x5B, 0xBC, 0xB6, 0xB6, 0xB6, 0xF6, 0xD6, 0xFF, 0x00, 0xBB, 0xFF, 0x00, 0x66, 0x3B, 0x65,
+	0xC9, 0xFE, 0x2F, 0xC6, 0xBD, 0x43, 0xF6, 0xF6, 0xFF, 0x00, 0x82, 0xBD, 0xFE, 0xD9, 0x1F, 0xF0,
+	0x52, 0x2F, 0x08, 0x68, 0x1E, 0x0C, 0xFD, 0xA5, 0xF5, 0xBD, 0x06, 0xF2, 0xC7, 0xC3, 0x7A, 0x84,
+	0x97, 0xFA, 0x5F, 0xF6, 0x2F, 0x87, 0x52, 0xD5, 0xBC, 0xE7, 0x88, 0x27, 0xCC, 0x7D, 0x31, 0x4F,
+	0xDA, 0x2D, 0x45, 0xEC, 0xE5, 0xCD, 0x1F, 0x23, 0xF5, 0xEB, 0xFE, 0x09, 0x8F, 0xFF, 0x00, 0x2A,
+	0xA7, 0x7C, 0x46, 0xFF, 0x00, 0xB2, 0x4F, 0xF1, 0x2B, 0xFF, 0x00, 0x45, 0xEA, 0x75, 0xF1, 0xD7,
+	0xFC, 0x1A, 0x11, 0xFF, 0x00, 0x29, 0x28, 0xF1, 0xC7, 0xFD, 0x90, 0xFD, 0x4B, 0xFF, 0x00, 0x4F,
+	0x3A, 0x2D, 0x7C, 0xA9, 0xF0, 0x8B, 0xFE, 0x0B, 0x17, 0xFB, 0x67, 0xFC, 0x10, 0xFD, 0x8A, 0xF5,
+	0x6F, 0xD8, 0x07, 0xC0, 0xDA, 0xEF, 0x86, 0xE3, 0xF8, 0x7B, 0xAD, 0x68, 0x3A, 0xC6, 0x93, 0x79,
+	0x6F, 0x71, 0xA0, 0xA4, 0xB3, 0x9B, 0x7D, 0x49, 0x67, 0x17, 0x21, 0x66, 0xFE, 0x1E, 0x26, 0x92,
+	0xBC, 0xFF, 0x00, 0xF6, 0x17, 0xFD, 0xBD, 0xFF, 0x00, 0x68, 0x6F, 0xF8, 0x27, 0x4F, 0xC5, 0xDD,
+	0x4B, 0xE3, 0x67, 0xEC, 0xDD, 0xA9, 0xE9, 0x36, 0xBA, 0xF6, 0xA9, 0xE1, 0xB9, 0xB4, 0x5B, 0xC9,
+	0x75, 0xAD, 0x36, 0x2B, 0xB8, 0x4D, 0x94, 0xB7, 0x16, 0xF7, 0x0E, 0x02, 0x76, 0x3B, 0xED, 0x53,
+	0xE6, 0xEF, 0x47, 0x3C, 0x34, 0xF2, 0x17, 0xB1, 0x97, 0x24, 0x97, 0x73, 0xE9, 0x6F, 0xF8, 0x2B,
+	0x1F, 0xFC, 0xAC, 0x2F, 0xE2, 0xAF, 0xFB, 0x2A, 0x9E, 0x1A, 0xFF, 0x00, 0xD2, 0x7D, 0x3E, 0xBE,
+	0xE0, 0xFF, 0x00, 0x83, 0xC9, 0xBF, 0xE4, 0x9B, 0xFC, 0x05, 0xFF, 0x00, 0xB0, 0xEF, 0x88, 0x3F,
+	0xF4, 0x9A, 0xC6, 0xBF, 0x1B, 0xFE, 0x39, 0xFE, 0xD7, 0xBF, 0x19, 0xBF, 0x68, 0x2F, 0xDA, 0xA2,
+	0xF7, 0xF6, 0xC7, 0xF8, 0x8F, 0x79, 0xA6, 0xC9, 0xE3, 0x4B, 0xED, 0x6A, 0xD3, 0x56, 0xBA, 0xB8,
+	0xB3, 0xB3, 0x10, 0xC0, 0xB7, 0x36, 0xC9, 0x12, 0xC1, 0xB6, 0x21, 0xDB, 0xF7, 0x49, 0x9F, 0xEF,
+	0x57, 0xA4, 0x7E, 0xDF, 0x3F, 0xF0, 0x56, 0x4F, 0xDA, 0xF3, 0xFE, 0x0A, 0x4F, 0xA4, 0xF8, 0x67,
+	0x46, 0xFD, 0xA7, 0xB5, 0x7D, 0x06, 0xF2, 0xDF, 0xC2, 0x57, 0x57, 0x17, 0x1A, 0x4B, 0x69, 0x3A,
+	0x1A, 0x59, 0x6D, 0x79, 0xB6, 0x09, 0x32, 0x0F, 0x5E, 0x12, 0x3A, 0x9E, 0x6D, 0x5F, 0x98, 0x7B,
+	0x29, 0x7B, 0x48, 0xBE, 0xC7, 0xEC, 0x17, 0xEC, 0x70, 0x7F, 0xE3, 0x91, 0x4D, 0x6B, 0xFE, 0xC9,
+	0x3F, 0x8F, 0x3F, 0xF4, 0xF1, 0xAB, 0xD7, 0xCE, 0x3F, 0xF0, 0x67, 0x6F, 0xFC, 0x9C, 0xB7, 0xC6,
+	0x5F, 0xFB, 0x11, 0x6C, 0x7F, 0xF4, 0xB5, 0xAB, 0xE1, 0xAF, 0x00, 0x7F, 0xC1, 0x63, 0x3F, 0x6C,
+	0xCF, 0x86, 0xDF, 0xB0, 0xCC, 0xFF, 0x00, 0xF0, 0x4F, 0x0F, 0x0D, 0xF8, 0x83, 0xC3, 0x71, 0xFC,
+	0x35, 0xBA, 0xD0, 0xF5, 0x3D, 0x26, 0x5B, 0x79, 0xF4, 0x08, 0xE4, 0xBA, 0x6B, 0x6B, 0xFB, 0x89,
+	0x26, 0xB8, 0xC4, 0xDF, 0xC2, 0x77, 0xDC, 0xC9, 0x5C, 0xB7, 0xEC, 0x0F, 0xFF, 0x00, 0x05, 0x23,
+	0xFD, 0xA6, 0xBF, 0xE0, 0x9B, 0xDE, 0x2E, 0xD7, 0xBC, 0x6D, 0xFB, 0x35, 0x6A, 0x1A, 0x2D, 0xAD,
+	0xF7, 0x89, 0x34, 0xF8, 0xEC, 0x75, 0x66, 0xD6, 0xB4, 0xA4, 0xBB, 0x5F, 0xB3, 0xC7, 0x29, 0x94,
+	0xE3, 0xD4, 0xEE, 0x35, 0x5C, 0xDA, 0xA7, 0xD8, 0x3D, 0x8C, 0xB9, 0x25, 0xE6, 0xCF, 0x65, 0xFD,
+	0xA4, 0xBF, 0xE5, 0x62, 0xCD, 0x63, 0xFE, 0xCE, 0xB6, 0xDF, 0xFF, 0x00, 0x4F, 0x56, 0xF5, 0xF6,
+	0x3F, 0xFC, 0x1E, 0x49, 0xFF, 0x00, 0x25, 0x2B, 0xE0, 0x27, 0xFD, 0x80, 0x75, 0xFF, 0x00, 0xFD,
+	0x29, 0xD3, 0xEB, 0xF2, 0x73, 0xC5, 0xBF, 0xB5, 0x57, 0xC5, 0xBF, 0x19, 0xFE, 0xD5, 0x73, 0xFE,
+	0xD9, 0x1A, 0xED, 0xED, 0x97, 0xFC, 0x26, 0xD7, 0x3E, 0x34, 0x5F, 0x15, 0x4B, 0x70, 0xBA, 0x6F,
+	0xFA, 0x31, 0xD4, 0x96, 0xE7, 0xCE, 0xCF, 0x93, 0xFC, 0x23, 0x76, 0xDF, 0x97, 0xB7, 0x4A, 0xEF,
+	0x7F, 0x6F, 0xEF, 0xF8, 0x29, 0xCF, 0xED, 0x45, 0xFF, 0x00, 0x05, 0x28, 0xD5, 0x3C, 0x33, 0xAE,
+	0x7E, 0xD4, 0x1A, 0xBE, 0x87, 0x79, 0x37, 0x84, 0xED, 0x6E, 0xE1, 0xD1, 0xCE, 0x91, 0xA2, 0xFD,
+	0x8F, 0x6A, 0x4F, 0xE5, 0x99, 0x01, 0xFE, 0xF1, 0xDF, 0x12, 0xF3, 0x53, 0xCD, 0xBF, 0x99, 0x5E,
+	0xCE, 0x5E, 0xD2, 0x2F, 0xB1, 0xFB, 0x2B, 0xF0, 0xF7, 0xFE, 0x55, 0x17, 0xB8, 0xFF, 0x00, 0xB2,
+	0x53, 0xAA, 0x7F, 0xE9, 0xE2, 0x7A, 0xF0, 0xFF, 0x00, 0xF8, 0x33, 0x63, 0xFE, 0x4A, 0x57, 0xC7,
+	0xAF, 0xFB, 0x02, 0x78, 0x7B, 0xFF, 0x00, 0x47, 0x6A, 0x15, 0xF9, 0xFD, 0xA6, 0xFF, 0x00, 0xC1,
+	0x62, 0xBF, 0x6D, 0x0D, 0x1B, 0xF6, 0x1E, 0x6F, 0xF8, 0x27, 0x7D, 0xA6, 0xBB, 0xE1, 0xC1, 0xF0,
+	0xE5, 0xB4, 0x49, 0xB4, 0xA3, 0x6E, 0xDE, 0x1F, 0x46, 0xBA, 0x36, 0xF2, 0x5C, 0x9B, 0x99, 0x07,
+	0x9F, 0xD8, 0xEE, 0x6E, 0xBE, 0xB5, 0xCE, 0xFE, 0xC0, 0xBF, 0xF0, 0x53, 0x8F, 0xDA, 0x97, 0xFE,
+	0x09, 0xAD, 0xAA, 0xF8, 0x97, 0x57, 0xFD, 0x97, 0xB5, 0x7D, 0x0E, 0xCE, 0xE7, 0xC5, 0x96, 0xB6,
+	0xD0, 0x6A, 0xA3, 0x5A, 0xD2, 0x62, 0xBD, 0xCA, 0x40, 0x64, 0x68, 0xB0, 0xDD, 0xBE, 0x69, 0x24,
+	0xAD, 0x3D, 0xA2, 0xBA, 0x64, 0xC6, 0x8C, 0xB9, 0x1F, 0x99, 0xEF, 0x3F, 0x0F, 0xBF, 0xE5, 0x66,
+	0xC9, 0xFF, 0x00, 0xEC, 0xF1, 0xF5, 0x4F, 0xFD, 0x48, 0x67, 0xAF, 0xA3, 0x7F, 0xE0, 0xF1, 0x8F,
+	0xF9, 0x39, 0x0F, 0x83, 0x7F, 0xF6, 0x21, 0xEA, 0x1F, 0xFA, 0x5A, 0xB5, 0xF9, 0x87, 0xA4, 0xFE,
+	0xD7, 0x9F, 0x18, 0xF4, 0x8F, 0xDB, 0x11, 0xBF, 0x6E, 0x4B, 0x0B, 0xDD, 0x34, 0xF8, 0xF9, 0xBC,
+	0x79, 0x37, 0x8C, 0x7C, 0xFF, 0x00, 0xB0, 0x86, 0xB4, 0x3A, 0x8B, 0xDE, 0xB5, 0xE3, 0x9F, 0x23,
+	0xFB, 0xA6, 0x57, 0x7C, 0x2F, 0x61, 0xC5, 0x75, 0x7F, 0xB7, 0xBF, 0xFC, 0x14, 0x8F, 0xF6, 0x9B,
+	0xFF, 0x00, 0x82, 0x93, 0xF8, 0xAF, 0x41, 0xF1, 0x87, 0xED, 0x3B, 0xA8, 0x68, 0xB7, 0x17, 0xDE,
+	0x1B, 0xD3, 0xA5, 0xD3, 0xF4, 0xD6, 0xD1, 0x74, 0x7F, 0xB1, 0x28, 0x82, 0x56, 0xDE, 0xD9, 0x1D,
+	0xF9, 0xA8, 0xE7, 0x2A, 0x34, 0xE6, 0xA7, 0x17, 0xD8, 0xFD, 0xA1, 0xFD, 0xB2, 0x73, 0xFF, 0x00,
+	0x10, 0x8D, 0x68, 0xFF, 0x00, 0xF6, 0x4A, 0xFC, 0x07, 0xFF, 0x00, 0xA7, 0xAD, 0x22, 0xBC, 0x9F,
+	0xFE, 0x0C, 0xC9, 0xFB, 0xBF, 0xB4, 0x6F, 0xFB, 0x9E, 0x0F, 0xFF, 0x00, 0xDC, 0xF5, 0x7E, 0x72,
+	0xF8, 0xFF, 0x00, 0xFE, 0x0B, 0x23, 0xFB, 0x6A, 0xFC, 0x4A, 0xFD, 0x86, 0xA1, 0xFF, 0x00, 0x82,
+	0x77, 0x78, 0xB3, 0xC4, 0x1E, 0x1B, 0x93, 0xE1, 0xCD, 0xBE, 0x8F, 0xA6, 0xE9, 0x51, 0xDB, 0xA6,
+	0x80, 0x89, 0x76, 0x2D, 0x6C, 0xA7, 0xB7, 0x9E, 0x01, 0xE7, 0x77, 0x6F, 0x32, 0x04, 0xCB, 0x77,
+	0x3C, 0xD6, 0x1F, 0xEC, 0x03, 0xFF, 0x00, 0x05, 0x52, 0xFD, 0xAB, 0xBF, 0xE0, 0x9A, 0x31, 0xF8,
+	0xB9, 0x7F, 0x65, 0xBD, 0x5B, 0x44, 0xB3, 0x1E, 0x35, 0x4B, 0x23, 0xAD, 0x0D, 0x7B, 0x49, 0x4B,
+	0xC7, 0x2D, 0x68, 0x2E, 0x7C, 0x9D, 0xA7, 0xB7, 0x37, 0x32, 0x53, 0xE6, 0xEA, 0x4F, 0xB1, 0x97,
+	0xB3, 0x6B, 0xBB, 0x3D, 0xCB, 0xF6, 0x2E, 0xFF, 0x00, 0x95, 0x91, 0xF4, 0xDF, 0xFB, 0x39, 0x0D,
+	0x6F, 0xFF, 0x00, 0x4B, 0x2F, 0x2B, 0xDC, 0xBF, 0xE0, 0xF0, 0x9F, 0xF9, 0x3D, 0xDF, 0x86, 0x3F,
+	0xF6, 0x4A, 0x7F, 0xF7, 0x25, 0x79, 0x5F, 0x9B, 0xBE, 0x02, 0xFD, 0xAF, 0x7E, 0x33, 0x7C, 0x2F,
+	0xFD, 0xAD, 0xD7, 0xF6, 0xD9, 0xF0, 0xBD, 0xEE, 0x9F, 0xFF, 0x00, 0x09, 0xCC, 0x5E, 0x2B, 0xBA,
+	0xF1, 0x22, 0xDC, 0x4F, 0x61, 0xBE, 0xD8, 0xDF, 0x4F, 0x23, 0xBB, 0x91, 0x0F, 0x65, 0xCB, 0x9C,
+	0x2F, 0x61, 0xC5, 0x74, 0x9F, 0xB7, 0x87, 0xFC, 0x14, 0x43, 0xF6, 0x91, 0xFF, 0x00, 0x82, 0x8D,
+	0x7C, 0x46, 0xD1, 0x7E, 0x2B, 0x7E, 0xD3, 0x1A, 0x86, 0x8F, 0x71, 0xAB, 0x68, 0x7A, 0x4A, 0xE9,
+	0x5A, 0x6B, 0x68, 0xBA, 0x4F, 0xD8, 0xA3, 0x10, 0xAC, 0xD2, 0xCF, 0xF3, 0x2F, 0xF1, 0x7C, 0xF2,
+	0x9A, 0x5C, 0xDA, 0x15, 0xEC, 0xE5, 0xED, 0x53, 0xF2, 0x3F, 0x69, 0x7F, 0xE0, 0xA7, 0x3F, 0xF2,
+	0xAA, 0xA7, 0xC3, 0x8F, 0xFB, 0x25, 0x7F, 0x0C, 0xFF, 0x00, 0xF4, 0x5E, 0x97, 0x58, 0x5F, 0xF0,
+	0x67, 0x4F, 0xFC, 0x9B, 0x4F, 0xC6, 0x3F, 0xFB, 0x1E, 0x6C, 0x3F, 0xF4, 0x8A, 0xBF, 0x2B, 0x3E,
+	0x2F, 0xFF, 0x00, 0xC1, 0x63, 0x7F, 0x6C, 0xFF, 0x00, 0x8D, 0xDF, 0xB1, 0x4E, 0x8F, 0xFB, 0x02,
+	0x78, 0xEF, 0x5F, 0xF0, 0xD4, 0x9F, 0x0F, 0x74, 0x5D, 0x0F, 0x48, 0xD2, 0xB4, 0xFB, 0x7B, 0x7F,
+	0x0F, 0xC6, 0x97, 0x02, 0xDF, 0x4D, 0x48, 0x56, 0xD0, 0x19, 0x8F, 0x56, 0xCC, 0x31, 0xE4, 0xF7,
+	0x3C, 0xD5, 0x5F, 0xD8, 0x27, 0xFE, 0x0A, 0xED, 0xFB, 0x60, 0x7F, 0xC1, 0x37, 0x7C, 0x27, 0xAF,
+	0x78, 0x23, 0xF6, 0x65, 0xD6, 0x34, 0x1B, 0x5D, 0x3F, 0xC4, 0x9A, 0x94, 0x57, 0xFA, 0x84, 0x5A,
+	0xBE, 0x8B, 0x15, 0xEC, 0x8D, 0x2C, 0x71, 0xB2, 0x71, 0x27, 0xF0, 0x7C, 0x87, 0xF0, 0xA7, 0xCD,
+	0xD4, 0x9F, 0x63, 0x3F, 0x67, 0x63, 0xD1, 0x7F, 0xE0, 0x89, 0x7F, 0xF2, 0x9C, 0xFF, 0x00, 0x86,
+	0x5F, 0xF6, 0x3D, 0x6B, 0x1F, 0xFA, 0x43, 0xA8, 0xD7, 0xAB, 0x7F, 0xC1, 0xD9, 0x5F, 0xF2, 0x94,
+	0x6B, 0x1F, 0xFB, 0x24, 0xFA, 0x47, 0xFE, 0x95, 0xDF, 0x57, 0xC1, 0x9F, 0xB3, 0xC7, 0xED, 0x4D,
+	0xF1, 0x63, 0xF6, 0x5F, 0xFD, 0xA4, 0xB4, 0x7F, 0xDA, 0xAB, 0xE1, 0x55, 0xEE, 0x9B, 0x1F, 0x8C,
+	0x34, 0x5D, 0x4A, 0xE6, 0xF2, 0xC6, 0x6B, 0xAD, 0x3C, 0x4D, 0x6F, 0xE6, 0xCF, 0x13, 0xA3, 0x1F,
+	0x2C, 0x76, 0xC3, 0xBF, 0x1E, 0x95, 0xB7, 0xFB, 0x70, 0x7E, 0xDC, 0xDF, 0x1D, 0xFF, 0x00, 0xE0,
+	0xA0, 0xFF, 0x00, 0x19, 0xE1, 0xF8, 0xF3, 0xFB, 0x46, 0xEA, 0x7A, 0x4D, 0xD6, 0xBD, 0x6F, 0xA2,
+	0xDB, 0xE9, 0x2A, 0xDA, 0x3E, 0x9B, 0xF6, 0x48, 0x7E, 0xCB, 0x0C, 0xB2, 0x4B, 0x1E, 0x57, 0xFB,
+	0xDE, 0x64, 0xB2, 0x54, 0xF3, 0x69, 0x63, 0x4E, 0x49, 0x7B, 0x44, 0xFB, 0x23, 0xC7, 0x4F, 0x5A,
+	0x28, 0x3B, 0xC1, 0xC4, 0x9F, 0x7B, 0xF8, 0xBE, 0xB4, 0x54, 0x9A, 0x05, 0x14, 0x51, 0x40, 0x5C,
+	0x3F, 0x8D, 0x94, 0xF4, 0x1F, 0x79, 0x63, 0xFF, 0x00, 0x58, 0x41, 0x0B, 0xB9, 0x47, 0xFB, 0xC1,
+	0x96, 0xBF, 0x67, 0x3F, 0x62, 0x1F, 0xD9, 0x27, 0xE2, 0x37, 0xC0, 0x7F, 0xD9, 0xB3, 0xC3, 0xBE,
+	0x0E, 0xBB, 0xF8, 0x75, 0xAC, 0x47, 0xAB, 0x5E, 0x5B, 0x9D, 0x4F, 0x5C, 0x07, 0x4D, 0x91, 0xB6,
+	0x5D, 0x4C, 0x03, 0xBF, 0x21, 0x39, 0xD8, 0x8C, 0x90, 0xE7, 0xFD, 0x9A, 0xF8, 0xC3, 0xFE, 0x08,
+	0x2D, 0xFB, 0x0F, 0x9F, 0xDB, 0x93, 0xFE, 0x0A, 0x31, 0xE0, 0xFF, 0x00, 0x0E, 0xF8, 0x87, 0x46,
+	0xFB, 0x47, 0x84, 0xBC, 0x0F, 0x37, 0xFC, 0x25, 0x1E, 0x30, 0xDD, 0x06, 0xE8, 0xE5, 0xB6, 0xB6,
+	0x64, 0x68, 0x2D, 0x9C, 0x77, 0x13, 0xDD, 0x79, 0x31, 0x3A, 0xFF, 0x00, 0x14, 0x46, 0x56, 0xAF,
+	0xEA, 0xF9, 0x09, 0x28, 0x0B, 0x0C, 0x1C, 0x74, 0xCD, 0x6D, 0x4E, 0x36, 0x38, 0xB1, 0x53, 0xD7,
+	0x95, 0x1F, 0x8D, 0x67, 0xE1, 0xA7, 0xC4, 0x62, 0x72, 0x3E, 0x1D, 0x6B, 0x9F, 0x86, 0x97, 0x2F,
+	0xFF, 0x00, 0x11, 0x49, 0xFF, 0x00, 0x0A, 0xCF, 0xE2, 0x3F, 0xFD, 0x13, 0xAD, 0x73, 0xFF, 0x00,
+	0x05, 0x72, 0xFF, 0x00, 0xF1, 0x15, 0xFB, 0x2D, 0x45, 0x6C, 0x72, 0x1F, 0x8D, 0x3F, 0xF0, 0xAC,
+	0xFE, 0x23, 0xFF, 0x00, 0xD1, 0x3A, 0xD7, 0x3F, 0xF0, 0x57, 0x2F, 0xFF, 0x00, 0x11, 0x5F, 0xA4,
+	0x5F, 0xF0, 0x4E, 0xAD, 0x2B, 0x55, 0xD1, 0xBF, 0x65, 0x5D, 0x06, 0xC3, 0x57, 0xD2, 0xA6, 0xB4,
+	0xB8, 0x4B, 0xCB, 0xE2, 0x6D, 0xEE, 0xA0, 0x31, 0xB8, 0x06, 0xE9, 0xF9, 0xE7, 0x15, 0xEE, 0x94,
+	0x50, 0x07, 0xE6, 0x0F, 0xFC, 0x15, 0x03, 0x4F, 0xBD, 0xB9, 0xFD, 0xAD, 0xF5, 0x3F, 0xB3, 0xD8,
+	0x4A, 0xCB, 0xFD, 0x97, 0x63, 0xB5, 0x95, 0x33, 0x93, 0xE5, 0x0C, 0xD7, 0xCF, 0x63, 0x48, 0xD4,
+	0x80, 0xC7, 0xF6, 0x6D, 0xC7, 0xFD, 0xFA, 0xAF, 0xDB, 0x6B, 0xAD, 0x77, 0x45, 0xB2, 0x9F, 0xC8,
+	0xBD, 0xD6, 0xAD, 0xE1, 0x7F, 0xEE, 0x49, 0x70, 0x8B, 0xFC, 0xE9, 0xA3, 0xC5, 0x5E, 0x19, 0x23,
+	0x27, 0xC4, 0x96, 0x23, 0xFE, 0xDE, 0x92, 0x83, 0xA6, 0x38, 0x8E, 0x58, 0xA5, 0x63, 0xF1, 0x2F,
+	0xFB, 0x27, 0x52, 0xFF, 0x00, 0xA0, 0x6D, 0xC7, 0xFD, 0xFA, 0xA3, 0xFB, 0x27, 0x52, 0xFF, 0x00,
+	0xA0, 0x6D, 0xC7, 0xFD, 0xFA, 0xAF, 0xDB, 0x3F, 0xF8, 0x4A, 0x3C, 0x31, 0xFF, 0x00, 0x43, 0x2D,
+	0x97, 0xFE, 0x05, 0xA5, 0x1F, 0xF0, 0x93, 0xF8, 0x63, 0xFE, 0x86, 0x5B, 0x2F, 0xFC, 0x0B, 0x4A,
+	0x07, 0xF5, 0x8F, 0x23, 0xF1, 0x33, 0xFB, 0x27, 0x52, 0xFF, 0x00, 0xA0, 0x6D, 0xC7, 0xFD, 0xFA,
+	0xAF, 0xD8, 0xAF, 0xD9, 0x8D, 0x1A, 0x3F, 0xD9, 0xB3, 0xE1, 0xEC, 0x6E, 0xA5, 0x59, 0x7C, 0x0F,
+	0xA4, 0x86, 0x56, 0xED, 0xFE, 0x87, 0x15, 0x75, 0x3F, 0xF0, 0x94, 0xF8, 0x67, 0xFE, 0x86, 0x4B,
+	0x2F, 0xFC, 0x0A, 0x8E, 0xAE, 0xC5, 0x2C, 0x53, 0xC4, 0xB3, 0xC1, 0x22, 0xBA, 0x3A, 0x86, 0x47,
+	0x53, 0x90, 0xC0, 0xF4, 0x22, 0x83, 0x3A, 0xB5, 0x1D, 0x4B, 0x69, 0xB1, 0xF9, 0x6F, 0xFB, 0x64,
+	0xF8, 0x0F, 0xC7, 0x57, 0xFF, 0x00, 0xB5, 0x1F, 0x8D, 0x35, 0x2D, 0x37, 0xC1, 0x5A, 0xA5, 0xC4,
+	0x32, 0x6B, 0x84, 0xAC, 0xD0, 0x69, 0xB2, 0x30, 0x2A, 0x55, 0x30, 0x41, 0x1D, 0x47, 0xBD, 0x79,
+	0x9A, 0xFC, 0x33, 0xF8, 0x8F, 0xB4, 0x63, 0xE1, 0xE6, 0xB8, 0x7D, 0xFF, 0x00, 0xB2, 0xE5, 0xE7,
+	0xFF, 0x00, 0x1C, 0xAF, 0xD9, 0x6A, 0x28, 0x31, 0x3F, 0x1A, 0x7F, 0xE1, 0x59, 0xFC, 0x47, 0xFF,
+	0x00, 0xA2, 0x75, 0xAE, 0x7F, 0xE0, 0xAE, 0x5F, 0xFE, 0x22, 0x8F, 0xF8, 0x56, 0x7F, 0x11, 0xFF,
+	0x00, 0xE8, 0x9D, 0x6B, 0x9F, 0xF8, 0x2B, 0x97, 0xFF, 0x00, 0x88, 0xAF, 0xD9, 0x6A, 0x28, 0x03,
+	0xF1, 0xA7, 0xFE, 0x15, 0x9F, 0xC4, 0x7F, 0xFA, 0x27, 0x5A, 0xE7, 0xFE, 0x0A, 0xE5, 0xFF, 0x00,
+	0xE2, 0x2B, 0xEE, 0x4F, 0xF8, 0x24, 0xE6, 0x83, 0xAE, 0xF8, 0x7B, 0xE1, 0xE7, 0x8C, 0x2D, 0x35,
+	0xCD, 0x0A, 0xF2, 0xC6, 0x46, 0xD6, 0xA0, 0x65, 0x8E, 0xF2, 0x0F, 0x2D, 0x98, 0x79, 0x3D, 0x46,
+	0x71, 0xFD, 0x2B, 0xEB, 0x2A, 0xA3, 0x01, 0xC7, 0x88, 0xAF, 0x8F, 0xFD, 0x38, 0xDB, 0x7F, 0xE8,
+	0x73, 0x50, 0x07, 0xC0, 0x3F, 0xF0, 0x53, 0xCF, 0x07, 0x78, 0xB7, 0xC4, 0x1F, 0xB4, 0x8C, 0x37,
+	0xDA, 0x0F, 0x85, 0xB5, 0x3B, 0xE8, 0xD7, 0xC3, 0x76, 0xAA, 0xF2, 0x59, 0xD8, 0x3B, 0xAA, 0xFE,
+	0xF2, 0x6E, 0xA7, 0x07, 0xF9, 0x57, 0xCE, 0xBF, 0xF0, 0xAC, 0xFE, 0x23, 0xFF, 0x00, 0xD1, 0x3A,
+	0xD7, 0x3F, 0xF0, 0x57, 0x2F, 0xFF, 0x00, 0x11, 0x5F, 0xB1, 0x7A, 0x77, 0xFC, 0x7F, 0x6A, 0x1F,
+	0xF5, 0xF8, 0xBF, 0xFA, 0x26, 0x3A, 0xB7, 0x40, 0x1F, 0x8D, 0x3F, 0xF0, 0xAC, 0xFE, 0x23, 0xFF,
+	0x00, 0xD1, 0x3A, 0xD7, 0x3F, 0xF0, 0x57, 0x2F, 0xFF, 0x00, 0x11, 0x47, 0xFC, 0x2B, 0x3F, 0x88,
+	0xFF, 0x00, 0xF4, 0x4E, 0xB5, 0xCF, 0xFC, 0x15, 0xCB, 0xFF, 0x00, 0xC4, 0x57, 0xEC, 0xB5, 0x14,
+	0x01, 0xF8, 0xD2, 0x7E, 0x1A, 0x7C, 0x48, 0x1C, 0xFF, 0x00, 0xC2, 0xBD, 0xD7, 0x17, 0xDC, 0xE9,
+	0x52, 0x7F, 0xF1, 0x03, 0xF9, 0xD7, 0xDB, 0x5F, 0xF0, 0x49, 0x7F, 0x0E, 0x6B, 0xDE, 0x1D, 0xF0,
+	0xCF, 0x8D, 0xA3, 0xD7, 0x7C, 0x3B, 0x7F, 0xA7, 0xC9, 0x25, 0xE5, 0x89, 0x58, 0xEF, 0xAD, 0xCC,
+	0x6C, 0xE0, 0x2C, 0xDC, 0x8C, 0xF6, 0xAF, 0xAF, 0x28, 0x27, 0x08, 0xC6, 0x80, 0x3F, 0x3C, 0xFF,
+	0x00, 0xE0, 0xA7, 0x9E, 0x0E, 0xF1, 0x6F, 0x88, 0x3F, 0x69, 0x18, 0x6F, 0xB4, 0x1F, 0x0B, 0x6A,
+	0x77, 0xD1, 0xAF, 0x86, 0xED, 0x55, 0xE4, 0xB3, 0xB0, 0x77, 0x55, 0xFD, 0xE4, 0xDD, 0x4E, 0x0F,
+	0xF2, 0xAF, 0x9D, 0x7F, 0xE1, 0x59, 0xFC, 0x47, 0xFF, 0x00, 0xA2, 0x75, 0xAE, 0x7F, 0xE0, 0xAE,
+	0x5F, 0xFE, 0x22, 0xBF, 0x62, 0xF4, 0xEF, 0xF8, 0xFE, 0xD4, 0x3F, 0xEB, 0xF1, 0x7F, 0xF4, 0x4C,
+	0x75, 0x6E, 0x80, 0x3F, 0x1A, 0x7F, 0xE1, 0x59, 0xFC, 0x47, 0xFF, 0x00, 0xA2, 0x75, 0xAE, 0x7F,
+	0xE0, 0xAE, 0x5F, 0xFE, 0x22, 0x8F, 0xF8, 0x56, 0x7F, 0x11, 0xFF, 0x00, 0xE8, 0x9D, 0x6B, 0x9F,
+	0xF8, 0x2B, 0x97, 0xFF, 0x00, 0x88, 0xAF, 0xD9, 0x6A, 0x28, 0x03, 0xF1, 0xA4, 0xFC, 0x34, 0xF8,
+	0x90, 0x39, 0xFF, 0x00, 0x85, 0x7B, 0xAE, 0x2F, 0xB9, 0xD2, 0xA4, 0xFF, 0x00, 0xE2, 0x07, 0xF3,
+	0xAF, 0xB5, 0x7F, 0xE0, 0x93, 0xBE, 0x1D, 0xD7, 0xBC, 0x39, 0xE1, 0xEF, 0x1A, 0x47, 0xAF, 0x78,
+	0x72, 0xFF, 0x00, 0x4F, 0x92, 0x6B, 0xAB, 0x3D, 0xA9, 0x7D, 0x6A, 0xD1, 0xB3, 0xFC, 0xB3, 0x72,
+	0x33, 0x5F, 0x60, 0xD0, 0x7A, 0x72, 0x3F, 0x4C, 0xD1, 0xBE, 0x80, 0x3A, 0x1F, 0xB9, 0xF7, 0xB3,
+	0x4E, 0xA6, 0xC5, 0x8C, 0x12, 0x06, 0x39, 0xE9, 0x4E, 0xA0, 0x02, 0x83, 0xD2, 0x8A, 0x0F, 0x4A,
+	0x00, 0xF8, 0x4F, 0xFE, 0x0A, 0xF8, 0x31, 0xE2, 0x2F, 0x03, 0x0F, 0xFA, 0x71, 0xBE, 0xFF, 0x00,
+	0xD0, 0xE3, 0xAF, 0x8D, 0xEB, 0xEC, 0x9F, 0xF8, 0x2B, 0xEF, 0xFC, 0x8C, 0x9E, 0x07, 0xFF, 0x00,
+	0xAF, 0x2B, 0xEF, 0xFD, 0x19, 0x1D, 0x7C, 0x6D, 0x40, 0x05, 0x14, 0x51, 0x40, 0x00, 0xEB, 0x5F,
+	0x57, 0xFF, 0x00, 0xC1, 0x24, 0x7F, 0xE4, 0xB4, 0xF8, 0x9B, 0xFE, 0xC5, 0x45, 0xFF, 0x00, 0xD2,
+	0x98, 0xAB, 0xE5, 0x01, 0xD6, 0xBE, 0xAF, 0xFF, 0x00, 0x82, 0x48, 0xFF, 0x00, 0xC9, 0x69, 0xF1,
+	0x37, 0xFD, 0x8A, 0x8B, 0xFF, 0x00, 0xA5, 0x31, 0x50, 0xF6, 0x03, 0xD6, 0x7F, 0xE0, 0xAC, 0xD9,
+	0xFF, 0x00, 0x86, 0x7A, 0xD0, 0xB9, 0xFF, 0x00, 0x99, 0xC2, 0x1F, 0xFD, 0x25, 0xB9, 0xAF, 0xCF,
+	0x7A, 0xFD, 0x08, 0xFF, 0x00, 0x82, 0xB2, 0xFF, 0x00, 0xC9, 0xBB, 0xE8, 0x7F, 0xF6, 0x39, 0x43,
+	0xFF, 0x00, 0xA4, 0xB7, 0x35, 0xF9, 0xEF, 0x53, 0x14, 0x96, 0xC5, 0x3D, 0x22, 0x90, 0x51, 0x45,
+	0x15, 0x44, 0x85, 0x7B, 0xD7, 0xFC, 0x13, 0x63, 0xFE, 0x4E, 0xE7, 0x41, 0xFF, 0x00, 0xB0, 0x7E,
+	0xA1, 0xFF, 0x00, 0xA4, 0xEF, 0x5E, 0x0B, 0x5E, 0xF5, 0xFF, 0x00, 0x04, 0xD8, 0xFF, 0x00, 0x93,
+	0xB9, 0xD0, 0x7F, 0xEC, 0x1F, 0xA8, 0x7F, 0xE9, 0x3B, 0xD0, 0x07, 0xD8, 0x7F, 0xF0, 0x51, 0x5C,
+	0xFF, 0x00, 0xC3, 0x1E, 0xF8, 0xB3, 0x9F, 0xF9, 0x69, 0x63, 0xFF, 0x00, 0xA5, 0xB0, 0xD7, 0xE6,
+	0x15, 0x7E, 0x9F, 0x7F, 0xC1, 0x45, 0x3F, 0xE4, 0xCE, 0xFC, 0x5B, 0xFF, 0x00, 0x5D, 0x2C, 0x7F,
+	0xF4, 0xB6, 0x0A, 0xFC, 0xC1, 0xA8, 0x82, 0x51, 0xDB, 0xFA, 0xD1, 0x15, 0xF6, 0x57, 0xF5, 0xD4,
+	0x28, 0xA2, 0x8A, 0xB2, 0x42, 0xBD, 0x13, 0xF6, 0x4A, 0xFF, 0x00, 0x93, 0x9C, 0xF0, 0x0F, 0xFD,
+	0x8D, 0x56, 0x9F, 0xFA, 0x10, 0xAF, 0x3B, 0xAF, 0x44, 0xFD, 0x92, 0xBF, 0xE4, 0xE7, 0x3C, 0x03,
+	0xFF, 0x00, 0x63, 0x55, 0xA7, 0xFE, 0x84, 0x28, 0x03, 0xF4, 0xAB, 0xF6, 0xA6, 0xCF, 0xFC, 0x33,
+	0x3F, 0xC4, 0x3C, 0x1F, 0xF9, 0x92, 0xF5, 0x2F, 0xFD, 0x25, 0x92, 0xBF, 0x1B, 0x6B, 0xF6, 0x53,
+	0xF6, 0xA4, 0xFF, 0x00, 0x93, 0x68, 0xF8, 0x89, 0xFF, 0x00, 0x62, 0x4E, 0xA7, 0xFF, 0x00, 0xA4,
+	0xB2, 0x57, 0xE3, 0x5D, 0x7E, 0x7D, 0xC6, 0x0F, 0x96, 0xBD, 0x14, 0xBB, 0x3F, 0xCC, 0xFE, 0x90,
+	0xF0, 0x36, 0x9D, 0x39, 0x65, 0x98, 0xC7, 0x24, 0x9F, 0xBF, 0x1D, 0xD7, 0xF7, 0x58, 0x51, 0x45,
+	0x15, 0xF1, 0xDC, 0xD2, 0xEE, 0xFE, 0xF3, 0xF7, 0x4F, 0x63, 0x4B, 0xF9, 0x57, 0xDC, 0x82, 0xBE,
+	0x86, 0xFF, 0x00, 0x82, 0x5F, 0x67, 0xFE, 0x1A, 0xE7, 0x49, 0xC7, 0xFD, 0x02, 0xEF, 0x7F, 0xF4,
+	0x51, 0xAF, 0x9E, 0x6B, 0xE8, 0x7F, 0xF8, 0x25, 0xE7, 0xFC, 0x9D, 0xD6, 0x93, 0xFF, 0x00, 0x60,
+	0xAB, 0xEF, 0xFD, 0x14, 0x6B, 0xD1, 0xC9, 0xE5, 0x2F, 0xED, 0x2A, 0x5A, 0xF5, 0x47, 0xCA, 0xF1,
+	0xCD, 0x3A, 0x71, 0xE0, 0xFC, 0x6B, 0x51, 0x5F, 0xC3, 0x97, 0x43, 0xED, 0x1F, 0xF8, 0x29, 0x47,
+	0xFC, 0x9A, 0x46, 0xB9, 0xFF, 0x00, 0x5F, 0x96, 0x3F, 0xFA, 0x3D, 0x6B, 0xF3, 0x2E, 0xBF, 0x4D,
+	0x3F, 0xE0, 0xA5, 0x3F, 0xF2, 0x69, 0x3A, 0xE7, 0xFD, 0x7E, 0x58, 0xFF, 0x00, 0xE9, 0x42, 0xD7,
+	0xE6, 0x5D, 0x7E, 0xC2, 0x7F, 0x12, 0x2D, 0x82, 0x8A, 0x28, 0xA0, 0x61, 0x5D, 0xD6, 0xBF, 0xFB,
+	0x0B, 0xD9, 0xFF, 0x00, 0xC1, 0x41, 0x3F, 0xE0, 0x9C, 0x5F, 0x1A, 0x3E, 0x0A, 0xE9, 0x9A, 0x5C,
+	0x73, 0xF8, 0xA3, 0x4E, 0xB8, 0xD3, 0xF5, 0xCF, 0x04, 0xC8, 0x63, 0xF9, 0xD7, 0x53, 0xB7, 0x8A,
+	0xE4, 0xAC, 0x63, 0xFE, 0xBB, 0x46, 0xD3, 0x5B, 0x7F, 0xDB, 0xC5, 0x70, 0xB5, 0xF7, 0x17, 0xFC,
+	0x12, 0x1D, 0x0C, 0x9E, 0x1B, 0xF1, 0xC0, 0x97, 0xE6, 0x46, 0xBE, 0xB1, 0x4C, 0x6D, 0xDC, 0xAC,
+	0x36, 0x4F, 0x90, 0x68, 0x7A, 0xA1, 0xC5, 0xF2, 0xCA, 0xE7, 0xF2, 0x89, 0x73, 0x6D, 0x77, 0x67,
+	0x71, 0x25, 0x9D, 0xF5, 0xB3, 0x43, 0x3C, 0x2E, 0x52, 0x68, 0x5F, 0xAA, 0x30, 0x38, 0x2A, 0x7D,
+	0xC1, 0xE2, 0x99, 0x5F, 0xA3, 0x1F, 0xF0, 0x72, 0xD7, 0xEC, 0x09, 0x1F, 0xEC, 0x8D, 0xFB, 0x77,
+	0x4D, 0xF1, 0x8F, 0xC1, 0x7A, 0x28, 0x5F, 0x07, 0x7C, 0x5E, 0x37, 0x1A, 0xCD, 0x94, 0x71, 0xF0,
+	0x2D, 0xF5, 0x40, 0xCA, 0x6F, 0xED, 0xC7, 0xB1, 0x92, 0x51, 0x71, 0xFF, 0x00, 0x6F, 0x95, 0xF9,
+	0xCE, 0x09, 0x3C, 0x96, 0xDD, 0xFE, 0xD1, 0xEF, 0x5C, 0x92, 0xD1, 0xD8, 0xF5, 0x69, 0xC9, 0x4E,
+	0x37, 0x41, 0x45, 0x14, 0x52, 0x28, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x5C, 0xA8, 0x02, 0xBD, 0xAB, 0xF6, 0x4E, 0xF8, 0x7D, 0xE1, 0x1F, 0x1A, 0xE9, 0xDA, 0xD5,
+	0xC7, 0x8A, 0x7C, 0x3D, 0x6F, 0x7C, 0xF6, 0xF3, 0x5B, 0x0B, 0x5F, 0x37, 0xB7, 0x32, 0x66, 0xBC,
+	0x56, 0xBE, 0x82, 0xFD, 0x89, 0xBF, 0xE4, 0x17, 0xE2, 0x1F, 0xFA, 0xFA, 0xB4, 0xFE, 0x52, 0x55,
+	0xC2, 0x2A, 0x52, 0xD4, 0xCE, 0xAD, 0xF9, 0x4F, 0x46, 0x1F, 0x01, 0x3E, 0x0D, 0x63, 0xE5, 0xF0,
+	0x25, 0x80, 0x1D, 0x87, 0x93, 0xD2, 0x8F, 0xF8, 0x50, 0x9F, 0x07, 0x3F, 0xE8, 0x46, 0xB0, 0xFF,
+	0x00, 0xBF, 0x35, 0xD6, 0x51, 0x5D, 0x1C, 0x91, 0xE8, 0x70, 0xF3, 0x4B, 0xB9, 0xC9, 0xFF, 0x00,
+	0xC2, 0x84, 0xF8, 0x39, 0xFF, 0x00, 0x42, 0x35, 0x87, 0xFD, 0xF9, 0xA3, 0xFE, 0x14, 0x27, 0xC1,
+	0xCF, 0xFA, 0x11, 0xAC, 0x3F, 0xEF, 0xCD, 0x75, 0x94, 0x51, 0xC9, 0x10, 0xE6, 0x9F, 0x73, 0x93,
+	0xFF, 0x00, 0x85, 0x09, 0xF0, 0x73, 0xFE, 0x84, 0x6B, 0x0F, 0xFB, 0xF3, 0x47, 0xFC, 0x28, 0x4F,
+	0x83, 0x9F, 0xF4, 0x23, 0x58, 0x7F, 0xDF, 0x9A, 0xEB, 0x28, 0xA3, 0x92, 0x3D, 0x05, 0xCD, 0x25,
+	0xD4, 0xE4, 0xFF, 0x00, 0xE1, 0x42, 0x7C, 0x1C, 0xFF, 0x00, 0xA1, 0x1A, 0xC3, 0xFE, 0xFC, 0xD1,
+	0xFF, 0x00, 0x0A, 0x13, 0xE0, 0xE7, 0xFD, 0x08, 0xD6, 0x1F, 0xF7, 0xE6, 0xBA, 0xCA, 0x28, 0xE5,
+	0x8F, 0x51, 0xF3, 0x4B, 0xB9, 0xC9, 0xFF, 0x00, 0xC2, 0x84, 0xF8, 0x39, 0xFF, 0x00, 0x42, 0x35,
+	0x87, 0xFD, 0xF9, 0xA3, 0xFE, 0x14, 0x27, 0xC1, 0xCF, 0xFA, 0x11, 0xAC, 0x3F, 0xEF, 0xCD, 0x75,
+	0x94, 0x51, 0xC9, 0x1E, 0x82, 0xE6, 0x97, 0x73, 0x93, 0xFF, 0x00, 0x85, 0x09, 0xF0, 0x73, 0xFE,
+	0x84, 0x6B, 0x0F, 0xFB, 0xF3, 0x5F, 0x4F, 0x7E, 0xCC, 0x1F, 0xB1, 0x4F, 0xEC, 0xA1, 0xE2, 0xFF,
+	0x00, 0x84, 0x56, 0x7A, 0xC7, 0x8A, 0x7E, 0x09, 0x68, 0x77, 0x77, 0x12, 0x5D, 0x5C, 0x24, 0xD3,
+	0x4D, 0x0C, 0x9C, 0xA8, 0x73, 0xB4, 0x71, 0x5E, 0x1B, 0x5F, 0x61, 0x7E, 0xC7, 0x5F, 0xF2, 0x43,
+	0x6C, 0xFF, 0x00, 0xEB, 0xF2, 0xE3, 0xFF, 0x00, 0x43, 0x35, 0x51, 0x8C, 0x7A, 0x8B, 0x9A, 0x4B,
+	0xA9, 0x9F, 0xFF, 0x00, 0x0C, 0x01, 0xFB, 0x1A, 0xB7, 0xCC, 0xDF, 0xB3, 0xD7, 0x87, 0xC1, 0x3D,
+	0x84, 0x6F, 0x47, 0xFC, 0x3B, 0xFF, 0x00, 0xF6, 0x33, 0xFF, 0x00, 0xA3, 0x7B, 0xD0, 0x3F, 0xEF,
+	0xDB, 0xD7, 0xB1, 0x51, 0x55, 0xCB, 0x1E, 0x88, 0x9E, 0x7A, 0x9D, 0xCF, 0x1D, 0xFF, 0x00, 0x87,
+	0x7F, 0xFE, 0xC6, 0x7F, 0xF4, 0x6F, 0x7A, 0x07, 0xFD, 0xFB, 0x7A, 0x3F, 0xE1, 0xDF, 0xFF, 0x00,
+	0xB1, 0x9F, 0xFD, 0x1B, 0xDE, 0x81, 0xFF, 0x00, 0x7E, 0xDE, 0xBD, 0x8A, 0x8A, 0x39, 0x43, 0x9A,
+	0xA7, 0x73, 0xC7, 0x7F, 0xE1, 0xDF, 0xFF, 0x00, 0xB1, 0x9F, 0xFD, 0x1B, 0xDE, 0x81, 0xFF, 0x00,
+	0x7E, 0xDE, 0x8F, 0xF8, 0x77, 0xFF, 0x00, 0xEC, 0x67, 0xFF, 0x00, 0x46, 0xF7, 0xA0, 0x7F, 0xDF,
+	0xB7, 0xAF, 0x62, 0xA2, 0x8E, 0x58, 0xF6, 0x0E, 0x6A, 0x9D, 0xCF, 0x1D, 0xFF, 0x00, 0x87, 0x7F,
+	0xFE, 0xC6, 0x7F, 0xF4, 0x6F, 0x7A, 0x07, 0xFD, 0xFB, 0x7A, 0x3F, 0xE1, 0xDF, 0xFF, 0x00, 0xB1,
+	0x9F, 0xFD, 0x1B, 0xDE, 0x81, 0xFF, 0x00, 0x7E, 0xDE, 0xBD, 0x8A, 0x8A, 0x39, 0x43, 0x9A, 0xA7,
+	0x73, 0xC7, 0x7F, 0xE1, 0xDF, 0xFF, 0x00, 0xB1, 0x9F, 0xFD, 0x1B, 0xDE, 0x81, 0xFF, 0x00, 0x7E,
+	0xDE, 0x8F, 0xF8, 0x77, 0xFF, 0x00, 0xEC, 0x67, 0xFF, 0x00, 0x46, 0xF7, 0xA0, 0x7F, 0xDF, 0xB7,
+	0xAF, 0x62, 0xA2, 0x8E, 0x58, 0x87, 0x35, 0x4E, 0xE7, 0x8E, 0xFF, 0x00, 0xC3, 0xBF, 0xFF, 0x00,
+	0x63, 0x3F, 0xFA, 0x37, 0xBD, 0x03, 0xFE, 0xFD, 0xBD, 0x1F, 0xF0, 0xEF, 0xFF, 0x00, 0xD8, 0xCF,
+	0xFE, 0x8D, 0xEF, 0x40, 0xFF, 0x00, 0xBF, 0x6F, 0x5E, 0xC5, 0x45, 0x1C, 0xA1, 0xCD, 0x53, 0xB9,
+	0xE3, 0xBF, 0xF0, 0xEF, 0xFF, 0x00, 0xD8, 0xCF, 0xFE, 0x8D, 0xEF, 0x40, 0xFF, 0x00, 0xBF, 0x6F,
+	0x47, 0xFC, 0x3B, 0xFF, 0x00, 0xF6, 0x33, 0xFF, 0x00, 0xA3, 0x7B, 0xD0, 0x3F, 0xEF, 0xDB, 0xD7,
+	0xB1, 0x51, 0x47, 0x2C, 0x43, 0x9A, 0xA7, 0x73, 0xC7, 0x7F, 0xE1, 0xDF, 0xFF, 0x00, 0xB1, 0x9F,
+	0xFD, 0x1B, 0xDE, 0x81, 0xFF, 0x00, 0x7E, 0xDE, 0x8F, 0xF8, 0x77, 0xFF, 0x00, 0xEC, 0x67, 0xFF,
+	0x00, 0x46, 0xF7, 0xA0, 0x7F, 0xDF, 0xB7, 0xAF, 0x62, 0xA2, 0x8E, 0x50, 0xE6, 0xA9, 0xDC, 0xF2,
+	0xBF, 0x0C, 0xFF, 0x00, 0xC1, 0x3D, 0x3F, 0x62, 0xCD, 0x47, 0xC6, 0x7E, 0x1F, 0xD3, 0x6F, 0x3F,
+	0x67, 0x8F, 0x0F, 0xB4, 0x37, 0x1E, 0x22, 0xD2, 0xED, 0x2E, 0xE3, 0xF2, 0x65, 0xD9, 0x24, 0x72,
+	0xDE, 0xC6, 0x1C, 0x37, 0xCF, 0xFF, 0x00, 0x3C, 0x99, 0xAB, 0xEB, 0xB6, 0xFF, 0x00, 0x82, 0x41,
+	0x7F, 0xC1, 0x35, 0x4B, 0x12, 0xDF, 0xB1, 0xC7, 0x83, 0xB3, 0xDF, 0xFD, 0x15, 0xFF, 0x00, 0xF8,
+	0xBA, 0xF2, 0x7F, 0x08, 0x7F, 0xC8, 0xFD, 0xE1, 0x7F, 0xFB, 0x1C, 0x34, 0x9F, 0xFD, 0x2D, 0xB7,
+	0xAF, 0xBA, 0x6A, 0x65, 0x18, 0xA0, 0xF6, 0x93, 0xEE, 0x7C, 0xDB, 0xFF, 0x00, 0x0E, 0x81, 0xFF,
+	0x00, 0x82, 0x69, 0xFF, 0x00, 0xD1, 0x9C, 0xF8, 0x3F, 0xFF, 0x00, 0x01, 0x5F, 0xFF, 0x00, 0x8B,
+	0xA3, 0xFE, 0x1D, 0x03, 0xFF, 0x00, 0x04, 0xD3, 0xFF, 0x00, 0xA3, 0x39, 0xF0, 0x7F, 0xFE, 0x02,
+	0xBF, 0xFF, 0x00, 0x17, 0x5F, 0x49, 0x51, 0x53, 0xCB, 0x10, 0xE6, 0xA9, 0xDC, 0xF9, 0xB7, 0xFE,
+	0x1D, 0x03, 0xFF, 0x00, 0x04, 0xD3, 0xFF, 0x00, 0xA3, 0x39, 0xF0, 0x7F, 0xFE, 0x02, 0xBF, 0xFF,
+	0x00, 0x17, 0x47, 0xFC, 0x3A, 0x07, 0xFE, 0x09, 0xA7, 0xFF, 0x00, 0x46, 0x73, 0xE0, 0xFF, 0x00,
+	0xFC, 0x05, 0x7F, 0xFE, 0x2E, 0xBE, 0x92, 0xA2, 0x8E, 0x48, 0xF6, 0x0E, 0x6A, 0x9D, 0xCF, 0x9B,
+	0x7F, 0xE1, 0xD0, 0x3F, 0xF0, 0x4D, 0x3F, 0xFA, 0x33, 0x9F, 0x07, 0xFF, 0x00, 0xE0, 0x2B, 0xFF,
+	0x00, 0xF1, 0x74, 0x7F, 0xC3, 0xA0, 0x7F, 0xE0, 0x9A, 0x7F, 0xF4, 0x67, 0x3E, 0x0F, 0xFF, 0x00,
+	0xC0, 0x57, 0xFF, 0x00, 0xE2, 0xEB, 0xE9, 0x2A, 0x28, 0xE5, 0x88, 0x73, 0x54, 0xEE, 0x7C, 0xDB,
+	0xFF, 0x00, 0x0E, 0x81, 0xFF, 0x00, 0x82, 0x69, 0xFF, 0x00, 0xD1, 0x9C, 0xF8, 0x3F, 0xFF, 0x00,
+	0x01, 0x5F, 0xFF, 0x00, 0x8B, 0xA3, 0xFE, 0x1D, 0x03, 0xFF, 0x00, 0x04, 0xD3, 0xFF, 0x00, 0xA3,
+	0x39, 0xF0, 0x7F, 0xFE, 0x02, 0xBF, 0xFF, 0x00, 0x17, 0x5F, 0x49, 0x51, 0x47, 0x24, 0x7B, 0x07,
+	0x35, 0x4E, 0xE7, 0xCD, 0xBF, 0xF0, 0xE8, 0x1F, 0xF8, 0x26, 0x9F, 0xFD, 0x19, 0xCF, 0x83, 0xFF,
+	0x00, 0xF0, 0x15, 0xFF, 0x00, 0xF8, 0xBA, 0x3F, 0xE1, 0xD0, 0x3F, 0xF0, 0x4D, 0x3F, 0xFA, 0x33,
+	0x9F, 0x07, 0xFF, 0x00, 0xE0, 0x2B, 0xFF, 0x00, 0xF1, 0x75, 0xF4, 0x95, 0x14, 0x72, 0xC4, 0x39,
+	0xA7, 0xDC, 0xF9, 0xCF, 0xC3, 0x5F, 0xF0, 0x48, 0x1F, 0xF8, 0x26, 0x75, 0xCF, 0xC4, 0xEF, 0x0A,
+	0xE9, 0x17, 0x3F, 0xB1, 0xBF, 0x83, 0xDE, 0xD6, 0xF7, 0x57, 0x9A, 0x0B, 0x98, 0x24, 0xB5, 0x97,
+	0x13, 0xA8, 0xD3, 0xEE, 0x65, 0xFE, 0xFF, 0x00, 0x66, 0x58, 0xCF, 0xFC, 0x02, 0xBD, 0xAC, 0x7F,
+	0xC1, 0x0F, 0xBF, 0xE0, 0x93, 0x38, 0xE7, 0xF6, 0x16, 0xF0, 0x29, 0xF7, 0xFB, 0x2C, 0xBC, 0xFF,
+	0x00, 0xE3, 0xF5, 0xD4, 0xF8, 0x4F, 0xFE, 0x4B, 0x07, 0x82, 0x7F, 0xEC, 0x39, 0x3F, 0xFE, 0x9B,
+	0x2F, 0xAB, 0xE8, 0x41, 0xD2, 0x8E, 0x48, 0xF6, 0x0F, 0x69, 0x3E, 0xE7, 0xCA, 0x7F, 0xF0, 0xE3,
+	0xDF, 0xF8, 0x24, 0xC7, 0xFD, 0x18, 0xA7, 0x81, 0x7F, 0xF0, 0x16, 0x5F, 0xFE, 0x2E, 0x8F, 0xF8,
+	0x71, 0xEF, 0xFC, 0x12, 0x63, 0xFE, 0x8C, 0x53, 0xC0, 0xBF, 0xF8, 0x0B, 0x2F, 0xFF, 0x00, 0x17,
+	0x5F, 0x56, 0x51, 0x47, 0x2C, 0x43, 0xDA, 0x54, 0xEE, 0x7C, 0xA7, 0xFF, 0x00, 0x0E, 0x3D, 0xFF,
+	0x00, 0x82, 0x4C, 0x7F, 0xD1, 0x8A, 0x78, 0x17, 0xFF, 0x00, 0x01, 0x65, 0xFF, 0x00, 0xE2, 0xE8,
+	0xFF, 0x00, 0x87, 0x1E, 0xFF, 0x00, 0xC1, 0x26, 0x3F, 0xE8, 0xC5, 0x3C, 0x0B, 0xFF, 0x00, 0x80,
+	0xB2, 0xFF, 0x00, 0xF1, 0x75, 0xF5, 0x65, 0x14, 0x72, 0x47, 0xB0, 0x73, 0xCF, 0xB9, 0xF2, 0x9F,
+	0xFC, 0x38, 0xF7, 0xFE, 0x09, 0x31, 0xFF, 0x00, 0x46, 0x29, 0xE0, 0x5F, 0xFC, 0x05, 0x97, 0xFF,
+	0x00, 0x8B, 0xA3, 0xFE, 0x1C, 0x7B, 0xFF, 0x00, 0x04, 0x98, 0xFF, 0x00, 0xA3, 0x14, 0xF0, 0x2F,
+	0xFE, 0x02, 0xCB, 0xFF, 0x00, 0xC5, 0xD7, 0xD5, 0x94, 0x51, 0xCB, 0x10, 0xF6, 0x95, 0x3B, 0x9F,
+	0x29, 0x7F, 0xC3, 0x8F, 0x7F, 0xE0, 0x93, 0x3F, 0xF4, 0x62, 0xBE, 0x05, 0xFF, 0x00, 0xC0, 0x59,
+	0x7F, 0xF8, 0xE5, 0x1F, 0xF0, 0xE3, 0xDF, 0xF8, 0x24, 0xCF, 0xFD, 0x18, 0xAF, 0x81, 0x7F, 0xF0,
+	0x16, 0x5F, 0xFE, 0x39, 0x5F, 0x56, 0xD1, 0x47, 0x2C, 0x43, 0xDA, 0x54, 0xEE, 0x7C, 0xA5, 0xFF,
+	0x00, 0x0E, 0x3D, 0xFF, 0x00, 0x82, 0x4C, 0xFF, 0x00, 0xD1, 0x8A, 0xF8, 0x17, 0xFF, 0x00, 0x01,
+	0x65, 0xFF, 0x00, 0xE3, 0x94, 0xA7, 0xFE, 0x08, 0x81, 0xFF, 0x00, 0x04, 0x9A, 0x5C, 0x97, 0xFD,
+	0x85, 0x3C, 0x0B, 0xB5, 0x57, 0x3B, 0xBE, 0xCB, 0x2F, 0x1F, 0xF8, 0xFD, 0x7D, 0x59, 0x58, 0xFE,
+	0x24, 0x79, 0x5A, 0x21, 0xA4, 0xD8, 0x48, 0x52, 0x7B, 0xE9, 0x3C, 0x9F, 0x3A, 0x33, 0x86, 0xB7,
+	0x53, 0xCB, 0xC8, 0x0F, 0xF0, 0x10, 0xBC, 0x83, 0xDD, 0xD9, 0x28, 0xE5, 0x88, 0x7B, 0x4A, 0x9D,
+	0xCF, 0xCE, 0x5F, 0xDB, 0x27, 0xF6, 0x22, 0xFD, 0x95, 0x3F, 0x64, 0x7D, 0x1F, 0x4B, 0xD4, 0xFF,
+	0x00, 0x66, 0x9F, 0x81, 0x5A, 0x1F, 0x82, 0xE3, 0xF1, 0x2E, 0xA7, 0x3C, 0x57, 0xD1, 0xE8, 0x96,
+	0x2E, 0x8D, 0x7B, 0x0D, 0xB4, 0x7B, 0x51, 0xA5, 0x32, 0xF2, 0x48, 0x79, 0xE6, 0xC6, 0xDE, 0x3C,
+	0xAD, 0xB8, 0xAF, 0x01, 0x0F, 0xE6, 0x7C, 0xFB, 0xB7, 0x6E, 0xE7, 0x77, 0x3C, 0xFE, 0x7C, 0xFE,
+	0x75, 0xF7, 0x07, 0xFC, 0x15, 0xD2, 0xDA, 0xDA, 0xCB, 0xC2, 0xBF, 0x0F, 0xEC, 0xEC, 0xAD, 0xD6,
+	0x18, 0x61, 0xB8, 0xBC, 0x48, 0x62, 0x55, 0xC0, 0x45, 0x11, 0xC4, 0x02, 0xE3, 0xB6, 0x05, 0x7C,
+	0x3F, 0x54, 0x2E, 0x66, 0xF7, 0x0A, 0x28, 0xA2, 0x81, 0x05, 0x7E, 0x9A, 0x7F, 0xC1, 0x35, 0x7F,
+	0xE4, 0xD1, 0xF4, 0x3F, 0xFA, 0xFE, 0xBF, 0xFF, 0x00, 0xD2, 0x96, 0xAF, 0xCC, 0xBA, 0xFD, 0x34,
+	0xFF, 0x00, 0x82, 0x6A, 0xFF, 0x00, 0xC9, 0xA3, 0xE8, 0x7F, 0xF5, 0xFD, 0x7F, 0xFF, 0x00, 0xA5,
+	0x2D, 0x40, 0x1F, 0x1C, 0xFF, 0x00, 0xC1, 0x51, 0xBF, 0xE4, 0xEE, 0xF5, 0x4F, 0xFB, 0x04, 0xE9,
+	0xFF, 0x00, 0xFA, 0x28, 0x57, 0xCF, 0x35, 0xF4, 0x37, 0xFC, 0x15, 0x1B, 0xFE, 0x4E, 0xEF, 0x54,
+	0xFF, 0x00, 0xB0, 0x4E, 0x9F, 0xFF, 0x00, 0xA2, 0x85, 0x7C, 0xF3, 0x41, 0xE9, 0x53, 0xFE, 0x1A,
+	0x0A, 0x28, 0xA2, 0x82, 0xBE, 0x41, 0x5F, 0xB1, 0xFF, 0x00, 0xB3, 0x0F, 0xFC, 0x9B, 0x57, 0xC3,
+	0xCF, 0xFB, 0x11, 0xB4, 0x9F, 0xFD, 0x23, 0x8A, 0xBF, 0x1C, 0x2B, 0xF6, 0x3F, 0xF6, 0x61, 0xFF,
+	0x00, 0x93, 0x6A, 0xF8, 0x79, 0xFF, 0x00, 0x62, 0x36, 0x93, 0xFF, 0x00, 0xA4, 0x71, 0x50, 0x73,
+	0x62, 0x12, 0x49, 0x1F, 0x9B, 0x5F, 0xB6, 0x9F, 0xFC, 0x9D, 0x77, 0x8D, 0xBF, 0xEC, 0x38, 0x7F,
+	0xF4, 0x15, 0xAF, 0x2C, 0x4F, 0xB8, 0x3E, 0x95, 0xEA, 0x7F, 0xB6, 0x9F, 0xFC, 0x9D, 0x77, 0x8D,
+	0xBF, 0xEC, 0x38, 0x7F, 0xF4, 0x15, 0xAF, 0x2C, 0x4F, 0xB8, 0x3E, 0x94, 0x1C, 0x82, 0xD1, 0x45,
+	0x14, 0x00, 0x57, 0xDE, 0x9F, 0xF0, 0x48, 0x71, 0x9F, 0x86, 0x7E, 0x31, 0x1F, 0xF5, 0x1C, 0x83,
+	0xFF, 0x00, 0x44, 0xD7, 0xC1, 0x75, 0xF7, 0xA7, 0xFC, 0x12, 0x17, 0xFE, 0x49, 0xAF, 0x8C, 0x3F,
+	0xEC, 0x39, 0x07, 0xFE, 0x89, 0xA0, 0x0F, 0x1E, 0xFF, 0x00, 0x82, 0xA8, 0xFF, 0x00, 0xC9, 0xCC,
+	0xDB, 0xFF, 0x00, 0xD8, 0xB1, 0x6B, 0xFF, 0x00, 0xA1, 0xCB, 0x5F, 0x36, 0x57, 0xD2, 0x7F, 0xF0,
+	0x55, 0x1F, 0xF9, 0x39, 0x9B, 0x7F, 0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0x00,
+	0x28, 0xA2, 0x8A, 0x00, 0x3B, 0x7E, 0x15, 0xF7, 0x3F, 0xFC, 0x12, 0x04, 0x67, 0xC3, 0x7E, 0x3E,
+	0x1F, 0xF5, 0x10, 0xB0, 0xFF, 0x00, 0xD1, 0x73, 0x57, 0xC3, 0x1D, 0xBF, 0x0A, 0xFB, 0xA3, 0xFE,
+	0x09, 0x01, 0xFF, 0x00, 0x22, 0xE7, 0x8F, 0xBF, 0xEC, 0x21, 0x61, 0xFF, 0x00, 0xA2, 0xE6, 0xA0,
+	0x0F, 0x2A, 0xFF, 0x00, 0x82, 0xA8, 0xFF, 0x00, 0xC9, 0xCC, 0xDB, 0xFF, 0x00, 0xD8, 0xB1, 0x6B,
+	0xFF, 0x00, 0xA1, 0xCB, 0x5F, 0x36, 0x57, 0xD2, 0x7F, 0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B, 0x7F,
+	0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x3B, 0x7E,
+	0x15, 0xF7, 0x27, 0xFC, 0x12, 0x1B, 0xFE, 0x45, 0xBF, 0x1E, 0xFF, 0x00, 0xD8, 0x42, 0xC7, 0xFF,
+	0x00, 0x45, 0xCD, 0x5F, 0x0D, 0xF6, 0xFC, 0x2B, 0xEE, 0x4F, 0xF8, 0x24, 0x37, 0xFC, 0x8B, 0x7E,
+	0x3D, 0xFF, 0x00, 0xB0, 0x85, 0x8F, 0xFE, 0x8B, 0x9A, 0xA6, 0x5F, 0x0B, 0x03, 0xEC, 0xD8, 0x3F,
+	0xD5, 0x0A, 0x7D, 0x36, 0x0F, 0xF5, 0x4B, 0x4E, 0xAA, 0xDB, 0x60, 0xDB, 0x40, 0xA0, 0xF4, 0xA2,
+	0x83, 0xD2, 0x80, 0x3E, 0x14, 0xFF, 0x00, 0x82, 0xBE, 0xFF, 0x00, 0xC8, 0xC9, 0xE0, 0x7F, 0xFA,
+	0xF2, 0xBE, 0xFF, 0x00, 0xD1, 0x91, 0xD7, 0xC6, 0xD5, 0xF6, 0x4F, 0xFC, 0x15, 0xF7, 0xFE, 0x46,
+	0x4F, 0x03, 0xFF, 0x00, 0xD7, 0x95, 0xF7, 0xFE, 0x8C, 0x8E, 0xBE, 0x36, 0xA0, 0x02, 0x8A, 0x28,
+	0xA0, 0x00, 0x75, 0xAF, 0xAB, 0xFF, 0x00, 0xE0, 0x92, 0x3F, 0xF2, 0x5A, 0x7C, 0x4D, 0xFF, 0x00,
+	0x62, 0xA2, 0xFF, 0x00, 0xE9, 0x4C, 0x55, 0xF2, 0x80, 0xEB, 0x5F, 0x57, 0xFF, 0x00, 0xC1, 0x24,
+	0x7F, 0xE4, 0xB4, 0xF8, 0x9B, 0xFE, 0xC5, 0x45, 0xFF, 0x00, 0xD2, 0x98, 0xA8, 0x03, 0xD6, 0x7F,
+	0xE0, 0xAC, 0xA7, 0xFE, 0x31, 0xDF, 0x43, 0xFF, 0x00, 0xB1, 0xCA, 0x1F, 0xFD, 0x25, 0xB9, 0xAF,
+	0xCF, 0x7A, 0xFD, 0x08, 0xFF, 0x00, 0x82, 0xB2, 0xFF, 0x00, 0xC9, 0xBC, 0xE8, 0x7F, 0xF6, 0x38,
+	0xC3, 0xFF, 0x00, 0xA4, 0xB7, 0x35, 0xF9, 0xEF, 0x53, 0x1E, 0xA5, 0x4B, 0xA0, 0x51, 0x45, 0x15,
+	0x44, 0x85, 0x7B, 0xD7, 0xFC, 0x13, 0x63, 0xFE, 0x4E, 0xE7, 0x41, 0xFF, 0x00, 0xB0, 0x7E, 0xA1,
+	0xFF, 0x00, 0xA4, 0xEF, 0x5E, 0x0B, 0x5E, 0xF5, 0xFF, 0x00, 0x04, 0xD8, 0xFF, 0x00, 0x93, 0xB9,
+	0xD0, 0x7F, 0xEC, 0x1F, 0xA8, 0x7F, 0xE9, 0x3B, 0xD0, 0x07, 0xD8, 0x9F, 0xF0, 0x51, 0x43, 0xFF,
+	0x00, 0x18, 0x79, 0xE2, 0xDF, 0xFA, 0xE9, 0x63, 0xFF, 0x00, 0xA5, 0xB0, 0x57, 0xE6, 0x0D, 0x7E,
+	0x9F, 0x7F, 0xC1, 0x45, 0x3F, 0xE4, 0xCF, 0x7C, 0x59, 0xFF, 0x00, 0x5D, 0x2C, 0x7F, 0xF4, 0xB6,
+	0x0A, 0xFC, 0xC1, 0xA9, 0x8F, 0x5F, 0xEB, 0xA2, 0x2A, 0x5B, 0x2F, 0x40, 0xA2, 0x8A, 0x2A, 0x89,
+	0x0A, 0xF4, 0x4F, 0xD9, 0x2B, 0xFE, 0x4E, 0x73, 0xC0, 0x3F, 0xF6, 0x35, 0x5A, 0x7F, 0xE8, 0x42,
+	0xBC, 0xEE, 0xBD, 0x13, 0xF6, 0x4A, 0xFF, 0x00, 0x93, 0x9C, 0xF0, 0x0F, 0xFD, 0x8D, 0x56, 0x9F,
+	0xFA, 0x10, 0xA0, 0x0F, 0xD2, 0xCF, 0xDA, 0x90, 0xFF, 0x00, 0xC6, 0x34, 0x7C, 0x44, 0xFF, 0x00,
+	0xB1, 0x27, 0x53, 0xFF, 0x00, 0xD2, 0x59, 0x2B, 0xF1, 0xAE, 0xBF, 0x64, 0xFF, 0x00, 0x6A, 0x5F,
+	0xF9, 0x36, 0x8F, 0x88, 0x7F, 0xF6, 0x25, 0x6A, 0x7F, 0xFA, 0x4B, 0x25, 0x7E, 0x36, 0x57, 0xE7,
+	0xBC, 0x63, 0xFE, 0xF1, 0x49, 0x3F, 0xE5, 0x7F, 0x99, 0xFD, 0x25, 0xE0, 0x5B, 0x4B, 0x2C, 0xC6,
+	0x27, 0xFC, 0xF1, 0xFF, 0x00, 0xD2, 0x58, 0x51, 0x45, 0x15, 0xF1, 0xBA, 0x1F, 0xBB, 0x05, 0x7D,
+	0x0F, 0xFF, 0x00, 0x04, 0xBC, 0x3F, 0xF1, 0x97, 0x5A, 0x4F, 0xFD, 0x82, 0xAF, 0xBF, 0xF4, 0x51,
+	0xAF, 0x9E, 0x2B, 0xE8, 0x6F, 0xF8, 0x25, 0xF7, 0xFC, 0x9D, 0xCE, 0x93, 0x9F, 0xFA, 0x05, 0x5E,
+	0xFF, 0x00, 0xE8, 0xA3, 0x5E, 0x96, 0x51, 0xFF, 0x00, 0x23, 0x2A, 0x5F, 0xE2, 0x47, 0xC9, 0xF1,
+	0xD3, 0xFF, 0x00, 0x8C, 0x3F, 0x1B, 0xFF, 0x00, 0x5E, 0xD9, 0xF6, 0x97, 0xFC, 0x14, 0xA7, 0xFE,
+	0x4D, 0x27, 0x5C, 0xFF, 0x00, 0xAF, 0xCB, 0x1F, 0xFD, 0x28, 0x5A, 0xFC, 0xCB, 0xAF, 0xD3, 0x4F,
+	0xF8, 0x29, 0x4F, 0xFC, 0x9A, 0x4E, 0xB9, 0xFF, 0x00, 0x5F, 0x96, 0x3F, 0xFA, 0x50, 0xB5, 0xF9,
+	0x97, 0x5F, 0xB1, 0x1F, 0xC4, 0x61, 0x45, 0x14, 0x50, 0x01, 0x5F, 0x71, 0xFF, 0x00, 0xC1, 0x20,
+	0xFF, 0x00, 0xE4, 0x5B, 0xF1, 0xD7, 0xFD, 0x7F, 0xD8, 0xFF, 0x00, 0xE8, 0xAB, 0x8A, 0xF8, 0x72,
+	0xBE, 0xE3, 0xFF, 0x00, 0x82, 0x41, 0xFF, 0x00, 0xC8, 0xB7, 0xE3, 0xAF, 0xFA, 0xFF, 0x00, 0xB1,
+	0xFF, 0x00, 0xD1, 0x57, 0x14, 0x01, 0xE5, 0x9F, 0xF0, 0x72, 0x07, 0xEC, 0xF5, 0x69, 0xFB, 0x4B,
+	0x7E, 0xCD, 0x7E, 0x1E, 0xF0, 0x2C, 0x56, 0xD1, 0x8D, 0x62, 0xDE, 0xFA, 0xFA, 0xF3, 0xC3, 0x97,
+	0x1E, 0x5F, 0xCD, 0x1D, 0xE4, 0x70, 0xC6, 0x51, 0x3F, 0xED, 0xA6, 0x0C, 0x6D, 0xFE, 0xCC, 0x82,
+	0xBF, 0x99, 0x9B, 0xFD, 0x3E, 0xF3, 0x49, 0xBF, 0x9B, 0x4A, 0xD4, 0x6D, 0x9E, 0x1B, 0x8B, 0x59,
+	0x9A, 0x29, 0xE1, 0x93, 0xEF, 0x46, 0xEA, 0x70, 0x54, 0xFB, 0x82, 0x31, 0x5F, 0xD5, 0xD7, 0xFC,
+	0x16, 0x03, 0xFE, 0x40, 0x1E, 0x05, 0xFF, 0x00, 0xAF, 0xEB, 0xEF, 0xFD, 0x17, 0x1D, 0x7E, 0x01,
+	0xFF, 0x00, 0xC1, 0x59, 0x3F, 0x65, 0xF3, 0xE0, 0x5F, 0x1C, 0xC3, 0xFB, 0x44, 0x78, 0x43, 0x4F,
+	0xDB, 0xA4, 0xF8, 0x8A, 0xE1, 0x21, 0xD7, 0x04, 0x5F, 0x72, 0xDF, 0x51, 0xC6, 0x56, 0x53, 0xFE,
+	0xC4, 0xA3, 0x3F, 0xF6, 0xDA, 0x26, 0x1F, 0xC7, 0x59, 0xD4, 0xA7, 0xD4, 0xEA, 0xC3, 0xD4, 0xB3,
+	0xE5, 0x3E, 0x3B, 0xA2, 0x83, 0x81, 0xC2, 0xAE, 0xD1, 0xD8, 0x7A, 0x51, 0x5C, 0xE7, 0x70, 0x51,
+	0x45, 0x14, 0x00, 0x51, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14, 0x00, 0x57, 0xD0, 0x5F, 0xB1, 0x37,
+	0xFC, 0x82, 0xFC, 0x43, 0xFF, 0x00, 0x5F, 0x56, 0x9F, 0xCA, 0x4A, 0xF9, 0xF6, 0xBE, 0x82, 0xFD,
+	0x89, 0xBF, 0xE4, 0x17, 0xE2, 0x1F, 0xFA, 0xFA, 0xB4, 0xFE, 0x52, 0x56, 0x94, 0xFE, 0x23, 0x3A,
+	0xBF, 0x01, 0xEE, 0x54, 0x51, 0x45, 0x74, 0x1E, 0x78, 0x51, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14,
+	0x00, 0x51, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14, 0x00, 0x57, 0xD8, 0x5F, 0xB1, 0xD7, 0xFC, 0x90,
+	0xDB, 0x3F, 0xFA, 0xFC, 0xB8, 0xFF, 0x00, 0xD0, 0xCD, 0x7C, 0x7B, 0x5F, 0x61, 0x7E, 0xC7, 0x5F,
+	0xF2, 0x43, 0x6C, 0xFF, 0x00, 0xEB, 0xF2, 0xE3, 0xFF, 0x00, 0x43, 0x35, 0x51, 0x26, 0x47, 0xA9,
+	0x51, 0x45, 0x15, 0x44, 0x85, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40,
+	0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40,
+	0x17, 0xFC, 0x21, 0xFF, 0x00, 0x23, 0xF7, 0x85, 0xFF, 0x00, 0xEC, 0x70, 0xD2, 0x7F, 0xF4, 0xB6,
+	0xDE, 0xBE, 0xE9, 0xAF, 0x85, 0xBC, 0x21, 0xFF, 0x00, 0x23, 0xF7, 0x85, 0xFF, 0x00, 0xEC, 0x70,
+	0xD2, 0x7F, 0xF4, 0xB6, 0xDE, 0xBE, 0xE9, 0xA9, 0x90, 0x05, 0x14, 0x51, 0x52, 0x01, 0x45, 0x14,
+	0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x05, 0x8F, 0x09,
+	0xFF, 0x00, 0xC9, 0x60, 0xF0, 0x4F, 0xFD, 0x87, 0x27, 0xFF, 0x00, 0xD3, 0x65, 0xF5, 0x7D, 0x08,
+	0x3A, 0x57, 0xCF, 0x7E, 0x13, 0xFF, 0x00, 0x92, 0xC1, 0xE0, 0x9F, 0xFB, 0x0E, 0x4F, 0xFF, 0x00,
+	0xA6, 0xCB, 0xEA, 0xFA, 0x10, 0x74, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02,
+	0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x08, 0x66, 0x70, 0x81, 0x9A, 0x5C, 0x7D, 0xEC, 0x33,
+	0x16, 0xDA, 0xBB, 0x71, 0x9C, 0x9F, 0xA0, 0xAF, 0x23, 0xF8, 0x07, 0xF1, 0xBB, 0x4D, 0xF8, 0xEB,
+	0xF1, 0x7B, 0xE2, 0x04, 0x9A, 0x4B, 0x89, 0xB4, 0x8F, 0x0C, 0xDC, 0x5A, 0xE9, 0x1A, 0x5C, 0x8C,
+	0xBB, 0x84, 0xC0, 0xF9, 0x86, 0xE2, 0x45, 0x3D, 0xC3, 0xC8, 0x17, 0x3E, 0xAB, 0x14, 0x75, 0xCD,
+	0xFF, 0x00, 0xC1, 0x41, 0xFF, 0x00, 0x69, 0x39, 0x3E, 0x08, 0x7C, 0x28, 0x93, 0xC3, 0x3E, 0x19,
+	0xBD, 0xC7, 0x89, 0x7C, 0x4D, 0xBA, 0xDA, 0xC5, 0x61, 0x9B, 0x0D, 0x6D, 0x07, 0x49, 0x26, 0xFA,
+	0xE3, 0xE5, 0x1F, 0xED, 0x39, 0x3F, 0xC1, 0x5E, 0x71, 0xFF, 0x00, 0x04, 0x83, 0x20, 0xF8, 0x6F,
+	0xC7, 0x45, 0x5B, 0x3F, 0xE9, 0xF6, 0x3C, 0xFA, 0xFE, 0xEA, 0xE2, 0x80, 0x0F, 0xF8, 0x2B, 0xE9,
+	0xDD, 0xE1, 0xDF, 0x01, 0xB6, 0x4F, 0xFC, 0x7E, 0x5F, 0x7D, 0xEF, 0xFA, 0xE7, 0x1D, 0x7C, 0x39,
+	0x5F, 0x72, 0x7F, 0xC1, 0x60, 0x3F, 0xE4, 0x01, 0xE0, 0x5F, 0xFA, 0xFD, 0xBE, 0xFF, 0x00, 0xD0,
+	0x23, 0xAF, 0x86, 0xE8, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xAF, 0xD3, 0x4F, 0xF8, 0x26, 0xAF, 0xFC,
+	0x9A, 0x3E, 0x87, 0xFF, 0x00, 0x5F, 0xD7, 0xFF, 0x00, 0xFA, 0x52, 0xD5, 0xF9, 0x97, 0x5F, 0xA6,
+	0x9F, 0xF0, 0x4D, 0x5F, 0xF9, 0x34, 0x7D, 0x0F, 0xFE, 0xBF, 0xAF, 0xFF, 0x00, 0xF4, 0xA5, 0xA8,
+	0x03, 0xE3, 0x9F, 0xF8, 0x2A, 0x37, 0xFC, 0x9D, 0xDE, 0xA9, 0xFF, 0x00, 0x60, 0x9D, 0x3F, 0xFF,
+	0x00, 0x45, 0x0A, 0xF9, 0xE6, 0xBE, 0x86, 0xFF, 0x00, 0x82, 0xA3, 0x7F, 0xC9, 0xDD, 0xEA, 0x9F,
+	0xF6, 0x0A, 0xD3, 0xFF, 0x00, 0xF4, 0x50, 0xAF, 0x9E, 0x68, 0x3D, 0x2A, 0x6F, 0xDC, 0x41, 0x45,
+	0x14, 0x50, 0x56, 0x81, 0x5F, 0xB1, 0xFF, 0x00, 0xB3, 0x0F, 0xFC, 0x9B, 0x57, 0xC3, 0xCF, 0xFB,
+	0x11, 0xB4, 0x9F, 0xFD, 0x23, 0x8A, 0xBF, 0x1C, 0x2B, 0xF6, 0x3F, 0xF6, 0x61, 0xFF, 0x00, 0x93,
+	0x6A, 0xF8, 0x79, 0xFF, 0x00, 0x62, 0x36, 0x93, 0xFF, 0x00, 0xA4, 0x71, 0x50, 0x73, 0xE2, 0x6F,
+	0xCB, 0x13, 0xF3, 0x6B, 0xF6, 0xD3, 0xFF, 0x00, 0x93, 0xAE, 0xF1, 0xB7, 0xFD, 0x87, 0x0F, 0xFE,
+	0x82, 0xB5, 0xE5, 0x89, 0xF7, 0x07, 0xD2, 0xBD, 0x4F, 0xF6, 0xD3, 0xFF, 0x00, 0x93, 0xAE, 0xF1,
+	0xB7, 0xFD, 0x87, 0x0F, 0xFE, 0x82, 0xB5, 0xE5, 0x89, 0xF7, 0x07, 0xD2, 0x83, 0x8C, 0x5A, 0x28,
+	0xA2, 0x80, 0x0A, 0xFB, 0xD3, 0xFE, 0x09, 0x0B, 0xFF, 0x00, 0x24, 0xD7, 0xC6, 0x1F, 0xF6, 0x1C,
+	0x83, 0xFF, 0x00, 0x44, 0xD7, 0xC1, 0x75, 0xF7, 0xA7, 0xFC, 0x12, 0x17, 0xFE, 0x49, 0xAF, 0x8C,
+	0x3F, 0xEC, 0x39, 0x07, 0xFE, 0x89, 0xA0, 0x0F, 0x1E, 0xFF, 0x00, 0x82, 0xA8, 0xFF, 0x00, 0xC9,
+	0xCC, 0xDB, 0xFF, 0x00, 0xD8, 0xB1, 0x6B, 0xFF, 0x00, 0xA1, 0xCB, 0x5F, 0x36, 0x57, 0xD2, 0x7F,
+	0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B, 0x7F, 0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA,
+	0x00, 0x28, 0xA2, 0x8A, 0x00, 0x3B, 0x7E, 0x15, 0xF7, 0x47, 0xFC, 0x12, 0x03, 0xFE, 0x45, 0xCF,
+	0x1F, 0x7F, 0xD8, 0x42, 0xC3, 0xFF, 0x00, 0x45, 0xCD, 0x5F, 0x0B, 0xF6, 0xFC, 0x2B, 0xEE, 0x8F,
+	0xF8, 0x24, 0x07, 0xFC, 0x8B, 0x9E, 0x3E, 0xFF, 0x00, 0xB0, 0x85, 0x87, 0xFE, 0x8B, 0x9A, 0x80,
+	0x3C, 0xAB, 0xFE, 0x0A, 0xA3, 0xFF, 0x00, 0x27, 0x33, 0x6F, 0xFF, 0x00, 0x62, 0xC5, 0xAF, 0xFE,
+	0x87, 0x2D, 0x7C, 0xD9, 0x5F, 0x49, 0xFF, 0x00, 0xC1, 0x54, 0x7F, 0xE4, 0xE6, 0x6D, 0xFF, 0x00,
+	0xEC, 0x58, 0xB5, 0xFF, 0x00, 0xD0, 0xE5, 0xAF, 0x9B, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xED,
+	0xF8, 0x57, 0xDC, 0x9F, 0xF0, 0x48, 0x6F, 0xF9, 0x16, 0xFC, 0x7B, 0xFF, 0x00, 0x61, 0x0B, 0x1F,
+	0xFD, 0x17, 0x35, 0x7C, 0x37, 0xDB, 0xF0, 0xAF, 0xB9, 0x3F, 0xE0, 0x90, 0xDF, 0xF2, 0x2D, 0xF8,
+	0xF7, 0xFE, 0xC2, 0x16, 0x3F, 0xFA, 0x2E, 0x6A, 0x4F, 0x54, 0x07, 0xD9, 0xD0, 0x7F, 0xAA, 0x5A,
+	0x75, 0x32, 0x0F, 0xF5, 0x42, 0x9F, 0x4C, 0x02, 0x91, 0xC9, 0x54, 0x62, 0x07, 0x6A, 0x5A, 0x6C,
+	0x87, 0x6C, 0x6C, 0xDE, 0x8B, 0x40, 0x1F, 0x37, 0xFE, 0xDC, 0x1F, 0xB2, 0x37, 0x8D, 0xBF, 0x6A,
+	0x3D, 0x7F, 0x40, 0x6F, 0x07, 0x78, 0x9B, 0x4D, 0xD3, 0xC6, 0x87, 0x6F, 0x3F, 0xDA, 0x3F, 0xB5,
+	0x3C, 0xEC, 0x37, 0x9C, 0xDC, 0x6D, 0xD8, 0x08, 0xFE, 0x0E, 0xE0, 0xD7, 0x85, 0xFF, 0x00, 0xC3,
+	0xA3, 0xFE, 0x36, 0xFF, 0x00, 0xD1, 0x48, 0xF0, 0xAF, 0xFE, 0x4C, 0x7F, 0xF1, 0xAA, 0xFA, 0xA7,
+	0xE3, 0xF7, 0xED, 0x59, 0xF0, 0xBF, 0xF6, 0x66, 0xD6, 0xEC, 0x47, 0xC4, 0x78, 0x75, 0x49, 0x1B,
+	0x5A, 0xB6, 0x2D, 0x66, 0xDA, 0x65, 0x98, 0x90, 0xE2, 0x26, 0xC7, 0x27, 0x78, 0xFE, 0xFD, 0x70,
+	0x5F, 0xF0, 0xF5, 0x5F, 0xD9, 0x93, 0xFE, 0x7D, 0x3C, 0x55, 0xFF, 0x00, 0x82, 0x94, 0xFF, 0x00,
+	0xE3, 0xB4, 0x01, 0xE2, 0x7F, 0xF0, 0xE8, 0xFF, 0x00, 0x8D, 0xBF, 0xF4, 0x52, 0x3C, 0x2B, 0xFF,
+	0x00, 0x93, 0x1F, 0xFC, 0x6A, 0x8F, 0xF8, 0x74, 0x7F, 0xC6, 0xDF, 0xFA, 0x29, 0x1E, 0x15, 0xFF,
+	0x00, 0xC9, 0x8F, 0xFE, 0x35, 0x5E, 0xD9, 0xFF, 0x00, 0x0F, 0x55, 0xFD, 0x99, 0x3F, 0xE7, 0xD3,
+	0xC5, 0x5F, 0xF8, 0x29, 0x4F, 0xFE, 0x3B, 0x47, 0xFC, 0x3D, 0x57, 0xF6, 0x64, 0xFF, 0x00, 0x9F,
+	0x4F, 0x15, 0x7F, 0xE0, 0xA5, 0x3F, 0xF8, 0xED, 0x00, 0x78, 0x99, 0xFF, 0x00, 0x82, 0x48, 0x7C,
+	0x6D, 0x03, 0x27, 0xE2, 0x47, 0x85, 0x7F, 0xF2, 0x67, 0xFA, 0x45, 0x9F, 0xCB, 0x9A, 0xF6, 0x2F,
+	0xD8, 0xAB, 0xF6, 0x28, 0xF8, 0x83, 0xFB, 0x32, 0x78, 0xEF, 0x58, 0xF1, 0x77, 0x8B, 0x3C, 0x5B,
+	0xA4, 0xEA, 0x50, 0x5F, 0xE9, 0x1F, 0x64, 0x58, 0xF4, 0xFF, 0x00, 0x3B, 0x28, 0x7C, 0xC8, 0xE4,
+	0xC9, 0xF3, 0x13, 0x3D, 0xAA, 0xD1, 0xFF, 0x00, 0x82, 0xAA, 0xFE, 0xCC, 0x58, 0xF9, 0xAC, 0xFC,
+	0x52, 0x47, 0x71, 0xFD, 0x92, 0x9C, 0xFF, 0x00, 0xE4, 0x5A, 0xED, 0xFE, 0x05, 0x7E, 0xD9, 0x5F,
+	0x0A, 0x3F, 0x68, 0xBF, 0x12, 0x5F, 0x78, 0x4F, 0xE1, 0xDD, 0x9E, 0xAA, 0xB7, 0x56, 0x16, 0xA6,
+	0xE6, 0x6F, 0xED, 0x4B, 0x45, 0x8D, 0x76, 0xEF, 0x09, 0xC7, 0xCE, 0x7D, 0x7D, 0x28, 0x5B, 0x81,
+	0x47, 0xF6, 0xCB, 0xFD, 0x9D, 0x7C, 0x4B, 0xFB, 0x4C, 0x7C, 0x32, 0xD3, 0x7C, 0x0D, 0xE1, 0x0D,
+	0x62, 0xC7, 0x4F, 0x9E, 0xD3, 0x5A, 0x8A, 0xF8, 0xDC, 0x6A, 0x0D, 0x27, 0x93, 0xB1, 0x23, 0x95,
+	0x08, 0xC4, 0x7C, 0xE7, 0xE7, 0x1D, 0xFF, 0x00, 0x0A, 0xF9, 0xAB, 0xFE, 0x1D, 0x1F, 0xF1, 0xB7,
+	0xFE, 0x8A, 0x47, 0x85, 0x7F, 0xF2, 0x63, 0xFF, 0x00, 0x8D, 0x57, 0xD7, 0xBF, 0x1C, 0xBF, 0x68,
+	0x2F, 0x03, 0x7E, 0xCE, 0x7E, 0x14, 0xB4, 0xF1, 0xBF, 0x8F, 0xE3, 0xBE, 0x97, 0x4F, 0xBC, 0xBE,
+	0x16, 0x88, 0xDA, 0x7D, 0xBF, 0x9B, 0x27, 0x98, 0xC8, 0xEE, 0xBC, 0x6F, 0x07, 0x18, 0x8C, 0xF6,
+	0xC5, 0x79, 0x77, 0xFC, 0x3D, 0x57, 0xF6, 0x64, 0xFF, 0x00, 0x9F, 0x4F, 0x15, 0x7F, 0xE0, 0xA5,
+	0x3F, 0xF8, 0xED, 0x25, 0x6E, 0x81, 0xAF, 0x2A, 0x3C, 0x4F, 0xFE, 0x1D, 0x1F, 0xF1, 0xB7, 0xFE,
+	0x8A, 0x47, 0x85, 0x7F, 0xF2, 0x63, 0xFF, 0x00, 0x8D, 0x51, 0xFF, 0x00, 0x0E, 0x8F, 0xF8, 0xDB,
+	0xFF, 0x00, 0x45, 0x23, 0xC2, 0xBF, 0xF9, 0x31, 0xFF, 0x00, 0xC6, 0xAB, 0xDB, 0x3F, 0xE1, 0xEA,
+	0xBF, 0xB3, 0x27, 0xFC, 0xFA, 0x78, 0xAB, 0xFF, 0x00, 0x05, 0x29, 0xFF, 0x00, 0xC7, 0x68, 0xFF,
+	0x00, 0x87, 0xAA, 0xFE, 0xCC, 0x9F, 0xF3, 0xE9, 0xE2, 0xAF, 0xFC, 0x14, 0xA7, 0xFF, 0x00, 0x1D,
+	0xA6, 0x07, 0x89, 0xFF, 0x00, 0xC3, 0xA3, 0xFE, 0x36, 0xFF, 0x00, 0xD1, 0x48, 0xF0, 0xAF, 0xFE,
+	0x4C, 0x7F, 0xF1, 0xAA, 0xF4, 0x4F, 0xD9, 0x43, 0xFE, 0x09, 0xF5, 0xF1, 0x3B, 0xE0, 0x1F, 0xC6,
+	0xDD, 0x3F, 0xE2, 0x6F, 0x88, 0xBC, 0x6B, 0xA2, 0xDF, 0x5A, 0xD9, 0xDA, 0xDC, 0x47, 0x25, 0xAD,
+	0x8F, 0xDA, 0x37, 0xFE, 0xF2, 0x27, 0x4F, 0xF9, 0x6A, 0x95, 0xD4, 0x7F, 0xC3, 0xD5, 0x7F, 0x66,
+	0x4F, 0xF9, 0xF4, 0xF1, 0x57, 0xFE, 0x0A, 0x53, 0xFF, 0x00, 0x8E, 0xD7, 0x4D, 0xF0, 0x83, 0xF6,
+	0xF4, 0xF8, 0x25, 0xF1, 0xC3, 0xC7, 0xB6, 0xDF, 0x0E, 0x3C, 0x0B, 0x63, 0xAD, 0x2E, 0xA1, 0x79,
+	0x1B, 0xC9, 0x0F, 0xF6, 0x85, 0x8A, 0x47, 0x1E, 0xD4, 0x4D, 0xFF, 0x00, 0xF3, 0xD2, 0x80, 0x3A,
+	0x0F, 0xDA, 0x7B, 0xE1, 0x16, 0xB1, 0xF1, 0xDF, 0xE0, 0x66, 0xB1, 0xF0, 0xB7, 0xC3, 0x57, 0xD6,
+	0xF6, 0xB7, 0x7A, 0xA3, 0x42, 0x21, 0xB8, 0xB9, 0x2E, 0x22, 0x46, 0x49, 0xE3, 0x94, 0xEE, 0x09,
+	0xF3, 0x74, 0x53, 0xE9, 0x5F, 0x26, 0x9F, 0xF8, 0x24, 0x87, 0xC6, 0xD6, 0x3B, 0x87, 0xC4, 0xAF,
+	0x0A, 0x1C, 0xF7, 0x1F, 0x68, 0xE7, 0xF3, 0x8C, 0xFF, 0x00, 0x33, 0x5F, 0x67, 0x7C, 0x58, 0xF8,
+	0xAF, 0xE1, 0xCF, 0x82, 0xBE, 0x01, 0xBC, 0xF8, 0x9B, 0xE2, 0xE4, 0x9E, 0x4D, 0x37, 0x4F, 0x92,
+	0x31, 0x78, 0xB6, 0x71, 0x89, 0x24, 0x50, 0xF2, 0x2C, 0x58, 0x55, 0xDC, 0xBF, 0xC4, 0xE3, 0xA0,
+	0xAF, 0x1D, 0x5F, 0xF8, 0x2A, 0xAF, 0xEC, 0xC6, 0x54, 0x11, 0x69, 0xE2, 0xAF, 0xC7, 0x49, 0x4F,
+	0xFE, 0x3B, 0x47, 0x57, 0xEA, 0x1F, 0x65, 0x1E, 0x27, 0xFF, 0x00, 0x0E, 0x8F, 0xF8, 0xDB, 0xFF,
+	0x00, 0x45, 0x23, 0xC2, 0xBF, 0xF9, 0x31, 0xFF, 0x00, 0xC6, 0xA8, 0xFF, 0x00, 0x87, 0x47, 0xFC,
+	0x6D, 0xFF, 0x00, 0xA2, 0x91, 0xE1, 0x5F, 0xFC, 0x98, 0xFF, 0x00, 0xE3, 0x55, 0xED, 0x9F, 0xF0,
+	0xF5, 0x5F, 0xD9, 0x93, 0xFE, 0x7D, 0x3C, 0x55, 0xFF, 0x00, 0x82, 0x94, 0xFF, 0x00, 0xE3, 0xB4,
+	0x7F, 0xC3, 0xD5, 0x7F, 0x66, 0x4F, 0xF9, 0xF4, 0xF1, 0x57, 0xFE, 0x0A, 0x53, 0xFF, 0x00, 0x8E,
+	0xD0, 0x07, 0x89, 0xFF, 0x00, 0xC3, 0xA3, 0xFE, 0x36, 0xFF, 0x00, 0xD1, 0x48, 0xF0, 0xAF, 0xFE,
+	0x4C, 0x7F, 0xF1, 0xAA, 0xE9, 0x3E, 0x0A, 0xFF, 0x00, 0xC1, 0x33, 0x7E, 0x2E, 0x7C, 0x32, 0xF8,
+	0xBD, 0xE1, 0xCF, 0x88, 0x3A, 0x9F, 0x8F, 0xFC, 0x3F, 0x3D, 0xBE, 0x8B, 0xAB, 0x45, 0x77, 0x2D,
+	0xBD, 0xAF, 0xDA, 0x77, 0xB8, 0x47, 0x53, 0xC6, 0xF4, 0xC7, 0x7E, 0xDC, 0x57, 0xA4, 0x7F, 0xC3,
+	0xD5, 0x7F, 0x66, 0x4F, 0xF9, 0xF4, 0xF1, 0x57, 0xFE, 0x0A, 0x53, 0xFF, 0x00, 0x8E, 0xD6, 0xA7,
+	0x81, 0xFF, 0x00, 0xE0, 0xA3, 0xDF, 0xB3, 0xE7, 0xC4, 0x4F, 0x19, 0x69, 0x9E, 0x05, 0xF0, 0xED,
+	0x87, 0x88, 0x16, 0xF3, 0x58, 0xBA, 0x4B, 0x6B, 0x53, 0x75, 0xA7, 0xA4, 0x71, 0x96, 0x76, 0x2B,
+	0xC9, 0xF3, 0x3D, 0xA8, 0x03, 0xD3, 0x3E, 0x36, 0xF8, 0x37, 0x50, 0xF8, 0x8B, 0xF0, 0x73, 0xC5,
+	0xDE, 0x00, 0xD0, 0xDA, 0x14, 0xBC, 0xD6, 0xB4, 0x0B, 0xCB, 0x0B, 0x77, 0x95, 0x8A, 0xA2, 0xC9,
+	0x34, 0x0F, 0x1A, 0x97, 0xC2, 0x93, 0xB7, 0x24, 0x74, 0x5A, 0xF8, 0x1C, 0x7F, 0xC1, 0x22, 0x3F,
+	0x69, 0x9C, 0x29, 0x6F, 0x14, 0x78, 0x27, 0x27, 0xAE, 0xDD, 0x4E, 0xEC, 0x7F, 0xED, 0xA5, 0x7E,
+	0x83, 0xFC, 0x43, 0xF1, 0xB5, 0x87, 0xC3, 0xAF, 0x02, 0x6B, 0x9F, 0x10, 0xF5, 0xB8, 0x64, 0x92,
+	0xD7, 0x41, 0xD3, 0x67, 0xBE, 0xBE, 0x86, 0xDD, 0x54, 0xB7, 0x97, 0x0C, 0x6D, 0x23, 0xED, 0x0C,
+	0xCA, 0x32, 0x55, 0x7D, 0x7F, 0x1A, 0xF9, 0xAD, 0x7F, 0xE0, 0xB0, 0x9F, 0xB3, 0xDA, 0xFC, 0xAD,
+	0xE0, 0x0F, 0x1A, 0x63, 0x18, 0xC7, 0xD8, 0x6D, 0x72, 0x3F, 0xF2, 0x6A, 0xBC, 0x0C, 0xEB, 0x0B,
+	0x94, 0xD7, 0xA8, 0x9E, 0x32, 0x69, 0x3E, 0x97, 0x76, 0xEA, 0x7E, 0x85, 0xC1, 0x39, 0xA7, 0x1C,
+	0x65, 0xF8, 0x5A, 0xB0, 0xC8, 0x69, 0xB9, 0x41, 0xB4, 0xE5, 0x68, 0xF3, 0x6A, 0x96, 0x87, 0x86,
+	0x9F, 0xF8, 0x24, 0x37, 0xED, 0x30, 0x3F, 0xE6, 0x68, 0xF0, 0x57, 0xFE, 0x0D, 0x2E, 0xFF, 0x00,
+	0xF9, 0x12, 0x8F, 0xF8, 0x74, 0x3F, 0xED, 0x31, 0xFF, 0x00, 0x43, 0x3F, 0x82, 0xFF, 0x00, 0xF0,
+	0x69, 0x77, 0xFF, 0x00, 0xC8, 0x95, 0xEE, 0x7F, 0xF0, 0xF8, 0x6F, 0xD9, 0xEB, 0xB7, 0xC3, 0xEF,
+	0x19, 0xFF, 0x00, 0xE0, 0x0D, 0xAF, 0xFF, 0x00, 0x25, 0xD1, 0xFF, 0x00, 0x0F, 0x86, 0xFD, 0x9E,
+	0xBF, 0xE8, 0x9F, 0x78, 0xCF, 0xFF, 0x00, 0x00, 0x6D, 0x7F, 0xF9, 0x2E, 0xBC, 0x8F, 0xEC, 0xFE,
+	0x15, 0xFE, 0x75, 0xFF, 0x00, 0x81, 0x33, 0xED, 0xBF, 0xD6, 0x2F, 0x19, 0x7A, 0xE1, 0xDF, 0xFE,
+	0x0B, 0x47, 0x86, 0x7F, 0xC3, 0xA1, 0xBF, 0x69, 0x8C, 0xE3, 0xFE, 0x12, 0x8F, 0x05, 0x7F, 0xE0,
+	0xD2, 0xEF, 0xFF, 0x00, 0x91, 0x2B, 0xD5, 0x3F, 0x63, 0x2F, 0xF8, 0x27, 0xDF, 0xC6, 0xCF, 0xD9,
+	0xEB, 0xE3, 0xC5, 0xAF, 0xC4, 0xEF, 0x1C, 0xEB, 0xBE, 0x19, 0x9E, 0xC6, 0xD6, 0xC6, 0xE2, 0x29,
+	0x23, 0xD2, 0xEF, 0x27, 0x92, 0x67, 0x2E, 0xA1, 0x07, 0xDE, 0x81, 0x38, 0x18, 0xF5, 0xAD, 0xF1,
+	0xFF, 0x00, 0x05, 0x84, 0xFD, 0x9E, 0x0B, 0x64, 0xF8, 0x07, 0xC6, 0x83, 0x8F, 0xE1, 0xB1, 0xB4,
+	0xFF, 0x00, 0xE4, 0xAA, 0xEC, 0x7E, 0x01, 0x7F, 0xC1, 0x44, 0x3E, 0x0F, 0xFE, 0xD1, 0x3F, 0x13,
+	0x20, 0xF8, 0x67, 0xE0, 0xEF, 0x0A, 0x78, 0x9A, 0xCE, 0xFA, 0xE2, 0x19, 0x24, 0x86, 0x7D, 0x5A,
+	0xD6, 0xD9, 0x61, 0xF9, 0x14, 0x3B, 0x7F, 0xAB, 0x9D, 0xCE, 0x70, 0x7D, 0x2B, 0xA3, 0x07, 0x81,
+	0xE1, 0xBA, 0x78, 0x88, 0xCA, 0x84, 0xD7, 0x35, 0xD5, 0xBD, 0xE3, 0xCD, 0xCE, 0xB3, 0xCF, 0x15,
+	0x71, 0x19, 0x5D, 0x6A, 0x78, 0xFA, 0x12, 0x54, 0x65, 0x16, 0xA6, 0xDD, 0x34, 0x95, 0xBD, 0x7A,
+	0x1D, 0xEF, 0xED, 0x59, 0xF0, 0x6B, 0x5F, 0xF8, 0xFF, 0x00, 0xF0, 0x43, 0x50, 0xF8, 0x67, 0xE1,
+	0xCD, 0x4E, 0xD6, 0xCA, 0xF2, 0xEE, 0x7B, 0x69, 0x23, 0x9E, 0xF3, 0x7F, 0x96, 0x3C, 0xB9, 0x63,
+	0x90, 0xE7, 0x67, 0x3F, 0xC3, 0x5F, 0x24, 0xAF, 0xFC, 0x12, 0x3F, 0xE3, 0x66, 0xD1, 0xB7, 0xE2,
+	0x4F, 0x85, 0x31, 0xDB, 0x6F, 0xDA, 0x31, 0xFF, 0x00, 0xA2, 0x8F, 0xF3, 0x35, 0xF6, 0x97, 0xC5,
+	0x4F, 0x8A, 0xBA, 0x2F, 0xC2, 0x4F, 0x0C, 0xFF, 0x00, 0xC2, 0x55, 0xE2, 0x1B, 0x0B, 0xAB, 0x88,
+	0x5A, 0xE5, 0x2D, 0xC2, 0xD8, 0xAA, 0xB3, 0x16, 0x6E, 0x9F, 0x79, 0x94, 0x63, 0xF1, 0xAF, 0x37,
+	0x5F, 0xDB, 0xE7, 0xE1, 0x6B, 0x28, 0x66, 0xF0, 0xAF, 0x88, 0x33, 0x8F, 0xF9, 0xF7, 0xB7, 0xE3,
+	0xFF, 0x00, 0x23, 0xD6, 0x79, 0xE7, 0x1F, 0x70, 0x8F, 0x0D, 0xE3, 0x3E, 0xAB, 0x99, 0x62, 0xE1,
+	0x4A, 0xA5, 0x93, 0xE5, 0x93, 0x77, 0xB3, 0xD9, 0xEC, 0x7E, 0x57, 0x84, 0xC9, 0xF3, 0x4C, 0x75,
+	0x2F, 0x69, 0x87, 0xA4, 0xE5, 0x1D, 0xAE, 0x91, 0xF3, 0xAF, 0xFC, 0x3A, 0x3F, 0xE3, 0x6F, 0xFD,
+	0x14, 0x8F, 0x0A, 0xFF, 0x00, 0xE4, 0xC7, 0xFF, 0x00, 0x1A, 0xA3, 0xFE, 0x1D, 0x1F, 0xF1, 0xB7,
+	0xFE, 0x8A, 0x47, 0x85, 0x7F, 0xF2, 0x63, 0xFF, 0x00, 0x8D, 0x57, 0xD1, 0x83, 0xF6, 0xFA, 0xF8,
+	0x59, 0x8E, 0x7C, 0x2B, 0xE2, 0x1F, 0xFB, 0xF1, 0x07, 0xFF, 0x00, 0x1F, 0xA3, 0xFE, 0x1B, 0xEB,
+	0xE1, 0x5F, 0xFD, 0x0A, 0x9E, 0x21, 0xFF, 0x00, 0xBF, 0x30, 0x7F, 0xF1, 0xFA, 0xF1, 0xFF, 0x00,
+	0xE2, 0x2F, 0xF8, 0x73, 0xFF, 0x00, 0x43, 0x1A, 0x7F, 0x7B, 0xFF, 0x00, 0x23, 0xAB, 0xFD, 0x59,
+	0xCF, 0xBF, 0xE8, 0x1E, 0x5F, 0x71, 0xF3, 0x9F, 0xFC, 0x3A, 0x3F, 0xE3, 0x6F, 0xFD, 0x14, 0x8F,
+	0x0A, 0xFF, 0x00, 0xE4, 0xC7, 0xFF, 0x00, 0x1A, 0xAF, 0xA1, 0xBF, 0x61, 0xFF, 0x00, 0xD9, 0x57,
+	0xC6, 0x3F, 0xB2, 0xDE, 0x97, 0xE2, 0x0B, 0x1F, 0x17, 0xEB, 0xFA, 0x6E, 0xA0, 0xDA, 0xC5, 0xD5,
+	0xAB, 0xC0, 0xDA, 0x5F, 0x99, 0x85, 0xD8, 0xAE, 0xA7, 0x3E, 0x68, 0x1F, 0xDF, 0xEC, 0x00, 0xA9,
+	0xBF, 0xE1, 0xBE, 0x7E, 0x15, 0xF7, 0xF0, 0xAF, 0x88, 0x7F, 0xEF, 0xC4, 0x1F, 0xFC, 0x7E, 0xBB,
+	0x2F, 0x83, 0x7F, 0x1F, 0xFC, 0x31, 0xF1, 0xB2, 0x7D, 0x41, 0x7C, 0x35, 0xA6, 0xDF, 0x5A, 0x9D,
+	0x3F, 0xCB, 0x6B, 0x85, 0xBE, 0x8E, 0x30, 0xCD, 0xBC, 0xB8, 0x5C, 0x6C, 0x91, 0xFB, 0x21, 0xAF,
+	0x4B, 0x29, 0xF1, 0x1B, 0x82, 0xF3, 0xCC, 0x74, 0x70, 0x98, 0x1C, 0x6C, 0x2A, 0x54, 0x96, 0xD1,
+	0x4D, 0xDD, 0xFE, 0x07, 0x3E, 0x27, 0x23, 0xCD, 0xB0, 0x74, 0x5D, 0x5A, 0xD4, 0x65, 0x18, 0xAE,
+	0xAD, 0x1C, 0x37, 0xED, 0xBB, 0xFB, 0x29, 0xF8, 0xC7, 0xF6, 0xA5, 0xD3, 0xBC, 0x3F, 0xA6, 0xF8,
+	0x4B, 0xC4, 0x1A, 0x6E, 0x9D, 0xFD, 0x8F, 0x75, 0x71, 0x2C, 0xED, 0xA9, 0x6F, 0xF9, 0x84, 0x9B,
+	0x00, 0xC6, 0xC4, 0x3F, 0xDC, 0xAF, 0x96, 0x7E, 0x29, 0xFF, 0x00, 0xC1, 0x12, 0x7C, 0x79, 0xF1,
+	0x7B, 0xE1, 0xD6, 0xAD, 0xF0, 0xC3, 0xC7, 0x1E, 0x3F, 0xF0, 0xBC, 0xDA, 0x6E, 0xAF, 0x66, 0xD6,
+	0xD3, 0x2A, 0x8B, 0x82, 0xD1, 0x31, 0x1B, 0x96, 0x45, 0xFD, 0xD7, 0xFA, 0xC8, 0xDF, 0x12, 0xA7,
+	0xFB, 0x48, 0xB5, 0xF6, 0xBF, 0xC7, 0xDF, 0xDA, 0x73, 0xE1, 0xE7, 0xEC, 0xD7, 0x67, 0xA5, 0xEA,
+	0x1F, 0x10, 0xE1, 0xD4, 0x9D, 0x35, 0x79, 0x25, 0x8E, 0xCF, 0xFB, 0x3A, 0xDD, 0x64, 0x3B, 0xA3,
+	0x50, 0x5B, 0x21, 0x9C, 0x7F, 0x7C, 0x76, 0xAF, 0x35, 0xFF, 0x00, 0x87, 0xAA, 0x7E, 0xCC, 0x83,
+	0x8F, 0xB2, 0x78, 0xA7, 0xFF, 0x00, 0x05, 0x31, 0xFF, 0x00, 0xF1, 0xDA, 0xFB, 0x7B, 0xF3, 0x44,
+	0xF2, 0xD5, 0xE3, 0xB1, 0xFC, 0xAD, 0xFE, 0xDA, 0x3F, 0xB2, 0x57, 0xC5, 0x6F, 0xD8, 0x6F, 0xF6,
+	0x8F, 0xF1, 0x2F, 0xEC, 0xD7, 0xF1, 0x8F, 0x4F, 0x54, 0xD5, 0xBC, 0x3B, 0x7C, 0xDE, 0x5D, 0xDD,
+	0xA9, 0x3E, 0x56, 0xA3, 0x66, 0x53, 0x7C, 0x37, 0x56, 0xD9, 0x00, 0xB2, 0x48, 0xA4, 0x3E, 0xF2,
+	0x01, 0x88, 0x36, 0xCE, 0xD5, 0xE5, 0xAC, 0x19, 0x5B, 0x0C, 0x54, 0x9E, 0xFB, 0x7A, 0x7E, 0x15,
+	0xFB, 0xD1, 0xFF, 0x00, 0x07, 0x00, 0xF8, 0x67, 0xF6, 0x6E, 0xFF, 0x00, 0x82, 0x8B, 0xFC, 0x10,
+	0xB3, 0xF8, 0xA7, 0xF0, 0x6B, 0x48, 0xD6, 0xE1, 0xF8, 0xB1, 0xE0, 0x35, 0x66, 0xD1, 0x64, 0xB8,
+	0xD2, 0xD5, 0x06, 0xB1, 0xA6, 0xEE, 0xF3, 0x26, 0xB3, 0x72, 0xB2, 0x33, 0xB1, 0x56, 0x6D, 0xF1,
+	0x60, 0x70, 0xE6, 0x58, 0xFF, 0x00, 0xE5, 0xE2, 0xBF, 0x1B, 0x53, 0xF6, 0x15, 0xFD, 0xB6, 0x59,
+	0x15, 0xA0, 0xFD, 0x8E, 0xBE, 0x2A, 0x79, 0x64, 0x65, 0x31, 0xE0, 0x1D, 0x48, 0xF1, 0xDB, 0x91,
+	0x6E, 0x73, 0xF9, 0x9A, 0xE7, 0x9C, 0x79, 0x64, 0x7A, 0x54, 0xEB, 0x46, 0x51, 0xD4, 0xF2, 0x9A,
+	0x2B, 0xD5, 0xBF, 0xE1, 0x84, 0xFF, 0x00, 0x6D, 0xEF, 0xFA, 0x33, 0x9F, 0x8A, 0x9F, 0xF8, 0x6F,
+	0xF5, 0x3F, 0xFE, 0x46, 0xA3, 0xFE, 0x18, 0x4F, 0xF6, 0xDE, 0xFF, 0x00, 0xA3, 0x39, 0xF8, 0xA9,
+	0xFF, 0x00, 0x86, 0xFF, 0x00, 0x53, 0xFF, 0x00, 0xE4, 0x6A, 0x83, 0x4E, 0x68, 0xF7, 0x3C, 0xA6,
+	0x8A, 0xF5, 0x6F, 0xF8, 0x61, 0x3F, 0xDB, 0x7B, 0xFE, 0x8C, 0xE7, 0xE2, 0xA7, 0xFE, 0x1B, 0xFD,
+	0x4F, 0xFF, 0x00, 0x91, 0xA8, 0xFF, 0x00, 0x86, 0x13, 0xFD, 0xB7, 0xBF, 0xE8, 0xCE, 0x7E, 0x2A,
+	0x7F, 0xE1, 0xBF, 0xD4, 0xFF, 0x00, 0xF9, 0x1A, 0x80, 0xE6, 0x8F, 0x73, 0xCA, 0x68, 0xAF, 0x56,
+	0xFF, 0x00, 0x86, 0x13, 0xFD, 0xB7, 0xBF, 0xE8, 0xCE, 0x7E, 0x2A, 0x7F, 0xE1, 0xBF, 0xD4, 0xFF,
+	0x00, 0xF9, 0x1A, 0x8F, 0xF8, 0x61, 0x3F, 0xDB, 0x7B, 0xFE, 0x8C, 0xE7, 0xE2, 0xA7, 0xFE, 0x1B,
+	0xFD, 0x4F, 0xFF, 0x00, 0x91, 0xA8, 0x0E, 0x68, 0xF7, 0x3C, 0xA6, 0xBE, 0x82, 0xFD, 0x89, 0xBF,
+	0xE4, 0x17, 0xE2, 0x1F, 0xFA, 0xFA, 0xB4, 0xFE, 0x52, 0x57, 0x27, 0xFF, 0x00, 0x0C, 0x27, 0xFB,
+	0x6F, 0x7F, 0xD1, 0x9C, 0xFC, 0x54, 0xFF, 0x00, 0xC3, 0x7F, 0xA9, 0xFF, 0x00, 0xF2, 0x35, 0x7B,
+	0xAF, 0xEC, 0x77, 0xFB, 0x19, 0x7E, 0xD7, 0x9A, 0x26, 0x99, 0xAE, 0x47, 0xAF, 0x7E, 0xCA, 0xDF,
+	0x12, 0x2C, 0xDA, 0x69, 0xED, 0xF6, 0x0B, 0xDF, 0x03, 0xEA, 0x08, 0xC7, 0x06, 0x4F, 0xBB, 0xFB,
+	0xB1, 0xC7, 0xE0, 0x2B, 0x4A, 0x7B, 0xDC, 0xCE, 0xAC, 0x97, 0xB3, 0x3A, 0x9A, 0x2B, 0xBC, 0x1F,
+	0xB2, 0xA7, 0xED, 0x40, 0xC3, 0x3F, 0xF0, 0xCE, 0x1F, 0x10, 0x3F, 0x1F, 0x07, 0x5E, 0xFF, 0x00,
+	0xF1, 0x14, 0xBF, 0xF0, 0xCA, 0x5F, 0xB5, 0x0F, 0xFD, 0x1B, 0x87, 0x8F, 0xFF, 0x00, 0xF0, 0x8D,
+	0xBD, 0xFF, 0x00, 0xE2, 0x2B, 0xA0, 0xE1, 0xB9, 0xC1, 0x51, 0x5D, 0xEF, 0xFC, 0x32, 0x97, 0xED,
+	0x43, 0xFF, 0x00, 0x46, 0xE1, 0xE3, 0xFF, 0x00, 0xFC, 0x23, 0x6F, 0x7F, 0xF8, 0x8A, 0x3F, 0xE1,
+	0x94, 0xBF, 0x6A, 0x1F, 0xFA, 0x37, 0x0F, 0x1F, 0xFF, 0x00, 0xE1, 0x1B, 0x7B, 0xFF, 0x00, 0xC4,
+	0x50, 0x17, 0x38, 0x2A, 0x2B, 0xBD, 0xFF, 0x00, 0x86, 0x52, 0xFD, 0xA8, 0x7F, 0xE8, 0xDC, 0x3C,
+	0x7F, 0xFF, 0x00, 0x84, 0x6D, 0xEF, 0xFF, 0x00, 0x11, 0x5C, 0x27, 0xC4, 0x2B, 0x5B, 0x9F, 0x84,
+	0xDE, 0x22, 0x6F, 0x07, 0xFC, 0x57, 0x8A, 0x4F, 0x0A, 0xEA, 0xCB, 0x02, 0xCC, 0xFA, 0x6E, 0xBF,
+	0x19, 0xB5, 0xB8, 0x48, 0x98, 0x65, 0x5F, 0xCA, 0x9F, 0xE6, 0x01, 0x87, 0xF1, 0x2F, 0xAD, 0x1D,
+	0x2E, 0x34, 0xAE, 0x36, 0x8A, 0xC6, 0x3F, 0x12, 0x3E, 0x1E, 0x83, 0x86, 0xF1, 0xDE, 0x8A, 0xBE,
+	0xDF, 0xDA, 0xD1, 0x9C, 0x7E, 0x27, 0xAD, 0x27, 0xFC, 0x2C, 0x9F, 0x87, 0x9F, 0xF4, 0x3E, 0xE8,
+	0xBF, 0xF8, 0x34, 0x8A, 0x8E, 0x68, 0xF7, 0x2B, 0xD9, 0xC8, 0xDA, 0xA2, 0xB1, 0x7F, 0xE1, 0x64,
+	0xFC, 0x3C, 0xFF, 0x00, 0xA1, 0xF7, 0x45, 0xFF, 0x00, 0xC1, 0xA4, 0x54, 0x7F, 0xC2, 0xC9, 0xF8,
+	0x79, 0xFF, 0x00, 0x43, 0xEE, 0x8B, 0xFF, 0x00, 0x83, 0x48, 0xA8, 0xE6, 0x8F, 0x70, 0xF6, 0x72,
+	0x36, 0xAB, 0xEC, 0x2F, 0xD8, 0xEB, 0xFE, 0x48, 0x6D, 0x9F, 0xFD, 0x7E, 0x5C, 0x7F, 0xE8, 0x66,
+	0xBE, 0x23, 0xFF, 0x00, 0x85, 0x93, 0xF0, 0xF3, 0xFE, 0x87, 0xDD, 0x17, 0xFF, 0x00, 0x06, 0x91,
+	0x57, 0xD6, 0x1F, 0xB2, 0x7F, 0xC7, 0xFF, 0x00, 0x81, 0x7A, 0x07, 0xC1, 0x9B, 0x3B, 0x4D, 0x63,
+	0xE3, 0x47, 0x83, 0xED, 0x6E, 0x23, 0xBA, 0xB8, 0x26, 0x1B, 0xAF, 0x12, 0x5A, 0xC6, 0xE0, 0x17,
+	0x3C, 0x8C, 0xBE, 0x45, 0x0A, 0x51, 0xEE, 0x43, 0x8C, 0x8F, 0x7E, 0xA2, 0xB8, 0xBF, 0xF8, 0x69,
+	0x2F, 0xD9, 0xD0, 0x70, 0xBF, 0x1F, 0xFC, 0x1A, 0x47, 0xAB, 0x78, 0xA2, 0xCC, 0x9F, 0xFD, 0x19,
+	0x47, 0xFC, 0x34, 0x9F, 0xEC, 0xEB, 0xFF, 0x00, 0x45, 0xFB, 0xC1, 0x7F, 0xF8, 0x54, 0x59, 0x7F,
+	0xF1, 0xCA, 0xBE, 0x68, 0xF7, 0x27, 0x96, 0x5D, 0x8E, 0xD2, 0x8A, 0xE2, 0xFF, 0x00, 0xE1, 0xA4,
+	0xFF, 0x00, 0x67, 0x5F, 0xFA, 0x2F, 0xDE, 0x0B, 0xFF, 0x00, 0xC2, 0xA2, 0xCB, 0xFF, 0x00, 0x8E,
+	0x51, 0xFF, 0x00, 0x0D, 0x27, 0xFB, 0x3A, 0xFF, 0x00, 0xD1, 0x7E, 0xF0, 0x5F, 0xFE, 0x15, 0x16,
+	0x5F, 0xFC, 0x72, 0x8E, 0x68, 0xF7, 0x0E, 0x59, 0x76, 0x3B, 0x4A, 0x2B, 0x8B, 0xFF, 0x00, 0x86,
+	0x93, 0xFD, 0x9D, 0x7F, 0xE8, 0xBF, 0x78, 0x2F, 0xFF, 0x00, 0x0A, 0x8B, 0x2F, 0xFE, 0x39, 0x47,
+	0xFC, 0x34, 0x9F, 0xEC, 0xEB, 0xFF, 0x00, 0x45, 0xFB, 0xC1, 0x7F, 0xF8, 0x54, 0x59, 0x7F, 0xF1,
+	0xCA, 0x39, 0xA3, 0xDC, 0x39, 0x65, 0xD8, 0xED, 0x28, 0xAE, 0x2F, 0xFE, 0x1A, 0x4F, 0xF6, 0x75,
+	0xFF, 0x00, 0xA2, 0xFD, 0xE0, 0xBF, 0xFC, 0x2A, 0x2C, 0xBF, 0xF8, 0xE5, 0x1F, 0xF0, 0xD2, 0x7F,
+	0xB3, 0xAF, 0xFD, 0x17, 0xEF, 0x05, 0xFF, 0x00, 0xE1, 0x51, 0x65, 0xFF, 0x00, 0xC7, 0x28, 0xE6,
+	0x8F, 0x70, 0xE5, 0x97, 0x63, 0xB4, 0xA2, 0xB8, 0xBF, 0xF8, 0x69, 0x3F, 0xD9, 0xD7, 0xFE, 0x8B,
+	0xF7, 0x82, 0xFF, 0x00, 0xF0, 0xA8, 0xB2, 0xFF, 0x00, 0xE3, 0x94, 0x7F, 0xC3, 0x49, 0xFE, 0xCE,
+	0xBF, 0xF4, 0x5F, 0xBC, 0x17, 0xFF, 0x00, 0x85, 0x45, 0x97, 0xFF, 0x00, 0x1C, 0xA3, 0x9A, 0x3D,
+	0xC3, 0x96, 0x5D, 0x8E, 0xD2, 0x8A, 0xE2, 0xFF, 0x00, 0xE1, 0xA4, 0xFF, 0x00, 0x67, 0x5F, 0xFA,
+	0x2F, 0xDE, 0x0B, 0xFF, 0x00, 0xC2, 0xA2, 0xCB, 0xFF, 0x00, 0x8E, 0x51, 0xFF, 0x00, 0x0D, 0x27,
+	0xFB, 0x3A, 0xFF, 0x00, 0xD1, 0x7E, 0xF0, 0x5F, 0xFE, 0x15, 0x16, 0x5F, 0xFC, 0x72, 0x8E, 0x68,
+	0xF7, 0x0E, 0x59, 0x76, 0x3B, 0x4A, 0x2B, 0x8B, 0xFF, 0x00, 0x86, 0x93, 0xFD, 0x9D, 0x7F, 0xE8,
+	0xBF, 0x78, 0x2F, 0xFF, 0x00, 0x0A, 0x8B, 0x2F, 0xFE, 0x39, 0x47, 0xFC, 0x34, 0x9F, 0xEC, 0xEB,
+	0xFF, 0x00, 0x45, 0xFB, 0xC1, 0x7F, 0xF8, 0x54, 0x59, 0x7F, 0xF1, 0xCA, 0x39, 0xA3, 0xDC, 0x39,
+	0x65, 0xD8, 0xED, 0x28, 0xAE, 0x2F, 0xFE, 0x1A, 0x4F, 0xF6, 0x75, 0xFF, 0x00, 0xA2, 0xFD, 0xE0,
+	0xBF, 0xFC, 0x2A, 0x2C, 0xBF, 0xF8, 0xE5, 0x1F, 0xF0, 0xD2, 0x7F, 0xB3, 0xAF, 0xFD, 0x17, 0xEF,
+	0x05, 0xFF, 0x00, 0xE1, 0x51, 0x65, 0xFF, 0x00, 0xC7, 0x28, 0xE6, 0x8F, 0x70, 0xE5, 0x97, 0x63,
+	0xD0, 0xFC, 0x21, 0xFF, 0x00, 0x23, 0xF7, 0x85, 0xFF, 0x00, 0xEC, 0x70, 0xD2, 0x7F, 0xF4, 0xB6,
+	0xDE, 0xBE, 0xE9, 0xAF, 0xCE, 0x1F, 0x0A, 0x7E, 0xD2, 0xDF, 0xB3, 0x9D, 0xBF, 0x8F, 0x3C, 0x37,
+	0x71, 0x37, 0xED, 0x03, 0xE0, 0xB1, 0x1C, 0x1E, 0x2C, 0xD2, 0x5E, 0x59, 0x24, 0xF1, 0x65, 0x92,
+	0xC7, 0x1A, 0xAD, 0xED, 0xBB, 0xE4, 0xFC, 0xFE, 0xF5, 0xF6, 0x87, 0xFC, 0x36, 0xEF, 0xEC, 0x65,
+	0xFC, 0x3F, 0xB5, 0xD7, 0xC3, 0x22, 0x3B, 0x1F, 0xF8, 0x4E, 0xF4, 0xFE, 0x7F, 0xF2, 0x2D, 0x4C,
+	0xA5, 0x17, 0x2B, 0x07, 0x2C, 0xBB, 0x1E, 0x9D, 0x45, 0x79, 0x8F, 0xFC, 0x36, 0xEF, 0xEC, 0x67,
+	0xFF, 0x00, 0x47, 0x73, 0xF0, 0xCF, 0xFF, 0x00, 0x0B, 0xCD, 0x3F, 0xFF, 0x00, 0x8E, 0xD1, 0xFF,
+	0x00, 0x0D, 0xBB, 0xFB, 0x19, 0xFF, 0x00, 0xD1, 0xDC, 0xFC, 0x33, 0xFF, 0x00, 0xC2, 0xF3, 0x4F,
+	0xFF, 0x00, 0xE3, 0xB4, 0xB9, 0xA3, 0xDC, 0x39, 0x65, 0xD8, 0xF4, 0xEA, 0x2B, 0xCC, 0x7F, 0xE1,
+	0xB7, 0x7F, 0x63, 0x3F, 0xFA, 0x3B, 0x9F, 0x86, 0x7F, 0xF8, 0x5E, 0x69, 0xFF, 0x00, 0xFC, 0x76,
+	0x8F, 0xF8, 0x6D, 0xDF, 0xD8, 0xCF, 0xFE, 0x8E, 0xE7, 0xE1, 0x9F, 0xFE, 0x17, 0x9A, 0x7F, 0xFF,
+	0x00, 0x1D, 0xA3, 0x9A, 0x3D, 0xC3, 0x96, 0x5D, 0x8F, 0x4E, 0xA2, 0xBC, 0xF7, 0xC3, 0xBF, 0xB5,
+	0xCF, 0xEC, 0xA1, 0xE2, 0x9F, 0x10, 0x5A, 0xF8, 0x7B, 0xC2, 0xFF, 0x00, 0xB4, 0xCF, 0xC3, 0xAD,
+	0x4F, 0x50, 0xBE, 0xB9, 0x48, 0xEC, 0xF4, 0xFB, 0x1F, 0x1A, 0xD8, 0x4F, 0x71, 0x3B, 0x95, 0xE9,
+	0x1A, 0x2C, 0x9B, 0xCB, 0x7F, 0xBB, 0x5E, 0xA2, 0x3C, 0x31, 0xE2, 0x48, 0xC7, 0x96, 0xDA, 0x06,
+	0xA0, 0x0A, 0xF0, 0x43, 0xDB, 0xCA, 0x5B, 0xF1, 0x3D, 0xCD, 0x00, 0xE3, 0xCB, 0xB9, 0x42, 0x8A,
+	0xD0, 0xFF, 0x00, 0x84, 0x6F, 0xC4, 0x7F, 0xF4, 0x01, 0xBE, 0xFF, 0x00, 0xC0, 0x59, 0x68, 0xFF,
+	0x00, 0x84, 0x6F, 0xC4, 0x7F, 0xF4, 0x01, 0xBE, 0xFF, 0x00, 0xC0, 0x59, 0x68, 0x24, 0xCF, 0xA2,
+	0xB4, 0x3F, 0xE1, 0x1B, 0xF1, 0x1F, 0xFD, 0x00, 0x6F, 0xBF, 0xF0, 0x16, 0x5A, 0x3F, 0xE1, 0x1B,
+	0xF1, 0x1F, 0xFD, 0x00, 0x6F, 0xBF, 0xF0, 0x16, 0x5A, 0x00, 0xAF, 0xE1, 0x3F, 0xF9, 0x2C, 0x1E,
+	0x09, 0xFF, 0x00, 0xB0, 0xE4, 0xFF, 0x00, 0xFA, 0x6C, 0xBE, 0xAF, 0xA1, 0x07, 0x4A, 0xF0, 0x5F,
+	0x0E, 0x78, 0x77, 0xC4, 0x36, 0xDF, 0x14, 0xFC, 0x1F, 0x7D, 0x3E, 0x87, 0x79, 0x1C, 0x30, 0xEB,
+	0x17, 0x1F, 0x68, 0x95, 0xAD, 0x5F, 0x68, 0xCE, 0x9D, 0x7C, 0x17, 0x3F, 0x8B, 0xA5, 0x7B, 0xD2,
+	0x96, 0x2A, 0x0B, 0x1E, 0x7B, 0xF1, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00,
+	0x28, 0xA2, 0x8A, 0x00, 0x2B, 0x2F, 0x5E, 0xBF, 0xB7, 0xD2, 0xA0, 0x6D, 0x42, 0x49, 0x36, 0xF9,
+	0x7F, 0x74, 0xAE, 0x77, 0x16, 0x3F, 0xC2, 0x07, 0xF1, 0x12, 0x7A, 0x2F, 0xF1, 0xBE, 0x07, 0x6A,
+	0xD4, 0xAF, 0x9D, 0x3E, 0x2A, 0xFE, 0xDF, 0xFF, 0x00, 0xB3, 0xDF, 0xC3, 0xFF, 0x00, 0x8A, 0x77,
+	0xDE, 0x04, 0xF1, 0x35, 0xCE, 0xAF, 0x74, 0xDA, 0x1C, 0xE6, 0x3B, 0xA3, 0xA6, 0xDA, 0xA3, 0x42,
+	0x6E, 0xC1, 0x2A, 0x46, 0xFF, 0x00, 0x30, 0x65, 0xE3, 0x20, 0xA0, 0x5C, 0x03, 0xBC, 0x37, 0x74,
+	0x4A, 0x00, 0xF3, 0x8F, 0x8F, 0x7F, 0xB0, 0x27, 0xED, 0x13, 0xFB, 0x44, 0xFC, 0x51, 0xBE, 0xF8,
+	0x8F, 0xE2, 0x1F, 0x88, 0x7E, 0x1D, 0xB5, 0x37, 0x32, 0x2C, 0x76, 0x16, 0x13, 0x4D, 0x3B, 0x9D,
+	0x3E, 0xD4, 0x0F, 0x92, 0x00, 0xC1, 0x30, 0xCF, 0x8C, 0x3B, 0x11, 0xC1, 0x39, 0xAF, 0x56, 0xFD,
+	0x87, 0xBF, 0x65, 0x6F, 0x18, 0xFE, 0xCB, 0xBA, 0x57, 0x88, 0x2C, 0xFC, 0x5F, 0xAF, 0xE9, 0xBA,
+	0x83, 0x6B, 0x37, 0x56, 0xB2, 0x40, 0xDA, 0x5F, 0x99, 0x85, 0xD8, 0xAE, 0xA7, 0x77, 0x9B, 0xDF,
+	0xE7, 0xEC, 0x31, 0x58, 0x91, 0xFF, 0x00, 0xC1, 0x54, 0x7F, 0x66, 0x38, 0x51, 0x62, 0x16, 0x1E,
+	0x29, 0x4D, 0xAB, 0x8D, 0xA3, 0x47, 0x45, 0xDB, 0xED, 0x8F, 0x37, 0x8F, 0xA5, 0x7A, 0x67, 0xEC,
+	0xFF, 0x00, 0xFB, 0x4F, 0xFC, 0x39, 0xFD, 0xA5, 0x2C, 0xF5, 0x4B, 0xFF, 0x00, 0x00, 0x41, 0xA8,
+	0x2C, 0x3A, 0x4C, 0xD1, 0xA5, 0xE1, 0xD4, 0xAD, 0x7C, 0xB6, 0xF9, 0xD1, 0xD8, 0x63, 0x93, 0xFD,
+	0xDF, 0x5A, 0x00, 0xE3, 0x7F, 0x6D, 0xDF, 0xD9, 0x4F, 0xC6, 0x3F, 0xB5, 0x2E, 0x9D, 0xE1, 0xFD,
+	0x33, 0xC2, 0x5E, 0x20, 0xD3, 0x34, 0xE3, 0xA3, 0xDD, 0x5C, 0x4B, 0x33, 0x6A, 0x5B, 0xFE, 0x61,
+	0x26, 0xC0, 0x31, 0xB1, 0x0F, 0xF7, 0x2B, 0xE7, 0xA5, 0xFF, 0x00, 0x82, 0x47, 0x7C, 0x6D, 0x0A,
+	0x07, 0xFC, 0x2C, 0x8F, 0x0A, 0xFF, 0x00, 0xE4, 0xC7, 0xFF, 0x00, 0x1A, 0xAF, 0xAF, 0x7E, 0x33,
+	0x7C, 0x7F, 0xF0, 0xAF, 0xC1, 0x19, 0xEC, 0xA3, 0xF1, 0x2E, 0x97, 0x7D, 0x70, 0xDA, 0x8F, 0x9C,
+	0x6D, 0xFE, 0xC6, 0xAA, 0xD8, 0xF2, 0xF6, 0x93, 0x9D, 0xCC, 0xA3, 0xF8, 0xFD, 0x6B, 0x8D, 0x1F,
+	0xB7, 0xBF, 0xC2, 0xC5, 0x1B, 0x47, 0x86, 0x3C, 0x41, 0xEF, 0x8B, 0x7B, 0x7C, 0x1F, 0xFC, 0x8F,
+	0x5F, 0x0F, 0x9B, 0x78, 0x91, 0xC1, 0x59, 0x1E, 0x3A, 0x58, 0x3C, 0x76, 0x36, 0x14, 0xEA, 0x47,
+	0x78, 0xC9, 0xB4, 0xF6, 0xBF, 0x63, 0xD6, 0xC3, 0x64, 0x79, 0xB6, 0x32, 0x8A, 0xAB, 0x46, 0x8C,
+	0xA5, 0x17, 0xB3, 0x48, 0xF9, 0xD3, 0xFE, 0x1D, 0x1F, 0xF1, 0xB7, 0xFE, 0x8A, 0x47, 0x85, 0x7F,
+	0xF2, 0x63, 0xFF, 0x00, 0x8D, 0x51, 0xFF, 0x00, 0x0E, 0x8F, 0xF8, 0xDB, 0xFF, 0x00, 0x45, 0x23,
+	0xC2, 0xBF, 0xF9, 0x31, 0xFF, 0x00, 0xC6, 0xAB, 0xE8, 0xC1, 0xFB, 0x7C, 0xFC, 0x2B, 0x03, 0xFE,
+	0x45, 0x5F, 0x10, 0xFF, 0x00, 0xDF, 0x88, 0x3F, 0xF8, 0xFD, 0x1F, 0xF0, 0xDF, 0x5F, 0x0A, 0xFF,
+	0x00, 0xE8, 0x54, 0xF1, 0x0F, 0xFD, 0xF9, 0x83, 0xFF, 0x00, 0x8F, 0xD7, 0x99, 0xFF, 0x00, 0x11,
+	0x7F, 0xC3, 0x9F, 0xFA, 0x18, 0xD3, 0xFB, 0xDF, 0xF9, 0x1B, 0x7F, 0xAB, 0x39, 0xF7, 0xFD, 0x03,
+	0xCB, 0xEE, 0x3E, 0x73, 0xFF, 0x00, 0x87, 0x47, 0xFC, 0x6D, 0xFF, 0x00, 0xA2, 0x91, 0xE1, 0x5F,
+	0xFC, 0x98, 0xFF, 0x00, 0xE3, 0x55, 0xF5, 0xB7, 0xEC, 0x9F, 0xF0, 0x57, 0x5B, 0xF8, 0x05, 0xF0,
+	0x4B, 0x4E, 0xF8, 0x63, 0xE2, 0x7D, 0x56, 0xD6, 0xEA, 0xF2, 0xCE, 0xE2, 0xE1, 0xA4, 0x9E, 0xC4,
+	0x10, 0x84, 0x4B, 0x33, 0x38, 0xC6, 0x40, 0x3D, 0xFD, 0x05, 0x72, 0xA7, 0xF6, 0xFA, 0xF8, 0x59,
+	0x9E, 0x3C, 0x2D, 0xE2, 0x2F, 0xFB, 0xF3, 0x07, 0xFF, 0x00, 0x1F, 0xAF, 0x4A, 0xF8, 0x51, 0xF1,
+	0x4F, 0x41, 0xF8, 0xBF, 0xE1, 0x71, 0xE2, 0xCF, 0x0F, 0xD9, 0xDD, 0x43, 0x03, 0x5C, 0x34, 0x5B,
+	0x2F, 0x10, 0x2B, 0x6E, 0x53, 0x83, 0xD0, 0x91, 0xF9, 0x13, 0xF5, 0x35, 0xEC, 0xE4, 0x7E, 0x20,
+	0x70, 0x8F, 0x12, 0x63, 0x1E, 0x17, 0x2C, 0xC5, 0xC2, 0xAD, 0x44, 0xAF, 0x64, 0xFA, 0x2D, 0xDE,
+	0xC7, 0x2E, 0x2F, 0x27, 0xCD, 0x30, 0x34, 0xD5, 0x4A, 0xF4, 0x9C, 0x57, 0x76, 0xAC, 0x7C, 0xBD,
+	0xFB, 0x62, 0x7F, 0xC1, 0x3E, 0x3E, 0x35, 0xFE, 0xD0, 0xDF, 0x1D, 0x2F, 0x3E, 0x28, 0x78, 0x3F,
+	0xC5, 0x1E, 0x19, 0xB4, 0xB1, 0xB8, 0xB3, 0x82, 0x38, 0xED, 0xF5, 0x2B, 0xCB, 0x98, 0xE6, 0x56,
+	0x8D, 0x36, 0x93, 0xFB, 0xA8, 0x0F, 0x07, 0xEA, 0x6B, 0xCB, 0x93, 0xFE, 0x09, 0x07, 0xFB, 0x4A,
+	0x14, 0x52, 0x3C, 0x6B, 0xE0, 0x7E, 0x9F, 0xC3, 0xAA, 0xDE, 0x11, 0xFA, 0xDA, 0x67, 0xF3, 0xE6,
+	0xBE, 0xA1, 0xF8, 0xE9, 0xFF, 0x00, 0x05, 0x07, 0xF8, 0x2F, 0xFB, 0x3C, 0xFC, 0x42, 0xBA, 0xF8,
+	0x67, 0xE3, 0xAF, 0x0F, 0x78, 0x96, 0xE3, 0x50, 0xB7, 0x82, 0x29, 0x1E, 0x4D, 0x32, 0xCA, 0x19,
+	0x21, 0xDB, 0x22, 0xEE, 0x41, 0xF3, 0xCE, 0xBC, 0xE3, 0xD8, 0x57, 0x1C, 0x3F, 0xE0, 0xAF, 0x9F,
+	0xB3, 0x79, 0x50, 0x7F, 0xE1, 0x09, 0xF1, 0xC0, 0xFA, 0xE9, 0x76, 0x79, 0xFF, 0x00, 0xD2, 0xCA,
+	0xFB, 0x23, 0x96, 0x35, 0x2B, 0xF2, 0xD9, 0x1E, 0x21, 0xFF, 0x00, 0x0E, 0x83, 0xFD, 0xA5, 0x3F,
+	0xE8, 0x75, 0xF0, 0x47, 0xFE, 0x0D, 0x2E, 0xFF, 0x00, 0xF9, 0x0E, 0x8F, 0xF8, 0x74, 0x1F, 0xED,
+	0x29, 0xFF, 0x00, 0x43, 0xAF, 0x82, 0x3F, 0xF0, 0x69, 0x77, 0xFF, 0x00, 0xC8, 0x75, 0xED, 0xFF,
+	0x00, 0xF0, 0xF7, 0xCF, 0xD9, 0xBF, 0xFE, 0x84, 0xAF, 0x1C, 0x7F, 0xE0, 0xAE, 0xCF, 0xFF, 0x00,
+	0x93, 0x29, 0x7F, 0xE1, 0xEF, 0x9F, 0xB3, 0x77, 0xFD, 0x09, 0x5E, 0x38, 0xFF, 0x00, 0xC1, 0x5D,
+	0x9F, 0xFF, 0x00, 0x26, 0x50, 0x57, 0xB4, 0xC4, 0x1E, 0x1C, 0x7F, 0xE0, 0x90, 0x9F, 0xB4, 0xA8,
+	0xFF, 0x00, 0x99, 0xD7, 0xC1, 0x3F, 0xF8, 0x34, 0xBB, 0xFF, 0x00, 0xE4, 0x3A, 0xFB, 0xEB, 0xE0,
+	0xE7, 0x84, 0x35, 0x3F, 0x87, 0xBF, 0x08, 0xBC, 0x2B, 0xE0, 0x1D, 0x6A, 0x78, 0x24, 0xBC, 0xD0,
+	0xFC, 0x37, 0x63, 0xA7, 0xDD, 0xC9, 0x6A, 0xC5, 0xA3, 0x79, 0x61, 0xB7, 0x48, 0xD8, 0xA1, 0x60,
+	0xA4, 0xA9, 0x2A, 0x70, 0x48, 0x07, 0x1D, 0x87, 0x4A, 0xF9, 0xD4, 0xFF, 0x00, 0xC1, 0x5F, 0x3F,
+	0x66, 0xFF, 0x00, 0xFA, 0x12, 0xBC, 0x6F, 0xFF, 0x00, 0x82, 0xBB, 0x4F, 0xFE, 0x4C, 0xAF, 0xA6,
+	0x3C, 0x07, 0xE3, 0x0D, 0x37, 0xE2, 0x17, 0x81, 0xB4, 0x5F, 0x1F, 0x68, 0xD0, 0x4F, 0x1D, 0x9E,
+	0xB9, 0xA4, 0xDB, 0xEA, 0x16, 0xB1, 0xDD, 0x28, 0x59, 0x12, 0x39, 0xA2, 0x59, 0x14, 0x38, 0x52,
+	0xC0, 0x30, 0x0C, 0x32, 0x01, 0x23, 0x3D, 0x09, 0xEB, 0x41, 0x8D, 0x49, 0x54, 0x71, 0x5C, 0xC7,
+	0xC8, 0x7F, 0x1F, 0xFF, 0x00, 0xE0, 0x9B, 0x3F, 0x14, 0xBE, 0x2C, 0xFC, 0x64, 0xF1, 0x0F, 0xC4,
+	0xBD, 0x1F, 0xC7, 0x3E, 0x1F, 0xB4, 0xB5, 0xD5, 0x35, 0x33, 0x75, 0x0D, 0xBD, 0xD7, 0x9F, 0xB8,
+	0x00, 0xBC, 0x67, 0x08, 0x46, 0x70, 0x7B, 0x71, 0x5C, 0x7F, 0xFC, 0x3A, 0x3F, 0xE3, 0x6F, 0xFD,
+	0x14, 0x8F, 0x0A, 0xFF, 0x00, 0xE4, 0xC7, 0xFF, 0x00, 0x1A, 0xAF, 0xA2, 0x7E, 0x24, 0xFF, 0x00,
+	0xC1, 0x44, 0xBE, 0x01, 0x7C, 0x2B, 0xF1, 0xD6, 0xA7, 0xF0, 0xF3, 0xC5, 0x36, 0x7E, 0x20, 0x37,
+	0xFA, 0x5D, 0xD0, 0x82, 0xEC, 0xDA, 0xE9, 0xA8, 0xEA, 0x5B, 0xB1, 0x07, 0x78, 0xC8, 0xE3, 0x8A,
+	0xC2, 0x1F, 0xF0, 0x55, 0x5F, 0xD9, 0x90, 0x8C, 0x9B, 0x4F, 0x15, 0x7F, 0xE0, 0xA5, 0x3F, 0xF8,
+	0xED, 0x06, 0x67, 0x89, 0xFF, 0x00, 0xC3, 0xA3, 0xFE, 0x36, 0xFF, 0x00, 0xD1, 0x48, 0xF0, 0xAF,
+	0xFE, 0x4C, 0x7F, 0xF1, 0xAA, 0x3F, 0xE1, 0xD1, 0xFF, 0x00, 0x1B, 0x7F, 0xE8, 0xA4, 0x78, 0x57,
+	0xFF, 0x00, 0x26, 0x3F, 0xF8, 0xD5, 0x7B, 0x67, 0xFC, 0x3D, 0x57, 0xF6, 0x64, 0xFF, 0x00, 0x9F,
+	0x4F, 0x15, 0x7F, 0xE0, 0xA5, 0x3F, 0xF8, 0xED, 0x1F, 0xF0, 0xF5, 0x5F, 0xD9, 0x93, 0xFE, 0x7D,
+	0x3C, 0x55, 0xFF, 0x00, 0x82, 0x94, 0xFF, 0x00, 0xE3, 0xB4, 0x01, 0xE2, 0x7F, 0xF0, 0xE8, 0xFF,
+	0x00, 0x8D, 0xBF, 0xF4, 0x52, 0x3C, 0x2B, 0xFF, 0x00, 0x93, 0x1F, 0xFC, 0x6A, 0xBE, 0x8C, 0xFD,
+	0x87, 0x3F, 0x66, 0x9F, 0x15, 0xFE, 0xCC, 0x3A, 0x07, 0x88, 0xBC, 0x2B, 0xE2, 0xED, 0x7B, 0x4F,
+	0xD4, 0x2E, 0x35, 0x0B, 0xCB, 0x7B, 0xA5, 0x93, 0x4D, 0xF3, 0x76, 0xAA, 0xED, 0x64, 0xC1, 0xDE,
+	0x07, 0x3F, 0x2F, 0x60, 0x3F, 0x0A, 0xE7, 0xFF, 0x00, 0xE1, 0xEA, 0xBF, 0xB3, 0x27, 0xFC, 0xFA,
+	0x78, 0xAB, 0xFF, 0x00, 0x05, 0x29, 0xFF, 0x00, 0xC7, 0x6B, 0xD2, 0xBF, 0x67, 0x9F, 0xDA, 0x2F,
+	0xC0, 0x5F, 0xB4, 0x6C, 0x7A, 0xDF, 0x8A, 0xBC, 0x03, 0x1D, 0xF4, 0x76, 0xB6, 0x2D, 0x6D, 0x6B,
+	0x21, 0xD4, 0x2D, 0xFC, 0xA6, 0xDD, 0x87, 0x6F, 0x5F, 0xF6, 0xBD, 0x68, 0x03, 0xC7, 0x3F, 0x6C,
+	0x1F, 0xD8, 0x63, 0xE2, 0x27, 0xED, 0x2D, 0xF1, 0x78, 0x78, 0xEB, 0xC2, 0x5E, 0x2F, 0xD1, 0xEC,
+	0x6D, 0xAD, 0x74, 0xA8, 0x6C, 0x5A, 0x2D, 0x53, 0xCF, 0xDE, 0x59, 0x49, 0x7E, 0x36, 0x82, 0xBF,
+	0xC7, 0xE9, 0x5E, 0x59, 0xFF, 0x00, 0x0E, 0x8F, 0xF8, 0xDB, 0xFF, 0x00, 0x45, 0x23, 0xC2, 0xBF,
+	0xF9, 0x31, 0xFF, 0x00, 0xC6, 0xAB, 0xE9, 0x7F, 0x8D, 0x1F, 0xB6, 0xB7, 0xC1, 0xCF, 0xD9, 0xCB,
+	0xC7, 0x72, 0xF8, 0x1F, 0xE2, 0x15, 0xBE, 0xB0, 0xD7, 0xD7, 0x10, 0xC7, 0x78, 0xAD, 0xA6, 0xE9,
+	0xE1, 0xD7, 0x63, 0x82, 0xBC, 0x93, 0x20, 0xFF, 0x00, 0x9E, 0x75, 0xCA, 0x7F, 0xC3, 0xD5, 0x7F,
+	0x66, 0x4F, 0xF9, 0xF4, 0xF1, 0x57, 0xFE, 0x0A, 0x53, 0xFF, 0x00, 0x8E, 0xD0, 0x07, 0x89, 0xFF,
+	0x00, 0xC3, 0xA3, 0xFE, 0x36, 0xFF, 0x00, 0xD1, 0x48, 0xF0, 0xAF, 0xFE, 0x4C, 0x7F, 0xF1, 0xAA,
+	0x3F, 0xE1, 0xD1, 0xFF, 0x00, 0x1B, 0x7F, 0xE8, 0xA4, 0x78, 0x57, 0xFF, 0x00, 0x26, 0x3F, 0xF8,
+	0xD5, 0x7B, 0x67, 0xFC, 0x3D, 0x57, 0xF6, 0x64, 0xFF, 0x00, 0x9F, 0x4F, 0x15, 0x7F, 0xE0, 0xA5,
+	0x3F, 0xF8, 0xED, 0x1F, 0xF0, 0xF5, 0x5F, 0xD9, 0x93, 0xFE, 0x7D, 0x3C, 0x55, 0xFF, 0x00, 0x82,
+	0x94, 0xFF, 0x00, 0xE3, 0xB4, 0x01, 0xE2, 0x4D, 0xFF, 0x00, 0x04, 0x91, 0xF8, 0xD8, 0x8B, 0xB8,
+	0xFC, 0x48, 0xF0, 0xAF, 0xE1, 0xF6, 0xAF, 0xFD, 0x96, 0x2C, 0xD7, 0xD1, 0x3F, 0xB0, 0xB7, 0xEC,
+	0xAD, 0xE3, 0x1F, 0xD9, 0x73, 0x46, 0xF1, 0x25, 0x87, 0x8B, 0xFC, 0x47, 0xA7, 0xEA, 0x4F, 0xAC,
+	0x5D, 0xDB, 0x3C, 0x2F, 0xA7, 0xF9, 0x9B, 0x50, 0x47, 0xE6, 0x29, 0x07, 0x7A, 0x83, 0xFC, 0x42,
+	0xB1, 0x17, 0xFE, 0x0A, 0xA5, 0xFB, 0x31, 0xC8, 0xC2, 0x33, 0x65, 0xE2, 0x96, 0xDC, 0xD8, 0xC1,
+	0xD2, 0x50, 0xFF, 0x00, 0xED, 0x5A, 0xF4, 0xDF, 0xD9, 0xE7, 0xF6, 0xA1, 0xF8, 0x73, 0xFB, 0x4A,
+	0xE9, 0x9A, 0xAE, 0xA3, 0xF0, 0xF2, 0x2D, 0x42, 0x38, 0x74, 0x99, 0x61, 0x8E, 0xEB, 0xFB, 0x4A,
+	0x15, 0x89, 0xB7, 0x48, 0x18, 0x8C, 0x61, 0x8F, 0xF7, 0x4F, 0xA5, 0x00, 0x78, 0xC7, 0xED, 0x83,
+	0xFB, 0x0C, 0x7C, 0x44, 0xFD, 0xA5, 0xBE, 0x2F, 0x0F, 0x1D, 0x78, 0x4B, 0xC5, 0xFA, 0x3D, 0x8D,
+	0xB5, 0xAE, 0x95, 0x0D, 0x8B, 0x45, 0xAA, 0x79, 0xFB, 0xCB, 0x29, 0x2F, 0xC6, 0xD0, 0x57, 0xF8,
+	0xFD, 0x2B, 0xCB, 0x3F, 0xE1, 0xD1, 0xFF, 0x00, 0x1B, 0x7F, 0xE8, 0xA4, 0x78, 0x57, 0xFF, 0x00,
+	0x26, 0x3F, 0xF8, 0xD5, 0x7D, 0x2F, 0xF1, 0xA3, 0xF6, 0xD6, 0xF8, 0x39, 0xFB, 0x39, 0x78, 0xEE,
+	0x5F, 0x03, 0xFC, 0x42, 0xB7, 0xD6, 0x1A, 0xFA, 0xE2, 0x18, 0xEF, 0x15, 0xB4, 0xDD, 0x3C, 0x3A,
+	0xEC, 0x70, 0x57, 0x92, 0x64, 0x1F, 0xF3, 0xCE, 0xB9, 0x4F, 0xF8, 0x7A, 0xAF, 0xEC, 0xC9, 0xFF,
+	0x00, 0x3E, 0x9E, 0x2A, 0xFF, 0x00, 0xC1, 0x4A, 0x7F, 0xF1, 0xDA, 0x00, 0xF1, 0x3F, 0xF8, 0x74,
+	0x7F, 0xC6, 0xDF, 0xFA, 0x29, 0x1E, 0x15, 0xFF, 0x00, 0xC9, 0x8F, 0xFE, 0x35, 0x47, 0xFC, 0x3A,
+	0x3F, 0xE3, 0x6F, 0xFD, 0x14, 0x8F, 0x0A, 0xFF, 0x00, 0xE4, 0xC7, 0xFF, 0x00, 0x1A, 0xAF, 0x6C,
+	0xFF, 0x00, 0x87, 0xAA, 0xFE, 0xCC, 0x9F, 0xF3, 0xE9, 0xE2, 0xAF, 0xFC, 0x14, 0xA7, 0xFF, 0x00,
+	0x1D, 0xA3, 0xFE, 0x1E, 0xAB, 0xFB, 0x32, 0x7F, 0xCF, 0xA7, 0x8A, 0xBF, 0xF0, 0x52, 0x9F, 0xFC,
+	0x76, 0x80, 0x3C, 0x49, 0xBF, 0xE0, 0x92, 0x3F, 0x1B, 0x11, 0x77, 0x1F, 0x89, 0x1E, 0x15, 0xFC,
+	0x3E, 0xD5, 0xFF, 0x00, 0xB2, 0xC5, 0x9A, 0xFA, 0x07, 0xF6, 0x25, 0xFD, 0x95, 0x3C, 0x65, 0xFB,
+	0x2F, 0x68, 0x9E, 0x24, 0xD3, 0xFC, 0x63, 0xE2, 0x3D, 0x37, 0x52, 0xFE, 0xD8, 0xBA, 0xB7, 0x78,
+	0xDE, 0xC0, 0x49, 0xB5, 0x3C, 0xB1, 0x22, 0xE0, 0xEF, 0x50, 0x7F, 0x8B, 0xD6, 0xB3, 0x17, 0xFE,
+	0x0A, 0xA5, 0xFB, 0x31, 0xC8, 0xC2, 0x33, 0x65, 0xE2, 0x96, 0xDC, 0xD8, 0xC1, 0xD2, 0x50, 0xFF,
+	0x00, 0xED, 0x5A, 0xF4, 0x5F, 0x80, 0xBF, 0xB5, 0x1F, 0xC3, 0x9F, 0xDA, 0x4F, 0x4F, 0xD4, 0xAF,
+	0xFE, 0x1D, 0xDB, 0xEA, 0x09, 0x16, 0x92, 0xD1, 0xA5, 0xE1, 0xD4, 0xED, 0xD6, 0x36, 0x1E, 0x60,
+	0x27, 0x80, 0x18, 0xFF, 0x00, 0x77, 0xD2, 0x9A, 0xDC, 0x1E, 0xC7, 0xA7, 0x58, 0x1C, 0xC2, 0x58,
+	0x0E, 0x0B, 0x64, 0x73, 0xEC, 0x3A, 0x7B, 0x54, 0xD5, 0x0D, 0x86, 0x44, 0x18, 0x27, 0x3F, 0x37,
+	0xDE, 0xF5, 0xE0, 0x73, 0xD4, 0xFF, 0x00, 0x4A, 0x9A, 0xA6, 0x3B, 0x00, 0x50, 0xD9, 0xDA, 0x71,
+	0x45, 0x07, 0xA5, 0x30, 0x3E, 0x13, 0xFF, 0x00, 0x82, 0xBE, 0x02, 0x3C, 0x45, 0xE0, 0x60, 0x4F,
+	0xFC, 0xB8, 0xDF, 0x7F, 0xE8, 0x71, 0xD7, 0xC6, 0xF5, 0xF6, 0x4F, 0xFC, 0x15, 0xF7, 0xFE, 0x46,
+	0x4F, 0x03, 0xFF, 0x00, 0xD7, 0x95, 0xF7, 0xFE, 0x8C, 0x8E, 0xBE, 0x36, 0xA0, 0x02, 0x8A, 0x28,
+	0xA0, 0x00, 0x75, 0xAF, 0xAB, 0xFF, 0x00, 0xE0, 0x92, 0x3F, 0xF2, 0x5A, 0x3C, 0x4D, 0xFF, 0x00,
+	0x62, 0xA2, 0xFF, 0x00, 0xE9, 0x4C, 0x55, 0xF2, 0x80, 0xEB, 0x5F, 0x57, 0xFF, 0x00, 0xC1, 0x24,
+	0x7F, 0xE4, 0xB4, 0xF8, 0x9B, 0xFE, 0xC5, 0x45, 0xFF, 0x00, 0xD2, 0x98, 0xA8, 0x03, 0xD6, 0x7F,
+	0xE0, 0xAC, 0xBF, 0xF2, 0x6F, 0x1A, 0x1F, 0xFD, 0x8E, 0x30, 0xFF, 0x00, 0xE9, 0x2D, 0xCD, 0x7E,
+	0x7B, 0xD7, 0xE8, 0x47, 0xFC, 0x15, 0x97, 0xFE, 0x4D, 0xDF, 0x43, 0xFF, 0x00, 0xB1, 0xCA, 0x1F,
+	0xFD, 0x25, 0xB9, 0xAF, 0xCF, 0x7A, 0x98, 0x94, 0xF6, 0x5F, 0xD7, 0x50, 0xA2, 0x8A, 0x2A, 0x89,
+	0x0A, 0xF7, 0xAF, 0xF8, 0x26, 0xC7, 0xFC, 0x9D, 0xCE, 0x83, 0xFF, 0x00, 0x60, 0xFD, 0x43, 0xFF,
+	0x00, 0x49, 0xDE, 0xBC, 0x16, 0xBD, 0xEB, 0xFE, 0x09, 0xB1, 0xFF, 0x00, 0x27, 0x73, 0xA0, 0xFF,
+	0x00, 0xD8, 0x3F, 0x50, 0xFF, 0x00, 0xD2, 0x77, 0xA0, 0x0F, 0xB1, 0x3F, 0xE0, 0xA2, 0x9F, 0xF2,
+	0x67, 0x9E, 0x2C, 0x1F, 0xF4, 0xD2, 0xC7, 0xFF, 0x00, 0x4B, 0x60, 0xAF, 0xCC, 0x1A, 0xFD, 0x3E,
+	0xFF, 0x00, 0x82, 0x8A, 0x7F, 0xC9, 0x9D, 0xF8, 0xB7, 0xFE, 0xBA, 0x58, 0xFF, 0x00, 0xE9, 0x6C,
+	0x15, 0xF9, 0x83, 0x53, 0x0D, 0x8A, 0x7B, 0x2F, 0xEB, 0xA8, 0x51, 0x45, 0x15, 0x44, 0x85, 0x7A,
+	0x27, 0xEC, 0x95, 0xFF, 0x00, 0x27, 0x39, 0xE0, 0x1F, 0xFB, 0x1A, 0xAD, 0x3F, 0xF4, 0x21, 0x5E,
+	0x77, 0x5E, 0x89, 0xFB, 0x25, 0x7F, 0xC9, 0xCE, 0x78, 0x07, 0xFE, 0xC6, 0xAB, 0x4F, 0xFD, 0x08,
+	0x50, 0x07, 0xE9, 0x5F, 0xED, 0x49, 0xFF, 0x00, 0x26, 0xD1, 0xF1, 0x10, 0x7F, 0xD4, 0x95, 0xA9,
+	0xFF, 0x00, 0xE9, 0x2C, 0x95, 0xF8, 0xD9, 0x5F, 0xB2, 0x9F, 0xB5, 0x27, 0xFC, 0x9B, 0x47, 0xC4,
+	0x4F, 0xFB, 0x12, 0x75, 0x3F, 0xFD, 0x25, 0x92, 0xBF, 0x1A, 0xEB, 0xF3, 0xDE, 0x30, 0xFF, 0x00,
+	0x78, 0xA5, 0xE8, 0xFF, 0x00, 0x33, 0xFA, 0x4B, 0xC0, 0xBD, 0x72, 0xBC, 0x6F, 0xF8, 0xE3, 0xFF,
+	0x00, 0xA4, 0xB0, 0xA2, 0x8A, 0x2B, 0xE3, 0x6C, 0x8F, 0xDD, 0x82, 0xBE, 0x86, 0xFF, 0x00, 0x82,
+	0x5E, 0xFF, 0x00, 0xC9, 0xDC, 0xE9, 0x3F, 0xF6, 0x0A, 0xBE, 0xFF, 0x00, 0xD1, 0x46, 0xBE, 0x79,
+	0xAF, 0xA1, 0xFF, 0x00, 0xE0, 0x97, 0x9F, 0xF2, 0x77, 0x5A, 0x4F, 0xFD, 0x82, 0xAF, 0xBF, 0xF4,
+	0x51, 0xAF, 0x4B, 0x27, 0xD3, 0x32, 0xA3, 0xE4, 0xD1, 0xF2, 0x7C, 0x75, 0x7F, 0xF5, 0x3F, 0x1A,
+	0xFF, 0x00, 0xE9, 0xDB, 0x3E, 0xE5, 0xFD, 0xB9, 0x3F, 0xE4, 0x8A, 0xA7, 0xFD, 0x86, 0x20, 0xFE,
+	0x4F, 0x5F, 0x1E, 0x1E, 0xB5, 0xF6, 0x27, 0xED, 0xCB, 0xFF, 0x00, 0x24, 0x56, 0x3F, 0xFB, 0x0C,
+	0x41, 0xFC, 0x9E, 0xBE, 0x3A, 0x3D, 0x6B, 0xF9, 0x6F, 0xE9, 0x39, 0x6F, 0xF8, 0x88, 0x69, 0xBF,
+	0xF9, 0xF5, 0x0F, 0xD4, 0xFC, 0x43, 0xC3, 0xAF, 0xF9, 0x11, 0xBB, 0x7F, 0x3B, 0xFD, 0x02, 0x8A,
+	0x28, 0xAF, 0xE7, 0x13, 0xEF, 0xC2, 0xBE, 0x91, 0xFF, 0x00, 0x82, 0x7A, 0x7F, 0xC7, 0xCF, 0x8A,
+	0x87, 0xFB, 0x36, 0x5F, 0xFB, 0x71, 0x5F, 0x37, 0x57, 0xD2, 0x1F, 0xF0, 0x4F, 0x4F, 0xF8, 0xFB,
+	0xF1, 0x4F, 0xFB, 0xB6, 0x7F, 0xCE, 0xE2, 0xBF, 0x69, 0xF0, 0x07, 0xFE, 0x4E, 0x86, 0x0F, 0xFE,
+	0xDE, 0xFC, 0x8F, 0x8F, 0xE3, 0x9F, 0xF9, 0x26, 0xEA, 0xFA, 0xAF, 0xCD, 0x1C, 0x7F, 0xFC, 0x15,
+	0xFF, 0x00, 0xFE, 0x45, 0xFF, 0x00, 0x02, 0x7F, 0xD7, 0xE5, 0xF7, 0xFE, 0x8B, 0x8E, 0xBE, 0x1B,
+	0xAF, 0xB9, 0x3F, 0xE0, 0xAF, 0xFF, 0x00, 0xF2, 0x2F, 0xF8, 0x13, 0xFE, 0xBF, 0x2F, 0xBF, 0xF4,
+	0x5C, 0x75, 0xF0, 0xDD, 0x7F, 0xA5, 0x67, 0xE0, 0x68, 0x5E, 0x41, 0x50, 0x8C, 0xC3, 0x73, 0x65,
+	0x5E, 0x3E, 0xCC, 0x2B, 0xEF, 0x9F, 0xF8, 0x26, 0xFF, 0x00, 0xED, 0x61, 0xFF, 0x00, 0x09, 0xFF,
+	0x00, 0x87, 0xE3, 0xF8, 0x1D, 0xE3, 0xAB, 0xE0, 0xDA, 0xE6, 0x95, 0x0A, 0xFF, 0x00, 0x61, 0xDC,
+	0x37, 0xDE, 0xBB, 0xB3, 0x55, 0x00, 0xC4, 0x7F, 0xDB, 0x8C, 0x0F, 0xFB, 0xF7, 0x83, 0xFC, 0x15,
+	0xF0, 0x2D, 0x5E, 0xF0, 0xD7, 0x89, 0x35, 0xEF, 0x07, 0xF8, 0x86, 0xCF, 0xC5, 0x1E, 0x18, 0xD5,
+	0xA4, 0xB2, 0xD4, 0x2C, 0xAE, 0x12, 0x6B, 0x1B, 0xAB, 0x7E, 0xB0, 0xCC, 0xA7, 0xFD, 0x6F, 0xD0,
+	0x2F, 0xC8, 0x69, 0x5A, 0xE0, 0x7E, 0xD0, 0xA6, 0x36, 0x8C, 0x63, 0xA7, 0xF0, 0xD2, 0xD7, 0x91,
+	0xFE, 0xC8, 0xBF, 0xB4, 0xF6, 0x85, 0xFB, 0x4D, 0xFC, 0x39, 0x4D, 0x63, 0x31, 0xDB, 0x6B, 0xDA,
+	0x7A, 0xAC, 0x7A, 0xF6, 0x9E, 0xB2, 0x72, 0x93, 0x60, 0x62, 0x54, 0xFF, 0x00, 0xA6, 0x6F, 0xC9,
+	0x1E, 0xC6, 0xBD, 0x70, 0x60, 0x0C, 0x01, 0x4C, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0,
+	0x03, 0xAF, 0x51, 0x45, 0x14, 0x51, 0x60, 0xD0, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00,
+	0x2B, 0xF9, 0xAF, 0xFF, 0x00, 0x83, 0xB4, 0x7F, 0xE5, 0x28, 0x1A, 0x5F, 0xFD, 0x92, 0x8D, 0x27,
+	0xFF, 0x00, 0x4B, 0x2F, 0xAB, 0xFA, 0x50, 0xAF, 0xE6, 0xBF, 0xFE, 0x0E, 0xD1, 0xFF, 0x00, 0x94,
+	0xA0, 0x69, 0x7F, 0xF6, 0x4A, 0x34, 0x9F, 0xFD, 0x2C, 0xBE, 0xAC, 0xEA, 0xFC, 0x27, 0x46, 0x1F,
+	0xF8, 0x87, 0xE6, 0x19, 0xEB, 0x45, 0x07, 0xAD, 0x15, 0xCE, 0x7A, 0x01, 0x45, 0x14, 0x50, 0x01,
+	0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x51, 0x70, 0x0A, 0x28, 0xA2, 0x8B,
+	0x80, 0x51, 0x45, 0x14, 0x5C, 0x02, 0x8A, 0x28, 0xA2, 0xE0, 0x14, 0x51, 0x45, 0x17, 0x00, 0xA2,
+	0x8A, 0x28, 0xB8, 0x05, 0x14, 0x51, 0x45, 0xC0, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00,
+	0x28, 0xA2, 0x8A, 0x00, 0xFA, 0x3B, 0xFE, 0x09, 0x09, 0xFF, 0x00, 0x29, 0x45, 0xF8, 0x03, 0xFF,
+	0x00, 0x65, 0x5B, 0x47, 0xFF, 0x00, 0xD2, 0x94, 0xAF, 0xEB, 0xF9, 0x7E, 0xED, 0x7F, 0x20, 0x3F,
+	0xF0, 0x48, 0x4F, 0xF9, 0x4A, 0x2F, 0xC0, 0x1F, 0xFB, 0x2A, 0xDA, 0x3F, 0xFE, 0x94, 0xA5, 0x7F,
+	0x5F, 0xCB, 0xF7, 0x6B, 0xA2, 0x9B, 0xB9, 0xC3, 0x8A, 0xF8, 0x82, 0x8A, 0x28, 0xAD, 0x0E, 0x50,
+	0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00,
+	0xA2, 0x8A, 0xE1, 0xFE, 0x3E, 0xFC, 0x6C, 0xF0, 0x8F, 0xEC, 0xFD, 0xF0, 0xEE, 0xF7, 0xE2, 0x27,
+	0x8B, 0x2E, 0x57, 0x6C, 0x3F, 0x25, 0xA5, 0xAF, 0xF1, 0xDD, 0x4C, 0x47, 0xCB, 0x12, 0xFB, 0x13,
+	0xC9, 0xA0, 0x0F, 0x3B, 0xFD, 0xBB, 0x3F, 0x6A, 0x9B, 0x6F, 0xD9, 0xDF, 0xC0, 0x7F, 0xD9, 0x1E,
+	0x1B, 0xB9, 0x2F, 0xE2, 0xBD, 0x72, 0x17, 0x4D, 0x2E, 0x35, 0x7F, 0xF8, 0xF2, 0x8B, 0xEE, 0xBD,
+	0xD9, 0xFA, 0x7D, 0xD4, 0xFF, 0x00, 0x6F, 0xD8, 0x3D, 0x7E, 0x67, 0x5C, 0xDC, 0x4F, 0x77, 0x71,
+	0x25, 0xDD, 0xD4, 0xC6, 0x49, 0x25, 0x72, 0xF2, 0x48, 0xDD, 0x5D, 0x89, 0xC9, 0x3F, 0x89, 0xAE,
+	0x87, 0xE2, 0xD7, 0xC5, 0x2F, 0x14, 0xFC, 0x68, 0xF8, 0x81, 0xA8, 0x78, 0xFF, 0x00, 0xC6, 0xD7,
+	0xE2, 0x6B, 0xCD, 0x42, 0xE5, 0x7E, 0x4F, 0xE1, 0x86, 0x2E, 0xA9, 0x1C, 0x7F, 0xEC, 0x81, 0x80,
+	0x3D, 0x85, 0x73, 0x79, 0x63, 0xCB, 0x86, 0xDD, 0xDF, 0x77, 0x5A, 0x00, 0x2B, 0xEE, 0x3F, 0xF8,
+	0x24, 0x1F, 0xFC, 0x8B, 0x7E, 0x3A, 0xFF, 0x00, 0xAF, 0xFB, 0x1F, 0xFD, 0x15, 0x71, 0x5F, 0x0E,
+	0x57, 0xDC, 0x7F, 0xF0, 0x48, 0x3F, 0xF9, 0x16, 0xFC, 0x75, 0xFF, 0x00, 0x5F, 0xF6, 0x3F, 0xFA,
+	0x2A, 0xE2, 0x80, 0x3B, 0x1F, 0xF8, 0x28, 0x33, 0x03, 0x73, 0xE1, 0x50, 0x07, 0x46, 0xBE, 0xFE,
+	0x50, 0xD7, 0xCD, 0xF5, 0xF4, 0x87, 0xFC, 0x14, 0x1B, 0xFE, 0x3E, 0x7C, 0x2B, 0xFE, 0xF5, 0xF7,
+	0xF2, 0x86, 0xBE, 0x6F, 0xAF, 0xF3, 0x57, 0xC7, 0xCF, 0xF9, 0x39, 0xD8, 0xCD, 0x3F, 0x97, 0xFF,
+	0x00, 0x49, 0x47, 0xEF, 0xFC, 0x0F, 0xFF, 0x00, 0x24, 0xDD, 0x24, 0xBB, 0xBF, 0xCC, 0x28, 0xA2,
+	0x8A, 0xFC, 0x54, 0xFA, 0xDD, 0x42, 0xBE, 0xC4, 0xFD, 0x86, 0xB9, 0xF8, 0x2D, 0x27, 0xFD, 0x86,
+	0x65, 0xFF, 0x00, 0xD0, 0x63, 0xAF, 0x8E, 0xEB, 0xEC, 0x4F, 0xD8, 0x67, 0xFE, 0x48, 0xBB, 0x7F,
+	0xD8, 0x6A, 0x5F, 0xFD, 0x06, 0x3A, 0xFE, 0x8B, 0xFA, 0x32, 0xFF, 0x00, 0xC9, 0xC3, 0x6F, 0xFE,
+	0x9D, 0x4F, 0xF4, 0x3E, 0x07, 0xC4, 0x45, 0xFF, 0x00, 0x08, 0x31, 0xFF, 0x00, 0x12, 0x3E, 0x25,
+	0xFF, 0x00, 0x82, 0xA2, 0x67, 0xFE, 0x1A, 0xEB, 0x54, 0xFF, 0x00, 0xB0, 0x4E, 0x9F, 0xFF, 0x00,
+	0xA2, 0x85, 0x7C, 0xF3, 0x5F, 0x43, 0x7F, 0xC1, 0x50, 0xFF, 0x00, 0xE4, 0xEE, 0x75, 0x4F, 0xFB,
+	0x04, 0xD8, 0x7F, 0xE8, 0xA1, 0x5F, 0x3C, 0xD7, 0xFA, 0x12, 0x7E, 0x47, 0x4F, 0xF8, 0x68, 0x28,
+	0xA2, 0x8A, 0x0A, 0x0A, 0xFD, 0x8F, 0xFD, 0x98, 0x7F, 0xE4, 0xDA, 0xBE, 0x1E, 0x7F, 0xD8, 0x8D,
+	0xA4, 0xFF, 0x00, 0xE9, 0x1C, 0x55, 0xF8, 0xE1, 0x5F, 0xB1, 0xFF, 0x00, 0xB3, 0x0F, 0xFC, 0x9B,
+	0x57, 0xC3, 0xCF, 0xFB, 0x11, 0xB4, 0x9F, 0xFD, 0x23, 0x8A, 0x83, 0x9F, 0x13, 0xB2, 0xB9, 0xF9,
+	0xB5, 0xFB, 0x69, 0xFF, 0x00, 0xC9, 0xD7, 0x78, 0xDB, 0xFE, 0xC3, 0x87, 0xFF, 0x00, 0x41, 0x5A,
+	0xF2, 0xC4, 0xFB, 0x83, 0xE9, 0x5E, 0xA7, 0xFB, 0x69, 0xFF, 0x00, 0xC9, 0xD7, 0x78, 0xDB, 0xFE,
+	0xC3, 0x87, 0xFF, 0x00, 0x41, 0x5A, 0xF2, 0xC4, 0xFB, 0x83, 0xE9, 0x41, 0xC6, 0x2D, 0x14, 0x51,
+	0x40, 0x05, 0x7D, 0xE9, 0xFF, 0x00, 0x04, 0x87, 0x04, 0xFC, 0x33, 0xF1, 0x88, 0x53, 0x8F, 0xF8,
+	0x9E, 0x41, 0xFF, 0x00, 0xA2, 0x6B, 0xE0, 0xBA, 0xFB, 0xD3, 0xFE, 0x09, 0x0B, 0xFF, 0x00, 0x24,
+	0xD7, 0xC6, 0x1F, 0xF6, 0x1C, 0x83, 0xFF, 0x00, 0x44, 0xD0, 0x07, 0x8F, 0x7F, 0xC1, 0x54, 0x7F,
+	0xE4, 0xE6, 0x6D, 0xFF, 0x00, 0xEC, 0x58, 0xB5, 0xFF, 0x00, 0xD0, 0xE5, 0xAF, 0x9B, 0x2B, 0xE9,
+	0x3F, 0xF8, 0x2A, 0x8F, 0xFC, 0x9C, 0xCD, 0xBF, 0xFD, 0x8B, 0x16, 0xBF, 0xFA, 0x1C, 0xB5, 0xF3,
+	0x65, 0x00, 0x14, 0x51, 0x45, 0x00, 0x1D, 0xBF, 0x0A, 0xFB, 0x9B, 0xFE, 0x09, 0x04, 0x09, 0xF0,
+	0xD7, 0x8F, 0x82, 0x9C, 0x7F, 0xC4, 0xC2, 0xC3, 0xFF, 0x00, 0x45, 0xCD, 0x5F, 0x0C, 0xF6, 0xFC,
+	0x2B, 0xEE, 0x8F, 0xF8, 0x24, 0x07, 0xFC, 0x8B, 0x9E, 0x3E, 0xFF, 0x00, 0xB0, 0x85, 0x87, 0xFE,
+	0x8B, 0x9A, 0x80, 0x3C, 0xAB, 0xFE, 0x0A, 0xA3, 0xFF, 0x00, 0x27, 0x33, 0x6F, 0xFF, 0x00, 0x62,
+	0xC5, 0xAF, 0xFE, 0x87, 0x2D, 0x7C, 0xD9, 0x5F, 0x49, 0xFF, 0x00, 0xC1, 0x54, 0x7F, 0xE4, 0xE6,
+	0x6D, 0xFF, 0x00, 0xEC, 0x58, 0xB5, 0xFF, 0x00, 0xD0, 0xE5, 0xAF, 0x9B, 0x28, 0x00, 0xA2, 0x8A,
+	0x28, 0x00, 0xED, 0xF8, 0x57, 0xDC, 0x9F, 0xF0, 0x48, 0x6F, 0xF9, 0x16, 0xFC, 0x7B, 0xFF, 0x00,
+	0x61, 0x0B, 0x1F, 0xFD, 0x17, 0x35, 0x7C, 0x37, 0xDB, 0xF0, 0xAF, 0xB9, 0x3F, 0xE0, 0x90, 0xDF,
+	0xF2, 0x2D, 0xF8, 0xF7, 0xFE, 0xC2, 0x16, 0x3F, 0xFA, 0x2E, 0x6A, 0x52, 0xF8, 0x40, 0xFB, 0x36,
+	0x03, 0x98, 0x85, 0x3E, 0x9B, 0x07, 0xFA, 0xA5, 0xA7, 0x53, 0x0D, 0x82, 0x83, 0xD2, 0x8A, 0x0F,
+	0x4A, 0x00, 0xF8, 0x53, 0xFE, 0x0A, 0xFB, 0xFF, 0x00, 0x23, 0x27, 0x81, 0xFF, 0x00, 0xEB, 0xCA,
+	0xFB, 0xFF, 0x00, 0x46, 0x47, 0x5F, 0x1B, 0x57, 0xD9, 0x3F, 0xF0, 0x57, 0xDF, 0xF9, 0x19, 0x3C,
+	0x0F, 0xFF, 0x00, 0x5E, 0x57, 0xDF, 0xFA, 0x32, 0x3A, 0xF8, 0xDA, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x01, 0xD6, 0xBE, 0xAF, 0xFF, 0x00, 0x82, 0x48, 0xFF, 0x00, 0xC9, 0x69, 0xF1, 0x37, 0xFD, 0x8A,
+	0x8B, 0xFF, 0x00, 0xA5, 0x31, 0x57, 0xCA, 0x03, 0xAD, 0x7D, 0x5D, 0xFF, 0x00, 0x04, 0x92, 0xCF,
+	0xFC, 0x2E, 0x8F, 0x13, 0x60, 0x7F, 0xCC, 0xA6, 0xBF, 0xFA, 0x53, 0x15, 0x0C, 0x0F, 0x5A, 0xFF,
+	0x00, 0x82, 0xB2, 0xFF, 0x00, 0xC9, 0xBB, 0xE8, 0x7F, 0xF6, 0x39, 0x43, 0xFF, 0x00, 0xA4, 0xB7,
+	0x35, 0xF9, 0xEF, 0x5F, 0xA1, 0x1F, 0xF0, 0x56, 0x53, 0xFF, 0x00, 0x18, 0xF1, 0xA1, 0x83, 0xFF,
+	0x00, 0x43, 0x84, 0x3F, 0xFA, 0x4B, 0x73, 0x5F, 0x9E, 0xF5, 0x31, 0xEB, 0x61, 0xFD, 0x95, 0xFD,
+	0x75, 0x0A, 0x28, 0xA2, 0xA8, 0x41, 0x5E, 0xF5, 0xFF, 0x00, 0x04, 0xD8, 0xFF, 0x00, 0x93, 0xB9,
+	0xD0, 0x7F, 0xEC, 0x1F, 0xA8, 0x7F, 0xE9, 0x3B, 0xD7, 0x82, 0xD7, 0xBD, 0x7F, 0xC1, 0x36, 0x3F,
+	0xE4, 0xEE, 0x74, 0x1F, 0xFB, 0x07, 0xEA, 0x1F, 0xFA, 0x4E, 0xF4, 0x01, 0xF6, 0x27, 0xFC, 0x14,
+	0x53, 0xFE, 0x4C, 0xEF, 0xC5, 0xBF, 0xF5, 0xD2, 0xC7, 0xFF, 0x00, 0x4B, 0x60, 0xAF, 0xCC, 0x1A,
+	0xFD, 0x3D, 0xFF, 0x00, 0x82, 0x89, 0x93, 0xFF, 0x00, 0x0C, 0x79, 0xE2, 0xCC, 0x8F, 0xF9, 0x69,
+	0x63, 0xFF, 0x00, 0xA5, 0xB0, 0x57, 0xE6, 0x15, 0x4C, 0x7F, 0xAF, 0xB9, 0x14, 0xF6, 0x5F, 0xD7,
+	0x50, 0xA2, 0x8A, 0x2A, 0x89, 0x0A, 0xF4, 0x4F, 0xD9, 0x2B, 0xFE, 0x4E, 0x73, 0xC0, 0x3F, 0xF6,
+	0x35, 0x5A, 0x7F, 0xE8, 0x42, 0xBC, 0xEE, 0xBD, 0x13, 0xF6, 0x4A, 0xFF, 0x00, 0x93, 0x9C, 0xF0,
+	0x0F, 0xFD, 0x8D, 0x56, 0x9F, 0xFA, 0x10, 0xA0, 0x0F, 0xD2, 0xCF, 0xDA, 0x93, 0xFE, 0x4D, 0xA3,
+	0xE2, 0x27, 0xFD, 0x89, 0x3A, 0x9F, 0xFE, 0x92, 0xC9, 0x5F, 0x8D, 0x75, 0xFB, 0x25, 0xFB, 0x52,
+	0x13, 0xFF, 0x00, 0x0C, 0xD1, 0xF1, 0x13, 0x23, 0xFE, 0x64, 0xBD, 0x4F, 0xFF, 0x00, 0x49, 0x64,
+	0xAF, 0xC6, 0xDA, 0xFC, 0xF7, 0x8C, 0x7F, 0xDE, 0x28, 0xFA, 0x3F, 0xCC, 0xFE, 0x92, 0xF0, 0x2F,
+	0xFE, 0x45, 0x78, 0xDF, 0xF1, 0xC7, 0xFF, 0x00, 0x49, 0x61, 0x45, 0x14, 0x57, 0xC6, 0xD8, 0xFD,
+	0xD8, 0x2B, 0xE8, 0x7F, 0xF8, 0x25, 0xE1, 0xFF, 0x00, 0x8C, 0xBA, 0xD2, 0x7F, 0xEC, 0x15, 0x7D,
+	0xFF, 0x00, 0xA2, 0x8D, 0x7C, 0xF1, 0x5F, 0x43, 0x7F, 0xC1, 0x2F, 0x7F, 0xE4, 0xEE, 0x74, 0x9C,
+	0x8F, 0xF9, 0x85, 0x5F, 0x7F, 0xE8, 0xA3, 0x5E, 0x96, 0x4F, 0xFF, 0x00, 0x23, 0x4A, 0x4A, 0xDD,
+	0x51, 0xF2, 0x7C, 0x75, 0xFF, 0x00, 0x24, 0x7E, 0x33, 0xFE, 0xBD, 0xC8, 0xFB, 0x9F, 0xF6, 0xE5,
+	0xFF, 0x00, 0x92, 0x2B, 0x1F, 0xFD, 0x86, 0x20, 0xFE, 0x4F, 0x5F, 0x1D, 0x1E, 0xB5, 0xF6, 0x27,
+	0xED, 0xC9, 0xFF, 0x00, 0x24, 0x56, 0x3F, 0xFB, 0x0C, 0x41, 0xFC, 0x9E, 0xBE, 0x3B, 0x3D, 0x6B,
+	0xF9, 0x6B, 0xE9, 0x37, 0xAF, 0x88, 0x49, 0xFF, 0x00, 0xD3, 0xA8, 0x7E, 0xA7, 0xE1, 0xFE, 0x1D,
+	0x5B, 0xFB, 0x0D, 0xFF, 0x00, 0x89, 0xFE, 0x81, 0x45, 0x14, 0x57, 0xF3, 0x91, 0xFA, 0x03, 0xDC,
+	0x2B, 0xE9, 0x0F, 0xF8, 0x27, 0xA7, 0xFC, 0x7D, 0xF8, 0xA7, 0xFD, 0xDB, 0x3F, 0xE7, 0x71, 0x5F,
+	0x37, 0xD7, 0xD2, 0x3F, 0xF0, 0x4F, 0x4F, 0xF8, 0xF9, 0xF1, 0x57, 0xFB, 0xB6, 0x5F, 0xCE, 0xE2,
+	0xBF, 0x68, 0xF0, 0x07, 0x4F, 0x13, 0xF0, 0x6D, 0x7F, 0x7B, 0xF2, 0x3E, 0x3F, 0x8E, 0x6D, 0xFE,
+	0xAD, 0xD5, 0xF9, 0x7E, 0x68, 0xE3, 0xBF, 0xE0, 0xAF, 0xFF, 0x00, 0xF2, 0x2F, 0xF8, 0x13, 0xFE,
+	0xBF, 0x2F, 0xBF, 0xF4, 0x5C, 0x75, 0xF0, 0xDD, 0x7D, 0xC9, 0xFF, 0x00, 0x05, 0x7F, 0xFF, 0x00,
+	0x91, 0x7F, 0xC0, 0x9F, 0xF5, 0xF9, 0x7D, 0xFF, 0x00, 0xA2, 0xE3, 0xAF, 0x86, 0xEB, 0xFD, 0x2C,
+	0x3F, 0x03, 0x0A, 0x28, 0xA2, 0x80, 0x3A, 0xCF, 0x82, 0xBF, 0x18, 0xFC, 0x65, 0xF0, 0x1F, 0xE2,
+	0x05, 0x9F, 0xC4, 0x1F, 0x06, 0x5C, 0x81, 0x3C, 0x0B, 0xB6, 0x7B, 0x39, 0x7E, 0xE5, 0xCC, 0x25,
+	0xBE, 0x78, 0xA4, 0xFF, 0x00, 0xA6, 0x6C, 0x3E, 0x61, 0xFE, 0xD5, 0x7E, 0xAC, 0x7C, 0x1B, 0xF8,
+	0xAD, 0xE1, 0xDF, 0x8D, 0x9F, 0x0E, 0x34, 0xBF, 0x89, 0x9E, 0x16, 0xDD, 0x1D, 0x9E, 0xA7, 0x19,
+	0x61, 0x0C, 0xBF, 0x7E, 0x19, 0x15, 0xCC, 0x6F, 0x1B, 0x7B, 0xAB, 0x02, 0x0F, 0xB8, 0xAF, 0xC7,
+	0xBA, 0xFD, 0x34, 0xFF, 0x00, 0x82, 0x6A, 0xFF, 0x00, 0xC9, 0xA3, 0xE8, 0x7F, 0xF5, 0xFD, 0x7F,
+	0xFF, 0x00, 0xA5, 0x2D, 0x40, 0x1E, 0xF6, 0xA7, 0x2A, 0x0E, 0x3B, 0x52, 0xD0, 0x3A, 0x51, 0x40,
+	0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40,
+	0x05, 0x7F, 0x35, 0xFF, 0x00, 0xF0, 0x76, 0x8F, 0xFC, 0xA5, 0x03, 0x4B, 0xFF, 0x00, 0xB2, 0x51,
+	0xA4, 0xFF, 0x00, 0xE9, 0x65, 0xF5, 0x7F, 0x4A, 0x15, 0xFC, 0xD7, 0xFF, 0x00, 0xC1, 0xDA, 0x3F,
+	0xF2, 0x94, 0x0D, 0x2F, 0xFE, 0xC9, 0x46, 0x93, 0xFF, 0x00, 0xA5, 0x97, 0xD5, 0x9D, 0x5F, 0x84,
+	0xE8, 0xC3, 0x7F, 0x15, 0x1F, 0x98, 0x67, 0xAD, 0x14, 0x1E, 0xB4, 0x57, 0x39, 0xE8, 0x05, 0x14,
+	0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14,
+	0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14,
+	0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14,
+	0x51, 0x40, 0x1F, 0x47, 0x7F, 0xC1, 0x21, 0x3F, 0xE5, 0x28, 0xBF, 0x00, 0x7F, 0xEC, 0xAB, 0x68,
+	0xFF, 0x00, 0xFA, 0x52, 0x95, 0xFD, 0x7F, 0x2F, 0xDD, 0xAF, 0xE4, 0x07, 0xFE, 0x09, 0x09, 0xFF,
+	0x00, 0x29, 0x45, 0xF8, 0x03, 0xFF, 0x00, 0x65, 0x5B, 0x47, 0xFF, 0x00, 0xD2, 0x94, 0xAF, 0xEB,
+	0xF9, 0x7E, 0xED, 0x6D, 0x48, 0xE1, 0xC5, 0x7C, 0x41, 0x45, 0x14, 0x56, 0xC7, 0x28, 0x51, 0x45,
+	0x14, 0x00, 0x51, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14, 0x01, 0x8B, 0xE3,
+	0xCF, 0x1B, 0xF8, 0x5F, 0xE1, 0xD7, 0x85, 0x75, 0x0F, 0x1B, 0x78, 0xC7, 0x53, 0x86, 0xD3, 0x4E,
+	0xD3, 0x60, 0x32, 0x5D, 0x4B, 0x21, 0xCE, 0x17, 0xFB, 0xBF, 0x52, 0x7A, 0x57, 0xE5, 0xDF, 0xED,
+	0x59, 0xFB, 0x4B, 0xF8, 0x83, 0xF6, 0x92, 0xF8, 0x89, 0x27, 0x88, 0x2F, 0x04, 0x96, 0xDA, 0x1D,
+	0x9B, 0x34, 0x7A, 0x1E, 0x96, 0xD2, 0xE0, 0x24, 0x79, 0xC1, 0x91, 0xFF, 0x00, 0xE9, 0xA1, 0xEF,
+	0xEF, 0x5F, 0x72, 0xFF, 0x00, 0xC1, 0x49, 0xFF, 0x00, 0xE4, 0xD1, 0xF5, 0xEF, 0xFA, 0xFE, 0xB1,
+	0xFF, 0x00, 0xD2, 0x84, 0xAF, 0xCC, 0x8A, 0x00, 0x00, 0x2A, 0x30, 0xC3, 0xF3, 0x34, 0x51, 0x45,
+	0x00, 0x15, 0xF7, 0x1F, 0xFC, 0x12, 0x0F, 0xFE, 0x45, 0xBF, 0x1D, 0x7F, 0xD7, 0xFD, 0x8F, 0xFE,
+	0x8A, 0xB8, 0xAF, 0x87, 0x2B, 0xEE, 0x3F, 0xF8, 0x24, 0x1F, 0xFC, 0x8B, 0x7E, 0x3A, 0xFF, 0x00,
+	0xAF, 0xFB, 0x1F, 0xFD, 0x15, 0x71, 0x40, 0x1D, 0x8F, 0xFC, 0x14, 0x1F, 0xFE, 0x3E, 0x7C, 0x2B,
+	0xFE, 0xF5, 0xF7, 0xF2, 0x86, 0xBE, 0x6F, 0xAF, 0xA4, 0x3F, 0xE0, 0xA0, 0xC4, 0xFD, 0xA7, 0xC2,
+	0xBC, 0xFF, 0x00, 0x15, 0xF7, 0xF2, 0x86, 0xBE, 0x6F, 0x18, 0xEF, 0x5F, 0xE6, 0xAF, 0x8F, 0x89,
+	0xFF, 0x00, 0xC4, 0x4E, 0xC6, 0x7F, 0xDB, 0xBF, 0xFA, 0x49, 0xFB, 0xF7, 0x03, 0x35, 0xFE, 0xAD,
+	0xD2, 0xF5, 0x7F, 0x98, 0x51, 0x45, 0x15, 0xF8, 0xA9, 0xF5, 0xC1, 0x5F, 0x62, 0x7E, 0xC3, 0x3F,
+	0xF2, 0x45, 0xDB, 0xFE, 0xC3, 0x52, 0xFF, 0x00, 0xE8, 0x31, 0xD7, 0xC7, 0x7D, 0x78, 0xAF, 0xB1,
+	0x3F, 0x61, 0xA3, 0xFF, 0x00, 0x16, 0x5D, 0xFF, 0x00, 0xEC, 0x33, 0x2F, 0xF2, 0x8E, 0xBF, 0xA2,
+	0xBE, 0x8C, 0xAB, 0xFE, 0x36, 0x1B, 0x5F, 0xF4, 0xEA, 0x7F, 0xA1, 0xF0, 0x5E, 0x22, 0x5F, 0xFB,
+	0x0D, 0x5F, 0xF9, 0x91, 0xF1, 0x2F, 0xFC, 0x15, 0x0F, 0x3F, 0xF0, 0xD7, 0x3A, 0xA7, 0xFD, 0x82,
+	0x74, 0xFF, 0x00, 0xFD, 0x14, 0x2B, 0xE7, 0x9A, 0xFA, 0x1B, 0xFE, 0x0A, 0x89, 0x9F, 0xF8, 0x6B,
+	0xAD, 0x53, 0xFE, 0xC1, 0x3A, 0x7F, 0xFE, 0x8A, 0x15, 0xF3, 0xCD, 0x7F, 0xA1, 0x47, 0xE4, 0x54,
+	0xFF, 0x00, 0x86, 0x82, 0x8A, 0x28, 0xA0, 0xA0, 0xAF, 0xD8, 0xFF, 0x00, 0xD9, 0x87, 0xFE, 0x4D,
+	0xAB, 0xE1, 0xE7, 0xFD, 0x88, 0xDA, 0x4F, 0xFE, 0x91, 0xC5, 0x5F, 0x8E, 0x15, 0xFB, 0x1F, 0xFB,
+	0x30, 0xFF, 0x00, 0xC9, 0xB5, 0x7C, 0x3C, 0xFF, 0x00, 0xB1, 0x1B, 0x49, 0xFF, 0x00, 0xD2, 0x38,
+	0xA8, 0x39, 0xF1, 0x3B, 0x44, 0xFC, 0xDA, 0xFD, 0xB4, 0xFF, 0x00, 0xE4, 0xEB, 0xBC, 0x6D, 0xFF,
+	0x00, 0x61, 0xC3, 0xFF, 0x00, 0xA0, 0xAD, 0x79, 0x62, 0x7D, 0xC1, 0xF4, 0xAF, 0x53, 0xFD, 0xB4,
+	0xFF, 0x00, 0xE4, 0xEB, 0xBC, 0x6D, 0xFF, 0x00, 0x61, 0xC3, 0xFF, 0x00, 0xA0, 0xAD, 0x79, 0x62,
+	0x7D, 0xC1, 0xF4, 0xA0, 0xE3, 0x16, 0x8A, 0x28, 0xA0, 0x02, 0xBE, 0xF4, 0xFF, 0x00, 0x82, 0x42,
+	0xFF, 0x00, 0xC9, 0x35, 0xF1, 0x87, 0xFD, 0x87, 0x20, 0xFF, 0x00, 0xD1, 0x35, 0xF0, 0x5D, 0x7D,
+	0xE9, 0xFF, 0x00, 0x04, 0x85, 0xFF, 0x00, 0x92, 0x6B, 0xE3, 0x0F, 0xFB, 0x0E, 0x41, 0xFF, 0x00,
+	0xA2, 0x68, 0x03, 0xC7, 0xBF, 0xE0, 0xAA, 0x3F, 0xF2, 0x73, 0x36, 0xFF, 0x00, 0xF6, 0x2C, 0x5A,
+	0xFF, 0x00, 0xE8, 0x72, 0xD7, 0xCD, 0x95, 0xF4, 0x9F, 0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66, 0xDF,
+	0xFE, 0xC5, 0x8B, 0x5F, 0xFD, 0x0E, 0x5A, 0xF9, 0xB2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0E, 0xDF,
+	0x85, 0x7D, 0xD1, 0xFF, 0x00, 0x04, 0x80, 0xFF, 0x00, 0x91, 0x73, 0xC7, 0xDF, 0xF6, 0x10, 0xB0,
+	0xFF, 0x00, 0xD1, 0x73, 0x57, 0xC2, 0xFD, 0xBF, 0x0A, 0xFB, 0xA3, 0xFE, 0x09, 0x01, 0xFF, 0x00,
+	0x22, 0xE7, 0x8F, 0xBF, 0xEC, 0x21, 0x61, 0xFF, 0x00, 0xA2, 0xE6, 0xA0, 0x0F, 0x2A, 0xFF, 0x00,
+	0x82, 0xA8, 0xFF, 0x00, 0xC9, 0xCC, 0xDB, 0xFF, 0x00, 0xD8, 0xB1, 0x6B, 0xFF, 0x00, 0xA1, 0xCB,
+	0x5F, 0x36, 0x57, 0xD2, 0x7F, 0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B, 0x7F, 0xFB, 0x16, 0x2D, 0x7F,
+	0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x3B, 0x7E, 0x15, 0xF7, 0x27, 0xFC,
+	0x12, 0x1B, 0xFE, 0x45, 0xBF, 0x1E, 0xFF, 0x00, 0xD8, 0x42, 0xC7, 0xFF, 0x00, 0x45, 0xCD, 0x5F,
+	0x0D, 0xF6, 0xFC, 0x2B, 0xEE, 0x4F, 0xF8, 0x24, 0x3E, 0x7F, 0xE1, 0x1A, 0xF1, 0xEE, 0x07, 0xFC,
+	0xC4, 0x2C, 0x3F, 0xF4, 0x5C, 0xD5, 0x32, 0xF8, 0x43, 0x7D, 0x0F, 0xB3, 0xA0, 0xFF, 0x00, 0x54,
+	0xB4, 0xEA, 0x64, 0x1F, 0xEA, 0xC5, 0x3E, 0xA8, 0x37, 0xD4, 0x29, 0x1C, 0x85, 0x42, 0xC7, 0xD2,
+	0x96, 0x91, 0xC1, 0x64, 0x2A, 0x07, 0x6A, 0x00, 0xF3, 0x7F, 0x8B, 0x3F, 0xB3, 0x9F, 0xC1, 0xBF,
+	0x8F, 0xBA, 0xCD, 0xBB, 0xFC, 0x5A, 0xF0, 0x70, 0xD5, 0x9F, 0x4B, 0x87, 0x6D, 0xAF, 0xFC, 0x4C,
+	0xAE, 0xA1, 0xF2, 0x3C, 0xC3, 0x96, 0x1F, 0xBA, 0x95, 0x01, 0xCE, 0xC5, 0xED, 0x5C, 0xC7, 0xFC,
+	0x3B, 0xB3, 0xF6, 0x3A, 0xFF, 0x00, 0xA2, 0x3D, 0xFF, 0x00, 0x95, 0xED, 0x43, 0xFF, 0x00, 0x92,
+	0x2B, 0x88, 0xFF, 0x00, 0x82, 0x80, 0xFE, 0xD4, 0x5F, 0x15, 0xFF, 0x00, 0x67, 0x0D, 0x77, 0xC3,
+	0x31, 0x7C, 0x32, 0xBC, 0xD3, 0xD5, 0x75, 0x8B, 0x5B, 0x97, 0xBC, 0x6B, 0xDB, 0x11, 0x27, 0xFA,
+	0xA3, 0x18, 0x52, 0x3B, 0x67, 0xE7, 0x6A, 0xF9, 0xE7, 0xFE, 0x1E, 0x7B, 0xFB, 0x54, 0x7F, 0xD0,
+	0x63, 0x43, 0xFF, 0x00, 0xC1, 0x3C, 0x74, 0x01, 0xF5, 0xEF, 0xFC, 0x3B, 0xB3, 0xF6, 0x3A, 0xFF,
+	0x00, 0xA2, 0x3D, 0xFF, 0x00, 0x95, 0xED, 0x43, 0xFF, 0x00, 0x92, 0x28, 0xFF, 0x00, 0x87, 0x76,
+	0x7E, 0xC7, 0x5F, 0xF4, 0x47, 0xBF, 0xF2, 0xBD, 0xA8, 0x7F, 0xF2, 0x45, 0x7C, 0x85, 0xFF, 0x00,
+	0x0F, 0x3D, 0xFD, 0xAA, 0x3F, 0xE8, 0x31, 0xA1, 0xFF, 0x00, 0xE0, 0x9E, 0x3A, 0x3F, 0xE1, 0xE7,
+	0xBF, 0xB5, 0x47, 0xFD, 0x06, 0x34, 0x3F, 0xFC, 0x13, 0xC7, 0x40, 0x1F, 0x5E, 0x37, 0xFC, 0x13,
+	0xB7, 0xF6, 0x3B, 0x55, 0x2C, 0x3E, 0x0E, 0xE7, 0x1C, 0xFF, 0x00, 0xC8, 0x7B, 0x50, 0xFF, 0x00,
+	0xE4, 0x9A, 0xE9, 0x7E, 0x12, 0xFE, 0xCB, 0x5F, 0x03, 0xBE, 0x03, 0xEB, 0x37, 0x5E, 0x20, 0xF8,
+	0x51, 0xE0, 0x6F, 0xEC, 0x9B, 0xAB, 0xCB, 0x4F, 0xB3, 0xDC, 0xCE, 0x75, 0x4B, 0x9B, 0x8D, 0xD1,
+	0x6F, 0x12, 0x6D, 0xC4, 0xF2, 0x38, 0x5F, 0x98, 0x76, 0x35, 0xF0, 0xF7, 0xFC, 0x3C, 0xFB, 0xF6,
+	0xA8, 0x1C, 0xFF, 0x00, 0x6B, 0xE8, 0x9F, 0x86, 0x8C, 0x86, 0xBD, 0xCF, 0xF6, 0x0A, 0xFD, 0xAF,
+	0x3E, 0x30, 0xFE, 0xD0, 0xDF, 0x11, 0xF5, 0xAF, 0x0D, 0x7C, 0x4A, 0xBE, 0xD3, 0x66, 0xB7, 0xB1,
+	0xD0, 0x5A, 0xEE, 0xDD, 0x6C, 0x74, 0xFF, 0x00, 0x29, 0x83, 0xF9, 0xF1, 0xC7, 0xCF, 0xE7, 0x40,
+	0x1F, 0x42, 0x7C, 0x58, 0xF8, 0x2B, 0xF0, 0xD7, 0xE3, 0xA6, 0x81, 0x07, 0x85, 0x7E, 0x29, 0x78,
+	0x5F, 0xFB, 0x53, 0x4F, 0xB7, 0xBB, 0xFB, 0x4C, 0x76, 0xFF, 0x00, 0x6C, 0x9E, 0x10, 0x92, 0xED,
+	0x74, 0x0D, 0x98, 0x9D, 0x09, 0xE2, 0x46, 0xEF, 0x5C, 0x2F, 0xFC, 0x3B, 0xB3, 0xF6, 0x3A, 0xFF,
+	0x00, 0xA2, 0x3D, 0xFF, 0x00, 0x95, 0xED, 0x43, 0xFF, 0x00, 0x92, 0x2A, 0x9F, 0xED, 0xEB, 0xF1,
+	0xDF, 0xE2, 0x0F, 0xEC, 0xF3, 0xF0, 0xAB, 0x4B, 0xF1, 0x8F, 0xC3, 0x89, 0xAC, 0xD6, 0xF6, 0xEF,
+	0xC4, 0x51, 0xD9, 0x48, 0x6F, 0x20, 0x32, 0x29, 0x8C, 0xC1, 0x33, 0x9F, 0x97, 0xB7, 0x31, 0xAD,
+	0x7C, 0x9D, 0xFF, 0x00, 0x0F, 0x3D, 0xFD, 0xAA, 0x3F, 0xE8, 0x31, 0xA1, 0xFF, 0x00, 0xE0, 0x9E,
+	0x3A, 0x03, 0xA1, 0xF5, 0xEF, 0xFC, 0x3B, 0xB3, 0xF6, 0x3A, 0xFF, 0x00, 0xA2, 0x3D, 0xFF, 0x00,
+	0x95, 0xED, 0x43, 0xFF, 0x00, 0x92, 0x28, 0xFF, 0x00, 0x87, 0x76, 0x7E, 0xC7, 0x5F, 0xF4, 0x47,
+	0xBF, 0xF2, 0xBD, 0xA8, 0x7F, 0xF2, 0x45, 0x7C, 0x85, 0xFF, 0x00, 0x0F, 0x3D, 0xFD, 0xAA, 0x3F,
+	0xE8, 0x31, 0xA1, 0xFF, 0x00, 0xE0, 0x9E, 0x3A, 0x3F, 0xE1, 0xE7, 0xBF, 0xB5, 0x47, 0xFD, 0x06,
+	0x34, 0x3F, 0xFC, 0x13, 0xC7, 0x40, 0x1F, 0x5E, 0xFF, 0x00, 0xC3, 0xBB, 0x3F, 0x63, 0xAF, 0xFA,
+	0x23, 0xDF, 0xF9, 0x5E, 0xD4, 0x3F, 0xF9, 0x22, 0xB5, 0xFE, 0x1B, 0x7E, 0xC7, 0x3F, 0xB3, 0xB7,
+	0xC2, 0x2F, 0x17, 0xC1, 0xE3, 0xCF, 0x87, 0x1F, 0x0E, 0x3F, 0xB3, 0x75, 0x58, 0x63, 0x91, 0x21,
+	0xBA, 0xFE, 0xD8, 0xBB, 0x9F, 0x60, 0x91, 0x36, 0x3F, 0xC9, 0x2C, 0xAE, 0x9F, 0x76, 0xBE, 0x2B,
+	0xFF, 0x00, 0x87, 0x9E, 0xFE, 0xD5, 0x1F, 0xF4, 0x18, 0xD0, 0xFF, 0x00, 0xF0, 0x4F, 0x1D, 0x7A,
+	0x8F, 0xEC, 0x71, 0xFB, 0x72, 0xFC, 0x76, 0xF8, 0xDD, 0xF1, 0xFB, 0x49, 0xF8, 0x7D, 0xE3, 0xED,
+	0x47, 0x4A, 0x93, 0x4E, 0xBC, 0xB7, 0xBA, 0x92, 0x48, 0xED, 0x74, 0xBF, 0x2A, 0x5D, 0xD1, 0xDB,
+	0xBB, 0x8A, 0x00, 0xFA, 0xD3, 0xE2, 0x1F, 0xC3, 0xAF, 0x07, 0x7C, 0x59, 0xF0, 0x8D, 0xCF, 0x81,
+	0xBC, 0x7D, 0xA1, 0xFF, 0x00, 0x68, 0xE9, 0x57, 0xAD, 0x1B, 0x5D, 0x5A, 0x2D, 0xC4, 0x91, 0x89,
+	0x36, 0x32, 0xBA, 0xFC, 0xD1, 0xB2, 0x9F, 0xBC, 0x8B, 0xDC, 0x7F, 0x4A, 0xF3, 0x54, 0xFF, 0x00,
+	0x82, 0x75, 0x7E, 0xC7, 0x2A, 0xA1, 0x47, 0xC1, 0xFE, 0x83, 0x1F, 0xF2, 0x1E, 0xD4, 0x3F, 0xF9,
+	0x26, 0xB6, 0xBF, 0x6B, 0xEF, 0x8A, 0x1E, 0x2C, 0xF8, 0x31, 0xFB, 0x3D, 0xEB, 0x9F, 0x12, 0x7C,
+	0x12, 0xF0, 0x2E, 0xA5, 0xA7, 0xB5, 0xA0, 0xB7, 0x37, 0x31, 0x97, 0x5F, 0xDE, 0x5C, 0xC5, 0x1B,
+	0x02, 0xBD, 0xFE, 0x57, 0x6F, 0x7A, 0xF8, 0xA8, 0xFF, 0x00, 0xC1, 0x4F, 0x7F, 0x6A, 0x9E, 0xFA,
+	0xBE, 0x84, 0x3D, 0x97, 0x47, 0x4C, 0x0A, 0x03, 0xFA, 0xFE, 0xBE, 0x67, 0xD7, 0xBF, 0xF0, 0xEE,
+	0xCF, 0xD8, 0xEB, 0xFE, 0x88, 0xF7, 0xFE, 0x57, 0xB5, 0x0F, 0xFE, 0x48, 0xA3, 0xFE, 0x1D, 0xD9,
+	0xFB, 0x1D, 0x7F, 0xD1, 0x1E, 0xFF, 0x00, 0xCA, 0xF6, 0xA1, 0xFF, 0x00, 0xC9, 0x15, 0xF2, 0x17,
+	0xFC, 0x3C, 0xF7, 0xF6, 0xA8, 0xFF, 0x00, 0xA0, 0xC6, 0x87, 0xFF, 0x00, 0x82, 0x78, 0xE8, 0xFF,
+	0x00, 0x87, 0x9E, 0xFE, 0xD5, 0x1F, 0xF4, 0x18, 0xD0, 0xFF, 0x00, 0xF0, 0x4F, 0x1D, 0x00, 0x7D,
+	0x7B, 0xFF, 0x00, 0x0E, 0xEC, 0xFD, 0x8E, 0xBF, 0xE8, 0x8F, 0x7F, 0xE5, 0x7B, 0x50, 0xFF, 0x00,
+	0xE4, 0x8A, 0xB7, 0xE1, 0x4F, 0xD8, 0x63, 0xF6, 0x5D, 0xF0, 0x27, 0x8A, 0xAC, 0x3C, 0x6F, 0xE1,
+	0x2F, 0x85, 0x5F, 0x65, 0xD4, 0xF4, 0xBB, 0xC4, 0xB8, 0xB1, 0xB8, 0xFE, 0xDC, 0xBD, 0x93, 0x64,
+	0xB1, 0x93, 0xB5, 0xB6, 0x3C, 0xCE, 0xA7, 0xAF, 0x71, 0x5F, 0x1B, 0xFF, 0x00, 0xC3, 0xCF, 0x7F,
+	0x6A, 0x8F, 0xFA, 0x0C, 0x68, 0x7F, 0xF8, 0x27, 0x8E, 0xBA, 0xDF, 0x80, 0xFF, 0x00, 0xF0, 0x50,
+	0xBF, 0xDA, 0x33, 0xE2, 0x2F, 0xC6, 0x9F, 0x0B, 0x78, 0x1B, 0xC4, 0xFA, 0xA6, 0x8C, 0xDA, 0x7E,
+	0xAD, 0xAF, 0x5A, 0xDA, 0x5D, 0x2C, 0x7A, 0x4F, 0x97, 0x21, 0x47, 0x90, 0x0E, 0x0F, 0xE1, 0x40,
+	0x1F, 0x70, 0x78, 0xCB, 0xC2, 0xDA, 0x1F, 0x8D, 0x7C, 0x23, 0xAA, 0x78, 0x33, 0xC5, 0x10, 0x79,
+	0xFA, 0x6E, 0xA9, 0x61, 0x2D, 0x9E, 0xA0, 0x8B, 0x23, 0x27, 0x99, 0x0B, 0xAB, 0x23, 0x8C, 0xA7,
+	0x4F, 0x94, 0x9A, 0xF1, 0x18, 0xFF, 0x00, 0xE0, 0x97, 0xFF, 0x00, 0xB1, 0xFA, 0xAA, 0xAC, 0xBF,
+	0x0E, 0x6F, 0x77, 0x6D, 0xE7, 0x6E, 0xBD, 0x73, 0x8F, 0xFD, 0x0E, 0xBD, 0x53, 0xE3, 0xDF, 0x89,
+	0x35, 0xCF, 0x07, 0xFC, 0x0C, 0xF1, 0x87, 0x8C, 0x7C, 0x2F, 0x3A, 0xC3, 0xA8, 0xE9, 0x7E, 0x18,
+	0xBF, 0xBC, 0xD3, 0xE4, 0x91, 0x41, 0xD9, 0x34, 0x70, 0x3B, 0x21, 0xDA, 0xDF, 0x29, 0xF9, 0x82,
+	0xF0, 0x78, 0xAF, 0xCD, 0xB5, 0xFF, 0x00, 0x82, 0x97, 0x7E, 0xD9, 0xAC, 0x8B, 0xB3, 0xE2, 0xA4,
+	0x7B, 0x7A, 0xAF, 0xFC, 0x48, 0x2C, 0xFF, 0x00, 0xA4, 0x64, 0x7E, 0x44, 0x8A, 0xF0, 0x73, 0x8C,
+	0x76, 0x5B, 0x84, 0x9C, 0x56, 0x2E, 0x9F, 0x33, 0x6A, 0xEB, 0x4B, 0xD8, 0xFD, 0x1B, 0x81, 0xF8,
+	0x7F, 0x8B, 0xF3, 0x9C, 0x35, 0x7A, 0x99, 0x3E, 0x27, 0xD9, 0x42, 0x2D, 0x29, 0x7B, 0xF2, 0x85,
+	0xDB, 0x5A, 0x69, 0x14, 0xCF, 0xB4, 0xFF, 0x00, 0xE1, 0xD7, 0xDF, 0xB1, 0xF7, 0xFD, 0x13, 0x9B,
+	0xEF, 0xFC, 0x1F, 0xDC, 0x7F, 0xF1, 0xCA, 0x3F, 0xE1, 0xD7, 0xDF, 0xB1, 0xF7, 0xFD, 0x13, 0x9B,
+	0xEF, 0xFC, 0x1F, 0xDC, 0x7F, 0xF1, 0xCA, 0xF8, 0xB7, 0xFE, 0x1E, 0x5D, 0xFB, 0x67, 0xFF, 0x00,
+	0xD1, 0x53, 0x8B, 0xFF, 0x00, 0x09, 0xFB, 0x3F, 0xFE, 0x37, 0x47, 0xFC, 0x3C, 0xBB, 0xF6, 0xCF,
+	0xFF, 0x00, 0xA2, 0xA7, 0x1F, 0xFE, 0x08, 0x2D, 0x3F, 0xF8, 0xDD, 0x78, 0x7F, 0xDB, 0x1C, 0x37,
+	0xFF, 0x00, 0x3E, 0x17, 0xFE, 0x02, 0xBF, 0xCC, 0xFB, 0xAF, 0xF5, 0x23, 0xC5, 0x6F, 0xFA, 0x18,
+	0xFF, 0x00, 0xE5, 0x5A, 0x9F, 0xFC, 0x89, 0xF6, 0x8F, 0xFC, 0x3B, 0x03, 0xF6, 0x3D, 0xCF, 0xFC,
+	0x93, 0x9B, 0xEF, 0xFC, 0x1F, 0xDC, 0x7F, 0xF1, 0xCA, 0xE9, 0x3E, 0x13, 0x7E, 0xC3, 0xFF, 0x00,
+	0xB3, 0xD7, 0xC0, 0xDF, 0x1A, 0x43, 0xF1, 0x03, 0xE1, 0xD7, 0x84, 0xAE, 0x2D, 0x75, 0x48, 0x63,
+	0x92, 0x38, 0xE4, 0x93, 0x55, 0x9A, 0x6C, 0x2B, 0xA8, 0x56, 0xE2, 0x47, 0xC7, 0x40, 0x2B, 0xE0,
+	0x9F, 0xF8, 0x79, 0x77, 0xED, 0x9F, 0xFF, 0x00, 0x45, 0x4E, 0x3F, 0xFC, 0x10, 0x5A, 0x7F, 0xF1,
+	0xBA, 0xF6, 0x2F, 0xD8, 0x3F, 0xF6, 0xD0, 0xFD, 0xA3, 0x3E, 0x35, 0x7E, 0xD1, 0x16, 0x7E, 0x02,
+	0xF8, 0x91, 0xE3, 0x94, 0xBE, 0xD3, 0x2E, 0x34, 0xEB, 0xA9, 0x26, 0xB7, 0x5D, 0x2A, 0xDA, 0x1F,
+	0xDE, 0x22, 0x86, 0x53, 0x98, 0xD3, 0x3D, 0xEB, 0xAB, 0x03, 0x99, 0xE4, 0x15, 0xB1, 0x31, 0x8D,
+	0x1A, 0x36, 0x95, 0xD2, 0x5E, 0xEA, 0xFF, 0x00, 0x33, 0xC9, 0xCF, 0x38, 0x47, 0xC4, 0x8C, 0x1E,
+	0x53, 0x5E, 0xB6, 0x33, 0x1D, 0xCF, 0x4E, 0x31, 0xBC, 0xA3, 0xED, 0x26, 0xEE, 0xBD, 0x1A, 0x49,
+	0x9F, 0x69, 0x78, 0xF7, 0xE1, 0xEF, 0x85, 0x7E, 0x26, 0x68, 0x27, 0x43, 0xF1, 0x7D, 0x9B, 0x5C,
+	0x5A, 0xF9, 0xCB, 0x36, 0xC8, 0xE5, 0x65, 0x3B, 0xD4, 0x60, 0x1C, 0xA5, 0x71, 0x49, 0xFB, 0x1B,
+	0x7C, 0x05, 0xD8, 0x01, 0xF0, 0xC5, 0xD1, 0xE3, 0xFE, 0x82, 0x97, 0x3F, 0xFC, 0x5D, 0x58, 0xFD,
+	0xA9, 0x7E, 0x20, 0xF8, 0xAB, 0xE1, 0xDF, 0xC3, 0x25, 0xD7, 0x3C, 0x1F, 0x7C, 0xB6, 0xF7, 0xCD,
+	0xA8, 0xC7, 0x09, 0x99, 0xA2, 0x47, 0xC2, 0x94, 0x62, 0x7E, 0xF6, 0x07, 0xE7, 0x5F, 0x39, 0xFF,
+	0x00, 0xC3, 0x5E, 0x7E, 0xD0, 0xAB, 0xC4, 0x7E, 0x3F, 0x1B, 0x7F, 0x87, 0xFE, 0x25, 0xB6, 0x9F,
+	0xFC, 0x45, 0x7E, 0x59, 0xE2, 0x6F, 0x1B, 0x78, 0x5D, 0xC3, 0xFC, 0x40, 0xB0, 0xFC, 0x43, 0x97,
+	0xFB, 0x7A, 0xDC, 0xA9, 0xF3, 0x7B, 0x3A, 0x73, 0xB2, 0xE9, 0xAC, 0x9A, 0x67, 0xC5, 0x70, 0xF6,
+	0x51, 0xC4, 0xB9, 0x86, 0x01, 0xD4, 0xCB, 0xEB, 0x38, 0x42, 0xEF, 0xED, 0x49, 0x7E, 0x49, 0x9F,
+	0x42, 0xFF, 0x00, 0xC3, 0x1B, 0x7C, 0x04, 0xFF, 0x00, 0xA1, 0x5E, 0xEB, 0xFF, 0x00, 0x06, 0x97,
+	0x3F, 0xFC, 0x5D, 0x1F, 0xF0, 0xC6, 0xDF, 0x01, 0x3F, 0xE8, 0x57, 0xBA, 0xFF, 0x00, 0xC1, 0xA5,
+	0xCF, 0xFF, 0x00, 0x17, 0x5F, 0x3D, 0x7F, 0xC3, 0x5F, 0x7E, 0xD1, 0x1F, 0xF4, 0x3F, 0xFF, 0x00,
+	0xE5, 0x36, 0xD7, 0xFF, 0x00, 0x88, 0xA3, 0xFE, 0x1A, 0xFB, 0xF6, 0x88, 0xFF, 0x00, 0xA1, 0xFF,
+	0x00, 0xFF, 0x00, 0x29, 0xB6, 0xBF, 0xFC, 0x45, 0x7E, 0x79, 0xFF, 0x00, 0x11, 0x47, 0xE8, 0xFF,
+	0x00, 0xFF, 0x00, 0x42, 0x7F, 0xFC, 0xA3, 0x4F, 0xFF, 0x00, 0x92, 0x3D, 0xDF, 0xF5, 0x6F, 0x8E,
+	0x3F, 0xE8, 0x2B, 0xFF, 0x00, 0x27, 0x97, 0xF9, 0x1F, 0x42, 0xFF, 0x00, 0xC3, 0x1B, 0xFC, 0x04,
+	0xE8, 0x7C, 0x2D, 0x73, 0xFF, 0x00, 0x83, 0x4B, 0x9F, 0xFE, 0x2E, 0xBA, 0x4F, 0x86, 0x3F, 0x06,
+	0xBE, 0x1F, 0xFC, 0x27, 0x9A, 0xF5, 0xFC, 0x15, 0xA7, 0xCB, 0x6E, 0x6F, 0x95, 0x12, 0xE3, 0xCD,
+	0xB8, 0x91, 0xC1, 0x08, 0x64, 0x23, 0xEF, 0x93, 0xDD, 0xDA, 0xBE, 0x55, 0xFF, 0x00, 0x86, 0xBD,
+	0xFD, 0xA1, 0xFF, 0x00, 0xE8, 0x7E, 0xFF, 0x00, 0xCA, 0x65, 0xA7, 0xFF, 0x00, 0x11, 0x5E, 0xCD,
+	0xFB, 0x21, 0xFC, 0x5D, 0xF1, 0xFF, 0x00, 0xC5, 0x3F, 0xF8, 0x48, 0x0F, 0x8E, 0x35, 0xD1, 0x7C,
+	0xF6, 0x9F, 0x67, 0x36, 0xA4, 0xDB, 0x45, 0x1E, 0x37, 0xF9, 0xA1, 0xBF, 0xD5, 0x75, 0xFB, 0x9D,
+	0xEB, 0xEC, 0x38, 0x0B, 0x8F, 0xBC, 0x21, 0xCE, 0xB8, 0x9A, 0x8E, 0x17, 0x23, 0xCB, 0x3D, 0x96,
+	0x26, 0x57, 0xE5, 0x97, 0xB2, 0x84, 0x6D, 0xA6, 0xBA, 0xA9, 0x39, 0x6C, 0x79, 0x59, 0xD6, 0x4B,
+	0xC5, 0x58, 0x4C, 0xBA, 0x75, 0xB1, 0xB8, 0x87, 0x3A, 0x6A, 0xDA, 0x73, 0x49, 0xBF, 0xB9, 0xA3,
+	0xD0, 0xBE, 0x2F, 0x7E, 0xCF, 0x9F, 0x08, 0xFE, 0x3E, 0x5A, 0x69, 0xF6, 0x9F, 0x16, 0x7C, 0x25,
+	0xFD, 0xAD, 0x0E, 0x96, 0xD2, 0x35, 0x8C, 0x7F, 0x6D, 0x9A, 0x1D, 0x8C, 0xEB, 0xB5, 0x8E, 0x62,
+	0x64, 0xEC, 0x3D, 0x6B, 0x8B, 0xFF, 0x00, 0x87, 0x76, 0xFE, 0xC7, 0x4D, 0xF3, 0x1F, 0x83, 0xFD,
+	0x7F, 0xEA, 0x3F, 0xA8, 0x1F, 0xFD, 0xB9, 0xAE, 0x77, 0xFE, 0x0A, 0x01, 0xFB, 0x4A, 0x7C, 0x4D,
+	0xFD, 0x9C, 0xF4, 0x9F, 0x0A, 0xDD, 0xFC, 0x31, 0xB8, 0xB3, 0x8D, 0xB5, 0x4B, 0xAB, 0x88, 0xEF,
+	0x3E, 0xD9, 0x69, 0xE6, 0x0C, 0x46, 0xB1, 0x11, 0xC7, 0xFC, 0x0E, 0xBE, 0x63, 0x8B, 0xFE, 0x0A,
+	0x7F, 0xFB, 0x55, 0x34, 0x6A, 0xCF, 0xAC, 0x68, 0x5B, 0x8A, 0x82, 0xDB, 0x74, 0x74, 0xC5, 0x7F,
+	0x4A, 0xAD, 0x8F, 0x82, 0x3E, 0xBE, 0xFF, 0x00, 0x87, 0x76, 0x7E, 0xC7, 0x5F, 0xF4, 0x47, 0xBF,
+	0xF2, 0xBD, 0xA8, 0x7F, 0xF2, 0x45, 0x1F, 0xF0, 0xEE, 0xCF, 0xD8, 0xEB, 0xFE, 0x88, 0xF7, 0xFE,
+	0x57, 0xB5, 0x0F, 0xFE, 0x48, 0xAF, 0x90, 0xBF, 0xE1, 0xE7, 0xBF, 0xB5, 0x47, 0xFD, 0x06, 0x34,
+	0x3F, 0xFC, 0x13, 0xC7, 0x47, 0xFC, 0x3C, 0xF7, 0xF6, 0xA8, 0xFF, 0x00, 0xA0, 0xC6, 0x87, 0xFF,
+	0x00, 0x82, 0x78, 0xE9, 0x81, 0xF5, 0xEF, 0xFC, 0x3B, 0xB3, 0xF6, 0x3A, 0xFF, 0x00, 0xA2, 0x3D,
+	0xFF, 0x00, 0x95, 0xED, 0x43, 0xFF, 0x00, 0x92, 0x2B, 0xD1, 0xBE, 0x1A, 0x7C, 0x2E, 0xF0, 0x57,
+	0xC2, 0x0F, 0x0B, 0x45, 0xE0, 0x5F, 0x87, 0xFA, 0x1F, 0xF6, 0x7E, 0x95, 0x6E, 0xF2, 0xBD, 0xBD,
+	0xAF, 0x9D, 0x2C, 0xD8, 0x32, 0x36, 0xE6, 0x3B, 0xA4, 0x24, 0xF5, 0x3D, 0xC9, 0xFA, 0xD7, 0xE7,
+	0xE7, 0xFC, 0x3C, 0xF7, 0xF6, 0xA8, 0xFF, 0x00, 0xA0, 0xC6, 0x87, 0xFF, 0x00, 0x82, 0x78, 0xEB,
+	0xED, 0x0F, 0xD8, 0xD3, 0xE2, 0xD7, 0x8B, 0xBE, 0x36, 0xFC, 0x02, 0xD2, 0xFE, 0x23, 0xF8, 0xE6,
+	0x48, 0x64, 0xD4, 0x6E, 0xEE, 0xAE, 0xA3, 0x91, 0xAD, 0xA0, 0x11, 0xA9, 0x58, 0xE7, 0x65, 0x1F,
+	0x4E, 0x94, 0x01, 0xDF, 0xC5, 0xE1, 0xED, 0x2A, 0xCB, 0xC4, 0x37, 0x1E, 0x27, 0x81, 0x27, 0x37,
+	0x97, 0xD0, 0xC5, 0x0D, 0xC3, 0x35, 0xD3, 0x98, 0x8A, 0xC6, 0xC4, 0xA9, 0xF2, 0x99, 0xF6, 0x67,
+	0xE7, 0xFB, 0xCA, 0x32, 0x6B, 0x62, 0x30, 0xCB, 0x1A, 0x86, 0xEB, 0xB7, 0x9A, 0xF8, 0xF7, 0xF6,
+	0xE8, 0xFD, 0xB3, 0xBE, 0x36, 0x7C, 0x05, 0xF8, 0xD5, 0x0F, 0x81, 0x3E, 0x1F, 0x5F, 0x69, 0x90,
+	0xD8, 0xBE, 0x87, 0x6D, 0x71, 0x22, 0x5E, 0x58, 0x79, 0xAC, 0x5E, 0x49, 0x26, 0x5E, 0x3F, 0xEF,
+	0xDD, 0x79, 0x67, 0x84, 0x7F, 0xE0, 0xA9, 0x5F, 0x1F, 0xF4, 0xEF, 0x13, 0x5A, 0x5E, 0xF8, 0xCA,
+	0xCF, 0x47, 0xD4, 0xB4, 0xDD, 0xC1, 0x6F, 0x2D, 0x63, 0xB1, 0xFB, 0x3B, 0xB2, 0x9E, 0xAC, 0xAF,
+	0xFC, 0x2C, 0xBF, 0xDD, 0xEF, 0x53, 0x29, 0x72, 0xC5, 0xC9, 0x26, 0xEC, 0x9B, 0xB2, 0xDF, 0x4E,
+	0x8B, 0xCF, 0xC8, 0x7D, 0x52, 0x3F, 0x45, 0xE8, 0xAF, 0x9F, 0x7C, 0x29, 0xFB, 0x4C, 0xEA, 0x7F,
+	0x10, 0xB4, 0x81, 0xE2, 0x6F, 0x04, 0xF8, 0x86, 0x3B, 0x8B, 0x09, 0x5B, 0xE5, 0x6F, 0x25, 0x56,
+	0x48, 0xBF, 0xD8, 0x91, 0x7B, 0x30, 0xE8, 0x47, 0x63, 0x5A, 0x5F, 0xF0, 0xB8, 0xBC, 0x7A, 0x4E,
+	0x7E, 0xDF, 0x1F, 0xFD, 0xF9, 0x4A, 0xFE, 0x63, 0xCD, 0x3E, 0x95, 0x9E, 0x1F, 0xE4, 0xF9, 0x85,
+	0x5C, 0x1E, 0x2B, 0x0D, 0x89, 0x8D, 0x4A, 0x6D, 0xC5, 0xA7, 0x4E, 0x29, 0xDD, 0x3E, 0xCE, 0x68,
+	0xFA, 0x1A, 0x7C, 0x33, 0x8E, 0xAD, 0x05, 0x28, 0x4A, 0x2D, 0x3F, 0x3F, 0xF8, 0x07, 0xB8, 0x51,
+	0x5E, 0x21, 0xFF, 0x00, 0x0B, 0x8B, 0xC7, 0xBF, 0xF3, 0xFE, 0x9F, 0xF8, 0x0E, 0x94, 0x7F, 0xC2,
+	0xE2, 0xF1, 0xEF, 0xFC, 0xFF, 0x00, 0xAF, 0xFE, 0x03, 0xA5, 0x70, 0xFF, 0x00, 0xC4, 0xE0, 0x78,
+	0x63, 0xFF, 0x00, 0x3E, 0x71, 0x1F, 0xF8, 0x04, 0x3F, 0xF9, 0x61, 0x7F, 0xEA, 0xAE, 0x65, 0xDE,
+	0x3F, 0x7B, 0xFF, 0x00, 0x23, 0xDB, 0xE8, 0xAF, 0x10, 0xFF, 0x00, 0x85, 0xC5, 0xE3, 0xDF, 0xF9,
+	0xFF, 0x00, 0x5F, 0xFC, 0x07, 0x4A, 0x3F, 0xE1, 0x71, 0x78, 0xF7, 0xFE, 0x7F, 0xD7, 0xFF, 0x00,
+	0x01, 0xD2, 0x8F, 0xF8, 0x9C, 0x0F, 0x0C, 0x7F, 0xE7, 0xCE, 0x23, 0xFF, 0x00, 0x00, 0x87, 0xFF,
+	0x00, 0x2C, 0x0F, 0xF5, 0x57, 0x32, 0xEF, 0x1F, 0xBD, 0xFF, 0x00, 0x91, 0xED, 0xF4, 0x57, 0x88,
+	0x7F, 0xC2, 0xE2, 0xF1, 0xEF, 0xFC, 0xFF, 0x00, 0xAF, 0xFE, 0x03, 0xA5, 0x1F, 0xF0, 0xB8, 0xBC,
+	0x7B, 0xFF, 0x00, 0x3F, 0xEB, 0xFF, 0x00, 0x80, 0xE9, 0x47, 0xFC, 0x4E, 0x07, 0x86, 0x3F, 0xF3,
+	0xE7, 0x11, 0xFF, 0x00, 0x80, 0x43, 0xFF, 0x00, 0x96, 0x07, 0xFA, 0xAB, 0x99, 0x77, 0x8F, 0xDE,
+	0xFF, 0x00, 0xC8, 0xF6, 0xFA, 0xFE, 0x6B, 0xFF, 0x00, 0xE0, 0xED, 0x1F, 0xF9, 0x4A, 0x0E, 0x97,
+	0xFF, 0x00, 0x64, 0xA3, 0x49, 0xFF, 0x00, 0xD2, 0xCB, 0xEA, 0xFD, 0xE0, 0xFF, 0x00, 0x85, 0xC1,
+	0xE3, 0xDF, 0xF9, 0xFF, 0x00, 0x5F, 0xFC, 0x07, 0x4A, 0xF9, 0x6B, 0xF6, 0xCB, 0xFF, 0x00, 0x82,
+	0x69, 0x7E, 0xC7, 0xFF, 0x00, 0xB7, 0xA7, 0xC5, 0xA8, 0x7E, 0x35, 0x7E, 0xD3, 0x5F, 0x0F, 0xEF,
+	0xB5, 0x8F, 0x11, 0x41, 0xA3, 0xC5, 0xA5, 0x2D, 0xE5, 0x9E, 0xB7, 0x73, 0x6A, 0xAB, 0x6B, 0x0B,
+	0xC9, 0x2A, 0x29, 0x48, 0x24, 0x0B, 0xF7, 0xA6, 0x7E, 0x58, 0x54, 0xBF, 0xA5, 0xF7, 0x86, 0x35,
+	0x34, 0xF6, 0x38, 0x8F, 0xFC, 0x02, 0x1F, 0xFC, 0xB0, 0xD6, 0x8F, 0x0C, 0xE6, 0x14, 0xEA, 0x5D,
+	0xB8, 0xFD, 0xEF, 0xFC, 0x8F, 0xE6, 0x20, 0xF5, 0xA2, 0xBF, 0xA2, 0x21, 0xFF, 0x00, 0x06, 0xFC,
+	0x7F, 0xC1, 0x2F, 0x88, 0xC9, 0xF8, 0x2B, 0xAB, 0x7E, 0x1E, 0x31, 0xBF, 0xFE, 0x92, 0xD1, 0xFF,
+	0x00, 0x10, 0xFB, 0xFF, 0x00, 0xC1, 0x2F, 0x7F, 0xE8, 0x8A, 0xEB, 0x1F, 0xF8, 0x58, 0x6A, 0x1F,
+	0xFC, 0x76, 0xB3, 0xFF, 0x00, 0x89, 0xBA, 0xF0, 0xC7, 0xFE, 0x7D, 0x62, 0x3F, 0xF0, 0x08, 0x7F,
+	0xF2, 0xC3, 0xB3, 0xFD, 0x5F, 0xC6, 0xF7, 0x8F, 0xDF, 0xFF, 0x00, 0x00, 0xFE, 0x77, 0x68, 0xAF,
+	0xE8, 0x8B, 0xFE, 0x21, 0xF7, 0xFF, 0x00, 0x82, 0x5E, 0xFF, 0x00, 0xD1, 0x15, 0xD6, 0x3F, 0xF0,
+	0xB0, 0xD4, 0x3F, 0xF8, 0xED, 0x1F, 0xF1, 0x0F, 0xBF, 0xFC, 0x12, 0xF7, 0xFE, 0x88, 0xAE, 0xB1,
+	0xFF, 0x00, 0x85, 0x86, 0xA1, 0xFF, 0x00, 0xC7, 0x68, 0xFF, 0x00, 0x89, 0xBA, 0xF0, 0xC3, 0xFE,
+	0x7D, 0x62, 0x3F, 0xF0, 0x08, 0x7F, 0xF2, 0xC0, 0xFF, 0x00, 0x57, 0xF1, 0xBD, 0xD7, 0xDF, 0xFF,
+	0x00, 0x00, 0xFE, 0x77, 0x68, 0xAF, 0xE8, 0x8B, 0xFE, 0x21, 0xF7, 0xFF, 0x00, 0x82, 0x5E, 0xFF,
+	0x00, 0xD1, 0x15, 0xD6, 0x3F, 0xF0, 0xB0, 0xD4, 0x3F, 0xF8, 0xED, 0x1F, 0xF1, 0x0F, 0xBF, 0xFC,
+	0x12, 0xF7, 0xFE, 0x88, 0xAE, 0xB1, 0xFF, 0x00, 0x85, 0x86, 0xA1, 0xFF, 0x00, 0xC7, 0x68, 0xFF,
+	0x00, 0x89, 0xBA, 0xF0, 0xC3, 0xFE, 0x7D, 0x62, 0x3F, 0xF0, 0x08, 0x7F, 0xF2, 0xC0, 0xFF, 0x00,
+	0x57, 0xF1, 0xBD, 0xD7, 0xDF, 0xFF, 0x00, 0x00, 0xFE, 0x77, 0x68, 0xAF, 0xE8, 0x8B, 0xFE, 0x21,
+	0xF7, 0xFF, 0x00, 0x82, 0x5E, 0xFF, 0x00, 0xD1, 0x15, 0xD6, 0x3F, 0xF0, 0xB0, 0xD4, 0x3F, 0xF8,
+	0xED, 0x1F, 0xF1, 0x0F, 0xBF, 0xFC, 0x12, 0xF7, 0xFE, 0x88, 0xAE, 0xB1, 0xFF, 0x00, 0x85, 0x86,
+	0xA1, 0xFF, 0x00, 0xC7, 0x68, 0xFF, 0x00, 0x89, 0xBA, 0xF0, 0xC3, 0xFE, 0x7D, 0x62, 0x3F, 0xF0,
+	0x08, 0x7F, 0xF2, 0xC0, 0xFF, 0x00, 0x57, 0xF1, 0xBD, 0xD7, 0xDF, 0xFF, 0x00, 0x00, 0xFE, 0x77,
+	0x68, 0xAF, 0xE8, 0x8B, 0xFE, 0x21, 0xF7, 0xFF, 0x00, 0x82, 0x5E, 0xFF, 0x00, 0xD1, 0x15, 0xD6,
+	0x3F, 0xF0, 0xB0, 0xD4, 0x3F, 0xF8, 0xED, 0x1F, 0xF1, 0x0F, 0xBF, 0xFC, 0x12, 0xF7, 0xFE, 0x88,
+	0xAE, 0xB1, 0xFF, 0x00, 0x85, 0x86, 0xA1, 0xFF, 0x00, 0xC7, 0x68, 0xFF, 0x00, 0x89, 0xBA, 0xF0,
+	0xC3, 0xFE, 0x7D, 0x62, 0x3F, 0xF0, 0x08, 0x7F, 0xF2, 0xC0, 0xFF, 0x00, 0x57, 0xF1, 0xBD, 0xD7,
+	0xDF, 0xFF, 0x00, 0x00, 0xFE, 0x77, 0x68, 0xAF, 0xE8, 0x8B, 0xFE, 0x21, 0xF8, 0xFF, 0x00, 0x82,
+	0x5E, 0xF5, 0xFF, 0x00, 0x85, 0x2B, 0xAC, 0x7F, 0xE1, 0x61, 0xA8, 0x7F, 0xF1, 0xDA, 0xFC, 0xB9,
+	0xFD, 0xB8, 0xFF, 0x00, 0x62, 0xEF, 0xD9, 0xF7, 0xE0, 0xB7, 0xED, 0x57, 0xE3, 0x0F, 0x86, 0x7F,
+	0x0F, 0xBC, 0x27, 0x75, 0x65, 0xA2, 0xE9, 0x37, 0xD0, 0x47, 0x65, 0x6A, 0xDA, 0x9C, 0xB2, 0xE1,
+	0x4D, 0xBC, 0x2E, 0xD9, 0x2C, 0x49, 0x27, 0x3D, 0xC9, 0x24, 0xF7, 0xAF, 0xB3, 0xE0, 0xAF, 0xA4,
+	0x07, 0x04, 0xF1, 0xE6, 0x3E, 0xA6, 0x13, 0x2E, 0xA7, 0x59, 0x4A, 0x0B, 0x99, 0xF3, 0xC6, 0x29,
+	0x5A, 0xF6, 0xD2, 0xD3, 0x95, 0xCF, 0xAE, 0xE0, 0xDF, 0x0A, 0xF8, 0x93, 0x8E, 0x33, 0x19, 0x60,
+	0xB0, 0x12, 0x82, 0x9C, 0x63, 0xCC, 0xF9, 0x9B, 0x4A, 0xD7, 0x4B, 0x4B, 0x27, 0xDC, 0xF8, 0x8E,
+	0x8A, 0xFA, 0x04, 0x7C, 0x04, 0xF8, 0x70, 0x83, 0x64, 0x9A, 0x4D, 0xC6, 0xE5, 0xE1, 0xBF, 0xD2,
+	0x1F, 0xAD, 0x2F, 0xFC, 0x28, 0x6F, 0x86, 0xDF, 0xF4, 0x09, 0xB8, 0xFF, 0x00, 0xC0, 0x87, 0xAF,
+	0xD3, 0x7F, 0xD6, 0xAC, 0xBF, 0xB4, 0xBE, 0xE3, 0xF4, 0xEF, 0xF8, 0x95, 0x5F, 0x11, 0x3F, 0xE7,
+	0xF5, 0x0F, 0xFC, 0x0E, 0x5F, 0xFC, 0x81, 0xF3, 0xED, 0x15, 0xF4, 0x17, 0xFC, 0x28, 0x6F, 0x86,
+	0xDF, 0xF4, 0x09, 0xB8, 0xFF, 0x00, 0xC0, 0x87, 0xA3, 0xFE, 0x14, 0x37, 0xC3, 0x6F, 0xFA, 0x04,
+	0xDC, 0x7F, 0xE0, 0x43, 0xD1, 0xFE, 0xB5, 0x65, 0xFD, 0xA5, 0xF7, 0x07, 0xFC, 0x4A, 0xAF, 0x88,
+	0x9F, 0xF3, 0xFA, 0x87, 0xFE, 0x07, 0x2F, 0xFE, 0x40, 0xF9, 0xF6, 0x8A, 0xFA, 0xAF, 0xE0, 0x97,
+	0xEC, 0xB3, 0xF0, 0x6B, 0xC6, 0x9F, 0x19, 0x7C, 0x23, 0xE1, 0x1F, 0x10, 0xE8, 0x57, 0x13, 0x59,
+	0x6A, 0xDE, 0x26, 0xB1, 0xB1, 0xBE, 0x85, 0x2F, 0xA6, 0x8C, 0xBC, 0x53, 0x4C, 0xAB, 0x8D, 0xD1,
+	0xBE, 0x47, 0xDF, 0xAF, 0xD7, 0x54, 0xFF, 0x00, 0x83, 0x7E, 0xBF, 0xE0, 0x97, 0xAC, 0x8A, 0xC3,
+	0xE0, 0xA6, 0xAD, 0xF3, 0x0C, 0xFC, 0xBE, 0x30, 0xD4, 0x30, 0x3F, 0xF2, 0x2D, 0x7E, 0x73, 0xC7,
+	0x1E, 0x3C, 0x70, 0x6F, 0x00, 0xE2, 0x28, 0xD2, 0xCC, 0xA9, 0xD6, 0x6E, 0xAA, 0x6E, 0x3C, 0x91,
+	0x8B, 0x56, 0x5A, 0x3B, 0xDE, 0x71, 0x3F, 0x3A, 0xE3, 0x6F, 0x08, 0x78, 0x9B, 0x80, 0xF1, 0x14,
+	0x68, 0x66, 0x13, 0xA6, 0xE5, 0x51, 0x39, 0x2E, 0x59, 0x36, 0xAC, 0x9D, 0xB7, 0x71, 0x47, 0xF3,
+	0xBF, 0x45, 0x7F, 0x44, 0x5F, 0xF1, 0x0F, 0xBF, 0xFC, 0x12, 0xF7, 0xFE, 0x88, 0xAE, 0xB1, 0xFF,
+	0x00, 0x85, 0x86, 0xA1, 0xFF, 0x00, 0xC7, 0x68, 0xFF, 0x00, 0x88, 0x7D, 0xFF, 0x00, 0xE0, 0x97,
+	0xBF, 0xF4, 0x45, 0x75, 0x8F, 0xFC, 0x2C, 0x35, 0x0F, 0xFE, 0x3B, 0x5F, 0x0B, 0xFF, 0x00, 0x13,
+	0x75, 0xE1, 0x87, 0xFC, 0xFA, 0xC4, 0x7F, 0xE0, 0x10, 0xFF, 0x00, 0xE5, 0x87, 0xC4, 0x7F, 0xAB,
+	0xF8, 0xDE, 0xEB, 0xEF, 0x3F, 0x9D, 0xDA, 0x2B, 0xFA, 0x22, 0xFF, 0x00, 0x88, 0x7D, 0xFF, 0x00,
+	0xE0, 0x97, 0xBF, 0xF4, 0x45, 0x75, 0x8F, 0xFC, 0x2C, 0x35, 0x0F, 0xFE, 0x3B, 0x47, 0xFC, 0x43,
+	0xEF, 0xFF, 0x00, 0x04, 0xBD, 0xFF, 0x00, 0xA2, 0x2B, 0xAC, 0x7F, 0xE1, 0x61, 0xA8, 0x7F, 0xF1,
+	0xDA, 0x3F, 0xE2, 0x6E, 0xBC, 0x30, 0xFF, 0x00, 0x9F, 0x58, 0x8F, 0xFC, 0x02, 0x1F, 0xFC, 0xB0,
+	0x3F, 0xD5, 0xFC, 0x6F, 0x75, 0xF7, 0xFF, 0x00, 0xC0, 0x3F, 0x9D, 0xDA, 0x2B, 0xFA, 0x22, 0xFF,
+	0x00, 0x88, 0x7D, 0xFF, 0x00, 0xE0, 0x97, 0xBF, 0xF4, 0x45, 0x75, 0x8F, 0xFC, 0x2C, 0x35, 0x0F,
+	0xFE, 0x3B, 0x47, 0xFC, 0x43, 0xEF, 0xFF, 0x00, 0x04, 0xBD, 0xFF, 0x00, 0xA2, 0x2B, 0xAC, 0x7F,
+	0xE1, 0x61, 0xA8, 0x7F, 0xF1, 0xDA, 0x3F, 0xE2, 0x6E, 0xBC, 0x30, 0xFF, 0x00, 0x9F, 0x58, 0x8F,
+	0xFC, 0x02, 0x1F, 0xFC, 0xB0, 0x3F, 0xD5, 0xFC, 0x6F, 0x75, 0xF7, 0xFF, 0x00, 0xC0, 0x3F, 0x9D,
+	0xDA, 0x2B, 0xFA, 0x22, 0xFF, 0x00, 0x88, 0x7D, 0xFF, 0x00, 0xE0, 0x97, 0xBF, 0xF4, 0x45, 0x75,
+	0x8F, 0xFC, 0x2C, 0x35, 0x0F, 0xFE, 0x3B, 0x47, 0xFC, 0x43, 0xEF, 0xFF, 0x00, 0x04, 0xBD, 0xFF,
+	0x00, 0xA2, 0x2B, 0xAC, 0x7F, 0xE1, 0x61, 0xA8, 0x7F, 0xF1, 0xDA, 0x3F, 0xE2, 0x6E, 0xBC, 0x30,
+	0xFF, 0x00, 0x9F, 0x58, 0x8F, 0xFC, 0x02, 0x1F, 0xFC, 0xB0, 0x3F, 0xD5, 0xFC, 0x6F, 0x75, 0xF7,
+	0xFF, 0x00, 0xC0, 0x3F, 0x9D, 0xDA, 0x2B, 0xFA, 0x22, 0xFF, 0x00, 0x88, 0x7D, 0xFF, 0x00, 0xE0,
+	0x97, 0xBF, 0xF4, 0x45, 0x75, 0x8F, 0xFC, 0x2C, 0x35, 0x0F, 0xFE, 0x3B, 0x47, 0xFC, 0x43, 0xEF,
+	0xFF, 0x00, 0x04, 0xBD, 0xFF, 0x00, 0xA2, 0x2B, 0xAC, 0x7F, 0xE1, 0x61, 0xA8, 0x7F, 0xF1, 0xDA,
+	0x3F, 0xE2, 0x6E, 0xBC, 0x30, 0xFF, 0x00, 0x9F, 0x58, 0x8F, 0xFC, 0x02, 0x1F, 0xFC, 0xB0, 0x3F,
+	0xD5, 0xFC, 0x6F, 0x75, 0xF7, 0xFF, 0x00, 0xC0, 0x3F, 0x1A, 0xFF, 0x00, 0xE0, 0x90, 0x9F, 0xF2,
+	0x94, 0x5F, 0x80, 0x3F, 0xF6, 0x55, 0xB4, 0x7F, 0xFD, 0x29, 0x4A, 0xFE, 0xBF, 0x97, 0xEE, 0xD7,
+	0xE5, 0xDF, 0xC1, 0x6F, 0xF8, 0x22, 0xD7, 0xFC, 0x13, 0xDB, 0xF6, 0x7C, 0xF8, 0xB1, 0xE1, 0xDF,
+	0x8D, 0xFF, 0x00, 0x0B, 0xBE, 0x12, 0xEA, 0x36, 0x9E, 0x23, 0xF0, 0xAE, 0xAF, 0x1E, 0xA7, 0xA1,
+	0xDD, 0x49, 0xE2, 0xAB, 0xE9, 0x92, 0x2B, 0xA8, 0x99, 0x4A, 0x13, 0x1B, 0x49, 0xB1, 0xB9, 0x53,
+	0xF7, 0xBF, 0x1A, 0xFB, 0x53, 0xFE, 0x17, 0x07, 0x8F, 0x3F, 0xE8, 0x24, 0x8D, 0xFE, 0xD0, 0xB7,
+	0x4E, 0x7D, 0xFA, 0xD5, 0xC7, 0xE9, 0x7D, 0xE1, 0x8C, 0x3F, 0xE5, 0xCE, 0x23, 0xFF, 0x00, 0x00,
+	0x87, 0xFF, 0x00, 0x2C, 0x39, 0x2B, 0x70, 0xCE, 0x61, 0x52, 0x5A, 0x38, 0xFD, 0xEF, 0xFC, 0x8F,
+	0x70, 0xA2, 0xBC, 0x3F, 0xFE, 0x17, 0x17, 0x8F, 0x7F, 0xE7, 0xFD, 0x3F, 0xF0, 0x1D, 0x29, 0x7F,
+	0xE1, 0x71, 0x78, 0xF7, 0xFE, 0x7F, 0xD7, 0xFF, 0x00, 0x01, 0xD2, 0xAF, 0xFE, 0x27, 0x03, 0xC3,
+	0x1F, 0xF9, 0xF3, 0x88, 0xFF, 0x00, 0xC0, 0x21, 0xFF, 0x00, 0xCB, 0x0C, 0x7F, 0xD5, 0x5C, 0xCB,
+	0xBC, 0x7E, 0xF7, 0xFE, 0x47, 0xB7, 0xD1, 0x5E, 0x21, 0xFF, 0x00, 0x0B, 0x8B, 0xC7, 0xBF, 0xF3,
+	0xFE, 0xBF, 0xF8, 0x0E, 0x94, 0x7F, 0xC2, 0xE2, 0xF1, 0xEF, 0xFC, 0xFF, 0x00, 0xAF, 0xFE, 0x03,
+	0xA5, 0x1F, 0xF1, 0x38, 0x1E, 0x18, 0xFF, 0x00, 0xCF, 0x9C, 0x47, 0xFE, 0x01, 0x0F, 0xFE, 0x58,
+	0x1F, 0xEA, 0xAE, 0x65, 0xDE, 0x3F, 0x7B, 0xFF, 0x00, 0x23, 0xDB, 0xE8, 0xAF, 0x10, 0xFF, 0x00,
+	0x85, 0xC5, 0xE3, 0xDF, 0xF9, 0xFF, 0x00, 0x5F, 0xFC, 0x07, 0x4A, 0x3F, 0xE1, 0x71, 0x78, 0xF7,
+	0xFE, 0x7F, 0xD7, 0xFF, 0x00, 0x01, 0xD2, 0x8F, 0xF8, 0x9C, 0x0F, 0x0C, 0x7F, 0xE7, 0xCE, 0x23,
+	0xFF, 0x00, 0x00, 0x87, 0xFF, 0x00, 0x2C, 0x0F, 0xF5, 0x57, 0x32, 0xEF, 0x1F, 0xBD, 0xFF, 0x00,
+	0x91, 0xED, 0xF4, 0x57, 0x87, 0xFF, 0x00, 0xC2, 0xE0, 0xF1, 0xF7, 0xF0, 0xDF, 0x2F, 0xFD, 0xF8,
+	0x4A, 0xA9, 0xAD, 0xFC, 0x7B, 0xF1, 0x27, 0x87, 0x74, 0xDB, 0x8D, 0x7B, 0x5F, 0xF1, 0x3D, 0xAD,
+	0x9D, 0xA4, 0x11, 0xE5, 0xEE, 0x2E, 0x22, 0x41, 0x1C, 0x38, 0xEC, 0x5B, 0xFB, 0xC7, 0xB2, 0xD6,
+	0xD8, 0x6F, 0xA5, 0xB7, 0x87, 0x38, 0xCC, 0x44, 0x68, 0x50, 0xC3, 0xE2, 0x65, 0x39, 0x34, 0x94,
+	0x54, 0x22, 0xDB, 0x6F, 0x44, 0xB4, 0x9E, 0xE2, 0x97, 0x0B, 0xE3, 0xE9, 0xC6, 0xF2, 0x94, 0x57,
+	0xCF, 0xFE, 0x01, 0xEF, 0x75, 0x1B, 0xC1, 0x1C, 0x93, 0x25, 0xC3, 0x93, 0xBA, 0x3C, 0xED, 0xF9,
+	0xEB, 0xF3, 0xE7, 0xE2, 0x6F, 0xFC, 0x15, 0x2F, 0xE3, 0x15, 0xC7, 0x88, 0xCD, 0xAF, 0xC2, 0x9B,
+	0x4D, 0x3E, 0xC7, 0x4B, 0xB7, 0x8C, 0x47, 0x1C, 0xFA, 0x85, 0xA8, 0x9A, 0x6B, 0xB9, 0x07, 0x0D,
+	0x23, 0x01, 0xF7, 0x11, 0xBA, 0xA8, 0xEC, 0x0E, 0x2B, 0xD1, 0x3F, 0x61, 0x8F, 0xDB, 0x47, 0xE3,
+	0x77, 0xC7, 0xFF, 0x00, 0x8D, 0x33, 0x78, 0x23, 0xE2, 0x1D, 0xF6, 0x9C, 0xD6, 0x23, 0x43, 0xB8,
+	0xBB, 0x8D, 0x6D, 0x74, 0xCF, 0x28, 0x89, 0x56, 0x54, 0x51, 0xF3, 0x77, 0xE1, 0xAB, 0xFA, 0x83,
+	0x0D, 0x5B, 0xEB, 0x18, 0x78, 0x55, 0xE5, 0x71, 0xE6, 0x49, 0xD9, 0xEE, 0xAE, 0xAF, 0x67, 0xE6,
+	0xB6, 0x67, 0xCE, 0xCA, 0x3C, 0xB2, 0x71, 0xEC, 0x7D, 0x3F, 0xF1, 0x33, 0xE1, 0x87, 0x82, 0x3E,
+	0x30, 0x78, 0x66, 0x6F, 0x03, 0xFC, 0x44, 0xD1, 0x5B, 0x50, 0xD2, 0xAE, 0x5A, 0x36, 0x9A, 0xD3,
+	0xED, 0x52, 0x43, 0x96, 0x46, 0xDC, 0x0E, 0x51, 0x91, 0xBF, 0x23, 0x5E, 0x72, 0x3F, 0xE0, 0x9D,
+	0x9F, 0xB1, 0xD9, 0x19, 0x3F, 0x07, 0xBF, 0xF2, 0xBD, 0xA8, 0x7F, 0xF2, 0x4D, 0x6B, 0xFE, 0xD9,
+	0x9F, 0x16, 0x7C, 0x5B, 0xF0, 0x4F, 0xF6, 0x7E, 0xD5, 0x7E, 0x21, 0xF8, 0x12, 0x78, 0x57, 0x51,
+	0xB4, 0x9A, 0xD9, 0x21, 0x37, 0x50, 0xF9, 0x8B, 0x89, 0x26, 0x54, 0x3F, 0xFA, 0x15, 0x7C, 0x59,
+	0xFF, 0x00, 0x0F, 0x3E, 0xFD, 0xAA, 0x0F, 0x3F, 0xDA, 0xFA, 0x1F, 0xFE, 0x09, 0xD2, 0xB6, 0x24,
+	0xFA, 0xF7, 0xFE, 0x1D, 0xD9, 0xFB, 0x1D, 0x7F, 0xD1, 0x1E, 0xFF, 0x00, 0xCA, 0xF6, 0xA1, 0xFF,
+	0x00, 0xC9, 0x14, 0x7F, 0xC3, 0xBB, 0x3F, 0x63, 0xAF, 0xFA, 0x23, 0xDF, 0xF9, 0x5E, 0xD4, 0x3F,
+	0xF9, 0x22, 0xBE, 0x42, 0xFF, 0x00, 0x87, 0x9E, 0xFE, 0xD5, 0x1F, 0xF4, 0x18, 0xD0, 0xFF, 0x00,
+	0xF0, 0x4F, 0x1D, 0x1F, 0xF0, 0xF3, 0xDF, 0xDA, 0xA3, 0xFE, 0x83, 0x1A, 0x1F, 0xFE, 0x09, 0xE3,
+	0xA0, 0x0F, 0xAF, 0x7F, 0xE1, 0xDD, 0x9F, 0xB1, 0xD7, 0xFD, 0x11, 0xEF, 0xFC, 0xAF, 0x6A, 0x1F,
+	0xFC, 0x91, 0x5D, 0x97, 0xC1, 0xFF, 0x00, 0x80, 0x1F, 0x09, 0x7E, 0x03, 0xAD, 0xF5, 0x9F, 0xC2,
+	0x8F, 0x0B, 0x7F, 0x65, 0x43, 0xA9, 0x48, 0xAF, 0x7B, 0x19, 0xBD, 0x9E, 0xE3, 0xCC, 0x64, 0x1B,
+	0x54, 0xE6, 0x69, 0x5F, 0x1F, 0x7B, 0xB5, 0x7C, 0x21, 0xFF, 0x00, 0x0F, 0x3D, 0xFD, 0xAA, 0x3F,
+	0xE8, 0x31, 0xA1, 0xFF, 0x00, 0xE0, 0x9E, 0x3A, 0xFA, 0x6B, 0xFE, 0x09, 0xFD, 0xFB, 0x4A, 0xFC,
+	0x50, 0xFD, 0xA3, 0xF4, 0x9F, 0x14, 0x5E, 0x7C, 0x48, 0xBA, 0xB1, 0x92, 0x4D, 0x1E, 0xE6, 0xD1,
+	0x2C, 0xFE, 0xC7, 0x67, 0xE5, 0x8C, 0x3A, 0xBB, 0x1C, 0xE3, 0xFD, 0xDA, 0x00, 0xF5, 0x7F, 0x89,
+	0x5F, 0x05, 0xBC, 0x0B, 0xF1, 0x5E, 0xE2, 0xD6, 0x7F, 0x1C, 0x69, 0x92, 0x5C, 0x1B, 0x2F, 0x30,
+	0x5B, 0xB4, 0x77, 0x0C, 0xB8, 0x32, 0x6C, 0xCF, 0xDC, 0xC1, 0xFE, 0x0A, 0xE7, 0x47, 0xEC, 0x71,
+	0xF0, 0x19, 0xFE, 0x63, 0xE1, 0x8B, 0xAF, 0x5C, 0xFF, 0x00, 0x6A, 0x5C, 0xF3, 0xFF, 0x00, 0x8F,
+	0xD6, 0x07, 0xED, 0x83, 0xF1, 0x77, 0xC7, 0xFF, 0x00, 0x0B, 0x65, 0xD0, 0xFF, 0x00, 0xE1, 0x06,
+	0xD7, 0x16, 0xC5, 0x6F, 0x8D, 0xCA, 0xDD, 0x9F, 0xB2, 0xC4, 0xF9, 0x54, 0x08, 0x47, 0xFA, 0xC4,
+	0x23, 0xF8, 0xEB, 0xC6, 0x17, 0xF6, 0xBA, 0xFD, 0xA1, 0x55, 0x54, 0x2F, 0x8F, 0xB8, 0x5E, 0x07,
+	0xFC, 0x4B, 0x6D, 0x3F, 0xA2, 0x57, 0xF3, 0x4F, 0x1E, 0x71, 0xE7, 0x84, 0x39, 0x3F, 0x13, 0x56,
+	0xC2, 0xE7, 0x79, 0x77, 0xB5, 0xC4, 0x46, 0xDC, 0xD3, 0xF6, 0x54, 0xE5, 0x7D, 0x34, 0xD6, 0x4D,
+	0x33, 0xEF, 0x72, 0x5C, 0x97, 0x8A, 0xB1, 0x79, 0x6D, 0x3A, 0xB8, 0x2A, 0xFC, 0xB4, 0xDD, 0xD2,
+	0xF7, 0xA4, 0xB5, 0xF9, 0x23, 0xE8, 0x6F, 0xF8, 0x63, 0x6F, 0x80, 0x9F, 0xF4, 0x2B, 0xDD, 0x7F,
+	0xE0, 0xD2, 0xE7, 0xFF, 0x00, 0x8B, 0xA3, 0xFE, 0x18, 0xDB, 0xE0, 0x27, 0xFD, 0x0A, 0xF7, 0x5F,
+	0xF8, 0x34, 0xB9, 0xFF, 0x00, 0xE2, 0xEB, 0xE7, 0x9F, 0xF8, 0x6B, 0xDF, 0xDA, 0x23, 0xFE, 0x87,
+	0xEF, 0xFC, 0xA6, 0xDA, 0x7F, 0xF1, 0x14, 0xBF, 0xF0, 0xD7, 0xDF, 0xB4, 0x47, 0xFD, 0x0F, 0xFF,
+	0x00, 0xF9, 0x4D, 0xB5, 0xFF, 0x00, 0xE2, 0x2B, 0xE3, 0xBF, 0xE2, 0x28, 0xFD, 0x1F, 0xFF, 0x00,
+	0xE8, 0x4F, 0xFF, 0x00, 0x94, 0x69, 0xFF, 0x00, 0xF2, 0x47, 0xAB, 0xFE, 0xAD, 0xF1, 0xC7, 0xFD,
+	0x05, 0x7F, 0xE4, 0xF2, 0xFF, 0x00, 0x23, 0xE8, 0x53, 0xFB, 0x1B, 0xFC, 0x05, 0xCE, 0x07, 0x85,
+	0x2E, 0x7E, 0xBF, 0xDA, 0xB7, 0x3F, 0xFC, 0x5D, 0x76, 0xDF, 0x0F, 0xFE, 0x1D, 0x78, 0x5F, 0xE1,
+	0x96, 0x84, 0xBE, 0x1C, 0xF0, 0x95, 0xA3, 0x5B, 0x5A, 0x89, 0x9A, 0x40, 0xB2, 0x4C, 0x64, 0xF9,
+	0x98, 0xF3, 0xD7, 0x93, 0xF8, 0xF3, 0x5F, 0x21, 0xFF, 0x00, 0xC3, 0x5E, 0x7E, 0xD0, 0xFF, 0x00,
+	0xF4, 0x3F, 0x7F, 0xE5, 0x36, 0xD7, 0xFF, 0x00, 0x88, 0xAF, 0xA3, 0xBF, 0x65, 0x6F, 0x1E, 0xF8,
+	0xAB, 0xE2, 0x3F, 0xC3, 0x2F, 0xF8, 0x48, 0xFC, 0x63, 0xA8, 0xAD, 0xC5, 0xF7, 0xF6, 0x84, 0xD1,
+	0x99, 0x84, 0x02, 0x3C, 0xA8, 0x2B, 0x8E, 0x07, 0x1F, 0x97, 0x15, 0xFA, 0x1F, 0x86, 0xBC, 0x6B,
+	0xE1, 0x6E, 0x7F, 0xC4, 0x3F, 0x55, 0xE1, 0xDC, 0x07, 0xB0, 0xC4, 0x72, 0xB7, 0xCD, 0xEC, 0xE1,
+	0x1F, 0x77, 0xAA, 0xBC, 0x5B, 0xFB, 0x8F, 0x0F, 0x3F, 0xCA, 0x38, 0x93, 0x2F, 0xC1, 0x73, 0xE3,
+	0xEB, 0x73, 0xC2, 0xE9, 0x5B, 0x9A, 0x4F, 0xF3, 0x45, 0x3F, 0x8A, 0xBF, 0xB1, 0x17, 0xEC, 0xEF,
+	0xF1, 0xBF, 0xC6, 0x32, 0xF8, 0xF3, 0xE2, 0x37, 0x84, 0xEE, 0x2F, 0x35, 0x59, 0xA2, 0x8E, 0x19,
+	0xAE, 0x23, 0xD5, 0x27, 0x8F, 0x28, 0xAB, 0x85, 0x5C, 0x2B, 0x8C, 0x57, 0x36, 0xBF, 0xF0, 0x4C,
+	0x7F, 0xD8, 0xFF, 0x00, 0x1F, 0xF2, 0x20, 0x5F, 0x2F, 0xB7, 0xF6, 0xF5, 0xC7, 0x1F, 0xF8, 0xFD,
+	0x78, 0xA7, 0xED, 0xDF, 0xFB, 0x69, 0xFE, 0xD1, 0x5F, 0x04, 0x7F, 0x68, 0x6B, 0xEF, 0x01, 0xFC,
+	0x37, 0xF1, 0xB4, 0x5A, 0x7E, 0x97, 0x0E, 0x9B, 0x6D, 0x3C, 0x36, 0xF2, 0x69, 0x16, 0xD3, 0x1F,
+	0x31, 0x90, 0x16, 0x3B, 0xA5, 0x43, 0x8F, 0xCE, 0xBC, 0x70, 0xFF, 0x00, 0xC1, 0x4B, 0xFF, 0x00,
+	0x6C, 0xB3, 0xFF, 0x00, 0x35, 0x52, 0xDF, 0xFF, 0x00, 0x04, 0x36, 0x27, 0xF9, 0x26, 0x3F, 0x2A,
+	0xFE, 0x84, 0x3E, 0x46, 0x34, 0xEB, 0x72, 0xA6, 0x8F, 0xB3, 0xBF, 0xE1, 0xD8, 0xFF, 0x00, 0xB1,
+	0xF7, 0xFD, 0x08, 0x37, 0xDF, 0xF8, 0x3E, 0xB8, 0xFF, 0x00, 0xE2, 0xE8, 0xFF, 0x00, 0x87, 0x63,
+	0xFE, 0xC7, 0xDF, 0xF4, 0x20, 0xDF, 0x7F, 0xE0, 0xFA, 0xE3, 0xFF, 0x00, 0x8B, 0xAF, 0x8C, 0x3F,
+	0xE1, 0xE5, 0xDF, 0xB6, 0x5F, 0xFD, 0x15, 0x4B, 0x7F, 0xFC, 0x27, 0xEC, 0xBF, 0xF8, 0x8A, 0x5F,
+	0xF8, 0x79, 0x7F, 0xED, 0x97, 0xFF, 0x00, 0x45, 0x52, 0xDF, 0xFF, 0x00, 0x09, 0xFB, 0x2F, 0xFE,
+	0x22, 0x82, 0xFD, 0x9D, 0x7E, 0xE7, 0xD9, 0xC7, 0xFE, 0x09, 0x8F, 0xFB, 0x1F, 0xFF, 0x00, 0xD0,
+	0x85, 0x7D, 0xFF, 0x00, 0x83, 0xEB, 0x8F, 0xFE, 0x2E, 0xBD, 0xCB, 0xC2, 0x5E, 0x18, 0xD1, 0xFC,
+	0x13, 0xE1, 0x5D, 0x33, 0xC1, 0x9E, 0x1E, 0xB7, 0x68, 0x74, 0xFD, 0x23, 0x4F, 0x86, 0xCA, 0xC6,
+	0x26, 0x90, 0xB1, 0x48, 0x62, 0x8C, 0x22, 0x29, 0x63, 0xC9, 0x21, 0x54, 0x72, 0x79, 0x35, 0xF9,
+	0x7F, 0xFF, 0x00, 0x0F, 0x31, 0xFD, 0xB2, 0xFF, 0x00, 0xE8, 0xA7, 0x5B, 0xFF, 0x00, 0xE0, 0x86,
+	0xCB, 0xFF, 0x00, 0x88, 0xAF, 0xD2, 0x6F, 0x81, 0x5E, 0x26, 0xD6, 0x7C, 0x6B, 0xF0, 0x47, 0xC1,
+	0xBE, 0x32, 0xF1, 0x1D, 0xD0, 0x9B, 0x50, 0xD5, 0xBC, 0x2B, 0xA7, 0xDE, 0xDF, 0xCC, 0xB1, 0xAA,
+	0x09, 0x26, 0x96, 0xDA, 0x37, 0x76, 0xDA, 0xBC, 0x0C, 0xB3, 0x13, 0x81, 0xC0, 0xED, 0x41, 0x95,
+	0x48, 0xD4, 0x8A, 0x5C, 0xC7, 0x1B, 0xE3, 0x4F, 0xD8, 0x7B, 0xF6, 0x60, 0xF8, 0x85, 0xE2, 0xDB,
+	0xCF, 0x1D, 0x78, 0xCF, 0xE1, 0xAB, 0x5E, 0xEA, 0x7A, 0x95, 0xC9, 0x9A, 0xFA, 0xF1, 0xB5, 0xBB,
+	0xE4, 0xDC, 0x41, 0x3F, 0xC2, 0xB3, 0x85, 0x5E, 0x7B, 0x00, 0x07, 0xA0, 0xAC, 0xD5, 0xFF, 0x00,
+	0x82, 0x75, 0xFE, 0xC7, 0x61, 0x40, 0x6F, 0x83, 0xDC, 0xE3, 0x9F, 0xF8, 0x9F, 0x6A, 0x1F, 0xFC,
+	0x93, 0x5F, 0x3C, 0xFE, 0xD2, 0x9F, 0xB7, 0xEF, 0xED, 0x17, 0xF0, 0xC7, 0xE3, 0xA7, 0x8A, 0x3E,
+	0x1F, 0xF8, 0x4E, 0xFF, 0x00, 0x4B, 0x5B, 0x1D, 0x37, 0x54, 0x36, 0xF6, 0x2B, 0x3E, 0x96, 0x8C,
+	0x40, 0x2B, 0x9E, 0x4F, 0x73, 0x8E, 0xF5, 0xC5, 0x7F, 0xC3, 0xCF, 0xFF, 0x00, 0x6A, 0x77, 0xF9,
+	0x86, 0xAF, 0xA1, 0xF3, 0xCF, 0xFC, 0x81, 0xD2, 0x83, 0x13, 0xEB, 0xDF, 0xF8, 0x77, 0x67, 0xEC,
+	0x75, 0xFF, 0x00, 0x44, 0x7B, 0xFF, 0x00, 0x2B, 0xDA, 0x87, 0xFF, 0x00, 0x24, 0x51, 0xFF, 0x00,
+	0x0E, 0xEC, 0xFD, 0x8E, 0xBF, 0xE8, 0x8F, 0x7F, 0xE5, 0x7B, 0x50, 0xFF, 0x00, 0xE4, 0x8A, 0xF9,
+	0x0B, 0xFE, 0x1E, 0x7B, 0xFB, 0x54, 0x7F, 0xD0, 0x63, 0x43, 0xFF, 0x00, 0xC1, 0x3C, 0x74, 0x7F,
+	0xC3, 0xCF, 0x7F, 0x6A, 0x8F, 0xFA, 0x0C, 0x68, 0x7F, 0xF8, 0x27, 0x8E, 0x80, 0x3E, 0xBD, 0xFF,
+	0x00, 0x87, 0x76, 0x7E, 0xC7, 0x5F, 0xF4, 0x47, 0xBF, 0xF2, 0xBD, 0xA8, 0x7F, 0xF2, 0x45, 0x76,
+	0x3F, 0x06, 0xBE, 0x07, 0x7C, 0x2F, 0xF8, 0x0C, 0xDA, 0xB6, 0x81, 0xF0, 0xA7, 0xC3, 0x1F, 0xD9,
+	0x96, 0xB7, 0xBE, 0x45, 0xC4, 0xF6, 0xED, 0x7D, 0x3C, 0xFB, 0xA4, 0xCC, 0x88, 0x0E, 0x66, 0x91,
+	0xC8, 0xE1, 0x47, 0x4C, 0x0A, 0xF8, 0x47, 0xFE, 0x1E, 0x7B, 0xFB, 0x54, 0x7F, 0xD0, 0x63, 0x43,
+	0xFF, 0x00, 0xC1, 0x3C, 0x75, 0xF5, 0x17, 0xFC, 0x13, 0xF3, 0xF6, 0x81, 0xF8, 0x8B, 0xFB, 0x44,
+	0x78, 0x57, 0xC4, 0xDE, 0x23, 0xF8, 0x8F, 0x77, 0x66, 0xF7, 0x56, 0x17, 0xD6, 0xF6, 0xD0, 0xBD,
+	0x9D, 0xB8, 0x8D, 0x42, 0x6C, 0x67, 0xE4, 0x74, 0xFE, 0x2A, 0x00, 0xED, 0x7E, 0x23, 0xFE, 0xCA,
+	0x1F, 0x00, 0x7E, 0x39, 0x78, 0xB6, 0x6F, 0x16, 0xFC, 0x4F, 0xF0, 0x27, 0xF6, 0xB6, 0xA1, 0x0A,
+	0xAD, 0xB4, 0x77, 0x5F, 0xDA, 0xD7, 0x91, 0x6D, 0x8D, 0x06, 0x76, 0x62, 0x39, 0x94, 0x70, 0x64,
+	0x6E, 0xD5, 0x8B, 0xFF, 0x00, 0x0E, 0xEC, 0xFD, 0x8E, 0xBF, 0xE8, 0x8F, 0x7F, 0xE5, 0x7B, 0x50,
+	0xFF, 0x00, 0xE4, 0x8A, 0xF2, 0x4F, 0xDB, 0x8B, 0xF6, 0xC9, 0xF8, 0xD9, 0xFB, 0x3E, 0x7C, 0x6C,
+	0x5F, 0x04, 0x7C, 0x3A, 0xBD, 0xD3, 0x23, 0xB1, 0x9B, 0x46, 0x86, 0xF2, 0x4F, 0xB6, 0x69, 0xE2,
+	0x46, 0x12, 0x3B, 0xC8, 0xBC, 0x13, 0xEC, 0x8B, 0x5E, 0x3B, 0xFF, 0x00, 0x0F, 0x3D, 0xFD, 0xAA,
+	0x3F, 0xE8, 0x31, 0xA1, 0xFF, 0x00, 0xE0, 0x9E, 0x3A, 0x00, 0xFA, 0xF7, 0xFE, 0x1D, 0xD9, 0xFB,
+	0x1D, 0x7F, 0xD1, 0x1E, 0xFF, 0x00, 0xCA, 0xF6, 0xA1, 0xFF, 0x00, 0xC9, 0x14, 0x7F, 0xC3, 0xBB,
+	0x3F, 0x63, 0xAF, 0xFA, 0x23, 0xDF, 0xF9, 0x5E, 0xD4, 0x3F, 0xF9, 0x22, 0xBE, 0x42, 0xFF, 0x00,
+	0x87, 0x9E, 0xFE, 0xD5, 0x1F, 0xF4, 0x18, 0xD0, 0xFF, 0x00, 0xF0, 0x4F, 0x1D, 0x1F, 0xF0, 0xF3,
+	0xDF, 0xDA, 0xA3, 0xFE, 0x83, 0x1A, 0x1F, 0xFE, 0x09, 0xE3, 0xA0, 0x0F, 0xAE, 0xDF, 0xFE, 0x09,
+	0xDB, 0xFB, 0x1D, 0x2A, 0xE7, 0xFE, 0x14, 0xEE, 0x7B, 0x7F, 0xC8, 0x7F, 0x50, 0xFF, 0x00, 0xE4,
+	0x9A, 0xED, 0xFE, 0x0C, 0xFE, 0xCF, 0xDF, 0x09, 0xBE, 0x00, 0x59, 0x6A, 0x56, 0x5F, 0x09, 0xFC,
+	0x21, 0xFD, 0x95, 0x1E, 0xA4, 0xF1, 0x35, 0xDC, 0x7F, 0xDA, 0x17, 0x17, 0x1E, 0x6B, 0x46, 0x0A,
+	0xA7, 0xCD, 0x33, 0x39, 0x1C, 0x1E, 0xC7, 0x1C, 0xD7, 0xC1, 0xBF, 0xF0, 0xF3, 0xEF, 0xDA, 0xA4,
+	0x74, 0xD5, 0xF4, 0x43, 0xF4, 0xD1, 0x50, 0xFE, 0x82, 0xBE, 0x9B, 0xFF, 0x00, 0x82, 0x7C, 0x7E,
+	0xD2, 0x7F, 0x12, 0xFF, 0x00, 0x68, 0xED, 0x1B, 0xC5, 0x77, 0x9F, 0x12, 0x6F, 0xAC, 0x24, 0x9B,
+	0x49, 0x9E, 0xCD, 0x6D, 0x5A, 0xC6, 0xD4, 0x44, 0xAA, 0xB2, 0x2C, 0xAC, 0x72, 0x0F, 0x53, 0xF2,
+	0x8A, 0x00, 0xEF, 0x3E, 0x23, 0xFE, 0xCA, 0x1F, 0x00, 0x7E, 0x39, 0x78, 0xB6, 0x6F, 0x16, 0xFC,
+	0x4F, 0xF0, 0x27, 0xF6, 0xB6, 0xA1, 0x0A, 0xAD, 0xB4, 0x77, 0x5F, 0xDA, 0xD7, 0x91, 0x6D, 0x8D,
+	0x06, 0x76, 0x62, 0x39, 0x94, 0x70, 0x64, 0x6E, 0xD5, 0x8B, 0xFF, 0x00, 0x0E, 0xEC, 0xFD, 0x8E,
+	0xBF, 0xE8, 0x8F, 0x7F, 0xE5, 0x7B, 0x50, 0xFF, 0x00, 0xE4, 0x8A, 0xF2, 0x4F, 0xDB, 0x8B, 0xF6,
+	0xC9, 0xF8, 0xD9, 0xFB, 0x3E, 0x7C, 0x6C, 0x5F, 0x04, 0x7C, 0x3A, 0xBD, 0xD3, 0x23, 0xB1, 0x9B,
+	0x46, 0x86, 0xF2, 0x4F, 0xB6, 0x69, 0xE2, 0x46, 0x12, 0x3B, 0xC8, 0xBC, 0x13, 0xEC, 0x8B, 0x5E,
+	0x3B, 0xFF, 0x00, 0x0F, 0x3D, 0xFD, 0xAA, 0x3F, 0xE8, 0x31, 0xA1, 0xFF, 0x00, 0xE0, 0x9E, 0x3A,
+	0x00, 0xFA, 0xF7, 0xFE, 0x1D, 0xD9, 0xFB, 0x1D, 0x7F, 0xD1, 0x1E, 0xFF, 0x00, 0xCA, 0xF6, 0xA1,
+	0xFF, 0x00, 0xC9, 0x14, 0x7F, 0xC3, 0xBB, 0x3F, 0x63, 0xAF, 0xFA, 0x23, 0xDF, 0xF9, 0x5E, 0xD4,
+	0x3F, 0xF9, 0x22, 0xBE, 0x42, 0xFF, 0x00, 0x87, 0x9E, 0xFE, 0xD5, 0x1F, 0xF4, 0x18, 0xD0, 0xFF,
+	0x00, 0xF0, 0x4F, 0x1D, 0x1F, 0xF0, 0xF3, 0xDF, 0xDA, 0xA3, 0xFE, 0x83, 0x1A, 0x1F, 0xFE, 0x09,
+	0xE3, 0xA0, 0x0F, 0xAE, 0xDF, 0xFE, 0x09, 0xDB, 0xFB, 0x1D, 0x2A, 0xE7, 0xFE, 0x14, 0xEE, 0x7B,
+	0x7F, 0xC8, 0x7F, 0x50, 0xFF, 0x00, 0xE4, 0x9A, 0xEC, 0xFE, 0x0F, 0xFE, 0xCF, 0xBF, 0x09, 0xFE,
+	0x00, 0xDA, 0xDF, 0x58, 0xFC, 0x27, 0xF0, 0x97, 0xF6, 0x4C, 0x3A, 0x84, 0x91, 0x3D, 0xEA, 0x9D,
+	0x42, 0x7B, 0x8F, 0x35, 0xA3, 0x52, 0x89, 0xF3, 0x4E, 0xCC, 0x47, 0x0C, 0x7A, 0x1A, 0xF8, 0x47,
+	0xFE, 0x1E, 0x7D, 0xFB, 0x54, 0x8E, 0x9A, 0xBE, 0x88, 0x7E, 0x9A, 0x2A, 0x1F, 0xD0, 0x57, 0xD3,
+	0x3F, 0xF0, 0x4F, 0xDF, 0xDA, 0x53, 0xE2, 0x5F, 0xED, 0x1B, 0xA4, 0xF8, 0x9E, 0xF3, 0xE2, 0x55,
+	0xE5, 0x8C, 0xD3, 0x69, 0x77, 0x56, 0x71, 0xDA, 0xFF, 0x00, 0x67, 0xD9, 0xF9, 0x40, 0x2C, 0xAB,
+	0x2B, 0x1C, 0xFF, 0x00, 0xDF, 0x34, 0x01, 0xF4, 0x7D, 0x98, 0xC4, 0x58, 0x03, 0xF9, 0xF1, 0xC0,
+	0xA9, 0x6A, 0x2B, 0x40, 0x44, 0x59, 0x3D, 0xDB, 0x3D, 0x4D, 0x4B, 0x40, 0x96, 0xC1, 0x41, 0x3C,
+	0x51, 0x41, 0xE9, 0x40, 0xCF, 0x84, 0xFF, 0x00, 0xE0, 0xAF, 0x8A, 0x17, 0xC4, 0x5E, 0x06, 0x55,
+	0x1C, 0x0B, 0x1B, 0xE0, 0x3F, 0xEF, 0xB8, 0xEB, 0xE3, 0x7A, 0xFB, 0x27, 0xFE, 0x0A, 0xFB, 0xFF,
+	0x00, 0x23, 0x27, 0x81, 0xFF, 0x00, 0xEB, 0xCA, 0xFB, 0xFF, 0x00, 0x46, 0x47, 0x5F, 0x1B, 0x50,
+	0x01, 0x45, 0x14, 0x50, 0x00, 0x3A, 0xD7, 0xD5, 0xFF, 0x00, 0xF0, 0x49, 0x1F, 0xF9, 0x2D, 0x1E,
+	0x26, 0xCF, 0xFD, 0x0A, 0x8B, 0xFF, 0x00, 0xA5, 0x31, 0x57, 0xCA, 0x03, 0xAD, 0x7D, 0x5F, 0xFF,
+	0x00, 0x04, 0x91, 0xFF, 0x00, 0x92, 0xD3, 0xE2, 0x6F, 0xFB, 0x15, 0x17, 0xFF, 0x00, 0x4A, 0x62,
+	0xA0, 0x0F, 0x59, 0xFF, 0x00, 0x82, 0xB2, 0xF1, 0xFB, 0x3B, 0xE8, 0x60, 0x0F, 0xF9, 0x9C, 0xA1,
+	0xFF, 0x00, 0xD2, 0x5B, 0x9A, 0xFC, 0xF7, 0xAF, 0xD0, 0x8F, 0xF8, 0x2B, 0x2F, 0xFC, 0x9B, 0xBE,
+	0x87, 0xFF, 0x00, 0x63, 0x94, 0x3F, 0xFA, 0x4B, 0x73, 0x5F, 0x9E, 0xF5, 0x31, 0xEB, 0xFD, 0x74,
+	0x2A, 0x5D, 0x02, 0x8A, 0x28, 0xAA, 0x24, 0x2B, 0xDE, 0xBF, 0xE0, 0x9B, 0x1F, 0xF2, 0x77, 0x3A,
+	0x0F, 0xFD, 0x83, 0xF5, 0x0F, 0xFD, 0x27, 0x7A, 0xF0, 0x5A, 0xF7, 0xAF, 0xF8, 0x26, 0xC7, 0xFC,
+	0x9D, 0xCE, 0x83, 0xFF, 0x00, 0x60, 0xFD, 0x43, 0xFF, 0x00, 0x49, 0xDE, 0x80, 0x3E, 0xC4, 0xFF,
+	0x00, 0x82, 0x89, 0xE0, 0x7E, 0xC7, 0x7E, 0x2D, 0xC0, 0xFF, 0x00, 0x96, 0x96, 0x3F, 0xFA, 0x5B,
+	0x05, 0x7E, 0x60, 0xD7, 0xE9, 0xF7, 0xFC, 0x14, 0x53, 0xFE, 0x4C, 0xEF, 0xC5, 0xBF, 0xF5, 0xD2,
+	0xC7, 0xFF, 0x00, 0x4B, 0x60, 0xAF, 0xCC, 0x1A, 0x98, 0xFF, 0x00, 0x5F, 0x71, 0x52, 0xD9, 0x05,
+	0x14, 0x51, 0x54, 0x48, 0x57, 0xA2, 0x7E, 0xC9, 0x5F, 0xF2, 0x73, 0x9E, 0x01, 0xFF, 0x00, 0xB1,
+	0xAA, 0xD3, 0xFF, 0x00, 0x42, 0x15, 0xE7, 0x75, 0xE8, 0x9F, 0xB2, 0x57, 0xFC, 0x9C, 0xE7, 0x80,
+	0x7F, 0xEC, 0x6A, 0xB4, 0xFF, 0x00, 0xD0, 0x85, 0x00, 0x7E, 0x95, 0xFE, 0xD4, 0x78, 0xFF, 0x00,
+	0x86, 0x68, 0xF8, 0x88, 0x40, 0xFF, 0x00, 0x99, 0x2B, 0x53, 0xFF, 0x00, 0xD2, 0x59, 0x2B, 0xF1,
+	0xB2, 0xBF, 0x65, 0x3F, 0x6A, 0x4F, 0xF9, 0x36, 0x8F, 0x88, 0x9F, 0xF6, 0x24, 0xEA, 0x7F, 0xFA,
+	0x4B, 0x25, 0x7E, 0x35, 0xD7, 0xE7, 0xBC, 0x63, 0x67, 0x88, 0xA2, 0xFF, 0x00, 0xBA, 0xFF, 0x00,
+	0x33, 0xFA, 0x4B, 0xC0, 0xBD, 0x72, 0xCC, 0x67, 0xF8, 0xE1, 0xF9, 0x30, 0xA2, 0x8A, 0x2B, 0xE3,
+	0x4F, 0xDD, 0xEE, 0x15, 0xF4, 0x37, 0xFC, 0x12, 0xFB, 0x3F, 0xF0, 0xD7, 0x3A, 0x4E, 0x0F, 0xFC,
+	0xC2, 0xAF, 0xBF, 0xF4, 0x51, 0xAF, 0x9E, 0x6B, 0xE8, 0x7F, 0xF8, 0x25, 0xE7, 0xFC, 0x9D, 0xD6,
+	0x93, 0xFF, 0x00, 0x60, 0xAB, 0xEF, 0xFD, 0x14, 0x6B, 0xD2, 0xCA, 0x3F, 0xE4, 0x65, 0x49, 0xBF,
+	0xE6, 0x47, 0xC9, 0x71, 0xD7, 0xFC, 0x91, 0xD8, 0xD5, 0xFD, 0xC6, 0x7D, 0xCB, 0xFB, 0x72, 0x60,
+	0xFC, 0x15, 0x8C, 0x8F, 0xFA, 0x0C, 0x41, 0xFC, 0x9E, 0xBE, 0x3C, 0x23, 0x24, 0xD7, 0xD8, 0x9F,
+	0xB7, 0x2F, 0xFC, 0x91, 0x58, 0xFF, 0x00, 0xEC, 0x31, 0x07, 0xF2, 0x7A, 0xF8, 0xE8, 0xF5, 0xAF,
+	0xE5, 0x9F, 0xA4, 0xDE, 0x9E, 0x21, 0xDF, 0xFE, 0x9D, 0x43, 0xF5, 0x3F, 0x0F, 0xF0, 0xEB, 0xFE,
+	0x44, 0x72, 0x7D, 0x79, 0x9F, 0xE8, 0x14, 0x51, 0x45, 0x7F, 0x39, 0x9F, 0xA0, 0x05, 0x7D, 0x21,
+	0xFF, 0x00, 0x04, 0xF7, 0x00, 0xDD, 0x78, 0xA7, 0xFD, 0xDB, 0x2F, 0xFD, 0xB8, 0xAF, 0x9B, 0xEB,
+	0xE9, 0x0F, 0xF8, 0x27, 0xA7, 0xFC, 0x7D, 0xF8, 0xA7, 0xFD, 0xDB, 0x3F, 0xE7, 0x71, 0x5F, 0xB5,
+	0x78, 0x03, 0xAF, 0x8A, 0x18, 0x3F, 0x49, 0x7F, 0xE9, 0x27, 0xC8, 0x71, 0xCF, 0xFC, 0x93, 0xB5,
+	0x1F, 0x9A, 0xFC, 0xD1, 0xC7, 0xFF, 0x00, 0xC1, 0x5F, 0xFF, 0x00, 0xE4, 0x5E, 0xF0, 0x27, 0xFD,
+	0x7E, 0x5F, 0x7F, 0xE8, 0xB8, 0xEB, 0xE1, 0xBA, 0xFB, 0x93, 0xFE, 0x0A, 0xFF, 0x00, 0xFF, 0x00,
+	0x22, 0xFF, 0x00, 0x81, 0x3F, 0xEB, 0xF2, 0xFB, 0xFF, 0x00, 0x45, 0xC7, 0x5F, 0x0D, 0xD7, 0xFA,
+	0x54, 0x8F, 0xC0, 0x82, 0x8A, 0x28, 0xA0, 0x02, 0xBF, 0x4D, 0x3F, 0xE0, 0x9A, 0xBF, 0xF2, 0x68,
+	0xFA, 0x1F, 0xFD, 0x7F, 0x5F, 0xFF, 0x00, 0xE9, 0x4B, 0x57, 0xE6, 0x5D, 0x7E, 0x9A, 0x7F, 0xC1,
+	0x35, 0x7F, 0xE4, 0xD1, 0xF4, 0x3F, 0xFA, 0xFE, 0xBF, 0xFF, 0x00, 0xD2, 0x96, 0xA0, 0x0F, 0x97,
+	0x7F, 0xE0, 0xAA, 0xDF, 0xF2, 0x72, 0xD1, 0x7F, 0xD8, 0xAB, 0x6B, 0xFF, 0x00, 0xA3, 0x26, 0xAF,
+	0x9B, 0x4F, 0x5A, 0xFA, 0x4B, 0xFE, 0x0A, 0xAF, 0xFF, 0x00, 0x27, 0x2D, 0x17, 0xFD, 0x8A, 0xB6,
+	0xBF, 0xFA, 0x32, 0x6A, 0xF9, 0xB4, 0xF5, 0xA3, 0xAD, 0xC0, 0xE9, 0xBE, 0x17, 0x7C, 0x59, 0xF1,
+	0x77, 0xC2, 0x3F, 0x10, 0xFF, 0x00, 0x6D, 0xF8, 0x5E, 0xE0, 0x32, 0xB9, 0x51, 0x7B, 0x67, 0x22,
+	0xEE, 0x82, 0xEE, 0x3F, 0xEE, 0xC8, 0x9D, 0x88, 0xEC, 0xD5, 0xF6, 0x37, 0xC2, 0x6F, 0x8C, 0x7E,
+	0x12, 0xF8, 0xC7, 0xA1, 0xFF, 0x00, 0x6A, 0x78, 0x72, 0xF4, 0xA5, 0xCC, 0x3C, 0x5F, 0x69, 0xB2,
+	0x49, 0xFB, 0xDB, 0x73, 0xEB, 0xFE, 0xD2, 0xFB, 0xF7, 0xAF, 0x84, 0xEB, 0x43, 0xC2, 0xFE, 0x2A,
+	0xF1, 0x0F, 0x82, 0xB5, 0xC8, 0x3C, 0x4B, 0xE1, 0x7D, 0x55, 0xEC, 0xAF, 0x61, 0x6C, 0xC3, 0x71,
+	0x13, 0x6D, 0xDA, 0x3B, 0xAB, 0x0E, 0xE1, 0xAB, 0xF0, 0x1F, 0x18, 0xBC, 0x09, 0xC8, 0xBC, 0x4E,
+	0xC2, 0xBC, 0x4D, 0x0B, 0x51, 0xC7, 0xC5, 0x3E, 0x59, 0xA5, 0xA4, 0xAC, 0xB4, 0x55, 0x2D, 0xBF,
+	0x93, 0xDD, 0x79, 0xEC, 0x7B, 0x99, 0x4E, 0x77, 0x5B, 0x2D, 0x97, 0x2C, 0xB5, 0x83, 0xFE, 0xB4,
+	0x3F, 0x42, 0x06, 0x00, 0xE4, 0x7E, 0x98, 0xFD, 0x29, 0x72, 0xBF, 0xDD, 0xAF, 0x24, 0xF8, 0x11,
+	0xFB, 0x52, 0x78, 0x6B, 0xE2, 0x74, 0x50, 0xF8, 0x7B, 0xC4, 0x62, 0x1D, 0x2F, 0x5B, 0xFF, 0x00,
+	0x9E, 0x6C, 0xFB, 0x61, 0xBC, 0x3D, 0xF6, 0x9F, 0xEF, 0x67, 0xF8, 0x7B, 0x57, 0xAD, 0x74, 0x1D,
+	0x0F, 0xFC, 0x08, 0x62, 0xBF, 0xCC, 0x2E, 0x2E, 0xE0, 0xCE, 0x21, 0xE0, 0x7C, 0xDE, 0x79, 0x76,
+	0x6F, 0x45, 0xD3, 0xA9, 0x1D, 0xAE, 0x9D, 0xA4, 0xBB, 0xC5, 0xF5, 0x4F, 0xA3, 0x47, 0xE8, 0xD8,
+	0x4C, 0x5D, 0x0C, 0x6D, 0x15, 0x52, 0x93, 0xBA, 0xF5, 0x17, 0x2B, 0xFD, 0xDA, 0x32, 0xBF, 0xDD,
+	0xA4, 0xA2, 0xBE, 0x53, 0xDE, 0x3A, 0x85, 0xCA, 0xFF, 0x00, 0x76, 0x8C, 0xAF, 0xF7, 0x69, 0x28,
+	0xA5, 0x76, 0x02, 0x6D, 0x1D, 0x71, 0x4B, 0x45, 0x14, 0xEE, 0x1A, 0x85, 0x14, 0x51, 0x4A, 0xFE,
+	0x40, 0x14, 0x51, 0x45, 0x17, 0xF2, 0x00, 0xA2, 0x8A, 0x28, 0xBF, 0x90, 0x05, 0x14, 0x51, 0x45,
+	0xFC, 0x80, 0x28, 0xA2, 0x8A, 0x2F, 0xE4, 0x00, 0x3E, 0xF6, 0x0D, 0x7E, 0x1D, 0x7F, 0xC1, 0x4F,
+	0x30, 0xDF, 0xB7, 0x7F, 0xC4, 0x03, 0x9E, 0x9A, 0xA5, 0xB7, 0xFE, 0x92, 0x43, 0x5F, 0xB8, 0xB5,
+	0xF8, 0x71, 0xFF, 0x00, 0x05, 0x3A, 0x3F, 0xF1, 0x9D, 0xBE, 0x3E, 0xFF, 0x00, 0xB0, 0x9D, 0xB7,
+	0xFE, 0x92, 0x43, 0x5F, 0xD2, 0xDF, 0x46, 0x3F, 0xF9, 0x2B, 0x31, 0x7F, 0xF5, 0xEB, 0xFF, 0x00,
+	0x6E, 0x47, 0xF4, 0x07, 0xD1, 0xD7, 0xFE, 0x4B, 0x1A, 0xD7, 0xFF, 0x00, 0x9F, 0x4F, 0xF3, 0x47,
+	0x81, 0x9C, 0x67, 0x91, 0x47, 0x1E, 0x94, 0x87, 0xAD, 0x15, 0xFD, 0xBA, 0x7F, 0x6C, 0x0B, 0xC7,
+	0xA5, 0x1C, 0x7A, 0x52, 0x51, 0x40, 0x1D, 0xD7, 0xEC, 0xD1, 0xCF, 0xED, 0x19, 0xF0, 0xF4, 0x13,
+	0xFF, 0x00, 0x33, 0x96, 0x99, 0xFF, 0x00, 0xA5, 0x91, 0x57, 0xF4, 0x11, 0x18, 0xFD, 0xD2, 0x81,
+	0xFD, 0xDE, 0xB5, 0xFC, 0xFB, 0xFE, 0xCC, 0xE7, 0xFE, 0x32, 0x33, 0xE1, 0xEF, 0xFD, 0x8E, 0x9A,
+	0x5F, 0xFE, 0x96, 0x45, 0x5F, 0xD0, 0x44, 0x5F, 0xEA, 0xD7, 0xE9, 0x5F, 0xC6, 0xFF, 0x00, 0x4A,
+	0x16, 0xFF, 0x00, 0xB5, 0x32, 0xED, 0x7E, 0xC4, 0xFF, 0x00, 0xF4, 0xA4, 0x7F, 0x1F, 0xFD, 0x25,
+	0xAD, 0xFD, 0xB1, 0x97, 0xFF, 0x00, 0xD7, 0xB9, 0x7F, 0xE9, 0x48, 0x77, 0x23, 0xAD, 0x14, 0x51,
+	0x5F, 0xCA, 0x97, 0xF2, 0x3F, 0x99, 0xC2, 0x8A, 0x28, 0xA2, 0xFE, 0x40, 0x14, 0x51, 0x45, 0x17,
+	0xF2, 0x00, 0xA2, 0x8A, 0x28, 0xBF, 0x90, 0x05, 0x14, 0x51, 0x45, 0xFC, 0x80, 0x28, 0xA2, 0x8A,
+	0x7C, 0xCC, 0x00, 0x6D, 0x03, 0x1B, 0x69, 0x72, 0xBF, 0xDD, 0xA4, 0xA2, 0x95, 0xD8, 0x0B, 0x95,
+	0xFE, 0xED, 0x19, 0x5F, 0xEE, 0xD2, 0x50, 0x40, 0xE8, 0x0D, 0x30, 0xD4, 0x5C, 0xAF, 0xF7, 0x68,
+	0xCA, 0xFF, 0x00, 0x76, 0x92, 0xB8, 0x0F, 0x8D, 0x7F, 0xB4, 0x17, 0x83, 0xBE, 0x0E, 0x58, 0x3D,
+	0xB4, 0xB2, 0x7D, 0xAF, 0x59, 0x9A, 0x3C, 0xDA, 0xE9, 0x70, 0xC9, 0xB4, 0x8F, 0x49, 0x1F, 0xFB,
+	0x83, 0xFF, 0x00, 0x42, 0xAF, 0xA0, 0xE1, 0xCE, 0x18, 0xCF, 0x38, 0xB3, 0x36, 0xA7, 0x97, 0x65,
+	0x74, 0x9D, 0x4A, 0xB3, 0x6A, 0xC9, 0x27, 0xA7, 0x9B, 0x7D, 0x12, 0xEA, 0xF6, 0x47, 0x3E, 0x23,
+	0x13, 0x4B, 0x0B, 0x4D, 0xCE, 0xAB, 0xB2, 0x5E, 0x67, 0x47, 0xE3, 0xFF, 0x00, 0x88, 0x5E, 0x13,
+	0xF8, 0x69, 0xE1, 0xC9, 0xBC, 0x4D, 0xE3, 0x0D, 0x55, 0x6D, 0xED, 0xD4, 0x11, 0x1C, 0x7B, 0x72,
+	0xF3, 0xBF, 0x64, 0x03, 0xF8, 0xFF, 0x00, 0xF6, 0x5A, 0xF8, 0xF7, 0xE3, 0x77, 0xC7, 0x9F, 0x15,
+	0x7C, 0x69, 0xD5, 0x7C, 0xBB, 0x97, 0x7B, 0x5D, 0x2E, 0x29, 0x09, 0xB2, 0xD2, 0xD0, 0x6F, 0xC7,
+	0x3C, 0xB3, 0xFF, 0x00, 0xCF, 0x53, 0xEB, 0xFD, 0xD3, 0x58, 0x9F, 0x11, 0x3E, 0x26, 0x78, 0xBF,
+	0xE2, 0x8E, 0xBC, 0xDE, 0x25, 0xF1, 0x65, 0xF7, 0x99, 0x2F, 0x22, 0x18, 0x55, 0x70, 0x91, 0x27,
+	0x65, 0x03, 0xD0, 0x0E, 0x05, 0x60, 0x0A, 0xFF, 0x00, 0x4C, 0xBC, 0x14, 0xFA, 0x3E, 0xE5, 0x1E,
+	0x1D, 0xD1, 0x8E, 0x67, 0x99, 0xF2, 0xD7, 0xC7, 0x35, 0xBD, 0xAF, 0x1A, 0x7E, 0x50, 0xBE, 0xF2,
+	0xEF, 0x2F, 0xB8, 0xFC, 0xF3, 0x38, 0xCF, 0x2B, 0x63, 0xBF, 0x77, 0x4F, 0x48, 0x7E, 0x2C, 0x0E,
+	0xDC, 0xFC, 0x98, 0xDB, 0xFC, 0x38, 0x6D, 0xDF, 0xAF, 0x7F, 0xAD, 0x7D, 0x25, 0xFF, 0x00, 0x04,
+	0xAD, 0xFF, 0x00, 0x93, 0x9A, 0x9F, 0xFE, 0xC5, 0x6B, 0xEF, 0xFD, 0x1B, 0x6F, 0x5F, 0x36, 0xD7,
+	0xD2, 0x5F, 0xF0, 0x4A, 0xDF, 0xF9, 0x39, 0xA9, 0xFF, 0x00, 0xEC, 0x56, 0xBE, 0xFF, 0x00, 0xD1,
+	0xB6, 0xF5, 0xFD, 0x28, 0x7C, 0xF1, 0xF5, 0x1F, 0xFC, 0x14, 0xAB, 0xFE, 0x4D, 0x2B, 0x5E, 0xFF,
+	0x00, 0xAF, 0xDB, 0x1F, 0xFD, 0x28, 0x5A, 0xFC, 0xCA, 0xAF, 0xD3, 0x5F, 0xF8, 0x29, 0x57, 0xFC,
+	0x9A, 0x56, 0xBD, 0xFF, 0x00, 0x5F, 0xB6, 0x3F, 0xFA, 0x50, 0xB5, 0xF9, 0x95, 0x40, 0x05, 0x14,
+	0x51, 0x40, 0x05, 0x7D, 0xC7, 0xFF, 0x00, 0x04, 0x83, 0xFF, 0x00, 0x91, 0x6F, 0xC7, 0x5F, 0xF5,
+	0xFF, 0x00, 0x63, 0xFF, 0x00, 0xA2, 0xAE, 0x2B, 0xE1, 0xCA, 0xFB, 0x8F, 0xFE, 0x09, 0x07, 0xFF,
+	0x00, 0x22, 0xDF, 0x8E, 0xBF, 0xEB, 0xFE, 0xC7, 0xFF, 0x00, 0x45, 0x5C, 0x50, 0x07, 0x61, 0xFF,
+	0x00, 0x05, 0x05, 0xDD, 0xF6, 0x9F, 0x0B, 0x6E, 0xFE, 0xF5, 0xF6, 0x3F, 0x28, 0x6B, 0xE7, 0x0D,
+	0xC7, 0x18, 0xCD, 0x7D, 0x21, 0xFF, 0x00, 0x05, 0x07, 0xFF, 0x00, 0x8F, 0x9F, 0x0A, 0xFF, 0x00,
+	0xBD, 0x7D, 0xFC, 0xA1, 0xAF, 0x9B, 0xEB, 0xFC, 0xD5, 0xF1, 0xFB, 0x5F, 0x13, 0xF1, 0xB7, 0xFE,
+	0xEF, 0xFE, 0x92, 0x8F, 0xDF, 0xB8, 0x1E, 0x31, 0x7C, 0x37, 0x49, 0xDB, 0x5B, 0xBF, 0xCC, 0x28,
+	0xA2, 0x8A, 0xFC, 0x54, 0xFA, 0xE0, 0x39, 0xAF, 0xB1, 0x3F, 0x61, 0x93, 0x8F, 0x82, 0xEE, 0x7F,
+	0xEA, 0x33, 0x2F, 0xF2, 0x8E, 0xBE, 0x3B, 0xAF, 0xB1, 0x3F, 0x61, 0x9F, 0xF9, 0x22, 0xED, 0xFF,
+	0x00, 0x61, 0xA9, 0x7F, 0xF4, 0x18, 0xEB, 0xFA, 0x2F, 0xE8, 0xCA, 0xFF, 0x00, 0xE3, 0x61, 0x3F,
+	0xFA, 0xF5, 0x3F, 0xD0, 0xF8, 0x3F, 0x11, 0x39, 0xBF, 0xB0, 0x62, 0xBF, 0xBE, 0x8F, 0x89, 0x7F,
+	0xE0, 0xA8, 0x9F, 0xF2, 0x77, 0x5A, 0xA7, 0xFD, 0x82, 0x74, 0xFF, 0x00, 0xFD, 0x14, 0x2B, 0xE7,
+	0x9A, 0xFA, 0x1B, 0xFE, 0x0A, 0x87, 0xFF, 0x00, 0x27, 0x73, 0xAA, 0x7F, 0xD8, 0x26, 0xC3, 0xFF,
+	0x00, 0x45, 0x0A, 0xF9, 0xE6, 0xBF, 0xD0, 0x93, 0xF2, 0x0A, 0x6B, 0xF7, 0x68, 0x28, 0xA2, 0x8A,
+	0x0B, 0x0A, 0xFD, 0x8F, 0xFD, 0x98, 0x7F, 0xE4, 0xDA, 0xBE, 0x1E, 0x7F, 0xD8, 0x8D, 0xA4, 0xFF,
+	0x00, 0xE9, 0x1C, 0x55, 0xF8, 0xE1, 0x5F, 0xB1, 0xFF, 0x00, 0xB3, 0x0F, 0xFC, 0x9B, 0x57, 0xC3,
+	0xCF, 0xFB, 0x11, 0xB4, 0x9F, 0xFD, 0x23, 0x8A, 0x83, 0x9F, 0x13, 0xF0, 0xC4, 0xFC, 0xDA, 0xFD,
+	0xB4, 0xFF, 0x00, 0xE4, 0xEB, 0xBC, 0x6D, 0xFF, 0x00, 0x61, 0xC3, 0xFF, 0x00, 0xA0, 0xAD, 0x79,
+	0x62, 0x7D, 0xC1, 0xF4, 0xAF, 0x53, 0xFD, 0xB4, 0xFF, 0x00, 0xE4, 0xEB, 0xBC, 0x6D, 0xFF, 0x00,
+	0x61, 0xC3, 0xFF, 0x00, 0xA0, 0xAD, 0x79, 0x62, 0x7D, 0xC1, 0xF4, 0xA0, 0xE3, 0x16, 0x8A, 0x28,
+	0xA0, 0x02, 0xBE, 0xF4, 0xFF, 0x00, 0x82, 0x43, 0x80, 0xDF, 0x0C, 0xFC, 0x64, 0xAC, 0x38, 0x3A,
+	0xE4, 0x20, 0xFF, 0x00, 0xDF, 0x9A, 0xF8, 0x2E, 0xBE, 0xF4, 0xFF, 0x00, 0x82, 0x42, 0xFF, 0x00,
+	0xC9, 0x35, 0xF1, 0x87, 0xFD, 0x87, 0x20, 0xFF, 0x00, 0xD1, 0x34, 0x01, 0xE3, 0xDF, 0xF0, 0x55,
+	0x1F, 0xF9, 0x39, 0x9B, 0x7F, 0xFB, 0x16, 0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0xFA, 0x4F,
+	0xFE, 0x0A, 0xA3, 0xFF, 0x00, 0x27, 0x33, 0x6F, 0xFF, 0x00, 0x62, 0xC5, 0xAF, 0xFE, 0x87, 0x2D,
+	0x7C, 0xD9, 0x40, 0x05, 0x14, 0x51, 0x40, 0x07, 0x6F, 0xC2, 0xBE, 0xE7, 0xFF, 0x00, 0x82, 0x41,
+	0x00, 0xDE, 0x1B, 0xF1, 0xF2, 0xB0, 0xE0, 0xEA, 0x16, 0x00, 0xFF, 0x00, 0xDF, 0xB9, 0xAB, 0xE1,
+	0x8E, 0xDF, 0x85, 0x7D, 0xD1, 0xFF, 0x00, 0x04, 0x80, 0xFF, 0x00, 0x91, 0x73, 0xC7, 0xDF, 0xF6,
+	0x10, 0xB0, 0xFF, 0x00, 0xD1, 0x73, 0x50, 0x07, 0x95, 0x7F, 0xC1, 0x54, 0x7F, 0xE4, 0xE6, 0x6D,
+	0xFF, 0x00, 0xEC, 0x58, 0xB5, 0xFF, 0x00, 0xD0, 0xE5, 0xAF, 0x9B, 0x2B, 0xE9, 0x3F, 0xF8, 0x2A,
+	0x8F, 0xFC, 0x9C, 0xCD, 0xBF, 0xFD, 0x8B, 0x16, 0xBF, 0xFA, 0x1C, 0xB5, 0xF3, 0x65, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x1D, 0xBF, 0x0A, 0xFB, 0x93, 0xFE, 0x09, 0x0F, 0xFF, 0x00, 0x22, 0xDF, 0x8F,
+	0x73, 0xFF, 0x00, 0x41, 0x0B, 0x1F, 0xFD, 0x17, 0x35, 0x7C, 0x37, 0xDB, 0xF0, 0xAF, 0xB9, 0x3F,
+	0xE0, 0x90, 0xDF, 0xF2, 0x2D, 0xF8, 0xF7, 0xFE, 0xC2, 0x16, 0x3F, 0xFA, 0x2E, 0x6A, 0x52, 0xF8,
+	0x40, 0xFB, 0x36, 0x0E, 0x22, 0x5E, 0x29, 0xF4, 0xD8, 0x3F, 0xD5, 0x2D, 0x3A, 0x98, 0x05, 0x07,
+	0xA5, 0x14, 0x8C, 0x70, 0xA4, 0xE3, 0xB7, 0x6A, 0x00, 0xF8, 0x57, 0xFE, 0x0A, 0xFB, 0xFF, 0x00,
+	0x23, 0x27, 0x81, 0xFF, 0x00, 0xEB, 0xCA, 0xFB, 0xFF, 0x00, 0x46, 0x47, 0x5F, 0x1B, 0x57, 0xDB,
+	0xDF, 0xF0, 0x55, 0x9F, 0x03, 0x78, 0xE7, 0xC6, 0x9E, 0x21, 0xF0, 0x6B, 0xF8, 0x3B, 0xC1, 0xDA,
+	0xA6, 0xAC, 0x2D, 0xAC, 0xEF, 0x45, 0xC2, 0xE9, 0x76, 0x33, 0x4C, 0x61, 0xCB, 0xC3, 0x82, 0x76,
+	0x71, 0x83, 0x5F, 0x24, 0xFF, 0x00, 0xC2, 0x91, 0xF8, 0xDB, 0xFF, 0x00, 0x44, 0x7B, 0xC5, 0x5F,
+	0xF8, 0x21, 0xB8, 0xFF, 0x00, 0xE2, 0x28, 0x03, 0x97, 0xA2, 0xBA, 0x8F, 0xF8, 0x52, 0x3F, 0x1B,
+	0x7F, 0xE8, 0x8F, 0x78, 0xAB, 0xFF, 0x00, 0x04, 0x37, 0x1F, 0xFC, 0x45, 0x1F, 0xF0, 0xA4, 0x7E,
+	0x36, 0xFF, 0x00, 0xD1, 0x1E, 0xF1, 0x57, 0xFE, 0x08, 0x6E, 0x3F, 0xF8, 0x8A, 0x00, 0xE5, 0xC7,
+	0x5A, 0xFA, 0xBF, 0xFE, 0x09, 0x23, 0xFF, 0x00, 0x25, 0xA7, 0xC4, 0xDF, 0xF6, 0x2A, 0x2F, 0xFE,
+	0x94, 0xC5, 0x5F, 0x3C, 0x2F, 0xC1, 0x0F, 0x8D, 0xA5, 0xB1, 0xFF, 0x00, 0x0A, 0x77, 0xC5, 0x47,
+	0xD8, 0xE8, 0x37, 0x3C, 0xFE, 0x49, 0x9F, 0xCB, 0x9A, 0xFA, 0x73, 0xFE, 0x09, 0x73, 0xF0, 0xFF,
+	0x00, 0xC7, 0xFE, 0x0C, 0xF8, 0xBD, 0xAF, 0x5E, 0x78, 0xBB, 0xC1, 0x7A, 0xB6, 0x97, 0x6F, 0x37,
+	0x87, 0x8A, 0xC3, 0x2E, 0xA9, 0xA5, 0x4D, 0x6A, 0x19, 0xBC, 0xF8, 0xBE, 0x50, 0x65, 0x40, 0x4D,
+	0x0F, 0x60, 0x3D, 0x13, 0xFE, 0x0A, 0xCB, 0xFF, 0x00, 0x26, 0xEF, 0xA1, 0xFF, 0x00, 0xD8, 0xE5,
+	0x0F, 0xFE, 0x92, 0xDC, 0xD7, 0xE7, 0xBD, 0x7E, 0x8A, 0x7F, 0xC1, 0x50, 0xBC, 0x2B, 0xE2, 0x9F,
+	0x18, 0x7C, 0x08, 0xD1, 0x74, 0xDF, 0x08, 0xF8, 0x67, 0x50, 0xD5, 0x2E, 0x53, 0xC5, 0x71, 0x48,
+	0xD6, 0xDA, 0x75, 0xAC, 0x92, 0xCA, 0x23, 0x16, 0xB7, 0x39, 0x6C, 0x27, 0x3C, 0x64, 0x7B, 0x57,
+	0xC2, 0x7F, 0xF0, 0xA4, 0x7E, 0x36, 0xFF, 0x00, 0xD1, 0x1E, 0xF1, 0x57, 0xFE, 0x08, 0x6E, 0x3F,
+	0xF8, 0x8A, 0x98, 0xF5, 0x1F, 0x32, 0x94, 0x53, 0x47, 0x2F, 0x45, 0x75, 0x1F, 0xF0, 0xA4, 0x7E,
+	0x36, 0xFF, 0x00, 0xD1, 0x1E, 0xF1, 0x57, 0xFE, 0x08, 0x6E, 0x3F, 0xF8, 0x8A, 0x3F, 0xE1, 0x48,
+	0xFC, 0x6D, 0xFF, 0x00, 0xA2, 0x3D, 0xE2, 0xAF, 0xFC, 0x10, 0xDC, 0x7F, 0xF1, 0x15, 0x42, 0x39,
+	0x7A, 0xF7, 0xAF, 0xF8, 0x26, 0xC7, 0xFC, 0x9D, 0xCE, 0x83, 0xFF, 0x00, 0x60, 0xFD, 0x43, 0xFF,
+	0x00, 0x49, 0xDE, 0xBC, 0xB7, 0xFE, 0x14, 0x8F, 0xC6, 0xDF, 0xFA, 0x23, 0xDE, 0x2A, 0xFF, 0x00,
+	0xC1, 0x0D, 0xC7, 0xFF, 0x00, 0x11, 0x5E, 0xD9, 0xFF, 0x00, 0x04, 0xFB, 0xF8, 0x61, 0xF1, 0x3B,
+	0xC2, 0x7F, 0xB5, 0x1E, 0x8D, 0xAC, 0xF8, 0x93, 0xE1, 0xEE, 0xB7, 0xA6, 0xD9, 0xA5, 0xAD, 0xE2,
+	0xC9, 0x71, 0xA8, 0x68, 0xB7, 0x16, 0xF1, 0xA3, 0x7D, 0x9D, 0xFF, 0x00, 0x8E, 0x54, 0xA0, 0x0F,
+	0xAA, 0xBF, 0xE0, 0xA2, 0x9F, 0xF2, 0x67, 0x7E, 0x2D, 0xFF, 0x00, 0xAE, 0x96, 0x3F, 0xFA, 0x5B,
+	0x05, 0x7E, 0x60, 0xD7, 0xEA, 0x2F, 0xED, 0xF3, 0xA1, 0xEB, 0x5E, 0x25, 0xFD, 0x94, 0xFC, 0x4D,
+	0xA2, 0xF8, 0x6F, 0x46, 0xB8, 0xD4, 0x2F, 0x26, 0x92, 0xC4, 0x5B, 0xDA, 0x5A, 0x42, 0xD2, 0x49,
+	0x21, 0x17, 0xB0, 0x92, 0x14, 0x2F, 0x27, 0x8F, 0x4A, 0xFC, 0xE1, 0x1F, 0x04, 0x7E, 0x36, 0x63,
+	0xFE, 0x48, 0xF7, 0x8B, 0x3F, 0xE0, 0x5A, 0x0D, 0xC6, 0x7F, 0xF4, 0x0A, 0x98, 0x7F, 0x5F, 0x72,
+	0x1D, 0xD3, 0x8A, 0xB7, 0xF5, 0xA9, 0xCC, 0x51, 0x5D, 0x47, 0xFC, 0x29, 0x1F, 0x8D, 0xBF, 0xF4,
+	0x47, 0xBC, 0x55, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x22, 0x8F, 0xF8, 0x52, 0x3F, 0x1B, 0x7F,
+	0xE8, 0x8F, 0x78, 0xAB, 0xFF, 0x00, 0x04, 0x37, 0x1F, 0xFC, 0x45, 0x50, 0x8E, 0x5E, 0xBD, 0x13,
+	0xF6, 0x4A, 0xFF, 0x00, 0x93, 0x9C, 0xF0, 0x0F, 0xFD, 0x8D, 0x56, 0x9F, 0xFA, 0x10, 0xAC, 0x3F,
+	0xF8, 0x52, 0x3F, 0x1B, 0x7F, 0xE8, 0x8F, 0x78, 0xAB, 0xFF, 0x00, 0x04, 0x37, 0x1F, 0xFC, 0x45,
+	0x77, 0x9F, 0xB3, 0x0F, 0xC2, 0x1F, 0x8B, 0x9A, 0x2F, 0xED, 0x0F, 0xE0, 0xBD, 0x5B, 0x55, 0xF8,
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+	0xDD, 0xB3, 0xFE, 0x77, 0x15, 0xF3, 0xEF, 0xFC, 0x23, 0x7A, 0xCF, 0xFD, 0x0B, 0xF7, 0x5F, 0xF8,
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+	0x8A, 0x3F, 0xE1, 0x48, 0xFC, 0x6D, 0xFF, 0x00, 0xA2, 0x3D, 0xE2, 0xAF, 0xFC, 0x10, 0xDC, 0x7F,
+	0xF1, 0x14, 0x01, 0xCB, 0xD7, 0xE9, 0xA7, 0xFC, 0x13, 0x57, 0xFE, 0x4D, 0x1F, 0x43, 0xFF, 0x00,
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+	0x88, 0xF7, 0x8A, 0xBF, 0xF0, 0x43, 0x71, 0xFF, 0x00, 0xC4, 0x57, 0xE8, 0xC7, 0xFC, 0x13, 0xCF,
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+	0x8A, 0xBF, 0xF0, 0x43, 0x71, 0xFF, 0x00, 0xC4, 0x51, 0xFF, 0x00, 0x0A, 0x47, 0xE3, 0x6F, 0xFD,
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+	0xA5, 0x85, 0xFD, 0xAC, 0xB0, 0x4F, 0x07, 0x86, 0xEC, 0x63, 0x9A, 0x19, 0xE3, 0x2A, 0xF1, 0xB8,
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+	0xE1, 0xEF, 0x10, 0x82, 0x69, 0xAD, 0x64, 0x73, 0xE6, 0x41, 0x23, 0x47, 0x3C, 0x6D, 0xD5, 0x19,
+	0x4E, 0x08, 0xFC, 0x0D, 0x47, 0xC7, 0xF0, 0xF4, 0xAF, 0x00, 0xF8, 0xE8, 0xFF, 0x00, 0xB4, 0x87,
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+	0x2E, 0x64, 0x82, 0xDF, 0x43, 0x9E, 0x6B, 0x5B, 0xE5, 0xF9, 0x0F, 0xDD, 0x09, 0x8C, 0x81, 0xFC,
+	0x63, 0x83, 0xD6, 0xBD, 0x57, 0xE1, 0x7F, 0x8F, 0x35, 0xEF, 0x1D, 0x58, 0xE3, 0x5F, 0xF8, 0x75,
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+	0x52, 0x78, 0xCC, 0x0C, 0x5E, 0x27, 0x06, 0xBE, 0xDC, 0x55, 0xE5, 0x15, 0xFD, 0xF8, 0xAB, 0xDB,
+	0xD5, 0x5D, 0x77, 0xB1, 0xF7, 0xD9, 0x5F, 0x10, 0xE1, 0xF1, 0x8B, 0x92, 0xA3, 0xE5, 0x97, 0xE0,
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+	0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05,
+	0x7E, 0x1C, 0x7F, 0xC1, 0x4E, 0xBF, 0xE4, 0xFB, 0x7C, 0x7D, 0xFF, 0x00, 0x61, 0x3B, 0x6F, 0xFD,
+	0x24, 0x86, 0xBF, 0x71, 0xEB, 0xF0, 0xE3, 0xFE, 0x0A, 0x75, 0xFF, 0x00, 0x27, 0xDB, 0xE3, 0xEF,
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+	0xFF, 0x00, 0x5E, 0x97, 0xFE, 0x94, 0x8F, 0xE8, 0x0F, 0xA3, 0xAF, 0xFC, 0x96, 0x15, 0xBF, 0xEB,
+	0xD3, 0xFC, 0xD1, 0xE0, 0x47, 0xAD, 0x14, 0x1E, 0xB4, 0x57, 0xF6, 0xE1, 0xFD, 0xB0, 0x14, 0x51,
+	0x45, 0x00, 0x77, 0x5F, 0xB3, 0x3F, 0xFC, 0x9C, 0x67, 0xC3, 0xDF, 0xFB, 0x1D, 0x34, 0xBF, 0xFD,
+	0x2C, 0x8A, 0xBF, 0xA0, 0x88, 0xBF, 0xD5, 0xAF, 0xD2, 0xBF, 0x9F, 0x7F, 0xD9, 0x9F, 0xFE, 0x4E,
+	0x33, 0xE1, 0xEF, 0xFD, 0x8E, 0x9A, 0x5F, 0xFE, 0x96, 0x45, 0x5F, 0xD0, 0x44, 0x5F, 0xEA, 0xD7,
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+	0xFF, 0x00, 0xA4, 0xAF, 0xFC, 0x8E, 0x30, 0x1F, 0xF5, 0xEE, 0x5F, 0xFA, 0x52, 0x1D, 0x45, 0x14,
+	0x57, 0xF2, 0xA9, 0xFC, 0xCE, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45,
+	0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x46, 0x58, 0x0E, 0x4D, 0x57,
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+	0x58, 0xD3, 0xA9, 0x35, 0x87, 0xE3, 0xBF, 0x17, 0xDC, 0xF8, 0x27, 0x48, 0xFE, 0xD0, 0xB3, 0xF0,
+	0x76, 0xB7, 0xAB, 0xDC, 0x38, 0x3F, 0x67, 0xB4, 0xD2, 0x74, 0xDB, 0x89, 0x99, 0xDB, 0xDD, 0x91,
+	0x36, 0xA8, 0xFA, 0xD7, 0x8F, 0xFC, 0x3C, 0xF1, 0x2F, 0xED, 0x25, 0xF1, 0x0F, 0xF6, 0x92, 0xF0,
+	0x6D, 0xDF, 0x8B, 0x3E, 0x1B, 0x78, 0x8B, 0x47, 0xD0, 0xAD, 0x7C, 0x49, 0x6A, 0xED, 0x67, 0xFD,
+	0x8D, 0x71, 0x1C, 0x31, 0x8F, 0x34, 0x61, 0xA4, 0x77, 0xF9, 0x58, 0xE3, 0xA9, 0x1C, 0x1E, 0xDC,
+	0x57, 0xF4, 0x07, 0x85, 0x7F, 0x47, 0xFE, 0x30, 0xF1, 0x0A, 0xB4, 0x71, 0x33, 0x83, 0xC3, 0xE1,
+	0x2F, 0xAD, 0x49, 0xA6, 0xB9, 0x97, 0x55, 0x4D, 0x3F, 0x89, 0xF9, 0xED, 0xE6, 0x78, 0x59, 0x96,
+	0x79, 0x85, 0xC0, 0xC7, 0x91, 0x3B, 0xCF, 0xB7, 0x6F, 0x53, 0xE9, 0xDD, 0x7F, 0xE1, 0xB6, 0xA5,
+	0xA2, 0xFC, 0x2B, 0xF1, 0x1F, 0x8C, 0x35, 0xA9, 0xDA, 0xDA, 0x6B, 0x1F, 0x0F, 0xDE, 0xDC, 0xDA,
+	0x46, 0x8D, 0x92, 0x8C, 0x96, 0xEC, 0xE1, 0x98, 0xF6, 0xFB, 0xBC, 0x7A, 0x57, 0xE6, 0x4E, 0xA3,
+	0xA8, 0x5E, 0x6A, 0x97, 0xB2, 0x5E, 0xEA, 0xF7, 0x52, 0x4F, 0x71, 0x24, 0x8C, 0xD2, 0x4D, 0x23,
+	0x65, 0xA4, 0x62, 0x72, 0x58, 0x9E, 0xE4, 0x9E, 0x4D, 0x7E, 0xBF, 0xFC, 0x68, 0x82, 0x6B, 0xDF,
+	0x83, 0x1E, 0x2A, 0xB6, 0xB4, 0x46, 0x9E, 0x59, 0xBC, 0x33, 0x7C, 0xB0, 0xA4, 0x2B, 0x96, 0x90,
+	0x98, 0x1F, 0x01, 0x57, 0xB9, 0xAF, 0xCA, 0x33, 0xF0, 0x43, 0xE3, 0x6A, 0x9C, 0x1F, 0x83, 0xDE,
+	0x2A, 0xFF, 0x00, 0xC1, 0x0C, 0xFF, 0x00, 0xD1, 0x31, 0xF9, 0x71, 0x5F, 0xE9, 0x17, 0x87, 0xFE,
+	0x18, 0x70, 0xA7, 0x86, 0xF9, 0x5A, 0xC2, 0xE5, 0x34, 0x6D, 0x26, 0xBD, 0xEA, 0x92, 0xD6, 0x73,
+	0x7D, 0xE4, 0xFF, 0x00, 0x45, 0x64, 0xBB, 0x1F, 0x9F, 0x63, 0x73, 0x0C, 0x4E, 0x3E, 0xA7, 0x35,
+	0x49, 0x69, 0xDB, 0xA1, 0xCB, 0xE7, 0x3C, 0xD1, 0x5D, 0x47, 0xFC, 0x29, 0x1F, 0x8D, 0xBF, 0xF4,
+	0x47, 0xBC, 0x55, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x22, 0x8F, 0xF8, 0x52, 0x3F, 0x1B, 0x7F,
+	0xE8, 0x8F, 0x78, 0xAB, 0xFF, 0x00, 0x04, 0x37, 0x1F, 0xFC, 0x45, 0x7E, 0x8B, 0x7E, 0xC7, 0x0D,
+	0xBA, 0x23, 0x97, 0xAF, 0xA4, 0xBF, 0xE0, 0x95, 0xBF, 0xF2, 0x73, 0x53, 0xFF, 0x00, 0xD8, 0xAD,
+	0x7D, 0xFF, 0x00, 0xA3, 0x6D, 0xEB, 0xC5, 0x7F, 0xE1, 0x48, 0xFC, 0x6D, 0xFF, 0x00, 0xA2, 0x3D,
+	0xE2, 0xAF, 0xFC, 0x10, 0xDC, 0x7F, 0xF1, 0x15, 0xF4, 0x37, 0xFC, 0x13, 0x37, 0xE1, 0xB7, 0xC4,
+	0x4F, 0x09, 0xFE, 0xD1, 0x57, 0x1A, 0xB7, 0x8A, 0xBC, 0x09, 0xAD, 0x69, 0x76, 0xCD, 0xE1, 0xDB,
+	0xA5, 0xF3, 0xF5, 0x0D, 0x2E, 0x68, 0x54, 0xB6, 0xFB, 0x6E, 0x32, 0xFC, 0x52, 0x03, 0xE8, 0x7F,
+	0xF8, 0x29, 0x57, 0xFC, 0x9A, 0x56, 0xBD, 0xFF, 0x00, 0x5F, 0xB6, 0x3F, 0xFA, 0x50, 0xB5, 0xF9,
+	0x95, 0x5F, 0xA8, 0x1F, 0xF0, 0x50, 0xCD, 0x03, 0xC4, 0x1E, 0x2A, 0xFD, 0x96, 0xF5, 0xAD, 0x1B,
+	0xC3, 0x1A, 0x2D, 0xD6, 0xA1, 0x79, 0x25, 0xED, 0x99, 0x8A, 0xD6, 0xCE, 0xD1, 0xE6, 0x93, 0x02,
+	0xE1, 0x32, 0x40, 0x8F, 0x9A, 0xFC, 0xE6, 0x5F, 0x82, 0x3F, 0x1A, 0xF6, 0xFC, 0xBF, 0x07, 0xBC,
+	0x59, 0x8E, 0xDB, 0xB4, 0x0B, 0x9C, 0xFE, 0xA9, 0x40, 0x1C, 0xC5, 0x15, 0xD4, 0x7F, 0xC2, 0x91,
+	0xF8, 0xDB, 0xFF, 0x00, 0x44, 0x7B, 0xC5, 0x5F, 0xF8, 0x21, 0xB8, 0xFF, 0x00, 0xE2, 0x28, 0xFF,
+	0x00, 0x85, 0x23, 0xF1, 0xB7, 0xFE, 0x88, 0xF7, 0x8A, 0xBF, 0xF0, 0x43, 0x71, 0xFF, 0x00, 0xC4,
+	0x50, 0x07, 0x2F, 0x5F, 0x71, 0xFF, 0x00, 0xC1, 0x20, 0xFF, 0x00, 0xE4, 0x5B, 0xF1, 0xD7, 0xFD,
+	0x7F, 0xD8, 0xFF, 0x00, 0xE8, 0xAB, 0x8A, 0xF9, 0x13, 0xFE, 0x14, 0x8F, 0xC6, 0xDF, 0xFA, 0x23,
+	0xDE, 0x2A, 0xFF, 0x00, 0xC1, 0x0D, 0xC7, 0xFF, 0x00, 0x11, 0x5F, 0x66, 0x7F, 0xC1, 0x2A, 0x3C,
+	0x17, 0xE3, 0x4F, 0x07, 0x68, 0x1E, 0x32, 0x83, 0xC5, 0x9E, 0x16, 0xD4, 0xB4, 0x99, 0x2E, 0x6F,
+	0x2C, 0xCD, 0xBC, 0x7A, 0xA5, 0x8C, 0xD0, 0x97, 0x50, 0xB2, 0xEE, 0x23, 0x7F, 0x6C, 0xD0, 0x07,
+	0x41, 0xFF, 0x00, 0x05, 0x07, 0xFF, 0x00, 0x8F, 0x9F, 0x0A, 0xFF, 0x00, 0xBD, 0x7D, 0xFC, 0xA1,
+	0xAF, 0x9B, 0xEB, 0xE9, 0x5F, 0xDB, 0xEA, 0xC7, 0x50, 0xD4, 0x6F, 0x3C, 0x2A, 0x74, 0xFD, 0x3E,
+	0x49, 0xF6, 0x8B, 0xD2, 0xDE, 0x5C, 0x7B, 0xF6, 0xFF, 0x00, 0xC7, 0xBD, 0x7C, 0xF0, 0x7C, 0x37,
+	0xAC, 0xF4, 0xFE, 0xC1, 0xBA, 0x3E, 0xFF, 0x00, 0x65, 0x7E, 0x6B, 0xFC, 0xE1, 0xF1, 0xDB, 0x2D,
+	0xCC, 0x31, 0x3E, 0x25, 0x63, 0x2A, 0x52, 0xA5, 0x26, 0xBD, 0xDD, 0x54, 0x5B, 0xE8, 0xBB, 0x23,
+	0xF7, 0xAE, 0x09, 0xAF, 0x46, 0x9F, 0x0E, 0xD2, 0x52, 0x9A, 0x5A, 0xCB, 0x76, 0xBB, 0xB2, 0x8D,
+	0x15, 0x7B, 0xFE, 0x11, 0xAD, 0x67, 0xFE, 0x85, 0xFB, 0xAF, 0xFC, 0x05, 0x7A, 0x3F, 0xE1, 0x1A,
+	0xD6, 0x7F, 0xE8, 0x5F, 0xBA, 0xFF, 0x00, 0xC0, 0x57, 0xAF, 0xC7, 0x7F, 0xB1, 0xB3, 0x4F, 0xF9,
+	0xF3, 0x2F, 0xFC, 0x06, 0x5F, 0xE4, 0x7D, 0x5F, 0xD6, 0xB0, 0xFF, 0x00, 0xCE, 0xBE, 0xF5, 0xFE,
+	0x65, 0x1A, 0xFB, 0x13, 0xF6, 0x19, 0xFF, 0x00, 0x92, 0x2E, 0xDF, 0xF6, 0x1A, 0x97, 0xFF, 0x00,
+	0x41, 0x8E, 0xBE, 0x49, 0xFF, 0x00, 0x84, 0x6B, 0x58, 0xEF, 0xE1, 0xFB, 0xAF, 0xFC, 0x05, 0x7A,
+	0xFA, 0xE7, 0xF6, 0x26, 0xB4, 0xB9, 0xB0, 0xF8, 0x38, 0xD0, 0xDD, 0xDB, 0x49, 0x0B, 0x7F, 0x6B,
+	0x4D, 0x88, 0xE4, 0x5C, 0x71, 0xB5, 0x2B, 0xFA, 0x13, 0xE8, 0xD9, 0x96, 0xE3, 0xB0, 0xDE, 0x20,
+	0x4A, 0x55, 0x69, 0xCA, 0x2B, 0xD9, 0x4B, 0x57, 0x16, 0x97, 0x4E, 0xAD, 0x1F, 0x0D, 0xE2, 0x05,
+	0x6A, 0x55, 0x32, 0x45, 0x18, 0xC9, 0x37, 0xCC, 0x8F, 0x88, 0xBF, 0xE0, 0xA8, 0x79, 0xFF, 0x00,
+	0x86, 0xB9, 0xD5, 0x3F, 0xEC, 0x13, 0xA7, 0xFF, 0x00, 0xE8, 0xA1, 0x5F, 0x3C, 0xD7, 0xD2, 0x9F,
+	0xF0, 0x53, 0x3F, 0x09, 0x78, 0xA3, 0x56, 0xFD, 0xAC, 0x35, 0x4B, 0xDD, 0x27, 0xC3, 0x57, 0xD3,
+	0x5B, 0xBE, 0x9D, 0x62, 0xBF, 0x68, 0xB7, 0xB3, 0x90, 0x8D, 0xC2, 0x21, 0xC6, 0x47, 0x5A, 0xF9,
+	0xFF, 0x00, 0xFE, 0x10, 0x6F, 0x1B, 0xB7, 0xCC, 0xDE, 0x0C, 0xD5, 0x39, 0xE7, 0xFE, 0x3C, 0x64,
+	0xAF, 0xEF, 0xC3, 0xF2, 0x3A, 0x72, 0xFD, 0xDA, 0x32, 0xE8, 0xAD, 0x4F, 0xF8, 0x41, 0x3C, 0x6D,
+	0xFF, 0x00, 0x42, 0x66, 0xA9, 0xFF, 0x00, 0x80, 0x32, 0x51, 0xFF, 0x00, 0x08, 0x27, 0x8D, 0xBF,
+	0xE8, 0x4C, 0xD5, 0x3F, 0xF0, 0x06, 0x4A, 0x0A, 0xE6, 0x32, 0xEB, 0xF6, 0x3F, 0xF6, 0x61, 0xFF,
+	0x00, 0x93, 0x6A, 0xF8, 0x79, 0xFF, 0x00, 0x62, 0x36, 0x93, 0xFF, 0x00, 0xA4, 0x71, 0x57, 0xE4,
+	0x27, 0xFC, 0x20, 0x9E, 0x36, 0xFF, 0x00, 0xA1, 0x33, 0x54, 0xFF, 0x00, 0xC0, 0x19, 0x2B, 0xF5,
+	0xFB, 0xF6, 0x68, 0x82, 0x7B, 0x5F, 0xD9, 0xC7, 0xE1, 0xFD, 0xAD, 0xCC, 0x0D, 0x1C, 0x91, 0xF8,
+	0x27, 0x49, 0x59, 0x23, 0x91, 0x48, 0x64, 0x61, 0x67, 0x10, 0x20, 0x83, 0xD0, 0x83, 0x41, 0xCF,
+	0x88, 0x97, 0x35, 0x8F, 0xCD, 0x7F, 0xDB, 0x4F, 0xFE, 0x4E, 0xBB, 0xC6, 0xDF, 0xF6, 0x1C, 0x3F,
+	0xFA, 0x0A, 0xD7, 0x96, 0x27, 0xDC, 0x1F, 0x4A, 0xF7, 0x3F, 0xDB, 0x0B, 0xE1, 0x1F, 0xC5, 0x1D,
+	0x73, 0xF6, 0x9A, 0xF1, 0xA6, 0xA9, 0xA3, 0x7C, 0x32, 0xF1, 0x0D, 0xE5, 0xAD, 0xD6, 0xAC, 0xC6,
+	0x2B, 0xAB, 0x5D, 0x16, 0x77, 0x57, 0xE1, 0x31, 0x86, 0x09, 0x82, 0x0F, 0x62, 0x38, 0x35, 0xE6,
+	0xA7, 0xE0, 0x8F, 0xC6, 0xEC, 0xFC, 0xDF, 0x07, 0x7C, 0x57, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE,
+	0x22, 0x83, 0x94, 0xE5, 0xE8, 0xAE, 0xA3, 0xFE, 0x14, 0x8F, 0xC6, 0xDF, 0xFA, 0x23, 0xDE, 0x2A,
+	0xFF, 0x00, 0xC1, 0x0D, 0xC7, 0xFF, 0x00, 0x11, 0x47, 0xFC, 0x29, 0x1F, 0x8D, 0xBF, 0xF4, 0x47,
+	0xBC, 0x55, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x22, 0x80, 0x39, 0x7A, 0xFB, 0xD3, 0xFE, 0x09,
+	0x0B, 0xFF, 0x00, 0x24, 0xD7, 0xC6, 0x1F, 0xF6, 0x1C, 0x83, 0xFF, 0x00, 0x44, 0xD7, 0xC6, 0x7F,
+	0xF0, 0xA4, 0x7E, 0x36, 0xFF, 0x00, 0xD1, 0x1E, 0xF1, 0x57, 0xFE, 0x08, 0x6E, 0x3F, 0xF8, 0x8A,
+	0xFB, 0x73, 0xFE, 0x09, 0x53, 0xE1, 0x2F, 0x16, 0x78, 0x3B, 0xE1, 0xFF, 0x00, 0x8B, 0xAC, 0x7C,
+	0x5B, 0xE1, 0x8D, 0x43, 0x4B, 0xB8, 0x93, 0x58, 0xB7, 0x74, 0xB7, 0xD4, 0x34, 0xF9, 0x2D, 0xD8,
+	0xA9, 0x87, 0x82, 0x03, 0xE3, 0x3F, 0x51, 0x40, 0x1E, 0x1D, 0xFF, 0x00, 0x05, 0x51, 0xFF, 0x00,
+	0x93, 0x99, 0xB7, 0xFF, 0x00, 0xB1, 0x62, 0xD7, 0xFF, 0x00, 0x43, 0x96, 0xBE, 0x6C, 0xAF, 0xAB,
+	0x3F, 0xE0, 0xA6, 0x1F, 0x0E, 0x3E, 0x23, 0x78, 0xBB, 0xF6, 0x8A, 0x87, 0x55, 0xF0, 0x97, 0x80,
+	0xB5, 0xAD, 0x52, 0xD5, 0x7C, 0x3B, 0x6B, 0x1B, 0x5C, 0x69, 0x9A, 0x6C, 0xF2, 0xA2, 0x30, 0x92,
+	0x6F, 0x94, 0x95, 0x04, 0x7E, 0x95, 0xF3, 0xDF, 0xFC, 0x29, 0x1F, 0x8D, 0xBF, 0xF4, 0x47, 0xBC,
+	0x55, 0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x22, 0x80, 0x39, 0x7A, 0x2B, 0xA8, 0xFF, 0x00, 0x85,
+	0x23, 0xF1, 0xB7, 0xFE, 0x88, 0xF7, 0x8A, 0xBF, 0xF0, 0x43, 0x71, 0xFF, 0x00, 0xC4, 0x51, 0xFF,
+	0x00, 0x0A, 0x47, 0xE3, 0x6F, 0xFD, 0x11, 0xEF, 0x15, 0x7F, 0xE0, 0x86, 0xE3, 0xFF, 0x00, 0x88,
+	0xA0, 0x0E, 0x5F, 0xB7, 0xE1, 0x5F, 0x74, 0x7F, 0xC1, 0x20, 0x3F, 0xE4, 0x5C, 0xF1, 0xF7, 0xFD,
+	0x84, 0x2C, 0x3F, 0xF4, 0x5C, 0xD5, 0xF1, 0xFA, 0xFC, 0x10, 0xF8, 0xD8, 0xC7, 0x07, 0xE0, 0xEF,
+	0x8A, 0x8F, 0xD7, 0xC3, 0xF7, 0x47, 0xFF, 0x00, 0x41, 0x4C, 0xD7, 0xDA, 0x3F, 0xF0, 0x4A, 0x3F,
+	0x06, 0xF8, 0xCF, 0xC1, 0x7E, 0x1C, 0xF1, 0xAD, 0xBF, 0x8C, 0x3C, 0x2B, 0xA9, 0x69, 0xB2, 0x4D,
+	0x79, 0x62, 0xD6, 0xE9, 0xA9, 0x69, 0xB2, 0x5B, 0x34, 0x8B, 0xB6, 0x6E, 0x40, 0x91, 0x41, 0x20,
+	0x67, 0xAD, 0x00, 0x78, 0xCF, 0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B, 0x5F,
+	0xFD, 0x0E, 0x5A, 0xF9, 0xB2, 0xBE, 0xAC, 0xFF, 0x00, 0x82, 0x98, 0x7C, 0x38, 0xF8, 0x8D, 0xE2,
+	0xEF, 0xDA, 0x2A, 0x1D, 0x57, 0xC2, 0x5E, 0x02, 0xD6, 0xB5, 0x4B, 0x55, 0xF0, 0xED, 0xAC, 0x6D,
+	0x71, 0xA6, 0x69, 0xB3, 0xCA, 0x88, 0xC2, 0x49, 0xBE, 0x52, 0x54, 0x11, 0xFA, 0x57, 0xCF, 0x7F,
+	0xF0, 0xA4, 0x7E, 0x36, 0xFF, 0x00, 0xD1, 0x1E, 0xF1, 0x57, 0xFE, 0x08, 0x6E, 0x3F, 0xF8, 0x8A,
+	0x00, 0xE5, 0xE8, 0xAE, 0xA3, 0xFE, 0x14, 0x8F, 0xC6, 0xDF, 0xFA, 0x23, 0xDE, 0x2A, 0xFF, 0x00,
+	0xC1, 0x0D, 0xC7, 0xFF, 0x00, 0x11, 0x47, 0xFC, 0x29, 0x1F, 0x8D, 0xBF, 0xF4, 0x47, 0xBC, 0x55,
+	0xFF, 0x00, 0x82, 0x1B, 0x8F, 0xFE, 0x22, 0x80, 0x39, 0x7E, 0xDF, 0x85, 0x7D, 0xC9, 0xFF, 0x00,
+	0x04, 0x86, 0xFF, 0x00, 0x91, 0x6F, 0xC7, 0xBF, 0xF6, 0x10, 0xB1, 0xFF, 0x00, 0xD1, 0x73, 0x57,
+	0xC8, 0x6B, 0xF0, 0x43, 0xE3, 0x63, 0x1C, 0x1F, 0x83, 0xBE, 0x2A, 0x3F, 0x5F, 0x0F, 0xDD, 0x1F,
+	0xFD, 0x05, 0x33, 0x5F, 0x65, 0xFF, 0x00, 0xC1, 0x2B, 0x3C, 0x1B, 0xE3, 0x2F, 0x05, 0xE8, 0x3E,
+	0x32, 0xB6, 0xF1, 0x97, 0x85, 0xB5, 0x1D, 0x2D, 0xAE, 0x2E, 0xAC, 0xDA, 0x05, 0xD4, 0xF4, 0xF9,
+	0x2D, 0x5A, 0x41, 0xB2, 0x6E, 0x82, 0x45, 0x04, 0xFE, 0x75, 0x32, 0xF8, 0x40, 0xFA, 0xFE, 0x0F,
+	0xF5, 0x4B, 0x4E, 0xA8, 0xED, 0x49, 0x31, 0xF2, 0x3F, 0x8B, 0xD2, 0xA4, 0xAA, 0x0B, 0xF3, 0x6A,
+	0x14, 0x8E, 0x4A, 0xA3, 0x30, 0xF4, 0xA5, 0xA4, 0x6C, 0x95, 0x20, 0x1E, 0xD4, 0x01, 0x93, 0x71,
+	0xA8, 0x69, 0xBA, 0x76, 0xB1, 0x30, 0xBE, 0xBD, 0x86, 0xDD, 0x7E, 0xCF, 0x18, 0x53, 0x25, 0xC0,
+	0x5C, 0xFC, 0xCF, 0xEB, 0x4F, 0xFF, 0x00, 0x84, 0x8F, 0xC3, 0x9F, 0xF4, 0x1E, 0xB2, 0xFF, 0x00,
+	0xC0, 0xA8, 0xEB, 0xE2, 0x9F, 0xF8, 0x2B, 0xF1, 0xCF, 0x89, 0x3C, 0x0E, 0x7F, 0xE9, 0xCE, 0xFB,
+	0xFF, 0x00, 0x46, 0x47, 0x5F, 0x1A, 0xD0, 0x07, 0xED, 0x07, 0xFC, 0x24, 0x7E, 0x1C, 0xFF, 0x00,
+	0xA0, 0xF5, 0x97, 0xFE, 0x05, 0x47, 0x47, 0xFC, 0x24, 0x7E, 0x1C, 0xFF, 0x00, 0xA0, 0xF5, 0x97,
+	0xFE, 0x05, 0x47, 0x5F, 0x8B, 0xF4, 0x50, 0x07, 0xED, 0x00, 0xF1, 0x1F, 0x87, 0x41, 0xC8, 0xD7,
+	0xAC, 0xBF, 0xF0, 0x2A, 0x3A, 0x9A, 0xCB, 0x56, 0xD2, 0xF5, 0x36, 0x65, 0xB3, 0xD4, 0xA1, 0x99,
+	0x97, 0xA8, 0x8E, 0x5C, 0xE2, 0xBF, 0x16, 0x47, 0x5A, 0xFA, 0xBB, 0xFE, 0x09, 0x25, 0xFF, 0x00,
+	0x25, 0x9F, 0xC4, 0xDF, 0xF6, 0x29, 0xAF, 0xFE, 0x94, 0xC5, 0x40, 0x1F, 0x7D, 0x5E, 0xDE, 0xD9,
+	0xD8, 0xA0, 0x9E, 0xFA, 0xE6, 0x38, 0x53, 0x9F, 0xDE, 0x49, 0x26, 0xDE, 0xDE, 0xB5, 0x5F, 0xFE,
+	0x12, 0x3F, 0x0E, 0x7F, 0xD0, 0x7A, 0xCB, 0xFF, 0x00, 0x02, 0xA3, 0xAF, 0x9B, 0x3F, 0xE0, 0xAD,
+	0x1F, 0xF2, 0x6E, 0x9A, 0x47, 0xFD, 0x8E, 0xD6, 0xFF, 0x00, 0xFA, 0x49, 0x75, 0x5F, 0x9E, 0x54,
+	0x01, 0xFB, 0x41, 0xFF, 0x00, 0x09, 0x1F, 0x87, 0x3F, 0xE8, 0x3D, 0x65, 0xFF, 0x00, 0x81, 0x51,
+	0xD1, 0xFF, 0x00, 0x09, 0x1F, 0x87, 0x3F, 0xE8, 0x3D, 0x65, 0xFF, 0x00, 0x81, 0x51, 0xD7, 0xE2,
+	0xFD, 0x14, 0x01, 0xFB, 0x41, 0xFF, 0x00, 0x09, 0x1F, 0x87, 0x3F, 0xE8, 0x3D, 0x65, 0xFF, 0x00,
+	0x81, 0x51, 0xD4, 0x96, 0xBA, 0xDE, 0x91, 0xA8, 0x4F, 0xF6, 0x7B, 0x6D, 0x56, 0xDE, 0x67, 0xFF,
+	0x00, 0x9E, 0x71, 0xCD, 0x5F, 0x8B, 0x75, 0xEF, 0x5F, 0xF0, 0x4D, 0x8F, 0xF9, 0x3B, 0x9D, 0x07,
+	0xFE, 0xC1, 0xFA, 0x87, 0xFE, 0x93, 0xBD, 0x00, 0x7E, 0x98, 0x5C, 0xCF, 0x05, 0xB4, 0x5E, 0x7D,
+	0xCC, 0xA9, 0x1A, 0x2B, 0x0F, 0xDE, 0x48, 0xDB, 0x7B, 0xFA, 0xD5, 0x55, 0xF1, 0x27, 0x86, 0xCA,
+	0xE4, 0x6B, 0xF6, 0x7F, 0xF8, 0x15, 0x1D, 0x79, 0x0F, 0xFC, 0x14, 0x47, 0xFE, 0x4C, 0xEB, 0xC6,
+	0x1F, 0xEE, 0x69, 0xFF, 0x00, 0xFA, 0x5F, 0x6F, 0x5F, 0x97, 0xB4, 0x01, 0xFB, 0x41, 0xFF, 0x00,
+	0x09, 0x1F, 0x87, 0x3F, 0xE8, 0x3D, 0x65, 0xFF, 0x00, 0x81, 0x51, 0xD1, 0xFF, 0x00, 0x09, 0x1F,
+	0x87, 0x3F, 0xE8, 0x3D, 0x65, 0xFF, 0x00, 0x81, 0x51, 0xD7, 0xE2, 0xFD, 0x14, 0x01, 0xFB, 0x41,
+	0xFF, 0x00, 0x09, 0x1F, 0x87, 0x3F, 0xE8, 0x3D, 0x65, 0xFF, 0x00, 0x81, 0x51, 0xD3, 0xA1, 0xF1,
+	0x06, 0x89, 0x73, 0x32, 0xDB, 0x43, 0xAC, 0xDA, 0xBB, 0x1F, 0xBB, 0x1A, 0x4C, 0x39, 0xFC, 0xAB,
+	0xF1, 0x76, 0xBD, 0x13, 0xF6, 0x4A, 0xFF, 0x00, 0x93, 0x9C, 0xF0, 0x0F, 0xFD, 0x8D, 0x56, 0x9F,
+	0xFA, 0x10, 0xA0, 0x0F, 0xD6, 0x89, 0x9A, 0x28, 0xE3, 0x66, 0x94, 0xA8, 0x45, 0xFB, 0xCC, 0xFD,
+	0x05, 0x67, 0xFF, 0x00, 0x6E, 0x78, 0x64, 0x72, 0xBA, 0xCD, 0x82, 0xFA, 0xFF, 0x00, 0xA4, 0x46,
+	0x2B, 0x23, 0xE3, 0x6F, 0xFC, 0x91, 0x8F, 0x16, 0x7F, 0xD8, 0xAF, 0xA8, 0x7F, 0xE8, 0x87, 0xAF,
+	0xC7, 0xAA, 0x56, 0xEE, 0x3E, 0x66, 0x8F, 0xD9, 0xEF, 0xED, 0xDF, 0x0B, 0xFF, 0x00, 0xD0, 0x6B,
+	0x4F, 0xFF, 0x00, 0xC0, 0x88, 0xA8, 0xFE, 0xDC, 0xF0, 0xBF, 0xFD, 0x06, 0xB4, 0xFF, 0x00, 0xFC,
+	0x08, 0x8A, 0xBF, 0x18, 0x68, 0xA6, 0x1C, 0xD2, 0xEE, 0x7E, 0xCE, 0x9D, 0x77, 0xC3, 0x03, 0xEE,
+	0xEB, 0x56, 0x1F, 0xF8, 0x13, 0x15, 0x4D, 0xA7, 0x6A, 0x5A, 0x3D, 0xEC, 0xED, 0x15, 0x86, 0xA3,
+	0x6F, 0x2C, 0x98, 0xFF, 0x00, 0x96, 0x73, 0x06, 0x20, 0x7E, 0x15, 0xF8, 0xB9, 0x5F, 0x49, 0x7F,
+	0xC1, 0x2B, 0x7F, 0xE4, 0xE6, 0xA7, 0xFF, 0x00, 0xB1, 0x5A, 0xFB, 0xFF, 0x00, 0x46, 0xDB, 0xD1,
+	0xCB, 0x10, 0xB9, 0xFA, 0x2F, 0x73, 0x3D, 0xBD, 0xAC, 0x3E, 0x75, 0xDC, 0xF1, 0x47, 0x1F, 0x73,
+	0x23, 0x6D, 0xAA, 0x83, 0xC4, 0x3E, 0x19, 0x23, 0x70, 0xD6, 0xEC, 0x7F, 0xF0, 0x2A, 0x3F, 0xEB,
+	0x5E, 0x2D, 0xFF, 0x00, 0x05, 0x2A, 0xFF, 0x00, 0x93, 0x4A, 0xD7, 0xBF, 0xEB, 0xF6, 0xC7, 0xFF,
+	0x00, 0x4A, 0x16, 0xBF, 0x32, 0xAA, 0x65, 0x4E, 0x9C, 0x9D, 0xE4, 0xAE, 0x24, 0xCF, 0xD9, 0xEF,
+	0xF8, 0x48, 0x3C, 0x37, 0xFF, 0x00, 0x41, 0xDB, 0x1F, 0xFC, 0x09, 0x8E, 0x8F, 0xF8, 0x48, 0x3C,
+	0x37, 0xFF, 0x00, 0x41, 0xDB, 0x1F, 0xFC, 0x08, 0x8A, 0xBF, 0x18, 0x68, 0xA9, 0xF6, 0x34, 0xBF,
+	0x95, 0x7D, 0xC8, 0x7C, 0xD2, 0x3F, 0x67, 0x7F, 0xB7, 0xFC, 0x37, 0xFF, 0x00, 0x41, 0xCB, 0x11,
+	0xCF, 0xFC, 0xFC, 0x47, 0xCD, 0x59, 0xD3, 0xF5, 0x0D, 0x32, 0xF9, 0x58, 0x69, 0x97, 0xB0, 0x4D,
+	0xB4, 0xFC, 0xC6, 0x19, 0x83, 0x60, 0xFE, 0x15, 0xF8, 0xB3, 0x5F, 0x71, 0xFF, 0x00, 0xC1, 0x20,
+	0xFF, 0x00, 0xE4, 0x5B, 0xF1, 0xD7, 0xFD, 0x7F, 0xD8, 0xFF, 0x00, 0xE8, 0xAB, 0x8A, 0x23, 0x4A,
+	0x9C, 0x65, 0x78, 0xA1, 0x6B, 0xA9, 0xF6, 0x25, 0xDE, 0xA5, 0xA7, 0xE9, 0xCB, 0x8D, 0x42, 0xFA,
+	0x38, 0x8B, 0x74, 0x69, 0x24, 0xDB, 0x50, 0x0F, 0x11, 0xF8, 0x73, 0x1F, 0xF2, 0x1E, 0xB2, 0xFF,
+	0x00, 0xC0, 0xA8, 0xEB, 0xE4, 0x3F, 0xF8, 0x2C, 0x07, 0xFC, 0x80, 0x3C, 0x0B, 0xFF, 0x00, 0x5F,
+	0xB7, 0xDF, 0xFA, 0x04, 0x75, 0xF0, 0xDD, 0x68, 0x07, 0xED, 0x07, 0xFC, 0x24, 0x7E, 0x1C, 0xFF,
+	0x00, 0xA0, 0xF5, 0x97, 0xFE, 0x05, 0x47, 0x47, 0xFC, 0x24, 0x7E, 0x1C, 0xFF, 0x00, 0xA0, 0xF5,
+	0x97, 0xFE, 0x05, 0x47, 0x5F, 0x8B, 0xF4, 0x50, 0x07, 0xED, 0x07, 0xFC, 0x24, 0x7E, 0x1C, 0xFF,
+	0x00, 0xA0, 0xF5, 0x97, 0xFE, 0x05, 0x47, 0x56, 0xAD, 0xAF, 0x2D, 0x6F, 0x60, 0xF3, 0xED, 0x2E,
+	0x22, 0x99, 0x77, 0x63, 0x7C, 0x64, 0x1F, 0xD4, 0x57, 0xE2, 0xAD, 0x7E, 0x9A, 0x7F, 0xC1, 0x35,
+	0x7F, 0xE4, 0xD1, 0xF4, 0x3F, 0xFA, 0xFE, 0xBF, 0xFF, 0x00, 0xD2, 0x96, 0xA0, 0x0F, 0x70, 0xBA,
+	0xD6, 0x74, 0x5B, 0x39, 0x3E, 0xCD, 0x7D, 0xAC, 0x5B, 0xC2, 0xC3, 0xF8, 0x66, 0xB8, 0x45, 0xCD,
+	0x46, 0x7C, 0x47, 0xE1, 0xC3, 0xCF, 0xF6, 0xF5, 0x8F, 0xE1, 0x75, 0x1D, 0x7E, 0x78, 0xFF, 0x00,
+	0xC1, 0x55, 0xFF, 0x00, 0xE4, 0xE5, 0xA2, 0xFF, 0x00, 0xB1, 0x56, 0xD7, 0xFF, 0x00, 0x46, 0x4D,
+	0x5F, 0x36, 0x9E, 0xB4, 0x01, 0xFB, 0x41, 0xFF, 0x00, 0x09, 0x1F, 0x87, 0x3F, 0xE8, 0x3D, 0x65,
+	0xFF, 0x00, 0x81, 0x51, 0xD1, 0xFF, 0x00, 0x09, 0x1F, 0x87, 0x3F, 0xE8, 0x3D, 0x65, 0xFF, 0x00,
+	0x81, 0x51, 0xD7, 0xE2, 0xFD, 0x14, 0x01, 0xFB, 0x46, 0x3C, 0x47, 0xE1, 0xBC, 0x7F, 0xC8, 0x7E,
+	0xC7, 0xFF, 0x00, 0x02, 0x92, 0xAD, 0xC7, 0x24, 0x73, 0x46, 0xB3, 0x43, 0x22, 0xB2, 0x32, 0xE5,
+	0x59, 0x4E, 0x43, 0x0E, 0xC4, 0x57, 0xE2, 0x7B, 0xFF, 0x00, 0x17, 0xFB, 0xDF, 0xFB, 0x2A, 0xD7,
+	0xEC, 0x57, 0xC0, 0xFF, 0x00, 0xF9, 0x22, 0xBE, 0x0F, 0xFF, 0x00, 0xB1, 0x5F, 0x4F, 0xFF, 0x00,
+	0xD2, 0x68, 0xE8, 0x03, 0x6E, 0xE7, 0x5C, 0xD1, 0x6D, 0xDD, 0xA2, 0xB8, 0xD6, 0xED, 0x51, 0x95,
+	0xB0, 0xCB, 0x25, 0xCA, 0x02, 0xBE, 0xD5, 0x14, 0xBE, 0x22, 0xF0, 0xDB, 0xA6, 0xD7, 0xD7, 0xEC,
+	0x4A, 0xF4, 0xDB, 0xF6, 0xA4, 0xAF, 0xCB, 0x3F, 0xDB, 0x4F, 0xFE, 0x4E, 0xBB, 0xC6, 0xDF, 0xF6,
+	0x1C, 0x3F, 0xFA, 0x0A, 0xD7, 0x96, 0x27, 0xDC, 0x1F, 0x4A, 0x99, 0xC2, 0x35, 0x22, 0xE3, 0x2D,
+	0x53, 0xEF, 0xFE, 0x5B, 0x07, 0x5B, 0x9F, 0xAD, 0xBE, 0x2F, 0xF0, 0x17, 0x80, 0xF5, 0xF7, 0x7B,
+	0xAD, 0x2B, 0x5F, 0xB2, 0xB1, 0xBC, 0x62, 0x4B, 0x18, 0xEE, 0x10, 0x89, 0x0F, 0x7C, 0x8F, 0xEB,
+	0x5E, 0x6F, 0xAD, 0x68, 0x57, 0xDA, 0x05, 0xD8, 0x86, 0x59, 0x63, 0x99, 0x48, 0xF9, 0x64, 0xB7,
+	0xB8, 0xDE, 0xBF, 0x5A, 0xFC, 0xDB, 0xA9, 0x2C, 0xEE, 0xEE, 0xF4, 0xDB, 0xB8, 0xF5, 0x1B, 0x0B,
+	0x89, 0x20, 0x96, 0x16, 0xDD, 0x15, 0xCC, 0x72, 0x6C, 0x91, 0x1B, 0xDA, 0xBF, 0x9C, 0x7C, 0x48,
+	0xFA, 0x35, 0xF0, 0x4F, 0x1B, 0x73, 0xE3, 0x30, 0x29, 0x61, 0x31, 0x2E, 0xFE, 0xF4, 0x57, 0xB9,
+	0x27, 0xDE, 0x50, 0x56, 0x4B, 0xCD, 0xAB, 0x3E, 0xE9, 0x9F, 0x41, 0x97, 0xF1, 0x06, 0x2F, 0x05,
+	0xEE, 0x4D, 0xF3, 0x47, 0xCF, 0x7F, 0xBC, 0xFD, 0x14, 0x1F, 0x5F, 0xCA, 0x8A, 0xF9, 0x6F, 0xE0,
+	0x97, 0xED, 0x73, 0xE3, 0xDB, 0x4D, 0x63, 0x4F, 0xF0, 0x6F, 0x8C, 0xA3, 0x5D, 0x6E, 0xDE, 0xF6,
+	0xEA, 0x2B, 0x7F, 0xB5, 0x4E, 0x71, 0x71, 0x09, 0x6C, 0x05, 0x24, 0xF7, 0x1E, 0xF5, 0xF5, 0xE7,
+	0x89, 0x7C, 0x0D, 0xE2, 0x5F, 0x0C, 0x48, 0xC7, 0x52, 0xB1, 0x6F, 0x2F, 0x3F, 0x2D, 0xCA, 0x37,
+	0xCA, 0x7E, 0xB5, 0xFC, 0x19, 0xC7, 0x9E, 0x05, 0x71, 0xFF, 0x00, 0x00, 0xD4, 0x94, 0xF1, 0x78,
+	0x77, 0x52, 0x82, 0xDA, 0xAD, 0x34, 0xE5, 0x0F, 0x9D, 0xB5, 0x8F, 0xCD, 0x23, 0xED, 0x30, 0x39,
+	0xDE, 0x07, 0x1A, 0xAD, 0x19, 0x59, 0xF6, 0x7B, 0x98, 0xF4, 0x51, 0xF3, 0x63, 0x77, 0xFE, 0x83,
+	0x40, 0x25, 0x86, 0x4F, 0x15, 0xF8, 0xE3, 0x8B, 0x8E, 0xE7, 0xAF, 0xE6, 0x14, 0x51, 0x45, 0x48,
+	0xC2, 0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0xBF, 0x0E, 0x3F,
+	0xE0, 0xA7, 0x5F, 0xF2, 0x7D, 0xBE, 0x3E, 0xFF, 0x00, 0xB0, 0x9D, 0xB7, 0xFE, 0x92, 0x43, 0x5F,
+	0xB8, 0xF5, 0xF8, 0x71, 0xFF, 0x00, 0x05, 0x3A, 0xFF, 0x00, 0x93, 0xED, 0xF1, 0xF7, 0xFD, 0x84,
+	0xED, 0xBF, 0xF4, 0x92, 0x1A, 0xFE, 0x98, 0xFA, 0x31, 0xFF, 0x00, 0xC9, 0x57, 0x8B, 0xFF, 0x00,
+	0xAF, 0x4B, 0xFF, 0x00, 0x4A, 0x47, 0xF4, 0x07, 0xD1, 0xD7, 0xFE, 0x4B, 0x0A, 0xDF, 0xF5, 0xE9,
+	0xFE, 0x68, 0xF0, 0x23, 0xD6, 0x8A, 0x0F, 0x5A, 0x2B, 0xFB, 0x70, 0xFE, 0xD8, 0x0A, 0x28, 0xA2,
+	0x80, 0x3B, 0xAF, 0xD9, 0x9F, 0xFE, 0x4E, 0x33, 0xE1, 0xEF, 0xFD, 0x8E, 0x9A, 0x5F, 0xFE, 0x96,
+	0x45, 0x5F, 0xD0, 0x44, 0x5F, 0xEA, 0xD7, 0xE9, 0x5F, 0xCF, 0xBF, 0xEC, 0xCF, 0xFF, 0x00, 0x27,
+	0x19, 0xF0, 0xF7, 0xFE, 0xC7, 0x4D, 0x2F, 0xFF, 0x00, 0x4B, 0x22, 0xAF, 0xE8, 0x22, 0x2F, 0xF5,
+	0x6B, 0xF4, 0xAF, 0xE3, 0x5F, 0xA5, 0x0F, 0xFC, 0x8D, 0x32, 0xEF, 0xF0, 0x4F, 0xFF, 0x00, 0x4A,
+	0x47, 0xF1, 0xFF, 0x00, 0xD2, 0x57, 0xFE, 0x47, 0x18, 0x0F, 0xFA, 0xF7, 0x2F, 0xFD, 0x29, 0x0E,
+	0xA2, 0x8A, 0x2B, 0xF9, 0x54, 0xFE, 0x67, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0x38, 0xEC, 0x28, 0xE3, 0x15, 0x5C, 0xAC, 0x02, 0x8A, 0x06, 0x08, 0xE6, 0x8C, 0x9C, 0xE4,
+	0xD1, 0xCB, 0xD0, 0x3D, 0x42, 0x8A, 0xD1, 0xD0, 0x3C, 0x2F, 0xAF, 0xF8, 0x92, 0x6D, 0xBA, 0x4E,
+	0x9D, 0x24, 0x8B, 0xBF, 0xF7, 0x93, 0x67, 0x6A, 0xA8, 0x03, 0xB9, 0xAF, 0x98, 0x7E, 0x3A, 0xFE,
+	0xD7, 0xDE, 0x2A, 0xD0, 0x3C, 0x49, 0xAB, 0x7C, 0x3F, 0xF0, 0x36, 0x94, 0x96, 0x33, 0x69, 0xB7,
+	0xD3, 0xD8, 0xDC, 0xEA, 0x97, 0x1F, 0xBC, 0x62, 0xF1, 0x39, 0x8C, 0x98, 0xD3, 0xB0, 0xCA, 0xF0,
+	0xDE, 0x95, 0xFA, 0xA7, 0x02, 0xF8, 0x2F, 0xC7, 0xDE, 0x20, 0x56, 0x8F, 0xF6, 0x7E, 0x15, 0xC6,
+	0x93, 0xDE, 0xA4, 0xD3, 0x8C, 0x17, 0xCE, 0xDA, 0xFA, 0x24, 0xD9, 0xE5, 0xE3, 0x33, 0x8C, 0x0E,
+	0x05, 0x7E, 0xF2, 0x5A, 0xF6, 0x5A, 0xB3, 0xE9, 0x5D, 0x33, 0x4C, 0xB9, 0xD6, 0x2E, 0xD6, 0xD6,
+	0xD1, 0x15, 0x5B, 0xFE, 0x7A, 0x49, 0x26, 0xD5, 0x1F, 0x5A, 0xF4, 0x1F, 0x08, 0xFC, 0x37, 0xF0,
+	0x86, 0x9C, 0x56, 0xF7, 0xC4, 0xDA, 0xF5, 0x95, 0xC4, 0xEB, 0xCF, 0xD9, 0xC5, 0xD2, 0x04, 0x53,
+	0xF4, 0xEF, 0xF5, 0xAF, 0xCA, 0xAD, 0x7B, 0x5F, 0xD7, 0xBC, 0x55, 0xA8, 0xB6, 0xB1, 0xE2, 0x5D,
+	0x56, 0xE2, 0xFA, 0xF2, 0x62, 0x77, 0x5D, 0x5D, 0xCF, 0xB8, 0x8F, 0x65, 0xF6, 0xAA, 0x7B, 0xB7,
+	0x7C, 0xC0, 0xF5, 0xE7, 0x9A, 0xFE, 0xF0, 0xF0, 0xDF, 0xE8, 0xBD, 0xC2, 0x5C, 0x23, 0xC9, 0x8D,
+	0xCE, 0x3F, 0xDA, 0xF1, 0x0A, 0xD6, 0x52, 0x4B, 0xD9, 0xC5, 0xF9, 0x47, 0x5B, 0xFA, 0xCA, 0xFD,
+	0xEC, 0x8F, 0x8B, 0xCC, 0xB8, 0x8B, 0x15, 0x8B, 0xF7, 0x29, 0x7B, 0xB1, 0xFC, 0x7E, 0xF3, 0xF6,
+	0x72, 0xDB, 0x5B, 0xF0, 0xBD, 0xBC, 0x0B, 0x6F, 0x06, 0xB7, 0x62, 0x88, 0x8A, 0x02, 0xAA, 0xDC,
+	0x46, 0x00, 0x1E, 0x95, 0x34, 0x1E, 0x20, 0xD1, 0x2E, 0x66, 0x5B, 0x58, 0x75, 0x8B, 0x57, 0x63,
+	0xF7, 0x52, 0x39, 0x87, 0x3F, 0x95, 0x7E, 0x2E, 0xD7, 0xA2, 0x7E, 0xC9, 0x5F, 0xF2, 0x73, 0x9E,
+	0x01, 0xFF, 0x00, 0xB1, 0xAA, 0xD3, 0xFF, 0x00, 0x42, 0x15, 0xFD, 0x3D, 0x4E, 0x95, 0x3A, 0x34,
+	0xD5, 0x38, 0x2B, 0x45, 0x6C, 0x96, 0x96, 0xFB, 0x8F, 0x9C, 0x3F, 0x5A, 0x25, 0x91, 0x22, 0x8C,
+	0xB4, 0xAC, 0xAA, 0xA9, 0xC9, 0x67, 0xE8, 0x2A, 0x99, 0xF1, 0x27, 0x87, 0x49, 0xC9, 0xD7, 0x6C,
+	0xFF, 0x00, 0x1B, 0x98, 0xC7, 0xF3, 0xAC, 0x4F, 0x8D, 0xBF, 0xF2, 0x46, 0x3C, 0x59, 0xFF, 0x00,
+	0x62, 0xBE, 0xA1, 0xFF, 0x00, 0xA2, 0x1E, 0xBF, 0x1E, 0xAB, 0x41, 0x1F, 0xB4, 0x1F, 0xF0, 0x91,
+	0xF8, 0x73, 0xFE, 0x83, 0xD6, 0x5F, 0xF8, 0x15, 0x1D, 0x1F, 0xF0, 0x91, 0xF8, 0x73, 0xFE, 0x83,
+	0xD6, 0x5F, 0xF8, 0x15, 0x1D, 0x7E, 0x2F, 0xD1, 0x40, 0x1F, 0xB4, 0x1F, 0xF0, 0x91, 0xF8, 0x73,
+	0xFE, 0x83, 0xD6, 0x5F, 0xF8, 0x15, 0x1D, 0x4D, 0x63, 0xAC, 0x69, 0x37, 0xD2, 0xB4, 0x16, 0x3A,
+	0x9D, 0xBC, 0xCC, 0x06, 0x71, 0x1D, 0xC0, 0x6F, 0xE5, 0x5F, 0x8B, 0x35, 0xF4, 0x97, 0xFC, 0x12,
+	0xB7, 0xFE, 0x4E, 0x6A, 0x7F, 0xFB, 0x15, 0xAF, 0xBF, 0xF4, 0x6D, 0xBD, 0x00, 0x7E, 0x8D, 0x5C,
+	0xDD, 0xC1, 0x69, 0x0F, 0x9F, 0x73, 0x3C, 0x71, 0x27, 0x76, 0x92, 0x4D, 0x95, 0x4C, 0x78, 0x93,
+	0xC3, 0x8C, 0x37, 0x0D, 0x7A, 0xCB, 0x9F, 0xFA, 0x7A, 0x8F, 0xFA, 0xD7, 0x8A, 0x7F, 0xC1, 0x4A,
+	0xBF, 0xE4, 0xD2, 0xB5, 0xEF, 0xFA, 0xFD, 0xB1, 0xFF, 0x00, 0xD2, 0x85, 0xAF, 0xCC, 0xAA, 0x00,
+	0xFD, 0xA0, 0xFF, 0x00, 0x84, 0x8F, 0xC3, 0x9F, 0xF4, 0x1E, 0xB2, 0xFF, 0x00, 0xC0, 0xA8, 0xE8,
+	0xFF, 0x00, 0x84, 0x8F, 0xC3, 0x9F, 0xF4, 0x1E, 0xB2, 0xFF, 0x00, 0xC0, 0xA8, 0xEB, 0xF1, 0x7E,
+	0x8A, 0x00, 0xFD, 0xA0, 0xFF, 0x00, 0x84, 0x8F, 0xC3, 0x9F, 0xF4, 0x1E, 0xB2, 0xFF, 0x00, 0xC0,
+	0xA8, 0xEA, 0xC5, 0x86, 0xA7, 0xA7, 0x6A, 0x01, 0xBF, 0xB3, 0xAF, 0xE1, 0x9F, 0x6F, 0x0C, 0x63,
+	0x9C, 0x36, 0x3F, 0x2A, 0xFC, 0x57, 0xAF, 0xB8, 0xFF, 0x00, 0xE0, 0x90, 0x7F, 0xF2, 0x2D, 0xF8,
+	0xEB, 0xFE, 0xBF, 0xEC, 0x7F, 0xF4, 0x55, 0xC5, 0x00, 0x7D, 0x83, 0x7D, 0x7D, 0xA7, 0xD8, 0x0C,
+	0x6A, 0x37, 0xB0, 0xC7, 0xBB, 0x95, 0x32, 0x36, 0xDC, 0xD4, 0x23, 0xC4, 0x1E, 0x1A, 0x2B, 0xC6,
+	0xB9, 0x63, 0xFF, 0x00, 0x81, 0x51, 0xD7, 0xC8, 0xBF, 0xF0, 0x58, 0x0F, 0xF9, 0x00, 0x78, 0x17,
+	0xFE, 0xBF, 0x6F, 0xBF, 0xF4, 0x08, 0xEB, 0xE1, 0xBA, 0xCE, 0x54, 0xA9, 0xCB, 0x59, 0x24, 0xFE,
+	0x43, 0xB9, 0xFB, 0x3D, 0xFF, 0x00, 0x09, 0x07, 0x86, 0xFF, 0x00, 0xE8, 0x3B, 0x63, 0xFF, 0x00,
+	0x81, 0x11, 0xD1, 0xFF, 0x00, 0x09, 0x07, 0x86, 0xFF, 0x00, 0xE8, 0x3B, 0x63, 0xFF, 0x00, 0x81,
+	0x11, 0x57, 0xE3, 0x0D, 0x14, 0x7B, 0x1A, 0x5F, 0xCA, 0xBE, 0xE4, 0x1C, 0xD2, 0x3F, 0x67, 0xBF,
+	0xB7, 0xBC, 0x33, 0x9C, 0x1D, 0x72, 0xC7, 0xFF, 0x00, 0x02, 0x23, 0xAB, 0x56, 0x97, 0x36, 0x97,
+	0x70, 0x79, 0xD6, 0x57, 0x11, 0x48, 0x9B, 0xB1, 0xBA, 0x22, 0x31, 0xFA, 0x57, 0xE2, 0xBD, 0x7E,
+	0x9A, 0x7F, 0xC1, 0x35, 0x7F, 0xE4, 0xD1, 0xF4, 0x3F, 0xFA, 0xFE, 0xBF, 0xFF, 0x00, 0xD2, 0x96,
+	0xA7, 0x1A, 0x74, 0xE2, 0xEE, 0x92, 0x11, 0xEE, 0x17, 0x5A, 0xC6, 0x8B, 0x67, 0x27, 0xD9, 0xAF,
+	0xB5, 0x8B, 0x78, 0x58, 0x7F, 0x0C, 0xB7, 0x08, 0xB9, 0xFC, 0xEA, 0x33, 0xE2, 0x3F, 0x0E, 0x1E,
+	0x7F, 0xB7, 0xAC, 0x7F, 0x0B, 0xB8, 0xEB, 0xF3, 0xC7, 0xFE, 0x0A, 0xAF, 0xFF, 0x00, 0x27, 0x2D,
+	0x17, 0xFD, 0x8A, 0xB6, 0xBF, 0xFA, 0x32, 0x6A, 0xF9, 0xB4, 0xF5, 0xAB, 0x03, 0xF6, 0x83, 0xFE,
+	0x12, 0x2F, 0x0E, 0x7F, 0xD0, 0x7A, 0xCF, 0xFF, 0x00, 0x02, 0xA3, 0xA3, 0xFE, 0x12, 0x2F, 0x0E,
+	0x7F, 0xD0, 0x7A, 0xCF, 0xFF, 0x00, 0x02, 0xA3, 0xAF, 0xC5, 0xFA, 0x28, 0x0D, 0x4F, 0xDA, 0x21,
+	0xE2, 0x1F, 0x0E, 0x63, 0xFE, 0x46, 0x0B, 0x1F, 0xFC, 0x0A, 0x4F, 0xF1, 0xAB, 0x91, 0x49, 0x1C,
+	0xD1, 0xAC, 0xB0, 0xC8, 0xAE, 0x8C, 0xA0, 0xAB, 0x29, 0xC8, 0x61, 0xEA, 0x2B, 0xF1, 0x3D, 0xFF,
+	0x00, 0x8B, 0xFD, 0xEF, 0xFD, 0x95, 0x6B, 0xF6, 0x2B, 0xE0, 0x7F, 0xFC, 0x91, 0x5F, 0x07, 0xFF,
+	0x00, 0xD8, 0xAF, 0xA7, 0xFF, 0x00, 0xE9, 0x34, 0x74, 0x01, 0xB9, 0x71, 0xAE, 0xE8, 0x96, 0xF2,
+	0x18, 0xEE, 0x35, 0xAB, 0x35, 0x65, 0x38, 0x65, 0x92, 0xE1, 0x01, 0x07, 0xD2, 0xA3, 0xFF, 0x00,
+	0x84, 0x8F, 0xC3, 0x67, 0x91, 0xAF, 0x58, 0xFF, 0x00, 0xE0, 0x54, 0x75, 0xF9, 0x63, 0xFB, 0x69,
+	0xFF, 0x00, 0xC9, 0xD7, 0x78, 0xDB, 0xFE, 0xC3, 0x87, 0xFF, 0x00, 0x41, 0x5A, 0xF2, 0xC4, 0xFB,
+	0x83, 0xE9, 0x40, 0x1F, 0xB4, 0x3F, 0xF0, 0x91, 0xF8, 0x73, 0xFE, 0x83, 0xD6, 0x5F, 0xF8, 0x15,
+	0x1D, 0x1F, 0xF0, 0x91, 0xF8, 0x73, 0xFE, 0x83, 0xD6, 0x5F, 0xF8, 0x15, 0x1D, 0x7E, 0x2F, 0xD1,
+	0x40, 0x1F, 0xB4, 0x1F, 0xF0, 0x91, 0xF8, 0x73, 0xFE, 0x83, 0xD6, 0x5F, 0xF8, 0x15, 0x1D, 0x47,
+	0xA5, 0x6A, 0x16, 0x1A, 0x86, 0xBF, 0x7C, 0xD6, 0x37, 0x91, 0x4C, 0xA2, 0xCE, 0xD5, 0x59, 0xA3,
+	0x6D, 0xC0, 0x7C, 0xF3, 0x71, 0xC5, 0x7E, 0x31, 0xD7, 0xDE, 0x9F, 0xF0, 0x48, 0x5C, 0xFF, 0x00,
+	0xC2, 0xB5, 0xF1, 0x86, 0x0F, 0xFC, 0xC7, 0x60, 0xFF, 0x00, 0xD1, 0x34, 0x01, 0xF5, 0x3C, 0x7A,
+	0xB6, 0x95, 0x63, 0x7B, 0x77, 0x1D, 0xFE, 0xA5, 0x6F, 0x03, 0x1B, 0x85, 0xC2, 0xC9, 0x70, 0x17,
+	0x3F, 0xBB, 0x5E, 0xC6, 0xA5, 0xFF, 0x00, 0x84, 0x8F, 0xC3, 0x9F, 0xF4, 0x1E, 0xB2, 0xFF, 0x00,
+	0xC0, 0xA8, 0xEB, 0xF3, 0xCB, 0xFE, 0x0A, 0xA3, 0xFF, 0x00, 0x27, 0x33, 0x6F, 0xFF, 0x00, 0x62,
+	0xC5, 0xAF, 0xFE, 0x87, 0x2D, 0x7C, 0xD9, 0x40, 0x1F, 0xB4, 0x1F, 0xF0, 0x91, 0xF8, 0x73, 0xFE,
+	0x83, 0xD6, 0x5F, 0xF8, 0x15, 0x1D, 0x1F, 0xF0, 0x91, 0xF8, 0x73, 0xFE, 0x83, 0xD6, 0x5F, 0xF8,
+	0x15, 0x1D, 0x7E, 0x2F, 0xD1, 0x40, 0x1F, 0xB4, 0x03, 0xC4, 0x9E, 0x1D, 0x5E, 0x57, 0x5D, 0xB2,
+	0xFF, 0x00, 0xC0, 0x94, 0xFE, 0x9C, 0xD5, 0x9B, 0x1D, 0x46, 0xC3, 0x52, 0x85, 0xA4, 0xB1, 0xBE,
+	0x8A, 0x75, 0xDC, 0x03, 0x34, 0x6D, 0xB8, 0x0C, 0x9E, 0x95, 0xF8, 0xAD, 0xDB, 0xF0, 0xAF, 0xBA,
+	0x3F, 0xE0, 0x90, 0x19, 0xFF, 0x00, 0x84, 0x73, 0xC7, 0xB8, 0x3F, 0xF3, 0x11, 0xB0, 0xFF, 0x00,
+	0xD1, 0x72, 0xD0, 0x07, 0xD6, 0x71, 0xEA, 0xDA, 0x55, 0x8D, 0xED, 0xDC, 0x77, 0xFA, 0x95, 0xBC,
+	0x0C, 0x6E, 0x17, 0x0B, 0x25, 0xC0, 0x5C, 0xFE, 0xED, 0x7B, 0x1A, 0x97, 0xFE, 0x12, 0x3F, 0x0E,
+	0x7F, 0xD0, 0x7A, 0xCB, 0xFF, 0x00, 0x02, 0xA3, 0xAF, 0xCF, 0x2F, 0xF8, 0x2A, 0x8F, 0xFC, 0x9C,
+	0xCD, 0xBF, 0xFD, 0x8B, 0x16, 0xBF, 0xFA, 0x1C, 0xB5, 0xF3, 0x65, 0x00, 0x7E, 0xD0, 0x7F, 0xC2,
+	0x47, 0xE1, 0xCF, 0xFA, 0x0F, 0x59, 0x7F, 0xE0, 0x54, 0x74, 0x7F, 0xC2, 0x47, 0xE1, 0xCF, 0xFA,
+	0x0F, 0x59, 0x7F, 0xE0, 0x54, 0x75, 0xF8, 0xBF, 0x45, 0x00, 0x7E, 0xD0, 0x0F, 0x12, 0x78, 0x75,
+	0x79, 0x5D, 0x76, 0xCB, 0xFF, 0x00, 0x02, 0x53, 0xFA, 0x73, 0x56, 0x2C, 0xB5, 0x1D, 0x3F, 0x52,
+	0x46, 0x96, 0xCA, 0xFE, 0x39, 0x82, 0xF5, 0x68, 0xE4, 0xCE, 0x2B, 0xF1, 0x5F, 0xB7, 0xE1, 0x5F,
+	0x73, 0x7F, 0xC1, 0x20, 0xFF, 0x00, 0xE4, 0x5F, 0xF1, 0xDF, 0xFD, 0x84, 0xB4, 0xFF, 0x00, 0xFD,
+	0x17, 0x2D, 0x00, 0x7D, 0x99, 0x16, 0x76, 0xF2, 0xB8, 0xE6, 0x9D, 0x4C, 0x83, 0xFD, 0x5F, 0xE3,
+	0x4F, 0xA0, 0x02, 0x83, 0xD2, 0x8A, 0x0F, 0x4A, 0x00, 0xF8, 0x53, 0xFE, 0x0A, 0xFB, 0xFF, 0x00,
+	0x23, 0x27, 0x81, 0xFF, 0x00, 0xEB, 0xCA, 0xFB, 0xFF, 0x00, 0x46, 0x47, 0x5F, 0x1B, 0x57, 0xD9,
+	0x3F, 0xF0, 0x57, 0xDF, 0xF9, 0x19, 0x3C, 0x0F, 0xFF, 0x00, 0x5E, 0x57, 0xDF, 0xFA, 0x32, 0x3A,
+	0xF8, 0xDA, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x01, 0xD6, 0xBE, 0xAE, 0xFF, 0x00, 0x82, 0x49, 0x7F,
+	0xC9, 0x67, 0xF1, 0x37, 0xFD, 0x8A, 0x6B, 0xFF, 0x00, 0xA5, 0x31, 0x57, 0xCA, 0x23, 0xAD, 0x7D,
+	0x5D, 0xFF, 0x00, 0x04, 0x92, 0xFF, 0x00, 0x92, 0xCF, 0xE2, 0x6F, 0xFB, 0x14, 0xD7, 0xFF, 0x00,
+	0x4A, 0x62, 0xA0, 0x0F, 0x5F, 0xFF, 0x00, 0x82, 0xB4, 0x7F, 0xC9, 0xBA, 0x69, 0x1F, 0xF6, 0x3B,
+	0x5B, 0xFF, 0x00, 0xE9, 0x25, 0xD5, 0x7E, 0x79, 0x57, 0xE8, 0x6F, 0xFC, 0x15, 0xA3, 0xFE, 0x4D,
+	0xD3, 0x48, 0xFF, 0x00, 0xB1, 0xDA, 0xDF, 0xFF, 0x00, 0x49, 0x2E, 0xAB, 0xF3, 0xCA, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0xF7, 0xAF, 0xF8, 0x26, 0xC7, 0xFC, 0x9D, 0xCE, 0x83, 0xFF, 0x00, 0x60,
+	0xFD, 0x43, 0xFF, 0x00, 0x49, 0xDE, 0xBC, 0x16, 0xBD, 0xEB, 0xFE, 0x09, 0xB1, 0xFF, 0x00, 0x27,
+	0x73, 0xA0, 0xFF, 0x00, 0xD8, 0x3F, 0x50, 0xFF, 0x00, 0xD2, 0x77, 0xA0, 0x0F, 0xB2, 0x3F, 0xE0,
+	0xA2, 0x3F, 0xF2, 0x67, 0x5E, 0x30, 0xFF, 0x00, 0x73, 0x4F, 0xFF, 0x00, 0xD2, 0xFB, 0x7A, 0xFC,
+	0xBD, 0xAF, 0xD4, 0x2F, 0xF8, 0x28, 0x8F, 0xFC, 0x99, 0xD7, 0x8C, 0x3F, 0xDC, 0xD3, 0xFF, 0x00,
+	0xF4, 0xBE, 0xDE, 0xBF, 0x2F, 0x68, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xAF, 0x44, 0xFD, 0x92, 0xBF,
+	0xE4, 0xE7, 0x3C, 0x03, 0xFF, 0x00, 0x63, 0x55, 0xA7, 0xFE, 0x84, 0x2B, 0xCE, 0xEB, 0xD1, 0x3F,
+	0x64, 0xAF, 0xF9, 0x39, 0xCF, 0x00, 0xFF, 0x00, 0xD8, 0xD5, 0x69, 0xFF, 0x00, 0xA1, 0x0A, 0x00,
+	0xFD, 0x41, 0xF8, 0xDB, 0xFF, 0x00, 0x24, 0x63, 0xC5, 0x9F, 0xF6, 0x2B, 0xEA, 0x1F, 0xFA, 0x21,
+	0xEB, 0xF1, 0xEA, 0xBF, 0x61, 0x7E, 0x36, 0xFF, 0x00, 0xC9, 0x18, 0xF1, 0x67, 0xFD, 0x8A, 0xFA,
+	0x87, 0xFE, 0x88, 0x7A, 0xFC, 0x7A, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0xBE, 0x92, 0xFF, 0x00,
+	0x82, 0x56, 0xFF, 0x00, 0xC9, 0xCD, 0x4F, 0xFF, 0x00, 0x62, 0xB5, 0xF7, 0xFE, 0x8D, 0xB7, 0xAF,
+	0x9B, 0x6B, 0xE9, 0x2F, 0xF8, 0x25, 0x6F, 0xFC, 0x9C, 0xD4, 0xFF, 0x00, 0xF6, 0x2B, 0x5F, 0x7F,
+	0xE8, 0xDB, 0x7A, 0x00, 0xFA, 0x8F, 0xFE, 0x0A, 0x55, 0xFF, 0x00, 0x26, 0x95, 0xAF, 0x7F, 0xD7,
+	0xED, 0x8F, 0xFE, 0x94, 0x2D, 0x7E, 0x65, 0x57, 0xE9, 0xAF, 0xFC, 0x14, 0xAB, 0xFE, 0x4D, 0x2B,
+	0x5E, 0xFF, 0x00, 0xAF, 0xDB, 0x1F, 0xFD, 0x28, 0x5A, 0xFC, 0xCA, 0xA0, 0x02, 0x8A, 0x28, 0xA0,
+	0x02, 0xBE, 0xE3, 0xFF, 0x00, 0x82, 0x41, 0xFF, 0x00, 0xC8, 0xB7, 0xE3, 0xAF, 0xFA, 0xFF, 0x00,
+	0xB1, 0xFF, 0x00, 0xD1, 0x57, 0x15, 0xF0, 0xE5, 0x7D, 0xC7, 0xFF, 0x00, 0x04, 0x83, 0xFF, 0x00,
+	0x91, 0x6F, 0xC7, 0x5F, 0xF5, 0xFF, 0x00, 0x63, 0xFF, 0x00, 0xA2, 0xAE, 0x28, 0x01, 0x7F, 0xE0,
+	0xB0, 0x1F, 0xF2, 0x00, 0xF0, 0x2F, 0xFD, 0x7E, 0xDF, 0x7F, 0xE8, 0x11, 0xD7, 0xC3, 0x75, 0xF7,
+	0x27, 0xFC, 0x16, 0x03, 0xFE, 0x40, 0x1E, 0x05, 0xFF, 0x00, 0xAF, 0xDB, 0xEF, 0xFD, 0x02, 0x3A,
+	0xF8, 0x6E, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0xFD, 0x34, 0xFF, 0x00, 0x82, 0x6A, 0xFF, 0x00,
+	0xC9, 0xA3, 0xE8, 0x7F, 0xF5, 0xFD, 0x7F, 0xFF, 0x00, 0xA5, 0x2D, 0x5F, 0x99, 0x75, 0xFA, 0x69,
+	0xFF, 0x00, 0x04, 0xD5, 0xFF, 0x00, 0x93, 0x47, 0xD0, 0xFF, 0x00, 0xEB, 0xFA, 0xFF, 0x00, 0xFF,
+	0x00, 0x4A, 0x5A, 0x80, 0x3E, 0x5D, 0xFF, 0x00, 0x82, 0xAB, 0xFF, 0x00, 0xC9, 0xCB, 0x45, 0xFF,
+	0x00, 0x62, 0xAD, 0xAF, 0xFE, 0x8C, 0x9A, 0xBE, 0x6D, 0x3D, 0x6B, 0xE9, 0x2F, 0xF8, 0x2A, 0xBF,
+	0xFC, 0x9C, 0xB4, 0x5F, 0xF6, 0x2A, 0xDA, 0xFF, 0x00, 0xE8, 0xC9, 0xAB, 0xE6, 0xD3, 0xD6, 0x80,
+	0x0A, 0x28, 0xA2, 0x80, 0x1A, 0xFF, 0x00, 0xC5, 0xFE, 0xF7, 0xFE, 0xCA, 0xB5, 0xFB, 0x15, 0xF0,
+	0x3F, 0xFE, 0x48, 0xAF, 0x83, 0xFF, 0x00, 0xEC, 0x57, 0xD3, 0xFF, 0x00, 0xF4, 0x9A, 0x3A, 0xFC,
+	0x75, 0x7F, 0xE2, 0xFF, 0x00, 0x7B, 0xFF, 0x00, 0x65, 0x5A, 0xFD, 0x8A, 0xF8, 0x1F, 0xFF, 0x00,
+	0x24, 0x57, 0xC1, 0xFF, 0x00, 0xF6, 0x2B, 0xE9, 0xFF, 0x00, 0xFA, 0x4D, 0x1D, 0x00, 0x7E, 0x64,
+	0xFE, 0xDA, 0x7F, 0xF2, 0x75, 0xDE, 0x36, 0xFF, 0x00, 0xB0, 0xE1, 0xFF, 0x00, 0xD0, 0x56, 0xBC,
+	0xB1, 0x3E, 0xE0, 0xFA, 0x57, 0xA9, 0xFE, 0xDA, 0x7F, 0xF2, 0x75, 0xDE, 0x36, 0xFF, 0x00, 0xB0,
+	0xE1, 0xFF, 0x00, 0xD0, 0x56, 0xBC, 0xB1, 0x3E, 0xE0, 0xFA, 0x50, 0x02, 0xD1, 0x45, 0x14, 0x6B,
+	0xB2, 0x03, 0x73, 0xE1, 0xAF, 0xFC, 0x94, 0x6F, 0x0E, 0x7F, 0xD8, 0x6A, 0xD7, 0xFF, 0x00, 0x4A,
+	0x52, 0xBF, 0x63, 0x27, 0xB7, 0x8E, 0xE1, 0x58, 0x4C, 0xA0, 0x8E, 0x9F, 0x77, 0xE6, 0x1E, 0xE3,
+	0xF1, 0xAF, 0xC7, 0x3F, 0x86, 0xBF, 0xF2, 0x51, 0xBC, 0x39, 0xFF, 0x00, 0x61, 0xAB, 0x5F, 0xFD,
+	0x29, 0x4A, 0xFD, 0x92, 0x6F, 0xB8, 0x3F, 0xCF, 0x63, 0x59, 0xD5, 0xA5, 0x4E, 0xB4, 0x5C, 0x6A,
+	0x2B, 0xA7, 0xBA, 0x7A, 0xAF, 0xB9, 0x82, 0xF7, 0x5D, 0xD6, 0x87, 0xE4, 0xEF, 0xC3, 0xCF, 0xDA,
+	0xBF, 0xE2, 0xE7, 0x80, 0xC2, 0x69, 0xD7, 0x97, 0xFF, 0x00, 0xDB, 0x16, 0x29, 0x8D, 0xD6, 0xBA,
+	0x92, 0x9D, 0xCA, 0xA3, 0xF8, 0x51, 0x81, 0x0C, 0x00, 0xED, 0x96, 0x2B, 0xFE, 0xCF, 0x6A, 0xF6,
+	0xFF, 0x00, 0x87, 0xDF, 0xB6, 0x67, 0xC2, 0xCF, 0x15, 0xAC, 0x76, 0xFE, 0x23, 0x5B, 0x8D, 0x06,
+	0xE9, 0xB0, 0x3F, 0xD2, 0x7E, 0x68, 0x77, 0x77, 0xF9, 0xD0, 0x04, 0xC7, 0xBB, 0x01, 0x5F, 0x22,
+	0x51, 0x5F, 0x89, 0x71, 0xB7, 0xD1, 0xEB, 0xC3, 0x4E, 0x34, 0x72, 0xAB, 0x53, 0x0B, 0xEC, 0x2B,
+	0x3F, 0xB7, 0x4B, 0xDC, 0x77, 0xEE, 0xE2, 0xBD, 0xC6, 0xFB, 0xDE, 0x27, 0xB1, 0x83, 0xCF, 0x33,
+	0x0C, 0x26, 0x9C, 0xDC, 0xCB, 0xB3, 0x3F, 0x44, 0x34, 0xAD, 0x5F, 0x46, 0xD7, 0xAC, 0x97, 0x53,
+	0xD1, 0xB5, 0x98, 0x2F, 0x2D, 0xDB, 0xEE, 0xDC, 0x5A, 0xDC, 0x87, 0x43, 0xF9, 0x71, 0x8F, 0xA7,
+	0x15, 0x60, 0xF0, 0x71, 0xFC, 0xAB, 0xF3, 0xE3, 0xC3, 0xFE, 0x2B, 0xF1, 0x37, 0x84, 0xEE, 0xD7,
+	0x52, 0xF0, 0xCF, 0x88, 0x6F, 0x2C, 0x26, 0x5E, 0x92, 0xD9, 0xCD, 0xB5, 0x4F, 0xB3, 0x2F, 0x73,
+	0x5E, 0xA7, 0xE0, 0xAF, 0xDB, 0x63, 0xE2, 0x9E, 0x80, 0x89, 0x07, 0x89, 0xEC, 0xEC, 0xB5, 0xB8,
+	0x46, 0x03, 0x19, 0xA3, 0x30, 0xCE, 0x7E, 0x8C, 0xA5, 0x54, 0x9F, 0xF7, 0x95, 0x8F, 0xA9, 0x35,
+	0xFC, 0xA5, 0xC5, 0xFF, 0x00, 0x43, 0xDE, 0x2E, 0xC0, 0xB7, 0x57, 0x21, 0xC4, 0xC3, 0x13, 0x05,
+	0xF6, 0x65, 0xFB, 0xB9, 0xFE, 0x37, 0x8B, 0xFB, 0xD1, 0xF4, 0xF8, 0x4E, 0x2C, 0xC3, 0x49, 0x72,
+	0xD7, 0x8B, 0x8F, 0x9A, 0xD5, 0x7D, 0xE7, 0xD6, 0x94, 0x57, 0x9A, 0xFC, 0x0D, 0xFD, 0xA5, 0x3C,
+	0x31, 0xF1, 0xC3, 0xC6, 0x56, 0x7F, 0x0F, 0x34, 0x7D, 0x0A, 0xFA, 0xCF, 0x5C, 0xD4, 0x3C, 0xC7,
+	0xB7, 0xB6, 0xB8, 0x68, 0xA4, 0x8C, 0xAC, 0x50, 0xB3, 0xB0, 0x0E, 0x00, 0xE7, 0x0A, 0xFD, 0x87,
+	0xD0, 0x57, 0xAB, 0xEA, 0x1E, 0x1C, 0xD7, 0xF4, 0x55, 0xD9, 0xAA, 0xE9, 0x33, 0x42, 0xAB, 0xC6,
+	0x5D, 0x47, 0x5F, 0xA8, 0xEB, 0xF5, 0xAF, 0xE7, 0x2E, 0x22, 0xF0, 0xC7, 0x8E, 0xB8, 0x56, 0x6D,
+	0x66, 0x78, 0x0A, 0x94, 0xD2, 0xFB, 0x5C, 0xAD, 0xC7, 0xFF, 0x00, 0x02, 0x57, 0x8F, 0xDC, 0xCF,
+	0x7B, 0x0F, 0x99, 0x60, 0xB1, 0x1A, 0x53, 0xA8, 0x9F, 0xCC, 0xA5, 0x45, 0x03, 0x18, 0xEB, 0x46,
+	0x4F, 0x42, 0x6B, 0xE1, 0xA5, 0x4E, 0x51, 0x95, 0x9A, 0xB5, 0xBB, 0x9D, 0xC9, 0xF3, 0x6C, 0x14,
+	0x50, 0x31, 0xDC, 0x51, 0x51, 0x61, 0x85, 0x7E, 0x1C, 0x7F, 0xC1, 0x4E, 0xBF, 0xE4, 0xFB, 0x7C,
+	0x7D, 0xFF, 0x00, 0x61, 0x3B, 0x6F, 0xFD, 0x24, 0x86, 0xBF, 0x72, 0x06, 0x08, 0xAF, 0xC3, 0x8F,
+	0xF8, 0x29, 0xDF, 0xFC, 0x9F, 0x7F, 0x8F, 0xF1, 0xFF, 0x00, 0x41, 0x4B, 0x7F, 0xFD, 0x24, 0x86,
+	0xBF, 0xA5, 0xFE, 0x8C, 0x7F, 0xF2, 0x55, 0x62, 0xFF, 0x00, 0xEB, 0xD2, 0xFF, 0x00, 0xD2, 0x91,
+	0xFB, 0xFF, 0x00, 0xD1, 0xD5, 0xFF, 0x00, 0xC6, 0x61, 0x5B, 0xFE, 0xBD, 0x3F, 0xCD, 0x1E, 0x02,
+	0x7A, 0xD1, 0x4A, 0xC4, 0x93, 0x48, 0x3D, 0xEB, 0xFB, 0x71, 0x6B, 0xB1, 0xFD, 0xB3, 0xE8, 0x14,
+	0x50, 0x71, 0xDA, 0x8C, 0x9A, 0x34, 0x40, 0xF4, 0x3B, 0xAF, 0xD9, 0x9F, 0xFE, 0x4E, 0x33, 0xE1,
+	0xEF, 0xFD, 0x8E, 0x9A, 0x5F, 0xFE, 0x96, 0x45, 0x5F, 0xD0, 0x44, 0x5C, 0x46, 0xB9, 0xF4, 0xAF,
+	0xE7, 0xE3, 0xF6, 0x67, 0x24, 0x7E, 0xD1, 0x5F, 0x0F, 0x8F, 0xFD, 0x4E, 0x7A, 0x5F, 0xFE, 0x96,
+	0x45, 0x5F, 0xD0, 0x3C, 0x67, 0xCC, 0x8D, 0x49, 0x1D, 0x45, 0x7F, 0x1B, 0xFD, 0x28, 0x57, 0xFC,
+	0x2A, 0x65, 0xDF, 0xE0, 0x9B, 0xFF, 0x00, 0xC9, 0x91, 0xFC, 0x7F, 0xF4, 0x96, 0xD3, 0x38, 0xCB,
+	0xDF, 0xFD, 0x3B, 0x97, 0xFE, 0x94, 0x87, 0x51, 0x46, 0x08, 0x38, 0xA3, 0x8F, 0x5A, 0xFE, 0x55,
+	0xB1, 0xFC, 0xCF, 0xB0, 0x51, 0x41, 0xF6, 0x34, 0xA4, 0x93, 0xDE, 0x88, 0xC2, 0x52, 0x76, 0x44,
+	0xDF, 0x4B, 0x89, 0x45, 0x5A, 0xD3, 0x74, 0x7D, 0x57, 0x54, 0x3E, 0x5E, 0x9B, 0xA6, 0x5C, 0x5C,
+	0x37, 0xF7, 0xA3, 0x4E, 0x95, 0xE6, 0x7F, 0x19, 0x7F, 0x69, 0x1F, 0x02, 0xFC, 0x15, 0xF1, 0x35,
+	0xD7, 0x81, 0xFC, 0x47, 0x6B, 0xA9, 0x4D, 0xAD, 0x59, 0x46, 0xA6, 0xE2, 0xC6, 0xDE, 0xDB, 0x2A,
+	0x8C, 0xF0, 0xAC, 0xB1, 0x16, 0x7F, 0xE1, 0x25, 0x4D, 0x7D, 0xA6, 0x41, 0xE1, 0xCF, 0x1A, 0x71,
+	0x45, 0x45, 0x1C, 0xAF, 0x03, 0x52, 0xAD, 0xFA, 0xC6, 0x0F, 0x97, 0xE7, 0x26, 0x92, 0x5F, 0x36,
+	0x8E, 0x4A, 0xD9, 0x86, 0x0F, 0x0E, 0xAF, 0x52, 0x69, 0x7C, 0xCF, 0x42, 0x04, 0x8E, 0x94, 0xCB,
+	0xBB, 0x88, 0x2C, 0x2D, 0xDA, 0xFA, 0xEE, 0xE6, 0x38, 0xA1, 0x8D, 0x73, 0x25, 0xC3, 0xC9, 0xB5,
+	0x10, 0x7B, 0xD7, 0xCB, 0x1E, 0x32, 0xFD, 0xB9, 0x7E, 0x21, 0x6A, 0xBB, 0xED, 0x3C, 0x19, 0xE1,
+	0xFB, 0x1D, 0x16, 0x3C, 0x11, 0xE6, 0x5C, 0x2B, 0x5C, 0xCF, 0x8F, 0x62, 0x4A, 0xC6, 0x0F, 0xD5,
+	0x5B, 0xEA, 0x6B, 0xCA, 0xFC, 0x59, 0xF1, 0x13, 0xC7, 0x5E, 0x3D, 0x9B, 0xCF, 0xF1, 0x77, 0x8B,
+	0x6F, 0xF5, 0x06, 0x3C, 0xAA, 0xCD, 0x70, 0xBB, 0x57, 0xD8, 0x2A, 0x80, 0xAA, 0x3D, 0x80, 0x00,
+	0x76, 0x00, 0x57, 0xF4, 0x4F, 0x08, 0x7D, 0x10, 0xF8, 0xE3, 0x34, 0x94, 0x6A, 0x67, 0x35, 0xA1,
+	0x85, 0x87, 0x54, 0x9F, 0x3C, 0xED, 0xF2, 0x7C, 0xAB, 0xFF, 0x00, 0x02, 0x7E, 0x87, 0x85, 0x8A,
+	0xE2, 0xAC, 0x1D, 0x35, 0x6A, 0x49, 0xCB, 0xF0, 0x3E, 0xB0, 0xF1, 0xE7, 0xED, 0x69, 0xF0, 0x87,
+	0xC1, 0xE2, 0x48, 0x6C, 0x35, 0x67, 0xD6, 0x2F, 0x17, 0x2A, 0xB0, 0x69, 0x2B, 0xFB, 0xB2, 0x47,
+	0xF7, 0xA4, 0x94, 0x88, 0xC7, 0xFC, 0x05, 0x8B, 0x7F, 0xB3, 0xDA, 0xBC, 0x43, 0xE2, 0x27, 0xED,
+	0x93, 0xF1, 0x43, 0xC5, 0x51, 0xC9, 0x67, 0xE1, 0xD3, 0x0E, 0x81, 0x64, 0xCA, 0xDB, 0xBE, 0xCE,
+	0xBE, 0x74, 0xC2, 0x33, 0x85, 0x2A, 0xCF, 0x81, 0xD4, 0x7B, 0x0A, 0xF2, 0x4C, 0x11, 0xC1, 0x14,
+	0xAB, 0xD4, 0xFF, 0x00, 0xBC, 0xBF, 0xD2, 0xBF, 0xAA, 0xF8, 0x33, 0xE8, 0xDF, 0xE1, 0xAF, 0x08,
+	0xF2, 0xD5, 0x9D, 0x0F, 0xAD, 0x56, 0x5F, 0x6E, 0xB7, 0xBD, 0xAF, 0x94, 0x34, 0x8A, 0x5D, 0xAE,
+	0x9B, 0xF3, 0x3E, 0x67, 0x17, 0xC4, 0x19, 0x86, 0x2B, 0xDD, 0x4F, 0x96, 0x3D, 0x97, 0xF9, 0xEE,
+	0x7E, 0xD3, 0xD9, 0xC1, 0x05, 0xAD, 0xBA, 0xA5, 0xBC, 0x42, 0x35, 0x55, 0xC2, 0xAF, 0xA7, 0x5A,
+	0xFC, 0x7F, 0xF8, 0xE0, 0x49, 0xF8, 0xD5, 0xE3, 0x02, 0x7F, 0xE8, 0x68, 0xD4, 0x3F, 0xF4, 0xA6,
+	0x4A, 0xFD, 0x85, 0x8B, 0xEE, 0x9F, 0xF3, 0xEB, 0x5F, 0x8F, 0x5F, 0x1C, 0x3F, 0xE4, 0xB5, 0x78,
+	0xC3, 0xFE, 0xC6, 0x8D, 0x43, 0xFF, 0x00, 0x4A, 0x64, 0xAF, 0xDE, 0xA8, 0xD1, 0xA7, 0x87, 0xA6,
+	0xA1, 0x4E, 0x2A, 0x29, 0x6C, 0x92, 0xB2, 0x4B, 0xB5, 0x8F, 0x0E, 0x5E, 0xF6, 0xE7, 0x2F, 0x45,
+	0x14, 0x56, 0x96, 0x00, 0xAF, 0x44, 0xFD, 0x92, 0xBF, 0xE4, 0xE7, 0x3C, 0x03, 0xFF, 0x00, 0x63,
+	0x55, 0xA7, 0xFE, 0x84, 0x2B, 0xCE, 0xEB, 0xD1, 0x3F, 0x64, 0xAF, 0xF9, 0x39, 0xCF, 0x00, 0xFF,
+	0x00, 0xD8, 0xD5, 0x69, 0xFF, 0x00, 0xA1, 0x0A, 0x00, 0xFD, 0x41, 0xF8, 0xDB, 0xFF, 0x00, 0x24,
+	0x63, 0xC5, 0x9F, 0xF6, 0x2B, 0xEA, 0x1F, 0xFA, 0x21, 0xEB, 0xF1, 0xEA, 0xBF, 0x61, 0x7E, 0x36,
+	0xFF, 0x00, 0xC9, 0x18, 0xF1, 0x67, 0xFD, 0x8A, 0xFA, 0x87, 0xFE, 0x88, 0x7A, 0xFC, 0x7A, 0xA0,
+	0x02, 0x8A, 0x28, 0xA0, 0x02, 0xBE, 0x92, 0xFF, 0x00, 0x82, 0x56, 0xFF, 0x00, 0xC9, 0xCD, 0x4F,
+	0xFF, 0x00, 0x62, 0xB5, 0xF7, 0xFE, 0x8D, 0xB7, 0xAF, 0x9B, 0x6B, 0xE9, 0x2F, 0xF8, 0x25, 0x6F,
+	0xFC, 0x9C, 0xD4, 0xFF, 0x00, 0xF6, 0x2B, 0x5F, 0x7F, 0xE8, 0xDB, 0x7A, 0x00, 0xFA, 0x8F, 0xFE,
+	0x0A, 0x55, 0xFF, 0x00, 0x26, 0x95, 0xAF, 0x7F, 0xD7, 0xED, 0x8F, 0xFE, 0x94, 0x2D, 0x7E, 0x65,
+	0x57, 0xE9, 0xAF, 0xFC, 0x14, 0xAB, 0xFE, 0x4D, 0x2B, 0x5E, 0xFF, 0x00, 0xAF, 0xDB, 0x1F, 0xFD,
+	0x28, 0x5A, 0xFC, 0xCA, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0xBE, 0xE3, 0xFF, 0x00, 0x82, 0x41,
+	0xFF, 0x00, 0xC8, 0xB7, 0xE3, 0xAF, 0xFA, 0xFF, 0x00, 0xB1, 0xFF, 0x00, 0xD1, 0x57, 0x15, 0xF0,
+	0xE5, 0x7D, 0xC7, 0xFF, 0x00, 0x04, 0x83, 0xFF, 0x00, 0x91, 0x6F, 0xC7, 0x5F, 0xF5, 0xFF, 0x00,
+	0x63, 0xFF, 0x00, 0xA2, 0xAE, 0x28, 0x01, 0x7F, 0xE0, 0xB0, 0x1F, 0xF2, 0x00, 0xF0, 0x2F, 0xFD,
+	0x7E, 0xDF, 0x7F, 0xE8, 0x11, 0xD7, 0xC3, 0x75, 0xF7, 0x27, 0xFC, 0x16, 0x03, 0xFE, 0x40, 0x1E,
+	0x05, 0xFF, 0x00, 0xAF, 0xDB, 0xEF, 0xFD, 0x02, 0x3A, 0xF8, 0x6E, 0x80, 0x0A, 0x28, 0xA2, 0x80,
+	0x0A, 0xFD, 0x34, 0xFF, 0x00, 0x82, 0x6A, 0xFF, 0x00, 0xC9, 0xA3, 0xE8, 0x7F, 0xF5, 0xFD, 0x7F,
+	0xFF, 0x00, 0xA5, 0x2D, 0x5F, 0x99, 0x75, 0xFA, 0x69, 0xFF, 0x00, 0x04, 0xD5, 0xFF, 0x00, 0x93,
+	0x47, 0xD0, 0xFF, 0x00, 0xEB, 0xFA, 0xFF, 0x00, 0xFF, 0x00, 0x4A, 0x5A, 0x80, 0x3E, 0x5D, 0xFF,
+	0x00, 0x82, 0xAB, 0xFF, 0x00, 0xC9, 0xCB, 0x45, 0xFF, 0x00, 0x62, 0xAD, 0xAF, 0xFE, 0x8C, 0x9A,
+	0xBE, 0x6D, 0x3D, 0x6B, 0xE9, 0x2F, 0xF8, 0x2A, 0xBF, 0xFC, 0x9C, 0xB4, 0x5F, 0xF6, 0x2A, 0xDA,
+	0xFF, 0x00, 0xE8, 0xC9, 0xAB, 0xE6, 0xD3, 0xD6, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x1A, 0xFF, 0x00,
+	0xC5, 0xFE, 0xF7, 0xFE, 0xCA, 0xB5, 0xFB, 0x15, 0xF0, 0x3F, 0xFE, 0x48, 0xAF, 0x83, 0xFF, 0x00,
+	0xEC, 0x57, 0xD3, 0xFF, 0x00, 0xF4, 0x9A, 0x3A, 0xFC, 0x75, 0x7F, 0xE2, 0xFF, 0x00, 0x7B, 0xFF,
+	0x00, 0x65, 0x5A, 0xFD, 0x8A, 0xF8, 0x1F, 0xFF, 0x00, 0x24, 0x57, 0xC1, 0xFF, 0x00, 0xF6, 0x2B,
+	0xE9, 0xFF, 0x00, 0xFA, 0x4D, 0x1D, 0x00, 0x7E, 0x64, 0xFE, 0xDA, 0x7F, 0xF2, 0x75, 0xDE, 0x36,
+	0xFF, 0x00, 0xB0, 0xE1, 0xFF, 0x00, 0xD0, 0x56, 0xBC, 0xB1, 0x3E, 0xE0, 0xFA, 0x57, 0xA9, 0xFE,
+	0xDA, 0x7F, 0xF2, 0x75, 0xDE, 0x36, 0xFF, 0x00, 0xB0, 0xE1, 0xFF, 0x00, 0xD0, 0x56, 0xBC, 0xB1,
+	0x3E, 0xE0, 0xFA, 0x50, 0x02, 0xD1, 0x45, 0x14, 0x00, 0x57, 0xDE, 0x9F, 0xF0, 0x48, 0x5F, 0xF9,
+	0x26, 0xBE, 0x30, 0xFF, 0x00, 0xB0, 0xE4, 0x1F, 0xFA, 0x26, 0xBE, 0x0B, 0xAF, 0xBD, 0x3F, 0xE0,
+	0x90, 0xBF, 0xF2, 0x4D, 0x7C, 0x61, 0xFF, 0x00, 0x61, 0xC8, 0x3F, 0xF4, 0x4D, 0x00, 0x78, 0xF7,
+	0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B, 0x5F, 0xFD, 0x0E, 0x5A, 0xF9, 0xB2,
+	0xBE, 0x93, 0xFF, 0x00, 0x82, 0xA8, 0xFF, 0x00, 0xC9, 0xCC, 0xDB, 0xFF, 0x00, 0xD8, 0xB1, 0x6B,
+	0xFF, 0x00, 0xA1, 0xCB, 0x5F, 0x36, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0xDB, 0xF0, 0xAF, 0xBA,
+	0x3F, 0xE0, 0x90, 0x1F, 0xF2, 0x2E, 0x78, 0xFB, 0xFE, 0xC2, 0x16, 0x1F, 0xFA, 0x2E, 0x6A, 0xF8,
+	0x5F, 0xB7, 0xE1, 0x5F, 0x74, 0x7F, 0xC1, 0x20, 0x3F, 0xE4, 0x5C, 0xF1, 0xF7, 0xFD, 0x84, 0x2C,
+	0x3F, 0xF4, 0x5C, 0xD4, 0x01, 0xE5, 0x5F, 0xF0, 0x55, 0x1F, 0xF9, 0x39, 0x9B, 0x7F, 0xFB, 0x16,
+	0x2D, 0x7F, 0xF4, 0x39, 0x6B, 0xE6, 0xCA, 0xFA, 0x4F, 0xFE, 0x0A, 0xA3, 0xFF, 0x00, 0x27, 0x33,
+	0x6F, 0xFF, 0x00, 0x62, 0xC5, 0xAF, 0xFE, 0x87, 0x2D, 0x7C, 0xD9, 0x40, 0x05, 0x14, 0x51, 0x40,
+	0x07, 0x6F, 0xC2, 0xBE, 0xE6, 0xFF, 0x00, 0x82, 0x41, 0xFF, 0x00, 0xC8, 0xBF, 0xE3, 0xBF, 0xFB,
+	0x09, 0x69, 0xFF, 0x00, 0xFA, 0x2E, 0x5A, 0xF8, 0x67, 0xB7, 0xE1, 0x5F, 0x73, 0x7F, 0xC1, 0x20,
+	0xFF, 0x00, 0xE4, 0x5F, 0xF1, 0xDF, 0xFD, 0x84, 0xB4, 0xFF, 0x00, 0xFD, 0x17, 0x2D, 0x00, 0x7D,
+	0x97, 0x07, 0xFA, 0xBF, 0xC6, 0x9F, 0x4C, 0x83, 0xFD, 0x5F, 0xE3, 0x4F, 0xA0, 0x02, 0x83, 0xD2,
+	0x8A, 0x0F, 0x4A, 0x00, 0xF8, 0x53, 0xFE, 0x0A, 0xFB, 0xFF, 0x00, 0x23, 0x27, 0x81, 0xFF, 0x00,
+	0xEB, 0xCA, 0xFB, 0xFF, 0x00, 0x46, 0x47, 0x5F, 0x1B, 0x57, 0xD9, 0x3F, 0xF0, 0x57, 0xDF, 0xF9,
+	0x19, 0x3C, 0x0F, 0xFF, 0x00, 0x5E, 0x57, 0xDF, 0xFA, 0x32, 0x3A, 0xF8, 0xDA, 0x80, 0x0A, 0x28,
+	0xA2, 0x80, 0x01, 0xD6, 0xBE, 0xAE, 0xFF, 0x00, 0x82, 0x49, 0x7F, 0xC9, 0x67, 0xF1, 0x37, 0xFD,
+	0x8A, 0x6B, 0xFF, 0x00, 0xA5, 0x31, 0x57, 0xCA, 0x23, 0xAD, 0x7D, 0x5D, 0xFF, 0x00, 0x04, 0x92,
+	0xFF, 0x00, 0x92, 0xCF, 0xE2, 0x6F, 0xFB, 0x14, 0xD7, 0xFF, 0x00, 0x4A, 0x62, 0xA0, 0x0F, 0x5F,
+	0xFF, 0x00, 0x82, 0xB4, 0x7F, 0xC9, 0xBA, 0x69, 0x1F, 0xF6, 0x3B, 0x5B, 0xFF, 0x00, 0xE9, 0x25,
+	0xD5, 0x7E, 0x79, 0x57, 0xE8, 0x6F, 0xFC, 0x15, 0xA3, 0xFE, 0x4D, 0xD3, 0x48, 0xFF, 0x00, 0xB1,
+	0xDA, 0xDF, 0xFF, 0x00, 0x49, 0x2E, 0xAB, 0xF3, 0xCA, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0xF7,
+	0xAF, 0xF8, 0x26, 0xC7, 0xFC, 0x9D, 0xCE, 0x83, 0xFF, 0x00, 0x60, 0xFD, 0x43, 0xFF, 0x00, 0x49,
+	0xDE, 0xBC, 0x16, 0xBD, 0xEB, 0xFE, 0x09, 0xB1, 0xFF, 0x00, 0x27, 0x73, 0xA0, 0xFF, 0x00, 0xD8,
+	0x3F, 0x50, 0xFF, 0x00, 0xD2, 0x77, 0xA0, 0x0F, 0xB2, 0x3F, 0xE0, 0xA2, 0x3F, 0xF2, 0x67, 0x5E,
+	0x30, 0xFF, 0x00, 0x73, 0x4F, 0xFF, 0x00, 0xD2, 0xFB, 0x7A, 0xFC, 0xBD, 0xAF, 0xD4, 0x2F, 0xF8,
+	0x28, 0x8F, 0xFC, 0x99, 0xD7, 0x8C, 0x3F, 0xDC, 0xD3, 0xFF, 0x00, 0xF4, 0xBE, 0xDE, 0xBF, 0x2F,
+	0x68, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xAF, 0x44, 0xFD, 0x92, 0xBF, 0xE4, 0xE7, 0x3C, 0x03, 0xFF,
+	0x00, 0x63, 0x55, 0xA7, 0xFE, 0x84, 0x2B, 0xCE, 0xEB, 0xD1, 0x3F, 0x64, 0xAF, 0xF9, 0x39, 0xCF,
+	0x00, 0xFF, 0x00, 0xD8, 0xD5, 0x69, 0xFF, 0x00, 0xA1, 0x0A, 0x00, 0xFD, 0x41, 0xF8, 0xDB, 0xFF,
+	0x00, 0x24, 0x63, 0xC5, 0x9F, 0xF6, 0x2B, 0xEA, 0x1F, 0xFA, 0x21, 0xEB, 0xF1, 0xEA, 0xBF, 0x61,
+	0x7E, 0x36, 0xFF, 0x00, 0xC9, 0x18, 0xF1, 0x67, 0xFD, 0x8A, 0xFA, 0x87, 0xFE, 0x88, 0x7A, 0xFC,
+	0x7A, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0xBE, 0x92, 0xFF, 0x00, 0x82, 0x56, 0xFF, 0x00, 0xC9,
+	0xCD, 0x4F, 0xFF, 0x00, 0x62, 0xB5, 0xF7, 0xFE, 0x8D, 0xB7, 0xAF, 0x9B, 0x6B, 0xE9, 0x2F, 0xF8,
+	0x25, 0x6F, 0xFC, 0x9C, 0xD4, 0xFF, 0x00, 0xF6, 0x2B, 0x5F, 0x7F, 0xE8, 0xDB, 0x7A, 0x00, 0xFA,
+	0x8F, 0xFE, 0x0A, 0x55, 0xFF, 0x00, 0x26, 0x95, 0xAF, 0x7F, 0xD7, 0xED, 0x8F, 0xFE, 0x94, 0x2D,
+	0x7E, 0x65, 0x57, 0xE9, 0xAF, 0xFC, 0x14, 0xAB, 0xFE, 0x4D, 0x2B, 0x5E, 0xFF, 0x00, 0xAF, 0xDB,
+	0x1F, 0xFD, 0x28, 0x5A, 0xFC, 0xCA, 0xA0, 0x02, 0x8A, 0x28, 0xA0, 0x02, 0xBE, 0xE3, 0xFF, 0x00,
+	0x82, 0x41, 0xFF, 0x00, 0xC8, 0xB7, 0xE3, 0xAF, 0xFA, 0xFF, 0x00, 0xB1, 0xFF, 0x00, 0xD1, 0x57,
+	0x15, 0xF0, 0xE5, 0x7D, 0xC9, 0xFF, 0x00, 0x04, 0x82, 0x04, 0xF8, 0x6F, 0xC7, 0x58, 0x1F, 0xF2,
+	0xFF, 0x00, 0x63, 0xFF, 0x00, 0xA2, 0xAE, 0x28, 0x00, 0xFF, 0x00, 0x82, 0xC0, 0x7F, 0xC8, 0x03,
+	0xC0, 0xBF, 0xF5, 0xFB, 0x7D, 0xFF, 0x00, 0xA0, 0x47, 0x5F, 0x0D, 0xD7, 0xDC, 0x9F, 0xF0, 0x58,
+	0x1F, 0xF9, 0x00, 0x78, 0x17, 0xFE, 0xBF, 0x6F, 0xBF, 0xF4, 0x5C, 0x75, 0xF0, 0xDD, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x15, 0xFA, 0x69, 0xFF, 0x00, 0x04, 0xD5, 0xFF, 0x00, 0x93, 0x47, 0xD0, 0xFF,
+	0x00, 0xEB, 0xFA, 0xFF, 0x00, 0xFF, 0x00, 0x4A, 0x5A, 0xBF, 0x32, 0xEB, 0xF4, 0xD3, 0xFE, 0x09,
+	0xAB, 0xFF, 0x00, 0x26, 0x8F, 0xA1, 0xFF, 0x00, 0xD7, 0xF5, 0xFF, 0x00, 0xFE, 0x94, 0xB5, 0x00,
+	0x7C, 0xBB, 0xFF, 0x00, 0x05, 0x57, 0xFF, 0x00, 0x93, 0x96, 0x8B, 0xFE, 0xC5, 0x5B, 0x5F, 0xFD,
+	0x19, 0x35, 0x7C, 0xDA, 0x7A, 0xD7, 0xD2, 0x5F, 0xF0, 0x55, 0x7F, 0xF9, 0x39, 0x68, 0xBF, 0xEC,
+	0x55, 0xB5, 0xFF, 0x00, 0xD1, 0x93, 0x57, 0xCD, 0xA7, 0xAD, 0x00, 0x14, 0x51, 0x45, 0x00, 0x35,
+	0xFF, 0x00, 0x8B, 0xFD, 0xEF, 0xFD, 0x95, 0x6B, 0xF6, 0x2B, 0xE0, 0x7F, 0xFC, 0x91, 0x5F, 0x07,
+	0xFF, 0x00, 0xD8, 0xAF, 0xA7, 0xFF, 0x00, 0xE9, 0x34, 0x75, 0xF8, 0xEA, 0xFF, 0x00, 0xC5, 0xFE,
+	0xF7, 0xFE, 0xCA, 0xB5, 0xFB, 0x15, 0xF0, 0x3F, 0xFE, 0x48, 0xAF, 0x83, 0xFF, 0x00, 0xEC, 0x57,
+	0xD3, 0xFF, 0x00, 0xF4, 0x9A, 0x3A, 0x00, 0xFC, 0xC9, 0xFD, 0xB4, 0xFF, 0x00, 0xE4, 0xEB, 0xBC,
+	0x6D, 0xFF, 0x00, 0x61, 0xC3, 0xFF, 0x00, 0xA0, 0xAD, 0x79, 0x62, 0x7D, 0xC1, 0xF4, 0xAF, 0x53,
+	0xFD, 0xB4, 0xFF, 0x00, 0xE4, 0xEB, 0xBC, 0x6D, 0xFF, 0x00, 0x61, 0xC3, 0xFF, 0x00, 0xA0, 0xAD,
+	0x79, 0x62, 0x7D, 0xC1, 0xF4, 0xA0, 0x05, 0xA2, 0x8A, 0x28, 0x03, 0x73, 0xE1, 0xAF, 0xFC, 0x94,
+	0x6F, 0x0E, 0x7F, 0xD8, 0x6A, 0xD7, 0xFF, 0x00, 0x4A, 0x52, 0xBF, 0x64, 0x8F, 0xDC, 0x1F, 0xE7,
+	0xB1, 0xAF, 0xC6, 0xDF, 0x86, 0xBF, 0xF2, 0x51, 0xBC, 0x39, 0xFF, 0x00, 0x61, 0xAB, 0x5F, 0xFD,
+	0x29, 0x4A, 0xFD, 0x92, 0x60, 0xC1, 0x07, 0x1F, 0xE7, 0x06, 0x80, 0x3F, 0x14, 0x68, 0xA2, 0x8A,
+	0x00, 0x28, 0xA2, 0x8A, 0x3A, 0xDC, 0x0F, 0x6C, 0xFF, 0x00, 0x82, 0x76, 0xFF, 0x00, 0xC9, 0xE3,
+	0xF8, 0x37, 0xFD, 0xDD, 0x4B, 0xFF, 0x00, 0x4D, 0xF7, 0x35, 0xF7, 0x87, 0xED, 0xA9, 0xBD, 0x3F,
+	0x65, 0x7F, 0x1D, 0x4B, 0x14, 0x8C, 0xB2, 0x2E, 0x87, 0x21, 0x56, 0x5E, 0xAB, 0xC8, 0xAF, 0x83,
+	0xFF, 0x00, 0xE0, 0x9D, 0x9F, 0xF2, 0x79, 0x1E, 0x0D, 0xFF, 0x00, 0x77, 0x52, 0xFF, 0x00, 0xD3,
+	0x75, 0xCD, 0x7D, 0xE5, 0xFB, 0x6B, 0xFF, 0x00, 0xC9, 0xAB, 0xF8, 0xE3, 0xFE, 0xC0, 0x6F, 0xFC,
+	0xC5, 0x45, 0x4A, 0x74, 0xEA, 0xA6, 0xA6, 0xAE, 0xBB, 0x35, 0x74, 0x1F, 0x0E, 0xC7, 0xE6, 0x5E,
+	0x81, 0xF1, 0xAF, 0xE2, 0xCF, 0x85, 0x24, 0xFF, 0x00, 0x8A, 0x7B, 0xC7, 0xDA, 0xA4, 0x4A, 0xBC,
+	0x08, 0x9A, 0xE0, 0xCB, 0x16, 0x3D, 0x36, 0xBF, 0x03, 0xE8, 0x38, 0x15, 0xDB, 0x68, 0x3F, 0xB6,
+	0xCF, 0xC6, 0x5D, 0x27, 0x6C, 0x7A, 0xBC, 0x1A, 0x4E, 0xAA, 0x98, 0xC3, 0x35, 0xC5, 0x8B, 0x23,
+	0x0F, 0xA1, 0x89, 0xEB, 0xC7, 0xE8, 0xAF, 0x87, 0xCE, 0xBC, 0x31, 0xF0, 0xFF, 0x00, 0x88, 0x6E,
+	0xF1, 0xF9, 0x6D, 0x29, 0xB7, 0xBC, 0xB9, 0x12, 0x97, 0xFE, 0x04, 0x92, 0x7F, 0x89, 0xD9, 0x47,
+	0x30, 0xC7, 0x50, 0xF8, 0x2A, 0x33, 0xE9, 0x0D, 0x17, 0xF6, 0xF6, 0xB5, 0x7D, 0xA9, 0xE2, 0x0F,
+	0x86, 0xD2, 0xAE, 0x06, 0x1A, 0x6B, 0x1D, 0x41, 0x98, 0x9F, 0x7D, 0xAC, 0x80, 0x8F, 0xA1, 0x62,
+	0x47, 0x72, 0x7A, 0xD7, 0x51, 0xA4, 0xFE, 0xDB, 0x7F, 0x07, 0xEF, 0xF6, 0xAD, 0xED, 0xBE, 0xB1,
+	0x64, 0x7F, 0x89, 0xAE, 0x2C, 0x43, 0x00, 0x7E, 0xA9, 0x23, 0x13, 0xF5, 0x20, 0x1F, 0x61, 0x5F,
+	0x23, 0xD1, 0x5F, 0x97, 0x66, 0x9F, 0x45, 0x9F, 0x08, 0xF3, 0x06, 0xDD, 0x2C, 0x3C, 0xE8, 0xDF,
+	0xF9, 0x2A, 0x37, 0xFF, 0x00, 0xA5, 0x73, 0x1E, 0x95, 0x1E, 0x24, 0xCD, 0x29, 0xFC, 0x52, 0x4F,
+	0xE4, 0x7D, 0xF7, 0xF0, 0x97, 0xE2, 0x27, 0x84, 0x7E, 0x37, 0xDD, 0xDE, 0x58, 0xFC, 0x32, 0xD4,
+	0xE4, 0xD4, 0xA6, 0xB1, 0x89, 0x64, 0xBE, 0xB7, 0x36, 0x92, 0xC4, 0xEA, 0xA7, 0xA6, 0x3C, 0xCE,
+	0x1B, 0xEB, 0xDE, 0xBF, 0x24, 0xFF, 0x00, 0xE0, 0xA8, 0x5F, 0xB2, 0xF7, 0xED, 0x11, 0x6F, 0xFB,
+	0x5A, 0x78, 0xD7, 0xE2, 0x5D, 0xCF, 0xC0, 0xDF, 0x16, 0x0D, 0x03, 0x54, 0xD6, 0x2D, 0xA0, 0xB1,
+	0xD6, 0x93, 0x43, 0x99, 0xAD, 0xE7, 0x93, 0xEC, 0xD1, 0xA9, 0x50, 0x55, 0x30, 0x48, 0xD8, 0xFC,
+	0x8E, 0x0E, 0xCE, 0x2B, 0xF4, 0xAF, 0xFE, 0x09, 0x17, 0xFF, 0x00, 0x25, 0x17, 0xC6, 0x1F, 0xF6,
+	0x01, 0x8B, 0xFF, 0x00, 0x47, 0x1A, 0xF5, 0x4F, 0xF8, 0x2B, 0x5A, 0x20, 0xFD, 0x9D, 0x74, 0x56,
+	0x08, 0x33, 0xFF, 0x00, 0x09, 0xBD, 0xB7, 0x38, 0xFF, 0x00, 0xA7, 0x4B, 0xBA, 0xE8, 0xE0, 0x9F,
+	0xA3, 0xA7, 0x0A, 0x70, 0x0E, 0x69, 0x53, 0x1B, 0x97, 0x62, 0x6A, 0xC9, 0xCE, 0x3C, 0xAD, 0x4D,
+	0xC5, 0xF5, 0xBF, 0xD9, 0x8C, 0x4F, 0xD0, 0xB8, 0x07, 0xC6, 0x2C, 0xE3, 0x80, 0xF3, 0x59, 0x63,
+	0xA8, 0x50, 0x85, 0x47, 0x28, 0xF2, 0xB5, 0x2B, 0xAD, 0x1B, 0xBF, 0x4F, 0x43, 0xF9, 0xE3, 0x9F,
+	0xE1, 0x9F, 0xC4, 0xBB, 0x5D, 0xC6, 0xF7, 0xE1, 0xFE, 0xB7, 0x16, 0xD3, 0x89, 0x3E, 0xD1, 0xA4,
+	0xCA, 0xA5, 0x4F, 0x70, 0x7D, 0xEA, 0xA9, 0xF0, 0x6F, 0x8B, 0xF3, 0xFF, 0x00, 0x22, 0x9E, 0xA3,
+	0xFF, 0x00, 0x80, 0x2F, 0x5F, 0xA3, 0x03, 0xA5, 0x15, 0xFA, 0x7B, 0xE0, 0xDA, 0x3D, 0x2B, 0x3F,
+	0xB9, 0x1F, 0xB8, 0x53, 0xFA, 0x62, 0x66, 0xA9, 0x7B, 0xF9, 0x5C, 0x1F, 0xFD, 0xC4, 0x92, 0xFD,
+	0x0F, 0xCE, 0x71, 0xE0, 0xEF, 0x17, 0x8E, 0x9E, 0x13, 0xD4, 0xBF, 0xF0, 0x05, 0xEA, 0x7B, 0x7F,
+	0x87, 0xBF, 0x10, 0x2E, 0xC6, 0xEB, 0x4F, 0x03, 0xEA, 0xB2, 0x8E, 0xFE, 0x56, 0x9B, 0x23, 0x57,
+	0xE8, 0x8D, 0x14, 0xBF, 0xD4, 0xDA, 0x7D, 0x6B, 0x3F, 0xB9, 0x0E, 0x5F, 0x4C, 0x4C, 0xD3, 0x96,
+	0xD1, 0xCA, 0xE0, 0xBF, 0xEE, 0x24, 0xBF, 0xC8, 0xF9, 0x33, 0xF6, 0x4C, 0xFD, 0x95, 0xFF, 0x00,
+	0x69, 0x5F, 0x14, 0xFC, 0x65, 0xF0, 0x6F, 0x8C, 0x7C, 0x37, 0xF0, 0x03, 0xC6, 0xD7, 0x5A, 0x4D,
+	0x87, 0x8C, 0x34, 0xE9, 0x2F, 0xF5, 0x4B, 0x7F, 0x0C, 0xDD, 0x7D, 0x9E, 0x05, 0x49, 0xE2, 0x66,
+	0x66, 0x97, 0x67, 0x3B, 0x57, 0x0D, 0xB4, 0x64, 0x73, 0x5F, 0xB5, 0xBF, 0x11, 0x7E, 0x22, 0xF8,
+	0x4B, 0xE0, 0xE2, 0xE9, 0xE9, 0xF1, 0x3B, 0x57, 0x93, 0x49, 0x93, 0x54, 0xB7, 0xDF, 0x63, 0x0C,
+	0x96, 0x32, 0x17, 0x7E, 0x32, 0x7E, 0x45, 0x4D, 0xCA, 0x7D, 0x8F, 0x23, 0xA1, 0xAD, 0x2F, 0xF8,
+	0x24, 0xC4, 0x71, 0xB7, 0xEC, 0xE7, 0xAD, 0x33, 0x46, 0xA4, 0xFF, 0x00, 0xC2, 0x6D, 0x71, 0xC9,
+	0x1F, 0xF4, 0xE7, 0x69, 0x5E, 0x5F, 0xFF, 0x00, 0x05, 0x7A, 0x18, 0xF8, 0x8F, 0xE1, 0x1E, 0x3F,
+	0xE6, 0x07, 0x37, 0xFE, 0x8E, 0x35, 0xF9, 0xBF, 0x1C, 0xFD, 0x1E, 0xF8, 0x67, 0x8F, 0xB1, 0x54,
+	0x2B, 0x66, 0x18, 0x8A, 0xB1, 0xF6, 0x69, 0xAB, 0x47, 0x95, 0x6E, 0xEF, 0xBB, 0x4F, 0xF2, 0x3F,
+	0x1A, 0xF1, 0x0B, 0xC6, 0xCC, 0xE3, 0xC4, 0x0C, 0x65, 0x2C, 0x45, 0x7C, 0x34, 0x29, 0x3A, 0x69,
+	0xA5, 0xCA, 0xDB, 0xD1, 0xBB, 0xEB, 0x71, 0xBA, 0x9F, 0xED, 0xB1, 0xF0, 0x62, 0xC1, 0x77, 0xE9,
+	0xF2, 0xEA, 0xDA, 0x87, 0xF7, 0x56, 0x0B, 0x2D, 0x84, 0xFF, 0x00, 0xDF, 0xD9, 0x07, 0xEA, 0x07,
+	0xD0, 0x57, 0x37, 0xAD, 0xFE, 0xDE, 0xBA, 0x1A, 0xA3, 0x0F, 0x0E, 0x7C, 0x38, 0xBA, 0x99, 0xBB,
+	0x3E, 0xA1, 0x7C, 0xB1, 0x63, 0xEA, 0xB1, 0xA9, 0xCF, 0xE6, 0x7E, 0xA6, 0xBE, 0x69, 0xA2, 0xBC,
+	0xDC, 0xB3, 0xE8, 0xAF, 0xE1, 0x36, 0x02, 0xDE, 0xD6, 0x8D, 0x4A, 0xDF, 0xE3, 0xA8, 0xFF, 0x00,
+	0xF6, 0xDE, 0x55, 0xF8, 0x1F, 0x99, 0xD4, 0xE2, 0x5C, 0xD2, 0x7F, 0x0B, 0x51, 0xF4, 0x47, 0xB3,
+	0x6B, 0xFF, 0x00, 0xB7, 0x27, 0xC5, 0x5D, 0x43, 0x30, 0x68, 0x9A, 0x46, 0x91, 0xA7, 0xAB, 0x2F,
+	0xFA, 0xC5, 0x85, 0xA5, 0x91, 0x7F, 0xEF, 0xE7, 0x15, 0xC3, 0xF8, 0x8F, 0xE3, 0xEF, 0xC6, 0x5F,
+	0x14, 0xC6, 0xCB, 0xAB, 0x7C, 0x43, 0xD4, 0xD6, 0x26, 0xF9, 0x7C, 0x9B, 0x59, 0x96, 0xDD, 0x0F,
+	0xD5, 0x62, 0xE4, 0xD7, 0x23, 0x45, 0x7E, 0x9D, 0x92, 0xF8, 0x53, 0xE1, 0xCF, 0x0F, 0xC9, 0x4B,
+	0x03, 0x95, 0xD1, 0x8B, 0x5F, 0x69, 0xC1, 0x4A, 0x5F, 0xF8, 0x14, 0xAE, 0xFF, 0x00, 0x13, 0xCD,
+	0xAD, 0x99, 0xE6, 0x15, 0xFE, 0x3A, 0x8D, 0x9F, 0xAB, 0x9F, 0xB1, 0x93, 0x3C, 0xBF, 0xB2, 0xD7,
+	0x82, 0xE7, 0xB8, 0x73, 0x24, 0x8D, 0xA2, 0x03, 0x24, 0x8C, 0x49, 0x2C, 0xDB, 0x9B, 0x92, 0x4F,
+	0x39, 0xFA, 0xF3, 0x5F, 0x06, 0xFF, 0x00, 0xC1, 0x46, 0x7F, 0xE4, 0xF1, 0x3C, 0x65, 0xFF, 0x00,
+	0x70, 0xFF, 0x00, 0xFD, 0x36, 0xDB, 0xD7, 0xDE, 0x5F, 0xB1, 0x6F, 0xFC, 0x9A, 0xA7, 0x82, 0x3F,
+	0xEC, 0x02, 0xBF, 0xFA, 0x13, 0x57, 0xC1, 0xFF, 0x00, 0xF0, 0x51, 0xBF, 0xF9, 0x3C, 0x6F, 0x19,
+	0xFF, 0x00, 0xDC, 0x3F, 0xFF, 0x00, 0x4D, 0xB6, 0xF5, 0xF7, 0xD0, 0xA5, 0x4E, 0x9C, 0x54, 0x61,
+	0x14, 0x97, 0x92, 0xE8, 0x70, 0xC9, 0xCA, 0x4E, 0xEC, 0xF1, 0x33, 0xD6, 0x8A, 0x0F, 0x5A, 0x2B,
+	0x4F, 0x20, 0xEA, 0x14, 0xAB, 0xD4, 0xFF, 0x00, 0xBC, 0xBF, 0xD2, 0x92, 0x95, 0x7A, 0x9F, 0xF7,
+	0x97, 0xFA, 0x50, 0x07, 0xED, 0x64, 0x5F, 0x74, 0xFF, 0x00, 0x9F, 0x5A, 0xFC, 0x7A, 0xF8, 0xE1,
+	0xFF, 0x00, 0x25, 0xAB, 0xC6, 0x1F, 0xF6, 0x34, 0x6A, 0x1F, 0xFA, 0x53, 0x25, 0x7E, 0xC2, 0xC5,
+	0xF7, 0x4F, 0xF9, 0xF5, 0xAF, 0xC7, 0xAF, 0x8E, 0x1F, 0xF2, 0x5A, 0xBC, 0x61, 0xFF, 0x00, 0x63,
+	0x46, 0xA1, 0xFF, 0x00, 0xA5, 0x32, 0x50, 0x07, 0x2F, 0x45, 0x14, 0x50, 0x01, 0x5E, 0x89, 0xFB,
+	0x25, 0x7F, 0xC9, 0xCE, 0x78, 0x07, 0xFE, 0xC6, 0xAB, 0x4F, 0xFD, 0x08, 0x57, 0x9D, 0xD7, 0xA2,
+	0x7E, 0xC9, 0x5F, 0xF2, 0x73, 0x9E, 0x01, 0xFF, 0x00, 0xB1, 0xAA, 0xD3, 0xFF, 0x00, 0x42, 0x14,
+	0x01, 0xFA, 0x83, 0xF1, 0xB7, 0xFE, 0x48, 0xC7, 0x8B, 0x3F, 0xEC, 0x57, 0xD4, 0x3F, 0xF4, 0x43,
+	0xD7, 0xE3, 0xD5, 0x7E, 0xC2, 0xFC, 0x6D, 0xFF, 0x00, 0x92, 0x31, 0xE2, 0xCF, 0xFB, 0x15, 0xF5,
+	0x0F, 0xFD, 0x10, 0xF5, 0xF8, 0xF5, 0x40, 0x05, 0x14, 0x51, 0x40, 0x05, 0x7D, 0x25, 0xFF, 0x00,
+	0x04, 0xAD, 0xFF, 0x00, 0x93, 0x9A, 0x9F, 0xFE, 0xC5, 0x6B, 0xEF, 0xFD, 0x1B, 0x6F, 0x5F, 0x36,
+	0xD7, 0xD2, 0x5F, 0xF0, 0x4A, 0xDF, 0xF9, 0x39, 0xA9, 0xFF, 0x00, 0xEC, 0x56, 0xBE, 0xFF, 0x00,
+	0xD1, 0xB6, 0xF4, 0x01, 0xF5, 0x1F, 0xFC, 0x14, 0xAB, 0xFE, 0x4D, 0x2B, 0x5E, 0xFF, 0x00, 0xAF,
+	0xDB, 0x1F, 0xFD, 0x28, 0x5A, 0xFC, 0xCA, 0xAF, 0xD3, 0x5F, 0xF8, 0x29, 0x57, 0xFC, 0x9A, 0x56,
+	0xBD, 0xFF, 0x00, 0x5F, 0xB6, 0x3F, 0xFA, 0x50, 0xB5, 0xF9, 0x95, 0x40, 0x05, 0x14, 0x51, 0x40,
+	0x05, 0x7D, 0xC7, 0xFF, 0x00, 0x04, 0x83, 0xFF, 0x00, 0x91, 0x6F, 0xC7, 0x5F, 0xF5, 0xFF, 0x00,
+	0x63, 0xFF, 0x00, 0xA2, 0xAE, 0x2B, 0xE1, 0xCA, 0xFB, 0x8F, 0xFE, 0x09, 0x07, 0xFF, 0x00, 0x22,
+	0xDF, 0x8E, 0xBF, 0xEB, 0xFE, 0xC7, 0xFF, 0x00, 0x45, 0x5C, 0x50, 0x02, 0xFF, 0x00, 0xC1, 0x60,
+	0x3F, 0xE4, 0x01, 0xE0, 0x5F, 0xFA, 0xFD, 0xBE, 0xFF, 0x00, 0xD0, 0x23, 0xAF, 0x86, 0xEB, 0xEE,
+	0x4F, 0xF8, 0x2C, 0x07, 0xFC, 0x80, 0x3C, 0x0B, 0xFF, 0x00, 0x5F, 0xB7, 0xDF, 0xFA, 0x04, 0x75,
+	0xF0, 0xDD, 0x00, 0x14, 0x51, 0x45, 0x00, 0x15, 0xFA, 0x69, 0xFF, 0x00, 0x04, 0xD5, 0xFF, 0x00,
+	0x93, 0x47, 0xD0, 0xFF, 0x00, 0xEB, 0xFA, 0xFF, 0x00, 0xFF, 0x00, 0x4A, 0x5A, 0xBF, 0x32, 0xEB,
+	0xF4, 0xD3, 0xFE, 0x09, 0xAB, 0xFF, 0x00, 0x26, 0x8F, 0xA1, 0xFF, 0x00, 0xD7, 0xF5, 0xFF, 0x00,
+	0xFE, 0x94, 0xB5, 0x00, 0x7C, 0xBB, 0xFF, 0x00, 0x05, 0x57, 0xFF, 0x00, 0x93, 0x96, 0x8B, 0xFE,
+	0xC5, 0x5B, 0x5F, 0xFD, 0x19, 0x35, 0x7C, 0xDA, 0x7A, 0xD7, 0xD2, 0x5F, 0xF0, 0x55, 0x7F, 0xF9,
+	0x39, 0x68, 0xBF, 0xEC, 0x55, 0xB5, 0xFF, 0x00, 0xD1, 0x93, 0x57, 0xCD, 0xA7, 0xAD, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x35, 0xFF, 0x00, 0x8B, 0xFD, 0xEF, 0xFD, 0x95, 0x6B, 0xF6, 0x2B, 0xE0, 0x7F,
+	0xFC, 0x91, 0x5F, 0x07, 0xFF, 0x00, 0xD8, 0xAF, 0xA7, 0xFF, 0x00, 0xE9, 0x34, 0x75, 0xF8, 0xEA,
+	0xFF, 0x00, 0xC5, 0xFE, 0xF7, 0xFE, 0xCA, 0xB5, 0xFB, 0x15, 0xF0, 0x3F, 0xFE, 0x48, 0xAF, 0x83,
+	0xFF, 0x00, 0xEC, 0x57, 0xD3, 0xFF, 0x00, 0xF4, 0x9A, 0x3A, 0x00, 0xFC, 0xC9, 0xFD, 0xB4, 0xFF,
+	0x00, 0xE4, 0xEB, 0xBC, 0x6D, 0xFF, 0x00, 0x61, 0xC3, 0xFF, 0x00, 0xA0, 0xAD, 0x79, 0x62, 0x7D,
+	0xC1, 0xF4, 0xAF, 0x53, 0xFD, 0xB4, 0xFF, 0x00, 0xE4, 0xEB, 0xBC, 0x6D, 0xFF, 0x00, 0x61, 0xC3,
+	0xFF, 0x00, 0xA0, 0xAD, 0x79, 0x62, 0x7D, 0xC1, 0xF4, 0xA0, 0x05, 0xA2, 0x8A, 0x28, 0x00, 0xAF,
+	0xBD, 0x3F, 0xE0, 0x90, 0xBF, 0xF2, 0x4D, 0x7C, 0x61, 0xFF, 0x00, 0x61, 0xC8, 0x3F, 0xF4, 0x4D,
+	0x7C, 0x17, 0x5F, 0x7A, 0x7F, 0xC1, 0x21, 0x7F, 0xE4, 0x9A, 0xF8, 0xC3, 0xFE, 0xC3, 0x90, 0x7F,
+	0xE8, 0x9A, 0x00, 0xF1, 0xEF, 0xF8, 0x2A, 0x8F, 0xFC, 0x9C, 0xCD, 0xBF, 0xFD, 0x8B, 0x16, 0xBF,
+	0xFA, 0x1C, 0xB5, 0xF3, 0x65, 0x7D, 0x27, 0xFF, 0x00, 0x05, 0x51, 0xFF, 0x00, 0x93, 0x99, 0xB7,
+	0xFF, 0x00, 0xB1, 0x62, 0xD7, 0xFF, 0x00, 0x43, 0x96, 0xBE, 0x6C, 0xA0, 0x02, 0x8A, 0x28, 0xA0,
+	0x03, 0xB7, 0xE1, 0x5F, 0x74, 0x7F, 0xC1, 0x20, 0x3F, 0xE4, 0x5C, 0xF1, 0xF7, 0xFD, 0x84, 0x2C,
+	0x3F, 0xF4, 0x5C, 0xD5, 0xF0, 0xBF, 0x6F, 0xC2, 0xBE, 0xE8, 0xFF, 0x00, 0x82, 0x40, 0x7F, 0xC8,
+	0xB9, 0xE3, 0xEF, 0xFB, 0x08, 0x58, 0x7F, 0xE8, 0xB9, 0xA8, 0x03, 0xCA, 0xBF, 0xE0, 0xAA, 0x3F,
+	0xF2, 0x73, 0x36, 0xFF, 0x00, 0xF6, 0x2C, 0x5A, 0xFF, 0x00, 0xE8, 0x72, 0xD7, 0xCD, 0x95, 0xF4,
+	0x9F, 0xFC, 0x15, 0x47, 0xFE, 0x4E, 0x66, 0xDF, 0xFE, 0xC5, 0x8B, 0x5F, 0xFD, 0x0E, 0x5A, 0xF9,
+	0xB2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0E, 0xDF, 0x85, 0x7D, 0xCD, 0xFF, 0x00, 0x04, 0x83, 0xFF,
+	0x00, 0x91, 0x7F, 0xC7, 0x7F, 0xF6, 0x12, 0xD3, 0xFF, 0x00, 0xF4, 0x5C, 0xB5, 0xF0, 0xCF, 0x6F,
+	0xC2, 0xBE, 0xE6, 0xFF, 0x00, 0x82, 0x41, 0xFF, 0x00, 0xC8, 0xBF, 0xE3, 0xBF, 0xFB, 0x09, 0x69,
+	0xFF, 0x00, 0xFA, 0x2E, 0x5A, 0x00, 0xFB, 0x2E, 0x0F, 0xF5, 0x7F, 0x8D, 0x3E, 0x99, 0x07, 0xFA,
+	0xBF, 0xC6, 0x9F, 0x40, 0x01, 0x20, 0x0C, 0x93, 0x41, 0xE9, 0x45, 0x14, 0x01, 0xC9, 0xFC, 0x47,
+	0xF8, 0x19, 0xF0, 0x8F, 0xE2, 0xF4, 0xD6, 0xB7, 0x3F, 0x13, 0x3C, 0x03, 0xA7, 0xEB, 0x52, 0x58,
+	0xAB, 0x2D, 0xA3, 0x5E, 0xC6, 0x58, 0xC4, 0x0F, 0x5C, 0x60, 0x8A, 0xE6, 0x7F, 0xE1, 0x89, 0xFF,
+	0x00, 0x65, 0x3F, 0xFA, 0x21, 0xDA, 0x27, 0xFD, 0xFB, 0x7F, 0xFE, 0x2A, 0x8A, 0x28, 0x00, 0xFF,
+	0x00, 0x86, 0x27, 0xFD, 0x94, 0xFF, 0x00, 0xE8, 0x87, 0x68, 0x9F, 0xF7, 0xED, 0xFF, 0x00, 0xF8,
+	0xAA, 0x3F, 0xE1, 0x89, 0xFF, 0x00, 0x65, 0x3F, 0xFA, 0x21, 0xDA, 0x27, 0xFD, 0xFB, 0x7F, 0xFE,
+	0x2A, 0x8A, 0x28, 0x00, 0xFF, 0x00, 0x86, 0x27, 0xFD, 0x94, 0xFF, 0x00, 0xE8, 0x87, 0x68, 0x9F,
+	0xF7, 0xED, 0xFF, 0x00, 0xF8, 0xAA, 0xE8, 0x3E, 0x1C, 0x7E, 0xCF, 0x9F, 0x06, 0x3E, 0x10, 0xEA,
+	0x53, 0x6A, 0xFF, 0x00, 0x0D, 0x7E, 0x1E, 0xD8, 0xE8, 0xF7, 0x37, 0x10, 0x79, 0x33, 0x4B, 0x6B,
+	0xBB, 0x2C, 0x99, 0xCE, 0x39, 0x24, 0x75, 0xFC, 0x68, 0xA2, 0x80, 0x35, 0x3E, 0x21, 0xFC, 0x31,
+	0xF0, 0x07, 0xC5, 0x9D, 0x0E, 0x3F, 0x0D, 0x7C, 0x47, 0xF0, 0xAD, 0xA6, 0xB1, 0x61, 0x15, 0xD2,
+	0xDC, 0xC7, 0x6B, 0x78, 0x85, 0x91, 0x65, 0x50, 0x42, 0xBF, 0x5E, 0xA0, 0x33, 0x7E, 0x75, 0xC5,
+	0xFF, 0x00, 0xC3, 0x13, 0xFE, 0xCA, 0x7F, 0xF4, 0x43, 0xB4, 0x4F, 0xFB, 0xF6, 0xFF, 0x00, 0xFC,
+	0x55, 0x14, 0x50, 0x01, 0xFF, 0x00, 0x0C, 0x4F, 0xFB, 0x29, 0xFF, 0x00, 0xD1, 0x0E, 0xD1, 0x3F,
+	0xEF, 0xDB, 0xFF, 0x00, 0xF1, 0x54, 0x7F, 0xC3, 0x13, 0xFE, 0xCA, 0x7F, 0xF4, 0x43, 0xB4, 0x4F,
+	0xFB, 0xF6, 0xFF, 0x00, 0xFC, 0x55, 0x14, 0x50, 0x01, 0xFF, 0x00, 0x0C, 0x4F, 0xFB, 0x29, 0xFF,
+	0x00, 0xD1, 0x0E, 0xD1, 0x3F, 0xEF, 0xDB, 0xFF, 0x00, 0xF1, 0x55, 0xAD, 0xE0, 0x6F, 0xD9, 0x87,
+	0xE0, 0x17, 0xC3, 0x4F, 0x10, 0xC5, 0xE2, 0xCF, 0x02, 0x7C, 0x2F, 0xD3, 0x74, 0xCD, 0x42, 0x15,
+	0x75, 0x8E, 0xEA, 0xD8, 0x3E, 0xE5, 0x0D, 0xD7, 0xAB, 0x11, 0xFA, 0x51, 0x45, 0x00, 0x75, 0x1E,
+	0x33, 0xF0, 0x5F, 0x85, 0x7E, 0x22, 0x78, 0x66, 0xEB, 0xC1, 0xBE, 0x36, 0xD0, 0xE0, 0xD4, 0xB4,
+	0xBB, 0xE5, 0x55, 0xBB, 0xB1, 0xB9, 0x5C, 0xC7, 0x28, 0x56, 0x0C, 0x01, 0xFA, 0x32, 0x83, 0xF8,
+	0x57, 0x02, 0x7F, 0x62, 0x8F, 0xD9, 0x4C, 0x9C, 0x9F, 0x81, 0xDA, 0x1F, 0xFD, 0xFA, 0x6F, 0xFE,
+	0x2A, 0x8A, 0x28, 0x00, 0xFF, 0x00, 0x86, 0x27, 0xFD, 0x94, 0xFF, 0x00, 0xE8, 0x87, 0x68, 0x9F,
+	0xF7, 0xED, 0xFF, 0x00, 0xF8, 0xAA, 0x3F, 0xE1, 0x89, 0xFF, 0x00, 0x65, 0x3F, 0xFA, 0x21, 0xDA,
+	0x27, 0xFD, 0xFB, 0x7F, 0xFE, 0x2A, 0x8A, 0x28, 0x00, 0xFF, 0x00, 0x86, 0x27, 0xFD, 0x94, 0xFF,
+	0x00, 0xE8, 0x87, 0x68, 0x9F, 0xF7, 0xED, 0xFF, 0x00, 0xF8, 0xAA, 0xB9, 0xE1, 0xAF, 0xD9, 0x27,
+	0xF6, 0x6F, 0xF0, 0x77, 0x88, 0x2D, 0x7C, 0x55, 0xE1, 0x7F, 0x84, 0x7A, 0x5D, 0x8E, 0xA1, 0x63,
+	0x70, 0xB3, 0xDA, 0xDD, 0x5B, 0x87, 0x0D, 0x1C, 0x8B, 0xD1, 0x87, 0xCD, 0x45, 0x14, 0x01, 0xDF,
+	0xEA, 0x9A, 0x6D, 0x8E, 0xB5, 0xA6, 0xDC, 0x68, 0xFA, 0xA5, 0xBA, 0xCD, 0x6D, 0x77, 0x03, 0xC3,
+	0x71, 0x0B, 0x67, 0x0F, 0x1B, 0x29, 0x56, 0x5E, 0x3D, 0x41, 0x35, 0xE6, 0x8B, 0xFB, 0x13, 0x7E,
+	0xCA, 0x4A, 0xA1, 0x47, 0xC0, 0xFD, 0x17, 0x8E, 0x39, 0x8D, 0xCF, 0xFE, 0xCD, 0x45, 0x14, 0x00,
+	0x7F, 0xC3, 0x13, 0xFE, 0xCA, 0x7F, 0xF4, 0x43, 0xB4, 0x4F, 0xFB, 0xF6, 0xFF, 0x00, 0xFC, 0x55,
+	0x1F, 0xF0, 0xC4, 0xFF, 0x00, 0xB2, 0x9F, 0xFD, 0x10, 0xED, 0x13, 0xFE, 0xFD, 0xBF, 0xFF, 0x00,
+	0x15, 0x45, 0x14, 0x00, 0x7F, 0xC3, 0x13, 0xFE, 0xCA, 0x7F, 0xF4, 0x43, 0xB4, 0x4F, 0xFB, 0xF6,
+	0xFF, 0x00, 0xFC, 0x55, 0x6D, 0x78, 0x03, 0xF6, 0x6B, 0xF8, 0x17, 0xF0, 0xB3, 0xC4, 0x1F, 0xF0,
+	0x95, 0x7C, 0x3C, 0xF8, 0x6D, 0xA7, 0xE9, 0x3A, 0x87, 0x92, 0xD1, 0x7D, 0xA6, 0xD3, 0x78, 0x25,
+	0x0F, 0x51, 0x82, 0xD8, 0x3F, 0x95, 0x14, 0x50, 0x06, 0xF7, 0x8F, 0xBE, 0x1E, 0x78, 0x33, 0xE2,
+	0x8F, 0x86, 0xE4, 0xF0, 0x87, 0x8F, 0xB4, 0x08, 0x75, 0x3D, 0x36, 0x66, 0x56, 0x9A, 0xCE, 0x76,
+	0x60, 0x8E, 0x47, 0x4C, 0xED, 0x23, 0x35, 0xC3, 0xFF, 0x00, 0xC3, 0x13, 0xFE, 0xCA, 0x7F, 0xF4,
+	0x43, 0xB4, 0x5F, 0xFB, 0xF6, 0xFF, 0x00, 0xFC, 0x55, 0x14, 0x50, 0x01, 0xFF, 0x00, 0x0C, 0x4F,
+	0xFB, 0x29, 0xFF, 0x00, 0xD1, 0x0E, 0xD1, 0x3F, 0xEF, 0xDB, 0xFF, 0x00, 0xF1, 0x54, 0x7F, 0xC3,
+	0x13, 0xFE, 0xCA, 0x7F, 0xF4, 0x43, 0xB4, 0x4F, 0xFB, 0xF6, 0xFF, 0x00, 0xFC, 0x55, 0x14, 0x50,
+	0x01, 0xFF, 0x00, 0x0C, 0x4F, 0xFB, 0x29, 0xFF, 0x00, 0xD1, 0x0E, 0xD1, 0x3F, 0xEF, 0xDB, 0xFF,
+	0x00, 0xF1, 0x55, 0xD6, 0x7C, 0x35, 0xF8, 0x33, 0xF0, 0xBF, 0xE0, 0xF5, 0xBD, 0xDD, 0xA7, 0xC3,
+	0x2F, 0x06, 0x5A, 0x68, 0xD1, 0xDF, 0x48, 0xAF, 0x77, 0x1D, 0x9E, 0xEC, 0x48, 0xCB, 0x9C, 0x13,
+	0x92, 0x7A, 0x64, 0xFE, 0x74, 0x51, 0x40, 0x0D, 0xF8, 0x97, 0xF0, 0x63, 0xE1, 0x77, 0xC6, 0x28,
+	0x6C, 0xED, 0xFE, 0x26, 0xF8, 0x32, 0xD7, 0x58, 0x8F, 0x4F, 0x91, 0xDE, 0xCD, 0x6E, 0xB7, 0x62,
+	0x26, 0x60, 0x03, 0x11, 0x82, 0x3A, 0xE0, 0x7E, 0x55, 0xCA, 0x8F, 0xD8, 0x9B, 0xF6, 0x52, 0x03,
+	0x03, 0xE0, 0x76, 0x8B, 0xFF, 0x00, 0x7E, 0xDF, 0xFF, 0x00, 0x8A, 0xA2, 0x8A, 0x00, 0x3F, 0xE1,
+	0x89, 0xFF, 0x00, 0x65, 0x3F, 0xFA, 0x21, 0xDA, 0x27, 0xFD, 0xFB, 0x7F, 0xFE, 0x2A, 0x8F, 0xF8,
+	0x62, 0x7F, 0xD9, 0x4F, 0xFE, 0x88, 0x76, 0x89, 0xFF, 0x00, 0x7E, 0xDF, 0xFF, 0x00, 0x8A, 0xA2,
+	0x8A, 0x00, 0x3F, 0xE1, 0x89, 0xFF, 0x00, 0x65, 0x3F, 0xFA, 0x21, 0xDA, 0x27, 0xFD, 0xFB, 0x7F,
+	0xFE, 0x2A, 0xBB, 0x8F, 0x01, 0xFC, 0x3D, 0xF0, 0x67, 0xC3, 0x0F, 0x0F, 0xAF, 0x85, 0x7C, 0x05,
+	0xA0, 0x43, 0xA6, 0xE9, 0xC9, 0x2B, 0x48, 0x96, 0x90, 0x33, 0x6C, 0x56, 0x6E, 0xA4, 0x6E, 0x27,
+	0x1F, 0x4E, 0x94, 0x51, 0x40, 0x18, 0x3E, 0x3D, 0xFD, 0x9B, 0x3E, 0x06, 0x7C, 0x51, 0xF1, 0x01,
+	0xF1, 0x4F, 0xC4, 0x1F, 0x86, 0xF6, 0x3A, 0xB6, 0xA0, 0x62, 0x11, 0xFD, 0xA2, 0xEC, 0xB9, 0x21,
+	0x40, 0xC0, 0x00, 0x6E, 0xC0, 0xFC, 0xAB, 0x15, 0x7F, 0x62, 0x6F, 0xD9, 0x45, 0x57, 0x6A, 0xFC,
+	0x0D, 0xD1, 0x30, 0x38, 0xFF, 0x00, 0x56, 0xFF, 0x00, 0xFC, 0x55, 0x14, 0x50, 0x01, 0xFF, 0x00,
+	0x0C, 0x4F, 0xFB, 0x29, 0xFF, 0x00, 0xD1, 0x0E, 0xD1, 0x3F, 0xEF, 0xDB, 0xFF, 0x00, 0xF1, 0x54,
+	0x7F, 0xC3, 0x13, 0xFE, 0xCA, 0x7F, 0xF4, 0x43, 0xB4, 0x4F, 0xFB, 0xF6, 0xFF, 0x00, 0xFC, 0x55,
+	0x14, 0x50, 0x00, 0x3F, 0x62, 0x8F, 0xD9, 0x50, 0x10, 0xC3, 0xE0, 0x7E, 0x8B, 0x95, 0x6C, 0xAF,
+	0xEE, 0xDF, 0x83, 0xFF, 0x00, 0x7D, 0x57, 0xA5, 0x69, 0x1A, 0x56, 0x9D, 0xA0, 0xE9, 0x56, 0xBA,
+	0x1E, 0x8F, 0x68, 0xB6, 0xF6, 0x96, 0x76, 0xE9, 0x05, 0xAC, 0x11, 0xFD, 0xD8, 0xE3, 0x45, 0x0A,
+	0xAA, 0x3D, 0x80, 0x00, 0x51, 0x45, 0x00, 0x70, 0x7E, 0x27, 0xFD, 0x93, 0x7F, 0x67, 0x2F, 0x1A,
+	0x6B, 0xD7, 0x9E, 0x28, 0xF1, 0x4F, 0xC2, 0x3D, 0x26, 0xFB, 0x50, 0xBF, 0x90, 0xBD, 0xE5, 0xD4,
+	0xC8, 0xDB, 0xA5, 0x62, 0x72, 0x49, 0xF9, 0xBD, 0x4D, 0x51, 0xFF, 0x00, 0x86, 0x27, 0xFD, 0x94,
+	0xFF, 0x00, 0xE8, 0x87, 0x68, 0x9F, 0xF7, 0xE9, 0xBF, 0xF8, 0xAA, 0x28, 0xA0, 0x03, 0xFE, 0x18,
+	0x9F, 0xF6, 0x53, 0xFF, 0x00, 0xA2, 0x1D, 0xA2, 0x7F, 0xDF, 0xB7, 0xFF, 0x00, 0xE2, 0xA8, 0xFF,
+	0x00, 0x86, 0x27, 0xFD, 0x94, 0xFF, 0x00, 0xE8, 0x87, 0x68, 0x9F, 0xF7, 0xED, 0xFF, 0x00, 0xF8,
+	0xAA, 0x28, 0xA0, 0x09, 0x2D, 0x3F, 0x63, 0x3F, 0xD9, 0x76, 0xC2, 0xF2, 0x2D, 0x42, 0xC7, 0xE0,
+	0xB6, 0x8F, 0x0C, 0xF0, 0xC8, 0xB2, 0x43, 0x34, 0x68, 0xEA, 0xC8, 0xCB, 0xD0, 0x82, 0x1B, 0xB5,
+	0x7A, 0x75, 0x14, 0x50, 0x07, 0x96, 0x9F, 0xD8, 0xA3, 0xF6, 0x54, 0x27, 0x2D, 0xF0, 0x43, 0x45,
+	0x63, 0xDD, 0x9A, 0x37, 0x24, 0xFF, 0x00, 0xE3, 0xD4, 0x7F, 0xC3, 0x13, 0xFE, 0xCA, 0x7F, 0xF4,
+	0x43, 0xB4, 0x4F, 0xFB, 0xF6, 0xFF, 0x00, 0xFC, 0x55, 0x14, 0x50, 0x01, 0xFF, 0x00, 0x0C, 0x4F,
+	0xFB, 0x29, 0xFF, 0x00, 0xD1, 0x0E, 0xD1, 0x3F, 0xEF, 0xDB, 0xFF, 0x00, 0xF1, 0x54, 0x7F, 0xC3,
+	0x13, 0xFE, 0xCA, 0x7F, 0xF4, 0x43, 0xB4, 0x4F, 0xFB, 0xF6, 0xFF, 0x00, 0xFC, 0x55, 0x14, 0x50,
+	0x06, 0xA7, 0x82, 0x7F, 0x65, 0xCF, 0xD9, 0xFF, 0x00, 0xE1, 0xC7, 0x8A, 0x2D, 0x7C, 0x69, 0xE0,
+	0x6F, 0x85, 0xDA, 0x76, 0x99, 0xAA, 0x59, 0xAB, 0xAD, 0xAD, 0xE5, 0xAE, 0xF0, 0xD1, 0x87, 0x56,
+	0x56, 0x1F, 0x7B, 0x1C, 0x87, 0x6E, 0xDD, 0xEB, 0xAE, 0xF1, 0x57, 0x85, 0x7C, 0x3F, 0xE3, 0x7F,
+	0x0F, 0xDD, 0x78, 0x57, 0xC5, 0x5A, 0x62, 0x5E, 0x69, 0xF7, 0xB1, 0xEC, 0xBA, 0xB5, 0x91, 0x88,
+	0x59, 0x17, 0x20, 0xE0, 0xE0, 0x83, 0xD4, 0x0E, 0xF4, 0x51, 0x40, 0x1E, 0x78, 0x9F, 0xB1, 0x2F,
+	0xEC, 0xA2, 0x88, 0x11, 0x7E, 0x06, 0xE8, 0xB8, 0x51, 0x81, 0xFB, 0xB7, 0xFF, 0x00, 0xE2, 0xA9,
+	0x7F, 0xE1, 0x89, 0xFF, 0x00, 0x65, 0x3F, 0xFA, 0x21, 0xDA, 0x27, 0xFD, 0xFB, 0x7F, 0xFE, 0x2A,
+	0x8A, 0x28, 0x00, 0xFF, 0x00, 0x86, 0x27, 0xFD, 0x94, 0xFF, 0x00, 0xE8, 0x87, 0x68, 0x9F, 0xF7,
+	0xED, 0xFF, 0x00, 0xF8, 0xAA, 0x3F, 0xE1, 0x89, 0xFF, 0x00, 0x65, 0x3F, 0xFA, 0x21, 0xDA, 0x27,
+	0xFD, 0xFB, 0x7F, 0xFE, 0x2A, 0x8A, 0x28, 0x03, 0xA2, 0xF8, 0x71, 0xF0, 0x03, 0xE0, 0xDF, 0xC2,
+	0x2D, 0x4A, 0xE7, 0x57, 0xF8, 0x6B, 0xE0, 0x1B, 0x2D, 0x1E, 0xE2, 0xF2, 0x31, 0x1D, 0xC4, 0x96,
+	0xBB, 0xFE, 0x75, 0x1D, 0x06, 0x0B, 0x11, 0xF9, 0x56, 0x87, 0xC4, 0x6F, 0x85, 0x3F, 0x0E, 0xFE,
+	0x2D, 0xE8, 0xB1, 0x78, 0x77, 0xE2, 0x47, 0x84, 0xED, 0x75, 0x6B, 0x18, 0x6E, 0xD6, 0xE6, 0x2B,
+	0x7B, 0xAC, 0xED, 0x59, 0x82, 0xB2, 0x87, 0xE0, 0x8E, 0x70, 0xEC, 0x3F, 0x1A, 0x28, 0xA0, 0x0E,
+	0x34, 0x7E, 0xC4, 0xDF, 0xB2, 0x98, 0x18, 0xFF, 0x00, 0x85, 0x1F, 0xA2, 0xFE, 0x31, 0xBF, 0xFF,
+	0x00, 0x15, 0x47, 0xFC, 0x31, 0x3F, 0xEC, 0xA7, 0xFF, 0x00, 0x44, 0x3B, 0x44, 0xFF, 0x00, 0xBF,
+	0x6F, 0xFF, 0x00, 0xC5, 0x51, 0x45, 0x00, 0x1F, 0xF0, 0xC4, 0xFF, 0x00, 0xB2, 0x9F, 0xFD, 0x10,
+	0xED, 0x13, 0xFE, 0xFD, 0xBF, 0xFF, 0x00, 0x15, 0x47, 0xFC, 0x31, 0x3F, 0xEC, 0xA7, 0xFF, 0x00,
+	0x44, 0x3B, 0x44, 0xFF, 0x00, 0xBF, 0x6F, 0xFF, 0x00, 0xC5, 0x51, 0x45, 0x00, 0x76, 0x1F, 0x0E,
+	0x7E, 0x13, 0x7C, 0x3A, 0xF8, 0x49, 0xA5, 0x4F, 0xA1, 0xFC, 0x38, 0xF0, 0xA5, 0xBE, 0x93, 0x67,
+	0x73, 0x74, 0x6E, 0x26, 0xB7, 0xB7, 0x66, 0x2A, 0x65, 0x28, 0xA8, 0x5B, 0x0C, 0x4E, 0x3E, 0x55,
+	0x51, 0xC6, 0x3A, 0x55, 0x1F, 0x88, 0xDF, 0x00, 0x7E, 0x0E, 0x7C, 0x5C, 0xD4, 0x2D, 0x75, 0x5F,
+	0x89, 0x3E, 0x01, 0xB2, 0xD5, 0xEE, 0x2C, 0xD3, 0x6D, 0xAC, 0x97, 0x5B, 0xBF, 0x76, 0x3D, 0x80,
+	0x20, 0x51, 0x45, 0x00, 0x73, 0xA3, 0xF6, 0x26, 0xFD, 0x94, 0x80, 0xC0, 0xF8, 0x1D, 0xA2, 0xFF,
+	0x00, 0xDF, 0xB7, 0xFF, 0x00, 0xE2, 0xA8, 0xFF, 0x00, 0x86, 0x27, 0xFD, 0x94, 0xFF, 0x00, 0xE8,
+	0x87, 0x68, 0x9F, 0xF7, 0xED, 0xFF, 0x00, 0xF8, 0xAA, 0x28, 0xA0, 0x03, 0xFE, 0x18, 0x9F, 0xF6,
+	0x53, 0xFF, 0x00, 0xA2, 0x1D, 0xA2, 0x7F, 0xDF, 0xB7, 0xFF, 0x00, 0xE2, 0xA8, 0xFF, 0x00, 0x86,
+	0x27, 0xFD, 0x94, 0xFF, 0x00, 0xE8, 0x87, 0x68, 0x9F, 0xF7, 0xED, 0xFF, 0x00, 0xF8, 0xAA, 0x28,
+	0xA0, 0x0F, 0x42, 0xF0, 0xAF, 0x85, 0x7C, 0x3F, 0xE0, 0x8F, 0x0F, 0x5A, 0xF8, 0x53, 0xC2, 0xBA,
+	0x62, 0x59, 0xE9, 0xD6, 0x31, 0xF9, 0x76, 0x96, 0xB1, 0xB1, 0x2B, 0x12, 0x67, 0x3B, 0x46, 0x49,
+	0x38, 0xE7, 0x81, 0xDB, 0xA0, 0xE2, 0xB9, 0x1F, 0x19, 0xFE, 0xCB, 0xBF, 0xB3, 0xFF, 0x00, 0xC4,
+	0x3F, 0x13, 0x5C, 0x78, 0xCB, 0xC6, 0xDF, 0x0B, 0x34, 0xCD, 0x4B, 0x54, 0xBA, 0x68, 0xDA, 0xE2,
+	0xF2, 0xE1, 0x58, 0xB3, 0x98, 0xD7, 0x6A, 0x67, 0x0D, 0x8E, 0x07, 0x1D, 0x28, 0xA2, 0x80, 0x32,
+	0xC7, 0xEC, 0x4F, 0xFB, 0x29, 0x0E, 0x07, 0xC0, 0xDD, 0x0F, 0xFE, 0xFD, 0x37, 0xFF, 0x00, 0x15,
+	0x47, 0xFC, 0x31, 0x3F, 0xEC, 0xA7, 0xFF, 0x00, 0x44, 0x3B, 0x44, 0xFF, 0x00, 0xBF, 0x6F, 0xFF,
+	0x00, 0xC5, 0x51, 0x45, 0x00, 0x1F, 0xF0, 0xC4, 0xFF, 0x00, 0xB2, 0x9F, 0xFD, 0x10, 0xED, 0x13,
+	0xFE, 0xFD, 0xBF, 0xFF, 0x00, 0x15, 0x40, 0xFD, 0x8A, 0x7F, 0x65, 0x50, 0xDB, 0x97, 0xE0, 0x8E,
+	0x8A, 0xA4, 0x00, 0x01, 0x54, 0x71, 0x8C, 0x36, 0xE1, 0xD1, 0xBA, 0xE7, 0x9C, 0xD1, 0x45, 0x00,
+	0x7A, 0x84, 0x70, 0xC7, 0x14, 0x2B, 0x6E, 0xAB, 0xF2, 0x2A, 0xED, 0x0A, 0xDC, 0xF1, 0x8F, 0x7E,
+	0xB5, 0xE7, 0x1A, 0xCF, 0xEC, 0x7F, 0xFB, 0x32, 0xF8, 0x87, 0x58, 0xBA, 0xD7, 0xF5, 0xAF, 0x83,
+	0x3A, 0x35, 0xC5, 0xE5, 0xF5, 0xCC, 0x97, 0x17, 0x77, 0x0F, 0x13, 0x6E, 0x92, 0x47, 0x62, 0xCC,
+	0xC7, 0x0D, 0xD4, 0x92, 0x4D, 0x14, 0x50, 0x05, 0x6F, 0xF8, 0x62, 0x7F, 0xD9, 0x4F, 0xFE, 0x88,
+	0x76, 0x89, 0xFF, 0x00, 0x7E, 0xDF, 0xFF, 0x00, 0x8A, 0xA3, 0xFE, 0x18, 0x9F, 0xF6, 0x53, 0xFF,
+	0x00, 0xA2, 0x1D, 0xA2, 0x7F, 0xDF, 0xB7, 0xFF, 0x00, 0xE2, 0xA8, 0xA2, 0x80, 0x0F, 0xF8, 0x62,
+	0x7F, 0xD9, 0x4F, 0xFE, 0x88, 0x76, 0x89, 0xFF, 0x00, 0x7E, 0xDF, 0xFF, 0x00, 0x8A, 0xAB, 0x9E,
+	0x1A, 0xFD, 0x92, 0x7F, 0x66, 0xFF, 0x00, 0x07, 0x78, 0x82, 0xD7, 0xC5, 0x5E, 0x17, 0xF8, 0x47,
+	0xA5, 0xD8, 0xEA, 0x16, 0x37, 0x0B, 0x3D, 0xAD, 0xD5, 0xB8, 0x70, 0xD1, 0xC8, 0xBD, 0x18, 0x7C,
+	0xD4, 0x51, 0x40, 0x1D, 0xFE, 0xA9, 0xA6, 0xD8, 0xEB, 0x5A, 0x6D, 0xC6, 0x8F, 0xAA, 0x5B, 0xAC,
+	0xD6, 0xD7, 0x70, 0x3C, 0x37, 0x10, 0xB6, 0x70, 0xF1, 0xB2, 0x95, 0x65, 0xE3, 0xD4, 0x13, 0x5E,
+	0x68, 0xBF, 0xB1, 0x37, 0xEC, 0xA4, 0xAA, 0x14, 0x7C, 0x0F, 0xD1, 0x78, 0xE3, 0x98, 0xDC, 0xFF,
+	0x00, 0xEC, 0xD4, 0x51, 0x40, 0x07, 0xFC, 0x31, 0x3F, 0xEC, 0xA7, 0xFF, 0x00, 0x44, 0x3B, 0x44,
+	0xFF, 0x00, 0xBF, 0x6F, 0xFF, 0x00, 0xC5, 0x51, 0xFF, 0x00, 0x0C, 0x4F, 0xFB, 0x29, 0xFF, 0x00,
+	0xD1, 0x0E, 0xD1, 0x3F, 0xEF, 0xDB, 0xFF, 0x00, 0xF1, 0x54, 0x51, 0x40, 0x07, 0xFC, 0x31, 0x3F,
+	0xEC, 0xA7, 0xFF, 0x00, 0x44, 0x3B, 0x44, 0xFF, 0x00, 0xBF, 0x6F, 0xFF, 0x00, 0xC5, 0x56, 0xCF,
+	0x80, 0x7F, 0x66, 0xAF, 0x81, 0x5F, 0x0B, 0xB5, 0xFF, 0x00, 0xF8, 0x4A, 0x7E, 0x1F, 0x7C, 0x35,
+	0xD3, 0xF4, 0x9B, 0xFF, 0x00, 0x25, 0xA2, 0xFB, 0x45, 0xAE, 0xF0, 0x4A, 0x1E, 0xA3, 0x05, 0x88,
+	0x3F, 0x95, 0x14, 0x50, 0x06, 0xFF, 0x00, 0x8F, 0x7E, 0x1D, 0x78, 0x2B, 0xE2, 0x7F, 0x87, 0x26,
+	0xF0, 0x8F, 0x8F, 0x7C, 0x3D, 0x0E, 0xA5, 0xA6, 0xDC, 0x3A, 0xB4, 0xD6, 0x73, 0x33, 0x05, 0x90,
+	0x8E, 0x99, 0xDA, 0x46, 0x6B, 0x87, 0xFF, 0x00, 0x86, 0x27, 0xFD, 0x94, 0xFF, 0x00, 0xE8, 0x87,
+	0x68, 0xBF, 0xF7, 0xED, 0xFF, 0x00, 0xF8, 0xAA, 0x28, 0xA0, 0x03, 0xFE, 0x18, 0x9F, 0xF6, 0x53,
+	0xFF, 0x00, 0xA2, 0x1D, 0xA2, 0x7F, 0xDF, 0xB7, 0xFF, 0x00, 0xE2, 0xA8, 0xFF, 0x00, 0x86, 0x27,
+	0xFD, 0x94, 0xFF, 0x00, 0xE8, 0x87, 0x68, 0x9F, 0xF7, 0xED, 0xFF, 0x00, 0xF8, 0xAA, 0x28, 0xA0,
+	0x03, 0xFE, 0x18, 0x9F, 0xF6, 0x53, 0xFF, 0x00, 0xA2, 0x1D, 0xA2, 0x7F, 0xDF, 0xB7, 0xFF, 0x00,
+	0xE2, 0xAB, 0xA9, 0xF8, 0x73, 0xF0, 0x4F, 0xE1, 0x4F, 0xC2, 0x38, 0x2E, 0xED, 0x7E, 0x1B, 0xF8,
+	0x1A, 0xC7, 0x49, 0x8E, 0xF9, 0x95, 0xAE, 0xD2, 0xD5, 0x4E, 0x24, 0x23, 0x38, 0xCE, 0x49, 0xF5,
+	0xA2, 0x8A, 0x00, 0x4F, 0x89, 0x1F, 0x04, 0x3E, 0x14, 0x7C, 0x5F, 0x36, 0xA7, 0xE2, 0x5F, 0x82,
+	0x6D, 0x75, 0x8F, 0xB1, 0x31, 0x36, 0xAB, 0x74, 0xCF, 0x88, 0xC9, 0xEA, 0x40, 0x0C, 0x06, 0x4D,
+	0x72, 0xE3, 0xF6, 0x26, 0xFD, 0x94, 0x80, 0xC0, 0xF8, 0x1D, 0xA2, 0xFF, 0x00, 0xDF, 0xB7, 0xFF,
+	0x00, 0xE2, 0xA8, 0xA2, 0x80, 0x0F, 0xF8, 0x62, 0x7F, 0xD9, 0x4F, 0xFE, 0x88, 0x76, 0x89, 0xFF,
+	0x00, 0x7E, 0xDF, 0xFF, 0x00, 0x8A, 0xA3, 0xFE, 0x18, 0x9F, 0xF6, 0x53, 0xFF, 0x00, 0xA2, 0x1D,
+	0xA2, 0x7F, 0xDF, 0xB7, 0xFF, 0x00, 0xE2, 0xA8, 0xA2, 0x80, 0x0F, 0xF8, 0x62, 0x7F, 0xD9, 0x4F,
+	0xFE, 0x88, 0x76, 0x89, 0xFF, 0x00, 0x7E, 0xDF, 0xFF, 0x00, 0x8A, 0xAE, 0xE3, 0xC0, 0x9F, 0x0E,
+	0xFC, 0x15, 0xF0, 0xCB, 0x40, 0x4F, 0x0B, 0x78, 0x0F, 0xC3, 0xD0, 0xE9, 0xBA, 0x7C, 0x73, 0x34,
+	0xB1, 0xDA, 0xC2, 0x58, 0xAA, 0x33, 0x75, 0x23, 0x71, 0x38, 0xFA, 0x0E, 0x28, 0xA2, 0x80, 0x30,
+	0x7C, 0x79, 0xFB, 0x35, 0xFC, 0x0B, 0xF8, 0x9F, 0xAF, 0xFF, 0x00, 0xC2, 0x51, 0xF1, 0x03, 0xE1,
+	0xBD, 0x86, 0xAB, 0x7F, 0xE5, 0x08, 0xFE, 0xD1, 0x74, 0x5C, 0x90, 0x80, 0x60, 0x00, 0x03, 0x60,
+	0x71, 0xE8, 0x2B, 0x15, 0x7F, 0x62, 0x6F, 0xD9, 0x45, 0x57, 0x6A, 0xFC, 0x0D, 0xD1, 0x30, 0x38,
+	0xFF, 0x00, 0x56, 0xFF, 0x00, 0xFC, 0x55, 0x14, 0x50, 0x01, 0xFF, 0x00, 0x0C, 0x4F, 0xFB, 0x29,
+	0xFF, 0x00, 0xD1, 0x0E, 0xD1, 0x3F, 0xEF, 0xDB, 0xFF, 0x00, 0xF1, 0x54, 0x7F, 0xC3, 0x13, 0xFE,
+	0xCA, 0x7F, 0xF4, 0x43, 0xB4, 0x4F, 0xFB, 0xF6, 0xFF, 0x00, 0xFC, 0x55, 0x14, 0x50, 0x00, 0x3F,
+	0x62, 0x8F, 0xD9, 0x50, 0x10, 0xC3, 0xE0, 0x7E, 0x8B, 0x95, 0x6C, 0xAF, 0xEE, 0xDF, 0x83, 0xFF,
+	0x00, 0x7D, 0x57, 0xA5, 0x69, 0x1A, 0x56, 0x9D, 0xA0, 0xE9, 0x56, 0xBA, 0x1E, 0x8F, 0x68, 0xB6,
+	0xF6, 0x96, 0x76, 0xE9, 0x05, 0xAC, 0x11, 0xFD, 0xD8, 0xE3, 0x45, 0x0A, 0xAA, 0x3D, 0x80, 0x00,
+	0x51, 0x45, 0x00, 0x70, 0x7E, 0x27, 0xFD, 0x93, 0x7F, 0x67, 0x2F, 0x1A, 0x6B, 0xD7, 0x9E, 0x28,
+	0xF1, 0x4F, 0xC2, 0x3D, 0x26, 0xFB, 0x50, 0xBF, 0x90, 0xBD, 0xE5, 0xD4, 0xC8, 0xDB, 0xA5, 0x62,
+	0x72, 0x49, 0xF9, 0xBD, 0x4D, 0x51, 0xFF, 0x00, 0x86, 0x27, 0xFD, 0x94, 0xFF, 0x00, 0xE8, 0x87,
+	0x68, 0x9F, 0xF7, 0xE9, 0xBF, 0xF8, 0xAA, 0x28, 0xA0, 0x03, 0xFE, 0x18, 0x9F, 0xF6, 0x53, 0xFF,
+	0x00, 0xA2, 0x1D, 0xA2, 0x7F, 0xDF, 0xB7, 0xFF, 0x00, 0xE2, 0xA8, 0xFF, 0x00, 0x86, 0x27, 0xFD,
+	0x94, 0xFF, 0x00, 0xE8, 0x87, 0x68, 0x9F, 0xF7, 0xED, 0xFF, 0x00, 0xF8, 0xAA, 0x28, 0xA0, 0x00,
+	0xFE, 0xC5, 0x1F, 0xB2, 0x90, 0xE4, 0xFC, 0x0F, 0xD0, 0xFF, 0x00, 0xEF, 0xDB, 0x7F, 0xF1, 0x55,
+	0xD7, 0x7C, 0x39, 0xF8, 0x41, 0xF0, 0xCF, 0xE1, 0x15, 0x8D, 0xD6, 0x9D, 0xF0, 0xD3, 0xC1, 0xB6,
+	0x7A, 0x3C, 0x17, 0x92, 0xAC, 0x97, 0x51, 0xD9, 0xA9, 0x02, 0x46, 0x03, 0x00, 0x9C, 0x93, 0xDA,
+	0x8A, 0x28, 0x03, 0x37, 0xE2, 0x07, 0xEC, 0xE3, 0xF0, 0x37, 0xE2, 0xA6, 0xB8, 0x3C, 0x4D, 0xF1,
+	0x0F, 0xE1, 0x9E, 0x99, 0xAB, 0x6A, 0x0B, 0x08, 0x85, 0x6E, 0xAE, 0xE3, 0x25, 0xC2, 0x0E, 0x8B,
+	0x90, 0x47, 0x15, 0x87, 0xFF, 0x00, 0x0C, 0x4F, 0xFB, 0x29, 0xFF, 0x00, 0xD1, 0x0E, 0xD1, 0x3F,
+	0xEF, 0xDB, 0xFF, 0x00, 0xF1, 0x54, 0x51, 0x40, 0x07, 0xFC, 0x31, 0x3F, 0xEC, 0xA7, 0xFF, 0x00,
+	0x44, 0x3B, 0x44, 0xFF, 0x00, 0xBF, 0x6F, 0xFF, 0x00, 0xC5, 0x51, 0xFF, 0x00, 0x0C, 0x4F, 0xFB,
+	0x29, 0xFF, 0x00, 0xD1, 0x0E, 0xD1, 0x3F, 0xEF, 0xDB, 0xFF, 0x00, 0xF1, 0x54, 0x51, 0x40, 0x08,
+	0xFF, 0x00, 0xB1, 0x37, 0xEC, 0xA2, 0x54, 0xAB, 0xFC, 0x0F, 0xD1, 0x30, 0xDC, 0x7F, 0xAB, 0x7F,
+	0xFE, 0x2A, 0xBA, 0xDF, 0x86, 0xFF, 0x00, 0x06, 0xFE, 0x18, 0xFC, 0x20, 0xB6, 0xBB, 0xB3, 0xF8,
+	0x69, 0xE0, 0xEB, 0x5D, 0x1E, 0x2B, 0xE9, 0x15, 0xEE, 0xE3, 0xB5, 0xDD, 0x89, 0x19, 0x41, 0x0A,
+	0x70, 0x49, 0xE8, 0x09, 0xE9, 0x45, 0x14, 0x01, 0x9F, 0xF1, 0x03, 0xF6, 0x71, 0xF8, 0x1B, 0xF1,
+	0x53, 0x5C, 0x1E, 0x26, 0xF8, 0x87, 0xF0, 0xCF, 0x4C, 0xD5, 0xB5, 0x05, 0x84, 0x42, 0xB7, 0x57,
+	0x71, 0x92, 0xE1, 0x07, 0x45, 0xC8, 0x23, 0x8A, 0xC3, 0xFF, 0x00, 0x86, 0x27, 0xFD, 0x94, 0xFF,
+	0x00, 0xE8, 0x87, 0x68, 0x9F, 0xF7, 0xED, 0xFF, 0x00, 0xF8, 0xAA, 0x28, 0xA0, 0x03, 0xFE, 0x18,
+	0x9F, 0xF6, 0x53, 0xFF, 0x00, 0xA2, 0x1D, 0xA2, 0x7F, 0xDF, 0xB7, 0xFF, 0x00, 0xE2, 0xA8, 0xFF,
+	0x00, 0x86, 0x27, 0xFD, 0x94, 0xFF, 0x00, 0xE8, 0x87, 0x68, 0x9F, 0xF7, 0xED, 0xFF, 0x00, 0xF8,
+	0xAA, 0x28, 0xA0, 0x01, 0xBF, 0x62, 0x5F, 0xD9, 0x49, 0x94, 0xAB, 0x7C, 0x0E, 0xD1, 0x30, 0x46,
+	0x0F, 0xEE, 0xDF, 0xFF, 0x00, 0x8A, 0xAE, 0xB3, 0xE1, 0xB7, 0xC1, 0xBF, 0x86, 0x3F, 0x07, 0xED,
+	0xEE, 0xED, 0x3E, 0x19, 0xF8, 0x3A, 0xD7, 0x47, 0x8A, 0xFA, 0x45, 0x7B, 0xA8, 0xED, 0x77, 0x62,
+	0x46, 0x50, 0x42, 0x9E, 0x49, 0xE8, 0x09, 0xE9, 0x45, 0x14, 0x01, 0xD3, 0x51, 0x45, 0x14, 0x01,
+	0xFF, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46,
+	0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60, 0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x22,
+	0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D, 0x00, 0x2A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01,
+	0x01, 0x12, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xFF, 0xDB, 0x00, 0x43, 0x00, 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x02,
+	0x02, 0x02, 0x02, 0x02, 0x04, 0x03, 0x02, 0x02, 0x02, 0x02, 0x05, 0x04, 0x04, 0x03, 0x04, 0x06,
+	0x05, 0x06, 0x06, 0x06, 0x05, 0x06, 0x06, 0x06, 0x07, 0x09, 0x08, 0x06, 0x07, 0x09, 0x07, 0x06,
+	0x06, 0x08, 0x0B, 0x08, 0x09, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x06, 0x08, 0x0B, 0x0C, 0x0B, 0x0A,
+	0x0C, 0x09, 0x0A, 0x0A, 0x0A, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+	0x05, 0x03, 0x03, 0x05, 0x0A, 0x07, 0x06, 0x07, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x02,
+	0x58, 0x04, 0x00, 0x03, 0x01, 0x22, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00,
+	0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4,
+	0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00,
+	0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13,
+	0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15,
+	0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25,
+	0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46,
+	0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66,
+	0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86,
+	0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4,
+	0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2,
+	0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9,
+	0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5,
+	0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00, 0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+	0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04,
+	0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00, 0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11,
+	0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, 0x13, 0x22, 0x32, 0x81, 0x08,
+	0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A,
+	0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35,
+	0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55,
+	0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75,
+	0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93,
+	0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA,
+	0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8,
+	0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6,
+	0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00,
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+	0x00, 0x84, 0xF1, 0xAD, 0xF7, 0xF2, 0x33, 0xFE, 0xB3, 0x4E, 0xE3, 0x03, 0x77, 0x5F, 0x4F, 0x71,
+	0x40, 0x73, 0x44, 0xFD, 0x42, 0xA2, 0xBF, 0x25, 0x35, 0x3F, 0xF8, 0x38, 0xBF, 0xF6, 0x81, 0xD4,
+	0x17, 0x6F, 0x86, 0xFF, 0x00, 0x60, 0x5D, 0xAD, 0xFF, 0x00, 0x65, 0x52, 0xD7, 0xDB, 0xFB, 0xDA,
+	0x7F, 0xD6, 0xB1, 0x5F, 0xFE, 0x0B, 0xEB, 0xFB, 0x79, 0x6A, 0x73, 0xF9, 0x1A, 0x6F, 0xEC, 0x2F,
+	0xE4, 0x2B, 0x74, 0x93, 0xFE, 0x16, 0x76, 0x96, 0xD8, 0xE3, 0xD0, 0xD8, 0xFB, 0x1A, 0xAE, 0x49,
+	0x07, 0x3C, 0x4F, 0xD8, 0x5C, 0xE7, 0xA5, 0x15, 0xF8, 0xDD, 0xA8, 0xFF, 0x00, 0xC1, 0x68, 0x7F,
+	0xE0, 0xA4, 0x9A, 0xE0, 0xD9, 0xA7, 0x7E, 0xCD, 0x9F, 0xD9, 0xFF, 0x00, 0xED, 0x7F, 0xC2, 0x65,
+	0xA3, 0xCB, 0xFC, 0xEC, 0xC7, 0xA7, 0xEB, 0x58, 0xED, 0xFF, 0x00, 0x05, 0x4F, 0xFF, 0x00, 0x82,
+	0xAD, 0x3C, 0xE2, 0xEE, 0xD7, 0xC2, 0x5F, 0x63, 0xC7, 0x7F, 0xB7, 0xE8, 0x52, 0x63, 0x8C, 0x77,
+	0xB5, 0xFF, 0x00, 0x39, 0xA7, 0xC8, 0xC5, 0xCE, 0x8F, 0xDA, 0x9A, 0x33, 0x8E, 0xB5, 0xF8, 0x7D,
+	0xAC, 0x7F, 0xC1, 0x45, 0xFF, 0x00, 0xE0, 0xB2, 0x7E, 0x23, 0x9F, 0xCD, 0xD3, 0x7C, 0x7D, 0xFD,
+	0x9B, 0xED, 0xFD, 0x95, 0xE1, 0xE9, 0xBB, 0x0F, 0x5B, 0x71, 0xE8, 0x7F, 0x3F, 0x6A, 0x59, 0x7F,
+	0x6E, 0x1F, 0xF8, 0x2D, 0xCE, 0xA9, 0xA6, 0xB6, 0x9A, 0x9F, 0xB4, 0x47, 0xD9, 0x9A, 0x4C, 0x6D,
+	0x9F, 0xFE, 0x11, 0x1F, 0x0D, 0x3E, 0xCC, 0x1C, 0xF4, 0xF2, 0x79, 0xCE, 0x31, 0xF8, 0xD1, 0xC8,
+	0xC3, 0x9D, 0x1F, 0xB7, 0xE5, 0xD4, 0x72, 0x4D, 0x20, 0x96, 0x36, 0x6D, 0xA1, 0xB9, 0xAF, 0xC3,
+	0x26, 0xFD, 0xAA, 0xFF, 0x00, 0xE0, 0xB8, 0x6D, 0xFF, 0x00, 0x37, 0x6D, 0xFF, 0x00, 0x96, 0x1F,
+	0x86, 0xBF, 0xF8, 0xD5, 0x24, 0x7F, 0xB5, 0x2F, 0xFC, 0x16, 0xE3, 0x7F, 0xFA, 0x77, 0xED, 0x73,
+	0x88, 0xBF, 0x88, 0xFF, 0x00, 0xC2, 0x03, 0xE1, 0xBF, 0xE9, 0x17, 0xAD, 0x1C, 0x8C, 0x39, 0xD1,
+	0xFB, 0xA1, 0x48, 0x1D, 0x49, 0xDA, 0x0D, 0x7E, 0x15, 0x5E, 0x7E, 0xD1, 0x7F, 0xF0, 0x59, 0xAB,
+	0xDE, 0x07, 0xED, 0x95, 0xE5, 0xFF, 0x00, 0xDD, 0x3B, 0xF0, 0xE9, 0xFF, 0x00, 0xDA, 0x75, 0x9F,
+	0x1F, 0xC6, 0x0F, 0xF8, 0x2D, 0x0D, 0xDD, 0xD2, 0x8F, 0xF8, 0x6D, 0xEF, 0x5F, 0x97, 0xFE, 0x15,
+	0xAF, 0x87, 0x3D, 0x3F, 0xDC, 0xA3, 0x91, 0x87, 0x3A, 0x3F, 0x79, 0xA8, 0xAF, 0xC2, 0x2F, 0xF8,
+	0x59, 0xFF, 0x00, 0xF0, 0x5A, 0x0F, 0xFA, 0x3D, 0xBF, 0xFC, 0xC6, 0xDE, 0x1D, 0xFF, 0x00, 0xE2,
+	0x69, 0x0F, 0xC5, 0x0F, 0xF8, 0x2D, 0x00, 0x19, 0xFF, 0x00, 0x86, 0xDA, 0xFF, 0x00, 0xCC, 0x6D,
+	0xE1, 0xDF, 0xFE, 0x26, 0x8E, 0x46, 0x1C, 0xE8, 0xFD, 0xDE, 0xA2, 0xBF, 0x08, 0x3F, 0xE1, 0x69,
+	0xFF, 0x00, 0xC1, 0x68, 0x3F, 0xE8, 0xF6, 0xBF, 0xF3, 0x1B, 0xF8, 0x77, 0xFF, 0x00, 0x89, 0xA5,
+	0x5F, 0x8A, 0x7F, 0xF0, 0x59, 0xF0, 0x72, 0x7F, 0x6D, 0xAF, 0xFC, 0xC6, 0xFE, 0x1D, 0xFF, 0x00,
+	0xE2, 0x68, 0xE4, 0x61, 0xCE, 0x8F, 0xDD, 0xEA, 0x09, 0x0A, 0x32, 0x6B, 0xF0, 0x8F, 0xFE, 0x16,
+	0xAF, 0xFC, 0x16, 0x7B, 0xFE, 0x8F, 0x6B, 0xFF, 0x00, 0x31, 0xB7, 0x87, 0x7F, 0xF8, 0x9A, 0x92,
+	0xD7, 0xE3, 0x57, 0xFC, 0x16, 0x93, 0x45, 0x9D, 0x75, 0x3B, 0x7F, 0xDB, 0x53, 0xCC, 0x78, 0xFE,
+	0xEA, 0x7F, 0xC2, 0xB8, 0xF0, 0xE0, 0xCE, 0x46, 0x3A, 0xEC, 0x3E, 0xB4, 0x72, 0x30, 0xE7, 0x47,
+	0xEE, 0xB7, 0x9B, 0x1F, 0xF7, 0xA8, 0x12, 0x23, 0x1C, 0x03, 0x5F, 0x86, 0xBF, 0xF0, 0xD4, 0xFF,
+	0x00, 0xF0, 0x5B, 0x8F, 0xFA, 0x3C, 0x1F, 0xFC, 0xC7, 0xFE, 0x1B, 0xFF, 0x00, 0xE3, 0x54, 0xAB,
+	0xFB, 0x54, 0xFF, 0x00, 0xC1, 0x6E, 0xD0, 0xEE, 0x8F, 0xF6, 0xBE, 0xDC, 0xDF, 0xDD, 0xFF, 0x00,
+	0x85, 0x7F, 0xE1, 0xA1, 0xFF, 0x00, 0xB4, 0xA8, 0xE4, 0x61, 0xCE, 0x8F, 0xDC, 0x77, 0xBA, 0x82,
+	0x36, 0xDA, 0xF2, 0x73, 0xF4, 0x35, 0x20, 0x39, 0xE9, 0x5F, 0x85, 0xC7, 0xF6, 0xA4, 0xFF, 0x00,
+	0x82, 0xE1, 0x89, 0xFC, 0xD6, 0xFD, 0xAD, 0xF3, 0xED, 0xFF, 0x00, 0x08, 0x17, 0x86, 0xBD, 0x3F,
+	0xEB, 0x95, 0x6C, 0x2F, 0xED, 0xCB, 0xFF, 0x00, 0x05, 0xB7, 0xD2, 0xAC, 0x19, 0x8F, 0xED, 0x17,
+	0xF6, 0xB6, 0x4F, 0xBA, 0x9F, 0xF0, 0x88, 0xF8, 0x6E, 0x3C, 0xE4, 0xFA, 0xF9, 0x1E, 0xFF, 0x00,
+	0xA5, 0x1C, 0x8C, 0x39, 0xD1, 0xFB, 0x72, 0xCC, 0xAB, 0xCB, 0x36, 0x3E, 0xB4, 0x03, 0x91, 0x91,
+	0x5F, 0x86, 0xCD, 0xFF, 0x00, 0x05, 0x00, 0xFF, 0x00, 0x82, 0xDD, 0xC9, 0x30, 0x7B, 0xAF, 0x8C,
+	0xDE, 0x62, 0x0F, 0xE1, 0xFF, 0x00, 0x84, 0x77, 0xC3, 0x43, 0xF5, 0x10, 0x57, 0x49, 0xA7, 0xFF,
+	0x00, 0xC1, 0x4D, 0x3F, 0xE0, 0xAF, 0xD6, 0x16, 0x7E, 0x55, 0xE6, 0xA9, 0xF6, 0xA9, 0x3F, 0xBD,
+	0xE4, 0x78, 0x7E, 0x3C, 0xF3, 0xE8, 0x2D, 0xBF, 0xCE, 0x28, 0xE4, 0x63, 0xE7, 0x47, 0xED, 0x2D,
+	0x15, 0xF8, 0xC3, 0x17, 0xFC, 0x15, 0x93, 0xFE, 0x0A, 0xC1, 0xA6, 0x7F, 0xC7, 0xFF, 0x00, 0x84,
+	0xBE, 0xD9, 0xED, 0xF6, 0xFD, 0x0A, 0x3F, 0xE5, 0x6B, 0xEF, 0xFA, 0x55, 0xAB, 0x6F, 0xF8, 0x2D,
+	0x17, 0xFC, 0x14, 0xBE, 0xD1, 0xD7, 0xED, 0x7F, 0xB3, 0xBF, 0xDB, 0x47, 0x78, 0xFF, 0x00, 0xE1,
+	0x2E, 0xD1, 0xA3, 0xDD, 0xF8, 0x8B, 0x3E, 0x3F, 0xFA, 0xD4, 0x72, 0x31, 0x73, 0xA3, 0xF6, 0x52,
+	0x8A, 0xFC, 0x77, 0x8F, 0xFE, 0x0B, 0xA9, 0xFB, 0x7E, 0x69, 0x78, 0x6D, 0x53, 0xF6, 0x28, 0xFB,
+	0x57, 0xFD, 0xD4, 0x8D, 0x2A, 0x3F, 0xE5, 0x65, 0xEE, 0x3F, 0x2A, 0xBD, 0xA3, 0xFF, 0x00, 0xC1,
+	0xC3, 0xDF, 0xB5, 0x4E, 0x99, 0xA8, 0x47, 0x2F, 0x88, 0xFF, 0x00, 0xE0, 0x9C, 0xBE, 0x75, 0xBA,
+	0xE7, 0xCD, 0x3F, 0xF0, 0xB7, 0xAC, 0x57, 0xB1, 0xC7, 0xDD, 0xB0, 0xCF, 0x52, 0x28, 0xE4, 0x61,
+	0xCE, 0x8F, 0xD7, 0xAA, 0x2B, 0xF2, 0xB2, 0xC7, 0xFE, 0x0E, 0x46, 0xF1, 0x24, 0x47, 0xFE, 0x2A,
+	0x4F, 0xD8, 0x43, 0xFB, 0x3D, 0x7B, 0xB7, 0xFC, 0x2D, 0x04, 0x9B, 0x1F, 0xF7, 0xCE, 0x9D, 0xF4,
+	0xFC, 0xEB, 0x66, 0xC3, 0xFE, 0x0E, 0x5C, 0xF8, 0x33, 0x6F, 0x22, 0xC9, 0xE2, 0xEF, 0x81, 0xFF,
+	0x00, 0xD9, 0x76, 0xEB, 0xFE, 0xBA, 0x7F, 0xF8, 0x49, 0xAE, 0x27, 0xD9, 0xE9, 0xF2, 0xA6, 0x9D,
+	0x93, 0x93, 0x81, 0xC7, 0xAF, 0xB5, 0x2E, 0x56, 0x1C, 0xE8, 0xFD, 0x3A, 0xA2, 0xBF, 0x3B, 0x7C,
+	0x3D, 0xFF, 0x00, 0x07, 0x2D, 0x7F, 0xC1, 0x3F, 0x6F, 0x58, 0x7F, 0xC2, 0x55, 0xE2, 0x8F, 0xEC,
+	0x85, 0xFE, 0x26, 0xFB, 0x16, 0xAB, 0x71, 0x8E, 0xBF, 0xDC, 0xD3, 0xBE, 0x9F, 0x9F, 0xB5, 0x77,
+	0xDE, 0x13, 0xFF, 0x00, 0x83, 0x85, 0x3F, 0xE0, 0x92, 0x5E, 0x2E, 0xD4, 0xA0, 0xD0, 0xEC, 0x3F,
+	0x6A, 0x8C, 0x5F, 0x5C, 0x6E, 0xF2, 0xED, 0x7F, 0xE1, 0x07, 0xD7, 0xB9, 0xDA, 0x0B, 0x1F, 0x98,
+	0xD8, 0x05, 0xFB, 0xA3, 0x3D, 0x6A, 0x47, 0xCD, 0x13, 0xED, 0x4A, 0x2B, 0xC2, 0x7C, 0x09, 0xFF,
+	0x00, 0x05, 0x2C, 0xFD, 0x8A, 0x7E, 0x26, 0x48, 0xB1, 0x78, 0x23, 0xE3, 0x3F, 0xDB, 0x99, 0xBE,
+	0xE8, 0xFF, 0x00, 0x84, 0x77, 0x52, 0x8F, 0xFB, 0xDF, 0xF3, 0xD2, 0xD9, 0x7F, 0xBA, 0xDF, 0x97,
+	0xD2, 0xBD, 0x87, 0xC3, 0xDE, 0x34, 0xF0, 0xEF, 0x8A, 0xA3, 0x59, 0xB4, 0x3B, 0xFF, 0x00, 0x39,
+	0x1B, 0x3B, 0x5B, 0xCA, 0x75, 0xF5, 0xFE, 0xF0, 0x1E, 0x86, 0x80, 0xE6, 0x89, 0xAB, 0x45, 0x31,
+	0x5E, 0x63, 0x26, 0xD3, 0x06, 0x17, 0xFB, 0xDB, 0xA9, 0x7C, 0xC5, 0xDD, 0xB4, 0x50, 0x50, 0xEA,
+	0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x80, 0x0A,
+	0x28, 0xA2, 0x80, 0x0A, 0x2A, 0xAE, 0xB7, 0xAD, 0xE9, 0x9E, 0x1D, 0xD3, 0x24, 0xD6, 0x75, 0x9B,
+	0x9F, 0x26, 0xDA, 0x1D, 0xBE, 0x64, 0x9B, 0x19, 0xB1, 0x96, 0x0A, 0x38, 0x50, 0x4F, 0x52, 0x3B,
+	0x57, 0xE7, 0x5F, 0xED, 0x57, 0xFF, 0x00, 0x07, 0x16, 0xFE, 0xCE, 0xFE, 0x05, 0xF1, 0x14, 0x9F,
+	0x0B, 0xFF, 0x00, 0x64, 0x9F, 0x02, 0x49, 0xF1, 0x6F, 0xC4, 0xC2, 0x35, 0xF3, 0xB4, 0xD6, 0xD4,
+	0xAE, 0xBC, 0x3E, 0x15, 0x8A, 0xC7, 0x2E, 0x16, 0x5B, 0xBB, 0x16, 0x46, 0x1E, 0x4B, 0x48, 0xD9,
+	0x24, 0x73, 0x11, 0x5C, 0x65, 0x94, 0x90, 0x0F, 0xD1, 0x97, 0xBD, 0xB6, 0x49, 0xBC, 0x86, 0x97,
+	0xE6, 0xFE, 0xEE, 0xD3, 0x5E, 0x17, 0xFB, 0x4A, 0x7F, 0xC1, 0x4B, 0xFF, 0x00, 0x63, 0x0F, 0xD9,
+	0x2B, 0x4E, 0xB8, 0xBF, 0xF8, 0xE9, 0xF1, 0x7F, 0xFB, 0x1F, 0xEC, 0xDB, 0x3C, 0xC5, 0xFF, 0x00,
+	0x84, 0x7F, 0x51, 0xB8, 0xFB, 0xC6, 0x20, 0x3F, 0xE3, 0xDE, 0xDA, 0x4F, 0xF9, 0xED, 0x1F, 0xFD,
+	0xF5, 0xEC, 0x71, 0xF9, 0x0B, 0xE3, 0x1F, 0x8C, 0x3F, 0xF0, 0x53, 0x2F, 0xDB, 0xA3, 0x54, 0x9A,
+	0xDF, 0xE2, 0x3F, 0xC7, 0x7F, 0xEC, 0x6F, 0x0E, 0xCD, 0xB7, 0x1E, 0x11, 0xFF, 0x00, 0x84, 0x5F,
+	0x46, 0xB8, 0xF2, 0xF0, 0xAB, 0xFF, 0x00, 0x2F, 0x51, 0x24, 0x52, 0x1C, 0xC9, 0x6E, 0xB2, 0xFB,
+	0x6E, 0xDB, 0xD0, 0x1C, 0xD6, 0xF0, 0x2F, 0xEC, 0x21, 0xFB, 0x30, 0xFC, 0x07, 0x91, 0xBC, 0x47,
+	0xF1, 0x15, 0xBC, 0x8B, 0x88, 0xFF, 0x00, 0xD6, 0x49, 0xFE, 0x9A, 0xD9, 0xCE, 0xE5, 0x1C, 0x45,
+	0x3B, 0x8E, 0x92, 0x2F, 0x6F, 0xEB, 0x8A, 0xE5, 0x64, 0xF3, 0x23, 0xEB, 0xEF, 0x8A, 0xBF, 0xF0,
+	0x72, 0xC7, 0xC3, 0x7D, 0x3A, 0x53, 0x1F, 0xEC, 0xF7, 0xFB, 0x3C, 0xFF, 0x00, 0xC2, 0x7F, 0x09,
+	0xFF, 0x00, 0x57, 0x75, 0xFF, 0x00, 0x09, 0x6C, 0xDA, 0x56, 0x7E, 0xE6, 0x7E, 0x5B, 0x9D, 0x3B,
+	0x3D, 0x4C, 0x83, 0xFE, 0xD9, 0xE7, 0xF8, 0x85, 0x78, 0x8F, 0x8B, 0x7F, 0xE0, 0xAF, 0x5F, 0xF0,
+	0x55, 0xEF, 0x8D, 0x96, 0x73, 0x5E, 0xFC, 0x27, 0xF0, 0xA7, 0xFC, 0x2B, 0xCB, 0x77, 0xDB, 0xB6,
+	0xE3, 0xED, 0xDA, 0x16, 0xAD, 0xE4, 0xE0, 0x81, 0xF7, 0x66, 0xB4, 0x52, 0xD9, 0x28, 0xE3, 0xDB,
+	0xCC, 0xFF, 0x00, 0x64, 0x56, 0x3D, 0x97, 0xC5, 0x4F, 0xD9, 0xB3, 0xC0, 0x31, 0x63, 0xC3, 0x5A,
+	0x57, 0xF6, 0xAA, 0x8F, 0xBB, 0x1F, 0x9F, 0x79, 0x07, 0xEA, 0xCA, 0x7F, 0xBC, 0x7F, 0x2F, 0x7A,
+	0xCB, 0xD5, 0xBF, 0x6E, 0x5F, 0x12, 0x59, 0x5C, 0x79, 0x3E, 0x0B, 0xF0, 0x3F, 0xF6, 0x5C, 0x3F,
+	0xF3, 0xD3, 0xFB, 0x49, 0x26, 0xC7, 0x03, 0xB3, 0xC1, 0x9E, 0xBB, 0xBF, 0x3F, 0x6A, 0x7E, 0xCE,
+	0x44, 0xFB, 0x58, 0x19, 0xBA, 0xCF, 0x87, 0x7F, 0xE0, 0xA8, 0x5F, 0x17, 0xD4, 0xCF, 0xF1, 0x63,
+	0xF6, 0xB6, 0xFB, 0x4C, 0x33, 0xFD, 0xEB, 0x7F, 0xF8, 0x40, 0xF4, 0x44, 0xE9, 0x8C, 0x7C, 0xD0,
+	0x95, 0x3D, 0x51, 0x0F, 0xE1, 0xF5, 0xAE, 0x7E, 0xDB, 0xFE, 0x09, 0x01, 0xE1, 0xFD, 0x77, 0x52,
+	0x8F, 0xC4, 0xBF, 0x10, 0x2C, 0x3F, 0xB5, 0xAE, 0x39, 0xDD, 0x75, 0xE6, 0xBD, 0xBF, 0x6D, 0xBF,
+	0x76, 0x3B, 0xB0, 0x3A, 0x05, 0x1D, 0x3B, 0x67, 0xB9, 0xAB, 0x1A, 0xCF, 0xED, 0x93, 0xFB, 0x44,
+	0x6B, 0x3B, 0xA2, 0x9F, 0xE2, 0x16, 0x21, 0x3D, 0x22, 0xFE, 0xC9, 0xB4, 0xE3, 0xA7, 0x7F, 0x24,
+	0x1E, 0xA2, 0xB8, 0xDD, 0x4B, 0xE2, 0x47, 0x8A, 0x35, 0xE7, 0x32, 0x78, 0x8B, 0x52, 0xFB, 0x66,
+	0xEF, 0xBD, 0xFB, 0x94, 0x8F, 0xD3, 0xFB, 0xAA, 0x3D, 0x07, 0xE5, 0x4F, 0xD9, 0xC8, 0x52, 0xA9,
+	0x0B, 0x1E, 0xCB, 0xA5, 0x7F, 0xC1, 0x35, 0xFF, 0x00, 0x67, 0x5F, 0x06, 0x5A, 0x89, 0x2E, 0xB4,
+	0x2F, 0x21, 0x97, 0xFE, 0x9E, 0xAE, 0xDB, 0xB9, 0xF4, 0xB8, 0x3F, 0xDE, 0xAE, 0xA7, 0x48, 0xF8,
+	0x33, 0xFB, 0x28, 0x78, 0x0B, 0x4F, 0x6D, 0x52, 0xEF, 0xC4, 0xBF, 0xD9, 0xED, 0x6F, 0x8F, 0xF4,
+	0x8F, 0xB1, 0xDF, 0x4B, 0xB3, 0x71, 0x23, 0xEE, 0x87, 0x39, 0xCE, 0xEC, 0x7E, 0x35, 0xF2, 0xBC,
+	0xB7, 0x99, 0x9B, 0xCD, 0x6E, 0x9F, 0xDD, 0xAA, 0xB2, 0x48, 0x4D, 0xD2, 0xDC, 0xC0, 0xFE, 0x5E,
+	0xDE, 0xD8, 0xCF, 0x6C, 0x55, 0xF2, 0x33, 0x0E, 0x63, 0xEB, 0x8F, 0xF8, 0x4D, 0x3F, 0x64, 0xAD,
+	0x1F, 0x94, 0xF8, 0x99, 0xE7, 0xE3, 0xFE, 0xA0, 0xB7, 0xEB, 0xFD, 0x0F, 0xAD, 0x37, 0xFE, 0x1A,
+	0x33, 0xF6, 0x50, 0xD2, 0x0F, 0x9C, 0x7C, 0x41, 0xB8, 0x27, 0xF1, 0x7D, 0x96, 0xFC, 0x75, 0xFF,
+	0x00, 0xB6, 0x67, 0xD6, 0xBE, 0x4C, 0x17, 0xF7, 0x59, 0xCB, 0x5C, 0x67, 0xFE, 0x00, 0x29, 0x4E,
+	0xA3, 0x2A, 0xFC, 0xC1, 0xF9, 0xFA, 0x53, 0xE4, 0x0E, 0x63, 0xEB, 0x06, 0xFD, 0xAF, 0xBF, 0x66,
+	0xF8, 0xF9, 0xD2, 0xED, 0x7E, 0xD8, 0x7F, 0xEB, 0xA5, 0xE4, 0x79, 0xFC, 0xE2, 0xFA, 0xFE, 0x55,
+	0x0B, 0x7E, 0xDA, 0x5F, 0x0E, 0x2D, 0x7F, 0x7D, 0xA6, 0x7C, 0x2B, 0xF3, 0x59, 0x7E, 0xEB, 0x7F,
+	0x6E, 0x4C, 0xBF, 0xCE, 0x1F, 0xAD, 0x7C, 0xA6, 0xDA, 0xA5, 0xE1, 0xFB, 0xB7, 0x38, 0xFF, 0x00,
+	0x80, 0x0F, 0xF0, 0xA6, 0x8B, 0xFB, 0xD9, 0x3E, 0x49, 0x2F, 0x37, 0x2F, 0xA7, 0x96, 0x2A, 0xF9,
+	0x50, 0x73, 0x1F, 0x54, 0x4F, 0xFB, 0x78, 0x78, 0x7E, 0x2F, 0xF5, 0x7F, 0x08, 0x7F, 0xF2, 0xE0,
+	0x7F, 0xFE, 0x31, 0x55, 0xCF, 0xED, 0xFB, 0xA7, 0x4A, 0xE2, 0x3B, 0x6F, 0x84, 0x5F, 0x33, 0x74,
+	0xFF, 0x00, 0x89, 0xF9, 0xFF, 0x00, 0xE3, 0x15, 0xF2, 0xFF, 0x00, 0x9C, 0x4F, 0x57, 0xFD, 0x28,
+	0x77, 0x8D, 0xC6, 0x08, 0xA3, 0x95, 0x07, 0x31, 0xF4, 0xEC, 0xDF, 0xB7, 0xC4, 0x90, 0xF3, 0x1F,
+	0xC2, 0x5F, 0xFC, 0xAF, 0x7F, 0xF6, 0x8A, 0xA5, 0x75, 0xFF, 0x00, 0x05, 0x08, 0xD5, 0xD6, 0x22,
+	0xB6, 0x9F, 0x0B, 0xBC, 0xA7, 0xFE, 0x19, 0x3F, 0xB7, 0x15, 0xB1, 0xF8, 0x1B, 0x7A, 0xF9, 0xB7,
+	0x65, 0xB1, 0x39, 0x31, 0xFF, 0x00, 0xE3, 0xC6, 0x81, 0xF6, 0x78, 0x8F, 0x9B, 0x14, 0x7B, 0x58,
+	0x74, 0x6D, 0xC6, 0x8E, 0x54, 0x1C, 0xC7, 0xD1, 0x1F, 0xF0, 0xF0, 0x9F, 0x16, 0x7F, 0xD0, 0x8D,
+	0xFF, 0x00, 0x95, 0x38, 0xFF, 0x00, 0xF9, 0x1E, 0x9B, 0x37, 0xFC, 0x14, 0x23, 0xC6, 0x46, 0x32,
+	0x2D, 0xFC, 0x1D, 0xE5, 0x3F, 0xF0, 0xC9, 0xFD, 0xA1, 0x1B, 0x63, 0xF0, 0xFB, 0x3D, 0x7C, 0xF5,
+	0xF6, 0xD9, 0x7F, 0xE7, 0xA7, 0xFE, 0x3B, 0x48, 0xF7, 0x73, 0x3A, 0xED, 0x13, 0x63, 0xFE, 0x02,
+	0x28, 0xE5, 0x41, 0xCC, 0x7D, 0x05, 0x1F, 0xFC, 0x14, 0x1B, 0xE2, 0x30, 0xE7, 0xFB, 0x1B, 0xFF,
+	0x00, 0x26, 0x21, 0xFF, 0x00, 0xE3, 0x15, 0x23, 0xFF, 0x00, 0xC1, 0x41, 0x7E, 0x23, 0x94, 0xF9,
+	0x74, 0x8D, 0xA7, 0xD7, 0xED, 0x10, 0x9C, 0x7F, 0xE4, 0x0A, 0xF9, 0xD9, 0x66, 0x9D, 0x7F, 0xE5,
+	0xE7, 0xFF, 0x00, 0x1C, 0x14, 0xE7, 0xBB, 0x94, 0xAE, 0x24, 0x7D, 0xCB, 0xFD, 0xDC, 0x63, 0x34,
+	0x72, 0xA0, 0xE6, 0x3E, 0x82, 0xFF, 0x00, 0x87, 0x81, 0xFC, 0x4C, 0xFF, 0x00, 0x9F, 0x2F, 0xFC,
+	0x89, 0x0F, 0xFF, 0x00, 0x18, 0xA4, 0x93, 0xFE, 0x0A, 0x07, 0xF1, 0x30, 0x21, 0x22, 0xCB, 0xFF,
+	0x00, 0x22, 0x43, 0xFF, 0x00, 0xC6, 0x2B, 0xE7, 0xBF, 0xB4, 0xC7, 0xFF, 0x00, 0x3C, 0x3F, 0xF1,
+	0xEA, 0x6C, 0x97, 0x51, 0x84, 0xCF, 0x91, 0xFF, 0x00, 0x8F, 0x51, 0xCA, 0x83, 0x98, 0xFA, 0x03,
+	0xFE, 0x1E, 0x0B, 0xF1, 0x3B, 0xFE, 0x7C, 0xBF, 0xF2, 0x24, 0x3F, 0xFC, 0x62, 0x81, 0xFF, 0x00,
+	0x05, 0x05, 0xF8, 0x9A, 0x78, 0x3A, 0x3F, 0x9F, 0xFF, 0x00, 0x4C, 0xBE, 0xD1, 0x0A, 0xEE, 0xFC,
+	0x7C, 0x8A, 0xF9, 0xF5, 0x6E, 0xE3, 0x6F, 0xF9, 0x61, 0xFF, 0x00, 0x8F, 0x52, 0xB4, 0xE9, 0xB7,
+	0x2B, 0x17, 0xFE, 0x3D, 0x47, 0x2A, 0x0E, 0x63, 0xE8, 0x2F, 0xF8, 0x78, 0x1F, 0xC4, 0xCF, 0xFA,
+	0x11, 0xBF, 0xF2, 0xA7, 0x0F, 0xFF, 0x00, 0x18, 0xA5, 0x4F, 0xF8, 0x28, 0x37, 0xC4, 0xA8, 0xDB,
+	0x7B, 0x78, 0x1B, 0x8F, 0xFB, 0x09, 0xC3, 0xFF, 0x00, 0xC6, 0x2B, 0xE7, 0x9F, 0x3F, 0xFD, 0x9F,
+	0xD6, 0x95, 0x66, 0x04, 0xE1, 0x93, 0xF5, 0xA3, 0x95, 0x07, 0x31, 0xF4, 0x47, 0xFC, 0x3C, 0x3F,
+	0xE2, 0x27, 0xFD, 0x08, 0xDF, 0xF9, 0x54, 0x87, 0xFF, 0x00, 0x91, 0xE9, 0xD1, 0x7F, 0xC1, 0x43,
+	0xBC, 0x7E, 0xD2, 0x01, 0x3F, 0x81, 0x7E, 0x5E, 0xFF, 0x00, 0xF1, 0x34, 0x8B, 0xFF, 0x00, 0x91,
+	0xEB, 0xE7, 0x7D, 0xF1, 0x7F, 0xCF, 0x1F, 0xFC, 0x7A, 0x94, 0x4E, 0xB1, 0x7C, 0xF1, 0xC5, 0x86,
+	0x1D, 0xF7, 0x51, 0xCA, 0x83, 0x98, 0xFA, 0x2D, 0xFF, 0x00, 0xE0, 0xA1, 0x9E, 0x2E, 0x1D, 0x7C,
+	0x0B, 0xFF, 0x00, 0x95, 0x38, 0xFF, 0x00, 0xF9, 0x1E, 0x99, 0x0F, 0xFC, 0x14, 0x23, 0xC5, 0x6F,
+	0x30, 0x59, 0x3E, 0x1E, 0xF9, 0xCB, 0xFD, 0xCF, 0xED, 0x68, 0xD7, 0x3F, 0x8F, 0xD9, 0xEB, 0xE7,
+	0x53, 0x7B, 0x39, 0x18, 0xDF, 0xFA, 0x0A, 0x6F, 0xDA, 0x26, 0x73, 0xB5, 0xDF, 0xE5, 0xEE, 0x31,
+	0x47, 0x2A, 0x0E, 0x63, 0xE9, 0x29, 0x3F, 0xE0, 0xA0, 0x3E, 0x21, 0xFF, 0x00, 0xA2, 0x4B, 0xFF,
+	0x00, 0x95, 0xE4, 0xFF, 0x00, 0xE3, 0x15, 0x09, 0xFF, 0x00, 0x82, 0x82, 0xEA, 0xF0, 0xFE, 0xF2,
+	0xF3, 0xE1, 0x2F, 0xEE, 0x87, 0xDE, 0xFF, 0x00, 0x89, 0xF2, 0xFF, 0x00, 0x48, 0x3D, 0x6B, 0xE7,
+	0x36, 0xC1, 0xE3, 0x14, 0x47, 0x1A, 0x19, 0x01, 0x71, 0xC7, 0xA5, 0x1C, 0xA8, 0x39, 0x8F, 0xA4,
+	0xA1, 0xFF, 0x00, 0x82, 0x83, 0x59, 0x49, 0xF7, 0xFE, 0x11, 0x7F, 0xE5, 0x7C, 0xFF, 0x00, 0xF1,
+	0x8A, 0xB0, 0x7F, 0x6F, 0x3D, 0x0A, 0x54, 0x3E, 0x6F, 0xC2, 0x1E, 0x3B, 0xFF, 0x00, 0xC5, 0x40,
+	0xDF, 0xFC, 0x62, 0xBE, 0x6B, 0xD9, 0x07, 0x45, 0x5F, 0xE7, 0x42, 0xC8, 0x61, 0x3E, 0x64, 0x72,
+	0x61, 0x87, 0x7C, 0x51, 0xCA, 0x83, 0x98, 0xFA, 0x5E, 0x1F, 0xDB, 0x8F, 0xC0, 0x53, 0x7F, 0xC7,
+	0xF7, 0xC2, 0x0F, 0xFC, 0xB8, 0x25, 0xFE, 0x90, 0xD5, 0xDB, 0x6F, 0xDB, 0x13, 0xE0, 0x86, 0xA8,
+	0xEB, 0x65, 0x7F, 0xF0, 0xAB, 0xC8, 0x57, 0xFB, 0xD2, 0x7F, 0x6E, 0x5C, 0xB6, 0xDC, 0x73, 0xD0,
+	0x43, 0xED, 0x5F, 0x2F, 0x7F, 0x68, 0x48, 0xDF, 0xEB, 0x1B, 0x75, 0x23, 0xDD, 0x5B, 0xE3, 0x26,
+	0xDF, 0x3F, 0xF0, 0x33, 0x47, 0x2A, 0x0E, 0x63, 0xEA, 0xC5, 0xFD, 0xA4, 0x3F, 0x66, 0xA9, 0xBF,
+	0xD7, 0x69, 0x3F, 0x65, 0xFF, 0x00, 0xB7, 0x8B, 0xC7, 0xFF, 0x00, 0xDA, 0x7F, 0xE7, 0x34, 0xE7,
+	0xF8, 0xF9, 0xFB, 0x26, 0x4C, 0xBB, 0x75, 0x1F, 0x12, 0xF9, 0x31, 0x7F, 0x1F, 0xFA, 0x1D, 0xFB,
+	0x63, 0xD3, 0xA4, 0x7E, 0xB5, 0xF2, 0x5B, 0xDF, 0x40, 0x39, 0x5B, 0x6F, 0xFC, 0x7C, 0xD4, 0x2F,
+	0x7E, 0x31, 0xF2, 0xC7, 0x8F, 0x7D, 0xD4, 0xB9, 0x43, 0x98, 0xFA, 0xBE, 0xEF, 0xC6, 0x3F, 0xB1,
+	0x4F, 0x89, 0xFF, 0x00, 0x76, 0x3C, 0x69, 0xFF, 0x00, 0x94, 0xDD, 0x4B, 0xFC, 0x07, 0xA5, 0x67,
+	0x5C, 0x7C, 0x26, 0xFD, 0x8C, 0xFC, 0x53, 0xFE, 0x87, 0x6D, 0xE2, 0x8F, 0x39, 0xA4, 0xFB, 0xB1,
+	0xFD, 0x87, 0x51, 0x5D, 0xD8, 0xE7, 0xA9, 0x71, 0xE9, 0x5F, 0x30, 0xA6, 0xA8, 0xE9, 0xD0, 0x7F,
+	0x9F, 0xCA, 0xA6, 0x5D, 0x5E, 0x1B, 0x8F, 0xDC, 0x5E, 0x5A, 0xF9, 0x91, 0xB7, 0xDE, 0x5F, 0x30,
+	0x8C, 0xFE, 0x43, 0xD6, 0xA3, 0x91, 0x87, 0x31, 0xEF, 0x9A, 0xDF, 0xEC, 0x09, 0xFB, 0x33, 0x78,
+	0xCD, 0x4A, 0x69, 0xB6, 0xDE, 0x79, 0x3D, 0xB7, 0xDE, 0xAF, 0xA7, 0xAC, 0xE3, 0xFB, 0xA6, 0xB9,
+	0x5B, 0xAF, 0xF8, 0x23, 0xAF, 0x80, 0x62, 0x9B, 0xFB, 0x73, 0xC2, 0x5A, 0x0F, 0xD8, 0xEF, 0x23,
+	0xFF, 0x00, 0x51, 0x79, 0xF6, 0xA9, 0x64, 0xF2, 0xF3, 0xF2, 0x9F, 0x91, 0xEE, 0xF0, 0x72, 0x32,
+	0x39, 0x1C, 0x67, 0x35, 0xE5, 0xDE, 0x76, 0x90, 0x9F, 0xEA, 0x34, 0xED, 0x9F, 0xF6, 0xD9, 0x8D,
+	0x4B, 0x61, 0xAF, 0xCF, 0xA5, 0x5D, 0xAD, 0xF5, 0xA3, 0x6D, 0x68, 0xF3, 0xB7, 0xA7, 0x71, 0x8E,
+	0xE3, 0xDE, 0x93, 0x83, 0x1A, 0x9E, 0xA7, 0xB2, 0x78, 0x77, 0xF6, 0x7B, 0xFD, 0xBD, 0x3E, 0x0C,
+	0x38, 0x8F, 0xE0, 0xB7, 0xED, 0x29, 0xFD, 0x8E, 0xB1, 0xFD, 0xD8, 0xFF, 0x00, 0xE1, 0x0D, 0xD2,
+	0xEE, 0x3A, 0xE7, 0xBC, 0xF2, 0x37, 0xF7, 0xDF, 0xFE, 0xFA, 0xF6, 0x15, 0xDC, 0xE8, 0x5F, 0xF0,
+	0x50, 0x0F, 0xF8, 0x2C, 0xBF, 0xC1, 0xBB, 0xC8, 0x53, 0x5D, 0xF8, 0xA9, 0xFF, 0x00, 0x09, 0x95,
+	0xAD, 0xBE, 0xED, 0xDA, 0x57, 0xF6, 0x1F, 0x87, 0x74, 0xEF, 0xB4, 0x6E, 0x07, 0xFE, 0x5A, 0xAC,
+	0x0C, 0x57, 0x69, 0x70, 0xDE, 0xFB, 0x31, 0xDE, 0xBC, 0x33, 0x47, 0xFD, 0xA6, 0xBE, 0x35, 0x78,
+	0x68, 0x6C, 0xF0, 0xD7, 0x8D, 0x7E, 0xC6, 0xBF, 0xDD, 0xFE, 0xCD, 0xB6, 0x93, 0xD7, 0xFB, 0xF1,
+	0x9F, 0x53, 0xF9, 0xD7, 0x5B, 0xA0, 0xFE, 0xDC, 0x1F, 0x15, 0x2C, 0xA6, 0x49, 0xF5, 0xEF, 0xF8,
+	0x9A, 0xC8, 0xB9, 0xFF, 0x00, 0x9E, 0x10, 0x67, 0xAF, 0xF7, 0x61, 0xF4, 0xC7, 0xE5, 0xEF, 0x51,
+	0xEC, 0xE4, 0x6F, 0xED, 0x60, 0x7D, 0x1B, 0xE0, 0x4F, 0xF8, 0x38, 0xAF, 0xE3, 0xE7, 0x80, 0xEE,
+	0x57, 0x4F, 0xFD, 0xA2, 0x7F, 0x62, 0x6F, 0xEC, 0xF8, 0x7F, 0xE5, 0xA6, 0xB3, 0xFF, 0x00, 0x0B,
+	0x22, 0xD6, 0x5E, 0xCC, 0x47, 0xEE, 0xAD, 0xB4, 0xF2, 0x7A, 0xB4, 0x69, 0xF8, 0xE7, 0xD6, 0xBE,
+	0x8E, 0xF8, 0x4D, 0xFF, 0x00, 0x07, 0x07, 0xFF, 0x00, 0xC1, 0x39, 0xBE, 0x27, 0xEA, 0xB6, 0x7E,
+	0x17, 0xB9, 0xF8, 0xC2, 0x74, 0xCD, 0x66, 0xEB, 0xCC, 0xF2, 0xEC, 0xFF, 0x00, 0xB0, 0x35, 0x89,
+	0xBE, 0xEA, 0xBB, 0x9F, 0x98, 0x58, 0x2A, 0x7D, 0xC4, 0xCF, 0x27, 0xBF, 0xA8, 0xAF, 0x80, 0xE2,
+	0xFD, 0xB3, 0x7C, 0x05, 0xAF, 0x0F, 0x2B, 0xC5, 0x7F, 0x0C, 0xBE, 0xCF, 0x21, 0xFB, 0xD7, 0x1F,
+	0xDB, 0x52, 0xB7, 0xFE, 0x3A, 0x90, 0x8E, 0xC0, 0x0A, 0xCE, 0xD7, 0xF4, 0xBF, 0xD8, 0xE7, 0xE2,
+	0xBD, 0x8C, 0x96, 0x5E, 0x27, 0x93, 0xCC, 0x7B, 0x8D, 0xBF, 0xB8, 0xDB, 0xA8, 0x0C, 0xED, 0x20,
+	0xF5, 0x42, 0xBF, 0xDC, 0x06, 0x8F, 0x67, 0x20, 0xF6, 0x90, 0x3F, 0x77, 0xFC, 0x19, 0xE3, 0xCF,
+	0x0C, 0xFC, 0x42, 0xD1, 0xAD, 0xFC, 0x47, 0xE0, 0xDB, 0xF3, 0x7B, 0xA7, 0xDC, 0x6F, 0xD9, 0x75,
+	0xE4, 0xBC, 0x7F, 0x75, 0x8A, 0xFD, 0xD9, 0x02, 0xB7, 0xDE, 0x56, 0x1D, 0x3B, 0x7A, 0x1C, 0xD6,
+	0xBF, 0x98, 0x9B, 0xB6, 0x6F, 0x19, 0xF4, 0xCD, 0x7F, 0x3D, 0xBA, 0x57, 0xEC, 0x31, 0xE2, 0x5F,
+	0x85, 0x2E, 0x7E, 0x21, 0x7E, 0xC9, 0xFF, 0x00, 0x13, 0x7F, 0xE1, 0x13, 0xB9, 0x1F, 0xEA, 0xEE,
+	0x7F, 0xB1, 0x52, 0xFB, 0xD6, 0x33, 0xF2, 0xDE, 0x4E, 0xC3, 0xA3, 0xCC, 0x3A, 0x7F, 0x1F, 0xB0,
+	0x35, 0xEB, 0xBF, 0x09, 0xFF, 0x00, 0xE0, 0xB3, 0xBF, 0xF0, 0x53, 0x3F, 0xD9, 0x62, 0x31, 0x7F,
+	0xFB, 0x41, 0x7C, 0x37, 0xFF, 0x00, 0x85, 0xB9, 0xE1, 0xEB, 0x0F, 0xF8, 0xFC, 0xBE, 0xFE, 0xD8,
+	0xD1, 0xB4, 0x1C, 0x6F, 0xDE, 0x13, 0xE4, 0xB6, 0xB3, 0x91, 0xFF, 0x00, 0xD6, 0x4B, 0x1A, 0xF1,
+	0x9F, 0xF5, 0x39, 0x3C, 0x39, 0xC4, 0xF2, 0xB2, 0xEE, 0x8F, 0xDB, 0x6A, 0x2B, 0xE5, 0x9F, 0xD8,
+	0xDF, 0xFE, 0x0B, 0x03, 0xFB, 0x19, 0xFE, 0xDA, 0x16, 0xD1, 0x69, 0xDF, 0x0F, 0xFE, 0x20, 0x79,
+	0x5E, 0x20, 0x3B, 0xBE, 0xD1, 0xA1, 0xFF, 0x00, 0x64, 0xEA, 0x2D, 0xE4, 0xF3, 0x39, 0x5F, 0xDF,
+	0x49, 0x69, 0x12, 0x36, 0x63, 0x81, 0x9F, 0x8E, 0x9D, 0x3A, 0xE3, 0x3F, 0x52, 0x44, 0xCE, 0xF1,
+	0xAB, 0x49, 0x16, 0xC6, 0xFE, 0x25, 0xCE, 0x71, 0x48, 0x63, 0xA8, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2,
+	0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x09, 0x00,
+	0x64, 0x9A, 0xF9, 0x6B, 0xFE, 0x0A, 0x3D, 0xFF, 0x00, 0x05, 0x58, 0xF8, 0x1F, 0xFF, 0x00, 0x04,
+	0xEC, 0xF0, 0xAC, 0x72, 0x78, 0xA2, 0xCF, 0xFB, 0x77, 0xC5, 0x37, 0xDB, 0xBF, 0xB1, 0xFC, 0x2F,
+	0xE6, 0x5C, 0xDA, 0xFD, 0xB3, 0x63, 0xDB, 0x79, 0xBF, 0xE9, 0x29, 0x6B, 0x34, 0x71, 0xEC, 0x8A,
+	0xE4, 0x49, 0xF3, 0x63, 0x76, 0xDD, 0xA3, 0x93, 0xC7, 0x9D, 0x7F, 0xC1, 0x65, 0xBF, 0xE0, 0xB0,
+	0x7E, 0x11, 0xFF, 0x00, 0x82, 0x77, 0x78, 0x06, 0x3F, 0x02, 0xF8, 0x11, 0xBF, 0xB4, 0x3E, 0x27,
+	0x6B, 0xDB, 0xBF, 0xE1, 0x1D, 0xD2, 0x71, 0x24, 0x39, 0xF2, 0x25, 0xB2, 0x92, 0xE3, 0xF7, 0xB2,
+	0x5A, 0x4D, 0x6F, 0xFF, 0x00, 0x1E, 0xD7, 0x2C, 0xDF, 0x39, 0x1D, 0x30, 0xB9, 0x6C, 0x63, 0xF2,
+	0x97, 0xF6, 0x75, 0xFD, 0x9B, 0xBC, 0x57, 0x67, 0xAF, 0x6A, 0xFF, 0x00, 0xB5, 0x0F, 0xED, 0x65,
+	0x7B, 0xFD, 0xB3, 0xE2, 0xF7, 0xFB, 0x3F, 0x98, 0xBE, 0x5C, 0x76, 0xFE, 0x56, 0x16, 0x4B, 0x41,
+	0xFF, 0x00, 0x1E, 0x72, 0x79, 0x4D, 0x98, 0x7C, 0x9F, 0xE0, 0xE3, 0x6F, 0xA9, 0x63, 0x4D, 0x6A,
+	0xC4, 0xF6, 0x3B, 0x0F, 0x8A, 0x5E, 0x36, 0xFD, 0xB3, 0xBF, 0xE0, 0xAB, 0x5A, 0xC4, 0x9A, 0x87,
+	0xED, 0x35, 0xE2, 0x0F, 0xEC, 0xDF, 0x02, 0xAE, 0x3E, 0xCB, 0xE1, 0x0F, 0xB2, 0xE9, 0xD3, 0x63,
+	0xE5, 0x40, 0xDF, 0xE9, 0x56, 0x8B, 0x6F, 0x37, 0xFA, 0xFB, 0x48, 0xA5, 0xE7, 0xD7, 0x68, 0xF9,
+	0x41, 0xCF, 0x55, 0xE1, 0xCB, 0x8F, 0xD9, 0xEB, 0xF6, 0x78, 0xD1, 0xE1, 0xF0, 0x3F, 0xC3, 0x4D,
+	0x13, 0xFE, 0x12, 0x04, 0xB7, 0xDD, 0xBA, 0xC7, 0xED, 0x37, 0x76, 0x9F, 0x67, 0xDC, 0xC6, 0x4F,
+	0xBF, 0x2E, 0xFD, 0xDB, 0xBC, 0xC6, 0x6E, 0xBC, 0x6D, 0xC7, 0x70, 0x07, 0x0F, 0xF1, 0x8F, 0xE3,
+	0xF6, 0xA7, 0xA9, 0xA2, 0xE8, 0x7A, 0x49, 0xF2, 0x74, 0xD5, 0xFF, 0x00, 0x97, 0x3F, 0x95, 0xBF,
+	0xB8, 0xDF, 0x7C, 0xC7, 0xBB, 0xEF, 0x02, 0x7A, 0xFB, 0x74, 0xAF, 0x32, 0x9F, 0x56, 0xD4, 0xF5,
+	0x0B, 0x37, 0x79, 0x2E, 0xF6, 0xC2, 0xB8, 0xDB, 0x0F, 0x96, 0xBC, 0x73, 0xEB, 0x8C, 0xF5, 0xE6,
+	0xB7, 0xE5, 0x30, 0xE6, 0x3D, 0x77, 0xE2, 0x47, 0xED, 0x6B, 0xE3, 0xCD, 0x6A, 0x13, 0xA2, 0x8F,
+	0x1C, 0xFD, 0x8A, 0xC3, 0xFE, 0x81, 0x7F, 0xD9, 0x91, 0x49, 0x8E, 0x55, 0xBF, 0xD6, 0x79, 0x41,
+	0xBE, 0xF0, 0xDD, 0xD7, 0xBE, 0x2B, 0xCE, 0xE3, 0xD6, 0x6C, 0xF5, 0x14, 0x68, 0xB4, 0xBB, 0x5D,
+	0xB3, 0xC9, 0xD1, 0x7C, 0xC3, 0xF3, 0x63, 0xEA, 0x30, 0x38, 0xCD, 0x73, 0x5A, 0x75, 0xCC, 0xDA,
+	0x6D, 0xC7, 0xDA, 0x22, 0x9B, 0xFF, 0x00, 0x1D, 0xF6, 0xA9, 0xF5, 0x3D, 0x62, 0x5D, 0x41, 0xBC,
+	0xD9, 0x47, 0xCC, 0x3F, 0xFA, 0xDE, 0xD4, 0x72, 0xD8, 0x52, 0x96, 0x86, 0xCC, 0xB3, 0x6A, 0x76,
+	0xFF, 0x00, 0xEB, 0xED, 0xB6, 0xFF, 0x00, 0xC0, 0xD6, 0xAB, 0x49, 0xAD, 0x46, 0xDF, 0xBB, 0xCF,
+	0xCC, 0x7F, 0xCF, 0xA5, 0x61, 0xB5, 0xDB, 0x01, 0xD2, 0xA1, 0x92, 0xFD, 0xD5, 0x72, 0xB1, 0xEE,
+	0xFF, 0x00, 0x81, 0x55, 0x73, 0x18, 0x1B, 0xDF, 0xDA, 0x5E, 0xF4, 0x1D, 0x4B, 0x1C, 0x93, 0xFE,
+	0x7F, 0x2A, 0xC9, 0x02, 0x46, 0x83, 0xCE, 0x5E, 0x4F, 0xF7, 0x7F, 0x1A, 0x8E, 0x3B, 0xCB, 0x40,
+	0x9B, 0xAE, 0xEE, 0xBC, 0xA3, 0xE9, 0xE5, 0x96, 0xFE, 0x54, 0x73, 0x01, 0xAE, 0xFA, 0xAF, 0x1C,
+	0x1F, 0xF3, 0xF9, 0x54, 0x4D, 0xA9, 0xF7, 0x2D, 0xFE, 0x7F, 0x2A, 0xCB, 0x6B, 0xCB, 0x67, 0x6F,
+	0xDC, 0xDC, 0x6E, 0xFF, 0x00, 0x80, 0x91, 0x4A, 0x11, 0x0C, 0x7B, 0x84, 0xFF, 0x00, 0x37, 0xF7,
+	0x76, 0xD1, 0xCC, 0x06, 0x97, 0xF6, 0xA2, 0xFF, 0x00, 0x7B, 0xFC, 0xFE, 0x54, 0xA9, 0xA9, 0x06,
+	0x6D, 0xA0, 0xFF, 0x00, 0x9F, 0xCA, 0xB2, 0xB0, 0xDF, 0xDE, 0xA5, 0x47, 0xF2, 0x9B, 0xCC, 0x77,
+	0xE0, 0x7B, 0x51, 0xCC, 0x06, 0xC7, 0xDB, 0x3D, 0xA9, 0x52, 0xF3, 0xE6, 0xE9, 0x59, 0x5F, 0x6F,
+	0x83, 0xFE, 0x7B, 0x7F, 0xE3, 0xA6, 0x95, 0x35, 0x0B, 0x60, 0xD9, 0x69, 0xF0, 0x3F, 0xDD, 0x34,
+	0x73, 0x01, 0xAF, 0xF6, 0xCF, 0x6A, 0x3E, 0xD9, 0xED, 0x59, 0x7F, 0xDA, 0x56, 0x1F, 0xF3, 0xF9,
+	0xFF, 0x00, 0x90, 0xCF, 0xF8, 0x50, 0x75, 0x2B, 0x33, 0xF7, 0x2E, 0xB7, 0x1F, 0x4D, 0x87, 0xFC,
+	0x28, 0xE6, 0x03, 0x53, 0xED, 0x9E, 0xD4, 0x8F, 0x79, 0xF2, 0xF4, 0xAC, 0xBF, 0xED, 0x08, 0xBF,
+	0xBF, 0xFA, 0x52, 0x8B, 0xC1, 0x2F, 0xEE, 0xE2, 0x3B, 0x98, 0xF4, 0x14, 0x73, 0x01, 0xA1, 0xF6,
+	0xCF, 0x6A, 0x3E, 0xD9, 0xED, 0x59, 0xF9, 0xBB, 0xFF, 0x00, 0x9E, 0x1F, 0xF8, 0xF0, 0xA0, 0x7D,
+	0xA7, 0x3F, 0x34, 0x38, 0x1E, 0xBB, 0x85, 0x1C, 0xC0, 0x68, 0x7D, 0xB3, 0xDA, 0x91, 0xEF, 0x0E,
+	0xDE, 0x2A, 0x97, 0xEF, 0x29, 0x1F, 0xCC, 0xDB, 0x47, 0x30, 0x16, 0xBE, 0xD6, 0xDE, 0xB4, 0x8F,
+	0x76, 0x4A, 0xE0, 0x9A, 0xA7, 0xFB, 0xCA, 0x6C, 0xD2, 0x49, 0x14, 0x66, 0x40, 0xB9, 0xC7, 0x6A,
+	0x39, 0x80, 0xBC, 0x97, 0x04, 0x8C, 0x0A, 0x90, 0x5C, 0x64, 0xE3, 0x35, 0x9F, 0x03, 0x5D, 0xC9,
+	0xF3, 0x0B, 0x5F, 0xFC, 0x88, 0x2A, 0x45, 0xBC, 0x48, 0x5C, 0x79, 0xFF, 0x00, 0x2A, 0xFE, 0x74,
+	0x73, 0x01, 0x7B, 0xCD, 0xFF, 0x00, 0x6A, 0x83, 0x29, 0xEC, 0x6A, 0xAC, 0x57, 0xF6, 0xF3, 0x9C,
+	0x40, 0xFB, 0xBF, 0x02, 0x2A, 0x39, 0xF5, 0x01, 0x1B, 0x79, 0x2C, 0x9F, 0x31, 0xE9, 0xCD, 0x1C,
+	0xC0, 0x5D, 0xF3, 0x9A, 0x91, 0xE7, 0x21, 0x72, 0x6A, 0x87, 0xDB, 0x5B, 0xFB, 0x9F, 0xAD, 0x21,
+	0xBC, 0x62, 0x31, 0xB3, 0xF5, 0xA3, 0x98, 0x0B, 0x9F, 0x69, 0xF7, 0xA0, 0x5C, 0x91, 0xC8, 0x35,
+	0x4B, 0xED, 0x4D, 0xFD, 0xDA, 0x49, 0x2E, 0xD8, 0x26, 0x76, 0xD1, 0xCC, 0x05, 0xFF, 0x00, 0xB5,
+	0xB7, 0xAD, 0x28, 0xBD, 0x2B, 0xC9, 0x35, 0x95, 0xF6, 0xD6, 0xFE, 0xE7, 0xEB, 0x48, 0x6F, 0x18,
+	0x8C, 0x6C, 0xFD, 0x68, 0xE6, 0x03, 0x5B, 0xFB, 0x4B, 0xDE, 0x91, 0xF5, 0x1C, 0xAE, 0x09, 0xAC,
+	0x9F, 0xB5, 0x37, 0xF7, 0x69, 0x0D, 0xCB, 0x11, 0x8C, 0x51, 0xCC, 0x06, 0x9F, 0xDB, 0xD6, 0x83,
+	0x7C, 0x3B, 0x1A, 0xCB, 0xF3, 0x9A, 0x83, 0x39, 0x1C, 0x91, 0x47, 0x30, 0x1A, 0x2F, 0x79, 0xEF,
+	0x50, 0xB5, 0xE7, 0xA9, 0xAA, 0x46, 0xE4, 0x9F, 0xE1, 0xFD, 0x69, 0x8D, 0x31, 0xC6, 0x48, 0xA3,
+	0x98, 0x0B, 0xFF, 0x00, 0x6B, 0x5F, 0x5A, 0x65, 0xC5, 0xEE, 0xD8, 0x58, 0xA1, 0xE6, 0xA8, 0xF9,
+	0xFF, 0x00, 0xEC, 0xFE, 0xB4, 0x19, 0xF3, 0xC1, 0x4F, 0xD6, 0x8E, 0x60, 0x24, 0xFE, 0xD2, 0x9F,
+	0xD7, 0xF9, 0x53, 0xA1, 0xD4, 0xA6, 0x12, 0x02, 0xC7, 0xF9, 0x7F, 0x85, 0x41, 0xE6, 0xAF, 0xF7,
+	0x3F, 0x5A, 0x6C, 0xAE, 0x1A, 0x32, 0x02, 0xE2, 0x8E, 0x60, 0x34, 0x3F, 0xB5, 0x1B, 0xFB, 0xDF,
+	0xE7, 0xF2, 0xA5, 0x1A, 0x80, 0x94, 0xEC, 0x91, 0xF0, 0xA7, 0xDA, 0xB2, 0x30, 0xDF, 0xDE, 0xA4,
+	0x91, 0x25, 0x64, 0xDB, 0x1C, 0xBB, 0x5B, 0xFB, 0xDB, 0x73, 0x47, 0x30, 0x1B, 0x8B, 0x0C, 0x8F,
+	0xF3, 0xDB, 0xA6, 0xFF, 0x00, 0xC7, 0x1F, 0xCE, 0xAC, 0x58, 0xDE, 0xEA, 0x86, 0xE5, 0x6D, 0x67,
+	0x9F, 0xEC, 0x31, 0xB6, 0x77, 0x5D, 0xED, 0x59, 0x36, 0x71, 0x9F, 0xBB, 0xDF, 0x3D, 0x3D, 0xB3,
+	0x9A, 0xC3, 0xB5, 0xBD, 0x96, 0x04, 0xDB, 0x27, 0xEF, 0x3F, 0x4A, 0x6B, 0x34, 0x32, 0x4C, 0x24,
+	0x10, 0xE3, 0xFE, 0x04, 0x68, 0xE6, 0x1C, 0x77, 0x3A, 0xAD, 0x1F, 0xC4, 0x37, 0x1E, 0x0F, 0xD4,
+	0x7F, 0xB4, 0x3C, 0x2F, 0xAB, 0x7D, 0x8E, 0xE0, 0x7F, 0xCB, 0xE7, 0xD9, 0xC4, 0x99, 0xE0, 0x8F,
+	0xBA, 0xE0, 0x8E, 0x8C, 0x47, 0xE3, 0x9A, 0xF4, 0xAD, 0x17, 0xF6, 0xC7, 0xF1, 0x53, 0xB2, 0x69,
+	0x9E, 0x2C, 0xB0, 0xFF, 0x00, 0x84, 0x81, 0x9B, 0x3F, 0xBE, 0xF3, 0x63, 0xB4, 0xC7, 0x53, 0xD1,
+	0x21, 0xFA, 0x0F, 0xF8, 0x0F, 0xBD, 0x78, 0x82, 0x35, 0xBB, 0xFF, 0x00, 0xAE, 0xB6, 0xDD, 0xFF,
+	0x00, 0x03, 0x22, 0xAE, 0x41, 0xAA, 0xDF, 0x5A, 0xAE, 0xDD, 0x36, 0x7F, 0x27, 0xD3, 0xE5, 0x0D,
+	0x8F, 0xCC, 0x7D, 0x6A, 0x79, 0x4D, 0xF9, 0x8F, 0x64, 0xD6, 0x3E, 0x0E, 0xFE, 0xCA, 0x1F, 0xB4,
+	0x79, 0x11, 0xE8, 0xD6, 0x7F, 0xD8, 0xFA, 0xE7, 0xFC, 0xB1, 0xB3, 0xF3, 0x2F, 0xAE, 0x36, 0xF4,
+	0xCF, 0xCE, 0xCE, 0x89, 0xF7, 0x22, 0x27, 0x9F, 0x5C, 0x75, 0x1C, 0xFA, 0xAF, 0xEC, 0xF3, 0xFF,
+	0x00, 0x05, 0x72, 0xFD, 0xB8, 0x3F, 0xE0, 0x9C, 0x1A, 0xE5, 0xB7, 0xC2, 0xFF, 0x00, 0xDA, 0xCF,
+	0x4F, 0xFF, 0x00, 0x85, 0x8D, 0xE0, 0xE5, 0xDF, 0xF6, 0x2D, 0x47, 0xCE, 0xD3, 0x74, 0x7F, 0xEC,
+	0xCF, 0x96, 0x49, 0x9F, 0xF7, 0x76, 0x76, 0xB3, 0x4B, 0x3F, 0x99, 0x35, 0xCC, 0x2B, 0xCB, 0x7C,
+	0x9E, 0x56, 0x47, 0x0C, 0xC0, 0x7C, 0x8D, 0x70, 0xB6, 0x33, 0xA0, 0xB4, 0x86, 0xD7, 0xCB, 0xB5,
+	0xFE, 0x3B, 0x7F, 0x30, 0x9C, 0xF7, 0x1F, 0x37, 0x5E, 0xBC, 0xD7, 0xA5, 0xF8, 0x13, 0xE3, 0x85,
+	0xD3, 0x58, 0x2F, 0x82, 0x7E, 0x22, 0xC5, 0xFD, 0xA5, 0xA3, 0x36, 0x76, 0xC7, 0xB8, 0x43, 0xE4,
+	0xF2, 0xD2, 0x75, 0x89, 0x37, 0xB6, 0x5F, 0x6F, 0x7E, 0x31, 0xE8, 0x4D, 0x29, 0x47, 0x40, 0xE7,
+	0x3F, 0x7E, 0xBF, 0x67, 0xBF, 0xDA, 0x57, 0xE0, 0xD7, 0xED, 0x37, 0xF0, 0xBE, 0xCF, 0xE2, 0xF7,
+	0xC1, 0xAF, 0x1C, 0x26, 0xB5, 0xE1, 0xFB, 0xDF, 0x33, 0xEC, 0xFA, 0x9B, 0x69, 0xF7, 0x16, 0x81,
+	0xF6, 0x4D, 0x24, 0x0D, 0xF2, 0x5C, 0x47, 0x1B, 0xAF, 0xEF, 0x22, 0x75, 0xE5, 0x46, 0x71, 0x91,
+	0xC1, 0x04, 0xF7, 0xD5, 0xFC, 0xD8, 0xF8, 0x53, 0x5A, 0xF8, 0xD7, 0xFF, 0x00, 0x04, 0xC4, 0xF8,
+	0x92, 0xDF, 0xB4, 0x87, 0xEC, 0x5D, 0x79, 0xF6, 0xAD, 0x27, 0x5C, 0xC7, 0xDB, 0xB4, 0x9F, 0x2E,
+	0xD9, 0x3F, 0xB4, 0x7C, 0x98, 0x4D, 0xAA, 0x7E, 0xF6, 0xF8, 0x4E, 0xD0, 0xF9, 0x6F, 0x75, 0x3B,
+	0x70, 0x83, 0x76, 0x30, 0x72, 0x36, 0x91, 0xFB, 0xA5, 0xFF, 0x00, 0x04, 0xFD, 0xFD, 0xBC, 0xBE,
+	0x0E, 0x7E, 0xDF, 0x3F, 0x03, 0x34, 0xFF, 0x00, 0x8B, 0xBF, 0x07, 0xE4, 0xF2, 0x61, 0xFD, 0xEF,
+	0xF6, 0x96, 0x99, 0xB6, 0xE1, 0xBE, 0xC7, 0xFE, 0x93, 0x71, 0x0C, 0x7F, 0xBC, 0x9E, 0x08, 0x4C,
+	0x9B, 0xCD, 0xBB, 0xB7, 0xCA, 0xBF, 0x2F, 0x43, 0xD8, 0x9C, 0x0D, 0x23, 0x52, 0xFA, 0x1E, 0xF9,
+	0x45, 0x14, 0x50, 0x68, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00,
+	0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00,
+	0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00,
+	0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00,
+	0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00,
+	0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00,
+	0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00,
+	0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00,
+	0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x15, 0xE2, 0x1F, 0xB7,
+	0xF7, 0xED, 0xC9, 0xF0, 0xB7, 0xF6, 0x02, 0xFD, 0x9E, 0x75, 0x6F, 0x8F, 0x1F, 0x13, 0x49, 0x9A,
+	0x1D, 0x3F, 0xEC, 0xFE, 0x45, 0x82, 0x99, 0xD3, 0xED, 0x1B, 0xEE, 0xED, 0xED, 0xCF, 0xEF, 0x21,
+	0x86, 0x52, 0x9B, 0x4D, 0xC2, 0xB7, 0x2A, 0x73, 0xD3, 0xD4, 0x8F, 0x6F, 0xFC, 0x2B, 0xF9, 0xE2,
+	0xFF, 0x00, 0x82, 0xE1, 0xFE, 0xD6, 0x1A, 0xA7, 0xED, 0xC9, 0xFB, 0x75, 0xAF, 0xEC, 0xEB, 0xF0,
+	0xF5, 0xFC, 0xCF, 0x0C, 0xF8, 0x07, 0x3F, 0x63, 0xD5, 0xB0, 0xAB, 0xFD, 0xB5, 0xF6, 0xED, 0x32,
+	0xC2, 0xE5, 0xFF, 0x00, 0x75, 0x24, 0x51, 0x49, 0x6D, 0xE4, 0xC9, 0x03, 0x2F, 0x2E, 0xFE, 0x67,
+	0x51, 0xB4, 0x60, 0x1A, 0x51, 0x72, 0xD8, 0x4E, 0x49, 0x6E, 0x79, 0x67, 0xEC, 0xCF, 0xE0, 0xAF,
+	0x89, 0x3F, 0xB4, 0x5F, 0xC4, 0x9F, 0x11, 0xFE, 0xD8, 0x7F, 0xB5, 0x26, 0xAB, 0xF6, 0xEF, 0x13,
+	0x5E, 0x7D, 0x8F, 0xFB, 0x4F, 0x55, 0xF2, 0x21, 0x8F, 0xCE, 0xDB, 0x0C, 0xB6, 0x51, 0xFE, 0xEA,
+	0xD1, 0x92, 0x35, 0xC4, 0x71, 0x44, 0xBF, 0x2C, 0x7C, 0xE3, 0x27, 0x9C, 0xB1, 0xD9, 0xF8, 0xAF,
+	0xF1, 0x57, 0xC4, 0x3F, 0x16, 0xB5, 0xB6, 0xBC, 0xD5, 0x2E, 0x7C, 0x88, 0x6D, 0x31, 0xFD, 0x8B,
+	0x63, 0xB1, 0x1B, 0xC9, 0xDC, 0xA8, 0x26, 0xF9, 0xC2, 0xA9, 0x6C, 0x94, 0x0D, 0xF3, 0x74, 0xE8,
+	0x2B, 0x57, 0xE3, 0x3D, 0xFD, 0x97, 0x86, 0x6D, 0xF4, 0xCF, 0x83, 0x1E, 0x16, 0xD4, 0x36, 0x58,
+	0xE8, 0xBE, 0x76, 0xDD, 0x4B, 0xC9, 0x27, 0xCC, 0xF3, 0x8A, 0x4F, 0xFE, 0xAD, 0xF2, 0x46, 0x18,
+	0x95, 0xFB, 0xC7, 0x3D, 0x78, 0xE9, 0x5E, 0x7B, 0x0D, 0xC5, 0xBD, 0x85, 0xB2, 0xE9, 0xD6, 0xB1,
+	0x6D, 0xB7, 0x87, 0x3F, 0x61, 0x5D, 0xC7, 0xE4, 0xC9, 0xCB, 0xF5, 0xE4, 0xE4, 0xFA, 0xFE, 0x15,
+	0x71, 0xA7, 0x2B, 0xDC, 0xCE, 0x55, 0x23, 0xCA, 0x3C, 0x69, 0xB3, 0x1F, 0x9E, 0xE6, 0x4E, 0x7E,
+	0x9F, 0xE0, 0x69, 0x8F, 0x7A, 0x63, 0xFF, 0x00, 0x47, 0x5E, 0x86, 0xAB, 0xCF, 0x71, 0x70, 0xE7,
+	0x26, 0x7F, 0xFC, 0x74, 0x53, 0x4D, 0xD0, 0x31, 0x14, 0x68, 0xFE, 0x6F, 0xEF, 0x6E, 0xAE, 0x9F,
+	0x74, 0xE5, 0xBB, 0x2C, 0x7D, 0xA7, 0xDE, 0x9B, 0x25, 0xC1, 0x28, 0x40, 0xAA, 0xBE, 0x67, 0xB5,
+	0x43, 0xA8, 0x5F, 0xC1, 0x61, 0x66, 0xF7, 0x77, 0x2D, 0xB5, 0x17, 0x1B, 0x9B, 0x04, 0xE3, 0x27,
+	0x1D, 0xA8, 0x7C, 0xA1, 0x72, 0xCB, 0xDC, 0x71, 0x9A, 0xAD, 0x75, 0x78, 0xF0, 0xC6, 0xD2, 0xA0,
+	0xE6, 0x9B, 0x79, 0x29, 0xD3, 0xE7, 0x6B, 0x1D, 0x48, 0x79, 0x37, 0x51, 0xE3, 0xCD, 0x87, 0xEF,
+	0x6D, 0xC8, 0xC8, 0xE4, 0x70, 0x72, 0x30, 0x6A, 0xF6, 0x9F, 0xE1, 0xFD, 0x72, 0x5D, 0x46, 0x58,
+	0xC6, 0x91, 0xE6, 0x45, 0x0E, 0xDD, 0xAD, 0xF6, 0x85, 0x5F, 0x33, 0x23, 0xEB, 0xC6, 0x0F, 0xE7,
+	0x59, 0x7B, 0x48, 0x8B, 0x72, 0x39, 0x6E, 0xB4, 0xD8, 0xED, 0x04, 0xC2, 0xF7, 0xF7, 0x9F, 0xDD,
+	0xF2, 0xCF, 0xAD, 0x5B, 0xD0, 0xEF, 0x35, 0x79, 0xA3, 0xFB, 0x54, 0x36, 0x7F, 0x2A, 0xFF, 0x00,
+	0x1F, 0x98, 0xBE, 0xE3, 0xA5, 0x71, 0xD7, 0x5F, 0x15, 0x3E, 0x1E, 0xD8, 0xEB, 0x67, 0x43, 0xF0,
+	0x3E, 0x8B, 0xFF, 0x00, 0x09, 0x46, 0xB5, 0xDF, 0x4C, 0xFB, 0x44, 0xB6, 0x38, 0xF9, 0x77, 0x7F,
+	0xAC, 0x91, 0x76, 0x7D, 0xCD, 0xCD, 0xD7, 0xF8, 0x31, 0xD4, 0x8A, 0x35, 0x8F, 0x0C, 0x7C, 0x62,
+	0xD5, 0xEE, 0x96, 0xE7, 0xC4, 0x9E, 0x30, 0xFF, 0x00, 0x85, 0x75, 0x70, 0xD9, 0xF2, 0x74, 0xDF,
+	0xEC, 0xFB, 0x7D, 0x5F, 0x7F, 0x00, 0x1F, 0xDE, 0x29, 0x00, 0x60, 0x00, 0xDC, 0xFF, 0x00, 0xCF,
+	0x4C, 0x7F, 0x0D, 0x1E, 0xD2, 0x25, 0x2A, 0x72, 0x67, 0x69, 0x2C, 0x37, 0x3A, 0x84, 0xBB, 0x64,
+	0x9F, 0x0D, 0xE9, 0xB4, 0x56, 0x87, 0xFC, 0x21, 0x5E, 0x21, 0x83, 0x4D, 0x7B, 0xF4, 0xB5, 0xFD,
+	0xD2, 0xE3, 0x74, 0x9E, 0x62, 0x71, 0xCE, 0x3A, 0x67, 0xD6, 0xBC, 0xF5, 0x3C, 0x0B, 0xE0, 0x93,
+	0x0E, 0xDF, 0x1E, 0xEA, 0xFF, 0x00, 0xF0, 0x94, 0x3F, 0x76, 0xFB, 0x3C, 0x96, 0x39, 0xE7, 0xFE,
+	0x99, 0xB7, 0xFB, 0xBF, 0xF7, 0xC7, 0xB9, 0xAE, 0x7E, 0xFB, 0xE1, 0x3F, 0xEC, 0xF9, 0x75, 0x7E,
+	0x1A, 0x0F, 0x81, 0xD9, 0x1F, 0xF6, 0x33, 0x5D, 0xFA, 0x7F, 0xBF, 0x47, 0xB4, 0x89, 0x5E, 0xCA,
+	0x67, 0xAB, 0xFF, 0x00, 0x63, 0xEB, 0x1E, 0x9F, 0xFA, 0x0F, 0xF8, 0xD1, 0xFD, 0x95, 0xAC, 0x47,
+	0xF3, 0xEC, 0xDD, 0xFE, 0xCE, 0x57, 0xFC, 0x6B, 0xCA, 0x57, 0xE0, 0xE7, 0xEC, 0xF9, 0xFF, 0x00,
+	0x2D, 0x3E, 0x08, 0x6D, 0xFF, 0x00, 0xB9, 0x96, 0xEC, 0xFF, 0x00, 0xEC, 0xF5, 0x2A, 0x7C, 0x19,
+	0xFD, 0x9D, 0xD8, 0xE2, 0x0F, 0x83, 0x5F, 0x3F, 0x6F, 0xF8, 0xA8, 0xAE, 0xFF, 0x00, 0xF8, 0xBA,
+	0x3D, 0xA4, 0x43, 0xD9, 0x4C, 0xF5, 0x1F, 0xB1, 0xEB, 0x1F, 0xF3, 0xE7, 0xFF, 0x00, 0x91, 0x16,
+	0x94, 0x69, 0xBA, 0xC4, 0xFF, 0x00, 0xBA, 0x16, 0x9D, 0x7F, 0xE9, 0xA2, 0xFF, 0x00, 0x8D, 0x79,
+	0x63, 0xFC, 0x1B, 0xF8, 0x12, 0xBD, 0x3E, 0x0B, 0x67, 0xFE, 0xE6, 0x3B, 0xAF, 0xFE, 0x2E, 0x98,
+	0x3E, 0x10, 0xFC, 0x08, 0xCE, 0x1F, 0xE0, 0xBF, 0x97, 0xFE, 0xD7, 0xFC, 0x24, 0x57, 0x47, 0x1F,
+	0xF8, 0xFD, 0x1E, 0xD2, 0x21, 0xEC, 0xA6, 0x7A, 0xB7, 0xFC, 0x23, 0x9A, 0xD7, 0xFC, 0xFA, 0xFF,
+	0x00, 0xE3, 0xEB, 0xFE, 0x34, 0x1F, 0x0E, 0x6B, 0xF8, 0xFD, 0xCD, 0xAF, 0xCD, 0xDB, 0xE7, 0x4F,
+	0xF1, 0xAF, 0x2B, 0x5F, 0x83, 0xDF, 0x00, 0xCF, 0x1F, 0xF0, 0xAA, 0x7F, 0xF2, 0xBB, 0x75, 0xFF,
+	0x00, 0xC5, 0xD1, 0x37, 0xC1, 0xFF, 0x00, 0x80, 0xB0, 0x44, 0x66, 0x8F, 0xE1, 0x57, 0x23, 0xFE,
+	0xA3, 0x97, 0x5F, 0xFC, 0x5D, 0x1E, 0xD2, 0x21, 0xEC, 0xA6, 0x7A, 0x97, 0xFC, 0x23, 0x9E, 0x2C,
+	0xFF, 0x00, 0x9F, 0x5F, 0xFC, 0x7E, 0x3F, 0xF1, 0xA0, 0x68, 0x3E, 0x28, 0x84, 0xF9, 0xB3, 0x5A,
+	0xFC, 0xA3, 0xAF, 0xEF, 0x13, 0xFC, 0x6B, 0xCA, 0x17, 0xE1, 0x6F, 0xC1, 0x03, 0xC7, 0xFC, 0x2A,
+	0x9F, 0xFC, 0xAE, 0x5C, 0xFF, 0x00, 0xF1, 0x55, 0x2C, 0x1F, 0x0A, 0xBE, 0x07, 0xF9, 0x80, 0xFF,
+	0x00, 0xC2, 0xAC, 0xC7, 0xFD, 0xC7, 0x2E, 0x7F, 0xF8, 0xAA, 0x3D, 0xA4, 0x43, 0xD9, 0x4C, 0xF5,
+	0x4F, 0xB0, 0x6B, 0x5F, 0xF3, 0xE5, 0xFF, 0x00, 0x91, 0x16, 0x8F, 0xEC, 0xBD, 0x6A, 0x6F, 0xDD,
+	0x7D, 0x8F, 0xAF, 0xFD, 0x34, 0x5F, 0xF1, 0xAF, 0x32, 0xFF, 0x00, 0x85, 0x57, 0xF0, 0x3B, 0xFE,
+	0x89, 0x7F, 0xFE, 0x56, 0xEE, 0x7F, 0xF8, 0xAA, 0x3F, 0xE1, 0x55, 0x7C, 0x10, 0x3C, 0x2F, 0xC3,
+	0x1D, 0xA7, 0xD7, 0xFB, 0x6A, 0xE7, 0xFF, 0x00, 0x8A, 0xA3, 0xDA, 0x44, 0x3D, 0x94, 0xCF, 0x4D,
+	0xFF, 0x00, 0x84, 0x73, 0x5A, 0xFF, 0x00, 0x9F, 0x5F, 0xFC, 0x7D, 0x7F, 0xC6, 0x83, 0xE1, 0xBD,
+	0x69, 0xB8, 0x16, 0xDF, 0xF8, 0xFA, 0xFF, 0x00, 0x8D, 0x79, 0x97, 0xFC, 0x2A, 0x7F, 0x82, 0xDF,
+	0xF4, 0x4D, 0xFF, 0x00, 0xF2, 0xB1, 0x73, 0xFF, 0x00, 0xC5, 0xD2, 0xAF, 0xC2, 0x8F, 0x82, 0xA0,
+	0xE4, 0xFC, 0x36, 0xFF, 0x00, 0xCA, 0xC5, 0xCF, 0xFF, 0x00, 0x15, 0x47, 0xB4, 0x88, 0x7B, 0x29,
+	0x9E, 0x97, 0xFF, 0x00, 0x08, 0xB6, 0xB9, 0xFF, 0x00, 0x3E, 0xDF, 0xF8, 0xFA, 0xFF, 0x00, 0x8D,
+	0x07, 0xC3, 0xBA, 0xED, 0xBF, 0xEF, 0x97, 0x4A, 0xFB, 0x46, 0xDF, 0xF9, 0x63, 0xE7, 0xAA, 0xEE,
+	0xFC, 0x73, 0xC5, 0x79, 0xB7, 0xFC, 0x2A, 0xCF, 0x82, 0x9F, 0xF4, 0x4D, 0x3F, 0xF2, 0xB3, 0x73,
+	0xFF, 0x00, 0xC5, 0x54, 0x77, 0x9F, 0x0A, 0xBE, 0x0C, 0x35, 0xBB, 0x2C, 0x3F, 0x0D, 0xF6, 0xB7,
+	0x18, 0x6F, 0xED, 0x8B, 0x83, 0xDF, 0xFD, 0xEA, 0x3D, 0xA4, 0x43, 0xD9, 0x4C, 0xF4, 0x3B, 0x9B,
+	0x62, 0x38, 0xBD, 0xD3, 0x7E, 0xCC, 0xDE, 0x9E, 0x76, 0xFF, 0x00, 0xE5, 0xFE, 0x79, 0xA6, 0x59,
+	0x5B, 0xCE, 0x97, 0x6A, 0xD6, 0x5F, 0xBD, 0xEB, 0xF2, 0xF0, 0xB9, 0xE3, 0xD4, 0xD7, 0x2B, 0xA1,
+	0xF8, 0x27, 0xE0, 0xD6, 0x9F, 0x07, 0x97, 0x6B, 0xA0, 0xFF, 0x00, 0x66, 0xCB, 0xDA, 0x6F, 0xB5,
+	0x5C, 0x4D, 0x8E, 0x4F, 0x62, 0xDE, 0x9C, 0x7E, 0x3E, 0xD5, 0x0D, 0xD7, 0x81, 0xB5, 0x7B, 0xAB,
+	0xE5, 0x6D, 0x3F, 0xF6, 0xC4, 0xFE, 0xCD, 0xB1, 0xFF, 0x00, 0x96, 0x96, 0x1F, 0xF0, 0xAF, 0x56,
+	0x6C, 0xF1, 0xC7, 0xCE, 0x5B, 0x3F, 0x7B, 0xE6, 0xFC, 0x71, 0xDA, 0x8F, 0x69, 0x10, 0xF6, 0x53,
+	0x3A, 0x7F, 0xB1, 0x35, 0xBD, 0xEF, 0x9F, 0xAA, 0x49, 0xE4, 0x8F, 0xF7, 0x77, 0x76, 0xF6, 0xFC,
+	0x29, 0x66, 0x48, 0x24, 0xBF, 0x8E, 0xEA, 0xD2, 0xE3, 0x72, 0x2E, 0x7F, 0x84, 0x8E, 0xD8, 0xEF,
+	0x5C, 0xEE, 0xAD, 0xAC, 0xFC, 0x5E, 0xF8, 0x71, 0x34, 0xF6, 0xBF, 0x16, 0x7E, 0x0D, 0xF9, 0xBA,
+	0x04, 0x1B, 0x76, 0xF8, 0xAB, 0xFE, 0x12, 0x2B, 0x75, 0xF3, 0x33, 0x83, 0xFF, 0x00, 0x1E, 0xD0,
+	0x86, 0x71, 0x89, 0x19, 0x23, 0xF7, 0xFB, 0xDD, 0x33, 0x57, 0x3C, 0x1F, 0xE3, 0x0F, 0x01, 0xF8,
+	0xDB, 0x40, 0x8B, 0x5D, 0xF8, 0x6F, 0xAB, 0x7F, 0x68, 0x5A, 0xCB, 0xBB, 0xCE, 0x3F, 0x67, 0x96,
+	0x2F, 0x2B, 0x0E, 0xCA, 0x3F, 0xD6, 0x80, 0x4E, 0x4A, 0xB7, 0x6E, 0x31, 0xF4, 0xA3, 0xDA, 0x44,
+	0x3D, 0x9C, 0xCD, 0xCF, 0x37, 0xFD, 0xAA, 0x3C, 0xDF, 0xF6, 0xAA, 0x1B, 0x8B, 0x5B, 0xFB, 0x0B,
+	0x25, 0xB8, 0xD4, 0xED, 0x3C, 0x89, 0x9B, 0xEE, 0xC1, 0xE6, 0x06, 0xCF, 0x3C, 0xF2, 0x38, 0xE9,
+	0x83, 0x55, 0xBE, 0xDC, 0x23, 0xB8, 0x8E, 0xC2, 0xED, 0x3C, 0xBB, 0x96, 0xDD, 0xBE, 0x1C, 0xEE,
+	0xDB, 0xC6, 0x47, 0x23, 0x83, 0x91, 0xCD, 0x5D, 0xCC, 0xF6, 0x2F, 0xF9, 0xBF, 0xED, 0x52, 0x3C,
+	0xBF, 0x2F, 0xDE, 0xA8, 0x28, 0xA7, 0x66, 0x2E, 0x64, 0x49, 0xE6, 0xFF, 0x00, 0xB5, 0x47, 0x9B,
+	0xFE, 0xD5, 0x47, 0x45, 0x21, 0x92, 0x79, 0xBF, 0xED, 0x51, 0xE6, 0xFF, 0x00, 0xB5, 0x51, 0xD2,
+	0x3B, 0x6D, 0x5D, 0xD8, 0xA0, 0x09, 0x7C, 0xDF, 0xF6, 0xA9, 0x1E, 0x4C, 0xAE, 0x0B, 0x54, 0x1E,
+	0x7F, 0xFB, 0x3F, 0xAD, 0x06, 0x7C, 0x8C, 0x6D, 0xA0, 0x07, 0xEE, 0x5F, 0x5A, 0x50, 0xC0, 0xF4,
+	0x35, 0x0F, 0x99, 0xED, 0x4E, 0x8D, 0xF2, 0xF8, 0xC5, 0x00, 0x49, 0x45, 0x14, 0x50, 0x01, 0x48,
+	0xFF, 0x00, 0x76, 0x96, 0x91, 0xFE, 0xED, 0x00, 0x32, 0x8A, 0x28, 0xA0, 0x02, 0x82, 0x70, 0x33,
+	0x45, 0x23, 0xE7, 0x6F, 0x14, 0x00, 0xF4, 0x97, 0x9E, 0xB5, 0x20, 0x93, 0x1C, 0xD5, 0x65, 0x62,
+	0x29, 0xDE, 0x69, 0xC6, 0x31, 0x55, 0xEE, 0x8E, 0xEC, 0xB8, 0x97, 0x18, 0x38, 0x14, 0xDB, 0xF6,
+	0x8E, 0x7B, 0x29, 0x23, 0x9A, 0x1F, 0x31, 0x4E, 0x3E, 0x5D, 0xD8, 0xCF, 0x35, 0x59, 0x24, 0x39,
+	0xC6, 0x2A, 0x55, 0x79, 0x08, 0xF9, 0x1B, 0x69, 0xF5, 0xC7, 0x4A, 0x52, 0xB3, 0x8E, 0x81, 0x76,
+	0x77, 0x9F, 0x0C, 0xBE, 0x30, 0xDE, 0x7C, 0x32, 0xD2, 0xDB, 0x48, 0xF1, 0x34, 0x1F, 0xDB, 0x1A,
+	0x3D, 0xD6, 0x3F, 0xB6, 0xAD, 0x37, 0x0B, 0x7F, 0xB6, 0xED, 0x66, 0x68, 0x7E, 0x64, 0x46, 0x68,
+	0xF6, 0x3B, 0x03, 0xF2, 0x9F, 0x9B, 0x6E, 0x0F, 0x06, 0xB3, 0xBE, 0x14, 0x7C, 0x70, 0xF1, 0x9F,
+	0xFC, 0x11, 0xE3, 0xF6, 0xB1, 0xB6, 0xFD, 0xA4, 0x3E, 0x1D, 0xBF, 0xDB, 0xBC, 0x13, 0xE2, 0x9D,
+	0xFF, 0x00, 0xF0, 0x90, 0x69, 0xF8, 0x8E, 0x2F, 0xB4, 0x7D, 0x9A, 0xC1, 0xED, 0x60, 0xF9, 0xE5,
+	0x4B, 0x99, 0x93, 0x6C, 0xD7, 0xAC, 0xDF, 0x22, 0x2E, 0x71, 0x86, 0xCA, 0xE0, 0xAF, 0x37, 0x03,
+	0xAD, 0xB5, 0xE7, 0xDA, 0xAC, 0x57, 0xCA, 0x55, 0xFB, 0xB1, 0xFD, 0xEC, 0x71, 0x8E, 0xA6, 0xBA,
+	0x58, 0x62, 0x97, 0xE2, 0xDF, 0x84, 0x6E, 0x3E, 0x0F, 0xEA, 0xD6, 0x3F, 0x68, 0xB8, 0xD4, 0x36,
+	0xFF, 0x00, 0x66, 0xEA, 0x1E, 0x66, 0xCF, 0xB1, 0xEC, 0x93, 0xCF, 0x93, 0xE4, 0x1B, 0x44, 0x9B,
+	0xC2, 0x05, 0xF9, 0x98, 0x6D, 0xEA, 0x3D, 0x2B, 0x9B, 0xD9, 0xCC, 0x71, 0xB9, 0xFD, 0x22, 0xFC,
+	0x2E, 0xF8, 0x89, 0xE1, 0x3F, 0x8A, 0x1E, 0x0F, 0xB4, 0xF1, 0x9F, 0x81, 0xB5, 0x7F, 0xED, 0x0D,
+	0x22, 0xFB, 0xCC, 0xFB, 0x0D, 0xF7, 0x91, 0x24, 0x3E, 0x76, 0xC9, 0x1A, 0x37, 0xF9, 0x24, 0x55,
+	0x65, 0xC3, 0xAB, 0x0E, 0x40, 0xCE, 0x32, 0x38, 0xE6, 0xBA, 0x2A, 0xFC, 0x4E, 0xFF, 0x00, 0x83,
+	0x63, 0x7F, 0x6D, 0x1D, 0x43, 0xC1, 0x37, 0xB7, 0x1F, 0xF0, 0x4E, 0xAF, 0x18, 0x6A, 0x7F, 0xBA,
+	0x8F, 0x67, 0xFC, 0x20, 0x2F, 0xE4, 0x8F, 0x93, 0x23, 0x55, 0xD4, 0xEF, 0xB8, 0x48, 0x49, 0x39,
+	0x2C, 0xBF, 0xEB, 0xA6, 0xFF, 0x00, 0x73, 0xFB, 0xB5, 0xFB, 0x5B, 0x6B, 0x73, 0x0D, 0xE4, 0x0B,
+	0x71, 0x03, 0xEE, 0x56, 0xE8, 0xD8, 0x3C, 0xF3, 0x8A, 0x86, 0xAC, 0x76, 0x45, 0xE8, 0x49, 0x45,
+	0x14, 0x52, 0x28, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0x28,
+	0xA2, 0x8A, 0x00, 0x28, 0xA2, 0x8A, 0x00, 0xF1, 0x0F, 0xF8, 0x28, 0xBF, 0xED, 0x51, 0x0F, 0xEC,
+	0x5D, 0xFB, 0x20, 0xF8, 0xB3, 0xF6, 0x8B, 0x79, 0x30, 0xFA, 0x07, 0xD8, 0x7C, 0xB5, 0xDA, 0x7E,
+	0x6F, 0x3F, 0x50, 0xB6, 0xB6, 0x3F, 0xF2, 0xCA, 0x5F, 0xF9, 0xEF, 0xFD, 0xC3, 0xF8, 0x75, 0x1F,
+	0xCE, 0x17, 0xFC, 0x13, 0xEB, 0x46, 0xBB, 0xF0, 0xDD, 0xCE, 0xA3, 0xF1, 0x77, 0xC4, 0xB2, 0x79,
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+	0xB7, 0xC9, 0x9B, 0x69, 0x39, 0xC9, 0x00, 0xF0, 0x71, 0xD8, 0x63, 0x9A, 0x00, 0xFA, 0x2D, 0x35,
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+	0x6E, 0xD3, 0xE7, 0x7D, 0xFC, 0xBB, 0x9F, 0xEE, 0xF1, 0x80, 0x2B, 0xB4, 0xD3, 0x2E, 0xD2, 0xDB,
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+	0x52, 0xF3, 0x7E, 0xCF, 0x1F, 0x9F, 0x1A, 0xE7, 0xCB, 0x89, 0xE5, 0x6E, 0x5D, 0x95, 0x7E, 0xEA,
+	0x37, 0x56, 0x1F, 0x89, 0xE2, 0x80, 0x31, 0xFE, 0xD3, 0xEF, 0x47, 0xDA, 0x7D, 0xEB, 0xD0, 0xBE,
+	0x27, 0xFE, 0xCD, 0xFA, 0x97, 0x86, 0x74, 0x5D, 0x3F, 0xE2, 0x1F, 0xC2, 0xBF, 0x10, 0xFF, 0x00,
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+	0xB2, 0x2F, 0xFC, 0xB3, 0xDA, 0x7F, 0x9D, 0x57, 0x83, 0x53, 0xB6, 0xB9, 0xBB, 0xFE, 0xCB, 0xB7,
+	0x7D, 0xFA, 0x8B, 0xFF, 0x00, 0xC7, 0xBD, 0x9E, 0x08, 0xF3, 0x30, 0x32, 0xDF, 0x3E, 0x36, 0x8C,
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+	0x3A, 0x6C, 0x72, 0xF9, 0x13, 0x5C, 0xED, 0x90, 0x7D, 0xE5, 0xD8, 0xC7, 0x1F, 0xA5, 0x4A, 0x6F,
+	0xF4, 0xF7, 0x3B, 0xED, 0x2E, 0xBC, 0xD8, 0x87, 0xFA, 0xC9, 0x3C, 0xB2, 0xBB, 0x7D, 0x38, 0x3D,
+	0x79, 0xA0, 0x0B, 0xFF, 0x00, 0x69, 0xF7, 0xA0, 0xCA, 0x92, 0x7C, 0x92, 0x1F, 0x94, 0xD5, 0x18,
+	0x4D, 0xED, 0xE2, 0x97, 0xB0, 0xB2, 0xF3, 0x94, 0x7F, 0x17, 0x98, 0x17, 0xF9, 0xD5, 0x59, 0x75,
+	0x15, 0xB8, 0x0D, 0x66, 0xC3, 0xCB, 0x90, 0xFF, 0x00, 0xC0, 0xB1, 0xDE, 0x93, 0xD8, 0x0D, 0x6B,
+	0x56, 0x6D, 0x09, 0xBC, 0xA9, 0xA3, 0xFD, 0xC0, 0xFF, 0x00, 0x97, 0x5D, 0xDF, 0xFB, 0x37, 0x27,
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+	0x2D, 0x63, 0xF3, 0x3F, 0xE1, 0x1F, 0xBE, 0xF2, 0xCA, 0x7D, 0x9B, 0x32, 0x09, 0x67, 0xF9, 0x01,
+	0x05, 0xF7, 0x11, 0x8F, 0x9D, 0xB8, 0xEA, 0xBE, 0x95, 0x1C, 0x77, 0x97, 0x2F, 0x75, 0x25, 0xF5,
+	0xD4, 0xBE, 0x65, 0xC4, 0x9B, 0x71, 0x26, 0xD0, 0x31, 0x81, 0x8E, 0x83, 0x8E, 0x94, 0x59, 0xDB,
+	0x5B, 0xC0, 0xC7, 0x4F, 0xD3, 0x4F, 0xD9, 0xEC, 0x9B, 0xFE, 0x5D, 0xB9, 0x7C, 0x63, 0x9F, 0xBC,
+	0x79, 0xFB, 0xDC, 0xD4, 0x46, 0xE2, 0x92, 0x46, 0x9F, 0xC2, 0xEF, 0x1F, 0xEA, 0x1F, 0x17, 0x3C,
+	0x1B, 0x65, 0xE2, 0x2D, 0x52, 0x0F, 0x27, 0x53, 0xB8, 0xF3, 0x3F, 0xE1, 0x20, 0xB5, 0xDC, 0x1B,
+	0xEC, 0x5B, 0x64, 0x75, 0x83, 0xE6, 0x0A, 0xAB, 0x26, 0xF5, 0x40, 0x7E, 0x41, 0xF2, 0xFF, 0x00,
+	0x17, 0x35, 0xD0, 0x58, 0x4C, 0xD1, 0x41, 0x26, 0x9A, 0xDF, 0xEA, 0xE2, 0xDB, 0xF6, 0x77, 0xFF,
+	0x00, 0x9E, 0x99, 0x39, 0x6E, 0x3B, 0x60, 0xFA, 0xF5, 0xAF, 0x3C, 0xF0, 0xBF, 0x8C, 0x97, 0x45,
+	0xF8, 0xD1, 0x67, 0xA9, 0xFF, 0x00, 0x67, 0x79, 0x70, 0xF8, 0xE3, 0xCC, 0xFF, 0x00, 0x84, 0x88,
+	0x79, 0xD9, 0xFF, 0x00, 0x8F, 0x2B, 0x62, 0x20, 0xEC, 0x4F, 0x53, 0xFC, 0x1B, 0x7F, 0xDA, 0xDD,
+	0x5E, 0x8B, 0x04, 0x1E, 0x64, 0x49, 0x1C, 0x9F, 0xBB, 0x5B, 0x5C, 0xF9, 0x31, 0xF5, 0xC6, 0xEE,
+	0xBC, 0xFF, 0x00, 0x8D, 0x75, 0x42, 0xE7, 0x34, 0x85, 0xA2, 0x9F, 0xE5, 0x2F, 0xFC, 0xF4, 0xFD,
+	0x29, 0x1D, 0x02, 0x2E, 0xE0, 0xD9, 0xAD, 0x8C, 0x46, 0xD1, 0x4D, 0xF3, 0x3D, 0xA8, 0x0F, 0x93,
+	0x8C, 0x50, 0x03, 0xA9, 0xD1, 0xE7, 0x7F, 0x14, 0xDA, 0x54, 0x6D, 0xAD, 0xBB, 0x14, 0x01, 0x2F,
+	0xEF, 0x28, 0xFD, 0xE5, 0x37, 0xCF, 0xFF, 0x00, 0x67, 0xF5, 0xA3, 0xCF, 0xFF, 0x00, 0x67, 0xF5,
+	0xA0, 0x07, 0x7E, 0xF2, 0x8F, 0xDE, 0x53, 0x7C, 0xFF, 0x00, 0xF6, 0x7F, 0x5A, 0x3C, 0xFF, 0x00,
+	0xF6, 0x7F, 0x5A, 0x00, 0x77, 0xEF, 0x29, 0xC8, 0xD7, 0x0A, 0xDB, 0xA2, 0x3F, 0x37, 0x6E, 0x95,
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+	0x3A, 0xA3, 0xAB, 0xDA, 0x78, 0xD7, 0xC4, 0xD7, 0x16, 0xDE, 0x27, 0xB7, 0xFB, 0x2D, 0xF5, 0xC6,
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+	0x2B, 0x4D, 0xB8, 0xD3, 0x6E, 0x97, 0xE7, 0xB5, 0xDB, 0xE5, 0xB6, 0x7A, 0xEE, 0x24, 0x9E, 0x95,
+	0xE7, 0x91, 0x5F, 0xDE, 0xC9, 0xAB, 0x43, 0xA3, 0xB5, 0xE7, 0x99, 0x1B, 0x6E, 0xFD, 0xE7, 0x96,
+	0x17, 0x6F, 0xCB, 0xBB, 0xA7, 0x7F, 0xCE, 0xBB, 0x4D, 0x4E, 0xC2, 0x30, 0x9A, 0x4F, 0xF6, 0x47,
+	0xFA, 0x3C, 0x77, 0x9E, 0x7F, 0xDA, 0x23, 0xFB, 0xFB, 0xB6, 0x63, 0x6F, 0x2D, 0xD3, 0xBF, 0x4C,
+	0x50, 0x07, 0x57, 0xF0, 0xB7, 0x57, 0xFE, 0xCC, 0xF1, 0x95, 0x9A, 0xCA, 0x7F, 0x72, 0xDE, 0x67,
+	0x99, 0xFF, 0x00, 0x7E, 0xDF, 0x1D, 0xB3, 0xD4, 0xD7, 0xB1, 0x1B, 0xC3, 0x0B, 0x2C, 0x82, 0x3D,
+	0xCA, 0x73, 0xF2, 0xE7, 0x19, 0xAF, 0x9F, 0xF4, 0x9B, 0xA7, 0x68, 0x91, 0x63, 0x8B, 0x6B, 0x4F,
+	0x9D, 0xB2, 0x6E, 0xCE, 0xCD, 0xB9, 0xED, 0xDF, 0x35, 0xEE, 0xF1, 0xDC, 0x49, 0x0C, 0x6B, 0x14,
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+	0xFF, 0x00, 0xEB, 0x5B, 0x77, 0xE9, 0x5E, 0xA1, 0xFB, 0x15, 0x6A, 0x1A, 0x6E, 0x91, 0xFB, 0x4D,
+	0x78, 0x67, 0x52, 0xBA, 0xD0, 0x7E, 0xDA, 0xB1, 0xFD, 0xB3, 0x75, 0xBF, 0xDA, 0x8C, 0x7B, 0xF3,
+	0x65, 0x38, 0xFB, 0xC3, 0xA6, 0x33, 0x9F, 0xC2, 0x80, 0x3E, 0x81, 0xFD, 0xBC, 0xBC, 0x5F, 0xF1,
+	0x13, 0xE2, 0x6F, 0xC0, 0x17, 0xB4, 0xF8, 0xE9, 0xF0, 0x63, 0xFE, 0x15, 0xBE, 0xBB, 0x67, 0x8F,
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+	0xA5, 0x8C, 0xF1, 0xC0, 0xD7, 0x56, 0xA9, 0xE6, 0xC8, 0xB8, 0xDB, 0x1E, 0x42, 0xE7, 0x90, 0x3A,
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+	0x07, 0x8F, 0x3C, 0x01, 0x3C, 0x7A, 0x0D, 0xE6, 0xB9, 0xE1, 0xF9, 0xBE, 0xD5, 0x6F, 0xA2, 0xF9,
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+	0xFA, 0x8F, 0xE1, 0x82, 0x46, 0x93, 0xFE, 0x3E, 0x08, 0x8F, 0xFD, 0x52, 0xC9, 0xF7, 0x8F, 0xD3,
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+	0xA7, 0xFC, 0x2E, 0xFF, 0x00, 0x84, 0xAB, 0x43, 0xF0, 0xE7, 0x9F, 0xF6, 0xDB, 0x4F, 0xED, 0xB5,
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+	0xD2, 0x45, 0x27, 0x80, 0xED, 0xBE, 0xDD, 0x0C, 0x3B, 0xBC, 0xE9, 0x37, 0xC1, 0x16, 0xDC, 0xED,
+	0xC7, 0x12, 0x3A, 0xE7, 0x25, 0x1B, 0xA7, 0xA7, 0xD2, 0xBA, 0x4F, 0x0C, 0x58, 0x6A, 0x5E, 0x1F,
+	0xD3, 0x17, 0x44, 0xB8, 0xBE, 0xFB, 0x43, 0x47, 0x9F, 0x3F, 0xF7, 0x41, 0x76, 0x65, 0x8B, 0x0F,
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+	0x72, 0xC7, 0x18, 0xF9, 0x87, 0xAD, 0x4C, 0x62, 0xC9, 0x93, 0xD0, 0x77, 0x8A, 0x2F, 0x85, 0xAF,
+	0x87, 0x92, 0xE9, 0x8F, 0xAF, 0x99, 0xFF, 0x00, 0x7D, 0x80, 0x2B, 0xD2, 0xBE, 0x1E, 0x5A, 0x1B,
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+	0x49, 0x10, 0x9E, 0x4F, 0x1D, 0x33, 0xD6, 0xBE, 0x80, 0x97, 0x4B, 0x87, 0x45, 0xB7, 0x1A, 0x55,
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+	0xE9, 0x8C, 0x59, 0xCD, 0x26, 0x47, 0xE6, 0xFF, 0x00, 0xB5, 0x4A, 0x92, 0xFC, 0xDF, 0x7A, 0xA2,
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+	0x33, 0xDA, 0x8F, 0x33, 0xDA, 0x80, 0xBA, 0x26, 0xF3, 0x7F, 0xDA, 0xA3, 0xCD, 0xFF, 0x00, 0x6A,
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+	0x99, 0x61, 0xB8, 0x85, 0x7C, 0x2D, 0x6B, 0x0F, 0x96, 0x13, 0xFD, 0x7B, 0x6E, 0xCF, 0x5F, 0x9C,
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+	0xBC, 0x4F, 0x2A, 0x5B, 0xAD, 0x98, 0x93, 0x3B, 0xB1, 0xB4, 0xFA, 0x0F, 0x6A, 0xF4, 0xFF, 0x00,
+	0xDA, 0x6F, 0xC0, 0x5E, 0x1D, 0xF8, 0x7B, 0xF0, 0x37, 0xE1, 0x7F, 0x8F, 0x3C, 0x25, 0xA6, 0xFD,
+	0x9A, 0xE3, 0x54, 0xFE, 0xDB, 0xF3, 0xAE, 0x3C, 0xE7, 0x7C, 0xF9, 0x77, 0x31, 0x46, 0x3E, 0x57,
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+	0xB1, 0xEC, 0x5E, 0x38, 0xFB, 0xDD, 0x4D, 0x7D, 0xED, 0xFB, 0x3A, 0x7F, 0xC1, 0x58, 0xB4, 0x3D,
+	0x4F, 0xC3, 0x12, 0x78, 0x4B, 0xF6, 0x83, 0x1E, 0x5D, 0xC2, 0xE3, 0xED, 0x1A, 0xF7, 0xCC, 0x7C,
+	0xFF, 0x00, 0x9E, 0x57, 0x5F, 0xDC, 0xDB, 0x5A, 0xE1, 0x76, 0x81, 0x1A, 0x70, 0x79, 0xEB, 0xEB,
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+	0x79, 0x7A, 0x8F, 0xFC, 0xB8, 0xF8, 0x7F, 0xED, 0x56, 0xA7, 0xED, 0x1C, 0x92, 0xFF, 0x00, 0xBF,
+	0x6B, 0x90, 0xA9, 0xB5, 0x41, 0x7E, 0x7A, 0xFD, 0xD1, 0xCD, 0x71, 0xFF, 0x00, 0x05, 0xBF, 0x66,
+	0x5F, 0x89, 0xDF, 0x1A, 0xFC, 0x21, 0xFF, 0x00, 0x09, 0xDE, 0x8F, 0xAC, 0x7D, 0x87, 0xC3, 0x50,
+	0xFF, 0x00, 0xC7, 0xAE, 0xA9, 0xF6, 0x78, 0x24, 0xF2, 0xB3, 0x23, 0xC6, 0xDF, 0xBB, 0x69, 0x16,
+	0x46, 0xCC, 0x88, 0x57, 0x91, 0xC6, 0x72, 0x38, 0xE6, 0xA2, 0xF1, 0x2E, 0xD2, 0x3D, 0x37, 0xFE,
+	0x0A, 0x23, 0xFB, 0x66, 0x68, 0x3F, 0xB5, 0xD7, 0x89, 0x3C, 0x37, 0xA6, 0xFC, 0x3F, 0xD0, 0xBC,
+	0xED, 0x37, 0x41, 0xFB, 0x67, 0x93, 0x27, 0xDA, 0x99, 0x7E, 0xD1, 0xE7, 0xA5, 0xB1, 0x3C, 0x49,
+	0x0C, 0x6C, 0xBB, 0x5A, 0x16, 0xEB, 0x9C, 0xFB, 0x0C, 0x67, 0xE6, 0x65, 0xD4, 0xA5, 0xB4, 0x47,
+	0xD2, 0xA2, 0x9F, 0xC9, 0x58, 0xF1, 0xF6, 0x78, 0x36, 0xEE, 0xF3, 0xF3, 0xCB, 0x73, 0x8F, 0x97,
+	0x6F, 0x5E, 0x7A, 0xD7, 0xBC, 0xC9, 0xFB, 0x20, 0xF8, 0xC7, 0xC1, 0xDE, 0x0F, 0xF8, 0xA1, 0xE1,
+	0x3F, 0x17, 0xFC, 0x1D, 0xFE, 0xDC, 0xD4, 0xB4, 0x3F, 0xEC, 0x4F, 0xB2, 0x6A, 0xDF, 0xF0, 0x90,
+	0x47, 0x6D, 0xFD, 0x8F, 0xE7, 0x49, 0xBD, 0xBF, 0x74, 0x92, 0x95, 0xB8, 0xF3, 0x55, 0x82, 0xF2,
+	0x4E, 0xCD, 0xB9, 0x18, 0x26, 0xB7, 0xFF, 0x00, 0x68, 0xAF, 0xF8, 0x27, 0xEF, 0xC5, 0x5F, 0x87,
+	0x9E, 0x3E, 0xBA, 0xD0, 0x3E, 0x13, 0xD9, 0x7F, 0x6D, 0x5A, 0xDB, 0xF9, 0x7F, 0x63, 0xD3, 0xBC,
+	0xC8, 0x2D, 0xBC, 0xAD, 0xD1, 0x46, 0xCF, 0xFB, 0xC9, 0xA7, 0x25, 0xB2, 0x59, 0xDB, 0x93, 0xC6,
+	0xDC, 0x0E, 0xA2, 0x9D, 0xE2, 0x1C, 0xB2, 0x32, 0xBF, 0x61, 0x4F, 0xDB, 0xBF, 0x5A, 0xFD, 0x9A,
+	0xF5, 0x9B, 0x9F, 0x07, 0x78, 0xCB, 0x4C, 0xFF, 0x00, 0x84, 0x83, 0xC2, 0xB7, 0x1B, 0x3E, 0xD5,
+	0x69, 0xE7, 0x2D, 0xA7, 0xD9, 0x76, 0xAD, 0xC3, 0xAF, 0xCC, 0x90, 0x3C, 0x8F, 0xBA, 0x59, 0x54,
+	0xF0, 0x78, 0xDB, 0x8E, 0x87, 0x8F, 0x1C, 0xF8, 0xD7, 0x17, 0xC2, 0x68, 0xBE, 0x21, 0x6A, 0xB0,
+	0xFC, 0x1D, 0xBD, 0xDD, 0xE0, 0x9F, 0xDC, 0x7F, 0x64, 0xDC, 0xF9, 0x73, 0x8C, 0xFE, 0xE9, 0x3C,
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+	0x8F, 0xFD, 0xA7, 0x58, 0xF2, 0x33, 0x4E, 0x63, 0xE5, 0x4F, 0xF8, 0x5B, 0xDF, 0x0D, 0xFF, 0x00,
+	0xE8, 0x69, 0xFF, 0x00, 0xC9, 0x19, 0xBF, 0xF8, 0x8A, 0x3F, 0xE1, 0x6F, 0x7C, 0x37, 0xFF, 0x00,
+	0xA1, 0xA7, 0xFF, 0x00, 0x24, 0x66, 0xFF, 0x00, 0xE2, 0x2B, 0xEA, 0xCF, 0xF8, 0x68, 0x2F, 0x13,
+	0xFF, 0x00, 0xCF, 0xBF, 0xFE, 0x3C, 0x9F, 0xFC, 0x6E, 0x8F, 0xF8, 0x68, 0x2F, 0x13, 0xFF, 0x00,
+	0xCF, 0xBF, 0xFE, 0x3C, 0x9F, 0xFC, 0x6E, 0x8E, 0x46, 0x1C, 0xE7, 0xCA, 0x7F, 0xF0, 0xB7, 0xBE,
+	0x1B, 0xFF, 0x00, 0xD0, 0xD3, 0xFF, 0x00, 0x92, 0x33, 0x7F, 0xF1, 0x14, 0xA3, 0xE2, 0xF7, 0xC3,
+	0x73, 0xC0, 0xF1, 0x4F, 0xFE, 0x48, 0xCD, 0xFF, 0x00, 0xC4, 0x57, 0xD5, 0x7F, 0xF0, 0xD0, 0x5E,
+	0x27, 0xFF, 0x00, 0x9F, 0x7F, 0xFC, 0x79, 0x3F, 0xF8, 0xDD, 0x3A, 0x2F, 0xDA, 0x03, 0xC4, 0xED,
+	0x20, 0x5F, 0x23, 0xFF, 0x00, 0x1E, 0x4F, 0xFE, 0x37, 0x47, 0x23, 0x2B, 0xDA, 0x1F, 0x29, 0x7F,
+	0xC2, 0xDC, 0xF8, 0x73, 0xFF, 0x00, 0x43, 0x47, 0xFE, 0x48, 0xCD, 0xFF, 0x00, 0xC4, 0x50, 0x7E,
+	0x2B, 0xF8, 0x0A, 0x61, 0xE5, 0xD9, 0xF8, 0x83, 0xCC, 0x90, 0xFD, 0xD8, 0xFE, 0xC9, 0x2A, 0xE7,
+	0xF1, 0x2B, 0xE9, 0x5F, 0x5A, 0x2F, 0xC7, 0xAF, 0x13, 0x1E, 0x3C, 0xBF, 0xFC, 0x79, 0x3F, 0xF8,
+	0x8A, 0x70, 0xF8, 0xE9, 0xE2, 0x46, 0xE1, 0xA3, 0xC8, 0xFF, 0x00, 0x79, 0x3F, 0xF8, 0x8A, 0x39,
+	0x18, 0x7B, 0x43, 0xE4, 0xB4, 0xF8, 0x91, 0xE1, 0xD3, 0xC0, 0xBB, 0xFF, 0x00, 0xC8, 0x6F, 0xFF,
+	0x00, 0xC4, 0xD3, 0xA4, 0xF8, 0x91, 0xE1, 0x83, 0x19, 0xF3, 0xEE, 0xFE, 0x5E, 0xFF, 0x00, 0xBB,
+	0x7F, 0xFE, 0x26, 0xBE, 0xB4, 0x5F, 0x8E, 0x5E, 0x20, 0x1F, 0xF2, 0xED, 0xFF, 0x00, 0x8F, 0xA7,
+	0xFF, 0x00, 0x11, 0x4E, 0x6F, 0x8E, 0x7A, 0xEB, 0xA7, 0x96, 0xF6, 0x79, 0x1F, 0xF5, 0xD1, 0x7F,
+	0xF8, 0x8A, 0x39, 0x19, 0x3C, 0xC7, 0xC8, 0x9F, 0xF0, 0xB1, 0xBC, 0x13, 0xFF, 0x00, 0x3F, 0x5F,
+	0xF8, 0xE4, 0x9F, 0xFC, 0x4D, 0x2A, 0xFC, 0x45, 0xF0, 0x71, 0x38, 0x82, 0xF7, 0x6B, 0x76, 0x6F,
+	0x2E, 0x43, 0x8F, 0xFC, 0x76, 0xBE, 0xB6, 0xFF, 0x00, 0x85, 0xD7, 0xAB, 0x7F, 0xD0, 0x3F, 0xFF,
+	0x00, 0x23, 0x2F, 0xFF, 0x00, 0x11, 0x4D, 0x93, 0xE3, 0x66, 0xAC, 0xA8, 0x58, 0xE9, 0xFF, 0x00,
+	0xF9, 0x19, 0x7F, 0xF8, 0x8A, 0x39, 0x18, 0x73, 0x1F, 0x26, 0xFF, 0x00, 0xC2, 0xC3, 0xF0, 0xF7,
+	0xFD, 0x06, 0x3F, 0xF2, 0x5D, 0xFF, 0x00, 0xF8, 0x9A, 0x07, 0xC4, 0x2F, 0x0C, 0x9E, 0x27, 0xD5,
+	0xFE, 0x5E, 0xFF, 0x00, 0xE8, 0xEF, 0xFF, 0x00, 0xC4, 0xD7, 0xD5, 0x8D, 0xF1, 0xCF, 0x56, 0x1C,
+	0x8D, 0x37, 0xFF, 0x00, 0x23, 0x2F, 0xFF, 0x00, 0x11, 0x4D, 0xFF, 0x00, 0x85, 0xEF, 0xA9, 0x8F,
+	0xF5, 0x9A, 0x4E, 0xE1, 0xFD, 0xDF, 0xB4, 0x2F, 0x3F, 0xF8, 0xE5, 0x1C, 0x8C, 0x39, 0x8F, 0x95,
+	0xBF, 0xE1, 0x60, 0x78, 0x27, 0xFE, 0x82, 0xFF, 0x00, 0xF9, 0x2F, 0x27, 0xFF, 0x00, 0x13, 0x4C,
+	0x9F, 0xE2, 0x47, 0x82, 0xED, 0x62, 0x33, 0xAD, 0xEF, 0x9D, 0xB7, 0xFE, 0x59, 0xF9, 0x72, 0x2E,
+	0x7F, 0x1D, 0xB5, 0xF5, 0x67, 0xFC, 0x2F, 0x8B, 0xBF, 0xFA, 0x17, 0xFF, 0x00, 0xF2, 0x68, 0x7F,
+	0xF1, 0x14, 0x1F, 0x8F, 0x57, 0x63, 0x93, 0xE1, 0xFF, 0x00, 0xFC, 0x9B, 0x1F, 0xFC, 0x45, 0x35,
+	0x0D, 0x43, 0x98, 0xF9, 0x1E, 0x4F, 0x1F, 0x78, 0x36, 0xCC, 0x7D, 0xBF, 0xFB, 0x43, 0xEC, 0xFF,
+	0x00, 0xF6, 0xC6, 0x47, 0xF6, 0xFE, 0xED, 0x58, 0xF0, 0xE7, 0x88, 0xAC, 0xFE, 0x23, 0xEB, 0x90,
+	0xE8, 0x7E, 0x0D, 0xF1, 0x97, 0x9D, 0xA9, 0x4D, 0xBB, 0xEC, 0xD6, 0xBF, 0xD9, 0xE5, 0x77, 0xE1,
+	0x4B, 0x37, 0xCC, 0xE1, 0x54, 0x61, 0x55, 0x8F, 0x27, 0xF5, 0xAF, 0xAB, 0xA0, 0xFD, 0xA4, 0xBC,
+	0x7F, 0x61, 0x26, 0xED, 0x26, 0xEB, 0xEC, 0xE3, 0xFB, 0xBE, 0x5C, 0x4F, 0xFC, 0xE3, 0xFA, 0xD2,
+	0x6B, 0x3F, 0xB5, 0x3F, 0xC7, 0x9D, 0x6A, 0xC2, 0x4D, 0x1E, 0xE3, 0xC7, 0x78, 0xB3, 0x9B, 0x1E,
+	0x6D, 0xBF, 0xF6, 0x5D, 0xAF, 0xCD, 0x82, 0x18, 0x7C, 0xDE, 0x50, 0x23, 0x91, 0x9E, 0xB5, 0xA7,
+	0x28, 0x73, 0x1E, 0x55, 0xA0, 0xFE, 0xC9, 0x9F, 0x1D, 0xF5, 0x6B, 0x51, 0xAC, 0x7C, 0x4D, 0xB2,
+	0xFF, 0x00, 0x85, 0x67, 0xA4, 0xFF, 0x00, 0xD0, 0xE1, 0xE6, 0x5A, 0xEB, 0x3E, 0x67, 0x25, 0x7F,
+	0xE3, 0xD2, 0x29, 0x77, 0x0C, 0x38, 0x58, 0xBA, 0x73, 0xE6, 0xEE, 0xE8, 0xA6, 0xBB, 0x2F, 0x04,
+	0xE9, 0x3F, 0x09, 0xFF, 0x00, 0x66, 0xFD, 0x56, 0x1D, 0x6F, 0xE0, 0xE7, 0x86, 0xFF, 0x00, 0xB5,
+	0xBC, 0x4A, 0xBB, 0xBE, 0xC5, 0xE3, 0x8F, 0xB6, 0x4F, 0x6F, 0xBB, 0xE5, 0x65, 0x7F, 0xF4, 0x39,
+	0xCB, 0xC6, 0x31, 0x1C, 0xAF, 0x0F, 0x23, 0xB6, 0xF1, 0xC9, 0x18, 0xC7, 0xD4, 0x2E, 0x86, 0xA9,
+	0x7B, 0xFD, 0xA9, 0x7D, 0x17, 0x99, 0x74, 0x7A, 0xCD, 0xBB, 0x1D, 0xB1, 0xD0, 0x71, 0xD0, 0x62,
+	0xA0, 0x36, 0xBA, 0x7A, 0x5B, 0xC9, 0x6F, 0x61, 0x67, 0xE4, 0x34, 0xDB, 0x7C, 0xC7, 0xF3, 0x0B,
+	0x6E, 0xC1, 0xE3, 0x83, 0x47, 0x2D, 0x89, 0x94, 0xBD, 0xD3, 0x43, 0x52, 0x83, 0x58, 0xF1, 0xFD,
+	0xFC, 0x8F, 0xAD, 0x68, 0xDF, 0x6C, 0x91, 0xB1, 0xBF, 0x58, 0xFB, 0x42, 0xC7, 0xB3, 0x81, 0x8F,
+	0xDD, 0x2E, 0x33, 0x90, 0xA1, 0x7D, 0xB1, 0x9A, 0x8E, 0x19, 0x9C, 0x58, 0xCB, 0xA7, 0xD8, 0xEA,
+	0x3F, 0x68, 0x82, 0xDF, 0x6F, 0x9B, 0x27, 0x93, 0xB3, 0x76, 0xE3, 0x91, 0xC1, 0xE4, 0x73, 0x55,
+	0x9E, 0xCB, 0x4B, 0x96, 0xD7, 0xFB, 0x3E, 0x5B, 0x0D, 0xD6, 0xBD, 0xE1, 0xF3, 0x5B, 0x9E, 0x73,
+	0xD7, 0xAF, 0x5E, 0x69, 0xCD, 0x25, 0xFC, 0xE6, 0x38, 0x6E, 0x2F, 0x77, 0x43, 0x0E, 0x7C, 0x88,
+	0xBC, 0xB0, 0x36, 0x67, 0xEF, 0x73, 0xD4, 0xE4, 0xFA, 0xD5, 0x73, 0x1C, 0xA1, 0x4D, 0x97, 0xFD,
+	0x59, 0xA9, 0x0A, 0x60, 0x67, 0x35, 0x1C, 0x87, 0x23, 0x6D, 0x1C, 0xC0, 0x31, 0x3E, 0xED, 0x4A,
+	0x0E, 0x0E, 0x6A, 0x30, 0x30, 0x31, 0x4E, 0x2F, 0x91, 0x8C, 0x51, 0xCC, 0x04, 0xC9, 0x27, 0x15,
+	0x32, 0x3E, 0xEA, 0xAA, 0x99, 0x3D, 0x0D, 0x4F, 0x06, 0x4C, 0x80, 0x66, 0x8E, 0x60, 0x25, 0xA5,
+	0x4F, 0xBD, 0x4B, 0xE5, 0xFB, 0xD0, 0x13, 0x07, 0x39, 0xA3, 0x98, 0x07, 0x51, 0x45, 0x14, 0x73,
+	0x00, 0x51, 0x45, 0x14, 0x73, 0x00, 0x51, 0x45, 0x14, 0x73, 0x00, 0x51, 0x45, 0x14, 0x73, 0x00,
+	0xE8, 0xEA, 0x54, 0xFB, 0xB5, 0x14, 0x75, 0x2A, 0x7D, 0xDA, 0x39, 0x80, 0x91, 0x3E, 0xED, 0x4A,
+	0x06, 0x4E, 0x2A, 0x24, 0xFB, 0xB5, 0x3C, 0x65, 0x77, 0xFC, 0xC7, 0x8A, 0x39, 0x8D, 0x07, 0x24,
+	0x75, 0x21, 0x88, 0x95, 0xDB, 0x8A, 0x8C, 0xDC, 0x48, 0x1F, 0x11, 0x43, 0xBB, 0xFE, 0x05, 0x8A,
+	0xB5, 0x02, 0x39, 0x1E, 0x65, 0xC2, 0xF9, 0x6B, 0xFD, 0xEC, 0xE7, 0x14, 0x73, 0x00, 0xB6, 0xB0,
+	0x64, 0xE2, 0xB4, 0xAC, 0xEC, 0x6E, 0x27, 0x91, 0x61, 0xB5, 0x38, 0x76, 0xFB, 0xBD, 0x3F, 0xAD,
+	0x57, 0xD3, 0x23, 0x33, 0xC1, 0x23, 0xCC, 0x9E, 0x5C, 0x90, 0x6D, 0xF3, 0xA1, 0xCE, 0x76, 0x64,
+	0x9C, 0x73, 0xDF, 0x23, 0xD2, 0xBA, 0x1D, 0x6E, 0xDE, 0xC7, 0xE1, 0xF7, 0x85, 0x7F, 0xE1, 0x62,
+	0x6A, 0xFA, 0x87, 0xFA, 0x15, 0xBF, 0xFA, 0xE3, 0xE5, 0x1F, 0x97, 0x73, 0x88, 0x87, 0xDD, 0xC9,
+	0xFB, 0xCC, 0x3A, 0x0F, 0xF1, 0xA7, 0x29, 0x1A, 0xC6, 0x27, 0x41, 0xF0, 0x5B, 0xF6, 0x76, 0xBB,
+	0xFD, 0xAE, 0xFF, 0x00, 0x69, 0x6F, 0x0E, 0x7E, 0xC8, 0x9E, 0x18, 0x8F, 0x6D, 0xBE, 0xB9, 0xF6,
+	0xCF, 0xED, 0x2B, 0x8D, 0xC0, 0xFD, 0x97, 0xC9, 0xB3, 0x7B, 0xD8, 0xFE, 0x57, 0x92, 0x32, 0xFB,
+	0x8C, 0x24, 0x7C, 0xB2, 0x0C, 0x77, 0xCF, 0xDD, 0x3F, 0xD2, 0x0E, 0x85, 0x6B, 0x61, 0x6F, 0xA6,
+	0xC3, 0x1D, 0x8D, 0xA7, 0x93, 0x1C, 0x7B, 0xBC, 0xB8, 0xF7, 0x16, 0xDB, 0x96, 0x39, 0xE4, 0xFB,
+	0xD7, 0xE7, 0x8F, 0xFC, 0x10, 0x13, 0xF6, 0x23, 0xF1, 0x6F, 0xC1, 0x7F, 0x86, 0x5A, 0xB7, 0xED,
+	0x2D, 0xF1, 0x8B, 0x4D, 0xF2, 0x3C, 0x49, 0xE3, 0xEF, 0xB3, 0xF9, 0x1A, 0x7F, 0x9D, 0x1B, 0x7F,
+	0x66, 0xFD, 0x86, 0x6D, 0x46, 0xD5, 0xBF, 0x79, 0x04, 0xCD, 0x1C, 0xDE, 0x64, 0x6E, 0x8D, 0xCA,
+	0x2E, 0xDE, 0x9F, 0x31, 0xC9, 0xAF, 0xD1, 0xA4, 0x52, 0x88, 0x10, 0xB1, 0x6C, 0x0F, 0xBC, 0xDD,
+	0xFD, 0xEB, 0x9A, 0x52, 0xB9, 0xD3, 0x18, 0xD8, 0x5A, 0x28, 0xA2, 0xA4, 0xA0, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28,
+	0x00, 0xA8, 0xEE, 0x6D, 0xE3, 0xB8, 0x4C, 0x49, 0x1E, 0xEC, 0x74, 0xF9, 0xB1, 0x52, 0x51, 0x40,
+	0x1F, 0x82, 0x9F, 0xF0, 0x54, 0x8F, 0xD8, 0x07, 0xC4, 0xFF, 0x00, 0xF0, 0x4D, 0xEF, 0x8D, 0xAF,
+	0xF1, 0x87, 0xE1, 0x06, 0x95, 0xFF, 0x00, 0x16, 0xB7, 0x5E, 0xC7, 0x93, 0x6F, 0xE7, 0xA7, 0xFC,
+	0x48, 0x3C, 0x8B, 0x6B, 0x48, 0x0F, 0xCD, 0x34, 0xF3, 0x5C, 0x5D, 0x79, 0xF7, 0x57, 0x2E, 0x79,
+	0x51, 0xE5, 0xFB, 0xAE, 0x08, 0xF0, 0xAD, 0x4F, 0xE1, 0xDF, 0x85, 0xFC, 0x79, 0x65, 0x71, 0xAD,
+	0xFC, 0x3D, 0xB9, 0xDB, 0x9D, 0xBE, 0x4D, 0xAE, 0xC7, 0xFD, 0xCF, 0x21, 0x4F, 0xCD, 0x23, 0x0D,
+	0xD9, 0xDA, 0xC7, 0x91, 0xC7, 0xE5, 0x5F, 0xD2, 0x57, 0x8E, 0x3C, 0x0F, 0xE1, 0x7F, 0x89, 0x1E,
+	0x17, 0xBA, 0xF0, 0x67, 0x8C, 0xF4, 0xBF, 0xB6, 0x69, 0xB7, 0x9B, 0x3E, 0xD3, 0x6D, 0xE7, 0x3C,
+	0x7B, 0xF6, 0x3A, 0xBA, 0xFC, 0xC8, 0xCA, 0xC3, 0x0C, 0xAA, 0x78, 0x23, 0xA7, 0xA5, 0x7E, 0x22,
+	0xFE, 0xDD, 0x9F, 0xF0, 0x49, 0xFF, 0x00, 0x8A, 0xBF, 0xB0, 0x0E, 0xB0, 0xFF, 0x00, 0x13, 0xBE,
+	0x0D, 0x0F, 0xED, 0xBF, 0x86, 0x76, 0xD8, 0xF2, 0xD7, 0xF7, 0x16, 0xDF, 0xF0, 0x8F, 0xEE, 0x5B,
+	0x78, 0x8F, 0xFA, 0xFB, 0xA9, 0xAE, 0x2E, 0xFC, 0xFB, 0x9B, 0x87, 0xFE, 0x1F, 0xDD, 0xED, 0xFE,
+	0xE9, 0x04, 0x6D, 0x1A, 0x8A, 0xDA, 0x99, 0xCE, 0x3A, 0x1F, 0x14, 0xEA, 0x7A, 0x6E, 0xAB, 0xA6,
+	0xEA, 0x07, 0x4C, 0xD6, 0x62, 0xF9, 0x47, 0xF1, 0x6E, 0x5F, 0x40, 0x7F, 0x84, 0xFB, 0x8A, 0x8E,
+	0xE3, 0x4E, 0xB6, 0xB1, 0x91, 0x45, 0xAF, 0xDD, 0x3F, 0x5F, 0xEB, 0x5E, 0xC7, 0xA1, 0x78, 0xA3,
+	0xC0, 0xBF, 0x13, 0x6D, 0xCE, 0x99, 0x73, 0x0F, 0x95, 0x78, 0x3E, 0xF4, 0x9B, 0xA5, 0x6C, 0x72,
+	0x4F, 0x40, 0x14, 0x74, 0x5A, 0xE5, 0xBC, 0x4B, 0xF0, 0x3F, 0xC5, 0x90, 0x5C, 0x31, 0xF0, 0xF5,
+	0xB7, 0xDB, 0xA3, 0xE3, 0x2D, 0xBE, 0x38, 0xB1, 0xC0, 0xFE, 0xF3, 0xFA, 0xE7, 0xF2, 0xAB, 0xF6,
+	0x91, 0x39, 0x39, 0x59, 0xE7, 0xB7, 0x35, 0x56, 0x6C, 0xE0, 0xE2, 0xAF, 0xCF, 0x69, 0x35, 0xDD,
+	0xE3, 0x69, 0xDA, 0x4A, 0xFD, 0xA6, 0xE2, 0x3C, 0x79, 0x91, 0xFD, 0xCD, 0xB9, 0x19, 0x1C, 0x9E,
+	0x0F, 0x19, 0xFC, 0xAA, 0xA5, 0xD4, 0x70, 0xDB, 0x06, 0xFB, 0x5C, 0xFE, 0x5B, 0x2F, 0xDE, 0x5D,
+	0xB9, 0xC7, 0xE5, 0x4F, 0x9E, 0x22, 0x6B, 0x42, 0xAF, 0xEF, 0x29, 0xD1, 0xEF, 0xDF, 0xCD, 0x2A,
+	0xC7, 0x34, 0xDF, 0xF1, 0xE9, 0x17, 0x98, 0x3D, 0x77, 0x6D, 0xFE, 0x74, 0xAD, 0x05, 0xDA, 0xAF,
+	0xC9, 0x6F, 0xBA, 0x4F, 0xE1, 0x8F, 0x70, 0x19, 0xFC, 0x6A, 0x8C, 0xAE, 0x87, 0x51, 0x4D, 0x0B,
+	0xA8, 0xAF, 0xFA, 0xEB, 0x0D, 0xBF, 0xF6, 0xD4, 0x1A, 0x72, 0x12, 0xED, 0xB3, 0x6F, 0xCD, 0xE9,
+	0x40, 0xD4, 0xB5, 0x22, 0x7F, 0xBB, 0x51, 0x49, 0x56, 0x9E, 0xD8, 0xAA, 0xFC, 0xED, 0x8A, 0xAF,
+	0x28, 0x88, 0x0F, 0x96, 0x6C, 0xB7, 0xA6, 0xDA, 0x39, 0x4D, 0x39, 0x88, 0xE8, 0xA2, 0x8A, 0x39,
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+	0xD9, 0xC8, 0xDB, 0x23, 0xB9, 0xCB, 0x7A, 0x6C, 0x34, 0x73, 0x00, 0xB4, 0x8F, 0xF7, 0x69, 0xFB,
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+	0x4F, 0xFF, 0x00, 0x27, 0xA1, 0xFF, 0x00, 0xE2, 0xAA, 0x78, 0x3E, 0x10, 0x7C, 0x4D, 0x92, 0x50,
+	0xB3, 0x78, 0x5B, 0xCB, 0x5F, 0xE2, 0x7F, 0xB7, 0x42, 0x71, 0xF8, 0x6F, 0xA3, 0x98, 0x39, 0x4E,
+	0x63, 0xCA, 0xFF, 0x00, 0x66, 0x8F, 0x2B, 0xFD, 0x9A, 0xEE, 0xAC, 0xFF, 0x00, 0x67, 0x9F, 0x8B,
+	0x37, 0xC7, 0x74, 0x1E, 0x18, 0xCA, 0x7F, 0x7B, 0xED, 0xB0, 0x7F, 0xF1, 0xCA, 0xD4, 0xB6, 0xFD,
+	0x99, 0xFC, 0x5D, 0x33, 0x0B, 0x79, 0xAE, 0x3C, 0xB9, 0xDB, 0xEE, 0xC3, 0xB2, 0x33, 0x9F, 0xC7,
+	0xCC, 0xC7, 0x4E, 0x6B, 0x3E, 0x60, 0xE5, 0x3C, 0xCD, 0x13, 0x1D, 0xAA, 0x52, 0xA8, 0x8B, 0xBE,
+	0x43, 0x85, 0xFE, 0xF5, 0x7A, 0xC5, 0xB7, 0xEC, 0xAB, 0xAC, 0x28, 0xCE, 0xA5, 0xE2, 0x4F, 0xB3,
+	0xFF, 0x00, 0xDB, 0x9A, 0xBF, 0xF2, 0x96, 0xAD, 0xE9, 0xDF, 0xB3, 0x5F, 0x87, 0xD3, 0x50, 0x8D,
+	0x75, 0x6F, 0x1B, 0xFD, 0xA2, 0x1E, 0x7C, 0xCB, 0x7F, 0xEC, 0xD7, 0x4D, 0xDC, 0x71, 0xF3, 0x09,
+	0x32, 0x39, 0xC1, 0xA3, 0x98, 0x39, 0x4F, 0x1B, 0x31, 0xC5, 0x37, 0x11, 0x4D, 0xFF, 0x00, 0x8E,
+	0xD3, 0x65, 0xB1, 0x11, 0x21, 0x9E, 0xE1, 0x7C, 0xC8, 0xC7, 0xDE, 0x4F, 0xBB, 0x9F, 0xC6, 0xBD,
+	0xF2, 0xD7, 0xE0, 0xCF, 0xC3, 0x9D, 0x36, 0x5F, 0x9B, 0x4D, 0xF3, 0x14, 0x7F, 0x17, 0x9D, 0x32,
+	0xFF, 0x00, 0xEC, 0xFE, 0xF5, 0x2F, 0xDA, 0xFE, 0x19, 0xF8, 0x32, 0xF5, 0x2F, 0x2C, 0xBC, 0x37,
+	0xB2, 0x68, 0xF3, 0xB6, 0x7F, 0xB6, 0x4C, 0x76, 0xE4, 0x63, 0xA1, 0xCE, 0x78, 0x6C, 0x51, 0xCC,
+	0x1C, 0xA7, 0x86, 0x69, 0x1E, 0x18, 0x93, 0x58, 0x3B, 0x74, 0xCD, 0x37, 0x6F, 0xFD, 0xB6, 0xFA,
+	0xFA, 0x91, 0xE8, 0x6B, 0xA8, 0xB0, 0xF8, 0x29, 0xE3, 0x71, 0xB6, 0xF5, 0x6D, 0xF6, 0xC6, 0xBD,
+	0x7E, 0x78, 0xBE, 0x9F, 0xDF, 0xAE, 0xE3, 0xC5, 0x7F, 0xB4, 0x4F, 0x85, 0x3C, 0x35, 0x0F, 0xDA,
+	0x66, 0x93, 0xC9, 0x8F, 0xF8, 0xA4, 0xDB, 0x23, 0x63, 0xA0, 0xE9, 0xE5, 0x9E, 0xE6, 0xB2, 0x7C,
+	0x1D, 0xF1, 0xD3, 0xC6, 0xDF, 0x17, 0xF5, 0xA8, 0x7C, 0x39, 0xF0, 0x3F, 0x46, 0xFF, 0x00, 0x84,
+	0x82, 0xF2, 0xE3, 0x77, 0x93, 0x0F, 0xDA, 0x23, 0xB5, 0xDD, 0xB5, 0x59, 0x8F, 0x37, 0x08, 0xA3,
+	0xA2, 0x48, 0x79, 0x3F, 0xC3, 0xEE, 0x29, 0x4A, 0x5A, 0x07, 0x29, 0xA5, 0xA4, 0xFC, 0x13, 0xB9,
+	0xF0, 0xE5, 0x98, 0xB9, 0xF1, 0x6F, 0x8E, 0xFF, 0x00, 0x72, 0xFF, 0x00, 0xF2, 0xED, 0xFD, 0x96,
+	0x3B, 0x12, 0x3E, 0xF2, 0x39, 0x3D, 0x48, 0x35, 0x6D, 0x75, 0xEF, 0x87, 0x5F, 0x0E, 0xAC, 0xDE,
+	0x6D, 0x1B, 0xC0, 0xFF, 0x00, 0xDA, 0x12, 0x71, 0x87, 0xFE, 0xD2, 0x9A, 0x2C, 0xF3, 0xE8, 0xC1,
+	0xBF, 0xBC, 0x7F, 0x2A, 0xF6, 0x5F, 0x84, 0x5F, 0xF0, 0x48, 0xBF, 0xF8, 0x28, 0xEF, 0xED, 0x1B,
+	0x71, 0x1D, 0xEF, 0x8A, 0x74, 0xBF, 0xF8, 0x56, 0xFA, 0x6C, 0x9B, 0xBF, 0xE2, 0x69, 0xE7, 0x68,
+	0xFA, 0xC7, 0x40, 0xE3, 0xFD, 0x5A, 0x5D, 0xA3, 0x7D, 0xE8, 0x82, 0xFF, 0x00, 0xDB, 0x5C, 0xF4,
+	0x5E, 0x7E, 0xD3, 0xFD, 0x9F, 0xBF, 0xE0, 0xDE, 0x0F, 0xD9, 0x27, 0xE1, 0xF5, 0xE4, 0x3A, 0xFF,
+	0x00, 0xED, 0x05, 0x7B, 0xFF, 0x00, 0x0B, 0x2B, 0x58, 0xB7, 0xDD, 0xE5, 0xEA, 0x7E, 0x5D, 0xFE,
+	0x8D, 0x8D, 0xC2, 0x45, 0x3F, 0xBB, 0xB6, 0xBF, 0x29, 0xF7, 0x1A, 0x35, 0xE9, 0xFF, 0x00, 0x2C,
+	0xB3, 0xD5, 0x8D, 0x60, 0x69, 0xEC, 0xFC, 0x8F, 0xCC, 0xEF, 0x84, 0x1E, 0x1B, 0xFD, 0xA1, 0xFF,
+	0x00, 0x6D, 0xFD, 0x59, 0xB4, 0xAF, 0xD9, 0x2F, 0xE1, 0xFF, 0x00, 0xFC, 0x25, 0xB2, 0x47, 0x8F,
+	0xB4, 0x37, 0xF6, 0xB5, 0xA5, 0x87, 0xD9, 0x32, 0xAE, 0x57, 0xFE, 0x3F, 0x0C, 0x5E, 0x66, 0xEF,
+	0x22, 0x6E, 0x9F, 0x77, 0x67, 0xBA, 0xE7, 0xF4, 0x6B, 0xF6, 0x10, 0xFF, 0x00, 0x82, 0x15, 0xFC,
+	0x35, 0xF8, 0x37, 0xAB, 0x5B, 0xFC, 0x5D, 0xFD, 0xA2, 0x3C, 0x4A, 0x3C, 0x75, 0xE3, 0xAB, 0x22,
+	0xC2, 0xC2, 0x46, 0xB3, 0x9F, 0x4B, 0x1A, 0x66, 0xF1, 0x71, 0x04, 0x87, 0xFD, 0x16, 0xF5, 0xE1,
+	0x9B, 0xCC, 0x81, 0xE3, 0xEA, 0xA7, 0x6F, 0x97, 0xC7, 0xCC, 0xC4, 0xD7, 0xE8, 0x47, 0x86, 0xFC,
+	0x25, 0xA1, 0xF8, 0x4B, 0x45, 0xB7, 0xF0, 0xFE, 0x81, 0x6C, 0xD0, 0x5A, 0xDA, 0xEE, 0xF2, 0x63,
+	0xF3, 0x0B, 0x6D, 0xDC, 0xC5, 0x9B, 0x96, 0x24, 0x9C, 0x92, 0x7F, 0x3A, 0xD2, 0x00, 0x0E, 0x82,
+	0x82, 0xE3, 0x4C, 0x87, 0x4E, 0xD3, 0xAC, 0xF4, 0x9B, 0x34, 0xD3, 0xF4, 0xF8, 0x7C, 0xB8, 0x63,
+	0xCE, 0xC4, 0xDC, 0x4E, 0x32, 0x72, 0x79, 0x3C, 0xF5, 0x35, 0x35, 0x14, 0x50, 0x6A, 0x14, 0x51,
+	0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51,
+	0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51,
+	0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51,
+	0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51,
+	0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51,
+	0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51,
+	0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51,
+	0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51,
+	0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51,
+	0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x55, 0xD6, 0x34, 0x6D, 0x37, 0x5E,
+	0xB1, 0x6D, 0x3B, 0x54, 0xB6, 0xF3, 0x21, 0x7C, 0x6E, 0x5D, 0xC5, 0x7A, 0x10, 0x7A, 0x8C, 0x1E,
+	0xA2, 0xBE, 0x5F, 0xF8, 0xDB, 0xFF, 0x00, 0x04, 0x5D, 0xFF, 0x00, 0x82, 0x75, 0xFC, 0x7B, 0xBF,
+	0x93, 0x5D, 0xF1, 0xDF, 0xC0, 0x2F, 0x3B, 0x54, 0x6D, 0xBE, 0x5E, 0xA1, 0xFF, 0x00, 0x09, 0x56,
+	0xAE, 0xBB, 0x38, 0x8D, 0x4F, 0xEE, 0xE3, 0xBC, 0x45, 0x39, 0x58, 0xD5, 0x7F, 0x5E, 0xB9, 0xCF,
+	0xD5, 0x54, 0x50, 0x07, 0xE7, 0x5F, 0x89, 0x3F, 0xE0, 0xDE, 0x3F, 0x83, 0x16, 0xFA, 0x94, 0xD7,
+	0xFF, 0x00, 0x09, 0x3E, 0x2B, 0x7F, 0xC2, 0x2D, 0x0C, 0xBB, 0x73, 0x6D, 0xFD, 0x85, 0x73, 0x7D,
+	0xD1, 0x40, 0xFB, 0xD3, 0x5F, 0xFA, 0xEF, 0x3F, 0xF0, 0x3F, 0x61, 0x5F, 0x05, 0xF8, 0x23, 0xE2,
+	0xEF, 0xEC, 0xEF, 0xE0, 0x49, 0xE0, 0xD0, 0x7E, 0x24, 0xFC, 0x64, 0xFB, 0x54, 0x87, 0x76, 0xEB,
+	0x9F, 0xF8, 0x47, 0x6E, 0xE3, 0xC7, 0x0C, 0xDF, 0x76, 0x24, 0x3F, 0xDE, 0x51, 0xD7, 0xB7, 0xD6,
+	0xBF, 0xA0, 0x77, 0x04, 0xA3, 0x00, 0xB9, 0xE3, 0xA7, 0xAD, 0x7F, 0x22, 0x5F, 0xF0, 0x51, 0xED,
+	0x22, 0x2F, 0x0D, 0x78, 0xC6, 0x4D, 0x11, 0x23, 0xF2, 0x87, 0xCB, 0x98, 0xB7, 0x6E, 0xCF, 0xEE,
+	0xED, 0x9B, 0xAE, 0x4F, 0xAF, 0xAD, 0x04, 0xF2, 0xAB, 0x1F, 0xA6, 0x1E, 0x34, 0xF8, 0xAF, 0xFB,
+	0x3C, 0x78, 0x4B, 0x44, 0x8E, 0xF3, 0x52, 0xF8, 0xA7, 0xE6, 0x69, 0xF2, 0x67, 0x03, 0xFB, 0x0E,
+	0xEC, 0x74, 0x65, 0x1D, 0x94, 0xB7, 0xDE, 0x23, 0xFF, 0x00, 0xD5, 0x5C, 0x4C, 0x5F, 0xB4, 0xB7,
+	0xEC, 0xDF, 0xAD, 0xDC, 0x22, 0xF8, 0x4F, 0xC6, 0x5E, 0x75, 0xAA, 0xE7, 0xCD, 0x8F, 0xFB, 0x3E,
+	0xF1, 0x73, 0xC7, 0x1C, 0xBC, 0x60, 0xF5, 0x06, 0xBF, 0x2A, 0x75, 0xEB, 0x68, 0x35, 0x1B, 0xA8,
+	0x53, 0x6F, 0x97, 0xE5, 0x6E, 0xF5, 0x39, 0xC8, 0x15, 0x89, 0xAB, 0x35, 0xBB, 0xAE, 0xF7, 0xB7,
+	0xCA, 0xB7, 0xF0, 0xEF, 0x3E, 0xD5, 0xA7, 0x31, 0x97, 0xB3, 0x3F, 0x61, 0x2D, 0xBE, 0x25, 0x7C,
+	0x2A, 0xD6, 0x38, 0xD3, 0xB5, 0xAF, 0xFC, 0x97, 0x9F, 0xFA, 0xA8, 0xF4, 0xAD, 0x1B, 0x58, 0xF4,
+	0x4B, 0xF9, 0x17, 0xEC, 0x5A, 0xDE, 0x4B, 0x7D, 0xDF, 0xF4, 0x66, 0xFE, 0xB5, 0xF8, 0xB6, 0x75,
+	0x6B, 0x8B, 0x0E, 0x6C, 0x4F, 0x95, 0xF9, 0x37, 0xF3, 0x14, 0x2F, 0xC4, 0x7F, 0x1B, 0xDB, 0x9F,
+	0xF4, 0x7D, 0x77, 0x6F, 0xB7, 0xD9, 0x62, 0x3F, 0xCD, 0x68, 0x52, 0xD4, 0x3D, 0x99, 0xFB, 0x5E,
+	0x9A, 0x24, 0x3D, 0x7E, 0xD7, 0xE6, 0x7F, 0xDB, 0x32, 0x3F, 0xAD, 0x25, 0xDE, 0x87, 0x04, 0x96,
+	0xAC, 0xA7, 0xF7, 0x23, 0x8F, 0xDF, 0x72, 0xDB, 0x79, 0xF4, 0xCF, 0xE1, 0x5F, 0x8B, 0x56, 0xFF,
+	0x00, 0x1A, 0x3E, 0x24, 0x59, 0x9C, 0xC3, 0xE2, 0x3C, 0x7F, 0xDB, 0x9C, 0x3F, 0xFC, 0x45, 0x69,
+	0xE9, 0x9F, 0xB4, 0xFF, 0x00, 0xC6, 0x1D, 0x12, 0xEA, 0x3B, 0xEB, 0x3F, 0x13, 0xED, 0x92, 0x3C,
+	0xED, 0xFF, 0x00, 0x42, 0xB7, 0xEE, 0x08, 0xEF, 0x11, 0xF5, 0xAD, 0x7D, 0xA4, 0x43, 0xD9, 0x9F,
+	0xB0, 0xE9, 0xE1, 0xBB, 0x4C, 0xF1, 0xAA, 0xEF, 0xFF, 0x00, 0xB6, 0x04, 0x7F, 0x5A, 0x7C, 0x9E,
+	0x1D, 0xB4, 0x54, 0x67, 0x53, 0x93, 0xEB, 0xCF, 0xF8, 0xD7, 0xE4, 0x7D, 0xBF, 0xED, 0xD9, 0xFB,
+	0x42, 0xD9, 0xF3, 0x1F, 0x8C, 0x3F, 0xF2, 0x9F, 0x69, 0xFF, 0x00, 0xC6, 0x2A, 0xF5, 0xBF, 0xFC,
+	0x14, 0x5B, 0xF6, 0x92, 0xB4, 0x93, 0x73, 0xF8, 0xB7, 0x7A, 0x8F, 0xE1, 0xFB, 0x05, 0x98, 0xCF,
+	0xFE, 0x4B, 0xD1, 0xED, 0x22, 0x27, 0x4D, 0xD8, 0xFD, 0x60, 0x5F, 0x0D, 0x47, 0x2F, 0x51, 0xFE,
+	0x7F, 0x3A, 0x2E, 0x3C, 0x1D, 0x02, 0xC0, 0xD2, 0x34, 0x5B, 0xB1, 0xFE, 0xD1, 0x1D, 0xFE, 0xB5,
+	0xF9, 0x5B, 0x07, 0xFC, 0x14, 0xCB, 0xF6, 0x89, 0x80, 0xE7, 0xFB, 0x6B, 0x3F, 0xF6, 0xEF, 0x69,
+	0xFF, 0x00, 0xC8, 0xD5, 0x7A, 0xDB, 0xFE, 0x0A, 0x97, 0xFB, 0x43, 0x40, 0xC0, 0xB5, 0xF6, 0xE0,
+	0x3B, 0x79, 0x76, 0x83, 0x3F, 0xF9, 0x2D, 0x47, 0xB4, 0x89, 0x9F, 0xB2, 0x99, 0xFA, 0x73, 0xFF,
+	0x00, 0x08, 0x75, 0x9C, 0x9F, 0xF2, 0xE3, 0xFF, 0x00, 0x91, 0x4F, 0xF8, 0xD3, 0x25, 0xF8, 0x7D,
+	0x61, 0xE5, 0x97, 0x96, 0xC3, 0xE5, 0xFF, 0x00, 0xAE, 0xA7, 0xFF, 0x00, 0x8A, 0xAF, 0xCD, 0x58,
+	0x3F, 0xE0, 0xAB, 0xDF, 0xB4, 0x0C, 0x3D, 0x5F, 0x77, 0xE1, 0x69, 0xFF, 0x00, 0xC8, 0xB5, 0x68,
+	0x7F, 0xC1, 0x5C, 0x3E, 0x3E, 0xAA, 0xE2, 0x5B, 0x7D, 0xCB, 0xDC, 0x6E, 0xB5, 0x19, 0xFF, 0x00,
+	0xC9, 0x5A, 0x3D, 0xA4, 0x43, 0xD9, 0x4C, 0xFD, 0x1A, 0xFF, 0x00, 0x84, 0x07, 0x45, 0xFF, 0x00,
+	0x9F, 0x1F, 0xFC, 0x8A, 0xDF, 0xFC, 0x55, 0x41, 0xA9, 0xF8, 0x17, 0x48, 0x8A, 0xCA, 0x49, 0x23,
+	0xB0, 0xF9, 0x86, 0x3F, 0xE5, 0xAB, 0x7A, 0x8F, 0xF6, 0xAB, 0xF3, 0xB3, 0xFE, 0x1E, 0xE3, 0xF1,
+	0xCB, 0xFE, 0x81, 0xBF, 0xF9, 0x1A, 0xD7, 0xFF, 0x00, 0x91, 0x69, 0xD1, 0x7F, 0xC1, 0x5C, 0xBE,
+	0x38, 0x09, 0x01, 0x93, 0x4A, 0xDC, 0xBF, 0xDD, 0xF3, 0xED, 0x87, 0xFE, 0xDA, 0xD1, 0xED, 0x22,
+	0x1E, 0xCA, 0x67, 0xDF, 0xC9, 0xE1, 0x1B, 0x3E, 0xBF, 0xD9, 0xDF, 0xF9, 0x18, 0xFF, 0x00, 0x8D,
+	0x58, 0xB6, 0xF0, 0x7D, 0x93, 0xCC, 0xAA, 0xFA, 0x77, 0xFE, 0x46, 0x3F, 0xE3, 0x5F, 0x00, 0xAF,
+	0xFC, 0x15, 0xDB, 0xE3, 0x32, 0xFF, 0x00, 0xCC, 0xBF, 0xFF, 0x00, 0x93, 0x56, 0xFF, 0x00, 0xFC,
+	0x89, 0x4F, 0x4F, 0xF8, 0x2B, 0xE7, 0xC6, 0x74, 0xE4, 0x78, 0x7B, 0xFF, 0x00, 0x26, 0xED, 0xBF,
+	0xF9, 0x12, 0x8F, 0x69, 0x10, 0xF6, 0x53, 0x3F, 0x41, 0x7F, 0xE1, 0x08, 0xD3, 0x7F, 0xE8, 0x1D,
+	0xFF, 0x00, 0x91, 0x9B, 0xFF, 0x00, 0x8A, 0xA3, 0xFE, 0x10, 0x3D, 0x36, 0x6F, 0xDD, 0xFF, 0x00,
+	0x67, 0xF5, 0xFF, 0x00, 0xA6, 0xCD, 0xFF, 0x00, 0xC5, 0x57, 0xE7, 0xEA, 0xFF, 0x00, 0xC1, 0x5F,
+	0xFE, 0x34, 0x37, 0xFC, 0xC0, 0x3F, 0xF2, 0x6A, 0xDB, 0xFF, 0x00, 0x91, 0x29, 0xCF, 0xFF, 0x00,
+	0x05, 0x7B, 0xF8, 0xD6, 0x17, 0x2B, 0xA1, 0x60, 0xFF, 0x00, 0xD7, 0xD5, 0xB7, 0xFF, 0x00, 0x22,
+	0x51, 0xED, 0x22, 0x1E, 0xCA, 0x67, 0xE8, 0x07, 0xFC, 0x2B, 0x5D, 0x37, 0xFE, 0x7C, 0xBF, 0xF2,
+	0x23, 0x7F, 0xF1, 0x54, 0xA9, 0xF0, 0xCB, 0x4D, 0x91, 0xB6, 0x7D, 0x93, 0x6F, 0xFB, 0x5E, 0x63,
+	0x7F, 0xF1, 0x55, 0xF9, 0xFA, 0xBF, 0xF0, 0x57, 0xAF, 0x8D, 0xE7, 0xFE, 0x61, 0x3F, 0xF9, 0x31,
+	0x6D, 0xFF, 0x00, 0xC8, 0x94, 0xF1, 0xFF, 0x00, 0x05, 0x75, 0xF8, 0xDA, 0x4E, 0x25, 0xD1, 0xF7,
+	0x2F, 0x71, 0xF6, 0x8B, 0x6F, 0xFE, 0x44, 0xA3, 0xDA, 0x44, 0x3D, 0x94, 0xCF, 0xD0, 0x2F, 0xF8,
+	0x55, 0x3A, 0x6F, 0xF7, 0x7F, 0xF4, 0x2F, 0xFE, 0x2A, 0x9D, 0x0F, 0xC3, 0x2D, 0x2E, 0xD2, 0x51,
+	0x70, 0xD0, 0xEE, 0x0B, 0xFC, 0x3B, 0x98, 0x67, 0xFF, 0x00, 0x1E, 0xAF, 0xCF, 0xD5, 0xFF, 0x00,
+	0x82, 0xB7, 0x7C, 0x63, 0x6E, 0x9A, 0x07, 0xFE, 0x4D, 0x5B, 0xFF, 0x00, 0xF2, 0x2D, 0x3C, 0x7F,
+	0xC1, 0x5A, 0x3E, 0x32, 0xBF, 0x09, 0xA2, 0xED, 0x6F, 0x5F, 0xB4, 0xDB, 0x9F, 0xFD, 0xB5, 0xA3,
+	0xDA, 0x44, 0x3D, 0x94, 0xCF, 0xD0, 0x7F, 0xF8, 0x43, 0x34, 0x5F, 0xFA, 0x06, 0xFF, 0x00, 0xE4,
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+	0x56, 0xE4, 0x5B, 0xB7, 0x89, 0x4E, 0x9F, 0xB6, 0xEB, 0x6E, 0xFF, 0x00, 0x2B, 0xEC, 0xFA, 0x95,
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+	0x00, 0x35, 0xDF, 0xB2, 0xB6, 0xA9, 0xAD, 0xFC, 0x4A, 0x49, 0x5F, 0x59, 0xD1, 0xFE, 0xCF, 0xA9,
+	0xC5, 0xB7, 0xED, 0xBA, 0x5F, 0xDA, 0x15, 0xFE, 0xCF, 0x9F, 0x3B, 0x67, 0xEF, 0x14, 0x2A, 0xBE,
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+	0x08, 0x31, 0x16, 0x9D, 0xA6, 0x5A, 0x66, 0xEA, 0xEE, 0xE5, 0xD8, 0xEE, 0x92, 0x49, 0x64, 0xFD,
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+	0xAF, 0x5E, 0xB4, 0xF8, 0x91, 0xA2, 0x6B, 0x11, 0xAC, 0xDA, 0xB1, 0xFB, 0x64, 0xD2, 0x7F, 0xC7,
+	0x8D, 0xE7, 0xCD, 0x1E, 0xEC, 0x7D, 0xFF, 0x00, 0x90, 0x28, 0x03, 0x00, 0x01, 0xCF, 0xA6, 0x45,
+	0x00, 0x7C, 0xC7, 0xAA, 0xFC, 0x1F, 0xF1, 0x0D, 0xA5, 0x97, 0xF6, 0xB6, 0x8F, 0xE1, 0xEF, 0xB7,
+	0x43, 0xFF, 0x00, 0x3F, 0xDF, 0x6B, 0x48, 0xB3, 0xC8, 0x1F, 0x71, 0x9F, 0x3D, 0x72, 0x3F, 0x0C,
+	0xD7, 0x17, 0xA8, 0x69, 0x3A, 0x94, 0x11, 0xBE, 0xA1, 0x7B, 0x0F, 0x98, 0xB0, 0xE3, 0x77, 0xCC,
+	0xA3, 0x19, 0xE3, 0xB1, 0xAF, 0xB1, 0x2F, 0xFE, 0x16, 0x7C, 0x05, 0xB9, 0x3F, 0xF0, 0x90, 0x78,
+	0x56, 0xDF, 0xFB, 0x3F, 0x58, 0x3D, 0x6E, 0x77, 0x5D, 0x4D, 0xFE, 0xCF, 0xDD, 0x76, 0xDB, 0xF7,
+	0x32, 0x3A, 0x77, 0xF5, 0xAE, 0x7E, 0xFB, 0x47, 0xF1, 0x0D, 0xA5, 0xC0, 0xD6, 0xBC, 0x61, 0xE3,
+	0xDF, 0xED, 0x68, 0x2D, 0xFF, 0x00, 0xE5, 0xC7, 0xFB, 0x2D, 0x20, 0xDF, 0xB8, 0x6D, 0xFB, 0xE8,
+	0x72, 0x30, 0x70, 0x7A, 0x73, 0x8C, 0x77, 0xA0, 0x0F, 0x94, 0x6D, 0xAF, 0x26, 0x3C, 0xC2, 0xBB,
+	0x3F, 0x5A, 0xB3, 0x75, 0xA8, 0xEB, 0x90, 0xDA, 0x34, 0x83, 0x51, 0xC0, 0x18, 0xF9, 0x7C, 0x95,
+	0xF5, 0xAF, 0xA1, 0x6F, 0x74, 0xEB, 0xED, 0x74, 0xB3, 0x2F, 0xC1, 0x4F, 0x32, 0x0E, 0xD3, 0xFF,
+	0x00, 0xC2, 0x48, 0x17, 0x3F, 0x87, 0x07, 0xA8, 0xC5, 0x64, 0xC9, 0xF0, 0xEB, 0xE1, 0x7B, 0xDA,
+	0xC9, 0x7B, 0xE2, 0x7F, 0x08, 0x7F, 0x66, 0xC6, 0x98, 0xF3, 0x24, 0xFE, 0xD0, 0x9E, 0x6D, 0xB9,
+	0x38, 0x1C, 0x23, 0x73, 0xDB, 0xF3, 0xF6, 0xA0, 0x0F, 0x04, 0x5D, 0x77, 0x55, 0xEB, 0x26, 0xA3,
+	0xFF, 0x00, 0x90, 0x57, 0xFC, 0x29, 0x67, 0xD7, 0xF5, 0x0F, 0x25, 0xBC, 0x8B, 0xFD, 0xD2, 0x7F,
+	0x08, 0xF2, 0x87, 0x3C, 0xFD, 0x2B, 0xD9, 0xAE, 0x7E, 0x1F, 0x7E, 0xCE, 0xD3, 0x8C, 0x45, 0xA8,
+	0xFF, 0x00, 0xE4, 0x1B, 0xBF, 0xFE, 0x2A, 0xAA, 0x0F, 0x84, 0x5F, 0x03, 0xEE, 0xE6, 0x11, 0x59,
+	0xEB, 0x5E, 0x5B, 0x9F, 0xBA, 0xFF, 0x00, 0x66, 0xB9, 0x6C, 0x7E, 0x05, 0xE8, 0x03, 0xC8, 0xED,
+	0x75, 0xFD, 0x6C, 0x1C, 0xC9, 0x71, 0xFF, 0x00, 0x8E, 0xAF, 0xF8, 0x55, 0xB9, 0x3C, 0x45, 0x7B,
+	0x14, 0x0D, 0x24, 0xD2, 0xEE, 0x55, 0xFE, 0x1D, 0xA3, 0xD7, 0xE9, 0x5E, 0xA3, 0x27, 0xC0, 0x6F,
+	0x85, 0x8F, 0xF7, 0x7C, 0x69, 0xB7, 0xFE, 0xE1, 0xD3, 0xFF, 0x00, 0xF1, 0x75, 0x08, 0xFD, 0x9E,
+	0x7E, 0x1D, 0x3B, 0x81, 0x67, 0xE3, 0xDC, 0x49, 0xFC, 0x3F, 0xF1, 0x2B, 0x9B, 0xFA, 0xC9, 0x40,
+	0x1E, 0x5B, 0xFF, 0x00, 0x09, 0x7B, 0x7F, 0xCF, 0x3F, 0xD7, 0xFF, 0x00, 0xAD, 0x4E, 0x8B, 0xC5,
+	0xFF, 0x00, 0xBC, 0x1B, 0xA3, 0xE3, 0xEB, 0xFF, 0x00, 0xD6, 0xAF, 0x53, 0xFF, 0x00, 0x86, 0x74,
+	0xF0, 0xB7, 0xFD, 0x0F, 0xFF, 0x00, 0xF9, 0x4A, 0x7F, 0xFE, 0x39, 0x4D, 0x9F, 0xF6, 0x74, 0xF0,
+	0xD0, 0x88, 0xF9, 0x5E, 0x3D, 0xDC, 0xDD, 0x87, 0xF6, 0x5B, 0xFF, 0x00, 0xF1, 0xCA, 0x00, 0xF3,
+	0x4F, 0xF8, 0x4B, 0xE2, 0xFF, 0x00, 0x9E, 0x7F, 0xAF, 0xFF, 0x00, 0x5A, 0x99, 0x71, 0xE2, 0xE8,
+	0xCC, 0x2C, 0x16, 0x3F, 0xFC, 0x7B, 0xFF, 0x00, 0xAD, 0x5E, 0x88, 0xDF, 0xB3, 0xC6, 0x8E, 0x38,
+	0xFF, 0x00, 0x84, 0xD7, 0xFF, 0x00, 0x29, 0xAD, 0xFF, 0x00, 0xC7, 0x29, 0x23, 0xFD, 0x9E, 0xF4,
+	0x67, 0x70, 0xAD, 0xE3, 0x4C, 0x7F, 0xDC, 0x35, 0xBF, 0xF8, 0xE5, 0x00, 0x79, 0x97, 0xFC, 0x25,
+	0xBF, 0xF4, 0xCB, 0xFF, 0x00, 0x1E, 0xFF, 0x00, 0xEB, 0x53, 0xA1, 0xF1, 0x4C, 0xB2, 0x48, 0x12,
+	0x11, 0xB5, 0xBB, 0x37, 0x5C, 0x7E, 0x95, 0xEA, 0x1F, 0xF0, 0xCE, 0xBA, 0x0F, 0xFD, 0x0F, 0x1F,
+	0xF9, 0x4D, 0x6F, 0xFE, 0x39, 0x4D, 0x97, 0xF6, 0x79, 0xF0, 0xCC, 0x51, 0x97, 0xBB, 0xF1, 0xAE,
+	0xE8, 0xC7, 0xDE, 0x5F, 0xEC, 0xD7, 0x1F, 0xCA, 0x4A, 0x00, 0xF3, 0x8F, 0xF8, 0x48, 0x35, 0x4F,
+	0xF9, 0xF9, 0xFF, 0x00, 0xC7, 0x17, 0xFC, 0x29, 0x97, 0x1E, 0x20, 0xD4, 0x44, 0x2D, 0xE6, 0x5D,
+	0xED, 0x5F, 0x5F, 0x2C, 0x7F, 0x85, 0x77, 0xD3, 0xFC, 0x16, 0xF8, 0x59, 0x69, 0xCD, 0xDF, 0x8E,
+	0x3C, 0xBF, 0xFB, 0x86, 0xCE, 0x7F, 0x93, 0xD5, 0x1B, 0xBF, 0x03, 0xFC, 0x01, 0xD2, 0x62, 0x6B,
+	0xBD, 0x43, 0xE2, 0x0F, 0x9D, 0x1A, 0x7D, 0xE8, 0x7F, 0xB2, 0x6E, 0x97, 0x76, 0x78, 0xEA, 0x1B,
+	0xDF, 0x34, 0x01, 0xC0, 0xCF, 0xAB, 0xDF, 0xCD, 0xC2, 0x6A, 0x1F, 0xF9, 0x04, 0x7F, 0x85, 0x43,
+	0x6D, 0x79, 0xAA, 0xC3, 0x70, 0xB3, 0xCD, 0xA8, 0x7C, 0x83, 0xEF, 0x7E, 0xE5, 0x7D, 0x2B, 0xD2,
+	0xB4, 0xB8, 0xFF, 0x00, 0x65, 0xD4, 0x3F, 0xF2, 0x19, 0xDD, 0xFF, 0x00, 0x6E, 0xF7, 0xA3, 0xD6,
+	0xBA, 0x1B, 0x33, 0xFB, 0x30, 0xC8, 0x36, 0x5B, 0xDB, 0x7D, 0xBA, 0x43, 0xF7, 0x6D, 0xB7, 0xDE,
+	0xC5, 0xBF, 0xFE, 0x05, 0xDB, 0x1D, 0x7F, 0x0A, 0x00, 0xF1, 0xD6, 0xBF, 0x9A, 0x7E, 0xB7, 0x1B,
+	0xBF, 0xE0, 0x00, 0x52, 0xC0, 0x6E, 0xAD, 0xE6, 0x5B, 0x88, 0x47, 0x96, 0xCB, 0xF7, 0x64, 0xE0,
+	0xE3, 0xF0, 0xAF, 0x61, 0xD5, 0xED, 0xF4, 0xBD, 0x2A, 0x2F, 0xB4, 0x78, 0x1F, 0xE0, 0x2F, 0xDB,
+	0x23, 0xFE, 0xFF, 0x00, 0xFC, 0x25, 0x0D, 0x1F, 0xA7, 0x69, 0x3E, 0xAD, 0xF9, 0x7D, 0x2B, 0x5F,
+	0xC3, 0x96, 0xBA, 0xFF, 0x00, 0x89, 0xB4, 0xC6, 0x82, 0xD6, 0x1F, 0xF8, 0x46, 0xAF, 0x9B, 0x1E,
+	0x4C, 0x9B, 0x92, 0xF3, 0x67, 0xCC, 0x73, 0xC1, 0xC2, 0x9C, 0xA8, 0xEF, 0xFD, 0xEF, 0x6A, 0x00,
+	0xF2, 0x4F, 0x0F, 0x7C, 0x38, 0xF1, 0x97, 0x8C, 0x1F, 0xCC, 0xF0, 0xE7, 0x86, 0xB7, 0x37, 0x7B,
+	0x8F, 0xB6, 0x47, 0xEF, 0xFC, 0x2C, 0xC3, 0xFB, 0xA4, 0x55, 0xB6, 0xF0, 0x9F, 0x87, 0xBC, 0x33,
+	0xAD, 0xC3, 0xA7, 0x78, 0x8B, 0x51, 0xFB, 0x46, 0xB8, 0xDB, 0xBE, 0xCB, 0x67, 0xE4, 0xBA, 0x6F,
+	0xF9, 0x72, 0xDF, 0x3A, 0x92, 0x83, 0x08, 0x41, 0xE7, 0xE9, 0xD6, 0xBD, 0xAA, 0xD7, 0xE0, 0xA4,
+	0x1A, 0xEA, 0x83, 0xF1, 0x27, 0xC5, 0xDF, 0xDB, 0x51, 0x8F, 0xF9, 0x67, 0xFD, 0x9E, 0x6D, 0xBF,
+	0x58, 0x9C, 0x77, 0x0B, 0xFF, 0x00, 0x7C, 0xFB, 0x9A, 0xEB, 0xB4, 0x98, 0x3E, 0x1B, 0x78, 0x0B,
+	0x4D, 0x6D, 0x2F, 0x41, 0xD2, 0xFE, 0xC9, 0x6A, 0x71, 0xE6, 0x47, 0xE7, 0xCD, 0x26, 0x7E, 0x62,
+	0x47, 0x2D, 0x93, 0xD5, 0x8F, 0xE7, 0x40, 0x1E, 0x23, 0xE1, 0x3F, 0xD9, 0xD7, 0xC4, 0x1E, 0x2E,
+	0x9B, 0xFB, 0x63, 0xC5, 0x51, 0x79, 0x30, 0xAF, 0xFA, 0xB5, 0xDC, 0x8D, 0xEA, 0xA7, 0xEE, 0x48,
+	0x0F, 0x50, 0x3B, 0x56, 0x4F, 0xC5, 0xDD, 0x3F, 0x4B, 0xF0, 0x5E, 0x85, 0x71, 0x26, 0xAD, 0x07,
+	0x93, 0x6F, 0x6F, 0xB3, 0xF7, 0xDB, 0x99, 0xB1, 0xB9, 0x93, 0xB0, 0xC9, 0xEA, 0xC0, 0x57, 0xB2,
+	0x7C, 0x42, 0xF8, 0xD5, 0xE1, 0xDF, 0x0F, 0xC3, 0x1D, 0xE6, 0xAD, 0xAE, 0xFF, 0x00, 0xA3, 0xDC,
+	0x67, 0xFB, 0x3E, 0x3F, 0xB2, 0xBF, 0xEF, 0xF6, 0xED, 0x0F, 0xC8, 0x42, 0x57, 0x69, 0x23, 0xAF,
+	0x5E, 0xD5, 0xCF, 0xFF, 0x00, 0xC1, 0x3E, 0xFF, 0x00, 0x62, 0xEF, 0x8C, 0x3F, 0xF0, 0x5A, 0x2F,
+	0xDA, 0x62, 0x6F, 0x03, 0x78, 0x7E, 0xE3, 0xFE, 0x11, 0xEF, 0x87, 0x3A, 0x0E, 0xDF, 0xF8, 0x4D,
+	0x3C, 0x45, 0xB6, 0xDE, 0xEF, 0xEC, 0x1E, 0x7D, 0x95, 0xCC, 0x96, 0x7F, 0xE8, 0xED, 0x35, 0xB4,
+	0xF2, 0xEF, 0xB8, 0xB1, 0x31, 0xFE, 0xE8, 0x9D, 0xBB, 0xB7, 0x36, 0x14, 0x61, 0x80, 0x3F, 0x42,
+	0x7F, 0xE0, 0xD3, 0x5F, 0xD9, 0x06, 0xE3, 0xC1, 0xDF, 0x0D, 0xBC, 0x65, 0xFB, 0x6B, 0x78, 0xA6,
+	0x1F, 0x93, 0xE2, 0x97, 0xF6, 0x77, 0xFC, 0x22, 0xCB, 0xB8, 0x7E, 0xE7, 0xFB, 0x36, 0x6D, 0x62,
+	0xC2, 0xE7, 0xEE, 0x4A, 0x77, 0x67, 0x70, 0xFF, 0x00, 0x59, 0x1A, 0x63, 0xF8, 0x77, 0x7D, 0xEA,
+	0xFD, 0x91, 0x8A, 0x3F, 0x2A, 0x31, 0x1E, 0x73, 0x8A, 0xE6, 0x7E, 0x17, 0x7C, 0x1C, 0xF8, 0x7B,
+	0xF0, 0x63, 0xC1, 0xDA, 0x6F, 0xC3, 0xEF, 0x86, 0xFA, 0x0F, 0xF6, 0x76, 0x8B, 0xA3, 0xF9, 0xDF,
+	0xD9, 0x76, 0x3F, 0x6A, 0x9A, 0x6F, 0x23, 0xCD, 0x91, 0xE4, 0x93, 0xE7, 0x95, 0xD9, 0xDB, 0x73,
+	0xBB, 0x1F, 0x98, 0x9C, 0x67, 0x03, 0x00, 0x01, 0x5D, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14, 0x51, 0x45, 0x00, 0x14,
+	0x51, 0x45, 0x00, 0x7E, 0x44, 0x7F, 0xC1, 0x50, 0x7F, 0xE0, 0xD7, 0x5F, 0x86, 0x5F, 0xB4, 0x3F,
+	0x89, 0xEE, 0x3E, 0x39, 0xFE, 0xC6, 0xDE, 0x32, 0xFF, 0x00, 0x84, 0x13, 0xC5, 0x1F, 0x27, 0xDA,
+	0x34, 0xBF, 0xEC, 0xF9, 0xB5, 0x4F, 0xB7, 0xFC, 0x96, 0x96, 0xEB, 0xFB, 0xDB, 0xED, 0x49, 0x23,
+	0x8B, 0x64, 0x51, 0xCE, 0xDC, 0x2F, 0xCD, 0xE6, 0x63, 0xAA, 0xA9, 0x3F, 0x8E, 0xDF, 0xB5, 0x47,
+	0xEC, 0x93, 0xFF, 0x00, 0x05, 0x1D, 0xFD, 0x82, 0x6D, 0x6E, 0x8F, 0xED, 0x81, 0xF0, 0xAF, 0xFB,
+	0x07, 0x48, 0x8B, 0x67, 0x97, 0xAC, 0xFF, 0x00, 0x6E, 0x68, 0xF7, 0x5B, 0x72, 0x62, 0xCF, 0xEE,
+	0x6C, 0xA5, 0x95, 0x8E, 0x5E, 0xE2, 0x14, 0xFF, 0x00, 0x81, 0x67, 0xA0, 0x6C, 0x7F, 0x5F, 0xD2,
+	0x46, 0x93, 0x46, 0x62, 0x95, 0x77, 0x2B, 0x75, 0x14, 0x8C, 0x92, 0x90, 0xDB, 0x67, 0x23, 0x3F,
+	0x77, 0xE5, 0x1C, 0x50, 0x07, 0xF1, 0x4D, 0xE1, 0xEF, 0xDB, 0x33, 0xCD, 0x3F, 0xD9, 0x90, 0xB7,
+	0x99, 0xFF, 0x00, 0x4D, 0x71, 0x8F, 0x53, 0xD3, 0xC9, 0xAE, 0xCB, 0x4D, 0xFD, 0xA6, 0xBC, 0x43,
+	0x29, 0x5D, 0x36, 0xC2, 0x7D, 0xB2, 0x4B, 0xF7, 0x26, 0xDA, 0x9F, 0x2E, 0x32, 0x4F, 0x06, 0x3E,
+	0x7D, 0x2B, 0xFA, 0x98, 0xFD, 0xA6, 0xFF, 0x00, 0xE0, 0x91, 0x7F, 0xF0, 0x4F, 0x8F, 0xDB, 0x1A,
+	0x66, 0xBB, 0xFD, 0xA3, 0x7E, 0x00, 0xFF, 0x00, 0xC2, 0x45, 0x33, 0xE3, 0x74, 0x9F, 0xF0, 0x95,
+	0x6A, 0xD6, 0x99, 0xC0, 0x88, 0x74, 0xB5, 0xBB, 0x8C, 0x74, 0x86, 0x2F, 0xFB, 0xE7, 0xDC, 0xE7,
+	0xE2, 0x6F, 0x8B, 0x1F, 0xF0, 0x68, 0x47, 0xEC, 0x0F, 0xE2, 0x39, 0xE4, 0xBC, 0xF8, 0x23, 0xAC,
+	0x7F, 0xC2, 0x07, 0x37, 0x1F, 0x67, 0x93, 0xEC, 0xFA, 0xAE, 0xA9, 0xE5, 0x70, 0x81, 0xB8, 0xB8,
+	0xD5, 0x80, 0x6C, 0x81, 0x27, 0x5E, 0x9E, 0x67, 0xFB, 0x22, 0x80, 0x3F, 0x18, 0xEE, 0x7F, 0x68,
+	0xCD, 0x5E, 0x14, 0x44, 0xF1, 0x0E, 0xAB, 0xBA, 0x3E, 0x7F, 0xE5, 0x82, 0xFF, 0x00, 0xEC, 0xB1,
+	0xFA, 0xE2, 0xA2, 0xD6, 0xFE, 0x3D, 0xBD, 0xC1, 0x59, 0x3C, 0x2D, 0x3F, 0xC9, 0xCE, 0xE6, 0xDB,
+	0xF4, 0xFE, 0xFA, 0x7D, 0x6B, 0xF4, 0x4B, 0xE2, 0x9F, 0xFC, 0x19, 0xD9, 0xF1, 0xAB, 0x49, 0x95,
+	0xE4, 0xF8, 0x5B, 0xFB, 0x77, 0xFD, 0xBE, 0x1E, 0x36, 0xDA, 0xFF, 0x00, 0xC2, 0xAF, 0xB6, 0x8B,
+	0xFB, 0x9F, 0xC5, 0x36, 0xAD, 0x9E, 0xA5, 0xCF, 0xE1, 0xF4, 0xAF, 0x18, 0xF1, 0x27, 0xFC, 0x1A,
+	0xCF, 0xFF, 0x00, 0x05, 0x30, 0xF0, 0x86, 0x91, 0x70, 0x3C, 0x23, 0x7D, 0xFF, 0x00, 0x09, 0x4D,
+	0xC7, 0xC9, 0xE4, 0xDB, 0xF9, 0x5A, 0x35, 0x8F, 0x9B, 0xF3, 0x0C, 0xFC, 0xCF, 0xA9, 0x90, 0xB8,
+	0x04, 0x9E, 0x7A, 0xEC, 0xF7, 0xA0, 0x0F, 0x92, 0x13, 0xF6, 0x8A, 0xF1, 0x85, 0x97, 0x3F, 0x6C,
+	0xFF, 0x00, 0xC8, 0x71, 0xFF, 0x00, 0xF1, 0xBA, 0x74, 0xDF, 0xB5, 0x3F, 0x8B, 0xA7, 0x85, 0xAD,
+	0x24, 0xBC, 0xDA, 0xAD, 0xFC, 0x5E, 0x5C, 0x67, 0x1C, 0xE7, 0xFE, 0x79, 0x57, 0xAC, 0x78, 0xAF,
+	0xFE, 0x0D, 0xF7, 0xFF, 0x00, 0x82, 0xDA, 0x78, 0x62, 0xEF, 0xC9, 0xB4, 0xFD, 0x8B, 0x7F, 0xB4,
+	0x23, 0xFF, 0x00, 0x9E, 0xDF, 0xF0, 0xB1, 0xBC, 0x37, 0x0F, 0x61, 0xD8, 0xDF, 0x9E, 0xE7, 0x1F,
+	0x85, 0x73, 0x7E, 0x22, 0xFF, 0x00, 0x82, 0x2A, 0xFF, 0x00, 0xC1, 0x64, 0x7C, 0x23, 0xA2, 0xCF,
+	0xAF, 0xF8, 0x87, 0xF6, 0x1B, 0xFB, 0x3D, 0xAD, 0xBE, 0xDF, 0x32, 0x6F, 0xF8, 0x59, 0x9E, 0x1E,
+	0x7C, 0x6E, 0x60, 0xA3, 0x85, 0xBC, 0x27, 0xA9, 0x1D, 0xA8, 0x03, 0x83, 0xFF, 0x00, 0x86, 0x8E,
+	0xF1, 0x2F, 0xFD, 0x05, 0xBF, 0xF2, 0x5D, 0x3F, 0xF8, 0xDD, 0x03, 0xF6, 0x88, 0xF1, 0x2D, 0xC1,
+	0xF2, 0x7F, 0xB4, 0xB7, 0x6E, 0xFE, 0x1F, 0x25, 0x06, 0x7F, 0xF2, 0x1D, 0x69, 0xFF, 0x00, 0xC3,
+	0xAF, 0xBF, 0xE0, 0xA9, 0x7F, 0xF4, 0x67, 0xFF, 0x00, 0xF9, 0x90, 0x34, 0x4F, 0xFE, 0x49, 0xA7,
+	0xC3, 0xFF, 0x00, 0x04, 0xB8, 0xFF, 0x00, 0x82, 0xA5, 0x5C, 0x4A, 0x21, 0x3F, 0xB1, 0xD7, 0x99,
+	0xBB, 0xF8, 0x7F, 0xE1, 0x61, 0x68, 0x83, 0x3F, 0x8F, 0xDA, 0x68, 0x03, 0x2F, 0xFE, 0x17, 0xAF,
+	0x89, 0x7F, 0xE7, 0xB7, 0xFE, 0x3A, 0x9F, 0xFC, 0x45, 0x3A, 0x1F, 0x8E, 0x5A, 0xFC, 0x92, 0x84,
+	0xB8, 0x9B, 0xE4, 0xFE, 0x2F, 0x95, 0x3F, 0xF8, 0x8A, 0xBB, 0x7D, 0xFF, 0x00, 0x04, 0xC6, 0xFF,
+	0x00, 0x82, 0x97, 0x69, 0x83, 0x3A, 0x87, 0xEC, 0x6B, 0xE5, 0x8F, 0xFB, 0x28, 0x9A, 0x33, 0x7F,
+	0x2B, 0x9F, 0x7A, 0xCA, 0x97, 0xF6, 0x08, 0xFD, 0xBF, 0x34, 0xE7, 0xDF, 0x37, 0xEC, 0xA9, 0xE5,
+	0xB2, 0xFF, 0x00, 0xD4, 0xF5, 0xA5, 0x1C, 0x7F, 0xE4, 0x7A, 0x00, 0xBC, 0xFF, 0x00, 0x1A, 0x6F,
+	0x48, 0xCF, 0x9B, 0xFF, 0x00, 0x8E, 0x8F, 0xFE, 0x22, 0xAA, 0xDD, 0x7C, 0x6B, 0xBE, 0x8E, 0x16,
+	0x2B, 0x37, 0x3F, 0xEE, 0x8F, 0xFE, 0x22, 0xA1, 0x6F, 0xD8, 0x8F, 0xF6, 0xF8, 0x3C, 0x7F, 0xC3,
+	0x2F, 0xFF, 0x00, 0xE5, 0xED, 0xA5, 0x7F, 0xF1, 0xEA, 0x60, 0xFD, 0x86, 0x7F, 0x6F, 0x89, 0x9B,
+	0x61, 0xFD, 0x98, 0xBA, 0xFF, 0x00, 0xD4, 0xE9, 0xA5, 0xFF, 0x00, 0xF1, 0xFA, 0x00, 0x4F, 0xF8,
+	0x5E, 0x5A, 0x97, 0xFC, 0xF7, 0xFF, 0x00, 0xC7, 0x57, 0xFF, 0x00, 0x88, 0xA7, 0x43, 0xF1, 0xCE,
+	0xF8, 0x4A, 0x0C, 0xD7, 0xFE, 0x52, 0xF7, 0x93, 0xCA, 0x0D, 0x8F, 0xC3, 0x65, 0x5C, 0xB1, 0xFF,
+	0x00, 0x82, 0x76, 0xFF, 0x00, 0xC1, 0x44, 0x75, 0x33, 0x8D, 0x3F, 0xF6, 0x56, 0xF3, 0x0F, 0xFD,
+	0x8F, 0x1A, 0x42, 0xFF, 0x00, 0x3B, 0x8F, 0x6A, 0xD3, 0xFF, 0x00, 0x87, 0x5A, 0x7F, 0xC1, 0x50,
+	0x26, 0x84, 0xCA, 0x9F, 0xB1, 0xC6, 0xE4, 0xFF, 0x00, 0xB2, 0x85, 0xA2, 0x8E, 0xFF, 0x00, 0xF5,
+	0xF3, 0x40, 0x18, 0xE7, 0xE3, 0xF6, 0xA5, 0x17, 0xFC, 0x7A, 0x6B, 0x9E, 0x67, 0xFD, 0xBA, 0xA8,
+	0xFE, 0x71, 0xD3, 0xEC, 0xFF, 0x00, 0x69, 0x8F, 0x1B, 0x58, 0xDD, 0x2C, 0xF0, 0x5E, 0x6D, 0xDB,
+	0xFC, 0x5E, 0x5C, 0x7C, 0x71, 0xE9, 0xE5, 0xD7, 0x49, 0xA4, 0xFF, 0x00, 0xC1, 0x1D, 0xFF, 0x00,
+	0xE0, 0xAC, 0x5E, 0x25, 0x7D, 0x9A, 0x4F, 0xEC, 0x45, 0xE6, 0x67, 0xFE, 0xAA, 0x56, 0x84, 0xBE,
+	0xBE, 0xB7, 0x63, 0xD0, 0xD7, 0x51, 0xA6, 0x7F, 0xC1, 0xBF, 0xBF, 0xF0, 0x5A, 0xAD, 0x5D, 0x94,
+	0xE9, 0xBF, 0xB0, 0x3F, 0x9A, 0xCD, 0xF7, 0x57, 0xFE, 0x16, 0x9F, 0x87, 0x17, 0x3D, 0x7D, 0x6F,
+	0xFD, 0x8D, 0x00, 0x79, 0xBD, 0xD7, 0xED, 0x53, 0xE2, 0xD9, 0x87, 0xFA, 0x5E, 0xB7, 0x8F, 0xFB,
+	0x76, 0x8F, 0xFA, 0x45, 0x59, 0xE7, 0xF6, 0x95, 0x94, 0xCC, 0x1E, 0xEB, 0x53, 0xFB, 0x42, 0xF7,
+	0x87, 0xC9, 0xDB, 0xBB, 0xF1, 0x11, 0xD7, 0xD1, 0x1E, 0x17, 0xFF, 0x00, 0x83, 0x69, 0xFF, 0x00,
+	0xE0, 0xB2, 0x1E, 0x20, 0x70, 0x3C, 0x43, 0xFB, 0x2E, 0xFF, 0x00, 0xC2, 0x3E, 0xBF, 0xDE, 0xFF,
+	0x00, 0x84, 0xDB, 0xC3, 0xD7, 0x58, 0xEB, 0xFD, 0xDD, 0x44, 0x7A, 0x0F, 0xFB, 0xEB, 0xDA, 0xBD,
+	0x13, 0x40, 0xFF, 0x00, 0x83, 0x4C, 0xFF, 0x00, 0xE0, 0xA1, 0x3E, 0x25, 0x92, 0x3B, 0x2F, 0x19,
+	0x7C, 0x40, 0xFE, 0xC1, 0xB5, 0x93, 0x3E, 0x7D, 0xC7, 0xF6, 0x4E, 0x93, 0x75, 0xE5, 0x63, 0x24,
+	0x7C, 0xA9, 0xAA, 0x02, 0x72, 0x42, 0x8E, 0x3A, 0x6E, 0xF6, 0xA0, 0x0F, 0x8D, 0x97, 0xF6, 0x9B,
+	0xB8, 0x43, 0xF2, 0x37, 0x96, 0xBF, 0x83, 0x7F, 0xED, 0x3A, 0xB0, 0xDF, 0xB5, 0x2E, 0xB9, 0x1D,
+	0xAB, 0x18, 0xB5, 0xAD, 0xF1, 0xFF, 0x00, 0x14, 0x7F, 0x67, 0x51, 0x9E, 0x7D, 0x7C, 0xAA, 0xFD,
+	0x0B, 0xF0, 0xC7, 0xFC, 0x19, 0xC1, 0xFB, 0x43, 0xEA, 0x91, 0x2C, 0x3E, 0x22, 0xFD, 0xBC, 0xBF,
+	0xB3, 0xE1, 0xFE, 0xEF, 0xFC, 0x2A, 0xEB, 0x49, 0xBD, 0x7B, 0xAE, 0xAF, 0x9E, 0xA0, 0x7E, 0x75,
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+	0x3F, 0xE1, 0x2E, 0x8F, 0xE6, 0xFB, 0x45, 0xB7, 0xFC, 0x22, 0x77, 0x96, 0x1E, 0x6F, 0xDF, 0xDB,
+	0xF3, 0x41, 0xAB, 0x1D, 0xB8, 0xCA, 0x1E, 0x3A, 0xEC, 0xF7, 0x34, 0x01, 0xF8, 0xEF, 0x79, 0xFB,
+	0x53, 0xEB, 0xCB, 0x6F, 0xE6, 0x3C, 0xD8, 0x5F, 0xEF, 0x6D, 0x5F, 0x5F, 0xFA, 0xE5, 0x5C, 0xDE,
+	0x85, 0xFB, 0x4A, 0xF8, 0xAF, 0xE2, 0x17, 0x8A, 0xE0, 0xF0, 0x77, 0xC3, 0xDB, 0xBF, 0xB6, 0x6B,
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+	0x22, 0xB1, 0xE4, 0xF6, 0xC0, 0xE7, 0x15, 0xFD, 0x1D, 0x7C, 0x1D, 0xFF, 0x00, 0x83, 0x5E, 0x7F,
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+	0x2A, 0xA8, 0x40, 0x23, 0x6E, 0x46, 0x64, 0x03, 0x91, 0x9E, 0x7D, 0x05, 0x01, 0xE7, 0x73, 0xE7,
+	0xD6, 0xF3, 0xDD, 0x79, 0x75, 0xF9, 0x94, 0x11, 0xF3, 0x76, 0x23, 0x22, 0x9B, 0xE6, 0x3C, 0x2B,
+	0xFB, 0xD6, 0x1D, 0x72, 0xCC, 0xDF, 0x74, 0x2F, 0xD7, 0xA5, 0x7E, 0xB8, 0x3F, 0xFC, 0x1A, 0x09,
+	0xFB, 0x5F, 0x46, 0xD8, 0x7F, 0xDA, 0xD7, 0xE1, 0xCB, 0x2E, 0xE0, 0xB1, 0xEE, 0xD1, 0x6F, 0xBD,
+	0x3A, 0x70, 0x7D, 0x73, 0x59, 0x7E, 0x23, 0xFF, 0x00, 0x83, 0x45, 0x7F, 0x6E, 0xAB, 0x2B, 0x46,
+	0x3E, 0x16, 0xFD, 0xA2, 0xFE, 0x15, 0x5F, 0x4A, 0xAB, 0xBA, 0x16, 0xBC, 0x5B, 0xFB, 0x50, 0x64,
+	0xCE, 0x36, 0x16, 0x10, 0xC8, 0x57, 0xA0, 0xF9, 0x86, 0x79, 0x3D, 0x38, 0xC9, 0x03, 0x9B, 0xCC,
+	0xFC, 0xA4, 0x1E, 0x66, 0x37, 0x09, 0x55, 0xB7, 0xF2, 0xAC, 0xAD, 0x90, 0x56, 0x91, 0xA2, 0x7F,
+	0x30, 0x66, 0x4F, 0x94, 0x2E, 0x36, 0xD7, 0xD1, 0xDF, 0xB6, 0xEF, 0xFC, 0x12, 0x67, 0xF6, 0xF0,
+	0xFF, 0x00, 0x82, 0x7E, 0xDB, 0xC3, 0xAF, 0xFE, 0xD2, 0x1F, 0x07, 0x16, 0xDF, 0x45, 0xB8, 0x72,
+	0x8B, 0xE2, 0x9F, 0x0F, 0xEA, 0x4B, 0xA8, 0x69, 0xAE, 0xFB, 0xB1, 0xF3, 0x4A, 0xA0, 0x3C, 0x39,
+	0xE3, 0x1E, 0x72, 0x46, 0x4E, 0x40, 0x19, 0xAF, 0x9C, 0xF2, 0xDB, 0x15, 0xDB, 0xA3, 0x2E, 0x54,
+	0xFA, 0x8A, 0x03, 0x9B, 0xCC, 0x6B, 0x06, 0x29, 0xE6, 0x49, 0x2B, 0x2E, 0xD5, 0x25, 0x95, 0x13,
+	0x20, 0x80, 0x33, 0x4E, 0x20, 0xBB, 0x2C, 0x91, 0x95, 0x58, 0xCA, 0xF1, 0xB4, 0xE7, 0x3E, 0xFF,
+	0x00, 0x5A, 0xED, 0xBF, 0x66, 0xDF, 0x81, 0xBE, 0x3D, 0xFD, 0xA7, 0x3E, 0x3F, 0x78, 0x37, 0xF6,
+	0x7D, 0xF8, 0x62, 0x17, 0xFB, 0x73, 0xC6, 0x1E, 0x22, 0xB7, 0xD2, 0xAC, 0x64, 0x99, 0x41, 0x8A,
+	0xDF, 0xCE, 0x75, 0x59, 0x2E, 0x64, 0xF5, 0x58, 0x53, 0x74, 0x84, 0x75, 0x21, 0x48, 0x00, 0x9E,
+	0x2B, 0xF4, 0xE1, 0xFF, 0x00, 0xE0, 0xD0, 0x5F, 0xDA, 0xE5, 0x36, 0xAB, 0xFE, 0xD6, 0x7F, 0x0F,
+	0x63, 0xCE, 0x15, 0x55, 0x74, 0x8B, 0xC2, 0x09, 0xC7, 0xD1, 0x7B, 0xE7, 0xB5, 0x01, 0xCD, 0xE6,
+	0x7E, 0x48, 0x24, 0x77, 0x7E, 0x60, 0x01, 0xDD, 0x94, 0xE7, 0x6E, 0xD5, 0xCF, 0xE3, 0xED, 0x46,
+	0x62, 0x32, 0x6D, 0x88, 0xFC, 0xB1, 0xFC, 0xAD, 0xEF, 0xF4, 0xF5, 0xAF, 0xB2, 0xFF, 0x00, 0xE0,
+	0xA7, 0xFF, 0x00, 0xF0, 0x45, 0x1F, 0xDA, 0x1F, 0xFE, 0x09, 0x6F, 0xE0, 0xEF, 0x0B, 0xF8, 0xF7,
+	0xE2, 0x4F, 0x8F, 0x74, 0x2F, 0x17, 0x68, 0xFE, 0x24, 0xD4, 0xA5, 0xB1, 0x4B, 0xED, 0x02, 0x09,
+	0xA1, 0xFB, 0x1D, 0xC2, 0xC7, 0xBD, 0x11, 0xC4, 0x87, 0x24, 0x30, 0x07, 0x07, 0xA7, 0x15, 0xF1,
+	0xBC, 0xCC, 0xA3, 0xE4, 0x54, 0xDA, 0xA8, 0xA0, 0x28, 0xDB, 0x8C, 0x71, 0x93, 0xFA, 0x93, 0x40,
+	0x73, 0x79, 0x91, 0x9D, 0x8A, 0xDD, 0x36, 0xFA, 0x7B, 0xD3, 0x94, 0x31, 0xB7, 0x28, 0x02, 0xB3,
+	0x6E, 0xCE, 0xE6, 0x34, 0x43, 0x04, 0xD7, 0xB7, 0x50, 0xD9, 0xD9, 0xC4, 0xD2, 0xCD, 0x71, 0x28,
+	0x8A, 0xDE, 0x18, 0xC6, 0xE7, 0x96, 0x42, 0x40, 0x54, 0x55, 0x1C, 0x96, 0x24, 0x80, 0x14, 0x72,
+	0x4F, 0x4C, 0xE0, 0xD7, 0xE8, 0xA7, 0xEC, 0x4B, 0xFF, 0x00, 0x06, 0xCC, 0x7E, 0xDF, 0x1F, 0xB5,
+	0x4E, 0x89, 0x6F, 0xE3, 0xCF, 0x8A, 0x4D, 0xA4, 0xFC, 0x29, 0xF0, 0xCD, 0xDA, 0xEE, 0xB4, 0x9B,
+	0xC4, 0x4A, 0xF7, 0x1A, 0xA5, 0xD2, 0xE0, 0x1D, 0xC2, 0xD2, 0x26, 0x1E, 0x5A, 0x1C, 0xE0, 0x79,
+	0xAE, 0x8D, 0x95, 0x6C, 0xA0, 0x1B, 0x4B, 0x04, 0xC9, 0xF9, 0x9F, 0x9D, 0x46, 0x17, 0x52, 0xA8,
+	0x61, 0x91, 0x99, 0x86, 0x76, 0xED, 0x3F, 0x30, 0xF5, 0x1C, 0x52, 0x31, 0x28, 0x58, 0x83, 0x1F,
+	0xCA, 0xC0, 0x61, 0x98, 0x7C, 0xA4, 0xE7, 0x19, 0xF4, 0xE8, 0x6B, 0xF6, 0xE6, 0xFB, 0xFE, 0x0C,
+	0xF3, 0x85, 0xF4, 0x7C, 0xE9, 0xDF, 0xB6, 0xF5, 0xEA, 0xDF, 0x79, 0x78, 0xDB, 0x37, 0x84, 0x62,
+	0x10, 0x06, 0xF7, 0x08, 0xD9, 0x65, 0xFA, 0x93, 0xF5, 0x3D, 0xBE, 0x06, 0xFF, 0x00, 0x82, 0x93,
+	0xFF, 0x00, 0xC1, 0x15, 0xFF, 0x00, 0x6B, 0x3F, 0xF8, 0x26, 0x0E, 0x97, 0xA7, 0xF8, 0xDF, 0xE2,
+	0xCF, 0x89, 0xBC, 0x37, 0xAF, 0xF8, 0x37, 0x58, 0xD4, 0x52, 0xC7, 0x4D, 0xF1, 0x17, 0x87, 0x6F,
+	0x9A, 0x36, 0x5B, 0x83, 0xBD, 0xBC, 0xA9, 0x6D, 0x64, 0x1B, 0x94, 0xEC, 0x42, 0xDF, 0x20, 0x64,
+	0x1B, 0xBE, 0xF6, 0x72, 0x00, 0x4C, 0x65, 0x76, 0x7C, 0x7E, 0xA6, 0x47, 0x4D, 0xF1, 0xCA, 0x3E,
+	0x61, 0x9F, 0xF3, 0xE9, 0x44, 0xC2, 0x60, 0x71, 0x0C, 0xDC, 0xE0, 0x95, 0x07, 0xAE, 0x47, 0x7A,
+	0xFD, 0x0A, 0xFD, 0x80, 0xFF, 0x00, 0xE0, 0xDD, 0x8F, 0xDA, 0x2B, 0xFE, 0x0A, 0x11, 0xFB, 0x33,
+	0x68, 0xFF, 0x00, 0xB5, 0x27, 0x80, 0xFE, 0x3F, 0x78, 0x43, 0xC3, 0xFA, 0x6E, 0xB9, 0x75, 0x75,
+	0x14, 0x5A, 0x6E, 0xA9, 0xA6, 0xDC, 0x49, 0x3A, 0x18, 0x25, 0x31, 0x12, 0xC6, 0x33, 0xB7, 0x9D,
+	0xBF, 0xA5, 0x79, 0xBF, 0xFC, 0x15, 0x1B, 0xFE, 0x08, 0xE3, 0xF1, 0x8B, 0xFE, 0x09, 0x53, 0xA4,
+	0xF8, 0x3F, 0x5B, 0xF8, 0xAF, 0xF1, 0x6B, 0x41, 0xF1, 0x54, 0x7E, 0x30, 0xBA, 0xBC, 0x83, 0x4D,
+	0x5D, 0x0A, 0xD2, 0x58, 0x7E, 0xCF, 0x2C, 0x08, 0x8C, 0x4B, 0x79, 0xBF, 0x7B, 0x3B, 0xC7, 0xCA,
+	0x0E, 0x4E, 0x38, 0x1C, 0x1A, 0x0D, 0x39, 0xBC, 0xCF, 0x90, 0x22, 0x59, 0x58, 0x2A, 0xB1, 0xDC,
+	0xC4, 0x80, 0xD8, 0x3C, 0x12, 0x69, 0x24, 0x47, 0x6D, 0xBE, 0x4B, 0xE3, 0x73, 0x6D, 0x38, 0x39,
+	0xC7, 0xF8, 0x7E, 0x35, 0xEA, 0x1F, 0xB1, 0x97, 0xEC, 0x6F, 0xF1, 0x97, 0xF6, 0xE7, 0xFD, 0xA0,
+	0xB4, 0x5F, 0xD9, 0xC3, 0xE0, 0x9E, 0x86, 0xB7, 0xDA, 0x96, 0xAD, 0x30, 0x7B, 0x8B, 0xBB, 0xA5,
+	0x2B, 0x69, 0xA6, 0x5B, 0x02, 0xA2, 0x7B, 0xA9, 0x8F, 0x04, 0x2A, 0x0D, 0xD8, 0x5E, 0xAC, 0x53,
+	0x0A, 0x18, 0xF1, 0x5F, 0xA3, 0x52, 0x7F, 0xC1, 0xA0, 0xDF, 0xB5, 0xC7, 0x9B, 0x19, 0x6F, 0xDA,
+	0xC3, 0xE1, 0xBB, 0x48, 0xA7, 0x7B, 0x47, 0xFD, 0x93, 0x7D, 0xB1, 0x9C, 0x74, 0xC1, 0x01, 0x7E,
+	0x5E, 0x7A, 0x11, 0xD7, 0xEA, 0x28, 0x0E, 0x6F, 0x33, 0xF2, 0x57, 0x7B, 0x48, 0x63, 0x75, 0x65,
+	0xC2, 0xFF, 0x00, 0x0A, 0xB6, 0x43, 0xFD, 0x7D, 0x28, 0xF9, 0xD5, 0xF3, 0x9A, 0xF4, 0xEF, 0xDB,
+	0x2F, 0xF6, 0x69, 0xB5, 0xFD, 0x90, 0xBE, 0x3F, 0xEB, 0x1F, 0xB3, 0xDD, 0xB7, 0xC6, 0x9D, 0x17,
+	0xC7, 0xD7, 0x5E, 0x1D, 0x6F, 0x23, 0x56, 0xD7, 0x3C, 0x3F, 0x6B, 0x24, 0x56, 0x91, 0xDD, 0xEE,
+	0x63, 0x25, 0xBA, 0x79, 0x9F, 0x7F, 0x67, 0x19, 0x60, 0x48, 0xC9, 0x23, 0xAA, 0x90, 0x3C, 0xC5,
+	0x4B, 0x1F, 0xBD, 0x8F, 0xC6, 0x82, 0xA3, 0x2D, 0x77, 0x1A, 0xCB, 0xF3, 0x79, 0x89, 0xF7, 0x9A,
+	0xBA, 0x3F, 0x82, 0x77, 0x92, 0x69, 0xBF, 0x1A, 0x3C, 0x23, 0x73, 0x0B, 0xED, 0x65, 0xF1, 0x1D,
+	0x9A, 0xFF, 0x00, 0xE4, 0x65, 0xAE, 0x7A, 0xB5, 0x7E, 0x18, 0xDC, 0x25, 0x8F, 0xC5, 0xAF, 0x09,
+	0x5C, 0xCB, 0xF7, 0x7F, 0xE1, 0x28, 0xB1, 0x5F, 0xFC, 0x8C, 0xB4, 0x19, 0xD4, 0x3F, 0xB5, 0x1F,
+	0x03, 0xC9, 0xFF, 0x00, 0x14, 0x56, 0x8F, 0xC7, 0xFC, 0xC2, 0xED, 0xFF, 0x00, 0xF4, 0x5A, 0xD1,
+	0x4D, 0xF0, 0x3B, 0xC5, 0xFF, 0x00, 0x08, 0x5E, 0x8F, 0xFF, 0x00, 0x60, 0xBB, 0x7F, 0xFD, 0x16,
+	0xB4, 0x50, 0x73, 0x9F, 0xC9, 0x1F, 0xFC, 0x16, 0x40, 0xED, 0xFF, 0x00, 0x82, 0xB0, 0x7C, 0x4A,
+	0x71, 0xFC, 0x3A, 0x6D, 0x9F, 0xFE, 0x8B, 0x5A, 0xF9, 0xD4, 0x31, 0x3C, 0x1F, 0xAD, 0x7D, 0x0F,
+	0xFF, 0x00, 0x05, 0x92, 0xDE, 0x7F, 0xE0, 0xAB, 0x7F, 0x12, 0x95, 0xBB, 0xE9, 0xF6, 0x63, 0xFF,
+	0x00, 0x21, 0xAD, 0x7C, 0xF1, 0xB3, 0x60, 0x2C, 0x4F, 0xF0, 0xD0, 0x6D, 0x4C, 0x25, 0xFD, 0xDC,
+	0x7E, 0x7B, 0x1F, 0x97, 0x38, 0xFA, 0x9F, 0xA5, 0x1E, 0x5B, 0xE3, 0x2A, 0x38, 0x19, 0x39, 0xFA,
+	0x0C, 0x9A, 0xD4, 0xF8, 0x79, 0xE1, 0x4B, 0x8F, 0x88, 0x3E, 0x3C, 0xD1, 0x7C, 0x0B, 0xA6, 0xEB,
+	0xDA, 0x76, 0x97, 0x71, 0xAD, 0x6A, 0xF6, 0xF6, 0x51, 0xEA, 0x5A, 0xE5, 0xE2, 0x5A, 0x58, 0xDB,
+	0xEF, 0x62, 0x37, 0xCD, 0x3B, 0x1F, 0x91, 0x47, 0x53, 0x9C, 0x02, 0x3A, 0x1A, 0xFE, 0x85, 0xFF,
+	0x00, 0xE0, 0x98, 0x3F, 0xF0, 0x6D, 0xA7, 0xEC, 0x75, 0xF0, 0x33, 0x48, 0xD1, 0x7E, 0x3A, 0xFE,
+	0xD1, 0x7A, 0xFE, 0x97, 0xF1, 0x9B, 0xC5, 0x0A, 0x05, 0xE5, 0x8B, 0xC3, 0x28, 0x9B, 0xC3, 0x70,
+	0x36, 0x72, 0xAD, 0x0C, 0x1F, 0x76, 0xE8, 0xA9, 0x1C, 0x49, 0x26, 0xE1, 0x93, 0xC2, 0x8C, 0x64,
+	0x85, 0x4A, 0x5C, 0xAB, 0x73, 0xF2, 0x5B, 0xFE, 0x09, 0xD7, 0xFF, 0x00, 0x04, 0x4B, 0xFD, 0xB6,
+	0xBF, 0xE0, 0xA0, 0xF7, 0x76, 0xBE, 0x2A, 0xF0, 0x6F, 0x84, 0x7F, 0xE1, 0x13, 0xF0, 0x0C, 0xCC,
+	0xBF, 0x6C, 0xF1, 0xEF, 0x88, 0x58, 0xC3, 0x04, 0x91, 0xF5, 0x22, 0xD6, 0x2F, 0xBF, 0x72, 0x70,
+	0x7A, 0x85, 0xF2, 0xF9, 0xC6, 0xEC, 0x82, 0x07, 0xEF, 0x87, 0xFC, 0x13, 0xAB, 0xFE, 0x08, 0x79,
+	0xFB, 0x11, 0xFF, 0x00, 0xC1, 0x3B, 0x12, 0x1F, 0x15, 0xF8, 0x17, 0xC0, 0xAB, 0xE2, 0x4F, 0x1E,
+	0x6D, 0x06, 0xE3, 0xC7, 0x5E, 0x24, 0x51, 0x35, 0xD2, 0x3E, 0xD5, 0x0C, 0x2D, 0x54, 0xE5, 0x6D,
+	0x17, 0x23, 0x3F, 0x27, 0xCC, 0x4B, 0x36, 0x49, 0x18, 0x03, 0xEB, 0xEB, 0x1B, 0x1B, 0x2B, 0x08,
+	0xA3, 0xB3, 0xD3, 0xAD, 0x63, 0x86, 0x38, 0x40, 0x48, 0x62, 0x89, 0xB0, 0x15, 0x42, 0x80, 0x06,
+	0xD1, 0xC0, 0xC0, 0xE0, 0x0E, 0xC0, 0x0F, 0xA5, 0x5A, 0xB7, 0x1B, 0x61, 0x51, 0xF3, 0x7F, 0xC0,
+	0xBA, 0xD0, 0x63, 0x29, 0x39, 0x1F, 0x93, 0x5F, 0xF0, 0x77, 0x2C, 0x6C, 0x9F, 0xB0, 0x9F, 0x81,
+	0xCB, 0x2F, 0xDE, 0xF8, 0x91, 0x19, 0xDB, 0xE9, 0xFE, 0x87, 0x37, 0xBE, 0x3F, 0x2C, 0x57, 0xC6,
+	0x1F, 0xF0, 0x69, 0xB9, 0x1F, 0xF0, 0xF1, 0xAF, 0x14, 0x01, 0xFF, 0x00, 0x44, 0xDE, 0xEB, 0xFF,
+	0x00, 0x4B, 0x2D, 0xAB, 0xED, 0x3F, 0xF8, 0x3B, 0xC4, 0x84, 0xFD, 0x85, 0x3C, 0x0A, 0x58, 0xFF,
+	0x00, 0xCD, 0x46, 0x4F, 0xFD, 0x24, 0x9A, 0xBE, 0x29, 0xFF, 0x00, 0x83, 0x4D, 0x25, 0x49, 0x7F,
+	0xE0, 0xA3, 0xDE, 0x28, 0x54, 0x6D, 0xC4, 0x7C, 0x35, 0xBA, 0x3F, 0xF9, 0x39, 0x6D, 0x41, 0x5C,
+	0xDF, 0xBB, 0xB1, 0xFB, 0xA1, 0xFF, 0x00, 0x05, 0x06, 0xFD, 0xA9, 0x75, 0x0F, 0xD8, 0xAB, 0xF6,
+	0x3E, 0xF1, 0xD7, 0xED, 0x43, 0xA5, 0xF8, 0x5A, 0x1D, 0x6A, 0xE3, 0xC1, 0xFA, 0x39, 0xBD, 0x8F,
+	0x4D, 0xB8, 0xB8, 0xF2, 0x92, 0x62, 0x64, 0x54, 0xC1, 0x6E, 0xDD, 0x7B, 0x57, 0xC1, 0x1F, 0xF0,
+	0x4D, 0xCF, 0xF8, 0x39, 0xA7, 0xC3, 0xDF, 0xB6, 0xA7, 0xED, 0x3F, 0xE1, 0xBF, 0xD9, 0x7B, 0xE2,
+	0x8F, 0xEC, 0xE1, 0x3F, 0x84, 0xF5, 0x1F, 0x17, 0xDE, 0x49, 0x67, 0xA0, 0xEA, 0xDA, 0x6E, 0xA9,
+	0xF6, 0xAB, 0x7F, 0xB5, 0x2C, 0x2D, 0x3A, 0xC5, 0x22, 0xB8, 0x0C, 0x37, 0x2A, 0x9E, 0x54, 0x10,
+	0xB9, 0x19, 0x23, 0x20, 0x57, 0xE9, 0x17, 0xED, 0x2F, 0xFB, 0x3A, 0xFC, 0x32, 0xFD, 0xAC, 0xFE,
+	0x09, 0x78, 0x8B, 0xF6, 0x76, 0xF8, 0xCB, 0xA7, 0xDD, 0x5D, 0x78, 0x67, 0xC5, 0x5A, 0x7F, 0xD9,
+	0x35, 0x7B, 0x7B, 0x3B, 0xE9, 0x2D, 0xA4, 0x78, 0xF7, 0x06, 0xF9, 0x64, 0x8C, 0x86, 0x53, 0x90,
+	0x3B, 0xFA, 0x57, 0xCF, 0x7F, 0xB2, 0x1F, 0xFC, 0x10, 0xDB, 0xFE, 0x09, 0xC3, 0xFB, 0x0E, 0x7C,
+	0x4C, 0xB7, 0xF8, 0xCD, 0xF0, 0x27, 0xE0, 0xEE, 0xA0, 0xBE, 0x2A, 0xB1, 0x89, 0xD2, 0xC3, 0x5C,
+	0xF1, 0x07, 0x8A, 0x2F, 0xF5, 0x29, 0x6D, 0x0B, 0x29, 0x42, 0xD1, 0x2C, 0xF2, 0xB2, 0x2B, 0x10,
+	0x4A, 0xF0, 0xBD, 0x0F, 0x14, 0x10, 0xB7, 0x3D, 0xC3, 0xF6, 0xC0, 0xF8, 0x4B, 0xF0, 0xFF, 0x00,
+	0xE3, 0x77, 0xEC, 0xB7, 0xE3, 0xEF, 0x84, 0x1F, 0x13, 0xF4, 0xCF, 0xB5, 0xF8, 0x7F, 0x5A, 0xF0,
+	0x8D, 0xFD, 0xA6, 0xA1, 0x1C, 0xD8, 0x6C, 0x29, 0x81, 0xB6, 0xBA, 0xEE, 0xE9, 0x22, 0x36, 0xD7,
+	0x46, 0xEC, 0xC8, 0x3A, 0x71, 0x5F, 0xC6, 0xBD, 0xCC, 0x6E, 0x97, 0x2D, 0x18, 0x95, 0x64, 0x53,
+	0x27, 0x97, 0x0B, 0x47, 0xDF, 0x68, 0x00, 0xF1, 0xDB, 0x9C, 0x9F, 0xC6, 0xBF, 0xA7, 0x4F, 0xF8,
+	0x2F, 0xAE, 0xBF, 0xFF, 0x00, 0x05, 0x36, 0xFF, 0x00, 0x86, 0x46, 0xF1, 0x5F, 0x84, 0xFF, 0x00,
+	0x62, 0xCF, 0x85, 0x3A, 0x3E, 0xA5, 0xE1, 0x1D, 0x4B, 0x41, 0x9A, 0x1F, 0x1E, 0xEA, 0xF6, 0x3A,
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+	0x38, 0x6C, 0x30, 0x69, 0x08, 0x3D, 0xB8, 0xF7, 0xAE, 0x59, 0x7F, 0x6F, 0x8F, 0xF8, 0x26, 0xDF,
+	0x80, 0xED, 0x5B, 0x52, 0x3F, 0xB5, 0xD7, 0xC1, 0x8D, 0x1E, 0x15, 0x91, 0x97, 0xED, 0x03, 0xC6,
+	0xDA, 0x54, 0x3E, 0x57, 0x7C, 0x1C, 0x48, 0xB8, 0x5C, 0x1C, 0xE4, 0x9E, 0xA4, 0xD0, 0x07, 0xB8,
+	0xC2, 0xEF, 0x36, 0x9E, 0xB6, 0x9A, 0xAD, 0xAC, 0x7B, 0xA4, 0x87, 0x6D, 0xCC, 0x6C, 0xD9, 0x46,
+	0xCA, 0xFC, 0xF8, 0xF5, 0x50, 0x49, 0x07, 0x81, 0xC7, 0xB5, 0x7F, 0x2E, 0x7E, 0x22, 0xFD, 0x88,
+	0xB4, 0x3F, 0xDA, 0x13, 0xFE, 0x0E, 0x23, 0xF1, 0x17, 0xEC, 0x61, 0xF0, 0xCE, 0xC1, 0x53, 0xC2,
+	0xAB, 0xF1, 0xB9, 0xE6, 0xD6, 0x23, 0xB3, 0x20, 0xAD, 0xAE, 0x8D, 0x13, 0xC5, 0x7F, 0x7C, 0x83,
+	0x91, 0xC1, 0xCC, 0xB1, 0x7A, 0x86, 0x95, 0x78, 0xC0, 0x35, 0xFA, 0xC9, 0xFB, 0x7F, 0xFF, 0x00,
+	0xC1, 0xCF, 0xDF, 0xF0, 0x4F, 0x2F, 0xD9, 0xC3, 0xE1, 0xD6, 0xB5, 0xA6, 0x7E, 0xCD, 0x1F, 0x13,
+	0xAC, 0xBE, 0x2B, 0xF8, 0xF7, 0xEC, 0x33, 0x26, 0x87, 0x63, 0xE1, 0x74, 0x69, 0x74, 0xC8, 0x2E,
+	0x4A, 0x91, 0x1B, 0xDC, 0x5E, 0xED, 0x10, 0xBC, 0x62, 0x40, 0x19, 0x96, 0x27, 0x76, 0x2A, 0x3A,
+	0x72, 0x33, 0xF1, 0xFF, 0x00, 0xFC, 0x1A, 0xCD, 0xAA, 0x7C, 0x31, 0xD7, 0xFE, 0x34, 0xFC, 0x68,
+	0xFF, 0x00, 0x82, 0x85, 0xFE, 0xD4, 0xFF, 0x00, 0x1C, 0x3C, 0x2F, 0x63, 0xE2, 0xDD, 0x7F, 0x56,
+	0x97, 0x48, 0xD2, 0xA4, 0xD7, 0xBC, 0x45, 0x6D, 0x6F, 0x71, 0x2C, 0xB3, 0xB2, 0xDE, 0xDF, 0xDC,
+	0x2A, 0xCA, 0xEA, 0xEA, 0x8C, 0x66, 0x82, 0x35, 0x62, 0x00, 0xC2, 0x10, 0x09, 0x21, 0x80, 0x00,
+	0xFD, 0xE9, 0xB0, 0xB0, 0xD3, 0x34, 0xEB, 0x7B, 0x7D, 0x37, 0x4D, 0xB0, 0x8E, 0xDE, 0x18, 0x60,
+	0xFB, 0x3C, 0x11, 0x42, 0xA1, 0x7C, 0xA4, 0x41, 0xB5, 0x54, 0x60, 0xE4, 0x00, 0xBD, 0x00, 0xE8,
+	0x3D, 0x2B, 0xE2, 0xEF, 0x8D, 0x9F, 0xF0, 0x6F, 0x7F, 0xFC, 0x13, 0x07, 0xF6, 0x87, 0xF8, 0xB1,
+	0xE2, 0x2F, 0x8E, 0xFF, 0x00, 0x14, 0xBE, 0x12, 0xF8, 0x83, 0x52, 0xF1, 0x47, 0x8A, 0x35, 0x06,
+	0xBE, 0xD5, 0x75, 0x06, 0xF1, 0xE6, 0xA9, 0x10, 0x9A, 0x63, 0x90, 0x3E, 0x55, 0x9B, 0x08, 0x00,
+	0xC2, 0xF0, 0x3A, 0x0A, 0xE0, 0xBF, 0xE0, 0xBD, 0xFF, 0x00, 0xF0, 0x54, 0xAF, 0x86, 0xBF, 0xB3,
+	0xE7, 0xFC, 0x13, 0x9B, 0xC5, 0xD7, 0x9F, 0xB3, 0x57, 0xED, 0x1F, 0xA1, 0xC9, 0xE3, 0xAF, 0x12,
+	0xCD, 0x06, 0x89, 0xA0, 0xCD, 0xE1, 0x1F, 0x12, 0xC3, 0x2D, 0xED, 0x9B, 0x4D, 0x20, 0x12, 0x5C,
+	0x2F, 0x92, 0xE7, 0x69, 0x54, 0xCF, 0xCC, 0x71, 0xD7, 0x00, 0xE7, 0x8A, 0xFE, 0x7B, 0x87, 0xFC,
+	0x15, 0xB7, 0xFE, 0x0A, 0x72, 0x53, 0x7A, 0xFE, 0xDF, 0x9F, 0x15, 0x95, 0x5B, 0x25, 0x54, 0x78,
+	0xBA, 0x74, 0x23, 0x93, 0x90, 0x40, 0x20, 0x67, 0x76, 0x79, 0xF4, 0xC5, 0x00, 0x7F, 0x5C, 0xDF,
+	0xB2, 0xF7, 0xEC, 0xCB, 0xF0, 0x87, 0xF6, 0x3B, 0xF8, 0x29, 0xA1, 0xFE, 0xCF, 0x3F, 0x02, 0x74,
+	0x7D, 0x43, 0x4F, 0xF0, 0xAE, 0x82, 0x66, 0xFE, 0xC9, 0xB1, 0xD4, 0x35, 0x69, 0xEF, 0x9E, 0xD9,
+	0x5D, 0xDA, 0x43, 0x18, 0x92, 0x67, 0x77, 0xDB, 0x97, 0x6C, 0x0C, 0xE0, 0x7D, 0x4F, 0x3F, 0x92,
+	0x3F, 0xF0, 0x77, 0xC7, 0xEC, 0x7D, 0xFD, 0xA5, 0xE0, 0xFF, 0x00, 0x87, 0xDF, 0xB7, 0x97, 0x85,
+	0x74, 0x38, 0xC5, 0xE6, 0x82, 0xCF, 0xE1, 0x2F, 0x15, 0x5C, 0x2F, 0x25, 0xAC, 0x67, 0x2D, 0x2D,
+	0xA9, 0x70, 0x3A, 0xEC, 0x98, 0xCC, 0xB9, 0xE4, 0xE2, 0xE0, 0x8A, 0xF9, 0xCB, 0xFE, 0x0D, 0xE6,
+	0xFF, 0x00, 0x82, 0xC7, 0xFE, 0xD0, 0xFF, 0x00, 0xF0, 0xDF, 0xD6, 0xBF, 0x0B, 0xBF, 0x6D, 0x3F,
+	0xDA, 0xD7, 0xC4, 0x3A, 0xF7, 0x83, 0x7C, 0x61, 0xE1, 0xFB, 0xBB, 0x4B, 0x5B, 0x8F, 0x1C, 0xF8,
+	0x91, 0xA5, 0xB5, 0xB2, 0xD4, 0x22, 0x43, 0x71, 0x11, 0xDF, 0x37, 0xCB, 0x1E, 0xF4, 0x8E, 0x45,
+	0xDC, 0xCE, 0xAB, 0x90, 0x07, 0x56, 0x50, 0xDF, 0xB0, 0x5F, 0xF0, 0x52, 0x6F, 0x12, 0xFE, 0xC6,
+	0xBF, 0xB6, 0xB7, 0xEC, 0x2F, 0xF1, 0x3B, 0xF6, 0x67, 0xB8, 0xFD, 0xA8, 0x3E, 0x1D, 0xB5, 0xD7,
+	0x89, 0x3C, 0x27, 0x75, 0x1E, 0x8D, 0x70, 0xDE, 0x31, 0xB2, 0x63, 0x6B, 0xA8, 0x46, 0x86, 0x5B,
+	0x49, 0xB1, 0xE6, 0x83, 0xB9, 0x67, 0x58, 0xF8, 0x1C, 0xE2, 0x80, 0x3C, 0xF3, 0xFE, 0x0D, 0xAC,
+	0xFD, 0xAE, 0xFC, 0x33, 0xFB, 0x4C, 0xFF, 0x00, 0xC1, 0x2D, 0xFC, 0x1B, 0xE0, 0xD8, 0xF5, 0x6F,
+	0x33, 0x5F, 0xF8, 0x57, 0x9F, 0x09, 0x6B, 0xB6, 0xB2, 0x73, 0x32, 0x24, 0x00, 0x35, 0xA4, 0x84,
+	0x0E, 0x08, 0x7B, 0x67, 0x88, 0x6E, 0x19, 0x05, 0x91, 0x87, 0x50, 0x40, 0xE3, 0xBF, 0xE0, 0xE3,
+	0x4F, 0xF8, 0x24, 0x7F, 0x8F, 0xBF, 0xE0, 0xA1, 0x9F, 0x08, 0xB4, 0x1F, 0x8D, 0xFF, 0x00, 0xB3,
+	0x7E, 0x84, 0x9A, 0x9F, 0xC4, 0x8F, 0x87, 0xF6, 0xB7, 0x50, 0x47, 0xA2, 0xFD, 0xA1, 0x23, 0x6D,
+	0x73, 0x4D, 0x97, 0xE6, 0x92, 0xD1, 0x1A, 0x46, 0x55, 0x59, 0x96, 0x41, 0xBD, 0x0B, 0x11, 0x82,
+	0x58, 0x75, 0x35, 0xF8, 0x35, 0xFF, 0x00, 0x04, 0xC7, 0xFF, 0x00, 0x82, 0x9E, 0x7C, 0x7F, 0xFF,
+	0x00, 0x82, 0x59, 0x7E, 0xD1, 0xB1, 0xFC, 0x50, 0xF0, 0x05, 0xB4, 0x77, 0x5A, 0x36, 0xA1, 0x30,
+	0xB3, 0xF8, 0x81, 0xE1, 0x19, 0x26, 0xC5, 0xBE, 0xB5, 0x69, 0x1C, 0xBB, 0x4F, 0x96, 0xC0, 0xE1,
+	0x67, 0x8F, 0x32, 0x98, 0xE4, 0x07, 0x69, 0xEE, 0x71, 0x8C, 0xFF, 0x00, 0x4C, 0x9F, 0xB0, 0xDF,
+	0xFC, 0x16, 0x6B, 0xFE, 0x09, 0xF5, 0xFB, 0x7D, 0xF8, 0x76, 0x0D, 0x43, 0xE1, 0x47, 0xC7, 0x6D,
+	0x27, 0x4D, 0xF1, 0x11, 0x8C, 0x0D, 0x43, 0xC1, 0x7E, 0x28, 0xBC, 0x4B, 0x1D, 0x52, 0xCD, 0xB6,
+	0xA9, 0xC2, 0xAC, 0xA5, 0x44, 0xC8, 0x37, 0x7F, 0xAC, 0x88, 0xBA, 0x92, 0x18, 0x06, 0xCA, 0xB0,
+	0x01, 0x4A, 0xE7, 0xF2, 0xD7, 0xAD, 0x7E, 0xC8, 0x7F, 0xB5, 0xEF, 0x87, 0xBC, 0x60, 0x9F, 0x0F,
+	0x35, 0xDF, 0xD9, 0x5B, 0xC7, 0xB1, 0x6B, 0x69, 0x33, 0x5B, 0x35, 0x8A, 0xF8, 0x4E, 0xF1, 0x9B,
+	0xCC, 0x63, 0x83, 0x80, 0x23, 0x21, 0xCF, 0x4E, 0x46, 0x57, 0x39, 0x39, 0xC7, 0x35, 0xEC, 0x7F,
+	0xB4, 0xB7, 0xFC, 0x12, 0x37, 0xF6, 0xA4, 0xFD, 0x8D, 0xFF, 0x00, 0x61, 0x8D, 0x1F, 0xF6, 0xB8,
+	0xFD, 0xAA, 0xB4, 0x68, 0x7C, 0x17, 0xA8, 0x78, 0x9B, 0xC6, 0x50, 0x69, 0x1A, 0x0F, 0x82, 0xA6,
+	0x90, 0x4B, 0x7C, 0xB6, 0xEF, 0x6F, 0x2C, 0x86, 0xEA, 0xE8, 0xC6, 0xCC, 0xA8, 0x4F, 0x96, 0x80,
+	0x47, 0x90, 0xC3, 0xA9, 0x03, 0x26, 0xBF, 0xAC, 0x29, 0x3C, 0x67, 0xF0, 0xE6, 0x08, 0xBF, 0xB5,
+	0x6E, 0xFC, 0x5F, 0xA3, 0xFF, 0x00, 0xAB, 0xFF, 0x00, 0x8F, 0x99, 0x2F, 0xA1, 0x5E, 0x31, 0xD7,
+	0x76, 0x72, 0x38, 0xF7, 0xCD, 0x7E, 0x2E, 0x7F, 0xC1, 0xD8, 0xFF, 0x00, 0xB6, 0xF7, 0xEC, 0x8F,
+	0xF1, 0x5F, 0xF6, 0x62, 0xF0, 0x6F, 0xEC, 0xF5, 0xF0, 0xA7, 0xF6, 0x85, 0xF0, 0xBF, 0x89, 0xBC,
+	0x65, 0xA7, 0xF8, 0xFA, 0x1D, 0x4B, 0x50, 0xD0, 0xFC, 0x3F, 0xA9, 0x0B, 0xD9, 0x2D, 0x2D, 0xD6,
+	0x19, 0xA2, 0x2D, 0x34, 0x91, 0xEE, 0x48, 0xDC, 0x39, 0x03, 0x63, 0xB0, 0x7C, 0x10, 0x76, 0xE3,
+	0x9A, 0x02, 0x47, 0xD9, 0x3F, 0xF0, 0x6C, 0x74, 0xFF, 0x00, 0x6A, 0xFF, 0x00, 0x82, 0x40, 0x78,
+	0x06, 0x71, 0x19, 0x50, 0xDA, 0xC6, 0xB1, 0xF2, 0xB7, 0x51, 0xFE, 0x9B, 0x26, 0x47, 0xE7, 0x9A,
+	0xE5, 0x7F, 0xE0, 0xBD, 0xBF, 0xF0, 0x52, 0x1F, 0x89, 0xFF, 0x00, 0xF0, 0x4C, 0x3F, 0x8C, 0x7F,
+	0xB3, 0x9F, 0xC7, 0xAF, 0x06, 0xBC, 0xD7, 0xBE, 0x1E, 0xBA, 0xF1, 0x16, 0xA9, 0x61, 0xE3, 0xCF,
+	0x0E, 0xAB, 0x6D, 0x1A, 0xAE, 0x92, 0xD1, 0x40, 0xD2, 0xAA, 0xE7, 0x8F, 0x3A, 0x3C, 0x79, 0xB1,
+	0x9E, 0xA1, 0xE3, 0x55, 0xFB, 0xAE, 0xF5, 0x95, 0xFF, 0x00, 0x06, 0xD7, 0xFE, 0xD3, 0x3F, 0xB3,
+	0xBF, 0xC3, 0xFF, 0x00, 0xF8, 0x24, 0xA7, 0x81, 0x7C, 0x2D, 0xF1, 0x03, 0xE3, 0xBF, 0x83, 0xF4,
+	0x3D, 0x52, 0x1D, 0x63, 0x58, 0x69, 0xB4, 0xDD, 0x63, 0xC4, 0x96, 0xD6, 0xD7, 0x11, 0xAB, 0x5E,
+	0xC8, 0x54, 0xB4, 0x72, 0x38, 0x61, 0x90, 0x73, 0xC8, 0xAF, 0x95, 0x3F, 0xE0, 0xF0, 0x6F, 0x8D,
+	0xFF, 0x00, 0x07, 0x3E, 0x2A, 0x78, 0x27, 0xE0, 0x41, 0xF8, 0x5B, 0xF1, 0x47, 0xC3, 0xDE, 0x26,
+	0x6D, 0x3F, 0xC4, 0x3A, 0xC3, 0x6A, 0x09, 0xA0, 0xEB, 0x90, 0x5D, 0xF9, 0x08, 0xD6, 0xF0, 0x85,
+	0x67, 0x11, 0x33, 0x6D, 0x20, 0x8C, 0xA9, 0x3C, 0x64, 0x1C, 0xF6, 0xA0, 0x93, 0xF6, 0xB7, 0xE0,
+	0x77, 0xC6, 0xEF, 0x84, 0xFF, 0x00, 0xB4, 0xD7, 0xC1, 0xDF, 0x0F, 0x7C, 0x6A, 0xF8, 0x45, 0xE2,
+	0x9B, 0x7D, 0x73, 0xC2, 0x7E, 0x2A, 0xD2, 0xFE, 0xDD, 0xA6, 0xDE, 0x46, 0x49, 0x8E, 0x78, 0x9F,
+	0x1B, 0x83, 0x86, 0xC3, 0x0D, 0xA4, 0xB2, 0xB2, 0xB0, 0xC0, 0x39, 0x53, 0x8C, 0x0A, 0xFE, 0x7E,
+	0xFF, 0x00, 0xE0, 0xE2, 0xDF, 0xF8, 0x22, 0xF1, 0xFD, 0x90, 0xFE, 0x20, 0xDE, 0x7E, 0xDA, 0x5F,
+	0xB3, 0x77, 0x83, 0x9E, 0x3F, 0x85, 0xBE, 0x24, 0xB8, 0xF3, 0x7C, 0x51, 0xA5, 0xD8, 0xA8, 0x58,
+	0xFC, 0x31, 0xA9, 0xC9, 0x23, 0x1F, 0x3B, 0x19, 0xDC, 0x2D, 0x66, 0x66, 0x8C, 0x67, 0x18, 0x49,
+	0x18, 0xA9, 0xDB, 0xB9, 0x33, 0xC5, 0xFF, 0x00, 0xC1, 0xB8, 0x1F, 0xF0, 0x59, 0xE1, 0xFB, 0x0C,
+	0x7C, 0x5B, 0x87, 0xF6, 0x55, 0xFD, 0xA0, 0xFC, 0x4F, 0x34, 0x7F, 0x0A, 0x7C, 0x77, 0xAA, 0x43,
+	0x1E, 0x97, 0xA8, 0x5C, 0xE1, 0xA3, 0xF0, 0xD6, 0xAF, 0x31, 0x8E, 0x1F, 0x3C, 0x75, 0xF2, 0xED,
+	0x67, 0x2A, 0x9E, 0x62, 0x8F, 0x95, 0x18, 0x07, 0x38, 0xF9, 0x88, 0xFE, 0x81, 0x3E, 0x24, 0x7E,
+	0xD0, 0x9F, 0xB0, 0x57, 0xC6, 0x4F, 0x00, 0xEB, 0x1F, 0x0A, 0x7E, 0x24, 0x7C, 0x79, 0xF8, 0x5B,
+	0xE2, 0x0F, 0x0D, 0xF8, 0x83, 0x4F, 0x9A, 0xC7, 0x5A, 0xD2, 0x75, 0x0F, 0x19, 0x58, 0xCB, 0x6F,
+	0x75, 0x04, 0xA9, 0x86, 0x8D, 0xD7, 0xCD, 0xF9, 0x95, 0x95, 0xB9, 0xE7, 0x20, 0x91, 0x8F, 0x50,
+	0x15, 0x13, 0xF8, 0xDB, 0x17, 0xF2, 0x5C, 0x20, 0xBB, 0x2A, 0x17, 0xCC, 0x19, 0x3B, 0x73, 0x8C,
+	0xF4, 0x38, 0xCF, 0xB8, 0x23, 0xEA, 0x29, 0xAB, 0xA8, 0x03, 0xFF, 0x00, 0x2D, 0x2B, 0xE8, 0xEF,
+	0xF8, 0x2B, 0xA7, 0xEC, 0x25, 0xE0, 0xBF, 0xD8, 0x17, 0xF6, 0x9F, 0x9B, 0xC1, 0xDF, 0x01, 0xFE,
+	0x28, 0xE9, 0x3E, 0x32, 0xF8, 0x67, 0xAE, 0x5B, 0xBD, 0xF7, 0x83, 0x75, 0x4D, 0x27, 0x5C, 0x82,
+	0xFE, 0x4B, 0x28, 0x3C, 0xC7, 0xDD, 0x63, 0x72, 0xD1, 0x3B, 0x1F, 0x36, 0x2C, 0x0C, 0x3B, 0x01,
+	0xE6, 0x23, 0xC6, 0xDF, 0x78, 0xB0, 0x1F, 0x2C, 0xC9, 0x74, 0x01, 0xDA, 0x1B, 0xF8, 0x79, 0xF6,
+	0xA0, 0xA3, 0x67, 0xED, 0xBF, 0x36, 0x37, 0xD2, 0x69, 0x37, 0x2F, 0x3F, 0x8F, 0xFC, 0x25, 0x0A,
+	0x49, 0xB9, 0xBF, 0xE1, 0x2D, 0xD3, 0xFF, 0x00, 0xF4, 0x72, 0xD6, 0x2F, 0xDB, 0x1F, 0xCC, 0xFB,
+	0xF5, 0x7F, 0xC0, 0xEA, 0xF7, 0x9F, 0x15, 0xFC, 0x1F, 0x0E, 0xFF, 0x00, 0xF9, 0x9B, 0x74, 0xFF,
+	0x00, 0xFD, 0x28, 0x5A, 0x01, 0xB3, 0xFB, 0x87, 0xF8, 0x75, 0xBF, 0xFE, 0x15, 0xF6, 0x83, 0xD7,
+	0xFE, 0x40, 0xD6, 0xBF, 0xFA, 0x29, 0x68, 0xA9, 0x3E, 0x1E, 0x7F, 0xC8, 0x81, 0xA1, 0xFF, 0x00,
+	0xD8, 0x1E, 0xD7, 0xFF, 0x00, 0x45, 0x2D, 0x14, 0x19, 0x9F, 0xC8, 0x2F, 0xFC, 0x17, 0x88, 0x3D,
+	0x9F, 0xFC, 0x15, 0x6F, 0xE2, 0x06, 0xDF, 0xE1, 0xB3, 0xB5, 0xFF, 0x00, 0xD1, 0x6B, 0x5F, 0x23,
+	0xFD, 0xBF, 0xEE, 0xB6, 0x7A, 0xD7, 0xD9, 0x9F, 0xF0, 0x71, 0x87, 0x87, 0x75, 0x8F, 0x09, 0xFF,
+	0x00, 0xC1, 0x53, 0xBC, 0x61, 0x7F, 0x7F, 0x66, 0xD0, 0xAD, 0xC5, 0x9D, 0xAA, 0xEE, 0x6F, 0x97,
+	0x77, 0xEE, 0xEB, 0xE1, 0xDF, 0xED, 0x27, 0x5F, 0xB8, 0xBB, 0xA3, 0x6F, 0xBB, 0xFE, 0xF5, 0x05,
+	0x72, 0x9B, 0x1F, 0x6D, 0x7F, 0x5A, 0x3E, 0xDA, 0xFE, 0xB5, 0x8F, 0xF6, 0xF1, 0xFD, 0xFA, 0x3E,
+	0xDE, 0x3F, 0xBF, 0x41, 0x46, 0xC7, 0xDB, 0x5F, 0xD6, 0x9C, 0xB7, 0x80, 0xA6, 0x19, 0xB9, 0xAC,
+	0x61, 0x7B, 0x9E, 0x8C, 0x68, 0x37, 0xB8, 0xEA, 0xC6, 0x80, 0x35, 0xE2, 0xBB, 0x2A, 0xEC, 0x85,
+	0xC2, 0xAC, 0x91, 0xED, 0x66, 0xDA, 0x0E, 0x0E, 0x41, 0x07, 0x18, 0xC9, 0xC7, 0x3C, 0x67, 0xF8,
+	0xBA, 0x75, 0xA8, 0xEE, 0x27, 0x5B, 0xEB, 0x58, 0x52, 0xFE, 0xD2, 0xDD, 0xBF, 0x78, 0xDE, 0x62,
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+	0x7F, 0xE8, 0x55, 0x86, 0x2A, 0x51, 0x94, 0xAE, 0x75, 0x60, 0x65, 0x19, 0x44, 0xDF, 0x8E, 0xE9,
+	0xE3, 0x5F, 0x91, 0xE9, 0x3E, 0xD5, 0x32, 0xF0, 0x8F, 0x4D, 0x8E, 0x3A, 0x36, 0x0A, 0xE4, 0x89,
+	0xD5, 0x29, 0x4B, 0x9A, 0xC8, 0x72, 0xDD, 0x3A, 0xFC, 0x88, 0xFB, 0x9B, 0xFB, 0xB4, 0x9F, 0x6E,
+	0x99, 0x5B, 0x6E, 0xCA, 0x58, 0xED, 0x67, 0x91, 0x77, 0x94, 0xF9, 0x17, 0xF8, 0x96, 0xB3, 0xEE,
+	0xBC, 0x59, 0xE1, 0x2B, 0x39, 0x1A, 0xDA, 0xE7, 0xC5, 0xB6, 0x28, 0xEB, 0xF7, 0xA3, 0x69, 0x7E,
+	0x65, 0xAA, 0xE5, 0xA8, 0xF6, 0x44, 0xB9, 0x47, 0xAC, 0x8D, 0x06, 0x99, 0xD7, 0xF7, 0x9F, 0x69,
+	0xDD, 0x4A, 0xB7, 0x13, 0x37, 0xF1, 0xD6, 0x43, 0x78, 0xE3, 0xE1, 0xEC, 0x6D, 0x97, 0xF1, 0xB6,
+	0x9F, 0xFF, 0x00, 0x02, 0x95, 0x68, 0xFF, 0x00, 0x85, 0x85, 0xE0, 0x03, 0xF2, 0x27, 0x8C, 0xF4,
+	0xFF, 0x00, 0xFB, 0xFB, 0x4B, 0x92, 0xA7, 0x62, 0x79, 0xA3, 0xFC, 0xC5, 0xEB, 0xAF, 0x10, 0xD8,
+	0x58, 0xDD, 0x43, 0xA6, 0xDE, 0x6A, 0xB0, 0xDB, 0xDC, 0x5D, 0x7F, 0xC7, 0xBC, 0x73, 0x48, 0xAB,
+	0xE6, 0x7F, 0xDF, 0x55, 0x62, 0x49, 0xAE, 0x15, 0x95, 0x11, 0xF7, 0x6E, 0xFE, 0x2A, 0xFC, 0xBB,
+	0xFF, 0x00, 0x83, 0x91, 0x3E, 0x27, 0x5E, 0x78, 0x37, 0xC2, 0x7F, 0x0C, 0xFE, 0x22, 0xFC, 0x22,
+	0xF8, 0xB4, 0xBA, 0x7E, 0xBD, 0xA3, 0xDC, 0x5C, 0x3D, 0x9F, 0xD9, 0x6F, 0xDA, 0x38, 0xA4, 0x6F,
+	0xFA, 0x68, 0xAB, 0xF7, 0xAA, 0x8F, 0xFC, 0x12, 0xB7, 0xFE, 0x0B, 0xF9, 0x2F, 0xC5, 0x4D, 0x2F,
+	0x4D, 0xF8, 0x39, 0xFB, 0x70, 0xD9, 0xAE, 0x9B, 0xE2, 0x79, 0x1D, 0x6D, 0x6C, 0xF5, 0xE5, 0x89,
+	0x60, 0xB5, 0x92, 0x3F, 0xBB, 0x1F, 0xFC, 0x0A, 0xBA, 0x3D, 0x85, 0xE9, 0xDD, 0x9C, 0xEF, 0x15,
+	0x4A, 0x35, 0x39, 0x5B, 0x3F, 0x54, 0x5A, 0xF9, 0xFF, 0x00, 0x87, 0xF8, 0x7E, 0x57, 0xA5, 0xFB,
+	0x54, 0xDF, 0xDE, 0xAA, 0x7A, 0x3E, 0xA9, 0xA3, 0xF8, 0x8B, 0x48, 0x8F, 0x58, 0xF0, 0xF6, 0xAB,
+	0x0D, 0xE5, 0xAC, 0xDF, 0x34, 0x57, 0x10, 0xB6, 0xE5, 0x91, 0x6A, 0xDB, 0x29, 0x5F, 0x91, 0xD2,
+	0xB9, 0xF9, 0x79, 0x64, 0x75, 0xC7, 0x96, 0xA4, 0x74, 0x22, 0x6B, 0xAB, 0x98, 0x64, 0x5B, 0x98,
+	0x66, 0xF9, 0x97, 0xE6, 0xAE, 0x57, 0xFE, 0x0A, 0x3B, 0xE2, 0x14, 0xF1, 0x37, 0xFC, 0x13, 0x27,
+	0xE2, 0xD6, 0xAA, 0x90, 0xED, 0x1F, 0xF0, 0x86, 0xDC, 0x27, 0x97, 0xFE, 0xEB, 0x2D, 0x74, 0x1A,
+	0xC6, 0xF8, 0xA1, 0x69, 0xD3, 0xF8, 0x6B, 0xC9, 0xFF, 0x00, 0x6C, 0x1D, 0x7E, 0x5D, 0x5B, 0xFE,
+	0x09, 0xD5, 0xF1, 0xC2, 0xC4, 0xB7, 0xEE, 0x61, 0xF0, 0x6C, 0x8D, 0x1A, 0xFF, 0x00, 0xC0, 0xA9,
+	0xC7, 0xF8, 0x8B, 0xD4, 0x99, 0xC7, 0x96, 0x9C, 0xBD, 0x0F, 0xE6, 0xA7, 0xE0, 0x07, 0x9C, 0x7C,
+	0x3B, 0x7D, 0xCF, 0xFC, 0xC4, 0x1A, 0x8A, 0x83, 0xE0, 0x8A, 0x48, 0x74, 0x1B, 0xED, 0x93, 0x7F,
+	0xCC, 0x4A, 0x4A, 0x2B, 0xDD, 0xE4, 0x3C, 0x68, 0x54, 0xF7, 0x51, 0xF4, 0xFF, 0x00, 0xFC, 0x11,
+	0x21, 0x76, 0xFF, 0x00, 0xC1, 0x64, 0xFE, 0x1F, 0xB3, 0x8F, 0xF5, 0x9A, 0xA7, 0xFE, 0xD3, 0x6A,
+	0xFE, 0x80, 0x2C, 0xE1, 0x0D, 0xE3, 0x6D, 0x55, 0xFE, 0xF3, 0x7F, 0x6B, 0x4D, 0xFF, 0x00, 0xA1,
+	0x57, 0xF3, 0xFF, 0x00, 0xFF, 0x00, 0x04, 0x4B, 0x38, 0xFF, 0x00, 0x82, 0xC7, 0xFC, 0x3B, 0x3F,
+	0xF5, 0x14, 0xFF, 0x00, 0xDA, 0x75, 0xFD, 0x06, 0x69, 0xB1, 0xFF, 0x00, 0xC5, 0x63, 0xAA, 0xB9,
+	0xFF, 0x00, 0xA0, 0xB4, 0xDF, 0xFA, 0x15, 0x79, 0x38, 0xA8, 0x35, 0x52, 0xC8, 0xEC, 0xCA, 0xE4,
+	0xE3, 0x85, 0xBB, 0xDC, 0xE9, 0x61, 0xB1, 0xF9, 0x77, 0xBF, 0xCB, 0xFE, 0xED, 0x78, 0xC7, 0xED,
+	0xB5, 0xFB, 0x73, 0x7C, 0x0B, 0xFD, 0x85, 0x7C, 0x02, 0xFE, 0x2D, 0xF8, 0xB7, 0xAF, 0x2C, 0x37,
+	0x93, 0x5A, 0xB3, 0xE9, 0x76, 0x2B, 0xF3, 0x79, 0xCD, 0xFC, 0x2A, 0xCB, 0xFE, 0xF5, 0x7B, 0x37,
+	0x8C, 0xBC, 0x45, 0xA6, 0xF8, 0x07, 0xE1, 0xFE, 0xB9, 0xF1, 0x0B, 0x52, 0x7F, 0xF4, 0x6D, 0x07,
+	0x49, 0x9B, 0x51, 0xB8, 0x66, 0xFF, 0x00, 0x9E, 0x71, 0xAE, 0xE6, 0x5A, 0xFE, 0x5F, 0xFF, 0x00,
+	0xE0, 0xA1, 0x1F, 0xB7, 0x36, 0xBF, 0xFF, 0x00, 0x05, 0x08, 0xF8, 0xF1, 0xAE, 0x7C, 0x42, 0xF1,
+	0x6D, 0xCC, 0xD2, 0x78, 0x4F, 0x4B, 0xD4, 0x19, 0x3C, 0x2B, 0x66, 0xB2, 0xED, 0x56, 0x87, 0xFF,
+	0x00, 0x66, 0xF9, 0xAA, 0xB0, 0xB4, 0x63, 0x2A, 0x89, 0x4D, 0x5C, 0xAC, 0x76, 0x26, 0x54, 0x69,
+	0xFB, 0xAE, 0xCC, 0xF6, 0x2F, 0xDA, 0x5B, 0xFE, 0x0B, 0xF3, 0xFB, 0x6D, 0xFE, 0xD3, 0x13, 0x5F,
+	0x5B, 0x78, 0x4B, 0x4B, 0x87, 0xC0, 0x7A, 0x5C, 0x72, 0x30, 0x5B, 0x8D, 0x0E, 0xF1, 0x96, 0x46,
+	0x8F, 0x77, 0xCA, 0xD5, 0xF3, 0xAE, 0xB9, 0xFB, 0x5A, 0x7E, 0xD5, 0xDE, 0x22, 0xB7, 0xB7, 0xB9,
+	0xFF, 0x00, 0x86, 0x9C, 0xF1, 0x22, 0xCD, 0x71, 0x2E, 0xD6, 0x9B, 0xED, 0x5F, 0x35, 0x79, 0xDE,
+	0xB5, 0xAC, 0x6E, 0x85, 0x5E, 0xE6, 0xDB, 0xCB, 0x86, 0x65, 0xDA, 0xB0, 0xAF, 0xF1, 0x56, 0xA6,
+	0x93, 0xF0, 0xC7, 0xC7, 0xFE, 0x28, 0xD0, 0x5E, 0xFF, 0x00, 0xC2, 0x5F, 0x0D, 0x35, 0x09, 0xAD,
+	0xE1, 0x5D, 0xFE, 0x72, 0xAB, 0x57, 0xB9, 0xEC, 0xB0, 0xB1, 0x56, 0xB2, 0x3E, 0x75, 0x56, 0xC6,
+	0x54, 0x9D, 0xDB, 0x7A, 0x9D, 0x43, 0x7E, 0xD2, 0x9F, 0xB4, 0xFC, 0x7F, 0xB9, 0xFF, 0x00, 0x86,
+	0x93, 0xF1, 0x23, 0xB4, 0x7F, 0x2B, 0x33, 0x5C, 0x7D, 0xEA, 0x63, 0xFE, 0xD2, 0x9F, 0xB5, 0x2B,
+	0xFC, 0x90, 0xFE, 0xD1, 0xBE, 0x22, 0xDD, 0xFF, 0x00, 0x5F, 0x15, 0x95, 0x6F, 0xF0, 0x6F, 0xE3,
+	0x7C, 0xD6, 0x71, 0xBF, 0xFC, 0x2A, 0x2D, 0x53, 0x73, 0x2F, 0xF7, 0x5A, 0x9B, 0x27, 0xC1, 0x7F,
+	0x8D, 0x31, 0xAF, 0xC9, 0xF0, 0x97, 0x52, 0xDD, 0xFE, 0xEB, 0x50, 0xA3, 0x85, 0xEC, 0x8D, 0x25,
+	0xF5, 0xAB, 0x69, 0x72, 0xBF, 0x8E, 0xBE, 0x25, 0x7C, 0x51, 0xF1, 0xEE, 0x94, 0xCF, 0xF1, 0x53,
+	0xE2, 0x46, 0xA1, 0xE2, 0xAB, 0x5B, 0x1F, 0x9B, 0xCB, 0xD4, 0xA5, 0xDC, 0xD6, 0xBF, 0xF5, 0xCD,
+	0x6B, 0x0C, 0x5F, 0xFF, 0x00, 0xC2, 0x49, 0x67, 0x6B, 0xA9, 0x59, 0xDF, 0xCC, 0xF1, 0xDA, 0xCB,
+	0xFE, 0x8F, 0x75, 0x71, 0xF2, 0xC9, 0x0B, 0x2F, 0xF7, 0x6B, 0x53, 0x52, 0xF8, 0x7F, 0xE2, 0xAF,
+	0x06, 0x5D, 0x5B, 0x5F, 0xF8, 0xB7, 0xC2, 0xB7, 0x5A, 0x5A, 0x49, 0xBB, 0xF7, 0x37, 0x1F, 0xF2,
+	0xF1, 0x54, 0xB5, 0x4B, 0x85, 0xD6, 0x6C, 0xE4, 0xD5, 0x5A, 0xDB, 0xC9, 0xF2, 0x7F, 0xD5, 0x69,
+	0x2B, 0xFE, 0xB2, 0x4A, 0xA9, 0xC7, 0x09, 0xC9, 0xA2, 0x47, 0x34, 0x69, 0xE2, 0x25, 0x5A, 0xEE,
+	0xE7, 0xD7, 0x7F, 0xF0, 0x4E, 0xFF, 0x00, 0xF8, 0x2D, 0x07, 0xED, 0x27, 0xFB, 0x16, 0xEA, 0x11,
+	0xF8, 0x27, 0xC7, 0x93, 0x49, 0xE3, 0x0F, 0x08, 0xCD, 0x75, 0xF3, 0x5F, 0x6B, 0x17, 0x0C, 0xCF,
+	0x67, 0x1F, 0xF7, 0x63, 0x5F, 0xEE, 0xAA, 0xD7, 0xEE, 0xFF, 0x00, 0xEC, 0x93, 0xFB, 0x57, 0x7C,
+	0x1F, 0xFD, 0xB2, 0x7E, 0x15, 0xC3, 0xF1, 0x2F, 0xE1, 0x46, 0xB6, 0xB7, 0x56, 0xF1, 0xAA, 0xAD,
+	0xFA, 0xFF, 0x00, 0x14, 0x72, 0x37, 0xF0, 0xD7, 0xE0, 0x27, 0xEC, 0x3F, 0xFF, 0x00, 0x04, 0x97,
+	0xFD, 0xA9, 0x7F, 0xE0, 0xA0, 0x50, 0xD8, 0xDF, 0xE9, 0xBA, 0x3D, 0xC7, 0x83, 0xFC, 0x23, 0xE7,
+	0xAC, 0x57, 0xFA, 0xC5, 0xF5, 0xBF, 0x99, 0x1C, 0xD1, 0xFF, 0x00, 0x14, 0x3F, 0xEF, 0x6D, 0xAF,
+	0xDE, 0xEF, 0xD8, 0x67, 0xFE, 0x09, 0xFB, 0xF0, 0x13, 0xF6, 0x07, 0xF8, 0x55, 0x6D, 0xF0, 0xEB,
+	0xE1, 0x16, 0x8F, 0x32, 0xCC, 0xB1, 0x2F, 0xF6, 0xB5, 0xE3, 0x5D, 0x33, 0x2D, 0xD4, 0xCB, 0xFF,
+	0x00, 0x2D, 0x15, 0x5B, 0xEE, 0xD7, 0x8B, 0x88, 0x8D, 0x15, 0x2F, 0x75, 0x1F, 0x4B, 0x84, 0xE7,
+	0x8C, 0x75, 0x3D, 0x27, 0xC5, 0x16, 0x2F, 0x0D, 0x9B, 0xA3, 0xFC, 0xBF, 0x2F, 0xF0, 0xD7, 0x88,
+	0xFE, 0xD5, 0xAA, 0xBF, 0xF0, 0xC0, 0x1F, 0x1E, 0x30, 0x36, 0xAF, 0xFC, 0x21, 0x6D, 0xF2, 0xFF,
+	0x00, 0xC0, 0xAB, 0xDE, 0xFC, 0x51, 0x6B, 0xFE, 0x86, 0xEF, 0xFE, 0xCF, 0xCD, 0x5E, 0x0F, 0xFB,
+	0x59, 0xAF, 0x97, 0xFB, 0x00, 0xFC, 0x7B, 0x3F, 0xF5, 0x26, 0xC9, 0xFF, 0x00, 0xA1, 0x57, 0x1A,
+	0xF8, 0xA3, 0xEA, 0x77, 0x3F, 0x7A, 0x9C, 0xEF, 0xD8, 0xFE, 0x6C, 0x3E, 0x02, 0x46, 0x47, 0x87,
+	0xAF, 0xF1, 0xFF, 0x00, 0x41, 0x29, 0x28, 0xA7, 0x7C, 0x03, 0x39, 0xF0, 0xF5, 0xFF, 0x00, 0xFD,
+	0x84, 0xA4, 0xA2, 0xBE, 0x96, 0x34, 0xE2, 0xD5, 0xCF, 0x9C, 0x8E, 0xC7, 0xD3, 0x3F, 0xF0, 0x44,
+	0xF5, 0xDB, 0xFF, 0x00, 0x05, 0x91, 0xF8, 0x76, 0x31, 0xFF, 0x00, 0x31, 0x4F, 0xFD, 0xA6, 0xD5,
+	0xFD, 0x0B, 0x68, 0xF1, 0xA7, 0xFC, 0x26, 0x1A, 0xA6, 0xFF, 0x00, 0xFA, 0x0B, 0x4D, 0xFF, 0x00,
+	0xA1, 0x57, 0xF3, 0xCF, 0xFF, 0x00, 0x04, 0x4D, 0x57, 0x6F, 0xF8, 0x2C, 0x97, 0xC3, 0xA7, 0xFF,
+	0x00, 0xA8, 0xA7, 0xFE, 0xD3, 0x6A, 0xFE, 0x86, 0x34, 0x75, 0xC7, 0x8B, 0xB5, 0x42, 0x3F, 0xE8,
+	0x2D, 0x37, 0xFE, 0x85, 0x5E, 0x16, 0x39, 0xBF, 0x6C, 0x7B, 0x58, 0x58, 0xC7, 0xD8, 0xA6, 0x8F,
+	0x2F, 0xFF, 0x00, 0x82, 0xA9, 0xF8, 0xBB, 0xC6, 0x1E, 0x0F, 0xFD, 0x86, 0x7C, 0x60, 0x9E, 0x00,
+	0xD1, 0xE6, 0xBE, 0xBE, 0xD5, 0xB4, 0xDB, 0x8B, 0x06, 0xB7, 0xB5, 0x87, 0xCC, 0x93, 0xCB, 0x92,
+	0x36, 0x56, 0xF9, 0x6B, 0xF9, 0x9B, 0xF8, 0x77, 0xF0, 0x17, 0xE3, 0x96, 0x9B, 0xA1, 0x58, 0xE8,
+	0x3A, 0x57, 0xC0, 0xAF, 0x12, 0x49, 0x73, 0x6E, 0xB2, 0x2F, 0xEF, 0xB4, 0x99, 0x36, 0x37, 0xCC,
+	0xD5, 0xFD, 0x70, 0xEA, 0x7A, 0x3D, 0x86, 0xB5, 0x66, 0xD6, 0x1A, 0xC5, 0x84, 0x73, 0xDA, 0xB2,
+	0xFC, 0xD0, 0xC9, 0xF7, 0x5A, 0xB1, 0xAD, 0xFE, 0x11, 0xFC, 0x34, 0xB1, 0x58, 0xFE, 0xC1, 0xE0,
+	0xCB, 0x38, 0xFE, 0x5F, 0xE1, 0x89, 0x6B, 0x3A, 0x75, 0xBD, 0x9D, 0x44, 0xC5, 0x8C, 0xC3, 0x7B,
+	0x6B, 0x34, 0x7F, 0x38, 0x1F, 0xF0, 0x4C, 0x5F, 0xF8, 0x27, 0x9F, 0xC5, 0x7F, 0xDA, 0x73, 0xF6,
+	0xB4, 0xB0, 0xF0, 0xDF, 0xC4, 0x2F, 0x86, 0x9A, 0xB6, 0x9F, 0xE1, 0xED, 0x3E, 0xE9, 0x5B, 0x52,
+	0x93, 0x52, 0xB0, 0x68, 0xE3, 0x55, 0xFF, 0x00, 0x81, 0x57, 0xF4, 0x37, 0xF0, 0xF7, 0xF6, 0x4D,
+	0xFD, 0x9E, 0x3E, 0x14, 0xF8, 0x56, 0xDB, 0xC1, 0x3A, 0x0F, 0xC2, 0x8D, 0x0E, 0x68, 0x6D, 0xE2,
+	0x55, 0x96, 0x49, 0xAC, 0x15, 0x99, 0xAB, 0xB4, 0xD0, 0xFC, 0x21, 0xE1, 0x9F, 0x0B, 0xC9, 0x70,
+	0xFE, 0x15, 0xD1, 0x2D, 0xED, 0x6E, 0x2E, 0x3F, 0xE3, 0xE2, 0x48, 0xE2, 0x55, 0xF3, 0x2A, 0xFC,
+	0x90, 0xBC, 0x72, 0x2E, 0xC7, 0xDA, 0xDF, 0xC5, 0x45, 0x4A, 0x95, 0x25, 0x26, 0xEE, 0x55, 0x3A,
+	0x34, 0x62, 0x92, 0xB1, 0xCC, 0x2F, 0xC1, 0x5F, 0x82, 0x71, 0xAA, 0xEC, 0xF8, 0x3F, 0xE1, 0xF5,
+	0xDB, 0xFC, 0x3F, 0xD9, 0xAB, 0x47, 0xFC, 0x29, 0x4F, 0x82, 0x0B, 0xF3, 0xA7, 0xC1, 0xFF, 0x00,
+	0x0E, 0xE7, 0xFE, 0xC1, 0xAB, 0x5D, 0x43, 0x43, 0x22, 0xFF, 0x00, 0xB5, 0xBA, 0x99, 0xE5, 0x37,
+	0xF7, 0x2A, 0x13, 0xAD, 0xDC, 0xE8, 0x51, 0xA5, 0xD8, 0xFC, 0x9C, 0xFF, 0x00, 0x83, 0x97, 0xBE,
+	0x13, 0xF8, 0x62, 0xDF, 0xC2, 0x3F, 0x0B, 0xF4, 0x2F, 0x84, 0xBF, 0x06, 0x99, 0xB5, 0xCD, 0x52,
+	0xE2, 0xE1, 0x2D, 0x7F, 0xE1, 0x1F, 0xD2, 0xFE, 0x5D, 0xDF, 0xF4, 0xD7, 0x6D, 0x71, 0x7F, 0xF0,
+	0x4A, 0x3F, 0xF8, 0x37, 0x8F, 0xC5, 0xB6, 0xBA, 0xF5, 0xBF, 0xED, 0x09, 0xFB, 0x6D, 0xDF, 0xDB,
+	0xB7, 0x9D, 0x6F, 0x1C, 0xBA, 0x6E, 0x8F, 0xA7, 0xCB, 0xBA, 0x3F, 0xEF, 0x2F, 0x99, 0x1B, 0x57,
+	0xEC, 0x17, 0x89, 0x3E, 0x1E, 0xF8, 0x3F, 0xC6, 0x57, 0xD6, 0x7A, 0x97, 0x8A, 0xBC, 0x3D, 0x0D,
+	0xFD, 0xC6, 0x9A, 0xCC, 0xD6, 0x0D, 0x32, 0xEE, 0xF2, 0x5B, 0xF8, 0xB6, 0xD6, 0xB2, 0xDB, 0xEE,
+	0x54, 0xB6, 0x85, 0x55, 0x16, 0x3F, 0x97, 0x6A, 0xFF, 0x00, 0x76, 0xB5, 0x55, 0xA7, 0x18, 0xD9,
+	0xB3, 0x19, 0x50, 0x84, 0xA5, 0xCC, 0x91, 0x97, 0xE0, 0xDF, 0x06, 0xF8, 0x4B, 0xE1, 0xDF, 0x86,
+	0xE1, 0xF0, 0x77, 0x80, 0xF4, 0x4B, 0x5D, 0x2F, 0x4D, 0xB7, 0x5F, 0x92, 0xDE, 0xCE, 0x2D, 0x88,
+	0xDF, 0xED, 0x32, 0xFF, 0x00, 0x7A, 0xB5, 0xAD, 0x55, 0x1B, 0x6A, 0x39, 0xDB, 0xB9, 0x69, 0xAB,
+	0x6E, 0x7E, 0x64, 0xD9, 0xBB, 0xFD, 0x9A, 0x7C, 0x71, 0xBC, 0x2D, 0xF3, 0xAE, 0xE5, 0x6F, 0xFC,
+	0x76, 0xB1, 0x94, 0xA5, 0x23, 0x68, 0xC5, 0x47, 0x63, 0x33, 0xC4, 0xD0, 0xA7, 0xD8, 0x5D, 0xFF,
+	0x00, 0x8B, 0x6D, 0x7C, 0xFF, 0x00, 0xFB, 0x5D, 0xC7, 0xB7, 0xF6, 0x02, 0xF8, 0xF4, 0x07, 0xFD,
+	0x09, 0xB2, 0x7F, 0xE8, 0x55, 0xF4, 0x27, 0x89, 0xA3, 0xF2, 0x74, 0xF9, 0x21, 0xDF, 0xF7, 0x56,
+	0xBE, 0x7D, 0xFD, 0xAF, 0x7F, 0xE4, 0xC0, 0xFE, 0x3C, 0xFF, 0x00, 0xD8, 0x96, 0xDF, 0xFA, 0x11,
+	0xA5, 0x1D, 0x25, 0x1F, 0x52, 0xAF, 0x7A, 0x73, 0xF4, 0x3F, 0x9A, 0xBF, 0x80, 0x63, 0x1E, 0x1E,
+	0xBF, 0x03, 0xFE, 0x82, 0x52, 0x51, 0x4E, 0xF8, 0x0B, 0xFF, 0x00, 0x20, 0x0D, 0x43, 0xFE, 0xC2,
+	0x52, 0x51, 0x5F, 0x53, 0x1F, 0x85, 0x1F, 0x35, 0x1D, 0x8F, 0xA5, 0xBF, 0xE0, 0x89, 0xED, 0xFF,
+	0x00, 0x1B, 0x90, 0xF8, 0x74, 0x07, 0xFD, 0x05, 0x3F, 0xF6, 0x9D, 0x7F, 0x42, 0x5A, 0x6D, 0xD2,
+	0x2F, 0x8C, 0x35, 0x4D, 0xFF, 0x00, 0xF4, 0x16, 0x9B, 0xFF, 0x00, 0x46, 0x57, 0xF3, 0xDB, 0xFF,
+	0x00, 0x04, 0x4D, 0x5C, 0xFF, 0x00, 0xC1, 0x63, 0xBE, 0x1D, 0x9F, 0xFA, 0x8A, 0x7F, 0xED, 0x36,
+	0xAF, 0xDF, 0x78, 0xF5, 0x4F, 0xF8, 0xAE, 0x35, 0x54, 0xFE, 0xEE, 0xAD, 0x37, 0xFE, 0x8C, 0xAF,
+	0x07, 0x1C, 0xF9, 0xAB, 0x5D, 0x9E, 0xAE, 0x06, 0xF2, 0xC3, 0xF2, 0x9E, 0x96, 0xDA, 0x82, 0x47,
+	0x22, 0xBB, 0xBE, 0xE5, 0xFB, 0xBE, 0x5D, 0x35, 0xAF, 0x21, 0xF3, 0x3E, 0x47, 0xDB, 0xBB, 0xFB,
+	0xD5, 0x80, 0xDA, 0x93, 0x88, 0xFC, 0xC2, 0xF5, 0x16, 0xAD, 0xE2, 0x2D, 0x27, 0x45, 0xD2, 0x6E,
+	0x35, 0x8D, 0x6F, 0x58, 0xB5, 0xB0, 0xB7, 0xB7, 0x89, 0xA5, 0x6B, 0xAB, 0xEB, 0x85, 0x8A, 0x35,
+	0x55, 0x5D, 0xCD, 0xF3, 0x37, 0xF1, 0x57, 0x1B, 0xF7, 0xA5, 0x63, 0xD0, 0xF6, 0x9E, 0xCE, 0x95,
+	0x99, 0xD3, 0x43, 0x73, 0x35, 0xCC, 0x7B, 0x37, 0xEE, 0xFE, 0xEE, 0xDA, 0xF2, 0x2F, 0x88, 0x1F,
+	0xB7, 0x67, 0xEC, 0xF1, 0xE0, 0x1F, 0x8E, 0x1A, 0x57, 0xEC, 0xF7, 0xA9, 0x78, 0xCE, 0xD6, 0x4F,
+	0x13, 0xEA, 0x92, 0xC7, 0x15, 0xAE, 0x9F, 0x1D, 0xC7, 0xEF, 0x15, 0x9B, 0xEE, 0xEE, 0x5A, 0xFC,
+	0xE5, 0xFF, 0x00, 0x82, 0x9B, 0x7F, 0xC1, 0x7C, 0x34, 0x7D, 0x37, 0x43, 0xD6, 0x3E, 0x0E, 0x7E,
+	0xCA, 0x17, 0x8D, 0x26, 0xA1, 0x22, 0xB4, 0x0B, 0xAB, 0x2F, 0xCA, 0xD1, 0xB7, 0xF1, 0x32, 0xB2,
+	0xD7, 0xE7, 0x2F, 0xEC, 0x2F, 0xF1, 0xB3, 0x5B, 0xD0, 0x7F, 0x6F, 0xAF, 0x0A, 0x7E, 0xD1, 0x5F,
+	0xB5, 0x5F, 0x8E, 0x6E, 0xB5, 0x49, 0xA3, 0xD6, 0xA1, 0x96, 0x5B, 0xC9, 0xA5, 0xF3, 0x5A, 0x35,
+	0x56, 0xAD, 0xFE, 0xAB, 0x51, 0xEA, 0x71, 0xAC, 0x65, 0x3D, 0xAC, 0x8F, 0xEA, 0x3E, 0x4B, 0xE6,
+	0xB7, 0x91, 0x91, 0xDF, 0xE6, 0x5F, 0xBD, 0x4D, 0xFE, 0xD6, 0xFF, 0x00, 0xA6, 0x95, 0xF2, 0x7E,
+	0xA1, 0xFF, 0x00, 0x05, 0x8E, 0xFD, 0x84, 0xE4, 0xBE, 0x92, 0x6F, 0xF8, 0x58, 0x57, 0x1B, 0x99,
+	0xB7, 0x6D, 0xDA, 0xB5, 0x1A, 0xFF, 0x00, 0xC1, 0x61, 0xBF, 0x61, 0x59, 0x3E, 0x77, 0xF8, 0x85,
+	0x70, 0x3F, 0xE0, 0x2B, 0x51, 0xEC, 0x6A, 0xC4, 0xDA, 0x35, 0xE9, 0xC8, 0xFA, 0xD1, 0xB5, 0x6D,
+	0xDF, 0x27, 0x9C, 0xAB, 0x5C, 0xB7, 0xC6, 0x8F, 0x8E, 0xDF, 0x0F, 0x7E, 0x02, 0xFC, 0x3F, 0xBC,
+	0xF8, 0x91, 0xF1, 0x47, 0x5E, 0x86, 0xC3, 0x4B, 0xD3, 0xE2, 0x69, 0x65, 0xB8, 0x9A, 0x5F, 0x2D,
+	0x76, 0xAD, 0x7C, 0xE1, 0x71, 0xFF, 0x00, 0x05, 0x9A, 0xFD, 0x83, 0xED, 0xE3, 0x37, 0x37, 0x3E,
+	0x39, 0x99, 0x52, 0x15, 0xF9, 0xBE, 0x55, 0xF9, 0xAB, 0xF2, 0xF3, 0xFE, 0x0B, 0x55, 0xFF, 0x00,
+	0x05, 0x64, 0xD1, 0x3F, 0x6D, 0x4D, 0x1E, 0xC7, 0xE0, 0x3F, 0xC1, 0xCB, 0xFB, 0x88, 0x74, 0x6D,
+	0x26, 0xF1, 0xAE, 0x75, 0x29, 0x15, 0x7C, 0xBF, 0xB6, 0x42, 0xDF, 0xF2, 0xCD, 0xFF, 0x00, 0xBC,
+	0xB5, 0xB5, 0x0C, 0x2C, 0xEA, 0xD4, 0xB4, 0x8C, 0x71, 0x18, 0xCA, 0x74, 0x63, 0x78, 0xEE, 0x7E,
+	0xB3, 0x69, 0x7F, 0xF0, 0x57, 0xCF, 0xD8, 0x57, 0x52, 0xD3, 0xD6, 0xF1, 0x3E, 0x37, 0xE8, 0xA9,
+	0x1C, 0x91, 0xF9, 0xFB, 0x9A, 0xFD, 0x7E, 0xED, 0x77, 0x7F, 0xB3, 0x4F, 0xED, 0xF5, 0xFB, 0x36,
+	0x7E, 0xD6, 0x9A, 0x85, 0xE6, 0x89, 0xF0, 0x4F, 0xC7, 0x96, 0x3A, 0xA5, 0xC5, 0x8C, 0xBB, 0x5A,
+	0x3B, 0x5B, 0x8F, 0x31, 0xAB, 0xF9, 0x60, 0xB7, 0xB8, 0xD3, 0x5A, 0xE2, 0x1F, 0x0D, 0xE9, 0x5A,
+	0x24, 0x2F, 0x6D, 0x25, 0x96, 0xCB, 0x89, 0x99, 0x7F, 0xD4, 0xAF, 0xF1, 0x57, 0xEA, 0x87, 0xFC,
+	0x1A, 0xAF, 0xF0, 0x67, 0xFB, 0x3D, 0x7E, 0x28, 0x7C, 0x54, 0x48, 0x64, 0x86, 0xDF, 0x45, 0xF1,
+	0x1A, 0xD9, 0xD8, 0x33, 0x2E, 0xD5, 0xB8, 0x8D, 0x97, 0xEF, 0x7F, 0xB5, 0x57, 0x88, 0xC2, 0xC7,
+	0x0F, 0xD4, 0xCF, 0x0B, 0x8E, 0x96, 0x23, 0x74, 0x8F, 0xD9, 0xFF, 0x00, 0x12, 0xDF, 0x3B, 0x69,
+	0xEC, 0xFB, 0xD5, 0x77, 0x2F, 0xCC, 0xB5, 0xE0, 0x7F, 0xB5, 0xB4, 0xDE, 0x67, 0xEC, 0x03, 0xF1,
+	0xEB, 0x67, 0xFD, 0x09, 0xB2, 0x7F, 0xE8, 0x55, 0xEB, 0x9E, 0x26, 0xD5, 0x7C, 0x9B, 0x16, 0x47,
+	0x7D, 0xCC, 0xCB, 0x5E, 0x2F, 0xFB, 0x4F, 0xCA, 0xF2, 0xFF, 0x00, 0xC1, 0x3D, 0x7E, 0x3D, 0x4D,
+	0xFF, 0x00, 0x52, 0x6C, 0x9F, 0xFA, 0x15, 0x72, 0x2D, 0xE3, 0xEA, 0x77, 0x7F, 0xCB, 0xB9, 0xFA,
+	0x1F, 0xCD, 0xE7, 0xC0, 0x4F, 0xF9, 0x17, 0xEF, 0xFF, 0x00, 0xEC, 0x25, 0x25, 0x14, 0x9F, 0x01,
+	0x98, 0x8F, 0x0F, 0xDF, 0xE3, 0xFE, 0x82, 0x52, 0x51, 0x5F, 0x51, 0x1F, 0x85, 0x1F, 0x39, 0x1D,
+	0x8F, 0xA6, 0xBF, 0xE0, 0x89, 0x7F, 0xF2, 0x98, 0xDF, 0x87, 0x7F, 0xF6, 0x14, 0xFF, 0x00, 0xDA,
+	0x6D, 0x5F, 0xBA, 0x51, 0x6B, 0x1E, 0x5F, 0x8F, 0xB5, 0xA4, 0xDF, 0xFF, 0x00, 0x31, 0x9B, 0x8F,
+	0xFD, 0x18, 0xD5, 0xF8, 0x57, 0xFF, 0x00, 0x04, 0x49, 0xDB, 0xFF, 0x00, 0x0F, 0x8F, 0xF8, 0x7F,
+	0xBB, 0x73, 0x6D, 0xD4, 0x7F, 0x87, 0xFE, 0xB9, 0xB5, 0x7E, 0xCF, 0x37, 0x8D, 0x2D, 0x5B, 0xE2,
+	0x7E, 0xB9, 0x0A, 0x4C, 0xAE, 0xAB, 0xAF, 0x5C, 0x2E, 0xD5, 0xFB, 0xDF, 0xEB, 0x1A, 0xBE, 0x77,
+	0x19, 0xFC, 0x53, 0xD7, 0xCB, 0x7F, 0x82, 0x7A, 0x87, 0x8B, 0xBC, 0x75, 0x37, 0x84, 0x7C, 0x1F,
+	0xAA, 0xF8, 0xB6, 0xDB, 0x47, 0x6D, 0x41, 0xF4, 0xBB, 0x09, 0x2E, 0x96, 0xC5, 0x5B, 0x6B, 0x4D,
+	0xE5, 0xAE, 0xED, 0xBF, 0xF0, 0x2A, 0xFC, 0x00, 0xFD, 0xBF, 0xBF, 0xE0, 0xAE, 0xDF, 0xB5, 0x5F,
+	0xED, 0x77, 0xF1, 0x43, 0x5A, 0xF0, 0x05, 0xE5, 0xB5, 0xF7, 0x82, 0x7C, 0x03, 0xA6, 0xDC, 0x34,
+	0x3A, 0x97, 0x85, 0x64, 0x6F, 0x9A, 0xE9, 0xBF, 0x85, 0xBC, 0xCF, 0xBD, 0xF2, 0xD7, 0xEF, 0x3C,
+	0x7A, 0xDA, 0x49, 0x6A, 0xFB, 0xF6, 0xBA, 0xC9, 0xF2, 0xB4, 0x6D, 0xF7, 0x5A, 0x3F, 0xEE, 0xB5,
+	0x7C, 0x97, 0xFB, 0x7C, 0x7F, 0xC1, 0x26, 0x7F, 0x66, 0xCF, 0xDB, 0x4B, 0x4B, 0x5F, 0x10, 0xD8,
+	0x69, 0xB2, 0x68, 0x3E, 0x26, 0xB7, 0xB7, 0x6F, 0xB0, 0x49, 0xA5, 0xED, 0x82, 0x09, 0x9B, 0xFB,
+	0xD2, 0xED, 0xFB, 0xD4, 0xA8, 0xA5, 0xCF, 0xA9, 0xD1, 0x88, 0xE6, 0xF6, 0x6E, 0xC7, 0xE0, 0xFC,
+	0x3A, 0xA6, 0x89, 0xA5, 0xC3, 0x34, 0x30, 0xDA, 0xB2, 0x3C, 0xDF, 0x7A, 0x69, 0x1B, 0x76, 0xDA,
+	0xB3, 0x1D, 0xAE, 0x9B, 0xA8, 0x68, 0xAF, 0xF6, 0x3B, 0x9F, 0x3A, 0xFE, 0x3F, 0x9E, 0x26, 0x5A,
+	0xEF, 0xFF, 0x00, 0x69, 0x8F, 0xD8, 0xDF, 0xF6, 0x81, 0xFD, 0x8C, 0xFC, 0x54, 0xDE, 0x0F, 0xF8,
+	0xDF, 0xE1, 0xB5, 0xB9, 0xB3, 0xF3, 0x59, 0x6D, 0x75, 0xCB, 0x1B, 0x76, 0xFB, 0x36, 0xDF, 0xE1,
+	0xDD, 0x25, 0x73, 0x3F, 0x09, 0xFE, 0x1C, 0x78, 0xC3, 0xE2, 0xD7, 0xC4, 0x6D, 0x3F, 0xE1, 0x47,
+	0xC3, 0xA9, 0xAC, 0xEE, 0x35, 0x0D, 0x72, 0x55, 0x82, 0xC2, 0xF2, 0x3F, 0x9A, 0x28, 0xD9, 0xBE,
+	0xEE, 0xE6, 0xAF, 0xA3, 0x8D, 0x4A, 0x3E, 0xCD, 0x23, 0xE4, 0xE5, 0x86, 0xC6, 0x4A, 0xA3, 0x6B,
+	0xB9, 0xCD, 0x43, 0xA7, 0x7E, 0xED, 0x5E, 0xF3, 0xED, 0x1E, 0x77, 0xFC, 0xB4, 0xFF, 0x00, 0x48,
+	0x6F, 0xBD, 0x4B, 0xFD, 0x97, 0x6A, 0xCF, 0xBD, 0xFE, 0xD1, 0xBB, 0xFE, 0xBE, 0x1A, 0xBE, 0xBA,
+	0x6F, 0xF8, 0x22, 0x1F, 0xED, 0xFF, 0x00, 0x6F, 0x33, 0xDB, 0x4D, 0xA9, 0x78, 0x75, 0x9E, 0x36,
+	0xDA, 0xCD, 0xB5, 0xBE, 0x6A, 0x72, 0xFF, 0x00, 0xC1, 0x0F, 0xFF, 0x00, 0x6F, 0xC5, 0xF9, 0xFF,
+	0x00, 0xB5, 0x7C, 0x37, 0xFF, 0x00, 0x8F, 0x57, 0x3C, 0xA7, 0x44, 0xDA, 0x38, 0x6C, 0x5D, 0x8F,
+	0x90, 0x75, 0x0B, 0x4B, 0x6B, 0x88, 0xD1, 0x26, 0xB6, 0xB8, 0x65, 0x5F, 0xFA, 0x78, 0x6A, 0xB1,
+	0x0A, 0xD9, 0xDD, 0x5E, 0x2E, 0xA4, 0x9F, 0xE8, 0xF0, 0xC8, 0xBE, 0x55, 0xE4, 0x8D, 0xF3, 0x7E,
+	0xED, 0x6B, 0xEB, 0xED, 0x2B, 0xFE, 0x08, 0x6B, 0xFB, 0x76, 0x8D, 0x4A, 0x3B, 0xCD, 0x4B, 0x58,
+	0xF0, 0xEE, 0xC8, 0xFF, 0x00, 0x85, 0x77, 0x6D, 0xAF, 0x52, 0xF8, 0x4F, 0xFF, 0x00, 0x06, 0xEE,
+	0xFC, 0x57, 0xF1, 0x65, 0xF9, 0xB9, 0xF8, 0xFD, 0xE3, 0x9D, 0x35, 0x34, 0x7B, 0xCF, 0x92, 0xEA,
+	0x1D, 0x0E, 0xE3, 0xCB, 0x95, 0x63, 0xAC, 0xFE, 0xB5, 0x4A, 0x9E, 0xC6, 0x9F, 0x52, 0xAD, 0x52,
+	0xCA, 0x47, 0xC3, 0xBF, 0x00, 0xFF, 0x00, 0x67, 0xFF, 0x00, 0x89, 0xDF, 0xB4, 0x47, 0xC4, 0x88,
+	0xFE, 0x15, 0xFC, 0x1C, 0xD0, 0x66, 0x92, 0xD7, 0x52, 0x6F, 0x2A, 0xEB, 0x52, 0x8D, 0x77, 0x2C,
+	0x31, 0xB7, 0xCA, 0xCD, 0x5F, 0xD1, 0x67, 0xEC, 0x27, 0xFB, 0x32, 0xF8, 0x3F, 0xF6, 0x33, 0xFD,
+	0x9B, 0x7C, 0x3F, 0xF0, 0x8B, 0xC3, 0x76, 0x11, 0xC7, 0x7D, 0x6F, 0x63, 0x1A, 0xEB, 0xD7, 0xCB,
+	0xFF, 0x00, 0x2F, 0xD7, 0x0B, 0xFF, 0x00, 0x2D, 0x2B, 0x89, 0xFD, 0x8D, 0x7F, 0x61, 0x5F, 0xD9,
+	0xE3, 0xF6, 0x21, 0xF0, 0x6A, 0x78, 0x3B, 0xE1, 0x2E, 0x9D, 0x35, 0xC3, 0xEF, 0xDC, 0xDA, 0x86,
+	0xA9, 0xB6, 0x49, 0xFF, 0x00, 0xEF, 0xAA, 0xF6, 0xE6, 0xD5, 0xBC, 0xC2, 0xCF, 0xBD, 0x9A, 0xBC,
+	0xEC, 0x4D, 0x6F, 0x6D, 0xB1, 0xEC, 0x61, 0x30, 0xBE, 0xC6, 0x3A, 0x9A, 0x5E, 0x28, 0xD7, 0x36,
+	0xD9, 0x33, 0xFF, 0x00, 0xB3, 0xF7, 0xAB, 0xCE, 0xFF, 0x00, 0x68, 0xBB, 0x84, 0xB8, 0xFF, 0x00,
+	0x82, 0x71, 0x7C, 0x76, 0x98, 0x7F, 0xD0, 0x9B, 0x27, 0xFE, 0x85, 0x5B, 0x1E, 0x32, 0xF1, 0x42,
+	0x5A, 0x69, 0xAC, 0x3E, 0x55, 0xF9, 0x7E, 0xF3, 0x57, 0x23, 0xF1, 0x7E, 0xF1, 0xF5, 0x2F, 0xF8,
+	0x26, 0x67, 0xC7, 0x4D, 0x63, 0x6B, 0x35, 0xAC, 0x9E, 0x0F, 0x98, 0x47, 0x70, 0xBF, 0x75, 0x9B,
+	0x77, 0xCD, 0x5C, 0x91, 0x56, 0x94, 0x7D, 0x4F, 0x42, 0xF7, 0xA7, 0x3F, 0x43, 0xF9, 0xD3, 0xF8,
+	0x1D, 0xBB, 0xFB, 0x0A, 0xF7, 0x6F, 0xFC, 0xFF, 0x00, 0x35, 0x15, 0x27, 0xC0, 0x78, 0xA6, 0x97,
+	0xC3, 0xF7, 0xED, 0x03, 0x46, 0x17, 0xFB, 0x4A, 0x4F, 0xBD, 0x45, 0x7D, 0x44, 0x7E, 0x14, 0x7C,
+	0xD4, 0x76, 0x3E, 0x96, 0xFF, 0x00, 0x82, 0x25, 0xB4, 0x3F, 0xF0, 0xF8, 0xBF, 0x87, 0x7E, 0x4C,
+	0xCD, 0xFF, 0x00, 0x21, 0x4D, 0xAB, 0xFF, 0x00, 0x7E, 0xEB, 0xF5, 0xFB, 0xF6, 0xBD, 0xF8, 0x61,
+	0xAE, 0x7E, 0xCE, 0x5F, 0x1A, 0xEE, 0x3C, 0x51, 0x60, 0xD3, 0x49, 0xE1, 0xED, 0x6A, 0xE1, 0xA7,
+	0x5B, 0xC6, 0xFB, 0xCB, 0x71, 0x23, 0x6E, 0x65, 0xFF, 0x00, 0x80, 0xD7, 0xE3, 0xDF, 0xFC, 0x11,
+	0xC6, 0xF6, 0x2F, 0x0A, 0xFF, 0x00, 0xC1, 0x65, 0x7E, 0x18, 0xD8, 0xEB, 0x43, 0xEC, 0xFA, 0x95,
+	0xF6, 0xB3, 0xE5, 0xC7, 0x63, 0x27, 0xCA, 0xFF, 0x00, 0xEA, 0xEB, 0xFA, 0x09, 0xFD, 0xB3, 0x74,
+	0xBB, 0xAF, 0x88, 0xBE, 0x03, 0xD5, 0x3C, 0x1D, 0x37, 0x86, 0xE4, 0x92, 0xE5, 0x5A, 0x4F, 0xB1,
+	0x5C, 0x6D, 0xF9, 0x61, 0x6F, 0xE1, 0x6A, 0xF9, 0xDC, 0x44, 0x7F, 0x79, 0x76, 0x7A, 0xF8, 0x25,
+	0xCB, 0x4E, 0xC7, 0x82, 0x78, 0x27, 0xE2, 0xA6, 0x8B, 0xA9, 0x5A, 0xC6, 0xEF, 0xA9, 0x6F, 0x66,
+	0x5F, 0x9B, 0x75, 0x74, 0x6B, 0xE2, 0xAD, 0x36, 0x4D, 0xCF, 0x6D, 0x7E, 0xAD, 0xB7, 0xF8, 0x7F,
+	0xBB, 0x5F, 0x1F, 0xEA, 0x1A, 0x5F, 0xC6, 0x0F, 0x85, 0x37, 0x4D, 0xA5, 0x5E, 0x78, 0x5E, 0xFA,
+	0xE6, 0x35, 0x7F, 0xF8, 0xFA, 0x8D, 0x7E, 0x5A, 0x82, 0xEB, 0xE3, 0xE6, 0xAB, 0xA1, 0xB2, 0xA6,
+	0xAB, 0x73, 0x24, 0x7F, 0xDE, 0x66, 0xFE, 0x1A, 0xE7, 0x9C, 0xA4, 0x9A, 0x92, 0x3B, 0x97, 0x2C,
+	0xA3, 0xCA, 0xCF, 0xA8, 0x3E, 0x30, 0x7C, 0x3F, 0xF8, 0x33, 0xF1, 0xFB, 0xC2, 0x72, 0x78, 0x27,
+	0xE2, 0xEF, 0x86, 0x2C, 0xF5, 0xBD, 0x3F, 0xCA, 0x65, 0x8A, 0x1B, 0xC5, 0xF9, 0x57, 0x75, 0x7E,
+	0x74, 0x7C, 0x2D, 0xFF, 0x00, 0x82, 0x3E, 0xF8, 0xFF, 0x00, 0xF6, 0x39, 0xFD, 0xB4, 0xBC, 0x3D,
+	0xF1, 0x3B, 0xF6, 0x7E, 0xF1, 0x24, 0x9E, 0x2A, 0xF0, 0x6C, 0x9E, 0x20, 0x5B, 0xAD, 0x51, 0x6F,
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+	0x93, 0xFF, 0x00, 0x42, 0xAC, 0x63, 0x19, 0x53, 0x92, 0x5D, 0x6F, 0x66, 0x69, 0x2E, 0x5A, 0x94,
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+	0xE1, 0xEB, 0x83, 0xFF, 0x00, 0x31, 0x4F, 0xFD, 0xA7, 0x5F, 0xD0, 0xB6, 0x8E, 0xBF, 0xF1, 0x58,
+	0x6A, 0xBF, 0xF6, 0x16, 0x9B, 0xFF, 0x00, 0x42, 0xAF, 0xE7, 0xA7, 0xFE, 0x08, 0x95, 0xF3, 0x7F,
+	0xC1, 0x63, 0xFE, 0x1D, 0xE7, 0xFE, 0x82, 0x9F, 0xFB, 0x4D, 0xAB, 0xFA, 0x18, 0xD1, 0xFF, 0x00,
+	0xE4, 0x73, 0xD4, 0xFF, 0x00, 0xEC, 0x2D, 0x37, 0xFE, 0x85, 0x5E, 0x16, 0x36, 0x52, 0xF6, 0xD3,
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+	0xEF, 0x8A, 0xD7, 0x3F, 0x0F, 0xBF, 0x6C, 0xCF, 0x86, 0xBF, 0xDA, 0xBA, 0xAE, 0xA1, 0xFF, 0x00,
+	0x08, 0xF6, 0x97, 0x67, 0x6F, 0xAA, 0x6A, 0x5A, 0x4D, 0xBC, 0xBF, 0xBB, 0x93, 0xCB, 0x93, 0x73,
+	0x48, 0xB1, 0xFF, 0x00, 0xCF, 0x4D, 0xB5, 0x4B, 0xE2, 0x3F, 0xED, 0xD1, 0xFB, 0x6C, 0x7F, 0xC1,
+	0x4A, 0xB5, 0x3D, 0x4F, 0xE0, 0x57, 0xEC, 0xBB, 0xE0, 0xCD, 0x43, 0x44, 0xF0, 0x9E, 0xB5, 0x71,
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+	0xBB, 0xAB, 0xEA, 0x4F, 0xDB, 0xB3, 0xFE, 0x09, 0x85, 0xA0, 0xFE, 0xDC, 0x5F, 0x12, 0xB4, 0xAF,
+	0x89, 0xDA, 0xAF, 0xC5, 0x4B, 0x8D, 0x0E, 0xE3, 0x4B, 0xD3, 0x7E, 0xC4, 0xB6, 0xB0, 0xDB, 0xF9,
+	0x8A, 0xD1, 0xFF, 0x00, 0x7A, 0xBC, 0x7F, 0xC6, 0x1F, 0xF0, 0x4E, 0xDF, 0xDB, 0x93, 0xF6, 0x5F,
+	0xF0, 0x1A, 0xD9, 0xFE, 0xC5, 0x5F, 0xB5, 0x16, 0xAD, 0xA9, 0x32, 0xDD, 0x43, 0x2D, 0xC6, 0x8A,
+	0xB6, 0xB1, 0xC2, 0xB2, 0x2A, 0xB7, 0xCD, 0x1E, 0xE6, 0xFE, 0xF2, 0xD7, 0xD0, 0x51, 0x9E, 0x16,
+	0xA6, 0x16, 0x94, 0x54, 0x92, 0xA8, 0xBB, 0xED, 0xF3, 0x3C, 0xCC, 0x5A, 0xAF, 0xCC, 0xD5, 0x9B,
+	0xA7, 0xE5, 0xB9, 0x3F, 0xC3, 0xBF, 0xF8, 0x22, 0xA5, 0xE7, 0xC4, 0xEF, 0x86, 0x36, 0x96, 0x1F,
+	0xB7, 0x0F, 0xC7, 0x2F, 0x14, 0x6B, 0x1E, 0x22, 0x85, 0x59, 0xE5, 0xB7, 0xD3, 0xF5, 0x66, 0x96,
+	0xD2, 0x3D, 0xBF, 0x37, 0xCB, 0xBA, 0xAC, 0x59, 0xFC, 0x01, 0xF8, 0x39, 0xE1, 0x3F, 0xD9, 0x67,
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+	0xAA, 0xAC, 0x8C, 0xD6, 0xED, 0xB5, 0x99, 0xB6, 0xFF, 0x00, 0x15, 0x7D, 0x95, 0xF0, 0x37, 0xC5,
+	0x5F, 0x13, 0x3C, 0x55, 0xF0, 0x9E, 0xC7, 0x5E, 0xF8, 0xBB, 0xE0, 0x18, 0xFC, 0x33, 0xE2, 0x46,
+	0xB1, 0x91, 0x35, 0x4D, 0x1E, 0x3B, 0x8F, 0x31, 0x63, 0x65, 0x8D, 0x97, 0x76, 0xEF, 0xF6, 0xBE,
+	0xF5, 0x7C, 0x7B, 0xFB, 0x13, 0xF8, 0x17, 0xC5, 0xBF, 0x16, 0xBF, 0xE0, 0x97, 0x5F, 0x16, 0xFE,
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+	0x46, 0x99, 0xB6, 0xAE, 0xEA, 0xF3, 0xE5, 0x8C, 0xC4, 0x4A, 0x6E, 0x55, 0x5A, 0xF8, 0xDD, 0xED,
+	0x6B, 0x6E, 0xF6, 0xB1, 0xD3, 0x1C, 0x35, 0x18, 0xD1, 0x51, 0xA5, 0x7D, 0x52, 0x7A, 0xEF, 0xF3,
+	0x3E, 0xA3, 0xFD, 0x91, 0xED, 0x93, 0xFE, 0x19, 0x4F, 0xE1, 0xCF, 0x94, 0xF2, 0x2C, 0x6B, 0xE1,
+	0x2B, 0x5F, 0x2B, 0x77, 0xF7, 0x7C, 0xBA, 0xF4, 0x36, 0x85, 0x24, 0x54, 0x7C, 0xFC, 0xFF, 0x00,
+	0xDD, 0x8F, 0xEE, 0xB5, 0x7C, 0xDF, 0xFF, 0x00, 0x04, 0xFC, 0xFD, 0xA9, 0xFC, 0x25, 0xE2, 0xEF,
+	0x03, 0x69, 0xBF, 0xB2, 0xF7, 0x8C, 0x51, 0x74, 0x7F, 0x1C, 0xF8, 0x1F, 0x4B, 0x5B, 0x0D, 0x43,
+	0x4B, 0xBA, 0xF9, 0x23, 0x91, 0x61, 0x5D, 0xAD, 0x26, 0xF6, 0xF9, 0x6B, 0xE8, 0x8D, 0x43, 0x5C,
+	0xF0, 0xC6, 0x93, 0xA7, 0xCD, 0xAA, 0xDF, 0xF8, 0x93, 0x4F, 0xB7, 0xB7, 0xB5, 0x89, 0xA5, 0xB8,
+	0x9A, 0x3B, 0xC8, 0xD9, 0xA3, 0x8D, 0x7E, 0x66, 0xF9, 0x77, 0x57, 0x0E, 0x22, 0x9D, 0x68, 0xE2,
+	0xA6, 0xD2, 0x4D, 0x33, 0xB2, 0x85, 0x4A, 0x32, 0xA7, 0x18, 0xC9, 0xEA, 0x8F, 0x99, 0x3F, 0x6D,
+	0x3B, 0x56, 0xBC, 0xFD, 0xBC, 0x3F, 0x66, 0xF7, 0x98, 0x7C, 0xB1, 0xDC, 0x6A, 0x8A, 0xAC, 0xDF,
+	0x7A, 0x3D, 0xD0, 0xB7, 0xDD, 0xAF, 0x9F, 0xBE, 0x06, 0xFF, 0x00, 0xC1, 0x33, 0x7F, 0x67, 0x0F,
+	0xDA, 0x63, 0xC5, 0x5E, 0x24, 0xF0, 0x67, 0xC4, 0x1D, 0x57, 0x58, 0xB3, 0xBC, 0xD2, 0xFC, 0x43,
+	0x79, 0xA8, 0xAD, 0xF6, 0x9A, 0xCA, 0xB2, 0xC9, 0xE6, 0x4C, 0xDF, 0x2B, 0x37, 0xF7, 0x6B, 0xBE,
+	0xF0, 0x0F, 0xED, 0x03, 0xFF, 0x00, 0x0F, 0x18, 0xFF, 0x00, 0x82, 0x82, 0x69, 0x5E, 0x24, 0xF8,
+	0x45, 0xE1, 0xBB, 0x85, 0xF0, 0x5F, 0xC0, 0xD9, 0xA6, 0x76, 0xF1, 0x04, 0xD1, 0xB4, 0x4D, 0xAB,
+	0x79, 0xD1, 0xB2, 0xB7, 0xCA, 0xDF, 0xDD, 0x6A, 0xF5, 0x0F, 0xD8, 0x63, 0x4F, 0x92, 0xF3, 0xE2,
+	0xB7, 0x8D, 0x3C, 0x67, 0x0D, 0xB6, 0xCB, 0x7B, 0x8B, 0x89, 0xA2, 0x89, 0x57, 0xEE, 0xEE, 0x59,
+	0x2B, 0xBA, 0x95, 0x6F, 0xAB, 0xE5, 0xD2, 0x70, 0xE8, 0xBD, 0xEF, 0xEB, 0xD0, 0xE6, 0xA9, 0x0E,
+	0x6C, 0x72, 0x55, 0x3E, 0x19, 0x6C, 0x7C, 0xD7, 0xFB, 0x40, 0x7F, 0xC1, 0x36, 0x7F, 0x6D, 0x8F,
+	0x81, 0x7E, 0x34, 0xB3, 0xF8, 0x8B, 0xFB, 0x2E, 0xFC, 0x69, 0xD6, 0xB5, 0x8F, 0x06, 0x78, 0x56,
+	0x25, 0xBD, 0x5D, 0x1F, 0x52, 0xD5, 0x24, 0x96, 0x7B, 0x89, 0x23, 0xF9, 0xBC, 0x9F, 0x2D, 0x7E,
+	0xF2, 0xFF, 0x00, 0xB3, 0x5E, 0x57, 0xFB, 0x51, 0xFF, 0x00, 0xC1, 0x53, 0xFE, 0x24, 0x7C, 0x7F,
+	0xFD, 0x95, 0x3C, 0x41, 0xFB, 0x3F, 0xFE, 0xD0, 0xFF, 0x00, 0x0D, 0xEF, 0xBC, 0x3D, 0xE3, 0x6B,
+	0xAD, 0x6E, 0xDE, 0xEF, 0xC3, 0xAB, 0x67, 0x60, 0xD0, 0x45, 0x1D, 0xBC, 0x3F, 0x7B, 0xCC, 0xDD,
+	0xF7, 0x64, 0xAF, 0xB9, 0xBF, 0x6F, 0xC5, 0xFD, 0xBE, 0x7C, 0x6D, 0xA9, 0x68, 0x9F, 0x0C, 0x7F,
+	0x63, 0xFD, 0x1E, 0x4D, 0x13, 0x4B, 0x6B, 0xC8, 0x6E, 0xB5, 0x6F, 0x1E, 0x5A, 0xDC, 0x2F, 0x9B,
+	0x1A, 0xFF, 0x00, 0xCB, 0x4B, 0x7F, 0x2D, 0xBF, 0x86, 0xBC, 0x97, 0xC6, 0x9F, 0xF0, 0x44, 0xDF,
+	0x12, 0x7C, 0x66, 0xBA, 0x4F, 0x16, 0xFC, 0x60, 0xFD, 0xAD, 0x35, 0x2B, 0xFD, 0x62, 0xEA, 0x2D,
+	0xD7, 0x52, 0x49, 0xA6, 0xAE, 0xE5, 0x66, 0xFB, 0xD5, 0xD9, 0x83, 0xAD, 0x4D, 0x46, 0x95, 0x7C,
+	0x43, 0x5A, 0x3D, 0x12, 0xDF, 0xE6, 0x70, 0x62, 0x28, 0xFB, 0x29, 0x54, 0xA1, 0x85, 0x4E, 0xEF,
+	0x76, 0xF6, 0xB7, 0x91, 0xED, 0xDF, 0xF0, 0x4E, 0x5D, 0x6F, 0x52, 0xF1, 0x77, 0xEC, 0x07, 0xE0,
+	0x9F, 0x13, 0xEB, 0x9A, 0xC5, 0xD5, 0xFD, 0xF5, 0xC5, 0xAC, 0x9F, 0x68, 0xBA, 0xBC, 0x97, 0xCC,
+	0x95, 0xB6, 0xB7, 0xF1, 0x35, 0x57, 0xFD, 0xAE, 0xE3, 0xDB, 0xFB, 0x01, 0x7C, 0x78, 0xFF, 0x00,
+	0xB1, 0x2D, 0xBF, 0xF4, 0x2A, 0xF4, 0x3F, 0xD9, 0xF7, 0xE0, 0x1D, 0x87, 0xEC, 0xC3, 0xFB, 0x3D,
+	0xE8, 0xFF, 0x00, 0x03, 0x74, 0x7F, 0x12, 0x49, 0xAC, 0x43, 0xA1, 0xC4, 0xCB, 0xFD, 0xA5, 0x22,
+	0xED, 0x69, 0xB7, 0x36, 0xEF, 0xBB, 0x5E, 0x7D, 0xFB, 0x5E, 0xFF, 0x00, 0xC9, 0x81, 0xFC, 0x79,
+	0xFF, 0x00, 0xB1, 0x2D, 0xBF, 0xF4, 0x23, 0x5E, 0x0E, 0x32, 0x5E, 0xD3, 0x30, 0x9D, 0x4F, 0xE6,
+	0x95, 0xFF, 0x00, 0x23, 0xDB, 0xC3, 0x2E, 0x5C, 0x17, 0x2B, 0xE9, 0x13, 0xF9, 0xAB, 0xF8, 0x06,
+	0x31, 0xE1, 0xEB, 0xF0, 0x3F, 0xE8, 0x25, 0x25, 0x14, 0xEF, 0x80, 0xBF, 0xF2, 0x00, 0xD4, 0x3F,
+	0xEC, 0x25, 0x25, 0x15, 0xF4, 0x11, 0xF8, 0x51, 0xE0, 0xC7, 0x63, 0xE9, 0x6F, 0xF8, 0x22, 0x6B,
+	0x1F, 0xF8, 0x7C, 0x87, 0xC3, 0xBC, 0xFF, 0x00, 0xD0, 0x53, 0xFF, 0x00, 0x69, 0xB5, 0x7F, 0x42,
+	0x1A, 0x6D, 0xC7, 0x97, 0xE3, 0x2D, 0x50, 0x6F, 0xFF, 0x00, 0x98, 0xB4, 0xDF, 0xFA, 0x15, 0x7F,
+	0x3D, 0xFF, 0x00, 0xF0, 0x44, 0xBF, 0xF9, 0x4C, 0x8F, 0xC3, 0xBF, 0xFB, 0x0A, 0x7F, 0xED, 0x36,
+	0xAF, 0xDF, 0x88, 0x75, 0x5D, 0xBE, 0x3C, 0xD5, 0x90, 0xFF, 0x00, 0xD0, 0x5A, 0x6F, 0xFD, 0x19,
+	0x5E, 0x0E, 0x2A, 0xA4, 0xA5, 0x53, 0x9B, 0x63, 0xD7, 0xCB, 0x65, 0xFB, 0x9B, 0xBD, 0x4F, 0x48,
+	0x6B, 0xD4, 0xF9, 0x51, 0x1F, 0x6B, 0xFF, 0x00, 0x7A, 0x9D, 0xFD, 0xA0, 0x88, 0xC7, 0x63, 0xED,
+	0xDD, 0xFD, 0xDA, 0xE7, 0xBF, 0xB4, 0xB7, 0x2F, 0xDF, 0xA5, 0xFE, 0xD1, 0x1E, 0xB5, 0xC3, 0x18,
+	0x47, 0x95, 0xC5, 0xEB, 0x73, 0xBE, 0x32, 0xB3, 0xE7, 0x47, 0x46, 0xBA, 0x97, 0x9D, 0x1D, 0xC4,
+	0xD3, 0x7C, 0xCD, 0xF6, 0x79, 0x3F, 0xF4, 0x16, 0xAF, 0x98, 0x3F, 0xE0, 0x91, 0x7A, 0x82, 0x2F,
+	0xEC, 0xC3, 0xE2, 0x24, 0x47, 0x5D, 0xAB, 0xF1, 0x23, 0x56, 0x65, 0x65, 0xFF, 0x00, 0xAE, 0xCD,
+	0x5E, 0xF8, 0xBA, 0x86, 0xE8, 0xE6, 0xD8, 0xFB, 0x7F, 0xD1, 0x64, 0xDD, 0xFE, 0xD7, 0xCA, 0xD5,
+	0xF3, 0x1F, 0xFC, 0x12, 0x5E, 0xF1, 0xD7, 0xF6, 0x65, 0xF1, 0x0B, 0xBA, 0x34, 0x7B, 0x7E, 0x24,
+	0x6A, 0xCD, 0xB7, 0xFD, 0x9F, 0x39, 0xAB, 0xB2, 0x8C, 0x63, 0x4B, 0x27, 0x97, 0x32, 0xFB, 0x5A,
+	0x7D, 0xE6, 0x1E, 0xD2, 0x12, 0xCC, 0x93, 0x7D, 0x56, 0xA7, 0xB4, 0x7C, 0x7E, 0xFD, 0x92, 0xFE,
+	0x00, 0xFE, 0xD2, 0x51, 0xC7, 0xFF, 0x00, 0x0B, 0x0F, 0x47, 0xBC, 0xB1, 0x9A, 0x36, 0xDD, 0xF6,
+	0xEF, 0x0E, 0xDC, 0x7D, 0x96, 0x79, 0x3F, 0xDE, 0x91, 0x7E, 0x66, 0xAF, 0x39, 0xD3, 0xFF, 0x00,
+	0xE0, 0x94, 0x3F, 0xB2, 0x1E, 0x9F, 0x32, 0x4D, 0x1E, 0xB1, 0xE3, 0x87, 0x48, 0xEE, 0x16, 0x75,
+	0x8E, 0x6F, 0x13, 0x48, 0xCA, 0xCC, 0xBF, 0x32, 0xAB, 0x7C, 0xDF, 0x76, 0xB7, 0x3F, 0x68, 0x4F,
+	0xDB, 0xC3, 0xE0, 0xB7, 0xEC, 0xC3, 0xE2, 0xCB, 0x6F, 0x0B, 0x7C, 0x45, 0xF0, 0xDF, 0x8A, 0xAF,
+	0xAF, 0x2F, 0x2C, 0xFE, 0xD1, 0x13, 0x68, 0x7A, 0x1C, 0x97, 0x11, 0x2A, 0xFF, 0x00, 0xB4, 0xCB,
+	0xFC, 0x54, 0xCF, 0xD9, 0xF7, 0xF6, 0xEE, 0xF8, 0x39, 0xFB, 0x4D, 0x6B, 0x53, 0x78, 0x6F, 0xE1,
+	0xD7, 0x87, 0xBC, 0x55, 0x6B, 0x71, 0x1B, 0x7E, 0xF6, 0x4D, 0x73, 0x46, 0x92, 0xDA, 0x3F, 0xFB,
+	0xE9, 0xAB, 0x48, 0x43, 0x19, 0xEC, 0xF9, 0xD3, 0xD2, 0xC6, 0x51, 0x95, 0x05, 0x5E, 0x51, 0xB7,
+	0xCC, 0xF7, 0x3F, 0x0F, 0xE9, 0xDE, 0x15, 0xF0, 0xDE, 0x99, 0x71, 0x0F, 0x87, 0x3C, 0x31, 0xA6,
+	0xE9, 0xAC, 0xB6, 0x12, 0x23, 0x36, 0x9F, 0x66, 0xB1, 0x79, 0xDB, 0x63, 0x6D, 0xBB, 0xB6, 0xFD,
+	0xEA, 0xF9, 0xEB, 0xFE, 0x09, 0x4B, 0xE2, 0x07, 0xD4, 0x3F, 0x66, 0xDD, 0x5A, 0xE6, 0xF6, 0xE6,
+	0x39, 0x2F, 0x1B, 0xC7, 0x9A, 0xA2, 0xCA, 0xDF, 0xC5, 0xE5, 0xF9, 0xCD, 0xB6, 0xBD, 0xD6, 0x5D,
+	0x41, 0x24, 0xB7, 0xB9, 0x48, 0x7E, 0x55, 0x5B, 0x39, 0xB6, 0xFF, 0x00, 0xDF, 0xB6, 0xAF, 0x8F,
+	0x7F, 0xE0, 0x8E, 0x7A, 0x95, 0xFC, 0x7F, 0x06, 0x7C, 0x4D, 0x6D, 0xA9, 0x5C, 0xB7, 0x9C, 0xBE,
+	0x37, 0xD5, 0x19, 0x61, 0x66, 0xF9, 0xB6, 0xF9, 0xCD, 0xFC, 0x35, 0x58, 0x5E, 0x6A, 0x98, 0x1C,
+	0x44, 0xDE, 0xEA, 0xDF, 0x3D, 0x88, 0xAF, 0x1B, 0x56, 0xA5, 0x04, 0xEF, 0xBD, 0x9F, 0x6D, 0x4F,
+	0xB7, 0x57, 0x58, 0x78, 0x77, 0x43, 0xBD, 0x99, 0x77, 0x7F, 0x0B, 0x7C, 0xB4, 0xF8, 0x6F, 0x9F,
+	0x73, 0xA2, 0x4C, 0xBB, 0x64, 0xF9, 0xBE, 0x6F, 0xE1, 0xAE, 0x75, 0xB5, 0x24, 0x12, 0xEC, 0xDF,
+	0xFE, 0xD5, 0x11, 0xEA, 0x9B, 0xB7, 0x7E, 0xF3, 0xF8, 0xAB, 0xCC, 0x6A, 0x3E, 0xC6, 0x0D, 0x2B,
+	0x5C, 0xF4, 0x25, 0x2B, 0x54, 0xB3, 0x34, 0xFC, 0x4D, 0x74, 0x9F, 0xD9, 0xFE, 0x5A, 0x3E, 0xD5,
+	0x55, 0xFF, 0x00, 0xBE, 0xAB, 0xC1, 0x3F, 0x6B, 0x69, 0x84, 0x9F, 0xB0, 0x0F, 0xC7, 0xAD, 0x9F,
+	0x37, 0xFC, 0x51, 0xAD, 0xFF, 0x00, 0xA1, 0x57, 0xAD, 0xF8, 0x9B, 0x54, 0xDB, 0xA6, 0xF0, 0xFF,
+	0x00, 0xC3, 0x5E, 0x31, 0xFB, 0x4F, 0xCA, 0xF2, 0xFF, 0x00, 0xC1, 0x3D, 0x7E, 0x3D, 0x4D, 0xFF,
+	0x00, 0x52, 0x6C, 0x9F, 0xFA, 0x15, 0x69, 0x14, 0xE3, 0xCB, 0x77, 0x7D, 0x4C, 0xFE, 0xCD, 0x4F,
+	0x43, 0xF9, 0xBC, 0xF8, 0x09, 0xFF, 0x00, 0x22, 0xFD, 0xFF, 0x00, 0xFD, 0x84, 0xA4, 0xA2, 0x93,
+	0xE0, 0x33, 0x11, 0xE1, 0xFB, 0xFC, 0x7F, 0xD0, 0x4A, 0x4A, 0x2B, 0xEA, 0x63, 0xF0, 0xA3, 0xE7,
+	0x23, 0xB1, 0xF4, 0xC7, 0xFC, 0x11, 0x37, 0xE5, 0xFF, 0x00, 0x82, 0xC9, 0x7C, 0x3B, 0xFF, 0x00,
+	0xB0, 0xA7, 0xFE, 0xD3, 0x6A, 0xFD, 0xD4, 0x5D, 0x60, 0xC7, 0xF1, 0x03, 0x5A, 0x3F, 0xF5, 0x19,
+	0xB8, 0xFF, 0x00, 0xD1, 0x8D, 0x5F, 0x85, 0xBF, 0xF0, 0x44, 0x8C, 0xC9, 0xFF, 0x00, 0x05, 0x8F,
+	0xF8, 0x7B, 0xB8, 0x63, 0x6E, 0xA9, 0xFF, 0x00, 0xB4, 0xDA, 0xBF, 0x67, 0x1B, 0xC6, 0xD0, 0xB7,
+	0xC4, 0xED, 0x72, 0xD9, 0x26, 0x56, 0xDB, 0xAF, 0x5C, 0x2F, 0xFE, 0x44, 0x6A, 0xF9, 0xEC, 0x47,
+	0xC4, 0x7A, 0xB9, 0x76, 0xB8, 0x73, 0xD8, 0x3F, 0xB6, 0x38, 0xFB, 0xF4, 0x7F, 0x6B, 0xFF, 0x00,
+	0xD3, 0x4A, 0xE5, 0xE3, 0xD6, 0x0E, 0xDF, 0xDD, 0xBE, 0xEA, 0x71, 0xD6, 0xB7, 0x7F, 0x1D, 0x73,
+	0x1D, 0xCB, 0xE1, 0x67, 0x50, 0xBA, 0xE6, 0xE5, 0x74, 0x4F, 0xE1, 0xB7, 0x93, 0xFF, 0x00, 0x41,
+	0x6A, 0xF0, 0x5F, 0xF8, 0x27, 0x5B, 0x6A, 0x5A, 0x2F, 0xC0, 0x3D, 0x6E, 0x1B, 0xCB, 0x3F, 0x2D,
+	0xA4, 0xF1, 0xBE, 0xA4, 0xDB, 0x7F, 0xD9, 0xF3, 0x2B, 0xD4, 0xE3, 0xD6, 0x11, 0x63, 0x99, 0xFC,
+	0xE5, 0xDD, 0xF6, 0x79, 0x3C, 0xAF, 0xF6, 0x7E, 0x56, 0xFB, 0xD5, 0xE0, 0x3F, 0xF0, 0x4E, 0x0D,
+	0x72, 0x6F, 0xF8, 0x50, 0x7A, 0xDC, 0x37, 0x97, 0x32, 0x3B, 0xB7, 0x8E, 0xB5, 0x2F, 0xDE, 0x48,
+	0xDB, 0xBF, 0xE5, 0xA5, 0x74, 0x47, 0x9A, 0xA6, 0x07, 0x92, 0x5B, 0x5E, 0xE6, 0x7E, 0xCE, 0x9F,
+	0xD6, 0x94, 0xBC, 0x8F, 0x4E, 0xFD, 0xA0, 0x3E, 0x19, 0xFE, 0xD2, 0xDF, 0x12, 0x3C, 0x5D, 0x6B,
+	0xAD, 0xFC, 0x16, 0xFD, 0xA1, 0x2C, 0x7C, 0x25, 0xA4, 0xC7, 0x61, 0xE4, 0x5C, 0x69, 0x37, 0x5A,
+	0x4C, 0x77, 0x2D, 0x24, 0xDF, 0xF3, 0xD3, 0x73, 0x57, 0x37, 0xF0, 0xD3, 0xE0, 0x5F, 0xED, 0x9F,
+	0xE1, 0x3F, 0x19, 0x5A, 0xEB, 0xDE, 0x3F, 0xFD, 0xAD, 0xF4, 0xFD, 0x6B, 0x44, 0x85, 0x59, 0x6E,
+	0xB4, 0x9B, 0x7D, 0x0E, 0x38, 0x9A, 0x66, 0xFF, 0x00, 0x79, 0x6B, 0xD6, 0xD7, 0x54, 0x0B, 0x1A,
+	0x87, 0x75, 0xFF, 0x00, 0x66, 0x89, 0xF5, 0x8F, 0xDC, 0xFD, 0xFA, 0xA5, 0x8E, 0xAD, 0x4E, 0x0E,
+	0x9F, 0x41, 0xCA, 0x8D, 0x35, 0x51, 0xCC, 0xDD, 0x5D, 0x5B, 0x6D, 0xBB, 0x42, 0xEF, 0xB9, 0x1A,
+	0x1D, 0x8C, 0xDF, 0xDE, 0xF9, 0x6B, 0xE5, 0xDF, 0xD9, 0x5F, 0x4D, 0x4F, 0x85, 0x1F, 0xB7, 0xE7,
+	0xC4, 0x9F, 0x83, 0x9A, 0x54, 0xDF, 0xF1, 0x27, 0x87, 0xC3, 0x30, 0xEA, 0x51, 0x46, 0xBF, 0x77,
+	0xCE, 0x99, 0xB7, 0x35, 0x7B, 0xE7, 0xF6, 0xB2, 0x79, 0x6D, 0xB1, 0xFE, 0x5F, 0xEE, 0xD7, 0x84,
+	0x78, 0x0F, 0x55, 0xD1, 0xE3, 0xFF, 0x00, 0x82, 0x94, 0x7C, 0x40, 0xB9, 0x85, 0xD9, 0xAE, 0x1B,
+	0xC1, 0x16, 0x6B, 0x34, 0x9F, 0xC3, 0xFF, 0x00, 0x01, 0xAD, 0xF0, 0x72, 0xB6, 0x06, 0xB2, 0xEF,
+	0x62, 0x6B, 0xD3, 0x5F, 0x58, 0xA6, 0xD1, 0xF4, 0xD4, 0x9A, 0xA3, 0xCB, 0x27, 0xDF, 0xF9, 0xA8,
+	0x8F, 0x52, 0xDA, 0x1B, 0xE7, 0xAE, 0x75, 0x75, 0x7F, 0xF9, 0x69, 0x33, 0xFC, 0xDF, 0xC3, 0xB7,
+	0xFB, 0xB4, 0xDF, 0xED, 0x64, 0x67, 0x6D, 0x8F, 0x5E, 0x6B, 0xF8, 0x63, 0x13, 0x57, 0xFC, 0xDE,
+	0x66, 0xAF, 0x8A, 0x35, 0xCD, 0xB6, 0x2D, 0xFE, 0xCA, 0xD7, 0x9D, 0x7E, 0xD1, 0x77, 0x09, 0x71,
+	0xFF, 0x00, 0x04, 0xE2, 0xF8, 0xED, 0x30, 0xFF, 0x00, 0xA1, 0x36, 0x4F, 0xFD, 0x0A, 0xB6, 0x3C,
+	0x65, 0xE2, 0x84, 0xB4, 0xD3, 0x58, 0x7C, 0xAB, 0xF2, 0xFD, 0xE6, 0xAE, 0x47, 0xE2, 0xFD, 0xE3,
+	0xEA, 0x5F, 0xF0, 0x4C, 0xCF, 0x8E, 0x9A, 0xC6, 0xD6, 0x6B, 0x59, 0x3C, 0x1F, 0x30, 0x8E, 0xE1,
+	0x7E, 0xEB, 0x36, 0xEF, 0x9A, 0xAD, 0x7C, 0x51, 0xF5, 0x2A, 0x5F, 0x0C, 0xFD, 0x0F, 0xE7, 0x4F,
+	0xE0, 0x76, 0xEF, 0xEC, 0x2B, 0xDD, 0xBF, 0xF3, 0xFC, 0xD4, 0x54, 0x9F, 0x01, 0xE2, 0x9A, 0x5F,
+	0x0F, 0xDF, 0xB4, 0x0D, 0x18, 0x5F, 0xED, 0x29, 0x3E, 0xF5, 0x15, 0xF5, 0x11, 0xF8, 0x51, 0xF3,
+	0x51, 0xD8, 0xFA, 0x5B, 0xFE, 0x08, 0x99, 0x22, 0x2F, 0xFC, 0x16, 0x37, 0xE1, 0xDE, 0xC5, 0xDC,
+	0xBF, 0xDA, 0xDB, 0x77, 0x7F, 0xDB, 0x3A, 0xFD, 0x7F, 0xFD, 0xAF, 0xBE, 0x18, 0xEB, 0x7F, 0xB3,
+	0xB7, 0xC6, 0xDB, 0x8F, 0x14, 0x58, 0x47, 0x24, 0xDE, 0x1D, 0xD6, 0xAE, 0x9A, 0x75, 0xBA, 0x6F,
+	0xBC, 0xB7, 0x12, 0x36, 0xE6, 0x8F, 0xFE, 0x03, 0x5F, 0x8F, 0x5F, 0xF0, 0x47, 0x3B, 0xB8, 0xBC,
+	0x31, 0xFF, 0x00, 0x05, 0x95, 0xF8, 0x63, 0x63, 0xAD, 0xB7, 0xD9, 0xF5, 0x1B, 0xED, 0x6B, 0x6D,
+	0xBD, 0x8C, 0x9F, 0x2B, 0xEE, 0xF2, 0xEB, 0xFA, 0x0A, 0xFD, 0xB3, 0xB4, 0xCB, 0x9F, 0x88, 0x9E,
+	0x00, 0xD5, 0x7C, 0x20, 0xFE, 0x1B, 0x92, 0x4B, 0x95, 0x69, 0x3E, 0xC7, 0x71, 0xB7, 0xFD, 0x4B,
+	0x7F, 0x0B, 0x57, 0xCF, 0xE2, 0x57, 0xBC, 0x7A, 0xF8, 0x05, 0xCB, 0x46, 0xCC, 0xF0, 0x7F, 0x06,
+	0x7C, 0x52, 0xD1, 0xF5, 0x4B, 0x54, 0xDF, 0xA8, 0x2F, 0xDD, 0xAD, 0xF5, 0xF1, 0x5E, 0x94, 0xCD,
+	0xF2, 0x5E, 0x2E, 0xDA, 0xF8, 0xFB, 0x50, 0xD2, 0x7E, 0x30, 0x7C, 0x29, 0xBC, 0x6D, 0x3A, 0xF3,
+	0xC3, 0x17, 0xD7, 0x28, 0xBF, 0x2F, 0xDA, 0xA3, 0x5F, 0x96, 0xA2, 0xBA, 0xF8, 0xFD, 0xAC, 0x68,
+	0x6C, 0xB1, 0xEA, 0xB7, 0x32, 0x47, 0xFD, 0xE6, 0x6F, 0xE1, 0xAE, 0x59, 0x7B, 0xA7, 0x6C, 0x75,
+	0xD0, 0xFB, 0x1F, 0xFE, 0x12, 0xAD, 0x36, 0x3D, 0xC8, 0xAE, 0xA5, 0x66, 0x56, 0x56, 0x6D, 0xDF,
+	0xDE, 0x5D, 0xB5, 0xC2, 0xFE, 0xCF, 0x7F, 0x0C, 0xF4, 0x1F, 0xD9, 0xF7, 0xC0, 0xB7, 0x9E, 0x03,
+	0xB0, 0xF1, 0x84, 0x9A, 0xB4, 0x77, 0x5A, 0xE5, 0xC6, 0xA5, 0xF6, 0xAB, 0x85, 0xDA, 0xCA, 0xD3,
+	0x36, 0xEF, 0x2F, 0xFE, 0x03, 0x5F, 0x30, 0x5D, 0x7E, 0xD7, 0x5E, 0x1B, 0xD3, 0x64, 0x6F, 0xB4,
+	0xF8, 0xC2, 0x1F, 0x97, 0xF8, 0x77, 0x35, 0x56, 0x5F, 0xDB, 0x73, 0xE1, 0xEC, 0x71, 0xEC, 0x93,
+	0xC7, 0x96, 0xA8, 0xBF, 0xED, 0x33, 0x55, 0x7B, 0x4A, 0x92, 0x8C, 0x7B, 0x10, 0xE0, 0xBD, 0xA2,
+	0x91, 0xF7, 0x3C, 0x1E, 0x2E, 0xD2, 0xBC, 0xBD, 0xAF, 0x7E, 0xB4, 0x49, 0xE2, 0xAD, 0x1D, 0x97,
+	0xFE, 0x3F, 0xD6, 0xBE, 0x18, 0x6F, 0xDB, 0x9B, 0xE1, 0x56, 0xDF, 0x93, 0xE2, 0x2D, 0x9A, 0xED,
+	0xFF, 0x00, 0x6D, 0xA9, 0xAB, 0xFB, 0x73, 0x7C, 0x31, 0x66, 0xFF, 0x00, 0x92, 0x91, 0x67, 0xFF,
+	0x00, 0x7D, 0x35, 0x1E, 0xF3, 0xBF, 0x99, 0xA4, 0xD4, 0x65, 0x4D, 0x25, 0xB9, 0xF7, 0x22, 0xF8,
+	0x93, 0x46, 0xDC, 0xAE, 0xF7, 0xFB, 0x6B, 0xCC, 0x7E, 0x1E, 0xFC, 0x13, 0xD0, 0x7C, 0x09, 0xFB,
+	0x45, 0x78, 0x9B, 0xF6, 0x83, 0x7F, 0x89, 0x17, 0x1A, 0x94, 0xDE, 0x20, 0xD2, 0x63, 0xB2, 0xFE,
+	0xCB, 0x99, 0x76, 0xC7, 0x6A, 0xAB, 0xFC, 0x4A, 0xD5, 0xF3, 0x5C, 0x9F, 0xB7, 0x17, 0xC3, 0x47,
+	0x8F, 0x6C, 0x3F, 0x11, 0x6D, 0x5B, 0xFE, 0x04, 0xD5, 0x37, 0xFC, 0x36, 0x57, 0x83, 0x2E, 0xA1,
+	0x5F, 0xB3, 0x78, 0xDA, 0xDD, 0x8F, 0xF0, 0xED, 0x6A, 0xD2, 0x9D, 0x4E, 0x48, 0xCA, 0x3D, 0xED,
+	0xF9, 0x0A, 0x4A, 0x32, 0x94, 0x5A, 0xE8, 0x7D, 0xB6, 0xBE, 0x28, 0xD3, 0x7F, 0xE7, 0xF1, 0x5B,
+	0x77, 0xF0, 0xEE, 0xA8, 0x6F, 0x3C, 0x6D, 0xA2, 0x69, 0xF6, 0xF2, 0x4C, 0xFA, 0x96, 0xDD, 0xBF,
+	0xDD, 0xAF, 0x8D, 0xB4, 0xFF, 0x00, 0xDA, 0x82, 0x1B, 0xE8, 0xF7, 0xD9, 0xF8, 0x92, 0x39, 0xBF,
+	0xD9, 0x5A, 0x9A, 0xF3, 0xE2, 0xB7, 0xC4, 0x8D, 0x6A, 0x15, 0x7F, 0x0D, 0xF8, 0x62, 0xFB, 0x52,
+	0x49, 0xA5, 0x54, 0x55, 0xB7, 0x5F, 0xEF, 0x7F, 0x15, 0x73, 0xFB, 0xDC, 0xF7, 0x09, 0x47, 0xF7,
+	0x7C, 0xA7, 0xAE, 0xFC, 0x5E, 0xF8, 0xE5, 0x61, 0x24, 0x2F, 0xA5, 0x69, 0xB7, 0xF7, 0x17, 0x13,
+	0x4C, 0xDB, 0x22, 0x86, 0x18, 0x99, 0x99, 0x99, 0x9B, 0x6F, 0xDD, 0xAF, 0x70, 0xF8, 0xCB, 0xF0,
+	0xE7, 0xC5, 0xFF, 0x00, 0x0B, 0xFF, 0x00, 0xE0, 0x8C, 0x9F, 0x12, 0xBC, 0x31, 0xE3, 0x8D, 0x3A,
+	0x38, 0x2F, 0x9B, 0xC2, 0xB7, 0x97, 0x46, 0xDD, 0x1F, 0x76, 0x12, 0x46, 0x56, 0x5A, 0xF2, 0xDF,
+	0xD8, 0xDF, 0xE0, 0x6F, 0x8F, 0x3C, 0x1B, 0xF1, 0x6A, 0xDB, 0xE2, 0x5F, 0x8D, 0xB4, 0x4F, 0xED,
+	0x09, 0xAD, 0x7E, 0x6D, 0x2D, 0x5A, 0xDF, 0x72, 0x43, 0xB9, 0x7E, 0x6D, 0xCB, 0xFC, 0x55, 0xF4,
+	0x8F, 0xFC, 0x14, 0x8F, 0xC4, 0xDA, 0x85, 0xC7, 0xFC, 0x13, 0x53, 0xE2, 0xFE, 0xA5, 0xE2, 0x24,
+	0xFB, 0x3A, 0xC7, 0xE1, 0x09, 0x9A, 0x69, 0x24, 0xF9, 0x56, 0x38, 0xF7, 0x2D, 0x5D, 0x3F, 0x89,
+	0x2F, 0x31, 0x54, 0x5F, 0xBB, 0x7E, 0x96, 0x3F, 0x97, 0x9F, 0x81, 0x2F, 0x14, 0x1A, 0x15, 0xF2,
+	0x5C, 0x3E, 0xC6, 0xFE, 0xD0, 0x6F, 0x94, 0x51, 0x57, 0x3F, 0x66, 0xED, 0x13, 0x5D, 0xF1, 0x1F,
+	0x84, 0xEF, 0xB5, 0x2F, 0x0F, 0xE8, 0xD3, 0xDD, 0x5B, 0xB6, 0xA5, 0x26, 0xD9, 0xA2, 0x5C, 0x86,
+	0xA2, 0xBE, 0x8D, 0x62, 0x21, 0x63, 0xC0, 0xF6, 0x53, 0x3E, 0xB0, 0xFF, 0x00, 0x82, 0xAA, 0x7E,
+	0xC8, 0xFF, 0x00, 0x1E, 0x7F, 0xE0, 0x99, 0xFF, 0x00, 0xB7, 0xA5, 0xAF, 0xED, 0x4B, 0xF0, 0xC7,
+	0x41, 0x6B, 0x83, 0x67, 0x2C, 0x32, 0xE8, 0x77, 0x96, 0xEA, 0xCD, 0xE4, 0xB2, 0xAF, 0xCC, 0xDB,
+	0x97, 0xEE, 0xD7, 0xE8, 0x67, 0xEC, 0xB1, 0xFF, 0x00, 0x07, 0x44, 0x7E, 0xC0, 0xBF, 0x11, 0x3E,
+	0x0F, 0xE9, 0xEF, 0xFB, 0x43, 0x1D, 0x53, 0x4F, 0xF1, 0x6D, 0x9D, 0xBA, 0xC1, 0xAB, 0x43, 0x1E,
+	0x95, 0xB9, 0x24, 0x91, 0x57, 0xE6, 0x6D, 0xDB, 0xAB, 0xEF, 0x0F, 0xDB, 0xAB, 0xE0, 0x67, 0xC2,
+	0xCF, 0x8B, 0x9F, 0xB3, 0xFF, 0x00, 0x88, 0xDF, 0xE2, 0x07, 0x84, 0x6D, 0xB5, 0x07, 0xB5, 0xD3,
+	0x9A, 0x48, 0x24, 0x99, 0x79, 0x56, 0xAF, 0xE7, 0x57, 0xF6, 0xF0, 0xFD, 0x90, 0x7F, 0x67, 0xFF,
+	0x00, 0x87, 0x7A, 0xC4, 0x11, 0xF8, 0x43, 0xC0, 0x90, 0xD9, 0x89, 0x6E, 0x99, 0xE4, 0xF2, 0xE4,
+	0x6E, 0x58, 0xD7, 0x89, 0x29, 0x7B, 0x4D, 0xCE, 0xF8, 0xCB, 0xD9, 0xEC, 0x7E, 0xB2, 0x6B, 0x9F,
+	0xF0, 0x70, 0x37, 0xFC, 0x11, 0xD3, 0x5C, 0xDC, 0x9A, 0xAC, 0x9A, 0xC4, 0x88, 0xDF, 0x7B, 0xFE,
+	0x24, 0xAB, 0xB7, 0xFF, 0x00, 0x42, 0xAE, 0x4F, 0x59, 0xFF, 0x00, 0x82, 0xCE, 0x7F, 0xC1, 0x0B,
+	0x7C, 0x41, 0xF2, 0xEA, 0x7A, 0x2E, 0xA6, 0xDF, 0xEE, 0xE8, 0x4B, 0xF3, 0x57, 0xE2, 0x13, 0x7C,
+	0x28, 0xF0, 0x34, 0x6D, 0xE5, 0x2E, 0x8F, 0xF2, 0xE3, 0x3F, 0xEB, 0x0D, 0x3C, 0x7C, 0x26, 0xF0,
+	0x29, 0x76, 0x43, 0xA4, 0x70, 0x3F, 0xE9, 0xA1, 0xAD, 0x63, 0x45, 0x49, 0x6E, 0x66, 0xF1, 0x52,
+	0x4E, 0xE7, 0xEC, 0xD5, 0xDF, 0xFC, 0x15, 0x33, 0xFE, 0x0D, 0xFB, 0xD4, 0x99, 0x9E, 0xEB, 0xC2,
+	0x5A, 0xA7, 0xCD, 0xFF, 0x00, 0x50, 0x15, 0xAC, 0xBB, 0xCF, 0xF8, 0x28, 0x87, 0xFC, 0x1B, 0xC1,
+	0x7D, 0xF3, 0xBF, 0x85, 0x75, 0x65, 0xFF, 0x00, 0x77, 0x41, 0x8E, 0xBF, 0x1D, 0x57, 0xE1, 0x67,
+	0x82, 0x5E, 0x35, 0xDD, 0xA4, 0x7F, 0xE4, 0x43, 0x4D, 0x4F, 0x85, 0xBE, 0x09, 0xE9, 0xFD, 0x91,
+	0xFF, 0x00, 0x91, 0x0D, 0x6D, 0x1C, 0x0C, 0x03, 0xEB, 0x52, 0x67, 0xEB, 0xF3, 0xFE, 0xDF, 0x5F,
+	0xF0, 0x6E, 0xBB, 0x70, 0x3C, 0x31, 0xAC, 0x7F, 0xE0, 0x86, 0x3A, 0x07, 0xED, 0xEB, 0xFF, 0x00,
+	0x06, 0xEB, 0xAF, 0x5F, 0x0C, 0x6B, 0x1F, 0xF8, 0x23, 0x8E, 0xBF, 0x20, 0xFF, 0x00, 0xE1, 0x55,
+	0xF8, 0x1B, 0xFE, 0x80, 0xAB, 0xFF, 0x00, 0x7F, 0x0F, 0xF8, 0xD1, 0xFF, 0x00, 0x0A, 0xAB, 0xC0,
+	0xFF, 0x00, 0xF4, 0x07, 0x1F, 0xF7, 0xF0, 0xD5, 0x7D, 0x46, 0x01, 0xF5, 0xA9, 0x9F, 0xB0, 0x96,
+	0xFF, 0x00, 0xF0, 0x50, 0x8F, 0xF8, 0x37, 0x6A, 0xC7, 0x73, 0xFF, 0x00, 0xC2, 0x2B, 0xAC, 0x36,
+	0xEF, 0xFA, 0x80, 0xC7, 0x5A, 0x56, 0xBF, 0xF0, 0x53, 0x2F, 0xF8, 0x37, 0xB2, 0xD5, 0x7F, 0xD1,
+	0xBC, 0x2D, 0xAB, 0x7F, 0xE0, 0x86, 0x3A, 0xFC, 0x69, 0xFF, 0x00, 0x85, 0x55, 0xE0, 0x7F, 0xFA,
+	0x03, 0x8F, 0xFB, 0xF8, 0x68, 0xFF, 0x00, 0x85, 0x55, 0xE0, 0x7F, 0xFA, 0x03, 0x8F, 0xFB, 0xF8,
+	0x6A, 0x1E, 0x16, 0x31, 0x76, 0x29, 0x62, 0x24, 0x7E, 0xD8, 0x69, 0x7F, 0xF0, 0x56, 0xFF, 0x00,
+	0xF8, 0x20, 0x96, 0x8E, 0x55, 0x2C, 0xFC, 0x39, 0xA9, 0x2B, 0x74, 0xF9, 0xB4, 0x05, 0xAE, 0xAF,
+	0x45, 0xFF, 0x00, 0x82, 0xEE, 0x7F, 0xC1, 0x14, 0xFC, 0x3A, 0x3E, 0xC5, 0xA3, 0xD8, 0x6A, 0x90,
+	0xF9, 0x7F, 0xF3, 0xCF, 0x43, 0x5F, 0xFE, 0x2A, 0xBF, 0x09, 0xBF, 0xE1, 0x52, 0x78, 0x13, 0x9F,
+	0xF8, 0x93, 0xF5, 0xFF, 0x00, 0xA6, 0x86, 0x9B, 0x71, 0xF0, 0xB3, 0xC1, 0x10, 0xED, 0x8E, 0x3D,
+	0x1C, 0x01, 0xFF, 0x00, 0x5D, 0x0D, 0x2F, 0xAB, 0xC7, 0xB8, 0x2C, 0x54, 0x8F, 0xDF, 0xEB, 0x1F,
+	0xF8, 0x39, 0x0F, 0xFE, 0x09, 0x2D, 0xA6, 0xAB, 0x25, 0xB6, 0xA7, 0xAE, 0x46, 0xB1, 0xFF, 0x00,
+	0xD4, 0x17, 0xFF, 0x00, 0xB2, 0xAF, 0x83, 0x7F, 0xE0, 0xAF, 0xBF, 0xF0, 0x70, 0x2E, 0x8F, 0xFB,
+	0x74, 0xF8, 0x3E, 0xFB, 0xF6, 0x52, 0xFD, 0x88, 0xAC, 0x2F, 0x26, 0xF0, 0x9D, 0xF5, 0xBF, 0x95,
+	0xE2, 0xA9, 0xAF, 0x2D, 0x5A, 0x2B, 0xAB, 0x88, 0x5B, 0xEF, 0x2C, 0x71, 0xEE, 0xF9, 0xBE, 0x6A,
+	0xFC, 0xF9, 0xB1, 0xF8, 0x45, 0xE0, 0x1B, 0x8B, 0xF8, 0xEC, 0xA6, 0xD0, 0xD5, 0xA3, 0x91, 0xFE,
+	0x65, 0xF3, 0x0F, 0x35, 0xFA, 0xA1, 0xFF, 0x00, 0x04, 0x7C, 0xFD, 0x80, 0x3F, 0x65, 0x1D, 0x63,
+	0xC5, 0xDE, 0x15, 0xF8, 0x93, 0xAA, 0x7C, 0x2B, 0xB5, 0x9F, 0x57, 0xBB, 0xBE, 0xD9, 0x3D, 0xC4,
+	0x8E, 0x4E, 0xE5, 0x5E, 0x9C, 0x54, 0xCA, 0x8C, 0x61, 0x2B, 0x9A, 0x46, 0xB4, 0xA4, 0xAC, 0xCE,
+	0xBB, 0xFE, 0x08, 0xB3, 0xFF, 0x00, 0x04, 0x78, 0xD7, 0x74, 0x4F, 0xD8, 0xF6, 0xDF, 0x50, 0xF1,
+	0x4E, 0x8E, 0xA1, 0xF5, 0x4D, 0x49, 0xAE, 0xAD, 0x97, 0x58, 0x8F, 0xCB, 0x95, 0x62, 0x65, 0x5C,
+	0x71, 0x45, 0x7E, 0xCB, 0xE8, 0xF6, 0x56, 0x7A, 0x5D, 0xA2, 0xE9, 0x5A, 0x75, 0xAC, 0x70, 0xDB,
+	0xDA, 0xA2, 0xC7, 0x0C, 0x31, 0xAE, 0x02, 0xA8, 0x1D, 0x28, 0xAE, 0x7F, 0xAC, 0x54, 0x5A, 0x23,
+	0xA1, 0x50, 0xA7, 0x2D, 0x59, 0xFF, 0xD9, 0x00, 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46,
+	0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60, 0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x3A,
+	0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D, 0x00, 0x2A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x03,
+	0x51, 0x10, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x51, 0x11, 0x00, 0x04,
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x51, 0x12, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x02, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x04, 0x03, 0x02, 0x02,
+	0x02, 0x02, 0x05, 0x04, 0x04, 0x03, 0x04, 0x06, 0x05, 0x06, 0x06, 0x06, 0x05, 0x06, 0x06, 0x06,
+	0x07, 0x09, 0x08, 0x06, 0x07, 0x09, 0x07, 0x06, 0x06, 0x08, 0x0B, 0x08, 0x09, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x06, 0x08, 0x0B, 0x0C, 0x0B, 0x0A, 0x0C, 0x09, 0x0A, 0x0A, 0x0A, 0xFF, 0xDB, 0x00,
+	0x43, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x05, 0x03, 0x03, 0x05, 0x0A, 0x07, 0x06, 0x07,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A,
+	0x0A, 0x0A, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00, 0x92, 0x00, 0x4C, 0x03, 0x01, 0x22, 0x00, 0x02,
+	0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00, 0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
+	0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03,
+	0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04,
+	0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81,
+	0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82,
+	0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36,
+	0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56,
+	0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76,
+	0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95,
+	0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3,
+	0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA,
+	0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
+	0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00,
+	0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4,
+	0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00,
+	0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51,
+	0x07, 0x61, 0x71, 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23,
+	0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18,
+	0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45,
+	0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65,
+	0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84,
+	0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2,
+	0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9,
+	0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7,
+	0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5,
+	0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11,
+	0x00, 0x3F, 0x00, 0xF8, 0x4F, 0xFE, 0x0B, 0x17, 0xFF, 0x00, 0x05, 0x24, 0xFF, 0x00, 0x82, 0x8A,
+	0x7C, 0x2D, 0xFF, 0x00, 0x82, 0xA5, 0xFC, 0x79, 0xF8, 0x79, 0xF0, 0xCF, 0xF6, 0xFA, 0xF8, 0xD9,
+	0xE1, 0xEF, 0x0F, 0xE8, 0xFF, 0x00, 0x12, 0xF5, 0x2B, 0x6D, 0x27, 0x43, 0xD1, 0x3E, 0x2A, 0xEB,
+	0x16, 0xB6, 0x76, 0x30, 0xAC, 0xA7, 0x6C, 0x50, 0xC3, 0x1D, 0xC8, 0x48, 0x90, 0x74, 0x0A, 0xA0,
+	0x28, 0x1C, 0x00, 0x05, 0x7C, 0xD7, 0xFF, 0x00, 0x0F, 0x62, 0xFF, 0x00, 0x82, 0xA6, 0xFF, 0x00,
+	0xD2, 0x4B, 0x3F, 0x68, 0x0F, 0xFC, 0x3C, 0x9A, 0xE7, 0xFF, 0x00, 0x25, 0x57, 0x55, 0xFF, 0x00,
+	0x05, 0xC7, 0xFF, 0x00, 0x94, 0xBE, 0x7E, 0xD1, 0x5F, 0xF6, 0x55, 0x35, 0x4F, 0xFD, 0x1B, 0x5F,
+	0xAA, 0x9F, 0xF0, 0x44, 0xEF, 0xF8, 0x20, 0xCF, 0xFC, 0x12, 0x2B, 0xF6, 0xCF, 0xFF, 0x00, 0x82,
+	0x62, 0xFC, 0x31, 0xFD, 0xA5, 0xBF, 0x6A, 0x18, 0xF5, 0x0F, 0xF8, 0x4E, 0xBC, 0x4A, 0x35, 0xAF,
+	0xED, 0xC3, 0x0F, 0xC4, 0x27, 0xB1, 0x53, 0xF6, 0x7D, 0x6A, 0xFE, 0xD6, 0x1C, 0x40, 0x18, 0x04,
+	0xFD, 0xC4, 0x11, 0x76, 0xE4, 0xF3, 0xDE, 0x80, 0x3F, 0x20, 0x7F, 0xE1, 0xEC, 0x5F, 0xF0, 0x54,
+	0xDF, 0xFA, 0x49, 0x67, 0xED, 0x01, 0xFF, 0x00, 0x87, 0x93, 0x5C, 0xFF, 0x00, 0xE4, 0xAA, 0x3F,
+	0xE1, 0xEC, 0x5F, 0xF0, 0x54, 0xDF, 0xFA, 0x49, 0x67, 0xED, 0x01, 0xFF, 0x00, 0x87, 0x93, 0x5C,
+	0xFF, 0x00, 0xE4, 0xAA, 0xF7, 0xEF, 0xF8, 0x38, 0xC7, 0xF6, 0x0C, 0xFD, 0x90, 0xBF, 0xE0, 0x9E,
+	0x7F, 0xB6, 0x9F, 0x86, 0x7E, 0x0D, 0x7E, 0xC6, 0x06, 0xE3, 0xFE, 0x11, 0x9D, 0x4B, 0xE1, 0xC5,
+	0xAE, 0xAF, 0x7C, 0x2E, 0x3C, 0x42, 0x75, 0x26, 0x17, 0xAF, 0x7B, 0x7B, 0x13, 0x7E, 0xF0, 0x93,
+	0xB4, 0x79, 0x70, 0xC5, 0xF2, 0xF6, 0xEB, 0xDE, 0xBE, 0x01, 0xA0, 0x0F, 0xA0, 0x3F, 0xE1, 0xEC,
+	0x5F, 0xF0, 0x54, 0xDF, 0xFA, 0x49, 0x67, 0xED, 0x01, 0xFF, 0x00, 0x87, 0x93, 0x5C, 0xFF, 0x00,
+	0xE4, 0xAA, 0x3F, 0xE1, 0xEC, 0x5F, 0xF0, 0x54, 0xDF, 0xFA, 0x49, 0x67, 0xED, 0x01, 0xFF, 0x00,
+	0x87, 0x93, 0x5C, 0xFF, 0x00, 0xE4, 0xAA, 0xFD, 0xD5, 0xFD, 0x88, 0x3F, 0xE0, 0xDC, 0x5F, 0xF8,
+	0x22, 0x37, 0xC6, 0x9F, 0xD8, 0xD3, 0xE1, 0x4F, 0xC6, 0x0F, 0x8A, 0x1F, 0xDA, 0x8D, 0xE2, 0x5F,
+	0x14, 0x7C, 0x3B, 0xD1, 0xB5, 0x5F, 0x10, 0x15, 0xF8, 0x9C, 0xF0, 0x0F, 0xB6, 0xDC, 0x59, 0x45,
+	0x2C, 0xD8, 0x8C, 0x30, 0x11, 0x8F, 0x31, 0x9B, 0xE5, 0xC7, 0xCB, 0xD3, 0xB5, 0x7E, 0x2A, 0x7F,
+	0xC1, 0x6D, 0x3F, 0x65, 0xDF, 0x80, 0x7F, 0xB1, 0x7F, 0xFC, 0x14, 0xEB, 0xE2, 0x67, 0xEC, 0xD3,
+	0xFB, 0x30, 0x24, 0xCB, 0xE0, 0x5F, 0x0D, 0x8D, 0x17, 0xFB, 0x0C, 0x4F, 0xAB, 0x1B, 0xE6, 0xFF,
+	0x00, 0x48, 0xD1, 0x6C, 0x2E, 0xA6, 0xCC, 0xE4, 0x92, 0xFF, 0x00, 0xBF, 0x9E, 0x5E, 0xFC, 0x0E,
+	0x3B, 0x50, 0x07, 0xF4, 0x51, 0xFF, 0x00, 0x06, 0xA7, 0x7C, 0x74, 0xF8, 0xDD, 0xFB, 0x43, 0xFF,
+	0x00, 0xC1, 0x2D, 0x24, 0xF8, 0x87, 0xFB, 0x40, 0x7C, 0x64, 0xF1, 0x67, 0x8E, 0xBC, 0x40, 0x7E,
+	0x25, 0xEA, 0xF6, 0xDF, 0xDB, 0x9E, 0x32, 0xF1, 0x15, 0xD6, 0xA9, 0x79, 0xE4, 0x24, 0x56, 0xBB,
+	0x22, 0xF3, 0xAE, 0x64, 0x77, 0x08, 0xB9, 0x6C, 0x2E, 0x70, 0x0B, 0x12, 0x07, 0x26, 0xBF, 0x4A,
+	0xAB, 0xF2, 0xAF, 0xFE, 0x0C, 0xED, 0xFF, 0x00, 0x94, 0x41, 0xB7, 0xFD, 0x95, 0x4D, 0x6F, 0xFF,
+	0x00, 0x45, 0x5A, 0x57, 0xEA, 0xA5, 0x00, 0x14, 0x51, 0x45, 0x00, 0x7F, 0x15, 0xBF, 0xF0, 0x5C,
+	0x7F, 0xF9, 0x4B, 0xE7, 0xED, 0x15, 0xFF, 0x00, 0x65, 0x53, 0x54, 0xFF, 0x00, 0xD1, 0xB5, 0x9B,
+	0xFF, 0x00, 0x04, 0xE3, 0xF8, 0x7F, 0xFF, 0x00, 0x04, 0xFF, 0x00, 0xF8, 0xA3, 0xE2, 0x4F, 0x11,
+	0x68, 0xDF, 0xF0, 0x50, 0xCF, 0xDB, 0x5B, 0xC5, 0xFF, 0x00, 0x07, 0xF4, 0x4B, 0x0B, 0x18, 0x1F,
+	0xC3, 0x37, 0x5E, 0x17, 0xF0, 0xDD, 0xDE, 0xA8, 0x6F, 0xE7, 0x67, 0x7F, 0x36, 0x36, 0x4B, 0x78,
+	0x25, 0xF2, 0xC2, 0x8D, 0xAD, 0x92, 0x00, 0x25, 0x8F, 0x5E, 0xDA, 0x5F, 0xF0, 0x5C, 0x7F, 0xF9,
+	0x4B, 0xE7, 0xED, 0x15, 0xFF, 0x00, 0x65, 0x53, 0x54, 0xFF, 0x00, 0xD1, 0xB5, 0xF3, 0x1F, 0x86,
+	0xBC, 0x31, 0xE2, 0x5F, 0x19, 0xEB, 0xB6, 0xBE, 0x16, 0xF0, 0x7F, 0x87, 0xAF, 0xB5, 0x6D, 0x4E,
+	0xF6, 0x4F, 0x2E, 0xCF, 0x4E, 0xD3, 0x6D, 0x1E, 0x79, 0xE7, 0x7C, 0x67, 0x6A, 0x46, 0x80, 0xB3,
+	0x1F, 0x60, 0x09, 0xA0, 0x0B, 0x9F, 0x11, 0x5B, 0x45, 0x5F, 0x1D, 0x6A, 0xF6, 0x9E, 0x16, 0xF1,
+	0x4D, 0xDE, 0xB5, 0xA3, 0xDA, 0xEA, 0x57, 0x10, 0x68, 0xBA, 0xA5, 0xF2, 0xBA, 0xC9, 0x75, 0x66,
+	0xB2, 0xB0, 0x86, 0x56, 0x57, 0x00, 0xA1, 0x64, 0xC3, 0x15, 0x20, 0x60, 0xB1, 0xE0, 0x56, 0x2D,
+	0x7D, 0x49, 0xF0, 0xBB, 0xFE, 0x08, 0x97, 0xFF, 0x00, 0x05, 0x63, 0xF8, 0xC9, 0xA4, 0x2E, 0xBD,
+	0xE0, 0x0F, 0xD8, 0x2B, 0xE2, 0x1C, 0xF6, 0xB2, 0x7D, 0xD9, 0x2F, 0xF4, 0x8F, 0xB0, 0x9F, 0xC5,
+	0x6E, 0x9A, 0x36, 0x1D, 0x3B, 0x8A, 0xEB, 0xAF, 0x7F, 0xE0, 0xDD, 0xEF, 0xF8, 0x2D, 0x0D, 0x8C,
+	0x2B, 0x33, 0xFE, 0xC0, 0xBE, 0x2E, 0x93, 0x72, 0xE7, 0x6C, 0x37, 0x56, 0x4E, 0xCB, 0xF5, 0x02,
+	0x7A, 0x00, 0xE6, 0xFF, 0x00, 0x61, 0x8F, 0x86, 0xDF, 0xF0, 0x4D, 0xAF, 0x88, 0xDF, 0x06, 0x7C,
+	0x63, 0xAD, 0x7E, 0xDC, 0x1F, 0xB7, 0xA7, 0x8D, 0xFE, 0x18, 0xF8, 0xBB, 0x4B, 0x9B, 0xCB, 0xF0,
+	0x3F, 0x87, 0x3C, 0x3F, 0xE1, 0x6B, 0xCD, 0x46, 0xDF, 0x54, 0x88, 0x5B, 0x96, 0x06, 0x49, 0x21,
+	0x82, 0x45, 0x87, 0xF7, 0xA0, 0x47, 0x82, 0xCB, 0x80, 0x73, 0xD2, 0xBE, 0x55, 0xBA, 0xBB, 0xBB,
+	0xBE, 0x9D, 0xAE, 0xAF, 0x6E, 0x64, 0x9A, 0x56, 0xC6, 0xE9, 0x25, 0x72, 0xCC, 0x70, 0x31, 0xD4,
+	0xFB, 0x57, 0xAC, 0x7C, 0x79, 0xFD, 0x81, 0xFF, 0x00, 0x6D, 0x7F, 0xD9, 0x80, 0x5D, 0x4F, 0xF1,
+	0xFF, 0x00, 0xF6, 0x57, 0xF1, 0xDF, 0x85, 0x6D, 0x6C, 0xF6, 0x8B, 0xAD, 0x4B, 0x54, 0xF0, 0xDD,
+	0xC2, 0xD9, 0xC6, 0x49, 0xC0, 0x06, 0xE4, 0x29, 0x87, 0x39, 0xED, 0xBF, 0x3F, 0x9D, 0x79, 0x1D,
+	0x00, 0x7F, 0x55, 0x1F, 0xF0, 0x67, 0x6F, 0xFC, 0xA2, 0x0D, 0xBF, 0xEC, 0xAA, 0x6B, 0x7F, 0xFA,
+	0x2A, 0xD2, 0xBF, 0x55, 0x2B, 0xF2, 0xAF, 0xFE, 0x0C, 0xED, 0xFF, 0x00, 0x94, 0x41, 0xB7, 0xFD,
+	0x95, 0x4D, 0x6F, 0xFF, 0x00, 0x45, 0x5A, 0x57, 0xEA, 0xA5, 0x00, 0x14, 0x51, 0x45, 0x00, 0x7E,
+	0x37, 0x5C, 0x7F, 0xC1, 0xAA, 0x7E, 0x12, 0xFD, 0xAA, 0xBF, 0xE0, 0xA2, 0x7F, 0x17, 0xBF, 0x6D,
+	0x2F, 0xDB, 0xAF, 0xE2, 0x4C, 0x87, 0xC2, 0x9E, 0x2C, 0xF8, 0x8D, 0xA9, 0x6A, 0x7E, 0x17, 0xF8,
+	0x7F, 0xE1, 0x3B, 0xA2, 0x93, 0x5D, 0xD9, 0x3C, 0x8D, 0xE5, 0xCB, 0x7D, 0x74, 0x54, 0x79, 0x45,
+	0xBE, 0xF0, 0x86, 0x1C, 0x90, 0xBB, 0x77, 0x48, 0x09, 0x68, 0xD7, 0xE9, 0xFF, 0x00, 0x16, 0x7E,
+	0xD2, 0x9F, 0xF0, 0x41, 0x8F, 0xF8, 0x21, 0xC7, 0x87, 0x26, 0xF0, 0x4D, 0x8D, 0xFF, 0x00, 0xC2,
+	0xFF, 0x00, 0x86, 0xFA, 0x94, 0x31, 0x2A, 0xDD, 0x68, 0x7E, 0x13, 0xD1, 0xD6, 0xFB, 0xC4, 0x17,
+	0x84, 0x31, 0xDB, 0xE7, 0xFD, 0x9D, 0x24, 0xBA, 0x94, 0x86, 0xE3, 0x74, 0xED, 0x85, 0xE3, 0x25,
+	0x40, 0xE3, 0xF2, 0x1F, 0xFE, 0x0B, 0x9B, 0xFF, 0x00, 0x07, 0x3C, 0x7E, 0xD3, 0x7F, 0x1C, 0xFE,
+	0x23, 0x78, 0xAB, 0xF6, 0x48, 0xFD, 0x8A, 0x75, 0x3D, 0x6B, 0xE1, 0x6F, 0x81, 0xF4, 0x1D, 0x62,
+	0xE7, 0x48, 0xD7, 0x3C, 0x47, 0x69, 0x74, 0x20, 0xD7, 0xB5, 0xD9, 0x2D, 0xE5, 0x68, 0xA5, 0x0B,
+	0x34, 0x4C, 0x4D, 0x95, 0xB9, 0x91, 0x1B, 0x0B, 0x13, 0xF9, 0x92, 0x20, 0x1B, 0xDD, 0x55, 0xDE,
+	0x2A, 0xFC, 0x73, 0xD4, 0xB5, 0x3D, 0x47, 0x59, 0xBF, 0x9B, 0x55, 0xD5, 0xEF, 0xE6, 0xBA, 0xBA,
+	0xB8, 0x90, 0xC9, 0x71, 0x73, 0x73, 0x29, 0x92, 0x49, 0x58, 0xF5, 0x66, 0x66, 0x24, 0x92, 0x7D,
+	0x4D, 0x00, 0x7F, 0x4A, 0x9F, 0x13, 0xFF, 0x00, 0xE0, 0xF6, 0x5F, 0xD8, 0x63, 0x42, 0xBC, 0x92,
+	0xD7, 0xE1, 0x17, 0xEC, 0xA1, 0xF1, 0x4B, 0xC4, 0x71, 0xC6, 0xEC, 0xBF, 0x68, 0xD6, 0xA6, 0xD3,
+	0xF4, 0xB4, 0x93, 0x07, 0x1B, 0x97, 0x64, 0xD7, 0x0D, 0xB4, 0x8E, 0x46, 0xE5, 0x56, 0xF5, 0x50,
+	0x6B, 0x8F, 0xB1, 0xFF, 0x00, 0x83, 0xE1, 0x3E, 0x06, 0x49, 0x74, 0xA9, 0xA9, 0x7E, 0xC0, 0x1E,
+	0x2C, 0x86, 0x1C, 0xFE, 0xF2, 0x48, 0x3C, 0x71, 0x6B, 0x23, 0x01, 0xEC, 0xA6, 0xD9, 0x41, 0xFC,
+	0xC5, 0x7F, 0x3A, 0xB4, 0x50, 0x07, 0xF5, 0x5B, 0xFB, 0x3A, 0x7F, 0xC1, 0xDC, 0xDF, 0xF0, 0x49,
+	0x0F, 0xDA, 0x1B, 0x52, 0x8B, 0xC1, 0x7F, 0x15, 0x97, 0xC6, 0xBF, 0x0C, 0xE6, 0xBA, 0x0B, 0x1B,
+	0x4D, 0xE3, 0xAF, 0x0E, 0x45, 0x3E, 0x9B, 0x23, 0xB1, 0xC6, 0xCF, 0x3E, 0xCA, 0x6B, 0x8D, 0xAA,
+	0x3B, 0xBC, 0xD1, 0xC4, 0xA3, 0x3C, 0x9A, 0xEB, 0x7F, 0x69, 0x1F, 0xF8, 0x21, 0x4F, 0xFC, 0x11,
+	0x6B, 0xFE, 0x0A, 0xC9, 0xF0, 0xC2, 0x6F, 0x8B, 0x3F, 0x00, 0xFC, 0x3D, 0xE1, 0x1D, 0x07, 0x50,
+	0xD6, 0x14, 0xCD, 0x63, 0xF1, 0x13, 0xE0, 0xBC, 0xD6, 0xB0, 0xC5, 0x24, 0xCC, 0x77, 0x79, 0x93,
+	0x41, 0x07, 0xFA, 0x3C, 0xE5, 0xB2, 0x4B, 0x6E, 0x40, 0xED, 0xB8, 0x92, 0xD9, 0xC1, 0x1F, 0xC9,
+	0x2D, 0x7B, 0x07, 0xEC, 0x6B, 0xFB, 0x7A, 0xFE, 0xD6, 0x9F, 0xB0, 0x1F, 0xC5, 0x2B, 0x3F, 0x8B,
+	0x5F, 0xB2, 0xAF, 0xC6, 0xAD, 0x6B, 0xC2, 0xF7, 0xD6, 0xF7, 0x0B, 0x25, 0xE6, 0x9F, 0x6F, 0x78,
+	0xED, 0xA7, 0xEA, 0xA9, 0xD0, 0xC3, 0x79, 0x6A, 0x4F, 0x95, 0x73, 0x19, 0x1D, 0x9D, 0x49, 0x52,
+	0x15, 0x94, 0xAB, 0xAA, 0xB0, 0x00, 0xFE, 0xB4, 0x3F, 0xE0, 0x86, 0x5F, 0xF0, 0x4E, 0x3F, 0x8A,
+	0x3F, 0xF0, 0x4B, 0x1F, 0xD8, 0xEB, 0x57, 0xFD, 0x94, 0xBE, 0x29, 0xF8, 0xC7, 0x47, 0xF1, 0x14,
+	0xF6, 0xFF, 0x00, 0x11, 0x35, 0x4D, 0x4F, 0x47, 0xD7, 0x74, 0x51, 0x22, 0xC7, 0x7D, 0x61, 0x3C,
+	0x76, 0xDE, 0x4C, 0x8F, 0x1C, 0x83, 0x74, 0x32, 0xFC, 0x8C, 0x1E, 0x3C, 0xB8, 0x56, 0x53, 0xB5,
+	0xDD, 0x70, 0xC7, 0xEC, 0xCA, 0xF8, 0xA7, 0xFE, 0x08, 0x67, 0xFF, 0x00, 0x05, 0x75, 0xB0, 0xFF,
+	0x00, 0x82, 0xBD, 0x7E, 0xCB, 0x5A, 0x87, 0xC5, 0x3D, 0x53, 0xE1, 0xA4, 0xDE, 0x17, 0xF1, 0x67,
+	0x84, 0x75, 0x64, 0xD2, 0x3C, 0x5F, 0x63, 0x14, 0x82, 0x4B, 0x29, 0xAE, 0x5A, 0x21, 0x2A, 0x4F,
+	0x6A, 0xF9, 0xDF, 0xE5, 0xBA, 0x10, 0x4A, 0xB8, 0x0C, 0x8D, 0xB9, 0x72, 0xC0, 0x06, 0x3F, 0x6B,
+	0x50, 0x01, 0x45, 0x14, 0x50, 0x07, 0xF0, 0x93, 0xFB, 0x62, 0x7F, 0xC9, 0xDC, 0x7C, 0x53, 0xFF,
+	0x00, 0xB2, 0x8D, 0xAE, 0x7F, 0xE9, 0x7C, 0xD5, 0xE7, 0x35, 0xE8, 0xDF, 0xB6, 0x27, 0xFC, 0x9D,
+	0xC7, 0xC5, 0x3F, 0xFB, 0x28, 0xDA, 0xE7, 0xFE, 0x97, 0xCD, 0x5E, 0x73, 0x40, 0x05, 0x14, 0x51,
+	0x40, 0x05, 0x14, 0x51, 0x40, 0x1F, 0xD2, 0x27, 0xFC, 0x19, 0x15, 0xFF, 0x00, 0x26, 0x8F, 0xF1,
+	0xAF, 0xFE, 0xCA, 0x35, 0x97, 0xFE, 0x90, 0x2D, 0x7E, 0xDC, 0x57, 0xE2, 0x3F, 0xFC, 0x19, 0x15,
+	0xFF, 0x00, 0x26, 0x8F, 0xF1, 0xAF, 0xFE, 0xCA, 0x35, 0x97, 0xFE, 0x90, 0x2D, 0x7E, 0xDC, 0x50,
+	0x01, 0x45, 0x14, 0x50, 0x07, 0xF0, 0x93, 0xFB, 0x62, 0x7F, 0xC9, 0xDC, 0x7C, 0x53, 0xFF, 0x00,
+	0xB2, 0x8D, 0xAE, 0x7F, 0xE9, 0x7C, 0xD5, 0xE7, 0x35, 0xE8, 0xDF, 0xB6, 0x27, 0xFC, 0x9D, 0xC7,
+	0xC5, 0x3F, 0xFB, 0x28, 0xDA, 0xE7, 0xFE, 0x97, 0xCD, 0x5E, 0x73, 0x40, 0x05, 0x14, 0x51, 0x40,
+	0x05, 0x14, 0x51, 0x40, 0x1F, 0xD2, 0x27, 0xFC, 0x19, 0x15, 0xFF, 0x00, 0x26, 0x8F, 0xF1, 0xAF,
+	0xFE, 0xCA, 0x35, 0x97, 0xFE, 0x90, 0x2D, 0x7E, 0xDC, 0x57, 0xE2, 0x3F, 0xFC, 0x19, 0x15, 0xFF,
+	0x00, 0x26, 0x8F, 0xF1, 0xAF, 0xFE, 0xCA, 0x35, 0x97, 0xFE, 0x90, 0x2D, 0x7E, 0xDC, 0x50, 0x01,
+	0x45, 0x14, 0x50, 0x07, 0xF1, 0x5F, 0xFF, 0x00, 0x05, 0x49, 0xFF, 0x00, 0x82, 0x79, 0xFE, 0xDB,
+	0x3F, 0xB2, 0x9F, 0xED, 0x1D, 0xF1, 0x03, 0xC7, 0xDF, 0x1F, 0xBF, 0x66, 0xAF, 0x14, 0x78, 0x7B,
+	0xC3, 0xDA, 0xCF, 0x8D, 0xF5, 0x4B, 0xDD, 0x33, 0xC4, 0x53, 0x58, 0x79, 0xDA, 0x74, 0xF0, 0x4F,
+	0x7D, 0x29, 0x85, 0xFE, 0xD3, 0x09, 0x78, 0x94, 0xB8, 0x65, 0xC2, 0xB3, 0x06, 0x39, 0xC6, 0x33,
+	0xC5, 0x7C, 0xA7, 0x5F, 0xDF, 0x9E, 0xB1, 0xA3, 0x68, 0xFE, 0x21, 0xD3, 0x26, 0xD1, 0x75, 0xFD,
+	0x26, 0xDA, 0xFA, 0xCE, 0xE6, 0x36, 0x8E, 0xE2, 0xD2, 0xF2, 0xDD, 0x65, 0x8A, 0x54, 0x23, 0x05,
+	0x59, 0x58, 0x10, 0xC0, 0x82, 0x41, 0x04, 0x60, 0x8A, 0xFE, 0x67, 0xBF, 0xE0, 0xF0, 0x6F, 0xD8,
+	0xB7, 0xF6, 0x50, 0xFD, 0x92, 0xBE, 0x32, 0xFC, 0x1B, 0xD7, 0x3F, 0x66, 0x2F, 0x80, 0x1E, 0x19,
+	0xF0, 0x14, 0x9E, 0x32, 0xD2, 0x75, 0xC9, 0xBC, 0x49, 0x6F, 0xE1, 0x5D, 0x35, 0x6C, 0xAD, 0xAE,
+	0xE4, 0xB7, 0x92, 0xC5, 0x62, 0x6F, 0xB3, 0xC5, 0x88, 0xA3, 0x2A, 0x25, 0x93, 0xFD, 0x5A, 0x2E,
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+	0x24, 0xF2, 0xEC, 0x34, 0x9D, 0x1E, 0xC6, 0x4B, 0xAB, 0x9B, 0x97, 0xC1, 0x3B, 0x63, 0x8A, 0x30,
+	0x59, 0xCE, 0x01, 0x38, 0x00, 0x9C, 0x03, 0x59, 0xB5, 0xFD, 0xC3, 0xFE, 0xC3, 0x9F, 0xB0, 0xA7,
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+	0xF5, 0x0D, 0x16, 0xD5, 0xF5, 0x2D, 0x4B, 0x47, 0xD1, 0xA3, 0x5B, 0xEB, 0xD2, 0x50, 0x3F, 0xEF,
+	0xEE, 0x98, 0x19, 0xE6, 0xC3, 0x33, 0x10, 0x1D, 0xD8, 0x2E, 0x78, 0xC0, 0xA0, 0x0F, 0x84, 0x3F,
+	0xE0, 0xD2, 0x8F, 0xD8, 0x93, 0xF6, 0xA9, 0xFD, 0x8C, 0x3F, 0x64, 0xCF, 0x88, 0xF6, 0x9F, 0xB5,
+	0x27, 0xC1, 0x8D, 0x57, 0xC1, 0x57, 0x5E, 0x2D, 0xF1, 0x95, 0xAE, 0xA3, 0xA0, 0xD9, 0x6B, 0x5E,
+	0x5A, 0xCF, 0x71, 0x6A, 0xB6, 0x6A, 0x86, 0x43, 0x1A, 0xB1, 0x68, 0xC6, 0xEE, 0x30, 0xE1, 0x4F,
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+	0x13, 0x9B, 0xF6, 0x24, 0xFD, 0xBB, 0x6F, 0xF4, 0x3D, 0x4F, 0xF6, 0xB9, 0xFD, 0x9D, 0xF4, 0x3F,
+	0x1D, 0x5C, 0x78, 0x6E, 0x19, 0xE2, 0xD0, 0xE5, 0xD5, 0xDA, 0x60, 0x6C, 0xD2, 0x62, 0x86, 0x50,
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+	0xFE, 0x0E, 0x76, 0xFF, 0x00, 0x82, 0x4E, 0xFF, 0x00, 0xC1, 0x3A, 0xBF, 0x63, 0x1F, 0xF8, 0x26,
+	0x7A, 0xFC, 0x62, 0xFD, 0x97, 0xFF, 0x00, 0x65, 0x3F, 0x0E, 0xF8, 0x37, 0xC4, 0xCD, 0xF1, 0x13,
+	0x49, 0xB0, 0x3A, 0xC6, 0x96, 0xF7, 0x06, 0x5F, 0xB3, 0xC9, 0x15, 0xD1, 0x78, 0xFF, 0x00, 0x79,
+	0x2B, 0x0C, 0x31, 0x45, 0xCF, 0x1D, 0xAB, 0xF1, 0x9F, 0xFE, 0x09, 0x25, 0xF0, 0x9F, 0xE1, 0xD7,
+	0xC7, 0x6F, 0xF8, 0x29, 0x8F, 0xC1, 0x0F, 0x83, 0xBF, 0x17, 0x3C, 0x29, 0x6D, 0xAE, 0xF8, 0x67,
+	0xC4, 0x9F, 0x11, 0x34, 0xFB, 0x1D, 0x73, 0x47, 0xBC, 0xDD, 0xE5, 0x5E, 0x5B, 0xBC, 0x98, 0x78,
+	0xDB, 0x69, 0x07, 0x04, 0x7A, 0x11, 0x5F, 0xD1, 0x07, 0xFC, 0x1E, 0x29, 0xFF, 0x00, 0x28, 0x84,
+	0x8F, 0xFE, 0xCA, 0xB6, 0x8B, 0xFF, 0x00, 0xA2, 0x6F, 0x2B, 0xF0, 0x07, 0xFE, 0x08, 0x71, 0xFF,
+	0x00, 0x29, 0x7C, 0xFD, 0x9D, 0x7F, 0xEC, 0xAA, 0x69, 0x7F, 0xFA, 0x36, 0x80, 0x3F, 0xA8, 0x75,
+	0xFF, 0x00, 0x83, 0x7B, 0x3F, 0xE0, 0x8C, 0x0A, 0x77, 0x0F, 0xF8, 0x27, 0xEF, 0x82, 0xF8, 0xF5,
+	0x92, 0xF3, 0xFF, 0x00, 0x8F, 0xD7, 0xD8, 0xBA, 0x7D, 0x85, 0x9E, 0x93, 0xA7, 0xC1, 0xA5, 0xE9,
+	0xD0, 0x2C, 0x56, 0xF6, 0xD0, 0xAC, 0x50, 0x46, 0xBD, 0x11, 0x14, 0x60, 0x0F, 0xC0, 0x0A, 0x9A,
+	0x8A, 0x00, 0x28, 0xA1, 0x99, 0x51, 0x4B, 0xBB, 0x61, 0x47, 0x24, 0x9E, 0xD5, 0xF9, 0x69, 0xFF,
+	0x00, 0x05, 0x2D, 0xFF, 0x00, 0x83, 0xAD, 0x7F, 0x61, 0x8F, 0xD8, 0x7B, 0xC6, 0x3A, 0x97, 0xC1,
+	0x6F, 0x82, 0x7A, 0x1D, 0xF7, 0xC6, 0x0F, 0x1C, 0x69, 0x73, 0x3D, 0xBE, 0xA8, 0x34, 0x0B, 0xC8,
+	0xE0, 0xD1, 0xB4, 0xDB, 0x85, 0xE1, 0xA2, 0x96, 0xF4, 0xEE, 0xF3, 0x64, 0x56, 0x38, 0x29, 0x02,
+	0x3A, 0x82, 0xAE, 0xAC, 0xE8, 0xCB, 0xB6, 0x80, 0x3F, 0x52, 0xE8, 0xAF, 0xE7, 0x0B, 0xC3, 0x5F,
+	0xF0, 0x7B, 0x47, 0xED, 0x33, 0x2F, 0xC5, 0x1D, 0x27, 0x50, 0xF1, 0x97, 0xEC, 0x85, 0xE0, 0xF8,
+	0x7C, 0x1E, 0x35, 0x08, 0xBF, 0xB7, 0x34, 0xDD, 0x2B, 0x54, 0xB8, 0x7B, 0xE3, 0x6B, 0x9C, 0x49,
+	0xE4, 0xCB, 0x26, 0x13, 0xCC, 0x0B, 0x96, 0x5D, 0xCA, 0x14, 0x90, 0x01, 0xC0, 0x24, 0x8F, 0xDF,
+	0x5F, 0xD9, 0x27, 0xF6, 0xB4, 0xF8, 0x13, 0xFB, 0x6F, 0xFC, 0x03, 0xD0, 0x7F, 0x69, 0x4F, 0xD9,
+	0xC7, 0xC6, 0xB0, 0xEB, 0x9E, 0x17, 0xF1, 0x0D, 0xBE, 0xFB, 0x6B, 0x85, 0xF9, 0x65, 0xB7, 0x95,
+	0x78, 0x92, 0xDE, 0x78, 0xF3, 0x98, 0xA6, 0x8D, 0xBE, 0x57, 0x43, 0xC8, 0x3E, 0xA0, 0x82, 0x40,
+	0x3D, 0x22, 0x8A, 0x28, 0xA0, 0x0F, 0xCA, 0xBF, 0xF8, 0x3C, 0x53, 0xFE, 0x51, 0x09, 0x1F, 0xFD,
+	0x95, 0x6D, 0x17, 0xFF, 0x00, 0x44, 0xDE, 0x57, 0xE0, 0x0F, 0xFC, 0x10, 0xE3, 0xFE, 0x52, 0xF9,
+	0xFB, 0x3A, 0xFF, 0x00, 0xD9, 0x54, 0xD2, 0xFF, 0x00, 0xF4, 0x6D, 0x7E, 0xFF, 0x00, 0x7F, 0xC1,
+	0xE2, 0x6A, 0xCD, 0xFF, 0x00, 0x04, 0x84, 0x42, 0x17, 0xEE, 0xFC, 0x55, 0xD1, 0x09, 0xF6, 0xFD,
+	0xD5, 0xDD, 0x7E, 0x00, 0xFF, 0x00, 0xC1, 0x0E, 0xDD, 0x53, 0xFE, 0x0A, 0xF7, 0xFB, 0x3A, 0x97,
+	0x6C, 0x7F, 0xC5, 0xD6, 0xD2, 0x87, 0x3E, 0xF3, 0x01, 0x40, 0x1F, 0xDA, 0x95, 0x14, 0x51, 0x40,
+	0x1F, 0x8D, 0xBF, 0xF0, 0x76, 0x87, 0xFC, 0x15, 0xDF, 0xC6, 0x5F, 0xB2, 0x47, 0xC2, 0x1D, 0x27,
+	0xF6, 0x11, 0xFD, 0x9E, 0x3C, 0x61, 0x75, 0xA3, 0xF8, 0xDB, 0xE2, 0x46, 0x98, 0xD7, 0xDE, 0x2A,
+	0xD6, 0xB4, 0xDB, 0x8F, 0x2E, 0xE7, 0x4C, 0xD0, 0x7C, 0xC6, 0x8C, 0x45, 0x1B, 0xAB, 0x06, 0x8D,
+	0xEE, 0x64, 0x49, 0x13, 0x70, 0x1F, 0xEA, 0xE2, 0x94, 0x64, 0x16, 0x15, 0xFC, 0xE7, 0xFE, 0xCD,
+	0xDF, 0xB3, 0x57, 0xC7, 0x0F, 0xDA, 0xEB, 0xE3, 0x1E, 0x8F, 0xF0, 0x0B, 0xF6, 0x75, 0xF8, 0x79,
+	0x7D, 0xE2, 0x8F, 0x15, 0xEB, 0x93, 0x32, 0x58, 0x69, 0x76, 0x2A, 0x33, 0xB5, 0x46, 0xE7, 0x91,
+	0xD8, 0x90, 0xB1, 0xC6, 0xAA, 0x0B, 0x33, 0xB1, 0x0A, 0x07, 0x53, 0x5F, 0x5D, 0x7F, 0xC1, 0xCD,
+	0x7F, 0x11, 0x35, 0x5F, 0x88, 0xBF, 0xF0, 0x5B, 0x4F, 0x8D, 0x52, 0xDF, 0xEA, 0x32, 0x4D, 0x6F,
+	0xA2, 0xDD, 0xE9, 0x3A, 0x46, 0x9D, 0x0B, 0x4C, 0x59, 0x6D, 0xA2, 0xB7, 0xD2, 0x6C, 0xD5, 0x91,
+	0x33, 0xF7, 0x41, 0x97, 0xCD, 0x90, 0xA8, 0xE3, 0x74, 0x8C, 0x7A, 0x93, 0x5F, 0xA7, 0xDF, 0xF0,
+	0x65, 0x0F, 0xEC, 0xD7, 0xE0, 0x2D, 0x37, 0xE0, 0x07, 0xC5, 0x3F, 0xDA, 0xC2, 0xF3, 0xC3, 0xF6,
+	0xD2, 0xF8, 0xA3, 0x54, 0xF1, 0x44, 0x7E, 0x1D, 0xB3, 0xD5, 0x24, 0x4D, 0xD2, 0xDB, 0xE9, 0xF0,
+	0xC3, 0x1C, 0xCF, 0x12, 0x13, 0xF7, 0x03, 0xCB, 0x20, 0x66, 0xDB, 0x8D, 0xDE, 0x5A, 0x67, 0x3B,
+	0x57, 0x00, 0x1E, 0x09, 0xFB, 0x35, 0x7F, 0xC1, 0x94, 0xFF, 0x00, 0xB5, 0x7E, 0xB5, 0xAF, 0x78,
+	0x7B, 0x5C, 0xFD, 0xAA, 0xBF, 0x69, 0x6F, 0x02, 0xE8, 0x3A, 0x33, 0xDF, 0x43, 0x2F, 0x88, 0xB4,
+	0x3F, 0x0A, 0x35, 0xDD, 0xF5, 0xFA, 0xDA, 0x70, 0xCF, 0x0A, 0x4B, 0x24, 0x31, 0x44, 0xB3, 0x1E,
+	0x53, 0x20, 0xBA, 0x29, 0x3B, 0x81, 0x7C, 0x60, 0xFF, 0x00, 0x41, 0x7F, 0xB3, 0x5F, 0xEC, 0xD7,
+	0xF0, 0x4F, 0xF6, 0x43, 0xF8, 0x27, 0xA0, 0xFE, 0xCF, 0x3F, 0xB3, 0xC7, 0x80, 0x6C, 0xBC, 0x37,
+	0xE1, 0x3F, 0x0D, 0xD9, 0xF9, 0x1A, 0x6E, 0x99, 0x63, 0x1E, 0x3A, 0x9D, 0xCF, 0x2C, 0x8D, 0xD6,
+	0x49, 0x64, 0x72, 0xCE, 0xF2, 0x31, 0x2C, 0xEE, 0xCC, 0xCC, 0x49, 0x35, 0xDD, 0x51, 0x40, 0x05,
+	0x14, 0x51, 0x40, 0x1F, 0x19, 0xFF, 0x00, 0xC1, 0x7F, 0xFF, 0x00, 0x63, 0x9F, 0x14, 0x7E, 0xDC,
+	0x5F, 0xF0, 0x4A, 0x3F, 0x8A, 0x5F, 0x07, 0xBE, 0x1E, 0xE9, 0xDF, 0x6A, 0xF1, 0x46, 0x9F, 0x63,
+	0x6F, 0xE2, 0x1F, 0x0C, 0xDB, 0x6D, 0x25, 0xA7, 0xBA, 0xD3, 0xE7, 0x4B, 0x97, 0x81, 0x07, 0x79,
+	0x25, 0x81, 0x27, 0x85, 0x32, 0x40, 0x0F, 0x2A, 0x92, 0x70, 0x0D, 0x7F, 0x1E, 0x1F, 0x0B, 0x3E,
+	0x25, 0x78, 0xD3, 0xE0, 0x87, 0xC5, 0x2D, 0x03, 0xE2, 0xD7, 0x80, 0xB5, 0x09, 0x2C, 0x35, 0xFF,
+	0x00, 0x0A, 0xEB, 0x56, 0xFA, 0x9E, 0x97, 0x71, 0xF3, 0x29, 0x8A, 0xE6, 0x09, 0x56, 0x44, 0xCE,
+	0x08, 0x38, 0xDC, 0xB8, 0x23, 0x23, 0x23, 0x22, 0xBF, 0xBD, 0xB3, 0xCF, 0x04, 0x57, 0xF3, 0xE5,
+	0xFF, 0x00, 0x05, 0xFD, 0xFF, 0x00, 0x83, 0x5F, 0xFE, 0x26, 0xEB, 0x5F, 0x13, 0x35, 0xFF, 0x00,
+	0xDB, 0x5B, 0xFE, 0x09, 0xB7, 0xE0, 0xC8, 0x75, 0x8B, 0x3D, 0x76, 0xE9, 0xAF, 0xBC, 0x5F, 0xF0,
+	0xB3, 0x4F, 0x09, 0x0D, 0xCD, 0xA5, 0xD3, 0x9F, 0xDE, 0xDD, 0x69, 0xCB, 0xC2, 0xC9, 0x13, 0xB6,
+	0x64, 0x78, 0x32, 0x1D, 0x59, 0x98, 0xA0, 0x65, 0x3B, 0x50, 0x03, 0xF4, 0x8B, 0xFE, 0x09, 0x73,
+	0xFF, 0x00, 0x05, 0xFB, 0xFD, 0x86, 0x3F, 0xE0, 0xA2, 0xBF, 0x08, 0x74, 0x7B, 0xCD, 0x53, 0xE2,
+	0xCE, 0x83, 0xE0, 0x3F, 0x89, 0x4B, 0x62, 0x17, 0xC5, 0x1E, 0x01, 0xF1, 0x36, 0xAD, 0x1D, 0xAC,
+	0xD0, 0xDC, 0xA2, 0x8F, 0x36, 0x4B, 0x59, 0x25, 0x2A, 0xB7, 0x36, 0xEC, 0x7E, 0x64, 0x75, 0x3B,
+	0x80, 0x60, 0x1D, 0x51, 0xB2, 0xB5, 0xB3, 0xFF, 0x00, 0x05, 0x23, 0xFF, 0x00, 0x82, 0xEF, 0x7E,
+	0xC0, 0x9F, 0xF0, 0x4E, 0x8F, 0x84, 0xDA, 0x97, 0x89, 0xB5, 0xFF, 0x00, 0x8C, 0x3A, 0x3F, 0x8C,
+	0xBC, 0x66, 0x6D, 0xB6, 0xF8, 0x6F, 0xE1, 0xFF, 0x00, 0x84, 0x75, 0x28, 0xAF, 0x2F, 0x75, 0x0B,
+	0x87, 0x1F, 0xBB, 0x32, 0x14, 0x62, 0x96, 0xD6, 0xEB, 0xF7, 0xA4, 0x9A, 0x46, 0x18, 0x55, 0x21,
+	0x04, 0x92, 0x14, 0x8D, 0xFF, 0x00, 0x8E, 0x7F, 0x17, 0xF8, 0x37, 0xC6, 0x1F, 0x0F, 0x7C, 0x4B,
+	0x79, 0xE0, 0xCF, 0x1F, 0x78, 0x53, 0x52, 0xD0, 0xF5, 0x8D, 0x3E, 0x4F, 0x2E, 0xFF, 0x00, 0x49,
+	0xD6, 0x2C, 0x64, 0xB6, 0xB9, 0xB6, 0x7C, 0x03, 0xB6, 0x48, 0xA4, 0x01, 0x90, 0xE0, 0x83, 0x82,
+	0x01, 0xC1, 0xA8, 0xFC, 0x33, 0xE1, 0x7F, 0x13, 0x78, 0xD7, 0x5F, 0xB4, 0xF0, 0xA7, 0x83, 0x7C,
+	0x3B, 0x7D, 0xAB, 0x6A, 0x97, 0xF3, 0x08, 0x6C, 0x74, 0xDD, 0x32, 0xCD, 0xEE, 0x2E, 0x2E, 0x64,
+	0x3D, 0x12, 0x38, 0xD0, 0x16, 0x76, 0x3E, 0x80, 0x13, 0x40, 0x1D, 0x37, 0xED, 0x1B, 0xF1, 0xDF,
+	0xC7, 0x5F, 0xB4, 0xFF, 0x00, 0xC7, 0xAF, 0x18, 0x7E, 0xD1, 0x1F, 0x13, 0x2F, 0x04, 0xFA, 0xF7,
+	0x8D, 0x3C, 0x43, 0x75, 0xAB, 0xEA, 0x8E, 0xBF, 0x75, 0x65, 0x9A, 0x42, 0xFB, 0x17, 0xFD, 0x95,
+	0x04, 0x28, 0xF6, 0x51, 0x5F, 0xD6, 0x77, 0xFC, 0x1B, 0x45, 0xFB, 0x20, 0x78, 0xAF, 0xF6, 0x3C,
+	0xFF, 0x00, 0x82, 0x48, 0xF8, 0x07, 0x43, 0xF8, 0x89, 0xA4, 0x49, 0xA7, 0xF8, 0x93, 0xC6, 0xD7,
+	0x17, 0x5E, 0x2D, 0xD5, 0xAC, 0x27, 0x84, 0xA4, 0x96, 0xAB, 0x78, 0xE3, 0xEC, 0xB1, 0x38, 0x20,
+	0x30, 0x6F, 0xB2, 0x47, 0x6E, 0xCC, 0xAC, 0x01, 0x47, 0x77, 0x5E, 0xD9, 0x3F, 0x98, 0x3F, 0xF0,
+	0x41, 0x9F, 0xF8, 0x35, 0xDF, 0xE2, 0xEF, 0x8C, 0xBE, 0x26, 0xF8, 0x7F, 0xF6, 0xBD, 0xFF, 0x00,
+	0x82, 0x90, 0xF8, 0x1B, 0xFE, 0x11, 0xEF, 0x07, 0xE8, 0xF3, 0x47, 0xA8, 0x78, 0x77, 0xE1, 0xAE,
+	0xA5, 0xFF, 0x00, 0x1F, 0xFA, 0xDD, 0xC2, 0x9C, 0xC5, 0x25, 0xF4, 0x78, 0xFD, 0xC5, 0xAA, 0x90,
+	0xAF, 0xE5, 0x93, 0xE6, 0x4B, 0xC0, 0x60, 0x89, 0x9D, 0xFF, 0x00, 0xD1, 0xB4, 0x30, 0xC3, 0x6D,
+	0x0A, 0xDB, 0xDB, 0xC2, 0xB1, 0xC7, 0x1A, 0x85, 0x8E, 0x34, 0x5C, 0x2A, 0xA8, 0x1C, 0x00, 0x07,
+	0x41, 0x40, 0x0E, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x00, 0xA2, 0x8A, 0x28, 0x03, 0x81,
+	0xF8, 0xCB, 0xFB, 0x29, 0xFE, 0xCB, 0xBF, 0xB4, 0x64, 0x31, 0x5B, 0xFE, 0xD0, 0x7F, 0xB3, 0x6F,
+	0x80, 0x7C, 0x77, 0x1C, 0x0D, 0x98, 0x63, 0xF1, 0x97, 0x83, 0xAC, 0xB5, 0x45, 0x8C, 0xE7, 0x39,
+	0x51, 0x73, 0x13, 0xE3, 0xF0, 0xA8, 0x7E, 0x0D, 0x7E, 0xC8, 0x3F, 0xB2, 0x67, 0xEC, 0xE7, 0x2C,
+	0xF3, 0xFE, 0xCF, 0x7F, 0xB2, 0xEF, 0xC3, 0xBF, 0x01, 0xC9, 0x75, 0xCD, 0xCB, 0xF8, 0x37, 0xC1,
+	0x36, 0x1A, 0x59, 0x97, 0xA7, 0xDE, 0x36, 0xD1, 0x26, 0xEE, 0x83, 0xAF, 0xA5, 0x14, 0x50, 0x07,
+	0xA2, 0x51, 0x45, 0x14, 0x00, 0x51, 0x45, 0x14, 0x01, 0xFF, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60,
+	0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x22, 0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D,
+	0x00, 0x2A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x01, 0x12, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x02, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x04, 0x03, 0x02, 0x02,
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+	0xF3, 0xE3, 0x6A, 0x59, 0x5A, 0xDC, 0xC8, 0x24, 0xDB, 0xBF, 0x0C, 0x50, 0x2E, 0xDD, 0xC0, 0xB0,
+	0x25, 0x43, 0x77, 0x3F, 0xF0, 0x86, 0x7E, 0xC5, 0x3F, 0xF3, 0xC7, 0xE0, 0x3F, 0xFE, 0x11, 0x3E,
+	0x27, 0xFF, 0x00, 0xE5, 0x1D, 0x7F, 0xA1, 0x87, 0xE1, 0x27, 0xE8, 0xAF, 0xC3, 0x3F, 0xF8, 0x2C,
+	0x37, 0xEC, 0xB1, 0xF1, 0x63, 0xE2, 0x1E, 0x87, 0xF0, 0xCB, 0xC2, 0x7E, 0x1C, 0xF1, 0xA3, 0x6A,
+	0x5A, 0xFE, 0xAD, 0x6F, 0xA7, 0xD9, 0xB4, 0xDA, 0x4D, 0xB7, 0x96, 0x92, 0x4D, 0x22, 0xC6, 0xAC,
+	0xE5, 0x6E, 0x58, 0x84, 0x05, 0x81, 0x62, 0x01, 0xC0, 0x04, 0xE0, 0xD7, 0xD5, 0x95, 0xF9, 0xB3,
+	0xFF, 0x00, 0x04, 0xF1, 0xD6, 0xFF, 0x00, 0xE0, 0x98, 0x7F, 0x07, 0x7E, 0x20, 0xDB, 0xF8, 0x83,
+	0xFE, 0x16, 0x07, 0xC3, 0xEB, 0x0F, 0x18, 0x6A, 0x36, 0xE6, 0x0B, 0x6F, 0xEC, 0xDF, 0x01, 0x5F,
+	0xE9, 0x76, 0x36, 0x65, 0x59, 0xA4, 0x25, 0xB5, 0x1B, 0xFB, 0x58, 0x41, 0xC8, 0x48, 0xCA, 0x86,
+	0xF2, 0x57, 0xCC, 0x00, 0x62, 0x47, 0x11, 0x15, 0xFB, 0xAF, 0xFE, 0x1A, 0x93, 0xF6, 0x65, 0xFF,
+	0x00, 0xA3, 0x8B, 0xF0, 0x27, 0xFE, 0x15, 0xD6, 0x5F, 0xFC, 0x76, 0x80, 0x3B, 0xBA, 0x2B, 0x99,
+	0xF0, 0x77, 0xC6, 0x8F, 0x83, 0xBF, 0x10, 0xF5, 0x47, 0xD0, 0xFC, 0x01, 0xF1, 0x63, 0xC3, 0x3A,
+	0xE5, 0xEC, 0x70, 0x19, 0xA4, 0xB3, 0xD1, 0xF5, 0xEB, 0x7B, 0xA9, 0x56, 0x30, 0x40, 0x2E, 0x52,
+	0x37, 0x24, 0x28, 0x2C, 0xA3, 0x38, 0xC6, 0x58, 0x7A, 0x8A, 0xE9, 0xA8, 0x03, 0xF0, 0xCF, 0xFE,
+	0x0A, 0x5D, 0xAB, 0xFF, 0x00, 0xC1, 0x4C, 0xAD, 0xFF, 0x00, 0x6C, 0x6F, 0x1C, 0xC3, 0xE2, 0x1B,
+	0xCF, 0x8A, 0x96, 0xFA, 0x18, 0xF1, 0x25, 0xDF, 0xFC, 0x21, 0xD1, 0xE8, 0xB2, 0xDF, 0x2E, 0x98,
+	0x74, 0xBD, 0xC3, 0xEC, 0xCD, 0x6D, 0xF6, 0x63, 0xE4, 0xF3, 0x00, 0x87, 0xCC, 0xDB, 0xF3, 0x79,
+	0x9B, 0xBC, 0xCF, 0xDE, 0x07, 0x15, 0xE0, 0x7F, 0xDB, 0xBF, 0xB7, 0xD7, 0xFD, 0x06, 0x7E, 0x30,
+	0x7F, 0xE0, 0x46, 0xAB, 0xFE, 0x35, 0xFD, 0x24, 0x51, 0x40, 0x1F, 0xCD, 0xBF, 0xF6, 0xEF, 0xED,
+	0xF5, 0xFF, 0x00, 0x41, 0x9F, 0x8C, 0x1F, 0xF8, 0x11, 0xAA, 0xFF, 0x00, 0x8D, 0x1F, 0xDB, 0xBF,
+	0xB7, 0xD7, 0xFD, 0x06, 0x7E, 0x30, 0x7F, 0xE0, 0x46, 0xAB, 0xFE, 0x35, 0xFD, 0x24, 0x51, 0x40,
+	0x1F, 0xCD, 0xBF, 0xF6, 0xEF, 0xED, 0xF5, 0xFF, 0x00, 0x41, 0x9F, 0x8C, 0x1F, 0xF8, 0x11, 0xAA,
+	0xFF, 0x00, 0x8D, 0x4B, 0x61, 0xAD, 0xFE, 0xDC, 0x52, 0x5F, 0x43, 0x1F, 0x88, 0x75, 0x6F, 0x8A,
+	0xCD, 0xA7, 0xB4, 0xCA, 0x2F, 0x96, 0xF2, 0xE3, 0x53, 0xF2, 0x4C, 0x39, 0xF9, 0xF7, 0xEE, 0x3B,
+	0x76, 0x6D, 0xCE, 0x73, 0xC6, 0x33, 0x9A, 0xFE, 0x90, 0xEA, 0x1D, 0x47, 0x4E, 0xD3, 0xF5, 0x8D,
+	0x3E, 0xE3, 0x49, 0xD5, 0xAC, 0x21, 0xBA, 0xB5, 0xBA, 0x85, 0xA1, 0xBA, 0xB5, 0xB8, 0x88, 0x3C,
+	0x73, 0x46, 0xC3, 0x0C, 0x8C, 0xA7, 0x21, 0x94, 0x82, 0x41, 0x07, 0x82, 0x0D, 0x73, 0xE2, 0xA8,
+	0xBC, 0x46, 0x16, 0x74, 0x93, 0xB7, 0x34, 0x5A, 0xFB, 0xD5, 0x8D, 0x29, 0xCB, 0xD9, 0xD4, 0x8C,
+	0xBB, 0x34, 0xCF, 0x8A, 0x7E, 0x10, 0x7F, 0x60, 0x7F, 0xC2, 0x35, 0x3F, 0xF6, 0xAF, 0xFA, 0xCF,
+	0xB7, 0x36, 0xDE, 0x9F, 0x77, 0x62, 0x7F, 0xF5, 0xE8, 0xD2, 0x7F, 0xB0, 0x3F, 0xE1, 0x6D, 0x6A,
+	0x9E, 0x6F, 0xFC, 0x7A, 0xFD, 0x85, 0x7C, 0xBE, 0x9F, 0x7B, 0x10, 0xFF, 0x00, 0xF5, 0xEB, 0xE9,
+	0x2F, 0x19, 0x7E, 0xCA, 0x9F, 0x0B, 0x7C, 0x5F, 0xAA, 0x47, 0xA9, 0x5B, 0x47, 0x75, 0xA1, 0xAC,
+	0x76, 0xE2, 0x2F, 0xB2, 0xE8, 0x11, 0xDB, 0xDB, 0xC2, 0xE4, 0x33, 0x1D, 0xE5, 0x7C, 0xA3, 0x97,
+	0x39, 0xC1, 0x39, 0xE8, 0xAB, 0xE9, 0x45, 0xE7, 0xEC, 0xA9, 0xF0, 0xB6, 0xEF, 0xC2, 0x16, 0xBE,
+	0x13, 0x58, 0xEE, 0xA1, 0x92, 0xD6, 0xE0, 0xCA, 0xDA, 0xD5, 0xBC, 0x76, 0xEB, 0x7D, 0x70, 0x09,
+	0x7F, 0x92, 0x49, 0x7C, 0xAF, 0x99, 0x06, 0xFE, 0x98, 0x1F, 0x71, 0x3D, 0x2B, 0xF8, 0xC6, 0x3E,
+	0x01, 0xF1, 0xCD, 0x0A, 0x74, 0xF0, 0xB1, 0x8D, 0x19, 0x47, 0x0E, 0xF9, 0xA3, 0x3B, 0xDB, 0xDA,
+	0xB5, 0x74, 0xA2, 0xD6, 0xF1, 0xBA, 0x93, 0x77, 0x7A, 0x7B, 0xB6, 0xEA, 0x8F, 0xD6, 0xBF, 0xD7,
+	0x6C, 0x9A, 0x72, 0x75, 0x1B, 0x9A, 0x75, 0x34, 0x6A, 0xDF, 0x0D, 0xF5, 0xBD, 0xFA, 0xDA, 0xD6,
+	0xD3, 0xB9, 0xF2, 0xD7, 0xC4, 0xAF, 0xF8, 0x47, 0xBF, 0xE1, 0x6A, 0xF8, 0x37, 0xEC, 0x3F, 0x73,
+	0xCB, 0xBB, 0xF3, 0xFA, 0x7D, 0xDF, 0x3E, 0xCB, 0xFF, 0x00, 0xAF, 0x5D, 0x5C, 0x1F, 0xF0, 0x8E,
+	0x7F, 0xC2, 0xD3, 0xD2, 0xFE, 0xC5, 0xFF, 0x00, 0x42, 0xFE, 0xA3, 0xBB, 0xA7, 0xFC, 0xF7, 0xB1,
+	0xC5, 0x7B, 0x66, 0x8D, 0xFB, 0x1B, 0x7C, 0x27, 0xD2, 0x35, 0x39, 0xF5, 0x6B, 0x8B, 0xBD, 0x53,
+	0x50, 0x9A, 0x5D, 0x26, 0xE2, 0xC2, 0x16, 0xD4, 0x8D, 0xB4, 0xBF, 0x65, 0x13, 0x34, 0x64, 0xCD,
+	0x17, 0xEE, 0x46, 0xC9, 0x54, 0xC4, 0xBB, 0x5B, 0xB6, 0x4F, 0x07, 0xB7, 0x9F, 0x7C, 0x55, 0xFD,
+	0x9A, 0x2E, 0x3E, 0x18, 0xF8, 0x8F, 0x49, 0xF1, 0x87, 0xC3, 0xDB, 0x3F, 0x11, 0x6B, 0x56, 0xEB,
+	0xA6, 0xDE, 0xDB, 0x6A, 0x59, 0x55, 0xB9, 0x92, 0x16, 0x79, 0x2D, 0x5A, 0x2D, 0xB1, 0xC3, 0x18,
+	0x90, 0xE7, 0x64, 0x99, 0x20, 0x30, 0x1B, 0x79, 0xC6, 0x46, 0x6A, 0xB7, 0x85, 0x7C, 0x71, 0x90,
+	0xD3, 0x96, 0x67, 0x5B, 0x0D, 0x4E, 0x69, 0xAB, 0xCE, 0x30, 0x7C, 0xD2, 0x85, 0xBD, 0xD5, 0xCA,
+	0x92, 0xBC, 0xAF, 0x75, 0x27, 0x6D, 0x95, 0xEF, 0xB0, 0xA9, 0xF1, 0x2E, 0x4F, 0x8C, 0x92, 0xC3,
+	0xC6, 0xA4, 0x93, 0x5A, 0x27, 0x2D, 0x13, 0xBE, 0xBA, 0xB7, 0xB5, 0xB6, 0xD7, 0x73, 0x98, 0xF8,
+	0xD7, 0xFD, 0x99, 0xFF, 0x00, 0x0A, 0xA7, 0x5C, 0xDB, 0x9F, 0xF8, 0xF1, 0x3F, 0xCC, 0x57, 0x90,
+	0xFE, 0xC9, 0x3F, 0xD9, 0xFF, 0x00, 0xF0, 0xB1, 0xEF, 0x77, 0xFF, 0x00, 0xD0, 0x12, 0x4F, 0xFD,
+	0x1D, 0x0D, 0x7A, 0x27, 0xC4, 0x8B, 0x7B, 0xED, 0x57, 0x47, 0xB8, 0xF8, 0x7D, 0xAB, 0xC7, 0x75,
+	0xA6, 0xEA, 0x1A, 0xA5, 0xB6, 0xD8, 0x6D, 0x2E, 0x2C, 0x5C, 0x5C, 0xB0, 0x24, 0x1C, 0xAC, 0x07,
+	0x0E, 0xE7, 0xD1, 0x40, 0xC9, 0x3C, 0x56, 0x2F, 0x86, 0x7F, 0x67, 0xDF, 0x11, 0xFE, 0xCF, 0x5E,
+	0x2E, 0xFE, 0xD3, 0xF1, 0x34, 0x57, 0xF6, 0x92, 0x5F, 0x69, 0xF2, 0xC3, 0x05, 0xBD, 0xF7, 0x90,
+	0xDE, 0x6A, 0x89, 0x23, 0x26, 0x45, 0x78, 0x64, 0x75, 0xE3, 0x00, 0x15, 0x3F, 0x30, 0xDC, 0xA4,
+	0x80, 0x08, 0xCF, 0x9B, 0x87, 0xCC, 0x2B, 0x53, 0xCA, 0x71, 0x33, 0x9E, 0x1E, 0x49, 0x53, 0x6B,
+	0x99, 0xF2, 0x4A, 0xD1, 0xE6, 0xB2, 0x5C, 0xCE, 0xD6, 0x8D, 0xDE, 0xD7, 0xB5, 0xCE, 0x99, 0xD0,
+	0x8C, 0xB1, 0x54, 0xD2, 0xA8, 0xAF, 0x2D, 0xB5, 0x57, 0x76, 0xDE, 0xCA, 0xFA, 0xDB, 0xC8, 0xF5,
+	0xDF, 0xF8, 0x95, 0xFB, 0xD1, 0xFF, 0x00, 0x12, 0xBF, 0x7A, 0xE3, 0x3F, 0xE1, 0x28, 0x1F, 0xF3,
+	0xD2, 0x8F, 0xF8, 0x4A, 0x07, 0xFC, 0xF4, 0xAF, 0x9A, 0xFF, 0x00, 0x58, 0xB0, 0x7F, 0xCA, 0x8F,
+	0x43, 0xEA, 0x15, 0x7B, 0xB3, 0x85, 0xF1, 0xAF, 0xF6, 0x77, 0xFC, 0x35, 0x5E, 0x93, 0x8F, 0xBB,
+	0xFE, 0x8F, 0xFF, 0x00, 0xA0, 0xB5, 0x62, 0xFC, 0x33, 0xFE, 0xCF, 0xFF, 0x00, 0x8B, 0x91, 0x9F,
+	0xFA, 0x02, 0x5E, 0x6D, 0xFF, 0x00, 0xC8, 0x95, 0x99, 0xE3, 0x3F, 0x11, 0x83, 0xFB, 0x51, 0xE9,
+	0x32, 0x6F, 0xFF, 0x00, 0x9E, 0x1D, 0xFF, 0x00, 0xD9, 0x6A, 0xC5, 0xF8, 0x6D, 0xE2, 0x2D, 0xBF,
+	0xF0, 0xB1, 0x3E, 0x7F, 0xBD, 0xA2, 0xDE, 0x77, 0xFF, 0x00, 0xAE, 0x95, 0xF4, 0xB1, 0xCF, 0x70,
+	0xBF, 0x55, 0x4E, 0xCB, 0xE0, 0x87, 0xFE, 0x94, 0x79, 0xDF, 0x52, 0xA9, 0xED, 0x1E, 0xFB, 0xBF,
+	0xC8, 0xF6, 0x3F, 0xD9, 0x27, 0xFB, 0x3B, 0xFE, 0x15, 0xC5, 0xEE, 0xFF, 0x00, 0xFA, 0x0D, 0xC9,
+	0xFF, 0x00, 0xA2, 0x61, 0xAF, 0x51, 0xFF, 0x00, 0x89, 0x5F, 0xBD, 0x7C, 0xFF, 0x00, 0xFB, 0x29,
+	0x78, 0x90, 0x47, 0xF0, 0xEE, 0xF1, 0x4B, 0xFF, 0x00, 0xCC, 0x6A, 0x4F, 0xFD, 0x13, 0x0D, 0x7A,
+	0x6F, 0xFC, 0x25, 0x03, 0xFE, 0x7A, 0x57, 0x8F, 0x98, 0x71, 0x06, 0x12, 0x38, 0xE9, 0xAE, 0x55,
+	0xB9, 0xD7, 0x87, 0xC0, 0xD5, 0x74, 0x62, 0xEE, 0xCE, 0xCF, 0xFE, 0x25, 0x7E, 0xF4, 0x7F, 0xC4,
+	0xAF, 0xDE, 0xB8, 0xCF, 0xF8, 0x4A, 0x07, 0xFC, 0xF4, 0xA3, 0xFE, 0x12, 0x81, 0xFF, 0x00, 0x3D,
+	0x2B, 0x8B, 0xFD, 0x62, 0xC1, 0xFF, 0x00, 0x2A, 0x36, 0xFA, 0x85, 0x5E, 0xEC, 0xEC, 0xFF, 0x00,
+	0xE2, 0x57, 0xEF, 0x5E, 0x05, 0xFF, 0x00, 0x05, 0x18, 0xFE, 0xCA, 0xFF, 0x00, 0x85, 0x21, 0xA6,
+	0x6E, 0xFB, 0xBF, 0xF0, 0x94, 0xC1, 0xBB, 0xA7, 0xFC, 0xFB, 0x5C, 0xD7, 0xA5, 0x7F, 0xC2, 0x50,
+	0x3F, 0xE7, 0xA5, 0x7C, 0xCF, 0xFF, 0x00, 0x05, 0x5C, 0xF8, 0xA9, 0x17, 0x82, 0x3F, 0x66, 0x0B,
+	0x7F, 0x12, 0xCB, 0x0C, 0x93, 0x2D, 0xBF, 0x8A, 0xAD, 0x07, 0x97, 0x1A, 0x92, 0x4E, 0xE8, 0xA7,
+	0x5E, 0xDF, 0x5A, 0xFA, 0x7E, 0x09, 0xCF, 0x30, 0xB8, 0x8E, 0x2E, 0xC0, 0x53, 0x8A, 0x57, 0x75,
+	0xA9, 0xAF, 0xFC, 0x99, 0x1E, 0x6E, 0x71, 0x83, 0xA9, 0x4F, 0x2A, 0xAF, 0x26, 0xDE, 0x90, 0x97,
+	0xE4, 0x78, 0xEF, 0x81, 0x3E, 0x26, 0xFC, 0x0D, 0xF8, 0x53, 0x69, 0x7D, 0xE2, 0x2F, 0x8C, 0x1A,
+	0x56, 0xA5, 0x79, 0xA6, 0x4D, 0x24, 0x36, 0xD0, 0xC7, 0xA5, 0xD9, 0x79, 0xF2, 0x09, 0xC8, 0x91,
+	0x94, 0x95, 0x1D, 0x17, 0x6A, 0x3F, 0x3E, 0xA4, 0x7A, 0xD6, 0xE7, 0xFC, 0x36, 0x6F, 0xFC, 0x13,
+	0xF3, 0xFE, 0x84, 0x8F, 0x18, 0x7F, 0xE1, 0x38, 0xD5, 0xE0, 0x3F, 0xB2, 0x0F, 0xC6, 0xAD, 0x0B,
+	0xE3, 0x97, 0x8A, 0xB5, 0x6F, 0x06, 0xDF, 0x78, 0x17, 0x40, 0xBE, 0x58, 0x34, 0xF5, 0xBD, 0x11,
+	0xF8, 0xC2, 0xF3, 0x51, 0xB5, 0xB5, 0x52, 0x8E, 0x13, 0x2A, 0xF6, 0x57, 0x56, 0xB2, 0x19, 0x3F,
+	0x7B, 0xC2, 0x99, 0x0A, 0x95, 0x2C, 0x4A, 0x12, 0x15, 0x97, 0xDF, 0xBF, 0xE1, 0x5D, 0x78, 0x3B,
+	0xFE, 0x88, 0xE7, 0xC1, 0x9F, 0xFC, 0x2A, 0xBC, 0x53, 0xFF, 0x00, 0xCB, 0xEA, 0xFE, 0xE4, 0x3F,
+	0x1B, 0x2D, 0x68, 0x7F, 0xB5, 0x9F, 0xEC, 0x1F, 0xE2, 0x3D, 0x5E, 0xDF, 0x42, 0xD1, 0xBE, 0x1F,
+	0xF8, 0xC2, 0x6B, 0xAB, 0xA9, 0x44, 0x70, 0xC7, 0xFF, 0x00, 0x08, 0xF9, 0x50, 0x58, 0xF7, 0x2C,
+	0xD8, 0x55, 0x03, 0xA9, 0x62, 0x40, 0x00, 0x12, 0x48, 0x00, 0x9A, 0xE7, 0xFC, 0x67, 0xF1, 0xCB,
+	0xF6, 0x03, 0xF0, 0xDF, 0x8A, 0x6F, 0x74, 0x3B, 0x6F, 0x82, 0xDE, 0x35, 0xD4, 0x96, 0xDE, 0x6D,
+	0xA6, 0xFB, 0x49, 0xD1, 0x63, 0x7B, 0x69, 0x1B, 0x00, 0xB7, 0x96, 0xCC, 0xEB, 0xB9, 0x41, 0x25,
+	0x72, 0x06, 0xD3, 0x8F, 0x97, 0x2B, 0x82, 0x7E, 0xAC, 0xFD, 0x82, 0xFE, 0x0E, 0xFE, 0xC3, 0x3E,
+	0x32, 0xF1, 0xA5, 0x9E, 0x99, 0xE3, 0xDF, 0xD9, 0xD3, 0xC2, 0x90, 0x78, 0xB2, 0xCE, 0x13, 0x25,
+	0x9D, 0xDD, 0x9F, 0x8D, 0x35, 0x1D, 0x53, 0x4C, 0xBE, 0x91, 0x8B, 0x21, 0x56, 0xB1, 0xBE, 0xBA,
+	0x99, 0x63, 0x21, 0x5D, 0x02, 0x79, 0x86, 0x65, 0x2F, 0xC8, 0x64, 0x7F, 0x2D, 0x5B, 0xED, 0x7F,
+	0xF8, 0x65, 0xCF, 0xD9, 0x97, 0xFE, 0x8D, 0xD3, 0xC0, 0x9F, 0xF8, 0x48, 0xD9, 0x7F, 0xF1, 0xAA,
+	0x00, 0xFC, 0x9C, 0xFD, 0x9E, 0xBE, 0x38, 0xFE, 0xCC, 0xDE, 0x24, 0xF8, 0xCB, 0xA0, 0xE8, 0xFF,
+	0x00, 0x02, 0xBE, 0x07, 0xFC, 0x50, 0xB1, 0xF1, 0x5C, 0xD7, 0x98, 0xD1, 0xEF, 0x2C, 0x74, 0xD8,
+	0xA0, 0x96, 0x26, 0xDA, 0x77, 0x30, 0x65, 0x97, 0x76, 0x02, 0x6E, 0xDC, 0x14, 0x12, 0x57, 0x70,
+	0xC1, 0x19, 0x15, 0xFB, 0x1D, 0xE1, 0x2F, 0xF8, 0x48, 0xFF, 0x00, 0xE1, 0x14, 0xD3, 0x3F, 0xE1,
+	0x30, 0x10, 0xFF, 0x00, 0x6B, 0x7F, 0x67, 0xC3, 0xFD, 0xA9, 0xF6, 0x7F, 0xF5, 0x7F, 0x69, 0xF2,
+	0xC7, 0x99, 0xB7, 0xFD, 0x9D, 0xFB, 0xB1, 0xED, 0x59, 0x3E, 0x0F, 0xF8, 0x2F, 0xF0, 0x77, 0xE1,
+	0xE6, 0xA8, 0xDA, 0xE7, 0x80, 0x3E, 0x13, 0x78, 0x67, 0x43, 0xBD, 0x92, 0x13, 0x0C, 0x97, 0x9A,
+	0x3E, 0x83, 0x6F, 0x6B, 0x2B, 0x46, 0x48, 0x25, 0x0B, 0xC6, 0x80, 0x95, 0x25, 0x54, 0xE3, 0x38,
+	0xC8, 0x1E, 0x95, 0xD3, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14,
+	0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x45, 0x14, 0x50, 0x01, 0x58, 0x7E, 0x3B, 0xF8, 0x71, 0xE1,
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+	0xA1, 0x7F, 0xB3, 0xD6, 0xB1, 0xE3, 0x9F, 0xDA, 0x9F, 0xC5, 0x56, 0x3A, 0xB6, 0xA1, 0x69, 0xA9,
+	0x49, 0x15, 0x9C, 0xD6, 0x76, 0x69, 0x06, 0xE4, 0x53, 0xFC, 0x4A, 0xBC, 0x03, 0x5F, 0x83, 0x7F,
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+	0x0E, 0x86, 0x91, 0x8E, 0x2D, 0x58, 0xE7, 0x12, 0x9F, 0x4F, 0xAD, 0x67, 0x85, 0xAD, 0x4D, 0x60,
+	0xE5, 0x26, 0xAF, 0x2B, 0x68, 0x6F, 0x8C, 0xC3, 0x4A, 0x58, 0x88, 0xD2, 0x4E, 0xCB, 0x4B, 0x9F,
+	0xA6, 0x5F, 0xF0, 0x5F, 0xFF, 0x00, 0xF8, 0x2F, 0xC2, 0xFE, 0xC0, 0x7A, 0x5A, 0x7E, 0xCF, 0xBF,
+	0xB2, 0xE6, 0xAD, 0x6B, 0x75, 0xF1, 0x3A, 0xE4, 0x89, 0x66, 0xD5, 0x59, 0x52, 0x68, 0x74, 0xE8,
+	0xC1, 0x39, 0x8D, 0x97, 0xBB, 0x74, 0xE0, 0xFA, 0x57, 0xE5, 0xD7, 0xC1, 0xCF, 0xF8, 0x38, 0xBF,
+	0xFE, 0x0B, 0xC7, 0xF1, 0xEF, 0xE2, 0x5E, 0x93, 0xF0, 0x7B, 0xE1, 0x2F, 0xC4, 0x2D, 0x2B, 0x5A,
+	0xF1, 0x0E, 0xB9, 0x22, 0xC3, 0xA7, 0xE9, 0xF6, 0x9E, 0x17, 0x85, 0xD8, 0xEE, 0xFE, 0x32, 0x41,
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+	0xC6, 0x45, 0xD5, 0xFC, 0x63, 0xE2, 0x86, 0xD5, 0x3C, 0x51, 0xE2, 0x9D, 0x61, 0x53, 0xED, 0x9A,
+	0x95, 0xC1, 0x08, 0xB3, 0xC9, 0x20, 0x03, 0x73, 0x36, 0x42, 0xA7, 0xCD, 0xF8, 0x57, 0xF4, 0xFF,
+	0x00, 0xFF, 0x00, 0x04, 0x0C, 0xFF, 0x00, 0x82, 0x20, 0x7C, 0x34, 0xFF, 0x00, 0x82, 0x79, 0xFC,
+	0x29, 0xB3, 0xF8, 0xD3, 0xF1, 0x19, 0x74, 0xDF, 0x11, 0x7C, 0x4E, 0xF1, 0x25, 0xAA, 0x4D, 0x3E,
+	0xB3, 0x08, 0x49, 0x62, 0xD3, 0x11, 0x81, 0x22, 0x3B, 0x67, 0xC7, 0x20, 0x83, 0xC9, 0xAD, 0x70,
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+	0xA9, 0xD3, 0x94, 0x69, 0xD2, 0x5F, 0x2F, 0xD5, 0x9F, 0x53, 0x7F, 0xC1, 0x39, 0x7E, 0x1C, 0x7E,
+	0xDF, 0x7E, 0x08, 0xF8, 0x47, 0x1C, 0x9F, 0xF0, 0x50, 0x1F, 0x8D, 0xBA, 0x2F, 0x8C, 0x3C, 0x4F,
+	0x79, 0x0A, 0x4B, 0x19, 0xD1, 0x74, 0xF1, 0x6E, 0xB6, 0x65, 0x86, 0x4C, 0x6D, 0x85, 0x01, 0x8A,
+	0xF4, 0xC8, 0xAF, 0xA2, 0xD0, 0x26, 0xDD, 0x8A, 0x73, 0xEA, 0x7D, 0xE9, 0xA9, 0x02, 0x44, 0xF9,
+	0x45, 0x19, 0xEA, 0xD8, 0x1D, 0x69, 0xD1, 0x32, 0xC6, 0x4F, 0x9B, 0x22, 0x0F, 0xC6, 0xB0, 0x94,
+	0xA5, 0xBC, 0x76, 0xED, 0xD8, 0x9A, 0x71, 0x94, 0x63, 0xAE, 0xFF, 0x00, 0x99, 0x22, 0x0D, 0xBD,
+	0x79, 0xAA, 0x7A, 0xD4, 0xF2, 0xC1, 0x65, 0x71, 0x71, 0x19, 0xFF, 0x00, 0x57, 0x6E, 0xCC, 0xBF,
+	0xEF, 0x01, 0x56, 0x84, 0xD0, 0x13, 0xB4, 0x4A, 0xBC, 0xFA, 0x35, 0x67, 0xF8, 0x97, 0x23, 0x47,
+	0xBB, 0xC7, 0x6B, 0x37, 0xC0, 0x1F, 0x4A, 0xE7, 0xC6, 0x4B, 0xD9, 0x61, 0xE5, 0x28, 0x9B, 0x43,
+	0x96, 0xA5, 0x44, 0xBC, 0xCF, 0xE6, 0xB7, 0xFE, 0x0A, 0x39, 0xFF, 0x00, 0x07, 0x17, 0xFF, 0x00,
+	0xC1, 0x57, 0xFF, 0x00, 0x67, 0xBF, 0xDB, 0x53, 0xC6, 0xDF, 0x07, 0xBE, 0x18, 0xFC, 0x57, 0xD1,
+	0x6C, 0x34, 0x3D, 0x1E, 0xFB, 0xCB, 0xD3, 0x6C, 0xE6, 0xD0, 0xE1, 0x94, 0xA4, 0x78, 0x1C, 0x96,
+	0x6C, 0x1C, 0xE7, 0x3C, 0x57, 0x84, 0xCD, 0xFF, 0x00, 0x07, 0x52, 0x7F, 0xC1, 0x64, 0x91, 0xCA,
+	0x4B, 0xF1, 0xC7, 0x41, 0xC8, 0xE3, 0xE5, 0xF0, 0xCC, 0x27, 0xF9, 0x1A, 0xF1, 0x1F, 0xF8, 0x2C,
+	0x6C, 0xB2, 0x4F, 0xFF, 0x00, 0x05, 0x1D, 0xF8, 0x91, 0x2D, 0xD0, 0x64, 0x7F, 0xB6, 0xB6, 0xDF,
+	0x5C, 0xE3, 0x8A, 0xFD, 0x70, 0xFF, 0x00, 0x83, 0x60, 0xBE, 0x09, 0xFF, 0x00, 0xC1, 0x3C, 0xFE,
+	0x22, 0xFE, 0xC0, 0xF7, 0x9A, 0xB7, 0xED, 0x35, 0xE0, 0x8F, 0x86, 0x37, 0xFE, 0x20, 0x1E, 0x24,
+	0xB8, 0x56, 0x9B, 0xC5, 0xD7, 0x16, 0xEB, 0x75, 0xE4, 0x86, 0x38, 0xC0, 0x94, 0x8F, 0x97, 0xD3,
+	0x15, 0xD5, 0x83, 0x8C, 0x6A, 0x60, 0x95, 0x59, 0x6E, 0x92, 0x7F, 0x97, 0xF9, 0x95, 0x8B, 0xFD,
+	0xCE, 0x21, 0xC5, 0x77, 0x3F, 0x3F, 0xE0, 0xFF, 0x00, 0x83, 0xA7, 0xFF, 0x00, 0xE0, 0xB2, 0xB7,
+	0x04, 0x6D, 0xF8, 0xE5, 0xA0, 0x95, 0x0C, 0x07, 0xCD, 0xE1, 0xB8, 0x17, 0xFA, 0xD7, 0xED, 0xF7,
+	0xFC, 0x10, 0x87, 0xFE, 0x0B, 0x79, 0xE0, 0xDF, 0xF8, 0x2A, 0x17, 0xC3, 0x36, 0xF0, 0x47, 0xC4,
+	0x1B, 0x78, 0xF4, 0x3F, 0x89, 0xFE, 0x1B, 0x8E, 0x28, 0xB5, 0x8B, 0x79, 0x24, 0x4D, 0xBA, 0xD7,
+	0xCA, 0x73, 0x71, 0x0A, 0x8E, 0x40, 0x1D, 0xC7, 0x6A, 0xFC, 0x97, 0xFF, 0x00, 0x83, 0xA8, 0x3C,
+	0x0D, 0xFB, 0x05, 0xF8, 0x13, 0xF6, 0x8F, 0xF0, 0x8E, 0x8B, 0xFB, 0x27, 0xE8, 0xDE, 0x1D, 0xB1,
+	0xD7, 0x3F, 0xE1, 0x1D, 0x07, 0x50, 0xB3, 0xF0, 0x6A, 0xC2, 0x6C, 0x19, 0x0B, 0x36, 0x19, 0xFC,
+	0xAF, 0x97, 0xCC, 0xC6, 0x3A, 0x7A, 0x57, 0x33, 0xFF, 0x00, 0x06, 0x9E, 0x5A, 0xEA, 0x37, 0x5F,
+	0xF0, 0x53, 0x8D, 0x2E, 0xEE, 0xDE, 0xDE, 0xE6, 0x48, 0x61, 0xD1, 0xA7, 0xF3, 0xA7, 0x8D, 0x49,
+	0x48, 0x49, 0x53, 0x80, 0xDD, 0x86, 0x6B, 0x6C, 0x0C, 0x56, 0x36, 0x9D, 0x44, 0xD5, 0xAD, 0x7F,
+	0x9D, 0xBB, 0x1C, 0xB9, 0x85, 0x39, 0x61, 0xE3, 0x0A, 0x8B, 0x57, 0xA7, 0xE3, 0x6D, 0xCF, 0xAB,
+	0x7F, 0xE0, 0xBE, 0x9F, 0xF0, 0x5D, 0x8F, 0xF8, 0x28, 0x57, 0xEC, 0x2F, 0xFB, 0x73, 0x6A, 0x5F,
+	0x03, 0xFF, 0x00, 0x66, 0xFF, 0x00, 0x8B, 0x5A, 0x3E, 0x9B, 0xA1, 0xD9, 0xDA, 0xA3, 0x8B, 0x2B,
+	0x9D, 0x15, 0x27, 0x91, 0x58, 0x81, 0xD5, 0x98, 0x74, 0xEB, 0xDE, 0xBE, 0x1F, 0xFF, 0x00, 0x88,
+	0xAA, 0x7F, 0xE0, 0xB2, 0x3B, 0xFF, 0x00, 0xE4, 0xB8, 0xE8, 0x5F, 0xF8, 0x4C, 0x45, 0xFE, 0x35,
+	0xFD, 0x3F, 0xFC, 0x50, 0xFD, 0x8A, 0xBF, 0x64, 0x8F, 0x8D, 0xBE, 0x25, 0x93, 0xC6, 0xDF, 0x16,
+	0x7F, 0x66, 0x8F, 0x09, 0x78, 0x93, 0x54, 0x91, 0x8A, 0xCB, 0xA9, 0x6A, 0xDA, 0x5C, 0x72, 0xCA,
+	0xC0, 0x1E, 0xE5, 0x86, 0x6B, 0xE7, 0x1F, 0xDB, 0xC3, 0xE1, 0x9F, 0xFC, 0x12, 0x63, 0xFE, 0x09,
+	0xF7, 0xFB, 0x3E, 0x6A, 0xDF, 0x1E, 0xFE, 0x2A, 0x7E, 0xC8, 0x7F, 0x0D, 0xE3, 0x7D, 0x3E, 0xD5,
+	0x9F, 0x49, 0xD2, 0x9B, 0x46, 0x81, 0x64, 0xBE, 0x9B, 0x1C, 0x22, 0x82, 0x3D, 0x7E, 0xB5, 0xC3,
+	0xCC, 0xB0, 0xB4, 0x52, 0x9B, 0x3B, 0x2F, 0x1A, 0xD3, 0x4E, 0x0B, 0xB1, 0xF8, 0x23, 0x17, 0xFC,
+	0x1D, 0x43, 0xFF, 0x00, 0x05, 0x95, 0x99, 0x70, 0x9F, 0x1B, 0xF4, 0x1E, 0x0F, 0x53, 0xE1, 0xB8,
+	0x01, 0xFD, 0x4D, 0x7D, 0x59, 0xFF, 0x00, 0x04, 0x63, 0xFF, 0x00, 0x82, 0xFC, 0x7F, 0xC1, 0x4E,
+	0xBF, 0x6C, 0x0F, 0xF8, 0x28, 0x57, 0x84, 0x3E, 0x02, 0x7C, 0x75, 0xF8, 0xB7, 0xA3, 0x5F, 0x78,
+	0x6F, 0x58, 0x86, 0x56, 0xBE, 0xB6, 0xB7, 0xD1, 0x62, 0x88, 0x90, 0xAA, 0x08, 0x21, 0x93, 0x24,
+	0x1E, 0x7A, 0x57, 0xE4, 0xE7, 0xED, 0x4F, 0xF1, 0xAE, 0xD7, 0xF6, 0xBC, 0xFD, 0xA1, 0xEF, 0xBE,
+	0x22, 0xF8, 0x17, 0xE1, 0x06, 0x97, 0xE1, 0x38, 0x35, 0x8B, 0xF3, 0x1E, 0x89, 0xE1, 0xBD, 0x06,
+	0xDC, 0x2C, 0x60, 0x33, 0xE1, 0x50, 0x00, 0x39, 0x6E, 0x40, 0xAF, 0xE8, 0x0F, 0xFE, 0x0D, 0xB1,
+	0xFF, 0x00, 0x82, 0x20, 0xDE, 0xFE, 0xC9, 0x5E, 0x0B, 0x87, 0xF6, 0xBA, 0xFD, 0xA6, 0x3C, 0x31,
+	0x6E, 0xBE, 0x37, 0xD7, 0x21, 0x59, 0x7C, 0x35, 0x63, 0x22, 0xE2, 0x4B, 0x0B, 0x66, 0x5C, 0xFC,
+	0xE0, 0x8F, 0x95, 0x8F, 0xA5, 0x7A, 0x58, 0x58, 0xC6, 0x31, 0xE7, 0xAC, 0xAC, 0xAD, 0x7B, 0x1C,
+	0x38, 0xA9, 0xF2, 0x27, 0x0A, 0x7A, 0xC9, 0xFF, 0x00, 0x57, 0x3F, 0x4E, 0xBF, 0x6B, 0x1F, 0x8F,
+	0x16, 0x9F, 0xB3, 0x8F, 0xEC, 0xD3, 0xE2, 0xEF, 0x8D, 0xF7, 0xD0, 0xF9, 0xCB, 0xE1, 0xFD, 0x26,
+	0x59, 0xE1, 0x5E, 0x99, 0x90, 0x2F, 0xCA, 0x7F, 0x3C, 0x57, 0xE7, 0xCF, 0xFC, 0x1B, 0x9F, 0xFF,
+	0x00, 0x05, 0x09, 0xFD, 0xBC, 0xFF, 0x00, 0xE0, 0xA1, 0x97, 0xFE, 0x3E, 0xF8, 0xA1, 0xFB, 0x4E,
+	0x78, 0xF3, 0x49, 0xD4, 0xBC, 0x23, 0x0D, 0xF4, 0x90, 0xF8, 0x5E, 0xCA, 0xCE, 0xC5, 0x22, 0x92,
+	0xDC, 0x87, 0xE0, 0x31, 0x51, 0xF3, 0x00, 0x38, 0xE4, 0xE7, 0xBD, 0x76, 0x5F, 0xF0, 0x73, 0x8F,
+	0xED, 0x11, 0xA6, 0xFC, 0x1A, 0xFF, 0x00, 0x82, 0x66, 0x78, 0xAB, 0xC1, 0x91, 0xEA, 0x13, 0x5A,
+	0xEA, 0x5E, 0x2C, 0x54, 0xB5, 0xD3, 0x5A, 0x0E, 0x37, 0x16, 0x38, 0x20, 0xFE, 0x75, 0x6F, 0xFE,
+	0x0D, 0x8F, 0xFD, 0x9D, 0xEE, 0xFE, 0x01, 0xFF, 0x00, 0xC1, 0x2E, 0xFC, 0x3A, 0x35, 0xFD, 0x2A,
+	0x0B, 0x7D, 0x4B, 0x5C, 0xD4, 0x24, 0xD4, 0x26, 0x99, 0x31, 0xB9, 0x92, 0x42, 0x19, 0x41, 0x3E,
+	0xD9, 0x35, 0xC7, 0x83, 0x8F, 0xD6, 0x29, 0xCF, 0x11, 0xD1, 0x3B, 0x1A, 0x62, 0x3F, 0x73, 0x4A,
+	0x9C, 0x3E, 0xD4, 0xBF, 0x43, 0xEC, 0xBF, 0xDA, 0xBF, 0xE3, 0xCE, 0x99, 0xFB, 0x35, 0x7E, 0xCE,
+	0x3E, 0x2D, 0xF8, 0xCB, 0xAA, 0xCA, 0x9E, 0x66, 0x87, 0xA1, 0x4F, 0x75, 0x6E, 0x24, 0x61, 0xFB,
+	0xC9, 0x95, 0x18, 0xA8, 0xFC, 0xF1, 0x5F, 0xCC, 0x6F, 0x8B, 0xFF, 0x00, 0xE0, 0xEA, 0x5F, 0xF8,
+	0x2B, 0xAE, 0xAD, 0xE2, 0xCB, 0xED, 0x5B, 0xC2, 0x1F, 0x16, 0x34, 0x3D, 0x3F, 0x4A, 0x9E, 0xE9,
+	0xFE, 0xC3, 0x63, 0x26, 0x87, 0x0B, 0x79, 0x31, 0x86, 0xE0, 0x12, 0x48, 0x24, 0xE3, 0x15, 0xFA,
+	0xA7, 0xFF, 0x00, 0x07, 0x64, 0x7E, 0xD6, 0x91, 0x7C, 0x19, 0xFD, 0x89, 0x2C, 0xFE, 0x0E, 0xF8,
+	0x6B, 0xC5, 0x11, 0x41, 0xE2, 0x2F, 0x10, 0xEA, 0xAB, 0xE7, 0x59, 0x24, 0xB8, 0x91, 0xAC, 0xCE,
+	0x43, 0x36, 0x3A, 0xE2, 0xBF, 0x01, 0x7F, 0x60, 0x4F, 0xD8, 0x0F, 0xE2, 0x2F, 0xED, 0xEB, 0xE3,
+	0xFD, 0x63, 0xC3, 0x9E, 0x08, 0xB6, 0x98, 0x69, 0xFA, 0x16, 0x87, 0x71, 0xA8, 0xEA, 0x37, 0x28,
+	0x3E, 0xE7, 0x96, 0x9B, 0xB1, 0xFA, 0x57, 0x1E, 0x11, 0xD5, 0xAD, 0x5A, 0x75, 0x65, 0xB2, 0xD3,
+	0xEE, 0x3B, 0xAA, 0xD3, 0xA5, 0x47, 0x0B, 0x0B, 0xBF, 0x7A, 0x5F, 0xF0, 0xC8, 0xFD, 0xB9, 0xFF,
+	0x00, 0x83, 0x71, 0xBF, 0xE0, 0xB9, 0x7F, 0xB5, 0x27, 0xED, 0xC3, 0xF1, 0xB3, 0xC5, 0x9F, 0x06,
+	0xFF, 0x00, 0x6C, 0xEF, 0x1F, 0xE9, 0xBA, 0xB5, 0xD4, 0xD6, 0xF1, 0x1F, 0x0A, 0xFD, 0x8E, 0xC6,
+	0x3B, 0x72, 0xB2, 0xE4, 0xEF, 0x18, 0x5F, 0xBC, 0x30, 0x06, 0x0F, 0xBD, 0x7E, 0xD5, 0x42, 0x55,
+	0xF2, 0xC5, 0xFE, 0xEF, 0x04, 0xD7, 0xF1, 0x73, 0xFF, 0x00, 0x04, 0x97, 0xFD, 0xA2, 0x64, 0xFD,
+	0x8E, 0x7F, 0xE0, 0xA2, 0xDE, 0x04, 0xF8, 0xA3, 0xA9, 0x5F, 0x18, 0x6C, 0x74, 0x8F, 0x10, 0x3D,
+	0x9D, 0xE2, 0xB3, 0x95, 0x49, 0x01, 0x62, 0x98, 0x6F, 0xC4, 0x8A, 0xFE, 0xCC, 0xBC, 0x21, 0xE2,
+	0x0B, 0x7F, 0x11, 0xF8, 0x73, 0x4F, 0xF1, 0x0D, 0xAE, 0x3C, 0xAD, 0x52, 0xC2, 0x3B, 0xD8, 0xFF,
+	0x00, 0xDC, 0x74, 0x0C, 0x31, 0xF8, 0x11, 0x5E, 0xC5, 0x68, 0xD3, 0x74, 0x63, 0x56, 0x3E, 0x7F,
+	0x81, 0xE4, 0xDE, 0xA4, 0x71, 0x7E, 0xCA, 0x7B, 0x6E, 0x8D, 0x09, 0x6E, 0xA4, 0xF3, 0x5A, 0x3B,
+	0x18, 0xD5, 0xE4, 0x51, 0x9D, 0x8C, 0xD8, 0xE2, 0xBF, 0x21, 0x7F, 0xE0, 0xE1, 0x3F, 0xF8, 0x38,
+	0x22, 0xFB, 0xF6, 0x23, 0xBB, 0xB4, 0xFD, 0x99, 0xBF, 0x62, 0x4F, 0x88, 0x1A, 0x55, 0xE7, 0xC4,
+	0x99, 0x2E, 0x37, 0xF8, 0x8B, 0x54, 0x41, 0x1D, 0xC4, 0x7A, 0x12, 0xAB, 0x63, 0xC8, 0x91, 0x4F,
+	0xCB, 0xBD, 0x87, 0x6E, 0xDF, 0xA5, 0x78, 0xE7, 0xFC, 0x1C, 0x9B, 0xFF, 0x00, 0x05, 0x8C, 0xFD,
+	0xB6, 0x3E, 0x0E, 0xFC, 0x74, 0x93, 0xF6, 0x05, 0xFD, 0x9C, 0xAD, 0x5B, 0x4B, 0x86, 0xEB, 0x4F,
+	0x8F, 0x50, 0xFE, 0xDC, 0xF0, 0xEF, 0x98, 0xFA, 0xBB, 0xE7, 0x77, 0xC8, 0xA1, 0x32, 0x55, 0x40,
+	0xC9, 0xE9, 0xCF, 0xE1, 0x5F, 0x8C, 0x1F, 0x1E, 0xBF, 0x65, 0x4F, 0xDA, 0xB3, 0xC0, 0x9E, 0x0A,
+	0xB4, 0xFD, 0xA3, 0xBF, 0x68, 0x7D, 0x17, 0x53, 0xB5, 0x8F, 0xC6, 0x52, 0x1B, 0xAF, 0xB5, 0x6B,
+	0xAC, 0xEB, 0x7D, 0x78, 0xCC, 0x73, 0xBD, 0xD6, 0x41, 0xBB, 0x27, 0xAF, 0x35, 0xE5, 0x7B, 0xB2,
+	0xB4, 0xA5, 0xDF, 0x43, 0xD5, 0xE4, 0xE5, 0x91, 0xFB, 0x9F, 0xFF, 0x00, 0x06, 0xE2, 0xFF, 0x00,
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+	0xE7, 0x5F, 0xEC, 0x9B, 0xFF, 0x00, 0x06, 0xC6, 0x7F, 0xC1, 0x3D, 0x3F, 0x64, 0x3F, 0x8D, 0xDA,
+	0x5F, 0xC7, 0x9F, 0x85, 0xFE, 0x24, 0xF1, 0x85, 0xC6, 0xB3, 0xA3, 0xC9, 0xBA, 0xCE, 0x3D, 0x4B,
+	0x53, 0xF3, 0x22, 0x07, 0x20, 0xF2, 0xB8, 0x19, 0xE8, 0x2B, 0xF4, 0x47, 0xC4, 0x71, 0x16, 0xD1,
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+	0x48, 0x7E, 0x24, 0x07, 0x3F, 0x38, 0xBF, 0x24, 0x63, 0xBE, 0x05, 0x70, 0x3F, 0x0C, 0xFF, 0x00,
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+	0x90, 0x0E, 0x78, 0xC1, 0xED, 0x5E, 0x81, 0xFF, 0x00, 0x05, 0x91, 0x17, 0x12, 0xFF, 0x00, 0xC1,
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+	0xFC, 0x1A, 0x71, 0xE1, 0x3D, 0x13, 0xE2, 0x07, 0xFC, 0x12, 0xCB, 0x5E, 0xF8, 0x73, 0xE3, 0x7D,
+	0x3F, 0xED, 0x9A, 0x1E, 0xAD, 0xAF, 0x5E, 0x41, 0x7D, 0x63, 0x70, 0xA0, 0xC7, 0x2C, 0x6F, 0x90,
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+	0xF0, 0xFC, 0x77, 0x93, 0x1F, 0x2A, 0xC6, 0x28, 0x97, 0x32, 0x47, 0x18, 0x27, 0x8C, 0xE4, 0xF1,
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+	0xFB, 0x56, 0x9B, 0x50, 0xBA, 0x9D, 0xB6, 0xE3, 0x03, 0x2A, 0xAA, 0x0F, 0x52, 0x4F, 0x1C, 0x57,
+	0xF2, 0x3F, 0xFF, 0x00, 0x05, 0x83, 0xFF, 0x00, 0x82, 0xAF, 0xFC, 0x4B, 0xFF, 0x00, 0x82, 0xA2,
+	0xFE, 0xD0, 0xFA, 0x87, 0x8D, 0x35, 0x4B, 0x8B, 0xAD, 0x2F, 0xC0, 0xBA, 0x54, 0xC6, 0x2F, 0x0D,
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+	0xEE, 0x7F, 0xF0, 0x71, 0xB7, 0xFC, 0x15, 0x87, 0xE2, 0xC7, 0xED, 0xA1, 0xFB, 0x4F, 0xEA, 0xDF,
+	0xB3, 0xB7, 0x84, 0xF5, 0x0B, 0xCD, 0x2F, 0xE1, 0x9F, 0x82, 0xEE, 0x9A, 0x0D, 0x3F, 0x4C, 0x8D,
+	0x5A, 0x36, 0xD4, 0xA5, 0x52, 0x15, 0x9E, 0xE0, 0x03, 0xF3, 0x0C, 0x8E, 0x01, 0xCE, 0x2B, 0xE5,
+	0x9F, 0xF8, 0x26, 0x3F, 0xC4, 0x5F, 0xD8, 0x37, 0xE1, 0x1F, 0xED, 0x23, 0x67, 0xF1, 0x1F, 0xFE,
+	0x0A, 0x13, 0xE0, 0xCF, 0x10, 0x6B, 0xDE, 0x1A, 0xD0, 0xF6, 0x5D, 0x68, 0xBA, 0x3E, 0x8F, 0x1E,
+	0xF4, 0xB8, 0xB9, 0x46, 0xDC, 0xA9, 0x3A, 0xFF, 0x00, 0x14, 0x63, 0x8E, 0x2B, 0xCD, 0xC2, 0xD1,
+	0x78, 0x89, 0x7B, 0x6A, 0xAF, 0x4E, 0x87, 0x75, 0x49, 0x47, 0x0F, 0x4F, 0xDC, 0x57, 0x76, 0x3F,
+	0x54, 0x3F, 0xE0, 0xDB, 0x0F, 0xF8, 0x20, 0x9F, 0xF6, 0xDA, 0x69, 0xFF, 0x00, 0xB7, 0xBF, 0xED,
+	0xA9, 0xF0, 0xF1, 0xD6, 0xD4, 0x3C, 0x77, 0x5F, 0x0F, 0xFC, 0x2F, 0x7D, 0x16, 0x3C, 0xFF, 0x00,
+	0xBA, 0xC9, 0x7C, 0xCB, 0x9E, 0x06, 0x79, 0x00, 0xD7, 0xEF, 0xEC, 0x4A, 0x12, 0x11, 0x14, 0xE1,
+	0x51, 0x98, 0x05, 0x08, 0xBF, 0x74, 0x0E, 0xD8, 0x1D, 0xAB, 0xF2, 0x13, 0x47, 0xFF, 0x00, 0x83,
+	0xC0, 0xBF, 0xE0, 0x96, 0xDA, 0x06, 0x9B, 0x67, 0xA1, 0x69, 0x1F, 0x08, 0x7C, 0x79, 0x6D, 0x67,
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+	0x00, 0x07, 0xE1, 0x5E, 0x83, 0xFB, 0x3B, 0x7F, 0xC1, 0xD4, 0xBF, 0xF0, 0x4F, 0x4F, 0xDA, 0x5B,
+	0xE3, 0x3E, 0x8F, 0xF0, 0x6B, 0xC1, 0x3F, 0x0F, 0xBC, 0x71, 0x6F, 0xA9, 0x6B, 0x17, 0x02, 0x3B,
+	0x5B, 0xAB, 0xCD, 0x3D, 0x44, 0x48, 0x7B, 0x96, 0x21, 0xB2, 0x00, 0xFC, 0xAB, 0xAB, 0x19, 0x88,
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+	0x33, 0xE5, 0x6F, 0xF8, 0x3B, 0x63, 0xE2, 0x25, 0xF7, 0xC6, 0x1F, 0x8C, 0x9F, 0x06, 0xFF, 0x00,
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+	0x00, 0xF1, 0x4E, 0xC3, 0xFE, 0x34, 0x51, 0x44, 0x74, 0x8A, 0x44, 0x20, 0xFF, 0x00, 0x88, 0x22,
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+	0x47, 0xC1, 0xDF, 0xB0, 0x67, 0xED, 0x69, 0xE2, 0x8F, 0xDA, 0xBE, 0x4F, 0x8F, 0x7A, 0xAF, 0x8B,
+	0xB5, 0x3F, 0x12, 0x16, 0xDB, 0x6B, 0xA9, 0x59, 0x85, 0x16, 0xD9, 0x62, 0x78, 0x6C, 0x92, 0x7A,
+	0xD7, 0xB4, 0x7F, 0xC1, 0x53, 0x3F, 0xE0, 0x9D, 0x37, 0x7F, 0xF0, 0x52, 0x9F, 0x80, 0x0B, 0xF0,
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+	0x88, 0xF0, 0x3F, 0x76, 0xC0, 0x91, 0x91, 0x45, 0x15, 0x8E, 0x35, 0x7D, 0x61, 0xC3, 0xDA, 0x6B,
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+	0x65, 0x6B, 0x7A, 0x94, 0x3A, 0x06, 0xB1, 0x05, 0xFB, 0x69, 0xF2, 0x68, 0x31, 0x2A, 0xCF, 0xE5,
+	0x48, 0x1C, 0x47, 0x90, 0xDC, 0x02, 0x47, 0x35, 0xFB, 0x59, 0xA2, 0xE9, 0x09, 0xA1, 0xE9, 0xB0,
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+	0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA,
+	0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
+	0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00,
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+	0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00,
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+	0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18,
+	0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45,
+	0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65,
+	0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84,
+	0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2,
+	0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9,
+	0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7,
+	0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5,
+	0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11,
+	0x00, 0x3F, 0x00, 0xFB, 0xEF, 0xF6, 0xBD, 0xFF, 0x00, 0x82, 0xEA, 0xF8, 0x0B, 0xF6, 0x49, 0xFD,
+	0xA0, 0x75, 0x7F, 0xD9, 0xF3, 0x5A, 0xFD, 0x9F, 0x75, 0xFD, 0x72, 0xEB, 0x4A, 0x82, 0x39, 0x1B,
+	0x50, 0xB1, 0xBA, 0x55, 0x49, 0xFC, 0xC5, 0xDD, 0x80, 0x36, 0xD7, 0x9F, 0x4F, 0xFF, 0x00, 0x07,
+	0x29, 0xFC, 0x3B, 0x86, 0x64, 0xFB, 0x67, 0xEC, 0x97, 0xE2, 0xC8, 0x97, 0x6E, 0xEF, 0x31, 0xAE,
+	0x97, 0xE5, 0xFF, 0x00, 0xC7, 0x6B, 0xE5, 0xEF, 0xF8, 0x28, 0xF4, 0x56, 0xB7, 0x3F, 0xF0, 0x58,
+	0x2B, 0xF8, 0x6E, 0x6C, 0xD6, 0xE1, 0x24, 0x6B, 0x31, 0x2D, 0xBC, 0x8B, 0xB9, 0x5B, 0xE5, 0x5F,
+	0xE1, 0xAF, 0xD5, 0xEF, 0x1B, 0x7E, 0xCC, 0xDF, 0xB3, 0x3E, 0xA5, 0xFB, 0x33, 0xDC, 0x49, 0xE2,
+	0x5F, 0x85, 0x9E, 0x1D, 0xD3, 0xE1, 0x9B, 0xC3, 0x2B, 0xF6, 0xAB, 0xE6, 0xD3, 0x62, 0x8D, 0xE1,
+	0xDD, 0x17, 0xCC, 0xC1, 0xB6, 0xFD, 0xEA, 0xFD, 0x6B, 0x31, 0xCA, 0x38, 0x4F, 0x23, 0xCB, 0xB2,
+	0xDA, 0xB5, 0xB0, 0xB2, 0xA9, 0x2C, 0x44, 0x6F, 0x26, 0xA6, 0xD5, 0xB5, 0xB6, 0x89, 0x1E, 0x6C,
+	0x6A, 0x56, 0xAF, 0x98, 0x54, 0xA4, 0x9F, 0x2C, 0x62, 0xED, 0xA2, 0x4F, 0x7F, 0xF2, 0x20, 0xFD,
+	0x89, 0x7F, 0xE0, 0xA1, 0xFF, 0x00, 0x05, 0xFF, 0x00, 0x6D, 0xDF, 0x0F, 0x3D, 0xCF, 0x85, 0x65,
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+	0x47, 0x99, 0xD3, 0x69, 0xF4, 0xD7, 0x4E, 0xE7, 0x8F, 0x4F, 0x0A, 0xEA, 0xE3, 0x6B, 0xF3, 0x5D,
+	0x2E, 0x6B, 0xA6, 0xB4, 0xBD, 0xCF, 0x97, 0xFF, 0x00, 0xE0, 0x9C, 0x1F, 0xF0, 0x4B, 0x4F, 0x03,
+	0x7E, 0xC2, 0x16, 0xCD, 0xAF, 0x5F, 0x78, 0x83, 0xFB, 0x7B, 0xC4, 0xD7, 0x49, 0xB4, 0x6A, 0x92,
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+	0xF0, 0x70, 0x2F, 0x88, 0xA2, 0x95, 0x77, 0x6D, 0xD6, 0x9B, 0xE5, 0xFF, 0x00, 0x80, 0xD7, 0xEC,
+	0xF1, 0x2F, 0xE7, 0x2E, 0xE4, 0xC8, 0xFE, 0xF5, 0x7E, 0x43, 0xEA, 0xFF, 0x00, 0x01, 0x3F, 0x68,
+	0x89, 0x7F, 0xE0, 0xB9, 0xBE, 0x20, 0xF8, 0xA9, 0x17, 0xC0, 0xFF, 0x00, 0x10, 0x7F, 0xC2, 0x2A,
+	0xDA, 0xB3, 0x35, 0xAF, 0x88, 0xD6, 0xCD, 0xBE, 0xCA, 0xEB, 0xB7, 0xEF, 0x6E, 0xAF, 0x17, 0x83,
+	0x78, 0x86, 0xBE, 0x3B, 0x36, 0xCC, 0x71, 0x99, 0x8D, 0x7F, 0x7E, 0x78, 0x7A, 0x89, 0x39, 0x34,
+	0xAF, 0xB5, 0xA2, 0xBF, 0x44, 0x75, 0x56, 0xC3, 0x53, 0xA3, 0x81, 0x94, 0x29, 0xAB, 0x5F, 0x5F,
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+	0x6B, 0xBB, 0x6B, 0x57, 0xD3, 0x9E, 0x13, 0xF8, 0xCF, 0xFF, 0x00, 0x05, 0x6F, 0x5F, 0x87, 0x5A,
+	0x67, 0x83, 0xEC, 0x3F, 0x63, 0x1B, 0x7B, 0xAD, 0x0D, 0xB4, 0x98, 0x60, 0x83, 0xFE, 0x26, 0x90,
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+	0x23, 0x8F, 0xE5, 0x0D, 0xB9, 0xAB, 0xD8, 0xC1, 0xE2, 0xB0, 0x39, 0xD7, 0x08, 0x60, 0xE8, 0xE1,
+	0x21, 0x42, 0x75, 0x68, 0x5D, 0x4A, 0x15, 0xA5, 0x28, 0x34, 0xF4, 0xB4, 0xA2, 0xD4, 0xA2, 0xB5,
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+	0x7D, 0xFC, 0xCF, 0x44, 0xFF, 0x00, 0x82, 0x5F, 0x7E, 0xC3, 0x9F, 0xB6, 0x47, 0xC1, 0x5F, 0xF8,
+	0x28, 0x36, 0xB9, 0xFB, 0x48, 0xFC, 0x6E, 0xF8, 0x46, 0x9E, 0x15, 0xF0, 0xCE, 0xA5, 0xA4, 0xDE,
+	0x3C, 0xD2, 0x7F, 0x68, 0x2C, 0x8B, 0x1C, 0x8D, 0xFC, 0x3B, 0x56, 0xBD, 0x43, 0xF6, 0x82, 0xFF,
+	0x00, 0x82, 0xC6, 0x3F, 0x87, 0x7F, 0x68, 0x4B, 0xCF, 0xD9, 0xD3, 0xF6, 0x4B, 0xF8, 0x2B, 0x07,
+	0x8C, 0xBC, 0x45, 0x34, 0xED, 0x1D, 0xE5, 0xFC, 0x72, 0xF9, 0x65, 0x64, 0x5F, 0xFD, 0x0A, 0x93,
+	0xFE, 0x09, 0xF7, 0xAF, 0x7F, 0xC1, 0x48, 0x3F, 0x68, 0x9F, 0x8A, 0xBA, 0xAF, 0x8D, 0xBF, 0x6B,
+	0x7D, 0x2A, 0x6F, 0x0F, 0xE8, 0xB7, 0x9E, 0x17, 0xBA, 0xD3, 0x6D, 0x74, 0xB9, 0x2C, 0xDA, 0x0F,
+	0x2E, 0x69, 0x17, 0x89, 0x36, 0xFF, 0x00, 0xB3, 0x5F, 0x1B, 0x78, 0xCB, 0xF6, 0x67, 0xFD, 0xBE,
+	0x3F, 0x60, 0x4F, 0xDB, 0x3E, 0xE7, 0xE2, 0x6F, 0xC0, 0xBF, 0x83, 0x9A, 0x87, 0x8B, 0xAF, 0xA1,
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+	0x1F, 0x12, 0x67, 0x95, 0xBF, 0xB5, 0xAB, 0x52, 0xF6, 0xD4, 0xE8, 0xC5, 0x42, 0x31, 0x93, 0x54,
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+	0x73, 0x36, 0xE5, 0xAB, 0x92, 0xD7, 0xCD, 0xA5, 0xA1, 0xD3, 0x7F, 0xC1, 0x55, 0x3E, 0x26, 0x7E,
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+	0xDB, 0x63, 0x46, 0xFF, 0x00, 0x82, 0xAB, 0xFE, 0xD5, 0x5F, 0x00, 0x34, 0x7F, 0x11, 0x7C, 0x64,
+	0xF8, 0x58, 0x75, 0x18, 0x56, 0xE2, 0x49, 0x2C, 0xFC, 0x37, 0xA1, 0x68, 0xAD, 0x0D, 0xD5, 0xAB,
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+	0x00, 0xF0, 0x4B, 0x85, 0xF0, 0xC6, 0x89, 0xE1, 0x2D, 0x5B, 0xC2, 0x7E, 0x38, 0xD3, 0x75, 0xEB,
+	0x8B, 0xCD, 0x3A, 0xC7, 0x54, 0x89, 0xA3, 0x93, 0xCC, 0xDB, 0xF2, 0xB3, 0x2F, 0xF1, 0x2D, 0x75,
+	0x66, 0x59, 0x85, 0x1A, 0x3C, 0x13, 0x43, 0x0B, 0x4E, 0x54, 0x69, 0x54, 0x86, 0x21, 0x3E, 0x58,
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+	0xE4, 0xD2, 0x8C, 0x93, 0x6F, 0xF2, 0x3E, 0x57, 0xFD, 0x96, 0x74, 0x8F, 0xF8, 0x29, 0x5F, 0xFC,
+	0x12, 0xFB, 0xC4, 0x5A, 0xF5, 0x8E, 0x89, 0xF0, 0xBA, 0xE2, 0xFF, 0x00, 0xC2, 0xF6, 0xAB, 0x33,
+	0x5E, 0x69, 0xBF, 0x2B, 0x2C, 0xCC, 0xBF, 0xF2, 0xF1, 0xF7, 0x7F, 0xF1, 0xDA, 0xFA, 0x3B, 0xF6,
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+	0xB7, 0xCB, 0xB7, 0x6F, 0xF1, 0x57, 0x97, 0xAF, 0xFC, 0x14, 0x0B, 0xFE, 0x0B, 0x8B, 0xE1, 0x5B,
+	0x8B, 0x9F, 0x08, 0xDC, 0xFE, 0xCA, 0xF3, 0x6A, 0xCB, 0xA7, 0xB3, 0x45, 0x2D, 0xE4, 0x9E, 0x15,
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+	0x35, 0xFB, 0xB5, 0xD1, 0x99, 0x7F, 0x64, 0xE6, 0x38, 0x4C, 0x55, 0x7C, 0xEE, 0x14, 0x63, 0x55,
+	0xC2, 0xF0, 0xAB, 0x4A, 0xA3, 0x73, 0x94, 0x92, 0xD2, 0x2E, 0x2F, 0x4B, 0xBE, 0xB7, 0xD9, 0x68,
+	0x61, 0xCB, 0xEC, 0x62, 0xD5, 0x06, 0xD2, 0x6D, 0x7B, 0xAD, 0x69, 0xE6, 0x7C, 0xD9, 0xF1, 0xCB,
+	0x59, 0xF8, 0xA9, 0xE2, 0x5F, 0xF8, 0x2B, 0x52, 0xF8, 0x9B, 0xC3, 0x7A, 0x0B, 0x78, 0x87, 0xC5,
+	0x92, 0x5F, 0xAA, 0xE9, 0x3A, 0x2D, 0xC4, 0xBE, 0x5A, 0xDD, 0x6D, 0x5F, 0x95, 0x77, 0x37, 0xCA,
+	0xBF, 0x2D, 0x7D, 0x95, 0xF1, 0xA3, 0xC6, 0x7F, 0xF0, 0x57, 0x7F, 0x8C, 0x9F, 0x09, 0x35, 0xBF,
+	0x84, 0x5A, 0xF7, 0xEC, 0x5D, 0x0F, 0xD8, 0xF5, 0x7D, 0x2D, 0xAC, 0x96, 0x45, 0xD5, 0x21, 0xFD,
+	0xCA, 0xB7, 0xF1, 0x55, 0x2F, 0xF8, 0x2A, 0x67, 0xFC, 0x13, 0x2B, 0xE2, 0x55, 0xDF, 0xC6, 0xEB,
+	0x5F, 0xDA, 0xFB, 0xF6, 0x53, 0x86, 0x61, 0xE2, 0x6D, 0xCA, 0x6F, 0x2D, 0xED, 0xF7, 0x33, 0x2F,
+	0x96, 0xBF, 0x2E, 0xD5, 0x5F, 0xBB, 0x5E, 0x55, 0xA7, 0xFF, 0x00, 0xC1, 0x46, 0x3F, 0xE0, 0xB9,
+	0x9A, 0x16, 0x9B, 0x1F, 0x86, 0xE2, 0xFD, 0x97, 0xB5, 0x49, 0x8D, 0x8A, 0xF9, 0x5F, 0x6A, 0x9B,
+	0xC3, 0x7B, 0x9A, 0x65, 0x5F, 0x97, 0x76, 0xEA, 0xAC, 0x46, 0x3B, 0x0D, 0xC4, 0x19, 0x76, 0x0B,
+	0x13, 0x80, 0x8E, 0x1E, 0x52, 0xA7, 0x08, 0xC5, 0xAA, 0xB2, 0x94, 0x27, 0x09, 0x47, 0xAA, 0x4A,
+	0x49, 0x5B, 0xAF, 0x76, 0x75, 0xD6, 0xF6, 0x94, 0x31, 0x55, 0x2A, 0xCF, 0x99, 0x29, 0x28, 0xEA,
+	0x95, 0xFE, 0x49, 0x59, 0x9E, 0xF1, 0xFF, 0x00, 0x04, 0x4A, 0xFD, 0x8C, 0x3F, 0x6A, 0x2F, 0xD9,
+	0x2C, 0xEA, 0x96, 0x1F, 0x1C, 0x3E, 0x1F, 0x7F, 0x61, 0xD9, 0xDD, 0x3C, 0x8E, 0xB1, 0xFD, 0xA9,
+	0x64, 0xF3, 0x1B, 0xF8, 0x5B, 0xE5, 0xAF, 0xD1, 0x08, 0x97, 0x6C, 0x4B, 0xE7, 0xAE, 0x59, 0xBE,
+	0x6F, 0x2F, 0xFB, 0xB5, 0xF2, 0x6F, 0xFC, 0x13, 0x65, 0xFF, 0x00, 0x6C, 0x5F, 0x18, 0xD8, 0xDC,
+	0xFC, 0x52, 0xFD, 0xAF, 0x1A, 0x4B, 0x7D, 0x46, 0xF1, 0x98, 0xD9, 0x69, 0xBE, 0x4B, 0x45, 0xF6,
+	0x78, 0xDB, 0xF8, 0x59, 0x7F, 0xBD, 0x5F, 0x59, 0xB4, 0x9B, 0x4E, 0xF8, 0xE4, 0x55, 0x5F, 0xE2,
+	0xDD, 0xFC, 0x55, 0xF9, 0x27, 0x16, 0x63, 0x31, 0x18, 0xEC, 0xE6, 0xAD, 0x6C, 0x43, 0x8B, 0x9E,
+	0xCF, 0x92, 0xEE, 0x2D, 0xA5, 0xD2, 0xFA, 0xBF, 0x53, 0xA3, 0x03, 0x4E, 0x14, 0xE9, 0xBB, 0x26,
+	0xAE, 0xDB, 0xD7, 0x43, 0xF2, 0xF3, 0xFE, 0x0B, 0x2D, 0xFF, 0x00, 0x04, 0xF1, 0xFD, 0xA4, 0xBE,
+	0x20, 0x7C, 0x62, 0xB6, 0xFD, 0xA7, 0xBF, 0x67, 0x5B, 0x69, 0x35, 0x6B, 0xA6, 0xF2, 0xFE, 0xDF,
+	0x6F, 0x1C, 0x8B, 0xBB, 0x4F, 0x58, 0xD7, 0x86, 0xDB, 0xFC, 0x5B, 0xAB, 0xCD, 0x13, 0xFE, 0x0A,
+	0xF3, 0xFB, 0x71, 0xFE, 0xC8, 0xFE, 0x17, 0xD2, 0xBC, 0x15, 0xFB, 0x43, 0xFC, 0x1B, 0x93, 0x54,
+	0x92, 0xD5, 0x63, 0x46, 0x5B, 0x88, 0x95, 0x56, 0xEA, 0x15, 0x5F, 0x96, 0x3D, 0xDB, 0x6B, 0xDC,
+	0x7F, 0xE0, 0xA2, 0x7E, 0x2E, 0xFF, 0x00, 0x82, 0x8F, 0x7E, 0xCD, 0xFF, 0x00, 0xB4, 0xF5, 0xE7,
+	0xC5, 0x9F, 0xD9, 0x4B, 0xC2, 0x1A, 0x87, 0x8A, 0x74, 0x7F, 0x10, 0x5B, 0xC3, 0x14, 0xDA, 0x5C,
+	0x36, 0x4D, 0x71, 0x1C, 0x3E, 0x5A, 0xFF, 0x00, 0x77, 0xEE, 0xD7, 0xCD, 0xFF, 0x00, 0x16, 0x3E,
+	0x33, 0xFF, 0x00, 0xC1, 0x5D, 0x3F, 0x6D, 0x4D, 0x26, 0x3F, 0x84, 0x7F, 0x14, 0x7F, 0x65, 0x45,
+	0xD2, 0xEC, 0x6F, 0x9B, 0x63, 0x6A, 0x93, 0x78, 0x57, 0xCB, 0x68, 0x77, 0x7F, 0x17, 0x99, 0xB6,
+	0xBF, 0x51, 0xC8, 0x2A, 0x47, 0x1D, 0x95, 0xE0, 0xE8, 0x66, 0x90, 0xC3, 0xE2, 0x30, 0xD1, 0x57,
+	0x4E, 0x53, 0x70, 0x9C, 0x13, 0x5A, 0xE8, 0xBA, 0xC7, 0xEF, 0x67, 0x3E, 0x2B, 0xD8, 0xD3, 0xAF,
+	0x29, 0xC5, 0xB8, 0xCD, 0xAB, 0x5D, 0x2B, 0xAF, 0x24, 0x7D, 0xDD, 0xF0, 0x7B, 0xE2, 0x1F, 0xEC,
+	0xED, 0xFB, 0x6E, 0xFE, 0xC2, 0x7E, 0x33, 0xF1, 0x0F, 0xC0, 0x8D, 0x06, 0xDF, 0x4C, 0x7B, 0xFB,
+	0x1B, 0x8B, 0x8F, 0x10, 0xE9, 0x36, 0xC8, 0x5B, 0xEC, 0xDA, 0x9F, 0x90, 0xCD, 0xE5, 0xFF, 0x00,
+	0xFB, 0x35, 0xF9, 0xC7, 0xFF, 0x00, 0x04, 0xF4, 0xFD, 0xB3, 0x2E, 0xFF, 0x00, 0x61, 0x5F, 0xD9,
+	0xEF, 0xE3, 0x07, 0x83, 0x7C, 0x45, 0x03, 0x37, 0x89, 0x35, 0x6D, 0x49, 0x63, 0xD2, 0xF4, 0xF9,
+	0x1B, 0x6B, 0x2E, 0xED, 0xCA, 0xDF, 0xFA, 0x15, 0x7E, 0x9E, 0x7F, 0xC1, 0x2B, 0x7F, 0x61, 0x9B,
+	0xBF, 0xD8, 0x7B, 0xF6, 0x7F, 0xB8, 0xF0, 0x27, 0x88, 0x2F, 0xE1, 0xBA, 0xD4, 0x35, 0xCB, 0xC5,
+	0xBE, 0xBF, 0x58, 0xD7, 0x85, 0xDC, 0xBB, 0x59, 0x48, 0xAF, 0xCC, 0xBF, 0xF8, 0x28, 0x67, 0xEC,
+	0x39, 0xFB, 0x48, 0x6A, 0x9F, 0xF0, 0x50, 0xAF, 0x10, 0x6B, 0x7F, 0x0C, 0x7E, 0x00, 0xF8, 0x82,
+	0xFB, 0xC3, 0x3A, 0x97, 0x88, 0xED, 0xE5, 0x5B, 0xCB, 0x1B, 0x0D, 0xD6, 0xDE, 0x5E, 0xE5, 0xDC,
+	0xD5, 0x87, 0x08, 0xE2, 0xB8, 0x6E, 0xA6, 0x65, 0x98, 0x64, 0xF5, 0xF1, 0x16, 0xC2, 0x54, 0x6A,
+	0xA4, 0x25, 0x2F, 0xB4, 0xE9, 0xB4, 0xD2, 0xF4, 0xB7, 0xDE, 0xB5, 0x33, 0xAD, 0x2C, 0x5C, 0x72,
+	0xE8, 0x55, 0x6B, 0xDF, 0x8E, 0xAD, 0x2F, 0x3D, 0x0A, 0xBE, 0x3A, 0xFD, 0x8E, 0xFE, 0x21, 0x78,
+	0x1B, 0xFE, 0x09, 0xE7, 0xE0, 0x7F, 0xDB, 0x6F, 0xC3, 0x36, 0x73, 0x59, 0xF8, 0xA2, 0xD7, 0x5C,
+	0xBC, 0xBF, 0xF1, 0x1D, 0xC2, 0xFF, 0x00, 0xAC, 0x86, 0x16, 0x9B, 0xF7, 0x75, 0xB7, 0xFB, 0x6A,
+	0x7E, 0xD0, 0x57, 0x3F, 0xB7, 0x27, 0xED, 0x45, 0xF0, 0x6F, 0xE0, 0xEE, 0x83, 0x7E, 0xD7, 0x3A,
+	0x4D, 0xD6, 0x93, 0xA4, 0xC5, 0x74, 0xCB, 0xF3, 0x2C, 0x77, 0x4D, 0x1A, 0xF9, 0x8D, 0x5F, 0xA8,
+	0xBF, 0xB4, 0x9F, 0xEC, 0xFB, 0x75, 0xAF, 0xFE, 0xC0, 0x7A, 0xF7, 0xC1, 0x1F, 0x06, 0x68, 0xEA,
+	0xD7, 0x37, 0x9E, 0x19, 0x8E, 0x28, 0xAC, 0x96, 0x3D, 0xDF, 0xBC, 0xDA, 0xBB, 0x94, 0x2D, 0x7E,
+	0x6F, 0xFF, 0x00, 0xC1, 0x1B, 0x3F, 0x62, 0x2F, 0x8C, 0xD6, 0x9F, 0xB5, 0xD6, 0xA1, 0xAC, 0xFC,
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+	0x37, 0x32, 0x8F, 0x95, 0x9B, 0x75, 0x48, 0x9D, 0x69, 0x1F, 0xEF, 0x55, 0x47, 0xCC, 0x96, 0xBB,
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+	0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66,
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+	0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9,
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+	0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8,
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+	0x70, 0xD7, 0x1E, 0x5F, 0xFC, 0xF4, 0xFF, 0x00, 0x76, 0xBE, 0x53, 0xD5, 0x3F, 0xE0, 0xA3, 0x9F,
+	0xB5, 0x4D, 0x97, 0xFC, 0x15, 0xD3, 0x5C, 0xFD, 0x94, 0xFF, 0x00, 0xE1, 0x28, 0xB3, 0x6F, 0x04,
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+	0xC3, 0xB6, 0x7A, 0x5D, 0xF2, 0x5A, 0xC8, 0xCD, 0xF2, 0xC9, 0x1E, 0xEF, 0x95, 0x96, 0xAF, 0xEB,
+	0x7B, 0x1B, 0xFE, 0x0B, 0xFD, 0xE2, 0x68, 0x66, 0xFB, 0xCD, 0xAC, 0xB6, 0xDD, 0xBF, 0xF5, 0xCE,
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+	0x41, 0x0B, 0xEC, 0xDD, 0xBA, 0x35, 0x34, 0xE3, 0x2C, 0x4A, 0x32, 0x93, 0x70, 0xCD, 0x8D, 0xB5,
+	0xF3, 0xFF, 0x00, 0xED, 0xCF, 0xFB, 0x7D, 0xFC, 0x34, 0xFD, 0x85, 0x3E, 0x1B, 0x69, 0xFA, 0xC7,
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+	0x73, 0xC3, 0xDF, 0xB1, 0xEE, 0x9E, 0xFA, 0x4E, 0xE6, 0x7B, 0x2B, 0xA9, 0x34, 0x9B, 0x8F, 0x9A,
+	0x1E, 0xCC, 0xDF, 0xF0, 0x1A, 0xFC, 0xCF, 0x23, 0xE0, 0x7E, 0x20, 0xE2, 0x0C, 0x37, 0xD6, 0x68,
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+	0xE0, 0xA8, 0x1A, 0x3F, 0xED, 0xAD, 0x6E, 0xDE, 0x00, 0xF1, 0xC6, 0x97, 0xFD, 0x97, 0xE3, 0x8B,
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+	0xF2, 0x51, 0x8D, 0x95, 0xB5, 0xE6, 0x76, 0x4D, 0x76, 0xB6, 0xFD, 0x02, 0x38, 0xDC, 0x34, 0xA8,
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+	0x6C, 0x6E, 0xF2, 0xBF, 0x92, 0xFF, 0x00, 0x32, 0xAF, 0xFC, 0xB4, 0xAF, 0xC7, 0xD8, 0xBF, 0xE0,
+	0xBC, 0x9F, 0xF0, 0x50, 0x0F, 0x87, 0x5E, 0x28, 0xD1, 0xEF, 0xFE, 0x3F, 0x7E, 0xCD, 0x7A, 0x6E,
+	0x83, 0xE1, 0xBB, 0x8B, 0x8D, 0xB7, 0x97, 0x13, 0x69, 0xD3, 0x45, 0x2B, 0x2F, 0xFD, 0x33, 0xDD,
+	0xF7, 0x9A, 0xBF, 0x48, 0x3C, 0x1D, 0xFB, 0x6B, 0x7C, 0x1E, 0xF1, 0x77, 0xEC, 0xC3, 0x75, 0xFB,
+	0x57, 0xDB, 0x6A, 0x13, 0x0F, 0x0D, 0x69, 0xDA, 0x6B, 0xDC, 0xDF, 0x11, 0x1F, 0xCE, 0x1A, 0x35,
+	0xDC, 0xEA, 0xAB, 0xFD, 0xEA, 0xD3, 0x39, 0xE0, 0x8E, 0x20, 0xC8, 0x69, 0xD3, 0xAB, 0x89, 0xA6,
+	0xA5, 0x0A, 0x8D, 0x46, 0x32, 0x84, 0x94, 0xE2, 0xE4, 0xF4, 0x4A, 0xEB, 0x4B, 0xBE, 0xC4, 0xD3,
+	0xC6, 0x50, 0xAD, 0x55, 0xD2, 0x8D, 0xEF, 0x6D, 0x9E, 0x87, 0xB1, 0x32, 0xED, 0x42, 0x17, 0xE5,
+	0x6D, 0xD4, 0x26, 0xE5, 0x46, 0x55, 0x7F, 0x9B, 0xF8, 0xAB, 0xF2, 0x6F, 0xE2, 0x07, 0xFC, 0x17,
+	0x77, 0xF6, 0xB5, 0xF8, 0x91, 0xE2, 0xD9, 0xB5, 0x2F, 0xD8, 0xA3, 0xF6, 0x78, 0x8F, 0xC4, 0xDE,
+	0x13, 0x5D, 0xDF, 0xE9, 0x97, 0xDA, 0x5C, 0xCF, 0x34, 0x6D, 0xFD, 0xD6, 0xDB, 0x5E, 0xB5, 0xFF,
+	0x00, 0x04, 0xEA, 0xFF, 0x00, 0x82, 0xAA, 0x7E, 0xD6, 0x5F, 0x1F, 0x7E, 0x3D, 0x2F, 0xC1, 0x5F,
+	0xDA, 0xA3, 0xE0, 0x12, 0xF8, 0x5E, 0x5D, 0x49, 0x19, 0xF4, 0x8B, 0x8B, 0x7D, 0x3E, 0x44, 0x56,
+	0x55, 0x5F, 0x9B, 0x71, 0x6A, 0xEC, 0xC5, 0x78, 0x73, 0xC4, 0xF8, 0x2C, 0x14, 0xF1, 0x55, 0x79,
+	0x17, 0xB3, 0x8F, 0x34, 0xA1, 0xCE, 0xBD, 0xA2, 0x5A, 0x6F, 0x0D, 0xEF, 0xD7, 0xD3, 0x53, 0x3F,
+	0xED, 0x2C, 0x24, 0xA5, 0xA3, 0xBA, 0xBD, 0x93, 0xB6, 0x97, 0xDB, 0x7F, 0x5D, 0x0F, 0xD0, 0xC8,
+	0xF0, 0xCD, 0xF2, 0x26, 0xD5, 0x5A, 0x6C, 0x32, 0x46, 0xA1, 0xBC, 0xA7, 0xFF, 0x00, 0x79, 0xAB,
+	0xE4, 0x1F, 0xF8, 0x28, 0xB7, 0xFC, 0x15, 0x23, 0x43, 0xFD, 0x8F, 0x26, 0xB5, 0xF8, 0x73, 0xE0,
+	0x0D, 0x35, 0x75, 0xCF, 0x1C, 0x5F, 0x33, 0x2D, 0xBE, 0x92, 0xB0, 0xF9, 0x8B, 0xBB, 0xF8, 0x77,
+	0x2A, 0xFC, 0xD5, 0xF1, 0xF4, 0xDF, 0xF0, 0x5B, 0x9F, 0xF8, 0x2A, 0x2E, 0x81, 0xE4, 0x78, 0x87,
+	0xC5, 0x9F, 0xB2, 0x3E, 0x9F, 0x63, 0xA1, 0xAC, 0xFB, 0xAF, 0xAE, 0xE6, 0xD2, 0xEE, 0x17, 0xCB,
+	0x87, 0xFB, 0xD9, 0xAC, 0x32, 0x9F, 0x0F, 0xB8, 0x8B, 0x3A, 0xC1, 0xC3, 0x17, 0x42, 0x31, 0x84,
+	0x2A, 0x69, 0x1E, 0x79, 0xA8, 0x39, 0xF4, 0xF7, 0x53, 0xD5, 0xF6, 0xB9, 0xB5, 0x6C, 0x65, 0x1A,
+	0x12, 0xE4, 0x94, 0xB5, 0x5B, 0xA5, 0xFA, 0xFA, 0xF4, 0x3F, 0x60, 0x55, 0x40, 0x3B, 0xD9, 0xB3,
+	0xBB, 0xF8, 0xA9, 0xC4, 0x65, 0x76, 0x1F, 0xBB, 0x5E, 0x07, 0xFB, 0x01, 0x7E, 0xDE, 0xFF, 0x00,
+	0x0C, 0xFF, 0x00, 0x6F, 0x3F, 0x84, 0xF7, 0x1E, 0x3E, 0xF0, 0x3C, 0x57, 0x10, 0xDC, 0xE9, 0x57,
+	0x5F, 0x62, 0xD6, 0x6D, 0x6E, 0x21, 0xDB, 0x8B, 0x8D, 0xBF, 0x36, 0xCF, 0xEF, 0x2D, 0x7B, 0xE2,
+	0xCD, 0xBA, 0x35, 0x74, 0x4F, 0xBD, 0x5F, 0x31, 0x8F, 0xC0, 0xE2, 0xB2, 0xBC, 0x64, 0xF0, 0x78,
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+	0x75, 0x4D, 0x7C, 0xFE, 0x62, 0x6D, 0x48, 0xD4, 0xBE, 0x3E, 0xEF, 0xFE, 0x3D, 0x51, 0xF9, 0x91,
+	0x9F, 0x9D, 0x3E, 0xEB, 0x7F, 0x0D, 0x7C, 0x91, 0xFF, 0x00, 0x05, 0x2A, 0xFF, 0x00, 0x82, 0x9E,
+	0xE8, 0xFF, 0x00, 0xB1, 0x30, 0xD3, 0xBC, 0x1F, 0xE0, 0xDD, 0x2D, 0x75, 0x8F, 0x16, 0x6A, 0xCC,
+	0xC9, 0x6F, 0xA7, 0xB2, 0x17, 0x48, 0xDB, 0x6F, 0xCB, 0xBB, 0x6F, 0xDD, 0xAF, 0x8D, 0xEF, 0xBF,
+	0xE0, 0xB5, 0x3F, 0xF0, 0x56, 0x0D, 0x3E, 0xD5, 0xF5, 0x29, 0xFF, 0x00, 0x63, 0x6B, 0x36, 0xB5,
+	0xDB, 0xE6, 0xA4, 0xCB, 0xA3, 0x5C, 0x6D, 0x68, 0xFB, 0x35, 0x7D, 0x36, 0x4F, 0xC0, 0x3C, 0x47,
+	0x9E, 0x61, 0x56, 0x27, 0x0E, 0xA9, 0xC6, 0x12, 0xD9, 0xD4, 0x92, 0x87, 0x33, 0xF2, 0xBE, 0xE6,
+	0x75, 0x71, 0x54, 0x68, 0xCB, 0x95, 0xB7, 0xB6, 0xCB, 0x56, 0x7E, 0xC1, 0x6D, 0x48, 0xFF, 0x00,
+	0x83, 0x23, 0xFB, 0xD4, 0x42, 0x55, 0x7E, 0xE3, 0xFF, 0x00, 0xBA, 0xB5, 0xF0, 0x87, 0xC5, 0xCF,
+	0xF8, 0x29, 0x57, 0xED, 0x2B, 0x67, 0xFF, 0x00, 0x04, 0xEF, 0x87, 0xF6, 0xAE, 0xF8, 0x33, 0xF0,
+	0xEB, 0x49, 0xBC, 0xF1, 0x55, 0xAE, 0xA5, 0x0D, 0xAE, 0xB9, 0xA2, 0xEA, 0x11, 0xB7, 0x95, 0x6F,
+	0xB9, 0x77, 0x3F, 0xCA, 0xBF, 0x37, 0xCB, 0x5E, 0xA3, 0xFF, 0x00, 0x04, 0xE1, 0xFD, 0xB9, 0x75,
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+	0xD8, 0xEA, 0x96, 0xBA, 0x7F, 0xFA, 0xA8, 0xE4, 0xDA, 0xCD, 0xFF, 0x00, 0xB2, 0xD7, 0x1E, 0x33,
+	0x84, 0xB3, 0xCC, 0x0E, 0x5B, 0x57, 0x1F, 0x5A, 0x0B, 0x92, 0x94, 0xDD, 0x39, 0x72, 0xBB, 0xB8,
+	0xCF, 0xA2, 0x6B, 0xB3, 0xE8, 0xFA, 0x93, 0x1C, 0x6E, 0x1E, 0x55, 0x21, 0x1B, 0xBB, 0xD4, 0x4D,
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+	0x86, 0xD8, 0xE9, 0xB5, 0x9B, 0xEE, 0xB5, 0x7E, 0x5B, 0xFC, 0x33, 0xFF, 0x00, 0x82, 0xE0, 0xFC,
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+	0x7A, 0xB6, 0xA9, 0xAD, 0x6A, 0xDF, 0x66, 0x5B, 0x7D, 0x4B, 0x73, 0x2F, 0x96, 0xCB, 0xB8, 0x32,
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+	0x94, 0xA1, 0xAA, 0x69, 0xA7, 0xAE, 0xAF, 0x65, 0x65, 0xAB, 0x5D, 0x02, 0x9E, 0x33, 0x0F, 0x5A,
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+	0x37, 0x7E, 0xC9, 0x9F, 0xB2, 0x31, 0xF8, 0x9B, 0xF0, 0x0A, 0xF6, 0x18, 0x35, 0xEF, 0xED, 0xCB,
+	0x7B, 0x7F, 0x32, 0x4B, 0x5F, 0x35, 0x7C, 0xB6, 0xDD, 0xBB, 0xE5, 0xAD, 0x4F, 0xF8, 0x25, 0xD7,
+	0xED, 0x13, 0xF1, 0x7F, 0xF6, 0x95, 0xFD, 0x9F, 0x61, 0xF1, 0xB7, 0xC6, 0x89, 0xE3, 0x9B, 0x54,
+	0x65, 0x53, 0xE6, 0x47, 0x6F, 0xE5, 0x2F, 0xFD, 0xF3, 0x5E, 0x41, 0xFB, 0x5D, 0x7E, 0xDC, 0x3F,
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+	0xAE, 0xF8, 0x8B, 0x57, 0xBC, 0xB3, 0x65, 0xD0, 0x75, 0x2B, 0x7F, 0x36, 0xC5, 0x63, 0x99, 0x77,
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+	0xFB, 0x24, 0x43, 0xF1, 0x77, 0x55, 0xF8, 0x79, 0xA0, 0xF8, 0x7E, 0xF5, 0xB4, 0xA9, 0x2E, 0x97,
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+	0xBD, 0x4E, 0x96, 0x4D, 0xED, 0xB3, 0x6D, 0x7E, 0x55, 0xFE, 0xCE, 0xDF, 0xF0, 0x5F, 0x5F, 0x8C,
+	0xDA, 0xFF, 0x00, 0x8D, 0x7C, 0x5B, 0xE1, 0x2F, 0x8D, 0x5F, 0x05, 0x56, 0xF2, 0x4B, 0x3B, 0x89,
+	0x20, 0xF0, 0xE4, 0x7E, 0x0F, 0xB1, 0x92, 0xE1, 0xD9, 0x95, 0x99, 0x7F, 0x7F, 0xFD, 0xDA, 0xE4,
+	0x75, 0x4F, 0xF8, 0x2F, 0x2F, 0xED, 0xD7, 0xF0, 0xF7, 0xC7, 0x90, 0xDD, 0x7C, 0x5D, 0xFD, 0x9C,
+	0x2C, 0x74, 0x5F, 0x07, 0xB6, 0xA5, 0xB6, 0x4B, 0xCB, 0xCD, 0x3A, 0x68, 0x67, 0x6B, 0x7D, 0xDF,
+	0xC3, 0xBB, 0xFE, 0x5A, 0x6D, 0xA9, 0x8F, 0x85, 0x9C, 0x5D, 0x2C, 0x67, 0xD5, 0x14, 0x21, 0xCC,
+	0xA2, 0xA4, 0x93, 0x9A, 0xF7, 0x93, 0x57, 0x5C, 0xB7, 0xD6, 0x4F, 0xC8, 0x75, 0x33, 0x0A, 0x14,
+	0x63, 0x37, 0x2B, 0xBE, 0x57, 0x67, 0xA7, 0xF5, 0xA1, 0xFB, 0x00, 0x59, 0x87, 0xEE, 0x73, 0xB4,
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+	0xA6, 0x3E, 0x1A, 0xF8, 0x97, 0xF6, 0x74, 0xB5, 0xFD, 0xA3, 0xE5, 0xD5, 0xE3, 0x5D, 0x0C, 0xE8,
+	0x9F, 0xDA, 0x53, 0xB6, 0xE5, 0xF3, 0x11, 0x7C, 0xBD, 0xDE, 0x5E, 0xDF, 0xF9, 0xE9, 0xFE, 0xCD,
+	0x7E, 0x75, 0xFC, 0x55, 0xFF, 0x00, 0x82, 0xEF, 0xFE, 0xD4, 0x1F, 0x11, 0xFC, 0x55, 0xF6, 0xFF,
+	0x00, 0xD8, 0x67, 0xF6, 0x74, 0x9B, 0xC4, 0x9E, 0x17, 0x85, 0x99, 0x6E, 0x2E, 0xB5, 0x4D, 0x22,
+	0x66, 0x95, 0x5B, 0xF8, 0x7E, 0xED, 0x78, 0xB9, 0x2F, 0x08, 0xE7, 0x99, 0xF5, 0x6A, 0x94, 0xB0,
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+	0x66, 0x8D, 0xB6, 0x3A, 0xAB, 0x7F, 0xCF, 0x4A, 0x36, 0xAE, 0xDD, 0xBF, 0x7B, 0x6D, 0x7E, 0x63,
+	0x7E, 0xC9, 0x7F, 0xF0, 0x5C, 0x4F, 0x8C, 0xBE, 0x22, 0xF8, 0xD7, 0xA6, 0xFC, 0x22, 0xFD, 0xB1,
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+	0x9A, 0x05, 0x92, 0x19, 0x15, 0xBE, 0xF2, 0xB7, 0xDD, 0xAE, 0x5C, 0xFB, 0x86, 0xB3, 0x7E, 0x1B,
+	0xAD, 0x0A, 0x78, 0xD8, 0x25, 0xCC, 0xAF, 0x19, 0x45, 0xA9, 0x46, 0x4B, 0xAF, 0x2C, 0x96, 0x8C,
+	0xAA, 0x38, 0x8A, 0x38, 0x89, 0x4A, 0x11, 0x7A, 0xAD, 0xD3, 0xE8, 0x3B, 0x50, 0xBC, 0xB6, 0xD3,
+	0xF4, 0xD9, 0xB5, 0x19, 0x39, 0x5B, 0x78, 0x99, 0xDF, 0xFE, 0x03, 0x5F, 0x39, 0xFC, 0x21, 0xFF,
+	0x00, 0x82, 0x95, 0xFC, 0x22, 0xF8, 0xC7, 0xFB, 0x48, 0xDC, 0x7E, 0xCD, 0x1E, 0x1A, 0xB1, 0x91,
+	0x75, 0xA8, 0x7C, 0xCD, 0xD2, 0x34, 0xCA, 0x55, 0x76, 0xAE, 0xE6, 0xE2, 0xBA, 0x3F, 0xDB, 0xE7,
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+	0xD6, 0x37, 0x7D, 0x9D, 0x2C, 0xDA, 0x06, 0x91, 0x7C, 0xB6, 0x56, 0xDC, 0xDB, 0x56, 0xBF, 0x0E,
+	0xFE, 0x00, 0x7E, 0xD3, 0xDF, 0xB4, 0x67, 0xC2, 0xAF, 0xDA, 0xE6, 0xE3, 0xF6, 0x83, 0xF8, 0x6B,
+	0xF0, 0xB6, 0xDF, 0x56, 0xF1, 0xE5, 0xC7, 0x9D, 0xE7, 0x68, 0x2D, 0x6A, 0xCC, 0xBF, 0x32, 0xED,
+	0x6F, 0x95, 0x7E, 0x6F, 0xBB, 0x5F, 0x61, 0xC0, 0xFC, 0x0B, 0x47, 0x89, 0x72, 0x8C, 0x66, 0x2A,
+	0xB5, 0x93, 0x84, 0x5F, 0xB3, 0x7C, 0xEA, 0x29, 0x4E, 0xDF, 0x6D, 0x6E, 0xA2, 0xD7, 0x57, 0xD4,
+	0xE7, 0xC6, 0xE3, 0x16, 0x1E, 0x9C, 0x5C, 0x6F, 0x79, 0x34, 0xAF, 0xE5, 0xFE, 0x7D, 0x8F, 0xDB,
+	0x7F, 0xF8, 0x28, 0xCF, 0xC6, 0xCF, 0x1F, 0xFE, 0xCE, 0xFF, 0x00, 0xB2, 0x37, 0x8A, 0xBE, 0x29,
+	0x7C, 0x2F, 0xD4, 0x61, 0xB3, 0xD7, 0x34, 0xDB, 0x3D, 0xF6, 0x92, 0x5C, 0x43, 0xE6, 0x2E, 0xED,
+	0xDF, 0xDD, 0xAF, 0x37, 0xFF, 0x00, 0x82, 0x33, 0xFE, 0xD6, 0xBF, 0x1A, 0x3F, 0x6C, 0x0F, 0xD9,
+	0x95, 0xBE, 0x25, 0xFC, 0x6F, 0xD5, 0xED, 0xEF, 0xB5, 0x5F, 0xED, 0x49, 0xA1, 0xFB, 0x45, 0xAD,
+	0xBA, 0xC4, 0xBB, 0x57, 0xF8, 0x76, 0xD7, 0xCC, 0x3E, 0x35, 0xFD, 0xB1, 0xFF, 0x00, 0x6B, 0x0F,
+	0xDA, 0xFF, 0x00, 0xF6, 0x09, 0xF8, 0xD1, 0x0F, 0xED, 0x43, 0xF0, 0x72, 0x1F, 0x08, 0xBE, 0x87,
+	0xA3, 0xC3, 0x26, 0x97, 0xE5, 0xD9, 0xC9, 0x17, 0xDA, 0x19, 0x9B, 0xE6, 0x5F, 0x9B, 0xEF, 0x57,
+	0x99, 0xFF, 0x00, 0xC1, 0x33, 0x3F, 0xE0, 0xA0, 0xBE, 0x24, 0xFD, 0x95, 0xBF, 0x62, 0x8B, 0x9F,
+	0x85, 0xBF, 0x08, 0xFE, 0x11, 0x6B, 0x5E, 0x26, 0xF1, 0xA7, 0xDB, 0xE6, 0xB8, 0xB7, 0xF2, 0x74,
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+	0x0E, 0xE9, 0x53, 0x9E, 0x2A, 0x9D, 0x6A, 0x6B, 0xDA, 0x29, 0x26, 0x94, 0x64, 0xAF, 0xA4, 0xF6,
+	0xB6, 0xB7, 0x96, 0xBA, 0x33, 0x9F, 0x11, 0x8C, 0x75, 0x2B, 0x61, 0xAB, 0x46, 0x4E, 0x34, 0xDA,
+	0x9F, 0x32, 0x6A, 0xD7, 0x69, 0xA4, 0xB4, 0x3F, 0x6A, 0x95, 0x7E, 0x6F, 0x93, 0x8A, 0x73, 0x2A,
+	0x65, 0x7E, 0x5C, 0x05, 0xAF, 0xCA, 0x6F, 0xD9, 0x57, 0xFE, 0x0B, 0xB7, 0xFB, 0x48, 0xEA, 0x7F,
+	0x1F, 0x74, 0xDF, 0x85, 0xDF, 0xB6, 0x17, 0xC2, 0x1D, 0x2F, 0xC3, 0x76, 0x3A, 0xAD, 0xC2, 0xDA,
+	0xDB, 0xFD, 0x86, 0xDA, 0x44, 0x9F, 0xED, 0x0C, 0xDB, 0x57, 0xE5, 0x6F, 0xE1, 0xAF, 0xBF, 0xFF,
+	0x00, 0x6C, 0x2F, 0xDA, 0xF7, 0xE1, 0x37, 0xEC, 0x6F, 0xF0, 0x7E, 0xE3, 0xE3, 0x27, 0xC5, 0x3B,
+	0xE9, 0x8D, 0xA5, 0xBE, 0xD1, 0x0D, 0xA5, 0x8F, 0xCF, 0x2D, 0xC3, 0x37, 0x4D, 0xAB, 0xFC, 0x42,
+	0xBE, 0x1F, 0x38, 0xE0, 0xBE, 0x20, 0xC9, 0xF3, 0x0A, 0x58, 0x1A, 0xF4, 0xF9, 0xAA, 0x56, 0xD6,
+	0x1C, 0x8F, 0x99, 0x4B, 0x5B, 0x5A, 0x2D, 0x6F, 0xAF, 0x43, 0xD0, 0xA3, 0x88, 0xA7, 0x88, 0x94,
+	0xB9, 0x37, 0x5B, 0xDF, 0xB7, 0x77, 0xE5, 0x63, 0xD6, 0x8B, 0xC6, 0xC1, 0x9B, 0x66, 0xE6, 0xA6,
+	0xC6, 0xC0, 0xB7, 0x27, 0x72, 0xFF, 0x00, 0x77, 0xFB, 0xB5, 0xF9, 0x17, 0xAD, 0x7F, 0xC1, 0x6E,
+	0xFF, 0x00, 0xE0, 0xA3, 0xBE, 0x31, 0xD7, 0xAE, 0xF5, 0xBF, 0x81, 0x1F, 0xB2, 0x85, 0xBE, 0xA9,
+	0xE1, 0x29, 0x79, 0xD2, 0x75, 0x0B, 0x8D, 0x26, 0x66, 0x79, 0x17, 0xF8, 0xB7, 0x6D, 0xAF, 0xA3,
+	0xFF, 0x00, 0xE0, 0x9A, 0xDF, 0xF0, 0x57, 0x0B, 0x8F, 0xDA, 0xCF, 0xC6, 0x1A, 0x87, 0xC1, 0xCF,
+	0x8E, 0x3E, 0x1C, 0xB7, 0xF0, 0xEF, 0x8B, 0xEC, 0x6D, 0xFC, 0xDF, 0xB3, 0xC6, 0xAD, 0x1C, 0x52,
+	0x36, 0xED, 0xBE, 0x5A, 0xEE, 0xFB, 0xCD, 0xFE, 0xCD, 0x7A, 0x79, 0x87, 0x87, 0x5C, 0x51, 0x96,
+	0xE0, 0x6A, 0x62, 0xEA, 0xC6, 0x12, 0x54, 0xED, 0xCC, 0xA3, 0x35, 0x29, 0xC2, 0xFF, 0x00, 0xCD,
+	0x15, 0xAA, 0x5D, 0xDF, 0x43, 0x0F, 0xED, 0x0C, 0x37, 0x32, 0xBB, 0xB5, 0xFA, 0xDB, 0x4F, 0xBC,
+	0xFB, 0x9E, 0x25, 0xE4, 0xB6, 0xCE, 0x68, 0xF3, 0x1C, 0x37, 0xDC, 0xDD, 0xB7, 0xF8, 0x7F, 0xBB,
+	0x4D, 0x12, 0xF9, 0x0A, 0xAE, 0x77, 0x36, 0xEF, 0xEE, 0xD7, 0x99, 0xFE, 0xD7, 0xDF, 0xB5, 0x77,
+	0xC3, 0x5F, 0xD8, 0xD3, 0xE0, 0x9E, 0xA5, 0xF1, 0xBB, 0xE2, 0x7C, 0x93, 0x1B, 0x0B, 0x16, 0x54,
+	0xFB, 0x3D, 0x9A, 0xEE, 0x96, 0x46, 0x6F, 0x95, 0x76, 0xAD, 0x7C, 0x55, 0x1A, 0x15, 0xB1, 0x55,
+	0xE3, 0x46, 0x8A, 0x72, 0x94, 0x9D, 0x92, 0x5A, 0xB6, 0xDF, 0x64, 0x76, 0xC7, 0xD3, 0xFC, 0xBD,
+	0x4F, 0x4E, 0x66, 0xDD, 0xFE, 0xEF, 0xF1, 0x2D, 0x39, 0xBF, 0x78, 0xBE, 0x72, 0x3D, 0x7E, 0x45,
+	0xF8, 0x8B, 0xFE, 0x0B, 0x85, 0xFF, 0x00, 0x05, 0x11, 0xF1, 0xB6, 0xB7, 0x73, 0xE2, 0x4F, 0xD9,
+	0xDB, 0xF6, 0x58, 0xB3, 0xD6, 0xBC, 0x1B, 0x27, 0xFC, 0x82, 0xF5, 0x29, 0x34, 0xBB, 0x86, 0x69,
+	0xBD, 0x7E, 0x65, 0xF9, 0x6B, 0xEA, 0x1F, 0xF8, 0x25, 0x9F, 0xFC, 0x14, 0x53, 0xE3, 0xBF, 0xED,
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+	0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5,
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+	0xF4, 0xEF, 0xF8, 0x39, 0x17, 0xF8, 0x3F, 0xE0, 0x9C, 0x5E, 0x31, 0xFF, 0x00, 0xC1, 0x5C, 0x34,
+	0x7F, 0xC3, 0xD3, 0xFF, 0x00, 0xE0, 0xE4, 0x8F, 0xFA, 0x47, 0x17, 0x8C, 0x3F, 0xF0, 0x57, 0x0D,
+	0x7E, 0xBB, 0x8D, 0x77, 0x5D, 0x75, 0xDE, 0x9A, 0xBD, 0xC2, 0x86, 0xFE, 0xF4, 0x94, 0xBF, 0xDB,
+	0x9A, 0xF7, 0xFD, 0x06, 0x27, 0xFF, 0x00, 0xBF, 0x94, 0x7F, 0xC4, 0x4D, 0xC5, 0x7F, 0xD0, 0x3C,
+	0x7F, 0xAF, 0x98, 0xBF, 0xD5, 0xF9, 0x7F, 0x3A, 0xFC, 0x4F, 0xC8, 0x7F, 0xF8, 0x7A, 0x7F, 0xFC,
+	0x1C, 0x91, 0xFF, 0x00, 0x48, 0xE2, 0xF1, 0x87, 0xFE, 0x0A, 0xE1, 0xA3, 0xFE, 0x1E, 0x9F, 0xFF,
+	0x00, 0x07, 0x24, 0x7F, 0xD2, 0x38, 0xBC, 0x61, 0xFF, 0x00, 0x82, 0xB8, 0x6B, 0xF5, 0xE3, 0xFB,
+	0x73, 0x5E, 0xFF, 0x00, 0xA0, 0xC4, 0xFF, 0x00, 0xF7, 0xF2, 0x8F, 0xED, 0xCD, 0x7B, 0xFE, 0x83,
+	0x13, 0xFF, 0x00, 0xDF, 0xCA, 0x7F, 0xF1, 0x13, 0x71, 0x7F, 0xF4, 0x0F, 0x1F, 0xEB, 0xE6, 0x1F,
+	0xEA, 0xFC, 0xBF, 0xE7, 0xE2, 0xFC, 0x7F, 0xC8, 0xFC, 0x87, 0xFF, 0x00, 0x87, 0xA7, 0xFF, 0x00,
+	0xC1, 0xC9, 0x1F, 0xF4, 0x8E, 0x2F, 0x18, 0x7F, 0xE0, 0xAE, 0x1A, 0x3F, 0xE1, 0xE9, 0xFF, 0x00,
+	0xF0, 0x72, 0x47, 0xFD, 0x23, 0x8B, 0xC6, 0x1F, 0xF8, 0x2B, 0x86, 0xBF, 0x5E, 0x3F, 0xB7, 0x35,
+	0xEF, 0xFA, 0x0C, 0x4F, 0xFF, 0x00, 0x7F, 0x28, 0xFE, 0xDC, 0xD7, 0xBF, 0xE8, 0x31, 0x3F, 0xFD,
+	0xFC, 0xA3, 0xFE, 0x22, 0x6E, 0x2F, 0xFE, 0x81, 0xE3, 0xFD, 0x7C, 0xC3, 0xFD, 0x5F, 0x97, 0xFC,
+	0xFC, 0x5F, 0x8F, 0xF9, 0x1F, 0x90, 0xFF, 0x00, 0xF0, 0xF4, 0xFF, 0x00, 0xF8, 0x39, 0x23, 0xFE,
+	0x91, 0xC5, 0xE3, 0x0F, 0xFC, 0x15, 0xC3, 0x47, 0xFC, 0x3D, 0x3F, 0xFE, 0x0E, 0x48, 0xFF, 0x00,
+	0xA4, 0x71, 0x78, 0xC3, 0xFF, 0x00, 0x05, 0x70, 0xD7, 0xEB, 0xC7, 0xF6, 0xE6, 0xBD, 0xFF, 0x00,
+	0x41, 0x89, 0xFF, 0x00, 0xEF, 0xE5, 0x1F, 0xDB, 0x9A, 0xF7, 0xFD, 0x06, 0x27, 0xFF, 0x00, 0xBF,
+	0x94, 0x7F, 0xC4, 0x4D, 0xC5, 0xFF, 0x00, 0xD0, 0x3C, 0x7F, 0xAF, 0x98, 0x7F, 0xAB, 0xF2, 0xFF,
+	0x00, 0x9F, 0x8B, 0xF1, 0xFF, 0x00, 0x23, 0xF2, 0x1F, 0xFE, 0x1E, 0x9F, 0xFF, 0x00, 0x07, 0x24,
+	0x7F, 0xD2, 0x38, 0xBC, 0x61, 0xFF, 0x00, 0x82, 0xB8, 0x68, 0xFF, 0x00, 0x87, 0xA7, 0xFF, 0x00,
+	0xC1, 0xC9, 0x1F, 0xF4, 0x8E, 0x2F, 0x18, 0x7F, 0xE0, 0xAE, 0x1A, 0xFD, 0x78, 0xFE, 0xDC, 0xD7,
+	0xBF, 0xE8, 0x31, 0x3F, 0xFD, 0xFC, 0xA3, 0xFB, 0x73, 0x5E, 0xFF, 0x00, 0xA0, 0xC4, 0xFF, 0x00,
+	0xF7, 0xF2, 0x8F, 0xF8, 0x89, 0xB8, 0xBF, 0xFA, 0x07, 0x8F, 0xF5, 0xF3, 0x0F, 0xF5, 0x7E, 0x5F,
+	0xF3, 0xF1, 0x7E, 0x3F, 0xE4, 0x7E, 0x43, 0xFF, 0x00, 0xC3, 0xD3, 0xFF, 0x00, 0xE0, 0xE4, 0x8F,
+	0xFA, 0x47, 0x17, 0x8C, 0x3F, 0xF0, 0x57, 0x0D, 0x1F, 0xF0, 0xF4, 0xFF, 0x00, 0xF8, 0x39, 0x23,
+	0xFE, 0x91, 0xC5, 0xE3, 0x0F, 0xFC, 0x15, 0xC3, 0x5F, 0xAF, 0x1F, 0xDB, 0x9A, 0xF7, 0xFD, 0x06,
+	0x27, 0xFF, 0x00, 0xBF, 0x94, 0x7F, 0x6E, 0x6B, 0xDF, 0xF4, 0x18, 0x9F, 0xFE, 0xFE, 0x51, 0xFF,
+	0x00, 0x11, 0x37, 0x17, 0xFF, 0x00, 0x40, 0xF1, 0xFE, 0xBE, 0x61, 0xFE, 0xAF, 0xCB, 0xFE, 0x7E,
+	0x2F, 0xC7, 0xFC, 0x8F, 0xC8, 0x7F, 0xF8, 0x7A, 0x7F, 0xFC, 0x1C, 0x91, 0xFF, 0x00, 0x48, 0xE2,
+	0xF1, 0x87, 0xFE, 0x0A, 0xE1, 0xA3, 0xFE, 0x1E, 0x9F, 0xFF, 0x00, 0x07, 0x24, 0x7F, 0xD2, 0x38,
+	0xBC, 0x61, 0xFF, 0x00, 0x82, 0xB8, 0x6B, 0xF5, 0xE3, 0xFB, 0x73, 0x5E, 0xFF, 0x00, 0xA0, 0xC4,
+	0xFF, 0x00, 0xF7, 0xF2, 0x8F, 0xED, 0xCD, 0x7B, 0xFE, 0x83, 0x13, 0xFF, 0x00, 0xDF, 0xCA, 0x3F,
+	0xE2, 0x26, 0xE2, 0xFF, 0x00, 0xE8, 0x1E, 0x3F, 0xD7, 0xCC, 0x3F, 0xD5, 0xF9, 0x7F, 0xCF, 0xC5,
+	0xF8, 0xFF, 0x00, 0x91, 0xF9, 0x0F, 0xFF, 0x00, 0x0F, 0x4F, 0xFF, 0x00, 0x83, 0x92, 0x3F, 0xE9,
+	0x1C, 0x5E, 0x30, 0xFF, 0x00, 0xC1, 0x5C, 0x34, 0xD6, 0xFF, 0x00, 0x82, 0xA7, 0x7F, 0xC1, 0xC8,
+	0xA7, 0xE4, 0xFF, 0x00, 0x87, 0x71, 0x78, 0xC5, 0x5B, 0xFE, 0xC1, 0x70, 0xD7, 0xEB, 0xD7, 0xF6,
+	0xE6, 0xBD, 0xFF, 0x00, 0x41, 0x89, 0xFF, 0x00, 0xEF, 0xE5, 0x1F, 0xDB, 0x9E, 0x20, 0xE7, 0xFE,
+	0x27, 0x53, 0x7C, 0xBC, 0xFF, 0x00, 0xAC, 0xFB, 0xD4, 0xFF, 0x00, 0xE2, 0x26, 0xE2, 0xFF, 0x00,
+	0xE8, 0x1E, 0x3F, 0xD7, 0xCC, 0x3F, 0xB0, 0x25, 0xD2, 0x6B, 0xFA, 0xF9, 0x1F, 0x91, 0x9A, 0x5F,
+	0xFC, 0x15, 0x4B, 0xFE, 0x0E, 0x39, 0xB5, 0xD5, 0x23, 0xB8, 0xD6, 0x3F, 0xE0, 0x9B, 0x9E, 0x34,
+	0x9A, 0xCD, 0x79, 0x92, 0x35, 0xD2, 0xE1, 0x56, 0x6F, 0xF8, 0x15, 0x7D, 0x11, 0xFB, 0x22, 0x7F,
+	0xC1, 0xC8, 0x7E, 0x09, 0xF1, 0xCF, 0xC7, 0x7D, 0x27, 0xF6, 0x4F, 0xFD, 0xB7, 0x7F, 0x67, 0xAD,
+	0x7B, 0xE0, 0xBF, 0x8B, 0xAE, 0x95, 0xA2, 0x6B, 0xEF, 0x16, 0x5D, 0x2A, 0xC1, 0x71, 0x32, 0xFD,
+	0xD5, 0x55, 0x55, 0xF9, 0x77, 0x37, 0xCB, 0x5F, 0x75, 0xFF, 0x00, 0x6E, 0xEB, 0xD2, 0x47, 0xF2,
+	0x6A, 0xF3, 0x6E, 0xEB, 0xF3, 0x35, 0x7C, 0x43, 0xFF, 0x00, 0x05, 0xCA, 0xFD, 0x91, 0x7E, 0x14,
+	0x7C, 0x7D, 0xFD, 0x86, 0xFC, 0x55, 0xE3, 0x51, 0xE0, 0x9D, 0x36, 0xD7, 0xC6, 0xDA, 0x5C, 0xF6,
+	0xF7, 0xBA, 0x6F, 0x8A, 0xA1, 0xB5, 0x55, 0xBE, 0x87, 0xCB, 0x6F, 0x31, 0xB6, 0xC9, 0xF7, 0xBE,
+	0x6D, 0xB5, 0xD9, 0x96, 0xF8, 0x89, 0x2C, 0x56, 0x32, 0x14, 0x71, 0x14, 0x14, 0x63, 0x27, 0x66,
+	0xD7, 0x4B, 0xE8, 0xBA, 0x99, 0x56, 0xC9, 0x65, 0x46, 0x9B, 0x9F, 0x35, 0xEC, 0x7E, 0x99, 0x5B,
+	0x4D, 0x6D, 0x76, 0xAB, 0x73, 0x09, 0x0C, 0xB2, 0x2A, 0xBC, 0x6E, 0xAD, 0xF2, 0xBA, 0xF6, 0x6A,
+	0x9E, 0x3D, 0xDD, 0x1D, 0x2B, 0xE2, 0xEF, 0xF8, 0x20, 0x0F, 0xED, 0x0D, 0xE3, 0x4F, 0xDA, 0x83,
+	0xFE, 0x09, 0x79, 0xE0, 0x3F, 0x8A, 0x7F, 0x10, 0xB5, 0x79, 0xAF, 0xB5, 0x26, 0x92, 0xEA, 0xCA,
+	0x4B, 0x8B, 0x89, 0x77, 0x3B, 0x2D, 0xBC, 0x9E, 0x5A, 0xF3, 0xFF, 0x00, 0x01, 0xAF, 0xB4, 0x23,
+	0xE5, 0xD9, 0xF2, 0xDF, 0xEE, 0xD7, 0xE9, 0x9D, 0x4F, 0x0C, 0x92, 0x91, 0xFE, 0xED, 0x2D, 0x53,
+	0xD7, 0x35, 0x21, 0xA5, 0x68, 0xF7, 0x9A, 0xA6, 0x3F, 0xE3, 0xD6, 0xD6, 0x49, 0x7F, 0xEF, 0x95,
+	0xDD, 0x54, 0x07, 0xCA, 0x3F, 0xF0, 0x53, 0xFF, 0x00, 0xF8, 0x2B, 0xC7, 0xEC, 0xF9, 0xFF, 0x00,
+	0x04, 0xBE, 0xF0, 0x6D, 0x86, 0xAD, 0xF1, 0x16, 0xCE, 0x4D, 0x7B, 0xC4, 0x1A, 0xC4, 0x8C, 0x9A,
+	0x57, 0x85, 0x74, 0xDB, 0x85, 0x5B, 0xAB, 0xA6, 0xF4, 0x1F, 0x7A, 0xBE, 0x01, 0xF1, 0xEF, 0xFC,
+	0x16, 0x83, 0xFE, 0x0B, 0x81, 0xF1, 0x92, 0xEA, 0x3F, 0x18, 0x7E, 0xCD, 0x3F, 0xF0, 0x4C, 0x1F,
+	0x1D, 0x69, 0xBE, 0x1F, 0xBA, 0x89, 0x67, 0xB3, 0x5B, 0xAB, 0x28, 0xE6, 0xF3, 0x21, 0x6E, 0x55,
+	0xB7, 0x57, 0x37, 0xFF, 0x00, 0x04, 0xF2, 0xD0, 0xBC, 0x1F, 0xFF, 0x00, 0x05, 0x48, 0xFF, 0x00,
+	0x82, 0xC0, 0xFC, 0x72, 0xFD, 0xA3, 0x3E, 0x3A, 0xDB, 0x47, 0xE2, 0x5D, 0x1F, 0xC0, 0x31, 0xDA,
+	0xB7, 0x85, 0x34, 0x2D, 0x51, 0x7C, 0xFB, 0x5B, 0x79, 0x95, 0xBC, 0xB6, 0x65, 0x8D, 0xBE, 0xEF,
+	0xDD, 0xAF, 0xD7, 0x5B, 0x3D, 0x47, 0x51, 0xD2, 0x6D, 0x63, 0xD2, 0xB4, 0x77, 0x16, 0x96, 0xB0,
+	0xA6, 0xD8, 0x20, 0xB7, 0xF9, 0x52, 0x35, 0xFE, 0x15, 0x55, 0xAF, 0x81, 0xCF, 0xF8, 0xDA, 0x19,
+	0x36, 0x3D, 0xE0, 0xA9, 0x52, 0x53, 0x94, 0x17, 0xBC, 0xDE, 0xDA, 0x9E, 0xB6, 0x0F, 0x2A, 0x96,
+	0x32, 0x9F, 0x3F, 0x35, 0x8F, 0xC8, 0xEF, 0xF8, 0x7A, 0x7F, 0xFC, 0x1C, 0x93, 0xFF, 0x00, 0x48,
+	0xE0, 0xF1, 0x87, 0xFE, 0x0A, 0xE1, 0xFF, 0x00, 0xE2, 0x68, 0xFF, 0x00, 0x87, 0xA7, 0x7F, 0xC1,
+	0xC9, 0x3F, 0xF4, 0x8E, 0x6F, 0x19, 0x7F, 0xE0, 0xA6, 0x1A, 0xFD, 0x79, 0xFF, 0x00, 0x84, 0x83,
+	0xC4, 0x3F, 0xF4, 0x19, 0x9F, 0xFE, 0xFA, 0xA3, 0xFB, 0x77, 0xC4, 0x1D, 0xB5, 0x7B, 0xAF, 0xFB,
+	0xEA, 0xBC, 0x27, 0xE2, 0x66, 0x2A, 0x3F, 0xF3, 0x0E, 0x9F, 0xDF, 0xFE, 0x67, 0x67, 0xFA, 0xBF,
+	0x3F, 0xE7, 0x5F, 0x89, 0xF9, 0x11, 0xFF, 0x00, 0x0F, 0x4C, 0xFF, 0x00, 0x83, 0x92, 0x7F, 0xE9,
+	0x1C, 0x3E, 0x31, 0xFF, 0x00, 0xC1, 0x5C, 0x54, 0x7F, 0xC3, 0xD3, 0xFF, 0x00, 0xE0, 0xE4, 0x8F,
+	0xFA, 0x47, 0x17, 0x8C, 0x3F, 0xF0, 0x57, 0x0D, 0x7E, 0xBC, 0x7F, 0x6D, 0xEB, 0xFF, 0x00, 0xF4,
+	0x18, 0x9B, 0xFE, 0xFE, 0x51, 0xFD, 0xB9, 0xAF, 0x7F, 0xD0, 0x62, 0x7F, 0xFB, 0xF9, 0x47, 0xFC,
+	0x44, 0xDC, 0x5F, 0xFD, 0x03, 0xC7, 0xFA, 0xF9, 0x8B, 0xFD, 0x5F, 0x97, 0xFC, 0xFC, 0x5F, 0x8F,
+	0xF9, 0x1F, 0x90, 0xFF, 0x00, 0xF0, 0xF4, 0xFF, 0x00, 0xF8, 0x39, 0x23, 0xFE, 0x91, 0xC5, 0xE3,
+	0x0F, 0xFC, 0x15, 0xC3, 0x47, 0xFC, 0x3D, 0x3F, 0xFE, 0x0E, 0x48, 0xFF, 0x00, 0xA4, 0x71, 0x78,
+	0xC3, 0xFF, 0x00, 0x05, 0x70, 0xD7, 0xEB, 0xC7, 0xF6, 0xE6, 0xBD, 0xFF, 0x00, 0x41, 0x89, 0xFF,
+	0x00, 0xEF, 0xE5, 0x1F, 0xDB, 0x9A, 0xF7, 0xFD, 0x06, 0x27, 0xFF, 0x00, 0xBF, 0x94, 0x7F, 0xC4,
+	0x4D, 0xC5, 0xFF, 0x00, 0xD0, 0x3C, 0x7F, 0xAF, 0x98, 0x7F, 0xAB, 0xF2, 0xFF, 0x00, 0x9F, 0x8B,
+	0xF1, 0xFF, 0x00, 0x23, 0xF2, 0x1F, 0xFE, 0x1E, 0x9F, 0xFF, 0x00, 0x07, 0x24, 0x7F, 0xD2, 0x38,
+	0xBC, 0x61, 0xFF, 0x00, 0x82, 0xB8, 0x68, 0xFF, 0x00, 0x87, 0xA7, 0xFF, 0x00, 0xC1, 0xC9, 0x1F,
+	0xF4, 0x8E, 0x2F, 0x18, 0x7F, 0xE0, 0xAE, 0x1A, 0xFD, 0x78, 0xFE, 0xDC, 0xD7, 0xBF, 0xE8, 0x31,
+	0x3F, 0xFD, 0xFC, 0xA3, 0xFB, 0x73, 0x5E, 0xFF, 0x00, 0xA0, 0xC4, 0xFF, 0x00, 0xF7, 0xF2, 0x8F,
+	0xF8, 0x89, 0xB8, 0xBF, 0xFA, 0x07, 0x8F, 0xF5, 0xF3, 0x0F, 0xF5, 0x7E, 0x5F, 0xF3, 0xF1, 0x7E,
+	0x3F, 0xE4, 0x7E, 0x43, 0xFF, 0x00, 0xC3, 0xD3, 0xFF, 0x00, 0xE0, 0xE4, 0x8F, 0xFA, 0x47, 0x17,
+	0x8C, 0x3F, 0xF0, 0x57, 0x0D, 0x1F, 0xF0, 0xF4, 0xFF, 0x00, 0xF8, 0x39, 0x23, 0xFE, 0x91, 0xC5,
+	0xE3, 0x0F, 0xFC, 0x15, 0xC3, 0x5F, 0xAF, 0x1F, 0xDB, 0x9A, 0xF7, 0xFD, 0x06, 0x27, 0xFF, 0x00,
+	0xBF, 0x94, 0x7F, 0x6E, 0x6B, 0xDF, 0xF4, 0x18, 0x9F, 0xFE, 0xFE, 0x51, 0xFF, 0x00, 0x11, 0x37,
+	0x17, 0xFF, 0x00, 0x40, 0xF1, 0xFE, 0xBE, 0x61, 0xFE, 0xAF, 0xCB, 0xFE, 0x7E, 0x2F, 0xC7, 0xFC,
+	0x8F, 0xC8, 0x7F, 0xF8, 0x7A, 0x7F, 0xFC, 0x1C, 0x91, 0xFF, 0x00, 0x48, 0xE2, 0xF1, 0x87, 0xFE,
+	0x0A, 0xE1, 0xA3, 0xFE, 0x1E, 0x9F, 0xFF, 0x00, 0x07, 0x24, 0x7F, 0xD2, 0x38, 0xBC, 0x61, 0xFF,
+	0x00, 0x82, 0xB8, 0x6B, 0xF5, 0xE3, 0xFB, 0x73, 0x5E, 0xFF, 0x00, 0xA0, 0xC4, 0xFF, 0x00, 0xF7,
+	0xF2, 0x8F, 0xED, 0xCD, 0x7B, 0xFE, 0x83, 0x13, 0xFF, 0x00, 0xDF, 0xCA, 0x3F, 0xE2, 0x26, 0xE2,
+	0xFF, 0x00, 0xE8, 0x1E, 0x3F, 0xD7, 0xCC, 0x3F, 0xD5, 0xF9, 0x7F, 0xCF, 0xC5, 0xF8, 0xFF, 0x00,
+	0x91, 0xF9, 0x0F, 0xFF, 0x00, 0x0F, 0x4F, 0xFF, 0x00, 0x83, 0x92, 0x3F, 0xE9, 0x1C, 0x5E, 0x30,
+	0xFF, 0x00, 0xC1, 0x5C, 0x34, 0x7F, 0xC3, 0xD3, 0xFF, 0x00, 0xE0, 0xE4, 0x8F, 0xFA, 0x47, 0x17,
+	0x8C, 0x3F, 0xF0, 0x57, 0x0D, 0x7E, 0xBC, 0x7F, 0x6E, 0x6B, 0xDF, 0xF4, 0x18, 0x9F, 0xFE, 0xFE,
+	0x51, 0xFD, 0xB9, 0xAF, 0x7F, 0xD0, 0x62, 0x7F, 0xFB, 0xF9, 0x47, 0xFC, 0x44, 0xDC, 0x5F, 0xFD,
+	0x03, 0xC7, 0xFA, 0xF9, 0x87, 0xFA, 0xBF, 0x2F, 0xF9, 0xF8, 0xBF, 0x1F, 0xF2, 0x3F, 0x21, 0xFF,
+	0x00, 0xE1, 0xEA, 0x1F, 0xF0, 0x72, 0x4F, 0xFD, 0x23, 0x83, 0xC6, 0x1F, 0xF8, 0x2B, 0x86, 0x8F,
+	0xF8, 0x7A, 0x87, 0xFC, 0x1C, 0x93, 0xFF, 0x00, 0x48, 0xE0, 0xF1, 0x87, 0xFE, 0x0A, 0xE1, 0xAF,
+	0xD7, 0x7F, 0xED, 0xCF, 0x10, 0x37, 0x3F, 0xDB, 0x53, 0x7F, 0xDF, 0xCA, 0x55, 0xD6, 0xBC, 0x40,
+	0x7F, 0xE6, 0x35, 0x37, 0xFD, 0xF5, 0x4B, 0xFE, 0x22, 0x76, 0x2B, 0xFE, 0x81, 0xD7, 0xF5, 0xF3,
+	0x17, 0xFA, 0xBF, 0x2F, 0xF9, 0xF8, 0xBF, 0x13, 0xF2, 0x1F, 0xFE, 0x1E, 0xA1, 0xFF, 0x00, 0x07,
+	0x24, 0xFF, 0x00, 0xD2, 0x38, 0x3C, 0x61, 0xFF, 0x00, 0x82, 0xB8, 0x69, 0xDA, 0x7F, 0xFC, 0x15,
+	0x3B, 0xFE, 0x0E, 0x3B, 0xB7, 0xD4, 0x52, 0x6B, 0xFF, 0x00, 0xF8, 0x27, 0x17, 0x8C, 0xE6, 0xB7,
+	0x56, 0xCB, 0x42, 0xBA, 0x5C, 0x3B, 0x99, 0x6B, 0xF5, 0xD9, 0xB5, 0xCF, 0x10, 0xAF, 0xFC, 0xC6,
+	0x67, 0xFF, 0x00, 0xBF, 0x94, 0x3E, 0xBB, 0xE2, 0x3D, 0xBF, 0x3E, 0xAF, 0x20, 0x0D, 0xFC, 0x4B,
+	0x27, 0xDD, 0xA7, 0x2F, 0x13, 0x31, 0x3B, 0xFD, 0x59, 0x3F, 0x9B, 0xFF, 0x00, 0x32, 0x7F, 0xD5,
+	0xF9, 0x7F, 0xCF, 0xCF, 0xCF, 0xFC, 0x8F, 0x80, 0xBF, 0x66, 0xAF, 0xF8, 0x39, 0x47, 0x48, 0xB5,
+	0xF8, 0xD1, 0xA3, 0xFE, 0xCC, 0x5F, 0xF0, 0x50, 0x7F, 0xD9, 0x97, 0xC4, 0x5F, 0x06, 0x3C, 0x49,
+	0x78, 0xCB, 0x0C, 0xBA, 0xDF, 0x8A, 0xAE, 0x16, 0x3B, 0x66, 0x66, 0xFB, 0xBC, 0x2A, 0xD7, 0xEA,
+	0x4E, 0x95, 0xA9, 0x69, 0xBA, 0xCE, 0x93, 0x6B, 0xAD, 0xE9, 0x57, 0xD1, 0xDC, 0x59, 0xDE, 0x42,
+	0xB3, 0xD9, 0xDC, 0x46, 0xDB, 0x96, 0x68, 0xD9, 0x77, 0x2B, 0x2F, 0xFB, 0xCA, 0x6B, 0xE0, 0x7F,
+	0xF8, 0x2A, 0xFF, 0x00, 0xEC, 0x0F, 0xF0, 0x77, 0xF6, 0xDD, 0xFD, 0x95, 0xFC, 0x61, 0xA7, 0xEB,
+	0x5E, 0x13, 0xB1, 0x5F, 0x1A, 0xC3, 0xA6, 0xEF, 0xD0, 0x7C, 0x49, 0x25, 0xBA, 0xF9, 0xF0, 0xCC,
+	0xAD, 0xBB, 0xFD, 0x67, 0xF0, 0xFD, 0xDA, 0x6F, 0xFC, 0x1B, 0x67, 0xFB, 0x4B, 0x7C, 0x51, 0xFD,
+	0xA2, 0xBF, 0xE0, 0x9D, 0xE2, 0x0F, 0x8C, 0x1A, 0x82, 0xDD, 0x6A, 0xFE, 0x09, 0xF1, 0x65, 0xE7,
+	0x86, 0x62, 0xB8, 0xDC, 0xCD, 0xBE, 0x1B, 0x5D, 0xB1, 0xA7, 0x3F, 0xF0, 0x16, 0xAF, 0xB7, 0xE1,
+	0xAE, 0x20, 0xA3, 0xC4, 0x58, 0x59, 0x54, 0x8C, 0x79, 0x65, 0x07, 0x69, 0x2B, 0xDE, 0xDD, 0x8F,
+	0x3B, 0x1D, 0x83, 0xFA, 0x9D, 0x65, 0x0B, 0xDC, 0xFD, 0x08, 0xCF, 0x1F, 0x2F, 0xCD, 0xFC, 0x2C,
+	0xB4, 0x6D, 0x75, 0x0D, 0xF3, 0xE7, 0xFB, 0xB5, 0x18, 0x93, 0x63, 0x2A, 0x0F, 0xE2, 0xF9, 0x99,
+	0xAA, 0x4D, 0xFB, 0x7F, 0xE0, 0x55, 0xF4, 0x5D, 0x6E, 0x70, 0x91, 0x49, 0xF2, 0xC8, 0xBF, 0x3E,
+	0xEF, 0xEF, 0x35, 0x7C, 0xC5, 0xFF, 0x00, 0x05, 0x2A, 0xFF, 0x00, 0x82, 0xAB, 0x7E, 0xCF, 0x7F,
+	0xF0, 0x4C, 0x8F, 0x86, 0x6B, 0xE3, 0x4F, 0x8B, 0x9A, 0x80, 0xD4, 0xB5, 0x5B, 0xA9, 0x3C, 0xBD,
+	0x37, 0xC3, 0x76, 0x77, 0x0A, 0xB7, 0x77, 0x4D, 0xB7, 0x72, 0xAA, 0xFF, 0x00, 0xBD, 0x5F, 0x50,
+	0x18, 0xC3, 0x36, 0xF7, 0xEB, 0x5F, 0x82, 0xBF, 0xB2, 0x8D, 0x9F, 0x87, 0xFF, 0x00, 0xE0, 0xB7,
+	0x5F, 0xF0, 0x5A, 0xDF, 0x88, 0xDF, 0x19, 0xFF, 0x00, 0x68, 0x7D, 0x23, 0xCE, 0xF0, 0x6F, 0xC2,
+	0x5B, 0x16, 0xD3, 0xFC, 0x3B, 0xE1, 0xD6, 0xF9, 0xAD, 0x26, 0xBE, 0xB4, 0xB9, 0xF2, 0xF7, 0x49,
+	0x1B, 0x7F, 0xB3, 0x5C, 0x99, 0x86, 0x32, 0x96, 0x5B, 0x82, 0x9E, 0x26, 0x7A, 0xA8, 0xAB, 0xDB,
+	0x6B, 0xF9, 0x1A, 0x53, 0x87, 0xB4, 0xA8, 0xA3, 0xDC, 0xEF, 0xBC, 0x75, 0xFF, 0x00, 0x05, 0xBF,
+	0xFF, 0x00, 0x82, 0xC8, 0x7C, 0x7F, 0xD3, 0x6D, 0x7C, 0x7B, 0xFB, 0x23, 0x7F, 0xC1, 0x2E, 0x7C,
+	0x7F, 0x65, 0xE1, 0xFB, 0xF8, 0x96, 0x5D, 0x3E, 0xEA, 0xE2, 0xDE, 0x39, 0x56, 0x68, 0xDB, 0xEE,
+	0xB5, 0x73, 0x31, 0x7F, 0xC1, 0x52, 0xFF, 0x00, 0xE0, 0xE4, 0x85, 0x5F, 0x2D, 0xFF, 0x00, 0xE0,
+	0x9C, 0x7E, 0x32, 0x76, 0xFE, 0x2F, 0xF8, 0x95, 0xC3, 0x5F, 0xAE, 0x1A, 0x44, 0x89, 0xE1, 0xCB,
+	0x18, 0x74, 0x1F, 0x0D, 0x85, 0xD3, 0x6C, 0xED, 0xE2, 0xDB, 0x6B, 0x63, 0x64, 0x3C, 0xB8, 0x61,
+	0x8D, 0x7F, 0x85, 0x57, 0xF8, 0x6A, 0xD2, 0xEB, 0x9E, 0x20, 0x75, 0xF3, 0x17, 0x58, 0x9B, 0xE6,
+	0xFE, 0x1D, 0xD5, 0xF9, 0x94, 0xBC, 0x4A, 0xC4, 0x29, 0x7B, 0xB8, 0x75, 0x6F, 0x36, 0xDF, 0xEA,
+	0x7B, 0xBF, 0xD8, 0x52, 0x7B, 0x4F, 0xFA, 0xFB, 0x8F, 0xC8, 0x8F, 0xF8, 0x7A, 0x8F, 0xFC, 0x1C,
+	0x8B, 0xFF, 0x00, 0x48, 0xDF, 0xF1, 0x8F, 0xFE, 0x0A, 0xE1, 0xA4, 0xFF, 0x00, 0x87, 0xA7, 0xFF,
+	0x00, 0xC1, 0xC9, 0x1F, 0xF4, 0x8E, 0x0F, 0x18, 0x7F, 0xE0, 0xAE, 0x1A, 0xFD, 0x78, 0xFE, 0xDB,
+	0xD7, 0xFF, 0x00, 0xE8, 0x31, 0x37, 0xFD, 0xFC, 0xA4, 0xFE, 0xDB, 0xF1, 0x07, 0xFD, 0x06, 0x66,
+	0xFF, 0x00, 0xBF, 0x95, 0x3F, 0xF1, 0x13, 0x31, 0x5F, 0xF4, 0x0E, 0xBF, 0xAF, 0x98, 0x7F, 0xAB,
+	0xF2, 0xFF, 0x00, 0x9F, 0x8B, 0xF1, 0x3F, 0x22, 0x3F, 0xE1, 0xE9, 0xFF, 0x00, 0xF0, 0x72, 0x47,
+	0xFD, 0x23, 0x8B, 0xC6, 0x1F, 0xF8, 0x2B, 0x86, 0x8F, 0xF8, 0x7A, 0x7F, 0xFC, 0x1C, 0x91, 0xFF,
+	0x00, 0x48, 0xE2, 0xF1, 0x87, 0xFE, 0x0A, 0xE1, 0xAF, 0xD7, 0x8F, 0xED, 0xCD, 0x7B, 0xFE, 0x83,
+	0x13, 0xFF, 0x00, 0xDF, 0xCA, 0x3F, 0xB7, 0x35, 0xEF, 0xFA, 0x0C, 0x4F, 0xFF, 0x00, 0x7F, 0x29,
+	0xFF, 0x00, 0xC4, 0x4D, 0xC5, 0xFF, 0x00, 0xD0, 0x3C, 0x7F, 0xAF, 0x98, 0xFF, 0x00, 0xD5, 0xF9,
+	0x7F, 0xCF, 0xC5, 0xF8, 0xFF, 0x00, 0x91, 0xF9, 0x0F, 0xFF, 0x00, 0x0F, 0x4F, 0xFF, 0x00, 0x83,
+	0x92, 0x3F, 0xE9, 0x1C, 0x5E, 0x30, 0xFF, 0x00, 0xC1, 0x5C, 0x34, 0x7F, 0xC3, 0xD3, 0xFF, 0x00,
+	0xE0, 0xE4, 0x8F, 0xFA, 0x47, 0x17, 0x8C, 0x3F, 0xF0, 0x57, 0x0D, 0x7E, 0xBC, 0x7F, 0x6E, 0x6B,
+	0xDF, 0xF4, 0x18, 0x9F, 0xFE, 0xFE, 0x51, 0xFD, 0xB9, 0xAF, 0x7F, 0xD0, 0x62, 0x7F, 0xFB, 0xF9,
+	0x47, 0xFC, 0x44, 0xDC, 0x5F, 0xFD, 0x03, 0xC7, 0xFA, 0xF9, 0x87, 0xFA, 0xBF, 0x2F, 0xF9, 0xF8,
+	0xBF, 0x1F, 0xF2, 0x3F, 0x21, 0xFF, 0x00, 0xE1, 0xE9, 0xFF, 0x00, 0xF0, 0x72, 0x47, 0xFD, 0x23,
+	0x8B, 0xC6, 0x1F, 0xF8, 0x2B, 0x86, 0x8F, 0xF8, 0x7A, 0x7F, 0xFC, 0x1C, 0x91, 0xFF, 0x00, 0x48,
+	0xE2, 0xF1, 0x87, 0xFE, 0x0A, 0xE1, 0xAF, 0xD7, 0x8F, 0xED, 0xCD, 0x7B, 0xFE, 0x83, 0x13, 0xFF,
+	0x00, 0xDF, 0xCA, 0x3F, 0xB7, 0x35, 0xEF, 0xFA, 0x0C, 0x4F, 0xFF, 0x00, 0x7F, 0x28, 0xFF, 0x00,
+	0x88, 0x9B, 0x8B, 0xFF, 0x00, 0xA0, 0x78, 0xFF, 0x00, 0x5F, 0x30, 0xFF, 0x00, 0x57, 0xE5, 0xFF,
+	0x00, 0x3F, 0x17, 0xE3, 0xFE, 0x47, 0xE4, 0x3F, 0xFC, 0x3D, 0x3F, 0xFE, 0x0E, 0x48, 0xFF, 0x00,
+	0xA4, 0x71, 0x78, 0xC3, 0xFF, 0x00, 0x05, 0x70, 0xD1, 0xFF, 0x00, 0x0F, 0x4F, 0xFF, 0x00, 0x83,
+	0x92, 0x3F, 0xE9, 0x1C, 0x5E, 0x30, 0xFF, 0x00, 0xC1, 0x5C, 0x35, 0xFA, 0xF1, 0xFD, 0xB9, 0xAF,
+	0x7F, 0xD0, 0x62, 0x7F, 0xFB, 0xF9, 0x47, 0xF6, 0xE6, 0xBD, 0xFF, 0x00, 0x41, 0x89, 0xFF, 0x00,
+	0xEF, 0xE5, 0x1F, 0xF1, 0x13, 0x71, 0x7F, 0xF4, 0x0F, 0x1F, 0xEB, 0xE6, 0x1F, 0xEA, 0xFC, 0xBF,
+	0xE7, 0xE2, 0xFC, 0x7F, 0xC8, 0xFC, 0x87, 0xFF, 0x00, 0x87, 0xA7, 0xFF, 0x00, 0xC1, 0xC9, 0x1F,
+	0xF4, 0x8E, 0x2F, 0x18, 0x7F, 0xE0, 0xAE, 0x1A, 0x3F, 0xE1, 0xE9, 0xFF, 0x00, 0xF0, 0x72, 0x47,
+	0xFD, 0x23, 0x8B, 0xC6, 0x1F, 0xF8, 0x2B, 0x86, 0xBF, 0x5E, 0x3F, 0xB7, 0x35, 0xEF, 0xFA, 0x0C,
+	0x4F, 0xFF, 0x00, 0x7F, 0x28, 0xFE, 0xDC, 0xD7, 0xBF, 0xE8, 0x31, 0x3F, 0xFD, 0xFC, 0xA3, 0xFE,
+	0x22, 0x6E, 0x2F, 0xFE, 0x81, 0xE3, 0xFD, 0x7C, 0xC3, 0xFD, 0x5F, 0x97, 0xFC, 0xFC, 0x5F, 0x8F,
+	0xF9, 0x1F, 0x90, 0xFF, 0x00, 0xF0, 0xF4, 0xFF, 0x00, 0xF8, 0x39, 0x23, 0xFE, 0x91, 0xC5, 0xE3,
+	0x0F, 0xFC, 0x15, 0xC3, 0x47, 0xFC, 0x3D, 0x3F, 0xFE, 0x0E, 0x48, 0xFF, 0x00, 0xA4, 0x71, 0x78,
+	0xC3, 0xFF, 0x00, 0x05, 0x70, 0xD7, 0xEB, 0xC7, 0xF6, 0xE6, 0xBD, 0xFF, 0x00, 0x41, 0x89, 0xFF,
+	0x00, 0xEF, 0xE5, 0x1F, 0xDB, 0x9A, 0xF7, 0xFD, 0x06, 0x27, 0xFF, 0x00, 0xBF, 0x94, 0x7F, 0xC4,
+	0x4D, 0xC5, 0xFF, 0x00, 0xD0, 0x3C, 0x7F, 0xAF, 0x98, 0x7F, 0xAB, 0xF2, 0xFF, 0x00, 0x9F, 0x8B,
+	0xF1, 0xFF, 0x00, 0x23, 0xF2, 0x1C, 0xFF, 0x00, 0xC1, 0x53, 0x7F, 0xE0, 0xE4, 0x73, 0xF7, 0xBF,
+	0xE0, 0x9C, 0x7E, 0x30, 0xFF, 0x00, 0xC1, 0x5C, 0x34, 0xDF, 0xF8, 0x7A, 0x6F, 0xFC, 0x1C, 0x97,
+	0xFF, 0x00, 0x48, 0xE6, 0xF1, 0x87, 0xFE, 0x0A, 0x61, 0xAF, 0xD7, 0xA3, 0xAD, 0xEB, 0x9F, 0xC7,
+	0xAD, 0x5C, 0x7F, 0xC0, 0x64, 0xA6, 0xFF, 0x00, 0xC2, 0x41, 0xAE, 0xAF, 0xFC, 0xC5, 0xEE, 0x3F,
+	0xEF, 0xAA, 0x5F, 0xF1, 0x13, 0xB1, 0x9F, 0xF4, 0x0E, 0xBF, 0xAF, 0x98, 0xD7, 0x0F, 0xCD, 0xFD,
+	0xB5, 0xF8, 0x9F, 0x91, 0x56, 0xDF, 0xF0, 0x54, 0xCF, 0xF8, 0x39, 0x23, 0xCC, 0x12, 0x4D, 0xFF,
+	0x00, 0x04, 0xE0, 0xF1, 0x8B, 0xAA, 0xFD, 0xE5, 0x5D, 0x2E, 0x1A, 0xF6, 0x5F, 0x81, 0x1F, 0xF0,
+	0x72, 0xC6, 0xB1, 0xE0, 0x0F, 0x8A, 0xBE, 0x1F, 0xFD, 0x9C, 0xFF, 0x00, 0xE0, 0xA3, 0x9F, 0xB2,
+	0x1F, 0x8A, 0xBE, 0x13, 0x6B, 0xBA, 0xA4, 0xF1, 0xC5, 0x27, 0x88, 0xBC, 0x41, 0x3A, 0xC7, 0x68,
+	0xAA, 0xDF, 0xC4, 0xCB, 0xB6, 0xBF, 0x44, 0x57, 0xC4, 0x5E, 0x24, 0x2C, 0xAA, 0xBA, 0xC4, 0xAA,
+	0xAD, 0xF7, 0xB7, 0x35, 0x7C, 0xE5, 0xFF, 0x00, 0x05, 0x29, 0xFD, 0x8E, 0x7E, 0x13, 0x7E, 0xD8,
+	0xBF, 0xB2, 0x67, 0x8F, 0xF4, 0xDF, 0x19, 0xF8, 0x1B, 0x4D, 0xBC, 0xF1, 0x45, 0xBF, 0x87, 0x2E,
+	0x0E, 0x83, 0xAF, 0x5D, 0x5A, 0xAB, 0x5C, 0xDB, 0x4C, 0xAB, 0xFB, 0xB6, 0x59, 0x3F, 0x86, 0xBA,
+	0xF0, 0xBE, 0x23, 0x4A, 0xA6, 0x2A, 0x10, 0xAD, 0x87, 0xF7, 0x5D, 0x93, 0x6B, 0xA3, 0x7B, 0x6E,
+	0xCC, 0xEA, 0xE4, 0x75, 0x29, 0x53, 0x73, 0x73, 0xFB, 0xBF, 0xE1, 0x8F, 0xB6, 0x3C, 0x2B, 0xE2,
+	0x9F, 0x0F, 0x78, 0xDB, 0xC3, 0xB6, 0x5E, 0x2C, 0xF0, 0x96, 0xB1, 0x0E, 0xA1, 0xA5, 0xEA, 0x36,
+	0xAB, 0x3D, 0x8D, 0xF5, 0xAB, 0x6E, 0x8E, 0x68, 0xDB, 0xEE, 0xB2, 0xB5, 0x69, 0xAB, 0x6E, 0xED,
+	0x5F, 0x99, 0x5F, 0xF0, 0x6B, 0xA7, 0xED, 0x13, 0xF1, 0x5B, 0xE3, 0x2F, 0xEC, 0x4B, 0xE2, 0x4F,
+	0x85, 0xBF, 0x15, 0xEF, 0xBE, 0xD1, 0x75, 0xF0, 0xA7, 0xC5, 0xCD, 0xE1, 0x7B, 0x59, 0xB7, 0x16,
+	0xDD, 0x1C, 0x31, 0xD7, 0xE9, 0xAA, 0xAE, 0xDA, 0xFD, 0x3E, 0x3C, 0xBD, 0x3F, 0xAB, 0x9E, 0x13,
+	0xD1, 0xD8, 0x47, 0xFB, 0xBD, 0x71, 0x4D, 0x0A, 0x98, 0x6F, 0xE2, 0xA7, 0xBF, 0xDD, 0xA8, 0x88,
+	0x0E, 0x72, 0xBF, 0x2D, 0x29, 0x2D, 0x7F, 0x31, 0x1E, 0x4B, 0xFB, 0x67, 0xFE, 0xD9, 0xDF, 0x02,
+	0xBF, 0x61, 0x0F, 0x81, 0x9A, 0x97, 0xC7, 0x8F, 0x8F, 0xBE, 0x2C, 0xB7, 0xD2, 0x74, 0xAB, 0x3F,
+	0xDD, 0xDA, 0xC7, 0x71, 0x2E, 0xD6, 0xBA, 0xB8, 0xDB, 0xF2, 0x43, 0x1F, 0xFB, 0x4D, 0x5F, 0x96,
+	0xFE, 0x33, 0xFF, 0x00, 0x83, 0x81, 0xBF, 0xE0, 0xA4, 0x5F, 0xB5, 0x87, 0x86, 0x2D, 0xFC, 0x4B,
+	0xFF, 0x00, 0x04, 0xF8, 0xFF, 0x00, 0x82, 0x64, 0x7C, 0x40, 0x9B, 0x49, 0xF9, 0xB6, 0x6B, 0x93,
+	0x2C, 0x73, 0xC5, 0x74, 0xBB, 0xBE, 0x56, 0x5F, 0x96, 0xB0, 0xFF, 0x00, 0xE0, 0xA0, 0xDA, 0x06,
+	0x9B, 0xFF, 0x00, 0x05, 0x70, 0xFF, 0x00, 0x82, 0xE6, 0x78, 0x3F, 0xF6, 0x26, 0xF1, 0x47, 0x8B,
+	0x35, 0x2B, 0x7F, 0x87, 0xFE, 0x01, 0xF0, 0xDC, 0xDA, 0xB6, 0xAD, 0xA2, 0xDB, 0xCD, 0xFB, 0x8B,
+	0xCB, 0xEB, 0x59, 0xB7, 0x6D, 0x91, 0x3E, 0xEB, 0x2B, 0x7D, 0xDA, 0xFD, 0x4E, 0xF0, 0x87, 0x87,
+	0xBC, 0x2F, 0xF0, 0xD7, 0x43, 0xB7, 0xF0, 0xD7, 0xC2, 0xCD, 0x06, 0xD7, 0x41, 0xD3, 0x63, 0x55,
+	0x58, 0xF4, 0xFD, 0x36, 0x15, 0x8A, 0x28, 0xF6, 0xAE, 0xDF, 0x95, 0x56, 0xBE, 0x3B, 0x89, 0x38,
+	0xBA, 0x1C, 0x3F, 0x5E, 0x14, 0x29, 0x41, 0x54, 0x9C, 0x95, 0xDD, 0xF6, 0x4B, 0xFC, 0xCF, 0x4B,
+	0x03, 0x97, 0xCB, 0x18, 0x9C, 0xAF, 0x6F, 0x91, 0xF9, 0x3A, 0xBF, 0xF0, 0x54, 0xCF, 0xF8, 0x39,
+	0x23, 0x6F, 0x96, 0x3F, 0xE0, 0x9C, 0xDE, 0x31, 0xDD, 0xFF, 0x00, 0x60, 0x88, 0x78, 0xA7, 0x1F,
+	0xF8, 0x2A, 0x77, 0xFC, 0x1C, 0x92, 0xBF, 0xF3, 0x8E, 0x0F, 0x18, 0xFF, 0x00, 0xE0, 0xAE, 0x1A,
+	0xFD, 0x78, 0x6D, 0x7B, 0x5E, 0x91, 0x8A, 0x7F, 0x6D, 0x5C, 0x2A, 0x2F, 0xDE, 0x6F, 0x33, 0xE6,
+	0xA6, 0xFF, 0x00, 0x6F, 0x6B, 0xDF, 0xC3, 0xAD, 0xDC, 0x37, 0xFD, 0xB5, 0xAF, 0x9B, 0x7E, 0x26,
+	0x62, 0x7A, 0x61, 0xE3, 0xFD, 0x7C, 0xCE, 0xEF, 0xEC, 0x19, 0x3F, 0xB7, 0xF8, 0x33, 0xF2, 0x27,
+	0xFE, 0x1E, 0xA1, 0xFF, 0x00, 0x07, 0x24, 0xFF, 0x00, 0xD2, 0x38, 0x3C, 0x61, 0xFF, 0x00, 0x82,
+	0xB8, 0x68, 0xFF, 0x00, 0x87, 0xA8, 0x7F, 0xC1, 0xC9, 0x3F, 0xF4, 0x8E, 0x0F, 0x18, 0x7F, 0xE0,
+	0xAE, 0x1A, 0xFD, 0x78, 0xFE, 0xDB, 0xF1, 0x03, 0x1F, 0xF9, 0x0C, 0x5C, 0x7F, 0xDF, 0xCA, 0x3F,
+	0xB7, 0x35, 0xCF, 0xFA, 0x0D, 0xCD, 0xFF, 0x00, 0x7F, 0x2B, 0x3F, 0xF8, 0x89, 0xB8, 0xAF, 0xFA,
+	0x07, 0x5F, 0xD7, 0xCC, 0x3F, 0xB0, 0x25, 0xFF, 0x00, 0x3F, 0x17, 0xE2, 0x7E, 0x43, 0xFF, 0x00,
+	0xC3, 0xD3, 0xFF, 0x00, 0xE0, 0xE4, 0x8F, 0xFA, 0x47, 0x17, 0x8C, 0x3F, 0xF0, 0x57, 0x0D, 0x1F,
+	0xF0, 0xF4, 0xFF, 0x00, 0xF8, 0x39, 0x23, 0xFE, 0x91, 0xC5, 0xE3, 0x0F, 0xFC, 0x15, 0xC3, 0x5F,
+	0xAF, 0x1F, 0xDB, 0x9A, 0xF7, 0xFD, 0x06, 0x27, 0xFF, 0x00, 0xBF, 0x94, 0x7F, 0x6E, 0x6B, 0xDF,
+	0xF4, 0x18, 0x9F, 0xFE, 0xFE, 0x53, 0xFF, 0x00, 0x88, 0x9B, 0x8B, 0xFF, 0x00, 0xA0, 0x78, 0xFF,
+	0x00, 0x5F, 0x31, 0xFF, 0x00, 0xAB, 0xF2, 0xFF, 0x00, 0x9F, 0x8B, 0xF1, 0xFF, 0x00, 0x23, 0xF2,
+	0x1F, 0xFE, 0x1E, 0x9F, 0xFF, 0x00, 0x07, 0x24, 0x7F, 0xD2, 0x38, 0xBC, 0x61, 0xFF, 0x00, 0x82,
+	0xB8, 0x68, 0xFF, 0x00, 0x87, 0xA7, 0xFF, 0x00, 0xC1, 0xC9, 0x1F, 0xF4, 0x8E, 0x2F, 0x18, 0x7F,
+	0xE0, 0xAE, 0x1A, 0xFD, 0x78, 0xFE, 0xDC, 0xD7, 0xBF, 0xE8, 0x31, 0x3F, 0xFD, 0xFC, 0xA3, 0xFB,
+	0x73, 0x5E, 0xFF, 0x00, 0xA0, 0xC4, 0xFF, 0x00, 0xF7, 0xF2, 0x8F, 0xF8, 0x89, 0xB8, 0xBF, 0xFA,
+	0x07, 0x8F, 0xF5, 0xF3, 0x0F, 0xF5, 0x7E, 0x5F, 0xF3, 0xF1, 0x7E, 0x3F, 0xE4, 0x7E, 0x43, 0xFF,
+	0x00, 0xC3, 0xD3, 0xFF, 0x00, 0xE0, 0xE4, 0x8F, 0xFA, 0x47, 0x17, 0x8C, 0x3F, 0xF0, 0x57, 0x0D,
+	0x1F, 0xF0, 0xF4, 0xFF, 0x00, 0xF8, 0x39, 0x23, 0xFE, 0x91, 0xC5, 0xE3, 0x0F, 0xFC, 0x15, 0xC3,
+	0x5F, 0xAF, 0x1F, 0xDB, 0x9A, 0xF7, 0xFD, 0x06, 0x27, 0xFF, 0x00, 0xBF, 0x94, 0x7F, 0x6E, 0x6B,
+	0xDF, 0xF4, 0x18, 0x9F, 0xFE, 0xFE, 0x51, 0xFF, 0x00, 0x11, 0x37, 0x17, 0xFF, 0x00, 0x40, 0xF1,
+	0xFE, 0xBE, 0x61, 0xFE, 0xAF, 0xCB, 0xFE, 0x7E, 0x2F, 0xC7, 0xFC, 0x8F, 0xC8, 0x7F, 0xF8, 0x7A,
+	0x7F, 0xFC, 0x1C, 0x91, 0xFF, 0x00, 0x48, 0xE2, 0xF1, 0x87, 0xFE, 0x0A, 0xE1, 0xA3, 0xFE, 0x1E,
+	0x9F, 0xFF, 0x00, 0x07, 0x24, 0x7F, 0xD2, 0x38, 0xBC, 0x61, 0xFF, 0x00, 0x82, 0xB8, 0x6B, 0xF5,
+	0xE3, 0xFB, 0x73, 0x5E, 0xFF, 0x00, 0xA0, 0xC4, 0xFF, 0x00, 0xF7, 0xF2, 0x8F, 0xED, 0xCD, 0x7B,
+	0xFE, 0x83, 0x13, 0xFF, 0x00, 0xDF, 0xCA, 0x3F, 0xE2, 0x26, 0xE2, 0xFF, 0x00, 0xE8, 0x1E, 0x3F,
+	0xD7, 0xCC, 0x3F, 0xD5, 0xF9, 0x7F, 0xCF, 0xC5, 0xF8, 0xFF, 0x00, 0x91, 0xF9, 0x0F, 0xFF, 0x00,
+	0x0F, 0x4F, 0xFF, 0x00, 0x83, 0x92, 0x3F, 0xE9, 0x1C, 0x5E, 0x30, 0xFF, 0x00, 0xC1, 0x5C, 0x34,
+	0x7F, 0xC3, 0xD3, 0xFF, 0x00, 0xE0, 0xE4, 0x8F, 0xFA, 0x47, 0x17, 0x8C, 0x3F, 0xF0, 0x57, 0x0D,
+	0x7E, 0xBC, 0x7F, 0x6E, 0x6B, 0xDF, 0xF4, 0x18, 0x9F, 0xFE, 0xFE, 0x51, 0xFD, 0xB9, 0xAF, 0x7F,
+	0xD0, 0x62, 0x7F, 0xFB, 0xF9, 0x47, 0xFC, 0x44, 0xDC, 0x5F, 0xFD, 0x03, 0xC7, 0xFA, 0xF9, 0x87,
+	0xFA, 0xBF, 0x2F, 0xF9, 0xF8, 0xBF, 0x1F, 0xF2, 0x3F, 0x21, 0xFF, 0x00, 0xE1, 0xE9, 0xFF, 0x00,
+	0xF0, 0x72, 0x47, 0xFD, 0x23, 0x8B, 0xC6, 0x1F, 0xF8, 0x2B, 0x86, 0x8F, 0xF8, 0x7A, 0x7F, 0xFC,
+	0x1C, 0x91, 0xFF, 0x00, 0x48, 0xE2, 0xF1, 0x87, 0xFE, 0x0A, 0xE1, 0xAF, 0xD7, 0x8F, 0xED, 0xCD,
+	0x7B, 0xFE, 0x83, 0x13, 0xFF, 0x00, 0xDF, 0xCA, 0x3F, 0xB7, 0x3C, 0x41, 0xFF, 0x00, 0x41, 0xB9,
+	0xBF, 0xEF, 0xE5, 0x1F, 0xF1, 0x13, 0x71, 0x7F, 0xF4, 0x0F, 0x1F, 0xEB, 0xE6, 0x1F, 0xEA, 0xFC,
+	0xBF, 0xE7, 0xE2, 0xFC, 0x7F, 0xC8, 0xFC, 0x86, 0xFF, 0x00, 0x87, 0xA7, 0xFF, 0x00, 0xC1, 0xC9,
+	0x1F, 0xF4, 0x8E, 0x4F, 0x18, 0xFF, 0x00, 0xE0, 0xA6, 0x1A, 0x0F, 0xFC, 0x15, 0x2B, 0xFE, 0x0E,
+	0x4B, 0x75, 0xC2, 0x7F, 0xC1, 0x39, 0x3C, 0x63, 0x9F, 0xFB, 0x05, 0xC3, 0x5F, 0xAF, 0x3F, 0xDB,
+	0x9A, 0xEF, 0xFD, 0x06, 0xE6, 0xFF, 0x00, 0xBF, 0x94, 0xC6, 0xD7, 0x7C, 0x45, 0xFF, 0x00, 0x2C,
+	0xF5, 0x7B, 0x8F, 0xFB, 0xF9, 0x4E, 0x3E, 0x26, 0x62, 0xA4, 0xD2, 0xFA, 0xBA, 0xFE, 0xBE, 0x63,
+	0x59, 0x04, 0xBF, 0x9D, 0x7E, 0x27, 0xE6, 0x67, 0x80, 0x7F, 0xE0, 0xE3, 0xBF, 0xDA, 0x6F, 0xF6,
+	0x61, 0x8F, 0x49, 0xF0, 0xDF, 0xFC, 0x14, 0xC7, 0xFE, 0x09, 0xFF, 0x00, 0xE3, 0x6F, 0x06, 0xAE,
+	0xA5, 0xA9, 0x47, 0x13, 0x78, 0xC2, 0xF5, 0xA3, 0x8A, 0xD6, 0xDE, 0x36, 0xF9, 0x77, 0x32, 0xED,
+	0xFE, 0x1F, 0xBD, 0x5F, 0xAC, 0xDF, 0x06, 0xBE, 0x31, 0x7C, 0x32, 0xFD, 0xA1, 0x7E, 0x19, 0xE9,
+	0x3F, 0x18, 0x7E, 0x0F, 0xF8, 0xAE, 0xD7, 0x5D, 0xF0, 0xDE, 0xB9, 0x6A, 0xB7, 0x3A, 0x5E, 0xAD,
+	0x62, 0xDB, 0xA2, 0xB8, 0x8F, 0xFB, 0xCB, 0x5E, 0x2B, 0xF1, 0xF3, 0xE0, 0x7F, 0x80, 0x7F, 0x69,
+	0xDF, 0x86, 0x7A, 0xD7, 0xC3, 0x1F, 0x8B, 0x5E, 0x07, 0xD2, 0xFC, 0x43, 0x0E, 0xAD, 0xA4, 0xDC,
+	0x59, 0x5B, 0xFF, 0x00, 0x6C, 0xDA, 0xAC, 0xBE, 0x4C, 0x92, 0x2B, 0x2A, 0xC8, 0xBB, 0xBE, 0xEB,
+	0x2E, 0xEA, 0xF8, 0x93, 0xFE, 0x0D, 0x9E, 0xB6, 0xF1, 0xEF, 0xC0, 0x5F, 0x8A, 0x1F, 0xB4, 0x57,
+	0xEC, 0x1B, 0xE2, 0xCF, 0x17, 0x5E, 0xEA, 0x1A, 0x5F, 0xC2, 0xDF, 0x17, 0x5B, 0xD9, 0x78, 0x6E,
+	0xDE, 0xEA, 0x76, 0x75, 0xB6, 0x85, 0x95, 0x99, 0x95, 0x7F, 0xBB, 0xF7, 0xAB, 0xEA, 0xB8, 0x5F,
+	0x8A, 0x69, 0xF1, 0x22, 0xAB, 0x09, 0x43, 0xD9, 0xCE, 0x1A, 0xD9, 0x75, 0x5B, 0x5C, 0xF3, 0x71,
+	0xD9, 0x7C, 0xF0, 0x32, 0x4E, 0xF7, 0x4C, 0xFD, 0x71, 0x8C, 0xEF, 0x5E, 0x53, 0x6D, 0x3A, 0x9A,
+	0x9B, 0xF6, 0xFC, 0xFD, 0x69, 0xD5, 0xF6, 0x07, 0x9E, 0x43, 0x3E, 0xC5, 0xFD, 0xF3, 0x7C, 0xA7,
+	0xEE, 0xD7, 0x9C, 0xFE, 0xD4, 0x7F, 0xB4, 0xE7, 0xC2, 0x1F, 0xD8, 0xF7, 0xE0, 0x7E, 0xAF, 0xF1,
+	0xF3, 0xE3, 0x9F, 0x8A, 0x2D, 0xF4, 0x7D, 0x07, 0x47, 0x87, 0x32, 0xDC, 0x5D, 0x49, 0xB5, 0x5A,
+	0x46, 0xFB, 0xB1, 0xFF, 0x00, 0xBC, 0xCD, 0xF2, 0xD7, 0xA3, 0xCC, 0xAB, 0x24, 0x8A, 0x8C, 0x2B,
+	0xF1, 0x57, 0xFE, 0x0B, 0x81, 0xE1, 0x9B, 0xCF, 0xDB, 0xF3, 0xFE, 0x0A, 0xDF, 0xF0, 0x27, 0xFE,
+	0x09, 0xF7, 0xE2, 0xBF, 0x19, 0xEA, 0x9A, 0x7F, 0x83, 0x26, 0xB4, 0xBE, 0xBA, 0xD6, 0xB4, 0xAB,
+	0x0B, 0x86, 0x10, 0xDF, 0xC9, 0x0B, 0x2C, 0x8A, 0x65, 0x4F, 0xBA, 0xDF, 0x77, 0x6D, 0x73, 0xD6,
+	0xAD, 0x4F, 0x0F, 0x4E, 0x75, 0x67, 0xF0, 0xC5, 0x5D, 0xDB, 0xB1, 0x54, 0xE3, 0xED, 0x26, 0xA3,
+	0xDC, 0xBB, 0xE2, 0xFF, 0x00, 0xF8, 0x38, 0x8B, 0xF6, 0xEC, 0xFD, 0xAC, 0xBC, 0x2C, 0xFA, 0x9F,
+	0xFC, 0x13, 0x97, 0xFE, 0x09, 0xAD, 0xE3, 0xED, 0x52, 0xC6, 0x3B, 0x89, 0x12, 0x1F, 0x12, 0x7E,
+	0xEE, 0x78, 0x2E, 0x55, 0x5B, 0x68, 0x65, 0x5D, 0xB5, 0xC4, 0x2F, 0xFC, 0x15, 0x27, 0xFE, 0x0E,
+	0x4D, 0x8A, 0x05, 0x57, 0xFF, 0x00, 0x82, 0x71, 0xF8, 0xC1, 0xA4, 0xEA, 0xCD, 0xFD, 0x97, 0x0E,
+	0xDD, 0xB5, 0xFA, 0xB7, 0xF0, 0xFB, 0xC1, 0x5E, 0x0F, 0xF8, 0x3F, 0xE1, 0x4B, 0x3F, 0x07, 0x7C,
+	0x25, 0xF0, 0x8D, 0x8F, 0x87, 0x34, 0xFB, 0x3B, 0x58, 0xED, 0xFE, 0xC3, 0xA5, 0x5B, 0xAC, 0x11,
+	0xFE, 0xED, 0x76, 0xEE, 0xDA, 0xBF, 0xC5, 0x5D, 0x03, 0x6B, 0x9A, 0xE8, 0x45, 0x65, 0xD6, 0xAE,
+	0x19, 0x7F, 0xEB, 0xA7, 0xCD, 0x5F, 0x96, 0xBF, 0x13, 0x2B, 0xDD, 0xB8, 0x61, 0xD5, 0xAE, 0xED,
+	0x7E, 0xDD, 0xF7, 0x47, 0xBD, 0xFD, 0x85, 0x29, 0x45, 0x3E, 0x7B, 0x5F, 0xD4, 0xFC, 0x86, 0xFF,
+	0x00, 0x87, 0xA6, 0xFF, 0x00, 0xC1, 0xC8, 0x81, 0xBE, 0x4F, 0xF8, 0x27, 0x17, 0x8C, 0xBF, 0xDA,
+	0xDD, 0xA5, 0xC5, 0xF7, 0xBF, 0x2A, 0x5F, 0xF8, 0x7A, 0x7F, 0xFC, 0x1C, 0x91, 0xFF, 0x00, 0x48,
+	0xE2, 0xF1, 0x87, 0xFE, 0x0A, 0xE1, 0xAF, 0xD7, 0x7F, 0xED, 0xED, 0x79, 0xB8, 0xFE, 0xDA, 0x9F,
+	0xFE, 0xFE, 0x52, 0xFF, 0x00, 0x6E, 0x6B, 0xDF, 0xF4, 0x18, 0x9F, 0xFE, 0xFE, 0x52, 0xFF, 0x00,
+	0x88, 0x9D, 0x8B, 0xFF, 0x00, 0xA0, 0x78, 0xFF, 0x00, 0x5F, 0x31, 0xFF, 0x00, 0xAB, 0xF2, 0xFE,
+	0x7F, 0xCF, 0xFC, 0x8F, 0xC8, 0x7F, 0xF8, 0x7A, 0x7F, 0xFC, 0x1C, 0x91, 0xFF, 0x00, 0x48, 0xE2,
+	0xF1, 0x87, 0xFE, 0x0A, 0xE1, 0xA3, 0xFE, 0x1E, 0x9F, 0xFF, 0x00, 0x07, 0x24, 0x7F, 0xD2, 0x38,
+	0xBC, 0x61, 0xFF, 0x00, 0x82, 0xB8, 0x6B, 0xF5, 0xE3, 0xFB, 0x73, 0x5E, 0xFF, 0x00, 0xA0, 0xC4,
+	0xFF, 0x00, 0xF7, 0xF2, 0x8F, 0xED, 0xCD, 0x7B, 0xFE, 0x83, 0x13, 0xFF, 0x00, 0xDF, 0xCA, 0x3F,
+	0xE2, 0x26, 0xE2, 0xFF, 0x00, 0xE8, 0x1E, 0x3F, 0xD7, 0xCC, 0x3F, 0xD5, 0xF9, 0x7F, 0xCF, 0xC5,
+	0xF8, 0xFF, 0x00, 0x91, 0xF9, 0x0F, 0xFF, 0x00, 0x0F, 0x4F, 0xFF, 0x00, 0x83, 0x92, 0x3F, 0xE9,
+	0x1C, 0x5E, 0x30, 0xFF, 0x00, 0xC1, 0x5C, 0x34, 0x7F, 0xC3, 0xD3, 0xFF, 0x00, 0xE0, 0xE4, 0x8F,
+	0xFA, 0x47, 0x17, 0x8C, 0x3F, 0xF0, 0x57, 0x0D, 0x7E, 0xBC, 0x7F, 0x6E, 0x6B, 0xDF, 0xF4, 0x18,
+	0x9F, 0xFE, 0xFE, 0x51, 0xFD, 0xB9, 0xAF, 0x7F, 0xD0, 0x62, 0x7F, 0xFB, 0xF9, 0x47, 0xFC, 0x44,
+	0xDC, 0x5F, 0xFD, 0x03, 0xC7, 0xFA, 0xF9, 0x87, 0xFA, 0xBF, 0x2F, 0xF9, 0xF8, 0xBF, 0x1F, 0xF2,
+	0x3F, 0x21, 0xFF, 0x00, 0xE1, 0xE9, 0xFF, 0x00, 0xF0, 0x72, 0x47, 0xFD, 0x23, 0x8B, 0xC6, 0x1F,
+	0xF8, 0x2B, 0x86, 0x8F, 0xF8, 0x7A, 0x7F, 0xFC, 0x1C, 0x91, 0xFF, 0x00, 0x48, 0xE2, 0xF1, 0x87,
+	0xFE, 0x0A, 0xE1, 0xAF, 0xD7, 0x8F, 0xED, 0xCD, 0x7B, 0xFE, 0x83, 0x13, 0xFF, 0x00, 0xDF, 0xCA,
+	0x3F, 0xB7, 0x35, 0xEF, 0xFA, 0x0C, 0x4F, 0xFF, 0x00, 0x7F, 0x28, 0xFF, 0x00, 0x88, 0x9B, 0x8B,
+	0xFF, 0x00, 0xA0, 0x78, 0xFF, 0x00, 0x5F, 0x30, 0xFF, 0x00, 0x57, 0xE5, 0xFF, 0x00, 0x3F, 0x17,
+	0xE3, 0xFE, 0x47, 0xE4, 0x3F, 0xFC, 0x3D, 0x3F, 0xFE, 0x0E, 0x48, 0xFF, 0x00, 0xA4, 0x71, 0x78,
+	0xC3, 0xFF, 0x00, 0x05, 0x70, 0xD1, 0xFF, 0x00, 0x0F, 0x4F, 0xFF, 0x00, 0x83, 0x92, 0x3F, 0xE9,
+	0x1C, 0x5E, 0x30, 0xFF, 0x00, 0xC1, 0x5C, 0x35, 0xFA, 0xF1, 0xFD, 0xB9, 0xAF, 0x7F, 0xD0, 0x62,
+	0x7F, 0xFB, 0xF9, 0x47, 0xF6, 0xE6, 0xBD, 0xFF, 0x00, 0x41, 0x89, 0xFF, 0x00, 0xEF, 0xE5, 0x1F,
+	0xF1, 0x13, 0x71, 0x7F, 0xF4, 0x0F, 0x1F, 0xEB, 0xE6, 0x1F, 0xEA, 0xFC, 0xBF, 0xE7, 0xE2, 0xFC,
+	0x7F, 0xC8, 0xFC, 0x87, 0xFF, 0x00, 0x87, 0xA7, 0xFF, 0x00, 0xC1, 0xC9, 0x1F, 0xF4, 0x8E, 0x2F,
+	0x18, 0x7F, 0xE0, 0xAE, 0x1A, 0x3F, 0xE1, 0xE9, 0xFF, 0x00, 0xF0, 0x72, 0x47, 0xFD, 0x23, 0x8B,
+	0xC6, 0x1F, 0xF8, 0x2B, 0x86, 0xBF, 0x5E, 0x3F, 0xB7, 0x35, 0xEF, 0xFA, 0x0C, 0x4F, 0xFF, 0x00,
+	0x7F, 0x28, 0xFE, 0xDC, 0xD7, 0xBF, 0xE8, 0x31, 0x3F, 0xFD, 0xFC, 0xA3, 0xFE, 0x22, 0x6E, 0x2F,
+	0xFE, 0x81, 0xE3, 0xFD, 0x7C, 0xC3, 0xFD, 0x5F, 0x97, 0xFC, 0xFC, 0x5F, 0x8F, 0xF9, 0x1F, 0x90,
+	0xFF, 0x00, 0xF0, 0xF4, 0xFF, 0x00, 0xF8, 0x39, 0x23, 0xFE, 0x91, 0xC5, 0xE3, 0x0F, 0xFC, 0x15,
+	0xC3, 0x47, 0xFC, 0x3D, 0x3F, 0xFE, 0x0E, 0x48, 0xFF, 0x00, 0xA4, 0x71, 0x78, 0xC3, 0xFF, 0x00,
+	0x05, 0x70, 0xD7, 0xEB, 0xC7, 0xF6, 0xE6, 0xBD, 0xFF, 0x00, 0x41, 0x89, 0xFF, 0x00, 0xEF, 0xE5,
+	0x1F, 0xDB, 0x9A, 0xF7, 0xFD, 0x06, 0x27, 0xFF, 0x00, 0xBF, 0x94, 0x7F, 0xC4, 0x4D, 0xC5, 0xFF,
+	0x00, 0xD0, 0x3C, 0x7F, 0xAF, 0x98, 0x7F, 0xAB, 0xF2, 0xFF, 0x00, 0x9F, 0x8B, 0xF1, 0xFF, 0x00,
+	0x23, 0xF2, 0x1F, 0xFE, 0x1E, 0x9F, 0xFF, 0x00, 0x07, 0x24, 0x7F, 0xD2, 0x38, 0xBC, 0x61, 0xFF,
+	0x00, 0x82, 0xB8, 0x68, 0x6F, 0xF8, 0x2A, 0x6F, 0xFC, 0x1C, 0x90, 0xC3, 0x62, 0x7F, 0xC1, 0x38,
+	0xBC, 0x62, 0xAC, 0xDD, 0xFF, 0x00, 0xB2, 0xE1, 0xAF, 0xD7, 0x8F, 0xED, 0xCD, 0x7B, 0xFE, 0x83,
+	0x13, 0xFF, 0x00, 0xDF, 0xCA, 0x43, 0xAF, 0xEB, 0xAB, 0xF7, 0xF5, 0x7B, 0x8E, 0x7F, 0xBA, 0xD4,
+	0xBF, 0xE2, 0x26, 0xE2, 0xFF, 0x00, 0xE8, 0x1E, 0x3F, 0xD7, 0xCC, 0x6B, 0x20, 0x97, 0xFC, 0xFC,
+	0x5F, 0xD7, 0xC8, 0xFC, 0x86, 0x6F, 0xF8, 0x2A, 0x67, 0xFC, 0x1C, 0x8E, 0xD1, 0x6C, 0x4F, 0xF8,
+	0x27, 0x2F, 0x8C, 0x7C, 0xCE, 0x9B, 0xBF, 0xB2, 0xE1, 0xDB, 0x5D, 0xF7, 0x83, 0xBF, 0xE0, 0xE3,
+	0x1F, 0xDB, 0x1B, 0xF6, 0x4E, 0xD0, 0x6D, 0xE3, 0xFF, 0x00, 0x82, 0x94, 0x7F, 0xC1, 0x38, 0xFC,
+	0x79, 0xA0, 0x5B, 0x5D, 0x5D, 0x46, 0x9F, 0xF0, 0x96, 0x3F, 0x97, 0x0D, 0xBD, 0xBA, 0xB3, 0x6D,
+	0xDD, 0x22, 0xED, 0xAF, 0xD3, 0xB1, 0xAE, 0x6B, 0x93, 0xB6, 0xC5, 0xD6, 0xA7, 0x56, 0x5F, 0xFA,
+	0x69, 0xF7, 0xAB, 0x9A, 0xF8, 0xA9, 0xF0, 0xEB, 0xE1, 0xDF, 0xC7, 0x0F, 0x08, 0x5F, 0x78, 0x27,
+	0xE3, 0x4F, 0x82, 0x74, 0xFF, 0x00, 0x12, 0x58, 0x5E, 0x59, 0xC9, 0x0B, 0x5A, 0xEA, 0x96, 0xAB,
+	0x3C, 0x71, 0xB3, 0x2E, 0xDD, 0xCA, 0xAD, 0x57, 0x1F, 0x13, 0x2A, 0x3A, 0xCB, 0xDA, 0xE1, 0xD2,
+	0x8E, 0x97, 0x6A, 0xF7, 0xB7, 0x5B, 0x6A, 0x44, 0xB2, 0x39, 0x46, 0x2D, 0xF3, 0xDF, 0xFA, 0xF4,
+	0x3D, 0x0F, 0xF6, 0x79, 0xFD, 0xA2, 0x7E, 0x12, 0x7E, 0xD4, 0xBF, 0x07, 0xF4, 0x7F, 0x8E, 0xDF,
+	0x04, 0x7C, 0x63, 0x67, 0xE2, 0x0F, 0x0E, 0xEB, 0x11, 0x6F, 0xB3, 0xBE, 0xB1, 0x6D, 0xC8, 0xCD,
+	0xFC, 0x49, 0xFE, 0xF2, 0xB5, 0x77, 0x71, 0xC6, 0xDF, 0xC5, 0xF7, 0x5B, 0x9D, 0xBF, 0xDD, 0xAF,
+	0xC5, 0xBF, 0xF8, 0x20, 0x16, 0x93, 0xE2, 0x2F, 0xD8, 0x9B, 0xFE, 0x0A, 0x51, 0xF1, 0xF3, 0xFE,
+	0x09, 0xDD, 0x6F, 0xE3, 0x6D, 0x4B, 0x52, 0xF0, 0x6E, 0x8D, 0x6B, 0x6B, 0x79, 0xE1, 0xAD, 0x3E,
+	0xE6, 0x7D, 0xD1, 0x59, 0x49, 0x3B, 0x34, 0x8D, 0xB1, 0x7E, 0xEA, 0xD7, 0xED, 0x34, 0x6C, 0xB2,
+	0x36, 0x31, 0xD2, 0xBF, 0x52, 0xA1, 0x56, 0x9D, 0x6A, 0x71, 0x9C, 0x1B, 0x6A, 0x49, 0x35, 0x7F,
+	0x33, 0xC2, 0x9A, 0x71, 0x93, 0x8B, 0xE8, 0x49, 0x45, 0x14, 0x56, 0xE4, 0x85, 0x14, 0x51, 0x40,
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+	0x3F, 0xF8, 0x36, 0x8F, 0x2D, 0xFB, 0x55, 0xFE, 0xD1, 0x7F, 0xF6, 0x3B, 0x6B, 0x5F, 0xFA, 0x54,
+	0xD5, 0xFB, 0xBC, 0xFD, 0xFF, 0x00, 0xDD, 0xAF, 0xC1, 0xFF, 0x00, 0xF8, 0x36, 0x8D, 0xB1, 0xFB,
+	0x57, 0x7E, 0xD1, 0x89, 0xFF, 0x00, 0x53, 0xB6, 0xB9, 0xFF, 0x00, 0xA5, 0x4D, 0x5F, 0x31, 0xC6,
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+	0xBE, 0x5A, 0xFC, 0x82, 0x95, 0x52, 0x34, 0xFB, 0x8B, 0x8A, 0x45, 0xF9, 0x93, 0x14, 0xEA, 0xFE,
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+	0x40, 0xC1, 0xE1, 0x97, 0x6D, 0x3A, 0x98, 0x44, 0x8C, 0xEA, 0xD8, 0xE3, 0xBE, 0x7D, 0x3D, 0x28,
+	0xF5, 0x25, 0xDF, 0xA0, 0x9B, 0x77, 0x47, 0xBF, 0xEE, 0xFF, 0x00, 0xB5, 0xFD, 0xDA, 0x15, 0xB7,
+	0x4B, 0xE5, 0xA2, 0xFE, 0xEF, 0x6F, 0xFA, 0xCA, 0x75, 0xDC, 0x0A, 0xF2, 0x2B, 0x43, 0x27, 0xF3,
+	0xF9, 0x7F, 0xC6, 0x95, 0x55, 0xCC, 0x27, 0x7C, 0xA0, 0x7F, 0xB0, 0xB9, 0xC9, 0xCF, 0x5C, 0x1E,
+	0xD4, 0x69, 0xC9, 0xCC, 0xDF, 0x4B, 0x75, 0xDF, 0xD2, 0xD7, 0x23, 0x99, 0xE9, 0xA3, 0xD7, 0xF0,
+	0x12, 0x3F, 0xDE, 0x66, 0x4F, 0x2F, 0x01, 0x7E, 0x5D, 0xBF, 0xDE, 0xA6, 0x99, 0x93, 0x6A, 0xBE,
+	0xCE, 0x3F, 0x89, 0xBF, 0xBB, 0x4E, 0xF2, 0x95, 0xD3, 0x6F, 0xCC, 0x9C, 0xFA, 0xF5, 0xF6, 0xA5,
+	0x91, 0x42, 0x94, 0x68, 0x86, 0xE6, 0xDB, 0x86, 0x6F, 0x4A, 0x3E, 0x77, 0xF9, 0x76, 0xF9, 0x69,
+	0xF3, 0x1F, 0xBD, 0x7D, 0x84, 0xEA, 0xCC, 0xFB, 0x76, 0xAB, 0x7D, 0xD5, 0xA2, 0x33, 0xE7, 0x47,
+	0x9D, 0x9B, 0x1D, 0x7F, 0x87, 0xFB, 0xD4, 0xE1, 0x15, 0xB9, 0xB5, 0x6F, 0xB4, 0xE5, 0xD9, 0xFF,
+	0x00, 0xE5, 0x9A, 0x1C, 0x6D, 0xFE, 0x94, 0xD4, 0x81, 0x13, 0x89, 0x5F, 0x76, 0xE5, 0xDB, 0xF2,
+	0xF6, 0x1E, 0x94, 0xBD, 0xD5, 0xCC, 0xBA, 0xF4, 0x76, 0x7B, 0xF5, 0x4F, 0x44, 0x9A, 0xF3, 0x44,
+	0xA7, 0xD3, 0x50, 0xDA, 0x5A, 0x36, 0x7D, 0x9B, 0x59, 0x7F, 0x86, 0x9A, 0xA7, 0xCC, 0xFF, 0x00,
+	0x53, 0xF3, 0x37, 0xFE, 0x85, 0x5F, 0x3B, 0xFC, 0x01, 0xFD, 0xB7, 0x7E, 0x29, 0xFC, 0x61, 0xFD,
+	0xB4, 0x3E, 0x25, 0xFE, 0xCC, 0x3E, 0x24, 0xFD, 0x8D, 0xFC, 0x4F, 0xE1, 0x1F, 0x0F, 0x78, 0x0E,
+	0x18, 0x06, 0x83, 0xF1, 0x33, 0x52, 0xBC, 0x91, 0xEC, 0x7C, 0x4D, 0xBD, 0x54, 0xB2, 0x44, 0x8D,
+	0x6C, 0x88, 0xA5, 0x72, 0x73, 0xB2, 0x69, 0xB1, 0xB4, 0x86, 0xD8, 0x7E, 0x5A, 0xFA, 0x32, 0x58,
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+	0xB3, 0xF2, 0x31, 0xA7, 0x88, 0xA7, 0x52, 0x52, 0x84, 0x6F, 0xEE, 0xC9, 0xC5, 0xE8, 0xF4, 0x69,
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+	0xA6, 0xFF, 0x00, 0xD0, 0x6B, 0xA0, 0xFF, 0x00, 0x96, 0x95, 0xCF, 0x7C, 0x60, 0x07, 0xFE, 0x14,
+	0xEF, 0x8A, 0x93, 0xFE, 0xA0, 0xD3, 0x7F, 0xE8, 0x35, 0xAD, 0x16, 0xFD, 0xAC, 0x7C, 0xDC, 0x7F,
+	0x33, 0x1C, 0x42, 0xFD, 0xCC, 0xBD, 0x0F, 0x89, 0x3F, 0xE0, 0xD4, 0x42, 0xC7, 0xE1, 0x2F, 0xED,
+	0x15, 0x91, 0xF3, 0x7F, 0xC2, 0xF4, 0xBC, 0xFF, 0x00, 0xD1, 0x75, 0xFA, 0xC8, 0xBB, 0xFF, 0x00,
+	0x8A, 0xBF, 0x26, 0xFF, 0x00, 0xE0, 0xD4, 0x3F, 0xF9, 0x24, 0xBF, 0xB4, 0x4F, 0xFD, 0x97, 0x4B,
+	0xCF, 0xFD, 0x17, 0x5F, 0xAC, 0xD5, 0xFD, 0x43, 0x43, 0xF8, 0x31, 0x5E, 0x4B, 0xF2, 0x3F, 0x3C,
+	0x97, 0xC4, 0xC6, 0xC9, 0xF7, 0x0D, 0x0B, 0xD4, 0x52, 0xB1, 0xC2, 0xF1, 0x49, 0xFF, 0x00, 0x2D,
+	0x2B, 0x59, 0x08, 0xFC, 0x39, 0xFD, 0x8E, 0x43, 0x43, 0xFF, 0x00, 0x07, 0x3D, 0xF8, 0xE1, 0x13,
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+	0x53, 0xFE, 0xC7, 0x6D, 0xBB, 0xFE, 0x0E, 0x7C, 0xF1, 0xC0, 0xFF, 0x00, 0xA9, 0x4B, 0x58, 0xFF,
+	0x00, 0xD0, 0xAB, 0xF5, 0x72, 0xBF, 0x10, 0xF1, 0x0F, 0x4E, 0x20, 0x7C, 0xBA, 0x7E, 0xED, 0x7E,
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+	0xF8, 0x5B, 0xBE, 0x64, 0x7B, 0xEF, 0x62, 0x3A, 0x03, 0x60, 0xEF, 0x74, 0xFF, 0x00, 0x80, 0xD2,
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+	0xC5, 0xFD, 0xD6, 0xA0, 0x44, 0xA2, 0x25, 0x88, 0x8F, 0xBA, 0x73, 0xBB, 0xBD, 0x01, 0x18, 0x1C,
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+	0xC0, 0xC3, 0xA6, 0xD7, 0xFE, 0xED, 0x0C, 0xA9, 0xE6, 0x6C, 0xFE, 0x2A, 0x43, 0x17, 0x1F, 0x23,
+	0x63, 0xFD, 0xEE, 0x69, 0xE3, 0x72, 0xE1, 0x94, 0xFC, 0xCA, 0x3E, 0x56, 0xA5, 0x2F, 0x85, 0xB5,
+	0xF7, 0x7E, 0xB7, 0xB0, 0x7B, 0xC4, 0x72, 0x49, 0xF3, 0xEC, 0x85, 0x37, 0x7F, 0x7A, 0x9D, 0xF2,
+	0x6E, 0x5D, 0x9F, 0x32, 0xFF, 0x00, 0x7A, 0x84, 0x42, 0x83, 0x86, 0xE7, 0x39, 0x3C, 0x7F, 0x2F,
+	0x4A, 0x04, 0x44, 0x2F, 0x92, 0x8F, 0xB5, 0x5D, 0xBF, 0x78, 0x7F, 0xAD, 0x57, 0xBB, 0xBB, 0xFF,
+	0x00, 0x86, 0xFE, 0xBC, 0x83, 0xDE, 0xDE, 0xC3, 0x59, 0x91, 0x37, 0x7F, 0x7B, 0x75, 0x39, 0xB6,
+	0x46, 0x40, 0x3F, 0x79, 0xBF, 0x87, 0xFB, 0xB4, 0xE0, 0x02, 0xB2, 0xC4, 0x9F, 0xEA, 0xD5, 0x71,
+	0xBB, 0xB9, 0x3E, 0xB4, 0xD8, 0x56, 0x48, 0xE4, 0x63, 0x23, 0x6F, 0x56, 0xE0, 0x76, 0x20, 0x7D,
+	0x68, 0xB5, 0xD2, 0x57, 0x49, 0xBF, 0xC3, 0xFA, 0xEC, 0x1E, 0xF6, 0xE3, 0xB6, 0xA2, 0xFD, 0xFF,
+	0x00, 0x97, 0xFF, 0x00, 0x65, 0xA6, 0xC2, 0x52, 0x48, 0xFF, 0x00, 0x72, 0xFB, 0xF6, 0xFF, 0x00,
+	0x15, 0x21, 0x8D, 0xDD, 0xBF, 0x7A, 0xF9, 0x51, 0xF7, 0x45, 0x62, 0x7C, 0x4C, 0xF8, 0xA3, 0xF0,
+	0xD7, 0xE0, 0xC7, 0x81, 0x6F, 0xBE, 0x24, 0xFC, 0x5E, 0xF1, 0xEE, 0x87, 0xE1, 0x7F, 0x0F, 0xE9,
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+	0xD3, 0x32, 0xC6, 0x9B, 0x9D, 0xD5, 0x17, 0x24, 0x65, 0x99, 0x40, 0xE4, 0x81, 0x47, 0x2D, 0xDB,
+	0x8C, 0x75, 0x7B, 0x2D, 0x37, 0x7E, 0x5F, 0xA0, 0x5A, 0x51, 0x46, 0xE3, 0x2F, 0xCB, 0xBE, 0x8D,
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+	0x82, 0x41, 0xAB, 0x6A, 0xA4, 0x35, 0x15, 0x21, 0x3A, 0x73, 0xE5, 0x9E, 0x8D, 0x68, 0xD3, 0x56,
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+	0x14, 0x51, 0x53, 0xD5, 0x17, 0x61, 0xF6, 0x8C, 0x5A, 0xEE, 0x17, 0xC7, 0xCC, 0xB2, 0x2E, 0xDF,
+	0xFB, 0xEA, 0xBE, 0x0A, 0xFF, 0x00, 0x82, 0x2C, 0x7E, 0xFB, 0xFE, 0x0A, 0xDB, 0xFB, 0x6D, 0x4D,
+	0x37, 0xCC, 0xFF, 0x00, 0xF0, 0x9E, 0x59, 0xFC, 0xDF, 0xF6, 0xC6, 0xBE, 0xF4, 0xB3, 0xFF, 0x00,
+	0x8F, 0x98, 0xFF, 0x00, 0xEB, 0xA2, 0xD7, 0xC1, 0x1F, 0xF0, 0x45, 0x1F, 0xF9, 0x4B, 0x5F, 0xED,
+	0xB5, 0xFF, 0x00, 0x63, 0xE5, 0x9F, 0xFE, 0x89, 0xAF, 0xD2, 0xFC, 0x31, 0xD7, 0x34, 0xAF, 0xFF,
+	0x00, 0x5E, 0xFF, 0x00, 0x54, 0x7C, 0xDF, 0x10, 0x69, 0x4A, 0x3E, 0xBF, 0xE6, 0x7E, 0xAE, 0xD1,
+	0x45, 0x15, 0xFB, 0x09, 0xF3, 0x03, 0x5D, 0x7E, 0x60, 0x6B, 0xF1, 0x9B, 0xF6, 0xA0, 0xFD, 0xDF,
+	0xFC, 0x1C, 0xF1, 0xF0, 0x5C, 0xFF, 0x00, 0xD4, 0x17, 0x56, 0xFF, 0x00, 0xD1, 0x75, 0xFB, 0x32,
+	0xDD, 0x45, 0x7E, 0x31, 0xFE, 0xD4, 0xDF, 0xF2, 0xB3, 0xE7, 0xC1, 0x7F, 0xFB, 0x02, 0xEB, 0x1F,
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+	0xFB, 0xD4, 0x7D, 0x4F, 0xD3, 0x7B, 0xA6, 0xDF, 0x78, 0xCC, 0xFF, 0x00, 0x79, 0x5A, 0x99, 0xB7,
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+	0x9F, 0x91, 0xFA, 0x14, 0x55, 0xE2, 0x86, 0xBE, 0x15, 0x7E, 0x44, 0xDC, 0xCD, 0x41, 0x8F, 0xCA,
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+	0x87, 0x66, 0xFE, 0x2F, 0xC2, 0x9B, 0x14, 0x4B, 0x0C, 0x45, 0x55, 0x8E, 0xE6, 0xFE, 0x5E, 0x99,
+	0xA5, 0xA4, 0xA0, 0xA5, 0xD5, 0xEE, 0xBB, 0x79, 0x12, 0xB9, 0xBA, 0x8D, 0x8D, 0x92, 0x6D, 0xCE,
+	0x8F, 0xC5, 0x0D, 0x22, 0xA0, 0xFF, 0x00, 0x57, 0xB9, 0x57, 0xEF, 0x50, 0xF0, 0x79, 0xB2, 0xA9,
+	0x91, 0xF0, 0x8B, 0xFD, 0xDF, 0xF3, 0xD6, 0x9C, 0xE1, 0xD9, 0xB6, 0x6D, 0x5D, 0x83, 0xEE, 0xF3,
+	0xCF, 0xD4, 0xD3, 0x96, 0x9A, 0xA7, 0xA7, 0x6D, 0xD8, 0x5B, 0x6B, 0x8D, 0x69, 0x04, 0x3B, 0x7C,
+	0xE8, 0xFE, 0x69, 0x3E, 0xEA, 0xD0, 0xCD, 0xB4, 0x7F, 0xAB, 0xF9, 0xBF, 0x8B, 0xFD, 0x9A, 0x7E,
+	0x0C, 0x6B, 0xB2, 0x12, 0x36, 0x9E, 0xEC, 0xBC, 0xD2, 0x7E, 0xFB, 0x66, 0xD2, 0xCA, 0x73, 0xC3,
+	0x1F, 0xEF, 0x2D, 0x3F, 0x85, 0xDA, 0xF7, 0xF9, 0x09, 0xBE, 0x5F, 0x7A, 0xC3, 0x59, 0x7F, 0x83,
+	0xBF, 0xDE, 0xDD, 0xFE, 0xCD, 0x37, 0xCE, 0x46, 0x8B, 0xCC, 0x4F, 0xF5, 0x6D, 0xFF, 0x00, 0x2D,
+	0xBF, 0xBB, 0x5E, 0x13, 0xFB, 0x0A, 0xFE, 0xD6, 0xBF, 0x1A, 0x3F, 0x6A, 0x1B, 0xCF, 0x89, 0x16,
+	0xFF, 0x00, 0x18, 0x7F, 0x62, 0xEF, 0x16, 0xFC, 0x20, 0x5F, 0x05, 0xF8, 0xCA, 0x4D, 0x1F, 0xC3,
+	0xF2, 0xF8, 0xA2, 0x69, 0x99, 0x7C, 0x4D, 0x68, 0xA6, 0x40, 0x2F, 0xAD, 0xFC, 0xDB, 0x68, 0x3E,
+	0x43, 0xB1, 0x7E, 0xE1, 0x95, 0x3F, 0x78, 0xBB, 0x64, 0x6E, 0x6B, 0xDE, 0x95, 0x48, 0x76, 0x66,
+	0x39, 0x04, 0xFD, 0xDF, 0xE9, 0x5B, 0xE2, 0xB0, 0x75, 0xB0, 0x35, 0xFD, 0x95, 0x46, 0xB6, 0x8B,
+	0xD1, 0xA7, 0xA4, 0xA2, 0xA4, 0xB5, 0x4D, 0xAD, 0x9A, 0xBA, 0xDD, 0x3D, 0x1A, 0x4D, 0x34, 0x65,
+	0x4A, 0xA2, 0xAD, 0x16, 0xE3, 0x7B, 0x26, 0xD3, 0xE9, 0xAC, 0x5B, 0x4F, 0x7F, 0x34, 0xF5, 0xD9,
+	0xEE, 0xAE, 0x86, 0xBA, 0xFC, 0xEC, 0x91, 0x8D, 0xC3, 0xFB, 0xD4, 0xEF, 0xF5, 0x7F, 0x3C, 0x69,
+	0xBD, 0x76, 0xFD, 0xDF, 0xEE, 0xD3, 0xA3, 0x2C, 0xB2, 0x2C, 0x92, 0x36, 0xE6, 0x5F, 0xBB, 0xDA,
+	0x85, 0x01, 0x59, 0x98, 0x7F, 0x17, 0x1D, 0x78, 0xC5, 0x73, 0x59, 0xA8, 0xAE, 0xAF, 0xFA, 0xF2,
+	0x36, 0xB5, 0x4E, 0xA4, 0x7F, 0x68, 0x84, 0x27, 0xCC, 0x9F, 0x3F, 0xF7, 0x68, 0x92, 0x45, 0x6F,
+	0x91, 0x3E, 0xF3, 0x7D, 0xDA, 0x71, 0x45, 0x29, 0xB3, 0x1F, 0xFD, 0x7A, 0x5D, 0xA0, 0xB2, 0x97,
+	0x3B, 0x82, 0x7D, 0xD5, 0x3D, 0x07, 0x18, 0xC5, 0x1F, 0xD5, 0xBF, 0x3D, 0x77, 0x1F, 0xBC, 0x31,
+	0xD9, 0xA3, 0x46, 0x8D, 0x61, 0xDF, 0xFD, 0xD6, 0xFE, 0xF5, 0x0C, 0xB8, 0xE0, 0xD7, 0x9A, 0x7E,
+	0xD5, 0x9F, 0xB6, 0x3F, 0xEC, 0xD7, 0xFB, 0x11, 0xF8, 0x23, 0x4B, 0xF8, 0x9D, 0xFB, 0x4D, 0xFC,
+	0x44, 0xFF, 0x00, 0x84, 0x5F, 0x44, 0xD6, 0x35, 0xF8, 0x34, 0x4D, 0x36, 0xF0, 0x69, 0x17, 0xB7,
+	0xC2, 0x6B, 0xF9, 0xA3, 0x91, 0xE3, 0x8B, 0x65, 0xAC, 0x52, 0xBA, 0xEE, 0x48, 0x64, 0x3B, 0x98,
+	0x05, 0x1B, 0x79, 0x20, 0x91, 0x9F, 0x4F, 0x91, 0x5E, 0x3B, 0xA9, 0x22, 0x99, 0x76, 0xB4, 0x6C,
+	0x55, 0xBD, 0x88, 0xE2, 0xB6, 0x96, 0x17, 0x15, 0x1C, 0x2A, 0xC4, 0x38, 0x35, 0x4D, 0xB6, 0x94,
+	0xAC, 0xF9, 0x5B, 0x56, 0x6D, 0x27, 0x6B, 0x36, 0x93, 0x57, 0x5B, 0xAB, 0xA3, 0x38, 0xCE, 0x3E,
+	0xD3, 0xD9, 0xF3, 0x2E, 0x6B, 0x5E, 0xD7, 0xD6, 0xD7, 0xB5, 0xED, 0xDA, 0xE9, 0xAB, 0xED, 0x74,
+	0x26, 0xC4, 0xDD, 0xBF, 0x1C, 0xD2, 0x32, 0x79, 0x7B, 0xDD, 0x3E, 0xF3, 0x2F, 0xCD, 0x4E, 0xA6,
+	0xBF, 0xFA, 0xA6, 0xFF, 0x00, 0x76, 0xB3, 0x97, 0x5F, 0x43, 0x59, 0x6C, 0x7E, 0x68, 0x7F, 0xC1,
+	0x3B, 0x79, 0xFF, 0x00, 0x83, 0x8A, 0xFF, 0x00, 0x68, 0x24, 0x7F, 0xFA, 0x03, 0x69, 0x3F, 0xFA,
+	0x0D, 0x7E, 0xCB, 0x60, 0x2C, 0x9B, 0xAB, 0xF1, 0xA3, 0xFE, 0x09, 0xD4, 0x73, 0xFF, 0x00, 0x07,
+	0x17, 0xFE, 0xD0, 0x68, 0x7F, 0xE8, 0x0B, 0xA4, 0xFF, 0x00, 0xE8, 0x35, 0xFB, 0x31, 0xB7, 0xE6,
+	0xC5, 0x7F, 0x4C, 0x65, 0x37, 0xFE, 0xCC, 0xA0, 0xDB, 0xFB, 0x31, 0xFC, 0x91, 0xF9, 0xD5, 0x7F,
+	0xE3, 0xCF, 0xD5, 0x8E, 0xA2, 0x8A, 0x2B, 0xD2, 0x32, 0x0A, 0x28, 0xA2, 0x80, 0x38, 0x9F, 0xDA,
+	0x4B, 0xFE, 0x4D, 0xDF, 0xC7, 0x9F, 0xF6, 0x27, 0xEA, 0x5F, 0xFA, 0x4B, 0x25, 0x7E, 0x47, 0x7F,
+	0xC1, 0xB1, 0xEB, 0x8F, 0x85, 0xDF, 0x16, 0x0F, 0xFD, 0x4C, 0x30, 0xFF, 0x00, 0xE8, 0x4D, 0x5F,
+	0xAE, 0x3F, 0xB4, 0x9F, 0xFC, 0x9B, 0xC7, 0x8F, 0x3F, 0xEC, 0x4F, 0xD4, 0xBF, 0xF4, 0x96, 0x4A,
+	0xFC, 0x8E, 0xFF, 0x00, 0x83, 0x64, 0x3F, 0xE4, 0x97, 0x7C, 0x58, 0xFF, 0x00, 0xB0, 0xF4, 0x3F,
+	0xFA, 0x13, 0x57, 0xC7, 0x71, 0xCF, 0xFC, 0x93, 0x75, 0x17, 0x9A, 0xFC, 0xCF, 0x53, 0x28, 0xFF,
+	0x00, 0x7C, 0x5F, 0xD7, 0x54, 0x7E, 0x9F, 0xD1, 0x45, 0x15, 0xF8, 0x25, 0x8F, 0xB8, 0x0A, 0x28,
+	0xA2, 0x80, 0x0A, 0x28, 0xA2, 0x8F, 0x40, 0x3E, 0x49, 0xFF, 0x00, 0x82, 0xEA, 0x7C, 0x43, 0xF8,
+	0x9D, 0xF0, 0xBB, 0xFE, 0x09, 0x31, 0xF1, 0xA3, 0xC6, 0x3F, 0x09, 0x6F, 0xEF, 0xAC, 0xF5, 0xA4,
+	0xF0, 0xF4, 0x36, 0xEB, 0x77, 0xA6, 0xB3, 0x2C, 0xF6, 0xF6, 0xD3, 0xDF, 0xDB, 0x5B, 0xDD, 0x3A,
+	0x32, 0x7C, 0xCB, 0xB6, 0xDA, 0x59, 0xB2, 0xC3, 0x1B, 0x46, 0x5B, 0x23, 0x15, 0xF9, 0x75, 0xE0,
+	0x1F, 0xF8, 0x25, 0xCF, 0xED, 0xA3, 0xF1, 0xCF, 0xF6, 0x0A, 0xF8, 0x2F, 0xF1, 0x9B, 0xE1, 0x11,
+	0xFD, 0x86, 0x7E, 0x18, 0x68, 0x3A, 0x0A, 0xF8, 0x7F, 0xC4, 0x3E, 0x17, 0xF8, 0xD5, 0xE1, 0xC9,
+	0xF5, 0xAD, 0x1F, 0xC5, 0x5F, 0x6C, 0x47, 0x58, 0x21, 0xFE, 0xD0, 0xD4, 0xDA, 0xDE, 0x48, 0xE4,
+	0xBA, 0x6B, 0xC9, 0x04, 0x72, 0x46, 0x72, 0xA2, 0xED, 0x55, 0x23, 0x0A, 0x51, 0x14, 0x7E, 0xF7,
+	0xEB, 0xFA, 0x1E, 0x85, 0xE2, 0xDD, 0x06, 0xFB, 0xC2, 0x5E, 0x2B, 0xD0, 0xEC, 0xF5, 0x3D, 0x2F,
+	0x54, 0xB1, 0x9A, 0xCB, 0x52, 0xD3, 0xB5, 0x0B, 0x65, 0x9A, 0xDE, 0xF2, 0xD6, 0x54, 0x31, 0xCB,
+	0x04, 0xB1, 0xB8, 0x2B, 0x24, 0x6E, 0x8E, 0xCA, 0xC8, 0xC0, 0xAB, 0x29, 0x20, 0x82, 0x09, 0x15,
+	0xF2, 0x9F, 0xC3, 0xEF, 0xF8, 0x21, 0x0F, 0xFC, 0x12, 0x57, 0xE1, 0x77, 0xC6, 0x1B, 0x5F, 0x8E,
+	0xDE, 0x0B, 0xFD, 0x8B, 0xF4, 0x28, 0x3C, 0x45, 0x63, 0xA9, 0xC9, 0xA8, 0x59, 0x35, 0xD6, 0xB1,
+	0xA8, 0xDD, 0x58, 0xC1, 0x70, 0xC5, 0x8E, 0xF4, 0xB0, 0x9E, 0xE5, 0xED, 0x14, 0x29, 0x6D, 0xD1,
+	0xA8, 0x8B, 0x6C, 0x45, 0x50, 0xC6, 0x10, 0xA2, 0x91, 0xF7, 0x1C, 0x33, 0xC4, 0xB8, 0x5C, 0x8E,
+	0x9C, 0xA1, 0x2B, 0xC6, 0x5E, 0xD6, 0x15, 0x23, 0x38, 0x45, 0x4B, 0x48, 0x27, 0x68, 0xB5, 0x29,
+	0x47, 0xAB, 0xBA, 0x77, 0xB2, 0xD6, 0xF1, 0x77, 0xD3, 0xC9, 0xCC, 0x70, 0x35, 0x31, 0x91, 0x8F,
+	0x2A, 0x4D, 0x28, 0xCE, 0x2E, 0x2F, 0x44, 0xF9, 0xF9, 0x7A, 0xD9, 0xFF, 0x00, 0x2D, 0x9E, 0x8F,
+	0xA5, 0xAD, 0x6D, 0x7E, 0x5E, 0xFD, 0xB5, 0x6F, 0xF5, 0x7F, 0xDA, 0xBB, 0xFE, 0x0A, 0xF7, 0xE3,
+	0x6F, 0xD9, 0x33, 0xF6, 0x54, 0xFD, 0x83, 0x3F, 0x66, 0xBF, 0x16, 0x7C, 0x42, 0xF0, 0x6F, 0xC3,
+	0x9D, 0x37, 0x50, 0xF1, 0xD7, 0x8E, 0xFF, 0x00, 0x69, 0xFD, 0x3A, 0xF3, 0x56, 0xB4, 0xB8, 0xB1,
+	0xDB, 0x6F, 0x35, 0xAD, 0xB6, 0x9D, 0x67, 0x10, 0x63, 0x6D, 0xE5, 0xFF, 0x00, 0x69, 0xFE, 0xF2,
+	0x64, 0x42, 0x26, 0x2E, 0x03, 0x95, 0x11, 0x44, 0x64, 0xF0, 0x4F, 0xF8, 0x24, 0x6F, 0xC1, 0xDB,
+	0x8F, 0xDA, 0x57, 0xFE, 0x09, 0x6B, 0xFB, 0x64, 0x7E, 0xCA, 0x1A, 0xA7, 0xC7, 0x8F, 0x09, 0xF8,
+	0x02, 0xCF, 0xC4, 0x1F, 0x16, 0x5B, 0x4F, 0xD2, 0x75, 0xDD, 0x0F, 0x54, 0x30, 0xF8, 0x72, 0xD6,
+	0xFE, 0xE1, 0xED, 0xA3, 0x8E, 0x1B, 0x57, 0x76, 0x04, 0xD9, 0x5D, 0x4B, 0x15, 0xBD, 0xAA, 0xAE,
+	0x4B, 0xC9, 0x0C, 0xA8, 0xA0, 0x3B, 0x30, 0x53, 0xFA, 0x91, 0xFB, 0x5C, 0x7F, 0xC1, 0x25, 0x7F,
+	0xE0, 0x9D, 0xFF, 0x00, 0xB7, 0x57, 0x8E, 0xEC, 0xFE, 0x27, 0xFE, 0xD4, 0x9F, 0xB3, 0x3E, 0x9B,
+	0xE2, 0x4F, 0x10, 0xD8, 0xDA, 0x7D, 0x96, 0x3D, 0x62, 0xDF, 0x56, 0xBF, 0xD3, 0x6E, 0x25, 0x84,
+	0x63, 0x6A, 0x4C, 0xF6, 0x33, 0xC2, 0x6E, 0x02, 0xE3, 0x0B, 0xE6, 0xEF, 0xD8, 0x09, 0x0B, 0x80,
+	0xC4, 0x1D, 0x0F, 0x08, 0xFF, 0x00, 0xC1, 0x2E, 0xBF, 0x60, 0x2F, 0x01, 0xFC, 0x26, 0xF8, 0x89,
+	0xF0, 0x1F, 0xC2, 0x3F, 0xB3, 0x1E, 0x83, 0x63, 0xE0, 0xBF, 0x8A, 0xB7, 0xEF, 0x7B, 0xE3, 0x8F,
+	0x0B, 0xC5, 0x25, 0xC1, 0xB1, 0xBB, 0x9C, 0xF4, 0x78, 0x62, 0x32, 0x15, 0xB1, 0xF2, 0xC8, 0x56,
+	0x88, 0x5A, 0x88, 0x44, 0x2C, 0x88, 0xD1, 0x84, 0x64, 0x52, 0x3A, 0xE8, 0xF1, 0x56, 0x53, 0x0C,
+	0x96, 0x58, 0x6E, 0x49, 0xC6, 0x72, 0x84, 0x22, 0xEC, 0x93, 0x49, 0xC6, 0xBC, 0x2A, 0xB9, 0x45,
+	0xB9, 0x68, 0x9C, 0x63, 0x68, 0xC1, 0x42, 0xD1, 0x69, 0x6E, 0x9B, 0x6B, 0x29, 0x65, 0xD8, 0xA5,
+	0x8F, 0xA5, 0x56, 0x32, 0x4E, 0x30, 0x92, 0x92, 0x6E, 0xF7, 0xB7, 0xB2, 0x70, 0xD7, 0x4F, 0x79,
+	0xF3, 0x3B, 0xDD, 0xC9, 0x5E, 0x3A, 0x69, 0x64, 0x7C, 0x0F, 0xFF, 0x00, 0x04, 0xFC, 0x69, 0x7F,
+	0x62, 0x5F, 0xF8, 0x28, 0x57, 0xC2, 0x9F, 0xD8, 0x4B, 0xF6, 0xD4, 0xFF, 0x00, 0x82, 0x6C, 0xFC,
+	0x1A, 0xF0, 0x8F, 0xC4, 0xC9, 0xFC, 0x2F, 0x7E, 0xBF, 0x0A, 0xFE, 0x37, 0x7C, 0x12, 0xF2, 0xED,
+	0x63, 0xD7, 0xAD, 0x2D, 0xF4, 0xBF, 0x2A, 0x57, 0xD4, 0x20, 0xF9, 0x6E, 0x27, 0x79, 0x85, 0xB5,
+	0xD8, 0x7B, 0x9B, 0x80, 0xB9, 0x9F, 0x1B, 0x6D, 0x94, 0x16, 0x9C, 0x7C, 0x9F, 0xFF, 0x00, 0x04,
+	0xE4, 0xFD, 0x93, 0xBF, 0x6D, 0x8F, 0xF8, 0x29, 0x5F, 0xC2, 0x6F, 0x8E, 0xDA, 0xF7, 0x86, 0xFE,
+	0x15, 0x7E, 0xC9, 0x7E, 0x33, 0xF1, 0x37, 0x89, 0xBE, 0x20, 0x6A, 0x96, 0x5E, 0x3A, 0xD7, 0xBE,
+	0x3C, 0x69, 0x7A, 0xD5, 0xCF, 0x8D, 0xB4, 0x1B, 0xAB, 0x9B, 0x70, 0x89, 0xF6, 0x49, 0xAD, 0xA3,
+	0x71, 0x63, 0x12, 0xE2, 0x43, 0x6E, 0xC9, 0x86, 0x12, 0xC5, 0x28, 0x39, 0x11, 0x2A, 0xAF, 0xEC,
+	0xE7, 0xEC, 0x87, 0xFF, 0x00, 0x04, 0x9D, 0xFF, 0x00, 0x82, 0x7A, 0x7E, 0xC1, 0xFE, 0x30, 0xBE,
+	0xF8, 0x85, 0xFB, 0x2B, 0xFE, 0xCD, 0x1A, 0x5F, 0x86, 0xF5, 0xED, 0x46, 0xD9, 0x6D, 0xE6, 0xD6,
+	0xAE, 0x35, 0x4B, 0xED, 0x4E, 0xEA, 0x38, 0x46, 0xEC, 0xC7, 0x0C, 0xB7, 0xD3, 0xCC, 0xD6, 0xEA,
+	0xDB, 0xBE, 0x71, 0x11, 0x41, 0x26, 0x17, 0x7E, 0xED, 0x8B, 0x8E, 0x67, 0xF6, 0x84, 0xFF, 0x00,
+	0x82, 0x1E, 0x7F, 0xC1, 0x2B, 0x3F, 0x6A, 0x4F, 0x8A, 0x77, 0xFF, 0x00, 0x1A, 0xBE, 0x34, 0xFE,
+	0xC8, 0x3A, 0x4D, 0xF7, 0x89, 0xB5, 0x57, 0x32, 0x6A, 0x9A, 0x8E, 0x93, 0xAE, 0x6A, 0x5A, 0x48,
+	0xBD, 0x98, 0xBB, 0x3B, 0xCF, 0x34, 0x56, 0x17, 0x30, 0xC7, 0x2C, 0xCE, 0xCE, 0xC5, 0xE6, 0x65,
+	0x32, 0x39, 0x3F, 0x33, 0x36, 0x06, 0x3A, 0x6A, 0xF1, 0x96, 0x57, 0x5A, 0xAC, 0xE7, 0x28, 0xCF,
+	0xDA, 0x54, 0xA6, 0xA3, 0x2A, 0x9C, 0xAB, 0xE2, 0x55, 0x7D, 0xA5, 0xD5, 0x37, 0x51, 0xA8, 0xC5,
+	0xAF, 0x89, 0x46, 0x70, 0x4E, 0x5E, 0xF5, 0x93, 0xBF, 0x36, 0x54, 0xB2, 0x9C, 0x45, 0x1A, 0x7C,
+	0x90, 0xB2, 0x8C, 0x66, 0xA5, 0x18, 0xDE, 0xFA, 0x28, 0x38, 0xBB, 0xCB, 0x95, 0x36, 0xF5, 0xD2,
+	0xEA, 0x56, 0x8A, 0xB3, 0x6F, 0x4E, 0x5E, 0x93, 0xFE, 0x09, 0x2F, 0xF0, 0xBF, 0xE2, 0x07, 0xC1,
+	0x0F, 0xF8, 0x27, 0x2F, 0xC2, 0xCF, 0x83, 0xBF, 0x13, 0xFE, 0x34, 0x78, 0x67, 0xE2, 0x06, 0xAD,
+	0xA0, 0xE8, 0x93, 0x5A, 0xC7, 0xE2, 0xFF, 0x00, 0x07, 0xEB, 0xCF, 0xA9, 0x69, 0x97, 0x96, 0x69,
+	0x77, 0x71, 0xF6, 0x25, 0xB5, 0xB9, 0x78, 0xE3, 0x32, 0x47, 0x15, 0xA1, 0x82, 0x11, 0xF2, 0x80,
+	0xBE, 0x4E, 0xD1, 0x90, 0xA0, 0x9F, 0xA2, 0xBA, 0x0A, 0xC7, 0xF0, 0x2F, 0x80, 0x3C, 0x07, 0xF0,
+	0xC3, 0xC1, 0xDA, 0x6F, 0xC3, 0xBF, 0x86, 0xFE, 0x0A, 0xD3, 0x74, 0x1D, 0x0F, 0x47, 0xB6, 0x5B,
+	0x6D, 0x23, 0x49, 0xD1, 0x6C, 0xD2, 0xD6, 0xD6, 0xCA, 0x21, 0xD1, 0x23, 0x8A, 0x30, 0x15, 0x57,
+	0x9C, 0xE0, 0x01, 0x5B, 0x15, 0xF0, 0xF9, 0xCE, 0x63, 0x2C, 0xD3, 0x36, 0xAF, 0x8B, 0xFF, 0x00,
+	0x9F, 0x93, 0x94, 0xB6, 0x51, 0x6E, 0xED, 0xBB, 0xB4, 0xAE, 0x93, 0x7B, 0xBB, 0x37, 0xAD, 0xF5,
+	0x3D, 0x2C, 0x0E, 0x1B, 0xEA, 0x98, 0x68, 0x51, 0x4A, 0xDC, 0xA9, 0x2B, 0x5E, 0xE9, 0x69, 0xB2,
+	0x6D, 0x2D, 0x16, 0xCB, 0x45, 0xA2, 0x5A, 0x20, 0xA2, 0x8A, 0x2B, 0xCB, 0xF3, 0x3B, 0x82, 0x8A,
+	0x28, 0xA0, 0x02, 0xBC, 0x23, 0xFE, 0x0A, 0x6A, 0x7F, 0xE3, 0x07, 0xFC, 0x72, 0x3F, 0xEA, 0x1A,
+	0xDF, 0xFA, 0x0B, 0x57, 0xBB, 0xD7, 0x83, 0xFF, 0x00, 0xC1, 0x4D, 0x3F, 0xE4, 0xC7, 0xBC, 0x71,
+	0xFF, 0x00, 0x60, 0xD6, 0xFF, 0x00, 0xD0, 0x5A, 0xBB, 0x32, 0xF4, 0xFE, 0xBB, 0x4F, 0xFC, 0x51,
+	0xFC, 0xD1, 0xCF, 0x8B, 0xFF, 0x00, 0x77, 0x97, 0xA1, 0xC5, 0xFF, 0x00, 0xC1, 0xAC, 0xDF, 0xF2,
+	0x86, 0xEF, 0x01, 0xFF, 0x00, 0xD8, 0x6B, 0x58, 0xFF, 0x00, 0xD2, 0xC7, 0xAF, 0xD1, 0x34, 0xFB,
+	0xB5, 0xF9, 0xD9, 0xFF, 0x00, 0x06, 0xB3, 0xFF, 0x00, 0xCA, 0x1C, 0x3C, 0x07, 0xFF, 0x00, 0x61,
+	0xBD, 0x63, 0xFF, 0x00, 0x4A, 0x9A, 0xBF, 0x44, 0xD5, 0xB3, 0x5F, 0xD3, 0xE7, 0xE7, 0x62, 0xD6,
+	0x3F, 0x8F, 0xB9, 0xF0, 0x1E, 0xB7, 0xFF, 0x00, 0x60, 0x9B, 0xAF, 0xFD, 0x16, 0xD5, 0xAE, 0xFF,
+	0x00, 0x76, 0xB2, 0x3C, 0x7D, 0xFF, 0x00, 0x22, 0x1E, 0xB7, 0xFF, 0x00, 0x60, 0x9B, 0xAF, 0xFD,
+	0x16, 0xD4, 0xC0, 0xFC, 0x31, 0xFF, 0x00, 0x83, 0x5B, 0x7F, 0xE4, 0xE3, 0x7F, 0x69, 0x8F, 0xFA,
+	0xF8, 0xFF, 0x00, 0xDB, 0x86, 0xAF, 0xD7, 0xEE, 0x82, 0xBF, 0x1F, 0xFF, 0x00, 0xE0, 0xD6, 0xFF,
+	0x00, 0xF9, 0x38, 0xBF, 0xDA, 0x63, 0xFE, 0xBE, 0x3F, 0xF6, 0xE1, 0xAB, 0xF6, 0x01, 0x49, 0x2B,
+	0x5F, 0xCF, 0x7C, 0x65, 0xFF, 0x00, 0x25, 0x25, 0x65, 0xE6, 0xBF, 0x23, 0xEC, 0xB2, 0x3F, 0xF7,
+	0x50, 0xA2, 0x8A, 0x2B, 0xE6, 0x65, 0xA4, 0x8F, 0x68, 0x28, 0xA2, 0x8A, 0x39, 0xBD, 0xD6, 0x03,
+	0x5C, 0x92, 0x70, 0x6B, 0xF3, 0x0F, 0xFE, 0x0A, 0xAB, 0xFF, 0x00, 0x29, 0xCB, 0xFD, 0x85, 0x7F,
+	0xEB, 0xFF, 0x00, 0x5B, 0xFE, 0x51, 0x57, 0xE9, 0xE1, 0x04, 0x9D, 0xA1, 0x2B, 0xE6, 0x1F, 0xDA,
+	0xAB, 0xFE, 0x09, 0xC4, 0x7F, 0x69, 0xBF, 0xDB, 0x9B, 0xE0, 0x5F, 0xED, 0x9E, 0x3E, 0x31, 0xFF,
+	0x00, 0x62, 0x7F, 0xC2, 0x95, 0xB8, 0xBD, 0x97, 0xFE, 0x11, 0xAF, 0xF8, 0x47, 0x7E, 0xD3, 0xFD,
+	0xB3, 0xF6, 0x8D, 0xBC, 0x7D, 0xA3, 0xED, 0x09, 0xF6, 0x7D, 0xBB, 0x7F, 0xE7, 0x9C, 0x99, 0xCF,
+	0x6A, 0xF6, 0x78, 0x53, 0x1D, 0x85, 0xCB, 0x78, 0x8B, 0x0F, 0x8A, 0xC4, 0xCB, 0x96, 0x10, 0x72,
+	0xE6, 0x76, 0x6E, 0xD7, 0x84, 0x92, 0xD1, 0x26, 0xF7, 0x6B, 0x64, 0x79, 0x79, 0xB5, 0x1A, 0x98,
+	0x8C, 0xA7, 0x11, 0x46, 0x9A, 0xBC, 0xA7, 0x1B, 0x25, 0xDD, 0xF3, 0x45, 0xEE, 0xF4, 0xD9, 0x75,
+	0x3E, 0x69, 0xFD, 0x94, 0x7E, 0x3C, 0xFC, 0x72, 0xF1, 0x1F, 0xFC, 0x15, 0xC7, 0xF6, 0xE3, 0xF8,
+	0x6D, 0xE2, 0x1F, 0x8C, 0xFE, 0x2C, 0xBE, 0xF0, 0xEF, 0x84, 0xBC, 0x27, 0x65, 0x37, 0x85, 0x74,
+	0x0B, 0xCF, 0x11, 0x5C, 0xCB, 0x65, 0xA3, 0x48, 0xD6, 0x8A, 0xC5, 0xED, 0x20, 0x67, 0x31, 0xDB,
+	0xB1, 0x6E, 0x49, 0x8D, 0x54, 0x93, 0xCD, 0x7C, 0xB3, 0xFB, 0x30, 0x78, 0x6B, 0xF6, 0xDE, 0xFD,
+	0xA7, 0xFF, 0x00, 0xE0, 0x87, 0x1E, 0x26, 0xFD, 0xBC, 0xFC, 0x6B, 0xFF, 0x00, 0x05, 0x4A, 0xF8,
+	0xF1, 0x63, 0xE2, 0x6F, 0x86, 0x1A, 0x47, 0x88, 0xAF, 0x3C, 0x17, 0xA5, 0xF8, 0x7F, 0xC6, 0x0D,
+	0x67, 0x6F, 0x32, 0xD9, 0x4A, 0x6E, 0x66, 0x1A, 0xB5, 0xC6, 0xD7, 0xBB, 0xD5, 0xDA, 0x40, 0xAC,
+	0x91, 0x99, 0x66, 0x51, 0x02, 0xED, 0x45, 0x1B, 0x03, 0x06, 0xFD, 0x29, 0xF8, 0x37, 0xFF, 0x00,
+	0x04, 0xC3, 0x1F, 0x09, 0x7F, 0x6D, 0x4F, 0xDA, 0x0B, 0xF6, 0xBE, 0xFF, 0x00, 0x85, 0xE1, 0xFD,
+	0xA1, 0xFF, 0x00, 0x0B, 0xD7, 0x47, 0xB7, 0xD3, 0xFF, 0x00, 0xE1, 0x1D, 0xFF, 0x00, 0x84, 0x6B,
+	0xCA, 0xFE, 0xC3, 0xF2, 0xE0, 0x11, 0x6F, 0xF3, 0xFE, 0xD2, 0xDF, 0x69, 0xCE, 0x33, 0xB7, 0xCB,
+	0x8B, 0xD3, 0x27, 0xAD, 0x60, 0x7E, 0xCC, 0x9F, 0xF0, 0x48, 0xF5, 0xFD, 0x9D, 0x3F, 0xE0, 0x95,
+	0x1E, 0x30, 0xFF, 0x00, 0x82, 0x66, 0x7F, 0xC3, 0x42, 0x0D, 0x64, 0x78, 0xBB, 0x48, 0xD7, 0xAC,
+	0x57, 0xC6, 0xFF, 0x00, 0xF0, 0x8A, 0x7D, 0x9F, 0xEC, 0xDF, 0xDA, 0x51, 0xBA, 0xEF, 0xFB, 0x1F,
+	0xDA, 0xDF, 0xCC, 0xF2, 0xF7, 0x67, 0x1E, 0x72, 0xEF, 0xC7, 0x55, 0xAF, 0xA7, 0xA3, 0x9F, 0x64,
+	0xF8, 0x6C, 0xB5, 0x2A, 0x52, 0x4A, 0xA2, 0xA3, 0x86, 0x8A, 0xF7, 0x1D, 0xD4, 0xE1, 0x39, 0xFB,
+	0x5D, 0x5C, 0x6D, 0x75, 0x19, 0x6B, 0x2E, 0xB7, 0xB2, 0x6D, 0x9C, 0x33, 0xC2, 0x62, 0x2A, 0xE3,
+	0xEF, 0x25, 0x7A, 0x6E, 0xB5, 0x59, 0x3D, 0x74, 0xF6, 0x72, 0x84, 0x54, 0x74, 0xBD, 0xED, 0xCC,
+	0x9E, 0x9B, 0xAD, 0xDA, 0xB1, 0xF1, 0xFF, 0x00, 0xED, 0x91, 0xFF, 0x00, 0x05, 0x71, 0xFD, 0xAB,
+	0xB5, 0xEF, 0xF8, 0x27, 0x07, 0xEC, 0x87, 0x6F, 0xE0, 0xBD, 0x6B, 0xC5, 0xD6, 0xBE, 0x33, 0xFD,
+	0xA3, 0x7F, 0xD0, 0x3C, 0x79, 0xE2, 0x0F, 0x86, 0x5E, 0x1E, 0x8A, 0x7F, 0x12, 0xCF, 0x6F, 0x68,
+	0xD0, 0x5A, 0xDF, 0x7F, 0x63, 0xDB, 0x26, 0xC8, 0xE3, 0xBF, 0xB9, 0x79, 0xF7, 0xC5, 0xE5, 0x79,
+	0x7B, 0x1F, 0x02, 0x33, 0x16, 0x41, 0x5D, 0xEF, 0xF8, 0x26, 0x2F, 0xC5, 0xFF, 0x00, 0xDB, 0x6F,
+	0xC1, 0x7F, 0xF0, 0x52, 0x4F, 0x0F, 0xFC, 0x2A, 0xF0, 0x7F, 0x82, 0xFF, 0x00, 0x6D, 0x8D, 0x5F,
+	0xE0, 0x47, 0x8D, 0x3C, 0x2F, 0x79, 0x1F, 0x8B, 0xF5, 0x1F, 0xDB, 0x03, 0xC2, 0x77, 0x12, 0x5C,
+	0xE8, 0x3A, 0xBD, 0xB5, 0xBD, 0xD5, 0xC4, 0x17, 0x36, 0x9A, 0x82, 0x83, 0x1C, 0x31, 0x49, 0xE5,
+	0xC5, 0x6F, 0xE5, 0x16, 0x45, 0x76, 0x9D, 0xB7, 0x2C, 0x8E, 0x21, 0x29, 0xEF, 0xDE, 0x37, 0xFF,
+	0x00, 0x82, 0x13, 0xFC, 0x3D, 0xF8, 0x81, 0xFB, 0x01, 0x7C, 0x23, 0xFD, 0x91, 0xF5, 0x4F, 0xDA,
+	0x03, 0x5C, 0xD3, 0x7C, 0x6B, 0xF0, 0x36, 0x69, 0x2F, 0x7E, 0x1E, 0xFC, 0x5C, 0xF0, 0xEE, 0x92,
+	0xB6, 0xB7, 0x36, 0x37, 0xED, 0x2B, 0xCA, 0x24, 0x6B, 0x56, 0x99, 0xF3, 0x11, 0x7F, 0x25, 0x9A,
+	0x35, 0x99, 0x1C, 0xB5, 0xB4, 0x65, 0x65, 0x4E, 0x41, 0xF5, 0x8F, 0xD9, 0x5B, 0xF6, 0x3A, 0xFD,
+	0xB6, 0x3E, 0x1D, 0xFC, 0x58, 0x8F, 0xE2, 0x9F, 0xED, 0x7D, 0xFF, 0x00, 0x05, 0x3B, 0xF1, 0x27,
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+	0xEE, 0xD2, 0x77, 0x7C, 0xAA, 0x09, 0xA4, 0xAC, 0xA2, 0xDD, 0xD7, 0x93, 0x7E, 0xC2, 0xDF, 0xF0,
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+	0x84, 0xBF, 0x69, 0xFF, 0x00, 0x02, 0xDC, 0x7C, 0x4A, 0xF8, 0x85, 0xF1, 0x14, 0x78, 0xA3, 0xC1,
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+	0xFF, 0x00, 0xFC, 0x14, 0x87, 0xF6, 0xE8, 0xD4, 0x3E, 0x03, 0x78, 0x6B, 0xC4, 0x1E, 0x0E, 0xD2,
+	0xEE, 0xA0, 0xD3, 0xF4, 0xBF, 0xD9, 0xFB, 0x41, 0xBF, 0x87, 0xFE, 0x12, 0x6B, 0x9B, 0xAB, 0x69,
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+	0x38, 0x45, 0xA9, 0x28, 0xA6, 0xE3, 0x2F, 0xAB, 0xC7, 0x99, 0x28, 0x3A, 0x6A, 0x2D, 0x4A, 0xA3,
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+	0xA4, 0xE5, 0x19, 0xCB, 0x4B, 0xB5, 0xCD, 0x1F, 0x6B, 0xEE, 0xDE, 0x5C, 0xD7, 0x56, 0x8A, 0x4F,
+	0xDE, 0xE6, 0x52, 0x8B, 0x69, 0xF3, 0x33, 0xE2, 0x5F, 0x88, 0x5F, 0xF0, 0x70, 0x4F, 0xC6, 0x2F,
+	0x8F, 0x57, 0xFF, 0x00, 0x12, 0x7E, 0x2D, 0x78, 0x43, 0xFE, 0x0A, 0x93, 0xE1, 0xFF, 0x00, 0xD9,
+	0xF5, 0x7C, 0x39, 0xA8, 0x5E, 0xD9, 0xFC, 0x33, 0xF8, 0x34, 0x3E, 0x04, 0xCB, 0xE2, 0x47, 0xF1,
+	0x44, 0x16, 0xE8, 0x64, 0x82, 0xE6, 0xF7, 0x55, 0x7B, 0x59, 0x96, 0xCD, 0xEE, 0x5D, 0x84, 0x27,
+	0x61, 0xDB, 0x18, 0x8F, 0x3E, 0x5A, 0xE3, 0x7C, 0x9F, 0x7F, 0x7C, 0x15, 0xFF, 0x00, 0x82, 0xF9,
+	0x7E, 0xC7, 0x56, 0x3F, 0xB0, 0xF7, 0xC1, 0x9F, 0xDA, 0x97, 0xF6, 0xDF, 0xF1, 0xED, 0xAF, 0xC3,
+	0x4D, 0x63, 0xE2, 0xB6, 0x8F, 0xA8, 0xC9, 0x6F, 0xA4, 0xD8, 0xF8, 0x7F, 0x55, 0xD4, 0x6D, 0xE6,
+	0xBA, 0xD3, 0x6F, 0x1A, 0xCA, 0xF5, 0xE1, 0xFB, 0x2C, 0x17, 0x0D, 0x14, 0x46, 0x55, 0x0E, 0x89,
+	0x2B, 0x17, 0x09, 0x2A, 0xAE, 0xE9, 0x0A, 0xB3, 0x57, 0x07, 0xFB, 0x3E, 0xFF, 0x00, 0xC1, 0x38,
+	0x3F, 0xE0, 0xAC, 0x9F, 0xF0, 0x4C, 0xCD, 0x73, 0xC6, 0xBF, 0x0B, 0xBF, 0xE0, 0x9B, 0x5F, 0x17,
+	0x7E, 0x01, 0xF8, 0x93, 0xE1, 0x17, 0x8A, 0x3C, 0x59, 0x2F, 0x88, 0xB4, 0x7D, 0x13, 0xE3, 0x85,
+	0xBE, 0xB9, 0x1E, 0xA1, 0xA0, 0x4D, 0x29, 0x28, 0xF6, 0xD1, 0x1D, 0x33, 0xE5, 0x99, 0x3C, 0xA4,
+	0xB6, 0x56, 0x95, 0x9C, 0x17, 0x68, 0x43, 0x2C, 0x70, 0x92, 0xDB, 0xFF, 0x00, 0x40, 0x3E, 0x08,
+	0xF8, 0x5B, 0xE2, 0x77, 0x82, 0xFE, 0x14, 0x68, 0x3E, 0x16, 0xF8, 0xCF, 0xF1, 0x42, 0x2F, 0x1B,
+	0x78, 0xB2, 0xC7, 0x4F, 0x58, 0xF5, 0xEF, 0x16, 0x43, 0xA1, 0x45, 0xA6, 0xAE, 0xA7, 0x71, 0x92,
+	0x4C, 0xA2, 0xDA, 0x22, 0x52, 0x11, 0xCE, 0x02, 0x82, 0x40, 0xEB, 0xD4, 0x9A, 0xF3, 0xF3, 0xCC,
+	0x57, 0x0C, 0xFF, 0x00, 0x67, 0x42, 0x9E, 0x12, 0x9C, 0x65, 0x0B, 0xD2, 0x69, 0xC5, 0xA8, 0xD5,
+	0xD2, 0x94, 0x94, 0xD3, 0xBD, 0x29, 0x3B, 0x3A, 0x96, 0x72, 0x73, 0x9C, 0xEE, 0xD2, 0xE4, 0x8A,
+	0x52, 0x7C, 0x9D, 0x78, 0x78, 0x63, 0xBE, 0xBB, 0x37, 0x36, 0xD3, 0xF7, 0xED, 0x7D, 0x61, 0x67,
+	0x34, 0xE2, 0xEC, 0xA4, 0x95, 0xD4, 0x74, 0x49, 0x46, 0x2D, 0x5D, 0xF3, 0x39, 0x35, 0xAF, 0xC1,
+	0xBF, 0xB5, 0x97, 0xFC, 0x15, 0x2F, 0xE2, 0xC7, 0xED, 0x31, 0xF1, 0xEF, 0xE0, 0x1F, 0xEC, 0x59,
+	0xFF, 0x00, 0x04, 0xA5, 0xF8, 0xBB, 0xA1, 0xE9, 0x37, 0x9F, 0x1D, 0xFC, 0x3D, 0x75, 0xE2, 0x7B,
+	0x9F, 0x8B, 0xDA, 0xCF, 0x85, 0x65, 0xBA, 0x3A, 0x16, 0x85, 0x6B, 0x3D, 0xC8, 0x79, 0x6D, 0xAC,
+	0x2F, 0x11, 0x03, 0xDC, 0x30, 0xD3, 0xAF, 0x97, 0x65, 0xCC, 0x61, 0x48, 0xF2, 0x94, 0x18, 0xCC,
+	0xA2, 0x68, 0xA4, 0xF8, 0x0F, 0xFB, 0x58, 0xFE, 0xDE, 0x7F, 0xB1, 0xD7, 0xFC, 0x15, 0x63, 0xC2,
+	0xFF, 0x00, 0xF0, 0x4D, 0x1F, 0xDB, 0x9B, 0xE3, 0xFE, 0x9F, 0xF1, 0xB3, 0x44, 0xF8, 0xB1, 0xE0,
+	0x99, 0xB5, 0xEF, 0x01, 0x7C, 0x44, 0xB5, 0xF0, 0x2D, 0xAF, 0x87, 0xAF, 0x34, 0xFB, 0x98, 0x23,
+	0xB9, 0x69, 0x2D, 0x66, 0xB7, 0xB4, 0x26, 0x16, 0x8B, 0x36, 0x37, 0x2B, 0xD5, 0xE4, 0xCC, 0xB0,
+	0x39, 0x74, 0x52, 0xD1, 0x8F, 0x4F, 0xFF, 0x00, 0x82, 0x8F, 0xFF, 0x00, 0xC1, 0x3B, 0x7E, 0x3B,
+	0xFC, 0x77, 0xFD, 0xA4, 0xFE, 0x15, 0x7F, 0xC1, 0x40, 0x7F, 0x62, 0xBF, 0x8A, 0x3E, 0x17, 0xF0,
+	0xDF, 0xC6, 0x8F, 0x84, 0x76, 0xB3, 0x69, 0xDA, 0x6D, 0x97, 0x8E, 0xAC, 0x26, 0x93, 0x43, 0xD7,
+	0xB4, 0xB9, 0xDD, 0x84, 0x96, 0x97, 0x4F, 0x6A, 0x0C, 0xF0, 0x01, 0x1D, 0xCD, 0xF7, 0xCF, 0x1A,
+	0xB3, 0x3F, 0xDA, 0x36, 0x83, 0x11, 0x02, 0x55, 0xC1, 0xFD, 0x98, 0x7F, 0xE0, 0x9D, 0x3F, 0xB6,
+	0x0F, 0x8C, 0x3F, 0x6F, 0xEB, 0x1F, 0xF8, 0x29, 0x97, 0xFC, 0x14, 0x9B, 0xE2, 0xA7, 0xC3, 0xBB,
+	0xEF, 0x1D, 0x78, 0x4F, 0xC2, 0xB3, 0x78, 0x67, 0xE1, 0xFF, 0x00, 0x83, 0x7E, 0x11, 0xE9, 0xF7,
+	0xAB, 0xA2, 0xE9, 0x76, 0x72, 0x45, 0x22, 0xC9, 0x74, 0xF3, 0xEA, 0x1F, 0xE9, 0x0F, 0x33, 0x9B,
+	0xBB, 0xDC, 0xC6, 0x41, 0x0A, 0x66, 0xDC, 0x24, 0xC6, 0xD8, 0x93, 0xAF, 0x03, 0x89, 0xE0, 0xF8,
+	0xE5, 0xD0, 0x7C, 0xB1, 0x50, 0xE4, 0xAF, 0xED, 0x23, 0x34, 0xA5, 0x59, 0xCD, 0xDF, 0xD8, 0xF2,
+	0xCF, 0x95, 0x6D, 0x78, 0x25, 0x28, 0x28, 0xAB, 0xA9, 0x4A, 0x51, 0xE5, 0xBA, 0x30, 0xC5, 0xD3,
+	0xCD, 0x5D, 0x59, 0x24, 0xDB, 0x95, 0xA9, 0xF2, 0x38, 0xFB, 0xB0, 0x52, 0x4D, 0x7B, 0x47, 0x25,
+	0x77, 0xA7, 0xC4, 0xED, 0x27, 0x2D, 0x2C, 0xA3, 0xEF, 0x58, 0x8F, 0xFE, 0x08, 0xF5, 0xFB, 0x64,
+	0xFE, 0xD2, 0x3F, 0xB5, 0x37, 0x85, 0x7F, 0x69, 0x0D, 0x4B, 0xE3, 0xC7, 0xC4, 0x6F, 0xED, 0xD9,
+	0xBC, 0x03, 0xF1, 0xB3, 0x5C, 0xD0, 0x3C, 0x26, 0xFF, 0x00, 0xD8, 0xF6, 0x76, 0xBF, 0x61, 0xD3,
+	0xAD, 0xD0, 0x18, 0x60, 0xC5, 0xBC, 0x31, 0x89, 0x76, 0x93, 0xF7, 0xE4, 0xDE, 0xE7, 0xBB, 0x1A,
+	0xF8, 0x33, 0xF6, 0x81, 0xFD, 0xA1, 0x7F, 0x6D, 0x3F, 0xDB, 0xD3, 0xFE, 0x0D, 0x93, 0xD6, 0xBF,
+	0x69, 0x9F, 0x8C, 0xDF, 0xB4, 0xFF, 0x00, 0x9F, 0x79, 0xA7, 0xF8, 0xC5, 0xE2, 0xF1, 0xB5, 0x8F,
+	0xFC, 0x21, 0x5A, 0x72, 0xFF, 0x00, 0xC2, 0x4F, 0x64, 0xBA, 0xCD, 0x9C, 0x16, 0x96, 0xDB, 0xE0,
+	0x8E, 0x21, 0x65, 0xE4, 0x4A, 0xC9, 0x37, 0x99, 0x12, 0x16, 0x93, 0xCB, 0xD8, 0xDC, 0x31, 0x35,
+	0xF5, 0xB7, 0xC3, 0xDF, 0xF8, 0x25, 0x4F, 0xFC, 0x14, 0xAB, 0xF6, 0x66, 0xF8, 0xEB, 0xF1, 0xB3,
+	0xC1, 0x7F, 0xB2, 0x0F, 0xED, 0x5F, 0xF0, 0xDF, 0xC3, 0xBF, 0x05, 0xFE, 0x39, 0x78, 0xBE, 0xE3,
+	0x5F, 0xD4, 0xB5, 0xCF, 0x10, 0x68, 0x77, 0xB7, 0xDE, 0x2C, 0xF0, 0xA4, 0xB7, 0x2B, 0x2B, 0x4E,
+	0x34, 0xEB, 0x74, 0xF2, 0xED, 0x25, 0x93, 0x32, 0x2C, 0x22, 0x59, 0xE6, 0x20, 0xA4, 0x51, 0xC8,
+	0x12, 0x37, 0x0C, 0xAD, 0x73, 0xE0, 0x4F, 0xFC, 0x11, 0x57, 0xE2, 0xAF, 0x87, 0x3F, 0xE0, 0x88,
+	0x3E, 0x31, 0xFF, 0x00, 0x82, 0x59, 0xFC, 0x5B, 0xF8, 0x9B, 0xE1, 0xB8, 0x3C, 0x49, 0xE2, 0x0B,
+	0xDB, 0xEB, 0xCD, 0x2F, 0xC4, 0x5A, 0x04, 0x97, 0x37, 0x56, 0x30, 0xCC, 0x2F, 0xE2, 0xBE, 0xB3,
+	0x0E, 0x65, 0x86, 0x19, 0x36, 0x99, 0x2D, 0xD1, 0x25, 0xC2, 0x1D, 0xAA, 0xEE, 0x54, 0x39, 0x00,
+	0x55, 0xC7, 0x15, 0xC3, 0xB8, 0x6A, 0x95, 0x31, 0x54, 0xE5, 0x4F, 0x55, 0x84, 0xE4, 0x4A, 0x2B,
+	0x9A, 0x32, 0xA7, 0xEC, 0xD5, 0x6B, 0x2E, 0x5D, 0x1C, 0x9A, 0x93, 0x6D, 0x3F, 0x7B, 0x56, 0xD9,
+	0x71, 0x86, 0x3A, 0x55, 0xA9, 0x52, 0x97, 0x35, 0x95, 0x4A, 0xCE, 0x4E, 0xFA, 0x38, 0x4F, 0x9D,
+	0xD3, 0xD6, 0xF7, 0x6A, 0x2A, 0xCA, 0xD6, 0xF7, 0x1D, 0x92, 0xE8, 0x7B, 0xDF, 0xFC, 0x12, 0x2B,
+	0xE1, 0x5F, 0xED, 0x23, 0xF0, 0xDB, 0xF6, 0x2F, 0xF0, 0x3D, 0xC7, 0xED, 0x07, 0xFB, 0x54, 0x7F,
+	0xC2, 0xCC, 0xB7, 0xD6, 0xBC, 0x0B, 0xE1, 0xEB, 0xEF, 0x07, 0xDB, 0xFF, 0x00, 0xC2, 0x0F, 0x67,
+	0xA2, 0xFF, 0x00, 0xC2, 0x37, 0xA6, 0xBE, 0x95, 0x6E, 0x63, 0xD3, 0xB7, 0x5B, 0x33, 0x1B, 0xCF,
+	0x2D, 0x4A, 0xAF, 0x9F, 0x26, 0x1D, 0xB6, 0xE4, 0x8E, 0x4D, 0x7D, 0x3F, 0xB5, 0xD8, 0xD7, 0xCF,
+	0xFF, 0x00, 0xF0, 0x4D, 0xBF, 0x86, 0xBF, 0xB7, 0x1F, 0xC1, 0x7F, 0xD9, 0xCF, 0x4A, 0xF8, 0x3D,
+	0xFB, 0x70, 0xEA, 0xDF, 0x0B, 0x6F, 0xAF, 0xBC, 0x25, 0xA5, 0xE9, 0xDA, 0x17, 0x84, 0x6E, 0x3E,
+	0x17, 0xFF, 0x00, 0x68, 0x94, 0x9B, 0x4C, 0xB3, 0xB2, 0x8A, 0xDD, 0x24, 0xBD, 0x6B, 0xD5, 0x4D,
+	0xD7, 0x2C, 0x63, 0xCB, 0x79, 0x51, 0xA4, 0x7D, 0xC0, 0x19, 0xC2, 0xFD, 0x05, 0xFC, 0x6D, 0x5F,
+	0x2B, 0xC5, 0xF8, 0xCA, 0x18, 0xDE, 0x27, 0xC5, 0x56, 0xA1, 0x35, 0x38, 0x4E, 0x72, 0x94, 0x5A,
+	0xB5, 0x9C, 0x5B, 0xBC, 0x6F, 0x64, 0xAF, 0x2B, 0x5B, 0x99, 0xBB, 0xC9, 0xCA, 0xEE, 0x4D, 0xC9,
+	0xB6, 0xF7, 0xC8, 0xA8, 0xD4, 0xC3, 0xE5, 0x34, 0x69, 0x54, 0x4D, 0x4A, 0x31, 0x49, 0xA7, 0xDD,
+	0x68, 0xED, 0xDA, 0x37, 0xBF, 0x2A, 0x56, 0x4A, 0x36, 0x49, 0x25, 0x64, 0x8A, 0x28, 0xA2, 0xBE,
+	0x6C, 0xF5, 0xC5, 0xB3, 0xFF, 0x00, 0x8F, 0x88, 0xF3, 0xFF, 0x00, 0x3D, 0x17, 0xFF, 0x00, 0x42,
+	0xAF, 0x82, 0xBF, 0xE0, 0x8A, 0xBF, 0xF2, 0x96, 0xCF, 0xDB, 0x6B, 0xFE, 0xC7, 0xCB, 0x3F, 0xFD,
+	0x13, 0x5F, 0x7B, 0x5B, 0x7F, 0xAF, 0x8B, 0xFE, 0xBA, 0x2F, 0xFE, 0x85, 0x5F, 0x04, 0x7F, 0xC1,
+	0x14, 0xFF, 0x00, 0xE5, 0x2D, 0x9F, 0xB6, 0xD7, 0xFD, 0x8F, 0x96, 0x7F, 0xFA, 0x26, 0xBF, 0x4A,
+	0xF0, 0xC7, 0xFE, 0x46, 0x55, 0x9F, 0xFD, 0x3B, 0xFD, 0x51, 0xF3, 0x7C, 0x43, 0xFC, 0x18, 0xFA,
+	0xAF, 0xD4, 0xFD, 0x5D, 0xA2, 0x8A, 0x2B, 0xF6, 0x23, 0xE5, 0xC6, 0xB7, 0x51, 0x5F, 0x8C, 0x7F,
+	0xB5, 0x28, 0xFF, 0x00, 0x8E, 0x9E, 0x7E, 0x0B, 0xFF, 0x00, 0xD8, 0x17, 0x58, 0xFF, 0x00, 0xD1,
+	0x75, 0xFB, 0x38, 0xDD, 0x45, 0x7E, 0x30, 0xFE, 0xD4, 0x5F, 0xF2, 0xB3, 0xCF, 0xC1, 0x7F, 0xFB,
+	0x03, 0xEB, 0x1F, 0xFA, 0x2E, 0xBC, 0xAC, 0xF3, 0xFE, 0x44, 0x78, 0xA8, 0xF7, 0xA7, 0x2F, 0xC8,
+	0xDB, 0x0B, 0xFE, 0xF5, 0x0F, 0x53, 0xF4, 0xE2, 0xE7, 0x26, 0xE5, 0x87, 0xFB, 0x4D, 0x47, 0x41,
+	0x45, 0xDF, 0xFC, 0x7C, 0x1F, 0xF7, 0x9A, 0x8A, 0xFE, 0x6A, 0x8D, 0x9C, 0x74, 0x3F, 0x44, 0x87,
+	0xC2, 0x84, 0x66, 0x55, 0xC6, 0xFD, 0xDF, 0xF0, 0x1A, 0xFC, 0xB0, 0xFF, 0x00, 0x82, 0xE2, 0x7E,
+	0xDC, 0xFF, 0x00, 0x1E, 0x7C, 0x39, 0xFB, 0x6D, 0xFC, 0x29, 0xFF, 0x00, 0x82, 0x7B, 0xFC, 0x2F,
+	0xD4, 0x7E, 0x35, 0x69, 0xFE, 0x17, 0xF1, 0x27, 0x85, 0xA6, 0xF1, 0x47, 0x8F, 0x64, 0xFD, 0x9B,
+	0xF4, 0x81, 0x75, 0xE3, 0x8D, 0x42, 0x04, 0x92, 0xE4, 0x41, 0x6F, 0xA7, 0xB1, 0x21, 0xA0, 0x44,
+	0x7B, 0x22, 0xF3, 0x3A, 0x10, 0x7C, 0xA7, 0x6D, 0xDB, 0xD5, 0x5A, 0x37, 0xFD, 0x4F, 0x66, 0xC5,
+	0x7C, 0x9F, 0xFF, 0x00, 0x05, 0x04, 0xFF, 0x00, 0x82, 0x5A, 0x58, 0xFE, 0xD8, 0xFF, 0x00, 0x17,
+	0x3C, 0x05, 0xFB, 0x55, 0xFC, 0x1D, 0xFD, 0xA0, 0xF5, 0xAF, 0x84, 0x3F, 0x1A, 0x3E, 0x19, 0xE6,
+	0x2F, 0x09, 0xF8, 0xFB, 0x49, 0xD1, 0xE0, 0xD4, 0xE1, 0x36, 0xAD, 0x26, 0xF6, 0xB7, 0xBB, 0xB2,
+	0x9D, 0x91, 0x6E, 0x63, 0x01, 0xE7, 0x55, 0x5F, 0x31, 0x50, 0x8B, 0x99, 0x44, 0x8B, 0x2A, 0x36,
+	0xCA, 0xF6, 0xB8, 0x77, 0x11, 0x96, 0x61, 0x73, 0x7A, 0x55, 0x71, 0xC9, 0xFB, 0x35, 0x7B, 0xBB,
+	0x5F, 0x95, 0xB8, 0xB5, 0x19, 0x72, 0xF5, 0xE5, 0x95, 0x9D, 0xBC, 0xBA, 0xEC, 0xF9, 0xF1, 0x91,
+	0xAD, 0x53, 0x05, 0x56, 0x14, 0x7E, 0x36, 0xB4, 0xBB, 0x6B, 0xAA, 0x6D, 0x5D, 0x6A, 0xAE, 0xAE,
+	0xAF, 0xD2, 0xFF, 0x00, 0x35, 0xF2, 0xE7, 0xFC, 0x12, 0x5F, 0xF6, 0x84, 0xFD, 0xB2, 0x3C, 0x17,
+	0xF1, 0xCF, 0xE3, 0x47, 0xC3, 0x1F, 0x8B, 0xF6, 0xFF, 0x00, 0xB4, 0xC6, 0x93, 0xFB, 0x3F, 0xE9,
+	0xFF, 0x00, 0x0F, 0x66, 0xF1, 0x57, 0x84, 0x7E, 0x23, 0xFE, 0xD6, 0xDE, 0x11, 0x9A, 0x2D, 0x73,
+	0xC3, 0xF7, 0xD6, 0xEB, 0x6F, 0x1D, 0xD4, 0x52, 0x5E, 0xB8, 0x30, 0xDC, 0xC2, 0x56, 0x49, 0xAE,
+	0x04, 0x45, 0xF0, 0xA9, 0x69, 0x95, 0x44, 0xCC, 0xED, 0x27, 0xC5, 0x5F, 0xB5, 0x17, 0xED, 0xC1,
+	0xF1, 0x33, 0xC0, 0x1F, 0x05, 0x66, 0xFD, 0xB0, 0xBF, 0x64, 0xBF, 0xDB, 0x23, 0xFE, 0x0A, 0x05,
+	0xE2, 0xDF, 0x10, 0x59, 0xF8, 0xA2, 0x29, 0x22, 0xF8, 0xAD, 0xE2, 0xED, 0x16, 0x2B, 0x2F, 0x84,
+	0xFA, 0xEC, 0xC2, 0xEC, 0xC3, 0x73, 0x25, 0xB5, 0x86, 0x3C, 0xBB, 0x6B, 0x79, 0x25, 0x0E, 0x21,
+	0xB3, 0x95, 0x19, 0x63, 0x38, 0x85, 0xE3, 0x04, 0x10, 0x3F, 0x62, 0xBE, 0x0A, 0xFE, 0xC1, 0x5F,
+	0x1F, 0x1B, 0xC1, 0x1E, 0x3E, 0xF0, 0xB7, 0xED, 0xD9, 0xFB, 0x7D, 0x78, 0xAF, 0xE3, 0x7C, 0x9E,
+	0x3E, 0xF0, 0x8D, 0xC7, 0x85, 0x6E, 0x2D, 0xE1, 0xF0, 0xBD, 0x87, 0x86, 0x74, 0xBB, 0x0D, 0x2A,
+	0x64, 0x91, 0x5C, 0xC5, 0x61, 0x66, 0x1D, 0x0D, 0xEB, 0x19, 0xE6, 0x0D, 0x76, 0xCC, 0x58, 0xA7,
+	0x95, 0x1E, 0xD0, 0x22, 0x52, 0x7E, 0x55, 0xF1, 0x5F, 0xFC, 0x1B, 0xB3, 0xFB, 0x41, 0x78, 0xDB,
+	0xF6, 0x50, 0x97, 0xF6, 0x14, 0xF1, 0x2F, 0xFC, 0x15, 0xA7, 0xC5, 0x17, 0x1F, 0x08, 0x74, 0x79,
+	0x9A, 0xE3, 0xC0, 0x3E, 0x0F, 0x5F, 0x85, 0xBA, 0x7C, 0x67, 0x4C, 0x98, 0x5F, 0x1B, 0x88, 0xFE,
+	0xDF, 0x74, 0x97, 0x02, 0xE3, 0x53, 0x89, 0x23, 0x96, 0xE1, 0x44, 0x25, 0xE1, 0x41, 0x2B, 0x43,
+	0x2A, 0xED, 0x58, 0x16, 0x13, 0xF6, 0x78, 0x7C, 0xEB, 0x22, 0xFA, 0xEF, 0xB6, 0xAD, 0x52, 0x0A,
+	0x49, 0x51, 0x57, 0x50, 0x97, 0x2C, 0x94, 0x1C, 0xB9, 0xAE, 0xDD, 0x3E, 0x77, 0x24, 0xB9, 0x63,
+	0x67, 0x18, 0xC2, 0x7F, 0x69, 0xBE, 0x54, 0xCF, 0x2E, 0x58, 0x5C, 0x47, 0xD5, 0xFD, 0x9C, 0x20,
+	0xEC, 0xDC, 0xEF, 0x76, 0xB4, 0xBC, 0x62, 0xA2, 0xD2, 0x52, 0xE5, 0x4B, 0x9B, 0x99, 0xBD, 0x5B,
+	0x8E, 0xF1, 0x8A, 0x72, 0x92, 0x74, 0xBF, 0xE0, 0xB1, 0xDF, 0x1F, 0x3F, 0x6B, 0xCB, 0x1D, 0x77,
+	0xE0, 0xDF, 0xC5, 0x1F, 0x11, 0x6A, 0xDF, 0x1F, 0x3C, 0x33, 0xFB, 0x33, 0xDF, 0x7C, 0x3D, 0x93,
+	0x5F, 0xF8, 0x95, 0xAD, 0xFE, 0xCB, 0xAC, 0x90, 0x78, 0x87, 0x4E, 0xD6, 0xBE, 0xCD, 0x2B, 0xC7,
+	0xF6, 0x8B, 0xB9, 0x3F, 0xE3, 0xDE, 0xC1, 0x04, 0xB6, 0xE7, 0xF7, 0x8C, 0xB1, 0x38, 0xF3, 0x89,
+	0xDD, 0x24, 0x71, 0x6C, 0xC5, 0xFD, 0xA4, 0xFF, 0x00, 0xE0, 0xA5, 0xDA, 0xA7, 0xEC, 0x97, 0xFF,
+	0x00, 0x04, 0x54, 0x8F, 0xE3, 0x1F, 0xEC, 0x23, 0xFB, 0x73, 0x78, 0x83, 0xE3, 0x8D, 0xD7, 0x88,
+	0xBE, 0x28, 0x7F, 0xC2, 0x21, 0xE0, 0xBF, 0x88, 0x9E, 0x35, 0xD2, 0xC5, 0xC6, 0xBD, 0xA1, 0x2C,
+	0xB1, 0xC9, 0x70, 0xF6, 0xB7, 0x8B, 0x3C, 0x48, 0xF7, 0x57, 0x91, 0x24, 0x2F, 0xB2, 0x4B, 0x88,
+	0x94, 0xBA, 0xDD, 0x42, 0xC1, 0x1A, 0x31, 0x19, 0x6F, 0xB1, 0xBE, 0x3B, 0x7E, 0xC3, 0x9F, 0xB6,
+	0x7E, 0xB9, 0xA8, 0x78, 0x3F, 0x59, 0xFD, 0x90, 0x3F, 0xE0, 0xA6, 0xFA, 0xF7, 0xC2, 0x19, 0x34,
+	0x1F, 0x05, 0x59, 0x78, 0x77, 0x5E, 0xD2, 0xEE, 0x3E, 0x1D, 0x69, 0xFE, 0x24, 0xD2, 0x75, 0x51,
+	0x68, 0x49, 0x86, 0xF2, 0x2B, 0x3B, 0xE9, 0x02, 0xD9, 0xDC, 0x13, 0x24, 0x8B, 0x2B, 0xAB, 0x39,
+	0x95, 0x16, 0x04, 0x38, 0x10, 0xE5, 0xBC, 0xFF, 0x00, 0x42, 0xFF, 0x00, 0x82, 0x06, 0x7E, 0xCB,
+	0x2D, 0xFF, 0x00, 0x04, 0xF4, 0xD7, 0x3F, 0x60, 0xDF, 0x88, 0xBE, 0x3B, 0xF1, 0x37, 0x88, 0x26,
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+	0xCD, 0xBB, 0x1F, 0xF6, 0x95, 0x77, 0x2D, 0x0D, 0x0C, 0xDD, 0x7E, 0xCD, 0x27, 0xFD, 0xF3, 0x5F,
+	0x80, 0x73, 0x5C, 0xFB, 0x88, 0xCE, 0x2E, 0x2A, 0xCC, 0x28, 0xA5, 0x10, 0xCE, 0x9C, 0xF9, 0x32,
+	0x7F, 0xDF, 0x34, 0x9E, 0x4C, 0xDF, 0xF3, 0xEB, 0x27, 0xFD, 0xF1, 0x46, 0xA5, 0x73, 0x47, 0xB8,
+	0x51, 0x47, 0x93, 0x37, 0xFC, 0xFA, 0xC9, 0xFF, 0x00, 0x7C, 0x52, 0xF9, 0x33, 0xFF, 0x00, 0xCF,
+	0x19, 0x3F, 0xEF, 0x9A, 0x39, 0x7B, 0xA0, 0xE6, 0x8F, 0x71, 0x8C, 0xBF, 0xDC, 0xEB, 0x46, 0xE9,
+	0x8C, 0x80, 0xEC, 0x53, 0x9F, 0xBC, 0x3D, 0x2A, 0x4F, 0x22, 0x5E, 0x9E, 0x43, 0x7F, 0xDF, 0x34,
+	0x9E, 0x55, 0xC7, 0xFC, 0xFA, 0x37, 0xFD, 0xF3, 0x46, 0xAB, 0x64, 0x85, 0x78, 0x8C, 0x93, 0xCD,
+	0x55, 0x63, 0x19, 0x56, 0x3F, 0xC3, 0xBA, 0x9A, 0x7E, 0xE1, 0x65, 0x7F, 0x99, 0xBB, 0x35, 0x48,
+	0x62, 0x98, 0x7D, 0xEB, 0x79, 0x3F, 0xEF, 0x9A, 0x3C, 0x99, 0x7F, 0xE7, 0x83, 0xFF, 0x00, 0xDF,
+	0x34, 0xD7, 0xBB, 0xB3, 0xFD, 0x44, 0xDC, 0x7B, 0x91, 0xAA, 0x38, 0xDB, 0x96, 0x3F, 0xED, 0x7C,
+	0xD4, 0xA2, 0x37, 0xDF, 0xB9, 0xA5, 0xFA, 0x00, 0x7A, 0xD3, 0xDA, 0x09, 0x7F, 0xE7, 0xDE, 0x4F,
+	0xFB, 0xE6, 0x8F, 0x2A, 0x7F, 0xF9, 0xF4, 0x7F, 0xFB, 0xE6, 0x9F, 0x4B, 0x5A, 0xFF, 0x00, 0x20,
+	0xE6, 0x5D, 0xC6, 0xA1, 0x90, 0x23, 0x44, 0x4E, 0x43, 0x7F, 0x76, 0x95, 0x57, 0x6D, 0x3F, 0xCA,
+	0xB9, 0xEF, 0x6A, 0xFF, 0x00, 0xF7, 0xCD, 0x1E, 0x4C, 0xFF, 0x00, 0xF3, 0xC1, 0xFF, 0x00, 0xEF,
+	0x9A, 0x9D, 0x36, 0x8A, 0xB0, 0x73, 0x44, 0x6D, 0x14, 0x79, 0x33, 0x7F, 0xCF, 0xAC, 0x9F, 0xF7,
+	0xC5, 0x2F, 0x97, 0x3F, 0xFC, 0xFB, 0x49, 0xFF, 0x00, 0x7C, 0xD1, 0x66, 0x57, 0x34, 0x7B, 0x89,
+	0x47, 0xF7, 0xB8, 0xFB, 0xB4, 0x79, 0x33, 0x7F, 0xCF, 0xAC, 0x9F, 0xF7, 0xC5, 0x0D, 0x1D, 0xCE,
+	0xD5, 0xDB, 0x6F, 0x23, 0x1F, 0xE2, 0xF9, 0x7F, 0x86, 0x8F, 0x90, 0x73, 0xC7, 0xB8, 0x37, 0x0E,
+	0xA9, 0xFD, 0xEF, 0xE2, 0xAF, 0x07, 0xFF, 0x00, 0x82, 0x9C, 0xEE, 0x1F, 0xB0, 0xF7, 0x8E, 0x93,
+	0x6B, 0x37, 0xFC, 0x4B, 0x5B, 0xFF, 0x00, 0x41, 0x6A, 0xF7, 0x87, 0x8E, 0xEA, 0x35, 0xF9, 0xED,
+	0xE4, 0x78, 0xFF, 0x00, 0xBD, 0xB7, 0xEE, 0xB5, 0x7C, 0x93, 0xFF, 0x00, 0x05, 0xB6, 0xFD, 0xA2,
+	0xBC, 0x1B, 0xFB, 0x36, 0xFE, 0xC0, 0x7E, 0x2A, 0xD5, 0x7C, 0x4F, 0xAD, 0xDA, 0xBE, 0xA7, 0xA9,
+	0x79, 0x76, 0x7A, 0x6E, 0x8E, 0xD3, 0x2F, 0x9D, 0x71, 0xE7, 0x37, 0x97, 0xF7, 0x7E, 0xF7, 0xF1,
+	0x57, 0xA1, 0x95, 0x61, 0xEA, 0xE2, 0x73, 0x2A, 0x54, 0xA0, 0x9D, 0xDC, 0x97, 0xE0, 0xFB, 0x9C,
+	0x78, 0xCA, 0x90, 0x8D, 0x09, 0x5D, 0xF4, 0x65, 0x8F, 0xF8, 0x35, 0xA5, 0xB6, 0xFF, 0x00, 0xC1,
+	0x1B, 0xBC, 0x07, 0xFC, 0x5F, 0xF1, 0x3B, 0xD6, 0x3F, 0xF4, 0xA9, 0xAB, 0xF4, 0x4D, 0x3E, 0xF5,
+	0x7C, 0x2D, 0xFF, 0x00, 0x06, 0xE6, 0xFC, 0x23, 0xF1, 0x47, 0xC1, 0x8F, 0xF8, 0x24, 0xFF, 0x00,
+	0x80, 0x7C, 0x17, 0xE3, 0x2D, 0x3E, 0x6B, 0x3D, 0x43, 0xED, 0x97, 0xD7, 0x8D, 0x0C, 0xCB, 0xB5,
+	0x95, 0x66, 0x99, 0xA4, 0x5F, 0xFC, 0x75, 0xAB, 0xEE, 0x98, 0x95, 0x97, 0x82, 0xFB, 0xAB, 0xFA,
+	0x6A, 0xED, 0x3B, 0x33, 0xE0, 0x47, 0xD6, 0x3F, 0x8F, 0x78, 0xF0, 0x1E, 0xB4, 0xA3, 0xFE, 0x81,
+	0x37, 0x5F, 0xFA, 0x2D, 0xAB, 0x62, 0xA8, 0xF8, 0x8A, 0xC0, 0xEA, 0xFE, 0x1D, 0xD4, 0x34, 0xA5,
+	0x1C, 0xDD, 0x59, 0xCD, 0x17, 0xFD, 0xF4, 0xA5, 0x6A, 0x80, 0xFC, 0x24, 0xFF, 0x00, 0x83, 0x5C,
+	0x83, 0xAF, 0xED, 0x15, 0xFB, 0x4C, 0x7F, 0x12, 0xFD, 0xA3, 0xEF, 0x2F, 0xFD, 0x7C, 0x35, 0x7E,
+	0xBF, 0xFF, 0x00, 0x12, 0xA5, 0x7E, 0x46, 0xFF, 0x00, 0xC1, 0x1F, 0xCF, 0x84, 0xBF, 0x60, 0x9F,
+	0xF8, 0x2B, 0x7F, 0xED, 0x09, 0xFB, 0x1F, 0xFC, 0x45, 0xF1, 0x0B, 0x69, 0xB7, 0x3E, 0x26, 0x82,
+	0xD5, 0xBC, 0x33, 0x36, 0xA1, 0xFB, 0xA8, 0xEE, 0xA4, 0x91, 0x9A, 0x46, 0x5D, 0xCD, 0xFE, 0xF5,
+	0x7E, 0xBA, 0x2D, 0xBD, 0xCA, 0x3B, 0x2A, 0x23, 0x32, 0x2F, 0x1E, 0x64, 0x7F, 0x32, 0xB7, 0xFB,
+	0xB5, 0xF8, 0x0F, 0x1B, 0x51, 0xAD, 0x47, 0x89, 0x2A, 0xA9, 0x2F, 0x8B, 0xDE, 0x5E, 0x96, 0xFF,
+	0x00, 0x80, 0x7D, 0x86, 0x4B, 0x38, 0xFD, 0x5E, 0xD7, 0x0A, 0x29, 0xDE, 0x5D, 0xC7, 0xFC, 0xFB,
+	0x3F, 0xFD, 0xF3, 0x48, 0xB1, 0x5C, 0x63, 0x9B, 0x79, 0x3F, 0xEF, 0x9A, 0xF9, 0x1E, 0xD2, 0x8E,
+	0xA9, 0x9E, 0xD7, 0x34, 0x7B, 0x89, 0x45, 0x1E, 0x4C, 0xDF, 0xF3, 0xEB, 0x27, 0xFD, 0xF1, 0x47,
+	0x93, 0x37, 0xFC, 0xFA, 0xC9, 0xFF, 0x00, 0x7C, 0x53, 0x5A, 0x74, 0x0E, 0x68, 0xF7, 0x14, 0x7C,
+	0xC9, 0x8F, 0xE2, 0xFE, 0x1A, 0x44, 0x54, 0xDD, 0xBD, 0xFE, 0xF5, 0x06, 0x0B, 0x83, 0xFF, 0x00,
+	0x2C, 0x24, 0xFF, 0x00, 0xBE, 0x68, 0xF2, 0x6E, 0x7F, 0xE7, 0x8C, 0x9F, 0xF7, 0xCD, 0x28, 0xC7,
+	0x97, 0x62, 0x7D, 0xDE, 0xE4, 0x7B, 0x72, 0xCD, 0xBF, 0xF8, 0xBF, 0xBB, 0x42, 0xAC, 0x8D, 0x13,
+	0x43, 0x30, 0x5F, 0xF6, 0x76, 0xD4, 0x9F, 0x66, 0xB8, 0xFF, 0x00, 0x9E, 0x12, 0x7F, 0xDF, 0x34,
+	0x2C, 0x17, 0x0B, 0xFF, 0x00, 0x2E, 0xF2, 0x7F, 0xDF, 0x35, 0x51, 0x9C, 0xB5, 0x5A, 0x07, 0xBB,
+	0xDC, 0x8C, 0xDB, 0xFC, 0xAB, 0xB1, 0xDB, 0xFB, 0xB5, 0x22, 0xC7, 0xE5, 0xB6, 0xF4, 0xA7, 0x0B,
+	0x7B, 0xAE, 0xBE, 0x54, 0x8B, 0xFF, 0x00, 0x00, 0xA3, 0xEC, 0xD7, 0xBF, 0xDC, 0x93, 0xFE, 0xF9,
+	0xA9, 0x7C, 0xAD, 0xDD, 0xBF, 0x2D, 0xB6, 0xF4, 0x12, 0xE5, 0xEE, 0x46, 0xDB, 0xDA, 0x45, 0x77,
+	0x4D, 0xAB, 0x4A, 0xCD, 0xB5, 0x9B, 0x62, 0xFC, 0x9F, 0xDD, 0x6A, 0x71, 0xB7, 0xBC, 0x1F, 0xF2,
+	0xC2, 0x43, 0xFF, 0x00, 0x01, 0xA4, 0xFB, 0x3D, 0xE7, 0xFC, 0xFB, 0xC9, 0xFF, 0x00, 0x7C, 0xD5,
+	0x5E, 0x4D, 0xE8, 0xF4, 0xFB, 0x87, 0xEE, 0xF7, 0x23, 0x8F, 0xE5, 0x66, 0xD9, 0xF7, 0x6A, 0x4A,
+	0x51, 0x6F, 0x72, 0xAD, 0xF3, 0xDB, 0x49, 0xFF, 0x00, 0x7C, 0xD2, 0x79, 0x33, 0x7F, 0xCF, 0xAC,
+	0x9F, 0xF7, 0xC5, 0x4F, 0x2B, 0x2B, 0x9A, 0x3D, 0xC2, 0x8A, 0x3C, 0x99, 0xBF, 0xE7, 0xD6, 0x4F,
+	0xFB, 0xE2, 0x93, 0xC8, 0xBD, 0xFF, 0x00, 0x9E, 0x4F, 0xFF, 0x00, 0x7C, 0xD3, 0xB0, 0x73, 0x47,
+	0xB8, 0xB4, 0x6E, 0xFF, 0x00, 0xBE, 0x68, 0xFB, 0x3D, 0xCF, 0x4F, 0x2E, 0x4F, 0xFB, 0xE6, 0x91,
+	0xA1, 0xB9, 0x8E, 0x35, 0xFD, 0xD4, 0x8D, 0xFE, 0xCE, 0xDA, 0x4E, 0xC0, 0xE5, 0x1E, 0x8C, 0xE5,
+	0xBE, 0x35, 0xB2, 0x3F, 0xC2, 0x3D, 0x7D, 0xF7, 0xAA, 0xAF, 0xF6, 0x7C, 0x9F, 0x33, 0x7F, 0xBA,
+	0xD5, 0xF2, 0x5F, 0xFC, 0x1A, 0x93, 0xC7, 0xEC, 0x2B, 0xE3, 0xE6, 0xCE, 0x73, 0xF1, 0x9B, 0x5C,
+	0xFF, 0x00, 0xD1, 0xD5, 0xEC, 0xDF, 0xF0, 0x52, 0x8F, 0xDA, 0x8B, 0xE1, 0xC7, 0xEC, 0x7F, 0xFB,
+	0x1B, 0xF8, 0xC3, 0xE2, 0xAF, 0x8F, 0x75, 0x3B, 0x5F, 0xB5, 0x5B, 0xE9, 0xAD, 0xFD, 0x97, 0xA3,
+	0xCD, 0x2A, 0xEE, 0xBC, 0x91, 0xBE, 0x5D, 0xBB, 0x7E, 0xF7, 0xF1, 0x57, 0x9D, 0xFF, 0x00, 0xC1,
+	0xB0, 0x3F, 0x08, 0x7E, 0x24, 0x7C, 0x30, 0xFF, 0x00, 0x82, 0x78, 0x5E, 0x6B, 0xDF, 0x12, 0xF4,
+	0x06, 0xD3, 0x2E, 0xBC, 0x61, 0xE3, 0xCD, 0x43, 0x5E, 0xB3, 0xB5, 0x6E, 0xD6, 0xB7, 0x0C, 0xB2,
+	0x47, 0xFF, 0x00, 0xA1, 0x57, 0xEB, 0xDE, 0x1A, 0x51, 0xAD, 0x4F, 0x07, 0x89, 0xA9, 0x25, 0xEE,
+	0xCE, 0x51, 0xB7, 0xC9, 0x2B, 0x9F, 0x23, 0x9F, 0x54, 0x8C, 0xAB, 0xC5, 0x2E, 0x87, 0xE9, 0x03,
+	0x3F, 0xCB, 0xD3, 0x34, 0x33, 0x6D, 0x6D, 0x94, 0xD6, 0x6C, 0x7D, 0xCF, 0xBC, 0xBF, 0x7A, 0x8F,
+	0x9F, 0x6E, 0xFF, 0x00, 0xEF, 0x57, 0xE9, 0x89, 0xEE, 0x78, 0x63, 0x9F, 0x95, 0x3C, 0xFD, 0xE5,
+	0xAF, 0xC2, 0x1F, 0xF8, 0x36, 0x8D, 0x5D, 0x7F, 0x6A, 0xDF, 0xDA, 0x35, 0xDE, 0x16, 0x55, 0xFF,
+	0x00, 0x84, 0xE3, 0x5C, 0xF9, 0xBF, 0xED, 0xED, 0xAB, 0xF7, 0x72, 0x4D, 0xAD, 0x94, 0xCE, 0xDF,
+	0x97, 0xE5, 0x6A, 0xFC, 0x1B, 0xFF, 0x00, 0x82, 0x5E, 0xA4, 0x3F, 0xF0, 0x4B, 0xCF, 0xF8, 0x2D,
+	0x27, 0xC6, 0x0F, 0xD9, 0x4B, 0xF6, 0x98, 0xF1, 0x37, 0xF6, 0x65, 0xAF, 0xC4, 0x08, 0x6E, 0x35,
+	0x9F, 0x09, 0xDE, 0x5D, 0x37, 0xEE, 0xAE, 0x2E, 0x2F, 0x2E, 0xB7, 0x2C, 0x7B, 0xBE, 0xEA, 0xFC,
+	0xB5, 0xF3, 0x9C, 0x57, 0x85, 0xA9, 0x8A, 0xE1, 0xDA, 0xF0, 0x8F, 0x93, 0xFB, 0x8E, 0x9C, 0x1C,
+	0xD4, 0x31, 0x29, 0xB3, 0xF5, 0xF9, 0x9B, 0xE5, 0xF9, 0x3E, 0x65, 0xA9, 0x28, 0x92, 0xCE, 0xEA,
+	0x16, 0xC6, 0xC5, 0x78, 0xDB, 0xEE, 0xC9, 0x6E, 0xDB, 0x95, 0xBF, 0xDA, 0xDD, 0x43, 0x45, 0x36,
+	0x4A, 0xFD, 0x9E, 0x4D, 0xCB, 0xFE, 0xCD, 0x7F, 0x3C, 0xD9, 0x6D, 0xAF, 0xF4, 0x8F, 0xBF, 0x8C,
+	0xE2, 0xD5, 0xD3, 0x0A, 0x43, 0x9F, 0xE1, 0xFB, 0xD4, 0xBE, 0x55, 0xCF, 0xFC, 0xF0, 0x93, 0xFE,
+	0xF8, 0xA1, 0x62, 0xB9, 0x3C, 0x88, 0xA4, 0xFF, 0x00, 0xBE, 0x68, 0xB3, 0xDC, 0xAE, 0x68, 0xF7,
+	0x05, 0xF9, 0x4F, 0xC9, 0xFC, 0x5F, 0x7B, 0x75, 0x35, 0x43, 0x29, 0xDA, 0xC5, 0xA9, 0xDE, 0x4C,
+	0xDF, 0xF3, 0xED, 0x27, 0xFD, 0xF1, 0x4E, 0xF2, 0xEE, 0x3F, 0xE7, 0xD9, 0xFF, 0x00, 0xEF, 0x9A,
+	0x49, 0xCA, 0x29, 0x24, 0x85, 0xCD, 0x1E, 0x84, 0x68, 0xCE, 0x65, 0xF9, 0xD7, 0xF7, 0x7E, 0xA3,
+	0xAD, 0x03, 0xCC, 0xDA, 0x41, 0x6E, 0x77, 0xFF, 0x00, 0xE3, 0xB5, 0x27, 0x91, 0x71, 0xFF, 0x00,
+	0x3E, 0x8F, 0xFF, 0x00, 0x7C, 0x51, 0xE4, 0xCF, 0x8C, 0x79, 0x12, 0x7F, 0xDF, 0x34, 0xE3, 0x7E,
+	0xA2, 0xE6, 0x4F, 0xAF, 0xE2, 0x46, 0xED, 0xF2, 0xE2, 0x27, 0xF9, 0xB1, 0x9F, 0x9A, 0x81, 0x22,
+	0x63, 0x71, 0x6E, 0x7F, 0xBB, 0xDA, 0x97, 0xEC, 0xB2, 0x7F, 0xCF, 0x16, 0xFF, 0x00, 0xBE, 0x68,
+	0xFB, 0x2C, 0x9F, 0xF3, 0xC5, 0xBF, 0xEF, 0x9A, 0x5C, 0xC9, 0xFF, 0x00, 0xC3, 0x06, 0x9D, 0xFF,
+	0x00, 0x11, 0x8F, 0xE6, 0x9F, 0xBA, 0xF8, 0xDB, 0xE8, 0x3E, 0xF5, 0x3E, 0x2E, 0x59, 0xBC, 0xD6,
+	0xFE, 0x1C, 0xAE, 0xDA, 0x7F, 0x97, 0x73, 0xFF, 0x00, 0x3E, 0xAD, 0xFF, 0x00, 0x7C, 0xD1, 0xE5,
+	0x4D, 0xFF, 0x00, 0x3E, 0xD2, 0x7E, 0x55, 0x51, 0xD3, 0x74, 0xB7, 0xBE, 0xFF, 0x00, 0xD6, 0x81,
+	0xCC, 0xBB, 0xFE, 0x24, 0x7F, 0x36, 0xFC, 0xEE, 0xF9, 0x76, 0xFA, 0x50, 0xA2, 0x41, 0x1B, 0x06,
+	0x6D, 0xCF, 0xD2, 0x3F, 0xFE, 0xBD, 0x49, 0xE5, 0x4D, 0xFF, 0x00, 0x3E, 0xD2, 0x7F, 0xDF, 0x34,
+	0x79, 0x52, 0xE3, 0xFE, 0x3D, 0xE4, 0xFF, 0x00, 0xBE, 0x6A, 0x79, 0x65, 0x2B, 0xA0, 0xE6, 0x5D,
+	0xC8, 0xF6, 0x23, 0xC7, 0xF3, 0x96, 0xDD, 0x4A, 0xAB, 0xB6, 0x9F, 0xE5, 0x4D, 0xFF, 0x00, 0x3E,
+	0xD2, 0x7F, 0xDF, 0x34, 0xDF, 0x2E, 0x6F, 0xF9, 0xE3, 0x27, 0xFD, 0xF3, 0x46, 0xAD, 0x2B, 0x84,
+	0x64, 0x14, 0x52, 0xF9, 0x37, 0x1F, 0xF3, 0xC2, 0x4F, 0xFB, 0xE6, 0x97, 0xCA, 0xB8, 0xFF, 0x00,
+	0x9F, 0x67, 0xFF, 0x00, 0xBE, 0x6A, 0x92, 0x6A, 0x49, 0x87, 0x34, 0x7B, 0x8D, 0x5F, 0x95, 0xF7,
+	0xD7, 0x39, 0xF1, 0x79, 0xB6, 0xFC, 0x23, 0xF1, 0x62, 0x3F, 0x01, 0x74, 0x39, 0x9B, 0x77, 0xF7,
+	0xBE, 0x5A, 0xE9, 0x56, 0xDA, 0xF2, 0x46, 0xD8, 0xB6, 0x8C, 0x43, 0x7D, 0xED, 0xCB, 0x5E, 0x3F,
+	0xFF, 0x00, 0x05, 0x02, 0xFD, 0xA0, 0x3C, 0x15, 0xFB, 0x2B, 0xFE, 0xC6, 0x1F, 0x10, 0xFE, 0x26,
+	0xF8, 0xCB, 0x57, 0xB3, 0x4B, 0x9B, 0x5F, 0x0C, 0xDC, 0x36, 0x99, 0xA7, 0xDD, 0x5C, 0x2A, 0xB5,
+	0xD4, 0xCA, 0xBF, 0x2C, 0x7B, 0x6B, 0x7C, 0x1D, 0x3A, 0xD5, 0xB1, 0x10, 0x8C, 0x16, 0xAE, 0x4B,
+	0xEF, 0xBF, 0x63, 0x9F, 0x15, 0x56, 0x31, 0xA1, 0x26, 0xD9, 0xF2, 0xFF, 0x00, 0xFC, 0x1A, 0x8F,
+	0xCF, 0xC2, 0x5F, 0xDA, 0x21, 0xFF, 0x00, 0xBD, 0xF1, 0xCA, 0xF3, 0xFF, 0x00, 0x45, 0xD7, 0xEB,
+	0x2A, 0xB6, 0xEE, 0xD5, 0xF9, 0x61, 0xFF, 0x00, 0x06, 0xA4, 0x7C, 0x30, 0xF8, 0xA5, 0xE1, 0x6F,
+	0xD8, 0xD3, 0xC7, 0x5F, 0x17, 0xBE, 0x28, 0x78, 0x73, 0xFB, 0x2F, 0xFE, 0x16, 0x77, 0x8F, 0x9B,
+	0xC4, 0x7A, 0x4D, 0xBA, 0xFD, 0xDF, 0xB3, 0xCD, 0x1F, 0x1B, 0x6B, 0xF5, 0x3D, 0x47, 0xCB, 0x5F,
+	0xD4, 0x14, 0xE3, 0x2A, 0x74, 0xE3, 0x19, 0x6E, 0x92, 0xFC, 0x8F, 0x81, 0x93, 0xBC, 0x9B, 0x40,
+	0xC7, 0x03, 0x34, 0x99, 0x1E, 0x65, 0x2B, 0xFD, 0xDA, 0x84, 0x48, 0xE1, 0xFE, 0xEF, 0xCD, 0xFF,
+	0x00, 0xB2, 0xD3, 0xFB, 0x44, 0x9F, 0x87, 0x9F, 0xB1, 0xD3, 0x79, 0xDF, 0xF0, 0x73, 0xE7, 0x8E,
+	0x7C, 0x97, 0xDC, 0xAB, 0xE1, 0x5D, 0x63, 0x73, 0x2F, 0xFB, 0xD5, 0xFA, 0xC1, 0x1B, 0x2A, 0x33,
+	0x26, 0xED, 0xBB, 0x6B, 0xF2, 0x9F, 0xF6, 0x98, 0xD6, 0xBC, 0x07, 0xFF, 0x00, 0x04, 0xBD, 0xFF,
+	0x00, 0x83, 0x89, 0x7C, 0x33, 0xF1, 0xEF, 0xE2, 0xA5, 0xDD, 0xC5, 0x97, 0x84, 0xFE, 0x25, 0x78,
+	0x3E, 0xEA, 0xD1, 0x75, 0x25, 0xB7, 0x66, 0x81, 0x75, 0x0B, 0xA9, 0xB6, 0xA2, 0xB3, 0x7D, 0xD5,
+	0xF9, 0xAB, 0xF5, 0x60, 0x2C, 0x33, 0xDA, 0xC7, 0x75, 0xA5, 0x49, 0x0D, 0xF4, 0x37, 0x0A, 0xAF,
+	0x15, 0xC5, 0xAC, 0xBB, 0xD1, 0x97, 0xFB, 0xDB, 0x96, 0xBF, 0x15, 0xF1, 0x0A, 0x8D, 0x6A, 0x79,
+	0xCC, 0x6A, 0x49, 0x69, 0x28, 0x5A, 0xF6, 0xEC, 0xFF, 0x00, 0xCC, 0xFA, 0xAC, 0x8E, 0xA4, 0x7D,
+	0x93, 0x8D, 0xFF, 0x00, 0xAD, 0x40, 0xC9, 0xF2, 0xAB, 0xEC, 0x6F, 0xFE, 0x26, 0x9D, 0x41, 0x5B,
+	0xA6, 0x25, 0x36, 0x48, 0xBB, 0x7E, 0xF7, 0xCB, 0xF7, 0xA8, 0xF2, 0x2E, 0xBF, 0xE7, 0x8B, 0x7F,
+	0xDF, 0x35, 0xF0, 0x1C, 0xB2, 0xB6, 0xA7, 0xBE, 0xA5, 0xDC, 0x46, 0x5D, 0xD4, 0x82, 0x25, 0x45,
+	0xDD, 0x1B, 0xFC, 0xDF, 0xED, 0x53, 0xBC, 0x8B, 0xAF, 0xF9, 0xE2, 0xDF, 0xF7, 0xCD, 0x1E, 0x4C,
+	0xDD, 0x7E, 0xCF, 0x27, 0xFD, 0xF1, 0x4F, 0xE2, 0x4E, 0x23, 0xE6, 0x8F, 0x71, 0xA5, 0x4F, 0x90,
+	0xC8, 0xAD, 0xF3, 0x0F, 0xBA, 0xD9, 0xEB, 0x46, 0xC0, 0x0A, 0x85, 0x73, 0x8F, 0xE2, 0x39, 0xA7,
+	0x79, 0x52, 0xE7, 0xFE, 0x3D, 0xA4, 0xFF, 0x00, 0xBE, 0x68, 0xF2, 0xAE, 0x33, 0xF2, 0x41, 0x27,
+	0xFD, 0xF3, 0x53, 0x17, 0x53, 0x5B, 0xFE, 0x44, 0xFB, 0xB7, 0xBD, 0xC6, 0x80, 0x4E, 0x41, 0x7E,
+	0x9D, 0x29, 0x7E, 0x62, 0xBC, 0x1E, 0x69, 0xDE, 0x4D, 0xC7, 0xFC, 0xF0, 0x93, 0xFE, 0xF9, 0xA4,
+	0x6B, 0x5B, 0xA3, 0xD6, 0x19, 0x3F, 0xEF, 0x9A, 0xAF, 0x7B, 0x96, 0xFF, 0x00, 0xA0, 0x7B, 0xB1,
+	0xB7, 0xBC, 0x37, 0x61, 0xF3, 0x15, 0xCB, 0x9C, 0x2F, 0xDE, 0xA3, 0x63, 0xAC, 0x6C, 0x5D, 0xD7,
+	0xEF, 0x53, 0xBE, 0xCD, 0x71, 0xFF, 0x00, 0x3C, 0x24, 0xFF, 0x00, 0xBE, 0x68, 0xFB, 0x3C, 0xEB,
+	0xF7, 0x62, 0x93, 0xFE, 0xF9, 0xA9, 0xBC, 0x96, 0xAB, 0x7F, 0x4D, 0xC9, 0xD3, 0xB9, 0x19, 0x49,
+	0x24, 0xF9, 0x25, 0x2B, 0xB4, 0xF5, 0x2B, 0x44, 0x85, 0xCC, 0x9B, 0x93, 0x6E, 0xDF, 0xEE, 0xB7,
+	0xDD, 0xA9, 0xBC, 0x9B, 0x9F, 0xF9, 0xF5, 0x93, 0xFE, 0xF8, 0xA3, 0xCA, 0x97, 0xFE, 0x7D, 0xA4,
+	0xFF, 0x00, 0xBE, 0x69, 0xBB, 0x2D, 0x79, 0x75, 0x2B, 0x9A, 0x37, 0xDC, 0x8D, 0x59, 0xD6, 0x37,
+	0x3F, 0x2B, 0x3B, 0x50, 0xEA, 0xC1, 0x57, 0xEC, 0xDD, 0x7F, 0x8B, 0x75, 0x3F, 0xC8, 0x9B, 0xFE,
+	0x7D, 0x5F, 0xFE, 0xF9, 0xA4, 0xF2, 0x66, 0xEB, 0xF6, 0x69, 0x3F, 0xEF, 0x8A, 0x5A, 0xC6, 0x4A,
+	0x57, 0xD7, 0xD0, 0x3D, 0xCE, 0xE3, 0x55, 0x48, 0x6A, 0x70, 0x5F, 0x9B, 0x34, 0xEF, 0x26, 0x6F,
+	0xF9, 0xF7, 0x93, 0xFE, 0xF9, 0xA6, 0xF9, 0x73, 0x7F, 0xCF, 0x19, 0x3F, 0xEF, 0x9A, 0x2D, 0x2E,
+	0xA3, 0x52, 0x88, 0x51, 0x41, 0x82, 0xE0, 0xFF, 0x00, 0xCB, 0x09, 0x3F, 0xEF, 0x9A, 0x1A, 0x1B,
+	0x8D, 0xBF, 0xF1, 0xEF, 0x27, 0xFD, 0xF3, 0x47, 0xBC, 0x9A, 0xFC, 0x74, 0x1F, 0x34, 0x7B, 0x8F,
+	0xB7, 0xC3, 0x5C, 0xC2, 0x23, 0xE4, 0xF9, 0x8B, 0xF2, 0xFF, 0x00, 0xC0, 0xAB, 0xE0, 0x8F, 0xF8,
+	0x22, 0xAC, 0x4C, 0x9F, 0xF0, 0x56, 0x9F, 0xDB, 0x68, 0x17, 0xDD, 0xB7, 0xC7, 0x76, 0x7F, 0xFA,
+	0x26, 0xBE, 0xDE, 0xF1, 0xEF, 0x8D, 0x34, 0x7F, 0x85, 0xBF, 0x0F, 0xF5, 0x9F, 0x89, 0x7A, 0xF6,
+	0xA5, 0x67, 0x63, 0x0E, 0x8B, 0xA6, 0xCD, 0x7B, 0x2B, 0x6A, 0x17, 0x0B, 0x12, 0xC8, 0xB1, 0xAE,
+	0xE6, 0x5D, 0xCD, 0xFE, 0xED, 0x7E, 0x7F, 0xFF, 0x00, 0xC1, 0xB5, 0xFE, 0x3E, 0x7F, 0xDA, 0x73,
+	0xF6, 0xA1, 0xFD, 0xAB, 0x3F, 0x6C, 0xAB, 0x3D, 0x1E, 0xE2, 0xCF, 0x47, 0xF1, 0xA7, 0x8D, 0xED,
+	0x66, 0xD1, 0x59, 0xA2, 0x65, 0x8E, 0xE2, 0x35, 0x8D, 0x95, 0x99, 0x59, 0xBE, 0xF7, 0xDD, 0xAF,
+	0xD3, 0x7C, 0x34, 0xA5, 0x3F, 0xAF, 0xE2, 0x2A, 0xFD, 0x85, 0x0E, 0x5B, 0xFF, 0x00, 0x7A, 0xE9,
+	0xDB, 0xEE, 0x3E, 0x67, 0x3E, 0xA9, 0x19, 0x53, 0x8C, 0x53, 0xEB, 0xFE, 0x67, 0xEB, 0xF5, 0x14,
+	0x89, 0xF7, 0x69, 0x6B, 0xF5, 0xF3, 0xE6, 0xC6, 0x3B, 0x6D, 0x71, 0x5F, 0x8C, 0x9F, 0xB5, 0x10,
+	0xDD, 0xFF, 0x00, 0x07, 0x3C, 0xFC, 0x17, 0x3F, 0xF5, 0x06, 0xD6, 0x3F, 0xF4, 0x5D, 0x7E, 0xCC,
+	0x48, 0xC8, 0xD2, 0xAA, 0x0F, 0x99, 0xBA, 0xD7, 0xE2, 0xC7, 0xFC, 0x15, 0xDF, 0xC5, 0xFA, 0x1F,
+	0xEC, 0x53, 0xFF, 0x00, 0x05, 0xD2, 0xFD, 0x9F, 0xFF, 0x00, 0x6A, 0xBF, 0x8A, 0x6B, 0x75, 0x07,
+	0x85, 0x6F, 0xB4, 0xDD, 0x42, 0x0B, 0x8D, 0x5A, 0x18, 0x19, 0xA2, 0x86, 0x49, 0x3F, 0x76, 0xAA,
+	0xED, 0xF7, 0x57, 0xE6, 0x6A, 0xF3, 0x73, 0x8A, 0x75, 0x2B, 0x64, 0xF8, 0x9A, 0x10, 0x5E, 0xF4,
+	0xE1, 0x24, 0xBD, 0x6C, 0x6D, 0x87, 0x92, 0x8E, 0x26, 0x17, 0xEE, 0x7E, 0xA3, 0x4D, 0xF3, 0xCC,
+	0x71, 0xFD, 0xEA, 0x4A, 0x83, 0x4C, 0xBC, 0xB5, 0xD7, 0xB4, 0xDB, 0x6D, 0x7F, 0x47, 0xBF, 0xB7,
+	0xBC, 0xB5, 0xBC, 0xB7, 0x59, 0xAD, 0xE6, 0xB2, 0x95, 0x65, 0x8D, 0x95, 0x97, 0x72, 0xFC, 0xCB,
+	0x56, 0x0C, 0x52, 0xFF, 0x00, 0xCF, 0x29, 0x3F, 0xEF, 0x9A, 0xFE, 0x65, 0xD6, 0x3B, 0xAB, 0x3D,
+	0x9F, 0xAA, 0xD0, 0xFB, 0xF8, 0xD4, 0x84, 0xE2, 0xAC, 0xC4, 0xA6, 0x90, 0xEC, 0x56, 0x47, 0x2A,
+	0x19, 0x7F, 0x85, 0x7E, 0xED, 0x39, 0x61, 0x95, 0x7E, 0x7F, 0x2A, 0x4F, 0xFB, 0xE6, 0x8F, 0x2A,
+	0x5F, 0xF9, 0xE1, 0x27, 0xFD, 0xF3, 0x55, 0x65, 0xBD, 0xBC, 0xB6, 0x2E, 0xF1, 0xEE, 0x1F, 0x3A,
+	0xB7, 0xC9, 0xB5, 0x56, 0xA3, 0x58, 0x5D, 0x63, 0x64, 0x49, 0x55, 0x7E, 0x6F, 0xBD, 0x53, 0x79,
+	0x53, 0x7F, 0xCF, 0xBC, 0x9F, 0xF7, 0xCD, 0x37, 0xC8, 0xB8, 0xE8, 0x6D, 0xDB, 0xFE, 0xF9, 0xA9,
+	0x5C, 0xC9, 0xDE, 0xDF, 0x86, 0xC2, 0xBC, 0x76, 0x1A, 0x2D, 0x61, 0x55, 0xC9, 0xF9, 0x9A, 0x85,
+	0x5D, 0xBF, 0x23, 0x3E, 0xE5, 0xA7, 0x7D, 0x9E, 0xE3, 0xFE, 0x78, 0x3F, 0xFD, 0xF1, 0x43, 0x5A,
+	0xDC, 0xE3, 0xFE, 0x3D, 0xA4, 0xFF, 0x00, 0xBE, 0x6A, 0xA3, 0x79, 0x4E, 0xFE, 0x5D, 0xB5, 0x17,
+	0xBB, 0xDC, 0x8D, 0x57, 0x74, 0x7F, 0xBD, 0xDA, 0xA5, 0x7E, 0xEB, 0x2D, 0x11, 0xC6, 0xEB, 0x0B,
+	0x7F, 0x7D, 0xAA, 0x45, 0xB6, 0x9F, 0x3F, 0xF1, 0xEF, 0x27, 0xFD, 0xF3, 0x4E, 0xF2, 0xE5, 0xFF,
+	0x00, 0x9E, 0x12, 0x7F, 0xDF, 0x35, 0x3E, 0xAB, 0x52, 0x9B, 0x89, 0x0C, 0x70, 0xED, 0x8F, 0x67,
+	0xDE, 0xFF, 0x00, 0x69, 0xA9, 0xDB, 0x59, 0x4F, 0x9C, 0x9F, 0xEB, 0x3F, 0xDA, 0xFB, 0xB4, 0xFF,
+	0x00, 0x26, 0x7F, 0xF9, 0xE3, 0x27, 0xFD, 0xF3, 0x4B, 0xE5, 0x5C, 0x7F, 0xCF, 0xB3, 0xFF, 0x00,
+	0xDF, 0x34, 0xE4, 0xE3, 0xCA, 0xE4, 0xD5, 0xDF, 0xF9, 0xE8, 0x1C, 0xD1, 0x20, 0x58, 0xE7, 0x5D,
+	0xBB, 0x36, 0xD4, 0xBB, 0x77, 0x6E, 0xDE, 0x8B, 0xB6, 0x9D, 0xE5, 0x4B, 0xFF, 0x00, 0x3E, 0xF2,
+	0x7F, 0xDF, 0x34, 0x18, 0xA6, 0x1F, 0xF2, 0xEF, 0x27, 0xFD, 0xF3, 0x49, 0xC6, 0x5C, 0xCE, 0x36,
+	0xB3, 0x5D, 0x42, 0xF1, 0x21, 0xF2, 0xDF, 0x6F, 0x4F, 0xBB, 0xF7, 0x69, 0xCB, 0x1F, 0x99, 0xB5,
+	0xE6, 0x3B, 0x5F, 0xF8, 0xB6, 0xFD, 0xDA, 0x93, 0xCA, 0xB8, 0xFF, 0x00, 0x9F, 0x67, 0xFF, 0x00,
+	0xBE, 0x69, 0xA6, 0x19, 0x97, 0xAC, 0x12, 0x7F, 0xDF, 0x35, 0x4B, 0x99, 0x46, 0xD6, 0xD7, 0xD0,
+	0x3D, 0xD6, 0x36, 0x1F, 0x37, 0xE6, 0xFB, 0x4E, 0xD3, 0xB7, 0xFD, 0x55, 0x33, 0x73, 0xEE, 0xDE,
+	0xE9, 0xF3, 0x7F, 0xB3, 0x52, 0xF9, 0x72, 0xFF, 0x00, 0xCF, 0x29, 0x3F, 0xEF, 0x9A, 0x3C, 0x9B,
+	0x84, 0x65, 0x75, 0xB5, 0x27, 0x6F, 0xDE, 0xF9, 0x68, 0x97, 0x36, 0x88, 0x3D, 0xD4, 0xEE, 0x86,
+	0xAC, 0x88, 0xCD, 0xFF, 0x00, 0xB3, 0x53, 0xDF, 0xFD, 0x4B, 0x63, 0xEE, 0xED, 0xA4, 0x11, 0xDC,
+	0xFC, 0xDB, 0x74, 0xF6, 0xC3, 0x73, 0xF7, 0x6A, 0xAF, 0x88, 0x35, 0x7D, 0x1F, 0xC2, 0x3E, 0x1E,
+	0xBE, 0xF1, 0x3F, 0x8B, 0x35, 0x5B, 0x7D, 0x36, 0xC6, 0xC6, 0xCE, 0x49, 0x9E, 0x6B, 0xA9, 0x56,
+	0x38, 0xF6, 0xAA, 0xEE, 0xFB, 0xCD, 0x44, 0x79, 0xA4, 0xB9, 0x60, 0xBD, 0xE7, 0xA5, 0x89, 0xA9,
+	0x52, 0x31, 0x8D, 0xDB, 0x3F, 0x36, 0x3F, 0xE0, 0x9D, 0x7F, 0x2F, 0xFC, 0x1C, 0x57, 0xFB, 0x41,
+	0x49, 0x27, 0xCB, 0xBB, 0x46, 0xD2, 0xF6, 0xAF, 0xFC, 0x06, 0xBF, 0x65, 0x37, 0x0D, 0xFB, 0x6B,
+	0xF1, 0x63, 0xFE, 0x08, 0x69, 0xE2, 0xFB, 0x3F, 0xDB, 0x1F, 0xFE, 0x0A, 0xFF, 0x00, 0xFB, 0x43,
+	0x7E, 0xD8, 0x7F, 0x0F, 0x6C, 0xEE, 0x1B, 0xC1, 0xF2, 0x59, 0xD8, 0xDA, 0xE9, 0xFA, 0x9C, 0xD6,
+	0xED, 0x1C, 0x77, 0x12, 0x42, 0xCD, 0x1B, 0x79, 0x6D, 0xFC, 0x55, 0xFB, 0x49, 0x6E, 0x81, 0x09,
+	0x4F, 0x35, 0x9D, 0xB7, 0x67, 0xE6, 0xAF, 0xE9, 0xCC, 0xBA, 0x9D, 0x5A, 0x59, 0x7D, 0x18, 0x54,
+	0x56, 0x92, 0x84, 0x6E, 0xBE, 0x48, 0xFC, 0xF6, 0xB3, 0xBD, 0x69, 0x3F, 0x32, 0xC5, 0x14, 0x51,
+	0x5D, 0xC6, 0x61, 0x45, 0x14, 0x50, 0x04, 0x2D, 0x19, 0xCE, 0x36, 0xB6, 0x37, 0x66, 0xBE, 0x03,
+	0xFF, 0x00, 0x82, 0xB4, 0x7F, 0xC1, 0x0F, 0x7C, 0x27, 0xFB, 0x7D, 0xDD, 0xD9, 0xFC, 0x68, 0xF8,
+	0x1F, 0xE3, 0x58, 0xFE, 0x1E, 0xFC, 0x5C, 0xD1, 0xE4, 0xF3, 0x74, 0xAF, 0x17, 0x2A, 0x36, 0xC6,
+	0x6D, 0xDB, 0x9B, 0xCC, 0x58, 0xFE, 0xF6, 0xEC, 0x7F, 0x15, 0x7E, 0x80, 0x3F, 0x4A, 0x3F, 0xE5,
+	0x9D, 0x43, 0xF7, 0xAF, 0x17, 0xAA, 0xEC, 0x11, 0x94, 0xA3, 0xAA, 0xE8, 0x7E, 0x1D, 0xC9, 0xF0,
+	0xFB, 0xFE, 0x0E, 0x90, 0xF0, 0x5C, 0xBF, 0xF0, 0x88, 0x69, 0xBF, 0x1B, 0xB4, 0xFD, 0x52, 0xDF,
+	0x4F, 0x5F, 0x22, 0xDE, 0xFA, 0x3F, 0x0B, 0xC7, 0xB6, 0x65, 0x5F, 0x95, 0x5A, 0x9A, 0xDE, 0x1B,
+	0xFF, 0x00, 0x83, 0xA7, 0x4F, 0xFC, 0xD5, 0x5B, 0x1F, 0xFC, 0x25, 0xE3, 0xAF, 0xDC, 0x25, 0x76,
+	0xDD, 0xD6, 0xA6, 0xAF, 0x3A, 0x59, 0x36, 0x51, 0x52, 0x4E, 0x4E, 0x84, 0x6E, 0xFC, 0x8D, 0x16,
+	0x22, 0xBE, 0xDC, 0xC7, 0xE1, 0xBA, 0xF8, 0x6F, 0xFE, 0x0E, 0x9C, 0x5F, 0xF9, 0xAA, 0x96, 0x3F,
+	0xF8, 0x4B, 0xC7, 0x47, 0xFC, 0x23, 0x9F, 0xF0, 0x74, 0xEF, 0xFD, 0x15, 0x5B, 0x1F, 0xFC, 0x25,
+	0xE3, 0xAF, 0xDC, 0x6C, 0x9D, 0xF4, 0x9B, 0x9B, 0xD6, 0x8F, 0xEC, 0x4C, 0x9F, 0xFE, 0x81, 0xE3,
+	0xF7, 0x07, 0xB6, 0xC4, 0x7F, 0x3B, 0x3F, 0x0E, 0xBF, 0xE1, 0x1C, 0xFF, 0x00, 0x83, 0xA7, 0x7F,
+	0xE8, 0xAA, 0xD8, 0xFF, 0x00, 0xE1, 0x2F, 0x1D, 0x23, 0x78, 0x6B, 0xFE, 0x0E, 0x9C, 0x6E, 0xBF,
+	0x15, 0x6C, 0x7F, 0xF0, 0x97, 0x8E, 0xBF, 0x71, 0xB7, 0x37, 0xAD, 0x1B, 0x9B, 0xD6, 0x8F, 0xEC,
+	0x4C, 0x9F, 0xFE, 0x81, 0xE3, 0xF7, 0x07, 0xB6, 0xC4, 0x7F, 0x3B, 0x3F, 0x0E, 0xBF, 0xE1, 0x16,
+	0xFF, 0x00, 0x83, 0xA7, 0x47, 0x4F, 0x8A, 0x96, 0x3F, 0xF8, 0x4B, 0xC7, 0x49, 0xFF, 0x00, 0x08,
+	0xEF, 0xFC, 0x1D, 0x3F, 0xFF, 0x00, 0x45, 0x4E, 0xC7, 0xFF, 0x00, 0x09, 0x78, 0xEB, 0xF7, 0x1B,
+	0x73, 0x7A, 0xD1, 0xB9, 0xBD, 0x69, 0xFF, 0x00, 0x62, 0xE4, 0xFF, 0x00, 0xF4, 0x0F, 0x1F, 0xB8,
+	0x3D, 0xBE, 0x27, 0xF9, 0xD9, 0xF8, 0x74, 0x7C, 0x33, 0xFF, 0x00, 0x07, 0x4E, 0x3A, 0xF3, 0xF1,
+	0x52, 0xC7, 0x77, 0xFD, 0x8A, 0xF1, 0xD2, 0x7F, 0xC2, 0x2F, 0xFF, 0x00, 0x07, 0x50, 0x0F, 0xF9,
+	0xAA, 0xF6, 0x2B, 0xFF, 0x00, 0x72, 0xBC, 0x75, 0xFB, 0x8D, 0xB9, 0xBD, 0x68, 0xDC, 0xDE, 0xB4,
+	0x7F, 0x62, 0xE4, 0xFF, 0x00, 0xF3, 0xE2, 0x3F, 0x70, 0x7D, 0x63, 0x13, 0x6B, 0x73, 0xB3, 0xF0,
+	0xE3, 0xFE, 0x11, 0x8F, 0xF8, 0x3A, 0x6B, 0xFE, 0x8A, 0x9D, 0x8F, 0xFE, 0x12, 0xF1, 0xD3, 0xBF,
+	0xE1, 0x1C, 0xFF, 0x00, 0x83, 0xA7, 0x7F, 0xE8, 0xAA, 0xD8, 0xFF, 0x00, 0xE1, 0x2F, 0x1D, 0x7E,
+	0xE2, 0xEE, 0x6F, 0x5A, 0x37, 0x37, 0xAD, 0x1F, 0xD8, 0xB9, 0x3F, 0xFC, 0xF8, 0x8F, 0xDC, 0x1E,
+	0xDF, 0x11, 0xFC, 0xEC, 0xFC, 0x3A, 0xFF, 0x00, 0x84, 0x73, 0xFE, 0x0E, 0x9D, 0xFF, 0x00, 0xA2,
+	0xAB, 0x63, 0xFF, 0x00, 0x84, 0xBC, 0x74, 0x7F, 0xC2, 0x39, 0xFF, 0x00, 0x07, 0x4E, 0xFF, 0x00,
+	0xD1, 0x55, 0xB1, 0xFF, 0x00, 0xC2, 0x5E, 0x3A, 0xFD, 0xC5, 0xDC, 0xDE, 0xB4, 0x6E, 0x6F, 0x5A,
+	0x5F, 0xD8, 0x99, 0x3F, 0xFD, 0x03, 0xC7, 0xEE, 0x0F, 0x6F, 0x88, 0xFE, 0x76, 0x7E, 0x1D, 0x7F,
+	0xC2, 0x37, 0xFF, 0x00, 0x07, 0x4E, 0x7F, 0xD1, 0x54, 0xB1, 0xFF, 0x00, 0xC2, 0x5A, 0x3A, 0x3F,
+	0xE1, 0x1C, 0xFF, 0x00, 0x83, 0xA7, 0x7F, 0xE8, 0xAA, 0xD8, 0xFF, 0x00, 0xE1, 0x2F, 0x1D, 0x7E,
+	0xE2, 0xEE, 0x6F, 0x5A, 0x37, 0x37, 0xAD, 0x1F, 0xD8, 0x99, 0x3F, 0xFC, 0xF8, 0x8F, 0xDC, 0x1E,
+	0xDF, 0x11, 0xFC, 0xEC, 0xFC, 0x3A, 0xFF, 0x00, 0x84, 0x73, 0xFE, 0x0E, 0x9D, 0xFF, 0x00, 0xA2,
+	0xAB, 0x63, 0xFF, 0x00, 0x84, 0xBC, 0x74, 0x8D, 0xE1, 0x9F, 0xF8, 0x3A, 0x71, 0x97, 0xE5, 0xF8,
+	0xA7, 0x62, 0xAD, 0xFC, 0x4D, 0xFF, 0x00, 0x08, 0xBC, 0x75, 0xFB, 0x8D, 0xB9, 0xBD, 0x68, 0xDC,
+	0xDE, 0xB4, 0x7F, 0x62, 0x64, 0xFF, 0x00, 0xF3, 0xE2, 0x3F, 0x70, 0x2C, 0x46, 0x22, 0x2F, 0xE3,
+	0x67, 0xE1, 0xCF, 0xF6, 0x0F, 0xFC, 0x1D, 0x41, 0x67, 0xB9, 0x2D, 0xBE, 0x28, 0x58, 0xB3, 0x7D,
+	0xED, 0xDF, 0xF0, 0x8B, 0xC7, 0x5D, 0xDF, 0xEC, 0xF5, 0xFF, 0x00, 0x04, 0x0D, 0xFD, 0xA6, 0x7F,
+	0x6B, 0xCF, 0x8C, 0xDA, 0x0F, 0xED, 0x49, 0xFF, 0x00, 0x05, 0x84, 0xF8, 0xE7, 0x0F, 0x8D, 0x97,
+	0x4D, 0xDD, 0x71, 0x67, 0xE0, 0x9B, 0x1B, 0x79, 0x2C, 0xFC, 0x99, 0x3F, 0x87, 0xCC, 0xDB, 0xF2,
+	0xB6, 0xD6, 0x55, 0xAF, 0xD8, 0xBD, 0xCD, 0xEB, 0x49, 0x71, 0xF7, 0x6B, 0xA3, 0x0F, 0x97, 0x60,
+	0x70, 0xB2, 0xBD, 0x0A, 0x6A, 0x3E, 0x88, 0x25, 0x5A, 0xB4, 0xA3, 0xAB, 0xB9, 0x4F, 0x4B, 0xD2,
+	0x2C, 0x34, 0x4D, 0x1A, 0xDF, 0x44, 0xD2, 0x6D, 0x23, 0xB7, 0xB6, 0xB5, 0x85, 0x61, 0xB5, 0x86,
+	0x35, 0xC2, 0xC7, 0x1A, 0x8D, 0xAA, 0xBF, 0xF7, 0xCD, 0x5B, 0x89, 0x42, 0x77, 0xA7, 0xB7, 0x51,
+	0x4E, 0xAE, 0xAD, 0x99, 0x98, 0x53, 0x5D, 0x77, 0x2E, 0x29, 0xD4, 0x55, 0x01, 0xF0, 0x5F, 0xFC,
+	0x15, 0xCB, 0xFE, 0x08, 0x87, 0xF0, 0xE3, 0xFE, 0x0A, 0x47, 0x69, 0x6D, 0xE3, 0xFF, 0x00, 0x01,
+	0xF8, 0xA5, 0x7C, 0x11, 0xF1, 0x33, 0x4B, 0x6D, 0xFA, 0x4F, 0x8B, 0xA3, 0xF3, 0x36, 0xAC, 0x8B,
+	0xF7, 0x7C, 0xC5, 0x8F, 0xE6, 0x6A, 0xF8, 0xA2, 0xDF, 0xE1, 0x07, 0xFC, 0x1D, 0x09, 0xF0, 0xB6,
+	0xCE, 0x3F, 0x86, 0xBA, 0x07, 0xC7, 0x4D, 0x3F, 0x56, 0xD3, 0x74, 0x35, 0xFB, 0x25, 0x8E, 0xA1,
+	0x1F, 0x86, 0x55, 0xBC, 0xE8, 0xE3, 0xF9, 0x55, 0xB7, 0x7F, 0x16, 0xEA, 0xFD, 0xC7, 0x9B, 0xEE,
+	0x2D, 0x0A, 0xCD, 0x8E, 0xB5, 0xCB, 0x5F, 0x07, 0x83, 0xC6, 0x47, 0x97, 0x11, 0x4D, 0x4D, 0x79,
+	0xA3, 0x48, 0xD4, 0xA9, 0x0F, 0x85, 0x9F, 0x87, 0x4D, 0xE1, 0xBF, 0xF8, 0x3A, 0x83, 0xA7, 0xFC,
+	0x2D, 0x4B, 0x1F, 0xFC, 0x25, 0xE3, 0xA4, 0xFF, 0x00, 0x84, 0x6B, 0xFE, 0x0E, 0x9C, 0xFF, 0x00,
+	0xA2, 0xB1, 0x63, 0xFF, 0x00, 0x84, 0xBC, 0x75, 0xFB, 0x94, 0x7A, 0x53, 0x7B, 0x35, 0x72, 0xFF,
+	0x00, 0x62, 0xE4, 0xEB, 0x6C, 0x3C, 0x7E, 0xE2, 0xBE, 0xB1, 0x88, 0xFE, 0x63, 0xF0, 0xE7, 0xFE,
+	0x11, 0xCF, 0xF8, 0x3A, 0x77, 0xFE, 0x8A, 0xAD, 0x8F, 0xFE, 0x12, 0xF1, 0xD1, 0xFF, 0x00, 0x08,
+	0xE7, 0xFC, 0x1D, 0x3B, 0xFF, 0x00, 0x45, 0x56, 0xC7, 0xFF, 0x00, 0x09, 0x78, 0xEB, 0xF7, 0x17,
+	0x73, 0x7A, 0xD1, 0xB9, 0xBD, 0x68, 0xFE, 0xC4, 0xC9, 0xFF, 0x00, 0xE8, 0x1E, 0x3F, 0x71, 0x3E,
+	0xDB, 0x11, 0xFC, 0xEC, 0xFC, 0x3A, 0xFF, 0x00, 0x84, 0x73, 0xFE, 0x0E, 0x9D, 0xFF, 0x00, 0xA2,
+	0xAB, 0x63, 0xFF, 0x00, 0x84, 0xBC, 0x74, 0xDF, 0xF8, 0x46, 0x7F, 0xE0, 0xEA, 0x1F, 0xFA, 0x2A,
+	0xF6, 0x3F, 0xF8, 0x4B, 0xC7, 0x5F, 0xB8, 0xFB, 0x9B, 0xD6, 0x8D, 0xCD, 0xEB, 0x47, 0xF6, 0x1E,
+	0x4D, 0xFF, 0x00, 0x40, 0xF1, 0xFB, 0x87, 0xED, 0xF1, 0x1F, 0xCC, 0xCF, 0xC3, 0x9F, 0xF8, 0x47,
+	0x3F, 0xE0, 0xE9, 0xD5, 0x5E, 0x3E, 0x2A, 0xD8, 0xFF, 0x00, 0xE1, 0x2F, 0x1D, 0x1F, 0xF0, 0x8E,
+	0xFF, 0x00, 0xC1, 0xD3, 0xFF, 0x00, 0xF4, 0x54, 0xEC, 0x7F, 0xF0, 0x97, 0x8E, 0xBF, 0x71, 0xB7,
+	0x37, 0xAD, 0x1B, 0x9B, 0xD6, 0x9A, 0xC9, 0x72, 0x65, 0xFF, 0x00, 0x30, 0xF1, 0xFB, 0x83, 0xDB,
+	0xE2, 0x3F, 0x99, 0x9F, 0x87, 0x3F, 0xF0, 0x8C, 0xFF, 0x00, 0xC1, 0xD3, 0xDF, 0xC7, 0xF1, 0x52,
+	0xCD, 0xBF, 0xEE, 0x57, 0x8E, 0x93, 0xFE, 0x11, 0xBF, 0xF8, 0x3A, 0x6B, 0xFE, 0x8A, 0x95, 0x9F,
+	0xFE, 0x12, 0xF1, 0xD7, 0xEE, 0x3E, 0xE6, 0xF5, 0xA3, 0x73, 0x7A, 0xD3, 0xFE, 0xC5, 0xC9, 0xFF,
+	0x00, 0xE8, 0x1E, 0x1F, 0x70, 0xBD, 0xBE, 0x23, 0xF9, 0x99, 0xF8, 0x72, 0x3C, 0x37, 0xFF, 0x00,
+	0x07, 0x4E, 0xFF, 0x00, 0x07, 0xC5, 0x1B, 0x35, 0xFF, 0x00, 0xB9, 0x5E, 0x3A, 0x5F, 0xF8, 0x46,
+	0xFF, 0x00, 0xE0, 0xE9, 0xD6, 0xE0, 0x7C, 0x54, 0xB1, 0xFF, 0x00, 0xC2, 0x5E, 0x3A, 0xFD, 0xC5,
+	0xDC, 0xDE, 0xB4, 0x6E, 0x6F, 0x5A, 0x9F, 0xEC, 0x4C, 0x9F, 0xFE, 0x7C, 0x47, 0xEE, 0x1F, 0xB7,
+	0xC4, 0x7F, 0x33, 0x3F, 0x0E, 0xBF, 0xE1, 0x18, 0xFF, 0x00, 0x83, 0xA7, 0x57, 0xFE, 0x6A, 0xB5,
+	0x8F, 0xFE, 0x12, 0xF1, 0xD1, 0xFF, 0x00, 0x08, 0xE7, 0xFC, 0x1D, 0x39, 0xFF, 0x00, 0x45, 0x52,
+	0xC7, 0xFF, 0x00, 0x09, 0x78, 0xEB, 0xF7, 0x17, 0x73, 0x7A, 0xD1, 0xB9, 0xBD, 0x69, 0xFF, 0x00,
+	0x62, 0x64, 0xFF, 0x00, 0xF3, 0xE2, 0x3F, 0x70, 0xBD, 0xBE, 0x27, 0xF9, 0xD9, 0xF8, 0x75, 0xFF,
+	0x00, 0x08, 0xE7, 0xFC, 0x1D, 0x3B, 0xFF, 0x00, 0x45, 0x56, 0xC7, 0xFF, 0x00, 0x09, 0x78, 0xE8,
+	0xFF, 0x00, 0x84, 0x73, 0xFE, 0x0E, 0x9D, 0xFF, 0x00, 0xA2, 0xAB, 0x63, 0xFF, 0x00, 0x84, 0xBC,
+	0x75, 0xFB, 0x8B, 0xB9, 0xBD, 0x68, 0xDC, 0xDE, 0xB4, 0xBF, 0xB0, 0xF2, 0x6F, 0xFA, 0x07, 0x8F,
+	0xDC, 0x1F, 0x58, 0xC4, 0x7F, 0x3F, 0xE4, 0x7E, 0x1C, 0xB7, 0x86, 0xFF, 0x00, 0xE0, 0xE9, 0xD1,
+	0xFF, 0x00, 0x35, 0x52, 0xCF, 0xFF, 0x00, 0x09, 0x78, 0xE9, 0x17, 0x42, 0xFF, 0x00, 0x83, 0xA7,
+	0x2D, 0x59, 0x66, 0x93, 0xE2, 0x85, 0x9B, 0xAF, 0xFC, 0xF3, 0xFF, 0x00, 0x84, 0x5E, 0x3D, 0xD5,
+	0xFB, 0x8F, 0xB9, 0xBD, 0x69, 0x1D, 0x8E, 0xE5, 0xE6, 0x8F, 0xEC, 0x5C, 0x9E, 0x3A, 0xAA, 0x11,
+	0xFB, 0x87, 0xF5, 0x8C, 0x47, 0xF3, 0x1F, 0x8D, 0x7F, 0x04, 0x7F, 0xE0, 0x86, 0x1F, 0xB6, 0xCF,
+	0xED, 0xD5, 0xF1, 0x17, 0xC3, 0xDF, 0x1D, 0xBF, 0xE0, 0xAF, 0x9F, 0x1F, 0x6D, 0xFC, 0x49, 0xA5,
+	0xE9, 0x37, 0x9E, 0x75, 0xBF, 0x81, 0xEC, 0x6C, 0xDA, 0xCD, 0xD7, 0x6F, 0xFC, 0xF4, 0xDB, 0xF2,
+	0xB5, 0x7E, 0xC0, 0x78, 0x5B, 0xC2, 0xFA, 0x27, 0x81, 0xBC, 0x35, 0xA6, 0xF8, 0x3B, 0xC3, 0x1A,
+	0x74, 0x76, 0xBA, 0x6E, 0x97, 0x67, 0x1D, 0xAE, 0x9F, 0x6B, 0x0A, 0xED, 0x58, 0xA3, 0x8D, 0x76,
+	0xAA, 0xFF, 0x00, 0xDF, 0x22, 0xB5, 0x24, 0xFB, 0xEB, 0x4E, 0x4E, 0xB5, 0xDD, 0x4A, 0x14, 0xE1,
+	0x4F, 0xD9, 0xD3, 0x8A, 0x8A, 0x5D, 0x16, 0xC4, 0x4A, 0x53, 0x93, 0xBC, 0x9D, 0xC6, 0xB2, 0xE7,
+	0xE7, 0xF2, 0xFE, 0x6A, 0x71, 0x8F, 0xF7, 0x81, 0xE9, 0xD4, 0x56, 0xC4, 0x90, 0xCC, 0xDB, 0xB6,
+	0xA3, 0x42, 0xCC, 0x1B, 0xF8, 0xBF, 0xBB, 0x5F, 0x15, 0x7F, 0xC1, 0x58, 0x3F, 0xE0, 0x8C, 0x3F,
+	0x06, 0xBF, 0xE0, 0xA6, 0x3A, 0x04, 0x7E, 0x27, 0x4D, 0x53, 0xFE, 0x11, 0x9F, 0x88, 0x9A, 0x6A,
+	0x2F, 0xF6, 0x0F, 0x8B, 0xA3, 0x69, 0x3F, 0xD1, 0xD9, 0x57, 0xE4, 0xDC, 0xAB, 0xF3, 0x36, 0xDA,
+	0xFB, 0x69, 0xFE, 0xED, 0x30, 0xF4, 0xA5, 0x2D, 0x9A, 0x0B, 0xB5, 0xAA, 0x3F, 0x0E, 0x6C, 0xFF,
+	0x00, 0x67, 0xCF, 0xF8, 0x39, 0xBF, 0xF6, 0x7C, 0xB7, 0x8F, 0xE0, 0xD7, 0x81, 0x7F, 0x68, 0x3D,
+	0x3F, 0xC4, 0x3A, 0x2F, 0x87, 0x57, 0xEC, 0x9A, 0x5E, 0xA9, 0x1F, 0x87, 0x16, 0x4F, 0xB4, 0x42,
+	0xBF, 0x75, 0xB7, 0x37, 0xDE, 0xA5, 0x6F, 0x0C, 0xFF, 0x00, 0xC1, 0xD3, 0x53, 0x48, 0xCE, 0x9F,
+	0x15, 0x2C, 0xD7, 0xFE, 0xE5, 0x78, 0xEB, 0xF7, 0x1B, 0x24, 0x8E, 0x4D, 0x20, 0x24, 0x74, 0xAF,
+	0x33, 0xFB, 0x1B, 0x28, 0x9C, 0x9C, 0xA5, 0x42, 0x3F, 0x71, 0xAA, 0xAF, 0x88, 0x51, 0xF8, 0x8F,
+	0xC3, 0xAF, 0xF8, 0x45, 0x7F, 0xE0, 0xE9, 0xDF, 0xFA, 0x2A, 0x96, 0x3F, 0xF8, 0x4B, 0xC7, 0x49,
+	0xFF, 0x00, 0x08, 0xBF, 0xFC, 0x1D, 0x3B, 0xFF, 0x00, 0x45, 0x4E, 0xCF, 0xFF, 0x00, 0x09, 0x78,
+	0xEB, 0xF7, 0x1F, 0x73, 0x7A, 0xD1, 0xB9, 0xBD, 0x6A, 0xBF, 0xB1, 0x72, 0x7F, 0xFA, 0x07, 0x8F,
+	0xDC, 0x2F, 0xAC, 0x62, 0x3A, 0x4D, 0x9F, 0x87, 0x3F, 0xF0, 0x8D, 0x7F, 0xC1, 0xD3, 0x7F, 0xF4,
+	0x55, 0x2C, 0x7F, 0xF0, 0x97, 0x8E, 0x85, 0xF0, 0xD7, 0xFC, 0x1D, 0x38, 0xBD, 0x3E, 0x2A, 0xD8,
+	0xFF, 0x00, 0xE1, 0x2F, 0x1D, 0x7E, 0xE3, 0x6E, 0x6F, 0x5A, 0x37, 0x37, 0xAD, 0x4F, 0xF6, 0x26,
+	0x4F, 0xFF, 0x00, 0x3E, 0x23, 0xF7, 0x07, 0xD6, 0x31, 0x5F, 0xCE, 0xCF, 0xC3, 0xA6, 0xF0, 0xDF,
+	0xFC, 0x1D, 0x3B, 0xD3, 0xFE, 0x16, 0xA5, 0x8F, 0xFE, 0x12, 0xF1, 0xD3, 0x3F, 0xE1, 0x1A, 0xFF,
+	0x00, 0x83, 0xA7, 0xFF, 0x00, 0xE8, 0xAA, 0x58, 0xFF, 0x00, 0xE1, 0x2F, 0x1D, 0x7E, 0xE4, 0x6E,
+	0x6F, 0x5A, 0x37, 0x37, 0xAD, 0x1F, 0xD8, 0x99, 0x3F, 0xFD, 0x03, 0xC7, 0xEE, 0x1F, 0xD6, 0x31,
+	0x3F, 0xCE, 0xCF, 0xC3, 0x8F, 0xF8, 0x46, 0x3F, 0xE0, 0xE9, 0xAF, 0xFA, 0x2A, 0x76, 0x3F, 0xF8,
+	0x4B, 0xC7, 0x47, 0xFC, 0x23, 0x1F, 0xF0, 0x74, 0xD7, 0xFD, 0x15, 0x3B, 0x1F, 0xFC, 0x25, 0xE3,
+	0xAF, 0xDC, 0x7D, 0xCD, 0xEB, 0x46, 0xE6, 0xF5, 0xAA, 0xFE, 0xC5, 0xC9, 0xFF, 0x00, 0xE8, 0x1E,
+	0x3F, 0x70, 0xBE, 0xB1, 0x89, 0xFE, 0x76, 0x7E, 0x1D, 0x7F, 0xC2, 0x39, 0xFF, 0x00, 0x07, 0x4E,
+	0xFF, 0x00, 0xD1, 0x55, 0xB1, 0xFF, 0x00, 0xC2, 0x5E, 0x3A, 0x3F, 0xE1, 0x1C, 0xFF, 0x00, 0x83,
+	0xA7, 0x7F, 0xE8, 0xAA, 0xD8, 0xFF, 0x00, 0xE1, 0x2F, 0x1D, 0x7E, 0xE2, 0xEE, 0x6F, 0x5A, 0x37,
+	0x37, 0xAD, 0x1F, 0xD8, 0xB9, 0x3F, 0xFD, 0x03, 0xC7, 0xEE, 0x0F, 0x6D, 0x88, 0xFE, 0x76, 0x7E,
+	0x1C, 0xFF, 0x00, 0xC2, 0x35, 0xFF, 0x00, 0x07, 0x4D, 0xF7, 0xF8, 0xA9, 0x63, 0xFF, 0x00, 0x84,
+	0xBC, 0x74, 0x7F, 0xC2, 0x35, 0xFF, 0x00, 0x07, 0x4D, 0xFF, 0x00, 0xD1, 0x54, 0xB1, 0xFF, 0x00,
+	0xC2, 0x5E, 0x3A, 0xFD, 0xC6, 0xDC, 0xDE, 0xB4, 0x6E, 0x6F, 0x5A, 0x9F, 0xEC, 0x4C, 0x9F, 0x9A,
+	0xFE, 0xC2, 0x3F, 0x70, 0x7B, 0x7C, 0x4F, 0xF3, 0xB3, 0xF0, 0xEB, 0xFE, 0x11, 0xCF, 0xF8, 0x3A,
+	0x77, 0xFE, 0x8A, 0xAD, 0x8F, 0xFE, 0x12, 0xF1, 0xD1, 0xFF, 0x00, 0x08, 0xE7, 0xFC, 0x1D, 0x3B,
+	0xFF, 0x00, 0x45, 0x56, 0xC7, 0xFF, 0x00, 0x09, 0x78, 0xEB, 0xF7, 0x17, 0x73, 0x7A, 0xD1, 0xB9,
+	0xBD, 0x68, 0xFE, 0xC4, 0xC9, 0xFF, 0x00, 0xE8, 0x1E, 0x3F, 0x70, 0x7B, 0x7C, 0x47, 0xF3, 0xB3,
+	0xF0, 0xE8, 0xF8, 0x73, 0xFE, 0x0E, 0x9C, 0xED, 0xF1, 0x4E, 0xC7, 0xFF, 0x00, 0x09, 0x78, 0xE8,
+	0xFF, 0x00, 0x84, 0x77, 0xFE, 0x0E, 0x9E, 0xFF, 0x00, 0xA2, 0xA9, 0x63, 0xFF, 0x00, 0x84, 0xBC,
+	0x75, 0xFB, 0x8B, 0xB9, 0xBD, 0x68, 0xDC, 0xDE, 0xB4, 0x7F, 0x61, 0xE4, 0xB7, 0xBF, 0xD5, 0xE3,
+	0xF7, 0x04, 0x71, 0x18, 0x8D, 0xF9, 0xD9, 0xF8, 0x71, 0xFF, 0x00, 0x08, 0xDF, 0xFC, 0x1D, 0x34,
+	0xBF, 0xF3, 0x55, 0x2C, 0xD9, 0xBF, 0xEC, 0x57, 0x8E, 0xB6, 0xFE, 0x1D, 0x7F, 0xC1, 0x0D, 0x7F,
+	0xE0, 0xA0, 0x9F, 0xF0, 0x51, 0xDF, 0x1D, 0x68, 0xFF, 0x00, 0x14, 0x7F, 0xE0, 0xAE, 0x3F, 0xB4,
+	0x3C, 0x7A, 0x8F, 0x86, 0xF4, 0xBB, 0xC5, 0xF3, 0x7C, 0x0F, 0x63, 0x67, 0x25, 0x9C, 0xD7, 0x0B,
+	0x1F, 0xFB, 0x51, 0xFC, 0xBF, 0x35, 0x7E, 0xD6, 0x6E, 0x6F, 0x5A, 0x42, 0x49, 0xEB, 0x5A, 0xE1,
+	0xF2, 0xBC, 0xB7, 0x0B, 0x53, 0xDA, 0x51, 0xA3, 0x18, 0xCB, 0xBA, 0x5A, 0x8E, 0x55, 0xAB, 0x49,
+	0x59, 0xB3, 0x9E, 0xF8, 0x49, 0xF0, 0xBB, 0xC1, 0x7F, 0x05, 0x3E, 0x1A, 0xE8, 0x7F, 0x09, 0x7E,
+	0x1B, 0xE8, 0xAB, 0xA7, 0xE8, 0x1E, 0x1D, 0xD3, 0xA3, 0xB2, 0xD2, 0x6C, 0x57, 0xFE, 0x58, 0xC3,
+	0x1A, 0xED, 0x55, 0xAE, 0x96, 0x91, 0x3E, 0xED, 0x2D, 0x77, 0x99, 0x08, 0xCB, 0xB9, 0x76, 0xD3,
+	0x19, 0x37, 0x0D, 0x8F, 0x52, 0x51, 0x4A, 0xDA, 0xDC, 0x0F, 0x9C, 0xFF, 0x00, 0xE0, 0xA4, 0x1F,
+	0xF0, 0x4E, 0x2F, 0x81, 0x3F, 0xF0, 0x52, 0x8F, 0x80, 0x37, 0xDF, 0x04, 0xFE, 0x31, 0xE9, 0x0B,
+	0xF6, 0x8D, 0xAD, 0x36, 0x85, 0xAD, 0x43, 0xFB, 0xB9, 0x6C, 0x6E, 0x82, 0xB7, 0x97, 0x26, 0xE5,
+	0xF9, 0xB6, 0xAB, 0x7F, 0x0D, 0x7E, 0x5E, 0x69, 0x3F, 0xB0, 0xB7, 0xFC, 0x1C, 0x5F, 0xFB, 0x06,
+	0x78, 0x62, 0xD7, 0xF6, 0x7F, 0xFD, 0x9D, 0x7F, 0x6A, 0x4D, 0x3B, 0xC5, 0xBE, 0x19, 0xD3, 0x55,
+	0x93, 0x4B, 0xBE, 0x5F, 0x0F, 0xF9, 0xCD, 0x14, 0x3B, 0xB7, 0x2A, 0xB3, 0x49, 0xF3, 0x57, 0xEE,
+	0x5C, 0xF4, 0xBB, 0x9B, 0xD6, 0xB2, 0xAD, 0x87, 0xA3, 0x88, 0xA7, 0xC9, 0x56, 0x2A, 0x4B, 0xB3,
+	0x2A, 0x32, 0x94, 0x76, 0x67, 0xE1, 0xCA, 0xF8, 0x7F, 0xFE, 0x0E, 0x9F, 0x6D, 0xC9, 0xFF, 0x00,
+	0x0B, 0x52, 0xC4, 0x2A, 0xFD, 0xEF, 0xF8, 0xA5, 0xE3, 0xF9, 0xA9, 0x7F, 0xE1, 0x1C, 0xFF, 0x00,
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+	0xA2, 0x5A, 0x00, 0xFD, 0xAE, 0x60, 0x00, 0xFF, 0xB6, 0x65, 0x00, 0xFF, 0xBE, 0x6D, 0x02, 0xFF,
+	0xC6, 0x7D, 0x1D, 0xFF, 0xCE, 0x92, 0x42, 0xFF, 0xD8, 0xA9, 0x6B, 0xFF, 0xE3, 0xC1, 0x95, 0xFF,
+	0xEB, 0xD3, 0xB5, 0xFF, 0xF1, 0xE0, 0xCC, 0xFF, 0xF5, 0xE7, 0xD7, 0xFF, 0xF5, 0xE7, 0xD5, 0xFF,
+	0xF6, 0xE7, 0xD4, 0xFF, 0xF5, 0xE7, 0xD5, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF,
+	0xF5, 0xE8, 0xD6, 0xFF, 0xF6, 0xE8, 0xD6, 0xFF, 0xF6, 0xE8, 0xD7, 0xFF, 0xF6, 0xE8, 0xD7, 0xFF,
+	0xF6, 0xE8, 0xD8, 0xFF, 0xF6, 0xE8, 0xD7, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF,
+	0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD5, 0xFF, 0xF4, 0xE6, 0xD4, 0xFF,
+	0xF4, 0xE5, 0xD3, 0xFF, 0xEF, 0xDC, 0xC3, 0xFF, 0xE6, 0xC8, 0xA2, 0xFF, 0xDB, 0xB1, 0x7B, 0xFF,
+	0xD1, 0x97, 0x4C, 0xFF, 0xC7, 0x81, 0x24, 0xFF, 0xC2, 0x74, 0x0C, 0xFF, 0xBC, 0x6B, 0x00, 0xFF,
+	0xB2, 0x63, 0x00, 0xFF, 0xA7, 0x5C, 0x00, 0xFF, 0x9E, 0x58, 0x00, 0xF9, 0x96, 0x55, 0x02, 0xF1,
+	0x92, 0x53, 0x03, 0xEF, 0x91, 0x53, 0x02, 0xEA, 0x8F, 0x52, 0x02, 0xBA, 0x8A, 0x4F, 0x02, 0x65,
+	0x7D, 0x48, 0x01, 0x2A, 0x2D, 0x1A, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x9A, 0x56, 0x00, 0xFB, 0x9E, 0x59, 0x00, 0xFF, 0xA1, 0x5C, 0x04, 0xFF, 0xA8, 0x64, 0x0B, 0xFF,
+	0xB6, 0x73, 0x1B, 0xFF, 0xC5, 0x83, 0x2B, 0xFF, 0xCE, 0x8C, 0x33, 0xFF, 0xD6, 0x94, 0x3D, 0xFF,
+	0xDD, 0xA4, 0x58, 0xFF, 0xE3, 0xB7, 0x7C, 0xFF, 0xEB, 0xCC, 0xA1, 0xFF, 0xF3, 0xE1, 0xC8, 0xFF,
+	0xF9, 0xF0, 0xE4, 0xFF, 0xFD, 0xFB, 0xF7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFD, 0xFC, 0xFA, 0xFF,
+	0xFC, 0xFA, 0xF6, 0xFF, 0xFB, 0xF8, 0xF4, 0xFF, 0xFB, 0xF7, 0xF3, 0xFF, 0xFB, 0xF7, 0xF2, 0xFF,
+	0xFB, 0xF7, 0xF1, 0xFF, 0xFB, 0xF6, 0xF0, 0xFF, 0xFA, 0xF5, 0xEE, 0xFF, 0xFA, 0xF5, 0xEE, 0xFF,
+	0xFB, 0xF5, 0xEF, 0xFF, 0xFB, 0xF6, 0xF1, 0xFF, 0xFB, 0xF7, 0xF3, 0xFF, 0xFB, 0xF7, 0xF3, 0xFF,
+	0xFB, 0xF7, 0xF3, 0xFF, 0xFB, 0xF8, 0xF4, 0xFF, 0xFC, 0xFA, 0xF7, 0xFF, 0xFD, 0xFC, 0xF9, 0xFF,
+	0xFF, 0xFE, 0xFD, 0xFF, 0xFC, 0xF8, 0xF1, 0xFF, 0xF5, 0xE7, 0xD3, 0xFF, 0xEE, 0xD2, 0xB0, 0xFF,
+	0xE5, 0xBC, 0x85, 0xFF, 0xDE, 0xA8, 0x60, 0xFF, 0xDA, 0x9C, 0x49, 0xFF, 0xD4, 0x92, 0x38, 0xFF,
+	0xCA, 0x87, 0x2E, 0xFF, 0xBD, 0x7C, 0x24, 0xFF, 0xB0, 0x6D, 0x14, 0xFF, 0xA3, 0x5E, 0x03, 0xFF,
+	0x9D, 0x58, 0x00, 0xFF, 0x9B, 0x57, 0x00, 0xFF, 0x97, 0x55, 0x00, 0xF2, 0x90, 0x52, 0x02, 0xA5,
+	0x89, 0x4F, 0x04, 0x6E, 0x88, 0x4E, 0x04, 0x4E, 0x88, 0x4E, 0x04, 0x31, 0x81, 0x4A, 0x04, 0x18,
+	0x62, 0x3B, 0x03, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x85, 0x4E, 0x03, 0x16, 0x8E, 0x53, 0x04, 0x55, 0x8F, 0x53, 0x04, 0x87,
+	0x90, 0x53, 0x05, 0xB0, 0x91, 0x53, 0x05, 0xCE, 0x93, 0x54, 0x04, 0xE2, 0x9B, 0x57, 0x01, 0xF2,
+	0xA9, 0x5D, 0x00, 0xFF, 0xB4, 0x64, 0x00, 0xFF, 0xBA, 0x6D, 0x07, 0xFF, 0xC3, 0x7D, 0x21, 0xFF,
+	0xD2, 0x9D, 0x56, 0xFF, 0xE0, 0xBB, 0x87, 0xFF, 0xE7, 0xC8, 0x9C, 0xFF, 0xEB, 0xCE, 0xA7, 0xFF,
+	0xEF, 0xD7, 0xB5, 0xFF, 0xF2, 0xDE, 0xC3, 0xFF, 0xF4, 0xE4, 0xCF, 0xFF, 0xF6, 0xEA, 0xD9, 0xFF,
+	0xF7, 0xEE, 0xE1, 0xFF, 0xF9, 0xF2, 0xE6, 0xFF, 0xF9, 0xF3, 0xE8, 0xFF, 0xF8, 0xF2, 0xE7, 0xFF,
+	0xF8, 0xF1, 0xE5, 0xFF, 0xF8, 0xF1, 0xE5, 0xFF, 0xF8, 0xF0, 0xE4, 0xFF, 0xF8, 0xF0, 0xE4, 0xFF,
+	0xF8, 0xF0, 0xE4, 0xFF, 0xF8, 0xF0, 0xE3, 0xFF, 0xF8, 0xF0, 0xE3, 0xFF, 0xF8, 0xF0, 0xE3, 0xFF,
+	0xF8, 0xF0, 0xE3, 0xFF, 0xF8, 0xF0, 0xE4, 0xFF, 0xF8, 0xF0, 0xE4, 0xFF, 0xF8, 0xF0, 0xE4, 0xFF,
+	0xF8, 0xF0, 0xE4, 0xFF, 0xF8, 0xF1, 0xE5, 0xFF, 0xF8, 0xF1, 0xE6, 0xFF, 0xF9, 0xF2, 0xE6, 0xFF,
+	0xF9, 0xF3, 0xE7, 0xFF, 0xF8, 0xF1, 0xE4, 0xFF, 0xF7, 0xEB, 0xDC, 0xFF, 0xF5, 0xE6, 0xD2, 0xFF,
+	0xF3, 0xE0, 0xC7, 0xFF, 0xF0, 0xDA, 0xBB, 0xFF, 0xEE, 0xD4, 0xB1, 0xFF, 0xEA, 0xCC, 0xA3, 0xFF,
+	0xE4, 0xC1, 0x91, 0xFF, 0xDB, 0xB0, 0x75, 0xFF, 0xCC, 0x90, 0x40, 0xFF, 0xBA, 0x6D, 0x06, 0xFF,
+	0xB1, 0x5F, 0x00, 0xFF, 0xAD, 0x5F, 0x00, 0xFF, 0xA3, 0x5B, 0x00, 0xFD, 0x95, 0x55, 0x03, 0xE7,
+	0x8E, 0x52, 0x06, 0xD4, 0x91, 0x53, 0x05, 0xC6, 0x92, 0x53, 0x05, 0xA0, 0x89, 0x4F, 0x04, 0x55,
+	0x6A, 0x3F, 0x03, 0x1A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x93, 0x54, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x41, 0x21, 0x03, 0x05,
+	0x80, 0x49, 0x05, 0x13, 0x8E, 0x52, 0x04, 0x49, 0x91, 0x54, 0x04, 0x93, 0x94, 0x56, 0x04, 0xCC,
+	0x98, 0x57, 0x04, 0xF7, 0x9B, 0x59, 0x04, 0xFF, 0x9E, 0x5A, 0x03, 0xFF, 0xA8, 0x61, 0x06, 0xFF,
+	0xBA, 0x6F, 0x0C, 0xFF, 0xC8, 0x7E, 0x1A, 0xFF, 0xD1, 0x8C, 0x30, 0xFF, 0xDA, 0x9F, 0x52, 0xFF,
+	0xE6, 0xC0, 0x8C, 0xFF, 0xF1, 0xDC, 0xC0, 0xFF, 0xF5, 0xE8, 0xD6, 0xFF, 0xF6, 0xED, 0xDF, 0xFF,
+	0xF8, 0xF0, 0xE5, 0xFF, 0xF8, 0xF1, 0xE5, 0xFF, 0xF8, 0xEF, 0xE3, 0xFF, 0xF7, 0xED, 0xDF, 0xFF,
+	0xF6, 0xEB, 0xDC, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF, 0xF5, 0xEA, 0xD9, 0xFF, 0xF5, 0xEB, 0xDA, 0xFF,
+	0xF6, 0xEB, 0xDA, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF,
+	0xF6, 0xEB, 0xDA, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF,
+	0xF6, 0xEB, 0xDA, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF,
+	0xF6, 0xEB, 0xDA, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF, 0xF5, 0xEB, 0xDA, 0xFF,
+	0xF5, 0xEA, 0xD9, 0xFF, 0xF6, 0xEB, 0xDB, 0xFF, 0xF7, 0xEC, 0xDE, 0xFF, 0xF8, 0xEE, 0xE1, 0xFF,
+	0xF9, 0xF1, 0xE6, 0xFF, 0xF9, 0xF3, 0xE8, 0xFF, 0xF8, 0xF1, 0xE5, 0xFF, 0xF6, 0xEB, 0xDC, 0xFF,
+	0xF3, 0xE2, 0xCA, 0xFF, 0xEE, 0xD3, 0xAD, 0xFF, 0xE1, 0xB3, 0x75, 0xFF, 0xD2, 0x8F, 0x35, 0xFF,
+	0xC8, 0x7D, 0x19, 0xFF, 0xC0, 0x75, 0x13, 0xFE, 0xB3, 0x6A, 0x0B, 0xFF, 0xA1, 0x5D, 0x04, 0xFF,
+	0x99, 0x57, 0x02, 0xFF, 0x99, 0x58, 0x04, 0xFF, 0x98, 0x57, 0x05, 0xE5, 0x91, 0x54, 0x05, 0x95,
+	0x85, 0x4E, 0x04, 0x51, 0x82, 0x4C, 0x05, 0x29, 0x89, 0x4D, 0x06, 0x0E, 0x81, 0x41, 0x0F, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7B, 0x45, 0x04, 0x2F,
+	0x8D, 0x51, 0x05, 0x70, 0x91, 0x53, 0x05, 0xA6, 0x94, 0x55, 0x05, 0xD4, 0x9B, 0x59, 0x04, 0xF2,
+	0xA4, 0x5E, 0x03, 0xFF, 0xAC, 0x62, 0x00, 0xFF, 0xB4, 0x64, 0x00, 0xFF, 0xBE, 0x72, 0x0D, 0xFF,
+	0xCD, 0x8D, 0x38, 0xFF, 0xDA, 0xA8, 0x64, 0xFF, 0xE5, 0xBE, 0x89, 0xFF, 0xEC, 0xD0, 0xA9, 0xFF,
+	0xF1, 0xDC, 0xC0, 0xFF, 0xF4, 0xE5, 0xD0, 0xFF, 0xF5, 0xE9, 0xD8, 0xFF, 0xF6, 0xEB, 0xDB, 0xFF,
+	0xF6, 0xEC, 0xDD, 0xFF, 0xF6, 0xEC, 0xDD, 0xFF, 0xF6, 0xEB, 0xDB, 0xFF, 0xF5, 0xE9, 0xD9, 0xFF,
+	0xF5, 0xE8, 0xD7, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD5, 0xFF, 0xF5, 0xE7, 0xD5, 0xFF,
+	0xF5, 0xE7, 0xD5, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF,
+	0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF,
+	0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF,
+	0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD6, 0xFF, 0xF5, 0xE7, 0xD5, 0xFF, 0xF5, 0xE7, 0xD5, 0xFF,
+	0xF5, 0xE7, 0xD5, 0xFF, 0xF5, 0xE8, 0xD6, 0xFF, 0xF5, 0xE8, 0xD8, 0xFF, 0xF6, 0xEA, 0xDA, 0xFF,
+	0xF6, 0xEC, 0xDD, 0xFF, 0xF7, 0xED, 0xDE, 0xFF, 0xF6, 0xEC, 0xDD, 0xFF, 0xF6, 0xEA, 0xD9, 0xFF,
+	0xF5, 0xE7, 0xD3, 0xFF, 0xF3, 0xE1, 0xC9, 0xFF, 0xEF, 0xD8, 0xB7, 0xFF, 0xE9, 0xCA, 0x9F, 0xFF,
+	0xE0, 0xB6, 0x7C, 0xFF, 0xD5, 0x9C, 0x51, 0xFF, 0xC7, 0x82, 0x28, 0xFF, 0xB7, 0x69, 0x01, 0xFF,
+	0xAD, 0x5D, 0x00, 0xFF, 0xA8, 0x5E, 0x00, 0xFF, 0xA2, 0x5E, 0x06, 0xFA, 0x98, 0x58, 0x06, 0xDF,
+	0x90, 0x53, 0x05, 0xB8, 0x8C, 0x50, 0x05, 0x81, 0x88, 0x4D, 0x06, 0x4B, 0x7F, 0x47, 0x08, 0x17,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xBF, 0x6A, 0x05, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x20, 0x12, 0x01, 0x03, 0x2E, 0x17, 0x00, 0x0A, 0x67, 0x3A, 0x03, 0x22, 0x89, 0x4E, 0x05, 0x69,
+	0x92, 0x54, 0x05, 0xBE, 0x97, 0x57, 0x05, 0xEA, 0x9C, 0x5A, 0x05, 0xFF, 0xA5, 0x60, 0x05, 0xFF,
+	0xB2, 0x68, 0x06, 0xFF, 0xBE, 0x71, 0x0A, 0xFF, 0xC9, 0x7B, 0x11, 0xFF, 0xD4, 0x8F, 0x30, 0xFF,
+	0xDE, 0xAD, 0x6A, 0xFF, 0xE8, 0xC9, 0x9F, 0xFF, 0xF1, 0xE0, 0xC8, 0xFF, 0xF7, 0xEE, 0xE0, 0xFF,
+	0xF6, 0xEC, 0xDD, 0xFF, 0xF4, 0xE6, 0xD4, 0xFF, 0xF4, 0xE6, 0xD2, 0xFF, 0xF4, 0xE6, 0xD1, 0xFF,
+	0xF4, 0xE6, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF,
+	0xF4, 0xE4, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF,
+	0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF,
+	0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF,
+	0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF,
+	0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF,
+	0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE4, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF,
+	0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF, 0xF4, 0xE5, 0xD0, 0xFF, 0xF4, 0xE5, 0xD1, 0xFF,
+	0xF4, 0xE6, 0xD2, 0xFF, 0xF4, 0xE8, 0xD5, 0xFF, 0xF6, 0xED, 0xDF, 0xFF, 0xF8, 0xF0, 0xE4, 0xFF,
+	0xF1, 0xDE, 0xC3, 0xFF, 0xE4, 0xBD, 0x88, 0xFF, 0xD9, 0x9F, 0x52, 0xFF, 0xCE, 0x83, 0x1D, 0xFF,
+	0xC3, 0x71, 0x03, 0xFF, 0xB8, 0x6B, 0x05, 0xFF, 0xAD, 0x65, 0x07, 0xFF, 0xA1, 0x5E, 0x06, 0xFF,
+	0x99, 0x59, 0x05, 0xFF, 0x93, 0x55, 0x05, 0xCA, 0x8D, 0x51, 0x06, 0x8A, 0x8B, 0x50, 0x06, 0x45,
+	0x95, 0x56, 0x04, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x07, 0x81, 0x4B, 0x03, 0x43, 0x8F, 0x53, 0x04, 0x89, 0x93, 0x56, 0x05, 0xBE,
+	0x97, 0x59, 0x05, 0xE7, 0xA2, 0x5E, 0x04, 0xFD, 0xB0, 0x65, 0x03, 0xFF, 0xB9, 0x6C, 0x06, 0xFF,
+	0xC0, 0x74, 0x0E, 0xFF, 0xCC, 0x88, 0x2D, 0xFF, 0xDD, 0xA9, 0x62, 0xFF, 0xE8, 0xC1, 0x8A, 0xFF,
+	0xEC, 0xCD, 0xA4, 0xFF, 0xEF, 0xD8, 0xBA, 0xFF, 0xF3, 0xE4, 0xCE, 0xFF, 0xF6, 0xEB, 0xDA, 0xFF,
+	0xF5, 0xE8, 0xD6, 0xFF, 0xF3, 0xE4, 0xCF, 0xFF, 0xF3, 0xE3, 0xCD, 0xFF, 0xF3, 0xE3, 0xCD, 0xFF,
+	0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE2, 0xCC, 0xFF, 0xF3, 0xE2, 0xCC, 0xFF,
+	0xF3, 0xE2, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF,
+	0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF,
+	0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF,
+	0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF,
+	0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF,
+	0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF,
+	0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE2, 0xCC, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF,
+	0xF3, 0xE4, 0xCE, 0xFF, 0xF4, 0xE5, 0xD0, 0xFF, 0xF5, 0xE9, 0xD8, 0xFF, 0xF7, 0xEC, 0xDD, 0xFF,
+	0xF4, 0xE4, 0xCE, 0xFF, 0xEE, 0xD4, 0xB0, 0xFF, 0xE8, 0xC4, 0x93, 0xFF, 0xE2, 0xB3, 0x75, 0xFF,
+	0xD7, 0x9C, 0x4D, 0xFF, 0xC6, 0x7D, 0x1B, 0xFF, 0xB9, 0x6A, 0x00, 0xFF, 0xB1, 0x66, 0x01, 0xFF,
+	0xAA, 0x63, 0x05, 0xFF, 0x9D, 0x5C, 0x05, 0xF0, 0x92, 0x55, 0x05, 0xCC, 0x91, 0x54, 0x04, 0x9C,
+	0x95, 0x56, 0x04, 0x66, 0x89, 0x4E, 0x03, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x0B, 0x01, 0x03, 0x00, 0x00, 0x00, 0x06,
+	0x5E, 0x37, 0x03, 0x24, 0x8E, 0x53, 0x05, 0x85, 0x98, 0x59, 0x05, 0xE7, 0x9B, 0x5B, 0x05, 0xFF,
+	0xA0, 0x5F, 0x06, 0xFF, 0xAF, 0x67, 0x05, 0xFF, 0xC3, 0x73, 0x07, 0xFF, 0xCC, 0x7D, 0x11, 0xFF,
+	0xCE, 0x86, 0x25, 0xFF, 0xD8, 0xA3, 0x58, 0xFF, 0xEB, 0xD1, 0xAB, 0xFF, 0xF5, 0xE8, 0xD5, 0xFF,
+	0xF4, 0xE4, 0xCE, 0xFF, 0xF2, 0xDF, 0xC6, 0xFF, 0xF2, 0xDF, 0xC6, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF,
+	0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF,
+	0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF,
+	0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF,
+	0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF,
+	0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF,
+	0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF,
+	0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF,
+	0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF, 0xF2, 0xE1, 0xC7, 0xFF,
+	0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF,
+	0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF,
+	0xF2, 0xE1, 0xC8, 0xFF, 0xF2, 0xE2, 0xC9, 0xFF, 0xF2, 0xE0, 0xC7, 0xFF, 0xF0, 0xDC, 0xC1, 0xFF,
+	0xE7, 0xC4, 0x95, 0xFF, 0xD4, 0x95, 0x40, 0xFF, 0xC7, 0x78, 0x0C, 0xFF, 0xC3, 0x73, 0x06, 0xFF,
+	0xBB, 0x6F, 0x07, 0xFF, 0xA9, 0x63, 0x06, 0xFF, 0x9A, 0x5A, 0x05, 0xFE, 0x97, 0x58, 0x04, 0xE8,
+	0x96, 0x57, 0x04, 0xBE, 0x8D, 0x52, 0x04, 0x6C, 0x4F, 0x2F, 0x03, 0x17, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x58, 0x33, 0x03, 0x17, 0x81, 0x4C, 0x05, 0x4A,
+	0x8E, 0x54, 0x06, 0x85, 0x98, 0x5A, 0x07, 0xC8, 0xA0, 0x5E, 0x07, 0xFF, 0xA7, 0x62, 0x04, 0xFF,
+	0xB0, 0x67, 0x03, 0xFF, 0xBC, 0x71, 0x09, 0xFF, 0xCB, 0x7F, 0x16, 0xFF, 0xD5, 0x92, 0x35, 0xFF,
+	0xDD, 0xA9, 0x62, 0xFF, 0xE6, 0xC2, 0x90, 0xFF, 0xF0, 0xDD, 0xC1, 0xFF, 0xF5, 0xE9, 0xD7, 0xFF,
+	0xF3, 0xE4, 0xCE, 0xFF, 0xF2, 0xDF, 0xC6, 0xFF, 0xF1, 0xDD, 0xC3, 0xFF, 0xF1, 0xDD, 0xC2, 0xFF,
+	0xF1, 0xDD, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF,
+	0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF,
+	0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF,
+	0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF,
+	0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF,
+	0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF,
+	0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF,
+	0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF,
+	0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF,
+	0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDE, 0xC2, 0xFF, 0xF1, 0xDD, 0xC2, 0xFF, 0xF1, 0xDD, 0xC2, 0xFF,
+	0xF1, 0xDE, 0xC5, 0xFF, 0xF2, 0xE1, 0xC9, 0xFF, 0xF3, 0xE3, 0xCC, 0xFF, 0xF3, 0xE2, 0xCC, 0xFF,
+	0xED, 0xD5, 0xB2, 0xFF, 0xE3, 0xB9, 0x7F, 0xFF, 0xD8, 0x9F, 0x4E, 0xFF, 0xCD, 0x85, 0x21, 0xFE,
+	0xC2, 0x73, 0x05, 0xFF, 0xB6, 0x6B, 0x03, 0xFF, 0xAC, 0x66, 0x06, 0xFF, 0xA1, 0x5F, 0x06, 0xFE,
+	0x98, 0x59, 0x05, 0xE8, 0x92, 0x56, 0x04, 0xB6, 0x8C, 0x54, 0x03, 0x79, 0x80, 0x4D, 0x03, 0x3F,
+	0x31, 0x18, 0x02, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x51, 0x37, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x06, 0x36, 0x1E, 0x02, 0x14, 0x72, 0x43, 0x05, 0x3E, 0x90, 0x55, 0x06, 0x9C,
+	0x9A, 0x5B, 0x07, 0xEE, 0xA1, 0x60, 0x08, 0xFF, 0xAB, 0x66, 0x09, 0xFE, 0xB6, 0x6B, 0x05, 0xFF,
+	0xC2, 0x72, 0x04, 0xFF, 0xCA, 0x7E, 0x13, 0xFF, 0xD0, 0x8D, 0x30, 0xFF, 0xDB, 0xA9, 0x62, 0xFF,
+	0xE9, 0xCC, 0xA2, 0xFF, 0xF0, 0xDD, 0xC1, 0xFF, 0xF0, 0xDD, 0xC1, 0xFF, 0xF0, 0xDC, 0xBF, 0xFF,
+	0xEF, 0xDB, 0xBF, 0xFF, 0xEF, 0xDA, 0xBE, 0xFF, 0xEF, 0xDA, 0xBE, 0xFF, 0xEF, 0xDB, 0xBE, 0xFF,
+	0xF0, 0xDC, 0xBE, 0xFF, 0xF0, 0xDC, 0xBE, 0xFF, 0xF0, 0xDC, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF,
+	0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF,
+	0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF,
+	0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF,
+	0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF,
+	0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF,
+	0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF,
+	0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF,
+	0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF,
+	0xF0, 0xDC, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xF0, 0xDB, 0xBE, 0xFF, 0xEF, 0xDB, 0xBE, 0xFF,
+	0xEF, 0xDA, 0xBE, 0xFF, 0xEF, 0xDB, 0xBE, 0xFF, 0xEF, 0xDB, 0xBF, 0xFF, 0xEF, 0xDC, 0xBF, 0xFF,
+	0xEF, 0xDB, 0xBD, 0xFF, 0xEF, 0xDB, 0xBD, 0xFF, 0xE8, 0xC8, 0x9A, 0xFF, 0xD5, 0x9B, 0x48, 0xFF,
+	0xC7, 0x7A, 0x0D, 0xFF, 0xC5, 0x76, 0x06, 0xFF, 0xC0, 0x74, 0x0A, 0xFF, 0xAE, 0x68, 0x08, 0xFF,
+	0x9C, 0x5D, 0x07, 0xFC, 0x97, 0x5A, 0x05, 0xF9, 0x95, 0x5A, 0x04, 0xE5, 0x8F, 0x55, 0x04, 0x91,
+	0x67, 0x3A, 0x04, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x05,
+	0x5F, 0x37, 0x04, 0x1C, 0x81, 0x4C, 0x06, 0x50, 0x90, 0x55, 0x07, 0x8D, 0x9C, 0x5C, 0x07, 0xD6,
+	0xA4, 0x62, 0x08, 0xFF, 0xAD, 0x67, 0x08, 0xFF, 0xB7, 0x6E, 0x09, 0xFF, 0xC1, 0x75, 0x0A, 0xFF,
+	0xCB, 0x7E, 0x11, 0xFF, 0xD4, 0x90, 0x32, 0xFF, 0xDC, 0xA9, 0x61, 0xFF, 0xE5, 0xC1, 0x8E, 0xFF,
+	0xEE, 0xD8, 0xB8, 0xFF, 0xF1, 0xE1, 0xC8, 0xFF, 0xEF, 0xDB, 0xBE, 0xFF, 0xEE, 0xD8, 0xB8, 0xFF,
+	0xEE, 0xD8, 0xB9, 0xFF, 0xEE, 0xD8, 0xBA, 0xFF, 0xEE, 0xD8, 0xB9, 0xFF, 0xEE, 0xD9, 0xB9, 0xFF,
+	0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xDA, 0xB9, 0xFF, 0xEF, 0xDA, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF,
+	0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF,
+	0xEF, 0xDA, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF,
+	0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF,
+	0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF,
+	0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF,
+	0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF,
+	0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF,
+	0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF,
+	0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEF, 0xD9, 0xB9, 0xFF, 0xEE, 0xD9, 0xB9, 0xFF,
+	0xEE, 0xD8, 0xB9, 0xFF, 0xEE, 0xD8, 0xB9, 0xFF, 0xEE, 0xD9, 0xB9, 0xFF, 0xEE, 0xD9, 0xBA, 0xFF,
+	0xEF, 0xDC, 0xBE, 0xFF, 0xF2, 0xE1, 0xC8, 0xFF, 0xEE, 0xD6, 0xB4, 0xFF, 0xE1, 0xB6, 0x79, 0xFF,
+	0xD5, 0x99, 0x44, 0xFF, 0xD0, 0x88, 0x22, 0xFF, 0xC8, 0x7A, 0x0D, 0xFF, 0xBB, 0x70, 0x08, 0xFF,
+	0xAD, 0x68, 0x09, 0xFF, 0xA3, 0x62, 0x07, 0xFF, 0x9C, 0x5D, 0x06, 0xFF, 0x96, 0x5A, 0x05, 0xC8,
+	0x8B, 0x53, 0x06, 0x70, 0x7A, 0x49, 0x07, 0x33, 0x1E, 0x13, 0x02, 0x08, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x0D, 0x01, 0x08, 0x2C, 0x17, 0x02, 0x14,
+	0x75, 0x44, 0x06, 0x41, 0x92, 0x56, 0x07, 0xA2, 0x9D, 0x5D, 0x08, 0xED, 0xA8, 0x64, 0x09, 0xFF,
+	0xB3, 0x6B, 0x09, 0xFF, 0xBC, 0x70, 0x07, 0xFF, 0xC5, 0x76, 0x09, 0xFF, 0xCB, 0x7F, 0x14, 0xFF,
+	0xD0, 0x8B, 0x29, 0xFF, 0xDC, 0xA7, 0x5C, 0xFF, 0xE9, 0xC9, 0x9C, 0xFF, 0xEE, 0xD7, 0xB6, 0xFF,
+	0xEE, 0xD7, 0xB6, 0xFF, 0xEE, 0xD7, 0xB6, 0xFF, 0xED, 0xD6, 0xB5, 0xFF, 0xED, 0xD6, 0xB4, 0xFF,
+	0xED, 0xD6, 0xB4, 0xFF, 0xED, 0xD7, 0xB5, 0xFF, 0xED, 0xD7, 0xB5, 0xFF, 0xED, 0xD7, 0xB5, 0xFF,
+	0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD7, 0xB5, 0xFF,
+	0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF,
+	0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF,
+	0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF,
+	0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF,
+	0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF,
+	0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF,
+	0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF, 0xEE, 0xD8, 0xB5, 0xFF,
+	0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD7, 0xB5, 0xFF,
+	0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD7, 0xB5, 0xFF, 0xED, 0xD7, 0xB5, 0xFF,
+	0xED, 0xD7, 0xB5, 0xFF, 0xED, 0xD7, 0xB4, 0xFF, 0xED, 0xD7, 0xB4, 0xFF, 0xED, 0xD6, 0xB4, 0xFF,
+	0xEE, 0xD7, 0xB5, 0xFF, 0xEE, 0xD8, 0xB7, 0xFF, 0xED, 0xD6, 0xB4, 0xFF, 0xEC, 0xD2, 0xAD, 0xFF,
+	0xE7, 0xC2, 0x90, 0xFF, 0xD8, 0x9E, 0x4D, 0xFF, 0xCB, 0x7F, 0x15, 0xFF, 0xC8, 0x78, 0x0A, 0xFF,
+	0xC3, 0x76, 0x0B, 0xFF, 0xB5, 0x6D, 0x09, 0xFF, 0xA5, 0x63, 0x08, 0xFF, 0x9D, 0x5E, 0x07, 0xF1,
+	0x97, 0x5B, 0x07, 0xCF, 0x91, 0x58, 0x06, 0x80, 0x68, 0x40, 0x04, 0x17, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x6C, 0x3F, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3B, 0x23, 0x03, 0x13, 0x76, 0x47, 0x07, 0x41,
+	0x8C, 0x54, 0x08, 0x7F, 0x9A, 0x5C, 0x08, 0xD7, 0xA3, 0x62, 0x09, 0xFF, 0xB0, 0x6A, 0x0A, 0xFF,
+	0xBE, 0x73, 0x0B, 0xFF, 0xC5, 0x76, 0x06, 0xFE, 0xCA, 0x7B, 0x09, 0xFF, 0xD2, 0x8B, 0x28, 0xFF,
+	0xDA, 0xA2, 0x53, 0xFF, 0xE4, 0xBC, 0x84, 0xFF, 0xEE, 0xD6, 0xB3, 0xFF, 0xF1, 0xDD, 0xC0, 0xFF,
+	0xEE, 0xD6, 0xB3, 0xFF, 0xEC, 0xD3, 0xAE, 0xFF, 0xED, 0xD3, 0xAF, 0xFF, 0xED, 0xD4, 0xAF, 0xFF,
+	0xED, 0xD4, 0xB0, 0xFF, 0xED, 0xD5, 0xB0, 0xFF, 0xED, 0xD5, 0xB0, 0xFF, 0xED, 0xD5, 0xB0, 0xFF,
+	0xED, 0xD5, 0xB0, 0xFF, 0xED, 0xD5, 0xB0, 0xFF, 0xEE, 0xD5, 0xB0, 0xFF, 0xEE, 0xD5, 0xB1, 0xFF,
+	0xEE, 0xD5, 0xB0, 0xFF, 0xEE, 0xD5, 0xB0, 0xFF, 0xEE, 0xD5, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF,
+	0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF,
+	0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF,
+	0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF,
+	0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF,
+	0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF,
+	0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF, 0xEE, 0xD6, 0xB0, 0xFF,
+	0xEE, 0xD5, 0xB0, 0xFF, 0xEE, 0xD5, 0xB0, 0xFF, 0xEE, 0xD5, 0xB0, 0xFF, 0xEE, 0xD5, 0xB0, 0xFF,
+	0xEE, 0xD5, 0xB0, 0xFF, 0xED, 0xD5, 0xB0, 0xFF, 0xED, 0xD5, 0xB0, 0xFF, 0xED, 0xD5, 0xB0, 0xFF,
+	0xED, 0xD5, 0xB0, 0xFF, 0xED, 0xD5, 0xAF, 0xFF, 0xED, 0xD4, 0xAF, 0xFF, 0xED, 0xD4, 0xAF, 0xFF,
+	0xED, 0xD4, 0xAF, 0xFF, 0xED, 0xD4, 0xAF, 0xFF, 0xED, 0xD5, 0xB2, 0xFF, 0xF0, 0xDB, 0xBD, 0xFF,
+	0xEE, 0xD3, 0xAF, 0xFF, 0xE0, 0xB1, 0x70, 0xFF, 0xD3, 0x92, 0x36, 0xFF, 0xD0, 0x84, 0x1A, 0xFF,
+	0xCC, 0x7C, 0x0B, 0xFF, 0xC1, 0x73, 0x07, 0xFF, 0xB3, 0x6C, 0x0A, 0xFF, 0xA7, 0x65, 0x09, 0xFF,
+	0x9D, 0x5F, 0x08, 0xFC, 0x97, 0x5B, 0x07, 0xB9, 0x8F, 0x55, 0x07, 0x51, 0x73, 0x41, 0x06, 0x19,
+	0x21, 0x10, 0x01, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4C, 0x2D, 0x04, 0x23, 0x8E, 0x56, 0x08, 0x88,
+	0x99, 0x5D, 0x09, 0xD4, 0xA1, 0x62, 0x09, 0xF6, 0xAB, 0x68, 0x0A, 0xFF, 0xBA, 0x71, 0x0B, 0xFF,
+	0xC7, 0x7A, 0x0C, 0xFF, 0xC9, 0x78, 0x04, 0xFF, 0xCA, 0x7B, 0x0A, 0xFF, 0xD7, 0x9A, 0x44, 0xFF,
+	0xE6, 0xC1, 0x8D, 0xFF, 0xEC, 0xD1, 0xAA, 0xFF, 0xED, 0xD3, 0xAF, 0xFF, 0xEE, 0xD4, 0xB0, 0xFF,
+	0xED, 0xD2, 0xAC, 0xFF, 0xEC, 0xD1, 0xAA, 0xFF, 0xEC, 0xD2, 0xAB, 0xFF, 0xEC, 0xD2, 0xAB, 0xFF,
+	0xEC, 0xD2, 0xAB, 0xFF, 0xEC, 0xD2, 0xAB, 0xFF, 0xEC, 0xD2, 0xAB, 0xFF, 0xEC, 0xD2, 0xAB, 0xFF,
+	0xEC, 0xD2, 0xAB, 0xFF, 0xEC, 0xD2, 0xAB, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAD, 0xFF,
+	0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF,
+	0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF,
+	0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF,
+	0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF,
+	0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF,
+	0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF,
+	0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF,
+	0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF, 0xED, 0xD3, 0xAC, 0xFF,
+	0xED, 0xD3, 0xAB, 0xFF, 0xED, 0xD2, 0xAB, 0xFF, 0xEC, 0xD2, 0xAB, 0xFF, 0xEC, 0xD2, 0xAB, 0xFF,
+	0xEC, 0xD2, 0xAB, 0xFF, 0xEC, 0xD2, 0xAB, 0xFF, 0xEC, 0xD2, 0xAB, 0xFF, 0xEC, 0xD2, 0xAB, 0xFF,
+	0xEC, 0xD2, 0xAB, 0xFF, 0xEC, 0xD1, 0xAB, 0xFF, 0xED, 0xD2, 0xAC, 0xFF, 0xEE, 0xD5, 0xB1, 0xFF,
+	0xED, 0xD1, 0xAA, 0xFF, 0xE7, 0xC4, 0x91, 0xFF, 0xDF, 0xB0, 0x6D, 0xFF, 0xD4, 0x93, 0x36, 0xFF,
+	0xCA, 0x7A, 0x08, 0xFF, 0xC8, 0x76, 0x03, 0xFF, 0xC5, 0x78, 0x0D, 0xFF, 0xB5, 0x6F, 0x0C, 0xFF,
+	0xA3, 0x62, 0x0A, 0xFF, 0x9B, 0x5D, 0x08, 0xE3, 0x99, 0x5A, 0x08, 0xB0, 0x92, 0x56, 0x07, 0x6E,
+	0x67, 0x3B, 0x05, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x11, 0x0A, 0x03, 0x0A, 0x42, 0x28, 0x06, 0x1E, 0x7F, 0x4D, 0x08, 0x57, 0x98, 0x5C, 0x09, 0xC0,
+	0xA1, 0x62, 0x0A, 0xFF, 0xAB, 0x68, 0x0B, 0xFF, 0xB6, 0x70, 0x0C, 0xFF, 0xC2, 0x77, 0x0B, 0xFF,
+	0xCB, 0x7E, 0x0D, 0xFF, 0xCD, 0x80, 0x10, 0xFF, 0xCF, 0x88, 0x22, 0xFF, 0xDC, 0xAA, 0x62, 0xFF,
+	0xEC, 0xD1, 0xAA, 0xFF, 0xF0, 0xD9, 0xB9, 0xFF, 0xEC, 0xD0, 0xA9, 0xFF, 0xEB, 0xCE, 0xA5, 0xFF,
+	0xEC, 0xCF, 0xA6, 0xFF, 0xEC, 0xCF, 0xA6, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF,
+	0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF,
+	0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA8, 0xFF,
+	0xED, 0xD1, 0xA8, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF,
+	0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF,
+	0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF,
+	0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF,
+	0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF,
+	0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF,
+	0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF,
+	0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF, 0xED, 0xD1, 0xA7, 0xFF,
+	0xEC, 0xD1, 0xA7, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF,
+	0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF,
+	0xEC, 0xD0, 0xA6, 0xFF, 0xEC, 0xCF, 0xA6, 0xFF, 0xEC, 0xCF, 0xA6, 0xFF, 0xEC, 0xD0, 0xA7, 0xFF,
+	0xEC, 0xCF, 0xA5, 0xFF, 0xEB, 0xCE, 0xA3, 0xFF, 0xE6, 0xC4, 0x8F, 0xFF, 0xD9, 0xA2, 0x51, 0xFF,
+	0xCC, 0x81, 0x15, 0xFF, 0xCD, 0x7C, 0x09, 0xFF, 0xCE, 0x7F, 0x0E, 0xFF, 0xC0, 0x76, 0x0C, 0xFF,
+	0xAD, 0x69, 0x0B, 0xFF, 0xA3, 0x62, 0x0A, 0xFD, 0x9D, 0x5E, 0x09, 0xEC, 0x96, 0x59, 0x08, 0xAD,
+	0x7D, 0x4A, 0x07, 0x46, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x6F, 0x45, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x5E, 0x3A, 0x08, 0x23, 0x8D, 0x57, 0x0A, 0x77, 0x98, 0x5D, 0x0A, 0xBA, 0xA0, 0x61, 0x0A, 0xEA,
+	0xAA, 0x67, 0x0A, 0xFF, 0xB8, 0x71, 0x0C, 0xFF, 0xC4, 0x7A, 0x0E, 0xFF, 0xC8, 0x7A, 0x08, 0xFF,
+	0xCB, 0x7E, 0x0E, 0xFF, 0xD2, 0x90, 0x2E, 0xFF, 0xDA, 0xA6, 0x57, 0xFF, 0xE3, 0xBB, 0x80, 0xFF,
+	0xEB, 0xCE, 0xA4, 0xFF, 0xED, 0xD2, 0xAB, 0xFF, 0xEB, 0xCD, 0xA2, 0xFF, 0xEB, 0xCD, 0xA0, 0xFF,
+	0xEB, 0xCD, 0xA1, 0xFF, 0xEB, 0xCE, 0xA2, 0xFF, 0xEB, 0xCE, 0xA2, 0xFF, 0xEB, 0xCE, 0xA2, 0xFF,
+	0xEB, 0xCE, 0xA2, 0xFF, 0xEB, 0xCE, 0xA2, 0xFF, 0xEB, 0xCE, 0xA1, 0xFF, 0xEB, 0xCE, 0xA2, 0xFF,
+	0xEB, 0xCE, 0xA2, 0xFF, 0xEB, 0xCE, 0xA2, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF,
+	0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF,
+	0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF,
+	0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF,
+	0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF,
+	0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF,
+	0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF,
+	0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF,
+	0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF, 0xEC, 0xCF, 0xA3, 0xFF,
+	0xEB, 0xCF, 0xA3, 0xFF, 0xEB, 0xCE, 0xA2, 0xFF, 0xEB, 0xCE, 0xA2, 0xFF, 0xEB, 0xCF, 0xA2, 0xFF,
+	0xEB, 0xCE, 0xA1, 0xFF, 0xEB, 0xCE, 0xA2, 0xFF, 0xEB, 0xCE, 0xA2, 0xFF, 0xEB, 0xCE, 0xA2, 0xFF,
+	0xEB, 0xCE, 0xA1, 0xFF, 0xEB, 0xCD, 0xA1, 0xFF, 0xEB, 0xCD, 0xA1, 0xFF, 0xEB, 0xCD, 0xA1, 0xFF,
+	0xEB, 0xCD, 0xA1, 0xFF, 0xEC, 0xD0, 0xA6, 0xFF, 0xE9, 0xCA, 0x9B, 0xFF, 0xDE, 0xB0, 0x6A, 0xFF,
+	0xD3, 0x94, 0x36, 0xFF, 0xCF, 0x87, 0x1C, 0xFF, 0xCD, 0x7F, 0x0E, 0xFF, 0xC7, 0x79, 0x0A, 0xFF,
+	0xBE, 0x75, 0x0C, 0xFF, 0xB1, 0x6C, 0x0C, 0xFF, 0xA1, 0x61, 0x0A, 0xFF, 0x96, 0x5B, 0x09, 0xD1,
+	0x89, 0x53, 0x08, 0x7C, 0x74, 0x46, 0x08, 0x3B, 0x52, 0x32, 0x06, 0x10, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x0A,
+	0x7B, 0x4C, 0x08, 0x4A, 0x97, 0x5D, 0x0B, 0xBE, 0xA0, 0x62, 0x0B, 0xFF, 0xA9, 0x67, 0x0B, 0xFF,
+	0xB4, 0x6E, 0x0C, 0xFF, 0xC3, 0x79, 0x0E, 0xFF, 0xCE, 0x80, 0x0F, 0xFF, 0xCC, 0x7D, 0x08, 0xFF,
+	0xCC, 0x80, 0x11, 0xFF, 0xD7, 0x9D, 0x46, 0xFF, 0xE3, 0xBC, 0x80, 0xFF, 0xE8, 0xC7, 0x95, 0xFF,
+	0xEA, 0xCA, 0x9B, 0xFF, 0xEA, 0xCB, 0x9E, 0xFF, 0xEA, 0xCB, 0x9C, 0xFF, 0xEA, 0xCB, 0x9C, 0xFF,
+	0xEA, 0xCB, 0x9D, 0xFF, 0xEA, 0xCC, 0x9D, 0xFF, 0xEA, 0xCC, 0x9D, 0xFF, 0xEA, 0xCC, 0x9D, 0xFF,
+	0xEA, 0xCC, 0x9D, 0xFF, 0xEA, 0xCC, 0x9D, 0xFF, 0xEA, 0xCC, 0x9D, 0xFF, 0xEA, 0xCD, 0x9D, 0xFF,
+	0xEA, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF,
+	0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF,
+	0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF,
+	0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCE, 0x9E, 0xFF,
+	0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCE, 0x9E, 0xFF,
+	0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCE, 0x9E, 0xFF,
+	0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCE, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF,
+	0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF,
+	0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF, 0xEB, 0xCD, 0x9E, 0xFF,
+	0xEA, 0xCD, 0x9E, 0xFF, 0xEA, 0xCD, 0x9E, 0xFF, 0xEA, 0xCD, 0x9E, 0xFF, 0xEA, 0xCD, 0x9D, 0xFF,
+	0xEA, 0xCC, 0x9D, 0xFF, 0xEA, 0xCC, 0x9D, 0xFF, 0xEA, 0xCC, 0x9D, 0xFF, 0xEA, 0xCC, 0x9D, 0xFF,
+	0xEA, 0xCB, 0x9D, 0xFF, 0xEA, 0xCB, 0x9C, 0xFF, 0xEA, 0xCB, 0x9C, 0xFF, 0xEA, 0xCA, 0x9C, 0xFF,
+	0xEA, 0xCB, 0x9D, 0xFF, 0xEB, 0xCF, 0xA4, 0xFF, 0xEA, 0xCC, 0x9F, 0xFF, 0xE3, 0xBB, 0x7F, 0xFF,
+	0xDB, 0xA6, 0x58, 0xFF, 0xD3, 0x92, 0x31, 0xFF, 0xCC, 0x80, 0x11, 0xFF, 0xCB, 0x7C, 0x09, 0xFF,
+	0xCB, 0x7D, 0x0E, 0xFF, 0xBD, 0x75, 0x0D, 0xFF, 0xA8, 0x67, 0x0B, 0xFF, 0x9C, 0x60, 0x0A, 0xEB,
+	0x94, 0x5A, 0x09, 0xB1, 0x8A, 0x54, 0x09, 0x72, 0x7A, 0x4A, 0x08, 0x2C, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x62, 0x3B, 0x03, 0x14, 0x78, 0x49, 0x05, 0x41,
+	0x8D, 0x56, 0x08, 0x84, 0x9A, 0x5F, 0x0A, 0xDC, 0xA5, 0x66, 0x0B, 0xFF, 0xB4, 0x6F, 0x0C, 0xFF,
+	0xC1, 0x77, 0x0D, 0xFF, 0xC9, 0x7D, 0x0E, 0xFF, 0xCE, 0x81, 0x10, 0xFF, 0xCD, 0x7E, 0x0A, 0xFF,
+	0xCE, 0x84, 0x16, 0xFF, 0xDA, 0xA4, 0x52, 0xFF, 0xE7, 0xC4, 0x8F, 0xFF, 0xEA, 0xCC, 0x9D, 0xFF,
+	0xE9, 0xC9, 0x98, 0xFF, 0xE9, 0xC9, 0x98, 0xFF, 0xE9, 0xC9, 0x98, 0xFF, 0xE9, 0xC9, 0x98, 0xFF,
+	0xE9, 0xC9, 0x98, 0xFF, 0xE9, 0xC9, 0x99, 0xFF, 0xE9, 0xCA, 0x99, 0xFF, 0xE9, 0xCA, 0x99, 0xFF,
+	0xEA, 0xCA, 0x99, 0xFF, 0xEA, 0xCA, 0x99, 0xFF, 0xEA, 0xCA, 0x99, 0xFF, 0xE9, 0xCB, 0x99, 0xFF,
+	0xEA, 0xCB, 0x99, 0xFF, 0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x99, 0xFF, 0xEA, 0xCB, 0x99, 0xFF,
+	0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x9A, 0xFF,
+	0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF,
+	0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF,
+	0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF,
+	0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF,
+	0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF, 0xEA, 0xCC, 0x9A, 0xFF,
+	0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x9A, 0xFF,
+	0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x9A, 0xFF, 0xEA, 0xCB, 0x99, 0xFF,
+	0xEA, 0xCB, 0x99, 0xFF, 0xE9, 0xCB, 0x9A, 0xFF, 0xE9, 0xCB, 0x99, 0xFF, 0xE9, 0xCA, 0x99, 0xFF,
+	0xE9, 0xCA, 0x99, 0xFF, 0xE9, 0xCA, 0x99, 0xFF, 0xE9, 0xCA, 0x99, 0xFF, 0xE9, 0xCA, 0x99, 0xFF,
+	0xE9, 0xCA, 0x99, 0xFF, 0xE9, 0xC9, 0x98, 0xFF, 0xE9, 0xC9, 0x98, 0xFF, 0xE9, 0xC9, 0x98, 0xFF,
+	0xE9, 0xC9, 0x98, 0xFF, 0xE9, 0xCB, 0x9C, 0xFF, 0xE9, 0xCA, 0x9B, 0xFF, 0xE6, 0xC5, 0x90, 0xFF,
+	0xE2, 0xB8, 0x7A, 0xFF, 0xD8, 0x9E, 0x48, 0xFF, 0xCD, 0x84, 0x16, 0xFF, 0xCC, 0x7D, 0x09, 0xFF,
+	0xCD, 0x80, 0x0F, 0xFF, 0xC5, 0x7A, 0x0E, 0xFF, 0xB8, 0x72, 0x0D, 0xFF, 0xAC, 0x6B, 0x0C, 0xFB,
+	0xA1, 0x63, 0x0B, 0xE5, 0x97, 0x5D, 0x0A, 0xB1, 0x87, 0x52, 0x08, 0x5A, 0x58, 0x32, 0x02, 0x1F,
+	0x29, 0x14, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x4E, 0x07, 0x2D, 0x8F, 0x57, 0x08, 0x7F,
+	0x98, 0x5D, 0x09, 0xBD, 0xA0, 0x63, 0x0A, 0xED, 0xAC, 0x6B, 0x0C, 0xFF, 0xBF, 0x77, 0x0E, 0xFF,
+	0xCC, 0x7F, 0x0F, 0xFF, 0xCD, 0x7F, 0x0E, 0xFF, 0xCC, 0x80, 0x11, 0xFF, 0xCD, 0x83, 0x13, 0xFF,
+	0xD1, 0x8D, 0x24, 0xFF, 0xDC, 0xAA, 0x5C, 0xFF, 0xE7, 0xC7, 0x93, 0xFF, 0xEA, 0xCC, 0x9D, 0xFF,
+	0xE8, 0xC7, 0x95, 0xFF, 0xE8, 0xC7, 0x94, 0xFF, 0xE8, 0xC7, 0x94, 0xFF, 0xE8, 0xC7, 0x94, 0xFF,
+	0xE8, 0xC7, 0x94, 0xFF, 0xE8, 0xC7, 0x94, 0xFF, 0xE8, 0xC8, 0x95, 0xFF, 0xE8, 0xC8, 0x95, 0xFF,
+	0xE9, 0xC8, 0x95, 0xFF, 0xEA, 0xC8, 0x95, 0xFF, 0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC9, 0x95, 0xFF,
+	0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC9, 0x95, 0xFF,
+	0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC9, 0x96, 0xFF, 0xE9, 0xC9, 0x96, 0xFF, 0xE9, 0xCA, 0x96, 0xFF,
+	0xE9, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF,
+	0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF,
+	0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF,
+	0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF,
+	0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF,
+	0xEA, 0xCA, 0x96, 0xFF, 0xEA, 0xCA, 0x96, 0xFF, 0xE9, 0xCA, 0x96, 0xFF, 0xE9, 0xCA, 0x96, 0xFF,
+	0xE9, 0xC9, 0x96, 0xFF, 0xE9, 0xC9, 0x96, 0xFF, 0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC9, 0x95, 0xFF,
+	0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC9, 0x95, 0xFF, 0xE9, 0xC8, 0x95, 0xFF,
+	0xE9, 0xC8, 0x95, 0xFF, 0xE9, 0xC8, 0x95, 0xFF, 0xE9, 0xC8, 0x95, 0xFF, 0xE8, 0xC8, 0x95, 0xFF,
+	0xE8, 0xC8, 0x95, 0xFF, 0xE8, 0xC7, 0x94, 0xFF, 0xE8, 0xC7, 0x94, 0xFF, 0xE8, 0xC7, 0x94, 0xFF,
+	0xE8, 0xC7, 0x94, 0xFF, 0xE7, 0xC7, 0x94, 0xFF, 0xE7, 0xC7, 0x94, 0xFF, 0xE9, 0xCA, 0x9A, 0xFF,
+	0xE7, 0xC6, 0x92, 0xFF, 0xDC, 0xA9, 0x5B, 0xFF, 0xCF, 0x88, 0x1D, 0xFF, 0xCC, 0x7F, 0x0C, 0xFF,
+	0xCC, 0x80, 0x10, 0xFF, 0xCA, 0x7F, 0x0F, 0xFF, 0xC6, 0x7C, 0x0F, 0xFF, 0xBB, 0x75, 0x0E, 0xFF,
+	0xAA, 0x6A, 0x0C, 0xFF, 0x9E, 0x62, 0x0A, 0xE5, 0x8F, 0x57, 0x08, 0x8D, 0x75, 0x45, 0x05, 0x47,
+	0x57, 0x32, 0x03, 0x1E, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x0B, 0x82, 0x50, 0x08, 0x4C, 0x99, 0x5F, 0x09, 0xB1,
+	0xA4, 0x65, 0x0B, 0xE9, 0xAF, 0x6D, 0x0D, 0xFB, 0xBA, 0x74, 0x0E, 0xFF, 0xC7, 0x7D, 0x10, 0xFF,
+	0xCE, 0x82, 0x10, 0xFF, 0xCD, 0x80, 0x0C, 0xFF, 0xCD, 0x82, 0x12, 0xFF, 0xD2, 0x8E, 0x28, 0xFF,
+	0xD8, 0x9F, 0x46, 0xFF, 0xE0, 0xB4, 0x6F, 0xFF, 0xE7, 0xC6, 0x92, 0xFF, 0xE8, 0xC9, 0x97, 0xFF,
+	0xE7, 0xC5, 0x90, 0xFF, 0xE7, 0xC5, 0x8F, 0xFF, 0xE7, 0xC5, 0x8F, 0xFF, 0xE7, 0xC5, 0x8F, 0xFF,
+	0xE7, 0xC5, 0x90, 0xFF, 0xE7, 0xC6, 0x90, 0xFF, 0xE7, 0xC6, 0x90, 0xFF, 0xE8, 0xC6, 0x90, 0xFF,
+	0xE8, 0xC6, 0x90, 0xFF, 0xE9, 0xC7, 0x90, 0xFF, 0xE9, 0xC7, 0x91, 0xFF, 0xE8, 0xC7, 0x91, 0xFF,
+	0xE8, 0xC7, 0x91, 0xFF, 0xE8, 0xC8, 0x91, 0xFF, 0xE8, 0xC8, 0x91, 0xFF, 0xE8, 0xC8, 0x91, 0xFF,
+	0xE8, 0xC8, 0x91, 0xFF, 0xE8, 0xC8, 0x91, 0xFF, 0xE8, 0xC8, 0x91, 0xFF, 0xE8, 0xC8, 0x91, 0xFF,
+	0xE9, 0xC8, 0x92, 0xFF, 0xE9, 0xC9, 0x92, 0xFF, 0xE9, 0xC9, 0x92, 0xFF, 0xE9, 0xC9, 0x92, 0xFF,
+	0xEA, 0xC9, 0x92, 0xFF, 0xEA, 0xC9, 0x92, 0xFF, 0xE9, 0xC9, 0x92, 0xFF, 0xE9, 0xC9, 0x92, 0xFF,
+	0xE9, 0xC9, 0x92, 0xFF, 0xE9, 0xC9, 0x92, 0xFF, 0xE9, 0xC9, 0x92, 0xFF, 0xE9, 0xC9, 0x92, 0xFF,
+	0xE9, 0xC9, 0x92, 0xFF, 0xE9, 0xC9, 0x92, 0xFF, 0xE9, 0xC9, 0x92, 0xFF, 0xE9, 0xC9, 0x92, 0xFF,
+	0xE9, 0xC9, 0x92, 0xFF, 0xEA, 0xC9, 0x92, 0xFF, 0xEA, 0xC9, 0x92, 0xFF, 0xE9, 0xC8, 0x92, 0xFF,
+	0xE9, 0xC8, 0x92, 0xFF, 0xE9, 0xC8, 0x91, 0xFF, 0xE9, 0xC8, 0x91, 0xFF, 0xE8, 0xC8, 0x91, 0xFF,
+	0xE8, 0xC8, 0x91, 0xFF, 0xE8, 0xC8, 0x91, 0xFF, 0xE8, 0xC8, 0x91, 0xFF, 0xE8, 0xC8, 0x91, 0xFF,
+	0xE8, 0xC7, 0x91, 0xFF, 0xE8, 0xC7, 0x91, 0xFF, 0xE9, 0xC7, 0x91, 0xFF, 0xE9, 0xC7, 0x91, 0xFF,
+	0xE8, 0xC7, 0x91, 0xFF, 0xE8, 0xC7, 0x90, 0xFF, 0xE8, 0xC6, 0x90, 0xFF, 0xE8, 0xC6, 0x90, 0xFF,
+	0xE7, 0xC6, 0x90, 0xFF, 0xE7, 0xC6, 0x90, 0xFF, 0xE7, 0xC6, 0x90, 0xFF, 0xE8, 0xC5, 0x90, 0xFF,
+	0xE7, 0xC5, 0x8F, 0xFF, 0xE7, 0xC5, 0x8F, 0xFF, 0xE6, 0xC5, 0x8F, 0xFF, 0xE8, 0xC9, 0x98, 0xFF,
+	0xE8, 0xC7, 0x94, 0xFF, 0xDE, 0xAD, 0x62, 0xFF, 0xD2, 0x8E, 0x27, 0xFF, 0xCE, 0x83, 0x13, 0xFF,
+	0xCD, 0x82, 0x12, 0xFF, 0xCD, 0x81, 0x10, 0xFF, 0xCC, 0x81, 0x10, 0xFE, 0xC2, 0x7A, 0x0F, 0xFF,
+	0xB0, 0x6E, 0x0D, 0xFF, 0xA4, 0x65, 0x0C, 0xF7, 0x99, 0x5E, 0x0A, 0xBE, 0x8C, 0x55, 0x08, 0x7E,
+	0x72, 0x45, 0x07, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
+	0x02, 0x00, 0x00, 0x0F, 0x39, 0x21, 0x04, 0x26, 0x85, 0x52, 0x09, 0x70, 0xA0, 0x63, 0x0B, 0xDA,
+	0xAE, 0x6C, 0x0D, 0xFF, 0xBF, 0x77, 0x0F, 0xFF, 0xCA, 0x7F, 0x11, 0xFF, 0xCC, 0x81, 0x12, 0xFF,
+	0xCD, 0x82, 0x11, 0xFF, 0xCC, 0x7F, 0x0B, 0xFF, 0xCE, 0x85, 0x15, 0xFF, 0xD7, 0x9C, 0x40, 0xFF,
+	0xE0, 0xB2, 0x6B, 0xFF, 0xE4, 0xBD, 0x80, 0xFF, 0xE6, 0xC3, 0x8B, 0xFF, 0xE7, 0xC5, 0x8E, 0xFF,
+	0xE6, 0xC3, 0x8B, 0xFF, 0xE6, 0xC3, 0x8B, 0xFF, 0xE7, 0xC3, 0x8B, 0xFF, 0xE7, 0xC4, 0x8B, 0xFF,
+	0xE7, 0xC4, 0x8C, 0xFF, 0xE7, 0xC4, 0x8C, 0xFF, 0xE7, 0xC4, 0x8C, 0xFF, 0xE7, 0xC4, 0x8C, 0xFF,
+	0xE7, 0xC5, 0x8C, 0xFF, 0xE7, 0xC5, 0x8C, 0xFF, 0xE8, 0xC5, 0x8C, 0xFF, 0xE8, 0xC5, 0x8D, 0xFF,
+	0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC6, 0x8D, 0xFF,
+	0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC5, 0x8D, 0xFF,
+	0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC7, 0x8E, 0xFF, 0xE8, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF,
+	0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF,
+	0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF,
+	0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF,
+	0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF, 0xE9, 0xC7, 0x8E, 0xFF,
+	0xE8, 0xC7, 0x8D, 0xFF, 0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC6, 0x8D, 0xFF,
+	0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC6, 0x8D, 0xFF,
+	0xE8, 0xC6, 0x8D, 0xFF, 0xE8, 0xC5, 0x8D, 0xFF, 0xE8, 0xC5, 0x8D, 0xFF, 0xE8, 0xC5, 0x8D, 0xFF,
+	0xE8, 0xC5, 0x8D, 0xFF, 0xE7, 0xC5, 0x8C, 0xFF, 0xE7, 0xC5, 0x8C, 0xFF, 0xE7, 0xC4, 0x8C, 0xFF,
+	0xE7, 0xC3, 0x8C, 0xFF, 0xE7, 0xC4, 0x8C, 0xFF, 0xE7, 0xC4, 0x8C, 0xFF, 0xE7, 0xC4, 0x8B, 0xFF,
+	0xE7, 0xC3, 0x8B, 0xFF, 0xE6, 0xC3, 0x8B, 0xFF, 0xE6, 0xC3, 0x8B, 0xFF, 0xE7, 0xC6, 0x91, 0xFF,
+	0xE6, 0xC3, 0x8C, 0xFF, 0xDF, 0xAE, 0x64, 0xFF, 0xD5, 0x95, 0x34, 0xFF, 0xD0, 0x89, 0x1E, 0xFF,
+	0xCD, 0x84, 0x14, 0xFF, 0xCD, 0x82, 0x10, 0xFF, 0xCE, 0x83, 0x11, 0xFF, 0xC6, 0x7D, 0x10, 0xFF,
+	0xB7, 0x72, 0x0E, 0xFF, 0xAB, 0x6A, 0x0D, 0xFB, 0xA1, 0x64, 0x0C, 0xEA, 0x99, 0x5E, 0x0A, 0xB6,
+	0x83, 0x51, 0x09, 0x4D, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x09, 0x04, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
+	0x57, 0x36, 0x06, 0x23, 0x76, 0x49, 0x09, 0x56, 0x91, 0x5A, 0x0B, 0x9C, 0xA3, 0x66, 0x0C, 0xEE,
+	0xB1, 0x6F, 0x0E, 0xFF, 0xC5, 0x7C, 0x11, 0xFF, 0xD0, 0x83, 0x12, 0xFF, 0xCF, 0x83, 0x13, 0xFF,
+	0xCE, 0x83, 0x12, 0xFF, 0xCD, 0x81, 0x0D, 0xFF, 0xCF, 0x88, 0x19, 0xFF, 0xDA, 0xA3, 0x4C, 0xFF,
+	0xE4, 0xBB, 0x7B, 0xFF, 0xE6, 0xC1, 0x87, 0xFF, 0xE6, 0xC1, 0x87, 0xFF, 0xE6, 0xC2, 0x88, 0xFF,
+	0xE6, 0xC2, 0x87, 0xFF, 0xE6, 0xC2, 0x87, 0xFF, 0xE7, 0xC2, 0x87, 0xFF, 0xE7, 0xC2, 0x87, 0xFF,
+	0xE7, 0xC3, 0x88, 0xFF, 0xE7, 0xC3, 0x88, 0xFF, 0xE7, 0xC3, 0x88, 0xFF, 0xE7, 0xC3, 0x88, 0xFF,
+	0xE7, 0xC4, 0x88, 0xFF, 0xE7, 0xC4, 0x88, 0xFF, 0xE8, 0xC4, 0x88, 0xFF, 0xE8, 0xC4, 0x89, 0xFF,
+	0xE8, 0xC4, 0x89, 0xFF, 0xE8, 0xC5, 0x89, 0xFF, 0xE8, 0xC5, 0x89, 0xFF, 0xE8, 0xC5, 0x89, 0xFF,
+	0xE8, 0xC5, 0x89, 0xFF, 0xE8, 0xC5, 0x89, 0xFF, 0xE8, 0xC5, 0x89, 0xFF, 0xE8, 0xC4, 0x89, 0xFF,
+	0xE8, 0xC4, 0x89, 0xFF, 0xE8, 0xC5, 0x8A, 0xFF, 0xE8, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF,
+	0xE9, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF,
+	0xE9, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF,
+	0xE9, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF,
+	0xE9, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF, 0xE9, 0xC6, 0x8A, 0xFF, 0xE8, 0xC6, 0x8A, 0xFF,
+	0xE8, 0xC5, 0x89, 0xFF, 0xE8, 0xC5, 0x89, 0xFF, 0xE8, 0xC5, 0x89, 0xFF, 0xE8, 0xC5, 0x89, 0xFF,
+	0xE8, 0xC5, 0x89, 0xFF, 0xE8, 0xC5, 0x89, 0xFF, 0xE8, 0xC5, 0x89, 0xFF, 0xE8, 0xC5, 0x89, 0xFF,
+	0xE8, 0xC4, 0x89, 0xFF, 0xE8, 0xC4, 0x89, 0xFF, 0xE8, 0xC4, 0x89, 0xFF, 0xE8, 0xC4, 0x89, 0xFF,
+	0xE8, 0xC4, 0x89, 0xFF, 0xE7, 0xC4, 0x88, 0xFF, 0xE7, 0xC3, 0x88, 0xFF, 0xE7, 0xC2, 0x88, 0xFF,
+	0xE7, 0xC2, 0x88, 0xFF, 0xE7, 0xC3, 0x88, 0xFF, 0xE7, 0xC3, 0x88, 0xFF, 0xE7, 0xC2, 0x87, 0xFF,
+	0xE7, 0xC2, 0x87, 0xFF, 0xE6, 0xC2, 0x87, 0xFF, 0xE6, 0xC2, 0x87, 0xFF, 0xE7, 0xC4, 0x8B, 0xFF,
+	0xE6, 0xC1, 0x87, 0xFF, 0xE1, 0xB3, 0x6C, 0xFF, 0xDA, 0xA0, 0x48, 0xFF, 0xD4, 0x91, 0x2C, 0xFF,
+	0xCE, 0x85, 0x16, 0xFF, 0xCD, 0x82, 0x0E, 0xFF, 0xCF, 0x84, 0x11, 0xFF, 0xCB, 0x81, 0x11, 0xFF,
+	0xC2, 0x7B, 0x10, 0xFF, 0xB7, 0x73, 0x0E, 0xFF, 0xA9, 0x69, 0x0D, 0xFF, 0x9E, 0x62, 0x0B, 0xD8,
+	0x8C, 0x56, 0x0A, 0x74, 0x50, 0x31, 0x05, 0x26, 0x08, 0x05, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x04,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05,
+	0x78, 0x4B, 0x09, 0x3E, 0x91, 0x5B, 0x0B, 0x92, 0x9C, 0x61, 0x0C, 0xCC, 0xA6, 0x68, 0x0E, 0xF5,
+	0xB3, 0x71, 0x0F, 0xFF, 0xC6, 0x7E, 0x12, 0xFF, 0xD0, 0x85, 0x13, 0xFF, 0xD0, 0x85, 0x13, 0xFF,
+	0xCF, 0x85, 0x14, 0xFF, 0xCE, 0x83, 0x11, 0xFF, 0xD1, 0x8B, 0x1F, 0xFF, 0xDC, 0xA6, 0x52, 0xFF,
+	0xE6, 0xBE, 0x7E, 0xFF, 0xE7, 0xC2, 0x86, 0xFF, 0xE6, 0xC0, 0x83, 0xFF, 0xE6, 0xC0, 0x83, 0xFF,
+	0xE6, 0xC1, 0x83, 0xFF, 0xE6, 0xC1, 0x83, 0xFF, 0xE7, 0xC0, 0x83, 0xFF, 0xE7, 0xC1, 0x84, 0xFF,
+	0xE7, 0xC1, 0x84, 0xFF, 0xE7, 0xC2, 0x85, 0xFF, 0xE7, 0xC2, 0x85, 0xFF, 0xE7, 0xC2, 0x85, 0xFF,
+	0xE7, 0xC2, 0x85, 0xFF, 0xE7, 0xC3, 0x85, 0xFF, 0xE8, 0xC3, 0x85, 0xFF, 0xE8, 0xC3, 0x85, 0xFF,
+	0xE8, 0xC3, 0x85, 0xFF, 0xE8, 0xC3, 0x86, 0xFF, 0xE8, 0xC3, 0x86, 0xFF, 0xE8, 0xC4, 0x86, 0xFF,
+	0xE8, 0xC4, 0x86, 0xFF, 0xE8, 0xC4, 0x86, 0xFF, 0xE8, 0xC3, 0x86, 0xFF, 0xE8, 0xC3, 0x86, 0xFF,
+	0xE8, 0xC3, 0x86, 0xFF, 0xE8, 0xC4, 0x86, 0xFF, 0xE8, 0xC4, 0x86, 0xFF, 0xE9, 0xC4, 0x86, 0xFF,
+	0xE9, 0xC5, 0x87, 0xFF, 0xE9, 0xC5, 0x87, 0xFF, 0xE9, 0xC5, 0x87, 0xFF, 0xE9, 0xC5, 0x87, 0xFF,
+	0xE9, 0xC5, 0x87, 0xFF, 0xE9, 0xC5, 0x87, 0xFF, 0xE9, 0xC5, 0x87, 0xFF, 0xE9, 0xC5, 0x87, 0xFF,
+	0xE9, 0xC5, 0x87, 0xFF, 0xE9, 0xC5, 0x87, 0xFF, 0xE9, 0xC5, 0x87, 0xFF, 0xE9, 0xC5, 0x87, 0xFF,
+	0xE9, 0xC5, 0x87, 0xFF, 0xE9, 0xC5, 0x86, 0xFF, 0xE8, 0xC5, 0x86, 0xFF, 0xE8, 0xC5, 0x86, 0xFF,
+	0xE8, 0xC4, 0x86, 0xFF, 0xE8, 0xC4, 0x86, 0xFF, 0xE8, 0xC4, 0x86, 0xFF, 0xE8, 0xC3, 0x86, 0xFF,
+	0xE8, 0xC3, 0x86, 0xFF, 0xE8, 0xC4, 0x86, 0xFF, 0xE8, 0xC4, 0x86, 0xFF, 0xE8, 0xC4, 0x86, 0xFF,
+	0xE8, 0xC3, 0x86, 0xFF, 0xE8, 0xC3, 0x86, 0xFF, 0xE8, 0xC3, 0x85, 0xFF, 0xE8, 0xC3, 0x85, 0xFF,
+	0xE8, 0xC2, 0x85, 0xFF, 0xE7, 0xC2, 0x85, 0xFF, 0xE7, 0xC2, 0x85, 0xFF, 0xE7, 0xC1, 0x85, 0xFF,
+	0xE7, 0xC1, 0x84, 0xFF, 0xE7, 0xC2, 0x84, 0xFF, 0xE7, 0xC2, 0x84, 0xFF, 0xE7, 0xC1, 0x83, 0xFF,
+	0xE6, 0xC0, 0x83, 0xFF, 0xE6, 0xC1, 0x83, 0xFF, 0xE6, 0xC1, 0x83, 0xFF, 0xE7, 0xC1, 0x85, 0xFF,
+	0xE6, 0xC0, 0x83, 0xFF, 0xE4, 0xB8, 0x76, 0xFF, 0xDF, 0xAD, 0x60, 0xFF, 0xD8, 0x9A, 0x3D, 0xFF,
+	0xCF, 0x86, 0x17, 0xFF, 0xCD, 0x81, 0x0B, 0xFF, 0xCE, 0x84, 0x11, 0xFF, 0xCE, 0x85, 0x12, 0xFF,
+	0xCE, 0x84, 0x11, 0xFF, 0xC4, 0x7D, 0x10, 0xFF, 0xB1, 0x6F, 0x0E, 0xFF, 0xA2, 0x64, 0x0C, 0xEC,
+	0x91, 0x5A, 0x0A, 0xA2, 0x78, 0x4A, 0x08, 0x5D, 0x5E, 0x3A, 0x06, 0x2A, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x12,
+	0x80, 0x51, 0x0A, 0x5B, 0x9A, 0x61, 0x0C, 0xBE, 0xA5, 0x68, 0x0D, 0xEE, 0xB0, 0x6F, 0x0F, 0xFB,
+	0xBC, 0x77, 0x11, 0xFF, 0xC9, 0x81, 0x13, 0xFF, 0xD0, 0x86, 0x14, 0xFF, 0xD0, 0x86, 0x14, 0xFF,
+	0xCF, 0x86, 0x14, 0xFF, 0xCF, 0x86, 0x14, 0xFF, 0xD3, 0x8E, 0x23, 0xFF, 0xDD, 0xA8, 0x54, 0xFF,
+	0xE6, 0xBE, 0x7E, 0xFF, 0xE7, 0xC1, 0x84, 0xFF, 0xE6, 0xBE, 0x7E, 0xFF, 0xE6, 0xBE, 0x7E, 0xFF,
+	0xE6, 0xBF, 0x7E, 0xFF, 0xE6, 0xBF, 0x7F, 0xFF, 0xE6, 0xBF, 0x7F, 0xFF, 0xE7, 0xBF, 0x80, 0xFF,
+	0xE7, 0xC0, 0x80, 0xFF, 0xE7, 0xC0, 0x80, 0xFF, 0xE7, 0xC0, 0x80, 0xFF, 0xE7, 0xC0, 0x80, 0xFF,
+	0xE7, 0xC1, 0x80, 0xFF, 0xE7, 0xC1, 0x80, 0xFF, 0xE7, 0xC1, 0x80, 0xFF, 0xE8, 0xC1, 0x81, 0xFF,
+	0xE8, 0xC1, 0x81, 0xFF, 0xE8, 0xC1, 0x81, 0xFF, 0xE8, 0xC2, 0x81, 0xFF, 0xE8, 0xC2, 0x81, 0xFF,
+	0xE8, 0xC2, 0x81, 0xFF, 0xE8, 0xC2, 0x81, 0xFF, 0xE8, 0xC2, 0x81, 0xFF, 0xE8, 0xC2, 0x81, 0xFF,
+	0xE8, 0xC2, 0x81, 0xFF, 0xE8, 0xC2, 0x81, 0xFF, 0xE8, 0xC3, 0x81, 0xFF, 0xE9, 0xC3, 0x82, 0xFF,
+	0xE9, 0xC3, 0x82, 0xFF, 0xE9, 0xC3, 0x82, 0xFF, 0xE9, 0xC3, 0x82, 0xFF, 0xE9, 0xC3, 0x82, 0xFF,
+	0xE9, 0xC3, 0x82, 0xFF, 0xE9, 0xC3, 0x82, 0xFF, 0xE9, 0xC3, 0x82, 0xFF, 0xE9, 0xC3, 0x82, 0xFF,
+	0xE9, 0xC3, 0x82, 0xFF, 0xE9, 0xC3, 0x82, 0xFF, 0xE9, 0xC3, 0x82, 0xFF, 0xE9, 0xC3, 0x82, 0xFF,
+	0xE9, 0xC3, 0x82, 0xFF, 0xE9, 0xC3, 0x82, 0xFF, 0xE8, 0xC3, 0x82, 0xFF, 0xE8, 0xC3, 0x81, 0xFF,
+	0xE8, 0xC3, 0x81, 0xFF, 0xE8, 0xC3, 0x81, 0xFF, 0xE8, 0xC3, 0x81, 0xFF, 0xE8, 0xC2, 0x81, 0xFF,
+	0xE8, 0xC2, 0x81, 0xFF, 0xE8, 0xC2, 0x81, 0xFF, 0xE8, 0xC2, 0x81, 0xFF, 0xE8, 0xC2, 0x81, 0xFF,
+	0xE8, 0xC2, 0x81, 0xFF, 0xE8, 0xC1, 0x81, 0xFF, 0xE8, 0xC1, 0x81, 0xFF, 0xE8, 0xC1, 0x80, 0xFF,
+	0xE7, 0xC1, 0x80, 0xFF, 0xE7, 0xC0, 0x80, 0xFF, 0xE7, 0xC0, 0x80, 0xFF, 0xE7, 0xC0, 0x80, 0xFF,
+	0xE7, 0xC0, 0x80, 0xFF, 0xE7, 0xC0, 0x80, 0xFF, 0xE6, 0xC0, 0x7F, 0xFF, 0xE6, 0xBF, 0x7F, 0xFF,
+	0xE6, 0xBF, 0x7E, 0xFF, 0xE6, 0xBF, 0x7F, 0xFF, 0xE6, 0xBF, 0x7F, 0xFF, 0xE6, 0xBF, 0x80, 0xFF,
+	0xE6, 0xBE, 0x7F, 0xFF, 0xE5, 0xBB, 0x79, 0xFF, 0xE2, 0xB4, 0x6C, 0xFF, 0xDA, 0xA0, 0x46, 0xFF,
+	0xD0, 0x87, 0x18, 0xFF, 0xCD, 0x81, 0x0B, 0xFF, 0xCE, 0x85, 0x12, 0xFF, 0xD0, 0x87, 0x14, 0xFF,
+	0xD2, 0x88, 0x13, 0xFF, 0xCB, 0x82, 0x11, 0xFF, 0xB8, 0x74, 0x0F, 0xFF, 0xA9, 0x6A, 0x0D, 0xF9,
+	0x9B, 0x61, 0x0C, 0xCC, 0x8C, 0x58, 0x0A, 0x92, 0x75, 0x49, 0x08, 0x46, 0x00, 0x00, 0x00, 0x0B,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x0F, 0x2B, 0x1B, 0x04, 0x2A,
+	0x83, 0x52, 0x0B, 0x79, 0x9F, 0x64, 0x0D, 0xDE, 0xAE, 0x6E, 0x0E, 0xFF, 0xBF, 0x7A, 0x10, 0xFF,
+	0xCA, 0x81, 0x12, 0xFF, 0xCE, 0x84, 0x14, 0xFF, 0xD0, 0x86, 0x15, 0xFF, 0xD0, 0x87, 0x14, 0xFF,
+	0xD0, 0x88, 0x15, 0xFF, 0xD0, 0x88, 0x16, 0xFF, 0xD3, 0x90, 0x25, 0xFF, 0xDD, 0xA8, 0x52, 0xFF,
+	0xE5, 0xBC, 0x7A, 0xFF, 0xE6, 0xBF, 0x7F, 0xFF, 0xE5, 0xBC, 0x7A, 0xFF, 0xE5, 0xBC, 0x7A, 0xFF,
+	0xE5, 0xBD, 0x7A, 0xFF, 0xE5, 0xBD, 0x7B, 0xFF, 0xE5, 0xBE, 0x7B, 0xFF, 0xE5, 0xBE, 0x7B, 0xFF,
+	0xE5, 0xBE, 0x7C, 0xFF, 0xE6, 0xBE, 0x7C, 0xFF, 0xE6, 0xBF, 0x7C, 0xFF, 0xE6, 0xBF, 0x7C, 0xFF,
+	0xE6, 0xBF, 0x7C, 0xFF, 0xE6, 0xBF, 0x7C, 0xFF, 0xE7, 0xBF, 0x7C, 0xFF, 0xE7, 0xBF, 0x7C, 0xFF,
+	0xE7, 0xBF, 0x7D, 0xFF, 0xE7, 0xC0, 0x7D, 0xFF, 0xE7, 0xC0, 0x7D, 0xFF, 0xE7, 0xC1, 0x7D, 0xFF,
+	0xE7, 0xC1, 0x7D, 0xFF, 0xE7, 0xC1, 0x7D, 0xFF, 0xE7, 0xC1, 0x7D, 0xFF, 0xE7, 0xC1, 0x7D, 0xFF,
+	0xE7, 0xC1, 0x7D, 0xFF, 0xE7, 0xC1, 0x7C, 0xFF, 0xE7, 0xC2, 0x7D, 0xFF, 0xE8, 0xC2, 0x7D, 0xFF,
+	0xE8, 0xC2, 0x7E, 0xFF, 0xE8, 0xC2, 0x7E, 0xFF, 0xE8, 0xC2, 0x7E, 0xFF, 0xE8, 0xC2, 0x7E, 0xFF,
+	0xE8, 0xC2, 0x7E, 0xFF, 0xE8, 0xC2, 0x7E, 0xFF, 0xE8, 0xC2, 0x7E, 0xFF, 0xE8, 0xC2, 0x7E, 0xFF,
+	0xE8, 0xC2, 0x7E, 0xFF, 0xE8, 0xC2, 0x7E, 0xFF, 0xE8, 0xC2, 0x7E, 0xFF, 0xE8, 0xC2, 0x7E, 0xFF,
+	0xE8, 0xC2, 0x7E, 0xFF, 0xE8, 0xC2, 0x7E, 0xFF, 0xE8, 0xC2, 0x7D, 0xFF, 0xE8, 0xC2, 0x7D, 0xFF,
+	0xE7, 0xC2, 0x7D, 0xFF, 0xE7, 0xC2, 0x7D, 0xFF, 0xE7, 0xC1, 0x7D, 0xFF, 0xE7, 0xC1, 0x7D, 0xFF,
+	0xE7, 0xC1, 0x7D, 0xFF, 0xE7, 0xC1, 0x7D, 0xFF, 0xE7, 0xC0, 0x7D, 0xFF, 0xE7, 0xC0, 0x7D, 0xFF,
+	0xE7, 0xC0, 0x7D, 0xFF, 0xE7, 0xC0, 0x7D, 0xFF, 0xE7, 0xC0, 0x7C, 0xFF, 0xE7, 0xC0, 0x7C, 0xFF,
+	0xE7, 0xC0, 0x7B, 0xFF, 0xE6, 0xBF, 0x7C, 0xFF, 0xE6, 0xBF, 0x7C, 0xFF, 0xE6, 0xBF, 0x7C, 0xFF,
+	0xE6, 0xBF, 0x7B, 0xFF, 0xE6, 0xBE, 0x7B, 0xFF, 0xE5, 0xBD, 0x7B, 0xFF, 0xE5, 0xBE, 0x7A, 0xFF,
+	0xE5, 0xBE, 0x7A, 0xFF, 0xE5, 0xBD, 0x7A, 0xFF, 0xE5, 0xBD, 0x7A, 0xFF, 0xE5, 0xBD, 0x7B, 0xFF,
+	0xE4, 0xBC, 0x7A, 0xFF, 0xE4, 0xBB, 0x78, 0xFF, 0xE2, 0xB7, 0x6F, 0xFF, 0xDA, 0xA2, 0x49, 0xFF,
+	0xD0, 0x89, 0x19, 0xFF, 0xCD, 0x81, 0x0B, 0xFF, 0xCF, 0x85, 0x13, 0xFF, 0xD0, 0x87, 0x15, 0xFF,
+	0xD1, 0x87, 0x14, 0xFF, 0xCB, 0x83, 0x12, 0xFF, 0xBE, 0x7A, 0x10, 0xFF, 0xB2, 0x71, 0x0E, 0xFD,
+	0xA7, 0x6A, 0x0D, 0xF2, 0x9D, 0x63, 0x0C, 0xC8, 0x84, 0x53, 0x0A, 0x65, 0x00, 0x00, 0x00, 0x11,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x4E, 0x31, 0x06, 0x29, 0x6E, 0x45, 0x09, 0x58,
+	0x90, 0x5C, 0x0C, 0xA2, 0xA5, 0x69, 0x0E, 0xF3, 0xB5, 0x73, 0x10, 0xFF, 0xC8, 0x81, 0x12, 0xFF,
+	0xD1, 0x87, 0x14, 0xFF, 0xD1, 0x87, 0x15, 0xFF, 0xD0, 0x87, 0x15, 0xFF, 0xD0, 0x87, 0x14, 0xFF,
+	0xD0, 0x89, 0x16, 0xFF, 0xD1, 0x8A, 0x18, 0xFF, 0xD4, 0x92, 0x27, 0xFF, 0xDD, 0xA7, 0x51, 0xFF,
+	0xE4, 0xBA, 0x75, 0xFF, 0xE5, 0xBC, 0x7A, 0xFF, 0xE5, 0xBA, 0x75, 0xFF, 0xE5, 0xBB, 0x76, 0xFF,
+	0xE5, 0xBB, 0x76, 0xFF, 0xE5, 0xBC, 0x76, 0xFF, 0xE5, 0xBC, 0x76, 0xFF, 0xE5, 0xBC, 0x77, 0xFF,
+	0xE5, 0xBC, 0x77, 0xFF, 0xE5, 0xBD, 0x77, 0xFF, 0xE6, 0xBD, 0x77, 0xFF, 0xE6, 0xBE, 0x77, 0xFF,
+	0xE6, 0xBD, 0x77, 0xFF, 0xE6, 0xBD, 0x78, 0xFF, 0xE6, 0xBD, 0x78, 0xFF, 0xE7, 0xBE, 0x79, 0xFF,
+	0xE7, 0xBE, 0x79, 0xFF, 0xE7, 0xBE, 0x78, 0xFF, 0xE7, 0xBF, 0x78, 0xFF, 0xE7, 0xBF, 0x78, 0xFF,
+	0xE7, 0xC0, 0x78, 0xFF, 0xE7, 0xBF, 0x78, 0xFF, 0xE7, 0xBF, 0x78, 0xFF, 0xE7, 0xBF, 0x79, 0xFF,
+	0xE7, 0xC0, 0x79, 0xFF, 0xE7, 0xC0, 0x79, 0xFF, 0xE7, 0xC1, 0x79, 0xFF, 0xE8, 0xC0, 0x79, 0xFF,
+	0xE8, 0xC0, 0x79, 0xFF, 0xE8, 0xC0, 0x79, 0xFF, 0xE8, 0xC0, 0x79, 0xFF, 0xE8, 0xC0, 0x79, 0xFF,
+	0xE8, 0xC0, 0x79, 0xFF, 0xE8, 0xC1, 0x79, 0xFF, 0xE8, 0xC1, 0x79, 0xFF, 0xE8, 0xC1, 0x79, 0xFF,
+	0xE8, 0xC1, 0x79, 0xFF, 0xE8, 0xC1, 0x79, 0xFF, 0xE8, 0xC0, 0x79, 0xFF, 0xE8, 0xC0, 0x79, 0xFF,
+	0xE8, 0xC0, 0x79, 0xFF, 0xE8, 0xC0, 0x79, 0xFF, 0xE8, 0xC0, 0x7A, 0xFF, 0xE8, 0xC0, 0x79, 0xFF,
+	0xE7, 0xC1, 0x79, 0xFF, 0xE7, 0xC0, 0x79, 0xFF, 0xE7, 0xC0, 0x79, 0xFF, 0xE7, 0xBF, 0x79, 0xFF,
+	0xE7, 0xBF, 0x78, 0xFF, 0xE7, 0xBF, 0x78, 0xFF, 0xE7, 0xBF, 0x78, 0xFF, 0xE7, 0xBF, 0x78, 0xFF,
+	0xE7, 0xBE, 0x78, 0xFF, 0xE7, 0xBE, 0x78, 0xFF, 0xE7, 0xBE, 0x78, 0xFF, 0xE7, 0xBE, 0x78, 0xFF,
+	0xE7, 0xBE, 0x77, 0xFF, 0xE6, 0xBE, 0x77, 0xFF, 0xE6, 0xBD, 0x77, 0xFF, 0xE6, 0xBD, 0x78, 0xFF,
+	0xE6, 0xBD, 0x77, 0xFF, 0xE5, 0xBC, 0x77, 0xFF, 0xE5, 0xBB, 0x76, 0xFF, 0xE5, 0xBC, 0x76, 0xFF,
+	0xE5, 0xBC, 0x76, 0xFF, 0xE5, 0xBC, 0x76, 0xFF, 0xE5, 0xBB, 0x76, 0xFF, 0xE4, 0xBB, 0x76, 0xFF,
+	0xE4, 0xBA, 0x75, 0xFF, 0xE4, 0xBC, 0x77, 0xFF, 0xE3, 0xB9, 0x72, 0xFF, 0xDB, 0xA5, 0x4C, 0xFF,
+	0xD1, 0x8A, 0x1A, 0xFF, 0xCE, 0x83, 0x0C, 0xFF, 0xD0, 0x87, 0x13, 0xFF, 0xD0, 0x88, 0x16, 0xFF,
+	0xD1, 0x87, 0x15, 0xFF, 0xCD, 0x85, 0x14, 0xFF, 0xC5, 0x7F, 0x12, 0xFF, 0xBB, 0x78, 0x10, 0xFF,
+	0xAF, 0x6F, 0x0E, 0xFF, 0xA3, 0x68, 0x0D, 0xEA, 0x8C, 0x59, 0x0B, 0x82, 0x2A, 0x1B, 0x04, 0x26,
+	0x00, 0x00, 0x00, 0x0B, 0x07, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x7F, 0x50, 0x0A, 0x53, 0x96, 0x5F, 0x0C, 0xA6,
+	0xA3, 0x67, 0x0D, 0xDA, 0xAF, 0x6F, 0x0F, 0xFB, 0xBC, 0x78, 0x11, 0xFF, 0xCB, 0x83, 0x14, 0xFF,
+	0xD2, 0x88, 0x15, 0xFF, 0xD1, 0x88, 0x15, 0xFF, 0xD0, 0x88, 0x16, 0xFF, 0xD0, 0x88, 0x15, 0xFF,
+	0xD1, 0x8A, 0x17, 0xFF, 0xD2, 0x8C, 0x1B, 0xFF, 0xD5, 0x94, 0x2A, 0xFF, 0xDD, 0xA8, 0x51, 0xFF,
+	0xE4, 0xB8, 0x72, 0xFF, 0xE5, 0xBB, 0x76, 0xFF, 0xE4, 0xB9, 0x71, 0xFF, 0xE4, 0xBA, 0x72, 0xFF,
+	0xE4, 0xBA, 0x72, 0xFF, 0xE5, 0xBA, 0x72, 0xFF, 0xE5, 0xBA, 0x73, 0xFF, 0xE5, 0xBB, 0x73, 0xFF,
+	0xE5, 0xBB, 0x73, 0xFF, 0xE5, 0xBB, 0x73, 0xFF, 0xE6, 0xBC, 0x74, 0xFF, 0xE6, 0xBC, 0x74, 0xFF,
+	0xE6, 0xBC, 0x74, 0xFF, 0xE6, 0xBC, 0x74, 0xFF, 0xE6, 0xBC, 0x75, 0xFF, 0xE6, 0xBD, 0x75, 0xFF,
+	0xE6, 0xBD, 0x75, 0xFF, 0xE6, 0xBD, 0x75, 0xFF, 0xE7, 0xBE, 0x75, 0xFF, 0xE7, 0xBE, 0x75, 0xFF,
+	0xE7, 0xBE, 0x75, 0xFF, 0xE7, 0xBE, 0x75, 0xFF, 0xE7, 0xBE, 0x75, 0xFF, 0xE7, 0xBE, 0x76, 0xFF,
+	0xE7, 0xBE, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF,
+	0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF,
+	0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xC0, 0x76, 0xFF, 0xE7, 0xC0, 0x76, 0xFF,
+	0xE7, 0xC0, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF,
+	0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF,
+	0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBF, 0x76, 0xFF, 0xE7, 0xBE, 0x76, 0xFF, 0xE7, 0xBE, 0x76, 0xFF,
+	0xE7, 0xBE, 0x75, 0xFF, 0xE7, 0xBE, 0x75, 0xFF, 0xE7, 0xBE, 0x75, 0xFF, 0xE6, 0xBE, 0x75, 0xFF,
+	0xE6, 0xBD, 0x75, 0xFF, 0xE6, 0xBD, 0x75, 0xFF, 0xE6, 0xBD, 0x75, 0xFF, 0xE6, 0xBC, 0x75, 0xFF,
+	0xE6, 0xBC, 0x74, 0xFF, 0xE6, 0xBC, 0x74, 0xFF, 0xE6, 0xBC, 0x74, 0xFF, 0xE5, 0xBC, 0x74, 0xFF,
+	0xE5, 0xBB, 0x74, 0xFF, 0xE5, 0xBB, 0x73, 0xFF, 0xE5, 0xBB, 0x73, 0xFF, 0xE5, 0xBB, 0x73, 0xFF,
+	0xE4, 0xBA, 0x73, 0xFF, 0xE4, 0xBA, 0x73, 0xFF, 0xE4, 0xBA, 0x72, 0xFF, 0xE4, 0xBA, 0x72, 0xFF,
+	0xE4, 0xB9, 0x71, 0xFF, 0xE5, 0xBC, 0x77, 0xFF, 0xE4, 0xBA, 0x75, 0xFF, 0xDC, 0xA7, 0x4F, 0xFF,
+	0xD2, 0x8D, 0x1C, 0xFF, 0xCF, 0x85, 0x0D, 0xFF, 0xD0, 0x88, 0x14, 0xFF, 0xD1, 0x89, 0x16, 0xFF,
+	0xD0, 0x88, 0x16, 0xFF, 0xCF, 0x87, 0x15, 0xFF, 0xCE, 0x85, 0x14, 0xFF, 0xC6, 0x80, 0x13, 0xFF,
+	0xB4, 0x73, 0x10, 0xFF, 0xA5, 0x69, 0x0E, 0xF4, 0x90, 0x5B, 0x0C, 0x9D, 0x62, 0x3D, 0x09, 0x4A,
+	0x38, 0x22, 0x06, 0x21, 0x0C, 0x07, 0x01, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x18, 0x8B, 0x58, 0x0B, 0x74, 0xA3, 0x67, 0x0D, 0xDE,
+	0xAD, 0x6E, 0x0F, 0xFF, 0xB8, 0x76, 0x11, 0xFF, 0xC3, 0x7D, 0x13, 0xFF, 0xCD, 0x85, 0x15, 0xFF,
+	0xD2, 0x89, 0x17, 0xFF, 0xD1, 0x89, 0x16, 0xFF, 0xD0, 0x89, 0x16, 0xFF, 0xD1, 0x89, 0x16, 0xFF,
+	0xD1, 0x8B, 0x18, 0xFF, 0xD3, 0x8D, 0x1C, 0xFF, 0xD6, 0x95, 0x2B, 0xFF, 0xDE, 0xA8, 0x4F, 0xFF,
+	0xE4, 0xB7, 0x6E, 0xFF, 0xE5, 0xB9, 0x72, 0xFF, 0xE4, 0xB8, 0x6D, 0xFF, 0xE4, 0xB8, 0x6E, 0xFF,
+	0xE4, 0xB9, 0x6E, 0xFF, 0xE4, 0xB9, 0x6F, 0xFF, 0xE5, 0xB9, 0x6F, 0xFF, 0xE5, 0xB9, 0x6F, 0xFF,
+	0xE5, 0xBA, 0x6F, 0xFF, 0xE5, 0xBA, 0x6F, 0xFF, 0xE6, 0xBB, 0x70, 0xFF, 0xE6, 0xBB, 0x70, 0xFF,
+	0xE6, 0xBB, 0x70, 0xFF, 0xE6, 0xBB, 0x70, 0xFF, 0xE6, 0xBB, 0x71, 0xFF, 0xE6, 0xBC, 0x71, 0xFF,
+	0xE6, 0xBC, 0x71, 0xFF, 0xE6, 0xBC, 0x71, 0xFF, 0xE6, 0xBC, 0x71, 0xFF, 0xE7, 0xBD, 0x71, 0xFF,
+	0xE7, 0xBD, 0x71, 0xFF, 0xE7, 0xBD, 0x71, 0xFF, 0xE7, 0xBD, 0x72, 0xFF, 0xE7, 0xBD, 0x72, 0xFF,
+	0xE7, 0xBD, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF,
+	0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF,
+	0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBF, 0x72, 0xFF, 0xE7, 0xBF, 0x72, 0xFF,
+	0xE7, 0xBF, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF,
+	0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF,
+	0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBE, 0x72, 0xFF, 0xE7, 0xBD, 0x72, 0xFF, 0xE7, 0xBD, 0x72, 0xFF,
+	0xE7, 0xBD, 0x72, 0xFF, 0xE7, 0xBD, 0x71, 0xFF, 0xE6, 0xBD, 0x71, 0xFF, 0xE6, 0xBD, 0x71, 0xFF,
+	0xE6, 0xBC, 0x71, 0xFF, 0xE6, 0xBC, 0x71, 0xFF, 0xE6, 0xBB, 0x71, 0xFF, 0xE6, 0xBB, 0x71, 0xFF,
+	0xE6, 0xBB, 0x71, 0xFF, 0xE6, 0xBB, 0x70, 0xFF, 0xE6, 0xBA, 0x70, 0xFF, 0xE5, 0xBA, 0x70, 0xFF,
+	0xE5, 0xBA, 0x70, 0xFF, 0xE5, 0xBA, 0x6F, 0xFF, 0xE5, 0xBA, 0x6F, 0xFF, 0xE4, 0xB9, 0x6F, 0xFF,
+	0xE4, 0xB9, 0x6F, 0xFF, 0xE4, 0xB9, 0x6F, 0xFF, 0xE4, 0xB9, 0x6E, 0xFF, 0xE4, 0xB8, 0x6D, 0xFF,
+	0xE4, 0xB8, 0x6D, 0xFF, 0xE5, 0xBB, 0x75, 0xFF, 0xE5, 0xBA, 0x76, 0xFF, 0xDD, 0xA8, 0x50, 0xFF,
+	0xD3, 0x8F, 0x1D, 0xFF, 0xD0, 0x87, 0x0E, 0xFF, 0xD1, 0x8A, 0x15, 0xFF, 0xD1, 0x8A, 0x17, 0xFF,
+	0xD0, 0x89, 0x16, 0xFF, 0xD1, 0x88, 0x16, 0xFF, 0xD3, 0x8A, 0x16, 0xFF, 0xCD, 0x85, 0x15, 0xFF,
+	0xBA, 0x78, 0x11, 0xFF, 0xAA, 0x6C, 0x0F, 0xF8, 0x98, 0x61, 0x0D, 0xBC, 0x81, 0x51, 0x0B, 0x79,
+	0x69, 0x42, 0x09, 0x3D, 0x0E, 0x09, 0x01, 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x06,
+	0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x20, 0x88, 0x56, 0x0C, 0x7F, 0xA5, 0x69, 0x0E, 0xEC,
+	0xB2, 0x72, 0x10, 0xFF, 0xC0, 0x7C, 0x13, 0xFF, 0xC9, 0x83, 0x15, 0xFF, 0xCF, 0x87, 0x16, 0xFF,
+	0xD2, 0x8A, 0x17, 0xFF, 0xD1, 0x8A, 0x17, 0xFF, 0xD1, 0x8B, 0x17, 0xFF, 0xD1, 0x8B, 0x17, 0xFF,
+	0xD2, 0x8C, 0x19, 0xFF, 0xD4, 0x8F, 0x1D, 0xFF, 0xD7, 0x96, 0x2B, 0xFF, 0xDE, 0xA7, 0x4D, 0xFF,
+	0xE3, 0xB6, 0x69, 0xFF, 0xE4, 0xB8, 0x6D, 0xFF, 0xE3, 0xB6, 0x6A, 0xFF, 0xE3, 0xB7, 0x6A, 0xFF,
+	0xE3, 0xB7, 0x6B, 0xFF, 0xE4, 0xB7, 0x6B, 0xFF, 0xE4, 0xB7, 0x6B, 0xFF, 0xE5, 0xB8, 0x6B, 0xFF,
+	0xE4, 0xB9, 0x6B, 0xFF, 0xE5, 0xB9, 0x6B, 0xFF, 0xE5, 0xB9, 0x6C, 0xFF, 0xE6, 0xB9, 0x6C, 0xFF,
+	0xE6, 0xBA, 0x6D, 0xFF, 0xE5, 0xBA, 0x6D, 0xFF, 0xE5, 0xBB, 0x6D, 0xFF, 0xE5, 0xBB, 0x6D, 0xFF,
+	0xE5, 0xBB, 0x6D, 0xFF, 0xE5, 0xBB, 0x6D, 0xFF, 0xE6, 0xBB, 0x6D, 0xFF, 0xE6, 0xBB, 0x6D, 0xFF,
+	0xE7, 0xBC, 0x6D, 0xFF, 0xE6, 0xBC, 0x6E, 0xFF, 0xE6, 0xBC, 0x6E, 0xFF, 0xE6, 0xBC, 0x6D, 0xFF,
+	0xE6, 0xBC, 0x6E, 0xFF, 0xE6, 0xBC, 0x6F, 0xFF, 0xE7, 0xBC, 0x6F, 0xFF, 0xE7, 0xBD, 0x6F, 0xFF,
+	0xE7, 0xBD, 0x6F, 0xFF, 0xE7, 0xBD, 0x6F, 0xFF, 0xE7, 0xBD, 0x6F, 0xFF, 0xE7, 0xBD, 0x6F, 0xFF,
+	0xE7, 0xBD, 0x6F, 0xFF, 0xE7, 0xBD, 0x6F, 0xFF, 0xE7, 0xBD, 0x6F, 0xFF, 0xE7, 0xBD, 0x6F, 0xFF,
+	0xE7, 0xBD, 0x6F, 0xFF, 0xE7, 0xBD, 0x6F, 0xFF, 0xE7, 0xBD, 0x6F, 0xFF, 0xE7, 0xBD, 0x6F, 0xFF,
+	0xE7, 0xBD, 0x6F, 0xFF, 0xE7, 0xBD, 0x6F, 0xFF, 0xE7, 0xBC, 0x6F, 0xFF, 0xE6, 0xBC, 0x6F, 0xFF,
+	0xE6, 0xBC, 0x6E, 0xFF, 0xE6, 0xBC, 0x6E, 0xFF, 0xE6, 0xBC, 0x6E, 0xFF, 0xE6, 0xBC, 0x6E, 0xFF,
+	0xE7, 0xBC, 0x6E, 0xFF, 0xE6, 0xBB, 0x6E, 0xFF, 0xE6, 0xBB, 0x6D, 0xFF, 0xE5, 0xBB, 0x6D, 0xFF,
+	0xE5, 0xBB, 0x6D, 0xFF, 0xE5, 0xBB, 0x6D, 0xFF, 0xE5, 0xBB, 0x6D, 0xFF, 0xE5, 0xBA, 0x6D, 0xFF,
+	0xE5, 0xBA, 0x6D, 0xFF, 0xE6, 0xB9, 0x6C, 0xFF, 0xE5, 0xB9, 0x6C, 0xFF, 0xE5, 0xB9, 0x6C, 0xFF,
+	0xE5, 0xB9, 0x6C, 0xFF, 0xE5, 0xB9, 0x6B, 0xFF, 0xE4, 0xB8, 0x6B, 0xFF, 0xE4, 0xB8, 0x6B, 0xFF,
+	0xE3, 0xB7, 0x6B, 0xFF, 0xE3, 0xB7, 0x6B, 0xFF, 0xE3, 0xB7, 0x6A, 0xFF, 0xE3, 0xB7, 0x69, 0xFF,
+	0xE4, 0xB6, 0x6A, 0xFF, 0xE5, 0xB9, 0x71, 0xFF, 0xE4, 0xB9, 0x72, 0xFF, 0xDD, 0xA7, 0x4E, 0xFF,
+	0xD4, 0x8F, 0x1D, 0xFF, 0xD1, 0x88, 0x0F, 0xFF, 0xD2, 0x8B, 0x16, 0xFF, 0xD2, 0x8B, 0x18, 0xFF,
+	0xD1, 0x8A, 0x17, 0xFF, 0xD2, 0x8A, 0x16, 0xFF, 0xD4, 0x8B, 0x17, 0xFF, 0xD0, 0x87, 0x16, 0xFF,
+	0xC2, 0x7D, 0x14, 0xFF, 0xB4, 0x74, 0x11, 0xFD, 0xA6, 0x6A, 0x0E, 0xE7, 0x98, 0x61, 0x0B, 0xBA,
+	0x85, 0x55, 0x09, 0x62, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x01, 0x00, 0x0A,
+	0x00, 0x00, 0x00, 0x14, 0x26, 0x18, 0x03, 0x32, 0x88, 0x57, 0x0D, 0x8C, 0xA6, 0x6A, 0x10, 0xEF,
+	0xB5, 0x75, 0x12, 0xFF, 0xC6, 0x81, 0x14, 0xFF, 0xCE, 0x87, 0x16, 0xFF, 0xD0, 0x89, 0x17, 0xFF,
+	0xD2, 0x8B, 0x17, 0xFF, 0xD2, 0x8C, 0x18, 0xFF, 0xD2, 0x8C, 0x18, 0xFF, 0xD2, 0x8C, 0x18, 0xFF,
+	0xD3, 0x8E, 0x1A, 0xFF, 0xD5, 0x90, 0x1D, 0xFF, 0xD8, 0x97, 0x2A, 0xFF, 0xDD, 0xA7, 0x4A, 0xFF,
+	0xE2, 0xB4, 0x65, 0xFF, 0xE3, 0xB6, 0x69, 0xFF, 0xE3, 0xB5, 0x66, 0xFF, 0xE3, 0xB5, 0x67, 0xFF,
+	0xE3, 0xB5, 0x67, 0xFF, 0xE3, 0xB5, 0x67, 0xFF, 0xE4, 0xB6, 0x67, 0xFF, 0xE4, 0xB7, 0x67, 0xFF,
+	0xE4, 0xB8, 0x67, 0xFF, 0xE4, 0xB8, 0x67, 0xFF, 0xE5, 0xB8, 0x68, 0xFF, 0xE5, 0xB8, 0x68, 0xFF,
+	0xE5, 0xB9, 0x69, 0xFF, 0xE5, 0xB9, 0x69, 0xFF, 0xE5, 0xBA, 0x69, 0xFF, 0xE5, 0xBA, 0x69, 0xFF,
+	0xE5, 0xBA, 0x69, 0xFF, 0xE5, 0xBA, 0x69, 0xFF, 0xE5, 0xBA, 0x69, 0xFF, 0xE6, 0xBA, 0x69, 0xFF,
+	0xE6, 0xBA, 0x69, 0xFF, 0xE6, 0xBB, 0x6A, 0xFF, 0xE6, 0xBB, 0x6A, 0xFF, 0xE6, 0xBB, 0x69, 0xFF,
+	0xE6, 0xBB, 0x69, 0xFF, 0xE6, 0xBB, 0x6B, 0xFF, 0xE6, 0xBB, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF,
+	0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF,
+	0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF,
+	0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF,
+	0xE7, 0xBC, 0x6B, 0xFF, 0xE7, 0xBC, 0x6B, 0xFF, 0xE6, 0xBB, 0x6B, 0xFF, 0xE6, 0xBB, 0x6B, 0xFF,
+	0xE6, 0xBB, 0x6A, 0xFF, 0xE6, 0xBB, 0x6A, 0xFF, 0xE6, 0xBB, 0x6A, 0xFF, 0xE6, 0xBB, 0x6A, 0xFF,
+	0xE6, 0xBA, 0x6A, 0xFF, 0xE6, 0xBA, 0x6A, 0xFF, 0xE5, 0xBA, 0x69, 0xFF, 0xE5, 0xBA, 0x69, 0xFF,
+	0xE5, 0xBA, 0x69, 0xFF, 0xE5, 0xBA, 0x69, 0xFF, 0xE5, 0xBA, 0x69, 0xFF, 0xE5, 0xB9, 0x69, 0xFF,
+	0xE5, 0xB9, 0x69, 0xFF, 0xE5, 0xB8, 0x68, 0xFF, 0xE5, 0xB8, 0x68, 0xFF, 0xE5, 0xB8, 0x68, 0xFF,
+	0xE5, 0xB8, 0x68, 0xFF, 0xE4, 0xB7, 0x67, 0xFF, 0xE4, 0xB7, 0x67, 0xFF, 0xE3, 0xB6, 0x67, 0xFF,
+	0xE3, 0xB6, 0x67, 0xFF, 0xE3, 0xB5, 0x66, 0xFF, 0xE3, 0xB5, 0x66, 0xFF, 0xE3, 0xB5, 0x66, 0xFF,
+	0xE3, 0xB5, 0x66, 0xFF, 0xE4, 0xB7, 0x6C, 0xFF, 0xE4, 0xB6, 0x6C, 0xFF, 0xDD, 0xA6, 0x4B, 0xFF,
+	0xD5, 0x90, 0x1E, 0xFF, 0xD2, 0x89, 0x11, 0xFF, 0xD3, 0x8C, 0x17, 0xFF, 0xD3, 0x8D, 0x19, 0xFF,
+	0xD2, 0x8C, 0x17, 0xFF, 0xD2, 0x8B, 0x17, 0xFF, 0xD3, 0x8B, 0x17, 0xFF, 0xD0, 0x89, 0x17, 0xFF,
+	0xC9, 0x83, 0x16, 0xFF, 0xBF, 0x7B, 0x13, 0xFF, 0xB0, 0x72, 0x0F, 0xFF, 0xA3, 0x69, 0x0C, 0xF0,
+	0x91, 0x5E, 0x0A, 0x84, 0x16, 0x0E, 0x02, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0A, 0x06, 0x01, 0x0D,
+	0x43, 0x2A, 0x07, 0x2D, 0x67, 0x41, 0x0A, 0x5D, 0x91, 0x5C, 0x0E, 0xA9, 0xA8, 0x6C, 0x10, 0xF5,
+	0xB9, 0x78, 0x13, 0xFF, 0xCB, 0x85, 0x15, 0xFF, 0xD2, 0x8B, 0x17, 0xFF, 0xD2, 0x8B, 0x18, 0xFF,
+	0xD2, 0x8C, 0x18, 0xFF, 0xD3, 0x8D, 0x19, 0xFF, 0xD3, 0x8D, 0x19, 0xFF, 0xD3, 0x8D, 0x19, 0xFF,
+	0xD4, 0x8E, 0x1B, 0xFF, 0xD5, 0x90, 0x1D, 0xFF, 0xD7, 0x97, 0x29, 0xFF, 0xDD, 0xA6, 0x47, 0xFF,
+	0xE2, 0xB3, 0x61, 0xFF, 0xE3, 0xB5, 0x65, 0xFF, 0xE2, 0xB3, 0x62, 0xFF, 0xE3, 0xB3, 0x62, 0xFF,
+	0xE3, 0xB4, 0x62, 0xFF, 0xE3, 0xB4, 0x63, 0xFF, 0xE3, 0xB5, 0x63, 0xFF, 0xE4, 0xB5, 0x63, 0xFF,
+	0xE3, 0xB6, 0x63, 0xFF, 0xE4, 0xB6, 0x63, 0xFF, 0xE4, 0xB6, 0x64, 0xFF, 0xE4, 0xB7, 0x64, 0xFF,
+	0xE4, 0xB7, 0x65, 0xFF, 0xE5, 0xB8, 0x65, 0xFF, 0xE5, 0xB8, 0x65, 0xFF, 0xE5, 0xB8, 0x65, 0xFF,
+	0xE5, 0xB8, 0x65, 0xFF, 0xE5, 0xB9, 0x65, 0xFF, 0xE5, 0xB9, 0x65, 0xFF, 0xE5, 0xB9, 0x65, 0xFF,
+	0xE6, 0xB9, 0x66, 0xFF, 0xE6, 0xBA, 0x66, 0xFF, 0xE6, 0xBA, 0x66, 0xFF, 0xE6, 0xBA, 0x66, 0xFF,
+	0xE6, 0xBA, 0x66, 0xFF, 0xE6, 0xBA, 0x67, 0xFF, 0xE6, 0xBA, 0x67, 0xFF, 0xE6, 0xBB, 0x67, 0xFF,
+	0xE7, 0xBB, 0x67, 0xFF, 0xE7, 0xBB, 0x67, 0xFF, 0xE7, 0xBB, 0x67, 0xFF, 0xE7, 0xBB, 0x67, 0xFF,
+	0xE7, 0xBB, 0x67, 0xFF, 0xE7, 0xBB, 0x67, 0xFF, 0xE7, 0xBB, 0x67, 0xFF, 0xE7, 0xBB, 0x67, 0xFF,
+	0xE7, 0xBB, 0x67, 0xFF, 0xE7, 0xBB, 0x67, 0xFF, 0xE7, 0xBB, 0x67, 0xFF, 0xE7, 0xBB, 0x67, 0xFF,
+	0xE7, 0xBB, 0x67, 0xFF, 0xE6, 0xBB, 0x67, 0xFF, 0xE6, 0xBA, 0x67, 0xFF, 0xE6, 0xBA, 0x67, 0xFF,
+	0xE6, 0xBA, 0x66, 0xFF, 0xE6, 0xBA, 0x66, 0xFF, 0xE6, 0xBA, 0x66, 0xFF, 0xE6, 0xBA, 0x66, 0xFF,
+	0xE6, 0xB9, 0x66, 0xFF, 0xE6, 0xB9, 0x66, 0xFF, 0xE5, 0xB9, 0x66, 0xFF, 0xE5, 0xB9, 0x65, 0xFF,
+	0xE5, 0xB8, 0x65, 0xFF, 0xE5, 0xB8, 0x65, 0xFF, 0xE5, 0xB8, 0x65, 0xFF, 0xE5, 0xB8, 0x65, 0xFF,
+	0xE4, 0xB7, 0x65, 0xFF, 0xE5, 0xB7, 0x64, 0xFF, 0xE4, 0xB7, 0x64, 0xFF, 0xE4, 0xB7, 0x64, 0xFF,
+	0xE4, 0xB6, 0x64, 0xFF, 0xE4, 0xB6, 0x63, 0xFF, 0xE3, 0xB5, 0x63, 0xFF, 0xE3, 0xB5, 0x63, 0xFF,
+	0xE3, 0xB5, 0x63, 0xFF, 0xE3, 0xB4, 0x62, 0xFF, 0xE3, 0xB3, 0x62, 0xFF, 0xE3, 0xB3, 0x62, 0xFF,
+	0xE2, 0xB3, 0x62, 0xFF, 0xE3, 0xB5, 0x66, 0xFF, 0xE3, 0xB3, 0x64, 0xFF, 0xDD, 0xA4, 0x46, 0xFF,
+	0xD5, 0x91, 0x1E, 0xFF, 0xD2, 0x8B, 0x12, 0xFF, 0xD3, 0x8D, 0x18, 0xFF, 0xD3, 0x8E, 0x1A, 0xFF,
+	0xD3, 0x8D, 0x19, 0xFF, 0xD3, 0x8C, 0x18, 0xFF, 0xD3, 0x8C, 0x18, 0xFF, 0xD1, 0x8A, 0x17, 0xFF,
+	0xCD, 0x87, 0x17, 0xFF, 0xC5, 0x81, 0x15, 0xFF, 0xB6, 0x76, 0x11, 0xFF, 0xA9, 0x6D, 0x0E, 0xFE,
+	0x95, 0x61, 0x0D, 0x9B, 0x4B, 0x32, 0x08, 0x34, 0x00, 0x00, 0x00, 0x10, 0x05, 0x04, 0x01, 0x08,
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0A, 0x02, 0x11,
+	0x70, 0x47, 0x0B, 0x4B, 0x86, 0x56, 0x0E, 0x90, 0x9B, 0x63, 0x10, 0xCA, 0xAC, 0x6E, 0x11, 0xF9,
+	0xBD, 0x7A, 0x14, 0xFF, 0xCF, 0x89, 0x16, 0xFF, 0xD5, 0x8E, 0x18, 0xFF, 0xD3, 0x8D, 0x19, 0xFF,
+	0xD3, 0x8D, 0x19, 0xFF, 0xD4, 0x8E, 0x1A, 0xFF, 0xD4, 0x8E, 0x1A, 0xFF, 0xD4, 0x8E, 0x1A, 0xFF,
+	0xD4, 0x8F, 0x1B, 0xFF, 0xD4, 0x91, 0x1D, 0xFF, 0xD7, 0x96, 0x27, 0xFF, 0xDC, 0xA5, 0x44, 0xFF,
+	0xE1, 0xB2, 0x5D, 0xFF, 0xE2, 0xB3, 0x61, 0xFF, 0xE2, 0xB1, 0x5E, 0xFF, 0xE3, 0xB2, 0x5E, 0xFF,
+	0xE3, 0xB3, 0x5E, 0xFF, 0xE3, 0xB4, 0x5E, 0xFF, 0xE3, 0xB4, 0x5F, 0xFF, 0xE3, 0xB4, 0x5F, 0xFF,
+	0xE3, 0xB4, 0x60, 0xFF, 0xE3, 0xB4, 0x60, 0xFF, 0xE3, 0xB5, 0x60, 0xFF, 0xE3, 0xB5, 0x60, 0xFF,
+	0xE4, 0xB6, 0x61, 0xFF, 0xE4, 0xB6, 0x61, 0xFF, 0xE5, 0xB6, 0x61, 0xFF, 0xE5, 0xB6, 0x61, 0xFF,
+	0xE5, 0xB7, 0x61, 0xFF, 0xE5, 0xB7, 0x61, 0xFF, 0xE5, 0xB7, 0x61, 0xFF, 0xE5, 0xB7, 0x62, 0xFF,
+	0xE5, 0xB8, 0x62, 0xFF, 0xE6, 0xB8, 0x62, 0xFF, 0xE6, 0xB9, 0x62, 0xFF, 0xE6, 0xB9, 0x63, 0xFF,
+	0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF,
+	0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF,
+	0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x64, 0xFF, 0xE6, 0xB9, 0x64, 0xFF,
+	0xE6, 0xB9, 0x64, 0xFF, 0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF,
+	0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF,
+	0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB9, 0x63, 0xFF, 0xE6, 0xB8, 0x63, 0xFF,
+	0xE6, 0xB8, 0x62, 0xFF, 0xE6, 0xB8, 0x62, 0xFF, 0xE5, 0xB8, 0x62, 0xFF, 0xE5, 0xB7, 0x62, 0xFF,
+	0xE5, 0xB7, 0x61, 0xFF, 0xE5, 0xB6, 0x61, 0xFF, 0xE5, 0xB6, 0x61, 0xFF, 0xE4, 0xB6, 0x61, 0xFF,
+	0xE4, 0xB6, 0x61, 0xFF, 0xE4, 0xB6, 0x61, 0xFF, 0xE4, 0xB6, 0x61, 0xFF, 0xE3, 0xB6, 0x60, 0xFF,
+	0xE3, 0xB5, 0x60, 0xFF, 0xE3, 0xB4, 0x5F, 0xFF, 0xE3, 0xB4, 0x5F, 0xFF, 0xE3, 0xB4, 0x5F, 0xFF,
+	0xE3, 0xB4, 0x5F, 0xFF, 0xE3, 0xB3, 0x5E, 0xFF, 0xE3, 0xB2, 0x5E, 0xFF, 0xE3, 0xB2, 0x5E, 0xFF,
+	0xE2, 0xB1, 0x5E, 0xFF, 0xE2, 0xB2, 0x5F, 0xFF, 0xE2, 0xB0, 0x5B, 0xFF, 0xDC, 0xA3, 0x40, 0xFF,
+	0xD5, 0x92, 0x1E, 0xFF, 0xD3, 0x8C, 0x14, 0xFF, 0xD4, 0x8E, 0x19, 0xFF, 0xD4, 0x8F, 0x1B, 0xFF,
+	0xD3, 0x8E, 0x1A, 0xFF, 0xD3, 0x8D, 0x19, 0xFF, 0xD3, 0x8D, 0x18, 0xFF, 0xD2, 0x8B, 0x18, 0xFF,
+	0xD0, 0x8A, 0x17, 0xFF, 0xCA, 0x85, 0x16, 0xFF, 0xBC, 0x7A, 0x14, 0xFF, 0xAD, 0x70, 0x11, 0xFC,
+	0x97, 0x62, 0x0F, 0xAC, 0x64, 0x42, 0x0A, 0x55, 0x32, 0x22, 0x05, 0x27, 0x15, 0x0E, 0x02, 0x0E,
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x06, 0x01, 0x16,
+	0x82, 0x55, 0x0D, 0x66, 0x96, 0x62, 0x0F, 0xBD, 0xA5, 0x6B, 0x11, 0xE7, 0xB3, 0x74, 0x13, 0xFC,
+	0xC2, 0x7F, 0x15, 0xFF, 0xD1, 0x8B, 0x18, 0xFF, 0xD6, 0x8F, 0x19, 0xFF, 0xD4, 0x8E, 0x1A, 0xFF,
+	0xD4, 0x8E, 0x1A, 0xFF, 0xD4, 0x8F, 0x1A, 0xFF, 0xD5, 0x8F, 0x1B, 0xFF, 0xD5, 0x8F, 0x1B, 0xFF,
+	0xD5, 0x90, 0x1C, 0xFF, 0xD5, 0x91, 0x1C, 0xFF, 0xD7, 0x97, 0x26, 0xFF, 0xDC, 0xA5, 0x41, 0xFF,
+	0xE1, 0xB0, 0x5A, 0xFF, 0xE2, 0xB2, 0x5D, 0xFF, 0xE2, 0xB0, 0x5A, 0xFF, 0xE2, 0xB1, 0x5A, 0xFF,
+	0xE3, 0xB2, 0x5A, 0xFF, 0xE3, 0xB2, 0x5A, 0xFF, 0xE3, 0xB3, 0x5B, 0xFF, 0xE3, 0xB3, 0x5B, 0xFF,
+	0xE3, 0xB3, 0x5C, 0xFF, 0xE3, 0xB3, 0x5C, 0xFF, 0xE3, 0xB4, 0x5C, 0xFF, 0xE3, 0xB4, 0x5C, 0xFF,
+	0xE4, 0xB5, 0x5C, 0xFF, 0xE4, 0xB5, 0x5D, 0xFF, 0xE4, 0xB5, 0x5D, 0xFF, 0xE5, 0xB5, 0x5D, 0xFF,
+	0xE5, 0xB6, 0x5D, 0xFF, 0xE5, 0xB6, 0x5D, 0xFF, 0xE5, 0xB6, 0x5E, 0xFF, 0xE5, 0xB7, 0x5E, 0xFF,
+	0xE5, 0xB7, 0x5E, 0xFF, 0xE6, 0xB7, 0x5E, 0xFF, 0xE6, 0xB8, 0x5E, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF,
+	0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF,
+	0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF,
+	0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x60, 0xFF, 0xE6, 0xB8, 0x60, 0xFF,
+	0xE6, 0xB8, 0x60, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF,
+	0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF,
+	0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB8, 0x5F, 0xFF, 0xE6, 0xB7, 0x5F, 0xFF, 0xE6, 0xB7, 0x5F, 0xFF,
+	0xE6, 0xB7, 0x5E, 0xFF, 0xE6, 0xB7, 0x5E, 0xFF, 0xE5, 0xB7, 0x5E, 0xFF, 0xE5, 0xB6, 0x5E, 0xFF,
+	0xE5, 0xB6, 0x5E, 0xFF, 0xE5, 0xB6, 0x5D, 0xFF, 0xE5, 0xB5, 0x5D, 0xFF, 0xE4, 0xB5, 0x5D, 0xFF,
+	0xE4, 0xB5, 0x5D, 0xFF, 0xE4, 0xB5, 0x5D, 0xFF, 0xE4, 0xB5, 0x5C, 0xFF, 0xE3, 0xB4, 0x5C, 0xFF,
+	0xE3, 0xB4, 0x5B, 0xFF, 0xE3, 0xB3, 0x5B, 0xFF, 0xE3, 0xB3, 0x5B, 0xFF, 0xE3, 0xB3, 0x5B, 0xFF,
+	0xE3, 0xB2, 0x5B, 0xFF, 0xE2, 0xB2, 0x5A, 0xFF, 0xE2, 0xB1, 0x5A, 0xFF, 0xE2, 0xB1, 0x5A, 0xFF,
+	0xE2, 0xB0, 0x5A, 0xFF, 0xE2, 0xAF, 0x59, 0xFF, 0xE0, 0xAD, 0x53, 0xFF, 0xDC, 0xA1, 0x3C, 0xFF,
+	0xD6, 0x93, 0x1E, 0xFF, 0xD4, 0x8E, 0x16, 0xFF, 0xD4, 0x90, 0x1A, 0xFF, 0xD4, 0x90, 0x1C, 0xFF,
+	0xD4, 0x8F, 0x1B, 0xFF, 0xD4, 0x8E, 0x1A, 0xFF, 0xD3, 0x8D, 0x19, 0xFF, 0xD3, 0x8C, 0x18, 0xFF,
+	0xD3, 0x8C, 0x18, 0xFF, 0xCD, 0x88, 0x17, 0xFF, 0xBE, 0x7C, 0x15, 0xFF, 0xAF, 0x71, 0x13, 0xFD,
+	0x99, 0x63, 0x10, 0xBA, 0x72, 0x4A, 0x0B, 0x6E, 0x4E, 0x33, 0x07, 0x3A, 0x1A, 0x11, 0x02, 0x14,
+	0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01, 0x09, 0x06, 0x01, 0x1C,
+	0x8D, 0x5D, 0x0D, 0x80, 0xA2, 0x6B, 0x10, 0xE5, 0xAE, 0x73, 0x12, 0xFF, 0xBC, 0x7B, 0x15, 0xFF,
+	0xC7, 0x83, 0x17, 0xFF, 0xD2, 0x8C, 0x19, 0xFF, 0xD5, 0x8F, 0x1A, 0xFF, 0xD4, 0x8F, 0x1B, 0xFF,
+	0xD4, 0x8F, 0x1B, 0xFF, 0xD5, 0x90, 0x1B, 0xFF, 0xD5, 0x91, 0x1B, 0xFF, 0xD5, 0x91, 0x1C, 0xFF,
+	0xD6, 0x92, 0x1D, 0xFF, 0xD6, 0x92, 0x1C, 0xFF, 0xD7, 0x97, 0x24, 0xFF, 0xDD, 0xA4, 0x3F, 0xFF,
+	0xE1, 0xAF, 0x55, 0xFF, 0xE2, 0xB1, 0x59, 0xFF, 0xE2, 0xAF, 0x56, 0xFF, 0xE2, 0xB0, 0x56, 0xFF,
+	0xE2, 0xB0, 0x56, 0xFF, 0xE2, 0xB1, 0x57, 0xFF, 0xE2, 0xB1, 0x57, 0xFF, 0xE2, 0xB2, 0x58, 0xFF,
+	0xE3, 0xB2, 0x58, 0xFF, 0xE3, 0xB3, 0x58, 0xFF, 0xE3, 0xB3, 0x58, 0xFF, 0xE3, 0xB3, 0x58, 0xFF,
+	0xE4, 0xB3, 0x58, 0xFF, 0xE4, 0xB3, 0x59, 0xFF, 0xE4, 0xB4, 0x59, 0xFF, 0xE4, 0xB4, 0x59, 0xFF,
+	0xE5, 0xB5, 0x59, 0xFF, 0xE5, 0xB5, 0x59, 0xFF, 0xE5, 0xB6, 0x5A, 0xFF, 0xE5, 0xB6, 0x5A, 0xFF,
+	0xE5, 0xB6, 0x5B, 0xFF, 0xE5, 0xB6, 0x5A, 0xFF, 0xE5, 0xB7, 0x5A, 0xFF, 0xE5, 0xB7, 0x5B, 0xFF,
+	0xE5, 0xB7, 0x5B, 0xFF, 0xE5, 0xB7, 0x5A, 0xFF, 0xE5, 0xB6, 0x5B, 0xFF, 0xE6, 0xB6, 0x5B, 0xFF,
+	0xE6, 0xB6, 0x5B, 0xFF, 0xE6, 0xB6, 0x5B, 0xFF, 0xE6, 0xB6, 0x5B, 0xFF, 0xE6, 0xB6, 0x5B, 0xFF,
+	0xE6, 0xB6, 0x5B, 0xFF, 0xE6, 0xB7, 0x5C, 0xFF, 0xE6, 0xB7, 0x5C, 0xFF, 0xE6, 0xB7, 0x5C, 0xFF,
+	0xE6, 0xB7, 0x5C, 0xFF, 0xE6, 0xB7, 0x5C, 0xFF, 0xE6, 0xB6, 0x5B, 0xFF, 0xE6, 0xB6, 0x5B, 0xFF,
+	0xE6, 0xB6, 0x5B, 0xFF, 0xE6, 0xB6, 0x5B, 0xFF, 0xE5, 0xB6, 0x5C, 0xFF, 0xE5, 0xB6, 0x5B, 0xFF,
+	0xE5, 0xB6, 0x5B, 0xFF, 0xE5, 0xB6, 0x5A, 0xFF, 0xE5, 0xB6, 0x5B, 0xFF, 0xE5, 0xB6, 0x5B, 0xFF,
+	0xE5, 0xB6, 0x5A, 0xFF, 0xE5, 0xB6, 0x5A, 0xFF, 0xE5, 0xB6, 0x5B, 0xFF, 0xE5, 0xB5, 0x5B, 0xFF,
+	0xE5, 0xB5, 0x5A, 0xFF, 0xE5, 0xB5, 0x59, 0xFF, 0xE5, 0xB4, 0x59, 0xFF, 0xE4, 0xB3, 0x59, 0xFF,
+	0xE4, 0xB4, 0x59, 0xFF, 0xE4, 0xB4, 0x59, 0xFF, 0xE4, 0xB4, 0x58, 0xFF, 0xE3, 0xB3, 0x58, 0xFF,
+	0xE3, 0xB2, 0x57, 0xFF, 0xE3, 0xB2, 0x57, 0xFF, 0xE3, 0xB2, 0x57, 0xFF, 0xE3, 0xB1, 0x58, 0xFF,
+	0xE2, 0xB0, 0x57, 0xFF, 0xE2, 0xB0, 0x56, 0xFF, 0xE1, 0xB0, 0x56, 0xFF, 0xE2, 0xB0, 0x56, 0xFF,
+	0xE2, 0xAE, 0x56, 0xFF, 0xE1, 0xAD, 0x53, 0xFF, 0xDF, 0xA9, 0x4B, 0xFF, 0xDB, 0xA0, 0x37, 0xFF,
+	0xD6, 0x94, 0x1F, 0xFF, 0xD5, 0x90, 0x17, 0xFF, 0xD5, 0x91, 0x1B, 0xFF, 0xD5, 0x91, 0x1C, 0xFF,
+	0xD5, 0x90, 0x1C, 0xFF, 0xD5, 0x8F, 0x1B, 0xFF, 0xD4, 0x8E, 0x1A, 0xFF, 0xD4, 0x8D, 0x19, 0xFF,
+	0xD5, 0x8E, 0x19, 0xFF, 0xCF, 0x8A, 0x18, 0xFF, 0xBF, 0x7D, 0x15, 0xFF, 0xAE, 0x71, 0x13, 0xFD,
+	0x9B, 0x64, 0x10, 0xC7, 0x7E, 0x51, 0x0C, 0x86, 0x61, 0x3D, 0x08, 0x4C, 0x1D, 0x13, 0x03, 0x1A,
+	0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x0A, 0x21, 0x16, 0x04, 0x2A,
+	0x91, 0x60, 0x0E, 0x93, 0xA9, 0x70, 0x11, 0xF9, 0xB6, 0x78, 0x13, 0xFF, 0xC3, 0x81, 0x16, 0xFF,
+	0xCD, 0x88, 0x19, 0xFF, 0xD3, 0x8D, 0x1A, 0xFF, 0xD5, 0x90, 0x1B, 0xFF, 0xD4, 0x8F, 0x1B, 0xFF,
+	0xD4, 0x90, 0x1B, 0xFF, 0xD5, 0x91, 0x1B, 0xFF, 0xD5, 0x92, 0x1C, 0xFF, 0xD6, 0x92, 0x1D, 0xFF,
+	0xD6, 0x93, 0x1E, 0xFF, 0xD6, 0x93, 0x1C, 0xFF, 0xD8, 0x97, 0x23, 0xFF, 0xDC, 0xA3, 0x3B, 0xFF,
+	0xE1, 0xAD, 0x50, 0xFF, 0xE2, 0xAF, 0x54, 0xFF, 0xE2, 0xAF, 0x52, 0xFF, 0xE2, 0xAF, 0x52, 0xFF,
+	0xE2, 0xAF, 0x52, 0xFF, 0xE2, 0xB0, 0x53, 0xFF, 0xE2, 0xB0, 0x53, 0xFF, 0xE2, 0xB1, 0x54, 0xFF,
+	0xE3, 0xB1, 0x54, 0xFF, 0xE3, 0xB2, 0x54, 0xFF, 0xE3, 0xB2, 0x55, 0xFF, 0xE3, 0xB3, 0x55, 0xFF,
+	0xE4, 0xB3, 0x55, 0xFF, 0xE4, 0xB3, 0x55, 0xFF, 0xE4, 0xB3, 0x56, 0xFF, 0xE4, 0xB4, 0x56, 0xFF,
+	0xE4, 0xB4, 0x56, 0xFF, 0xE5, 0xB4, 0x56, 0xFF, 0xE5, 0xB5, 0x56, 0xFF, 0xE5, 0xB5, 0x57, 0xFF,
+	0xE5, 0xB5, 0x57, 0xFF, 0xE5, 0xB5, 0x57, 0xFF, 0xE5, 0xB6, 0x57, 0xFF, 0xE5, 0xB6, 0x57, 0xFF,
+	0xE5, 0xB6, 0x57, 0xFF, 0xE5, 0xB6, 0x57, 0xFF, 0xE5, 0xB6, 0x57, 0xFF, 0xE6, 0xB6, 0x58, 0xFF,
+	0xE6, 0xB6, 0x58, 0xFF, 0xE6, 0xB6, 0x58, 0xFF, 0xE6, 0xB6, 0x58, 0xFF, 0xE6, 0xB6, 0x58, 0xFF,
+	0xE6, 0xB6, 0x58, 0xFF, 0xE6, 0xB6, 0x58, 0xFF, 0xE6, 0xB7, 0x58, 0xFF, 0xE6, 0xB7, 0x58, 0xFF,
+	0xE6, 0xB7, 0x58, 0xFF, 0xE6, 0xB6, 0x58, 0xFF, 0xE6, 0xB6, 0x58, 0xFF, 0xE6, 0xB6, 0x58, 0xFF,
+	0xE6, 0xB6, 0x58, 0xFF, 0xE6, 0xB6, 0x58, 0xFF, 0xE5, 0xB6, 0x58, 0xFF, 0xE5, 0xB6, 0x58, 0xFF,
+	0xE5, 0xB6, 0x57, 0xFF, 0xE5, 0xB6, 0x57, 0xFF, 0xE5, 0xB6, 0x57, 0xFF, 0xE5, 0xB6, 0x57, 0xFF,
+	0xE5, 0xB6, 0x57, 0xFF, 0xE5, 0xB5, 0x57, 0xFF, 0xE5, 0xB5, 0x57, 0xFF, 0xE5, 0xB4, 0x57, 0xFF,
+	0xE5, 0xB5, 0x56, 0xFF, 0xE5, 0xB5, 0x56, 0xFF, 0xE4, 0xB4, 0x56, 0xFF, 0xE4, 0xB3, 0x56, 0xFF,
+	0xE4, 0xB3, 0x56, 0xFF, 0xE4, 0xB3, 0x55, 0xFF, 0xE4, 0xB3, 0x55, 0xFF, 0xE3, 0xB2, 0x54, 0xFF,
+	0xE3, 0xB1, 0x54, 0xFF, 0xE3, 0xB1, 0x54, 0xFF, 0xE3, 0xB1, 0x54, 0xFF, 0xE2, 0xB0, 0x54, 0xFF,
+	0xE2, 0xAF, 0x53, 0xFF, 0xE1, 0xB0, 0x52, 0xFF, 0xE1, 0xAF, 0x52, 0xFF, 0xE1, 0xAF, 0x53, 0xFF,
+	0xE2, 0xAE, 0x52, 0xFF, 0xE0, 0xAA, 0x4B, 0xFF, 0xDD, 0xA5, 0x40, 0xFF, 0xDA, 0x9D, 0x30, 0xFF,
+	0xD7, 0x95, 0x1F, 0xFF, 0xD6, 0x92, 0x1A, 0xFF, 0xD6, 0x93, 0x1C, 0xFF, 0xD5, 0x92, 0x1D, 0xFF,
+	0xD5, 0x91, 0x1C, 0xFF, 0xD5, 0x90, 0x1C, 0xFF, 0xD5, 0x8F, 0x1B, 0xFF, 0xD4, 0x8F, 0x1A, 0xFF,
+	0xD6, 0x8F, 0x1A, 0xFF, 0xD1, 0x8C, 0x19, 0xFF, 0xC1, 0x80, 0x16, 0xFF, 0xB1, 0x74, 0x13, 0xFD,
+	0xA1, 0x68, 0x11, 0xD7, 0x8C, 0x5A, 0x0E, 0xA2, 0x73, 0x49, 0x0B, 0x60, 0x22, 0x16, 0x03, 0x20,
+	0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x18, 0x36, 0x24, 0x06, 0x3F,
+	0x93, 0x60, 0x0F, 0x9F, 0xAF, 0x73, 0x12, 0xFB, 0xBD, 0x7D, 0x15, 0xFF, 0xCB, 0x87, 0x18, 0xFF,
+	0xD2, 0x8C, 0x1A, 0xFF, 0xD4, 0x8F, 0x1A, 0xFF, 0xD5, 0x90, 0x1B, 0xFF, 0xD5, 0x90, 0x1C, 0xFF,
+	0xD5, 0x91, 0x1C, 0xFF, 0xD5, 0x92, 0x1C, 0xFF, 0xD6, 0x93, 0x1D, 0xFF, 0xD6, 0x94, 0x1E, 0xFF,
+	0xD7, 0x94, 0x1E, 0xFF, 0xD7, 0x94, 0x1C, 0xFF, 0xD8, 0x97, 0x21, 0xFF, 0xDC, 0xA1, 0x36, 0xFF,
+	0xE0, 0xAA, 0x4A, 0xFF, 0xE1, 0xAD, 0x4E, 0xFF, 0xE1, 0xAE, 0x4E, 0xFF, 0xE1, 0xAF, 0x4E, 0xFF,
+	0xE1, 0xAE, 0x4E, 0xFF, 0xE1, 0xAF, 0x4F, 0xFF, 0xE2, 0xAF, 0x4F, 0xFF, 0xE2, 0xB0, 0x50, 0xFF,
+	0xE3, 0xB0, 0x50, 0xFF, 0xE3, 0xB1, 0x50, 0xFF, 0xE3, 0xB1, 0x51, 0xFF, 0xE3, 0xB2, 0x51, 0xFF,
+	0xE4, 0xB2, 0x52, 0xFF, 0xE4, 0xB2, 0x52, 0xFF, 0xE4, 0xB3, 0x52, 0xFF, 0xE4, 0xB3, 0x52, 0xFF,
+	0xE4, 0xB3, 0x52, 0xFF, 0xE4, 0xB3, 0x52, 0xFF, 0xE4, 0xB4, 0x52, 0xFF, 0xE4, 0xB4, 0x52, 0xFF,
+	0xE5, 0xB4, 0x53, 0xFF, 0xE5, 0xB4, 0x53, 0xFF, 0xE5, 0xB5, 0x53, 0xFF, 0xE5, 0xB5, 0x54, 0xFF,
+	0xE5, 0xB6, 0x54, 0xFF, 0xE5, 0xB5, 0x54, 0xFF, 0xE5, 0xB5, 0x54, 0xFF, 0xE6, 0xB6, 0x54, 0xFF,
+	0xE6, 0xB6, 0x54, 0xFF, 0xE6, 0xB6, 0x54, 0xFF, 0xE6, 0xB6, 0x54, 0xFF, 0xE6, 0xB6, 0x54, 0xFF,
+	0xE6, 0xB6, 0x54, 0xFF, 0xE6, 0xB6, 0x54, 0xFF, 0xE6, 0xB6, 0x54, 0xFF, 0xE6, 0xB6, 0x54, 0xFF,
+	0xE6, 0xB6, 0x54, 0xFF, 0xE6, 0xB6, 0x54, 0xFF, 0xE6, 0xB6, 0x54, 0xFF, 0xE6, 0xB6, 0x54, 0xFF,
+	0xE6, 0xB6, 0x54, 0xFF, 0xE6, 0xB6, 0x54, 0xFF, 0xE5, 0xB5, 0x54, 0xFF, 0xE5, 0xB5, 0x54, 0xFF,
+	0xE5, 0xB5, 0x54, 0xFF, 0xE5, 0xB5, 0x54, 0xFF, 0xE5, 0xB5, 0x53, 0xFF, 0xE5, 0xB5, 0x53, 0xFF,
+	0xE5, 0xB5, 0x53, 0xFF, 0xE5, 0xB4, 0x53, 0xFF, 0xE5, 0xB4, 0x53, 0xFF, 0xE4, 0xB3, 0x52, 0xFF,
+	0xE4, 0xB3, 0x52, 0xFF, 0xE4, 0xB4, 0x52, 0xFF, 0xE4, 0xB3, 0x52, 0xFF, 0xE4, 0xB3, 0x52, 0xFF,
+	0xE4, 0xB3, 0x52, 0xFF, 0xE4, 0xB2, 0x52, 0xFF, 0xE4, 0xB2, 0x52, 0xFF, 0xE3, 0xB2, 0x51, 0xFF,
+	0xE3, 0xB1, 0x51, 0xFF, 0xE2, 0xB0, 0x50, 0xFF, 0xE2, 0xB0, 0x50, 0xFF, 0xE2, 0xAF, 0x50, 0xFF,
+	0xE2, 0xAF, 0x4F, 0xFF, 0xE1, 0xAF, 0x4F, 0xFF, 0xE1, 0xAF, 0x4E, 0xFF, 0xE1, 0xAF, 0x50, 0xFF,
+	0xE1, 0xAD, 0x4F, 0xFF, 0xDE, 0xA8, 0x42, 0xFF, 0xDB, 0xA0, 0x33, 0xFF, 0xD9, 0x9B, 0x28, 0xFF,
+	0xD8, 0x96, 0x20, 0xFF, 0xD7, 0x94, 0x1C, 0xFF, 0xD7, 0x94, 0x1D, 0xFF, 0xD6, 0x93, 0x1D, 0xFF,
+	0xD6, 0x92, 0x1D, 0xFF, 0xD5, 0x91, 0x1C, 0xFF, 0xD5, 0x91, 0x1C, 0xFF, 0xD5, 0x90, 0x1B, 0xFF,
+	0xD7, 0x90, 0x1B, 0xFF, 0xD3, 0x8D, 0x1A, 0xFF, 0xC5, 0x83, 0x17, 0xFF, 0xB7, 0x79, 0x14, 0xFE,
+	0xA9, 0x6F, 0x12, 0xE9, 0x9A, 0x64, 0x10, 0xC2, 0x83, 0x55, 0x0E, 0x76, 0x28, 0x1A, 0x04, 0x25,
+	0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x02, 0x0A, 0x07, 0x01, 0x0F, 0x09, 0x07, 0x02, 0x27, 0x4A, 0x31, 0x08, 0x53,
+	0x95, 0x61, 0x10, 0xAB, 0xB3, 0x75, 0x13, 0xFC, 0xC2, 0x80, 0x16, 0xFF, 0xCF, 0x8B, 0x19, 0xFF,
+	0xD5, 0x8F, 0x1A, 0xFF, 0xD5, 0x90, 0x1B, 0xFF, 0xD5, 0x91, 0x1C, 0xFF, 0xD5, 0x91, 0x1C, 0xFF,
+	0xD6, 0x92, 0x1D, 0xFF, 0xD6, 0x93, 0x1D, 0xFF, 0xD7, 0x94, 0x1E, 0xFF, 0xD7, 0x95, 0x1F, 0xFF,
+	0xD7, 0x95, 0x1F, 0xFF, 0xD8, 0x95, 0x1D, 0xFF, 0xD9, 0x97, 0x21, 0xFF, 0xDC, 0x9F, 0x30, 0xFF,
+	0xDE, 0xA6, 0x40, 0xFF, 0xE0, 0xAB, 0x47, 0xFF, 0xE1, 0xAD, 0x4A, 0xFF, 0xE1, 0xAE, 0x4B, 0xFF,
+	0xE1, 0xAE, 0x4B, 0xFF, 0xE1, 0xAE, 0x4B, 0xFF, 0xE2, 0xAE, 0x4B, 0xFF, 0xE2, 0xAF, 0x4C, 0xFF,
+	0xE3, 0xAF, 0x4C, 0xFF, 0xE3, 0xB0, 0x4D, 0xFF, 0xE3, 0xB0, 0x4D, 0xFF, 0xE3, 0xB1, 0x4E, 0xFF,
+	0xE4, 0xB1, 0x4E, 0xFF, 0xE4, 0xB2, 0x4F, 0xFF, 0xE4, 0xB2, 0x4F, 0xFF, 0xE4, 0xB3, 0x4F, 0xFF,
+	0xE4, 0xB3, 0x4F, 0xFF, 0xE4, 0xB3, 0x4F, 0xFF, 0xE4, 0xB3, 0x4E, 0xFF, 0xE4, 0xB3, 0x4F, 0xFF,
+	0xE4, 0xB3, 0x4F, 0xFF, 0xE5, 0xB4, 0x4F, 0xFF, 0xE5, 0xB4, 0x50, 0xFF, 0xE5, 0xB5, 0x50, 0xFF,
+	0xE5, 0xB5, 0x51, 0xFF, 0xE5, 0xB5, 0x51, 0xFF, 0xE5, 0xB5, 0x51, 0xFF, 0xE6, 0xB5, 0x51, 0xFF,
+	0xE6, 0xB6, 0x51, 0xFF, 0xE6, 0xB6, 0x51, 0xFF, 0xE6, 0xB6, 0x51, 0xFF, 0xE6, 0xB6, 0x51, 0xFF,
+	0xE6, 0xB6, 0x51, 0xFF, 0xE6, 0xB6, 0x51, 0xFF, 0xE6, 0xB6, 0x51, 0xFF, 0xE6, 0xB6, 0x51, 0xFF,
+	0xE6, 0xB6, 0x51, 0xFF, 0xE6, 0xB6, 0x51, 0xFF, 0xE6, 0xB6, 0x51, 0xFF, 0xE6, 0xB6, 0x51, 0xFF,
+	0xE6, 0xB6, 0x51, 0xFF, 0xE6, 0xB5, 0x51, 0xFF, 0xE5, 0xB5, 0x51, 0xFF, 0xE5, 0xB5, 0x51, 0xFF,
+	0xE5, 0xB5, 0x51, 0xFF, 0xE5, 0xB5, 0x50, 0xFF, 0xE5, 0xB5, 0x50, 0xFF, 0xE5, 0xB5, 0x50, 0xFF,
+	0xE5, 0xB4, 0x50, 0xFF, 0xE5, 0xB4, 0x4F, 0xFF, 0xE4, 0xB3, 0x4F, 0xFF, 0xE4, 0xB3, 0x4F, 0xFF,
+	0xE4, 0xB3, 0x4E, 0xFF, 0xE4, 0xB3, 0x4F, 0xFF, 0xE4, 0xB3, 0x4F, 0xFF, 0xE4, 0xB3, 0x4F, 0xFF,
+	0xE4, 0xB2, 0x4F, 0xFF, 0xE4, 0xB1, 0x4F, 0xFF, 0xE4, 0xB0, 0x4E, 0xFF, 0xE3, 0xB1, 0x4E, 0xFF,
+	0xE3, 0xB0, 0x4D, 0xFF, 0xE2, 0xAF, 0x4D, 0xFF, 0xE2, 0xAE, 0x4C, 0xFF, 0xE2, 0xAF, 0x4C, 0xFF,
+	0xE2, 0xAF, 0x4B, 0xFF, 0xE1, 0xAE, 0x4B, 0xFF, 0xE1, 0xAD, 0x4B, 0xFF, 0xE1, 0xAE, 0x4D, 0xFF,
+	0xE0, 0xAD, 0x4B, 0xFF, 0xDD, 0xA6, 0x3C, 0xFF, 0xDA, 0x9D, 0x2A, 0xFF, 0xD9, 0x99, 0x23, 0xFF,
+	0xD8, 0x97, 0x20, 0xFF, 0xD8, 0x96, 0x1F, 0xFF, 0xD8, 0x95, 0x1E, 0xFF, 0xD7, 0x94, 0x1E, 0xFF,
+	0xD7, 0x93, 0x1E, 0xFF, 0xD6, 0x92, 0x1D, 0xFF, 0xD5, 0x92, 0x1D, 0xFF, 0xD5, 0x91, 0x1C, 0xFF,
+	0xD7, 0x91, 0x1C, 0xFF, 0xD4, 0x8F, 0x1B, 0xFF, 0xCA, 0x87, 0x18, 0xFF, 0xBE, 0x7F, 0x16, 0xFE,
+	0xB1, 0x75, 0x13, 0xF8, 0xA3, 0x6B, 0x11, 0xDD, 0x8C, 0x5C, 0x0F, 0x89, 0x2B, 0x1C, 0x05, 0x2A,
+	0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x05, 0x01, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x04, 0x11, 0x0C, 0x02, 0x15, 0x31, 0x21, 0x05, 0x36, 0x5E, 0x3F, 0x0A, 0x66,
+	0x97, 0x63, 0x10, 0xB6, 0xB4, 0x76, 0x14, 0xFD, 0xC3, 0x81, 0x17, 0xFF, 0xD1, 0x8C, 0x1A, 0xFF,
+	0xD6, 0x91, 0x1B, 0xFF, 0xD6, 0x91, 0x1C, 0xFF, 0xD6, 0x92, 0x1D, 0xFF, 0xD6, 0x93, 0x1D, 0xFF,
+	0xD7, 0x93, 0x1E, 0xFF, 0xD7, 0x94, 0x1F, 0xFF, 0xD7, 0x95, 0x1F, 0xFF, 0xD8, 0x96, 0x1F, 0xFF,
+	0xD8, 0x96, 0x20, 0xFF, 0xD9, 0x97, 0x1F, 0xFF, 0xD9, 0x98, 0x21, 0xFF, 0xDB, 0x9B, 0x28, 0xFF,
+	0xDC, 0xA0, 0x31, 0xFF, 0xDF, 0xA6, 0x3D, 0xFF, 0xE1, 0xAC, 0x47, 0xFF, 0xE1, 0xAD, 0x49, 0xFF,
+	0xE1, 0xAD, 0x47, 0xFF, 0xE1, 0xAD, 0x48, 0xFF, 0xE2, 0xAE, 0x48, 0xFF, 0xE2, 0xAE, 0x49, 0xFF,
+	0xE3, 0xAE, 0x49, 0xFF, 0xE3, 0xAE, 0x49, 0xFF, 0xE3, 0xAF, 0x49, 0xFF, 0xE3, 0xB0, 0x49, 0xFF,
+	0xE4, 0xB0, 0x4A, 0xFF, 0xE4, 0xB0, 0x4A, 0xFF, 0xE4, 0xB1, 0x4B, 0xFF, 0xE4, 0xB2, 0x4B, 0xFF,
+	0xE4, 0xB2, 0x4B, 0xFF, 0xE4, 0xB2, 0x4B, 0xFF, 0xE4, 0xB2, 0x4B, 0xFF, 0xE4, 0xB2, 0x4B, 0xFF,
+	0xE4, 0xB3, 0x4C, 0xFF, 0xE5, 0xB3, 0x4C, 0xFF, 0xE5, 0xB4, 0x4C, 0xFF, 0xE5, 0xB4, 0x4D, 0xFF,
+	0xE5, 0xB4, 0x4D, 0xFF, 0xE5, 0xB4, 0x4D, 0xFF, 0xE5, 0xB4, 0x4D, 0xFF, 0xE5, 0xB4, 0x4D, 0xFF,
+	0xE5, 0xB4, 0x4D, 0xFF, 0xE6, 0xB4, 0x4D, 0xFF, 0xE6, 0xB4, 0x4D, 0xFF, 0xE6, 0xB4, 0x4D, 0xFF,
+	0xE6, 0xB5, 0x4D, 0xFF, 0xE6, 0xB5, 0x4D, 0xFF, 0xE6, 0xB5, 0x4D, 0xFF, 0xE6, 0xB5, 0x4D, 0xFF,
+	0xE6, 0xB5, 0x4D, 0xFF, 0xE6, 0xB5, 0x4D, 0xFF, 0xE6, 0xB5, 0x4D, 0xFF, 0xE6, 0xB5, 0x4D, 0xFF,
+	0xE6, 0xB4, 0x4D, 0xFF, 0xE6, 0xB4, 0x4D, 0xFF, 0xE5, 0xB4, 0x4D, 0xFF, 0xE5, 0xB4, 0x4D, 0xFF,
+	0xE5, 0xB4, 0x4D, 0xFF, 0xE5, 0xB4, 0x4D, 0xFF, 0xE5, 0xB4, 0x4D, 0xFF, 0xE5, 0xB4, 0x4C, 0xFF,
+	0xE5, 0xB4, 0x4C, 0xFF, 0xE5, 0xB3, 0x4C, 0xFF, 0xE4, 0xB3, 0x4C, 0xFF, 0xE4, 0xB2, 0x4B, 0xFF,
+	0xE4, 0xB2, 0x4B, 0xFF, 0xE4, 0xB2, 0x4B, 0xFF, 0xE4, 0xB1, 0x4B, 0xFF, 0xE4, 0xB1, 0x4B, 0xFF,
+	0xE4, 0xB1, 0x4B, 0xFF, 0xE3, 0xB0, 0x4A, 0xFF, 0xE3, 0xAF, 0x4A, 0xFF, 0xE3, 0xAF, 0x49, 0xFF,
+	0xE3, 0xAF, 0x49, 0xFF, 0xE2, 0xAE, 0x49, 0xFF, 0xE2, 0xAE, 0x49, 0xFF, 0xE2, 0xAE, 0x48, 0xFF,
+	0xE2, 0xAE, 0x48, 0xFF, 0xE2, 0xAD, 0x47, 0xFF, 0xE1, 0xAC, 0x47, 0xFF, 0xE1, 0xAD, 0x48, 0xFF,
+	0xE0, 0xAC, 0x46, 0xFF, 0xDD, 0xA4, 0x38, 0xFF, 0xDA, 0x9C, 0x27, 0xFF, 0xD9, 0x99, 0x21, 0xFF,
+	0xD9, 0x98, 0x21, 0xFF, 0xD9, 0x97, 0x20, 0xFF, 0xD8, 0x96, 0x1F, 0xFF, 0xD8, 0x95, 0x1F, 0xFF,
+	0xD8, 0x94, 0x1F, 0xFF, 0xD7, 0x93, 0x1E, 0xFF, 0xD6, 0x93, 0x1D, 0xFF, 0xD6, 0x92, 0x1D, 0xFF,
+	0xD7, 0x92, 0x1D, 0xFF, 0xD5, 0x90, 0x1C, 0xFF, 0xD0, 0x8C, 0x1A, 0xFF, 0xC8, 0x86, 0x18, 0xFF,
+	0xB9, 0x7B, 0x15, 0xFF, 0xA9, 0x6F, 0x12, 0xF2, 0x92, 0x60, 0x0F, 0x98, 0x2B, 0x1D, 0x04, 0x2F,
+	0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x07, 0x02, 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x07, 0x15, 0x0E, 0x02, 0x1A, 0x46, 0x2F, 0x07, 0x43, 0x6D, 0x48, 0x0B, 0x77,
+	0x9A, 0x65, 0x11, 0xBF, 0xB4, 0x76, 0x14, 0xFC, 0xC4, 0x82, 0x17, 0xFF, 0xD2, 0x8E, 0x1B, 0xFF,
+	0xD6, 0x92, 0x1C, 0xFF, 0xD6, 0x92, 0x1D, 0xFF, 0xD7, 0x93, 0x1E, 0xFF, 0xD7, 0x94, 0x1E, 0xFF,
+	0xD7, 0x95, 0x1F, 0xFF, 0xD8, 0x96, 0x20, 0xFF, 0xD8, 0x96, 0x20, 0xFF, 0xD9, 0x97, 0x20, 0xFF,
+	0xD9, 0x97, 0x20, 0xFF, 0xDA, 0x98, 0x21, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xDA, 0x9A, 0x22, 0xFF,
+	0xDB, 0x9C, 0x26, 0xFF, 0xDE, 0xA3, 0x35, 0xFF, 0xE1, 0xAA, 0x43, 0xFF, 0xE1, 0xAC, 0x46, 0xFF,
+	0xE1, 0xAC, 0x44, 0xFF, 0xE1, 0xAC, 0x45, 0xFF, 0xE2, 0xAD, 0x45, 0xFF, 0xE2, 0xAD, 0x45, 0xFF,
+	0xE3, 0xAD, 0x45, 0xFF, 0xE3, 0xAD, 0x45, 0xFF, 0xE3, 0xAE, 0x45, 0xFF, 0xE3, 0xAF, 0x46, 0xFF,
+	0xE4, 0xAF, 0x46, 0xFF, 0xE4, 0xAF, 0x46, 0xFF, 0xE4, 0xB0, 0x47, 0xFF, 0xE4, 0xB1, 0x47, 0xFF,
+	0xE4, 0xB2, 0x47, 0xFF, 0xE4, 0xB2, 0x47, 0xFF, 0xE4, 0xB2, 0x48, 0xFF, 0xE4, 0xB2, 0x48, 0xFF,
+	0xE4, 0xB2, 0x48, 0xFF, 0xE5, 0xB3, 0x48, 0xFF, 0xE5, 0xB3, 0x49, 0xFF, 0xE5, 0xB3, 0x49, 0xFF,
+	0xE5, 0xB3, 0x49, 0xFF, 0xE5, 0xB3, 0x49, 0xFF, 0xE5, 0xB3, 0x49, 0xFF, 0xE5, 0xB3, 0x49, 0xFF,
+	0xE5, 0xB3, 0x4A, 0xFF, 0xE6, 0xB3, 0x4A, 0xFF, 0xE6, 0xB3, 0x4A, 0xFF, 0xE6, 0xB4, 0x4A, 0xFF,
+	0xE6, 0xB4, 0x4A, 0xFF, 0xE6, 0xB4, 0x4A, 0xFF, 0xE6, 0xB4, 0x4A, 0xFF, 0xE6, 0xB4, 0x4A, 0xFF,
+	0xE6, 0xB4, 0x4A, 0xFF, 0xE6, 0xB4, 0x4A, 0xFF, 0xE6, 0xB4, 0x4A, 0xFF, 0xE6, 0xB4, 0x4A, 0xFF,
+	0xE6, 0xB3, 0x4A, 0xFF, 0xE6, 0xB3, 0x4A, 0xFF, 0xE5, 0xB3, 0x4A, 0xFF, 0xE5, 0xB3, 0x49, 0xFF,
+	0xE5, 0xB3, 0x49, 0xFF, 0xE5, 0xB3, 0x49, 0xFF, 0xE5, 0xB3, 0x49, 0xFF, 0xE5, 0xB3, 0x49, 0xFF,
+	0xE5, 0xB3, 0x49, 0xFF, 0xE5, 0xB3, 0x48, 0xFF, 0xE4, 0xB2, 0x48, 0xFF, 0xE4, 0xB2, 0x48, 0xFF,
+	0xE4, 0xB1, 0x48, 0xFF, 0xE4, 0xB1, 0x47, 0xFF, 0xE4, 0xB0, 0x47, 0xFF, 0xE4, 0xB0, 0x47, 0xFF,
+	0xE4, 0xB0, 0x47, 0xFF, 0xE3, 0xAF, 0x47, 0xFF, 0xE3, 0xAF, 0x46, 0xFF, 0xE3, 0xAE, 0x46, 0xFF,
+	0xE3, 0xAE, 0x45, 0xFF, 0xE2, 0xAD, 0x45, 0xFF, 0xE2, 0xAD, 0x45, 0xFF, 0xE2, 0xAD, 0x45, 0xFF,
+	0xE2, 0xAD, 0x44, 0xFF, 0xE1, 0xAC, 0x44, 0xFF, 0xE1, 0xAB, 0x43, 0xFF, 0xE1, 0xAB, 0x44, 0xFF,
+	0xE0, 0xAA, 0x41, 0xFF, 0xDD, 0xA3, 0x34, 0xFF, 0xDA, 0x9C, 0x25, 0xFF, 0xD9, 0x99, 0x21, 0xFF,
+	0xD9, 0x98, 0x21, 0xFF, 0xD9, 0x98, 0x21, 0xFF, 0xD9, 0x97, 0x20, 0xFF, 0xD9, 0x97, 0x20, 0xFF,
+	0xD8, 0x96, 0x20, 0xFF, 0xD8, 0x95, 0x1F, 0xFF, 0xD7, 0x94, 0x1E, 0xFF, 0xD6, 0x93, 0x1D, 0xFF,
+	0xD6, 0x93, 0x1D, 0xFF, 0xD6, 0x92, 0x1D, 0xFF, 0xD5, 0x90, 0x1C, 0xFF, 0xCF, 0x8B, 0x1A, 0xFF,
+	0xC0, 0x7F, 0x16, 0xFF, 0xAF, 0x73, 0x12, 0xFF, 0x95, 0x62, 0x0F, 0xA4, 0x2A, 0x1B, 0x04, 0x37,
+	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x09, 0x16, 0x0E, 0x02, 0x20, 0x51, 0x36, 0x08, 0x4D, 0x75, 0x4D, 0x0C, 0x83,
+	0x9C, 0x67, 0x11, 0xC5, 0xB5, 0x77, 0x14, 0xFD, 0xC5, 0x84, 0x18, 0xFF, 0xD3, 0x90, 0x1C, 0xFF,
+	0xD8, 0x94, 0x1D, 0xFF, 0xD7, 0x94, 0x1E, 0xFF, 0xD7, 0x94, 0x1F, 0xFF, 0xD7, 0x95, 0x1F, 0xFF,
+	0xD8, 0x96, 0x20, 0xFF, 0xD9, 0x97, 0x20, 0xFF, 0xD9, 0x97, 0x21, 0xFF, 0xD9, 0x98, 0x21, 0xFF,
+	0xDA, 0x99, 0x21, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xDB, 0x9A, 0x23, 0xFF, 0xDA, 0x9A, 0x22, 0xFF,
+	0xDB, 0x9C, 0x24, 0xFF, 0xDD, 0xA2, 0x31, 0xFF, 0xE0, 0xA9, 0x3E, 0xFF, 0xE1, 0xAB, 0x42, 0xFF,
+	0xE1, 0xAB, 0x41, 0xFF, 0xE1, 0xAC, 0x42, 0xFF, 0xE2, 0xAC, 0x42, 0xFF, 0xE2, 0xAC, 0x42, 0xFF,
+	0xE3, 0xAC, 0x42, 0xFF, 0xE3, 0xAD, 0x43, 0xFF, 0xE3, 0xAE, 0x43, 0xFF, 0xE3, 0xAF, 0x43, 0xFF,
+	0xE4, 0xAF, 0x43, 0xFF, 0xE4, 0xAF, 0x43, 0xFF, 0xE4, 0xB0, 0x44, 0xFF, 0xE4, 0xB0, 0x44, 0xFF,
+	0xE4, 0xB1, 0x45, 0xFF, 0xE4, 0xB1, 0x45, 0xFF, 0xE5, 0xB1, 0x45, 0xFF, 0xE4, 0xB1, 0x45, 0xFF,
+	0xE5, 0xB2, 0x46, 0xFF, 0xE5, 0xB2, 0x46, 0xFF, 0xE5, 0xB2, 0x46, 0xFF, 0xE5, 0xB2, 0x46, 0xFF,
+	0xE5, 0xB2, 0x46, 0xFF, 0xE5, 0xB3, 0x46, 0xFF, 0xE5, 0xB3, 0x46, 0xFF, 0xE5, 0xB3, 0x47, 0xFF,
+	0xE6, 0xB3, 0x47, 0xFF, 0xE6, 0xB3, 0x47, 0xFF, 0xE7, 0xB3, 0x47, 0xFF, 0xE7, 0xB3, 0x47, 0xFF,
+	0xE7, 0xB4, 0x47, 0xFF, 0xE7, 0xB4, 0x47, 0xFF, 0xE7, 0xB4, 0x47, 0xFF, 0xE7, 0xB4, 0x47, 0xFF,
+	0xE7, 0xB4, 0x47, 0xFF, 0xE7, 0xB4, 0x47, 0xFF, 0xE7, 0xB3, 0x47, 0xFF, 0xE7, 0xB3, 0x47, 0xFF,
+	0xE7, 0xB3, 0x47, 0xFF, 0xE6, 0xB3, 0x47, 0xFF, 0xE6, 0xB3, 0x47, 0xFF, 0xE5, 0xB3, 0x47, 0xFF,
+	0xE5, 0xB3, 0x46, 0xFF, 0xE5, 0xB2, 0x46, 0xFF, 0xE5, 0xB2, 0x46, 0xFF, 0xE5, 0xB2, 0x46, 0xFF,
+	0xE5, 0xB2, 0x46, 0xFF, 0xE5, 0xB2, 0x45, 0xFF, 0xE5, 0xB2, 0x45, 0xFF, 0xE4, 0xB1, 0x45, 0xFF,
+	0xE4, 0xB1, 0x45, 0xFF, 0xE5, 0xB0, 0x45, 0xFF, 0xE4, 0xB0, 0x45, 0xFF, 0xE4, 0xB0, 0x44, 0xFF,
+	0xE4, 0xB0, 0x44, 0xFF, 0xE3, 0xAF, 0x43, 0xFF, 0xE3, 0xAF, 0x43, 0xFF, 0xE3, 0xAE, 0x43, 0xFF,
+	0xE3, 0xAE, 0x43, 0xFF, 0xE2, 0xAD, 0x43, 0xFF, 0xE2, 0xAD, 0x42, 0xFF, 0xE1, 0xAC, 0x42, 0xFF,
+	0xE1, 0xAC, 0x41, 0xFF, 0xE1, 0xAB, 0x42, 0xFF, 0xE1, 0xAA, 0x41, 0xFF, 0xE0, 0xA9, 0x3F, 0xFF,
+	0xE0, 0xA7, 0x3A, 0xFF, 0xDE, 0xA1, 0x2F, 0xFF, 0xDB, 0x9C, 0x24, 0xFF, 0xDA, 0x9A, 0x21, 0xFF,
+	0xDA, 0x9A, 0x22, 0xFF, 0xD9, 0x99, 0x22, 0xFF, 0xDA, 0x98, 0x21, 0xFF, 0xD9, 0x98, 0x21, 0xFF,
+	0xD9, 0x97, 0x20, 0xFF, 0xD8, 0x96, 0x20, 0xFF, 0xD8, 0x95, 0x1F, 0xFF, 0xD7, 0x94, 0x1E, 0xFF,
+	0xD7, 0x94, 0x1E, 0xFF, 0xD7, 0x93, 0x1D, 0xFF, 0xD8, 0x93, 0x1D, 0xFF, 0xD4, 0x90, 0x1C, 0xFF,
+	0xC5, 0x84, 0x18, 0xFF, 0xB4, 0x77, 0x14, 0xFF, 0x94, 0x61, 0x10, 0xAB, 0x20, 0x14, 0x03, 0x42,
+	0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x0F, 0x05, 0x04, 0x01, 0x05, 0x05, 0x04, 0x01, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x0B, 0x17, 0x0F, 0x02, 0x25, 0x5B, 0x3C, 0x09, 0x57, 0x7E, 0x53, 0x0D, 0x90,
+	0x9F, 0x6A, 0x11, 0xCC, 0xB6, 0x79, 0x15, 0xFD, 0xC6, 0x86, 0x18, 0xFF, 0xD5, 0x91, 0x1C, 0xFF,
+	0xD9, 0x95, 0x1E, 0xFF, 0xD7, 0x95, 0x1F, 0xFF, 0xD7, 0x96, 0x1F, 0xFF, 0xD8, 0x97, 0x20, 0xFF,
+	0xD8, 0x97, 0x20, 0xFF, 0xDA, 0x98, 0x21, 0xFF, 0xDA, 0x98, 0x21, 0xFF, 0xDA, 0x99, 0x22, 0xFF,
+	0xDA, 0x9A, 0x22, 0xFF, 0xDB, 0x9B, 0x23, 0xFF, 0xDB, 0x9B, 0x24, 0xFF, 0xDB, 0x9B, 0x23, 0xFF,
+	0xDB, 0x9D, 0x24, 0xFF, 0xDD, 0xA2, 0x2E, 0xFF, 0xE0, 0xA7, 0x38, 0xFF, 0xE1, 0xA9, 0x3D, 0xFF,
+	0xE1, 0xAB, 0x3F, 0xFF, 0xE1, 0xAB, 0x3F, 0xFF, 0xE2, 0xAB, 0x3F, 0xFF, 0xE2, 0xAB, 0x3F, 0xFF,
+	0xE3, 0xAD, 0x40, 0xFF, 0xE3, 0xAE, 0x40, 0xFF, 0xE3, 0xAF, 0x41, 0xFF, 0xE3, 0xAF, 0x41, 0xFF,
+	0xE4, 0xAF, 0x41, 0xFF, 0xE4, 0xAF, 0x41, 0xFF, 0xE4, 0xB0, 0x42, 0xFF, 0xE4, 0xB0, 0x42, 0xFF,
+	0xE5, 0xB0, 0x43, 0xFF, 0xE5, 0xB0, 0x43, 0xFF, 0xE5, 0xB0, 0x43, 0xFF, 0xE5, 0xB1, 0x43, 0xFF,
+	0xE5, 0xB1, 0x43, 0xFF, 0xE5, 0xB2, 0x44, 0xFF, 0xE5, 0xB2, 0x44, 0xFF, 0xE5, 0xB2, 0x44, 0xFF,
+	0xE5, 0xB2, 0x44, 0xFF, 0xE5, 0xB3, 0x44, 0xFF, 0xE5, 0xB3, 0x44, 0xFF, 0xE6, 0xB3, 0x45, 0xFF,
+	0xE6, 0xB3, 0x45, 0xFF, 0xE7, 0xB3, 0x45, 0xFF, 0xE7, 0xB3, 0x45, 0xFF, 0xE7, 0xB4, 0x45, 0xFF,
+	0xE7, 0xB4, 0x45, 0xFF, 0xE7, 0xB5, 0x45, 0xFF, 0xE7, 0xB5, 0x45, 0xFF, 0xE7, 0xB5, 0x45, 0xFF,
+	0xE7, 0xB4, 0x45, 0xFF, 0xE7, 0xB4, 0x45, 0xFF, 0xE7, 0xB3, 0x45, 0xFF, 0xE7, 0xB3, 0x45, 0xFF,
+	0xE7, 0xB3, 0x45, 0xFF, 0xE7, 0xB3, 0x45, 0xFF, 0xE6, 0xB4, 0x45, 0xFF, 0xE6, 0xB4, 0x45, 0xFF,
+	0xE5, 0xB3, 0x44, 0xFF, 0xE5, 0xB2, 0x44, 0xFF, 0xE5, 0xB2, 0x44, 0xFF, 0xE5, 0xB2, 0x44, 0xFF,
+	0xE5, 0xB1, 0x43, 0xFF, 0xE5, 0xB1, 0x43, 0xFF, 0xE5, 0xB1, 0x43, 0xFF, 0xE5, 0xB1, 0x43, 0xFF,
+	0xE5, 0xB1, 0x43, 0xFF, 0xE5, 0xB0, 0x43, 0xFF, 0xE5, 0xB0, 0x43, 0xFF, 0xE4, 0xB0, 0x42, 0xFF,
+	0xE4, 0xB0, 0x42, 0xFF, 0xE3, 0xAF, 0x41, 0xFF, 0xE3, 0xAF, 0x41, 0xFF, 0xE3, 0xAE, 0x41, 0xFF,
+	0xE3, 0xAE, 0x41, 0xFF, 0xE2, 0xAD, 0x40, 0xFF, 0xE2, 0xAD, 0x40, 0xFF, 0xE1, 0xAC, 0x3F, 0xFF,
+	0xE1, 0xAB, 0x3F, 0xFF, 0xE1, 0xAB, 0x40, 0xFF, 0xE1, 0xAA, 0x3F, 0xFF, 0xE0, 0xA7, 0x39, 0xFF,
+	0xDF, 0xA4, 0x32, 0xFF, 0xDE, 0xA0, 0x2A, 0xFF, 0xDC, 0x9C, 0x24, 0xFF, 0xDB, 0x9B, 0x22, 0xFF,
+	0xDA, 0x9B, 0x23, 0xFF, 0xDA, 0x9A, 0x23, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xDA, 0x99, 0x22, 0xFF,
+	0xD9, 0x98, 0x21, 0xFF, 0xD9, 0x98, 0x21, 0xFF, 0xD8, 0x97, 0x20, 0xFF, 0xD8, 0x96, 0x1F, 0xFF,
+	0xD7, 0x95, 0x1E, 0xFF, 0xD7, 0x94, 0x1E, 0xFF, 0xD9, 0x95, 0x1E, 0xFF, 0xD6, 0x93, 0x1D, 0xFF,
+	0xC9, 0x88, 0x19, 0xFF, 0xB8, 0x7B, 0x15, 0xFF, 0x94, 0x62, 0x11, 0xB2, 0x27, 0x18, 0x04, 0x51,
+	0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x0D, 0x1A, 0x11, 0x03, 0x29, 0x68, 0x45, 0x0C, 0x64, 0x88, 0x5B, 0x10, 0xA1,
+	0xA4, 0x6E, 0x13, 0xD6, 0xB8, 0x7C, 0x17, 0xFD, 0xC8, 0x88, 0x1A, 0xFF, 0xD6, 0x93, 0x1D, 0xFF,
+	0xDA, 0x97, 0x1F, 0xFF, 0xD8, 0x96, 0x1F, 0xFF, 0xD8, 0x97, 0x20, 0xFF, 0xD8, 0x98, 0x20, 0xFF,
+	0xD9, 0x99, 0x21, 0xFF, 0xDA, 0x99, 0x21, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xDB, 0x9B, 0x23, 0xFF,
+	0xDB, 0x9C, 0x23, 0xFF, 0xDB, 0x9C, 0x24, 0xFF, 0xDB, 0x9D, 0x24, 0xFF, 0xDB, 0x9D, 0x24, 0xFF,
+	0xDC, 0x9E, 0x25, 0xFF, 0xDD, 0xA1, 0x2A, 0xFF, 0xDF, 0xA4, 0x31, 0xFF, 0xE0, 0xA8, 0x38, 0xFF,
+	0xE1, 0xAB, 0x3E, 0xFF, 0xE2, 0xAC, 0x3F, 0xFF, 0xE2, 0xAC, 0x3E, 0xFF, 0xE3, 0xAC, 0x3E, 0xFF,
+	0xE3, 0xAD, 0x3E, 0xFF, 0xE3, 0xAD, 0x3F, 0xFF, 0xE3, 0xAF, 0x3F, 0xFF, 0xE4, 0xAF, 0x40, 0xFF,
+	0xE4, 0xAF, 0x40, 0xFF, 0xE4, 0xAF, 0x40, 0xFF, 0xE4, 0xB0, 0x41, 0xFF, 0xE4, 0xB0, 0x41, 0xFF,
+	0xE5, 0xB1, 0x41, 0xFF, 0xE6, 0xB1, 0x42, 0xFF, 0xE6, 0xB1, 0x42, 0xFF, 0xE5, 0xB1, 0x42, 0xFF,
+	0xE6, 0xB2, 0x42, 0xFF, 0xE6, 0xB2, 0x42, 0xFF, 0xE6, 0xB2, 0x43, 0xFF, 0xE6, 0xB3, 0x43, 0xFF,
+	0xE6, 0xB3, 0x43, 0xFF, 0xE6, 0xB3, 0x43, 0xFF, 0xE6, 0xB3, 0x43, 0xFF, 0xE6, 0xB4, 0x44, 0xFF,
+	0xE7, 0xB4, 0x44, 0xFF, 0xE7, 0xB4, 0x44, 0xFF, 0xE7, 0xB4, 0x44, 0xFF, 0xE7, 0xB4, 0x44, 0xFF,
+	0xE7, 0xB4, 0x44, 0xFF, 0xE7, 0xB5, 0x44, 0xFF, 0xE7, 0xB5, 0x44, 0xFF, 0xE7, 0xB5, 0x44, 0xFF,
+	0xE7, 0xB4, 0x44, 0xFF, 0xE7, 0xB4, 0x44, 0xFF, 0xE7, 0xB4, 0x44, 0xFF, 0xE7, 0xB4, 0x44, 0xFF,
+	0xE7, 0xB4, 0x44, 0xFF, 0xE7, 0xB4, 0x44, 0xFF, 0xE7, 0xB4, 0x44, 0xFF, 0xE6, 0xB4, 0x44, 0xFF,
+	0xE6, 0xB3, 0x43, 0xFF, 0xE6, 0xB3, 0x43, 0xFF, 0xE6, 0xB3, 0x43, 0xFF, 0xE6, 0xB3, 0x43, 0xFF,
+	0xE6, 0xB2, 0x43, 0xFF, 0xE5, 0xB2, 0x42, 0xFF, 0xE5, 0xB2, 0x42, 0xFF, 0xE5, 0xB1, 0x42, 0xFF,
+	0xE6, 0xB1, 0x42, 0xFF, 0xE6, 0xB0, 0x42, 0xFF, 0xE5, 0xB0, 0x42, 0xFF, 0xE5, 0xB0, 0x41, 0xFF,
+	0xE4, 0xB0, 0x40, 0xFF, 0xE4, 0xAF, 0x40, 0xFF, 0xE3, 0xAF, 0x40, 0xFF, 0xE3, 0xAE, 0x40, 0xFF,
+	0xE3, 0xAE, 0x3F, 0xFF, 0xE3, 0xAD, 0x3F, 0xFF, 0xE2, 0xAD, 0x3E, 0xFF, 0xE2, 0xAC, 0x3E, 0xFF,
+	0xE2, 0xAB, 0x3E, 0xFF, 0xE1, 0xAB, 0x3E, 0xFF, 0xE1, 0xA9, 0x3C, 0xFF, 0xE0, 0xA6, 0x34, 0xFF,
+	0xDE, 0xA2, 0x2C, 0xFF, 0xDD, 0x9F, 0x27, 0xFF, 0xDD, 0x9E, 0x24, 0xFF, 0xDC, 0x9D, 0x24, 0xFF,
+	0xDB, 0x9D, 0x24, 0xFF, 0xDB, 0x9C, 0x24, 0xFF, 0xDA, 0x9B, 0x23, 0xFF, 0xDA, 0x9A, 0x22, 0xFF,
+	0xDA, 0x99, 0x22, 0xFF, 0xD9, 0x99, 0x21, 0xFF, 0xD9, 0x98, 0x20, 0xFF, 0xD8, 0x97, 0x20, 0xFF,
+	0xD8, 0x96, 0x1F, 0xFF, 0xD8, 0x95, 0x1F, 0xFF, 0xDA, 0x96, 0x1F, 0xFF, 0xD7, 0x94, 0x1E, 0xFF,
+	0xCB, 0x8A, 0x1A, 0xFF, 0xBA, 0x7D, 0x16, 0xFF, 0x99, 0x66, 0x12, 0xBC, 0x49, 0x30, 0x08, 0x66,
+	0x03, 0x00, 0x00, 0x36, 0x05, 0x03, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x0E, 0x1C, 0x13, 0x03, 0x2D, 0x72, 0x4D, 0x0E, 0x70, 0x91, 0x62, 0x12, 0xB2,
+	0xA8, 0x72, 0x15, 0xDF, 0xBB, 0x80, 0x19, 0xFE, 0xCA, 0x8B, 0x1C, 0xFF, 0xD6, 0x95, 0x1E, 0xFF,
+	0xDA, 0x98, 0x20, 0xFF, 0xD9, 0x97, 0x20, 0xFF, 0xD9, 0x98, 0x20, 0xFF, 0xD9, 0x99, 0x21, 0xFF,
+	0xD9, 0x9A, 0x21, 0xFF, 0xDA, 0x9A, 0x22, 0xFF, 0xDA, 0x9A, 0x23, 0xFF, 0xDB, 0x9C, 0x24, 0xFF,
+	0xDC, 0x9D, 0x24, 0xFF, 0xDC, 0x9E, 0x24, 0xFF, 0xDC, 0x9F, 0x25, 0xFF, 0xDC, 0x9F, 0x25, 0xFF,
+	0xDD, 0xA0, 0x26, 0xFF, 0xDD, 0xA0, 0x27, 0xFF, 0xDE, 0xA2, 0x2A, 0xFF, 0xE0, 0xA6, 0x33, 0xFF,
+	0xE2, 0xAB, 0x3C, 0xFF, 0xE3, 0xAD, 0x3F, 0xFF, 0xE3, 0xAD, 0x3D, 0xFF, 0xE3, 0xAD, 0x3D, 0xFF,
+	0xE3, 0xAD, 0x3D, 0xFF, 0xE3, 0xAD, 0x3E, 0xFF, 0xE4, 0xAF, 0x3F, 0xFF, 0xE4, 0xAF, 0x3F, 0xFF,
+	0xE5, 0xAF, 0x40, 0xFF, 0xE5, 0xAF, 0x40, 0xFF, 0xE5, 0xB0, 0x40, 0xFF, 0xE5, 0xB1, 0x40, 0xFF,
+	0xE5, 0xB2, 0x41, 0xFF, 0xE6, 0xB2, 0x41, 0xFF, 0xE6, 0xB2, 0x42, 0xFF, 0xE6, 0xB2, 0x42, 0xFF,
+	0xE6, 0xB2, 0x42, 0xFF, 0xE7, 0xB3, 0x41, 0xFF, 0xE7, 0xB3, 0x42, 0xFF, 0xE7, 0xB4, 0x43, 0xFF,
+	0xE7, 0xB4, 0x43, 0xFF, 0xE7, 0xB4, 0x43, 0xFF, 0xE7, 0xB4, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF,
+	0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF,
+	0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF,
+	0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF,
+	0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB5, 0x43, 0xFF, 0xE7, 0xB4, 0x43, 0xFF, 0xE7, 0xB4, 0x43, 0xFF,
+	0xE7, 0xB4, 0x43, 0xFF, 0xE7, 0xB4, 0x43, 0xFF, 0xE7, 0xB4, 0x43, 0xFF, 0xE7, 0xB4, 0x43, 0xFF,
+	0xE6, 0xB3, 0x43, 0xFF, 0xE6, 0xB3, 0x42, 0xFF, 0xE6, 0xB2, 0x42, 0xFF, 0xE6, 0xB2, 0x41, 0xFF,
+	0xE6, 0xB1, 0x41, 0xFF, 0xE6, 0xB1, 0x41, 0xFF, 0xE6, 0xB0, 0x41, 0xFF, 0xE5, 0xB0, 0x40, 0xFF,
+	0xE5, 0xB0, 0x40, 0xFF, 0xE4, 0xAF, 0x3F, 0xFF, 0xE4, 0xAF, 0x3F, 0xFF, 0xE4, 0xAE, 0x3E, 0xFF,
+	0xE4, 0xAE, 0x3E, 0xFF, 0xE3, 0xAD, 0x3D, 0xFF, 0xE3, 0xAD, 0x3D, 0xFF, 0xE3, 0xAC, 0x3D, 0xFF,
+	0xE3, 0xAC, 0x3D, 0xFF, 0xE2, 0xAB, 0x3C, 0xFF, 0xE1, 0xA9, 0x38, 0xFF, 0xDF, 0xA4, 0x30, 0xFF,
+	0xDE, 0xA0, 0x28, 0xFF, 0xDD, 0x9F, 0x26, 0xFF, 0xDD, 0xA0, 0x26, 0xFF, 0xDC, 0x9F, 0x25, 0xFF,
+	0xDC, 0x9E, 0x25, 0xFF, 0xDB, 0x9D, 0x24, 0xFF, 0xDB, 0x9C, 0x23, 0xFF, 0xDB, 0x9B, 0x23, 0xFF,
+	0xDA, 0x9A, 0x22, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xD9, 0x98, 0x21, 0xFF, 0xD9, 0x97, 0x21, 0xFF,
+	0xD8, 0x96, 0x20, 0xFF, 0xD8, 0x96, 0x20, 0xFF, 0xDA, 0x97, 0x20, 0xFF, 0xD7, 0x94, 0x1F, 0xFF,
+	0xCB, 0x8B, 0x1B, 0xFF, 0xBC, 0x7F, 0x17, 0xFF, 0x9F, 0x6B, 0x13, 0xC7, 0x66, 0x44, 0x0C, 0x7B,
+	0x36, 0x23, 0x06, 0x47, 0x16, 0x0E, 0x02, 0x20, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
+	0x00, 0x00, 0x00, 0x0F, 0x1D, 0x14, 0x04, 0x30, 0x78, 0x51, 0x0F, 0x79, 0x96, 0x66, 0x13, 0xBE,
+	0xAD, 0x75, 0x16, 0xE6, 0xBF, 0x82, 0x19, 0xFE, 0xCC, 0x8D, 0x1C, 0xFF, 0xD7, 0x96, 0x1F, 0xFF,
+	0xDA, 0x98, 0x20, 0xFF, 0xDA, 0x98, 0x21, 0xFF, 0xDA, 0x98, 0x21, 0xFF, 0xDA, 0x9A, 0x21, 0xFF,
+	0xDA, 0x9B, 0x22, 0xFF, 0xDA, 0x9B, 0x23, 0xFF, 0xDB, 0x9C, 0x24, 0xFF, 0xDC, 0x9D, 0x24, 0xFF,
+	0xDD, 0x9E, 0x25, 0xFF, 0xDD, 0x9F, 0x25, 0xFF, 0xDD, 0xA0, 0x26, 0xFF, 0xDD, 0xA1, 0x26, 0xFF,
+	0xDE, 0xA1, 0x27, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDE, 0xA2, 0x28, 0xFF, 0xE0, 0xA6, 0x2F, 0xFF,
+	0xE2, 0xAA, 0x37, 0xFF, 0xE3, 0xAD, 0x3B, 0xFF, 0xE3, 0xAD, 0x3C, 0xFF, 0xE3, 0xAE, 0x3D, 0xFF,
+	0xE3, 0xAE, 0x3D, 0xFF, 0xE3, 0xAE, 0x3D, 0xFF, 0xE4, 0xAF, 0x3E, 0xFF, 0xE5, 0xAF, 0x3E, 0xFF,
+	0xE5, 0xAF, 0x3F, 0xFF, 0xE5, 0xB0, 0x3F, 0xFF, 0xE5, 0xB1, 0x3F, 0xFF, 0xE5, 0xB1, 0x3F, 0xFF,
+	0xE6, 0xB2, 0x3F, 0xFF, 0xE6, 0xB2, 0x40, 0xFF, 0xE6, 0xB3, 0x40, 0xFF, 0xE6, 0xB3, 0x41, 0xFF,
+	0xE7, 0xB3, 0x41, 0xFF, 0xE7, 0xB4, 0x40, 0xFF, 0xE8, 0xB4, 0x41, 0xFF, 0xE7, 0xB4, 0x42, 0xFF,
+	0xE7, 0xB4, 0x42, 0xFF, 0xE7, 0xB5, 0x42, 0xFF, 0xE7, 0xB5, 0x42, 0xFF, 0xE8, 0xB5, 0x42, 0xFF,
+	0xE8, 0xB5, 0x42, 0xFF, 0xE8, 0xB6, 0x42, 0xFF, 0xE8, 0xB6, 0x42, 0xFF, 0xE8, 0xB6, 0x42, 0xFF,
+	0xE8, 0xB6, 0x42, 0xFF, 0xE8, 0xB6, 0x42, 0xFF, 0xE8, 0xB6, 0x42, 0xFF, 0xE8, 0xB6, 0x42, 0xFF,
+	0xE8, 0xB6, 0x42, 0xFF, 0xE8, 0xB6, 0x42, 0xFF, 0xE8, 0xB6, 0x42, 0xFF, 0xE8, 0xB6, 0x42, 0xFF,
+	0xE8, 0xB5, 0x42, 0xFF, 0xE8, 0xB5, 0x42, 0xFF, 0xE7, 0xB5, 0x42, 0xFF, 0xE7, 0xB4, 0x42, 0xFF,
+	0xE7, 0xB4, 0x42, 0xFF, 0xE7, 0xB4, 0x42, 0xFF, 0xE8, 0xB4, 0x42, 0xFF, 0xE7, 0xB4, 0x42, 0xFF,
+	0xE7, 0xB4, 0x41, 0xFF, 0xE6, 0xB3, 0x41, 0xFF, 0xE6, 0xB3, 0x40, 0xFF, 0xE6, 0xB2, 0x40, 0xFF,
+	0xE6, 0xB2, 0x40, 0xFF, 0xE6, 0xB2, 0x40, 0xFF, 0xE6, 0xB1, 0x40, 0xFF, 0xE5, 0xB0, 0x3F, 0xFF,
+	0xE5, 0xB0, 0x3F, 0xFF, 0xE4, 0xAF, 0x3E, 0xFF, 0xE4, 0xAF, 0x3E, 0xFF, 0xE4, 0xAE, 0x3E, 0xFF,
+	0xE4, 0xAE, 0x3D, 0xFF, 0xE4, 0xAE, 0x3D, 0xFF, 0xE3, 0xAD, 0x3D, 0xFF, 0xE3, 0xAD, 0x3D, 0xFF,
+	0xE3, 0xAC, 0x3C, 0xFF, 0xE2, 0xAA, 0x38, 0xFF, 0xE1, 0xA8, 0x33, 0xFF, 0xE0, 0xA4, 0x2C, 0xFF,
+	0xDF, 0xA1, 0x27, 0xFF, 0xDE, 0xA1, 0x26, 0xFF, 0xDD, 0xA1, 0x27, 0xFF, 0xDD, 0xA0, 0x26, 0xFF,
+	0xDD, 0x9F, 0x26, 0xFF, 0xDC, 0x9E, 0x25, 0xFF, 0xDC, 0x9E, 0x24, 0xFF, 0xDB, 0x9D, 0x23, 0xFF,
+	0xDB, 0x9B, 0x23, 0xFF, 0xDA, 0x9A, 0x22, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xD9, 0x98, 0x21, 0xFF,
+	0xD9, 0x98, 0x21, 0xFF, 0xD9, 0x97, 0x21, 0xFF, 0xDA, 0x98, 0x20, 0xFF, 0xD8, 0x96, 0x1F, 0xFF,
+	0xCD, 0x8C, 0x1B, 0xFF, 0xBE, 0x81, 0x18, 0xFF, 0xA3, 0x6E, 0x14, 0xCE, 0x73, 0x4D, 0x0E, 0x8A,
+	0x4A, 0x31, 0x08, 0x54, 0x1C, 0x13, 0x03, 0x26, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05,
+	0x00, 0x00, 0x00, 0x11, 0x1E, 0x14, 0x04, 0x33, 0x7B, 0x54, 0x0F, 0x7F, 0x9A, 0x69, 0x13, 0xC5,
+	0xB0, 0x78, 0x16, 0xEA, 0xC3, 0x84, 0x1A, 0xFE, 0xCF, 0x8E, 0x1D, 0xFF, 0xD8, 0x97, 0x20, 0xFF,
+	0xDB, 0x99, 0x21, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xDA, 0x99, 0x22, 0xFF, 0xDA, 0x9A, 0x22, 0xFF,
+	0xDB, 0x9B, 0x23, 0xFF, 0xDB, 0x9D, 0x24, 0xFF, 0xDC, 0x9E, 0x25, 0xFF, 0xDC, 0x9E, 0x25, 0xFF,
+	0xDD, 0x9F, 0x25, 0xFF, 0xDD, 0xA0, 0x26, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDE, 0xA2, 0x27, 0xFF,
+	0xDF, 0xA3, 0x28, 0xFF, 0xDF, 0xA3, 0x28, 0xFF, 0xE0, 0xA3, 0x29, 0xFF, 0xE1, 0xA6, 0x2C, 0xFF,
+	0xE2, 0xA9, 0x31, 0xFF, 0xE2, 0xAB, 0x36, 0xFF, 0xE3, 0xAE, 0x3B, 0xFF, 0xE3, 0xAF, 0x3D, 0xFF,
+	0xE4, 0xAF, 0x3D, 0xFF, 0xE4, 0xAF, 0x3D, 0xFF, 0xE5, 0xAF, 0x3D, 0xFF, 0xE5, 0xAF, 0x3D, 0xFF,
+	0xE5, 0xB0, 0x3E, 0xFF, 0xE5, 0xB1, 0x3E, 0xFF, 0xE5, 0xB1, 0x3E, 0xFF, 0xE6, 0xB2, 0x3E, 0xFF,
+	0xE6, 0xB2, 0x3E, 0xFF, 0xE6, 0xB3, 0x3E, 0xFF, 0xE6, 0xB3, 0x3F, 0xFF, 0xE7, 0xB4, 0x3F, 0xFF,
+	0xE7, 0xB4, 0x40, 0xFF, 0xE8, 0xB5, 0x40, 0xFF, 0xE8, 0xB5, 0x40, 0xFF, 0xE8, 0xB5, 0x40, 0xFF,
+	0xE8, 0xB5, 0x40, 0xFF, 0xE8, 0xB5, 0x40, 0xFF, 0xE8, 0xB6, 0x41, 0xFF, 0xE9, 0xB6, 0x41, 0xFF,
+	0xE9, 0xB6, 0x41, 0xFF, 0xE9, 0xB6, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF,
+	0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF,
+	0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB6, 0x41, 0xFF,
+	0xE9, 0xB6, 0x41, 0xFF, 0xE8, 0xB6, 0x41, 0xFF, 0xE8, 0xB6, 0x41, 0xFF, 0xE8, 0xB5, 0x41, 0xFF,
+	0xE8, 0xB5, 0x41, 0xFF, 0xE8, 0xB5, 0x40, 0xFF, 0xE8, 0xB5, 0x40, 0xFF, 0xE8, 0xB5, 0x40, 0xFF,
+	0xE7, 0xB4, 0x40, 0xFF, 0xE7, 0xB4, 0x3F, 0xFF, 0xE7, 0xB3, 0x3F, 0xFF, 0xE7, 0xB3, 0x3F, 0xFF,
+	0xE6, 0xB3, 0x3F, 0xFF, 0xE6, 0xB3, 0x3E, 0xFF, 0xE6, 0xB2, 0x3E, 0xFF, 0xE6, 0xB1, 0x3E, 0xFF,
+	0xE5, 0xB0, 0x3E, 0xFF, 0xE5, 0xB0, 0x3D, 0xFF, 0xE5, 0xAF, 0x3D, 0xFF, 0xE5, 0xAF, 0x3D, 0xFF,
+	0xE5, 0xAF, 0x3D, 0xFF, 0xE4, 0xAE, 0x3C, 0xFF, 0xE4, 0xAE, 0x3C, 0xFF, 0xE3, 0xAE, 0x3D, 0xFF,
+	0xE3, 0xAD, 0x3B, 0xFF, 0xE2, 0xAA, 0x34, 0xFF, 0xE1, 0xA7, 0x2D, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF,
+	0xE0, 0xA3, 0x29, 0xFF, 0xDF, 0xA2, 0x28, 0xFF, 0xDE, 0xA2, 0x28, 0xFF, 0xDE, 0xA1, 0x27, 0xFF,
+	0xDE, 0xA0, 0x26, 0xFF, 0xDD, 0x9F, 0x25, 0xFF, 0xDD, 0x9F, 0x25, 0xFF, 0xDC, 0x9E, 0x24, 0xFF,
+	0xDB, 0x9C, 0x24, 0xFF, 0xDA, 0x9B, 0x23, 0xFF, 0xDA, 0x9A, 0x22, 0xFF, 0xDA, 0x99, 0x22, 0xFF,
+	0xDA, 0x99, 0x22, 0xFF, 0xDA, 0x98, 0x22, 0xFF, 0xDB, 0x99, 0x21, 0xFF, 0xD8, 0x97, 0x20, 0xFF,
+	0xCE, 0x8E, 0x1C, 0xFF, 0xC0, 0x82, 0x18, 0xFF, 0xA7, 0x70, 0x14, 0xD2, 0x7B, 0x53, 0x0F, 0x94,
+	0x55, 0x39, 0x0A, 0x5D, 0x1F, 0x15, 0x04, 0x2B, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x13, 0x1D, 0x14, 0x04, 0x36, 0x7C, 0x55, 0x0F, 0x83, 0x9C, 0x6B, 0x14, 0xCA,
+	0xB3, 0x7A, 0x17, 0xED, 0xC5, 0x86, 0x1A, 0xFE, 0xD0, 0x90, 0x1E, 0xFF, 0xD8, 0x98, 0x21, 0xFF,
+	0xDB, 0x9A, 0x22, 0xFF, 0xDA, 0x9A, 0x22, 0xFF, 0xDB, 0x9A, 0x23, 0xFF, 0xDB, 0x9B, 0x23, 0xFF,
+	0xDC, 0x9C, 0x24, 0xFF, 0xDC, 0x9E, 0x25, 0xFF, 0xDD, 0x9F, 0x26, 0xFF, 0xDD, 0x9F, 0x25, 0xFF,
+	0xDD, 0xA0, 0x26, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDF, 0xA2, 0x28, 0xFF, 0xDF, 0xA3, 0x28, 0xFF,
+	0xE0, 0xA4, 0x29, 0xFF, 0xE0, 0xA4, 0x29, 0xFF, 0xE0, 0xA4, 0x29, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF,
+	0xE2, 0xA8, 0x2D, 0xFF, 0xE2, 0xAA, 0x32, 0xFF, 0xE3, 0xAD, 0x38, 0xFF, 0xE3, 0xAF, 0x3B, 0xFF,
+	0xE4, 0xAF, 0x3D, 0xFF, 0xE5, 0xB0, 0x3D, 0xFF, 0xE5, 0xB0, 0x3D, 0xFF, 0xE5, 0xB0, 0x3D, 0xFF,
+	0xE5, 0xB1, 0x3D, 0xFF, 0xE6, 0xB2, 0x3E, 0xFF, 0xE6, 0xB2, 0x3E, 0xFF, 0xE7, 0xB3, 0x3E, 0xFF,
+	0xE6, 0xB3, 0x3E, 0xFF, 0xE6, 0xB3, 0x3E, 0xFF, 0xE7, 0xB4, 0x3F, 0xFF, 0xE7, 0xB5, 0x3F, 0xFF,
+	0xE8, 0xB5, 0x3F, 0xFF, 0xE8, 0xB5, 0x40, 0xFF, 0xE8, 0xB6, 0x40, 0xFF, 0xE8, 0xB6, 0x40, 0xFF,
+	0xE8, 0xB6, 0x40, 0xFF, 0xE8, 0xB6, 0x40, 0xFF, 0xE8, 0xB7, 0x40, 0xFF, 0xE9, 0xB6, 0x41, 0xFF,
+	0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF,
+	0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF,
+	0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF,
+	0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB6, 0x41, 0xFF, 0xE8, 0xB7, 0x41, 0xFF, 0xE8, 0xB6, 0x41, 0xFF,
+	0xE8, 0xB6, 0x40, 0xFF, 0xE8, 0xB6, 0x40, 0xFF, 0xE8, 0xB6, 0x40, 0xFF, 0xE8, 0xB6, 0x40, 0xFF,
+	0xE8, 0xB5, 0x3F, 0xFF, 0xE8, 0xB5, 0x3F, 0xFF, 0xE8, 0xB4, 0x3F, 0xFF, 0xE8, 0xB4, 0x3F, 0xFF,
+	0xE7, 0xB4, 0x3F, 0xFF, 0xE6, 0xB3, 0x3E, 0xFF, 0xE6, 0xB3, 0x3E, 0xFF, 0xE7, 0xB2, 0x3E, 0xFF,
+	0xE6, 0xB1, 0x3E, 0xFF, 0xE6, 0xB1, 0x3D, 0xFF, 0xE5, 0xB0, 0x3D, 0xFF, 0xE5, 0xB0, 0x3D, 0xFF,
+	0xE5, 0xAF, 0x3D, 0xFF, 0xE5, 0xAF, 0x3C, 0xFF, 0xE4, 0xAE, 0x3C, 0xFF, 0xE4, 0xAD, 0x3A, 0xFF,
+	0xE3, 0xAC, 0x37, 0xFF, 0xE2, 0xA9, 0x30, 0xFF, 0xE1, 0xA7, 0x2B, 0xFF, 0xE1, 0xA5, 0x29, 0xFF,
+	0xE0, 0xA5, 0x2A, 0xFF, 0xDF, 0xA4, 0x29, 0xFF, 0xDF, 0xA3, 0x29, 0xFF, 0xDE, 0xA2, 0x28, 0xFF,
+	0xDE, 0xA1, 0x27, 0xFF, 0xDE, 0xA0, 0x26, 0xFF, 0xDE, 0xA0, 0x26, 0xFF, 0xDD, 0x9F, 0x25, 0xFF,
+	0xDC, 0x9D, 0x25, 0xFF, 0xDB, 0x9C, 0x24, 0xFF, 0xDB, 0x9B, 0x23, 0xFF, 0xDA, 0x9B, 0x22, 0xFF,
+	0xDA, 0x9A, 0x22, 0xFF, 0xDA, 0x9A, 0x22, 0xFF, 0xDB, 0x9A, 0x22, 0xFF, 0xD9, 0x98, 0x20, 0xFF,
+	0xCF, 0x8F, 0x1D, 0xFF, 0xC2, 0x83, 0x19, 0xFF, 0xA9, 0x72, 0x15, 0xD5, 0x7F, 0x56, 0x10, 0x9A,
+	0x59, 0x3D, 0x0B, 0x63, 0x20, 0x15, 0x04, 0x2F, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x04,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x08,
+	0x00, 0x00, 0x00, 0x15, 0x1C, 0x13, 0x04, 0x39, 0x7C, 0x54, 0x10, 0x86, 0x9E, 0x6B, 0x15, 0xCC,
+	0xB3, 0x7B, 0x18, 0xED, 0xC6, 0x88, 0x1B, 0xFE, 0xD1, 0x91, 0x1F, 0xFF, 0xD9, 0x98, 0x22, 0xFF,
+	0xDC, 0x9B, 0x23, 0xFF, 0xDB, 0x9B, 0x23, 0xFF, 0xDB, 0x9C, 0x23, 0xFF, 0xDC, 0x9D, 0x24, 0xFF,
+	0xDD, 0x9E, 0x25, 0xFF, 0xDD, 0x9E, 0x26, 0xFF, 0xDE, 0x9F, 0x27, 0xFF, 0xDE, 0xA0, 0x26, 0xFF,
+	0xDE, 0xA1, 0x27, 0xFF, 0xDF, 0xA2, 0x28, 0xFF, 0xE0, 0xA3, 0x29, 0xFF, 0xE0, 0xA4, 0x29, 0xFF,
+	0xE1, 0xA4, 0x29, 0xFF, 0xE1, 0xA5, 0x2A, 0xFF, 0xE1, 0xA5, 0x2A, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF,
+	0xE2, 0xA8, 0x2C, 0xFF, 0xE2, 0xA9, 0x2F, 0xFF, 0xE3, 0xAC, 0x34, 0xFF, 0xE4, 0xAE, 0x38, 0xFF,
+	0xE5, 0xB0, 0x3C, 0xFF, 0xE6, 0xB1, 0x3D, 0xFF, 0xE6, 0xB1, 0x3D, 0xFF, 0xE6, 0xB1, 0x3D, 0xFF,
+	0xE6, 0xB2, 0x3D, 0xFF, 0xE7, 0xB3, 0x3D, 0xFF, 0xE7, 0xB3, 0x3E, 0xFF, 0xE8, 0xB4, 0x3E, 0xFF,
+	0xE8, 0xB4, 0x3F, 0xFF, 0xE7, 0xB4, 0x40, 0xFF, 0xE8, 0xB5, 0x40, 0xFF, 0xE9, 0xB5, 0x40, 0xFF,
+	0xE9, 0xB6, 0x40, 0xFF, 0xE9, 0xB6, 0x40, 0xFF, 0xE9, 0xB7, 0x40, 0xFF, 0xE9, 0xB7, 0x41, 0xFF,
+	0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF,
+	0xE9, 0xB8, 0x41, 0xFF, 0xEA, 0xB8, 0x42, 0xFF, 0xEA, 0xB8, 0x42, 0xFF, 0xEA, 0xB8, 0x42, 0xFF,
+	0xEA, 0xB9, 0x42, 0xFF, 0xEA, 0xB9, 0x42, 0xFF, 0xEA, 0xB9, 0x42, 0xFF, 0xEA, 0xB9, 0x42, 0xFF,
+	0xEA, 0xB9, 0x42, 0xFF, 0xEA, 0xB8, 0x42, 0xFF, 0xEA, 0xB8, 0x42, 0xFF, 0xEA, 0xB8, 0x42, 0xFF,
+	0xEA, 0xB7, 0x42, 0xFF, 0xEA, 0xB7, 0x42, 0xFF, 0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF,
+	0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x41, 0xFF, 0xE9, 0xB7, 0x40, 0xFF, 0xE9, 0xB7, 0x40, 0xFF,
+	0xE9, 0xB7, 0x40, 0xFF, 0xE9, 0xB6, 0x40, 0xFF, 0xE9, 0xB6, 0x40, 0xFF, 0xE9, 0xB5, 0x40, 0xFF,
+	0xE8, 0xB5, 0x3F, 0xFF, 0xE8, 0xB4, 0x3F, 0xFF, 0xE8, 0xB4, 0x3F, 0xFF, 0xE8, 0xB3, 0x3F, 0xFF,
+	0xE7, 0xB3, 0x3E, 0xFF, 0xE7, 0xB2, 0x3D, 0xFF, 0xE6, 0xB1, 0x3D, 0xFF, 0xE6, 0xB1, 0x3C, 0xFF,
+	0xE6, 0xB0, 0x3C, 0xFF, 0xE6, 0xB0, 0x3D, 0xFF, 0xE5, 0xAF, 0x3B, 0xFF, 0xE4, 0xAD, 0x36, 0xFF,
+	0xE3, 0xAA, 0x31, 0xFF, 0xE2, 0xA8, 0x2D, 0xFF, 0xE2, 0xA7, 0x2B, 0xFF, 0xE1, 0xA6, 0x2A, 0xFF,
+	0xE1, 0xA5, 0x2B, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF, 0xE0, 0xA4, 0x2A, 0xFF, 0xDF, 0xA4, 0x29, 0xFF,
+	0xDF, 0xA3, 0x28, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDE, 0xA0, 0x27, 0xFF, 0xDD, 0x9F, 0x26, 0xFF,
+	0xDD, 0x9F, 0x26, 0xFF, 0xDC, 0x9E, 0x25, 0xFF, 0xDC, 0x9D, 0x24, 0xFF, 0xDB, 0x9C, 0x23, 0xFF,
+	0xDB, 0x9B, 0x23, 0xFF, 0xDB, 0x9A, 0x23, 0xFF, 0xDC, 0x9B, 0x22, 0xFF, 0xD9, 0x99, 0x21, 0xFF,
+	0xD0, 0x90, 0x1E, 0xFF, 0xC2, 0x85, 0x1A, 0xFF, 0xA9, 0x73, 0x16, 0xD7, 0x80, 0x57, 0x11, 0x9D,
+	0x5A, 0x3D, 0x0C, 0x66, 0x1F, 0x15, 0x04, 0x31, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x05,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0A,
+	0x00, 0x00, 0x00, 0x17, 0x1C, 0x13, 0x04, 0x3B, 0x7C, 0x55, 0x10, 0x88, 0x9F, 0x6C, 0x15, 0xCE,
+	0xB4, 0x7C, 0x19, 0xEE, 0xC7, 0x8A, 0x1C, 0xFE, 0xD2, 0x93, 0x20, 0xFF, 0xDA, 0x99, 0x23, 0xFF,
+	0xDD, 0x9C, 0x24, 0xFF, 0xDB, 0x9C, 0x23, 0xFF, 0xDC, 0x9D, 0x24, 0xFF, 0xDD, 0x9E, 0x25, 0xFF,
+	0xDD, 0x9F, 0x26, 0xFF, 0xDE, 0x9F, 0x27, 0xFF, 0xDE, 0xA0, 0x27, 0xFF, 0xDE, 0xA1, 0x27, 0xFF,
+	0xDE, 0xA2, 0x28, 0xFF, 0xDF, 0xA3, 0x29, 0xFF, 0xE0, 0xA5, 0x29, 0xFF, 0xE1, 0xA5, 0x2A, 0xFF,
+	0xE1, 0xA6, 0x2A, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE2, 0xA7, 0x2B, 0xFF,
+	0xE2, 0xA8, 0x2C, 0xFF, 0xE2, 0xA9, 0x2E, 0xFF, 0xE3, 0xAB, 0x32, 0xFF, 0xE4, 0xAD, 0x36, 0xFF,
+	0xE6, 0xB0, 0x3A, 0xFF, 0xE6, 0xB1, 0x3C, 0xFF, 0xE6, 0xB2, 0x3D, 0xFF, 0xE6, 0xB3, 0x3D, 0xFF,
+	0xE7, 0xB3, 0x3D, 0xFF, 0xE7, 0xB3, 0x3D, 0xFF, 0xE8, 0xB4, 0x3D, 0xFF, 0xE8, 0xB4, 0x3E, 0xFF,
+	0xE8, 0xB5, 0x3F, 0xFF, 0xE8, 0xB5, 0x40, 0xFF, 0xE9, 0xB6, 0x40, 0xFF, 0xE9, 0xB6, 0x40, 0xFF,
+	0xE9, 0xB7, 0x40, 0xFF, 0xE9, 0xB7, 0x40, 0xFF, 0xE9, 0xB8, 0x40, 0xFF, 0xE9, 0xB8, 0x41, 0xFF,
+	0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF,
+	0xE9, 0xB8, 0x41, 0xFF, 0xEA, 0xB8, 0x42, 0xFF, 0xEA, 0xB8, 0x42, 0xFF, 0xEA, 0xB9, 0x42, 0xFF,
+	0xEA, 0xB9, 0x42, 0xFF, 0xEA, 0xB9, 0x42, 0xFF, 0xEA, 0xB9, 0x42, 0xFF, 0xEA, 0xB9, 0x42, 0xFF,
+	0xEA, 0xB9, 0x42, 0xFF, 0xEA, 0xB9, 0x42, 0xFF, 0xEA, 0xB8, 0x42, 0xFF, 0xEA, 0xB8, 0x42, 0xFF,
+	0xEA, 0xB8, 0x42, 0xFF, 0xEA, 0xB8, 0x42, 0xFF, 0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF,
+	0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x41, 0xFF, 0xE9, 0xB8, 0x40, 0xFF, 0xE9, 0xB8, 0x40, 0xFF,
+	0xE9, 0xB8, 0x40, 0xFF, 0xE9, 0xB7, 0x40, 0xFF, 0xE9, 0xB7, 0x40, 0xFF, 0xE9, 0xB6, 0x40, 0xFF,
+	0xE9, 0xB5, 0x3F, 0xFF, 0xE8, 0xB4, 0x3F, 0xFF, 0xE8, 0xB4, 0x3F, 0xFF, 0xE8, 0xB4, 0x3F, 0xFF,
+	0xE8, 0xB4, 0x3E, 0xFF, 0xE7, 0xB3, 0x3D, 0xFF, 0xE7, 0xB2, 0x3D, 0xFF, 0xE6, 0xB2, 0x3C, 0xFF,
+	0xE6, 0xB1, 0x3B, 0xFF, 0xE6, 0xB1, 0x3B, 0xFF, 0xE6, 0xAF, 0x38, 0xFF, 0xE4, 0xAC, 0x32, 0xFF,
+	0xE3, 0xAA, 0x2E, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF, 0xE2, 0xA7, 0x2B, 0xFF, 0xE2, 0xA7, 0x2B, 0xFF,
+	0xE1, 0xA7, 0x2B, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE0, 0xA6, 0x2A, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF,
+	0xDF, 0xA4, 0x29, 0xFF, 0xDF, 0xA2, 0x28, 0xFF, 0xDE, 0xA1, 0x28, 0xFF, 0xDE, 0xA0, 0x27, 0xFF,
+	0xDD, 0xA0, 0x27, 0xFF, 0xDD, 0x9F, 0x26, 0xFF, 0xDD, 0x9E, 0x25, 0xFF, 0xDC, 0x9D, 0x24, 0xFF,
+	0xDC, 0x9C, 0x24, 0xFF, 0xDB, 0x9B, 0x23, 0xFF, 0xDC, 0x9C, 0x23, 0xFF, 0xDA, 0x9A, 0x22, 0xFF,
+	0xD0, 0x91, 0x1E, 0xFF, 0xC3, 0x86, 0x1A, 0xFF, 0xA9, 0x74, 0x16, 0xD8, 0x80, 0x57, 0x11, 0x9F,
+	0x5A, 0x3D, 0x0C, 0x68, 0x1E, 0x15, 0x04, 0x33, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x06,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0B,
+	0x00, 0x00, 0x00, 0x19, 0x1C, 0x13, 0x03, 0x3D, 0x7D, 0x55, 0x10, 0x8A, 0xA0, 0x6D, 0x14, 0xD0,
+	0xB6, 0x7E, 0x19, 0xF0, 0xC8, 0x8B, 0x1D, 0xFE, 0xD3, 0x94, 0x20, 0xFF, 0xDA, 0x9A, 0x23, 0xFF,
+	0xDD, 0x9D, 0x24, 0xFF, 0xDC, 0x9D, 0x24, 0xFF, 0xDD, 0x9E, 0x25, 0xFF, 0xDD, 0xA0, 0x25, 0xFF,
+	0xDD, 0xA0, 0x26, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDE, 0xA1, 0x28, 0xFF, 0xDF, 0xA2, 0x28, 0xFF,
+	0xDF, 0xA3, 0x28, 0xFF, 0xE0, 0xA4, 0x2A, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF, 0xE0, 0xA6, 0x2B, 0xFF,
+	0xE1, 0xA7, 0x2B, 0xFF, 0xE1, 0xA7, 0x2C, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF, 0xE2, 0xA9, 0x2C, 0xFF,
+	0xE3, 0xAA, 0x2D, 0xFF, 0xE3, 0xAA, 0x2E, 0xFF, 0xE3, 0xAB, 0x2F, 0xFF, 0xE4, 0xAD, 0x32, 0xFF,
+	0xE6, 0xAF, 0x36, 0xFF, 0xE6, 0xB1, 0x39, 0xFF, 0xE7, 0xB2, 0x3B, 0xFF, 0xE7, 0xB3, 0x3C, 0xFF,
+	0xE7, 0xB3, 0x3C, 0xFF, 0xE7, 0xB4, 0x3D, 0xFF, 0xE8, 0xB4, 0x3D, 0xFF, 0xE8, 0xB5, 0x3D, 0xFF,
+	0xE8, 0xB6, 0x3E, 0xFF, 0xE9, 0xB6, 0x3F, 0xFF, 0xE9, 0xB6, 0x3F, 0xFF, 0xE9, 0xB7, 0x3F, 0xFF,
+	0xE9, 0xB7, 0x3F, 0xFF, 0xE9, 0xB7, 0x3F, 0xFF, 0xE9, 0xB8, 0x40, 0xFF, 0xE9, 0xB9, 0x40, 0xFF,
+	0xEA, 0xB9, 0x41, 0xFF, 0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB9, 0x40, 0xFF, 0xE9, 0xB8, 0x40, 0xFF,
+	0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB9, 0x41, 0xFF, 0xEB, 0xB9, 0x41, 0xFF, 0xEB, 0xB9, 0x42, 0xFF,
+	0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF,
+	0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xB9, 0x41, 0xFF, 0xEB, 0xB9, 0x41, 0xFF, 0xEB, 0xB9, 0x41, 0xFF,
+	0xEB, 0xB9, 0x42, 0xFF, 0xEA, 0xB9, 0x41, 0xFF, 0xEA, 0xB9, 0x41, 0xFF, 0xE9, 0xB9, 0x40, 0xFF,
+	0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB8, 0x40, 0xFF, 0xEA, 0xB8, 0x40, 0xFF, 0xEA, 0xB8, 0x40, 0xFF,
+	0xE9, 0xB8, 0x40, 0xFF, 0xE9, 0xB8, 0x3F, 0xFF, 0xE9, 0xB7, 0x3F, 0xFF, 0xE9, 0xB7, 0x3F, 0xFF,
+	0xE8, 0xB6, 0x3F, 0xFF, 0xE8, 0xB5, 0x3F, 0xFF, 0xE8, 0xB5, 0x3E, 0xFF, 0xE8, 0xB5, 0x3E, 0xFF,
+	0xE8, 0xB4, 0x3D, 0xFF, 0xE7, 0xB4, 0x3D, 0xFF, 0xE7, 0xB3, 0x3C, 0xFF, 0xE6, 0xB2, 0x3C, 0xFF,
+	0xE6, 0xB1, 0x3A, 0xFF, 0xE6, 0xB0, 0x36, 0xFF, 0xE5, 0xAE, 0x32, 0xFF, 0xE4, 0xAC, 0x30, 0xFF,
+	0xE3, 0xAB, 0x2E, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE3, 0xA9, 0x2C, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF,
+	0xE2, 0xA8, 0x2C, 0xFF, 0xE1, 0xA7, 0x2B, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE0, 0xA6, 0x2A, 0xFF,
+	0xE0, 0xA5, 0x29, 0xFF, 0xDF, 0xA3, 0x29, 0xFF, 0xDF, 0xA2, 0x29, 0xFF, 0xDE, 0xA2, 0x28, 0xFF,
+	0xDE, 0xA1, 0x27, 0xFF, 0xDD, 0xA1, 0x26, 0xFF, 0xDD, 0x9F, 0x26, 0xFF, 0xDC, 0x9E, 0x25, 0xFF,
+	0xDC, 0x9D, 0x25, 0xFF, 0xDC, 0x9C, 0x24, 0xFF, 0xDD, 0x9D, 0x24, 0xFF, 0xDB, 0x9B, 0x23, 0xFF,
+	0xD1, 0x92, 0x1F, 0xFF, 0xC3, 0x87, 0x1B, 0xFF, 0xA9, 0x74, 0x17, 0xD8, 0x7F, 0x56, 0x11, 0xA1,
+	0x58, 0x3B, 0x0C, 0x6A, 0x1D, 0x14, 0x04, 0x35, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x06,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0D,
+	0x00, 0x00, 0x00, 0x1A, 0x1B, 0x13, 0x03, 0x3E, 0x7D, 0x56, 0x0F, 0x8B, 0xA0, 0x6E, 0x14, 0xD2,
+	0xB7, 0x7E, 0x19, 0xF1, 0xC9, 0x8C, 0x1E, 0xFE, 0xD3, 0x95, 0x21, 0xFF, 0xDA, 0x9B, 0x24, 0xFF,
+	0xDD, 0x9E, 0x25, 0xFF, 0xDD, 0x9E, 0x25, 0xFF, 0xDD, 0x9F, 0x25, 0xFF, 0xDD, 0xA1, 0x26, 0xFF,
+	0xDD, 0xA2, 0x27, 0xFF, 0xDE, 0xA2, 0x28, 0xFF, 0xDE, 0xA3, 0x28, 0xFF, 0xE0, 0xA4, 0x29, 0xFF,
+	0xE0, 0xA5, 0x29, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF, 0xE0, 0xA6, 0x2B, 0xFF, 0xE1, 0xA7, 0x2C, 0xFF,
+	0xE1, 0xA8, 0x2C, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF, 0xE3, 0xAA, 0x2E, 0xFF,
+	0xE4, 0xAB, 0x2E, 0xFF, 0xE4, 0xAC, 0x2E, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE5, 0xAD, 0x30, 0xFF,
+	0xE6, 0xAE, 0x33, 0xFF, 0xE6, 0xB0, 0x36, 0xFF, 0xE7, 0xB2, 0x39, 0xFF, 0xE7, 0xB3, 0x3B, 0xFF,
+	0xE7, 0xB4, 0x3C, 0xFF, 0xE7, 0xB4, 0x3C, 0xFF, 0xE8, 0xB5, 0x3D, 0xFF, 0xE8, 0xB5, 0x3D, 0xFF,
+	0xE9, 0xB6, 0x3D, 0xFF, 0xE9, 0xB7, 0x3E, 0xFF, 0xE9, 0xB7, 0x3E, 0xFF, 0xE9, 0xB7, 0x3F, 0xFF,
+	0xE9, 0xB7, 0x3F, 0xFF, 0xE9, 0xB8, 0x3F, 0xFF, 0xE9, 0xB9, 0x3F, 0xFF, 0xEA, 0xB9, 0x40, 0xFF,
+	0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB9, 0x40, 0xFF,
+	0xEA, 0xB9, 0x40, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF,
+	0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF,
+	0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF,
+	0xEB, 0xBA, 0x41, 0xFF, 0xEB, 0xBA, 0x41, 0xFF, 0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB9, 0x40, 0xFF,
+	0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB9, 0x40, 0xFF, 0xEA, 0xB8, 0x40, 0xFF,
+	0xEA, 0xB8, 0x3F, 0xFF, 0xE9, 0xB8, 0x3F, 0xFF, 0xE9, 0xB8, 0x3F, 0xFF, 0xE9, 0xB7, 0x3F, 0xFF,
+	0xE9, 0xB7, 0x3F, 0xFF, 0xE8, 0xB6, 0x3E, 0xFF, 0xE8, 0xB6, 0x3E, 0xFF, 0xE8, 0xB5, 0x3D, 0xFF,
+	0xE8, 0xB5, 0x3D, 0xFF, 0xE7, 0xB4, 0x3C, 0xFF, 0xE7, 0xB4, 0x3B, 0xFF, 0xE6, 0xB3, 0x3B, 0xFF,
+	0xE6, 0xB1, 0x38, 0xFF, 0xE5, 0xAF, 0x32, 0xFF, 0xE5, 0xAE, 0x2F, 0xFF, 0xE4, 0xAD, 0x2F, 0xFF,
+	0xE4, 0xAC, 0x2F, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF,
+	0xE2, 0xA9, 0x2C, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF, 0xE1, 0xA7, 0x2B, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF,
+	0xE0, 0xA6, 0x2A, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF, 0xDF, 0xA4, 0x29, 0xFF, 0xDF, 0xA3, 0x29, 0xFF,
+	0xDE, 0xA3, 0x28, 0xFF, 0xDE, 0xA2, 0x27, 0xFF, 0xDD, 0xA0, 0x26, 0xFF, 0xDD, 0x9F, 0x26, 0xFF,
+	0xDC, 0x9E, 0x26, 0xFF, 0xDC, 0x9D, 0x25, 0xFF, 0xDE, 0x9E, 0x25, 0xFF, 0xDC, 0x9C, 0x24, 0xFF,
+	0xD2, 0x93, 0x20, 0xFF, 0xC4, 0x88, 0x1B, 0xFF, 0xA9, 0x74, 0x17, 0xD9, 0x7E, 0x56, 0x11, 0xA2,
+	0x57, 0x3B, 0x0C, 0x6B, 0x1C, 0x13, 0x04, 0x37, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0E,
+	0x00, 0x00, 0x00, 0x1C, 0x1B, 0x12, 0x03, 0x3F, 0x7D, 0x56, 0x10, 0x8C, 0xA1, 0x6F, 0x15, 0xD1,
+	0xB7, 0x7F, 0x1A, 0xF0, 0xC9, 0x8D, 0x1E, 0xFE, 0xD4, 0x96, 0x22, 0xFF, 0xDB, 0x9D, 0x24, 0xFF,
+	0xDE, 0x9F, 0x25, 0xFF, 0xDD, 0x9F, 0x25, 0xFF, 0xDD, 0xA0, 0x26, 0xFF, 0xDE, 0xA1, 0x27, 0xFF,
+	0xDE, 0xA2, 0x28, 0xFF, 0xDF, 0xA3, 0x29, 0xFF, 0xDF, 0xA4, 0x29, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF,
+	0xE1, 0xA6, 0x2A, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE1, 0xA7, 0x2C, 0xFF, 0xE1, 0xA8, 0x2C, 0xFF,
+	0xE2, 0xA9, 0x2D, 0xFF, 0xE2, 0xAA, 0x2D, 0xFF, 0xE3, 0xAB, 0x2E, 0xFF, 0xE4, 0xAB, 0x2F, 0xFF,
+	0xE4, 0xAC, 0x2F, 0xFF, 0xE5, 0xAD, 0x2F, 0xFF, 0xE5, 0xAD, 0x2F, 0xFF, 0xE5, 0xAE, 0x30, 0xFF,
+	0xE6, 0xAF, 0x32, 0xFF, 0xE7, 0xB0, 0x34, 0xFF, 0xE7, 0xB2, 0x36, 0xFF, 0xE7, 0xB3, 0x38, 0xFF,
+	0xE8, 0xB4, 0x3A, 0xFF, 0xE8, 0xB5, 0x3B, 0xFF, 0xE9, 0xB5, 0x3D, 0xFF, 0xE9, 0xB6, 0x3D, 0xFF,
+	0xE9, 0xB7, 0x3D, 0xFF, 0xEA, 0xB8, 0x3D, 0xFF, 0xEA, 0xB8, 0x3E, 0xFF, 0xEA, 0xB8, 0x3E, 0xFF,
+	0xEA, 0xB8, 0x3F, 0xFF, 0xEA, 0xB9, 0x3F, 0xFF, 0xEA, 0xB9, 0x3F, 0xFF, 0xEB, 0xBA, 0x3F, 0xFF,
+	0xEB, 0xBA, 0x40, 0xFF, 0xEB, 0xBB, 0x40, 0xFF, 0xEB, 0xBB, 0x40, 0xFF, 0xEB, 0xBB, 0x40, 0xFF,
+	0xEB, 0xBB, 0x40, 0xFF, 0xEC, 0xBB, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF,
+	0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF,
+	0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF,
+	0xEC, 0xBB, 0x40, 0xFF, 0xEB, 0xBB, 0x40, 0xFF, 0xEB, 0xBB, 0x40, 0xFF, 0xEB, 0xBB, 0x40, 0xFF,
+	0xEB, 0xBB, 0x40, 0xFF, 0xEB, 0xBB, 0x40, 0xFF, 0xEB, 0xBA, 0x40, 0xFF, 0xEB, 0xB9, 0x3F, 0xFF,
+	0xEA, 0xB9, 0x3F, 0xFF, 0xEA, 0xB9, 0x3E, 0xFF, 0xEA, 0xB9, 0x3E, 0xFF, 0xEA, 0xB8, 0x3E, 0xFF,
+	0xEA, 0xB8, 0x3E, 0xFF, 0xE9, 0xB7, 0x3E, 0xFF, 0xE9, 0xB7, 0x3D, 0xFF, 0xE9, 0xB6, 0x3D, 0xFF,
+	0xE8, 0xB6, 0x3C, 0xFF, 0xE8, 0xB4, 0x3A, 0xFF, 0xE7, 0xB3, 0x38, 0xFF, 0xE7, 0xB3, 0x37, 0xFF,
+	0xE6, 0xB1, 0x35, 0xFF, 0xE6, 0xB0, 0x32, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE5, 0xAE, 0x30, 0xFF,
+	0xE4, 0xAD, 0x2F, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF,
+	0xE3, 0xAA, 0x2D, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF, 0xE1, 0xA7, 0x2C, 0xFF,
+	0xE1, 0xA7, 0x2B, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF, 0xE0, 0xA4, 0x2A, 0xFF,
+	0xDF, 0xA3, 0x29, 0xFF, 0xDE, 0xA2, 0x28, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDE, 0xA0, 0x26, 0xFF,
+	0xDD, 0x9F, 0x26, 0xFF, 0xDD, 0x9F, 0x26, 0xFF, 0xDE, 0x9F, 0x26, 0xFF, 0xDC, 0x9D, 0x24, 0xFF,
+	0xD3, 0x94, 0x21, 0xFF, 0xC5, 0x88, 0x1C, 0xFF, 0xAB, 0x76, 0x18, 0xD9, 0x80, 0x59, 0x12, 0xA3,
+	0x59, 0x3D, 0x0D, 0x6D, 0x1D, 0x14, 0x04, 0x38, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x0F,
+	0x00, 0x00, 0x00, 0x1D, 0x1A, 0x12, 0x04, 0x40, 0x7C, 0x55, 0x11, 0x8B, 0xA0, 0x6F, 0x16, 0xCF,
+	0xB6, 0x7F, 0x1B, 0xEF, 0xC8, 0x8D, 0x1F, 0xFE, 0xD4, 0x97, 0x22, 0xFF, 0xDC, 0x9E, 0x25, 0xFF,
+	0xDE, 0xA1, 0x26, 0xFF, 0xDD, 0xA0, 0x26, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDF, 0xA1, 0x28, 0xFF,
+	0xDF, 0xA3, 0x29, 0xFF, 0xE0, 0xA4, 0x2A, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF,
+	0xE1, 0xA7, 0x2B, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF, 0xE3, 0xA9, 0x2C, 0xFF,
+	0xE3, 0xAA, 0x2D, 0xFF, 0xE3, 0xAB, 0x2E, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF,
+	0xE5, 0xAD, 0x30, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE6, 0xB0, 0x31, 0xFF,
+	0xE7, 0xB1, 0x32, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE7, 0xB2, 0x35, 0xFF,
+	0xE8, 0xB4, 0x38, 0xFF, 0xE9, 0xB5, 0x3B, 0xFF, 0xEA, 0xB6, 0x3C, 0xFF, 0xEA, 0xB7, 0x3D, 0xFF,
+	0xEA, 0xB8, 0x3D, 0xFF, 0xEA, 0xB9, 0x3D, 0xFF, 0xEA, 0xB9, 0x3D, 0xFF, 0xEB, 0xB9, 0x3E, 0xFF,
+	0xEB, 0xB9, 0x3E, 0xFF, 0xEB, 0xBA, 0x3F, 0xFF, 0xEB, 0xBA, 0x3F, 0xFF, 0xEC, 0xBB, 0x3F, 0xFF,
+	0xEC, 0xBB, 0x3F, 0xFF, 0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF,
+	0xEC, 0xBC, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF,
+	0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF,
+	0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF,
+	0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF,
+	0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBC, 0x40, 0xFF, 0xEC, 0xBB, 0x3F, 0xFF, 0xEC, 0xBB, 0x3F, 0xFF,
+	0xEB, 0xBA, 0x3E, 0xFF, 0xEB, 0xBA, 0x3E, 0xFF, 0xEB, 0xB9, 0x3E, 0xFF, 0xEB, 0xB9, 0x3E, 0xFF,
+	0xEB, 0xB9, 0x3E, 0xFF, 0xEA, 0xB8, 0x3D, 0xFF, 0xEA, 0xB8, 0x3D, 0xFF, 0xE9, 0xB7, 0x3C, 0xFF,
+	0xE9, 0xB6, 0x3B, 0xFF, 0xE8, 0xB5, 0x38, 0xFF, 0xE8, 0xB3, 0x36, 0xFF, 0xE7, 0xB2, 0x34, 0xFF,
+	0xE7, 0xB2, 0x33, 0xFF, 0xE6, 0xB1, 0x32, 0xFF, 0xE6, 0xB0, 0x32, 0xFF, 0xE5, 0xAF, 0x31, 0xFF,
+	0xE5, 0xAE, 0x30, 0xFF, 0xE5, 0xAD, 0x30, 0xFF, 0xE5, 0xAD, 0x30, 0xFF, 0xE5, 0xAC, 0x2F, 0xFF,
+	0xE4, 0xAB, 0x2E, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF,
+	0xE2, 0xA8, 0x2C, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE0, 0xA5, 0x2B, 0xFF,
+	0xDF, 0xA4, 0x2A, 0xFF, 0xDF, 0xA2, 0x29, 0xFF, 0xDF, 0xA2, 0x28, 0xFF, 0xDF, 0xA1, 0x27, 0xFF,
+	0xDE, 0xA0, 0x26, 0xFF, 0xDD, 0xA0, 0x26, 0xFF, 0xDF, 0xA0, 0x26, 0xFF, 0xDD, 0x9E, 0x25, 0xFF,
+	0xD3, 0x94, 0x21, 0xFF, 0xC6, 0x89, 0x1D, 0xFF, 0xAB, 0x76, 0x19, 0xD9, 0x80, 0x59, 0x13, 0xA1,
+	0x57, 0x3D, 0x0D, 0x6C, 0x1C, 0x13, 0x04, 0x38, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x08,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x0F,
+	0x00, 0x00, 0x00, 0x1E, 0x18, 0x11, 0x03, 0x41, 0x77, 0x52, 0x11, 0x87, 0x9D, 0x6D, 0x17, 0xC9,
+	0xB4, 0x7E, 0x1B, 0xEB, 0xC7, 0x8D, 0x1F, 0xFE, 0xD3, 0x97, 0x22, 0xFF, 0xDC, 0x9F, 0x25, 0xFF,
+	0xDF, 0xA2, 0x27, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDE, 0xA2, 0x27, 0xFF, 0xDF, 0xA3, 0x28, 0xFF,
+	0xE0, 0xA4, 0x29, 0xFF, 0xE1, 0xA5, 0x2B, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE1, 0xA7, 0x2B, 0xFF,
+	0xE2, 0xA8, 0x2C, 0xFF, 0xE2, 0xA9, 0x2C, 0xFF, 0xE3, 0xA9, 0x2D, 0xFF, 0xE4, 0xAA, 0x2D, 0xFF,
+	0xE4, 0xAB, 0x2E, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE4, 0xAD, 0x2F, 0xFF, 0xE5, 0xAD, 0x30, 0xFF,
+	0xE5, 0xAE, 0x31, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE6, 0xB0, 0x32, 0xFF, 0xE7, 0xB1, 0x32, 0xFF,
+	0xE7, 0xB2, 0x32, 0xFF, 0xE8, 0xB2, 0x33, 0xFF, 0xE8, 0xB3, 0x33, 0xFF, 0xE8, 0xB4, 0x34, 0xFF,
+	0xE9, 0xB5, 0x37, 0xFF, 0xEA, 0xB6, 0x38, 0xFF, 0xEA, 0xB7, 0x3A, 0xFF, 0xEB, 0xB8, 0x3B, 0xFF,
+	0xEA, 0xB9, 0x3C, 0xFF, 0xEA, 0xBA, 0x3D, 0xFF, 0xEB, 0xBA, 0x3D, 0xFF, 0xEC, 0xBA, 0x3E, 0xFF,
+	0xEC, 0xBB, 0x3E, 0xFF, 0xEC, 0xBB, 0x3E, 0xFF, 0xEC, 0xBB, 0x3E, 0xFF, 0xED, 0xBC, 0x3E, 0xFF,
+	0xED, 0xBC, 0x3F, 0xFF, 0xED, 0xBC, 0x3F, 0xFF, 0xED, 0xBD, 0x3F, 0xFF, 0xED, 0xBD, 0x40, 0xFF,
+	0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF,
+	0xED, 0xBD, 0x40, 0xFF, 0xEC, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x40, 0xFF,
+	0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBC, 0x3F, 0xFF, 0xED, 0xBC, 0x3F, 0xFF, 0xED, 0xBC, 0x3E, 0xFF,
+	0xEC, 0xBB, 0x3E, 0xFF, 0xEC, 0xBB, 0x3E, 0xFF, 0xEC, 0xBA, 0x3E, 0xFF, 0xEC, 0xBA, 0x3E, 0xFF,
+	0xEB, 0xB9, 0x3D, 0xFF, 0xEB, 0xB9, 0x3C, 0xFF, 0xEA, 0xB8, 0x3B, 0xFF, 0xEA, 0xB7, 0x3A, 0xFF,
+	0xE9, 0xB6, 0x38, 0xFF, 0xE9, 0xB5, 0x36, 0xFF, 0xE8, 0xB4, 0x35, 0xFF, 0xE8, 0xB3, 0x33, 0xFF,
+	0xE8, 0xB2, 0x33, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE7, 0xB1, 0x33, 0xFF, 0xE6, 0xB0, 0x32, 0xFF,
+	0xE6, 0xAF, 0x31, 0xFF, 0xE6, 0xAE, 0x31, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE5, 0xAD, 0x30, 0xFF,
+	0xE5, 0xAC, 0x2F, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE3, 0xAA, 0x2E, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF,
+	0xE3, 0xA9, 0x2D, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF,
+	0xE0, 0xA5, 0x2A, 0xFF, 0xE0, 0xA4, 0x29, 0xFF, 0xE0, 0xA3, 0x28, 0xFF, 0xDF, 0xA2, 0x28, 0xFF,
+	0xDE, 0xA1, 0x27, 0xFF, 0xDD, 0xA0, 0x26, 0xFF, 0xDF, 0xA1, 0x26, 0xFF, 0xDD, 0x9F, 0x25, 0xFF,
+	0xD4, 0x96, 0x21, 0xFF, 0xC6, 0x8A, 0x1D, 0xFF, 0xA9, 0x75, 0x19, 0xD5, 0x78, 0x54, 0x12, 0x9B,
+	0x4D, 0x36, 0x0C, 0x67, 0x18, 0x11, 0x04, 0x37, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x08,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x0F,
+	0x00, 0x00, 0x00, 0x1F, 0x16, 0x0F, 0x03, 0x40, 0x70, 0x4E, 0x10, 0x82, 0x97, 0x69, 0x16, 0xC0,
+	0xB1, 0x7D, 0x1B, 0xE7, 0xC6, 0x8C, 0x1F, 0xFE, 0xD3, 0x97, 0x23, 0xFF, 0xDD, 0xA0, 0x26, 0xFF,
+	0xE0, 0xA2, 0x28, 0xFF, 0xDF, 0xA2, 0x28, 0xFF, 0xDF, 0xA3, 0x28, 0xFF, 0xE0, 0xA4, 0x29, 0xFF,
+	0xE0, 0xA5, 0x2A, 0xFF, 0xE1, 0xA5, 0x2B, 0xFF, 0xE2, 0xA6, 0x2C, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF,
+	0xE2, 0xA9, 0x2C, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE5, 0xAC, 0x2E, 0xFF,
+	0xE5, 0xAD, 0x2F, 0xFF, 0xE5, 0xAD, 0x2F, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE5, 0xAF, 0x31, 0xFF,
+	0xE6, 0xB0, 0x32, 0xFF, 0xE6, 0xB1, 0x32, 0xFF, 0xE7, 0xB1, 0x33, 0xFF, 0xE7, 0xB2, 0x33, 0xFF,
+	0xE8, 0xB3, 0x34, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xEA, 0xB5, 0x36, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xEB, 0xB7, 0x37, 0xFF, 0xEB, 0xB8, 0x39, 0xFF,
+	0xEB, 0xB9, 0x3A, 0xFF, 0xEB, 0xBA, 0x3C, 0xFF, 0xEC, 0xBB, 0x3D, 0xFF, 0xED, 0xBC, 0x3D, 0xFF,
+	0xED, 0xBC, 0x3E, 0xFF, 0xED, 0xBC, 0x3E, 0xFF, 0xED, 0xBC, 0x3E, 0xFF, 0xED, 0xBD, 0x3E, 0xFF,
+	0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBD, 0x3F, 0xFF, 0xED, 0xBD, 0x3F, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xED, 0xBE, 0x41, 0xFF, 0xED, 0xBE, 0x41, 0xFF, 0xED, 0xBF, 0x41, 0xFF, 0xED, 0xBF, 0x41, 0xFF,
+	0xED, 0xBF, 0x41, 0xFF, 0xED, 0xBE, 0x41, 0xFF, 0xED, 0xBE, 0x41, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xED, 0xBF, 0x40, 0xFF, 0xED, 0xBF, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xED, 0xBD, 0x3F, 0xFF, 0xED, 0xBD, 0x3F, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBD, 0x3E, 0xFF,
+	0xED, 0xBC, 0x3E, 0xFF, 0xED, 0xBC, 0x3E, 0xFF, 0xEC, 0xBB, 0x3E, 0xFF, 0xEC, 0xBB, 0x3D, 0xFF,
+	0xEB, 0xBA, 0x3C, 0xFF, 0xEB, 0xB9, 0x3B, 0xFF, 0xEB, 0xB8, 0x3A, 0xFF, 0xEA, 0xB7, 0x38, 0xFF,
+	0xEA, 0xB6, 0x36, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB4, 0x34, 0xFF,
+	0xE9, 0xB4, 0x34, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE8, 0xB2, 0x34, 0xFF, 0xE7, 0xB2, 0x33, 0xFF,
+	0xE7, 0xB1, 0x32, 0xFF, 0xE6, 0xB0, 0x31, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE5, 0xAE, 0x30, 0xFF,
+	0xE5, 0xAE, 0x30, 0xFF, 0xE4, 0xAD, 0x2F, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE3, 0xAB, 0x2E, 0xFF,
+	0xE3, 0xAA, 0x2D, 0xFF, 0xE3, 0xA9, 0x2C, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF, 0xE2, 0xA6, 0x2C, 0xFF,
+	0xE1, 0xA6, 0x2B, 0xFF, 0xE1, 0xA5, 0x2A, 0xFF, 0xE0, 0xA4, 0x29, 0xFF, 0xE0, 0xA3, 0x29, 0xFF,
+	0xDF, 0xA2, 0x28, 0xFF, 0xDE, 0xA1, 0x27, 0xFF, 0xDF, 0xA2, 0x27, 0xFF, 0xDD, 0xA0, 0x26, 0xFF,
+	0xD5, 0x97, 0x22, 0xFF, 0xC7, 0x8B, 0x1D, 0xFF, 0xA7, 0x73, 0x18, 0xD1, 0x6C, 0x4B, 0x10, 0x91,
+	0x3C, 0x2A, 0x09, 0x5F, 0x13, 0x0D, 0x03, 0x36, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x08,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0E,
+	0x00, 0x00, 0x00, 0x1F, 0x14, 0x0E, 0x03, 0x40, 0x66, 0x47, 0x0F, 0x7B, 0x8E, 0x63, 0x15, 0xB6,
+	0xAD, 0x7A, 0x1A, 0xE0, 0xC5, 0x8B, 0x1E, 0xFE, 0xD3, 0x97, 0x23, 0xFF, 0xDD, 0xA1, 0x27, 0xFF,
+	0xE1, 0xA4, 0x28, 0xFF, 0xE0, 0xA3, 0x29, 0xFF, 0xE0, 0xA4, 0x29, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF,
+	0xE1, 0xA6, 0x2B, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF, 0xE2, 0xA7, 0x2D, 0xFF, 0xE2, 0xA9, 0x2C, 0xFF,
+	0xE3, 0xAA, 0x2D, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE5, 0xAC, 0x2F, 0xFF, 0xE5, 0xAD, 0x2F, 0xFF,
+	0xE5, 0xAE, 0x30, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE6, 0xB0, 0x32, 0xFF,
+	0xE7, 0xB1, 0x33, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE7, 0xB3, 0x33, 0xFF, 0xE8, 0xB3, 0x34, 0xFF,
+	0xE8, 0xB3, 0x34, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xEA, 0xB6, 0x36, 0xFF,
+	0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEB, 0xB9, 0x38, 0xFF,
+	0xEB, 0xB9, 0x39, 0xFF, 0xEB, 0xBA, 0x3B, 0xFF, 0xEC, 0xBB, 0x3B, 0xFF, 0xED, 0xBC, 0x3C, 0xFF,
+	0xED, 0xBC, 0x3D, 0xFF, 0xED, 0xBC, 0x3E, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBD, 0x3F, 0xFF,
+	0xED, 0xBE, 0x3F, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x41, 0xFF,
+	0xED, 0xBE, 0x41, 0xFF, 0xED, 0xBF, 0x41, 0xFF, 0xED, 0xBF, 0x42, 0xFF, 0xED, 0xBF, 0x42, 0xFF,
+	0xED, 0xBF, 0x42, 0xFF, 0xED, 0xBF, 0x42, 0xFF, 0xED, 0xBF, 0x43, 0xFF, 0xED, 0xC0, 0x43, 0xFF,
+	0xED, 0xBF, 0x43, 0xFF, 0xED, 0xBF, 0x42, 0xFF, 0xED, 0xBF, 0x42, 0xFF, 0xED, 0xBF, 0x42, 0xFF,
+	0xED, 0xBF, 0x42, 0xFF, 0xED, 0xBF, 0x41, 0xFF, 0xED, 0xBF, 0x41, 0xFF, 0xED, 0xBE, 0x41, 0xFF,
+	0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x3F, 0xFF, 0xED, 0xBD, 0x3E, 0xFF,
+	0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBC, 0x3D, 0xFF, 0xED, 0xBC, 0x3D, 0xFF, 0xEC, 0xBB, 0x3C, 0xFF,
+	0xEC, 0xBB, 0x3B, 0xFF, 0xEB, 0xBA, 0x3A, 0xFF, 0xEB, 0xB9, 0x39, 0xFF, 0xEA, 0xB8, 0x37, 0xFF,
+	0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xEA, 0xB6, 0x35, 0xFF, 0xEA, 0xB5, 0x35, 0xFF,
+	0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE8, 0xB4, 0x34, 0xFF, 0xE8, 0xB3, 0x33, 0xFF,
+	0xE7, 0xB2, 0x33, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE6, 0xB0, 0x32, 0xFF, 0xE6, 0xAF, 0x31, 0xFF,
+	0xE5, 0xAF, 0x30, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE4, 0xAD, 0x30, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF,
+	0xE3, 0xAB, 0x2E, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE3, 0xA8, 0x2D, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF,
+	0xE2, 0xA7, 0x2C, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE1, 0xA6, 0x2A, 0xFF, 0xE0, 0xA4, 0x29, 0xFF,
+	0xDF, 0xA3, 0x28, 0xFF, 0xDF, 0xA2, 0x28, 0xFF, 0xE0, 0xA3, 0x28, 0xFF, 0xDE, 0xA2, 0x27, 0xFF,
+	0xD6, 0x98, 0x22, 0xFF, 0xC7, 0x8C, 0x1E, 0xFF, 0xA2, 0x70, 0x17, 0xCA, 0x57, 0x3C, 0x0D, 0x84,
+	0x20, 0x15, 0x04, 0x55, 0x0A, 0x07, 0x01, 0x33, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x08,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0D,
+	0x00, 0x00, 0x00, 0x20, 0x10, 0x0C, 0x02, 0x3F, 0x59, 0x3E, 0x0D, 0x74, 0x83, 0x5C, 0x13, 0xA9,
+	0xA8, 0x76, 0x19, 0xD9, 0xC3, 0x89, 0x1E, 0xFD, 0xD3, 0x96, 0x22, 0xFF, 0xDE, 0xA1, 0x27, 0xFF,
+	0xE2, 0xA5, 0x29, 0xFF, 0xE0, 0xA4, 0x29, 0xFF, 0xE0, 0xA5, 0x2A, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF,
+	0xE2, 0xA7, 0x2C, 0xFF, 0xE2, 0xA8, 0x2D, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF,
+	0xE4, 0xAB, 0x2E, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE5, 0xAD, 0x30, 0xFF, 0xE5, 0xAE, 0x30, 0xFF,
+	0xE5, 0xAF, 0x31, 0xFF, 0xE6, 0xB0, 0x31, 0xFF, 0xE7, 0xB0, 0x32, 0xFF, 0xE7, 0xB1, 0x33, 0xFF,
+	0xE8, 0xB2, 0x34, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE8, 0xB4, 0x34, 0xFF,
+	0xE9, 0xB4, 0x34, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB6, 0x36, 0xFF, 0xEA, 0xB7, 0x37, 0xFF,
+	0xEA, 0xB8, 0x37, 0xFF, 0xEB, 0xB9, 0x37, 0xFF, 0xEB, 0xB9, 0x37, 0xFF, 0xEC, 0xBA, 0x38, 0xFF,
+	0xEC, 0xBA, 0x38, 0xFF, 0xEC, 0xBB, 0x39, 0xFF, 0xEC, 0xBB, 0x3A, 0xFF, 0xED, 0xBC, 0x3B, 0xFF,
+	0xED, 0xBC, 0x3C, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBD, 0x3F, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xED, 0xBE, 0x41, 0xFF, 0xED, 0xBF, 0x42, 0xFF, 0xED, 0xC0, 0x43, 0xFF, 0xED, 0xBF, 0x43, 0xFF,
+	0xED, 0xBF, 0x43, 0xFF, 0xEE, 0xBF, 0x44, 0xFF, 0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xC0, 0x44, 0xFF,
+	0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x45, 0xFF,
+	0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xBF, 0x44, 0xFF,
+	0xEE, 0xBF, 0x44, 0xFF, 0xEE, 0xBF, 0x44, 0xFF, 0xED, 0xBF, 0x43, 0xFF, 0xED, 0xBF, 0x42, 0xFF,
+	0xED, 0xBF, 0x42, 0xFF, 0xED, 0xBF, 0x41, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x3F, 0xFF,
+	0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBC, 0x3A, 0xFF,
+	0xEC, 0xBB, 0x39, 0xFF, 0xEC, 0xBB, 0x39, 0xFF, 0xEB, 0xBA, 0x38, 0xFF, 0xEB, 0xB9, 0x38, 0xFF,
+	0xEB, 0xB8, 0x37, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB6, 0x36, 0xFF,
+	0xEA, 0xB5, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE8, 0xB4, 0x34, 0xFF,
+	0xE8, 0xB3, 0x34, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE7, 0xB1, 0x33, 0xFF, 0xE6, 0xB1, 0x32, 0xFF,
+	0xE6, 0xB0, 0x31, 0xFF, 0xE5, 0xAF, 0x31, 0xFF, 0xE5, 0xAE, 0x31, 0xFF, 0xE4, 0xAD, 0x30, 0xFF,
+	0xE4, 0xAC, 0x2F, 0xFF, 0xE3, 0xAB, 0x2E, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE3, 0xA9, 0x2D, 0xFF,
+	0xE2, 0xA8, 0x2D, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE1, 0xA5, 0x2A, 0xFF,
+	0xE0, 0xA4, 0x29, 0xFF, 0xE0, 0xA3, 0x29, 0xFF, 0xE2, 0xA5, 0x29, 0xFF, 0xDF, 0xA2, 0x28, 0xFF,
+	0xD7, 0x99, 0x23, 0xFF, 0xC8, 0x8C, 0x1E, 0xFF, 0x9C, 0x6D, 0x17, 0xC2, 0x3A, 0x28, 0x08, 0x74,
+	0x00, 0x00, 0x00, 0x4A, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x0C,
+	0x00, 0x00, 0x00, 0x1F, 0x0E, 0x0A, 0x02, 0x3E, 0x4C, 0x35, 0x0B, 0x6C, 0x77, 0x54, 0x11, 0x9E,
+	0xA4, 0x73, 0x18, 0xD3, 0xC3, 0x89, 0x1E, 0xFD, 0xD3, 0x97, 0x23, 0xFF, 0xDE, 0xA2, 0x28, 0xFF,
+	0xE2, 0xA6, 0x2A, 0xFF, 0xE1, 0xA6, 0x2A, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF,
+	0xE2, 0xA8, 0x2D, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF,
+	0xE5, 0xAC, 0x2F, 0xFF, 0xE5, 0xAD, 0x30, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE5, 0xAF, 0x31, 0xFF,
+	0xE5, 0xB0, 0x32, 0xFF, 0xE6, 0xB1, 0x32, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE8, 0xB3, 0x33, 0xFF,
+	0xE8, 0xB3, 0x34, 0xFF, 0xE8, 0xB4, 0x34, 0xFF, 0xE8, 0xB5, 0x34, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xE9, 0xB6, 0x35, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xEA, 0xB7, 0x37, 0xFF, 0xEB, 0xB8, 0x37, 0xFF,
+	0xEB, 0xB9, 0x37, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xEC, 0xBB, 0x39, 0xFF,
+	0xEC, 0xBB, 0x39, 0xFF, 0xEC, 0xBC, 0x3A, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBC, 0x3C, 0xFF,
+	0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBD, 0x3F, 0xFF, 0xED, 0xBE, 0x41, 0xFF, 0xED, 0xBE, 0x42, 0xFF,
+	0xED, 0xBF, 0x43, 0xFF, 0xED, 0xC0, 0x43, 0xFF, 0xED, 0xC0, 0x44, 0xFF, 0xED, 0xC0, 0x45, 0xFF,
+	0xED, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC0, 0x46, 0xFF,
+	0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xC0, 0x47, 0xFF,
+	0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC0, 0x46, 0xFF,
+	0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xBF, 0x46, 0xFF, 0xED, 0xBF, 0x45, 0xFF, 0xED, 0xBF, 0x44, 0xFF,
+	0xED, 0xBF, 0x43, 0xFF, 0xED, 0xBF, 0x43, 0xFF, 0xED, 0xBF, 0x42, 0xFF, 0xED, 0xBE, 0x41, 0xFF,
+	0xED, 0xBE, 0x3F, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBC, 0x3B, 0xFF,
+	0xED, 0xBC, 0x3A, 0xFF, 0xEC, 0xBC, 0x3A, 0xFF, 0xEC, 0xBB, 0x39, 0xFF, 0xEC, 0xBA, 0x39, 0xFF,
+	0xEB, 0xB9, 0x38, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEB, 0xB7, 0x37, 0xFF,
+	0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xE9, 0xB6, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xE8, 0xB5, 0x34, 0xFF, 0xE8, 0xB4, 0x34, 0xFF, 0xE7, 0xB3, 0x34, 0xFF, 0xE7, 0xB2, 0x32, 0xFF,
+	0xE7, 0xB1, 0x31, 0xFF, 0xE6, 0xB0, 0x31, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE5, 0xAE, 0x31, 0xFF,
+	0xE5, 0xAD, 0x30, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE3, 0xAB, 0x2E, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF,
+	0xE3, 0xA9, 0x2D, 0xFF, 0xE2, 0xA8, 0x2D, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF,
+	0xE1, 0xA5, 0x2A, 0xFF, 0xE0, 0xA5, 0x29, 0xFF, 0xE2, 0xA5, 0x29, 0xFF, 0xDF, 0xA2, 0x28, 0xFF,
+	0xD5, 0x99, 0x23, 0xFF, 0xC6, 0x8B, 0x1E, 0xFF, 0x99, 0x6B, 0x16, 0xBC, 0x27, 0x1B, 0x05, 0x67,
+	0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x2E, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0A,
+	0x00, 0x00, 0x00, 0x1E, 0x0C, 0x08, 0x02, 0x3C, 0x3E, 0x2C, 0x08, 0x66, 0x6C, 0x4C, 0x10, 0x95,
+	0xA2, 0x72, 0x19, 0xCE, 0xC5, 0x8A, 0x1F, 0xFD, 0xD4, 0x98, 0x24, 0xFF, 0xDE, 0xA2, 0x28, 0xFF,
+	0xE2, 0xA6, 0x2A, 0xFF, 0xE2, 0xA6, 0x2B, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF, 0xE2, 0xA8, 0x2D, 0xFF,
+	0xE2, 0xA9, 0x2D, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF,
+	0xE5, 0xAE, 0x30, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE6, 0xAF, 0x32, 0xFF,
+	0xE6, 0xB0, 0x32, 0xFF, 0xE7, 0xB1, 0x33, 0xFF, 0xE8, 0xB2, 0x33, 0xFF, 0xE8, 0xB3, 0x34, 0xFF,
+	0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB6, 0x35, 0xFF, 0xEA, 0xB7, 0x36, 0xFF,
+	0xEA, 0xB8, 0x37, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEC, 0xB9, 0x38, 0xFF,
+	0xEC, 0xBA, 0x38, 0xFF, 0xED, 0xBB, 0x38, 0xFF, 0xED, 0xBC, 0x3A, 0xFF, 0xED, 0xBC, 0x3B, 0xFF,
+	0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xEE, 0xBD, 0x3F, 0xFF,
+	0xEE, 0xBE, 0x40, 0xFF, 0xEE, 0xBE, 0x41, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xBF, 0x43, 0xFF,
+	0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x47, 0xFF,
+	0xEE, 0xC0, 0x48, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC1, 0x49, 0xFF,
+	0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC1, 0x49, 0xFF,
+	0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC1, 0x48, 0xFF,
+	0xEE, 0xC0, 0x48, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xC0, 0x46, 0xFF,
+	0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xBF, 0x42, 0xFF,
+	0xEE, 0xBF, 0x41, 0xFF, 0xEE, 0xBE, 0x40, 0xFF, 0xEE, 0xBE, 0x3F, 0xFF, 0xEE, 0xBD, 0x3E, 0xFF,
+	0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBB, 0x39, 0xFF,
+	0xEC, 0xBB, 0x39, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xEC, 0xB9, 0x38, 0xFF, 0xEC, 0xB9, 0x38, 0xFF,
+	0xEB, 0xB9, 0x37, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB7, 0x36, 0xFF,
+	0xE9, 0xB6, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE8, 0xB3, 0x33, 0xFF,
+	0xE8, 0xB2, 0x32, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE7, 0xB0, 0x32, 0xFF, 0xE6, 0xAF, 0x31, 0xFF,
+	0xE6, 0xAE, 0x31, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE4, 0xAD, 0x2F, 0xFF, 0xE3, 0xAC, 0x2E, 0xFF,
+	0xE3, 0xAA, 0x2D, 0xFF, 0xE3, 0xA9, 0x2D, 0xFF, 0xE2, 0xA8, 0x2D, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF,
+	0xE1, 0xA6, 0x2B, 0xFF, 0xE1, 0xA5, 0x2A, 0xFF, 0xE2, 0xA5, 0x2A, 0xFF, 0xDE, 0xA2, 0x28, 0xFF,
+	0xD2, 0x97, 0x23, 0xFF, 0xC2, 0x89, 0x1E, 0xFF, 0x98, 0x6A, 0x16, 0xB8, 0x20, 0x16, 0x05, 0x5C,
+	0x00, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x06,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09,
+	0x00, 0x00, 0x00, 0x1D, 0x09, 0x06, 0x01, 0x3A, 0x2E, 0x21, 0x06, 0x5E, 0x5E, 0x43, 0x0E, 0x8A,
+	0x9F, 0x70, 0x19, 0xC8, 0xC6, 0x8B, 0x20, 0xFD, 0xD5, 0x99, 0x24, 0xFF, 0xDE, 0xA3, 0x29, 0xFF,
+	0xE2, 0xA7, 0x2B, 0xFF, 0xE2, 0xA7, 0x2C, 0xFF, 0xE2, 0xA8, 0x2D, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF,
+	0xE3, 0xAA, 0x2D, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE5, 0xAD, 0x30, 0xFF,
+	0xE5, 0xAF, 0x30, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE6, 0xB0, 0x31, 0xFF, 0xE7, 0xB1, 0x32, 0xFF,
+	0xE7, 0xB2, 0x33, 0xFF, 0xE8, 0xB2, 0x34, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE9, 0xB4, 0x35, 0xFF,
+	0xE9, 0xB5, 0x35, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xEB, 0xB8, 0x37, 0xFF,
+	0xEB, 0xB9, 0x38, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xEC, 0xBB, 0x39, 0xFF,
+	0xED, 0xBB, 0x39, 0xFF, 0xED, 0xBC, 0x3A, 0xFF, 0xED, 0xBD, 0x3B, 0xFF, 0xED, 0xBE, 0x3D, 0xFF,
+	0xED, 0xBE, 0x3F, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xEE, 0xBE, 0x41, 0xFF, 0xEE, 0xBE, 0x42, 0xFF,
+	0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xC0, 0x46, 0xFF,
+	0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC1, 0x49, 0xFF,
+	0xEE, 0xC1, 0x4A, 0xFF, 0xEE, 0xC1, 0x4B, 0xFF, 0xEE, 0xC1, 0x4B, 0xFF, 0xEE, 0xC1, 0x4B, 0xFF,
+	0xEE, 0xC1, 0x4B, 0xFF, 0xEE, 0xC1, 0x4B, 0xFF, 0xEE, 0xC1, 0x4B, 0xFF, 0xEE, 0xC1, 0x4B, 0xFF,
+	0xEE, 0xC1, 0x4B, 0xFF, 0xEE, 0xC1, 0x4B, 0xFF, 0xEE, 0xC1, 0x4B, 0xFF, 0xEE, 0xC2, 0x4B, 0xFF,
+	0xEE, 0xC2, 0x4A, 0xFF, 0xEE, 0xC1, 0x4A, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC0, 0x49, 0xFF,
+	0xEE, 0xC0, 0x48, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xBF, 0x45, 0xFF,
+	0xEE, 0xBF, 0x44, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xBE, 0x41, 0xFF,
+	0xEE, 0xBE, 0x40, 0xFF, 0xED, 0xBD, 0x3F, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBD, 0x3B, 0xFF,
+	0xED, 0xBC, 0x3A, 0xFF, 0xEC, 0xBB, 0x3A, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xEC, 0xBA, 0x39, 0xFF,
+	0xEC, 0xBA, 0x38, 0xFF, 0xEC, 0xB9, 0x38, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEB, 0xB8, 0x37, 0xFF,
+	0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB4, 0x34, 0xFF,
+	0xE8, 0xB3, 0x33, 0xFF, 0xE8, 0xB2, 0x33, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE7, 0xB0, 0x32, 0xFF,
+	0xE6, 0xB0, 0x31, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE4, 0xAD, 0x2F, 0xFF,
+	0xE3, 0xAB, 0x2E, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF, 0xE2, 0xA8, 0x2D, 0xFF,
+	0xE2, 0xA7, 0x2C, 0xFF, 0xE1, 0xA6, 0x2B, 0xFF, 0xE0, 0xA4, 0x2A, 0xFF, 0xDB, 0x9F, 0x27, 0xFF,
+	0xCE, 0x94, 0x22, 0xFF, 0xBD, 0x85, 0x1D, 0xFE, 0x94, 0x68, 0x16, 0xB1, 0x1B, 0x13, 0x04, 0x55,
+	0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00, 0x28, 0x01, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x06,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+	0x00, 0x00, 0x00, 0x1B, 0x06, 0x04, 0x01, 0x36, 0x1A, 0x13, 0x04, 0x55, 0x4C, 0x36, 0x0C, 0x7F,
+	0x9B, 0x6D, 0x18, 0xC2, 0xC7, 0x8C, 0x20, 0xFD, 0xD5, 0x9A, 0x25, 0xFF, 0xDD, 0xA3, 0x29, 0xFF,
+	0xE1, 0xA7, 0x2C, 0xFF, 0xE2, 0xA8, 0x2C, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF,
+	0xE4, 0xAB, 0x2E, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE5, 0xAD, 0x30, 0xFF, 0xE5, 0xAE, 0x30, 0xFF,
+	0xE6, 0xAF, 0x31, 0xFF, 0xE6, 0xB0, 0x32, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE8, 0xB2, 0x34, 0xFF,
+	0xE8, 0xB3, 0x34, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xE9, 0xB6, 0x36, 0xFF, 0xEA, 0xB7, 0x37, 0xFF, 0xEB, 0xB9, 0x37, 0xFF, 0xEC, 0xB9, 0x38, 0xFF,
+	0xEC, 0xB9, 0x38, 0xFF, 0xED, 0xBA, 0x39, 0xFF, 0xED, 0xBB, 0x39, 0xFF, 0xED, 0xBC, 0x3A, 0xFF,
+	0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBE, 0x3E, 0xFF, 0xEE, 0xBE, 0x3F, 0xFF,
+	0xEE, 0xBF, 0x41, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xC0, 0x45, 0xFF,
+	0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC1, 0x47, 0xFF, 0xEF, 0xC1, 0x49, 0xFF,
+	0xEF, 0xC2, 0x4A, 0xFF, 0xEF, 0xC2, 0x4A, 0xFF, 0xEF, 0xC2, 0x4B, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF,
+	0xEF, 0xC2, 0x4D, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF,
+	0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF,
+	0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4D, 0xFF,
+	0xEF, 0xC3, 0x4D, 0xFF, 0xEF, 0xC3, 0x4C, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC2, 0x4B, 0xFF,
+	0xEF, 0xC1, 0x4B, 0xFF, 0xEF, 0xC1, 0x4A, 0xFF, 0xEF, 0xC1, 0x49, 0xFF, 0xEF, 0xC1, 0x48, 0xFF,
+	0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xBF, 0x44, 0xFF,
+	0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xBE, 0x42, 0xFF, 0xEE, 0xBE, 0x40, 0xFF, 0xEE, 0xBD, 0x3E, 0xFF,
+	0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBC, 0x3C, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBB, 0x39, 0xFF,
+	0xED, 0xBA, 0x39, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xEB, 0xB9, 0x38, 0xFF,
+	0xEB, 0xB8, 0x37, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xEA, 0xB5, 0x36, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xE9, 0xB4, 0x34, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE8, 0xB2, 0x33, 0xFF, 0xE7, 0xB1, 0x33, 0xFF,
+	0xE7, 0xB1, 0x32, 0xFF, 0xE6, 0xB0, 0x31, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE5, 0xAE, 0x30, 0xFF,
+	0xE4, 0xAD, 0x2F, 0xFF, 0xE3, 0xAB, 0x2E, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE3, 0xA9, 0x2D, 0xFF,
+	0xE3, 0xA9, 0x2D, 0xFF, 0xE1, 0xA7, 0x2C, 0xFF, 0xDD, 0xA2, 0x29, 0xFF, 0xD5, 0x9B, 0x25, 0xFF,
+	0xC8, 0x8F, 0x21, 0xFF, 0xB7, 0x81, 0x1D, 0xF2, 0x8D, 0x63, 0x16, 0xAA, 0x1A, 0x12, 0x04, 0x54,
+	0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x05,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x19, 0x03, 0x02, 0x01, 0x32, 0x02, 0x02, 0x00, 0x4B, 0x39, 0x28, 0x09, 0x72,
+	0x97, 0x6B, 0x18, 0xBB, 0xC6, 0x8D, 0x20, 0xFC, 0xD5, 0x9A, 0x25, 0xFF, 0xDC, 0xA2, 0x29, 0xFF,
+	0xE1, 0xA7, 0x2C, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF, 0xE3, 0xAA, 0x2E, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF,
+	0xE4, 0xAC, 0x2F, 0xFF, 0xE5, 0xAD, 0x30, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE6, 0xAF, 0x31, 0xFF,
+	0xE6, 0xB0, 0x31, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE8, 0xB3, 0x34, 0xFF,
+	0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB6, 0x36, 0xFF,
+	0xEA, 0xB7, 0x37, 0xFF, 0xEB, 0xB8, 0x38, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xED, 0xBA, 0x38, 0xFF,
+	0xED, 0xBA, 0x39, 0xFF, 0xED, 0xBB, 0x3A, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBD, 0x3C, 0xFF,
+	0xED, 0xBE, 0x3D, 0xFF, 0xED, 0xBE, 0x3F, 0xFF, 0xEE, 0xBF, 0x40, 0xFF, 0xEE, 0xBF, 0x42, 0xFF,
+	0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xC1, 0x47, 0xFF,
+	0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC1, 0x4B, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF,
+	0xEF, 0xC3, 0x4D, 0xFF, 0xEF, 0xC3, 0x4D, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF,
+	0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC4, 0x51, 0xFF,
+	0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC4, 0x51, 0xFF,
+	0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC4, 0x50, 0xFF,
+	0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC4, 0x4F, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF,
+	0xEF, 0xC2, 0x4E, 0xFF, 0xEF, 0xC2, 0x4D, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC2, 0x4B, 0xFF,
+	0xEE, 0xC2, 0x4A, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xC0, 0x47, 0xFF,
+	0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xBF, 0x45, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xBE, 0x41, 0xFF,
+	0xEE, 0xBE, 0x3F, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBC, 0x3B, 0xFF,
+	0xED, 0xBB, 0x3A, 0xFF, 0xEC, 0xBB, 0x3A, 0xFF, 0xEC, 0xBB, 0x39, 0xFF, 0xEC, 0xBA, 0x39, 0xFF,
+	0xEB, 0xB9, 0x38, 0xFF, 0xEB, 0xB7, 0x37, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xEA, 0xB6, 0x36, 0xFF,
+	0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE8, 0xB2, 0x33, 0xFF,
+	0xE7, 0xB1, 0x32, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE6, 0xB0, 0x31, 0xFF, 0xE6, 0xAF, 0x31, 0xFF,
+	0xE5, 0xAE, 0x30, 0xFF, 0xE4, 0xAD, 0x2F, 0xFF, 0xE3, 0xAB, 0x2E, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF,
+	0xE4, 0xAA, 0x2E, 0xFF, 0xE1, 0xA7, 0x2D, 0xFF, 0xDA, 0xA0, 0x28, 0xFF, 0xCF, 0x96, 0x23, 0xFE,
+	0xC0, 0x8A, 0x20, 0xF8, 0xAD, 0x7A, 0x1C, 0xE2, 0x83, 0x5C, 0x15, 0x9F, 0x18, 0x11, 0x04, 0x53,
+	0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x04,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05,
+	0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x00, 0x00, 0x3F, 0x20, 0x17, 0x05, 0x62,
+	0x95, 0x6A, 0x18, 0xB3, 0xC7, 0x8E, 0x20, 0xFF, 0xD4, 0x99, 0x24, 0xFF, 0xDB, 0xA1, 0x29, 0xFF,
+	0xE0, 0xA6, 0x2B, 0xFF, 0xE2, 0xA9, 0x2D, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF,
+	0xE5, 0xAD, 0x2F, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE6, 0xB0, 0x31, 0xFF,
+	0xE7, 0xB1, 0x32, 0xFF, 0xE8, 0xB2, 0x33, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE9, 0xB4, 0x35, 0xFF,
+	0xE9, 0xB5, 0x35, 0xFF, 0xEA, 0xB6, 0x35, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xEB, 0xB7, 0x37, 0xFF,
+	0xEB, 0xB8, 0x38, 0xFF, 0xEC, 0xB9, 0x38, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xED, 0xBB, 0x39, 0xFF,
+	0xED, 0xBB, 0x3A, 0xFF, 0xED, 0xBC, 0x3C, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xEE, 0xBD, 0x3F, 0xFF,
+	0xEE, 0xBF, 0x40, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xC0, 0x43, 0xFF, 0xEE, 0xC0, 0x45, 0xFF,
+	0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC2, 0x4A, 0xFF, 0xEF, 0xC2, 0x4B, 0xFF,
+	0xEF, 0xC2, 0x4C, 0xFF, 0xEE, 0xC2, 0x4D, 0xFF, 0xEF, 0xC2, 0x4E, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF,
+	0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC4, 0x52, 0xFF,
+	0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC5, 0x53, 0xFF, 0xEF, 0xC5, 0x53, 0xFF, 0xEF, 0xC5, 0x54, 0xFF,
+	0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC5, 0x54, 0xFF,
+	0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC5, 0x53, 0xFF,
+	0xEF, 0xC5, 0x52, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC4, 0x52, 0xFF,
+	0xEF, 0xC3, 0x51, 0xFF, 0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF,
+	0xEF, 0xC3, 0x4D, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC2, 0x4A, 0xFF, 0xEF, 0xC1, 0x49, 0xFF,
+	0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC0, 0x44, 0xFF,
+	0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x3F, 0xFF, 0xED, 0xBD, 0x3E, 0xFF,
+	0xED, 0xBC, 0x3C, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xEC, 0xBB, 0x3A, 0xFF, 0xEC, 0xBB, 0x39, 0xFF,
+	0xEC, 0xBA, 0x38, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB7, 0x37, 0xFF, 0xEA, 0xB7, 0x36, 0xFF,
+	0xEA, 0xB6, 0x36, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE8, 0xB3, 0x34, 0xFF,
+	0xE8, 0xB2, 0x33, 0xFF, 0xE7, 0xB1, 0x33, 0xFF, 0xE7, 0xB0, 0x32, 0xFF, 0xE6, 0xB0, 0x31, 0xFF,
+	0xE6, 0xAF, 0x31, 0xFF, 0xE5, 0xAE, 0x30, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF,
+	0xE5, 0xAB, 0x2E, 0xFF, 0xE1, 0xA8, 0x2C, 0xFF, 0xD8, 0x9E, 0x27, 0xFF, 0xCB, 0x93, 0x22, 0xFE,
+	0xB6, 0x83, 0x1E, 0xEC, 0x9B, 0x6F, 0x1A, 0xCB, 0x70, 0x50, 0x12, 0x90, 0x14, 0x0E, 0x03, 0x50,
+	0x00, 0x00, 0x00, 0x2F, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x34, 0x08, 0x06, 0x01, 0x54,
+	0x8F, 0x66, 0x17, 0xA9, 0xC2, 0x8B, 0x20, 0xFB, 0xD0, 0x96, 0x24, 0xFF, 0xD8, 0x9E, 0x27, 0xFF,
+	0xDE, 0xA4, 0x2B, 0xFF, 0xE3, 0xAA, 0x2D, 0xFF, 0xE5, 0xAD, 0x2F, 0xFF, 0xE5, 0xAE, 0x30, 0xFF,
+	0xE5, 0xAE, 0x30, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE7, 0xB1, 0x32, 0xFF,
+	0xE7, 0xB2, 0x33, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xE9, 0xB6, 0x35, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEB, 0xB9, 0x38, 0xFF,
+	0xEC, 0xBA, 0x39, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xED, 0xBB, 0x3A, 0xFF, 0xED, 0xBC, 0x3B, 0xFF,
+	0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xEE, 0xBE, 0x40, 0xFF, 0xEE, 0xBE, 0x42, 0xFF,
+	0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xC1, 0x46, 0xFF, 0xEE, 0xC1, 0x48, 0xFF,
+	0xEE, 0xC2, 0x4A, 0xFF, 0xEE, 0xC2, 0x4B, 0xFF, 0xEE, 0xC3, 0x4C, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF,
+	0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC3, 0x51, 0xFF, 0xEF, 0xC4, 0x52, 0xFF,
+	0xEF, 0xC4, 0x53, 0xFF, 0xEF, 0xC4, 0x54, 0xFF, 0xEF, 0xC4, 0x54, 0xFF, 0xEF, 0xC5, 0x55, 0xFF,
+	0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC6, 0x56, 0xFF, 0xEF, 0xC6, 0x56, 0xFF, 0xEF, 0xC6, 0x57, 0xFF,
+	0xEF, 0xC6, 0x57, 0xFF, 0xEF, 0xC6, 0x57, 0xFF, 0xEF, 0xC6, 0x57, 0xFF, 0xEF, 0xC6, 0x57, 0xFF,
+	0xEF, 0xC6, 0x57, 0xFF, 0xEF, 0xC6, 0x57, 0xFF, 0xEF, 0xC6, 0x57, 0xFF, 0xEF, 0xC6, 0x56, 0xFF,
+	0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC5, 0x55, 0xFF,
+	0xEF, 0xC4, 0x54, 0xFF, 0xEF, 0xC4, 0x53, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC4, 0x51, 0xFF,
+	0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC2, 0x4D, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF,
+	0xEF, 0xC1, 0x4B, 0xFF, 0xEE, 0xC1, 0x4A, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC1, 0x47, 0xFF,
+	0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xBF, 0x41, 0xFF, 0xED, 0xBE, 0x41, 0xFF,
+	0xED, 0xBE, 0x3F, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBB, 0x3A, 0xFF,
+	0xED, 0xBB, 0x39, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB8, 0x37, 0xFF,
+	0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB6, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB4, 0x35, 0xFF,
+	0xE8, 0xB3, 0x34, 0xFF, 0xE8, 0xB2, 0x33, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE7, 0xB0, 0x32, 0xFF,
+	0xE6, 0xB0, 0x31, 0xFF, 0xE6, 0xAE, 0x31, 0xFF, 0xE5, 0xAD, 0x30, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF,
+	0xE5, 0xAC, 0x2E, 0xFF, 0xE2, 0xA9, 0x2C, 0xFF, 0xD7, 0x9E, 0x27, 0xFF, 0xC8, 0x90, 0x22, 0xFE,
+	0xAC, 0x7B, 0x1C, 0xDF, 0x86, 0x60, 0x16, 0xB4, 0x59, 0x40, 0x0F, 0x80, 0x0F, 0x0B, 0x03, 0x4C,
+	0x00, 0x00, 0x00, 0x2D, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x03,
+	0x02, 0x01, 0x00, 0x12, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x30, 0x02, 0x01, 0x00, 0x4E,
+	0x7F, 0x5B, 0x14, 0x9B, 0xB1, 0x7F, 0x1D, 0xE6, 0xC4, 0x8D, 0x21, 0xFD, 0xD2, 0x98, 0x25, 0xFE,
+	0xDC, 0xA2, 0x2A, 0xFF, 0xE4, 0xAB, 0x2E, 0xFF, 0xE7, 0xAE, 0x30, 0xFF, 0xE6, 0xAE, 0x30, 0xFF,
+	0xE6, 0xAF, 0x31, 0xFF, 0xE6, 0xB0, 0x31, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE7, 0xB2, 0x33, 0xFF,
+	0xE8, 0xB3, 0x34, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB6, 0x35, 0xFF,
+	0xEA, 0xB7, 0x36, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEC, 0xBA, 0x39, 0xFF,
+	0xEC, 0xBB, 0x3A, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBC, 0x3C, 0xFF, 0xED, 0xBD, 0x3D, 0xFF,
+	0xED, 0xBE, 0x3F, 0xFF, 0xEE, 0xBE, 0x41, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xC0, 0x44, 0xFF,
+	0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC2, 0x4B, 0xFF,
+	0xEE, 0xC3, 0x4C, 0xFF, 0xEE, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC3, 0x51, 0xFF,
+	0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC4, 0x53, 0xFF, 0xF0, 0xC4, 0x54, 0xFF, 0xEF, 0xC5, 0x55, 0xFF,
+	0xEF, 0xC5, 0x56, 0xFF, 0xEF, 0xC5, 0x57, 0xFF, 0xEF, 0xC5, 0x58, 0xFF, 0xEF, 0xC6, 0x58, 0xFF,
+	0xEF, 0xC6, 0x58, 0xFF, 0xEF, 0xC7, 0x59, 0xFF, 0xEF, 0xC7, 0x59, 0xFF, 0xEF, 0xC7, 0x5A, 0xFF,
+	0xEF, 0xC7, 0x5A, 0xFF, 0xEF, 0xC7, 0x5A, 0xFF, 0xEF, 0xC7, 0x5A, 0xFF, 0xEF, 0xC7, 0x5A, 0xFF,
+	0xEF, 0xC7, 0x5A, 0xFF, 0xEF, 0xC7, 0x5A, 0xFF, 0xEF, 0xC7, 0x5A, 0xFF, 0xEF, 0xC7, 0x59, 0xFF,
+	0xEF, 0xC6, 0x59, 0xFF, 0xEF, 0xC6, 0x58, 0xFF, 0xEF, 0xC6, 0x58, 0xFF, 0xEF, 0xC6, 0x57, 0xFF,
+	0xEF, 0xC6, 0x57, 0xFF, 0xEF, 0xC5, 0x56, 0xFF, 0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC5, 0x53, 0xFF,
+	0xEF, 0xC4, 0x53, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF,
+	0xEF, 0xC2, 0x4E, 0xFF, 0xEE, 0xC2, 0x4D, 0xFF, 0xEE, 0xC2, 0x4C, 0xFF, 0xEE, 0xC2, 0x4A, 0xFF,
+	0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC0, 0x44, 0xFF, 0xED, 0xBF, 0x43, 0xFF,
+	0xED, 0xBF, 0x42, 0xFF, 0xED, 0xBD, 0x40, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBD, 0x3C, 0xFF,
+	0xED, 0xBC, 0x3A, 0xFF, 0xED, 0xBB, 0x3A, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xEB, 0xB9, 0x38, 0xFF,
+	0xEA, 0xB8, 0x37, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB6, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB3, 0x34, 0xFF, 0xE8, 0xB2, 0x33, 0xFF, 0xE7, 0xB1, 0x32, 0xFF,
+	0xE7, 0xB0, 0x32, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE5, 0xAE, 0x31, 0xFF, 0xE5, 0xAD, 0x30, 0xFF,
+	0xE5, 0xAD, 0x2F, 0xFF, 0xE1, 0xA8, 0x2D, 0xFF, 0xD7, 0x9E, 0x27, 0xFF, 0xC8, 0x90, 0x22, 0xFD,
+	0xA5, 0x76, 0x1B, 0xD5, 0x72, 0x52, 0x13, 0xA3, 0x45, 0x31, 0x0B, 0x74, 0x0C, 0x08, 0x02, 0x48,
+	0x00, 0x00, 0x00, 0x2A, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x2E, 0x05, 0x04, 0x01, 0x4B,
+	0x66, 0x49, 0x10, 0x89, 0x96, 0x6C, 0x19, 0xC9, 0xB3, 0x81, 0x1E, 0xEB, 0xCB, 0x93, 0x23, 0xFC,
+	0xDA, 0xA0, 0x29, 0xFF, 0xE4, 0xAC, 0x2F, 0xFF, 0xE8, 0xB0, 0x31, 0xFF, 0xE6, 0xAF, 0x31, 0xFF,
+	0xE6, 0xB0, 0x31, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE8, 0xB3, 0x34, 0xFF,
+	0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB6, 0x35, 0xFF, 0xEA, 0xB7, 0x36, 0xFF,
+	0xEB, 0xB8, 0x37, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xEC, 0xBB, 0x3A, 0xFF,
+	0xED, 0xBD, 0x3A, 0xFF, 0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBE, 0x3E, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC1, 0x47, 0xFF,
+	0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC1, 0x4A, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF,
+	0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC4, 0x53, 0xFF,
+	0xEF, 0xC4, 0x54, 0xFF, 0xF0, 0xC5, 0x55, 0xFF, 0xF0, 0xC5, 0x56, 0xFF, 0xF0, 0xC7, 0x58, 0xFF,
+	0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF,
+	0xF0, 0xC7, 0x5C, 0xFF, 0xF0, 0xC7, 0x5C, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF,
+	0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF,
+	0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5C, 0xFF,
+	0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF,
+	0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC6, 0x57, 0xFF, 0xF0, 0xC6, 0x56, 0xFF,
+	0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC4, 0x53, 0xFF, 0xEF, 0xC4, 0x52, 0xFF,
+	0xEF, 0xC3, 0x51, 0xFF, 0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC2, 0x4E, 0xFF, 0xEF, 0xC2, 0x4D, 0xFF,
+	0xEF, 0xC2, 0x4B, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC0, 0x46, 0xFF,
+	0xEE, 0xBF, 0x45, 0xFF, 0xEE, 0xBE, 0x42, 0xFF, 0xEE, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x3E, 0xFF,
+	0xED, 0xBE, 0x3C, 0xFF, 0xED, 0xBD, 0x3B, 0xFF, 0xED, 0xBC, 0x3A, 0xFF, 0xEC, 0xBA, 0x39, 0xFF,
+	0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB8, 0x37, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB6, 0x36, 0xFF,
+	0xEA, 0xB5, 0x36, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE8, 0xB2, 0x33, 0xFF,
+	0xE7, 0xB1, 0x32, 0xFF, 0xE7, 0xB0, 0x32, 0xFF, 0xE6, 0xAF, 0x31, 0xFF, 0xE6, 0xAD, 0x31, 0xFF,
+	0xE4, 0xAC, 0x30, 0xFF, 0xE0, 0xA8, 0x2D, 0xFF, 0xD8, 0x9F, 0x28, 0xFF, 0xC9, 0x92, 0x23, 0xFD,
+	0xA0, 0x72, 0x1B, 0xCC, 0x5D, 0x41, 0x0F, 0x92, 0x2E, 0x1F, 0x07, 0x67, 0x08, 0x06, 0x01, 0x43,
+	0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x2C, 0x04, 0x03, 0x01, 0x47,
+	0x41, 0x2F, 0x0A, 0x74, 0x6F, 0x50, 0x12, 0xA6, 0xA1, 0x73, 0x1B, 0xD5, 0xC8, 0x90, 0x22, 0xFB,
+	0xD9, 0x9F, 0x28, 0xFF, 0xE3, 0xAB, 0x2F, 0xFF, 0xE8, 0xB0, 0x31, 0xFF, 0xE7, 0xB0, 0x31, 0xFF,
+	0xE7, 0xB0, 0x32, 0xFF, 0xE7, 0xB2, 0x33, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE9, 0xB4, 0x35, 0xFF,
+	0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB6, 0x35, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xEB, 0xB8, 0x37, 0xFF,
+	0xEB, 0xB9, 0x38, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xEC, 0xBB, 0x3A, 0xFF, 0xED, 0xBC, 0x3B, 0xFF,
+	0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBE, 0x3E, 0xFF, 0xED, 0xBF, 0x40, 0xFF, 0xEE, 0xBF, 0x42, 0xFF,
+	0xEE, 0xBF, 0x44, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC2, 0x4A, 0xFF,
+	0xEE, 0xC2, 0x4B, 0xFF, 0xEE, 0xC2, 0x4D, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC4, 0x50, 0xFF,
+	0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC5, 0x53, 0xFF, 0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC5, 0x56, 0xFF,
+	0xF0, 0xC5, 0x57, 0xFF, 0xF0, 0xC6, 0x58, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC8, 0x5B, 0xFF,
+	0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF,
+	0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC8, 0x5F, 0xFF, 0xF0, 0xC9, 0x5F, 0xFF, 0xF0, 0xC9, 0x60, 0xFF,
+	0xF0, 0xC9, 0x60, 0xFF, 0xF0, 0xC9, 0x60, 0xFF, 0xF0, 0xC9, 0x60, 0xFF, 0xF0, 0xC9, 0x60, 0xFF,
+	0xF0, 0xC9, 0x60, 0xFF, 0xF0, 0xC9, 0x60, 0xFF, 0xF0, 0xC9, 0x5F, 0xFF, 0xF0, 0xC9, 0x5F, 0xFF,
+	0xF0, 0xC9, 0x5F, 0xFF, 0xF0, 0xC9, 0x5F, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF,
+	0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC7, 0x59, 0xFF,
+	0xF0, 0xC7, 0x58, 0xFF, 0xEF, 0xC6, 0x57, 0xFF, 0xEF, 0xC6, 0x56, 0xFF, 0xEF, 0xC5, 0x55, 0xFF,
+	0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC3, 0x50, 0xFF,
+	0xEF, 0xC2, 0x4E, 0xFF, 0xEE, 0xC2, 0x4C, 0xFF, 0xEE, 0xC1, 0x4A, 0xFF, 0xEE, 0xC1, 0x49, 0xFF,
+	0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xBF, 0x45, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xBF, 0x40, 0xFF,
+	0xED, 0xBE, 0x3E, 0xFF, 0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xEC, 0xBB, 0x3A, 0xFF,
+	0xEC, 0xBA, 0x39, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB8, 0x37, 0xFF, 0xEA, 0xB7, 0x36, 0xFF,
+	0xEA, 0xB6, 0x36, 0xFF, 0xEA, 0xB5, 0x36, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE8, 0xB3, 0x34, 0xFF,
+	0xE8, 0xB2, 0x33, 0xFF, 0xE7, 0xB1, 0x32, 0xFF, 0xE7, 0xB0, 0x32, 0xFF, 0xE6, 0xAE, 0x31, 0xFF,
+	0xE4, 0xAC, 0x30, 0xFF, 0xDF, 0xA7, 0x2D, 0xFF, 0xD9, 0x9F, 0x28, 0xFF, 0xCB, 0x92, 0x23, 0xFF,
+	0x9A, 0x6E, 0x1A, 0xC2, 0x3E, 0x2B, 0x0A, 0x7E, 0x0A, 0x06, 0x01, 0x57, 0x04, 0x02, 0x01, 0x3C,
+	0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x29, 0x01, 0x01, 0x00, 0x42,
+	0x0B, 0x08, 0x02, 0x5E, 0x34, 0x26, 0x09, 0x82, 0x8C, 0x64, 0x17, 0xBD, 0xC5, 0x8E, 0x22, 0xF9,
+	0xD9, 0x9F, 0x28, 0xFF, 0xE2, 0xAA, 0x2E, 0xFF, 0xE7, 0xB0, 0x31, 0xFF, 0xE7, 0xB0, 0x32, 0xFF,
+	0xE7, 0xB1, 0x33, 0xFF, 0xE8, 0xB3, 0x34, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xE9, 0xB6, 0x35, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEB, 0xB9, 0x38, 0xFF,
+	0xEC, 0xBA, 0x39, 0xFF, 0xEC, 0xBB, 0x39, 0xFF, 0xED, 0xBC, 0x3A, 0xFF, 0xED, 0xBD, 0x3C, 0xFF,
+	0xED, 0xBE, 0x3E, 0xFF, 0xED, 0xBF, 0x40, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xC0, 0x44, 0xFF,
+	0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEF, 0xC1, 0x4A, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF,
+	0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC5, 0x52, 0xFF,
+	0xEF, 0xC5, 0x54, 0xFF, 0xF0, 0xC6, 0x56, 0xFF, 0xF0, 0xC6, 0x57, 0xFF, 0xF0, 0xC6, 0x59, 0xFF,
+	0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC7, 0x5C, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC9, 0x5E, 0xFF,
+	0xF0, 0xC9, 0x5F, 0xFF, 0xF1, 0xC9, 0x60, 0xFF, 0xF1, 0xC9, 0x60, 0xFF, 0xF1, 0xC9, 0x61, 0xFF,
+	0xF1, 0xCA, 0x61, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCA, 0x63, 0xFF,
+	0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xCB, 0x63, 0xFF, 0xF1, 0xCB, 0x63, 0xFF,
+	0xF1, 0xCB, 0x63, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCA, 0x62, 0xFF,
+	0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCA, 0x61, 0xFF, 0xF1, 0xC9, 0x60, 0xFF,
+	0xF1, 0xC9, 0x5F, 0xFF, 0xF1, 0xC9, 0x5F, 0xFF, 0xF0, 0xC9, 0x5E, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF,
+	0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC7, 0x58, 0xFF,
+	0xF0, 0xC6, 0x57, 0xFF, 0xF0, 0xC6, 0x55, 0xFF, 0xF0, 0xC5, 0x54, 0xFF, 0xEF, 0xC4, 0x52, 0xFF,
+	0xEF, 0xC3, 0x51, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC2, 0x4D, 0xFF, 0xEF, 0xC2, 0x4B, 0xFF,
+	0xEF, 0xC1, 0x49, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xBF, 0x45, 0xFF, 0xEE, 0xBF, 0x43, 0xFF,
+	0xEE, 0xBF, 0x41, 0xFF, 0xED, 0xBE, 0x3E, 0xFF, 0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBC, 0x3B, 0xFF,
+	0xED, 0xBC, 0x3A, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB8, 0x37, 0xFF,
+	0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB4, 0x34, 0xFF,
+	0xE8, 0xB3, 0x33, 0xFF, 0xE8, 0xB2, 0x33, 0xFF, 0xE8, 0xB2, 0x32, 0xFF, 0xE6, 0xB0, 0x31, 0xFF,
+	0xE3, 0xAC, 0x2F, 0xFF, 0xDD, 0xA6, 0x2C, 0xFF, 0xD8, 0x9E, 0x28, 0xFF, 0xCA, 0x91, 0x23, 0xFF,
+	0x92, 0x68, 0x19, 0xB7, 0x15, 0x0F, 0x03, 0x68, 0x00, 0x00, 0x00, 0x47, 0x00, 0x00, 0x00, 0x35,
+	0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x3D,
+	0x00, 0x00, 0x00, 0x4F, 0x09, 0x07, 0x01, 0x6D, 0x7F, 0x5C, 0x16, 0xAF, 0xC3, 0x8D, 0x22, 0xF6,
+	0xD7, 0x9E, 0x28, 0xFF, 0xDF, 0xA8, 0x2D, 0xFF, 0xE5, 0xAE, 0x31, 0xFF, 0xE7, 0xB1, 0x33, 0xFF,
+	0xE8, 0xB3, 0x34, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB6, 0x35, 0xFF,
+	0xEA, 0xB7, 0x36, 0xFF, 0xEB, 0xB8, 0x37, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEC, 0xBA, 0x39, 0xFF,
+	0xEC, 0xBB, 0x3A, 0xFF, 0xED, 0xBC, 0x3A, 0xFF, 0xED, 0xBC, 0x3C, 0xFF, 0xED, 0xBD, 0x3E, 0xFF,
+	0xED, 0xBE, 0x40, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC1, 0x47, 0xFF,
+	0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC2, 0x4B, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF,
+	0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC5, 0x53, 0xFF, 0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC5, 0x55, 0xFF,
+	0xF0, 0xC6, 0x57, 0xFF, 0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC8, 0x5B, 0xFF,
+	0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC9, 0x5F, 0xFF, 0xF0, 0xC9, 0x60, 0xFF,
+	0xF0, 0xCA, 0x61, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xCA, 0x64, 0xFF,
+	0xF1, 0xCB, 0x64, 0xFF, 0xF1, 0xCB, 0x64, 0xFF, 0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCB, 0x65, 0xFF,
+	0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCB, 0x66, 0xFF,
+	0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCB, 0x65, 0xFF,
+	0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCB, 0x64, 0xFF, 0xF1, 0xCB, 0x64, 0xFF, 0xF1, 0xCA, 0x64, 0xFF,
+	0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xC9, 0x61, 0xFF, 0xF0, 0xC9, 0x60, 0xFF, 0xF0, 0xC9, 0x5F, 0xFF,
+	0xF0, 0xC9, 0x5F, 0xFF, 0xF0, 0xC9, 0x5E, 0xFF, 0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF,
+	0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC6, 0x58, 0xFF, 0xF0, 0xC6, 0x56, 0xFF, 0xEF, 0xC5, 0x55, 0xFF,
+	0xEF, 0xC4, 0x53, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC3, 0x4D, 0xFF,
+	0xEF, 0xC2, 0x4B, 0xFF, 0xEE, 0xC1, 0x4A, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC0, 0x45, 0xFF,
+	0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xBE, 0x40, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBD, 0x3C, 0xFF,
+	0xED, 0xBC, 0x3B, 0xFF, 0xEC, 0xBB, 0x3A, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xEB, 0xB9, 0x38, 0xFF,
+	0xEA, 0xB8, 0x37, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xE9, 0xB6, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF,
+	0xE9, 0xB4, 0x34, 0xFF, 0xE8, 0xB3, 0x33, 0xFF, 0xE9, 0xB3, 0x33, 0xFF, 0xE6, 0xB0, 0x32, 0xFF,
+	0xE1, 0xAA, 0x2E, 0xFF, 0xD8, 0xA1, 0x2A, 0xFF, 0xCD, 0x96, 0x26, 0xFF, 0xBA, 0x86, 0x21, 0xEE,
+	0x80, 0x5C, 0x16, 0xA6, 0x00, 0x00, 0x00, 0x5B, 0x00, 0x00, 0x00, 0x3D, 0x00, 0x00, 0x00, 0x2F,
+	0x02, 0x02, 0x00, 0x1A, 0x01, 0x01, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x35,
+	0x00, 0x00, 0x00, 0x47, 0x02, 0x02, 0x00, 0x64, 0x7E, 0x5C, 0x16, 0xA9, 0xC1, 0x8D, 0x22, 0xF2,
+	0xD4, 0x9C, 0x28, 0xFF, 0xDB, 0xA4, 0x2C, 0xFF, 0xE2, 0xAB, 0x30, 0xFF, 0xE6, 0xB1, 0x33, 0xFF,
+	0xE9, 0xB4, 0x34, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xEA, 0xB7, 0x36, 0xFF,
+	0xEB, 0xB8, 0x37, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xEC, 0xBB, 0x39, 0xFF,
+	0xED, 0xBC, 0x3A, 0xFF, 0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xC2, 0x49, 0xFF,
+	0xEF, 0xC2, 0x4B, 0xFF, 0xEF, 0xC3, 0x4D, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC4, 0x51, 0xFF,
+	0xF0, 0xC5, 0x53, 0xFF, 0xF0, 0xC6, 0x54, 0xFF, 0xF0, 0xC6, 0x56, 0xFF, 0xF0, 0xC6, 0x58, 0xFF,
+	0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF1, 0xC8, 0x5E, 0xFF,
+	0xF1, 0xC9, 0x5F, 0xFF, 0xF1, 0xC9, 0x60, 0xFF, 0xF1, 0xC9, 0x62, 0xFF, 0xF1, 0xCA, 0x63, 0xFF,
+	0xF1, 0xCB, 0x64, 0xFF, 0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF2, 0xCB, 0x67, 0xFF,
+	0xF2, 0xCC, 0x67, 0xFF, 0xF2, 0xCC, 0x68, 0xFF, 0xF2, 0xCC, 0x68, 0xFF, 0xF2, 0xCC, 0x69, 0xFF,
+	0xF2, 0xCB, 0x69, 0xFF, 0xF2, 0xCB, 0x6A, 0xFF, 0xF2, 0xCC, 0x6A, 0xFF, 0xF2, 0xCC, 0x6A, 0xFF,
+	0xF2, 0xCC, 0x69, 0xFF, 0xF2, 0xCC, 0x69, 0xFF, 0xF2, 0xCC, 0x69, 0xFF, 0xF2, 0xCC, 0x68, 0xFF,
+	0xF2, 0xCC, 0x67, 0xFF, 0xF2, 0xCC, 0x67, 0xFF, 0xF1, 0xCC, 0x67, 0xFF, 0xF1, 0xCB, 0x67, 0xFF,
+	0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCA, 0x65, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xCA, 0x62, 0xFF,
+	0xF1, 0xCA, 0x61, 0xFF, 0xF1, 0xC9, 0x60, 0xFF, 0xF0, 0xC9, 0x5F, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF,
+	0xF0, 0xC7, 0x5C, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC6, 0x59, 0xFF, 0xF0, 0xC6, 0x57, 0xFF,
+	0xF0, 0xC5, 0x55, 0xFF, 0xEF, 0xC5, 0x53, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC3, 0x50, 0xFF,
+	0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC2, 0x4A, 0xFF, 0xEE, 0xC1, 0x47, 0xFF,
+	0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xBE, 0x41, 0xFF, 0xED, 0xBE, 0x3F, 0xFF,
+	0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBB, 0x3A, 0xFF, 0xEC, 0xBA, 0x38, 0xFF,
+	0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB8, 0x37, 0xFF, 0xEA, 0xB7, 0x36, 0xFF, 0xE9, 0xB6, 0x35, 0xFF,
+	0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB5, 0x34, 0xFF, 0xEA, 0xB5, 0x34, 0xFF, 0xE7, 0xB1, 0x32, 0xFF,
+	0xDF, 0xA7, 0x2D, 0xFF, 0xD1, 0x99, 0x27, 0xFD, 0xB6, 0x85, 0x21, 0xEB, 0x95, 0x6D, 0x1B, 0xCB,
+	0x61, 0x47, 0x11, 0x8F, 0x01, 0x01, 0x00, 0x54, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x28,
+	0x01, 0x01, 0x00, 0x15, 0x01, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x2E,
+	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x5C, 0x72, 0x53, 0x14, 0x9C, 0xB2, 0x82, 0x20, 0xE1,
+	0xC9, 0x93, 0x25, 0xFB, 0xD6, 0x9F, 0x2A, 0xFE, 0xE0, 0xA9, 0x2E, 0xFF, 0xE6, 0xB1, 0x33, 0xFF,
+	0xEA, 0xB5, 0x35, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB6, 0x36, 0xFF, 0xEB, 0xB7, 0x37, 0xFF,
+	0xEB, 0xB9, 0x38, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xEC, 0xBB, 0x3A, 0xFF, 0xED, 0xBC, 0x3B, 0xFF,
+	0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBE, 0x3E, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xEE, 0xBF, 0x43, 0xFF,
+	0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC2, 0x49, 0xFF, 0xEE, 0xC3, 0x4B, 0xFF,
+	0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC5, 0x54, 0xFF,
+	0xF0, 0xC6, 0x55, 0xFF, 0xF0, 0xC6, 0x56, 0xFF, 0xF0, 0xC6, 0x58, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF,
+	0xF0, 0xC7, 0x5C, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF1, 0xC9, 0x60, 0xFF, 0xF1, 0xC9, 0x61, 0xFF,
+	0xF1, 0xC9, 0x62, 0xFF, 0xF1, 0xC9, 0x63, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xCB, 0x66, 0xFF,
+	0xF1, 0xCC, 0x67, 0xFF, 0xF1, 0xCC, 0x68, 0xFF, 0xF1, 0xCC, 0x69, 0xFF, 0xF2, 0xCC, 0x6A, 0xFF,
+	0xF2, 0xCC, 0x6B, 0xFF, 0xF2, 0xCD, 0x6B, 0xFF, 0xF2, 0xCD, 0x6B, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF,
+	0xF2, 0xCC, 0x6C, 0xFF, 0xF2, 0xCC, 0x6D, 0xFF, 0xF2, 0xCC, 0x6D, 0xFF, 0xF2, 0xCC, 0x6D, 0xFF,
+	0xF2, 0xCC, 0x6C, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF,
+	0xF2, 0xCD, 0x6B, 0xFF, 0xF2, 0xCD, 0x6A, 0xFF, 0xF1, 0xCD, 0x6A, 0xFF, 0xF1, 0xCC, 0x6A, 0xFF,
+	0xF1, 0xCC, 0x69, 0xFF, 0xF1, 0xCB, 0x68, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCA, 0x65, 0xFF,
+	0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xC9, 0x62, 0xFF, 0xF0, 0xC8, 0x60, 0xFF,
+	0xF0, 0xC8, 0x5F, 0xFF, 0xF0, 0xC7, 0x5D, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC6, 0x5A, 0xFF,
+	0xF0, 0xC6, 0x58, 0xFF, 0xEF, 0xC6, 0x56, 0xFF, 0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC4, 0x52, 0xFF,
+	0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4C, 0xFF, 0xEE, 0xC2, 0x4A, 0xFF,
+	0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xBF, 0x44, 0xFF, 0xEE, 0xBE, 0x41, 0xFF,
+	0xED, 0xBD, 0x3F, 0xFF, 0xED, 0xBC, 0x3D, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBB, 0x39, 0xFF,
+	0xEC, 0xBA, 0x39, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB8, 0x37, 0xFF, 0xEA, 0xB7, 0x36, 0xFF,
+	0xEA, 0xB6, 0x36, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xE9, 0xB5, 0x34, 0xFF, 0xE5, 0xAF, 0x31, 0xFF,
+	0xDD, 0xA4, 0x2B, 0xFF, 0xCC, 0x94, 0x25, 0xFA, 0xA0, 0x75, 0x1D, 0xD5, 0x6A, 0x4E, 0x13, 0xA9,
+	0x3B, 0x2C, 0x0B, 0x79, 0x03, 0x02, 0x01, 0x4D, 0x00, 0x00, 0x00, 0x33, 0x00, 0x00, 0x00, 0x22,
+	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x27,
+	0x00, 0x00, 0x00, 0x39, 0x00, 0x00, 0x00, 0x54, 0x52, 0x3B, 0x0E, 0x87, 0x8B, 0x65, 0x19, 0xC0,
+	0xB1, 0x81, 0x20, 0xE5, 0xD1, 0x99, 0x27, 0xFC, 0xE0, 0xA8, 0x2D, 0xFF, 0xE8, 0xB3, 0x33, 0xFF,
+	0xEB, 0xB7, 0x36, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xEA, 0xB7, 0x37, 0xFF, 0xEB, 0xB8, 0x38, 0xFF,
+	0xEC, 0xBA, 0x39, 0xFF, 0xEC, 0xBB, 0x39, 0xFF, 0xED, 0xBC, 0x3A, 0xFF, 0xED, 0xBD, 0x3C, 0xFF,
+	0xED, 0xBE, 0x3E, 0xFF, 0xED, 0xBE, 0x40, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xC0, 0x45, 0xFF,
+	0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC2, 0x4A, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF,
+	0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC5, 0x55, 0xFF, 0xF0, 0xC6, 0x57, 0xFF,
+	0xF0, 0xC6, 0x58, 0xFF, 0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF,
+	0xF0, 0xC9, 0x5F, 0xFF, 0xF1, 0xC9, 0x61, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCA, 0x64, 0xFF,
+	0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCB, 0x68, 0xFF, 0xF2, 0xCC, 0x69, 0xFF,
+	0xF2, 0xCD, 0x6A, 0xFF, 0xF2, 0xCD, 0x6B, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF,
+	0xF2, 0xCD, 0x6E, 0xFF, 0xF2, 0xCD, 0x6E, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF,
+	0xF2, 0xCE, 0x70, 0xFF, 0xF2, 0xCE, 0x70, 0xFF, 0xF2, 0xCE, 0x71, 0xFF, 0xF2, 0xCE, 0x71, 0xFF,
+	0xF2, 0xCE, 0x70, 0xFF, 0xF2, 0xCE, 0x70, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF,
+	0xF2, 0xCE, 0x6E, 0xFF, 0xF2, 0xCD, 0x6E, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF,
+	0xF2, 0xCD, 0x6C, 0xFF, 0xF2, 0xCC, 0x6A, 0xFF, 0xF1, 0xCC, 0x69, 0xFF, 0xF1, 0xCC, 0x68, 0xFF,
+	0xF1, 0xCB, 0x67, 0xFF, 0xF1, 0xCA, 0x66, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xCA, 0x63, 0xFF,
+	0xF1, 0xC9, 0x61, 0xFF, 0xF1, 0xC8, 0x5F, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC7, 0x5C, 0xFF,
+	0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC7, 0x58, 0xFF, 0xF0, 0xC6, 0x56, 0xFF, 0xF0, 0xC5, 0x55, 0xFF,
+	0xF0, 0xC4, 0x53, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4C, 0xFF,
+	0xEF, 0xC2, 0x4A, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xBF, 0x43, 0xFF,
+	0xEE, 0xBE, 0x40, 0xFF, 0xED, 0xBE, 0x3E, 0xFF, 0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBC, 0x3B, 0xFF,
+	0xED, 0xBB, 0x3A, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xEB, 0xB9, 0x38, 0xFF, 0xEA, 0xB8, 0x37, 0xFF,
+	0xEA, 0xB7, 0x36, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE6, 0xB1, 0x33, 0xFF, 0xE1, 0xAB, 0x2F, 0xFF,
+	0xDB, 0xA2, 0x2B, 0xFF, 0xC9, 0x92, 0x25, 0xF9, 0x8C, 0x66, 0x19, 0xC0, 0x32, 0x26, 0x09, 0x86,
+	0x0A, 0x08, 0x02, 0x62, 0x02, 0x01, 0x00, 0x47, 0x00, 0x00, 0x00, 0x2E, 0x00, 0x00, 0x00, 0x1B,
+	0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x20,
+	0x00, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x4C, 0x2D, 0x20, 0x07, 0x72, 0x5C, 0x42, 0x10, 0x9E,
+	0x96, 0x6C, 0x1A, 0xCB, 0xC8, 0x91, 0x24, 0xF5, 0xDC, 0xA4, 0x2B, 0xFF, 0xE5, 0xB0, 0x32, 0xFF,
+	0xEA, 0xB7, 0x36, 0xFF, 0xEA, 0xB7, 0x37, 0xFF, 0xEB, 0xB8, 0x38, 0xFF, 0xEC, 0xB9, 0x38, 0xFF,
+	0xEC, 0xBA, 0x39, 0xFF, 0xED, 0xBB, 0x3A, 0xFF, 0xED, 0xBC, 0x3C, 0xFF, 0xED, 0xBD, 0x3E, 0xFF,
+	0xED, 0xBE, 0x40, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC1, 0x48, 0xFF,
+	0xEE, 0xC2, 0x4A, 0xFF, 0xEE, 0xC3, 0x4C, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x50, 0xFF,
+	0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC5, 0x55, 0xFF, 0xF0, 0xC6, 0x57, 0xFF, 0xF0, 0xC6, 0x59, 0xFF,
+	0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC7, 0x5C, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC9, 0x60, 0xFF,
+	0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCB, 0x66, 0xFF,
+	0xF1, 0xCC, 0x68, 0xFF, 0xF1, 0xCC, 0x69, 0xFF, 0xF1, 0xCD, 0x6B, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF,
+	0xF2, 0xCE, 0x6D, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCE, 0x70, 0xFF,
+	0xF2, 0xCE, 0x71, 0xFF, 0xF2, 0xCE, 0x71, 0xFF, 0xF2, 0xCE, 0x72, 0xFF, 0xF2, 0xCF, 0x72, 0xFF,
+	0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xCF, 0x74, 0xFF, 0xF2, 0xCF, 0x74, 0xFF,
+	0xF2, 0xCF, 0x74, 0xFF, 0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xCF, 0x72, 0xFF,
+	0xF2, 0xCE, 0x72, 0xFF, 0xF2, 0xCE, 0x71, 0xFF, 0xF2, 0xCE, 0x70, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF,
+	0xF2, 0xCD, 0x6E, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF, 0xF1, 0xCD, 0x6C, 0xFF, 0xF1, 0xCD, 0x6B, 0xFF,
+	0xF1, 0xCC, 0x6A, 0xFF, 0xF1, 0xCB, 0x68, 0xFF, 0xF1, 0xCB, 0x67, 0xFF, 0xF1, 0xCB, 0x66, 0xFF,
+	0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xC9, 0x62, 0xFF, 0xF1, 0xC9, 0x60, 0xFF, 0xF0, 0xC8, 0x5F, 0xFF,
+	0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC6, 0x57, 0xFF,
+	0xF0, 0xC5, 0x55, 0xFF, 0xEF, 0xC4, 0x53, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC4, 0x4E, 0xFF,
+	0xEF, 0xC3, 0x4C, 0xFF, 0xEE, 0xC2, 0x4A, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC0, 0x45, 0xFF,
+	0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xBF, 0x40, 0xFF, 0xED, 0xBE, 0x3E, 0xFF, 0xED, 0xBD, 0x3C, 0xFF,
+	0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBA, 0x39, 0xFF, 0xEB, 0xBA, 0x39, 0xFF, 0xEB, 0xB9, 0x38, 0xFF,
+	0xEB, 0xB8, 0x37, 0xFF, 0xE9, 0xB4, 0x35, 0xFF, 0xE3, 0xAE, 0x31, 0xFF, 0xDC, 0xA5, 0x2D, 0xFF,
+	0xD3, 0x9C, 0x29, 0xFF, 0xBE, 0x8B, 0x23, 0xEF, 0x77, 0x56, 0x15, 0xAB, 0x00, 0x00, 0x00, 0x6C,
+	0x00, 0x00, 0x00, 0x51, 0x01, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x15,
+	0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x19,
+	0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x42, 0x07, 0x04, 0x01, 0x5C, 0x27, 0x1C, 0x06, 0x7C,
+	0x7A, 0x58, 0x16, 0xB0, 0xBA, 0x88, 0x22, 0xEB, 0xD2, 0x9B, 0x29, 0xFF, 0xDD, 0xA7, 0x2E, 0xFF,
+	0xE5, 0xB0, 0x32, 0xFF, 0xE9, 0xB6, 0x36, 0xFF, 0xEC, 0xBA, 0x38, 0xFF, 0xED, 0xBA, 0x39, 0xFF,
+	0xED, 0xBB, 0x3A, 0xFF, 0xED, 0xBC, 0x3C, 0xFF, 0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBE, 0x40, 0xFF,
+	0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xC1, 0x47, 0xFF, 0xEE, 0xC2, 0x49, 0xFF,
+	0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC5, 0x52, 0xFF,
+	0xEF, 0xC5, 0x55, 0xFF, 0xF0, 0xC6, 0x57, 0xFF, 0xF0, 0xC6, 0x59, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF,
+	0xF0, 0xC7, 0x5D, 0xFF, 0xF1, 0xC8, 0x5F, 0xFF, 0xF1, 0xC9, 0x60, 0xFF, 0xF1, 0xCA, 0x62, 0xFF,
+	0xF1, 0xCB, 0x64, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCC, 0x68, 0xFF, 0xF2, 0xCC, 0x69, 0xFF,
+	0xF2, 0xCD, 0x6B, 0xFF, 0xF1, 0xCD, 0x6C, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF,
+	0xF2, 0xCE, 0x70, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xCF, 0x73, 0xFF,
+	0xF3, 0xCF, 0x74, 0xFF, 0xF3, 0xCF, 0x74, 0xFF, 0xF3, 0xD0, 0x75, 0xFF, 0xF3, 0xD0, 0x76, 0xFF,
+	0xF3, 0xD0, 0x76, 0xFF, 0xF3, 0xD0, 0x76, 0xFF, 0xF2, 0xD1, 0x76, 0xFF, 0xF3, 0xD1, 0x76, 0xFF,
+	0xF3, 0xD1, 0x76, 0xFF, 0xF3, 0xD0, 0x76, 0xFF, 0xF3, 0xD0, 0x75, 0xFF, 0xF3, 0xD0, 0x75, 0xFF,
+	0xF3, 0xD0, 0x75, 0xFF, 0xF2, 0xCF, 0x74, 0xFF, 0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xCF, 0x72, 0xFF,
+	0xF2, 0xCE, 0x71, 0xFF, 0xF2, 0xCE, 0x70, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF1, 0xCE, 0x6E, 0xFF,
+	0xF2, 0xCD, 0x6D, 0xFF, 0xF2, 0xCD, 0x6B, 0xFF, 0xF1, 0xCC, 0x6A, 0xFF, 0xF1, 0xCC, 0x68, 0xFF,
+	0xF1, 0xCC, 0x66, 0xFF, 0xF1, 0xCB, 0x64, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xC9, 0x61, 0xFF,
+	0xF0, 0xC9, 0x5F, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC6, 0x59, 0xFF,
+	0xF0, 0xC6, 0x57, 0xFF, 0xF0, 0xC5, 0x56, 0xFF, 0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC4, 0x51, 0xFF,
+	0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4C, 0xFF, 0xEF, 0xC2, 0x4A, 0xFF, 0xEE, 0xC1, 0x48, 0xFF,
+	0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xBF, 0x43, 0xFF, 0xEE, 0xBE, 0x40, 0xFF, 0xED, 0xBD, 0x3E, 0xFF,
+	0xED, 0xBC, 0x3B, 0xFF, 0xED, 0xBB, 0x3A, 0xFF, 0xEC, 0xBA, 0x39, 0xFF, 0xEC, 0xBA, 0x38, 0xFF,
+	0xED, 0xBB, 0x39, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xE3, 0xAD, 0x30, 0xFF, 0xD7, 0xA0, 0x2A, 0xFE,
+	0xC2, 0x8F, 0x24, 0xF5, 0xA5, 0x78, 0x1E, 0xD9, 0x61, 0x47, 0x11, 0x9A, 0x00, 0x00, 0x00, 0x60,
+	0x00, 0x00, 0x00, 0x46, 0x00, 0x00, 0x00, 0x36, 0x02, 0x01, 0x00, 0x21, 0x00, 0x00, 0x00, 0x0F,
+	0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x13,
+	0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x39, 0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x60,
+	0x5B, 0x43, 0x11, 0x97, 0xA6, 0x7A, 0x20, 0xD9, 0xC2, 0x8F, 0x25, 0xF8, 0xD4, 0x9D, 0x2A, 0xFD,
+	0xE0, 0xAA, 0x2F, 0xFF, 0xE9, 0xB5, 0x35, 0xFF, 0xED, 0xBC, 0x39, 0xFF, 0xED, 0xBB, 0x39, 0xFF,
+	0xED, 0xBB, 0x3B, 0xFF, 0xED, 0xBC, 0x3D, 0xFF, 0xED, 0xBD, 0x3F, 0xFF, 0xEE, 0xBE, 0x42, 0xFF,
+	0xEE, 0xBF, 0x44, 0xFF, 0xEE, 0xC1, 0x46, 0xFF, 0xEE, 0xC2, 0x49, 0xFF, 0xEE, 0xC3, 0x4B, 0xFF,
+	0xEF, 0xC3, 0x4D, 0xFF, 0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC5, 0x52, 0xFF, 0xEF, 0xC6, 0x55, 0xFF,
+	0xF0, 0xC7, 0x57, 0xFF, 0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC7, 0x5D, 0xFF,
+	0xF1, 0xC8, 0x5F, 0xFF, 0xF1, 0xC9, 0x61, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xCB, 0x64, 0xFF,
+	0xF1, 0xCC, 0x67, 0xFF, 0xF1, 0xCC, 0x69, 0xFF, 0xF1, 0xCC, 0x6B, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF,
+	0xF2, 0xCD, 0x6D, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCE, 0x70, 0xFF, 0xF2, 0xCF, 0x72, 0xFF,
+	0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xD0, 0x74, 0xFF, 0xF2, 0xD0, 0x74, 0xFF, 0xF3, 0xD0, 0x75, 0xFF,
+	0xF3, 0xD0, 0x76, 0xFF, 0xF3, 0xD1, 0x77, 0xFF, 0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD1, 0x79, 0xFF,
+	0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD2, 0x79, 0xFF, 0xF3, 0xD2, 0x79, 0xFF, 0xF3, 0xD2, 0x79, 0xFF,
+	0xF3, 0xD2, 0x79, 0xFF, 0xF3, 0xD2, 0x79, 0xFF, 0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD1, 0x79, 0xFF,
+	0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD1, 0x77, 0xFF, 0xF2, 0xD0, 0x76, 0xFF, 0xF2, 0xD0, 0x74, 0xFF,
+	0xF2, 0xCF, 0x74, 0xFF, 0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xCF, 0x71, 0xFF,
+	0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF, 0xF1, 0xCD, 0x6D, 0xFF, 0xF1, 0xCD, 0x6B, 0xFF,
+	0xF1, 0xCD, 0x69, 0xFF, 0xF1, 0xCC, 0x67, 0xFF, 0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCA, 0x64, 0xFF,
+	0xF1, 0xC9, 0x62, 0xFF, 0xF0, 0xC8, 0x60, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF,
+	0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC6, 0x58, 0xFF, 0xF0, 0xC6, 0x56, 0xFF, 0xEF, 0xC5, 0x53, 0xFF,
+	0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC3, 0x4C, 0xFF, 0xEE, 0xC2, 0x4A, 0xFF,
+	0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEE, 0xBE, 0x42, 0xFF, 0xEE, 0xBE, 0x40, 0xFF,
+	0xED, 0xBD, 0x3D, 0xFF, 0xED, 0xBC, 0x3B, 0xFF, 0xEC, 0xBB, 0x39, 0xFF, 0xEC, 0xBB, 0x39, 0xFF,
+	0xED, 0xBC, 0x39, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xE2, 0xAA, 0x2F, 0xFF, 0xD0, 0x9A, 0x28, 0xFA,
+	0xAB, 0x7D, 0x1F, 0xE0, 0x81, 0x5E, 0x16, 0xBC, 0x48, 0x34, 0x0C, 0x87, 0x00, 0x00, 0x00, 0x58,
+	0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x0B,
+	0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x0D,
+	0x03, 0x02, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x2F, 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x55,
+	0x3B, 0x2B, 0x0B, 0x83, 0x7F, 0x5D, 0x18, 0xBB, 0xAA, 0x7D, 0x20, 0xE1, 0xD0, 0x99, 0x28, 0xFA,
+	0xE3, 0xAB, 0x2F, 0xFF, 0xEA, 0xB6, 0x36, 0xFF, 0xEE, 0xBC, 0x3A, 0xFF, 0xEE, 0xBC, 0x3B, 0xFF,
+	0xED, 0xBC, 0x3C, 0xFF, 0xED, 0xBD, 0x3E, 0xFF, 0xED, 0xBE, 0x41, 0xFF, 0xEE, 0xBF, 0x43, 0xFF,
+	0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xC1, 0x49, 0xFF, 0xEE, 0xC2, 0x4B, 0xFF, 0xEF, 0xC3, 0x4D, 0xFF,
+	0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC5, 0x55, 0xFF, 0xF0, 0xC6, 0x57, 0xFF,
+	0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC8, 0x5B, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF1, 0xC8, 0x5F, 0xFF,
+	0xF1, 0xC9, 0x62, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCC, 0x67, 0xFF,
+	0xF1, 0xCC, 0x69, 0xFF, 0xF1, 0xCD, 0x6B, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF,
+	0xF2, 0xCF, 0x70, 0xFF, 0xF2, 0xCF, 0x72, 0xFF, 0xF3, 0xD0, 0x73, 0xFF, 0xF2, 0xD0, 0x75, 0xFF,
+	0xF2, 0xD0, 0x76, 0xFF, 0xF2, 0xD1, 0x77, 0xFF, 0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD1, 0x79, 0xFF,
+	0xF3, 0xD2, 0x79, 0xFF, 0xF3, 0xD2, 0x7A, 0xFF, 0xF3, 0xD3, 0x7B, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF,
+	0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD3, 0x7C, 0xFF, 0xF4, 0xD3, 0x7C, 0xFF, 0xF3, 0xD3, 0x7C, 0xFF,
+	0xF3, 0xD3, 0x7C, 0xFF, 0xF3, 0xD3, 0x7C, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF,
+	0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD2, 0x7A, 0xFF, 0xF3, 0xD2, 0x79, 0xFF, 0xF2, 0xD1, 0x78, 0xFF,
+	0xF2, 0xD1, 0x77, 0xFF, 0xF2, 0xD0, 0x76, 0xFF, 0xF3, 0xD0, 0x75, 0xFF, 0xF2, 0xCF, 0x73, 0xFF,
+	0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF1, 0xCD, 0x6D, 0xFF,
+	0xF1, 0xCD, 0x6C, 0xFF, 0xF1, 0xCD, 0x6A, 0xFF, 0xF1, 0xCC, 0x68, 0xFF, 0xF1, 0xCB, 0x66, 0xFF,
+	0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xC9, 0x62, 0xFF, 0xF0, 0xC9, 0x60, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF,
+	0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC6, 0x58, 0xFF, 0xF0, 0xC5, 0x55, 0xFF,
+	0xEF, 0xC4, 0x53, 0xFF, 0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF,
+	0xEE, 0xC1, 0x4A, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xBF, 0x44, 0xFF, 0xEE, 0xBE, 0x41, 0xFF,
+	0xEE, 0xBE, 0x3E, 0xFF, 0xED, 0xBD, 0x3C, 0xFF, 0xED, 0xBD, 0x3B, 0xFF, 0xEC, 0xBB, 0x39, 0xFF,
+	0xEA, 0xB8, 0x37, 0xFF, 0xE4, 0xB0, 0x33, 0xFF, 0xDD, 0xA5, 0x2D, 0xFF, 0xC8, 0x93, 0x26, 0xF5,
+	0x8E, 0x68, 0x1A, 0xC5, 0x4A, 0x36, 0x0D, 0x95, 0x1F, 0x16, 0x05, 0x6F, 0x00, 0x00, 0x00, 0x4E,
+	0x00, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x08,
+	0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x50,
+	0x1C, 0x14, 0x05, 0x71, 0x47, 0x33, 0x0C, 0x98, 0x8A, 0x65, 0x19, 0xC4, 0xCA, 0x95, 0x26, 0xF3,
+	0xE4, 0xAB, 0x2E, 0xFF, 0xEB, 0xB6, 0x35, 0xFF, 0xEE, 0xBC, 0x3A, 0xFF, 0xED, 0xBD, 0x3C, 0xFF,
+	0xED, 0xBD, 0x3D, 0xFF, 0xEE, 0xBE, 0x40, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xC0, 0x45, 0xFF,
+	0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC1, 0x4B, 0xFF, 0xEF, 0xC2, 0x4D, 0xFF, 0xEF, 0xC3, 0x50, 0xFF,
+	0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC5, 0x54, 0xFF, 0xF0, 0xC6, 0x57, 0xFF, 0xF0, 0xC7, 0x59, 0xFF,
+	0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF1, 0xC9, 0x5F, 0xFF, 0xF1, 0xC9, 0x61, 0xFF,
+	0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCB, 0x68, 0xFF, 0xF1, 0xCC, 0x6A, 0xFF,
+	0xF1, 0xCD, 0x6C, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCF, 0x71, 0xFF,
+	0xF2, 0xD0, 0x73, 0xFF, 0xF3, 0xD1, 0x75, 0xFF, 0xF3, 0xD1, 0x77, 0xFF, 0xF3, 0xD1, 0x78, 0xFF,
+	0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD2, 0x7A, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF,
+	0xF3, 0xD3, 0x7D, 0xFF, 0xF3, 0xD4, 0x7D, 0xFF, 0xF3, 0xD4, 0x7E, 0xFF, 0xF3, 0xD4, 0x7E, 0xFF,
+	0xF3, 0xD4, 0x7E, 0xFF, 0xF4, 0xD4, 0x7F, 0xFF, 0xF4, 0xD4, 0x7F, 0xFF, 0xF4, 0xD4, 0x7F, 0xFF,
+	0xF3, 0xD4, 0x7F, 0xFF, 0xF3, 0xD4, 0x7F, 0xFF, 0xF3, 0xD4, 0x7F, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF,
+	0xF3, 0xD3, 0x7E, 0xFF, 0xF3, 0xD3, 0x7D, 0xFF, 0xF3, 0xD3, 0x7C, 0xFF, 0xF3, 0xD3, 0x7B, 0xFF,
+	0xF3, 0xD2, 0x7A, 0xFF, 0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD0, 0x78, 0xFF, 0xF3, 0xD0, 0x76, 0xFF,
+	0xF2, 0xD0, 0x75, 0xFF, 0xF2, 0xD0, 0x73, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xCE, 0x70, 0xFF,
+	0xF2, 0xCD, 0x6E, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF, 0xF2, 0xCD, 0x6B, 0xFF, 0xF1, 0xCC, 0x69, 0xFF,
+	0xF1, 0xCB, 0x67, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xC9, 0x62, 0xFF, 0xF0, 0xC9, 0x61, 0xFF,
+	0xF0, 0xC8, 0x5F, 0xFF, 0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC6, 0x57, 0xFF,
+	0xF0, 0xC5, 0x55, 0xFF, 0xEF, 0xC4, 0x53, 0xFF, 0xEF, 0xC4, 0x50, 0xFF, 0xEF, 0xC2, 0x4E, 0xFF,
+	0xEF, 0xC1, 0x4B, 0xFF, 0xEF, 0xC0, 0x48, 0xFF, 0xEE, 0xC0, 0x46, 0xFF, 0xEE, 0xBF, 0x43, 0xFF,
+	0xEE, 0xBE, 0x40, 0xFF, 0xEE, 0xBE, 0x3E, 0xFF, 0xEE, 0xBE, 0x3C, 0xFF, 0xEB, 0xBA, 0x39, 0xFF,
+	0xE5, 0xB1, 0x34, 0xFF, 0xDD, 0xA8, 0x2F, 0xFF, 0xD4, 0x9E, 0x2A, 0xFF, 0xBA, 0x89, 0x23, 0xEA,
+	0x6A, 0x4E, 0x14, 0xA7, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x57, 0x00, 0x00, 0x00, 0x45,
+	0x00, 0x00, 0x00, 0x2E, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x05,
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x05,
+	0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x1D, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x46,
+	0x02, 0x01, 0x00, 0x5F, 0x19, 0x11, 0x04, 0x7B, 0x6F, 0x51, 0x14, 0xAB, 0xBC, 0x8B, 0x23, 0xE7,
+	0xD9, 0xA2, 0x2B, 0xFF, 0xE3, 0xAE, 0x31, 0xFF, 0xEA, 0xB7, 0x37, 0xFF, 0xED, 0xBC, 0x3C, 0xFF,
+	0xEE, 0xBF, 0x40, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xC0, 0x44, 0xFF, 0xEE, 0xC1, 0x47, 0xFF,
+	0xEE, 0xC1, 0x4A, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF, 0xEF, 0xC3, 0x52, 0xFF,
+	0xEF, 0xC4, 0x54, 0xFF, 0xEF, 0xC5, 0x56, 0xFF, 0xF0, 0xC6, 0x59, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF,
+	0xF0, 0xC8, 0x5D, 0xFF, 0xF1, 0xC9, 0x60, 0xFF, 0xF1, 0xC9, 0x62, 0xFF, 0xF1, 0xCA, 0x64, 0xFF,
+	0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCC, 0x68, 0xFF, 0xF1, 0xCC, 0x6A, 0xFF, 0xF1, 0xCD, 0x6C, 0xFF,
+	0xF2, 0xCE, 0x6E, 0xFF, 0xF2, 0xCF, 0x70, 0xFF, 0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xD0, 0x74, 0xFF,
+	0xF3, 0xD0, 0x76, 0xFF, 0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD2, 0x79, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF,
+	0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD2, 0x7D, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF, 0xF3, 0xD4, 0x7F, 0xFF,
+	0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD4, 0x81, 0xFF, 0xF3, 0xD5, 0x81, 0xFF,
+	0xF3, 0xD5, 0x82, 0xFF, 0xF4, 0xD5, 0x82, 0xFF, 0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD5, 0x83, 0xFF,
+	0xF3, 0xD5, 0x83, 0xFF, 0xF3, 0xD5, 0x82, 0xFF, 0xF3, 0xD4, 0x82, 0xFF, 0xF3, 0xD4, 0x81, 0xFF,
+	0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD4, 0x7F, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF,
+	0xF3, 0xD3, 0x7D, 0xFF, 0xF3, 0xD3, 0x7C, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD1, 0x79, 0xFF,
+	0xF3, 0xD1, 0x78, 0xFF, 0xF2, 0xD1, 0x76, 0xFF, 0xF2, 0xD0, 0x74, 0xFF, 0xF2, 0xCF, 0x72, 0xFF,
+	0xF2, 0xCE, 0x71, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF, 0xF1, 0xCD, 0x6B, 0xFF,
+	0xF1, 0xCC, 0x69, 0xFF, 0xF1, 0xCB, 0x67, 0xFF, 0xF1, 0xCA, 0x65, 0xFF, 0xF0, 0xCA, 0x63, 0xFF,
+	0xF0, 0xC9, 0x60, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC7, 0x5C, 0xFF, 0xF0, 0xC6, 0x59, 0xFF,
+	0xF0, 0xC6, 0x57, 0xFF, 0xEF, 0xC5, 0x55, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC3, 0x4F, 0xFF,
+	0xEF, 0xC2, 0x4C, 0xFF, 0xEF, 0xC1, 0x4A, 0xFF, 0xEE, 0xC1, 0x48, 0xFF, 0xEE, 0xC0, 0x45, 0xFF,
+	0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xBF, 0x40, 0xFF, 0xEE, 0xBF, 0x3E, 0xFF, 0xEB, 0xBA, 0x39, 0xFF,
+	0xE5, 0xAF, 0x33, 0xFF, 0xD8, 0xA2, 0x2C, 0xFD, 0xC1, 0x8F, 0x25, 0xF3, 0x9E, 0x74, 0x1D, 0xD2,
+	0x4D, 0x38, 0x0E, 0x92, 0x00, 0x00, 0x00, 0x5E, 0x00, 0x00, 0x00, 0x49, 0x01, 0x00, 0x00, 0x3A,
+	0x03, 0x02, 0x01, 0x25, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x3B,
+	0x00, 0x00, 0x00, 0x4D, 0x00, 0x00, 0x00, 0x63, 0x55, 0x3E, 0x0F, 0x94, 0xA5, 0x7A, 0x1E, 0xD6,
+	0xC5, 0x93, 0x26, 0xF9, 0xD7, 0xA2, 0x2C, 0xFE, 0xE3, 0xAF, 0x33, 0xFF, 0xEB, 0xBA, 0x3B, 0xFF,
+	0xEF, 0xC0, 0x42, 0xFF, 0xEF, 0xC0, 0x44, 0xFF, 0xEE, 0xC0, 0x47, 0xFF, 0xEE, 0xC1, 0x49, 0xFF,
+	0xEF, 0xC2, 0x4B, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC4, 0x51, 0xFF, 0xEF, 0xC5, 0x53, 0xFF,
+	0xEF, 0xC6, 0x56, 0xFF, 0xEF, 0xC6, 0x58, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC7, 0x5D, 0xFF,
+	0xF1, 0xC8, 0x5F, 0xFF, 0xF1, 0xC9, 0x62, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xCB, 0x67, 0xFF,
+	0xF1, 0xCB, 0x69, 0xFF, 0xF1, 0xCC, 0x6B, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF,
+	0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xD0, 0x73, 0xFF, 0xF2, 0xD0, 0x75, 0xFF, 0xF3, 0xD1, 0x77, 0xFF,
+	0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD2, 0x7D, 0xFF,
+	0xF3, 0xD3, 0x7F, 0xFF, 0xF3, 0xD3, 0x7F, 0xFF, 0xF3, 0xD4, 0x81, 0xFF, 0xF4, 0xD4, 0x82, 0xFF,
+	0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD5, 0x84, 0xFF, 0xF4, 0xD5, 0x85, 0xFF,
+	0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD6, 0x86, 0xFF,
+	0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD5, 0x85, 0xFF, 0xF4, 0xD5, 0x85, 0xFF, 0xF4, 0xD5, 0x84, 0xFF,
+	0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD4, 0x83, 0xFF, 0xF3, 0xD4, 0x82, 0xFF, 0xF3, 0xD4, 0x81, 0xFF,
+	0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD4, 0x7F, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF,
+	0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD2, 0x79, 0xFF, 0xF3, 0xD1, 0x77, 0xFF, 0xF3, 0xD0, 0x75, 0xFF,
+	0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF,
+	0xF2, 0xCC, 0x6B, 0xFF, 0xF1, 0xCC, 0x6A, 0xFF, 0xF1, 0xCB, 0x68, 0xFF, 0xF1, 0xCA, 0x65, 0xFF,
+	0xF1, 0xC9, 0x62, 0xFF, 0xF0, 0xC8, 0x60, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC7, 0x5B, 0xFF,
+	0xF0, 0xC7, 0x59, 0xFF, 0xEF, 0xC6, 0x56, 0xFF, 0xEF, 0xC5, 0x54, 0xFF, 0xEF, 0xC4, 0x51, 0xFF,
+	0xEF, 0xC3, 0x4E, 0xFF, 0xEF, 0xC2, 0x4C, 0xFF, 0xEE, 0xC2, 0x4A, 0xFF, 0xEE, 0xC1, 0x47, 0xFF,
+	0xEE, 0xBF, 0x44, 0xFF, 0xEE, 0xBF, 0x42, 0xFF, 0xEE, 0xBF, 0x40, 0xFF, 0xEB, 0xB9, 0x3A, 0xFF,
+	0xE5, 0xAE, 0x32, 0xFF, 0xD1, 0x9B, 0x29, 0xF8, 0xA3, 0x78, 0x1E, 0xD8, 0x71, 0x53, 0x13, 0xB1,
+	0x35, 0x27, 0x09, 0x80, 0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, 0x2F,
+	0x01, 0x01, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x0E, 0x02, 0x01, 0x00, 0x1D, 0x01, 0x01, 0x00, 0x30,
+	0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x53, 0x34, 0x26, 0x09, 0x7D, 0x7C, 0x5B, 0x17, 0xB6,
+	0xA7, 0x7C, 0x20, 0xDE, 0xCD, 0x99, 0x28, 0xF7, 0xE1, 0xAB, 0x30, 0xFF, 0xE8, 0xB6, 0x39, 0xFF,
+	0xED, 0xBD, 0x40, 0xFF, 0xEE, 0xC0, 0x45, 0xFF, 0xEF, 0xC1, 0x49, 0xFF, 0xEF, 0xC2, 0x4B, 0xFF,
+	0xEF, 0xC3, 0x4D, 0xFF, 0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC4, 0x53, 0xFF, 0xEF, 0xC5, 0x55, 0xFF,
+	0xEF, 0xC6, 0x58, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC7, 0x5D, 0xFF, 0xF1, 0xC8, 0x5F, 0xFF,
+	0xF1, 0xC9, 0x61, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xCB, 0x67, 0xFF, 0xF1, 0xCC, 0x69, 0xFF,
+	0xF1, 0xCC, 0x6B, 0xFF, 0xF1, 0xCD, 0x6D, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCF, 0x71, 0xFF,
+	0xF2, 0xD0, 0x73, 0xFF, 0xF2, 0xD0, 0x75, 0xFF, 0xF3, 0xD1, 0x77, 0xFF, 0xF3, 0xD1, 0x79, 0xFF,
+	0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD2, 0x7D, 0xFF, 0xF3, 0xD3, 0x7F, 0xFF, 0xF3, 0xD4, 0x80, 0xFF,
+	0xF3, 0xD4, 0x81, 0xFF, 0xF3, 0xD4, 0x82, 0xFF, 0xF3, 0xD5, 0x83, 0xFF, 0xF4, 0xD5, 0x85, 0xFF,
+	0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD6, 0x87, 0xFF, 0xF4, 0xD6, 0x87, 0xFF, 0xF4, 0xD6, 0x88, 0xFF,
+	0xF4, 0xD7, 0x89, 0xFF, 0xF4, 0xD7, 0x89, 0xFF, 0xF4, 0xD7, 0x89, 0xFF, 0xF4, 0xD7, 0x89, 0xFF,
+	0xF4, 0xD7, 0x89, 0xFF, 0xF4, 0xD6, 0x88, 0xFF, 0xF4, 0xD6, 0x88, 0xFF, 0xF4, 0xD6, 0x87, 0xFF,
+	0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD6, 0x85, 0xFF, 0xF3, 0xD5, 0x85, 0xFF, 0xF3, 0xD5, 0x84, 0xFF,
+	0xF3, 0xD5, 0x83, 0xFF, 0xF3, 0xD4, 0x81, 0xFF, 0xF3, 0xD4, 0x81, 0xFF, 0xF3, 0xD4, 0x7F, 0xFF,
+	0xF3, 0xD3, 0x7D, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD1, 0x7A, 0xFF, 0xF3, 0xD1, 0x78, 0xFF,
+	0xF3, 0xD0, 0x76, 0xFF, 0xF2, 0xD0, 0x74, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF,
+	0xF2, 0xCD, 0x6D, 0xFF, 0xF1, 0xCD, 0x6C, 0xFF, 0xF1, 0xCC, 0x6A, 0xFF, 0xF1, 0xCB, 0x67, 0xFF,
+	0xF1, 0xCA, 0x64, 0xFF, 0xF0, 0xC9, 0x62, 0xFF, 0xF0, 0xC8, 0x60, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF,
+	0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC6, 0x58, 0xFF, 0xEF, 0xC5, 0x56, 0xFF, 0xEF, 0xC4, 0x53, 0xFF,
+	0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC3, 0x4E, 0xFF, 0xEE, 0xC2, 0x4B, 0xFF, 0xEF, 0xC2, 0x49, 0xFF,
+	0xEF, 0xC1, 0x47, 0xFF, 0xED, 0xBE, 0x42, 0xFF, 0xEA, 0xB9, 0x3C, 0xFF, 0xE3, 0xB0, 0x35, 0xFF,
+	0xDA, 0xA3, 0x2E, 0xFF, 0xC0, 0x8D, 0x25, 0xEB, 0x82, 0x60, 0x18, 0xBC, 0x41, 0x30, 0x0A, 0x91,
+	0x1A, 0x13, 0x04, 0x6D, 0x00, 0x00, 0x00, 0x4E, 0x00, 0x00, 0x00, 0x37, 0x00, 0x00, 0x00, 0x25,
+	0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x00, 0x14, 0x00, 0x00, 0x00, 0x25,
+	0x00, 0x00, 0x00, 0x37, 0x00, 0x00, 0x00, 0x4C, 0x0A, 0x07, 0x02, 0x67, 0x28, 0x1E, 0x08, 0x89,
+	0x72, 0x55, 0x16, 0xB5, 0xC2, 0x91, 0x26, 0xED, 0xE2, 0xAA, 0x2F, 0xFF, 0xE4, 0xB0, 0x35, 0xFF,
+	0xE7, 0xB6, 0x3C, 0xFF, 0xEC, 0xBE, 0x45, 0xFF, 0xF0, 0xC3, 0x4B, 0xFF, 0xF0, 0xC4, 0x4D, 0xFF,
+	0xEF, 0xC4, 0x4F, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xF0, 0xC5, 0x55, 0xFF, 0xF0, 0xC5, 0x57, 0xFF,
+	0xF0, 0xC6, 0x59, 0xFF, 0xF0, 0xC7, 0x5C, 0xFF, 0xF1, 0xC8, 0x5F, 0xFF, 0xF1, 0xC9, 0x61, 0xFF,
+	0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCB, 0x69, 0xFF, 0xF1, 0xCC, 0x6B, 0xFF,
+	0xF1, 0xCD, 0x6D, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xD0, 0x73, 0xFF,
+	0xF2, 0xD0, 0x75, 0xFF, 0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD2, 0x7A, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF,
+	0xF3, 0xD3, 0x7E, 0xFF, 0xF4, 0xD3, 0x80, 0xFF, 0xF4, 0xD4, 0x82, 0xFF, 0xF4, 0xD5, 0x83, 0xFF,
+	0xF4, 0xD5, 0x84, 0xFF, 0xF4, 0xD5, 0x85, 0xFF, 0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD6, 0x88, 0xFF,
+	0xF4, 0xD7, 0x89, 0xFF, 0xF5, 0xD7, 0x8A, 0xFF, 0xF5, 0xD7, 0x8A, 0xFF, 0xF5, 0xD7, 0x8B, 0xFF,
+	0xF5, 0xD7, 0x8B, 0xFF, 0xF5, 0xD8, 0x8C, 0xFF, 0xF5, 0xD8, 0x8C, 0xFF, 0xF5, 0xD8, 0x8C, 0xFF,
+	0xF5, 0xD7, 0x8B, 0xFF, 0xF5, 0xD7, 0x8B, 0xFF, 0xF5, 0xD7, 0x8B, 0xFF, 0xF5, 0xD7, 0x8B, 0xFF,
+	0xF4, 0xD7, 0x89, 0xFF, 0xF4, 0xD7, 0x89, 0xFF, 0xF4, 0xD6, 0x88, 0xFF, 0xF4, 0xD6, 0x87, 0xFF,
+	0xF4, 0xD6, 0x85, 0xFF, 0xF4, 0xD5, 0x84, 0xFF, 0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD4, 0x82, 0xFF,
+	0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD1, 0x7A, 0xFF,
+	0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD1, 0x76, 0xFF, 0xF2, 0xD0, 0x74, 0xFF, 0xF2, 0xCF, 0x72, 0xFF,
+	0xF2, 0xCE, 0x70, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF, 0xF2, 0xCC, 0x6B, 0xFF, 0xF1, 0xCC, 0x69, 0xFF,
+	0xF1, 0xCB, 0x67, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xC9, 0x62, 0xFF, 0xF0, 0xC8, 0x5F, 0xFF,
+	0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF, 0xF0, 0xC6, 0x58, 0xFF, 0xEF, 0xC5, 0x55, 0xFF,
+	0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC2, 0x4D, 0xFF, 0xF0, 0xC3, 0x4C, 0xFF,
+	0xF0, 0xC3, 0x49, 0xFF, 0xEB, 0xBC, 0x41, 0xFF, 0xE3, 0xAE, 0x34, 0xFF, 0xD6, 0xA0, 0x2C, 0xFE,
+	0xC3, 0x91, 0x27, 0xF7, 0xA3, 0x78, 0x20, 0xD9, 0x5A, 0x42, 0x11, 0x9E, 0x0A, 0x07, 0x01, 0x71,
+	0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x00, 0x43, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x00, 0x00, 0x1B,
+	0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x1B,
+	0x00, 0x00, 0x00, 0x2D, 0x00, 0x00, 0x00, 0x42, 0x00, 0x00, 0x00, 0x55, 0x00, 0x00, 0x00, 0x6A,
+	0x3D, 0x2E, 0x0D, 0x94, 0xA3, 0x79, 0x20, 0xD3, 0xCB, 0x98, 0x2A, 0xF7, 0xD9, 0xA5, 0x30, 0xFF,
+	0xE2, 0xB0, 0x38, 0xFF, 0xEA, 0xBA, 0x42, 0xFF, 0xEE, 0xC1, 0x4A, 0xFF, 0xEF, 0xC4, 0x4E, 0xFF,
+	0xEF, 0xC4, 0x51, 0xFF, 0xF0, 0xC5, 0x54, 0xFF, 0xF0, 0xC5, 0x56, 0xFF, 0xF0, 0xC6, 0x59, 0xFF,
+	0xF0, 0xC7, 0x5B, 0xFF, 0xF0, 0xC8, 0x5E, 0xFF, 0xF1, 0xC9, 0x61, 0xFF, 0xF1, 0xCA, 0x63, 0xFF,
+	0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCC, 0x68, 0xFF, 0xF1, 0xCC, 0x6A, 0xFF, 0xF1, 0xCD, 0x6D, 0xFF,
+	0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xD0, 0x73, 0xFF, 0xF2, 0xD0, 0x75, 0xFF,
+	0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD1, 0x7A, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF,
+	0xF4, 0xD4, 0x80, 0xFF, 0xF4, 0xD4, 0x83, 0xFF, 0xF4, 0xD5, 0x84, 0xFF, 0xF4, 0xD6, 0x86, 0xFF,
+	0xF4, 0xD6, 0x87, 0xFF, 0xF4, 0xD6, 0x88, 0xFF, 0xF4, 0xD7, 0x89, 0xFF, 0xF4, 0xD7, 0x8A, 0xFF,
+	0xF4, 0xD8, 0x8C, 0xFF, 0xF5, 0xD8, 0x8D, 0xFF, 0xF5, 0xD8, 0x8D, 0xFF, 0xF5, 0xD8, 0x8E, 0xFF,
+	0xF5, 0xD8, 0x8E, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF,
+	0xF5, 0xD9, 0x8E, 0xFF, 0xF5, 0xD8, 0x8E, 0xFF, 0xF5, 0xD8, 0x8E, 0xFF, 0xF5, 0xD8, 0x8E, 0xFF,
+	0xF4, 0xD8, 0x8D, 0xFF, 0xF4, 0xD8, 0x8C, 0xFF, 0xF4, 0xD8, 0x8B, 0xFF, 0xF4, 0xD7, 0x89, 0xFF,
+	0xF4, 0xD7, 0x88, 0xFF, 0xF4, 0xD6, 0x87, 0xFF, 0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD5, 0x84, 0xFF,
+	0xF4, 0xD5, 0x83, 0xFF, 0xF3, 0xD4, 0x81, 0xFF, 0xF3, 0xD3, 0x7F, 0xFF, 0xF3, 0xD2, 0x7D, 0xFF,
+	0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD1, 0x76, 0xFF, 0xF2, 0xD0, 0x75, 0xFF,
+	0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF, 0xF1, 0xCD, 0x6B, 0xFF,
+	0xF1, 0xCC, 0x69, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCA, 0x64, 0xFF, 0xF0, 0xC9, 0x61, 0xFF,
+	0xF0, 0xC8, 0x5E, 0xFF, 0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC6, 0x56, 0xFF,
+	0xEF, 0xC4, 0x54, 0xFF, 0xEF, 0xC4, 0x52, 0xFF, 0xEF, 0xC3, 0x50, 0xFF, 0xEF, 0xC3, 0x4C, 0xFF,
+	0xEE, 0xC1, 0x47, 0xFF, 0xE8, 0xB7, 0x3D, 0xFF, 0xDE, 0xA7, 0x2F, 0xFF, 0xC8, 0x94, 0x26, 0xF7,
+	0xA4, 0x79, 0x20, 0xE1, 0x7A, 0x5A, 0x18, 0xBB, 0x30, 0x24, 0x0A, 0x84, 0x00, 0x00, 0x00, 0x5B,
+	0x00, 0x00, 0x00, 0x48, 0x01, 0x01, 0x00, 0x37, 0x02, 0x01, 0x00, 0x23, 0x00, 0x00, 0x00, 0x13,
+	0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x13,
+	0x01, 0x01, 0x00, 0x23, 0x01, 0x01, 0x00, 0x36, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x5C,
+	0x17, 0x11, 0x05, 0x7C, 0x51, 0x3D, 0x0F, 0xA5, 0x88, 0x66, 0x1B, 0xCC, 0xC3, 0x93, 0x28, 0xF2,
+	0xE2, 0xAC, 0x32, 0xFF, 0xE8, 0xB5, 0x3D, 0xFF, 0xEA, 0xBB, 0x46, 0xFF, 0xED, 0xC1, 0x4D, 0xFF,
+	0xEF, 0xC5, 0x53, 0xFF, 0xF0, 0xC6, 0x55, 0xFF, 0xF0, 0xC6, 0x57, 0xFF, 0xF0, 0xC7, 0x5A, 0xFF,
+	0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC9, 0x60, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCB, 0x64, 0xFF,
+	0xF2, 0xCB, 0x67, 0xFF, 0xF2, 0xCC, 0x69, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF,
+	0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xD0, 0x73, 0xFF, 0xF2, 0xD0, 0x76, 0xFF, 0xF3, 0xD1, 0x78, 0xFF,
+	0xF3, 0xD1, 0x7A, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF, 0xF4, 0xD4, 0x81, 0xFF,
+	0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD5, 0x85, 0xFF, 0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD6, 0x88, 0xFF,
+	0xF4, 0xD7, 0x89, 0xFF, 0xF5, 0xD8, 0x8A, 0xFF, 0xF5, 0xD8, 0x8B, 0xFF, 0xF5, 0xD9, 0x8D, 0xFF,
+	0xF5, 0xD9, 0x8E, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF, 0xF5, 0xD9, 0x90, 0xFF, 0xF5, 0xD9, 0x91, 0xFF,
+	0xF5, 0xD9, 0x92, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xDA, 0x92, 0xFF,
+	0xF5, 0xDA, 0x91, 0xFF, 0xF5, 0xDA, 0x91, 0xFF, 0xF5, 0xD9, 0x91, 0xFF, 0xF5, 0xD9, 0x91, 0xFF,
+	0xF5, 0xD9, 0x90, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF, 0xF5, 0xD9, 0x8D, 0xFF, 0xF5, 0xD8, 0x8C, 0xFF,
+	0xF5, 0xD8, 0x8B, 0xFF, 0xF5, 0xD7, 0x89, 0xFF, 0xF4, 0xD7, 0x88, 0xFF, 0xF4, 0xD6, 0x86, 0xFF,
+	0xF4, 0xD6, 0x85, 0xFF, 0xF4, 0xD5, 0x83, 0xFF, 0xF3, 0xD4, 0x81, 0xFF, 0xF3, 0xD3, 0x7F, 0xFF,
+	0xF3, 0xD2, 0x7D, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD1, 0x77, 0xFF,
+	0xF2, 0xD0, 0x74, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCD, 0x6D, 0xFF,
+	0xF2, 0xCC, 0x6A, 0xFF, 0xF1, 0xCC, 0x68, 0xFF, 0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCA, 0x63, 0xFF,
+	0xF1, 0xC9, 0x60, 0xFF, 0xF0, 0xC8, 0x5D, 0xFF, 0xF0, 0xC8, 0x5B, 0xFF, 0xF0, 0xC6, 0x58, 0xFF,
+	0xF0, 0xC5, 0x55, 0xFF, 0xF1, 0xC6, 0x55, 0xFF, 0xF1, 0xC7, 0x54, 0xFF, 0xEE, 0xC1, 0x4B, 0xFF,
+	0xE8, 0xB8, 0x3F, 0xFF, 0xE3, 0xAF, 0x35, 0xFF, 0xDC, 0xA6, 0x2D, 0xFF, 0xBC, 0x8C, 0x24, 0xEC,
+	0x70, 0x53, 0x16, 0xBA, 0x2C, 0x21, 0x09, 0x90, 0x09, 0x07, 0x02, 0x6E, 0x00, 0x00, 0x00, 0x51,
+	0x00, 0x00, 0x00, 0x3D, 0x01, 0x00, 0x00, 0x2B, 0x02, 0x01, 0x00, 0x1A, 0x00, 0x00, 0x00, 0x0D,
+	0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0C,
+	0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x2A, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x51,
+	0x00, 0x00, 0x00, 0x67, 0x00, 0x00, 0x00, 0x80, 0x3F, 0x2F, 0x0C, 0xA6, 0xA6, 0x7C, 0x20, 0xDD,
+	0xD5, 0xA0, 0x2D, 0xFF, 0xE1, 0xAD, 0x36, 0xFF, 0xE7, 0xB6, 0x40, 0xFF, 0xEC, 0xBF, 0x4B, 0xFF,
+	0xEF, 0xC5, 0x53, 0xFF, 0xF0, 0xC7, 0x56, 0xFF, 0xF0, 0xC7, 0x58, 0xFF, 0xF0, 0xC8, 0x5B, 0xFF,
+	0xF0, 0xC9, 0x5F, 0xFF, 0xF0, 0xCA, 0x61, 0xFF, 0xF1, 0xCB, 0x64, 0xFF, 0xF1, 0xCB, 0x66, 0xFF,
+	0xF2, 0xCC, 0x68, 0xFF, 0xF2, 0xCD, 0x6B, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF, 0xF2, 0xCF, 0x70, 0xFF,
+	0xF2, 0xD0, 0x73, 0xFF, 0xF2, 0xD0, 0x75, 0xFF, 0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD1, 0x7B, 0xFF,
+	0xF3, 0xD2, 0x7D, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF, 0xF4, 0xD4, 0x81, 0xFF, 0xF4, 0xD5, 0x83, 0xFF,
+	0xF4, 0xD6, 0x85, 0xFF, 0xF4, 0xD6, 0x87, 0xFF, 0xF4, 0xD6, 0x89, 0xFF, 0xF4, 0xD7, 0x8A, 0xFF,
+	0xF4, 0xD8, 0x8B, 0xFF, 0xF5, 0xD9, 0x8D, 0xFF, 0xF5, 0xD9, 0x8E, 0xFF, 0xF5, 0xDA, 0x90, 0xFF,
+	0xF5, 0xDA, 0x91, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xDA, 0x93, 0xFF, 0xF5, 0xDA, 0x94, 0xFF,
+	0xF5, 0xDA, 0x95, 0xFF, 0xF5, 0xDB, 0x95, 0xFF, 0xF5, 0xDB, 0x95, 0xFF, 0xF5, 0xDB, 0x95, 0xFF,
+	0xF5, 0xDB, 0x95, 0xFF, 0xF5, 0xDB, 0x94, 0xFF, 0xF5, 0xDA, 0x94, 0xFF, 0xF5, 0xDA, 0x93, 0xFF,
+	0xF5, 0xDA, 0x93, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xD9, 0x90, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF,
+	0xF5, 0xD8, 0x8E, 0xFF, 0xF5, 0xD8, 0x8C, 0xFF, 0xF4, 0xD8, 0x8A, 0xFF, 0xF4, 0xD7, 0x88, 0xFF,
+	0xF4, 0xD7, 0x87, 0xFF, 0xF4, 0xD6, 0x85, 0xFF, 0xF4, 0xD5, 0x83, 0xFF, 0xF3, 0xD4, 0x81, 0xFF,
+	0xF3, 0xD3, 0x80, 0xFF, 0xF3, 0xD2, 0x7E, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD1, 0x79, 0xFF,
+	0xF3, 0xD1, 0x76, 0xFF, 0xF2, 0xD0, 0x73, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF,
+	0xF2, 0xCD, 0x6C, 0xFF, 0xF1, 0xCC, 0x69, 0xFF, 0xF1, 0xCC, 0x67, 0xFF, 0xF1, 0xCB, 0x64, 0xFF,
+	0xF1, 0xCA, 0x62, 0xFF, 0xF0, 0xC9, 0x5F, 0xFF, 0xF0, 0xC8, 0x5C, 0xFF, 0xF0, 0xC7, 0x59, 0xFF,
+	0xF0, 0xC6, 0x57, 0xFF, 0xF1, 0xC7, 0x56, 0xFF, 0xF0, 0xC6, 0x53, 0xFF, 0xEB, 0xBD, 0x47, 0xFF,
+	0xE2, 0xAF, 0x37, 0xFF, 0xD8, 0xA4, 0x2E, 0xFE, 0xC9, 0x98, 0x28, 0xF9, 0xA0, 0x78, 0x1F, 0xD5,
+	0x37, 0x2A, 0x0B, 0x98, 0x00, 0x00, 0x00, 0x6E, 0x00, 0x00, 0x00, 0x5A, 0x02, 0x02, 0x00, 0x47,
+	0x02, 0x01, 0x00, 0x32, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x43,
+	0x00, 0x00, 0x00, 0x57, 0x00, 0x00, 0x00, 0x6D, 0x1F, 0x18, 0x06, 0x8E, 0x75, 0x58, 0x17, 0xBF,
+	0xAA, 0x80, 0x23, 0xE4, 0xD1, 0x9F, 0x2D, 0xF9, 0xEA, 0xB4, 0x38, 0xFF, 0xEF, 0xBE, 0x46, 0xFF,
+	0xEE, 0xC4, 0x53, 0xFF, 0xF0, 0xC7, 0x59, 0xFF, 0xF0, 0xC9, 0x5C, 0xFF, 0xF1, 0xCA, 0x5E, 0xFF,
+	0xF1, 0xCA, 0x61, 0xFF, 0xF1, 0xCA, 0x63, 0xFF, 0xF1, 0xCB, 0x66, 0xFF, 0xF1, 0xCC, 0x68, 0xFF,
+	0xF2, 0xCD, 0x6B, 0xFF, 0xF2, 0xCE, 0x6D, 0xFF, 0xF2, 0xCF, 0x70, 0xFF, 0xF2, 0xCF, 0x73, 0xFF,
+	0xF2, 0xD0, 0x75, 0xFF, 0xF3, 0xD1, 0x77, 0xFF, 0xF3, 0xD1, 0x7A, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF,
+	0xF3, 0xD3, 0x7E, 0xFF, 0xF4, 0xD4, 0x81, 0xFF, 0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD6, 0x85, 0xFF,
+	0xF4, 0xD7, 0x87, 0xFF, 0xF4, 0xD7, 0x89, 0xFF, 0xF4, 0xD7, 0x8B, 0xFF, 0xF4, 0xD8, 0x8D, 0xFF,
+	0xF5, 0xD8, 0x8E, 0xFF, 0xF5, 0xD9, 0x90, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xDA, 0x93, 0xFF,
+	0xF5, 0xDB, 0x94, 0xFF, 0xF5, 0xDB, 0x95, 0xFF, 0xF6, 0xDB, 0x96, 0xFF, 0xF6, 0xDB, 0x97, 0xFF,
+	0xF6, 0xDC, 0x97, 0xFF, 0xF6, 0xDC, 0x98, 0xFF, 0xF6, 0xDC, 0x98, 0xFF, 0xF6, 0xDC, 0x98, 0xFF,
+	0xF6, 0xDC, 0x98, 0xFF, 0xF6, 0xDC, 0x97, 0xFF, 0xF6, 0xDC, 0x96, 0xFF, 0xF5, 0xDB, 0x96, 0xFF,
+	0xF5, 0xDB, 0x96, 0xFF, 0xF5, 0xDB, 0x95, 0xFF, 0xF5, 0xDA, 0x93, 0xFF, 0xF5, 0xDA, 0x92, 0xFF,
+	0xF5, 0xD9, 0x91, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF, 0xF5, 0xD8, 0x8D, 0xFF, 0xF4, 0xD8, 0x8B, 0xFF,
+	0xF4, 0xD8, 0x8A, 0xFF, 0xF4, 0xD7, 0x88, 0xFF, 0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD5, 0x84, 0xFF,
+	0xF3, 0xD4, 0x82, 0xFF, 0xF3, 0xD3, 0x80, 0xFF, 0xF3, 0xD2, 0x7D, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF,
+	0xF3, 0xD1, 0x78, 0xFF, 0xF3, 0xD0, 0x75, 0xFF, 0xF2, 0xD0, 0x73, 0xFF, 0xF2, 0xCF, 0x71, 0xFF,
+	0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF, 0xF1, 0xCC, 0x69, 0xFF, 0xF1, 0xCB, 0x66, 0xFF,
+	0xF1, 0xCA, 0x64, 0xFF, 0xF1, 0xC9, 0x61, 0xFF, 0xF1, 0xC9, 0x5E, 0xFF, 0xF1, 0xC9, 0x5D, 0xFF,
+	0xF1, 0xC9, 0x5B, 0xFF, 0xEE, 0xC5, 0x54, 0xFF, 0xEA, 0xBE, 0x4A, 0xFF, 0xE8, 0xB6, 0x3E, 0xFF,
+	0xE2, 0xAC, 0x32, 0xFF, 0xC3, 0x93, 0x27, 0xF1, 0x88, 0x66, 0x1B, 0xCE, 0x4F, 0x3B, 0x0F, 0xA8,
+	0x0F, 0x0C, 0x03, 0x7E, 0x00, 0x00, 0x00, 0x5F, 0x00, 0x00, 0x00, 0x4B, 0x02, 0x02, 0x00, 0x39,
+	0x03, 0x02, 0x00, 0x26, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x35,
+	0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x5E, 0x11, 0x0D, 0x03, 0x7A, 0x3C, 0x2F, 0x0D, 0x9E,
+	0x72, 0x58, 0x17, 0xC2, 0xB9, 0x8C, 0x24, 0xE8, 0xE3, 0xAC, 0x30, 0xFF, 0xEB, 0xB8, 0x40, 0xFF,
+	0xEC, 0xBF, 0x4E, 0xFF, 0xEF, 0xC5, 0x57, 0xFF, 0xF0, 0xC9, 0x5D, 0xFF, 0xF1, 0xCA, 0x60, 0xFF,
+	0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCC, 0x68, 0xFF, 0xF1, 0xCD, 0x6B, 0xFF,
+	0xF2, 0xCE, 0x6D, 0xFF, 0xF2, 0xCF, 0x6F, 0xFF, 0xF2, 0xD0, 0x72, 0xFF, 0xF2, 0xD0, 0x75, 0xFF,
+	0xF3, 0xD1, 0x77, 0xFF, 0xF3, 0xD1, 0x7A, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD3, 0x7D, 0xFF,
+	0xF4, 0xD4, 0x80, 0xFF, 0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD7, 0x88, 0xFF,
+	0xF4, 0xD7, 0x8A, 0xFF, 0xF4, 0xD8, 0x8C, 0xFF, 0xF4, 0xD8, 0x8D, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF,
+	0xF5, 0xD9, 0x91, 0xFF, 0xF5, 0xDA, 0x93, 0xFF, 0xF5, 0xDA, 0x95, 0xFF, 0xF5, 0xDB, 0x96, 0xFF,
+	0xF5, 0xDB, 0x97, 0xFF, 0xF6, 0xDC, 0x98, 0xFF, 0xF6, 0xDC, 0x99, 0xFF, 0xF6, 0xDD, 0x9A, 0xFF,
+	0xF6, 0xDD, 0x9A, 0xFF, 0xF6, 0xDD, 0x9B, 0xFF, 0xF6, 0xDD, 0x9B, 0xFF, 0xF6, 0xDD, 0x9B, 0xFF,
+	0xF6, 0xDD, 0x9B, 0xFF, 0xF6, 0xDD, 0x9A, 0xFF, 0xF6, 0xDD, 0x99, 0xFF, 0xF6, 0xDD, 0x99, 0xFF,
+	0xF5, 0xDC, 0x98, 0xFF, 0xF5, 0xDC, 0x98, 0xFF, 0xF5, 0xDB, 0x97, 0xFF, 0xF5, 0xDB, 0x95, 0xFF,
+	0xF5, 0xDA, 0x94, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xD9, 0x90, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF,
+	0xF4, 0xD8, 0x8D, 0xFF, 0xF4, 0xD8, 0x8B, 0xFF, 0xF4, 0xD7, 0x88, 0xFF, 0xF4, 0xD6, 0x86, 0xFF,
+	0xF4, 0xD5, 0x84, 0xFF, 0xF3, 0xD4, 0x81, 0xFF, 0xF3, 0xD3, 0x7F, 0xFF, 0xF3, 0xD2, 0x7D, 0xFF,
+	0xF3, 0xD2, 0x7A, 0xFF, 0xF3, 0xD1, 0x77, 0xFF, 0xF3, 0xD1, 0x75, 0xFF, 0xF2, 0xD0, 0x73, 0xFF,
+	0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF, 0xF2, 0xCD, 0x6B, 0xFF, 0xF1, 0xCC, 0x68, 0xFF,
+	0xF1, 0xCB, 0x65, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xF1, 0xC9, 0x60, 0xFF, 0xF1, 0xCA, 0x5F, 0xFF,
+	0xF0, 0xC8, 0x5B, 0xFF, 0xEB, 0xC0, 0x4F, 0xFF, 0xE4, 0xB5, 0x3F, 0xFF, 0xE0, 0xAD, 0x34, 0xFF,
+	0xD8, 0xA2, 0x2C, 0xFF, 0xA5, 0x7B, 0x1F, 0xDC, 0x2F, 0x23, 0x09, 0xA2, 0x00, 0x00, 0x00, 0x7D,
+	0x00, 0x00, 0x00, 0x69, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x2B,
+	0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x1A, 0x01, 0x00, 0x00, 0x28,
+	0x00, 0x00, 0x00, 0x3A, 0x00, 0x00, 0x00, 0x4E, 0x02, 0x02, 0x01, 0x66, 0x13, 0x10, 0x04, 0x82,
+	0x43, 0x34, 0x0E, 0xA3, 0x8C, 0x69, 0x1A, 0xCC, 0xBC, 0x8E, 0x26, 0xED, 0xD9, 0xA7, 0x34, 0xFC,
+	0xEB, 0xB9, 0x41, 0xFF, 0xEF, 0xC1, 0x4D, 0xFF, 0xEE, 0xC5, 0x58, 0xFF, 0xF0, 0xC9, 0x60, 0xFF,
+	0xF1, 0xCB, 0x65, 0xFF, 0xF2, 0xCC, 0x68, 0xFF, 0xF1, 0xCC, 0x69, 0xFF, 0xF2, 0xCD, 0x6B, 0xFF,
+	0xF2, 0xCE, 0x6E, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xD0, 0x74, 0xFF, 0xF2, 0xD1, 0x77, 0xFF,
+	0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF, 0xF3, 0xD4, 0x80, 0xFF,
+	0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD6, 0x85, 0xFF, 0xF4, 0xD7, 0x88, 0xFF, 0xF4, 0xD7, 0x8B, 0xFF,
+	0xF4, 0xD8, 0x8D, 0xFF, 0xF4, 0xD9, 0x8E, 0xFF, 0xF5, 0xD9, 0x90, 0xFF, 0xF5, 0xDA, 0x92, 0xFF,
+	0xF5, 0xDB, 0x94, 0xFF, 0xF5, 0xDB, 0x96, 0xFF, 0xF5, 0xDB, 0x98, 0xFF, 0xF5, 0xDC, 0x99, 0xFF,
+	0xF5, 0xDD, 0x9A, 0xFF, 0xF6, 0xDD, 0x9B, 0xFF, 0xF6, 0xDD, 0x9C, 0xFF, 0xF6, 0xDE, 0x9D, 0xFF,
+	0xF6, 0xDE, 0x9D, 0xFF, 0xF6, 0xDE, 0x9E, 0xFF, 0xF6, 0xDE, 0x9E, 0xFF, 0xF6, 0xDE, 0x9E, 0xFF,
+	0xF6, 0xDE, 0x9E, 0xFF, 0xF6, 0xDE, 0x9D, 0xFF, 0xF6, 0xDE, 0x9D, 0xFF, 0xF6, 0xDE, 0x9C, 0xFF,
+	0xF5, 0xDD, 0x9B, 0xFF, 0xF5, 0xDD, 0x9A, 0xFF, 0xF5, 0xDC, 0x99, 0xFF, 0xF5, 0xDC, 0x98, 0xFF,
+	0xF5, 0xDB, 0x96, 0xFF, 0xF5, 0xDB, 0x95, 0xFF, 0xF5, 0xDA, 0x93, 0xFF, 0xF5, 0xDA, 0x91, 0xFF,
+	0xF5, 0xD9, 0x8F, 0xFF, 0xF4, 0xD8, 0x8D, 0xFF, 0xF4, 0xD8, 0x8B, 0xFF, 0xF4, 0xD7, 0x89, 0xFF,
+	0xF4, 0xD6, 0x86, 0xFF, 0xF3, 0xD5, 0x83, 0xFF, 0xF3, 0xD4, 0x81, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF,
+	0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD2, 0x79, 0xFF, 0xF3, 0xD1, 0x77, 0xFF, 0xF2, 0xD0, 0x74, 0xFF,
+	0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF, 0xF1, 0xCC, 0x6A, 0xFF,
+	0xF1, 0xCB, 0x67, 0xFF, 0xF2, 0xCC, 0x66, 0xFF, 0xF2, 0xCB, 0x63, 0xFF, 0xEF, 0xC5, 0x5A, 0xFF,
+	0xEB, 0xBF, 0x4E, 0xFF, 0xED, 0xBB, 0x43, 0xFF, 0xEA, 0xB5, 0x38, 0xFF, 0xD1, 0xA0, 0x2D, 0xF9,
+	0xA7, 0x7E, 0x21, 0xE1, 0x6C, 0x51, 0x14, 0xBA, 0x0B, 0x08, 0x02, 0x8A, 0x00, 0x00, 0x00, 0x6A,
+	0x00, 0x00, 0x00, 0x57, 0x03, 0x02, 0x01, 0x44, 0x02, 0x02, 0x00, 0x30, 0x00, 0x00, 0x00, 0x20,
+	0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x1D,
+	0x00, 0x00, 0x00, 0x2C, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x53, 0x00, 0x00, 0x00, 0x68,
+	0x16, 0x10, 0x04, 0x84, 0x4F, 0x3B, 0x0F, 0xAB, 0x82, 0x61, 0x1A, 0xCF, 0xBB, 0x8D, 0x25, 0xEE,
+	0xE2, 0xAC, 0x31, 0xFF, 0xEA, 0xB8, 0x40, 0xFF, 0xEA, 0xBF, 0x50, 0xFF, 0xEE, 0xC6, 0x5C, 0xFF,
+	0xF1, 0xCB, 0x66, 0xFF, 0xF2, 0xCD, 0x6A, 0xFF, 0xF2, 0xCD, 0x6A, 0xFF, 0xF2, 0xCD, 0x6C, 0xFF,
+	0xF2, 0xCE, 0x6F, 0xFF, 0xF2, 0xCF, 0x72, 0xFF, 0xF2, 0xD0, 0x75, 0xFF, 0xF2, 0xD1, 0x78, 0xFF,
+	0xF3, 0xD2, 0x7B, 0xFF, 0xF3, 0xD3, 0x7D, 0xFF, 0xF4, 0xD4, 0x80, 0xFF, 0xF4, 0xD5, 0x83, 0xFF,
+	0xF4, 0xD6, 0x85, 0xFF, 0xF4, 0xD7, 0x88, 0xFF, 0xF4, 0xD7, 0x8B, 0xFF, 0xF5, 0xD8, 0x8D, 0xFF,
+	0xF5, 0xD9, 0x8F, 0xFF, 0xF5, 0xDA, 0x91, 0xFF, 0xF5, 0xDB, 0x93, 0xFF, 0xF5, 0xDC, 0x95, 0xFF,
+	0xF5, 0xDC, 0x97, 0xFF, 0xF6, 0xDC, 0x99, 0xFF, 0xF6, 0xDC, 0x9A, 0xFF, 0xF6, 0xDD, 0x9C, 0xFF,
+	0xF6, 0xDE, 0x9D, 0xFF, 0xF6, 0xDF, 0x9E, 0xFF, 0xF6, 0xDF, 0x9F, 0xFF, 0xF6, 0xDF, 0xA0, 0xFF,
+	0xF6, 0xDF, 0xA0, 0xFF, 0xF6, 0xDF, 0xA1, 0xFF, 0xF6, 0xDF, 0xA1, 0xFF, 0xF6, 0xDF, 0xA1, 0xFF,
+	0xF6, 0xDF, 0xA0, 0xFF, 0xF6, 0xDF, 0xA0, 0xFF, 0xF6, 0xDF, 0xA0, 0xFF, 0xF6, 0xDF, 0x9F, 0xFF,
+	0xF6, 0xDE, 0x9E, 0xFF, 0xF6, 0xDE, 0x9D, 0xFF, 0xF6, 0xDD, 0x9C, 0xFF, 0xF6, 0xDD, 0x9B, 0xFF,
+	0xF6, 0xDC, 0x99, 0xFF, 0xF6, 0xDC, 0x97, 0xFF, 0xF5, 0xDB, 0x95, 0xFF, 0xF5, 0xDB, 0x93, 0xFF,
+	0xF5, 0xDA, 0x91, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF, 0xF4, 0xD8, 0x8E, 0xFF, 0xF4, 0xD8, 0x8C, 0xFF,
+	0xF4, 0xD7, 0x88, 0xFF, 0xF4, 0xD6, 0x85, 0xFF, 0xF4, 0xD5, 0x82, 0xFF, 0xF3, 0xD4, 0x80, 0xFF,
+	0xF3, 0xD3, 0x7E, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD1, 0x79, 0xFF, 0xF2, 0xD0, 0x75, 0xFF,
+	0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xCF, 0x70, 0xFF, 0xF2, 0xCE, 0x6E, 0xFF, 0xF1, 0xCD, 0x6B, 0xFF,
+	0xF1, 0xCC, 0x68, 0xFF, 0xF2, 0xCD, 0x68, 0xFF, 0xF1, 0xCA, 0x62, 0xFF, 0xEB, 0xBE, 0x50, 0xFF,
+	0xE5, 0xB2, 0x3E, 0xFF, 0xEA, 0xB3, 0x36, 0xFF, 0xE8, 0xB1, 0x32, 0xFF, 0xB7, 0x8B, 0x26, 0xE7,
+	0x5B, 0x46, 0x13, 0xB9, 0x20, 0x19, 0x06, 0x96, 0x07, 0x06, 0x01, 0x78, 0x00, 0x00, 0x00, 0x5E,
+	0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x16,
+	0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x13,
+	0x01, 0x01, 0x00, 0x20, 0x02, 0x01, 0x00, 0x31, 0x00, 0x00, 0x00, 0x42, 0x00, 0x00, 0x00, 0x55,
+	0x00, 0x00, 0x00, 0x6D, 0x22, 0x19, 0x07, 0x8E, 0x4F, 0x3B, 0x0F, 0xAF, 0x87, 0x65, 0x18, 0xCF,
+	0xB4, 0x88, 0x23, 0xEA, 0xD3, 0xA3, 0x33, 0xF9, 0xE9, 0xB9, 0x43, 0xFF, 0xEF, 0xC2, 0x4F, 0xFF,
+	0xEE, 0xC5, 0x5A, 0xFF, 0xF0, 0xCA, 0x65, 0xFF, 0xF2, 0xCE, 0x6D, 0xFF, 0xF3, 0xD0, 0x71, 0xFF,
+	0xF3, 0xCF, 0x72, 0xFF, 0xF2, 0xD0, 0x74, 0xFF, 0xF2, 0xD1, 0x77, 0xFF, 0xF2, 0xD2, 0x79, 0xFF,
+	0xF3, 0xD3, 0x7C, 0xFF, 0xF3, 0xD4, 0x7F, 0xFF, 0xF4, 0xD5, 0x82, 0xFF, 0xF4, 0xD6, 0x85, 0xFF,
+	0xF4, 0xD7, 0x87, 0xFF, 0xF4, 0xD7, 0x8A, 0xFF, 0xF4, 0xD8, 0x8C, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF,
+	0xF5, 0xD9, 0x91, 0xFF, 0xF5, 0xDB, 0x93, 0xFF, 0xF5, 0xDB, 0x95, 0xFF, 0xF5, 0xDC, 0x97, 0xFF,
+	0xF5, 0xDD, 0x9A, 0xFF, 0xF6, 0xDD, 0x9B, 0xFF, 0xF6, 0xDD, 0x9D, 0xFF, 0xF6, 0xDE, 0x9E, 0xFF,
+	0xF6, 0xDF, 0xA0, 0xFF, 0xF6, 0xE0, 0xA1, 0xFF, 0xF6, 0xE0, 0xA2, 0xFF, 0xF6, 0xE0, 0xA3, 0xFF,
+	0xF6, 0xE0, 0xA3, 0xFF, 0xF6, 0xE0, 0xA4, 0xFF, 0xF6, 0xE0, 0xA4, 0xFF, 0xF6, 0xE0, 0xA4, 0xFF,
+	0xF6, 0xE0, 0xA3, 0xFF, 0xF6, 0xE0, 0xA3, 0xFF, 0xF6, 0xE0, 0xA3, 0xFF, 0xF6, 0xDF, 0xA3, 0xFF,
+	0xF6, 0xDF, 0xA1, 0xFF, 0xF6, 0xDE, 0xA0, 0xFF, 0xF6, 0xDE, 0x9F, 0xFF, 0xF6, 0xDD, 0x9D, 0xFF,
+	0xF6, 0xDD, 0x9B, 0xFF, 0xF6, 0xDD, 0x99, 0xFF, 0xF6, 0xDC, 0x98, 0xFF, 0xF5, 0xDC, 0x96, 0xFF,
+	0xF5, 0xDB, 0x94, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xD9, 0x90, 0xFF, 0xF4, 0xD8, 0x8D, 0xFF,
+	0xF4, 0xD8, 0x8A, 0xFF, 0xF4, 0xD7, 0x87, 0xFF, 0xF4, 0xD6, 0x85, 0xFF, 0xF3, 0xD5, 0x83, 0xFF,
+	0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD3, 0x7D, 0xFF, 0xF3, 0xD2, 0x7A, 0xFF, 0xF2, 0xD1, 0x77, 0xFF,
+	0xF2, 0xD0, 0x74, 0xFF, 0xF2, 0xCF, 0x73, 0xFF, 0xF2, 0xCF, 0x71, 0xFF, 0xF2, 0xCF, 0x6F, 0xFF,
+	0xF1, 0xCD, 0x6A, 0xFF, 0xF0, 0xC9, 0x60, 0xFF, 0xEE, 0xC3, 0x54, 0xFF, 0xEA, 0xB9, 0x44, 0xFF,
+	0xE2, 0xAD, 0x35, 0xFF, 0xD1, 0x9F, 0x2D, 0xF8, 0xB7, 0x8A, 0x25, 0xE6, 0x80, 0x61, 0x19, 0xC4,
+	0x29, 0x20, 0x08, 0x9A, 0x00, 0x00, 0x00, 0x7B, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 0x4D,
+	0x00, 0x00, 0x00, 0x39, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x0E,
+	0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x46,
+	0x00, 0x00, 0x00, 0x5B, 0x03, 0x02, 0x00, 0x72, 0x17, 0x11, 0x04, 0x8C, 0x34, 0x27, 0x0A, 0xA7,
+	0x61, 0x4A, 0x13, 0xC4, 0xAC, 0x83, 0x24, 0xE6, 0xE4, 0xB0, 0x33, 0xFF, 0xEE, 0xBA, 0x3E, 0xFF,
+	0xE9, 0xBB, 0x49, 0xFF, 0xED, 0xC4, 0x5B, 0xFF, 0xF2, 0xCE, 0x6F, 0xFF, 0xF4, 0xD2, 0x76, 0xFF,
+	0xF3, 0xD0, 0x75, 0xFF, 0xF3, 0xD0, 0x76, 0xFF, 0xF3, 0xD1, 0x79, 0xFF, 0xF3, 0xD2, 0x7B, 0xFF,
+	0xF3, 0xD3, 0x7E, 0xFF, 0xF3, 0xD4, 0x81, 0xFF, 0xF4, 0xD5, 0x83, 0xFF, 0xF4, 0xD6, 0x86, 0xFF,
+	0xF4, 0xD7, 0x89, 0xFF, 0xF4, 0xD8, 0x8B, 0xFF, 0xF4, 0xD9, 0x8E, 0xFF, 0xF5, 0xDA, 0x90, 0xFF,
+	0xF5, 0xDB, 0x92, 0xFF, 0xF6, 0xDC, 0x95, 0xFF, 0xF6, 0xDC, 0x97, 0xFF, 0xF6, 0xDD, 0x9A, 0xFF,
+	0xF6, 0xDD, 0x9C, 0xFF, 0xF6, 0xDE, 0x9E, 0xFF, 0xF6, 0xDF, 0xA0, 0xFF, 0xF7, 0xDF, 0xA1, 0xFF,
+	0xF7, 0xE0, 0xA2, 0xFF, 0xF7, 0xE0, 0xA4, 0xFF, 0xF7, 0xE1, 0xA5, 0xFF, 0xF7, 0xE1, 0xA6, 0xFF,
+	0xF7, 0xE2, 0xA6, 0xFF, 0xF7, 0xE2, 0xA6, 0xFF, 0xF7, 0xE2, 0xA7, 0xFF, 0xF7, 0xE2, 0xA7, 0xFF,
+	0xF7, 0xE2, 0xA7, 0xFF, 0xF7, 0xE1, 0xA6, 0xFF, 0xF7, 0xE1, 0xA6, 0xFF, 0xF7, 0xE0, 0xA5, 0xFF,
+	0xF7, 0xE0, 0xA4, 0xFF, 0xF7, 0xDF, 0xA3, 0xFF, 0xF6, 0xDF, 0xA2, 0xFF, 0xF6, 0xDE, 0xA0, 0xFF,
+	0xF6, 0xDE, 0x9E, 0xFF, 0xF6, 0xDD, 0x9C, 0xFF, 0xF6, 0xDD, 0x9A, 0xFF, 0xF6, 0xDD, 0x98, 0xFF,
+	0xF5, 0xDC, 0x96, 0xFF, 0xF5, 0xDB, 0x94, 0xFF, 0xF5, 0xDA, 0x91, 0xFF, 0xF5, 0xD9, 0x8E, 0xFF,
+	0xF4, 0xD8, 0x8C, 0xFF, 0xF4, 0xD7, 0x8A, 0xFF, 0xF4, 0xD6, 0x87, 0xFF, 0xF4, 0xD5, 0x85, 0xFF,
+	0xF4, 0xD4, 0x82, 0xFF, 0xF3, 0xD3, 0x7F, 0xFF, 0xF3, 0xD2, 0x7C, 0xFF, 0xF3, 0xD1, 0x79, 0xFF,
+	0xF3, 0xD0, 0x76, 0xFF, 0xF3, 0xD0, 0x75, 0xFF, 0xF2, 0xCF, 0x73, 0xFF, 0xF3, 0xD0, 0x73, 0xFF,
+	0xF1, 0xCD, 0x6B, 0xFF, 0xED, 0xC1, 0x53, 0xFF, 0xE7, 0xB6, 0x3D, 0xFF, 0xE7, 0xB2, 0x36, 0xFF,
+	0xDC, 0xA8, 0x30, 0xFF, 0xA5, 0x7E, 0x23, 0xE0, 0x50, 0x3D, 0x10, 0xB5, 0x1F, 0x18, 0x06, 0x97,
+	0x0B, 0x09, 0x02, 0x7D, 0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x3D,
+	0x00, 0x00, 0x00, 0x2B, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x07,
+	0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x06,
+	0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00, 0x00, 0x27, 0x02, 0x02, 0x00, 0x37,
+	0x00, 0x00, 0x00, 0x49, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00, 0x00, 0x71, 0x00, 0x00, 0x00, 0x89,
+	0x26, 0x1E, 0x07, 0xA5, 0x7C, 0x5E, 0x17, 0xCA, 0xBD, 0x90, 0x26, 0xEC, 0xD5, 0xA5, 0x30, 0xFA,
+	0xE0, 0xB1, 0x3B, 0xFF, 0xEA, 0xBD, 0x4D, 0xFF, 0xF0, 0xC8, 0x61, 0xFF, 0xF3, 0xCD, 0x6D, 0xFF,
+	0xF3, 0xCF, 0x73, 0xFF, 0xF3, 0xD1, 0x78, 0xFF, 0xF4, 0xD2, 0x7C, 0xFF, 0xF4, 0xD3, 0x7F, 0xFF,
+	0xF3, 0xD4, 0x81, 0xFF, 0xF3, 0xD5, 0x83, 0xFF, 0xF4, 0xD5, 0x85, 0xFF, 0xF4, 0xD6, 0x87, 0xFF,
+	0xF4, 0xD7, 0x8A, 0xFF, 0xF4, 0xD8, 0x8D, 0xFF, 0xF5, 0xD9, 0x90, 0xFF, 0xF5, 0xDA, 0x92, 0xFF,
+	0xF5, 0xDB, 0x94, 0xFF, 0xF6, 0xDC, 0x97, 0xFF, 0xF6, 0xDD, 0x9A, 0xFF, 0xF6, 0xDD, 0x9C, 0xFF,
+	0xF6, 0xDE, 0x9F, 0xFF, 0xF6, 0xDF, 0xA1, 0xFF, 0xF6, 0xE0, 0xA2, 0xFF, 0xF7, 0xE0, 0xA4, 0xFF,
+	0xF7, 0xE0, 0xA5, 0xFF, 0xF7, 0xE1, 0xA7, 0xFF, 0xF7, 0xE2, 0xA8, 0xFF, 0xF7, 0xE2, 0xA8, 0xFF,
+	0xF7, 0xE2, 0xA9, 0xFF, 0xF7, 0xE2, 0xAA, 0xFF, 0xF7, 0xE3, 0xAA, 0xFF, 0xF7, 0xE3, 0xAA, 0xFF,
+	0xF7, 0xE3, 0xAA, 0xFF, 0xF7, 0xE2, 0xA9, 0xFF, 0xF7, 0xE2, 0xA9, 0xFF, 0xF7, 0xE1, 0xA8, 0xFF,
+	0xF7, 0xE1, 0xA7, 0xFF, 0xF7, 0xE0, 0xA6, 0xFF, 0xF6, 0xE0, 0xA4, 0xFF, 0xF6, 0xE0, 0xA3, 0xFF,
+	0xF6, 0xDF, 0xA1, 0xFF, 0xF6, 0xDE, 0x9F, 0xFF, 0xF6, 0xDE, 0x9D, 0xFF, 0xF6, 0xDD, 0x9B, 0xFF,
+	0xF6, 0xDC, 0x99, 0xFF, 0xF5, 0xDB, 0x96, 0xFF, 0xF5, 0xDA, 0x93, 0xFF, 0xF5, 0xD9, 0x90, 0xFF,
+	0xF5, 0xD8, 0x8E, 0xFF, 0xF4, 0xD7, 0x8B, 0xFF, 0xF4, 0xD7, 0x89, 0xFF, 0xF4, 0xD6, 0x86, 0xFF,
+	0xF4, 0xD5, 0x84, 0xFF, 0xF3, 0xD4, 0x80, 0xFF, 0xF3, 0xD3, 0x7E, 0xFF, 0xF3, 0xD3, 0x7D, 0xFF,
+	0xF3, 0xD2, 0x79, 0xFF, 0xF2, 0xCF, 0x74, 0xFF, 0xF1, 0xCE, 0x6E, 0xFF, 0xF3, 0xCD, 0x68, 0xFF,
+	0xF0, 0xC7, 0x5C, 0xFF, 0xE6, 0xB7, 0x44, 0xFF, 0xD8, 0xA6, 0x30, 0xFB, 0xC9, 0x9A, 0x2A, 0xF4,
+	0xB1, 0x87, 0x25, 0xE4, 0x6F, 0x55, 0x17, 0xBF, 0x0C, 0x09, 0x02, 0x94, 0x00, 0x00, 0x00, 0x7A,
+	0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0x3F, 0x01, 0x01, 0x00, 0x2E,
+	0x01, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x03,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x1B, 0x01, 0x01, 0x00, 0x29,
+	0x00, 0x00, 0x00, 0x39, 0x00, 0x00, 0x00, 0x4A, 0x00, 0x00, 0x00, 0x5E, 0x00, 0x00, 0x00, 0x73,
+	0x0C, 0x09, 0x02, 0x8A, 0x35, 0x29, 0x0A, 0xA5, 0x65, 0x4E, 0x15, 0xC2, 0xA1, 0x7D, 0x23, 0xE1,
+	0xD5, 0xA5, 0x30, 0xFC, 0xE7, 0xB5, 0x3B, 0xFF, 0xEB, 0xBB, 0x48, 0xFF, 0xEF, 0xC4, 0x58, 0xFF,
+	0xF2, 0xCC, 0x6C, 0xFF, 0xF3, 0xD2, 0x79, 0xFF, 0xF4, 0xD4, 0x81, 0xFF, 0xF5, 0xD5, 0x84, 0xFF,
+	0xF4, 0xD5, 0x84, 0xFF, 0xF4, 0xD5, 0x84, 0xFF, 0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD7, 0x89, 0xFF,
+	0xF4, 0xD8, 0x8C, 0xFF, 0xF5, 0xD9, 0x8F, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xDB, 0x94, 0xFF,
+	0xF5, 0xDC, 0x97, 0xFF, 0xF6, 0xDD, 0x9A, 0xFF, 0xF6, 0xDD, 0x9C, 0xFF, 0xF6, 0xDE, 0x9E, 0xFF,
+	0xF6, 0xDF, 0xA0, 0xFF, 0xF7, 0xE0, 0xA3, 0xFF, 0xF7, 0xE1, 0xA5, 0xFF, 0xF7, 0xE1, 0xA6, 0xFF,
+	0xF7, 0xE1, 0xA8, 0xFF, 0xF7, 0xE2, 0xA9, 0xFF, 0xF7, 0xE2, 0xAA, 0xFF, 0xF7, 0xE2, 0xAB, 0xFF,
+	0xF8, 0xE3, 0xAC, 0xFF, 0xF8, 0xE3, 0xAD, 0xFF, 0xF8, 0xE3, 0xAE, 0xFF, 0xF8, 0xE3, 0xAE, 0xFF,
+	0xF8, 0xE3, 0xAE, 0xFF, 0xF7, 0xE3, 0xAC, 0xFF, 0xF7, 0xE2, 0xAB, 0xFF, 0xF7, 0xE2, 0xAA, 0xFF,
+	0xF7, 0xE2, 0xAA, 0xFF, 0xF7, 0xE1, 0xA8, 0xFF, 0xF7, 0xE1, 0xA7, 0xFF, 0xF7, 0xE1, 0xA5, 0xFF,
+	0xF7, 0xE0, 0xA3, 0xFF, 0xF7, 0xDF, 0xA1, 0xFF, 0xF6, 0xDE, 0x9F, 0xFF, 0xF6, 0xDE, 0x9D, 0xFF,
+	0xF6, 0xDD, 0x9A, 0xFF, 0xF6, 0xDC, 0x98, 0xFF, 0xF5, 0xDB, 0x95, 0xFF, 0xF5, 0xDA, 0x93, 0xFF,
+	0xF5, 0xD9, 0x90, 0xFF, 0xF5, 0xD8, 0x8D, 0xFF, 0xF5, 0xD7, 0x8A, 0xFF, 0xF4, 0xD7, 0x87, 0xFF,
+	0xF4, 0xD6, 0x85, 0xFF, 0xF3, 0xD4, 0x82, 0xFF, 0xF3, 0xD4, 0x82, 0xFF, 0xF4, 0xD5, 0x82, 0xFF,
+	0xF3, 0xD3, 0x7D, 0xFF, 0xF0, 0xCE, 0x72, 0xFF, 0xF0, 0xC9, 0x63, 0xFF, 0xF3, 0xC6, 0x51, 0xFF,
+	0xEE, 0xBC, 0x41, 0xFF, 0xDB, 0xAB, 0x34, 0xFD, 0xBE, 0x93, 0x29, 0xF0, 0x88, 0x68, 0x1C, 0xD1,
+	0x45, 0x35, 0x0E, 0xB0, 0x1B, 0x14, 0x05, 0x95, 0x01, 0x01, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x68,
+	0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0x00, 0x41, 0x00, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x21,
+	0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x1C,
+	0x00, 0x00, 0x00, 0x2A, 0x01, 0x01, 0x00, 0x3A, 0x00, 0x00, 0x00, 0x4C, 0x00, 0x00, 0x00, 0x5E,
+	0x00, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, 0x88, 0x1B, 0x17, 0x06, 0xA0, 0x6A, 0x52, 0x16, 0xC2,
+	0xB0, 0x87, 0x24, 0xE5, 0xCF, 0x9F, 0x2D, 0xF6, 0xDF, 0xAD, 0x36, 0xFD, 0xE9, 0xBA, 0x46, 0xFF,
+	0xEF, 0xC5, 0x5C, 0xFF, 0xF2, 0xCC, 0x6C, 0xFF, 0xF3, 0xD0, 0x76, 0xFF, 0xF4, 0xD3, 0x7E, 0xFF,
+	0xF4, 0xD5, 0x82, 0xFF, 0xF4, 0xD6, 0x86, 0xFF, 0xF4, 0xD7, 0x89, 0xFF, 0xF4, 0xD8, 0x8C, 0xFF,
+	0xF5, 0xD9, 0x8E, 0xFF, 0xF5, 0xD9, 0x91, 0xFF, 0xF5, 0xDB, 0x93, 0xFF, 0xF5, 0xDC, 0x96, 0xFF,
+	0xF5, 0xDD, 0x99, 0xFF, 0xF6, 0xDD, 0x9C, 0xFF, 0xF6, 0xDE, 0x9E, 0xFF, 0xF6, 0xDF, 0xA0, 0xFF,
+	0xF6, 0xE0, 0xA2, 0xFF, 0xF7, 0xE1, 0xA5, 0xFF, 0xF7, 0xE1, 0xA7, 0xFF, 0xF7, 0xE1, 0xA9, 0xFF,
+	0xF7, 0xE2, 0xAB, 0xFF, 0xF7, 0xE3, 0xAC, 0xFF, 0xF7, 0xE4, 0xAE, 0xFF, 0xF8, 0xE4, 0xAF, 0xFF,
+	0xF8, 0xE4, 0xB0, 0xFF, 0xF8, 0xE4, 0xB2, 0xFF, 0xF8, 0xE5, 0xB3, 0xFF, 0xF8, 0xE5, 0xB3, 0xFF,
+	0xF8, 0xE5, 0xB2, 0xFF, 0xF8, 0xE4, 0xB1, 0xFF, 0xF7, 0xE4, 0xAF, 0xFF, 0xF7, 0xE3, 0xAE, 0xFF,
+	0xF7, 0xE2, 0xAD, 0xFF, 0xF7, 0xE2, 0xAB, 0xFF, 0xF7, 0xE2, 0xA9, 0xFF, 0xF7, 0xE2, 0xA7, 0xFF,
+	0xF7, 0xE1, 0xA5, 0xFF, 0xF7, 0xE0, 0xA3, 0xFF, 0xF6, 0xDF, 0xA1, 0xFF, 0xF6, 0xDE, 0x9F, 0xFF,
+	0xF6, 0xDE, 0x9C, 0xFF, 0xF6, 0xDD, 0x99, 0xFF, 0xF5, 0xDC, 0x97, 0xFF, 0xF5, 0xDA, 0x95, 0xFF,
+	0xF5, 0xD9, 0x92, 0xFF, 0xF5, 0xD9, 0x8E, 0xFF, 0xF5, 0xD8, 0x8C, 0xFF, 0xF4, 0xD8, 0x89, 0xFF,
+	0xF4, 0xD7, 0x87, 0xFF, 0xF3, 0xD5, 0x84, 0xFF, 0xF3, 0xD3, 0x7F, 0xFF, 0xF3, 0xD2, 0x79, 0xFF,
+	0xF2, 0xCE, 0x70, 0xFF, 0xEF, 0xC9, 0x64, 0xFF, 0xEB, 0xC1, 0x54, 0xFF, 0xE5, 0xB6, 0x3F, 0xFE,
+	0xD8, 0xA7, 0x2E, 0xF8, 0xBD, 0x92, 0x27, 0xEB, 0x96, 0x74, 0x1F, 0xD5, 0x4A, 0x39, 0x0F, 0xB0,
+	0x00, 0x00, 0x00, 0x8B, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x68, 0x00, 0x00, 0x00, 0x56,
+	0x00, 0x00, 0x00, 0x42, 0x00, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x16,
+	0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF5, 0xDB, 0x95, 0xFF, 0xF6, 0xDC, 0x97, 0xFF,
+	0xF6, 0xDD, 0x9A, 0xFF, 0xF6, 0xDD, 0x9D, 0xFF, 0xF6, 0xDE, 0xA0, 0xFF, 0xF7, 0xDF, 0xA2, 0xFF,
+	0xF7, 0xE0, 0xA5, 0xFF, 0xF7, 0xE1, 0xA6, 0xFF, 0xF7, 0xE2, 0xA9, 0xFF, 0xF7, 0xE3, 0xAB, 0xFF,
+	0xF8, 0xE3, 0xAE, 0xFF, 0xF7, 0xE4, 0xB0, 0xFF, 0xF8, 0xE5, 0xB2, 0xFF, 0xF8, 0xE6, 0xB4, 0xFF,
+	0xF9, 0xE6, 0xB6, 0xFF, 0xF9, 0xE6, 0xB8, 0xFF, 0xF9, 0xE6, 0xB9, 0xFF, 0xF9, 0xE6, 0xB9, 0xFF,
+	0xF9, 0xE6, 0xB8, 0xFF, 0xF9, 0xE6, 0xB7, 0xFF, 0xF8, 0xE6, 0xB5, 0xFF, 0xF8, 0xE5, 0xB2, 0xFF,
+	0xF8, 0xE3, 0xAF, 0xFF, 0xF7, 0xE3, 0xAD, 0xFF, 0xF7, 0xE3, 0xAC, 0xFF, 0xF7, 0xE3, 0xAA, 0xFF,
+	0xF7, 0xE2, 0xA7, 0xFF, 0xF7, 0xE1, 0xA5, 0xFF, 0xF7, 0xE0, 0xA3, 0xFF, 0xF7, 0xDE, 0xA0, 0xFF,
+	0xF6, 0xDE, 0x9E, 0xFF, 0xF6, 0xDD, 0x9B, 0xFF, 0xF5, 0xDC, 0x98, 0xFF, 0xF5, 0xDB, 0x96, 0xFF,
+	0xF5, 0xDA, 0x93, 0xFF, 0xF5, 0xDA, 0x91, 0xFF, 0xF5, 0xDA, 0x90, 0xFF, 0xF5, 0xDA, 0x90, 0xFF,
+	0xF4, 0xD8, 0x8C, 0xFF, 0xF3, 0xD6, 0x86, 0xFF, 0xF2, 0xD0, 0x76, 0xFF, 0xF1, 0xC8, 0x5F, 0xFF,
+	0xF0, 0xC2, 0x4F, 0xFF, 0xF1, 0xC0, 0x47, 0xFF, 0xE5, 0xB5, 0x3E, 0xFF, 0xC7, 0x9B, 0x2F, 0xF4,
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+	0xD5, 0xA3, 0x29, 0xF9, 0xDE, 0xAC, 0x32, 0xFD, 0xE4, 0xB6, 0x42, 0xFE, 0xEA, 0xC1, 0x56, 0xFF,
+	0xF0, 0xCD, 0x70, 0xFF, 0xF3, 0xD5, 0x82, 0xFF, 0xF4, 0xD7, 0x88, 0xFF, 0xF5, 0xD8, 0x8C, 0xFF,
+	0xF5, 0xDA, 0x90, 0xFF, 0xF5, 0xDB, 0x93, 0xFF, 0xF6, 0xDC, 0x97, 0xFF, 0xF6, 0xDC, 0x9A, 0xFF,
+	0xF6, 0xDD, 0x9C, 0xFF, 0xF6, 0xDE, 0x9F, 0xFF, 0xF6, 0xDF, 0xA2, 0xFF, 0xF7, 0xE0, 0xA5, 0xFF,
+	0xF7, 0xE1, 0xA7, 0xFF, 0xF7, 0xE2, 0xA8, 0xFF, 0xF7, 0xE3, 0xAB, 0xFF, 0xF8, 0xE4, 0xAE, 0xFF,
+	0xF8, 0xE5, 0xB1, 0xFF, 0xF8, 0xE6, 0xB4, 0xFF, 0xF8, 0xE7, 0xB7, 0xFF, 0xF9, 0xE8, 0xBA, 0xFF,
+	0xF9, 0xE9, 0xBD, 0xFF, 0xF9, 0xE9, 0xBE, 0xFF, 0xF9, 0xE8, 0xBF, 0xFF, 0xF9, 0xE9, 0xBF, 0xFF,
+	0xF9, 0xE8, 0xBE, 0xFF, 0xF9, 0xE8, 0xBD, 0xFF, 0xF9, 0xE8, 0xBB, 0xFF, 0xF9, 0xE6, 0xB7, 0xFF,
+	0xF8, 0xE5, 0xB3, 0xFF, 0xF8, 0xE4, 0xB0, 0xFF, 0xF7, 0xE3, 0xAF, 0xFF, 0xF7, 0xE3, 0xAC, 0xFF,
+	0xF7, 0xE3, 0xA9, 0xFF, 0xF7, 0xE2, 0xA7, 0xFF, 0xF7, 0xE0, 0xA4, 0xFF, 0xF7, 0xDF, 0xA2, 0xFF,
+	0xF7, 0xDE, 0xA0, 0xFF, 0xF6, 0xDD, 0x9D, 0xFF, 0xF6, 0xDD, 0x9B, 0xFF, 0xF5, 0xDC, 0x98, 0xFF,
+	0xF5, 0xDB, 0x95, 0xFF, 0xF5, 0xDA, 0x91, 0xFF, 0xF4, 0xD8, 0x8D, 0xFF, 0xF4, 0xD6, 0x89, 0xFF,
+	0xF4, 0xD5, 0x83, 0xFF, 0xF3, 0xD3, 0x7B, 0xFF, 0xEF, 0xC9, 0x66, 0xFF, 0xE7, 0xB9, 0x47, 0xFE,
+	0xE0, 0xAE, 0x34, 0xFD, 0xDD, 0xAB, 0x30, 0xFC, 0xCB, 0x9C, 0x2B, 0xF2, 0x9E, 0x7A, 0x22, 0xDE,
+	0x6A, 0x53, 0x17, 0xC4, 0x2D, 0x23, 0x0A, 0xA1, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00, 0x73,
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+	0x80, 0x61, 0x16, 0xD1, 0x9D, 0x79, 0x20, 0xE1, 0xC7, 0x9B, 0x30, 0xF5, 0xE2, 0xB3, 0x40, 0xFF,
+	0xEF, 0xC2, 0x50, 0xFF, 0xF6, 0xCB, 0x5E, 0xFF, 0xF5, 0xCD, 0x69, 0xFF, 0xF3, 0xD0, 0x76, 0xFF,
+	0xF4, 0xD7, 0x89, 0xFF, 0xF6, 0xDD, 0x99, 0xFF, 0xF7, 0xDF, 0xA0, 0xFF, 0xF7, 0xE0, 0xA3, 0xFF,
+	0xF7, 0xE0, 0xA4, 0xFF, 0xF7, 0xE1, 0xA5, 0xFF, 0xF7, 0xE1, 0xA6, 0xFF, 0xF7, 0xE1, 0xA8, 0xFF,
+	0xF7, 0xE1, 0xA9, 0xFF, 0xF7, 0xE2, 0xAB, 0xFF, 0xF8, 0xE3, 0xAD, 0xFF, 0xF8, 0xE4, 0xB0, 0xFF,
+	0xF9, 0xE5, 0xB4, 0xFF, 0xF9, 0xE7, 0xB8, 0xFF, 0xF9, 0xE8, 0xBC, 0xFF, 0xF9, 0xEA, 0xC0, 0xFF,
+	0xFA, 0xEB, 0xC3, 0xFF, 0xFA, 0xEB, 0xC5, 0xFF, 0xFA, 0xEB, 0xC7, 0xFF, 0xFA, 0xEB, 0xC7, 0xFF,
+	0xF9, 0xEB, 0xC5, 0xFF, 0xFA, 0xEB, 0xC4, 0xFF, 0xFA, 0xEA, 0xC1, 0xFF, 0xF9, 0xE9, 0xBD, 0xFF,
+	0xF9, 0xE7, 0xB9, 0xFF, 0xF8, 0xE5, 0xB5, 0xFF, 0xF8, 0xE4, 0xB1, 0xFF, 0xF7, 0xE3, 0xAE, 0xFF,
+	0xF7, 0xE3, 0xAB, 0xFF, 0xF7, 0xE3, 0xAA, 0xFF, 0xF7, 0xE2, 0xA8, 0xFF, 0xF7, 0xE1, 0xA6, 0xFF,
+	0xF7, 0xE1, 0xA5, 0xFF, 0xF7, 0xE0, 0xA5, 0xFF, 0xF7, 0xE1, 0xA4, 0xFF, 0xF7, 0xE0, 0xA2, 0xFF,
+	0xF6, 0xDE, 0x9C, 0xFF, 0xF5, 0xDA, 0x91, 0xFF, 0xF2, 0xD2, 0x7E, 0xFF, 0xF0, 0xCA, 0x69, 0xFF,
+	0xF5, 0xCA, 0x5E, 0xFF, 0xFB, 0xCD, 0x5A, 0xFF, 0xEE, 0xC0, 0x4C, 0xFF, 0xCE, 0xA2, 0x36, 0xF7,
+	0xB1, 0x89, 0x26, 0xEB, 0x94, 0x72, 0x1E, 0xDB, 0x76, 0x5B, 0x17, 0xC9, 0x56, 0x42, 0x11, 0xB5,
+	0x34, 0x29, 0x0B, 0xA0, 0x0D, 0x0A, 0x03, 0x86, 0x00, 0x00, 0x00, 0x6F, 0x00, 0x00, 0x00, 0x5E,
+	0x00, 0x00, 0x00, 0x50, 0x02, 0x02, 0x01, 0x3F, 0x00, 0x00, 0x00, 0x2F, 0x00, 0x00, 0x00, 0x22,
+	0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x1B,
+	0x00, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0x45, 0x00, 0x00, 0x00, 0x55,
+	0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x76, 0x00, 0x00, 0x00, 0x85, 0x04, 0x03, 0x01, 0x95,
+	0x13, 0x0F, 0x04, 0xA7, 0x4F, 0x3D, 0x10, 0xC0, 0xA0, 0x7A, 0x22, 0xE2, 0xCD, 0x9D, 0x2C, 0xF7,
+	0xE1, 0xAE, 0x33, 0xFD, 0xEB, 0xB8, 0x3C, 0xFF, 0xEC, 0xBD, 0x49, 0xFF, 0xEC, 0xC3, 0x5C, 0xFF,
+	0xF1, 0xD0, 0x79, 0xFF, 0xF5, 0xDA, 0x92, 0xFF, 0xF7, 0xDE, 0x9C, 0xFF, 0xF7, 0xDF, 0xA0, 0xFF,
+	0xF7, 0xE0, 0xA2, 0xFF, 0xF7, 0xE0, 0xA3, 0xFF, 0xF7, 0xE0, 0xA5, 0xFF, 0xF7, 0xE1, 0xA7, 0xFF,
+	0xF7, 0xE1, 0xAA, 0xFF, 0xF8, 0xE2, 0xAC, 0xFF, 0xF8, 0xE4, 0xB0, 0xFF, 0xF9, 0xE5, 0xB4, 0xFF,
+	0xF9, 0xE7, 0xB9, 0xFF, 0xFA, 0xE9, 0xBE, 0xFF, 0xFA, 0xEA, 0xC3, 0xFF, 0xFA, 0xEC, 0xC7, 0xFF,
+	0xFA, 0xED, 0xCA, 0xFF, 0xFB, 0xEE, 0xCD, 0xFF, 0xFB, 0xEE, 0xCF, 0xFF, 0xFB, 0xEE, 0xCF, 0xFF,
+	0xFA, 0xEE, 0xCD, 0xFF, 0xFA, 0xED, 0xCB, 0xFF, 0xFA, 0xEC, 0xC8, 0xFF, 0xFA, 0xEB, 0xC4, 0xFF,
+	0xF9, 0xEA, 0xC0, 0xFF, 0xF9, 0xE8, 0xBB, 0xFF, 0xF8, 0xE5, 0xB5, 0xFF, 0xF8, 0xE4, 0xB0, 0xFF,
+	0xF7, 0xE3, 0xAE, 0xFF, 0xF7, 0xE3, 0xAB, 0xFF, 0xF7, 0xE2, 0xA8, 0xFF, 0xF7, 0xE1, 0xA5, 0xFF,
+	0xF6, 0xE0, 0xA4, 0xFF, 0xF6, 0xE0, 0xA2, 0xFF, 0xF7, 0xE0, 0xA2, 0xFF, 0xF7, 0xDF, 0x9F, 0xFF,
+	0xF6, 0xDC, 0x96, 0xFF, 0xF4, 0xD5, 0x86, 0xFF, 0xEE, 0xC9, 0x69, 0xFF, 0xE8, 0xBA, 0x49, 0xFF,
+	0xEC, 0xB9, 0x3C, 0xFF, 0xF3, 0xBD, 0x3A, 0xFF, 0xDE, 0xAC, 0x33, 0xF8, 0xAC, 0x86, 0x27, 0xE7,
+	0x78, 0x5E, 0x1B, 0xD1, 0x3A, 0x2D, 0x0D, 0xB5, 0x0A, 0x08, 0x02, 0x9E, 0x00, 0x00, 0x00, 0x8D,
+	0x00, 0x00, 0x00, 0x7D, 0x00, 0x00, 0x00, 0x6E, 0x00, 0x00, 0x00, 0x5D, 0x00, 0x00, 0x00, 0x4C,
+	0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x2D, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x15,
+	0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0xFA, 0x8C, 0x5E, 0x75, 0xCF, 0x0F, 0x57, 0x67, 0xC7, 0x7F, 0x35, 0xAD, 0x6E, 0xBE, 0x77, 0x30,
+	0xFE, 0xFE, 0xBF, 0xBB, 0xD5, 0xFD, 0xE0, 0xCF, 0xDF, 0x49, 0xFF, 0xFE, 0x2F, 0xDE, 0x5B, 0xE0,
+	0xCF, 0x6E, 0x9E, 0xC0, 0x8D, 0xAB, 0xE8, 0xA9, 0xAA, 0x1D, 0x46, 0x81, 0xB0, 0x53, 0x11, 0xAE,
+	0x55, 0x82, 0x77, 0x7C, 0xC6, 0xB7, 0xA8, 0x83, 0x23, 0xC1, 0x58, 0x8A, 0x69, 0x1C, 0xE9, 0x2C,
+	0x37, 0xB0, 0xC7, 0x88, 0x79, 0x43, 0x33, 0xF7, 0x45, 0xAC, 0x6A, 0x56, 0x8A, 0x5A, 0xC7, 0x46,
+	0x92, 0x92, 0x02, 0x9F, 0x3B, 0x54, 0x20, 0x44, 0x5F, 0x81, 0x08, 0x88, 0x48, 0xE8, 0x52, 0xC2,
+	0x3C, 0x77, 0xB8, 0x6C, 0x33, 0xCE, 0x12, 0x70, 0x9E, 0x19, 0x17, 0x9D, 0xC3, 0xAC, 0x23, 0xB4,
+	0x42, 0x48, 0x29, 0xA2, 0xBB, 0x5C, 0xC7, 0xF6, 0xE8, 0x7C, 0xD6, 0xDC, 0xBF, 0x73, 0xBE, 0xBA,
+	0xF3, 0xBF, 0x8E, 0xD7, 0x8F, 0x7E, 0x75, 0xDA, 0xCC, 0x2F, 0xCF, 0xE2, 0x72, 0x3E, 0x93, 0x1C,
+	0x5B, 0xBB, 0x2B, 0xFB, 0xC0, 0xCE, 0x00, 0xCC, 0x2C, 0xA0, 0xF3, 0xC1, 0xF8, 0x2F, 0xBD, 0x34,
+	0x9D, 0x7B, 0xCB, 0x83, 0x2A, 0xAF, 0x54, 0xC5, 0x2B, 0xEB, 0x5D, 0x3B, 0xD3, 0xA5, 0xED, 0x3F,
+	0x1A, 0x00, 0x13, 0x94, 0xB2, 0x92, 0x52, 0x56, 0xED, 0xF1, 0xE1, 0x2A, 0xAF, 0x17, 0x6D, 0xEE,
+	0x16, 0x6D, 0x57, 0xD6, 0xAB, 0xEA, 0xEA, 0xFC, 0x82, 0x77, 0x6E, 0xED, 0xB9, 0x9D, 0x1B, 0x3B,
+	0x93, 0x9B, 0xEF, 0xD4, 0x7B, 0xB7, 0x0E, 0x42, 0xB7, 0x3F, 0xAA, 0xD2, 0xC4, 0x87, 0xAE, 0xAE,
+	0x30, 0x77, 0x84, 0x63, 0x66, 0xEC, 0x92, 0xC3, 0x4E, 0x20, 0xEC, 0x64, 0xC6, 0x6E, 0x00, 0xF6,
+	0x00, 0x8C, 0xC9, 0xD4, 0x4D, 0x8D, 0x19, 0xE0, 0x8B, 0x6C, 0x18, 0x32, 0xC9, 0x09, 0x3A, 0x2E,
+	0x2A, 0x94, 0xDA, 0x01, 0xEB, 0x24, 0x58, 0xE6, 0x84, 0x79, 0x61, 0xCC, 0x85, 0xB1, 0x48, 0x0E,
+	0xCB, 0x86, 0xB0, 0xEC, 0x0A, 0x56, 0x99, 0xB0, 0xE8, 0x3A, 0x9C, 0x4F, 0x67, 0xF1, 0xE2, 0x62,
+	0xDA, 0xAE, 0x97, 0x8B, 0x36, 0x2D, 0x67, 0xEB, 0x32, 0xBD, 0x9A, 0xCB, 0xC9, 0xE9, 0x55, 0x7C,
+	0xF8, 0xC1, 0xC5, 0xEA, 0xE3, 0xF7, 0x2F, 0x9A, 0x8B, 0x67, 0xE7, 0x59, 0xAB, 0xDA, 0xB9, 0xFD,
+	0x9E, 0x4B, 0x0B, 0xE8, 0xE5, 0xA0, 0x5D, 0x19, 0x16, 0x45, 0xF1, 0x1B, 0x7A, 0xED, 0x5F, 0xF2,
+	0x57, 0xF8, 0x26, 0x7F, 0x86, 0xB3, 0x63, 0x78, 0x02, 0x60, 0x17, 0xC0, 0xD8, 0xFE, 0xBE, 0x03,
+	0x8D, 0x41, 0xFF, 0xD8, 0x27, 0x1F, 0x6E, 0x70, 0x3D, 0xDE, 0xE5, 0x9D, 0xDD, 0xC0, 0xE3, 0xDD,
+	0x51, 0x16, 0xBA, 0x1E, 0xF6, 0x6E, 0x1C, 0xDC, 0xFA, 0x8F, 0x7F, 0x79, 0xFD, 0xD6, 0x5F, 0xFC,
+	0xE5, 0xB5, 0xDD, 0x6F, 0xBF, 0x77, 0xAD, 0xBA, 0xBE, 0xB7, 0x87, 0xF1, 0x7E, 0xE8, 0xDC, 0x2E,
+	0x0A, 0xD5, 0x00, 0x39, 0xEC, 0x06, 0xC2, 0xED, 0xB1, 0xE0, 0x46, 0x00, 0x26, 0x45, 0xDD, 0x4A,
+	0xC2, 0x98, 0x74, 0xB8, 0x41, 0x82, 0x50, 0x14, 0x16, 0x23, 0x65, 0xAB, 0xCE, 0xDD, 0x24, 0xC2,
+	0x22, 0x02, 0xD3, 0x98, 0x71, 0x9A, 0x22, 0xAE, 0x32, 0x61, 0x5D, 0x46, 0x88, 0x85, 0x50, 0x62,
+	0x03, 0x4A, 0x0D, 0x2A, 0x30, 0x68, 0xBD, 0x4A, 0x57, 0x4F, 0xEE, 0xCD, 0xCF, 0x3E, 0xBD, 0x73,
+	0x31, 0x7F, 0xF0, 0xE1, 0xE9, 0xEA, 0xC1, 0xC7, 0xA7, 0x69, 0x36, 0x9D, 0x32, 0xB9, 0x45, 0x59,
+	0x2F, 0x9A, 0xB2, 0xB8, 0x68, 0x4A, 0x6C, 0x17, 0xA2, 0x77, 0xE7, 0x6C, 0x10, 0xC0, 0xAB, 0xC1,
+	0xE7, 0xAB, 0x37, 0xC1, 0x17, 0xBD, 0xCD, 0x99, 0xFA, 0x9A, 0x19, 0xF1, 0x4B, 0xC7, 0x73, 0xF7,
+	0xD2, 0x83, 0xA8, 0x85, 0x48, 0x2B, 0x29, 0x36, 0x39, 0xC5, 0x49, 0x5E, 0xCE, 0xFA, 0xAA, 0x66,
+	0x9A, 0x80, 0xE9, 0x5C, 0xCA, 0x41, 0xED, 0xFC, 0xCD, 0x7C, 0xF9, 0xDD, 0x85, 0xBB, 0x7E, 0x7D,
+	0x2F, 0x4E, 0xAE, 0xD7, 0x2B, 0xBF, 0x4F, 0x2D, 0x55, 0x2E, 0x15, 0x76, 0x93, 0x8A, 0xFD, 0x6C,
+	0x8F, 0xDD, 0xF5, 0x91, 0x77, 0x23, 0x1A, 0x71, 0xE5, 0x03, 0x55, 0x23, 0xA2, 0x50, 0x2B, 0x8C,
+	0xD4, 0x89, 0x7A, 0x95, 0x8B, 0xB9, 0x67, 0x15, 0x01, 0xBA, 0x02, 0x59, 0x65, 0x94, 0x69, 0xDB,
+	0xE6, 0xB3, 0xE5, 0x2C, 0xCF, 0x9A, 0x54, 0x9A, 0xE4, 0x91, 0x33, 0x0A, 0x4B, 0x97, 0x42, 0x89,
+	0x69, 0x87, 0x38, 0x87, 0x66, 0xD9, 0x2E, 0x1E, 0x7F, 0x3C, 0x5F, 0x7E, 0xF2, 0xFE, 0xE5, 0xE2,
+	0xA3, 0xF7, 0x8F, 0xDB, 0x67, 0x4F, 0x5E, 0x58, 0xB0, 0xD6, 0x03, 0x80, 0xF5, 0xDA, 0x02, 0x39,
+	0x7F, 0xE5, 0xB1, 0x1C, 0x7C, 0xCF, 0x1B, 0xEF, 0x44, 0xDF, 0xF6, 0x4C, 0x1D, 0xFE, 0x2C, 0x1A,
+	0x94, 0xA0, 0x13, 0x3B, 0x8A, 0x47, 0x9A, 0xB9, 0xB4, 0x0B, 0xC8, 0xCE, 0x20, 0x83, 0xFB, 0x47,
+	0x05, 0x60, 0x1C, 0xF6, 0x0F, 0xF6, 0x47, 0x07, 0xB7, 0xAF, 0xFB, 0x9D, 0x9D, 0x1D, 0xAA, 0x47,
+	0x63, 0xD4, 0x13, 0x97, 0xAB, 0x09, 0x32, 0xF9, 0x50, 0x0A, 0xC6, 0xD5, 0xDE, 0x64, 0xB2, 0x7F,
+	0xFB, 0xC6, 0xDE, 0xE4, 0xE0, 0xD6, 0xB8, 0x9A, 0x7C, 0x27, 0xF8, 0xFA, 0x86, 0xF7, 0x81, 0x98,
+	0x59, 0x88, 0x07, 0xE2, 0x91, 0x86, 0xFD, 0x22, 0x08, 0x91, 0x50, 0x8E, 0x05, 0x5D, 0xD3, 0xCC,
+	0x2E, 0xD7, 0x8B, 0xA3, 0xA7, 0xCB, 0xE5, 0xE9, 0x69, 0xB7, 0x5E, 0xCE, 0x91, 0x62, 0x93, 0x20,
+	0x65, 0xED, 0x20, 0x8D, 0x2F, 0xA5, 0xA5, 0xD8, 0x36, 0x71, 0x76, 0xD1, 0xB5, 0xD3, 0x93, 0x75,
+	0x9C, 0x9E, 0x5E, 0x95, 0xA6, 0xB9, 0x1C, 0x64, 0xDD, 0x72, 0xB0, 0xF3, 0xEC, 0x67, 0xE1, 0xC3,
+	0xA1, 0x42, 0x33, 0xB8, 0x86, 0xCA, 0xD7, 0x7D, 0x7F, 0xFE, 0xA1, 0x83, 0xFA, 0x6A, 0x7F, 0xDC,
+	0x7B, 0x7F, 0x3A, 0x0B, 0xEC, 0xCE, 0x20, 0xD0, 0x13, 0xA8, 0x85, 0xE4, 0xEE, 0x60, 0x11, 0xBF,
+	0x33, 0x38, 0xBA, 0xAB, 0x01, 0x66, 0xAA, 0x02, 0x30, 0x71, 0xFB, 0xFB, 0xBB, 0xF5, 0xBF, 0xFA,
+	0xEE, 0x7E, 0xF5, 0xEE, 0xF7, 0x77, 0xC2, 0xB5, 0x1F, 0x04, 0x37, 0x7E, 0xC7, 0x33, 0x93, 0x23,
+	0x29, 0xA6, 0x24, 0x60, 0x8D, 0x8D, 0xC2, 0x30, 0xB4, 0x10, 0xE6, 0x14, 0x19, 0xAB, 0x75, 0xBE,
+	0x38, 0x5E, 0xB5, 0x0F, 0x1E, 0xCE, 0x9B, 0x67, 0x4F, 0xDA, 0x66, 0x76, 0x5C, 0x72, 0xEE, 0xE2,
+	0xE0, 0xB8, 0x6C, 0x06, 0x47, 0x66, 0xB7, 0x39, 0x5A, 0xF5, 0x64, 0x89, 0x16, 0xBC, 0x2B, 0x6C,
+	0x45, 0x60, 0x1A, 0xFB, 0x7C, 0x31, 0xF8, 0xDA, 0xEF, 0xF5, 0xE3, 0x0F, 0x15, 0x54, 0x1A, 0x04,
+	0x85, 0x2C, 0x30, 0x7D, 0x50, 0x2B, 0x0B, 0xDC, 0x9E, 0x05, 0xB1, 0x32, 0x5C, 0x48, 0x9F, 0xD5,
+	0x15, 0xB6, 0xC2, 0x74, 0x23, 0xFB, 0x33, 0x80, 0x50, 0xBB, 0xEB, 0xFB, 0x23, 0xDE, 0xBD, 0xE6,
+	0xDD, 0xE8, 0x26, 0x53, 0xD8, 0x61, 0x25, 0x3B, 0x14, 0x07, 0x53, 0x98, 0xED, 0x5B, 0x2E, 0x22,
+	0x16, 0x10, 0x29, 0x95, 0x49, 0xDA, 0x24, 0xAB, 0x45, 0xCC, 0x17, 0x17, 0x5D, 0x9E, 0xCF, 0xBA,
+	0x54, 0xDA, 0x38, 0xB8, 0x1E, 0xFA, 0x2A, 0xBE, 0xC3, 0x56, 0xE0, 0x44, 0x41, 0xD5, 0xDB, 0xA0,
+	0x0E, 0x33, 0x35, 0xD9, 0xF7, 0xAC, 0x7E, 0x1F, 0x77, 0xE7, 0xDB, 0x16, 0xD4, 0x57, 0x3F, 0x78,
+	0x90, 0xA5, 0xBD, 0xEB, 0x46, 0x1F, 0xE4, 0x3E, 0x80, 0xD5, 0xE0, 0x51, 0x0F, 0x8A, 0xAD, 0x7A,
+	0x80, 0xC0, 0xE0, 0xC1, 0x3D, 0x3E, 0x84, 0xDB, 0xF0, 0x2B, 0x55, 0x79, 0xFE, 0xB5, 0x79, 0xF5,
+	0xCB, 0x2C, 0xFA, 0x38, 0xE0, 0xAA, 0xE4, 0x57, 0x82, 0xD5, 0x3F, 0xBA, 0xC1, 0x5D, 0xBA, 0x1A,
+	0x00, 0xC3, 0x7E, 0x6F, 0x77, 0xE7, 0xDB, 0x1E, 0x54, 0x60, 0xC3, 0x11, 0xDB, 0xCC, 0x8B, 0x87,
+	0xD9, 0x38, 0x1E, 0x64, 0xEA, 0x30, 0xC0, 0x61, 0x10, 0x64, 0x87, 0x97, 0x1D, 0xD3, 0x78, 0x8B,
+	0xFC, 0x02, 0xBD, 0x12, 0xD4, 0x21, 0x90, 0x2E, 0x0E, 0xDE, 0x04, 0x79, 0x10, 0xD4, 0x38, 0xD8,
+	0x69, 0xF6, 0x8C, 0xFA, 0x66, 0xF0, 0x18, 0xD2, 0x0A, 0x87, 0x23, 0xBE, 0xFC, 0x87, 0x0C, 0xE8,
+	0xDB, 0x16, 0xD4, 0x2F, 0xBA, 0x77, 0xC3, 0x20, 0x2B, 0xC7, 0x83, 0xE0, 0xD6, 0x83, 0xEC, 0x0B,
+	0xF6, 0xF5, 0x30, 0xDC, 0x0A, 0x0D, 0xFE, 0xFD, 0x17, 0x99, 0xB1, 0xF7, 0xC1, 0x8F, 0x83, 0x42,
+	0x86, 0x07, 0xD3, 0xB0, 0x6E, 0x70, 0xFC, 0x0E, 0x8F, 0xE2, 0xDF, 0xF4, 0xF5, 0xF2, 0xB6, 0xBC,
+	0x70, 0x6F, 0x73, 0x50, 0x31, 0x38, 0x42, 0xC3, 0x20, 0x2B, 0x87, 0x41, 0x15, 0xFB, 0xFA, 0x64,
+	0x90, 0x91, 0xC3, 0x2A, 0xBB, 0x3F, 0x96, 0x87, 0x08, 0x48, 0x7A, 0x4D, 0xA6, 0xF2, 0x2B, 0xB3,
+	0xEB, 0x38, 0x98, 0x59, 0x0F, 0xB3, 0x36, 0x0F, 0x32, 0x32, 0xBF, 0x0D, 0x99, 0xF9, 0xC7, 0x16,
+	0xD4, 0x57, 0x9F, 0x23, 0x0D, 0x32, 0x77, 0x18, 0xD4, 0xF1, 0x2B, 0xC7, 0xEC, 0xF0, 0x0D, 0x41,
+	0x83, 0x20, 0xF0, 0x20, 0xC8, 0x5F, 0x04, 0xB9, 0x94, 0xD7, 0x14, 0x47, 0xDD, 0x2B, 0xC7, 0xF6,
+	0xAB, 0xFF, 0x06, 0xFF, 0x12, 0xD4, 0xDF, 0xFD, 0x39, 0x57, 0x83, 0xE7, 0xEE, 0x06, 0xF7, 0x31,
+	0xF0, 0xC5, 0x0E, 0x44, 0x05, 0x2F, 0x83, 0xD0, 0xE5, 0x35, 0xD9, 0x55, 0x5E, 0xC9, 0xC2, 0xF4,
+	0x75, 0xED, 0x38, 0xFF, 0x25, 0xA8, 0x6F, 0x3E, 0xC8, 0xF8, 0xA2, 0xCF, 0x09, 0x2F, 0x29, 0xE1,
+	0xBF, 0xF1, 0xD4, 0xAB, 0x7C, 0x41, 0x21, 0x25, 0x7F, 0x6C, 0x01, 0xFD, 0x63, 0x0E, 0xEA, 0x9B,
+	0xFC, 0x5E, 0x3C, 0x08, 0xCA, 0x40, 0x73, 0x0C, 0xF2, 0x05, 0x77, 0xEB, 0x1F, 0x65, 0xF0, 0x5E,
+	0xF7, 0xF1, 0xFF, 0x01, 0xC6, 0x53, 0xD0, 0xD4, 0x45, 0x33, 0xCF, 0x2B, 0x00, 0x00, 0x00, 0x00,
+	0x49, 0x45, 0x4E, 0x44, 0xAE, 0x42, 0x60, 0x82,
+};
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/LCD_shield_config/LcdCfg/LcdCfg.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,48 @@
+#include "LcdCfg.h"
+
+#if (LCD_VDC5_CH0_PANEL == LCD_CH0_PANEL_VKLCD70RT)
+const DisplayBase::lcd_config_t LcdCfgTbl = {
+      DisplayBase::LCD_TYPE_LVDS                                                    /* lcd_type             */
+    , LCD_INPUT_CLOCK                                                               /* intputClock          */
+    , LCD_OUTPUT_CLOCK                                                              /* outputClock          */
+    , DisplayBase::LCD_OUTFORMAT_RGB888                                             /* lcd_outformat        */
+    , DisplayBase::EDGE_RISING                                                      /* lcd_edge             */
+    , (LCD_PIXEL_WIDTH  + LCD_H_FRONT_PORCH + LCD_H_BACK_PORCH + LCD_H_SYNC_WIDTH)  /* h_toatal_period      */
+    , (LCD_PIXEL_HEIGHT + LCD_V_FRONT_PORCH + LCD_V_BACK_PORCH + LCD_V_SYNC_WIDTH)  /* v_toatal_period      */
+    , LCD_PIXEL_WIDTH                                                               /* h_disp_widht         */
+    , LCD_PIXEL_HEIGHT                                                              /* v_disp_widht         */
+    , LCD_H_BACK_PORCH                                                              /* h_back_porch         */
+    , LCD_V_BACK_PORCH                                                              /* v_back_porch         */
+    , DisplayBase::LCD_TCON_PIN_NON                                                 /* h_sync_port          */
+    , DisplayBase::SIG_POL_NOT_INVERTED                                             /* h_sync_port_polarity */
+    , LCD_H_SYNC_WIDTH                                                              /* h_sync_width         */
+    , DisplayBase::LCD_TCON_PIN_NON                                                 /* v_sync_port          */
+    , DisplayBase::SIG_POL_NOT_INVERTED                                             /* v_sync_port_polarity */
+    , LCD_V_SYNC_WIDTH                                                              /* v_sync_width         */
+    , DisplayBase::LCD_TCON_PIN_0                                                   /* de_port              */
+    , DisplayBase::SIG_POL_NOT_INVERTED                                             /* de_port_polarity     */
+};
+#else
+const DisplayBase::lcd_config_t LcdCfgTbl = {
+      DisplayBase::LCD_TYPE_PARALLEL_RGB                                            /* lcd_type             */
+    , LCD_INPUT_CLOCK                                                               /* intputClock          */
+    , LCD_OUTPUT_CLOCK                                                              /* outputClock          */
+    , DisplayBase::LCD_OUTFORMAT_RGB565                                             /* lcd_outformat        */
+    , DisplayBase::EDGE_RISING                                                      /* lcd_edge             */
+    , (LCD_PIXEL_WIDTH  + LCD_H_FRONT_PORCH + LCD_H_BACK_PORCH + LCD_H_SYNC_WIDTH)  /* h_toatal_period      */
+    , (LCD_PIXEL_HEIGHT + LCD_V_FRONT_PORCH + LCD_V_BACK_PORCH + LCD_V_SYNC_WIDTH)  /* v_toatal_period      */
+    , LCD_PIXEL_WIDTH                                                               /* h_disp_widht         */
+    , LCD_PIXEL_HEIGHT                                                              /* v_disp_widht         */
+    , LCD_H_BACK_PORCH                                                              /* h_back_porch         */
+    , LCD_V_BACK_PORCH                                                              /* v_back_porch         */
+    , DisplayBase::LCD_TCON_PIN_NON                                                 /* h_sync_port          */
+    , DisplayBase::SIG_POL_NOT_INVERTED                                             /* h_sync_port_polarity */
+    , LCD_H_SYNC_WIDTH                                                              /* h_sync_width         */
+    , DisplayBase::LCD_TCON_PIN_NON                                                 /* v_sync_port          */
+    , DisplayBase::SIG_POL_NOT_INVERTED                                             /* v_sync_port_polarity */
+    , LCD_V_SYNC_WIDTH                                                              /* v_sync_width         */
+    , DisplayBase::LCD_TCON_PIN_0                                                   /* de_port              */
+    , DisplayBase::SIG_POL_NOT_INVERTED                                             /* de_port_polarity     */
+};
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/LCD_shield_config/LcdCfg/LcdCfg.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,27 @@
+
+#ifndef LCD_CFG_H
+#define LCD_CFG_H
+
+#include "DisplayBace.h"
+#include "lcd_panel.h"
+
+/* LCD Parameter */
+#define LCD_INPUT_CLOCK                     (66.67)
+#if (LCD_VDC5_CH0_PANEL == LCD_CH0_PANEL_VKLCD70RT)
+  #define LCD_OUTPUT_CLOCK                  (51.2f)
+#else
+  #define LCD_OUTPUT_CLOCK                  (9.52f)
+#endif
+#define LCD_PIXEL_WIDTH                     LCD_CH0_DISP_HW
+#define LCD_PIXEL_HEIGHT                    LCD_CH0_DISP_VW
+#define LCD_H_BACK_PORCH                    (LCD_CH0_SIG_FH - (LCD_CH0_DISP_HW + LCD_CH0_DISP_HS))
+#define LCD_H_FRONT_PORCH                   LCD_CH0_DISP_HS
+#define LCD_H_SYNC_WIDTH                    (0u)
+#define LCD_V_BACK_PORCH                    (LCD_CH0_SIG_FV - (LCD_CH0_DISP_VW + LCD_CH0_DISP_VS))
+#define LCD_V_FRONT_PORCH                   LCD_CH0_DISP_VS
+#define LCD_V_SYNC_WIDTH                    (0u)
+
+extern const DisplayBase::lcd_config_t LcdCfgTbl;
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/LCD_shield_config/TouchCfg/Touch.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,348 @@
+#include "Touch.h"
+
+const touch_config_t  STMPE811_cfg = {
+	"STMPE811", LCD_VDC5_CH0_PANEL, RESISTIVE,
+    {I_2_C, TPIIC_SDA, TPIIC_SCL, NC, NC, NC, NC, 100000},
+    {INT_ON_EDGE, FALLING_OR_ACTIVE_LO, TPIRQ_PIN}
+};
+
+bool	Touch::new_data;
+
+
+/**************************************************************************//**
+ * @brief       Constructor of the Touch class
+ * @param[in]   pointer to Config structure (touch_config_t)
+******************************************************************************/
+//SPI(tp_cfg->interface.mosi, tp_cfg->interface.miso, tp_cfg->interface.sclk, tp_cfg->interface.ssel),
+Touch::Touch( const touch_config_t * tp_cfg ) : I2C(tp_cfg->interface.sda, tp_cfg->interface.scl), InterruptIn(tp_cfg->activity_irq.pin)
+{
+	if(tp_cfg == NULL)
+		touch_cfg = &STMPE811_cfg;
+	else
+		touch_cfg = tp_cfg;
+
+	x = y = z = 0;	  adc_x = adc_y = adc_z = 0;
+	xyz_data = screen_data; adc_data = raw_data;
+	last_xyz_idx = FIFO_DEPTH;
+	new_data = false;
+	calib.data.flag = 0;
+
+} /* End of constructor */
+
+
+/**************************************************************************//**
+ * @brief       Touch controller initialization
+ * @retval      error code
+******************************************************************************/
+Touch::init_err_t Touch::Init( void )
+{
+	init_err_t tp_err;
+
+	if(touch_cfg->type == RESISTIVE)
+	{
+		tp_err = Clb_Setup();
+
+		if(tp_err != TOUCH_OK)
+			return tp_err;
+	}
+
+	if(touch_cfg->interface.type == I_2_C)
+		I2C::frequency(touch_cfg->interface.freq);
+	//else
+		//SPI::frequency(touch_cfg->interface.freq);
+
+	tp_err = Drv_Setup();
+
+	if(tp_err != TOUCH_OK)
+		return tp_err;
+
+	if(touch_cfg->activity_irq.polarity == FALLING_OR_ACTIVE_LO)
+	{
+		rise(NULL);
+		fall(&Irq_Alert);
+	}
+	else
+	{
+		rise(&Irq_Alert);
+		fall(NULL);
+	}
+
+	if(tp_err == TOUCH_OK)
+		enable_irq();
+
+	return tp_err;
+} /* End of method Init() */
+
+
+/**************************************************************************//**
+ * @brief       Set Calibration data
+ * @retval      error code
+******************************************************************************/
+Touch::init_err_t Touch::Clb_Setup()
+{
+	if(touch_cfg->name == "STMPE811")
+	{
+		#ifndef __USE_DEFAULT_CALIBRATION_DATA__
+			// extract calibration info from lcdpanel EEPROM
+			char adr = 0;
+
+			if( (touch_cfg->interface.sda == EEIIC_SDA) || (touch_cfg->interface.scl == EEIIC_SCL))
+			{	// EEPROM is on the same I2C channel no need to initialize a new one !
+				if(I2C::write(EE_CALIB_DEVICE_ADDR, (const char *)&adr, 1, true) != 0)
+					return TOUCH_INIT_ERR;
+				if(I2C::read(EE_CALIB_DEVICE_ADDR, (char*)calib.KX08, sizeof(calib.KX08)) != 0)
+					return TOUCH_INIT_ERR;
+			}
+			else
+			{
+				I2C clb_eeprom(EEIIC_SDA, EEIIC_SCL);
+
+				clb_eeprom.frequency(100000);
+				if(clb_eeprom.write(EE_CALIB_DEVICE_ADDR, (const char *)&adr, 1, true) != 0)
+					return TOUCH_INIT_ERR;
+				if(clb_eeprom.read(EE_CALIB_DEVICE_ADDR, (char*)calib.KX08, sizeof(calib.KX08)) != 0)
+					return TOUCH_INIT_ERR;
+			}
+		#endif
+
+		if(calib.data.flag != 1)
+		{	// load default calibration info
+			unsigned char clb[] = {TPCALIBRATION_DATA};
+			memcpy(calib.KX08, clb, sizeof(clb));
+		}
+
+		return TOUCH_OK;
+	}
+	else
+		return TOUCH_UNSUPP_ERR;
+} /* End of method Clb_Setup() */
+
+
+/**************************************************************************//**
+ * @brief       Set Touch Controller settings
+ * @retval      error code
+******************************************************************************/
+Touch::init_err_t Touch::Drv_Setup()
+{
+	if(touch_cfg->name == "STMPE811")
+	{
+		unsigned char i, initdata[][2] = { INIT_DATA };
+
+		for(i=0; i<(sizeof(initdata)>>1); i++)
+		{
+			if(initdata[i][0] == INT_CTRL)
+			{	// reconfigure interrupt if needed
+				initdata[i][1] = 0x01;
+				initdata[i][1] |= (touch_cfg->activity_irq.trigger == INT_ON_EDGE)? 0x02 : 0x00;
+				initdata[i][1] |= (touch_cfg->activity_irq.polarity == RISING_OR_ACTIVE_HI)? 0x04 : 0x00;
+			}
+
+			if ((I2C::write(STMPE811_DEVICE_ADDR, (const char *)&initdata[i][0], 2)) != 0)
+				return TOUCH_INIT_ERR;
+
+			while (I2C::write(STMPE811_DEVICE_ADDR, (const char *)initdata, 0) != 0);  // ACK polling
+		}
+
+		return TOUCH_OK;
+	}
+	else
+		return TOUCH_UNSUPP_ERR;
+}
+
+
+/**************************************************************************//**
+ * @brief       Get one sample of data
+ * @param[in]   * raw	: pointer to ring buffer to store the samples
+******************************************************************************/
+void Touch::Get_Data( unsigned long long * raw )
+{
+	if(touch_cfg->name == "STMPE811")
+	{
+		int idx = last_xyz_idx;
+		unsigned char  i, packed_sample[16];
+		unsigned short raw_x, raw_y;
+		unsigned char  raw_z;
+
+		i = TSC_DATA_FIFO;
+		I2C::write(STMPE811_DEVICE_ADDR, (const char *)&i, 1, true);
+		I2C::read(STMPE811_DEVICE_ADDR, (char *)packed_sample, sizeof(packed_sample));
+		for(i=0; i<4; i++)
+		{
+			raw_x = (unsigned short)((packed_sample[(i*4)+0]<<4) | (packed_sample[(i*4)+1]>>4));
+			raw_y = (unsigned short)(((0x0F & packed_sample[(i*4)+1])<<8) | packed_sample[(i*4)+2]);
+			raw_z = packed_sample[(i*4)+3];
+
+			idx = ((idx+1) < FIFO_DEPTH)? idx+1 : 0;
+			raw[idx] = (unsigned long long)((raw_z<<32) + (raw_y<<16) + raw_x);
+		}
+	}
+} /* End of method Get_Data() */
+
+
+/**************************************************************************//**
+ * @brief       Get all available samples of data
+ * @param[in]   * raw	: pointer to ring buffer to store the samples
+ * @retval      		  samples count
+******************************************************************************/
+int Touch::Get_Fifo( unsigned long long * raw )
+{
+	if(touch_cfg->name == "STMPE811")
+	{
+	  int idx = last_xyz_idx;
+	  unsigned char packets;
+
+	  packets = FIFO_SIZE;
+	  I2C::write(STMPE811_DEVICE_ADDR, (const char *)&packets, 1, true);
+	  packets = 0;
+	  I2C::read(STMPE811_DEVICE_ADDR, (char *)&packets, 1);
+	  if(packets)
+	  {
+		unsigned char  packed_sample[FIFO_DEPTH*4];
+		unsigned short raw_x, raw_y, i;
+		unsigned char  raw_z;
+
+		raw_z = TSC_DATA_FIFO;
+		I2C::write(STMPE811_DEVICE_ADDR, (const char *)&raw_z, 1, true);
+		I2C::read(STMPE811_DEVICE_ADDR, (char *)packed_sample, packets*4);
+
+	    for(i=0; i<packets; i++)
+	    {
+	      raw_x = (unsigned short)((packed_sample[(i*4)+0]<<4) | (packed_sample[(i*4)+1]>>4));
+	      raw_y = (unsigned short)(((0x0F & packed_sample[(i*4)+1])<<8) | packed_sample[(i*4)+2]);
+	      raw_z = packed_sample[(i*4)+3];
+
+	      idx = ((idx+1) < FIFO_DEPTH)? idx+1 : 0;
+	      raw[idx] = (raw_z<<32) + (raw_y<<16) + raw_x;
+	    }
+
+	    return packets;
+	  }
+	  return 0;
+	}
+	else
+		return 0;
+} /* End of method Get_Fifo() */
+
+
+/**************************************************************************//**
+ * @brief       Coordinates Transfer function
+ * @param[in]   points		: number of samples which have to become meaningful
+******************************************************************************/
+void Touch::Get_XYZ( int points)
+{
+	if(touch_cfg->name == "STMPE811")
+	{
+		int i, idx;
+
+		for(i=0; i<points; i++)
+		{
+			idx = ((last_xyz_idx+1) < FIFO_DEPTH)? last_xyz_idx+1 : 0;
+			screen_data[idx].axis.x = (signed short)(calib.data.KX1*((signed short)raw_data[idx].axis.x)+calib.data.KX2*((signed short)raw_data[idx].axis.y)+calib.data.KX3+0.5);
+			screen_data[idx].axis.y = (signed short)(calib.data.KY1*((signed short)raw_data[idx].axis.x)+calib.data.KY2*((signed short)raw_data[idx].axis.y)+calib.data.KY3+0.5);
+			//screen_data[idx].axis.z = 0;
+			last_xyz_idx = idx;
+			//printf("\r\n REC: idx-> %d", idx);
+			//printf("\r\n TH: x-> %d, y-> %d, dots-> %d", screen_data[idx].axis.x, screen_data[idx].axis.y, idx);
+		}
+
+		x = screen_data[last_xyz_idx].axis.x; adc_x = raw_data[last_xyz_idx].axis.x;
+		y = screen_data[last_xyz_idx].axis.y; adc_y = raw_data[last_xyz_idx].axis.y;
+		//z = screen_data[last_xyz_idx].axis.z; adc_z = raw_data[last_xyz_idx].axis.z;
+		//printf("\r\n TH: x-> %d, y-> %d, dots-> %d", x, y, last_xyz_idx);
+
+	}
+} /* End of method Get_XYZ() */
+
+
+/**************************************************************************//**
+ * @brief       IRQ interrupt handler : indicates "New Data available" which activates i2c data transfer in Handle_touch()
+******************************************************************************/
+void Touch::Irq_Alert( void ) {	new_data = true; } /* End of method Irq_Alert() */
+
+
+/**************************************************************************//**
+ * @brief       Get index of the last sample in the ring buffer
+ * @retval      idx
+******************************************************************************/
+int Touch::Get_Last_Idx( void ) { return last_xyz_idx; }
+
+
+/**************************************************************************//**
+ * @brief       Pull the new samples if new data is available
+ * @param[in]   * pts 				: pointer to a variable to put the count of the new samples
+ * @retval      Status of the pen 	(Stylus position up/down)
+******************************************************************************/
+bool Touch::Handle_touch( unsigned char *pts )
+{
+	static bool PenDown = false;
+	unsigned char TP_IntStat = 0, rec[2];
+	int dots = 0;
+
+	*pts=0;
+
+ if(new_data)
+ {
+	TP_IntStat = INT_STA;
+	I2C::write(STMPE811_DEVICE_ADDR, (const char *)&TP_IntStat, 1, true);
+	TP_IntStat = 0;
+	I2C::read(STMPE811_DEVICE_ADDR, (char *)&TP_IntStat, 1);
+
+	if(TP_IntStat & INT_FIFO_TH)
+	{
+		Get_Data(&raw_data[0].dot);
+		Get_XYZ(4);
+
+		*pts = 4;
+
+		//Data = 1;
+		//SET_TP_STATE(TP_FLAG_PEN_DATA_TH);
+		//printf("\r\n TH: x-> %d, y-> %d", screen_data[3].axis.x, screen_data[3].axis.y);
+	}
+
+	if(TP_IntStat & INT_TOUCH_DET)
+	{
+		dots = Get_Fifo(&raw_data[0].dot);
+		if(dots)
+		{
+			Get_XYZ(dots);
+		    //Data = 1;
+		    //CLR_TP_STATE(TP_FLAG_PEN_DATA_TH); //SET_TP_STATE(TP_FLAG_DATA_READY);
+		    //printf("\r\n Touch Sample: x-> %d, y-> %d", screen_data[v-1].axis.x, screen_data[v-1].axis.y);
+		}
+		*pts = dots;
+
+		PenDown = (PenDown)? false : true;
+	}
+
+	if(TP_IntStat & INT_FIFO_OFLOW)
+	{
+		rec[0] = FIFO_STA;
+		rec[1] = 0x01;		// Clear FIFO
+		I2C::write(STMPE811_DEVICE_ADDR, (const char *)rec, 2);
+
+		rec[1] = 0x00;		// Reset FIFO
+		I2C::write(STMPE811_DEVICE_ADDR, (const char *)rec, 2);
+	}
+
+	rec[0] = INT_STA;
+	rec[1] = TP_IntStat;
+	I2C::write(STMPE811_DEVICE_ADDR, (const char *)rec, 2);
+
+	new_data = false;
+ }
+
+  return PenDown;
+}
+
+/**************************************************************************//**
+ * @brief       Destructor of the Touch class
+******************************************************************************/
+Touch::~Touch( )
+{
+	touch_cfg = NULL;
+	xyz_data = NULL;
+	adc_data = NULL;
+}
+
+/* End of file */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/LCD_shield_config/TouchCfg/Touch.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,161 @@
+/**************************************************************************//**
+ * @file         Touch.h
+ * @brief        Touch driver class for VK-LCD panels
+******************************************************************************/
+
+#ifndef MBED_TOUCH_H
+#define MBED_TOUCH_H
+
+#include "mbed.h"
+#include <string>
+#include "stmpe811iic.h"
+
+    /*! @enum Touch_type_t
+    	@brief Type of the touch controller
+    */
+    typedef enum {
+    	RESISTIVE = 0, /*!< Resistive */
+    	CAPACITIVE     /*!< Capacitive */
+    } Touch_type_t;
+
+    /*! @enum Touch_interface_type_t
+        @brief Communication interface
+    */
+    typedef enum {
+    	I_2_C = 0, 		 /*!< I2C */
+    	S_P_I     		 /*!< SPI */
+    } Touch_communication_type_t;
+
+    /*! @enum IRQ_trigger_t
+    	@brief Type of the interrupt
+    */
+    typedef enum {
+    	INT_ON_EDGE  = 0,   /*!< generate INT on front change */
+    	INT_ON_LEVEL        /*!< generate INT on active level */
+    } IRQ_trigger_t;
+
+    /*! @enum IRQ_polarity_t
+        @brief Edge of a signal
+    */
+    typedef enum {
+    	RISING_OR_ACTIVE_HI  = 0, /*!< Rising edge/HI level     */
+    	FALLING_OR_ACTIVE_LO      /*!< Falling edge/LOW level   */
+    } IRQ_polarity_t;
+
+    /*! @struct touch_config_t
+    	@brief Touch Config structure
+    */
+    typedef struct {
+    	string			name;				/*!< Name of the Touch driver */
+        int				screen;				/*!< reserved				  */
+        Touch_type_t	type;				/*!< Resistive or Capacitive  */
+        struct {							/*!< I2C or SPI & the pins of selected periphery */
+        	Touch_communication_type_t type;
+        	PinName sda;
+        	PinName scl;
+        	PinName mosi;
+        	PinName miso;
+        	PinName sclk;
+        	PinName ssel;
+        	int 	freq;
+        }interface;
+        struct {							/*!< IRQ : front and pin of selected periphery */
+        	IRQ_trigger_t	trigger;
+            IRQ_polarity_t	polarity;
+            PinName			pin;
+        }activity_irq;
+    }touch_config_t;
+
+extern const touch_config_t STMPE811_cfg;
+
+/*! @class Touch
+ *  @brief Touch driver class for VK-LCD panels
+ */
+
+class Touch : public I2C, public InterruptIn
+{
+public:
+    /*! @enum Init_err_t
+        @brief Error codes
+     */
+    typedef enum {
+        TOUCH_OK = 0,                   /*!< Initialization successful      */
+        TOUCH_INIT_ERR = -1,           	/*!< Communication interface err while configuring driver */
+		TOUCH_UNSUPP_ERR = -2,			/*!< Unsupported driver */
+        TOUCH_ERR = -3,         		/*!< unknown error */
+    } init_err_t;
+
+    /** Constructor method of Touch object
+    */
+    Touch( const touch_config_t * tp_cfg = &STMPE811_cfg );
+
+    /** Destructor method of Touch object
+    */
+    virtual ~Touch( void );
+
+    /** Touch controller initialization
+     *  @retval       Error code
+     */
+    init_err_t Init( void );
+
+    /** New Data available
+     */
+    static void Irq_Alert( void );
+
+    /** Set Calibration data (raw data interpretation)
+     *  @retval       Error code
+     */
+    virtual init_err_t Clb_Setup(void);
+
+    /** Set Touch Controller settings
+    *  @retval       Error code
+    */
+    virtual init_err_t Drv_Setup(void);
+
+    /** Get one sample of data
+     *  @param[in]   raw: pointer to ring buffer to store the samples
+     */
+    virtual void Get_Data( unsigned long long * raw );
+
+    /** Get all available samples of data
+     *  @param[in]   raw: pointer to ring buffer to store the samples
+     *  @retval           samples count
+     */
+    virtual int Get_Fifo( unsigned long long * raw );
+
+    /** Transfer function (from raw coordinates to screen coordinates)
+     *  @param[in]	 points : number of samples to transfer
+     */
+    virtual void Get_XYZ( int points );
+
+    /** Pull the new samples if new data is available
+     *  @param[in]   pts: pointer to a variable to put the count of the new samples
+     *  @retval       	  Status of the pen => up:false;  down:true
+     */
+    bool Handle_touch( unsigned char *pts );
+
+    /** Get index of the last sample in the ring buffer
+     */
+    int Get_Last_Idx( void );
+
+    short x;
+	short y;
+	float z;
+	const touch_screen_data_t *xyz_data;
+
+	unsigned short adc_x;
+	unsigned short adc_y;
+	unsigned short adc_z;
+	const touch_raw_data_t *adc_data;
+
+protected:
+    static bool			 new_data;
+    int					 last_xyz_idx;
+    touch_raw_data_t	 raw_data[FIFO_DEPTH];
+    touch_screen_data_t  screen_data[FIFO_DEPTH];
+    const touch_config_t *touch_cfg;
+    touch_calib_data_t	 calib;
+};
+
+#endif /* MBED_TOUCH_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/LCD_shield_config/TouchCfg/stmpe811iic.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,189 @@
+/*******************************************************************************
+
+*******************************************************************************/
+/******************************************************************************
+* File Name    : tpiic.h
+* Description  : TPIIC header
+******************************************************************************/
+#ifndef STMPE811IIC_H
+#define STMPE811IIC_H
+
+#include "lcd_panel.h"
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#define __USE_DEFAULT_CALIBRATION_DATA__
+
+#define STMPE811_DEVICE_ADDR   (0x82)
+//#define STMPE811_DEVICE_ADDR	(0x88)
+//#define EE_LPC11U35_DEVICE_ADDR (0xA0)
+
+#define TPIIC_CH      	3
+#define TPIIC_SCL		P1_6
+#define TPIIC_SDA		P1_7
+
+#if  (LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_VKLCD70RT)
+  #define TPIRQ_CH      1
+  #define TPIRQ_PIN     P7_8
+
+  #define EEIIC_CH	3
+  #define EEIIC_SCL	P1_6
+  #define EEIIC_SDA	P1_7
+  #define EE_CALIB_DEVICE_ADDR  0xA8
+
+  #define TPCALIBRATION_DATA				0x38,0x00,0x00,0x00,0x01,0x00,0x00,0x00,\
+    0x50,0xb4,0x52,0x38,0xec,0x97,0xd0,0x3f,0xd7,0xfe,0x58,0xc5,0x10,0xb2,0x52,0x3f,\
+	0xde,0x09,0xc6,0x87,0xaa,0x7d,0xbb,0x3e,0x65,0xaa,0xb4,0xd2,0x56,0x04,0xc5,0xbf,\
+	0x02,0xb3,0x33,0x61,0x9b,0x1e,0x34,0xc0,0x88,0x87,0xc3,0x39,0x38,0x7d,0x83,0x40
+#else
+  #define TPIRQ_CH      2
+  #define TPIRQ_PIN     P1_2
+
+  #define EEIIC_CH		0
+  #define EEIIC_SCL		P1_0
+  #define EEIIC_SDA		P1_1
+  #define EE_CALIB_DEVICE_ADDR  0xA8
+
+  #define TPCALIBRATION_DATA				0x38,0x00,0x00,0x00,0x01,0x00,0x00,0x00,\
+	0x66,0x44,0x6c,0xe9,0x11,0xa1,0xbf,0xbf,0x70,0x8f,0x61,0x1c,0x3f,0x5e,0x20,0x3f,\
+	0xad,0x80,0xca,0x76,0x62,0xb9,0x8a,0x3e,0xae,0x95,0xef,0x7e,0xa7,0x8d,0xb2,0xbf,\
+	0x24,0x37,0x82,0x68,0xe6,0xc1,0x7e,0x40,0xf4,0xb6,0xa8,0xe8,0x88,0xa3,0x71,0x40
+#endif
+
+#define FIFO_DEPTH     128      // packets, which means 12bit x + 12bit y +8bit = 32bit for 1 data packet
+
+//sys regs
+#define CHIP_ID        0x00     // 16 R 0x0811 Device identification
+#define ID_VER         0x02     // 8 R 0x01 Revision number 0x01 for engineering sample for final silicon
+#define SYS_CTRL1      0x03     // 8 R/W 0x00 Reset control
+#define SYS_CTRL2      0x04     // 8 R/W 0x0F Clock control
+#define SPI_CFG        0x08     // 8 R/W 0x01 SPI interface configuration
+#define INT_CTRL       0x09     // 8 R/W 0x00 Interrupt control register
+#define INT_EN         0x0A     // 8 R/W 0x00 Interrupt enable register
+#define INT_STA        0x0B     // 8 R 0x10 interrupt status register
+#define GPIO_EN        0x0C     // 8 R/W 0x00 GPIO interrupt enable register
+#define GPIO_INT_STA   0x0D     // 8 R 0x00 GPIO interrupt status register
+#define ADC_INT_EN     0x0E     // 8 R/W 0x00 ADC interrupt enable register
+#define ADC_INT_STA    0x0F     // 8 R 0x00 ADC interrupt status register
+#define GPIO_SET_PIN   0x10     // 8 R/W 0x00 GPIO set pin register
+#define GPIO_CLR_PIN   0x11     // 8 R/W 0x00 GPIO clear pin register
+#define GPIO_MP_STA    0x12     // 8 R/W 0x00 GPIO monitor pin state register
+#define GPIO_DIR       0x13     // 8 R/W 0x00 GPIO direction register
+#define GPIO_ED        0x14     // 8 R/W 0x00 GPIO edge detect register
+#define GPIO_RE        0x15     // 8 R/W 0x00 GPIO rising edge register
+#define GPIO_FE        0x16     // 8 R/W 0x00 GPIO falling edge register
+#define GPIO_AF        0x17     // 8 R/W 0x00 Alternate function register
+
+//ADC regs
+#define ADC_CTRL1      0x20     // 8 R/W 0x9C ADC control
+#define ADC_CTRL2      0x21     // 8 R/W 0x01 ADC control
+#define ADC_CAPT       0x22     // 8 R/W 0xFF To initiate ADC data acquisition
+#define ADC_DATA_CH0   0x30     // 16 R 0x0000 ADC channel 0
+#define ADC_DATA_CH1   0x32     // 16 R 0x0000 ADC channel 1
+#define ADC_DATA_CH2   0x34     // 16 R 0x0000 ADC channel 2
+#define ADC_DATA_CH3   0x36     // 16 R 0x0000 ADC channel 3
+#define ADC_DATA_CH4   0x38     // 16 R 0x0000 ADC channel 4
+#define ADC_DATA_CH5   0x3A     // 16 R 0x0000 ADC channel 5
+#define ADC_DATA_CH6   0x3C     // 16 R 0x0000 ADC channel 6
+#define ADC_DATA_CH7   0x3E     // 16 R 0x0000 ADC channel 7
+
+//touch regs
+#define TSC_CTRL       0x40     // 8 R/W 0x90 4-wire touchscreen controller setup
+#define TSC_CFG        0x41     // 8 R/W 0x00 Touchscreen controller configuration
+#define WDW_TR_X       0x42     // 16 R/W 0x0FFF Window setup for top right X
+#define WDW_TR_Y       0x44     // 16 R/W 0x0FFF Window setup for top right Y
+#define WDW_BL_X       0x46     // 16 R/W 0x0000 Window setup for bottom left X
+#define WDW_BL_Y       0x48     // 16 R/W 0x0000 Window setup for bottom left Y
+#define FIFO_TH        0x4A     // 8 R/W 0x00 FIFO level to generate interrupt
+#define FIFO_STA       0x4B     // 8 R/W 0x20 Current status of FIFO
+#define FIFO_SIZE      0x4C     // 8 R 0x00 Current filled level of FIFO
+#define TSC_DATA_X     0x4D     // 16 R 0x0000 Data port for touchscreen controller data access
+#define TSC_DATA_Y     0x4F     // 16 R 0x0000 Data port for touchscreen controller data access
+#define TSC_DATA_Z     0x51     // 8 R 0x0000 Data port for touchscreen controller data access
+#define TSC_DATA_XYZ   0x52     // 32 R 0x00000000 Data port for touchscreen controller data access
+#define TSC_FRACT_Z    0x56     // 8 0x00
+#define TSC_DATA_AI    0x57     // 8 R 0x00 Data port for touchscreen controller data access AUTO_INCREMENT
+#define TSC_DATA_NAI   0x07     // 8 R 0x00 Data port for touchscreen controller data access NONE_AUTO_INCREMENT
+#define TSC_DATA_FIFO  0xD7     //
+#define TSC_I_DRIVE    0x58     // 8 R/W 0x00
+#define TSC_SHIELD     0x59     // 8 R/W 0x00
+
+//temperature regs
+#define TEMP_CTRL      0x60     // 8 R/W 0x00 Temperature sensor setup
+#define TEMP_DATA      0x61     // 8 R 0x00 Temperature data access port
+#define TEMP_TH        0x62     // 8 R/W 0x00 Threshold for temperature controlled interrupt
+
+//interrupt status & enable bits
+#define INT_GPIO	   0x80
+#define INT_ADC        0x40
+#define INT_TEMP_SENS  0x20
+#define INT_FIFO_EMPTY 0x10
+#define INT_FIFO_FULL  0x08
+#define INT_FIFO_OFLOW 0x04
+#define INT_FIFO_TH    0x02
+#define INT_TOUCH_DET  0x01
+
+//Z axis accuracy
+#define _8_0		   0x00
+#define _7_1		   0x01
+#define _6_2		   0x02
+#define _5_3		   0x03
+#define _4_4		   0x04
+#define _3_5		   0x05
+#define _2_6		   0x06
+#define _1_7		   0x07
+
+#define INIT_DATA											/* {register, value}, ...	*/																				\
+{SYS_CTRL1, 0x02},											/* 0. Reset touchscreen controller	*/																		\
+{SYS_CTRL2, 0x0C},											/* 1. Disable the clock gating for the touchscreen controller and ADC in the SYS_CFG2 register*/			\
+{INT_EN, (INT_FIFO_OFLOW | INT_FIFO_TH | INT_TOUCH_DET)},	/* 2. Configure which interrupts to be outputed */															\
+{ADC_CTRL1, 0x49},											/* 3. Write: register Add = 0x20 ADC_CTRL1, data = 0x49 delay, 2mS */										\
+{ADC_CTRL2, 0x01},											/* 4. Write: register Add = 0x21 ADC_CTRL2, data = 0x01 */													\
+{GPIO_AF,   0x00},											/* 5. Write: register Add = 0x17 GPIO_AF, data = 0x00 */													\
+{TSC_CFG,   0x6C},											/* 6. 5ms panel voltage setting time, 1ms touch detection delay, averaging on every 2-nd sample */			\
+{FIFO_TH,   0x05},											/* 7. Group points reading (if more than 4 points collected generate interrupt) */							\
+{FIFO_STA,  0x01},											/* 8a. Clear FIFO */																						\
+{FIFO_STA,  0x00},											/* 8b. Reset FIFO */																						\
+{TSC_FRACT_Z, _1_7},										/* 9. Choose the appropriate accurency of the measured pressure of the touch 7 fractional bits & 1 int */ 	\
+{TSC_I_DRIVE, 0x00},										/* 10. Write: register Add = 0x58 TSC_I_DRIVE, data = 0x01 */												\
+{TSC_CTRL,  0x01},											/* 11. Configure the operating mode and the window tracking index, start touch detection & data acquisition*/\
+{INT_STA,   0xFF},											/* 12. Clear Interrupt register*/ 																			\
+{INT_CTRL,  0x03},											/* 13. Configure the interrupt signal and enable the interrupts //int-> Edge interrupt -> falling edge*/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+typedef union __CALIB {
+	struct __DATA
+	{
+	 unsigned long len;
+	 unsigned long flag;
+		   double KX1, KY1, KX2, KY2, KX3, KY3;
+	}data;
+	unsigned char KX08[sizeof(struct __DATA)];
+}touch_calib_data_t;
+
+typedef union RAW_SAMPLE__ {
+	struct AXIS__
+    {
+		unsigned short x;
+        unsigned short y;
+        unsigned long  z;
+    }axis;
+    unsigned long long dot;
+}touch_raw_data_t;
+
+typedef union SCREEN_SAMPLE__ {
+	struct AXIS_
+    {
+		short x;
+        short y;
+        float z;
+    }axis;
+    unsigned long long dot;
+}touch_screen_data_t;
+
+#endif  /* STMPE811IIC_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_inc/aioif.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,50 @@
+/******************************************************************************
+ *
+ * $Rev: 891 $
+ * $Date: 2012-12-14 19:28:37 +0900#$
+ *
+ * Description : ITRON support functions for IOIF Asynchronous I/O header file
+ *
+ * (C) Copyright RENESAS ELECTRONICS EUROPE Ltd 2012 All Rights Reserved
+ *****************************************************************************/
+
+#ifndef AIOIF_H
+#define AIOIF_H
+
+#include <ioif_aio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct AHF_S
+{
+    struct aiocb *head;
+    struct aiocb *tail;
+    uint32_t flags;
+    osMutexId semid; /* Source Merge 08-81 */
+    osMutexDef_t* p_cmtx;
+    int32_t saved_int_mask;
+} AHF_S;
+
+#define AHF_CREATESEM   0x1 /* create a semaphore for locking */ /* Source Merge 08-82 */
+#define AHF_LOCKSEM     0x2 /* use a semaphore for locking */    /* Source Merge 08-82 */
+#define AHF_LOCKINT     0x4 /* use interrupts for locking */
+
+/* AHF (Asynchronous Helper Functions */
+int32_t ahf_create (AHF_S * const ahf, const uint32_t f); /* Source Merge 08-83 */
+void ahf_destroy (AHF_S const * const ahf);
+void ahf_addtail (AHF_S * const ahf, struct aiocb * const aio); /* Source Merge 08-04 */
+struct aiocb *ahf_removehead (AHF_S * const ahf);
+int32_t ahf_remove (AHF_S *ahf, struct aiocb *aio);
+struct aiocb *ahf_peekhead (AHF_S * const ahf);
+void ahf_cancelall (AHF_S * const ahf);
+void ahf_complete (AHF_S *ahf, struct aiocb * const aio);
+int32_t ahf_cancel (AHF_S * const ahf, struct aiocb * const aio);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_inc/bsp_drv_cmn.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,46 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          bsp_drv_cmn.h
+* $Rev: 1667 $
+* $Date:: 2015-05-29 14:01:37 +0900#$
+* @brief         BSP Section settings
+******************************************************************************/
+
+#ifndef BSP_DRV_CMN_H
+#define BSP_DRV_CMN_H
+
+#if(1) /* mbed */
+#else  /* not mbed */
+#if defined (__CC_ARM)          /* ARM Compiler */
+
+#pragma arm section code="CODE_RDRV"
+#pragma arm section rodata="CONST_RDRV"
+#pragma arm section rwdata="DATA_RDRV"
+#pragma arm section zidata="BSS_RDRV"
+
+#endif /* __CC_ARM */
+#endif /* end mbed */
+
+#endif /* BSP_DRV_CMN_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_inc/bsp_util.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          bsp_util.h
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* @brief         BSP Utilities
+******************************************************************************/
+
+#ifndef BSP_UTIL_H
+#define BSP_UTIL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+/* ->MISRA 20.9,This header is no problem because it's based upon the standard of the ANSI. */
+#include <stdio.h>
+/* <-MISRA 20.9 */
+#include "bsp_util.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+int32_t R_ExceptionalMode(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _BSP_UTIL_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_inc/dma_if.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,398 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma_if.h
+* $Rev: 1318 $
+* $Date:: 2014-12-04 10:45:12 +0900#$
+* @brief        DMA Driver interface headers
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+#ifndef DMA_IF_H
+#define DMA_IF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+#include "r_errno.h"
+#include "r_typedefs.h"
+#include "ioif_aio.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/*************************************************************************
+ User Includes
+*************************************************************************/
+
+/*************************************************************************
+ Defines
+*************************************************************************/
+
+/* for searching free channel */
+#define DMA_ALLOC_CH  (-1)
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* Number od DMA channel */
+typedef enum
+{
+    DMA_CH_0 = 0,
+    DMA_CH_1 = 1,
+    DMA_CH_2 = 2,
+    DMA_CH_3 = 3,
+    DMA_CH_4 = 4,
+    DMA_CH_5 = 5,
+    DMA_CH_6 = 6,
+    DMA_CH_7 = 7,
+    DMA_CH_8 = 8,
+    DMA_CH_9 = 9,
+    DMA_CH_10 = 10,
+    DMA_CH_11 = 11,
+    DMA_CH_12 = 12,
+    DMA_CH_13 = 13,
+    DMA_CH_14 = 14,
+    DMA_CH_15 = 15,
+    DMA_CH_NUM = 16  /* Number of DMA channel */
+} dma_ch_num_t;
+
+/* Unit Size of DMA transfer */
+typedef enum
+{
+    DMA_UNIT_MIN =(-1),
+    DMA_UNIT_1 = 0,   /* Unit Size of DMA transfer = 1byte */
+    DMA_UNIT_2 = 1,   /* Unit Size of DMA transfer = 2byte */
+    DMA_UNIT_4 = 2,   /* Unit Size of DMA transfer = 4byte */
+    DMA_UNIT_8 = 3,   /* Unit Size of DMA transfer = 8byte */
+    DMA_UNIT_16 = 4,  /* Unit Size of DMA transfer = 16byte */
+    DMA_UNIT_32 = 5,  /* Unit Size of DMA transfer = 32byte */
+    DMA_UNIT_64 = 6,  /* Unit Size of DMA transfer = 64byte */
+    DMA_UNIT_128 = 7, /* Unit Size of DMA transfer = 128byte */
+    DMA_UNIT_MAX = 8
+} dma_unit_size_t;
+
+/* DMA transfer resource */
+typedef enum
+{
+    DMA_RS_OSTIM0     = 0x023,   /* OS Timer ch0 */
+    DMA_RS_OSTIM1     = 0x027,   /* OS Timer ch1 */
+    DMA_RS_TGI0A      = 0x043,   /* Multi Function Timer Pulse Unit2 ch0 */
+    DMA_RS_TGI1A      = 0x047,   /* Multi Function Timer Pulse Unit2 ch1  */
+    DMA_RS_TGI2A      = 0x04B,   /* Multi Function Timer Pulse Unit2 ch2  */
+    DMA_RS_TGI3A      = 0x04F,   /* Multi Function Timer Pulse Unit2 ch3  */
+    DMA_RS_TGI4A      = 0x053,   /* Multi Function Timer Pulse Unit2 ch4  */
+    DMA_RS_TXI0       = 0x061,   /* FIFO Serial Communication Interface ch0 (TX) */
+    DMA_RS_RXI0       = 0x062,   /* FIFO Serial Communication Interface ch0 (RX) */
+    DMA_RS_TXI1       = 0x065,   /* FIFO Serial Communication Interface ch1 (TX) */
+    DMA_RS_RXI1       = 0x066,   /* FIFO Serial Communication Interface ch1 (RX) */
+    DMA_RS_TXI2       = 0x069,   /* FIFO Serial Communication Interface ch2 (TX) */
+    DMA_RS_RXI2       = 0x06A,   /* FIFO Serial Communication Interface ch2 (RX) */
+    DMA_RS_TXI3       = 0x06D,   /* FIFO Serial Communication Interface ch3 (TX) */
+    DMA_RS_RXI3       = 0x06E,   /* FIFO Serial Communication Interface ch3 (RX) */
+    DMA_RS_TXI4       = 0x071,   /* FIFO Serial Communication Interface ch4 (TX) */
+    DMA_RS_RXI4       = 0x072,   /* FIFO Serial Communication Interface ch4 (RX) */
+    DMA_RS_TXI5       = 0x075,   /* FIFO Serial Communication Interface ch5 (TX) */
+    DMA_RS_RXI5       = 0x076,   /* FIFO Serial Communication Interface ch5 (RX) */
+    DMA_RS_TXI6       = 0x079,   /* FIFO Serial Communication Interface ch6 (TX) */
+    DMA_RS_RXI6       = 0x07A,   /* FIFO Serial Communication Interface ch6 (RX) */
+    DMA_RS_TXI7       = 0x07D,   /* FIFO Serial Communication Interface ch7 (TX) */
+    DMA_RS_RXI7       = 0x07E,   /* FIFO Serial Communication Interface ch7 (RX) */
+    DMA_RS_USB0_DMA0  = 0x083,   /* USB Module0 ch0 */
+    DMA_RS_USB0_DMA1  = 0x087,   /* USB Module0 ch1 */
+    DMA_RS_USB1_DMA0  = 0x08B,   /* USB Module1 ch0 */
+    DMA_RS_USB1_DMA1  = 0x08F,   /* USB Module1 ch1 */
+    DMA_RS_ADEND      = 0x093,   /* A/D Converter */
+    DMA_RS_IEBBTD     = 0x0A3,   /* IEBus Controller (Data interrupt) */
+    DMA_RS_IEBBTV     = 0x0A7,   /* IEBus Controller (Vector interrupt) */
+    DMA_RS_IREADY     = 0x0AB,   /* CD-Rom Decoder */
+    DMA_RS_FLDT       = 0x0B3,   /* NAND Memory Controller (Data) */
+    DMA_RS_SDHI_0T    = 0x0C1,   /* SD Host Interface0 (TX) */
+    DMA_RS_SDHI_0R    = 0x0C2,   /* SD Host Interface0 (RX) */
+    DMA_RS_SDHI_1T    = 0x0C5,   /* SD Host Interface1 (RX) */
+    DMA_RS_SDHI_1R    = 0x0C6,   /* SD Host Interface1 (TX) */
+    DMA_RS_MMCT       = 0x0C9,   /* MMC Host Interface (TX) */
+    DMA_RS_MMCR       = 0x0CA,   /* MMC Host Interface (RX) */
+    DMA_RS_SSITXI0    = 0x0E1,   /* SSIF0 (TX) */
+    DMA_RS_SSIRXI0    = 0x0E2,   /* SSIF0 (RX) */
+    DMA_RS_SSITXI1    = 0x0E5,   /* SSIF1 (TX) */
+    DMA_RS_SSIRXI1    = 0x0E6,   /* SSIF1 (RX) */
+    DMA_RS_SSIRTI2    = 0x0EB,   /* SSIF2 (TX) */
+    DMA_RS_SSITXI3    = 0x0ED,   /* SSIF2 (RTX) */
+    DMA_RS_SSIRXI3    = 0x0EE,   /* SSIF3 (TX) */
+    DMA_RS_SSIRTI4    = 0x0F3,   /* SSIF4 (RTX) */
+    DMA_RS_SSITXI5    = 0x0F5,   /* SSIF5 (TX) */
+    DMA_RS_SSIRXI5    = 0x0F6,   /* SSIF5 (RX) */
+    DMA_RS_SCUTXI0    = 0x101,   /* SCUX (FFD0) */
+    DMA_RS_SCURXI0    = 0x102,   /* SCUX (FFU0) */
+    DMA_RS_SCUTXI1    = 0x105,   /* SCUX (FFD1) */
+    DMA_RS_SCURXI1    = 0x106,   /* SCUX (FFU1) */
+    DMA_RS_SCUTXI2    = 0x109,   /* SCUX (FFD2) */
+    DMA_RS_SCURXI2    = 0x10A,   /* SCUX (FFU2) */
+    DMA_RS_SCUTXI3    = 0x10D,   /* SCUX (FFD3) */
+    DMA_RS_SCURXI3    = 0x10E,   /* SCUX (FFU3) */
+    DMA_RS_SPTI0      = 0x121,   /* SPI0 (TX) */
+    DMA_RS_SPRI0      = 0x122,   /* SPI0 (RX) */
+    DMA_RS_SPTI1      = 0x125,   /* SPI1 (TX) */
+    DMA_RS_SPRI1      = 0x126,   /* SPI1 (RX) */
+    DMA_RS_SPTI2      = 0x129,   /* SPI2 (TX) */
+    DMA_RS_SPRI2      = 0x12A,   /* SPI2 (RX) */
+    DMA_RS_SPTI3      = 0x12B,   /* SPI3 (TX) */
+    DMA_RS_SPRI3      = 0x12E,   /* SPI3 (RX) */
+    DMA_RS_SPTI4      = 0x131,   /* SPI4 (TX) */
+    DMA_RS_SPRI4      = 0x132,   /* SPI4 (RX) */
+    DMA_RS_SPDIFTXI   = 0x141,   /* SPDIF (TX) */
+    DMA_RS_SPDIFRXI   = 0x142,   /* SPDIF (RX) */
+    DMA_RS_CMI1       = 0x147,   /* Motor Control PWM Timer ch1 */
+    DMA_RS_CMI2       = 0x14B,   /* Motor Control PWM Timer ch2 */
+    DMA_RS_MLBCI      = 0x14F,   /* Media Local Bus */
+    DMA_RS_SGDEI0     = 0x153,   /* Sound Generator0 */
+    DMA_RS_SGDEI1     = 0x157,   /* Sound Generator1 */
+    DMA_RS_SGDEI2     = 0x15B,   /* Sound Generator2 */
+    DMA_RS_SGDEI3     = 0x15F,   /* Sound Generator3 */
+    DMA_RS_SCITXI0    = 0x169,   /* Serial Communication Interface ch0 (TX) */
+    DMA_RS_SCIRXI0    = 0x16A,   /* Serial Communication Interface ch0 (RX) */
+    DMA_RS_SCITXI1    = 0x16D,   /* Serial Communication Interface ch1 (TX) */
+    DMA_RS_SCIRXI1    = 0x16E,   /* Serial Communication Interface ch1 (RX) */
+    DMA_RS_TI0        = 0x181,   /* IIC ch0 (TX) */
+    DMA_RS_RI0        = 0x182,   /* IIC ch0 (RX) */
+    DMA_RS_TI1        = 0x185,   /* IIC ch1 (TX) */
+    DMA_RS_RI1        = 0x186,   /* IIC ch1 (RX) */
+    DMA_RS_TI2        = 0x189,   /* IIC ch2 (TX) */
+    DMA_RS_RI2        = 0x18A,   /* IIC ch2 (RX) */
+    DMA_RS_TI3        = 0x18D,   /* IIC ch3 (TX) */
+    DMA_RS_RI3        = 0x18E,   /* IIC ch3 (RX) */
+    DMA_RS_LIN0_INT_T = 0x1A1,   /* LIN0 (TX) */
+    DMA_RS_LIN0_INT_R = 0x1A2,   /* LIN0 (RX) */
+    DMA_RS_LIN1_INT_T = 0x1A5,   /* LIN1 (TX) */
+    DMA_RS_LIN1_INT_R = 0x1A6,   /* LIN1 (RX) */
+    DMA_RS_IFEI0      = 0x1B1,   /* Pixel Format Converter ch0 (TX) */
+    DMA_RS_OFFI0      = 0x1B2,   /* Pixel Format Converter ch0 (TX) */
+    DMA_RS_IFEI1      = 0x1B5,   /* Pixel Format Converter ch1 (RX) */
+    DMA_RS_OFFI1      = 0x1B6    /* Pixel Format Converter ch1 (TX) */
+} dma_res_select_t;
+
+/* DMA transfer direction */
+typedef enum
+{
+    DMA_REQ_MIN =(-1),
+    DMA_REQ_SRC = 0, /* Read DMA */
+    DMA_REQ_DES = 1, /* Write DMA */
+    DMA_REQ_MAX = 2
+} dma_req_dir_t;
+
+/* Address count direction */
+typedef enum
+{
+    DMA_ADDR_MIN = (-1),
+    DMA_ADDR_INCREMENT = 0, /* Address Count Increment */
+    DMA_ADDR_FIX = 1,       /* Address Count Fix */
+    DMA_ADDR_MAX = 2
+} dma_addr_cnt_t;
+
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* DMA Init Parameter */
+typedef struct
+{
+    bool_t   channel[DMA_CH_NUM]; /* Set enable channel */
+    AIOCB    *p_aio;              /* set callback function (DMA error interrupt) */
+}dma_drv_init_t;
+
+/* DMA Setup Parameter */
+typedef struct
+{
+    dma_res_select_t   resource;     /* DMA Transfer Resource */
+    dma_req_dir_t      direction;    /* DMA Transfer Direction */
+    dma_unit_size_t    dst_width;    /* DMA Transfer Unit Size (Destination) */
+    dma_unit_size_t    src_width;    /* DMA Transfer Unit Size (Source) */
+    dma_addr_cnt_t     dst_cnt;      /* DMA Address Count (Destination) */
+    dma_addr_cnt_t     src_cnt;      /* DMA Address Count (Source) */
+    AIOCB              *p_aio;       /* set callback function (DMA end interrupt) */
+} dma_ch_setup_t;
+
+/* DMA Transfer Paramter */
+typedef struct
+{
+    void       *src_addr;    /* Sorce Address */
+    void       *dst_addr;    /* Destination Address */
+    uint32_t   count;        /* DMA Transfer Size */
+} dma_trans_data_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+/***********************************************************************************
+* ingroup API
+* This function initializes the driver and must be called at system start
+* up, prior to any required DMA functionality being available. This function
+* also sets the enable or disable for each DMA channel and DMA error call back 
+* function.
+*
+* param [in] p_dma_init_param - parameter of ch enable and DMA error callback function.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully initialized.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function shutdown the driver, making DMA functionality is no longer available.
+* It can be carried out only in calse of all channel free.
+*
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully uninitialized.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_UnInit(int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function allocates a DMA channel.
+* When channel is (-1), it looking for a free channel
+* When set channel to DMA channel number, a set channel is allocated
+*
+* param [in] channel     - allocate channel. (when channel is (-1), it looking for a 
+*                           free channel.)
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval channel number - successfully allocated.
+* retval -1             - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function close a DMA channel.
+*
+* param [in] channel     - close channel.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully allocate.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Free(const int_t channel, int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a DMA transfer parameter.
+* before calling R_DMA_Start(), please carry out this function.
+*
+* param [in] channel     - set up channel.
+* param [in] p_ch_setup  - DMA transfer parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully setup.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup, 
+                         int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a DMA transfer address and start DMA.
+*
+* param [in] channel     - DMA start channel.
+* param [in] p_ch_setup  - DMA address parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully DMA start.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                         int32_t * const p_errno);
+
+/***********************************************************************************
+* ingroup API
+* This function set up a continous DMA transfer address and start continuous DMA.
+*
+* param [in] channel     - continuous DMA start channel.
+* param [in] p_ch_setup  - continuous DMA address parameters.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully continuous DMA start.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                            int32_t * const p_errno);
+                            
+/***********************************************************************************
+* ingroup API
+* This function cancel DMA transfer.
+* Continous DMA also stops at the same time.
+* Please call this function during DMA transfer.
+*
+* param [in] channel     - chancel DMA start channel.
+* param [out] p_remain   - remain sizei of DMA transfer.
+* param [in/out] p_errno - get error code. (when p_errno is NULL, erroc code isn't set.)
+*
+* retval ESUCCESS - successfully cancel.
+* retval -1       - error occured.
+***********************************************************************************/
+
+extern int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno);
+
+
+/***********************************************************************************
+* ingroup API
+* This function get DMA driver version.
+*
+* param none
+*
+* retval driver version
+***********************************************************************************/
+
+extern uint16_t R_DMA_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* DMA_IF_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_inc/ioif_aio.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,104 @@
+/******************************************************************************
+ *
+ *  V. 2.03.00
+ * $Rev: 891 $
+ * $Date:: 2014-06-27 10:40:52 +0900#$
+ *
+ * Description : ioif_aio header file
+ *
+ * Copyright (C) 2009,2012 Renesas Electronics Corporation. All rights reserved.
+ *****************************************************************************/
+
+#ifndef IOIF_AIO_H
+#define IOIF_AIO_H
+
+/*************************************************************************
+ System Includes
+*************************************************************************/
+
+#include <cmsis_os.h>
+#include <posix_types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*************************************************************************
+ User Includes
+*************************************************************************/
+
+/*************************************************************************
+ Defines
+*************************************************************************/
+
+/* sigev_notify values */
+
+#define SIGEV_NONE      (1) /**< No notification */
+#define SIGEV_THREAD    (2) /**< A notification function is called in the driver's context */
+#define SIGEV_EVENT     (3) /**< An event flag is set */
+#define SIGEV_CALLBACK  (4) /**< An inter-process callback is made */
+
+/*************************************************************************
+ Constant Macros
+*************************************************************************/
+
+/*************************************************************************
+ Function Macros
+*************************************************************************/
+
+/*************************************************************************
+ Typedefs
+*************************************************************************/
+
+typedef void *      pthread_attr_t;     /**< unsupported */
+
+union sigval
+{
+    int             sival_int;          /**< Integer interpretation */
+    void *          sival_ptr;          /**< Pointer interpretation */
+};
+
+struct sigevent
+{
+    int             sigev_notify;       /**< SIGEV_NONE, SIGEV_THREAD, SIGEV_EVENT */
+    int             sigev_signo;        /**< signal or callback fp */
+    union sigval    sigev_value;        /**< user defined value to pass */
+    void            (*sigev_notify_function) (union sigval);
+                                        /**< notification function */
+};
+
+struct aiocb
+{
+    /* Implementation specific stuff */
+    struct aiocb *  pNext;              /**< next aio request */
+    struct aiocb *  pPrev;              /**< previous aio request */
+    ssize_t         aio_return;         /**< return value of operation */
+    int             aio_complete;       /**< non-zero when op is completed */
+
+    /* User parameters */
+    int             aio_fildes;         /**< FD for asynchronous op */
+    off_t           aio_offset;         /**< Absolute offset to seek to */
+    volatile void*  aio_buf;            /**< Buffer to read from/write to */
+    size_t          aio_nbytes;         /**< Number of bytes to read/write */
+    struct sigevent aio_sigevent;       /**< Signal to deliver */
+
+    /* Private implementation specific function pointer used by IOIF. Application should not set. */
+    ssize_t (*aio_iofn)(void *,void *,size_t,int);  /* synchronous I/O function */
+};
+typedef struct aiocb AIOCB;
+
+#if(1) /* mbed */
+#else  /* not mbed */
+struct timespec
+{
+    time_t   tv_sec;            /* Seconds.  */
+    long int tv_nsec;           /* Nanoseconds.  */
+};
+#endif /* end mbed */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_inc/misratypes.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,190 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2009-2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+ *
+ *  V. 2.03.00
+ * $Rev: 1667 $
+ * $Date:: 2015-05-29 14:01:37 +0900#$
+ *
+ * Description : Types for MISRA compliant C code.
+ *
+ *****************************************************************************/
+
+#ifndef _MISRATYPES_H_INCLUDED_
+#define _MISRATYPES_H_INCLUDED_
+
+
+/***********************************************************************************
+ System Includes
+***********************************************************************************/
+#include <cmsis_os.h>
+
+/***********************************************************************************
+ User Includes
+***********************************************************************************/
+#include "r_typedefs.h"
+
+/***********************************************************************************
+ Defines
+***********************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***********************************************************************************
+ Constant Macros
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Function Macros
+***********************************************************************************/
+
+/* Use this macro for an unused function argument */
+#define UNUSED_ARG(var)  (void)unused_arg(&(var))
+
+/* Use this macro to check is a value of any type is an error code */
+#define ISERROR(val) iserror((int32_t)(val))
+
+/* Use this macro when assigning a function for a task */
+#define TO_FP_FUNCTION(val) to_fp_function(val)
+
+/***********************************************************************************
+ Typedefs
+***********************************************************************************/
+
+typedef void (*funcptr_t)(void);
+
+/***********************************************************************************
+ Enumerated Types
+***********************************************************************************/
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+/* These functions are inlined by the SHC compiler in an optimise=1 build */
+static const void* unused_arg(const void* const var);
+static void *error_to_ptr(int32_t er);
+static bool_t iserror(int32_t ser);
+static funcptr_t to_fp_function(void (*val)(int32_t));
+
+/***********************************************************************************
+ Inline Functions
+***********************************************************************************/
+
+/**********************************************************************************
+Function Name:  unused_arg
+Description:    Used to prevent unused argument warnings from QA-C.
+                This function will be inlined by the SHC compiler and generate no code.
+                Use this function via the UNUSED_ARG macro.
+
+Parameters:     Pointer to unused argument
+
+Return value:   Passed in argument.
+***********************************************************************************/
+#if   defined (__CC_ARM)
+#pragma inline unused_arg
+#elif defined (__ICCARM__)
+#pragma inline =forced
+#endif
+static const void* unused_arg(const void* const var)
+{
+    return var;
+}
+
+/**********************************************************************************
+Function Name:  iserror
+Description:    Check if a value is an error code.  This is used instead of the HIOS
+                iserrno macro as that generates many warnings in QA-C.
+                This function will be inlined by the SHC compiler.
+                Use this function via the ISERROR macro.
+
+Parameters:     Value to check for error code
+
+Return value:   Non-zero if the value is an error code
+***********************************************************************************/
+
+#if   defined (__CC_ARM)
+#pragma inline iserror
+#elif defined (__ICCARM__)
+#pragma inline =forced
+#endif
+static bool_t iserror(const int32_t ser)
+{
+    uint32_t er = (uint32_t) ser;
+    return er >= 0xffffff80u;
+}
+
+/**********************************************************************************
+Function Name:  error_to_ptr
+Description:    Convert an error code to a pointer so we can return an error from
+                IOIF driver functions such as open and initialise without getting
+                warnings from QA-C.
+                This function will be inlined by the SHC compiler.
+
+Parameters:     Error code
+
+Return value:   Error code converted to a pointer
+***********************************************************************************/
+#if   defined (__CC_ARM)
+#pragma inline error_to_ptr
+#elif defined (__ICCARM__)
+#pragma inline =forced
+#endif
+static void *error_to_ptr(const int32_t er)
+{
+    return (void*) er;
+}
+
+/**********************************************************************************
+Function Name:  to_fp_function
+Description:    Converts a void (*fn)(VP_INT) function pointer to a FP function pointer
+                without getting warnings from QA-C.
+                This function will be inlined by the SHC compiler.
+
+Parameters:     Function pointer as void (*fn)(VP_INT)
+
+Return value:   Functino pointer as a FP
+***********************************************************************************/
+#if   defined (__CC_ARM)
+#pragma inline to_fp_function
+#elif defined (__ICCARM__)
+#pragma inline =forced
+#endif
+static funcptr_t to_fp_function(void (*val)(int32_t))
+{
+    /* QA-C will generate an error for this line as we are casting
+     * between different function pointer types.
+     */
+    return (funcptr_t)val;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MISRATYPES_H_INCLUDED_ */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_inc/posix_types.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,169 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2009,2012 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+ *
+ *  V. 2.03.00
+ * $Rev: 1560 $
+ * $Date:: 2015-03-16 10:39:54 +0900#$
+ *
+ * Description : POSIX types
+ *
+ *****************************************************************************/
+
+#ifndef POSIXTYPES_H_INCLUDED
+#define POSIXTYPES_H_INCLUDED
+
+/***********************************************************************************
+ System Includes
+***********************************************************************************/
+
+
+/***********************************************************************************
+ User Includes
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Defines
+***********************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* From <unistd.h> */
+#ifndef SEEK_SET
+#define SEEK_SET        0           /* from the biginning of file */
+#define SEEK_CUR        1           /* from the current position in file */
+#define SEEK_END        2           /* from the end of file */
+#endif
+
+/* <unistd.h> POSIX Standard: 2.10 file descriptors for stdin, stdout,
+  stderr not included with SHC. Therefore defined below. */
+#ifndef STDIN_FILENO
+    #define STDIN_FILENO (0)
+#endif
+
+#ifndef STDOUT_FILENO
+    #define STDOUT_FILENO (1)
+#endif
+
+#ifndef STDERR_FILENO
+    #define STDERR_FILENO (2)
+#endif
+
+
+/* These values must be as defined under open in the compiler manual
+ * otherwise the buffered file functions fopen() etc. will not work.
+ */
+#if(1) /* mbed */
+#define O_ACCMODE    7
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+#    define O_RDONLY 0
+#    define O_WRONLY 1
+#    define O_RDWR   2
+#    define O_CREAT  0x0200
+#    define O_EXCL   0x0300
+#    define O_TRUNC  0x0400
+#    define O_APPEND 0x0008
+#    define O_NONBLOCK 0x4000
+#    define O_SYNC     0x8000
+
+#else
+#    include <sys/fcntl.h>
+#    include <sys/types.h>
+#    include <sys/syslimits.h>
+#endif
+
+#else  /* not mbed */
+#define O_ACCMODE       00000007
+#define O_RDONLY        00000001
+#define O_WRONLY        00000002
+#define O_RDWR          00000004
+#define O_CREAT         00000010
+#define O_EXCL          00000020
+#define O_TRUNC         00000040
+#define O_APPEND        00002000
+#define O_NONBLOCK      00004000
+#define O_SYNC          00010000
+#endif /* end mbed */
+
+/***********************************************************************************
+ Constant Macros
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Function Macros
+***********************************************************************************/
+
+
+/***********************************************************************************
+ Typedefs and Structures
+***********************************************************************************/
+
+/* The POSIX standard states that:-
+    mode_t                              shall be an integer type.
+    nlink_t, uid_t, gid_t, and id_t     shall be integer types.
+    blkcnt_t and off_t                  shall be signed integer types.
+    fsblkcnt_t, fsfilcnt_t, and ino_t   shall be defined as unsigned integer types.
+    size_t                              shall be an unsigned integer type.
+    blksize_t, pid_t, and ssize_t       shall be signed integer types.
+    time_t and clock_t                  shall be integer or real-floating types.
+*/
+
+#if(1) /* mbed */
+#ifndef off_t
+typedef long off_t;
+#endif
+#ifndef ssize_t
+typedef int ssize_t;
+#endif
+#else  /* not mbed */
+typedef int fsid_t;
+typedef long time_t;    /* Time in seconds. */
+typedef long long off_t;
+typedef unsigned int mode_t;
+typedef unsigned int ino_t;
+typedef int nlink_t;
+typedef int uid_t;
+typedef int gid_t;
+typedef int dev_t;
+typedef int ssize_t;
+#endif /* end mbed */
+
+#if !defined(__cplusplus) && defined(__STRICT_ANSI__)
+#if defined (__GNUC__)
+typedef unsigned int size_t;
+#else /*__GNUC__*/
+typedef unsigned long size_t;
+#endif/*__GNUC__*/
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_inc/r_errno.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,142 @@
+/****** ************************************************************************
+ *
+ * $Rev: 891 $
+ * $Date: 2012-12-07 20:36:39 +0900#$
+ *
+ * Description : errno for POSIX IEEE Std 1003.1-2001
+ *
+ * (C) Copyright RENESAS ELECTRONICS Ltd 2012 All Rights Reserved
+ *****************************************************************************/
+
+/* Detect if SHC include errno.h has been included first, this is not supported */
+#ifdef _ERRNO
+    #error Renesas/Sh/9_x_x/include/errno.h has been included before SDK errno.h. Please specify SDK include path first.
+#endif
+
+#ifndef SDK_ERRNO
+#define SDK_ERRNO
+
+/* Include std headers to override _errno with SDK version */
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <math.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _REENTRANT 1
+
+/***********************************************************************************
+ System Includes
+***********************************************************************************/
+#ifdef EBADF
+    #undef EBADF
+#endif
+#ifdef EDOM
+    #undef EDOM
+#endif
+
+/* SDK errno extension, SDK returns 0 as success, and -1 when errno set */
+#define ESUCCESS    (0)
+#define EERROR      (-1)
+
+#define EBADF       (-17) /* Bad file descriptor */
+#define EINVAL      (-28) /* Invalid argument */
+#define ENOMEM      (-33) /* No memory available */
+#define ENOLCK      (-34) /* No lock available */
+#define ENOENT      (-42) /* No such file or directory */
+#define ETIMEDOUT   (-50) /* Timed out */
+#define EACCES      (-64) /* Access denied */
+#define EAGAIN      (-65) /* Resource unavailable. Try again */
+#define EBUSY       (-67) /* Device or resource busy */
+#define ECANCELED   (-68) /* Operation was cancelled */
+#define EDOM        (-69) /* Maths argument out of domain */
+#define EEXIST      (-70) /* File, directory or mount exists */
+#define EFBIG       (-71) /* File too big */
+#define EINPROGRESS (-72) /* Operation in progress */
+#define EIO         (-74) /* Input or Output error (possibly recoverable)*/
+#define EISDIR      (-75) /* Is a directory */
+#define EMFILE      (-76) /* Too many open files */
+#define ENAMETOOLONG (-77) /* File name too long */
+#define ENFILE      (-78) /* Too many files are open in the system */
+#define ENOBUFS     (-79) /* No buffers available */
+#define ENODEV      (-80) /* Not a valid device */
+#define ENOSPC      (-84) /* No space available on device */
+#define ENOTDIR     (-85) /* Not a directory */
+#define ENOTEMPTY   (-86) /* Directory not empty */
+#define ENOTSUP     (-87) /* Not supported */
+#define ENOTTY      (-88) /* No TTY available */
+#define ENXIO       (-89) /* Not valid IO address or device (unrecoverable)*/
+#define EPERM       (-90) /* Operation not permitted */
+#define EROFS       (-91) /* Read only file system */
+#define ESPIPE      (-92) /* Invalid seek on pipe */
+#define EXDEV       (-93) /* Device cross linked */
+#define ENOTSOCK    (-94) /* Not a socket */
+#define EMSGSIZE    (-95) /* Message too large */
+#define EINTR       (-96) /* Function interrupted */
+#define EFAULT      (-97) /* Section fault, bad address */
+#define EPIPE       (-98) /* Broken pipe */
+#define EALREADY    (-99) /* Connection already started */
+#define EDESTADDRREQ (-100) /* Destination address requred */
+#define EPROTOTYPE  (-101) /* Wrong protocol or codec type */
+#define ENOPROTOOPT (-102) /* Protocol or codec not available */
+#define EPROTONOSUPPORT (-103) /* Protocol or codec not supported */
+#define EOPNOTSUPP  (-104) /* Operation not supported */
+#define EAFNOSUPPORT (-105) /* Address family not supported */
+#define EADDRINUSE  (-106) /* Address already in use */
+#define EADDRNOTAVAIL (-107) /* Address not available */
+#define ECONNRESET  (-108) /* Connection reset */
+#define EISCONN     (-109) /* Connected */
+#define ENOTCONN    (-110) /* Not connected */
+#define ECONNREFUSED (-112) /* Connection refused */
+#define EPROCLIM    (-113) /* Too many processes */
+#define EUSERS      (-114) /* Too many users */
+#define EDEADLK     (-115) /* Resource deadlock would occur */
+#define EPROTO      (-116) /* Protocol or codec error */
+#define EOVERFLOW   (-117) /* Value too large to store in data type */
+#define ESRCH       (-118) /* No such task */
+#define EILSEQ      (-119) /* Illegal byte sequence format */
+#define EBADMSG     (-120) /* Bad message */
+#define ENOSYS      (-121) /* Function not supported */
+#define ECRC        (-122) /* CRC failure */
+#define EEOF        (-123) /* Position is End Of File */
+#define ESEEKPASTEND (-124) /* Seek past EOF */
+#define EMEDIUMTYPE (-127) /* Wrong medium type */
+#define ENOMEDIUM   (-128) /* No medium present */
+#define ESEEKRANGE  (-129) /* seek setting error */  /* Source Merge 11-1 */
+
+/***********************************************************************************
+ Defines
+***********************************************************************************/
+/* errno is a macro so it is re-entrant (per thread/task value) - this
+ * definition works with SH C libs.  The errno returns an l-value so
+ * it can be used on the left of an assignment as it is legal for an
+ * application to assign to errno.
+ *
+ * Note: Application code should not call ioif_get_errno directly. All
+ * access to errno should be made using the POSIX "errno" macro.
+*/
+extern int *ioif_get_errno(void);
+
+/* Remove SHC definitions so SDK can be used instead */
+#ifdef _errno
+    #undef _errno
+#endif
+
+#define _errno (*ioif_get_errno())
+
+#ifndef  errno
+    #define  errno _errno
+#endif
+
+#define iserrno(e)((unsigned int)(e) >= 0xffffff80UL)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_inc/scux_if.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,464 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          scux_if.h
+* $Rev: 1032 $
+* $Date:: 2014-08-06 09:04:50 +0900#$
+* @brief         SCUX Driver IOIF API header
+******************************************************************************/
+
+#ifndef SCUX_IF_H
+#define SCUX_IF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+#include "r_errno.h"
+#include "r_typedefs.h"
+#if(1) /* mbed */
+#include "ioif_aio.h"
+#include "misratypes.h"
+#include "R_BSP_mbed_fns.h"
+#include "R_BSP_ScuxDef.h"
+#else  /* not mbed */
+#include "ioif_public.h"
+#endif /* end mbed */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* Number of SCUX channel */
+typedef enum
+{
+    SCUX_CH_0 = 0,
+    SCUX_CH_1 = 1,
+    SCUX_CH_2 = 2,
+    SCUX_CH_3 = 3,
+    SCUX_CH_NUM = 4  /* Number of SCUX channel */
+} scux_ch_num_t;
+#endif /* end mbed */
+
+/* SCUX route setting */
+typedef enum
+{
+    /* mem to mem */
+    SCUX_ROUTE_SRC_MEM_MIN = 0x1000,
+    SCUX_ROUTE_SRC0_MEM    = 0x1001,
+    SCUX_ROUTE_SRC1_MEM    = 0x1002,
+    SCUX_ROUTE_SRC2_MEM    = 0x1003,
+    SCUX_ROUTE_SRC3_MEM    = 0x1004,
+    SCUX_ROUTE_SRC_MEM_MAX = 0x1005,
+    /* mem to SSIF */
+    SCUX_ROUTE_SRC_SSIF_MIN = 0x2000,
+    SCUX_ROUTE_SRC0_SSIF0   = 0x2001,
+    SCUX_ROUTE_SRC0_SSIF012 = 0x2002,
+    SCUX_ROUTE_SRC0_SSIF3   = 0x2003,
+    SCUX_ROUTE_SRC0_SSIF345 = 0x2004,
+    SCUX_ROUTE_SRC1_SSIF0   = 0x2005,
+    SCUX_ROUTE_SRC1_SSIF012 = 0x2006,
+    SCUX_ROUTE_SRC1_SSIF3   = 0x2007,
+    SCUX_ROUTE_SRC1_SSIF345 = 0x2008,    
+    SCUX_ROUTE_SRC2_SSIF1   = 0x2009,
+    SCUX_ROUTE_SRC2_SSIF4   = 0x200A,
+    SCUX_ROUTE_SRC3_SSIF2   = 0x200B,
+    SCUX_ROUTE_SRC3_SSIF5   = 0x200C,
+    SCUX_ROUTE_SRC_SSIF_MAX = 0x200D,
+    /* mem to NIX to SSIF */
+    SCUX_ROUTE_SRC_MIX_SSIF_MIN  = 0x3000,
+    SCUX_ROUTE_SRC0_MIX_SSIF0   = 0x3001,
+    SCUX_ROUTE_SRC0_MIX_SSIF012 = 0x3002,
+    SCUX_ROUTE_SRC0_MIX_SSIF3   = 0x3003,
+    SCUX_ROUTE_SRC0_MIX_SSIF345 = 0x3004,
+    SCUX_ROUTE_SRC1_MIX_SSIF0   = 0x3005,
+    SCUX_ROUTE_SRC1_MIX_SSIF012 = 0x3006,
+    SCUX_ROUTE_SRC1_MIX_SSIF3   = 0x3007,
+    SCUX_ROUTE_SRC1_MIX_SSIF345 = 0x3008,   
+    SCUX_ROUTE_SRC2_MIX_SSIF0   = 0x3009,
+    SCUX_ROUTE_SRC2_MIX_SSIF012 = 0x300A,
+    SCUX_ROUTE_SRC2_MIX_SSIF3   = 0x300B,
+    SCUX_ROUTE_SRC2_MIX_SSIF345 = 0x300C,
+    SCUX_ROUTE_SRC3_MIX_SSIF0   = 0x300D,
+    SCUX_ROUTE_SRC3_MIX_SSIF012 = 0x300E,
+    SCUX_ROUTE_SRC3_MIX_SSIF3   = 0x300F,
+    SCUX_ROUTE_SRC3_MIX_SSIF345 = 0x3010,   
+    SCUX_ROUTE_SRC_MIX_SSIF_MAX = 0x3011
+} scux_route_t;
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* used audio channel number setting */
+typedef enum
+{
+    SCUX_USE_CH_1 = 1,   /* used audio channel number is 1 */
+    SCUX_USE_CH_2 = 2,   /* used audio channel number is 2 */
+    SCUX_USE_CH_4 = 4,   /* used audio channel number is 4 */
+    SCUX_USE_CH_6 = 6,   /* used audio channel number is 6 */
+    SCUX_USE_CH_8 = 8    /* used audio channel number is 8 */
+} scux_use_channel_t;
+#endif /* end mbed */
+
+/* select audio channel number setting */
+typedef enum
+{
+    SCUX_AUDIO_CH_MIN = -1,
+    SCUX_AUDIO_CH_0 = 0,   /* select audio channel number is 0 */
+    SCUX_AUDIO_CH_1 = 1,   /* select audio channel number is 1 */
+    SCUX_AUDIO_CH_2 = 2,   /* select audio channel number is 2 */
+    SCUX_AUDIO_CH_3 = 3,   /* select audio channel number is 3 */
+    SCUX_AUDIO_CH_4 = 4,   /* select audio channel number is 4 */
+    SCUX_AUDIO_CH_5 = 5,   /* select audio channel number is 5 */
+    SCUX_AUDIO_CH_6 = 6,   /* select audio channel number is 6 */
+    SCUX_AUDIO_CH_7 = 7,   /* select audio channel number is 7 */
+    SCUX_AUDIO_CH_MAX = 8
+} scux_audio_channel_t;
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* SCUX data word length */
+typedef enum
+{
+    SCUX_DATA_LEN_MIN      =(-1),
+    SCUX_DATA_LEN_24       = 0,   /* data word length is 24bit */
+    SCUX_DATA_LEN_16       = 1,   /* data word length is 16bit */
+    SCUX_DATA_LEN_16_TO_24 = 2,   /* data word length is 24bit */
+    SCUX_DATA_LEN_MAX      = 3
+} scux_data_word_len_t;
+#endif /* end mbed */
+
+/* SSIF PIN mode setting */
+typedef enum
+{
+    SCUX_PIN_MODE_MIN          =(-1),
+    SCUX_PIN_MODE_INDEPEND     = 0,   /* PIN mode is independent */
+    SCUX_PIN_MODE_SLAVE_SLAVE  = 1,   /* PIN mode is slave-slave */
+    SCUX_PIN_MODE_MASTER_SLAVE = 2,   /* PIN mode is master-slave */
+    SCUX_PIN_MODE_MAX = 3
+} scux_pin_mode_t;
+
+/* SCUX sampling rate */
+typedef enum
+{
+    SCUX_SYNC_RATE_8      = 8000,    /* 8KHz */
+    SCUX_SYNC_RATE_11_025 = 11025,   /* 11.025KHz */
+    SCUX_SYNC_RATE_12     = 12000,   /* 12KHz */
+    SCUX_SYNC_RATE_16     = 16000,   /* 16KHz */
+    SCUX_SYNC_RATE_22_05  = 22050,   /* 22.05KHz */
+    SCUX_SYNC_RATE_24     = 24000,   /* 24KHz */
+    SCUX_SYNC_RATE_32     = 32000,   /* 32KHz */
+    SCUX_SYNC_RATE_44_1   = 44100,   /* 44.1KHz */
+    SCUX_SYNC_RATE_48     = 48000,   /* 48KHz */
+    SCUX_SYNC_RATE_64     = 64000,   /* 64KHz */
+    SCUX_SYNC_RATE_88_2   = 88200,   /* 88.2KHz */
+    SCUX_SYNC_RATE_96     = 96000    /* 96KHz */
+} scux_src_sync_rate_t;
+
+/* SCUX clock source setting */
+typedef enum
+{
+    SCUX_CLK_MIN  =(-1),
+    SCUX_CLK_AUDIO_CLK  = 0,   /* clock source is AUDIO_CLK */
+    SCUX_CLK_AUDIO_X1   = 1,   /* clock source is AUDIO_X1 */
+    SCUX_CLK_MLB_CLK    = 2,   /* clock source is MLB_CLK */
+    SCUX_CLK_USB_X1     = 3,   /* clock source is USB_X1 */
+    SCUX_CLK_CLKP1_2    = 4,   /* clock source is surrounding clock */
+    SCUX_CLK_MTU_TIOC3A = 5,   /* clock source is TIOC3A */
+    SCUX_CLK_MTU_TIOC4A = 6,   /* clock source is TIOC4A */
+    SCUX_CLK_SSIF0_WS   = 8,   /* clock source is SSIF0 WS */
+    SCUX_CLK_SSIF1_WS   = 9,   /* clock source is SSIF1 WS */
+    SCUX_CLK_SSIF2_WS   = 10,   /* clock source is SSIF2 WS */
+    SCUX_CLK_SSIF3_WS   = 11,  /* clock source is SSIF3 WS */
+    SCUX_CLK_SSIF4_WS   = 12,  /* clock source is SSIF4 WS */
+    SCUX_CLK_SSIF5_WS   = 13,  /* clock source is SSIF5 WS */
+    SCUX_CLK_MAX        = 14
+} scux_src_clk_source_t;
+
+/* SCUX delay mode setting */
+typedef enum
+{
+    SCUX_DELAY_MIN         =(-1),  
+    SCUX_DELAY_NORMAL      = 0,    /* Delay mode is normal */
+    SCUX_DELAY_LOW_DELAY1  = 1,    /* Delay mode is Low Delay1 */
+    SCUX_DELAY_LOW_DELAY2  = 2,    /* Delay mode is Low Delay2 */
+    SCUX_DELAY_MAX         = 3     
+} scux_src_delay_mode_t;
+
+/* DVU ramp time setting */
+typedef enum
+{
+    SCUX_DVU_TIME_MIN  =(-1),
+    SCUX_DVU_TIME_128DB_1STEP      = 0,   /* volume change 128DB among 1 step */
+    SCUX_DVU_TIME_64DB_1STEP       = 1,   /* volume change 64DB among 1 step */
+    SCUX_DVU_TIME_32DB_1STEP       = 2,   /* volume change 32DB among 1 step */
+    SCUX_DVU_TIME_16DB_1STEP       = 3,   /* volume change 16DB among 1 step */
+    SCUX_DVU_TIME_8DB_1STEP        = 4,   /* volume change 8DB among 1 step */
+    SCUX_DVU_TIME_4DB_1STEP        = 5,   /* volume change 4DB among 1 step */
+    SCUX_DVU_TIME_2DB_1STEP        = 6,   /* volume change 2DB among 1 step */
+    SCUX_DVU_TIME_1DB_1STEP        = 7,   /* volume change 1DB among 1 step */
+    SCUX_DVU_TIME_0_5DB_1STEP      = 8,   /* volume change 0.5DB among 1 step */
+    SCUX_DVU_TIME_0_25DB_1STEP     = 9,   /* volume change 0.25DB among 1 step */
+    SCUX_DVU_TIME_0_125DB_1STEP    = 10,  /* volume change 0.125DB among 1 step */
+    SCUX_DVU_TIME_0_125DB_2STEP    = 11,  /* volume change 0.125DB among 2 step */
+    SCUX_DVU_TIME_0_125DB_4STEP    = 12,  /* volume change 0.125DB among 4 step */
+    SCUX_DVU_TIME_0_125DB_8STEP    = 13,  /* volume change 0.125DB among 8 step */
+    SCUX_DVU_TIME_0_125DB_16STEP   = 14,  /* volume change 0.125DB among 16 step */
+    SCUX_DVU_TIME_0_125DB_32STEP   = 15,  /* volume change 0.125DB among 32 step */
+    SCUX_DVU_TIME_0_125DB_64STEP   = 16,  /* volume change 0.125DB among 64 step */
+    SCUX_DVU_TIME_0_125DB_128STEP  = 17,  /* volume change 0.125DB among 128 step */
+    SCUX_DVU_TIME_0_125DB_256STEP  = 18,  /* volume change 0.125DB among 256 step */
+    SCUX_DVU_TIME_0_125DB_512STEP  = 19,  /* volume change 0.125DB among 512 step */
+    SCUX_DVU_TIME_0_125DB_1024STEP = 20,  /* volume change 0.125DB among 1024 step */
+    SCUX_DVU_TIME_0_125DB_2048STEP = 21,  /* volume change 0.125DB among 2048 step */
+    SCUX_DVU_TIME_0_125DB_4096STEP = 22,  /* volume change 0.125DB among 4096 step */
+    SCUX_DVU_TIME_0_125DB_8192STEP = 23,  /* volume change 0.125DB among 8192 step */
+    SCUX_DVU_TIME_MAX              = 24   
+} scux_dvu_ramp_time_t;
+
+/* MIX ramp time setting */
+typedef enum
+{
+    SCUX_MIX_TIME_MIN            =(-1),  
+    SCUX_MIX_TIME_128DB_1STEP    = 0,    /* volume change 128DB among 1 step */
+    SCUX_MIX_TIME_64DB_1STEP     = 1,    /* volume change 64DB among 1 step */
+    SCUX_MIX_TIME_32DB_1STEP     = 2,    /* volume change 32DB among 1 step */
+    SCUX_MIX_TIME_16DB_1STEP     = 3,    /* volume change 16DB among 1 step */
+    SCUX_MIX_TIME_8DB_1STEP      = 4,    /* volume change 8DB among 1 step */
+    SCUX_MIX_TIME_4DB_1STEP      = 5,    /* volume change 4DB among 1 step */
+    SCUX_MIX_TIME_2DB_1STEP      = 6,    /* volume change 2DB among 1 step */
+    SCUX_MIX_TIME_1DB_1STEP      = 7,    /* volume change 1DB among 1 step */
+    SCUX_MIX_TIME_0_5DB_1STEP    = 8,    /* volume change 0.5DB among 1 step */
+    SCUX_MIX_TIME_0_25DB_1STEP   = 9,    /* volume change 0.25DB among 1 step */
+    SCUX_MIX_TIME_0_125DB_1STEP  = 10,   /* volume change 0.125DB among 1 step */
+    SCUX_MIX_TIME_MAX            = 11     
+} scux_mix_ramp_time_t;
+
+/* SSIF channels */
+typedef enum
+{
+    SCUX_SSIF_CH_0    = 0,    /* volume change 128DB among 1 step */
+    SCUX_SSIF_CH_1    = 1,    /* volume change 64DB among 1 step */
+    SCUX_SSIF_CH_2    = 2,    /* volume change 32DB among 1 step */
+    SCUX_SSIF_CH_3    = 3,    /* volume change 16DB among 1 step */
+    SCUX_SSIF_CH_4    = 4,    /* volume change 8DB among 1 step */
+    SCUX_SSIF_CH_5    = 5,    /* volume change 4DB among 1 step */
+    SCUX_SSIF_CH_NUM  = 6
+} scux_ssif_ch_num_t;
+
+/* SSIF channels */
+typedef enum
+{
+    SCUX_SSIF_SYSTEM_LEN_MIN   = 0,    
+    SCUX_SSIF_SYSTEM_LEN_16    = 1,    /* SSIF system word length is 16bit */
+    SCUX_SSIF_SYSTEM_LEN_24    = 2,    /* SSIF system word length is 24bit */
+    SCUX_SSIF_SYSTEM_LEN_32    = 3,    /* SSIF system word length is 32bit */
+    SCUX_SSIF_SYSTEM_LEN_48    = 4,    /* SSIF system word length is 48bit */
+    SCUX_SSIF_SYSTEM_LEN_64    = 5,    /* SSIF system word length is 64bit */
+    SCUX_SSIF_SYSTEM_LEN_128   = 6,    /* SSIF system word length is 128bit */
+    SCUX_SSIF_SYSTEM_LEN_256   = 7,    /* SSIF system word length is 256bit */
+    SCUX_SSIF_SYSTEM_LEN_MAX   = 8
+} scux_ssif_system_len_t;
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* SCUX IOCTL function code */
+#define SCUX_IOCTL_MIN                 (-1)
+#define SCUX_IOCTL_SET_START           0   /* start transfer */
+#define SCUX_IOCTL_SET_FLUSH_STOP      1   /* set flush stop function */
+#define SCUX_IOCTL_SET_CLEAR_STOP      2   /* set clear stop function */
+#define SCUX_IOCTL_SET_ROUTE           3   /* set route parameter */
+#define SCUX_IOCTL_SET_PIN_CLK         4   /* set pin clock parameter */
+#define SCUX_IOCTL_SET_PIN_MODE        5   /* set pin mode parameter */
+#define SCUX_IOCTL_SET_SRC_CFG         6   /* set SRC parameter */
+#define SCUX_IOCTL_SET_DVU_CFG         7   /* set DVU parameter */
+#define SCUX_IOCTL_SET_DVU_DIGI_VOL    8   /* set dgital volume parameter */
+#define SCUX_IOCTL_SET_DVU_RAMP_VOL    9   /* set ramp volume parameter */
+#define SCUX_IOCTL_SET_ZEROCROSS_MUTE  10  /* set zerocross mute paramter */
+#define SCUX_IOCTL_SET_STOP_MUTE       11  /* set mute stop */
+#define SCUX_IOCTL_SET_MIX_CFG         12  /* set MIX parameter */
+#define SCUX_IOCTL_SET_MIX_VOL         13  /* set MIX volume parameter */
+#define SCUX_IOCTL_SET_SSIF_CFG        14  /* set SSIF parameter */
+#define SCUX_IOCTL_GET_WRITE_STAT      15  /* get write status */
+#define SCUX_IOCTL_GET_READ_STAT       16  /* get read status */
+#define SCUX_IOCTL_GET_DVU_STAT        17  /* get DVU status */
+#define SCUX_IOCTL_GET_MUTE_STAT       18  /* get MUTE status */
+#define SCUX_IOCTL_GET_MIX_STAT        19  /* get MIX status */
+#define SCUX_IOCTL_MAX                 20
+
+#if(1) /* mbed */
+#else  /* not mbed */
+/* SCUX status */
+#define SCUX_STAT_STOP    0  /* request regstration isn't start */
+#define SCUX_STAT_IDLE    1  /* request isn't receied */
+#define SCUX_STAT_TRANS   2  /* under data transfer execution */
+#endif /* end mbed */
+
+/* DVU status */
+#define SCUX_DVU_STAT_MUTE          0  /* DVU volume is mute */
+#define SCUX_DVU_STAT_RAMP_DOWN     1  /* DVU volume is ramp down */
+#define SCUX_DVU_STAT_RAMP_UP       2  /* DVU volume is ramp up */
+#define SCUX_DVU_STAT_RAMP_FIXED    3  /* DVU volume change is stop */
+#define SCUX_DVU_STAT_ORIGINAL_SIZE 4  /* DVU volume is original size */
+
+/* MIX status */
+#define SCUX_MIX_STAT_RAMP_FIXED  0  /* MIX volume change is stop */
+#define SCUX_MIX_STAT_RAMP_DOWN   1  /* MIX volume is ramp down */
+#define SCUX_MIX_STAT_RAMP_UP     2  /* MIX volume is ramp up */
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* SSIF channel synchronous setting */
+typedef struct
+{
+    scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
+    scux_pin_mode_t        pin_mode;          /* SSIF sync setting */
+} scux_ssif_pin_mode_t;
+
+/* SSIF AUDIO_CLK source parameters */
+typedef struct
+{
+    scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
+    scux_src_clk_source_t  pin_clk;           /* AUDIO_CLK source */
+} scux_ssif_pin_clk_t;
+
+/* SSIF parameters */
+typedef struct
+{
+    scux_ssif_ch_num_t     ssif_ch_num;       /* ssif channel number */
+    bool_t                 mode_master;       /* master mode / slave mode select */
+    bool_t                 select_audio_clk;  /* AUDIO_X1 / AUDIO_CLK select */
+    scux_ssif_system_len_t system_word;       /* system word length */
+    bool_t                 sck_polarity_rise; /* SCK polarity type select */
+    bool_t                 ws_polarity_high;  /* WS polarity type select */
+    bool_t                 padding_high;      /* padding type select */
+    bool_t                 serial_data_align; /* serial data alingment type select */
+    bool_t                 ws_delay;          /* WS delay type select */
+    bool_t                 use_noise_cancel;  /* noise cancel ON / OFF select */
+    bool_t                 use_tdm;           /* TDM mode ON / OFF select */
+} scux_ssif_cfg_t;
+
+/* MIX parameters */
+typedef struct
+{
+    bool_t               mixmode_ramp;                          /* ramp mode / step mpde select */
+    scux_mix_ramp_time_t up_period;                             /* ramp up period */
+    scux_mix_ramp_time_t down_period;                           /* ramp down period */
+    uint32_t             mix_vol[SCUX_CH_NUM];                  /* MIX volume value */
+    scux_audio_channel_t select_out_data_ch[SCUX_AUDIO_CH_MAX]; /* audio data position setting */
+} scux_mix_cfg_t;
+
+/* zerocross mute parameters */
+typedef struct
+{
+    bool_t               zc_mute_enable[SCUX_AUDIO_CH_MAX];     /* zerocross mute enable setting */
+    void                 (*pcallback[SCUX_AUDIO_CH_MAX])(void); /* callback pointer for zerocross */
+} scux_zc_mute_t;
+
+/* ramp volume parameters */
+typedef struct
+{
+    bool_t               ramp_vol_enable[SCUX_AUDIO_CH_MAX];  /* ramp volume enable setting */
+    scux_dvu_ramp_time_t up_period;                           /* ramp up period */
+    scux_dvu_ramp_time_t down_period;                         /* ramp down period */
+    uint32_t             ramp_vol;                            /* ramp volume value */
+    uint32_t             ramp_wait_time;                      /* wait time for volume change */
+} scux_dvu_ramp_vol_t;
+
+/* digital volume parameters */
+typedef struct
+{
+    bool_t               digi_vol_enable;             /* digital volume enable setting */
+    uint32_t             digi_vol[SCUX_AUDIO_CH_MAX]; /* digital volume value */
+} scux_dvu_digi_vol_t;
+
+/* DVU parameters */
+typedef struct
+{
+    bool_t               dvu_enable;          /* DVU enable setting */
+    scux_dvu_digi_vol_t  dvu_digi_vol;        /* digital volume setting */
+    scux_dvu_ramp_vol_t  dvu_ramp_vol;        /* ramp volume setting */
+    scux_zc_mute_t       dvu_zc_mute;         /* zerocross mute setting */
+} scux_dvu_cfg_t;
+
+/* SRC parameters */
+typedef struct
+{
+    bool_t                src_enable;          /* SRC enable setting */
+    scux_use_channel_t    use_ch;              /* used data channel setting */
+    scux_data_word_len_t  word_len;            /* used word length setting */
+    bool_t                mode_sync;           /* sync mode/async mode select */
+    scux_src_sync_rate_t  input_rate_sync;     /* input rate on sync mode */
+    scux_src_clk_source_t input_clk_async;      /* input clock source on async mode */
+    uint32_t              input_div_async;     /* input divide rate on async mode */
+    scux_src_sync_rate_t  output_rate_sync;    /* output rate on sync mode */
+    scux_src_clk_source_t output_clk_async;    /* output clock source on async mode */
+    uint32_t              output_div_async;    /* output divide rate on async mode */
+    uint32_t              input_ws;            /* input WS frequency */
+    uint32_t              output_ws;           /* output WS frequency */
+    uint32_t              freq_tioc3a;         /* frequency of TIOC3A */
+    uint32_t              freq_tioc4a;         /* frequency of TIOC4A */
+    scux_src_delay_mode_t delay_mode;          /* delay mode setting */
+    uint32_t              wait_sample;         /* wait time setting */
+    uint8_t               min_rate_percentage; /* minimum rate setting */
+    scux_audio_channel_t  select_in_data_ch[SCUX_AUDIO_CH_MAX]; /* audio data position setting */
+} scux_src_cfg_t;
+
+/* SCUX setup parameter */
+typedef struct
+{
+    bool_t           enabled;               /* channel used flag */
+    uint8_t          int_level;             /* interrupt priority */
+    scux_route_t     route;                 /* reoute setting */
+    scux_src_cfg_t   src_cfg;               /* SRC parameters */
+} scux_channel_cfg_t;
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#if(1) /* mbed */
+RBSP_MBED_FNS* R_SCUX_MakeCbTbl_mbed(void);
+#else  /* not mbed */
+IOIF_DRV_API* R_SCUX_MakeCbTbl(void);
+#endif /* end mbed */
+
+extern uint16_t R_SCUX_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SCUX_IF_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_inc/ssif_if.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,274 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : ssif_if.h
+* $Rev: 1032 $
+* $Date:: 2014-08-06 09:04:50 +0900#$
+* Description  : SSIF Driver API header
+******************************************************************************/
+
+#ifndef SSIF_IF_H
+#define SSIF_IF_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+
+#include "r_typedefs.h"
+#include "r_errno.h"
+#if(1) /* mbed */
+#include "misratypes.h"
+#include "aioif.h"
+#include "R_BSP_mbed_fns.h"
+#include "R_BSP_SsifDef.h"
+#else  /* not mbed */
+#include "ioif_public.h"
+#endif /* end mbed */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if(1) /* mbed */
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+
+extern RBSP_MBED_FNS* R_SSIF_MakeCbTbl_mbed(void);
+#else  /* not mbed */
+/******************************************************************************
+ Defines
+ *****************************************************************************/
+
+/******************************************************************************
+ Constant Macros
+ *****************************************************************************/
+#define SSIF_NUM_CHANS       (6u)    /**< Number of SSIF channels */
+
+#define SSIF_CFG_DISABLE_ROMDEC_DIRECT (0x0u)        /* Disable SSIRDR->STRMDIN0 route */
+#define SSIF_CFG_ENABLE_ROMDEC_DIRECT  (0xDEC0DEC1u) /* Enable  SSIRDR->STRMDIN0 route */
+
+/******************************************************************************
+ Function Macros
+ *****************************************************************************/
+
+/******************************************************************************
+ Enumerated Types
+ *****************************************************************************/
+
+/** SSICR:CKS(Clock source for oversampling) */
+typedef enum
+{
+    SSIF_CFG_CKS_AUDIO_X1  = 0,  /**< select AUDIO_X1   */
+    SSIF_CFG_CKS_AUDIO_CLK = 1   /**< select AUIDIO_CLK */
+} ssif_chcfg_cks_t; 
+
+/** SSICR:CHNL(Audio channels per system word) */
+typedef enum
+{
+    SSIF_CFG_MULTI_CH_1 = 0,     /**< 1ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_2 = 1,     /**< 2ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_3 = 2,     /**< 3ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_4 = 3      /**< 4ch within systemword (on tdm=0) */
+} ssif_chcfg_multi_ch_t;
+
+/** SSICR:DWL(Data word length) */
+typedef enum
+{
+    SSIF_CFG_DATA_WORD_8  = 0,   /**< Data word length 8  */
+    SSIF_CFG_DATA_WORD_16 = 1,   /**< Data word length 16 */
+    SSIF_CFG_DATA_WORD_18 = 2,   /**< Data word length 18 */
+    SSIF_CFG_DATA_WORD_20 = 3,   /**< Data word length 20 */
+    SSIF_CFG_DATA_WORD_22 = 4,   /**< Data word length 22 */
+    SSIF_CFG_DATA_WORD_24 = 5,   /**< Data word length 24 */
+    SSIF_CFG_DATA_WORD_32 = 6    /**< Data word length 32 */
+} ssif_chcfg_data_word_t;
+
+/** SSICR:SWL(System word length) */
+typedef enum
+{
+    SSIF_CFG_SYSTEM_WORD_8   = 0,    /**< System word length 8   */
+    SSIF_CFG_SYSTEM_WORD_16  = 1,    /**< System word length 16  */
+    SSIF_CFG_SYSTEM_WORD_24  = 2,    /**< System word length 24  */
+    SSIF_CFG_SYSTEM_WORD_32  = 3,    /**< System word length 32  */
+    SSIF_CFG_SYSTEM_WORD_48  = 4,    /**< System word length 48  */
+    SSIF_CFG_SYSTEM_WORD_64  = 5,    /**< System word length 64  */
+    SSIF_CFG_SYSTEM_WORD_128 = 6,    /**< System word length 128 */
+    SSIF_CFG_SYSTEM_WORD_256 = 7     /**< System word length 256 */
+} ssif_chcfg_system_word_t;
+
+/** SSICR:SCKP(Clock polarity) */
+typedef enum
+{
+    SSIF_CFG_FALLING = 0,    /**< Falling edge */
+    SSIF_CFG_RISING  = 1     /**< Rising edge  */
+} ssif_chcfg_clock_pol_t;
+
+/** SSICR:SWSP(Word select polarity) */
+typedef enum
+{
+    SSIF_CFG_WS_LOW  = 0,    /**< Low for ther 1st channel(not TDM) */
+    SSIF_CFG_WS_HIGH = 1     /**< High for the 1st channel(not TDM) */
+} ssif_chcfg_ws_pol_t;
+
+/** SSICR:SPDP(Serial padding polarity) */
+typedef enum
+{
+    SSIF_CFG_PADDING_LOW  = 0,   /**< Padding bits are low  */
+    SSIF_CFG_PADDING_HIGH = 1    /**< Padding bits are high */
+} ssif_chcfg_padding_pol_t;
+
+/** SSICR:SDTA(Serial data alignment) */
+typedef enum
+{
+    SSIF_CFG_DATA_FIRST    = 0,  /**< Data first         */
+    SSIF_CFG_PADDING_FIRST = 1   /**< Padding bits first */
+} ssif_chcfg_serial_alignment_t;
+
+/** SSICR:PDTA(Parallel data alignment) */
+typedef enum
+{
+    SSIF_CFG_LEFT  = 0,  /**< Left aligned  */
+    SSIF_CFG_RIGHT = 1   /**< Right aligned */
+} ssif_chcfg_parallel_alignment_t;
+
+/** SSICR:DEL(Serial data delay) */
+typedef enum
+{
+    SSIF_CFG_DELAY    = 0,   /**< 1 clock delay */
+    SSIF_CFG_NO_DELAY = 1    /**< No delay      */
+} ssif_chcfg_ws_delay_t;
+
+/** SSICR:CKDV(Serial oversampling clock division ratio) */
+typedef enum
+{
+    SSIF_CFG_CKDV_BITS_1   = 0,
+    SSIF_CFG_CKDV_BITS_2   = 1,
+    SSIF_CFG_CKDV_BITS_4   = 2,
+    SSIF_CFG_CKDV_BITS_8   = 3,
+    SSIF_CFG_CKDV_BITS_16  = 4,
+    SSIF_CFG_CKDV_BITS_32  = 5,
+    SSIF_CFG_CKDV_BITS_64  = 6,
+    SSIF_CFG_CKDV_BITS_128 = 7,
+    SSIF_CFG_CKDV_BITS_6   = 8,
+    SSIF_CFG_CKDV_BITS_12  = 9,
+    SSIF_CFG_CKDV_BITS_24  = 10,
+    SSIF_CFG_CKDV_BITS_48  = 11,
+    SSIF_CFG_CKDV_BITS_96  = 12
+} ssif_chcfg_ckdv_t;
+
+
+/** SNCR:SSIxNL(Serial sound interface channel x noise canceler enable) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_NOISE_CANCEL = 0, /**< Not use noise cancel function */
+    SSIF_CFG_ENABLE_NOISE_CANCEL  = 1  /**< Use noise cancel function     */
+} ssif_chcfg_noise_cancel_t;
+
+
+/** SSITDMR:TDM(TDM mode) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_TDM = 0,   /**< not TDM mode */
+    SSIF_CFG_ENABLE_TDM  = 1    /**< set TDM mode */
+} ssif_chcfg_tdm_t;
+
+/******************************************************************************
+ Structures
+ *****************************************************************************/
+
+typedef struct
+{
+    uint32_t    mode;               /* Enable/Disable SSIRDR->STRMDIN0 route */
+    void        (*p_cbfunc)(void);  /* SSIF error callback function          */
+} ssif_chcfg_romdec_t;
+
+/**< This structure contains the configuration settings */
+typedef struct
+{
+    bool_t                          enabled;             /* The enable flag for the channel       */
+    uint8_t                         int_level;           /* Interrupt priority for the channel    */
+    bool_t                          slave_mode;          /* Mode of operation                     */
+    uint32_t                        sample_freq;         /* Audio Sampling frequency(Hz)          */
+    ssif_chcfg_cks_t                clk_select;          /* SSICR-CKS : Audio clock select        */
+    ssif_chcfg_multi_ch_t           multi_ch;            /* SSICR-CHNL: Audio channels per system word */
+    ssif_chcfg_data_word_t          data_word;           /* SSICR-DWL : Data word length          */
+    ssif_chcfg_system_word_t        system_word;         /* SSICR-SWL : System word length        */
+    ssif_chcfg_clock_pol_t          bclk_pol;            /* SSICR-SCKP: Bit Clock polarity        */
+    ssif_chcfg_ws_pol_t             ws_pol;              /* SSICR-SWSP: Word Clock polarity       */
+    ssif_chcfg_padding_pol_t        padding_pol;         /* SSICR-SPDP: Padding polarity          */
+    ssif_chcfg_serial_alignment_t   serial_alignment;    /* SSICR-SDTA: Serial data alignment     */
+    ssif_chcfg_parallel_alignment_t parallel_alignment;  /* SSICR-PDTA: Parallel data alignment   */
+    ssif_chcfg_ws_delay_t           ws_delay;            /* SSICR-DEL : Serial clock delay        */
+    ssif_chcfg_noise_cancel_t       noise_cancel;        /* GPIO-SNCR : Noise cancel              */
+    ssif_chcfg_tdm_t                tdm_mode;            /* SSITDMR-TDM: TDM mode                 */
+    ssif_chcfg_romdec_t             romdec_direct;       /* DMA : SSIRDR->STRMDIN0 route settings */
+} ssif_channel_cfg_t;
+
+/******************************************************************************
+ IOCTLS
+ *****************************************************************************/
+
+#define SSIF_CONFIG_CHANNEL        (7)
+#define SSIF_GET_STATUS           (13)
+
+
+/******************************************************************************
+ External Data
+ *****************************************************************************/
+
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+/**
+* @ingroup API
+*
+* This function returns a pointer to the function table of the SSIF driver.
+* This is intended to be used as a parameter in the ioif_start_device function.
+*
+* @retval IOIF_DRV_API* - Pointer to the table of functions supported by the
+* driver.
+*
+*/
+extern IOIF_DRV_API *R_SSIF_MakeCbTbl(void);
+#endif /* end mbed */
+
+extern int_t R_SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl);
+
+extern int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch);
+extern int_t R_SSIF_Userdef_SetClockDiv(const ssif_channel_cfg_t* const p_ch_cfg, ssif_chcfg_ckdv_t* const p_clk_div);
+
+extern uint16_t R_SSIF_GetVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SSIF_IF_H */
+/*EOF*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/dma/dma.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1526 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* @brief        DMA Driver internal functions
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "dma.h"
+#include "aioif.h"
+#include "iodefine.h"
+#include "gic.h"
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/* driver management infrmation */
+static dma_info_drv_t gb_info_drv;
+
+/******************************************************************************
+Private function define (interrupt handler)
+******************************************************************************/
+
+static void R_DMA_End0InterruptHandler(void);
+static void R_DMA_End1InterruptHandler(void);
+static void R_DMA_End2InterruptHandler(void);
+static void R_DMA_End3InterruptHandler(void);
+static void R_DMA_End4InterruptHandler(void);
+static void R_DMA_End5InterruptHandler(void);
+static void R_DMA_End6InterruptHandler(void);
+static void R_DMA_End7InterruptHandler(void);
+static void R_DMA_End8InterruptHandler(void);
+static void R_DMA_End9InterruptHandler(void);
+static void R_DMA_End10InterruptHandler(void);
+static void R_DMA_End11InterruptHandler(void);
+static void R_DMA_End12InterruptHandler(void);
+static void R_DMA_End13InterruptHandler(void);
+static void R_DMA_End14InterruptHandler(void);
+static void R_DMA_End15InterruptHandler(void);
+static void R_DMA_ErrInterruptHandler(void);
+static void R_DMA_EndHandlerProcess(const int_t channel);
+
+/******************************************************************************
+ Function prototypes
+ *****************************************************************************/
+ 
+static void  DMA_OpenChannel(const int_t channel);
+
+/******************************************************************************
+* Function Name: DMA_GetDrvInstance
+* Description : Get pointer of gb_info_drv.
+* Arguments : *p_dma_info_drv -
+*                  Pointer of gb_info_drv is returned.
+* Return Value : None
+******************************************************************************/
+
+dma_info_drv_t *DMA_GetDrvInstance(void)
+{
+    
+    return &gb_info_drv;
+}
+
+/******************************************************************************
+End of function DMA_GetDrv_Instance
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetDrvChInfo
+* Description : Get pointer of gb_info_drv.info_ch[channel].
+* Arguments : *p_dma_info_drv -
+*                  Pointer of gb_info_drv is returned.
+* Return Value : None
+******************************************************************************/
+
+dma_info_ch_t *DMA_GetDrvChInfo(const int_t channel)
+{
+    
+    return &gb_info_drv.info_ch[channel];
+}
+
+/******************************************************************************
+End of function DMA_GetDrvChInfo
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Initialize
+* Description : Initialize DMA driver.
+* Arguments : *p_dma_init_param -
+*                  Pointer of init parameters.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                OS error num -
+*                  Registering handler failed.
+******************************************************************************/
+
+int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param)
+{
+    int_t    retval = ESUCCESS;
+    int_t    ch_count;
+    uint32_t error_code;
+    bool_t   init_check_flag;
+    
+    /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
+    /* address table of register set for each channel */
+    static volatile struct st_dmac_n *gb_dma_ch_register_addr_table[DMA_CH_NUM] = 
+        { &DMAC0,
+          &DMAC1,
+          &DMAC2,
+          &DMAC3,
+          &DMAC4,
+          &DMAC5,
+          &DMAC6,
+          &DMAC7,
+          &DMAC8,
+          &DMAC9,
+          &DMAC10,
+          &DMAC11,
+          &DMAC12,
+          &DMAC13,
+          &DMAC14,
+          &DMAC15 
+        };
+    /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
+    
+    /* ->MISRA 11.3, 11.4, IPA R3.6.2 This cast is needed for register access. */
+    /* address table of register set for common register */
+    static volatile struct st_dmaccommon_n *gb_dma_common_register_addr_table[DMA_CH_NUM] = 
+        { &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC07,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815,
+          &DMAC815 
+        };
+    /* <-MISRA 11.3, 11.4, IPA R3.6.2*/
+
+    /* ->MISRA 11.3, 11.4 This cast is needed for register access. */
+    /* address table of register set for DMARS */
+    static volatile uint32_t *gb_dmars_register_addr_table[DMA_CH_NUM] = 
+        { &DMACDMARS0,
+          &DMACDMARS0,
+          &DMACDMARS1,
+          &DMACDMARS1,
+          &DMACDMARS2,
+          &DMACDMARS2,
+          &DMACDMARS3,
+          &DMACDMARS3,
+          &DMACDMARS4,
+          &DMACDMARS4,
+          &DMACDMARS5,
+          &DMACDMARS5,
+          &DMACDMARS6,
+          &DMACDMARS6,
+          &DMACDMARS7,
+          &DMACDMARS7 
+        };
+    /* <-MISRA 11.3, 11.4 */
+    
+    /* Interrpt handlers table */
+    static const IRQHandler gb_dma_int_handler_table[DMA_CH_NUM] = 
+        { &R_DMA_End0InterruptHandler, /* DMA end interrupt for ch0 - ch15 */
+          &R_DMA_End1InterruptHandler,
+          &R_DMA_End2InterruptHandler,
+          &R_DMA_End3InterruptHandler,
+          &R_DMA_End4InterruptHandler,
+          &R_DMA_End5InterruptHandler,
+          &R_DMA_End6InterruptHandler,
+          &R_DMA_End7InterruptHandler,
+          &R_DMA_End8InterruptHandler,
+          &R_DMA_End9InterruptHandler,
+          &R_DMA_End10InterruptHandler,
+          &R_DMA_End11InterruptHandler,
+          &R_DMA_End12InterruptHandler,
+          &R_DMA_End13InterruptHandler,
+          &R_DMA_End14InterruptHandler,
+          &R_DMA_End15InterruptHandler
+        };
+    
+    /* Interrupt numbers table */
+    static const IRQn_Type gb_dma_int_num_table[DMA_CH_NUM] =
+        { DMAINT0_IRQn, /* DMA end interrupt for ch0 - ch15 */
+          DMAINT1_IRQn,
+          DMAINT2_IRQn,
+          DMAINT3_IRQn,
+          DMAINT4_IRQn,
+          DMAINT5_IRQn,
+          DMAINT6_IRQn,
+          DMAINT7_IRQn,
+          DMAINT8_IRQn,
+          DMAINT9_IRQn,
+          DMAINT10_IRQn,
+          DMAINT11_IRQn,
+          DMAINT12_IRQn,
+          DMAINT13_IRQn,
+          DMAINT14_IRQn,
+          DMAINT15_IRQn
+        };
+        
+    /* element of p_dma_init_param is copied to element of gb_info_drv */
+    gb_info_drv.p_err_aio = p_dma_init_param->p_aio;
+    
+    /* set DMA error interrupt number */
+    gb_info_drv.err_irq_num = DMAERR_IRQn;
+    
+    /* init channel management information */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        /* set channel number */
+        gb_info_drv.info_ch[ch_count].ch = ch_count;
+        
+        /* set DMA end interrupt number */
+        gb_info_drv.info_ch[ch_count].end_irq_num = gb_dma_int_num_table[ch_count];
+        
+        /* init next DMA setting flag */
+        gb_info_drv.info_ch[ch_count].next_dma_flag = false;
+        
+        if (1U == ((uint32_t)ch_count & CHECK_ODD_EVEN_MASK))
+        {
+            /* set shift number when channel is odd value */ 
+            gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_ODD_CH;
+            /* set mask value when channel is odd value */
+            gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_ODD_CH;
+        }
+        else
+        {
+            /* set shift number when channel is even value */ 
+            gb_info_drv.info_ch[ch_count].shift_dmars = SHIFT_DMARS_EVEN_CH;
+            /* set mask value when channel is even value */
+            gb_info_drv.info_ch[ch_count].mask_dmars = MASK_DMARS_EVEN_CH;
+        }
+        
+        /* init DMA setup flag */
+        gb_info_drv.info_ch[ch_count].setup_flag = false;
+        
+        /* ->MISRA 11.4 This cast is needed for register access. */
+        /* set DMA register address for each channel */
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg = gb_dma_ch_register_addr_table[ch_count];
+        /* set common resgiter for channel 0 - 7 */
+        gb_info_drv.info_ch[ch_count].p_dma_common_reg = gb_dma_common_register_addr_table[ch_count];
+        /* <-MISRA 11.4 */
+        
+        /* set DMARS register for each channel */
+        gb_info_drv.info_ch[ch_count].p_dma_dmars_reg = gb_dmars_register_addr_table[ch_count];
+    }
+    
+    /* init DMA registers */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n =   N0SA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n =   N1SA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n =   N0DA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n =   N1DA_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n =   N0TB_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n =   N1TB_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = CHCTRL_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n =  CHCFG_INIT_VALUE;
+        /* set DMA interval = 0 */
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = CHITVL_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n =  CHEXT_INIT_VALUE;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n =   NXLA_INIT_VALUE;
+        *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg)   =   DMARS_INIT_VALUE;
+    }
+    /* init common resgiter for channel 0 - 7 */
+    /* set interrupt output : pulse,
+       set round robin mode  */
+    gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
+    /* init common resgiter for channel 8 - 15 */
+    /* set interrupt output : pulse,
+       set round robin mode */
+    gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = DCTRL_INIT_VALUE;
+    
+    if (ESUCCESS == retval)
+    {
+        /* DMA end interrupt handler register */
+        init_check_flag = false;
+        ch_count = 0;
+        while (false == init_check_flag)
+        {
+            error_code = InterruptHandlerRegister(gb_info_drv.info_ch[ch_count].end_irq_num, 
+                                                  gb_dma_int_handler_table[ch_count]
+                                                  );
+            /* 0 is no error on InterruptHandlerRegister() */
+            if (0U != error_code)
+            {
+                retval = (int_t)error_code;
+                init_check_flag = true;
+            }
+            if ((DMA_CH_NUM - 1) == ch_count)
+            {
+                init_check_flag = true;
+            }
+            ch_count++;
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* DMA error interrupt handler register */
+            error_code = InterruptHandlerRegister(gb_info_drv.err_irq_num, 
+                                                  &R_DMA_ErrInterruptHandler
+                                                 );
+            /* 0 is no error on InterruptHandlerRegister() */
+            if (0U != error_code)
+            {
+                retval = (int_t)error_code;
+            }
+        }
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* set DMA end interrupt level & priority */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            /* set interrupt level (set edge trigger, 1-N model) */
+            GIC_SetLevelModel(gb_info_drv.info_ch[ch_count].end_irq_num, 1, 1);
+        }
+        /* set DMA error interrupt level (set edge trgger, 1-N model) */
+        GIC_SetLevelModel(gb_info_drv.err_irq_num, 1, 1);
+        /* DMA error interrupt enable */
+        GIC_EnableIRQ(gb_info_drv.err_irq_num);
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* set channel status */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            if ((bool_t)false != p_dma_init_param->channel[ch_count])
+            {
+                gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_INIT;
+            }
+            else
+            {
+                gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
+            }
+        }
+        /* set driver status to DMA_DRV_INIT */
+        gb_info_drv.drv_stat = DMA_DRV_INIT;
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_Initialize
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_UnInitialize
+* Description : UnInitialize DMA driver.
+* Arguments : None.
+* Return Value : ESUCCESS -
+*                  Operation successful.
+*                OS error num -
+*                  Unregistering handler failed
+******************************************************************************/
+
+int_t DMA_UnInitialize(void)
+{
+    int_t            retval = ESUCCESS;
+    int_t            ch_count;
+    uint32_t         error_code;
+    bool_t           uninit_check_flag;
+
+    /* init DMA registers */
+    for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+    {
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCTRL_n = 0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHCFG_n =  0;
+        *(gb_info_drv.info_ch[ch_count].p_dma_dmars_reg) =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0SA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1SA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0DA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1DA_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N0TB_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->N1TB_n =   0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHITVL_n = 0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->CHEXT_n =  0;
+        gb_info_drv.info_ch[ch_count].p_dma_ch_reg->NXLA_n =   0;
+    }
+    /* init common resgiter for channel 0 - 7 */
+    gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DCTRL_0_7 = 0;
+    /* init common resgiter for channel 8 - 15 */
+    gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DCTRL_0_7 = 0;
+    
+    /* uninit DMA interrupt */
+    ch_count = 0;
+    uninit_check_flag = false;
+    while (false == uninit_check_flag)
+    {
+        /* disable DMA end interrupt */
+        GIC_DisableIRQ(gb_info_drv.info_ch[ch_count].end_irq_num);
+
+        /* unregister DMA end interrupt handler */
+        error_code = InterruptHandlerUnregister(gb_info_drv.info_ch[ch_count].end_irq_num);
+        /* 0 is no error on InterruptHandlerUnRegister() */
+        if (0U != error_code)
+        {
+            retval = (int_t)error_code;
+            uninit_check_flag = true;
+        }
+        if ((DMA_CH_NUM - 1) == ch_count)
+        {
+            uninit_check_flag = true;
+        }
+        ch_count++;
+    }
+    if (ESUCCESS == retval)
+    {
+        /* disable DMA error interrupt */
+        GIC_DisableIRQ(gb_info_drv.err_irq_num);
+        
+        /* unregister DMA interrupt error handler */
+        error_code = InterruptHandlerUnregister(gb_info_drv.err_irq_num);
+        /* 0 is no error on InterruptHandlerUnRegister() */
+        if (0U != error_code)
+        {
+            retval = (int_t)error_code;
+        }
+    }
+
+    if (ESUCCESS == retval)
+    {
+        /* set channel status to DMA_CH_UNINIT */
+        for (ch_count = 0; ch_count < DMA_CH_NUM; ch_count++)
+        {
+            gb_info_drv.info_ch[ch_count].ch_stat = DMA_CH_UNINIT;
+        }
+        /* set driver status to DMA_DRV_UNINIT*/
+        gb_info_drv.drv_stat = DMA_DRV_UNINIT;
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_UnInitialize
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_OpenChannel
+* Description : DMA channel open.
+*               Set DMA channel status to DMA_CH_OPEN.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value : None.
+******************************************************************************/
+
+static void DMA_OpenChannel(const int_t channel)
+{
+    /* set channel status to DMA_CH_OPEN */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_OpenChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetFreeChannel
+* Description : Find free DMA channel and Get DMA channel.
+* Arguments : None
+* Return Value :   channel -
+*                     Open channel number.
+*                  error code -
+*                     EMFILE : When looking for a free channel, but a free
+*                              channel didn't exist.
+******************************************************************************/
+
+int_t DMA_GetFreeChannel(void)
+{
+    int_t           retval = EFAULT;
+    dma_info_ch_t   *dma_info_ch;
+    int_t           ch_alloc;
+    bool_t          ch_stat_check_flag;
+    
+    /* looking for free channel */
+    ch_stat_check_flag = false;
+    ch_alloc = 0;
+    while (false == ch_stat_check_flag)
+    {
+        dma_info_ch = DMA_GetDrvChInfo(ch_alloc);
+                        
+        if (false == ch_stat_check_flag)
+        {
+            if (DMA_CH_INIT == dma_info_ch->ch_stat)
+            {
+                DMA_OpenChannel(ch_alloc);
+                retval = ch_alloc;
+                ch_stat_check_flag = true;
+            }
+            if (false ==  ch_stat_check_flag)
+            {
+                ch_alloc++;
+                /* not detected free channel */
+                if (DMA_CH_NUM == ch_alloc)
+                {
+                    /* set error return value */
+                    retval = EMFILE;
+                    ch_stat_check_flag = true;
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_GetFreeChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_GetFixedChannel
+* Description : Get specified DMA channel number.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value :   channel -
+*                     Open channel number.
+*                  error code -
+*                     EBUSY : It has been allocated already in channel.
+*                     ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                     EFAULT: Channel status is besides the status definded in 
+*                             dma_stat_ch_t.
+******************************************************************************/
+
+int_t DMA_GetFixedChannel(const int_t channel)
+{
+    int_t           retval = ESUCCESS;
+    dma_info_ch_t   *dma_info_ch;
+    
+    /* allocate the specified number */
+    dma_info_ch = DMA_GetDrvChInfo(channel);
+            
+    if (ESUCCESS == retval)
+    {
+        if (DMA_CH_INIT == dma_info_ch->ch_stat)
+        {
+            DMA_OpenChannel(channel);
+            /* return alloc channel number */
+            retval = channel;
+        }
+        else
+        {
+            /* set error return value */
+            switch (dma_info_ch->ch_stat)
+            {
+                case DMA_CH_UNINIT:
+                    retval = ENOTSUP; 
+                break;
+                /* These 2 cases are intentionally combined. */
+                case DMA_CH_OPEN:
+                case DMA_CH_TRANSFER:
+                    retval = EBUSY; 
+                break;
+                                    
+                default:
+                    retval = EFAULT; 
+                break;
+                                    
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function DMA_GetFixedChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_CloseChannel
+* Description : DMA channel close.
+*               Set DMA channel status to DMA_CH_INIT.
+* Arguments : channel -
+*                  Close channel number.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_CloseChannel(const int_t channel)
+{
+    /* clear DMARS register */
+    *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) &= gb_info_drv.info_ch[channel].mask_dmars;
+
+    /* set channel status to DMA_CH_INIT */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_INIT;
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_CloseChannel
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Setparam
+* Description : Set DMA transfer parameter to Register.
+* Arguments : channel -
+*                  Set up channel number.
+*             *p_ch_setup -
+*                  Set up parameters.
+*             *p_ch_cfg -
+*                  DMA channel config table parameters.
+*             *reqd
+*                  set vaule for REQD bit on CHCFG
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetParam(const int_t channel, const dma_ch_setup_t *const p_ch_setup, 
+                  const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd)
+{
+    uint32_t  chcfg_sel;
+    uint32_t  value_dmars;
+    
+    /* set DMA transfer parameter to DMA channel infomation */
+    gb_info_drv.info_ch[channel].resource =  p_ch_setup->resource;
+    gb_info_drv.info_ch[channel].direction = p_ch_setup->direction;
+    gb_info_drv.info_ch[channel].src_width = p_ch_setup->src_width;
+    gb_info_drv.info_ch[channel].src_cnt =   p_ch_setup->src_cnt;
+    gb_info_drv.info_ch[channel].dst_width = p_ch_setup->dst_width;
+    gb_info_drv.info_ch[channel].dst_cnt =   p_ch_setup->dst_cnt;
+    gb_info_drv.info_ch[channel].p_end_aio = p_ch_setup->p_aio;
+    
+    /* set DMARS value and protect non change bit */
+    value_dmars = *(gb_info_drv.info_ch[channel].p_dma_dmars_reg);
+    value_dmars = ((value_dmars & gb_info_drv.info_ch[channel].mask_dmars) |
+                   (uint32_t)(p_ch_cfg->dmars << gb_info_drv.info_ch[channel].shift_dmars)); 
+    /* set DMARS register value */
+    *(gb_info_drv.info_ch[channel].p_dma_dmars_reg) = value_dmars;
+        
+    /* set CHCFG regsiter */
+    if (channel < HIGH_COMMON_REG_OFFSET)
+    {
+        chcfg_sel = (uint32_t)channel;
+    }
+    else
+    {
+        chcfg_sel = (uint32_t)(channel - HIGH_COMMON_REG_OFFSET);
+    }
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n 
+        = ((uint32_t)CHCFG_FIXED_VALUE |
+           /* ->MISRA 21.1 ,IPA R2.4.1 The value of every parameter won't be minus.
+              and the value after a shift will be less than 0x80000000 certainly. 
+           */
+           (((uint32_t)p_ch_setup->dst_cnt << CHCFG_SHIFT_DAD) & CHCFG_MASK_DAD) |
+           (((uint32_t)p_ch_setup->src_cnt << CHCFG_SHIFT_SAD) & CHCFG_MASK_SAD) |
+           (((uint32_t)p_ch_setup->dst_width << CHCFG_SHIFT_DDS) & CHCFG_MASK_DDS) |
+           (((uint32_t)p_ch_setup->src_width << CHCFG_SHIFT_SDS) & CHCFG_MASK_SDS) |
+           /* <-MISRA 21.1, IPA R2.4.1 */
+           p_ch_cfg->tm |
+           p_ch_cfg->lvl |
+           reqd |
+           chcfg_sel);
+           
+    /* set setup flag */
+    gb_info_drv.info_ch[channel].setup_flag = true;
+                     
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetParam
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_BusParam
+* Description : Set bus parameter for DMA.
+* Arguments : channel -
+*                  Set address channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data)
+{
+    uint32_t src_bus_addr = (uint32_t)p_dma_data->src_addr;
+    uint32_t dst_bus_addr = (uint32_t)p_dma_data->dst_addr;
+    uint32_t chext_value = (CHEXT_SET_DPR_NON_SECURE | CHEXT_SET_SPR_NON_SECURE);
+    
+    /* set bus parameter for SRC */
+    if ((DMA_EXTERNAL_BUS_END >= src_bus_addr)           ||
+        ((DMA_EXTERNAL_BUS_MIRROR_START <= src_bus_addr) &&
+         (DMA_EXTERNAL_BUS_MIRROR_END >= src_bus_addr)))
+        
+    {
+        chext_value |= CHEXT_SET_SCA_NORMAL;
+    }
+    else
+    {
+        chext_value |= CHEXT_SET_SCA_STRONG;
+    }
+    
+    /* set bus parameter for DST */
+    if ((DMA_EXTERNAL_BUS_END >= dst_bus_addr)           ||
+        ((DMA_EXTERNAL_BUS_MIRROR_START <= dst_bus_addr) &&
+         (DMA_EXTERNAL_BUS_MIRROR_END >= dst_bus_addr)))
+        
+    {
+        chext_value |= CHEXT_SET_DCA_NORMAL;
+    }
+    else
+    {
+        chext_value |= CHEXT_SET_DCA_STRONG;
+    }
+    
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHEXT_n = chext_value;
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_BusParam
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetData
+* Description : Set DMA transfer address to Register.
+* Arguments : channel -
+*                  Set address channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+*             next_register_set -
+*                  Number of next register set.
+* Return Value : None.
+******************************************************************************/
+    
+void DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                          const uint32_t next_register_set)
+{
+    if (0U == next_register_set)
+    {
+        /* set DMA transfer address parameters to next register set0 */
+        gb_info_drv.info_ch[channel].src_addr0 = p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].dst_addr0 = p_dma_data->dst_addr;
+        gb_info_drv.info_ch[channel].count0 =    p_dma_data->count;
+        
+        /* ->MISRA 11.3 This cast is needed for setting address to register. */
+        /* set DAM transfer addres to register */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0SA_n = (uint32_t)p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0DA_n = (uint32_t)p_dma_data->dst_addr;
+        /* <-MISRA 11.3 */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N0TB_n = p_dma_data->count;
+    }
+    else
+    {
+        /* set DMA transfer address parameters to next regiter set1 */
+        gb_info_drv.info_ch[channel].src_addr1 = p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].dst_addr1 = p_dma_data->dst_addr;
+        gb_info_drv.info_ch[channel].count1 =    p_dma_data->count;
+        
+        /* ->MISRA 11.3 This cast is needed for setting address to register. */
+        /* set DAM transfer addres to register */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1SA_n = (uint32_t)p_dma_data->src_addr;
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1DA_n = (uint32_t)p_dma_data->dst_addr;
+        /* <-MISRA 11.3 */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->N1TB_n = p_dma_data->count;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetData
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetNextData
+* Description : Set continuous DMA transfer setting.
+* Arguments : channel -
+*                  Set continuous DMA transfer channel number.
+*             *p_dma_data -
+*                  DMA transfer address parameter set.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data)
+{
+    uint32_t  next_register_set;
+    
+    /* check number of next register set for next DMA transfer */
+    /* The reverse number in current number is set in next regsiter set of next DMA. */
+    if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_SR))
+    {
+        next_register_set = 1U;
+    }
+    else
+    {
+        next_register_set = 0U;
+    }
+    
+    /* set DMA transfer address for next DMA */
+    DMA_SetData(channel, p_dma_data, next_register_set);
+    
+    /* start setting for next DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)(CHCFG_SET_REN | CHCFG_SET_RSW);
+    
+    /* set flag wich indicates that next DMA transfer set already */
+    gb_info_drv.info_ch[channel].next_dma_flag = true;
+
+    /* auto restart continous DMA */
+    if ((0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN)) &&
+        (false == gb_info_drv.info_ch[channel].setup_flag))
+    {
+        /* auto restart DMA */
+        DMA_SetData(channel, p_dma_data, 0);
+        DMA_Start(channel, true);
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Nextdata
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Start
+* Description : Start DMA transfer.
+* Arguments : channel -
+*                  DMA transfer start channel number.
+*           :restart_flag -
+*                  Flag of DMA continous transfer auto restart.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_Start(const int_t channel, const bool_t restart_flag)
+{
+    if (false != restart_flag)
+    {
+        /* clear continous DMA setting */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= 
+        ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL | CHCFG_SET_REN);
+        gb_info_drv.info_ch[channel].next_dma_flag = false;
+    }
+    
+    /* clear setup flag */
+    gb_info_drv.info_ch[channel].setup_flag = false;
+    
+    /* reset DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SWRST;
+    
+    /* clear mask of DMA transfer end */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~((uint32_t)CHCFG_SET_DEM);
+    
+    GIC_EnableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+    
+    /* start DMA transfer */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_SETEN;
+    
+    /* set channel status to DMA_CH_TRANSFER */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_TRANSFER;
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Start
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_Stop
+* Description : Stop DMA transfer.
+* Arguments : channel -
+*                  DMA transfer start channel number.
+*             *p_remain -
+*                  Remain data size of DMA transfer.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_Stop(const int_t channel, uint32_t * const p_remain)
+{
+    uint32_t  stop_wait_cnt;
+    
+    /* disable DMA end interrupt */
+    GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+    
+    /* stop DMA transfer */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = CHCTRL_SET_CLREN;
+    
+    /* wait DMA stop */
+    stop_wait_cnt = 0;
+    while ((0 != (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_TACT)) && 
+           (DMA_STOP_WAIT_MAX_CNT > stop_wait_cnt))
+    {
+        stop_wait_cnt++;
+    }    
+    
+    if (DMA_STOP_WAIT_MAX_CNT <= stop_wait_cnt)
+    {
+        /* NON_NOTICE_ASSERT: wait count is abnormal value (usually, a count is set to 0 or 1) */
+    }  
+    
+    /* get remain data size */
+    *p_remain = gb_info_drv.info_ch[channel].p_dma_ch_reg->CRTB_n;
+    
+    /* set mask of DMA transfer end */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
+    
+    /* clear setting of continuous DMA */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
+    
+    /* clear TC, END bit */
+    gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
+    
+    /* clear flag wich indicates that next DMA transfer set already */
+    gb_info_drv.info_ch[channel].next_dma_flag = false;
+    
+    /* interrupt clear, if interrupt occured already */
+    GIC_ClearPendingIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+    
+    /* set channel status to DMA_CH_OPEN */
+    gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_Stop
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: DMA_SetErrCode
+* Description : Set error code to error code pointer.
+*               If error code pointer is NULL, nothing is done.
+* Arguments : error_code -
+*                  Error code.
+*             *p_errno -
+*                  Pointer of set error code.
+* Return Value : None.
+******************************************************************************/
+
+void DMA_SetErrCode(const int_t error_code, int32_t * const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function DMA_SetErrCode
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_ErrInterruptHandler
+* Description : DMA error interrupt handler.
+*               Notify error information to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB member.
+******************************************************************************/
+
+static void R_DMA_ErrInterruptHandler(void)
+{
+    uint32_t dstat_er_0_7;
+    uint32_t dstat_er_8_15;
+    
+    if (NULL != gb_info_drv.p_err_aio)
+    {
+        /* get error channel number */
+        dstat_er_0_7  = gb_info_drv.info_ch[DMA_CH_0].p_dma_common_reg->DSTAT_ER_0_7;
+        dstat_er_8_15 = gb_info_drv.info_ch[HIGH_COMMON_REG_OFFSET].p_dma_common_reg->DSTAT_ER_0_7;
+        
+        /* set error infrmation */
+        gb_info_drv.p_err_aio->aio_sigevent.sigev_value.sival_int = (int_t)(dstat_er_0_7 | (dstat_er_8_15 << HIGH_COMMON_REG_OFFSET));
+        
+        /* set error code (EIO) */
+        gb_info_drv.p_err_aio->aio_return = EIO;
+        
+        /* call back to the module function which called DMA driver */
+        ahf_complete(NULL, gb_info_drv.p_err_aio);
+    }
+    else
+    {
+        ;
+        /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
+    }
+    
+}
+
+/******************************************************************************
+End of function R_DMA_ErrInteruuptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End0InterruptHandler
+* Description : DMA end interrupt handler for channel 0.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End0InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_0);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End0InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End1InterruptHandler
+* Description : DMA end interrupt handler for channel 1.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End1InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_1);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End1InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End2InterruptHandler
+* Description : DMA end interrupt handler for channel 2.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End2InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_2);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End2InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End3InterruptHandler
+* Description : DMA end interrupt handler for channel 3.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End3InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_3);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End3InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End4InterruptHandler
+* Description : DMA end interrupt handler for channel 4.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End4InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_4);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End4InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End5InterruptHandler
+* Description : DMA end interrupt handler for channel 5.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End5InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_5);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End5InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End6InterruptHandler
+* Description : DMA end interrupt handler for channel 6.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End6InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_6);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End6InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End7InterruptHandler
+* Description : DMA end interrupt handler for channel 7.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End7InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_7);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End7InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End8InterruptHandler
+* Description : DMA end interrupt handler for channel 8.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End8InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_8);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End8InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End9InterruptHandler
+* Description : DMA end interrupt handler for channel 9.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End9InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_9);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End9InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End10InterruptHandler
+* Description : DMA end interrupt handler for channel 10.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End10InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_10);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End10InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End11InterruptHandler
+* Description : DMA end interrupt handler for channel 11.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End11InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_11);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End11InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End12InterruptHandler
+* Description : DMA end interrupt handler for channel 12.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End12InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_12);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End12InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End13InterruptHandler
+* Description : DMA end interrupt handler for channel 13.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End13InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_13);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End13InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End14InterruptHandler
+* Description : DMA end interrupt handler for channel 14.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End14InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_14);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End14InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_End15InterruptHandler
+* Description : DMA end interrupt handler for channel 15.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : None.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+static void R_DMA_End15InterruptHandler(void)
+{
+    
+    R_DMA_EndHandlerProcess(DMA_CH_15);
+    
+}
+
+/******************************************************************************
+End of function R_DMA_End15InterruptHandler
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_DMA_EndHandlerProcess
+* Description : DMA end interrupt handler process carry out.
+*               It's processed to DMA complete and notify DMA transfer finished 
+*               to the module function which called DMA driver.
+* Arguments : channel -
+*                  Open channel number.
+* Return Value : None.
+*                Note: store error code (EIO) to AIOCB.
+*                  ESUCCESS -
+*                     DMA transfer completed.
+*                  EIO -
+*                     DMA transfer don't stopped. 
+******************************************************************************/
+
+__inline static void R_DMA_EndHandlerProcess(const int_t channel)
+{
+    bool_t   store_next_dma_flag;
+    int_t    was_masked;
+    
+    if (NULL != gb_info_drv.info_ch[channel].p_end_aio)
+    {
+        /* disable all irq */
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        /* store next_dma_flag */
+        store_next_dma_flag = gb_info_drv.info_ch[channel].next_dma_flag;
+    
+        /* clear flag wich indicates that next DMA transfer set already */
+        gb_info_drv.info_ch[channel].next_dma_flag = false;
+    
+        if (false == store_next_dma_flag) 
+        {
+            /* DMA transfer complete */
+            /* mask DMA end interrupt */
+            GIC_DisableIRQ(gb_info_drv.info_ch[channel].end_irq_num);
+        
+            /* set channel status to DMA_CH_OPEN */
+            gb_info_drv.info_ch[channel].ch_stat = DMA_CH_OPEN;
+        
+            /* set mask of DMA transfer end */
+            gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n |= (uint32_t)CHCFG_SET_DEM;
+    
+            /* clear setting of continuous DMA */
+            gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCFG_n &= ~(uint32_t)(CHCFG_SET_RSW | CHCFG_SET_RSEL);
+            
+            /* check EN bit is clear */
+            if (0U == (gb_info_drv.info_ch[channel].p_dma_ch_reg->CHSTAT_n & CHSTAT_MASK_EN))
+            {
+                /* set error code (ESUCCESS) */
+                gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
+            }
+            else
+            {
+                /* set error code (EIO) */
+                gb_info_drv.info_ch[channel].p_end_aio->aio_return = EIO;
+            }
+        }
+        else
+        {
+            /* set next DMA already */
+            /* set error code (ESUCCESS) */
+            gb_info_drv.info_ch[channel].p_end_aio->aio_return = ESUCCESS;
+        }
+    
+        /* clear TC, END bit */
+        gb_info_drv.info_ch[channel].p_dma_ch_reg->CHCTRL_n = (CHCTRL_SET_CLRTC | CHCTRL_SET_CLREND);
+
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+
+        /* call back to the module function which called DMA driver */
+        ahf_complete(NULL, gb_info_drv.info_ch[channel].p_end_aio);
+    }
+    else
+    {
+        ;
+        /* NON_NOTICE_ASSERT:<callback pointer is NULL> */
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function R_DMA_EndHandlerProcess
+******************************************************************************/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/dma/dma.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,263 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma.h
+* $Rev: 1616 $
+* $Date:: 2015-04-21 19:00:08 +0900#$
+* @brief        DMA Driver internal headers
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+#ifndef DMA_H
+#define DMA_H
+
+/******************************************************************************
+Includes <System Includes>, "Project Includes"
+******************************************************************************/
+
+#include "dma_if.h" 
+#include "Renesas_RZ_A1.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Number of channel configure table */
+#define DMA_CH_CONFIG_TABLE_NUM  (95U)
+
+/* Magic Number */
+#define SHIFT_DMARS_EVEN_CH      (0U)  /* Shift Value for DMARS Register access in Even ch */
+#define SHIFT_DMARS_ODD_CH       (16U) /* Shift Value for DMARS Register access in Odd ch */
+#define MASK_DMARS_EVEN_CH       (0xFFFF0000U) /* Mask value for DMARS Register in Even ch */
+#define MASK_DMARS_ODD_CH        (0x0000FFFFU) /* Mask value for DMARS Register in Odd ch */
+#define HIGH_COMMON_REG_OFFSET   (8)  /* for Common Register Access in ch 0-8 */
+#define CHECK_ODD_EVEN_MASK      (0x00000001U)  /* for check value of odd or even */
+#define DMA_STOP_WAIT_MAX_CNT    (10U) /* Loop count for DMA stop (usually, a count is set to 0 or 1) */
+
+/* Register Set Value */
+/* Init Value */
+#define N0SA_INIT_VALUE      (0U)          /* HW init value */
+#define N1SA_INIT_VALUE      (0U)          /* HW init value */
+#define N0DA_INIT_VALUE      (0U)          /* HW init value */
+#define N1DA_INIT_VALUE      (0U)          /* HW init value */
+#define N0TB_INIT_VALUE      (0U)          /* HW init value */
+#define N1TB_INIT_VALUE      (0U)          /* HW init value */
+#define CHCTRL_INIT_VALUE    (0U)          /* HW init value */
+#define CHCFG_INIT_VALUE     (0x01000000U) /* interrupt disable */
+#define CHITVL_INIT_VALUE    (0U)          /* DMA interval = 0 */
+#define CHEXT_INIT_VALUE     (0U)          /* HW init value */
+#define NXLA_INIT_VALUE      (0U)          /* HW init value */
+#define DCTRL_INIT_VALUE     (0x00000001U) /* interrupt output : pulse, round robin mode */
+#define DMARS_INIT_VALUE     (0U)          /* HW init value */
+/* Fixed Setting for CHCFG */
+#define CHCFG_FIXED_VALUE    (0x00000020U) /* register mode, not buffer sweep, interrupt detect when high pulse */
+
+/* Bit Value & Mask */
+/* CHSTAT */
+#define CHSTAT_MASK_SR         (0x00000080U)
+#define CHSTAT_MASK_END        (0x00000020U)
+#define CHSTAT_MASK_ER         (0x00000010U)
+#define CHSTAT_MASK_TACT       (0x00000004U)
+#define CHSTAT_MASK_EN         (0x00000001U)
+/* CHCTRL */
+#define CHCTRL_SET_CLRTC       (0x00000040U)
+#define CHCTRL_SET_CLREND      (0x00000020U)
+#define CHCTRL_SET_SWRST       (0x00000008U)
+#define CHCTRL_SET_CLREN       (0x00000002U)
+#define CHCTRL_SET_SETEN       (0x00000001U)
+/* CHCFG */
+#define CHCFG_SET_REN          (0x40000000U)
+#define CHCFG_MASK_REN         (0x40000000U)
+#define CHCFG_SET_RSW          (0x20000000U)
+#define CHCFG_MASK_RSW         (0x20000000U)
+#define CHCFG_SET_RSEL         (0x10000000U)
+#define CHCFG_MASK_RSEL        (0x10000000U)
+#define CHCFG_SET_DEM          (0x01000000U)
+#define CHCFG_MASK_DEM         (0x01000000U)
+#define CHCFG_MASK_DAD         (0x00200000U)
+#define CHCFG_MASK_SAD         (0x00100000U)
+#define CHCFG_MASK_DDS         (0x000f0000U)
+#define CHCFG_MASK_SDS         (0x0000f000U)
+#define CHCFG_SET_AM_LEVEL     (0x00000100U)
+#define CHCFG_SET_AM_BUS_CYCLE (0x00000200U)
+#define CHCFG_MASK_AM          (0x00000700U)
+#define CHCFG_SET_LVL_EDGE     (0x00000000U)
+#define CHCFG_SET_LVL_LEVEL    (0x00000040U)
+#define CHCFG_MASK_LVL         (0x00000040U)
+#define CHCFG_SET_REQD_SRC     (0x00000000U)
+#define CHCFG_SET_REQD_DST     (0x00000008U)
+#define CHCFG_MASK_REQD        (0x00000008U)
+#define CHCFG_SHIFT_DAD        (21U)
+#define CHCFG_SHIFT_SAD        (20U)
+#define CHCFG_SHIFT_DDS        (16U)
+#define CHCFG_SHIFT_SDS        (12U)
+/* CHEXT */
+#define CHEXT_SET_DCA_NORMAL      (0x00003000U)
+#define CHEXT_SET_DCA_STRONG      (0x00000000U)
+#define CHEXT_SET_DPR_NON_SECURE  (0x00000200U)
+#define CHEXT_SET_SCA_NORMAL      (0x00000030U)
+#define CHEXT_SET_SCA_STRONG      (0x00000000U)
+#define CHEXT_SET_SPR_NON_SECURE  (0x00000002U)
+
+
+/* REQD value in CHCFG is undecided on config table */
+/* used case of a resource is the same and two or more direction value exists.  */
+#define CHCFG_REQD_UNDEFINED   DMA_REQ_MAX
+
+/* Address of area which is the target of setting change */
+#define DMA_EXTERNAL_BUS_START         (0x00000000U)
+#define DMA_EXTERNAL_BUS_END           (0x1FFFFFFFU)
+#define DMA_EXTERNAL_BUS_MIRROR_START  (0x40000000U)
+#define DMA_EXTERNAL_BUS_MIRROR_END    (0x5FFFFFFFU)
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* DRV Status */
+typedef enum
+{
+    DMA_DRV_UNINIT = 0,   /* Uninit */
+    DMA_DRV_INIT   = 1    /* Init */
+} dma_stat_drv_t;
+
+/* Channel Status */
+typedef enum
+{
+    DMA_CH_UNINIT   = 0,   /* Uninit */
+    DMA_CH_INIT     = 1,   /* Init */
+    DMA_CH_OPEN     = 2,   /* Open */
+    DMA_CH_TRANSFER = 4    /* Transfer */
+} dma_stat_ch_t;
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* DMA Register (Common) */
+typedef struct
+{
+    volatile uint32_t  dctrl;            
+    volatile uint32_t  dstat_en;         
+    volatile uint32_t  dstat_er;         
+    volatile uint32_t  dstat_end;        
+    volatile uint32_t  dstat_tc;         
+    volatile uint32_t  dstat_sus;        
+} dma_reg_common_t;
+
+/* DMA Register (every Channel) */
+typedef struct
+{
+    volatile uint32_t  n0sa;        
+    volatile uint32_t  n0da;         
+    volatile uint32_t  n0tb;         
+    volatile uint32_t  n1sa;         
+    volatile uint32_t  n1da;         
+    volatile uint32_t  n1tb;         
+    volatile uint32_t  crsa;         
+    volatile uint32_t  crda;         
+    volatile uint32_t  crtb;         
+    volatile uint32_t  chstat;       
+    volatile uint32_t  chctrl;       
+    volatile uint32_t  chcfg;        
+    volatile uint32_t  chitvl;       
+    volatile uint32_t  chext;        
+    volatile uint32_t  nxla;        
+    volatile uint32_t  crla;         
+} dma_reg_ch_t;
+
+/* Information of Channel */
+typedef struct
+{
+    int_t              ch;                /* Channel Number */
+    dma_stat_ch_t      ch_stat;           /* Channel Status */
+    dma_res_select_t   resource;          /* DMA Transfer Resource */
+    dma_req_dir_t      direction;         /* DMA Transfer Direction */
+    dma_unit_size_t    src_width;         /* DMA Transfer Unit Size (Source) */
+    dma_addr_cnt_t     src_cnt;           /* DMA Address Count (Source) */
+    dma_unit_size_t    dst_width;         /* DMA Transfer Unit Size (Destination) */
+    dma_addr_cnt_t     dst_cnt;           /* DMA Address Count (Destination) */
+    void               *src_addr0;        /* Sorce Address (Next Register Set 0)*/
+    void               *dst_addr0;        /* Destination Address (Next Register Set 0)*/
+    uint32_t           count0;            /* DMA Transfer Size (Next Register Set 0)*/
+    void               *src_addr1;        /* Sorce Address (Next Register Set 1)*/
+    void               *dst_addr1;        /* Destination Address (Next Register Set 1)*/
+    uint32_t           count1;            /* DMA Transfer Size (Next Register Set 1)*/
+    IRQn_Type          end_irq_num;       /* DMA end interrupt number */
+    AIOCB              *p_end_aio;        /* set callback function (DMA end interrupt) */
+    bool_t             next_dma_flag;     /* Setting Flag of Continous DMA */
+    uint32_t           shift_dmars;       /* set SHIFT_DMARS_ODD_CH or SHIFT_DMARS_EVEN_CH */
+    uint32_t           mask_dmars;        /* set MASK_DMA_ODD_CH or MASK_DMARS_EVEN_CH */
+    bool_t             setup_flag;        /* incdicate called DMA_Setup() flag */
+    volatile struct st_dmac_n       *p_dma_ch_reg;     /* DMA Register for every channel */
+    volatile struct st_dmaccommon_n *p_dma_common_reg; /* DMA Register for common */
+    volatile uint32_t           *p_dma_dmars_reg;  /* DMARS Regsiter */
+} dma_info_ch_t;
+
+/* Information of Driver */
+typedef struct
+{
+    dma_stat_drv_t  drv_stat;            /* DRV Status */
+    AIOCB           *p_err_aio;          /* set callback function (DMA error interrupt) */
+    IRQn_Type       err_irq_num;         /* DMA error interrupt number */
+    dma_info_ch_t   info_ch[DMA_CH_NUM]; /* Enable Channel */
+} dma_info_drv_t;
+
+/* DMA Channel Configure Table */
+typedef struct
+{
+    dma_res_select_t   dmars;             /* Set Value for DMARS Register */
+    uint32_t           tm;                /* Set Value for TM Bit (CHCFG Register) */
+    uint32_t           lvl;               /* Set Value for LVL Bit (CHCFG Register) */
+    uint32_t           reqd;              /* Set Value for REQD (CHCFG Register) */
+} dma_ch_cfg_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+dma_info_drv_t *DMA_GetDrvInstance(void);
+dma_info_ch_t  *DMA_GetDrvChInfo(const int_t channel);
+int_t DMA_Initialize(const dma_drv_init_t * const p_dma_init_param);
+int_t DMA_UnInitialize(void);
+int_t DMA_GetFreeChannel(void);
+int_t DMA_GetFixedChannel(const int_t channel);
+void  DMA_CloseChannel(const int_t channel);
+void  DMA_SetParam(const int_t channel, const dma_ch_setup_t * const p_ch_setup,
+                   const dma_ch_cfg_t * const p_ch_cfg, const uint32_t reqd);
+void  DMA_BusParam(const int_t channel, const dma_trans_data_t * const p_dma_data);
+void  DMA_SetData(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                 const uint32_t next_register_set);
+void  DMA_SetNextData(const int_t channel, const dma_trans_data_t * const p_dma_data);
+void  DMA_Start(const int_t channel, const bool_t restart_flag);
+void  DMA_Stop(const int_t channel, uint32_t * const p_remain);
+void  DMA_SetErrCode(const int_t error_code, int32_t * const p_errno);
+
+#endif /* DMA_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/dma/dma_if.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1154 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         dma_if.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* @brief        DMA Driver interface functions
+******************************************************************************/
+
+/*****************************************************************************
+* History : DD.MM.YYYY Version Description
+* : 15.01.2013 1.00 First Release
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "dma.h"
+
+/******************************************************************************
+Private global tables
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Init
+* @brie          Init DMA driver.
+*                Check parameter in this function.
+*
+*                Description:<br>
+*
+* @param[in]     p_dma_init_param :Point of driver init parameter.
+* @param[in,out] p_errno          :Pointer of error code.
+*                                  When pointer is NULL, it isn't set error code.
+*                                  error code -
+*                                  OS error num : Registering handler failed.
+*                                  EPERM : Pointer of callback function which called in DMA 
+*                                          error interrupt handler is NULL.
+*                                  EFAULT : dma_init_param is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called.  */
+int_t R_DMA_Init(const dma_drv_init_t * const p_dma_init_param, int32_t * const p_errno) 
+/* <-IPA M1.1.1 */
+{
+    int_t         retval = ESUCCESS;
+    int_t         result_init;
+    int_t         was_masked;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    
+    if (NULL == p_dma_init_param)
+    {
+        /* set error return value */
+        retval = (EERROR);
+        DMA_SetErrCode(EFAULT, p_errno);
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+        if (NULL == p_dma_init_param->p_aio)
+        /* <-MISRA 1.2 */
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(EPERM, p_errno);
+        }
+    }
+    
+    /* disable all irq */
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif    
+
+    if (ESUCCESS == retval)
+    {
+        result_init = DMA_Initialize(p_dma_init_param);
+        if (ESUCCESS != result_init)
+        {
+            /* set error return value */
+            retval = (EERROR);
+            DMA_SetErrCode(result_init, p_errno);
+        }
+    }
+    
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Init
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_UnInit
+* @brie          UnInit DMA driver.
+*                Check parameter in this function.
+*
+*                Description:<br>
+*
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           OS error num : Unegistering handler failed.
+*                           EACCES : Driver status isn't DMA_DRV_INIT.
+*                           EBUSY : It has been allocated already in channel.
+*                           EFAULT : Channel status is besides the status definded in dma_stat_ch_t.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_UnInit(int32_t * const p_errno) 
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    int_t          result_uninit;
+    dma_info_drv_t *dma_info_drv;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          ch_count;
+    bool_t         ch_stat_check_flag;
+    int_t          was_masked;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    dma_info_drv = DMA_GetDrvInstance();
+    
+    /* disable all irq */
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif    
+
+    /* check driver status */
+    if (ESUCCESS == retval)
+    {
+        if (DMA_DRV_INIT != dma_info_drv->drv_stat)
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EACCES, p_errno);
+        }
+        else
+        {
+            ch_stat_check_flag = false;
+            ch_count = 0;
+            while (false == ch_stat_check_flag)
+            {
+                /* check channel status */
+                dma_info_ch = DMA_GetDrvChInfo(ch_count);
+                if ((DMA_CH_UNINIT != dma_info_ch->ch_stat) &&
+                    (DMA_CH_INIT != dma_info_ch->ch_stat))
+                {
+                    /*  set error return value */
+                    retval = EERROR;
+                    /* check channel status is busy */
+                    switch (dma_info_ch->ch_stat)
+                    {
+                        /* These 2 cases are intentionally combined. */
+                        case DMA_CH_OPEN:
+                        case DMA_CH_TRANSFER:
+                            DMA_SetErrCode(EBUSY, p_errno); 
+                        break;
+                        
+                        default:
+                            DMA_SetErrCode(EFAULT, p_errno);
+                        break;
+                    }
+                }
+                
+                if ((DMA_CH_NUM - 1) == ch_count)
+                {
+                    /* channel status check end */
+                    ch_stat_check_flag = true;
+                }
+                ch_count++;
+            }
+        }
+        /* uninitialize DMA */
+        if (ESUCCESS == retval)
+        {
+            result_uninit = DMA_UnInitialize();
+            if (ESUCCESS != result_uninit)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(result_uninit, p_errno);
+            }
+        }
+    }
+    
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_UnInit
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Alloc
+* @brie          Open DMA channel.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Open channel number.
+*                           If channel is (-1), it looking for free chanel and allocate.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EINVAL : Value of the ch is outside the range of DMA_ALLOC_CH(-1) <= ch < DMA_CH_NUM.
+*                           EACCES : Driver status isn't DMA_DRV_INIT.
+*                           EBUSY : It has been allocated already in channel.
+*                           EMFILE : When looking for a free channel, but a free channel didn't exist.
+*                           ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                           EFAULT: Channel status is besides the status definded in dma_stat_ch_t.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Alloc(const int_t channel, int32_t * const p_errno) 
+/* <-IPA M1.1.1 */
+{
+    int_t           retval = ESUCCESS;
+    int_t           ercd = ESUCCESS;
+    int_t           get_ch_num;
+    dma_info_drv_t  *dma_info_drv;
+    int_t           was_masked;
+
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* check driver status */
+    dma_info_drv = DMA_GetDrvInstance();
+    
+    /* disable all irq */
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif    
+
+    if (ESUCCESS == ercd)
+    {
+        if (DMA_DRV_INIT != dma_info_drv->drv_stat)
+        {
+            /* set error return value */
+            ercd =  EACCES;
+        }
+        else
+        {
+            /* check channel of argment */
+            if ((DMA_ALLOC_CH <= channel) && (channel < DMA_CH_NUM))
+            {
+                if (DMA_ALLOC_CH == channel)
+                {
+                    get_ch_num = DMA_GetFreeChannel();
+                }
+                else
+                {
+                    get_ch_num = DMA_GetFixedChannel(channel);
+                }
+                
+                /* check return number or error number */
+                if ((DMA_ALLOC_CH < get_ch_num) && (get_ch_num < DMA_CH_NUM))
+                {
+                    /* set channel number to return value */
+                    retval = get_ch_num;
+                }
+                else
+                {
+                    /* set error code to error value */
+                    ercd = get_ch_num;
+                }
+            }
+            else
+            {
+                /* set error return value */
+                ercd =  EINVAL;
+            }
+        }
+    }
+    
+    /* occured error check */
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+        DMA_SetErrCode(ercd, p_errno);
+    }
+    
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Alloc
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Free
+* @brie          Close DMA channel.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Close channel number.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF : Channel status is DMA_CH_INIT.
+*                           EINVAL : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EACCES : Driver status isn't DMA_DRV_INIT.
+*                           EBUSY : It has been start DMA transfer in channel.
+*                           ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                           EFAULT: Channel status is besides the status definded in dma_stat_ch_t.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Free(const int_t channel, int32_t *const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t           retval = ESUCCESS;
+    dma_info_drv_t  *dma_info_drv;
+    dma_info_ch_t   *dma_info_ch;
+    int_t           error_code;
+    int_t           was_masked;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+
+    /* disable all irq */
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif    
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+         /* check driver status */
+        dma_info_drv = DMA_GetDrvInstance();
+        
+        if (ESUCCESS == retval)
+        {
+            /* check driver status */
+            if (DMA_DRV_INIT == dma_info_drv->drv_stat)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        DMA_CloseChannel(channel);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                            break;
+                            
+                            case DMA_CH_INIT:
+                                error_code = EBADF;
+                            break;
+                            
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY; 
+                            break;
+                            
+                            default:
+                                error_code = EFAULT; 
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+            else
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EACCES, p_errno);
+            
+            }
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);
+    }
+    
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Free
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Setup
+* @brie          Setup DMA transfer parameter.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Setup channel number.
+* @param[in]     p_ch_setup:Set up parameters.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF : Channel status is DMA_CH_INIT.
+*                           EINVAL : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EBUSY : It has been start DMA transfer in channel.
+*                           ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                           EPERM : The value in p_ch_setup isn't in the right range.
+*                           EFAULT: Channel status is besides the status definded in dma_stat_ch_t. p_ch_setup is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Setup(const int_t channel, const dma_ch_setup_t * const p_ch_setup, 
+                  int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t            retval = ESUCCESS;
+    dma_info_ch_t    *dma_info_ch;
+    int_t            error_code;
+    uint32_t         cfg_table_count;
+    dma_ch_cfg_t     ch_cfg_set_table;
+    uint32_t         set_reqd;
+    bool_t           check_table_flag;
+    int_t            was_masked;
+    
+    /* Resouce Configure Set Table */
+    static const dma_ch_cfg_t ch_cfg_table[DMA_CH_CONFIG_TABLE_NUM] =
+    {
+        {DMA_RS_OSTIM0,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_OSTIM1,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI0A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI1A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI2A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI3A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TGI4A,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI0,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI0,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI1,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI1,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI2,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI2,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI3,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI3,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI4,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI4,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI5,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI5,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI6,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI6,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TXI7,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_RXI7,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_USB0_DMA0,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB0_DMA1,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB1_DMA0,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_USB1_DMA1,  CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_ADEND,      CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IEBBTD,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IEBBTV,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IREADY,     CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_FLDT,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SDHI_0T,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SDHI_0R,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SDHI_1T,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SDHI_1R,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_MMCT,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_MMCR,       CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSITXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSITXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSIRTI2,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SSITXI3,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI3,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SSIRTI4,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SSITXI5,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SSIRXI5,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI0,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI1,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI2,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI2,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI3,    CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI2,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI2,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI3,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI3,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPTI4,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPRI4,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SPDIFTXI,   CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SPDIFRXI,   CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_CMI1,       CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_CMI2,       CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_MLBCI,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_REQD_UNDEFINED},
+        {DMA_RS_SGDEI0,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI1,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI2,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SGDEI3,     CHCFG_SET_AM_LEVEL,     CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCUTXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI0,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_SCUTXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_SCURXI1,    CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI0,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI0,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI1,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI1,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI2,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI2,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_TI3,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_RI3,        CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_LIN0_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_LIN0_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_LIN1_INT_T, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_DST  },
+        {DMA_RS_LIN1_INT_R, CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_EDGE,  CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IFEI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_OFFI0,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  },
+        {DMA_RS_IFEI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_DST  },
+        {DMA_RS_OFFI1,      CHCFG_SET_AM_BUS_CYCLE, CHCFG_SET_LVL_LEVEL, CHCFG_SET_REQD_SRC  }
+    };
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    /* dummy init set_reqd */
+    set_reqd = CHCFG_REQD_UNDEFINED;
+    ch_cfg_set_table = ch_cfg_table[0];
+    
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_ch_setup)
+        {
+            /* check setup parameter */
+            /* check AIOCB pointer */
+            if (NULL == p_ch_setup->p_aio)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM, p_errno);
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer unit size for destination */
+                if (((int_t)p_ch_setup->dst_width <= DMA_UNIT_MIN) || 
+                    ((int_t)p_ch_setup->dst_width >= DMA_UNIT_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer unit size for source */
+                if (((int_t)p_ch_setup->src_width <= DMA_UNIT_MIN) || 
+                    ((int_t)p_ch_setup->src_width >= DMA_UNIT_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA address count direction for destination */
+                if (((int_t)p_ch_setup->dst_cnt <= DMA_ADDR_MIN) || 
+                    ((int_t)p_ch_setup->dst_cnt >= DMA_ADDR_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA address count direction for source */
+                if (((int_t)(p_ch_setup->src_cnt) <= DMA_ADDR_MIN) || 
+                    ((int_t)p_ch_setup->src_cnt >= DMA_ADDR_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer direction */
+                if (((int_t)p_ch_setup->direction <= DMA_REQ_MIN) || 
+                    ((int_t)p_ch_setup->direction >= DMA_REQ_MAX))
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    DMA_SetErrCode(EPERM, p_errno);
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check DMA transfer resouce */
+                check_table_flag = false;
+                cfg_table_count = 0;
+                while (false == check_table_flag)
+                {
+                    if (p_ch_setup->resource == ch_cfg_table[cfg_table_count].dmars)
+                    {
+                        /* check reqd is undefined */ 
+                        if (CHCFG_REQD_UNDEFINED == ch_cfg_table[cfg_table_count].reqd)
+                        {
+                            /* set reqd value on fixed value */
+                            if (DMA_REQ_SRC == p_ch_setup->direction)
+                            {
+                                set_reqd = CHCFG_SET_REQD_SRC;
+                            }
+                            else 
+                            {
+                                set_reqd = CHCFG_SET_REQD_DST;
+                            }
+                        }
+                        else
+                        {
+                            /* set reqd value in channel config table */
+                            set_reqd = ch_cfg_table[cfg_table_count].reqd;
+                        }
+                        /* set channel config table address for DMA_SetParam() */
+                        ch_cfg_set_table = ch_cfg_table[cfg_table_count];
+                        check_table_flag = true;
+                    }
+                    if (false == check_table_flag)
+                    {
+                        /* resource value did not exist in channel config table */
+                        if ((uint32_t)((sizeof(ch_cfg_table)/sizeof(dma_ch_cfg_t)) - 1U) == cfg_table_count)
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode(EPERM, p_errno);
+                            check_table_flag = true;
+                        }
+                        cfg_table_count++;
+                    }
+                }
+            }
+            
+            /* disable all irq */
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif    
+
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        /* set up parameter */
+                        DMA_SetParam(channel, p_ch_setup, &ch_cfg_set_table, set_reqd);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                            break;
+                             
+                            case DMA_CH_INIT:
+                                error_code = EBADF;
+                            break;
+                        
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY; 
+                            break;
+                        
+                            default:
+                                error_code = EFAULT; 
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);        
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_SetParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Start
+* @brie          Start DMA transfer.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :DMA start channel number.
+* @param[in]     p_dma_data:DMA address parameters.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF : Channel status is DMA_CH_INIT.
+*                           EINVAL : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EBUSY : It has been start DMA transfer in channel.
+*                           ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                           EPERM : The value in p_ch_setup isn't in the right range.
+*                           EFAULT: Channel status is besides the status definded in dma_stat_ch_t. p_dma_data is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Start(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                  int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          error_code;
+    int_t          was_masked;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    
+    /* disable all irq */
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif    
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_dma_data)
+        {
+            /* check address parameter */
+            /* check DMA transfer count destination address is 0 */
+            if (0U == p_dma_data->count)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM, p_errno);
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                
+                if (ESUCCESS == retval)
+                {
+                    if (DMA_CH_OPEN == dma_info_ch->ch_stat)
+                    {
+                        /* set bus paramter for DMA */
+                        DMA_BusParam(channel, p_dma_data);
+                        /* set up address parameter */
+                        /* Next register set is 0 */
+                        DMA_SetData(channel, p_dma_data, 0);
+                        /* DMA transfer start */
+                        DMA_Start(channel, false);
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                             break;
+                             
+                             case DMA_CH_INIT:
+                                error_code = EBADF;
+                             break;
+                        
+                            case DMA_CH_TRANSFER:
+                                error_code = EBUSY; 
+                            break;
+                        
+                            default:
+                                error_code = EFAULT; 
+                             break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);        
+    }
+    
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Start
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_NextData
+* @brie          Set continous DMA mode.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Continuous DMA channel number.
+* @param[in,out] p_dma_data:DMA address parameters.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF : Channel status is DMA_CH_INIT.
+*                           EINVAL : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           EBUSY : It has been set continous DMA transfer.
+*                           ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                           EPERM : The value in p_ch_setup isn't in the right range.
+*                           EFAULT: Channel status is besides the status definded in dma_stat_ch_t. p_dma_data is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_NextData(const int_t channel, const dma_trans_data_t * const p_dma_data, 
+                     int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          error_code;
+    int_t          was_masked;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    
+    /* disable all irq */
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif    
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        if (NULL != p_dma_data)
+        {
+            /* check address parameter */
+            /* check DMA transfer count destination address is 0 */
+            if (0U == p_dma_data->count)
+            {
+                /* set error return value */
+                retval = EERROR;
+                DMA_SetErrCode(EPERM, p_errno);
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                dma_info_ch = DMA_GetDrvChInfo(channel);
+                    
+                if (ESUCCESS == retval)
+                {
+                    if ((DMA_CH_OPEN == dma_info_ch->ch_stat) ||
+                        (DMA_CH_TRANSFER == dma_info_ch->ch_stat))
+                    {
+                        if (false == dma_info_ch->next_dma_flag)
+                        {
+                            /* set up address parameter for continous DMA*/
+                            DMA_SetNextData(channel, p_dma_data);
+                        }
+                        else
+                        {
+                            /* set error return value */
+                            retval = EERROR;
+                            DMA_SetErrCode(EBUSY, p_errno);
+                        }
+                    }
+                    else
+                    {
+                        /* set error return value */
+                        retval = EERROR;
+                        switch (dma_info_ch->ch_stat)
+                        {
+                            case DMA_CH_UNINIT:
+                                error_code = ENOTSUP; 
+                            break;
+                            
+                            case DMA_CH_INIT:
+                                error_code = EBADF;
+                            break;
+                            
+                            default:
+                                error_code = EFAULT; 
+                            break;
+                        }
+                        DMA_SetErrCode(error_code, p_errno);
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);        
+    }
+    
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_NextData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_Cancel
+* @brie          Cancel DMA transfer.
+*                Check parameter in this function mainly.
+*
+*                Description:<br>
+*
+* @param[in]     channel   :Cancel DMA channel number.
+* @param[in]    p_remain   :Remain data size of DMA transfer when it stopping.
+* @param[in,out] p_errno   :Pointer of error code
+*                           When pointer is NULL, it isn't set error code.
+*                           error code -
+*                           EBADF : Channel status is DMA_CH_INIT or DMA_CH_OPEN. (DMA stopped)
+*                           EINVAL : Value of the ch is outside the range of (-1) < ch < (DMA_CH_NUM + 1).
+*                           ENOTSUP : Channel status is DMA_CH_UNINIT.
+*                           EFAULT: Channel status is besides the status definded in dma_stat_ch_t. p_remain is NULL.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+int_t R_DMA_Cancel(const int_t channel, uint32_t * const p_remain, int32_t * const p_errno)
+/* <-IPA M1.1.1 */
+{
+    int_t          retval = ESUCCESS;
+    dma_info_ch_t  *dma_info_ch;
+    int_t          error_code;
+    int_t          was_masked;
+    
+    DMA_SetErrCode(ESUCCESS, p_errno);
+    
+    /* disable all irq */
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif    
+
+    /* check channel of argument */
+    if ((0 <= channel) && (channel < DMA_CH_NUM))
+    {
+        /* check whether p_remain is NULL */
+        if (NULL != p_remain)
+        {
+            dma_info_ch = DMA_GetDrvChInfo(channel);
+            
+            if (ESUCCESS == retval)
+            {
+                if (DMA_CH_TRANSFER == dma_info_ch->ch_stat)
+                {
+                    /* set up address parameter for continous DMA*/
+                    DMA_Stop(channel, p_remain);
+                }
+                else
+                {
+                    /* set error return value */
+                    retval = EERROR;
+                    switch (dma_info_ch->ch_stat)
+                    {
+                        case DMA_CH_UNINIT:
+                            error_code = ENOTSUP; 
+                        break;
+                        
+                        case DMA_CH_INIT:
+                            error_code = EBADF;
+                        break;
+                        
+                        case DMA_CH_OPEN:
+                            error_code = EBADF;
+                        break;
+                        
+                        default:
+                            error_code = EFAULT; 
+                        break;
+                    }
+                    DMA_SetErrCode(error_code, p_errno);
+                }
+            }
+        }
+        else
+        {
+            /* set error return value */
+            retval = EERROR;
+            DMA_SetErrCode(EFAULT, p_errno);
+        }
+    }
+    else
+    {
+        /* set error return value */
+        retval = EERROR;
+        DMA_SetErrCode(EINVAL, p_errno);
+    }
+    
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_DMA_Cancel
+******************************************************************************/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/dma/dma_ver.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         dma_ver.c
+* $Rev: 1645 $
+* $Date:: 2015-05-21 10:35:06 +0900#$
+* @brief        DMA Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "dma_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V2.12 -> MAJOR=2, MINOR=12 */
+#define DMA_DRV_VER_MAJOR  (2u)
+#define DMA_DRV_VER_MINOR  (2u)
+
+#define DMA_DRV_VER_MASK   (0xFFu)
+#define DMA_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_DMA_GetVersion
+* @brief         Get DMA driver version.
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_DMA_GetVersion(void)
+{
+    const uint16_t version =
+        ((DMA_DRV_VER_MAJOR & DMA_DRV_VER_MASK) << DMA_DRV_VER_SHIFT)
+        | (DMA_DRV_VER_MINOR & DMA_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_DMA_GetVersion
+******************************************************************************/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/ioif/aioif.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,489 @@
+/******************************************************************************
+ *
+ * $Rev: 1674 $
+ * $Date: 2012-12-18 11:09:19 +0900#$
+ *
+ * Description : ITRON support functions for IOIF Asynchronous I/O header file
+ *
+ * (C) Copyright RENESAS ELECTRONICS EUROPE Ltd 2012 All Rights Reserved
+ *****************************************************************************/
+
+/*************************************************************************
+ System Includes
+*************************************************************************/
+
+#include <r_errno.h>
+#include <cmsis_os.h>
+#include <aioif.h>
+#if(1) /* mbed */
+#include "cmsis.h"
+#else  /* not mbed */
+#include <ipcb.h>
+#include <ioif_aio_helper.h>
+#endif /* end mbed */
+#include <misratypes.h>
+#include "bsp_drv_cmn.h"
+#if defined (__ICCARM__)
+#include <intrinsics.h>
+#include "Renesas_RZ_A1.h"
+#endif
+
+/*************************************************************************
+ OS Resources
+*************************************************************************/
+
+
+/*************************************************************************
+ Functions
+*************************************************************************/
+static void ahf_lock(AHF_S * const ahf);
+static void ahf_unlock(AHF_S * const ahf);
+
+static void ahf_lock(AHF_S * const ahf)
+{
+    if(ahf->flags & AHF_LOCKSEM)
+    {
+        osMutexWait(ahf->semid, 0);
+    }
+    else if (ahf->flags & AHF_LOCKINT)
+    {
+#if defined (__ICCARM__)
+        ahf->saved_int_mask = __disable_irq_iar();
+#else
+        ahf->saved_int_mask = __disable_irq();
+#endif
+    }
+    else
+    {
+        ;   /* MISRA compliance. */
+    }
+}
+
+static void ahf_unlock(AHF_S * const ahf)
+{
+    if(ahf->flags & AHF_LOCKSEM)
+    {
+        osMutexRelease(ahf->semid);
+    }
+    else if (ahf->flags & AHF_LOCKINT)
+    {
+        if (0 == ahf->saved_int_mask)
+        {
+            __enable_irq();
+        }
+    }
+    else
+    {
+        ;   /* MISRA compliance. */
+    }
+}
+
+/***********************************************************************************
+Function Name:         ahf_create
+
+Description:    Creates an empty aio control queue pointer.
+                Creates a mutex if AHF_CREATESEM bit flag is set.
+
+Parameters:     ahf  - aio queue structure pointer.
+                f    - flag indicating that at semaphore is to be created.
+
+Return value:   0 on success.   negative error code on error.
+***********************************************************************************/
+int32_t ahf_create (AHF_S * const ahf, const uint32_t f)
+{
+    osMutexDef_t* p_mutex_def;
+    uint32_t*     p_mutex_data;
+#if defined (__GNUC__)
+    int_t was_masked;
+#endif/*__GNUC__*/
+
+    if (ahf == NULL)
+    {
+        return EFAULT;
+    }
+
+    ahf->head = NULL;
+    ahf->tail = NULL;
+    ahf->flags = f;
+
+    /* create the mutex if required */
+    if (f & AHF_CREATESEM)
+    {
+#if defined (__GNUC__)
+        /* disable all irq */
+        was_masked = __disable_irq();
+#endif/*__GNUC__*/
+        p_mutex_def = calloc(1, sizeof(osMutexDef_t));
+#if defined (__GNUC__)
+        if (0 == was_masked)
+        {
+            /* enable all irq */
+            __enable_irq();
+        }
+#endif/*__GNUC__*/
+        if ( NULL == p_mutex_def )
+        {
+            return ENOMEM;
+        }
+#if defined (__GNUC__)
+        /* disable all irq */
+        was_masked = __disable_irq();
+#endif/*__GNUC__*/
+        p_mutex_data = calloc(3, sizeof(uint32_t));
+#if defined (__GNUC__)
+        if (0 == was_masked)
+        {
+            /* enable all irq */
+            __enable_irq();
+        }
+#endif/*__GNUC__*/
+        if ( NULL == p_mutex_data )
+        {
+#if defined (__GNUC__)
+            /* disable all irq */
+            was_masked = __disable_irq();
+#endif/*__GNUC__*/
+            free(p_mutex_def);
+#if defined (__GNUC__)
+            if (0 == was_masked)
+            {
+                /* enable all irq */
+                __enable_irq();
+            }
+#endif/*__GNUC__*/
+            return ENOMEM;
+        }
+        p_mutex_def->mutex = p_mutex_data;
+        ahf->p_cmtx = p_mutex_def;
+        ahf->semid = osMutexCreate (p_mutex_def);
+        if ( NULL == ahf->semid )
+        {
+#if defined (__GNUC__)
+            /* disable all irq */
+            was_masked = __disable_irq();
+#endif/*__GNUC__*/
+            free(p_mutex_data);
+            free(p_mutex_def);
+#if defined (__GNUC__)
+            if (0 == was_masked)
+            {
+                /* enable all irq */
+                __enable_irq();
+            }
+#endif/*__GNUC__*/
+            return ENOMEM;
+        }
+    }
+
+    return 0;
+}
+
+/***********************************************************************************
+Function Name:         ahf_destroy
+
+Description:    Delete aio control block mutex (if it exists).
+                Note: This function does not delete the aio control block queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   void
+
+***********************************************************************************/
+void ahf_destroy (AHF_S const * const ahf)
+{
+#if defined (__GNUC__)
+    int_t was_masked;
+#endif/*__GNUC__*/
+
+    if (ahf == NULL)
+    {
+        return; 
+    }
+     
+    if (ahf->flags & AHF_CREATESEM)
+    {
+        osMutexDelete (ahf->semid);
+#if defined (__GNUC__)
+        /* disable all irq */
+        was_masked = __disable_irq();
+#endif/*__GNUC__*/
+        free(ahf->p_cmtx->mutex);
+        free(ahf->p_cmtx);
+#if defined (__GNUC__)
+        if (0 == was_masked)
+        {
+            /* enable all irq */
+            __enable_irq();
+        }
+#endif/*__GNUC__*/
+    }
+}
+
+/***********************************************************************************
+Function Name:         ahf_addtail
+
+Description:    Add an aio control block to the queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+                aio  - pointer to queue structure.
+
+Return value:   void
+
+***********************************************************************************/
+void ahf_addtail (AHF_S * const ahf, struct aiocb * const aio)
+{
+    if (ahf == NULL)
+    {
+        return; 
+    }
+     
+    ahf_lock (ahf);
+    if (ahf->tail != NULL)
+    {
+        ahf->tail->pNext = aio;
+    }
+    aio->pPrev = ahf->tail;
+    aio->pNext = NULL;
+    ahf->tail = aio;
+    if (ahf->head == NULL)
+    {
+        /* list was empty */
+        ahf->head = aio;
+    }
+
+    ahf_unlock (ahf);
+}
+
+/***********************************************************************************
+Function Name:         ahf_removehead
+
+Description:    Remove an aio control block from the queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   aio control block, or NULL if queue is empty.
+
+***********************************************************************************/
+struct aiocb *ahf_removehead (AHF_S * const ahf)
+{
+    struct aiocb *aio;
+    
+    if (ahf == NULL)
+    {
+        return(NULL);   
+    }
+     
+    ahf_lock (ahf);
+
+    aio = ahf->head;
+    if (aio != NULL)
+    {
+        ahf->head = aio->pNext;
+        if (aio->pNext != NULL)
+        {
+            aio->pNext->pPrev = NULL;
+        }
+        if (ahf->tail == aio)
+        {
+            /* the list is now empty */
+            ahf->tail = NULL;
+        }
+    }
+
+    ahf_unlock (ahf);
+    return aio;
+}
+
+/***********************************************************************************
+Function Name:         ahf_peekhead
+
+Description:    Get an aio control block from the queue, but do not remove from the queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   aio control block, or NULL if queue is empty.
+
+***********************************************************************************/
+struct aiocb *ahf_peekhead (AHF_S * const ahf)
+{
+    struct aiocb *aio;
+
+    ahf_lock (ahf);
+
+    aio = ahf->head;
+
+    ahf_unlock (ahf);
+    return aio;
+}
+
+/***********************************************************************************
+Function Name:         ahf_cancelall
+
+Description:    Empty an aio control block queue.
+
+Parameters:     ahf  - aio queue structure pointer.
+
+Return value:   void
+
+***********************************************************************************/
+void ahf_cancelall (AHF_S * const ahf)
+{
+    struct aiocb *cur, *next;
+
+    ahf_lock (ahf);
+
+    /* cancel all pending requests */
+    cur = ahf->head;
+    while (cur != NULL)
+    {
+        next = cur->pNext;
+        cur->aio_return = ECANCELED;
+        ahf_complete (ahf, cur);
+        cur = next;
+    }
+    /* mark the list as empty */
+    ahf->head = NULL;
+    ahf->tail = NULL;
+
+    ahf_unlock (ahf);
+}
+
+/***********************************************************************************
+Function Name:         ahf_complete
+
+Description:    Flag that the operation is complete.
+                If required by the sigev_notify variable contents, the calling task is
+                notified.
+                If a notify was setup, it is signalled.
+                
+Parameters:     ahf  - aio queue structure pointer.
+                aio  - pointer to queue structure.
+
+Return value:   0 on success.   negative error code on error.
+
+***********************************************************************************/
+void ahf_complete (AHF_S *ahf, struct aiocb * const aio)
+{
+#if(1) /* mbed */
+#else  /* not mbed */
+    int rv;
+#endif /* end mbed */
+    UNUSED_ARG(ahf);
+
+    if (NULL == aio)
+    {
+        return;
+    }
+
+    /* Flag that the operation is complete */
+    /*  This function must be here
+        because another task may release AIOCB block
+        after the task changed by an iTRON function in the switch statement */
+    aio->aio_complete = 1;
+    switch (aio->aio_sigevent.sigev_notify)
+    {
+    case SIGEV_EVENT:
+         osSignalSet ((osThreadId)aio->aio_sigevent.sigev_value.sival_int,
+             (int32_t)aio->aio_sigevent.sigev_signo);
+        break;
+
+    case SIGEV_THREAD:
+        if (aio->aio_sigevent.sigev_notify_function)
+        {
+            (aio->aio_sigevent.sigev_notify_function)
+                (aio->aio_sigevent.sigev_value);
+        }
+        break;
+
+#if(1) /* mbed */
+#else  /* not mbed */
+    case SIGEV_CALLBACK:
+        rv = ipcb_callback ((ipcb_id_t*)aio->aio_sigevent.sigev_signo, &aio->aio_sigevent);
+        break;
+#endif /* end mbed */
+
+    default:
+        /* No notify function */
+        break;
+
+    }
+
+    /* Wakeup any suspended tasks */
+#if(1) /* mbed */
+#else  /* not mbed */
+    aio_complete_suspended(aio);
+#endif /* end mbed */
+}
+
+/***********************************************************************************
+Function Name:         ahf_cancel
+
+Description:    Remove an aio control block from the queue.
+                Signal completion to the calling task and wake it up.
+                If aio is NULL, cancel all.
+                
+Parameters:     ahf  - aio queue structure pointer.
+                aio  - pointer to queue structure.
+
+Return value:   0 on success.   negative error code on error.
+
+***********************************************************************************/
+int32_t ahf_cancel (AHF_S * const ahf, struct aiocb * const aio)
+{
+    struct aiocb *cur;
+    int32_t rv = EINVAL;
+
+    if (ahf == NULL)
+    {
+        return EFAULT;  
+    }
+     
+    /* If aio is NULL, must cancel all. */
+    if(NULL == aio)
+    {
+        ahf_cancelall(ahf);
+        rv = 0;
+    }
+    
+    else
+    {
+        ahf_lock (ahf);
+
+        cur = ahf->head;
+        while ((cur != NULL) && (cur != aio))
+        {
+            cur = cur->pNext;
+        }
+
+        if (cur == aio)
+        {
+            if (aio->pPrev != NULL)
+            {
+                aio->pPrev->pNext = aio->pNext;
+            }
+
+            if (aio->pNext != NULL)
+            {
+                aio->pNext->pPrev = aio->pPrev;
+            }
+
+            if (ahf->head == cur)
+            {
+                ahf->head = cur->pNext;
+            }
+
+            if (ahf->tail == cur)
+            {
+                ahf->tail = cur->pPrev;
+            }
+
+            cur->aio_return = ECANCELED;
+            ahf_complete (ahf, aio);
+            rv = 0;
+        }
+
+        ahf_unlock (ahf);
+    }
+    return rv;
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/scux/scux.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,2841 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* @brief        SCUX Driver functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+
+#if(1) /* mbed */
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define INIT_WAIT_TIME_MSEC (1)
+#define INIT_WAIT_NUM       (1000U)
+
+#endif /* end mbed */
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/* ->MISRA 8.8 This description is based on the way to fill out OS defined. */
+/* ->IPA M2.2.2, MISRA 8.10 This description is based on the way to fill out OS defined. */
+osSemaphoreDef(scux_ch0_access);
+osSemaphoreDef(scux_ch1_access);
+osSemaphoreDef(scux_ch2_access);
+osSemaphoreDef(scux_ch3_access);
+
+osSemaphoreDef(scux_ssif_ch0_access);
+osSemaphoreDef(scux_ssif_ch1_access);
+osSemaphoreDef(scux_ssif_ch2_access);
+osSemaphoreDef(scux_ssif_ch3_access);
+osSemaphoreDef(scux_ssif_ch4_access);
+osSemaphoreDef(scux_ssif_ch5_access);
+
+osSemaphoreDef(scux_shared_access);
+/* <-MISRA 8.10, IPA M2.2.2 */
+/* <-MISRA 8.8 */
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/* driver management infrmation */
+static scux_info_drv_t gb_scux_info_drv = {
+    SCUX_DRV_UNINIT,
+    {
+        {SCUX_CH_0, false, 0, SCUX_CH_UNINIT}, /* ch0 */
+        {SCUX_CH_1, false, 0, SCUX_CH_UNINIT}, /* ch1 */
+        {SCUX_CH_2, false, 0, SCUX_CH_UNINIT}, /* ch2 */
+        {SCUX_CH_3, false, 0, SCUX_CH_UNINIT}  /* ch3 */
+    }
+};
+
+/* SSIF management information */
+static scux_ssif_info_t gb_scux_ssif_info[SCUX_SSIF_CH_NUM];
+
+/* ->MISRA 11.3, 11.4 11.5 This cast is needed for register access. */
+/* address table of register set for each SCUX channel */
+static scux_reg_info_t p_scux_ch_reg_addr_table[SCUX_CH_NUM] = {
+    {
+        &SCUX_FROM_DVUIR_DVU0_0,
+        &SCUX_FROM_SRCIR0_2SRC0_0, 
+        &SCUX_FROM_FFUIR_FFU0_0, 
+        &SCUX_FROM_FFDIR_FFD0_0, 
+        &SCUX_FROM_OPCIR_OPC0_0, 
+        &SCUX_FROM_IPCIR_IPC0_0,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBAR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD0_CIM,
+        &SCUXDMATU0_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL0_CIM,
+        &SCUXFUTSEL0_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL0_CIM,
+        &SCUXMIXRSEL_CIM
+    },
+    {
+        &SCUX_FROM_DVUIR_DVU0_1, 
+        &SCUX_FROM_SRCIR0_2SRC0_0, 
+        &SCUX_FROM_FFUIR_FFU0_1, 
+        &SCUX_FROM_FFDIR_FFD0_1, 
+        &SCUX_FROM_OPCIR_OPC0_1, 
+        &SCUX_FROM_IPCIR_IPC0_1,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBBR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD1_CIM,
+        &SCUXDMATU1_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL1_CIM,
+        &SCUXFUTSEL1_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL1_CIM,
+        &SCUXMIXRSEL_CIM
+    },
+    {
+        &SCUX_FROM_DVUIR_DVU0_2, 
+        &SCUX_FROM_SRCIR0_2SRC0_1, 
+        &SCUX_FROM_FFUIR_FFU0_2, 
+        &SCUX_FROM_FFDIR_FFD0_2, 
+        &SCUX_FROM_OPCIR_OPC0_2, 
+        &SCUX_FROM_IPCIR_IPC0_2,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBCR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD2_CIM,
+        &SCUXDMATU2_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL2_CIM,
+        &SCUXFUTSEL2_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL2_CIM,
+        &SCUXMIXRSEL_CIM
+    },
+    {
+        &SCUX_FROM_DVUIR_DVU0_3, 
+        &SCUX_FROM_SRCIR0_2SRC0_1, 
+        &SCUX_FROM_FFUIR_FFU0_3, 
+        &SCUX_FROM_FFDIR_FFD0_3, 
+        &SCUX_FROM_OPCIR_OPC0_3, 
+        &SCUX_FROM_IPCIR_IPC0_3,
+        &SCUXMIXIR_MIX0_0,
+        &SCUXMADIR_MIX0_0,
+        &SCUXMIXBR_MIX0_0,
+        &SCUXMIXMR_MIX0_0,
+        &SCUXMVPDR_MIX0_0,
+        &SCUXMDBDR_MIX0_0,
+        &SCUXMDBER_MIX0_0,
+        &SCUXMIXSR_MIX0_0,
+        &SCUXSWRSR_CIM,
+        &SCUXDMACR_CIM,
+        &SCUXDMATD3_CIM,
+        &SCUXDMATU3_CIM,
+        &SCUXSSIRSEL_CIM,
+        &SCUXFDTSEL3_CIM,
+        &SCUXFUTSEL3_CIM,
+        &SCUXSSIPMD_CIM,
+        &SCUXSSICTRL_CIM,
+        &SCUXSRCRSEL3_CIM,
+        &SCUXMIXRSEL_CIM
+    }
+};
+/* <-MISRA 11.3, 11.4 11.5 */
+    
+/* ->MISRA 11.3 This cast is needed for register access. */
+/* address table of register set for each SSIF channel */
+static volatile struct st_ssif * const p_scux_ssif_ch_reg_addr[SCUX_SSIF_CH_NUM] = 
+{ 
+    &SSIF0,
+    &SSIF1,
+    &SSIF2,
+    &SSIF3,
+    &SSIF4,
+    &SSIF5
+};
+/* <-MISRA 11.3 */
+    
+/* SCUX semaphore table define */
+static const osSemaphoreDef_t * const p_semdef_ch_scux_access[SCUX_CH_NUM] = 
+{ 
+    osSemaphore(scux_ch0_access),
+    osSemaphore(scux_ch1_access),
+    osSemaphore(scux_ch2_access),
+    osSemaphore(scux_ch3_access)
+};
+    
+/* SSIF semaphore table define */
+static const osSemaphoreDef_t * const p_semdef_ch_scux_ssif_access[SCUX_SSIF_CH_NUM] = 
+{ 
+    osSemaphore(scux_ssif_ch0_access),
+    osSemaphore(scux_ssif_ch1_access),
+    osSemaphore(scux_ssif_ch2_access),
+    osSemaphore(scux_ssif_ch3_access),
+    osSemaphore(scux_ssif_ch4_access),
+    osSemaphore(scux_ssif_ch5_access)
+};
+
+/* write DMA resource define */
+static const dma_res_select_t gb_dma_res_select_tx[SCUX_CH_NUM] =
+{
+    DMA_RS_SCUTXI0,
+    DMA_RS_SCUTXI1,
+    DMA_RS_SCUTXI2,
+    DMA_RS_SCUTXI3
+};
+   
+/* read DMA resource define */
+static const dma_res_select_t gb_dma_res_select_rx[SCUX_CH_NUM] =
+{
+    DMA_RS_SCURXI0,
+    DMA_RS_SCURXI1,
+    DMA_RS_SCURXI2,
+    DMA_RS_SCURXI3
+}; 
+
+/* write dummy data buffer */
+static uint8_t gb_scux_write_dummy_buf[SCUX_DUMMY_BUF_SIZE];
+   
+/* read dummy data buffer */
+static uint8_t gb_scux_read_dummy_buf[SCUX_DUMMY_BUF_SIZE];
+
+/******************************************************************************
+ Function prototypes
+******************************************************************************/
+ 
+static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT]);
+static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch);
+static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag);
+static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch);
+#if(1) /* mbed */
+static int_t SCUX_CmnUnInitialize(void);
+#endif /* end mbed */
+
+/**************************************************************************//**
+* Function Name: SCUX_GetDrvInstance
+* @brief         Get pointer of gb_scux_info_drv.
+*
+*                Description:<br>
+*                
+* @param         None. 
+* @retval        pointer of gb_scux_info_drv -
+*                  driver instance.
+******************************************************************************/
+
+scux_info_drv_t *SCUX_GetDrvInstance(void)
+{
+    
+    return &gb_scux_info_drv;
+}
+
+/******************************************************************************
+End of function SCUX_GetDrv_Instance
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_GetDrvChInfo
+* @brief         gb_scux_info_drv.info_ch[channel].
+*
+*                Description:<br>
+*                
+* @param[in]     channel information number. 
+* @retval        pointer of gb_scux_info_drv -
+*                  pointer of channel information.
+******************************************************************************/
+
+scux_info_ch_t *SCUX_GetDrvChInfo(const int_t channel)
+{
+    
+    return &gb_scux_info_drv.info_ch[channel];
+}
+
+/******************************************************************************
+End of function SCUX_GetDrvChInfo
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_GetSsifChInfo
+* @brief         gb_scux_ssif_info.channel.
+*
+*                Description:<br>
+*                
+* @param[in]     SSIF channel number. 
+* @retval        pointer of gb_scux_ssif_info -
+*                  pointer of SSIF information.
+******************************************************************************/
+
+scux_ssif_info_t *SCUX_GetSsifChInfo(const int_t channel)
+{
+    
+    return &gb_scux_ssif_info[channel];
+}
+
+/******************************************************************************
+End of function SCUX_GetSsifChInfo
+******************************************************************************/
+
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: SCUX_InitializeOne
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :initialize channel number.
+* @param[in]     p_scux_init_param :Initialize parameter for SCUX. 
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+*                    error code -
+*                       ENOMEM : Making semaphore is failed.
+*                       EFAULT : Internal error is occured.
+******************************************************************************/
+int_t SCUX_InitializeOne(const int_t channel, const scux_channel_cfg_t * const p_scux_init_param)
+{
+    int_t    retval = ESUCCESS;
+    osStatus sem_ercd;
+    int_t    scux_ch_count;
+    int_t    audio_ch_count;
+    scux_ssif_ch_num_t    ssif_ch_count;
+    uint32_t cpg_value;
+    bool_t   init_shared_flag = false;
+    int_t    was_masked;
+    volatile uint8_t dummy_buf;
+    uint32_t scux_init_count;
+    int_t    uninit_ercd;
+    bool_t   init_start_flag = false;
+    bool_t   uninit_all_flag = false;
+    uint32_t i;
+
+    if (NULL == p_scux_init_param)
+    {
+        retval = EFAULT;
+    }
+    else if (false == p_scux_init_param->enabled)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* init channel management information */
+        scux_ch_count = channel;
+
+        for (i = 0; ((i < INIT_WAIT_NUM) && (false == init_start_flag)); i++)
+        {
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif
+
+            if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
+            {
+                /* already scux driver shared information is initialized */
+                init_shared_flag = true;
+
+                /* enable the channel */
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
+
+                init_start_flag = true;
+            }
+            else if (SCUX_DRV_UNINIT == gb_scux_info_drv.drv_stat)
+            {
+                /* change the status to scux initialization running */
+                gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
+
+                for (scux_init_count = SCUX_CH_0; scux_init_count < SCUX_CH_NUM; scux_init_count++)
+                {
+                    gb_scux_info_drv.info_ch[scux_init_count].enabled = false;
+                    gb_scux_info_drv.info_ch[scux_init_count].ch_stat = SCUX_CH_UNINIT;
+
+                    gb_scux_info_drv.info_ch[scux_init_count].sem_ch_scux_access = NULL;
+                }
+
+                for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                {
+                    gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
+                }
+
+                gb_scux_info_drv.shared_info.sem_shared_access = NULL;
+
+                /* enable the channel */
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
+
+                init_start_flag = true;
+            }
+            else
+            {
+                /* do nothing : SCUX_DRV_INIT_RUNNING */
+            }
+
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }
+
+            if (false == init_start_flag)
+            {
+                /* wait for the change of drv_stat to SCUX_DRV_INIT */
+                (void)osDelay(INIT_WAIT_TIME_MSEC);
+            }
+        }
+
+        if (false == init_start_flag)
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            {
+    
+                /* copy parameter */
+                /* set interrupt parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param->int_level;
+                        
+                /* set route parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param->route;
+                
+                /* set SRC paramter */
+                SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param->src_cfg);
+                
+                /* init SCUX parameter */
+                if ((SCUX_CH_0 == scux_ch_count) || (SCUX_CH_1 == scux_ch_count))
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH0_1;
+                }
+                else
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH2_3;
+                }
+                gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_tx = gb_dma_res_select_tx[scux_ch_count];
+                gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_rx = gb_dma_res_select_rx[scux_ch_count];
+                gb_scux_info_drv.info_ch[scux_ch_count].futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].err_stat_backup = ESUCCESS;
+                
+                /* init DVU parameter */
+                for (audio_ch_count = SCUX_AUDIO_CH_0; audio_ch_count < SCUX_AUDIO_CH_MAX; audio_ch_count++)
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch_count] = false; 
+                }
+                gb_scux_info_drv.info_ch[scux_ch_count].dvu_setup = false;
+             
+                if (false == init_shared_flag)
+                {
+                    /* init MIX parameter */
+                    gb_scux_info_drv.shared_info.mix_setup = false;
+                    gb_scux_info_drv.shared_info.mix_run_ch = 0U;
+                    gb_scux_info_drv.shared_info.mix_ssif_ch = 0U;
+                    
+                    /* init SSIF parameter */
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].ssif_setup = false;
+                        gb_scux_ssif_info[ssif_ch_count].ssif_cfg.ssif_ch_num = ssif_ch_count;
+                        gb_scux_ssif_info[ssif_ch_count].scux_channel = 0;
+                        gb_scux_ssif_info[ssif_ch_count].pin_mode = SCUX_PIN_MODE_INDEPEND;
+                    }
+                    
+                    /* init regsiter store value */
+                    gb_scux_info_drv.shared_info.ssictrl_cim_value = SSICTRL_CIM_INIT_VALUE;
+                }
+            
+                /* set register address */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg = &p_scux_ch_reg_addr_table[scux_ch_count];
+                                       
+                if (false == init_shared_flag) {
+#if defined (__ICCARM__)
+                    was_masked = __disable_irq_iar();
+#else
+                    was_masked = __disable_irq();
+#endif
+
+                    /* supply clock for SCUX */
+                    cpg_value = (uint32_t)CPG.STBCR8 & ~(CPG_STBCR8_BIT_MSTP81);
+                    CPG.STBCR8 = (uint8_t)cpg_value;
+                    dummy_buf = CPG.STBCR8;
+                    
+                    if (0 == was_masked)
+                    {
+                        __enable_irq();
+                    }
+
+                    /* software reset */
+                    SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
+                    SCUX.SWRSR_CIM |= SWRSR_CIM_SWRST_SET;
+                }
+                
+                /* init DVU register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
+                
+                /* init SRC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 = SRCIRR_2SRC0_INIT_VALUE;
+                
+                /* init FFU register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
+                
+                /* init FFD register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+                
+                /* init OPC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
+    
+                /* init IPC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
+    
+                /* init MIX register for each channel */
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
+                
+                /* init CIM register for each channel */
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
+                
+                /* init shared register */
+                if (false == init_shared_flag)
+                {
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->dmacr_cim) = DMACR_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssirsel_cim) = SSIRSEL_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssipmd_cim) = SSIPMD_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssictrl_cim) = SSICTRL_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
+                }
+                
+                if (false == init_shared_flag)
+                {
+                    /* set SSIF register */
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].p_scux_ssif_reg = p_scux_ssif_ch_reg_addr[ssif_ch_count];
+                    }
+                }
+            
+                /* set  semaphore parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = osSemaphoreCreate(p_semdef_ch_scux_access[scux_ch_count], 1);
+                if (NULL == gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
+                {
+                     retval = ENOMEM;
+                }
+                if ((ESUCCESS == retval) && (false == init_shared_flag))
+                {
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ((ssif_ch_count < SCUX_SSIF_CH_NUM) && (ESUCCESS == retval)); ssif_ch_count++) 
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = osSemaphoreCreate(p_semdef_ch_scux_ssif_access[ssif_ch_count], 1);
+                        if (NULL == gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
+                        {
+                            retval = ENOMEM;
+                        }
+                    }
+                }
+                if ((ESUCCESS == retval) && (false == init_shared_flag))
+                {
+                    gb_scux_info_drv.shared_info.sem_shared_access = osSemaphoreCreate(osSemaphore(scux_shared_access), 1);
+                    if (NULL == gb_scux_info_drv.shared_info.sem_shared_access)
+                    {
+                        retval = ENOMEM;
+                    }
+                }
+                
+                
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_INIT;
+            }
+
+            if (ESUCCESS != retval)
+            {
+                /* uninit each resouces */
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+
+                if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
+                {
+                    /* semaphore delete */
+                    sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+                    /* semaphore error check */
+                    if (osOK != sem_ercd)
+                    {
+                        /* set error return value */
+                        retval = EFAULT;
+                    }
+
+                    gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
+                }
+
+#if defined (__ICCARM__)
+                was_masked = __disable_irq_iar();
+#else
+                was_masked = __disable_irq();
+#endif
+
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+
+                for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
+                {
+                    if (false != gb_scux_info_drv.info_ch[i].enabled)
+                    {
+                        break;
+                    }
+                }
+
+                if (SCUX_CH_NUM == i)
+                {
+                    gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
+                    uninit_all_flag = true;
+                }
+
+                if (0 == was_masked)
+                {
+                    __enable_irq();
+                }
+
+                if (false != uninit_all_flag)
+                {
+                    /* uninitialize driver infomation */
+                    uninit_ercd = SCUX_CmnUnInitialize();
+                    if (ESUCCESS != uninit_ercd)
+                    {
+                        retval = uninit_ercd;
+                    }
+
+                    gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+                }
+            }
+            else
+            {
+                gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_InitializeOne
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_UnInitializeOne
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :unInitialize channel number.
+* @retval        None.
+******************************************************************************/
+void SCUX_UnInitializeOne(const int_t channel)
+{
+    osStatus sem_ercd;
+    int_t    ercd;
+    int_t    scux_ch_count;
+    int_t    ssif_ch_count;
+    bool_t   uninit_all_flag = false;
+    uint32_t i;
+    int_t    was_masked;
+
+    scux_ch_count = channel;
+    if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+    {
+        /* check ch_stat whether going transfer */
+        if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) && 
+            (SCUX_CH_INIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
+            (SCUX_CH_STOP != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat))
+        {
+            /* The exclusive access control (interrupt disabled) starts */
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif
+
+            /* This exclusive access control ends in the SCUX_IoctlClearStop */
+            /* call the __enable_irq in the SCUX_IoctlClearStop */
+            ercd = SCUX_IoctlClearStop(scux_ch_count, was_masked);
+            if (ESUCCESS != ercd)
+            {
+                /* NON_NOTICE_ASSERT: SCUX stop failed */
+            }
+            
+            ercd = R_DMA_Free(gb_scux_info_drv.info_ch[scux_ch_count].dma_tx_ch, NULL);
+            if (ESUCCESS != ercd)
+            {
+                 /* NON_NOTICE_ASSERT: DMA release failed */
+            }
+        }
+    }
+    
+    if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+    {
+        if (gb_scux_info_drv.info_ch[scux_ch_count].ch_stat == SCUX_CH_UNINIT)
+        {
+            /* NON_NOTICE_ASSERT: abnormal status */
+        }
+        
+        /* uninit each resouces */
+        gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+        
+        if (NULL != gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
+        {
+            /* delete each semaphore  */
+            sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+
+            sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+
+            gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
+        }
+        
+        /* delete queue */
+        ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
+        ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
+        ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
+        ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
+    }
+
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif
+
+    gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+
+    for (i = SCUX_CH_0; i < SCUX_CH_NUM; i++)
+    {
+        if (false != gb_scux_info_drv.info_ch[i].enabled)
+        {
+            break;
+        }
+    }
+
+    if (SCUX_CH_NUM == i)
+    {
+        if (SCUX_DRV_INIT == gb_scux_info_drv.drv_stat)
+        {
+            gb_scux_info_drv.drv_stat = SCUX_DRV_INIT_RUNNING;
+            uninit_all_flag = true;
+        }
+    }
+
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    if (false != uninit_all_flag)
+    {
+        for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
+        {
+            if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
+            {
+                sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* NON_NOTICE_ASSERT: semaphore error */
+                }
+            }
+        }
+
+        if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
+        {
+            sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+        }
+
+        /* uninitialize driver infomation */
+        (void)SCUX_CmnUnInitialize();
+
+        gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+    }
+}
+
+/******************************************************************************
+End of function SCUX_UnInitializeOne
+******************************************************************************/
+#endif /* end mbed */
+
+/**************************************************************************//**
+* Function Name: SCUX_Initialize
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     p_scux_init_param :Initialize parameter for SCUX. 
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+*                    error code -
+*                       ENOMEM : Making semaphore is failed.
+*                       EFAULT : Internal error is occured.
+******************************************************************************/
+int_t SCUX_Initialize(const scux_channel_cfg_t * const p_scux_init_param)
+{
+    int_t    retval = ESUCCESS;
+    osStatus sem_ercd;
+    int_t    scux_ch_count;
+    int_t    audio_ch_count;
+    scux_ssif_ch_num_t    ssif_ch_count;
+    uint32_t cpg_value;
+    bool_t   init_shared_flag = false;
+    int_t    was_masked;
+    volatile uint8_t dummy_buf;
+
+    if (NULL == p_scux_init_param)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* init channel management information */
+        for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+        {
+            if (false == p_scux_init_param[scux_ch_count].enabled)
+            {
+                /* set disable parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+            }
+            else
+            {
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = true;
+    
+                /* copy parameter */
+                /* set interrupt parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].int_level = p_scux_init_param[scux_ch_count].int_level;
+                        
+                /* set route parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].route_set = p_scux_init_param[scux_ch_count].route;
+                
+                /* set SRC paramter */
+                SCUX_IoctlSetSrcCfg(scux_ch_count, &p_scux_init_param[scux_ch_count].src_cfg);
+                
+                /* init SCUX parameter */
+                if ((SCUX_CH_0 == scux_ch_count) || (SCUX_CH_1 == scux_ch_count))
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH0_1;
+                }
+                else
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].fifo_size = SCUX_FIFO_SIZE_CH2_3;
+                }
+                gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_tx = gb_dma_res_select_tx[scux_ch_count];
+                gb_scux_info_drv.info_ch[scux_ch_count].dma_resource_rx = gb_dma_res_select_rx[scux_ch_count];
+                gb_scux_info_drv.info_ch[scux_ch_count].futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].err_stat_backup = ESUCCESS;
+                
+                /* init DVU parameter */
+                for (audio_ch_count = SCUX_AUDIO_CH_0; audio_ch_count < SCUX_AUDIO_CH_MAX; audio_ch_count++)
+                {
+                    gb_scux_info_drv.info_ch[scux_ch_count].dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch_count] = false; 
+                }
+                gb_scux_info_drv.info_ch[scux_ch_count].dvu_setup = false;
+             
+                if (false == init_shared_flag)
+                {
+                    /* init MIX parameter */
+                    gb_scux_info_drv.shared_info.mix_setup = false;
+                    gb_scux_info_drv.shared_info.mix_run_ch = 0U;
+                    gb_scux_info_drv.shared_info.mix_ssif_ch = 0U;
+                    
+                    /* init SSIF parameter */
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].ssif_setup = false;
+                        gb_scux_ssif_info[ssif_ch_count].ssif_cfg.ssif_ch_num = ssif_ch_count;
+                        gb_scux_ssif_info[ssif_ch_count].scux_channel = 0;
+                        gb_scux_ssif_info[ssif_ch_count].pin_mode = SCUX_PIN_MODE_INDEPEND;
+                    }
+                    
+                    /* init regsiter store value */
+                    gb_scux_info_drv.shared_info.ssictrl_cim_value = SSICTRL_CIM_INIT_VALUE;
+                }
+            
+                /* set register address */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg = &p_scux_ch_reg_addr_table[scux_ch_count];
+                                       
+                if (false == init_shared_flag) {
+#if defined (__ICCARM__)
+                    was_masked = __disable_irq_iar();
+#else
+                    was_masked = __disable_irq();
+#endif
+
+                    /* supply clock for SCUX */
+                    cpg_value = (uint32_t)CPG.STBCR8 & ~(CPG_STBCR8_BIT_MSTP81);
+                    CPG.STBCR8 = (uint8_t)cpg_value;
+                    dummy_buf = CPG.STBCR8;
+                    
+                    if (0 == was_masked)
+                    {
+                        __enable_irq();
+                    }
+
+                    /* software reset */
+                    SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
+                    SCUX.SWRSR_CIM |= SWRSR_CIM_SWRST_SET;
+                }
+                
+                /* init DVU register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
+                
+                /* init SRC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 = SRCIRR_2SRC0_INIT_VALUE;
+                
+                /* init FFU register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
+                
+                /* init FFD register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+                
+                /* init OPC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
+    
+                /* init IPC register */
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
+                gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
+    
+                /* init MIX register for each channel */
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
+                
+                /* init CIM register for each channel */
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
+                *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
+                
+                /* init shared register */
+                if (false == init_shared_flag)
+                {
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->dmacr_cim) = DMACR_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssirsel_cim) = SSIRSEL_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssipmd_cim) = SSIPMD_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->ssictrl_cim) = SSICTRL_CIM_INIT_VALUE;
+                    *(gb_scux_info_drv.info_ch[scux_ch_count].p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
+                }
+                
+                if (false == init_shared_flag)
+                {
+                    /* set SSIF register */
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++)
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].p_scux_ssif_reg = p_scux_ssif_ch_reg_addr[ssif_ch_count];
+                    }
+                }
+            
+                /* set  semaphore parameter */
+                gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = osSemaphoreCreate(p_semdef_ch_scux_access[scux_ch_count], 1);
+                if (NULL == gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access)
+                {
+                     retval = ENOMEM;
+                }
+                if ((ESUCCESS == retval) && (false == init_shared_flag))
+                {
+                    for (ssif_ch_count = SCUX_SSIF_CH_0; ((ssif_ch_count < SCUX_SSIF_CH_NUM) && (ESUCCESS == retval)); ssif_ch_count++) 
+                    {
+                        gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = osSemaphoreCreate(p_semdef_ch_scux_ssif_access[ssif_ch_count], 1);
+                        if (NULL == gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
+                        {
+                            retval = ENOMEM;
+                        }
+                    }
+                }
+                if ((ESUCCESS == retval) && (false == init_shared_flag))
+                {
+                    gb_scux_info_drv.shared_info.sem_shared_access = osSemaphoreCreate(osSemaphore(scux_shared_access), 1);
+                    if (NULL == gb_scux_info_drv.shared_info.sem_shared_access)
+                    {
+                        retval = ENOMEM;
+                    }
+                }
+                
+                if (false == init_shared_flag)
+                {
+                    init_shared_flag = true;
+                }
+                
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_INIT;
+            }
+        }
+    }
+    
+    if (ESUCCESS != retval)
+    {
+        for (scux_ch_count = SCUX_SSIF_CH_0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+        {
+            if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+            {
+                /* semaphore delete */
+                sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set error return value */
+                    retval = EFAULT;
+                }
+                
+                gb_scux_info_drv.info_ch[scux_ch_count].enabled = false;
+                gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+            }
+        }
+        
+        for (ssif_ch_count = SCUX_SSIF_CH_0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
+        {
+            sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                retval = EFAULT;
+            }
+        }
+                
+        sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* set error return value */
+            retval = EFAULT;
+        }
+        
+        gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+    }
+    else
+    {
+        gb_scux_info_drv.drv_stat = SCUX_DRV_INIT;
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_Initialize
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_UnInitialize
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     None. 
+* @retval        None.
+******************************************************************************/
+void SCUX_UnInitialize(void)
+{
+    osStatus sem_ercd;
+    int_t    ercd;
+    int_t    scux_ch_count;
+    int_t    ssif_ch_count;
+    uint32_t cpg_value;
+    int_t    was_masked;
+
+    for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+    {
+        if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+        {
+            /* check ch_stat whether going transfer */
+            if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) && 
+                (SCUX_CH_INIT != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat) &&
+                (SCUX_CH_STOP != gb_scux_info_drv.info_ch[scux_ch_count].ch_stat))
+            {
+#if defined (__ICCARM__)
+                was_masked = __disable_irq_iar();
+#else
+                was_masked = __disable_irq();
+#endif
+
+                /* This exclusive access control ends in the SCUX_IoctlClearStop */
+                ercd = SCUX_IoctlClearStop(scux_ch_count, was_masked);
+                if (ESUCCESS != ercd)
+                {
+                    /* NON_NOTICE_ASSERT: SCUX stop failed */
+                }
+                
+                ercd = R_DMA_Free(gb_scux_info_drv.info_ch[scux_ch_count].dma_tx_ch, NULL);
+                if (ESUCCESS != ercd)
+                {
+                     /* NON_NOTICE_ASSERT: DMA release failed */
+                }
+            }
+        }
+    }
+    
+    /* software reset */
+    SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
+
+    for (scux_ch_count = 0; scux_ch_count < SCUX_CH_NUM; scux_ch_count++)
+    {
+        if (false != gb_scux_info_drv.info_ch[scux_ch_count].enabled)
+        {
+            if (gb_scux_info_drv.info_ch[scux_ch_count].ch_stat == SCUX_CH_UNINIT)
+            {
+                /* NON_NOTICE_ASSERT: abnormal status */
+            }
+            
+            /* uninit each resouces */
+            gb_scux_info_drv.info_ch[scux_ch_count].ch_stat = SCUX_CH_UNINIT;
+            
+            /* delete each semaphore  */
+            sem_ercd = osSemaphoreRelease(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+            
+            sem_ercd = osSemaphoreDelete(gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* NON_NOTICE_ASSERT: semaphore error */
+            }
+            
+            gb_scux_info_drv.info_ch[scux_ch_count].sem_ch_scux_access = NULL;
+            
+            /* delete queue */
+            ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
+            ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].tx_que);
+            ahf_cancelall(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
+            ahf_destroy(&gb_scux_info_drv.info_ch[scux_ch_count].rx_que);
+        }
+    }
+
+    for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
+    {
+        sem_ercd = osSemaphoreRelease(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* NON_NOTICE_ASSERT: semaphore error */
+        }
+            
+        sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* NON_NOTICE_ASSERT: semaphore error */
+        }
+            
+        gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
+    }
+            
+    sem_ercd = osSemaphoreRelease(gb_scux_info_drv.shared_info.sem_shared_access);
+    /* semaphore error check */
+    if (osOK != sem_ercd)
+    {
+        /* NON_NOTICE_ASSERT: semaphore error */
+    }
+            
+    sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
+    /* semaphore error check */
+    if (osOK != sem_ercd)
+    {
+        /* NON_NOTICE_ASSERT: semaphore error */
+    }
+            
+    gb_scux_info_drv.shared_info.sem_shared_access = NULL;
+         
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif
+
+    /* stop clock for SCUX */
+    cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
+    CPG.STBCR8 = (uint8_t)cpg_value;
+          
+    if (0 == was_masked)
+    {
+        /* enable all irq */
+        __enable_irq();
+    }
+
+    gb_scux_info_drv.drv_stat = SCUX_DRV_UNINIT;
+}
+
+/******************************************************************************
+End of function SCUX_UnInitialize
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_OpenChannel
+* @brief         Open SCUX driver channel.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:open channel number.
+* @param[in]     flags:specifies the access mode whether the channel is 
+*                      opened for a read or a write
+* @retval        ESUCCESS: Operation successful.
+*                ENOMEM: Create queue is failed.
+*                EMFILE: Allocate DMA ch for write is failed.
+******************************************************************************/
+
+int_t SCUX_OpenChannel(const int_t channel, const int_t flags)
+{
+    int_t    retval;
+    
+    /* create write request queue */
+    retval = ahf_create(&gb_scux_info_drv.info_ch[channel].tx_que, AHF_LOCKINT);
+    if (ESUCCESS != retval)
+    {
+        retval = ENOMEM;
+    }
+    else
+    {
+        /* create read request queue */
+        retval = ahf_create(&gb_scux_info_drv.info_ch[channel].rx_que, AHF_LOCKINT);
+        if (ESUCCESS != retval)
+        {
+            retval = ENOMEM;
+        }
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        SCUX_InterruptInit(channel);
+        
+        /* init channel information parameter */
+        gb_scux_info_drv.info_ch[channel].open_flags = flags;
+        gb_scux_info_drv.info_ch[channel].p_tx_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_tx_next_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_rx_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_rx_next_aio = NULL;
+        gb_scux_info_drv.info_ch[channel].p_ssif_info1 = NULL;
+        gb_scux_info_drv.info_ch[channel].p_ssif_info2 = NULL;
+        gb_scux_info_drv.info_ch[channel].p_ssif_info3 = NULL;
+        gb_scux_info_drv.info_ch[channel].p_flush_callback = NULL;
+        gb_scux_info_drv.info_ch[channel].p_tx_dummy_data = &gb_scux_write_dummy_buf[0];
+        gb_scux_info_drv.info_ch[channel].p_rx_dummy_data = &gb_scux_read_dummy_buf[0];
+        
+        /* get DMA channel for write */
+        gb_scux_info_drv.info_ch[channel].dma_tx_ch = R_DMA_Alloc(DMA_ALLOC_CH, NULL);
+        if (EERROR == gb_scux_info_drv.info_ch[channel].dma_tx_ch)
+        {
+            retval = EMFILE;
+        }
+        else
+        {
+            gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_STOP;
+        }
+
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_OpenChannel
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CloseChannel
+* @brief         Close SCUX driver channel.
+*
+*                Description:<br>
+*                
+* @param[in]     channel: SCUX channel number.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t  SCUX_CloseChannel(const int_t channel)
+{
+    int_t    retval = ESUCCESS;
+    int_t    ercd;
+    int_t    was_masked;
+
+    /* check ch_stat whether going transfer */
+    if ((SCUX_CH_UNINIT != gb_scux_info_drv.info_ch[channel].ch_stat) && 
+        (SCUX_CH_INIT != gb_scux_info_drv.info_ch[channel].ch_stat) &&
+        (SCUX_CH_STOP != gb_scux_info_drv.info_ch[channel].ch_stat))
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        /* This exclusive access control ends in the SCUX_IoctlClearStop */
+        ercd = SCUX_IoctlClearStop(channel, was_masked);
+        if (ESUCCESS != ercd)
+        {
+            retval = EFAULT;
+        }
+    }
+    
+    if (ESUCCESS == retval)
+    {
+        /* delete queue */
+        ahf_cancelall(&gb_scux_info_drv.info_ch[channel].tx_que);
+        ahf_destroy(&gb_scux_info_drv.info_ch[channel].tx_que);
+        ahf_cancelall(&gb_scux_info_drv.info_ch[channel].rx_que);
+        ahf_destroy(&gb_scux_info_drv.info_ch[channel].rx_que);
+
+        SCUX_InterruptUninit(channel);
+        
+        ercd = R_DMA_Free(gb_scux_info_drv.info_ch[channel].dma_tx_ch, NULL);
+        if (ESUCCESS != ercd)
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            /* reset error status */
+            gb_scux_info_drv.info_ch[channel].err_stat_backup = ESUCCESS;
+            /* set channel status to open */
+            gb_scux_info_drv.info_ch[channel].ch_stat = SCUX_CH_INIT;
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CloseChannel
+******************************************************************************/
+
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckParam
+* @brief         Check SCUX parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES : DVU setting isn't performed when DVU is used.
+*                EACCES : MIX setting isn't performed when MIX is used.
+*                EACCES : SSIF setting isn't performed when SSIF is used.
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CheckParam(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT] = {SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH, SCUX_SSIF_NO_USE_CH};
+    bool_t use_mix_flag = false;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* check route parameter */
+        if (((SCUX_ROUTE_SRC_MEM_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MEM_MAX <= p_scux_info_ch->route_set)) &&
+            ((SCUX_ROUTE_SRC_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_SSIF_MAX <= p_scux_info_ch->route_set)) &&
+            ((SCUX_ROUTE_SRC_MIX_SSIF_MIN >= p_scux_info_ch->route_set) || (SCUX_ROUTE_SRC_MIX_SSIF_MAX <= p_scux_info_ch->route_set)))
+        {
+            retval = EPERM;
+        }
+        else
+        {
+            /* check route whether include SCUX channel */
+            switch (p_scux_info_ch->channel)
+            {
+                case SCUX_CH_0:
+                    if ((SCUX_ROUTE_SRC0_MEM != p_scux_info_ch->route_set)         &&
+                        (SCUX_ROUTE_SRC0_SSIF0 != p_scux_info_ch->route_set)       && 
+                        (SCUX_ROUTE_SRC0_MIX_SSIF0 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC0_SSIF3 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC0_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC0_SSIF012 != p_scux_info_ch->route_set)     &&
+                        (SCUX_ROUTE_SRC0_MIX_SSIF012 != p_scux_info_ch->route_set) &&
+                        (SCUX_ROUTE_SRC0_SSIF345 != p_scux_info_ch->route_set)     &&
+                        (SCUX_ROUTE_SRC0_MIX_SSIF345 != p_scux_info_ch->route_set))
+                    {       
+                        retval = EPERM;
+                    }
+                break;
+                
+                case SCUX_CH_1:
+                    if ((SCUX_ROUTE_SRC1_MEM != p_scux_info_ch->route_set)         &&
+                        (SCUX_ROUTE_SRC1_SSIF0 != p_scux_info_ch->route_set)       && 
+                        (SCUX_ROUTE_SRC1_MIX_SSIF0 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC1_SSIF3 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC1_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC1_SSIF012 != p_scux_info_ch->route_set)     &&
+                        (SCUX_ROUTE_SRC1_MIX_SSIF012 != p_scux_info_ch->route_set) &&
+                        (SCUX_ROUTE_SRC1_SSIF345 != p_scux_info_ch->route_set)     &&
+                        (SCUX_ROUTE_SRC1_MIX_SSIF345 != p_scux_info_ch->route_set))
+                    {  
+                        retval = EPERM;
+                    }
+                break;
+                
+                case SCUX_CH_2:
+                    if ((SCUX_ROUTE_SRC2_MEM != p_scux_info_ch->route_set)         &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF0 != p_scux_info_ch->route_set)   && 
+                        (SCUX_ROUTE_SRC2_SSIF1 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF3 != p_scux_info_ch->route_set)   &&
+                        (SCUX_ROUTE_SRC2_SSIF4 != p_scux_info_ch->route_set)       &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF012 != p_scux_info_ch->route_set) &&
+                        (SCUX_ROUTE_SRC2_MIX_SSIF345 != p_scux_info_ch->route_set))
+                    {  
+                        retval = EPERM;
+                    }
+                break;
+                
+                case SCUX_CH_3:
+                    if ((SCUX_ROUTE_SRC3_MEM != p_scux_info_ch->route_set)          && 
+                        (SCUX_ROUTE_SRC3_MIX_SSIF0 != p_scux_info_ch->route_set)    && 
+                        (SCUX_ROUTE_SRC3_SSIF2 != p_scux_info_ch->route_set)        &&
+                        (SCUX_ROUTE_SRC3_MIX_SSIF3 != p_scux_info_ch->route_set)    &&
+                        (SCUX_ROUTE_SRC3_SSIF5 != p_scux_info_ch->route_set)        &&
+                        (SCUX_ROUTE_SRC3_MIX_SSIF012 != p_scux_info_ch->route_set)  &&
+                        (SCUX_ROUTE_SRC3_MIX_SSIF345 != p_scux_info_ch->route_set))
+                    {  
+                        retval = EPERM;
+                    }
+                break;
+                
+                default :
+                    /* NOTREACHED on At the time of a normal performance */
+                    retval = EFAULT;
+                break;
+                
+            }
+        }
+    
+        if (ESUCCESS == retval)
+        {
+            /* set using SSIF channel and MIX information */
+            switch (p_scux_info_ch->route_set)
+            {
+                case SCUX_ROUTE_SRC0_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MEM :
+                    /* do nothing, when mem to mem route is setting */
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                break;                
+                
+                case SCUX_ROUTE_SRC0_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
+                break;
+                
+                case SCUX_ROUTE_SRC1_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                break;
+                
+                case SCUX_ROUTE_SRC1_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_0;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_1;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_2;
+                break;
+                
+                case SCUX_ROUTE_SRC1_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                break;                
+                
+                case SCUX_ROUTE_SRC1_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_3;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = SCUX_SSIF_CH_4;
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = SCUX_SSIF_CH_5;
+                break;      
+                
+                case SCUX_ROUTE_SRC2_SSIF1 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_1;
+                break;                
+                          
+                case SCUX_ROUTE_SRC2_SSIF4 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_4;
+                break;                
+                
+                case SCUX_ROUTE_SRC3_SSIF2 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_2;
+                break;
+                
+                case SCUX_ROUTE_SRC3_SSIF5 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = SCUX_SSIF_CH_5;
+                break;                                
+                
+                case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_0);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_1);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_2);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    use_mix_flag = true;
+                break;
+
+                case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1] = (SCUX_SSIF_CH_3);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2] = (SCUX_SSIF_CH_4);
+                    ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3] = (SCUX_SSIF_CH_5);
+                    use_mix_flag = true;
+                break;
+                        
+                default :
+                    /* NOTREACHED on At the time of a normal performance */
+                    retval = EPERM;
+                break;
+            }
+        }
+        
+        if (ESUCCESS == retval) 
+        {
+            if (false != p_scux_info_ch->src_cfg.src_enable)
+            {
+                retval = SCUX_CheckSrcParam(p_scux_info_ch, ssif_ch);
+            }
+            else
+            {
+                if (false != p_scux_info_ch->src_cfg.mode_sync)
+                {
+                    /* src disable is async mode only */
+                    retval = EPERM;
+                }
+            }
+        }
+        
+        if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
+        {
+            /* check parameter for SSIF direct route */
+            if ((ESUCCESS == retval) && (false != p_scux_info_ch->dvu_cfg.dvu_enable))
+            {
+                retval = SCUX_CheckDvuParam(p_scux_info_ch);
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                retval = SCUX_CheckSsifParam(p_scux_info_ch, ssif_ch, use_mix_flag);
+            }
+            
+            if ((ESUCCESS == retval) && (false != use_mix_flag))
+            {
+                retval = SCUX_CheckMixParam(p_scux_info_ch);
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckSrcParam
+* @brief         Check SRC parameter and set rate parameter to SCUX information.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     ssif_ch : Used ssif channel number.
+* @param[in]     use_mix_flag : Flag of Using MIX .
+* @retval        ESUCCESS : Parameter is no problems.
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckSrcParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT])
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssif_arrange_num;
+    uint32_t rate_sample_ratio;
+    uint32_t max_conv_rate;
+    uint32_t min_conv_rate = 0;
+    uint32_t freq_value = 0;
+    int_t audio_ch;
+    uint32_t max_rate;
+    
+    if ((NULL == p_scux_info_ch) || (NULL == ssif_ch))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* check use ch */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_1 == p_scux_info_ch->channel))
+        {
+            if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) && 
+                (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch) && 
+                (SCUX_USE_CH_4 != p_scux_info_ch->src_cfg.use_ch) && 
+                (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch) && 
+                (SCUX_USE_CH_8 != p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM;
+            }
+        }
+        else
+        {
+            /* on SCUX2, SCUX3, enable audio channel is only 1ch and 2ch */
+            if ((SCUX_USE_CH_1 != p_scux_info_ch->src_cfg.use_ch) && (SCUX_USE_CH_2 != p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM;
+            }           
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* if using SSIF, 1ch audio channel is disabled */
+            if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]) && (SCUX_USE_CH_1 == p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM;
+            }
+        }
+            
+        if (ESUCCESS == retval)
+        {
+            /* if  mutiple SSIF channel and enable TDM mode, only 2ch audio channel is enabled */
+            for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+            {
+                if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+                {
+                    if (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm)
+                    {
+                        if (SCUX_USE_CH_2 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                }
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* multiple SSIF ch check (multiple SSIF is used SSIF2) */
+            if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) && (SCUX_USE_CH_6 != p_scux_info_ch->src_cfg.use_ch))
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check word length */
+            if ((SCUX_DATA_LEN_MIN >= p_scux_info_ch->src_cfg.word_len) || (SCUX_DATA_LEN_MAX <= p_scux_info_ch->src_cfg.word_len))
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check delay mode */
+            if ((SCUX_DELAY_MIN >= p_scux_info_ch->src_cfg.delay_mode) || (SCUX_DELAY_MAX <= p_scux_info_ch->src_cfg.delay_mode))
+            {
+                retval = EPERM;
+            }
+            else
+            {
+                /* enable audio channel is less than 2ch when delay mode is enabled */
+                if ((SCUX_DELAY_NORMAL != p_scux_info_ch->src_cfg.delay_mode) && (SCUX_USE_CH_2 < p_scux_info_ch->src_cfg.use_ch))
+                {
+                    retval = EPERM;
+                }
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check rate setting */
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                /* check input rate */
+                if ((SCUX_SYNC_RATE_8      == p_scux_info_ch->src_cfg.input_rate_sync)  ||
+                    (SCUX_SYNC_RATE_11_025  == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_12      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_16      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_22_05   == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_24      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_32      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_44_1    == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_48      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_64      == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_88_2    == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                    (SCUX_SYNC_RATE_96      == p_scux_info_ch->src_cfg.input_rate_sync))
+                {
+                    /* enable rate is less than 66KHz on 6ch */
+                    if ((SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch) && 
+                        ((SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                         (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
+                    {
+                        retval = EPERM;
+                    }
+                    
+                    /* enable rate is less than 49KHz on 8ch */
+                    if ((SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch) && 
+                        ((SCUX_SYNC_RATE_64 == p_scux_info_ch->src_cfg.input_rate_sync)   ||
+                         (SCUX_SYNC_RATE_88_2 == p_scux_info_ch->src_cfg.input_rate_sync) ||
+                         (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.input_rate_sync)))
+                    {
+                        retval = EPERM;
+                    }
+                }
+                else
+                {
+                    retval = EPERM;
+                }
+                
+                if (ESUCCESS == retval) {
+                    /* check output rate */
+                    if ((SCUX_SYNC_RATE_8   == p_scux_info_ch->src_cfg.output_rate_sync)  ||
+                        (SCUX_SYNC_RATE_16   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_24   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_32   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_44_1 == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_48   == p_scux_info_ch->src_cfg.output_rate_sync) ||
+                        (SCUX_SYNC_RATE_96   == p_scux_info_ch->src_cfg.output_rate_sync))
+                    {
+                        /* enable rate is less than 66KHz on 6ch, enable rate is less than 49KHz on 8ch  */
+                        if ((SCUX_USE_CH_6 <= p_scux_info_ch->src_cfg.use_ch) && 
+                            (SCUX_SYNC_RATE_96 == p_scux_info_ch->src_cfg.output_rate_sync))
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                    else
+                    {
+                        retval = EPERM;
+                    }
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    p_scux_info_ch->input_rate = p_scux_info_ch->src_cfg.input_rate_sync;
+                    p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_rate_sync;
+                }
+            }
+            else
+            {
+                /* async mode */
+                /* check input rate */
+                /* get input source clock */
+                switch (p_scux_info_ch->src_cfg.input_clk_async)
+                {
+                    case SCUX_CLK_AUDIO_CLK :
+                        freq_value = SCUX_AUDIO_CLK;
+                    break;                  
+                    
+                    case SCUX_CLK_AUDIO_X1 :
+                        freq_value = SCUX_AUDIO_X1;
+                    break;
+                    
+                    case SCUX_CLK_MLB_CLK :
+                        freq_value = SCUX_MLB_CLK;
+                    break;
+    
+                    case SCUX_CLK_USB_X1 :
+                        freq_value = SCUX_USB_X1;
+                    break;
+    
+                    case SCUX_CLK_CLKP1_2 :
+                        freq_value = SCUX_CLKLP1_DIV2;
+                    break;
+    
+                    case SCUX_CLK_MTU_TIOC3A :
+                        freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
+                        if (0U == freq_value)
+                        {
+                            retval = EPERM;
+                        }
+                    break;
+    
+                    case SCUX_CLK_MTU_TIOC4A :
+                        freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
+                        if (0U == freq_value)
+                        {
+                            retval = EPERM;
+                        }
+                    break;
+    
+                    case SCUX_CLK_SSIF0_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF1_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF2_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF3_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF4_WS :
+                        /* fall through */
+                    case SCUX_CLK_SSIF5_WS :
+                        freq_value = p_scux_info_ch->src_cfg.input_ws;
+                        if (0U == freq_value)
+                        {
+                            retval = EPERM;
+                        }
+                    break;
+                    
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                        retval = EPERM;
+                    break;
+                }
+                    
+                if (ESUCCESS == retval)
+                { 
+                    /* check devide rate and devide source clock */
+                    /* check source clock isn't SSIF WS signal */
+                    if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 
+                        (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
+                    {
+                        if ((0U != (p_scux_info_ch->src_cfg.input_div_async % SCUX_EVEN_VALUE_DIV)) ||
+                            (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.input_div_async))
+                        {
+                            retval = EPERM;
+                        }
+                        else
+                        {
+                            if (0U == p_scux_info_ch->src_cfg.input_div_async)
+                            {
+                                /* 0 is a same size */
+                                p_scux_info_ch->input_rate = freq_value;
+                            }
+                            else{
+                                p_scux_info_ch->input_rate = freq_value / p_scux_info_ch->src_cfg.input_div_async;
+                            }
+                        }
+                    }
+                    else
+                    {
+                        p_scux_info_ch->input_rate = freq_value;
+                    }
+                    
+                    if (ESUCCESS == retval)
+                    {
+                        /* check input frequency is enable range */
+                        if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH6;
+                        }
+                        else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH8;
+                        }
+                        else
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH1_4;
+                        }
+                        
+                        if ((SCUX_MIN_FREQ > p_scux_info_ch->input_rate) || 
+                           (max_rate < p_scux_info_ch->input_rate))
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                }
+                    
+                if (ESUCCESS == retval)
+                {
+                    /* if output route is SSIF direct route ,WS signal frequency is used */
+                    if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1])
+                    {
+                        if ((SCUX_SYNC_RATE_8      == p_scux_info_ch->src_cfg.output_ws)  ||
+                            (SCUX_SYNC_RATE_11_025  == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_12      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_16      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_22_05   == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_24      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_32      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_44_1    == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_48      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_64      == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_88_2    == p_scux_info_ch->src_cfg.output_ws) ||
+                            (SCUX_SYNC_RATE_96      == p_scux_info_ch->src_cfg.output_ws))
+                        {
+                            p_scux_info_ch->output_rate = p_scux_info_ch->src_cfg.output_ws;
+                        }   
+                        else
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                    else
+                    {              
+                        /* check output rate (mem to mem)*/
+                        /* get output source clock */
+                        switch (p_scux_info_ch->src_cfg.output_clk_async)
+                        {
+                            case SCUX_CLK_AUDIO_CLK :
+                                freq_value = SCUX_AUDIO_CLK;
+                            break;
+                                                        
+                            case SCUX_CLK_AUDIO_X1 :
+                                freq_value = SCUX_AUDIO_X1;
+                            break;
+                          
+                            case SCUX_CLK_MLB_CLK :
+                                freq_value = SCUX_MLB_CLK;
+                            break;
+            
+                            case SCUX_CLK_USB_X1 :
+                                freq_value = SCUX_USB_X1;
+                            break;
+            
+                            case SCUX_CLK_CLKP1_2 :
+                                freq_value = SCUX_CLKLP1_DIV2;
+                            break;
+        
+                            case SCUX_CLK_MTU_TIOC3A :
+                                freq_value = p_scux_info_ch->src_cfg.freq_tioc3a;
+                                if (0U == freq_value)
+                                {
+                                    retval = EPERM;
+                                }
+                            break;
+            
+                            case SCUX_CLK_MTU_TIOC4A :
+                                freq_value = p_scux_info_ch->src_cfg.freq_tioc4a;
+                                if (0U == freq_value)
+                                {
+                                    retval = EPERM;
+                                }
+                            break;
+            
+                            case SCUX_CLK_SSIF0_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF1_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF2_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF3_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF4_WS :
+                                /* fall through */
+                            case SCUX_CLK_SSIF5_WS :
+                                freq_value = p_scux_info_ch->src_cfg.output_ws;
+                                if (0U == freq_value)
+                                {
+                                    retval = EPERM;
+                                }
+                            break;
+                            
+                            default :
+                                /* error check is gone when route is other than SSIF */
+                                if (SCUX_ROUTE_SSIF != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                                {
+                                    retval = EPERM;
+                                }
+                            break;
+                        }
+                    }
+                    
+                    if (ESUCCESS == retval)
+                    {         
+                        /* check devide rate on only except for SSIF route, MISRA R1.1 mesure */          
+                        if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) && 
+                            (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
+                        {                  
+                            if ((0U != (p_scux_info_ch->src_cfg.output_div_async % SCUX_EVEN_VALUE_DIV)) ||
+                                (SCUX_MAX_DIV_CLK < p_scux_info_ch->src_cfg.output_div_async))
+                            {
+                                retval = EPERM;
+                            }
+                        }
+                    }
+
+                    if (ESUCCESS == retval)
+                    {
+                        /* check source clock isn't SSIF WS signal */
+                        if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.output_clk_async) && 
+                            (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.output_clk_async) &&
+                            (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.output_clk_async))
+                        {
+                            if (0U == p_scux_info_ch->src_cfg.output_div_async)
+                            {
+                                /* 0 is a same size */
+                                p_scux_info_ch->output_rate = freq_value;
+                            }
+                            else
+                            {
+                                p_scux_info_ch->output_rate = freq_value / p_scux_info_ch->src_cfg.output_div_async;
+                            }
+                        }
+                        else
+                        {
+                            p_scux_info_ch->output_rate = freq_value;
+                        }
+                        /* check input frequency is enable range */
+                        if (SCUX_USE_CH_6 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH6;
+                        }
+                        else if (SCUX_USE_CH_8 == p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH8;
+                        }
+                        else
+                        {
+                            max_rate = SCUX_MAX_FREQ_CH1_4;
+                        }
+                        
+                        if ((SCUX_MIN_FREQ > p_scux_info_ch->output_rate) || 
+                            (max_rate < p_scux_info_ch->output_rate))
+                        {
+                            retval = EPERM;
+                        }
+                        
+                    }
+                }
+            }
+            
+            if (ESUCCESS == retval)
+            {
+                /* check convert rate range */
+                max_conv_rate = SCUX_MAX_CONV_RATE;
+                switch (p_scux_info_ch->src_cfg.delay_mode)
+                {
+                    case SCUX_DELAY_NORMAL :
+                        switch (p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            case SCUX_USE_CH_1 :
+                                /* fall through */
+                            case SCUX_USE_CH_2 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH1_2;
+                            break;
+                            
+                            case SCUX_USE_CH_4 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH4;
+                            break;
+                            
+                            case SCUX_USE_CH_6 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH6;
+                            break;
+                            
+                            case SCUX_USE_CH_8 :
+                                min_conv_rate = SCUX_MIN_CONV_RATE_NORMAL_CH8;
+                            break;                          
+                    
+                            default :
+                                /* NOTREACHED on At the time of a normal performance */
+                                retval = EPERM;
+                            break;
+                        }                   
+                    break;
+                        
+                    case SCUX_DELAY_LOW_DELAY1 :
+                        min_conv_rate = SCUX_MIN_CONV_RATE_DELAY1;
+                    break;
+    
+                    case SCUX_DELAY_LOW_DELAY2 :
+                        min_conv_rate = SCUX_MIN_CONV_RATE_DELAY2;
+                    break;                
+                        
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                        retval = EPERM;
+                    break;
+                }
+                        
+                rate_sample_ratio = ((p_scux_info_ch->output_rate * SCUX_RATE_INT_CONV_VALUE) / p_scux_info_ch->input_rate);
+                if ((min_conv_rate > rate_sample_ratio) || (max_conv_rate < rate_sample_ratio))
+                {
+                    retval = EPERM;
+                }
+            }
+        }
+    
+        if (ESUCCESS == retval)
+        {
+            /* check wait time */
+            if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->src_cfg.wait_sample)
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check min rate ratio */
+            if ((SCUX_MIN_RATE_MIN_PAERCENTAGE > (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) || 
+                (SCUX_MIN_RATE_MAX_PAERCENTAGE < (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage))
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* check input data position */
+            for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
+            {
+                if ((SCUX_AUDIO_CH_MIN >= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]) || 
+                    (SCUX_AUDIO_CH_MAX <= p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch]))
+                {
+                    retval = EPERM;
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckSrcParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckDvuParam
+* @brief         Check DVU parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES : DVU setting isn't performed when DVU is used.
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckDvuParam(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    int_t audio_ch;
+    uint32_t enable_ch_flag = false;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (false == p_scux_info_ch->dvu_setup)
+        {
+            retval = EACCES;
+        }
+        else
+        {
+            if (false != p_scux_info_ch->dvu_cfg.dvu_enable)
+            {
+                /* check digital volume value */
+                if (false !=  p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable)
+                {
+                    /* check digital volume value */
+                    for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
+                    {
+                        if (SCUX_MAX_DIGITAL_VOLUME < p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch])
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                }
+                
+                /* check ramp volume value */
+                for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+                {
+                    enable_ch_flag |= (uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch];
+                }
+                
+                if ((ESUCCESS == retval) && (false != (bool_t)enable_ch_flag))
+                {
+                    /* check ramp up period */
+                    if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period <= SCUX_DVU_TIME_MIN) ||
+                        (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period >= SCUX_DVU_TIME_MAX))
+                    {
+                        retval = EPERM;
+                    }
+                    
+                    if (ESUCCESS == retval) 
+                    {
+                        /* check ramp down period */
+                        if ((p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period <= SCUX_DVU_TIME_MIN) ||
+                            (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period >= SCUX_DVU_TIME_MAX))
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                
+                    if (ESUCCESS == retval)
+                    {
+                        /* check ramp volume */
+                        if (SCUX_MAX_RAMP_VOLUME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol)
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                
+                    if (ESUCCESS != retval)
+                    {
+                        /* check wait time */
+                        if (SCUX_MAX_WAIT_TIME < p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time)
+                        {
+                            retval = EPERM;
+                        }
+                    }
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckDvuParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckSsifParam
+* @brief         Check SSIF parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     ssif_ch : Used ssif channel number.
+* @param[in]     use_mix_flag : Flag of Using MIX .
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES : SSIF setting isn't performed when SSIF is used.
+*                EACCES : SSIF channel is already used.
+*                EACCES : When use MIX, it is a setup which does not agree in a route setup. 
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckSsifParam(scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch[SCUX_SSIF_NUM_CH_ARRANGEMENT], const bool_t use_mix_flag)
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssif_arrange_num;
+    uint32_t mix_ssif_ch_bit = 0;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch) || (NULL == ssif_ch)) 
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (false == use_mix_flag)
+        {
+            /* used SSIF channel check no used MIX route */
+            for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+            {
+                if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+                {
+                    /* check SSIF is already setup */
+                    if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
+                    {
+                        retval = EACCES;
+                    }
+                    else
+                    {
+                        /* used SSIF channel is checked by other SCUX channel */
+                        if (0 != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel)
+                        {
+                            retval = EACCES;
+                        }
+                    }
+                }
+            }
+        }
+        else
+        {
+            /* used SSIF channel check on MIX route */
+            for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+            {
+                if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+                {
+                    /* clear SCUX_SSIF_use_mix_flag and get SSIF channel number */
+                    mix_ssif_ch_bit |= (1U << ssif_ch[ssif_arrange_num]);
+                    /* check SSIF is already setup */
+                    if (false == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_setup)
+                    {
+                        retval = EACCES;
+                    }
+                }
+            }
+            if (ESUCCESS == retval)
+            {
+                /* used SSIF channel check, on MIX route check */
+                if (0U != p_info_drv->shared_info.mix_ssif_ch)
+                {
+                    /* In the MIX setup for the and after 2times, it is checked that same SSIF ch on 1st setting is set up */
+                    if (p_info_drv->shared_info.mix_ssif_ch != mix_ssif_ch_bit)
+                    {
+                        retval = EACCES;
+                    }   
+                }
+                else
+                {
+                    /*It checks that SSIF channel is not used once on first MIX setup */
+                    if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
+                    {
+                        if ((0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel) ||
+                            (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]].scux_channel) ||
+                            (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]].scux_channel))
+                        {
+                            retval = EACCES;
+                        }
+                    }
+                    else
+                    {
+                        if (0 != gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]].scux_channel)
+                        {
+                            retval = EACCES;
+                        }
+                    }
+                }
+            }
+        }
+                
+        /* each SSIF parameter check */
+        for (ssif_arrange_num = 0; ((ESUCCESS == retval) && (ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT)); ssif_arrange_num++)
+        {
+            /* used SSIF channel check, on SSIF direct route check */
+            if (SCUX_SSIF_NO_USE_CH != ssif_ch[ssif_arrange_num])
+            {
+                
+                /* check system word */
+                if ((gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word <= SCUX_SSIF_SYSTEM_LEN_MIN) ||
+                    (gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word >= SCUX_SSIF_SYSTEM_LEN_MAX))
+                {
+                    retval = EPERM;
+                }
+                else
+                {
+                    /* check system word >= data word */
+                    /* The combination applicable to error only of data word of 24bit and system word of 16bit */
+                    if ((SCUX_DATA_LEN_16 != p_scux_info_ch->src_cfg.word_len) && 
+                        (SCUX_SSIF_SYSTEM_LEN_16 == gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.system_word))
+                    {
+                        retval = EPERM;
+                    }
+                }
+    
+                if (ESUCCESS == retval)
+                {
+                    /* if multiple channel is used, TDM is disable */
+                    if ((SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]) &&
+                        (false != gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].ssif_cfg.use_tdm))
+                    {
+                        retval = EPERM;
+                    }
+                }
+                if (ESUCCESS == retval)
+                {
+                    retval = SCUX_CheckSsifClockDiv(p_scux_info_ch, ssif_ch[ssif_arrange_num]);
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel 
+                    = (int_t)((uint32_t)gb_scux_ssif_info[ssif_ch[ssif_arrange_num]].scux_channel | (1U << p_scux_info_ch->channel));
+                }
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            /* set SSIF information structure pointer */
+            if (SCUX_SSIF_NO_USE_CH != ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2])
+            {
+                p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
+                p_scux_info_ch->p_ssif_info2 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT2]];
+                p_scux_info_ch->p_ssif_info3 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT3]];
+            }
+            else
+            {
+                p_scux_info_ch->p_ssif_info1 = &gb_scux_ssif_info[ssif_ch[SCUX_SSIF_CH_ARRANGEMENT1]];
+                p_scux_info_ch->p_ssif_info2 = NULL;
+                p_scux_info_ch->p_ssif_info3 = NULL;
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckSsifParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckMixParam
+* @brief         Check MIX parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EACCES : MIX setting isn't performed when MIX is used.
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+static int_t SCUX_CheckMixParam(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    int_t scux_ch;
+    int_t audio_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    { 
+        retval = EFAULT;
+    }
+    else
+    {
+        if (false == p_info_drv->shared_info.mix_setup)
+        {
+            retval = EACCES;
+        }
+        else
+        {
+            if (false != p_info_drv->shared_info.mixmode_ramp)
+            {
+                /* check ramp up time */
+                if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.up_period) ||
+                    (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.up_period))
+                {
+                    retval = EPERM;
+                }
+                
+                /* check ramp down time */
+                if ((SCUX_MIX_TIME_MIN >= p_info_drv->shared_info.down_period) ||
+                    (SCUX_MIX_TIME_MAX <= p_info_drv->shared_info.down_period))
+                {
+                    retval = EPERM;
+                }
+            }
+            
+            /* check MIX volume */
+            for (scux_ch = SCUX_CH_0; ((ESUCCESS == retval) && (SCUX_CH_NUM > scux_ch)); scux_ch++)
+            {
+                /* register set on the channel itself which sets up or channel which has already MIX operated */
+                if ((scux_ch == p_scux_info_ch->channel) ||
+                    (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))))
+                {
+                    if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[scux_ch])
+                    {
+                        retval = EPERM;
+                    }
+                }
+            }
+                    
+            /* check output data position */
+            for (audio_ch = 0; ((ESUCCESS == retval) && (audio_ch < p_scux_info_ch->src_cfg.use_ch)); audio_ch++)
+            {
+                /* check min rate ratio */
+                if ((SCUX_AUDIO_CH_MIN >= p_info_drv->shared_info.select_out_data_ch[audio_ch]) || 
+                    (SCUX_AUDIO_CH_MAX <= p_info_drv->shared_info.select_out_data_ch[audio_ch]))
+                {
+                    retval = EPERM;
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckMixParam
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_StrNLen
+* @brief         computes the length of the string
+*
+*                Description:<br>
+*                if string is longer than maxlen, this function return maxlen
+* @param[in]     p_str      :pointer of string 
+* @param[in]     maxlen     :maximum length of inspection
+* @retval        'number of characters in the string' or 'maxlen'
+******************************************************************************/
+size_t SCUX_StrNLen(const char_t* p_str, size_t maxlen)
+{
+    size_t ret_len;
+
+    if (NULL == p_str)
+    {
+        /* character string does not exist */
+        ret_len = 0;
+    }
+    else
+    {
+        /* ->IPA P1.3.1 Even if a sign is positive, even a negative is no problem. */
+        for (ret_len = 0; (maxlen != 0U) && (*p_str != '\0'); ret_len++)
+        /* <-IPA P1.3.1 */
+        {
+            maxlen--;
+            p_str++;
+        }
+    }
+
+    return ret_len;
+}
+
+/******************************************************************************
+End of function SCUX_StrNLen
+******************************************************************************/
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: SCUX_CmnUnInitialize
+* @brief         uninitialize driver infomation.
+*
+*                Description:<br>
+*                
+* @param[in]     None.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+static int_t SCUX_CmnUnInitialize(void)
+{
+    int_t    retval = ESUCCESS;
+    osStatus sem_ercd;
+    int_t    ssif_ch_count;
+    uint32_t cpg_value;
+    uint32_t was_masked;
+    volatile uint8_t dummy_buf;
+
+    /* software reset */
+    SCUX.SWRSR_CIM &= ~SWRSR_CIM_SWRST_SET;
+
+    for (ssif_ch_count = 0; ssif_ch_count < SCUX_SSIF_CH_NUM; ssif_ch_count++) 
+    {
+        if (NULL != gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access)
+        {
+            sem_ercd = osSemaphoreDelete(gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                 retval = EFAULT;
+            }
+
+            gb_scux_ssif_info[ssif_ch_count].sem_ch_scux_ssif_access = NULL;
+        }
+    }
+
+    if (NULL != gb_scux_info_drv.shared_info.sem_shared_access)
+    {
+        sem_ercd = osSemaphoreDelete(gb_scux_info_drv.shared_info.sem_shared_access);
+        /* semaphore error check */
+        if (osOK != sem_ercd)
+        {
+            /* set error return value */
+            retval = EFAULT;
+        }
+
+        gb_scux_info_drv.shared_info.sem_shared_access = NULL;
+    }
+
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif
+
+    /* stop clock for SCUX */
+    cpg_value = ((uint32_t)CPG.STBCR8 | CPG_STBCR8_BIT_MSTP81);
+    CPG.STBCR8 = (uint8_t)cpg_value;
+    dummy_buf = CPG.STBCR8;
+
+    if (0U == was_masked)
+    {
+        /* enable all irq */
+        __enable_irq();
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CmnUnInitialize
+******************************************************************************/
+#endif /* end mbed */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/scux/scux.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,780 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          scux.h
+* $Rev: 993 $
+* $Date:: 2014-07-22 09:54:45 +0900#$
+* @brief         Sample driver internal header
+******************************************************************************/
+
+#ifndef SCUX_H
+#define SCUX_H
+
+/******************************************************************************
+Includes <System Includes>, "Project Includes"
+******************************************************************************/
+
+#include "scux_if.h" 
+#include "scux_int.h"
+#include "aioif.h"
+#include "iodefine.h"
+#include "Renesas_RZ_A1.h"
+#include "dma_if.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* SCUX Register Set Value */
+/* Init Value */
+/* IPC */
+#define IPCIR_IPC0_INIT_VALUE      (0x00000001U)
+#define IPSLR_IPC0_INIT_VALUE      (0x00000000U)
+/* OPC */
+#define OPCIR_OPC0_INIT_VALUE      (0x00000001U)
+#define OPSLR_OPC0_INIT_VALUE      (0x00000000U)
+/* FFD */
+#define FFDIR_FFD0_INIT_VALUE      (0x00000001U)
+#define FDAIR_FFD0_INIT_VALUE      (0x00000000U)
+#define DRQSR_FFD0_INIT_VALUE      (0x00000000U)
+#define FFDPR_FFD0_INIT_VALUE      (0x00000000U)
+#define FFDBR_FFD0_INIT_VALUE      (0x00000000U)
+#define DEVMR_FFD0_INIT_VALUE      (0x00000000U)
+#define DEVCR_FFD0_INIT_VALUE      (0x00000000U)
+/* FFU */
+#define FFUIR_FFU0_INIT_VALUE      (0x00000001U)
+#define FUAIR_FFU0_INIT_VALUE      (0x00000000U)
+#define URQSR_FFU0_INIT_VALUE      (0x00000000U)
+#define FFUPR_FFU0_INIT_VALUE      (0x00000000U)
+#define UEVMR_FFU0_INIT_VALUE      (0x00000000U)
+#define UEVCR_FFU0_INIT_VALUE      (0x00000000U)
+/* SRC */
+#define SRCIR_2SRC0_INIT_VALUE     (0x00000001U)
+#define SADIR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SRCBR_2SRC0_INIT_VALUE     (0x00000000U)
+#define IFSCR_2SRC0_INIT_VALUE     (0x00000000U)
+#define IFSVR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SRCCR_2SRC0_INIT_VALUE     (0x00000000U)
+#define MNFSR_2SRC0_INIT_VALUE     (0x00000000U)
+#define BFSSR_2SRC0_INIT_VALUE     (0x00000000U)
+#define WATSR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SEVMR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SEVCR_2SRC0_INIT_VALUE     (0x00000000U)
+#define SRCIRR_2SRC0_INIT_VALUE    (0x00000001U)
+/* DVU */
+#define DVUIR_DVU0_INIT_VALUE      (0x00000001U)
+#define VADIR_DVU0_INIT_VALUE      (0x00000000U)
+#define DVUBR_DVU0_INIT_VALUE      (0x00000000U)
+#define DVUCR_DVU0_INIT_VALUE      (0x00000000U)
+#define ZCMCR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRCTR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRPDR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRDBR_DVU0_INIT_VALUE      (0x00000000U)
+#define VRWTR_DVU0_INIT_VALUE      (0x00000000U)
+#define VOL_N_R_DVU0_INIT_VALUE    (0x00000000U)
+#define DVUER_DVU0_INIT_VALUE      (0x00000000U)
+#define VEVMR_DVU0_INIT_VALUE      (0x00000000U)
+#define VEVCR_DVU0_INIT_VALUE      (0x00000000U)
+/* MIX */
+#define MIXIR_MIX0_0_INIT_VALUE    (0x00000001U)
+#define MADIR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MIXBR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MIXMR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MVPDR_MIX0_0_INIT_VALUE    (0x00000000U)
+#define MDB_N_R_MIX0_0_INIT_VALUE  (0x00000000U)
+#define MDBER_MIX0_0_INIT_VALUE    (0x00000000U)
+/* CIM */
+#define SWRSR_CIM_INIT_VALUE       (0x00000001U)
+#define DMACR_CIM_INIT_VALUE       (0x00000000U)
+#define SSIRSEL_CIM_INIT_VALUE     (0x00000000U)
+#define FDTSEL_CIM_INIT_VALUE      (0x00000000U)
+#define FUTSEL_CIM_INIT_VALUE      (0x00000000U)
+#define SSIPMD_CIM_INIT_VALUE      (0x00000000U)
+#define SSICTRL_CIM_INIT_VALUE     (0x00000000U)
+#define SRCRSEL_CIM_INIT_VALUE     (0x76543210U)
+#define MIXRSEL_CIM_INIT_VALUE     (0x76543210U)
+
+/* SCUX bit value & mask & fixed setting */
+
+/* IPC */
+#define IPCIR_IPC0_INIT_SET           (1U << 0)
+
+#define IPSLR_IPC_PASS_SEL_MASK       (7U << 0)
+#define IPSLR_IPC_PASS_SEL_SET_ASYNC  (3U << 0)
+#define IPSLR_IPC_PASS_SEL_SET_SYNC   (4U << 0)
+
+/* OPC */
+#define OPCIR_OPC0_INIT_SET           (1U << 0)
+
+#define OPSLR_OPC_PASS_SEL_MASK       (7U << 0)
+#define OPSLR_OPC_PASS_SEL_SET_DIRECT (1U << 0)
+#define OPSLR_OPC_PASS_SEL_SET_ASYNC  (3U << 0)
+#define OPSLR_OPC_PASS_SEL_SET_SYNC   (4U << 0)
+
+/* FFD */
+#define FFDIR_FFD0_INIT_SET           (1U << 0)
+
+#define FDAIR_FFD0_CHNUM_MASK         (0x0FU << 0)
+
+#define DRQSR_FFD0_SIZE_MASK          (0x0FU << 0)
+
+#define FFDPR_FFD0_PASS_SET_ASYNC     (1U << 0)
+#define FFDPR_FFD0_PASS_SET_SYNC      (2U << 0)
+
+#define FFDBR_FFD0_BOOT_SET           (1U << 0)
+
+#define DEVMR_FFD0_DEVMUF_SET         (1U << 31)
+#define DEVMR_FFD0_DEVMOF_SET         (1U << 30)
+#define DEVMR_FFD0_DEVMOL_SET         (1U << 29)
+#define DEVMR_FFD0_DEVMIUF_SET        (1U << 28)
+#define DEVMR_FFD0_DEVMRQ_SET         (1U << 15)
+
+#define DEVCR_FFD0_DEVCUF_MASK        (1U << 31)
+#define DEVCR_FFD0_DEVCUF_SET         (1U << 31)
+#define DEVCR_FFD0_DEVCOF_MASK        (1U << 30)
+#define DEVCR_FFD0_DEVCOF_SET         (1U << 30)
+#define DEVCR_FFD0_DEVCOL_MASK        (1U << 29)
+#define DEVCR_FFD0_DEVCOL_SET         (1U << 29)
+#define DEVCR_FFD0_DEVCIUF_MASK       (1U << 28)
+#define DEVCR_FFD0_DEVCIUF_SET        (1U << 28)
+#define DEVCR_FFD0_DEVCRQ_MASK        (1U << 15)
+#define DEVCR_FFD0_DEVCRQ_SET         (1U << 15)
+
+/* FFU */
+#define FFUIR_FFU0_INIT_SET           (1U << 0)
+
+#define FUAIR_FFU0_CHNUM_MASK         (0x0FU << 0)
+
+#define URQSR_FFU0_SIZE_MASK          (0x0FU << 0)
+
+#define FFUPR_FFU0_PASS_SET_ASYNC     (1U << 0)
+#define FFUPR_FFU0_PASS_SET_SYNC      (2U << 0)
+
+#define UEVMR_FFU0_UEVMUF_SET         (1U << 31)
+#define UEVMR_FFU0_UEVMOF_SET         (1U << 30)
+#define UEVMR_FFU0_UEVMOL_SET         (1U << 29)
+#define UEVMR_FFU0_UEVMRQ_SET         (1U << 15)
+
+#define UEVCR_FFU0_UEVCUF_MASK        (1U << 31)
+#define UEVCR_FFU0_UEVCUF_SET         (1U << 31)
+#define UEVCR_FFU0_UEVCOF_MASK        (1U << 30)
+#define UEVCR_FFU0_UEVCOF_SET         (1U << 30)
+#define UEVCR_FFU0_UEVCOL_MASK        (1U << 29)
+#define UEVCR_FFU0_UEVCOL_SET         (1U << 29)
+#define UEVCR_FFU0_UEVCRQ_MASK        (1U << 15)
+#define UEVCR_FFU0_UEVCRQ_SET         (1U << 15)
+
+/* SRC */
+#define SRCIR_2SRC0_INIT_SET          (1U << 0)
+
+#define SADIR_2SRC0_CHNUM_MASK        (0x0FU << 0)
+#define SADIR_2SRC0_OTBL_MASK         (0x1FU << 16)
+#define SADIR_2SRC0_OTBL_SET_24BIT    (0x0U << 16)
+#define SADIR_2SRC0_OTBL_SET_16BIT    (0x8U << 16)
+
+#define SRCBR_2SRC0_BYPASS_SET        (0x1U << 0)
+
+#define IFSCR_2SRC0_INTIFSEN_SET      (0x1U << 0)
+
+#define IFSVR_2SRC0_INTIFS_MASK       (0x0FFFFFFFU << 0)
+
+#define SRCCR_2SRC0_BASE_VALUE        (0x00010110U)
+#define SRCCR_2SRC0_WATMD_SET         (1U << 20)
+#define SRCCR_2SRC0_BUFMD_SET         (1U << 12)
+#define SRCCR_2SRC0_SRCMD_SET         (1U << 0)
+
+#define MNFSR_2SRC0_MINFS_MASK        (0x0FFFFFFFU << 0)
+
+#define BFSSR_2SRC0_BUFDATA_MASK      (0x3FFU << 16)
+#define BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE1 (0x80U << 16)
+#define BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE2 (0x40U << 16)
+#define BFSSR_2SRC0_BUFIN_MASK        (0x0FU << 0)
+#define BFSSR_2SRC0_BUFIN_SET_DELAY_MODE (0x05U << 0)
+
+#define WATSR_2SRC0_WTIME_MASK        (0xFFFFFFU << 0)
+
+#define SEVMR_2SRC0_EVMUF_SET         (1U << 31)
+#define SEVMR_2SRC0_EVMOF_SET         (1U << 30)
+
+#define SEVCR_2SRC0_EVCUF_MASK        (1U << 31)
+#define SEVCR_2SRC0_EVCUF_SET         (1U << 31)
+#define SEVCR_2SRC0_EVCOF_MASK        (1U << 30)
+#define SEVCR_2SRC0_EVCOF_SET         (1U << 30)
+
+#define SRCIRR_2SRC0_INIT_SET         (1U << 0)
+
+#define DVUIR_DVU0_INIT_SET           (1U << 0)
+
+#define VADIR_DVU0_OTBL_MASK          (0x1FU << 16)
+#define VADIR_DVU0_OTBL_SET_24BIT     (0x0U << 16)
+#define VADIR_DVU0_OTBL_SET_16BIT     (0x8U << 16)
+#define VADIR_DVU0_CHNUM_MASK         (0x0FU << 0)
+
+#define DVUBR_DVU0_BYPASS_SET         (0x1U << 0)
+
+#define DVUCR_DVU0_VVMD_SET           (1U << 8)
+#define DVUCR_DVU0_VRMD_SET           (1U << 4)
+#define DVUCR_DVU0_ZCMD_SET           (1U << 0)
+
+#define ZCMCR_DVU0_ZCEN_SET           (1U << 0)
+
+#define VRCTR_DVU0_VREN_SET           (1U << 0)
+
+#define VRPDR_DVU0_VRPDUP_SHIFT       (8U)
+#define VRPDR_DVU0_VRPDUP_MASK        (0x1F << VRPDR_DVU0_VRPDUP_SHIFT)
+#define VRPDR_DVU0_VRPDDW_SHIFT       (0U)
+#define VRPDR_DVU0_VRPDDW_MASK        (0x1F << VRPDR_DVU0_VRPDDW_SHIFT)
+
+#define VRDBR_DVU0_VRDB_MASK          (0x3FFU << 0)
+
+#define VRWTR_DVU0_VRWT_MASK          (0xFFFFFFU << 0)
+
+#define VOL_N_R_DVU_VOLVAL_MASK       (0xFFFFFFU << 0)
+
+#define DVUER_DVU0_DVUEN_SET          (1U << 0)
+
+#define DVUSR_DVU0_ZSTS_N_SHIFT       (16U)
+#define DVUSR_DVU0_ZSTS_N_MASK        (1U << DVUSR_DVU0_ZSTS_N_SHIFT)
+#define DVUSR_DVU0_ZSTS_MASK          (0xFFU << DVUSR_DVU0_ZSTS_N_SHIFT)
+#define DVUSR_DVU0_VRSTS_MASK         (7U << 0)
+#define DVUSR_DVU0_VRSTS_VOL_FIX      (4U << 0)
+
+#define VEVMR_DVU0_VEVMZCM_SET        (1U << 24)
+
+#define VEVCR_DVU0_VEVCZCM_SET        (1U << 24)
+
+/* MIX */
+#define MIXIR_MIX0_INIT_SET           (1U << 0)
+
+#define MADIR_MIX0_CHNUM_MASK         (0x0FU << 0)
+
+#define MIXMR_MIX0_MIXMODE_SET        (1U << 0)
+
+#define MVPDR_MIX0_MXPDUP_SHIFT       (8U)
+#define MVPDR_MIX0_MXPDUP_MASK        (0x0FU << MVPDR_MIX0_MXPDUP_SHIFT)
+#define MVPDR_MIX0_MXPDDW_SHIFT       (0U)
+#define MVPDR_MIX0_MXPDDW_MASK        (0x0FU << MVPDR_MIX0_MXPDDW_SHIFT)
+
+#define MDB_N_R_MIX0_MIXDB_N_MASK     (0x3FFU <<0)
+
+#define MDBER_MIX0_MIXDBEN_SET        (1U << 0)
+
+#define MIXSR_MIX0_MIXSTS_MASK        (3U << 0)
+
+/* CIM */
+#define SWRSR_CIM_SWRST_SET           (1U << 0)
+
+#define DMACR_CIM_DMAMDFFU_N_SET      (1U << 4)
+#define DMACR_CIM_DMAMDFFD_N_SET      (1U << 0)
+
+#define SSIRSEL_CIM_SOSEL5_MASK       (3U << 20)
+#define SSIRSEL_CIM_SOSEL5_SRC3_SET   (0U << 20)
+#define SSIRSEL_CIM_SOSEL5_SRC1_SET   (1U << 20)
+#define SSIRSEL_CIM_SOSEL5_SRC0_SET   (2U << 20)
+#define SSIRSEL_CIM_SOSEL5_MIX_SET    (3U << 20)
+#define SSIRSEL_CIM_SOSEL4_MASK       (3U << 16)
+#define SSIRSEL_CIM_SOSEL4_SRC2_SET   (0U << 16)
+#define SSIRSEL_CIM_SOSEL4_SRC1_SET   (1U << 16)
+#define SSIRSEL_CIM_SOSEL4_SRC0_SET   (2U << 16)
+#define SSIRSEL_CIM_SOSEL4_MIX_SET    (3U << 16)
+#define SSIRSEL_CIM_SOSEL3_MASK       (3U << 12)
+#define SSIRSEL_CIM_SOSEL3_SRC1_SET   (0U << 12)
+#define SSIRSEL_CIM_SOSEL3_SRC0_SET   (1U << 12)
+#define SSIRSEL_CIM_SOSEL3_MIX_SET    (2U << 12)
+#define SSIRSEL_CIM_SOSEL2_MASK       (3U << 8)
+#define SSIRSEL_CIM_SOSEL2_SRC3_SET   (0U << 8)
+#define SSIRSEL_CIM_SOSEL2_SRC0_SET   (1U << 8)
+#define SSIRSEL_CIM_SOSEL2_SRC1_SET   (2U << 8)
+#define SSIRSEL_CIM_SOSEL2_MIX_SET    (3U << 8)
+#define SSIRSEL_CIM_SOSEL1_MASK       (3U << 4)
+#define SSIRSEL_CIM_SOSEL1_SRC2_SET   (0U << 4)
+#define SSIRSEL_CIM_SOSEL1_SRC0_SET   (1U << 4)
+#define SSIRSEL_CIM_SOSEL1_SRC1_SET   (2U << 4)
+#define SSIRSEL_CIM_SOSEL1_MIX_SET    (3U << 4)
+#define SSIRSEL_CIM_SOSEL0_MASK       (3U << 0)
+#define SSIRSEL_CIM_SOSEL0_SRC0_SET   (0U << 0)
+#define SSIRSEL_CIM_SOSEL0_SRC1_SET   (1U << 0)
+#define SSIRSEL_CIM_SOSEL0_MIX_SET    (2U << 0)
+
+#define FDTSEL_CIM_SCKDIV_SHIFT       (16U)
+#define FDTSEL_CIM_SCKDIV_MASK        (0x7FFU << FDTSEL_CIM_SCKDIV_SHIFT)
+#define FDTSEL_CIM_DIVEN_MASK         (1U << 8)
+#define FDTSEL_CIM_DIVEN_SET          (1U << 8)
+#define FDTSEL_CIM_MTUSEL_MASK        (1U << 4)
+#define FDTSEL_CIM_MTUSEL_SET_TIOC3A  (0U << 4)
+#define FDTSEL_CIM_MTUSEL_SET_TIOC4A  (1U << 4)
+#define FDTSEL_CIM_SCKSEL_MASK        (0x0FU << 0)
+#define FDTSEL_CIM_SCKSEL_AUDIO_CLK_SET (0U)
+#define FDTSEL_CIM_SCKSEL_AUDIO_X1_SET  (1U)
+#define FDTSEL_CIM_SCKSEL_MLB_CLK_SET   (2U)
+#define FDTSEL_CIM_SCKSEL_USB_X1_SET    (3U)
+#define FDTSEL_CIM_SCKSEL_CLKP1_2_SET   (4U)
+#define FDTSEL_CIM_SCKSEL_MTUSEL2_SET   (5U)
+#define FDTSEL_CIM_SCKSEL_SSIF0_WS_SET  (8U)
+#define FDTSEL_CIM_SCKSEL_SSIF1_WS_SET  (9U)
+#define FDTSEL_CIM_SCKSEL_SSIF2_WS_SET  (10U)
+#define FDTSEL_CIM_SCKSEL_SSIF3_WS_SET  (11U)
+#define FDTSEL_CIM_SCKSEL_SSIF4_WS_SET  (12U)
+#define FDTSEL_CIM_SCKSEL_SSIF5_WS_SET  (13U)
+
+#define FUTSEL_CIM_SCKDIV_SHIFT         (16U)
+#define FUTSEL_CIM_SCKDIV_MASK          (0x7FFU << FDTSEL_CIM_SCKDIV_SHIFT)
+#define FUTSEL_CIM_DIVEN_MASK           (1U << 8)
+#define FUTSEL_CIM_DIVEN_SET            (1U << 8)
+#define FUTSEL_CIM_MTUSEL_MASK          (1U << 4)
+#define FUTSEL_CIM_MTUSEL_SET_TIOC3A    (0U << 4)
+#define FUTSEL_CIM_MTUSEL_SET_TIOC4A    (1U << 4)
+#define FUTSEL_CIM_SCKSEL_MASK          (0x0FU << 0)
+#define FUTSEL_CIM_SCKSEL_AUDIO_CLK_SET (0U)
+#define FUTSEL_CIM_SCKSEL_AUDIO_X1_SET  (1U)
+#define FUTSEL_CIM_SCKSEL_MLB_CLK_SET   (2U)
+#define FUTSEL_CIM_SCKSEL_USB_X1_SET    (3U)
+#define FUTSEL_CIM_SCKSEL_CLKP1_2_SET   (4U)
+#define FUTSEL_CIM_SCKSEL_MTUSEL2_SET   (5U)
+#define FUTSEL_CIM_SCKSEL_SSIF0_WS_SET  (8U)
+#define FUTSEL_CIM_SCKSEL_SSIF1_WS_SET  (9U)
+#define FUTSEL_CIM_SCKSEL_SSIF2_WS_SET  (10U)
+#define FUTSEL_CIM_SCKSEL_SSIF3_WS_SET  (11U)
+#define FUTSEL_CIM_SCKSEL_SSIF4_WS_SET  (12U)
+#define FUTSEL_CIM_SCKSEL_SSIF5_WS_SET  (13U)
+
+#define SSIPMD_CIM_SSI5CKS_MASK     (1U << 21)
+#define SSIPMD_CIM_SSI5CKS_SET      (1U << 21)
+#define SSIPMD_CIM_SSI4CKS_MASK     (1U << 20)
+#define SSIPMD_CIM_SSI4CKS_SET      (1U << 20)
+#define SSIPMD_CIM_SSI3CKS_MASK     (1U << 19)
+#define SSIPMD_CIM_SSI3CKS_SET      (1U << 19)
+#define SSIPMD_CIM_SSI2CKS_MASK     (1U << 18)
+#define SSIPMD_CIM_SSI2CKS_SET      (1U << 18)
+#define SSIPMD_CIM_SSI1CKS_MASK     (1U << 17)
+#define SSIPMD_CIM_SSI1CKS_SET      (1U << 17)
+#define SSIPMD_CIM_SSI0CKS_MASK     (1U << 16)
+#define SSIPMD_CIM_SSI0CKS_SET      (1U << 16)
+#define SSIPMD_CIM_SSI3PMD_SHIFT    (14U)
+#define SSIPMD_CIM_SSI3PMD_MASK     (3U << SSIPMD_CIM_SSI3PMD_SHIFT)
+#define SSIPMD_CIM_SSI345EN_MASK    (1U << 12)
+#define SSIPMD_CIM_SSI345EN_SET     (1U << 12)
+#define SSIPMD_CIM_SSI4PMD_SHIFT    (10U)
+#define SSIPMD_CIM_SSI4PMD_MASK     (3U << SSIPMD_CIM_SSI4PMD_SHIFT)
+#define SSIPMD_CIM_SSI5PMD_SHIFT    (8U)
+#define SSIPMD_CIM_SSI5PMD_MASK     (3U << SSIPMD_CIM_SSI5PMD_SHIFT)
+#define SSIPMD_CIM_SSI012EN_MASK    (1U << 4)
+#define SSIPMD_CIM_SSI012EN_SET     (1U << 4)
+#define SSIPMD_CIM_SSI2PMD_SHIFT    (2U)
+#define SSIPMD_CIM_SSI2PMD_MASK     (3U << SSIPMD_CIM_SSI2PMD_SHIFT)
+#define SSIPMD_CIM_SSI1PMD_SHIFT    (0U)
+#define SSIPMD_CIM_SSI1PMD_MASK     (3U << SSIPMD_CIM_SSI1PMD_SHIFT)
+
+#define SSICTRL_CIM_SSI3TX_SET      (1U << 30)
+#define SSICTRL_CIM_SSI4TX_SET      (1U << 29)
+#define SSICTRL_CIM_SSI5TX_SET      (1U << 28)
+#define SSICTRL_CIM_SSI345TEN_SET   (1U << 17)
+#define SSICTRL_CIM_SSI0TX_SET      (1U << 14)
+#define SSICTRL_CIM_SSI1TX_SET      (1U << 13)
+#define SSICTRL_CIM_SSI2TX_SET      (1U << 12)
+#define SSICTRL_CIM_SSI012TEN_SET   (1U << 1)
+
+#define SRCRSEL_CIM_PLACE_N_MASK    (7U)
+#define SRCRSEL_CIM_PLACE_N_SHIFT   (4U)
+
+#define MIXRSEL_CIM_PLACE_N_MASK    (7U)
+#define MIXRSEL_CIM_PLACE_N_SHIFT   (4U)
+
+
+/* SSIF Register Set Value */
+/* Init Value */
+#define SCUX_SSICR_INIT_VALUE       (0x00000000U)
+#define SCUX_SSIFCR_INIT_VALUE      (0x00000000U)
+#define SCUX_SSIFTDR_INIT_VALUE     (0x00000000U)
+#define SCUX_SSITDMR_INIT_VALUE     (0x00000000U)
+#define SCUX_SSIFCCR_INIT_VALUE     (0x00000000U)
+#define SCUX_SSIFCMR_INIT_VALUE     (0x00000000U)
+
+/* SSIF bit value & mask & fixed setting */
+#define SCUX_SSICR_CKS_SET              (1U << 30)
+#define SCUX_SSICR_TUIEN_SET            (1U << 29)
+#define SCUX_SSICR_TOIEN_SET            (1U << 28)
+#define SCUX_SSICR_RUIEN_SET            (1U << 27)
+#define SCUX_SSICR_ROIEN_SET            (1U << 26)
+#define SCUX_SSICR_CHNL_SET_1CH         (0U << 22)
+#define SCUX_SSICR_CHNL_SET_2CH         (1U << 22)
+#define SCUX_SSICR_CHNL_SET_3CH         (2U << 22)
+#define SCUX_SSICR_CHNL_SET_4CH         (3U << 22)
+#define SCUX_SSICR_DWL_16BIT_SET        (1U << 19)
+#define SCUX_SSICR_DWL_24BIT_SET        (5U << 19)
+#define SCUX_SSICR_SWL_SHIFT            (16U)
+#define SCUX_SSICR_SCKD_SET             (1U << 15)
+#define SCUX_SSICR_SWSD_SET             (1U << 14)
+#define SCUX_SSICR_SCKP_SET             (1U << 13)
+#define SCUX_SSICR_SWSP_SET             (1U << 12)
+#define SCUX_SSICR_SPDP_SET             (1U << 11)
+#define SCUX_SSICR_SDTA_SET             (1U << 10)
+#define SCUX_SSICR_DEL_SET              (1U << 8)
+#define SCUX_SSICR_CKDV_SHIFT           (4U)
+#define SCUX_SSICR_TEN_SET              (1U << 1)
+
+#define SCUX_SSITDMR_CONT_SET           (1U << 8)
+#define SCUX_SSITDMR_TDM_SET            (1U << 0)
+
+/* SCUX fixed value */
+#define SCUX_RATE_CONVERT_CALC_VALUE     (0x400000U)
+#define SCUX_CALC_MINFS_VALUE            (100U)
+#define SCUX_MAX_DIV_CLK                 (2046U)
+#define SCUX_MIN_RATE_MIN_PAERCENTAGE    (90U)
+#define SCUX_MIN_RATE_MAX_PAERCENTAGE    (98U)
+#define SCUX_MIN_RATE_DENOMINATOR        (100U)
+#define SCUX_MAX_WAIT_TIME               (0xFFFFFFU)
+#define SCUX_MAX_DIGITAL_VOLUME          (0x7FFFFFU)
+#define SCUX_MAX_RAMP_VOLUME             (0x3FFU)
+#define SCUX_RATE_INT_CONV_VALUE         (1000U)
+#define SCUX_ADJUST_REST_VALUE           (1U)
+#define SCUX_MAX_CONV_RATE               (16000U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH1_2  (125U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH4    (250U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH6    (375U)
+#define SCUX_MIN_CONV_RATE_NORMAL_CH8    (500U)
+#define SCUX_MIN_CONV_RATE_DELAY1        (500U)
+#define SCUX_MIN_CONV_RATE_DELAY2        (1000U)
+#define SCUX_MIN_FREQ                    (1000U)
+#define SCUX_MAX_FREQ_CH1_4              (96000U)
+#define SCUX_MAX_FREQ_CH6                (66000U)
+#define SCUX_MAX_FREQ_CH8                (49000U)
+#define SCUX_PROC_DELAY_NONE             (0U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH1    (641U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH2    (321U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH4    (161U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH6    (102U)
+#define SCUX_PROCESS_DELAY_NORMAL_CH8    (81U)
+#define SCUX_PROCESS_DELAY_1_CH1_2       (81U)
+#define SCUX_PROCESS_DELAY_2_CH1_2       (49U)
+#define SCUX_LOGIC_DELAY_BYPASS_ON       (1U)
+#define SCUX_LOGIC_DELAY_BYPASS_OFF      (3U)
+#define SCUX_AUDIO_X1                    (22579200U)
+#define SCUX_AUDIO_CLK                   (0U)
+#define SCUX_MLB_CLK                     (66670000U)
+#define SCUX_USB_X1                      (48000000U)
+#define SCUX_CLKLP1_DIV2                 (33335000U)
+#define SCUX_SYSTEMWORD_16               (16U)
+#define SCUX_SYSTEMWORD_24               (24U)
+#define SCUX_SYSTEMWORD_32               (32U)
+#define SCUX_SYSTEMWORD_48               (48U)
+#define SCUX_SYSTEMWORD_64               (64U)
+#define SCUX_SYSTEMWORD_128              (128U)
+#define SCUX_SYSTEMWORD_256              (256U)
+#define SCUX_SSIF_CLK_DIV1               (1U)
+#define SCUX_SSIF_CLK_DIV2               (2U)
+#define SCUX_SSIF_CLK_DIV4               (4U)
+#define SCUX_SSIF_CLK_DIV8               (8U)
+#define SCUX_SSIF_CLK_DIV16              (16U)
+#define SCUX_SSIF_CLK_DIV32              (32U)
+#define SCUX_SSIF_CLK_DIV64              (64U)
+#define SCUX_SSIF_CLK_DIV128             (128U)
+#define SCUX_SSIF_CLK_DIV6               (6U)
+#define SCUX_SSIF_CLK_DIV12              (12U)
+#define SCUX_SSIF_CLK_DIV24              (24U)
+#define SCUX_SSIF_CLK_DIV48              (48U)
+#define SCUX_SSIF_CLK_DIV96              (96U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH0    (0U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH1    (1U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH2    (2U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH3    (3U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH4    (4U)
+#define SCUX_SSIF_GPIO_SNCR_SHIFT_CH5    (5U)
+#define SCUX_DUMMY_BUF_SIZE              (4096U)
+#define SCUX_GET_ROUTE_MASK              (0xF000)
+#define SCUX_ROUTE_MEM_TO_MEM            (0x1000)
+#define SCUX_ROUTE_SSIF                  (0x2000)
+#define SCUX_ROUTE_MIX                   (0x3000)
+#define SCUX_FIFO_SIZE_CH0_1             (1024U)
+#define SCUX_FIFO_SIZE_CH2_3             (256U)
+#define SCUX_SSIF_NO_USE_CH              (0xFFFFU)
+#define SCUX_SSIF_USE_MIX_BIT            (0x1000U)
+#define SRC_MOD_SRC0                     (0U)
+#define SRC_MOD_SRC1                     (1U)
+#define SCUX_EVEN_VALUE_DIV              (2U)
+#define SCUX_SSIF_NUM_CH_ARRANGEMENT     (3U)
+#define SCUX_SSIF_CH_ARRANGEMENT1        (0U)
+#define SCUX_SSIF_CH_ARRANGEMENT2        (1U)
+#define SCUX_SSIF_CH_ARRANGEMENT3        (2U)
+#define SCUX_DMA_UNIT_SIZE16             (2U)
+#define SCUX_DMA_UNIT_SIZE24             (4U)
+#define SCUX_HALF_SIZE_VALUE             (2U)
+#define SCUX_RAMP_WAIT_MAX               (10U)
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* DRV Status */
+typedef enum
+{
+    SCUX_DRV_UNINIT = 0,   /* Uninit */
+#if(1) /* mbed */
+    SCUX_DRV_INIT_RUNNING = 1, /* Init running */
+    SCUX_DRV_INIT         = 2  /* Init */
+#else  /* not mbed */
+    SCUX_DRV_INIT   = 1    /* Init */
+#endif /* end mbed */
+} scux_stat_drv_t;
+
+/* Channel Status */
+typedef enum
+{
+    SCUX_CH_UNINIT         = 0,   /* Uninit */
+    SCUX_CH_INIT           = 1,   /* Init */
+    SCUX_CH_STOP           = 2,   /* Open (request can't be received) */
+    SCUX_CH_TRANS_IDLE     = 4,   /* Open (request is not received) */
+    SCUX_CH_TRANS_RD       = 8,   /* Transfer (read only) */
+    SCUX_CH_TRANS_WR       = 16,  /* Transfer (read only) */
+    SCUX_CH_TRANS_RDWR     = 32,  /* Transfer (read & write) */
+    SCUX_CH_STOP_WAIT      = 64,  /* Transfer (wait flush stop) */
+    SCUX_CH_STOP_WAIT_IDLE = 128  /* Transfer (wait flush stop and request is not received */
+} scux_stat_ch_t;
+
+/* fifo size */
+typedef enum
+{
+    SCUX_FIFO_REQ_SIZE_256_64 = 0, /* fifo size is 256 data (SRC0, 1) and 64 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_128_32 = 1, /* fifo size is 128 data (SRC0, 1) and 32 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_64_16  = 2, /* fifo size is 64 data (SRC0, 1) and 16 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_32_8   = 3, /* fifo size is 32 data (SRC0, 1) and 8 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_16_4   = 4, /* fifo size is 16 data (SRC0, 1) and 4 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_8_2    = 5, /* fifo size is 8 data (SRC0, 1) and 2 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_4_1    = 6, /* fifo size is 4 data (SRC0, 1) and 1 data (SRC2, 3) */
+    SCUX_FIFO_REQ_SIZE_2      = 7, /* fifo size is 2 data (SRC0, 1) */
+    SCUX_FIFO_REQ_SIZE_1      = 8  /* fifo size is 1 data (SRC0, 1) */
+} scux_fifo_req_size_t;
+
+/* SSIF over sampling clock divide rate */
+typedef enum
+{
+    SCUX_SSIF_CKDIV_1      = 0,   /* divide rate 1/1 */
+    SCUX_SSIF_CKDIV_2      = 1,   /* divide rate 1/2 */
+    SCUX_SSIF_CKDIV_4      = 2,   /* divide rate 1/4 */
+    SCUX_SSIF_CKDIV_8      = 3,   /* divide rate 1/8 */
+    SCUX_SSIF_CKDIV_16     = 4,   /* divide rate 1/16 */
+    SCUX_SSIF_CKDIV_32     = 5,   /* divide rate 1/32 */
+    SCUX_SSIF_CKDIV_64     = 6,   /* divide rate 1/64 */
+    SCUX_SSIF_CKDIV_128    = 7,   /* divide rate 1/128 */
+    SCUX_SSIF_CKDIV_6      = 8,   /* divide rate 1/6 */
+    SCUX_SSIF_CKDIV_12     = 9,   /* divide rate 1/12 */
+    SCUX_SSIF_CKDIV_24     = 10,  /* divide rate 1/24 */
+    SCUX_SSIF_CKDIV_48     = 11,  /* divide rate 1/48 */
+    SCUX_SSIF_CKDIV_96     = 12   /* divide rate 1/96 */
+} scux_ssif_ckdiv_t;
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/* Information of SCUX register */
+typedef struct
+{
+    struct st_scux_from_dvuir_dvu0_n            *p_dvu_reg;      /* DVU register */
+    struct st_scux_from_srcir0_2src0_n          *p_src_reg;      /* SRC register */
+    struct st_scux_from_ffuir_ffu0_n            *p_ffu_reg;      /* FFU register */
+    struct st_scux_from_ffdir_ffd0_n            *p_ffd_reg;      /* FFD register */
+    struct st_scux_from_opcir_opc0_n            *p_opc_reg;      /* OPC register */
+    struct st_scux_from_ipcir_ipc0_n            *p_ipc_reg;      /* IPC register */
+    volatile uint32_t                           *mixir_mix0_0;   /* MIXIR_MIX0_0 register */
+    volatile uint32_t                           *madir_mix0_0;   /* MADIR_MIX0_0 register */
+    volatile uint32_t                           *mixbr_mix0_0;   /* MIXBR_MIX0_0 register */
+    volatile uint32_t                           *mixmr_mix0_0;   /* MIXMR_MIX0_0 register */
+    volatile uint32_t                           *mvpdr_mix0_0;   /* MVPDR_MIX0_0 register */
+    volatile uint32_t                           *mdb_n_r_mix0_0; /* MDBAR_MIX0_0 - MDBDR_MIX0_0 register */
+    volatile uint32_t                           *mdber_mix0_0;   /* MDBER_MIX0_0 register */
+    volatile uint32_t                           *mixsr_mix0_0;   /* MIXSR_MIX0_0 register */
+    volatile uint32_t                           *swrsr_cim;      /* SWRSR_CIM register */
+    volatile uint32_t                           *dmacr_cim;      /* DMACR_CIM register */
+    volatile uint32_t                           *dmatd_n_cim;    /* DMATD0_CIM - DMATD3_CIM register */
+    volatile uint32_t                           *dmatu_n_cim;    /* DMATU0_CIM - DMATU3_CIM register */
+    volatile uint32_t                           *ssirsel_cim;    /* SSIRSEL_CIM register */
+    volatile uint32_t                           *fdtsel_n_cim;   /* FDTSEL0_CIM - FDTSEL3_CIM register */
+    volatile uint32_t                           *futsel_n_cim;   /* FUTSEL0_CIM - FUTSEL3_CIM register */
+    volatile uint32_t                           *ssipmd_cim;     /* SSIPMD_CIM register */
+    volatile uint32_t                           *ssictrl_cim;    /* SSICTRL_CIM register */
+    volatile uint32_t                           *srcrsel_n_cim;  /* SRCRSEL0_CIM - SRCRSEL3_CIM register */
+    volatile uint32_t                           *mixrsel_cim;    /* MIXRSEL_CIM register */
+} scux_reg_info_t;
+
+/* Information of SSIF */
+typedef struct
+{
+    bool_t                  ssif_enable;              /* USE SSIF flag */
+    bool_t                  ssif_setup;               /* SSIF setup complete flag */
+    osSemaphoreId           sem_ch_scux_ssif_access;  /* SSIF info semaphore */
+    int_t                   scux_channel;             /* SCUX ch which is using SSIF */
+    scux_src_clk_source_t   pin_clk;                  /* AUDIO_CLK source */
+    scux_pin_mode_t         pin_mode;                 /* SSIF sync setting */
+    scux_pin_mode_t         pin_mode_backup;          /* back up of SSIF sync setting */
+    scux_ssif_cfg_t         ssif_cfg;                 /* SSIF parameters */
+    scux_ssif_ckdiv_t       clk_div;                  /* Over sampling clock divide rate */
+    volatile struct st_ssif *p_scux_ssif_reg;         /* SSIF register */
+} scux_ssif_info_t;
+
+/* Information of Driver */
+typedef struct
+{
+    osSemaphoreId        sem_shared_access;        /* Shared info semaphore */
+    bool_t               mix_setup;                /* MIX setup complete flag */
+    uint32_t             mix_run_ch;               /* MIX used channel */
+    uint32_t             mix_ssif_ch;              /* SSIF channel on used MIX */
+    bool_t               mixmode_ramp;             /* Ramp mode / Step mode select */
+    scux_mix_ramp_time_t up_period;                /* Ramp up period */
+    scux_mix_ramp_time_t down_period;              /* Ramp down period */
+    uint32_t             mix_vol[SCUX_CH_NUM];     /* MIX volume value */
+    scux_audio_channel_t select_out_data_ch[SCUX_AUDIO_CH_MAX]; /* Audio data position setting */
+    uint32_t             ssictrl_cim_value;        /* SSICTRL_CIM register (write only) value */
+} scux_shared_info_t;
+
+/* Information of Channel */
+typedef struct
+{
+    int_t              channel;                    /* Channel Number */
+    bool_t             enabled;                    /* Used channel flag */
+    int_t              open_flags;                 /* Read/write flag */
+    scux_stat_ch_t     ch_stat;                    /* Channel Status */
+    osSemaphoreId      sem_ch_scux_access;         /* Channel Semaphore */
+    AHF_S              tx_que;                     /* Write request queue */
+    AHF_S              rx_que;                     /* Read request queue */
+    AIOCB              *p_tx_aio;                  /* Write request information pointer */
+    AIOCB              *p_tx_next_aio;             /* Next write request information pointer */ 
+    AIOCB              *p_rx_aio;                  /* Read request information pointer */
+    AIOCB              *p_rx_next_aio;             /* Next read request information pointer */ 
+    uint8_t            int_level;                  /* Interrupt priority */
+    IRQn_Type          int_num[SCUX_INT_MAX];      /* Each interrupt number */
+    int_t              dma_tx_ch;                  /* Write DMA channel */
+    int_t              dma_rx_ch;                  /* Read DMA channel */
+    dma_res_select_t   dma_resource_tx;            /* Write DMA resource */
+    dma_res_select_t   dma_resource_rx;            /* Read DMA resource */
+    uint32_t           dma_tx_current_size;        /* Current write DMA size */
+    uint32_t           dma_tx_next_size;           /* Next write DMA size */
+    uint32_t           dma_rx_current_size;        /* Current read DMA size */
+    uint32_t           dma_rx_next_size;           /* Next read DMA size */
+    dma_ch_setup_t     dma_tx_setup;               /* Write DMA paramtter */
+    dma_ch_setup_t     dma_rx_setup;               /* Read DMA paramtter */
+    scux_reg_info_t    *p_scux_reg;                /* SCUX register information */
+    scux_route_t       route_set;                  /* SCUX route paramter */
+    scux_src_cfg_t     src_cfg;                    /* SRC parameter */
+    scux_dvu_cfg_t     dvu_cfg;                    /* DVU parameter */
+    bool_t             dvu_setup;                  /* DVU setup complete flag */
+    uint32_t           dvu_mute_stat;              /* DVU mute status */
+    scux_ssif_info_t   *p_ssif_info1;              /* SSIF channel information1  */
+    scux_ssif_info_t   *p_ssif_info2;              /* SSIF channel information2  */
+    scux_ssif_info_t   *p_ssif_info3;              /* SSIF channel information3  */
+    void               (*p_flush_callback)(int_t ercd);   /* Call back pointer for flush stop */
+    bool_t             first_tx_flag;              /* First write data transfer flag */
+    bool_t             first_rx_flag;              /* First read data transfer flag */    
+    bool_t             first_ramp_flag;            /* First ramp setting flag */
+    volatile uint8_t   *p_tx_dummy_data;           /* Write dummy data buffer pointer */
+    volatile uint8_t   *p_rx_dummy_data;           /* Read dummy data buffer pointer */
+    uint32_t           flush_stop_size;            /* Needed transfer size for flush stop */ 
+    uint32_t           fifo_size;                  /* Fifo size */
+    uint32_t           fifo_req_size;              /* Fifo request size */
+    uint32_t           last_dummy_size;            /* Last dummy data size for flush stop */
+    uint32_t           tx_fifo_total_size;         /* Total data size of write request size / FIFO size */
+    uint32_t           rx_fifo_total_size;         /* Total data size of read request size / FIFO size */
+    bool_t             tx_dummy_run_flag;          /* Dummy data transfer flag */
+    bool_t             cancel_operate_flag;        /* indicate cancel operation */
+    bool_t             restart_ramp_flag;          /* ramp restart flag after cancel operation */
+    uint32_t           input_rate;                 /* Input rate */
+    uint32_t           output_rate;                /* Output rate */
+    uint32_t           futsel_cim_value;           /* FUTSEL_CIM register value (write only) */
+    int_t              err_stat_backup;            /* SCUX HW error status backup */
+} scux_info_ch_t;
+
+/* Information of Driver */
+typedef struct
+{
+    scux_stat_drv_t    drv_stat;              /* DRV status */
+    scux_info_ch_t     info_ch[SCUX_CH_NUM];  /* CH status */
+    scux_shared_info_t shared_info;           /* shared resource information */
+} scux_info_drv_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+scux_info_drv_t *SCUX_GetDrvInstance(void);
+scux_info_ch_t  *SCUX_GetDrvChInfo(const int_t channel);
+scux_ssif_info_t *SCUX_GetSsifChInfo(const int_t channel);
+#if(1) /* mbed */
+int_t SCUX_InitializeOne(const int_t channel, const scux_channel_cfg_t * const p_scux_init_param);
+void SCUX_UnInitializeOne(const int_t channel);
+#endif /* end mbed */
+int_t SCUX_Initialize(const scux_channel_cfg_t * const p_scux_init_param);
+void SCUX_UnInitialize(void);
+int_t SCUX_OpenChannel(const int_t channel, const int_t flags);
+int_t SCUX_CloseChannel(const int_t channel);
+int_t SCUX_IoctlTransStart(const int_t channel);
+int_t SCUX_IoctlFlushStop(const int_t channel, void (* const callback)(int_t ercd), const int_t was_masked);
+int_t SCUX_IoctlClearStop(const int_t channel, const int_t was_masked);
+void SCUX_IoctlSetRoute(const int_t channel, const scux_route_t route);
+int_t SCUX_IoctlSetPinClk(const int_t channel, const scux_ssif_pin_clk_t * const p_pin_clk_param);
+int_t SCUX_IoctlSetPinMode(const int_t channel, const scux_ssif_pin_mode_t * const p_pin_mode_param);
+void SCUX_IoctlSetSrcCfg(const int_t channel, const scux_src_cfg_t * const p_src_param);
+void SCUX_IoctlSetDvuCfg(const int_t channel, const scux_dvu_cfg_t * const p_dvu_param);
+int_t SCUX_IoctlSetDvuDigiVol(const int_t channel, const scux_dvu_digi_vol_t * const p_digi_vol_param);
+int_t SCUX_IoctlSetDvuRampVol(const int_t channel, const scux_dvu_ramp_vol_t * const p_ramp_vol_param);
+int_t SCUX_IoctlSetDvuZerocrossMute(const int_t channel, const scux_zc_mute_t * const p_zc_mute_param);
+int_t SCUX_IoctlSetStopMute(const int_t channel, const uint32_t audio_channel);
+int_t SCUX_IoctlSetMixCfg(const scux_mix_cfg_t * const p_mix_param);
+int_t SCUX_IoctlSetMixVol(const int_t channel, const uint32_t mix_vol);
+int_t SCUX_IoctlSetSsifCfg(const scux_ssif_cfg_t *const p_ssif_param);
+void SCUX_IoctlGetWriteStat(const int_t channel, uint32_t * const p_write_stat);
+void SCUX_IoctlGetReadStat(const int_t channel, uint32_t * const p_read_stat);
+void SCUX_IoctlGetDvuStat(const int_t channel, uint32_t * const p_dvu_stat);
+void SCUX_IoctlGetMuteStat(const int_t channel, uint32_t * const p_mute_stat);
+void SCUX_IoctlGetMixStat(const int_t channel, uint32_t * const p_mix_stat);
+int_t SCUX_CheckParam(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_FlushWriteStart(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_InitHw(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetupSsif(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetupSrc(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetupDvu(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_SetupDma(scux_info_ch_t * const p_scux_info_ch);
+void  SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_CopyWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio);
+int_t SCUX_DirectWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio);
+int_t SCUX_CopyReadStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_read_aio);
+int_t SCUX_CopyCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio);
+int_t SCUX_DirectCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio);
+int_t SCUX_CopyCancelAll(scux_info_ch_t * const p_scux_info_ch);
+int_t SCUX_DirectCancelAll(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_AdjustAccessFifo(scux_info_ch_t * const p_scux_info_ch, const uint32_t tx_remain_size, const uint32_t rx_remain_size);
+void  SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch);
+void  SCUX_SyncStopHw(const scux_info_ch_t * const p_scux_info_ch);
+void  SCUX_AsyncStopHw(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetDigiVolRegister(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetRampVolRegister(scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetZerocrossMuteRegister(const scux_info_ch_t * const p_scux_info_ch);
+void SCUX_SetMixVolRegister(const int_t channel);
+int_t SCUX_CheckSsifClockDiv(const scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch_num);
+void SCUX_SetupSsifGpio(const scux_ssif_ch_num_t ssif_ch);
+size_t SCUX_StrNLen(const char_t* p_str, size_t maxlen);
+
+#endif /* SCUX_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/scux/scux_board.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,565 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_board.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* @brief        SCUX functions depending on borad 
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CheckSsifClockDiv
+* @brief         Check SSIF clock divide rate.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     ssif_ch : Used ssif channel number.
+* @retval        ESUCCESS : Parameter is no problems.
+*                EPERM : Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CheckSsifClockDiv(const scux_info_ch_t * const p_scux_info_ch, const uint32_t ssif_ch_num)
+{
+    int_t retval = ESUCCESS;
+    uint32_t input_clk;
+    uint32_t dot_clk;
+    uint32_t n_syswd_per_smp;
+    uint32_t syswd_len =0;
+    uint32_t smp_freq;
+    uint32_t result;
+    uint32_t division;
+    scux_ssif_info_t * p_ssif_ch;
+    
+    p_ssif_ch = SCUX_GetSsifChInfo((int_t)ssif_ch_num);
+
+    if ((NULL == p_scux_info_ch) || (NULL == p_ssif_ch))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (false == p_ssif_ch->ssif_cfg.mode_master)
+        {
+            /* In slave mode, a temporary value is to SCUX_SSIF_CKDIV_1 (0) */
+            p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_1;         
+        }
+        else
+        {
+            /* check only SSIF master mode */
+            /* get source clock */
+            if (false == p_ssif_ch->ssif_cfg.select_audio_clk)
+            {
+                input_clk = SCUX_AUDIO_X1;
+            }
+            else
+            {
+                input_clk = SCUX_AUDIO_CLK;
+            }
+            
+            if (0u == input_clk)
+            {
+                retval = EPERM;
+            }
+        
+            if (ESUCCESS == retval)
+            {
+                switch (p_ssif_ch->ssif_cfg.system_word)
+                {
+                    case SCUX_SSIF_SYSTEM_LEN_16 :
+                        syswd_len = SCUX_SYSTEMWORD_16;
+                    break;
+                    
+                    case SCUX_SSIF_SYSTEM_LEN_24 :
+                        syswd_len = SCUX_SYSTEMWORD_24;
+                    break;
+        
+                    case SCUX_SSIF_SYSTEM_LEN_32 :
+                        syswd_len = SCUX_SYSTEMWORD_32;
+                    break;
+        
+                    case SCUX_SSIF_SYSTEM_LEN_48 :
+                        syswd_len = SCUX_SYSTEMWORD_48;
+                    break;
+                            
+                    case SCUX_SSIF_SYSTEM_LEN_64 :
+                        syswd_len = SCUX_SYSTEMWORD_64;
+                    break;
+        
+                    case SCUX_SSIF_SYSTEM_LEN_128 :
+                        syswd_len = SCUX_SYSTEMWORD_128;
+                    break;
+        
+                    case SCUX_SSIF_SYSTEM_LEN_256 :
+                        syswd_len = SCUX_SYSTEMWORD_256;
+                    break;
+                            
+                    default :
+                        retval = EPERM;
+                    break;
+                }
+        
+                smp_freq = p_scux_info_ch->src_cfg.output_ws;
+            
+                if (false == p_ssif_ch->ssif_cfg.use_tdm)
+                {
+                    n_syswd_per_smp = SCUX_USE_CH_2;
+                }
+                else
+                {
+                    n_syswd_per_smp = p_scux_info_ch->src_cfg.use_ch;
+                }
+        
+                dot_clk = syswd_len * n_syswd_per_smp * smp_freq;
+                if (0u == dot_clk)
+                {
+                    retval = EPERM;
+                }
+                else
+                {
+                    /* check if input audio clock can be divided by dotclock */
+                    result = input_clk % dot_clk;
+        
+                    if (0U != result)
+                    {
+                        /* cannot create dotclock from input audio clock */
+                        retval = EPERM;
+                    }
+                    else
+                    {
+                        division = input_clk / dot_clk;
+        
+                        switch (division)
+                        {
+                            case SCUX_SSIF_CLK_DIV1:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_1;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV2:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_2;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV4:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_4;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV8:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_8;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV16:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_16;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV32:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_32;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV64:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_64;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV128:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_128;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV6:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_6;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV12:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_12;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV24:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_24;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV48:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_48;
+                            break;
+                            
+                            case SCUX_SSIF_CLK_DIV96:
+                                p_ssif_ch->clk_div = SCUX_SSIF_CKDIV_96;
+                            break;
+                            
+                            default:
+                                retval = EPERM;
+                            break;
+                        }
+                    }
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CheckSsifClockDiv
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupSsifGpio
+* @brief         GPIO of SSIF module setup.
+
+*                Description:<br>
+*                R7S72100 Boards depended pin connections bellow<br>
+*                Clock settings<br>
+*                  AUDIO_X1 : Private use pin(nothing to do)<br>
+*                  AUDIO_X2 : No connection<br>
+*                  AUDIO_CLK: Working with SSIF5<br>
+*                Channel settings<br>
+*                  SSIF0    : Fully connected to WM8978<br>
+*                  SSIF1    : Read only (NC:SSITxD1) connected to CD Deck<br>
+*                  SSIF2    : No connection<br>
+*                  SSIF3    : Write only (NC:SSIRxD3) connected to AK4353<br>
+*                  SSIF4    : Fully connected to AK4353<br>
+*                  SSIF5    : Fully connected to HCI
+*                
+* @param[in]     ssif_ch :SSIF channel number.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SetupSsifGpio(const scux_ssif_ch_num_t ssif_ch)
+{
+    switch (ssif_ch)
+    {
+        case SCUX_SSIF_CH_0:
+            /* SSISCK0(P4_4, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N4);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS0(P4_5, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N5);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD0(P4_6, Alternative Mode 5,Input) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N6);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD0(P4_7, Alternative Mode 5,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N7);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N7);
+        break;
+
+        case SCUX_SSIF_CH_1:
+            /* SSISCK1(P3_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS1(P3_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC3 |=  (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD1(P3_6, Alternative Mode 3,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD1:  no connection */
+        break;
+
+        case SCUX_SSIF_CH_2:
+            /* SSISCK2:  no connection */
+            /* SSIWS2:   no connection */
+            /* SSIDATA2: no connection */
+            break;
+
+        case SCUX_SSIF_CH_3:
+            /* SSISCK3(P4_12, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N12);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N12);
+
+            GPIO.PIPC4  |= (uint16_t) GPIO_BIT_N12;
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N12);
+
+            /* SSIWS3(P4_13, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N13);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N13);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N13);
+
+            /* SSIRxD3:  no connection */
+
+            /* SSITxD3(P4_15, Alternative Mode 6,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N15);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N15);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N15);
+        break;
+
+        case SCUX_SSIF_CH_4:
+            /* SSISCK4(P11_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS4(P11_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC11  |= (uint16_t) GPIO_BIT_N5;
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIDATA4(P11_6, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N6);
+        break;
+
+        case SCUX_SSIF_CH_5:
+            /* SSISCK5(P2_4, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS5(P2_5, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD5(P2_6, Alternative Mode 4,Input) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD5(P2_7, Alternative Mode 4,Output) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM2    &= (uint16_t)~(GPIO_BIT_N7);
+
+            /* AUDIO_CLK(P3_1, Alternative Mode 6,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N1);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFC3   |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PFCE3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFCAE3 |= (uint16_t) (GPIO_BIT_N1);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N1);
+        break;
+
+        default:
+            /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+            /* <-IPA R3.5.2 */
+            /* NOTREACHED on At the time of a normal performance */
+        break;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSsifGpio
+******************************************************************************/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/scux/scux_dev.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,4833 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_dev.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* @brief        SCUX device control functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/* SSIF clock mask register table define */
+static const uint32_t gb_cpg_scux_ssif_stbcr_bit[SCUX_SSIF_CH_NUM] = 
+{ 
+    CPG_STBCR11_BIT_MSTP115,    /* SSIF0 */
+    CPG_STBCR11_BIT_MSTP114,    /* SSIF1 */
+    CPG_STBCR11_BIT_MSTP113,    /* SSIF2 */
+    CPG_STBCR11_BIT_MSTP112,    /* SSIF3 */
+    CPG_STBCR11_BIT_MSTP111,    /* SSIF4 */
+    CPG_STBCR11_BIT_MSTP110     /* SSIF5 */
+};
+
+/* SSIF software reset register table define */
+static const uint32_t gb_cpg_scux_ssif_swrst_bit[SCUX_SSIF_CH_NUM] = 
+{ 
+    CPG_SWRSTCR1_BIT_SRST16,    /* SSIF0 */
+    CPG_SWRSTCR1_BIT_SRST15,    /* SSIF1 */
+    CPG_SWRSTCR1_BIT_SRST14,    /* SSIF2 */
+    CPG_SWRSTCR1_BIT_SRST13,    /* SSIF3 */
+    CPG_SWRSTCR1_BIT_SRST12,    /* SSIF4 */
+    CPG_SWRSTCR1_BIT_SRST11     /* SSIF5 */
+};
+
+/* SSIF noise cancel register table define */
+static const uint32_t gb_cpg_scux_ssif_sncr_bit[SCUX_SSIF_CH_NUM] = 
+{ 
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH0,  /* SSIF0 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH1,  /* SSIF1 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH2,  /* SSIF2 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH3,  /* SSIF3 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH4,  /* SSIF4 */
+    SCUX_SSIF_GPIO_SNCR_SHIFT_CH5   /* SSIF5 */
+};
+
+/* AIOCB information for DMA */
+static AIOCB gb_scux_write_dma_aio[SCUX_CH_NUM];
+static AIOCB gb_scux_read_dma_aio[SCUX_CH_NUM];
+
+/******************************************************************************
+ Function prototypes
+******************************************************************************/
+ 
+static void  SCUX_SetupDataPosition(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupSrcClk(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupFifo(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupSrcFunction(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupDvuVolume(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_SetupMix(scux_info_ch_t * const p_scux_info_ch);
+static void  SCUX_DMA_CopyRxCallBack(union sigval const param);
+static void  SCUX_DMA_CommonTxNextDummyData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxEndFlush(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxNextRemainData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxNextData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_CopyTxCallBack(union sigval const param);
+static void  SCUX_DMA_DirectTxEndFlush(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_DirectTxNextRemainData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_DirectTxNextData(scux_info_ch_t * const p_info_ch);
+static void  SCUX_DMA_DirectTxCallBack(union sigval const param);
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyWriteStart
+* @brief         Start write request (mem->mem).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_write_aio:Write request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CopyWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio)
+{
+    int_t    retval;
+    int_t    dma_retval;
+    dma_trans_data_t dma_address_param;
+    uint32_t         dma_src_addr;
+    int_t            ret;
+    
+    if ((NULL == p_scux_info_ch) || (NULL == p_write_aio))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
+        
+        if (ESUCCESS != retval)
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            /* set first trans information */
+            p_scux_info_ch->p_tx_aio = p_write_aio;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+            p_scux_info_ch->first_tx_flag = false;
+                
+            /* cast uint8_t pointer from void pointer */
+            dma_src_addr = (uint32_t)p_write_aio->aio_buf;
+                
+            /* set 1st DMA parameter */
+            dma_address_param.src_addr = (void *)dma_src_addr;
+            dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_address_param.count = p_write_aio->aio_nbytes;
+                
+            dma_retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, &ret);
+            if (ESUCCESS != dma_retval)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
+                /* enable interrupt */
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET | 
+                                                                       DEVMR_FFD0_DEVMOF_SET | 
+                                                                       DEVMR_FFD0_DEVMOL_SET | 
+                                                                       DEVMR_FFD0_DEVMIUF_SET);
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+                /* start clock devide on async mode */
+                if (false == p_scux_info_ch->src_cfg.mode_sync) 
+                {
+                    if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 
+                        (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
+                    {
+                        *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
+                    }
+                }
+                /* update channel status */
+                switch (p_scux_info_ch->ch_stat)
+                {
+                    case SCUX_CH_UNINIT :
+                        /* fall through */
+                    case SCUX_CH_INIT :
+                        /* fall through */
+                    case SCUX_CH_STOP :
+                        retval = EBADF;
+                    break;                  
+                    
+                    case SCUX_CH_TRANS_IDLE :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_WR;
+                    break;
+                    
+                    case SCUX_CH_TRANS_RD :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RDWR;
+                    break;
+                    
+                    case SCUX_CH_TRANS_WR :
+                        /* fall through */
+                    case SCUX_CH_TRANS_RDWR :
+                        /* fall through */
+                    case SCUX_CH_STOP_WAIT :
+                        /* fall through */
+                    case SCUX_CH_STOP_WAIT_IDLE :
+                        /* do nothing, stats isn't updated */
+                    break;
+                    
+                    default :
+                        retval = EFAULT;
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CopyWriteStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DirectWriteStart
+* @brief         Start write request(SSIF direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_write_aio:Write request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_DirectWriteStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_write_aio)
+{
+    int_t    retval;
+    int_t    dma_retval;
+    dma_trans_data_t dma_address_param;
+    dma_trans_data_t next_dma_address_param;
+    uint32_t         dma_src_addr;
+    int_t            ret;
+    uint32_t         ramp_wait_cnt = 0;
+    
+    if ((NULL == p_scux_info_ch) || (NULL == p_write_aio))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
+        
+        if (ESUCCESS != retval)
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            /* set first trans information */
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = p_write_aio;
+            p_scux_info_ch->first_tx_flag = true;
+            
+            /* cast uint8_t pointer from void pointer */
+            dma_src_addr = (uint32_t)p_write_aio->aio_buf;
+            
+            /* set 2nd DMA parameter */
+            next_dma_address_param.src_addr = (void *)(dma_src_addr + (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE));
+            next_dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+            next_dma_address_param.count = (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE);
+            if (0U != (p_write_aio->aio_nbytes % SCUX_HALF_SIZE_VALUE))
+            {
+                /* last data ,when even value size */
+                next_dma_address_param.count++;
+            }
+            dma_retval = R_DMA_NextData(p_scux_info_ch->dma_tx_ch, &next_dma_address_param, &ret);
+            
+            if (ESUCCESS != dma_retval)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                p_scux_info_ch->dma_tx_next_size = next_dma_address_param.count;
+                /* set 1st DMA parameter */
+                dma_address_param.src_addr = (void *)dma_src_addr;
+                dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+                dma_address_param.count = (p_write_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE);
+            
+                dma_retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, &ret);
+                if (ESUCCESS != dma_retval)
+                {
+                    retval = EFAULT;
+                }
+                else
+                {
+                    p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
+                    /* enable interrupt */
+                    p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET | 
+                                                                           DEVMR_FFD0_DEVMOF_SET | 
+                                                                           DEVMR_FFD0_DEVMOL_SET | 
+                                                                           DEVMR_FFD0_DEVMIUF_SET);
+                    p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+                    *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
+                    
+                    switch (p_scux_info_ch->ch_stat)
+                    {
+                        case SCUX_CH_UNINIT :
+                            /* fall through */
+                        case SCUX_CH_INIT :
+                            /* fall through */
+                        case SCUX_CH_STOP :
+                            /* fall through */
+                            retval = EBADF;
+                        break;
+                    
+                        case SCUX_CH_TRANS_IDLE :
+                            p_scux_info_ch->ch_stat = SCUX_CH_TRANS_WR;
+                        break;   
+                        
+                        case SCUX_CH_TRANS_RD :
+                            /* read function disabled */
+                            retval = EFAULT;
+                        break;                 
+                    
+                        case SCUX_CH_TRANS_WR :
+                            /* do nothing, stats isn't updated */
+                        break;                        
+                        
+                        case SCUX_CH_TRANS_RDWR :
+                            /* read function disabled */
+                            retval = EFAULT;
+                        break;                          
+                        
+                        case SCUX_CH_STOP_WAIT :
+                            /* do nothing, stats isn't updated */
+                        break;
+                    
+                        case SCUX_CH_STOP_WAIT_IDLE :
+                            /* read function disabled */
+                            retval = EFAULT;
+                        break; 
+                    
+                        default :
+                            /* NOTREACHED on At the time of a normal performance */
+                            retval = EFAULT;
+                        break;
+                    }
+                    
+                    /* set ramp setting */
+                    if (false == p_scux_info_ch->first_ramp_flag)
+                    {
+                        while((DVUSR_DVU0_VRSTS_VOL_FIX != (p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUSR_DVU0_0 & DVUSR_DVU0_VRSTS_MASK)) &&
+                              (SCUX_RAMP_WAIT_MAX > ramp_wait_cnt))
+                        {
+                            ramp_wait_cnt++;
+                        }
+                        if (SCUX_RAMP_WAIT_MAX <= ramp_wait_cnt)
+                        {
+                            retval = EFAULT;
+                        }
+                        else
+                        {
+                            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+                            SCUX_SetRampVolRegister(p_scux_info_ch);
+                            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+                            p_scux_info_ch->first_ramp_flag = true;
+                        }
+                    }
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_DirectWriteStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyReadStart
+* @brief         Start read request(mem -> mem).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_read_aio:Read request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_CopyReadStart(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_read_aio)
+{
+    int_t    retval;
+    int_t    dma_retval;
+    dma_trans_data_t dma_address_param;
+    uint32_t         dma_dst_addr;
+    
+    if ((NULL == p_scux_info_ch) || (NULL == p_read_aio))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        retval = R_DMA_Setup(p_scux_info_ch->dma_rx_ch, &p_scux_info_ch->dma_rx_setup, NULL);
+                    
+        if (ESUCCESS != retval)
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            /* set first trans information */
+            p_scux_info_ch->p_rx_aio = p_read_aio;
+            p_scux_info_ch->p_rx_next_aio = NULL;
+            p_scux_info_ch->first_rx_flag = false;
+            
+            /* cast uint8_t pointer from void pointer */
+            dma_dst_addr = (uint32_t)p_read_aio->aio_buf;
+            
+            /* set 1st DMA parameter */
+            dma_address_param.src_addr = (void *)p_scux_info_ch->p_scux_reg->dmatu_n_cim;
+            dma_address_param.dst_addr = (void *)dma_dst_addr;
+            dma_address_param.count = p_read_aio->aio_nbytes;
+            
+            dma_retval = R_DMA_Start(p_scux_info_ch->dma_rx_ch, &dma_address_param, NULL);
+                
+            if (ESUCCESS != dma_retval)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                /* enable interrupt */
+                p_scux_info_ch->dma_rx_current_size = dma_address_param.count;
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = (UEVMR_FFU0_UEVMUF_SET | 
+                                                                       UEVMR_FFU0_UEVMOF_SET | 
+                                                                       UEVMR_FFU0_UEVMOL_SET);
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = DEVCR_FFD0_INIT_VALUE;
+                /* start clock devide on async mode */
+                if (false == p_scux_info_ch->src_cfg.mode_sync)
+                {
+                    if ((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 
+                        (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                        (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async))
+                    {
+                        p_scux_info_ch->futsel_cim_value |= FUTSEL_CIM_DIVEN_SET;
+                        *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+                    }
+                }
+                /* update channel status */
+                
+                switch (p_scux_info_ch->ch_stat)
+                {
+                    case SCUX_CH_UNINIT :
+                        /* fall through */
+                    case SCUX_CH_INIT :
+                        /* fall through */
+                    case SCUX_CH_STOP :
+                        /* fall through */
+                        retval = EBADF;
+                    break;                  
+                    
+                    case SCUX_CH_TRANS_IDLE :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RD;
+                    break;
+
+                    case SCUX_CH_TRANS_RD :
+                        /* do nothing, stats isn't updated */
+                    break;
+
+                    case SCUX_CH_TRANS_WR :
+                        p_scux_info_ch->ch_stat = SCUX_CH_TRANS_RDWR;
+                    break;
+                    
+                    case SCUX_CH_TRANS_RDWR :
+                        /* fall through */
+                    case SCUX_CH_STOP_WAIT :
+                        /* do nothing, stats isn't updated */
+                    break;
+                    
+                    case SCUX_CH_STOP_WAIT_IDLE :
+                        p_scux_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                    break;
+                    
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                        retval = EFAULT;
+                    break;
+                }
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CopyReadStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_FlushWriteStart
+* @brief         Start dummy write for FIFO flush.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch:SCUX channel information.
+* @param[in]     *p_write_aio:Write request information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_FlushWriteStart(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t retval = ESUCCESS;
+    dma_trans_data_t dma_address_param;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (0U != p_scux_info_ch->flush_stop_size)
+        {
+            retval = R_DMA_Setup(p_scux_info_ch->dma_tx_ch, &p_scux_info_ch->dma_tx_setup, NULL);
+                    
+            if (ESUCCESS != retval)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                /* trans dummy data size is FIFO size unit */
+                if (p_scux_info_ch->flush_stop_size >= p_scux_info_ch->fifo_size)
+                {
+                    dma_address_param.count = p_scux_info_ch->fifo_size;
+                    p_scux_info_ch->flush_stop_size -= p_scux_info_ch->fifo_size;
+                }
+                else
+                {
+                    /* last data is fraction of FIFO size */
+                    dma_address_param.count = p_scux_info_ch->flush_stop_size;
+                    p_scux_info_ch->flush_stop_size = 0;
+                }
+                      
+                dma_address_param.src_addr = (void *)(p_scux_info_ch->p_tx_dummy_data);
+                dma_address_param.dst_addr = (void *)p_scux_info_ch->p_scux_reg->dmatd_n_cim;
+                                            
+                retval = R_DMA_Start(p_scux_info_ch->dma_tx_ch, &dma_address_param, NULL);
+                if (ESUCCESS != retval)
+                {
+                    retval = EFAULT;
+                }
+                else
+                {
+                    p_scux_info_ch->dma_tx_current_size = dma_address_param.count;
+                        
+                    p_scux_info_ch->tx_dummy_run_flag = true;
+                     
+                    if ((SCUX_CH_TRANS_RD == p_scux_info_ch->ch_stat) || (SCUX_CH_TRANS_IDLE == p_scux_info_ch->ch_stat))
+                    {
+                        /* restart write operation when write is stopped */
+                        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = (DEVMR_FFD0_DEVMUF_SET | 
+                                                                               DEVMR_FFD0_DEVMOF_SET | 
+                                                                               DEVMR_FFD0_DEVMOL_SET | 
+                                                                               DEVMR_FFD0_DEVMIUF_SET);
+                        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 
+                        = DEVCR_FFD0_INIT_VALUE;
+                        /* start clock devide on async mode or SSIF direct route setting */
+                        if (false == p_scux_info_ch->src_cfg.mode_sync)  
+                        {
+                            if((SCUX_CLK_SSIF0_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF1_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF2_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF3_WS != p_scux_info_ch->src_cfg.input_clk_async) && 
+                               (SCUX_CLK_SSIF4_WS != p_scux_info_ch->src_cfg.input_clk_async) &&
+                               (SCUX_CLK_SSIF5_WS != p_scux_info_ch->src_cfg.input_clk_async)) 
+                            {
+                                *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) |= FDTSEL_CIM_DIVEN_SET;
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_FlushWriteStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyCancelSpecific
+* @brief         Cancel specific request(mem->mem).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     *p_cancel_aio : Cancel request information.
+* @retval        ESUCCESS : Operation successful.
+*                EBUSY  : Cancel requst is on going.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O0
+#endif
+#endif /* end mbed */
+int_t SCUX_CopyCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio)
+{
+    int_t    retval = ESUCCESS;
+    int_t    dummy_retval;
+    int_t    was_masked;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif    
+    
+        /* check cancel request */
+        if ((p_scux_info_ch->p_tx_aio == p_cancel_aio) || (p_scux_info_ch->p_rx_aio == p_cancel_aio))
+        {
+            retval = EBUSY;
+        }
+        else
+        {
+            /* request don't going */
+            dummy_retval = ahf_cancel(&p_scux_info_ch->tx_que, p_cancel_aio);
+            if (ESUCCESS != dummy_retval)
+            {
+                /* NON_NOTICE_ASSERT: queue cancel error */
+            }
+            dummy_retval = ahf_cancel(&p_scux_info_ch->rx_que, p_cancel_aio);
+            if (ESUCCESS != dummy_retval)
+            {
+                /* NON_NOTICE_ASSERT: queue cancel error */
+            }
+        }
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+    
+    return retval;
+}
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O3
+#endif
+#endif /* end mbed */
+
+/******************************************************************************
+End of function SCUX_CopyCancelSpecific
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DirectCancelSpecific
+* @brief         Cancel specific request(SSIF direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @param[in]     *p_cancel_aio : Cancel request information.
+* @retval        ESUCCESS : Operation successful.
+*                EBUSY  : Cancel requst is on going.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_DirectCancelSpecific(scux_info_ch_t * const p_scux_info_ch, AIOCB * const p_cancel_aio)
+{
+    int_t    retval = ESUCCESS;
+    int_t    dummy_retval;
+    int_t    was_masked;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif    
+    
+        /* check cancel request */
+        if ((p_scux_info_ch->p_tx_aio == p_cancel_aio) || (p_scux_info_ch->p_tx_next_aio == p_cancel_aio))
+        {
+            retval = EBUSY;
+        }
+        else
+        {
+            /* request don't going */
+            dummy_retval = ahf_cancel(&p_scux_info_ch->tx_que, p_cancel_aio);
+            if (ESUCCESS != dummy_retval)
+            {
+                /* NON_NOTICE_ASSERT: queue cancel error */
+            }
+        }
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_DirectCancelSpecific
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_CopyCancelAll
+* @brief         Cancel all request(mem->mem).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O0
+#endif
+#endif /* end mbed */
+int_t SCUX_CopyCancelAll(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    retval = ESUCCESS;
+    int_t    dma_ercd;
+    int_t    dma_retval;
+    int_t    was_masked;
+    uint32_t tx_remain_size = 0;
+    uint32_t rx_remain_size = 0;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+        if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size;
+            p_scux_info_ch->dma_tx_current_size = 0;
+        }
+             
+        dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd);
+        /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+        if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            p_scux_info_ch->rx_fifo_total_size += p_scux_info_ch->dma_rx_current_size;
+            p_scux_info_ch->dma_rx_current_size = 0;
+        }
+                        
+        if (ESUCCESS == retval)
+        {
+            /* return write request */
+            if (NULL !=  p_scux_info_ch->p_tx_aio)
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ECANCELED;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
+            }
+            
+            /* return read request */
+            if (NULL != p_scux_info_ch->p_rx_aio)
+            {
+                p_scux_info_ch->p_rx_aio->aio_return = ECANCELED;
+                ahf_complete(&p_scux_info_ch->rx_que, p_scux_info_ch->p_rx_aio);
+            }   
+                               
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+            ahf_cancelall(&p_scux_info_ch->rx_que);
+            
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_rx_aio = NULL;
+        
+            SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, rx_remain_size);
+            p_scux_info_ch->cancel_operate_flag = true;
+            
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                SCUX_SyncStopHw(p_scux_info_ch);
+                SCUX_InitHw(p_scux_info_ch);
+                SCUX_SetupSrc(p_scux_info_ch);
+                SCUX_SyncStartHw(p_scux_info_ch);
+            }
+            else
+            {
+                SCUX_AsyncStopHw(p_scux_info_ch);
+                SCUX_InitHw(p_scux_info_ch);
+                SCUX_SetupSrc(p_scux_info_ch);
+                SCUX_AsyncStartHw(p_scux_info_ch);
+            }
+            
+            p_scux_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+            p_scux_info_ch->p_flush_callback = NULL;
+            
+            p_scux_info_ch->tx_fifo_total_size = 0;
+            p_scux_info_ch->rx_fifo_total_size = 0;            
+            
+            p_scux_info_ch->cancel_operate_flag = false;
+        }
+
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_CopyCancelAll
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DirectCancelAll
+* @brief         Cancel all request(SSIF direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_DirectCancelAll(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    retval = ESUCCESS;
+    int_t    dma_ercd;
+    int_t    dma_retval;
+    int_t    was_masked;
+    uint32_t tx_remain_size = 0;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        dma_retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+        if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+        {
+            retval = EFAULT;
+        }
+        else
+        {
+            p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size;
+            p_scux_info_ch->dma_tx_current_size = 0;
+            
+            if (NULL != p_scux_info_ch->p_tx_aio)
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ECANCELED;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
+            }
+            if (NULL != p_scux_info_ch->p_tx_next_aio)
+            {
+                p_scux_info_ch->p_tx_next_aio->aio_return = ECANCELED;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_next_aio);
+            }
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+                
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+            
+            SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, 0);
+            
+            p_scux_info_ch->cancel_operate_flag = true;
+            p_scux_info_ch->restart_ramp_flag = true;
+            
+            SCUX_AsyncStopHw(p_scux_info_ch);
+            
+            SCUX_InitHw(p_scux_info_ch);
+            SCUX_SetupSsif(p_scux_info_ch);
+            SCUX_SetupSrc(p_scux_info_ch);
+            SCUX_SetupDvu(p_scux_info_ch);
+            SCUX_AsyncStartHw(p_scux_info_ch);
+            
+            p_scux_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+            p_scux_info_ch->p_flush_callback = NULL;
+            
+            p_scux_info_ch->tx_fifo_total_size = 0;
+            p_scux_info_ch->rx_fifo_total_size = 0;
+            p_scux_info_ch->dvu_mute_stat = 0;
+            p_scux_info_ch->first_ramp_flag = false;
+            p_scux_info_ch->cancel_operate_flag = false;            
+        }   
+
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+    
+    return retval;
+}
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O3
+#endif
+#endif /* end mbed */
+
+/******************************************************************************
+End of function SCUX_DirectCancelAll
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_AdjustAccessFifo
+* @brief         Fifo is Cleared.
+*
+*                Description:<br>
+*                
+* @param[in]     p_scux_info_ch:channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_AdjustAccessFifo(scux_info_ch_t * const p_scux_info_ch, const uint32_t tx_remain_size, const uint32_t rx_remain_size)
+{
+    uint32_t dummy_data_size;
+    uint32_t request_data_size;
+    uint32_t access_size = SCUX_DMA_UNIT_SIZE16;
+    uint32_t dummy_read_data;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        *(p_scux_info_ch->p_scux_reg->dmacr_cim) &= ~(DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
+        switch (p_scux_info_ch->src_cfg.word_len)
+        {
+            case SCUX_DATA_LEN_24 :
+                access_size = SCUX_DMA_UNIT_SIZE24;
+            break;
+            
+            case SCUX_DATA_LEN_16 :
+                /* fall through */
+            case SCUX_DATA_LEN_16_TO_24 :
+                access_size = SCUX_DMA_UNIT_SIZE16;
+            break;
+            
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                /* NOTREACHED on At the time of a normal performance */
+            break;
+        }
+
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET | 
+                                                                 DEVMR_FFD0_DEVMOF_SET | 
+                                                                 DEVMR_FFD0_DEVMOL_SET | 
+                                                                 DEVMR_FFD0_DEVMIUF_SET);
+        /* access count is adjusted for tx DMA remain size */
+        if (0U != tx_remain_size)
+        {
+            for (dummy_data_size = 0; dummy_data_size < tx_remain_size; dummy_data_size += access_size )
+            {
+                *(p_scux_info_ch->p_scux_reg->dmatd_n_cim) = 0;
+            }
+        }    
+        
+        /* access count is adjusted for tx total remain size */
+        if (0U != (p_scux_info_ch->tx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)))
+        {
+            request_data_size = (p_scux_info_ch->fifo_size - (p_scux_info_ch->tx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)));
+            for (dummy_data_size = 0; dummy_data_size < request_data_size; dummy_data_size += access_size )
+            {
+                *(p_scux_info_ch->p_scux_reg->dmatd_n_cim) = 0;
+            }
+        }
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = 0;
+        *(p_scux_info_ch->p_scux_reg->dmacr_cim) |= (DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
+    
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            *(p_scux_info_ch->p_scux_reg->dmacr_cim) &= ~(DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
+            switch (p_scux_info_ch->src_cfg.word_len)
+            {
+                case SCUX_DATA_LEN_16 :
+                    access_size = SCUX_DMA_UNIT_SIZE16;
+                break;
+                
+                case SCUX_DATA_LEN_24 :
+                    /* fall through */
+                case SCUX_DATA_LEN_16_TO_24 :
+                    access_size = SCUX_DMA_UNIT_SIZE24;
+                break;
+                
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }            
+        
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET | 
+                                                                     UEVMR_FFU0_UEVMOF_SET | 
+                                                                     UEVMR_FFU0_UEVMOL_SET);
+            /* access count is adjusted for rx DMA remain size */
+            if (0U != rx_remain_size)
+            {
+                for (dummy_data_size = 0; dummy_data_size < rx_remain_size; dummy_data_size += access_size )
+                {
+                    dummy_read_data = *(p_scux_info_ch->p_scux_reg->dmatu_n_cim);
+                    UNUSED_ARG(dummy_read_data);
+                }
+            }
+            
+            /* access count is adjusted for rx total remain size */
+            if (0U != (p_scux_info_ch->rx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)))
+            {
+                request_data_size = (p_scux_info_ch->fifo_size - (p_scux_info_ch->rx_fifo_total_size & (p_scux_info_ch->fifo_size - 1U)));
+                
+                for (dummy_data_size = 0; dummy_data_size < request_data_size; dummy_data_size += access_size )
+                {
+                    dummy_read_data = *(p_scux_info_ch->p_scux_reg->dmatu_n_cim);
+                    UNUSED_ARG(dummy_read_data);
+                }
+            }
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = 0;
+            *(p_scux_info_ch->p_scux_reg->dmacr_cim) |= (DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_AdjustAccessFifo
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupSrc
+* @brief         SRC HW setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_SetupSrc(scux_info_ch_t * const p_scux_info_ch)
+{
+    uint32_t process_delay = 0;
+    uint32_t data_size;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (false != p_scux_info_ch->src_cfg.src_enable)
+        {
+            /* check delay mode and enabled audio channel */
+            switch (p_scux_info_ch->src_cfg.delay_mode)
+            {
+                case SCUX_DELAY_NORMAL :
+                    switch (p_scux_info_ch->src_cfg.use_ch)
+                    {
+                        case SCUX_USE_CH_1 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH1;
+                        break;
+        
+                        case SCUX_USE_CH_2 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH2;
+                        break;
+        
+                        case SCUX_USE_CH_4 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH4;
+                        break;
+                        
+                        case SCUX_USE_CH_6 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH6;
+                        break;
+        
+                        case SCUX_USE_CH_8 :
+                            process_delay = SCUX_PROCESS_DELAY_NORMAL_CH8;
+                        break;
+                        
+                        default :
+                            /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                            /* <-IPA R3.5.2 */
+                            /* NOTREACHED on At the time of a normal performance */
+                        break;  
+                    }                                          
+                break;
+                            
+                case SCUX_DELAY_LOW_DELAY1 :
+                    process_delay = SCUX_PROCESS_DELAY_1_CH1_2;
+                break;
+        
+                case SCUX_DELAY_LOW_DELAY2 :
+                    process_delay = SCUX_PROCESS_DELAY_2_CH1_2;
+                break;                
+                            
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }        
+        
+            /* set dummy data size for flush */
+            if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+            {
+                data_size = sizeof(uint16_t);
+            }
+            else
+            {
+                data_size = sizeof(uint32_t);
+            }
+        
+            process_delay = (process_delay * ((p_scux_info_ch->output_rate * SCUX_RATE_INT_CONV_VALUE) / p_scux_info_ch->input_rate));
+            if (0U != (process_delay % SCUX_RATE_INT_CONV_VALUE))
+            {
+                /* A redundant value is added that delay size below a decimal point may come out */
+                process_delay = ((process_delay / SCUX_RATE_INT_CONV_VALUE) + SCUX_ADJUST_REST_VALUE);
+            }
+            else
+            {
+                process_delay = (process_delay / SCUX_RATE_INT_CONV_VALUE);
+            }
+            
+            p_scux_info_ch->flush_stop_size = (p_scux_info_ch->src_cfg.use_ch * (data_size * (process_delay + SCUX_LOGIC_DELAY_BYPASS_OFF)));    
+            if (0U != (p_scux_info_ch->flush_stop_size % SCUX_EVEN_VALUE_DIV))
+            {
+                /* set even value */
+                p_scux_info_ch->flush_stop_size++;
+            }
+        }
+        else
+        {
+            /* set dummy data size for flush */
+            if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+            {
+                data_size = sizeof(uint16_t);
+            }
+            else
+            {
+                data_size = sizeof(uint32_t);
+            }
+            
+            p_scux_info_ch->flush_stop_size = (p_scux_info_ch->src_cfg.use_ch * (data_size * SCUX_LOGIC_DELAY_BYPASS_ON));
+            if (0U != (p_scux_info_ch->flush_stop_size % SCUX_EVEN_VALUE_DIV))
+            {
+                /* set even value */
+                p_scux_info_ch->flush_stop_size++;
+            }
+        }
+            
+        p_scux_info_ch->tx_dummy_run_flag = false;
+        
+        /* set FFD & FFU parameter depend on the combination of route and sync mode */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_SYNC;
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_PASS_SET_SYNC;
+                p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_SYNC;
+                p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_SYNC;
+            }
+            else
+            {
+                p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_ASYNC;
+                p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_PASS_SET_ASYNC;
+                p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_ASYNC;
+                p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_ASYNC;
+            }
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_PASS_SET_ASYNC;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = 0;
+            p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC_PASS_SEL_SET_ASYNC;
+            p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC_PASS_SEL_SET_DIRECT;
+        }
+            
+        /* set route CIM register for SSIF channel and MIX */
+        switch (p_scux_info_ch->route_set)
+        {
+            case SCUX_ROUTE_SRC0_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC1_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_MEM :
+                /* do nothing, when mem to mem route is setting */
+            break;
+                        
+            case SCUX_ROUTE_SRC0_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_SRC0_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC0_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_SRC0_SET | SSIRSEL_CIM_SOSEL1_SRC0_SET | SSIRSEL_CIM_SOSEL2_SRC0_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC0_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_SRC0_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC0_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_SRC0_SET | SSIRSEL_CIM_SOSEL4_SRC0_SET | SSIRSEL_CIM_SOSEL5_SRC0_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC1_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_SRC1_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC1_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_SRC1_SET | SSIRSEL_CIM_SOSEL1_SRC1_SET | SSIRSEL_CIM_SOSEL2_SRC1_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC1_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_SRC1_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC1_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_SRC1_SET | SSIRSEL_CIM_SOSEL4_SRC1_SET | SSIRSEL_CIM_SOSEL5_SRC1_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC2_SSIF1 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL1_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL1_SRC2_SET;
+            break;
+        
+            case SCUX_ROUTE_SRC2_SSIF4 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL4_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL4_SRC2_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC3_SSIF2 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL2_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL2_SRC3_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC3_SSIF5 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL5_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL5_SRC3_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;            
+            
+            case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;            
+            
+            case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;            
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;            
+            
+            case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL0_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL0_MIX_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL0_MASK | SSIRSEL_CIM_SOSEL1_MASK | SSIRSEL_CIM_SOSEL2_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL0_MIX_SET | SSIRSEL_CIM_SOSEL1_MIX_SET | SSIRSEL_CIM_SOSEL2_MIX_SET);
+            break;            
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~SSIRSEL_CIM_SOSEL3_MASK;
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= SSIRSEL_CIM_SOSEL3_MIX_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) &= ~(SSIRSEL_CIM_SOSEL3_MASK | SSIRSEL_CIM_SOSEL4_MASK | SSIRSEL_CIM_SOSEL5_MASK);
+                *(p_scux_info_ch->p_scux_reg->ssirsel_cim) |= (SSIRSEL_CIM_SOSEL3_MIX_SET | SSIRSEL_CIM_SOSEL4_MIX_SET | SSIRSEL_CIM_SOSEL5_MIX_SET);
+            break;
+            
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                 /* NOTREACHED on At the time of a normal performance */
+            break;
+        }
+            
+        SCUX_SetupDataPosition(p_scux_info_ch);
+        
+        /* set route SSICTRL register for each route */
+        if (false == p_scux_info_ch->src_cfg.mode_sync)
+        {
+            switch (p_scux_info_ch->route_set)
+            {
+                case SCUX_ROUTE_SRC0_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MEM :
+                    /* do nothing, when mem to mem route is setting */
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC0_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC1_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC1_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC2_SSIF1 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI1TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC2_SSIF4 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI4TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                
+                case SCUX_ROUTE_SRC3_SSIF2 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI2TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+
+                case SCUX_ROUTE_SRC3_SSIF5 :
+                    /* fall through */
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI5TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;                
+                
+                case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                
+                case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;                
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                
+                case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+    
+                case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                
+                case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                
+                case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;          
+                
+                case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                break;
+                        
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+        }
+        
+        SCUX_SetupSrcClk(p_scux_info_ch);
+        
+        /* set pin mode for each route */
+        switch (p_scux_info_ch->route_set)
+        {
+            case SCUX_ROUTE_SRC0_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC1_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_MEM :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_SSIF1 :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_SSIF4 :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_SSIF2 :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_SSIF5 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                /* fall through */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI1PMD_MASK | SSIPMD_CIM_SSI2PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                    
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI1PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI2PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;    
+                }
+            break;
+
+            case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI012EN_SET | SSIPMD_CIM_SSI345EN_SET);
+            break;
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~SSIPMD_CIM_SSI012EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= SSIPMD_CIM_SSI345EN_SET;
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI4PMD_MASK | SSIPMD_CIM_SSI5PMD_MASK);
+                if (false != p_scux_info_ch->p_ssif_info1->ssif_cfg.mode_master)
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_MASTER_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_MASTER_SLAVE;                                                                  
+                }
+                else
+                {
+                    *(p_scux_info_ch->p_scux_reg->ssipmd_cim) |= ((SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI4PMD_SHIFT) |
+                                                                  (SCUX_PIN_MODE_SLAVE_SLAVE << SSIPMD_CIM_SSI5PMD_SHIFT));
+                    p_scux_info_ch->p_ssif_info2->pin_mode_backup = p_scux_info_ch->p_ssif_info2->pin_mode;
+                    p_scux_info_ch->p_ssif_info2->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;
+                    p_scux_info_ch->p_ssif_info3->pin_mode_backup = p_scux_info_ch->p_ssif_info3->pin_mode;
+                    p_scux_info_ch->p_ssif_info3->pin_mode = SCUX_PIN_MODE_SLAVE_SLAVE;                                                                  
+                }
+            break;
+            
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                /* NOTREACHED on At the time of a normal performance */
+            break;
+        }
+            
+        SCUX_SetupFifo(p_scux_info_ch);
+        SCUX_SetupSrcFunction(p_scux_info_ch);
+    }
+        
+    return;
+}
+    
+/******************************************************************************
+End of function SCUX_SetupSrc
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupDataPosition
+* @brief         Audio data position setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupDataPosition(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+    uint32_t audio_place = 0;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {    
+        /* set data posion for SRC */
+        for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+        {
+            audio_place |= (((uint32_t)p_scux_info_ch->src_cfg.select_in_data_ch[audio_ch] & SRCRSEL_CIM_PLACE_N_MASK) << ((uint32_t)audio_ch * SRCRSEL_CIM_PLACE_N_SHIFT));
+        }
+        *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = audio_place;
+        
+        /* set data position for MIX */
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            if (0U == p_info_drv->shared_info.mix_run_ch)
+            {
+                audio_place = 0;
+                for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+                {
+                    audio_place |= (((uint32_t)p_info_drv->shared_info.select_out_data_ch[audio_ch] & MIXRSEL_CIM_PLACE_N_MASK) << ((uint32_t)audio_ch * MIXRSEL_CIM_PLACE_N_SHIFT));
+                }
+                *(p_scux_info_ch->p_scux_reg->mixrsel_cim) = audio_place;
+            }
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDataPosition
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupSrcClk
+* @brief         SRC clock setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupSrcClk(scux_info_ch_t * const p_scux_info_ch)
+{
+    uint32_t fdtsel_value = 0;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* set input timing clock */
+        if (false == p_scux_info_ch->src_cfg.mode_sync)
+        {
+            /* get value of register setting */
+            switch (p_scux_info_ch->src_cfg.input_clk_async)
+            {
+    
+                case SCUX_CLK_AUDIO_CLK :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                   FDTSEL_CIM_SCKSEL_AUDIO_CLK_SET);
+                break;              
+                
+                case SCUX_CLK_AUDIO_X1 :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                   FDTSEL_CIM_SCKSEL_AUDIO_X1_SET);
+                break;
+                    
+                case SCUX_CLK_MLB_CLK :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                   FDTSEL_CIM_SCKSEL_MLB_CLK_SET);
+                break;
+    
+                case SCUX_CLK_USB_X1 :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                   FDTSEL_CIM_SCKSEL_USB_X1_SET);
+                break;
+    
+                case SCUX_CLK_CLKP1_2 :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                   FDTSEL_CIM_SCKSEL_CLKP1_2_SET);
+                break;
+    
+                case SCUX_CLK_MTU_TIOC3A :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                    FDTSEL_CIM_SCKSEL_MTUSEL2_SET | 
+                                    FDTSEL_CIM_MTUSEL_SET_TIOC3A);
+                break;
+                
+                case SCUX_CLK_MTU_TIOC4A :
+                    fdtsel_value = (((p_scux_info_ch->src_cfg.input_div_async << FDTSEL_CIM_SCKDIV_SHIFT) & FDTSEL_CIM_SCKDIV_MASK) | 
+                                    FDTSEL_CIM_SCKSEL_MTUSEL2_SET | 
+                                    FDTSEL_CIM_MTUSEL_SET_TIOC4A);
+                break;
+    
+                case SCUX_CLK_SSIF0_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF0_WS_SET;
+                break;
+                    
+                case SCUX_CLK_SSIF1_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF1_WS_SET;
+                break;
+                    
+                case SCUX_CLK_SSIF2_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF2_WS_SET;
+                break;
+                    
+                case SCUX_CLK_SSIF3_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF3_WS_SET;
+                break;
+                    
+                case SCUX_CLK_SSIF4_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF4_WS_SET;
+                break;
+                    
+                case SCUX_CLK_SSIF5_WS :
+                    fdtsel_value = FDTSEL_CIM_SCKSEL_SSIF5_WS_SET;
+                break;
+                
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+            *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) = fdtsel_value;
+        }
+        
+        /* set output timing clock on MIX */
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->futsel_cim_value = (((0 << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                (((uint32_t)p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num | FUTSEL_CIM_SCKSEL_SSIF0_WS_SET) & FUTSEL_CIM_SCKSEL_MASK));
+            *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+        }
+        else if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {   
+            /* set output timing clock on other MIX */
+            if (false == p_scux_info_ch->src_cfg.mode_sync)
+            {
+                switch (p_scux_info_ch->src_cfg.output_clk_async)
+                {
+                    case SCUX_CLK_AUDIO_CLK :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_AUDIO_CLK_SET);
+                    break;
+                    
+                    case SCUX_CLK_AUDIO_X1 :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_AUDIO_X1_SET);
+                    break;
+                        
+                    case SCUX_CLK_MLB_CLK :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_MLB_CLK_SET);
+                    break;
+        
+                    case SCUX_CLK_USB_X1 :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_USB_X1_SET);
+                    break;
+        
+                    case SCUX_CLK_CLKP1_2 :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_CLKP1_2_SET);
+                    break;
+        
+                    case SCUX_CLK_MTU_TIOC3A :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_MTUSEL2_SET | 
+                                                            FUTSEL_CIM_MTUSEL_SET_TIOC3A);
+                    break;
+                    
+                    case SCUX_CLK_MTU_TIOC4A :
+                        p_scux_info_ch->futsel_cim_value = (((p_scux_info_ch->src_cfg.output_div_async << FUTSEL_CIM_SCKDIV_SHIFT) & FUTSEL_CIM_SCKDIV_MASK) | 
+                                                            FUTSEL_CIM_SCKSEL_MTUSEL2_SET | 
+                                                            FUTSEL_CIM_MTUSEL_SET_TIOC4A);
+                    break;
+        
+                    case SCUX_CLK_SSIF0_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF0_WS_SET;
+                    break;
+                        
+                    case SCUX_CLK_SSIF1_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF1_WS_SET;
+                    break;
+                        
+                    case SCUX_CLK_SSIF2_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF2_WS_SET;
+                    break;
+                        
+                    case SCUX_CLK_SSIF3_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF3_WS_SET;
+                    break;
+                        
+                    case SCUX_CLK_SSIF4_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF4_WS_SET;
+                    break;
+                        
+                    case SCUX_CLK_SSIF5_WS :
+                        p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_SCKSEL_SSIF5_WS_SET;
+                    break;
+                    
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+                *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+            }
+        }
+        else
+        {
+            /* do nothing for SSIF route */
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSrcClk
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupFifo
+* @brief         SRC FIFO setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupFifo(scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* set FFD register */
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = p_scux_info_ch->src_cfg.use_ch;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = SCUX_FIFO_REQ_SIZE_128_32;
+    
+        GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
+        
+        /* set FFU register */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = p_scux_info_ch->src_cfg.use_ch;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = SCUX_FIFO_REQ_SIZE_128_32;
+        
+            GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
+        }   
+        
+        p_scux_info_ch->tx_fifo_total_size = 0;
+        p_scux_info_ch->rx_fifo_total_size = 0;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupFifo
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupSrcFunction
+* @brief         SRC function setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupSrcFunction(scux_info_ch_t * const p_scux_info_ch)
+{
+    float32_t ifs_calc_value;
+    uint32_t ifs_value;
+    uint32_t sadir_value;
+    uint32_t srccr_value = 0;
+    uint32_t bfssr_value;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (false == p_scux_info_ch->src_cfg.src_enable)
+        {
+            /* set bypass mode */
+            if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 |= SRCBR_2SRC0_BYPASS_SET;
+            }
+            else
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 |= SRCBR_2SRC0_BYPASS_SET;
+            }
+        }   
+        else
+        {
+            /* calculate sampling rate convert rate parameter */
+            ifs_calc_value = ((float32_t)p_scux_info_ch->input_rate / (float32_t)p_scux_info_ch->output_rate);
+            /* ->IPA R2.4.1 float value is intentionall casted to uint32_t value, because it is resigter value. */
+            ifs_value = (uint32_t)(ifs_calc_value * (float32_t)SCUX_RATE_CONVERT_CALC_VALUE);
+            /* <-IPA R2.4.1 */
+            if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+            {
+                sadir_value = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & SADIR_2SRC0_CHNUM_MASK) | SADIR_2SRC0_OTBL_SET_16BIT);
+            }
+            else
+            {
+                sadir_value = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & SADIR_2SRC0_CHNUM_MASK) | SADIR_2SRC0_OTBL_SET_24BIT);
+            }
+            
+            /* setting of sync mode bit */
+            if (false != p_scux_info_ch->src_cfg.mode_sync)
+            {
+                /* set sync mode */
+                srccr_value |= SRCCR_2SRC0_SRCMD_SET;
+            }
+            else
+            {
+                /* set async mode (bit clear) */
+                srccr_value &= ~SRCCR_2SRC0_SRCMD_SET;
+            }
+            
+            /* setting of buffer for delay mode */
+            if (SCUX_DELAY_NORMAL == p_scux_info_ch->src_cfg.delay_mode)
+            {
+                /* delay normal setting (bit clear) */
+                srccr_value &= ~SRCCR_2SRC0_BUFMD_SET;
+            }
+            else
+            {
+                /* delay setting (bit set) */
+                srccr_value |= SRCCR_2SRC0_BUFMD_SET;
+            }
+            
+            /* setting enable bit for wait mode */
+            if ((0U == p_scux_info_ch->src_cfg.wait_sample) || (false != p_scux_info_ch->cancel_operate_flag))
+            {
+                /* clear wait mode enable bit when wait value is 0 or cancel operatin on going */
+                srccr_value &= ~SRCCR_2SRC0_WATMD_SET;
+            }
+            else
+            {
+                /* set wait mode enable bit when wait value is other than 0 */
+                srccr_value |= SRCCR_2SRC0_WATMD_SET;
+            }
+            
+            /* setting buffer value for delay mode */
+            if (SCUX_DELAY_NORMAL == p_scux_info_ch->src_cfg.delay_mode)
+            {
+                /* set 0 to BFSSR register on delay normal */
+                bfssr_value = 0;
+            }
+            else if (SCUX_DELAY_LOW_DELAY1 == p_scux_info_ch->src_cfg.delay_mode)
+            {
+                /* set delay mode 1 setting to BFSSR register on delay mode1 */
+                bfssr_value = ((BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE1 & BFSSR_2SRC0_BUFDATA_MASK) | 
+                               (BFSSR_2SRC0_BUFIN_SET_DELAY_MODE & BFSSR_2SRC0_BUFIN_MASK));
+            }
+            else
+            {
+                /* set delay mode 2 setting to BFSSR register on delay mode2 */
+                bfssr_value = ((BFSSR_2SRC0_BUFDATA_SET_DELAY_MODE2 & BFSSR_2SRC0_BUFDATA_MASK) | 
+                               (BFSSR_2SRC0_BUFIN_SET_DELAY_MODE & BFSSR_2SRC0_BUFIN_MASK));
+            }
+            
+            /* set register */
+            if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 &= ~SRCBR_2SRC0_BYPASS_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = sadir_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 |= IFSCR_2SRC0_INTIFSEN_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = ifs_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = ((ifs_value * (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) 
+                                                                         / SCUX_CALC_MINFS_VALUE);
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_BASE_VALUE | srccr_value);
+                p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = bfssr_value;
+                if (false != p_scux_info_ch->cancel_operate_flag)
+                {
+                    /* set 0 to register compulsorily when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = 0U;
+                }
+                else
+                {
+                    /* set wait value to register when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = (p_scux_info_ch->src_cfg.wait_sample & WATSR_2SRC0_WTIME_MASK);
+                }
+            }
+            else
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 &= ~SRCBR_2SRC0_BYPASS_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = sadir_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 |= IFSCR_2SRC0_INTIFSEN_SET;
+                p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = ifs_value;
+                p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = ((ifs_value * (uint32_t)p_scux_info_ch->src_cfg.min_rate_percentage) 
+                                                                         / SCUX_CALC_MINFS_VALUE);
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_BASE_VALUE | srccr_value);
+                p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = bfssr_value;
+                if (false != p_scux_info_ch->cancel_operate_flag)
+                {
+                    /* set 0 to register compulsorily when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = 0U;
+                }
+                else
+                {
+                    /* set wait value to register when cancel operation on going */
+                    p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = (p_scux_info_ch->src_cfg.wait_sample & WATSR_2SRC0_WTIME_MASK);
+                }
+            }
+        }
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSrcFunction
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupDvu
+* @brief         DVU module setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SetupDvu(scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & VADIR_DVU0_CHNUM_MASK) | 
+                                                                   VADIR_DVU0_OTBL_SET_16BIT);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = (((uint32_t)p_scux_info_ch->src_cfg.use_ch & VADIR_DVU0_CHNUM_MASK) | 
+                                                                   VADIR_DVU0_OTBL_SET_24BIT);
+        }
+        
+        if (false == p_scux_info_ch->dvu_cfg.dvu_enable)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 |= DVUBR_DVU0_BYPASS_SET;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 &= ~DVUBR_DVU0_BYPASS_SET;
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDvu
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupDvuVolume
+* @brief         DVU volume setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupDvuVolume(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+    uint32_t vrctr_value = 0;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* init DVU module */
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 &= ~DVUIR_DVU0_INIT_SET;
+        if (false != p_scux_info_ch->dvu_cfg.dvu_enable)
+        {
+            /* set digital volume */
+            SCUX_SetDigiVolRegister(p_scux_info_ch);
+            
+            /* dummy setting to volume ramp */
+            for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+            {
+                vrctr_value |= (VRCTR_DVU0_VREN_SET << audio_ch);
+            }
+
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_VRMD_SET;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = vrctr_value;
+        
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = 0;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = 0;  
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = 0;
+        
+            /* set zerocross mute */
+            SCUX_SetZerocrossMuteRegister(p_scux_info_ch);
+            
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+            GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_DVI]);
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDvu
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupMix
+* @brief         MIX module setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_SetupMix(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t scux_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */ 
+        if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
+        {
+            *(p_scux_info_ch->p_scux_reg->madir_mix0_0) = ((uint32_t)p_scux_info_ch->src_cfg.use_ch & MADIR_MIX0_CHNUM_MASK);
+            *(p_scux_info_ch->p_scux_reg->mixir_mix0_0) &= ~MIXIR_MIX0_INIT_SET;
+        }    
+        
+        for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++)
+        {
+            /* register set on the channel itself which sets up or channel which has already MIX operated */
+            if ((scux_ch == p_scux_info_ch->channel) ||
+                (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch))))
+            {
+                SCUX_SetMixVolRegister(scux_ch);
+            }
+        }
+        
+        /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */ 
+        if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
+        {
+            *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
+            
+            if (false != p_info_drv->shared_info.mixmode_ramp)
+            {
+                /* set ramp mode */
+                *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) |= MIXMR_MIX0_MIXMODE_SET;
+                *(p_scux_info_ch->p_scux_reg->mvpdr_mix0_0) = (uint32_t)((((uint32_t)p_info_drv->shared_info.up_period << MVPDR_MIX0_MXPDUP_SHIFT) & MVPDR_MIX0_MXPDUP_MASK) | 
+                                                              (((uint32_t)p_info_drv->shared_info.down_period << MVPDR_MIX0_MXPDDW_SHIFT) & MVPDR_MIX0_MXPDDW_MASK));
+            }
+            else
+            {
+                /* set step mode */
+                *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) &= ~MIXMR_MIX0_MIXMODE_SET;
+            }
+            
+            *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) |= MDBER_MIX0_MIXDBEN_SET;
+        }
+        /* set bit SCUX channel which useing MIX */
+        p_info_drv->shared_info.mix_run_ch |= (1U << p_scux_info_ch->channel);
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupMix
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SetupSsif
+* @brief         SSIF module setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SetupSsif(const scux_info_ch_t * const p_scux_info_ch)
+{
+    scux_ssif_info_t *p_set_ssif;
+    volatile uint8_t dummy_buf;
+    uint32_t ssif_arrange_num;
+    uint32_t ssicr_value = 0;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    int_t    was_masked;
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {    
+        for (ssif_arrange_num = 0; ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT; ssif_arrange_num++)
+        {
+            switch (ssif_arrange_num)
+            {
+                case SCUX_SSIF_CH_ARRANGEMENT1:
+                    p_set_ssif = p_scux_info_ch->p_ssif_info1;
+                break;
+                
+                case SCUX_SSIF_CH_ARRANGEMENT2:
+                    p_set_ssif = p_scux_info_ch->p_ssif_info2;
+                break;
+                
+                case SCUX_SSIF_CH_ARRANGEMENT3:
+                    p_set_ssif = p_scux_info_ch->p_ssif_info3;
+                break;
+                
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+            
+            /* check wherher SSIF pointer 1, 2, 3 is NULL */
+            if (NULL != p_set_ssif)
+            {
+                /* check SSIF is used on other MIX SCUX channel */
+                if (0U == ((uint32_t)p_set_ssif->scux_channel & ~(1U << p_scux_info_ch->channel)))
+                {
+                    if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch |= (1U << p_set_ssif->ssif_cfg.ssif_ch_num);
+                    }
+                    
+#if defined (__ICCARM__)
+                    was_masked = __disable_irq_iar();
+#else
+                    was_masked = __disable_irq();
+#endif
+
+                    /* input clock */
+                    CPGSTBCR11 &= (uint8_t)~((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    dummy_buf = CPGSTBCR11;
+
+                    /* SSIF rest */
+                    CPGSWRSTCR1 |= (uint8_t)gb_cpg_scux_ssif_swrst_bit[p_set_ssif->ssif_cfg.ssif_ch_num];
+                    dummy_buf = CPGSWRSTCR1;
+                    
+                    CPGSWRSTCR1 &= (uint8_t)~((uint8_t)gb_cpg_scux_ssif_swrst_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    dummy_buf = CPGSWRSTCR1;
+                    
+                    if (0 == was_masked)
+                    {
+                        __enable_irq();
+                    }
+
+                    SCUX_SetupSsifGpio(p_set_ssif->ssif_cfg.ssif_ch_num);
+                    
+                    /* if mode is master mode, WS continue mode is enabled */
+                    if (false != p_set_ssif->ssif_cfg.mode_master)
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR |= SCUX_SSITDMR_CONT_SET;
+                    }
+                    else
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR &= ~SCUX_SSITDMR_CONT_SET;
+                    }
+                    
+                    /* TDM mode is set according to use_tdm */
+                    if (false != p_set_ssif->ssif_cfg.use_tdm)
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR |= SCUX_SSITDMR_TDM_SET;
+                    }
+                    else
+                    {
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR &= ~SCUX_SSITDMR_TDM_SET;
+                    }
+                    
+                    /* over sample clock is set according to select_audio_clk */
+                    /* if select_audio_clk is 0, set AUDIO_X1 */
+                    /* if select_audio_clk is 0, set AUDIO_CLK */
+                    if (false != p_set_ssif->ssif_cfg.select_audio_clk)
+                    {
+                        ssicr_value |= SCUX_SSICR_CKS_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_CKS_SET;
+                    }
+                    
+                    if (NULL == p_scux_info_ch->p_ssif_info2)
+                    {
+                        /* in case single channel, SSIF channel is set as use_ch kinds */
+                        switch (p_scux_info_ch->src_cfg.use_ch)
+                        {
+                            case SCUX_USE_CH_1:
+                                /* NOTREACHED on At the time of a normal performance */
+                            break;                          
+                            
+                            case SCUX_USE_CH_2:
+                                /* if TDM mode is used on audio 2ch , error occured in SCUX_CheckSrcParam */
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_1CH;
+                            break;
+                            
+                            case SCUX_USE_CH_4:
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_2CH;
+                            break;
+                                            
+                            case SCUX_USE_CH_6:
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_3CH;
+                            break;
+                            
+                            case SCUX_USE_CH_8:
+                                ssicr_value |= SCUX_SSICR_CHNL_SET_4CH;
+                            break;
+                            
+                            default :
+                                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                                /* <-IPA R3.5.2 */
+                                /* NOTREACHED on At the time of a normal performance */
+                            break;
+                        }
+                    }
+                    else
+                    {
+                        /* in case multi channel, SSIF channel is set 1ch compulsorily */
+                        ssicr_value |= SCUX_SSICR_CHNL_SET_1CH;
+                    }
+                    
+                    /* set data word */
+                    if (SCUX_DATA_LEN_16 == p_scux_info_ch->src_cfg.word_len)
+                    {
+                        ssicr_value |= SCUX_SSICR_DWL_16BIT_SET;
+                    }
+                    else
+                    {
+                        ssicr_value |= SCUX_SSICR_DWL_24BIT_SET;
+                    }
+                    
+                    ssicr_value |= ((uint32_t)p_set_ssif->ssif_cfg.system_word << SCUX_SSICR_SWL_SHIFT);
+                            
+                    
+                    if (SCUX_PIN_MODE_INDEPEND == p_set_ssif->pin_mode)
+                    {
+                        /* in case pin synchronization is slave, SSIF mode is set mode following mode_master */
+                        if (false != p_set_ssif->ssif_cfg.mode_master)
+                        {
+                            ssicr_value |= (SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
+                        }
+                        else
+                        {
+                            ssicr_value &= ~(SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
+                        }
+                    }
+                    else
+                    {
+                        /* in case pin synchronization is slave, SSIF mode is set slave mode compulsorily */
+                        ssicr_value &= ~(SCUX_SSICR_SCKD_SET | SCUX_SSICR_SWSD_SET);
+                    }
+                    
+                    /* set serial bit clock polarity */
+                    if (false != p_set_ssif->ssif_cfg.sck_polarity_rise)
+                    {
+                        ssicr_value |= SCUX_SSICR_SCKP_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SCKP_SET;
+                    }
+                    
+                    /* set WS signal polarity */
+                    if (false != p_set_ssif->ssif_cfg.ws_polarity_high)
+                    {
+                        ssicr_value |= SCUX_SSICR_SWSP_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SWSP_SET;
+                    }
+                    
+                    /* set serial padding polarity */
+                    if (false != p_set_ssif->ssif_cfg.padding_high)
+                    {
+                        ssicr_value |= SCUX_SSICR_SPDP_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SPDP_SET;
+                    }
+                
+                    /* set serial data align polarity */
+                    if (false != p_set_ssif->ssif_cfg.serial_data_align)
+                    {
+                        ssicr_value &= ~SCUX_SSICR_SDTA_SET;
+                    }
+                    else
+                    {
+                        ssicr_value |= SCUX_SSICR_SDTA_SET;
+                    }
+                    
+                    /* set WS delay setting */
+                    if (false == p_set_ssif->ssif_cfg.ws_delay)
+                    {
+                        ssicr_value |= SCUX_SSICR_DEL_SET;
+                    }
+                    else
+                    {
+                        ssicr_value &= ~SCUX_SSICR_DEL_SET;
+                    }
+                
+                    /* set SSIF devide rate */
+                    ssicr_value |= ((uint32_t)p_set_ssif->clk_div << SCUX_SSICR_CKDV_SHIFT);
+                    
+                    p_set_ssif->p_scux_ssif_reg->SSICR = ssicr_value;
+                
+                    /* set noise cancel setting */
+                    if ((false == p_set_ssif->ssif_cfg.mode_master) && (false != p_set_ssif->ssif_cfg.use_noise_cancel))
+                    {
+                        GPIO.SNCR |= (1U << gb_cpg_scux_ssif_sncr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    }
+                    else
+                    {
+                        GPIO.SNCR &= ~(1U << gb_cpg_scux_ssif_sncr_bit[p_set_ssif->ssif_cfg.ssif_ch_num]);
+                    }
+                }
+            }
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetupSsif
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetupDma
+* @brief         DMA setup.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+int_t SCUX_SetupDma(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    retval = ESUCCESS;
+    AIOCB    *dma_aio;
+    uint32_t dmacr_cim_value = 0;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        dma_aio = &gb_scux_write_dma_aio[p_scux_info_ch->channel];
+        /* dummy data write start */
+        dma_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+        dma_aio->aio_sigevent.sigev_value.sival_int = p_scux_info_ch->channel;
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_DirectTxCallBack;
+        }
+        else
+        {
+            dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_CopyTxCallBack;
+        }
+        p_scux_info_ch->dma_tx_setup.resource = p_scux_info_ch->dma_resource_tx;
+        p_scux_info_ch->dma_tx_setup.direction = DMA_REQ_DES;
+        
+        switch (p_scux_info_ch->src_cfg.word_len)
+        {
+            case SCUX_DATA_LEN_16 :
+                /* fall through */
+            case SCUX_DATA_LEN_16_TO_24 :
+                p_scux_info_ch->dma_tx_setup.dst_width = DMA_UNIT_2;
+                p_scux_info_ch->dma_tx_setup.src_width = DMA_UNIT_2;
+            break;
+            
+            case SCUX_DATA_LEN_24 :
+                p_scux_info_ch->dma_tx_setup.dst_width = DMA_UNIT_4;
+                p_scux_info_ch->dma_tx_setup.src_width = DMA_UNIT_4;
+            break;
+            
+            default :
+                /* NOTREACHED on At the time of a normal performance */
+            break;
+        }  
+        
+        p_scux_info_ch->dma_tx_setup.dst_cnt = DMA_ADDR_FIX;
+        p_scux_info_ch->dma_tx_setup.src_cnt = DMA_ADDR_INCREMENT;
+        p_scux_info_ch->dma_tx_setup.p_aio = dma_aio;
+        
+        /* get read DMA channel */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->dma_rx_ch = R_DMA_Alloc(DMA_ALLOC_CH, NULL);
+            if (EERROR == p_scux_info_ch->dma_rx_ch)
+            {
+                retval = EMFILE;
+            }
+            else
+            {
+                dma_aio = &gb_scux_read_dma_aio[p_scux_info_ch->channel];
+                dma_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                dma_aio->aio_sigevent.sigev_value.sival_int = p_scux_info_ch->channel;
+                dma_aio->aio_sigevent.sigev_notify_function = &SCUX_DMA_CopyRxCallBack;
+                p_scux_info_ch->dma_rx_setup.resource = p_scux_info_ch->dma_resource_rx;
+                p_scux_info_ch->dma_rx_setup.direction = DMA_REQ_SRC;
+                
+                switch (p_scux_info_ch->src_cfg.word_len)
+                {
+                    case SCUX_DATA_LEN_16 :
+                        p_scux_info_ch->dma_rx_setup.dst_width = DMA_UNIT_2;
+                        p_scux_info_ch->dma_rx_setup.src_width = DMA_UNIT_2;
+                    break;
+                    
+                    case SCUX_DATA_LEN_24 :
+                        /* fall through */
+                    case SCUX_DATA_LEN_16_TO_24 :
+                        p_scux_info_ch->dma_rx_setup.dst_width = DMA_UNIT_4;
+                        p_scux_info_ch->dma_rx_setup.src_width = DMA_UNIT_4;
+                    break;
+                    
+                    default :
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }    
+                
+                p_scux_info_ch->dma_rx_setup.dst_cnt = DMA_ADDR_INCREMENT;
+                p_scux_info_ch->dma_rx_setup.src_cnt = DMA_ADDR_FIX;
+                p_scux_info_ch->dma_rx_setup.p_aio = dma_aio;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            dmacr_cim_value = *(p_scux_info_ch->p_scux_reg->dmacr_cim);
+            /* set write DMA param */
+            dmacr_cim_value |= (DMACR_CIM_DMAMDFFD_N_SET << p_scux_info_ch->channel);
+          
+            /* set read DMA param */
+            if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+            {
+                dmacr_cim_value |= (DMACR_CIM_DMAMDFFU_N_SET << p_scux_info_ch->channel);
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            *(p_scux_info_ch->p_scux_reg->dmacr_cim) = dmacr_cim_value;
+        }
+    }
+        
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_SetupDma
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_InitHw
+* @brief         Initialize HW .
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_InitHw(scux_info_ch_t * const p_scux_info_ch)
+{
+    scux_ssif_info_t *p_set_ssif;
+    uint32_t ssif_arrange_num;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* init FFD register */
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 = FFDIR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FDAIR_FFD0_0 = FDAIR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DRQSR_FFD0_0 = DRQSR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDPR_FFD0_0 = FFDPR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 = FFDBR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 = DEVMR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 = DEVCR_FFD0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 = IPCIR_IPC0_INIT_VALUE;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPSLR_IPC0_0 = IPSLR_IPC0_INIT_VALUE;
+        *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) = FDTSEL_CIM_INIT_VALUE;
+        *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
+                
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SADIR0_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR0_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR0_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR0_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR0_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+            p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR0_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR0_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->WATSR0_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SADIR1_2SRC0_0 = SADIR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCBR1_2SRC0_0 = SRCBR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSCR1_2SRC0_0 = IFSCR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->IFSVR1_2SRC0_0 = IFSVR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCCR1_2SRC0_0 = (SRCCR_2SRC0_INIT_VALUE | SRCCR_2SRC0_BASE_VALUE);
+            p_scux_info_ch->p_scux_reg->p_src_reg->MNFSR1_2SRC0_0 = MNFSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->BFSSR1_2SRC0_0 = BFSSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->WATSR1_2SRC0_0 = WATSR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 = SEVMR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SEVCR_2SRC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 = SRCIR_2SRC0_INIT_VALUE;
+        }
+        
+        /* init FFU register */
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 = FFUIR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FUAIR_FFU0_0 = FUAIR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->URQSR_FFU0_0 = URQSR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUPR_FFU0_0 = FFUPR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 = UEVMR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 = UEVCR_FFU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 = OPCIR_OPC0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_opc_reg->OPSLR_OPC0_0 = OPSLR_OPC0_INIT_VALUE;
+            *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
+            p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 = DVUIR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VADIR_DVU0_0 = VADIR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUBR_DVU0_0 = DVUBR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 = DVUCR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = ZCMCR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = VRCTR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = VRPDR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = VRDBR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = VRWTR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = VOL_N_R_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 = DVUER_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = VEVMR_DVU0_INIT_VALUE;
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 = VEVCR_DVU0_INIT_VALUE;
+            
+            for (ssif_arrange_num = 0; ssif_arrange_num < SCUX_SSIF_NUM_CH_ARRANGEMENT; ssif_arrange_num++)
+            {
+                switch (ssif_arrange_num)
+                {
+                    case SCUX_SSIF_CH_ARRANGEMENT1:
+                        p_set_ssif = p_scux_info_ch->p_ssif_info1;
+                    break;
+                    
+                    case SCUX_SSIF_CH_ARRANGEMENT2:
+                        p_set_ssif = p_scux_info_ch->p_ssif_info2;
+                    break;
+                    
+                    case SCUX_SSIF_CH_ARRANGEMENT3:
+                        p_set_ssif = p_scux_info_ch->p_ssif_info3;
+                    break;
+                    
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+                
+                if (NULL != p_set_ssif)
+                {
+                    /* check SSIF is used on other MIX SCUX channel */
+                    if (0U == ((uint32_t)p_set_ssif->scux_channel & ~(1U << p_scux_info_ch->channel)))
+                    {
+                        /* init SSIF register */
+                        p_set_ssif->p_scux_ssif_reg->SSICR = SCUX_SSICR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFCR = SCUX_SSIFCR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFTDR = SCUX_SSIFTDR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSITDMR = SCUX_SSITDMR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFCCR = SCUX_SSIFCCR_INIT_VALUE;
+                        p_set_ssif->p_scux_ssif_reg->SSIFCMR = SCUX_SSIFCMR_INIT_VALUE;
+                    }
+                }
+            }
+        }
+    
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* initialized MIX resgister when the channel using MIX to the begining and not on going cancel */ 
+            if ((0U == p_info_drv->shared_info.mix_run_ch) && (false == p_scux_info_ch->cancel_operate_flag))
+            {
+                *(p_scux_info_ch->p_scux_reg->mdb_n_r_mix0_0) = MDB_N_R_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = FUTSEL_CIM_INIT_VALUE;
+                p_scux_info_ch->futsel_cim_value = FUTSEL_CIM_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->srcrsel_n_cim) = SRCRSEL_CIM_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixir_mix0_0) = MIXIR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->madir_mix0_0) = MADIR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixbr_mix0_0) = MIXBR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) = MIXMR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mvpdr_mix0_0) = MVPDR_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) = MDBER_MIX0_0_INIT_VALUE;
+                *(p_scux_info_ch->p_scux_reg->mixrsel_cim) = MIXRSEL_CIM_INIT_VALUE;
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_InitHw
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SyncStartHw
+* @brief         Start Hw on sync mode.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SyncStartHw(const scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 &= ~FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 |= FFDBR_FFD0_BOOT_SET;
+        p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 &= ~FFUIR_FFU0_INIT_SET;
+        
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 &= ~IPCIR_IPC0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 &= ~OPCIR_OPC0_INIT_SET;
+        
+        p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 &= ~SRCIRR_2SRC0_INIT_SET;
+        
+        GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SyncStartHw
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_AsyncStartHw
+* @brief         Start Hw on async mode.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_AsyncStartHw(scux_info_ch_t * const p_scux_info_ch)
+{
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 &= ~FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 |= FFDBR_FFD0_BOOT_SET;
+            
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 &= ~FFUIR_FFU0_INIT_SET;
+        }
+        
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 &= ~SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 |= (SEVMR_2SRC0_EVMUF_SET | SEVMR_2SRC0_EVMOF_SET);
+        }
+        
+        p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 &= ~SRCIRR_2SRC0_INIT_SET;
+        
+        GIC_EnableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+        
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            SCUX_SetupDvuVolume(p_scux_info_ch);
+            
+            if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+            {
+                SCUX_SetupMix(p_scux_info_ch);
+            }
+        }
+        
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 &= ~IPCIR_IPC0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 &= ~OPCIR_OPC0_INIT_SET;
+            
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* check used SSIF is only 1 ch */
+            if (NULL == p_scux_info_ch->p_ssif_info2)
+            {
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR |= SCUX_SSICR_TEN_SET;
+            }
+            else
+            {
+                if (SCUX_SSIF_CH_0 == p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  |= SSICTRL_CIM_SSI012TEN_SET; 
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                }
+                else
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value |= SSICTRL_CIM_SSI345TEN_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                }
+            }
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_AsyncStartHw
+******************************************************************************/
+    
+/**************************************************************************//**
+* Function Name: SCUX_SyncStopHw
+* @brief         Stop Hw on sync mode.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SyncStopHw(const scux_info_ch_t * const p_scux_info_ch)
+{
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET | 
+                                                                 UEVMR_FFU0_UEVMOF_SET | 
+                                                                 UEVMR_FFU0_UEVMOL_SET);
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
+        
+        p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 |= FFUIR_FFU0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 |= OPCIR_OPC0_INIT_SET;
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET | 
+                                                                 DEVMR_FFD0_DEVMOF_SET | 
+                                                                 DEVMR_FFD0_DEVMOL_SET | 
+                                                                 DEVMR_FFD0_DEVMIUF_SET);
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 |= FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 |= IPCIR_IPC0_INIT_SET;
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 &= ~FFDBR_FFD0_BOOT_SET;
+        
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 
+                                                                       SEVMR_2SRC0_EVMOF_SET);
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 
+                                                                       SEVMR_2SRC0_EVMOF_SET);
+        }
+    
+        p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 |= SRCIRR_2SRC0_INIT_SET;
+        
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SyncStopHw
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_AsyncStopHw
+* @brief         Stop Hw on async mode.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_AsyncStopHw(scux_info_ch_t * const p_scux_info_ch)
+{
+    uint32_t  scux_check_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    uint32_t  ssipmd_mask_ssif2 = 0;
+    uint32_t  ssipmd_mask_ssif3 = 0;
+    uint32_t  ssipmd_shift_ssif2 = 0;
+    uint32_t  ssipmd_shift_ssif3 = 0;
+    uint32_t  ssipmd_reg;
+    scux_info_ch_t *p_pair_scux_ch;
+    int_t    was_masked;
+    
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->UEVMR_FFU0_0 &= ~(UEVMR_FFU0_UEVMUF_SET | 
+                                                                     UEVMR_FFU0_UEVMOF_SET | 
+                                                                     UEVMR_FFU0_UEVMOL_SET);
+            GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FUI]);
+            p_scux_info_ch->futsel_cim_value &= ~FUTSEL_CIM_DIVEN_SET;
+            *(p_scux_info_ch->p_scux_reg->futsel_n_cim) = p_scux_info_ch->futsel_cim_value;
+            
+            p_scux_info_ch->p_scux_reg->p_ffu_reg->FFUIR_FFU0_0 |= FFUIR_FFU0_INIT_SET;
+        }
+    
+        p_scux_info_ch->p_scux_reg->p_opc_reg->OPCIR_OPC0_0 |= OPCIR_OPC0_INIT_SET;
+        
+        if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_info_drv->shared_info.mix_run_ch &= ~(1U << p_scux_info_ch->channel);
+        }
+        
+        switch (p_scux_info_ch->route_set)
+        {
+            case SCUX_ROUTE_SRC0_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC1_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC2_MEM :
+                /* fall through */
+            case SCUX_ROUTE_SRC3_MEM :
+                /* do nothing, when mem to mem route is setting */
+            break;          
+            
+            case SCUX_ROUTE_SRC0_SSIF0 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+            
+            case SCUX_ROUTE_SRC0_SSIF012 :
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF3 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;            
+            
+            case SCUX_ROUTE_SRC0_SSIF345 :
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;            
+            
+            case SCUX_ROUTE_SRC1_SSIF0 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;            
+            
+            case SCUX_ROUTE_SRC1_SSIF012 :
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;            
+            
+            case SCUX_ROUTE_SRC1_SSIF3 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;                      
+                            
+            case SCUX_ROUTE_SRC1_SSIF345 : 
+                p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+            break;              
+            
+            case SCUX_ROUTE_SRC2_SSIF1 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI1TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+                
+            case SCUX_ROUTE_SRC2_SSIF4 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI4TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+                
+            case SCUX_ROUTE_SRC3_SSIF2 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI2TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+                
+            case SCUX_ROUTE_SRC3_SSIF5 :
+                p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI5TX_SET;
+                *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+            break;
+                
+            case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag) 
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;                
+                
+            case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;                
+            
+            case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;                
+                
+            case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag) 
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+
+            case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;                
+                
+            case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI0TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI0TX_SET | SSICTRL_CIM_SSI012TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+            
+            case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value &= ~SSICTRL_CIM_SSI3TX_SET;
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;                 
+                    p_scux_info_ch->p_ssif_info1->p_scux_ssif_reg->SSICR &= ~SCUX_SSICR_TEN_SET;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+                
+            case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    p_info_drv->shared_info.ssictrl_cim_value  &= ~(SSICTRL_CIM_SSI3TX_SET | SSICTRL_CIM_SSI345TEN_SET);
+                    *(p_scux_info_ch->p_scux_reg->ssictrl_cim) = p_info_drv->shared_info.ssictrl_cim_value;
+                    /* initialized MIX parameter not on going cancel */ 
+                    if (false == p_scux_info_ch->cancel_operate_flag)
+                    {
+                        p_info_drv->shared_info.mix_ssif_ch = 0;
+                    }
+                }
+            break;
+                        
+            default :
+                /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                /* <-IPA R3.5.2 */
+                /* do nothing, when mem to mem route is setting */
+            break;
+        }
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->DEVMR_FFD0_0 &= ~(DEVMR_FFD0_DEVMUF_SET | 
+                                                                 DEVMR_FFD0_DEVMOF_SET | 
+                                                                 DEVMR_FFD0_DEVMOL_SET | 
+                                                                 DEVMR_FFD0_DEVMIUF_SET);
+        GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_FDI]);
+        
+        *(p_scux_info_ch->p_scux_reg->fdtsel_n_cim) &= ~FDTSEL_CIM_DIVEN_SET;
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDIR_FFD0_0 |= FFDIR_FFD0_INIT_SET;
+        p_scux_info_ch->p_scux_reg->p_ipc_reg->IPCIR_IPC0_0 |= IPCIR_IPC0_INIT_SET;
+        
+        p_scux_info_ch->p_scux_reg->p_ffd_reg->FFDBR_FFD0_0 &= ~FFDBR_FFD0_BOOT_SET;
+        
+        /* check usc_ch ,and init SRC register */
+        if ((SCUX_CH_0 == p_scux_info_ch->channel) || (SCUX_CH_2 == p_scux_info_ch->channel))
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR0_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 
+                                                                       SEVMR_2SRC0_EVMOF_SET);        
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR0_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_src_reg->SEVMR1_2SRC0_0 &= ~(SEVMR_2SRC0_EVMUF_SET | 
+                                                                       SEVMR_2SRC0_EVMOF_SET);
+            p_scux_info_ch->p_scux_reg->p_src_reg->SRCIR1_2SRC0_0 |= SRCIR_2SRC0_INIT_SET;
+        }
+        
+        /* if pair channel is stopped, common SRC unit is initialized */
+        if (SCUX_CH_0 == p_scux_info_ch->channel)
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_1);
+        }
+        else if (SCUX_CH_1 == p_scux_info_ch->channel)
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_0);
+        }
+        else if (SCUX_CH_2 == p_scux_info_ch->channel)
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_3);
+        }
+        else
+        {
+            p_pair_scux_ch = SCUX_GetDrvChInfo(SCUX_CH_2);
+        }
+        
+        if (NULL != p_pair_scux_ch)
+        {
+            if ((SCUX_CH_UNINIT == p_pair_scux_ch->ch_stat) ||
+                (SCUX_CH_INIT == p_pair_scux_ch->ch_stat)   || 
+                (SCUX_CH_STOP == p_pair_scux_ch->ch_stat))
+            {
+                p_scux_info_ch->p_scux_reg->p_src_reg->SRCIRR_2SRC0_0 |= SRCIRR_2SRC0_INIT_SET;
+                GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_AI]);
+            }
+        }
+        else
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+            
+        if (SCUX_ROUTE_MEM_TO_MEM != (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUIR_DVU0_0 |= DVUIR_DVU0_INIT_SET;
+        
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = 0;
+            GIC_DisableIRQ(p_scux_info_ch->int_num[SCUX_INT_DVI]);
+            
+            scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info1->scux_channel;
+            scux_check_ch &= ~(1U << p_scux_info_ch->channel);
+            p_scux_info_ch->p_ssif_info1->scux_channel = (int_t)scux_check_ch;
+            if (0 == p_scux_info_ch->p_ssif_info1->scux_channel)
+            {
+#if defined (__ICCARM__)
+                was_masked = __disable_irq_iar();
+#else
+                was_masked = __disable_irq();
+#endif
+
+                /* clock mask on all used SSIF channel shutdown */
+                CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info1->ssif_cfg.ssif_ch_num]);
+
+                if (0 == was_masked)
+                {
+                    __enable_irq();
+                }
+            }
+            
+            if (NULL != p_scux_info_ch->p_ssif_info2)
+            {
+                /* clear multiple SSIF setting */
+                scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info2->scux_channel;
+                scux_check_ch &= ~(1U << p_scux_info_ch->channel);
+                p_scux_info_ch->p_ssif_info2->scux_channel = (int_t)scux_check_ch;
+                p_scux_info_ch->p_ssif_info2->pin_mode = p_scux_info_ch->p_ssif_info2->pin_mode_backup;
+                
+                switch (p_scux_info_ch->p_ssif_info2->ssif_cfg.ssif_ch_num)
+                {
+                    case SCUX_SSIF_CH_1 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI1PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI1PMD_SHIFT;
+                    break;
+                                
+                    case SCUX_SSIF_CH_2 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI2PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI2PMD_SHIFT;
+                    break;
+            
+                    case SCUX_SSIF_CH_3 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI3PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI3PMD_SHIFT;
+                    break;
+            
+                    case SCUX_SSIF_CH_4 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI4PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI4PMD_SHIFT;
+                    break;
+                                
+                    case SCUX_SSIF_CH_5 :
+                        ssipmd_mask_ssif2 = SSIPMD_CIM_SSI5PMD_MASK;
+                        ssipmd_shift_ssif2 = SSIPMD_CIM_SSI5PMD_SHIFT;
+                    break;                  
+                            
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+                
+                scux_check_ch = (uint32_t)p_scux_info_ch->p_ssif_info3->scux_channel;
+                scux_check_ch &= ~(1U << p_scux_info_ch->channel);
+                p_scux_info_ch->p_ssif_info3->scux_channel = (int_t)scux_check_ch;  
+                p_scux_info_ch->p_ssif_info3->pin_mode = p_scux_info_ch->p_ssif_info3->pin_mode_backup;
+                
+                switch (p_scux_info_ch->p_ssif_info3->ssif_cfg.ssif_ch_num)
+                {
+                    case SCUX_SSIF_CH_1 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI1PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI1PMD_SHIFT;
+                    break;
+                                
+                    case SCUX_SSIF_CH_2 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI2PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI2PMD_SHIFT;
+                    break;
+            
+                    case SCUX_SSIF_CH_3 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI3PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI3PMD_SHIFT;
+                    break;
+            
+                    case SCUX_SSIF_CH_4 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI4PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI4PMD_SHIFT;
+                    break;
+                                
+                    case SCUX_SSIF_CH_5 :
+                        ssipmd_mask_ssif3 = SSIPMD_CIM_SSI5PMD_MASK;
+                        ssipmd_shift_ssif3 = SSIPMD_CIM_SSI5PMD_SHIFT;
+                    break;                  
+                            
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+                ssipmd_reg = *(p_scux_info_ch->p_scux_reg->ssipmd_cim);
+                ssipmd_reg &= ~(ssipmd_mask_ssif2 | ssipmd_mask_ssif3);
+                
+                /* ->IPA R2.4.1 Even if pinmode and ssipmd_shift are max value, omission dose not occur. */
+                *(p_scux_info_ch->p_scux_reg->ssipmd_cim) = (ssipmd_reg | 
+                                                        ((uint32_t)p_scux_info_ch->p_ssif_info2->pin_mode << ssipmd_shift_ssif2) |
+                                                        ((uint32_t)p_scux_info_ch->p_ssif_info3->pin_mode << ssipmd_shift_ssif3));
+                /* <-IPA R2.4.1 */
+                
+                if (0 == p_scux_info_ch->p_ssif_info2->scux_channel)
+                {
+#if defined (__ICCARM__)
+                    was_masked = __disable_irq_iar();
+#else
+                    was_masked = __disable_irq();
+#endif
+
+                    /* clock mask */
+                    CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info2->ssif_cfg.ssif_ch_num]);
+
+                    if (0 == was_masked)
+                    {
+                        __enable_irq();
+                    }
+                }
+                
+                if (0 == p_scux_info_ch->p_ssif_info3->scux_channel)
+                {                
+#if defined (__ICCARM__)
+                    was_masked = __disable_irq_iar();
+#else
+                    was_masked = __disable_irq();
+#endif
+
+                    CPGSTBCR11 |= ((uint8_t)gb_cpg_scux_ssif_stbcr_bit[p_scux_info_ch->p_ssif_info3->ssif_cfg.ssif_ch_num]);
+
+                    if (0 == was_masked)
+                    {
+                        __enable_irq();
+                    }
+                }
+                
+                if (false == p_scux_info_ch->cancel_operate_flag)
+                {
+                    /* set NULL to SSIF information when cancel not on going */
+                    p_scux_info_ch->p_ssif_info2 = NULL;
+                    p_scux_info_ch->p_ssif_info3 = NULL;
+                }
+            }
+            if (false == p_scux_info_ch->cancel_operate_flag)
+            {
+                /* set NULL to SSIF information when cancel not on going */
+                p_scux_info_ch->p_ssif_info1 = NULL;
+            }
+            
+            if (SCUX_ROUTE_MIX == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+            {
+                if (0U == p_info_drv->shared_info.mix_run_ch)
+                {
+                    *(p_scux_info_ch->p_scux_reg->mixmr_mix0_0) |= MIXIR_MIX0_INIT_SET;
+                    *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
+                }
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_AsyncStopHw
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetDigiVolRegister
+* @brief         Set digital volume register.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        none.
+******************************************************************************/
+    
+void SCUX_SetDigiVolRegister(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* check and set digital volume */
+        if (false != p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_VVMD_SET;
+        
+            for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+            {
+                switch (audio_ch)
+                {
+                    case SCUX_AUDIO_CH_0 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL0R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+                       
+                    case SCUX_AUDIO_CH_1 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL1R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+                    
+                    case SCUX_AUDIO_CH_2 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL2R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;      
+            
+                    case SCUX_AUDIO_CH_3 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL3R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;  
+    
+                    case SCUX_AUDIO_CH_4 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL4R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+        
+                    case SCUX_AUDIO_CH_5 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL5R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+        
+                    case SCUX_AUDIO_CH_6 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL6R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+        
+                    case SCUX_AUDIO_CH_7 :
+                        p_scux_info_ch->p_scux_reg->p_dvu_reg->VOL7R_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch];
+                    break;
+        
+                    default :
+                        /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                        /* <-IPA R3.5.2 */
+                        /* NOTREACHED on At the time of a normal performance */
+                    break;
+                }
+            }
+        }
+        else
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 &= ~DVUCR_DVU0_VVMD_SET;
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetDigiVolRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetRampVolRegister
+* @brief         Set ramp volume register.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        none.
+******************************************************************************/
+    
+void SCUX_SetRampVolRegister(scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t audio_ch;
+    uint32_t vrctr_value = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+        {
+            if (false != p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch])
+            {
+                vrctr_value |= (VRCTR_DVU0_VREN_SET << audio_ch);
+            }
+            else
+            {
+                vrctr_value &= ~(VRCTR_DVU0_VREN_SET << audio_ch);
+            }
+        }
+            
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->VRCTR_DVU0_0 = vrctr_value;
+        
+        if (false == p_scux_info_ch->restart_ramp_flag)
+        {
+            /* set ramp paramteter to register when timming isn't restart after cancel */ 
+            /* ->IPA R2.4.1 Even if each parameters are max value, omission dose not occur. */
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = (uint32_t)((((uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.up_period << VRPDR_DVU0_VRPDUP_SHIFT) & VRPDR_DVU0_VRPDUP_MASK) | 
+                                                                  (((uint32_t)p_scux_info_ch->dvu_cfg.dvu_ramp_vol.down_period << VRPDR_DVU0_VRPDDW_SHIFT) & VRPDR_DVU0_VRPDDW_MASK));
+            /* <-IPA R2.4.1 */    
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = (p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time & VRWTR_DVU0_VRWT_MASK);
+        }
+        else
+        {
+            /* set fatest ramp parameter to register when timming is restart after cancel */ 
+            /* ->IPA R2.4.1 Even if each parameters are max value, omission dose not occur. */
+            /* when restart ,volume is changed immedeatly */
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRPDR_DVU0_0 = (uint32_t)((((uint32_t)SCUX_DVU_TIME_128DB_1STEP << VRPDR_DVU0_VRPDUP_SHIFT) & VRPDR_DVU0_VRPDUP_MASK) | 
+                                                                  (((uint32_t)SCUX_DVU_TIME_128DB_1STEP << VRPDR_DVU0_VRPDDW_SHIFT) & VRPDR_DVU0_VRPDDW_MASK));
+            /* <-IPA R2.4.1 */    
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->VRWTR_DVU0_0 = 0U;
+            p_scux_info_ch->restart_ramp_flag = false;
+        }   
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->VRDBR_DVU0_0 = p_scux_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetRampVolRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetZerocrossMuteRegister
+* @brief         Set zerocross mute register.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SetZerocrossMuteRegister(const scux_info_ch_t * const p_scux_info_ch)
+{
+    int_t    audio_ch;
+    uint32_t zcmcr_value = 0;
+    uint32_t vevmr_value = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (audio_ch = 0; audio_ch < p_scux_info_ch->src_cfg.use_ch; audio_ch++)
+        {
+            if (false != p_scux_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch])
+            {
+                zcmcr_value |= (ZCMCR_DVU0_ZCEN_SET << audio_ch);
+                vevmr_value |= (VEVMR_DVU0_VEVMZCM_SET << audio_ch);
+            }
+            else
+            {
+                zcmcr_value &= ~(ZCMCR_DVU0_ZCEN_SET << audio_ch);
+                vevmr_value &= ~(VEVMR_DVU0_VEVMZCM_SET << audio_ch);
+            }
+        }
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 = zcmcr_value;
+        p_scux_info_ch->p_scux_reg->p_dvu_reg->VEVMR_DVU0_0 = vevmr_value;
+
+        if (0U != zcmcr_value)
+        {
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 |= DVUCR_DVU0_ZCMD_SET;
+        }
+        else
+        {   
+            p_scux_info_ch->p_scux_reg->p_dvu_reg->DVUCR_DVU0_0 &= ~DVUCR_DVU0_ZCMD_SET;
+        }
+        
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetZerocrossMuteRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_SetMixVolRegister
+* @brief         Set MIX volume register.
+*
+*                Description:<br>
+*                
+* @param[in]     channel : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+    
+void SCUX_SetMixVolRegister(const int_t channel)
+{
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_scux_info_ch = SCUX_GetDrvChInfo(channel);
+
+    if ((NULL == p_info_drv) || (NULL == p_scux_info_ch))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) &= ~MDBER_MIX0_MIXDBEN_SET;
+        *(p_scux_info_ch->p_scux_reg->mdb_n_r_mix0_0) = p_info_drv->shared_info.mix_vol[channel];
+        *(p_scux_info_ch->p_scux_reg->mdber_mix0_0) |= MDBER_MIX0_MIXDBEN_SET;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_SetMixVolRegister
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_RxCallBack
+* @brief         Read request callback (mem to mem).
+*
+*                Description:<br>
+*                
+* @param[in]     param : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CopyRxCallBack(union sigval const param)
+{
+    dma_trans_data_t dma_address_param;
+    int_t retval;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (NULL != p_info_ch->p_rx_aio)
+        {
+            p_info_ch->p_rx_aio->aio_return = (ssize_t)p_info_ch->p_rx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio);
+            p_info_ch->first_rx_flag = false;
+        }
+          
+        p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size;
+        p_info_ch->dma_rx_current_size = 0;
+        p_info_ch->p_rx_aio = ahf_removehead(&p_info_ch->rx_que);
+                     
+        if (NULL != p_info_ch->p_rx_aio)
+        {
+            /* set nect data read */
+            dma_address_param.src_addr = (void *)p_info_ch->p_scux_reg->dmatu_n_cim;
+            dma_address_param.dst_addr = (void *)(p_info_ch->p_rx_aio->aio_buf);
+            dma_address_param.count = p_info_ch->p_rx_aio->aio_nbytes;
+                        
+            retval = R_DMA_Start(p_info_ch->dma_rx_ch, &dma_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_rx_current_size = dma_address_param.count;
+            }
+        }
+        else
+        {
+            switch (p_info_ch->ch_stat)
+            {
+                case SCUX_CH_UNINIT :
+                    /* fall through */
+                case SCUX_CH_INIT :
+                    /* fall through */
+                case SCUX_CH_STOP :
+                    /* fall through */
+                case SCUX_CH_TRANS_IDLE :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;                  
+                
+                case SCUX_CH_TRANS_RD :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+                break;
+                                
+                case SCUX_CH_TRANS_WR :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;              
+                                
+                case SCUX_CH_TRANS_RDWR :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_WR;
+                break;
+                
+                case SCUX_CH_STOP_WAIT :
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE;
+                break;
+
+                case SCUX_CH_STOP_WAIT_IDLE :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+
+                default :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+            }
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyRxCallBack
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CommonTxNextDummyData
+* @brief         Set next dummy data for flush (mem to mem , SSIF direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CommonTxNextDummyData(scux_info_ch_t * const p_info_ch)
+{
+    int_t retval;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+                    
+        retval = SCUX_FlushWriteStart(p_info_ch);
+        if (ESUCCESS != retval)
+        {
+            /* NON_NOTICE_ASSERT: DMA operation failed */
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CommonTxNextDummyData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxEndFlush
+* @brief         End of flush operation (mem to mem route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CopyTxEndFlush(scux_info_ch_t * const p_info_ch)
+{
+    int_t retval;
+    int_t dma_ercd;
+    uint32_t tx_remain_size = 0;
+    uint32_t rx_remain_size = 0;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* finish send dummy data process, and SCUX stop process */
+        retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* It isn't an error even if error code is EBADF, because it is already stopped. */
+        if ((ESUCCESS != retval) && (EBADF != dma_ercd))
+        {
+            /* NON_NOTICE_ASSERT: DMA operation failed */
+        }
+                    
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+               
+        retval = R_DMA_Cancel(p_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd);
+        /* It isn't an error even if error code is EBADF, because it is already stopped. */
+        if ((ESUCCESS != retval) && (EBADF != dma_ercd))
+        {
+            /* NON_NOTICE_ASSERT: DMA operation failed */
+        }
+        else
+        {
+            retval = R_DMA_Free(p_info_ch->dma_rx_ch, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+        }
+        p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size;
+        p_info_ch->dma_rx_current_size = 0;
+                    
+        if (NULL != p_info_ch->p_rx_aio)
+        {
+            /* in case NULL, dummy data read */
+            p_info_ch->p_rx_aio->aio_return = (ssize_t)(p_info_ch->p_rx_aio->aio_nbytes - rx_remain_size);
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio);
+        }
+        ahf_cancelall(&p_info_ch->rx_que);
+        p_info_ch->p_rx_aio = NULL;
+                    
+        SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, rx_remain_size);
+                      
+        if (false != p_info_ch->src_cfg.mode_sync)
+        {
+            SCUX_SyncStopHw(p_info_ch);
+        }   
+        else    
+        {
+            SCUX_AsyncStopHw(p_info_ch);
+        }
+                    
+        p_info_ch->ch_stat = SCUX_CH_STOP;
+        if (NULL != p_info_ch->p_flush_callback)
+        {
+            p_info_ch->p_flush_callback(ESUCCESS);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxEndFlush
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxNextRemainData
+* @brief         Set next remain data for flush (mem to mem route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CopyTxNextRemainData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_address_param;
+    int_t retval;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* send remain tx data prcess for flush */
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+        }
+                
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+        p_info_ch->p_tx_aio = ahf_removehead(&p_info_ch->tx_que);
+                
+        if (NULL == p_info_ch->p_tx_aio)
+        {
+            retval = SCUX_FlushWriteStart(p_info_ch);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+        }
+        else
+        {
+            dma_address_param.src_addr = (void *)(p_info_ch->p_tx_aio->aio_buf);
+            dma_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_address_param.count = p_info_ch->p_tx_aio->aio_nbytes;
+                        
+            retval = R_DMA_Start(p_info_ch->dma_tx_ch, &dma_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = dma_address_param.count;
+            }
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxNextRemainData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxNextData
+* @brief         Set next data for normal operation (mem to mem route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CopyTxNextData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_address_param;
+    int_t retval;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* normal send process */
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+        }
+            
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+        p_info_ch->p_tx_aio = ahf_removehead(&p_info_ch->tx_que);
+                
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            dma_address_param.src_addr = (void *)(p_info_ch->p_tx_aio->aio_buf);
+            dma_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_address_param.count = p_info_ch->p_tx_aio->aio_nbytes;
+                    
+            retval = R_DMA_Start(p_info_ch->dma_tx_ch, &dma_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = dma_address_param.count;
+            }
+        }
+        else
+        {
+            switch (p_info_ch->ch_stat)
+            {
+                case SCUX_CH_UNINIT :
+                    /* fall through */
+                case SCUX_CH_INIT :
+                    /* fall through */
+                case SCUX_CH_STOP :
+                    /* fall through */
+                case SCUX_CH_TRANS_IDLE :
+                    /* fall through */
+                case SCUX_CH_TRANS_RD :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+              
+                case SCUX_CH_TRANS_WR :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+                break;                  
+                    
+                case SCUX_CH_TRANS_RDWR :
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_RD;
+                break;
+                    
+                case SCUX_CH_STOP_WAIT :
+                    /* fall through */
+                case SCUX_CH_STOP_WAIT_IDLE :
+                    /* NON_NOTICE_ASSERT : NOTREACHED on At the time of a normal performance */
+                break;
+                    
+                default :
+                    /* NOTREACHED on At the time of a normal performance */
+                break;                    
+            }           
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxNextData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_CopyTxCallBack
+* @brief         Write request callback (mem to mem route).
+*
+*                Description:<br>
+*                
+* @param[in]     param : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_CopyTxCallBack(union sigval const param)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if ((SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) || (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat))
+        {
+            /* data flush process */
+            if (false != p_info_ch->tx_dummy_run_flag)
+            {
+                if (0U == p_info_ch->flush_stop_size)
+                {
+                    SCUX_DMA_CopyTxEndFlush(p_info_ch);
+                }
+                else
+                {
+                    SCUX_DMA_CommonTxNextDummyData(p_info_ch);
+                }
+            }
+            else
+            {
+                SCUX_DMA_CopyTxNextRemainData(p_info_ch);   
+            }
+        }
+        else
+        {
+            SCUX_DMA_CopyTxNextData(p_info_ch);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_CopyTxCallBack
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxEndFlush
+* @brief         End of flush operation (SSIF Direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_DirectTxEndFlush(scux_info_ch_t * const p_info_ch)
+{
+    int_t retval;
+    int_t dma_ercd;
+    uint32_t tx_remain_size = 0;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* finish send dummy data process, and SCUX stop process */
+        retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+        /* It isn't an error even if error code is EBADF, because it is already stopped. */
+        if ((ESUCCESS != retval) && (EBADF != dma_ercd))
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+                                      
+        SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, 0);
+                      
+        SCUX_AsyncStopHw(p_info_ch);
+                  
+        p_info_ch->ch_stat = SCUX_CH_STOP;
+        if (NULL != p_info_ch->p_flush_callback)
+        {
+            p_info_ch->p_flush_callback(ESUCCESS);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirectTxEndFlush
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxNextRemainData
+* @brief         Set next remain data for flush (SSIF Direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_DirectTxNextRemainData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_next_address_param;
+    int_t retval;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+            p_info_ch->first_tx_flag = false;
+        }
+                
+
+        /* send remain tx data prcess for flush */
+        p_info_ch->p_tx_aio = p_info_ch->p_tx_next_aio;
+        p_info_ch->p_tx_next_aio = ahf_removehead(&p_info_ch->tx_que);
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->dma_tx_current_size = 0;
+                    
+        if ((NULL != p_info_ch->p_tx_next_aio) && (NULL != p_info_ch->p_tx_aio))
+        {
+           /* 1.
+            * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio isn't NULL.
+            * Since, Next DMA is effective and p_info_ch->p_tx_aio is set to Next DMA
+            * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 
+            * p_info_ch->dma_tx_next_size.
+            * The vaule of p_info_ch->dma_tx_next_size is updated to the value of DMA size
+            * on Next DMA.
+            */
+            dma_next_address_param.src_addr = (void *)(p_info_ch->p_tx_next_aio->aio_buf);
+            dma_next_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_next_address_param.count = p_info_ch->p_tx_next_aio->aio_nbytes;
+                        
+            retval = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_next_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+                p_info_ch->dma_tx_next_size = dma_next_address_param.count;
+            }
+        }
+        else if ((NULL != p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+           /* 2.
+            * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio is NULL.
+            * Since, Next DMA is Stopped and DMA is restarted to p_info_ch->p_tx_aio
+            * The vaule of p_info_ch->dma_tx_current_size and p_info_ch->dma_tx_next_size 
+            * are updated to restart DMA value. 
+            */
+            retval = SCUX_DirectWriteStart(p_info_ch, p_info_ch->p_tx_next_aio);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+        }
+        else if ((NULL == p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+            /* 3.
+             * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio is NULL.
+             * Since, all request finished, and flush data write start.
+             * The vaule of p_info_ch->dma_tx_current_size is updated to flush DMA value. 
+             */
+                        
+            retval = SCUX_FlushWriteStart(p_info_ch);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: DMA operation failed */
+            }
+        }
+        else
+        {
+           /* 4.
+            * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio isn't NULL.
+            * Since, Nothing new aio request, and processing of 2. or 3. is performed
+            * in the next loop.
+            * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 
+            * p_info_ch->dma_tx_next_size.
+            */  
+                        
+            p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+            p_info_ch->dma_tx_next_size = 0;
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirectTxNextRemainData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxNextData
+* @brief         Set next data normal operation (SSIF Direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     *p_scux_info_ch : SCUX channel information.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_DirectTxNextData(scux_info_ch_t * const p_info_ch)
+{
+    dma_trans_data_t dma_next_address_param;
+    int_t retval;
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (NULL != p_info_ch->p_tx_aio)
+        {
+            p_info_ch->p_tx_aio->aio_return = (ssize_t)p_info_ch->p_tx_aio->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+            p_info_ch->first_tx_flag = false;
+        }
+           
+        /* normal send process */
+        p_info_ch->p_tx_aio = p_info_ch->p_tx_next_aio;
+        p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+        p_info_ch->p_tx_next_aio = ahf_removehead(&p_info_ch->tx_que);
+            
+        if ((NULL != p_info_ch->p_tx_next_aio) && (NULL != p_info_ch->p_tx_aio))
+        {
+            /* 1.
+             * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio isn't NULL.
+.            * Since, Next DMA is effective and p_info_ch->p_tx_aio is set to Next DMA
+             * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 
+             * p_info_ch->dma_tx_next_size.
+             * The vaule of p_info_ch->dma_tx_next_size is updated to the value of DMA size
+             * on Next DMA.
+             */
+            dma_next_address_param.src_addr = (void *)(p_info_ch->p_tx_next_aio->aio_buf);
+            dma_next_address_param.dst_addr = (void *)p_info_ch->p_scux_reg->dmatd_n_cim;
+            dma_next_address_param.count = p_info_ch->p_tx_next_aio->aio_nbytes;
+                    
+            retval = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_next_address_param, NULL);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+                p_info_ch->dma_tx_next_size = dma_next_address_param.count;
+            }
+        }
+        else if ((NULL != p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+            /* 2.
+             * p_info_ch->p_tx_next_aio isn't NULL, and p_info_ch->p_tx_aio is NULL.
+             * Since, Next DMA is Stopped and DMA is restarted to p_info_ch->p_tx_aio
+             * The vaule of p_info_ch->dma_tx_current_size and p_info_ch->dma_tx_next_size 
+             * are updated to restart DMA value. 
+             */
+                   
+            retval = SCUX_DirectWriteStart(p_info_ch, p_info_ch->p_tx_next_aio);
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+        }
+        else if((NULL == p_info_ch->p_tx_next_aio) && (NULL == p_info_ch->p_tx_aio))
+        {
+            /* 3.
+             * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio is NULL.
+             * Since, all request finished, and status is made to change IDLE.
+             * The vaule of p_info_ch->dma_tx_current_size is updated to 0. 
+             */
+            p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+            p_info_ch->dma_tx_current_size = 0;
+                    
+        }
+        else
+        {
+            /* 4.
+             * p_info_ch->p_tx_next_aio is NULL, and p_info_ch->p_tx_aio isn't NULL.
+             * Since, Nothing new aio request, and processing of 2. or 3. is performed
+             * in the next loop.
+             * The vaule of p_info_ch->dma_tx_current_size is updated to the value of 
+             * p_info_ch->dma_tx_next_size.
+             */                 
+                
+            p_info_ch->dma_tx_current_size = p_info_ch->dma_tx_next_size;
+            p_info_ch->dma_tx_next_size = 0;
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirectTxNextData
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_DMA_DirectTxCallBack
+* @brief         Write request callback (SSIF Direct route).
+*
+*                Description:<br>
+*                
+* @param[in]     param : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+    
+static void SCUX_DMA_DirectTxCallBack(union sigval const param)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(param.sival_int);
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_CH_STOP_WAIT == p_info_ch->ch_stat)
+        {
+            /* data flush process */
+            if (false != p_info_ch->tx_dummy_run_flag)
+            {                
+                if (0U == p_info_ch->flush_stop_size)
+                {
+                    SCUX_DMA_DirectTxEndFlush(p_info_ch);
+                }
+                else
+                {
+                    SCUX_DMA_CommonTxNextDummyData(p_info_ch);
+                }
+            }
+            else
+            {
+                SCUX_DMA_DirectTxNextRemainData(p_info_ch);
+            }
+        }
+        else
+        {
+            SCUX_DMA_DirectTxNextData(p_info_ch);
+        }
+    }
+}
+
+/******************************************************************************
+End of function SCUX_DMA_DirextTxCallBack
+******************************************************************************/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/scux/scux_if.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1849 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_if.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* @brief        SCUX Driver interface functions
+
+*******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+#include "bsp_util.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define SCUX_PATH_CH0 "\\0"    /**< channel 0 pathname */
+#define SCUX_PATH_CH1 "\\1"    /**< channel 1 pathname */
+#define SCUX_PATH_CH2 "\\2"    /**< channel 2 pathname */
+#define SCUX_PATH_CH3 "\\3"    /**< channel 3 pathname */
+#define MAX_PATH_SEARCH_LEN (32U)
+
+/******************************************************************************
+Private global tables
+******************************************************************************/
+
+#if(1) /* mbed */
+#else  /* not mbed */
+static IOIF_DRV_API gb_ioif_scux_cb_table;
+#endif /* end mbed */
+
+static const char_t* const p_gb_device_name[SCUX_CH_NUM] =
+{
+    SCUX_PATH_CH0,
+    SCUX_PATH_CH1,
+    SCUX_PATH_CH2,
+    SCUX_PATH_CH3
+};
+
+/******************************************************************************
+Private global driver semaphore informationn
+******************************************************************************/
+
+/******************************************************************************
+ Function prototypes
+ *****************************************************************************/
+#if(1) /* mbed */
+static void *R_SCUX_InitOne(const int_t channel, const void * const p_config_data, int32_t * const p_errno); 
+static int_t R_SCUX_UnInitOne(const int_t channel, const void* const p_driver_instance, int32_t * const p_errno);
+#else
+static void* R_SCUX_Init(void * p_config_data, int32_t * const p_errno);
+static int_t R_SCUX_UnInit(void *p_driver_instance, int32_t * const p_errno);
+#endif /* end mbed */
+static int_t R_SCUX_Open(void * const p_driver_instance, const char_t * p_path_name, const int_t flags, int_t mode, int32_t * const p_errno);
+static int_t R_SCUX_Close(void * const p_fd, int32_t * const p_errno);
+static int_t R_SCUX_Ioctl(void * const p_fd, const int_t request, void * const p_buf, int32_t * const p_errno);
+static int_t R_SCUX_WriteAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+static int_t R_SCUX_ReadAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+static int_t R_SCUX_Cancel(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno);
+static void  SCUX_SetErrCode(const int_t error_code, int32_t * const p_errno);
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: R_SCUX_MakeCbTbl_mbed
+* @brief         Returns the SCUX driver callback function table.
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        pointer of sample driver callback table
+******************************************************************************/
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+RBSP_MBED_FNS* R_SCUX_MakeCbTbl_mbed(void)
+/* <-IPA M1.1.1 */
+{
+    static RBSP_MBED_FNS scux_apitbl_mbed;
+
+    scux_apitbl_mbed.initialise_one   = &R_SCUX_InitOne;
+    scux_apitbl_mbed.uninitialise_one = &R_SCUX_UnInitOne;
+    scux_apitbl_mbed.open             = &R_SCUX_Open;
+    scux_apitbl_mbed.close            = &R_SCUX_Close;
+    scux_apitbl_mbed.ioctl            = &R_SCUX_Ioctl;
+    scux_apitbl_mbed.write_a          = &R_SCUX_WriteAsync;
+    scux_apitbl_mbed.read_a           = &R_SCUX_ReadAsync;
+    scux_apitbl_mbed.cancel           = &R_SCUX_Cancel;
+
+    return &scux_apitbl_mbed;
+}
+/******************************************************************************
+End of function R_SCUX_MakeCbTbl_mbed
+******************************************************************************/
+#else
+
+/**************************************************************************//**
+* Function Name: R_SCUX_MakeCbTbl
+* @brief         Returns the SCUX driver callback function table.
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        pointer of sample driver callback table
+******************************************************************************/
+/* ->IPA M1.1.1 If this function is the whole system, it will be called. */
+IOIF_DRV_API* R_SCUX_MakeCbTbl(void)
+/* <-IPA M1.1.1 */
+{
+    static IOIF_DRV_API gb_ioif_scux_cb_table;
+    IOIF_DRV_API* const p_api = &gb_ioif_scux_cb_table;
+
+    /* ->MISRA 16.4, IPA M4.5.1 This description is based on the way to fill out OS defined. */
+    p_api->family = IOIF_SERIAL_FAMILY;
+    p_api->fns.serial.initialise   = &R_SCUX_Init;
+    p_api->fns.serial.uninitialise = &R_SCUX_UnInit;
+    p_api->fns.serial.open         = &R_SCUX_Open;
+    p_api->fns.serial.close        = &R_SCUX_Close;
+    p_api->fns.serial.ioctl        = &R_SCUX_Ioctl;
+    p_api->fns.serial.write_a      = &R_SCUX_WriteAsync;
+    p_api->fns.serial.read_a       = &R_SCUX_ReadAsync;
+    p_api->fns.serial.cancel       = &R_SCUX_Cancel;
+    /* <-MISRA 16.4, IPA M4.5.1 */
+     
+    return p_api;
+}
+
+/******************************************************************************
+End of function R_SCUX_MakeCbTbl
+******************************************************************************/
+#endif /* end mbed */
+
+/**************************************************************************//**
+* Function Name: SCUX_SetErrCode
+* @brief         Set error code to error code pointer.
+*
+*                Description:<br>
+*                If error code pointer is NULL, nothing is done.
+* @param[in]     error_code :Error code.
+* @param[in,out] p_errno    :Pointer of set error code.
+* @retval        none
+******************************************************************************/
+static void SCUX_SetErrCode(int_t error_code, int32_t * const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function R_SCUX_SetErrCode
+******************************************************************************/
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+#if(1) /* mbed */
+/**************************************************************************//**
+* Function Name: R_SCUX_InitOne
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :Initialize channel number.
+* @param[in]     p_config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            ENOMEM : Making semaphore failed.
+*                            EBUSY  : SCUX driver has been initialized already.
+*                            EFAULT : p_config_data is NULL.
+*                            EFAULT : Internal error is occured.
+* @retval        other than (-1)
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static void *R_SCUX_InitOne(const int_t channel, const void * const p_config_data, int32_t * const p_errno) 
+{
+    int_t         ercd;
+    void          *ret;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t  * p_info_ch;
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else if ((SCUX_CH_0 > channel) || ( SCUX_CH_NUM <= channel))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        p_info_ch = SCUX_GetDrvChInfo(channel);
+
+        if (NULL == p_info_ch)
+        {
+            ercd = EFAULT;
+        }
+        else if (false != p_info_ch->enabled)
+        {
+            ercd = EBUSY;
+        }
+        else
+        {
+            if (NULL == p_config_data)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            else
+            {
+                /* init SCUX driver */
+                ercd = SCUX_InitializeOne(channel, (const scux_channel_cfg_t *)p_config_data);
+            }
+        }
+    }
+    
+    if (ESUCCESS == ercd)
+    {
+        ret = (void *)p_info_drv;
+    }
+    else
+    {
+        ret = (void *)(EERROR);
+    }
+
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return ret;
+}
+/******************************************************************************
+End of function R_SCUX_InitOne
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_UnInitOne
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :Uninitialize channel number.
+* @param[in]     p_driver_instance :which was returned by R_SCUX_Init
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            EBADF : Driver status isn't SCUX_DRV_INIT.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+/* ->MISRA 16.7 'p_driver_instance' is based on the way to fill out OS defined. */
+/* ->IPA M1.11.1 */
+static int_t R_SCUX_UnInitOne(const int_t channel, const void* const p_driver_instance, int32_t * const p_errno)
+/* <-IPA M1.11.1 */
+/* <-MISRA 16.7 */
+{
+    int_t            retval = ESUCCESS;
+    int_t            ercd = ESUCCESS;
+    scux_info_drv_t  * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t   * p_info_ch;
+
+    UNUSED_ARG(p_driver_instance);
+    
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else if ((SCUX_CH_0 > channel) || ( SCUX_CH_NUM <= channel))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EBADF;
+        }
+        else
+        {
+            p_info_ch = SCUX_GetDrvChInfo(channel);
+
+            if (NULL == p_info_ch)
+            {
+                ercd = EFAULT;
+            }
+            else if (false == p_info_ch->enabled)
+            {
+                ercd = EBADF;
+            }
+            else
+            {
+                SCUX_UnInitializeOne(channel);
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+
+    return retval;
+}
+
+/******************************************************************************
+End of function R_SCUX_UnInitOne
+******************************************************************************/
+#else  /* not mbed */
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Init
+* @brief         Init SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     p_config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            ENOMEM : Making semaphore failed.
+*                            EBUSY  : SCUX driver has been initialized already.
+*                            EFAULT : p_config_data is NULL.
+*                            EFAULT : Internal error is occured.
+* @retval        other than (-1)
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+/* ->MISRA 16.7 'p_config_data' is based on the way to fill out OS defined. */
+/* ->IPA M1.11.1 */
+static void *R_SCUX_Init(void * p_config_data, int32_t * const p_errno) 
+/* <-IPA M1.11.1 */
+/* <-MISRA 16.7 */
+{
+    int_t         ercd;
+    void          *ret;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SCUX_DRV_UNINIT != p_info_drv->drv_stat)
+        {
+            ercd = EBUSY;
+        }
+        else
+        {
+            if (NULL == p_config_data)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            else
+            {
+                /* init SCUX driver */
+                ercd = SCUX_Initialize((scux_channel_cfg_t *)p_config_data);
+            }
+        }
+    }
+    
+    if (ESUCCESS == ercd)
+    {
+        ret = (void *)p_info_drv;
+    }
+    else
+    {
+        ret = (void *)(EERROR);
+    }
+
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return ret;
+}
+
+/******************************************************************************
+End of function R_SCUX_Init
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_UnInit
+* @brief         Uninit SCUX driver.
+*
+*                Description:<br>
+*                
+* @param[in]     p_driver_instance :which was returned by R_SCUX_Init
+* @param[in,out] p_errno    :pointer of error code
+*                            error code -
+*                            EBADF : Driver status isn't SCUX_DRV_INIT.
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+/* ->MISRA 16.7 'p_driver_instance' is based on the way to fill out OS defined. */
+/* ->IPA M1.11.1 */
+static int_t R_SCUX_UnInit(void* p_driver_instance, int32_t * const p_errno)
+/* <-IPA M1.11.1 */
+/* <-MISRA 16.7 */
+{
+    int_t            retval = ESUCCESS;
+    int_t            ercd = ESUCCESS;
+    scux_info_drv_t  * const p_info_drv = SCUX_GetDrvInstance();
+
+    UNUSED_ARG(p_driver_instance);
+    
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EBADF;
+        }
+        else
+        {
+            SCUX_UnInitialize();
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+}
+#endif /* end mbed */
+
+/******************************************************************************
+End of function R_SCUX_UnInit
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Open
+* @brief         Open SCUX Channel.
+*
+*                Description:<br>
+*                
+* @param[in]     p_driver_instance:which was returned by R_SCUX_Init()
+* @param[in]     p_path_name   :device Name
+* @param[in]     flags         :specifies the access mode whether the channel is 
+*                               opened for a read or a write
+* @param[in]     mode          :specifies the permissions to use in case a new file
+*                               is created (not used for serial family driver)
+* @param[in,out] p_errno       :pointer of error code
+*                               error code -
+*                               ENOMEM : Craeaton of IOIF queue is failed.
+*                               ENOENT : Pathname is incorrect length.
+*                               ENOENT : Channel information is NULL.
+*                               EACCES : Setting to flag is other than O_WONLY or O_RDWR
+*                               EMFILE : Allocation of write DMA channel is failed.
+*                               ENOTSUP : Channel is not support.
+*                               EFAULT : Internal error is occured.
+*                               
+* @retval        Except ERROR -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+/* ->IPA M1.11.1 This description is based on the way to fill out OS defined. */
+static int_t R_SCUX_Open(void * const p_driver_instance, const char_t * p_path_name, const int_t flags, int_t mode , int32_t * const p_errno)
+/* <-IPA M1.11.1 */
+{
+    int_t ercd = ESUCCESS;
+    osStatus sem_ercd;
+    int32_t  sem_wait_ercd;
+    void* p_channel_handle;
+    scux_info_drv_t * const p_info_drv = (scux_info_drv_t *)p_driver_instance;
+    scux_info_ch_t *p_info_ch = NULL;
+    uint32_t open_channel;
+    size_t pathname_len;
+    size_t compare_len;
+
+    UNUSED_ARG(mode);
+
+    /* check driver instance */
+    if (NULL == p_driver_instance)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (NULL == p_info_drv)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT;
+            }
+        }
+    }
+    
+    /* check path name */
+    if (ESUCCESS == ercd)
+    {
+        if (NULL == p_info_drv)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            if (NULL == p_path_name)
+            {
+                ercd = EFAULT;
+            }
+            else
+            {
+                /* check length of path name */
+                pathname_len = SCUX_StrNLen(p_path_name, MAX_PATH_SEARCH_LEN);
+                if ( (0U == pathname_len) || (MAX_PATH_SEARCH_LEN == pathname_len) )
+                {
+                    ercd = ENOENT;
+                }
+                else
+                {
+                    for (open_channel = 0; ((open_channel < SCUX_CH_NUM) && (NULL == p_info_ch)); open_channel++)
+                    {
+                        /* Avoid reading beyond the end of the shortest of the two strings */
+                        compare_len = SCUX_StrNLen(p_gb_device_name[open_channel], MAX_PATH_SEARCH_LEN);
+                        if (pathname_len < compare_len)
+                        {
+                            compare_len = pathname_len;
+                        }
+        
+                        if (0 == strncmp(p_path_name, p_gb_device_name[open_channel], compare_len))
+                        {
+                            if (NULL != p_info_drv->info_ch)
+                            {
+                                p_info_ch = &p_info_drv->info_ch[open_channel]; /* found a match */
+                            }
+                        }           
+                    }
+                    
+                    if (NULL == p_info_ch)
+                    {
+                        ercd = ENOENT; /* Pathname not recognised */
+                    }
+                }
+            }
+        }
+    }
+    
+    if (NULL != p_info_ch)
+    {
+        if (ESUCCESS == ercd)
+        {
+            if ((O_WRONLY != flags) && (O_RDWR != flags))
+            {
+                ercd = EACCES;
+            }
+            
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            else
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = ENOTSUP;
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+                    if (SCUX_CH_INIT != p_info_ch->ch_stat)
+                    {
+                        ercd = EBUSY;
+                    }
+                }
+    
+                if (ESUCCESS == ercd)
+                {
+                    ercd = SCUX_OpenChannel(p_info_ch->channel, flags);
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+        }
+    }
+
+    if (ESUCCESS == ercd)
+    {
+        p_channel_handle = (void*)p_info_ch;
+    }
+    else
+    {
+        p_channel_handle = (void*)EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return (int_t)p_channel_handle;
+}
+
+/******************************************************************************
+End of function R_SCUX_Open
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Close
+* @brief         Close SCUX Channel.
+*
+*                Description:<br>
+*                
+* @param[in]     p_fd:which was returned by R_SCUX_Init()
+* @param[in,out] p_errno:pointer of error code
+*                        error code -
+*                           EFAULT : Internal error is occured.
+*                               
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static int_t R_SCUX_Close(void * const p_fd, int32_t * const p_errno)
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    int32_t sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_ch) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT;
+        }
+        
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT;
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+                    if ((SCUX_CH_UNINIT == p_info_ch->ch_stat) ||
+                        (SCUX_CH_INIT == p_info_ch->ch_stat))
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+                    /* close channel */
+                    ercd = SCUX_CloseChannel(p_info_ch->channel);               
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                    ercd = EFAULT;
+            }
+            
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_SCUX_Close
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Ioctl
+* @brief         SCUX driver IOCTL function.
+*
+*                Description:<br>
+*                
+* @param[in]     p_fd: pointer of SCUX handler
+* @param[in]     request:IOCTL request code
+* @param[in]     p_buf  :Data buffer for IOCTL request code.
+* @param[in,out] p_errno:pointer of error code
+*                        error code -
+*                           EINVAL : IOCTL request code is unexpected value.
+*                           EFAULT : Internal error is occured.
+*                           other value : The value depending on IOCTL request code.
+*                                         Refer to the function of scux_ioctl.c for those meanings. 
+*                               
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static int_t R_SCUX_Ioctl(void * const p_fd, const int_t request, void * const p_buf, int32_t * const p_errno)
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    int32_t sem_wait_ercd;
+    int_t  was_masked;
+    osStatus sem_ercd;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_ch) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT;
+        }
+    
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            if (0 == R_ExceptionalMode())
+            {
+                sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* <-MISRA 1.2 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set error return value */
+                    ercd = EFAULT;
+                }
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT;
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+                    if ((SCUX_CH_UNINIT == p_info_ch->ch_stat) ||
+                        (SCUX_CH_INIT == p_info_ch->ch_stat))
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+                
+            }
+            
+            if (0 == R_ExceptionalMode())
+            {
+                sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set error return value */
+                    ercd = EFAULT;
+                }
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                switch (request)
+                {
+                    case SCUX_IOCTL_SET_START:
+                    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                ercd = SCUX_IoctlTransStart(p_info_ch->channel);
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        
+                    break;
+            
+                    case SCUX_IOCTL_SET_FLUSH_STOP:
+                    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            /* check p_Buf */
+                            if (NULL == p_buf)
+                            {
+                                ercd = EFAULT;
+                            }
+                            else
+                            {                    
+#if defined (__ICCARM__)
+                                was_masked = __disable_irq_iar();
+#else
+                                was_masked = __disable_irq();
+#endif    
+                                if (SCUX_CH_STOP == p_info_ch->ch_stat)
+                                {
+                                    ercd = EBUSY;
+                                }
+                                
+                                /* The mesure to MISRA 1.1 , SEC P1.1.1 */
+                                if ((ESUCCESS != ercd) && (0 == was_masked))
+                                {
+                                    /* enable all irq when ch_stat is SCUX_CH_STOP */
+                                    __enable_irq();                                 
+                                }
+                                
+                                if (ESUCCESS == ercd)
+                                {
+                                    /* ->MISRA 11.1 Since it is necessary to register a callback function, 
+                                    the cast from a void pointer is performed intentionally. */
+                                    ercd = SCUX_IoctlFlushStop(p_info_ch->channel, (void ( *)(int_t))p_buf, was_masked);
+                                    /* <-MISRA 11.1 */
+                                }
+                                
+                            }
+                        }
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                                                
+                    break;
+            
+                    case SCUX_IOCTL_SET_CLEAR_STOP:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                   
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+#if defined (__ICCARM__)
+                            was_masked = __disable_irq_iar();
+#else
+                            was_masked = __disable_irq();
+#endif    
+                            if (SCUX_CH_STOP == p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                                        
+                                if (0 == was_masked)
+                                {
+                                    /* enable all irq */
+                                    __enable_irq();
+                                }                                
+                            }
+                            else
+                            {
+                                /* This exclusive access control ends in the SCUX_IoctlClearStop */
+                                ercd = SCUX_IoctlClearStop(p_info_ch->channel, was_masked);
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_ROUTE:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    SCUX_IoctlSetRoute(p_info_ch->channel, *(scux_route_t *)p_buf);
+                                }
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_PIN_CLK:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    ercd = SCUX_IoctlSetPinClk(p_info_ch->channel, (scux_ssif_pin_clk_t *)p_buf);
+                                }
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        
+                    break;
+    
+                    case SCUX_IOCTL_SET_PIN_MODE:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    ercd = SCUX_IoctlSetPinMode(p_info_ch->channel, (scux_ssif_pin_mode_t *)p_buf);
+                                }
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }                    
+                            
+                    break;
+                    
+                    case SCUX_IOCTL_SET_SRC_CFG:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    SCUX_IoctlSetSrcCfg(p_info_ch->channel, (scux_src_cfg_t *)p_buf);
+                                }
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                            
+                    break;
+                            
+                    case SCUX_IOCTL_SET_DVU_CFG:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    SCUX_IoctlSetDvuCfg(p_info_ch->channel, (scux_dvu_cfg_t *)p_buf);
+                                }
+                            }   
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }                    
+                        
+                    break;
+                       
+                    case SCUX_IOCTL_SET_DVU_DIGI_VOL:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetDvuDigiVol(p_info_ch->channel, (scux_dvu_digi_vol_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_DVU_RAMP_VOL:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetDvuRampVol(p_info_ch->channel, (scux_dvu_ramp_vol_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_ZEROCROSS_MUTE:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetDvuZerocrossMute(p_info_ch->channel, (scux_zc_mute_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_STOP_MUTE:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetStopMute(p_info_ch->channel, *(uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_MIX_CFG:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetMixCfg((scux_mix_cfg_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_SET_MIX_VOL:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SCUX_IoctlSetMixVol(p_info_ch->channel, *(uint32_t *)p_buf);
+                        }
+                    
+                    break;
+                        
+                    case SCUX_IOCTL_SET_SSIF_CFG:
+    
+                        /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+                        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/                     
+                        sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+                        /* <-MISRA 10.6 */
+                        /* <-MISRA 1.2 */
+                        /* semaphore error check */
+                        if ((-1) == sem_wait_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            if (SCUX_CH_STOP != p_info_ch->ch_stat)
+                            {
+                                ercd = EBUSY;
+                            }
+                            else
+                            {
+                                if (NULL == p_buf)
+                                {
+                                    ercd = EFAULT;
+                                }
+                                else
+                                {
+                                    ercd = SCUX_IoctlSetSsifCfg((scux_ssif_cfg_t *)p_buf);
+                                }
+                            }
+                        }
+                        
+                        sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+                        /* semaphore error check */
+                        if (osOK != sem_ercd)
+                        {
+                            /* set error return value */
+                            ercd = EFAULT;
+                        }                    
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_GET_WRITE_STAT:
+                    
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetWriteStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                    
+                    case SCUX_IOCTL_GET_READ_STAT:
+                    
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetReadStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_GET_DVU_STAT:
+                    
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetDvuStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                    
+                    case SCUX_IOCTL_GET_MUTE_STAT:
+                    
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetMuteStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                        
+                    case SCUX_IOCTL_GET_MIX_STAT:
+                        
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            SCUX_IoctlGetMixStat(p_info_ch->channel, (uint32_t *)p_buf);
+                        }
+                            
+                    break;
+                                            
+                    default:
+                        ercd = EINVAL;
+                    break;
+                }
+            }
+        }
+    }
+    
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Ioctl
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_WriteAsync
+* @brief         SCUX driver asynchronous write.
+*
+*                Description:<br>
+*                
+* @param[in]     p_fd   :channel handle which was returned by R_SCUX_Open
+* @param[in]     p_aio  :aio control block.
+* @param[in,out] p_errno:pointer of error code
+*                               error code -
+*                               EBADF : Channel status isn't SCUX_CH_STOP or SCUX_CH_STOP_WAIT. 
+*                               EINVAL : p_fd is NULL.
+*                               EINVAL : write size is 0.
+*                               EFAULT : Internal error is occured.
+*                               
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static int_t R_SCUX_WriteAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    int_t sem_ercd;
+    int32_t  sem_wait_ercd;
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_ch) || (NULL == p_aio) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (0U == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL;
+        }
+        
+        if (ESUCCESS == ercd)
+        {
+            if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT;
+            }
+        }
+        
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            else
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT;
+                }
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+#if defined (__ICCARM__)
+                was_masked = __disable_irq_iar();
+#else
+                was_masked = __disable_irq();
+#endif
+
+                if (ESUCCESS != p_info_ch->err_stat_backup)
+                {
+                    /* set error code */
+                    ercd = p_info_ch->err_stat_backup;
+                }
+                else
+                {
+                    switch (p_info_ch->ch_stat)
+                    {
+                        case SCUX_CH_UNINIT :
+                            /* fall through */
+                        case SCUX_CH_INIT :
+                            ercd = EFAULT;
+                        break;              
+                        
+                        case SCUX_CH_STOP :
+                            ercd = EBADF;
+                        break;                  
+                        
+                        case SCUX_CH_TRANS_IDLE :
+                            /* fall through */
+                        case SCUX_CH_TRANS_RD :
+                            if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                            {
+                                ercd = SCUX_DirectWriteStart(p_info_ch, p_aio);
+                            }
+                            else
+                            {
+                                ercd = SCUX_CopyWriteStart(p_info_ch, p_aio);
+                            }
+                        break;
+                        
+                        case SCUX_CH_TRANS_WR :
+                            /* fall through */
+                        case SCUX_CH_TRANS_RDWR :
+                            ahf_addtail(&p_info_ch->tx_que, p_aio);
+                        break;
+                        
+                        case SCUX_CH_STOP_WAIT :
+                            /* fall through */
+                        case SCUX_CH_STOP_WAIT_IDLE :
+                            ercd = EBADF;
+                        break;
+                        
+                        default :
+                            ercd = EFAULT;
+                        break;
+                    }
+                }
+                
+                if (0 == was_masked)
+                {
+                    __enable_irq();
+                } 
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+        }
+    }
+    
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_WriteAsync
+******************************************************************************/
+/**************************************************************************//**
+* Function Name: R_SCUX_ReadAsync
+* @brief         SCUX driver asynchronous read.
+*
+*                Description:<br>
+*                
+* @param[in]     p_fd   :channel handle which was returned by R_SCUX_open
+* @param[in]     p_aio  :aio control block.
+* @param[in,out] p_errno:pointer of error code
+*                               error code -
+*                               EBADF : Channel status isn't SCUX_CH_STOP or SCUX_CH_STOP_WAIT. 
+*                               EINVAL : read size is 0.
+*                               EACCES : Request for write only mode channel.
+*                               EACCES : Route setting is unexpected.
+*                               EFAULT : Internal error is occured.
+*                               
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static int_t R_SCUX_ReadAsync(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus sem_ercd;
+    int32_t sem_wait_ercd;
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_ch) || (NULL == p_info_drv) || (NULL == p_aio))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (0U == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL;
+        }
+        
+        if (ESUCCESS == ercd)
+        {
+            if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT;
+            }
+        }
+        
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            else
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT;
+                }
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                if (O_WRONLY == (p_info_ch->open_flags & O_ACCMODE))
+                {
+                    ercd = EACCES;
+                }
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                
+                if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                {
+                    ercd = EACCES;
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+#if defined (__ICCARM__)
+                    was_masked = __disable_irq_iar();
+#else
+                    was_masked = __disable_irq();
+#endif
+
+                    if (ESUCCESS != p_info_ch->err_stat_backup)
+                    {
+                        /* set error code */
+                        ercd = p_info_ch->err_stat_backup;
+                    }
+                    else
+                    {
+                        switch (p_info_ch->ch_stat)
+                        {
+                            case SCUX_CH_UNINIT :
+                                /* fall through */
+                            case SCUX_CH_INIT :
+                                ercd = EFAULT;
+                            break;              
+                            
+                            case SCUX_CH_STOP :
+                                ercd = EBADF;
+                            break;                          
+                            
+                            case SCUX_CH_TRANS_IDLE :
+                                ercd = SCUX_CopyReadStart(p_info_ch, p_aio);
+                            break;
+                            
+                            case SCUX_CH_TRANS_RD :
+                                ahf_addtail(&p_info_ch->rx_que, p_aio);
+                            break;
+                            
+                            case SCUX_CH_TRANS_WR :
+                                ercd = SCUX_CopyReadStart(p_info_ch, p_aio);
+                            break;
+                            
+                            case SCUX_CH_TRANS_RDWR :
+                                /* fall through */
+                            case SCUX_CH_STOP_WAIT :
+                                ahf_addtail(&p_info_ch->rx_que, p_aio);
+                            break;
+                            
+                            case SCUX_CH_STOP_WAIT_IDLE :
+                                ercd = SCUX_CopyReadStart(p_info_ch, p_aio);
+                            break;                        
+                            
+                            default :
+                                ercd = EFAULT;
+                            break;
+                        }
+                    }                 
+                    
+                    if (0 == was_masked)
+                    {
+                        __enable_irq();
+                    }
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+        }
+    }
+    
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_ReadAsync
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Cancel
+* @brief         Request cancel.
+*
+*                Description:<br>
+*                
+* @param[in]     p_fd   :channel handle which was returned by R_SCUX_open
+* @param[in]     p_aio  :aio control block.
+* @param[in,out] p_errno:pointer of error code
+*                               error code -
+*                               EFAULT : Internal error is occured.
+*                               
+* @retval        ESUCCESS -
+*                  Operation successful.
+*                EERROR -
+*                  Error occured.
+******************************************************************************/
+static int_t R_SCUX_Cancel(void * const p_fd, AIOCB * const p_aio, int32_t * const p_errno)
+{
+    int_t retval = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus sem_ercd;
+    int32_t sem_wait_ercd;
+    scux_info_ch_t * const p_info_ch = p_fd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_ch) || (NULL == p_info_drv))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SCUX_DRV_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT;
+        }
+    
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 1.2 It is confirming in advance whether to be NULL or not. */
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_ch->sem_ch_scux_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* <-MISRA 1.2 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+            
+            if (ESUCCESS == ercd)
+            {
+                if (false == p_info_ch->enabled)
+                {
+                    ercd = EFAULT;
+                }
+                
+                if (ESUCCESS == ercd)
+                {
+                    if ((SCUX_CH_INIT == p_info_ch->ch_stat) ||
+                        (SCUX_CH_UNINIT == p_info_ch->ch_stat))
+                    {
+                        /* It should not becomde status */
+                        ercd = EFAULT;
+                    }
+                    else if ((SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) ||
+                              (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat) ||
+                              (SCUX_CH_STOP == p_info_ch->ch_stat))
+                    {
+                        /* busy error on flush waiting */
+                        ercd = EBADF;
+                    }
+                    else
+                    {
+                        if (NULL == p_aio)
+                        {
+                            if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                            {
+                                ercd = SCUX_DirectCancelAll(p_info_ch);
+                            }
+                            else
+                            {
+                                ercd = SCUX_CopyCancelAll(p_info_ch);   
+                            }
+                        }
+                        else
+                        {
+                            if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                            {
+                                ercd = SCUX_DirectCancelSpecific(p_info_ch, p_aio);
+                            }
+                            else
+                            {
+                                ercd = SCUX_CopyCancelSpecific(p_info_ch, p_aio);
+                            }
+                        }
+                    }
+                }
+            }
+            sem_ercd = osSemaphoreRelease(p_info_ch->sem_ch_scux_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set error return value */
+                ercd = EFAULT;
+            }
+        }
+    }
+    
+    if (ESUCCESS != ercd)
+    {
+        retval = EERROR;
+    }
+    SCUX_SetErrCode(ercd, p_errno);
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function R_SCUX_Cancel
+******************************************************************************/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/scux/scux_int.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,888 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_int.c
+* $Rev: 993 $
+* $Date:: 2014-07-22 09:54:45 +0900#$
+* @brief        SCUX Driver interrupt functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "scux.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static void R_SCUX_Fdi0InterruptHandler(void);
+static void R_SCUX_Fdi1InterruptHandler(void);
+static void R_SCUX_Fdi2InterruptHandler(void);
+static void R_SCUX_Fdi3InterruptHandler(void);
+static void R_SCUX_FdiHandlerProcess(const scux_ch_num_t channel);
+
+static void R_SCUX_Fui0InterruptHandler(void);
+static void R_SCUX_Fui1InterruptHandler(void);
+static void R_SCUX_Fui2InterruptHandler(void);
+static void R_SCUX_Fui3InterruptHandler(void);
+static void R_SCUX_FuiHandlerProcess(const scux_ch_num_t channel);
+
+static void R_SCUX_Dvi0InterruptHandler(void);
+static void R_SCUX_Dvi1InterruptHandler(void);
+static void R_SCUX_Dvi2InterruptHandler(void);
+static void R_SCUX_Dvi3InterruptHandler(void);
+static void R_SCUX_DviHandlerProcess(const scux_ch_num_t channel);
+
+static void R_SCUX_Ai0InterruptHandler(void);
+static void R_SCUX_Ai1InterruptHandler(void);
+static void R_SCUX_AiHandlerProcess(const uint32_t src_channel);
+
+static void R_SCUX_ErrHandlerProcess(scux_info_ch_t * const p_scux_info_ch, const int_t ercd);
+
+/**************************************************************************//**
+* Function Name: SCUX_InterruptInit
+* @brief         Initialize SCUX interrupts.
+*
+*                Description:<br>
+*                
+* @param[in] channel : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_InterruptInit(const int_t channel)
+{
+    uint32_t int_type;
+    uint32_t ercd;
+    scux_info_ch_t * const p_scux_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    /* interrupt information table define */
+    static const scux_info_int_t scux_int_info[SCUX_CH_NUM][SCUX_INT_MAX] = 
+    {
+        {                                                                 /* ch0 */
+            {&R_SCUX_Fdi0InterruptHandler, SCUFDI0_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui0InterruptHandler, SCUFUI0_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi0InterruptHandler, SCUDVI0_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai0InterruptHandler,  SCUAI0_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        },
+        {                                                                 /* ch1 */
+            {&R_SCUX_Fdi1InterruptHandler, SCUFDI1_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui1InterruptHandler, SCUFUI1_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi1InterruptHandler, SCUDVI1_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai0InterruptHandler,  SCUAI0_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        },
+        {                                                                 /* ch2 */
+            {&R_SCUX_Fdi2InterruptHandler, SCUFDI2_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui2InterruptHandler, SCUFUI2_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi2InterruptHandler, SCUDVI2_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai1InterruptHandler,  SCUAI1_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        },
+        {                                                                 /* ch3 */
+            {&R_SCUX_Fdi3InterruptHandler, SCUFDI3_IRQn, SCUX_INT_LEVEL}, /* FDI */
+            {&R_SCUX_Fui3InterruptHandler, SCUFUI3_IRQn, SCUX_INT_LEVEL}, /* FUI */
+            {&R_SCUX_Dvi3InterruptHandler, SCUDVI3_IRQn, SCUX_INT_LEVEL}, /* DVI */
+            {&R_SCUX_Ai1InterruptHandler,  SCUAI1_IRQn,  SCUX_INT_LEVEL}  /* AI */
+        }
+    };
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (int_type = SCUX_INT_FDI; int_type < SCUX_INT_MAX; int_type++)
+        {
+            ercd = InterruptHandlerRegister(scux_int_info[channel][int_type].int_num,
+                                     scux_int_info[channel][int_type].int_handler
+                                     );
+                                     
+            if (0U != ercd)
+            {
+                /* NON_NOTICE_ASSERT: interrupt handler regist error */
+            }
+                                     
+            /* set interrupt level (1-N model) */
+            GIC_SetLevelModel(scux_int_info[channel][int_type].int_num, 
+                              (int8_t)scux_int_info[channel][int_type].info_level, 
+                              1
+                              );
+            
+            /* set interrupt priority */
+            GIC_SetPriority(scux_int_info[channel][int_type].int_num, p_scux_info_ch->int_level);
+            
+            /* get interrupt number */
+            p_scux_info_ch->int_num[int_type] = scux_int_info[channel][int_type].int_num;
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_InterrptInit
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_InterruptUntinit
+* @brief         Uninitialize SCUX interrupts.
+*
+*                Description:<br>
+*                
+* @param[in/out] channel : SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_InterruptUninit(const int_t channel)
+{
+    uint32_t int_type;
+    uint32_t ercd;
+    scux_info_ch_t * const p_scux_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        for (int_type = SCUX_INT_FDI; int_type < SCUX_INT_MAX; int_type++)
+        {
+            GIC_DisableIRQ(p_scux_info_ch->int_num[int_type]);
+            ercd = InterruptHandlerUnregister(p_scux_info_ch->int_num[int_type]);
+            
+            if (0U != ercd)
+            {
+                /* NON_NOTICE_ASSERT: interrupt handler unregist error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_InterruptUnInit
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi0InterruptHandler
+* @brief         FDI interrupt handler on channel 0.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi0InterruptHandler(void)
+{
+    
+    R_SCUX_FdiHandlerProcess(SCUX_CH_0);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi1InterruptHandler
+* @brief         FDI interrupt handler on channel 1.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi1InterruptHandler(void)
+{
+    
+    R_SCUX_FdiHandlerProcess(SCUX_CH_1);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi2InterruptHandler
+* @brief         FDI interrupt handler on channel 2.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi2InterruptHandler(void)
+{
+    
+    R_SCUX_FdiHandlerProcess(SCUX_CH_2);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi2InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fdi3InterruptHandler
+* @brief         FDI interrupt handler on channel 3.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fdi3InterruptHandler(void)
+{
+    
+    R_SCUX_FdiHandlerProcess(SCUX_CH_3);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fdi3InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_FdiHandlerProcess
+* @brief         Processing FDI interrupt handler.
+*
+*                Description:<br>
+*                
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_FdiHandlerProcess(const scux_ch_num_t channel)
+{   
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo((int_t)channel);
+    int_t ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* check error type */
+        if ((p_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 & DEVCR_FFD0_DEVCOL_MASK) != 0)
+        {
+            /* critical error (over lap) */
+            ercd = EIO;
+        }
+        else
+        {
+            /* be returned error (FFD under flow, over flow) */
+            ercd = EOVERFLOW;
+        }
+        
+        p_info_ch->p_scux_reg->p_ffd_reg->DEVCR_FFD0_0 &= ~(DEVCR_FFD0_DEVCUF_SET | 
+                                                            DEVCR_FFD0_DEVCOF_SET | 
+                                                            DEVCR_FFD0_DEVCOL_SET | 
+                                                            DEVCR_FFD0_DEVCIUF_SET);
+                                                            
+        R_SCUX_ErrHandlerProcess(p_info_ch, ercd);
+    }
+
+}
+
+/******************************************************************************
+End of function R_SCUX_FdiHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui0InterruptHandler
+* @brief         FUI interrupt handler on channel 0.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui0InterruptHandler(void)
+{
+    
+    R_SCUX_FuiHandlerProcess(SCUX_CH_0);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui1InterruptHandler
+* @brief         FUI interrupt handler on channel 1.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui1InterruptHandler(void)
+{
+    
+    R_SCUX_FuiHandlerProcess(SCUX_CH_1);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui2InterruptHandler
+* @brief         FUI interrupt handler on channel 2.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui2InterruptHandler(void)
+{
+    
+    R_SCUX_FuiHandlerProcess(SCUX_CH_2);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui2InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Fui3InterruptHandler
+* @brief         FUI interrupt handler on channel 3.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Fui3InterruptHandler(void)
+{
+    
+    R_SCUX_FuiHandlerProcess(SCUX_CH_3);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Fui3InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_FuiHandlerProcess
+* @brief         Processing FUI interrupt handler.
+*
+*                Description:<br>
+*                
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_FuiHandlerProcess(const scux_ch_num_t channel)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo((int_t)channel);
+    int_t ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        /* check error type */
+        if ((p_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 & UEVCR_FFU0_UEVCOL_MASK) != 0)
+        {
+            /* critical error (over lap) */
+            ercd = EIO;
+        }
+        else
+        {
+            /* be returned error (FFU under flow, over flow) */
+            ercd = EOVERFLOW;
+        }
+        
+        p_info_ch->p_scux_reg->p_ffu_reg->UEVCR_FFU0_0 &= ~(UEVCR_FFU0_UEVCUF_SET | 
+                                                            UEVCR_FFU0_UEVCOF_SET | 
+                                                            UEVCR_FFU0_UEVCOL_SET);
+                                                                
+        R_SCUX_ErrHandlerProcess(p_info_ch, ercd);
+
+    }
+
+}
+
+/******************************************************************************
+End of function R_SCUX_FuiHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi0InterruptHandler
+* @brief         DVI interrupt handler on channel 0.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi0InterruptHandler(void)
+{
+    
+    R_SCUX_DviHandlerProcess(SCUX_CH_0);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi1InterruptHandler
+* @brief         DVI interrupt handler on channel 1.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi1InterruptHandler(void)
+{
+    
+    R_SCUX_DviHandlerProcess(SCUX_CH_1);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi2InterruptHandler
+* @brief         DVI interrupt handler on channel 2.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi2InterruptHandler(void)
+{
+    
+    R_SCUX_DviHandlerProcess(SCUX_CH_2);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi2InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Dvi3InterruptHandler
+* @brief         DVI interrupt handler on channel 3.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Dvi3InterruptHandler(void)
+{
+    
+    R_SCUX_DviHandlerProcess(SCUX_CH_3);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Dvi3InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_DviHandlerProcess
+* @brief         Processing DVI interrupt handler.
+*
+*                Description:<br>
+*                
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_DviHandlerProcess(const scux_ch_num_t channel)
+{
+    uint32_t stat_zerocross;
+    int_t    ch_zerocross;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo((int_t)channel);
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        stat_zerocross = p_info_ch->p_scux_reg->p_dvu_reg->VEVCR_DVU0_0;
+        
+        for (ch_zerocross = 0; ch_zerocross <= p_info_ch->src_cfg.use_ch; ch_zerocross++)
+        {
+            /* check zerocross bit */
+            if (0U != (stat_zerocross & (VEVCR_DVU0_VEVCZCM_SET << ch_zerocross)))
+            {
+                p_info_ch->dvu_mute_stat |= (1U << ch_zerocross);
+                if (NULL != p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[ch_zerocross])
+                {
+                    /* callback function */
+                    p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[ch_zerocross]();
+                }
+            }
+            p_info_ch->p_scux_reg->p_dvu_reg->VEVCR_DVU0_0 &= ~stat_zerocross;
+        }
+    }
+
+}
+
+/******************************************************************************
+End of function R_SCUX_DviHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Ai0InterruptHandler
+* @brief         AI interrupt handler on channel 0.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Ai0InterruptHandler(void)
+{
+    
+    R_SCUX_AiHandlerProcess(SRC_MOD_SRC0);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Ai0InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_Ai1InterruptHandler
+* @brief         AI interrupt handler on channel 1.
+*
+*                Description:<br>
+*                
+* @param         None.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_Ai1InterruptHandler(void)
+{
+    
+    R_SCUX_AiHandlerProcess(SRC_MOD_SRC1);
+    
+}
+
+/******************************************************************************
+End of function R_SCUX_Ai1InterruptHandler
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_AiHandlerProcess
+* @brief         Processing AI interrupt handler.
+*
+*                Description:<br>
+*                
+* @param[in] channel:SCUX channel number.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_AiHandlerProcess(const uint32_t src_channel)
+{
+    scux_info_ch_t *p_info_ch_check;
+    scux_info_ch_t *p_info_ch;
+
+    if (SRC_MOD_SRC0 == src_channel)
+    {
+        p_info_ch_check = SCUX_GetDrvChInfo(SCUX_CH_0);
+        if (NULL == p_info_ch_check)
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        else
+        {
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0)
+            {
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_0);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET | 
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW);
+                }
+            }
+            
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0)
+            {
+                
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_1);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET | 
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */                                                      
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW);
+                }
+            }
+        }
+    }
+    else
+    {
+        p_info_ch_check = SCUX_GetDrvChInfo(SCUX_CH_2);
+        if (NULL == p_info_ch_check)
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        else
+        {
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0)
+            {
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_2);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR0_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET | 
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */                                                       
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW);
+                }
+            }
+            
+            if (0U != p_info_ch_check->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0)
+            {
+                
+                p_info_ch = SCUX_GetDrvChInfo(SCUX_CH_3);
+                if (NULL == p_info_ch)
+                {
+                    /* NON_NOTICE_ASSERT: NULL pointer */
+                }
+                else
+                {
+                    p_info_ch->p_scux_reg->p_src_reg->SEVCR1_2SRC0_0 &= ~(SEVCR_2SRC0_EVCUF_SET | 
+                                                                          SEVCR_2SRC0_EVCOF_SET);
+                    /* be returned error (FFU under flow, over flow) */                                                       
+                    R_SCUX_ErrHandlerProcess(p_info_ch, EOVERFLOW);
+                }
+            }
+        }
+    }
+}
+
+/******************************************************************************
+End of function R_SCUX_AiHandlerProcess
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_ErrHandlerProcess
+* @brief         Error processing on interrupt handler.
+*
+*                Description:<br>
+*                
+* @param[in] p_scux_info_ch:SCUX channel information.
+* @param[in] ercd:return error code.
+* @retval        None.
+******************************************************************************/
+
+static void R_SCUX_ErrHandlerProcess(scux_info_ch_t * const p_scux_info_ch, const int_t ercd)
+{
+    int_t retval;
+    int_t dma_retval;
+    scux_stat_ch_t old_stat;
+    uint32_t tx_remain_size = 0;
+    uint32_t rx_remain_size = 0;
+
+    if (NULL == p_scux_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        retval = R_DMA_Cancel(p_scux_info_ch->dma_tx_ch, &tx_remain_size, &dma_retval);
+        /* DMA stop check, (when dma_retval is EBADF, DMA stopped already) */
+        if ((ESUCCESS != retval) && (EBADF != dma_retval))
+        {
+            /* NON_NOTICE_ASSERT: NULL pointer */
+        }
+        else
+        {
+            p_scux_info_ch->tx_fifo_total_size += p_scux_info_ch->dma_tx_current_size;
+            p_scux_info_ch->dma_tx_current_size = 0;
+        }
+        
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            retval = R_DMA_Cancel(p_scux_info_ch->dma_rx_ch, &rx_remain_size, &dma_retval);
+
+            /* DMA stop check, (when dma_retval is EBADF, DMA stopped already) */
+            if ((ESUCCESS != retval) && (EBADF != dma_retval))
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+            else
+            {
+                p_scux_info_ch->rx_fifo_total_size += p_scux_info_ch->dma_rx_current_size;
+                p_scux_info_ch->dma_rx_current_size = 0;
+            }
+            
+            retval = R_DMA_Free(p_scux_info_ch->dma_rx_ch, NULL);
+            
+            if (ESUCCESS != retval)
+            {
+                /* NON_NOTICE_ASSERT: NULL pointer */
+            }
+        }
+        
+        SCUX_AdjustAccessFifo(p_scux_info_ch, tx_remain_size, rx_remain_size);
+        /* stop HW */
+        if (false != p_scux_info_ch->src_cfg.mode_sync)
+        {
+            SCUX_SyncStopHw(p_scux_info_ch);
+        }
+        else
+        {
+            SCUX_AsyncStopHw(p_scux_info_ch);
+        }
+
+        if (false == p_scux_info_ch->first_tx_flag)
+        {
+            /* return callback on normal operation */
+            if (NULL != p_scux_info_ch->p_tx_aio)
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);
+            }
+            if (NULL != p_scux_info_ch->p_tx_next_aio)
+            {
+                if (NULL == p_scux_info_ch->p_tx_aio)
+                {
+                    p_scux_info_ch->p_tx_next_aio->aio_return = ercd;
+                }
+                else
+                {
+                    p_scux_info_ch->p_tx_next_aio->aio_return = ECANCELED;
+                }
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_next_aio);
+            }
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+        }
+        else
+        {
+            /* return callback on first operation */
+            if (NULL != p_scux_info_ch->p_tx_next_aio)
+            {
+                p_scux_info_ch->p_tx_next_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_next_aio);
+            }
+            else
+            {
+                p_scux_info_ch->p_tx_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->tx_que, p_scux_info_ch->p_tx_aio);                
+            }
+            ahf_cancelall(&p_scux_info_ch->tx_que);
+            p_scux_info_ch->p_tx_aio = NULL;
+            p_scux_info_ch->p_tx_next_aio = NULL;
+        }
+        
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_scux_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* if request is nothing, aio is NULL */
+            if (NULL != p_scux_info_ch->p_rx_aio)
+            {
+                p_scux_info_ch->p_rx_aio->aio_return = ercd;
+                ahf_complete(&p_scux_info_ch->rx_que, p_scux_info_ch->p_rx_aio);
+            }
+            ahf_cancelall(&p_scux_info_ch->rx_que);
+            p_scux_info_ch->p_rx_aio = NULL;
+        }
+        old_stat = p_scux_info_ch->ch_stat;
+        p_scux_info_ch->ch_stat = SCUX_CH_STOP;
+        if ((SCUX_CH_STOP_WAIT == old_stat) || (SCUX_CH_STOP_WAIT_IDLE == old_stat))
+        {
+            if (NULL != p_scux_info_ch->p_flush_callback)
+            {
+                p_scux_info_ch->p_flush_callback(ercd);
+            }
+        }
+        
+        /* set error status */
+        p_scux_info_ch->err_stat_backup = ercd;
+    }
+}
+
+/******************************************************************************
+End of function R_SCUX_ErrHandlerProcess
+******************************************************************************/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/scux/scux_int.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          scux_int.h
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* @brief         SCUX driver interrupt header
+******************************************************************************/
+
+#ifndef SCUX_INT_H
+#define SCUX_INT_H
+
+/******************************************************************************
+Includes <System Includes>, "Project Includes"
+******************************************************************************/
+
+#include "scux.h" 
+#include "Renesas_RZ_A1.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/* Interrupt types */
+typedef enum
+{
+    SCUX_INT_FDI  = 0,   /* FDI interrupt */
+    SCUX_INT_FUI  = 1,   /* FUI interrupt */
+    SCUX_INT_DVI  = 2,   /* DVI interrupt */
+    SCUX_INT_AI   = 3,   /* AI interrupt */
+    SCUX_INT_MAX  = 4
+} scux_int_type_t;
+
+/* Interrupt level */
+typedef enum
+{
+    SCUX_INT_LEVEL = 0,   /* Level interrupt */
+    SCUX_INT_EDGE  = 1    /* Edge interrupt */
+} scux_int_leve_t;
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+/* Table Information of Interrupt */
+typedef struct
+{
+    IRQHandler       int_handler;          /* Interrupt handler */
+    IRQn_Type        int_num;              /* Interrupt number */
+    scux_int_leve_t  info_level;           /* Edge or level  */
+} scux_info_int_t;
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+
+void SCUX_InterruptInit(const int_t channel);
+void SCUX_InterruptUninit(const int_t channel);
+
+#endif /* SCUX_INT_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/scux/scux_ioctl.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,2584 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         scux_ioctl.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* @brief        SCUX Driver ioctl functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+
+#include "scux.h"
+#include "bsp_util.h"
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global driver management information
+******************************************************************************/
+
+/******************************************************************************
+ Function prototypes
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlTransStart
+* @brief         SCUX transfer start.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     p_scux_addr_param:address parameter.
+* @retval        ESUCCESS : Operation successful.
+*                EACCES : DVU setup isn't carried out when using DVU.
+*                EACCES : MIX setup isn't carried out when using MIX.
+*                EACCES : SSIF setup isn't carried out when using SSIF.
+*                EACCES : SSIF channel is already used.
+*                EACCES : When use MIX, it is a setup which does not agree in a route setup. 
+*                EBUSY : It has already transmitted.
+*                EMFILE : Allocate DMA ch for read is failed.
+*                EPERM : Transfer parameter is unexpected.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O0
+#endif
+#endif /* end mbed */
+int_t SCUX_IoctlTransStart(const int_t channel)
+{
+    int32_t          sem_wait_ercd;
+    int_t            retval = ESUCCESS;
+    uint32_t         ssif_sem_ch = 0;
+    int_t            was_masked;
+    int_t            ssif_ch;
+    osStatus         sem_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+    scux_ssif_info_t  * p_ssif_ch_num[SCUX_SSIF_CH_NUM];
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+
+    /* for processing for the measure against MISRA R1.1 and IPA R3.2.2 */
+    for (ssif_ch = 0; ssif_ch < SCUX_SSIF_CH_NUM; ssif_ch++)
+    {
+        p_ssif_ch_num[ssif_ch] = SCUX_GetSsifChInfo(ssif_ch);
+    }
+    if ((NULL == p_info_drv) || (NULL == p_info_ch)) 
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* check using MIX route */
+        if (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+            sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT;
+            }
+        }
+
+        if ((SCUX_ROUTE_SSIF == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)) || 
+            (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK)))
+        {
+            /* check using SSIF route */
+            /* mode is async mode only when SSIF direvct route */
+            p_info_ch->src_cfg.mode_sync = false;
+            switch (p_info_ch->route_set)
+            {
+                case SCUX_ROUTE_SRC0_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC1_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC2_MEM :
+                    /* fall through */
+                case SCUX_ROUTE_SRC3_MEM :
+                    /* NOTREACHED on At the time of a normal performance */
+                break;              
+                
+                case SCUX_ROUTE_SRC0_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC0_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC1_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC1_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC1_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC1_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC2_SSIF1 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC2_SSIF4 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC3_SSIF2 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;                
+                
+                case SCUX_ROUTE_SRC3_SSIF5 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;                
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC0_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+
+                case SCUX_ROUTE_SRC1_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC1_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC1_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC1_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC2_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC2_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC2_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC2_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;              
+                
+                case SCUX_ROUTE_SRC3_MIX_SSIF0 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                break;
+                
+                case SCUX_ROUTE_SRC3_MIX_SSIF012 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_0];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_0);
+                    }
+                     
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_1];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_1);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_2];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_2);
+                    }
+                break;                
+                
+                case SCUX_ROUTE_SRC3_MIX_SSIF3 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                break;
+    
+                case SCUX_ROUTE_SRC3_MIX_SSIF345 :
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_3];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_3);
+                    }
+                    
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_4];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_4);
+                    }
+                        
+                    p_ssif_ch = p_ssif_ch_num[SCUX_SSIF_CH_5];
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        ssif_sem_ch |= (1U << SCUX_SSIF_CH_5);
+                    }
+                break;
+                        
+                default :
+                    /* ->IPA R3.5.2 Nothing is being processed intentionally. */
+                    /* <-IPA R3.5.2 */
+                    /* NOTREACHED on At the time of a normal performance */
+                break;
+            }
+        }
+
+        if (ESUCCESS == retval)
+        {
+            retval = SCUX_CheckParam(p_info_ch);
+                
+            if (ESUCCESS == retval)
+            {
+#if defined (__ICCARM__)
+                was_masked = __disable_irq_iar();
+#else
+                was_masked = __disable_irq();
+#endif    
+                SCUX_InitHw(p_info_ch);
+                if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                {
+                    SCUX_SetupSsif(p_info_ch);
+                }
+                
+                SCUX_SetupSrc(p_info_ch);
+                if (SCUX_ROUTE_MEM_TO_MEM != (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+                {
+                    SCUX_SetupDvu(p_info_ch);
+                }
+                
+                retval = SCUX_SetupDma(p_info_ch);
+                
+                if (ESUCCESS == retval)
+                {
+                    if (false != p_info_ch->src_cfg.mode_sync)
+                    {
+                        SCUX_SyncStartHw(p_info_ch);
+                    }
+                    else
+                    {
+                        SCUX_AsyncStartHw(p_info_ch);
+                    }
+                    p_info_ch->ch_stat = SCUX_CH_TRANS_IDLE;
+                    p_info_ch->p_flush_callback = NULL;
+                    
+                    p_info_ch->dma_tx_current_size = 0;
+                    p_info_ch->dma_rx_current_size = 0;
+                    p_info_ch->tx_fifo_total_size = 0;
+                    p_info_ch->rx_fifo_total_size = 0;
+                    
+                    p_info_ch->p_tx_aio = NULL;
+                    p_info_ch->p_rx_aio = NULL;
+                    p_info_ch->p_tx_next_aio = NULL;
+                    p_info_ch->p_rx_next_aio = NULL;
+                    p_info_ch->dvu_mute_stat = 0;
+                    p_info_ch->first_ramp_flag = false;
+                    p_info_ch->cancel_operate_flag = false;
+                    p_info_ch->restart_ramp_flag = false;
+                    p_info_ch->err_stat_backup = ESUCCESS;
+                }
+                
+                if (0 == was_masked)
+                {
+                    __enable_irq();
+                }
+            }
+        }
+        
+        for (ssif_ch = 0; ssif_ch < SCUX_SSIF_CH_NUM; ssif_ch++)
+        {
+            if (0U != (ssif_sem_ch & (1U << ssif_ch)))
+            {
+                p_ssif_ch = p_ssif_ch_num[ssif_ch];
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                    p_info_ch->ch_stat = SCUX_CH_STOP;
+                }
+            }
+        }
+        
+        /* check using MIX route */
+        if (SCUX_ROUTE_MIX == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {
+            sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT;
+                p_info_ch->ch_stat = SCUX_CH_STOP;
+            }
+        }
+    }
+    
+    return retval;
+}
+#if(1) /* mbed */
+#if defined (__CC_ARM)
+#pragma O3
+#endif
+#endif /* end mbed */
+
+/******************************************************************************
+End of function SCUX_IoctlTransStart
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlFlushStop
+* @brief         Set flush stop paramter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     (*callback)(void):callback function pointer.
+* @param[in]     was_masked:interrupt enable information.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlFlushStop(const int_t channel, void (* const callback)(int_t), const int_t was_masked) 
+{
+    int_t retval = ESUCCESS;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if (NULL == p_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        {  
+            /* mem to mem route */
+            if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) || (SCUX_CH_TRANS_RD == p_info_ch->ch_stat))
+            {
+                /* Flush process is performed only when dummy buffer transmission has not been started yet */
+                if (false == p_info_ch->tx_dummy_run_flag)
+                {
+                    /* start flush write */
+                    retval = SCUX_FlushWriteStart(p_info_ch);
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    /* memory to memory route */
+                    if (SCUX_CH_TRANS_RD == p_info_ch->ch_stat)
+                    {
+                        p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                    }
+                    else
+                    {
+                        p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE;
+                    }
+                    p_info_ch->p_flush_callback = callback;
+                }
+            }
+            else
+            {
+                /* on going write process */
+                /* status is SCUX_CH_TRANS_WR, SCUX_CH_TRANS_RDWR, SCUX_CH_STOP_WAIT, SCUX_CH_STOP_WAIT_IDLE */
+                if (SCUX_CH_TRANS_RDWR == p_info_ch->ch_stat)
+                {
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                }
+                if (SCUX_CH_TRANS_WR == p_info_ch->ch_stat)
+                {
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT_IDLE;
+                }
+                
+                p_info_ch->p_flush_callback = callback;
+            }
+        }
+        else
+        {
+            /* SSIF direct route */
+            if (SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat)
+            {
+                /* Flush process is performed only when dummy buffer transmission has not been started yet */
+                if (false == p_info_ch->tx_dummy_run_flag)
+                {
+                    /* start flush write */
+                    retval = SCUX_FlushWriteStart(p_info_ch);
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    /* memory to memory route */
+                    p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                    p_info_ch->p_flush_callback = callback;
+                }
+            }
+            else
+            {
+                /* on going write process */
+                p_info_ch->ch_stat = SCUX_CH_STOP_WAIT;
+                p_info_ch->p_flush_callback = callback;
+                
+            }
+        }
+    }
+    
+    if (0 == was_masked)
+    {
+        /* enable all irq */
+        __enable_irq();
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlFlushStop
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlClearStop
+* @brief         Set flush stop paramter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @retval        ESUCCESS : Operation successful.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlClearStop(const int_t channel, const int_t was_masked) 
+{
+    int_t retval = ESUCCESS;
+    int_t dma_ercd;
+    int_t dma_retval;
+    scux_stat_ch_t old_stat;
+    uint32_t rx_remain_size = 0;
+    uint32_t tx_remain_size = 0;
+    
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    if (NULL == p_info_ch)
+    {
+        retval = EFAULT;
+        if (0 == was_masked)
+        {
+            /* enable all irq */
+            __enable_irq();
+        } 
+    }
+    else
+    {  
+        if (SCUX_ROUTE_MEM_TO_MEM == (p_info_ch->route_set & SCUX_GET_ROUTE_MASK))
+        { 
+            /* memory to memory route */
+            dma_retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+            /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+            if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+                p_info_ch->dma_tx_current_size = 0;
+            }
+             
+            dma_retval = R_DMA_Cancel(p_info_ch->dma_rx_ch, &rx_remain_size, &dma_ercd);
+            /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+            if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                p_info_ch->rx_fifo_total_size += p_info_ch->dma_rx_current_size;
+                p_info_ch->dma_rx_current_size = 0;
+                
+                dma_retval = R_DMA_Free(p_info_ch->dma_rx_ch, NULL);
+                if (ESUCCESS != dma_retval)
+                {
+                    retval = EFAULT;
+                }
+            }
+                        
+            if (ESUCCESS == retval)
+            {
+                /* return write request */
+                if (NULL !=  p_info_ch->p_tx_aio)
+                {
+                    p_info_ch->p_tx_aio->aio_return = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size);
+                    ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+                }
+                
+                /* return read request */
+                if (NULL != p_info_ch->p_rx_aio)
+                {
+                    p_info_ch->p_rx_aio->aio_return = (ssize_t)(p_info_ch->p_rx_aio->aio_nbytes - rx_remain_size);
+                    ahf_complete(&p_info_ch->rx_que, p_info_ch->p_rx_aio);
+                }   
+                               
+                ahf_cancelall(&p_info_ch->tx_que);
+                ahf_cancelall(&p_info_ch->rx_que);
+                
+                p_info_ch->p_tx_aio = NULL;
+                p_info_ch->p_rx_aio = NULL;
+            }
+        }
+        else
+        {
+            /* SSIF direct route */
+            dma_retval = R_DMA_Cancel(p_info_ch->dma_tx_ch, &tx_remain_size, &dma_ercd);
+            /* DMA stop check, (when dma_ercd is EBADF, DMA stopped already) */
+            if ((ESUCCESS != dma_retval) && (EBADF != dma_ercd))
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                p_info_ch->tx_fifo_total_size += p_info_ch->dma_tx_current_size;
+                p_info_ch->dma_tx_current_size = 0;
+            }
+            
+            if (ESUCCESS == retval) 
+            {
+                /* return the request after 2nd */
+                if (false == p_info_ch->first_tx_flag)
+                {
+                    /* return current aio request */
+                    if (NULL !=  p_info_ch->p_tx_aio)
+                    {
+                        p_info_ch->p_tx_aio->aio_return = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size);
+                        ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+                    }
+                    /* return next aio request */
+                    if (NULL != p_info_ch->p_tx_next_aio)
+                    {
+                        p_info_ch->p_tx_next_aio->aio_return = ECANCELED;
+                        ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio);
+                    }
+                }
+                else
+                {
+                    /* return the 1st request  */
+                    if (NULL == p_info_ch->p_tx_aio)
+                    {
+                        /* return the first half part of a 1st request */
+                        if (NULL != p_info_ch->p_tx_next_aio)
+                        {
+                            p_info_ch->p_tx_next_aio->aio_return 
+                            = (ssize_t)((p_info_ch->p_tx_next_aio->aio_nbytes / SCUX_HALF_SIZE_VALUE) - tx_remain_size);
+                            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio);
+                        }
+                    }
+                    else
+                    {
+                        /* return the second half part of a 1st request */
+                        p_info_ch->p_tx_aio->aio_return 
+                        = (ssize_t)(p_info_ch->p_tx_aio->aio_nbytes - tx_remain_size);
+                        ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_aio);
+                         
+                        /* in case of the next request is acquired */
+                        if (NULL != p_info_ch->p_tx_next_aio)
+                        {
+                            p_info_ch->p_tx_next_aio->aio_return = ECANCELED;
+                            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_tx_next_aio);
+                        }
+                    }
+                }
+                ahf_cancelall(&p_info_ch->tx_que);
+                
+                p_info_ch->p_tx_aio = NULL;
+                p_info_ch->p_tx_next_aio = NULL;
+            }   
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            SCUX_AdjustAccessFifo(p_info_ch, tx_remain_size, rx_remain_size);
+            if (false != p_info_ch->src_cfg.mode_sync)
+            {
+                SCUX_SyncStopHw(p_info_ch);
+            }
+            else
+            {
+                SCUX_AsyncStopHw(p_info_ch);
+            }
+            
+            old_stat = p_info_ch->ch_stat;
+            p_info_ch->ch_stat = SCUX_CH_STOP;
+            
+            if (0 == was_masked)
+            {
+                /* enable all irq */
+                __enable_irq();
+            } 
+            
+            if ((SCUX_CH_STOP_WAIT == old_stat) || (SCUX_CH_STOP_WAIT_IDLE == old_stat))
+            {         
+                p_info_ch->p_flush_callback(ECANCELED);
+                p_info_ch->p_flush_callback = NULL;
+            }
+        }
+        else
+        {
+            if (0 == was_masked)
+            {
+                /* enable all irq */
+                __enable_irq();
+            } 
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlClearStop
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetRoute
+* @brief         Set SCUX data transfer route.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     route:route parameter.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlSetRoute(const int_t channel, const scux_route_t route) 
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->route_set = route;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetRoute
+******************************************************************************/
+
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetPinClk
+* @brief         Set clock source for AUDIO_CLK pin.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_pin_clk_param:clock source parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EFAULT:Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetPinClk(const int_t channel, const scux_ssif_pin_clk_t * const p_pin_clk_param) 
+{
+    int_t retval = ESUCCESS;
+    int32_t  sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_drv) || (NULL == p_info_ch) || (NULL == p_pin_clk_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* check SSIF channel number */
+        if (SCUX_SSIF_CH_NUM > p_pin_clk_param->ssif_ch_num)
+        {
+            p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_pin_clk_param->ssif_ch_num);
+            if (NULL == p_ssif_ch)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+                else
+                {
+                    /* check clock source parameter */
+                    if ((SCUX_CLK_AUDIO_CLK == p_pin_clk_param->pin_clk) || (SCUX_CLK_MLB_CLK == p_pin_clk_param->pin_clk))
+                    {
+                        p_ssif_ch->pin_clk = p_pin_clk_param->pin_clk;
+                    }
+                    else
+                    {
+                        retval = EPERM;
+                    }
+                }
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        if (SCUX_CLK_MLB_CLK == p_pin_clk_param->pin_clk)
+                        {
+                            /* set MLB_CLK */
+                            *(p_info_ch->p_scux_reg->ssipmd_cim) |= (SSIPMD_CIM_SSI0CKS_SET << p_pin_clk_param->ssif_ch_num);
+                        }
+                        else
+                        {
+                            /* set AUDIO_CLK */
+                            *(p_info_ch->p_scux_reg->ssipmd_cim) &= ~(SSIPMD_CIM_SSI0CKS_SET << p_pin_clk_param->ssif_ch_num);
+                        }
+                    }
+                    
+                    sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+                    /* semaphore error check */
+                    if (osOK != sem_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                }
+            }
+        }
+        else
+        {
+            retval = EPERM;
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetPinClk
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetPinMode
+* @brief         Set synchronous setting for each SSIP pin.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_pin_mode_param:synchronous setting parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EFAUT:Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetPinMode(const int_t channel, const scux_ssif_pin_mode_t * const p_pin_mode_param) 
+{
+    int_t retval = ESUCCESS;
+    uint32_t ssipmd_reg;
+    uint32_t ssipmd_mask = 0;
+    uint32_t ssipmd_shift = 0;
+    osStatus sem_ercd;
+    int32_t  sem_wait_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_drv) || (NULL == p_info_ch) || (NULL == p_pin_mode_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* check SSIF channel number (disable setting for SSIF0) */
+        if (SCUX_SSIF_CH_NUM > p_pin_mode_param->ssif_ch_num)
+        {
+            p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_pin_mode_param->ssif_ch_num);
+            if (NULL == p_ssif_ch)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+                else
+                {
+                    /* check clock source parameter */
+                    if ((SCUX_PIN_MODE_MIN < p_pin_mode_param->pin_mode) || (SCUX_PIN_MODE_MAX > p_pin_mode_param->pin_mode))
+                    {
+                        p_ssif_ch->pin_mode = p_pin_mode_param->pin_mode;
+                    }
+                    else
+                    {
+                        retval = EPERM;
+                    }
+                }
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+                
+                if (ESUCCESS == retval)
+                {
+                    /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                    sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+                    /* <-MISRA 10.6 */
+                    /* semaphore error check */
+                    if ((-1) == sem_wait_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                    else
+                    {
+                        /* pin_mode setup to SSIF0 does not exist */
+                        if (SCUX_SSIF_CH_0 != p_pin_mode_param->ssif_ch_num)
+                        {
+                            switch (p_pin_mode_param->ssif_ch_num)
+                            {
+                                case SCUX_SSIF_CH_1 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI1PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI1PMD_SHIFT;
+                                break;
+                                
+                                case SCUX_SSIF_CH_2 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI2PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI2PMD_SHIFT;
+                                break;
+            
+                                case SCUX_SSIF_CH_3 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI3PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI3PMD_SHIFT;
+                                break;
+            
+                                case SCUX_SSIF_CH_4 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI4PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI4PMD_SHIFT;
+                                break;
+                                
+                                case SCUX_SSIF_CH_5 :
+                                    ssipmd_mask = SSIPMD_CIM_SSI5PMD_MASK;
+                                    ssipmd_shift = SSIPMD_CIM_SSI5PMD_SHIFT;
+                                break;                  
+                            
+                                default :
+                                    /* SCUX channel is 6 oe more */
+                                    retval = EPERM;
+                                break;
+                            }
+                        
+                            if (ESUCCESS == retval)
+                            {
+                                ssipmd_reg = *(p_info_ch->p_scux_reg->ssipmd_cim);
+                                ssipmd_reg &= ~ssipmd_mask;
+                            
+                                /* ->IPA R2.4.1 Even if pinmode and ssipmd_shift are max value, omission dose not occur. */
+                                *(p_info_ch->p_scux_reg->ssipmd_cim) = (ssipmd_reg | ((uint32_t)p_pin_mode_param->pin_mode << ssipmd_shift));
+                                /* <-IPA R2.4.1 */
+                            }
+                        }
+                    }
+                    
+                    sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+                    /* semaphore error check */
+                    if (osOK != sem_ercd)
+                    {
+                        /* set semaphore error */
+                        retval = EFAULT;
+                    }
+                }
+            }
+        }
+        else
+        {
+            retval = EPERM;
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetPinMode
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetSrcCfg
+* @brief         Set SRC paramter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_src_param:SRC parameter.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlSetSrcCfg(const int_t channel, const scux_src_cfg_t * const p_src_param)
+{
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_src_param))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->src_cfg.src_enable = p_src_param->src_enable;
+        p_info_ch->src_cfg.use_ch = p_src_param->use_ch;
+        p_info_ch->src_cfg.word_len = p_src_param->word_len;
+        p_info_ch->src_cfg.mode_sync = p_src_param->mode_sync;
+        p_info_ch->src_cfg.input_rate_sync = p_src_param->input_rate_sync;
+        p_info_ch->src_cfg.input_clk_async = p_src_param->input_clk_async;
+        p_info_ch->src_cfg.input_div_async = p_src_param->input_div_async;
+        p_info_ch->src_cfg.output_rate_sync = p_src_param->output_rate_sync;
+        p_info_ch->src_cfg.output_clk_async = p_src_param->output_clk_async;
+        p_info_ch->src_cfg.output_div_async = p_src_param->output_div_async;
+        p_info_ch->src_cfg.delay_mode = p_src_param->delay_mode;
+        p_info_ch->src_cfg.wait_sample = p_src_param->wait_sample;
+        p_info_ch->src_cfg.min_rate_percentage = p_src_param->min_rate_percentage;
+        p_info_ch->src_cfg.output_ws = p_src_param->output_ws;
+        p_info_ch->src_cfg.input_ws = p_src_param->input_ws;
+        p_info_ch->src_cfg.freq_tioc3a = p_src_param->freq_tioc3a;
+        p_info_ch->src_cfg.freq_tioc4a = p_src_param->freq_tioc4a;
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->src_cfg.select_in_data_ch[audio_ch] = p_src_param->select_in_data_ch[audio_ch];
+        }
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetSrcCfg
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuCfg
+* @brief         Set DVU parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_param:DVU parameter.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlSetDvuCfg(const int_t channel, const scux_dvu_cfg_t * const p_dvu_param)
+{
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_dvu_param))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        p_info_ch->dvu_cfg.dvu_enable = p_dvu_param->dvu_enable;
+            
+        /* digital volume setting */
+        p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable = p_dvu_param->dvu_digi_vol.digi_vol_enable;
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch] = p_dvu_param->dvu_digi_vol.digi_vol[audio_ch];
+        }
+        
+        /* ramp volume setting */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch] = p_dvu_param->dvu_ramp_vol.ramp_vol_enable[audio_ch];
+        }
+        p_info_ch->dvu_cfg.dvu_ramp_vol.up_period = p_dvu_param->dvu_ramp_vol.up_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.down_period = p_dvu_param->dvu_ramp_vol.down_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol = p_dvu_param->dvu_ramp_vol.ramp_vol;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time = p_dvu_param->dvu_ramp_vol.ramp_wait_time;
+        
+        /* zerocross mute setting */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch] = p_dvu_param->dvu_zc_mute.zc_mute_enable[audio_ch];
+            p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[audio_ch] = p_dvu_param->dvu_zc_mute.pcallback[audio_ch];
+        }
+        
+        p_info_ch->dvu_setup = true;
+    }
+    
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuCfg
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuDigiVol
+* @brief         Set Digital volume parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_param:Digital volume parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetDvuDigiVol(const int_t channel, const scux_dvu_digi_vol_t * const p_digi_vol_param)
+{
+    int_t retval = ESUCCESS;
+    int_t was_masked;
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_digi_vol_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* digital volume setting */
+        p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol_enable = p_digi_vol_param->digi_vol_enable;
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch] = p_digi_vol_param->digi_vol[audio_ch];
+        }
+        
+        /* check digital volume */
+        for (audio_ch = SCUX_AUDIO_CH_0; ((ESUCCESS == retval) && (audio_ch < p_info_ch->src_cfg.use_ch)); audio_ch++)
+        {
+            if (SCUX_MAX_DIGITAL_VOLUME < p_info_ch->dvu_cfg.dvu_digi_vol.digi_vol[audio_ch])
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif
+
+            if (SCUX_CH_STOP != p_info_ch->ch_stat) 
+            {
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+                
+                /* set parameter for register */
+                SCUX_SetDigiVolRegister(p_info_ch);
+                    
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+            }   
+        
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuDigiVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuRampVol
+* @brief         Set Digital volume parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_param:Digital volume parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetDvuRampVol(const int_t channel, const scux_dvu_ramp_vol_t * const p_ramp_vol_param)
+{
+    int_t retval = ESUCCESS;
+    int_t was_masked;
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_ramp_vol_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* ramp volume setting */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol_enable[audio_ch] = p_ramp_vol_param->ramp_vol_enable[audio_ch];
+        }
+        p_info_ch->dvu_cfg.dvu_ramp_vol.up_period = p_ramp_vol_param->up_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.down_period = p_ramp_vol_param->down_period;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol = p_ramp_vol_param->ramp_vol;
+        p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time = p_ramp_vol_param->ramp_wait_time;
+        
+        /* check ramp volume */
+        /* check ramp down period */
+        if ((p_info_ch->dvu_cfg.dvu_ramp_vol.down_period <= SCUX_DVU_TIME_MIN) ||
+            (p_info_ch->dvu_cfg.dvu_ramp_vol.down_period >= SCUX_DVU_TIME_MAX))
+        {
+               retval = EPERM;
+        }
+                
+        if (ESUCCESS == retval)
+        {
+            /* check ramp up period */
+            if ((p_info_ch->dvu_cfg.dvu_ramp_vol.up_period <= SCUX_DVU_TIME_MIN) ||
+                (p_info_ch->dvu_cfg.dvu_ramp_vol.up_period >= SCUX_DVU_TIME_MAX))
+            {
+                retval = EPERM;
+            }
+        }
+                
+        if (ESUCCESS == retval)
+        {
+            /* check ramp volume */
+            if (SCUX_MAX_RAMP_VOLUME < p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_vol)
+            {
+                retval = EPERM;
+            }
+        }
+                
+        if (ESUCCESS != retval)
+        {
+            /* check wait time */
+            if (SCUX_MAX_WAIT_TIME < p_info_ch->dvu_cfg.dvu_ramp_vol.ramp_wait_time)
+            {
+                retval = EPERM;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif
+
+            if ((SCUX_CH_STOP != p_info_ch->ch_stat) && (false != p_info_ch->first_ramp_flag))
+            {
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+                
+                /* set parameter for register */
+                SCUX_SetRampVolRegister(p_info_ch);
+                    
+                p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+            }   
+            
+            /* an updating setting is used when a seting is updated before the first request is going */
+            p_info_ch->restart_ramp_flag = false;
+            
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuRampVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetDvuZerocrossMute
+* @brief         Set zerocross mute parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_zc_mute_param:zerocross mute parameter.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EPERM:Rewrite callback pointer while waiting zerocross.
+******************************************************************************/
+
+int_t SCUX_IoctlSetDvuZerocrossMute(const int_t channel, const scux_zc_mute_t * const p_zc_mute_param)
+{
+    int_t retval = ESUCCESS;
+    int_t was_masked;
+    scux_audio_channel_t audio_ch;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_zc_mute_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* set zerocross mute paramter */
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_ch]= p_zc_mute_param->zc_mute_enable[audio_ch];
+            p_info_ch->dvu_cfg.dvu_zc_mute.pcallback[audio_ch] = p_zc_mute_param->pcallback[audio_ch];
+        }
+        
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif    
+
+        if (SCUX_CH_STOP != p_info_ch->ch_stat)
+        {
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+            
+            /* set parameter for register */
+            SCUX_SetZerocrossMuteRegister(p_info_ch);
+            
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+        }
+            
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetDvuZerocrossMute
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetStopMute
+* @brief         Stop mute.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     audio_channel:Audio channel number.
+* @retval        ESUCCESS:Operation successful.
+*                EPERM:Parameter is unexpected value.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetStopMute(const int_t channel, const uint32_t audio_channel)
+{
+    int_t retval = ESUCCESS;
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if (NULL == p_info_ch)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (audio_channel >= (uint32_t)p_info_ch->src_cfg.use_ch)
+        {
+            retval = EPERM;
+        }
+        
+        if (ESUCCESS == retval)
+        {
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif
+
+            p_info_ch->dvu_mute_stat &= ~(1U << audio_channel);
+            p_info_ch->dvu_cfg.dvu_zc_mute.zc_mute_enable[audio_channel] = false;
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 &= ~DVUER_DVU0_DVUEN_SET;
+            p_info_ch->p_scux_reg->p_dvu_reg->ZCMCR_DVU0_0 &= ~(ZCMCR_DVU0_ZCEN_SET << audio_channel);
+            p_info_ch->p_scux_reg->p_dvu_reg->DVUER_DVU0_0 |= DVUER_DVU0_DVUEN_SET;
+            
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }       
+        }
+    }
+    
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetStopMute
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetMixCfg
+* @brief         Set MIX parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     *p_mix_param:MIX parameter.
+* @retval        ESUCCESS : Operation successful.
+*                EPERM : Transfer parameter is unexpected.
+*                EFAULT : Internal error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetMixCfg(const scux_mix_cfg_t * const p_mix_param)
+{
+    int_t retval = ESUCCESS;
+    int_t scux_ch;
+    int_t audio_ch;
+    int_t was_masked;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if ((NULL == p_info_drv) || (NULL == p_mix_param))
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        p_info_drv->shared_info.mixmode_ramp = p_mix_param->mixmode_ramp;
+        p_info_drv->shared_info.up_period = p_mix_param->up_period;
+        p_info_drv->shared_info.down_period = p_mix_param->down_period;
+        for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++)
+        {
+            p_info_drv->shared_info.mix_vol[scux_ch] = p_mix_param->mix_vol[scux_ch];
+        }
+        for (audio_ch = SCUX_AUDIO_CH_0; audio_ch < SCUX_AUDIO_CH_MAX; audio_ch++)
+        {
+            p_info_drv->shared_info.select_out_data_ch[audio_ch] = p_mix_param->select_out_data_ch[audio_ch];
+        }
+            
+        for (scux_ch = SCUX_CH_0; ((ESUCCESS == retval) && (scux_ch < SCUX_CH_NUM)); scux_ch++)
+        {
+            /* check going channel number */
+            if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch)))
+            {
+                /* check ramp volume */
+                if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[scux_ch])
+                {
+                    retval = EPERM;
+                }
+            }
+        }
+            
+        if (ESUCCESS == retval)
+        {
+            for (scux_ch = SCUX_CH_0; scux_ch < SCUX_CH_NUM; scux_ch++)
+            {
+                /* check going channel number */
+                if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << scux_ch)))
+                {   
+                    /* set parameter for register */
+                    SCUX_SetMixVolRegister(scux_ch);
+                }
+            }
+            
+            p_info_drv->shared_info.mix_setup = true;
+        }
+        else
+        {
+            p_info_drv->shared_info.mix_setup = false;
+        }
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+       
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetMixCfg
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetMixVol
+* @brief         Set MIX volume.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     mix_vol:MIX volume.
+* @retval        ESUCCESS : Operation successful.
+*                EPERM : Transfer parameter is unexpected.
+*                EFAULT: Internel error si occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetMixVol(const int_t channel, const uint32_t mix_vol)
+{
+    int_t retval = ESUCCESS;
+    int_t was_masked;
+    int32_t  sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_info_drv_t * const p_info_drv = SCUX_GetDrvInstance();
+    
+    if (NULL == p_info_drv)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+        if (0 == R_ExceptionalMode())
+        {  
+            sem_wait_ercd = osSemaphoreWait(p_info_drv->shared_info.sem_shared_access, osWaitForever);
+            /* <-MISRA 10.6 */
+            /* semaphore error check */
+            if ((-1) == sem_wait_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT;
+            }
+        }
+        
+        if (ESUCCESS == retval)
+        {
+            p_info_drv->shared_info.mix_vol[channel] = mix_vol;
+            
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif
+
+            /* check going channel number */
+            if (0U != (p_info_drv->shared_info.mix_run_ch & (1U << channel)))
+            {
+                /* check ramp volume */
+                if (SCUX_MAX_RAMP_VOLUME < p_info_drv->shared_info.mix_vol[channel])
+                {
+                    retval = EPERM;
+                }
+                else
+                {               
+                    /* set parameter for register */
+                    SCUX_SetMixVolRegister(channel);
+                }
+            }
+            
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }
+        }
+        
+        if (0 == R_ExceptionalMode())
+        {  
+            sem_ercd = osSemaphoreRelease(p_info_drv->shared_info.sem_shared_access);
+            /* semaphore error check */
+            if (osOK != sem_ercd)
+            {
+                /* set semaphore error */
+                retval = EFAULT;
+            }
+        }
+    }
+        
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetMixVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlSetSsifCfg
+* @brief         Set SSIF parameter.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     p_ssif_param:SSIF parameter.
+* @retval        ESUCCESS : Operation successful.
+*                EBADF : SSIF channel has already used on other SCUX channel.
+*                EPERM : Transfer parameter is unexpected.
+*                EFAULT: Internel error is occured.
+******************************************************************************/
+
+int_t SCUX_IoctlSetSsifCfg(const scux_ssif_cfg_t * const p_ssif_param)
+{
+    int_t retval = ESUCCESS;
+    int32_t  sem_wait_ercd;
+    osStatus sem_ercd;
+    scux_ssif_info_t * p_ssif_ch;
+    
+    if (NULL == p_ssif_param)
+    {
+        retval = EFAULT;
+    }
+    else
+    {
+        if (SCUX_SSIF_CH_NUM > p_ssif_param->ssif_ch_num)
+        {
+            p_ssif_ch = SCUX_GetSsifChInfo((int_t)p_ssif_param->ssif_ch_num);
+            if (NULL == p_ssif_ch)
+            {
+                retval = EFAULT;
+            }
+            else
+            {
+                /* ->MISRA 10.6, osWaitForever is defined by the header got from related section*/ 
+                sem_wait_ercd = osSemaphoreWait(p_ssif_ch->sem_ch_scux_ssif_access, osWaitForever);
+                /* <-MISRA 10.6 */
+                /* semaphore error check */
+                if ((-1) == sem_wait_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+                else
+                {
+                    if (0 != p_ssif_ch->scux_channel)
+                    {
+                        retval = EBADF;
+                    }
+                    else
+                    {
+                        p_ssif_ch->ssif_cfg.ssif_ch_num = p_ssif_param->ssif_ch_num;
+                        p_ssif_ch->ssif_cfg.mode_master = p_ssif_param->mode_master;
+                        p_ssif_ch->ssif_cfg.select_audio_clk = p_ssif_param->select_audio_clk;
+                        p_ssif_ch->ssif_cfg.system_word = p_ssif_param->system_word;
+                        p_ssif_ch->ssif_cfg.sck_polarity_rise = p_ssif_param->sck_polarity_rise;
+                        p_ssif_ch->ssif_cfg.ws_polarity_high = p_ssif_param->ws_polarity_high;
+                        p_ssif_ch->ssif_cfg.padding_high = p_ssif_param->padding_high;
+                        p_ssif_ch->ssif_cfg.serial_data_align = p_ssif_param->serial_data_align;
+                        p_ssif_ch->ssif_cfg.ws_delay = p_ssif_param->ws_delay;
+                        p_ssif_ch->ssif_cfg.use_noise_cancel = p_ssif_param->use_noise_cancel;
+                        p_ssif_ch->ssif_cfg.use_tdm = p_ssif_param->use_tdm;
+                        p_ssif_ch->ssif_setup = true;
+                    }
+                }
+                
+                sem_ercd = osSemaphoreRelease(p_ssif_ch->sem_ch_scux_ssif_access);
+                /* semaphore error check */
+                if (osOK != sem_ercd)
+                {
+                    /* set semaphore error */
+                    retval = EFAULT;
+                }
+            }
+        }
+        else
+        {
+            retval = EPERM;
+        }
+    }
+            
+    return retval;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlSetMixVol
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetWriteStat
+* @brief         Get write request status.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_write_stat:Write request status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetWriteStat(const int_t channel, uint32_t * const p_write_stat)
+{
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_write_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        if ((SCUX_CH_STOP == p_info_ch->ch_stat) || 
+            (SCUX_CH_STOP_WAIT == p_info_ch->ch_stat) || 
+            (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat))
+        {
+            *p_write_stat = SCUX_STAT_STOP;
+        }
+        else if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) || (SCUX_CH_TRANS_RD == p_info_ch->ch_stat))
+        {
+            *p_write_stat = SCUX_STAT_IDLE;
+        }
+        else
+        {
+            *p_write_stat = SCUX_STAT_TRANS;
+        }
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetWriteStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetReadStat
+* @brief         Get read request status.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_read_stat:Read request status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetReadStat(const int_t channel, uint32_t * const p_read_stat)
+{
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif
+
+    if ((NULL == p_info_ch) || (NULL == p_read_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+        if (SCUX_CH_STOP == p_info_ch->ch_stat)
+        {
+            *p_read_stat = SCUX_STAT_STOP;
+        }
+        else if ((SCUX_CH_TRANS_IDLE == p_info_ch->ch_stat) || 
+                 (SCUX_CH_TRANS_WR == p_info_ch->ch_stat) || 
+                 (SCUX_CH_STOP_WAIT_IDLE == p_info_ch->ch_stat))
+        {
+            *p_read_stat = SCUX_STAT_IDLE;
+        }
+        else
+        {
+            *p_read_stat = SCUX_STAT_TRANS;
+        }
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetReadStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetDvuStat
+* @brief         Get DVU status.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_dvu_stat:DVU status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetDvuStat(const int_t channel, uint32_t * const p_dvu_stat)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_dvu_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */   
+    }
+    else
+    {
+        *p_dvu_stat = (p_info_ch->p_scux_reg->p_dvu_reg->DVUSR_DVU0_0 & DVUSR_DVU0_VRSTS_MASK);
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetDvuStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetMuteStat
+* @brief         Get MUTE status.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_mute_stat:MUTE status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetMuteStat(const int_t channel, uint32_t * const p_mute_stat)
+{
+    int_t was_masked;
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_mute_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */
+    }
+    else
+    {
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        *p_mute_stat = p_info_ch->dvu_mute_stat;
+        
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetMuteStat
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: SCUX_IoctlGetMixStat
+* @brief         Get MIX status.
+*
+*                Description:<br>
+*                
+* @param[in]     channel:SCUX channel number.
+* @param[in]     *p_mix_stat:MIX status.
+* @retval        None.
+******************************************************************************/
+
+void SCUX_IoctlGetMixStat(const int_t channel, uint32_t * const p_mix_stat)
+{
+    scux_info_ch_t * const p_info_ch = SCUX_GetDrvChInfo(channel);
+    
+    if ((NULL == p_info_ch) || (NULL == p_mix_stat))
+    {
+        /* NON_NOTICE_ASSERT: NULL pointer */   
+    }
+    else
+    {
+        *p_mix_stat = (*(p_info_ch->p_scux_reg->mixsr_mix0_0) & MIXSR_MIX0_MIXSTS_MASK);
+    }
+        
+    return;
+}
+
+/******************************************************************************
+End of function SCUX_IoctlGetMixStat
+******************************************************************************/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/scux/scux_ver.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         scux_ver.c
+* $Rev: 1645 $
+* $Date:: 2015-05-21 10:35:06 +0900#$
+* @brief        SCUX Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "scux_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V2.12 -> MAJOR=2, MINOR=12 */
+#define SCUX_DRV_VER_MAJOR  (2u)
+#define SCUX_DRV_VER_MINOR  (2u)
+
+#define SCUX_DRV_VER_MASK   (0xFFu)
+#define SCUX_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SCUX_GetVersion
+* @brief         Get SCUX driver version.
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_SCUX_GetVersion(void)
+{
+    const uint16_t version =
+        ((SCUX_DRV_VER_MAJOR & SCUX_DRV_VER_MASK) << SCUX_DRV_VER_SHIFT)
+        | (SCUX_DRV_VER_MINOR & SCUX_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_SCUX_GetVersion
+******************************************************************************/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/ssif/ssif.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1469 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* Description : SSIF driver functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "iodefine.h"
+#include "ssif_int.h"
+#include "Renesas_RZ_A1.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+/* ->MISRA 8.8, MISRA 8.10, IPA M2.2.2 : These declare statements are dependent on CMSIS-RTOS */
+osSemaphoreDef(ssif_ch0_access);
+osSemaphoreDef(ssif_ch1_access);
+osSemaphoreDef(ssif_ch2_access);
+osSemaphoreDef(ssif_ch3_access);
+osSemaphoreDef(ssif_ch4_access);
+osSemaphoreDef(ssif_ch5_access);
+/* <-MISRA 8.8, MISRA 8.10, IPA M2.2.2 */
+
+ssif_info_drv_t g_ssif_info_drv;
+
+volatile struct st_ssif* const g_ssireg[SSIF_NUM_CHANS] = SSIF_ADDRESS_LIST;
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static int_t SSIF_InitChannel(ssif_info_ch_t* const p_info_ch);
+static void SSIF_UnInitChannel(ssif_info_ch_t* const p_info_ch);
+static int_t SSIF_UpdateChannelConfig(ssif_info_ch_t* const p_info_ch,
+                                      const ssif_channel_cfg_t* const p_ch_cfg);
+static int_t SSIF_SetCtrlParams(const ssif_info_ch_t* const p_info_ch);
+static int_t SSIF_CheckChannelCfg(const ssif_channel_cfg_t* const p_ch_cfg);
+static int_t SSIF_CheckWordSize(const ssif_info_ch_t* const p_info_ch);
+static void SSIF_Reset(const uint32_t ssif_ch);
+
+static const uint32_t gb_cpg_stbcr_bit[SSIF_NUM_CHANS] =
+{
+    CPG_STBCR11_BIT_MSTP115,    /* SSIF0 */
+    CPG_STBCR11_BIT_MSTP114,    /* SSIF1 */
+    CPG_STBCR11_BIT_MSTP113,    /* SSIF2 */
+    CPG_STBCR11_BIT_MSTP112,    /* SSIF3 */
+    CPG_STBCR11_BIT_MSTP111,    /* SSIF4 */
+    CPG_STBCR11_BIT_MSTP110     /* SSIF5 */
+};
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)                       
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: SSIF_InitialiseOne
+* @brief         Initialize the SSIF driver's internal data
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :channel number
+* @param[in]     p_cfg_data :pointer of several parameters array per channels
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_InitialiseOne(const int_t channel, const ssif_channel_cfg_t* const p_cfg_data)
+{
+    int_t           ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    if (NULL == p_cfg_data)
+    {
+        ercd = EFAULT;
+    }
+    else if (false == p_cfg_data->enabled)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        p_info_ch = &g_ssif_info_drv.info_ch[channel];
+        p_info_ch->channel = channel;
+        p_info_ch->enabled = p_cfg_data->enabled;
+
+        /* copy config data to channel info */
+        ercd = SSIF_UpdateChannelConfig(p_info_ch, p_cfg_data);
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = SSIF_InitChannel(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            SSIF_InterruptInit(channel, p_cfg_data->int_level);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitialiseOne
+* @brief         UnInitialize the SSIF driver's internal data
+*
+*                Description:<br>
+*                
+* @param[in]     channel    :channel number
+* @retval        ESUCCESS   :Success.
+******************************************************************************/
+int_t SSIF_UnInitialiseOne(const int_t channel)
+{
+    const int_t     ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    p_info_ch = &g_ssif_info_drv.info_ch[channel];
+
+    if (false != p_info_ch->enabled)
+    {
+        SSIF_UnInitChannel(p_info_ch);
+    }
+
+    return ercd;
+}
+
+#endif /* end mbed */
+/******************************************************************************
+* Function Name: SSIF_Initialise
+* @brief         Initialize the SSIF driver's internal data
+*
+*                Description:<br>
+*                
+* @param[in]     p_cfg_data :pointer of several parameters array per channels
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_Initialise(const ssif_channel_cfg_t* const p_cfg_data)
+{
+    uint32_t        ssif_ch;
+    int_t           ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    if (NULL == p_cfg_data)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        for (ssif_ch = 0; (ssif_ch < SSIF_NUM_CHANS) && (ESUCCESS == ercd); ssif_ch++)
+        {
+            p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+            p_info_ch->channel = ssif_ch;
+            p_info_ch->enabled = p_cfg_data[ssif_ch].enabled;
+            
+            if (false != p_info_ch->enabled)
+            {
+                /* copy config data to channel info */
+                ercd = SSIF_UpdateChannelConfig(p_info_ch, &p_cfg_data[ssif_ch]);
+
+                if (ESUCCESS == ercd)
+                {
+                    ercd = SSIF_InitChannel(p_info_ch);
+                }
+            }
+        } 
+
+        if (ESUCCESS == ercd)
+        {
+            for (ssif_ch = 0; ssif_ch < SSIF_NUM_CHANS; ssif_ch++)
+            {
+                p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+
+                if (false != p_info_ch->enabled)
+                {
+                    SSIF_InterruptInit(ssif_ch, p_cfg_data[ssif_ch].int_level);
+                }
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitialise
+* @brief         UnInitialize the SSIF driver's internal data
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        ESUCCESS   :Success.
+******************************************************************************/
+int_t SSIF_UnInitialise(void)
+{
+    uint32_t        ssif_ch;
+    const int_t     ercd = ESUCCESS;
+    ssif_info_ch_t* p_info_ch;
+
+    for (ssif_ch = 0; ssif_ch < SSIF_NUM_CHANS; ssif_ch++)
+    {
+        p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+
+        if (false != p_info_ch->enabled)
+        {
+            SSIF_UnInitChannel(p_info_ch);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_EnableChannel
+* @brief         Enable the SSIF channel
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_EnableChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    int_t was_masked;
+    uint32_t ssif_ch;
+    volatile uint8_t dummy_buf;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ercd = EFAULT;
+        }
+        else 
+        {
+            /* check channel open flag(duplex) */
+            if ((O_RDWR == p_info_ch->openflag)
+                && (false == p_info_ch->is_full_duplex))
+            {
+                ercd = EINVAL;
+            }
+
+            /* check channel open flag(romdec direct input) */
+            if (ESUCCESS == ercd)
+            {
+                if ((O_RDONLY != p_info_ch->openflag)
+                    && (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                        == p_info_ch->romdec_direct.mode))
+                {
+                    ercd = EINVAL;
+                }
+            }
+
+            /* enable the SSIF clock */
+            if (ESUCCESS == ercd)
+            {
+#if defined (__ICCARM__)
+                was_masked = __disable_irq_iar();
+#else
+                was_masked = __disable_irq();
+#endif
+
+                /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */
+                CPGSTBCR11 &= (uint8_t)~((uint8_t)gb_cpg_stbcr_bit[ssif_ch]);
+                /* <-IPA R2.4.2 */
+                dummy_buf = CPGSTBCR11;
+
+                if (0 == was_masked)
+                {
+                    __enable_irq();
+                }
+            }
+
+            /* configure channel hardware */
+            if (ESUCCESS == ercd)
+            {
+                /* software reset */
+                SSIF_Reset(ssif_ch);
+
+                /* Set control parameters */
+                ercd = SSIF_SetCtrlParams(p_info_ch);
+            }
+
+            /* allocate and setup/start DMA transfer */
+            if (ESUCCESS == ercd)
+            {
+                ercd = SSIF_InitDMA(p_info_ch);
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DisableChannel
+* @brief         Disable the SSIF channel
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_DisableChannel(ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t dummy_read;
+    int_t   was_masked;
+    int_t   ret = ESUCCESS;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ret = EFAULT;
+        }
+        else
+        {
+            SSIF_DisableErrorInterrupt(ssif_ch);
+
+            /* TEN and REN are disable */
+            g_ssireg[ssif_ch]->SSICR &= ~(SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN);
+
+            /* Reset FIFO */
+            g_ssireg[ssif_ch]->SSIFCR |= (SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+            dummy_read = g_ssireg[ssif_ch]->SSIFCR;
+            UNUSED_ARG(dummy_read);
+            g_ssireg[ssif_ch]->SSIFCR &= ~(SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+
+            /* free DMA resources */
+            SSIF_UnInitDMA(p_info_ch);
+
+            /* clear status reg */
+            g_ssireg[ssif_ch]->SSISR = 0u; /* ALL CLEAR */
+
+            /* disable ssif clock */
+#if defined (__ICCARM__)
+            was_masked = __disable_irq_iar();
+#else
+            was_masked = __disable_irq();
+#endif
+
+            /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 8bit register. */
+            CPGSTBCR11 |= (uint8_t)gb_cpg_stbcr_bit[ssif_ch];
+            /* <-IPA R2.4.2 */
+
+            if (0 == was_masked)
+            {
+                __enable_irq();
+            }
+
+            /* cancel event to ongoing request */
+            if (NULL != p_info_ch->p_aio_tx_curr)
+            {
+                p_info_ch->p_aio_tx_curr->aio_return = ECANCELED;
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+                p_info_ch->p_aio_tx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_tx_next)
+            {
+                p_info_ch->p_aio_tx_next->aio_return = ECANCELED;
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next);
+                p_info_ch->p_aio_tx_next = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_curr)
+            {
+                p_info_ch->p_aio_rx_curr->aio_return = ECANCELED;
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+                p_info_ch->p_aio_rx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_next)
+            {
+                p_info_ch->p_aio_rx_next->aio_return = ECANCELED;
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next);
+                p_info_ch->p_aio_rx_next = NULL;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_ErrorRecovery
+* @brief         Restart the SSIF channel
+*
+*                Description:<br>
+*                When normal mode<br>
+*                  Stop and restart DMA transfer.<br>
+*                When ROMDEC direct input mode<br>
+*                  Stop DMA transfer, and execute callback function.<br>
+*                Note: This function execute in interrupt context.
+* @param[in,out] p_info_ch  :channel object
+* @retval        none
+******************************************************************************/
+void SSIF_ErrorRecovery(ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t dummy_read;
+    int_t   ercd = ESUCCESS;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (ssif_ch >= SSIF_NUM_CHANS)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            /* disable DMA end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR &= ~((uint32_t)SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE);
+
+            SSIF_DisableErrorInterrupt(ssif_ch);
+
+            /* TEN and REN are disable */
+            g_ssireg[ssif_ch]->SSICR &= ~(SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN);
+
+            /* Reset FIFO */
+            g_ssireg[ssif_ch]->SSIFCR |= (SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+            dummy_read = g_ssireg[ssif_ch]->SSIFCR;
+            UNUSED_ARG(dummy_read);
+            g_ssireg[ssif_ch]->SSIFCR &= ~(SSIF_FCR_BIT_TFRST | SSIF_FCR_BIT_RFRST);
+
+            /* pause DMA transfer */
+            SSIF_CancelDMA(p_info_ch);
+
+            /* clear status reg */
+            g_ssireg[ssif_ch]->SSISR = 0u; /* ALL CLEAR */
+
+            /* cancel event to ongoing request */
+            if (NULL != p_info_ch->p_aio_tx_curr)
+            {
+                p_info_ch->p_aio_tx_curr->aio_return = EIO;
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+                p_info_ch->p_aio_tx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_tx_next)
+            {
+                p_info_ch->p_aio_tx_next->aio_return = EIO;
+                ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_next);
+                p_info_ch->p_aio_tx_next = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_curr)
+            {
+                p_info_ch->p_aio_rx_curr->aio_return = EIO;
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+                p_info_ch->p_aio_rx_curr = NULL;
+            }
+            if (NULL != p_info_ch->p_aio_rx_next)
+            {
+                p_info_ch->p_aio_rx_next->aio_return = EIO;
+                ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_next);
+                p_info_ch->p_aio_rx_next = NULL;
+            }
+        }
+
+        /* configure channel hardware */
+        if (ESUCCESS == ercd)
+        {
+            /* software reset */
+            SSIF_Reset(ssif_ch);
+
+            /* Set control parameters */
+            ercd = SSIF_SetCtrlParams(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                != p_info_ch->romdec_direct.mode)
+            {
+                /* setup/restart DMA transfer */
+                ercd = SSIF_RestartDMA(p_info_ch);
+            }
+            else
+            {
+                /* execute callback function */
+                if (NULL != p_info_ch->romdec_direct.p_cbfunc)
+                {
+                    (*p_info_ch->romdec_direct.p_cbfunc)();
+                }
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        /* NON_NOTICE_ASSERT: cannot restart channel */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_PostAsyncIo
+* @brief         Enqueue asynchronous read/write request
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object
+* @param[in,out] p_aio      :aio control block of read/write request
+* @retval        none
+******************************************************************************/
+void SSIF_PostAsyncIo(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio)
+{
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (SSIF_ASYNC_W == p_aio->aio_return)
+        {
+            ahf_addtail(&p_info_ch->tx_que, p_aio);
+        }
+        else if (SSIF_ASYNC_R == p_aio->aio_return)
+        {
+            ahf_addtail(&p_info_ch->rx_que, p_aio);
+        }
+        else
+        {
+            /* NON_NOTICE_ASSERT: illegal request type */
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_PostAsyncCancel
+* @brief         Cancel read or write request(s)
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object
+* @param[in,out] p_aio      :aio control block to cancel or NULL to cancel all.
+* @retval        none
+******************************************************************************/
+void SSIF_PostAsyncCancel(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio)
+{
+    int32_t ioif_ret;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (NULL == p_aio)
+        {
+            ahf_cancelall(&p_info_ch->tx_que);
+            ahf_cancelall(&p_info_ch->rx_que);
+        }
+        else
+        {
+            ioif_ret = ahf_cancel(&p_info_ch->tx_que, p_aio);
+            if (ESUCCESS != ioif_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected aioif error */
+            }
+
+            ioif_ret = ahf_cancel(&p_info_ch->rx_que, p_aio);
+            if (ESUCCESS != ioif_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected aioif error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_IOCTL_ConfigChannel
+* @brief         Save configuration to the SSIF driver.
+*
+*                Description:<br>
+*                Update channel object.
+* @param[in,out] p_info_ch  :channel object
+* @param[in]     p_ch_cfg   :SSIF channel configuration parameter
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_IOCTL_ConfigChannel(ssif_info_ch_t* const p_info_ch,
+                                const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t    ercd;
+
+    if ((NULL == p_info_ch) || (NULL == p_ch_cfg))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        /* stop DMA transfer */
+        ercd = SSIF_DisableChannel(p_info_ch);
+
+        if (ESUCCESS == ercd)
+        {
+            /* copy config data to channel info */
+            ercd = SSIF_UpdateChannelConfig(p_info_ch, p_ch_cfg);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* restart DMA transfer */
+            ercd = SSIF_EnableChannel(p_info_ch);
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_IOCTL_GetStatus
+* @brief         Get a value of SSISR register.
+*
+*                Description:<br>
+*                
+* @param[in]     p_info_ch  :channel object
+* @param[in,out] p_status   :pointer of status value
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_IOCTL_GetStatus(const ssif_info_ch_t* const p_info_ch, uint32_t* const p_status)
+{
+    int_t ret = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_status))
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        *p_status = g_ssireg[p_info_ch->channel]->SSISR;
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SWLtoLen
+* @brief         Convert SSICR:SWL bits to system word length
+*
+*                Description:<br>
+*                
+* @param[in]     ssicr_swl  :SSICR register SWL field value(0 to 7)
+* @retval        8 to 256   :system word length(byte)
+******************************************************************************/
+int_t SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl)
+{
+    /* -> IPA M1.10.1 : This is conversion table that can't be macro-coding. */
+    static const int_t decode_enum_swl[SSIF_CFG_SYSTEM_WORD_256+1] = {
+        8,      /* SSIF_CFG_SYSTEM_WORD_8   */
+        16,     /* SSIF_CFG_SYSTEM_WORD_16  */
+        24,     /* SSIF_CFG_SYSTEM_WORD_24  */
+        32,     /* SSIF_CFG_SYSTEM_WORD_32  */
+        48,     /* SSIF_CFG_SYSTEM_WORD_48  */
+        64,     /* SSIF_CFG_SYSTEM_WORD_64  */
+        128,    /* SSIF_CFG_SYSTEM_WORD_128 */
+        256     /* SSIF_CFG_SYSTEM_WORD_256 */
+    };
+    /* <- IPA M1.10.1 */
+
+    return decode_enum_swl[ssicr_swl];
+}
+
+/******************************************************************************
+* Function Name: SSIF_DWLtoLen
+* @brief         Convert SSICR:DWL bits to data word length
+*
+*                Description:<br>
+*                
+* @param[in]     ssicr_dwl  :SSICR register DWL field value(0 to 6)
+* @retval        8 to 32    :data word length(byte)
+******************************************************************************/
+int_t SSIF_DWLtoLen(const ssif_chcfg_data_word_t ssicr_dwl)
+{
+    /* -> IPA M1.10.1 : This is conversion table that can't be macro-coding. */
+    static const int_t decode_enum_dwl[SSIF_CFG_DATA_WORD_32+1] = {
+        8,   /* SSIF_CFG_DATA_WORD_8  */
+        16,  /* SSIF_CFG_DATA_WORD_16 */
+        18,  /* SSIF_CFG_DATA_WORD_18 */
+        20,  /* SSIF_CFG_DATA_WORD_20 */
+        22,  /* SSIF_CFG_DATA_WORD_22 */
+        24,  /* SSIF_CFG_DATA_WORD_24 */
+        32   /* SSIF_CFG_DATA_WORD_32 */
+    };
+    /* <- IPA M1.10.1 */
+
+    return decode_enum_dwl[ssicr_dwl];
+}
+
+/******************************************************************************
+Private functions                                                               
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: SSIF_InitChannel
+* @brief         Initialize for the SSIF channel
+*
+*                Description:<br>
+*                Create semaphore and queue for channel.<br>
+*                And setup SSIF pin.
+* @param[in,out] p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_InitChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int32_t os_ret;
+    uint32_t ssif_ch;
+    int_t ercd = ESUCCESS;
+    static const osSemaphoreDef_t* semdef_access[SSIF_NUM_CHANS] =
+    {
+        osSemaphore(ssif_ch0_access),
+        osSemaphore(ssif_ch1_access),
+        osSemaphore(ssif_ch2_access),
+        osSemaphore(ssif_ch3_access),
+        osSemaphore(ssif_ch4_access),
+        osSemaphore(ssif_ch5_access)
+    };
+    static const bool_t is_duplex_ch[SSIF_NUM_CHANS] =
+    {
+        true,   /* SSIF0 is full duplex channel */
+        true,   /* SSIF1 is full duplex channel */
+        false,  /* SSIF2 is half duplex channel */
+        true,   /* SSIF3 is full duplex channel */
+        false,  /* SSIF4 is half duplex channel */
+        true    /* SSIF5 is full duplex channel */
+    };
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        p_info_ch->is_full_duplex = is_duplex_ch[ssif_ch];
+
+        /* Create sem_access semaphore */
+        p_info_ch->sem_access = osSemaphoreCreate(semdef_access[ssif_ch], 1);
+
+        if (NULL == p_info_ch->sem_access)
+        {
+            ercd = ENOMEM;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = ahf_create(&p_info_ch->tx_que, AHF_LOCKINT);
+            if (ESUCCESS != ercd)
+            {
+                ercd = ENOMEM;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = ahf_create(&p_info_ch->rx_que, AHF_LOCKINT);
+            if (ESUCCESS != ercd)
+            {
+                ercd = ENOMEM;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* set channel initialize */
+            p_info_ch->openflag = 0;
+
+            p_info_ch->p_aio_tx_curr = NULL;       /* tx request pointer */
+            p_info_ch->p_aio_tx_next = NULL;       /* tx request pointer */
+            p_info_ch->p_aio_rx_curr = NULL;       /* rx request pointer */
+            p_info_ch->p_aio_rx_next = NULL;       /* rx request pointer */
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = R_SSIF_Userdef_InitPinMux(ssif_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            p_info_ch->ch_stat = SSIF_CHSTS_INIT;
+        }
+        else
+        {
+            if (NULL != p_info_ch->sem_access)
+            {
+                os_ret = osSemaphoreDelete(p_info_ch->sem_access);
+                if (osOK != os_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected semaphore error */
+                }
+                p_info_ch->sem_access = NULL;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitChannel
+* @brief         Uninitialise the SSIF channel.
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object
+* @retval        none
+******************************************************************************/
+static void SSIF_UnInitChannel(ssif_info_ch_t* const p_info_ch)
+{
+    int32_t os_ret;
+    int_t was_masked;
+    uint32_t ssif_ch;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (SSIF_CHSTS_INIT != p_info_ch->ch_stat)
+        {
+            /* NON_NOTICE_ASSERT: unexpected channel status */
+        }
+
+        p_info_ch->ch_stat = SSIF_CHSTS_UNINIT;
+
+        SSIF_DisableErrorInterrupt(ssif_ch);
+
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        /* delete the tx queue */
+        ahf_cancelall(&p_info_ch->tx_que);
+        ahf_destroy(&p_info_ch->tx_que);
+
+        /* delete the rx queue */
+        ahf_cancelall(&p_info_ch->rx_que);
+        ahf_destroy(&p_info_ch->rx_que);
+
+        /* delete the private semaphore */
+        os_ret = osSemaphoreDelete(p_info_ch->sem_access);
+        if (osOK != os_ret)
+        {
+            /* NON_NOTICE_ASSERT: unexpected semaphore error */
+        }
+
+        SSIF_InterruptShutdown(ssif_ch);
+
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UpdateChannelConfig
+* @brief         Save configuration to the SSIF driver.
+*
+*                Description:<br>
+*                Update channel object.
+* @param[in,out] p_info_ch  :channel object
+* @param[in]     p_ch_cfg   :SSIF channel configuration parameter
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_UpdateChannelConfig(ssif_info_ch_t* const p_info_ch,
+                                      const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t ercd;
+
+    if ((NULL == p_info_ch) || (NULL == p_ch_cfg))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ercd = SSIF_CheckChannelCfg(p_ch_cfg);
+
+        if (ESUCCESS == ercd)
+        {
+            p_info_ch->slave_mode = p_ch_cfg->slave_mode;
+
+            if (false != p_info_ch->slave_mode)
+            {
+                /* slave mode */
+                p_info_ch->clock_direction = SSIF_CFG_CLOCK_IN;
+                p_info_ch->ws_direction = SSIF_CFG_WS_IN;
+            }
+            else
+            {
+                /* master mode */
+                p_info_ch->clock_direction = SSIF_CFG_CLOCK_OUT;
+                p_info_ch->ws_direction = SSIF_CFG_WS_OUT;
+
+                /* when master mode, always disable noise cancel */
+                p_info_ch->noise_cancel = SSIF_CFG_DISABLE_NOISE_CANCEL;
+            }
+
+            p_info_ch->sample_freq        = p_ch_cfg->sample_freq;
+
+            p_info_ch->clk_select         = p_ch_cfg->clk_select;
+            p_info_ch->multi_ch           = p_ch_cfg->multi_ch;
+            p_info_ch->data_word          = p_ch_cfg->data_word;
+            p_info_ch->system_word        = p_ch_cfg->system_word;
+            p_info_ch->bclk_pol           = p_ch_cfg->bclk_pol;
+            p_info_ch->ws_pol             = p_ch_cfg->ws_pol;
+            p_info_ch->padding_pol        = p_ch_cfg->padding_pol;
+            p_info_ch->serial_alignment   = p_ch_cfg->serial_alignment;
+            p_info_ch->parallel_alignment = p_ch_cfg->parallel_alignment;
+            p_info_ch->ws_delay           = p_ch_cfg->ws_delay;
+            p_info_ch->noise_cancel       = p_ch_cfg->noise_cancel;
+            p_info_ch->tdm_mode           = p_ch_cfg->tdm_mode;
+            p_info_ch->romdec_direct.mode     = p_ch_cfg->romdec_direct.mode;
+            p_info_ch->romdec_direct.p_cbfunc = p_ch_cfg->romdec_direct.p_cbfunc;
+
+            if (SSIF_CFG_ENABLE_TDM == p_info_ch->tdm_mode)
+            {
+                /* check combination of parameters */
+                if ((SSIF_CFG_MULTI_CH_1 == p_info_ch->multi_ch)
+                    || (SSIF_CFG_WS_HIGH == p_info_ch->ws_pol))
+                {
+                    ercd = EINVAL;
+                }
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            ercd = SSIF_CheckWordSize(p_info_ch);
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (false == p_info_ch->slave_mode)
+            {
+                /* Master: call user own clock setting function */
+                ercd = R_SSIF_Userdef_SetClockDiv(p_ch_cfg, &p_info_ch->clk_div);
+            }
+            else
+            {
+                /* Slave: set dummy value for clear */
+                p_info_ch->clk_div = SSIF_CFG_CKDV_BITS_1;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SetCtrlParams
+* @brief         Set SSIF configuration to hardware.
+*
+*                Description:<br>
+*                Update SSICR register.
+* @param[in]     p_info_ch  :channel object
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+static int_t SSIF_SetCtrlParams(const ssif_info_ch_t* const p_info_ch)
+{
+    int_t ret = ESUCCESS;
+    int_t was_masked;
+    uint32_t ssif_ch;
+    static const uint32_t gpio_sncr_bit[SSIF_NUM_CHANS] =
+    {
+        GPIO_SNCR_BIT_SSI0NCE,  /* SSIF0 */
+        GPIO_SNCR_BIT_SSI1NCE,  /* SSIF1 */
+        GPIO_SNCR_BIT_SSI2NCE,  /* SSIF2 */
+        GPIO_SNCR_BIT_SSI3NCE,  /* SSIF3 */
+        GPIO_SNCR_BIT_SSI4NCE,  /* SSIF4 */
+        GPIO_SNCR_BIT_SSI5NCE   /* SSIF5 */
+    };
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* ALL CLEAR */
+        g_ssireg[ssif_ch]->SSICR = 0u;
+        g_ssireg[ssif_ch]->SSISR = 0u;
+        g_ssireg[ssif_ch]->SSIFCCR = 0u;
+
+        g_ssireg[ssif_ch]->SSICR = (uint32_t)(
+             ((uint32_t)(p_info_ch->clk_select)         << SSIF_CR_SHIFT_CKS) |
+             ((uint32_t)(p_info_ch->multi_ch)           << SSIF_CR_SHIFT_CHNL) |
+             ((uint32_t)(p_info_ch->data_word)          << SSIF_CR_SHIFT_DWL) |
+             ((uint32_t)(p_info_ch->system_word)        << SSIF_CR_SHIFT_SWL) |
+             ((uint32_t)(p_info_ch->bclk_pol)           << SSIF_CR_SHIFT_SCKP) |
+             ((uint32_t)(p_info_ch->ws_pol)             << SSIF_CR_SHIFT_SWSP) |
+             ((uint32_t)(p_info_ch->padding_pol)        << SSIF_CR_SHIFT_SPDP) |
+             ((uint32_t)(p_info_ch->serial_alignment)   << SSIF_CR_SHIFT_SDTA) |
+             ((uint32_t)(p_info_ch->parallel_alignment) << SSIF_CR_SHIFT_PDTA) |
+             ((uint32_t)(p_info_ch->ws_delay)           << SSIF_CR_SHIFT_DEL) |
+             ((uint32_t)(p_info_ch->clock_direction)    << SSIF_CR_SHIFT_SCKD) |
+             ((uint32_t)(p_info_ch->ws_direction)       << SSIF_CR_SHIFT_SWSD) |
+             ((uint32_t)(p_info_ch->clk_div)            << SSIF_CR_SHIFT_CKDV)
+             );
+
+        g_ssireg[ssif_ch]->SSITDMR = ((uint32_t)(p_info_ch->tdm_mode) << SSIF_TDMR_SHIFT_TDM);
+
+        /* change SNCR register: enter exclusive */
+#if defined (__ICCARM__)
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif
+
+        if ((SSIF_CFG_ENABLE_NOISE_CANCEL == p_info_ch->noise_cancel)
+            && (false != p_info_ch->slave_mode))
+        {
+            /* ENABLE_NOISE_CANCEL && slave mode */
+            GPIO.SNCR |= (uint32_t)gpio_sncr_bit[ssif_ch];
+        }
+        else
+        {
+            /* DISABLE_NOISE_CANCEL || master mode */
+            GPIO.SNCR &= ~((uint32_t)gpio_sncr_bit[ssif_ch]);
+        }
+
+        /* change SNCR register: exit exclusive */
+        if (0 == was_masked)
+        {
+            __enable_irq();
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CheckChannelCfg
+* @brief         Check channel configuration parameters are valid or not.
+*
+*                Description:<br>
+*                
+* @param[in]     p_ch_cfg     :channel configuration
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+static int_t SSIF_CheckChannelCfg(const ssif_channel_cfg_t* const p_ch_cfg)
+{
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_ch_cfg)
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        switch (p_ch_cfg->clk_select)
+        {
+        case SSIF_CFG_CKS_AUDIO_X1:
+            /* fall through */
+        case SSIF_CFG_CKS_AUDIO_CLK:
+            /* do nothing */
+            break;
+        default:
+            ret = EINVAL;
+            break;
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->multi_ch)
+            {
+            case SSIF_CFG_MULTI_CH_1:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_2:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_3:
+                /* fall through */
+            case SSIF_CFG_MULTI_CH_4:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->data_word)
+            {
+            case SSIF_CFG_DATA_WORD_8:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_16:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_18:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_20:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_22:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_24:
+                /* fall through */
+            case SSIF_CFG_DATA_WORD_32:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->system_word)
+            {
+            case SSIF_CFG_SYSTEM_WORD_8:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_16:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_24:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_32:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_48:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_64:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_128:
+                /* fall through */
+            case SSIF_CFG_SYSTEM_WORD_256:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->bclk_pol)
+            {
+            case SSIF_CFG_FALLING:
+                /* fall through */
+            case SSIF_CFG_RISING:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->ws_pol)
+            {
+            case SSIF_CFG_WS_LOW:
+                /* fall through */
+            case SSIF_CFG_WS_HIGH:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->padding_pol)
+            {
+            case SSIF_CFG_PADDING_LOW:
+                /* fall through */
+            case SSIF_CFG_PADDING_HIGH:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->serial_alignment)
+            {
+            case SSIF_CFG_DATA_FIRST:
+                /* fall through */
+            case SSIF_CFG_PADDING_FIRST:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->parallel_alignment)
+            {
+            case SSIF_CFG_LEFT:
+                /* fall through */
+            case SSIF_CFG_RIGHT:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->ws_delay)
+            {
+            case SSIF_CFG_DELAY:
+                /* fall through */
+            case SSIF_CFG_NO_DELAY:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->noise_cancel)
+            {
+            case SSIF_CFG_DISABLE_NOISE_CANCEL:
+                /* fall through */
+            case SSIF_CFG_ENABLE_NOISE_CANCEL:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->tdm_mode)
+            {
+            case SSIF_CFG_DISABLE_TDM:
+                /* fall through */
+            case SSIF_CFG_ENABLE_TDM:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+
+        if (ESUCCESS == ret)
+        {
+            switch (p_ch_cfg->romdec_direct.mode)
+            {
+            case SSIF_CFG_DISABLE_ROMDEC_DIRECT:
+                /* fall through */
+            case SSIF_CFG_ENABLE_ROMDEC_DIRECT:
+                /* do nothing */
+                break;
+            default:
+                ret = EINVAL;
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CheckWordSize
+* @brief         Check system word size whether that is valid or not.
+*
+*                Description:<br>
+*                if system_words couldn't involve specified number of<br>
+*                data_words then error.
+* @param[in]     p_info_ch    :channel object
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+static int_t SSIF_CheckWordSize(const ssif_info_ch_t* const p_info_ch)
+{
+    uint32_t ssicr_chnl;
+    uint32_t dw_per_sw;
+    uint32_t datawd_len;
+    uint32_t syswd_len;
+    int_t ret = ESUCCESS;
+
+    if (NULL == p_info_ch)
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        ssicr_chnl = p_info_ch->multi_ch;
+        /* ->MISRA 13.7 : This is verbose error check by way of precaution */
+        if (SSIF_CFG_MULTI_CH_4 < ssicr_chnl)
+        /* <-MISRA 13.7 */
+        {
+            ret = EINVAL;
+        }
+        else
+        {
+            /* data_words number per system_words */
+            if (SSIF_CFG_ENABLE_TDM == p_info_ch->tdm_mode)
+            {
+                /* When TDM Mode data_word number per system_words fixed to 1 */
+                dw_per_sw = 1u;
+            }
+            else
+            {
+                /* When not TDM data_word number per system_words depends CHNL */
+                dw_per_sw = ssicr_chnl + 1u;
+            }
+
+            /* size of data_words */
+            datawd_len = (uint32_t)SSIF_DWLtoLen(p_info_ch->data_word);
+
+            if (0u == datawd_len)
+            {
+                ret = EINVAL;
+            }
+            else
+            {
+                /* size of system_words */
+                syswd_len = (uint32_t)SSIF_SWLtoLen(p_info_ch->system_word);
+
+                if (syswd_len < (datawd_len * dw_per_sw))
+                {
+                    ret = EINVAL;
+                }
+            }
+        }
+    }
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_Reset
+* @brief         SSIF software reset
+*
+*                Description:<br>
+*                
+* @param[in]     ssif_ch       :SSIF channel
+* @retval        none
+******************************************************************************/
+static void SSIF_Reset(const uint32_t ssif_ch)
+{
+    int_t was_masked;
+    uint8_t dummy_read_u8;
+    static const uint32_t cpg_swrst_bit[SSIF_NUM_CHANS] =
+    {
+        CPG_SWRSTCR1_BIT_SRST16,    /* SSIF0 */
+        CPG_SWRSTCR1_BIT_SRST15,    /* SSIF1 */
+        CPG_SWRSTCR1_BIT_SRST14,    /* SSIF2 */
+        CPG_SWRSTCR1_BIT_SRST13,    /* SSIF3 */
+        CPG_SWRSTCR1_BIT_SRST12,    /* SSIF4 */
+        CPG_SWRSTCR1_BIT_SRST11     /* SSIF5 */
+    };
+
+    /* change register: enter exclusive */
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif
+
+    /* SW Reset ON */
+    /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on accessing to 8bit register. */
+    CPGSWRSTCR1 |= (uint8_t)cpg_swrst_bit[ssif_ch];
+    dummy_read_u8 = CPGSWRSTCR1;
+    /* <-IPA R2.4.2 */
+    UNUSED_ARG(dummy_read_u8);
+
+    /* SW Reset OFF */
+    /* ->IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on accessing to 8bit register. */
+    CPGSWRSTCR1 &= (uint8_t)~((uint8_t)cpg_swrst_bit[ssif_ch]);
+    dummy_read_u8 = CPGSWRSTCR1;
+    /* <-IPA R2.4.2 */
+    UNUSED_ARG(dummy_read_u8);
+
+    /* change register: exit exclusive */
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    return;
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/ssif/ssif.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,266 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : ssif.h
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* Description  : SSIF driver functions header
+******************************************************************************/
+
+#ifndef SSIF_H
+#define SSIF_H
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "aioif.h"
+#include "iodefine.h"
+#include "ssif_if.h"
+#include "bsp_drv_cmn.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define SSIF_CHNUM_0    (0u)
+#define SSIF_CHNUM_1    (1u)
+#define SSIF_CHNUM_2    (2u)
+#define SSIF_CHNUM_3    (3u)
+#define SSIF_CHNUM_4    (4u)
+#define SSIF_CHNUM_5    (5u)
+
+#define SSIF_CHSTR_0 "\\0"
+#define SSIF_CHSTR_1 "\\1"
+#define SSIF_CHSTR_2 "\\2"
+#define SSIF_CHSTR_3 "\\3"
+#define SSIF_CHSTR_4 "\\4"
+#define SSIF_CHSTR_5 "\\5"
+
+#define SSIF_MAX_PATH_LEN           (32u)
+
+#define SSIF_CR_SHIFT_CKS   (30u)
+#define SSIF_CR_SHIFT_TUIEN (29u)
+#define SSIF_CR_SHIFT_TOIEN (28u)
+#define SSIF_CR_SHIFT_RUIEN (27u)
+#define SSIF_CR_SHIFT_ROIEN (26u)
+#define SSIF_CR_SHIFT_IIEN  (25u)
+#define SSIF_CR_SHIFT_CHNL  (22u)
+#define SSIF_CR_SHIFT_DWL   (19u)
+#define SSIF_CR_SHIFT_SWL   (16u)
+#define SSIF_CR_SHIFT_SCKD  (15u)
+#define SSIF_CR_SHIFT_SWSD  (14u)
+#define SSIF_CR_SHIFT_SCKP  (13u)
+#define SSIF_CR_SHIFT_SWSP  (12u)
+#define SSIF_CR_SHIFT_SPDP  (11u)
+#define SSIF_CR_SHIFT_SDTA  (10u)
+#define SSIF_CR_SHIFT_PDTA  ( 9u)
+#define SSIF_CR_SHIFT_DEL   ( 8u)
+#define SSIF_CR_SHIFT_CKDV  ( 4u)
+#define SSIF_CR_SHIFT_MUEN  ( 3u)
+#define SSIF_CR_SHIFT_TEN   ( 1u)
+#define SSIF_CR_SHIFT_REN   ( 0u)
+
+#define SSIF_CR_BIT_CKS     (1u << SSIF_CR_SHIFT_CKS)
+#define SSIF_CR_BIT_TUIEN   (1u << SSIF_CR_SHIFT_TUIEN)
+#define SSIF_CR_BIT_TOIEN   (1u << SSIF_CR_SHIFT_TOIEN)
+#define SSIF_CR_BIT_RUIEN   (1u << SSIF_CR_SHIFT_RUIEN)
+#define SSIF_CR_BIT_ROIEN   (1u << SSIF_CR_SHIFT_ROIEN)
+#define SSIF_CR_BIT_IIEN    (1u << SSIF_CR_SHIFT_IIEN)
+#define SSIF_CR_BITS_CHNL   (3u << SSIF_CR_SHIFT_CHNL)
+#define SSIF_CR_BITS_DWL    (7u << SSIF_CR_SHIFT_DWL)
+#define SSIF_CR_BITS_SWL    (7u << SSIF_CR_SHIFT_SWL)
+#define SSIF_CR_BIT_SCKD    (1u << SSIF_CR_SHIFT_SCKD)
+#define SSIF_CR_BIT_SWSD    (1u << SSIF_CR_SHIFT_SWSD)
+#define SSIF_CR_BIT_SCKP    (1u << SSIF_CR_SHIFT_SCKP)
+#define SSIF_CR_BIT_SWSP    (1u << SSIF_CR_SHIFT_SWSP)
+#define SSIF_CR_BIT_SPDP    (1u << SSIF_CR_SHIFT_SPDP)
+#define SSIF_CR_BIT_SDTA    (1u << SSIF_CR_SHIFT_SDTA)
+#define SSIF_CR_BIT_PDTA    (1u << SSIF_CR_SHIFT_PDTA)
+#define SSIF_CR_BIT_DEL     (1u << SSIF_CR_SHIFT_DEL)
+#define SSIF_CR_BITS_CKDV   (0xfu << SSIF_CR_SHIFT_CKDV)
+#define SSIF_CR_BIT_MUEN    (1u << SSIF_CR_SHIFT_MUEN)
+#define SSIF_CR_BIT_TEN     (1u << SSIF_CR_SHIFT_TEN)
+#define SSIF_CR_BIT_REN     (1u << SSIF_CR_SHIFT_REN)
+#define SSIF_CR_INT_ERR_MASK    (SSIF_CR_BIT_TUIEN | SSIF_CR_BIT_TOIEN | SSIF_CR_BIT_RUIEN | SSIF_CR_BIT_ROIEN)
+
+#define SSIF_SR_SHIFT_TUIRQ (29u)
+#define SSIF_SR_SHIFT_TOIRQ (28u)
+#define SSIF_SR_SHIFT_RUIRQ (27u)
+#define SSIF_SR_SHIFT_ROIRQ (26u)
+#define SSIF_SR_SHIFT_IIRQ  (25u)
+#define SSIF_SR_SHIFT_IDST  ( 0u)
+
+#define SSIF_SR_BIT_TUIRQ   (1u << SSIF_SR_SHIFT_TUIRQ)
+#define SSIF_SR_BIT_TOIRQ   (1u << SSIF_SR_SHIFT_TOIRQ)
+#define SSIF_SR_BIT_RUIRQ   (1u << SSIF_SR_SHIFT_RUIRQ)
+#define SSIF_SR_BIT_ROIRQ   (1u << SSIF_SR_SHIFT_ROIRQ)
+#define SSIF_SR_BIT_IIRQ    (1u << SSIF_SR_SHIFT_IIRQ)
+#define SSIF_SR_BIT_IDST    (1u << SSIF_SR_SHIFT_IDST)
+#define SSIF_SR_INT_ERR_MASK    (SSIF_SR_BIT_TUIRQ | SSIF_SR_BIT_TOIRQ | SSIF_SR_BIT_RUIRQ | SSIF_SR_BIT_ROIRQ)
+
+#define SSIF_FCR_SHIFT_TIE      (3u)
+#define SSIF_FCR_SHIFT_RIE      (2u)
+#define SSIF_FCR_SHIFT_TFRST    (1u)
+#define SSIF_FCR_SHIFT_RFRST    (0u)
+
+#define SSIF_FCR_BIT_TIE   (1u << SSIF_FCR_SHIFT_TIE)
+#define SSIF_FCR_BIT_RIE   (1u << SSIF_FCR_SHIFT_RIE)
+#define SSIF_FCR_BIT_TFRST (1u << SSIF_FCR_SHIFT_TFRST)
+#define SSIF_FCR_BIT_RFRST (1u << SSIF_FCR_SHIFT_RFRST)
+
+#define SSIF_TDMR_SHIFT_CONT    (8u)
+#define SSIF_TDMR_SHIFT_TDM     (0u)
+
+#define SSIF_TDMR_BIT_CONT (1u << SSIF_TDMR_SHIFT_CONT)
+#define SSIF_TDMR_BIT_TDM  (1u << SSIF_TDMR_SHIFT_TDM)
+
+/* noise canceled bit */
+#define GPIO_SNCR_BIT_SSI5NCE  (1u << 5)
+#define GPIO_SNCR_BIT_SSI4NCE  (1u << 4)
+#define GPIO_SNCR_BIT_SSI3NCE  (1u << 3)
+#define GPIO_SNCR_BIT_SSI2NCE  (1u << 2)
+#define GPIO_SNCR_BIT_SSI1NCE  (1u << 1)
+#define GPIO_SNCR_BIT_SSI0NCE  (1u << 0)
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+typedef enum {
+    SSIF_DRVSTS_UNINIT = 0,
+    SSIF_DRVSTS_INIT
+} ssif_drv_stat_t;
+
+typedef enum
+{
+    SSIF_CHSTS_UNINIT = 0,
+    SSIF_CHSTS_INIT,
+    SSIF_CHSTS_OPEN
+} ssif_ch_stat_t;
+
+typedef enum
+{
+    SSIF_ASYNC_W = 0,
+    SSIF_ASYNC_R
+} ssif_rw_mode_t;
+
+/** Serial bit clock direction */
+typedef enum
+{
+    SSIF_CFG_CLOCK_IN  = 0,  /**< Clock IN - Slave mode */
+    SSIF_CFG_CLOCK_OUT = 1   /**< Clock OUT - Master mode */
+} ssif_chcfg_clock_dir_t;
+
+
+/** Serial word select direction */
+typedef enum
+{
+    SSIF_CFG_WS_IN  = 0,     /**< Word select IN - Slave mode */
+    SSIF_CFG_WS_OUT = 1      /**< Word select OUT - Master mode */
+} ssif_chcfg_ws_dir_t;
+
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+typedef struct ssif_info_ch
+{
+    uint32_t    channel;
+    bool_t      enabled;
+    bool_t      slave_mode;
+    uint32_t    sample_freq;
+    ssif_ch_stat_t ch_stat;
+    osSemaphoreId  sem_access;
+    AHF_S       tx_que;
+    AHF_S       rx_que;
+    int_t       dma_rx_ch;
+    int_t       dma_tx_ch;
+    bool_t      is_full_duplex;         /* full/half duplex */
+    int_t       openflag;
+    AIOCB*      p_aio_tx_curr;
+    AIOCB*      p_aio_tx_next;
+    AIOCB*      p_aio_rx_curr;
+    AIOCB*      p_aio_rx_next;
+    ssif_chcfg_cks_t                clk_select;
+    ssif_chcfg_multi_ch_t           multi_ch;
+    ssif_chcfg_data_word_t          data_word;
+    ssif_chcfg_system_word_t        system_word;
+    ssif_chcfg_clock_dir_t          clock_direction;
+    ssif_chcfg_ws_dir_t             ws_direction;
+    ssif_chcfg_clock_pol_t          bclk_pol;
+    ssif_chcfg_ws_pol_t             ws_pol;
+    ssif_chcfg_padding_pol_t        padding_pol;
+    ssif_chcfg_serial_alignment_t   serial_alignment;
+    ssif_chcfg_parallel_alignment_t parallel_alignment;
+    ssif_chcfg_ws_delay_t           ws_delay;
+    ssif_chcfg_noise_cancel_t       noise_cancel;
+    ssif_chcfg_tdm_t                tdm_mode;
+    ssif_chcfg_ckdv_t               clk_div;
+    ssif_chcfg_romdec_t             romdec_direct;
+} ssif_info_ch_t;
+
+
+typedef struct ssif_info_drv
+{
+    ssif_drv_stat_t drv_stat;
+    ssif_info_ch_t  info_ch[SSIF_NUM_CHANS];
+} ssif_info_drv_t;
+
+extern volatile struct st_ssif* const g_ssireg[SSIF_NUM_CHANS];
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+#if(1) /* mbed */
+int_t SSIF_InitialiseOne(const int_t channel, const ssif_channel_cfg_t* const p_cfg_data);
+int_t SSIF_UnInitialiseOne(const int_t channel);
+#endif /* end mbed */
+int_t SSIF_Initialise(const ssif_channel_cfg_t* const p_cfg_data);
+int_t SSIF_UnInitialise(void);
+int_t SSIF_EnableChannel(ssif_info_ch_t* const p_info_ch);
+int_t SSIF_DisableChannel(ssif_info_ch_t* const p_info_ch);
+void  SSIF_ErrorRecovery(ssif_info_ch_t* const p_info_ch);
+
+void SSIF_PostAsyncIo(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio);
+void SSIF_PostAsyncCancel(ssif_info_ch_t* const p_info_ch, AIOCB* const p_aio);
+
+int_t SSIF_IOCTL_ConfigChannel(ssif_info_ch_t* const p_info_ch,
+                const ssif_channel_cfg_t* const p_ch_cfg);
+int_t SSIF_IOCTL_GetStatus(const ssif_info_ch_t* const p_info_ch, uint32_t* const p_status);
+
+int_t SSIF_InitDMA(ssif_info_ch_t* const p_info_ch);
+void SSIF_UnInitDMA(ssif_info_ch_t* const p_info_ch);
+void SSIF_CancelDMA(const ssif_info_ch_t* const p_info_ch);
+int_t SSIF_RestartDMA(ssif_info_ch_t* const p_info_ch);
+
+int_t SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl);
+int_t SSIF_DWLtoLen(const ssif_chcfg_data_word_t ssicr_dwl);
+
+extern ssif_info_drv_t g_ssif_info_drv;
+
+#endif /* SSIF_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/ssif/ssif_cfg.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,560 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_cfg.c
+* $Rev: 1674 $
+* $Date:: 2015-05-29 16:35:57 +0900#$
+* Description : SSIF driver userown functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "dma_if.h"
+#include "ssif_if.h"
+#include "iodefine.h"
+#include "Renesas_RZ_A1.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+/***** Audio Clock Source Configurations *****/
+/* AUDIO_X1 : Connect to CPU Board X8(22579200Hz) */
+#define SSIF_AUDIO_X1  (22579200u)
+
+/* AUDIO_CLK: Connect to option board J7(no clock on board) */
+#define SSIF_AUDIO_CLK (0u)
+
+/* SSICR CKDV divieded value */
+#define SSIF_AUDIO_CLK_DIV_1    (1u)
+#define SSIF_AUDIO_CLK_DIV_2    (2u)
+#define SSIF_AUDIO_CLK_DIV_4    (4u)
+#define SSIF_AUDIO_CLK_DIV_8    (8u)
+#define SSIF_AUDIO_CLK_DIV_16   (16u)
+#define SSIF_AUDIO_CLK_DIV_32   (32u)
+#define SSIF_AUDIO_CLK_DIV_64   (64u)
+#define SSIF_AUDIO_CLK_DIV_128  (128u)
+#define SSIF_AUDIO_CLK_DIV_6    (6u)
+#define SSIF_AUDIO_CLK_DIV_12   (12u)
+#define SSIF_AUDIO_CLK_DIV_24   (24u)
+#define SSIF_AUDIO_CLK_DIV_48   (48u)
+#define SSIF_AUDIO_CLK_DIV_96   (96u)
+
+/* SSIF channel number */
+#define SSIF_CHNUM_0    (0u)
+#define SSIF_CHNUM_1    (1u)
+#define SSIF_CHNUM_2    (2u)
+#define SSIF_CHNUM_3    (3u)
+#define SSIF_CHNUM_4    (4u)
+#define SSIF_CHNUM_5    (5u)
+
+/* misc constant value */
+#define SSIF_I2S_LR_CH  (2u)
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+/******************************************************************************
+* Function Name: R_SSIF_Userdef_InitPinMux
+* @brief         This function initialise pin multiplex settings.
+*
+*                Description:<br>
+*                R7S72100 Boards depended pin connections bellow<br>
+*                Clock settings<br>
+*                  AUDIO_X1 : Private use pin(nothing to do)<br>
+*                  AUDIO_X2 : No connection<br>
+*                  AUDIO_CLK: Working with SSIF5<br>
+*                Channel settings<br>
+*                  SSIF0    : Fully connected to WM8978<br>
+*                  SSIF1    : Read only (NC:SSITxD1) connected to CD Deck<br>
+*                  SSIF2    : No connection<br>
+*                  SSIF3    : Write only (NC:SSIRxD3) connected to AK4353<br>
+*                  SSIF4    : Fully connected to AK4353<br>
+*                  SSIF5    : Fully connected to HCI
+* @param[in]     ssif_ch      :channel number.
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+int_t R_SSIF_Userdef_InitPinMux(const uint32_t ssif_ch)
+{
+#if(1) /* mbed */
+    UNUSED_ARG(ssif_ch);
+
+    return ESUCCESS;
+#else  /* not mbed */
+    int_t ercd = ESUCCESS;
+    int_t was_masked;
+
+#if defined (__ICCARM__)
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif
+
+    /* -> IPA R2.4.2 : This is implicit type conversion that doesn't have bad effect on writing to 16bit register. */
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            /* SSISCK0(P4_4, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N4);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS0(P4_5, Alternative Mode 5,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N5);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD0(P4_6, Alternative Mode 5,Input) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N6);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD0(P4_7, Alternative Mode 5,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC4   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N7);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N7);
+            break;
+
+        case SSIF_CHNUM_1:
+            /* SSISCK1(P3_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS1(P3_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC3 |=  (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD1(P3_6, Alternative Mode 3,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC3   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE3 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD1:  no connection */
+            break;
+
+        case SSIF_CHNUM_2:
+            /* SSISCK2:  no connection */
+            /* SSIWS2:   no connection */
+            /* SSIDATA2: no connection */
+            break;
+
+        case SSIF_CHNUM_3:
+            /* SSISCK3(P4_12, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N12);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N12);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N12);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N12);
+
+            GPIO.PIPC4  |= (uint16_t) GPIO_BIT_N12;
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N12);
+
+            /* SSIWS3(P4_13, Alternative Mode 6,InputOutput) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N13);
+
+            GPIO.PBDC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N13);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N13);
+
+            GPIO.PIPC4  |= (uint16_t) (GPIO_BIT_N13);
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N13);
+
+            /* SSIRxD3:  no connection */
+
+            /* SSITxD3(P4_15, Alternative Mode 6,Output) */
+            GPIO.PIBC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PM4    |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PMC4   &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PIPC4  &= (uint16_t)~(GPIO_BIT_N15);
+
+            GPIO.PBDC4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PFCE4  &= (uint16_t)~(GPIO_BIT_N15);
+            GPIO.PFCAE4 |= (uint16_t) (GPIO_BIT_N15);
+
+            GPIO.PMC4   |= (uint16_t) (GPIO_BIT_N15);
+            GPIO.PM4    &= (uint16_t)~(GPIO_BIT_N15);
+            break;
+
+        case SSIF_CHNUM_4:
+            /* SSISCK4(P11_4, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS4(P11_5, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC11  |= (uint16_t) GPIO_BIT_N5;
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIDATA4(P11_6, Alternative Mode 3,InputOutput) */
+            GPIO.PIBC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC11  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM11    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC11  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFC11   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFCE11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE11 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC11  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC11   |= (uint16_t) (GPIO_BIT_N6);
+            break;
+
+        case SSIF_CHNUM_5:
+            /* SSISCK5(P2_4, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N4);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N4);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N4);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N4);
+
+            /* SSIWS5(P2_5, Alternative Mode 4,InputOutput) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N5);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PBDC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N5);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N5);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N5);
+
+            /* SSIRxD5(P2_6, Alternative Mode 4,Input) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N6);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N6);
+
+            GPIO.PIPC2  |= (uint16_t) (GPIO_BIT_N6);
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N6);
+
+            /* SSITxD5(P2_7, Alternative Mode 4,Output) */
+            GPIO.PIBC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PM2    |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PMC2   &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PIPC2  &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PBDC2  &= (uint16_t)~(GPIO_BIT_N7);
+            GPIO.PFC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCE2  |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PFCAE2 &= (uint16_t)~(GPIO_BIT_N7);
+
+            GPIO.PMC2   |= (uint16_t) (GPIO_BIT_N7);
+            GPIO.PM2    &= (uint16_t)~(GPIO_BIT_N7);
+
+            /* AUDIO_CLK(P3_1, Alternative Mode 6,Input) */
+            GPIO.PIBC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PM3    |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PIPC3  &= (uint16_t)~(GPIO_BIT_N1);
+
+            GPIO.PBDC3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFC3   |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PFCE3  &= (uint16_t)~(GPIO_BIT_N1);
+            GPIO.PFCAE3 |= (uint16_t) (GPIO_BIT_N1);
+
+            GPIO.PIPC3  |= (uint16_t) (GPIO_BIT_N1);
+            GPIO.PMC3   |= (uint16_t) (GPIO_BIT_N1);
+            break;
+
+        default:
+            ercd = EINVAL;
+            break;
+    }
+    /* <- IPA R2.4.2 */
+
+    if (0 == was_masked)
+    {
+        __enable_irq();
+    }
+
+    return ercd;
+#endif /* end mbed */
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Userdef_SetClockDiv
+* @brief         This function make a value of divieded audio clock.
+*
+*                Description:<br>
+*
+* @param[in]     p_ch_cfg     :pointer of channel configuration parameter.
+* @param[in,out] p_clk_div    :pointer of SSICR register CKDV value
+* @retval        ESUCCESS     :Success.
+* @retval        error code   :Failure.
+******************************************************************************/
+int_t R_SSIF_Userdef_SetClockDiv(const ssif_channel_cfg_t* const p_ch_cfg, ssif_chcfg_ckdv_t* const p_clk_div)
+{
+    uint32_t input_clk;
+    uint32_t dot_clk;
+    uint32_t n_syswd_per_smp;
+    uint32_t syswd_len;
+    uint32_t smp_freq;
+    uint32_t result;
+    uint32_t division;
+    int_t ret = ESUCCESS;
+
+    if ((NULL == p_ch_cfg) || (NULL == p_clk_div))
+    {
+        ret = EFAULT;
+    }
+    else
+    {
+        if (SSIF_CFG_CKS_AUDIO_X1 == p_ch_cfg->clk_select)
+        {
+            input_clk = SSIF_AUDIO_X1;
+        }
+        else if (SSIF_CFG_CKS_AUDIO_CLK == p_ch_cfg->clk_select)
+        {
+            input_clk = SSIF_AUDIO_CLK;
+        }
+        else
+        {
+            input_clk = 0u;
+        }
+
+        if (0u == input_clk)
+        {
+            ret = EINVAL;
+        }
+     
+        if (ESUCCESS == ret)
+        {
+            syswd_len = (uint32_t)R_SSIF_SWLtoLen(p_ch_cfg->system_word);
+            smp_freq = p_ch_cfg->sample_freq;
+
+            if (SSIF_CFG_DISABLE_TDM == p_ch_cfg->tdm_mode)
+            {
+                /* I2S format has 2 system_words */
+                n_syswd_per_smp = SSIF_I2S_LR_CH;
+            }
+            else
+            {
+                /* TDM frame has [(CHNL+1) * 2] system_words */
+                n_syswd_per_smp = (((uint32_t)p_ch_cfg->multi_ch) + 1) * SSIF_I2S_LR_CH;
+            }
+
+            dot_clk = syswd_len * n_syswd_per_smp * smp_freq;
+
+            if (0u == dot_clk)
+            {
+                ret = EINVAL;
+            }
+            else
+            {
+                /* check if input audio clock can be divided by dotclock */
+                result = input_clk % dot_clk;
+
+                if (0u != result)
+                {
+                    /* cannot create dotclock from input audio clock */
+                    ret = EINVAL;
+                }
+                else
+                {
+                    division = input_clk / dot_clk;
+
+                    switch (division)
+                    {
+                    case SSIF_AUDIO_CLK_DIV_1:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_1;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_2:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_2;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_4:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_4;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_8:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_8;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_16:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_16;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_32:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_32;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_64:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_64;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_128:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_128;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_6:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_6;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_12:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_12;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_24:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_24;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_48:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_48;
+                        break;
+                    case SSIF_AUDIO_CLK_DIV_96:
+                        *p_clk_div = SSIF_CFG_CKDV_BITS_96;
+                        break;
+                    default:
+                        ret = EINVAL;
+                        break;
+                    }
+                }
+            }
+        }
+    }
+
+    return ret;
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/ssif/ssif_dma.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,836 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_dma.c
+* $Rev: 1645 $
+* $Date:: 2015-05-21 10:35:06 +0900#$
+* Description : SSIF driver DMA functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "iodefine.h"
+#include "ssif_int.h"
+#include "dma_if.h"
+#include "Renesas_RZ_A1.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define SSIF_DUMMY_DMA_BUF_SIZE (4096u)
+#define SSIF_I2S_LR_CH          (2u)
+
+#define SSIF_ROMDEC_DMA_SIZE    (2352u)
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+static void SSIF_DMA_TxCallback(union sigval param);
+static void SSIF_DMA_RxCallback(union sigval param);
+
+static const dma_res_select_t gb_ssif_dma_tx_resource[SSIF_NUM_CHANS] =
+{
+    DMA_RS_SSITXI0,
+    DMA_RS_SSITXI1,
+    DMA_RS_SSIRTI2,
+    DMA_RS_SSITXI3,
+    DMA_RS_SSIRTI4,
+    DMA_RS_SSITXI5
+};
+
+static const dma_res_select_t gb_ssif_dma_rx_resource[SSIF_NUM_CHANS] =
+{
+    DMA_RS_SSIRXI0,
+    DMA_RS_SSIRXI1,
+    DMA_RS_SSIRTI2,
+    DMA_RS_SSIRXI3,
+    DMA_RS_SSIRTI4,
+    DMA_RS_SSIRXI5
+};
+
+static AIOCB gb_ssif_dma_tx_end_aiocb[SSIF_NUM_CHANS];
+static AIOCB gb_ssif_dma_rx_end_aiocb[SSIF_NUM_CHANS];
+
+static dma_trans_data_t gb_ssif_txdma_dummy_trparam[SSIF_NUM_CHANS];
+static dma_trans_data_t gb_ssif_rxdma_dummy_trparam[SSIF_NUM_CHANS];
+
+static uint32_t ssif_tx_dummy_buf[SSIF_DUMMY_DMA_BUF_SIZE];
+static uint32_t ssif_rx_dummy_buf[SSIF_DUMMY_DMA_BUF_SIZE];
+
+/******************************************************************************
+* Function Name: SSIF_InitDMA
+* @brief         Allocate and Setup DMA_CH for specified SSIF channel.
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object.
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_InitDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    int_t dma_ret;
+    uint32_t ssif_ch;
+    int32_t dma_ercd;
+    dma_ch_setup_t  dma_ch_setup;
+    uint32_t n_datawd_per_smp;
+    uint32_t byte_per_smp;
+    uint32_t dummy_smp_count;
+    uint32_t dummy_dma_size = 0u;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* calculate dummy dma transfer size */
+        n_datawd_per_smp = (uint32_t)(p_info_ch->multi_ch + 1) * SSIF_I2S_LR_CH;
+        byte_per_smp = n_datawd_per_smp * (uint32_t)SSIF_DWLtoLen(p_info_ch->data_word);
+
+        if (0u == byte_per_smp)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            dummy_smp_count = SSIF_DUMMY_DMA_BUF_SIZE / byte_per_smp;
+            dummy_dma_size = dummy_smp_count * byte_per_smp;
+
+            if (0u == dummy_dma_size)
+            {
+                ercd = EFAULT;
+            }
+        }
+
+        /* allocate DMA Channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY == p_info_ch->openflag)
+            {
+                p_info_ch->dma_tx_ch = -1;
+            }
+            else
+            {
+                dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    p_info_ch->dma_tx_ch = -1;
+                    ercd = ENOMEM;
+                }
+                else
+                {
+                    p_info_ch->dma_tx_ch = dma_ret;
+                    ercd = ESUCCESS;
+                }
+            }
+        }
+
+        /* allocate DMA Channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY == p_info_ch->openflag)
+            {
+                p_info_ch->dma_rx_ch = -1;
+            }
+            else
+            {
+                dma_ret = R_DMA_Alloc(DMA_ALLOC_CH, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    p_info_ch->dma_rx_ch = -1;
+                    ercd = ENOMEM;
+                }
+                else
+                {
+                    p_info_ch->dma_rx_ch = dma_ret;
+                    ercd = ESUCCESS;
+                }
+            }
+        }
+
+        /* setup DMA channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY != p_info_ch->openflag)
+            {
+                AIOCB* const p_tx_aio = &gb_ssif_dma_tx_end_aiocb[ssif_ch];
+                p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_tx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_TxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_tx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_DES;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.p_aio = p_tx_aio;
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+            }
+        }
+
+        /* setup DMA channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY != p_info_ch->openflag)
+            {
+                AIOCB* const p_rx_aio = &gb_ssif_dma_rx_end_aiocb[ssif_ch];
+                p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_rx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_RxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_rx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_SRC;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.src_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.p_aio = p_rx_aio;
+
+                if (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                    != p_info_ch->romdec_direct.mode)
+                {
+                    dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT;
+                }
+                else
+                {
+                    dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                }
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_txdma_dummy_trparam[ssif_ch].src_addr = (void*)&ssif_tx_dummy_buf[0];
+                gb_ssif_txdma_dummy_trparam[ssif_ch].dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR;
+                gb_ssif_txdma_dummy_trparam[ssif_ch].count = dummy_dma_size;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY != p_info_ch->openflag)
+            {
+                if (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                    != p_info_ch->romdec_direct.mode)
+                {
+                    /* setup short dummy transfer */
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR;
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ssif_rx_dummy_buf[0];
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].count = dummy_dma_size;
+                }
+                else
+                {
+                    /* setup ROMDEC direct input transfer */
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR;
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ROMDEC.STRMDIN0;
+                    gb_ssif_rxdma_dummy_trparam[ssif_ch].count = SSIF_ROMDEC_DMA_SIZE;
+                }
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+            }
+        }
+
+        /* enable ssif transfer */
+        if (ESUCCESS == ercd)
+        {
+            /* clear status and enable error interrupt */
+            SSIF_EnableErrorInterrupt(ssif_ch);
+
+            /* enable end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR |= SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE;
+
+            if (O_RDWR == p_info_ch->openflag)
+            {
+                /* start write and read DMA at the same time */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN;
+            }
+            else if (O_WRONLY == p_info_ch->openflag)
+            {
+                /* start write DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN;
+            }
+            else if (O_RDONLY == p_info_ch->openflag)
+            {
+                /* start read DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_REN;
+            }
+            else
+            {
+                ercd = EINVAL;
+            }
+        }
+
+        /* cleanup dma resources when error occured */
+        if (ESUCCESS != ercd)
+        {
+            if (-1 != p_info_ch->dma_tx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+
+            if (-1 != p_info_ch->dma_rx_ch)
+            {
+                uint32_t remain;
+                dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+            }
+
+            if (-1 != p_info_ch->dma_tx_ch)
+            {
+                dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+                p_info_ch->dma_tx_ch = -1;
+            }
+
+            if (-1 != p_info_ch->dma_rx_ch)
+            {
+                dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    /* NON_NOTICE_ASSERT: unexpected dma error */
+                }
+                p_info_ch->dma_rx_ch = -1;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_UnInitDMA
+* @brief         Free DMA_CH for specified SSIF channel.
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object.
+* @retval        none
+******************************************************************************/
+void SSIF_UnInitDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t dma_ret;
+    int32_t dma_ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            dma_ret = R_DMA_Free(p_info_ch->dma_tx_ch, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+            p_info_ch->dma_tx_ch = -1;
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            dma_ret = R_DMA_Free(p_info_ch->dma_rx_ch, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+            p_info_ch->dma_rx_ch = -1;
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_RestartDMA
+* @brief         Setup DMA_CH for specified SSIF channel(without allocate)
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object.
+* @retval        ESUCCESS   :Success.
+* @retval        error code :Failure.
+******************************************************************************/
+int_t SSIF_RestartDMA(ssif_info_ch_t* const p_info_ch)
+{
+    int_t ercd = ESUCCESS;
+    int_t dma_ret;
+    uint32_t ssif_ch;
+    int32_t dma_ercd;
+    dma_ch_setup_t  dma_ch_setup;
+    uint32_t n_datawd_per_smp;
+    uint32_t byte_per_smp;
+    uint32_t dummy_smp_count;
+    uint32_t dummy_dma_size = 0u;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        /* calculate dummy dma transfer size */
+        n_datawd_per_smp = (uint32_t)(p_info_ch->multi_ch + 1) * SSIF_I2S_LR_CH;
+        byte_per_smp = n_datawd_per_smp * (uint32_t)SSIF_DWLtoLen(p_info_ch->data_word);
+
+        if (0u == byte_per_smp)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            dummy_smp_count = SSIF_DUMMY_DMA_BUF_SIZE / byte_per_smp;
+            dummy_dma_size = dummy_smp_count * byte_per_smp;
+
+            if (0u == dummy_dma_size)
+            {
+                ercd = EFAULT;
+            }
+        }
+
+        /* setup DMA channel for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY != p_info_ch->openflag)
+            {
+                AIOCB* const p_tx_aio = &gb_ssif_dma_tx_end_aiocb[ssif_ch];
+                p_tx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_tx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_tx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_TxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_tx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_DES;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.src_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.p_aio = p_tx_aio;
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_tx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+            }
+        }
+
+        /* setup DMA channel for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY != p_info_ch->openflag)
+            {
+                AIOCB* const p_rx_aio = &gb_ssif_dma_rx_end_aiocb[ssif_ch];
+                p_rx_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+                p_rx_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_info_ch;
+                p_rx_aio->aio_sigevent.sigev_notify_function = &SSIF_DMA_RxCallback;
+
+                dma_ch_setup.resource = gb_ssif_dma_rx_resource[ssif_ch];
+                dma_ch_setup.direction = DMA_REQ_SRC;
+                dma_ch_setup.dst_width = DMA_UNIT_4;
+                dma_ch_setup.src_width = DMA_UNIT_4;
+                dma_ch_setup.dst_cnt = DMA_ADDR_INCREMENT;
+                dma_ch_setup.src_cnt = DMA_ADDR_FIX;
+                dma_ch_setup.p_aio = p_rx_aio;
+
+                dma_ret = R_DMA_Setup(p_info_ch->dma_rx_ch, &dma_ch_setup, &dma_ercd);
+
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for write(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_RDONLY != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_txdma_dummy_trparam[ssif_ch].src_addr = (void*)&ssif_tx_dummy_buf[0];
+                gb_ssif_txdma_dummy_trparam[ssif_ch].dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR;
+                gb_ssif_txdma_dummy_trparam[ssif_ch].count = dummy_dma_size;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+            }
+        }
+
+        /* start DMA dummy transfer for read(if necessary) */
+        if (ESUCCESS == ercd)
+        {
+            if (O_WRONLY != p_info_ch->openflag)
+            {
+                /* setup short dummy transfer */
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR;
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].dst_addr = (void*)&ssif_rx_dummy_buf[0];
+                gb_ssif_rxdma_dummy_trparam[ssif_ch].count = dummy_dma_size;
+
+                dma_ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                if (EERROR == dma_ret)
+                {
+                    ercd = EFAULT;
+                }
+                else
+                {
+                    dma_ret = R_DMA_Start(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &dma_ercd);
+                    if (EERROR == dma_ret)
+                    {
+                        ercd = EFAULT;
+                    }
+                }
+            }
+        }
+
+        /* enable ssif transfer */
+        if (ESUCCESS == ercd)
+        {
+            /* clear status and enable error interrupt */
+            SSIF_EnableErrorInterrupt(ssif_ch);
+
+            /* enable end interrupt */
+            g_ssireg[ssif_ch]->SSIFCR |= SSIF_FCR_BIT_TIE | SSIF_FCR_BIT_RIE;
+
+            if (O_RDWR == p_info_ch->openflag)
+            {
+                /* start write and read DMA at the same time */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN | SSIF_CR_BIT_REN;
+            }
+            else if (O_WRONLY == p_info_ch->openflag)
+            {
+                /* start write DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_TEN;
+            }
+            else if (O_RDONLY == p_info_ch->openflag)
+            {
+                /* start read DMA only */
+                g_ssireg[ssif_ch]->SSICR  |= SSIF_CR_BIT_REN;
+            }
+            else
+            {
+                ercd = EINVAL;
+            }
+        }
+    }
+
+    return ercd;
+}
+
+/******************************************************************************
+* Function Name: SSIF_CancelDMA
+* @brief         Pause DMA transfer for specified SSIF channel.
+*
+*                Description:<br>
+*                
+* @param[in,out] p_info_ch  :channel object.
+* @retval        none
+******************************************************************************/
+void SSIF_CancelDMA(const ssif_info_ch_t* const p_info_ch)
+{
+    int_t dma_ret;
+    int32_t dma_ercd;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        if (-1 != p_info_ch->dma_tx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_tx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+
+        if (-1 != p_info_ch->dma_rx_ch)
+        {
+            uint32_t remain;
+            dma_ret = R_DMA_Cancel(p_info_ch->dma_rx_ch, &remain, &dma_ercd);
+            if (EERROR == dma_ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected dma error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+Private functions                                                               
+******************************************************************************/
+
+/******************************************************************************
+* Function Name: SSIF_DMA_TxCallback
+* @brief         DMA callback function
+*
+*                Description:<br>
+*                
+* @param[in]     param      :callback param
+* @retval        none
+******************************************************************************/
+static void SSIF_DMA_TxCallback(const union sigval param)
+{
+    ssif_info_ch_t* const p_info_ch = param.sival_ptr;
+    uint32_t ssif_ch;
+    dma_trans_data_t dma_data_next;
+    int_t ercd = ESUCCESS;
+    int_t ret;
+
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (NULL == p_info_ch->p_aio_tx_curr)
+        {
+            /* now complete dummy transfer, It isn't neccessary to signal. */
+        }
+        else
+        {
+            /* now complete user request transfer, Signal to application */
+
+            /* return aio complete */
+            p_info_ch->p_aio_tx_curr->aio_return = (ssize_t)p_info_ch->p_aio_tx_curr->aio_nbytes;
+            ahf_complete(&p_info_ch->tx_que, p_info_ch->p_aio_tx_curr);
+        }
+
+        /* copy next to curr(even if it's NULL) */
+        p_info_ch->p_aio_tx_curr = p_info_ch->p_aio_tx_next;
+
+        /* get next request(It's maybe NULL) */
+        p_info_ch->p_aio_tx_next = ahf_removehead(&p_info_ch->tx_que);
+
+        if (NULL != p_info_ch->p_aio_tx_next)
+        {
+            /* add user request */
+            dma_data_next.dst_addr = (void*)&g_ssireg[ssif_ch]->SSIFTDR;
+            dma_data_next.src_addr = (void*)p_info_ch->p_aio_tx_next->aio_buf;
+            dma_data_next.count = (uint32_t)p_info_ch->p_aio_tx_next->aio_nbytes;
+
+            ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &dma_data_next, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+        else
+        {
+            /* add dummy request */
+            ret = R_DMA_NextData(p_info_ch->dma_tx_ch, &gb_ssif_txdma_dummy_trparam[ssif_ch], &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DMA_RxCallback
+* @brief         DMA callback function
+*
+*                Description:<br>
+*                
+* @param[in]     param      :callback param
+* @retval        none
+******************************************************************************/
+static void SSIF_DMA_RxCallback(const union sigval param)
+{
+    ssif_info_ch_t* const p_info_ch = param.sival_ptr;
+    uint32_t ssif_ch;
+    dma_trans_data_t dma_data_next;
+    int_t ercd = ESUCCESS;
+    int_t ret;
+
+    if (NULL == p_info_ch)
+    {
+        /* NON_NOTICE_ASSERT: illegal pointer */
+    }
+    else
+    {
+        ssif_ch = p_info_ch->channel;
+
+        if (NULL == p_info_ch->p_aio_rx_curr)
+        {
+            /* now complete dummy transfer, It isn't neccessary to signal. */
+        }
+        else
+        {
+            /* now complete user request transfer, Signal to application */
+
+            /* return aio complete */
+            p_info_ch->p_aio_rx_curr->aio_return = (ssize_t)p_info_ch->p_aio_rx_curr->aio_nbytes;
+            ahf_complete(&p_info_ch->rx_que, p_info_ch->p_aio_rx_curr);
+        }
+
+        /* copy next to curr(even if it's NULL) */
+        p_info_ch->p_aio_rx_curr = p_info_ch->p_aio_rx_next;
+
+        /* get next request(It's maybe NULL) */
+        p_info_ch->p_aio_rx_next = ahf_removehead(&p_info_ch->rx_que);
+
+        if (NULL != p_info_ch->p_aio_rx_next)
+        {
+            /* add user request */
+            dma_data_next.src_addr = (void*)&g_ssireg[ssif_ch]->SSIFRDR;
+            dma_data_next.dst_addr = (void*)p_info_ch->p_aio_rx_next->aio_buf;
+            dma_data_next.count = (uint32_t)p_info_ch->p_aio_rx_next->aio_nbytes;
+
+            ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &dma_data_next, &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+        else
+        {
+            /* add dummy request */
+            ret = R_DMA_NextData(p_info_ch->dma_rx_ch, &gb_ssif_rxdma_dummy_trparam[ssif_ch], &ercd);
+            if (EERROR == ret)
+            {
+                /* NON_NOTICE_ASSERT: unexpected DMA error */
+            }
+        }
+    }
+
+    return;
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/ssif/ssif_if.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,926 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_if.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* Description : SSIF driver interface functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "cmsis_os.h"
+#if(1) /* mbed */
+#include "r_bsp_cmn.h"
+#else
+#include "ioif_public.h"
+#endif
+#include "ssif.h"
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+#if(1) /* mbed */
+static ssif_drv_stat_t ch_drv_stat[SSIF_NUM_CHANS] = {SSIF_DRVSTS_UNINIT};
+
+static void* R_SSIF_InitOne(const int_t channel, const void* const config_data, int32_t* const p_errno);
+static int_t R_SSIF_UnInitOne(const int_t channel, const void* const driver_instance, int32_t* const p_errno);
+#else  /* not mbed */
+static void* R_SSIF_Init(void* const config_data, int32_t* const p_errno);
+static int_t R_SSIF_UnInit(void* const driver_instance, int32_t* const p_errno);
+#endif /* end mbed */
+static int_t R_SSIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno);
+static int_t R_SSIF_Close(void* const p_fd, int32_t* const p_errno);
+static int_t R_SSIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno);
+static int_t R_SSIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+static int_t R_SSIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+static int_t R_SSIF_Cancel(void* const p_fd, AIOCB* p_aio, int32_t* const p_errno);
+
+static size_t SSIF_StrnLen(const char_t p_str[], const size_t maxlen);
+static int32_t SSIF_Strncmp(const char_t p_str1[], const char_t p_str2[], const uint32_t maxlen);
+static void   SSIF_SetErrCode(const int_t error_code, int32_t* const p_errno);
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: R_SSIF_MakeCbTbl_mbed
+* @brief         Make the SSIF driver function callback table
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        pointer of SSIF driver function callback table
+******************************************************************************/
+/* ->IPA M1.1.1 : This is liblary funciotn that is called from other module. */
+RBSP_MBED_FNS* R_SSIF_MakeCbTbl_mbed(void)
+/* <-IPA M1.1.1 */
+{
+    static RBSP_MBED_FNS ssif_apitbl_mbed;
+
+    ssif_apitbl_mbed.initialise_one   = &R_SSIF_InitOne;
+    ssif_apitbl_mbed.uninitialise_one = &R_SSIF_UnInitOne;
+    ssif_apitbl_mbed.open             = &R_SSIF_Open;
+    ssif_apitbl_mbed.close            = &R_SSIF_Close;
+    ssif_apitbl_mbed.ioctl            = &R_SSIF_Ioctl;
+    ssif_apitbl_mbed.read_a           = &R_SSIF_ReadAsync;
+    ssif_apitbl_mbed.write_a          = &R_SSIF_WriteAsync;
+    ssif_apitbl_mbed.cancel           = &R_SSIF_Cancel;
+
+    return &ssif_apitbl_mbed;
+}
+#else  /* not mbed */
+/******************************************************************************
+* Function Name: R_SSIF_MakeCbTbl
+* @brief         Make the SSIF driver function callback table
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        pointer of SSIF driver function callback table
+******************************************************************************/
+/* ->IPA M1.1.1 : This is liblary funciotn that is called from other module. */
+IOIF_DRV_API* R_SSIF_MakeCbTbl(void)
+/* <-IPA M1.1.1 */
+{
+    static IOIF_DRV_API ssif_apitbl;
+
+    /* ->MISRA 16.4, IPA M4.5.1 : This is IOIF library API type definitnon that can't be modified. */
+    ssif_apitbl.family = IOIF_SERIAL_FAMILY;
+    ssif_apitbl.fns.serial.initialise   = &R_SSIF_Init;
+    ssif_apitbl.fns.serial.uninitialise = &R_SSIF_UnInit;
+    ssif_apitbl.fns.serial.open         = &R_SSIF_Open;
+    ssif_apitbl.fns.serial.close        = &R_SSIF_Close;
+    ssif_apitbl.fns.serial.ioctl        = &R_SSIF_Ioctl;
+    ssif_apitbl.fns.serial.read_a       = &R_SSIF_ReadAsync;
+    ssif_apitbl.fns.serial.write_a      = &R_SSIF_WriteAsync;
+    ssif_apitbl.fns.serial.cancel       = &R_SSIF_Cancel;
+    /* <-MISRA 16.4, IPA M4.5.1 */
+
+    return &ssif_apitbl;
+}
+#endif /* end mbed */
+
+/******************************************************************************
+* Function Name: R_SSIF_SWLtoLen
+* @brief         Convert SSICR:SWL bits to system word length
+*
+*                Description:<br>
+*                
+* @param[in]     ssicr_swl  :SSICR register SWL field value(0 to 7)
+* @retval        8 to 256   :system word length(byte)
+******************************************************************************/
+int_t R_SSIF_SWLtoLen(const ssif_chcfg_system_word_t ssicr_swl)
+{
+    return SSIF_SWLtoLen(ssicr_swl);
+}
+
+/******************************************************************************
+Private functions
+******************************************************************************/
+
+#if(1) /* mbed */
+/******************************************************************************
+* Function Name: R_SSIF_InitOne
+* @brief         Initialise the SSIF driver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel     :channel number
+* @param[in]     config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno     :pointer of error code
+* @retval        not ERRROR  :driver instance.
+* @retval        EERROR      :Failure.
+******************************************************************************/
+/* ->MISRA 16.7, IPA M1.11.1 : This is IOIF library API type definitnon that can't be modified. */
+static void* R_SSIF_InitOne(const int_t channel, const void* const config_data, int32_t* const p_errno)
+/* <-MISRA 16.7, IPA M1.11.1 */
+{
+    int_t ercd;
+    void* p_ret = (void*)EERROR;
+
+    if (NULL == config_data)
+    {
+        ercd = EFAULT;
+    }
+    else if (channel >= SSIF_NUM_CHANS)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        g_ssif_info_drv.drv_stat = SSIF_DRVSTS_INIT;
+        ch_drv_stat[channel] = SSIF_DRVSTS_INIT;
+
+        ercd = SSIF_InitialiseOne(channel, (const ssif_channel_cfg_t*)config_data);
+
+        if (ESUCCESS == ercd)
+        {
+            p_ret = (void*)&g_ssif_info_drv;
+        }
+        else
+        {
+            ch_drv_stat[channel] = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return p_ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_UnInitOne
+* @brief         Uninitialise the SSIF deiver.
+*
+*                Description:<br>
+*                
+* @param[in]     channel         :channel number
+* @param[in,out] driver_instance :driver instance which was returned by<br>
+                                  R_SSIF_Init
+* @param[in,out] p_errno         :pointer of error code
+* @retval        ESUCCESS        :Success.
+* @retval        EERROR          :Failure.
+******************************************************************************/
+static int_t R_SSIF_UnInitOne(const int_t channel, const void* const driver_instance, int32_t* const p_errno)
+{
+    int_t   ercd;
+    int_t   ret = ESUCCESS;
+
+    if (NULL == driver_instance)
+    {
+        ercd = EFAULT;
+    }
+    else if (channel >= SSIF_NUM_CHANS)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SSIF_DRVSTS_INIT != ch_drv_stat[channel])
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            ercd = SSIF_UnInitialiseOne(channel);
+            ch_drv_stat[channel] = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+#else  /* not mbed */
+
+/******************************************************************************
+* Function Name: R_SSIF_Init
+* @brief         Initialise the SSIF driver.
+*
+*                Description:<br>
+*                
+* @param[in]     config_data :pointer of several parameters array per channels
+* @param[in,out] p_errno     :pointer of error code
+* @retval        not ERRROR  :driver instance.
+* @retval        EERROR      :Failure.
+******************************************************************************/
+/* ->MISRA 16.7, IPA M1.11.1 : This is IOIF library API type definitnon that can't be modified. */
+static void* R_SSIF_Init(void* const config_data, int32_t* const p_errno)
+/* <-MISRA 16.7, IPA M1.11.1 */
+{
+    int_t ercd;
+    void* p_ret = (void*)EERROR;
+
+    if (NULL == config_data)
+    {
+        ercd = EFAULT;
+    }
+    else if (SSIF_DRVSTS_UNINIT != g_ssif_info_drv.drv_stat)
+    {
+        ercd = EBUSY;
+    }
+    else
+    {
+        g_ssif_info_drv.drv_stat = SSIF_DRVSTS_INIT;
+
+        ercd = SSIF_Initialise((ssif_channel_cfg_t*)config_data);
+
+        if (ESUCCESS == ercd)
+        {
+            p_ret = (void*)&g_ssif_info_drv;
+        }
+        else
+        {
+            g_ssif_info_drv.drv_stat = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return p_ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_UnInit
+* @brief         Uninitialise the SSIF deiver.
+*
+*                Description:<br>
+*                
+* @param[in,out] driver_instance :driver instance which was returned by<br>
+                                  R_SSIF_Init
+* @param[in,out] p_errno         :pointer of error code
+* @retval        ESUCCESS        :Success.
+* @retval        EERROR          :Failure.
+******************************************************************************/
+static int_t R_SSIF_UnInit(void* const driver_instance, int32_t* const p_errno)
+{
+    int_t   ercd;
+    int_t   ret = ESUCCESS;
+    ssif_info_drv_t* const p_info_drv   = driver_instance;
+
+    if (NULL == p_info_drv)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SSIF_DRVSTS_INIT != p_info_drv->drv_stat)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            ercd = SSIF_UnInitialise();
+            p_info_drv->drv_stat = SSIF_DRVSTS_UNINIT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+#endif /* end mbed */
+
+/******************************************************************************
+* Function Name: R_SSIF_Open
+* @brief         Open an SSIF channel
+*
+*                Description:<br>
+*                
+* @param[in,out] p_drv_instance :driver instance which was returned by<br>
+                                 R_SSIF_Init
+* @param[in]     p_path_name    :string of channel
+* @param[in]     flags          :access mode whether the channel is opened<br>
+                                 for a read or a write
+* @param[in]     mode           :not used
+* @param[in,out] p_errno        :pointer of error code
+* @retval        not EERROR     :channel handle
+* @retval        EERROR         :Failure.
+******************************************************************************/
+static int_t R_SSIF_Open(void* const p_driver_instance, const char_t* const p_path_name, const int_t flags, const int_t mode, int32_t* const p_errno)
+{
+    uint32_t ssif_ch;
+    void* p_channelHandle;
+    size_t len;
+    size_t req_path_len;
+    ssif_info_drv_t* const p_info_drv = p_driver_instance;
+    ssif_info_ch_t* p_info_ch = NULL;
+    int_t ret;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+    static const char_t* const ch_name_string[SSIF_NUM_CHANS] =
+    {
+        SSIF_CHSTR_0,
+        SSIF_CHSTR_1,
+        SSIF_CHSTR_2,
+        SSIF_CHSTR_3,
+        SSIF_CHSTR_4,
+        SSIF_CHSTR_5
+    };
+
+    UNUSED_ARG(mode);
+
+    if ((NULL == p_info_drv) || (NULL == p_path_name))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        req_path_len = strlen(p_path_name);
+        if (0u == req_path_len)
+        {
+            ercd = ENOENT;
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SSIF_DRVSTS_INIT != p_info_drv->drv_stat)
+            {
+                ercd = EFAULT;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* Serch the same pathname */
+            for (ssif_ch = 0u; (ssif_ch < SSIF_NUM_CHANS) && (p_info_ch == NULL); ssif_ch++)
+            {
+                len = SSIF_StrnLen(ch_name_string[ssif_ch], SSIF_MAX_PATH_LEN);
+
+                if (req_path_len < len)
+                {
+                    len = req_path_len;
+                }
+
+                if (0 == SSIF_Strncmp(p_path_name, ch_name_string[ssif_ch], len))
+                {
+                    /* found a match */
+                    p_info_ch = &p_info_drv->info_ch[ssif_ch];
+                }
+            }
+        }
+    }
+
+    if (NULL == p_info_ch)
+    {
+        ercd = ENOENT;
+    }
+    else
+    {
+        if (ESUCCESS == ercd)
+        {
+            if (false == p_info_ch->enabled)
+            {
+                ercd = ENOTSUP;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            if (SSIF_CHSTS_INIT != p_info_ch->ch_stat)
+            {
+                ercd = EBADF;
+            }
+        }
+
+        if (ESUCCESS == ercd)
+        {
+            /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+            os_ret = osSemaphoreWait(p_info_ch->sem_access, osWaitForever);
+            /* <-MISRA 10.6 */
+
+            if ((-1) == os_ret)
+            {
+                ercd = EFAULT;
+            }
+            else
+            {
+                p_info_ch->openflag = flags;
+                p_info_ch->p_aio_tx_curr = NULL;
+                p_info_ch->p_aio_rx_curr = NULL;
+
+                ercd = SSIF_EnableChannel(p_info_ch);
+
+                if (ESUCCESS == ercd)
+                {
+                    p_info_ch->ch_stat = SSIF_CHSTS_OPEN;
+                }
+            }
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    else
+    {
+        p_channelHandle = (void*)p_info_ch;
+        ret = (int_t)p_channelHandle;
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Close
+* @brief         Close an SSIF channel.
+*
+*                Description:<br>
+*                
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_Close(void* const p_fd, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t ret = ESUCCESS;
+    int_t ercd;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+        /* Get semaphore to access the channel data */
+        os_ret = osSemaphoreWait(p_info_ch->sem_access, osWaitForever);
+        /* <-MISRA 10.6 */
+
+        if ((-1) == os_ret)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+            {
+                ercd = EFAULT;
+            }
+            else
+            {
+                SSIF_PostAsyncCancel(p_info_ch, NULL);
+
+                ercd = SSIF_DisableChannel(p_info_ch);
+
+                if (ESUCCESS == ercd)
+                {
+                    p_info_ch->ch_stat = SSIF_CHSTS_INIT;
+                }
+            }
+
+            /* Relese semaphore */
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Ioctl 
+* @brief         IOCTL function of the SSIF deiver
+*
+*                Description:<br>
+*                
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     request    :IOCTL request code
+* @param[in,out] p_buf      :Meaning depends upon request.
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_Ioctl(void* const p_fd, const int_t request, void* const p_buf, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+            os_ret = osSemaphoreWait(p_info_ch->sem_access, osWaitForever);
+            /* <-MISRA 10.6 */
+
+            if ((-1) == os_ret)
+            {
+                ercd = EFAULT;
+            }
+
+            if (ESUCCESS == ercd)
+            {
+                switch (request)
+                {
+                    case SSIF_CONFIG_CHANNEL:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ssif_channel_cfg_t* const ch_info = (ssif_channel_cfg_t*)p_buf;
+                            ercd = SSIF_IOCTL_ConfigChannel(p_info_ch, ch_info);
+                        }
+                        break;
+                    }
+
+                    case SSIF_GET_STATUS:
+                    {
+                        if (NULL == p_buf)
+                        {
+                            ercd = EFAULT;
+                        }
+                        else
+                        {
+                            ercd = SSIF_IOCTL_GetStatus(p_info_ch, (uint32_t*)p_buf);
+                        }
+                        break;
+                    }
+
+                    default:
+                    {
+                        ercd = EINVAL;
+                        break;
+                    }
+                } /* switch */
+            }
+        }
+
+        os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+        if (osOK != os_ercd)
+        {
+            ercd = EFAULT;
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_WriteAsync
+* @brief         Enqueue asynchronous write request
+*
+*                Description:<br>
+*                
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block of write request
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_WriteAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if (((uint32_t)O_RDONLY) == ((uint32_t)p_info_ch->openflag & O_ACCMODE))
+        {
+            ercd = EACCES;
+        }
+        else if (0u == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL;
+        }
+        else
+        {
+            p_aio->aio_return = SSIF_ASYNC_W;
+            SSIF_PostAsyncIo(p_info_ch, p_aio);
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_ReadAsync
+* @brief         Enqueue asynchronous read request
+*
+*                Description:<br>
+*                
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block of read request
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_ReadAsync(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t   ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+
+    if ((NULL == p_info_ch) || (NULL == p_aio))
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        if ((O_WRONLY == ((uint32_t)p_info_ch->openflag & O_ACCMODE))
+            || (SSIF_CFG_ENABLE_ROMDEC_DIRECT
+                == p_info_ch->romdec_direct.mode))
+        {
+            ercd = EACCES;
+        }
+        else if (0u == p_aio->aio_nbytes)
+        {
+            ercd = EINVAL;
+        }
+        else
+        {
+            p_aio->aio_return = SSIF_ASYNC_R;
+            SSIF_PostAsyncIo(p_info_ch, p_aio);
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: R_SSIF_Cancel
+* @brief         Cancel read or write request(s)
+*
+*                Description:<br>
+*                
+* @param[in,out] p_fd       :channel handle which was returned by R_SSIF_Open
+* @param[in]     p_aio      :aio control block to cancel or NULL to cancel all.
+* @param[in,out] p_errno    :pointer of error code
+* @retval        ESUCCESS   :Success.
+* @retval        EERROR     :Failure.
+******************************************************************************/
+static int_t R_SSIF_Cancel(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno)
+{
+    ssif_info_ch_t* const p_info_ch = p_fd;
+    int_t ret = ESUCCESS;
+    int_t ercd = ESUCCESS;
+    osStatus os_ercd;
+    int32_t os_ret;
+
+    if (NULL == p_info_ch)
+    {
+        ercd = EFAULT;
+    }
+    else
+    {
+        /* ->MISRA 10.6 : This macro is defined by CMSIS-RTOS that can't be modified. */
+        /* Get semaphore to access the channel data */
+        os_ret = osSemaphoreWait(p_info_ch->sem_access, osWaitForever);
+        /* <-MISRA 10.6 */
+
+        if ((-1) == os_ret)
+        {
+            ercd = EFAULT;
+        }
+        else
+        {
+            if (SSIF_CHSTS_OPEN != p_info_ch->ch_stat)
+            {
+                ercd = EFAULT;
+            }
+            else
+            {
+                SSIF_PostAsyncCancel(p_info_ch, p_aio);
+            }
+
+            os_ercd = osSemaphoreRelease(p_info_ch->sem_access);
+
+            if (osOK != os_ercd)
+            {
+                ercd = EFAULT;
+            }
+        }
+    }
+
+    if (ESUCCESS != ercd)
+    {
+        ret = EERROR;   /* EERROR(-1) */
+    }
+    SSIF_SetErrCode(ercd, p_errno);
+
+    return ret;
+}
+
+/******************************************************************************
+* Function Name: SSIF_StrnLen 
+* @brief         computes the length of the string
+*
+*                Description:<br>
+*                
+* @param[in]     p_str      :pointer of string.
+* @param[in]     maxlen     :maximum length of inspection
+* @retval        < maxlen   :number of characters in the string
+* @retval        maxlen     :string is longer than maxlen
+******************************************************************************/
+static size_t SSIF_StrnLen(const char_t p_str[], const size_t maxlen)
+{
+    size_t len;
+
+    if (NULL == p_str)
+    {
+        len = 0;
+    }
+    else
+    {
+        for (len = 0; len < maxlen; len++)
+        {
+            if ((int_t)p_str[len] == '\0')
+            {
+                break;
+            }
+        }
+    }
+
+    return len;
+}
+
+/******************************************************************************
+* Function Name: SSIF_Strncmp
+* @brief         Compare two strings
+*
+*                Description:<br>
+*                
+* @param[in]     p_str1     :pointer of string1
+* @param[in]     p_str2     :pointer of string2
+* @param[in]     maxlen     :maximum length of comparison
+* @retval        zero       :strings are same.
+* @retval        non zero   :strings are different.
+******************************************************************************/
+static int32_t SSIF_Strncmp(const char_t p_str1[], const char_t p_str2[], const uint32_t maxlen)
+{
+    int32_t result = 0;
+    uint32_t index;
+
+    if ((NULL == p_str1) || (NULL == p_str2))
+    {
+        result = -1;
+    }
+    else
+    {
+        for (index = 0; index < maxlen; index++)
+        {
+            /* compare charctor */
+            result = ((int_t)p_str1[index]) - ((int_t)p_str2[index]);
+            if ((result != 0)
+                || ((int_t)p_str1[index] == '\0')
+                || ((int_t)p_str2[index] == '\0'))
+            {
+                /* "charactor mismatch" or "end of string" */
+                break;
+            }
+        }
+    }
+
+    return result;
+}
+
+/******************************************************************************
+* Function Name: SSIF_SetErrCode
+* @brief         Set error code to error code pointer.
+*
+*                Description:<br>
+*                If error code pointer is NULL, do nothing.
+* @param[in]     error_code :Error code.
+* @param[in,out] p_errno    :Pointer of set error code.
+* @retval        none
+******************************************************************************/
+static void SSIF_SetErrCode(const int_t error_code, int32_t* const p_errno)
+{
+    if (NULL != p_errno)
+    {
+        *p_errno = error_code;
+    }
+
+    return;
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/ssif/ssif_int.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,355 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+* File Name   : ssif_int.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* Description : SSIF driver interrupt functions
+******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "ssif.h"
+#include "ssif_int.h"
+#include "Renesas_RZ_A1.h"
+#include "gic.h"
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define SSIF_INT_PER_CH     (4u)
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+/******************************************************************************
+ Function prototypes
+ *****************************************************************************/
+
+static void SSIF_ERI0_Handler(void);
+static void SSIF_ERI1_Handler(void);
+static void SSIF_ERI2_Handler(void);
+static void SSIF_ERI3_Handler(void);
+static void SSIF_ERI4_Handler(void);
+static void SSIF_ERI5_Handler(void);
+
+static void SSIF_ERI_Handler(const uint32_t ssif_ch);
+
+/******************************************************************************
+* Function Name: SSIF_InterruptInit
+* @brief         Initialize interrupt setting for SSIF channel.
+*
+*                Description:<br>
+*                Enable interrupt and register interrupt handler.
+* @param[in]     ssif_ch    :SSIF channel
+* @param[in]     int_level  :GIC priority level of interrupt
+* @retval        none
+******************************************************************************/
+void SSIF_InterruptInit(const uint32_t ssif_ch, const uint8_t int_level)
+{
+    uint32_t ret;
+
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            ret = InterruptHandlerRegister(SSII0_IRQn, &SSIF_ERI0_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII0_IRQn, int_level);
+            GIC_SetPriority(SSIRXI0_IRQn, int_level);
+            GIC_SetPriority(SSITXI0_IRQn, int_level);
+            GIC_EnableIRQ(SSII0_IRQn);
+            GIC_EnableIRQ(SSIRXI0_IRQn);
+            GIC_EnableIRQ(SSITXI0_IRQn);
+            break;
+        case SSIF_CHNUM_1:
+            ret = InterruptHandlerRegister(SSII1_IRQn, &SSIF_ERI1_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII1_IRQn, int_level);
+            GIC_SetPriority(SSIRXI1_IRQn, int_level);
+            GIC_SetPriority(SSITXI1_IRQn, int_level);
+            GIC_EnableIRQ(SSII1_IRQn);
+            GIC_EnableIRQ(SSIRXI1_IRQn);
+            GIC_EnableIRQ(SSITXI1_IRQn);
+            break;
+        case SSIF_CHNUM_2:
+            ret = InterruptHandlerRegister(SSII2_IRQn, &SSIF_ERI2_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII2_IRQn, int_level);
+            GIC_SetPriority(SSIRTI2_IRQn, int_level);
+            GIC_EnableIRQ(SSII2_IRQn);
+            GIC_EnableIRQ(SSIRTI2_IRQn);
+            break;
+        case SSIF_CHNUM_3:
+            ret = InterruptHandlerRegister(SSII3_IRQn, &SSIF_ERI3_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII3_IRQn, int_level);
+            GIC_SetPriority(SSIRXI3_IRQn, int_level);
+            GIC_SetPriority(SSITXI3_IRQn, int_level);
+            GIC_EnableIRQ(SSII3_IRQn);
+            GIC_EnableIRQ(SSIRXI3_IRQn);
+            GIC_EnableIRQ(SSITXI3_IRQn);
+            break;
+        case SSIF_CHNUM_4:
+            ret = InterruptHandlerRegister(SSII4_IRQn, &SSIF_ERI4_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII4_IRQn, int_level);
+            GIC_SetPriority(SSIRTI4_IRQn, int_level);
+            GIC_EnableIRQ(SSII4_IRQn);
+            GIC_EnableIRQ(SSIRTI4_IRQn);
+            break;
+        case SSIF_CHNUM_5:
+            ret = InterruptHandlerRegister(SSII5_IRQn, &SSIF_ERI5_Handler);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            GIC_SetPriority(SSII5_IRQn, int_level);
+            GIC_SetPriority(SSIRXI5_IRQn, int_level);
+            GIC_SetPriority(SSITXI5_IRQn, int_level);
+            GIC_EnableIRQ(SSII5_IRQn);
+            GIC_EnableIRQ(SSIRXI5_IRQn);
+            GIC_EnableIRQ(SSITXI5_IRQn);
+            break;
+        /* ->IPA R3.5.2 : There is nothing to do when unusual conditons. */
+        default:
+            /* NON_NOTICE_ASSERT: Illegal channel number */
+            break;
+        /* <-IPA R3.5.2 */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_InterruptShutdown
+* @brief         Uninitialize interrupt setting for SSIF channel.
+*
+*                Description:<br>
+*                Disable interrupt and unregister interrupt handler 
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_InterruptShutdown(const uint32_t ssif_ch)
+{
+    uint32_t ret;
+
+    switch (ssif_ch)
+    {
+        case SSIF_CHNUM_0:
+            GIC_DisableIRQ(SSII0_IRQn);
+            GIC_DisableIRQ(SSIRXI0_IRQn);
+            GIC_DisableIRQ(SSITXI0_IRQn);
+            ret = InterruptHandlerUnregister(SSII0_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_1:
+            GIC_DisableIRQ(SSII1_IRQn);
+            GIC_DisableIRQ(SSIRXI1_IRQn);
+            GIC_DisableIRQ(SSITXI1_IRQn);
+            ret = InterruptHandlerUnregister(SSII1_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_2:
+            GIC_DisableIRQ(SSII2_IRQn);
+            GIC_DisableIRQ(SSIRTI2_IRQn);
+            ret = InterruptHandlerUnregister(SSII2_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_3:
+            GIC_DisableIRQ(SSII3_IRQn);
+            GIC_DisableIRQ(SSIRXI3_IRQn);
+            GIC_DisableIRQ(SSITXI3_IRQn);
+            ret = InterruptHandlerUnregister(SSII3_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_4:
+            GIC_DisableIRQ(SSII4_IRQn);
+            GIC_DisableIRQ(SSIRTI4_IRQn);
+            ret = InterruptHandlerUnregister(SSII4_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        case SSIF_CHNUM_5:
+            GIC_DisableIRQ(SSII5_IRQn);
+            GIC_DisableIRQ(SSIRXI5_IRQn);
+            GIC_DisableIRQ(SSITXI5_IRQn);
+            ret = InterruptHandlerUnregister(SSII5_IRQn);
+            if (0u != ret)
+            {
+                /* NON_NOTICE_ASSERT: Illegal IRQ number */
+            }
+            break;
+        /* ->IPA R3.5.2 : There is nothing to do when unusual conditons. */
+        default:
+            /* NON_NOTICE_ASSERT: Illegal channel number */
+            break;
+        /* <-IPA R3.5.2 */
+    }
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_EnableErrorInterrupt
+* @brief         Enable the SSIF channel error interrupt
+*
+*                Description:<br>
+*                
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_EnableErrorInterrupt(const uint32_t ssif_ch)
+{
+    /* clear error status */
+    g_ssireg[ssif_ch]->SSISR = 0u;
+
+    /* enable error interrupt */
+    g_ssireg[ssif_ch]->SSICR |= SSIF_CR_INT_ERR_MASK;
+ 
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_DisableErrorInterrupt
+* @brief         Disable the SSIF channel error interrupt
+*
+*                Description:<br>
+*                
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+void SSIF_DisableErrorInterrupt(const uint32_t ssif_ch)
+{
+    /* disable error interrupt */
+    g_ssireg[ssif_ch]->SSICR &= ~(SSIF_CR_INT_ERR_MASK);
+
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_ERI<n>_Handler
+* @brief         SSIF error interrupt handler per channel
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        none
+******************************************************************************/
+
+static void SSIF_ERI0_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_0);
+    return;
+}
+
+static void SSIF_ERI1_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_1);
+    return;
+}
+
+static void SSIF_ERI2_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_2);
+    return;
+}
+
+static void SSIF_ERI3_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_3);
+    return;
+}
+
+static void SSIF_ERI4_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_4);
+    return;
+}
+
+static void SSIF_ERI5_Handler(void)
+{
+    SSIF_ERI_Handler(SSIF_CHNUM_5);
+    return;
+}
+
+/******************************************************************************
+* Function Name: SSIF_ERI_Handler
+* @brief         SSIF error interrupt handler common function
+*
+*                Description:<br>
+*                
+* @param[in]     ssif_ch    :SSIF channel
+* @retval        none
+******************************************************************************/
+
+static void SSIF_ERI_Handler(const uint32_t ssif_ch)
+{
+    ssif_info_ch_t* const p_info_ch = &g_ssif_info_drv.info_ch[ssif_ch];
+
+    if (0u != (g_ssireg[ssif_ch]->SSISR & SSIF_SR_INT_ERR_MASK))
+    {
+        /* Restart or Callback */
+        SSIF_ErrorRecovery(p_info_ch);
+    }
+
+    return;
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/ssif/ssif_int.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,62 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/******************************************************************************
+* File Name    : ssif_int.h
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* Description  : SSIF driver interrupt functions header
+******************************************************************************/
+
+#ifndef SSIF_INT_H
+#define SSIF_INT_H
+
+/*******************************************************************************
+Includes <System Includes>, "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/*************************************************************************
+ Structures
+*************************************************************************/
+
+/******************************************************************************
+ Function Prototypes
+ *****************************************************************************/
+void SSIF_InterruptInit(const uint32_t ssif_ch, const uint8_t int_level);
+void SSIF_InterruptShutdown(const uint32_t ssif_ch);
+
+void SSIF_EnableErrorInterrupt(const uint32_t ssif_ch);
+void SSIF_DisableErrorInterrupt(const uint32_t ssif_ch);
+
+#endif /* SSIF_INT_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/RenesasBSP/drv_src/ssif/ssif_ver.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         ssif_ver.c
+* $Rev: 1645 $
+* $Date:: 2015-05-21 10:35:06 +0900#$
+* @brief        SSIF Driver get verion function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "ssif_if.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/* Ex. V2.12 -> MAJOR=2, MINOR=12 */
+#define SSIF_DRV_VER_MAJOR  (2u)
+#define SSIF_DRV_VER_MINOR  (1u)
+
+#define SSIF_DRV_VER_MASK   (0xFFu)
+#define SSIF_DRV_VER_SHIFT  (8u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_SSIF_GetVersion
+* @brief         Get SSIF driver version.
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval        driver version -
+*                    upper 8bit=MAJOR
+*                    lower 8bit=MINOR
+******************************************************************************/
+uint16_t R_SSIF_GetVersion(void)
+{
+    const uint16_t version =
+        ((SSIF_DRV_VER_MAJOR & SSIF_DRV_VER_MASK) << SSIF_DRV_VER_SHIFT)
+        | (SSIF_DRV_VER_MINOR & SSIF_DRV_VER_MASK);
+
+    return version;
+}
+/******************************************************************************
+End of function R_SSIF_GetVersion
+******************************************************************************/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/api/R_BSP_Aio.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,138 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_Aio.h
+* @brief         R_BSP_Aio API
+******************************************************************************/
+
+#ifndef R_BSP_AIO_H
+#define R_BSP_AIO_H
+
+#include <stdint.h>
+#include "rtos.h"
+
+/** Callback function type 
+  *
+  * @param p_data Location of the data.
+  * @param result Number of bytes transmit on success. negative number on error.
+  * @param p_app_data User definition data.
+  */
+typedef void (*rbsp_notify_func_t)(void * p_data, int32_t result, void * p_app_data);
+
+/** Asynchronous control block structure */
+typedef struct {
+    rbsp_notify_func_t  p_notify_func;  /**< Callback function type. */
+    void *              p_app_data;     /**< User definition data. */
+} rbsp_data_conf_t;
+
+/**
+ * A class to communicate a R_BSP_Aio
+ */
+class R_BSP_Aio {
+
+public:
+
+    /** Write count bytes to the file associated
+     *
+     * @param p_data Location of the data.
+     * @param data_size Number of bytes to write.
+     * @param p_data_conf Asynchronous control block structure.
+     * @return Number of bytes written on success. negative number on error.
+     */
+    int32_t write(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf = NULL);
+
+    /** Read count bytes to the file associated
+     *
+     * @param p_data Location of the data.
+     * @param data_size Number of bytes to read.
+     * @param p_data_conf Asynchronous control block structure.
+     * @return Number of bytes read on success. negative number on error.
+     */
+    int32_t read(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf = NULL);
+
+protected:
+
+    /** Constructor
+     *
+     */
+    R_BSP_Aio();
+
+    /** Destructor
+     *
+     */
+    virtual ~R_BSP_Aio();
+
+    /** Write init
+     *
+     * @param handle channel handle.
+     * @param p_func_a Pointer of write function.
+     * @param max_buff_num The upper limit of write buffer.
+     */
+    void write_init(void * handle, void * p_func_a, int32_t max_buff_num = 16) {
+        init(&write_ctl, handle, p_func_a, max_buff_num);
+    };
+
+    /** Read init
+     *
+     * @param handle channel handle.
+     * @param p_func_a Pointer of read function.
+     * @param max_buff_num The upper limit of read buffer.
+     */
+    void read_init(void * handle, void * p_func_a, int32_t max_buff_num = 16) {
+        init(&read_ctl, handle, p_func_a, max_buff_num);
+    };
+private:
+    typedef struct {
+        rbsp_notify_func_t  p_cb_func;
+        void *              p_cb_data;
+        Semaphore *         p_sem;
+        void *              p_aio;
+    } rbsp_sival_t;
+
+    typedef struct {
+        void *              ch_handle;
+        void *              p_async_func;
+        void *              p_aio_top;
+        int32_t             index;
+        rbsp_sival_t *      p_sival_top;
+        Semaphore *         p_sem_ctl;
+        int32_t             MaxNum;
+    } rbsp_serial_ctl_t;
+
+    typedef struct {
+        Semaphore *         p_sem;
+        int32_t             result;
+    } rbsp_sync_t;
+
+    void init(rbsp_serial_ctl_t * p_ctl, void * handle, void * p_func_a, int32_t max_buff_num);
+    static int32_t sync_trans(rbsp_serial_ctl_t * p_ctl, void * const p_data, uint32_t data_size);
+    static void callback_sync_trans(void * p_data, int32_t result, void * p_app_data);
+    static int32_t aio_trans(rbsp_serial_ctl_t * const p_ctl, void * const p_data, uint32_t data_size,
+                             const rbsp_data_conf_t * const p_data_conf);
+    static void callback_aio_trans(union sigval signo);
+
+    rbsp_serial_ctl_t write_ctl;
+    rbsp_serial_ctl_t read_ctl;
+};
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/api/R_BSP_Scux.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,149 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_Scux.h
+* @brief         SCUX API
+******************************************************************************/
+
+#ifndef R_BSP_SCUX_H
+#define R_BSP_SCUX_H
+
+#include "R_BSP_SerialFamily.h"
+#include "R_BSP_ScuxDef.h"
+
+#define SAMPLING_RATE_8000HZ  (8000U)  /* Selects a sampling rate of 8 kHz. */
+#define SAMPLING_RATE_11025HZ (11025U) /* Selects a sampling rate of 11.025 kHz. */
+#define SAMPLING_RATE_12000HZ (12000U) /* Selects a sampling rate of 12 kHz. */
+#define SAMPLING_RATE_16000HZ (16000U) /* Selects a sampling rate of 16 kHz. */
+#define SAMPLING_RATE_22050HZ (22050U) /* Selects a sampling rate of 22.05 kHz. */
+#define SAMPLING_RATE_24000HZ (24000U) /* Selects a sampling rate of 24 kHz. */
+#define SAMPLING_RATE_32000HZ (32000U) /* Selects a sampling rate of 32 kHz. */
+#define SAMPLING_RATE_44100HZ (44100U) /* Selects a sampling rate of 44.1 kHz. */
+#define SAMPLING_RATE_48000HZ (48000U) /* Selects a sampling rate of 48 kHz. */
+#define SAMPLING_RATE_64000HZ (64000U) /* Selects a sampling rate of 64 kHz. */
+#define SAMPLING_RATE_88200HZ (88200U) /* Selects a sampling rate of 88.2 kHz. */
+#define SAMPLING_RATE_96000HZ (96000U) /* Selects a sampling rate of 96 kHz. */
+#define SELECT_IN_DATA_CH_0   (0U)     /* Specifies audio channel 0ch. */
+#define SELECT_IN_DATA_CH_1   (1U)     /* Specifies audio channel 1ch. */
+
+/** SRC parameter information */
+typedef struct
+{
+    bool                  src_enable;                       /**< SRC function enable setting */
+    scux_data_word_len_t  word_len;                         /**< Word length of the audio data to be used
+                                                                 by the SRC. */
+    bool                  mode_sync;                        /**< Synchronization mode */
+    uint32_t              input_rate;                       /**< Input sampling rate */
+    uint32_t              output_rate;                      /**< Output sampling rate */
+    uint32_t              select_in_data_ch[SCUX_USE_CH_2]; /**< For SRC's input data position swapping */
+} scux_src_usr_cfg_t;
+
+/** The SCUX module is made up of a sampling rate converter, a digital volume unit, and a mixer.
+ *  The SCUX driver can perform asynchronous and synchronous sampling rate conversions using the sampling rate
+ *  converter. 
+ *  The SCUX driver uses the DMA transfer mode to input and output audio data.
+ */
+class R_BSP_Scux : public R_BSP_SerialFamily {
+
+public:
+    /** Constructor: Initializes and opens the channel designated by the SCUX driver.
+     *
+     * @param channel SCUX channel number
+     * @param int_level Transfer interrupt priority level (0x00-0xF7; default = 0x80)
+     * @param max_write_num Maximum number of writes (1 to 128; default = 16)
+     * @param max_read_num Maximum number of reads (1 to 128; default = 16)
+     */
+    R_BSP_Scux(scux_ch_num_t channel, uint8_t int_level = 0x80, int32_t max_write_num = 16, int32_t max_read_num = 16);
+
+    /** Destructor: Closes the channel designated by the SCUX driver and exits.
+     *
+     */
+    virtual ~R_BSP_Scux(void);
+
+    /** Sets up the SCUX HW and starts operation, then starts accepting write/read requests.
+     * Allocates a DMA channel for read requests.
+     * The function also initializes the SCUX HW error state.
+     *
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool TransStart(void);
+
+    /** Stops accepting write/read requests, flushes out all data in the SCUX that is requested for transfer,
+     *  then stops the HW operation.
+     *   If a transfer request is being processed, the function stops accepting write/read requests,
+     *   then performs preprocessing to stop the HW operation after flushing out all data in the SCUX
+     *   that is requested for transfer. 
+     *   If no transfer request is being processed, the function stops accepting write/read requests 
+     *   before stopping the HW operation.
+     * The function releases the DMA channel for read requests when the HW operation is stopped.
+     * It also calls the user-own callback function at the end of the transfer.
+     *
+     * @param callback Pointer to the callback function
+     *                 The SCUX driver places an error code indicating the execution result of FlushStop 
+     *                 in the argument of the callback function before calling the callback function. 
+     *                 The error code is set to 0 if FlushStop is successful. A negative number is set 
+     *                 if FlushStop fails.
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool FlushStop(void (* const callback)(int32_t));
+
+    /** Discards all data in the SCUX that is requested for transfer before stopping the hardware operation
+     *  and stops accepting write/read requests. 
+     *  The function releases the DMA channel for read requests when the HW operation is stopped.
+     *
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool ClearStop(void);
+
+    /** Sets up SRC parameters.
+     *
+     * @param p_src_param SRC parameter information
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool SetSrcCfg(const scux_src_usr_cfg_t * const p_src_param);
+
+    /** Obtains the state information of the write request.
+     *
+     * @param p_write_stat Status of the write request
+     *        SCUX_STAT_STOP (0)  Acceptance of requests is stopped.
+     *        SCUX_STAT_IDLE (1)  Processing of all requests is completed and waiting for a request.
+     *        SCUX_STAT_TRANS(2)  Transfer in progress
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool GetWriteStat(uint32_t * const p_write_stat);
+
+    /** Obtains the state information of the read request.
+     *
+     * @param p_read_stat ead request state
+     *        SCUX_STAT_STOP (0)  Acceptance of requests is stopped
+     *        SCUX_STAT_IDLE (1)  Processing of all requests is completed and waiting for a request.
+     *        SCUX_STAT_TRANS(2)  Transfer in progress
+     * @return Returns true if the function is successful. Returns false if the function fails.
+     */
+    bool GetReadStat(uint32_t * const p_read_stat);
+
+private:
+    int32_t scux_ch;
+};
+#endif /* R_BSP_SCUX_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/api/R_BSP_ScuxDef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,88 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_ScuxDef.h
+* @brief         SCUX defines
+******************************************************************************/
+
+#ifndef R_BSP_SCUXDEF_H
+#define R_BSP_SCUXDEF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*************************************************************************
+ Enumerated Types
+*************************************************************************/
+
+/** SCUX channel number */
+typedef enum
+{
+    SCUX_CH_0 = 0,   /**< Specifies SCUX0. */
+    SCUX_CH_1 = 1,   /**< Specifies SCUX1. */
+    SCUX_CH_2 = 2,   /**< Specifies SCUX2. */
+    SCUX_CH_3 = 3,   /**< Specifies SCUX3. */
+    SCUX_CH_NUM = 4  /**< Number of SCUX channels. */
+} scux_ch_num_t;
+
+/** used audio channel number setting */
+typedef enum
+{
+    SCUX_USE_CH_1 = 1,   /**< used audio channel number is 1 */
+    SCUX_USE_CH_2 = 2,   /**< used audio channel number is 2 */
+    SCUX_USE_CH_4 = 4,   /**< used audio channel number is 4 */
+    SCUX_USE_CH_6 = 6,   /**< used audio channel number is 6 */
+    SCUX_USE_CH_8 = 8    /**< used audio channel number is 8 */
+} scux_use_channel_t;
+
+/** SCUX data word length */
+typedef enum
+{
+    SCUX_DATA_LEN_MIN      =(-1), /**< For data word length identification [unsettable] */
+    SCUX_DATA_LEN_24       = 0,   /**< Runs with a data word length of 24 bits. */
+    SCUX_DATA_LEN_16       = 1,   /**< Runs with a data word length of 16 bits. */
+    SCUX_DATA_LEN_16_TO_24 = 2,   /**< Outputs 16-bit data in 24-bit mode. */
+    SCUX_DATA_LEN_MAX      = 3    /**< For data word length identification [unsettable] */
+} scux_data_word_len_t;
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/** Status of the request */
+#define SCUX_STAT_STOP    0  /**< Acceptance of requests is stopped */
+#define SCUX_STAT_IDLE    1  /**< Processing of all requests is completed and waiting for a request. */
+#define SCUX_STAT_TRANS   2  /**< Transfer in progress */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_SCUXDEF_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/api/R_BSP_SerialFamily.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,74 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_SerialFamily.h
+* @brief         R_BSP_SerialFamily API
+******************************************************************************/
+
+#ifndef R_BSP_IOIF_H
+#define R_BSP_IOIF_H
+
+#include <stdint.h>
+#include <stdarg.h>
+#include "R_BSP_Aio.h"
+#include "R_BSP_mbed_fns.h"
+#include "rtos.h"
+
+/** A class to communicate a R_BSP_SerialFamily
+ *
+ */
+class R_BSP_SerialFamily : public R_BSP_Aio {
+
+public:
+    /** Manipulates the underlying device parameters of special files
+     *
+     * @param request has encoded in it whether the argument is an "in" parameter or "out" parameter,
+     * and the size of the argument argp in bytes.
+     * @return true = success, false = failure
+     */
+     bool ioctl(int request, ...);
+
+protected:
+    /** Destructor
+     *
+     */
+    virtual ~R_BSP_SerialFamily();
+
+    /** Channel init
+     *
+     * @param function_list pointer of driver function callback table
+     * @param channel       channel number
+     * @param config_data   pointer of several parameters for a channel
+     * @param max_write_num The upper limit of write buffer
+     * @param max_read_num  The upper limit of read buffer
+     */
+    bool init_channel(RBSP_MBED_FNS * function_list, int channel, void * const config_data, int32_t max_write_num = 16, int32_t max_read_num = 16);
+
+private:
+    void * instance;
+    void * ch_handle;
+    int32_t ch_no;
+    RBSP_MBED_FNS * functions;
+};
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/api/R_BSP_Ssif.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,88 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_Ssif.h
+* @brief         SSIF API
+******************************************************************************/
+
+#ifndef R_BSP_SSIF_H
+#define R_BSP_SSIF_H
+
+#include <stdint.h>
+#include "R_BSP_SerialFamily.h"
+#include "R_BSP_SsifDef.h"
+#include "rtos.h"
+#include "pinmap.h"
+
+/** A class to communicate a R_BSP_Ssif
+ *
+ */
+class R_BSP_Ssif : public R_BSP_SerialFamily {
+
+public:
+
+    /** Constructor
+     *
+     * @param sck SSIF serial bit clock
+     * @param ws  SSIF word selection
+     * @param tx  SSIF serial data output
+     * @param rx  SSIF serial data input
+     * @param int_level     Interupt priority (SSIF)
+     * @param max_write_num The upper limit of write buffer (SSIF)
+     * @param max_read_num  The upper limit of read buffer (SSIF)
+     */
+    R_BSP_Ssif(PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level = 0x80, int32_t max_write_num = 16, int32_t max_read_num = 16);
+
+    /** Destructor
+     *
+     */
+    virtual ~R_BSP_Ssif();
+
+    /** Get a value of SSIF channel number
+     *
+     * @return SSIF channel number
+     */
+    int32_t GetSsifChNo(void) {
+        return ssif_ch;
+    };
+
+    /** Save configuration to the SSIF driver
+     *
+     * @param p_ch_cfg SSIF channel configuration parameter
+     * @return true = success, false = failure
+     */
+    bool ConfigChannel(const ssif_channel_cfg_t* const p_ch_cfg);
+
+    /** Get a value of SSISR register
+     *
+     * @param p_status Pointer of status value
+     * @return true = success, false = failure
+     */
+    bool GetStatus(uint32_t* const p_status);
+
+private:
+    ssif_channel_cfg_t  ssif_cfg;
+    int32_t ssif_ch;
+};
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/api/R_BSP_SsifDef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,222 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          R_BSP_SsifDef.h
+* @brief         SSIF defines
+******************************************************************************/
+
+#ifndef R_BSP_SSIF_DEF_H
+#define R_BSP_SSIF_DEF_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/******************************************************************************
+ Defines
+ *****************************************************************************/
+
+/******************************************************************************
+ Constant Macros
+ *****************************************************************************/
+#define SSIF_NUM_CHANS       (6u)    /**< Number of SSIF channels */
+
+#define SSIF_CFG_DISABLE_ROMDEC_DIRECT (0x0u)        /* Disable SSIRDR->STRMDIN0 route */
+#define SSIF_CFG_ENABLE_ROMDEC_DIRECT  (0xDEC0DEC1u) /* Enable  SSIRDR->STRMDIN0 route */
+
+/******************************************************************************
+ Function Macros
+ *****************************************************************************/
+
+/******************************************************************************
+ Enumerated Types
+ *****************************************************************************/
+
+/** SSICR:CKS(Clock source for oversampling) */
+typedef enum
+{
+    SSIF_CFG_CKS_AUDIO_X1  = 0,  /**< select AUDIO_X1   */
+    SSIF_CFG_CKS_AUDIO_CLK = 1   /**< select AUIDIO_CLK */
+} ssif_chcfg_cks_t; 
+
+/** SSICR:CHNL(Audio channels per system word) */
+typedef enum
+{
+    SSIF_CFG_MULTI_CH_1 = 0,     /**< 1ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_2 = 1,     /**< 2ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_3 = 2,     /**< 3ch within systemword (on tdm=0) */
+    SSIF_CFG_MULTI_CH_4 = 3      /**< 4ch within systemword (on tdm=0) */
+} ssif_chcfg_multi_ch_t;
+
+/** SSICR:DWL(Data word length) */
+typedef enum
+{
+    SSIF_CFG_DATA_WORD_8  = 0,   /**< Data word length 8  */
+    SSIF_CFG_DATA_WORD_16 = 1,   /**< Data word length 16 */
+    SSIF_CFG_DATA_WORD_18 = 2,   /**< Data word length 18 */
+    SSIF_CFG_DATA_WORD_20 = 3,   /**< Data word length 20 */
+    SSIF_CFG_DATA_WORD_22 = 4,   /**< Data word length 22 */
+    SSIF_CFG_DATA_WORD_24 = 5,   /**< Data word length 24 */
+    SSIF_CFG_DATA_WORD_32 = 6    /**< Data word length 32 */
+} ssif_chcfg_data_word_t;
+
+/** SSICR:SWL(System word length) */
+typedef enum
+{
+    SSIF_CFG_SYSTEM_WORD_8   = 0,    /**< System word length 8   */
+    SSIF_CFG_SYSTEM_WORD_16  = 1,    /**< System word length 16  */
+    SSIF_CFG_SYSTEM_WORD_24  = 2,    /**< System word length 24  */
+    SSIF_CFG_SYSTEM_WORD_32  = 3,    /**< System word length 32  */
+    SSIF_CFG_SYSTEM_WORD_48  = 4,    /**< System word length 48  */
+    SSIF_CFG_SYSTEM_WORD_64  = 5,    /**< System word length 64  */
+    SSIF_CFG_SYSTEM_WORD_128 = 6,    /**< System word length 128 */
+    SSIF_CFG_SYSTEM_WORD_256 = 7     /**< System word length 256 */
+} ssif_chcfg_system_word_t;
+
+/** SSICR:SCKP(Clock polarity) */
+typedef enum
+{
+    SSIF_CFG_FALLING = 0,    /**< Falling edge */
+    SSIF_CFG_RISING  = 1     /**< Rising edge  */
+} ssif_chcfg_clock_pol_t;
+
+/** SSICR:SWSP(Word select polarity) */
+typedef enum
+{
+    SSIF_CFG_WS_LOW  = 0,    /**< Low for ther 1st channel(not TDM) */
+    SSIF_CFG_WS_HIGH = 1     /**< High for the 1st channel(not TDM) */
+} ssif_chcfg_ws_pol_t;
+
+/** SSICR:SPDP(Serial padding polarity) */
+typedef enum
+{
+    SSIF_CFG_PADDING_LOW  = 0,   /**< Padding bits are low  */
+    SSIF_CFG_PADDING_HIGH = 1    /**< Padding bits are high */
+} ssif_chcfg_padding_pol_t;
+
+/** SSICR:SDTA(Serial data alignment) */
+typedef enum
+{
+    SSIF_CFG_DATA_FIRST    = 0,  /**< Data first         */
+    SSIF_CFG_PADDING_FIRST = 1   /**< Padding bits first */
+} ssif_chcfg_serial_alignment_t;
+
+/** SSICR:PDTA(Parallel data alignment) */
+typedef enum
+{
+    SSIF_CFG_LEFT  = 0,  /**< Left aligned  */
+    SSIF_CFG_RIGHT = 1   /**< Right aligned */
+} ssif_chcfg_parallel_alignment_t;
+
+/** SSICR:DEL(Serial data delay) */
+typedef enum
+{
+    SSIF_CFG_DELAY    = 0,   /**< 1 clock delay */
+    SSIF_CFG_NO_DELAY = 1    /**< No delay      */
+} ssif_chcfg_ws_delay_t;
+
+/** SSICR:CKDV(Serial oversampling clock division ratio) */
+typedef enum
+{
+    SSIF_CFG_CKDV_BITS_1   = 0,
+    SSIF_CFG_CKDV_BITS_2   = 1,
+    SSIF_CFG_CKDV_BITS_4   = 2,
+    SSIF_CFG_CKDV_BITS_8   = 3,
+    SSIF_CFG_CKDV_BITS_16  = 4,
+    SSIF_CFG_CKDV_BITS_32  = 5,
+    SSIF_CFG_CKDV_BITS_64  = 6,
+    SSIF_CFG_CKDV_BITS_128 = 7,
+    SSIF_CFG_CKDV_BITS_6   = 8,
+    SSIF_CFG_CKDV_BITS_12  = 9,
+    SSIF_CFG_CKDV_BITS_24  = 10,
+    SSIF_CFG_CKDV_BITS_48  = 11,
+    SSIF_CFG_CKDV_BITS_96  = 12
+} ssif_chcfg_ckdv_t;
+
+
+/** SNCR:SSIxNL(Serial sound interface channel x noise canceler enable) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_NOISE_CANCEL = 0, /**< Not use noise cancel function */
+    SSIF_CFG_ENABLE_NOISE_CANCEL  = 1  /**< Use noise cancel function     */
+} ssif_chcfg_noise_cancel_t;
+
+
+/** SSITDMR:TDM(TDM mode) */
+typedef enum
+{
+    SSIF_CFG_DISABLE_TDM = 0,   /**< not TDM mode */
+    SSIF_CFG_ENABLE_TDM  = 1    /**< set TDM mode */
+} ssif_chcfg_tdm_t;
+
+/******************************************************************************
+ Structures
+ *****************************************************************************/
+
+/** It's used for ROMDEC direct transfer mode and the call back function registration. */
+typedef struct
+{
+    uint32_t    mode;               /**< Enable/Disable SSIRDR->STRMDIN0 route */
+    void        (*p_cbfunc)(void);  /**< SSIF error callback function          */
+} ssif_chcfg_romdec_t;
+
+/** This structure contains the configuration settings */
+typedef struct
+{
+    bool                            enabled;             /**< The enable flag for the channel       */
+    uint8_t                         int_level;           /**< Interrupt priority for the channel    */
+    bool                            slave_mode;          /**< Mode of operation                     */
+    uint32_t                        sample_freq;         /**< Audio Sampling frequency(Hz)          */
+    ssif_chcfg_cks_t                clk_select;          /**< SSICR-CKS : Audio clock select        */
+    ssif_chcfg_multi_ch_t           multi_ch;            /**< SSICR-CHNL: Audio channels per system word */
+    ssif_chcfg_data_word_t          data_word;           /**< SSICR-DWL : Data word length          */
+    ssif_chcfg_system_word_t        system_word;         /**< SSICR-SWL : System word length        */
+    ssif_chcfg_clock_pol_t          bclk_pol;            /**< SSICR-SCKP: Bit Clock polarity        */
+    ssif_chcfg_ws_pol_t             ws_pol;              /**< SSICR-SWSP: Word Clock polarity       */
+    ssif_chcfg_padding_pol_t        padding_pol;         /**< SSICR-SPDP: Padding polarity          */
+    ssif_chcfg_serial_alignment_t   serial_alignment;    /**< SSICR-SDTA: Serial data alignment     */
+    ssif_chcfg_parallel_alignment_t parallel_alignment;  /**< SSICR-PDTA: Parallel data alignment   */
+    ssif_chcfg_ws_delay_t           ws_delay;            /**< SSICR-DEL : Serial clock delay        */
+    ssif_chcfg_noise_cancel_t       noise_cancel;        /**< GPIO-SNCR : Noise cancel              */
+    ssif_chcfg_tdm_t                tdm_mode;            /**< SSITDMR-TDM: TDM mode                 */
+    ssif_chcfg_romdec_t             romdec_direct;       /**< DMA : SSIRDR->STRMDIN0 route settings */
+} ssif_channel_cfg_t;
+
+/******************************************************************************
+ IOCTLS
+ *****************************************************************************/
+
+#define SSIF_CONFIG_CHANNEL        (7)
+#define SSIF_GET_STATUS           (13)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_SSIF_DEF_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/common/R_BSP_Aio.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,160 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "r_errno.h"
+#include "misratypes.h"
+#include "aioif.h"
+#include "R_BSP_Aio.h"
+
+typedef int32_t (*rbsp_read_write_a_func_t)(void* const p_fd, AIOCB* const p_aio, int32_t* const p_errno);
+
+R_BSP_Aio::R_BSP_Aio() {
+}
+
+R_BSP_Aio::~R_BSP_Aio() {
+    if (write_ctl.MaxNum != 0) {
+        delete [] (rbsp_sival_t *)write_ctl.p_sival_top;
+        delete [] (AIOCB *)write_ctl.p_aio_top;
+        delete write_ctl.p_sem_ctl;
+    }
+    if (read_ctl.MaxNum != 0) {
+        delete [] (rbsp_sival_t *)read_ctl.p_sival_top;
+        delete [] (AIOCB *)read_ctl.p_aio_top;
+        delete read_ctl.p_sem_ctl;
+    }
+}
+
+void R_BSP_Aio::init(rbsp_serial_ctl_t * p_ctl, void * handle, void * p_func_a, int32_t max_buff_num) {
+    if (handle != NULL) {
+        p_ctl->ch_handle    = handle;
+        p_ctl->MaxNum       = max_buff_num;
+        p_ctl->p_aio_top    = NULL;
+        p_ctl->index        = 0;
+        p_ctl->p_async_func = p_func_a;
+        if (p_ctl->MaxNum != 0) {
+            p_ctl->p_sem_ctl    = new Semaphore(p_ctl->MaxNum);
+            p_ctl->p_aio_top    = new AIOCB[p_ctl->MaxNum];
+            p_ctl->p_sival_top  = new rbsp_sival_t[p_ctl->MaxNum];
+        }
+    }
+}
+
+int32_t R_BSP_Aio::write(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf) {
+    if (p_data_conf == NULL) {
+        return sync_trans(&write_ctl, p_data, data_size);
+    } else {
+        return aio_trans(&write_ctl, p_data, data_size, p_data_conf);
+    }
+}
+
+int32_t R_BSP_Aio::read(void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf) {
+    if (p_data_conf == NULL) {
+        return sync_trans(&read_ctl, p_data, data_size);
+    } else {
+        return aio_trans(&read_ctl, p_data, data_size, p_data_conf);
+    }
+}
+
+/* static */ int32_t R_BSP_Aio::sync_trans(rbsp_serial_ctl_t * p_ctl, void * const p_data, uint32_t data_size) {
+    rbsp_sync_t sync_info;
+    rbsp_data_conf_t data_conf;
+    Semaphore * p_sem_wait = new Semaphore(0);
+
+    sync_info.result = -1;
+    if (p_sem_wait != NULL) {
+        sync_info.p_sem  = p_sem_wait;
+
+        data_conf.p_notify_func = &callback_sync_trans;
+        data_conf.p_app_data    = &sync_info;
+
+        if (aio_trans(p_ctl, p_data, data_size, &data_conf) == ESUCCESS) {
+            p_sem_wait->wait(osWaitForever);
+        }
+        delete p_sem_wait;
+    }
+
+    return sync_info.result;
+}
+
+/* static */ void R_BSP_Aio::callback_sync_trans(void * p_data, int32_t result, void * p_app_data) {
+    rbsp_sync_t * p_sync_info = (rbsp_sync_t *)p_app_data;
+
+    p_sync_info->result = result;
+    p_sync_info->p_sem->release();
+}
+
+/* static */ int32_t R_BSP_Aio::aio_trans(rbsp_serial_ctl_t * const p_ctl,
+               void * const p_data, uint32_t data_size, const rbsp_data_conf_t * const p_data_conf) {
+    int32_t wk_errno;
+    AIOCB * p_rbsp_aio;
+    rbsp_sival_t * p_sival;
+    rbsp_read_write_a_func_t p_func = (rbsp_read_write_a_func_t)p_ctl->p_async_func;
+
+    if ((p_data_conf == NULL) || (p_data == NULL)) {
+        wk_errno = ENOSPC;
+    } else if (p_ctl->p_sem_ctl->wait(osWaitForever) == -1) {
+        wk_errno = EIO;
+    } else {
+        p_rbsp_aio = (AIOCB *)p_ctl->p_aio_top + p_ctl->index;
+        p_sival    = p_ctl->p_sival_top + p_ctl->index;
+
+        p_sival->p_cb_func     = p_data_conf->p_notify_func;
+        p_sival->p_cb_data     = p_data_conf->p_app_data;
+        p_sival->p_sem         = p_ctl->p_sem_ctl;
+        p_sival->p_aio         = p_rbsp_aio;
+
+        p_rbsp_aio->aio_fildes = 0;
+        p_rbsp_aio->aio_buf    = p_data;
+        p_rbsp_aio->aio_nbytes = data_size;
+        p_rbsp_aio->aio_offset = 0;
+        p_rbsp_aio->aio_sigevent.sigev_notify = SIGEV_THREAD;
+        p_rbsp_aio->aio_sigevent.sigev_value.sival_ptr = (void*)p_sival;
+        p_rbsp_aio->aio_sigevent.sigev_notify_function = &callback_aio_trans;
+        p_func(p_ctl->ch_handle, p_rbsp_aio, &wk_errno);
+
+        if (wk_errno == ESUCCESS) {
+            if ((p_ctl->index + 1) >= p_ctl->MaxNum) {
+                p_ctl->index = 0;
+            } else {
+                p_ctl->index++;
+            }
+        } else {
+            p_ctl->p_sem_ctl->release();
+        }
+    }
+
+    return wk_errno;
+}
+
+/* static */ void R_BSP_Aio::callback_aio_trans(union sigval signo) {
+    rbsp_sival_t * p_sival = (rbsp_sival_t *)signo.sival_ptr;
+    AIOCB * p_aio_result = (AIOCB *)p_sival->p_aio;
+
+    if ((p_sival->p_cb_func != NULL) && (p_aio_result != NULL)) {
+        p_sival->p_cb_func((void *)p_aio_result->aio_buf, p_aio_result->aio_return, p_sival->p_cb_data);
+    }
+    p_sival->p_sem->release();
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/common/R_BSP_Scux.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,355 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "r_bsp_cmn.h"
+#include "R_BSP_Scux.h"
+#include "scux_if.h"
+
+#define CH_ERR_NUM                  (-1)     /* Channel error number */
+#define INT_LEVEL_MAX               (0xF7)   /* The maximum value of the interrupt level */
+#define REQ_BUFF_NUM_MIN            (1)      /* The minimum value of the request buffer */
+#define REQ_BUFF_NUM_MAX            (128)    /* The maximum value of the request buffer */
+#define INPUT_DIV_INIT_VALUE        (1000U)  /* The initial value of input divide ratio */
+#define OUTPUT_DIV_INIT_VALUE       (0U)     /* The initial value of output divide ratio  */
+#define INPUT_WS_INIT_VALUE         (1U)     /* The initial value of input WS frequency */
+#define OUTPUT_WS_INIT_VALUE        (96000U) /* The initial value of output WS frequency */
+#define FREQ_TIOC3A_INIT_VALUE      (1U)     /* The initial value of frequency of TIOC3 */
+#define FREQ_TIOC4A_INIT_VALUE      (1U)     /* The initial value of frequency of TIOC4 */
+#define WAIT_SAMPLE_INIT_VALUE      (0U)     /* The initial value of wait time */
+#define MIN_RATE_PER_INIT_VALUE     (98U)    /* The initial value of minimum rate */
+#define DIV_RATIO_CLK_AUDIO_22050HZ (1024U)  /* Divide ratio when the frequency is 22050Hz */
+#define DIV_RATIO_CLK_AUDIO_44100HZ (512U)   /* Divide ratio when the frequency is 44100Hz */
+#define DIV_RATIO_CLK_AUDIO_88200HZ (256U)   /* Divide ratio when the frequency is 88200Hz */
+#define DIV_RATIO_CLK_USB_24000HZ   (2000U)  /* Divide ratio when the frequency is 24000Hz */
+#define DIV_RATIO_CLK_USB_32000HZ   (1500U)  /* Divide ratio when the frequency is 36000Hz */
+#define DIV_RATIO_CLK_USB_48000HZ   (1000U)  /* Divide ratio when the frequency is 48000Hz */
+#define DIV_RATIO_CLK_USB_64000HZ   (750U)   /* Divide ratio when the frequency is 64000Hz */
+#define DIV_RATIO_CLK_USB_96000HZ   (500U)   /* Divide ratio when the frequency is 96000Hz */
+
+static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg);
+
+R_BSP_Scux::R_BSP_Scux(scux_ch_num_t channel, uint8_t int_level, int32_t max_write_num, int32_t max_read_num) {
+    scux_channel_cfg_t scux_cfg;
+    int32_t result;
+    bool    init_result;
+
+    if (channel >= SCUX_CH_NUM) {
+        result = EERROR;
+    } else if (int_level > INT_LEVEL_MAX) {
+        result = EERROR;
+    } else if ((max_write_num < REQ_BUFF_NUM_MIN) || (max_write_num > REQ_BUFF_NUM_MAX)) {
+        result = EERROR;
+    } else if ((max_read_num < REQ_BUFF_NUM_MIN) || (max_read_num > REQ_BUFF_NUM_MAX)) {
+        result = EERROR;
+    } else {
+        result = R_BSP_CMN_Init();
+        if (result == ESUCCESS) {
+            scux_ch = (int32_t)channel;
+
+            scux_cfg.enabled       = true;
+            scux_cfg.int_level     = int_level;
+
+            switch (channel) {
+                case SCUX_CH_0:
+                    scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
+                    break;
+                case SCUX_CH_1:
+                    scux_cfg.route = SCUX_ROUTE_SRC1_MEM;
+                    break;
+                case SCUX_CH_2:
+                    scux_cfg.route = SCUX_ROUTE_SRC2_MEM;
+                    break;
+                case SCUX_CH_3:
+                    scux_cfg.route = SCUX_ROUTE_SRC3_MEM;
+                    break;
+                default:
+                    /* NOTREACHED on At the time of a normal performance */
+                    scux_cfg.route = SCUX_ROUTE_SRC0_MEM;
+                    break;
+            }
+
+            init_result = set_src_init_cfg(&scux_cfg.src_cfg);
+            if (init_result != false) {
+                init_result = init_channel(R_SCUX_MakeCbTbl_mbed(), (int32_t)channel, &scux_cfg, max_write_num, max_read_num);
+                if (init_result == false) {
+                    result = EERROR;
+                }
+            } else {
+                result = EERROR;
+            }
+        }
+    }
+
+    if (result != ESUCCESS) {
+        scux_ch   = CH_ERR_NUM;
+    }
+}
+
+R_BSP_Scux::~R_BSP_Scux(void) {
+}
+
+bool R_BSP_Scux::TransStart(void) {
+    return ioctl(SCUX_IOCTL_SET_START, NULL);
+}
+
+bool R_BSP_Scux::FlushStop(void (* const callback)(int32_t)) {
+    return ioctl(SCUX_IOCTL_SET_FLUSH_STOP, (void *)callback);
+}
+
+bool R_BSP_Scux::ClearStop(void) {
+    return ioctl(SCUX_IOCTL_SET_CLEAR_STOP, NULL);
+}
+
+bool R_BSP_Scux::SetSrcCfg(const scux_src_usr_cfg_t * const p_src_param) {
+    scux_src_cfg_t src_cfg;
+    bool    init_result;
+    bool    ret = true;
+    int32_t i;
+
+    if (scux_ch == CH_ERR_NUM) {
+        ret = false;
+    } else if (p_src_param == NULL) {
+        ret = false;
+    } else if ((p_src_param->mode_sync != false) && (p_src_param->src_enable == false)) {
+        ret = false;
+    } else {
+        init_result = set_src_init_cfg(&src_cfg);
+        if (init_result != true) {
+            ret = false;
+        } else {
+            src_cfg.src_enable = p_src_param->src_enable;
+            src_cfg.mode_sync  = p_src_param->mode_sync;
+
+            switch (p_src_param->word_len) {
+                case SCUX_DATA_LEN_24:
+                    /* fall through */
+                case SCUX_DATA_LEN_16:
+                    /* fall through */
+                case SCUX_DATA_LEN_16_TO_24:
+                    src_cfg.word_len = p_src_param->word_len;
+                    break;
+                default:
+                    ret = false;
+                    break;
+            }
+
+            if (ret == true) {
+                if (p_src_param->mode_sync != false) {
+                    switch (p_src_param->input_rate) {
+                        case SAMPLING_RATE_8000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_8;
+                            break;
+                        case SAMPLING_RATE_11025HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_11_025;
+                            break;
+                        case SAMPLING_RATE_12000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_12;
+                            break;
+                        case SAMPLING_RATE_16000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_16;
+                            break;
+                        case SAMPLING_RATE_22050HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_22_05;
+                            break;
+                        case SAMPLING_RATE_24000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_24;
+                            break;
+                        case SAMPLING_RATE_32000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_32;
+                            break;
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_44_1;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_48;
+                            break;
+                        case SAMPLING_RATE_64000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_64;
+                            break;
+                        case SAMPLING_RATE_88200HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_88_2;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.input_rate_sync = SCUX_SYNC_RATE_96;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                } else {
+                    switch (p_src_param->input_rate) {
+                        case SAMPLING_RATE_22050HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_22050HZ;
+                            break;
+                        case SAMPLING_RATE_24000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_24000HZ;
+                            break;
+                        case SAMPLING_RATE_32000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_32000HZ;
+                            break;
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_44100HZ;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_48000HZ;
+                            break;
+                        case SAMPLING_RATE_64000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_64000HZ;
+                            break;
+                        case SAMPLING_RATE_88200HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_AUDIO_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_AUDIO_88200HZ;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.input_clk_async = SCUX_CLK_USB_X1;
+                            src_cfg.input_div_async = DIV_RATIO_CLK_USB_96000HZ;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                }
+            }
+
+            if (ret == true) {
+                if (p_src_param->mode_sync != false) {
+                    switch (p_src_param->output_rate) {
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.output_rate_sync = SCUX_SYNC_RATE_44_1;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.output_rate_sync = SCUX_SYNC_RATE_48;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.output_rate_sync = SCUX_SYNC_RATE_96;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                } else {
+                    switch (p_src_param->output_rate) {
+                        case SAMPLING_RATE_44100HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_44100HZ;
+                            break;
+                        case SAMPLING_RATE_48000HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_48000HZ;
+                            break;
+                        case SAMPLING_RATE_88200HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_88200HZ;
+                            break;
+                        case SAMPLING_RATE_96000HZ:
+                            src_cfg.output_ws = SAMPLING_RATE_96000HZ;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                }
+            }
+
+            if (ret == true) {
+                for (i = 0; i < SCUX_USE_CH_2; i++) {
+                    switch (p_src_param->select_in_data_ch[i]) {
+                        case SELECT_IN_DATA_CH_0:
+                            src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_0;
+                            break;
+                        case SELECT_IN_DATA_CH_1:
+                            src_cfg.select_in_data_ch[i] = SCUX_AUDIO_CH_1;
+                            break;
+                        default:
+                            ret = false;
+                            break;
+                    }
+                }
+            }
+
+            if (ret == true) {
+                ret = ioctl(SCUX_IOCTL_SET_SRC_CFG, (void *)&src_cfg);
+            }
+        }
+    }
+
+    return ret;
+}
+
+bool R_BSP_Scux::GetWriteStat(uint32_t * const p_write_stat) {
+    return ioctl(SCUX_IOCTL_GET_WRITE_STAT, (void *)p_write_stat);
+}
+
+bool R_BSP_Scux::GetReadStat(uint32_t * const p_read_stat) {
+    return ioctl(SCUX_IOCTL_GET_READ_STAT, (void *)p_read_stat);
+}
+
+/**************************************************************************//**
+* Function Name: set_src_init_cfg
+* @brief         SRC configuration initialization.
+*
+*                Description:<br>
+*                
+* @param[in]     src_cfg SRC configuration. 
+* @retval        true  Setting success.
+*                false Setting fails.
+******************************************************************************/
+static bool set_src_init_cfg(scux_src_cfg_t * const src_cfg) {
+    bool ret = true;
+
+    if (src_cfg == NULL) {
+        ret = false;
+    } else {
+        src_cfg->src_enable                         = true;
+        src_cfg->use_ch                             = SCUX_USE_CH_2;
+        src_cfg->word_len                           = SCUX_DATA_LEN_16;
+        src_cfg->mode_sync                          = true;
+        src_cfg->input_rate_sync                    = SCUX_SYNC_RATE_48;
+        src_cfg->input_clk_async                    = SCUX_CLK_USB_X1;
+        src_cfg->input_div_async                    = INPUT_DIV_INIT_VALUE;
+        src_cfg->output_rate_sync                   = SCUX_SYNC_RATE_96;
+        src_cfg->output_clk_async                   = SCUX_CLK_SSIF0_WS;
+        src_cfg->output_div_async                   = OUTPUT_DIV_INIT_VALUE;
+        src_cfg->input_ws                           = INPUT_WS_INIT_VALUE;
+        src_cfg->output_ws                          = OUTPUT_WS_INIT_VALUE;
+        src_cfg->freq_tioc3a                        = FREQ_TIOC3A_INIT_VALUE;
+        src_cfg->freq_tioc4a                        = FREQ_TIOC4A_INIT_VALUE;
+        src_cfg->delay_mode                         = SCUX_DELAY_NORMAL;
+        src_cfg->wait_sample                        = WAIT_SAMPLE_INIT_VALUE;
+        src_cfg->min_rate_percentage                = MIN_RATE_PER_INIT_VALUE;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_0] = SCUX_AUDIO_CH_0;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_1] = SCUX_AUDIO_CH_1;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_2] = SCUX_AUDIO_CH_2;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_3] = SCUX_AUDIO_CH_3;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_4] = SCUX_AUDIO_CH_4;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_5] = SCUX_AUDIO_CH_5;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_6] = SCUX_AUDIO_CH_6;
+        src_cfg->select_in_data_ch[SCUX_AUDIO_CH_7] = SCUX_AUDIO_CH_7;
+    }
+
+    return ret;
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/common/R_BSP_SerialFamily.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "r_bsp_cmn.h"
+#include "R_BSP_SerialFamily.h"
+#include "posix_types.h"
+#include "r_errno.h"
+
+#define PATH_NAME_LENGTH            (3)      /* Path name length */
+#define PATH_TOP_PART               (0)      /* Path top part */
+#define CH_ID_PART                  (1)      /* Channel identifier part */
+#define TERM_CHAR_PART              (2)      /* Termination character part */
+#define PATH_SEPARATOR              ('\\')   /* Path separator */
+#define CHARACTER_0                 (0x30)   /* character 0 */
+
+R_BSP_SerialFamily::~R_BSP_SerialFamily() {
+    if (functions != NULL) {
+        if ((ch_handle != NULL) && (functions->close != NULL)) {
+            (void)functions->close(ch_handle, NULL);
+        }
+        if ((ch_no != -1) && (instance != NULL) && (functions->uninitialise_one != NULL)) {
+            (void)functions->uninitialise_one(ch_no, instance, NULL);
+        }
+    }
+}
+
+bool R_BSP_SerialFamily::init_channel(RBSP_MBED_FNS * function_list, int channel, void * const config_data,
+                                      int32_t max_write_num, int32_t max_read_num) {
+    bool    ret = false;
+    int32_t wk_errno;
+    char_t  path_name[PATH_NAME_LENGTH];
+
+    if ((channel >= 0) && (channel <= 9) && (function_list != NULL)) {
+        ch_no     = channel;
+        functions = function_list;
+
+        if ((functions->initialise_one != NULL) && (functions->open != NULL)) {
+            R_BSP_CMN_Init();
+            instance = functions->initialise_one(ch_no, config_data, &wk_errno);
+            if ((int32_t)instance != EERROR) {
+                path_name[PATH_TOP_PART]  = PATH_SEPARATOR;
+                path_name[CH_ID_PART]     = CHARACTER_0 + ch_no;
+                path_name[TERM_CHAR_PART] = '\0';
+                ch_handle = (void *)functions->open(instance, path_name, O_RDWR, 0, &wk_errno);
+                if ((int32_t)ch_handle != EERROR) {
+                    if (functions->write_a != NULL) {
+                        write_init(ch_handle, (void *)functions->write_a, max_write_num);
+                    }
+                    if (functions->read_a != NULL) {
+                        read_init(ch_handle, (void *)functions->read_a, max_read_num);
+                    }
+                    ret = true;
+                } else {
+                    (void)((RBSP_MBED_FNS *)functions)->uninitialise_one(ch_no, instance, NULL);
+                }
+            }
+        }
+    }
+
+    if (ret == false) {
+        functions = NULL;
+        instance  = NULL;
+        ch_handle = NULL;
+        ch_no     = -1;
+    }
+
+    return ret;
+}
+
+bool R_BSP_SerialFamily::ioctl(int request, ...) {
+    bool    ret = true;
+    int32_t wk_errno;
+    void *buf;
+    va_list ap;
+
+    if (functions == NULL) {
+        ret = false;
+    } else if (functions->ioctl == NULL) {
+        ret = false;
+    } else {
+        va_start(ap, request);
+        buf = (void *)va_arg(ap, void*);
+        functions->ioctl(ch_handle, request, buf, &wk_errno);
+        va_end(ap);
+        if (wk_errno != ESUCCESS) {
+            ret = false;
+        }
+    }
+
+    return ret;
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/common/R_BSP_Ssif.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,70 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "r_bsp_cmn.h"
+#include "R_BSP_Ssif.h"
+#include "ssif_if.h"
+#include "ssif_api.h"
+
+R_BSP_Ssif::R_BSP_Ssif(PinName sck, PinName ws, PinName tx, PinName rx, uint8_t int_level, int32_t max_write_num, int32_t max_read_num) {
+    int32_t wk_channel;
+
+    wk_channel = ssif_init(sck, ws, tx, rx);
+    if (wk_channel != NC) {
+        ssif_ch      = wk_channel;
+
+        ssif_cfg.enabled                = true;
+        ssif_cfg.int_level              = 0x78;
+        ssif_cfg.slave_mode             = true;
+        ssif_cfg.sample_freq            = 44100u;
+        ssif_cfg.clk_select             = SSIF_CFG_CKS_AUDIO_X1;
+        ssif_cfg.multi_ch               = SSIF_CFG_MULTI_CH_1;
+        ssif_cfg.data_word              = SSIF_CFG_DATA_WORD_16;
+        ssif_cfg.system_word            = SSIF_CFG_SYSTEM_WORD_32;
+        ssif_cfg.bclk_pol               = SSIF_CFG_FALLING;
+        ssif_cfg.ws_pol                 = SSIF_CFG_WS_LOW;
+        ssif_cfg.padding_pol            = SSIF_CFG_PADDING_LOW;
+        ssif_cfg.serial_alignment       = SSIF_CFG_DATA_FIRST;
+        ssif_cfg.parallel_alignment     = SSIF_CFG_LEFT;
+        ssif_cfg.ws_delay               = SSIF_CFG_DELAY;
+        ssif_cfg.noise_cancel           = SSIF_CFG_ENABLE_NOISE_CANCEL;
+        ssif_cfg.tdm_mode               = SSIF_CFG_DISABLE_TDM;
+        ssif_cfg.romdec_direct.mode     = SSIF_CFG_DISABLE_ROMDEC_DIRECT;
+        ssif_cfg.romdec_direct.p_cbfunc = NULL;
+
+        init_channel(R_SSIF_MakeCbTbl_mbed(), ssif_ch, &ssif_cfg, max_write_num, max_read_num);
+    }
+}
+
+R_BSP_Ssif::~R_BSP_Ssif() {
+    // do nothing
+}
+
+bool R_BSP_Ssif::ConfigChannel(const ssif_channel_cfg_t* const p_ch_cfg) {
+    return ioctl(SSIF_CONFIG_CHANNEL, (void *)p_ch_cfg);
+}
+
+bool R_BSP_Ssif::GetStatus(uint32_t* const p_status) {
+    return ioctl(SSIF_CONFIG_CHANNEL, (void *)p_status);
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/tools/R_BSP_mbed_fns.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,55 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+
+#ifndef R_BSP_MBED_FNS_H
+#define R_BSP_MBED_FNS_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+#include "ioif_aio.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+typedef struct {
+    void *(*initialise_one)(const int_t channel, const void* const config_data, int32_t* const p_errno);
+    int_t (*uninitialise_one)(const int_t channel, const void* const driver_instance, int32_t* const p_errno);
+    int_t (*open)(void *driver_instance, const char_t *pathname, int_t flags, int_t mode, int32_t* p_errno);
+    int_t (*close)(void *fd, int32_t* p_errno);
+    int_t (*ioctl)(void *fd, int_t request, void *buf, int32_t* p_errno);
+    int_t (*read_a)(void *fd, struct aiocb *p_aio, int32_t* p_errno);
+    int_t (*write_a)(void *fd, struct aiocb *p_aio, int32_t* p_errno);
+    int_t (*cancel)(void *fd, struct aiocb *p_aio, int32_t* p_errno);
+} RBSP_MBED_FNS;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_MBED_FNS_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/tools/Renesas_RZ_A1.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,26 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "VKRZA1H.h"
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/tools/bsp_util.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,133 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         bsp_util.c
+* $Rev: 891 $
+* $Date:: 2014-06-27 10:40:52 +0900#$
+* @brief        BSP Utilities
+******************************************************************************/
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    rt_CMSIS.c
+ *      Purpose: CMSIS RTOS API
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "cmsis_os.h"
+#include "Renesas_RZ_A1.h"
+#include "bsp_util.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+extern uint32_t IRQNestLevel; /* Indicates whether inside an ISR, and the depth of nesting.  0 = not in ISR. */
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+* Function Name: R_ExceptionalMode
+* @brief         Get current context
+*
+*                Description:<br>
+*                
+* @param         none
+* @retval 0      Current context is non-task
+* @retval 1      Current context is task
+******************************************************************************/
+int32_t R_ExceptionalMode(void)
+{
+    int32_t ret = 0;
+
+    switch(__get_CPSR() & 0x1fu)
+    {
+    case MODE_USR:
+        break;
+    case MODE_SYS:
+        break;
+    case MODE_SVC:
+        if (IRQNestLevel == 0)
+        {
+            /* handling a regular service call */
+        }
+        else
+        {
+            /* handling an ISR in SVC mode */
+            ret = 1;
+        }
+        break;
+    default:
+        ret = 1;
+        break;
+    }
+    return ret;
+}
+
+/******************************************************************************
+End of file
+******************************************************************************/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/tools/r_bsp_cmn.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,85 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include <stdio.h>
+#include "dma_if.h"
+
+
+static bool_t dma_init_end = false;
+static dma_drv_init_t dma_init_param;
+void userdef_dma_error_callback(union sigval signo);
+static AIOCB dma_err_aio;
+
+int32_t R_BSP_CMN_Init(void) {
+    int32_t retval = ESUCCESS;
+
+    if (dma_init_end == false) {
+        dma_init_end = true;
+        /***********************************************************************/
+        /* Initialise DMA */
+        /***********************************************************************/
+
+        dma_init_param.channel[DMA_CH_0] = true;
+        dma_init_param.channel[DMA_CH_1] = true;
+        dma_init_param.channel[DMA_CH_2] = true;
+        dma_init_param.channel[DMA_CH_3] = true;
+        dma_init_param.channel[DMA_CH_4] = true;
+        dma_init_param.channel[DMA_CH_5] = true;
+        dma_init_param.channel[DMA_CH_6] = true;
+        dma_init_param.channel[DMA_CH_7] = true;
+        dma_init_param.channel[DMA_CH_8] = true;
+        dma_init_param.channel[DMA_CH_9] = true;
+        dma_init_param.channel[DMA_CH_10] = true;
+        dma_init_param.channel[DMA_CH_11] = true;
+        dma_init_param.channel[DMA_CH_12] = true;
+        dma_init_param.channel[DMA_CH_13] = true;
+        dma_init_param.channel[DMA_CH_14] = true;
+        dma_init_param.channel[DMA_CH_15] = true;
+
+        dma_err_aio.aio_sigevent.sigev_notify = SIGEV_THREAD;
+        dma_err_aio.aio_sigevent.sigev_notify_function = &userdef_dma_error_callback;
+        dma_init_param.p_aio = &dma_err_aio;
+
+        retval = R_DMA_Init(&dma_init_param, NULL);
+        if (retval != ESUCCESS) {
+            dma_init_end = false;
+        }
+    }
+
+    return retval;
+}
+
+/**************************************************************************//**
+* Function Name: userdef_dma_error_callback
+* @brief         DMA driver : error callback function
+*
+*                Description:<br>
+*                DMA error interrupt callback function
+* @param[in]     signo.sival_int : bitmap of error channel(bit0=ch0)
+* @retval        none
+******************************************************************************/
+void userdef_dma_error_callback(union sigval signo) {
+    printf("DMAERR MAP:0x%02x\n", signo.sival_int);
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/tools/r_bsp_cmn.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,49 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+
+#ifndef R_BSP_CMN_H
+#define R_BSP_CMN_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+
+#include "cmsis_os.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/***********************************************************************************
+ Function Prototypes
+***********************************************************************************/
+extern int32_t R_BSP_CMN_Init(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* R_BSP_CMN_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/tools/ssif_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,145 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#include "ssif_api.h"
+
+static const PinMap PinMap_SSIF_SCK[] = {
+//   pin      ch     func
+    {P2_8   , 0    , 4},
+    {P4_4   , 0    , 5},
+    {P3_4   , 1    , 3},
+    {P7_1   , 1    , 6},
+    {P7_5   , 2    , 6},
+    {P9_5   , 2    , 3},
+    {P4_12  , 3    , 6},
+    {P7_8   , 3    , 2},
+    {P7_12  , 4    , 2},
+    {P8_12  , 4    , 8},
+    {P2_4   , 5    , 4},
+    {P4_8   , 5    , 5},
+    {P8_8   , 5    , 8},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_WS[] = {
+//   pin      ch     func
+    {P2_9   , 0    , 4},
+    {P4_5   , 0    , 5},
+    {P3_5   , 1    , 3},
+    {P7_2   , 1    , 6},
+    {P7_6   , 2    , 6},
+    {P9_6   , 2    , 3},
+    {P4_13  , 3    , 6},
+    {P7_9   , 3    , 2},
+    {P7_13  , 4    , 2},
+    {P8_13  , 4    , 8},
+    {P2_5   , 5    , 4},
+    {P4_9   , 5    , 5},
+    {P8_9   , 5    , 8},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_TxD[] = {
+//   pin      ch     func
+    {P2_11  , 0    , 4},
+    {P4_7   , 0    , 5},
+    {P7_4   , 1    , 6},
+    {P7_7   , 2    , 6},  /* SSIDATA2 */
+    {P9_7   , 2    , 3},  /* SSIDATA2 */
+    {P4_15  , 3    , 6},
+    {P7_11  , 3    , 2},
+    {P6_1   , 4    , 6},  /* SSIDATA4 */
+    {P7_14  , 4    , 2},  /* SSIDATA4 */
+    {P8_14  , 4    , 8},  /* SSIDATA4 */
+    {P2_7   , 5    , 4},
+    {P4_11  , 5    , 5},
+    {P8_10  , 5    , 8},
+    {NC     , NC   , 0}
+};
+
+static const PinMap PinMap_SSIF_RxD[] = {
+//   pin      ch     func
+    {P2_10  , 0    , 4},
+    {P4_6   , 0    , 5},
+    {P3_7   , 1    , 3},
+    {P7_3   , 1    , 6},
+    {P7_7   , 2    , 6},  /* SSIDATA2 */
+    {P9_7   , 2    , 3},  /* SSIDATA2 */
+    {P4_14  , 3    , 6},
+    {P7_10  , 3    , 2},
+    {P6_1   , 4    , 6},  /* SSIDATA4 */
+    {P7_14  , 4    , 2},  /* SSIDATA4 */
+    {P8_14  , 4    , 8},  /* SSIDATA4 */
+    {P2_6   , 5    , 4},
+    {P4_10  , 5    , 5},
+    {NC     , NC   , 0}
+};
+
+static void ssif_power_enable(uint32_t ssif_ch) {
+    volatile uint8_t dummy;
+
+    switch (ssif_ch) {
+        case 0:
+            CPGSTBCR11 &= ~(0x20);
+            break;
+        case 1:
+            CPGSTBCR11 &= ~(0x10);
+            break;
+        case 2:
+            CPGSTBCR11 &= ~(0x08);
+            break;
+        case 3:
+            CPGSTBCR11 &= ~(0x04);
+            break;
+        case 4:
+            CPGSTBCR11 &= ~(0x02);
+            break;
+        case 5:
+            CPGSTBCR11 &= ~(0x01);
+            break;
+    }
+    dummy = CPGSTBCR11;
+}
+
+int32_t ssif_init(PinName sck, PinName ws, PinName tx, PinName rx) {
+    /* determine the ssif to use */
+    uint32_t ssif_sck = pinmap_peripheral(sck, PinMap_SSIF_SCK);
+    uint32_t ssif_ws  = pinmap_peripheral(ws,  PinMap_SSIF_WS);
+    uint32_t ssif_tx  = pinmap_peripheral(tx,  PinMap_SSIF_TxD);
+    uint32_t ssif_rx  = pinmap_peripheral(rx,  PinMap_SSIF_RxD);
+    uint32_t ssif_ch  = pinmap_merge(ssif_tx, ssif_rx);
+
+    if ((ssif_ch == ssif_sck) && (ssif_ch == ssif_ws)) {
+        ssif_power_enable(ssif_ch);
+        pinmap_pinout(sck, PinMap_SSIF_SCK);
+        pinmap_pinout(ws,  PinMap_SSIF_WS);
+        pinmap_pinout(tx,  PinMap_SSIF_TxD);
+        pinmap_pinout(rx,  PinMap_SSIF_RxD);
+    } else {
+        ssif_ch = (uint32_t)NC;
+    }
+
+    return (int32_t)ssif_ch;
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/R_BSP/tools/ssif_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,40 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef MBED_SSIF_API_H
+#define MBED_SSIF_API_H
+
+#include "pinmap.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int32_t ssif_init(PinName sck, PinName ws, PinName tx, PinName rx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/main.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1223 @@
+/*
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+ 
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+ 
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*/
+
+
+#define __SOFT_JPEG__
+
+#include "mbed.h"
+#include "rga_func.h"
+#include "DisplayBace.h"
+#include "rtos.h"
+#include "LcdCfg.h"
+#include "Touch.h"
+#include "rza_io_regrw.h"
+#include "USBHostCam.h"
+//#include "JPEG_Converter.h"
+
+#include "Images/BinaryImage_RZ_A1H.h"
+
+#ifdef __SOFT_JPEG__
+#include "jpeglib.h"
+#include <setjmp.h>
+#endif
+
+#define VIDEO_CVBS             (0)                 /* Analog  Video Signal */
+#define VIDEO_CMOS_CAMERA      (1)                 /* Digital Video Signal */
+
+#define VIDEO_YCBCR422         (0)
+#define VIDEO_RGB888           (1)
+#define VIDEO_RGB565           (2)
+
+/**** User Selection *********/
+#define VIDEO_INPUT_METHOD     (VIDEO_CVBS)        /* Select  VIDEO_CVBS or VIDEO_CMOS_CAMERA                       */
+#define VIDEO_INPUT_FORMAT     (VIDEO_RGB565)      /* Select  VIDEO_YCBCR422 or VIDEO_RGB888 or VIDEO_RGB565        */
+#define USE_VIDEO_CH           (0)                 /* Select  0 or 1            If selecting VIDEO_CMOS_CAMERA, should be 0.)               */
+#define VIDEO_PAL              (1)                 /* Select  0(NTSC) or 1(PAL) If selecting VIDEO_CVBS, this parameter is not referenced.) */
+/*****************************/
+
+#if USE_VIDEO_CH == (0)
+#define VIDEO_INPUT_CH         (DisplayBase::VIDEO_INPUT_CHANNEL_0)
+#define VIDEO_INT_TYPE         (DisplayBase::INT_TYPE_S0_VFIELD)
+#else
+#define VIDEO_INPUT_CH         (DisplayBase::VIDEO_INPUT_CHANNEL_1)
+#define VIDEO_INT_TYPE         (DisplayBase::INT_TYPE_S1_VFIELD)
+#endif
+
+/** Video and Grapics (GRAPHICS_LAYER_0) parameter **/
+/* NTSC or PAL */
+#if VIDEO_PAL == 0
+  #define COL_SYS              (DisplayBase::COL_SYS_NTSC_358)
+#else
+  #define COL_SYS              (DisplayBase::COL_SYS_PAL_443)
+#endif
+
+/* Video input and LCD layer 0 output */
+#if VIDEO_INPUT_FORMAT == VIDEO_YCBCR422
+  #define VIDEO_FORMAT         (DisplayBase::VIDEO_FORMAT_YCBCR422)
+  #define GRAPHICS_FORMAT      (DisplayBase::GRAPHICS_FORMAT_YCBCR422)
+  #define WR_RD_WRSWA          (DisplayBase::WR_RD_WRSWA_NON)
+#elif VIDEO_INPUT_FORMAT == VIDEO_RGB565
+  #define VIDEO_FORMAT         (DisplayBase::VIDEO_FORMAT_RGB565)
+  #define GRAPHICS_FORMAT      (DisplayBase::GRAPHICS_FORMAT_RGB565)
+  #define WR_RD_WRSWA          (DisplayBase::WR_RD_WRSWA_32_16BIT)
+#else
+  #define VIDEO_FORMAT         (DisplayBase::VIDEO_FORMAT_RGB888)
+  #define GRAPHICS_FORMAT      (DisplayBase::GRAPHICS_FORMAT_RGB888)
+  #define WR_RD_WRSWA          (DisplayBase::WR_RD_WRSWA_32BIT)
+#endif
+
+/* NOSIGNAL bit position */
+#define NOSIGNAL			   (11u)
+#define MASK(n)				   (1<<(n))
+
+#define MAX_TRY				   3
+
+/* FRAME BUFFER Parameter */
+#if ( VIDEO_INPUT_FORMAT == VIDEO_YCBCR422 || VIDEO_INPUT_FORMAT == VIDEO_RGB565 )
+  #define FRAME_BUFFER_BYTE_PER_PIXEL         (2u)
+#else
+  #define FRAME_BUFFER_BYTE_PER_PIXEL         (4u)
+#endif
+#define FRAME_BUFFER_STRIDE                 (((LCD_PIXEL_WIDTH * FRAME_BUFFER_BYTE_PER_PIXEL) + 31u) & ~31u)
+#define FASTR_RENDER							user_video_buffer
+
+#define DRAW_RECTANGLE_CNT_MAX              (4)
+#define TOUCH_NUM                           (1u)
+#define ROTRNDR_SIZE						((uint8_t*)Board_wide_jpg_File - (uint8_t *)Board_jpg_File)
+#define SCRRNDR_SIZE						((uint8_t*)TopScrn_jpg_File - (uint8_t *)Board_wide_jpg_File)
+
+#define VID_X	0
+#define VID_Y	0
+#define VID_W	LCD_PIXEL_WIDTH-SLIDE_WIDTH
+#define VID_H	SLIDE_WIDTH
+
+#define RVID_X	SLIDE_WIDTH
+#define RVID_Y	LCD_PIXEL_HEIGHT-SLIDE_WIDTH
+#define RVID_W	LCD_PIXEL_WIDTH-SLIDE_WIDTH
+#define RVID_H	SLIDE_WIDTH
+
+
+#define CAM_X	LCD_PIXEL_WIDTH-SLIDE_WIDTH
+#define CAM_Y   0
+#define CAM_W   SLIDE_WIDTH
+#define CAM_H	LCD_PIXEL_HEIGHT
+
+#define RCAM_X	0
+#define RCAM_Y  0
+#define RCAM_W  SLIDE_WIDTH
+#define RCAM_H	LCD_PIXEL_HEIGHT
+
+
+typedef enum {
+    RGA_FUNC_NON,
+    RGA_FUNC_DRAW_RECTANGLE,
+    RGA_FUNC_DRAW_IMAGE,
+    RGA_FUNC_DISSOLVE,
+    RGA_FUNC_SCROLL,
+    RGA_FUNC_ZOOM,
+    RGA_FUNC_ROTATION,
+    RGA_FUNC_ACCELERATE,
+    RGA_FUNC_ANIME_EASE,
+    RGA_FUNC_ANIME_LINEAR,
+    RGA_FUNC_ANIME_EASE_IN,
+    RGA_FUNC_ANIME_EASE_OUT,
+    RGA_FUNC_ANIME_EASE_IN_OUT,
+    RGA_FUNC_RETURN,
+	RGA_FUNC_AUTO_MANUAL,
+	RGA_FUNC_VIDEO,
+	RGA_FUNC_USBCAM,
+    RGA_FUNC_END
+} func_code_t;
+
+DigitalOut  test_point(LED1);
+PwmOut      lcd_cntrst(P8_15);
+DisplayBase Display;
+Touch 		STMPE811;
+USBHostCam  Cam(_432x240);
+interact_t Interaction_mode;
+
+typedef struct {
+        uint32_t x;      /**< The position of the x-coordinate. */
+        uint32_t y;      /**< The position of the y-coordinate. */
+        bool     touch_down;  /**< IS stylus still down */
+} touch_pos_t;
+
+typedef struct {
+    uint32_t pic_pos_x;             /* X position of the key picture. */
+    uint32_t pic_pos_y;             /* Y position of the key picture. */
+    uint32_t pic_width;             /* Width of the key picture. */
+    uint32_t pic_height;            /* Height of the key picture. */
+    func_code_t func_code;          /* func code of the key picture. */
+} key_pic_info_t;
+
+#ifdef __SOFT_JPEG__
+struct my_error_mgr {
+  struct jpeg_error_mgr pub;	/* "public" fields */
+
+  jmp_buf setjmp_buffer;	/* for return to caller */
+};
+
+typedef struct my_error_mgr * my_error_ptr;
+#endif
+
+#if defined(__ICCARM__)
+#pragma data_alignment=32
+static uint8_t user_frame_buffer1[FRAME_BUFFER_STRIDE * LCD_PIXEL_HEIGHT];
+static uint8_t user_frame_buffer2[FRAME_BUFFER_STRIDE * LCD_PIXEL_HEIGHT];
+static uint8_t  user_video_buffer[FRAME_BUFFER_STRIDE * LCD_PIXEL_HEIGHT];
+#pragma data_alignment=4
+#else
+static uint8_t user_frame_buffer1[FRAME_BUFFER_STRIDE * LCD_PIXEL_HEIGHT]__attribute((aligned(32))); /* 32 bytes aligned */
+static uint8_t user_frame_buffer2[FRAME_BUFFER_STRIDE * LCD_PIXEL_HEIGHT]__attribute((aligned(32))); /* 32 bytes aligned */
+static uint8_t  user_video_buffer[FRAME_BUFFER_STRIDE * LCD_PIXEL_HEIGHT]__attribute((aligned(32))); /* 32 bytes aligned */
+static uint8_t 		  shot_buffer[100                 *             1024]__attribute((aligned(32))); /* 32 bytes aligned */
+//static uint8_t 		  shot_buffer[200*1024]__attribute((section("NC_BSS"),aligned(32))); /* 32 bytes aligned */
+#endif
+static frame_buffer_t frame_buffer_info;
+static volatile int32_t vsync_count = 0;
+//static volatile int32_t vfield_count_0 = 1;
+static volatile bool usb_plug = false;
+static volatile bool video_signal = false;
+static volatile bool try_cam_connect = false;
+static volatile DisplayBase::slide_t slide_screen = DisplayBase::SLIDE_NONE;
+static bool graphics_init_end = false;
+
+
+#if (LCD_VDC5_CH0_PANEL == LCD_CH0_PANEL_VKLCD70RT)
+  static const key_pic_info_t top_screen_key_tbl[] = {
+    /*   X       Y     Width   Height   Func code                 */
+    {    40,    468,    102,    106,    RGA_FUNC_DRAW_RECTANGLE    },  /* RGA Func1 */
+    {   180,    468,    102,    106,    RGA_FUNC_DRAW_IMAGE        },  /* RGA Func2 */
+    {   322,    468,    102,    106,    RGA_FUNC_DISSOLVE          },  /* RGA Func3 */
+    {   462,    468,    102,    106,    RGA_FUNC_SCROLL            },  /* RGA Func4 */
+    {   884,    468,    102,    106,    RGA_FUNC_ZOOM              },  /* RGA Func5 */
+    {   604,    468,    102,    106,    RGA_FUNC_ROTATION          },  /* RGA Func6 */
+    {   744,    468,    102,    106,    RGA_FUNC_ACCELERATE        },  /* RGA Func7 */
+	{ VID_X,  VID_Y,  VID_W,  VID_H,	RGA_FUNC_VIDEO             },  /* RGA FuncN */
+	{ CAM_X,  CAM_Y,  CAM_W,  CAM_H,	RGA_FUNC_USBCAM			   },
+    {     0,      0,      0,      0,    RGA_FUNC_END               }   /* table end */
+  };
+
+  static const key_pic_info_t return_key_tbl[] = {
+    /*   X       Y     Width   Height   Func code                 */
+    {   792,      6,    226,     93,    RGA_FUNC_RETURN            },  /* Return Top Screen */
+	{   849,    230,    117,    124,    RGA_FUNC_AUTO_MANUAL       },  /* Interaction_Mode */
+    {     0,      0,      0,      0,    RGA_FUNC_END               }   /* table end */
+  };
+
+  static const key_pic_info_t animetion_timing_key_tbl[] = {
+    /*   X       Y     Width   Height   Func code                 */
+    {   792,      6,    226,     93,    RGA_FUNC_RETURN            },  /* Return Top Screen */
+    {    21,    501,    173,     66,    RGA_FUNC_ANIME_EASE        },  /* ease */
+    {   220,    501,    173,     66,    RGA_FUNC_ANIME_LINEAR      },  /* linear */
+    {   422,    501,    173,     66,    RGA_FUNC_ANIME_EASE_IN     },  /* ease-in */
+    {   623,    501,    173,     66,    RGA_FUNC_ANIME_EASE_OUT    },  /* ease-out */
+    {   823,    501,    173,     66,    RGA_FUNC_ANIME_EASE_IN_OUT },  /* ease-in-out */
+    {     0,      0,      0,      0,    RGA_FUNC_END               }   /* table end */
+  };
+#else
+  static const key_pic_info_t top_screen_key_tbl[] = {
+    /*   X       Y     Width   Height   Func code                 */
+    {    18,    216,     50,     50,    RGA_FUNC_DRAW_RECTANGLE    },  /* RGA Func1 */
+    {    84,    216,     50,     50,    RGA_FUNC_DRAW_IMAGE        },  /* RGA Func2 */
+    {   150,    216,     50,     50,    RGA_FUNC_DISSOLVE          },  /* RGA Func3 */
+    {   216,    216,     50,     50,    RGA_FUNC_SCROLL            },  /* RGA Func4 */
+    {   414,    216,     50,     50,    RGA_FUNC_ZOOM              },  /* RGA Func5 */
+    {   282,    216,     50,     50,    RGA_FUNC_ROTATION          },  /* RGA Func6 */
+    {   348,    216,     50,     50,    RGA_FUNC_ACCELERATE        },  /* RGA Func7 */
+	{ VID_X,  VID_Y,  VID_W,  VID_H,	RGA_FUNC_VIDEO             },  /* RGA FuncN */
+	{ CAM_X,  CAM_Y,  CAM_W,  CAM_H,	RGA_FUNC_USBCAM			   },
+    {     0,      0,      0,      0,    RGA_FUNC_END               }   /* table end */
+  };
+
+  static const key_pic_info_t return_key_tbl[] = {
+    /*   X       Y     Width   Height   Func code                 */
+    {   372,      6,    104,     40,    RGA_FUNC_RETURN            },  /* Return Top Screen */
+	{   398,    104,     55,     56,    RGA_FUNC_AUTO_MANUAL       },  /* Interaction_Mode */
+    {     0,      0,      0,      0,    RGA_FUNC_END               }   /* table end */
+  };
+
+  static const key_pic_info_t animetion_timing_key_tbl[] = {
+    /*   X       Y     Width   Height   Func code                 */
+    {   372,      6,    104,     40,    RGA_FUNC_RETURN            },  /* Return Top Screen */
+    {    10,    227,     81,     30,    RGA_FUNC_ANIME_EASE        },  /* ease */
+    {   103,    227,     81,     30,    RGA_FUNC_ANIME_LINEAR      },  /* linear */
+    {   198,    227,     81,     30,    RGA_FUNC_ANIME_EASE_IN     },  /* ease-in */
+    {   292,    227,     81,     30,    RGA_FUNC_ANIME_EASE_OUT    },  /* ease-out */
+    {   386,    227,     81,     30,    RGA_FUNC_ANIME_EASE_IN_OUT },  /* ease-in-out */
+    {     0,      0,      0,      0,    RGA_FUNC_END               }   /* table end */
+  };
+#endif
+
+  static const key_pic_info_t video_screen_key_tbl[] = {
+    /*   X       Y     Width   Height   Func code				   */
+    {RVID_X, RVID_Y, RVID_W, RVID_H,	RGA_FUNC_RETURN				},  /* Return Top Screen */
+    {     0,      0,      0,      0,    RGA_FUNC_END				}   /* table end */
+  };
+
+  static const key_pic_info_t cam_screen_key_tbl[] = {
+    /*   X       Y     Width   Height   Func code                  */
+    {RCAM_X, RCAM_Y, RCAM_W, RCAM_H,	RGA_FUNC_RETURN				},  /* Return Top Screen */
+    {     0,      0,      0,      0,    RGA_FUNC_END				}   /* table end */
+  };
+
+#ifdef __SOFT_JPEG__
+METHODDEF(void)
+my_error_exit (j_common_ptr cinfo)
+  {
+    /* cinfo->err really points to a my_error_mgr struct, so coerce pointer */
+    my_error_ptr myerr = (my_error_ptr) cinfo->err;
+
+    /* Always display the message. */
+    /* We could postpone this until after returning, if we chose. */
+    (*cinfo->err->output_message) (cinfo);
+
+    /* Return control to the setjmp point */
+    longjmp(myerr->setjmp_buffer, 1);
+  }
+#endif
+
+
+/****** LCD ******/
+static void IntCallbackFunc_LoVsync(DisplayBase::int_type_t int_type) {
+	bool plug = Cam.plugged();
+    /* Interrupt callback function for Vsync interruption */
+    if (vsync_count > 0) {
+        vsync_count--;
+    }
+
+    if(slide_screen != DisplayBase::SLIDE_NONE)
+    {
+    	Display.Graphics_Read_Change_More(DisplayBase::GRAPHICS_LAYER_2,
+    	(void *)frame_buffer_info.buffer_address[frame_buffer_info.draw_buffer_index], FRAME_BUFFER_STRIDE, (DisplayBase::slide_t *)&slide_screen);
+    }
+
+    /* Read NOSIGNAL bit */
+    video_signal = (RZA_IO_RegRead_16(&DVDEC0.VSYNCSR, NOSIGNAL, MASK(NOSIGNAL)))? false : true;
+    /* Read USB ATTCH DTTCH signals */
+    if(plug ^ usb_plug)
+    {
+  		try_cam_connect = plug;
+        usb_plug = plug;
+    }
+}
+
+static void Wait_Vsync(const int32_t wait_count) {
+    /* Wait for the specified number of times Vsync occurs */
+    vsync_count = wait_count;
+    while (vsync_count > 0) {
+        /* Do nothing */
+    }
+}
+
+static void IntCallbackFunc_Vfield_0(DisplayBase::int_type_t int_type) {
+    /*DisplayBase::graphics_error_t error;
+
+    // Interrupt callback function
+    if (vfield_count_0 == 0) {
+        vfield_count_0 = 1;
+        error = Display.Video_Stop( DisplayBase::VIDEO_INPUT_CHANNEL_0 );
+        if (error != DisplayBase::GRAPHICS_OK) {
+            printf("Line %d, error %d\n", __LINE__, error);
+            mbed_die();
+        }
+    } else {
+        ;
+    }*/
+}
+
+static void Init_LCD_Display(void) {
+    DisplayBase::graphics_error_t error;
+    DisplayBase::lcd_config_t lcd_config;
+
+	#if (LCD_VDC5_CH0_PANEL == LCD_CH0_PANEL_VKLCD70RT)
+    	PinName lvds_pin[] = {P5_7, P5_6, P5_5, P5_4, P5_3, P5_2, P5_1, P5_0};
+    	Display.Graphics_Lvds_Port_Init(lvds_pin, sizeof(lvds_pin)/sizeof(lvds_pin[0]));
+	#else 	 	 	 	  /* D15,  D14,  D13,  D12,  D11,  D10,   D9,   D8,   D7,    D6,    D5,    D4,    D3,    D2,    D1,   D0,   DE,  CLK */
+    	PinName lcd_pin[] = {P4_7, P4_6, P4_5, P4_4, P4_3, P4_2, P4_1, P4_0, P3_15, P3_14, P3_13, P3_12, P3_11, P3_10, P3_9, P3_8, P3_1, P3_0};
+    	Display.Graphics_Lcd_Port_Init(lcd_pin, sizeof(lcd_pin)/sizeof(lcd_pin[0]));
+    #endif
+
+
+    /* Graphics initialization process */
+    lcd_config = LcdCfgTbl;
+    error = Display.Graphics_init(&lcd_config);
+    if (error != DisplayBase::GRAPHICS_OK) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        mbed_die();
+    }
+
+    /* Interrupt callback function setting (Vsync signal output from scaler 0) */
+    error = Display.Graphics_Irq_Handler_Set(DisplayBase::INT_TYPE_S0_LO_VSYNC, 0, IntCallbackFunc_LoVsync);
+    if (error != DisplayBase::GRAPHICS_OK) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        mbed_die();
+    }
+
+    graphics_init_end = true;
+}
+
+/****** Video ******/
+static void Init_Video(void) {
+    DisplayBase::graphics_error_t error;
+
+    /* Graphics initialization process */
+    if (graphics_init_end == false) {
+        /* When not initializing LCD, this processing is needed. */
+        error = Display.Graphics_init(NULL);
+        if (error != DisplayBase::GRAPHICS_OK) {
+            printf("Line %d, error %d\n", __LINE__, error);
+            mbed_die();
+        }
+        graphics_init_end = true;
+    }
+
+    error = Display.Graphics_Video_init( DisplayBase::INPUT_SEL_VDEC, NULL);
+    if( error != DisplayBase::GRAPHICS_OK ) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        mbed_die();
+    }
+
+    /* Interrupt callback function setting (Field end signal for recording function in scaler 0) */
+    error = Display.Graphics_Irq_Handler_Set(VIDEO_INT_TYPE, 0, IntCallbackFunc_Vfield_0);
+    if (error != DisplayBase::GRAPHICS_OK) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        mbed_die();
+    }
+}
+
+static void Start_Video(DisplayBase::video_input_channel_t ch, uint8_t * p_frame_buffer,
+ uint16_t pos_x, uint16_t pos_y, uint16_t width, uint16_t height) {
+    DisplayBase::graphics_error_t error;
+    //uint8_t * p_buf;
+
+    //p_buf = p_frame_buffer + (FRAME_BUFFER_BYTE_PER_PIXEL * pos_x) + (FRAME_BUFFER_STRIDE * pos_y);
+
+    /* Video capture setting (progressive form fixed) */
+    error = Display.Video_Write_Setting(
+                ch,
+                COL_SYS,
+				p_frame_buffer, //p_buf,
+                FRAME_BUFFER_STRIDE,
+                VIDEO_FORMAT,
+                WR_RD_WRSWA,
+				height, //(height & ~7u),      /* A multiple of 8 */
+				width   //(width  & ~15u)      /* A multiple of 16 */
+            );
+    if (error != DisplayBase::GRAPHICS_OK) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        mbed_die();
+    }
+
+    /* Video write process start */
+    error = Display.Video_Start(ch);
+    if (error != DisplayBase::GRAPHICS_OK) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        mbed_die();
+    }
+
+    error = Display.Video_Stop( DisplayBase::VIDEO_INPUT_CHANNEL_0 );
+    if (error != DisplayBase::GRAPHICS_OK) {
+        printf("Line %d, error %d\n", __LINE__, error);
+        mbed_die();
+    }
+}
+
+static void Start_LCD_Display(uint8_t * p_buf) {
+    DisplayBase::rect_t rect;
+
+    rect.vs = 0;
+    rect.vw = LCD_PIXEL_HEIGHT;
+    rect.hs = 0;
+    rect.hw = LCD_PIXEL_WIDTH;
+    Display.Graphics_Read_Setting(
+        DisplayBase::GRAPHICS_LAYER_0,
+        (void *)user_video_buffer,
+        FRAME_BUFFER_STRIDE,
+        GRAPHICS_FORMAT,
+        WR_RD_WRSWA,
+        &rect
+    );
+
+    Display.Graphics_Start(DisplayBase::GRAPHICS_LAYER_0);
+
+    rect.vs = 0;
+    rect.vw = LCD_PIXEL_HEIGHT;
+    rect.hs = 0;
+    rect.hw = LCD_PIXEL_WIDTH;
+    Display.Graphics_Read_Setting(
+        DisplayBase::GRAPHICS_LAYER_2,
+        (void *)p_buf,
+        FRAME_BUFFER_STRIDE,
+        GRAPHICS_FORMAT,
+        WR_RD_WRSWA,
+        &rect
+    );
+
+    Display.Graphics_Start(DisplayBase::GRAPHICS_LAYER_2);
+}
+
+static void Update_LCD_Display(frame_buffer_t * frmbuf_info) {
+    Display.Graphics_Read_Change(DisplayBase::GRAPHICS_LAYER_2,
+     (void *)frmbuf_info->buffer_address[frmbuf_info->draw_buffer_index]);
+    Wait_Vsync(1);
+}
+
+static void Update_VIDEO_Display(frame_buffer_t * frmbuf_info) {
+    Display.Graphics_Read_Change(DisplayBase::GRAPHICS_LAYER_0,
+     (void *)frmbuf_info->buffer_address[frmbuf_info->draw_buffer_index]);
+    Wait_Vsync(1);
+}
+
+static void Swap_FrameBuffer(frame_buffer_t * frmbuf_info) {
+    if (frmbuf_info->draw_buffer_index == 1) {
+        frmbuf_info->draw_buffer_index = 0;
+    } else {
+        frmbuf_info->draw_buffer_index = 1;
+    }
+}
+
+
+/****** Touch ******/
+static func_code_t Scan_Key(const key_pic_info_t * key_tbl, const uint32_t pos_x, const uint32_t pos_y) {
+    func_code_t ret = RGA_FUNC_NON;
+
+    while (ret == RGA_FUNC_NON) {
+        if (key_tbl->func_code == RGA_FUNC_END) {
+            break;
+        }
+        /* Check the range of the X position */
+        if ((pos_x >= key_tbl->pic_pos_x) && (pos_x <= (key_tbl->pic_pos_x + key_tbl->pic_width))) {
+            /* Check the range of the Y position */
+            if ((pos_y >= key_tbl->pic_pos_y) && (pos_y <= (key_tbl->pic_pos_y + key_tbl->pic_height))) {
+                /* Decide the func code. */
+                ret = key_tbl->func_code;
+            }
+        }
+        key_tbl++;
+    }
+
+    return ret;
+}
+
+static int GetCoordinates(touch_pos_t * p_touch) {
+	touch_pos_t * wk_touch;
+	int count = 0;
+	int i;
+
+	if (p_touch != NULL)
+	{
+		wk_touch        = p_touch;
+	    wk_touch->x     = 0;
+	    wk_touch->y     = 0;
+	    wk_touch->touch_down = false;
+
+	    wk_touch->touch_down = STMPE811.Handle_touch((uint8_t*)&count);
+	    if(count)
+	    {
+	    	wk_touch->x = STMPE811.x;
+	    	wk_touch->y = STMPE811.y;
+	    }
+	}
+
+	 return count;
+}
+
+/****** Efect ******/
+static void Exe_RGA_Func(func_code_t func_name, frame_buffer_t* frmbuf_info) {
+    uint8_t touch_num = 0;
+    touch_pos_t touch_pos[TOUCH_NUM];
+
+    switch (func_name) {
+        case RGA_FUNC_DRAW_RECTANGLE:
+            bool key_on = false;
+            bool first = false;
+            bool second = false;
+            int cnt = 0;
+            int color_cnt = 0;
+            int x_0 = 0;
+            int y_0 = 0;
+            draw_rectangle_pos_t pos_tbl[DRAW_RECTANGLE_CNT_MAX] = {0};
+
+            pos_tbl[0].style = "#FF0000";  /* red */
+            pos_tbl[1].style = "#00FF00";  /* green */
+            pos_tbl[2].style = "#0000FF";  /* blue */
+            pos_tbl[3].style = "#000000";  /* black */
+
+            while (1) {
+                /* Get coordinates */
+                touch_num = GetCoordinates(touch_pos);
+                if (touch_num != 0)
+                {
+                    if (Scan_Key(return_key_tbl, touch_pos[0].x, touch_pos[0].y) == RGA_FUNC_RETURN) {
+                        break;
+                    }
+                    if(touch_pos[0].touch_down)  {
+                    	if(!key_on)	{
+                    		pos_tbl[cnt].x = x_0 = touch_pos[0].x;
+                    		pos_tbl[cnt].y = y_0 = touch_pos[0].y;
+                    		pos_tbl[cnt].w = 0;
+							pos_tbl[cnt].h = 0;
+							if(cnt == 0) {
+								for (color_cnt = 1; color_cnt < DRAW_RECTANGLE_CNT_MAX; color_cnt++) {
+									pos_tbl[color_cnt].x = 0;
+							        pos_tbl[color_cnt].y = 0;
+							        pos_tbl[color_cnt].w = 0;
+							        pos_tbl[color_cnt].h = 0;
+							    }
+							}
+                    		key_on = true;
+                    	}
+                    	else {
+                    		if(touch_pos[0].x >= x_0) {
+                    			pos_tbl[cnt].x = x_0;
+                    			pos_tbl[cnt].w = touch_pos[0].x - pos_tbl[cnt].x;
+                    		}
+                    		else {
+                    			pos_tbl[cnt].x = touch_pos[0].x;
+                    			pos_tbl[cnt].w = x_0 - touch_pos[0].x;
+                    		}
+
+                    		if(touch_pos[0].y >= y_0) {
+                    			pos_tbl[cnt].y = y_0;
+                    			pos_tbl[cnt].h = touch_pos[0].y - pos_tbl[cnt].y;
+                    		}
+                    		else {
+                    			pos_tbl[cnt].y = touch_pos[0].y;
+								pos_tbl[cnt].h = y_0 - touch_pos[0].y;
+                    		}
+                    	}
+
+                    }
+                    else {
+                    	if(key_on) {
+                    		if(touch_pos[0].x >= x_0) {
+                    			pos_tbl[cnt].x = x_0;
+                    			pos_tbl[cnt].w = touch_pos[0].x - pos_tbl[cnt].x;
+                    		}
+                    		else {
+                    			pos_tbl[cnt].x = touch_pos[0].x;
+                    			pos_tbl[cnt].w = x_0 - touch_pos[0].x;
+                    		}
+
+                    		if(touch_pos[0].y >= y_0) {
+                    			pos_tbl[cnt].y = y_0;
+                    			pos_tbl[cnt].h = touch_pos[0].y - pos_tbl[cnt].y;
+                    		}
+                    		else {
+                    			pos_tbl[cnt].y = touch_pos[0].y;
+                    			pos_tbl[cnt].h = y_0 - touch_pos[0].y;
+                    		}
+
+                    		cnt++;
+                    		if (cnt == DRAW_RECTANGLE_CNT_MAX)
+                    			cnt = 0;
+                    		key_on = false;
+                    	}
+                    	else
+                    	{
+
+                    	}
+                    }
+                }
+                /* Draw screen */
+                Swap_FrameBuffer(frmbuf_info);
+                RGA_Func_DrawRectangle(frmbuf_info, pos_tbl, DRAW_RECTANGLE_CNT_MAX);
+                Update_LCD_Display(frmbuf_info);
+            }
+            break;
+        case RGA_FUNC_DRAW_IMAGE:
+            int center_pos_x = 320;
+            int center_pos_y = 110;
+            while (1) {
+                /* Get coordinates */
+                touch_num = GetCoordinates(touch_pos);
+                if (touch_num != 0) {
+                    if (Scan_Key(return_key_tbl, touch_pos[0].x, touch_pos[0].y) == RGA_FUNC_RETURN) {
+                        break;
+                    }
+                    center_pos_x = touch_pos[0].x;
+                    center_pos_y = touch_pos[0].y;
+                }
+                /* Draw screen */
+                Swap_FrameBuffer(frmbuf_info);
+                RGA_Func_DrawImage(frmbuf_info, center_pos_x, center_pos_y);
+                Update_LCD_Display(frmbuf_info);
+            }
+            break;
+        case RGA_FUNC_DISSOLVE:
+            float32_t work_alpha = 0.0f;
+            uint16_t xa = LCD_PIXEL_WIDTH;
+
+            RGA_Func_Dissolve(frmbuf_info, 0.0f, Interaction_mode);
+            Swap_FrameBuffer(frmbuf_info);
+            RGA_Func_Dissolve(frmbuf_info, 0.0f, Interaction_mode);
+            Update_LCD_Display(frmbuf_info);
+            memcpy(FASTR_RENDER, (uint8_t*)Board_jpg_File, ROTRNDR_SIZE);
+            while (1) {
+                /* Get coordinates */
+                touch_num = GetCoordinates(touch_pos);
+                if (touch_num != 0) {
+                	func_code_t func_code;
+
+                	func_code = Scan_Key(return_key_tbl, touch_pos[0].x, touch_pos[0].y);
+                    if (func_code == RGA_FUNC_RETURN) {
+                        break;
+                    }
+
+                    if(!touch_pos[0].touch_down && (func_code == RGA_FUNC_AUTO_MANUAL))
+                    	Interaction_mode = (Interaction_mode == AUTO_INTERACT)? MANUAL_INTERACT : AUTO_INTERACT;
+                    else
+                    	work_alpha = (float32_t)touch_pos[0].x / (float32_t)(LCD_PIXEL_WIDTH);
+                }
+                if(Interaction_mode == AUTO_INTERACT)
+                {
+                	xa= (xa >= LCD_PIXEL_WIDTH)? 0: (xa+1);
+                	work_alpha = (float32_t)xa / (float32_t)(LCD_PIXEL_WIDTH);
+                }
+                /* Draw screen */
+                Swap_FrameBuffer(frmbuf_info);
+                RGA_Func_Diss(frmbuf_info, work_alpha, Interaction_mode, (graphics_image_t*)FASTR_RENDER);
+                Update_LCD_Display(frmbuf_info);
+            }
+            break;
+        case RGA_FUNC_SCROLL:
+            int work_width_pos = 0;
+            uint16_t xs = LCD_PIXEL_WIDTH;
+
+            RGA_Func_Scroll(frmbuf_info, 0, Interaction_mode);
+            Swap_FrameBuffer(frmbuf_info);
+            RGA_Func_Scroll(frmbuf_info, 0, Interaction_mode);
+            Update_LCD_Display(frmbuf_info);
+            memcpy(FASTR_RENDER, (uint8_t*)Board_wide_jpg_File, SCRRNDR_SIZE);
+            while (1) {
+                /* Get coordinates */
+                touch_num = GetCoordinates(touch_pos);
+                if (touch_num != 0) {
+                	func_code_t func_code;
+
+                	func_code = Scan_Key(return_key_tbl, touch_pos[0].x, touch_pos[0].y);
+                    if (func_code == RGA_FUNC_RETURN) {
+                        break;
+                    }
+
+                    if(!touch_pos[0].touch_down && (func_code == RGA_FUNC_AUTO_MANUAL))
+                    	Interaction_mode = (Interaction_mode == AUTO_INTERACT)? MANUAL_INTERACT : AUTO_INTERACT;
+                    else
+                    	work_width_pos = SCROLL_MAX_NUM * ((float32_t)touch_pos[0].x / (float32_t)(LCD_PIXEL_WIDTH));
+                }
+                if(Interaction_mode == AUTO_INTERACT)
+                {
+                	xs= (xs >= LCD_PIXEL_WIDTH)? 0: (xs+1);
+                	work_width_pos = SCROLL_MAX_NUM * ((float32_t)xs / (float32_t)(LCD_PIXEL_WIDTH));
+                }
+                /* Draw screen */
+                Swap_FrameBuffer(frmbuf_info);
+                RGA_Func_Scr(frmbuf_info, work_width_pos, Interaction_mode, (graphics_image_t*)FASTR_RENDER);
+                Update_LCD_Display(frmbuf_info);
+            }
+            break;
+        case RGA_FUNC_ZOOM:
+            int work_height_pos = ZOOM_MAX_NUM;
+            uint16_t xz = LCD_PIXEL_WIDTH;
+
+            RGA_Func_Zoom(frmbuf_info,  0, Interaction_mode);
+            Swap_FrameBuffer(frmbuf_info);
+            RGA_Func_Zoom(frmbuf_info,  0, Interaction_mode);
+            Update_LCD_Display(frmbuf_info);
+            memcpy(FASTR_RENDER, (uint8_t*)Board_jpg_File, ROTRNDR_SIZE);
+            while (1) {
+                /* Get coordinates */
+                touch_num = GetCoordinates(touch_pos);
+                if (touch_num != 0) {
+                	func_code_t func_code;
+
+                	func_code = Scan_Key(return_key_tbl, touch_pos[0].x, touch_pos[0].y);
+                    if (func_code == RGA_FUNC_RETURN) {
+                        break;
+                    }
+
+                    if(!touch_pos[0].touch_down && (func_code == RGA_FUNC_AUTO_MANUAL))
+                    	Interaction_mode = (Interaction_mode == AUTO_INTERACT)? MANUAL_INTERACT : AUTO_INTERACT;
+                    else
+                    	work_height_pos = ZOOM_MAX_NUM * ((float32_t)touch_pos[0].x / (float32_t)(LCD_PIXEL_WIDTH));
+                }
+                if(Interaction_mode == AUTO_INTERACT)
+                {
+                	xz= (xz >= LCD_PIXEL_WIDTH)? 0: (xz+1);
+                	work_height_pos = ZOOM_MAX_NUM * ((float32_t)xz / (float32_t)(LCD_PIXEL_WIDTH));
+				}
+                /* Draw screen */
+                Swap_FrameBuffer(frmbuf_info);
+                RGA_Func_Zo(frmbuf_info,  work_height_pos, Interaction_mode, (graphics_image_t*)FASTR_RENDER);
+                Update_LCD_Display(frmbuf_info);
+            }
+            break;
+        case RGA_FUNC_ROTATION:
+            graphics_matrix_float_t work_angle = 0;
+            uint16_t xr = LCD_PIXEL_WIDTH;
+
+            RGA_Func_Rotation(frmbuf_info, 0, Interaction_mode);
+            Swap_FrameBuffer(frmbuf_info);
+            RGA_Func_Rotation(frmbuf_info, 0, Interaction_mode);
+            Update_LCD_Display(frmbuf_info);
+            memcpy(FASTR_RENDER, (uint8_t*)Board_jpg_File, ROTRNDR_SIZE);
+            while (1) {
+                /* Get coordinates */
+                touch_num = GetCoordinates(touch_pos);
+                if (touch_num != 0) {
+                	func_code_t func_code;
+
+                	func_code = Scan_Key(return_key_tbl, touch_pos[0].x, touch_pos[0].y);
+                    if (func_code == RGA_FUNC_RETURN) {
+                        break;
+                    }
+
+                    if(!touch_pos[0].touch_down && (func_code == RGA_FUNC_AUTO_MANUAL))
+                    	Interaction_mode = (Interaction_mode == AUTO_INTERACT)? MANUAL_INTERACT : AUTO_INTERACT;
+                    else
+                    	work_angle = ROTATION_MAX_NUM * ((float32_t)touch_pos[0].x / (float32_t)(LCD_PIXEL_WIDTH));
+                }
+                if(Interaction_mode == AUTO_INTERACT)
+                {
+                	xr= (xr >= LCD_PIXEL_WIDTH)? 0: (xr+1);
+                	work_angle = ROTATION_MAX_NUM * ((float32_t)xr / (float32_t)(LCD_PIXEL_WIDTH));
+                }
+                /* Draw screen */
+                Swap_FrameBuffer(frmbuf_info);
+                RGA_Func_Rotor(frmbuf_info, work_angle, Interaction_mode, (graphics_image_t*)FASTR_RENDER);
+                Update_LCD_Display(frmbuf_info);
+            }
+            break;
+        case RGA_FUNC_ACCELERATE:
+            int acce_frame_num = 0;
+            int animation_timing = 0;
+            float32_t work_relative_pos;
+
+            RGA_Func_Accelerate(frmbuf_info, 0, 0);
+            Swap_FrameBuffer(frmbuf_info);
+            RGA_Func_Accelerate(frmbuf_info, 0, 0);
+            Update_LCD_Display(frmbuf_info);
+            memcpy(FASTR_RENDER, (uint8_t*)Board_jpg_File, ROTRNDR_SIZE);
+            while (1) {
+                /* Get coordinates */
+                touch_num = GetCoordinates(touch_pos);
+                if (touch_num != 0) {
+                    func_code_t func_code;
+
+                    func_code = Scan_Key(animetion_timing_key_tbl, touch_pos[0].x, touch_pos[0].y);
+                    if (func_code == RGA_FUNC_RETURN) {
+                        break;
+                    }
+                    switch (func_code) {
+                        case RGA_FUNC_ANIME_EASE:
+                            animation_timing = 0;
+                            acce_frame_num = 0;
+                            break;
+                        case RGA_FUNC_ANIME_LINEAR:
+                            animation_timing = 1;
+                            acce_frame_num = 0;
+                            break;
+                        case RGA_FUNC_ANIME_EASE_IN:
+                            animation_timing = 2;
+                            acce_frame_num = 0;
+                            break;
+                        case RGA_FUNC_ANIME_EASE_OUT:
+                            animation_timing = 3;
+                            acce_frame_num = 0;
+                            break;
+                        case RGA_FUNC_ANIME_EASE_IN_OUT:
+                            animation_timing = 4;
+                            acce_frame_num = 0;
+                            break;
+                        default:
+                            /* Do Nothing */
+                            break;
+                    }
+                }
+                work_relative_pos = acce_frame_num / (float32_t)ACCELERATE_MAX_NUM;
+                acce_frame_num++;
+                if (acce_frame_num > ACCELERATE_MAX_NUM) {
+                    acce_frame_num = 0;
+                }
+                /* Draw screen */
+                Swap_FrameBuffer(frmbuf_info);
+                RGA_Func_Axel(frmbuf_info, animation_timing, work_relative_pos, (graphics_image_t*)FASTR_RENDER);
+                Update_LCD_Display(frmbuf_info);
+            }
+            break;
+
+        case RGA_FUNC_VIDEO:
+        	static bool old_signal;
+
+        	if(video_signal)
+        	{	/* Video write process start */
+        		if (Display.Video_Start(DisplayBase::VIDEO_INPUT_CHANNEL_0) != DisplayBase::GRAPHICS_OK) {
+        			printf("Line %d, error %d\n", __LINE__, error);
+        			mbed_die();
+        		}
+        	}
+        	else
+        	{
+        		frmbuf_info->buffer_address[frmbuf_info->draw_buffer_index] = user_video_buffer;
+        		RGA_Func_DrawFullScreen(frmbuf_info, TstScrn_jpg_File);
+        		frmbuf_info->buffer_address[frmbuf_info->draw_buffer_index] = (frmbuf_info->draw_buffer_index)? user_frame_buffer2 : user_frame_buffer1;
+        	}
+
+        	old_signal = video_signal;
+        	slide_screen = DisplayBase::SLIDE_OUT_BOTTOM;
+        	while(slide_screen !=DisplayBase::SLIDE_NONE);
+        	frmbuf_info->buffer_address[frmbuf_info->draw_buffer_index] = user_video_buffer;
+
+            while (1) {
+                /* Get coordinates */
+                touch_num = GetCoordinates(touch_pos);
+                if (touch_num != 0) {
+                    if (Scan_Key(video_screen_key_tbl, touch_pos[0].x, touch_pos[0].y) == RGA_FUNC_RETURN) {
+                    	if(video_signal)
+                    	{
+                    		if (Display.Video_Stop(DisplayBase::VIDEO_INPUT_CHANNEL_0) != DisplayBase::GRAPHICS_OK) {
+                    			printf("Line %d, error %d\n", __LINE__, error);
+                    			mbed_die();
+                    		}
+                    	}
+                    	frmbuf_info->buffer_address[frmbuf_info->draw_buffer_index] = (frmbuf_info->draw_buffer_index)? user_frame_buffer2 : user_frame_buffer1;
+                    	slide_screen = DisplayBase::SLIDE_IN_BOTTOM;
+                        break;
+                    }
+                }
+
+                if(video_signal ^ old_signal)
+                {
+                	if(video_signal)
+                	{
+                		if (Display.Video_Start(DisplayBase::VIDEO_INPUT_CHANNEL_0) != DisplayBase::GRAPHICS_OK) {
+                		     printf("Line %d, error %d\n", __LINE__, error);
+                		     mbed_die();
+                		}
+                	}
+                	else
+                	{
+                		if (Display.Video_Stop(DisplayBase::VIDEO_INPUT_CHANNEL_0) != DisplayBase::GRAPHICS_OK) {
+                			printf("Line %d, error %d\n", __LINE__, error);
+                		    mbed_die();
+                		}
+                		Wait_Vsync(3);
+                		RGA_Func_DrawFullScreen(frmbuf_info, TstScrn_jpg_File);
+                	}
+                	old_signal = video_signal;
+                }
+            }
+            break;
+
+        case RGA_FUNC_USBCAM:
+        	static int swaped_idx;
+        	static bool old_usbplug;
+        	static int try_recognize;
+        	int shot_size;
+
+        	try_recognize = 0;
+        	swaped_idx = frmbuf_info->draw_buffer_index;
+        	frmbuf_info->buffer_address[(swaped_idx)? 0 : 1] = user_video_buffer;
+        	frmbuf_info->buffer_address[swaped_idx] = (swaped_idx)? user_frame_buffer1 : user_frame_buffer2;
+
+        	RGA_Func_DrawFullScreen(frmbuf_info, CamScrn_jpg_File);
+        	if(!Cam.connected())
+        		RGA_Func_DrawPNG(frmbuf_info, NoDevice_png_ARGB4444, NO_DEV_X, NO_DEV_Y);
+        	Swap_FrameBuffer(frmbuf_info);
+        	RGA_Func_DrawFullScreen(frmbuf_info, CamScrn_jpg_File);
+        	if(!Cam.connected())
+        	    RGA_Func_DrawPNG(frmbuf_info, NoDevice_png_ARGB4444, NO_DEV_X, NO_DEV_Y);
+        	Swap_FrameBuffer(frmbuf_info);
+
+        	frmbuf_info->buffer_address[swaped_idx] = (swaped_idx)? user_frame_buffer2 : user_frame_buffer1;
+        	old_usbplug = usb_plug;
+        	slide_screen = DisplayBase::SLIDE_OUT_LEFT;
+        	while(slide_screen !=DisplayBase::SLIDE_NONE);
+        	frmbuf_info->buffer_address[swaped_idx] = (swaped_idx)? user_frame_buffer1 : user_frame_buffer2;
+
+        	if(Cam.connected())
+        	{
+        		RGA_Func_DrawFullScreen(frmbuf_info, NULL);
+        		Swap_FrameBuffer(frmbuf_info);
+        		RGA_Func_DrawFullScreen(frmbuf_info, NULL);
+        	}
+
+
+#ifdef __SOFT_JPEG__
+            // decompression with libJPEG
+            //1:	Allocate and initialize a JPEG decompression object
+            //2:	Specify the source of the compressed data (eg, a file)
+            //3:	Call jpeg_read_header() to obtain image info
+            //4:	Set parameters for decompression
+            //5:	jpeg_start_decompress(...);
+            //6:	while (scan lines remain to be read)
+            //			jpeg_read_scanlines(...);
+            //7:	jpeg_finish_decompress(...);
+            //8:	Release the JPEG decompression object
+
+            struct jpeg_decompress_struct cinfo;
+            struct my_error_mgr jerr;
+            JSAMPARRAY buffer;	/* Output row buffer */
+            int row_stride;		/* physical row width in output buffer */
+            //...
+            cinfo.err = jpeg_std_error(&jerr.pub);  /* We set up the normal JPEG error routines  */
+            jerr.pub.error_exit = my_error_exit;	/* then override error_exit. */
+
+            /* Establish the setjmp return context for my_error_exit to use. */
+              if (setjmp(jerr.setjmp_buffer)) {
+                /* If we get here, the JPEG code has signaled an error.
+                 * We need to clean up the JPEG object, close the input file, and return.
+                 */
+                jpeg_destroy_decompress(&cinfo);
+              }
+
+            //1:
+            jpeg_create_decompress(&cinfo);
+#endif
+
+            while (1) {
+                /* Get coordinates */
+                touch_num = GetCoordinates(touch_pos);
+                if (touch_num != 0) {
+                   if (Scan_Key(cam_screen_key_tbl, touch_pos[0].x, touch_pos[0].y) == RGA_FUNC_RETURN) {
+                	   frmbuf_info->buffer_address[frmbuf_info->draw_buffer_index] = user_video_buffer;
+                	   Update_VIDEO_Display(frmbuf_info);
+                	   frmbuf_info->buffer_address[0] = user_frame_buffer1;
+                	   frmbuf_info->buffer_address[1] = user_frame_buffer2;
+                	   slide_screen = DisplayBase::SLIDE_IN_LEFT;
+                       break;
+                   }
+                }
+
+                if(Cam.connected())
+                {
+                	shot_size = Cam.readJPEG(shot_buffer, sizeof(shot_buffer));
+                	//printf("JPEG size: %d\r\n", shot_size);
+                	//test_point = !test_point;
+
+                	Swap_FrameBuffer(frmbuf_info);
+
+#ifdef __SOFT_JPEG__
+                	//2:
+                	jpeg_mem_src(&cinfo, shot_buffer ,shot_size);
+
+					//3:
+                	jpeg_read_header(&cinfo, TRUE);
+                	//4:
+                	// Default decompression parameters
+                	//5:
+                	jpeg_start_decompress(&cinfo);
+
+                	//6:
+                	row_stride = cinfo.output_width * cinfo.output_components;
+                	buffer = (*cinfo.mem->alloc_sarray)	((j_common_ptr) &cinfo, JPOOL_IMAGE, row_stride, 1);
+                	while (cinfo.output_scanline < cinfo.output_height) {
+                		jpeg_read_scanlines(&cinfo, buffer, 1);
+
+                		for(int i=0; i<cinfo.output_width; i++)
+                		{
+                			uint16_t _565;
+
+                			_565  = (uint16_t)(0xF8 & buffer[0][(i*3)+2])>>3;
+                			_565 |= (uint16_t)(0xFC & buffer[0][(i*3)+1])<<3;
+                			_565 |= (uint16_t)(0xF8 & buffer[0][i*3])<<8;
+
+                			((uint16_t*)(frmbuf_info->buffer_address[frmbuf_info->draw_buffer_index]))[((cinfo.output_scanline-1)*LCD_PIXEL_WIDTH)+i] = _565;
+                		}
+                    }
+                	//7:
+                	jpeg_finish_decompress(&cinfo);
+
+                	RGA_Func_DrawCamScreen(NULL);
+#else
+                	RGA_Func_DrawCamScreen(shot_buffer);
+#endif
+
+                	Update_VIDEO_Display(frmbuf_info);
+
+                	Cam.poll();
+                }
+
+                if(usb_plug ^ old_usbplug)
+                {
+                	if(usb_plug)
+                    {
+                		//Swap_FrameBuffer(frmbuf_info);
+                		//RGA_Func_DrawFullScreen(frmbuf_info, CamScrn_jpg_File);
+                		//Update_VIDEO_Display(frmbuf_info);
+                    }
+                    else
+                    {
+                    	Swap_FrameBuffer(frmbuf_info);
+                    	RGA_Func_DrawFullScreen(frmbuf_info, CamScrn_jpg_File);
+                    	RGA_Func_DrawPNG(frmbuf_info, NoDevice_png_ARGB4444, NO_DEV_X, NO_DEV_Y);
+                    	Update_VIDEO_Display(frmbuf_info);
+                    }
+                    old_usbplug = usb_plug;
+                }
+
+                if(try_cam_connect)
+                {
+                	if(!Cam.connected())
+                	{
+                		Cam.connect();
+                		Thread::wait(500);
+                		if(try_recognize == 0)
+                		{
+                			Swap_FrameBuffer(frmbuf_info);
+                			RGA_Func_DrawFullScreen(frmbuf_info, CamScrn_jpg_File);
+                			Update_VIDEO_Display(frmbuf_info);
+                		}
+
+                		try_recognize++;
+                		if(try_recognize > MAX_TRY)
+                		{
+                			try_cam_connect = false;
+                			Swap_FrameBuffer(frmbuf_info);
+                			RGA_Func_DrawFullScreen(frmbuf_info, CamScrn_jpg_File);
+                			RGA_Func_DrawPNG(frmbuf_info, NoDevice_png_ARGB4444, NO_DEV_X, NO_DEV_Y);
+                			Update_VIDEO_Display(frmbuf_info);
+                		}
+                	}
+                	else
+                	{
+                		try_cam_connect = false;
+                		RGA_Func_DrawFullScreen(frmbuf_info, NULL);
+                		Swap_FrameBuffer(frmbuf_info);
+                		RGA_Func_DrawFullScreen(frmbuf_info, NULL);
+                		Swap_FrameBuffer(frmbuf_info);
+                	}
+                }
+                else
+                	try_recognize = 0;
+            }
+
+#ifdef __SOFT_JPEG__
+            //8:
+            jpeg_destroy_decompress(&cinfo);
+#endif
+            break;
+
+        default :
+            /* Do nothing */
+            break;
+    }
+}
+
+
+//void test(int x)
+//{
+//	test_point=x;
+//}
+
+int main(void) {
+    func_code_t func_code;
+    uint8_t touch_num = 0;
+    touch_pos_t touch_pos[TOUCH_NUM];
+
+    /* Initialization of LCD */
+    Init_LCD_Display();    /* When using LCD, please call before than Init_Video(). */
+
+    /* Initialization of Video */
+    Init_Video();
+
+    /* Start of Video ch0 */
+    Start_Video(
+    	DisplayBase::VIDEO_INPUT_CHANNEL_0,   /* Video input channe */
+        user_video_buffer,                    /* Output buffer */
+        0,                                    /* The x coordinate of the upper-left corner */
+        0,                                    /* The y coordinate of the upper-left corner */
+        LCD_PIXEL_WIDTH,                	  /* width  (A multiple of 16) */
+        LCD_PIXEL_HEIGHT                      /* height (A multiple of 8) */
+    );
+
+    memset(user_frame_buffer1, 0, sizeof(user_frame_buffer1));
+    memset(user_frame_buffer2, 0, sizeof(user_frame_buffer2));
+    frame_buffer_info.buffer_address[0] = user_frame_buffer1;
+    frame_buffer_info.buffer_address[1] = user_frame_buffer2;
+    frame_buffer_info.buffer_count      = 2;
+    frame_buffer_info.show_buffer_index = 0;
+    frame_buffer_info.draw_buffer_index = 0;
+    frame_buffer_info.width             = LCD_PIXEL_WIDTH;
+    frame_buffer_info.byte_per_pixel    = FRAME_BUFFER_BYTE_PER_PIXEL;
+    frame_buffer_info.stride            = LCD_PIXEL_WIDTH * FRAME_BUFFER_BYTE_PER_PIXEL;
+    frame_buffer_info.height            = LCD_PIXEL_HEIGHT;
+    frame_buffer_info.pixel_format      = PIXEL_FORMAT_RGB565;
+
+    /* Display Top Screen */
+    Set_RGAObject(&frame_buffer_info);
+    RGA_Func_DrawFullScreen(&frame_buffer_info, TopScrn_jpg_File);
+
+    Swap_FrameBuffer(&frame_buffer_info);
+    RGA_Func_DrawFullScreen(&frame_buffer_info, TopScrn_jpg_File);
+    Swap_FrameBuffer(&frame_buffer_info);
+
+    /* Start of LCD */
+    Start_LCD_Display(frame_buffer_info.buffer_address[0]);
+
+    /* Backlight on */
+    Thread::wait(200);
+    lcd_cntrst.period_us(100);
+    lcd_cntrst.write(((float)LCD_CH0_INITIAL_DC)/100.0f); //
+
+    /* Reset touch IC */
+    STMPE811.Init();
+
+    Interaction_mode = MANUAL_INTERACT;
+
+    while (1) {
+        /* Get Coordinates */
+        touch_num = GetCoordinates(touch_pos);
+        if (touch_num != 0) {
+            func_code = Scan_Key(top_screen_key_tbl, touch_pos[0].x, touch_pos[0].y);
+            if (func_code != RGA_FUNC_NON) {
+                /* Wait key off */
+                while (1) {
+                    touch_num = GetCoordinates(touch_pos);
+                    if (touch_num == 0) {
+                        break;
+                    }
+                    Thread::wait(20);
+                }
+
+                /* Execute RGA functions */
+                Exe_RGA_Func(func_code, &frame_buffer_info);
+
+                /* Return Top Screen */
+                touch_num = 0;
+                touch_num = (RGA_Func_CheckPorts(&frame_buffer_info, false, false))? 1 : 0;
+                touch_num = (RGA_Func_CheckPorts(&frame_buffer_info, video_signal, usb_plug))? 1 : 0;
+                if(touch_num == 0)
+                {
+                	Swap_FrameBuffer(&frame_buffer_info);
+                	RGA_Func_DrawFullScreen(&frame_buffer_info, TopScrn_jpg_File);
+                }
+                Update_LCD_Display(&frame_buffer_info);
+            }
+        }
+        else
+        	if(RGA_Func_CheckPorts(&frame_buffer_info, video_signal, usb_plug))
+        		Update_LCD_Display(&frame_buffer_info);
+        Thread::wait(20);
+    }
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/rga_func.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1193 @@
+/*
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*/
+
+#include "mbed.h"
+#include "rga_func.h"
+#include "Images/BinaryImage_RZ_A1H.h"
+
+#define ZOOM_SRC_CENTER_X                   (IMAGE_WIDTH_ZOOM_FUNC / 2)
+#define ZOOM_SRC_CENTER_Y                   (IMAGE_HEIGHT_ZOOM_FUNC / 2)
+
+Canvas2D_ContextClass canvas2d;
+
+static animation_timing_function_t* accelerator;
+
+void Set_RGAObject(frame_buffer_t* frmbuf_info) {
+    errnum_t err;
+    Canvas2D_ContextConfigClass config;
+
+    config.frame_buffer = frmbuf_info;
+    canvas2d = R_RGA_New_Canvas2D_ContextClass(config);
+    err = R_OSPL_GetErrNum();
+    if (err != 0) {
+        printf("Line %d, error %d\n", __LINE__, err);
+        while (1);
+    }
+}
+
+void RGA_Func_DrawFullScreen(frame_buffer_t* frmbuf_info, const graphics_image_t* image) {
+
+    /* Draw a image */
+    if(image)
+    	canvas2d.drawImage(image, 0, 0);
+    else
+    {
+    	/* Clear */
+    	canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+    	//canvas2d.fillStyle = "#000000";
+    	//canvas2d.fillRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+    }
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_DrawPNG(frame_buffer_t* frmbuf_info, const graphics_image_t* png_img, int x, int y) {
+    /* Clear */
+    //canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw a image */
+	if (frmbuf_info->pixel_format == PIXEL_FORMAT_RGB565)
+		canvas2d.drawImage(png_img, x, y);  //png_ARGB4444 assumed
+	//else
+	//    canvas2d.drawImage(png_img, x, y);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_DrawCamScreen(uint8_t* cam_buffer) {
+    /* Clear */
+	//if(cam_buffer)
+    //canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw a image */
+	if(cam_buffer)
+		canvas2d.drawImage((graphics_image_t*)cam_buffer, 0, 0);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+#if (LCD_VDC5_CH0_PANEL == LCD_CH0_PANEL_VKLCD70RT)
+
+void RGA_Func_DrawRectangle(frame_buffer_t* frmbuf_info, draw_rectangle_pos_t * pos, int pos_num) {
+    int cnt;
+
+    /* Clear */
+    canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw description */
+    canvas2d.drawImage(decs_swipe_jpg_File, 294, 530);
+
+    /* Draw rectangle */
+    for (cnt = 0; cnt < pos_num; cnt++) {
+        canvas2d.fillStyle = pos->style;
+        canvas2d.fillRect(pos->x, pos->y, pos->w, pos->h);
+        pos++;
+    }
+
+    /* Draw return button */
+    canvas2d.drawImage(RetBtn_jpg_File, 792, 6);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_DrawImage(frame_buffer_t* frmbuf_info, int x, int y) {
+    int draw_pos_x = x - (CRYSTAL_DIAMETER / 2);
+    int draw_pos_y = y - (CRYSTAL_DIAMETER / 2);
+
+    /* Clear */
+    canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw description */
+    canvas2d.drawImage(decs_board_jpg_File, 170, 55);
+    canvas2d.drawImage(decs_swipe_jpg_File, 294, 530);
+
+    /* Draw the first image */
+    canvas2d.drawImage(Board_jpg_File, 106, 140);
+
+    /* Draw the second image */
+    if ((frmbuf_info->pixel_format == PIXEL_FORMAT_ARGB8888) || (frmbuf_info->pixel_format == PIXEL_FORMAT_XRGB8888)) {
+        canvas2d.drawImage(Crystal_png_ARGB8888, draw_pos_x, draw_pos_y);
+    } else if (frmbuf_info->pixel_format != PIXEL_FORMAT_YUV422) {
+        canvas2d.drawImage(Crystal_png_ARGB4444, draw_pos_x, draw_pos_y);
+    } else {
+        canvas2d.drawImage(Crystal_png_File, draw_pos_x, draw_pos_y);
+    }
+
+    /* Draw return button */
+    canvas2d.drawImage(RetBtn_jpg_File, 792, 6);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Dissolve(frame_buffer_t* frmbuf_info, float32_t global_alpha, interact_t mode) {
+	/* Dissolve = Fade Out + Fade In */
+	/* Clear */
+	canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+	/* Draw description */
+	canvas2d.drawImage(decs_board_jpg_File, 170, 55);
+	if(mode == AUTO_INTERACT)
+	{
+	  	canvas2d.drawImage(ManualBtn_jpg_File, 848, 230);
+	    canvas2d.drawImage(decs_wait_jpg_File, 405, 530);
+	}
+	else
+	{
+	  	canvas2d.drawImage(AutoBtn_jpg_File, 848, 230);
+	  	canvas2d.drawImage(decs_swipe_side_jpg_File, 180, 530);
+	}
+
+	/* fade Out */
+	canvas2d.globalAlpha = 1.0f - global_alpha;
+	canvas2d.drawImage(Board_jpg_File, 106, 140);
+
+	/* fade In */
+	canvas2d.globalAlpha = global_alpha;
+	canvas2d.fillStyle = "#FFFFFF";
+	canvas2d.fillRect(106, 140, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+	canvas2d.globalAlpha = 1.0f;
+
+	/* Draw return button */
+	canvas2d.drawImage(RetBtn_jpg_File, 792, 6);
+
+	/* Complete drawing */
+	R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+
+}
+
+void RGA_Func_Diss(frame_buffer_t* frmbuf_info, float32_t global_alpha, interact_t mode, graphics_image_t* image) {
+    /* Dissolve = Fade Out + Fade In */
+	static int prv_mode = mode;
+	static int crsr = 0;
+
+	if(!crsr)
+		if(prv_mode != mode)
+		{
+			prv_mode = mode;
+			crsr = 2;
+		}
+
+	if(crsr)
+	{
+		canvas2d.clearRect(0, 530, frmbuf_info->width, 44);
+		if(mode == AUTO_INTERACT)
+		{
+			canvas2d.drawImage(ManualBtn_jpg_File, 848, 230);
+			canvas2d.drawImage(decs_wait_jpg_File, 405, 530);
+		}
+		else
+		{
+			canvas2d.drawImage(AutoBtn_jpg_File, 848, 230);
+			canvas2d.drawImage(decs_swipe_side_jpg_File, 180, 530);
+		}
+
+		crsr--;
+	}
+
+    /* fade Out */
+    canvas2d.globalAlpha = 1.0f - global_alpha;
+    canvas2d.drawImage(image, 106, 140);
+
+    /* fade In */
+    canvas2d.globalAlpha = global_alpha;
+    canvas2d.fillStyle = "#FFFFFF";
+    canvas2d.fillRect(106, 140, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+    canvas2d.globalAlpha = 1.0f;
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Scroll(frame_buffer_t* frmbuf_info, int src_width_pos,  interact_t mode) {
+	/* Clear */
+	canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+	/* Draw description */
+	canvas2d.drawImage(decs_board_jpg_File, 170, 55);
+	if(mode == AUTO_INTERACT)
+	{
+		canvas2d.drawImage(ManualBtn_jpg_File, 848, 230);
+		canvas2d.drawImage(decs_wait_jpg_File, 405, 530);
+	}
+	else
+	{
+		canvas2d.drawImage(AutoBtn_jpg_File, 848, 230);
+		canvas2d.drawImage(decs_swipe_side_jpg_File, 180, 530);
+	}
+
+	/* Scroll from left to right */
+	canvas2d.drawImage(Board_wide_jpg_File,
+	                     /* src */       src_width_pos, 0, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT,
+	                     /* dst */       106, 140, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+	/* Draw return button */
+	canvas2d.drawImage(RetBtn_jpg_File, 792, 6);
+
+	/* Complete drawing */
+	R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Scr(frame_buffer_t* frmbuf_info, int src_width_pos, interact_t mode, graphics_image_t* image) {
+	static int prv_mode = mode;
+	static int crsr = 0;
+
+	if(!crsr)
+		if(prv_mode != mode)
+		{
+			prv_mode = mode;
+			crsr = 2;
+		}
+
+	if(crsr)
+	{
+		canvas2d.clearRect(0, 530, frmbuf_info->width, 44);
+		if(mode == AUTO_INTERACT)
+		{
+			canvas2d.drawImage(ManualBtn_jpg_File, 848, 230);
+			canvas2d.drawImage(decs_wait_jpg_File, 405, 530);
+		}
+		else
+		{
+			canvas2d.drawImage(AutoBtn_jpg_File, 848, 230);
+			canvas2d.drawImage(decs_swipe_side_jpg_File, 180, 530);
+		}
+		crsr--;
+	}
+
+	/* Scroll from left to right */
+    canvas2d.drawImage(image,
+                        /* src */       src_width_pos, 0, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT,
+                        /* dst */       106, 140, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Zoom(frame_buffer_t* frmbuf_info, int src_height_pos, interact_t mode) {
+	/* Clear */
+	canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+	/* Draw description */
+	canvas2d.drawImage(decs_board_jpg_File, 170, 55);
+	if(mode == AUTO_INTERACT)
+	{
+		canvas2d.drawImage(ManualBtn_jpg_File, 848, 230);
+		canvas2d.drawImage(decs_wait_jpg_File, 405, 530);
+	}
+	else
+	{
+		canvas2d.drawImage(AutoBtn_jpg_File, 848, 230);
+		canvas2d.drawImage(decs_swipe_side_jpg_File, 180, 530);
+	}
+
+	/* Zoom out */
+	canvas2d.drawImage(Board_jpg_File,
+	                   /* src X */     ZOOM_SRC_CENTER_X - (src_height_pos * IMG_DRAW_WIDTH / IMG_DRAW_HEIGHT),
+	                   /* src Y */     ZOOM_SRC_CENTER_Y - src_height_pos,
+	                   /* src W */     src_height_pos * 2 * IMG_DRAW_WIDTH / IMG_DRAW_HEIGHT,
+	                   /* src H */     src_height_pos * 2,
+	                   /* dst   */     106, 140, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+	/* Draw return button */
+	canvas2d.drawImage(RetBtn_jpg_File, 792, 6);
+
+	/* Complete drawing */
+	R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+
+void RGA_Func_Zo(frame_buffer_t* frmbuf_info, int src_height_pos, interact_t mode, graphics_image_t* image) {
+	static int prv_mode = mode;
+	static int crsr = 0;
+
+	if(!crsr)
+	if(prv_mode != mode)
+	{
+		prv_mode = mode;
+		crsr = 2;
+	}
+
+	if(crsr)
+	{
+		canvas2d.clearRect(0, 530, frmbuf_info->width, 44);
+		if(mode == AUTO_INTERACT)
+		{
+			canvas2d.drawImage(ManualBtn_jpg_File, 848, 230);
+			canvas2d.drawImage(decs_wait_jpg_File, 405, 530);
+		}
+		else
+		{
+			canvas2d.drawImage(AutoBtn_jpg_File, 848, 230);
+			canvas2d.drawImage(decs_swipe_side_jpg_File, 180, 530);
+		}
+		crsr--;
+	}
+
+    /* Zoom out */
+    canvas2d.drawImage(image,
+                        /* src X */     ZOOM_SRC_CENTER_X - (src_height_pos * IMG_DRAW_WIDTH / IMG_DRAW_HEIGHT),
+                        /* src Y */     ZOOM_SRC_CENTER_Y - src_height_pos,
+                        /* src W */     src_height_pos * 2 * IMG_DRAW_WIDTH / IMG_DRAW_HEIGHT,
+                        /* src H */     src_height_pos * 2,
+                        /* dst   */     106, 140, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Rotation(frame_buffer_t* frmbuf_info, graphics_matrix_float_t image_angle, interact_t mode) {
+	/* Rotate the image to the right */
+	/* Clear */
+	canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+	/* Draw description */
+	canvas2d.drawImage(decs_board_jpg_File, 650, 143);
+	if(mode == AUTO_INTERACT)
+	{
+		canvas2d.drawImage(ManualBtn_jpg_File, 848, 230);
+	    canvas2d.drawImage(decs_wait_jpg_File, 704, 530);
+	}
+	else
+	{
+		canvas2d.drawImage(AutoBtn_jpg_File, 848, 230);
+	   	canvas2d.drawImage(decs_swipe_side_jpg_File,   0, 0, 238, 42, 704, 397, 238, 42);
+	   	canvas2d.drawImage(decs_swipe_side_jpg_File, 241, 0, 198, 42, 714, 463, 198, 42);
+	   	canvas2d.drawImage(decs_swipe_side_jpg_File, 439, 0, 234, 42, 693, 530, 234, 42);
+	}
+
+	/* Move to drawing position */
+	canvas2d.translate((100 + (IMG_DRAW_WIDTH / 2)), (140 + (IMG_DRAW_HEIGHT / 2)));
+
+	/* Rotate */
+	canvas2d.rotate(image_angle * (3.14159 / 180));
+
+	/* Move to center to rotate */
+	canvas2d.translate((-IMG_DRAW_WIDTH / 2), (-IMG_DRAW_HEIGHT / 2));
+	canvas2d.drawImage(Board_jpg_File, 0, 0);
+	canvas2d.setTransform(1, 0, 0, 1, 0, 0);
+
+	/* Draw return button */
+	canvas2d.drawImage(RetBtn_jpg_File, 792, 6);
+
+	/* Complete drawing */
+	R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Rotor(frame_buffer_t* frmbuf_info, graphics_matrix_float_t image_angle, interact_t mode, graphics_image_t* image) {
+	/* Rotate the image to the right */
+	static int prv_mode = mode;
+	static int crsr = 0;
+
+	if(!crsr)
+		if(prv_mode != mode)
+		{
+			prv_mode = mode;
+			crsr = 2;
+		}
+
+	if(crsr)
+	{
+		if(mode == AUTO_INTERACT)
+		{
+			canvas2d.drawImage(ManualBtn_jpg_File, 848, 230);
+			canvas2d.clearRect(704, 397, 341, 198);
+			canvas2d.drawImage(decs_wait_jpg_File, 704, 530);
+		}
+		else
+		{
+			canvas2d.drawImage(AutoBtn_jpg_File, 848, 230);
+			canvas2d.drawImage(decs_swipe_side_jpg_File,   0, 0, 238, 42, 704, 397, 238, 42);
+			canvas2d.drawImage(decs_swipe_side_jpg_File, 241, 0, 198, 42, 714, 463, 198, 42);
+			canvas2d.drawImage(decs_swipe_side_jpg_File, 439, 0, 234, 42, 693, 530, 234, 42);
+		}
+		crsr--;
+	}
+
+    /* Clear [6ms] */
+    canvas2d.clearRect(0, 0, 90+(IMG_DRAW_WIDTH / 2)+(frmbuf_info->height / 2), frmbuf_info->height);
+
+    /* Move to drawing position [1ms]*/
+    canvas2d.translate((100 + (IMG_DRAW_WIDTH / 2)), (140 + (IMG_DRAW_HEIGHT / 2)));
+
+    /* Rotate [2ms]*/
+    canvas2d.rotate(image_angle * (3.14159 / 180));
+
+    /* Move to center to rotate [0,5 + 120 + 1ms]*/
+    canvas2d.translate((-IMG_DRAW_WIDTH / 2), (-IMG_DRAW_HEIGHT / 2));
+    canvas2d.drawImage(image, 0, 0);
+    canvas2d.setTransform(1, 0, 0, 1, 0, 0);
+
+    /* Complete drawing [4ms]*/
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Accelerate(frame_buffer_t* frmbuf_info, int animation_timing, float32_t relative_pos) {
+    /* Do accelerated motion from right to left */
+    int position;
+
+    /* Clear */
+    canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw description */
+    canvas2d.drawImage(decs_board_jpg_File, 170, 55);
+
+    if (relative_pos == 0.0f) {
+        switch (animation_timing) {
+            case ANIMATION_TIMING_EASE:
+                R_Get_AnimationTimingFunction("ease", &accelerator);
+                break;
+            case ANIMATION_TIMING_LINEAR:
+                R_Get_AnimationTimingFunction("linear", &accelerator);
+                break;
+            case ANIMATION_TIMING_EASE_IN:
+                R_Get_AnimationTimingFunction("ease-in", &accelerator);
+                break;
+            case ANIMATION_TIMING_EASE_OUT:
+                R_Get_AnimationTimingFunction("ease-out", &accelerator);
+                break;
+            case ANIMATION_TIMING_EASE_IN_OUT:
+            default:
+                R_Get_AnimationTimingFunction("ease-in-out", &accelerator);
+                break;
+        }
+    }
+
+    /* Draw rectangle */
+    canvas2d.fillStyle = "#0000FF";  /* blue */
+    switch (animation_timing) {
+        case ANIMATION_TIMING_EASE:
+            canvas2d.fillRect(21, 562, 173, 13);
+            break;
+        case ANIMATION_TIMING_LINEAR:
+            canvas2d.fillRect(220, 562, 173, 13);
+            break;
+        case ANIMATION_TIMING_EASE_IN:
+            canvas2d.fillRect(422, 562, 173, 13);
+            break;
+        case ANIMATION_TIMING_EASE_OUT:
+            canvas2d.fillRect(623, 562, 173, 13);
+            break;
+        case ANIMATION_TIMING_EASE_IN_OUT:
+        default:
+            canvas2d.fillRect(823, 562, 173, 13);
+            break;
+    }
+
+    /* Draw button */
+    canvas2d.drawImage(animetion_timing_jpg_File, 0, 496);
+
+    position = R_ANIMATION_TIMING_FUNCTION_GetValue(accelerator, relative_pos, 505.0f, 6.0f);
+    canvas2d.drawImage(Board_jpg_File, position, 140);
+
+    /* Draw return button */
+    canvas2d.drawImage(RetBtn_jpg_File, 792, 6);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Axel(frame_buffer_t* frmbuf_info, int animation_timing, float32_t relative_pos, graphics_image_t* image) {
+	/* Do accelerated motion from right to left */
+	    static int prv_timing = animation_timing;
+	    static int crsr = 0;
+		int position;
+
+	    /* Clear */
+	    canvas2d.clearRect(0, 140, frmbuf_info->width, IMG_DRAW_HEIGHT);
+
+	    if (relative_pos == 0.0f) {
+	        switch (animation_timing) {
+	            case ANIMATION_TIMING_EASE:
+	                R_Get_AnimationTimingFunction("ease", &accelerator);
+	                break;
+	            case ANIMATION_TIMING_LINEAR:
+	                R_Get_AnimationTimingFunction("linear", &accelerator);
+	                break;
+	            case ANIMATION_TIMING_EASE_IN:
+	                R_Get_AnimationTimingFunction("ease-in", &accelerator);
+	                break;
+	            case ANIMATION_TIMING_EASE_OUT:
+	                R_Get_AnimationTimingFunction("ease-out", &accelerator);
+	                break;
+	            case ANIMATION_TIMING_EASE_IN_OUT:
+	            default:
+	                R_Get_AnimationTimingFunction("ease-in-out", &accelerator);
+	                break;
+	        }
+	        if(prv_timing != animation_timing)
+	        {
+	        	prv_timing = animation_timing;
+	        	crsr = 2;
+	        }
+	    }
+
+	    /* Draw rectangle */
+	    canvas2d.fillStyle = "#0000FF";  /* blue */
+	    switch (animation_timing) {
+	        case ANIMATION_TIMING_EASE:
+	        	if(crsr)
+	        	{
+	        		canvas2d.clearRect(0, 563, frmbuf_info->width, 13);
+	        		canvas2d.fillRect(21, 563, 173, 13);
+	        	}
+	            break;
+	        case ANIMATION_TIMING_LINEAR:
+	        	if(crsr)
+	        	{
+	        		canvas2d.clearRect(0, 563, frmbuf_info->width, 13);
+	        		canvas2d.fillRect(220, 563, 173, 13);
+	        	}
+	            break;
+	        case ANIMATION_TIMING_EASE_IN:
+	        	if(crsr)
+	        	{
+	        		canvas2d.clearRect(0, 563, frmbuf_info->width, 13);
+	        		canvas2d.fillRect(422, 563, 173, 13);
+	        	}
+	        	break;
+	        case ANIMATION_TIMING_EASE_OUT:
+	            if(crsr)
+	            {
+	            	canvas2d.clearRect(0, 563, frmbuf_info->width, 13);
+	            	canvas2d.fillRect(623, 563, 173, 13);
+	            }
+	            break;
+	        case ANIMATION_TIMING_EASE_IN_OUT:
+	        default:
+	        	if(crsr)
+	        	{
+	        		canvas2d.clearRect(0, 563, frmbuf_info->width, 13);
+	        		canvas2d.fillRect(823, 563, 173, 13);
+	        	}
+	            break;
+	    }
+
+	    /* Draw button */
+	    if(crsr)
+	    {
+	    	canvas2d.drawImage(animetion_timing_jpg_File, 0, 496);
+    		crsr--;
+	    }
+
+	    position = R_ANIMATION_TIMING_FUNCTION_GetValue(accelerator, relative_pos, 505.0f, 6.0f);
+	    canvas2d.drawImage(image, position, 140);
+
+	    /* Complete drawing */
+	    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+bool RGA_Func_CheckPorts(frame_buffer_t* frmbuf_info, bool rca_pluged, bool usb_pluged) {
+	static bool rca_visible = false;
+	static bool usb_visible = false;
+	bool rca_changed = false;
+	bool usb_changed = false;
+
+	/* Detect Change in ports status */
+	if(rca_pluged ^ rca_visible)
+	{
+		rca_visible = rca_pluged;
+		rca_changed = true;
+	}
+
+	if(usb_pluged ^ usb_visible)
+	{
+		usb_visible = usb_pluged;
+		usb_changed = true;
+	}
+
+	if(rca_changed | usb_changed)
+	{
+		frmbuf_info->draw_buffer_index = (frmbuf_info->draw_buffer_index)? 0 : 1;
+
+		/* Draw a image Clear */
+		canvas2d.drawImage(TopScrn_jpg_File, 0, 0);
+
+		if(rca_visible)
+			canvas2d.drawImage(RCA_jpg_File, (frmbuf_info->width/2)-160, 50);
+
+		if(usb_visible)
+			canvas2d.drawImage(Usb_jpg_File, frmbuf_info->width-100, (frmbuf_info->height/2)-73);
+
+		/* Complete drawing */
+		R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+	}
+
+    return (rca_changed | usb_changed);
+}
+#else
+
+void RGA_Func_DrawRectangle(frame_buffer_t* frmbuf_info, draw_rectangle_pos_t * pos, int pos_num) {
+    int cnt;
+
+    /* Clear */
+    canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw description */
+    canvas2d.drawImage(decs_swipe_jpg_File, 138, 240);
+
+    /* Draw rectangle */
+    for (cnt = 0; cnt < pos_num; cnt++) {
+        canvas2d.fillStyle = pos->style;
+        canvas2d.fillRect(pos->x, pos->y, pos->w, pos->h);
+        pos++;
+    }
+
+    /* Draw return button */
+    canvas2d.drawImage(RetBtn_jpg_File, 368, 6);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_DrawImage(frame_buffer_t* frmbuf_info, int x, int y) {
+    int draw_pos_x = x - (CRYSTAL_DIAMETER / 2);
+    int draw_pos_y = y - (CRYSTAL_DIAMETER / 2);
+
+    /* Clear */
+    canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw description */
+    canvas2d.drawImage(decs_board_jpg_File, 80, 25);
+    canvas2d.drawImage(decs_swipe_jpg_File, 138, 240);
+
+    /* Draw the first image */
+    canvas2d.drawImage(Board_jpg_File, 50, 65);
+
+    /* Draw the second image */
+    if ((frmbuf_info->pixel_format == PIXEL_FORMAT_ARGB8888) || (frmbuf_info->pixel_format == PIXEL_FORMAT_XRGB8888)) {
+        canvas2d.drawImage(Crystal_png_ARGB8888, draw_pos_x, draw_pos_y);
+    } else if (frmbuf_info->pixel_format != PIXEL_FORMAT_YUV422) {
+        canvas2d.drawImage(Crystal_png_ARGB4444, draw_pos_x, draw_pos_y);
+    } else {
+        canvas2d.drawImage(Crystal_png_File, draw_pos_x, draw_pos_y);
+    }
+
+    /* Draw return button */
+    canvas2d.drawImage(RetBtn_jpg_File, 368, 6);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Dissolve(frame_buffer_t* frmbuf_info, float32_t global_alpha, interact_t mode) {
+    /* Dissolve = Fade Out + Fade In */
+    /* Clear */
+    canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw description */
+    canvas2d.drawImage(decs_board_jpg_File, 80, 25);
+    if(mode == AUTO_INTERACT)
+    {
+    	canvas2d.drawImage(ManualBtn_jpg_File, 398, 104);
+        canvas2d.drawImage(decs_wait_jpg_File, 190, 240);
+    }
+    else
+    {
+    	canvas2d.drawImage(AutoBtn_jpg_File, 398, 104);
+    	canvas2d.drawImage(decs_swipe_side_jpg_File, 84, 240);
+    }
+
+    /* fade Out */
+    canvas2d.globalAlpha = 1.0f - global_alpha;
+    canvas2d.drawImage(Board_jpg_File, 50, 65);
+
+    /* fade In */
+    canvas2d.globalAlpha = global_alpha;
+    canvas2d.fillStyle = "#FFFFFF";
+    canvas2d.fillRect(50, 65, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+    canvas2d.globalAlpha = 1.0f;
+
+    /* Draw return button */
+    canvas2d.drawImage(RetBtn_jpg_File, 368, 6);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Diss(frame_buffer_t* frmbuf_info, float32_t global_alpha, interact_t mode, graphics_image_t* image) {
+    /* Dissolve = Fade Out + Fade In */
+	static int prv_mode = mode;
+	static int crsr = 0;
+
+	if(!crsr)
+		if(prv_mode != mode)
+		{
+			prv_mode = mode;
+			crsr = 2;
+		}
+
+	if(crsr)
+	{
+		canvas2d.clearRect(0, 240, frmbuf_info->width, 20);
+		if(mode == AUTO_INTERACT)
+		{
+			canvas2d.drawImage(ManualBtn_jpg_File, 398, 104);
+			canvas2d.drawImage(decs_wait_jpg_File, 190, 240);
+		}
+		else
+		{
+			canvas2d.drawImage(AutoBtn_jpg_File, 398, 104);
+			canvas2d.drawImage(decs_swipe_side_jpg_File, 84, 240);
+		}
+
+		crsr--;
+	}
+
+    /* fade Out */
+    canvas2d.globalAlpha = 1.0f - global_alpha;
+    canvas2d.drawImage(image, 50, 65);
+
+    /* fade In */
+    canvas2d.globalAlpha = global_alpha;
+    canvas2d.fillStyle = "#FFFFFF";
+    canvas2d.fillRect(50, 65, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+    canvas2d.globalAlpha = 1.0f;
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Scroll(frame_buffer_t* frmbuf_info, int src_width_pos, interact_t mode) {
+    /* Clear */
+    canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw description */
+    canvas2d.drawImage(decs_board_jpg_File, 80, 25);
+    if(mode == AUTO_INTERACT)
+    {
+        canvas2d.drawImage(ManualBtn_jpg_File, 398, 104);
+        canvas2d.drawImage(decs_wait_jpg_File, 190, 240);
+    }
+    else
+    {
+       	canvas2d.drawImage(AutoBtn_jpg_File, 398, 104);
+       	canvas2d.drawImage(decs_swipe_side_jpg_File, 84, 240);
+    }
+
+    /* Scroll from left to right */
+    canvas2d.drawImage(Board_wide_jpg_File,
+                        /* src */       src_width_pos, 0, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT,
+                        /* dst */       50, 65, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+    /* Draw return button */
+    canvas2d.drawImage(RetBtn_jpg_File, 368, 6);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Scr(frame_buffer_t* frmbuf_info, int src_width_pos, interact_t mode, graphics_image_t* image) {
+	static int prv_mode = mode;
+	static int crsr = 0;
+
+	if(!crsr)
+		if(prv_mode != mode)
+		{
+			prv_mode = mode;
+			crsr = 2;
+		}
+
+	if(crsr)
+	{
+		canvas2d.clearRect(0, 240, frmbuf_info->width, 20);
+		if(mode == AUTO_INTERACT)
+		{
+			canvas2d.drawImage(ManualBtn_jpg_File, 398, 104);
+			canvas2d.drawImage(decs_wait_jpg_File, 190, 240);
+		}
+		else
+		{
+			canvas2d.drawImage(AutoBtn_jpg_File, 398, 104);
+			canvas2d.drawImage(decs_swipe_side_jpg_File, 84, 240);
+		}
+		crsr--;
+	}
+
+	/* Scroll from left to right */
+    canvas2d.drawImage(image,
+                        /* src */       src_width_pos, 0, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT,
+                        /* dst */       50, 65, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Zoom(frame_buffer_t* frmbuf_info, int src_height_pos, interact_t mode) {
+    /* Clear */
+    canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw description */
+    canvas2d.drawImage(decs_board_jpg_File, 80, 25);
+    if(mode == AUTO_INTERACT)
+    {
+        canvas2d.drawImage(ManualBtn_jpg_File, 398, 104);
+        canvas2d.drawImage(decs_wait_jpg_File, 190, 240);
+    }
+    else
+    {
+      	canvas2d.drawImage(AutoBtn_jpg_File, 398, 104);
+       	canvas2d.drawImage(decs_swipe_side_jpg_File, 84, 240);
+    }
+
+    /* Zoom out */
+    canvas2d.drawImage(Board_jpg_File,
+                        /* src X */     ZOOM_SRC_CENTER_X - (src_height_pos * IMG_DRAW_WIDTH / IMG_DRAW_HEIGHT),
+                        /* src Y */     ZOOM_SRC_CENTER_Y - src_height_pos,
+                        /* src W */     src_height_pos * 2 * IMG_DRAW_WIDTH / IMG_DRAW_HEIGHT,
+                        /* src H */     src_height_pos * 2,
+                        /* dst   */     50, 65, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+    /* Draw return button */
+    canvas2d.drawImage(RetBtn_jpg_File, 368, 6);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Zo(frame_buffer_t* frmbuf_info, int src_height_pos, interact_t mode, graphics_image_t* image) {
+	static int prv_mode = mode;
+	static int crsr = 0;
+
+	if(!crsr)
+	if(prv_mode != mode)
+	{
+		prv_mode = mode;
+		crsr = 2;
+	}
+
+	if(crsr)
+	{
+		canvas2d.clearRect(0, 240, frmbuf_info->width, 20);
+		if(mode == AUTO_INTERACT)
+		{
+			canvas2d.drawImage(ManualBtn_jpg_File, 398, 104);
+			canvas2d.drawImage(decs_wait_jpg_File, 190, 240);
+		}
+		else
+		{
+			canvas2d.drawImage(AutoBtn_jpg_File, 398, 104);
+			canvas2d.drawImage(decs_swipe_side_jpg_File, 84, 240);
+		}
+		crsr--;
+	}
+
+    /* Zoom out */
+    canvas2d.drawImage(image,
+                        /* src X */     ZOOM_SRC_CENTER_X - (src_height_pos * IMG_DRAW_WIDTH / IMG_DRAW_HEIGHT),
+                        /* src Y */     ZOOM_SRC_CENTER_Y - src_height_pos,
+                        /* src W */     src_height_pos * 2 * IMG_DRAW_WIDTH / IMG_DRAW_HEIGHT,
+                        /* src H */     src_height_pos * 2,
+                        /* dst   */     50, 65, IMG_DRAW_WIDTH, IMG_DRAW_HEIGHT);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Rotation(frame_buffer_t* frmbuf_info, graphics_matrix_float_t image_angle, interact_t mode) {
+    /* Rotate the image to the right */
+    /* Clear */
+    canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw description */
+    canvas2d.drawImage(decs_board_jpg_File, 305, 65);
+    if(mode == AUTO_INTERACT)
+    {
+    	canvas2d.drawImage(ManualBtn_jpg_File, 398, 104);
+    	canvas2d.drawImage(decs_wait_jpg_File, 330, 240);
+    }
+    else
+    {
+    	canvas2d.drawImage(AutoBtn_jpg_File, 398, 104);
+    	canvas2d.drawImage(decs_swipe_side_jpg_File,   0, 0, 112, 19, 330, 180, 112, 19);
+    	canvas2d.drawImage(decs_swipe_side_jpg_File, 113, 0, 93,  19, 335, 210,  93, 19);
+    	canvas2d.drawImage(decs_swipe_side_jpg_File, 206, 0, 110, 19, 325, 240, 110, 19);
+    }
+
+    /* Move to drawing position */
+    canvas2d.translate((50 + (IMG_DRAW_WIDTH / 2)), (65 + (IMG_DRAW_HEIGHT / 2)));
+
+    /* Rotate */
+    canvas2d.rotate(image_angle * (3.14159 / 180));
+
+    /* Move to center to rotate */
+    canvas2d.translate((-IMG_DRAW_WIDTH / 2), (-IMG_DRAW_HEIGHT / 2));
+    canvas2d.drawImage(Board_jpg_File, 0, 0);
+    canvas2d.setTransform(1, 0, 0, 1, 0, 0);
+
+    /* Draw return button */
+    canvas2d.drawImage(RetBtn_jpg_File, 368, 6);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Rotor(frame_buffer_t* frmbuf_info, graphics_matrix_float_t image_angle, interact_t mode, graphics_image_t* image) {
+	/* Rotate the image to the right */
+	static int prv_mode = mode;
+	static int crsr = 0;
+
+	if(!crsr)
+		if(prv_mode != mode)
+		{
+			prv_mode = mode;
+			crsr = 2;
+		}
+
+	if(crsr)
+	{
+		//canvas2d.clearRect(0, 240, frmbuf_info->width, 20);
+		if(mode == AUTO_INTERACT)
+		{
+			canvas2d.drawImage(ManualBtn_jpg_File, 398, 104);
+			canvas2d.clearRect(330, 180, 160, 90);
+			canvas2d.drawImage(decs_wait_jpg_File, 330, 240);
+		}
+		else
+		{
+			canvas2d.drawImage(AutoBtn_jpg_File, 398, 104);
+			canvas2d.drawImage(decs_swipe_side_jpg_File,   0, 0, 112, 19, 330, 180, 112, 19);
+			canvas2d.drawImage(decs_swipe_side_jpg_File, 113, 0, 93,  19, 335, 210,  93, 19);
+			canvas2d.drawImage(decs_swipe_side_jpg_File, 206, 0, 110, 19, 325, 240, 110, 19);
+		}
+		crsr--;
+	}
+
+    /* Clear [6ms] */
+    canvas2d.clearRect(0, 0, 50+(IMG_DRAW_WIDTH / 2)+(frmbuf_info->height / 2), frmbuf_info->height);
+
+    /* Move to drawing position [1ms]*/
+    canvas2d.translate((50 + (IMG_DRAW_WIDTH / 2)), (65 + (IMG_DRAW_HEIGHT / 2)));
+
+    /* Rotate [2ms]*/
+    canvas2d.rotate(image_angle * (3.14159 / 180));
+
+    /* Move to center to rotate [0,5 + 120 + 1ms]*/
+    canvas2d.translate((-IMG_DRAW_WIDTH / 2), (-IMG_DRAW_HEIGHT / 2));
+    canvas2d.drawImage(image, 0, 0);
+    canvas2d.setTransform(1, 0, 0, 1, 0, 0);
+
+    /* Complete drawing [4ms]*/
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Accelerate(frame_buffer_t* frmbuf_info, int animation_timing, float32_t relative_pos) {
+    /* Do accelerated motion from right to left */
+    int position;
+
+    /* Clear */
+    canvas2d.clearRect(0, 0, frmbuf_info->width, frmbuf_info->height);
+
+    /* Draw description */
+    canvas2d.drawImage(decs_board_jpg_File, 80, 25);
+
+    if (relative_pos == 0.0f) {
+        switch (animation_timing) {
+            case ANIMATION_TIMING_EASE:
+                R_Get_AnimationTimingFunction("ease", &accelerator);
+                break;
+            case ANIMATION_TIMING_LINEAR:
+                R_Get_AnimationTimingFunction("linear", &accelerator);
+                break;
+            case ANIMATION_TIMING_EASE_IN:
+                R_Get_AnimationTimingFunction("ease-in", &accelerator);
+                break;
+            case ANIMATION_TIMING_EASE_OUT:
+                R_Get_AnimationTimingFunction("ease-out", &accelerator);
+                break;
+            case ANIMATION_TIMING_EASE_IN_OUT:
+            default:
+                R_Get_AnimationTimingFunction("ease-in-out", &accelerator);
+                break;
+        }
+    }
+
+    /* Draw rectangle */
+    canvas2d.fillStyle = "#0000FF";  /* blue */
+    switch (animation_timing) {
+        case ANIMATION_TIMING_EASE:
+            canvas2d.fillRect(10, 255, 81, 6);
+            break;
+        case ANIMATION_TIMING_LINEAR:
+            canvas2d.fillRect(103, 255, 81, 6);
+            break;
+        case ANIMATION_TIMING_EASE_IN:
+            canvas2d.fillRect(198, 255, 81, 6);
+            break;
+        case ANIMATION_TIMING_EASE_OUT:
+            canvas2d.fillRect(292, 255, 81, 6);
+            break;
+        case ANIMATION_TIMING_EASE_IN_OUT:
+        default:
+            canvas2d.fillRect(386, 255, 81, 6);
+            break;
+    }
+
+    /* Draw button */
+    canvas2d.drawImage(animetion_timing_jpg_File, 0, 225);
+
+    position = R_ANIMATION_TIMING_FUNCTION_GetValue(accelerator, relative_pos, 240.0f, 6.0f);
+    canvas2d.drawImage(Board_jpg_File, position, 65);
+
+    /* Draw return button */
+    canvas2d.drawImage(RetBtn_jpg_File, 368, 6);
+
+    /* Complete drawing */
+    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+void RGA_Func_Axel(frame_buffer_t* frmbuf_info, int animation_timing, float32_t relative_pos, graphics_image_t* image) {
+	/* Do accelerated motion from right to left */
+	    static int prv_timing = animation_timing;
+	    static int crsr = 0;
+		int position;
+
+	    /* Clear */
+	    canvas2d.clearRect(0, 65, frmbuf_info->width, IMG_DRAW_HEIGHT);
+
+	    if (relative_pos == 0.0f) {
+	        switch (animation_timing) {
+	            case ANIMATION_TIMING_EASE:
+	                R_Get_AnimationTimingFunction("ease", &accelerator);
+	                break;
+	            case ANIMATION_TIMING_LINEAR:
+	                R_Get_AnimationTimingFunction("linear", &accelerator);
+	                break;
+	            case ANIMATION_TIMING_EASE_IN:
+	                R_Get_AnimationTimingFunction("ease-in", &accelerator);
+	                break;
+	            case ANIMATION_TIMING_EASE_OUT:
+	                R_Get_AnimationTimingFunction("ease-out", &accelerator);
+	                break;
+	            case ANIMATION_TIMING_EASE_IN_OUT:
+	            default:
+	                R_Get_AnimationTimingFunction("ease-in-out", &accelerator);
+	                break;
+	        }
+	        if(prv_timing != animation_timing)
+	        {
+	        	prv_timing = animation_timing;
+	        	crsr = 2;
+	        }
+	    }
+
+	    /* Draw rectangle */
+	    canvas2d.fillStyle = "#0000FF";  /* blue */
+	    switch (animation_timing) {
+	        case ANIMATION_TIMING_EASE:
+	        	if(crsr)
+	        	{
+	        		canvas2d.clearRect(0, 255, frmbuf_info->width, 6);
+	        		canvas2d.fillRect(10, 255, 81, 6);
+	        	}
+	            break;
+	        case ANIMATION_TIMING_LINEAR:
+	        	if(crsr)
+	        	{
+	        		canvas2d.clearRect(0, 255, frmbuf_info->width, 6);
+	        		canvas2d.fillRect(103, 255, 81, 6);
+	        	}
+	            break;
+	        case ANIMATION_TIMING_EASE_IN:
+	        	if(crsr)
+	        	{
+	        		canvas2d.clearRect(0, 255, frmbuf_info->width, 6);
+	        		canvas2d.fillRect(198, 255, 81, 6);
+	        	}
+	        	break;
+	        case ANIMATION_TIMING_EASE_OUT:
+	            if(crsr)
+	            {
+	            	canvas2d.clearRect(0, 255, frmbuf_info->width, 6);
+	            	canvas2d.fillRect(292, 255, 81, 6);
+	            }
+	            break;
+	        case ANIMATION_TIMING_EASE_IN_OUT:
+	        default:
+	        	if(crsr)
+	        	{
+	        		canvas2d.clearRect(0, 255, frmbuf_info->width, 6);
+	        		canvas2d.fillRect(386, 255, 81, 6);
+	        	}
+	            break;
+	    }
+
+	    /* Draw button */
+	    if(crsr)
+	    {
+	    	canvas2d.drawImage(animetion_timing_jpg_File, 0, 225);
+    		crsr--;
+	    }
+
+	    position = R_ANIMATION_TIMING_FUNCTION_GetValue(accelerator, relative_pos, 240.0f, 6.0f);
+	    canvas2d.drawImage(image, position, 65);
+
+	    /* Complete drawing */
+	    R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+}
+
+bool RGA_Func_CheckPorts(frame_buffer_t* frmbuf_info, bool rca_pluged, bool usb_pluged) {
+	static bool rca_visible = false;
+	static bool usb_visible = false;
+	bool rca_changed = false;
+	bool usb_changed = false;
+
+	/* Detect Change in ports status */
+	if(rca_pluged ^ rca_visible)
+	{
+		rca_visible = rca_pluged;
+		rca_changed = true;
+	}
+
+	if(usb_pluged ^ usb_visible)
+	{
+		usb_visible = usb_pluged;
+		usb_changed = true;
+	}
+
+	if(rca_changed | usb_changed)
+	{
+		frmbuf_info->draw_buffer_index = (frmbuf_info->draw_buffer_index)? 0 : 1;
+
+		/* Draw a image Clear */
+		canvas2d.drawImage(TopScrn_jpg_File, 0, 0);
+
+		if(rca_visible)
+			canvas2d.drawImage(RCA_jpg_File, (frmbuf_info->width/2)-80, 22);
+
+		if(usb_visible)
+			canvas2d.drawImage(Usb_jpg_File, frmbuf_info->width-50, (frmbuf_info->height/2)-36);
+
+		/* Complete drawing */
+		R_GRAPHICS_Finish(canvas2d.c_LanguageContext);
+	}
+
+    return (rca_changed | usb_changed);
+}
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/rga_func.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,96 @@
+/*
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+ 
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+ 
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+*/
+ 
+#ifndef RGA_FUNC_H
+#define RGA_FUNC_H
+
+#include "RGA.h"
+#include "lcd_panel.h"
+
+typedef struct {
+    char * style;
+    int x;
+    int y;
+    int w;
+    int h;
+} draw_rectangle_pos_t;
+
+typedef enum {
+	MANUAL_INTERACT,
+	AUTO_INTERACT
+}interact_t;
+
+#if (LCD_VDC5_CH0_PANEL == LCD_CH0_PANEL_VKLCD70RT)
+ #define IMG_DRAW_WIDTH                      (518)
+ #define IMG_DRAW_HEIGHT                     (322)
+ #define IMAGE_WIDTH_SCROLL_FUNC             (835)      // Image width of Scroll function
+ #define IMAGE_HEIGHT_SCROLL_FUNC            (322)      // Image height of Scroll function
+ #define IMAGE_WIDTH_ZOOM_FUNC               (518)      // Image width of Zoom function
+ #define IMAGE_HEIGHT_ZOOM_FUNC              (322)      // Image height of Zoom function
+ #define CRYSTAL_DIAMETER                    (119)
+ #define SLIDE_WIDTH                         (106)
+ #define NO_DEV_X							 (285)
+ #define NO_DEV_Y							 (75)
+#else
+ #define IMG_DRAW_WIDTH                      (235)
+ #define IMG_DRAW_HEIGHT                     (146)
+ #define IMAGE_WIDTH_SCROLL_FUNC             (379)      // Image width of Scroll function
+ #define IMAGE_HEIGHT_SCROLL_FUNC            (146)      // Image height of Scroll function
+ #define IMAGE_WIDTH_ZOOM_FUNC               (235)      // Image width of Zoom function
+ #define IMAGE_HEIGHT_ZOOM_FUNC              (146)      // Image height of Zoom function
+ #define CRYSTAL_DIAMETER                    (55)
+ #define SLIDE_WIDTH                         (50)
+ #define NO_DEV_X							 (128)
+ #define NO_DEV_Y 							 (24)
+#endif
+
+#define DISSOLVE_MAX_NUM                    (256)
+#define SCROLL_MAX_NUM                      (IMAGE_WIDTH_SCROLL_FUNC - IMG_DRAW_WIDTH)
+#define ZOOM_MAX_NUM                        (IMAGE_HEIGHT_ZOOM_FUNC / 2)
+#define ROTATION_MAX_NUM                    (360)
+#define ACCELERATE_MAX_NUM                  (256)
+
+#define ANIMATION_TIMING_EASE               (0)
+#define ANIMATION_TIMING_LINEAR             (1)
+#define ANIMATION_TIMING_EASE_IN            (2)
+#define ANIMATION_TIMING_EASE_OUT           (3)
+#define ANIMATION_TIMING_EASE_IN_OUT        (4)
+
+extern void Set_RGAObject(frame_buffer_t* frmbuf_info);
+extern void RGA_Func_DrawFullScreen(frame_buffer_t* frmbuf_info, const graphics_image_t *image);
+extern void RGA_Func_DrawRectangle(frame_buffer_t* frmbuf_info, draw_rectangle_pos_t * pos, int pos_num);
+extern void RGA_Func_DrawImage(frame_buffer_t* frmbuf_info, int x, int y);
+extern void RGA_Func_Dissolve(frame_buffer_t* frmbuf_info, float32_t global_alpha, interact_t mode);
+extern void RGA_Func_Scroll(frame_buffer_t* frmbuf_info, int src_width_pos, interact_t mode);
+extern void RGA_Func_Zoom(frame_buffer_t* frmbuf_info, int src_height_pos, interact_t mode);
+extern void RGA_Func_Rotation(frame_buffer_t* frmbuf_info, graphics_matrix_float_t image_angle, interact_t mode);
+extern void RGA_Func_Accelerate(frame_buffer_t* frmbuf_info, int animation_timing, float32_t relative_pos);
+extern void Rotor(frame_buffer_t* frmbuf_info, graphics_matrix_float_t image_angle);
+
+extern void RGA_Func_DrawCamScreen(uint8_t* cam_buffer);
+extern void RGA_Func_DrawPNG(frame_buffer_t* frmbuf_info, const graphics_image_t* png_img, int x, int y);
+extern bool RGA_Func_CheckPorts(frame_buffer_t* frmbuf_info, bool rca_pluged, bool usb_pluged);
+extern void RGA_Func_Rotor(frame_buffer_t* frmbuf_info, graphics_matrix_float_t image_angle, interact_t mode, graphics_image_t *image);
+extern void RGA_Func_Axel(frame_buffer_t* frmbuf_info, int animation_timing, float32_t relative_pos, graphics_image_t* image);
+extern void RGA_Func_Zo(frame_buffer_t* frmbuf_info, int src_height_pos, interact_t mode, graphics_image_t* image);
+extern void RGA_Func_Scr(frame_buffer_t* frmbuf_info, int src_width_pos, interact_t mode, graphics_image_t* image);
+extern void RGA_Func_Diss(frame_buffer_t* frmbuf_info, float32_t global_alpha, interact_t mode, graphics_image_t* image);
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/DisplayBace.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,553 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+ * @file         DisplayBase.h
+ * @brief        Display driver wrapper class for RGA
+******************************************************************************/
+
+#ifndef MBED_DISPLAYBASE_H
+#define MBED_DISPLAYBASE_H
+
+#include "pinmap.h"
+
+/*! @class DisplayBase
+ *  @brief Display driver wrapper class for RGA
+ */
+class DisplayBase
+{
+
+public:
+    /*! @enum video_input_channel_t
+        @brief Video input channel select
+     */
+    typedef enum {
+        VIDEO_INPUT_CHANNEL_0 = 0, /*!< Video input channel 0 */
+        VIDEO_INPUT_CHANNEL_1      /*!< Video input channel 1 */
+    } video_input_channel_t;
+
+    /*! @enum video_adc_vinsel_t
+        @brief Input pin control
+     */
+    typedef enum {
+        VIDEO_ADC_VINSEL_VIN1 = 0, /*!< VIN1 input            */
+        VIDEO_ADC_VINSEL_VIN2      /*!< VIN2 input            */
+    } video_adc_vinsel_t;
+
+    /*! @enum graphics_layer_t
+        @brief Graphics layer select
+     */
+    typedef enum {
+        GRAPHICS_LAYER_0 = 0,           /*!< Graphics layer 0         */
+        GRAPHICS_LAYER_1,               /*!< Graphics layer 1         */
+        GRAPHICS_LAYER_2,               /*!< Graphics layer 2         */
+        GRAPHICS_LAYER_3                /*!< Graphics layer 3         */
+    } graphics_layer_t;
+
+    /*! @enum graphics_error_t
+        @brief Error codes
+     */
+    typedef enum {
+        GRAPHICS_OK = 0,                   /*!< Normal termination       */
+        GRAPHICS_VDC5_ERR = -1,            /*!< VDC5 driver error        */
+        GRAPHICS_FORMA_ERR = -2,           /*!< Not support format       */
+        GRAPHICS_LAYER_ERR = -3,           /*!< Invalid layer ID error   */
+        GRAPHICS_CHANNLE_ERR = -4,         /*!< Invalid channel error */
+        GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /*!< Video write size(vw) error */
+        GRAPHICS_VIDEO_PAL_SIZE_ERR = -6,  /*!< Video Write size(vw) error */
+        GRAPHICS_PARAM_RANGE_ERR = -7      /*!< Parameter range error */
+    } graphics_error_t;
+
+    /*! @enum graphics_format_t
+        @brief Graphics layer read format selects
+    */
+    typedef enum {
+        GRAPHICS_FORMAT_YCBCR422 = 0,      /*!< YCbCr422 (2byte / px)  */
+        GRAPHICS_FORMAT_RGB565,            /*!< RGB565   (2byte / px)  */
+        GRAPHICS_FORMAT_RGB888,            /*!< RGB888   (4byte / px)  */
+        GRAPHICS_FORMAT_ARGB8888,          /*!< ARGB8888 (4byte / px)  */
+        GRAPHICS_FORMAT_ARGB4444           /*!< ARGB4444 (2byte / px)  */
+    } graphics_format_t;
+
+    /*! @enum video_format_t
+        @brief Video writing format selects
+     */
+    typedef enum {
+        VIDEO_FORMAT_YCBCR422 = 0,      /*!< YCbCr422 (2byte / px)    */
+        VIDEO_FORMAT_RGB565,            /*!< RGB565   (2byte / px)    */
+        VIDEO_FORMAT_RGB888             /*!< RGB888   (4byte / px)    */
+    } video_format_t;
+
+    /*! @enum wr_rd_swa_t
+        @brief Frame buffer swap setting
+     */
+    typedef enum {
+        WR_RD_WRSWA_NON = 0,           /*!< Not swapped: 1-2-3-4-5-6-7-8 */
+        WR_RD_WRSWA_8BIT,              /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+        WR_RD_WRSWA_16BIT,             /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+        WR_RD_WRSWA_16_8BIT,           /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+        WR_RD_WRSWA_32BIT,             /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+        WR_RD_WRSWA_32_8BIT,           /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+        WR_RD_WRSWA_32_16BIT,          /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+        WR_RD_WRSWA_32_16_8BIT,        /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+    } wr_rd_swa_t;
+
+    /*! @enum lcd_tcon_pin_t
+        @brief LCD tcon output pin selects
+     */
+    typedef enum {
+        LCD_TCON_PIN_NON = -1,          /*!< Not using output         */
+        LCD_TCON_PIN_0,                 /*!< LCD_TCON0                */
+        LCD_TCON_PIN_1,                 /*!< LCD_TCON1                */
+        LCD_TCON_PIN_2,                 /*!< LCD_TCON2                */
+        LCD_TCON_PIN_3,                 /*!< LCD_TCON3                */
+        LCD_TCON_PIN_4,                 /*!< LCD_TCON4                */
+    } lcd_tcon_pin_t;
+
+    /*! @enum lcd_outformat_t
+        @brief LCD output format selects
+     */
+    typedef enum {
+        LCD_OUTFORMAT_RGB888 = 0,       /*!< RGB888 or LVDS           */
+        LCD_OUTFORMAT_RGB666,           /*!< RGB666                   */
+        LCD_OUTFORMAT_RGB565            /*!< RGB565                   */
+    } lcd_outformat_t;
+
+    /*! @enum edge_t
+        @brief Edge of a signal
+     */
+    typedef enum {
+        EDGE_RISING    = 0,             /*!< Rising edge              */
+        EDGE_FALLING   = 1              /*!< Falling edge             */
+    } edge_t;
+
+    /*! @enum lcd_type_t
+        @brief LCD type
+     */
+    typedef enum {
+        LCD_TYPE_LVDS = 0,              /*!< LVDS control                */
+        LCD_TYPE_PARALLEL_RGB           /*!< RGB parallel signal control */
+    } lcd_type_t;
+
+    /*! @enum sig_pol_t
+        @brief Polarity of a signal
+     */
+    typedef enum {
+        SIG_POL_NOT_INVERTED = 0,       /*!< Not inverted             */
+        SIG_POL_INVERTED                /*!< Inverted                 */
+    } sig_pol_t;
+
+    /*! @enum int_type_t
+        @brief Interrupt type
+     */
+    typedef enum {
+        INT_TYPE_S0_VI_VSYNC = 0,      /*!< Vsync signal input to scaler 0 */
+        INT_TYPE_S0_LO_VSYNC,          /*!< Vsync signal output from scaler 0 */
+        INT_TYPE_S0_VSYNCERR,          /*!< Missing Vsync signal for scaler 0 */
+        INT_TYPE_VLINE,                /*!< Specified line signal for panel output in graphics 3 */
+        INT_TYPE_S0_VFIELD,            /*!< Field end signal for recording function in scaler 0 */
+        INT_TYPE_IV1_VBUFERR,          /*!< Frame buffer write overflow signal for scaler 0 */
+        INT_TYPE_IV3_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 0 */
+        INT_TYPE_IV5_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 2 */
+        INT_TYPE_IV6_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 3 */
+        INT_TYPE_S0_WLINE,             /*!< Write specification line signal input to scaling-down control block in scaler 0 */
+        INT_TYPE_S1_VI_VSYNC,          /*!< Vsync signal input to scaler 1 */
+        INT_TYPE_S1_LO_VSYNC,          /*!< Vsync signal output from scaler 1 */
+        INT_TYPE_S1_VSYNCERR,          /*!< Missing Vsync signal for scaler 1 */
+        INT_TYPE_S1_VFIELD,            /*!< Field end signal for recording function in scaler 1 */
+        INT_TYPE_IV2_VBUFERR,          /*!< Frame buffer write overflow signal for scaler 1 */
+        INT_TYPE_IV4_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 1 */
+        INT_TYPE_S1_WLINE,             /*!< Write specification line signal input to scaling-down control block in scaler 1 */
+        INT_TYPE_OIR_VI_VSYNC,         /*!< Vsync signal input to output image generator */
+        INT_TYPE_OIR_LO_VSYNC,         /*!< Vsync signal output from output image generator */
+        INT_TYPE_OIR_VLINE,            /*!< Specified line signal for panel output in output image generator */
+        INT_TYPE_OIR_VFIELD,           /*!< Field end signal for recording function in output image generator */
+        INT_TYPE_IV7_VBUFERR,          /*!< Frame buffer write overflow signal for output image generator */
+        INT_TYPE_IV8_VBUFERR,          /*!< Frame buffer read underflow signal for graphics (OIR) */
+        INT_TYPE_NUM                   /*!< The number of VDC5 interrupt types */
+    } int_type_t;
+
+    /*! @enum graphics_video_col_sys_t
+        @brief Video color system
+     */
+    typedef enum {
+        COL_SYS_NTSC_358       = 0,        /*!< NTSC-3.58 */
+        COL_SYS_NTSC_443       = 1,        /*!< NTSC-4.43 */
+        COL_SYS_PAL_443        = 2,        /*!< PAL-4.43 */
+        COL_SYS_PAL_M          = 3,        /*!< PAL-M */
+        COL_SYS_PAL_N          = 4,        /*!< PAL-N */
+        COL_SYS_SECAM          = 5,        /*!< SECAM */
+        COL_SYS_NTSC_443_60    = 6,        /*!< NTSC-4.43 (60Hz) */
+        COL_SYS_PAL_60         = 7,        /*!< PAL-60 */
+    } graphics_video_col_sys_t;
+
+    /*! @enum video_input_sel_t
+        @brief External Input select
+     */
+    typedef enum {
+        INPUT_SEL_VDEC     = 0,            /*!< Video decoder output signals */
+        INPUT_SEL_EXT      = 1             /*!< Signals supplied via the external input pins */
+    } video_input_sel_t;
+
+    /*! @enum video_extin_format_t
+       @brief External input format select
+    */
+    typedef enum {
+        VIDEO_EXTIN_FORMAT_RGB888 = 0,   /*!< RGB888 Not support */
+        VIDEO_EXTIN_FORMAT_RGB666,       /*!< RGB666 */
+        VIDEO_EXTIN_FORMAT_RGB565,       /*!< RGB565 */
+        VIDEO_EXTIN_FORMAT_BT656,        /*!< BT6556 */
+        VIDEO_EXTIN_FORMAT_BT601,        /*!< BT6501 */
+        VIDEO_EXTIN_FORMAT_YCBCR422,     /*!< YCbCr422 */
+        VIDEO_EXTIN_FORMAT_YCBCR444,     /*!< YCbCr444 Not support */
+    } video_extin_format_t;
+
+    /*! @enum onoff_t
+        @brief On/off
+     */
+    typedef enum {
+        OFF    = 0,            /*!< Off */
+        ON     = 1             /*!< On */
+    } onoff_t;
+
+    /*! @enum extin_input_line_t
+        @brief Number of lines for BT.656 external input
+     */
+    typedef enum {
+        EXTIN_LINE_525     = 0,    /*!< 525 lines */
+        EXTIN_LINE_625     = 1     /*!< 625 lines */
+    } extin_input_line_t;
+
+    /*! @enum extin_h_pos_t
+        @brief Y/Cb/Y/Cr data string start timing
+     */
+    typedef enum {
+        EXTIN_H_POS_CBYCRY = 0,    /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+        EXTIN_H_POS_YCRYCB,        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+        EXTIN_H_POS_CRYCBY,        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+        EXTIN_H_POS_YCBYCR,        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+        EXTIN_H_POS_NUM
+    } extin_h_pos_t;
+
+    typedef enum
+    {
+        SLIDE_OUT_RIGHT = 0,	/*!<	-->		*/
+        SLIDE_IN_RIGHT,			/*!<	<--		*/
+        SLIDE_OUT_BOTTOM,		/*!<	\/		*/
+        SLIDE_IN_BOTTOM,		/*!<	/\		*/
+        SLIDE_OUT_LEFT,			/*!<	<--		*/
+        SLIDE_IN_LEFT,			/*!<	-->		*/
+        SLIDE_OUT_TOP,			/*!<	\/		*/
+        SLIDE_IN_TOP,			/*!<	/\		*/
+    	SLIDE_NONE,				/*!<	.		*/
+    } slide_t;
+
+    /*! @struct rect_t
+        @brief The relative position within the graphics display area
+     */
+    typedef struct {
+        unsigned short vs;          /*!< Vertical start pos       */
+        unsigned short vw;          /*!< Vertical width (height)  */
+        unsigned short hs;          /*!< Horizontal start pos     */
+        unsigned short hw;          /*!< Horizontal width         */
+    } rect_t;
+
+    /*! @struct lcd_config_t
+        @brief LCD configuration
+     */
+    typedef struct {
+        lcd_type_t      lcd_type;               /*!< LVDS or Pararel RGB                      */
+        double          intputClock;            /*!< P1  clk [MHz] ex. 66.67f                 */
+        double          outputClock;            /*!< LCD clk [MHz] ex. 33.33f                 */
+
+        lcd_outformat_t lcd_outformat;          /*!< Output format select */
+        edge_t          lcd_edge;               /*!< Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+        unsigned short  h_toatal_period;        /*!< Free-running Hsync period                */
+        unsigned short  v_toatal_period;        /*!< Free-running Vsync period                */
+        unsigned short  h_disp_widht;           /*!< LCD display area size, horizontal width  */
+        unsigned short  v_disp_widht;           /*!< LCD display area size, vertical width    */
+        unsigned short  h_back_porch;           /*!< LCD display horizontal back porch period */
+        unsigned short  v_back_porch;           /*!< LCD display vertical back porch period   */
+
+        lcd_tcon_pin_t  h_sync_port;            /*!< TCONn or Not use(-1)                     */
+        sig_pol_t       h_sync_port_polarity;   /*!< Polarity inversion control of signal     */
+        unsigned short  h_sync_width;           /*!< Hsync width                              */
+
+        lcd_tcon_pin_t  v_sync_port;            /*!< TCONn or Not use(-1)                     */
+        sig_pol_t       v_sync_port_polarity;   /*!< Polarity inversion control of signal     */
+        unsigned short  v_sync_width;           /*!< Vsync width  */
+
+        lcd_tcon_pin_t  de_port;                /*!< TCONn or Not use(-1)                     */
+        sig_pol_t       de_port_polarity;       /*!< Polarity inversion control of signal     */
+    } lcd_config_t;
+
+    /*! @struct video_ext_in_config_t
+        @brief Digital Video Input configuration
+     */
+    typedef struct {
+        video_extin_format_t     inp_format;    /*!< External Input Format Select                                */
+        edge_t                   inp_pxd_edge;  /*!< Clock Edge Select for Capturing External Input Video Image  */
+        edge_t                   inp_vs_edge;   /*!< Clock Edge Select for Capturing External Input Vsync Signal */
+        edge_t                   inp_hs_edge;   /*!< Clock Edge Select for Capturing External Input Hsync Signal */
+        onoff_t                  inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control               */
+        onoff_t                  inp_swap_on;   /*!< External Input Bit Endian Change On/Off Control             */
+        sig_pol_t                inp_vs_inv;    /*!< External Input Vsync Signal DV_VSYNC Inversion Control      */
+        sig_pol_t                inp_hs_inv;    /*!< External Input Hsync Signal DV_HSYNC Inversion Control      */
+        extin_input_line_t       inp_f525_625;  /*!< Number of lines for BT.656 external input */
+        extin_h_pos_t            inp_h_pos;     /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
+        unsigned short           cap_vs_pos;    /*!< Capture start position from Vsync */
+        unsigned short           cap_hs_pos;    /*!< Capture start position form Hsync */
+        unsigned short           cap_width;     /*!< Capture width  */
+        unsigned short           cap_height;    /*!< Capture height should be a multiple of 4.*/
+    } video_ext_in_config_t;
+
+    /** Constructor method of display base object
+     */
+    DisplayBase( void );
+
+    /** Graphics initialization processing<br>
+     *  If not using display, set NULL in parameter.
+     *  @param[in]    lcd_config          : LCD configuration
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_init( lcd_config_t * lcd_config );
+
+    /** Graphics Video initialization processing<br>
+     *  If setting INPUT_SEL_VDEC in video_input_sel parameter, set NULL in video_ext_in_config parameter.
+     *  @param[in]    video_input_sel     : Input select
+     *  @param[in]    video_ext_in_config : Video configuration
+     *  @retval       error code
+     */
+    graphics_error_t Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config );
+
+    /** LCD output port initialization processing
+     *  @param[in]    pin                 : Pin assign for LCD output
+     *  @param[in]    pin_count           : Total number of pin assign
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count );
+
+    /** LVDS output port initialization processing
+     *  @param[in]    pin                 : Pin assign for LVDS output
+     *  @param[in]    pin_count           : Total number of pin assign
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count );
+
+    /** Digital video input port initialization processing
+     *  @param[in]    pin                 : Pin assign for digital video input port
+     *  @param[in]    pin_count           : Total number of pin assign
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count );
+
+    /**  Interrupt callback setup
+     *  This function performs the following processing:
+     *  - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.<br>
+     *  - Registers the specified interrupt callback function.<br>
+     *  - Disables the interrupt when the pointer to the corresponding interrupt callback function is not specified.<br>
+     *  @param[in]    Graphics_Irq_Handler_Set : VDC5 interrupt type
+     *  @param[in]    num                      : Interrupt line number
+     *  @param[in]    callback                 : Interrupt callback function pointer
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Irq_Handler_Set( int_type_t Graphics_Irq_Handler_Set, unsigned short num, void (* callback)(int_type_t)  );
+
+    /** Start the graphics surface read process
+     *  @param[in]    layer_id            : Graphics layer ID <br />
+     *      - GRAPHICS_LAYER_0 : Layer 0
+     *      - GRAPHICS_LAYER_1 : Layer 1
+     *      - GRAPHICS_LAYER_2 : Layer 2
+     *      - GRAPHICS_LAYER_3 : Layer 3
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Start( graphics_layer_t layer_id );
+
+    /** Stop the graphics surface read process
+     *  @param[in]    layer_id            : Graphics layer ID <br />
+     *      - GRAPHICS_LAYER_0 : Layer 0
+     *      - GRAPHICS_LAYER_1 : Layer 1
+     *      - GRAPHICS_LAYER_2 : Layer 2
+     *      - GRAPHICS_LAYER_3 : Layer 3
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Stop( graphics_layer_t layer_id );
+
+    /** Start the video surface write process
+     *  @param[in]    video_input_channel : Video input channel <br />
+     *      - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+     *      - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+     *  @retval       Error code
+     */
+    graphics_error_t Video_Start ( video_input_channel_t video_input_channel );
+
+    /** Stop the video surface write process
+     *  @param[in]    video_input_channel : Video input channel <br />
+     *      - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+     *      - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+     *  @retval       Error code
+     */
+    graphics_error_t Video_Stop ( video_input_channel_t video_input_channel );
+
+    /** Graphics surface read process setting
+     *  @param[in]    layer_id            : Graphics layer ID <br />
+     *      - GRAPHICS_LAYER_0 : Layer 0
+     *      - GRAPHICS_LAYER_1 : Layer 1
+     *      - GRAPHICS_LAYER_2 : Layer 2
+     *      - GRAPHICS_LAYER_3 : Layer 3
+     *  @param[in]    framebuff           : Base address of the frame buffer(Not set NULL)
+     *  @param[in]    fb_stride           : Line offset address of the frame buffer[byte]  <br />
+     *      Frame buffer stride should be set to a multiple of 32 or 128
+     *      in accordance with the frame buffer burst transfer mode.
+     *  @param[in]    gr_format           : Format of the frame buffer read signal <br />
+     *      - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
+     *      - VIDEO_FORMAT_RGB565   : RGB565 (2byte/px)
+     *      - VIDEO_FORMAT_RGB888   : RGB888 (4byte/px)
+     *      - VIDEO_FORMAT_ARGB8888 : ARGB8888 (4byte/px)
+     *  @param[in]    wr_rd_swa : frame buffer swap setting <br />
+     *      -    WR_RD_WRSWA_NON        : Not swapped: 1-2-3-4-5-6-7-8
+     *      -    WR_RD_WRSWA_8BIT       : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+     *      -    WR_RD_WRSWA_16BIT      : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+     *      -    WR_RD_WRSWA_16_8BIT    : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+     *      -    WR_RD_WRSWA_32BIT      : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+     *      -    WR_RD_WRSWA_32_8BIT    : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+     *      -    WR_RD_WRSWA_32_16BIT   : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+     *      -    WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+     *  @param[in]    gr_rect             : Graphics display area
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Read_Setting (
+        graphics_layer_t    layer_id,
+        void              * framebuff,
+        unsigned int        fb_stride,
+        graphics_format_t   gr_format,
+        wr_rd_swa_t         wr_rd_swa,
+        rect_t            * gr_rect );
+
+    /** Graphics surface read buffer change process
+     *  @param[in]    layer_id            : Graphics layer ID <br />
+     *      - GRAPHICS_LAYER_0 : Layer 0
+     *      - GRAPHICS_LAYER_1 : Layer 1
+     *      - GRAPHICS_LAYER_2 : Layer 2
+     *      - GRAPHICS_LAYER_3 : Layer 3
+     *  @param[in]    framebuff           : Base address of the frame buffer(Not set NULL)
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Read_Change (
+        graphics_layer_t    layer_id,
+        void             *  framebuff);
+
+    /** Graphics surface read buffer change process
+     *  @param[in]    layer_id            : Graphics layer ID <br />
+     *      - GRAPHICS_LAYER_0 : Layer 0
+     *      - GRAPHICS_LAYER_1 : Layer 1
+     *      - GRAPHICS_LAYER_2 : Layer 2
+     *      - GRAPHICS_LAYER_3 : Layer 3
+     *  @param[in]    framebuff           : Base address of the frame buffer(Not set NULL)
+     *  @param[in]    fb_stride           : stride of the framebuff
+     *  @param[in]    slide_dir           : slide direction
+     *  @retval       Error code
+     */
+    graphics_error_t Graphics_Read_Change_More (
+        graphics_layer_t    layer_id,
+        void             *  framebuff,
+		unsigned int        fb_stride,
+		slide_t			 *  slide_dir);
+
+    /** Video surface write process setting
+     *  @param[in]    video_input_channel : Video input channel <br />
+     *                If using digital input, this parameter is not referenced. <br />
+     *      - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+     *      - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+     *  @param[in]    col_sys             : Analog video signal color system <br />
+     *                If using digital input, this parameter is not referenced. <br />
+     *      - COL_SYS_NTSC_358    : NTSC-3.58
+     *      - COL_SYS_NTSC_443    : NTSC-4.43
+     *      - COL_SYS_PAL_443     : PAL-4.43
+     *      - COL_SYS_PAL_M       : PAL-M
+     *      - COL_SYS_PAL_N       : PAL-N
+     *      - COL_SYS_SECAM       : SECAM
+     *      - COL_SYS_NTSC_443_60 : NTSC-4.43 (60Hz)
+     *      - COL_SYS_PAL_60      : PAL-60
+     *  @param[in]    framebuff           : Base address of the frame buffer(Not set NULL)
+     *  @param[in]    fb_stride           : Line offset address of the frame buffer[byte]  <br />
+     *      Frame buffer stride should be set to a multiple of 32 or 128
+     *      in accordance with the frame buffer burst transfer mode.
+     *  @param[in]    video_format        : Frame buffer video-signal writing format <br />
+     *      - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
+     *      - VIDEO_FORMAT_RGB565   : RGB565 (2byte/px)
+     *      - VIDEO_FORMAT_RGB888   : RGB888 (4byte/px)
+     *  @param[in]    wr_rd_swa : frame buffer swap setting  <br />
+     *      -    WR_RD_WRSWA_NON        : Not swapped: 1-2-3-4-5-6-7-8
+     *      -    WR_RD_WRSWA_8BIT       : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+     *      -    WR_RD_WRSWA_16BIT      : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+     *      -    WR_RD_WRSWA_16_8BIT    : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+     *      -    WR_RD_WRSWA_32BIT      : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+     *      -    WR_RD_WRSWA_32_8BIT    : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+     *      -    WR_RD_WRSWA_32_16BIT   : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+     *      -    WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+     *  @param[in]    video_write_buff_vw : Output height[px] <br />
+     *      - NTSC format : Max height is 480[px]
+     *      - PAL format  : Max height is 520[px]
+     *  @param[in]    video_write_buff_hw : Output width[px] <br />
+     *      - Max width : 800[px]
+     *  @param[in]    video_adc_vinsel : Input pin control <br />
+     *      - VIDEO_ADC_VINSEL_VIN1 : VIN1 input
+     *      - VIDEO_ADC_VINSEL_VIN2 : VIN2 input
+     *  @retval       Error code
+     */
+    graphics_error_t Video_Write_Setting (
+        video_input_channel_t       video_input_channel,
+        graphics_video_col_sys_t    col_sys,
+        void                      * framebuff,
+        unsigned int                fb_stride,
+        video_format_t              video_format,
+        wr_rd_swa_t                 wr_rd_swa,
+        unsigned short              video_write_buff_vw,
+        unsigned short              video_write_buff_hw,
+        video_adc_vinsel_t          video_adc_vinsel = VIDEO_ADC_VINSEL_VIN1 );
+
+    /** Video surface write buffer change process
+     *  @param[in]    video_input_channel : Video input channel <br />
+     *      - VIDEO_INPUT_CHANNEL_0 : Video channel 0
+     *      - VIDEO_INPUT_CHANNEL_1 : Video channel 1
+     *  @param[in]    framebuff           : Base address of the frame buffer(Not set NULL)
+     *  @param[in]    fb_stride           : Line offset address of the frame buffer <br />
+     *      Frame buffer stride should be set to a multiple of 32 or 128
+     *      in accordance with the frame buffer burst transfer mode.
+     *  @retval       Error code
+     */
+    graphics_error_t Video_Write_Change (
+        video_input_channel_t    video_input_channel,
+        void                   * framebuff,
+        uint32_t                 fb_stride );
+
+protected:
+    lcd_config_t          _lcd_config;
+    video_input_sel_t     _video_input_sel;
+    video_ext_in_config_t _video_ext_in_config;
+};
+
+
+#endif /* MBED_DISPLAYBASE_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/DisplayBase.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,465 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+#include <string.h>
+#include "DisplayBace.h"
+#include "vdc5.h"
+
+/**************************************************************************//**
+ * @brief       Constructor of the DisplayBase class
+ * @param[in]   None
+ * @retval      None
+******************************************************************************/
+DisplayBase::DisplayBase( void )
+{
+    /* Lcd setting (default) */
+    _lcd_config.lcd_type             = LCD_TYPE_PARALLEL_RGB;       /* LVDS or Pararel RGB                      */
+    _lcd_config.intputClock          = 66.67f;                      /* P1  clk [MHz] ex. 66.67                  */
+    _lcd_config.outputClock          = 40.00f;                      /* LCD clk [MHz] ex. 33.33                  */
+
+    _lcd_config.lcd_outformat        = LCD_OUTFORMAT_RGB888;        /* Output format select */
+    _lcd_config.lcd_edge             = EDGE_FALLING;                /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+    _lcd_config.h_toatal_period      = (800u + 40u + 128u+ 88u);    /* Free-running Hsync period                */
+    _lcd_config.v_toatal_period      = (600u + 1u + 4u + 23u);      /* Free-running Vsync period                */
+    _lcd_config.h_disp_widht         = 800u;                        /* LCD display area size, horizontal width  */
+    _lcd_config.v_disp_widht         = 600u;                        /* LCD display area size, vertical width    */
+    _lcd_config.h_back_porch         = (128u+ 88u);                 /* LCD display horizontal back porch period */
+    _lcd_config.v_back_porch         = (4u + 23u);                  /* LCD display vertical back porch period   */
+
+    _lcd_config.h_sync_port          = LCD_TCON_PIN_0;              /* TCONn or Not use(-1)                     */
+    _lcd_config.h_sync_port_polarity = SIG_POL_NOT_INVERTED;        /* Polarity inversion control of signal     */
+    _lcd_config.h_sync_width         = 128u;                        /* Hsync width                              */
+
+    _lcd_config.v_sync_port          = LCD_TCON_PIN_1;              /* TCONn or Not use(-1)                     */
+    _lcd_config.v_sync_port_polarity = SIG_POL_NOT_INVERTED;        /* Polarity inversion control of signal     */
+    _lcd_config.v_sync_width         = 4u;                          /* Vsync width                              */
+
+    _lcd_config.de_port              = LCD_TCON_PIN_NON;            /* TCONn or Not use(-1)                     */
+    _lcd_config.de_port_polarity     = SIG_POL_NOT_INVERTED;        /* Polarity inversion control of signal     */
+
+    /* Digital video input setting (default) */
+    _video_input_sel                    = INPUT_SEL_VDEC;           /* Video decoder output signals */
+    _video_ext_in_config.inp_format     = VIDEO_EXTIN_FORMAT_BT601;
+    _video_ext_in_config.inp_pxd_edge   = EDGE_RISING;              /* Clock edge select for capturing data          */
+    _video_ext_in_config.inp_vs_edge    = EDGE_RISING;              /* Clock edge select for capturing Vsync signals */
+    _video_ext_in_config.inp_hs_edge    = EDGE_RISING;              /* Clock edge select for capturing Hsync signals */
+    _video_ext_in_config.inp_endian_on  = OFF;                      /* External input bit endian change on/off       */
+    _video_ext_in_config.inp_swap_on    = OFF;                      /* External input B/R signal swap on/off         */
+    _video_ext_in_config.inp_vs_inv     = SIG_POL_NOT_INVERTED;     /* External input DV_VSYNC inversion control     */
+    _video_ext_in_config.inp_hs_inv     = SIG_POL_INVERTED;         /* External input DV_HSYNC inversion control     */
+    _video_ext_in_config.inp_f525_625   = EXTIN_LINE_525;           /* Number of lines for BT.656 external input     */
+    _video_ext_in_config.inp_h_pos      = EXTIN_H_POS_CRYCBY;       /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+    _video_ext_in_config.cap_vs_pos     = 6u;                       /* Capture start position from Vsync             */
+    _video_ext_in_config.cap_hs_pos     = 302u;                     /* Capture start position form Hsync             */
+    _video_ext_in_config.cap_width      = 640u;                     /* Capture width                                 */
+    _video_ext_in_config.cap_height     = 468u;                     /* Capture height should be a multiple of 4      */
+} /* End of constructor method () */
+
+/**************************************************************************//**
+ * @brief       Graphics initialization processing
+ * @param[in]   lcd_config                : LCD configuration
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_init( lcd_config_t * lcd_config )
+{
+    if( lcd_config != NULL ) {
+        _lcd_config.lcd_type             = lcd_config->lcd_type;            /* LVDS or Pararel RGB                      */
+        _lcd_config.intputClock          = lcd_config->intputClock;         /* P1  clk [MHz] ex. 66.67                  */
+        _lcd_config.outputClock          = lcd_config->outputClock;         /* LCD clk [MHz] ex. 33.33                  */
+
+        _lcd_config.lcd_outformat        = lcd_config->lcd_outformat;       /* Output format select */
+        _lcd_config.lcd_edge             = lcd_config->lcd_edge;            /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+        _lcd_config.h_toatal_period      = lcd_config->h_toatal_period;     /* Free-running Hsync period                */
+        _lcd_config.v_toatal_period      = lcd_config->v_toatal_period;     /* Free-running Vsync period                */
+        _lcd_config.h_disp_widht         = lcd_config->h_disp_widht;        /* LCD display area size, horizontal width  */
+        _lcd_config.v_disp_widht         = lcd_config->v_disp_widht;        /* LCD display area size, vertical width    */
+        _lcd_config.h_back_porch         = lcd_config->h_back_porch;        /* LCD display horizontal back porch period */
+        _lcd_config.v_back_porch         = lcd_config->v_back_porch;        /* LCD display vertical back porch period   */
+
+        _lcd_config.h_sync_port          = lcd_config->h_sync_port;         /* TCONn or Not use(-1)                     */
+        _lcd_config.h_sync_port_polarity = lcd_config->h_sync_port_polarity;/* Polarity inversion control of signal     */
+        _lcd_config.h_sync_width         = lcd_config->h_sync_width;        /* Hsync width                              */
+
+        _lcd_config.v_sync_port          = lcd_config->v_sync_port;         /* TCONn or Not use(-1)                     */
+        _lcd_config.v_sync_port_polarity = lcd_config->v_sync_port_polarity;/* Polarity inversion control of signal     */
+        _lcd_config.v_sync_width         = lcd_config->v_sync_width;        /* Vsync width  */
+
+        _lcd_config.de_port              = lcd_config->de_port;             /* TCONn or Not use(-1)                     */
+        _lcd_config.de_port_polarity     = lcd_config->de_port_polarity;    /* Polarity inversion control of signal     */
+    }
+
+    return (graphics_error_t)DRV_Graphics_Init( (drv_lcd_config_t *)&_lcd_config );
+} /* End of method Graphics_init() */
+
+/**************************************************************************//**
+ * @brief       Graphics Video initialization processing
+ * @param[in]   video_input_sel                : Input select
+ * @param[in]   video_ext_in_config            : Digtal video input configuration
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Video_init( video_input_sel_t video_input_sel, video_ext_in_config_t * video_ext_in_config )
+{
+    graphics_error_t error = GRAPHICS_OK;
+
+    if( _video_input_sel == INPUT_SEL_VDEC || _video_input_sel == INPUT_SEL_EXT ) {
+        _video_input_sel = video_input_sel;
+    } else {
+        error = GRAPHICS_PARAM_RANGE_ERR;
+    }
+
+    if( error == GRAPHICS_OK ) {
+        if( video_ext_in_config != NULL ) {
+            /* Signals supplied via the external input pins        */
+            /* if using Video decoder output signals, not using value. */
+            _video_ext_in_config.inp_format    = video_ext_in_config->inp_format;
+            _video_ext_in_config.inp_pxd_edge  = video_ext_in_config->inp_pxd_edge;
+            _video_ext_in_config.inp_vs_edge   = video_ext_in_config->inp_vs_edge;
+            _video_ext_in_config.inp_hs_edge   = video_ext_in_config->inp_hs_edge;
+            _video_ext_in_config.inp_endian_on = video_ext_in_config->inp_endian_on;
+            _video_ext_in_config.inp_swap_on   = video_ext_in_config->inp_swap_on;
+            _video_ext_in_config.inp_vs_inv    = video_ext_in_config->inp_vs_inv;
+            _video_ext_in_config.inp_hs_inv    = video_ext_in_config->inp_hs_inv;
+            _video_ext_in_config.inp_f525_625  = video_ext_in_config->inp_f525_625;
+            _video_ext_in_config.inp_h_pos     = video_ext_in_config->inp_h_pos;
+            _video_ext_in_config.cap_vs_pos    = video_ext_in_config->cap_vs_pos;
+            _video_ext_in_config.cap_hs_pos    = video_ext_in_config->cap_hs_pos;
+            _video_ext_in_config.cap_width     = video_ext_in_config->cap_width;
+            _video_ext_in_config.cap_height    = video_ext_in_config->cap_height;
+        }
+    }
+    return (graphics_error_t)DRV_Graphics_Video_init( (drv_video_input_sel_t)video_input_sel,
+            (drv_video_ext_in_config_t *)&_video_ext_in_config );
+} /* End of method Graphics_Video_init() */
+
+/**************************************************************************//**
+ * @brief       LCD I/O initialization processing
+ * @param[in]   pin                       : Pointer of the pin assignment
+ * @param[in]   pin_count                 : Total number of the pin assignment
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Lcd_Port_Init( PinName *pin, unsigned int pin_count )
+{
+    return (graphics_error_t)DRV_Graphics_Lcd_Port_Init( pin, pin_count );
+} /* End of method Graphics_Lcd_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       LVDS I/O port initialization processing
+ * @param[in]   pin                       : Pointer of the pin assignment
+ * @param[in]   pin_count                 : Total number of the pin assignment
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Lvds_Port_Init( PinName *pin, unsigned int pin_count )
+{
+    return (graphics_error_t)DRV_Graphics_Lvds_Port_Init( pin, pin_count );
+} /* End of method Graphics_Lvds_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       Digital video input I/O port initialization processing
+ * @param[in]   pin                       : Pointer of the pin assignment
+ * @param[in]   pin_count                 : Total number of the pin assignment
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Dvinput_Port_Init( PinName *pin, unsigned int pin_count )
+{
+    return (graphics_error_t)DRV_Graphics_Dvinput_Port_Init( pin, pin_count );
+} /* End of method Graphics_Dvinput_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       IRQ interrupt handler setting
+ * @param[in]   irq                       : VDC5 interrupt type
+ * @param[in]   num                       : Interrupt line number
+ * @param[in]   * callback                : Interrupt callback function pointer
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Irq_Handler_Set( int_type_t irq, unsigned short num, void (* callback)(int_type_t)  )
+{
+    return (graphics_error_t)DRV_Graphics_Irq_Handler_Set( (vdc5_int_type_t)irq, num, (void (*)(vdc5_int_type_t))callback );
+} /* End of method Graphics_Irq_Handler_Set() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read start processing
+ * @param[in]   layer_id                  : Graphics layer ID
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Start( graphics_layer_t layer_id )
+{
+    return (graphics_error_t)DRV_Graphics_Start( (drv_graphics_layer_t)layer_id );
+} /* End of method Graphics_Start() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read stop processing
+ * @param[in]   layer_id                  : Graphics layer ID
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Stop( graphics_layer_t layer_id )
+{
+    return (graphics_error_t)DRV_Graphics_Stop( (drv_graphics_layer_t)layer_id );
+} /* End of method Graphics_Stop() */
+
+/**************************************************************************//**
+ * @brief       Video surface write start processing
+ * @param[in]   video_input_channel        : Video input channel
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Start( video_input_channel_t video_input_channel )
+{
+    graphics_error_t error = GRAPHICS_OK;
+
+    /*  Digital video inputs : supporting video_input_channel 0 only. */
+    if( _video_input_sel == INPUT_SEL_EXT && video_input_channel == VIDEO_INPUT_CHANNEL_1 ) {
+        error = GRAPHICS_PARAM_RANGE_ERR;
+    }
+
+    if( error == GRAPHICS_OK ) {
+        error = (graphics_error_t)DRV_Video_Start( (drv_video_input_channel_t)video_input_channel );
+    }
+    return error;
+} /* End of method Video_Start() */
+
+/**************************************************************************//**
+ * @brief       Video surface write stop processing
+ * @param[in]   video_input_channel        : Video input channel
+ * @retval      error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Stop( video_input_channel_t video_input_channel )
+{
+    graphics_error_t error = GRAPHICS_OK;
+
+    /*  Digital video inputs : supporting video_input_channel 0 only. */
+    if( _video_input_sel == INPUT_SEL_EXT && video_input_channel == VIDEO_INPUT_CHANNEL_1 ) {
+        error = GRAPHICS_PARAM_RANGE_ERR;
+    }
+
+    if( error == GRAPHICS_OK ) {
+        error = (graphics_error_t)DRV_Video_Stop(
+                    (drv_video_input_channel_t)video_input_channel );
+    }
+    return error;
+} /* End of method Video_Stop() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read process setting
+ *
+ *              Description:<br>
+ *              This function supports the following 4 image format.
+ *                  YCbCr422, RGB565, RGB888, ARGB8888
+ * @param[in]   layer_id                   : Graphics layer ID
+ * @param[in]   framebuff                  : Base address of the frame buffer
+ * @param[in]   fb_stride                  : Line offset address of the frame buffer
+ * @param[in]   gr_format                  : Format of the frame buffer read signal
+ * @param[in]   wr_rd_swa                  : frame buffer swap setting
+ *      - WR_RD_WRSWA_NON        : Not swapped: 1-2-3-4-5-6-7-8
+ *      - WR_RD_WRSWA_8BIT       : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+ *      - WR_RD_WRSWA_16BIT      : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+ *      - WR_RD_WRSWA_16_8BIT    : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+ *      - WR_RD_WRSWA_32BIT      : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+ *      - WR_RD_WRSWA_32_8BIT    : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+ *      - WR_RD_WRSWA_32_16BIT   : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+ *      - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+ * @param[in]   gr_rect                    : Graphics display area
+ * @retval      Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Read_Setting(
+    graphics_layer_t    layer_id,
+    void              * framebuff,
+    unsigned int        fb_stride,
+    graphics_format_t   gr_format,
+    wr_rd_swa_t         wr_rd_swa,
+    rect_t            * gr_rect )
+{
+    rect_t rect;
+
+    rect.hs = gr_rect->hs + _lcd_config.h_back_porch;
+    rect.vs = gr_rect->vs + _lcd_config.v_back_porch;
+    rect.hw = gr_rect->hw;
+    rect.vw = gr_rect->vw;
+
+    return (graphics_error_t)DRV_Graphics_Read_Setting(
+               (drv_graphics_layer_t)layer_id,
+               framebuff,
+               fb_stride,
+               (drv_graphics_format_t)gr_format,
+               (drv_wr_rd_swa_t)wr_rd_swa,
+               (drv_rect_t *)&rect );
+} /* End of method Graphics_Read_Setting() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read process changing
+ *
+ *              Description:<br>
+ *              This function is used to swap buffers.
+ *
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @retval      Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Read_Change ( graphics_layer_t layer_id, void *  framebuff)
+{
+    return (graphics_error_t)DRV_Graphics_Read_Change(
+               (drv_graphics_layer_t)layer_id, framebuff );
+} /* End of method Graphics_Read_Change() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read process changing
+ *
+ *              Description:<br>
+ *              This function is used to swap buffers.
+ *
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride               : stride of the framebuff
+ * @param[in]   slide_dir               : slide direction
+ * @retval      Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Graphics_Read_Change_More ( graphics_layer_t layer_id, void *  framebuff, unsigned int fb_stride, slide_t* slide_dir)
+{
+    return (graphics_error_t)DRV_Graphics_Read_Change_More(
+               (drv_graphics_layer_t)layer_id, framebuff, fb_stride, (void *) slide_dir);
+} /* End of method Graphics_Read_Change_More() */
+
+/**************************************************************************//**
+ * @brief       Video surface write process setting
+ *              This function set the video write process. Input form is weave
+ *              (progressive) mode fixed.
+ *              This function supports the following 3 image format.
+ *                  YCbCr422, RGB565, RGB888
+ * @param[in]   video_input_ch          : Video input channel
+ * @param[in]   col_sys                 : Analog video signal color system
+ * @param[in]   adc_vinsel              : Video input pin
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride [byte]        : Line offset address of the frame buffer
+ * @param[in]   video_format            : Frame buffer video-signal writing format
+ *      - VIDEO_FORMAT_YCBCR422 : YCBCR422 (2byte/px)
+ *      - VIDEO_FORMAT_RGB565   : RGB565 (2byte/px)
+ *      - VIDEO_FORMAT_RGB888   : RGB888 (4byte/px)
+ * @param[in]   wr_rd_swa               : frame buffer swap setting
+ *      - WR_RD_WRSWA_NON        : Not swapped: 1-2-3-4-5-6-7-8
+ *      - WR_RD_WRSWA_8BIT       : Swapped in 8-bit units: 2-1-4-3-6-5-8-7
+ *      - WR_RD_WRSWA_16BIT      : Swapped in 16-bit units: 3-4-1-2-7-8-5-6
+ *      - WR_RD_WRSWA_16_8BIT    : Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5
+ *      - WR_RD_WRSWA_32BIT      : Swapped in 32-bit units: 5-6-7-8-1-2-3-4
+ *      - WR_RD_WRSWA_32_8BIT    : Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3
+ *      - WR_RD_WRSWA_32_16BIT   : Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2
+ *      - WR_RD_WRSWA_32_16_8BIT : Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1
+ * @param[in]   video_write_size_vw [px]: output v width
+ * @param[in]   video_write_size_hw [px]: output h width
+ * @param[in]   video_adc_vinsel        : Input pin control
+ * @retval      Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Write_Setting(
+    video_input_channel_t       video_input_channel,
+    graphics_video_col_sys_t    col_sys,
+    void                      * framebuff,
+    unsigned int                fb_stride,
+    video_format_t              video_format,
+    wr_rd_swa_t                 wr_rd_swa,
+    unsigned short              write_buff_vw,
+    unsigned short              write_buff_hw,
+    video_adc_vinsel_t          video_adc_vinsel )
+
+{
+    graphics_error_t error = GRAPHICS_OK;
+
+    if( _video_input_sel == INPUT_SEL_VDEC ) {
+	  #ifdef NO_SCALE_UP
+        if( col_sys == COL_SYS_NTSC_358 || col_sys == COL_SYS_NTSC_443 || col_sys == COL_SYS_NTSC_443_60 ) {
+            if( (write_buff_vw / 2u) > 240u ) {
+                error = GRAPHICS_VIDEO_NTSC_SIZE_ERR;
+            }
+        } else {
+            if( (write_buff_vw / 2u) > 280u ) {
+                error = GRAPHICS_VIDEO_PAL_SIZE_ERR;
+            }
+        }
+
+        if( write_buff_hw > 800u ) {
+            error = GRAPHICS_PARAM_RANGE_ERR;
+        }
+	  #endif
+        if( error == GRAPHICS_OK ) {
+            error = (graphics_error_t)DRV_Video_Write_Setting(
+                        (drv_video_input_channel_t)video_input_channel,
+                        (drv_graphics_video_col_sys_t)col_sys,
+                        framebuff,
+                        fb_stride,
+                        (drv_video_format_t)video_format,
+                        (drv_wr_rd_swa_t)wr_rd_swa,
+                        write_buff_vw,
+                        write_buff_hw,
+                        (drv_video_adc_vinsel_t)video_adc_vinsel);
+        }
+    } else if( _video_input_sel == INPUT_SEL_EXT ) {
+        rect_t cap_area;
+
+        cap_area.hs = _video_ext_in_config.cap_hs_pos * 2;
+        cap_area.hw = _video_ext_in_config.cap_width  * 2;
+        cap_area.vs = _video_ext_in_config.cap_vs_pos;
+        cap_area.vw = _video_ext_in_config.cap_height;
+
+        error = (graphics_error_t) DRV_Video_Write_Setting_Digital(
+                    framebuff,
+                    fb_stride,
+                    (drv_video_format_t)video_format,
+                    (drv_wr_rd_swa_t)wr_rd_swa,
+                    write_buff_vw,
+                    write_buff_hw,
+                    (drv_rect_t *)&cap_area );
+    } else {
+        error = GRAPHICS_PARAM_RANGE_ERR;
+    }
+    return error;
+} /* End of method Video_Write_Setting() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface write process changing
+ *              This function is used to swap buffers of the weave write processing.
+ * @param[in]   video_input_ch          : Video input channle
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride               : Line offset address of the frame buffer
+ * @retval      Error code
+******************************************************************************/
+DisplayBase::graphics_error_t
+DisplayBase::Video_Write_Change (
+    video_input_channel_t video_input_channel, void * framebuff, uint32_t fb_stride )
+{
+    return (graphics_error_t)DRV_Video_Write_Change(
+               (drv_video_input_channel_t)video_input_channel, framebuff, fb_stride );
+} /* End of method Video_Write_Change() */
+
+/* End of file */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/common/lcd_panel/lcd_analog_rgb_ch1.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,239 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_analog_rgb_ch1.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 1 function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+#include    "iodefine.h"
+#include    "lcd_panel.h"
+
+#if     (LCD_VDC5_CH1_PANEL==1)
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Port 4 */
+#define LCD_PORT4_2ND (0x5400u)
+/* Port 9 */
+#define LCD_PORT9_1ST (0x00FCu)
+/* Port 5 */
+#define LCD_PORT5_7TH (0x0600u)
+#define LCD_PORT5_2ND (0x00FFu)
+/* Port 2 */
+#define LCD_PORT2_7TH (0xF000u)
+#define LCD_PORT2_6TH (0x0F00u)
+
+#define FH_1_2_CYCLE   (2u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       LCD panel I/O port setup (VDC5 channel 1)
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch1 (void)
+{
+    volatile uint32_t   dummy_read;
+    uint32_t            reg_data;
+
+    /*  Analog RGB D-sub15 (RGB888)
+            VSYNC       : LCD1_TCON1            ... P4_14, 2nd alternative function
+                        : LCD1_CLK              ... P4_12, 2nd alternative function
+            HSYNC       : LCD1_TCON5            ... P4_10, 2nd alternative function
+        LCD1_DATA
+            R[7:0]      : LCD1_DATA[23:18]      ... P9_7 ~ P9_2, 1st alternative function
+                        :          [17:16]      ... P5_10 ~ P5_9, 7th alternative function
+            G[7:0]      : LCD1_DATA[15:12]      ... P2_15 ~ P2_12, 7th alternative function
+                        :          [11:8]       ... P2_11 ~ P2_8, 6th alternative function
+            B[7:0]      : LCD1_DATA[7:0]        ... P5_7 ~ P5_0, 2nd alternative function
+    */
+    /* Port 4 */
+    reg_data        = (uint32_t)GPIO.PMC4 & (uint32_t)~LCD_PORT4_2ND;
+    GPIO.PMC4       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC4;
+    dummy_read      = reg_data;
+    /* PFCAE4, PFCE4, PFC4 ... 2nd alternative function
+       PIPC4, PMC4
+       b14      : P4_14
+       b12      : P4_12
+       b10      : P4_10 */
+    reg_data        = (uint32_t)GPIO.PFCAE4 & (uint32_t)~LCD_PORT4_2ND;
+    GPIO.PFCAE4     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE4 & (uint32_t)~LCD_PORT4_2ND;
+    GPIO.PFCE4      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC4 | (uint32_t)LCD_PORT4_2ND;
+    GPIO.PFC4       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PIPC4 | (uint32_t)LCD_PORT4_2ND;
+    GPIO.PIPC4      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC4 | (uint32_t)LCD_PORT4_2ND;
+    GPIO.PMC4       = (uint16_t)reg_data;
+
+    /* Port 9 */
+    reg_data        = (uint32_t)GPIO.PMC9 & (uint32_t)~LCD_PORT9_1ST;
+    GPIO.PMC9       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC9;
+    dummy_read      = reg_data;
+    /* PFCAE9, PFCE9, PFC9 ... 1st alternative function
+       PIPC9, PMC9
+       b7:b2    : P9_7 ~ P9_2 */
+    reg_data        = (uint32_t)GPIO.PFCAE9 & (uint32_t)~LCD_PORT9_1ST;
+    GPIO.PFCAE9     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE9 & (uint32_t)~LCD_PORT9_1ST;
+    GPIO.PFCE9      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC9 & (uint32_t)~LCD_PORT9_1ST;
+    GPIO.PFC9       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PIPC9 | (uint32_t)LCD_PORT9_1ST;
+    GPIO.PIPC9      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC9 | (uint32_t)LCD_PORT9_1ST;
+    GPIO.PMC9       = (uint16_t)reg_data;
+
+    /* Port 5 */
+    reg_data        = (uint32_t)GPIO.PMC5 & (uint32_t)~(LCD_PORT5_7TH|LCD_PORT5_2ND);
+    GPIO.PMC5       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC5;
+    dummy_read      = reg_data;
+    /* PFCAE5, PFCE5, PFC5 ... 7th alternative function
+       b10:b9   : P5_10 ~ P5_9 */
+    reg_data        = (uint32_t)GPIO.PFCAE5 | (uint32_t)LCD_PORT5_7TH;
+    GPIO.PFCAE5     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE5 | (uint32_t)LCD_PORT5_7TH;
+    GPIO.PFCE5      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC5 & (uint32_t)~LCD_PORT5_7TH;
+    GPIO.PFC5       = (uint16_t)reg_data;
+    /* PFCAE5, PFCE5, PFC5 ... 2nd alternative function
+       b7:b0    : P5_7 ~ P5_0 */
+    reg_data        = (uint32_t)GPIO.PFCAE5 & (uint32_t)~LCD_PORT5_2ND;
+    GPIO.PFCAE5     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE5 & (uint32_t)~LCD_PORT5_2ND;
+    GPIO.PFCE5      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC5 | (uint32_t)LCD_PORT5_2ND;
+    GPIO.PFC5       = (uint16_t)reg_data;
+    /* PIPC5, PMC5
+       b10:b9   : P5_10 ~ P5_9
+       b7:b0    : P5_7 ~ P5_0 */
+    reg_data        = (uint32_t)GPIO.PIPC5 | (uint32_t)(LCD_PORT5_7TH|LCD_PORT5_2ND);
+    GPIO.PIPC5      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC5 | (uint32_t)(LCD_PORT5_7TH|LCD_PORT5_2ND);
+    GPIO.PMC5       = (uint16_t)reg_data;
+
+    /* Port 2 */
+    reg_data        = (uint32_t)GPIO.PMC2 & (uint32_t)~(LCD_PORT2_7TH|LCD_PORT2_6TH);
+    GPIO.PMC2       = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC2;
+    dummy_read      = reg_data;
+    /* PFCAE2, PFCE2, PFC2 ... 7th alternative function
+       b15:b12  : P2_15 ~ P2_12 */
+    reg_data        = (uint32_t)GPIO.PFCAE2 | (uint32_t)LCD_PORT2_7TH;
+    GPIO.PFCAE2     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE2 | (uint32_t)LCD_PORT2_7TH;
+    GPIO.PFCE2      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC2 & (uint32_t)~LCD_PORT2_7TH;
+    GPIO.PFC2       = (uint16_t)reg_data;
+    /* PFCAE2, PFCE2, PFC2 ... 6th alternative function
+       b11:b8   : P2_11 ~ P2_8 */
+    reg_data        = (uint32_t)GPIO.PFCAE2 | (uint32_t)LCD_PORT2_6TH;
+    GPIO.PFCAE2     = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFCE2 & (uint32_t)~LCD_PORT2_6TH;
+    GPIO.PFCE2      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PFC2 | (uint32_t)LCD_PORT2_6TH;
+    GPIO.PFC2       = (uint16_t)reg_data;
+    /* PIPC2, PMC2
+       b15:b8   : P2_15 ~ P2_8 */
+    reg_data        = (uint32_t)GPIO.PIPC2 | (uint32_t)(LCD_PORT2_7TH|LCD_PORT2_6TH);
+    GPIO.PIPC2      = (uint16_t)reg_data;
+    reg_data        = (uint32_t)GPIO.PMC2 | (uint32_t)(LCD_PORT2_7TH|LCD_PORT2_6TH);
+    GPIO.PMC2       = (uint16_t)reg_data;
+}   /* End of function GRAPHICS_SetLcdPanel_Ch1() */
+
+/**************************************************************************//**
+ * @brief       LCD TCON setup parameter acquisition processing (VDC5 channel 1)
+ * @param[out]  outctrl     : Address of the area for storing the LCD TCON timing setup data table
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings_Ch1 (const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+    /* Analog RGB D-sub15 (RGB888), SVGA signal 800x600 */
+    /* TCON timing setting, VS */
+    static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS = {
+        (uint16_t)(LCD_CH1_S_VSYNC * FH_1_2_CYCLE),   /* Signal pulse start position */
+        (uint16_t)(LCD_CH1_W_VSYNC * FH_1_2_CYCLE),   /* Pulse width */
+        VDC5_LCD_TCON_POLMD_NORMAL,
+        VDC5_LCD_TCON_REFSEL_HSYNC,
+        LCD_CH1_POL_VSYNC,                  /* Polarity inversion control of signal */
+        VDC5_LCD_TCON_PIN_1,                /* Output pin for LCD driving signal */
+        LCD_CH1_OUT_EDGE                    /* Output phase control of signal */
+    };
+    /* TCON timing setting, HS */
+    static const vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS = {
+        (uint16_t)LCD_CH1_S_HSYNC,          /* Signal pulse start position */
+        (uint16_t)LCD_CH1_W_HSYNC,          /* Pulse width */
+        VDC5_LCD_TCON_POLMD_NORMAL,
+        VDC5_LCD_TCON_REFSEL_HSYNC,         /* Signal operating reference select */
+        LCD_CH1_POL_HSYNC,                  /* Polarity inversion control of signal */
+        VDC5_LCD_TCON_PIN_5,                /* Output pin for LCD driving signal */
+        LCD_CH1_OUT_EDGE                    /* Output phase control of signal */
+    };
+
+    if (outctrl != NULL) {
+        outctrl[VDC5_LCD_TCONSIG_STVA_VS]   = &lcd_tcon_timing_VS;  /* STVA/VS: Vsync */
+        outctrl[VDC5_LCD_TCONSIG_STVB_VE]   = NULL;                 /* STVB/VE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = &lcd_tcon_timing_HS;  /* STH/SP/HS: Hsync */
+        outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL;                 /* STB/LP/HE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_CPV_GCK]   = NULL;                 /* CPV/GCK: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLA]      = NULL;                 /* POLA: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLB]      = NULL;                 /* POLB: Not used */
+        outctrl[VDC5_LCD_TCONSIG_DE]        = NULL;                 /* DE: Not used */
+    }
+}   /* End of function GRAPHICS_SetLcdTconSettings_Ch1() */
+
+#endif  /* LCD_VDC5_CH1_PANEL==LCD_CH1_PANEL_ANALOG_RGB */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/common/lcd_panel/lcd_vklcd50rta_ch0.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,100 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_vklcd50rta_ch0.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 0 function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+#include    "iodefine.h"
+#include    "lcd_panel.h"
+
+#if     (LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_VKLCD50RTA)
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       LCD panel I/O port setup (VDC5 channel 0)
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch0 (void)
+{
+
+    /* Not Support */
+
+}   /* End of function GRAPHICS_SetLcdPanel_Ch0() */
+
+/**************************************************************************//**
+ * @brief       LCD TCON setup parameter acquisition processing (VDC5 channel 0)
+ * @param[out]  outctrl     : Address of the area for storing the LCD TCON timing setup data table
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings_Ch0 (const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+    /* Not Support */
+
+    if (outctrl != NULL) {
+        outctrl[VDC5_LCD_TCONSIG_STVA_VS]   = NULL;                 /* STVA/VS: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STVB_VE]   = NULL;                 /* STVB/VE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = NULL;                 /* STH/SP/HS: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL;                 /* STB/LP/HE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_CPV_GCK]   = NULL;                 /* CPV/GCK: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLA]      = NULL;                 /* POLA: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLB]      = NULL;                 /* POLB: Not used */
+        outctrl[VDC5_LCD_TCONSIG_DE]        = NULL;                 /* DE: Not used */
+    }
+}   /* End of function GRAPHICS_SetLcdTconSettings_Ch0() */
+
+#endif  /* LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_VKLCD50RTA */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/common/lcd_panel/lcd_vklcd70rt_ch0.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,100 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_vklcd70rt_ch0.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 0 function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+#include    "iodefine.h"
+#include    "lcd_panel.h"
+
+#if     (LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_VKLCD70RT)
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       LCD panel I/O port setup (VDC5 channel 0)
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch0 (void)
+{
+
+    /* Not Support */
+
+}   /* End of function GRAPHICS_SetLcdPanel_Ch0() */
+
+/**************************************************************************//**
+ * @brief       LCD TCON setup parameter acquisition processing (VDC5 channel 0)
+ * @param[out]  outctrl     : Address of the area for storing the LCD TCON timing setup data table
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings_Ch0 (const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+    /* Not Support */
+
+    if (outctrl != NULL) {
+        outctrl[VDC5_LCD_TCONSIG_STVA_VS]   = NULL;                 /* STVA/VS: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STVB_VE]   = NULL;                 /* STVB/VE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = NULL;                 /* STH/SP/HS: Not used */
+        outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL;                 /* STB/LP/HE: Not used */
+        outctrl[VDC5_LCD_TCONSIG_CPV_GCK]   = NULL;                 /* CPV/GCK: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLA]      = NULL;                 /* POLA: Not used */
+        outctrl[VDC5_LCD_TCONSIG_POLB]      = NULL;                 /* POLB: Not used */
+        outctrl[VDC5_LCD_TCONSIG_DE]        = NULL;                 /* DE: Not used */
+    }
+}   /* End of function GRAPHICS_SetLcdTconSettings_Ch0() */
+
+#endif  /* LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_VKLCD70RT */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/common/lcd_settings.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,115 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_settings.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver LCD panel settings sample
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+#include    "iodefine.h"
+#include    "lcd_panel.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define LVDSPLL_TST (16u)     /* LVDSPLL_TST (LVDS PLL internal parameters) */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       LCD panel I/O port setup
+ * @param[in]   channel
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdPanel (const vdc5_channel_t channel)
+{
+    if (channel == VDC5_CHANNEL_0)    {
+        GRAPHICS_SetLcdPanel_Ch0();
+    } else {
+        GRAPHICS_SetLcdPanel_Ch1();
+    }
+}   /* End of function GRAPHICS_SetLcdPanel() */
+
+/**************************************************************************//**
+ * @brief       LCD TCON setup parameter acquisition processing
+ * @param[in]   channel
+ * @param[out]  outctrl         : Address of the area for storing the LCD TCON timing setup data table
+ * @retval      None
+******************************************************************************/
+void GRAPHICS_SetLcdTconSettings (const vdc5_channel_t channel, const vdc5_lcd_tcon_timing_t * * const outctrl)
+{
+    /* LCD TCON timing setting */
+    if (channel == VDC5_CHANNEL_0) {
+        GRAPHICS_SetLcdTconSettings_Ch0(outctrl);
+    } else {
+        GRAPHICS_SetLcdTconSettings_Ch1(outctrl);
+    }
+}   /* End of function GRAPHICS_SetLcdTconSettings() */
+
+/**************************************************************************//**
+ * @brief       LVDS-related parameter acquisition processing
+ * @param[in]   channel
+ * @retval      Address of the area containing the LVDS-related parameters
+******************************************************************************/
+vdc5_lvds_t * GRAPHICS_GetLvdsParam (const vdc5_channel_t channel)
+{
+    static vdc5_lvds_t  lvds_param;
+    vdc5_lvds_t       * p_lvds;
+
+    p_lvds = (vdc5_lvds_t *)&lvds_param;
+
+    if (channel == VDC5_CHANNEL_0) {
+        p_lvds = NULL;
+    } else {
+        p_lvds = NULL;
+    }
+    return p_lvds;
+}   /* End of function GRAPHICS_GetLvdsParam() */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdc5/include/r_vdc5.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,965 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver API definitions
+******************************************************************************/
+
+#ifndef R_VDC5_H
+#define R_VDC5_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5_user.h"
+
+
+#ifdef  __cplusplus
+extern  "C"
+{
+#endif  /* __cplusplus */
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC5_GAM_GAIN_ADJ_NUM       (32u)   /*!< The number of the gamma correction gain coefficient */
+#define     VDC5_GAM_START_TH_NUM       (31u)   /*!< The number of the gamma correction start threshold */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Error codes of the VDC5 driver */
+typedef enum {
+    VDC5_OK = 0,                /*!< Normal termination */
+    VDC5_ERR_PARAM_CHANNEL,     /*!< Invalid channel error (parameter error): An illegal channel is specified. */
+    VDC5_ERR_PARAM_LAYER_ID,    /*!< Invalid layer ID error (parameter error): An illegal layer ID is specified. */
+    VDC5_ERR_PARAM_NULL,        /*!< NULL specification error (parameter error):
+                                     NULL is specified for a required parameter. */
+    VDC5_ERR_PARAM_BIT_WIDTH,   /*!< Bit width error (parameter error):
+                                     A value exceeding the possible bit width is specified. */
+    VDC5_ERR_PARAM_UNDEFINED,   /*!< Undefined parameter error (parameter error):
+                                     A value that is not defined in the specification is specified. */
+    VDC5_ERR_PARAM_EXCEED_RANGE,/*!< Out-of-value-range error (parameter error):
+                                     The specified parameter value is beyond the value range defined
+                                     in the specification. */
+    VDC5_ERR_PARAM_CONDITION,   /*!< Unauthorized condition error (parameter error):
+                                     A parameter is specified under conditions that are not authorized
+                                     by the specification. */
+    VDC5_ERR_IF_CONDITION,      /*!< Interface condition error (interface error):
+                                     An API function is called under unauthorized conditions. */
+    VDC5_ERR_RESOURCE_CLK,      /*!< Clock resource error (resource error): No panel clock is set up. */
+    VDC5_ERR_RESOURCE_VSYNC,    /*!< Vsync signal resource error (resource error): No Vsync signal is set up. */
+    VDC5_ERR_RESOURCE_INPUT,    /*!< Input signal resource error (resource error): No video image input is set up. */
+    VDC5_ERR_RESOURCE_OUTPUT,   /*!< Output resource error (resource error): No display output is set up. */
+    VDC5_ERR_RESOURCE_LVDS_CLK, /*!< LVDS clock resource error (resource error):
+                                     An attempt is made to use the LVDS clock without setting it up,
+                                     or the LVDS clock is specified when it is already set up. */
+    VDC5_ERR_RESOURCE_LAYER,    /*!< Layer resource error (resource error):
+                                     The specified layer is under unavailable conditions. */
+    VDC5_ERR_NUM                /*!< The number of error codes */
+} vdc5_error_t;
+
+/*! VDC5 channels */
+typedef enum {
+    VDC5_CHANNEL_0 = 0,         /*!< Channel 0 */
+    VDC5_CHANNEL_1,             /*!< Channel 1 */
+    VDC5_CHANNEL_NUM            /*!< The number of channels */
+} vdc5_channel_t;
+
+/*! On/off */
+typedef enum {
+    VDC5_OFF    = 0,            /*!< Off */
+    VDC5_ON     = 1             /*!< On */
+} vdc5_onoff_t;
+/*! Edge of a signal */
+typedef enum {
+    VDC5_EDGE_RISING    = 0,    /*!< Rising edge */
+    VDC5_EDGE_FALLING   = 1     /*!< Falling edge */
+} vdc5_edge_t;
+/*! Polarity of a signal */
+typedef enum {
+    VDC5_SIG_POL_NOT_INVERTED   = 0,    /*!< Not inverted */
+    VDC5_SIG_POL_INVERTED       = 1     /*!< Inverted */
+} vdc5_sig_pol_t;
+
+/*! Scaling type ID */
+typedef enum {
+    VDC5_SC_TYPE_SC0 = 0,               /*!< Scaler 0 */
+    VDC5_SC_TYPE_SC1,                   /*!< Scaler 1 */
+    VDC5_SC_TYPE_OIR,                   /*!< Output image generator (OIR) */
+    VDC5_SC_TYPE_NUM                    /*!< The number of scaler types */
+} vdc5_scaling_type_t;
+/*! Graphics type ID */
+typedef enum {
+    VDC5_GR_TYPE_GR0 = 0,               /*!< Graphics 0 */
+    VDC5_GR_TYPE_GR1,                   /*!< Graphics 1 */
+    VDC5_GR_TYPE_GR2,                   /*!< Graphics 2 */
+    VDC5_GR_TYPE_GR3,                   /*!< Graphics 3 */
+    VDC5_GR_TYPE_VIN,                   /*!< VIN synthesizer */
+    VDC5_GR_TYPE_OIR,                   /*!< Output image generator (OIR) */
+    VDC5_GR_TYPE_NUM                    /*!< The number of graphics types */
+} vdc5_graphics_type_t;
+/*! Layer ID */
+typedef enum {
+    VDC5_LAYER_ID_ALL       = -1,                                       /*!< All layers */
+    VDC5_LAYER_ID_0_WR      = (VDC5_SC_TYPE_SC0 + 0),                   /*!< Write process for layer 0 */
+    VDC5_LAYER_ID_1_WR      = (VDC5_SC_TYPE_SC1 + 0),                   /*!< Write process for layer 1 */
+    VDC5_LAYER_ID_OIR_WR    = (VDC5_SC_TYPE_OIR + 0),                   /*!< Write process for layer OIR */
+    VDC5_LAYER_ID_0_RD      = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR0),    /*!< Read process for layer 0 */
+    VDC5_LAYER_ID_1_RD      = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR1),    /*!< Read process for layer 1 */
+    VDC5_LAYER_ID_2_RD      = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR2),    /*!< Read process for layer 2 */
+    VDC5_LAYER_ID_3_RD      = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_GR3),    /*!< Read process for layer 3 */
+    VDC5_LAYER_ID_VIN_RD    = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_VIN),    /*!< VIN synthesizer */
+    VDC5_LAYER_ID_OIR_RD    = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_OIR),    /*!< Read process for layer OIR */
+    VDC5_LAYER_ID_NUM       = (VDC5_SC_TYPE_NUM + VDC5_GR_TYPE_NUM)     /*!< The number of layer IDs */
+} vdc5_layer_id_t;
+/*! The horizontal/vertical timing of the VDC5 signals */
+typedef struct {
+    uint16_t    vs;                 /*!< Vertical signal start position from the reference signal */
+    uint16_t    vw;                 /*!< Vertical signal width (height) */
+    uint16_t    hs;                 /*!< Horizontal signal start position from the reference signal */
+    uint16_t    hw;                 /*!< Horizontal signal width */
+} vdc5_period_rect_t;
+/*! The relative position within the graphics display area */
+typedef struct {
+    uint16_t   vs_rel;              /*!< Vertical start position */
+    uint16_t   vw_rel;              /*!< Vertical width (height) */
+    uint16_t   hs_rel;              /*!< Horizontal start position */
+    uint16_t   hw_rel;              /*!< Horizontal width */
+} vdc5_pd_disp_rect_t;
+
+/***********************    For R_VDC5_Initialize       ***********************/
+/*! Panel clock select */
+typedef enum {
+    VDC5_PANEL_ICKSEL_IMG = 0,      /*!< Divided video image clock (VIDEO_X1) */
+    VDC5_PANEL_ICKSEL_IMG_DV,       /*!< Divided video image clock (DV_CLK) */
+    VDC5_PANEL_ICKSEL_EXT_0,        /*!< Divided external clock (LCD0_EXTCLK) */
+    VDC5_PANEL_ICKSEL_EXT_1,        /*!< Divided external clock (LCD1_EXTCLK) */
+    VDC5_PANEL_ICKSEL_PERI,         /*!< Divided peripheral clock 1 */
+    VDC5_PANEL_ICKSEL_LVDS,         /*!< LVDS PLL clock */
+    VDC5_PANEL_ICKSEL_LVDS_DIV7,    /*!< LVDS PLL clock divided by 7 */
+    VDC5_PANEL_ICKSEL_NUM           /*!< The number of panel clock select settings */
+} vdc5_panel_clksel_t;
+/*! Clock frequency division ratio */
+typedef enum {
+    VDC5_PANEL_CLKDIV_1_1 = 0,      /*!< Division Ratio 1/1 */
+    VDC5_PANEL_CLKDIV_1_2,          /*!< Division Ratio 1/2 */
+    VDC5_PANEL_CLKDIV_1_3,          /*!< Division Ratio 1/3 */
+    VDC5_PANEL_CLKDIV_1_4,          /*!< Division Ratio 1/4 */
+    VDC5_PANEL_CLKDIV_1_5,          /*!< Division Ratio 1/5 */
+    VDC5_PANEL_CLKDIV_1_6,          /*!< Division Ratio 1/6 */
+    VDC5_PANEL_CLKDIV_1_7,          /*!< Division Ratio 1/7 */
+    VDC5_PANEL_CLKDIV_1_8,          /*!< Division Ratio 1/8 */
+    VDC5_PANEL_CLKDIV_1_9,          /*!< Division Ratio 1/9 */
+    VDC5_PANEL_CLKDIV_1_12,         /*!< Division Ratio 1/12 */
+    VDC5_PANEL_CLKDIV_1_16,         /*!< Division Ratio 1/16 */
+    VDC5_PANEL_CLKDIV_1_24,         /*!< Division Ratio 1/24 */
+    VDC5_PANEL_CLKDIV_1_32,         /*!< Division Ratio 1/32 */
+    VDC5_PANEL_CLKDIV_NUM           /*!< The number of division ratio settings */
+} vdc5_panel_clk_dcdr_t;
+/*! The clock input to frequency divider 1 */
+typedef enum {
+    VDC5_LVDS_INCLK_SEL_IMG = 0,    /*!< Video image clock (VIDEO_X1) */
+    VDC5_LVDS_INCLK_SEL_DV_0,       /*!< Video image clock (DV0_CLK) */
+    VDC5_LVDS_INCLK_SEL_DV_1,       /*!< Video image clock (DV1_CLK) */
+    VDC5_LVDS_INCLK_SEL_EXT_0,      /*!< External clock (LCD0_EXTCLK) */
+    VDC5_LVDS_INCLK_SEL_EXT_1,      /*!< External clock (LCD1_EXTCLK) */
+    VDC5_LVDS_INCLK_SEL_PERI,       /*!< Peripheral clock 1 */
+    VDC5_LVDS_INCLK_SEL_NUM
+} vdc5_lvds_in_clk_sel_t;
+/*! The frequency dividing value (NIDIV or NODIV) */
+typedef enum {
+    VDC5_LVDS_NDIV_1 = 0,           /*!< Div 1 */
+    VDC5_LVDS_NDIV_2,               /*!< Div 2 */
+    VDC5_LVDS_NDIV_4,               /*!< Div 4 */
+    VDC5_LVDS_NDIV_NUM
+} vdc5_lvds_ndiv_t;
+/*! The frequency dividing value (NOD) for the output frequency */
+typedef enum {
+    VDC5_LVDS_PLL_NOD_1 = 0,        /*!< Div 1 */
+    VDC5_LVDS_PLL_NOD_2,            /*!< Div 2 */
+    VDC5_LVDS_PLL_NOD_4,            /*!< Div 4 */
+    VDC5_LVDS_PLL_NOD_8,            /*!< Div 8 */
+    VDC5_LVDS_PLL_NOD_NUM
+} vdc5_lvds_pll_nod_t;
+/*! LVDS parameter */
+typedef struct {
+    vdc5_lvds_in_clk_sel_t  lvds_in_clk_sel;/*!< The clock input to frequency divider 1 */
+    vdc5_lvds_ndiv_t        lvds_idiv_set;  /*!< The frequency dividing value (NIDIV) for frequency divider 1 */
+    uint16_t                lvdspll_tst;    /*!< Internal parameter setting for LVDS PLL */
+    vdc5_lvds_ndiv_t        lvds_odiv_set;  /*!< The frequency dividing value (NODIV) for frequency divider 2 */
+    vdc5_channel_t          lvds_vdc_sel;   /*!< A channel in VDC5 whose data is to be output through the LVDS */
+    uint16_t                lvdspll_fd;     /*!< The frequency dividing value (NFD) for the feedback frequency */
+    uint16_t                lvdspll_rd;     /*!< The frequency dividing value (NRD) for the input frequency */
+    vdc5_lvds_pll_nod_t     lvdspll_od;     /*!< The frequency dividing value (NOD) for the output frequency */
+} vdc5_lvds_t;
+/*! Initialization parameter */
+typedef struct {
+    vdc5_panel_clksel_t     panel_icksel;   /*!< Panel clock select */
+    vdc5_panel_clk_dcdr_t   panel_dcdr;     /*!< Clock frequency division ratio */
+    const vdc5_lvds_t     * lvds;           /*!< LVDS-related parameter */
+} vdc5_init_t;
+
+/***********************    For R_VDC5_VideoInput       ***********************/
+/*! Input select */
+typedef enum {
+    VDC5_INPUT_SEL_VDEC     = 0,    /*!< Video decoder output signals */
+    VDC5_INPUT_SEL_EXT      = 1     /*!< Signals supplied via the external input pins */
+} vdc5_input_sel_t;
+/*! Sync signal delay adjustment parameter */
+typedef struct {
+    uint16_t    inp_vs_dly_l;       /*!< Number of lines for delaying Vsync signal and field differentiation signal */
+    uint16_t    inp_fld_dly;        /*!< Field differentiation signal delay amount */
+    uint16_t    inp_vs_dly;         /*!< Vsync signal delay amount */
+    uint16_t    inp_hs_dly;         /*!< Hsync signal delay amount */
+} vdc5_sync_delay_t;
+/*! External input format select */
+typedef enum {
+    VDC5_EXTIN_FORMAT_RGB888 = 0,   /*!< RGB888 */
+    VDC5_EXTIN_FORMAT_RGB666,       /*!< RGB666 */
+    VDC5_EXTIN_FORMAT_RGB565,       /*!< RGB565 */
+    VDC5_EXTIN_FORMAT_BT656,        /*!< BT6556 */
+    VDC5_EXTIN_FORMAT_BT601,        /*!< BT6501 */
+    VDC5_EXTIN_FORMAT_YCBCR422,     /*!< YCbCr422 */
+    VDC5_EXTIN_FORMAT_YCBCR444,     /*!< YCbCr444 */
+    VDC5_EXTIN_FORMAT_NUM
+} vdc5_extin_format_t;
+/*! Reference select for external input BT.656 Hsync signal */
+typedef enum {
+    VDC5_EXTIN_REF_H_EAV    = 0,    /*!< EAV */
+    VDC5_EXTIN_REF_H_SAV    = 1     /*!< SAV */
+} vdc5_extin_ref_hsync_t;
+/*! Number of lines for BT.656 external input */
+typedef enum {
+    VDC5_EXTIN_LINE_525     = 0,    /*!< 525 lines */
+    VDC5_EXTIN_LINE_625     = 1     /*!< 625 lines */
+} vdc5_extin_input_line_t;
+/*! Y/Cb/Y/Cr data string start timing */
+typedef enum {
+    VDC5_EXTIN_H_POS_CBYCRY = 0,    /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+    VDC5_EXTIN_H_POS_YCRYCB,        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+    VDC5_EXTIN_H_POS_CRYCBY,        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+    VDC5_EXTIN_H_POS_YCBYCR,        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+    VDC5_EXTIN_H_POS_NUM
+} vdc5_extin_h_pos_t;
+/*! External input signal parameter */
+typedef struct {
+    vdc5_extin_format_t     inp_format;     /*!< External input format select */
+    vdc5_edge_t             inp_pxd_edge;   /*!< Clock edge select for capturing external input video image signals */
+    vdc5_edge_t             inp_vs_edge;    /*!< Clock edge select for capturing external input Vsync signals */
+    vdc5_edge_t             inp_hs_edge;    /*!< Clock edge select for capturing external input Hsync signals */
+    vdc5_onoff_t            inp_endian_on;  /*!< External input bit endian change on/off control */
+    vdc5_onoff_t            inp_swap_on;    /*!< External input B/R signal swap on/off control */
+    vdc5_sig_pol_t          inp_vs_inv;     /*!< External input Vsync signal DV_VSYNC inversion control */
+    vdc5_sig_pol_t          inp_hs_inv;     /*!< External input Hsync signal DV_HSYNC inversion control */
+    vdc5_extin_ref_hsync_t  inp_h_edge_sel; /*!< Reference select for external input BT.656 Hsync signal */
+    vdc5_extin_input_line_t inp_f525_625;   /*!< Number of lines for BT.656 external input */
+    vdc5_extin_h_pos_t      inp_h_pos;      /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
+} vdc5_ext_in_sig_t;
+/*! Video input setup parameter */
+typedef struct {
+    vdc5_input_sel_t            inp_sel;    /*!< Input select */
+    uint16_t                    inp_fh50;   /*!< Vsync signal 1/2fH phase timing */
+    uint16_t                    inp_fh25;   /*!< Vsync signal 1/4fH phase timing */
+    const vdc5_sync_delay_t   * dly;        /*!< Sync signal delay adjustment parameter */
+    const vdc5_ext_in_sig_t   * ext_sig;    /*!< External input signal parameter */
+} vdc5_input_t;
+
+/***********************    For R_VDC5_SyncControl      ***********************/
+/*! Horizontal/vertical sync signal output and full-screen enable signal select */
+typedef enum {
+    VDC5_RES_VS_IN_SEL_SC0  = 0,    /*!< Sync signal output and full-screen enable signal from scaler 0 */
+    VDC5_RES_VS_IN_SEL_SC1  = 1     /*!< Sync signal output and full-screen enable signal from scaler 1 */
+} vdc5_res_vs_in_sel_t;
+/*! Vsync signal compensation parameter */
+typedef struct {
+    uint16_t        res_vmask;              /*!< Repeated Vsync signal masking period */
+    uint16_t        res_vlack;              /*!< Missing-Sync compensating pulse output wait time */
+} vdc5_vsync_cpmpe_t;
+/*! Sync signal control parameter */
+typedef struct {
+    vdc5_onoff_t                res_vs_sel;     /*!< Vsync signal output select (free-running Vsync on/off control) */
+    vdc5_res_vs_in_sel_t        res_vs_in_sel;  /*!< Horizontal/vertical sync signal output
+                                                     and full-screen enable signal select */
+    uint16_t                    res_fv;         /*!< Free-running Vsync period setting */
+    uint16_t                    res_fh;         /*!< Hsync period setting */
+    uint16_t                    res_vsdly;      /*!< Vsync signal delay control */
+    vdc5_period_rect_t          res_f;          /*!< Full-screen enable signal */
+    const vdc5_vsync_cpmpe_t  * vsync_cpmpe;    /*!< Vsync signal compensation parameter */
+} vdc5_sync_ctrl_t;
+
+/***********************    For R_VDC5_DisplayOutput    ***********************/
+/*! POLA/POLB signal generation mode select */
+typedef enum {
+    VDC5_LCD_TCON_POLMD_NORMAL = 0,         /*!< Normal mode */
+    VDC5_LCD_TCON_POLMD_1X1REV,             /*!< 1x1 reverse mode */
+    VDC5_LCD_TCON_POLMD_1X2REV,             /*!< 1x2 reverse mode */
+    VDC5_LCD_TCON_POLMD_2X2REV,             /*!< 2x2 reverse mode */
+    VDC5_LCD_TCON_POLMD_NUM
+} vdc5_lcd_tcon_polmode_t;
+/*! Signal operating reference select */
+typedef enum {
+    VDC5_LCD_TCON_REFSEL_HSYNC      = 0,    /*!< Hsync signal reference */
+    VDC5_LCD_TCON_REFSEL_OFFSET_H   = 1     /*!< Offset Hsync signal reference */
+} vdc5_lcd_tcon_refsel_t;
+/*! LCD TCON output pin select */
+typedef enum {
+    VDC5_LCD_TCON_PIN_NON = -1,             /*!< Nothing output */
+    VDC5_LCD_TCON_PIN_0,                    /*!< LCD_TCON0 */
+    VDC5_LCD_TCON_PIN_1,                    /*!< LCD_TCON1 */
+    VDC5_LCD_TCON_PIN_2,                    /*!< LCD_TCON2 */
+    VDC5_LCD_TCON_PIN_3,                    /*!< LCD_TCON3 */
+    VDC5_LCD_TCON_PIN_4,                    /*!< LCD_TCON4 */
+    VDC5_LCD_TCON_PIN_5,                    /*!< LCD_TCON5 */
+    VDC5_LCD_TCON_PIN_6,                    /*!< LCD_TCON6 */
+    VDC5_LCD_TCON_PIN_NUM
+} vdc5_lcd_tcon_pin_t;
+/*! LCD TCON timing signal parameter */
+typedef struct {
+    uint16_t                tcon_hsvs;      /*!< Signal pulse start position */
+    uint16_t                tcon_hwvw;      /*!< Pulse width */
+    vdc5_lcd_tcon_polmode_t tcon_md;        /*!< POLA/POLB signal generation mode select */
+    vdc5_lcd_tcon_refsel_t  tcon_hs_sel;    /*!< Signal operating reference select */
+    vdc5_sig_pol_t          tcon_inv;       /*!< Polarity inversion control of signal */
+    vdc5_lcd_tcon_pin_t     tcon_pin;       /*!< LCD TCON output pin select */
+    vdc5_edge_t             outcnt_edge;    /*!< Output phase control of signal */
+} vdc5_lcd_tcon_timing_t;
+/*! Timing signals for driving the LCD panel */
+typedef enum {
+    VDC5_LCD_TCONSIG_STVA_VS = 0,           /*!< STVA/VS */
+    VDC5_LCD_TCONSIG_STVB_VE,               /*!< STVB/VE */
+    VDC5_LCD_TCONSIG_STH_SP_HS,             /*!< STH/SP/HS */
+    VDC5_LCD_TCONSIG_STB_LP_HE,             /*!< STB/LP/HE */
+    VDC5_LCD_TCONSIG_CPV_GCK,               /*!< CPV/GCK */
+    VDC5_LCD_TCONSIG_POLA,                  /*!< POLA */
+    VDC5_LCD_TCONSIG_POLB,                  /*!< POLB */
+    VDC5_LCD_TCONSIG_DE,                    /*!< DE */
+    VDC5_LCD_TCONSIG_NUM
+} vdc5_lcd_tcon_sigsel_t;
+/*! Output format select */
+typedef enum {
+    VDC5_LCD_OUTFORMAT_RGB888 = 0,          /*!< RGB888 */
+    VDC5_LCD_OUTFORMAT_RGB666,              /*!< RGB666 */
+    VDC5_LCD_OUTFORMAT_RGB565,              /*!< RGB565 */
+    VDC5_LCD_OUTFORMAT_SERIAL_RGB,          /*!< Serial RGB */
+    VDC5_LCD_OUTFORMAT_NUM
+} vdc5_lcd_outformat_t;
+/*! Clock frequency control */
+typedef enum {
+    VDC5_LCD_PARALLEL_CLKFRQ_1 = 0,         /*!< 100% speed (parallel RGB) */
+    VDC5_LCD_SERIAL_CLKFRQ_3,               /*!< Triple speed (serial RGB) */
+    VDC5_LCD_SERIAL_CLKFRQ_4,               /*!< Quadruple speed (serial RGB) */
+    VDC5_LCD_SERIAL_CLKFRQ_NUM
+} vdc5_lcd_clkfreqsel_t;
+/*! Scan direction select */
+typedef enum {
+    VDC5_LCD_SERIAL_SCAN_FORWARD   = 0,     /*!< Forward scan */
+    VDC5_LCD_SERIAL_SCAN_REVERSE   = 1      /*!< Reverse scan */
+} vdc5_lcd_scan_t;
+/*! Clock phase adjustment for serial RGB output */
+typedef enum {
+    VDC5_LCD_SERIAL_CLKPHASE_0 = 0,         /*!< 0[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_1,             /*!< 1[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_2,             /*!< 2[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_3,             /*!< 3[clk] */
+    VDC5_LCD_SERIAL_CLKPHASE_NUM
+} vdc5_lcd_clkphase_t;
+/*! Display output configuration parameter */
+typedef struct {
+    uint16_t                        tcon_half;                      /*!< 1/2fH timing */
+    uint16_t                        tcon_offset;                    /*!< Offset Hsync signal timing */
+    const vdc5_lcd_tcon_timing_t  * outctrl[VDC5_LCD_TCONSIG_NUM];  /*!< LCD TCON timing signal parameter */
+    vdc5_edge_t                     outcnt_lcd_edge;                /*!< Output phase control of LCD_DATA23
+                                                                         to LCD_DATA0 pin */
+    vdc5_onoff_t                    out_endian_on;                  /*!< Bit endian change on/off control */
+    vdc5_onoff_t                    out_swap_on;                    /*!< B/R signal swap on/off control */
+    vdc5_lcd_outformat_t            out_format;                     /*!< Output format select */
+    vdc5_lcd_clkfreqsel_t           out_frq_sel;                    /*!< Clock frequency control */
+    vdc5_lcd_scan_t                 out_dir_sel;                    /*!< Scan direction select */
+    vdc5_lcd_clkphase_t             out_phase;                      /*!< Clock phase adjustment
+                                                                         for serial RGB output */
+    uint32_t                        bg_color;                       /*!< Background color in 24-bit RGB color format */
+} vdc5_output_t;
+
+/***********************    For R_VDC5_CallbackISR      ***********************/
+/*! VDC5 interrupt type */
+typedef enum {
+    VDC5_INT_TYPE_S0_VI_VSYNC = 0,      /*!< Vsync signal input to scaler 0 */
+    VDC5_INT_TYPE_S0_LO_VSYNC,          /*!< Vsync signal output from scaler 0 */
+    VDC5_INT_TYPE_S0_VSYNCERR,          /*!< Missing Vsync signal for scaler 0 */
+    VDC5_INT_TYPE_VLINE,                /*!< Specified line signal for panel output in graphics 3 */
+    VDC5_INT_TYPE_S0_VFIELD,            /*!< Field end signal for recording function in scaler 0 */
+    VDC5_INT_TYPE_IV1_VBUFERR,          /*!< Frame buffer write overflow signal for scaler 0 */
+    VDC5_INT_TYPE_IV3_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 0 */
+    VDC5_INT_TYPE_IV5_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 2 */
+    VDC5_INT_TYPE_IV6_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 3 */
+    VDC5_INT_TYPE_S0_WLINE,             /*!< Write specification line signal input to scaling-down control block
+                                            in scaler 0 */
+    VDC5_INT_TYPE_S1_VI_VSYNC,          /*!< Vsync signal input to scaler 1 */
+    VDC5_INT_TYPE_S1_LO_VSYNC,          /*!< Vsync signal output from scaler 1 */
+    VDC5_INT_TYPE_S1_VSYNCERR,          /*!< Missing Vsync signal for scaler 1 */
+    VDC5_INT_TYPE_S1_VFIELD,            /*!< Field end signal for recording function in scaler 1 */
+    VDC5_INT_TYPE_IV2_VBUFERR,          /*!< Frame buffer write overflow signal for scaler 1 */
+    VDC5_INT_TYPE_IV4_VBUFERR,          /*!< Frame buffer read underflow signal for graphics 1 */
+    VDC5_INT_TYPE_S1_WLINE,             /*!< Write specification line signal input to scaling-down control block
+                                            in scaler 1 */
+    VDC5_INT_TYPE_OIR_VI_VSYNC,         /*!< Vsync signal input to output image generator */
+    VDC5_INT_TYPE_OIR_LO_VSYNC,         /*!< Vsync signal output from output image generator */
+    VDC5_INT_TYPE_OIR_VLINE,            /*!< Specified line signal for panel output in output image generator */
+    VDC5_INT_TYPE_OIR_VFIELD,           /*!< Field end signal for recording function in output image generator */
+    VDC5_INT_TYPE_IV7_VBUFERR,          /*!< Frame buffer write overflow signal for output image generator */
+    VDC5_INT_TYPE_IV8_VBUFERR,          /*!< Frame buffer read underflow signal for graphics (OIR) */
+    VDC5_INT_TYPE_NUM                   /*!< The number of VDC5 interrupt types */
+} vdc5_int_type_t;
+/*! Interrupt callback setup parameter */
+typedef struct {
+    vdc5_int_type_t     type;                       /*!< VDC5 interrupt type */
+    void             (* callback)(vdc5_int_type_t); /*!< Interrupt callback function pointer */
+    uint16_t            line_num;                   /*!< Line interrupt set */
+} vdc5_int_t;
+
+/***********************    For R_VDC5_WriteDataControl ***********************/
+/*! Frame buffer writing mode for image processing */
+typedef enum {
+    VDC5_WR_MD_NORMAL = 0,                  /*!< Normal */
+    VDC5_WR_MD_MIRROR,                      /*!< Horizontal mirroring */
+    VDC5_WR_MD_ROT_90DEG,                   /*!< 90 degree rotation */
+    VDC5_WR_MD_ROT_180DEG,                  /*!< 180 degree rotation */
+    VDC5_WR_MD_ROT_270DEG,                  /*!< 270 degree rotation */
+    VDC5_WR_MD_NUM
+} vdc5_wr_md_t;
+/*! Scaling-down and rotation parameter */
+typedef struct {
+    vdc5_period_rect_t  res;                /*!< Image area to be captured */
+    vdc5_onoff_t        res_pfil_sel;       /*!< Prefilter mode select for brightness signals (on/off) */
+    uint16_t            res_out_vw;         /*!< Number of valid lines in vertical direction
+                                                 output by scaling-down control block */
+    uint16_t            res_out_hw;         /*!< Number of valid horizontal pixels
+                                                 output by scaling-down control block */
+    vdc5_onoff_t        adj_sel;            /*!< Handling for lack of last-input line (on/off) */
+    vdc5_wr_md_t        res_ds_wr_md;       /*!< Frame buffer writing mode for image processing */
+} vdc5_scalingdown_rot_t;
+/*! Frame buffer swap setting */
+typedef enum {
+    VDC5_WR_RD_WRSWA_NON = 0,           /*!< Not swapped: 1-2-3-4-5-6-7-8 */
+    VDC5_WR_RD_WRSWA_8BIT,              /*!< Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+    VDC5_WR_RD_WRSWA_16BIT,             /*!< Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+    VDC5_WR_RD_WRSWA_16_8BIT,           /*!< Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+    VDC5_WR_RD_WRSWA_32BIT,             /*!< Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+    VDC5_WR_RD_WRSWA_32_8BIT,           /*!< Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+    VDC5_WR_RD_WRSWA_32_16BIT,          /*!< Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+    VDC5_WR_RD_WRSWA_32_16_8BIT,        /*!< Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+    VDC5_WR_RD_WRSWA_NUM
+} vdc5_wr_rd_swa_t;
+/*! Frame buffer video-signal writing format */
+typedef enum {
+    VDC5_RES_MD_YCBCR422 = 0,               /*!< YCbCr422 */
+    VDC5_RES_MD_RGB565,                     /*!< RGB565 */
+    VDC5_RES_MD_RGB888,                     /*!< RGB888 */
+    VDC5_RES_MD_YCBCR444,                   /*!< YCbCr444 */
+    VDC5_RES_MD_NUM
+} vdc5_res_md_t;
+/*! Transfer burst length */
+typedef enum {
+    VDC5_BST_MD_32BYTE = 0,                 /*!< 32-byte transfer (4 bursts) */
+    VDC5_BST_MD_128BYTE                     /*!< 128-byte transfer (16 bursts) */
+} vdc5_bst_md_t;
+/*! Field operating mode select */
+typedef enum {
+    VDC5_RES_INTER_PROGRESSIVE  = 0,        /*!< Progressive */
+    VDC5_RES_INTER_INTERLACE    = 1         /*!< Interlace */
+} vdc5_res_inter_t;
+/*! Writing rate */
+typedef enum {
+    VDC5_RES_FS_RATE_PER1 = 0,              /* 1/1 an input signal */
+    VDC5_RES_FS_RATE_PER2,                  /* 1/2 an input signal */
+    VDC5_RES_FS_RATE_PER4,                  /* 1/4 an input signal */
+    VDC5_RES_FS_RATE_PER8,                  /* 1/8 an input signal */
+    VDC5_RES_FS_RATE_NUM
+} vdc5_res_fs_rate_t;
+/*! Write field select */
+typedef enum {
+    VDC5_RES_FLD_SEL_TOP    = 0,            /*!< Top field */
+    VDC5_RES_FLD_SEL_BOTTOM = 1             /*!< Bottom field */
+} vdc5_res_fld_sel_t;
+/*! Data write control parameter */
+typedef struct {
+    vdc5_scalingdown_rot_t  scalingdown_rot;/*!< Scaling-down and rotation parameter */
+    vdc5_wr_rd_swa_t        res_wrswa;      /*!< Swap setting in frame buffer writing */
+    vdc5_res_md_t           res_md;         /*!< Frame buffer video-signal writing format */
+    vdc5_bst_md_t           res_bst_md;     /*!< Transfer burst length for frame buffer writing */
+    vdc5_res_inter_t        res_inter;      /*!< Field operating mode select */
+    vdc5_res_fs_rate_t      res_fs_rate;    /*!< Writing rate */
+    vdc5_res_fld_sel_t      res_fld_sel;    /*!< Write field select */
+    vdc5_onoff_t            res_dth_on;     /*!< Dither correction on/off */
+    void                  * base;           /*!< Frame buffer base address */
+    uint32_t                ln_off;         /*!< Frame buffer line offset address [byte] */
+    uint32_t                flm_num;        /*!< Number of frames of buffer to be written to (res_flm_num + 1) */
+    uint32_t                flm_off;        /*!< Frame buffer frame offset address [byte] */
+    void                  * btm_base;       /*!< Frame buffer base address for bottom */
+} vdc5_write_t;
+
+/***********************  For R_VDC5_ChangeWriteProcess ***********************/
+/*! Data write change parameter */
+typedef struct {
+    vdc5_scalingdown_rot_t  scalingdown_rot;/*!< Scaling-down and rotation parameter */
+} vdc5_write_chg_t;
+
+/***********************  For R_VDC5_ReadDataControl    ***********************/
+/*! Line offset address direction of the frame buffer */
+typedef enum {
+    VDC5_GR_LN_OFF_DIR_INC = 0,             /*!< Increments the address by the line offset address */
+    VDC5_GR_LN_OFF_DIR_DEC                  /*!< Decrements the address by the line offset address */
+} vdc5_gr_ln_off_dir_t;
+/*! Frame buffer address setting signal */
+typedef enum {
+    VDC5_GR_FLM_SEL_SCALE_DOWN = 0,         /*!< Links to scaling-down process */
+    VDC5_GR_FLM_SEL_FLM_NUM,                /*!< Selects frame 0 (graphics display) */
+    VDC5_GR_FLM_SEL_DISTORTION,             /*!< Links to distortion correction */
+    VDC5_GR_FLM_SEL_POINTER_BUFF,           /*!< Links to pointer buffer */
+    VDC5_GR_FLM_SEL_NUM
+} vdc5_gr_flm_sel_t;
+/*! Size of the frame buffer to be read */
+typedef struct {
+    uint16_t                in_vw;          /*!< Number of lines in a frame */
+    uint16_t                in_hw;          /*!< Width of the horizontal valid period */
+} vdc5_width_read_fb_t;
+/*! Format of the frame buffer read signal */
+typedef enum {
+    VDC5_GR_FORMAT_RGB565 = 0,              /*!< RGB565 */
+    VDC5_GR_FORMAT_RGB888,                  /*!< RGB888 */
+    VDC5_GR_FORMAT_ARGB1555,                /*!< ARGB1555 */
+    VDC5_GR_FORMAT_ARGB4444,                /*!< ARGB4444 */
+    VDC5_GR_FORMAT_ARGB8888,                /*!< ARGB8888 */
+    VDC5_GR_FORMAT_CLUT8,                   /*!< CLUT8 */
+    VDC5_GR_FORMAT_CLUT4,                   /*!< CLUT4 */
+    VDC5_GR_FORMAT_CLUT1,                   /*!< CLUT1 */
+    VDC5_GR_FORMAT_YCBCR422,                /*!< YCbCr422: This setting is prohibited for the graphics 2 and 3 */
+    VDC5_GR_FORMAT_YCBCR444,                /*!< YCbCr444: This setting is prohibited for the graphics 2 and 3 */
+    VDC5_GR_FORMAT_RGBA5551,                /*!< RGBA5551 */
+    VDC5_GR_FORMAT_RGBA8888,                /*!< RGBA8888 */
+    VDC5_GR_FORMAT_NUM                      /*!< The number of signal formats */
+} vdc5_gr_format_t;
+/*! Swapping of data read from buffer in the YCbCr422 format */
+typedef enum {
+    VDC5_GR_YCCSWAP_CBY0CRY1 = 0,
+    VDC5_GR_YCCSWAP_Y0CBY1CR,
+    VDC5_GR_YCCSWAP_CRY0CBY1,
+    VDC5_GR_YCCSWAP_Y0CRY1CB,
+    VDC5_GR_YCCSWAP_Y1CRY0CB,
+    VDC5_GR_YCCSWAP_CRY1CBY0,
+    VDC5_GR_YCCSWAP_Y1CBY0CR,
+    VDC5_GR_YCCSWAP_CBY1CRY0,
+    VDC5_GR_YCCSWAP_NUM
+} vdc5_gr_ycc_swap_t;
+/*! Data read control parameter */
+typedef struct {
+    vdc5_gr_ln_off_dir_t            gr_ln_off_dir;  /*!< Line offset address direction of the frame buffer */
+    vdc5_gr_flm_sel_t               gr_flm_sel;     /*!< Frame buffer address setting signal */
+    vdc5_onoff_t                    gr_imr_flm_inv; /*!< Frame buffer number for distortion correction */
+    vdc5_bst_md_t                   gr_bst_md;      /*!< Frame buffer burst transfer mode */
+    void                          * gr_base;        /*!< Frame buffer base address */
+    uint32_t                        gr_ln_off;      /*!< Frame buffer line offset address */
+    const vdc5_width_read_fb_t    * width_read_fb;  /*!< Size of the frame buffer to be read */
+    vdc5_onoff_t                    adj_sel;        /*!< Folding handling (on/off) */
+    vdc5_gr_format_t                gr_format;      /*!< Format of the frame buffer read signal */
+    vdc5_gr_ycc_swap_t              gr_ycc_swap;    /*!< Swapping of data read from buffer
+                                                         in the YCbCr422 format */
+    vdc5_wr_rd_swa_t                gr_rdswa;       /*!< Swap setting in frame buffer reading */
+    vdc5_period_rect_t              gr_grc;         /*!< Graphics display area */
+} vdc5_read_t;
+
+/******************************* For R_VDC5_ChangeReadProcess       *******************************/
+/*! The type of graphics display modes */
+typedef enum {
+    VDC5_DISPSEL_IGNORED    = -1,       /*!< Ignored */
+    VDC5_DISPSEL_BACK       = 0,        /*!< Background color display */
+    VDC5_DISPSEL_LOWER      = 1,        /*!< Lower-layer graphics display */
+    VDC5_DISPSEL_CURRENT    = 2,        /*!< Current graphics display */
+    VDC5_DISPSEL_BLEND      = 3,        /*!< Blended display of lower-layer graphics and current graphics */
+    VDC5_DISPSEL_NUM        = 4         /*!< The number of graphics display modes */
+} vdc5_gr_disp_sel_t;
+/*! Data read change parameter */
+typedef struct {
+    void                          * gr_base;        /*!< Frame buffer base address */
+    const vdc5_width_read_fb_t    * width_read_fb;  /*!< Size of the frame buffer to be read */
+    const vdc5_period_rect_t      * gr_grc;         /*!< Graphics display area */
+    const vdc5_gr_disp_sel_t      * gr_disp_sel;    /*!< Graphics display mode */
+} vdc5_read_chg_t;
+/*! Data read change more parameter */
+typedef struct {
+    void                          * gr_base;        /*!< Frame buffer base address */
+    vdc5_width_read_fb_t    	  * width_read_fb;  /*!< Size of the frame buffer to be read */
+    vdc5_period_rect_t      	  * gr_grc;         /*!< Graphics display area */
+    vdc5_gr_disp_sel_t			  * gr_disp_sel;    /*!< Graphics display mode */
+} vdc5_chg_read_chg_t;
+
+/******************************* For R_VDC5_StartProcess            *******************************/
+/*! Data write/read start parameter */
+typedef struct {
+    const vdc5_gr_disp_sel_t      * gr_disp_sel;    /*!< Graphics display mode */
+} vdc5_start_t;
+
+/******************************* For R_VDC5_VideoNoiseReduction     *******************************/
+/*! TAP select */
+typedef enum {
+    VDC5_NR_TAPSEL_1 = 0,           /*!< Adjacent pixel */
+    VDC5_NR_TAPSEL_2,               /*!< 2 adjacent pixels */
+    VDC5_NR_TAPSEL_3,               /*!< 3 adjacent pixels */
+    VDC5_NR_TAPSEL_4,               /*!< 4 adjacent pixels */
+    VDC5_NR_TAPSEL_NUM
+} vdc5_nr_tap_t;
+/*! Noise reduction gain adjustment */
+typedef enum {
+    VDC5_NR_GAIN_1_2 = 0,           /*!< 1/2 */
+    VDC5_NR_GAIN_1_4,               /*!< 1/4 */
+    VDC5_NR_GAIN_1_8,               /*!< 1/8 */
+    VDC5_NR_GAIN_1_16,              /*!< 1/16 */
+    VDC5_NR_GAIN_NUM
+} vdc5_nr_gain_t;
+/*! Noise reduction parameter */
+typedef struct {
+    vdc5_nr_tap_t   nr1d_tap;       /*!< TAP select */
+    uint32_t        nr1d_th;        /*!< Maximum value of coring (absolute value) */
+    vdc5_nr_gain_t  nr1d_gain;      /*!< Noise reduction gain adjustment */
+} vdc5_nr_param_t;
+/*! Noise reduction setup parameter */
+typedef struct {
+    vdc5_nr_param_t     y;          /*!< Y/G signal noise reduction parameter */
+    vdc5_nr_param_t     cb;         /*!< Cb/B signal noise reduction parameter */
+    vdc5_nr_param_t     cr;         /*!< Cr/R signal noise reduction parameter */
+} vdc5_noise_reduction_t;
+
+/******************************* For R_VDC5_ImageColorMatrix        *******************************/
+/*! Color matrix module */
+typedef enum {
+    VDC5_COLORMTX_IMGCNT = 0,           /*!< Input Controller (input video signal) */
+    VDC5_COLORMTX_ADJ_0,                /*!< Image quality improver 0 (scaler 0 output) */
+    VDC5_COLORMTX_ADJ_1,                /*!< Image quality improver 1 (scaler 1 output) */
+    VDC5_COLORMTX_NUM
+} vdc5_colormtx_module_t;
+/*! Operating mode */
+typedef enum {
+    VDC5_COLORMTX_GBR_GBR = 0,          /*!< GBR to GBR */
+    VDC5_COLORMTX_GBR_YCBCR,            /*!< GBR to YCbCr */
+    VDC5_COLORMTX_YCBCR_GBR,            /*!< YCbCr to GBR */
+    VDC5_COLORMTX_YCBCR_YCBCR,          /*!< YCbCr to YCbCr */
+    VDC5_COLORMTX_MODE_NUM              /*!< The number of operating modes */
+} vdc5_colormtx_mode_t;
+/*! Color matrix offset (DC) adjustment */
+typedef enum {
+    VDC5_COLORMTX_OFFST_YG = 0,         /*!< YG */
+    VDC5_COLORMTX_OFFST_B,              /*!< B */
+    VDC5_COLORMTX_OFFST_R,              /*!< R */
+    VDC5_COLORMTX_OFFST_NUM             /*!< The number of the color matrix DC offset values */
+} vdc5_colormtx_offset_t;
+/*! Color matrix signal gain adjustment */
+typedef enum {
+    VDC5_COLORMTX_GAIN_GG = 0,          /*!< GG */
+    VDC5_COLORMTX_GAIN_GB,              /*!< GB */
+    VDC5_COLORMTX_GAIN_GR,              /*!< GR */
+    VDC5_COLORMTX_GAIN_BG,              /*!< BG */
+    VDC5_COLORMTX_GAIN_BB,              /*!< BB */
+    VDC5_COLORMTX_GAIN_BR,              /*!< BR */
+    VDC5_COLORMTX_GAIN_RG,              /*!< RG */
+    VDC5_COLORMTX_GAIN_RB,              /*!< RB */
+    VDC5_COLORMTX_GAIN_RR,              /*!< RR */
+    VDC5_COLORMTX_GAIN_NUM              /*!< The number of the color matrix gain values */
+} vdc5_colormtx_gain_t;
+/*! Color matrix setup parameter */
+typedef struct {
+    vdc5_colormtx_module_t  module;                         /*!< Color matrix module */
+    vdc5_colormtx_mode_t    mtx_mode;                       /*!< Operating mode */
+    uint16_t                offset[VDC5_COLORMTX_OFFST_NUM];/*!< Offset (DC) adjustment of Y/G, B, and R signal */
+    uint16_t                gain[VDC5_COLORMTX_GAIN_NUM];   /*!< GG, GB, GR, BG, BB, BR, RG, RB, and RR signal
+                                                                 gain adjustment */
+} vdc5_color_matrix_t;
+
+/******************************* For R_VDC5_ImageEnhancement        *******************************/
+/*! Image quality improver ID */
+typedef enum {
+    VDC5_IMG_IMPRV_0 = 0,           /*!< Image quality improver 0 */
+    VDC5_IMG_IMPRV_1,               /*!< Image quality improver 1 */
+    VDC5_IMG_IMPRV_NUM              /*!< The number of image quality improvers */
+} vdc5_imgimprv_id_t;
+
+/*! Sharpness band */
+typedef enum {
+    VDC5_IMGENH_SHARP_H1 = 0,       /*!< H1: Adjacent pixel used as reference */
+    VDC5_IMGENH_SHARP_H2,           /*!< H2: Second adjacent pixel used as reference */
+    VDC5_IMGENH_SHARP_H3,           /*!< H3: Third adjacent pixel used as reference */
+    VDC5_IMGENH_SHARP_NUM           /*!< The number of horizontal sharpness bands */
+} vdc5_img_enh_sh_t;
+/*! Sharpness control parameter */
+typedef struct {
+    uint8_t     shp_clip_o;         /*!< Sharpness correction value clipping (on the overshoot side) */
+    uint8_t     shp_clip_u;         /*!< Sharpness correction value clipping (on the undershoot side) */
+    uint8_t     shp_gain_o;         /*!< Sharpness edge amplitude value gain (on the overshoot side) */
+    uint8_t     shp_gain_u;         /*!< Sharpness edge amplitude value gain (on the undershoot side) */
+    uint8_t     shp_core;           /*!< Active sharpness range */
+} vdc5_sharpness_ctrl_t;
+/*! Sharpness setup parameter */
+typedef struct {
+    vdc5_onoff_t            shp_h2_lpf_sel;                     /*!< LPF selection for folding prevention
+                                                                     before H2 edge detection */
+    vdc5_sharpness_ctrl_t   hrz_sharp[VDC5_IMGENH_SHARP_NUM];   /*!< Sharpness control parameter (H1, H2, and H3) */
+} vdc5_enhance_sharp_t;
+/*! LTI band */
+typedef enum {
+    VDC5_IMGENH_LTI1 = 0,           /*!< H2: Second adjacent pixel used as reference */
+    VDC5_IMGENH_LTI2,               /*!< H4: Fourth adjacent pixel used as reference */
+    VDC5_IMGENH_LTI_NUM             /*!< The number of horizontal LTI bands */
+} vdc5_img_enh_lti_t;
+/*! Median filter reference pixel select */
+typedef enum {
+    VDC5_LTI_MDFIL_SEL_ADJ2 = 0,    /*!< Second adjacent pixel selected as reference */
+    VDC5_LTI_MDFIL_SEL_ADJ1         /*!< Adjacent pixel selected as reference */
+} vdc5_lti_mdfil_sel_t;
+/*! LTI control parameter */
+typedef struct {
+    uint8_t     lti_inc_zero;       /*!< Median filter LTI correction threshold */
+    uint8_t     lti_gain;           /*!< LTI edge amplitude value gain */
+    uint8_t     lti_core;           /*!< LTI coring (maximum core value of 255) */
+} vdc5_lti_ctrl_t;
+/*! Luminance Transient Improvement setup parameter */
+typedef struct {
+    vdc5_onoff_t            lti_h2_lpf_sel;             /*!< LPF selection for folding prevention
+                                                             before H2 edge detection */
+    vdc5_lti_mdfil_sel_t    lti_h4_median_tap_sel;      /*!< Median filter reference pixel select */
+    vdc5_lti_ctrl_t         lti[VDC5_IMGENH_LTI_NUM];   /*!< LTI control parameter (H2 and H4) */
+} vdc5_enhance_lti_t;
+
+/******************************* For R_VDC5_ImageBlackStretch       *******************************/
+/*! Black stretch setup parameter */
+typedef struct {
+    uint16_t    bkstr_st;           /*!< Black stretch start point */
+    uint16_t    bkstr_d;            /*!< Black stretch depth */
+    uint16_t    bkstr_t1;           /*!< Black stretch time constant (T1) */
+    uint16_t    bkstr_t2;           /*!< Black stretch time constant (T2) */
+} vdc5_black_t;
+
+/******************************* For R_VDC5_AlphaBlending           *******************************/
+/*! Alpha signal of the ARGB1555/ARGB5551 format */
+typedef struct {
+    uint8_t     gr_a0;                  /*!< Alpha signal when alpha is set to '0' */
+    uint8_t     gr_a1;                  /*!< Alpha signal when alpha is set to '1' */
+} vdc5_alpha_argb1555_t;
+/*! Alpha blending in one-pixel units */
+typedef struct {
+    vdc5_onoff_t    gr_acalc_md;        /*!< Premultiplication processing at alpha blending
+                                             in one-pixel units (on/off) */
+} vdc5_alpha_pixel_t;
+/*! Alpha blending setup parameter */
+typedef struct {
+    const vdc5_alpha_argb1555_t   * alpha_1bit; /*!< Alpha signal of the ARGB1555/ARGB5551 format */
+    const vdc5_alpha_pixel_t      * alpha_pixel;/*!< Premultiplication processing at alpha blending in one-pixel */
+} vdc5_alpha_blending_t;
+
+/******************************* For R_VDC5_AlphaBlendingRect       *******************************/
+/*! Parameter for alpha blending in a rectangular area */
+typedef struct {
+    int16_t         gr_arc_coef;        /*!< Alpha coefficient for alpha blending in a rectangular area
+                                             (-255 to 255) */
+    uint8_t         gr_arc_rate;        /*!< Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
+    uint8_t         gr_arc_def;         /*!< Initial alpha value for alpha blending in a rectangular area */
+    vdc5_onoff_t    gr_arc_mul;         /*!< Multiplication processing with current alpha at alpha blending
+                                             in a rectangular area (on/off) */
+} vdc5_alpha_rect_t;
+/*! Selection of lower-layer plane in scaler */
+typedef struct {
+    vdc5_onoff_t    gr_vin_scl_und_sel; /*!< Selection of lower-layer plane in scaler
+                                             - VDC5_OFF: Selects graphics 0 as lower-layer graphics
+                                                         and graphics 1 as current graphics
+                                             - VDC5_ON: Selects graphics 1 as lower-layer graphics
+                                                        and graphics 0 as current graphics */
+} vdc5_scl_und_sel_t;
+/*! Setup parameter for alpha blending in a rectangular area */
+typedef struct {
+    const vdc5_pd_disp_rect_t * gr_arc;     /*!< Rectangular area subjected to alpha blending */
+    const vdc5_alpha_rect_t   * alpha_rect; /*!< Parameter for alpha blending in a rectangular area */
+    const vdc5_scl_und_sel_t  * scl_und_sel;/*!< Selection of lower-layer plane in scaler */
+} vdc5_alpha_blending_rect_t;
+
+/******************************* For R_VDC5_Chromakey               *******************************/
+/*! Chroma-key setup parameter */
+typedef struct {
+    uint32_t    ck_color;       /*!< RGB/CLUT signal for RGB/CLUT-index chroma-key processing */
+    uint32_t    rep_color;      /*!< Replaced ARGB signal after RGB/CLUT-index chroma-key processing */
+    uint8_t     rep_alpha;      /*!< Replaced alpha signal after RGB-index chroma-key processing (in 8 bits) */
+} vdc5_chromakey_t;
+
+/******************************* For R_VDC5_CLUT                    *******************************/
+/*! CLUT setup parameter */
+typedef struct {
+    uint32_t            color_num;  /*!< The number of colors in CLUT */
+    const uint32_t    * clut;       /*!< Address of the area storing the CLUT data (in ARGB8888 format) */
+} vdc5_clut_t;
+
+/******************************* For R_VDC5_DisplayCalibration      *******************************/
+/*! Correction circuit sequence control */
+typedef enum {
+    VDC5_CALIBR_ROUTE_BCG = 0,          /*!< Brightness -> contrast -> gamma correction */
+    VDC5_CALIBR_ROUTE_GBC               /*!< Gamma correction -> brightness -> contrast */
+} vdc5_calibr_route_t;
+/*! Brightness (DC) adjustment parameter */
+typedef struct {
+    uint16_t    pbrt_g;                 /*!< Brightness (DC) adjustment of G signal */
+    uint16_t    pbrt_b;                 /*!< Brightness (DC) adjustment of B signal */
+    uint16_t    pbrt_r;                 /*!< Brightness (DC) adjustment of R signal */
+} vdc5_calibr_bright_t;
+/*! Contrast (gain) adjustment parameter */
+typedef struct {
+    uint8_t     cont_g;                 /*!< Contrast (gain) adjustment of G signal */
+    uint8_t     cont_b;                 /*!< Contrast (gain) adjustment of B signal */
+    uint8_t     cont_r;                 /*!< Contrast (gain) adjustment of R signal */
+} vdc5_calibr_contrast_t;
+/*! Panel dither operation mode */
+typedef enum {
+    VDC5_PDTH_MD_TRU = 0,               /*!< Truncate */
+    VDC5_PDTH_MD_RDOF,                  /*!< Round-off */
+    VDC5_PDTH_MD_2X2,                   /*!< 2 x 2 pattern dither */
+    VDC5_PDTH_MD_RAND,                  /*!< Random pattern dither */
+    VDC5_PDTH_MD_NUM
+} vdc5_panel_dither_md_t;
+/*! Panel dithering parameter */
+typedef struct {
+    vdc5_panel_dither_md_t  pdth_sel;   /*!< Panel dither operation mode */
+    uint8_t                 pdth_pa;    /*!< Pattern value (A) of 2x2 pattern dither */
+    uint8_t                 pdth_pb;    /*!< Pattern value (B) of 2x2 pattern dither */
+    uint8_t                 pdth_pc;    /*!< Pattern value (C) of 2x2 pattern dither */
+    uint8_t                 pdth_pd;    /*!< Pattern value (D) of 2x2 pattern dither */
+} vdc5_calibr_dither_t;
+/*! Display calibration parameter */
+typedef struct {
+    vdc5_calibr_route_t             route;          /*!< Correction circuit sequence control */
+    const vdc5_calibr_bright_t    * bright;         /*!< Brightness (DC) adjustment parameter */
+    const vdc5_calibr_contrast_t  * contrast;       /*!< Contrast (gain) adjustment parameter */
+    const vdc5_calibr_dither_t    * panel_dither;   /*!< Panel dithering parameter */
+} vdc5_disp_calibration_t;
+
+/******************************* For R_VDC5_GammaCorrection         *******************************/
+/*! Gamma correction setup parameter */
+typedef struct {
+    const uint16_t    * gam_g_gain;     /*!< Gain adjustment of area 0 to 31 of G signal */
+    const uint8_t     * gam_g_th;       /*!< Start threshold of area 1 to 31 of G signal */
+    const uint16_t    * gam_b_gain;     /*!< Gain adjustment of area 0 to 31 of B signal */
+    const uint8_t     * gam_b_th;       /*!< Start threshold of area 1 to 31 of B signal */
+    const uint16_t    * gam_r_gain;     /*!< Gain adjustment of area 0 to 31 of R signal */
+    const uint8_t     * gam_r_th;       /*!< Start threshold of area 1 to 31 of R signal */
+} vdc5_gamma_correction_t;
+
+
+/******************************************************************************
+Exported global variables
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+vdc5_error_t R_VDC5_Initialize(
+    const vdc5_channel_t        ch,
+    const vdc5_init_t   * const param,
+    void               (* const init_func)(uint32_t),
+    const uint32_t              user_num);
+vdc5_error_t R_VDC5_Terminate(const vdc5_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num);
+vdc5_error_t R_VDC5_VideoInput(const vdc5_channel_t ch, const vdc5_input_t * const param);
+vdc5_error_t R_VDC5_SyncControl(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+vdc5_error_t R_VDC5_DisplayOutput(const vdc5_channel_t ch, const vdc5_output_t * const param);
+vdc5_error_t R_VDC5_CallbackISR(const vdc5_channel_t ch, const vdc5_int_t * const param);
+vdc5_error_t R_VDC5_WriteDataControl(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param);
+vdc5_error_t R_VDC5_ChangeWriteProcess(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t   * const param);
+vdc5_error_t R_VDC5_ReadDataControl(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_read_t   * const param);
+vdc5_error_t R_VDC5_ChangeReadProcess(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param);
+vdc5_error_t R_VDC5_StartProcess(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param);
+vdc5_error_t R_VDC5_StopProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t R_VDC5_ReleaseDataControl(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t R_VDC5_VideoNoiseReduction(
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      nr1d_on,
+    const vdc5_noise_reduction_t    * const param);
+vdc5_error_t R_VDC5_ImageColorMatrix(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
+vdc5_error_t R_VDC5_ImageEnhancement(
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area);
+vdc5_error_t R_VDC5_ImageBlackStretch(
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param);
+vdc5_error_t R_VDC5_AlphaBlending(
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param);
+vdc5_error_t R_VDC5_AlphaBlendingRect(
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param);
+vdc5_error_t R_VDC5_Chromakey(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param);
+vdc5_error_t R_VDC5_CLUT(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_clut_t * const param);
+vdc5_error_t R_VDC5_DisplayCalibration(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
+vdc5_error_t R_VDC5_GammaCorrection(
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      gam_on,
+    const vdc5_gamma_correction_t   * const param);
+
+void (*R_VDC5_GetISR(const vdc5_channel_t ch, const vdc5_int_type_t type))(const uint32_t int_sense);
+
+
+#ifdef  __cplusplus
+}
+#endif  /* __cplusplus */
+
+
+#endif  /* R_VDC5_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdc5/include/r_vdc5_user.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,104 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_user.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver user-defined header
+******************************************************************************/
+
+#ifndef R_VDC5_USER_H
+#define R_VDC5_USER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Compilation switch to enable parameter check functions<br>
+    If this definition is enabled, the parameter check in each API function will be performed. */
+#define R_VDC5_CHECK_PARAMETERS
+
+
+/*! GBR to YCbCr conversion <br>
+ *  Matrix coefficient (typical value) for SMPTE 293M
+ *  - Y  =  0.299 * R + 0.587 * G + 0.114 * B
+ *  - Cb = -0.169 * R - 0.331 * G + 0.500 * B
+ *  - Cr =  0.500 * R - 0.419 * G - 0.081 * B
+ *  @note
+ *      Coefficient values are represented in 11-bit two's complement integer
+ *      - DEFINITION = int(COEF * 256 + 0.5)
+ */
+typedef enum {
+    VDC5_COLORCONV_Y_R  = (77u),
+    VDC5_COLORCONV_Y_G  = (150u),
+    VDC5_COLORCONV_Y_B  = (29u),
+    VDC5_COLORCONV_CB_R = (2005u),
+    VDC5_COLORCONV_CB_G = (1963u),
+    VDC5_COLORCONV_CB_B = (128u),
+    VDC5_COLORCONV_CR_R = (128u),
+    VDC5_COLORCONV_CR_G = (1941u),
+    VDC5_COLORCONV_CR_B = (2027u)
+} vdc5_colcnv_rgb_ycbcr_t;
+
+/*! YCbCr to GBR conversion <br>
+ *  Matrix coefficient (typical value) for SMPTE 293M
+ *  - G = 1.0 * Y - 0.344 * Cb - 0.714 * Cr
+ *  - B = 1.0 * Y + 1.772 * Cb +   0.0 * Cr
+ *  - R = 1.0 * Y +   0.0 * Cb + 1.402 * Cr
+ *  @note
+ *      Coefficient values are represented in 11-bit two's complement integer
+ *      - DEFINITION = int(COEF * 256 + 0.5)
+ */
+typedef enum {
+    VDC5_COLORCONV_G_Y  = (256u),
+    VDC5_COLORCONV_G_CB = (1960u),
+    VDC5_COLORCONV_G_CR = (1865u),
+    VDC5_COLORCONV_B_Y  = (256u),
+    VDC5_COLORCONV_B_CB = (454u),
+    VDC5_COLORCONV_B_CR = (0u),
+    VDC5_COLORCONV_R_Y  = (256u),
+    VDC5_COLORCONV_R_CB = (0u),
+    VDC5_COLORCONV_R_CR = (359u)
+} vdc5_colcnv_ycbcr_rgb_t;
+
+/*! Color matrix DC offset typical value */
+#define     VDC5_COLORCONV_DC_OFFSET        (128u)
+/*! Color matrix coefficient value that represents one times */
+#define     VDC5_COLORCONV_1TIMES_GAIN      (256u)
+
+/*! 1usec wait cycle for LVDS PLL */
+#define     VDC5_LVDS_PLL_WAIT_CYCLE        (38u)
+/*! 200usec wait counter for LVDS PLL */
+#define     VDC5_LVDS_PLL_WAIT_200USEC      (13400u)
+
+
+#endif  /* R_VDC5_USER_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdc5/src/r_vdc5.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1225 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver API function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+#include    "r_vdc5_shared_param.h"
+#include    "r_vdc5_check_parameter.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_scaling_type_t ConvertRwProcId2SclId(const vdc5_layer_id_t layer_id);
+static vdc5_graphics_type_t ConvertRwProcId2GrId(const vdc5_layer_id_t layer_id);
+
+
+/**************************************************************************//**
+ * @brief       VDC5 driver initialization
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Initializes the VDC5 driver's internal variables.
+ *              - Calls the user-defined function specified in init_func.
+ *              - Sets up and enables the VDC5's panel clock.
+ *              - Sets up and enables the LVDS only if LVDS is used.
+ *              - Disables all the VDC5 interrupts.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Initialization parameter
+ * @param[in]   init_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Initialize (
+    const vdc5_channel_t        ch,
+    const vdc5_init_t   * const param,
+    void               (* const init_func)(uint32_t),
+    const uint32_t              user_num)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_InitializeCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmInit(ch);
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LVDS_CLK);
+        if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+            /* The LVDS PLL clock has been already set. */
+            if (param->lvds != NULL) {
+                ret = VDC5_ERR_RESOURCE_LVDS_CLK;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetInitParam(ch, param);
+
+        /* Callback function */
+        if (init_func != 0) {
+            init_func(user_num);
+        }
+
+        VDC5_Initialize(ch, param);
+
+        /* Disable all VDC5 interrupts */
+        VDC5_Int_Disable(ch);
+
+        VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_PANEL_CLK, VDC5_RESOURCE_ST_VALID);
+        if (param->lvds != NULL) {
+            VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_LVDS_CLK, VDC5_RESOURCE_ST_VALID);
+        }
+    }
+    return ret;
+}   /* End of function R_VDC5_Initialize() */
+
+/**************************************************************************//**
+ * @brief       VDC5 driver termination
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Disables all the VDC5 interrupts.
+ *              - Disables the VDC5 panel clock.
+ *              - Disables the LVDS if one is used and becomes unnecessary as the result of calling this function.
+ *              - Calls the user-defined function specified in quit_func.
+ * @param[in]   ch                      : Channel
+ * @param[in]   quit_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Terminate (const vdc5_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num)
+{
+    vdc5_error_t    ret;
+    vdc5_onoff_t    lvds_ref;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_TerminateCheckPrm(ch);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetTerminate(ch);
+
+        /* Disable all VDC5 interrupts */
+        VDC5_Int_Disable(ch);
+
+        VDC5_Terminate(ch);
+
+        VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_PANEL_CLK, VDC5_RESOURCE_ST_INVALID);
+
+        lvds_ref = VDC5_ShrdPrmGetLvdsClkRef();
+        if (lvds_ref == VDC5_OFF) {     /* LVDS PLL clock is not referred. */
+            VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_LVDS_CLK, VDC5_RESOURCE_ST_INVALID);
+        }
+
+        /* Callback function */
+        if (quit_func != 0) {
+            quit_func(user_num);
+        }
+    }
+    return ret;
+}   /* End of function R_VDC5_Terminate() */
+
+/**************************************************************************//**
+ * @brief       Video input setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Selects the video input.
+ *              - Sets up the phase timing of the input signals.
+ *              - Performs delay control on the sync signal for the video inputs.
+ *              - Sets up the parameters for the external input video signals only when they are used.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_VideoInput (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+    vdc5_error_t ret;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_VideoInputCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetInputParam(ch, param);
+
+        /* Setting VDC5 registers */
+        VDC5_VideoInput(ch, param);
+
+        VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_VIDEO_IN, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_VideoInput() */
+
+/**************************************************************************//**
+ * @brief       Sync control setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Selects the vertical sync signal.
+ *              - Sets up the period of the sync signal.
+ *              - Sets up the delay of the vertical sync signal.
+ *              - Sets up the full-screen enable signal.
+ *              - Sets up the compensation for the vertical sync signal.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Sync control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_SyncControl (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_SyncControlCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_CLK;
+        }
+    }
+    if (ret == VDC5_OK) {
+        if (param->res_vs_sel == VDC5_OFF) {
+            /* External input Vsync signal is selected. */
+            if (param->res_vs_in_sel == VDC5_RES_VS_IN_SEL_SC0) {
+                /* Scaler 0 */
+                rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+            } else {
+                /* Scaler 1 */
+                rsrc_state = VDC5_ShrdPrmGetResource(
+                                 ((ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0),
+                                 VDC5_RESOURCE_VIDEO_IN);
+            }
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+                ret = VDC5_ERR_RESOURCE_INPUT;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetSyncParam(ch, param);
+
+        /* Setting VDC5 registers */
+        VDC5_SyncControl(ch, param);
+
+        VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_VSYNC, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_SyncControl() */
+
+/**************************************************************************//**
+ * @brief       Display output setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the timing signals for driving the LCD panel.
+ *              - Sets up the phase, data sequence, and format of the LCD panel output data.
+ *              - Sets up the background color.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_DisplayOutput (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_DisplayOutputCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_CLK;
+        } else {
+            rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VSYNC);
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+                ret = VDC5_ERR_RESOURCE_VSYNC;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetOutputParam(ch, param);
+
+        /* Setting VDC5 registers */
+        VDC5_DisplayOutput(ch, param);
+
+        VDC5_ShrdPrmSetResource(ch, VDC5_RESOURCE_LCD_PANEL, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_DisplayOutput() */
+
+/**************************************************************************//**
+ * @brief       Interrupt callback setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
+ *              - Registers the specified interrupt callback function.
+ *              - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
+ *                specified.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Interrupt callback setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_CallbackISR (const vdc5_channel_t ch, const vdc5_int_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_CallbackISRCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_CLK;
+        } else {
+            rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VSYNC);
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+                ret = VDC5_ERR_RESOURCE_VSYNC;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_Int_SetInterrupt(ch, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_CallbackISR() */
+
+/**************************************************************************//**
+ * @brief       Data write control processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the input image area to be captured.
+ *              - Makes input image scale-down/rotation control settings (layers 0 and 1 only).
+ *              - Makes frame buffer write control settings.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_WR
+ *                                        - VDC5_LAYER_ID_1_WR
+ *                                        - VDC5_LAYER_ID_OIR_WR
+ * @param[in]   param                   : Data write control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_WriteDataControl (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_scaling_type_t     scaling_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    scaling_id = ConvertRwProcId2SclId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_WriteDataControlCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+        if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is already used. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        } else {
+            if (layer_id == VDC5_LAYER_ID_0_WR) {
+                /* Layer 0 */
+                rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+            } else if (layer_id == VDC5_LAYER_ID_1_WR) {
+                /* Layer 1 */
+                rsrc_state = VDC5_ShrdPrmGetResource(
+                                 ((ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0),
+                                 VDC5_RESOURCE_VIDEO_IN);
+            } else {
+                /* Layer OIR */
+                rsrc_state = VDC5_RESOURCE_ST_VALID;
+            }
+            if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+                ret = VDC5_ERR_RESOURCE_INPUT;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetWriteParam(ch, scaling_id, param);
+
+        /* Setting VDC5 registers */
+        VDC5_WriteDataControl(ch, scaling_id, param);
+
+        VDC5_ShrdPrmSetLayerResource(ch, layer_id, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_WriteDataControl() */
+
+/**************************************************************************//**
+ * @brief       Data write change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the input image area to be captured.
+ *              - Makes changes with respect to scaling-down/rotation control of the input image (layers 0 and 1 only).
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_WR
+ *                                        - VDC5_LAYER_ID_1_WR
+ *                                        - VDC5_LAYER_ID_OIR_WR
+ * @param[in]   param                   : Data write change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ChangeWriteProcess (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_scaling_type_t     scaling_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    scaling_id = ConvertRwProcId2SclId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ChangeWriteProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(ch, layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetChgWriteParam(ch, scaling_id, param);
+
+        /* Setting VDC5 registers */
+        VDC5_ChangeWriteProcess(ch, scaling_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ChangeWriteProcess() */
+
+/**************************************************************************//**
+ * @brief       Data read control processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the display area for graphics images.
+ *              - Makes image scale-up control settings (layers 0 and 1 only).
+ *              - Makes frame buffer read control settings.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ *                                        - VDC5_LAYER_ID_OIR_RD
+ * @param[in]   param                   : Data read control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ReadDataControl (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_read_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ReadDataControlCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+        if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is already used. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetReadParam(ch, graphics_id, param);
+
+        /* Setting VDC5 registers */
+        VDC5_ReadDataControl(ch, graphics_id, param);
+
+        VDC5_ShrdPrmSetLayerResource(ch, layer_id, VDC5_RESOURCE_ST_VALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_ReadDataControl() */
+
+/**************************************************************************//**
+ * @brief       Data read change processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Changes the frame buffer base address.
+ *              - Changes the frame buffer read size (image scale-up control) (layers 0 and 1 only).
+ *              - Changes the display area for graphics images.
+ *              - Changes the graphics display mode.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ *                                        - VDC5_LAYER_ID_OIR_RD
+ * @param[in]   param                   : Data read change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ChangeReadProcess (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ChangeReadProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(ch, layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        VDC5_ShrdPrmSetChgReadParam(ch, graphics_id, param);
+
+        /* Setting VDC5 registers */
+        VDC5_ChangeReadProcess(ch, graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ChangeReadProcess() */
+
+/**************************************************************************//**
+ * @brief       Data write/read start processing
+ *
+ *              Description:<br>
+ *              This function performs layer start processing. If the layer ID specified in layer_id
+ *              is VDC5_LAYER_ID_ALL, the function starts all the layers that are in the stopped state
+ *              and also enabled. If the layer ID is not VDC5_LAYER_ID_ALL, the function starts only
+ *              the specified layer.<br>
+ *              When performing start processing for write, the function starts a write to the frame buffer.
+ *              When performing start processing for read, the function starts a read from the frame buffer
+ *              and sets the graphics display mode to the specified values for each layer.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   param                   : Data write/read start parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_StartProcess (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_StartProcessCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        if (layer_id != VDC5_LAYER_ID_ALL) {
+            rsrc_state = VDC5_ShrdPrmGetRwProcReady(ch, layer_id);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+                /* The specified layer is invalid. */
+                ret = VDC5_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_StartProcess(ch, layer_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_StartProcess() */
+
+/**************************************************************************//**
+ * @brief       Data write/read stop processing
+ *
+ *              Description:<br>
+ *              This function performs layer stop processing. If the layer ID specified in layer_id is
+ *              VDC5_LAYER_ID_ALL, the function stops all the layers that are enabled and running.
+ *              If the layer ID is not VDC5_LAYER_ID_ALL, the function stops only the specified layer.<br>
+ *              When performing stop processing for write, the function stops the write to the frame buffer.
+ *              When performing stop processing for read, the function stops the read from the frame buffer
+ *              and resets the graphics display mode to the initial values for each of the layers.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_StopProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_StopProcessCheckPrm(ch, layer_id);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        if (layer_id != VDC5_LAYER_ID_ALL) {
+            rsrc_state = VDC5_ShrdPrmGetRwProcEnabled(ch, layer_id);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+                /* The specified layer is invalid. */
+                ret = VDC5_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_StopProcess(ch, layer_id);
+    }
+    return ret;
+}   /* End of function R_VDC5_StopSurface() */
+
+/**************************************************************************//**
+ * @brief       Data write/read control release processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Disables the specified layer.
+ *              - Initializes the cascaded connection settings (layer 1 read processing only).
+ *              - Initializes the VIN synthesizer settings (layer 0 and 1 read processing only).
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ReleaseDataControl (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ReleaseDataControlCheckPrm(ch, layer_id);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        if (layer_id != VDC5_LAYER_ID_ALL) {
+            rsrc_state = VDC5_ShrdPrmGetRwProcReady(ch, layer_id);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+                /* The specified layer is invalid. */
+                ret = VDC5_ERR_RESOURCE_LAYER;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_ReleaseDataControl(ch, layer_id);
+
+        VDC5_ShrdPrmSetLayerResource(ch, layer_id, VDC5_RESOURCE_ST_INVALID);
+    }
+    return ret;
+}   /* End of function R_VDC5_ReleaseDataControl() */
+
+/**************************************************************************//**
+ * @brief       Noise reduction setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off noise reduction processing.
+ *              - Sets up the noise reduction parameters for the Y/G, Cb/B, and Cr/R signals.
+ * @param[in]   ch                      : Channel
+ * @param[in]   nr1d_on                 : Noise reduction ON/OFF setting
+ * @param[in]   param                   : Noise reduction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_VideoNoiseReduction (
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      nr1d_on,
+    const vdc5_noise_reduction_t    * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_VideoNoiseReductCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_INPUT;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_VideoNoiseReduction(ch, nr1d_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_VideoNoiseReduction() */
+
+/**************************************************************************//**
+ * @brief       Color matrix setup
+ *
+ *              Description:<br>
+ *              This function sets up the specified color matrix.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Color matrix setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageColorMatrix (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ImageColorMatrixCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        if (param->module == VDC5_COLORMTX_IMGCNT) {
+            rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_WR);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+                rsrc_state = VDC5_ShrdPrmGetLayerResource(
+                                 ((ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0),
+                                 VDC5_LAYER_ID_1_WR);
+            }
+        } else if (param->module == VDC5_COLORMTX_ADJ_0) {
+            rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+        } else {
+            rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_1_RD);
+        }
+
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_ImageColorMatrix(ch, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ImageColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Image enhancement processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off sharpness processing.
+ *              - Sets up the sharpness parameter.
+ *              - Turns on and off LTI processing.
+ *              - Sets up the LTI parameter.
+ *              - Sets up the enhancer-enabled area to be subjected to sharpness and LTI processing.
+ * @param[in]   ch                      : Channel
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness setup parameter
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   enh_area                : Enhancer-enabled area setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageEnhancement (
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+    vdc5_color_space_t      color_space;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ImageEnhancementCheckPrm(ch, imgimprv_id, sharp_param, enh_area);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(
+                         ch,
+                         ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_LAYER_ID_0_RD : VDC5_LAYER_ID_1_RD));
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        } else {
+            /* Condition checks */
+            color_space = VDC5_ShrdPrmGetColorSpaceFbRd(
+                              ch,
+                              ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_GR_TYPE_GR0 : VDC5_GR_TYPE_GR1));
+            if (color_space == VDC5_COLOR_SPACE_GBR) {
+                /* The image quality improver does not act on RGB signals. */
+                ret = VDC5_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_ImageEnhancement(ch, imgimprv_id, shp_h_on, sharp_param, lti_h_on, lti_param, enh_area);
+    }
+    return ret;
+}   /* End of function R_VDC5_ImageEnhancement() */
+
+/**************************************************************************//**
+ * @brief       Black stretch setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off black stretch processing.
+ *              - Sets up the black stretch parameters.
+ * @param[in]   ch                      : Channel
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ * @param[in]   bkstr_on                : Black stretch ON/OFF setting
+ * @param[in]   param                   : Black stretch setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_ImageBlackStretch (
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+    vdc5_color_space_t      color_space;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ImageBlackStretchCheckPrm(ch, imgimprv_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(
+                         ch,
+                         ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_LAYER_ID_0_RD : VDC5_LAYER_ID_1_RD));
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        } else {
+            /* Condition checks */
+            color_space = VDC5_ShrdPrmGetColorSpaceFbRd(
+                              ch,
+                              ((imgimprv_id == VDC5_IMG_IMPRV_0) ? VDC5_GR_TYPE_GR0 : VDC5_GR_TYPE_GR1));
+            if (color_space == VDC5_COLOR_SPACE_GBR) {
+                /* The image quality improver does not act on RGB signals. */
+                ret = VDC5_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_ImageBlackStretch(ch, imgimprv_id, bkstr_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_ImageBlackStretch() */
+
+/**************************************************************************//**
+ * @brief       Alpha blending setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up the alpha value of the ARGB1555/RGBA5551 formats.
+ *              - Make settings for premultiplication processing at alpha blending in one-pixel.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ * @param[in]   param                   : Alpha blending setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_AlphaBlending (
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_AlphaBlendingCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_AlphaBlending(ch, graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief       Rectangle alpha blending setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off alpha blending in a rectangular area.
+ *              - Sets up the rectangular area subjected to alpha blending.
+ *              - Sets up the alpha value for alpha blending in a rectangular area.
+ *              - Makes fade-in/-out settings to be applied to rectangle alpha blending.
+ *              - Allocates graphics 0 and 1 to the lower-layer/current graphics in the VIN synthesizer.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ *                                        - VDC5_LAYER_ID_VIN_RD
+ * @param[in]   gr_arc_on               : ON/OFF setting for alpha blending in a rectangular area
+ * @param[in]   param                   : Setup parameter for alpha blending in a rectangular area
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_AlphaBlendingRect (
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_color_space_t      color_space;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_AlphaBlendingRectCheckPrm(ch, layer_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        if (layer_id != VDC5_LAYER_ID_VIN_RD) {
+            /* Resource checks */
+            rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+            if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+                /* The specified layer is invalid. */
+                ret = VDC5_ERR_RESOURCE_LAYER;
+            } else {
+                /* Condition checks */
+                color_space = VDC5_ShrdPrmGetColorSpaceFbRd(ch, graphics_id);
+                if (color_space == VDC5_COLOR_SPACE_YCBCR) {
+                    /* Alpha blending cannot be used
+                       when the format of the signal read from the frame buffer is YCbCr422 or YCbCr444. */
+                    ret = VDC5_ERR_IF_CONDITION;
+                }
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_AlphaBlendingRect(ch, graphics_id, gr_arc_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_AlphaBlendingRect() */
+
+/**************************************************************************//**
+ * @brief       Chroma-key setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off the chroma-key processing.
+ *              - Sets up the color signals to be subject to chroma-key processing and
+ *                the color signals after replacement.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ *                                        - VDC5_LAYER_ID_OIR_RD
+ * @param[in]   gr_ck_on                : Chroma-key ON/OFF setting
+ * @param[in]   param                   : Chroma-key setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_Chromakey (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_color_space_t      color_space;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_ChromakeyCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        } else {
+            /* Condition checks */
+            color_space = VDC5_ShrdPrmGetColorSpaceFbRd(ch, graphics_id);
+            if (color_space == VDC5_COLOR_SPACE_YCBCR) {
+                /* Chroma-key processing cannot be used
+                   when the format of the signal read from the frame buffer is YCbCr422 or YCbCr444. */
+                ret = VDC5_ERR_IF_CONDITION;
+            }
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_Chromakey(ch, graphics_id, gr_ck_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_Chromakey() */
+
+/**************************************************************************//**
+ * @brief       CLUT setup
+ *
+ *              Description:<br>
+ *              This function sets up CLUT for the specified layer.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ *                                        - VDC5_LAYER_ID_0_RD
+ *                                        - VDC5_LAYER_ID_1_RD
+ *                                        - VDC5_LAYER_ID_2_RD
+ *                                        - VDC5_LAYER_ID_3_RD
+ *                                        - VDC5_LAYER_ID_OIR_RD
+ * @param[in]   param                   : CLUT setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_CLUT (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_clut_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_graphics_type_t    graphics_id;
+    vdc5_resource_state_t   rsrc_state;
+
+    graphics_id = ConvertRwProcId2GrId(layer_id);
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_CLUTCheckPrm(ch, layer_id, graphics_id, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, layer_id);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The specified layer is invalid. */
+            ret = VDC5_ERR_RESOURCE_LAYER;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_CLUT(ch, graphics_id, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_SetCLUT() */
+
+/**************************************************************************//**
+ * @brief       Display calibration processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Sets up panel brightness adjustment.
+ *              - Sets up contrast adjustment.
+ *              - Sets up panel dithering.
+ *              - Makes control settings for the correction circuit sequence.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Display calibration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_DisplayCalibration (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_DisplayCalibrationCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LCD_PANEL);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_OUTPUT;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_DisplayCalibration(ch, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_DisplayCalibration() */
+
+/**************************************************************************//**
+ * @brief       Gamma correction setup
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Turns on and off gamma correction processing.
+ *              - Sets up the gamma correction gain adjustment values for the G/B/R signals.
+ *              - Sets up the gamma correction start threshold values for the G/B/R signals.
+ * @param[in]   ch                      : Channel
+ * @param[in]   gam_on                  : Gamma correction ON/OFF setting
+ * @param[in]   param                   : Gamma correction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t R_VDC5_GammaCorrection (
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      gam_on,
+    const vdc5_gamma_correction_t   * const param)
+{
+    vdc5_error_t            ret;
+    vdc5_resource_state_t   rsrc_state;
+
+    ret = VDC5_OK;
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    ret = VDC5_GammaCorrectionCheckPrm(ch, param);
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+    if (ret == VDC5_OK) {
+        /* Resource checks */
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LCD_PANEL);
+        if (rsrc_state != VDC5_RESOURCE_ST_VALID) {
+            ret = VDC5_ERR_RESOURCE_OUTPUT;
+        }
+    }
+    if (ret == VDC5_OK) {
+        /* Setting VDC5 registers */
+        VDC5_GammaCorrection(ch, gam_on, param);
+    }
+    return ret;
+}   /* End of function R_VDC5_GammaCorrection() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Convert read/write process ID into scaling type ID
+ *
+ * @param[in]   layer_id              : Layer ID
+ * @retval      Scaling type ID
+ *****************************************************************************/
+static vdc5_scaling_type_t ConvertRwProcId2SclId (const vdc5_layer_id_t layer_id)
+{
+    vdc5_scaling_type_t scaling_id;
+
+    switch (layer_id) {
+        case VDC5_LAYER_ID_0_WR:                /* Layer 0, write process */
+            scaling_id = VDC5_SC_TYPE_SC0;      /* Scaler 0 */
+            break;
+        case VDC5_LAYER_ID_1_WR:                /* Layer 1, write process */
+            scaling_id = VDC5_SC_TYPE_SC1;      /* Scaler 1 */
+            break;
+        case VDC5_LAYER_ID_OIR_WR:              /* Layer OIR, write process */
+            scaling_id = VDC5_SC_TYPE_OIR;      /* OIR */
+            break;
+        default:                                /* Error */
+            scaling_id = VDC5_SC_TYPE_NUM;
+            break;
+    }
+    return scaling_id;
+}   /* End of function ConvertRwProcId2SclId() */
+
+/**************************************************************************//**
+ * @brief       Convert read/write process ID into graphics type ID
+ *
+ * @param[in]   layer_id              : Layer ID
+ * @retval      Graphics type ID
+ *****************************************************************************/
+static vdc5_graphics_type_t ConvertRwProcId2GrId (const vdc5_layer_id_t layer_id)
+{
+    vdc5_graphics_type_t graphics_id;
+
+    switch (layer_id) {
+        case VDC5_LAYER_ID_0_RD:                /* Layer 0, read process */
+            graphics_id = VDC5_GR_TYPE_GR0;     /* Graphics 0 */
+            break;
+        case VDC5_LAYER_ID_1_RD:                /* Layer 1, read process */
+            graphics_id = VDC5_GR_TYPE_GR1;     /* Graphics 1 */
+            break;
+        case VDC5_LAYER_ID_2_RD:                /* Layer 2, read process */
+            graphics_id = VDC5_GR_TYPE_GR2;     /* Graphics 2 */
+            break;
+        case VDC5_LAYER_ID_3_RD:                /* Layer 3, read process */
+            graphics_id = VDC5_GR_TYPE_GR3;     /* Graphics 3 */
+            break;
+        case VDC5_LAYER_ID_VIN_RD:              /* Layer VIN, read process */
+            graphics_id = VDC5_GR_TYPE_VIN;     /* VIN */
+            break;
+        case VDC5_LAYER_ID_OIR_RD:              /* Layer OIR, read process */
+            graphics_id = VDC5_GR_TYPE_OIR;     /* OIR */
+            break;
+        default:                                /* Error */
+            graphics_id = VDC5_GR_TYPE_NUM;
+            break;
+    }
+    return graphics_id;
+}   /* End of function ConvertRwProcId2GrId() */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdc5/src/r_vdc5_check_parameter.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1953 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_check_parameter.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver parameter check processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_shared_param.h"
+#include    "r_vdc5_check_parameter.h"
+
+
+#ifdef      R_VDC5_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Valid bit range */
+#define VDC5_CPARA_RANGE_0X00000001 (0x00000001u)
+#define VDC5_CPARA_RANGE_0X00000003 (0x00000003u)
+#define VDC5_CPARA_RANGE_0X00000007 (0x00000007u)
+#define VDC5_CPARA_RANGE_0X0000000F (0x0000000Fu)
+#define VDC5_CPARA_RANGE_0X0000001F (0x0000001Fu)
+#define VDC5_CPARA_RANGE_0X0000003F (0x0000003Fu)
+#define VDC5_CPARA_RANGE_0X0000007F (0x0000007Fu)
+#define VDC5_CPARA_RANGE_0X000000FF (0x000000FFu)
+#define VDC5_CPARA_RANGE_0X000003FF (0x000003FFu)
+#define VDC5_CPARA_RANGE_0X000007FF (0x000007FFu)
+#define VDC5_CPARA_RANGE_0X00007FFF (0x00007FFFu)
+#define VDC5_CPARA_RANGE_0X0000FFFF (0x0000FFFFu)
+#define VDC5_CPARA_RANGE_0X007FFFFF (0x007FFFFFu)
+#define VDC5_CPARA_RANGE_0X00FFFFFF (0x00FFFFFFu)
+/* Valid range for signal delay amount */
+#define VDC5_CPARA_INP_FLD_DLY_MAX (254u)
+#define VDC5_CPARA_INP_VS_DLY_MAX  (254u)
+#define VDC5_CPARA_INP_HS_DLY_MAX  (254u)
+/* Valid range for NFS */
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_56 (56u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_24 (24u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_28 (28u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_31 (31u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_37 (37u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_39 (39u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_46 (46u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_47 (47u)
+#define VDC5_CPARA_LVDSPLL_FD_LIMIT_55 (55u)
+/* Valid range for HS + HW */
+#define VDC5_CPARA_HS_HW_MAX       (2015u)
+/* Valid range for HS */
+#define VDC5_CPARA_HS_MIN          (16u)
+/* Valid range for VS + VW */
+#define VDC5_CPARA_VS_VW_MAX       (2039u)
+/* Valid range for VS */
+#define VDC5_CPARA_VS_MIN          (4u)
+/* The max number of CLUT data values */
+#define VDC5_CPARA_CLUT8_NUM       (256u)
+#define VDC5_CPARA_CLUT4_NUM       (16u)
+#define VDC5_CPARA_CLUT1_NUM       (2u)
+/* Valid range for the alpha coefficient */
+#define VDC5_CPARA_GR_ARC_COEF_MIN (-255)
+#define VDC5_CPARA_GR_ARC_COEF_MAX (255)
+/* Valid range for HS of enhancer area */
+#define VDC5_CPARA_ENH_HS_LIMIT    (4u)
+/* Valid range for VS of enhancer area */
+#define VDC5_CPARA_ENH_VS_LIMIT    (2u)
+
+#define VDC5_BKSTR_T2_PROHIBITED    (31u)
+
+#define VDC5_MULTIPLE_4_MASK        (0x00000003u)
+#define VDC5_MULTIPLE_32_MASK       (0x0000001Fu)
+#define VDC5_MULTIPLE_128_MASK      (0x0000007Fu)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_error_t CheckChannel(const vdc5_channel_t ch);
+static vdc5_error_t CheckLayerId(const vdc5_layer_id_t layer_id);
+static vdc5_error_t CheckGraphicsTypeLayerId(const vdc5_layer_id_t layer_id);
+static vdc5_error_t CheckRect(const vdc5_period_rect_t * const rect);
+static vdc5_error_t CheckTcon_Vertical(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_Horizontal(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_HorizontalPol(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckTcon_DataEnable(const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing);
+static vdc5_error_t CheckGammaCrct_GainAdjustment(const uint16_t * gam_gain);
+
+
+/**************************************************************************//**
+ * @brief       Checks on initialization parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Initialization parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_InitializeCheckPrm (const vdc5_channel_t ch, const vdc5_init_t * const param)
+{
+    vdc5_error_t            error;
+    const vdc5_lvds_t     * lvds_tmp;
+    vdc5_resource_state_t   rsrc_state;
+    vdc5_input_sel_t        inp_sel_tmp;
+    vdc5_channel_t          lvds_vdc_sel_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Panel clock select */
+    if (param->panel_icksel >= VDC5_PANEL_ICKSEL_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if ((param->panel_icksel != VDC5_PANEL_ICKSEL_LVDS) && (param->panel_icksel != VDC5_PANEL_ICKSEL_LVDS_DIV7)) {
+        /* Clock frequency division ratio */
+        if (param->panel_dcdr >= VDC5_PANEL_CLKDIV_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+    rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_VIDEO_IN);
+    if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+        inp_sel_tmp = VDC5_ShrdPrmGetInputSelect(ch);
+        if (((inp_sel_tmp == VDC5_INPUT_SEL_VDEC) && (param->panel_icksel == VDC5_PANEL_ICKSEL_IMG_DV)) ||
+                ((inp_sel_tmp == VDC5_INPUT_SEL_EXT) && (param->panel_icksel == VDC5_PANEL_ICKSEL_IMG))) {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+
+    /* LVDS-related parameter */
+    lvds_tmp = param->lvds;
+    if (lvds_tmp == NULL) {
+        rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LVDS_CLK);
+        if (rsrc_state == VDC5_RESOURCE_ST_INVALID) {
+            /* The LVDS PLL clock has not been set yet. */
+            if ((param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS) || (param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS_DIV7)) {
+                error = VDC5_ERR_PARAM_NULL;
+                goto END;
+            }
+        } else {
+            if (param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS_DIV7) {
+                lvds_vdc_sel_tmp = VDC5_ShrdPrmGetLvdsCh();
+                if (ch != lvds_vdc_sel_tmp) {
+                    /* Channel mismatch error */
+                    error = VDC5_ERR_PARAM_CONDITION;
+                    goto END;
+                }
+            }
+        }
+    } else {
+        /* The clock input to frequency divider 1 */
+        if (lvds_tmp->lvds_in_clk_sel >= VDC5_LVDS_INCLK_SEL_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        /* The frequency dividing value (NIDIV and NODIV) for frequency divider 1 and 2 */
+        if ((lvds_tmp->lvds_idiv_set >= VDC5_LVDS_NDIV_NUM) || (lvds_tmp->lvds_odiv_set >= VDC5_LVDS_NDIV_NUM)) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        /* Internal parameter setting for LVDS PLL */
+        if (((uint32_t)lvds_tmp->lvdspll_tst & (uint32_t)~VDC5_CPARA_RANGE_0X0000003F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* A channel in VDC5 whose data is to be output through the LVDS */
+        if (lvds_tmp->lvds_vdc_sel >= VDC5_CHANNEL_NUM) {
+            error = VDC5_ERR_PARAM_CHANNEL;
+            goto END;
+        }
+        if (param->panel_icksel != VDC5_PANEL_ICKSEL_LVDS_DIV7) {
+            /* When using the clock output from the LVDS PLL as the clock for the LVDS output interface,
+               both channel number should match. */
+            if (ch != lvds_tmp->lvds_vdc_sel) {
+                /* Channel mismatch error */
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+        /* The frequency dividing value (NFD) for the feedback frequency */
+        if (((uint32_t)lvds_tmp->lvdspll_fd & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)lvds_tmp->lvdspll_fd < (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_56) {
+            if ((uint32_t)lvds_tmp->lvdspll_fd < (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_24) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+            if (((uint32_t)lvds_tmp->lvdspll_fd >= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_28) && ((uint32_t)lvds_tmp->lvdspll_fd <= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_31)) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+            if (((uint32_t)lvds_tmp->lvdspll_fd >= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_37) && ((uint32_t)lvds_tmp->lvdspll_fd <= (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_39)) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+            if (((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_46) ||
+                    ((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_47) ||
+                    ((uint32_t)lvds_tmp->lvdspll_fd == (uint32_t)VDC5_CPARA_LVDSPLL_FD_LIMIT_55)) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+        /* The frequency dividing value (NRD) for the input frequency */
+        if (((uint32_t)lvds_tmp->lvdspll_rd & (uint32_t)~VDC5_CPARA_RANGE_0X0000001F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* The frequency dividing value (NOD) for the output frequency */
+        if (lvds_tmp->lvdspll_od >= VDC5_LVDS_PLL_NOD_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_InitializeCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC5_Terminate
+ * @param[in]   ch          : Channel
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_TerminateCheckPrm (const vdc5_channel_t ch)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_TerminateCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on video input setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Video input setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_VideoInputCheckPrm (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+    vdc5_error_t                error;
+    const vdc5_sync_delay_t   * dly_tmp;
+    const vdc5_ext_in_sig_t   * ext_sig_tmp;
+    vdc5_panel_clksel_t         panel_clksel;
+    vdc5_resource_state_t       rsrc_state;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_PANEL_CLK);
+    if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+        panel_clksel = VDC5_ShrdPrmGetPanelClkSel(ch);
+        if (param->inp_sel == VDC5_INPUT_SEL_VDEC) {
+            /* Video decoder output signals */
+            if (panel_clksel == VDC5_PANEL_ICKSEL_IMG_DV) {
+                /* Video image clock, DV_CLK */
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        } else {
+            /* Signals supplied via the external input pins */
+            if (panel_clksel == VDC5_PANEL_ICKSEL_IMG) {
+                /* Video image clock, VIDEO_X1 */
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+    }
+
+    /* Vsync signal 1/2fH phase timing */
+    if (((uint32_t)param->inp_fh50 & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Vsync signal 1/4fH phase timing */
+    if (((uint32_t)param->inp_fh25 & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* Sync signal delay adjustment */
+    dly_tmp = param->dly;
+    if (dly_tmp != NULL) {
+        /* Number of lines for delaying Vsync signal and field differentiation signal */
+        if (((uint32_t)dly_tmp->inp_vs_dly_l & (uint32_t)~VDC5_CPARA_RANGE_0X00000007) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Field differentiation signal delay amount */
+        if (((uint32_t)dly_tmp->inp_fld_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_fld_dly > (uint32_t)VDC5_CPARA_INP_FLD_DLY_MAX) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Vsync signal delay amount */
+        if (((uint32_t)dly_tmp->inp_vs_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_vs_dly > (uint32_t)VDC5_CPARA_INP_VS_DLY_MAX) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Hsync signal delay amount */
+        if (((uint32_t)dly_tmp->inp_hs_dly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)dly_tmp->inp_hs_dly > (uint32_t)VDC5_CPARA_INP_HS_DLY_MAX) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+
+    /* External input signal */
+    ext_sig_tmp = param->ext_sig;
+    if (ext_sig_tmp == NULL) {
+        if (param->inp_sel != VDC5_INPUT_SEL_VDEC) {
+            error = VDC5_ERR_PARAM_NULL;
+            goto END;
+        }
+    } else {
+        /* External input format select */
+        if (ext_sig_tmp->inp_format >= VDC5_EXTIN_FORMAT_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+        if (ext_sig_tmp->inp_h_pos >= VDC5_EXTIN_H_POS_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if ((ext_sig_tmp->inp_h_pos == VDC5_EXTIN_H_POS_YCRYCB) || (ext_sig_tmp->inp_h_pos == VDC5_EXTIN_H_POS_CRYCBY)) {
+            if (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_YCBCR422) {
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_VideoInputCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on sync control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Sync control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_SyncControlCheckPrm (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    if (param->res_vs_sel != VDC5_OFF) {
+        /* Free-running Vsync period setting */
+        if (((uint32_t)param->res_fv & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Hsync period setting */
+    if (((uint32_t)param->res_fh & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Vsync signal delay control */
+    if (((uint32_t)param->res_vsdly & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* Full-screen enable control */
+    error = CheckRect(&param->res_f);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_SyncControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on display output configuration parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Display output configuration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_DisplayOutputCheckPrm (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+    vdc5_error_t                    error;
+    uint32_t                        tcon_sig_index;
+    static vdc5_error_t    (* const tcon_function_tbl[VDC5_LCD_TCONSIG_NUM])(
+        const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing) = {
+        &CheckTcon_Vertical,        /* STVA/VS */
+        &CheckTcon_Vertical,        /* STVB/VE */
+        &CheckTcon_Horizontal,      /* STH/HS */
+        &CheckTcon_Horizontal,      /* STB/HE */
+        &CheckTcon_Horizontal,      /* CPV/GCK */
+        &CheckTcon_HorizontalPol,   /* POLA */
+        &CheckTcon_HorizontalPol,   /* POLB */
+        &CheckTcon_DataEnable       /* DE */
+    };
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* 1/2fH timing */
+    if (((uint32_t)param->tcon_half & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Offset Hsync signal timing */
+    if (((uint32_t)param->tcon_offset & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+
+    /* LCD TCON timing setting */
+    for (tcon_sig_index = 0; tcon_sig_index < VDC5_LCD_TCONSIG_NUM; tcon_sig_index++) {
+        if (param->outctrl[tcon_sig_index] != NULL) {
+            error = tcon_function_tbl[tcon_sig_index](param->outctrl[tcon_sig_index]);
+            if (error != VDC5_OK) {
+                goto END;
+            }
+        }
+    }
+
+    /* LCD output format select */
+    if (param->out_format >= VDC5_LCD_OUTFORMAT_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if (param->out_format == VDC5_LCD_OUTFORMAT_SERIAL_RGB) {
+        /* Clock frequency control */
+        if (param->out_frq_sel >= VDC5_LCD_SERIAL_CLKFRQ_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (param->out_frq_sel == VDC5_LCD_PARALLEL_CLKFRQ_1) {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+        /* Clock phase adjustment */
+        if (param->out_phase >= VDC5_LCD_SERIAL_CLKPHASE_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (param->out_frq_sel == VDC5_LCD_SERIAL_CLKFRQ_3) {
+            if (param->out_phase == VDC5_LCD_SERIAL_CLKPHASE_3) {
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+        }
+    }
+    /* Background color in 24-bit RGB color format */
+    if ((param->bg_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_DisplayOutputCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on interrupt callback setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Interrupt callback setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_CallbackISRCheckPrm (const vdc5_channel_t ch, const vdc5_int_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* VDC5 interrupt type */
+    if (param->type >= VDC5_INT_TYPE_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Interrupt callback function pointer */
+    if (param->callback != 0) {
+        if ((param->type == VDC5_INT_TYPE_VLINE) ||
+                (param->type == VDC5_INT_TYPE_S0_WLINE) ||
+                (param->type == VDC5_INT_TYPE_S1_WLINE) ||
+                (param->type == VDC5_INT_TYPE_OIR_VLINE)) {
+            /* Line interrupt set */
+            if (((uint32_t)param->line_num & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_CallbackISRCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_WriteDataControlCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param)
+{
+    vdc5_error_t                    error;
+    const vdc5_scalingdown_rot_t  * scldw_rt_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    if ((layer_id != VDC5_LAYER_ID_0_WR) && (layer_id != VDC5_LAYER_ID_1_WR) && (layer_id != VDC5_LAYER_ID_OIR_WR)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Scaling-down and rotation parameter */
+    scldw_rt_tmp = &param->scalingdown_rot;
+    /* Image area to be captured */
+    error = CheckRect(&scldw_rt_tmp->res);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Frame buffer writing mode for image processing */
+    if (scldw_rt_tmp->res_ds_wr_md >= VDC5_WR_MD_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Swap setting in frame buffer writing */
+    if (param->res_wrswa >= VDC5_WR_RD_WRSWA_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Frame buffer video-signal writing format */
+    if (param->res_md >= VDC5_RES_MD_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Writing rate */
+    if (param->res_fs_rate >= VDC5_RES_FS_RATE_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Frame buffer base address */
+    if (param->base == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+    /* Frame buffer line offset address [byte] */
+    if ((param->ln_off & (uint32_t)~VDC5_CPARA_RANGE_0X00007FFF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (param->res_bst_md == VDC5_BST_MD_32BYTE) {
+        /* 32-byte transfer */
+        if ((param->ln_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    } else {
+        /* 128-byte transfer */
+        if ((param->ln_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Number of frames of buffer to be written to (res_flm_num + 1) */
+    if ((param->flm_num & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Frame buffer frame offset address [byte] */
+    if (param->flm_num != 0u) {
+        if ((param->flm_off & (uint32_t)~VDC5_CPARA_RANGE_0X007FFFFF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (param->res_bst_md == VDC5_BST_MD_32BYTE) {
+            /* 32-byte transfer */
+            if ((param->flm_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        } else {
+            /* 128-byte transfer */
+            if ((param->flm_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_WriteDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write change parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChangeWriteProcessCheckPrm (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t  * const param)
+{
+    vdc5_error_t                    error;
+    const vdc5_scalingdown_rot_t  * scldw_rt_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    if ((layer_id != VDC5_LAYER_ID_0_WR) && (layer_id != VDC5_LAYER_ID_1_WR) && (layer_id != VDC5_LAYER_ID_OIR_WR)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Scaling-down and rotation parameter */
+    scldw_rt_tmp = &param->scalingdown_rot;
+    /* Image area to be captured */
+    error = CheckRect(&scldw_rt_tmp->res);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    /* Number of valid lines in vertical direction output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_vw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Number of valid horizontal pixels output by scaling-down control block */
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)scldw_rt_tmp->res_out_hw & (uint32_t)VDC5_MULTIPLE_4_MASK) != 0u) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Frame buffer writing mode */
+    if (scldw_rt_tmp->res_ds_wr_md >= VDC5_WR_MD_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_ChangeWriteProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data read control parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : Data read control parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ReadDataControlCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param)
+{
+    vdc5_error_t            error;
+    void                  * btm_base_tmp;
+    vdc5_resource_state_t   rsrc_state;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Frame buffer address setting signal */
+    if (param->gr_flm_sel >= VDC5_GR_FLM_SEL_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    btm_base_tmp    = NULL;
+    rsrc_state      = VDC5_RESOURCE_ST_INVALID;
+    switch (graphics_id) {
+        case VDC5_GR_TYPE_GR0:
+            btm_base_tmp    = VDC5_ShrdPrmGetFrBuffBtm(ch, VDC5_SC_TYPE_SC0);
+            rsrc_state      = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_WR);
+            break;
+        case VDC5_GR_TYPE_GR1:
+            if (param->gr_flm_sel == VDC5_GR_FLM_SEL_DISTORTION) {
+                /* IMR-LS2 is implemented in scaler 0 only. */
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+            btm_base_tmp    = VDC5_ShrdPrmGetFrBuffBtm(ch, VDC5_SC_TYPE_SC1);
+            rsrc_state      = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_1_WR);
+            break;
+        /* The following two cases are intentionally combined. */
+        case VDC5_GR_TYPE_GR2:
+        case VDC5_GR_TYPE_GR3:
+            if (param->gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) {
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+            break;
+        case VDC5_GR_TYPE_OIR:
+            if (param->gr_flm_sel == VDC5_GR_FLM_SEL_POINTER_BUFF) {
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+            if ((ch != VDC5_CHANNEL_0) && (param->gr_flm_sel == VDC5_GR_FLM_SEL_DISTORTION)) {
+                /* IMR-LSD is implemented in channel 0 only. */
+                error = VDC5_ERR_PARAM_CONDITION;
+                goto END;
+            }
+            break;
+        default:
+            /* DO NOTHING */
+            break;
+    }
+    if ((btm_base_tmp != NULL) && (rsrc_state != VDC5_RESOURCE_ST_INVALID)) {
+        /* btm_base_tmp is valid only when rsrc_state is valid. */
+        if (param->gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    /* Frame buffer base address */
+    if (param->gr_base == NULL) {
+        if (param->gr_flm_sel != VDC5_GR_FLM_SEL_POINTER_BUFF) {
+            error = VDC5_ERR_PARAM_NULL;
+            goto END;
+        }
+    }
+    /* Frame buffer line offset address */
+    if ((param->gr_ln_off & (uint32_t)~VDC5_CPARA_RANGE_0X00007FFF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (param->gr_bst_md == VDC5_BST_MD_32BYTE) {
+        /* 32-byte transfer */
+        if ((param->gr_ln_off & (uint32_t)VDC5_MULTIPLE_32_MASK) != 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    } else {
+        /* 128-byte transfer */
+        if ((param->gr_ln_off & (uint32_t)VDC5_MULTIPLE_128_MASK) != 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    if (param->width_read_fb != NULL) {
+        /* Number of lines in a frame */
+        if (((uint32_t)param->width_read_fb->in_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_vw == 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Width of the horizontal valid period */
+        if (((uint32_t)param->width_read_fb->in_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_hw < (uint32_t)VDC5_CPARA_RANGE_0X00000003) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Format of the frame buffer read signal */
+    if (param->gr_format >= VDC5_GR_FORMAT_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if ((param->gr_format == VDC5_GR_FORMAT_YCBCR422) || (param->gr_format == VDC5_GR_FORMAT_YCBCR444)) {
+        /* YCbCr422 and YCbCr444 are supported for the graphics 0 and 1. */
+        if ((graphics_id != VDC5_GR_TYPE_GR0) && (graphics_id != VDC5_GR_TYPE_GR1)) {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    if (param->gr_format == VDC5_GR_FORMAT_YCBCR422) {
+        /* Swapping of data read from buffer in the YCbCr422 format */
+        if (param->gr_ycc_swap >= VDC5_GR_YCCSWAP_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+    /* Swap setting in frame buffer reading */
+    if (param->gr_rdswa >= VDC5_WR_RD_WRSWA_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Graphics display area */
+    error = CheckRect(&param->gr_grc);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_ReadDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data read change parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data read change parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChangeReadProcessCheckPrm (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+    /* Width of the image read from frame buffer */
+    if (param->width_read_fb != NULL) {
+        /* Number of lines in a frame */
+        if (((uint32_t)param->width_read_fb->in_vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_vw == 0u) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Width of the horizontal valid period */
+        if (((uint32_t)param->width_read_fb->in_hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->width_read_fb->in_hw < (uint32_t)VDC5_CPARA_RANGE_0X00000003) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+    /* Graphics display area */
+    if (param->gr_grc != NULL) {
+        error = CheckRect(param->gr_grc);
+        if (error != VDC5_OK) {
+            goto END;
+        }
+    }
+    /* Graphics display mode */
+    if (param->gr_disp_sel != NULL) {
+        if ((*(param->gr_disp_sel) < VDC5_DISPSEL_IGNORED) || (*(param->gr_disp_sel) >= VDC5_DISPSEL_NUM)) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ChangeReadProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on data write/read start parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Data write/read start parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_StartProcessCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param)
+{
+    vdc5_error_t                error;
+    uint32_t                    graphics_types;
+    const vdc5_gr_disp_sel_t  * gr_disp_sel_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    gr_disp_sel_tmp = param->gr_disp_sel;
+    if (gr_disp_sel_tmp == NULL) {
+        error = VDC5_OK;
+        goto END;
+    }
+    /* Graphics display mode */
+    if (layer_id == VDC5_LAYER_ID_ALL) {
+        for (graphics_types = 0; graphics_types < VDC5_GR_TYPE_NUM; graphics_types++) {
+            if ((gr_disp_sel_tmp[graphics_types] < VDC5_DISPSEL_IGNORED) ||
+                    (gr_disp_sel_tmp[graphics_types] >= VDC5_DISPSEL_NUM)) {
+                error = VDC5_ERR_PARAM_UNDEFINED;
+                goto END;
+            }
+        }
+    } else {
+        if ((*gr_disp_sel_tmp < VDC5_DISPSEL_IGNORED) || (*gr_disp_sel_tmp >= VDC5_DISPSEL_NUM)) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_StartProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC5_StopProcess
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_StopProcessCheckPrm (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_StopProcessCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on parameters in R_VDC5_ReleaseDataControl
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ReleaseDataControlCheckPrm (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_ReleaseDataControlCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on noise reduction setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Noise reduction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_VideoNoiseReductCheckPrm (const vdc5_channel_t ch, const vdc5_noise_reduction_t * const param)
+{
+    vdc5_error_t            error;
+    const vdc5_nr_param_t * nr_param;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_OK;
+        goto END;
+    }
+
+    /* Y/G signal noise reduction parameter */
+    nr_param = &param->y;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Cb/B signal noise reduction parameter */
+    nr_param = &param->cb;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Cr/R signal noise reduction parameter */
+    nr_param = &param->cr;
+    /* TAP select */
+    if (nr_param->nr1d_tap >= VDC5_NR_TAPSEL_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Maximum value of coring (absolute value) */
+    if ((nr_param->nr1d_th & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Noise reduction gain adjustment */
+    if (nr_param->nr1d_gain >= VDC5_NR_GAIN_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_VideoNoiseReductCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on color matrix setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Color matrix setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageColorMatrixCheckPrm (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
+{
+    vdc5_error_t    error;
+    int32_t         colormtx_index;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Color matrix module */
+    if (param->module >= VDC5_COLORMTX_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* Operating mode */
+    if (param->mtx_mode >= VDC5_COLORMTX_MODE_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    if (param->module != VDC5_COLORMTX_IMGCNT) {
+        if ((param->mtx_mode == VDC5_COLORMTX_GBR_YCBCR) || (param->mtx_mode == VDC5_COLORMTX_YCBCR_YCBCR)) {
+            error = VDC5_ERR_PARAM_CONDITION;
+            goto END;
+        }
+    }
+    /* Offset (DC) adjustment of Y/G, B, and R signal */
+    for (colormtx_index = 0; colormtx_index < VDC5_COLORMTX_OFFST_NUM; colormtx_index++) {
+        if (((uint32_t)param->offset[colormtx_index] & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment */
+    for (colormtx_index = 0; colormtx_index < VDC5_COLORMTX_GAIN_NUM; colormtx_index++) {
+        if (((uint32_t)param->gain[colormtx_index] & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ImageColorMatrixCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on sharpness setup parameter and enhancer-enabled area setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   imgimprv_id : Image quality improver ID
+ * @param[in]   sharp_param : Sharpness setup parameter
+ * @param[in]   enh_area    : Enhancer-enabled area setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageEnhancementCheckPrm (
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_period_rect_t    * const enh_area)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    /* Image quality improver ID */
+    if (imgimprv_id >= VDC5_IMG_IMPRV_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    /* Sharpness parameter */
+    if (sharp_param != NULL) {
+        /* Sharpness control parameter (H1, H2, and H3) */
+        if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H1].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H2].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if (((uint32_t)sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H3].shp_core & (uint32_t)~VDC5_CPARA_RANGE_0X0000007F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Enhancer area */
+    if (enh_area != NULL) {
+        /* Vertical start position */
+        if (((uint32_t)enh_area->vs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)enh_area->vs < (uint32_t)VDC5_CPARA_ENH_VS_LIMIT) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Height (vertical width) */
+        if (((uint32_t)enh_area->vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Horizontal start position */
+        if (((uint32_t)enh_area->hs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)enh_area->hs < (uint32_t)VDC5_CPARA_ENH_HS_LIMIT) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+        /* Horizontal width */
+        if (((uint32_t)enh_area->hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ImageEnhancementCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on black stretch setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   imgimprv_id : Image quality improver ID
+ * @param[in]   param       : Black stretch setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ImageBlackStretchCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_black_t  * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    /* Image quality improver ID */
+    if (imgimprv_id >= VDC5_IMG_IMPRV_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+
+    if (param != NULL) {
+        /* Black stretch start point */
+        if (((uint32_t)param->bkstr_st & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch depth */
+        if (((uint32_t)param->bkstr_d & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch time constant (T1) */
+        if (((uint32_t)param->bkstr_t1 & (uint32_t)~VDC5_CPARA_RANGE_0X0000001F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Black stretch time constant (T2) */
+        if (((uint32_t)param->bkstr_t2 & (uint32_t)~VDC5_CPARA_RANGE_0X0000001F) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        if ((uint32_t)param->bkstr_t2 == VDC5_BKSTR_T2_PROHIBITED) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+
+    }
+END:
+    return error;
+}   /* End of function VDC5_ImageBlackStretchCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on alpha blending setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Alpha blending setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_AlphaBlendingCheckPrm (
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    if ((layer_id != VDC5_LAYER_ID_1_RD) && (layer_id != VDC5_LAYER_ID_2_RD) && (layer_id != VDC5_LAYER_ID_3_RD)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_AlphaBlendingCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on setup parameter for alpha blending in a rectangular area
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   param       : Setup parameter for alpha blending in a rectangular area
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_AlphaBlendingRectCheckPrm (
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_alpha_blending_rect_t    * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    if ((layer_id != VDC5_LAYER_ID_1_RD) &&
+            (layer_id != VDC5_LAYER_ID_2_RD) &&
+            (layer_id != VDC5_LAYER_ID_3_RD) &&
+            (layer_id != VDC5_LAYER_ID_VIN_RD)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+
+    if (param != NULL) {
+        /* Rectangular area subjected to alpha blending */
+        if (param->gr_arc != NULL) {
+            /* Vertical start position */
+            if (((uint32_t)param->gr_arc->vs_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Height (vertical width) */
+            if (((uint32_t)param->gr_arc->vw_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Horizontal start position */
+            if (((uint32_t)param->gr_arc->hs_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            /* Horizontal width */
+            if (((uint32_t)param->gr_arc->hw_rel & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+        /* Alpha Blending in a rectangular area */
+        if (param->alpha_rect != NULL) {
+            /* Frame rate for alpha blending in a rectangular area */
+            if ((param->alpha_rect->gr_arc_coef < (int16_t)VDC5_CPARA_GR_ARC_COEF_MIN) || (param->alpha_rect->gr_arc_coef > (int16_t)VDC5_CPARA_GR_ARC_COEF_MAX)) {
+                error = VDC5_ERR_PARAM_EXCEED_RANGE;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_AlphaBlendingRectCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on chroma-key setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : Chroma-key setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_ChromakeyCheckPrm (
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_chromakey_t  * const param)
+{
+    vdc5_error_t        error;
+    vdc5_gr_format_t    gr_format_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param != NULL) {
+        gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+        switch (gr_format_tmp) {
+            /* The following four cases are intentionally combined,
+              since the four types of graphics format are represented as 16 bit unsigned integer. */
+            case VDC5_GR_FORMAT_RGB565:
+            case VDC5_GR_FORMAT_ARGB1555:
+            case VDC5_GR_FORMAT_ARGB4444:
+            case VDC5_GR_FORMAT_RGBA5551:
+                if (((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000FFFF) != 0u) ||
+                        ((param->rep_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000FFFF) != 0u)) {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+                break;
+            case VDC5_GR_FORMAT_RGB888:
+                if (((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u) ||
+                        ((param->rep_color & (uint32_t)~VDC5_CPARA_RANGE_0X00FFFFFF) != 0u)) {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+                break;
+            case VDC5_GR_FORMAT_CLUT8:
+                if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X000000FF) != 0u) {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+                break;
+            case VDC5_GR_FORMAT_CLUT4:
+                if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X0000000F) != 0u) {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+                break;
+            case VDC5_GR_FORMAT_CLUT1:
+                if ((param->ck_color & (uint32_t)~VDC5_CPARA_RANGE_0X00000001) != 0u) {
+                    error = VDC5_ERR_PARAM_BIT_WIDTH;
+                }
+                break;
+            default:
+                /* DO NOTHING */
+                break;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_ChromakeyCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on CLUT setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   layer_id    : Layer ID
+ * @param[in]   graphics_id : Graphics type ID
+ * @param[in]   param       : CLUT setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_CLUTCheckPrm (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_clut_t   * const param)
+{
+    vdc5_error_t        error;
+    vdc5_gr_format_t    gr_format_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+    error = CheckGraphicsTypeLayerId(layer_id);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* The number of colors in CLUT */
+    if (param->color_num == 0u) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+    if (gr_format_tmp == VDC5_GR_FORMAT_CLUT1) {
+        /* CLUT1 */
+        if (param->color_num > (uint32_t)VDC5_CPARA_CLUT1_NUM) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    } else if (gr_format_tmp == VDC5_GR_FORMAT_CLUT4) {
+        /* CLUT4 */
+        if (param->color_num > (uint32_t)VDC5_CPARA_CLUT4_NUM) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    } else {
+        /* CLUT8 */
+        if (param->color_num > (uint32_t)VDC5_CPARA_CLUT8_NUM) {
+            error = VDC5_ERR_PARAM_EXCEED_RANGE;
+            goto END;
+        }
+    }
+
+    /* Address of the area storing the CLUT data (in ARGB8888 format) */
+    if (param->clut == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function VDC5_CLUTCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on display calibration parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Display calibration parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_DisplayCalibrationCheckPrm (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
+{
+    vdc5_error_t                    error;
+    const vdc5_calibr_bright_t    * bright_tmp;
+    const vdc5_calibr_dither_t    * panel_dither_tmp;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param == NULL) {
+        error = VDC5_ERR_PARAM_NULL;
+        goto END;
+    }
+
+    /* Brightness (DC) adjustment */
+    bright_tmp = param->bright;
+    if (bright_tmp != NULL) {
+        /* Brightness (DC) adjustment of G signal */
+        if (((uint32_t)bright_tmp->pbrt_g & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Brightness (DC) adjustment of B signal */
+        if (((uint32_t)bright_tmp->pbrt_b & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+        /* Brightness (DC) adjustment of R signal */
+        if (((uint32_t)bright_tmp->pbrt_r & (uint32_t)~VDC5_CPARA_RANGE_0X000003FF) != 0u) {
+            error = VDC5_ERR_PARAM_BIT_WIDTH;
+            goto END;
+        }
+    }
+    /* Panel dithering */
+    panel_dither_tmp = param->panel_dither;
+    if (panel_dither_tmp != NULL) {
+        /* Panel dither operation mode */
+        if (panel_dither_tmp->pdth_sel >= VDC5_PDTH_MD_NUM) {
+            error = VDC5_ERR_PARAM_UNDEFINED;
+            goto END;
+        }
+        if (panel_dither_tmp->pdth_sel == VDC5_PDTH_MD_2X2) {
+            /* Pattern value (A)-(D) of 2x2 pattern dither */
+            if (((uint32_t)panel_dither_tmp->pdth_pa & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pb & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pc & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            if (((uint32_t)panel_dither_tmp->pdth_pd & (uint32_t)~VDC5_CPARA_RANGE_0X00000003) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_DisplayCalibrationCheckPrm() */
+
+/**************************************************************************//**
+ * @brief       Checks on gamma correction setup parameter
+ * @param[in]   ch          : Channel
+ * @param[in]   param       : Gamma correction setup parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdc5_error_t VDC5_GammaCorrectionCheckPrm (const vdc5_channel_t ch, const vdc5_gamma_correction_t * const param)
+{
+    vdc5_error_t error;
+
+    error = CheckChannel(ch);
+    if (error != VDC5_OK) {
+        goto END;
+    }
+
+    if (param != NULL) {
+        /* Gain adjustment of area 0 to 31 of G signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_g_gain);
+        if (error != VDC5_OK) {
+            goto END;
+        }
+        /* Gain adjustment of area 0 to 31 of B signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_b_gain);
+        if (error != VDC5_OK) {
+            goto END;
+        }
+        /* Gain adjustment of area 0 to 31 of R signal */
+        error = CheckGammaCrct_GainAdjustment(param->gam_r_gain);
+        if (error != VDC5_OK) {
+            goto END;
+        }
+    }
+END:
+    return error;
+}   /* End of function VDC5_GammaCorrectionCheckPrm() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Checks on VDC5 channel
+ * @param[in]   ch          : Channel
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckChannel (const vdc5_channel_t ch)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    if (ch >= VDC5_CHANNEL_NUM) {
+        error = VDC5_ERR_PARAM_CHANNEL;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckChannel() */
+
+/**************************************************************************//**
+ * @brief       Checks on layer ID
+ * @param[in]   layer_id        : Layer ID
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckLayerId (const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    if ((layer_id < VDC5_LAYER_ID_ALL) || (layer_id >= VDC5_LAYER_ID_NUM)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+    if (layer_id == VDC5_LAYER_ID_VIN_RD) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckLayerId() */
+
+/**************************************************************************//**
+ * @brief       Checks on layer ID related to graphics
+ * @param[in]   layer_id        : Layer ID
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckGraphicsTypeLayerId (const vdc5_layer_id_t layer_id)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    if ((layer_id < VDC5_LAYER_ID_0_RD) || (layer_id > VDC5_LAYER_ID_OIR_RD)) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+    if (layer_id == VDC5_LAYER_ID_VIN_RD) {
+        error = VDC5_ERR_PARAM_LAYER_ID;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckGraphicsTypeLayerId() */
+
+/**************************************************************************//**
+ * @brief       Checks on horizontal/vertical timing of the VDC5 signals
+ * @param[in]   rect            : Horizontal/vertical timing of the VDC5 signals
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckRect (const vdc5_period_rect_t * const rect)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Vertical start position */
+    if (((uint32_t)rect->vs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if ((uint32_t)rect->vs < (uint32_t)VDC5_CPARA_VS_MIN) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Height (vertical width) */
+    if (((uint32_t)rect->vw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)rect->vs + (uint32_t)rect->vw) > (uint32_t)VDC5_CPARA_VS_VW_MAX) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+
+    /* Horizontal start position */
+    if (((uint32_t)rect->hs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if ((uint32_t)rect->hs < (uint32_t)VDC5_CPARA_HS_MIN) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+    /* Horizontal width */
+    if (((uint32_t)rect->hw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    if (((uint32_t)rect->hs + (uint32_t)rect->hw) > (uint32_t)VDC5_CPARA_HS_HW_MAX) {
+        error = VDC5_ERR_PARAM_EXCEED_RANGE;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckRect() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for horizontal panel driver signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_Horizontal (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_Horizontal() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for horizontal panel driver signal (POLA/POLB)
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_HorizontalPol (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* POLA/POLB signal generation mode select */
+    if (lcd_tcon_timing->tcon_md >= VDC5_LCD_TCON_POLMD_NUM) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_HorizontalPol() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for vertical panel driver signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_Vertical (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* Signal pulse start position */
+    if (((uint32_t)lcd_tcon_timing->tcon_hsvs & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* Pulse width */
+    if (((uint32_t)lcd_tcon_timing->tcon_hwvw & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+        error = VDC5_ERR_PARAM_BIT_WIDTH;
+        goto END;
+    }
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_Vertical() */
+
+/**************************************************************************//**
+ * @brief       Checks on LCD TCON timing signal parameter for DE timing signal
+ * @param[in]   lcd_tcon_timing : LCD TCON timing signal parameter
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckTcon_DataEnable (const vdc5_lcd_tcon_timing_t * const lcd_tcon_timing)
+{
+    vdc5_error_t error;
+
+    error = VDC5_OK;
+
+    /* LCD TCON output pin select */
+    if ((lcd_tcon_timing->tcon_pin < VDC5_LCD_TCON_PIN_NON) || (lcd_tcon_timing->tcon_pin >= VDC5_LCD_TCON_PIN_NUM)) {
+        error = VDC5_ERR_PARAM_UNDEFINED;
+        goto END;
+    }
+END:
+    return error;
+}   /* End of function CheckTcon_DataEnable() */
+
+/**************************************************************************//**
+ * @brief       Checks on gain adjustment of area 0 to 31 of G/B/R signal
+ * @param[in]   gam_gain        : Gain adjustment of area 0 to 31 of G/B/R signal
+ * @retval      Error code
+******************************************************************************/
+static vdc5_error_t CheckGammaCrct_GainAdjustment (const uint16_t * gam_gain)
+{
+    uint32_t        gain_index;
+    vdc5_error_t    error;
+
+    error = VDC5_OK;
+
+    if (gam_gain != NULL) {
+        for (gain_index = 0; gain_index < VDC5_GAM_GAIN_ADJ_NUM; gain_index++) {
+            if (((uint32_t)*gam_gain & (uint32_t)~VDC5_CPARA_RANGE_0X000007FF) != 0u) {
+                error = VDC5_ERR_PARAM_BIT_WIDTH;
+                goto END;
+            }
+            gam_gain++;
+        }
+    }
+END:
+    return error;
+}   /* End of function CheckGammaCrct_GainAdjustment() */
+
+#endif      /* R_VDC5_CHECK_PARAMETERS */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdc5/src/r_vdc5_check_parameter.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,123 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_check_parameter.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver parameter check definitions
+******************************************************************************/
+
+#ifndef R_VDC5_CHECK_PARAMETER_H
+#define R_VDC5_CHECK_PARAMETER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+
+
+#ifdef      R_VDC5_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+vdc5_error_t VDC5_InitializeCheckPrm(const vdc5_channel_t ch, const vdc5_init_t * const param);
+vdc5_error_t VDC5_TerminateCheckPrm(const vdc5_channel_t ch);
+vdc5_error_t VDC5_VideoInputCheckPrm(const vdc5_channel_t ch, const vdc5_input_t * const param);
+vdc5_error_t VDC5_SyncControlCheckPrm(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+vdc5_error_t VDC5_DisplayOutputCheckPrm(const vdc5_channel_t ch, const vdc5_output_t * const param);
+vdc5_error_t VDC5_CallbackISRCheckPrm(const vdc5_channel_t ch, const vdc5_int_t * const param);
+vdc5_error_t VDC5_WriteDataControlCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_write_t  * const param);
+vdc5_error_t VDC5_ChangeWriteProcessCheckPrm(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_write_chg_t  * const param);
+vdc5_error_t VDC5_ReadDataControlCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param);
+vdc5_error_t VDC5_ChangeReadProcessCheckPrm(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_read_chg_t   * const param);
+vdc5_error_t VDC5_StartProcessCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_start_t  * const param);
+vdc5_error_t VDC5_StopProcessCheckPrm(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t VDC5_ReleaseDataControlCheckPrm(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_error_t VDC5_VideoNoiseReductCheckPrm(const vdc5_channel_t ch, const vdc5_noise_reduction_t * const param);
+vdc5_error_t VDC5_ImageColorMatrixCheckPrm(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
+vdc5_error_t VDC5_ImageEnhancementCheckPrm(
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_period_rect_t    * const enh_area);
+vdc5_error_t VDC5_ImageBlackStretchCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_black_t  * const param);
+vdc5_error_t VDC5_AlphaBlendingCheckPrm(
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_alpha_blending_t * const param);
+vdc5_error_t VDC5_AlphaBlendingRectCheckPrm(
+    const vdc5_channel_t                        ch,
+    const vdc5_layer_id_t                       layer_id,
+    const vdc5_alpha_blending_rect_t    * const param);
+vdc5_error_t VDC5_ChromakeyCheckPrm(
+    const vdc5_channel_t            ch,
+    const vdc5_layer_id_t           layer_id,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_chromakey_t  * const param);
+vdc5_error_t VDC5_CLUTCheckPrm(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_clut_t   * const param);
+vdc5_error_t VDC5_DisplayCalibrationCheckPrm(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
+vdc5_error_t VDC5_GammaCorrectionCheckPrm(const vdc5_channel_t ch, const vdc5_gamma_correction_t * const param);
+
+
+#endif      /* R_VDC5_CHECK_PARAMETERS */
+
+#endif  /* R_VDC5_CHECK_PARAMETER_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdc5/src/r_vdc5_interrupt.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1672 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_interrupt.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver interrupt related processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     UNUSED_PARAM(param)             (void)(param)
+
+#define VDC5_INT_BIT_S0_VI_VSYNC    ((uint32_t)0x00000001u)
+#define VDC5_INT_BIT_S0_LO_VSYNC    ((uint32_t)0x00000010u)
+#define VDC5_INT_BIT_S0_VSYNCERR    ((uint32_t)0x00000100u)
+#define VDC5_INT_BIT_VLINE          ((uint32_t)0x00001000u)
+#define VDC5_INT_BIT_S0_VFIELD      ((uint32_t)0x00010000u)
+#define VDC5_INT_BIT_IV1_VBUFERR    ((uint32_t)0x00100000u)
+#define VDC5_INT_BIT_IV3_VBUFERR    ((uint32_t)0x01000000u)
+#define VDC5_INT_BIT_IV5_VBUFERR    ((uint32_t)0x10000000u)
+#define VDC5_INT_BIT_IV6_VBUFERR    ((uint32_t)0x00000001u)
+#define VDC5_INT_BIT_S0_WLINE       ((uint32_t)0x00000010u)
+#define VDC5_INT_BIT_S1_VI_VSYNC    ((uint32_t)0x00000100u)
+#define VDC5_INT_BIT_S1_LO_VSYNC    ((uint32_t)0x00001000u)
+#define VDC5_INT_BIT_S1_VSYNCERR    ((uint32_t)0x00010000u)
+#define VDC5_INT_BIT_S1_VFIELD      ((uint32_t)0x00100000u)
+#define VDC5_INT_BIT_IV2_VBUFERR    ((uint32_t)0x01000000u)
+#define VDC5_INT_BIT_IV4_VBUFERR    ((uint32_t)0x10000000u)
+#define VDC5_INT_BIT_S1_WLINE       ((uint32_t)0x00000001u)
+#define VDC5_INT_BIT_OIR_VI_VSYNC   ((uint32_t)0x00000010u)
+#define VDC5_INT_BIT_OIR_LO_VSYNC   ((uint32_t)0x00000100u)
+#define VDC5_INT_BIT_OIR_VLINE      ((uint32_t)0x00001000u)
+#define VDC5_INT_BIT_OIR_VFIELD     ((uint32_t)0x00010000u)
+#define VDC5_INT_BIT_IV7_VBUFERR    ((uint32_t)0x00100000u)
+#define VDC5_INT_BIT_IV8_VBUFERR    ((uint32_t)0x01000000u)
+
+#define VDC5_GR_UPDATE_P_VEN_BIT    ((uint32_t)0x00000010u)
+#define VDC5_SCL0_UPDATE_VEN_A_BIT  ((uint32_t)0x00000001u)
+
+/* Valid bit range */
+#define VDC5_INT_RANGE_0X000007FF   (0x000007FFu)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void VDC5_Ch0_s0_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv1_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv3_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv5_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv6_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s0_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv2_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv4_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_s1_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_oir_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv7_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch0_iv8_vbuferr_ISR(const uint32_t int_sense);
+
+static void VDC5_Ch1_s0_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv1_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv3_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv5_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv6_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s0_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_vsyncerr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv2_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv4_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_s1_wline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_vi_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_lo_vsync_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_vline_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_oir_vfield_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv7_vbuferr_ISR(const uint32_t int_sense);
+static void VDC5_Ch1_iv8_vbuferr_ISR(const uint32_t int_sense);
+
+/*! List of the callback function pointers */
+static void (*vdc5_int_callback[VDC5_CHANNEL_NUM][VDC5_INT_TYPE_NUM])(vdc5_int_type_t int_type);
+
+
+/**************************************************************************//**
+ * @brief       Interrupt service routine acquisition processing
+ *
+ *              Description:<br>
+ *              This function returns the function pointer to the specified interrupt service routine.
+ * @param[in]   ch                              : Channel
+ * @param[in]   type                            : VDC5 interrupt type
+ * @retval      VDC5 Interrupt service routine
+ *****************************************************************************/
+void (*R_VDC5_GetISR (const vdc5_channel_t ch, const vdc5_int_type_t type))(const uint32_t int_sense)
+{
+    static void (* const isr_table[VDC5_CHANNEL_NUM][VDC5_INT_TYPE_NUM])(const uint32_t int_sense) = {
+        {
+            &VDC5_Ch0_s0_vi_vsync_ISR,
+            &VDC5_Ch0_s0_lo_vsync_ISR,
+            &VDC5_Ch0_s0_vsyncerr_ISR,
+            &VDC5_Ch0_vline_ISR,
+            &VDC5_Ch0_s0_vfield_ISR,
+            &VDC5_Ch0_iv1_vbuferr_ISR,
+            &VDC5_Ch0_iv3_vbuferr_ISR,
+            &VDC5_Ch0_iv5_vbuferr_ISR,
+            &VDC5_Ch0_iv6_vbuferr_ISR,
+            &VDC5_Ch0_s0_wline_ISR,
+            &VDC5_Ch0_s1_vi_vsync_ISR,
+            &VDC5_Ch0_s1_lo_vsync_ISR,
+            &VDC5_Ch0_s1_vsyncerr_ISR,
+            &VDC5_Ch0_s1_vfield_ISR,
+            &VDC5_Ch0_iv2_vbuferr_ISR,
+            &VDC5_Ch0_iv4_vbuferr_ISR,
+            &VDC5_Ch0_s1_wline_ISR,
+            &VDC5_Ch0_oir_vi_vsync_ISR,
+            &VDC5_Ch0_oir_lo_vsync_ISR,
+            &VDC5_Ch0_oir_vline_ISR,
+            &VDC5_Ch0_oir_vfield_ISR,
+            &VDC5_Ch0_iv7_vbuferr_ISR,
+            &VDC5_Ch0_iv8_vbuferr_ISR
+        },
+        {
+            &VDC5_Ch1_s0_vi_vsync_ISR,
+            &VDC5_Ch1_s0_lo_vsync_ISR,
+            &VDC5_Ch1_s0_vsyncerr_ISR,
+            &VDC5_Ch1_vline_ISR,
+            &VDC5_Ch1_s0_vfield_ISR,
+            &VDC5_Ch1_iv1_vbuferr_ISR,
+            &VDC5_Ch1_iv3_vbuferr_ISR,
+            &VDC5_Ch1_iv5_vbuferr_ISR,
+            &VDC5_Ch1_iv6_vbuferr_ISR,
+            &VDC5_Ch1_s0_wline_ISR,
+            &VDC5_Ch1_s1_vi_vsync_ISR,
+            &VDC5_Ch1_s1_lo_vsync_ISR,
+            &VDC5_Ch1_s1_vsyncerr_ISR,
+            &VDC5_Ch1_s1_vfield_ISR,
+            &VDC5_Ch1_iv2_vbuferr_ISR,
+            &VDC5_Ch1_iv4_vbuferr_ISR,
+            &VDC5_Ch1_s1_wline_ISR,
+            &VDC5_Ch1_oir_vi_vsync_ISR,
+            &VDC5_Ch1_oir_lo_vsync_ISR,
+            &VDC5_Ch1_oir_vline_ISR,
+            &VDC5_Ch1_oir_vfield_ISR,
+            &VDC5_Ch1_iv7_vbuferr_ISR,
+            &VDC5_Ch1_iv8_vbuferr_ISR
+        }
+    };
+    void (* isr_function)(const uint32_t int_sense);
+
+    isr_function = isr_table[ch][type];
+
+#ifdef  R_VDC5_CHECK_PARAMETERS
+    /* Channel and interrupt type */
+    if ((ch >= VDC5_CHANNEL_NUM) || (type >= VDC5_INT_TYPE_NUM)) {
+        isr_function = 0;
+    }
+#endif  /* R_VDC5_CHECK_PARAMETERS */
+
+    return isr_function;
+}   /* End of function R_VDC5_GetISR() */
+
+/**************************************************************************//**
+ * @brief       Disables all VDC5 interrupts
+ * @param[in]   ch                      : Channel
+ * @retval      None
+ *****************************************************************************/
+void VDC5_Int_Disable (const vdc5_channel_t ch)
+{
+    const vdc5_regaddr_system_ctrl_t  * system_ctrl;
+    int32_t                             int_type;
+
+    system_ctrl = &vdc5_regaddr_system_ctrl[ch];
+
+    for (int_type = 0; int_type < VDC5_INT_TYPE_NUM; int_type++) {
+        vdc5_int_callback[ch][int_type] = 0;
+    }
+    /* Interrupt output off */
+    *(system_ctrl->syscnt_int4) = 0u;
+    *(system_ctrl->syscnt_int5) = 0u;
+    *(system_ctrl->syscnt_int6) = 0u;
+
+}   /* End of function VDC5_Int_Disable() */
+
+/**************************************************************************//**
+ * @brief       Enables/disables the specified VDC5 interrupt
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Interrupt callback setup parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_Int_SetInterrupt (const vdc5_channel_t ch, const vdc5_int_t * const param)
+{
+    volatile uint32_t     * int_clhd_reg;
+    volatile uint32_t     * int_onoff_reg;
+    volatile uint32_t     * linenum_reg;
+    volatile uint16_t     * linenum16_reg;
+    volatile uint32_t     * linenum_update_reg;
+    uint32_t                mask_bit;
+    uint32_t                reg_data;
+    static const uint32_t   interrupt_bit_table[VDC5_INT_TYPE_NUM] = {
+        VDC5_INT_BIT_S0_VI_VSYNC,
+        VDC5_INT_BIT_S0_LO_VSYNC,
+        VDC5_INT_BIT_S0_VSYNCERR,
+        VDC5_INT_BIT_VLINE,
+        VDC5_INT_BIT_S0_VFIELD,
+        VDC5_INT_BIT_IV1_VBUFERR,
+        VDC5_INT_BIT_IV3_VBUFERR,
+        VDC5_INT_BIT_IV5_VBUFERR,
+        VDC5_INT_BIT_IV6_VBUFERR,
+        VDC5_INT_BIT_S0_WLINE,
+        VDC5_INT_BIT_S1_VI_VSYNC,
+        VDC5_INT_BIT_S1_LO_VSYNC,
+        VDC5_INT_BIT_S1_VSYNCERR,
+        VDC5_INT_BIT_S1_VFIELD,
+        VDC5_INT_BIT_IV2_VBUFERR,
+        VDC5_INT_BIT_IV4_VBUFERR,
+        VDC5_INT_BIT_S1_WLINE,
+        VDC5_INT_BIT_OIR_VI_VSYNC,
+        VDC5_INT_BIT_OIR_LO_VSYNC,
+        VDC5_INT_BIT_OIR_VLINE,
+        VDC5_INT_BIT_OIR_VFIELD,
+        VDC5_INT_BIT_IV7_VBUFERR,
+        VDC5_INT_BIT_IV8_VBUFERR
+    };
+
+    if (param->type < VDC5_INT_TYPE_IV6_VBUFERR) {
+        /* INT0: VDC5_INT_TYPE_S0_VI_VSYNC ~ INT7: VDC5_INT_TYPE_IV5_VBUFERR */
+        int_clhd_reg  = vdc5_regaddr_system_ctrl[ch].syscnt_int1;
+        int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int4;
+    } else if (param->type < VDC5_INT_TYPE_S1_WLINE) {
+        /* INT8: VDC5_INT_TYPE_IV6_VBUFERR ~ INT15: VDC5_INT_TYPE_IV4_VBUFERR */
+        int_clhd_reg  = vdc5_regaddr_system_ctrl[ch].syscnt_int2;
+        int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int5;
+    } else {
+        /* INT16: VDC5_INT_TYPE_S1_WLINE ~ INT22: VDC5_INT_TYPE_IV8_VBUFERR */
+        int_clhd_reg  = vdc5_regaddr_system_ctrl[ch].syscnt_int3;
+        int_onoff_reg = vdc5_regaddr_system_ctrl[ch].syscnt_int6;
+    }
+    mask_bit = interrupt_bit_table[param->type];
+
+    /* Interrupt callback function pointer */
+    vdc5_int_callback[ch][param->type] = param->callback;
+
+    if (param->callback != 0) {
+        /* ON */
+        if ((*int_onoff_reg & mask_bit) == 0u) {
+            /* OFF to ON */
+            *int_onoff_reg |= mask_bit;
+            reg_data        = *int_onoff_reg;
+            *int_clhd_reg   = reg_data;
+        }
+
+        if (param->type == VDC5_INT_TYPE_VLINE) {
+            /* Specified line signal for panel output in graphics 3 */
+            linenum_reg         = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_clut;
+            linenum_update_reg  = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
+            *linenum_reg        &= (uint32_t)~VDC5_INT_RANGE_0X000007FF;
+            *linenum_reg        |= (uint32_t)param->line_num;
+            *linenum_update_reg |= VDC5_GR_UPDATE_P_VEN_BIT;
+        } else if (param->type == VDC5_INT_TYPE_S0_WLINE) {
+            /* Write specification line signal input to scaling-down control block in scaler 0 */
+            linenum16_reg       = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_int;
+            linenum_update_reg  = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_update;
+            *linenum16_reg       = param->line_num;
+            *linenum_update_reg |= VDC5_SCL0_UPDATE_VEN_A_BIT;
+        } else if (param->type == VDC5_INT_TYPE_S1_WLINE) {
+            /* Write specification line signal input to scaling-down control block in scaler 1 */
+            linenum16_reg       = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_int;
+            linenum_update_reg  = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_update;
+            *linenum16_reg       = param->line_num;
+            *linenum_update_reg |= VDC5_SCL0_UPDATE_VEN_A_BIT;
+        } else if (param->type == VDC5_INT_TYPE_OIR_VLINE) {
+            /* Specified line signal for panel output in output image generator */
+            linenum_reg         = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_clut;
+            linenum_update_reg  = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
+            *linenum_reg        &= (uint32_t)~VDC5_INT_RANGE_0X000007FF;
+            *linenum_reg        |= (uint32_t)param->line_num;
+            *linenum_update_reg |= VDC5_GR_UPDATE_P_VEN_BIT;
+        } else {
+            /* Do nothing */
+        }
+    } else {
+        /* OFF */
+        *int_onoff_reg &= (uint32_t)~mask_bit;
+        reg_data        = *int_onoff_reg;
+        *int_clhd_reg   = reg_data;
+    }
+
+}   /* End of function VDC5_Int_Disable() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VI_VSYNC](VDC5_INT_TYPE_S0_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_LO_VSYNC](VDC5_INT_TYPE_S0_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VSYNCERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vsyncerr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VSYNCERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VSYNCERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VSYNCERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VSYNCERR](VDC5_INT_TYPE_S0_VSYNCERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 VLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_vline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_VLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_VLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_VLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_VLINE](VDC5_INT_TYPE_VLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_VFIELD](VDC5_INT_TYPE_S0_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV1_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv1_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV1_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV1_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV1_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV1_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV1_VBUFERR](VDC5_INT_TYPE_IV1_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv1_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV3_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv3_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV3_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV3_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV3_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV3_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV3_VBUFERR](VDC5_INT_TYPE_IV3_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv3_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV5_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv5_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV5_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV5_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV5_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV5_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV5_VBUFERR](VDC5_INT_TYPE_IV5_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv5_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV6_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv6_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV6_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV6_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV6_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV6_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV6_VBUFERR](VDC5_INT_TYPE_IV6_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv6_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_WLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s0_wline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_WLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_WLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_WLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S0_WLINE](VDC5_INT_TYPE_S0_WLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s0_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VI_VSYNC](VDC5_INT_TYPE_S1_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s1_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_LO_VSYNC](VDC5_INT_TYPE_S1_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s1_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VSYNCERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_vsyncerr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VSYNCERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VSYNCERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VSYNCERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VSYNCERR](VDC5_INT_TYPE_S1_VSYNCERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s1_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_VFIELD](VDC5_INT_TYPE_S1_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s1_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV2_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv2_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV2_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV2_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV2_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV2_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV2_VBUFERR](VDC5_INT_TYPE_IV2_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv2_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV4_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv4_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV4_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV4_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV4_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV4_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV4_VBUFERR](VDC5_INT_TYPE_IV4_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv4_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_WLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_s1_wline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_WLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_WLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_WLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_S1_WLINE](VDC5_INT_TYPE_S1_WLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_s1_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VI_VSYNC](VDC5_INT_TYPE_OIR_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_oir_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_LO_VSYNC](VDC5_INT_TYPE_OIR_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_oir_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_vline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VLINE](VDC5_INT_TYPE_OIR_VLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_oir_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_oir_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_OIR_VFIELD](VDC5_INT_TYPE_OIR_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_oir_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV7_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv7_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV7_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV7_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV7_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV7_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV7_VBUFERR](VDC5_INT_TYPE_IV7_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv7_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV8_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch0_iv8_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_0].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV8_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV8_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV8_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV8_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_0][VDC5_INT_TYPE_IV8_VBUFERR](VDC5_INT_TYPE_IV8_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch0_iv8_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VI_VSYNC](VDC5_INT_TYPE_S0_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s0_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_LO_VSYNC](VDC5_INT_TYPE_S0_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s0_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VSYNCERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_vsyncerr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VSYNCERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VSYNCERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VSYNCERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VSYNCERR](VDC5_INT_TYPE_S0_VSYNCERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s0_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 VLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_vline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_VLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_VLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_VLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_VLINE](VDC5_INT_TYPE_VLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_VFIELD](VDC5_INT_TYPE_S0_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s0_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV1_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv1_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV1_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV1_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV1_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV1_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV1_VBUFERR](VDC5_INT_TYPE_IV1_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv1_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV3_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv3_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV3_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV3_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV3_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV3_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV3_VBUFERR](VDC5_INT_TYPE_IV3_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv3_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV5_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv5_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int1;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int4;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV5_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV5_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV5_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV5_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV5_VBUFERR](VDC5_INT_TYPE_IV5_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv5_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV6_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv6_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV6_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV6_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV6_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV6_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV6_VBUFERR](VDC5_INT_TYPE_IV6_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv6_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S0_WLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s0_wline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S0_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S0_WLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S0_WLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_WLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S0_WLINE](VDC5_INT_TYPE_S0_WLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s0_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VI_VSYNC](VDC5_INT_TYPE_S1_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s1_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_LO_VSYNC](VDC5_INT_TYPE_S1_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s1_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VSYNCERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_vsyncerr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VSYNCERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VSYNCERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VSYNCERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VSYNCERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VSYNCERR](VDC5_INT_TYPE_S1_VSYNCERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s1_vsyncerr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_VFIELD](VDC5_INT_TYPE_S1_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s1_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV2_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv2_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV2_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV2_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV2_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV2_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV2_VBUFERR](VDC5_INT_TYPE_IV2_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv2_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV4_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv4_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int2;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int5;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV4_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV4_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV4_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV4_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV4_VBUFERR](VDC5_INT_TYPE_IV4_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv4_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 S1_WLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_s1_wline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_S1_WLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_S1_WLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_S1_WLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_WLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_S1_WLINE](VDC5_INT_TYPE_S1_WLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_s1_wline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VI_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_vi_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VI_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VI_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VI_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VI_VSYNC](VDC5_INT_TYPE_OIR_VI_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_oir_vi_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_LO_VSYNC interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_lo_vsync_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_LO_VSYNC) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_LO_VSYNC;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_LO_VSYNC] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_LO_VSYNC](VDC5_INT_TYPE_OIR_LO_VSYNC);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_oir_lo_vsync_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VLINE interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_vline_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VLINE) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VLINE) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VLINE;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VLINE] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VLINE](VDC5_INT_TYPE_OIR_VLINE);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_oir_vline_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 OIR_VFIELD interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_oir_vfield_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_OIR_VFIELD) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_OIR_VFIELD) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_OIR_VFIELD;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VFIELD] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_OIR_VFIELD](VDC5_INT_TYPE_OIR_VFIELD);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_oir_vfield_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV7_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv7_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV7_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV7_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV7_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV7_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV7_VBUFERR](VDC5_INT_TYPE_IV7_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv7_vbuferr_ISR() */
+
+/**************************************************************************//**
+ * @brief       VDC5 IV8_VBUFERR interrupt service routine
+ * @param[in]   int_sense
+ * @retval      None
+ *****************************************************************************/
+static void VDC5_Ch1_iv8_vbuferr_ISR (const uint32_t int_sense)
+{
+    uint32_t            IntState;
+    volatile uint32_t * int_clhd_reg;
+    volatile uint32_t * int_onoff_reg;
+
+    UNUSED_PARAM(int_sense);
+
+    int_clhd_reg  = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int3;
+    int_onoff_reg = vdc5_regaddr_system_ctrl[VDC5_CHANNEL_1].syscnt_int6;
+    IntState      = *int_onoff_reg;
+
+    if (((IntState & VDC5_INT_BIT_IV8_VBUFERR) != 0u) && ((*int_clhd_reg & VDC5_INT_BIT_IV8_VBUFERR) != 0u)) {
+        /* Clear */
+        *int_clhd_reg = IntState & ~VDC5_INT_BIT_IV8_VBUFERR;
+
+        if (vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV8_VBUFERR] != 0) {
+            vdc5_int_callback[VDC5_CHANNEL_1][VDC5_INT_TYPE_IV8_VBUFERR](VDC5_INT_TYPE_IV8_VBUFERR);
+        }
+        /* Set */
+        *int_clhd_reg = IntState;
+    }
+}   /* End of function VDC5_Ch1_iv8_vbuferr_ISR() */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdc5/src/r_vdc5_register.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,3785 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_register.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver register setup processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+#include    "r_vdc5_shared_param.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     INITIAL_SCALING_PHASE          ((uint32_t)2048u)
+#define     SCALING_RATIO_SAME_SIZE        (4096u)
+/* Vsync signal delay control for OIR */
+#define     OIR_VSYNC_DELAY                 ((uint32_t)1u)
+
+#define     LVDS_LPHYACC_VALUE              ((uint32_t)0x0001u)
+
+/* Panel clock frequency division ratio */
+#define     VDC5_REG_CLKDIV_1_1            (1u)
+#define     VDC5_REG_CLKDIV_1_2            (2u)
+#define     VDC5_REG_CLKDIV_1_3            (3u)
+#define     VDC5_REG_CLKDIV_1_4            (4u)
+#define     VDC5_REG_CLKDIV_1_5            (5u)
+#define     VDC5_REG_CLKDIV_1_6            (6u)
+#define     VDC5_REG_CLKDIV_1_7            (7u)
+#define     VDC5_REG_CLKDIV_1_8            (8u)
+#define     VDC5_REG_CLKDIV_1_9            (9u)
+#define     VDC5_REG_CLKDIV_1_12           (12u)
+#define     VDC5_REG_CLKDIV_1_16           (16u)
+#define     VDC5_REG_CLKDIV_1_24           (24u)
+#define     VDC5_REG_CLKDIV_1_32           (32u)
+/* Panel clock select */
+#define     VDC5_REG_ICKSEL_IMG            (0x0000u)
+#define     VDC5_REG_ICKSEL_IMG_DV         (0x0000u)
+#define     VDC5_REG_ICKSEL_EXT_0          (0x1000u)
+#define     VDC5_REG_ICKSEL_EXT_1          (0x2000u)
+#define     VDC5_REG_ICKSEL_PERI           (0x3000u)
+#define     VDC5_REG_ICKSEL_LVDS           (0x0400u)
+#define     VDC5_REG_ICKSEL_LVDS_DIV7      (0x0800u)
+/* Output pin edge select */
+#define     VDC5_REG_TCON0_EDGE            (0x0040u)
+#define     VDC5_REG_TCON1_EDGE            (0x0020u)
+#define     VDC5_REG_TCON2_EDGE            (0x0010u)
+#define     VDC5_REG_TCON3_EDGE            (0x0008u)
+#define     VDC5_REG_TCON4_EDGE            (0x0004u)
+#define     VDC5_REG_TCON5_EDGE            (0x0002u)
+#define     VDC5_REG_TCON6_EDGE            (0x0001u)
+/* Panel dither output format select */
+#define     VDC5_REG_PATH_FORMAT_RGB888    (0x00000000u)
+#define     VDC5_REG_PATH_FORMAT_RGB666    (0x00010000u)
+#define     VDC5_REG_PATH_FORMAT_RGB565    (0x00020000u)
+#define     VDC5_REG_PATH_FORMAT_NON       (0x00000000u)
+/* Calculate scaling ratio use value */
+#define     VDC5_REG_FLOAT_1_0 (1.0f)
+#define     VDC5_REG_FLOAT_0_5 (0.5f)
+/* bits per pixel */
+#define     VDC5_REG_BIT_PER_PIXEL_RGB565    (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_RGB888    (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_ARGB1555  (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_ARGB4444  (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_ARGB8888  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_CLUT8     (8u)
+#define     VDC5_REG_BIT_PER_PIXEL_CLUT4     (4u)
+#define     VDC5_REG_BIT_PER_PIXEL_CLUT1     (1u)
+#define     VDC5_REG_BIT_PER_PIXEL_YCBCR422  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_YCBCR444  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_RGBA5551  (16u)
+#define     VDC5_REG_BIT_PER_PIXEL_RGBA8888  (32u)
+#define     VDC5_REG_BIT_PER_PIXEL_VALUE_8   (8u)
+/* Convert the color data from 4 bits value into 8 bits value */
+#define     VDC5_REG_EXTENSION_VALUE_17      (17u)
+/* Convert the color data from 5 bits value into 8 bits value */
+#define     VDC5_REG_EXTENSION_VALUE_263     (263u)
+#define     VDC5_REG_EXTENSION_VALUE_32      (32u)
+/* Convert the color data from 6 bits value into 8 bits value */
+#define     VDC5_REG_EXTENSION_VALUE_259     (259u)
+#define     VDC5_REG_EXTENSION_VALUE_64      (64u)
+/* Round off */
+#define     VDC5_REG_ROUND_OFF_VALUE_1       (1u)
+#define     VDC5_REG_ROUND_OFF_VALUE_2       (2u)
+/* Color mask data */
+#define     VDC5_REG_ALPHA_8BIT              (0xFF000000u)
+#define     VDC5_REG_RGB_24BIT_MASK          (0x00FFFFFFu)
+#define     VDC5_REG_COLOR_8BIT_MASK         (0x000000FFu)
+#define     VDC5_REG_COLOR_6BIT_MASK         (0x0000003Fu)
+#define     VDC5_REG_COLOR_5BIT_MASK         (0x0000001Fu)
+#define     VDC5_REG_COLOR_4BIT_MASK         (0x0000000Fu)
+#define     VDC5_REG_ARGB8888_GB_MASK        (0x00FFFF00u)
+
+/* RGB565 bits mask data */
+#define     VDC5_REG_RGB565_R_MASK           (0x0000F800u)
+#define     VDC5_REG_RGB565_G_MASK           (0x000007E0u)
+#define     VDC5_REG_RGB565_B_MASK           (0x0000001Fu)
+/* ARGB4444 bits mask data */
+#define     VDC5_REG_ARGB4444_R_MASK         (0x00000F00u)
+#define     VDC5_REG_ARGB4444_G_MASK         (0x000000F0u)
+#define     VDC5_REG_ARGB4444_B_MASK         (0x0000000Fu)
+/* ARGB1555 bits mask data */
+#define     VDC5_REG_ARGB1555_R_MASK         (0x00007C00u)
+#define     VDC5_REG_ARGB1555_G_MASK         (0x000003E0u)
+#define     VDC5_REG_ARGB1555_B_MASK         (0x0000001Fu)
+/* RGBA5551 bits mask data */
+#define     VDC5_REG_RGBA5551_R_MASK         (0x0000F800u)
+#define     VDC5_REG_RGBA5551_G_MASK         (0x000007C0u)
+#define     VDC5_REG_RGBA5551_B_MASK         (0x0000003Eu)
+
+/* bit pattern */
+#define     VDC5_REG_BIT31          (0x80000000u)
+#define     VDC5_REG_BIT29          (0x20000000u)
+#define     VDC5_REG_BIT28          (0x10000000u)
+#define     VDC5_REG_BIT24          (0x01000000u)
+#define     VDC5_REG_BIT20          (0x00100000u)
+#define     VDC5_REG_BIT16          (0x00010000u)
+#define     VDC5_REG_BIT15          (0x00008000u)
+#define     VDC5_REG_BIT14          (0x00004000u)
+#define     VDC5_REG_BIT13          (0x00002000u)
+#define     VDC5_REG_BIT12          (0x00001000u)
+#define     VDC5_REG_BIT8           (0x00000100u)
+#define     VDC5_REG_BIT4           (0x00000010u)
+#define     VDC5_REG_BIT2           (0x00000004u)
+#define     VDC5_REG_BIT1           (0x00000002u)
+#define     VDC5_REG_BIT0           (0x00000001u)
+
+/* shift value */
+#define     VDC5_REG_SHIFT_28       (28u)
+#define     VDC5_REG_SHIFT_24       (24u)
+#define     VDC5_REG_SHIFT_20       (20u)
+#define     VDC5_REG_SHIFT_16       (16u)
+#define     VDC5_REG_SHIFT_13       (13u)
+#define     VDC5_REG_SHIFT_12       (12u)
+#define     VDC5_REG_SHIFT_11       (11u)
+#define     VDC5_REG_SHIFT_10       (10u)
+#define     VDC5_REG_SHIFT_8        (8u)
+#define     VDC5_REG_SHIFT_6        (6u)
+#define     VDC5_REG_SHIFT_5        (5u)
+#define     VDC5_REG_SHIFT_4        (4u)
+#define     VDC5_REG_SHIFT_2        (2u)
+#define     VDC5_REG_SHIFT_1        (1u)
+
+/* register set value */
+#define VDC5_REG_BIT_0XFFFF0000     (0xFFFF0000u) /* scaler_0->scl0_frc2                     */
+/* scaler_1->scl0_frc2                     */
+/* register mask value */
+#define VDC5_REG_MASK_0XF7FF1C3F    (0xF7FF1C3Fu) /* mask img_synthesizer->gr_flm6           */
+#define VDC5_REG_MASK_0X0000D000    (0x0000D000u) /* mask img_synthesizer->gr_ab1            */
+#define VDC5_REG_MASK_0X01FF00FF    (0x01FF00FFu) /* mask img_synthesizer->gr_ab6            */
+#define VDC5_REG_MASK_0X0000007F    (0x0000007Fu) /* mask output_ctrl->out_clk_phase         */
+#define VDC5_REG_MASK_0X11003313    (0x11003313u) /* mask output_ctrl->out_set               */
+#define VDC5_REG_MASK_0X00030000    (0x00030000u) /* mask output_ctrl->out_pdtha             */
+#define VDC5_REG_MASK_0X0007000D    (0x0007000Du) /* mask scaler->scl1_wr1                   */
+#define VDC5_REG_MASK_0X00000300    (0x00000300u) /* mask scaler->scl1_wr5                   */
+#define VDC5_REG_MASK_0X0703FF02    (0x0703FF02u) /* mask regaddr_lvds->lclkselr             */
+#define VDC5_REG_MASK_0X07FF1F30    (0x07FF1F30u) /* mask regaddr_lvds->lpllsetr             */
+#define VDC5_REG_MASK_0X00010301    (0x00010301u) /* mask img_synthesizer->gr_flm1           */
+#define VDC5_REG_MASK_0X7FFF03FF    (0x7FFF03FFu) /* mask img_synthesizer->gr_flm3           */
+#define VDC5_REG_MASK_0X0000E000    (0x0000E000u) /* mask img_synthesizer->gr_flm6           */
+#define VDC5_REG_MASK_0X00007F33    (0x00007F33u) /* mask input_ctrl->imgcnt_nr_cnt0         */
+#define VDC5_REG_MASK_0X00FF0000    (0x00FF0000u) /* mask img_synthesizer->gr_ab7            */
+#define VDC5_REG_MASK_0X00300000    (0x00300000u) /* mask output_ctrl->out_pdtha             */
+#define VDC5_REG_MASK_0X00003333    (0x00003333u) /* mask output_ctrl->out_pdtha             */
+#define VDC5_REG_MASK_0X00007111    (0x00007111u) /* mask input_ctrl->inp_sel_cnt            */
+#define VDC5_REG_MASK_0X11110113    (0x11110113u) /* mask input_ctrl->inp_ext_sync_cnt       */
+#define VDC5_REG_MASK_0X000007FF    (0x000007FFu) /* mask img_synthesizer->gr_flm5           */
+#define VDC5_REG_MASK_0X0000FFFF    (0x0000FFFFu) /* mask scaler->scl0_ds4                   */
+/*      caler->scl0_us5                    */
+#define VDC5_REG_MASK_0X00000011    (0x00000011u) /* mask scaler->scl0_ds1                   */
+/*      scaler->scl0_us1                   */
+#define VDC5_REG_MASK_0X00000070    (0x00000070u) /* mask scaler->scl1_wr1                   */
+#define VDC5_REG_MASK_0X00000080    (0x00000080u) /* mask scaler->scl1_wr1                   */
+#define VDC5_REG_MASK_0X00003110    (0x00003110u) /* mask output_ctrl->tcon_tim_pola2        */
+/*      output_ctrl->tcon_tim_polb2        */
+#define VDC5_REG_MASK_0X000000FF    (0x000000FFu) /* mask scaler_0->scl0_frc5                */
+/*      scaler_1->scl0_frc5                */
+#define VDC5_REG_MASK_0X0000003F    (0x0000003Fu) /* mask img_synthesizer->gr_flm6           */
+/*      img_qlty_imp->adj_enh_shp1         */
+#define VDC5_REG_MASK_0XFF000000    (0xFF000000u) /* mask img_synthesizer->gr_ab10           */
+/*      img_synthesizer->gr_ab11           */
+#define VDC5_REG_MASK_0X00000110    (0x00000110u) /* mask output_ctrl->tcon_tim_sth2         */
+/*      output_ctrl->tcon_tim_stb2         */
+/*      output_ctrl->tcon_tim_cpv2         */
+#define VDC5_REG_MASK_0X00000007    (0x00000007u) /* mask *(output_pin_regaddr[tcon_pin])    */
+/*      img_synthesizer->gr_flm2           */
+/*      img_synthesizer->gr_flm2           */
+#define VDC5_REG_MASK_0X07FF0000    (0x07FF0000u) /* mask scaler_0->scl0_frc4                */
+/*      scaler_1->scl0_frc4                */
+/*      img_synthesizer->gr_flm5           */
+/*      img_synthesizer->gr_flm6           */
+#define VDC5_REG_MASK_0X0FFF0FFF    (0x0FFF0FFFu) /* mask                                    */
+/*      scaler->scl0_ds5, scaler->scl0_us6 */
+/*      scaler->scl0_ds5, scaler->scl0_us6 */
+/*      scaler->scl0_ds5, scaler->scl0_us6 */
+/*      scaler->scl0_ds5, scaler->scl0_us6 */
+/*      scaler->scl0_ds5, scaler->scl0_us6 */
+#define VDC5_REG_MASK_0X00000003    (0x00000003u) /* mask img_synthesizer->gr_ab1            */
+/*      regaddr_lvds->lphyacc              */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void SetVideoExternalInput(
+    const vdc5_ext_in_sig_t         * const ext_sig_tmp,
+    const vdc5_regaddr_input_ctrl_t * const input_ctrl);
+static void SetInitialConnection(const vdc5_channel_t ch);
+static void SetGrapicsBackgroundColor(const vdc5_channel_t ch);
+static void SetScalerBackgroundColor(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_color_space_t    color_space);
+static void SetLcdTcon_STVA_VS(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STVB_VE(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STH_HS(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_STB_HE(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_CPV_GCK(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_POLA(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_POLB(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetLcdTcon_DE(
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl);
+static void SetScalingDown(
+    const vdc5_scalingdown_rot_t    * const scldw_rot,
+    const vdc5_res_inter_t                  res_inter,
+    const vdc5_regaddr_scaler_t     * const scaler);
+static void SetScalingUp(
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_onoff_t                  adj_sel,
+    const vdc5_onoff_t                  ip_conversion,
+    const vdc5_wr_md_t                  res_ds_wr_md,
+    const vdc5_gr_ln_off_dir_t          ln_off_dir,
+    const vdc5_regaddr_scaler_t * const scaler);
+static uint32_t CalcScalingRatio(
+    const uint32_t      before_scl,
+    const uint32_t      after_scl,
+    const vdc5_onoff_t  adj_sel,
+    const vdc5_onoff_t  round_up);
+static void SetInputCntrlColorMtx(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+static vdc5_onoff_t ConfirmGraphicsEnlargement(
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc);
+static void SetScalerGraphics(
+    const vdc5_channel_t                ch,
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_onoff_t                  gr_enlarge);
+static uint32_t DisplayStartPixelSetting(const uint32_t gr_base, const vdc5_gr_format_t gr_format);
+static vdc5_onoff_t SetCascade(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge);
+static void SetupGraphicsVIN(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge);
+static void ChangeGraphicsVIN(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge);
+static void SetImgQaImproverColorMtx(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_color_space_t    color_space);
+
+static void SetRwProcAbility_Write_0(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Write_1(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Write_OIR(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_0(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_1(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_2(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_3(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRwProcAbility_Read_OIR(const vdc5_channel_t ch, const vdc5_onoff_t ability);
+static void SetRegUpdateRwEnable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+
+static void SetGraphicsDisplayMode(
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_gr_disp_sel_t    * const gr_disp_sel);
+static void SetColorMatrix(
+    const vdc5_colormtx_mode_t                  mtx_mode,
+    const uint16_t                      * const offset,
+    const uint16_t                      * const gain,
+    const vdc5_regaddr_color_matrix_t   * const color_matrix);
+static void SetImageEnhancementSharpness(
+    const vdc5_onoff_t                          shp_h_on,
+    const vdc5_enhance_sharp_t          * const sharp_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp);
+static void SetImageEnhancementLti(
+    const vdc5_onoff_t                          lti_h_on,
+    const vdc5_enhance_lti_t            * const lti_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp);
+static void SetAlphaRectArea(
+    const vdc5_pd_disp_rect_t               * const pd_disp_rect,
+    const vdc5_regaddr_img_synthesizer_t    * const img_synthesizer);
+static void SetUndSel(const vdc5_channel_t ch, const vdc5_onoff_t und_sel);
+static uint32_t ColorConversion(const vdc5_gr_format_t gr_format, const uint32_t input_color);
+static uint32_t ColorConversionFrom4to8(const uint32_t color_value);
+static uint32_t ColorConversionFrom5to8(const uint32_t color_value);
+static uint32_t ColorConversionFrom6to8(const uint32_t color_value);
+static uint32_t ColorConversionIntoAgbr(const uint32_t color_value);
+static void Set_Clut(const vdc5_clut_t * const param, volatile uint32_t * regaddr_clut);
+static void Set_StartThreshold_Gamma(const uint8_t * gam_th, volatile uint32_t * const * const gam_area);
+static void Set_GainAdjustment_Gamma(const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut);
+static void Wait_200_usec(void);
+
+/*! Color matrix offset (DC) adjustment (YG, B, and R) */
+static const uint16_t colormtx_offset_adj[VDC5_COLORMTX_OFFST_NUM] = {
+    (uint16_t)VDC5_COLORCONV_DC_OFFSET, (uint16_t)VDC5_COLORCONV_DC_OFFSET, (uint16_t)VDC5_COLORCONV_DC_OFFSET
+};
+/*! Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+static const uint16_t colormtx_gain_adj[VDC5_COLORMTX_MODE_NUM][VDC5_COLORMTX_GAIN_NUM] = {
+    {   /* GBR to GBR */
+        (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0, 0,
+        0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0,
+        0, 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN
+    },
+    {   /* GBR to YCbCr */
+        (uint16_t)VDC5_COLORCONV_Y_G,  (uint16_t)VDC5_COLORCONV_Y_B,  (uint16_t)VDC5_COLORCONV_Y_R,
+        (uint16_t)VDC5_COLORCONV_CB_G, (uint16_t)VDC5_COLORCONV_CB_B, (uint16_t)VDC5_COLORCONV_CB_R,
+        (uint16_t)VDC5_COLORCONV_CR_G, (uint16_t)VDC5_COLORCONV_CR_B, (uint16_t)VDC5_COLORCONV_CR_R
+    },
+    {   /* YCbCr to GBR */
+        (uint16_t)VDC5_COLORCONV_G_Y, (uint16_t)VDC5_COLORCONV_G_CB, (uint16_t)VDC5_COLORCONV_G_CR,
+        (uint16_t)VDC5_COLORCONV_B_Y, (uint16_t)VDC5_COLORCONV_B_CB, (uint16_t)VDC5_COLORCONV_B_CR,
+        (uint16_t)VDC5_COLORCONV_R_Y, (uint16_t)VDC5_COLORCONV_R_CB, (uint16_t)VDC5_COLORCONV_R_CR
+    },
+    {   /* YCbCr to YCbCr */
+        (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0, 0,
+        0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN, 0,
+        0, 0, (uint16_t)VDC5_COLORCONV_1TIMES_GAIN
+    }
+};
+
+static void (* const rw_proc_function_tbl[VDC5_LAYER_ID_NUM])(const vdc5_channel_t ch, const vdc5_onoff_t ability) = {
+    &SetRwProcAbility_Write_0,          /* Write scaler 0 */
+    &SetRwProcAbility_Write_1,          /* Write scaler 1 */
+    &SetRwProcAbility_Write_OIR,        /* Write OIR */
+    &SetRwProcAbility_Read_0,           /* Read graphics 0 */
+    &SetRwProcAbility_Read_1,           /* Read graphics 1 */
+    &SetRwProcAbility_Read_2,           /* Read graphics 2 */
+    &SetRwProcAbility_Read_3,           /* Read graphics 3 */
+    0,                                  /* Read VIN */
+    &SetRwProcAbility_Read_OIR          /* Read OIR */
+};
+
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_Initialize (const vdc5_channel_t ch, const vdc5_init_t * const param)
+{
+    const vdc5_lvds_t         * lvds_tmp;
+    const vdc5_regaddr_lvds_t * regaddr_lvds;
+    volatile uint32_t           counter;
+    uint16_t                    syscnt_panel_clk_tmp;
+    volatile uint16_t         * syscnt_panel_clk_reg;
+    volatile uint32_t         * inp_sel_cnt_reg;
+    static const uint16_t       panel_dcdr_tbl[VDC5_PANEL_CLKDIV_NUM] = {
+        /* Panel clock frequency division ratio */
+        (uint16_t)VDC5_REG_CLKDIV_1_1, (uint16_t)VDC5_REG_CLKDIV_1_2,  (uint16_t)VDC5_REG_CLKDIV_1_3,  (uint16_t)VDC5_REG_CLKDIV_1_4,
+        (uint16_t)VDC5_REG_CLKDIV_1_5, (uint16_t)VDC5_REG_CLKDIV_1_6,  (uint16_t)VDC5_REG_CLKDIV_1_7,  (uint16_t)VDC5_REG_CLKDIV_1_8,
+        (uint16_t)VDC5_REG_CLKDIV_1_9, (uint16_t)VDC5_REG_CLKDIV_1_12, (uint16_t)VDC5_REG_CLKDIV_1_16, (uint16_t)VDC5_REG_CLKDIV_1_24,
+        (uint16_t)VDC5_REG_CLKDIV_1_32
+    };
+    static const uint16_t       panel_icksel_tbl[VDC5_PANEL_ICKSEL_NUM] = {
+        /* Panel clock select */
+        (uint16_t)VDC5_REG_ICKSEL_IMG,  (uint16_t)VDC5_REG_ICKSEL_IMG_DV, (uint16_t)VDC5_REG_ICKSEL_EXT_0, (uint16_t)VDC5_REG_ICKSEL_EXT_1,
+        (uint16_t)VDC5_REG_ICKSEL_PERI, (uint16_t)VDC5_REG_ICKSEL_LVDS,   (uint16_t)VDC5_REG_ICKSEL_LVDS_DIV7
+    };
+
+    syscnt_panel_clk_reg = vdc5_regaddr_system_ctrl[ch].syscnt_panel_clk;
+    /* Disable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC5_REG_BIT8));
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+    /* LVDS */
+    lvds_tmp = param->lvds;
+    if (lvds_tmp != NULL) {
+        regaddr_lvds = &vdc5_regaddr_lvds;
+
+        /* Output from the LVDS PLL is disabled. */
+        *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_BIT4;
+        /* Controls power-down for the LVDS PLL: Power-down state */
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)VDC5_REG_BIT0;
+        for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
+            /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+        }
+
+        /* LPHYACC */
+        *(regaddr_lvds->lphyacc) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(regaddr_lvds->lphyacc) |= LVDS_LPHYACC_VALUE;
+        /* LCLKSELR: LVDS clock select register */
+        *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_MASK_0X0703FF02;
+        /* The clock input to frequency divider 1 */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_in_clk_sel << VDC5_REG_SHIFT_24;
+        /* The frequency dividing value (NIDIV) for frequency divider 1 */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_idiv_set << VDC5_REG_SHIFT_16;
+        /* Internal parameter setting for LVDS PLL */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvdspll_tst << VDC5_REG_SHIFT_10;
+        /* The frequency dividing value (NODIV) for frequency divider 2 */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)lvds_tmp->lvds_odiv_set << VDC5_REG_SHIFT_8;
+        if (lvds_tmp->lvds_vdc_sel != VDC5_CHANNEL_0) {
+            /* A channel in VDC5 whose data is to be output through the LVDS */
+            *(regaddr_lvds->lclkselr) |= (uint32_t)VDC5_REG_BIT1;
+        }
+
+        /* LPLLSETR: LVDS PLL setting register */
+        *(regaddr_lvds->lpllsetr) &= (uint32_t)~VDC5_REG_MASK_0X07FF1F30;
+        /* The frequency dividing value (NFD) for the feedback frequency */
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_fd << VDC5_REG_SHIFT_16;
+        /* The frequency dividing value (NRD) for the input frequency */
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_rd << VDC5_REG_SHIFT_8;
+        /* The frequency dividing value (NOD) for the output frequency */
+        *(regaddr_lvds->lpllsetr) |= (uint32_t)lvds_tmp->lvdspll_od << VDC5_REG_SHIFT_4;
+
+        for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
+            /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+        }
+        /* Controls power-down for the LVDS PLL: Normal operation */
+        *(regaddr_lvds->lpllsetr) &= (uint32_t)~VDC5_REG_BIT0;
+
+        /* Wait for 200 usec. */
+        Wait_200_usec();
+
+        /* Output from the LVDS PLL is enabled. */
+        *(regaddr_lvds->lclkselr) |= (uint32_t)VDC5_REG_BIT4;
+    }
+
+    inp_sel_cnt_reg = vdc5_regaddr_input_ctrl[ch].inp_sel_cnt;
+    /* Input select */
+    if (param->panel_icksel == VDC5_PANEL_ICKSEL_IMG_DV) {
+        *inp_sel_cnt_reg |= (uint32_t)VDC5_REG_BIT20;
+    } else {
+        *inp_sel_cnt_reg &= (uint32_t)~VDC5_REG_BIT20;
+    }
+    syscnt_panel_clk_tmp    = panel_dcdr_tbl[param->panel_dcdr];
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)syscnt_panel_clk_tmp |
+                                         (uint32_t)panel_icksel_tbl[param->panel_icksel]);
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+    /* Enable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)syscnt_panel_clk_tmp | VDC5_REG_BIT8);
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+}   /* End of function VDC5_Initialize() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for termination
+ * @param[in]   ch                      : Channel
+ * @retval      None
+******************************************************************************/
+void VDC5_Terminate (const vdc5_channel_t ch)
+{
+    volatile uint16_t         * syscnt_panel_clk_reg;
+    uint16_t                    syscnt_panel_clk_tmp;
+    vdc5_resource_state_t       rsrc_state;
+    vdc5_onoff_t                lvds_ref;
+    const vdc5_regaddr_lvds_t * regaddr_lvds;
+    volatile uint32_t           counter;
+
+    syscnt_panel_clk_reg = vdc5_regaddr_system_ctrl[ch].syscnt_panel_clk;
+    /* Disable */
+    syscnt_panel_clk_tmp    = (uint16_t)((uint32_t)*syscnt_panel_clk_reg & (~VDC5_REG_BIT8));
+    *syscnt_panel_clk_reg   = syscnt_panel_clk_tmp;
+
+    rsrc_state = VDC5_ShrdPrmGetResource(ch, VDC5_RESOURCE_LVDS_CLK);
+    if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {       /* LVDS PLL clock is set. */
+        lvds_ref = VDC5_ShrdPrmGetLvdsClkRef();
+        if (lvds_ref == VDC5_OFF) {     /* LVDS PLL clock is not referred. */
+            regaddr_lvds = &vdc5_regaddr_lvds;
+
+            /* Output from the LVDS PLL is disabled. */
+            *(regaddr_lvds->lclkselr) &= (uint32_t)~VDC5_REG_BIT4;
+            /* Controls power-down for the LVDS PLL: Power-down state */
+            *(regaddr_lvds->lpllsetr) |= (uint32_t)VDC5_REG_BIT0;
+            for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_CYCLE; counter++) {
+                /* This is a delay (1 usec) while waiting for PLL PD to settle. */
+            }
+        }
+    }
+}   /* End of function VDC5_Terminate() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for video input
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_VideoInput (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+    const vdc5_regaddr_input_ctrl_t   * input_ctrl;
+    const vdc5_sync_delay_t           * dly_tmp;
+    const vdc5_ext_in_sig_t           * ext_sig_tmp;
+
+    input_ctrl = &vdc5_regaddr_input_ctrl[ch];
+
+    /* Input select */
+    if (param->inp_sel == VDC5_INPUT_SEL_VDEC) {
+        *(input_ctrl->inp_sel_cnt) &= (uint32_t)~VDC5_REG_BIT20;
+    } else {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT20;
+    }
+    /* Vsync signal 1/2fH and 1/4fH phase timing */
+    *(input_ctrl->inp_vsync_ph_adj)  = (uint32_t)param->inp_fh50 << VDC5_REG_SHIFT_16;
+    *(input_ctrl->inp_vsync_ph_adj) |= (uint32_t)param->inp_fh25;
+
+    /* Sync signal delay adjustment */
+    dly_tmp = param->dly;
+    if (dly_tmp != NULL) {
+        /* Number of lines for delaying Vsync signal and field differentiation signal */
+        *(input_ctrl->inp_dly_adj)  = (uint32_t)dly_tmp->inp_vs_dly_l << VDC5_REG_SHIFT_24;
+        /* Field differentiation signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_fld_dly << VDC5_REG_SHIFT_16;
+        /* Vsync signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_vs_dly << VDC5_REG_SHIFT_8;
+        /* Hsync signal delay amount */
+        *(input_ctrl->inp_dly_adj) |= (uint32_t)dly_tmp->inp_hs_dly;
+    }
+
+    /* Horizontal noise reduction operating mode, Y/Cb/Cr mode */
+    *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC5_REG_BIT20;
+
+    /* External input signal */
+    ext_sig_tmp = param->ext_sig;
+    if (ext_sig_tmp != NULL) {
+        /* Setting external input video signal */
+        SetVideoExternalInput(ext_sig_tmp, input_ctrl);
+
+        /* Horizontal noise reduction operating mode, G/B/R mode */
+        if ((ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB888) ||
+                (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB666) ||
+                (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_RGB565)) {
+            *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_BIT20;
+        }
+    }
+
+    /* Register update control register (INP_UPDATE)
+       b4       INP_EXT_UPDATE
+       b0       INP_IMG_UPDATE */
+    *(input_ctrl->inp_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+    /* Register update control register (IMGCNT_UPDATE)
+       b0       IMGCNT_VEN */
+    *(input_ctrl->imgcnt_update) |= (uint32_t)VDC5_REG_BIT0;
+}   /* End of function VDC5_VideoInput() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for sync control
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Sync signal control parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_SyncControl (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+    const vdc5_regaddr_scaler_t   * scaler_0;
+    const vdc5_regaddr_scaler_t   * scaler_1;
+    const vdc5_regaddr_scaler_t   * scaler_oir;
+    uint32_t                        full_scr;
+
+    scaler_0    = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+    scaler_1    = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+    scaler_oir  = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+
+    if (param->vsync_cpmpe != NULL) {
+        /* Frequent Vsync signal masking period */
+        *(scaler_0->scl0_frc1) = (uint32_t)param->vsync_cpmpe->res_vmask << VDC5_REG_SHIFT_16;
+        *(scaler_1->scl0_frc1) = (uint32_t)param->vsync_cpmpe->res_vmask << VDC5_REG_SHIFT_16;
+        /* Missing-Sync compensating pulse output wait time */
+        *(scaler_0->scl0_frc2) = (uint32_t)param->vsync_cpmpe->res_vlack << VDC5_REG_SHIFT_16;
+        *(scaler_1->scl0_frc2) = (uint32_t)param->vsync_cpmpe->res_vlack << VDC5_REG_SHIFT_16;
+        /* Frequent Vsync signal masking and missing Vsync signal compensation */
+        *(scaler_0->scl0_frc1) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc1) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc2) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc2) |= (uint32_t)VDC5_REG_BIT0;
+    } else {
+        /* Frequent Vsync signal masking and missing Vsync signal compensation are disabled, if unnecessary. */
+        *(scaler_0->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc2) |= (uint32_t)VDC5_REG_BIT_0XFFFF0000;
+        *(scaler_1->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc2) |= (uint32_t)VDC5_REG_BIT_0XFFFF0000;
+    }
+    /* In OIR, frequent Vsync signal masking and missing Vsync signal compensation are set to off. */
+    *(scaler_oir->scl0_frc1) &= (uint32_t)~VDC5_REG_BIT0;
+    *(scaler_oir->scl0_frc2) &= (uint32_t)~VDC5_REG_BIT0;
+
+    /* Hsync period setting and free-running Vsync period initialization */
+    *(scaler_0->scl0_frc4)      = (uint32_t)param->res_fh;
+    *(scaler_1->scl0_frc4)      = (uint32_t)param->res_fh;
+    *(scaler_oir->scl0_frc4)    = (uint32_t)param->res_fh;
+    /* Vsync signal output select (free-running Vsync on/off control) */
+    if (param->res_vs_sel == VDC5_OFF) {
+        *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
+    } else {
+        *(scaler_0->scl0_frc3) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT0;
+        *(scaler_0->scl0_frc4) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+        *(scaler_0->scl0_frc4) |= (uint32_t)param->res_fv << VDC5_REG_SHIFT_16;
+        *(scaler_1->scl0_frc4) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+        *(scaler_1->scl0_frc4) |= (uint32_t)param->res_fv << VDC5_REG_SHIFT_16;
+    }
+    /* In OIR, external input Vsync signal is selected automatically. */
+    *(scaler_oir->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT0;
+
+    /* Sync signal output and full-screen enable signal select: Scaler 0 */
+    *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+    *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+
+    /* Vsync signal delay control */
+    *(scaler_0->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
+    *(scaler_0->scl0_frc5) |= (uint32_t)param->res_vsdly;
+    *(scaler_1->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
+    *(scaler_1->scl0_frc5) |= (uint32_t)param->res_vsdly;
+    *(scaler_oir->scl0_frc5) &= (uint32_t)~VDC5_REG_MASK_0X000000FF;
+    *(scaler_oir->scl0_frc5) |= OIR_VSYNC_DELAY;
+
+    /* Full-screen enable signal */
+    full_scr  = (uint32_t)param->res_f.vs << VDC5_REG_SHIFT_16;
+    full_scr |= (uint32_t)param->res_f.vw;
+
+    *(scaler_0->scl0_frc6)   = full_scr;
+    *(scaler_1->scl0_frc6)   = full_scr;
+    *(scaler_oir->scl0_frc6) = full_scr;
+
+    full_scr  = (uint32_t)param->res_f.hs << VDC5_REG_SHIFT_16;
+    full_scr |= (uint32_t)param->res_f.hw;
+
+    *(scaler_0->scl0_frc7)   = full_scr;
+    *(scaler_1->scl0_frc7)   = full_scr;
+    *(scaler_oir->scl0_frc7) = full_scr;
+
+    /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+       b8       SCL0_UPDATE
+       b4       SCL0_VEN_B */
+    *(scaler_0->scl0_update)   |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+    *(scaler_1->scl0_update)   |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+    *(scaler_oir->scl0_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+
+    SetInitialConnection(ch);
+
+    VDC5_ShrdPrmSetUndSel(ch, VDC5_OFF);
+}   /* End of function VDC5_SyncControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for display output
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_DisplayOutput (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+    const vdc5_regaddr_output_ctrl_t      * output_ctrl;
+    volatile uint32_t                     * output_pin_regaddr[VDC5_LCD_TCON_PIN_NUM];
+    uint32_t                                tcon_sig_index;
+    const vdc5_lcd_tcon_timing_t  * const * lcd_tcon_timing;
+    static void                    (* const tcon_function_tbl[VDC5_LCD_TCONSIG_NUM])(
+        const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+        const vdc5_regaddr_output_ctrl_t    * const output_ctrl) = {
+        &SetLcdTcon_STVA_VS,    /* STVA/VS */
+        &SetLcdTcon_STVB_VE,    /* STVB/VE */
+        &SetLcdTcon_STH_HS,     /* STH_HS */
+        &SetLcdTcon_STB_HE,     /* STB_HE */
+        &SetLcdTcon_CPV_GCK,    /* CPV_GCK */
+        &SetLcdTcon_POLA,       /* POLA */
+        &SetLcdTcon_POLB,       /* POLB */
+        &SetLcdTcon_DE          /* DE */
+    };
+    const uint32_t                      output_pin_edge[VDC5_LCD_TCON_PIN_NUM] = {
+        VDC5_REG_TCON0_EDGE, VDC5_REG_TCON1_EDGE, VDC5_REG_TCON2_EDGE, VDC5_REG_TCON3_EDGE,
+        VDC5_REG_TCON4_EDGE, VDC5_REG_TCON5_EDGE, VDC5_REG_TCON6_EDGE
+    };
+    vdc5_lcd_tcon_pin_t                 tcon_pin_tmp;
+    const vdc5_gr_disp_sel_t            gr_disp_sel_tbl[VDC5_GR_TYPE_NUM] = {
+        /* Graphics display mode for initialization */
+        VDC5_DISPSEL_BACK,              /* Graphics 0 */
+        VDC5_DISPSEL_LOWER,             /* Graphics 1 */
+        VDC5_DISPSEL_LOWER,             /* Graphics 2 */
+        VDC5_DISPSEL_LOWER,             /* Graphics 3 */
+        VDC5_DISPSEL_IGNORED,           /* VIN */
+        VDC5_DISPSEL_BACK               /* OIR */
+    };
+    const uint32_t                      dither_format[VDC5_LCD_OUTFORMAT_NUM] = {
+        /* Panel dither output format select */
+        VDC5_REG_PATH_FORMAT_RGB888, VDC5_REG_PATH_FORMAT_RGB666,
+        VDC5_REG_PATH_FORMAT_RGB565, VDC5_REG_PATH_FORMAT_NON
+    };
+
+    output_ctrl = &vdc5_regaddr_output_ctrl[ch];
+
+    /* 1/2fH timing */
+    *(output_ctrl->tcon_tim)  = (uint32_t)param->tcon_half << VDC5_REG_SHIFT_16;
+    /* Offset Hsync signal timing */
+    *(output_ctrl->tcon_tim) |= (uint32_t)param->tcon_offset;
+
+    /* Create output pin register address table */
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_0] = output_ctrl->tcon_tim_stva2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_1] = output_ctrl->tcon_tim_stvb2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_2] = output_ctrl->tcon_tim_sth2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_3] = output_ctrl->tcon_tim_stb2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_4] = output_ctrl->tcon_tim_cpv2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_5] = output_ctrl->tcon_tim_pola2;
+    output_pin_regaddr[VDC5_LCD_TCON_PIN_6] = output_ctrl->tcon_tim_polb2;
+
+    /* Clear output phase control of LCT_TCON0~6 pin */
+    *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_MASK_0X0000007F;
+    /* LCD TCON */
+    lcd_tcon_timing = param->outctrl;
+    for (tcon_sig_index = 0; tcon_sig_index < VDC5_LCD_TCONSIG_NUM; tcon_sig_index++) {
+        if (*lcd_tcon_timing != NULL) {
+            /* Setting LCD TCON */
+            tcon_function_tbl[tcon_sig_index](*lcd_tcon_timing, output_ctrl);
+
+            tcon_pin_tmp = (*lcd_tcon_timing)->tcon_pin;
+            if (tcon_pin_tmp != VDC5_LCD_TCON_PIN_NON) {
+                /* LCD TCON output pin select */
+                *(output_pin_regaddr[tcon_pin_tmp]) &= (uint32_t)~VDC5_REG_MASK_0X00000007;
+                *(output_pin_regaddr[tcon_pin_tmp]) |= tcon_sig_index;
+                /* Output phase control of LCT_TCON pin */
+                if ((*lcd_tcon_timing)->outcnt_edge != VDC5_EDGE_RISING) {
+                    *(output_ctrl->out_clk_phase) |= output_pin_edge[tcon_pin_tmp];
+                }
+            }
+        }
+        lcd_tcon_timing++;
+    }
+
+    *(output_ctrl->out_set) &= (uint32_t)~VDC5_REG_MASK_0X11003313;
+    /* Bit endian change ON/OFF control */
+    if (param->out_endian_on != VDC5_OFF) {
+        *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT28;
+    }
+    /* B/R signal swap ON/OFF control */
+    if (param->out_swap_on != VDC5_OFF) {
+        *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT24;
+    }
+    /* Output format select */
+    *(output_ctrl->out_set) |= (uint32_t)param->out_format << VDC5_REG_SHIFT_12;
+
+    /* Panel dither output format select */
+    *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00030000;
+    *(output_ctrl->out_pdtha) |= dither_format[param->out_format];
+
+    if (param->out_format == VDC5_LCD_OUTFORMAT_SERIAL_RGB) {
+        /* Clock frequency control */
+        *(output_ctrl->out_set) |= (uint32_t)param->out_frq_sel << VDC5_REG_SHIFT_8;
+        /* Scan direction select */
+        if (param->out_dir_sel != VDC5_LCD_SERIAL_SCAN_FORWARD) {
+            *(output_ctrl->out_set) |= (uint32_t)VDC5_REG_BIT4;
+        }
+        /* Clock phase adjustment */
+        *(output_ctrl->out_set) |= (uint32_t)param->out_phase;
+    } else {
+        /* Clock frequency control */
+        *(output_ctrl->out_set) |= (uint32_t)VDC5_LCD_PARALLEL_CLKFRQ_1 << VDC5_REG_SHIFT_8;
+    }
+
+    /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+    if (param->outcnt_lcd_edge == VDC5_EDGE_RISING) {
+        *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_BIT8;
+    } else {
+        *(output_ctrl->out_clk_phase) |= (uint32_t)VDC5_REG_BIT8;
+    }
+
+    /* Set background color */
+    SetGrapicsBackgroundColor(ch);
+    /* Initialize graphics display mode */
+    SetGraphicsDisplayMode(ch, VDC5_LAYER_ID_ALL, gr_disp_sel_tbl);
+
+    /* TCON register update control register (TCON_UPDATE)
+       b0       TCON_VEN */
+    *(output_ctrl->tcon_update) |= (uint32_t)VDC5_REG_BIT0;
+    /* Register update control register (OUT_UPDATE)
+       b0       OUTCNT_VEN */
+    *(output_ctrl->out_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_DisplayOutput() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write control processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @param[in]   param                   : Data write control parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_WriteDataControl (
+    const vdc5_channel_t        ch,
+    const vdc5_scaling_type_t   scaling_id,
+    const vdc5_write_t  * const param)
+{
+    const vdc5_regaddr_scaler_t   * scaler;
+    const vdc5_scalingdown_rot_t  * scldw_rot;
+
+    scaler      = &vdc5_regaddr_scaler[ch][scaling_id];
+    scldw_rot   = &param->scalingdown_rot;
+
+    /* Image area to be captured */
+    *(scaler->scl0_ds2)  = (uint32_t)scldw_rot->res.vs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
+    *(scaler->scl0_ds3)  = (uint32_t)scldw_rot->res.hs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
+
+    *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X0007000D;
+    /* Swap setting in frame buffer writing */
+    *(scaler->scl1_wr1) |= (uint32_t)param->res_wrswa << VDC5_REG_SHIFT_16;
+    /* Frame buffer video-signal writing format */
+    *(scaler->scl1_wr1) |= (uint32_t)param->res_md << VDC5_REG_SHIFT_2;
+    /* Transfer burst length for frame buffer writing */
+    if (param->res_bst_md != VDC5_BST_MD_32BYTE) {
+        *(scaler->scl1_wr1) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    /* Frame buffer base address */
+    *(scaler->scl1_wr2) = (uint32_t)param->base;
+    /* Frame buffer line offset address[byte] */
+    *(scaler->scl1_wr3) = param->ln_off << VDC5_REG_SHIFT_16;
+    /* Number of frames of buffer to be written to (res_flm_num + 1) */
+    *(scaler->scl1_wr3) |= param->flm_num;
+    /* Frame buffer frame offset address [byte] */
+    if (param->flm_num != 0u) {
+        *(scaler->scl1_wr4) = param->flm_off;
+    }
+
+    /* Writing rate */
+    *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_MASK_0X00000300;
+    *(scaler->scl1_wr5) |= (uint32_t)param->res_fs_rate << VDC5_REG_SHIFT_8;
+
+    /* Dither correction on/off */
+    if (param->res_dth_on == VDC5_OFF) {
+        *(scaler->scl1_wr6) &= (uint32_t)~VDC5_REG_BIT4;
+    } else {
+        *(scaler->scl1_wr6) |= (uint32_t)VDC5_REG_BIT4;
+    }
+    /* Bit Reduction */
+    if (param->res_md == VDC5_RES_MD_RGB565) {
+        /* On */
+        *(scaler->scl1_wr6) |= (uint32_t)VDC5_REG_BIT0;
+    } else {
+        /* Off */
+        *(scaler->scl1_wr6) &= (uint32_t)~VDC5_REG_BIT0;
+    }
+
+    if (scaling_id == VDC5_SC_TYPE_OIR) {
+        /* OIR */
+        /* Vertical and horizontal width after scaling-down control block */
+        *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res.vw << VDC5_REG_SHIFT_16;
+        *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res.hw;
+
+        /* Vertical scaling-down and horizontal scaling-down : OFF */
+        *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_MASK_0X00000011;
+
+        /* Field operating mode select is fixed to progressive */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT12;
+    } else {
+        /* Scaler 0 or 1 */
+        /* Field determination signal delay control */
+        if (param->flm_num == 0u) {
+            /* Frame buffer: One plane */
+            *(scaler->scl0_frc5) &= (uint32_t)~VDC5_REG_BIT8;
+        } else {
+            /* Frame buffer: Two planes or more */
+            *(scaler->scl0_frc5) |= (uint32_t)VDC5_REG_BIT8;
+        }
+
+        /* Horizontal prefilter */
+        if (scldw_rot->res_pfil_sel == VDC5_OFF) {
+            *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_BIT29;
+        } else {
+            *(scaler->scl0_ds4) |= (uint32_t)VDC5_REG_BIT29;
+        }
+        /* Number of valid lines in vertical direction output by scaling-down control block */
+        *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res_out_vw << VDC5_REG_SHIFT_16;
+        /* Number of valid horizontal pixels output by scaling-down control block */
+        *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
+
+        /* Scaling-down */
+        SetScalingDown(scldw_rot, param->res_inter, scaler);
+
+        /* Frame buffer writing mode for image processing */
+        *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000070;
+        *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC5_REG_SHIFT_4;
+
+        /* Field operating mode select */
+        if (param->res_inter == VDC5_RES_INTER_PROGRESSIVE) {
+            /* Progressive */
+            *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT12;
+        } else {
+            /* Interlace */
+            *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT12;
+        }
+        /* Write field select */
+        if (param->res_fld_sel == VDC5_RES_FLD_SEL_TOP) {
+            /* Top field */
+            *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT4;
+        } else {
+            /* Bottom field */
+            *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT4;
+        }
+
+        /* Frame buffer for bottom */
+        if (param->btm_base != NULL) {
+            /* SC_RES_TB_ADD_MOD */
+            *(scaler->scl1_wr1) |= (uint32_t)VDC5_REG_MASK_0X00000080;
+
+            /* Frame buffer base address */
+            *(scaler->scl1_wr8) = (uint32_t)param->btm_base;
+            /* Frame buffer line offset address[byte] */
+            *(scaler->scl1_wr9)  = param->ln_off << VDC5_REG_SHIFT_16;
+            /* Number of frames of buffer to be written to (defined by res_flm_num + 1) */
+            *(scaler->scl1_wr9) |= param->flm_num;
+            /* Frame buffer frame offset address */
+            if (param->flm_num != 0u) {
+                *(scaler->scl1_wr10) = param->flm_off;
+            }
+        } else {
+            /* SC_RES_TB_ADD_MOD */
+            *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000080;
+        }
+    }
+
+    /* Register update control register (SC0/SC1/OIR_SCL0_UPDATE)
+       b12      SCL0_VEN_C
+       b4       SCL0_VEN_B
+       b0       SCL0_VEN_A */
+    *(scaler->scl0_update)   |= (uint32_t)(VDC5_REG_BIT12 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+    /* Register update control register (SC0/SC1/OIR_SCL1_UPDATE)
+       b16      SCL1_UPDATE_A
+       b4       SCL1_VEN_B
+       b0       SCL1_VEN_A */
+    *(scaler->scl1_update)   |= (uint32_t)(VDC5_REG_BIT16 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+    if (scaling_id != VDC5_SC_TYPE_OIR) {
+        SetInputCntrlColorMtx(ch, scaling_id);
+    }
+}   /* End of function VDC5_WriteDataControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write change processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @param[in]   param                   : Data write change parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ChangeWriteProcess (
+    const vdc5_channel_t            ch,
+    const vdc5_scaling_type_t       scaling_id,
+    const vdc5_write_chg_t  * const param)
+{
+    const vdc5_regaddr_scaler_t   * scaler;
+    const vdc5_scalingdown_rot_t  * scldw_rot;
+    vdc5_res_inter_t                res_inter_tmp;
+
+    scaler      = &vdc5_regaddr_scaler[ch][scaling_id];
+    scldw_rot   = &param->scalingdown_rot;
+
+    /* Image area to be captured */
+    *(scaler->scl0_ds2)  = (uint32_t)scldw_rot->res.vs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds2) |= (uint32_t)scldw_rot->res.vw;
+    *(scaler->scl0_ds3)  = (uint32_t)scldw_rot->res.hs << VDC5_REG_SHIFT_16;
+    *(scaler->scl0_ds3) |= (uint32_t)scldw_rot->res.hw;
+
+    if (scaling_id == VDC5_SC_TYPE_OIR) {
+        /* OIR */
+        /* Vertical and horizontal width after scaling-down control block */
+        *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res.vw << VDC5_REG_SHIFT_16;
+        *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res.hw;
+    } else {
+        /* Scaler 0 or 1 */
+        /* Horizontal prefilter */
+        if (scldw_rot->res_pfil_sel == VDC5_OFF) {
+            *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_BIT29;
+        } else {
+            *(scaler->scl0_ds4) |= (uint32_t)VDC5_REG_BIT29;
+        }
+        /* Number of valid lines in vertical direction output by scaling-down control block */
+        *(scaler->scl0_ds7)  = (uint32_t)scldw_rot->res_out_vw << VDC5_REG_SHIFT_16;
+        /* Number of valid horizontal pixels output by scaling-down control block */
+        *(scaler->scl0_ds7) |= (uint32_t)scldw_rot->res_out_hw;
+
+        /* Progressive or interlace */
+        res_inter_tmp = VDC5_ShrdPrmGetInterlace(ch, scaling_id);
+        /* Scaling-down */
+        SetScalingDown(scldw_rot, res_inter_tmp, scaler);
+
+        /* Frame buffer writing mode for image processing */
+        *(scaler->scl1_wr1) &= (uint32_t)~VDC5_REG_MASK_0X00000070;
+        *(scaler->scl1_wr1) |= (uint32_t)scldw_rot->res_ds_wr_md << VDC5_REG_SHIFT_4;
+
+        /* Register update control register (SC0/SC1)
+           b4       SCL1_VEN_B
+           b0       SCL1_VEN_A */
+        *(scaler->scl1_update)   |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+    }
+
+    /* Register update control register (SC0/SC1/OIR_SCL0_UPDATE)
+       b12      SCL0_VEN_C
+       b4       SCL0_VEN_B
+       b0       SCL0_VEN_A */
+    *(scaler->scl0_update)   |= (uint32_t)(VDC5_REG_BIT12 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+}   /* End of function VDC5_ChangeWriteProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data read control processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read control parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ReadDataControl (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_img_qlty_imp_t     * img_qlty_imp;
+    vdc5_width_read_fb_t                  * w_read_fb;
+    vdc5_onoff_t                            graphics_enlargement;
+    vdc5_color_space_t                      color_space;
+    vdc5_resource_state_t                   rsrc_state;
+    uint32_t                                reg_data;
+
+    w_read_fb = VDC5_ShrdPrmGetFrBuffWidth_Rd(ch, graphics_id);
+
+    graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, param->gr_flm_sel, w_read_fb, &param->gr_grc);
+
+    if ((graphics_id == VDC5_GR_TYPE_GR0) ||
+            (graphics_id == VDC5_GR_TYPE_GR1) ||
+            (graphics_id == VDC5_GR_TYPE_OIR)) {
+        SetScalerGraphics(ch, graphics_id, w_read_fb, &param->gr_grc, param->gr_flm_sel, graphics_enlargement);
+    }
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    *(img_synthesizer->gr_flm1) &= (uint32_t)~VDC5_REG_MASK_0X00010301;
+    /* Line offset address direction of the frame buffer */
+    if (param->gr_ln_off_dir != VDC5_GR_LN_OFF_DIR_INC) {
+        *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT16;
+    }
+    /* Frame buffer address setting signal */
+    *(img_synthesizer->gr_flm1) |= (uint32_t)param->gr_flm_sel << VDC5_REG_SHIFT_8;
+    /* Frame buffer burst transfer mode */
+    if (param->gr_bst_md != VDC5_BST_MD_32BYTE) {
+        *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT0;
+    }
+    /* Sets the frame buffer number for distortion correction */
+    if (param->gr_flm_sel == VDC5_GR_FLM_SEL_DISTORTION) {
+        if (param->gr_imr_flm_inv == VDC5_OFF) {
+            *(img_synthesizer->gr_flm1) &= (uint32_t)~VDC5_REG_BIT4;
+        } else {
+            *(img_synthesizer->gr_flm1) |= (uint32_t)VDC5_REG_BIT4;
+        }
+    }
+
+    /* Frame buffer base address */
+    *(img_synthesizer->gr_flm2) = (uint32_t)param->gr_base & (uint32_t)~VDC5_REG_MASK_0X00000007;
+
+    /* Frame buffer line offset address[byte] */
+    *(img_synthesizer->gr_flm3) &= (uint32_t)~VDC5_REG_MASK_0X7FFF03FF;
+    *(img_synthesizer->gr_flm3) |= param->gr_ln_off << VDC5_REG_SHIFT_16;
+
+    /* The number of lines when reading the addresses repeatedly */
+    *(img_synthesizer->gr_flm5) = (uint32_t)VDC5_REG_MASK_0X000007FF;
+    /* Number of lines in a frame */
+    *(img_synthesizer->gr_flm5) |= ((uint32_t)w_read_fb->in_vw - 1u) << VDC5_REG_SHIFT_16;
+
+    *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0XF7FF1C3F;
+    /* Format of the frame buffer read signal */
+    *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_format << VDC5_REG_SHIFT_28;
+    /* Width of the horizontal valid period */
+    *(img_synthesizer->gr_flm6) |= ((uint32_t)w_read_fb->in_hw - 1u) << VDC5_REG_SHIFT_16;
+    /* Swap setting in frame buffer reading */
+    *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_rdswa << VDC5_REG_SHIFT_10;
+
+    if ((param->gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) || (param->gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM)) {
+        /* Sets the amount of data to be skipped through */
+        *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, param->gr_format);
+    }
+
+    /* Graphics display mode */
+    *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+    if ((graphics_id == VDC5_GR_TYPE_GR0) ||
+            (graphics_id == VDC5_GR_TYPE_OIR)) {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
+    } else {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+    }
+
+    /* Graphics display area */
+    *(img_synthesizer->gr_ab2)  = (uint32_t)param->gr_grc.vs << VDC5_REG_SHIFT_16;
+    *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc.vw;
+    *(img_synthesizer->gr_ab3)  = (uint32_t)param->gr_grc.hs << VDC5_REG_SHIFT_16;
+    *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc.hw;
+
+    /* Initialize alpha blending in a rectangular area */
+    if ((graphics_id == VDC5_GR_TYPE_GR1) ||
+            (graphics_id == VDC5_GR_TYPE_GR2) ||
+            (graphics_id == VDC5_GR_TYPE_GR3)) {
+        /* Turns off alpha blending in a rectangular area */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X0000D000;
+        /* The valid image area for alpha blending in a rectangular area */
+        reg_data                   = *(img_synthesizer->gr_ab2);
+        *(img_synthesizer->gr_ab4) = reg_data;
+        reg_data                   = *(img_synthesizer->gr_ab3);
+        *(img_synthesizer->gr_ab5) = reg_data;
+        /* Disable fade-in and fade-out */
+        *(img_synthesizer->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
+        /* Set the initial alpha value to '255' */
+        *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
+    }
+    /* Turns off  chroma-key processing */
+    *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_BIT0;
+
+    if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+        /* Alpha value is set to 255. */
+        *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+        *(img_synthesizer->gr_ab11) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+    }
+    if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
+        /* Swapping of data read from buffer in the YCbCr422 format */
+        *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X0000E000;
+        if (param->gr_format == VDC5_GR_FORMAT_YCBCR422) {
+            *(img_synthesizer->gr_flm6) |= (uint32_t)param->gr_ycc_swap << VDC5_REG_SHIFT_13;
+            /* The interpolation mode for YCC422 to YCbCr444 conversion is fixed to average interpolation */
+            *(img_synthesizer->gr_flm6) |= (uint32_t)VDC5_REG_BIT8;
+        } else {
+            /* If the format of the frame buffer read signal is not YCbCr422,
+               initialize the swapping of data read from buffer in the YCbCr422 format. */
+            *(img_synthesizer->gr_flm6) |= (uint32_t)VDC5_GR_YCCSWAP_CBY0CRY1 << VDC5_REG_SHIFT_13;
+        }
+
+        SetupGraphicsVIN(ch, graphics_id, param->gr_flm_sel, graphics_enlargement);
+
+        color_space = VDC5_ShrdPrmGetColorSpaceFbRd(ch, graphics_id);
+
+        SetScalerBackgroundColor(ch, graphics_id, color_space);
+        SetImgQaImproverColorMtx(ch, graphics_id, color_space);
+
+        if (graphics_id == VDC5_GR_TYPE_GR0) {
+            img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][VDC5_IMG_IMPRV_0];
+        } else {
+            img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][VDC5_IMG_IMPRV_1];
+        }
+        /* Operating mode */
+        if (color_space == VDC5_COLOR_SPACE_GBR) {
+            *(img_qlty_imp->adj_enh_tim1) &= (uint32_t)~VDC5_REG_BIT4;
+        } else {
+            *(img_qlty_imp->adj_enh_tim1) |= (uint32_t)VDC5_REG_BIT4;
+        }
+        /* Register update control register (ADJx_UPDATE)
+           b0       ADJx_VEN */
+        *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    rsrc_state = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_1_RD);
+    if ((graphics_id == VDC5_GR_TYPE_GR0) && (rsrc_state == VDC5_RESOURCE_ST_INVALID)) {
+        /* Graphics 0 is specified when graphics 1 is not used. */
+        SetImgQaImproverColorMtx(ch, VDC5_GR_TYPE_GR1, VDC5_COLOR_SPACE_GBR);
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b8       GRx_UPDATE
+       b4       GRx_P_VEN
+       b0       GRx_IBUS_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT8 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+
+}   /* End of function VDC5_ReadDataControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data read change processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read change parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ChangeReadProcess (
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_read_chg_t   * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    vdc5_gr_flm_sel_t                       gr_flm_sel_tmp;
+    vdc5_period_rect_t                    * gr_grc_tmp;
+    vdc5_width_read_fb_t                  * w_read_fb;
+    vdc5_onoff_t                            graphics_enlargement;
+    vdc5_gr_format_t                        gr_format_tmp;
+
+    gr_flm_sel_tmp  = VDC5_ShrdPrmGetSelFbAddrSig(ch, graphics_id);
+    gr_grc_tmp      = VDC5_ShrdPrmGetDisplayArea(ch, graphics_id);
+    w_read_fb       = VDC5_ShrdPrmGetFrBuffWidth_Rd(ch, graphics_id);
+
+    graphics_enlargement = ConfirmGraphicsEnlargement(graphics_id, gr_flm_sel_tmp, w_read_fb, gr_grc_tmp);
+
+    if ((graphics_id == VDC5_GR_TYPE_GR0) ||
+            (graphics_id == VDC5_GR_TYPE_GR1) ||
+            (graphics_id == VDC5_GR_TYPE_OIR)) {
+        SetScalerGraphics(ch, graphics_id, w_read_fb, gr_grc_tmp, gr_flm_sel_tmp, graphics_enlargement);
+    }
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    /* Frame buffer base address */
+    if (param->gr_base != NULL) {
+        *(img_synthesizer->gr_flm2) = (uint32_t)param->gr_base & (uint32_t)~VDC5_REG_MASK_0X00000007;
+
+        if ((gr_flm_sel_tmp == VDC5_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel_tmp == VDC5_GR_FLM_SEL_FLM_NUM)) {
+            gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+            /* Sets the amount of data to be skipped through */
+            *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X0000003F;
+            *(img_synthesizer->gr_flm6) |= DisplayStartPixelSetting((uint32_t)param->gr_base, gr_format_tmp);
+        }
+    }
+
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL) {
+        /* Number of lines in a frame */
+        *(img_synthesizer->gr_flm5) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+        *(img_synthesizer->gr_flm5) |= ((uint32_t)param->width_read_fb->in_vw - 1u) << VDC5_REG_SHIFT_16;
+        /* Width of the horizontal valid period */
+        *(img_synthesizer->gr_flm6) &= (uint32_t)~VDC5_REG_MASK_0X07FF0000;
+        *(img_synthesizer->gr_flm6) |= ((uint32_t)param->width_read_fb->in_hw - 1u) << VDC5_REG_SHIFT_16;
+    }
+
+    /* Graphics display mode */
+    if (param->gr_disp_sel != NULL) {
+        if (*(param->gr_disp_sel) != VDC5_DISPSEL_IGNORED) {
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+            *(img_synthesizer->gr_ab1) |= (uint32_t)*(param->gr_disp_sel);
+        }
+    }
+
+    /* Graphics display area */
+    if (param->gr_grc != NULL) {
+        *(img_synthesizer->gr_ab2)  = (uint32_t)param->gr_grc->vs << VDC5_REG_SHIFT_16;
+        *(img_synthesizer->gr_ab2) |= (uint32_t)param->gr_grc->vw;
+        *(img_synthesizer->gr_ab3)  = (uint32_t)param->gr_grc->hs << VDC5_REG_SHIFT_16;
+        *(img_synthesizer->gr_ab3) |= (uint32_t)param->gr_grc->hw;
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN
+       b0       GRx_IBUS_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+
+    if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
+        ChangeGraphicsVIN(ch, graphics_id, gr_flm_sel_tmp, graphics_enlargement);
+    }
+}   /* End of function VDC5_ChangeReadProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write/read start processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   param                   : Data write/read start parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_StartProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_start_t * const param)
+{
+    uint32_t                    layer_id_num;
+    vdc5_resource_state_t       resource_state;
+    vdc5_resource_state_t       oir_resrc_st_before;
+    vdc5_resource_state_t       oir_resrc_st_after;
+    const vdc5_regaddr_scaler_t * scaler;
+
+    if (param->gr_disp_sel != NULL) {
+        /* Set graphics display mode */
+        SetGraphicsDisplayMode(ch, layer_id, param->gr_disp_sel);
+    }
+
+    oir_resrc_st_before = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+    if (layer_id != VDC5_LAYER_ID_ALL) {
+        rw_proc_function_tbl[layer_id](ch, VDC5_ON);
+    } else {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++) {
+            resource_state = VDC5_ShrdPrmGetRwProcReady(ch, (vdc5_layer_id_t)layer_id_num);
+            if (resource_state != VDC5_RESOURCE_ST_INVALID) {
+                rw_proc_function_tbl[layer_id_num](ch, VDC5_ON);
+            }
+        }
+    }
+    SetRegUpdateRwEnable(ch, layer_id);
+
+    oir_resrc_st_after = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+    /* OIR */
+    if ((oir_resrc_st_before == VDC5_RESOURCE_ST_INVALID) &&
+            (oir_resrc_st_after != VDC5_RESOURCE_ST_INVALID)) {
+        scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+        *(scaler->scl0_frc3) |= (uint32_t)VDC5_REG_BIT16;
+        /* Register update control register (OIR_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+    }
+}   /* End of function VDC5_StartProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write/read stop processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+******************************************************************************/
+void VDC5_StopProcess (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    uint32_t                    layer_id_num;
+    vdc5_resource_state_t       resource_state;
+    vdc5_resource_state_t       oir_resrc_st_before;
+    vdc5_resource_state_t       oir_resrc_st_after;
+    const vdc5_regaddr_scaler_t * scaler;
+
+    oir_resrc_st_before = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+    if (layer_id != VDC5_LAYER_ID_ALL) {
+        rw_proc_function_tbl[layer_id](ch, VDC5_OFF);
+    } else {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++) {
+            resource_state = VDC5_ShrdPrmGetRwProcEnabled(ch, (vdc5_layer_id_t)layer_id_num);
+            if (resource_state != VDC5_RESOURCE_ST_INVALID) {
+                rw_proc_function_tbl[layer_id_num](ch, VDC5_OFF);
+            }
+        }
+    }
+    SetRegUpdateRwEnable(ch, layer_id);
+
+    oir_resrc_st_after = VDC5_ShrdPrmGetOirRwProcEnabled(ch);
+
+    /* OIR */
+    if ((oir_resrc_st_before != VDC5_RESOURCE_ST_INVALID) &&
+            (oir_resrc_st_after == VDC5_RESOURCE_ST_INVALID)) {
+        scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+        *(scaler->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT16;
+        /* Register update control register (OIR_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+    }
+}   /* End of function VDC5_StopProcess() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for data write/read control release processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+******************************************************************************/
+void VDC5_ReleaseDataControl (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    const vdc5_regaddr_scaler_t           * scaler;
+    vdc5_resource_state_t                   resource_state;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer_vin;
+
+    resource_state = VDC5_ShrdPrmGetRwProcReady(ch, VDC5_LAYER_ID_1_RD);
+    if ((layer_id == VDC5_LAYER_ID_1_RD) ||
+            ((layer_id == VDC5_LAYER_ID_ALL) && (resource_state!= VDC5_RESOURCE_ST_INVALID))) {
+        SetInitialConnection(ch);
+
+        /* Use Vsync and enable signal output from scaler 0 */
+        scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+        *(scaler->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+        /* Register update control register (SC0_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+
+        scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+        *(scaler->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+        /* Register update control register (SC1_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+
+        /* Initialize the color matrix in the image quality improver (scaler 1 output) */
+        SetImgQaImproverColorMtx(ch, VDC5_GR_TYPE_GR1, VDC5_COLOR_SPACE_GBR);
+    }
+
+    resource_state = VDC5_ShrdPrmGetRwProcReady(ch, VDC5_LAYER_ID_0_RD);
+    if ((layer_id == VDC5_LAYER_ID_0_RD) ||
+            ((layer_id == VDC5_LAYER_ID_ALL) && (resource_state!= VDC5_RESOURCE_ST_INVALID))) {
+        img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+
+        /* Turns off alpha blending in a rectangular area */
+        *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
+        /* Selection of lower-layer plane in scaler, graphics 1 is used as lower-layer graphics. */
+        *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+        /* Graphics display mode in VIN */
+        *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+        /* Disable fade-in and fade-out */
+        *(img_synthesizer_vin->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
+        /* Set the initial alpha value to '255' */
+        *(img_synthesizer_vin->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
+
+        /* Graphics register update control register (GR_VIN_UPDATE)
+           b8       GR_VIN_UPDATE
+           b4       GR_VIN_P_VEN */
+        *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+    }
+}   /* End of function VDC5_ReleaseDataControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for noise reduction
+ * @param[in]   ch                      : Channel
+ * @param[in]   nr1d_on                 : Noise reduction ON/OFF setting
+ * @param[in]   param                   : Noise reduction setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_VideoNoiseReduction (
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      nr1d_on,
+    const vdc5_noise_reduction_t    * const param)
+{
+    const vdc5_regaddr_input_ctrl_t   * input_ctrl;
+    const vdc5_nr_param_t             * nr_param;
+
+    input_ctrl = &vdc5_regaddr_input_ctrl[ch];
+
+    if (param != NULL) {
+        /* Y/G signal noise reduction parameter */
+        nr_param = &param->y;
+        *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_MASK_0X00007F33;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt0) |= nr_param->nr1d_th << VDC5_REG_SHIFT_8;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_4;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)nr_param->nr1d_gain;
+
+        /* Cb/B signal noise reduction parameter */
+        nr_param = &param->cb;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt1)  = nr_param->nr1d_th << VDC5_REG_SHIFT_24;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_20;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain << VDC5_REG_SHIFT_16;
+
+        /* Cr/R signal noise reduction parameter */
+        nr_param = &param->cr;
+        /* Maximum value of coring (absolute value) */
+        *(input_ctrl->imgcnt_nr_cnt1) |= nr_param->nr1d_th << VDC5_REG_SHIFT_8;
+        /* TAP select */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_tap << VDC5_REG_SHIFT_4;
+        /* Noise reduction gain adjustment */
+        *(input_ctrl->imgcnt_nr_cnt1) |= (uint32_t)nr_param->nr1d_gain;
+    }
+
+    if (nr1d_on == VDC5_OFF) {
+        *(input_ctrl->imgcnt_nr_cnt0) &= (uint32_t)~VDC5_REG_BIT16;
+    } else {
+        *(input_ctrl->imgcnt_nr_cnt0) |= (uint32_t)VDC5_REG_BIT16;
+    }
+
+    /* Register update control register (IMGCNT_UPDATE)
+       b0       IMGCNT_VEN */
+    *(input_ctrl->imgcnt_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_VideoNoiseReduction() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for color matrix
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Color matrix setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ImageColorMatrix (const vdc5_channel_t ch, const vdc5_color_matrix_t * const param)
+{
+    SetColorMatrix(param->mtx_mode, param->offset, param->gain, &vdc5_regaddr_color_matrix[ch][param->module]);
+}   /* End of function VDC5_ImageColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for image enhancement processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness setup parameter
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   enh_area                : Enhancer-enabled area setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ImageEnhancement (
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area)
+{
+    const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
+
+    img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][imgimprv_id];
+
+    /* Sharpness */
+    SetImageEnhancementSharpness(shp_h_on, sharp_param, img_qlty_imp);
+
+    /* LTI */
+    SetImageEnhancementLti(lti_h_on, lti_param, img_qlty_imp);
+
+    /* Enhancer area */
+    if (enh_area != NULL) {
+        *(img_qlty_imp->adj_enh_tim2)  = (uint32_t)enh_area->vs << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_tim2) |= (uint32_t)enh_area->vw;
+        *(img_qlty_imp->adj_enh_tim3)  = (uint32_t)enh_area->hs << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_tim3) |= (uint32_t)enh_area->hw;
+    }
+
+    /* Register update control register (ADJx_UPDATE)
+       b0       ADJx_VEN */
+    *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_ImageEnhancement() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for black stretch
+ * @param[in]   ch                      : Channel
+ * @param[in]   imgimprv_id             : Image quality improver ID
+ * @param[in]   bkstr_on                : Black stretch ON/OFF setting
+ * @param[in]   param                   : Black stretch setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_ImageBlackStretch (
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param)
+{
+    const vdc5_regaddr_img_qlty_imp_t * img_qlty_imp;
+
+    img_qlty_imp = &vdc5_regaddr_img_qlty_imp[ch][imgimprv_id];
+
+    if (param != NULL) {
+        /* Black stretch start point */
+        *(img_qlty_imp->adj_bkstr_set)  = (uint32_t)((uint32_t)param->bkstr_st << VDC5_REG_SHIFT_20);
+        /* Black stretch depth */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_d << VDC5_REG_SHIFT_16);
+        /* Black stretch time constant (T1) */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)((uint32_t)param->bkstr_t1 << VDC5_REG_SHIFT_8);
+        /* Black stretch time constant (T2) */
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)param->bkstr_t2;
+    }
+
+    if (bkstr_on == VDC5_OFF) {
+        *(img_qlty_imp->adj_bkstr_set) &= (uint32_t)~VDC5_REG_BIT24;
+    } else {
+        *(img_qlty_imp->adj_bkstr_set) |= (uint32_t)VDC5_REG_BIT24;
+    }
+
+    /* Register update control register (ADJx_UPDATE)
+       b0       ADJx_VEN */
+    *(img_qlty_imp->adj_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_ImageBlackStretch() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for alpha blending
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Alpha blending setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_AlphaBlending (
+    const vdc5_channel_t                ch,
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_alpha_blending_t * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    /* Alpha signal of the ARGB1555/ARGB5551 format */
+    if (param->alpha_1bit != NULL) {
+        *(img_synthesizer->gr_ab10) &= (uint32_t)~VDC5_REG_MASK_0XFF000000;
+        *(img_synthesizer->gr_ab10) |= (uint32_t)param->alpha_1bit->gr_a0 << VDC5_REG_SHIFT_24;
+        *(img_synthesizer->gr_ab11) &= (uint32_t)~VDC5_REG_MASK_0XFF000000;
+        *(img_synthesizer->gr_ab11) |= (uint32_t)param->alpha_1bit->gr_a1 << VDC5_REG_SHIFT_24;
+    }
+
+    /* Premultiplication processing at alpha blending in one-pixel */
+    if (param->alpha_pixel != NULL) {
+        if (param->alpha_pixel->gr_acalc_md == VDC5_OFF) {
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT14;
+        } else {
+            *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT14;
+        }
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for rectangle alpha blending
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_arc_on               : ON/OFF setting for alpha blending in a rectangular area
+ * @param[in]   param                   : Setup parameter for alpha blending in a rectangular area
+ * @retval      None
+******************************************************************************/
+void VDC5_AlphaBlendingRect (
+    const vdc5_channel_t                        ch,
+    const vdc5_graphics_type_t                  graphics_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_alpha_rect_t               * alpha_rect_tmp;
+    uint32_t                                arc_coef;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    /* Alpha blending on/off control in a rectangular area */
+    if (gr_arc_on == VDC5_OFF) {
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
+    } else {
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT12;
+    }
+
+    if (param != NULL) {
+        /* Selection of lower-layer plane in scaler */
+        if (param->scl_und_sel != NULL) {
+            SetUndSel(ch, param->scl_und_sel->gr_vin_scl_und_sel);
+        }
+        /* Rectangular area subjected to alpha blending */
+        SetAlphaRectArea(param->gr_arc, img_synthesizer);
+
+        /* Alpha blending in a rectangular area */
+        alpha_rect_tmp = param->alpha_rect;
+        if (alpha_rect_tmp != NULL) {
+            if (graphics_id != VDC5_GR_TYPE_VIN) {
+                /* Multiplication processing with current alpha at alpha blending in a rectangular area (on/off) */
+                if (alpha_rect_tmp->gr_arc_mul == VDC5_OFF) {
+                    *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT15;
+                } else {
+                    *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT15;
+                }
+            }
+            /* Alpha coefficient for alpha blending in a rectangular area (-255 to 255) */
+            if (alpha_rect_tmp->gr_arc_coef < 0) {
+                arc_coef = (uint32_t)(alpha_rect_tmp->gr_arc_coef * (-1));  /* Conversion into absolute value */
+                /* Subtraction of the alpha coefficient */
+                *(img_synthesizer->gr_ab6) = (uint32_t)VDC5_REG_BIT24;
+            } else {
+                arc_coef = (uint32_t)alpha_rect_tmp->gr_arc_coef;
+                /* Addition of the alpha coefficient */
+                *(img_synthesizer->gr_ab6) = (uint32_t)0x00000000u;
+            }
+            *(img_synthesizer->gr_ab6) |= arc_coef << VDC5_REG_SHIFT_16;
+            /* Frame rate for alpha blending in a rectangular area (gr_arc_rate + 1) */
+            *(img_synthesizer->gr_ab6) |= (uint32_t)alpha_rect_tmp->gr_arc_rate;
+            /* Initial alpha value for alpha blending in a rectangular area */
+            *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_MASK_0X00FF0000;
+            *(img_synthesizer->gr_ab7) |= (uint32_t)alpha_rect_tmp->gr_arc_def << VDC5_REG_SHIFT_16;
+        }
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_AlphaBlending() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for chroma-key
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_ck_on                : Chroma-key ON/OFF setting
+ * @param[in]   param                   : Chroma-key setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_Chromakey (
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param)
+{
+    vdc5_gr_format_t                        gr_format_tmp;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    if (param != NULL) {
+        gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+        if ((gr_format_tmp == VDC5_GR_FORMAT_CLUT1) ||
+                (gr_format_tmp == VDC5_GR_FORMAT_CLUT4) ||
+                (gr_format_tmp == VDC5_GR_FORMAT_CLUT8)) {
+            *(img_synthesizer->gr_ab8)  = (uint32_t)(param->ck_color << VDC5_REG_SHIFT_24);
+            *(img_synthesizer->gr_ab9)  = ColorConversionIntoAgbr(param->rep_color & VDC5_REG_RGB_24BIT_MASK);
+        } else {
+            /* Color conversion from gr_format_tmp into RGB888 format */
+            *(img_synthesizer->gr_ab8)  = ColorConversion(gr_format_tmp, param->ck_color);
+            *(img_synthesizer->gr_ab9)  = ColorConversion(gr_format_tmp, param->rep_color);
+        }
+        if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+            /* Alpha value is set to 255. */
+            *(img_synthesizer->gr_ab9) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+        } else {
+            *(img_synthesizer->gr_ab9) |= (uint32_t)param->rep_alpha << VDC5_REG_SHIFT_24;
+        }
+    }
+
+    if (gr_ck_on == VDC5_OFF) {
+        *(img_synthesizer->gr_ab7) &= (uint32_t)~VDC5_REG_BIT0;
+    } else {
+        *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_Chromakey() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for CLUT
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : CLUT setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_CLUT (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id, const vdc5_clut_t * const param)
+{
+    vdc5_gr_format_t                        gr_format_tmp;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+    gr_format_tmp = VDC5_ShrdPrmGetGraphicsFormat(ch, graphics_id);
+    if (gr_format_tmp == VDC5_GR_FORMAT_CLUT1) {
+        if (param->color_num == ((uint32_t)1u)) {
+            *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
+            if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+                /* Alpha value is set to 255. */
+                *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+            }
+        } else {
+            *(img_synthesizer->gr_ab10) = ColorConversionIntoAgbr(param->clut[0]);
+            *(img_synthesizer->gr_ab11) = ColorConversionIntoAgbr(param->clut[1]);
+            if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+                /* Alpha value is set to 255. */
+                *(img_synthesizer->gr_ab10) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+                *(img_synthesizer->gr_ab11) |= (uint32_t)VDC5_REG_ALPHA_8BIT;
+            }
+        }
+    } else {    /* CLUT4 or CLUT8 */
+        Set_Clut(param, vdc5_regaddr_clut[ch][graphics_id]);
+
+        /* CLUT table control register (GRx_CLUT)
+           b16      GRx_CLT_SEL - CLUT table select signal - XOR, flip signal */
+        *(img_synthesizer->gr_clut) ^= (uint32_t)VDC5_REG_BIT16;
+    }
+    /* Graphics register update control register (GRx_UPDATE)
+       b4       GRx_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+
+}   /* End of function VDC5_CLUT() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for display calibration
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Display calibration parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_DisplayCalibration (const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param)
+{
+    const vdc5_calibr_bright_t        * bright_tmp;
+    const vdc5_calibr_contrast_t      * contrast_tmp;
+    const vdc5_calibr_dither_t        * panel_dither_tmp;
+    const vdc5_regaddr_output_ctrl_t  * output_ctrl;
+
+    output_ctrl = &vdc5_regaddr_output_ctrl[ch];
+
+    /* Correction circuit sequence control */
+    if (param->route == VDC5_CALIBR_ROUTE_BCG) {
+        *(output_ctrl->out_clk_phase) &= (uint32_t)~VDC5_REG_BIT12;
+    } else {
+        *(output_ctrl->out_clk_phase) |= (uint32_t)VDC5_REG_BIT12;
+    }
+
+    /* Brightness (DC) adjustment */
+    bright_tmp = param->bright;
+    if (bright_tmp != NULL) {
+        *(output_ctrl->out_bright1)  = (uint32_t)bright_tmp->pbrt_g;
+        *(output_ctrl->out_bright2)  = (uint32_t)bright_tmp->pbrt_b << VDC5_REG_SHIFT_16;
+        *(output_ctrl->out_bright2) |= (uint32_t)bright_tmp->pbrt_r;
+    }
+
+    /* Contrast (gain) adjustment */
+    contrast_tmp = param->contrast;
+    if (contrast_tmp != NULL) {
+        *(output_ctrl->out_contrast)  = (uint32_t)contrast_tmp->cont_g << VDC5_REG_SHIFT_16;
+        *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_b << VDC5_REG_SHIFT_8;
+        *(output_ctrl->out_contrast) |= (uint32_t)contrast_tmp->cont_r;
+    }
+
+    /* Panel dithering */
+    panel_dither_tmp = param->panel_dither;
+    if (panel_dither_tmp != NULL) {
+        *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00300000;
+        *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_sel << VDC5_REG_SHIFT_20;
+        if (panel_dither_tmp->pdth_sel == VDC5_PDTH_MD_2X2) {
+            *(output_ctrl->out_pdtha) &= (uint32_t)~VDC5_REG_MASK_0X00003333;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pa << VDC5_REG_SHIFT_12;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pb << VDC5_REG_SHIFT_8;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pc << VDC5_REG_SHIFT_4;
+            *(output_ctrl->out_pdtha) |= (uint32_t)panel_dither_tmp->pdth_pd;
+        }
+    }
+
+    /* Register update control register (OUT_UPDATE)
+       b0       OUTCNT_VEN */
+    *(output_ctrl->out_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function VDC5_DisplayCalibration() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for gamma correction
+ * @param[in]   ch          : Channel
+ * @param[in]   gam_on      : Gamma correction ON/OFF setting
+ * @param[in]   param       : Gamma correction setup parameter
+ * @retval      None
+******************************************************************************/
+void VDC5_GammaCorrection (
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      gam_on,
+    const vdc5_gamma_correction_t   * const param)
+{
+    const vdc5_regaddr_gamma_t  * gamma;
+
+    gamma = &vdc5_regaddr_gamma[ch];
+
+    /* Gamma correction on/off control */
+    *(gamma->gam_sw) = (gam_on == VDC5_OFF) ? 0x0000u : 0x0001u;
+
+    if (param != NULL) {
+        /* Start threshold of area 1 to 31 of G signal */
+        Set_StartThreshold_Gamma(param->gam_g_th, gamma->gam_g_area);
+        /* Gain adjustment of area 0 to 31 of G signal */
+        Set_GainAdjustment_Gamma(param->gam_g_gain, gamma->gam_g_lut);
+        /* Register update control register G (GAM_G_UPDATE)
+           b0       GAM_G_VEN */
+        *(gamma->gam_g_update) |= (uint32_t)VDC5_REG_BIT0;
+
+        /* Start threshold of area 1 to 31 of B signal */
+        Set_StartThreshold_Gamma(param->gam_b_th, gamma->gam_b_area);
+        /* Gain adjustment of area 0 to 31 of B signal */
+        Set_GainAdjustment_Gamma(param->gam_b_gain, gamma->gam_b_lut);
+        /* Register update control register B (GAM_B_UPDATE)
+           b0       GAM_B_VEN */
+        *(gamma->gam_b_update) |= (uint32_t)VDC5_REG_BIT0;
+
+        /* Start threshold of area 1 to 31 of R signal */
+        Set_StartThreshold_Gamma(param->gam_r_th, gamma->gam_r_area);
+        /* Gain adjustment of area 0 to 31 of R signal */
+        Set_GainAdjustment_Gamma(param->gam_r_gain, gamma->gam_r_lut);
+        /* Register update control register R (GAM_R_UPDATE)
+           b0       GAM_R_VEN */
+        *(gamma->gam_r_update) |= (uint32_t)VDC5_REG_BIT0;
+    }
+}   /* End of function VDC5_GammaCorrection() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Sets external input video signal
+ * @param[in]   ext_sig_tmp             : External input signal parameter
+ * @param[in]   input_ctrl              : Input controller registers
+ * @retval      None
+******************************************************************************/
+static void SetVideoExternalInput (
+    const vdc5_ext_in_sig_t         * const ext_sig_tmp,
+    const vdc5_regaddr_input_ctrl_t * const input_ctrl)
+{
+    *(input_ctrl->inp_sel_cnt) &= (uint32_t)~VDC5_REG_MASK_0X00007111;
+    /* External input format select */
+    if (ext_sig_tmp->inp_format == VDC5_EXTIN_FORMAT_YCBCR444) {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_EXTIN_FORMAT_RGB888 << VDC5_REG_SHIFT_12;
+    } else {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)ext_sig_tmp->inp_format << VDC5_REG_SHIFT_12;
+    }
+    /* Clock edge select for capturing external input video image signals */
+    if (ext_sig_tmp->inp_pxd_edge != VDC5_EDGE_RISING) {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Clock edge select for capturing external input Vsync signals */
+    if (ext_sig_tmp->inp_vs_edge != VDC5_EDGE_RISING) {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT4;
+    }
+    /* Clock edge select for capturing external input Hsync signals */
+    if (ext_sig_tmp->inp_hs_edge != VDC5_EDGE_RISING) {
+        *(input_ctrl->inp_sel_cnt) |= (uint32_t)VDC5_REG_BIT0;
+    }
+
+    *(input_ctrl->inp_ext_sync_cnt) &= (uint32_t)~VDC5_REG_MASK_0X11110113;
+    /* External input bit endian change on/off control */
+    if (ext_sig_tmp->inp_endian_on != VDC5_OFF) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT28;
+    }
+    /* External input B/R signal swap on/off control */
+    if (ext_sig_tmp->inp_swap_on != VDC5_OFF) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT24;
+    }
+    /* External input Vsync signal DV_VSYNC inversion control */
+    if (ext_sig_tmp->inp_vs_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT20;
+    }
+    /* External input Hsync signal DV_HSYNC inversion control */
+    if (ext_sig_tmp->inp_hs_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT16;
+    }
+    /* Reference select for external input BT.656 Hsync signal */
+    if (ext_sig_tmp->inp_h_edge_sel != VDC5_EXTIN_REF_H_EAV) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Number of lines for BT.656 external input */
+    if (ext_sig_tmp->inp_f525_625 != VDC5_EXTIN_LINE_525) {
+        *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)VDC5_REG_BIT4;
+    }
+    /* Y/Cb/Y/Cr data string start timing to Hsync reference */
+    *(input_ctrl->inp_ext_sync_cnt) |= (uint32_t)ext_sig_tmp->inp_h_pos;
+}   /* End of function SetVideoExternalInput() */
+
+/**************************************************************************//**
+ * @brief       Initializes cascaded connection
+ * @param[in]   ch                      : Channel
+ * @retval      None
+******************************************************************************/
+static void SetInitialConnection (const vdc5_channel_t ch)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+
+    /* Cascade ON */
+    *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT28;
+    /* Graphics register update control register (GR1_UPDATE)
+       b8       GR1_UPDATE */
+    *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT8;
+
+    VDC5_ShrdPrmSetCascade(ch, VDC5_ON);
+
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+
+    /* Turns off alpha blending in a rectangular area */
+    *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT12;
+    /* Selection of lower-layer plane in scaler, graphics 1 is used as lower-layer graphics. */
+    *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+    /* Graphics display mode in VIN */
+    *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+    *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+    /* Disable fade-in and fade-out */
+    *(img_synthesizer->gr_ab6) &= (uint32_t)~VDC5_REG_MASK_0X01FF00FF;
+    /* Set the initial alpha value to '255' */
+    *(img_synthesizer->gr_ab7) |= (uint32_t)VDC5_REG_MASK_0X00FF0000;
+    /* Graphics register update control register (GR_VIN_UPDATE)
+       b8       GR_VIN_UPDATE
+       b4       GR_VIN_P_VEN */
+    *(img_synthesizer->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+
+}   /* End of function SetInitialConnection() */
+
+/**************************************************************************//**
+ * @brief       Sets background color for graphics
+ * @param[in]   ch                  : Channel
+ * @retval      None
+******************************************************************************/
+static void SetGrapicsBackgroundColor (const vdc5_channel_t ch)
+{
+    uint32_t                bg_color_tmp;
+    uint32_t                bg_color_conv;
+    volatile uint32_t     * bg_color_reg;
+    volatile uint32_t     * update_reg;
+    vdc5_graphics_type_t    gr_type_index;
+
+    /* Background color in 24-bit RGB color format or CrYCb format */
+    bg_color_tmp = VDC5_ShrdPrmGetBgColor(ch, VDC5_COLOR_SPACE_GBR);
+    /* Conversion from RGB into GBR / from CrYCb into YCbCr */
+    bg_color_conv   = ColorConversionIntoAgbr(bg_color_tmp);
+    bg_color_conv  &= (uint32_t)VDC5_REG_RGB_24BIT_MASK;
+
+    /* GR2, GR3, VIN, OIR */
+    for (gr_type_index = VDC5_GR_TYPE_GR2; gr_type_index < VDC5_GR_TYPE_NUM; gr_type_index++) {
+        /* Background color in GBR format (GRx_BASE) */
+        bg_color_reg    = vdc5_regaddr_img_synthesizer[ch][gr_type_index].gr_base;
+        *bg_color_reg   = bg_color_conv;
+        /* Graphics register update control register (GRx_UPDATE)
+           b4       GRx_P_VEN */
+        update_reg      = vdc5_regaddr_img_synthesizer[ch][gr_type_index].gr_update;
+        *update_reg    |= (uint32_t)VDC5_REG_BIT4;
+    }
+    /* For OIR */
+    /* Background color in RGB format (OIR_SCL0_OVR1) */
+    bg_color_reg    = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl0_ovr1;
+    *bg_color_reg   = bg_color_tmp;
+    /* Register update control register (OIR_SCL0_UPDATE)
+       b4       SCL0_VEN_B */
+    update_reg      = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl0_update;
+    *update_reg    |= (uint32_t)VDC5_REG_BIT4;
+}   /* End of function SetGrapicsBackgroundColor() */
+
+/**************************************************************************//**
+ * @brief       Sets background color for scaler 0, scaler 1, graphics 0, and graphics 1
+ *
+ *              Description:<br>
+ *              This function should be called only when graphics 0 or graphics 1 is selected.
+ * @param[in]   ch                  : Channel
+ * @param[in]   graphics_id         : Graphics type ID
+ * @param[in]   color_space         : Color space (GBR or YCbCr)
+ * @retval      None
+******************************************************************************/
+static void SetScalerBackgroundColor (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_color_space_t    color_space)
+{
+    volatile uint32_t * scl0_update_reg;
+    volatile uint32_t * scl0_ovr1_reg;
+    volatile uint32_t * gr_base_reg;
+    volatile uint32_t * gr_update_reg;
+    uint32_t            bg_color_tmp;
+    uint32_t            bg_color_conv;
+
+    if (graphics_id == VDC5_GR_TYPE_GR0) {
+        scl0_ovr1_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_ovr1;
+        scl0_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl0_update;
+        gr_base_reg     = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_base;
+        gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
+    } else {
+        /* graphics_id == VDC5_GR_TYPE_GR1 */
+        scl0_ovr1_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_ovr1;
+        scl0_update_reg = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl0_update;
+        gr_base_reg     = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_base;
+        gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
+    }
+    /* Background color in 24-bit RGB color format or CrYCb format */
+    bg_color_tmp    = VDC5_ShrdPrmGetBgColor(ch, color_space);
+    /* Conversion from RGB into GBR / from CrYCb into YCbCr */
+    bg_color_conv   = ColorConversionIntoAgbr(bg_color_tmp);
+    bg_color_conv  &= (uint32_t)VDC5_REG_RGB_24BIT_MASK;
+
+    /* Background color in RGB format or CrYCb format */
+    *scl0_ovr1_reg      = bg_color_tmp;
+    /* Register update control register
+       b4       SCL0_VEN_B */
+    *scl0_update_reg   |= (uint32_t)VDC5_REG_BIT4;
+
+    /* Background color in GBR format or YCbCr format */
+    *gr_base_reg        = bg_color_conv;
+    /* Graphics register update control register
+       b4       GRx_P_VEN */
+    *gr_update_reg     |= (uint32_t)VDC5_REG_BIT4;
+}   /* End of function SetScalerBackgroundColor() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STVA/VS
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STVA_VS (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stva1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stva1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_stva2) &= (uint32_t)~VDC5_REG_BIT4;
+    } else {
+        *(output_ctrl->tcon_tim_stva2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STVA_VS() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STVB/VE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STVB_VE (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stvb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stvb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_stvb2) &= (uint32_t)~VDC5_REG_BIT4;
+    } else {
+        *(output_ctrl->tcon_tim_stvb2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STVB_VE() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STH/HS
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STH_HS (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_sth1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_sth1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_sth2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+        *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_sth2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STH_HS() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - STB/HE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_STB_HE (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_stb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_stb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_stb2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+        *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_stb2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_STB_HE() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - CPV/GCK
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_CPV_GCK (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_cpv1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_cpv1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_cpv2) &= (uint32_t)~VDC5_REG_MASK_0X00000110;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+        *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_cpv2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_CPV_GCK() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - POLA
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_POLA (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_pola1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_pola1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_pola2) &= (uint32_t)~VDC5_REG_MASK_0X00003110;
+    /* POLA/POLB signal generation mode select */
+    *(output_ctrl->tcon_tim_pola2) |= (uint32_t)lcd_tcon->tcon_md << VDC5_REG_SHIFT_12;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+        *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_pola2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_POLA() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - POLB
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_POLB (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Signal pulse start position */
+    *(output_ctrl->tcon_tim_polb1)  = (uint32_t)lcd_tcon->tcon_hsvs << VDC5_REG_SHIFT_16;
+    /* Pulse width */
+    *(output_ctrl->tcon_tim_polb1) |= (uint32_t)lcd_tcon->tcon_hwvw;
+
+    *(output_ctrl->tcon_tim_polb2) &= (uint32_t)~VDC5_REG_MASK_0X00003110;
+    /* POLA/POLB signal generation mode select */
+    *(output_ctrl->tcon_tim_polb2) |= (uint32_t)lcd_tcon->tcon_md << VDC5_REG_SHIFT_12;
+    /* Signal operating reference select */
+    if (lcd_tcon->tcon_hs_sel != VDC5_LCD_TCON_REFSEL_HSYNC) {
+        *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    /* Polarity inversion control of signal */
+    if (lcd_tcon->tcon_inv != VDC5_SIG_POL_NOT_INVERTED) {
+        *(output_ctrl->tcon_tim_polb2) |= (uint32_t)VDC5_REG_BIT4;
+    }
+}   /* End of function SetLcdTcon_POLB() */
+
+/**************************************************************************//**
+ * @brief       Sets LCD TCON - DE
+ * @param[in]   lcd_tcon                : LCD TCON timing signal parameter
+ * @param[in]   output_ctrl             : Output controller registers
+ * @retval      None
+******************************************************************************/
+static void SetLcdTcon_DE (
+    const vdc5_lcd_tcon_timing_t        * const lcd_tcon,
+    const vdc5_regaddr_output_ctrl_t    * const output_ctrl)
+{
+    /* Polarity inversion control of signal */
+    *(output_ctrl->tcon_tim_de) = (lcd_tcon->tcon_inv == VDC5_SIG_POL_NOT_INVERTED) ? (uint32_t)0u : (uint32_t)1u;
+
+}   /* End of function SetLcdTcon_DE() */
+
+/**************************************************************************//**
+ * @brief       Sets scaling-down
+ * @param[in]   scldw_rot               : Scaling-down and rotation parameter
+ * @param[in]   res_inter               : Field operating mode select
+ * @param[in]   scaler                  : Scaler registers
+ * @retval      None
+******************************************************************************/
+static void SetScalingDown (
+    const vdc5_scalingdown_rot_t    * const scldw_rot,
+    const vdc5_res_inter_t                  res_inter,
+    const vdc5_regaddr_scaler_t     * const scaler)
+{
+    uint32_t    vw_before_scld;    /* Vertical width before scaling-down */
+    uint32_t    hw_before_scld;    /* Horizontal width before scaling-down */
+    uint32_t    vw_after_scld;     /* Vertical width after scaling-down */
+    uint32_t    hw_after_scld;     /* Horizontal width after scaling-down */
+    uint32_t    scaling_ratio;
+
+    vw_before_scld = (uint32_t)scldw_rot->res.vw;
+    hw_before_scld = (uint32_t)scldw_rot->res.hw;
+
+    vw_after_scld = (uint32_t)scldw_rot->res_out_vw;
+    hw_after_scld = (uint32_t)scldw_rot->res_out_hw;
+
+    /* Vertical scaling-down: ON, vertical scaling-up: OFF */
+    *(scaler->scl0_ds1) |= (uint32_t)VDC5_REG_BIT4;
+    *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT4;
+    if (vw_before_scld > vw_after_scld) {
+        scaling_ratio = CalcScalingRatio(vw_before_scld, vw_after_scld, scldw_rot->adj_sel, VDC5_OFF);
+
+        *(scaler->scl0_ds6) = scaling_ratio;
+    } else {
+        *(scaler->scl0_ds6) = (uint32_t)SCALING_RATIO_SAME_SIZE;
+    }
+
+    /* Horizontal scaling-down */
+    if (hw_before_scld > hw_after_scld) {
+        /* ON */
+        *(scaler->scl0_ds1) |= (uint32_t)VDC5_REG_BIT0;
+
+        scaling_ratio = CalcScalingRatio(hw_before_scld, hw_after_scld, VDC5_ON, VDC5_ON);
+
+        *(scaler->scl0_ds4) &= (uint32_t)~VDC5_REG_MASK_0X0000FFFF;
+        *(scaler->scl0_ds4) |= scaling_ratio;
+    } else {
+        /* OFF */
+        *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_BIT0;
+    }
+
+    /* Initial scaling phase */
+    *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+    *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+    if (res_inter != VDC5_RES_INTER_PROGRESSIVE) {
+        /* Top */
+        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE << VDC5_REG_SHIFT_16;
+    }
+
+}   /* End of function SetScalingDown() */
+
+/**************************************************************************//**
+ * @brief       Sets scaling-up
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @param[in]   adj_sel                 : Folding handling (on/off)
+ * @param[in]   ip_conversion           : IP conversion on/off
+ * @param[in]   res_ds_wr_md            : Frame buffer writing mode for image processing
+ * @param[in]   ln_off_dir              : Line offset address direction of the frame buffer
+ * @param[in]   scaler                  : Scaler registers
+ * @retval      None
+******************************************************************************/
+static void SetScalingUp (
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_onoff_t                  adj_sel,
+    const vdc5_onoff_t                  ip_conversion,
+    const vdc5_wr_md_t                  res_ds_wr_md,
+    const vdc5_gr_ln_off_dir_t          ln_off_dir,
+    const vdc5_regaddr_scaler_t * const scaler)
+{
+    uint32_t            w_before_scl;       /* Width before scaling-up */
+    uint32_t            w_after_scl;        /* Width after scaling-up */
+    uint32_t            scaling_ratio;
+    vdc5_onoff_t        vscl_up;            /* Vertical scaling-up */
+
+    vscl_up = VDC5_OFF;
+
+    /* Vertical scaling-up */
+    w_before_scl    = (uint32_t)w_read_fb->in_vw;
+    w_after_scl     = (uint32_t)gr_grc->vw;
+    if (w_before_scl < w_after_scl) {
+        /* Vertical scaling-down: OFF, vertical scaling-up: ON */
+        *(scaler->scl0_ds1) &= (uint32_t)~VDC5_REG_BIT4;
+        *(scaler->scl0_us1) |= (uint32_t)VDC5_REG_BIT4;
+
+        scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC5_OFF);
+        *(scaler->scl0_ds6) = scaling_ratio;
+
+        vscl_up = VDC5_ON;
+    } else {
+        /* Vertical scaling-up: OFF */
+        *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT4;
+    }
+
+    /* Horizontal scaling-up */
+    w_before_scl    = (uint32_t)w_read_fb->in_hw;
+    w_after_scl     = (uint32_t)gr_grc->hw;
+    if (w_before_scl < w_after_scl) {
+        /* Horizontal scaling-up: ON */
+        *(scaler->scl0_us1) |= (uint32_t)VDC5_REG_BIT0;
+
+        scaling_ratio = CalcScalingRatio(w_before_scl, w_after_scl, adj_sel, VDC5_OFF);
+
+        *(scaler->scl0_us5) &= (uint32_t)~VDC5_REG_MASK_0X0000FFFF;
+        *(scaler->scl0_us5) |= scaling_ratio;
+    } else {
+        /* Horizontal scaling-up: OFF */
+        *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_BIT0;
+    }
+
+    /* Initial scaling phase */
+    if (ip_conversion == VDC5_OFF) {
+        *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+        *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+    } else {
+        if (vscl_up != VDC5_OFF) {
+            switch (res_ds_wr_md) {
+                case VDC5_WR_MD_ROT_90DEG:
+                    *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    /* US_HB */
+                    *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE;
+                    break;
+                case VDC5_WR_MD_ROT_180DEG:
+                    if (ln_off_dir == VDC5_GR_LN_OFF_DIR_INC) {
+                        *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        /* BTM */
+                        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
+                    }
+                    break;
+                case VDC5_WR_MD_ROT_270DEG:
+                    *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                    /* US_HT */
+                    *(scaler->scl0_us6) |= INITIAL_SCALING_PHASE << VDC5_REG_SHIFT_16;
+                    break;
+                default:    /* Normal or horizontal mirroring */
+                    if (ln_off_dir == VDC5_GR_LN_OFF_DIR_DEC) {
+                        *(scaler->scl0_ds5) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        *(scaler->scl0_us6) &= (uint32_t)~VDC5_REG_MASK_0X0FFF0FFF;
+                        /* BTM */
+                        *(scaler->scl0_ds5) |= INITIAL_SCALING_PHASE;
+                    }
+                    break;
+            }
+        }
+    }
+}   /* End of function SetScalingUp() */
+
+/**************************************************************************//**
+ * @brief       Calculates scaling ratio
+ *
+ *              Description:<br>
+ *              In this function, the overflow in calculation is not considered.
+ *              before_scl and after_scl are 11bit width, so the overflow does not occur.
+ * @param[in]   before_scl              : Size before scaling
+ * @param[in]   after_scl               : Size after scaling
+ * @param[in]   adj_sel                 : Handling for lack of last-input pixel/line, or folding handling
+ * @param[in]   round_up                : Round-up on/off
+ * @retval      Scaling ratio
+******************************************************************************/
+static uint32_t CalcScalingRatio (
+    const uint32_t      before_scl,
+    const uint32_t      after_scl,
+    const vdc5_onoff_t  adj_sel,
+    const vdc5_onoff_t  round_up)
+{
+    float32_t   ratio;
+    float32_t   sigma;
+    int32_t     ratio_int;
+    uint32_t    scaling_ratio;
+
+    /* When parameter checking is not performed,
+       following checks are necessary to avoid a division by zero exception and a negative number. */
+    if ((after_scl == 0u) || (after_scl == 1u)) {
+        scaling_ratio = (uint32_t)SCALING_RATIO_SAME_SIZE;
+    } else {
+        /* ratio = before_scl * 4096.0 / after_scl */
+        ratio  = (float32_t)before_scl * (float32_t)SCALING_RATIO_SAME_SIZE;
+        ratio /= (float32_t)after_scl;
+
+        if (adj_sel != VDC5_OFF) {
+            sigma  = ratio * ((float32_t)after_scl - (float32_t)VDC5_REG_FLOAT_1_0);
+            sigma -= ((float32_t)before_scl - (float32_t)VDC5_REG_FLOAT_1_0) * (float32_t)SCALING_RATIO_SAME_SIZE;
+            sigma /= ((float32_t)after_scl - (float32_t)VDC5_REG_FLOAT_1_0);
+            ratio -= sigma;
+        }
+
+        if (round_up == VDC5_OFF) {
+            /* Round off */
+            ratio    += (float32_t)VDC5_REG_FLOAT_0_5;
+            ratio_int = (int32_t)ratio;
+        } else {
+            /* Round up */
+            ratio_int = (int32_t)ratio;
+            if ((float32_t)ratio_int < ratio) {
+                ratio_int++;
+            }
+        }
+        scaling_ratio = (uint32_t)ratio_int;
+    }
+    return scaling_ratio;
+}   /* End of function CalcScalingRatio() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix in the input controller
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @retval      None
+******************************************************************************/
+static void SetInputCntrlColorMtx (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+    vdc5_channel_t          channel;
+    vdc5_color_space_t      color_space_input;
+    vdc5_color_space_t      color_space_fb;
+    vdc5_colormtx_mode_t    mtx_mode_tmp;
+    const uint16_t        * offset_tmp;
+    const uint16_t        * gain_tmp;
+
+    if (scaling_id == VDC5_SC_TYPE_SC0) {
+        channel = ch;
+    } else {
+        channel = (ch == VDC5_CHANNEL_0) ? VDC5_CHANNEL_1 : VDC5_CHANNEL_0;
+    }
+    color_space_input   = VDC5_ShrdPrmGetColorSpace(channel);
+    color_space_fb      = VDC5_ShrdPrmGetColorSpaceFbWr(ch, scaling_id);
+    /* Color matrix operating mode */
+    if (color_space_input == VDC5_COLOR_SPACE_GBR) {
+        if (color_space_fb == VDC5_COLOR_SPACE_GBR) {
+            /* GBR to GBR */
+            mtx_mode_tmp = VDC5_COLORMTX_GBR_GBR;
+        } else {
+            /* GBR to YCbCr */
+            mtx_mode_tmp = VDC5_COLORMTX_GBR_YCBCR;
+        }
+    } else {
+        if (color_space_fb == VDC5_COLOR_SPACE_GBR) {
+            /* YCbCr to GBR */
+            mtx_mode_tmp = VDC5_COLORMTX_YCBCR_GBR;
+        } else {
+            /* YCbCr to YCbCr */
+            mtx_mode_tmp = VDC5_COLORMTX_YCBCR_YCBCR;
+        }
+    }
+    /* Color matrix offset (DC) adjustment (YG, B, and R) */
+    offset_tmp = colormtx_offset_adj;
+    /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+    gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
+
+    SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc5_regaddr_color_matrix[channel][VDC5_COLORMTX_IMGCNT]);
+
+}   /* End of function SetInputCntrlColorMtx() */
+
+/**************************************************************************//**
+ * @brief       Confirms whether the graphics enlargement will occur or not
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @retval      Graphics enlargement on/off
+******************************************************************************/
+static vdc5_onoff_t ConfirmGraphicsEnlargement (
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc)
+{
+    vdc5_onoff_t graphics_enlargement;
+
+    graphics_enlargement = VDC5_OFF;
+    if (gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) {
+        if ((graphics_id == VDC5_GR_TYPE_GR0) || (graphics_id == VDC5_GR_TYPE_GR1)) {
+            if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) ||
+                    ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw)) {
+                graphics_enlargement = VDC5_ON;
+            }
+        }
+    } else {
+        if (((uint32_t)w_read_fb->in_vw < (uint32_t)gr_grc->vw) || ((uint32_t)w_read_fb->in_hw < (uint32_t)gr_grc->hw)) {
+            graphics_enlargement = VDC5_ON;
+        }
+    }
+    return graphics_enlargement;
+}   /* End of function ConfirmGraphicsEnlargement() */
+
+/**************************************************************************//**
+ * @brief       Sets scaler for graphics
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   w_read_fb               : Size of the frame buffer to be read
+ * @param[in]   gr_grc                  : Graphics display area
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   gr_enlarge              : Graphics enlargement on/off
+ * @retval      None
+******************************************************************************/
+static void SetScalerGraphics (
+    const vdc5_channel_t                ch,
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_width_read_fb_t  * const w_read_fb,
+    const vdc5_period_rect_t    * const gr_grc,
+    const vdc5_gr_flm_sel_t             gr_flm_sel,
+    const vdc5_onoff_t                  gr_enlarge)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_scaler_t           * scaler;
+    vdc5_scaling_type_t                     scaling_id;
+    vdc5_res_inter_t                        res_inter_tmp;
+    vdc5_wr_md_t                            res_ds_wr_md_tmp;
+    vdc5_onoff_t                            adj_sel_tmp;
+    vdc5_onoff_t                            ip_conversion;
+    uint32_t                                reg_data;
+    vdc5_gr_ln_off_dir_t                    ln_off_dir;
+
+    if (graphics_id == VDC5_GR_TYPE_GR0) {
+        /* Scaler 0 */
+        scaling_id = VDC5_SC_TYPE_SC0;
+    } else if (graphics_id == VDC5_GR_TYPE_GR1) {
+        /* Scaler 1 */
+        scaling_id = VDC5_SC_TYPE_SC1;
+    } else {
+        /* OIR */
+        scaling_id = VDC5_SC_TYPE_OIR;
+    }
+
+    scaler = &vdc5_regaddr_scaler[ch][scaling_id];
+
+    if ((gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) && (gr_enlarge == VDC5_OFF)) {
+        /* Normal graphics display */
+        /* Sync signals from the graphics processing block */
+        *(scaler->scl0_us8) |= (uint32_t)VDC5_REG_BIT4;
+
+        /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+           b13      SCL0_VEN_D
+           b4       SCL0_VEN_B */
+        *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT13 | VDC5_REG_BIT4);
+    } else {
+        /* Video image or graphics enlargement */
+        if (graphics_id == VDC5_GR_TYPE_OIR) {
+            /* Turn the vertical scaling-up and the horizontal scaling-up off */
+            *(scaler->scl0_us1) &= (uint32_t)~VDC5_REG_MASK_0X00000011;
+            /* Sync signals from the graphics processing block */
+            *(scaler->scl0_us8) |= (uint32_t)VDC5_REG_BIT4;
+        } else {
+            /* Sync signals from the scaling-up control block */
+            *(scaler->scl0_us8) &= (uint32_t)~VDC5_REG_BIT4;
+
+            /* Graphics display area */
+            *(scaler->scl0_us2)  = (uint32_t)gr_grc->vs << VDC5_REG_SHIFT_16;
+            *(scaler->scl0_us2) |= (uint32_t)gr_grc->vw;
+            *(scaler->scl0_us3)  = (uint32_t)gr_grc->hs << VDC5_REG_SHIFT_16;
+            *(scaler->scl0_us3) |= (uint32_t)gr_grc->hw;
+
+            *(scaler->scl0_us4)  = (uint32_t)w_read_fb->in_vw << VDC5_REG_SHIFT_16;
+            *(scaler->scl0_us4) |= (uint32_t)w_read_fb->in_hw;
+
+            res_ds_wr_md_tmp    = VDC5_ShrdPrmGetWritingMode(ch, scaling_id);
+            adj_sel_tmp         = VDC5_ShrdPrmGetMeasureFolding(ch, graphics_id);
+            ip_conversion       = VDC5_OFF;
+            if ((gr_flm_sel == VDC5_GR_FLM_SEL_SCALE_DOWN) || (gr_flm_sel == VDC5_GR_FLM_SEL_POINTER_BUFF)) {
+                res_inter_tmp = VDC5_ShrdPrmGetInterlace(ch, scaling_id);
+                if (res_inter_tmp != VDC5_RES_INTER_PROGRESSIVE) {
+                    ip_conversion = VDC5_ON;
+                }
+            }
+
+            ln_off_dir = VDC5_ShrdPrmGetLineOfsAddrDir(ch, graphics_id);
+            /* Scaling-up */
+            SetScalingUp(w_read_fb, gr_grc, adj_sel_tmp, ip_conversion, res_ds_wr_md_tmp, ln_off_dir, scaler);
+        }
+        /* Register update control register (SC0_SCL0_UPDATE, SC1_SCL0_UPDATE, OIR_SCL0_UPDATE)
+           b13      SCL0_VEN_D
+           b8       SCL0_UPDATE
+           b4       SCL0_VEN_B
+           b0       SCL0_VEN_A */
+        *(scaler->scl0_update) |= (uint32_t)(VDC5_REG_BIT13 | VDC5_REG_BIT8 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+    }
+
+    if (gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) {
+        img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+        /* Frame buffer frame offset address */
+        reg_data                    = *(scaler->scl1_wr4);
+        *(img_synthesizer->gr_flm4) = reg_data;
+
+        /* Graphics register update control register (GRx_UPDATE)
+           b0       GRx_IBUS_VEN */
+        *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT0;
+    }
+}   /* End of function SetScalerGraphics() */
+
+/**************************************************************************//**
+ * @brief       Gets the amount of data to be skipped through
+ * @param[in]   gr_base                 : Frame buffer base address
+ * @param[in]   gr_format               : Graphics format
+ * @retval      The amount of data to be skipped through
+******************************************************************************/
+static uint32_t DisplayStartPixelSetting (const uint32_t gr_base, const vdc5_gr_format_t gr_format)
+{
+    uint32_t                gr_sta_pos;
+    static const uint32_t   bits_per_pixel[VDC5_GR_FORMAT_NUM] = {
+        VDC5_REG_BIT_PER_PIXEL_RGB565,         /* RGB565 */
+        VDC5_REG_BIT_PER_PIXEL_RGB888,         /* RGB888 */
+        VDC5_REG_BIT_PER_PIXEL_ARGB1555,       /* ARGB1555 */
+        VDC5_REG_BIT_PER_PIXEL_ARGB4444,       /* ARGB4444 */
+        VDC5_REG_BIT_PER_PIXEL_ARGB8888,       /* ARGB8888 */
+        VDC5_REG_BIT_PER_PIXEL_CLUT8,          /* CLUT8 */
+        VDC5_REG_BIT_PER_PIXEL_CLUT4,          /* CLUT4 */
+        VDC5_REG_BIT_PER_PIXEL_CLUT1,          /* CLUT1 */
+        VDC5_REG_BIT_PER_PIXEL_YCBCR422,       /* YCbCr422: In the YCbCr422 format, 32 bits are used for two pixels. */
+        VDC5_REG_BIT_PER_PIXEL_YCBCR444,       /* YCbCr444 */
+        VDC5_REG_BIT_PER_PIXEL_RGBA5551,       /* RGBA5551 */
+        VDC5_REG_BIT_PER_PIXEL_RGBA8888        /* RGBA8888 */
+    };
+
+    gr_sta_pos  = gr_base & (uint32_t)VDC5_REG_MASK_0X00000007;
+    gr_sta_pos *= (uint32_t)VDC5_REG_BIT_PER_PIXEL_VALUE_8;
+    gr_sta_pos /= bits_per_pixel[gr_format];
+    gr_sta_pos &= (uint32_t)VDC5_REG_MASK_0X0000003F;
+
+    return gr_sta_pos;
+}   /* End of function DisplayStartPixelSetting() */
+
+/**************************************************************************//**
+ * @brief       Sets cascaded connection
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   gr_enlarge              : Graphics enlargement on/off
+ * @retval      Cascade ON/OFF
+******************************************************************************/
+static vdc5_onoff_t SetCascade (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_scaler_t           * scaler_0;
+    const vdc5_regaddr_scaler_t           * scaler_1;
+    vdc5_res_vs_in_sel_t                    res_vs_in_sel_tmp;
+    vdc5_onoff_t                            cascade;
+
+    cascade = VDC5_ShrdPrmGetCascade(ch);
+    /* Cascade */
+    if (graphics_id == VDC5_GR_TYPE_GR1) {
+        img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+        scaler_0        = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+        scaler_1        = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+
+        if ((gr_flm_sel != VDC5_GR_FLM_SEL_FLM_NUM) || (gr_enlarge != VDC5_OFF)) {
+            /* Video image or graphics enlargement */
+            /* Cascade OFF */
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_BIT28;
+
+            cascade = VDC5_OFF;
+            /* Get sync signal output and full-screen enable signal select */
+            res_vs_in_sel_tmp = VDC5_ShrdPrmGetVsInSel(ch);
+            if (res_vs_in_sel_tmp == VDC5_RES_VS_IN_SEL_SC0) {
+                /* Use Vsync and enable signal output from scaler 0 */
+                *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+                *(scaler_1->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+            } else {
+                /* Use Vsync and enable signal output from scaler 1 */
+                *(scaler_0->scl0_frc3) |= (uint32_t)VDC5_REG_BIT8;
+                *(scaler_1->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+            }
+        } else {
+            /* Cascade ON */
+            *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_REG_BIT28;
+
+            cascade = VDC5_ON;
+            /* Use Vsync and enable signal output from scaler 0 */
+            *(scaler_0->scl0_frc3) &= (uint32_t)~VDC5_REG_BIT8;
+        }
+        VDC5_ShrdPrmSetCascade(ch, cascade);
+
+        /* Register update control register (SC0_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler_0->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+        /* Register update control register (SC1_SCL0_UPDATE)
+           b8       SCL0_UPDATE */
+        *(scaler_1->scl0_update) |= (uint32_t)VDC5_REG_BIT8;
+        /* Graphics register update control register (GR1_UPDATE)
+           b8       GR1_UPDATE */
+        *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT8;
+    }
+    return cascade;
+}   /* End of function SetCascade() */
+
+/**************************************************************************//**
+ * @brief       Sets VIN synthesizer
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   gr_enlarge              : Graphics enlargement on/off
+ * @retval      None
+******************************************************************************/
+static void SetupGraphicsVIN (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer_vin;
+    vdc5_onoff_t                            cascade;
+    vdc5_resource_state_t                   rsrc_state;
+    vdc5_onoff_t                            und_sel;
+    uint32_t                                reg_data;
+
+    /* Cascade */
+    cascade     = SetCascade(ch, graphics_id, gr_flm_sel, gr_enlarge);
+
+    /* Display area for VIN */
+    rsrc_state  = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+    if ((cascade == VDC5_OFF) &&
+            ((rsrc_state != VDC5_RESOURCE_ST_INVALID) || (graphics_id == VDC5_GR_TYPE_GR0))) {
+        /* Cascade connection OFF and graphics 0 is used */
+        img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+
+        und_sel = VDC5_ShrdPrmGetUndSel(ch);
+        if (und_sel == VDC5_OFF) {
+            /* Graphics 1 is allocated to the upper-layer. */
+            *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
+
+            img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+        } else {
+            /* Graphics 0 is allocated to the upper-layer. */
+            *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+
+            img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+        }
+        /* Graphics display mode in VIN */
+        *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BLEND;
+        /* Copy the graphics display area in the upper-layer to the VIN display area. */
+        reg_data                        = *(img_synthesizer->gr_ab2);
+        *(img_synthesizer_vin->gr_ab2)  = reg_data;
+        reg_data                        = *(img_synthesizer->gr_ab3);
+        *(img_synthesizer_vin->gr_ab3)  = reg_data;
+        /* The valid image area for alpha blending in a rectangular area */
+        reg_data                        = *(img_synthesizer_vin->gr_ab2);
+        *(img_synthesizer_vin->gr_ab4)  = reg_data;
+        reg_data                        = *(img_synthesizer_vin->gr_ab3);
+        *(img_synthesizer_vin->gr_ab5)  = reg_data;
+
+        /* Graphics register update control register (GR_VIN_UPDATE)
+           b8       GR_VIN_UPDATE
+           b4       GR_VIN_P_VEN */
+        *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+    }
+}   /* End of function SetupGraphicsVIN() */
+
+/**************************************************************************//**
+ * @brief       Changes VIN synthesizer settings
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   gr_flm_sel              : Frame buffer address setting signal
+ * @param[in]   gr_enlarge              : Graphics enlargement on/off
+ * @retval      None
+******************************************************************************/
+static void ChangeGraphicsVIN (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_gr_flm_sel_t     gr_flm_sel,
+    const vdc5_onoff_t          gr_enlarge)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer_vin;
+    vdc5_onoff_t                            cascade;
+    vdc5_onoff_t                            cascade_prev;
+    vdc5_resource_state_t                   rsrc_state;
+    vdc5_onoff_t                            und_sel;
+    uint32_t                                reg_data;
+
+    /* Cascade */
+    cascade_prev    = VDC5_ShrdPrmGetCascade(ch);
+    cascade         = SetCascade(ch, graphics_id, gr_flm_sel, gr_enlarge);
+
+    /* Display area for VIN */
+    rsrc_state  = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+    if (rsrc_state != VDC5_RESOURCE_ST_INVALID) {
+        /* Graphics 0 is used */
+        img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+        if (cascade == VDC5_OFF) {
+            /* Cascade connection is OFF */
+            und_sel = VDC5_ShrdPrmGetUndSel(ch);
+            if (und_sel == VDC5_OFF) {
+                /* Graphics 1 is allocated to the upper-layer. */
+                *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
+
+                img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+            } else {
+                /* Graphics 0 is allocated to the upper-layer. */
+                *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+
+                img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+            }
+            /* Graphics display mode in VIN */
+            *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+            *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BLEND;
+            /* Copy the graphics display area in the upper-layer to the VIN display area. */
+            reg_data                        = *(img_synthesizer->gr_ab2);
+            *(img_synthesizer_vin->gr_ab2)  = reg_data;
+            reg_data                        = *(img_synthesizer->gr_ab3);
+            *(img_synthesizer_vin->gr_ab3)  = reg_data;
+        } else {
+            /* Cascade connection is ON */
+            if (cascade_prev == VDC5_OFF) {
+                /* Cascade connection was turned on in this function. */
+                /* Selection of lower-layer plane in scaler is set to 1. */
+                *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+                /* Graphics display mode in VIN */
+                *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+                *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+            }
+        }
+        /* Graphics register update control register (GR_VIN_UPDATE)
+           b8       GR_VIN_UPDATE
+           b4       GR_VIN_P_VEN */
+        *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+    }
+}   /* End of function ChangeGraphicsVIN() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix in the image quality improver
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   color_space             : Color space (GBR or YCbCr)
+ * @retval      None
+******************************************************************************/
+static void SetImgQaImproverColorMtx (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_color_space_t    color_space)
+{
+    vdc5_colormtx_module_t  module_tmp;
+    vdc5_colormtx_mode_t    mtx_mode_tmp;
+    const uint16_t        * offset_tmp;
+    const uint16_t        * gain_tmp;
+
+    /* Color matrix operating mode */
+    if (color_space == VDC5_COLOR_SPACE_GBR) {
+        mtx_mode_tmp = VDC5_COLORMTX_GBR_GBR;
+    } else {
+        mtx_mode_tmp = VDC5_COLORMTX_YCBCR_GBR;
+    }
+    /* Color matrix module */
+    module_tmp = (graphics_id == VDC5_GR_TYPE_GR0) ? VDC5_COLORMTX_ADJ_0 : VDC5_COLORMTX_ADJ_1;
+    /* Color matrix offset (DC) adjustment (YG, B, and R) */
+    offset_tmp = colormtx_offset_adj;
+    /* Color matrix signal gain adjustment (GG, GB, GR, BG, BB, BR, RG, RB, and RR) */
+    gain_tmp = colormtx_gain_adj[mtx_mode_tmp];
+
+    SetColorMatrix(mtx_mode_tmp, offset_tmp, gain_tmp, &vdc5_regaddr_color_matrix[ch][module_tmp]);
+
+}   /* End of function SetImgQaImproverColorMtx() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer writing for scaler 0
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Write_0 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_scaler_t   * scaler;
+    volatile uint32_t               dummy_read;
+    uint32_t                        reg_data;
+
+    /* SC0/GR0 writing */
+    scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0];
+
+    if (ability == VDC5_OFF) {
+        /* SC0 frame buffer writing is disabled */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_0_WR);
+    } else {
+        /* SC0 frame buffer writing is enabled */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
+        /* Reset and reset cancellation of the pointer buffer with dummy read */
+        *(scaler->scl1_pbuf_cnt) |= (uint32_t)VDC5_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+        *(scaler->scl1_pbuf_cnt) &= (uint32_t)~VDC5_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_0_WR);
+    }
+}   /* End of function SetRwProcAbility_Write_0() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer writing for scaler 1
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Write_1 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_scaler_t   * scaler;
+    volatile uint32_t               dummy_read;
+    uint32_t                        reg_data;
+
+    /* SC1/GR1 writing */
+    scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1];
+
+    if (ability == VDC5_OFF) {
+        /* SC1 frame buffer writing is disabled */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_1_WR);
+    } else {
+        /* SC1 frame buffer writing is enabled */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
+        /* Reset and reset cancellation of the pointer buffer with dummy read */
+        *(scaler->scl1_pbuf_cnt) |= (uint32_t)VDC5_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+        *(scaler->scl1_pbuf_cnt) &= (uint32_t)~VDC5_REG_BIT16;
+        reg_data    = *(scaler->scl1_pbuf_cnt);
+        dummy_read  = reg_data;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_1_WR);
+    }
+}   /* End of function SetRwProcAbility_Write_1() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer writing for OIR
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Write_OIR (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_scaler_t * scaler;
+
+    /* OIR writing */
+    scaler = &vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR];
+
+    if (ability == VDC5_OFF) {
+        /* OIR frame buffer writing is disabled */
+        *(scaler->scl1_wr5) &= (uint32_t)~VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_OIR_WR);
+    } else {
+        /* OIR frame buffer writing is enabled */
+        *(scaler->scl1_wr5) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_OIR_WR);
+    }
+}   /* End of function SetRwProcAbility_Write_OIR() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 0
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_0 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* SC0/GR0 reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+
+    if (ability == VDC5_OFF) {
+        /* GR0 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_0_RD);
+    } else {
+        /* GR0 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_0_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_0() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 1
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_1 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* SC1/GR1 reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+
+    if (ability == VDC5_OFF) {
+        /* GR1 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_1_RD);
+    } else {
+        /* GR1 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_1_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_1() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 2
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_2 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* GR2 reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2];
+
+    if (ability == VDC5_OFF) {
+        /* GR2 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_2_RD);
+    } else {
+        /* GR2 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_2_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_2() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for graphics 3
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_3 (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* GR3 reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3];
+
+    if (ability == VDC5_OFF) {
+        /* GR3 frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_LOWER;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_3_RD);
+    } else {
+        /* GR3 frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_3_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_3() */
+
+/**************************************************************************//**
+ * @brief       Activates/deactivates frame buffer reading for OIR
+ * @param[in]   ch              : Channel
+ * @param[in]   ability         : Ability to enable read/write access to the memory
+ * @retval      None
+******************************************************************************/
+static void SetRwProcAbility_Read_OIR (const vdc5_channel_t ch, const vdc5_onoff_t ability)
+{
+    const vdc5_regaddr_img_synthesizer_t * img_synthesizer;
+
+    /* OIR reading */
+    img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR];
+
+    if (ability == VDC5_OFF) {
+        /* OIR frame buffer reading is disabled */
+        *(img_synthesizer->gr_flm_rd) &= (uint32_t)~VDC5_REG_BIT0;
+        /* Graphics display mode */
+        *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+        *(img_synthesizer->gr_ab1) |= (uint32_t)VDC5_DISPSEL_BACK;
+
+        VDC5_ShrdPrmSetRwProcDisable(ch, VDC5_LAYER_ID_OIR_RD);
+    } else {
+        /* OIR frame buffer reading is enabled */
+        *(img_synthesizer->gr_flm_rd) |= (uint32_t)VDC5_REG_BIT0;
+
+        VDC5_ShrdPrmSetRwProcEnable(ch, VDC5_LAYER_ID_OIR_RD);
+    }
+}   /* End of function SetRwProcAbility_Read_OIR() */
+
+/**************************************************************************//**
+ * @brief       Sets register update control register to update the frame buffer
+ *              read and write enable settings.
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+******************************************************************************/
+static void SetRegUpdateRwEnable (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    volatile uint32_t * scl1_update_reg;
+    volatile uint32_t * gr_update_reg;
+
+    switch (layer_id) {
+        case VDC5_LAYER_ID_0_WR:        /* Layer 0, write process */
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_1_WR:        /* Layer 1, write process */
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_OIR_WR:      /* Layer OIR, write process */
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_0_RD:        /* Layer 0, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_1_RD:        /* Layer 1, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_2_RD:        /* Layer 2, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_3_RD:        /* Layer 3, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+        case VDC5_LAYER_ID_OIR_RD:      /* Layer OIR, read process */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+
+        case VDC5_LAYER_ID_ALL:         /* All */
+            /* Register update control register (SCx_SCL1_UPDATE)
+               b20      SCL1_UPDATE_B
+               b4       SCL1_VEN_B
+               b0       SCL1_VEN_A */
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC0].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_SC1].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT20 | VDC5_REG_BIT4 | VDC5_REG_BIT0);
+            /* Register update control register (OIR_SCL1_UPDATE)
+               b4       SCL1_VEN_B
+               b0       SCL1_VEN_A */
+            scl1_update_reg   = vdc5_regaddr_scaler[ch][VDC5_SC_TYPE_OIR].scl1_update;
+            *scl1_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            /* Graphics register update control register (GRx_UPDATE)
+               b4       GRx_P_VEN
+               b0       GRx_IBUS_VEN */
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR2].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR3].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            gr_update_reg   = vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_OIR].gr_update;
+            *gr_update_reg |= (uint32_t)(VDC5_REG_BIT4|VDC5_REG_BIT0);
+            break;
+
+        default:
+            /* DO NOTHING */
+            break;
+    }
+}   /* End of function SetRegUpdateRwEnable() */
+
+/**************************************************************************//**
+ * @brief       Sets graphics display mode
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   gr_disp_sel             : Graphics display mode
+ * @retval      None
+******************************************************************************/
+static void SetGraphicsDisplayMode (
+    const vdc5_channel_t                ch,
+    const vdc5_layer_id_t               layer_id,
+    const vdc5_gr_disp_sel_t    * const gr_disp_sel)
+{
+    uint32_t                                graphics_id;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+
+    if (layer_id == VDC5_LAYER_ID_ALL) {
+        for (graphics_id = 0; graphics_id < VDC5_GR_TYPE_NUM; graphics_id++) {
+            if ((graphics_id != VDC5_GR_TYPE_VIN) && (gr_disp_sel[graphics_id] != VDC5_DISPSEL_IGNORED)) {
+                img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+                *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+                *(img_synthesizer->gr_ab1) |= (uint32_t)gr_disp_sel[graphics_id];
+                /* Graphics register update control register (GRx_UPDATE)
+                   b4       GRx_P_VEN */
+                *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+            }
+        }
+    } else if ((layer_id >= VDC5_LAYER_ID_0_RD) && (layer_id <= VDC5_LAYER_ID_OIR_RD)) {
+        if (*gr_disp_sel != VDC5_DISPSEL_IGNORED) {
+            graphics_id = (uint32_t)(layer_id - VDC5_SC_TYPE_NUM);
+
+            img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][graphics_id];
+
+            *(img_synthesizer->gr_ab1) &= (uint32_t)~VDC5_REG_MASK_0X00000003;
+            *(img_synthesizer->gr_ab1) |= (uint32_t)*gr_disp_sel;
+            /* Graphics register update control register (GRx_UPDATE)
+               b4       GRx_P_VEN */
+            *(img_synthesizer->gr_update) |= (uint32_t)VDC5_REG_BIT4;
+        }
+    } else {
+        /* Do nothing */
+    }
+}   /* End of function SetGraphicsDisplayMode() */
+
+/**************************************************************************//**
+ * @brief       Sets color matrix
+ * @param[in]   mtx_mode                : Operating mode
+ * @param[in]   offset                  : Offset (DC) adjustment of Y/G, B, and R signal
+ * @param[in]   gain                    : GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment
+ * @param[in]   color_matrix            : Color matrix registers
+ * @retval      None
+******************************************************************************/
+static void SetColorMatrix (
+    const vdc5_colormtx_mode_t                  mtx_mode,
+    const uint16_t                      * const offset,
+    const uint16_t                      * const gain,
+    const vdc5_regaddr_color_matrix_t   * const color_matrix)
+{
+    /* Operating mode */
+    *(color_matrix->mtx_mode) = (uint32_t)mtx_mode;
+
+    /* Offset (DC) adjustment of Y/G, B, and R signal and
+       GG, GB, GR, BG, BB, BR, RG, RB, and RR signal gain adjustment */
+    *(color_matrix->mtx_yg_adj0)    = (uint32_t)offset[VDC5_COLORMTX_OFFST_YG] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_yg_adj0)   |= (uint32_t)gain[VDC5_COLORMTX_GAIN_GG];
+    *(color_matrix->mtx_yg_adj1)    = (uint32_t)gain[VDC5_COLORMTX_GAIN_GB] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_yg_adj1)   |= (uint32_t)gain[VDC5_COLORMTX_GAIN_GR];
+    *(color_matrix->mtx_cbb_adj0)   = (uint32_t)offset[VDC5_COLORMTX_OFFST_B] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_cbb_adj0)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_BG];
+    *(color_matrix->mtx_cbb_adj1)   = (uint32_t)gain[VDC5_COLORMTX_GAIN_BB] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_cbb_adj1)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_BR];
+    *(color_matrix->mtx_crr_adj0)   = (uint32_t)offset[VDC5_COLORMTX_OFFST_R] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_crr_adj0)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_RG];
+    *(color_matrix->mtx_crr_adj1)   = (uint32_t)gain[VDC5_COLORMTX_GAIN_RB] << VDC5_REG_SHIFT_16;
+    *(color_matrix->mtx_crr_adj1)  |= (uint32_t)gain[VDC5_COLORMTX_GAIN_RR];
+
+    /* Register update control register (IMGCNT_UPDATE/ADJx_UPDATE)
+       b0       IMGCNT_VEN/ADJx_VEN */
+    *(color_matrix->mtx_update) |= (uint32_t)VDC5_REG_BIT0;
+
+}   /* End of function SetColorMatrix() */
+
+/**************************************************************************//**
+ * @brief       Sets sharpness
+ * @param[in]   shp_h_on                : Sharpness ON/OFF setting
+ * @param[in]   sharp_param             : Sharpness ON/OFF setting
+ * @param[in]   img_qlty_imp            : Image quality improver registers
+ * @retval      None
+******************************************************************************/
+static void SetImageEnhancementSharpness (
+    const vdc5_onoff_t                          shp_h_on,
+    const vdc5_enhance_sharp_t          * const sharp_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp)
+{
+    const vdc5_sharpness_ctrl_t * sharpness_ctrl;
+
+    if (sharp_param != NULL) {
+        /* H1, adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H1];
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC5_REG_MASK_0X0000003F;
+        *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp2)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp2) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+
+        /* H2, second adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H2];
+        /* LPF selection for folding prevention before H2 edge detection */
+        if (sharp_param->shp_h2_lpf_sel == VDC5_OFF) {
+            *(img_qlty_imp->adj_enh_shp3) = (uint32_t)0x00000000u;
+        } else {
+            *(img_qlty_imp->adj_enh_shp3) = (uint32_t)VDC5_REG_BIT16;
+        }
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp3) |= (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp4)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp4) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+
+        /* H3, third adjacent pixel used as reference */
+        sharpness_ctrl = &sharp_param->hrz_sharp[VDC5_IMGENH_SHARP_H3];
+        /* Active sharpness range */
+        *(img_qlty_imp->adj_enh_shp5) = (uint32_t)sharpness_ctrl->shp_core;
+        /* Sharpness correction value clipping and sharpness edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_shp6)  = (uint32_t)sharpness_ctrl->shp_clip_o << VDC5_REG_SHIFT_24;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_clip_u << VDC5_REG_SHIFT_16;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_o << VDC5_REG_SHIFT_8;
+        *(img_qlty_imp->adj_enh_shp6) |= (uint32_t)sharpness_ctrl->shp_gain_u;
+    }
+
+    if (shp_h_on == VDC5_OFF) {
+        *(img_qlty_imp->adj_enh_shp1) &= (uint32_t)~VDC5_REG_BIT16;
+    } else {
+        *(img_qlty_imp->adj_enh_shp1) |= (uint32_t)VDC5_REG_BIT16;
+    }
+}   /* End of function SetImageEnhancementSharpness() */
+
+/**************************************************************************//**
+ * @brief       Sets LTI
+ * @param[in]   lti_h_on                : LTI ON/OFF setting
+ * @param[in]   lti_param               : LTI setup parameter
+ * @param[in]   img_qlty_imp            : Image quality improver registers
+ * @retval      None
+******************************************************************************/
+static void SetImageEnhancementLti (
+    const vdc5_onoff_t                          lti_h_on,
+    const vdc5_enhance_lti_t            * const lti_param,
+    const vdc5_regaddr_img_qlty_imp_t   * const img_qlty_imp)
+{
+    const vdc5_lti_ctrl_t * lti_ctrl;
+
+    if (lti_param != NULL) {
+        /* H2, second adjacent pixel used as reference */
+        lti_ctrl = &lti_param->lti[VDC5_IMGENH_LTI1];
+        /* LPF selection for folding prevention before H2 edge detection */
+        if (lti_param->lti_h2_lpf_sel == VDC5_OFF) {
+            *(img_qlty_imp->adj_enh_lti1) = (uint32_t)0x00000000u;
+        } else {
+            *(img_qlty_imp->adj_enh_lti1) = (uint32_t)VDC5_REG_BIT24;
+        }
+        /* Median filter LTI correction threshold */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC5_REG_SHIFT_16);
+        /* LTI edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC5_REG_SHIFT_8);
+        /* LTI coring (maximum core value of 255) */
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)lti_ctrl->lti_core;
+
+        /* H4, fourth adjacent pixel used as reference */
+        lti_ctrl = &lti_param->lti[VDC5_IMGENH_LTI2];
+        /* Median filter reference pixel select */
+        if (lti_param->lti_h4_median_tap_sel == VDC5_LTI_MDFIL_SEL_ADJ2) {
+            *(img_qlty_imp->adj_enh_lti2) = (uint32_t)0x00000000u;
+        } else {
+            *(img_qlty_imp->adj_enh_lti2) = (uint32_t)VDC5_REG_BIT24;
+        }
+        /* Median filter LTI correction threshold */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_inc_zero << VDC5_REG_SHIFT_16);
+        /* LTI edge amplitude value gain */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)((uint32_t)lti_ctrl->lti_gain << VDC5_REG_SHIFT_8);
+        /* LTI coring (maximum core value of 255) */
+        *(img_qlty_imp->adj_enh_lti2) |= (uint32_t)lti_ctrl->lti_core;
+    }
+
+    if (lti_h_on == VDC5_OFF) {
+        *(img_qlty_imp->adj_enh_lti1) &= (uint32_t)~VDC5_REG_BIT31;
+    } else {
+        *(img_qlty_imp->adj_enh_lti1) |= (uint32_t)VDC5_REG_BIT31;
+    }
+}   /* End of function SetImageEnhancementLti() */
+
+/**************************************************************************//**
+ * @brief       Sets alpha blending area of a rectangle
+ * @param[in]   pd_disp_rect        : Rectangular area for alpha blending
+ * @param[in]   img_synthesizer     : Image synthesizer registers
+ * @retval      None
+******************************************************************************/
+static void SetAlphaRectArea (
+    const vdc5_pd_disp_rect_t               * const pd_disp_rect,
+    const vdc5_regaddr_img_synthesizer_t    * const img_synthesizer)
+{
+    uint32_t v_start;
+    uint32_t h_start;
+
+    if (pd_disp_rect != NULL) {
+        v_start = *(img_synthesizer->gr_ab2) >> VDC5_REG_SHIFT_16;
+        h_start = *(img_synthesizer->gr_ab3) >> VDC5_REG_SHIFT_16;
+
+        v_start += (uint32_t)pd_disp_rect->vs_rel;
+        h_start += (uint32_t)pd_disp_rect->hs_rel;
+        /* If the start position exceeds the maximum bit width, the value should be saturated. */
+        if ((v_start & (uint32_t)~VDC5_REG_MASK_0X000007FF) != 0u) {
+            v_start = (uint32_t)VDC5_REG_MASK_0X000007FF;
+        }
+        if ((h_start & (uint32_t)~VDC5_REG_MASK_0X000007FF) != 0u) {
+            h_start = (uint32_t)VDC5_REG_MASK_0X000007FF;
+        }
+
+        *(img_synthesizer->gr_ab4) = (v_start << VDC5_REG_SHIFT_16) | (uint32_t)pd_disp_rect->vw_rel;
+        *(img_synthesizer->gr_ab5) = (h_start << VDC5_REG_SHIFT_16) | (uint32_t)pd_disp_rect->hw_rel;
+    }
+}   /* End of function SetAlphaRectArea() */
+
+/**************************************************************************//**
+ * @brief       Sets upper-layer and lower-layer plane in scaler
+ * @param[in]   ch                      : Channel
+ * @param[in]   und_sel                 : Selection of lower-layer plane in scaler
+ * @retval      None
+ *****************************************************************************/
+static void SetUndSel (const vdc5_channel_t ch, const vdc5_onoff_t und_sel)
+{
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer;
+    const vdc5_regaddr_img_synthesizer_t  * img_synthesizer_vin;
+    vdc5_onoff_t                            current_und_sel;
+    vdc5_onoff_t                            cascade;
+    vdc5_resource_state_t                   rsrc_state;
+    uint32_t                                reg_data;
+
+    current_und_sel = VDC5_ShrdPrmGetUndSel(ch);
+    if (und_sel != current_und_sel) {
+        VDC5_ShrdPrmSetUndSel(ch, und_sel);
+
+        cascade     = VDC5_ShrdPrmGetCascade(ch);
+        rsrc_state  = VDC5_ShrdPrmGetLayerResource(ch, VDC5_LAYER_ID_0_RD);
+        if ((cascade == VDC5_OFF) && (rsrc_state != VDC5_RESOURCE_ST_INVALID)) {
+            /* Cascade connection OFF and graphics 0 is used */
+            img_synthesizer_vin = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_VIN];
+            if (und_sel == VDC5_OFF) {
+                /* Graphics 1 is allocated to the upper-layer. */
+                *(img_synthesizer_vin->gr_ab1) &= (uint32_t)~VDC5_REG_BIT2;
+
+                img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR1];
+            } else {
+                /* Graphics 0 is allocated to the upper-layer. */
+                *(img_synthesizer_vin->gr_ab1) |= (uint32_t)VDC5_REG_BIT2;
+
+                img_synthesizer = &vdc5_regaddr_img_synthesizer[ch][VDC5_GR_TYPE_GR0];
+            }
+            /* Copy the graphics display area in the upper-layer to the VIN display area. */
+            reg_data                        = *(img_synthesizer->gr_ab2);
+            *(img_synthesizer_vin->gr_ab2)  = reg_data;
+            reg_data                        = *(img_synthesizer->gr_ab3);
+            *(img_synthesizer_vin->gr_ab3)  = reg_data;
+
+            /* Graphics register update control register (GR_VIN_UPDATE)
+               b8       GR_VIN_UPDATE
+               b4       GR_VIN_P_VEN */
+            *(img_synthesizer_vin->gr_update) |= (uint32_t)(VDC5_REG_BIT8|VDC5_REG_BIT4);
+        }
+    }
+}   /* End of function SetUndSel() */
+
+/**************************************************************************//**
+ * @brief       Converts the color format from gr_format format into 24-bit RGB888 format
+ * @param[in]   gr_format           : Color format
+ * @param[in]   input_color         : Color data
+ * @retval      RGB888 color data
+******************************************************************************/
+static uint32_t ColorConversion (const vdc5_gr_format_t gr_format, const uint32_t input_color)
+{
+    uint32_t red;
+    uint32_t green;
+    uint32_t blue;
+    uint32_t conv_color;
+
+    conv_color = 0;
+    switch (gr_format) {
+        case VDC5_GR_FORMAT_RGB565:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGB565_R_MASK) >> VDC5_REG_SHIFT_11));
+            green = ColorConversionFrom6to8((uint32_t)((input_color & VDC5_REG_RGB565_G_MASK) >> VDC5_REG_SHIFT_5));
+            blue  = ColorConversionFrom5to8((uint32_t)(input_color & VDC5_REG_RGB565_B_MASK));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+            break;
+        case VDC5_GR_FORMAT_RGB888:
+            conv_color = ColorConversionIntoAgbr(input_color);
+            break;
+        case VDC5_GR_FORMAT_ARGB1555:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_ARGB1555_R_MASK) >> VDC5_REG_SHIFT_10));
+            green = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_ARGB1555_G_MASK) >> VDC5_REG_SHIFT_5));
+            blue  = ColorConversionFrom5to8((uint32_t)(input_color & VDC5_REG_ARGB1555_B_MASK));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+            break;
+        case VDC5_GR_FORMAT_ARGB4444:
+            red   = ColorConversionFrom4to8((uint32_t)((input_color & VDC5_REG_ARGB4444_R_MASK) >> VDC5_REG_SHIFT_8));
+            green = ColorConversionFrom4to8((uint32_t)((input_color & VDC5_REG_ARGB4444_G_MASK) >> VDC5_REG_SHIFT_4));
+            blue  = ColorConversionFrom4to8((uint32_t)(input_color & VDC5_REG_ARGB4444_B_MASK));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+            break;
+        case VDC5_GR_FORMAT_ARGB8888:
+            conv_color = ColorConversionIntoAgbr((uint32_t)(input_color & VDC5_REG_RGB_24BIT_MASK));
+            break;
+        case VDC5_GR_FORMAT_RGBA5551:
+            red   = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_R_MASK) >> VDC5_REG_SHIFT_11));
+            green = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_G_MASK) >> VDC5_REG_SHIFT_6));
+            blue  = ColorConversionFrom5to8((uint32_t)((input_color & VDC5_REG_RGBA5551_B_MASK) >> VDC5_REG_SHIFT_1));
+            conv_color = (green << VDC5_REG_SHIFT_16) | (blue << VDC5_REG_SHIFT_8) | red;
+            break;
+        case VDC5_GR_FORMAT_RGBA8888:
+            conv_color = ColorConversionIntoAgbr((uint32_t)((input_color >> VDC5_REG_SHIFT_8) & VDC5_REG_RGB_24BIT_MASK));
+            break;
+        default:
+            /* DO NOTHING */
+            break;
+    }
+    return conv_color;
+}   /* End of function ColorConversion() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 4 bits value into 8 bits value
+ * @param[in]   color_value         : 4-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom4to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC5_REG_COLOR_4BIT_MASK;
+    color *= (uint32_t)VDC5_REG_EXTENSION_VALUE_17;
+
+    return color;
+}   /* End of function ColorConversionFrom4to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 5 bits value into 8 bits value
+ * @param[in]   color_value         : 5-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom5to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC5_REG_COLOR_5BIT_MASK;
+    color *= (uint32_t)(VDC5_REG_EXTENSION_VALUE_263 * VDC5_REG_ROUND_OFF_VALUE_2);
+    color /= (uint32_t)VDC5_REG_EXTENSION_VALUE_32;
+    /* Round off */
+    color += (uint32_t)VDC5_REG_ROUND_OFF_VALUE_1;
+    color /= (uint32_t)VDC5_REG_ROUND_OFF_VALUE_2;
+
+    return color;
+}   /* End of function ColorConversionFrom5to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from 6 bits value into 8 bits value
+ * @param[in]   color_value         : 6-bit color data
+ * @retval      8-bit color data
+******************************************************************************/
+static uint32_t ColorConversionFrom6to8 (const uint32_t color_value)
+{
+    uint32_t color;
+
+    color = color_value & (uint32_t)VDC5_REG_COLOR_6BIT_MASK;
+    color *= (uint32_t)(VDC5_REG_EXTENSION_VALUE_259 * VDC5_REG_ROUND_OFF_VALUE_2);
+    color /= (uint32_t)VDC5_REG_EXTENSION_VALUE_64;
+    /* Round off */
+    color += (uint32_t)VDC5_REG_ROUND_OFF_VALUE_1;
+    color /= (uint32_t)VDC5_REG_ROUND_OFF_VALUE_2;
+
+    return color;
+}   /* End of function ColorConversionFrom6to8() */
+
+/**************************************************************************//**
+ * @brief       Converts the color data from ARGB8888 format into AGBR8888 format
+ * @param[in]   color_value         : ARGB8888 color data
+ * @retval      AGBR8888 color data
+******************************************************************************/
+static uint32_t ColorConversionIntoAgbr (const uint32_t color_value)
+{
+    uint32_t color_bgr;
+    uint32_t color_dat;
+
+    /* Green and blue */
+    color_bgr   = (uint32_t)(color_value << VDC5_REG_SHIFT_8);
+    color_bgr  &= (uint32_t)VDC5_REG_ARGB8888_GB_MASK;
+    /* Alpha */
+    color_dat   = (uint32_t)(color_value & VDC5_REG_ALPHA_8BIT);
+    color_bgr  |= color_dat;
+    /* Red */
+    color_dat   = (uint32_t)((color_value >> VDC5_REG_SHIFT_16) & VDC5_REG_COLOR_8BIT_MASK);
+    color_bgr  |= color_dat;
+
+    return color_bgr;
+}   /* End of function ColorConversionIntoAgbr() */
+
+/**************************************************************************//**
+ * @brief       Sets color lookup table (CLUT)
+ * @param[in]   param               : CLUT parameter
+ * @param[out]  regaddr_clut        : CLUT register top address
+ * @retval      None
+******************************************************************************/
+static void Set_Clut (const vdc5_clut_t * const param, volatile uint32_t * regaddr_clut)
+{
+    uint32_t            data_len;
+    const uint32_t    * clut_tmp;
+
+    clut_tmp = param->clut;
+    for (data_len = 0; data_len < param->color_num; data_len++) {
+        *regaddr_clut = *clut_tmp;
+        regaddr_clut++;
+        clut_tmp++;
+    }
+}   /* End of function Set_Clut() */
+
+/**************************************************************************//**
+ * @brief       Sets start threshold for gamma correction
+ * @param[in]   gam_th          : Start threshold of area 1 to 31
+ * @param[out]  gam_area        : Gamma correction registers for start threshold
+ * @retval      None
+******************************************************************************/
+static void Set_StartThreshold_Gamma (const uint8_t * gam_th, volatile uint32_t * const * const gam_area)
+{
+    uint32_t reg_index;
+
+    if (gam_th != NULL) {
+        *(gam_area[0])  = (uint32_t)*gam_th << VDC5_REG_SHIFT_16;
+        gam_th++;
+        *(gam_area[0]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_8;
+        gam_th++;
+        *(gam_area[0]) |= (uint32_t)*gam_th;
+        gam_th++;
+
+        for (reg_index = 1; reg_index < VDC5_GAM_AREA_REG_NUM; reg_index++) {
+            *(gam_area[reg_index])  = (uint32_t)*gam_th << VDC5_REG_SHIFT_24;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_16;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th << VDC5_REG_SHIFT_8;
+            gam_th++;
+            *(gam_area[reg_index]) |= (uint32_t)*gam_th;
+            gam_th++;
+        }
+    }
+}   /* End of function Set_StartThreshold_Gamma() */
+
+/**************************************************************************//**
+ * @brief       Sets gain adjustment for gamma correction
+ * @param[in]   gam_gain        : Gain adjustment of area 0 to 31
+ * @param[out]  gam_lut         : Gamma correction registers for gain adjustment
+ * @retval      None
+******************************************************************************/
+static void Set_GainAdjustment_Gamma (const uint16_t * gam_gain, volatile uint32_t * const * const gam_lut)
+{
+    uint32_t reg_index;
+
+    if (gam_gain != NULL) {
+        for (reg_index = 0; reg_index < VDC5_GAM_LUT_REG_NUM; reg_index++) {
+            *(gam_lut[reg_index])  = (uint32_t)*gam_gain << VDC5_REG_SHIFT_16;
+            gam_gain++;
+            *(gam_lut[reg_index]) |= (uint32_t)*gam_gain;
+            gam_gain++;
+        }
+    }
+}   /* End of function Set_GainAdjustment_Gamma() */
+
+/**************************************************************************//**
+ * @brief       Waits for 200 usec
+ * @param[in]   void
+ * @retval      None
+******************************************************************************/
+static void Wait_200_usec (void)
+{
+    volatile uint32_t   counter;
+
+    for (counter = 0; counter < (uint32_t)VDC5_LVDS_PLL_WAIT_200USEC; counter++) {
+        /* Wait for 200 usec. */
+    }
+}   /* End of function Wait_200_usec() */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdc5/src/r_vdc5_register.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,319 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_register.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver register setup definitions
+******************************************************************************/
+
+#ifndef R_VDC5_REGISTER_H
+#define R_VDC5_REGISTER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC5_GAM_LUT_REG_NUM    (16u)   /*!< The number of table setting register in gamma correction block */
+#define     VDC5_GAM_AREA_REG_NUM   (8u)    /*!< The number of area setting register in gamma correction block */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! VDC5 input controller register address list */
+typedef struct {
+    volatile uint32_t * inp_update;
+    volatile uint32_t * inp_sel_cnt;
+    volatile uint32_t * inp_ext_sync_cnt;
+    volatile uint32_t * inp_vsync_ph_adj;
+    volatile uint32_t * inp_dly_adj;
+    volatile uint32_t * imgcnt_update;
+    volatile uint32_t * imgcnt_nr_cnt0;
+    volatile uint32_t * imgcnt_nr_cnt1;
+} vdc5_regaddr_input_ctrl_t;
+
+/*! VDC5 scaler register address list */
+typedef struct {
+    volatile uint32_t * scl0_update;
+    volatile uint32_t * scl0_frc1;
+    volatile uint32_t * scl0_frc2;
+    volatile uint32_t * scl0_frc3;
+    volatile uint32_t * scl0_frc4;
+    volatile uint32_t * scl0_frc5;
+    volatile uint32_t * scl0_frc6;
+    volatile uint32_t * scl0_frc7;
+    volatile uint32_t * scl0_frc9;
+    volatile uint16_t * scl0_mon0;
+    volatile uint16_t * scl0_int;
+    volatile uint32_t * scl0_ds1;
+    volatile uint32_t * scl0_ds2;
+    volatile uint32_t * scl0_ds3;
+    volatile uint32_t * scl0_ds4;
+    volatile uint32_t * scl0_ds5;
+    volatile uint32_t * scl0_ds6;
+    volatile uint32_t * scl0_ds7;
+    volatile uint32_t * scl0_us1;
+    volatile uint32_t * scl0_us2;
+    volatile uint32_t * scl0_us3;
+    volatile uint32_t * scl0_us4;
+    volatile uint32_t * scl0_us5;
+    volatile uint32_t * scl0_us6;
+    volatile uint32_t * scl0_us7;
+    volatile uint32_t * scl0_us8;
+    volatile uint32_t * scl0_ovr1;
+    volatile uint32_t * scl1_update;
+    volatile uint32_t * scl1_wr1;
+    volatile uint32_t * scl1_wr2;
+    volatile uint32_t * scl1_wr3;
+    volatile uint32_t * scl1_wr4;
+    volatile uint32_t * scl1_wr5;
+    volatile uint32_t * scl1_wr6;
+    volatile uint32_t * scl1_wr7;
+    volatile uint32_t * scl1_wr8;
+    volatile uint32_t * scl1_wr9;
+    volatile uint32_t * scl1_wr10;
+    volatile uint32_t * scl1_wr11;
+    volatile uint32_t * scl1_mon1;
+    volatile uint32_t * scl1_pbuf0;
+    volatile uint32_t * scl1_pbuf1;
+    volatile uint32_t * scl1_pbuf2;
+    volatile uint32_t * scl1_pbuf3;
+    volatile uint32_t * scl1_pbuf_fld;
+    volatile uint32_t * scl1_pbuf_cnt;
+} vdc5_regaddr_scaler_t;
+
+/*! VDC5 image quality improver register address list */
+typedef struct {
+    volatile uint32_t * adj_update;
+    volatile uint32_t * adj_bkstr_set;
+    volatile uint32_t * adj_enh_tim1;
+    volatile uint32_t * adj_enh_tim2;
+    volatile uint32_t * adj_enh_tim3;
+    volatile uint32_t * adj_enh_shp1;
+    volatile uint32_t * adj_enh_shp2;
+    volatile uint32_t * adj_enh_shp3;
+    volatile uint32_t * adj_enh_shp4;
+    volatile uint32_t * adj_enh_shp5;
+    volatile uint32_t * adj_enh_shp6;
+    volatile uint32_t * adj_enh_lti1;
+    volatile uint32_t * adj_enh_lti2;
+} vdc5_regaddr_img_qlty_imp_t;
+
+/*! VDC5 color matrix register address list */
+typedef struct {
+    volatile uint32_t * mtx_update;
+    volatile uint32_t * mtx_mode;
+    volatile uint32_t * mtx_yg_adj0;
+    volatile uint32_t * mtx_yg_adj1;
+    volatile uint32_t * mtx_cbb_adj0;
+    volatile uint32_t * mtx_cbb_adj1;
+    volatile uint32_t * mtx_crr_adj0;
+    volatile uint32_t * mtx_crr_adj1;
+} vdc5_regaddr_color_matrix_t;
+
+/*! VDC5 image synthesizer register address list */
+typedef struct {
+    volatile uint32_t * gr_update;
+    volatile uint32_t * gr_flm_rd;
+    volatile uint32_t * gr_flm1;
+    volatile uint32_t * gr_flm2;
+    volatile uint32_t * gr_flm3;
+    volatile uint32_t * gr_flm4;
+    volatile uint32_t * gr_flm5;
+    volatile uint32_t * gr_flm6;
+    volatile uint32_t * gr_ab1;
+    volatile uint32_t * gr_ab2;
+    volatile uint32_t * gr_ab3;
+    volatile uint32_t * gr_ab4;
+    volatile uint32_t * gr_ab5;
+    volatile uint32_t * gr_ab6;
+    volatile uint32_t * gr_ab7;
+    volatile uint32_t * gr_ab8;
+    volatile uint32_t * gr_ab9;
+    volatile uint32_t * gr_ab10;
+    volatile uint32_t * gr_ab11;
+    volatile uint32_t * gr_base;
+    volatile uint32_t * gr_clut;
+    volatile uint32_t * gr_mon;
+} vdc5_regaddr_img_synthesizer_t;
+
+/*! VDC5 gamma correction register address list */
+typedef struct {
+    volatile uint32_t * gam_sw;
+    volatile uint32_t * gam_g_update;
+    volatile uint32_t * gam_g_lut[VDC5_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_g_area[VDC5_GAM_AREA_REG_NUM];
+    volatile uint32_t * gam_b_update;
+    volatile uint32_t * gam_b_lut[VDC5_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_b_area[VDC5_GAM_AREA_REG_NUM];
+    volatile uint32_t * gam_r_update;
+    volatile uint32_t * gam_r_lut[VDC5_GAM_LUT_REG_NUM];
+    volatile uint32_t * gam_r_area[VDC5_GAM_AREA_REG_NUM];
+} vdc5_regaddr_gamma_t;
+
+/*! VDC5 output controller register address list */
+typedef struct {
+    volatile uint32_t * tcon_update;
+    volatile uint32_t * tcon_tim;
+    volatile uint32_t * tcon_tim_stva1;
+    volatile uint32_t * tcon_tim_stva2;
+    volatile uint32_t * tcon_tim_stvb1;
+    volatile uint32_t * tcon_tim_stvb2;
+    volatile uint32_t * tcon_tim_sth1;
+    volatile uint32_t * tcon_tim_sth2;
+    volatile uint32_t * tcon_tim_stb1;
+    volatile uint32_t * tcon_tim_stb2;
+    volatile uint32_t * tcon_tim_cpv1;
+    volatile uint32_t * tcon_tim_cpv2;
+    volatile uint32_t * tcon_tim_pola1;
+    volatile uint32_t * tcon_tim_pola2;
+    volatile uint32_t * tcon_tim_polb1;
+    volatile uint32_t * tcon_tim_polb2;
+    volatile uint32_t * tcon_tim_de;
+    volatile uint32_t * out_update;
+    volatile uint32_t * out_set;
+    volatile uint32_t * out_bright1;
+    volatile uint32_t * out_bright2;
+    volatile uint32_t * out_contrast;
+    volatile uint32_t * out_pdtha;
+    volatile uint32_t * out_clk_phase;
+} vdc5_regaddr_output_ctrl_t;
+
+/*! VDC5 system controller register address list */
+typedef struct {
+    volatile uint32_t * syscnt_int1;
+    volatile uint32_t * syscnt_int2;
+    volatile uint32_t * syscnt_int3;
+    volatile uint32_t * syscnt_int4;
+    volatile uint32_t * syscnt_int5;
+    volatile uint32_t * syscnt_int6;
+    volatile uint16_t * syscnt_panel_clk;
+    volatile uint16_t * syscnt_clut;
+} vdc5_regaddr_system_ctrl_t;
+
+/*! LVDS register address list */
+typedef struct {
+    volatile uint32_t * lvds_update;
+    volatile uint32_t * lvdsfcl;
+    volatile uint32_t * lclkselr;
+    volatile uint32_t * lpllsetr;
+    volatile uint32_t * lphyacc;
+} vdc5_regaddr_lvds_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const vdc5_regaddr_input_ctrl_t      vdc5_regaddr_input_ctrl[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_scaler_t          vdc5_regaddr_scaler[VDC5_CHANNEL_NUM][VDC5_SC_TYPE_NUM];
+extern const vdc5_regaddr_img_qlty_imp_t    vdc5_regaddr_img_qlty_imp[VDC5_CHANNEL_NUM][VDC5_IMG_IMPRV_NUM];
+extern const vdc5_regaddr_color_matrix_t    vdc5_regaddr_color_matrix[VDC5_CHANNEL_NUM][VDC5_COLORMTX_NUM];
+extern const vdc5_regaddr_img_synthesizer_t vdc5_regaddr_img_synthesizer[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM];
+extern uint32_t                     * const vdc5_regaddr_clut[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM];
+extern const vdc5_regaddr_output_ctrl_t     vdc5_regaddr_output_ctrl[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_gamma_t           vdc5_regaddr_gamma[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_system_ctrl_t     vdc5_regaddr_system_ctrl[VDC5_CHANNEL_NUM];
+extern const vdc5_regaddr_lvds_t            vdc5_regaddr_lvds;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDC5_Initialize(const vdc5_channel_t ch, const vdc5_init_t * const param);
+void VDC5_Terminate(const vdc5_channel_t ch);
+void VDC5_VideoInput(const vdc5_channel_t ch, const vdc5_input_t * const param);
+void VDC5_SyncControl(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+void VDC5_DisplayOutput(const vdc5_channel_t ch, const vdc5_output_t * const param);
+void VDC5_WriteDataControl(
+    const vdc5_channel_t        ch,
+    const vdc5_scaling_type_t   scaling_id,
+    const vdc5_write_t  * const param);
+void VDC5_ChangeWriteProcess(
+    const vdc5_channel_t            ch,
+    const vdc5_scaling_type_t       scaling_id,
+    const vdc5_write_chg_t  * const param);
+void VDC5_ReadDataControl(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param);
+void VDC5_ChangeReadProcess(
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_read_chg_t   * const param);
+void VDC5_StartProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id, const vdc5_start_t * const param);
+void VDC5_StopProcess(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+void VDC5_ReleaseDataControl(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+void VDC5_VideoNoiseReduction(
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      nr1d_on,
+    const vdc5_noise_reduction_t    * const param);
+void VDC5_ImageColorMatrix(const vdc5_channel_t ch, const vdc5_color_matrix_t * const param);
+void VDC5_ImageEnhancement(
+    const vdc5_channel_t                ch,
+    const vdc5_imgimprv_id_t            imgimprv_id,
+    const vdc5_onoff_t                  shp_h_on,
+    const vdc5_enhance_sharp_t  * const sharp_param,
+    const vdc5_onoff_t                  lti_h_on,
+    const vdc5_enhance_lti_t    * const lti_param,
+    const vdc5_period_rect_t    * const enh_area);
+void VDC5_ImageBlackStretch(
+    const vdc5_channel_t        ch,
+    const vdc5_imgimprv_id_t    imgimprv_id,
+    const vdc5_onoff_t          bkstr_on,
+    const vdc5_black_t  * const param);
+void VDC5_AlphaBlending(
+    const vdc5_channel_t                ch,
+    const vdc5_graphics_type_t          graphics_id,
+    const vdc5_alpha_blending_t * const param);
+void VDC5_AlphaBlendingRect(
+    const vdc5_channel_t                        ch,
+    const vdc5_graphics_type_t                  graphics_id,
+    const vdc5_onoff_t                          gr_arc_on,
+    const vdc5_alpha_blending_rect_t    * const param);
+void VDC5_Chromakey(
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_onoff_t              gr_ck_on,
+    const vdc5_chromakey_t  * const param);
+void VDC5_CLUT(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id, const vdc5_clut_t * const param);
+void VDC5_DisplayCalibration(const vdc5_channel_t ch, const vdc5_disp_calibration_t * const param);
+void VDC5_GammaCorrection(
+    const vdc5_channel_t                    ch,
+    const vdc5_onoff_t                      gam_on,
+    const vdc5_gamma_correction_t   * const param);
+
+void VDC5_Int_Disable(const vdc5_channel_t ch);
+void VDC5_Int_SetInterrupt(const vdc5_channel_t ch, const vdc5_int_t * const param);
+
+
+#endif  /* R_VDC5_REGISTER_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdc5/src/r_vdc5_register_address.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1106 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_register_address.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver register address table
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     VDC5_CH0_GR0_CLUT_TBL           (*(uint32_t*)0xFCFF6000u)
+#define     VDC5_CH0_GR1_CLUT_TBL           (*(uint32_t*)0xFCFF6400u)
+#define     VDC5_CH0_GR2_CLUT_TBL           (*(uint32_t*)0xFCFF6800u)
+#define     VDC5_CH0_GR3_CLUT_TBL           (*(uint32_t*)0xFCFF6C00u)
+#define     VDC5_CH0_GR_OIR_CLUT_TBL        (*(uint32_t*)0xFCFF7000u)
+#define     VDC5_CH1_GR0_CLUT_TBL           (*(uint32_t*)0xFCFF8000u)
+#define     VDC5_CH1_GR1_CLUT_TBL           (*(uint32_t*)0xFCFF8400u)
+#define     VDC5_CH1_GR2_CLUT_TBL           (*(uint32_t*)0xFCFF8800u)
+#define     VDC5_CH1_GR3_CLUT_TBL           (*(uint32_t*)0xFCFF8C00u)
+#define     VDC5_CH1_GR_OIR_CLUT_TBL        (*(uint32_t*)0xFCFF9000u)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/* VDC5 input controller register address list */
+const vdc5_regaddr_input_ctrl_t vdc5_regaddr_input_ctrl[VDC5_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        &VDC50.INP_UPDATE,
+        &VDC50.INP_SEL_CNT,
+        &VDC50.INP_EXT_SYNC_CNT,
+        &VDC50.INP_VSYNC_PH_ADJ,
+        &VDC50.INP_DLY_ADJ,
+        &VDC50.IMGCNT_UPDATE,
+        &VDC50.IMGCNT_NR_CNT0,
+        &VDC50.IMGCNT_NR_CNT1
+    },
+    {   /* Channel 1 */
+        &VDC51.INP_UPDATE,
+        &VDC51.INP_SEL_CNT,
+        &VDC51.INP_EXT_SYNC_CNT,
+        &VDC51.INP_VSYNC_PH_ADJ,
+        &VDC51.INP_DLY_ADJ,
+        &VDC51.IMGCNT_UPDATE,
+        &VDC51.IMGCNT_NR_CNT0,
+        &VDC51.IMGCNT_NR_CNT1
+    }
+};
+
+/* VDC5 scaler register address list */
+const vdc5_regaddr_scaler_t vdc5_regaddr_scaler[VDC5_CHANNEL_NUM][VDC5_SC_TYPE_NUM] = {
+    {   /* Channel 0 */
+        {   /* SC0 */
+            &VDC50.SC0_SCL0_UPDATE,
+            &VDC50.SC0_SCL0_FRC1,
+            &VDC50.SC0_SCL0_FRC2,
+            &VDC50.SC0_SCL0_FRC3,
+            &VDC50.SC0_SCL0_FRC4,
+            &VDC50.SC0_SCL0_FRC5,
+            &VDC50.SC0_SCL0_FRC6,
+            &VDC50.SC0_SCL0_FRC7,
+            &VDC50.SC0_SCL0_FRC9,
+            &VDC50.SC0_SCL0_MON0,
+            &VDC50.SC0_SCL0_INT,
+            &VDC50.SC0_SCL0_DS1,
+            &VDC50.SC0_SCL0_DS2,
+            &VDC50.SC0_SCL0_DS3,
+            &VDC50.SC0_SCL0_DS4,
+            &VDC50.SC0_SCL0_DS5,
+            &VDC50.SC0_SCL0_DS6,
+            &VDC50.SC0_SCL0_DS7,
+            &VDC50.SC0_SCL0_US1,
+            &VDC50.SC0_SCL0_US2,
+            &VDC50.SC0_SCL0_US3,
+            &VDC50.SC0_SCL0_US4,
+            &VDC50.SC0_SCL0_US5,
+            &VDC50.SC0_SCL0_US6,
+            &VDC50.SC0_SCL0_US7,
+            &VDC50.SC0_SCL0_US8,
+            &VDC50.SC0_SCL0_OVR1,
+            &VDC50.SC0_SCL1_UPDATE,
+            &VDC50.SC0_SCL1_WR1,
+            &VDC50.SC0_SCL1_WR2,
+            &VDC50.SC0_SCL1_WR3,
+            &VDC50.SC0_SCL1_WR4,
+            &VDC50.SC0_SCL1_WR5,
+            &VDC50.SC0_SCL1_WR6,
+            &VDC50.SC0_SCL1_WR7,
+            &VDC50.SC0_SCL1_WR8,
+            &VDC50.SC0_SCL1_WR9,
+            &VDC50.SC0_SCL1_WR10,
+            &VDC50.SC0_SCL1_WR11,
+            &VDC50.SC0_SCL1_MON1,
+            &VDC50.SC0_SCL1_PBUF0,
+            &VDC50.SC0_SCL1_PBUF1,
+            &VDC50.SC0_SCL1_PBUF2,
+            &VDC50.SC0_SCL1_PBUF3,
+            &VDC50.SC0_SCL1_PBUF_FLD,
+            &VDC50.SC0_SCL1_PBUF_CNT
+        },
+        {   /* SC1 */
+            &VDC50.SC1_SCL0_UPDATE,
+            &VDC50.SC1_SCL0_FRC1,
+            &VDC50.SC1_SCL0_FRC2,
+            &VDC50.SC1_SCL0_FRC3,
+            &VDC50.SC1_SCL0_FRC4,
+            &VDC50.SC1_SCL0_FRC5,
+            &VDC50.SC1_SCL0_FRC6,
+            &VDC50.SC1_SCL0_FRC7,
+            &VDC50.SC1_SCL0_FRC9,
+            &VDC50.SC1_SCL0_MON0,
+            &VDC50.SC1_SCL0_INT,
+            &VDC50.SC1_SCL0_DS1,
+            &VDC50.SC1_SCL0_DS2,
+            &VDC50.SC1_SCL0_DS3,
+            &VDC50.SC1_SCL0_DS4,
+            &VDC50.SC1_SCL0_DS5,
+            &VDC50.SC1_SCL0_DS6,
+            &VDC50.SC1_SCL0_DS7,
+            &VDC50.SC1_SCL0_US1,
+            &VDC50.SC1_SCL0_US2,
+            &VDC50.SC1_SCL0_US3,
+            &VDC50.SC1_SCL0_US4,
+            &VDC50.SC1_SCL0_US5,
+            &VDC50.SC1_SCL0_US6,
+            &VDC50.SC1_SCL0_US7,
+            &VDC50.SC1_SCL0_US8,
+            &VDC50.SC1_SCL0_OVR1,
+            &VDC50.SC1_SCL1_UPDATE,
+            &VDC50.SC1_SCL1_WR1,
+            &VDC50.SC1_SCL1_WR2,
+            &VDC50.SC1_SCL1_WR3,
+            &VDC50.SC1_SCL1_WR4,
+            &VDC50.SC1_SCL1_WR5,
+            &VDC50.SC1_SCL1_WR6,
+            &VDC50.SC1_SCL1_WR7,
+            &VDC50.SC1_SCL1_WR8,
+            &VDC50.SC1_SCL1_WR9,
+            &VDC50.SC1_SCL1_WR10,
+            &VDC50.SC1_SCL1_WR11,
+            &VDC50.SC1_SCL1_MON1,
+            &VDC50.SC1_SCL1_PBUF0,
+            &VDC50.SC1_SCL1_PBUF1,
+            &VDC50.SC1_SCL1_PBUF2,
+            &VDC50.SC1_SCL1_PBUF3,
+            &VDC50.SC1_SCL1_PBUF_FLD,
+            &VDC50.SC1_SCL1_PBUF_CNT
+        },
+        {   /* OIR */
+            &VDC50.OIR_SCL0_UPDATE,
+            &VDC50.OIR_SCL0_FRC1,
+            &VDC50.OIR_SCL0_FRC2,
+            &VDC50.OIR_SCL0_FRC3,
+            &VDC50.OIR_SCL0_FRC4,
+            &VDC50.OIR_SCL0_FRC5,
+            &VDC50.OIR_SCL0_FRC6,
+            &VDC50.OIR_SCL0_FRC7,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.OIR_SCL0_DS1,
+            &VDC50.OIR_SCL0_DS2,
+            &VDC50.OIR_SCL0_DS3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.OIR_SCL0_DS7,
+            &VDC50.OIR_SCL0_US1,
+            &VDC50.OIR_SCL0_US2,
+            &VDC50.OIR_SCL0_US3,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.OIR_SCL0_US8,
+            &VDC50.OIR_SCL0_OVR1,
+            &VDC50.OIR_SCL1_UPDATE,
+            &VDC50.OIR_SCL1_WR1,
+            &VDC50.OIR_SCL1_WR2,
+            &VDC50.OIR_SCL1_WR3,
+            &VDC50.OIR_SCL1_WR4,
+            &VDC50.OIR_SCL1_WR5,
+            &VDC50.OIR_SCL1_WR6,
+            &VDC50.OIR_SCL1_WR7,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL
+        }
+    },
+    {   /* Channel 1 */
+        {   /* SC0 */
+            &VDC51.SC0_SCL0_UPDATE,
+            &VDC51.SC0_SCL0_FRC1,
+            &VDC51.SC0_SCL0_FRC2,
+            &VDC51.SC0_SCL0_FRC3,
+            &VDC51.SC0_SCL0_FRC4,
+            &VDC51.SC0_SCL0_FRC5,
+            &VDC51.SC0_SCL0_FRC6,
+            &VDC51.SC0_SCL0_FRC7,
+            &VDC51.SC0_SCL0_FRC9,
+            &VDC51.SC0_SCL0_MON0,
+            &VDC51.SC0_SCL0_INT,
+            &VDC51.SC0_SCL0_DS1,
+            &VDC51.SC0_SCL0_DS2,
+            &VDC51.SC0_SCL0_DS3,
+            &VDC51.SC0_SCL0_DS4,
+            &VDC51.SC0_SCL0_DS5,
+            &VDC51.SC0_SCL0_DS6,
+            &VDC51.SC0_SCL0_DS7,
+            &VDC51.SC0_SCL0_US1,
+            &VDC51.SC0_SCL0_US2,
+            &VDC51.SC0_SCL0_US3,
+            &VDC51.SC0_SCL0_US4,
+            &VDC51.SC0_SCL0_US5,
+            &VDC51.SC0_SCL0_US6,
+            &VDC51.SC0_SCL0_US7,
+            &VDC51.SC0_SCL0_US8,
+            &VDC51.SC0_SCL0_OVR1,
+            &VDC51.SC0_SCL1_UPDATE,
+            &VDC51.SC0_SCL1_WR1,
+            &VDC51.SC0_SCL1_WR2,
+            &VDC51.SC0_SCL1_WR3,
+            &VDC51.SC0_SCL1_WR4,
+            &VDC51.SC0_SCL1_WR5,
+            &VDC51.SC0_SCL1_WR6,
+            &VDC51.SC0_SCL1_WR7,
+            &VDC51.SC0_SCL1_WR8,
+            &VDC51.SC0_SCL1_WR9,
+            &VDC51.SC0_SCL1_WR10,
+            &VDC51.SC0_SCL1_WR11,
+            &VDC51.SC0_SCL1_MON1,
+            &VDC51.SC0_SCL1_PBUF0,
+            &VDC51.SC0_SCL1_PBUF1,
+            &VDC51.SC0_SCL1_PBUF2,
+            &VDC51.SC0_SCL1_PBUF3,
+            &VDC51.SC0_SCL1_PBUF_FLD,
+            &VDC51.SC0_SCL1_PBUF_CNT
+        },
+        {   /* SC1 */
+            &VDC51.SC1_SCL0_UPDATE,
+            &VDC51.SC1_SCL0_FRC1,
+            &VDC51.SC1_SCL0_FRC2,
+            &VDC51.SC1_SCL0_FRC3,
+            &VDC51.SC1_SCL0_FRC4,
+            &VDC51.SC1_SCL0_FRC5,
+            &VDC51.SC1_SCL0_FRC6,
+            &VDC51.SC1_SCL0_FRC7,
+            &VDC51.SC1_SCL0_FRC9,
+            &VDC51.SC1_SCL0_MON0,
+            &VDC51.SC1_SCL0_INT,
+            &VDC51.SC1_SCL0_DS1,
+            &VDC51.SC1_SCL0_DS2,
+            &VDC51.SC1_SCL0_DS3,
+            &VDC51.SC1_SCL0_DS4,
+            &VDC51.SC1_SCL0_DS5,
+            &VDC51.SC1_SCL0_DS6,
+            &VDC51.SC1_SCL0_DS7,
+            &VDC51.SC1_SCL0_US1,
+            &VDC51.SC1_SCL0_US2,
+            &VDC51.SC1_SCL0_US3,
+            &VDC51.SC1_SCL0_US4,
+            &VDC51.SC1_SCL0_US5,
+            &VDC51.SC1_SCL0_US6,
+            &VDC51.SC1_SCL0_US7,
+            &VDC51.SC1_SCL0_US8,
+            &VDC51.SC1_SCL0_OVR1,
+            &VDC51.SC1_SCL1_UPDATE,
+            &VDC51.SC1_SCL1_WR1,
+            &VDC51.SC1_SCL1_WR2,
+            &VDC51.SC1_SCL1_WR3,
+            &VDC51.SC1_SCL1_WR4,
+            &VDC51.SC1_SCL1_WR5,
+            &VDC51.SC1_SCL1_WR6,
+            &VDC51.SC1_SCL1_WR7,
+            &VDC51.SC1_SCL1_WR8,
+            &VDC51.SC1_SCL1_WR9,
+            &VDC51.SC1_SCL1_WR10,
+            &VDC51.SC1_SCL1_WR11,
+            &VDC51.SC1_SCL1_MON1,
+            &VDC51.SC1_SCL1_PBUF0,
+            &VDC51.SC1_SCL1_PBUF1,
+            &VDC51.SC1_SCL1_PBUF2,
+            &VDC51.SC1_SCL1_PBUF3,
+            &VDC51.SC1_SCL1_PBUF_FLD,
+            &VDC51.SC1_SCL1_PBUF_CNT
+        },
+        {   /* OIR */
+            &VDC51.OIR_SCL0_UPDATE,
+            &VDC51.OIR_SCL0_FRC1,
+            &VDC51.OIR_SCL0_FRC2,
+            &VDC51.OIR_SCL0_FRC3,
+            &VDC51.OIR_SCL0_FRC4,
+            &VDC51.OIR_SCL0_FRC5,
+            &VDC51.OIR_SCL0_FRC6,
+            &VDC51.OIR_SCL0_FRC7,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.OIR_SCL0_DS1,
+            &VDC51.OIR_SCL0_DS2,
+            &VDC51.OIR_SCL0_DS3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.OIR_SCL0_DS7,
+            &VDC51.OIR_SCL0_US1,
+            &VDC51.OIR_SCL0_US2,
+            &VDC51.OIR_SCL0_US3,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.OIR_SCL0_US8,
+            &VDC51.OIR_SCL0_OVR1,
+            &VDC51.OIR_SCL1_UPDATE,
+            &VDC51.OIR_SCL1_WR1,
+            &VDC51.OIR_SCL1_WR2,
+            &VDC51.OIR_SCL1_WR3,
+            &VDC51.OIR_SCL1_WR4,
+            &VDC51.OIR_SCL1_WR5,
+            &VDC51.OIR_SCL1_WR6,
+            &VDC51.OIR_SCL1_WR7,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL
+        }
+    }
+};
+
+/* VDC5 image quality improver register address list */
+const vdc5_regaddr_img_qlty_imp_t vdc5_regaddr_img_qlty_imp[VDC5_CHANNEL_NUM][VDC5_IMG_IMPRV_NUM] = {
+    {   /* Channel 0 */
+        {   /* SC0 */
+            &VDC50.ADJ0_UPDATE,
+            &VDC50.ADJ0_BKSTR_SET,
+            &VDC50.ADJ0_ENH_TIM1,
+            &VDC50.ADJ0_ENH_TIM2,
+            &VDC50.ADJ0_ENH_TIM3,
+            &VDC50.ADJ0_ENH_SHP1,
+            &VDC50.ADJ0_ENH_SHP2,
+            &VDC50.ADJ0_ENH_SHP3,
+            &VDC50.ADJ0_ENH_SHP4,
+            &VDC50.ADJ0_ENH_SHP5,
+            &VDC50.ADJ0_ENH_SHP6,
+            &VDC50.ADJ0_ENH_LTI1,
+            &VDC50.ADJ0_ENH_LTI2
+        },
+        {   /* SC1 */
+            &VDC50.ADJ1_UPDATE,
+            &VDC50.ADJ1_BKSTR_SET,
+            &VDC50.ADJ1_ENH_TIM1,
+            &VDC50.ADJ1_ENH_TIM2,
+            &VDC50.ADJ1_ENH_TIM3,
+            &VDC50.ADJ1_ENH_SHP1,
+            &VDC50.ADJ1_ENH_SHP2,
+            &VDC50.ADJ1_ENH_SHP3,
+            &VDC50.ADJ1_ENH_SHP4,
+            &VDC50.ADJ1_ENH_SHP5,
+            &VDC50.ADJ1_ENH_SHP6,
+            &VDC50.ADJ1_ENH_LTI1,
+            &VDC50.ADJ1_ENH_LTI2
+        }
+    },
+    {   /* Channel 1 */
+        {   /* SC0 */
+            &VDC51.ADJ0_UPDATE,
+            &VDC51.ADJ0_BKSTR_SET,
+            &VDC51.ADJ0_ENH_TIM1,
+            &VDC51.ADJ0_ENH_TIM2,
+            &VDC51.ADJ0_ENH_TIM3,
+            &VDC51.ADJ0_ENH_SHP1,
+            &VDC51.ADJ0_ENH_SHP2,
+            &VDC51.ADJ0_ENH_SHP3,
+            &VDC51.ADJ0_ENH_SHP4,
+            &VDC51.ADJ0_ENH_SHP5,
+            &VDC51.ADJ0_ENH_SHP6,
+            &VDC51.ADJ0_ENH_LTI1,
+            &VDC51.ADJ0_ENH_LTI2
+        },
+        {   /* SC1 */
+            &VDC51.ADJ1_UPDATE,
+            &VDC51.ADJ1_BKSTR_SET,
+            &VDC51.ADJ1_ENH_TIM1,
+            &VDC51.ADJ1_ENH_TIM2,
+            &VDC51.ADJ1_ENH_TIM3,
+            &VDC51.ADJ1_ENH_SHP1,
+            &VDC51.ADJ1_ENH_SHP2,
+            &VDC51.ADJ1_ENH_SHP3,
+            &VDC51.ADJ1_ENH_SHP4,
+            &VDC51.ADJ1_ENH_SHP5,
+            &VDC51.ADJ1_ENH_SHP6,
+            &VDC51.ADJ1_ENH_LTI1,
+            &VDC51.ADJ1_ENH_LTI2
+        }
+    }
+};
+
+/* VDC5 color matrix register address list */
+const vdc5_regaddr_color_matrix_t vdc5_regaddr_color_matrix[VDC5_CHANNEL_NUM][VDC5_COLORMTX_NUM] = {
+    {   /* Channel 0 */
+        {   /* Input Controller */
+            &VDC50.IMGCNT_UPDATE,
+            &VDC50.IMGCNT_MTX_MODE,
+            &VDC50.IMGCNT_MTX_YG_ADJ0,
+            &VDC50.IMGCNT_MTX_YG_ADJ1,
+            &VDC50.IMGCNT_MTX_CBB_ADJ0,
+            &VDC50.IMGCNT_MTX_CBB_ADJ1,
+            &VDC50.IMGCNT_MTX_CRR_ADJ0,
+            &VDC50.IMGCNT_MTX_CRR_ADJ1
+        },
+        {   /* Image quality improver 0 */
+            &VDC50.ADJ0_UPDATE,
+            &VDC50.ADJ0_MTX_MODE,
+            &VDC50.ADJ0_MTX_YG_ADJ0,
+            &VDC50.ADJ0_MTX_YG_ADJ1,
+            &VDC50.ADJ0_MTX_CBB_ADJ0,
+            &VDC50.ADJ0_MTX_CBB_ADJ1,
+            &VDC50.ADJ0_MTX_CRR_ADJ0,
+            &VDC50.ADJ0_MTX_CRR_ADJ1
+        },
+        {   /* Image quality improver 1 */
+            &VDC50.ADJ1_UPDATE,
+            &VDC50.ADJ1_MTX_MODE,
+            &VDC50.ADJ1_MTX_YG_ADJ0,
+            &VDC50.ADJ1_MTX_YG_ADJ1,
+            &VDC50.ADJ1_MTX_CBB_ADJ0,
+            &VDC50.ADJ1_MTX_CBB_ADJ1,
+            &VDC50.ADJ1_MTX_CRR_ADJ0,
+            &VDC50.ADJ1_MTX_CRR_ADJ1
+        }
+    },
+    {   /* Channel 1 */
+        {   /* Input Controller */
+            &VDC51.IMGCNT_UPDATE,
+            &VDC51.IMGCNT_MTX_MODE,
+            &VDC51.IMGCNT_MTX_YG_ADJ0,
+            &VDC51.IMGCNT_MTX_YG_ADJ1,
+            &VDC51.IMGCNT_MTX_CBB_ADJ0,
+            &VDC51.IMGCNT_MTX_CBB_ADJ1,
+            &VDC51.IMGCNT_MTX_CRR_ADJ0,
+            &VDC51.IMGCNT_MTX_CRR_ADJ1
+        },
+        {   /* Image quality improver 0 */
+            &VDC51.ADJ0_UPDATE,
+            &VDC51.ADJ0_MTX_MODE,
+            &VDC51.ADJ0_MTX_YG_ADJ0,
+            &VDC51.ADJ0_MTX_YG_ADJ1,
+            &VDC51.ADJ0_MTX_CBB_ADJ0,
+            &VDC51.ADJ0_MTX_CBB_ADJ1,
+            &VDC51.ADJ0_MTX_CRR_ADJ0,
+            &VDC51.ADJ0_MTX_CRR_ADJ1
+        },
+        {   /* Image quality improver 1 */
+            &VDC51.ADJ1_UPDATE,
+            &VDC51.ADJ1_MTX_MODE,
+            &VDC51.ADJ1_MTX_YG_ADJ0,
+            &VDC51.ADJ1_MTX_YG_ADJ1,
+            &VDC51.ADJ1_MTX_CBB_ADJ0,
+            &VDC51.ADJ1_MTX_CBB_ADJ1,
+            &VDC51.ADJ1_MTX_CRR_ADJ0,
+            &VDC51.ADJ1_MTX_CRR_ADJ1
+        }
+    }
+};
+
+/* VDC5 image synthesizer register address list */
+const vdc5_regaddr_img_synthesizer_t vdc5_regaddr_img_synthesizer[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM] = {
+    {   /* Channel 0 */
+        {   /* GR0 */
+            &VDC50.GR0_UPDATE,
+            &VDC50.GR0_FLM_RD,
+            &VDC50.GR0_FLM1,
+            &VDC50.GR0_FLM2,
+            &VDC50.GR0_FLM3,
+            &VDC50.GR0_FLM4,
+            &VDC50.GR0_FLM5,
+            &VDC50.GR0_FLM6,
+            &VDC50.GR0_AB1,
+            &VDC50.GR0_AB2,
+            &VDC50.GR0_AB3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.GR0_AB7,
+            &VDC50.GR0_AB8,
+            &VDC50.GR0_AB9,
+            &VDC50.GR0_AB10,
+            &VDC50.GR0_AB11,
+            &VDC50.GR0_BASE,
+            &VDC50.GR0_CLUT,
+            NULL
+        },
+        {   /* GR1 */
+            &VDC50.GR1_UPDATE,
+            &VDC50.GR1_FLM_RD,
+            &VDC50.GR1_FLM1,
+            &VDC50.GR1_FLM2,
+            &VDC50.GR1_FLM3,
+            &VDC50.GR1_FLM4,
+            &VDC50.GR1_FLM5,
+            &VDC50.GR1_FLM6,
+            &VDC50.GR1_AB1,
+            &VDC50.GR1_AB2,
+            &VDC50.GR1_AB3,
+            &VDC50.GR1_AB4,
+            &VDC50.GR1_AB5,
+            &VDC50.GR1_AB6,
+            &VDC50.GR1_AB7,
+            &VDC50.GR1_AB8,
+            &VDC50.GR1_AB9,
+            &VDC50.GR1_AB10,
+            &VDC50.GR1_AB11,
+            &VDC50.GR1_BASE,
+            &VDC50.GR1_CLUT,
+            &VDC50.GR1_MON
+        },
+        {   /* GR2 */
+            &VDC50.GR2_UPDATE,
+            &VDC50.GR2_FLM_RD,
+            &VDC50.GR2_FLM1,
+            &VDC50.GR2_FLM2,
+            &VDC50.GR2_FLM3,
+            &VDC50.GR2_FLM4,
+            &VDC50.GR2_FLM5,
+            &VDC50.GR2_FLM6,
+            &VDC50.GR2_AB1,
+            &VDC50.GR2_AB2,
+            &VDC50.GR2_AB3,
+            &VDC50.GR2_AB4,
+            &VDC50.GR2_AB5,
+            &VDC50.GR2_AB6,
+            &VDC50.GR2_AB7,
+            &VDC50.GR2_AB8,
+            &VDC50.GR2_AB9,
+            &VDC50.GR2_AB10,
+            &VDC50.GR2_AB11,
+            &VDC50.GR2_BASE,
+            &VDC50.GR2_CLUT,
+            &VDC50.GR2_MON
+        },
+        {   /* GR3 */
+            &VDC50.GR3_UPDATE,
+            &VDC50.GR3_FLM_RD,
+            &VDC50.GR3_FLM1,
+            &VDC50.GR3_FLM2,
+            &VDC50.GR3_FLM3,
+            &VDC50.GR3_FLM4,
+            &VDC50.GR3_FLM5,
+            &VDC50.GR3_FLM6,
+            &VDC50.GR3_AB1,
+            &VDC50.GR3_AB2,
+            &VDC50.GR3_AB3,
+            &VDC50.GR3_AB4,
+            &VDC50.GR3_AB5,
+            &VDC50.GR3_AB6,
+            &VDC50.GR3_AB7,
+            &VDC50.GR3_AB8,
+            &VDC50.GR3_AB9,
+            &VDC50.GR3_AB10,
+            &VDC50.GR3_AB11,
+            &VDC50.GR3_BASE,
+            &VDC50.GR3_CLUT_INT,
+            &VDC50.GR3_MON
+        },
+        {   /* VIN */
+            &VDC50.GR_VIN_UPDATE,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.GR_VIN_AB1,
+            &VDC50.GR_VIN_AB2,
+            &VDC50.GR_VIN_AB3,
+            &VDC50.GR_VIN_AB4,
+            &VDC50.GR_VIN_AB5,
+            &VDC50.GR_VIN_AB6,
+            &VDC50.GR_VIN_AB7,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.GR_VIN_BASE,
+            NULL,
+            &VDC50.GR_VIN_MON
+        },
+        {   /* OIR */
+            &VDC50.GR_OIR_UPDATE,
+            &VDC50.GR_OIR_FLM_RD,
+            &VDC50.GR_OIR_FLM1,
+            &VDC50.GR_OIR_FLM2,
+            &VDC50.GR_OIR_FLM3,
+            &VDC50.GR_OIR_FLM4,
+            &VDC50.GR_OIR_FLM5,
+            &VDC50.GR_OIR_FLM6,
+            &VDC50.GR_OIR_AB1,
+            &VDC50.GR_OIR_AB2,
+            &VDC50.GR_OIR_AB3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC50.GR_OIR_AB7,
+            &VDC50.GR_OIR_AB8,
+            &VDC50.GR_OIR_AB9,
+            &VDC50.GR_OIR_AB10,
+            &VDC50.GR_OIR_AB11,
+            &VDC50.GR_OIR_BASE,
+            &VDC50.GR_OIR_CLUT,
+            &VDC50.GR_OIR_MON
+        }
+    },
+    {   /* Channel 1 */
+        {   /* GR0 */
+            &VDC51.GR0_UPDATE,
+            &VDC51.GR0_FLM_RD,
+            &VDC51.GR0_FLM1,
+            &VDC51.GR0_FLM2,
+            &VDC51.GR0_FLM3,
+            &VDC51.GR0_FLM4,
+            &VDC51.GR0_FLM5,
+            &VDC51.GR0_FLM6,
+            &VDC51.GR0_AB1,
+            &VDC51.GR0_AB2,
+            &VDC51.GR0_AB3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.GR0_AB7,
+            &VDC51.GR0_AB8,
+            &VDC51.GR0_AB9,
+            &VDC51.GR0_AB10,
+            &VDC51.GR0_AB11,
+            &VDC51.GR0_BASE,
+            &VDC51.GR0_CLUT,
+            NULL
+        },
+        {   /* GR1 */
+            &VDC51.GR1_UPDATE,
+            &VDC51.GR1_FLM_RD,
+            &VDC51.GR1_FLM1,
+            &VDC51.GR1_FLM2,
+            &VDC51.GR1_FLM3,
+            &VDC51.GR1_FLM4,
+            &VDC51.GR1_FLM5,
+            &VDC51.GR1_FLM6,
+            &VDC51.GR1_AB1,
+            &VDC51.GR1_AB2,
+            &VDC51.GR1_AB3,
+            &VDC51.GR1_AB4,
+            &VDC51.GR1_AB5,
+            &VDC51.GR1_AB6,
+            &VDC51.GR1_AB7,
+            &VDC51.GR1_AB8,
+            &VDC51.GR1_AB9,
+            &VDC51.GR1_AB10,
+            &VDC51.GR1_AB11,
+            &VDC51.GR1_BASE,
+            &VDC51.GR1_CLUT,
+            &VDC51.GR1_MON
+        },
+        {   /* GR2 */
+            &VDC51.GR2_UPDATE,
+            &VDC51.GR2_FLM_RD,
+            &VDC51.GR2_FLM1,
+            &VDC51.GR2_FLM2,
+            &VDC51.GR2_FLM3,
+            &VDC51.GR2_FLM4,
+            &VDC51.GR2_FLM5,
+            &VDC51.GR2_FLM6,
+            &VDC51.GR2_AB1,
+            &VDC51.GR2_AB2,
+            &VDC51.GR2_AB3,
+            &VDC51.GR2_AB4,
+            &VDC51.GR2_AB5,
+            &VDC51.GR2_AB6,
+            &VDC51.GR2_AB7,
+            &VDC51.GR2_AB8,
+            &VDC51.GR2_AB9,
+            &VDC51.GR2_AB10,
+            &VDC51.GR2_AB11,
+            &VDC51.GR2_BASE,
+            &VDC51.GR2_CLUT,
+            &VDC51.GR2_MON
+        },
+        {   /* GR3 */
+            &VDC51.GR3_UPDATE,
+            &VDC51.GR3_FLM_RD,
+            &VDC51.GR3_FLM1,
+            &VDC51.GR3_FLM2,
+            &VDC51.GR3_FLM3,
+            &VDC51.GR3_FLM4,
+            &VDC51.GR3_FLM5,
+            &VDC51.GR3_FLM6,
+            &VDC51.GR3_AB1,
+            &VDC51.GR3_AB2,
+            &VDC51.GR3_AB3,
+            &VDC51.GR3_AB4,
+            &VDC51.GR3_AB5,
+            &VDC51.GR3_AB6,
+            &VDC51.GR3_AB7,
+            &VDC51.GR3_AB8,
+            &VDC51.GR3_AB9,
+            &VDC51.GR3_AB10,
+            &VDC51.GR3_AB11,
+            &VDC51.GR3_BASE,
+            &VDC51.GR3_CLUT_INT,
+            &VDC51.GR3_MON
+        },
+        {   /* VIN */
+            &VDC51.GR_VIN_UPDATE,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.GR_VIN_AB1,
+            &VDC51.GR_VIN_AB2,
+            &VDC51.GR_VIN_AB3,
+            &VDC51.GR_VIN_AB4,
+            &VDC51.GR_VIN_AB5,
+            &VDC51.GR_VIN_AB6,
+            &VDC51.GR_VIN_AB7,
+            NULL,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.GR_VIN_BASE,
+            NULL,
+            &VDC51.GR_VIN_MON
+        },
+        {   /* OIR */
+            &VDC51.GR_OIR_UPDATE,
+            &VDC51.GR_OIR_FLM_RD,
+            &VDC51.GR_OIR_FLM1,
+            &VDC51.GR_OIR_FLM2,
+            &VDC51.GR_OIR_FLM3,
+            &VDC51.GR_OIR_FLM4,
+            &VDC51.GR_OIR_FLM5,
+            &VDC51.GR_OIR_FLM6,
+            &VDC51.GR_OIR_AB1,
+            &VDC51.GR_OIR_AB2,
+            &VDC51.GR_OIR_AB3,
+            NULL,
+            NULL,
+            NULL,
+            &VDC51.GR_OIR_AB7,
+            &VDC51.GR_OIR_AB8,
+            &VDC51.GR_OIR_AB9,
+            &VDC51.GR_OIR_AB10,
+            &VDC51.GR_OIR_AB11,
+            &VDC51.GR_OIR_BASE,
+            &VDC51.GR_OIR_CLUT,
+            &VDC51.GR_OIR_MON
+        }
+    }
+};
+
+/* VDC5 CLUT register address list */
+uint32_t * const vdc5_regaddr_clut[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM] = {
+    {   /* Channel 0 */
+        &VDC5_CH0_GR0_CLUT_TBL,
+        &VDC5_CH0_GR1_CLUT_TBL,
+        &VDC5_CH0_GR2_CLUT_TBL,
+        &VDC5_CH0_GR3_CLUT_TBL,
+        NULL,
+        &VDC5_CH0_GR_OIR_CLUT_TBL
+    },
+    {   /* Channel 1 */
+        &VDC5_CH1_GR0_CLUT_TBL,
+        &VDC5_CH1_GR1_CLUT_TBL,
+        &VDC5_CH1_GR2_CLUT_TBL,
+        &VDC5_CH1_GR3_CLUT_TBL,
+        NULL,
+        &VDC5_CH1_GR_OIR_CLUT_TBL
+    }
+};
+
+/* VDC5 output controller register address list */
+const vdc5_regaddr_output_ctrl_t vdc5_regaddr_output_ctrl[VDC5_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        &VDC50.TCON_UPDATE,
+        &VDC50.TCON_TIM,
+        &VDC50.TCON_TIM_STVA1,
+        &VDC50.TCON_TIM_STVA2,
+        &VDC50.TCON_TIM_STVB1,
+        &VDC50.TCON_TIM_STVB2,
+        &VDC50.TCON_TIM_STH1,
+        &VDC50.TCON_TIM_STH2,
+        &VDC50.TCON_TIM_STB1,
+        &VDC50.TCON_TIM_STB2,
+        &VDC50.TCON_TIM_CPV1,
+        &VDC50.TCON_TIM_CPV2,
+        &VDC50.TCON_TIM_POLA1,
+        &VDC50.TCON_TIM_POLA2,
+        &VDC50.TCON_TIM_POLB1,
+        &VDC50.TCON_TIM_POLB2,
+        &VDC50.TCON_TIM_DE,
+        &VDC50.OUT_UPDATE,
+        &VDC50.OUT_SET,
+        &VDC50.OUT_BRIGHT1,
+        &VDC50.OUT_BRIGHT2,
+        &VDC50.OUT_CONTRAST,
+        &VDC50.OUT_PDTHA,
+        &VDC50.OUT_CLK_PHASE
+    },
+    {   /* Channel 1 */
+        &VDC51.TCON_UPDATE,
+        &VDC51.TCON_TIM,
+        &VDC51.TCON_TIM_STVA1,
+        &VDC51.TCON_TIM_STVA2,
+        &VDC51.TCON_TIM_STVB1,
+        &VDC51.TCON_TIM_STVB2,
+        &VDC51.TCON_TIM_STH1,
+        &VDC51.TCON_TIM_STH2,
+        &VDC51.TCON_TIM_STB1,
+        &VDC51.TCON_TIM_STB2,
+        &VDC51.TCON_TIM_CPV1,
+        &VDC51.TCON_TIM_CPV2,
+        &VDC51.TCON_TIM_POLA1,
+        &VDC51.TCON_TIM_POLA2,
+        &VDC51.TCON_TIM_POLB1,
+        &VDC51.TCON_TIM_POLB2,
+        &VDC51.TCON_TIM_DE,
+        &VDC51.OUT_UPDATE,
+        &VDC51.OUT_SET,
+        &VDC51.OUT_BRIGHT1,
+        &VDC51.OUT_BRIGHT2,
+        &VDC51.OUT_CONTRAST,
+        &VDC51.OUT_PDTHA,
+        &VDC51.OUT_CLK_PHASE
+    }
+};
+
+/* VDC5 gamma correction register address list */
+const vdc5_regaddr_gamma_t vdc5_regaddr_gamma[VDC5_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        &VDC50.GAM_SW,
+        &VDC50.GAM_G_UPDATE,
+        {
+            &VDC50.GAM_G_LUT1,
+            &VDC50.GAM_G_LUT2,
+            &VDC50.GAM_G_LUT3,
+            &VDC50.GAM_G_LUT4,
+            &VDC50.GAM_G_LUT5,
+            &VDC50.GAM_G_LUT6,
+            &VDC50.GAM_G_LUT7,
+            &VDC50.GAM_G_LUT8,
+            &VDC50.GAM_G_LUT9,
+            &VDC50.GAM_G_LUT10,
+            &VDC50.GAM_G_LUT11,
+            &VDC50.GAM_G_LUT12,
+            &VDC50.GAM_G_LUT13,
+            &VDC50.GAM_G_LUT14,
+            &VDC50.GAM_G_LUT15,
+            &VDC50.GAM_G_LUT16
+        },
+        {
+            &VDC50.GAM_G_AREA1,
+            &VDC50.GAM_G_AREA2,
+            &VDC50.GAM_G_AREA3,
+            &VDC50.GAM_G_AREA4,
+            &VDC50.GAM_G_AREA5,
+            &VDC50.GAM_G_AREA6,
+            &VDC50.GAM_G_AREA7,
+            &VDC50.GAM_G_AREA8
+        },
+        &VDC50.GAM_B_UPDATE,
+        {
+            &VDC50.GAM_B_LUT1,
+            &VDC50.GAM_B_LUT2,
+            &VDC50.GAM_B_LUT3,
+            &VDC50.GAM_B_LUT4,
+            &VDC50.GAM_B_LUT5,
+            &VDC50.GAM_B_LUT6,
+            &VDC50.GAM_B_LUT7,
+            &VDC50.GAM_B_LUT8,
+            &VDC50.GAM_B_LUT9,
+            &VDC50.GAM_B_LUT10,
+            &VDC50.GAM_B_LUT11,
+            &VDC50.GAM_B_LUT12,
+            &VDC50.GAM_B_LUT13,
+            &VDC50.GAM_B_LUT14,
+            &VDC50.GAM_B_LUT15,
+            &VDC50.GAM_B_LUT16
+        },
+        {
+            &VDC50.GAM_B_AREA1,
+            &VDC50.GAM_B_AREA2,
+            &VDC50.GAM_B_AREA3,
+            &VDC50.GAM_B_AREA4,
+            &VDC50.GAM_B_AREA5,
+            &VDC50.GAM_B_AREA6,
+            &VDC50.GAM_B_AREA7,
+            &VDC50.GAM_B_AREA8
+        },
+        &VDC50.GAM_R_UPDATE,
+        {
+            &VDC50.GAM_R_LUT1,
+            &VDC50.GAM_R_LUT2,
+            &VDC50.GAM_R_LUT3,
+            &VDC50.GAM_R_LUT4,
+            &VDC50.GAM_R_LUT5,
+            &VDC50.GAM_R_LUT6,
+            &VDC50.GAM_R_LUT7,
+            &VDC50.GAM_R_LUT8,
+            &VDC50.GAM_R_LUT9,
+            &VDC50.GAM_R_LUT10,
+            &VDC50.GAM_R_LUT11,
+            &VDC50.GAM_R_LUT12,
+            &VDC50.GAM_R_LUT13,
+            &VDC50.GAM_R_LUT14,
+            &VDC50.GAM_R_LUT15,
+            &VDC50.GAM_R_LUT16
+        },
+        {
+            &VDC50.GAM_R_AREA1,
+            &VDC50.GAM_R_AREA2,
+            &VDC50.GAM_R_AREA3,
+            &VDC50.GAM_R_AREA4,
+            &VDC50.GAM_R_AREA5,
+            &VDC50.GAM_R_AREA6,
+            &VDC50.GAM_R_AREA7,
+            &VDC50.GAM_R_AREA8
+        }
+    },
+    {   /* Channel 1 */
+        &VDC51.GAM_SW,
+        &VDC51.GAM_G_UPDATE,
+        {
+            &VDC51.GAM_G_LUT1,
+            &VDC51.GAM_G_LUT2,
+            &VDC51.GAM_G_LUT3,
+            &VDC51.GAM_G_LUT4,
+            &VDC51.GAM_G_LUT5,
+            &VDC51.GAM_G_LUT6,
+            &VDC51.GAM_G_LUT7,
+            &VDC51.GAM_G_LUT8,
+            &VDC51.GAM_G_LUT9,
+            &VDC51.GAM_G_LUT10,
+            &VDC51.GAM_G_LUT11,
+            &VDC51.GAM_G_LUT12,
+            &VDC51.GAM_G_LUT13,
+            &VDC51.GAM_G_LUT14,
+            &VDC51.GAM_G_LUT15,
+            &VDC51.GAM_G_LUT16
+        },
+        {
+            &VDC51.GAM_G_AREA1,
+            &VDC51.GAM_G_AREA2,
+            &VDC51.GAM_G_AREA3,
+            &VDC51.GAM_G_AREA4,
+            &VDC51.GAM_G_AREA5,
+            &VDC51.GAM_G_AREA6,
+            &VDC51.GAM_G_AREA7,
+            &VDC51.GAM_G_AREA8
+        },
+        &VDC51.GAM_B_UPDATE,
+        {
+            &VDC51.GAM_B_LUT1,
+            &VDC51.GAM_B_LUT2,
+            &VDC51.GAM_B_LUT3,
+            &VDC51.GAM_B_LUT4,
+            &VDC51.GAM_B_LUT5,
+            &VDC51.GAM_B_LUT6,
+            &VDC51.GAM_B_LUT7,
+            &VDC51.GAM_B_LUT8,
+            &VDC51.GAM_B_LUT9,
+            &VDC51.GAM_B_LUT10,
+            &VDC51.GAM_B_LUT11,
+            &VDC51.GAM_B_LUT12,
+            &VDC51.GAM_B_LUT13,
+            &VDC51.GAM_B_LUT14,
+            &VDC51.GAM_B_LUT15,
+            &VDC51.GAM_B_LUT16
+        },
+        {
+            &VDC51.GAM_B_AREA1,
+            &VDC51.GAM_B_AREA2,
+            &VDC51.GAM_B_AREA3,
+            &VDC51.GAM_B_AREA4,
+            &VDC51.GAM_B_AREA5,
+            &VDC51.GAM_B_AREA6,
+            &VDC51.GAM_B_AREA7,
+            &VDC51.GAM_B_AREA8
+        },
+        &VDC51.GAM_R_UPDATE,
+        {
+            &VDC51.GAM_R_LUT1,
+            &VDC51.GAM_R_LUT2,
+            &VDC51.GAM_R_LUT3,
+            &VDC51.GAM_R_LUT4,
+            &VDC51.GAM_R_LUT5,
+            &VDC51.GAM_R_LUT6,
+            &VDC51.GAM_R_LUT7,
+            &VDC51.GAM_R_LUT8,
+            &VDC51.GAM_R_LUT9,
+            &VDC51.GAM_R_LUT10,
+            &VDC51.GAM_R_LUT11,
+            &VDC51.GAM_R_LUT12,
+            &VDC51.GAM_R_LUT13,
+            &VDC51.GAM_R_LUT14,
+            &VDC51.GAM_R_LUT15,
+            &VDC51.GAM_R_LUT16
+        },
+        {
+            &VDC51.GAM_R_AREA1,
+            &VDC51.GAM_R_AREA2,
+            &VDC51.GAM_R_AREA3,
+            &VDC51.GAM_R_AREA4,
+            &VDC51.GAM_R_AREA5,
+            &VDC51.GAM_R_AREA6,
+            &VDC51.GAM_R_AREA7,
+            &VDC51.GAM_R_AREA8
+        }
+    }
+};
+
+/* VDC5 system controller register address list */
+const vdc5_regaddr_system_ctrl_t vdc5_regaddr_system_ctrl[VDC5_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        &VDC50.SYSCNT_INT1,
+        &VDC50.SYSCNT_INT2,
+        &VDC50.SYSCNT_INT3,
+        &VDC50.SYSCNT_INT4,
+        &VDC50.SYSCNT_INT5,
+        &VDC50.SYSCNT_INT6,
+        &VDC50.SYSCNT_PANEL_CLK,
+        &VDC50.SYSCNT_CLUT
+    },
+    {   /* Channel 1 */
+        &VDC51.SYSCNT_INT1,
+        &VDC51.SYSCNT_INT2,
+        &VDC51.SYSCNT_INT3,
+        &VDC51.SYSCNT_INT4,
+        &VDC51.SYSCNT_INT5,
+        &VDC51.SYSCNT_INT6,
+        &VDC51.SYSCNT_PANEL_CLK,
+        &VDC51.SYSCNT_CLUT
+    }
+};
+
+/* LVDS register address list */
+const vdc5_regaddr_lvds_t vdc5_regaddr_lvds = {
+    &LVDS.LVDS_UPDATE,
+    &LVDS.LVDSFCL,
+    &LVDS.LCLKSELR,
+    &LVDS.LPLLSETR,
+    &LVDS.LPHYACC
+};
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdc5/src/r_vdc5_shared_param.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1030 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_shared_param.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver shared parameter processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <string.h>
+
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+#include    "r_vdc5_shared_param.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Two to the power of eleven */
+#define     TWO_POWER_ELEVEN                (2048)
+
+#define     VDC5_SPARA_DIV_2                (2)
+#define     VDC5_SPARA_DIV_256              (256)
+
+/* Color Conversion Value */
+#define     VDC5_SPARA_COLOR_CONV_RANGE     (255)
+#define     VDC5_SPARA_COLOR_CONV_OFFSET    (128)
+
+/* Color mask data */
+#define     VDC5_SPARA_COLOR_8BIT_MASK      (0x000000FFu)
+
+/* shift value */
+#define     VDC5_SPARA_SHIFT_16             (16u)
+#define     VDC5_SPARA_SHIFT_8              (8u)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef struct {
+    vdc5_panel_clksel_t     panel_icksel;   /*!< Panel clock select */
+    vdc5_onoff_t            lvds_ref;       /*!< Reference to the LVDS PLL clock */
+    vdc5_color_space_t      color_sp_in;    /*!< Color space of the input video image signal */
+    vdc5_input_sel_t        inp_sel;        /*!< Input select */
+    vdc5_res_vs_in_sel_t    res_vs_in_sel;  /*!< Horizontal/vertical sync signal output and
+                                                 full-screen enable signal select */
+    vdc5_onoff_t            cascade;        /*!< Cascaded connection */
+    vdc5_onoff_t            und_sel;        /*!< Selection of lower-layer plane in scaler */
+    uint32_t                bg_color_rgb;   /*!< Background color in 24-bit RGB color format */
+    uint32_t                bg_color_crycb; /*!< Background color in 24-bit CrYCb format */
+} vdc5_shared_param_common_t;
+
+typedef struct {
+    vdc5_wr_md_t            res_ds_wr_md;   /*!< Frame buffer writing mode for image processing */
+    vdc5_res_inter_t        res_inter;      /*!< Field operating mode select */
+    vdc5_color_space_t      color_sp_fb_wr; /*!< Color space of the frame buffer writing format */
+    void                  * btm_base;       /*!< Frame buffer base address for bottom */
+    vdc5_width_read_fb_t    width_wr_fb;    /*!< Size of the image output by scaling-down control block */
+} vdc5_shared_param_scaling_t;
+
+typedef struct {
+    vdc5_gr_ln_off_dir_t    gr_ln_off_dir;      /*!< Line offset address direction of the frame buffer */
+    vdc5_gr_flm_sel_t       gr_flm_sel;         /*!< Frame buffer address setting signal */
+    vdc5_gr_format_t        gr_format;          /*!< Format of the frame buffer read signal */
+    vdc5_color_space_t      color_sp_fb_rd;     /*!< Color space of the frame buffer reading format */
+    vdc5_onoff_t            adj_sel;            /*!< Folding handling (on/off) */
+    vdc5_period_rect_t      gr_grc;             /*!< Graphics display area */
+    vdc5_width_read_fb_t    width_read_fb;      /*!< Size of the frame buffer to be read */
+} vdc5_shared_param_graphics_t;
+
+typedef struct {
+    vdc5_resource_state_t   rsrc_panel_clock;
+    vdc5_resource_state_t   rsrc_video_input;
+    vdc5_resource_state_t   rsrc_vsync_signal;
+    vdc5_resource_state_t   rsrc_lcd_panel;
+} vdc5_shared_param_resource_t;
+
+/*! Read/write process state */
+typedef enum {
+    VDC5_RW_PROC_STATE_DISABLE   = 0,
+    VDC5_RW_PROC_STATE_ENABLE    = 1
+} vdc5_rw_proc_state_t;
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdc5_resource_state_t * GetResourceStatePointer(const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type);
+static uint32_t SumProduct(
+    const int32_t   red,
+    const int32_t   green,
+    const int32_t   blue,
+    int32_t         coeff_r,
+    int32_t         coeff_g,
+    int32_t         coeff_b,
+    const int32_t   offset);
+
+static vdc5_shared_param_common_t   param_common[VDC5_CHANNEL_NUM];
+static vdc5_shared_param_scaling_t  param_scaling[VDC5_CHANNEL_NUM][VDC5_SC_TYPE_NUM];
+static vdc5_shared_param_graphics_t param_graphics[VDC5_CHANNEL_NUM][VDC5_GR_TYPE_NUM];
+/*! A channel in VDC5 whose data is to be output through the LVDS */
+static vdc5_channel_t               lvds_vdc_sel_ch;
+
+static vdc5_resource_state_t        layer_resource[VDC5_CHANNEL_NUM][VDC5_LAYER_ID_NUM];
+static vdc5_rw_proc_state_t         rw_proc_state[VDC5_CHANNEL_NUM][VDC5_LAYER_ID_NUM];
+
+static vdc5_onoff_t video_input_flag[VDC5_CHANNEL_NUM] = {VDC5_OFF, VDC5_OFF};
+
+
+/**************************************************************************//**
+ * @brief       Initializes variables of the VDC5 driver
+ * @param[in]   ch                      : Channel
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmInit (const vdc5_channel_t ch)
+{
+    int32_t                         layer_id_num;
+    vdc5_shared_param_common_t    * shared_param_common;
+    vdc5_shared_param_scaling_t   * shared_param_scaling;
+    vdc5_scaling_type_t             scaling_id;
+    vdc5_shared_param_graphics_t  * shared_param_graphics;
+    vdc5_graphics_type_t            graphics_id;
+
+    for (layer_id_num = 0; layer_id_num < VDC5_LAYER_ID_NUM; layer_id_num++) {
+        layer_resource[ch][layer_id_num] = VDC5_RESOURCE_ST_INVALID;
+        rw_proc_state[ch][layer_id_num]  = VDC5_RW_PROC_STATE_DISABLE;
+    }
+
+    shared_param_common = &param_common[ch];
+
+    shared_param_common->panel_icksel   = VDC5_PANEL_ICKSEL_PERI;   /* Panel clock select */
+    shared_param_common->lvds_ref       = VDC5_OFF;                 /* Reference to the LVDS PLL clock */
+    shared_param_common->res_vs_in_sel  = VDC5_RES_VS_IN_SEL_SC0;   /* Horizontal/vertical sync signal output and
+                                                                       full-screen enable signal select */
+    shared_param_common->cascade        = VDC5_ON;                  /* Cascaded connection */
+    shared_param_common->und_sel        = VDC5_OFF;                 /* Selection of lower-layer plane in scaler */
+    shared_param_common->bg_color_rgb   = (uint32_t)0u;             /* Background color in 24-bit RGB color format */
+    shared_param_common->bg_color_crycb = (uint32_t)0u;             /* Background color in 24-bit CrYCb format */
+
+    if (video_input_flag[ch] == VDC5_OFF) {
+        shared_param_common->color_sp_in    = VDC5_COLOR_SPACE_GBR; /* Color space of the input video image signal */
+        shared_param_common->inp_sel        = VDC5_INPUT_SEL_VDEC;  /* Input select */
+    }
+
+    for (scaling_id = VDC5_SC_TYPE_SC0; scaling_id < VDC5_SC_TYPE_NUM; scaling_id++) {
+        shared_param_scaling = &param_scaling[ch][scaling_id];
+
+        /* Frame buffer writing mode for image processing */
+        shared_param_scaling->res_ds_wr_md      = VDC5_WR_MD_NORMAL;
+        shared_param_scaling->res_inter         = VDC5_RES_INTER_PROGRESSIVE;   /* Field operating mode select */
+        /* Color space of the frame buffer writing format */
+        shared_param_scaling->color_sp_fb_wr    = VDC5_COLOR_SPACE_GBR;
+        /* Frame buffer base address for bottom */
+        shared_param_scaling->btm_base          = NULL;
+        /* Size of the image output by scaling-down control block */
+        shared_param_scaling->width_wr_fb.in_vw = (uint16_t)0;
+        shared_param_scaling->width_wr_fb.in_hw = (uint16_t)0;
+    }
+
+    for (graphics_id = VDC5_GR_TYPE_GR0; graphics_id < VDC5_GR_TYPE_NUM; graphics_id++) {
+        shared_param_graphics = &param_graphics[ch][graphics_id];
+
+        /* Line offset address direction of the frame buffer */
+        shared_param_graphics->gr_ln_off_dir = VDC5_GR_LN_OFF_DIR_INC;
+        /* Frame buffer address setting signal */
+        shared_param_graphics->gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM;
+        /* Format of the frame buffer read signal */
+        shared_param_graphics->gr_format = VDC5_GR_FORMAT_RGB565;
+        /* Color space of the frame buffer reading format */
+        shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_GBR;
+        /* Folding handling (on/off) */
+        shared_param_graphics->adj_sel = VDC5_OFF;
+        /* Graphics display area */
+        shared_param_graphics->gr_grc.vs = (uint16_t)0;
+        shared_param_graphics->gr_grc.vw = (uint16_t)0;
+        shared_param_graphics->gr_grc.hs = (uint16_t)0;
+        shared_param_graphics->gr_grc.hw = (uint16_t)0;
+        /* Size of the frame buffer to be read */
+        shared_param_graphics->width_read_fb.in_vw = (uint16_t)0;
+        shared_param_graphics->width_read_fb.in_hw = (uint16_t)0;
+    }
+    /* A channel in VDC5 whose data is to be output through the LVDS */
+    lvds_vdc_sel_ch = VDC5_CHANNEL_NUM;     /* Initialized with invalid channel */
+}   /* End of function VDC5_ShrdPrmInit() */
+
+/**************************************************************************//**
+ * @brief       Sets the initialization parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Initialization parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetInitParam (const vdc5_channel_t ch, const vdc5_init_t * const param)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+
+    shared_param_common = &param_common[ch];
+
+    /* Panel clock select */
+    shared_param_common->panel_icksel = param->panel_icksel;
+    /* Reference to the LVDS PLL clock */
+    if ((param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS) || (param->panel_icksel == VDC5_PANEL_ICKSEL_LVDS_DIV7)) {
+        shared_param_common->lvds_ref = VDC5_ON;
+    }
+    if (param->lvds != NULL) {
+        /* A channel in VDC5 whose data is to be output through the LVDS */
+        lvds_vdc_sel_ch = param->lvds->lvds_vdc_sel;
+    }
+}   /* End of function VDC5_ShrdPrmSetInitParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the termination parameter
+ * @param[in]   ch                      : Channel
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetTerminate (const vdc5_channel_t ch)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+
+    shared_param_common = &param_common[ch];
+
+    /* Reference to the LVDS PLL clock */
+    shared_param_common->lvds_ref = VDC5_OFF;
+}   /* End of function VDC5_ShrdPrmSetTerminate() */
+
+/**************************************************************************//**
+ * @brief       Sets the video input setup parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Video input setup parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetInputParam (const vdc5_channel_t ch, const vdc5_input_t * const param)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+
+    video_input_flag[ch] = VDC5_ON;
+
+    shared_param_common = &param_common[ch];
+
+    /* Color space */
+    if (param->inp_sel == VDC5_INPUT_SEL_VDEC) {
+        /* Video decoder output signals */
+        shared_param_common->color_sp_in = VDC5_COLOR_SPACE_YCBCR;
+    } else {
+        /* Signals supplied via the external input pins */
+        if ((param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB888) ||
+                (param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB666) ||
+                (param->ext_sig->inp_format == VDC5_EXTIN_FORMAT_RGB565)) {
+            shared_param_common->color_sp_in = VDC5_COLOR_SPACE_GBR;
+        } else {
+            shared_param_common->color_sp_in = VDC5_COLOR_SPACE_YCBCR;
+        }
+    }
+    /* Input select */
+    shared_param_common->inp_sel = param->inp_sel;
+}   /* End of function VDC5_ShrdPrmSetInputParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the sync control parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Sync control parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetSyncParam (const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+
+    shared_param_common = &param_common[ch];
+
+    shared_param_common->res_vs_in_sel = param->res_vs_in_sel;
+}   /* End of function VDC5_ShrdPrmSetSyncParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the display output configuration parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Display output configuration parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetOutputParam (const vdc5_channel_t ch, const vdc5_output_t * const param)
+{
+    vdc5_shared_param_common_t    * shared_param_common;
+    int32_t                         red;
+    int32_t                         green;
+    int32_t                         blue;
+    uint32_t                        y_val;
+    uint32_t                        cb_val;
+    uint32_t                        cr_val;
+
+    shared_param_common = &param_common[ch];
+
+    /* Background color in 24-bit RGB color format */
+    shared_param_common->bg_color_rgb = param->bg_color;
+
+    red     = (int32_t)((param->bg_color >> VDC5_SPARA_SHIFT_16) & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+    green   = (int32_t)((param->bg_color >> VDC5_SPARA_SHIFT_8)  & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+    blue    = (int32_t)( param->bg_color                         & (uint32_t)VDC5_SPARA_COLOR_8BIT_MASK);
+    /* Y */
+    y_val = SumProduct(
+                red,
+                green,
+                blue,
+                (int32_t)VDC5_COLORCONV_Y_R,
+                (int32_t)VDC5_COLORCONV_Y_G,
+                (int32_t)VDC5_COLORCONV_Y_B,
+                0);
+    /* Cb */
+    cb_val = SumProduct(
+                 red,
+                 green,
+                 blue,
+                 (int32_t)VDC5_COLORCONV_CB_R,
+                 (int32_t)VDC5_COLORCONV_CB_G,
+                 (int32_t)VDC5_COLORCONV_CB_B,
+                 (int32_t)VDC5_SPARA_COLOR_CONV_OFFSET);
+    /* Cr */
+    cr_val = SumProduct(
+                 red,
+                 green,
+                 blue,
+                 (int32_t)VDC5_COLORCONV_CR_R,
+                 (int32_t)VDC5_COLORCONV_CR_G,
+                 (int32_t)VDC5_COLORCONV_CR_B,
+                 (int32_t)VDC5_SPARA_COLOR_CONV_OFFSET);
+    /* Background color in 24-bit CrYCb format */
+    shared_param_common->bg_color_crycb = (uint32_t)((cr_val << VDC5_SPARA_SHIFT_16) | (y_val << VDC5_SPARA_SHIFT_8) | cb_val);
+}   /* End of function VDC5_ShrdPrmSetOutputParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data write control parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @param[in]   param                   : Data write control parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetWriteParam (
+    const vdc5_channel_t        ch,
+    const vdc5_scaling_type_t   scaling_id,
+    const vdc5_write_t  * const param)
+{
+    vdc5_shared_param_scaling_t   * shared_param_scaling;
+
+    shared_param_scaling = &param_scaling[ch][scaling_id];
+
+    if (scaling_id == VDC5_SC_TYPE_OIR) {
+        /* Frame buffer writing mode for image processing */
+        shared_param_scaling->res_ds_wr_md = VDC5_WR_MD_NORMAL;
+        /* Field operating mode select */
+        shared_param_scaling->res_inter = VDC5_RES_INTER_PROGRESSIVE;
+    } else {
+        /* Frame buffer writing mode for image processing */
+        shared_param_scaling->res_ds_wr_md = param->scalingdown_rot.res_ds_wr_md;
+        /* Field operating mode select */
+        shared_param_scaling->res_inter = param->res_inter;
+    }
+
+    /* Color space of the frame buffer */
+    if ((param->res_md == VDC5_RES_MD_YCBCR422) || (param->res_md == VDC5_RES_MD_YCBCR444)) {
+        shared_param_scaling->color_sp_fb_wr = VDC5_COLOR_SPACE_YCBCR;
+    } else {
+        shared_param_scaling->color_sp_fb_wr = VDC5_COLOR_SPACE_GBR;
+    }
+
+    /* Frame buffer base address for bottom */
+    shared_param_scaling->btm_base = param->btm_base;
+    /* Size of the image output by scaling-down control block */
+    if (scaling_id == VDC5_SC_TYPE_OIR) {
+        /* OIR */
+        shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res.vw;
+        shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res.hw;
+    } else {
+        shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res_out_vw;
+        shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res_out_hw;
+    }
+}   /* End of function VDC5_ShrdPrmSetWriteParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data write change parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @param[in]   param                   : Data write change parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetChgWriteParam (
+    const vdc5_channel_t            ch,
+    const vdc5_scaling_type_t       scaling_id,
+    const vdc5_write_chg_t  * const param)
+{
+    vdc5_shared_param_scaling_t   * shared_param_scaling;
+
+    shared_param_scaling = &param_scaling[ch][scaling_id];
+
+    if (scaling_id != VDC5_SC_TYPE_OIR) {
+        /* Frame buffer writing mode for image processing */
+        shared_param_scaling->res_ds_wr_md = param->scalingdown_rot.res_ds_wr_md;
+    }
+
+    /* Size of the image output by scaling-down control block */
+    if (scaling_id == VDC5_SC_TYPE_OIR) {
+        /* OIR */
+        shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res.vw;
+        shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res.hw;
+    } else {
+        shared_param_scaling->width_wr_fb.in_vw = param->scalingdown_rot.res_out_vw;
+        shared_param_scaling->width_wr_fb.in_hw = param->scalingdown_rot.res_out_hw;
+    }
+}   /* End of function VDC5_ShrdPrmSetChgWriteParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data read control parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read control parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetReadParam (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param)
+{
+    vdc5_shared_param_graphics_t  * shared_param_graphics;
+
+    shared_param_graphics = &param_graphics[ch][graphics_id];
+
+    /* Line offset address direction of the frame buffer */
+    shared_param_graphics->gr_ln_off_dir = param->gr_ln_off_dir;
+
+    /* Frame buffer address setting signal */
+    shared_param_graphics->gr_flm_sel = param->gr_flm_sel;
+
+    /* Format of the frame buffer read signal */
+    shared_param_graphics->gr_format = param->gr_format;
+
+    /* Color space of the frame buffer */
+    if ((param->gr_format == VDC5_GR_FORMAT_YCBCR422) || (param->gr_format == VDC5_GR_FORMAT_YCBCR444)) {
+        shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_YCBCR;
+    } else {
+        shared_param_graphics->color_sp_fb_rd = VDC5_COLOR_SPACE_GBR;
+    }
+
+    /* Folding handling (on/off) */
+    shared_param_graphics->adj_sel = param->adj_sel;
+
+    /* Graphics display area */
+    shared_param_graphics->gr_grc = param->gr_grc;
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL) {
+        shared_param_graphics->width_read_fb.in_vw = param->width_read_fb->in_vw;
+        shared_param_graphics->width_read_fb.in_hw = param->width_read_fb->in_hw;
+    } else {
+        /* If not specified, ... */
+        if ((param->gr_flm_sel == VDC5_GR_FLM_SEL_FLM_NUM) || (graphics_id == VDC5_GR_TYPE_OIR)) {
+            /* The size of the frame buffer to be read is assumed that it is the same as
+               the width of the graphics display area. */
+            shared_param_graphics->width_read_fb.in_vw = param->gr_grc.vw;
+            shared_param_graphics->width_read_fb.in_hw = param->gr_grc.hw;
+        } else {
+            /* The size of the image output by scaling-down control block is used for the size of the frame buffer
+               to be read when a frame buffer address setting signal links to the video image signals. */
+            if (graphics_id == VDC5_GR_TYPE_GR0) {
+                /* Scaler 0 */
+                shared_param_graphics->width_read_fb = param_scaling[ch][VDC5_SC_TYPE_SC0].width_wr_fb;
+            } else { /* Scaler 1 */
+                shared_param_graphics->width_read_fb = param_scaling[ch][VDC5_SC_TYPE_SC1].width_wr_fb;
+            }
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetReadParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the data read change parameter
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @param[in]   param                   : Data read change parameter
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetChgReadParam (
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_read_chg_t   * const param)
+{
+    vdc5_shared_param_graphics_t  * shared_param_graphics;
+
+    shared_param_graphics = &param_graphics[ch][graphics_id];
+
+    /* Graphics display area */
+    if (param->gr_grc != NULL) {
+        shared_param_graphics->gr_grc = *(param->gr_grc);
+    }
+
+    /* Size of the frame buffer to be read */
+    if (param->width_read_fb != NULL) {
+        shared_param_graphics->width_read_fb.in_vw = param->width_read_fb->in_vw;
+        shared_param_graphics->width_read_fb.in_hw = param->width_read_fb->in_hw;
+    }
+}   /* End of function VDC5_ShrdPrmSetChgReadParam() */
+
+/**************************************************************************//**
+ * @brief       Sets the cascaded connection
+ * @param[in]   ch                      : Channel
+ * @param[in]   cascade                 : Cascaded connection
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetCascade (const vdc5_channel_t ch, const vdc5_onoff_t cascade)
+{
+    param_common[ch].cascade = cascade;
+}   /* End of function VDC5_ShrdPrmSetCascade() */
+
+/**************************************************************************//**
+ * @brief       Sets the selection of lower-layer plane in scaler
+ * @param[in]   ch                      : Channel
+ * @param[in]   und_sel                 : Selection of lower-layer plane in scaler
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetUndSel (const vdc5_channel_t ch, const vdc5_onoff_t und_sel)
+{
+    param_common[ch].und_sel = und_sel;
+}   /* End of function VDC5_ShrdPrmSetUndSel() */
+
+/**************************************************************************//**
+ * @brief       Gets the panel clock select
+ * @param[in]   ch                      : Channel
+ * @retval      Panel clock select
+ *****************************************************************************/
+vdc5_panel_clksel_t VDC5_ShrdPrmGetPanelClkSel (const vdc5_channel_t ch)
+{
+    return param_common[ch].panel_icksel;
+}   /* End of function VDC5_ShrdPrmGetPanelClkSel() */
+
+/**************************************************************************//**
+ * @brief       Gets the reference to the LVDS PLL clock
+ * @param[in]   void
+ * @retval      Reference to the LVDS PLL clock
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetLvdsClkRef (void)
+{
+    vdc5_onoff_t onoff;
+
+    if ((param_common[VDC5_CHANNEL_0].lvds_ref == VDC5_OFF) && (param_common[VDC5_CHANNEL_1].lvds_ref == VDC5_OFF)) {
+        onoff = VDC5_OFF;
+    } else {
+        onoff = VDC5_ON;
+    }
+    return onoff;
+}   /* End of function VDC5_ShrdPrmGetLvdsClkRef() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the input video image signal
+ * @param[in]   ch                      : Channel
+ * @retval      Color space of the input video image signal
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpace (const vdc5_channel_t ch)
+{
+    return param_common[ch].color_sp_in;
+}   /* End of function VDC5_ShrdPrmGetColorSpace() */
+
+/**************************************************************************//**
+ * @brief       Gets the input select
+ * @param[in]   ch                      : Channel
+ * @retval      Input select
+ *****************************************************************************/
+vdc5_input_sel_t VDC5_ShrdPrmGetInputSelect (const vdc5_channel_t ch)
+{
+    return param_common[ch].inp_sel;
+}   /* End of function VDC5_ShrdPrmGetInputSelect() */
+
+/**************************************************************************//**
+ * @brief       Gets the sync signal output and full-screen enable signal select
+ * @param[in]   ch                      : Channel
+ * @retval      Horizontal/vertical sync signal output and full-screen enable signal select
+ *              - VDC5_RES_VS_IN_SEL_SC0: Sync signal output and full-screen enable signal from scaler 0
+ *              - VDC5_RES_VS_IN_SEL_SC1: Sync signal output and full-screen enable signal from scaler 1
+ *****************************************************************************/
+vdc5_res_vs_in_sel_t VDC5_ShrdPrmGetVsInSel (const vdc5_channel_t ch)
+{
+    return param_common[ch].res_vs_in_sel;
+}   /* End of function VDC5_ShrdPrmGetVsInSel() */
+
+/**************************************************************************//**
+ * @brief       Gets the cascaded connection
+ * @param[in]   ch                      : Channel
+ * @retval      Cascaded connection (on/off)
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetCascade (const vdc5_channel_t ch)
+{
+    return param_common[ch].cascade;
+}   /* End of function VDC5_ShrdPrmGetCascade() */
+
+/**************************************************************************//**
+ * @brief       Gets the selection of lower-layer plane in scaler
+ * @param[in]   ch                      : Channel
+ * @retval      Selection of lower-layer plane in scaler
+ *              - VDC5_OFF: Selects graphics 0 as lower-layer graphics and graphics 1 as current graphics
+ *              - VDC5_ON: Selects graphics 1 as lower-layer graphics and graphics 0 as current graphics
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetUndSel (const vdc5_channel_t ch)
+{
+    return param_common[ch].und_sel;
+}   /* End of function VDC5_ShrdPrmGetUndSel() */
+
+/**************************************************************************//**
+ * @brief       Get the background color
+ * @param[in]   ch                      : Channel
+ * @param[in]   color_space             : Color space
+ * @retval      Background color in 24-bit RGB color format or CrYCb format
+ *****************************************************************************/
+uint32_t VDC5_ShrdPrmGetBgColor (const vdc5_channel_t ch, const vdc5_color_space_t color_space)
+{
+    return (color_space == VDC5_COLOR_SPACE_GBR) ? param_common[ch].bg_color_rgb : param_common[ch].bg_color_crycb;
+}   /* End of function VDC5_ShrdPrmGetBgColor() */
+
+/**************************************************************************//**
+ * @brief       Get the frame buffer writing mode for image processing
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @retval      Frame buffer writing mode for image processing
+ *****************************************************************************/
+vdc5_wr_md_t VDC5_ShrdPrmGetWritingMode (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+    return param_scaling[ch][scaling_id].res_ds_wr_md;
+}   /* End of function VDC5_ShrdPrmGetWritingMode() */
+
+/**************************************************************************//**
+ * @brief       Gets the field operating mode select
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @retval      Field operating mode select
+ *****************************************************************************/
+vdc5_res_inter_t VDC5_ShrdPrmGetInterlace (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+    return param_scaling[ch][scaling_id].res_inter;
+}   /* End of function VDC5_ShrdPrmGetInterlace() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the frame buffer writing format
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @retval      Color space of the frame buffer writing format
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbWr (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+    return param_scaling[ch][scaling_id].color_sp_fb_wr;
+}   /* End of function VDC5_ShrdPrmGetColorSpaceFbWr() */
+
+/**************************************************************************//**
+ * @brief       Gets the frame buffer base address for bottom
+ * @param[in]   ch                      : Channel
+ * @param[in]   scaling_id              : Scaling type ID
+ * @retval      Frame buffer base address for bottom
+ *****************************************************************************/
+void * VDC5_ShrdPrmGetFrBuffBtm (const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id)
+{
+    return param_scaling[ch][scaling_id].btm_base;
+}   /* End of function VDC5_ShrdPrmGetFrBuffBtm() */
+
+/**************************************************************************//**
+ * @brief       Gets the line offset address direction of the frame buffer
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Line offset address direction of the frame buffer
+ *****************************************************************************/
+vdc5_gr_ln_off_dir_t VDC5_ShrdPrmGetLineOfsAddrDir (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[ch][graphics_id].gr_ln_off_dir;
+}   /* End of function VDC5_ShrdPrmGetLineOfsAddrDir() */
+
+/**************************************************************************//**
+ * @brief       Gets the frame buffer address setting signal
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Frame buffer address setting signal
+ *****************************************************************************/
+vdc5_gr_flm_sel_t VDC5_ShrdPrmGetSelFbAddrSig (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[ch][graphics_id].gr_flm_sel;
+}   /* End of function VDC5_ShrdPrmGetSelFbAddrSig() */
+
+/**************************************************************************//**
+ * @brief       Gets the format of the frame buffer read signal
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Format of the frame buffer read signal
+ *****************************************************************************/
+vdc5_gr_format_t VDC5_ShrdPrmGetGraphicsFormat (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[ch][graphics_id].gr_format;
+}   /* End of function VDC5_ShrdPrmGetGraphicsFormat() */
+
+/**************************************************************************//**
+ * @brief       Gets the color space of the frame buffer reading format
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Color space of the frame buffer reading format
+ *****************************************************************************/
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbRd (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[ch][graphics_id].color_sp_fb_rd;
+}   /* End of function VDC5_ShrdPrmGetColorSpaceFbRd() */
+
+/**************************************************************************//**
+ * @brief       Gets the folding handling
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Folding handling (on/off)
+ *****************************************************************************/
+vdc5_onoff_t VDC5_ShrdPrmGetMeasureFolding (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return param_graphics[ch][graphics_id].adj_sel;
+}   /* End of function VDC5_ShrdPrmGetMeasureFolding() */
+
+/**************************************************************************//**
+ * @brief       Gets the graphics display area
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Graphics display area
+ *****************************************************************************/
+vdc5_period_rect_t * VDC5_ShrdPrmGetDisplayArea (const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id)
+{
+    return &param_graphics[ch][graphics_id].gr_grc;
+}   /* End of function VDC5_ShrdPrmGetDisplayArea() */
+
+/**************************************************************************//**
+ * @brief       Gets the size of the frame buffer to be read
+ * @param[in]   ch                      : Channel
+ * @param[in]   graphics_id             : Graphics type ID
+ * @retval      Size of the frame buffer to be read
+ *****************************************************************************/
+vdc5_width_read_fb_t * VDC5_ShrdPrmGetFrBuffWidth_Rd (
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id)
+{
+    return &param_graphics[ch][graphics_id].width_read_fb;
+}   /* End of function VDC5_ShrdPrmGetFrBuffWidth_Rd() */
+
+/**************************************************************************//**
+ * @brief       Gets the VDC5 channel whose data is to be output through the LVDS
+ * @param[in]   void
+ * @retval      A channel in VDC5 whose data is to be output through the LVDS
+ *****************************************************************************/
+vdc5_channel_t VDC5_ShrdPrmGetLvdsCh (void)
+{
+    /* This value is valid only when LVDS PLL clock resource (VDC5_RESOURCE_LVDS_CLK) is valid. */
+    return lvds_vdc_sel_ch;
+}   /* End of function VDC5_ShrdPrmGetLvdsCh() */
+
+/**************************************************************************//**
+ * @brief       Updates the resource state
+ * @param[in]   ch                      : Channel
+ * @param[in]   rsrc_type               : Resource type
+ * @param[in]   rsrc_state              : Resource state
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetResource (
+    const vdc5_channel_t        ch,
+    const vdc5_resource_type_t  rsrc_type,
+    const vdc5_resource_state_t rsrc_state)
+{
+    vdc5_resource_state_t * resource_state;
+
+    resource_state = GetResourceStatePointer(ch, rsrc_type);
+    if (resource_state != NULL) {
+        *resource_state = rsrc_state;
+    }
+}   /* End of function VDC5_ShrdPrmSetResource() */
+
+/**************************************************************************//**
+ * @brief       Updates the layer resource state
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @param[in]   rsrc_state              : Resource state
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetLayerResource (
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_resource_state_t rsrc_state)
+{
+    uint32_t layer_id_num;
+
+    if (layer_id != VDC5_LAYER_ID_ALL) {
+        layer_resource[ch][layer_id] = rsrc_state;
+    } else {
+        for (layer_id_num = 0; layer_id_num < (uint32_t)VDC5_LAYER_ID_NUM; layer_id_num++) {
+            if (rw_proc_state[ch][layer_id_num] == VDC5_RW_PROC_STATE_DISABLE) {
+                layer_resource[ch][layer_id_num] = rsrc_state;
+            }
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetLayerResource() */
+
+/**************************************************************************//**
+ * @brief       Gets the resource state
+ * @param[in]   ch                      : Channel
+ * @param[in]   rsrc_type               : Resource type
+ * @retval      Resource state
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetResource (const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type)
+{
+    vdc5_resource_state_t * resource_state;
+    vdc5_resource_state_t   rsrc_state;
+
+    rsrc_state = VDC5_RESOURCE_ST_INVALID;
+
+    resource_state = GetResourceStatePointer(ch, rsrc_type);
+    if (resource_state != NULL) {
+        rsrc_state = *resource_state;
+    }
+    return rsrc_state;
+}   /* End of function VDC5_ShrdPrmGetResource() */
+
+/**************************************************************************//**
+ * @brief       Gets the layer resource state
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Layer resource state
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetLayerResource (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    return layer_resource[ch][layer_id];
+}   /* End of function VDC5_ShrdPrmGetLayerResource() */
+
+/**************************************************************************//**
+ * @brief       Makes the data write/read processing enabled
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetRwProcEnable (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    if (layer_id != VDC5_LAYER_ID_ALL) {
+        if (layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) {
+            rw_proc_state[ch][layer_id] = VDC5_RW_PROC_STATE_ENABLE;
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetRwProcEnable() */
+
+/**************************************************************************//**
+ * @brief       Makes the data write/read processing disabled
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      None
+ *****************************************************************************/
+void VDC5_ShrdPrmSetRwProcDisable (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    if (layer_id != VDC5_LAYER_ID_ALL) {
+        if (layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) {
+            rw_proc_state[ch][layer_id] = VDC5_RW_PROC_STATE_DISABLE;
+        }
+    }
+}   /* End of function VDC5_ShrdPrmSetRwProcDisable() */
+
+/**************************************************************************//**
+ * @brief       Gets the state whether the specified layer is ready or not
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Resource state
+ *              - VDC5_RESOURCE_ST_VALID: The layer resource state of the specified layer is valid and
+ *                the data write/read processing in the layer is disabled.
+ *              - VDC5_RESOURCE_ST_INVALID: The specified layer is not ready.
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcReady (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_resource_state_t state;
+
+    if ((layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) &&
+            (rw_proc_state[ch][layer_id] == VDC5_RW_PROC_STATE_DISABLE)) {
+        state = VDC5_RESOURCE_ST_VALID;
+    } else {
+        state = VDC5_RESOURCE_ST_INVALID;
+    }
+    return state;
+}   /* End of function VDC5_ShrdPrmGetRwProcReady() */
+
+/**************************************************************************//**
+ * @brief       Gets the state whether the specified layer is already run or not
+ * @param[in]   ch                      : Channel
+ * @param[in]   layer_id                : Layer ID
+ * @retval      Resource state
+ *              - VDC5_RESOURCE_ST_VALID: The layer resource state of the specified layer is valid and
+ *                the data write/read processing in the layer is enabled.
+ *              - VDC5_RESOURCE_ST_INVALID: The specified layer is not enabled.
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcEnabled (const vdc5_channel_t ch, const vdc5_layer_id_t layer_id)
+{
+    vdc5_resource_state_t state;
+
+    if ((layer_resource[ch][layer_id] != VDC5_RESOURCE_ST_INVALID) &&
+            (rw_proc_state[ch][layer_id] != VDC5_RW_PROC_STATE_DISABLE)) {
+        state = VDC5_RESOURCE_ST_VALID;
+    } else {
+        state = VDC5_RESOURCE_ST_INVALID;
+    }
+    return state;
+}   /* End of function VDC5_ShrdPrmGetRwProcEnabled() */
+
+/**************************************************************************//**
+ * @brief       Gets the state whether the OIR is already run or not
+ * @param[in]   ch                      : Channel
+ * @retval      Resource state
+ *              - VDC5_RESOURCE_ST_VALID: The layer resource state of the OIR is valid and
+ *                the data write/read processing in the OIR is enabled.
+ *              - VDC5_RESOURCE_ST_INVALID: The OIR is not enabled.
+ *****************************************************************************/
+vdc5_resource_state_t VDC5_ShrdPrmGetOirRwProcEnabled (const vdc5_channel_t ch)
+{
+    vdc5_resource_state_t state;
+
+    state = VDC5_RESOURCE_ST_INVALID;
+
+    if ((layer_resource[ch][VDC5_LAYER_ID_OIR_WR] != VDC5_RESOURCE_ST_INVALID) &&
+            (rw_proc_state[ch][VDC5_LAYER_ID_OIR_WR] != VDC5_RW_PROC_STATE_DISABLE)) {
+        state = VDC5_RESOURCE_ST_VALID;
+    }
+    if ((layer_resource[ch][VDC5_LAYER_ID_OIR_RD] != VDC5_RESOURCE_ST_INVALID) &&
+            (rw_proc_state[ch][VDC5_LAYER_ID_OIR_RD] != VDC5_RW_PROC_STATE_DISABLE)) {
+        state = VDC5_RESOURCE_ST_VALID;
+    }
+    return state;
+}   /* End of function VDC5_ShrdPrmGetOirRwProcEnabled() */
+
+/******************************************************************************
+Local Functions
+******************************************************************************/
+/**************************************************************************//**
+ * @brief       Gets the pointer to the resource state
+ * @param[in]   ch                      : Channel
+ * @param[in]   rsrc_type               : Resource type
+ * @retval      Pointer to the resource state
+ *****************************************************************************/
+static vdc5_resource_state_t * GetResourceStatePointer (const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type)
+{
+    vdc5_resource_state_t             * resource_state;
+    static vdc5_shared_param_resource_t param_resource[VDC5_CHANNEL_NUM] = {
+        {VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID},
+        {VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID, VDC5_RESOURCE_ST_INVALID}
+    };
+    static vdc5_resource_state_t        lvds_resource = VDC5_RESOURCE_ST_INVALID;
+
+    switch (rsrc_type) {
+        case VDC5_RESOURCE_PANEL_CLK:
+            resource_state = &param_resource[ch].rsrc_panel_clock;
+            break;
+        case VDC5_RESOURCE_VIDEO_IN:
+            resource_state = &param_resource[ch].rsrc_video_input;
+            break;
+        case VDC5_RESOURCE_VSYNC:
+            resource_state = &param_resource[ch].rsrc_vsync_signal;
+            break;
+        case VDC5_RESOURCE_LCD_PANEL:
+            resource_state = &param_resource[ch].rsrc_lcd_panel;
+            break;
+        case VDC5_RESOURCE_LVDS_CLK:
+            resource_state = &lvds_resource;
+            break;
+
+        default:
+            resource_state = NULL;
+            break;
+    }
+    return resource_state;
+}   /* End of function GetResourceStatePointer() */
+
+/**************************************************************************//**
+ * @brief       Product-sum operation
+ * @param[in]   red             : 8 bits for red
+ * @param[in]   green           : 8 bits for green
+ * @param[in]   blue            : 8 bits for blue
+ * @param[in]   coeff_r         : Coefficient value for Cr/R signal gain adjustment
+ * @param[in]   coeff_g         : Coefficient value for Y/G signal gain adjustment
+ * @param[in]   coeff_b         : Coefficient value for Cb/B signal gain adjustment
+ * @param[in]   offset          : Coefficient value for offset adjustment
+ * @retval      Answer
+ *****************************************************************************/
+static uint32_t SumProduct (
+    const int32_t   red,
+    const int32_t   green,
+    const int32_t   blue,
+    int32_t         coeff_r,
+    int32_t         coeff_g,
+    int32_t         coeff_b,
+    const int32_t   offset)
+{
+    int32_t color_val;
+
+    /* Coefficient values are represented in 11-bit two's complement integer. */
+    if (coeff_r >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2)) {
+        coeff_r -= (int32_t)TWO_POWER_ELEVEN;
+    }
+    if (coeff_g >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2)) {
+        coeff_g -= (int32_t)TWO_POWER_ELEVEN;
+    }
+    if (coeff_b >= (TWO_POWER_ELEVEN / VDC5_SPARA_DIV_2)) {
+        coeff_b -= (int32_t)TWO_POWER_ELEVEN;
+    }
+
+    color_val  = (red * coeff_r) + (green * coeff_g) + (blue * coeff_b);
+    color_val /= (int32_t)VDC5_SPARA_DIV_256;
+    color_val += offset;
+    if (color_val < 0) {
+        color_val = 0;
+    } else if (color_val > (int32_t)VDC5_SPARA_COLOR_CONV_RANGE) {
+        color_val = (int32_t)VDC5_SPARA_COLOR_CONV_RANGE;
+    } else {
+    }
+    return (uint32_t)color_val;
+}   /* End of function SumProduct() */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdc5/src/r_vdc5_shared_param.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,144 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdc5_shared_param.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDC5 driver shared parameter definitions
+******************************************************************************/
+
+#ifndef R_VDC5_SHARED_PARAM_H
+#define R_VDC5_SHARED_PARAM_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdc5.h"
+#include    "r_vdc5_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Color space */
+typedef enum {
+    VDC5_COLOR_SPACE_GBR    = 0,        /*!< GBR */
+    VDC5_COLOR_SPACE_YCBCR  = 1         /*!< YCbCr */
+} vdc5_color_space_t;
+
+/*! Resource state */
+typedef enum {
+    VDC5_RESOURCE_ST_INVALID    = 0,    /*!< Invalid */
+    VDC5_RESOURCE_ST_VALID      = 1     /*!< Valid */
+} vdc5_resource_state_t;
+
+/*! Resource type */
+typedef enum {
+    VDC5_RESOURCE_PANEL_CLK = 0,        /*!< Panel clock */
+    VDC5_RESOURCE_VIDEO_IN,             /*!< Input video */
+    VDC5_RESOURCE_VSYNC,                /*!< Vsync signal */
+    VDC5_RESOURCE_LCD_PANEL,            /*!< LCD panel (output video) */
+    VDC5_RESOURCE_LVDS_CLK,             /*!< LVDS PLL clock */
+    VDC5_RESOURCE_NUM
+} vdc5_resource_type_t;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDC5_ShrdPrmInit(const vdc5_channel_t ch);
+
+void VDC5_ShrdPrmSetInitParam(const vdc5_channel_t ch, const vdc5_init_t * const param);
+void VDC5_ShrdPrmSetTerminate(const vdc5_channel_t ch);
+void VDC5_ShrdPrmSetInputParam(const vdc5_channel_t ch, const vdc5_input_t * const param);
+void VDC5_ShrdPrmSetSyncParam(const vdc5_channel_t ch, const vdc5_sync_ctrl_t * const param);
+void VDC5_ShrdPrmSetOutputParam(const vdc5_channel_t ch, const vdc5_output_t * const param);
+void VDC5_ShrdPrmSetWriteParam(
+    const vdc5_channel_t        ch,
+    const vdc5_scaling_type_t   scaling_id,
+    const vdc5_write_t  * const param);
+void VDC5_ShrdPrmSetChgWriteParam(
+    const vdc5_channel_t            ch,
+    const vdc5_scaling_type_t       scaling_id,
+    const vdc5_write_chg_t  * const param);
+void VDC5_ShrdPrmSetReadParam(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id,
+    const vdc5_read_t   * const param);
+void VDC5_ShrdPrmSetChgReadParam(
+    const vdc5_channel_t            ch,
+    const vdc5_graphics_type_t      graphics_id,
+    const vdc5_read_chg_t   * const param);
+void VDC5_ShrdPrmSetCascade(const vdc5_channel_t ch, const vdc5_onoff_t cascade);
+void VDC5_ShrdPrmSetUndSel(const vdc5_channel_t ch, const vdc5_onoff_t und_sel);
+
+vdc5_panel_clksel_t VDC5_ShrdPrmGetPanelClkSel(const vdc5_channel_t ch);
+vdc5_onoff_t VDC5_ShrdPrmGetLvdsClkRef(void);
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpace(const vdc5_channel_t ch);
+vdc5_input_sel_t VDC5_ShrdPrmGetInputSelect(const vdc5_channel_t ch);
+vdc5_res_vs_in_sel_t VDC5_ShrdPrmGetVsInSel(const vdc5_channel_t ch);
+vdc5_onoff_t VDC5_ShrdPrmGetCascade(const vdc5_channel_t ch);
+vdc5_onoff_t VDC5_ShrdPrmGetUndSel(const vdc5_channel_t ch);
+uint32_t VDC5_ShrdPrmGetBgColor(const vdc5_channel_t ch, const vdc5_color_space_t color_space);
+vdc5_wr_md_t VDC5_ShrdPrmGetWritingMode(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+vdc5_res_inter_t VDC5_ShrdPrmGetInterlace(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbWr(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+void * VDC5_ShrdPrmGetFrBuffBtm(const vdc5_channel_t ch, const vdc5_scaling_type_t scaling_id);
+
+vdc5_gr_ln_off_dir_t VDC5_ShrdPrmGetLineOfsAddrDir(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_gr_flm_sel_t VDC5_ShrdPrmGetSelFbAddrSig(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_gr_format_t VDC5_ShrdPrmGetGraphicsFormat(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_color_space_t VDC5_ShrdPrmGetColorSpaceFbRd(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_onoff_t VDC5_ShrdPrmGetMeasureFolding(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_period_rect_t * VDC5_ShrdPrmGetDisplayArea(const vdc5_channel_t ch, const vdc5_graphics_type_t graphics_id);
+vdc5_width_read_fb_t * VDC5_ShrdPrmGetFrBuffWidth_Rd(
+    const vdc5_channel_t        ch,
+    const vdc5_graphics_type_t  graphics_id);
+vdc5_channel_t VDC5_ShrdPrmGetLvdsCh(void);
+
+void VDC5_ShrdPrmSetResource(
+    const vdc5_channel_t        ch,
+    const vdc5_resource_type_t  rsrc_type,
+    const vdc5_resource_state_t rsrc_state);
+void VDC5_ShrdPrmSetLayerResource(
+    const vdc5_channel_t        ch,
+    const vdc5_layer_id_t       layer_id,
+    const vdc5_resource_state_t rsrc_state);
+vdc5_resource_state_t VDC5_ShrdPrmGetResource(const vdc5_channel_t ch, const vdc5_resource_type_t rsrc_type);
+vdc5_resource_state_t VDC5_ShrdPrmGetLayerResource(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+
+void VDC5_ShrdPrmSetRwProcEnable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+void VDC5_ShrdPrmSetRwProcDisable(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcReady(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_resource_state_t VDC5_ShrdPrmGetRwProcEnabled(const vdc5_channel_t ch, const vdc5_layer_id_t layer_id);
+vdc5_resource_state_t VDC5_ShrdPrmGetOirRwProcEnabled(const vdc5_channel_t ch);
+
+
+#endif  /* R_VDC5_SHARED_PARAM_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdec/include/r_vdec.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,637 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver API definitions
+******************************************************************************/
+
+#ifndef R_VDEC_H
+#define R_VDEC_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec_user.h"
+
+
+#ifdef  __cplusplus
+extern  "C"
+{
+#endif  /* __cplusplus */
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! The number of chroma filter TAP coefficient values for Y/C separation */
+#define     VDEC_CHRFIL_TAPCOEF_NUM     (9)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Error codes of the VDEC driver */
+typedef enum {
+    VDEC_OK = 0,                /*!< Normal termination */
+    VDEC_ERR_CHANNEL,           /*!< Invalid channel error */
+    VDEC_ERR_PARAM,             /*!< Parameter error */
+    VDEC_ERR_NUM                /*!< The number of the error codes */
+} vdec_error_t;
+
+/*! VDEC channel */
+typedef enum {
+    VDEC_CHANNEL_0 = 0,         /*!< Channel 0 */
+    VDEC_CHANNEL_1,             /*!< Channel 1 */
+    VDEC_CHANNEL_NUM            /*!< The number of channels */
+} vdec_channel_t;
+
+/*! On/Off */
+typedef enum {
+    VDEC_OFF    = 0,            /*!< Off */
+    VDEC_ON     = 1             /*!< On */
+} vdec_onoff_t;
+
+/***********************    For R_VDEC_Initialize       ***********************/
+/*! Input pin control */
+typedef enum {
+    VDEC_ADC_VINSEL_VIN1 = 0,       /*!< VIN1 input */
+    VDEC_ADC_VINSEL_VIN2,           /*!< VIN2 input */
+    VDEC_ADC_VINSEL_NUM             /*!< The number of input pins */
+} vdec_adc_vinsel_t;
+
+/***********************    For R_VDEC_ActivePeriod     ***********************/
+/*! Active image period parameter */
+typedef struct {
+    uint16_t    srcleft;            /*!< Left end of input video signal capturing area */
+    uint16_t    srctop;             /*!< Top end of input video signal capturing area */
+    uint16_t    srcheight;          /*!< Height of input video signal capturing area */
+    uint16_t    srcwidth;           /*!< Width of input video signal capturing area */
+} vdec_active_period_t;
+
+/***********************    For R_VDEC_SyncSeparation   ***********************/
+/*! LPF cutoff frequency before vertical sync separation */
+typedef enum {
+    VDEC_LPF_VSYNC_NONE = 0,        /*!< None */
+    VDEC_LPF_VSYNC_0_94,            /*!< 0.94 MHz */
+    VDEC_LPF_VSYNC_0_67,            /*!< 0.67 MHz */
+    VDEC_LPF_VSYNC_0_54,            /*!< 0.54 MHz */
+    VDEC_LPF_VSYNC_0_47,            /*!< 0.47 MHz */
+    VDEC_LPF_VSYNC_0_34,            /*!< 0.34 MHz */
+    VDEC_LPF_VSYNC_0_27,            /*!< 0.27 MHz */
+    VDEC_LPF_VSYNC_0_23,            /*!< 0.23 MHz */
+    VDEC_LPF_VSYNC_NUM
+} vdec_lpfvsync_t;
+/*! LPF cutoff frequency before horizontal sync separation */
+typedef enum {
+    VDEC_LPF_HSYNC_NONE = 0,        /*!< None */
+    VDEC_LPF_HSYNC_2_15,            /*!< 2.15 MHz */
+    VDEC_LPF_HSYNC_1_88,            /*!< 1.88 MHz */
+    VDEC_LPF_HSYNC_1_34,            /*!< 1.34 MHz */
+    VDEC_LPF_HSYNC_1_07,            /*!< 1.07 MHz */
+    VDEC_LPF_HSYNC_0_94,            /*!< 0.94 MHz */
+    VDEC_LPF_HSYNC_0_67,            /*!< 0.67 MHz */
+    VDEC_LPF_HSYNC_0_54,            /*!< 0.54 MHz */
+    VDEC_LPF_HSYNC_NUM
+} vdec_lpfhsync_t;
+/*! Noise reduction LPF parameter */
+typedef struct {
+    vdec_lpfvsync_t lpfvsync;       /*!< LPF cutoff frequency before vertical sync separation */
+    vdec_lpfhsync_t lpfhsync;       /*!< LPF cutoff frequency before horizontal sync separation */
+} vdec_noise_rd_lpf_t;
+/*! Reference level operation speed control for composite sync separation (for Hsync signal) */
+typedef enum {
+    VDEC_VELOCITY_SHIFT_1 = 0,      /*!< x1 */
+    VDEC_VELOCITY_SHIFT_2,          /*!< x2 */
+    VDEC_VELOCITY_SHIFT_4,          /*!< x4 */
+    VDEC_VELOCITY_SHIFT_8,          /*!< x8 */
+    VDEC_VELOCITY_SHIFT_16,         /*!< x16 */
+    VDEC_VELOCITY_SHIFT_32,         /*!< x32 */
+    VDEC_VELOCITY_SHIFT_64,         /*!< x64 */
+    VDEC_VELOCITY_SHIFT_128,        /*!< x128 */
+    VDEC_VELOCITY_SHIFT_256,        /*!< x256 */
+    VDEC_VELOCITY_SHIFT_NUM
+} vdec_velocityshift_h_t;
+/*! Auto-slice level setting for composite sync separation circuit */
+typedef enum {
+    VDEC_SLICE_MODE_MANULAL = 0,    /*!< Manual setting */
+    VDEC_SLICE_MODE_AUTO_25,        /*!< 25% of sync depth (Auto) */
+    VDEC_SLICE_MODE_AUTO_50,        /*!< 50% of sync depth (Auto) */
+    VDEC_SLICE_MODE_AUTO_75,        /*!< 75% of sync depth (Auto) */
+    VDEC_SLICE_MODE_NUM
+} vdec_slicermode_t;
+/*! Clipping level */
+typedef enum {
+    VDEC_CLIP_LV_512 = 0,           /*!< 512 */
+    VDEC_CLIP_LV_546,               /*!< 546 */
+    VDEC_CLIP_LV_580,               /*!< 580 */
+    VDEC_CLIP_LV_614,               /*!< 614 */
+    VDEC_CLIP_LV_648,               /*!< 648 */
+    VDEC_CLIP_LV_682,               /*!< 682 */
+    VDEC_CLIP_LV_716,               /*!< 716 */
+    VDEC_CLIP_LV_750,               /*!< 750 */
+    VDEC_CLIP_LV_785,               /*!< 785 */
+    VDEC_CLIP_LV_819,               /*!< 819 */
+    VDEC_CLIP_LV_853,               /*!< 853 */
+    VDEC_CLIP_LV_887,               /*!< 887 */
+    VDEC_CLIP_LV_921,               /*!< 921 */
+    VDEC_CLIP_LV_955,               /*!< 955 */
+    VDEC_CLIP_LV_989,               /*!< 989 */
+    VDEC_CLIP_LV_1023,              /*!< 1023 */
+    VDEC_CLIP_LV_NUM
+} vdec_ssclipsel_t;
+/*! Sync slicer */
+typedef struct {
+    vdec_velocityshift_h_t  velocityshift_h;    /*!< Reference level operation speed control for
+                                                     composite sync separation (for Hsync signal) */
+    vdec_slicermode_t       slicermode_h;       /*!< Auto-slice level setting for composite sync separation circuit
+                                                     (for Hsync signal) */
+    vdec_slicermode_t       slicermode_v;       /*!< Auto-slice level setting for composite sync separation circuit
+                                                     (for Vsync signal) */
+    uint16_t                syncmaxduty_h;      /*!< Max ratio of horizontal cycle
+                                                     to horizontal sync signal pulse width */
+    uint16_t                syncminduty_h;      /*!< Min ratio of horizontal cycle
+                                                     to horizontal sync signal pulse width */
+    vdec_ssclipsel_t        ssclipsel;          /*!< Clipping level */
+    uint16_t                csyncslice_h;       /*!< Slice level for composite sync signal separation
+                                                     (for Hsync signal) */
+    uint16_t                syncmaxduty_v;      /*!< Max ratio of horizontal cycle
+                                                     to vertical sync signal pulse width */
+    uint16_t                syncminduty_v;      /*!< Min ratio of horizontal cycle
+                                                     to horizontal sync signal pulse width */
+    vdec_onoff_t            vsyncdelay;         /*!< Delays the separated vertical sync signal
+                                                     for 1/4 horizontal cycle */
+    uint16_t                vsyncslice;         /*!< Threshold for vertical sync separation */
+    uint16_t                csyncslice_v;       /*!< Slice level for composite sync signal separation
+                                                     (for Vsync signal) */
+} vdec_sync_slicer_t;
+/*! Horizontal AFC VBI period operating mode */
+typedef enum {
+    VDEC_HAFCMD_FIX_PHST = 0,               /*!< Loop gain is fixed and phase comparison is stopped
+                                                 during VBI period */
+    VDEC_HAFCMD_FIX_LGRD,                   /*!< Loop gain is fixed and loop gain is reduced during VBI period */
+    VDEC_HAFCMD_AUTO_PHST,                  /*!< Loop gain is automatically controlled and
+                                                 phase comparison is stopped during VBI period */
+    VDEC_HAFCMD_AUTO_LGRD,                  /*!< Loop gain is automatically controlled and loop gain is reduced
+                                                 during VBI period */
+    VDEC_HAFCMD_NUM
+} vdec_hafcmode_t;
+/*! Phase comparator feedback adjust for low sync signal lock stability */
+typedef enum {
+    VDEC_PHDET_DIV_1_1 = 0,                 /*!< 1/1 */
+    VDEC_PHDET_DIV_1_2,                     /*!< 1/2 */
+    VDEC_PHDET_DIV_1_4,                     /*!< 1/4 */
+    VDEC_PHDET_DIV_1_8,                     /*!< 1/8 */
+    VDEC_PHDET_DIV_1_16,                    /*!< 1/16 */
+    VDEC_PHDET_DIV_1_32,                    /*!< 1/32 */
+    VDEC_PHDET_DIV_NUM
+} vdec_phdet_div_t;
+/*! Horizontal AFC parameter */
+typedef struct {
+    uint16_t            hafcgain;           /*!< Horizontal AFC loop gain */
+    uint16_t            hafctyp;            /*!< Horizontal AFC center oscillation frequency */
+    uint16_t            hafcstart;          /*!< Start line of horizontal AFC normal operation
+                                                 (VBI process end line) */
+    vdec_onoff_t        nox2hosc;           /*!< Disable of horizontal AFC double speed detection */
+    uint16_t            hafcmax;            /*!< Maximum oscillation frequency of horizontal AFC */
+    uint16_t            hafcend;            /*!< End line of horizontal AFC normal operation
+                                                 (VBI process start line) */
+    vdec_hafcmode_t     hafcmode;           /*!< Horizontal AFC VBI period operating mode */
+    uint16_t            hafcmin;            /*!< Min oscillation frequency of horizontal AFC */
+    vdec_onoff_t        phdet_fix;          /*!< Forcible or LOWGAIN control */
+    vdec_phdet_div_t    phdet_div;          /*!< Phase comparator feedback adjust for low sync signal lock stability */
+} vdec_horizontal_afc_t;
+/*! Vertical countdown center oscillation frequency */
+typedef enum {
+    VDEC_VCD_FRQ_AUTO = 0,                  /*!< Auto-detection */
+    VDEC_VCD_FRQ_50HZ,                      /*!< 50.00 Hz */
+    VDEC_VCD_FRQ_59_94HZ,                   /*!< 59.94 Hz */
+    VDEC_VCD_FRQ_60HZ,                      /*!< 60.00 Hz */
+    VDEC_VCD_FRQ_NUM
+} vdec_vcddefault_t;
+/*! Vertical count-down parameter */
+typedef struct {
+    vdec_onoff_t        novcd50_;           /*!< Vertical countdown 50-Hz oscillation mode */
+    vdec_onoff_t        novcd60_;           /*!< Vertical countdown 60-Hz (59.94-Hz) oscillation mode */
+    vdec_vcddefault_t   vcddefault;         /*!< Vertical countdown center oscillation frequency */
+    uint16_t            vcdwindow;          /*!< Vertical countdown sync area */
+    uint16_t            vcdoffset;          /*!< Vertical countdown minimum oscillation frequency */
+} vdec_vcount_down_t;
+/*! AGC/PGA parameter */
+typedef struct {
+    vdec_onoff_t    agcmode;                /*!< A/D converter AGC ON/OFF control & PGA switch */
+    vdec_onoff_t    doreduce;               /*!< Manual control of sync signal amplitude detection during VBI period */
+    vdec_onoff_t    noreduce_;              /*!< Control of sync signal amplitude detection during VBI period */
+    uint16_t        agcresponse;            /*!< AGC response speed */
+    uint16_t        agclevel;               /*!< Sync signal reference amplitude */
+    uint16_t        agcprecis;              /*!< AGC gain adjustment accuracy */
+    uint16_t        pga_gain;               /*!< PGA gain */
+} vdec_agc_t;
+/*! Peak luminance value to operate peak limiter */
+typedef enum {
+    VDEC_PEAKLV_LIM_OFF =0,                 /*!< Limiter OFF */
+    VDEC_PEAKLV_1008,                       /*!< 1008 LSB */
+    VDEC_PEAKLV_992,                        /*!< 992 LSB */
+    VDEC_PEAKLV_960,                        /*!< 960 LSB */
+    VDEC_PEAKLV_NUM
+} vdec_peaklevel_t;
+/*! Maximum compression rate of peak limiter */
+typedef enum {
+    VDEC_PEAKRATIO_50 = 0,                  /*!< Compressed up to 50% */
+    VDEC_PEAKRATIO_25,                      /*!< Compressed up to 25% */
+    VDEC_PEAKRATIO_12_5,                    /*!< Compressed up to 12.5% */
+    VDEC_PEAKRATIO_0,                       /*!< Compressed up to 0% */
+    VDEC_PEAKRATIO_NUM
+} vdec_peakratio_t;
+/*! Peak limiter control parameter */
+typedef struct {
+    vdec_peaklevel_t    peaklevel;          /*!< Peak luminance value limited by peak limiter (video signal level) */
+    uint16_t            peakattack;         /*!< Response speed with peak limiter gain decreased */
+    uint16_t            peakrelease;        /*!< Response speed with peak limiter gain increased */
+    vdec_peakratio_t    peakratio;          /*!< Maximum compression rate of peak limiter */
+    uint16_t            maxpeaksamples;     /*!< Allowable number of overflowing pixels */
+} vdec_peak_limiter_t;
+/*! Sync separation parameter */
+typedef struct {
+    vdec_noise_rd_lpf_t   * noise_rd_lpf;       /*!< Noise reduction LPF parameter */
+    vdec_sync_slicer_t    * sync_slicer;        /*!< Auto level control sync slicer parameter */
+    vdec_horizontal_afc_t * horizontal_afc;     /*!< Horizontal AFC parameter */
+    vdec_vcount_down_t    * vcount_down;        /*!< Vertical count-down parameter */
+    vdec_agc_t            * agc;                /*!< AGC/PGA parameter */
+    vdec_peak_limiter_t   * peak_limiter;       /*!< Peak limiter control parameter */
+} vdec_sync_separation_t;
+
+/***********************    For R_VDEC_YcSeparation     ***********************/
+/*! Over-range control parameter */
+typedef struct {
+    uint16_t        radj_o_level0;          /*!< A/D over-threshold level (between levels 0 and 1) */
+    uint16_t        radj_u_level0;          /*!< A/D under-threshold level (between levels 2 and 3) */
+    uint16_t        radj_o_level1;          /*!< A/D over-threshold level (between levels 1 and 2) */
+    uint16_t        radj_u_level1;          /*!< A/D under-threshold level (between levels 1 and 2) */
+    uint16_t        radj_o_level2;          /*!< A/D over-threshold level (between levels 2 and 3) */
+    uint16_t        radj_u_level2;          /*!< A/D under-threshold level (between levels 0 and 1) */
+    vdec_onoff_t    ucmp_sw;                /*!< Over-range detection enable */
+    vdec_onoff_t    dcmp_sw;                /*!< Under-range detection enable */
+    vdec_onoff_t    hwide_sw;               /*!< Horizontal enlargement of over/under-range level */
+} vdec_over_range_t;
+/*! Latter-stage BPF select */
+typedef enum {
+    VDEC_LSTG_BPFSEL_BYPASS     = 0,        /*!< Bypass */
+    VDEC_LSTG_BPFSEL_17TAP      = 1         /*!< 17 TAP */
+} vdec_lstg_bpfsel_t;
+/*! Former-stage BPF select */
+typedef enum {
+    VDEC_FSTG_BPFSEL_17TAP      = 0,        /*!< 17 TAP */
+    VDEC_FSTG_BPFSEL_9TAP       = 1         /*!< 9 TAP */
+} vdec_fstg_bpfsel_t;
+/*! Horizontal filter and horizontal/vertical filter bandwidth switch signal */
+typedef enum {
+    VDEC_HFIL_TAP_SEL_17TAP     = 0,        /*!< 17 TAP */
+    VDEC_HFIL_TAP_SEL_9TAP      = 1         /*!< 9 TAP */
+} vdec_hfil_tap_sel_t;
+/*! Mixing ratio of signals after passing filters */
+typedef enum {
+    VDEC_FILMIX_RATIO_0 = 0,            /*!< 0% */
+    VDEC_FILMIX_RATIO_12_5,             /*!< 12.5% */
+    VDEC_FILMIX_RATIO_25,               /*!< 25% */
+    VDEC_FILMIX_RATIO_37_5,             /*!< 37.5% */
+    VDEC_FILMIX_RATIO_50,               /*!< 50% */
+    VDEC_FILMIX_RATIO_62_5,             /*!< 62.5% */
+    VDEC_FILMIX_RATIO_75,               /*!< 75% */
+    VDEC_FILMIX_RATIO_87_5,             /*!< 87.5% */
+    VDEC_FILMIX_RATIO_100,              /*!< 100% */
+    VDEC_FILMIX_RATIO_NUM
+} vdec_filmix_ratio_t;
+/*! Two-dimensional cascade/TAKE-OFF filter mode select */
+typedef enum {
+    VDEC_2DFIL_MDSEL_BYPASS = 0,        /*!< Bypass */
+    VDEC_2DFIL_MDSEL_CASCADE,           /*!< Cascade filter */
+    VDEC_2DFIL_MDSEL_TAKEOFF,           /*!< TAKE-OFF filter */
+    VDEC_2DFIL_MDSEL_NUM
+} vdec_2dfil_mdsel_t;
+/*! Two-dimensional cascade filter select */
+typedef enum {
+    VDEC_2D_FIL_SEL_BYPASS      = 0,        /*!< Bypass */
+    VDEC_2D_FIL_SEL_17TAP       = 1         /*!< 17 TAP */
+} vdec_2d_fil_sel_t;
+/*! Y/C separation control parameter */
+typedef struct {
+    uint16_t            k15;            /*!< Two-dimensional Y/C separation filter select coefficient, K15 */
+    uint16_t            k13;            /*!< Two-dimensional Y/C separation filter select coefficient, K13 */
+    uint16_t            k11;            /*!< Two-dimensional Y/C separation filter select coefficient, K11 */
+    uint16_t            k16;            /*!< Two-dimensional Y/C separation filter select coefficient, K16 */
+    uint16_t            k14;            /*!< Two-dimensional Y/C separation filter select coefficient, K14 */
+    uint16_t            k12;            /*!< Two-dimensional Y/C separation filter select coefficient, K12 */
+    uint16_t            k22a;           /*!< Two-dimensional Y/C separation filter select coefficient, K22A */
+    uint16_t            k21a;           /*!< Two-dimensional Y/C separation filter select coefficient, K21A */
+    uint16_t            k22b;           /*!< Two-dimensional Y/C separation filter select coefficient, K22B */
+    uint16_t            k21b;           /*!< Two-dimensional Y/C separation filter select coefficient, K21B */
+    uint16_t            k23b;           /*!< Two-dimensional Y/C separation filter select coefficient, K23B */
+    uint16_t            k23a;           /*!< Two-dimensional Y/C separation filter select coefficient, K23A */
+    uint16_t            k24;            /*!< Two-dimensional Y/C separation filter select coefficient, K24 */
+    vdec_lstg_bpfsel_t  hbpf_narrow;    /*!< Latter-stage horizontal BPF select */
+    vdec_lstg_bpfsel_t  hvbpf_narrow;   /*!< Latter-stage horizontal/vertical BPF select */
+    vdec_fstg_bpfsel_t  hbpf1_9tap_on;  /*!< Former-stage horizontal BPF select */
+    vdec_fstg_bpfsel_t  hvbpf1_9tap_on; /*!< Former-stage horizontal/vertical BPF select */
+    vdec_hfil_tap_sel_t hfil_tap_sel;   /*!< Horizontal filter and horizontal/vertical filter
+                                             bandwidth switch signal */
+    vdec_onoff_t        det2_on;        /*!< Two-dimensional filter mixing select */
+    vdec_filmix_ratio_t hsel_mix_y;     /*!< Mixing ratio of signal after passing horizontal filter
+                                             to signal after passing former-stage horizontal filter */
+    vdec_filmix_ratio_t vsel_mix_y;     /*!< Mixing ratio of signal after passing vertical filter
+                                             to signal after passing former-stage horizontal/vertical filter */
+    vdec_filmix_ratio_t hvsel_mix_y;    /*!< Mixing ratio of signal after passing horizontal/vertical filter
+                                             to signal after passing former-stage horizontal/vertical filter */
+    uint16_t            v_y_level;      /*!< Vertical luminance detection level for correlation detection filter */
+    vdec_filmix_ratio_t det2_mix_c;     /*!< Mixing ratio of C signal after passing horizontal/vertical adaptive filter
+                                             to signal after passing correlation detection filter */
+    vdec_filmix_ratio_t det2_mix_y;     /*!< Mixing ratio of C signal for Y generation after passing
+                                             horizontal/vertical adaptive filter to signal
+                                             after passing correlation detection filter */
+    vdec_2dfil_mdsel_t  fil2_mode_2d;   /*!< Two-dimensional cascade/TAKE-OFF filter mode select */
+    vdec_2d_fil_sel_t   fil2_narrow_2d; /*!< Two-dimensional cascade filter select */
+} vdec_yc_sep_ctrl_t;
+/*! Chroma filter TAP coefficient for Y/C separation */
+typedef struct {
+    uint16_t    fil2_2d_f[VDEC_CHRFIL_TAPCOEF_NUM];     /*!< Chroma filter TAP coefficient 0 to 8 */
+} vdec_chrfil_tap_t;
+/*! Y/C separation parameter */
+typedef struct {
+    vdec_over_range_t         * over_range;     /*!< Over-range control parameter */
+    vdec_yc_sep_ctrl_t        * yc_sep_ctrl;    /*!< Y/C separation control parameter */
+    const vdec_chrfil_tap_t   * fil2_2d_wa;     /*!< Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF
+                                                     filter TAP coefficient */
+    const vdec_chrfil_tap_t * fil2_2d_wb;       /*!< Two-dimensional cascade broadband (SECAM-DB) filter
+                                                     TAP coefficient */
+    const vdec_chrfil_tap_t * fil2_2d_na;       /*!< Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter
+                                                     TAP coefficient */
+    const vdec_chrfil_tap_t * fil2_2d_nb;       /*!< Two-dimensional cascade narrowband (SECAMDB) filter
+                                                     TAP coefficient */
+} vdec_yc_separation_t;
+
+/***********************    For R_VDEC_ChromaDecoding   ***********************/
+/*! Color system */
+typedef enum {
+    VDEC_COL_SYS_NTSC = 0,                  /*!< NTSC */
+    VDEC_COL_SYS_PAL,                       /*!< PAL */
+    VDEC_COL_SYS_SECAM,                     /*!< SECAM */
+    VDEC_COL_SYS_NON,                       /*!< Not specified/undetectable */
+    VDEC_COL_SYS_NUM                        /*!< The number of color system settings */
+} vdec_color_sys_t;
+/*! Averaging processing for pre-demodulated line */
+typedef enum {
+    VDEC_DEMOD_MD_NO    = 0,                /*!< No processing */
+    VDEC_DEMOD_MD_PAL   = 2                 /*!< For PAL */
+} vdec_demodmode_t;
+/*! Color system detection parameter */
+typedef struct {
+    vdec_color_sys_t    defaultsys;         /*!< Default color system */
+    vdec_onoff_t        nontsc358_;         /*!< NTSC-M detection control */
+    vdec_onoff_t        nontsc443_;         /*!< NTSC-4.43 detection control */
+    vdec_onoff_t        nopalm_;            /*!< PAL-M detection control */
+    vdec_onoff_t        nopaln_;            /*!< PAL-N detection control */
+    vdec_onoff_t        nopal443_;          /*!< PAL-B, G, H, I, D detection control */
+    vdec_onoff_t        nosecam_;           /*!< SECAM detection control */
+    uint16_t            lumadelay;          /*!< Luminance signal delay adjustment */
+    vdec_onoff_t        chromalpf;          /*!< LPF for demodulated chroma */
+    vdec_demodmode_t    demodmode;          /*!< Averaging processing for pre-demodulated line */
+} vdec_chrmdec_ctrl_t;
+/*! Burst lock PLL lock range */
+typedef enum {
+    VDEC_LOCK_RANGE_400HZ = 0,              /*!< +-400 Hz */
+    VDEC_LOCK_RANGE_800HZ,                  /*!< +-800 Hz */
+    VDEC_LOCK_RANGE_1200HZ,                 /*!< +-1200 Hz */
+    VDEC_LOCK_RANGE_1600HZ,                 /*!< +-1600 Hz */
+    VDEC_LOCK_RANGE_NUM
+} vdec_lockrange_t;
+/*! BCO parameter */
+typedef struct {
+    vdec_lockrange_t    lockrange;          /*!< Burst lock PLL lock range */
+    uint16_t            loopgain;           /*!< Burst lock PLL loop gain */
+    uint16_t            locklimit;          /*!< Level for burst lock PLL to re-search free-run frequency */
+    uint16_t            bgpcheck;           /*!< burst gate pulse position check */
+    uint16_t            bgpwidth;           /*!< burst gate pulse width */
+    uint16_t            bgpstart;           /*!< burst gate pulse start position */
+} vdec_burst_lock_t;
+/*! ACC operating mode */
+typedef enum {
+    VDEC_ACC_MD_AUTO    = 0,                /*!< Auto gain */
+    VDEC_ACC_MD_MANUAL  = 1                 /*!< Manual gain */
+} vdec_accmode_t;
+/*! Maximum ACC gain */
+typedef enum {
+    VDEC_ACC_MAX_GAIN_6 = 0,                /*!< 6 times */
+    VDEC_ACC_MAX_GAIN_8,                    /*!< 8 times */
+    VDEC_ACC_MAX_GAIN_12,                   /*!< 12 times */
+    VDEC_ACC_MAX_GAIN_16,                   /*!< 16 times */
+    VDEC_ACC_MAX_GAIN_NUM
+} vdec_accmaxgain_t;
+/*! Chroma manual gain (sub) */
+typedef enum {
+    VDEC_CHRM_SB_GAIN_1 = 0,                /*!< 1 time */
+    VDEC_CHRM_SB_GAIN_2,                    /*!< 2 times */
+    VDEC_CHRM_SB_GAIN_4,                    /*!< 4 times */
+    VDEC_CHRM_SB_GAIN_8,                    /*!< 8 times */
+    VDEC_CHRM_SB_GAIN_NUM
+} vdec_chrm_subgain_t;
+/*! ACC and color killer parameter */
+typedef struct {
+    vdec_accmode_t      accmode;            /*!< ACC operating mode */
+    vdec_accmaxgain_t   accmaxgain;         /*!< Maximum ACC Gain */
+    uint16_t            acclevel;           /*!< ACC reference color burst amplitude */
+    vdec_chrm_subgain_t chromasubgain;      /*!< Chroma manual gain (sub) */
+    uint16_t            chromamaingain;     /*!< Chroma manual gain (main) */
+    uint16_t            accresponse;        /*!< ACC response speed */
+    uint16_t            accprecis;          /*!< ACC gain adjustment accuracy */
+    vdec_onoff_t        killermode;         /*!< Forced color killer mode ON/OFF */
+    uint16_t            killerlevel;        /*!< Color killer operation start point */
+    uint16_t            killeroffset;       /*!< Color killer offset */
+} vdec_acc_t;
+/*! TINT correction/R-Y axis correction parameter (only valid for NTSC/PAL) */
+typedef struct {
+    uint16_t    tintsub;                    /*!< Fine adjustment of R-Y demodulation axis */
+    uint16_t    tintmain;                   /*!< Hue adjustment level */
+} vdec_tint_ry_t;
+/*! Chroma decoding parameter */
+typedef struct {
+    vdec_chrmdec_ctrl_t   * chrmdec_ctrl;   /*!< Color system detection parameter */
+    vdec_burst_lock_t     * burst_lock;     /*!< BCO parameter */
+    vdec_acc_t            * acc;            /*!< ACC and color killer parameter */
+    vdec_tint_ry_t        * tint_ry;        /*!< TINT correction/R-Y axis correction parameter */
+} vdec_chroma_decoding_t;
+
+/***********************    For R_VDEC_DigitalClamp     ***********************/
+/*! Clamp level setting mode */
+typedef enum {
+    VDEC_DCPMODE_MANUAL = 0,                /*!< Manual clamp level setting */
+    VDEC_DCPMODE_AUTO   = 1                 /*!< Auto clamp level setting */
+} vdec_dcpmode_t;
+/*! Pedestal clamp parameter */
+typedef struct {
+    vdec_dcpmode_t      dcpmode_y;          /*!< Clamp level setting mode (Y signal) */
+    uint16_t            blanklevel_y;       /*!< Clamp offset level (Y signal) */
+    uint16_t            dcppos_y;           /*!< Digital clamp pulse horizontal start position (Y signal) */
+} vdec_pedestal_clamp_t;
+/*! Center clamp parameter */
+typedef struct {
+    vdec_dcpmode_t      dcpmode_c;          /*!< Clamp level setting mode (Cb/Cr signal) */
+    uint16_t            blanklevel_cb;      /*!< Clamp offset level (Cb signal) */
+    uint16_t            blanklevel_cr;      /*!< Clamp offset level (Cr signal) */
+    uint16_t            dcppos_c;           /*!< Digital clamp pulse horizontal start position (Cb/Cr signal) */
+} vdec_center_clamp_t;
+/*! Video signal for autocorrelation function */
+typedef enum {
+    VDEC_ACFINPUT_Y = 0,                    /*!< Y signal */
+    VDEC_ACFINPUT_CB,                       /*!< Cb signal */
+    VDEC_ACFINPUT_CR,                       /*!< Cr signal */
+    VDEC_ACFINPUT_NUM
+} vdec_acfinput_t;
+/*! Noise detection parameter */
+typedef struct {
+    vdec_acfinput_t     acfinput;           /*!< Video signal for autocorrelation function */
+    uint16_t            acflagtime;         /*!< Delay time for autocorrelation function calculation */
+    uint16_t            acffilter;          /*!< Smoothing parameter of autocorrelation function data */
+} vdec_noise_det_t;
+/*! Digital clamp parameter */
+typedef struct {
+    vdec_onoff_t            dcpcheck;       /*!< Digital clamp pulse position check */
+    uint16_t                dcpresponse;    /*!< Digital clamp response speed */
+    uint16_t                dcpstart;       /*!< Digital clamp start line */
+    uint16_t                dcpend;         /*!< Digital clamp end line */
+    uint16_t                dcpwidth;       /*!< Digital clamp pulse width */
+    vdec_pedestal_clamp_t * pedestal_clamp; /*!< Pedestal clamp parameter */
+    vdec_center_clamp_t   * center_clamp;   /*!< Center clamp parameter */
+    vdec_noise_det_t      * noise_det;      /*!< Noise detection parameter */
+} vdec_degital_clamp_t;
+
+/***********************    For R_VDEC_Output           ***********************/
+/*! Output adjustment parameter */
+typedef struct {
+    uint16_t    y_gain2;                /*!< Y signal gain coefficient */
+    uint16_t    cb_gain2;               /*!< Cb signal gain coefficient */
+    uint16_t    cr_gain2;               /*!< Cr signal gain coefficient */
+} vdec_output_t;
+
+/***********************    For R_VDEC_Query            ***********************/
+/*! Answer */
+typedef enum {
+    VDEC_NO         = 0,            /*!< No */
+    VDEC_YES        = 1             /*!< Yes */
+} vdec_answer_t;
+/*! Lock state */
+typedef enum {
+    VDEC_UNLOCK     = 0,            /*!< Unlocked */
+    VDEC_LOCK       = 1             /*!< Locked */
+} vdec_lock_t;
+/*! Speed detection result */
+typedef enum {
+    VDEC_FHMD_NORMAL        = 0,    /*!< Normal speed */
+    VDEC_FHMD_MULTIPLIED    = 1     /*!< Multiplied speed */
+} vdec_fhmode_t;
+/*! Vertical countdown oscillation mode */
+typedef enum {
+    VDEC_FVMD_50HZ  = 0,            /*!< 50 Hz */
+    VDEC_FVMD_60HZ  = 1             /*!< 60 Hz */
+} vdec_fvmode_t;
+/*! Color sub-carrier frequency detection result */
+typedef enum {
+    VDEC_FSCMD_3_58     = 0,        /*!< 3.58 MHz */
+    VDEC_FSCMD_4_43     = 1         /*!< 4.43 MHz */
+} vdec_fscmode_t;
+/*! Sync separation parameters (for query) */
+typedef struct {
+    vdec_lock_t     fhlock;         /*!< Horizontal AFC lock detection result */
+    vdec_answer_t   isnoisy;        /*!< Detection result of low S/N signal by sync separation */
+    vdec_fhmode_t   fhmode;         /*!< Speed detection result */
+    vdec_answer_t   nosignal_;      /*!< No-signal detection result */
+    vdec_lock_t     fvlock;         /*!< Vertical countdown lock detection result */
+    vdec_fvmode_t   fvmode;         /*!< Vertical countdown oscillation mode */
+    vdec_answer_t   interlaced;     /*!< Interlace detection result */
+    uint16_t        fvcount;        /*!< Vertical cycle measurement result */
+    uint32_t        fhcount;        /*!< Horizontal AFC oscillation cycle */
+    vdec_answer_t   isreduced;      /*!< Sync amplitude detection result during VBI period */
+    uint16_t        syncdepth;      /*!< Sync pulse amplitude detection result */
+} vdec_q_sync_sep_t;
+/*! AGC parameters (for query) */
+typedef struct {
+    uint16_t    highsamples;        /*!< Number of pixels which have larger luminance value than peak luminance
+                                         limited by peak limiter */
+    uint16_t    peaksamples;        /*!< Number of overflowing pixels */
+    uint16_t    agcconverge;        /*!< AGC convergence detection result */
+    uint16_t    agcgain;            /*!< Current AGC gain value */
+} vdec_q_agc_t;
+/*! Chroma decoding parameters (for query) */
+typedef struct {
+    vdec_color_sys_t    colorsys;   /*!< Color system detection result */
+    vdec_fscmode_t      fscmode;    /*!< Color sub-carrier frequency detection result */
+    vdec_lock_t         fsclock;    /*!< Burst lock PLL lock state detection result */
+    vdec_answer_t       noburst_;   /*!< Color burst detection result */
+    vdec_chrm_subgain_t accsubgain; /*!< Current ACC gain value (sub) */
+    uint16_t            accmaingain;/*!< Current ACC gain value (main) */
+    vdec_answer_t       issecam;    /*!< SECAM detection result */
+    vdec_answer_t       ispal;      /*!< PAL detection result */
+    vdec_answer_t       isntsc;     /*!< NTSC detection result */
+    uint16_t            locklevel;  /*!< Low S/N signal detection result by burst lock PLL */
+} vdec_q_chroma_dec_t;
+/*! Digital clamp parameters (for query) */
+typedef struct {
+    uint16_t    clamplevel_cb;      /*!< Digital clamp subtraction value (Cb signal) */
+    uint16_t    clamplevel_y;       /*!< Digital clamp subtraction value (Y signal) */
+    uint16_t    clamplevel_cr;      /*!< Digital clamp subtraction value (Cr signal) */
+    uint16_t    acfstrength;        /*!< Noise autocorrelation strength at digital clamp pulse position */
+} vdec_q_digital_clamp_t;
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+vdec_error_t R_VDEC_Initialize(
+    const vdec_channel_t    ch,
+    const vdec_adc_vinsel_t vinsel,
+    void           (* const init_func)(uint32_t),
+    const uint32_t          user_num);
+vdec_error_t R_VDEC_Terminate(const vdec_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num);
+vdec_error_t R_VDEC_ActivePeriod(const vdec_channel_t ch, const vdec_active_period_t * const param);
+vdec_error_t R_VDEC_SyncSeparation(const vdec_channel_t ch, const vdec_sync_separation_t * const param);
+vdec_error_t R_VDEC_YcSeparation(const vdec_channel_t ch, const vdec_yc_separation_t * const param);
+vdec_error_t R_VDEC_ChromaDecoding(const vdec_channel_t ch, const vdec_chroma_decoding_t * const param);
+vdec_error_t R_VDEC_DigitalClamp(const vdec_channel_t ch, const vdec_degital_clamp_t * const param);
+vdec_error_t R_VDEC_Output(const vdec_channel_t ch, const vdec_output_t * const param);
+vdec_error_t R_VDEC_Query(
+    const vdec_channel_t            ch,
+    vdec_q_sync_sep_t       * const q_sync_sep,
+    vdec_q_agc_t            * const q_agc,
+    vdec_q_chroma_dec_t     * const q_chroma_dec,
+    vdec_q_digital_clamp_t  * const q_digital_clamp);
+
+
+#ifdef  __cplusplus
+}
+#endif  /* __cplusplus */
+
+
+#endif  /* R_VDEC_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdec/include/r_vdec_user.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,50 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_user.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver user-defined header
+******************************************************************************/
+
+#ifndef R_VDEC_USER_H
+#define R_VDEC_USER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/*! Compilation switch to enable parameter check functions<br>
+    If this definition is enabled, the parameter check in each API function will be performed. */
+#define R_VDEC_CHECK_PARAMETERS
+
+
+#endif  /* R_VDEC_USER_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdec/src/r_vdec.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,346 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver API function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+#include    "r_vdec_register.h"
+#include    "r_vdec_check_parameter.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+/**************************************************************************//**
+ * @brief       VDEC driver initialization
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Calls the user-defined function specified in init_func.
+ *              - Sets up the input pins.
+ * @param[in]   ch                      : Channel
+ * @param[in]   vinsel                  : Input pin control
+ *                                        - VDEC_ADC_VINSEL_VIN1
+ *                                        - VDEC_ADC_VINSEL_VIN2
+ * @param[in]   init_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Initialize (
+    const vdec_channel_t    ch,
+    const vdec_adc_vinsel_t vinsel,
+    void           (* const init_func)(uint32_t),
+    const uint32_t          user_num)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_InitializeCheckParam(vinsel);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        /* User-defined function */
+        if (init_func != 0) {
+            init_func(user_num);
+        }
+        VDEC_Initialize(ch, vinsel);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_Initialize() */
+
+/**************************************************************************//**
+ * @brief       VDEC driver termination
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Calls the user-defined function specified in quit_func.
+ * @param[in]   ch                      : Channel
+ * @param[in]   quit_func               : Pointer to a user-defined function
+ * @param[in]   user_num                : User defined number
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Terminate (const vdec_channel_t ch, void (* const quit_func)(uint32_t), const uint32_t user_num)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        /* User-defined function */
+        if (quit_func != 0) {
+            quit_func(user_num);
+        }
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_Terminate() */
+
+/**************************************************************************//**
+ * @brief       Active image period setup
+ *
+ *              Description:<br>
+ *              This function configures the active image period.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Active image period parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_ActivePeriod (const vdec_channel_t ch, const vdec_active_period_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_ActivePeriodCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_ActivePeriod(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_ActivePeriod() */
+
+/**************************************************************************//**
+ * @brief       Sync separation processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Configures the noise reduction LPF.
+ *              - Configures the auto level control sync slicer.
+ *              - Configures the horizontal AFC.
+ *              - Configures the vertical count-down.
+ *              - Configures the AGC.
+ *              - Configures the peak limiter control.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Sync separation parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_SyncSeparation (const vdec_channel_t ch, const vdec_sync_separation_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_SyncSeparationCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_SyncSeparation(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_SyncSeparation() */
+
+/**************************************************************************//**
+ * @brief       Y/C separation processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Configures the over-range control.
+ *              - Configures the Y/C separation control.
+ *              - Configures the chroma filter TAP coefficients for Y/C separation.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Y/C separation parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_YcSeparation (const vdec_channel_t ch, const vdec_yc_separation_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_YcSeparationCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_YcSeparation(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_YcSeparation() */
+
+/**************************************************************************//**
+ * @brief       Chroma decoding processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Configures the color system detection.
+ *              - Configures the BCO.
+ *              - Configures the ACC/color killer.
+ *              - Configures the TINT correction/R-Y axis correction.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Chroma decoding parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_ChromaDecoding (const vdec_channel_t ch, const vdec_chroma_decoding_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_ChromaDecodingCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_ChromaDecoding(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_ChromaDecoding() */
+
+/**************************************************************************//**
+ * @brief       Digital clamp processing
+ *
+ *              Description:<br>
+ *              This function performs the following processing:
+ *              - Configures the digital clamp control.
+ *              - Configures the center clamp.
+ *              - Configures the pedestal clamp.
+ *              - Configures the noise detection control.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Digital clamp parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_DigitalClamp (const vdec_channel_t ch, const vdec_degital_clamp_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_DigitalClampCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_DigitalClamp(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_DigitalClamp() */
+
+/**************************************************************************//**
+ * @brief       Output adjustment processing
+ *
+ *              Description:<br>
+ *              This function makes settings for output adjustment.
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Output adjustment parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Output (const vdec_channel_t ch, const vdec_output_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+    if (vdec_error == VDEC_OK) {
+        vdec_error = VDEC_OutputCheckParam(param);
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_Output(ch, param);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_Output() */
+
+/**************************************************************************//**
+ * @brief       VDEC information acquisition processing
+ *
+ *              Description:<br>
+ *              This gets the parameters of the VDEC modules. The parameters that can be obtained are listed below.
+ *              - Sync separation parameters
+ *              - AGC parameters
+ *              - Chroma decoding parameters
+ *              - Digital clamp parameters
+ * @param[in]   ch                      : Channel
+ * @param[out]  q_sync_sep              : Pointer to the place where the sync separation parameters are stored.
+ * @param[out]  q_agc                   : Pointer to the place where the AGC parameters are stored.
+ * @param[out]  q_chroma_dec            : Pointer to the place where the chroma decoding parameters are stored.
+ * @param[out]  q_digital_clamp         : Pointer to the place where the digital clamp parameters are stored.
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t R_VDEC_Query (
+    const vdec_channel_t            ch,
+    vdec_q_sync_sep_t       * const q_sync_sep,
+    vdec_q_agc_t            * const q_agc,
+    vdec_q_chroma_dec_t     * const q_chroma_dec,
+    vdec_q_digital_clamp_t  * const q_digital_clamp)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+#ifdef      R_VDEC_CHECK_PARAMETERS
+    if ((ch != VDEC_CHANNEL_0) && (ch != VDEC_CHANNEL_1)) {
+        vdec_error = VDEC_ERR_CHANNEL;      /* Channel error */
+    }
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+    if (vdec_error == VDEC_OK) {
+        VDEC_Query(ch, q_sync_sep, q_agc, q_chroma_dec, q_digital_clamp);
+    }
+    return vdec_error;
+}   /* End of function R_VDEC_Query() */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdec/src/r_vdec_check_parameter.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,984 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_check_parameter.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver parameter check processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+#include    "r_vdec_check_parameter.h"
+
+
+#ifdef      R_VDEC_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Valid bit range */
+#define VDEC_CPARA_RANGE_0X00000001 (0x00000001u)
+#define VDEC_CPARA_RANGE_0X00000003 (0x00000003u)
+#define VDEC_CPARA_RANGE_0X00000007 (0x00000007u)
+#define VDEC_CPARA_RANGE_0X0000000F (0x0000000Fu)
+#define VDEC_CPARA_RANGE_0X0000001F (0x0000001Fu)
+#define VDEC_CPARA_RANGE_0X0000003F (0x0000003Fu)
+#define VDEC_CPARA_RANGE_0X0000007F (0x0000007Fu)
+#define VDEC_CPARA_RANGE_0X000000FF (0x000000FFu)
+#define VDEC_CPARA_RANGE_0X000001FF (0x000001FFu)
+#define VDEC_CPARA_RANGE_0X000003FF (0x000003FFu)
+#define VDEC_CPARA_RANGE_0X000007FF (0x000007FFu)
+#define VDEC_CPARA_RANGE_0X00001FFF (0x00001FFFu)
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static vdec_error_t NoiseReductionLPFCheckParam(const vdec_noise_rd_lpf_t * const p_noise_rd_lpf);
+static vdec_error_t SyncSlicerCheckParam(const vdec_sync_slicer_t * const p_sync_slicer);
+static vdec_error_t HorizontalAFCCheckParam(const vdec_horizontal_afc_t * const p_horizontal_afc);
+static vdec_error_t VerticalCountdownCheckParam(const vdec_vcount_down_t * const p_vcount_down);
+static vdec_error_t AgcPgaCheckParam(const vdec_agc_t * const p_agc);
+static vdec_error_t PeakLimiterControlCheckParam(const vdec_peak_limiter_t * const p_peak_limiter);
+static vdec_error_t OverRangeControlCheckParam(const vdec_over_range_t * const p_over_range);
+static vdec_error_t YcSeparationControlCheckParam(const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl);
+static vdec_error_t FilterTAPsCoefficientCheckParam(const vdec_chrfil_tap_t * const fil2_2d);
+static vdec_error_t ChromaDecodingControlCheckParam(const vdec_chrmdec_ctrl_t * const p_chrmdec_ctrl);
+static vdec_error_t BurstLockCheckParam(const vdec_burst_lock_t * const p_burst_lock);
+static vdec_error_t AccColorKillerCheckParam(const vdec_acc_t * const p_acc);
+
+
+/**************************************************************************//**
+ * @brief       Checks on input pin control
+ * @param[in]   vinsel                  : Input pin control
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_InitializeCheckParam (const vdec_adc_vinsel_t vinsel)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if ((vinsel != VDEC_ADC_VINSEL_VIN1) && (vinsel != VDEC_ADC_VINSEL_VIN2)) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_InitializeCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on active image period parameter
+ * @param[in]   param                   : Active image period parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_ActivePeriodCheckParam (const vdec_active_period_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Left end of input video signal capturing area */
+    if (((uint32_t)param->srcleft & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Top end of input video signal capturing area */
+    if (((uint32_t)param->srctop & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Height of input video signal capturing area */
+    if (((uint32_t)param->srcheight & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Width of input video signal capturing area */
+    if (((uint32_t)param->srcwidth & (uint32_t)(~VDEC_CPARA_RANGE_0X000007FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_ActivePeriodCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on sync separation parameter
+ * @param[in]   param                   : Sync separation parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_SyncSeparationCheckParam (const vdec_sync_separation_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Noise reduction LPF */
+    vdec_error = NoiseReductionLPFCheckParam(param->noise_rd_lpf);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Sync slicer */
+    vdec_error = SyncSlicerCheckParam(param->sync_slicer);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Horizontal AFC */
+    vdec_error = HorizontalAFCCheckParam(param->horizontal_afc);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Vertical countdown */
+    vdec_error = VerticalCountdownCheckParam(param->vcount_down);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* AGC / PGA */
+    vdec_error = AgcPgaCheckParam(param->agc);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Peak limiter control */
+    vdec_error = PeakLimiterControlCheckParam(param->peak_limiter);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_SyncSeparationCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on Y/C separation parameter
+ * @param[in]   param                   : Y/C separation parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_YcSeparationCheckParam (const vdec_yc_separation_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Over-range control */
+    vdec_error = OverRangeControlCheckParam(param->over_range);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Y/C separation control */
+    vdec_error = YcSeparationControlCheckParam(param->yc_sep_ctrl);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient */
+    vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_wa);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient */
+    vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_wb);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter TAP coefficient */
+    vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_na);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Two-dimensional cascade narrowband (SECAMDB) filter TAP coefficient */
+    vdec_error = FilterTAPsCoefficientCheckParam(param->fil2_2d_nb);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_YcSeparationCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on chroma decoding parameter
+ * @param[in]   param                   : Chroma decoding parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_ChromaDecodingCheckParam (const vdec_chroma_decoding_t * const param)
+{
+    vdec_tint_ry_t    * p_tint_ry;
+    vdec_error_t        vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Chroma decoding control */
+    vdec_error = ChromaDecodingControlCheckParam(param->chrmdec_ctrl);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* Burst lock */
+    vdec_error = BurstLockCheckParam(param->burst_lock);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* ACC/color killer */
+    vdec_error = AccColorKillerCheckParam(param->acc);
+    if (vdec_error != VDEC_OK) {
+        goto END;
+    }
+    /* TINT/R-Y axis correction (only valid for NTSC/PAL) */
+    p_tint_ry = param->tint_ry;
+    if (p_tint_ry != NULL) {
+        /* Fine adjustment of R-Y demodulation axis and hue adjustment level */
+        if ((((uint32_t)p_tint_ry->tintsub & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+                (((uint32_t)p_tint_ry->tintmain & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_ChromaDecodingCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on digital clamp parameter
+ * @param[in]   param                   : Digital clamp parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_DigitalClampCheckParam (const vdec_degital_clamp_t * const param)
+{
+    vdec_pedestal_clamp_t     * p_pedestal_clamp;
+    vdec_center_clamp_t       * p_center_clamp;
+    vdec_noise_det_t          * p_noise_det;
+    vdec_error_t                vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Digital clamp response speed */
+    if (((uint32_t)param->dcpresponse & (uint32_t)(~VDEC_CPARA_RANGE_0X00000007)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Digital clamp start line (in 1-line units) */
+    if (((uint32_t)param->dcpstart & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Digital clamp end line (in 1-line units) */
+    if (((uint32_t)param->dcpend & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Digital clamp pulse width */
+    if (((uint32_t)param->dcpwidth & (uint32_t)(~VDEC_CPARA_RANGE_0X0000007F)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+
+    /* Pedestal clamp */
+    p_pedestal_clamp = param->pedestal_clamp;
+    if (p_pedestal_clamp != NULL) {
+        /* Clamp offset level (Y signal) */
+        if (((uint32_t)p_pedestal_clamp->blanklevel_y & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Digital clamp pulse horizontal start position (Y signal) */
+        if (((uint32_t)p_pedestal_clamp->dcppos_y & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+    /* Center clamp */
+    p_center_clamp = param->center_clamp;
+    if (p_center_clamp != NULL) {
+        /* Clamp offset level (Cb signal) */
+        if (((uint32_t)p_center_clamp->blanklevel_cb & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Clamp offset level (Cr signal) */
+        if (((uint32_t)p_center_clamp->blanklevel_cr & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Digital clamp pulse horizontal start position (Cb/Cr signal) */
+        if (((uint32_t)p_center_clamp->dcppos_c & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+    /* Noise detection */
+    p_noise_det = param->noise_det;
+    if (p_noise_det != NULL) {
+        /* Video signal for autocorrelation function */
+        if (p_noise_det->acfinput >= VDEC_ACFINPUT_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Delay time for autocorrelation function calculation */
+        if (((uint32_t)p_noise_det->acflagtime & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Smoothing parameter of autocorrelation function data */
+        if (((uint32_t)p_noise_det->acffilter & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_DigitalClampCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on output adjustment parameter
+ * @param[in]   param                   : Output adjustment parameter
+ * @retval      Error code
+ *****************************************************************************/
+vdec_error_t VDEC_OutputCheckParam (const vdec_output_t * const param)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (param == NULL) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Y signal gain coefficient */
+    if (((uint32_t)param->y_gain2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Cb signal gain coefficient */
+    if (((uint32_t)param->cb_gain2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+    /* Cr signal gain coefficient */
+    if (((uint32_t)param->cr_gain2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+        vdec_error = VDEC_ERR_PARAM;
+        goto END;
+    }
+END:
+    return vdec_error;
+}   /* End of function VDEC_OutputCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on noise reduction LPF parameter
+ * @param[in]   p_noise_rd_lpf          : Noise reduction LPF parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t NoiseReductionLPFCheckParam (const vdec_noise_rd_lpf_t * const p_noise_rd_lpf)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Noise reduction LPF */
+    if (p_noise_rd_lpf != NULL) {
+        /* LPF cutoff frequency before vertical sync separation */
+        if (p_noise_rd_lpf->lpfvsync >= VDEC_LPF_VSYNC_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* LPF cutoff frequency before horizontal sync separation */
+        if (p_noise_rd_lpf->lpfhsync >= VDEC_LPF_HSYNC_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function NoiseReductionLPFCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on auto level control sync slicer parameter
+ * @param[in]   p_sync_slicer           : Auto level control sync slicer parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t SyncSlicerCheckParam (const vdec_sync_slicer_t * const p_sync_slicer)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Sync slicer */
+    if (p_sync_slicer != NULL) {
+        /* Reference level operation speed control for composite sync separation (for Hsync signal) */
+        if (p_sync_slicer->velocityshift_h >= VDEC_VELOCITY_SHIFT_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Auto-slice level setting for composite sync separator circuit (for Hsync signal) */
+        if (p_sync_slicer->slicermode_h >= VDEC_SLICE_MODE_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Auto-slice level setting for composite sync separation circuit (for Vsync signal) */
+        if (p_sync_slicer->slicermode_v >= VDEC_SLICE_MODE_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+           and min ratio of horizontal cycle to horizontal sync signal pulse width (for Hsync signal) */
+        if ((((uint32_t)p_sync_slicer->syncmaxduty_h & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+                (((uint32_t)p_sync_slicer->syncminduty_h & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Clipping level */
+        if (p_sync_slicer->ssclipsel >= VDEC_CLIP_LV_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Slice level for composite sync signal separation (for Hsync signal) */
+        if (((uint32_t)p_sync_slicer->csyncslice_h & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+           and min ratio of horizontal cycle to horizontal sync signal pulse width (for Vsync signal) */
+        if ((((uint32_t)p_sync_slicer->syncmaxduty_v & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+                (((uint32_t)p_sync_slicer->syncminduty_v & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Threshold for vertical sync separation */
+        if (((uint32_t)p_sync_slicer->vsyncslice & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Slice level for composite sync signal separation (for Vsync signal) */
+        if (((uint32_t)p_sync_slicer->csyncslice_v & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function SyncSlicerCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on horizontal AFC parameter
+ * @param[in]   p_horizontal_afc        : Horizontal AFC parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t HorizontalAFCCheckParam (const vdec_horizontal_afc_t * const p_horizontal_afc)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Horizontal AFC */
+    if (p_horizontal_afc != NULL) {
+        /* Horizontal AFC loop gain */
+        if (((uint32_t)p_horizontal_afc->hafcgain & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Horizontal AFC center oscillation frequency */
+        if (((uint32_t)p_horizontal_afc->hafcgain & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Start line of horizontal AFC normal operation */
+        if (((uint32_t)p_horizontal_afc->hafcstart & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Maximum oscillation frequency of horizontal AFC */
+        if (((uint32_t)p_horizontal_afc->hafcmax & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* End line of horizontal AFC normal operation */
+        if (((uint32_t)p_horizontal_afc->hafcend & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Horizontal AFC VBI period operating mode */
+        if (p_horizontal_afc->hafcmode >= VDEC_HAFCMD_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Min oscillation frequency of horizontal AFC */
+        if (((uint32_t)p_horizontal_afc->hafcmin & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Phase comparator feedback adjust for low sync signal lock stability */
+        if (p_horizontal_afc->phdet_div >= VDEC_PHDET_DIV_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function HorizontalAFCCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on vertical count-down parameter
+ * @param[in]   p_vcount_down           : Vertical count-down parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t VerticalCountdownCheckParam (const vdec_vcount_down_t * const p_vcount_down)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Vertical countdown */
+    if (p_vcount_down != NULL) {
+        /* Vertical countdown center oscillation frequency */
+        if (p_vcount_down->vcddefault >= VDEC_VCD_FRQ_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Vertical countdown sync area */
+        if (((uint32_t)p_vcount_down->vcdwindow & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Vertical countdown minimum oscillation frequency */
+        if (((uint32_t)p_vcount_down->vcdoffset & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function VerticalCountdownCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on AGC/PGA parameter
+ * @param[in]   p_agc                   : AGC/PGA parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t AgcPgaCheckParam (const vdec_agc_t * const p_agc)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* AGC / PGA */
+    if (p_agc != NULL) {
+        /* AGC response speed */
+        if (((uint32_t)p_agc->agcresponse & (uint32_t)(~VDEC_CPARA_RANGE_0X00000007)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Sync signal reference amplitude */
+        if (((uint32_t)p_agc->agclevel & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* AGC gain adjustment accuracy */
+        if (((uint32_t)p_agc->agcprecis & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* PGA gain */
+        if (((uint32_t)p_agc->pga_gain & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function AgcPgaCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on peak limiter control parameter
+ * @param[in]   p_peak_limiter          : Peak limiter control parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t PeakLimiterControlCheckParam (const vdec_peak_limiter_t * const p_peak_limiter)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Peak limiter control */
+    if (p_peak_limiter != NULL) {
+        /* Peak luminance value to operate peak limiter */
+        if (p_peak_limiter->peaklevel >= VDEC_PEAKLV_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+
+        /* Response speed with peak limiter gain decreased */
+        if (((uint32_t)p_peak_limiter->peakattack & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Response speed with peak limiter gain increased */
+        if (((uint32_t)p_peak_limiter->peakrelease & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Maximum compression rate of peak limiter */
+        if (p_peak_limiter->peakratio >= VDEC_PEAKRATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Allowable number of overflowing pixels */
+        if (((uint32_t)p_peak_limiter->maxpeaksamples & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function PeakLimiterControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on over-range control parameter
+ * @param[in]   p_over_range            : Over-range control parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t OverRangeControlCheckParam (const vdec_over_range_t * const p_over_range)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Over-range control */
+    if (p_over_range != NULL) {
+        /* A/D over-threshold level (between levels 0 and 1) */
+        if (((uint32_t)p_over_range->radj_o_level0 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* A/D under-threshold level (between levels 2 and 3) */
+        if (((uint32_t)p_over_range->radj_u_level0 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* A/D over-threshold level (between levels 1 and 2) */
+        if (((uint32_t)p_over_range->radj_o_level1 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* A/D under-threshold level (between levels 1 and 2) */
+        if (((uint32_t)p_over_range->radj_u_level1 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* A/D over-threshold level (between levels 2 and 3) */
+        if (((uint32_t)p_over_range->radj_o_level2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* A/D under-threshold level (between levels 0 and 1) */
+        if (((uint32_t)p_over_range->radj_u_level2 & (uint32_t)(~VDEC_CPARA_RANGE_0X000003FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function OverRangeControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on Y/C separation control parameter
+ * @param[in]   p_yc_sep_ctrl           : Y/C separation control parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t YcSeparationControlCheckParam (const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Y/C separation control */
+    if (p_yc_sep_ctrl != NULL) {
+        /* Two-dimensional Y/C separation filter select coefficient (K15, K13, and K11) */
+        if ((((uint32_t)p_yc_sep_ctrl->k15 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k13 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k11 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Two-dimensional Y/C separation filter select coefficient (K16, K14, and K12) */
+        if ((((uint32_t)p_yc_sep_ctrl->k16 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k14 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k12 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Two-dimensional Y/C separation filter select coefficient (K22A and K21A) */
+        if ((((uint32_t)p_yc_sep_ctrl->k22a & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k21a & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Two-dimensional Y/C separation filter select coefficient (K22B and K21B) */
+        if ((((uint32_t)p_yc_sep_ctrl->k22b & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k21b & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Two-dimensional Y/C separation filter select coefficient (K23B, K23A, and K24) */
+        if ((((uint32_t)p_yc_sep_ctrl->k23b & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k23a & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) ||
+                (((uint32_t)p_yc_sep_ctrl->k24 & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Mixing ratio of signal after passing horizontal filter
+          to signal after passing former-stage horizontal filter */
+        if (p_yc_sep_ctrl->hsel_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Mixing ratio of signal after passing vertical filter
+           to signal after passing former-stage horizontal/vertical filter */
+        if (p_yc_sep_ctrl->vsel_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Mixing ratio of signal after passing horizontal/vertical filter
+           to signal after passing former-stage horizontal/vertical filter */
+        if (p_yc_sep_ctrl->hvsel_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Vertical luminance detection level for correlation detection filter */
+        if (((uint32_t)p_yc_sep_ctrl->v_y_level & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+
+        /* Mixing ratio of c signal after passing horizontal/vertical adaptive filter
+           to signal after passing correlation detection filter */
+        if (p_yc_sep_ctrl->det2_mix_c >= VDEC_FILMIX_RATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Mixing ratio of C signal for Y generation after passing
+           horizontal/vertical adaptive filter to signal after passing correlation */
+        if (p_yc_sep_ctrl->det2_mix_y >= VDEC_FILMIX_RATIO_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Two-dimensional cascade/TAKE-OFF filter mode select */
+        if (p_yc_sep_ctrl->fil2_mode_2d >= VDEC_2DFIL_MDSEL_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function YcSeparationControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on chroma filter TAP coefficient for Y/C separation
+ * @param[in]   fil2_2d                 : Chroma filter TAP coefficient for Y/C separation
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t FilterTAPsCoefficientCheckParam (const vdec_chrfil_tap_t * const fil2_2d)
+{
+    int32_t             tap_coef;
+    const uint16_t    * taps;
+    vdec_error_t        vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    if (fil2_2d != NULL) {
+        taps = fil2_2d->fil2_2d_f;
+        for (tap_coef = 0; tap_coef < VDEC_CHRFIL_TAPCOEF_NUM; tap_coef++) {
+            if (((uint32_t)*taps & (uint32_t)(~VDEC_CPARA_RANGE_0X00001FFF)) != 0u) {
+                vdec_error = VDEC_ERR_PARAM;
+                goto END;
+            }
+            taps++;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function FilterTAPsCoefficientCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on color system detection parameter
+ * @param[in]   p_chrmdec_ctrl          : Color system detection parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t ChromaDecodingControlCheckParam (const vdec_chrmdec_ctrl_t * const p_chrmdec_ctrl)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Chroma decoding control */
+    if (p_chrmdec_ctrl != NULL) {
+        /* Default color system */
+        if (p_chrmdec_ctrl->defaultsys >= VDEC_COL_SYS_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Luminance signal delay adjustment */
+        if (((uint32_t)p_chrmdec_ctrl->lumadelay & (uint32_t)(~VDEC_CPARA_RANGE_0X0000001F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Averaging processing for pre-demodulated line */
+        if ((p_chrmdec_ctrl->demodmode != VDEC_DEMOD_MD_NO) && (p_chrmdec_ctrl->demodmode != VDEC_DEMOD_MD_PAL)) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function ChromaDecodingControlCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on BCO parameter
+ * @param[in]   p_burst_lock            : BCO parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t BurstLockCheckParam (const vdec_burst_lock_t * const p_burst_lock)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* Burst lock */
+    if (p_burst_lock != NULL) {
+        /* Burst lock PLL lock range */
+        if (p_burst_lock->lockrange >= VDEC_LOCK_RANGE_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Burst lock PLL loop gain */
+        if (((uint32_t)p_burst_lock->loopgain & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Level for burst lock PLL to re-search free-run frequency */
+        if (((uint32_t)p_burst_lock->locklimit & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* burst gate pulse position check */
+        if (((uint32_t)p_burst_lock->bgpcheck & (uint32_t)(~VDEC_CPARA_RANGE_0X00000001)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* burst gate pulse width */
+        if (((uint32_t)p_burst_lock->bgpwidth & (uint32_t)(~VDEC_CPARA_RANGE_0X0000007F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* burst gate pulse start position */
+        if (((uint32_t)p_burst_lock->bgpstart & (uint32_t)(~VDEC_CPARA_RANGE_0X000000FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function BurstLockCheckParam() */
+
+/**************************************************************************//**
+ * @brief       Checks on ACC and color killer parameter
+ * @param[in]   p_acc                   : ACC and color killer parameter
+ * @retval      Error code
+ *****************************************************************************/
+static vdec_error_t AccColorKillerCheckParam (const vdec_acc_t * const p_acc)
+{
+    vdec_error_t vdec_error;
+
+    vdec_error = VDEC_OK;
+
+    /* ACC/color killer */
+    if (p_acc != NULL) {
+        /* Maximum ACC Gain */
+        if (p_acc->accmaxgain >= VDEC_ACC_MAX_GAIN_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* ACC reference color burst amplitude */
+        if (((uint32_t)p_acc->acclevel & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Chroma manual gain (sub) */
+        if (p_acc->chromasubgain >= VDEC_CHRM_SB_GAIN_NUM) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Chroma manual gain (main) */
+        if (((uint32_t)p_acc->chromamaingain & (uint32_t)(~VDEC_CPARA_RANGE_0X000001FF)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* ACC response speed */
+        if (((uint32_t)p_acc->accresponse & (uint32_t)(~VDEC_CPARA_RANGE_0X00000003)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* ACC gain adjustment accuracy */
+        if (((uint32_t)p_acc->accprecis & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* Color killer operation start point */
+        if (((uint32_t)p_acc->killerlevel & (uint32_t)(~VDEC_CPARA_RANGE_0X0000003F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+        /* The offset level to turn off the color killer */
+        if (((uint32_t)p_acc->killeroffset & (uint32_t)(~VDEC_CPARA_RANGE_0X0000000F)) != 0u) {
+            vdec_error = VDEC_ERR_PARAM;
+            goto END;
+        }
+    }
+END:
+    return vdec_error;
+}   /* End of function AccColorKillerCheckParam() */
+
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdec/src/r_vdec_check_parameter.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,67 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_check_parameter.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver parameter check definitions
+******************************************************************************/
+
+#ifndef R_VDEC_CHECK_PARAMETER_H
+#define R_VDEC_CHECK_PARAMETER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+
+
+#ifdef      R_VDEC_CHECK_PARAMETERS
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+vdec_error_t VDEC_InitializeCheckParam(const vdec_adc_vinsel_t vinsel);
+vdec_error_t VDEC_ActivePeriodCheckParam(const vdec_active_period_t * const param);
+vdec_error_t VDEC_SyncSeparationCheckParam(const vdec_sync_separation_t * const param);
+vdec_error_t VDEC_YcSeparationCheckParam(const vdec_yc_separation_t * const param);
+vdec_error_t VDEC_ChromaDecodingCheckParam(const vdec_chroma_decoding_t * const param);
+vdec_error_t VDEC_DigitalClampCheckParam(const vdec_degital_clamp_t * const param);
+vdec_error_t VDEC_OutputCheckParam(const vdec_output_t * const param);
+#endif      /* R_VDEC_CHECK_PARAMETERS */
+
+#endif  /* R_VDEC_CHECK_PARAMETER_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdec/src/r_vdec_register.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,978 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_register.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver register setup processing
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+#include    "r_vdec_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* shift value */
+#define     VEDC_REG_SHIFT_15            (15u)
+#define     VEDC_REG_SHIFT_14            (14u)
+#define     VEDC_REG_SHIFT_13            (13u)
+#define     VEDC_REG_SHIFT_12            (12u)
+#define     VEDC_REG_SHIFT_11            (11u)
+#define     VEDC_REG_SHIFT_10            (10u)
+#define     VEDC_REG_SHIFT_9             (9u)
+#define     VEDC_REG_SHIFT_8             (8u)
+#define     VEDC_REG_SHIFT_6             (6u)
+#define     VEDC_REG_SHIFT_5             (5u)
+#define     VEDC_REG_SHIFT_4             (4u)
+#define     VEDC_REG_SHIFT_2             (2u)
+#define     VEDC_REG_SHIFT_1             (1u)
+
+/* bit set pattern */
+#define     VDEC_REG_SET_0X8000         (0x8000u)
+#define     VDEC_REG_SET_0X4000         (0x4000u)
+#define     VDEC_REG_SET_0X2000         (0x2000u)
+#define     VDEC_REG_SET_0X1000         (0x1000u)
+#define     VDEC_REG_SET_0X0800         (0x0800u)
+#define     VDEC_REG_SET_0X0100         (0x0100u)
+#define     VDEC_REG_SET_0X0080         (0x0080u)
+#define     VDEC_REG_SET_0X0020         (0x0020u)
+#define     VDEC_REG_SET_0X0010         (0x0010u)
+#define     VDEC_REG_SET_0X0008         (0x0008u)
+#define     VDEC_REG_SET_0X0004         (0x0004u)
+#define     VDEC_REG_SET_0X0002         (0x0002u)
+#define     VDEC_REG_SET_0X0001         (0x0001u)
+
+/* bit mask pattern */
+#define     VDEC_REG_BIT_MASK_0X8000    (0x8000u)
+#define     VDEC_REG_BIT_MASK_0X4000    (0x4000u)
+#define     VDEC_REG_BIT_MASK_0X2000    (0x2000u)
+#define     VDEC_REG_BIT_MASK_0X1000    (0x1000u)
+#define     VDEC_REG_BIT_MASK_0X0800    (0x0800u)
+#define     VDEC_REG_BIT_MASK_0X0400    (0x0400u)
+#define     VDEC_REG_BIT_MASK_0X0200    (0x0200u)
+#define     VDEC_REG_BIT_MASK_0X0100    (0x0100u)
+
+/* register mask value */
+#define     VDEC_REG_MASK_0X03FF        (0x03FFu) /* mask vdec_reg->syncssr  */
+#define     VDEC_REG_MASK_0XFF1F        (0xFF1Fu) /* mask vdec_reg->ycscr7   */
+#define     VDEC_REG_MASK_0XF3FF        (0xF3FFu) /* mask vdec_reg->hafccr1  */
+#define     VDEC_REG_MASK_0X83FF        (0x83FFu) /* mask vdec_reg->dcpcr1   */
+#define     VDEC_REG_MASK_0X01FF        (0x01FFu) /* mask vdec_reg->ycscr11  */
+#define     VDEC_REG_MASK_0X1C00        (0x1C00u) /* mask vdec_reg->dcpcr9   */
+#define     VDEC_REG_MASK_0X1F00        (0x1F00u) /* mask vdec_reg->pgacr    */
+#define     VDEC_REG_MASK_0X3F00        (0x3F00u) /* mask vdec_reg->agccr2   */
+#define     VDEC_REG_MASK_0X0007        (0x0007u) /* mask vdec_reg->rgorcr7  */
+#define     VDEC_REG_MASK_0XF800        (0xF800u) /* mask vdec_reg->ycscr8   */
+#define     VDEC_REG_MASK_0XFC00        (0xFC00u) /* mask vdec_reg->synscr1  */
+#define     VDEC_REG_MASK_0X00FF        (0x00FFu) /* mask vdec_reg->synscr1  */
+#define     VDEC_REG_MASK_0X0003        (0x0003u) /* mask vdec_reg->cromasr1 */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void NoiseReductionLPF(
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_noise_rd_lpf_t   * const p_noise_rd_lpf);
+static void SyncSlicer(const vdec_reg_address_t * const vdec_reg, const vdec_sync_slicer_t * const p_sync_slicer);
+static void HorizontalAFC(
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_horizontal_afc_t * const p_horizontal_afc);
+static void VerticalCountdown(
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_vcount_down_t    * const p_vcount_down);
+static void AgcPga(const vdec_reg_address_t * const vdec_reg, const vdec_agc_t * const p_agc);
+static void PeakLimiterControl(
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_peak_limiter_t   * const p_peak_limiter);
+static void OverRangeControl(const vdec_reg_address_t * const vdec_reg, const vdec_over_range_t * const p_over_range);
+static void YcSeparationControl(
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_yc_sep_ctrl_t    * const p_yc_sep_ctrl);
+static void FilterTAPsCoefficient(
+    volatile uint16_t       * const   * fil_reg_address,
+    const vdec_chrfil_tap_t * const     fil2_2d);
+
+
+/**************************************************************************//**
+ * @brief       Sets registers for initialization
+ * @param[in]   ch                      : Channel
+ * @param[in]   vinsel                  : Input pin control
+ * @retval      None
+ *****************************************************************************/
+void VDEC_Initialize (const vdec_channel_t ch, const vdec_adc_vinsel_t vinsel)
+{
+    const vdec_reg_address_t  * vdec_reg;
+    uint16_t                    reg_data;
+
+    vdec_reg = &vdec_reg_address[ch];
+
+    /* Input pin control */
+    if (vinsel == VDEC_ADC_VINSEL_VIN1) {
+        reg_data            = (uint16_t)((uint32_t)*(vdec_reg->adccr2) & (~0x0001u));
+        *(vdec_reg->adccr2) = reg_data;
+    } else {
+        reg_data            = (uint16_t)((uint32_t)*(vdec_reg->adccr2) | (0x0001u));
+        *(vdec_reg->adccr2) = reg_data;
+    }
+    return;
+}   /* End of function VDEC_Initialize() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for active image period
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Active image period parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_ActivePeriod (const vdec_channel_t ch, const vdec_active_period_t * const param)
+{
+    const vdec_reg_address_t * vdec_reg;
+
+    vdec_reg = &vdec_reg_address[ch];
+
+    /* Left end of input video signal capturing area */
+    *(vdec_reg->tgcr1) = param->srcleft;
+    /* Top end of input video signal capturing area
+       and height of input video signal capturing area */
+    *(vdec_reg->tgcr2) = (uint16_t)(((uint32_t)param->srctop << VEDC_REG_SHIFT_10) | (uint32_t)param->srcheight);
+    /* Width of input video signal capturing area */
+    *(vdec_reg->tgcr3) = param->srcwidth;
+
+    return;
+}   /* End of function VDEC_ActivePeriod() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for sync separation
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Sync separation parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_SyncSeparation (const vdec_channel_t ch, const vdec_sync_separation_t * const param)
+{
+    const vdec_reg_address_t  * vdec_reg;
+
+    vdec_reg            = &vdec_reg_address[ch];
+
+    /* Noise reduction LPF */
+    NoiseReductionLPF(vdec_reg, param->noise_rd_lpf);
+    /* Auto level control sync slicer */
+    SyncSlicer(vdec_reg, param->sync_slicer);
+    /* Horizontal AFC */
+    HorizontalAFC(vdec_reg, param->horizontal_afc);
+    /* Vertical count-down */
+    VerticalCountdown(vdec_reg, param->vcount_down);
+    /* AGC/PGA */
+    AgcPga(vdec_reg, param->agc);
+    /* Peak limiter control */
+    PeakLimiterControl(vdec_reg, param->peak_limiter);
+
+    return;
+}   /* End of function VDEC_SyncSeparation() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for Y/C separation
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Y/C separation parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_YcSeparation (const vdec_channel_t ch, const vdec_yc_separation_t * const param)
+{
+    const vdec_reg_address_t  * vdec_reg;
+
+    vdec_reg        = &vdec_reg_address[ch];
+
+    /* Over-range control */
+    OverRangeControl(vdec_reg, param->over_range);
+    /* Y/C separation control */
+    YcSeparationControl(vdec_reg, param->yc_sep_ctrl);
+
+    /* Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient */
+    FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctwa_f, param->fil2_2d_wa);
+    /* Two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient */
+    FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctwb_f, param->fil2_2d_wb);
+    /* Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter TAP coefficient */
+    FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctna_f, param->fil2_2d_na);
+    /* Two-dimensional cascade narrowband (SECAMDB) filter TAP coefficient */
+    FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctnb_f, param->fil2_2d_nb);
+
+    return;
+}   /* End of function VDEC_YcSeparation() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for chroma decoding
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Chroma decoding parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_ChromaDecoding (const vdec_channel_t ch, const vdec_chroma_decoding_t * const param)
+{
+    const vdec_reg_address_t  * vdec_reg;
+    vdec_chrmdec_ctrl_t       * p_chrmdec_ctrl;
+    vdec_burst_lock_t         * p_burst_lock;
+    vdec_acc_t                * p_acc;
+    vdec_tint_ry_t            * p_tint_ry;
+    uint32_t                    reg_data;
+
+    vdec_reg        = &vdec_reg_address[ch];
+    p_chrmdec_ctrl  = param->chrmdec_ctrl;
+    p_burst_lock    = param->burst_lock;
+    p_acc           = param->acc;
+    p_tint_ry       = param->tint_ry;
+
+    /* Color system detection */
+    if (p_chrmdec_ctrl != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->btlcr) & (uint32_t)(~VDEC_REG_MASK_0X00FF);
+        /* Default color system */
+        reg_data   |= (uint32_t)p_chrmdec_ctrl->defaultsys << VEDC_REG_SHIFT_6;
+        /* NTSC-M detection control */
+        reg_data   |= (p_chrmdec_ctrl->nontsc358_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0020 : (uint32_t)0x0000u;
+        /* NTSC-4.43 detection control */
+        reg_data   |= (p_chrmdec_ctrl->nontsc443_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0010 : (uint32_t)0x0000u;
+        /* PAL-M detection control */
+        reg_data   |= (p_chrmdec_ctrl->nopalm_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0008 : (uint32_t)0x0000u;
+        /* PAL-N detection control */
+        reg_data   |= (p_chrmdec_ctrl->nopaln_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0004 : (uint32_t)0x0000u;
+        /* PAL-B, G, H, I, D detection control */
+        reg_data   |= (p_chrmdec_ctrl->nopal443_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0002 : (uint32_t)0x0000u;
+        /* SECAM detection control */
+        reg_data   |= (p_chrmdec_ctrl->nosecam_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0001 : (uint32_t)0x0000u;
+
+        *(vdec_reg->btlcr) = (uint16_t)reg_data;
+
+        /* Luminance signal delay adjustment */
+        reg_data    = (uint32_t)p_chrmdec_ctrl->lumadelay << VEDC_REG_SHIFT_4;
+        /* LPF for demodulated chroma */
+        reg_data   |= (p_chrmdec_ctrl->chromalpf == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0004;
+        /* Averaging processing for pre-demodulated line */
+        reg_data   |= (uint32_t)p_chrmdec_ctrl->demodmode;
+
+        *(vdec_reg->ycdcr) = (uint16_t)reg_data;
+    }
+    /* BCO */
+    if (p_burst_lock != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->btlcr) & (uint32_t)(~VDEC_REG_MASK_0XFC00);
+        /* Burst lock PLL lock range */
+        reg_data   |= (uint32_t)p_burst_lock->lockrange << VEDC_REG_SHIFT_14;
+        /* Burst lock PLL loop gain */
+        reg_data   |= (uint32_t)p_burst_lock->loopgain << VEDC_REG_SHIFT_12;
+        /* Level for burst lock PLL to re-search free-run frequency */
+        reg_data   |= (uint32_t)p_burst_lock->locklimit << VEDC_REG_SHIFT_10;
+
+        *(vdec_reg->btlcr) = (uint16_t)reg_data;
+
+        /* burst gate pulse position check */
+        reg_data    = (uint32_t)p_burst_lock->bgpcheck << VEDC_REG_SHIFT_15;
+        /* burst gate pulse width */
+        reg_data   |= (uint32_t)p_burst_lock->bgpwidth << VEDC_REG_SHIFT_8;
+        /* burst gate pulse start position */
+        reg_data   |= (uint32_t)p_burst_lock->bgpstart;
+
+        *(vdec_reg->btgpcr) = (uint16_t)reg_data;
+    }
+    /* ACC and color killer */
+    if (p_acc != NULL) {
+        /* ACC operating mode */
+        reg_data    = (p_acc->accmode == VDEC_ACC_MD_AUTO) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0800;
+        /* Maximum ACC Gain */
+        reg_data   |= (uint32_t)p_acc->accmaxgain << VEDC_REG_SHIFT_9;
+        /* ACC reference color burst amplitude */
+        reg_data   |= (uint32_t)p_acc->acclevel;
+        /* Color killer offset */
+        reg_data   |= (uint32_t)p_acc->killeroffset << VEDC_REG_SHIFT_12;
+
+        *(vdec_reg->acccr1) = (uint16_t)reg_data;
+
+        /* Chroma manual gain (sub) */
+        reg_data    = (uint32_t)p_acc->chromasubgain << VEDC_REG_SHIFT_9;
+        /* Chroma manual gain (main) */
+        reg_data   |= (uint32_t)p_acc->chromamaingain;
+
+        *(vdec_reg->acccr2) = (uint16_t)reg_data;
+
+        /* ACC response speed */
+        reg_data    = (uint32_t)p_acc->accresponse << VEDC_REG_SHIFT_14;
+        /* ACC gain adjustment accuracy */
+        reg_data   |= (uint32_t)p_acc->accprecis << VEDC_REG_SHIFT_8;
+        /* Forced color killer mode ON/OFF */
+        reg_data   |= (p_acc->killermode == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0080;
+        /* Color killer operation start point */
+        reg_data   |= (uint32_t)p_acc->killerlevel << VEDC_REG_SHIFT_1;
+
+        *(vdec_reg->acccr3) = (uint16_t)reg_data;
+    }
+    /* TINT correction/R-Y axis correction (only valid for NTSC/PAL) */
+    if (p_tint_ry != NULL) {
+        /* Fine adjustment of R-Y demodulation axis and hue adjustment level */
+        reg_data    = (uint32_t)p_tint_ry->tintsub << VEDC_REG_SHIFT_10;
+        reg_data   |= (uint32_t)p_tint_ry->tintmain;
+
+        *(vdec_reg->tintcr) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function VDEC_ChromaDecoding() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for digital clamp
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Digital clamp parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_DigitalClamp (const vdec_channel_t ch, const vdec_degital_clamp_t * const param)
+{
+    const vdec_reg_address_t  * vdec_reg;
+    vdec_pedestal_clamp_t     * p_pedestal_clamp;
+    vdec_center_clamp_t       * p_center_clamp;
+    vdec_noise_det_t          * p_noise_det;
+    uint32_t                    reg_data;
+
+    vdec_reg            = &vdec_reg_address[ch];
+    p_pedestal_clamp    = param->pedestal_clamp;
+    p_center_clamp      = param->center_clamp;
+    p_noise_det         = param->noise_det;
+
+    /* Digital clamp pulse position check */
+    reg_data = (uint32_t)*(vdec_reg->dcpcr1);
+    if (param->dcpcheck == VDEC_OFF) {
+        reg_data &= (uint32_t)(~VDEC_REG_SET_0X0800);
+    } else {
+        reg_data |= (uint32_t)VDEC_REG_SET_0X0800;
+    }
+    *(vdec_reg->dcpcr1) = (uint16_t)reg_data;
+
+    /* Digital clamp response speed */
+    *(vdec_reg->dcpcr3) = (uint16_t)((uint32_t)param->dcpresponse << VEDC_REG_SHIFT_12);
+    /* Digital clamp start line */
+    *(vdec_reg->dcpcr4) = (uint16_t)((uint32_t)param->dcpstart << VEDC_REG_SHIFT_10);
+    /* Digital clamp end line */
+    *(vdec_reg->dcpcr5) = (uint16_t)((uint32_t)param->dcpend << VEDC_REG_SHIFT_10);
+    /* Digital clamp pulse width */
+    *(vdec_reg->dcpcr6) = (uint16_t)((uint32_t)param->dcpwidth << VEDC_REG_SHIFT_8);
+
+    /* Pedestal clamp */
+    if (p_pedestal_clamp != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->dcpcr1) & (uint32_t)(~VDEC_REG_MASK_0X83FF);
+        /* Clamp level setting mode (Y signal) */
+        reg_data   |= (p_pedestal_clamp->dcpmode_y == VDEC_DCPMODE_MANUAL) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X8000;
+        /* Clamp offset level (Y signal) */
+        reg_data   |= (uint32_t)p_pedestal_clamp->blanklevel_y;
+
+        *(vdec_reg->dcpcr1) = (uint16_t)reg_data;
+
+        /* Digital clamp pulse horizontal start position (Y signal) */
+        *(vdec_reg->dcpcr7) = (uint16_t)((uint32_t)p_pedestal_clamp->dcppos_y << VEDC_REG_SHIFT_8);
+    }
+    /* Center clamp */
+    if (p_center_clamp != NULL) {
+        /* Clamp level setting mode (Cb/Cr signal) */
+        reg_data    = (p_center_clamp->dcpmode_c == VDEC_DCPMODE_MANUAL) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X8000;
+        /* Clamp offset level (Cb signal) */
+        reg_data   |= (uint32_t)p_center_clamp->blanklevel_cb << VEDC_REG_SHIFT_6;
+        /* Clamp offset level (Cr signal) */
+        reg_data   |= (uint32_t)p_center_clamp->blanklevel_cr;
+
+        *(vdec_reg->dcpcr2) = (uint16_t)reg_data;
+
+        /* Digital clamp pulse horizontal start position (Cb/Cr signal) */
+        *(vdec_reg->dcpcr8) = (uint16_t)((uint32_t)p_center_clamp->dcppos_c << VEDC_REG_SHIFT_8);
+    }
+    /* Noise detection */
+    if (p_noise_det != NULL) {
+        /* Video signal for autocorrelation function */
+        reg_data    = (uint32_t)p_noise_det->acfinput << VEDC_REG_SHIFT_12;
+        /* Delay time for autocorrelation function calculation */
+        reg_data   |= (uint32_t)p_noise_det->acflagtime << VEDC_REG_SHIFT_4;
+        /* Smoothing parameter of autocorrelation function data */
+        reg_data   |= (uint32_t)p_noise_det->acffilter;
+
+        *(vdec_reg->nsdcr) = (uint16_t)reg_data;
+    }
+    /* Clamp data hold processing (Y, Cb, Cr) OFF */
+    reg_data            = (uint32_t)*(vdec_reg->dcpcr9) & (uint32_t)(~VDEC_REG_MASK_0X1C00);
+    *(vdec_reg->dcpcr9) = (uint16_t)reg_data;
+
+    return;
+}   /* End of function VDEC_DigitalClamp() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for output adjustment
+ * @param[in]   ch                      : Channel
+ * @param[in]   param                   : Output adjustment parameter
+ * @retval      None
+ *****************************************************************************/
+void VDEC_Output (const vdec_channel_t ch, const vdec_output_t * const param)
+{
+    const vdec_reg_address_t * vdec_reg;
+
+    vdec_reg = &vdec_reg_address[ch];
+
+    /* Y, Cb and Cr signal gain coefficient */
+    *(vdec_reg->ygaincr)    = param->y_gain2;
+    *(vdec_reg->cbgaincr)   = param->cb_gain2;
+    *(vdec_reg->crgaincr)   = param->cr_gain2;
+
+    return;
+}   /* End of function VDEC_Output() */
+
+/**************************************************************************//**
+ * @brief       Query VDEC parameters
+ * @param[in]   ch                      : Channel
+ * @param[out]  q_sync_sep              : Sync separation parameters
+ * @param[out]  q_agc                   : Agc parameters
+ * @param[out]  q_chroma_dec            : Chroma decoding parameters
+ * @param[out]  q_digital_clamp         : Digital clamp parameters
+ * @retval      None
+ *****************************************************************************/
+void VDEC_Query (
+    const vdec_channel_t            ch,
+    vdec_q_sync_sep_t       * const q_sync_sep,
+    vdec_q_agc_t            * const q_agc,
+    vdec_q_chroma_dec_t     * const q_chroma_dec,
+    vdec_q_digital_clamp_t  * const q_digital_clamp)
+{
+    const vdec_reg_address_t  * vdec_reg;
+    uint32_t                    reg_value;
+
+    vdec_reg = &vdec_reg_address[ch];
+
+    /* Sync separation */
+    if (q_sync_sep != NULL) {
+        reg_value = (uint32_t)*(vdec_reg->vsyncsr);
+        /* Horizontal AFC lock detection result */
+        q_sync_sep->fhlock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X4000) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
+        /* Detection result of low S/N signal by sync separation */
+        q_sync_sep->isnoisy = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X2000) == 0u) ? VDEC_NO : VDEC_YES;
+        /* Speed detection result */
+        q_sync_sep->fhmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_FHMD_NORMAL :
+                             VDEC_FHMD_MULTIPLIED;
+        /* No-signal detection result */
+        q_sync_sep->nosignal_ = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_YES : VDEC_NO;
+        /* Vertical countdown lock detection result */
+        q_sync_sep->fvlock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0400) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
+        /* Vertical countdown oscillation mode */
+        q_sync_sep->fvmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0200) == 0u) ? VDEC_FVMD_50HZ :
+                             VDEC_FVMD_60HZ;
+        /* Interlace detection result */
+        q_sync_sep->interlaced = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0100) == 0u) ? VDEC_NO : VDEC_YES;
+        /* Vertical cycle measurement result */
+        q_sync_sep->fvcount = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+        /* Horizontal AFC oscillation cycle */
+        q_sync_sep->fhcount  = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X8000) == 0u) ? 0x0000u : (uint32_t)0x0001u;
+        q_sync_sep->fhcount |= (uint32_t)*(vdec_reg->hsyncsr) << VEDC_REG_SHIFT_1;
+
+        reg_value = (uint32_t)*(vdec_reg->syncssr);
+        /* Sync amplitude detection result during VBI period */
+        q_sync_sep->isreduced = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_NO : VDEC_YES;
+        /* Sync pulse amplitude detection result */
+        q_sync_sep->syncdepth = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X03FF);
+    }
+    /* Agc */
+    if (q_agc != NULL) {
+        reg_value = (uint32_t)*(vdec_reg->agccsr1);
+        /* Number of pixels which have larger luminance value than peak luminance limited by peak limiter */
+        q_agc->highsamples = (uint16_t)(reg_value >> VEDC_REG_SHIFT_8);
+        /* Number of overflowing pixels */
+        q_agc->peaksamples = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+
+        reg_value = (uint32_t)*(vdec_reg->agccsr2);
+        /* AGC convergence detection result */
+        if ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0100) == 0u) {
+            q_agc->agcconverge = (uint16_t)0x0000u;
+        } else {
+            q_agc->agcconverge = (uint16_t)0x0001u;
+        }
+        /* Current AGC gain value */
+        q_agc->agcgain = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+    }
+    /* Chroma decoding */
+    if (q_chroma_dec != NULL) {
+        reg_value = (uint32_t)*(vdec_reg->cromasr1);
+        /* Color system detection result */
+        q_chroma_dec->colorsys = (vdec_color_sys_t)(reg_value >> VEDC_REG_SHIFT_14);
+        /* Color sub-carrier frequency detection result */
+        q_chroma_dec->fscmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X2000) == 0u) ? VDEC_FSCMD_3_58 :
+                                VDEC_FSCMD_4_43;
+        /* Burst lock PLL lock state detection result */
+        q_chroma_dec->fsclock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
+        /* Color burst detection result */
+        q_chroma_dec->noburst_ = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_YES : VDEC_NO;
+        /* Current ACC gain value (sub) */
+        q_chroma_dec->accsubgain = (vdec_chrm_subgain_t)((reg_value >> VEDC_REG_SHIFT_9) &
+                                   (uint32_t)VDEC_REG_MASK_0X0003);
+        /* Current ACC gain value (main) */
+        q_chroma_dec->accmaingain = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X01FF);
+
+        reg_value = (uint32_t)*(vdec_reg->cromasr2);
+        /* SECAM detection result */
+        q_chroma_dec->issecam = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_NO : VDEC_YES;
+        /* PAL detection result */
+        q_chroma_dec->ispal = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_NO : VDEC_YES;
+        /* NTSC detection result */
+        q_chroma_dec->isntsc = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0400) == 0u) ? VDEC_NO : VDEC_YES;
+        /* Low S/N signal detection result by burst lock PLL */
+        q_chroma_dec->locklevel = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
+    }
+    /* Digital clamp */
+    if (q_digital_clamp != NULL) {
+        reg_value = (uint32_t)*(vdec_reg->dcpsr1);
+        /* Digital clamp subtraction value (Cb signal) */
+        q_digital_clamp->clamplevel_cb = (uint16_t)(reg_value >> VEDC_REG_SHIFT_10);
+        /* Digital clamp subtraction value (Y signal) */
+        q_digital_clamp->clamplevel_y = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X03FF);
+
+        /* Digital clamp subtraction value (Cr signal) */
+        q_digital_clamp->clamplevel_cr = (uint16_t)((uint32_t)*(vdec_reg->dcpsr2) >> VEDC_REG_SHIFT_10);
+
+        /* Noise autocorrelation strength at digital clamp pulse position */
+        q_digital_clamp->acfstrength = *(vdec_reg->nsdsr);
+    }
+    return;
+}   /* End of function VDEC_Query() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for noise reduction LPF
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_noise_rd_lpf          : Noise reduction LPF parameter
+ * @retval      None
+ *****************************************************************************/
+static void NoiseReductionLPF (
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_noise_rd_lpf_t   * const p_noise_rd_lpf)
+{
+    uint32_t reg_data;
+
+    /* Noise reduction LPF */
+    if (p_noise_rd_lpf != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->synscr1) & (uint32_t)(~VDEC_REG_MASK_0XFC00);
+        /* LPF cutoff frequency before vertical sync separation */
+        reg_data   |= (uint32_t)p_noise_rd_lpf->lpfvsync << VEDC_REG_SHIFT_13;
+        /* LPF cutoff frequency before horizontal sync separation */
+        reg_data   |= (uint32_t)p_noise_rd_lpf->lpfhsync << VEDC_REG_SHIFT_10;
+
+        *(vdec_reg->synscr1) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function NoiseReductionLPF() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for auto level control sync slicer
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_sync_slicer           : Auto level control sync slicer parameter
+ * @retval      None
+ *****************************************************************************/
+static void SyncSlicer (const vdec_reg_address_t * const vdec_reg, const vdec_sync_slicer_t * const p_sync_slicer)
+{
+    uint32_t reg_data;
+
+    /* Auto level control sync slicer */
+    if (p_sync_slicer != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->synscr1) & (uint32_t)(~VDEC_REG_MASK_0X00FF);
+        /* Reference level operation speed control for composite sync separation (for Hsync signal) */
+        reg_data   |= (uint32_t)p_sync_slicer->velocityshift_h << VEDC_REG_SHIFT_4;
+        /* Auto-slice level setting for composite sync separation circuit (for Hsync signal) */
+        reg_data   |= (uint32_t)p_sync_slicer->slicermode_h << VEDC_REG_SHIFT_2;
+        /* Auto-slice level setting for composite sync separation circuit (for Vsync signal) */
+        reg_data   |= (uint32_t)p_sync_slicer->slicermode_v;
+
+        *(vdec_reg->synscr1) = (uint16_t)reg_data;
+
+        /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+           and min ratio of horizontal cycle to horizontal sync signal pulse width (for Hsync signal) */
+        reg_data    = (uint32_t)p_sync_slicer->syncmaxduty_h << VEDC_REG_SHIFT_6;
+        reg_data   |= (uint32_t)p_sync_slicer->syncminduty_h;
+
+        *(vdec_reg->synscr2) = (uint16_t)reg_data;
+
+        /* Clipping level and slice level for composite sync signal separation (for Hsync signal) */
+        reg_data    = (uint32_t)p_sync_slicer->ssclipsel << VEDC_REG_SHIFT_10;
+        reg_data   |= (uint32_t)p_sync_slicer->csyncslice_h;
+
+        *(vdec_reg->synscr3) = (uint16_t)reg_data;
+
+        /* Max ratio of horizontal cycle to horizontal sync signal pulse width
+           and min ratio of horizontal cycle to horizontal sync signal pulse width (for Vsync signal) */
+        reg_data    = (uint32_t)p_sync_slicer->syncmaxduty_v << VEDC_REG_SHIFT_6;
+        reg_data   |= (uint32_t)p_sync_slicer->syncminduty_v;
+
+        *(vdec_reg->synscr4) = (uint16_t)reg_data;
+
+        /* Delays the separated vertical sync signal for 1/4 horizontal cycle */
+        reg_data    = (p_sync_slicer->vsyncdelay == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X8000;
+        /* Threshold for vertical sync separation */
+        reg_data   |= (uint32_t)p_sync_slicer->vsyncslice << VEDC_REG_SHIFT_10;
+        /* Slice level for composite sync signal separation (for Vsync signal) */
+        reg_data   |= (uint32_t)p_sync_slicer->csyncslice_v;
+
+        *(vdec_reg->synscr5) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function SyncSlicer() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for horizontal AFC
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_horizontal_afc        : Horizontal AFC parameter
+ * @retval      None
+ *****************************************************************************/
+static void HorizontalAFC (
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_horizontal_afc_t * const p_horizontal_afc)
+{
+    uint32_t reg_data;
+
+    /* Horizontal AFC */
+    if (p_horizontal_afc != NULL) {
+        reg_data    = (uint32_t)*(vdec_reg->hafccr1) & (uint32_t)(~VDEC_REG_MASK_0XF3FF);
+        /* Horizontal AFC loop gain */
+        reg_data   |= (uint32_t)p_horizontal_afc->hafcgain << VEDC_REG_SHIFT_12;
+        /* Horizontal AFC center oscillation frequency */
+        reg_data   |= (uint32_t)p_horizontal_afc->hafctyp;
+
+        *(vdec_reg->hafccr1) = (uint16_t)reg_data;
+
+        /* Start line of horizontal AFC normal operation
+           and Horizontal AFC forced double-speed oscillation (DOX2HOSC = 0, auto control) */
+        reg_data    = (uint32_t)p_horizontal_afc->hafcstart << VEDC_REG_SHIFT_12;
+        /* Disable of horizontal AFC double speed detection */
+        reg_data   |= (p_horizontal_afc->nox2hosc == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0800;
+        /* Maximum oscillation frequency of horizontal AFC */
+        reg_data   |= (uint32_t)p_horizontal_afc->hafcmax;
+
+        *(vdec_reg->hafccr2) = (uint16_t)reg_data;
+
+        /* End line of horizontal AFC normal operation */
+        reg_data    = (uint32_t)p_horizontal_afc->hafcend << VEDC_REG_SHIFT_12;
+        /* Horizontal AFC VBI period operating mode */
+        reg_data   |= (uint32_t)p_horizontal_afc->hafcmode << VEDC_REG_SHIFT_10;
+        /* Min oscillation frequency of horizontal AFC */
+        reg_data   |= (uint32_t)p_horizontal_afc->hafcmin;
+
+        *(vdec_reg->hafccr3) = (uint16_t)reg_data;
+
+        /* Forcible or LOWGAIN control */
+        reg_data    = (p_horizontal_afc->phdet_fix == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0010;
+        /* Phase comparator feedback adjust for low sync signal lock stability */
+        reg_data   |= (uint32_t)p_horizontal_afc->phdet_div;
+
+        *(vdec_reg->afcpfcr) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function HorizontalAFC() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for vertical count-down
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_vcount_down           : Vertical count-down parameter
+ * @retval      None
+ *****************************************************************************/
+static void VerticalCountdown (
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_vcount_down_t    * const p_vcount_down)
+{
+    uint32_t reg_data;
+
+    /* Vertical count-down */
+    if (p_vcount_down != NULL) {
+        /* Vertical countdown 50-Hz oscillation mode
+           and Vertical countdown free-run oscillation mode (VCDFREERUN = OFF) */
+        reg_data    = (p_vcount_down->novcd50_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X4000 : (uint32_t)0x0000u;
+        /* Vertical countdown 60-Hz (59.94-Hz) oscillation mode */
+        reg_data   |= (p_vcount_down->novcd60_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X2000 : (uint32_t)0x0000u;
+        /* Vertical countdown center oscillation frequency */
+        reg_data   |= (uint32_t)p_vcount_down->vcddefault << VEDC_REG_SHIFT_11;
+        /* Vertical countdown sync area */
+        reg_data   |= (uint32_t)p_vcount_down->vcdwindow << VEDC_REG_SHIFT_5;
+        /* Vertical countdown minimum oscillation frequency */
+        reg_data   |= (uint32_t)p_vcount_down->vcdoffset;
+
+        *(vdec_reg->vcdwcr1) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function VerticalCountdown() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for AGC/PGA
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_agc                   : AGC/PGA parameter
+ * @retval      None
+ *****************************************************************************/
+static void AgcPga (const vdec_reg_address_t * const vdec_reg, const vdec_agc_t * const p_agc)
+{
+    uint32_t reg_data;
+
+    /* AGC/PGA */
+    if (p_agc != NULL) {
+        /* A/D converter AGC ON/OFF control & PGA switch */
+        if (p_agc->agcmode == VDEC_OFF) {
+            reg_data            = (uint32_t)*(vdec_reg->pgacr) | (uint32_t)VDEC_REG_SET_0X2000;
+            *(vdec_reg->pgacr)  = (uint16_t)reg_data;
+            *(vdec_reg->adccr1) = (uint16_t)0u;
+        } else {
+            *(vdec_reg->adccr1) = (uint16_t)VDEC_REG_SET_0X0100;
+            reg_data            = (uint32_t)*(vdec_reg->pgacr) & (uint32_t)(~VDEC_REG_SET_0X2000);
+            *(vdec_reg->pgacr)  = (uint16_t)reg_data;
+        }
+        /* PGA gain */
+        reg_data    = (uint32_t)*(vdec_reg->pgacr) & (uint32_t)(~VDEC_REG_MASK_0X1F00);
+        reg_data   |= (uint32_t)p_agc->pga_gain << VEDC_REG_SHIFT_8;
+
+        *(vdec_reg->pgacr) = (uint16_t)reg_data;
+
+        /* PGA register update register */
+        *(vdec_reg->pga_update) = (uint16_t)1u;
+
+        /* Manual control of sync signal amplitude detection during VBI period */
+        reg_data    = (p_agc->doreduce == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X2000;
+        /* Control of sync signal amplitude detection during VBI period */
+        reg_data   |= (p_agc->noreduce_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X1000 : (uint32_t)0x0000u;
+        /* AGC response speed */
+        reg_data   |= (uint32_t)p_agc->agcresponse << VEDC_REG_SHIFT_9;
+        /* Sync signal reference amplitude */
+        reg_data   |= (uint32_t)p_agc->agclevel;
+
+        *(vdec_reg->agccr1) = (uint16_t)reg_data;
+
+        /* AGC gain adjustment accuracy */
+        reg_data    = (uint32_t)*(vdec_reg->agccr2) & (uint32_t)(~VDEC_REG_MASK_0X3F00);
+        reg_data   |= (uint32_t)p_agc->agcprecis << VEDC_REG_SHIFT_8;
+
+        *(vdec_reg->agccr2) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function AgcPga() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for peak limiter control
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_peak_limiter          : Peak limiter control parameter
+ * @retval      None
+ *****************************************************************************/
+static void PeakLimiterControl (
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_peak_limiter_t   * const p_peak_limiter)
+{
+    uint32_t reg_data;
+
+    /* Peak limiter control */
+    if (p_peak_limiter != NULL) {
+        /* Peak luminance value limited by peak limiter */
+        reg_data    = (uint32_t)p_peak_limiter->peaklevel << VEDC_REG_SHIFT_14;
+        /* Response speed with peak limiter gain decreased */
+        reg_data   |= (uint32_t)p_peak_limiter->peakattack << VEDC_REG_SHIFT_12;
+        /* Response speed with peak limiter gain increased */
+        reg_data   |= (uint32_t)p_peak_limiter->peakrelease << VEDC_REG_SHIFT_10;
+        /* Maximum compression rate of peak limiter */
+        reg_data   |= (uint32_t)p_peak_limiter->peakratio << VEDC_REG_SHIFT_8;
+        /* Allowable number of overflowing pixels */
+        reg_data   |= (uint32_t)p_peak_limiter->maxpeaksamples;
+
+        *(vdec_reg->pklimitcr) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function PeakLimiterControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for over-range control
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_over_range            : Over-range control parameter
+ * @retval      None
+ *****************************************************************************/
+static void OverRangeControl (const vdec_reg_address_t * const vdec_reg, const vdec_over_range_t * const p_over_range)
+{
+    uint32_t reg_data;
+
+    /* Over-range control */
+    if (p_over_range != NULL) {
+        /* A/D over-threshold level (between levels 0 and 1) */
+        *(vdec_reg->rgorcr1) = p_over_range->radj_o_level0;
+        /* A/D under-threshold level (between levels 2 and 3) */
+        *(vdec_reg->rgorcr2) = p_over_range->radj_u_level0;
+        /* A/D over-threshold level (between levels 1 and 2) */
+        *(vdec_reg->rgorcr3) = p_over_range->radj_o_level1;
+        /* A/D under-threshold level (between levels 1 and 2) */
+        *(vdec_reg->rgorcr4) = p_over_range->radj_u_level1;
+        /* A/D over-threshold level (between levels 2 and 3) */
+        *(vdec_reg->rgorcr5) = p_over_range->radj_o_level2;
+        /* A/D under-threshold level (between levels 0 and 1) */
+        *(vdec_reg->rgorcr6) = p_over_range->radj_u_level2;
+
+        reg_data    = (uint32_t)*(vdec_reg->rgorcr7) & (uint32_t)(~VDEC_REG_MASK_0X0007);
+        /* Over-range detection enable */
+        reg_data   |= (p_over_range->ucmp_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0004;
+        /* Under-range detection enable */
+        reg_data   |= (p_over_range->dcmp_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0002;
+        /* Horizontal enlargement of over/under-range level */
+        reg_data   |= (p_over_range->hwide_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)0x0001u;
+
+        *(vdec_reg->rgorcr7) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function OverRangeControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for Y/C separation control
+ * @param[in]   vdec_reg                : VDEC registers
+ * @param[in]   p_yc_sep_ctrl           : Y/C separation control parameter
+ * @retval      None
+ *****************************************************************************/
+static void YcSeparationControl (
+    const vdec_reg_address_t    * const vdec_reg,
+    const vdec_yc_sep_ctrl_t    * const p_yc_sep_ctrl)
+{
+    uint32_t reg_data;
+
+    /* Y/C separation control */
+    if (p_yc_sep_ctrl != NULL) {
+        /* Two-dimensional Y/C separation filter select coefficient (K15, K13, and K11) */
+        reg_data    = (uint32_t)p_yc_sep_ctrl->k15 << VEDC_REG_SHIFT_12;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k13 << VEDC_REG_SHIFT_6;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k11;
+
+        *(vdec_reg->ycscr3) = (uint16_t)reg_data;
+
+        /* Two-dimensional Y/C separation filter select coefficient (K16, K14, and K12) */
+        reg_data    = (uint32_t)p_yc_sep_ctrl->k16 << VEDC_REG_SHIFT_12;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k14 << VEDC_REG_SHIFT_6;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k12;
+
+        *(vdec_reg->ycscr4) = (uint16_t)reg_data;
+
+        /* Two-dimensional Y/C separation filter select coefficient (K22A and K21A) */
+        reg_data    = (uint32_t)p_yc_sep_ctrl->k22a << VEDC_REG_SHIFT_8;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k21a;
+
+        *(vdec_reg->ycscr5) = (uint16_t)reg_data;
+
+        /* Two-dimensional Y/C separation filter select coefficient (K22B and K21B) */
+        reg_data    = (uint32_t)p_yc_sep_ctrl->k22b << VEDC_REG_SHIFT_8;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k21b;
+
+        *(vdec_reg->ycscr6) = (uint16_t)reg_data;
+
+        /* Two-dimensional Y/C separation filter select coefficient (K23B, K23A, and K24) */
+        reg_data    = (uint32_t)*(vdec_reg->ycscr7) & (uint32_t)(~VDEC_REG_MASK_0XFF1F);
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k23b << VEDC_REG_SHIFT_12;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k23a << VEDC_REG_SHIFT_8;
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->k24;
+
+        *(vdec_reg->ycscr7) = (uint16_t)reg_data;
+
+        reg_data    = (uint32_t)*(vdec_reg->ycscr8) & (uint32_t)(~VDEC_REG_MASK_0XF800);
+        /* Latter-stage horizontal BPF select */
+        reg_data   |= (p_yc_sep_ctrl->hbpf_narrow == VDEC_LSTG_BPFSEL_BYPASS) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X8000;
+        /* Latter-stage horizontal/vertical BPF select */
+        reg_data   |= (p_yc_sep_ctrl->hvbpf_narrow == VDEC_LSTG_BPFSEL_BYPASS) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X4000;
+        /* Former-stage horizontal BPF select */
+        reg_data   |= (p_yc_sep_ctrl->hbpf1_9tap_on == VDEC_FSTG_BPFSEL_17TAP) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X2000;
+        /* Former-stage horizontal/vertical BPF select */
+        reg_data   |= (p_yc_sep_ctrl->hvbpf1_9tap_on == VDEC_FSTG_BPFSEL_17TAP) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X1000;
+        /* Horizontal filter and horizontal/vertical filter bandwidth switch signal */
+        reg_data   |= (p_yc_sep_ctrl->hfil_tap_sel == VDEC_HFIL_TAP_SEL_17TAP) ? (uint32_t)0x0000u :
+                      (uint32_t)VDEC_REG_SET_0X0800;
+
+        *(vdec_reg->ycscr8) = (uint16_t)reg_data;
+
+        /* Two-dimensional filter mixing select */
+        reg_data    = (p_yc_sep_ctrl->det2_on == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X8000;
+        /* Mixing ratio of signal after passing horizontal filter
+          to signal after passing former-stage horizontal filter */
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->hsel_mix_y << VEDC_REG_SHIFT_8;
+        /* Mixing ratio of signal after passing vertical filter
+           to signal after passing former-stage horizontal/vertical filter */
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->vsel_mix_y << VEDC_REG_SHIFT_4;
+        /* Mixing ratio of signal after passing horizontal/vertical filter
+           to signal after passing former-stage horizontal/vertical filter */
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->hvsel_mix_y;
+
+        *(vdec_reg->ycscr9) = (uint16_t)reg_data;
+
+        /* Vertical luminance detection level for correlation detection filter */
+        reg_data    = (uint32_t)*(vdec_reg->ycscr11) & (uint32_t)(~VDEC_REG_MASK_0X01FF);
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->v_y_level;
+
+        *(vdec_reg->ycscr11) = (uint16_t)reg_data;
+
+        if (p_yc_sep_ctrl->det2_on == VDEC_OFF) {
+            reg_data    = ((uint32_t)VDEC_FILMIX_RATIO_0 << VEDC_REG_SHIFT_12) |
+                          ((uint32_t)VDEC_FILMIX_RATIO_0 << VEDC_REG_SHIFT_8);
+        } else {
+            /* Mixing ratio of C signal after passing horizontal/vertical adaptive filter
+               to signal after passing correlation detection filter */
+            reg_data    = (uint32_t)p_yc_sep_ctrl->det2_mix_c << VEDC_REG_SHIFT_12;
+            /* Mixing ratio of C signal for Y generation after passing
+               horizontal/vertical adaptive filter to signal after passing correlation */
+            reg_data   |= (uint32_t)p_yc_sep_ctrl->det2_mix_y << VEDC_REG_SHIFT_8;
+        }
+        /* Two-dimensional cascade/TAKE-OFF filter mode select */
+        reg_data   |= (uint32_t)p_yc_sep_ctrl->fil2_mode_2d << VEDC_REG_SHIFT_2;
+        /* Two-dimensional cascade filter select */
+        reg_data   |= (p_yc_sep_ctrl->fil2_narrow_2d == VDEC_2D_FIL_SEL_BYPASS) ? (uint32_t)0x0000u :
+                      (uint32_t)0x0001u;
+
+        *(vdec_reg->ycscr12) = (uint16_t)reg_data;
+    }
+    return;
+}   /* End of function YcSeparationControl() */
+
+/**************************************************************************//**
+ * @brief       Sets registers for chroma filter TAP coefficient
+ * @param[in]   fil_reg_address         : 2D filter TAP coefficient registers
+ * @param[in]   fil2_2d                 : Chroma filter TAP coefficient for Y/C separation
+ * @retval      None
+ *****************************************************************************/
+static void FilterTAPsCoefficient (
+    volatile uint16_t       * const   * fil_reg_address,
+    const vdec_chrfil_tap_t * const     fil2_2d)
+{
+    int32_t             tap_coef;
+    volatile uint16_t * fil_reg;
+    const uint16_t    * taps;
+
+    if (fil2_2d != NULL) {
+        taps = fil2_2d->fil2_2d_f;
+        for (tap_coef = 0; tap_coef < VDEC_CHRFIL_TAPCOEF_NUM; tap_coef++) {
+            fil_reg = *fil_reg_address;
+            fil_reg_address++;
+            *fil_reg = *taps;
+            taps++;
+        }
+    }
+    return;
+}   /* End of function FilterTAPsCoefficient() */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdec/src/r_vdec_register.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,154 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_register.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver register setup definitions
+******************************************************************************/
+
+#ifndef R_VDEC_REGISTER_H
+#define R_VDEC_REGISTER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! VDEC register address list */
+typedef struct {
+    volatile uint16_t * adccr1;
+    volatile uint16_t * tgcr1;
+    volatile uint16_t * tgcr2;
+    volatile uint16_t * tgcr3;
+    volatile uint16_t * synscr1;
+    volatile uint16_t * synscr2;
+    volatile uint16_t * synscr3;
+    volatile uint16_t * synscr4;
+    volatile uint16_t * synscr5;
+    volatile uint16_t * hafccr1;
+    volatile uint16_t * hafccr2;
+    volatile uint16_t * hafccr3;
+    volatile uint16_t * vcdwcr1;
+    volatile uint16_t * dcpcr1;
+    volatile uint16_t * dcpcr2;
+    volatile uint16_t * dcpcr3;
+    volatile uint16_t * dcpcr4;
+    volatile uint16_t * dcpcr5;
+    volatile uint16_t * dcpcr6;
+    volatile uint16_t * dcpcr7;
+    volatile uint16_t * dcpcr8;
+    volatile uint16_t * nsdcr;
+    volatile uint16_t * btlcr;
+    volatile uint16_t * btgpcr;
+    volatile uint16_t * acccr1;
+    volatile uint16_t * acccr2;
+    volatile uint16_t * acccr3;
+    volatile uint16_t * tintcr;
+    volatile uint16_t * ycdcr;
+    volatile uint16_t * agccr1;
+    volatile uint16_t * agccr2;
+    volatile uint16_t * pklimitcr;
+    volatile uint16_t * rgorcr1;
+    volatile uint16_t * rgorcr2;
+    volatile uint16_t * rgorcr3;
+    volatile uint16_t * rgorcr4;
+    volatile uint16_t * rgorcr5;
+    volatile uint16_t * rgorcr6;
+    volatile uint16_t * rgorcr7;
+    volatile uint16_t * afcpfcr;
+    volatile uint16_t * rupdcr;
+    volatile uint16_t * vsyncsr;
+    volatile uint16_t * hsyncsr;
+    volatile uint16_t * dcpsr1;
+    volatile uint16_t * dcpsr2;
+    volatile uint16_t * nsdsr;
+    volatile uint16_t * cromasr1;
+    volatile uint16_t * cromasr2;
+    volatile uint16_t * syncssr;
+    volatile uint16_t * agccsr1;
+    volatile uint16_t * agccsr2;
+    volatile uint16_t * ycscr3;
+    volatile uint16_t * ycscr4;
+    volatile uint16_t * ycscr5;
+    volatile uint16_t * ycscr6;
+    volatile uint16_t * ycscr7;
+    volatile uint16_t * ycscr8;
+    volatile uint16_t * ycscr9;
+    volatile uint16_t * ycscr11;
+    volatile uint16_t * ycscr12;
+    volatile uint16_t * dcpcr9;
+    volatile uint16_t * ygaincr;
+    volatile uint16_t * cbgaincr;
+    volatile uint16_t * crgaincr;
+    volatile uint16_t * pga_update;
+    volatile uint16_t * pgacr;
+    volatile uint16_t * adccr2;
+} vdec_reg_address_t;
+
+/*! VDEC register address list (for 2D filter tap coefficient) */
+typedef struct {
+    volatile uint16_t * yctwa_f[VDEC_CHRFIL_TAPCOEF_NUM];
+    volatile uint16_t * yctwb_f[VDEC_CHRFIL_TAPCOEF_NUM];
+    volatile uint16_t * yctna_f[VDEC_CHRFIL_TAPCOEF_NUM];
+    volatile uint16_t * yctnb_f[VDEC_CHRFIL_TAPCOEF_NUM];
+} vdec_filter_reg_address_t;
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const vdec_reg_address_t         vdec_reg_address[VDEC_CHANNEL_NUM];
+extern const vdec_filter_reg_address_t  vdec_filter_reg_address[VDEC_CHANNEL_NUM];
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void VDEC_Initialize(const vdec_channel_t ch, const vdec_adc_vinsel_t vinsel);
+void VDEC_ActivePeriod(const vdec_channel_t ch, const vdec_active_period_t * const param);
+void VDEC_SyncSeparation(const vdec_channel_t ch, const vdec_sync_separation_t * const param);
+void VDEC_YcSeparation(const vdec_channel_t ch, const vdec_yc_separation_t * const param);
+void VDEC_ChromaDecoding(const vdec_channel_t ch, const vdec_chroma_decoding_t * const param);
+void VDEC_DigitalClamp(const vdec_channel_t ch, const vdec_degital_clamp_t * const param);
+void VDEC_Output(const vdec_channel_t ch, const vdec_output_t * const param);
+void VDEC_Query(
+    const vdec_channel_t            ch,
+    vdec_q_sync_sep_t       * const q_sync_sep,
+    vdec_q_agc_t            * const q_agc,
+    vdec_q_chroma_dec_t     * const q_chroma_dec,
+    vdec_q_digital_clamp_t  * const q_digital_clamp);
+
+
+#endif  /* R_VDEC_REGISTER_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/drivers/vdec/src/r_vdec_register_address.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,288 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         r_vdec_register_address.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        VDEC driver register address table
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+#include    "r_vdec_register.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+/* VDEC register address list */
+const vdec_reg_address_t vdec_reg_address[VDEC_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        &DVDEC0.ADCCR1,
+        &DVDEC0.TGCR1,
+        &DVDEC0.TGCR2,
+        &DVDEC0.TGCR3,
+        &DVDEC0.SYNSCR1,
+        &DVDEC0.SYNSCR2,
+        &DVDEC0.SYNSCR3,
+        &DVDEC0.SYNSCR4,
+        &DVDEC0.SYNSCR5,
+        &DVDEC0.HAFCCR1,
+        &DVDEC0.HAFCCR2,
+        &DVDEC0.HAFCCR3,
+        &DVDEC0.VCDWCR1,
+        &DVDEC0.DCPCR1,
+        &DVDEC0.DCPCR2,
+        &DVDEC0.DCPCR3,
+        &DVDEC0.DCPCR4,
+        &DVDEC0.DCPCR5,
+        &DVDEC0.DCPCR6,
+        &DVDEC0.DCPCR7,
+        &DVDEC0.DCPCR8,
+        &DVDEC0.NSDCR,
+        &DVDEC0.BTLCR,
+        &DVDEC0.BTGPCR,
+        &DVDEC0.ACCCR1,
+        &DVDEC0.ACCCR2,
+        &DVDEC0.ACCCR3,
+        &DVDEC0.TINTCR,
+        &DVDEC0.YCDCR,
+        &DVDEC0.AGCCR1,
+        &DVDEC0.AGCCR2,
+        &DVDEC0.PKLIMITCR,
+        &DVDEC0.RGORCR1,
+        &DVDEC0.RGORCR2,
+        &DVDEC0.RGORCR3,
+        &DVDEC0.RGORCR4,
+        &DVDEC0.RGORCR5,
+        &DVDEC0.RGORCR6,
+        &DVDEC0.RGORCR7,
+        &DVDEC0.AFCPFCR,
+        &DVDEC0.RUPDCR,
+        &DVDEC0.VSYNCSR,
+        &DVDEC0.HSYNCSR,
+        &DVDEC0.DCPSR1,
+        &DVDEC0.DCPSR2,
+        &DVDEC0.NSDSR,
+        &DVDEC0.CROMASR1,
+        &DVDEC0.CROMASR2,
+        &DVDEC0.SYNCSSR,
+        &DVDEC0.AGCCSR1,
+        &DVDEC0.AGCCSR2,
+        &DVDEC0.YCSCR3,
+        &DVDEC0.YCSCR4,
+        &DVDEC0.YCSCR5,
+        &DVDEC0.YCSCR6,
+        &DVDEC0.YCSCR7,
+        &DVDEC0.YCSCR8,
+        &DVDEC0.YCSCR9,
+        &DVDEC0.YCSCR11,
+        &DVDEC0.YCSCR12,
+        &DVDEC0.DCPCR9,
+        &DVDEC0.YGAINCR,
+        &DVDEC0.CBGAINCR,
+        &DVDEC0.CRGAINCR,
+        &DVDEC0.PGA_UPDATE,
+        &DVDEC0.PGACR,
+        &DVDEC0.ADCCR2
+    },
+    {   /* Channel 1 */
+        &DVDEC1.ADCCR1,
+        &DVDEC1.TGCR1,
+        &DVDEC1.TGCR2,
+        &DVDEC1.TGCR3,
+        &DVDEC1.SYNSCR1,
+        &DVDEC1.SYNSCR2,
+        &DVDEC1.SYNSCR3,
+        &DVDEC1.SYNSCR4,
+        &DVDEC1.SYNSCR5,
+        &DVDEC1.HAFCCR1,
+        &DVDEC1.HAFCCR2,
+        &DVDEC1.HAFCCR3,
+        &DVDEC1.VCDWCR1,
+        &DVDEC1.DCPCR1,
+        &DVDEC1.DCPCR2,
+        &DVDEC1.DCPCR3,
+        &DVDEC1.DCPCR4,
+        &DVDEC1.DCPCR5,
+        &DVDEC1.DCPCR6,
+        &DVDEC1.DCPCR7,
+        &DVDEC1.DCPCR8,
+        &DVDEC1.NSDCR,
+        &DVDEC1.BTLCR,
+        &DVDEC1.BTGPCR,
+        &DVDEC1.ACCCR1,
+        &DVDEC1.ACCCR2,
+        &DVDEC1.ACCCR3,
+        &DVDEC1.TINTCR,
+        &DVDEC1.YCDCR,
+        &DVDEC1.AGCCR1,
+        &DVDEC1.AGCCR2,
+        &DVDEC1.PKLIMITCR,
+        &DVDEC1.RGORCR1,
+        &DVDEC1.RGORCR2,
+        &DVDEC1.RGORCR3,
+        &DVDEC1.RGORCR4,
+        &DVDEC1.RGORCR5,
+        &DVDEC1.RGORCR6,
+        &DVDEC1.RGORCR7,
+        &DVDEC1.AFCPFCR,
+        &DVDEC1.RUPDCR,
+        &DVDEC1.VSYNCSR,
+        &DVDEC1.HSYNCSR,
+        &DVDEC1.DCPSR1,
+        &DVDEC1.DCPSR2,
+        &DVDEC1.NSDSR,
+        &DVDEC1.CROMASR1,
+        &DVDEC1.CROMASR2,
+        &DVDEC1.SYNCSSR,
+        &DVDEC1.AGCCSR1,
+        &DVDEC1.AGCCSR2,
+        &DVDEC1.YCSCR3,
+        &DVDEC1.YCSCR4,
+        &DVDEC1.YCSCR5,
+        &DVDEC1.YCSCR6,
+        &DVDEC1.YCSCR7,
+        &DVDEC1.YCSCR8,
+        &DVDEC1.YCSCR9,
+        &DVDEC1.YCSCR11,
+        &DVDEC1.YCSCR12,
+        &DVDEC1.DCPCR9,
+        &DVDEC1.YGAINCR,
+        &DVDEC1.CBGAINCR,
+        &DVDEC1.CRGAINCR,
+        &DVDEC1.PGA_UPDATE,
+        &DVDEC1.PGACR,
+        &DVDEC1.ADCCR2
+    }
+};
+
+/* VDEC register address list (for 2D filter tap coefficient) */
+const vdec_filter_reg_address_t vdec_filter_reg_address[VDEC_CHANNEL_NUM] = {
+    {   /* Channel 0 */
+        {
+            &DVDEC0.YCTWA_F0,
+            &DVDEC0.YCTWA_F1,
+            &DVDEC0.YCTWA_F2,
+            &DVDEC0.YCTWA_F3,
+            &DVDEC0.YCTWA_F4,
+            &DVDEC0.YCTWA_F5,
+            &DVDEC0.YCTWA_F6,
+            &DVDEC0.YCTWA_F7,
+            &DVDEC0.YCTWA_F8
+        },
+        {
+            &DVDEC0.YCTWB_F0,
+            &DVDEC0.YCTWB_F1,
+            &DVDEC0.YCTWB_F2,
+            &DVDEC0.YCTWB_F3,
+            &DVDEC0.YCTWB_F4,
+            &DVDEC0.YCTWB_F5,
+            &DVDEC0.YCTWB_F6,
+            &DVDEC0.YCTWB_F7,
+            &DVDEC0.YCTWB_F8
+        },
+        {
+            &DVDEC0.YCTNA_F0,
+            &DVDEC0.YCTNA_F1,
+            &DVDEC0.YCTNA_F2,
+            &DVDEC0.YCTNA_F3,
+            &DVDEC0.YCTNA_F4,
+            &DVDEC0.YCTNA_F5,
+            &DVDEC0.YCTNA_F6,
+            &DVDEC0.YCTNA_F7,
+            &DVDEC0.YCTNA_F8
+        },
+        {
+            &DVDEC0.YCTNB_F0,
+            &DVDEC0.YCTNB_F1,
+            &DVDEC0.YCTNB_F2,
+            &DVDEC0.YCTNB_F3,
+            &DVDEC0.YCTNB_F4,
+            &DVDEC0.YCTNB_F5,
+            &DVDEC0.YCTNB_F6,
+            &DVDEC0.YCTNB_F7,
+            &DVDEC0.YCTNB_F8
+        }
+    },
+    {   /* Channel 1 */
+        {
+            &DVDEC1.YCTWA_F0,
+            &DVDEC1.YCTWA_F1,
+            &DVDEC1.YCTWA_F2,
+            &DVDEC1.YCTWA_F3,
+            &DVDEC1.YCTWA_F4,
+            &DVDEC1.YCTWA_F5,
+            &DVDEC1.YCTWA_F6,
+            &DVDEC1.YCTWA_F7,
+            &DVDEC1.YCTWA_F8
+        },
+        {
+            &DVDEC1.YCTWB_F0,
+            &DVDEC1.YCTWB_F1,
+            &DVDEC1.YCTWB_F2,
+            &DVDEC1.YCTWB_F3,
+            &DVDEC1.YCTWB_F4,
+            &DVDEC1.YCTWB_F5,
+            &DVDEC1.YCTWB_F6,
+            &DVDEC1.YCTWB_F7,
+            &DVDEC1.YCTWB_F8
+        },
+        {
+            &DVDEC1.YCTNA_F0,
+            &DVDEC1.YCTNA_F1,
+            &DVDEC1.YCTNA_F2,
+            &DVDEC1.YCTNA_F3,
+            &DVDEC1.YCTNA_F4,
+            &DVDEC1.YCTNA_F5,
+            &DVDEC1.YCTNA_F6,
+            &DVDEC1.YCTNA_F7,
+            &DVDEC1.YCTNA_F8
+        },
+        {
+            &DVDEC1.YCTNB_F0,
+            &DVDEC1.YCTNB_F1,
+            &DVDEC1.YCTNB_F2,
+            &DVDEC1.YCTNB_F3,
+            &DVDEC1.YCTNB_F4,
+            &DVDEC1.YCTNB_F5,
+            &DVDEC1.YCTNB_F6,
+            &DVDEC1.YCTNB_F7,
+            &DVDEC1.YCTNB_F8
+        }
+    }
+};
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/inc/lcd_analog_rgb.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,135 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_analog_rgb.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel  definition header
+******************************************************************************/
+
+#ifndef LCD_ANALOG_RGB_H
+#define LCD_ANALOG_RGB_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* SVGA signal 800x600
+    Pixel clock frequency: 40.0 MHz
+    Refresh rate: 60.3 Hz
+    Polarity of horizontal sync pulse: Positive
+    Polarity of vertical sync pulse: Positive
+*/
+#define     LCD_SVGA_H_VISIBLE_AREA     (800u)                      /* Horizontal visible area [pixel] */
+#define     LCD_SVGA_H_FRONT_PORCH      (40u)                       /* Horizontal front porch [pixel] */
+#define     LCD_SVGA_H_SYNC_WIDTH       (128u)                      /* Horizontal sync pulse width [pixel] */
+#define     LCD_SVGA_H_BACK_PORCH       (88u)                       /* Horizontal back porch [pixel] */
+/* Horizontal total (one line) [pixel] */
+#define     LCD_SVGA_H_TOTAL            (LCD_SVGA_H_VISIBLE_AREA +\
+                                        LCD_SVGA_H_FRONT_PORCH +\
+                                        LCD_SVGA_H_SYNC_WIDTH +\
+                                        LCD_SVGA_H_BACK_PORCH)
+#define     LCD_SVGA_H_POLARITY         (VDC5_SIG_POL_NOT_INVERTED) /* Polarity of horizontal sync pulse */
+
+#define     LCD_SVGA_V_VISIBLE_AREA     (600u)                      /* Vertical visible area [line] */
+#define     LCD_SVGA_V_FRONT_PORCH      (1u)                        /* Vertical front porch [line] */
+#define     LCD_SVGA_V_SYNC_WIDTH       (4u)                        /* Vertical sync pulse width [line] */
+#define     LCD_SVGA_V_BACK_PORCH       (23u)                       /* Vertical back porch [line] */
+/* Vertical total (one frame) [line] */
+#define     LCD_SVGA_V_TOTAL            (LCD_SVGA_V_VISIBLE_AREA +\
+                                        LCD_SVGA_V_FRONT_PORCH +\
+                                        LCD_SVGA_V_SYNC_WIDTH +\
+                                        LCD_SVGA_V_BACK_PORCH)
+#define     LCD_SVGA_V_POLARITY         (VDC5_SIG_POL_NOT_INVERTED) /* Polarity of vertical sync pulse */
+
+
+/* XGA signal 1024x768
+    Pixel clock frequency: 65.0 MHz
+    Refresh rate: 60.0 Hz
+    Polarity of horizontal sync pulse: Negative
+    Polarity of vertical sync pulse: Negative
+*/
+#define     LCD_XGA_H_VISIBLE_AREA      (1024u)                     /* Horizontal visible area [pixel] */
+#define     LCD_XGA_H_FRONT_PORCH       (24u)                       /* Horizontal front porch [pixel] */
+#define     LCD_XGA_H_SYNC_WIDTH        (136u)                      /* Horizontal sync pulse width [pixel] */
+#define     LCD_XGA_H_BACK_PORCH        (160u)                      /* Horizontal back porch [pixel] */
+/* Horizontal total (one line) [pixel] */
+#define     LCD_XGA_H_TOTAL             (LCD_XGA_H_VISIBLE_AREA +\
+                                        LCD_XGA_H_FRONT_PORCH +\
+                                        LCD_XGA_H_SYNC_WIDTH +\
+                                        LCD_XGA_H_BACK_PORCH)
+#define     LCD_XGA_H_POLARITY          (VDC5_SIG_POL_INVERTED)     /* Polarity of horizontal sync pulse */
+
+#define     LCD_XGA_V_VISIBLE_AREA      (768u)                      /* Vertical visible area [line] */
+#define     LCD_XGA_V_FRONT_PORCH       (3u)                        /* Vertical front porch [line] */
+#define     LCD_XGA_V_SYNC_WIDTH        (6u)                        /* Vertical sync pulse width [line] */
+#define     LCD_XGA_V_BACK_PORCH        (29u)                       /* Vertical back porch [line] */
+/* Vertical total (one frame) [line] */
+#define     LCD_XGA_V_TOTAL             (LCD_XGA_V_VISIBLE_AREA +\
+                                        LCD_XGA_V_FRONT_PORCH +\
+                                        LCD_XGA_V_SYNC_WIDTH +\
+                                        LCD_XGA_V_BACK_PORCH)
+#define     LCD_XGA_V_POLARITY          (VDC5_SIG_POL_INVERTED)     /* Polarity of vertical sync pulse */
+
+
+/* VGA signal 640x480
+    Pixel clock frequency: 25.175 MHz
+    Refresh rate: 59.94 Hz
+    Polarity of horizontal sync pulse: Negative
+    Polarity of vertical sync pulse: Negative
+*/
+#define     LCD_VGA_H_VISIBLE_AREA      (640u)                      /* Horizontal visible area [pixel] */
+#define     LCD_VGA_H_FRONT_PORCH       (16u)                       /* Horizontal front porch [pixel] */
+#define     LCD_VGA_H_SYNC_WIDTH        (96u)                       /* Horizontal sync pulse width [pixel] */
+#define     LCD_VGA_H_BACK_PORCH        (48u)                       /* Horizontal back porch [pixel] */
+/* Horizontal total (one line) [pixel] */
+#define     LCD_VGA_H_TOTAL             (LCD_VGA_H_VISIBLE_AREA +\
+                                        LCD_VGA_H_FRONT_PORCH +\
+                                        LCD_VGA_H_SYNC_WIDTH +\
+                                        LCD_VGA_H_BACK_PORCH)
+#define     LCD_VGA_H_POLARITY          (VDC5_SIG_POL_INVERTED)     /* Polarity of horizontal sync pulse */
+
+#define     LCD_VGA_V_VISIBLE_AREA      (480u)                      /* Vertical visible area [line] */
+#define     LCD_VGA_V_FRONT_PORCH       (10u)                       /* Vertical front porch [line] */
+#define     LCD_VGA_V_SYNC_WIDTH        (2u)                        /* Vertical sync pulse width [line] */
+#define     LCD_VGA_V_BACK_PORCH        (33u)                       /* Vertical back porch [line] */
+/* Vertical total (one frame) [line] */
+#define     LCD_VGA_V_TOTAL             (LCD_VGA_V_VISIBLE_AREA +\
+                                        LCD_VGA_V_FRONT_PORCH +\
+                                        LCD_VGA_V_SYNC_WIDTH +\
+                                        LCD_VGA_V_BACK_PORCH)
+#define     LCD_VGA_V_POLARITY          (VDC5_SIG_POL_INVERTED)     /* Polarity of vertical sync pulse */
+
+
+#endif  /* LCD_ANALOG_RGB_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/inc/lcd_analog_rgb_ch1.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,96 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_analog_rgb_ch1.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 1 definition header
+******************************************************************************/
+
+#ifndef LCD_ANALOG_RGB_CH1_H
+#define LCD_ANALOG_RGB_CH1_H
+
+#ifndef LCD_PANEL_H
+#error  Do not include this file directly!
+#else
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+#include    "lcd_analog_rgb.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* Option board (part number: RTK7721000B00000BR)
+    ADV7123 (Video DAC), U10
+    Analog RGB D-sub15 (RGB888), J16 */
+#define     LCD_CH1_S_HSYNC         (0u)                        /* Hsync start position */
+#define     LCD_CH1_W_HSYNC         (LCD_SVGA_H_SYNC_WIDTH)     /* Hsync width */
+#define     LCD_CH1_POL_HSYNC       (LCD_SVGA_H_POLARITY)       /* Polarity of Hsync pulse */
+/* LCD display area size, horizontal start position */
+#define     LCD_CH1_DISP_HS         (LCD_SVGA_H_SYNC_WIDTH + LCD_SVGA_H_BACK_PORCH)
+#define     LCD_CH1_DISP_HW         (LCD_SVGA_H_VISIBLE_AREA)   /* LCD display area size, horizontal width */
+
+/* Vsync start position */
+#define     LCD_CH1_S_VSYNC         (LCD_SVGA_V_BACK_PORCH + LCD_SVGA_V_VISIBLE_AREA + LCD_SVGA_V_FRONT_PORCH)
+#define     LCD_CH1_W_VSYNC         (LCD_SVGA_V_SYNC_WIDTH)     /* Vsync width */
+#define     LCD_CH1_POL_VSYNC       (LCD_SVGA_V_POLARITY)       /* Polarity of Vsync pulse */
+#define     LCD_CH1_DISP_VS         (LCD_SVGA_V_BACK_PORCH)     /* LCD display area size, vertical start position */
+#define     LCD_CH1_DISP_VW         (LCD_SVGA_V_VISIBLE_AREA)   /* LCD display area size, height (vertical width) */
+
+#define     LCD_CH1_SIG_FV          (LCD_SVGA_V_TOTAL - 1u)     /* Free-running Vsync period */
+#define     LCD_CH1_SIG_FH          (LCD_SVGA_H_TOTAL - 1u)     /* Hsync period */
+/* Pixel data is latched in the rising edge of pixel clock on ADV7123.
+   Therefore, pixel data should be output from VDC5 at the falling edge of the clock. */
+#define     LCD_CH1_OUT_EDGE        VDC5_EDGE_FALLING           /* Output phase control of LCD_DATA[23:0] signal */
+#define     LCD_CH1_OUT_FORMAT      VDC5_LCD_OUTFORMAT_RGB888   /* LCD output format select */
+
+#define     LCD_CH1_PANEL_CLK       VDC5_PANEL_ICKSEL_LVDS      /* Panel clock select */
+#define     LCD_CH1_PANEL_CLK_DIV   VDC5_PANEL_CLKDIV_1_1       /* Panel clock frequency division ratio */
+
+#define     LCD_CH1_TCON_HALF       (LCD_CH1_SIG_FH / 2u)       /* TCON reference timing, 1/2fH timing */
+#define     LCD_CH1_TCON_OFFSET     (0u)                        /* TCON reference timing, offset Hsync signal timing */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch1(void);
+void GRAPHICS_SetLcdTconSettings_Ch1(const vdc5_lcd_tcon_timing_t * * const outctrl);
+
+
+#endif  /* LCD_PANEL_H not defined */
+#endif  /* LCD_ANALOG_RGB_CH1_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/inc/lcd_panel.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,92 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_panel.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel definition header
+******************************************************************************/
+
+#ifndef LCD_PANEL_H
+#define LCD_PANEL_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* LCD panel select (CH0)
+    1: VKLCD50RTA, HVGA 480x272
+    2: VKLCD70RT, WSVGA 1024x600
+*/
+#define     LCD_CH0_PANEL_VKLCD50RTA            (1) /* 16bitRGB(565) */
+#define     LCD_CH0_PANEL_VKLCD70RT             (2) /* LVDS          */
+
+//#define     LCD_VDC5_CH0_PANEL                  LCD_CH0_PANEL_VKLCD50RTA
+#define     LCD_VDC5_CH0_PANEL                  LCD_CH0_PANEL_VKLCD70RT
+
+/* LCD panel select (CH1)
+    1: Analog RGB D-sub15, SVGA 800x600  debug code for GENMAI Board
+*/
+#define     LCD_CH1_PANEL_ANALOG_RGB            (1) /* debug */
+#define     LCD_VDC5_CH1_PANEL                  LCD_CH1_PANEL_ANALOG_RGB
+
+
+#if   (LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_VKLCD50RTA)
+#include    "lcd_vklcd50rta_ch0.h"   
+#elif   (LCD_VDC5_CH0_PANEL==LCD_CH0_PANEL_VKLCD70RT)
+#include    "lcd_vklcd70rt_ch0.h"   
+#else
+#error  Undefined LCD panel!
+#endif
+
+#if     (LCD_VDC5_CH1_PANEL==1)
+#include    "lcd_analog_rgb_ch1.h"
+#else
+#error  Undefined LCD panel!
+#endif
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+void GRAPHICS_SetLcdPanel(const vdc5_channel_t channel);
+void GRAPHICS_SetLcdTconSettings(const vdc5_channel_t channel, const vdc5_lcd_tcon_timing_t * * const outctrl);
+vdc5_lvds_t * GRAPHICS_GetLvdsParam(const vdc5_channel_t channel);
+
+
+#endif  /* LCD_PANEL_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/inc/lcd_vklcd50rta_ch0.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,82 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_vklcd50rta_ch0.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 0 definition header
+******************************************************************************/
+
+#ifndef LCD_VKLCD50RTA_CH0_H
+#define LCD_VKLCD50RTA_CH0_H
+
+#ifndef LCD_PANEL_H
+#error  Do not include this file directly!
+#else
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     LCD_CH0_DISP_HS         (22u)                       /* LCD display area size, horizontal start position */
+#define     LCD_CH0_DISP_HW         (480u)                      /* LCD display area size, horizontal width */
+#define     LCD_CH0_DISP_VS         (8u)                        /* LCD display area size, vertical start position */
+#define     LCD_CH0_DISP_VW         (272u)                      /* LCD display area size, height (vertical width) */
+#define     LCD_CH0_SIG_FV          (288u - 1u)                 /* Free-running Vsync period */
+#define     LCD_CH0_SIG_FH          (525u - 1u)                 /* Hsync period */
+/* Pixel data is latched in the falling edge of pixel clock.
+   Therefore, pixel data should be output from VDC5 at the rising edge of the clock. */
+#define     LCD_CH0_OUT_EDGE        VDC5_EDGE_RISING            /* Output phase control of LCD_DATA[23:0] signal */
+#define     LCD_CH0_OUT_FORMAT      VDC5_LCD_OUTFORMAT_RGB565   /* LCD output format select */
+
+#define     LCD_CH0_PANEL_CLK       VDC5_PANEL_ICKSEL_PERI      /* Panel clock select */
+#define     LCD_CH0_PANEL_CLK_DIV   VDC5_PANEL_CLKDIV_1_7       /* Panel clock frequency division ratio */
+
+#define     LCD_CH0_TCON_HALF       (LCD_CH0_SIG_FH / 2u)       /* TCON reference timing, 1/2fH timing */
+#define     LCD_CH0_TCON_OFFSET     (0u)                        /* TCON reference timing, offset Hsync signal timing */
+
+#define     LCD_CH0_INITIAL_DC      75
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch0(void);
+void GRAPHICS_SetLcdTconSettings_Ch0(const vdc5_lcd_tcon_timing_t * * const outctrl);
+
+
+#endif  /* LCD_PANEL_H not defined */
+#endif  /* LCD_VKLCD50RTA_CH0_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/inc/lcd_vklcd70rt_ch0.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,120 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lcd_vklcd70rt_ch0.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        LCD panel for vdc5 channel 0 definition header
+******************************************************************************/
+
+#ifndef LCD_VKLCD70RT_CH0_H
+#define LCD_VKLCD70RT_CH0_H
+
+#ifndef LCD_PANEL_H
+#error  Do not include this file directly!
+#else
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+
+#include    "r_vdc5.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     LCD_CH0_DISP_HS         (160u)                      /* LCD display area size, horizontal start position */
+#define     LCD_CH0_DISP_HW         (1024u)                     /* LCD display area size, horizontal width */
+#define     LCD_CH0_DISP_VS         (18u)                       /* LCD display area size, vertical start position */
+#define     LCD_CH0_DISP_VW         (600u)                      /* LCD display area size, height (vertical width) */
+#define     LCD_CH0_SIG_FV          (635u - 1u)                 /* Free-running Vsync period */
+#define     LCD_CH0_SIG_FH          (1344u - 1u)                /* Hsync period */
+/* Pixel data is latched in the falling edge of pixel clock.
+   Therefore, pixel data should be output from VDC5 at the rising edge of the clock. */
+#define     LCD_CH0_OUT_EDGE        VDC5_EDGE_RISING            /* Output phase control of LCD_DATA[23:0] signal */
+#define     LCD_CH0_OUT_FORMAT      VDC5_LCD_OUTFORMAT_RGB888   /* LCD output format select */
+
+#define     LCD_CH0_PANEL_CLK       VDC5_PANEL_ICKSEL_LVDS_DIV7 /* Panel clock select */
+#define     LCD_CH0_PANEL_CLK_DIV   VDC5_PANEL_CLKDIV_1_2       /* Panel clock frequency division ratio */
+
+#define     LCD_CH0_TCON_HALF       (LCD_CH0_SIG_FH / 2u)       /* TCON reference timing, 1/2fH timing */
+#define     LCD_CH0_TCON_OFFSET     (0u)                        /* TCON reference timing, offset Hsync signal timing */
+
+#define     LCD_CH0_INITIAL_DC      30
+
+#define     LCD_CH0_EXP_ADDR        0x80
+#define     LCD_CH0_CALIB_ADDR      0x90
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+enum CONTROL_BIT__ {
+   RGB_DATA = 0,
+   M666_888,
+   L_R_SCAN,
+   U_D_SCAN,
+   BL_EN   ,
+   RESET_CTP,
+//-----------
+   MAXBITS
+};
+
+enum CONTROL_REG__ {
+   PORTMODE = 0,
+   OUTPUT,
+   INPUT,
+   PWM_DC,
+   PWM_DIV,
+   PWM_T,
+//-----------
+   MAXREGS
+};
+
+typedef union __IOEXP
+{
+  struct __CONTROL
+  {
+    uint8_t portmode;
+    uint8_t output;
+    uint8_t input;
+    uint8_t PWM_dc;
+    uint8_t PWM_div;
+    uint8_t PWM_t;
+  }regs;
+  
+  uint8_t reg[sizeof(struct __CONTROL)];
+}ioexp_t;
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+void GRAPHICS_SetLcdPanel_Ch0(void);
+void GRAPHICS_SetLcdTconSettings_Ch0(const vdc5_lcd_tcon_timing_t * * const outctrl);
+
+
+#endif  /* LCD_PANEL_H not defined */
+#endif  /* LCD_VKLCD70RT_CH0_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/inc/lvds_pll_calc.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,71 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lvds_pll_calc.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        Debug function header
+******************************************************************************/
+
+#ifndef LVDS_PLL_CALC_H
+#define LVDS_PLL_CALC_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    "r_typedefs.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+typedef struct {
+    double comparison_freq;
+    double output_freq;
+    double nidiv;
+    double nrd;
+    double nfd;
+    double nod;
+    double nodiv;
+} pll_parameter_t;
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+#define LVDS_IF_NOT_USE (0u)
+#define LVDS_IF_USE     (1u)
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+extern int32_t lvds_pll_calc(
+    const double      InClock,
+    const double      OuClock,
+    const uint32_t    Lvds,
+    pll_parameter_t * result  );
+
+#endif  /* LVDS_PLL_CALC_H */
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/inc/video_decoder.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         video_decoder.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        Video decoder function header
+******************************************************************************/
+
+#ifndef VIDEO_DECODER_H
+#define VIDEO_DECODER_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+#include    <string.h>
+
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Video color system */
+typedef enum {
+    GRPH_COL_SYS_UNKNOWN        = -1,       /*!< Unknown */
+    GRPH_COL_SYS_NTSC_358       = 0,        /*!< NTSC-3.58 */
+    GRPH_COL_SYS_NTSC_443       = 1,        /*!< NTSC-4.43 */
+    GRPH_COL_SYS_PAL_443        = 2,        /*!< PAL-4.43 */
+    GRPH_COL_SYS_PAL_M          = 3,        /*!< PAL-M */
+    GRPH_COL_SYS_PAL_N          = 4,        /*!< PAL-N */
+    GRPH_COL_SYS_SECAM          = 5,        /*!< SECAM */
+    GRPH_COL_SYS_NTSC_443_60    = 6,        /*!< NTSC-4.43 (60Hz) */
+    GRPH_COL_SYS_PAL_60         = 7,        /*!< PAL-60 */
+    GRPH_COL_SYS_NUM            = 8
+} graphics_col_sys_t;
+
+
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+vdec_error_t GRAPHICS_VideoDecoderInit (const vdec_adc_vinsel_t adc_vinsel, const vdec_channel_t channel, graphics_col_sys_t col_sys);
+
+
+#endif  /* VIDEO_DECODER_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/lvds/lvds_pll_data.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,322 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/**************************************************************************//**
+* @file         lvds_pll_data.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        lvds pll for vdc5 channel 0 data
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdio.h>
+#include    <stdlib.h>
+
+
+/******************************************************************************
+Variables
+******************************************************************************/
+const double NIDIV_data[] = {
+    1.0,    2.0,    4.0,
+    0.0
+};
+
+const double NRD_data[] = {
+    1.0,    2.0,    3.0,    4.0,    5.0,    6.0,    7.0,    8.0,
+    9.0,    10.0,   11.0,   12.0,   13.0,   14.0,   15.0,   16.0,
+    17.0,   18.0,   19.0,   20.0,   21.0,   22.0,   23.0,   24.0,
+    25.0,   26.0,   27.0,   28.0,   29.0,   30.0,   31.0,   32.0,
+    0.0
+};
+
+const double NFD_data[] = {
+    24.0,   25.0,   26.0,   27.0,
+    32.0,   33.0,   34.0,   35.0,   36.0,
+    40.0,   41.0,   42.0,   43.0,   44.0,   45.0,
+    48.0,   49.0,   50.0,   51.0,   52.0,   53.0,   54.0,
+    56.0,   57.0,   58.0,   59.0,   60.0,   61.0,   62.0,   63.0,
+    64.0,   65.0,   66.0,   67.0,   68.0,   69.0,   70.0,   71.0,
+    72.0,   73.0,   74.0,   75.0,   76.0,   77.0,   78.0,   79.0,
+    80.0,   81.0,   82.0,   83.0,   84.0,   85.0,   86.0,   87.0,
+    88.0,   89.0,   90.0,   91.0,   92.0,   93.0,   94.0,   95.0,
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+    1568.0, 1569.0, 1570.0, 1571.0, 1572.0, 1573.0, 1574.0, 1575.0,
+    1576.0, 1577.0, 1578.0, 1579.0, 1580.0, 1581.0, 1582.0, 1583.0,
+    1584.0, 1585.0, 1586.0, 1587.0, 1588.0, 1589.0, 1590.0, 1591.0,
+    1592.0, 1593.0, 1594.0, 1595.0, 1596.0, 1597.0, 1598.0, 1599.0,
+    1600.0, 1601.0, 1602.0, 1603.0, 1604.0, 1605.0, 1606.0, 1607.0,
+    1608.0, 1609.0, 1610.0, 1611.0, 1612.0, 1613.0, 1614.0, 1615.0,
+    1616.0, 1617.0, 1618.0, 1619.0, 1620.0, 1621.0, 1622.0, 1623.0,
+    1624.0, 1625.0, 1626.0, 1627.0, 1628.0, 1629.0, 1630.0, 1631.0,
+    1632.0, 1633.0, 1634.0, 1635.0, 1636.0, 1637.0, 1638.0, 1639.0,
+    1640.0, 1641.0, 1642.0, 1643.0, 1644.0, 1645.0, 1646.0, 1647.0,
+    1648.0, 1649.0, 1650.0, 1651.0, 1652.0, 1653.0, 1654.0, 1655.0,
+    1656.0, 1657.0, 1658.0, 1659.0, 1660.0, 1661.0, 1662.0, 1663.0,
+    1664.0, 1665.0, 1666.0, 1667.0, 1668.0, 1669.0, 1670.0, 1671.0,
+    1672.0, 1673.0, 1674.0, 1675.0, 1676.0, 1677.0, 1678.0, 1679.0,
+    1680.0, 1681.0, 1682.0, 1683.0, 1684.0, 1685.0, 1686.0, 1687.0,
+    1688.0, 1689.0, 1690.0, 1691.0, 1692.0, 1693.0, 1694.0, 1695.0,
+    1696.0, 1697.0, 1698.0, 1699.0, 1700.0, 1701.0, 1702.0, 1703.0,
+    1704.0, 1705.0, 1706.0, 1707.0, 1708.0, 1709.0, 1710.0, 1711.0,
+    1712.0, 1713.0, 1714.0, 1715.0, 1716.0, 1717.0, 1718.0, 1719.0,
+    1720.0, 1721.0, 1722.0, 1723.0, 1724.0, 1725.0, 1726.0, 1727.0,
+    1728.0, 1729.0, 1730.0, 1731.0, 1732.0, 1733.0, 1734.0, 1735.0,
+    1736.0, 1737.0, 1738.0, 1739.0, 1740.0, 1741.0, 1742.0, 1743.0,
+    1744.0, 1745.0, 1746.0, 1747.0, 1748.0, 1749.0, 1750.0, 1751.0,
+    1752.0, 1753.0, 1754.0, 1755.0, 1756.0, 1757.0, 1758.0, 1759.0,
+    1760.0, 1761.0, 1762.0, 1763.0, 1764.0, 1765.0, 1766.0, 1767.0,
+    1768.0, 1769.0, 1770.0, 1771.0, 1772.0, 1773.0, 1774.0, 1775.0,
+    1776.0, 1777.0, 1778.0, 1779.0, 1780.0, 1781.0, 1782.0, 1783.0,
+    1784.0, 1785.0, 1786.0, 1787.0, 1788.0, 1789.0, 1790.0, 1791.0,
+    1792.0, 1793.0, 1794.0, 1795.0, 1796.0, 1797.0, 1798.0, 1799.0,
+    1800.0, 1801.0, 1802.0, 1803.0, 1804.0, 1805.0, 1806.0, 1807.0,
+    1808.0, 1809.0, 1810.0, 1811.0, 1812.0, 1813.0, 1814.0, 1815.0,
+    1816.0, 1817.0, 1818.0, 1819.0, 1820.0, 1821.0, 1822.0, 1823.0,
+    1824.0, 1825.0, 1826.0, 1827.0, 1828.0, 1829.0, 1830.0, 1831.0,
+    1832.0, 1833.0, 1834.0, 1835.0, 1836.0, 1837.0, 1838.0, 1839.0,
+    1840.0, 1841.0, 1842.0, 1843.0, 1844.0, 1845.0, 1846.0, 1847.0,
+    1848.0, 1849.0, 1850.0, 1851.0, 1852.0, 1853.0, 1854.0, 1855.0,
+    1856.0, 1857.0, 1858.0, 1859.0, 1860.0, 1861.0, 1862.0, 1863.0,
+    1864.0, 1865.0, 1866.0, 1867.0, 1868.0, 1869.0, 1870.0, 1871.0,
+    1872.0, 1873.0, 1874.0, 1875.0, 1876.0, 1877.0, 1878.0, 1879.0,
+    1880.0, 1881.0, 1882.0, 1883.0, 1884.0, 1885.0, 1886.0, 1887.0,
+    1888.0, 1889.0, 1890.0, 1891.0, 1892.0, 1893.0, 1894.0, 1895.0,
+    1896.0, 1897.0, 1898.0, 1899.0, 1900.0, 1901.0, 1902.0, 1903.0,
+    1904.0, 1905.0, 1906.0, 1907.0, 1908.0, 1909.0, 1910.0, 1911.0,
+    1912.0, 1913.0, 1914.0, 1915.0, 1916.0, 1917.0, 1918.0, 1919.0,
+    1920.0, 1921.0, 1922.0, 1923.0, 1924.0, 1925.0, 1926.0, 1927.0,
+    1928.0, 1929.0, 1930.0, 1931.0, 1932.0, 1933.0, 1934.0, 1935.0,
+    1936.0, 1937.0, 1938.0, 1939.0, 1940.0, 1941.0, 1942.0, 1943.0,
+    1944.0, 1945.0, 1946.0, 1947.0, 1948.0, 1949.0, 1950.0, 1951.0,
+    1952.0, 1953.0, 1954.0, 1955.0, 1956.0, 1957.0, 1958.0, 1959.0,
+    1960.0, 1961.0, 1962.0, 1963.0, 1964.0, 1965.0, 1966.0, 1967.0,
+    1968.0, 1969.0, 1970.0, 1971.0, 1972.0, 1973.0, 1974.0, 1975.0,
+    1976.0, 1977.0, 1978.0, 1979.0, 1980.0, 1981.0, 1982.0, 1983.0,
+    1984.0, 1985.0, 1986.0, 1987.0, 1988.0, 1989.0, 1990.0, 1991.0,
+    1992.0, 1993.0, 1994.0, 1995.0, 1996.0, 1997.0, 1998.0, 1999.0,
+    2000.0, 2001.0, 2002.0, 2003.0, 2004.0, 2005.0, 2006.0, 2007.0,
+    2008.0, 2009.0, 2010.0, 2011.0, 2012.0, 2013.0, 2014.0, 2015.0,
+    2016.0, 2017.0, 2018.0, 2019.0, 2020.0, 2021.0, 2022.0, 2023.0,
+    2024.0, 2025.0, 2026.0, 2027.0, 2028.0, 2029.0, 2030.0, 2031.0,
+    2032.0, 2033.0, 2034.0, 2035.0, 2036.0, 2037.0, 2038.0, 2039.0,
+    2040.0, 2041.0, 2042.0, 2043.0, 2044.0, 2045.0, 2046.0, 2047.0,
+    0.0
+};
+
+const double NOD_data[] = {
+    1.0,    2.0,    4.0,    8.0,
+    0.0
+};
+
+const double NODIV_data[] = {
+    1.0,    2.0,    4.0,
+    0.0
+};
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/lvds/lvds_pll_main.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,240 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         lvds_pll_main.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        lvds pll setting value
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdio.h>
+#include    <stdlib.h>
+#include    <math.h>
+
+#include    "r_typedefs.h"
+#include    "lvds_pll_calc.h"
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* FIN: LVDS PLL input frequency */
+#define     FIN_MIN             (9.0)           /*!< The lower limit of the FIN */
+#define     FIN_MAX             (30.0)          /*!< The upper limit of the FIN */
+/* FREF */
+#define     FREF_MIN            (2.5)           /*!< The lower limit of the FREF */
+#define     FREF_MAX            (30.0)          /*!< The upper limit of the FREF */
+/* FVCO: VCO output frequency */
+#define     FVCO_MIN            (750.0)         /*!< The lower limit of the FVCO */
+#define     FVCO_MAX            (1630.0)        /*!< The upper limit of the FVCO */
+/* FOUT: LVDS PLL output frequency */
+#define     FOUT_MIN            (0.0)           /*!< The lower limit of the FOUT */
+#define     FOUT_MAX            (609.0)         /*!< The upper limit of the FOUT */
+
+#define     DIVIDER_3           (7.0)           /*!< The frequency dividing value for frequency divider 3 */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+extern const double NIDIV_data[];
+extern const double NRD_data[];
+extern const double NFD_data[];
+extern const double NOD_data[];
+extern const double NODIV_data[];
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static double   InputClock;
+static double   OutputClock;
+static int      LvdsUsed;
+
+
+
+/**************************************************************************//**
+ * @brief
+ * @param       [in,out]param
+ * @param       [in]fout
+ * @retval      int
+ *****************************************************************************/
+static int compare_nodiv (pll_parameter_t * param, double fout)
+{
+    int             change;
+    const double  * nodiv_list;
+    double          diff_freq;
+
+    change      = 0;
+    nodiv_list  = NODIV_data;
+    while (*nodiv_list != 0.0) {
+        diff_freq   = fabs(OutputClock - (fout / *nodiv_list));
+        if (param->comparison_freq > diff_freq) {
+            param->comparison_freq  = diff_freq;
+            param->output_freq      = fout / *nodiv_list;
+            param->nodiv            = *nodiv_list;
+            change                  = 1;
+        }
+        nodiv_list++;
+    }
+    return change;
+}
+
+/**************************************************************************//**
+ * @brief
+ * @param       [in,out]param
+ * @param       [in]fout
+ * @retval      int
+ *****************************************************************************/
+static int compare_div3 (pll_parameter_t * param, double fout)
+{
+    double  diff_freq;
+    int     change;
+
+    change      = 0;
+    diff_freq   = fabs(OutputClock - (fout / DIVIDER_3));
+
+    if (param->comparison_freq > diff_freq) {
+        param->comparison_freq  = diff_freq;
+        param->output_freq      = fout / DIVIDER_3;
+        change                  = 1;
+    }
+    return change;
+}
+
+/**************************************************************************//**
+ * @brief
+ * @param       [out]param
+ * @retval      None
+ *****************************************************************************/
+static void SeekValue (pll_parameter_t * param)
+{
+    const double  * nidiv_list;
+    const double  * nrd_list;
+    const double  * nfd_list;
+    const double  * nod_list;
+
+    double  fin;
+    double  fref;
+    double  fvco;
+    double  fout;
+    int     ret;
+
+    nidiv_list = NIDIV_data;
+    while (*nidiv_list != 0.0) {
+        fin = InputClock / *nidiv_list;
+        if ((fin < FIN_MIN) || (FIN_MAX < fin)) {
+            nidiv_list++;
+            continue;
+        }
+        nrd_list = NRD_data;
+        while (*nrd_list != 0.0) {
+            fref = fin / *nrd_list;
+            if ((fref < FREF_MIN) || (FREF_MAX < fref)) {
+                nrd_list++;
+                continue;
+            }
+            nfd_list = NFD_data;
+            while (*nfd_list != 0.0) {
+                fvco = fref * (*nfd_list);
+                if ((fvco < FVCO_MIN) || (FVCO_MAX < fvco)) {
+                    nfd_list++;
+                    continue;
+                }
+                nod_list = NOD_data;
+                while (*nod_list != 0.0) {
+                    fout = fvco / *nod_list;
+                    if ((fout < FOUT_MIN) || (FOUT_MAX < fout)) {
+                        nod_list++;
+                        continue;
+                    }
+
+                    if (LvdsUsed == 0) {
+                        ret = compare_nodiv(param, fout);
+                    } else {
+                        ret = compare_div3(param, fout);
+                    }
+                    if (ret != 0) {
+                        param->nidiv    = *nidiv_list;
+                        param->nrd      = *nrd_list;
+                        param->nfd      = *nfd_list;
+                        param->nod      = *nod_list;
+                    }
+                    nod_list++;
+                }
+                nfd_list++;
+            }
+            nrd_list++;
+        }
+        nidiv_list++;
+    }
+}
+/**************************************************************************//**
+ * @brief       PLL value Calculation function
+ * @param[in]   InClock     : Input clock frequency [MHz]
+ * @param[in]   OuClock     : Output clock frequency [MHz]
+ * @param[in]   Lvds        : The LVDS output interface is used (=1) or not (=0)
+ * @param[out]  result      : pll_parameter_t
+ * @retval      error (-1)
+******************************************************************************/
+int32_t lvds_pll_calc(
+    const double      InClock,
+    const double      OuClock,
+    const uint32_t    Lvds,
+    pll_parameter_t * result  )
+{
+    result->comparison_freq  = 1000.0;
+    result->output_freq      = 0.0;
+    result->nidiv            = 0.0;
+    result->nrd              = 0.0;
+    result->nfd              = 0.0;
+    result->nod              = 0.0;
+    result->nodiv            = 0.0;
+
+    InputClock   = InClock;
+    OutputClock  = OuClock;
+    LvdsUsed     = Lvds;
+
+    /* Calculation */
+    SeekValue(result);
+
+    result->nidiv = result->nidiv/2;
+    result->nodiv = result->nodiv/2;
+    if( result->nod <= 4 ) {
+        result->nod = result->nod/2;
+    } else if( result->nod == 8 ) {
+        result->nod = 3;
+    } else {
+    }
+    result->nrd -=1;        /* nrd-1 */
+    return 0;
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/vdc5.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1373 @@
+/*******************************************************************************
+ * DISCLAIMER
+ * This software is supplied by Renesas Electronics Corporation and is only
+ * intended for use with Renesas products. No other uses are authorized. This
+ * software is owned by Renesas Electronics Corporation and is protected under
+ * all applicable laws, including copyright laws.
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+ * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+ * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+ * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+ * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+ * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+ * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+ * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ * Renesas reserves the right, without notice, to make changes to this software
+ * and to discontinue the availability of this software. By using this software,
+ * you agree to the additional terms and conditions found by accessing the
+ * following link:
+ * http://www.renesas.com/disclaimer
+ * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+ *******************************************************************************/
+/**************************************************************************//**
+ * @file         vdc5.c
+ * @version
+ * $Rev:
+ * $Date::
+ * @brief        VDC5 driver API wrapper function in C interface
+ ******************************************************************************/
+
+/******************************************************************************
+ Includes   <System Includes> , "Project Includes"
+ ******************************************************************************/
+#include    <stdio.h>
+#include    <string.h>
+
+#include    "r_typedefs.h"
+#include    "r_vdc5.h"
+#include    "video_decoder.h"
+#include    "lvds_pll_calc.h"
+#include    "vdc5.h"
+
+#include    "mbed_assert.h"
+#include    "pinmap.h"
+
+#include 	"lcd_panel.h"
+
+/******************************************************************************
+ Macro definitions
+ ******************************************************************************/
+#define STP91_BIT   (0x02u)
+#define STP90_BIT   (0x01u)
+#define STBRQ25_BIT (0x20u)
+#define STBAK25_BIT (0x20u)
+#define STBRQ24_BIT (0x10u)
+#define STBAK24_BIT (0x10u)
+
+/******************************************************************************
+ Typedef definitions
+ ******************************************************************************/
+typedef enum {
+	VDC5_CH0, VDC5_CH1,
+} VDC5Name;
+
+/******************************************************************************
+ Imported global variables and functions (from other files)
+ ******************************************************************************/
+
+/******************************************************************************
+ Exported global variables (to be accessed by other files)
+ ******************************************************************************/
+static const PinMap PinMap_DV_INPUT_PIN[] = { { P8_11, VDC5_CH0, 8 }, /* DV0_CLK    */
+{ P1_12, VDC5_CH0, 2 }, /* DV0_VSYNC  */
+{ P1_13, VDC5_CH0, 2 }, /* DV0_HSYNC  */
+{ P1_1, VDC5_CH0, 6 }, /* DV0_HSYNC  */
+{ P1_0, VDC5_CH0, 6 }, /* DV0_VSYNC  */
+{ P1_9, VDC5_CH0, 6 }, /* DV0_DATA15 */
+{ P2_15, VDC5_CH0, 3 }, /* DV0_DATA15 */
+{ P4_7, VDC5_CH0, 7 }, /* DV0_DATA15 */
+{ P5_7, VDC5_CH0, 4 }, /* DV0_DATA15 */
+{ P1_8, VDC5_CH0, 6 }, /* DV0_DATA14 */
+{ P2_14, VDC5_CH0, 3 }, /* DV0_DATA14 */
+{ P4_6, VDC5_CH0, 7 }, /* DV0_DATA14 */
+{ P5_6, VDC5_CH0, 4 }, /* DV0_DATA14 */
+{ P1_7, VDC5_CH0, 6 }, /* DV0_DATA13 */
+{ P2_13, VDC5_CH0, 3 }, /* DV0_DATA13 */
+{ P4_5, VDC5_CH0, 7 }, /* DV0_DATA13 */
+{ P5_5, VDC5_CH0, 4 }, /* DV0_DATA13 */
+{ P1_6, VDC5_CH0, 6 }, /* DV0_DATA12 */
+{ P4_4, VDC5_CH0, 7 }, /* DV0_DATA12 */
+{ P5_4, VDC5_CH0, 4 }, /* DV0_DATA12 */
+{ P2_10, VDC5_CH0, 3 }, /* DV0_DATA10 */
+{ P2_9, VDC5_CH0, 3 }, /* DV0_DATA9  */
+{ P2_7, VDC5_CH0, 3 }, /* DV0_DATA7  */
+{ P2_6, VDC5_CH0, 3 }, /* DV0_DATA6  */
+{ P2_5, VDC5_CH0, 3 }, /* DV0_DATA5  */
+{ P2_4, VDC5_CH0, 3 }, /* DV0_DATA4  */
+{ P2_3, VDC5_CH0, 3 }, /* DV0_DATA3  */
+{ P2_2, VDC5_CH0, 3 }, /* DV0_DATA2  */
+{ P2_1, VDC5_CH0, 3 }, /* DV0_DATA1  */
+{ P2_0, VDC5_CH0, 3 }, /* DV0_DATA0  */
+{ NC, NC, 0 } };
+
+#ifdef MAX_PERI
+static const PinMap PinMap_LCD_DISP_PIN[] = {
+	{	P2_7 , VDC5_CH0, 8}, {P4_15 , VDC5_CH0, 1}, {P5_7 , VDC5_CH0, 3}, /* LCD0_DATA23 */
+	{	P2_6 , VDC5_CH0, 8}, {P4_14 , VDC5_CH0, 1}, {P5_6 , VDC5_CH0, 3}, /* LCD0_DATA22 */
+	{	P2_5 , VDC5_CH0, 8}, {P4_13 , VDC5_CH0, 1}, {P5_5 , VDC5_CH0, 3}, /* LCD0_DATA21 */
+	{	P2_4 , VDC5_CH0, 8}, {P4_12 , VDC5_CH0, 1}, {P5_4 , VDC5_CH0, 3}, /* LCD0_DATA20 */
+	{	P2_3 , VDC5_CH0, 8}, {P4_11 , VDC5_CH0, 1}, {P5_3 , VDC5_CH0, 3}, /* LCD0_DATA19 */
+	{	P2_2 , VDC5_CH0, 8}, {P4_10 , VDC5_CH0, 1}, {P5_2 , VDC5_CH0, 3}, /* LCD0_DATA18 */
+	{	P2_1 , VDC5_CH0, 8}, {P4_9 , VDC5_CH0, 1}, {P5_1 , VDC5_CH0, 3}, /* LCD0_DATA17 */
+	{	P2_0 , VDC5_CH0, 8}, {P4_8 , VDC5_CH0, 1}, {P5_0 , VDC5_CH0, 3}, /* LCD0_DATA16 */
+	{	P4_7 , VDC5_CH0, 1}, /* LCD0_DATA15 */
+	{	P4_6 , VDC5_CH0, 1}, /* LCD0_DATA14 */
+	{	P4_5 , VDC5_CH0, 1}, /* LCD0_DATA13 */
+	{	P4_4 , VDC5_CH0, 1}, /* LCD0_DATA12 */
+	{	P4_3 , VDC5_CH0, 1}, /* LCD0_DATA11 */
+	{	P4_2 , VDC5_CH0, 1}, /* LCD0_DATA10 */
+	{	P4_1 , VDC5_CH0, 1}, /* LCD0_DATA9  */
+	{	P4_0 , VDC5_CH0, 1}, /* LCD0_DATA8  */
+	{	P3_15 , VDC5_CH0, 1}, {P6_15 , VDC5_CH0, 6}, /* LCD0_DATA7  */
+	{	P3_14 , VDC5_CH0, 1}, {P6_14 , VDC5_CH0, 6}, /* LCD0_DATA6  */
+	{	P3_13 , VDC5_CH0, 1}, {P6_13 , VDC5_CH0, 6}, /* LCD0_DATA5  */
+	{	P3_12 , VDC5_CH0, 1}, {P6_12 , VDC5_CH0, 6}, /* LCD0_DATA4  */
+	{	P3_11 , VDC5_CH0, 1}, {P6_11 , VDC5_CH0, 6}, /* LCD0_DATA3  */
+	{	P3_10 , VDC5_CH0, 1}, {P6_10 , VDC5_CH0, 6}, /* LCD0_DATA2  */
+	{	P3_9 , VDC5_CH0, 1}, {P6_9 , VDC5_CH0, 6}, /* LCD0_DATA1  */
+	{	P3_8 , VDC5_CH0, 1}, {P6_8 , VDC5_CH0, 6}, /* LCD0_DATA0  */
+	{	P3_7 , VDC5_CH0, 1}, {P6_7 , VDC5_CH0, 4}, {P2_8 , VDC5_CH0, 5}, /* LCD0_TCON6  {P6_11 , VDC5_CH0, 4} */
+	{	P3_6 , VDC5_CH0, 1}, {P6_6 , VDC5_CH0, 4}, /* LCD0_TCON5  {P6_10 , VDC5_CH0, 4} */
+	{	P3_5 , VDC5_CH0, 1}, /* LCD0_TCON4  */
+	{	P3_4 , VDC5_CH0, 1}, /* LCD0_TCON3  */
+	{	P3_3 , VDC5_CH0, 1}, /* LCD0_TCON2  */
+	{	P3_2 , VDC5_CH0, 1}, /* LCD0_TCON1  */
+	{	P3_1 , VDC5_CH0, 1}, /* LCD0_TCON0  */
+	{	P3_0 , VDC5_CH0, 1}, /* LCD0_CLK    */
+	{	P5_8 , VDC5_CH0, 1}, /* LCD0_EXTCLK */
+	{	NC , NC , 0}
+};
+#else
+static const PinMap PinMap_LCD_DISP_PIN[] = {
+//R
+		{ P4_7, VDC5_CH0, 1 }, /* LCD0_DATA15  */
+		{ P4_6, VDC5_CH0, 1 }, /* LCD0_DATA14  */
+		{ P4_5, VDC5_CH0, 1 }, /* LCD0_DATA13  */
+		{ P4_4, VDC5_CH0, 1 }, /* LCD0_DATA12  */
+		{ P4_3, VDC5_CH0, 1 }, /* LCD0_DATA11  */
+		//G
+		{ P4_2, VDC5_CH0, 1 }, /* LCD0_DATA10  */
+		{ P4_1, VDC5_CH0, 1 }, /* LCD0_DATA9   */
+		{ P4_0, VDC5_CH0, 1 }, /* LCD0_DATA8   */
+		{ P3_15, VDC5_CH0, 1 }, /* LCD0_DATA7   */
+		{ P3_14, VDC5_CH0, 1 }, /* LCD0_DATA6   */
+		{ P3_13, VDC5_CH0, 1 }, /* LCD0_DATA5   */
+		//B
+		{ P3_12, VDC5_CH0, 1 }, /* LCD0_DATA4   */
+		{ P3_11, VDC5_CH0, 1 }, /* LCD0_DATA3   */
+		{ P3_10, VDC5_CH0, 1 }, /* LCD0_DATA2   */
+		{ P3_9, VDC5_CH0, 1 }, /* LCD0_DATA1   */
+		{ P3_8, VDC5_CH0, 1 }, /* LCD0_DATA0   */
+		//DE
+		{ P3_1, VDC5_CH0, 1 }, /* LCD0_TCON0   */
+		{ P3_0, VDC5_CH0, 1 }, /* LCD0_CLK     */
+		{ NC, NC, 0 } };
+#endif
+
+#if 0
+static const PinMap PinMap_LCD_DISP_PIN[] = {
+	{	P2_7 , VDC5_CH0, 8}, /* LCD0_DATA23  */
+	{	P5_7 , VDC5_CH0, 3}, /* LCD0_DATA23  */
+	{	P2_6 , VDC5_CH0, 8}, /* LCD0_DATA22  */
+	{	P5_6 , VDC5_CH0, 3}, /* LCD0_DATA22  */
+	{	P2_5 , VDC5_CH0, 8}, /* LCD0_DATA21  */
+	{	P5_5 , VDC5_CH0, 3}, /* LCD0_DATA21  */
+	{	P2_4 , VDC5_CH0, 8}, /* LCD0_DATA20  */
+	{	P5_4 , VDC5_CH0, 3}, /* LCD0_DATA20  */
+	{	P2_3 , VDC5_CH0, 8}, /* LCD0_DATA19  */
+	{	P5_3 , VDC5_CH0, 3}, /* LCD0_DATA19  */
+	{	P2_2 , VDC5_CH0, 8}, /* LCD0_DATA18  */
+	{	P5_2 , VDC5_CH0, 3}, /* LCD0_DATA18  */
+	{	P2_1 , VDC5_CH0, 8}, /* LCD0_DATA17  */
+	{	P5_1 , VDC5_CH0, 3}, /* LCD0_DATA17  */
+	{	P2_0 , VDC5_CH0, 8}, /* LCD0_DATA16  */
+	{	P5_0 , VDC5_CH0, 3}, /* LCD0_DATA16  */
+	{	P4_7 , VDC5_CH0, 1}, /* LCD0_DATA15  */
+	{	P4_6 , VDC5_CH0, 1}, /* LCD0_DATA14  */
+	{	P4_5 , VDC5_CH0, 1}, /* LCD0_DATA13  */
+	{	P4_4 , VDC5_CH0, 1}, /* LCD0_DATA12  */
+	{	P4_0 , VDC5_CH0, 1}, /* LCD0_DATA8   */
+	{	P3_15 , VDC5_CH0, 1}, /* LCD0_DATA7   */
+	{	P3_14 , VDC5_CH0, 1}, /* LCD0_DATA6   */
+	{	P3_13 , VDC5_CH0, 1}, /* LCD0_DATA5   */
+	{	P3_12 , VDC5_CH0, 1}, /* LCD0_DATA4   */
+	{	P3_11 , VDC5_CH0, 1}, /* LCD0_DATA3   */
+	{	P3_10 , VDC5_CH0, 1}, /* LCD0_DATA2   */
+	{	P3_9 , VDC5_CH0, 1}, /* LCD0_DATA1   */
+	{	P3_8 , VDC5_CH0, 1}, /* LCD0_DATA0   */
+	{	P3_2 , VDC5_CH0, 1}, /* LCD0_TCON1   */
+	{	NC , NC , 0}
+};
+#endif
+
+static const PinMap PinMap_LVDS_DISP_PIN[] = { { P5_7, VDC5_CH0, 1 }, /* TXOUT0M   */
+{ P5_6, VDC5_CH0, 1 }, /* TXOUT0P   */
+{ P5_5, VDC5_CH0, 1 }, /* TXOUT1M   */
+{ P5_4, VDC5_CH0, 1 }, /* TXOUT1P   */
+{ P5_3, VDC5_CH0, 1 }, /* TXOUT2M   */
+{ P5_2, VDC5_CH0, 1 }, /* TXOUT2P   */
+{ P5_1, VDC5_CH0, 1 }, /* TXCLKOUTM */
+{ P5_0, VDC5_CH0, 1 }, /* TXCLKOUTP */
+{ NC, NC, 0 } };
+
+static const IRQn_Type vdc5_irq_set_tbl[] = { S0_VI_VSYNC0_IRQn,
+		S0_LO_VSYNC0_IRQn, S0_VSYNCERR0_IRQn, GR3_VLINE0_IRQn, S0_VFIELD0_IRQn,
+		IV1_VBUFERR0_IRQn, IV3_VBUFERR0_IRQn, IV5_VBUFERR0_IRQn,
+		IV6_VBUFERR0_IRQn, S0_WLINE0_IRQn, S1_VI_VSYNC0_IRQn, S1_LO_VSYNC0_IRQn,
+		S1_VSYNCERR0_IRQn, S1_VFIELD0_IRQn, IV2_VBUFERR0_IRQn,
+		IV4_VBUFERR0_IRQn, S1_WLINE0_IRQn, OIR_VI_VSYNC0_IRQn,
+		OIR_LO_VSYNC0_IRQn, OIR_VSYNCERR0_IRQn, OIR_VFIELD0_IRQn,
+		IV7_VBUFERR0_IRQn, IV8_VBUFERR0_IRQn };
+
+/******************************************************************************
+ Private global variables and functions
+ ******************************************************************************/
+static void init_func(const uint32_t user_num);
+static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable);
+
+/**************************************************************************//**
+ * @brief       User-defined function within R_VDC5_Initialize
+ * @param[in]   user_num                : VDC5 channel
+ * @retval      None
+ ******************************************************************************/
+static void init_func(const uint32_t user_num) {
+	uint32_t reg_data;
+	volatile uint8_t dummy_read;
+
+	if ((vdc5_channel_t) user_num == VDC5_CHANNEL_0) {
+
+		/* Standby control register 9 (STBCR9)
+		 b1      ------0-;  MSTP91 : 0 : Video display controller channel 0 & LVDS enable */
+		reg_data = (uint32_t) CPG.STBCR9 & (uint32_t) ~STP91_BIT;
+		CPG.STBCR9 = (uint8_t) reg_data;
+		/* In order to reflect the change, a dummy read should be done. */
+		dummy_read = CPG.STBCR9;
+
+		/* Standby Request Register 2 (STBREQ2)
+		 b5      --0-----;  STBRQ25 : The standby request to VDC5 channel 0 is invalid. */
+		reg_data = (uint32_t) CPG.STBREQ2 & (uint32_t) ~STBRQ25_BIT;
+		CPG.STBREQ2 = (uint8_t) reg_data;
+		/* Standby Acknowledge Register 2 (STBACK2)
+		 b5      --*-----;  STBAK25 : Standby acknowledgement from VDC5 channel 0. */
+		while (((uint32_t) CPG.STBACK2 & (uint32_t) STBAK25_BIT) != 0u) {
+			/* Wait for the STBAK25 to be cleared to 0. */
+		}
+
+		/* Standby control register 9 (STBCR9)
+		 b0      -------0;  MSTP90 : 0 : Video display controller channel 1 enable */
+		reg_data = (uint32_t) CPG.STBCR9 & (uint32_t) ~(STP91_BIT | STP90_BIT);
+		CPG.STBCR9 = (uint8_t) reg_data;
+		/* In order to reflect the change, a dummy read should be done. */
+		dummy_read = CPG.STBCR9;
+
+		/* Standby Request Register 2 (STBREQ2)
+		 b4      ---0----;  STBRQ24 : The standby request to VDC5 channel 1 is invalid. */
+		reg_data = (uint32_t) CPG.STBREQ2 & (uint32_t) ~STBRQ24_BIT;
+		CPG.STBREQ2 = (uint8_t) reg_data;
+		/* Standby Acknowledge Register 2 (STBACK2)
+		 b4      ---*----;  STBAK24 : Standby acknowledgement from VDC5 channel 1. */
+		while (((uint32_t) CPG.STBACK2 & (uint32_t) STBAK24_BIT) != 0u) {
+			/* Wait for the STBAK24 to be cleared to 0. */
+		}
+	}
+} /* End of function init_func() */
+
+/**************************************************************************//**
+ * @brief       Interrupt service routine acquisition processing
+ *
+ *              Description:<br>
+ *              This function returns the function pointer to the specified interrupt service routine.
+ * @param[in]   irq                     : VDC5 interrupt type
+ * @param[in]   enable                  : VDC5 interrupt enable
+ * @retval      None
+ ******************************************************************************/
+static void DRV_Graphics_Irq_Set(vdc5_int_type_t irq, uint32_t enable) {
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	IRQn_Type IRQn;
+	IRQHandler handler;
+
+	IRQn = vdc5_irq_set_tbl[irq];
+	handler = R_VDC5_GetISR(ch, irq);
+
+	if (enable) {
+		InterruptHandlerRegister(IRQn, (void (*)(uint32_t)) handler);
+		GIC_SetPriority(IRQn, 5);
+		GIC_EnableIRQ(IRQn);
+	} else {
+		GIC_DisableIRQ(IRQn);
+	}
+} /* End of function DRV_Graphics_Irq_Set() */
+
+/**************************************************************************//**
+ * @brief       Interrupt callback setup
+ *              This function performs the following processing:
+ *              - Enables the interrupt when the pointer to the corresponding interrupt callback function is specified.
+ *              - Registers the specified interrupt callback function.
+ *              - Disables the interrupt when the pointer to the corresponding interrupt callback function is not
+ *                specified.
+ * @param[in]   irq                     : VDC5 interrupt type
+ * @param[in]   num                     : Interrupt line number
+ * @param[in]   * callback              : Interrupt callback function pointer
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Irq_Handler_Set(vdc5_int_type_t irq,
+		uint16_t num, void (*callback)(vdc5_int_type_t)) {
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_error_t error;
+	vdc5_int_t interrupt;
+
+	if (callback == NULL) {
+		DRV_Graphics_Irq_Set(irq, 0);
+	} else {
+		DRV_Graphics_Irq_Set(irq, 1);
+	}
+
+	/* Interrupt parameter */
+	interrupt.type = irq; /* Interrupt type */
+	interrupt.line_num = num; /* Line number */
+
+	/* Interrupt parameter */
+	interrupt.callback = callback; /* Callback function pointer */
+	/* Set interrupt service routine */
+	error = R_VDC5_CallbackISR(ch, &interrupt);
+	if (error != VDC5_OK) {
+		drv_error = DRV_GRAPHICS_VDC5_ERR;
+	}
+	return drv_error;
+} /* End of function DRV_Graphics_Irq_Handler_Set() */
+
+/**************************************************************************//**
+ * @brief       LCD output port initialization processing
+ * @param[in]   pin                     : Pin assign for LCD output
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Lcd_Port_Init(PinName *pin,
+		uint32_t pin_count) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	uint32_t count;
+
+	for (count = 0; count < pin_count; count++) {
+		pinmap_peripheral(pin[count], PinMap_LCD_DISP_PIN);
+		pinmap_pinout(pin[count], PinMap_LCD_DISP_PIN);
+	}
+	return drv_error;
+} /* End of function DRV_Graphics_Lcd_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       LVDS output port initialization processing
+ * @param[in]   pin                     : Pin assign for LVDS output
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Lvds_Port_Init(PinName *pin,
+		uint32_t pin_count) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	uint32_t count;
+
+	for (count = 0; count < pin_count; count++) {
+		pinmap_peripheral(pin[count], PinMap_LVDS_DISP_PIN);
+		pinmap_pinout(pin[count], PinMap_LVDS_DISP_PIN);
+	}
+	return drv_error;
+} /* End of function DRV_Graphics_Lvds_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       Digital video inpout port initialization processing
+ * @param[in]   pin                     : Pin assign for digital video input port
+ * @param[in]   pin_count               : Total number of pin assign
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init(PinName *pin,
+		uint32_t pin_count) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	uint32_t count;
+
+	for (count = 0; count < pin_count; count++) {
+		pinmap_peripheral(pin[count], PinMap_DV_INPUT_PIN);
+		pinmap_pinout(pin[count], PinMap_DV_INPUT_PIN);
+	}
+	return drv_error;
+} /* End of function DRV_Graphics_Dvinput_Port_Init() */
+
+/**************************************************************************//**
+ * @brief       Graphics initialization processing
+ * @param[in]   drv_lcd_config          : LCD configuration
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Init(drv_lcd_config_t * drv_lcd_config) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	vdc5_error_t error;
+	vdc5_init_t init;
+	vdc5_lvds_t vdc5_lvds;
+	pll_parameter_t pll_parameter;
+	double InputClock = DEFAULT_INPUT_CLOCK;
+	double OutputClock = DEFAULT_OUTPUT_CLOCK;
+	uint32_t LvdsUsed = LVDS_IF_USE;
+
+	if (drv_lcd_config != NULL) {
+		InputClock = drv_lcd_config->intputClock;
+		OutputClock = drv_lcd_config->outputClock;
+		LvdsUsed =
+				(drv_lcd_config->lcd_type == DRV_LCD_TYPE_LVDS) ?
+						LVDS_IF_USE : LVDS_IF_NOT_USE;
+	}
+
+	/* Initialization parameter */
+	if (LvdsUsed) {
+		/* LVDS PLL Setting Calculation */
+		init.panel_icksel = VDC5_PANEL_ICKSEL_LVDS_DIV7; /* Panel clock select */
+		init.panel_dcdr = VDC5_PANEL_CLKDIV_1_2; /* Panel clock frequency division ratio */
+		lvds_pll_calc(InputClock, OutputClock, LvdsUsed, &pll_parameter);
+
+		vdc5_lvds.lvds_in_clk_sel = VDC5_LVDS_INCLK_SEL_PERI; /* P1 */
+		vdc5_lvds.lvds_idiv_set = (vdc5_lvds_ndiv_t) pll_parameter.nidiv;
+		vdc5_lvds.lvdspll_tst = 16u;
+		vdc5_lvds.lvds_odiv_set = (vdc5_lvds_ndiv_t) pll_parameter.nodiv;
+		vdc5_lvds.lvdspll_tst = 16u;
+		vdc5_lvds.lvds_vdc_sel = ch;
+		vdc5_lvds.lvdspll_fd = pll_parameter.nfd;
+		vdc5_lvds.lvdspll_rd = pll_parameter.nrd;
+		vdc5_lvds.lvdspll_od = (vdc5_lvds_pll_nod_t) pll_parameter.nod;
+		init.lvds = &vdc5_lvds; /* LVDS parameter */
+	} else {
+		init.panel_icksel = VDC5_PANEL_ICKSEL_PERI; /* Panel clock select */
+		init.panel_dcdr = VDC5_PANEL_CLKDIV_1_7; /* Panel clock frequency division ratio */
+		init.lvds = NULL;
+	}
+
+	/* Initialize (Set module clock to VDC5) */
+	error = R_VDC5_Initialize(ch, &init, &init_func, (uint32_t) ch);
+	if (error != VDC5_OK) {
+		drv_error = DRV_GRAPHICS_VDC5_ERR;
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		vdc5_sync_ctrl_t sync_ctrl;
+
+		/* Sync signal control */
+		sync_ctrl.res_vs_sel = VDC5_ON; /* Vsync signal output select (free-running Vsync on/off control) */
+		/* Sync signal output and full-screen enable signal select */
+		sync_ctrl.res_vs_in_sel = VDC5_RES_VS_IN_SEL_SC0;
+		sync_ctrl.res_fv = drv_lcd_config->v_toatal_period - 1; /* Free-running Vsync period setting */
+		sync_ctrl.res_fh = drv_lcd_config->h_toatal_period - 1; /* Hsync period setting */
+		sync_ctrl.res_vsdly = (uint16_t) 0u; /* Vsync signal delay control */
+		/* Full-screen enable control */
+		sync_ctrl.res_f.vs = (drv_lcd_config->v_back_porch);
+		sync_ctrl.res_f.vw = (drv_lcd_config->v_disp_widht);
+		sync_ctrl.res_f.hs = (drv_lcd_config->h_back_porch);
+		sync_ctrl.res_f.hw = (drv_lcd_config->h_disp_widht);
+		sync_ctrl.vsync_cpmpe = NULL; /* Vsync signal compensation */
+		/* Sync control */
+		error = R_VDC5_SyncControl(ch, &sync_ctrl);
+		if (error != VDC5_OK) {
+			drv_error = DRV_GRAPHICS_VDC5_ERR;
+		}
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		vdc5_output_t output;
+		vdc5_lcd_tcon_timing_t lcd_tcon_timing_VS;
+		vdc5_lcd_tcon_timing_t lcd_tcon_timing_VE;
+		vdc5_lcd_tcon_timing_t lcd_tcon_timing_HS;
+		vdc5_lcd_tcon_timing_t lcd_tcon_timing_HE;
+		vdc5_lcd_tcon_timing_t lcd_tcon_timing_DE;
+
+		/* Output parameter */
+		output.tcon_half = (drv_lcd_config->h_toatal_period - 1) / 2; /* TCON reference timing, 1/2fH timing */
+		output.tcon_offset = 0; /* TCON reference timing, offset Hsync signal timing */
+
+		/* LCD TCON timing setting */
+		if (drv_lcd_config->v_sync_port != DRV_LCD_TCON_PIN_NON) {
+			lcd_tcon_timing_VS.tcon_hsvs = 0u;
+			lcd_tcon_timing_VS.tcon_hwvw = (drv_lcd_config->v_sync_width * 2u);
+			lcd_tcon_timing_VS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
+			lcd_tcon_timing_VS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+			lcd_tcon_timing_VS.tcon_inv =
+					(vdc5_sig_pol_t) drv_lcd_config->v_sync_port_polarity;
+			lcd_tcon_timing_VS.tcon_pin =
+					(vdc5_lcd_tcon_pin_t) drv_lcd_config->v_sync_port;
+			lcd_tcon_timing_VS.outcnt_edge = VDC5_EDGE_FALLING;
+			output.outctrl[VDC5_LCD_TCONSIG_STVA_VS] = &lcd_tcon_timing_VS; /* STVA/VS: Vsync      */
+		} else {
+			output.outctrl[VDC5_LCD_TCONSIG_STVA_VS] = NULL; /* STVA/VS: Vsync      */
+		}
+
+		if (drv_lcd_config->h_sync_port != DRV_LCD_TCON_PIN_NON) {
+			lcd_tcon_timing_HS.tcon_hsvs = 0u;
+			lcd_tcon_timing_HS.tcon_hwvw = drv_lcd_config->h_sync_width;
+			lcd_tcon_timing_HS.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
+			lcd_tcon_timing_HS.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+			lcd_tcon_timing_HS.tcon_inv =
+					(vdc5_sig_pol_t) drv_lcd_config->h_sync_port_polarity;
+			lcd_tcon_timing_HS.tcon_pin =
+					(vdc5_lcd_tcon_pin_t) drv_lcd_config->h_sync_port;
+			lcd_tcon_timing_HS.outcnt_edge = VDC5_EDGE_FALLING;
+			output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = &lcd_tcon_timing_HS; /* STH/SP/HS: Hsync       */
+		} else {
+			output.outctrl[VDC5_LCD_TCONSIG_STH_SP_HS] = NULL; /* STH/SP/HS: Hsync       */
+		}
+
+		if (drv_lcd_config->de_port != DRV_LCD_TCON_PIN_NON) {
+			lcd_tcon_timing_VE.tcon_hsvs = (drv_lcd_config->v_back_porch * 2u);
+			lcd_tcon_timing_VE.tcon_hwvw = (drv_lcd_config->v_disp_widht * 2u);
+			lcd_tcon_timing_VE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
+			lcd_tcon_timing_VE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+			lcd_tcon_timing_VE.tcon_inv =
+					(vdc5_sig_pol_t) drv_lcd_config->de_port_polarity;
+			lcd_tcon_timing_VE.tcon_pin = VDC5_LCD_TCON_PIN_NON;
+			lcd_tcon_timing_VE.outcnt_edge = VDC5_EDGE_FALLING;
+			output.outctrl[VDC5_LCD_TCONSIG_STVB_VE] = &lcd_tcon_timing_VE; /* STVB/VE: Not used   */
+
+			lcd_tcon_timing_HE.tcon_hsvs = drv_lcd_config->h_back_porch;
+			lcd_tcon_timing_HE.tcon_hwvw = drv_lcd_config->h_disp_widht;
+			lcd_tcon_timing_HE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
+			lcd_tcon_timing_HE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+			lcd_tcon_timing_HE.tcon_inv =
+					(vdc5_sig_pol_t) drv_lcd_config->de_port_polarity;
+			lcd_tcon_timing_HE.tcon_pin = VDC5_LCD_TCON_PIN_NON;
+			lcd_tcon_timing_HE.outcnt_edge = VDC5_EDGE_FALLING;
+			output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = &lcd_tcon_timing_HE; /* STB/LP/HE: Not used */
+
+			lcd_tcon_timing_DE.tcon_hsvs = 0u;
+			lcd_tcon_timing_DE.tcon_hwvw = 0u;
+			lcd_tcon_timing_DE.tcon_md = VDC5_LCD_TCON_POLMD_NORMAL;
+			lcd_tcon_timing_DE.tcon_hs_sel = VDC5_LCD_TCON_REFSEL_HSYNC;
+			lcd_tcon_timing_DE.tcon_inv =
+					(vdc5_sig_pol_t) drv_lcd_config->de_port_polarity;
+			lcd_tcon_timing_DE.tcon_pin =
+					(vdc5_lcd_tcon_pin_t) drv_lcd_config->de_port;
+			lcd_tcon_timing_DE.outcnt_edge = VDC5_EDGE_FALLING;
+			output.outctrl[VDC5_LCD_TCONSIG_DE] = &lcd_tcon_timing_DE; /* DE      */
+		} else {
+			output.outctrl[VDC5_LCD_TCONSIG_STVB_VE] = NULL; /* STVB/VE: Not used   */
+			output.outctrl[VDC5_LCD_TCONSIG_STB_LP_HE] = NULL; /* STB/LP/HE: Not used */
+			output.outctrl[VDC5_LCD_TCONSIG_DE] = NULL; /* DE                  */
+		}
+
+		output.outctrl[VDC5_LCD_TCONSIG_CPV_GCK] = NULL;
+		output.outctrl[VDC5_LCD_TCONSIG_POLA] = NULL;
+		output.outctrl[VDC5_LCD_TCONSIG_POLB] = NULL;
+
+		output.outcnt_lcd_edge = (vdc5_edge_t) drv_lcd_config->lcd_edge; /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+		output.out_endian_on = VDC5_OFF; /* Bit endian change on/off control */
+		output.out_swap_on = VDC5_OFF; /* B/R signal swap on/off control */
+		output.out_format =
+				(vdc5_lcd_outformat_t) drv_lcd_config->lcd_outformat; /* Output format select */
+		output.out_frq_sel = VDC5_LCD_PARALLEL_CLKFRQ_1; /* Clock frequency control */
+		output.out_dir_sel = VDC5_LCD_SERIAL_SCAN_FORWARD; /* Scan direction select */
+		output.out_phase = VDC5_LCD_SERIAL_CLKPHASE_0; /* Clock phase adjustment */
+		output.bg_color = (uint32_t) 0x00000000u; /* Background color in 24-bit RGB color format */
+		/* Display output */
+		error = R_VDC5_DisplayOutput(ch, &output);
+		if (error != VDC5_OK) {
+			drv_error = DRV_GRAPHICS_VDC5_ERR;
+		}
+	}
+	return drv_error;
+} /* End of function DRV_Graphics_Init() */
+
+/**************************************************************************//**
+ * @brief       Video initialization processing
+ * @param[in]   drv_video_ext_in_config   : Video configuration
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Video_init(
+		drv_video_input_sel_t drv_video_input_sel,
+		drv_video_ext_in_config_t * drv_video_ext_in_config) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_error_t error;
+	vdc5_input_t input;
+	vdc5_ext_in_sig_t ext_in_sig;
+	vdc5_sync_delay_t sync_delay;
+
+	input.inp_sel = (vdc5_input_sel_t) drv_video_input_sel; /* Input select */
+	input.inp_fh50 = (uint16_t) VSYNC_1_2_FH_TIMING; /* Vsync signal 1/2fH phase timing */
+	input.inp_fh25 = (uint16_t) VSYNC_1_4_FH_TIMING; /* Vsync signal 1/4fH phase timing */
+
+	if (drv_video_input_sel == DRV_INPUT_SEL_VDEC) {
+		input.dly = NULL; /* Sync signal delay adjustment */
+		input.ext_sig = NULL; /* External input signal        */
+	} else {
+		ext_in_sig.inp_format =
+				(vdc5_extin_format_t) drv_video_ext_in_config->inp_format;
+		ext_in_sig.inp_pxd_edge =
+				(vdc5_edge_t) drv_video_ext_in_config->inp_pxd_edge;
+		ext_in_sig.inp_vs_edge =
+				(vdc5_edge_t) drv_video_ext_in_config->inp_vs_edge;
+		ext_in_sig.inp_hs_edge =
+				(vdc5_edge_t) drv_video_ext_in_config->inp_hs_edge;
+		ext_in_sig.inp_endian_on =
+				(vdc5_onoff_t) drv_video_ext_in_config->inp_endian_on;
+		ext_in_sig.inp_swap_on =
+				(vdc5_onoff_t) drv_video_ext_in_config->inp_swap_on;
+		ext_in_sig.inp_vs_inv =
+				(vdc5_sig_pol_t) drv_video_ext_in_config->inp_vs_inv;
+		ext_in_sig.inp_hs_inv =
+				(vdc5_sig_pol_t) drv_video_ext_in_config->inp_hs_inv;
+		ext_in_sig.inp_h_edge_sel =
+				(vdc5_extin_ref_hsync_t) drv_video_ext_in_config->inp_hs_edge;
+		ext_in_sig.inp_f525_625 =
+				(vdc5_extin_input_line_t) drv_video_ext_in_config->inp_f525_625;
+		ext_in_sig.inp_h_pos =
+				(vdc5_extin_h_pos_t) drv_video_ext_in_config->inp_h_pos;
+
+		sync_delay.inp_vs_dly_l = 0u;
+		sync_delay.inp_vs_dly = 16u;
+		sync_delay.inp_hs_dly = 16u;
+		sync_delay.inp_fld_dly = 16u;
+
+		input.dly = &sync_delay; /* Sync signal delay adjustment */
+		input.ext_sig = &ext_in_sig; /* External input signal        */
+	}
+	/* Video input 0ch */
+	error = R_VDC5_VideoInput(VDC5_CHANNEL_0, &input);
+	if (error != VDC5_OK) {
+		drv_error = DRV_GRAPHICS_VDC5_ERR;
+	}
+
+	if (drv_video_input_sel == DRV_INPUT_SEL_VDEC) {
+		if (drv_error == DRV_GRAPHICS_OK) {
+			/* Video input 1ch */
+			error = R_VDC5_VideoInput(VDC5_CHANNEL_1, &input);
+			if (error != VDC5_OK) {
+				drv_error = DRV_GRAPHICS_VDC5_ERR;
+			}
+		}
+	}
+	return drv_error;
+} /* End of function DRV_Video_Init() */
+
+/**************************************************************************//**
+ * @brief       Start the graphics surface read process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @retval      drv_graphics_error_t
+ ******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Start(drv_graphics_layer_t layer_id) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	vdc5_error_t error;
+	vdc5_start_t start;
+	vdc5_gr_disp_sel_t gr_disp_sel;
+	vdc5_layer_id_t vdc5_layer_id;
+
+	switch (layer_id) {
+	case DRV_GRAPHICS_LAYER_0:
+		vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+		gr_disp_sel = VDC5_DISPSEL_CURRENT;
+		break;
+	case DRV_GRAPHICS_LAYER_1:
+		vdc5_layer_id = VDC5_LAYER_ID_1_RD;
+		gr_disp_sel = VDC5_DISPSEL_BLEND;
+		break;
+	case DRV_GRAPHICS_LAYER_2:
+		vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+		gr_disp_sel = VDC5_DISPSEL_BLEND;
+		break;
+	case DRV_GRAPHICS_LAYER_3:
+		vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+		gr_disp_sel = VDC5_DISPSEL_BLEND;
+		break;
+	default:
+		drv_error = DRV_GRAPHICS_LAYER_ERR;
+		break;
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		/* Start process */
+		start.gr_disp_sel = &gr_disp_sel;
+		error = R_VDC5_StartProcess(ch, vdc5_layer_id, &start);
+		if (error != VDC5_OK) {
+			drv_error = DRV_GRAPHICS_VDC5_ERR;
+		}
+	}
+	return drv_error;
+} /* End of function DRV_Graphics_Start() */
+
+/**************************************************************************//**
+ * @brief       Stop the graphics surface read process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Stop(drv_graphics_layer_t layer_id) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	vdc5_error_t error;
+	vdc5_layer_id_t vdc5_layer_id;
+
+	switch (layer_id) {
+	case DRV_GRAPHICS_LAYER_0:
+		vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_1:
+		vdc5_layer_id = VDC5_LAYER_ID_1_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_2:
+		vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_3:
+		vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+		break;
+	default:
+		drv_error = DRV_GRAPHICS_LAYER_ERR;
+		break;
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		/* Stop process */
+		error = R_VDC5_StopProcess(ch, vdc5_layer_id);
+		if (error != VDC5_OK) {
+			drv_error = DRV_GRAPHICS_VDC5_ERR;
+		}
+	}
+	return drv_error;
+} /* End of function DRV_Graphics_Stop() */
+
+/**************************************************************************//**
+ * @brief      Start the video surface write process
+ * @param[in]   video_input_ch          : Video input channel
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Video_Start(drv_video_input_channel_t video_input_ch) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	vdc5_error_t error;
+	vdc5_start_t start;
+	vdc5_gr_disp_sel_t gr_disp_sel;
+	vdc5_layer_id_t vdc5_layer_id;
+
+	if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0) {
+		vdc5_layer_id = VDC5_LAYER_ID_0_WR;
+	} else if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1) {
+		vdc5_layer_id = VDC5_LAYER_ID_1_WR;
+	} else {
+		drv_error = DRV_GRAPHICS_LAYER_ERR;
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		/* Start process */
+		gr_disp_sel = VDC5_DISPSEL_CURRENT; /* CURRENT fixed for weave input mode */
+		start.gr_disp_sel = &gr_disp_sel;
+		error = R_VDC5_StartProcess(ch, vdc5_layer_id, &start);
+		if (error != VDC5_OK) {
+			drv_error = DRV_GRAPHICS_VDC5_ERR;
+		}
+	}
+	return drv_error;
+} /* End of function DRV_Video_Start() */
+
+/**************************************************************************//**
+ * @brief       Stop the video surface write process
+ * @param[in]   video_input_ch          : Video input channel
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Video_Stop(drv_video_input_channel_t video_input_ch) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	vdc5_error_t error;
+	vdc5_layer_id_t vdc5_layer_id;
+
+	switch (video_input_ch) {
+	case DRV_VIDEO_INPUT_CHANNEL_0:
+		vdc5_layer_id = VDC5_LAYER_ID_0_WR;
+		break;
+	case DRV_VIDEO_INPUT_CHANNEL_1:
+		vdc5_layer_id = VDC5_LAYER_ID_1_WR;
+		break;
+	default:
+		drv_error = DRV_GRAPHICS_LAYER_ERR;
+		break;
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		/* Stop process */
+		error = R_VDC5_StopProcess(ch, vdc5_layer_id);
+		if (error != VDC5_OK) {
+			drv_error = DRV_GRAPHICS_VDC5_ERR;
+		}
+	}
+	return drv_error;
+} /* End of function DRV_Video_Stop() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read process setting
+ *
+ *              Description:<br>
+ *              This function supports the following 4 image format.
+ *                  YCbCr422, RGB565, RGB888, ARGB8888
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride               : Line offset address of the frame buffer
+ * @param[in]   gr_format               : Format of the frame buffer read signal
+ * @param[in]   gr_rect                 : Graphics display area
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Read_Setting(drv_graphics_layer_t layer_id,
+		void * framebuff, uint32_t fb_stride, drv_graphics_format_t gr_format,
+		drv_wr_rd_swa_t wr_rd_swa, drv_rect_t * gr_rect) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	vdc5_error_t error;
+	vdc5_layer_id_t vdc5_layer_id;
+	vdc5_gr_format_t vdc5_gr_format;
+	vdc5_read_t read;
+
+	switch (layer_id) {
+	case DRV_GRAPHICS_LAYER_0:
+		vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_1:
+		vdc5_layer_id = VDC5_LAYER_ID_1_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_2:
+		vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_3:
+		vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+		break;
+	default:
+		drv_error = DRV_GRAPHICS_LAYER_ERR;
+		break;
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		switch (gr_format) {
+		case DRV_GRAPHICS_FORMAT_YCBCR422:
+			vdc5_gr_format = VDC5_GR_FORMAT_YCBCR422;
+			break;
+		case DRV_GRAPHICS_FORMAT_RGB565:
+			vdc5_gr_format = VDC5_GR_FORMAT_RGB565;
+			break;
+		case DRV_GRAPHICS_FORMAT_RGB888:
+			vdc5_gr_format = VDC5_GR_FORMAT_RGB888;
+			break;
+		case DRV_GRAPHICS_FORMAT_ARGB8888:
+			vdc5_gr_format = VDC5_GR_FORMAT_ARGB8888;
+			break;
+		case DRV_GRAPHICS_FORMAT_ARGB4444:
+			vdc5_gr_format = VDC5_GR_FORMAT_ARGB4444;
+			break;
+		default:
+			drv_error = DRV_GRAPHICS_FORMAT_ERR;
+			break;
+		}
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		/* Read data parameter */
+		read.gr_ln_off_dir = VDC5_GR_LN_OFF_DIR_INC; /* Line offset address direction of the frame buffer */
+		read.gr_flm_sel = VDC5_GR_FLM_SEL_FLM_NUM; /* Selects a frame buffer address setting signal */
+		read.gr_imr_flm_inv = VDC5_OFF; /* Frame buffer number for distortion correction */
+		read.gr_bst_md = VDC5_BST_MD_32BYTE; /* Frame buffer burst transfer mode */
+		read.gr_base = framebuff; /* Frame buffer base address */
+		read.gr_ln_off = fb_stride; /* Frame buffer line offset address */
+
+		read.width_read_fb = NULL; /* Width of the image read from frame buffer */
+
+		read.adj_sel = VDC5_OFF; /* Measures to decrease the influence
+		 by folding pixels/lines (on/off) */
+		read.gr_format = vdc5_gr_format; /* Format of the frame buffer read signal */
+		read.gr_ycc_swap = VDC5_GR_YCCSWAP_CBY0CRY1; /* Controls swapping of data read from buffer
+		 in the YCbCr422 format */
+		read.gr_rdswa = (vdc5_wr_rd_swa_t) wr_rd_swa; /* Frame buffer swap setting */
+		/* Display area */
+		read.gr_grc.vs = gr_rect->vs;
+		read.gr_grc.vw = gr_rect->vw;
+		read.gr_grc.hs = gr_rect->hs;
+		read.gr_grc.hw = gr_rect->hw;
+
+		/* Read data control */
+		error = R_VDC5_ReadDataControl(ch, vdc5_layer_id, &read);
+		if (error != VDC5_OK) {
+			drv_error = DRV_GRAPHICS_VDC5_ERR;
+		}
+	}
+	return drv_error;
+} /* End of function DRV_Graphics_Read_Setting() */
+
+/**************************************************************************//**
+ * @brief       Graphics surface read buffer change process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Read_Change(drv_graphics_layer_t layer_id,
+		void * framebuff) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	vdc5_error_t error;
+	vdc5_layer_id_t vdc5_layer_id;
+	vdc5_read_chg_t read_chg;
+
+	switch (layer_id) {
+	case DRV_GRAPHICS_LAYER_0:
+		vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_1:
+		vdc5_layer_id = VDC5_LAYER_ID_1_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_2:
+		vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_3:
+		vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+		break;
+	default:
+		drv_error = DRV_GRAPHICS_LAYER_ERR;
+		break;
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		/* Read data parameter */
+		read_chg.width_read_fb = NULL; /* Width of the image read from frame buffer */
+		read_chg.gr_grc = NULL; /* Display area */
+		read_chg.gr_disp_sel = NULL; /* Graphics display mode */
+		read_chg.gr_base = framebuff; /* Frame buffer base address */
+
+		/* Change read process */
+		error = R_VDC5_ChangeReadProcess(ch, vdc5_layer_id, &read_chg);
+		if (error != VDC5_OK) {
+			drv_error = DRV_GRAPHICS_VDC5_ERR;
+		}
+	}
+	return drv_error;
+} /* End of function DRV_Graphics_Read_Change() */
+
+//touch_pos_t dot_border
+void Slide(uint32_t fb_stride, vdc5_chg_read_chg_t * param, slide_dir_t* slide_dir) {
+
+#define SLIDE_STEP                   12
+
+	static int32_t v_line = 0; /* Vertical direction offset variable */
+	static int32_t h_pixel = 0; /* Horizontal direction offset variable */
+	int32_t stride_pix = fb_stride / LCD_CH0_DISP_HW; /* Size(px) of image buffer stride */
+	uint16_t *pos_buff = (uint16_t *) param->gr_base; /* Image buffer position */
+
+	/* Wait Vsync */
+
+	switch (*slide_dir) {
+	case SLIDE_OUT_RIGHT:
+		h_pixel += SLIDE_STEP; /* Increment offset value : 0u -> 800u by 16u step */
+		if (h_pixel >= LCD_CH0_DISP_HW) /* 800u */
+		{
+			h_pixel = LCD_CH0_DISP_HW;
+			*slide_dir = SLIDE_NONE;
+		}
+		param->gr_grc->hs = (uint16_t) ((int32_t) LCD_CH0_DISP_HS + h_pixel);
+		param->gr_grc->hw = (uint16_t) ((int32_t) LCD_CH0_DISP_HW - h_pixel);
+		break;
+	case SLIDE_IN_RIGHT:
+		h_pixel -= SLIDE_STEP; /* Decrement offset value : 800u -> 0u by 16u step */
+		if (h_pixel <= 0) /* 0u */
+		{
+			h_pixel = 0;
+			*slide_dir = SLIDE_NONE;;
+		}
+		param->gr_grc->hs = (uint16_t) ((int32_t) LCD_CH0_DISP_HS + h_pixel);
+		param->gr_grc->hw = (uint16_t) ((int32_t) LCD_CH0_DISP_HW - h_pixel);
+		break;
+
+	case SLIDE_OUT_BOTTOM:
+		v_line += SLIDE_STEP; /* Increment offset value : 0u -> 600u by 16u step */
+		if (v_line >= LCD_CH0_DISP_VW) /* 600u */
+		{
+			v_line = LCD_CH0_DISP_VW;
+			*slide_dir = SLIDE_NONE;;
+		}
+		param->gr_grc->vs = (uint16_t) ((int32_t) LCD_CH0_DISP_VS + v_line);
+		param->gr_grc->vw = (uint16_t) ((int32_t) LCD_CH0_DISP_VW - v_line);
+		break;
+	case SLIDE_IN_BOTTOM:
+		v_line -= SLIDE_STEP; /* Decrement offset value : 600u -> 0u by 16u step */
+		if (v_line <= 0) /* 0u */
+		{
+			v_line = 0;
+			*slide_dir = SLIDE_NONE;;
+		}
+		param->gr_grc->vs = (uint16_t) ((int32_t) LCD_CH0_DISP_VS + v_line);
+		param->gr_grc->vw = (uint16_t) ((int32_t) LCD_CH0_DISP_VW - v_line);
+		break;
+
+	case SLIDE_OUT_LEFT:
+		h_pixel += SLIDE_STEP; /* Increment offset value : 0u -> 800u by 16u step */
+		if (h_pixel >= LCD_CH0_DISP_HW) /* 800u */
+		{
+			h_pixel = LCD_CH0_DISP_HW;
+			*slide_dir = SLIDE_NONE;;
+		}
+		param->gr_base = &pos_buff[h_pixel];
+		param->gr_grc->hw = (uint16_t) ((int32_t) LCD_CH0_DISP_HW - h_pixel);
+		break;
+	case SLIDE_IN_LEFT:
+		h_pixel -= SLIDE_STEP; /* Decrement offset value : 800u -> 0u by 16u step */
+		if (h_pixel <= 0) /* 0u */
+		{
+			h_pixel = 0;
+			*slide_dir = SLIDE_NONE;;
+		}
+		param->gr_base = &pos_buff[h_pixel];
+		param->gr_grc->hw = (uint16_t) ((int32_t) LCD_CH0_DISP_HW - h_pixel);
+		break;
+
+	case SLIDE_OUT_TOP:
+		v_line += SLIDE_STEP; /* Increment offset value : 0u -> 800u by 16u step */
+		if (v_line >= LCD_CH0_DISP_VW) /* 600u */
+		{
+			v_line = LCD_CH0_DISP_VW;
+			*slide_dir = SLIDE_NONE;;
+		}
+		param->gr_base = &pos_buff[v_line * stride_pix];
+		param->gr_grc->vw = (uint16_t) ((int32_t) LCD_CH0_DISP_VW - v_line);
+		break;
+	case SLIDE_IN_TOP:
+		v_line -= SLIDE_STEP; /* Decrement offset value : 800u -> 0u by 16u step */
+		if (v_line <= 0) /* 0u */
+		{
+			v_line = 0;
+			*slide_dir = SLIDE_NONE;;
+		}
+		param->gr_base = &pos_buff[v_line * stride_pix];
+		param->gr_grc->vw = (uint16_t) ((int32_t) LCD_CH0_DISP_VW - v_line);
+		break;
+
+	default:
+		*slide_dir = SLIDE_NONE;
+		h_pixel = 0;
+		v_line = 0;
+		break;
+	}
+}
+
+/**************************************************************************//**
+ * @brief       Graphics surface read buffer change process
+ * @param[in]   layer_id                : Graphics layer ID
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Read_Change_More(
+		drv_graphics_layer_t layer_id, void * framebuff, uint32_t fb_stride, void * slide_dir) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	vdc5_error_t error;
+	vdc5_layer_id_t vdc5_layer_id;
+	vdc5_chg_read_chg_t read_chg;
+
+	vdc5_period_rect_t grN_grc = { LCD_CH0_DISP_VS, LCD_CH0_DISP_VW,
+			LCD_CH0_DISP_HS, LCD_CH0_DISP_HW };
+
+	switch (layer_id) {
+	case DRV_GRAPHICS_LAYER_0:
+		vdc5_layer_id = VDC5_LAYER_ID_0_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_1:
+		vdc5_layer_id = VDC5_LAYER_ID_1_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_2:
+		vdc5_layer_id = VDC5_LAYER_ID_2_RD;
+		break;
+	case DRV_GRAPHICS_LAYER_3:
+		vdc5_layer_id = VDC5_LAYER_ID_3_RD;
+		break;
+	default:
+		drv_error = DRV_GRAPHICS_LAYER_ERR;
+		break;
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		/* Read data parameter */
+
+		read_chg.width_read_fb = NULL; /* Width of the image read from frame buffer */
+		read_chg.gr_grc = &grN_grc; /* Display area */
+		read_chg.gr_disp_sel = NULL; /* Graphics display mode */
+		read_chg.gr_base = framebuff;
+
+		Slide( fb_stride, &read_chg, (slide_dir_t*)slide_dir);
+
+		//read_chg.gr_base        = framebuff;     /* Frame buffer base address */
+
+		/* Change read process */
+		error = R_VDC5_ChangeReadProcess(ch, vdc5_layer_id,
+				(vdc5_read_chg_t*) &read_chg);
+		if (error != VDC5_OK) {
+			drv_error = DRV_GRAPHICS_VDC5_ERR;
+		}
+	}
+	return drv_error;
+} /* End of function DRV_Graphics_Read_Change_More() */
+
+/**************************************************************************//**
+ * @brief       Video surface write process setting
+ *
+ *              Description:<br>
+ *              This function set the video write process. Input form is weave
+ *              (progressive) mode fixed.
+ *              This function supports the following 3 image format.
+ *                  YCbCr422, RGB565, RGB888
+ * @param[in]   video_input_ch          : Video input channel
+ * @param[in]   col_sys                 : Analog video signal color system
+ * @param[in]   adc_vinsel              : Video input pin
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride [byte]        : Line offset address of the frame buffer
+ * @param[in]   video_format            : Frame buffer video-signal writing format
+ * @param[in]   wr_rd_swa               : Frame buffer swap setting
+ * @param[in]   video_write_size_vw [px]: output height
+ * @param[in]   video_write_size_hw [px]: output width
+ * @param[in]   video_adc_vinsel        : Input pin control
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Setting(
+		drv_video_input_channel_t video_input_ch,
+		drv_graphics_video_col_sys_t col_sys, void * framebuff,
+		uint32_t fb_stride, drv_video_format_t video_format,
+		drv_wr_rd_swa_t wr_rd_swa, uint16_t video_write_buff_vw,
+		uint16_t video_write_buff_hw, drv_video_adc_vinsel_t video_adc_vinsel) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	vdc5_error_t error;
+	vdc5_layer_id_t vdc5_layer_id;
+	vdc5_write_t write;
+	vdc5_scalingdown_rot_t * scldw_rot;
+	vdc5_res_md_t res_md;
+	drv_rect_t video_in_rect;
+	uint8_t * framebuffer_t;
+	uint8_t * framebuffer_b;
+
+	if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0) {
+		GRAPHICS_VideoDecoderInit((vdec_adc_vinsel_t) video_adc_vinsel,
+				VDEC_CHANNEL_0, (graphics_col_sys_t) col_sys);
+	} else if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1) {
+		GRAPHICS_VideoDecoderInit((vdec_adc_vinsel_t) video_adc_vinsel,
+				VDEC_CHANNEL_1, (graphics_col_sys_t) col_sys);
+	} else {
+		drv_error = DRV_GRAPHICS_CHANNEL_ERR;
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0) {
+			vdc5_layer_id = VDC5_LAYER_ID_0_WR;
+		} else if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1) {
+			vdc5_layer_id = VDC5_LAYER_ID_1_WR;
+		} else {
+			drv_error = DRV_GRAPHICS_CHANNEL_ERR;
+		}
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		if (video_format == DRV_VIDEO_FORMAT_YCBCR422) {
+			res_md = VDC5_RES_MD_YCBCR422;
+		} else if (video_format == DRV_VIDEO_FORMAT_RGB888) {
+			res_md = VDC5_RES_MD_RGB888;
+		} else if (video_format == DRV_VIDEO_FORMAT_RGB565) {
+			res_md = VDC5_RES_MD_RGB565;
+		} else {
+			drv_error = DRV_GRAPHICS_FORMAT_ERR;
+		}
+	}
+
+	if (col_sys == DRV_COL_SYS_NTSC_358 || col_sys == DVV_COL_SYS_NTSC_443
+			|| col_sys == DRV_COL_SYS_NTSC_443_60) {
+		video_in_rect.hs = IMGCAP_SIZE_NTSC_HS * 2;
+		video_in_rect.hw = IMGCAP_SIZE_NTSC_HW * 2;
+		video_in_rect.vs = IMGCAP_SIZE_NTSC_VS;
+		video_in_rect.vw = IMGCAP_SIZE_NTSC_VW;
+	} else {
+		video_in_rect.hs = IMGCAP_SIZE_PAL_HS * 2;
+		video_in_rect.hw = IMGCAP_SIZE_PAL_HW * 2;
+		video_in_rect.vs = IMGCAP_SIZE_PAL_VS;
+		video_in_rect.vw = IMGCAP_SIZE_PAL_VW;
+	}
+
+#ifdef NO_SCALE_UP
+	if( drv_error == DRV_GRAPHICS_OK ) {
+		if( col_sys == DRV_COL_SYS_NTSC_358 || col_sys == DVV_COL_SYS_NTSC_443 || col_sys == DRV_COL_SYS_NTSC_443_60 ) {
+			if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
+				drv_error = DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR;
+			}
+		} else {
+			if( (video_write_buff_vw / 2u) > video_in_rect.vw ) {
+				drv_error = DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR;
+			}
+		}
+	}
+
+	if( drv_error == DRV_GRAPHICS_OK ) {
+		if( video_write_buff_hw > 800 ) {
+			drv_error = DRV_GRAPHICS_PARAM_RANGE_ERR;
+		}
+	}
+#endif
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		/* Scaling-down and rotation parameter */
+		scldw_rot = &write.scalingdown_rot;
+		/* Image area to be captured */
+		scldw_rot->res.vs = (uint16_t) ((uint32_t) video_in_rect.vs - 1u);
+		scldw_rot->res.vw = video_in_rect.vw;
+		scldw_rot->res.hs = video_in_rect.hs;
+		scldw_rot->res.hw = video_in_rect.hw;
+
+		/* Width of the image output from scaling-down control block
+		 Width of the image read from frame buffer */
+		if (video_write_buff_vw > LCD_CH0_DISP_VW) {
+			video_write_buff_vw = LCD_CH0_DISP_VW;
+		}
+
+		if (video_write_buff_hw > LCD_CH0_DISP_HW) {
+			video_write_buff_hw = LCD_CH0_DISP_HW;
+		}
+
+		//scldw_rot->res
+		/* Write data parameter */
+		framebuffer_t = framebuff;
+		framebuffer_b = &framebuffer_t[fb_stride];
+		scldw_rot->res_pfil_sel = VDC5_ON; /* Prefilter mode select for brightness signals (on/off) */
+		scldw_rot->res_out_vw = video_write_buff_vw / 2u; /* Number of valid lines in vertical direction
+		 output by scaling-down control block */
+		scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels
+		 output by scaling-down control block */
+		scldw_rot->adj_sel = VDC5_ON; /* Measures to decrease the influence
+		 by lack of last-input line (on/off) */
+		scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL; /* Frame buffer writing mode */
+		write.res_wrswa = (vdc5_wr_rd_swa_t) wr_rd_swa; /* Frame buffer swap setting */
+		write.res_md = res_md; /* Frame buffer video-signal writing format */
+		write.res_bst_md = VDC5_BST_MD_32BYTE; /* Transfer burst length for frame buffer */
+		write.res_inter = VDC5_RES_INTER_PROGRESSIVE; /* Field operating mode select */
+		write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */
+		write.res_fld_sel = VDC5_RES_FLD_SEL_TOP; /* Write field select */
+		write.res_dth_on = VDC5_ON; /* Dither correction on/off */
+		write.base = framebuff; /* Frame buffer base address */
+		write.ln_off = fb_stride * 2u; /* Frame buffer line offset address [byte] */
+		write.flm_num = (uint32_t) (1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */
+		/* Frame buffer frame offset address */
+		write.flm_off = fb_stride * 2u * (uint32_t) scldw_rot->res_out_vw;
+		write.btm_base = framebuffer_b; /* Frame buffer base address for bottom */
+
+		/* Write data control */
+		error = R_VDC5_WriteDataControl(ch, vdc5_layer_id, &write);
+		if (error != VDC5_OK) {
+			drv_error = DRV_GRAPHICS_VDC5_ERR;
+		}
+	}
+	return drv_error;
+} /* End of function DRV_Video_Write_Setting() */
+
+/**************************************************************************//**
+ * @brief       Video surface write process setting for digital input
+ *
+ *              Description:<br>
+ *              This function set the video write process for digital input.
+ *              This function supports the following 3 image format.
+ *                  YCbCr422, RGB565, RGB888
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride [byte]        : Line offset address of the frame buffer
+ * @param[in]   video_format            : Frame buffer video-signal writing format
+ * @param[in]   wr_rd_swa               : Frame buffer swap setting
+ * @param[in]   video_write_size_vw [px]: output height
+ * @param[in]   video_write_size_hw [px]: output width
+ * @param[in]   cap_area                : Capture area
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Setting_Digital(void * framebuff,
+		uint32_t fb_stride, drv_video_format_t video_format,
+		drv_wr_rd_swa_t wr_rd_swa, uint16_t video_write_buff_vw,
+		uint16_t video_write_buff_hw, drv_rect_t * cap_area) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	vdc5_channel_t ch = VDC5_CHANNEL_0;
+	vdc5_error_t error;
+	vdc5_layer_id_t vdc5_layer_id;
+	vdc5_write_t write;
+	vdc5_scalingdown_rot_t * scldw_rot;
+	vdc5_res_md_t res_md;
+
+	vdc5_layer_id = VDC5_LAYER_ID_0_WR;
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		if (video_format == DRV_VIDEO_FORMAT_YCBCR422) {
+			res_md = VDC5_RES_MD_YCBCR422;
+		} else if (video_format == DRV_VIDEO_FORMAT_RGB888) {
+			res_md = VDC5_RES_MD_RGB888;
+		} else if (video_format == DRV_VIDEO_FORMAT_RGB565) {
+			res_md = VDC5_RES_MD_RGB565;
+		} else {
+			drv_error = DRV_GRAPHICS_FORMAT_ERR;
+		}
+	}
+
+	if (drv_error == DRV_GRAPHICS_OK) {
+		/* Scaling-down and rotation parameter */
+		scldw_rot = &write.scalingdown_rot;
+		/* Image area to be captured */
+		scldw_rot->res.vs = (uint16_t) ((uint32_t) cap_area->vs - 1u);
+		scldw_rot->res.vw = cap_area->vw;
+		scldw_rot->res.hs = cap_area->hs;
+		scldw_rot->res.hw = cap_area->hw;
+
+		/* Write data parameter */
+		scldw_rot->res_pfil_sel = VDC5_ON; /* Prefilter mode select for brightness signals (on/off) */
+		scldw_rot->res_out_vw = video_write_buff_vw; /* Number of valid lines in vertical direction
+		 output by scaling-down control block */
+		scldw_rot->res_out_hw = video_write_buff_hw; /* Number of valid horizontal pixels
+		 output by scaling-down control block */
+		scldw_rot->adj_sel = VDC5_ON; /* Measures to decrease the influence
+		 by lack of last-input line (on/off) */
+		scldw_rot->res_ds_wr_md = VDC5_WR_MD_NORMAL; /* Frame buffer writing mode */
+		write.res_wrswa = (vdc5_wr_rd_swa_t) wr_rd_swa; /* Frame buffer swap setting */
+		write.res_md = res_md; /* Frame buffer video-signal writing format */
+		write.res_bst_md = VDC5_BST_MD_32BYTE; /* Transfer burst length for frame buffer */
+		write.res_inter = VDC5_RES_INTER_PROGRESSIVE; /* Field operating mode select */
+		write.res_fs_rate = VDC5_RES_FS_RATE_PER1; /* Writing rate */
+		write.res_fld_sel = VDC5_RES_FLD_SEL_TOP; /* Write field select */
+		write.res_dth_on = VDC5_ON; /* Dither correction on/off */
+		write.base = framebuff; /* Frame buffer base address */
+		write.ln_off = fb_stride;
+		/* Frame buffer line offset address [byte] */
+		write.flm_num = (uint32_t) (1u - 1u); /* Number of frames of buffer (res_flm_num + 1) */
+		/* Frame buffer frame offset address */
+		write.flm_off = fb_stride * (uint32_t) scldw_rot->res_out_vw;
+		write.btm_base = NULL; /* Frame buffer base address for bottom */
+
+		/* Write data control */
+		error = R_VDC5_WriteDataControl(ch, vdc5_layer_id, &write);
+		if (error != VDC5_OK) {
+			drv_error = DRV_GRAPHICS_VDC5_ERR;
+		}
+	}
+	return drv_error;
+} /* End of function DRV_Video_Write_Setting_Digital() */
+
+/**************************************************************************//**
+ * @brief       Video surface write buffer change process
+ * @param[in]   video_input_ch          : Video input channle
+ * @param[in]   framebuff               : Base address of the frame buffer
+ * @param[in]   fb_stride               : Line offset address of the frame buffer
+ * @retval      Error code
+ ******************************************************************************/
+drv_graphics_error_t DRV_Video_Write_Change(
+		drv_video_input_channel_t video_input_ch, void * framebuff,
+		uint32_t fb_stride) {
+	drv_graphics_error_t drv_error = DRV_GRAPHICS_OK;
+	uint8_t * framebuffer_t;
+	uint8_t * framebuffer_b;
+
+	framebuffer_t = (uint8_t *) ((uint32_t) framebuff & ~0x1F);
+	framebuffer_b = &framebuffer_t[fb_stride];
+
+	if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_0) {
+		VDC50.SC0_SCL1_WR2 = (uint32_t) framebuffer_t;
+		VDC50.SC0_SCL1_WR8 = (uint32_t) framebuffer_b;
+		VDC50.SC0_SCL1_UPDATE = 0x10;
+	} else if (video_input_ch == DRV_VIDEO_INPUT_CHANNEL_1) {
+		VDC50.SC1_SCL1_WR2 = (uint32_t) framebuffer_t;
+		VDC50.SC1_SCL1_WR8 = (uint32_t) framebuffer_b;
+		VDC50.SC1_SCL1_UPDATE = 0x10;
+	} else {
+		drv_error = DRV_GRAPHICS_CHANNEL_ERR;
+	}
+	return drv_error;
+} /* End of function DRV_Video_Write_Change() */
+
+/* End of file */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/vdc5.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,343 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         vdc5.h
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        Graphics driver wrapper function definitions in C
+******************************************************************************/
+
+#ifndef VDC5_H
+#define VDC5_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+
+#include    "r_typedefs.h"
+#include    "r_vdc5.h"
+#include    "pinmap.h"
+
+#ifdef  __cplusplus
+extern  "C"
+{
+#endif  /* __cplusplus */
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+#define VSYNC_1_2_FH_TIMING    (858u)   /* Vsync signal 1/2fH phase timing */
+#define VSYNC_1_4_FH_TIMING    (429u)   /* Vsync signal 1/4fH phase timing */
+#define DEFAULT_INPUT_CLOCK    (66.67)  /* P1 clock VDC5 */
+#define DEFAULT_OUTPUT_CLOCK   (66.67)  /* LVDS output clock */
+
+#define     IMGCAP_SIZE_NTSC_HS         (122u)
+#define     IMGCAP_SIZE_NTSC_HW         (720u)
+#define     IMGCAP_SIZE_NTSC_VS         (16u)
+#define     IMGCAP_SIZE_NTSC_VW         (240u)
+
+#define     IMGCAP_SIZE_PAL_HS          (132u)
+#define     IMGCAP_SIZE_PAL_HW          (720u)
+#define     IMGCAP_SIZE_PAL_VS          (19u)
+#define     IMGCAP_SIZE_PAL_VW          (280u)
+
+typedef void (*vdc5_irq_handler)(uint32_t int_sense);
+
+/* video channel select */
+typedef enum {
+    DRV_VIDEO_INPUT_CHANNEL_0 = 0,      /* video input channel 0    */
+    DRV_VIDEO_INPUT_CHANNEL_1           /* video input channel 1    */
+} drv_video_input_channel_t;
+
+/* input pin control */
+typedef enum {
+    DRV_VIDEO_ADC_VINSEL_VIN1 = 0,      /* VIN1 input               */
+    DRV_VIDEO_ADC_VINSEL_VIN2           /* VIN2 input               */
+} drv_video_adc_vinsel_t;
+
+/* graphics layer select */
+typedef enum {
+    DRV_GRAPHICS_LAYER_0 = 0,           /* graphics layer 0         */
+    DRV_GRAPHICS_LAYER_1,               /* graphics layer 1         */
+    DRV_GRAPHICS_LAYER_2,               /* graphics layer 2         */
+    DRV_GRAPHICS_LAYER_3                /* graphics layer 3         */
+} drv_graphics_layer_t;
+
+/* error codes */
+typedef enum {
+    DRV_GRAPHICS_OK = 0,                /* Normal termination       */
+    DRV_GRAPHICS_VDC5_ERR = -1,         /* VDC5 error               */
+    DRV_GRAPHICS_FORMAT_ERR = -2,       /* Not support format       */
+    DRV_GRAPHICS_LAYER_ERR = -3,        /* Invalid layer ID error   */
+    DRV_GRAPHICS_CHANNEL_ERR = -4,      /* Invalid channel error    */
+    DRV_GRAPHICS_VIDEO_NTSC_SIZE_ERR = -5, /* Video Write           */
+    DRV_GRAPHICS_VIDEO_PAL_SIZE_ERR = -6,  /* Video Write           */
+    DRV_GRAPHICS_PARAM_RANGE_ERR = -7   /* Parameter range error    */
+} drv_graphics_error_t;
+
+/* graphics layer format select */
+typedef enum {
+    DRV_GRAPHICS_FORMAT_YCBCR422 = 0,   /* YCbCr422                 */
+    DRV_GRAPHICS_FORMAT_RGB565,         /* RGB565                   */
+    DRV_GRAPHICS_FORMAT_RGB888,         /* RGB888                   */
+    DRV_GRAPHICS_FORMAT_ARGB8888,       /* ARGB8888                 */
+    DRV_GRAPHICS_FORMAT_ARGB4444        /* ARGB4444                 */
+} drv_graphics_format_t;
+
+/* video writing format select */
+typedef enum {
+    DRV_VIDEO_FORMAT_YCBCR422 = 0,      /* YCbCr422                 */
+    DRV_VIDEO_FORMAT_RGB565,            /* RGB565                   */
+    DRV_VIDEO_FORMAT_RGB888             /* RGB888                   */
+} drv_video_format_t;
+
+
+/* lcd tcon output pin select */
+typedef enum {
+    DRV_LCD_TCON_PIN_NON = -1,          /* Not using output         */
+    DRV_LCD_TCON_PIN_0,                 /* LCD_TCON0                */
+    DRV_LCD_TCON_PIN_1,                 /* LCD_TCON1                */
+    DRV_LCD_TCON_PIN_2                  /* LCD_TCON2                */
+} drv_lcd_tcon_pin_t;
+
+/* lcd output format select */
+typedef enum {
+    DRV_LCD_OUTFORMAT_RGB888 = 0,       /* RGB888 or LVDS           */
+    DRV_LCD_OUTFORMAT_RGB666,           /* RGB666                   */
+    DRV_LCD_OUTFORMAT_RGB565            /* RGB565                   */
+} drv_lcd_outformat_t;
+
+/* frame buffer swap setting */
+typedef enum {
+    DRV_WR_RD_WRSWA_NON = 0,           /* Not swapped: 1-2-3-4-5-6-7-8 */
+    DRV_WR_RD_WRSWA_8BIT,              /* Swapped in 8-bit units: 2-1-4-3-6-5-8-7 */
+    DRV_WR_RD_WRSWA_16BIT,             /* Swapped in 16-bit units: 3-4-1-2-7-8-5-6 */
+    DRV_WR_RD_WRSWA_16_8BIT,           /* Swapped in 16-bit units + 8-bit units: 4-3-2-1-8-7-6-5 */
+    DRV_WR_RD_WRSWA_32BIT,             /* Swapped in 32-bit units: 5-6-7-8-1-2-3-4 */
+    DRV_WR_RD_WRSWA_32_8BIT,           /* Swapped in 32-bit units + 8-bit units: 6-5-8-7-2-1-4-3 */
+    DRV_WR_RD_WRSWA_32_16BIT,          /* Swapped in 32-bit units + 16-bit units: 7-8-5-6-3-4-1-2 */
+    DRV_WR_RD_WRSWA_32_16_8BIT,        /* Swapped in 32-bit units + 16-bit units + 8-bit units: 8-7-6-5-4-3-2-1 */
+} drv_wr_rd_swa_t;
+
+/* edge of a signal */
+typedef enum {
+    DRV_EDGE_RISING    = 0,             /* Rising edge              */
+    DRV_EDGE_FALLING   = 1              /* Falling edge             */
+} drv_edge_t;
+
+/* lcd type */
+typedef enum {
+    DRV_LCD_TYPE_LVDS = 0,              /* LVDS signal control      */
+    DRV_LCD_TYPE_PARALLEL_RGB           /* RGB parallel signal control */
+} drv_lcd_type_t;
+
+/* Polarity of a signal */
+typedef enum {
+    DRV_SIG_POL_NOT_INVERTED = 0,       /* Not inverted             */
+    DRV_SIG_POL_INVERTED                /* Inverted                 */
+} drv_sig_pol_t;
+
+/* Video color system */
+typedef enum {
+    DRV_COL_SYS_NTSC_358       = 0,        /* NTSC-3.58 */
+    DVV_COL_SYS_NTSC_443       = 1,        /* NTSC-4.43 */
+    DRV_COL_SYS_PAL_443        = 2,        /* PAL-4.43 */
+    DRV_COL_SYS_PAL_M          = 3,        /* PAL-M */
+    DRV_COL_SYS_PAL_N          = 4,        /* PAL-N */
+    DRV_COL_SYS_SECAM          = 5,        /* SECAM */
+    DRV_COL_SYS_NTSC_443_60    = 6,        /* NTSC-4.43 (60Hz) */
+    DRV_COL_SYS_PAL_60         = 7,        /* PAL-60 */
+} drv_graphics_video_col_sys_t;
+
+/* External Input select */
+typedef enum {
+    DRV_INPUT_SEL_VDEC     = 0,            /*!< Video decoder output signals */
+    DRV_INPUT_SEL_EXT      = 1             /*!< Signals supplied via the external input pins */
+} drv_video_input_sel_t;
+
+/* External input format select  */
+typedef enum {
+    DRV_VIDEO_EXTIN_FORMAT_RGB888 = 0,   /*!< RGB888 Not support */
+    DRV_VIDEO_EXTIN_FORMAT_RGB666,       /*!< RGB666 */
+    DRV_VIDEO_EXTIN_FORMAT_RGB565,       /*!< RGB565 */
+    DRV_VIDEO_EXTIN_FORMAT_BT656,        /*!< BT6556 */
+    DRV_VIDEO_EXTIN_FORMAT_BT601,        /*!< BT6501 */
+    DRV_VIDEO_EXTIN_FORMAT_YCBCR422,     /*!< YCbCr422 */
+    DRV_VIDEO_EXTIN_FORMAT_YCBCR444,     /*!< YCbCr444 Not support */
+} drv_video_extin_format_t;
+
+/* On/off */
+typedef enum {
+    DRV_OFF    = 0,                      /*!< Off */
+    DRV_ON     = 1                       /*!< On */
+} drv_onoff_t;
+
+/* Number of lines for BT.656 external input  */
+typedef enum {
+    DRV_EXTIN_LINE_525     = 0,    /*!< 525 lines */
+    DRV_EXTIN_LINE_625     = 1     /*!< 625 lines */
+} drv_extin_input_line_t;
+
+/* Y/Cb/Y/Cr data string start timing */
+typedef enum {
+    DRV_EXTIN_H_POS_CBYCRY = 0,    /*!< Cb/Y/Cr/Y (BT656/601), Cb/Cr (YCbCr422) */
+    DRV_EXTIN_H_POS_YCRYCB,        /*!< Y/Cr/Y/Cb (BT656/601), setting prohibited (YCbCr422) */
+    DRV_EXTIN_H_POS_CRYCBY,        /*!< Cr/Y/Cb/Y (BT656/601), setting prohibited (YCbCr422) */
+    DRV_EXTIN_H_POS_YCBYCR,        /*!< Y/Cb/Y/Cr (BT656/601), Cr/Cb (YCbCr422) */
+} drv_extin_h_pos_t;
+
+/* The relative position within the graphics display area */
+typedef struct {
+    uint16_t   vs;                  /* Vertical start pos       */
+    uint16_t   vw;                  /* Vertical width (height)  */
+    uint16_t   hs;                  /* Horizontal start pos     */
+    uint16_t   hw;                  /* Horizontal width         */
+} drv_rect_t;
+
+/* lcd configuration  */
+typedef struct {
+    drv_lcd_type_t      lcd_type;               /* LVDS or Pararel RGB                      */
+    double              intputClock;            /* P1  clk [MHz] ex. 66.67                  */
+    double              outputClock;            /* LCD clk [MHz] ex. 33.33                  */
+
+    drv_lcd_outformat_t lcd_outformat;          /* Output format select */
+    drv_edge_t          lcd_edge;               /* Output phase control of LCD_DATA23 to LCD_DATA0 pin */
+
+    uint16_t            h_toatal_period;        /* Free-running Hsync period                */
+    uint16_t            v_toatal_period;        /* Free-running Vsync period                */
+    uint16_t            h_disp_widht;           /* LCD display area size, horizontal width  */
+    uint16_t            v_disp_widht;           /* LCD display area size, vertical width    */
+    uint16_t            h_back_porch;           /* LCD display horizontal back porch period */
+    uint16_t            v_back_porch;           /* LCD display vertical back porch period   */
+
+    drv_lcd_tcon_pin_t  h_sync_port;            /* TCONn or Not use(-1)                     */
+    drv_sig_pol_t       h_sync_port_polarity;   /* Polarity inversion control of signal     */
+    uint16_t            h_sync_width;           /* Hsync width                              */
+
+    drv_lcd_tcon_pin_t  v_sync_port;            /* TCONn or Not use(-1)                     */
+    drv_sig_pol_t       v_sync_port_polarity;   /* Polarity inversion control of signal     */
+    uint16_t            v_sync_width;           /* Vsync width  */
+
+    drv_lcd_tcon_pin_t  de_port;                /* TCONn or Not use(-1)                     */
+    drv_sig_pol_t       de_port_polarity;       /* Polarity inversion control of signal     */
+
+} drv_lcd_config_t;
+
+/* Digital video input configuration  */
+typedef struct {
+    drv_video_extin_format_t     inp_format;    /*!< External Input Format Select                                */
+    drv_edge_t                   inp_pxd_edge;  /*!< Clock Edge Select for Capturing External Input Video Image  */
+    drv_edge_t                   inp_vs_edge;   /*!< Clock Edge Select for Capturing External Input Vsync Signal */
+    drv_edge_t                   inp_hs_edge;   /*!< Clock Edge Select for Capturing External Input Hsync Signal */
+    drv_onoff_t                  inp_endian_on; /*!< External Input B/R Signal Swap On/Off Control               */
+    drv_onoff_t                  inp_swap_on;   /*!< External Input Bit Endian Change On/Off Control             */
+    drv_sig_pol_t                inp_vs_inv;    /*!< External Input Vsync Signal DV_VSYNC Inversion Control      */
+    drv_sig_pol_t                inp_hs_inv;    /*!< External Input Hsync Signal DV_HSYNC Inversion Control      */
+    drv_extin_input_line_t       inp_f525_625;  /*!< Number of lines for BT.656 external input */
+    drv_extin_h_pos_t            inp_h_pos;     /*!< Y/Cb/Y/Cr data string start timing to Hsync reference */
+} drv_video_ext_in_config_t;
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef enum
+{
+    SLIDE_OUT_RIGHT = 0,
+    SLIDE_IN_RIGHT,
+    SLIDE_OUT_BOTTOM,
+    SLIDE_IN_BOTTOM,
+    SLIDE_OUT_LEFT,
+    SLIDE_IN_LEFT,
+    SLIDE_OUT_TOP,
+    SLIDE_IN_TOP,
+    SLIDE_NONE,
+} slide_dir_t;
+/******************************************************************************
+Exported global functions (to be accessed by other files)
+******************************************************************************/
+drv_graphics_error_t DRV_Graphics_Init( drv_lcd_config_t * drv_lcd_config );
+drv_graphics_error_t DRV_Graphics_Video_init( drv_video_input_sel_t drv_video_input_sel, drv_video_ext_in_config_t * drv_video_ext_in_config );
+
+drv_graphics_error_t DRV_Graphics_Lcd_Port_Init( PinName *pin, uint32_t pin_count );
+drv_graphics_error_t DRV_Graphics_Lvds_Port_Init( PinName *pin, uint32_t pin_count );
+drv_graphics_error_t DRV_Graphics_Dvinput_Port_Init( PinName *pin, uint32_t pin_count );
+
+drv_graphics_error_t DRV_Graphics_Irq_Handler_Set( vdc5_int_type_t irq, uint16_t num, void (* callback)(vdc5_int_type_t)  );
+
+drv_graphics_error_t DRV_Graphics_Start ( drv_graphics_layer_t layer_id );
+drv_graphics_error_t DRV_Graphics_Stop ( drv_graphics_layer_t layer_id );
+drv_graphics_error_t DRV_Video_Start ( drv_video_input_channel_t video_input_ch );
+drv_graphics_error_t DRV_Video_Stop ( drv_video_input_channel_t video_input_ch );
+
+drv_graphics_error_t DRV_Graphics_Read_Setting (
+    drv_graphics_layer_t    layer_id,
+    void                  * framebuff,
+    uint32_t                fb_stride,
+    drv_graphics_format_t   gr_format,
+    drv_wr_rd_swa_t         wr_rd_swa,
+    drv_rect_t            * gr_rect );
+
+drv_graphics_error_t DRV_Graphics_Read_Change (
+    drv_graphics_layer_t    layer_id,
+    void                 *  framebuff);
+
+drv_graphics_error_t DRV_Graphics_Read_Change_More (
+    drv_graphics_layer_t    layer_id,
+    void                 *  framebuff,
+	uint32_t                fb_stride,
+	void				 *  slide_dir);
+
+drv_graphics_error_t DRV_Video_Write_Setting (
+    drv_video_input_channel_t       video_input_ch,
+    drv_graphics_video_col_sys_t    col_sys,
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_video_adc_vinsel_t          video_adc_vinsel );
+
+drv_graphics_error_t DRV_Video_Write_Setting_Digital (
+    void                          * framebuff,
+    uint32_t                        fb_stride,
+    drv_video_format_t              video_format,
+    drv_wr_rd_swa_t                 wr_rd_swa,
+    uint16_t                        video_write_buff_vw,
+    uint16_t                        video_write_buff_hw,
+    drv_rect_t                    * cap_area );
+
+drv_graphics_error_t DRV_Video_Write_Change (
+    drv_video_input_channel_t    video_input_ch,
+    void                       * framebuff,
+    uint32_t                     fb_stride );
+
+#ifdef  __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  /* VDC5_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/RGA/video/video_decoder/video_decoder.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,988 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         video_decoder.c
+* @version      1.00
+* $Rev: 199 $
+* $Date:: 2014-05-23 16:33:52 +0900#$
+* @brief        Video decoder function
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include    <stdlib.h>
+#include    <string.h>
+
+#include    "r_typedefs.h"
+#include    "iodefine.h"
+
+#include    "r_vdec.h"
+#include    "r_vdec_user.h"
+
+#include    "video_decoder.h"
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define     STBCR7_BIT7                 (0x80u)
+#define     STBCR7_BIT6                 (0x40u)
+
+/*! Video decoder recommended value */
+#define SRCLEFT_NTSC_3_58       ((uint16_t)256u)
+#define SRCLEFT_NTSC_4_43       ((uint16_t)256u)
+#define SRCLEFT_PAL_4_43        ((uint16_t)256u)
+#define SRCLEFT_PAL_M           ((uint16_t)256u)
+#define SRCLEFT_PAL_N           ((uint16_t)256u)
+#define SRCLEFT_SECAM           ((uint16_t)256u)
+#define SRCLEFT_NTSC_443_60     ((uint16_t)256u)
+#define SRCLEFT_PAL_60          ((uint16_t)256u)
+
+#define SRCTOP_NTSC_3_58        ((uint16_t)16u)
+#define SRCTOP_NTSC_4_43        ((uint16_t)19u)
+#define SRCTOP_PAL_4_43         ((uint16_t)19u)
+#define SRCTOP_PAL_M            ((uint16_t)16u)
+#define SRCTOP_PAL_N            ((uint16_t)19u)
+#define SRCTOP_SECAM            ((uint16_t)19u)
+#define SRCTOP_NTSC_443_60      ((uint16_t)16u)
+#define SRCTOP_PAL_60           ((uint16_t)16u)
+
+#define SRCHEIGHT_NTSC_3_58     ((uint16_t)241u)
+#define SRCHEIGHT_NTSC_4_43     ((uint16_t)288u)
+#define SRCHEIGHT_PAL_4_43      ((uint16_t)288u)
+#define SRCHEIGHT_PAL_M         ((uint16_t)241u)
+#define SRCHEIGHT_PAL_N         ((uint16_t)288u)
+#define SRCHEIGHT_SECAM         ((uint16_t)288u)
+#define SRCHEIGHT_NTSC_443_60   ((uint16_t)241u)
+#define SRCHEIGHT_PAL_60        ((uint16_t)241u)
+
+#define SRCWIDTH_NTSC_3_58      ((uint16_t)1428u)
+#define SRCWIDTH_NTSC_4_43      ((uint16_t)1412u)
+#define SRCWIDTH_PAL_4_43       ((uint16_t)1412u)
+#define SRCWIDTH_PAL_M          ((uint16_t)1428u)
+#define SRCWIDTH_PAL_N          ((uint16_t)1412u)
+#define SRCWIDTH_SECAM          ((uint16_t)1412u)
+#define SRCWIDTH_NTSC_443_60    ((uint16_t)1428u)
+#define SRCWIDTH_PAL_60         ((uint16_t)1428u)
+
+#define HAFCTYP_NTSC_3_58       ((uint16_t)692u)
+#define HAFCTYP_NTSC_4_43       ((uint16_t)704u)
+#define HAFCTYP_PAL_4_43        ((uint16_t)704u)
+#define HAFCTYP_PAL_M           ((uint16_t)692u)
+#define HAFCTYP_PAL_N           ((uint16_t)704u)
+#define HAFCTYP_SECAM           ((uint16_t)704u)
+#define HAFCTYP_NTSC_443_60     ((uint16_t)692u)
+#define HAFCTYP_PAL_60          ((uint16_t)692u)
+
+#define HAFCMAX_NTSC_3_58       ((uint16_t)792u)
+#define HAFCMAX_NTSC_4_43       ((uint16_t)785u)
+#define HAFCMAX_PAL_4_43        ((uint16_t)785u)
+#define HAFCMAX_PAL_M           ((uint16_t)792u)
+#define HAFCMAX_PAL_N           ((uint16_t)785u)
+#define HAFCMAX_SECAM           ((uint16_t)785u)
+#define HAFCMAX_NTSC_443_60     ((uint16_t)792u)
+#define HAFCMAX_PAL_60          ((uint16_t)792u)
+
+#define HAFCMIN_NTSC_3_58       ((uint16_t)592u)
+#define HAFCMIN_NTSC_4_43       ((uint16_t)630u)
+#define HAFCMIN_PAL_4_43        ((uint16_t)630u)
+#define HAFCMIN_PAL_M           ((uint16_t)592u)
+#define HAFCMIN_PAL_N           ((uint16_t)630u)
+#define HAFCMIN_SECAM           ((uint16_t)630u)
+#define HAFCMIN_NTSC_443_60     ((uint16_t)592u)
+#define HAFCMIN_PAL_60          ((uint16_t)592u)
+
+#define VCDWINDOW_NTSC_3_58     ((uint16_t)30u)
+#define VCDWINDOW_NTSC_4_43     ((uint16_t)30u)
+#define VCDWINDOW_PAL_4_43      ((uint16_t)30u)
+#define VCDWINDOW_PAL_M         ((uint16_t)30u)
+#define VCDWINDOW_PAL_N         ((uint16_t)30u)
+#define VCDWINDOW_SECAM         ((uint16_t)30u)
+#define VCDWINDOW_NTSC_443_60   ((uint16_t)30u)
+#define VCDWINDOW_PAL_60        ((uint16_t)30u)
+
+#define VCDOFFSET_NTSC_3_58     ((uint16_t)15u)
+#define VCDOFFSET_NTSC_4_43     ((uint16_t)15u)
+#define VCDOFFSET_PAL_4_43      ((uint16_t)15u)
+#define VCDOFFSET_PAL_M         ((uint16_t)15u)
+#define VCDOFFSET_PAL_N         ((uint16_t)15u)
+#define VCDOFFSET_SECAM         ((uint16_t)15u)
+#define VCDOFFSET_NTSC_443_60   ((uint16_t)15u)
+#define VCDOFFSET_PAL_60        ((uint16_t)15u)
+
+#define ACCLEVEL_NTSC_3_58      ((uint16_t)220u)
+#define ACCLEVEL_NTSC_4_43      ((uint16_t)220u)
+#define ACCLEVEL_PAL_4_43       ((uint16_t)220u)
+#define ACCLEVEL_PAL_M          ((uint16_t)230u)
+#define ACCLEVEL_PAL_N          ((uint16_t)230u)
+#define ACCLEVEL_SECAM          ((uint16_t)220u)
+#define ACCLEVEL_NTSC_443_60    ((uint16_t)220u)
+#define ACCLEVEL_PAL_60         ((uint16_t)230u)
+
+#define AGCLEVEL_NTSC_3_58      ((uint16_t)230u)
+#define AGCLEVEL_NTSC_4_43      ((uint16_t)230u)
+#define AGCLEVEL_PAL_4_43       ((uint16_t)242u)
+#define AGCLEVEL_PAL_M          ((uint16_t)242u)
+#define AGCLEVEL_PAL_N          ((uint16_t)242u)
+#define AGCLEVEL_SECAM          ((uint16_t)242u)
+#define AGCLEVEL_NTSC_443_60    ((uint16_t)230u)
+#define AGCLEVEL_PAL_60         ((uint16_t)242u)
+
+#define K15_NTSC_3_58           ((uint16_t)2u)
+#define K15_NTSC_4_43           ((uint16_t)2u)
+#define K15_PAL_4_43            ((uint16_t)2u)
+#define K15_PAL_M               ((uint16_t)2u)
+#define K15_PAL_N               ((uint16_t)2u)
+#define K15_SECAM               ((uint16_t)2u)
+#define K15_NTSC_443_60         ((uint16_t)2u)
+#define K15_PAL_60              ((uint16_t)2u)
+
+#define K13_NTSC_3_58           ((uint16_t)8u)
+#define K13_NTSC_4_43           ((uint16_t)8u)
+#define K13_PAL_4_43            ((uint16_t)8u)
+#define K13_PAL_M               ((uint16_t)8u)
+#define K13_PAL_N               ((uint16_t)8u)
+#define K13_SECAM               ((uint16_t)8u)
+#define K13_NTSC_443_60         ((uint16_t)8u)
+#define K13_PAL_60              ((uint16_t)8u)
+
+#define K11_NTSC_3_58           ((uint16_t)4u)
+#define K11_NTSC_4_43           ((uint16_t)4u)
+#define K11_PAL_4_43            ((uint16_t)3u)
+#define K11_PAL_M               ((uint16_t)3u)
+#define K11_PAL_N               ((uint16_t)3u)
+#define K11_SECAM               ((uint16_t)4u)
+#define K11_NTSC_443_60         ((uint16_t)4u)
+#define K11_PAL_60              ((uint16_t)3u)
+
+#define K16_NTSC_3_58           ((uint16_t)3u)
+#define K16_NTSC_4_43           ((uint16_t)3u)
+#define K16_PAL_4_43            ((uint16_t)4u)
+#define K16_PAL_M               ((uint16_t)4u)
+#define K16_PAL_N               ((uint16_t)4u)
+#define K16_SECAM               ((uint16_t)3u)
+#define K16_NTSC_443_60         ((uint16_t)3u)
+#define K16_PAL_60              ((uint16_t)4u)
+
+#define K14_NTSC_3_58           ((uint16_t)16u)
+#define K14_NTSC_4_43           ((uint16_t)16u)
+#define K14_PAL_4_43            ((uint16_t)63u)
+#define K14_PAL_M               ((uint16_t)63u)
+#define K14_PAL_N               ((uint16_t)63u)
+#define K14_SECAM               ((uint16_t)16u)
+#define K14_NTSC_443_60         ((uint16_t)16u)
+#define K14_PAL_60              ((uint16_t)63u)
+
+#define K12_NTSC_3_58           ((uint16_t)8u)
+#define K12_NTSC_4_43           ((uint16_t)8u)
+#define K12_PAL_4_43            ((uint16_t)2u)
+#define K12_PAL_M               ((uint16_t)2u)
+#define K12_PAL_N               ((uint16_t)2u)
+#define K12_SECAM               ((uint16_t)1u)
+#define K12_NTSC_443_60         ((uint16_t)8u)
+#define K12_PAL_60              ((uint16_t)2u)
+
+#define K22A_NTSC_3_58          ((uint16_t)32u)
+#define K22A_NTSC_4_43          ((uint16_t)32u)
+#define K22A_PAL_4_43           ((uint16_t)32u)
+#define K22A_PAL_M              ((uint16_t)32u)
+#define K22A_PAL_N              ((uint16_t)32u)
+#define K22A_SECAM              ((uint16_t)32u)
+#define K22A_NTSC_443_60        ((uint16_t)32u)
+#define K22A_PAL_60             ((uint16_t)32u)
+
+#define K21A_NTSC_3_58          ((uint16_t)6u)
+#define K21A_NTSC_4_43          ((uint16_t)6u)
+#define K21A_PAL_4_43           ((uint16_t)10u)
+#define K21A_PAL_M              ((uint16_t)10u)
+#define K21A_PAL_N              ((uint16_t)10u)
+#define K21A_SECAM              ((uint16_t)10u)
+#define K21A_NTSC_443_60        ((uint16_t)6u)
+#define K21A_PAL_60             ((uint16_t)10u)
+
+#define K22B_NTSC_3_58          ((uint16_t)8u)
+#define K22B_NTSC_4_43          ((uint16_t)8u)
+#define K22B_PAL_4_43           ((uint16_t)15u)
+#define K22B_PAL_M              ((uint16_t)15u)
+#define K22B_PAL_N              ((uint16_t)15u)
+#define K22B_SECAM              ((uint16_t)15u)
+#define K22B_NTSC_443_60        ((uint16_t)8u)
+#define K22B_PAL_60             ((uint16_t)15u)
+
+#define K21B_NTSC_3_58          ((uint16_t)6u)
+#define K21B_NTSC_4_43          ((uint16_t)6u)
+#define K21B_PAL_4_43           ((uint16_t)10u)
+#define K21B_PAL_M              ((uint16_t)10u)
+#define K21B_PAL_N              ((uint16_t)10u)
+#define K21B_SECAM              ((uint16_t)6u)
+#define K21B_NTSC_443_60        ((uint16_t)6u)
+#define K21B_PAL_60             ((uint16_t)10u)
+
+#define K23B_NTSC_3_58          ((uint16_t)6u)
+#define K23B_NTSC_4_43          ((uint16_t)6u)
+#define K23B_PAL_4_43           ((uint16_t)3u)
+#define K23B_PAL_M              ((uint16_t)3u)
+#define K23B_PAL_N              ((uint16_t)3u)
+#define K23B_SECAM              ((uint16_t)3u)
+#define K23B_NTSC_443_60        ((uint16_t)6u)
+#define K23B_PAL_60             ((uint16_t)3u)
+
+#define K23A_NTSC_3_58          ((uint16_t)3u)
+#define K23A_NTSC_4_43          ((uint16_t)3u)
+#define K23A_PAL_4_43           ((uint16_t)3u)
+#define K23A_PAL_M              ((uint16_t)3u)
+#define K23A_PAL_N              ((uint16_t)3u)
+#define K23A_SECAM              ((uint16_t)3u)
+#define K23A_NTSC_443_60        ((uint16_t)3u)
+#define K23A_PAL_60             ((uint16_t)3u)
+
+#define K24_NTSC_3_58           ((uint16_t)5u)
+#define K24_NTSC_4_43           ((uint16_t)5u)
+#define K24_PAL_4_43            ((uint16_t)8u)
+#define K24_PAL_M               ((uint16_t)8u)
+#define K24_PAL_N               ((uint16_t)8u)
+#define K24_SECAM               ((uint16_t)8u)
+#define K24_NTSC_443_60         ((uint16_t)5u)
+#define K24_PAL_60              ((uint16_t)8u)
+
+/* SyncSep */
+#define SYNCMAXDUTY_H_VALUE  ((uint16_t)15u)
+#define SYNCMINDUTY_H_VALUE  ((uint16_t)10u)
+#define CSYNCSLICE_H_VALUE   ((uint16_t)146u)
+#define SYNCMAXDUTY_V_VALUE  ((uint16_t)15u)
+#define SYNCMINDUTY_V_VALUE  ((uint16_t)9u)
+#define VSYNCSLICE_VALUE     ((uint16_t)10u)
+#define CSYNCSLICE_V_VALUE   ((uint16_t)146u)
+#define HAFCGAIN_VALUE       ((uint16_t)12u)
+#define HAFCSTART_VALUE      ((uint16_t)0u)
+#define HAFCEND_VALUE        ((uint16_t)8u)
+#define AGCRESPONSE_VALUE    ((uint16_t)4u)
+#define AGCPRECIS_VALUE      ((uint16_t)10u)
+#define PGA_GAIN_VALUE       ((uint16_t)0u)
+#define PEAKATTACK_VALUE     ((uint16_t)2u)
+#define PEAKRELEASE_VALUE    ((uint16_t)3u)
+#define MAXPEAKSAMPLES_VALUE ((uint16_t)20u)
+
+/* YcSep */
+#define RADJ_O_LEVEL0_VALUE  ((uint16_t)928u)
+#define RADJ_U_LEVEL0_VALUE  ((uint16_t)32u)
+#define RADJ_O_LEVEL1_VALUE  ((uint16_t)960u)
+#define RADJ_U_LEVEL1_VALUE  ((uint16_t)48u)
+#define RADJ_O_LEVEL2_VALUE  ((uint16_t)992u)
+#define RADJ_U_LEVEL2_VALUE  ((uint16_t)64u)
+#define V_Y_LEVEL_VALUE      ((uint16_t)0u)
+
+/* ChromaDec */
+#define LUMADELAY_VALUE      ((uint16_t)0u)
+#define LOOPGAIN_VALUE       ((uint16_t)3u)
+#define LOCKLIMIT_VALUE      ((uint16_t)1u)
+#define BGPCHECK_VALUE       ((uint16_t)0u)
+#define BGPWIDTH_VALUE       ((uint16_t)54u)
+#define BGPSTART_VALUE       ((uint16_t)110u)
+#define CHROMAMAINGAIN_VALUE ((uint16_t)210u)
+#define ACCRESPONSE_VALUE    ((uint16_t)1u)
+#define ACCPRECIS_VALUE      ((uint16_t)8u)
+#define KILLERLEVEL_VALUE    ((uint16_t)4u)
+#define KILLEROFFSET_VALUE   ((uint16_t)5u)
+
+/* DigitalClamp */
+#define BLANKLEVEL_Y_VALUE   ((uint16_t)984u)
+#define DCPPOS_Y_VALUE       ((uint16_t)162u)
+#define BLANKLEVEL_CB_VALUE  ((uint16_t)0u)
+#define BLANKLEVEL_CR_VALUE  ((uint16_t)0u)
+#define DCPPOS_C_VALUE       ((uint16_t)54u)
+#define ACFLAGTIME_VALUE     ((uint16_t)0u)
+#define ACFFILTER_VALUE      ((uint16_t)3u)
+#define DCPRESPONSE_VALUE    ((uint16_t)0u)
+#define DCPSTART_VALUE       ((uint16_t)16u)
+#define DCPEND_VALUE         ((uint16_t)16u)
+#define DCPWIDTH_VALUE       ((uint16_t)27u)
+
+/* Output */
+#define Y_GAIN2_VALUE        ((uint16_t)816u)
+#define CB_GAIN2_VALUE       ((uint16_t)663u)
+#define CR_GAIN2_VALUE       ((uint16_t)663u)
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+/*! Video decoder recommended value */
+typedef struct {
+    /* Capturing position setting */
+    uint16_t            srcleft;
+    uint16_t            srctop;
+    uint16_t            srcheight;
+    uint16_t            srcwidth;
+    /* Horizontal AFC setting */
+    uint16_t            hafctyp;
+    uint16_t            hafcmax;
+    uint16_t            hafcmin;
+    /* Vertical countdown setting */
+    vdec_onoff_t        novcd50_;
+    vdec_onoff_t        novcd60_;
+    vdec_vcddefault_t   vcddefault;
+    uint16_t            vcdwindow;
+    uint16_t            vcdoffset;
+    /* BCO setting */
+    vdec_color_sys_t    defaultsys;
+    vdec_onoff_t        nontsc358_;
+    vdec_onoff_t        nontsc443_;
+    vdec_onoff_t        nopalm_;
+    vdec_onoff_t        nopaln_;
+    vdec_onoff_t        nopal443_;
+    vdec_onoff_t        nosecam_;
+    /* ACC level setting */
+    uint16_t            acclevel;
+    /* AGC level setting */
+    uint16_t            agclevel;
+    /* Y/C separation setting */
+    uint16_t            k15;
+    uint16_t            k13;
+    uint16_t            k11;
+    uint16_t            k16;
+    uint16_t            k14;
+    uint16_t            k12;
+    uint16_t            k22A;
+    uint16_t            k21A;
+    uint16_t            k22B;
+    uint16_t            k21B;
+    uint16_t            k23B;
+    uint16_t            k23A;
+    uint16_t            k24;
+    vdec_onoff_t        det2_on;
+    vdec_filmix_ratio_t hsel_mix_y;
+    vdec_filmix_ratio_t vsel_mix_y;
+    vdec_filmix_ratio_t hvsel_mix_y;
+    vdec_filmix_ratio_t det2_mix_c;
+    vdec_filmix_ratio_t det2_mix_y;
+    vdec_2dfil_mdsel_t  fil2_mode_2d;
+    vdec_2d_fil_sel_t   fil2_narrow_2d;
+} video_recmd_val_t;
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+static void Input(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void SyncSep(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void YcSep(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void ChromaDec(const graphics_col_sys_t color_system, const vdec_channel_t channel);
+static void DigitalClamp(const vdec_channel_t channel);
+static void Output(const vdec_channel_t channel);
+
+static void init_func(const uint32_t user_num);
+
+static const video_recmd_val_t RecommendedValue[GRPH_COL_SYS_NUM] = {
+    {   /* NTSC-3.58 */
+        /* Capturing position setting */
+        SRCLEFT_NTSC_3_58, SRCTOP_NTSC_3_58, SRCHEIGHT_NTSC_3_58, SRCWIDTH_NTSC_3_58,
+        /* Horizontal AFC setting */
+        HAFCTYP_NTSC_3_58, HAFCMAX_NTSC_3_58, HAFCMIN_NTSC_3_58,
+        /* Vertical countdown setting */
+        VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_NTSC_3_58, VCDOFFSET_NTSC_3_58,
+        /* BCO setting */
+        VDEC_COL_SYS_NTSC, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_NTSC_3_58,
+        /* AGC level setting */
+        AGCLEVEL_NTSC_3_58,
+        /* Y/C separation setting */
+        K15_NTSC_3_58, K13_NTSC_3_58, K11_NTSC_3_58, K16_NTSC_3_58, K14_NTSC_3_58, K12_NTSC_3_58,
+        K22A_NTSC_3_58, K21A_NTSC_3_58, K22B_NTSC_3_58, K21B_NTSC_3_58, K23B_NTSC_3_58, K23A_NTSC_3_58, K24_NTSC_3_58,
+        VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_25, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* NTSC-4.43 */
+        /* Capturing position setting */
+        SRCLEFT_NTSC_4_43, SRCTOP_NTSC_4_43, SRCHEIGHT_NTSC_4_43, SRCWIDTH_NTSC_4_43,
+        /* Horizontal AFC setting */
+        HAFCTYP_NTSC_4_43, HAFCMAX_NTSC_4_43, HAFCMIN_NTSC_4_43,
+        /* Vertical countdown setting */
+        VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_NTSC_4_43, VCDOFFSET_NTSC_4_43,
+        /* BCO setting */
+        VDEC_COL_SYS_NTSC, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_NTSC_4_43,
+        /* AGC level setting */
+        AGCLEVEL_NTSC_4_43,
+        /* Y/C separation setting */
+        K15_NTSC_4_43, K13_NTSC_4_43, K11_NTSC_4_43, K16_NTSC_4_43, K14_NTSC_4_43, K12_NTSC_4_43,
+        K22A_NTSC_4_43, K21A_NTSC_4_43, K22B_NTSC_4_43, K21B_NTSC_4_43, K23B_NTSC_4_43, K23A_NTSC_4_43, K24_NTSC_4_43,
+        VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_25, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* PAL-4.43 */
+        /* Capturing position setting */
+        SRCLEFT_PAL_4_43, SRCTOP_PAL_4_43, SRCHEIGHT_PAL_4_43, SRCWIDTH_PAL_4_43,
+        /* Horizontal AFC setting */
+        HAFCTYP_PAL_4_43, HAFCMAX_PAL_4_43, HAFCMIN_PAL_4_43,
+        /* Vertical countdown setting */
+        VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_PAL_4_43, VCDOFFSET_PAL_4_43,
+        /* BCO setting */
+        VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_PAL_4_43,
+        /* AGC level setting */
+        AGCLEVEL_PAL_4_43,
+        /* Y/C separation setting */
+        K15_PAL_4_43, K13_PAL_4_43, K11_PAL_4_43, K16_PAL_4_43, K14_PAL_4_43, K12_PAL_4_43,
+        K22A_PAL_4_43, K21A_PAL_4_43, K22B_PAL_4_43, K21B_PAL_4_43, K23B_PAL_4_43, K23A_PAL_4_43, K24_PAL_4_43,
+        VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* PAL-M */
+        /* Capturing position setting */
+        SRCLEFT_PAL_M, SRCTOP_PAL_M, SRCHEIGHT_PAL_M, SRCWIDTH_PAL_M,
+        /* Horizontal AFC setting */
+        HAFCTYP_PAL_M, HAFCMAX_PAL_M, HAFCMIN_PAL_M,
+        /* Vertical countdown setting */
+        VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_PAL_M, VCDOFFSET_PAL_M,
+        /* BCO setting */
+        VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_PAL_M,
+        /* AGC level setting */
+        AGCLEVEL_PAL_M,
+        /* Y/C separation setting */
+        K15_PAL_M, K13_PAL_M, K11_PAL_M, K16_PAL_M, K14_PAL_M, K12_PAL_M,
+        K22A_PAL_M, K21A_PAL_M, K22B_PAL_M, K21B_PAL_M, K23B_PAL_M, K23A_PAL_M, K24_PAL_M,
+        VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* PAL-N */
+        /* Capturing position setting */
+        SRCLEFT_PAL_N, SRCTOP_PAL_N, SRCHEIGHT_PAL_N, SRCWIDTH_PAL_N,
+        /* Horizontal AFC setting */
+        HAFCTYP_PAL_N, HAFCMAX_PAL_N, HAFCMIN_PAL_N,
+        /* Vertical countdown setting */
+        VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_PAL_N, VCDOFFSET_PAL_N,
+        /* BCO setting */
+        VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_PAL_N,
+        /* AGC level setting */
+        AGCLEVEL_PAL_N,
+        /* Y/C separation setting */
+        K15_PAL_N, K13_PAL_N, K11_PAL_N, K16_PAL_N, K14_PAL_N, K12_PAL_N,
+        K22A_PAL_N, K21A_PAL_N, K22B_PAL_N, K21B_PAL_N, K23B_PAL_N, K23A_PAL_N, K24_PAL_N,
+        VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* SECAM */
+        /* Capturing position setting */
+        SRCLEFT_SECAM, SRCTOP_SECAM, SRCHEIGHT_SECAM, SRCWIDTH_SECAM,
+        /* Horizontal AFC setting */
+        HAFCTYP_SECAM, HAFCMAX_SECAM, HAFCMIN_SECAM,
+        /* Vertical countdown setting */
+        VDEC_ON, VDEC_OFF, VDEC_VCD_FRQ_50HZ, VCDWINDOW_SECAM, VCDOFFSET_SECAM,
+        /* BCO setting */
+        VDEC_COL_SYS_SECAM, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON,
+        /* ACC level setting */
+        ACCLEVEL_SECAM,
+        /* AGC level setting */
+        AGCLEVEL_SECAM,
+        /* Y/C separation setting */
+        K15_SECAM, K13_SECAM, K11_SECAM, K16_SECAM, K14_SECAM, K12_SECAM,
+        K22A_SECAM, K21A_SECAM, K22B_SECAM, K21B_SECAM, K23B_SECAM, K23A_SECAM, K24_SECAM,
+        VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* NTSC-4.43 (60Hz) */
+        /* Capturing position setting */
+        SRCLEFT_NTSC_443_60, SRCTOP_NTSC_443_60, SRCHEIGHT_NTSC_443_60, SRCWIDTH_NTSC_443_60,
+        /* Horizontal AFC setting */
+        HAFCTYP_NTSC_443_60, HAFCMAX_NTSC_443_60, HAFCMIN_NTSC_443_60,
+        /* Vertical countdown setting */
+        VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_NTSC_443_60, VCDOFFSET_NTSC_443_60,
+        /* BCO setting */
+        VDEC_COL_SYS_NTSC, VDEC_OFF, VDEC_ON, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_NTSC_443_60,
+        /* AGC level setting */
+        AGCLEVEL_NTSC_443_60,
+        /* Y/C separation setting */
+        K15_NTSC_443_60, K13_NTSC_443_60, K11_NTSC_443_60, K16_NTSC_443_60, K14_NTSC_443_60, K12_NTSC_443_60,
+        K22A_NTSC_443_60, K21A_NTSC_443_60, K22B_NTSC_443_60, K21B_NTSC_443_60, K23B_NTSC_443_60, K23A_NTSC_443_60,
+        K24_NTSC_443_60,
+        VDEC_ON, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_75, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_25, VDEC_2DFIL_MDSEL_CASCADE, VDEC_2D_FIL_SEL_17TAP
+    },
+    {   /* PAL-60 */
+        /* Capturing position setting */
+        SRCLEFT_PAL_60, SRCTOP_PAL_60, SRCHEIGHT_PAL_60, SRCWIDTH_PAL_60,
+        /* Horizontal AFC setting */
+        HAFCTYP_PAL_60, HAFCMAX_PAL_60, HAFCMIN_PAL_60,
+        /* Vertical countdown setting */
+        VDEC_OFF, VDEC_ON, VDEC_VCD_FRQ_59_94HZ, VCDWINDOW_PAL_60, VCDOFFSET_PAL_60,
+        /* BCO setting */
+        VDEC_COL_SYS_PAL, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_OFF, VDEC_ON, VDEC_OFF,
+        /* ACC level setting */
+        ACCLEVEL_PAL_60,
+        /* AGC level setting */
+        AGCLEVEL_PAL_60,
+        /* Y/C separation setting */
+        K15_PAL_60, K13_PAL_60, K11_PAL_60, K16_PAL_60, K14_PAL_60, K12_PAL_60,
+        K22A_PAL_60, K21A_PAL_60, K22B_PAL_60, K21B_PAL_60, K23B_PAL_60, K23A_PAL_60, K24_PAL_60,
+        VDEC_OFF, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0,
+        VDEC_FILMIX_RATIO_0, VDEC_FILMIX_RATIO_0, VDEC_2DFIL_MDSEL_BYPASS, VDEC_2D_FIL_SEL_17TAP
+    }
+};
+/* Two-Dimensional Cascade Broadband and Narrowband (3.58/4.43) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t wana_ntsc = {
+    {
+        (uint16_t)24u, (uint16_t)44u, (uint16_t)20u, (uint16_t)(0x1000u | 52u), (uint16_t)(0x1000u | 128u),
+        (uint16_t)(0x1000u | 128u), (uint16_t)(0x1000u | 12u), (uint16_t)132u, (uint16_t)200u
+    }
+};
+/* Two-Dimensional Cascade Broadband (SECAM-DR) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t wa_secam = {
+    {
+        (uint16_t)(0x1000u | 20u), (uint16_t)24u, (uint16_t)64u, (uint16_t)40u, (uint16_t)(0x1000u | 76u),
+        (uint16_t)(0x1000u | 164u), (uint16_t)(0x1000u | 84u), (uint16_t)108u, (uint16_t)216u
+    }
+};
+/* Two-Dimensional Cascade Broadband (SECAM-DB) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t wb_secam = {
+    {
+        (uint16_t)(0x1000u | 12u), (uint16_t)40u, (uint16_t)60u, (uint16_t)12u, (uint16_t)(0x1000u | 104u),
+        (uint16_t)(0x1000u | 156u), (uint16_t)(0x1000u | 64u), (uint16_t)120u, (uint16_t)208u
+    }
+};
+/* Two-Dimensional Cascade Narrowband (SECAM-DR) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t na_secam = {
+    {
+        (uint16_t)(0x1000u | 1008u), (uint16_t)1976u, (uint16_t)(0x1000u | 2024u), (uint16_t)444u, (uint16_t)1868u,
+        (uint16_t)(0x1000u | 2864u), (uint16_t)1352u, (uint16_t)1376u, (uint16_t)(0x1000u | 2240u)
+    }
+};
+/* Two-Dimensional Cascade Narrowband (SECAM-DB) Filter TAP Coefficient */
+static const vdec_chrfil_tap_t nb_secam = {
+    {
+        (uint16_t)(0x1000u | 1080u), (uint16_t)2800u, (uint16_t)(0x1000u | 3308u), (uint16_t)1628u, (uint16_t)1444u,
+        (uint16_t)(0x1000u | 3308u), (uint16_t)2140u, (uint16_t)376u, (uint16_t)(0x1000u | 1384u)
+    }
+};
+
+
+/**************************************************************************//**
+ * @brief       Video decoder initialization
+ * @param       [in]adc_vinsel      : Input pin control
+ * @param       [in]channel         : Channel
+ * @retval      Detected color system
+ *****************************************************************************/
+vdec_error_t GRAPHICS_VideoDecoderInit (const vdec_adc_vinsel_t adc_vinsel, const vdec_channel_t channel, graphics_col_sys_t col_sys)
+{
+    vdec_error_t        error = VDEC_OK;
+
+    /* Video Decoder Driver Initialization */
+    error = R_VDEC_Initialize(channel, adc_vinsel, &init_func, (uint32_t)channel);
+    if (error == VDEC_OK) {
+        if (col_sys != GRPH_COL_SYS_UNKNOWN) {
+            /* Input */
+            Input(col_sys, channel);
+            /* Sync separation */
+            SyncSep(col_sys, channel);
+            /* Y/C separation */
+            YcSep(col_sys, channel);
+            /* Chroma decoding */
+            ChromaDec(col_sys, channel);
+            /* Digital clamp */
+            DigitalClamp(channel);
+            /* Output */
+            Output(channel);
+        } else {
+            error = VDEC_ERR_PARAM;
+        }
+    }
+    return error;
+}   /* End of function GRAPHICS_VideoDecoderInit() */
+
+
+/**************************************************************************//**
+ * @brief       User-defined function
+ * @param       [in]user_num
+ * @retval      None
+ *****************************************************************************/
+static void init_func (const uint32_t user_num)
+{
+    uint32_t            reg_data;
+    volatile uint8_t    dummy_read;
+
+    reg_data = (uint32_t)CPG.STBCR7;
+    if ((vdec_channel_t)user_num == VDEC_CHANNEL_0) {
+        /* Standby control register 7 (STBCR7)
+            b7      0-------;  MSTP77 : 0 : Video decoder channel 0 enable */
+        reg_data &= (uint32_t)~STBCR7_BIT7;
+    } else {
+        /* Standby control register 7 (STBCR7)
+            b6      -0------;  MSTP76 : 0 : Video decoder channel 1 enable */
+        reg_data &= (uint32_t)~STBCR7_BIT6;
+    }
+    CPG.STBCR7 = (uint8_t)reg_data;
+    /* In order to reflect the change, a dummy read should be done. */
+    dummy_read = CPG.STBCR7;
+}   /* End of function init_func() */
+
+/**************************************************************************//**
+ * @brief       Video decoder input setup
+ * @param       [in]color_system    : Color system
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void Input (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+    vdec_error_t                error;
+    vdec_active_period_t        param;
+    const video_recmd_val_t   * RecommendValTbl;
+
+    RecommendValTbl = &RecommendedValue[color_system];
+
+    param.srcleft   = RecommendValTbl->srcleft;     /* Left end of input video signal capturing area */
+    param.srctop    = RecommendValTbl->srctop;      /* Top end of input video signal capturing area */
+    param.srcheight = RecommendValTbl->srcheight;   /* Height of input video signal capturing area */
+    param.srcwidth  = RecommendValTbl->srcwidth;    /* Width of input video signal capturing area */
+    /* Video decoder driver input */
+    error = R_VDEC_ActivePeriod(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function Input() */
+
+/**************************************************************************//**
+ * @brief       Video decoder sync separation setup
+ * @param       [in]color_system    : Color system
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void SyncSep (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+    vdec_error_t                error;
+    vdec_sync_separation_t      param;
+    vdec_noise_rd_lpf_t         noise_rd_lpf_tmp;
+    vdec_sync_slicer_t          sync_slicer_tmp;
+    vdec_horizontal_afc_t       horizontal_afc_tmp;
+    vdec_vcount_down_t          vcount_down_tmp;
+    vdec_agc_t                  agc_tmp;
+    vdec_peak_limiter_t         peak_limiter_tmp;
+    const video_recmd_val_t   * RecommendValTbl;
+
+    RecommendValTbl = &RecommendedValue[color_system];
+
+    /* Noise reduction LPF */
+    noise_rd_lpf_tmp.lpfvsync   = VDEC_LPF_VSYNC_0_54;      /* LPF cutoff frequency before vertical sync separation */
+    noise_rd_lpf_tmp.lpfhsync   = VDEC_LPF_HSYNC_0_94;      /* LPF cutoff frequency before horizontal sync separation */
+    /* Sync slicer */
+    sync_slicer_tmp.velocityshift_h = VDEC_VELOCITY_SHIFT_4;    /* Reference level operation speed control for
+                                                                   composite sync separation (for Hsync signal) */
+    sync_slicer_tmp.slicermode_h    = VDEC_SLICE_MODE_AUTO_50;  /* Auto-slice level setting for composite sync
+                                                                   separator circuit (for Hsync signal) */
+    sync_slicer_tmp.slicermode_v    = VDEC_SLICE_MODE_AUTO_50;  /* Auto-slice level setting for composite sync
+                                                                   separation circuit (for Vsync signal) */
+    sync_slicer_tmp.syncmaxduty_h   = SYNCMAXDUTY_H_VALUE;      /* Max ratio of horizontal cycle to horizontal sync
+                                                                   signal pulse width (for Hsync signal) */
+    sync_slicer_tmp.syncminduty_h   = SYNCMINDUTY_H_VALUE;      /* Min ratio of horizontal cycle to horizontal sync
+                                                                   signal pulse width (for Hsync signal) */
+    sync_slicer_tmp.ssclipsel       = VDEC_CLIP_LV_1023;        /* Clipping level */
+    sync_slicer_tmp.csyncslice_h    = CSYNCSLICE_H_VALUE;       /* Slice level for composite sync
+                                                                   signal separation (for Hsync signal) */
+    sync_slicer_tmp.syncmaxduty_v   = SYNCMAXDUTY_V_VALUE;      /* Max ratio of horizontal cycle to horizontal sync
+                                                                   signal pulse width (for Vsync signal) */
+    sync_slicer_tmp.syncminduty_v   = SYNCMINDUTY_V_VALUE;      /* Min ratio of horizontal cycle to horizontal sync
+                                                                   signal pulse width (for Vsync signal) */
+    sync_slicer_tmp.vsyncdelay      = VDEC_OFF;                 /* Delays the separated vertical sync signal for
+                                                                   1/4 horizontal cycle */
+    sync_slicer_tmp.vsyncslice      = VSYNCSLICE_VALUE;         /* Threshold for vertical sync separation */
+    sync_slicer_tmp.csyncslice_v    = CSYNCSLICE_V_VALUE;       /* Slice level for composite sync
+                                                                   signal separation (for Vsync signal) */
+    /* Horizontal AFC */
+    horizontal_afc_tmp.hafcgain     = HAFCGAIN_VALUE;           /* Horizontal AFC loop gain */
+    horizontal_afc_tmp.hafctyp      = RecommendValTbl->hafctyp; /* Horizontal AFC center oscillation frequency */
+    horizontal_afc_tmp.hafcstart    = HAFCSTART_VALUE;          /* Start line of horizontal AFC normal operation */
+    horizontal_afc_tmp.nox2hosc     = VDEC_ON;                  /* Disable of horizontal AFC double speed detection */
+    horizontal_afc_tmp.hafcmax      = RecommendValTbl->hafcmax; /* Maximum oscillation frequency of horizontal AFC */
+    horizontal_afc_tmp.hafcend      = HAFCEND_VALUE;            /* End line of horizontal AFC normal operation */
+    horizontal_afc_tmp.hafcmode     = VDEC_HAFCMD_AUTO_PHST;    /* Horizontal AFC VBI period operating mode */
+    horizontal_afc_tmp.hafcmin      = RecommendValTbl->hafcmin; /* Min oscillation frequency of horizontal AFC */
+    horizontal_afc_tmp.phdet_fix    = VDEC_OFF;                 /* Forcible or LOWGAIN control */
+    horizontal_afc_tmp.phdet_div    = VDEC_PHDET_DIV_1_32;      /* Phase comparator feedback adjust for
+                                                                   low sync signal lock stability */
+    /* Vertical countdown */
+    vcount_down_tmp.novcd50_    = RecommendValTbl->novcd50_;    /* Vertical countdown 50-Hz oscillation mode */
+    vcount_down_tmp.novcd60_    = RecommendValTbl->novcd60_;    /* Vertical countdown 60-Hz (59.94-Hz)
+                                                                   oscillation mode */
+    vcount_down_tmp.vcddefault  = RecommendValTbl->vcddefault;  /* Vertical countdown center oscillation frequency */
+    vcount_down_tmp.vcdwindow   = RecommendValTbl->vcdwindow;   /* Vertical countdown sync area */
+    vcount_down_tmp.vcdoffset   = RecommendValTbl->vcdoffset;   /* Vertical countdown minimum oscillation frequency */
+    /* AGC / PGA */
+    agc_tmp.agcmode     = VDEC_ON;                  /* A/D converter AGC ON/OFF control & PGA gain select */
+    agc_tmp.doreduce    = VDEC_OFF;                 /* Manual control of sync signal amplitude detection
+                                                       during VBI period */
+    agc_tmp.noreduce_   = VDEC_ON;                  /* Control of sync signal amplitude detection during VBI period */
+    agc_tmp.agcresponse = AGCRESPONSE_VALUE;        /* AGC response speed */
+    agc_tmp.agclevel    = RecommendValTbl->agclevel;/* Sync signal reference amplitude */
+    agc_tmp.agcprecis   = AGCPRECIS_VALUE;          /* AGC gain adjustment accuracy */
+    agc_tmp.pga_gain    = PGA_GAIN_VALUE;           /* PGA gain */
+    /* Peak limiter control */
+    peak_limiter_tmp.peaklevel      = VDEC_PEAKLV_992;      /* Peak luminance value to operate peak limiter */
+    peak_limiter_tmp.peakattack     = PEAKATTACK_VALUE;     /* Response speed with peak limiter gain decreased */
+    peak_limiter_tmp.peakrelease    = PEAKRELEASE_VALUE;    /* Response speed with peak limiter gain increased */
+    peak_limiter_tmp.peakratio      = VDEC_PEAKRATIO_50;    /* Maximum compression rate of peak limiter */
+    peak_limiter_tmp.maxpeaksamples = MAXPEAKSAMPLES_VALUE; /* Allowable number of overflowing pixels */
+
+    param.noise_rd_lpf      = &noise_rd_lpf_tmp;    /* Noise reduction LPF */
+    param.sync_slicer       = &sync_slicer_tmp;     /* Sync slicer */
+    param.horizontal_afc    = &horizontal_afc_tmp;  /* Horizontal AFC */
+    param.vcount_down       = &vcount_down_tmp;     /* Vertical countdown */
+    param.agc               = &agc_tmp;             /* AGC / PGA */
+    param.peak_limiter      = &peak_limiter_tmp;    /* Peak limiter control */
+    /* Video decoder driver sync separation */
+    error = R_VDEC_SyncSeparation(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function SyncSep() */
+
+/**************************************************************************//**
+ * @brief       Video decoder Y/C separation setup
+ * @param       [in]color_system    : Color system
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void YcSep (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+    vdec_error_t                error;
+    vdec_yc_separation_t        param;
+    vdec_over_range_t           over_range_tmp;
+    vdec_yc_sep_ctrl_t          yc_sep_ctrl_tmp;
+    const video_recmd_val_t   * RecommendValTbl;
+
+    RecommendValTbl = &RecommendedValue[color_system];
+
+    /* Over-range control */
+    over_range_tmp.radj_o_level0    = RADJ_O_LEVEL0_VALUE;   /* A/D over-threshold level (between levels 0 and 1) */
+    over_range_tmp.radj_u_level0    = RADJ_U_LEVEL0_VALUE;   /* A/D under-threshold level (between levels 2 and 3) */
+    over_range_tmp.radj_o_level1    = RADJ_O_LEVEL1_VALUE;   /* A/D over-threshold level (between levels 1 and 2) */
+    over_range_tmp.radj_u_level1    = RADJ_U_LEVEL1_VALUE;   /* A/D under-threshold level (between levels 1 and 2) */
+    over_range_tmp.radj_o_level2    = RADJ_O_LEVEL2_VALUE;   /* A/D over-threshold level (between levels 2 and 3) */
+    over_range_tmp.radj_u_level2    = RADJ_U_LEVEL2_VALUE;   /* A/D under-threshold level (between levels 0 and 1) */
+    over_range_tmp.ucmp_sw          = VDEC_ON;          /* Over-range detection */
+    over_range_tmp.dcmp_sw          = VDEC_ON;          /* Under-range detection */
+    over_range_tmp.hwide_sw         = VDEC_ON;          /* Horizontal enlargement of over/under-range level */
+    /* Y/C separation control */
+    /* Two-dimensional Y/C separation filter select coefficient */
+    yc_sep_ctrl_tmp.k15             = RecommendValTbl->k15;         /* K15 */
+    yc_sep_ctrl_tmp.k13             = RecommendValTbl->k13;         /* K13 */
+    yc_sep_ctrl_tmp.k11             = RecommendValTbl->k11;         /* K11 */
+    yc_sep_ctrl_tmp.k16             = RecommendValTbl->k16;         /* K16 */
+    yc_sep_ctrl_tmp.k14             = RecommendValTbl->k14;         /* K14 */
+    yc_sep_ctrl_tmp.k12             = RecommendValTbl->k12;         /* K12 */
+    yc_sep_ctrl_tmp.k22a            = RecommendValTbl->k22A;        /* K22A */
+    yc_sep_ctrl_tmp.k21a            = RecommendValTbl->k21A;        /* K21A */
+    yc_sep_ctrl_tmp.k22b            = RecommendValTbl->k22B;        /* K22B */
+    yc_sep_ctrl_tmp.k21b            = RecommendValTbl->k21B;        /* K21B */
+    yc_sep_ctrl_tmp.k23b            = RecommendValTbl->k23B;        /* K23B */
+    yc_sep_ctrl_tmp.k23a            = RecommendValTbl->k23A;        /* K23A */
+    yc_sep_ctrl_tmp.k24             = RecommendValTbl->k24;         /* K24 */
+    yc_sep_ctrl_tmp.hbpf_narrow     = VDEC_LSTG_BPFSEL_BYPASS;      /* Latter-stage horizontal BPF select */
+    yc_sep_ctrl_tmp.hvbpf_narrow    = VDEC_LSTG_BPFSEL_BYPASS;      /* Latter-stage horizontal/vertical BPF select */
+    yc_sep_ctrl_tmp.hbpf1_9tap_on   = VDEC_FSTG_BPFSEL_17TAP;       /* Former-stage horizontal BPF select */
+    yc_sep_ctrl_tmp.hvbpf1_9tap_on  = VDEC_FSTG_BPFSEL_17TAP;       /* Former-stage horizontal/vertical BPF select */
+    yc_sep_ctrl_tmp.hfil_tap_sel    = VDEC_HFIL_TAP_SEL_17TAP;      /* Horizontal filter and horizontal/vertical filter
+                                                                       bandwidth switch signal */
+    yc_sep_ctrl_tmp.det2_on         = RecommendValTbl->det2_on;     /* Two-dimensional filter mixing select */
+    yc_sep_ctrl_tmp.hsel_mix_y      = RecommendValTbl->hsel_mix_y;  /* Mixing ratio of signal after passing
+                                                                       horizontal filter to signal after passing
+                                                                       former-stage horizontal filter */
+    yc_sep_ctrl_tmp.vsel_mix_y      = RecommendValTbl->vsel_mix_y;  /* Mixing ratio of signal after passing
+                                                                       vertical filter to signal after passing
+                                                                       former-stage horizontal/vertical filter */
+    yc_sep_ctrl_tmp.hvsel_mix_y     = RecommendValTbl->hvsel_mix_y; /* Mixing ratio of signal after passing
+                                                                       horizontal/vertical filter to signal
+                                                                       after passing former-stage
+                                                                       horizontal/vertical filter */
+    yc_sep_ctrl_tmp.v_y_level       = V_Y_LEVEL_VALUE;              /* Vertical luminance detection level
+                                                                       for correlation detection filter */
+    yc_sep_ctrl_tmp.det2_mix_c      = RecommendValTbl->det2_mix_c;  /* Mixing ratio of c signal after passing
+                                                                       horizontal/vertical adaptive filter
+                                                                       to signal after passing correlation detection
+                                                                       filter */
+    yc_sep_ctrl_tmp.det2_mix_y      = RecommendValTbl->det2_mix_y;  /* Mixing ratio of c signal for y generation after
+                                                                       passing horizontal/vertical adaptive filter to
+                                                                       signal after passing correlation */
+    yc_sep_ctrl_tmp.fil2_mode_2d    = RecommendValTbl->fil2_mode_2d;/* Two-dimensional cascade/TAKE-OFF
+                                                                       filter mode select */
+    yc_sep_ctrl_tmp.fil2_narrow_2d  = RecommendValTbl->fil2_narrow_2d;  /* Two-dimensional cascade filter select */
+
+    param.over_range    = &over_range_tmp;  /* Over-range control */
+    param.yc_sep_ctrl   = &yc_sep_ctrl_tmp; /* Y/C separation control */
+    param.fil2_2d_wa    = NULL;             /* Two-dimensional cascade broadband
+                                               (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient */
+    param.fil2_2d_wb    = NULL;             /* Two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient */
+    param.fil2_2d_na    = NULL;             /* Two-dimensional cascade narrowband
+                                               (3.58/4.43/SECAM-DR) filter TAP coefficient */
+    param.fil2_2d_nb    = NULL;             /* Two-dimensional cascade narrowband (SECAMDB) filter TAP coefficient */
+    if ((color_system == GRPH_COL_SYS_NTSC_358) ||
+            (color_system == GRPH_COL_SYS_NTSC_443) ||
+            (color_system == GRPH_COL_SYS_NTSC_443_60)) {
+        param.fil2_2d_wa = &wana_ntsc;
+        param.fil2_2d_na = &wana_ntsc;
+    } else if (color_system == GRPH_COL_SYS_SECAM) {
+        param.fil2_2d_wa = &wa_secam;
+        param.fil2_2d_wb = &wb_secam;
+        param.fil2_2d_na = &na_secam;
+        param.fil2_2d_nb = &nb_secam;
+    } else {
+        /* Do nothing */
+    }
+    /* Video decoder driver y/c separation */
+    error = R_VDEC_YcSeparation(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function YcSep() */
+
+/**************************************************************************//**
+ * @brief       Video decoder chroma decoding setup
+ * @param       [in]color_system    : Color system
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void ChromaDec (const graphics_col_sys_t color_system, const vdec_channel_t channel)
+{
+    vdec_error_t                error;
+    vdec_chroma_decoding_t      param;
+    vdec_chrmdec_ctrl_t         chrmdec_ctrl_tmp;
+    vdec_burst_lock_t           burst_lock_tmp;
+    vdec_acc_t                  acc_tmp;
+    const video_recmd_val_t   * RecommendValTbl;
+
+    RecommendValTbl = &RecommendedValue[color_system];
+
+    /* Chroma decoding control */
+    chrmdec_ctrl_tmp.defaultsys = RecommendValTbl->defaultsys;  /* Default color system */
+    chrmdec_ctrl_tmp.nontsc358_ = RecommendValTbl->nontsc358_;  /* NTSC-M detection control */
+    chrmdec_ctrl_tmp.nontsc443_ = RecommendValTbl->nontsc443_;  /* NTSC-4.43 detection control */
+    chrmdec_ctrl_tmp.nopalm_    = RecommendValTbl->nopalm_;     /* PAL-M detection control */
+    chrmdec_ctrl_tmp.nopaln_    = RecommendValTbl->nopaln_;     /* PAL-N detection control */
+    chrmdec_ctrl_tmp.nopal443_  = RecommendValTbl->nopal443_;   /* PAL-B, G, H, I, D detection control */
+    chrmdec_ctrl_tmp.nosecam_   = RecommendValTbl->nosecam_;    /* SECAM detection control */
+    chrmdec_ctrl_tmp.lumadelay  = LUMADELAY_VALUE;              /* Luminance signal delay adjustment */
+    chrmdec_ctrl_tmp.chromalpf  = VDEC_OFF;                     /* LPF for demodulated chroma */
+    chrmdec_ctrl_tmp.demodmode  = VDEC_DEMOD_MD_PAL;            /* Averaging processing for pre-demodulated line */
+    /* Burst lock */
+    burst_lock_tmp.lockrange    = VDEC_LOCK_RANGE_800HZ;/* Burst lock PLL lock range */
+    burst_lock_tmp.loopgain     = LOOPGAIN_VALUE;       /* Burst lock PLL loop gain */
+    burst_lock_tmp.locklimit    = LOCKLIMIT_VALUE;      /* Level for burst lock PLL to re-search free-run frequency */
+    burst_lock_tmp.bgpcheck     = BGPCHECK_VALUE;       /* burst gate pulse position check */
+    burst_lock_tmp.bgpwidth     = BGPWIDTH_VALUE;       /* burst gate pulse width */
+    burst_lock_tmp.bgpstart     = BGPSTART_VALUE;       /* burst gate pulse start position */
+    /* ACC / color killer */
+    acc_tmp.accmode         = VDEC_ACC_MD_AUTO;         /* ACC operating mode */
+    acc_tmp.accmaxgain      = VDEC_ACC_MAX_GAIN_6;      /* Maximum ACC Gain */
+    acc_tmp.acclevel        = RecommendValTbl->acclevel;/* ACC reference color burst amplitude */
+    acc_tmp.chromasubgain   = VDEC_CHRM_SB_GAIN_1;      /* Chroma manual gain (sub) */
+    acc_tmp.chromamaingain  = CHROMAMAINGAIN_VALUE;     /* Chroma manual gain (main) */
+    acc_tmp.accresponse     = ACCRESPONSE_VALUE;        /* ACC response speed */
+    acc_tmp.accprecis       = ACCPRECIS_VALUE;          /* ACC gain adjustment accuracy */
+    acc_tmp.killermode      = VDEC_OFF;                 /* Forced color killer mode ON/OFF */
+    acc_tmp.killerlevel     = KILLERLEVEL_VALUE;        /* Color killer operation start point */
+    acc_tmp.killeroffset    = KILLEROFFSET_VALUE;       /* The offset level to turn off the color killer */
+
+    param.chrmdec_ctrl  = &chrmdec_ctrl_tmp;    /* Chroma decoding control */
+    param.burst_lock    = &burst_lock_tmp;      /* Burst lock */
+    param.acc           = &acc_tmp;             /* ACC/color killer */
+    param.tint_ry       = NULL;                 /* TINT/R-Y axis correction (only valid for NTSC/PAL) */
+    /* Video decoder driver chroma decoding */
+    error = R_VDEC_ChromaDecoding(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function ChromaDec() */
+
+/**************************************************************************//**
+ * @brief       Video decoder digital clamp setup
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void DigitalClamp (const vdec_channel_t channel)
+{
+    vdec_error_t            error;
+    vdec_degital_clamp_t    param;
+    vdec_pedestal_clamp_t   pedestal_clamp_tmp;
+    vdec_center_clamp_t     center_clamp_tmp;
+    vdec_noise_det_t        noise_det_tmp;
+
+    /* Pedestal clamp */
+    pedestal_clamp_tmp.dcpmode_y    = VDEC_DCPMODE_AUTO;    /* Clamp level setting mode */
+    pedestal_clamp_tmp.blanklevel_y = BLANKLEVEL_Y_VALUE;   /* Clamp offset level (Y signal) */
+    pedestal_clamp_tmp.dcppos_y     = DCPPOS_Y_VALUE;   /* Digital clamp pulse horizontal start position (Y signal) */
+    /* Center clamp */
+    center_clamp_tmp.dcpmode_c      = VDEC_DCPMODE_MANUAL;  /* Clamp level setting mode */
+    center_clamp_tmp.blanklevel_cb  = BLANKLEVEL_CB_VALUE;  /* Clamp offset level (Cb signal) */
+    center_clamp_tmp.blanklevel_cr  = BLANKLEVEL_CR_VALUE;  /* Clamp offset level (Cr signal) */
+    center_clamp_tmp.dcppos_c       = DCPPOS_C_VALUE;       /* Digital clamp pulse
+                                                               horizontal start position (Cb/Cr signal) */
+    /* Noise detection */
+    noise_det_tmp.acfinput      = VDEC_ACFINPUT_Y;  /* Video signal for autocorrelation function */
+    noise_det_tmp.acflagtime    = ACFLAGTIME_VALUE; /* Delay time for autocorrelation function calculation */
+    noise_det_tmp.acffilter     = ACFFILTER_VALUE;  /* Smoothing parameter of autocorrelation function data */
+
+    param.dcpcheck          = VDEC_OFF;             /* Digital clamp pulse position check */
+    param.dcpresponse       = DCPRESPONSE_VALUE;    /* Digital clamp response speed */
+    param.dcpstart          = DCPSTART_VALUE;       /* Digital clamp start line (in 1-line units) */
+    param.dcpend            = DCPEND_VALUE;         /* Digital clamp end line (in 1-line units) */
+    param.dcpwidth          = DCPWIDTH_VALUE;       /* Digital clamp pulse width */
+    param.pedestal_clamp    = &pedestal_clamp_tmp;  /* Pedestal clamp */
+    param.center_clamp      = &center_clamp_tmp;    /* Center clamp */
+    param.noise_det         = &noise_det_tmp;       /* Noise detection */
+    /* Video decoder driver digital clamp */
+    error = R_VDEC_DigitalClamp(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function DigitalClamp() */
+
+/**************************************************************************//**
+ * @brief       Video decoder output adjustment setup
+ * @param       [in]channel         : Channel
+ * @retval      None
+ *****************************************************************************/
+static void Output (const vdec_channel_t channel)
+{
+    vdec_error_t        error;
+    vdec_output_t       param;
+
+    param.y_gain2   = Y_GAIN2_VALUE;        /* Y signal gain coefficient */
+    param.cb_gain2  = CB_GAIN2_VALUE;       /* Cb signal gain coefficient */
+    param.cr_gain2  = CR_GAIN2_VALUE;       /* Cr signal gain coefficient */
+    /* Video decoder driver output */
+    error = R_VDEC_Output(channel, &param);
+    if (error != VDEC_OK) {
+    }
+}   /* End of function Output() */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/IUSBEnumerator.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,36 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef IUSBENUMERATOR_H_
+#define IUSBENUMERATOR_H_
+
+#include "stdint.h"
+#include "USBEndpoint.h"
+
+/*
+Generic interface to implement for "smart" USB enumeration
+*/
+
+class IUSBEnumerator
+{
+public:
+    virtual void setVidPid(uint16_t vid, uint16_t pid) = 0;
+    virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) = 0; //Must return true if the interface should be parsed
+    virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) = 0; //Must return true if the endpoint will be used
+};
+
+#endif /*IUSBENUMERATOR_H_*/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/devdrv_usb_host_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,329 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : devdrv_usb_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_HOST_API_H
+#define USB_HOST_API_H
+
+#include "r_typedefs.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_HOST_PORTNUM                            (2)
+
+#define USB_HOST_ELT_INTERRUPT_LEVEL                (9)
+
+#define USBHCLOCK_X1_48MHZ                          (0x0000u)       /* USB_X1_48MHz */
+#define USBHCLOCK_EXTAL_12MHZ                       (0x0004u)       /* EXTAL_12MHz  */
+
+#define USB_HOST_MAX_DEVICE                         (10)
+
+#define USB_HOST_ON                                 (1)
+#define USB_HOST_OFF                                (0)
+#define USB_HOST_YES                                (1)
+#define USB_HOST_NO                                 (0)
+
+#define USB_HOST_NON_SPEED                          (0)
+#define USB_HOST_LOW_SPEED                          (1)
+#define USB_HOST_FULL_SPEED                         (2)
+#define USB_HOST_HIGH_SPEED                         (3)
+
+/* DEVDRV_SUCCESS(0) & DEVDRV_ERROR(-1) is dev_drv.h */
+#define DEVDRV_USBH_STALL                           (-2)
+#define DEVDRV_USBH_TIMEOUT                         (-3)
+#define DEVDRV_USBH_NAK_TIMEOUT                     (-4)
+#define DEVDRV_USBH_DETACH_ERR                      (-5)
+#define DEVDRV_USBH_SETUP_ERR                       (-6)
+#define DEVDRV_USBH_CTRL_COM_ERR                    (-7)
+#define DEVDRV_USBH_COM_ERR                         (-8)
+#define DEVDRV_USBH_DEV_ADDR_ERR                    (-9)
+
+#define USB_HOST_ATTACH                             (1)
+#define USB_HOST_DETACH                             (0)
+
+#define USB_HOST_MAX_PIPE_NO                        (9u)
+#define USB_HOST_PIPE0                              (0)
+#define USB_HOST_PIPE1                              (1)
+#define USB_HOST_PIPE2                              (2)
+#define USB_HOST_PIPE3                              (3)
+#define USB_HOST_PIPE4                              (4)
+#define USB_HOST_PIPE5                              (5)
+#define USB_HOST_PIPE6                              (6)
+#define USB_HOST_PIPE7                              (7)
+#define USB_HOST_PIPE8                              (8)
+#define USB_HOST_PIPE9                              (9)
+
+#define USB_HOST_ISO                                (0xc000u)
+#define USB_HOST_INTERRUPT                          (0x8000u)
+#define USB_HOST_BULK                               (0x4000u)
+
+#define USB_HOST_PIPE_IDLE                          (0x00)
+#define USB_HOST_PIPE_WAIT                          (0x01)
+#define USB_HOST_PIPE_DONE                          (0x02)
+#define USB_HOST_PIPE_NORES                         (0x03)
+#define USB_HOST_PIPE_STALL                         (0x04)
+#define USB_HOST_PIPE_ERROR                         (0x05)
+
+#define USB_HOST_NONE                               (0x0000u)
+#define USB_HOST_BFREFIELD                          (0x0400u)
+#define USB_HOST_BFREON                             (0x0400u)
+#define USB_HOST_BFREOFF                            (0x0000u)
+#define USB_HOST_DBLBFIELD                          (0x0200u)
+#define USB_HOST_DBLBON                             (0x0200u)
+#define USB_HOST_DBLBOFF                            (0x0000u)
+#define USB_HOST_CNTMDFIELD                         (0x0100u)
+#define USB_HOST_CNTMDON                            (0x0100u)
+#define USB_HOST_CNTMDOFF                           (0x0000u)
+#define USB_HOST_SHTNAKON                           (0x0080u)
+#define USB_HOST_SHTNAKOFF                          (0x0000u)
+#define USB_HOST_DIRFIELD                           (0x0010u)
+#define USB_HOST_DIR_H_OUT                          (0x0010u)
+#define USB_HOST_DIR_H_IN                           (0x0000u)
+#define USB_HOST_EPNUMFIELD                         (0x000fu)
+
+#define USB_HOST_CUSE                               (0)
+#define USB_HOST_D0USE                              (1)
+#define USB_HOST_D0DMA                              (2)
+#define USB_HOST_D1USE                              (3)
+#define USB_HOST_D1DMA                              (4)
+
+#define USB_HOST_CFIFO_USE                          (0x0000)
+#define USB_HOST_D0FIFO_USE                         (0x1000)
+#define USB_HOST_D1FIFO_USE                         (0x2000)
+#define USB_HOST_D0FIFO_DMA                         (0x5000)
+#define USB_HOST_D1FIFO_DMA                         (0x6000)
+
+#define USB_HOST_BUF2FIFO                           (0)
+#define USB_HOST_FIFO2BUF                           (1)
+
+#define USB_HOST_DRV_DETACHED                       (0x0000)
+#define USB_HOST_DRV_ATTACHED                       (0x0001)
+#define USB_HOST_DRV_GET_DEVICE_DESC_64             (0x0002)
+#define USB_HOST_DRV_POWERED                        (0x0003)
+#define USB_HOST_DRV_DEFAULT                        (0x0004)
+#define USB_HOST_DRV_SET_ADDRESS                    (0x0005)
+#define USB_HOST_DRV_ADDRESSED                      (0x0006)
+#define USB_HOST_DRV_GET_DEVICE_DESC_18             (0x0007)
+#define USB_HOST_DRV_GET_CONGIG_DESC_9              (0x0008)
+#define USB_HOST_DRV_GET_CONGIG_DESC                (0x0009)
+#define USB_HOST_DRV_SET_CONFIG                     (0x000a)
+#define USB_HOST_DRV_CONFIGURED                     (0x000b)
+#define USB_HOST_DRV_SUSPEND                        (0x1000)
+#define USB_HOST_DRV_NORES                          (0x0100)
+#define USB_HOST_DRV_STALL                          (0x0200)
+
+#define USB_HOST_TESTMODE_FORCE                     (0x000du)
+#define USB_HOST_TESTMODE_TESTPACKET                (0x000cu)
+#define USB_HOST_TESTMODE_SE0_NAK                   (0x000bu)
+#define USB_HOST_TESTMODE_K                         (0x000au)
+#define USB_HOST_TESTMODE_J                         (0x0009u)
+#define USB_HOST_TESTMODE_NORMAL                    (0x0000u)
+
+#define USB_HOST_DT_DEVICE                          (0x01)
+#define USB_HOST_DT_CONFIGURATION                   (0x02)
+#define USB_HOST_DT_STRING                          (0x03)
+#define USB_HOST_DT_INTERFACE                       (0x04)
+#define USB_HOST_DT_ENDPOINT                        (0x05)
+#define USB_HOST_DT_DEVICE_QUALIFIER                (0x06)
+#define USB_HOST_DT_OTHER_SPEED_CONFIGURATION       (0x07)
+#define USB_HOST_DT_INTERFACE_POWER                 (0x08)
+
+#define USB_HOST_IF_CLS_NOT                         (0x00)
+#define USB_HOST_IF_CLS_AUDIO                       (0x01)
+#define USB_HOST_IF_CLS_CDC_CTRL                    (0x02)
+#define USB_HOST_IF_CLS_HID                         (0x03)
+#define USB_HOST_IF_CLS_PHYSICAL                    (0x05)
+#define USB_HOST_IF_CLS_IMAGE                       (0x06)
+#define USB_HOST_IF_CLS_PRINTER                     (0x07)
+#define USB_HOST_IF_CLS_MASS                        (0x08)
+#define USB_HOST_IF_CLS_HUB                         (0x09)
+#define USB_HOST_IF_CLS_CDC_DATA                    (0x0a)
+#define USB_HOST_IF_CLS_CRAD                        (0x0b)
+#define USB_HOST_IF_CLS_CONTENT                     (0x0d)
+#define USB_HOST_IF_CLS_VIDEO                       (0x0e)
+#define USB_HOST_IF_CLS_DIAG                        (0xdc)
+#define USB_HOST_IF_CLS_WIRELESS                    (0xe0)
+#define USB_HOST_IF_CLS_APL                         (0xfe)
+#define USB_HOST_IF_CLS_VENDOR                      (0xff)
+#define USB_HOST_IF_CLS_HELE                        (0xaa)
+
+#define USB_HOST_EP_DIR_MASK                        (0x80)
+#define USB_HOST_EP_OUT                             (0x00)
+#define USB_HOST_EP_IN                              (0x80)
+#define USB_HOST_EP_TYPE                            (0x03)
+#define USB_HOST_EP_CNTRL                           (0x00)
+#define USB_HOST_EP_ISO                             (0x01)
+#define USB_HOST_EP_BULK                            (0x02)
+#define USB_HOST_EP_INT                             (0x03)
+#define USB_HOST_EP_NUM_MASK                        (0x0f)
+
+#define USB_HOST_PIPE_IN                            (0)
+#define USB_HOST_PIPE_OUT                           (1)
+
+#define USB_END_POINT_ERROR                         (0xffff)
+
+#define USB_HOST_REQ_GET_STATUS                     (0x0000)
+#define USB_HOST_REQ_CLEAR_FEATURE                  (0x0100)
+#define USB_HOST_REQ_RESERVED2                      (0x0200)
+#define USB_HOST_REQ_SET_FEATURE                    (0x0300)
+#define USB_HOST_REQ_RESERVED4                      (0x0400)
+#define USB_HOST_REQ_SET_ADDRESS                    (0x0500)
+#define USB_HOST_REQ_GET_DESCRIPTOR                 (0x0600)
+#define USB_HOST_REQ_SET_DESCRIPTOR                 (0x0700)
+#define USB_HOST_REQ_GET_CONFIGURATION              (0x0800)
+#define USB_HOST_REQ_SET_CONFIGURATION              (0x0900)
+#define USB_HOST_REQ_GET_INTERFACE                  (0x0a00)
+#define USB_HOST_REQ_SET_INTERFACE                  (0x0b00)
+#define USB_HOST_REQ_SYNCH_FRAME                    (0x0c00)
+
+#define USB_HOST_REQTYPE_HOST_TO_DEVICE             (0x0000)
+#define USB_HOST_REQTYPE_DEVICE_TO_HOST             (0x0080)
+#define USB_HOST_REQTYPE_STANDARD                   (0x0020)
+#define USB_HOST_REQTYPE_CLASS                      (0x0040)
+#define USB_HOST_REQTYPE_VENDOR                     (0x0060)
+#define USB_HOST_REQTYPE_DEVICE                     (0x0000)
+#define USB_HOST_REQTYPE_INTERFACE                  (0x0001)
+#define USB_HOST_REQTYPE_ENDPOINT                   (0x0002)
+#define USB_HOST_REQTYPE_OTHER                      (0x0003)
+
+#define USB_HOST_DESCTYPE_DEVICE                    (0x0100)
+#define USB_HOST_DESCTYPE_CONFIGURATION             (0x0200)
+#define USB_HOST_DESCTYPE_STRING                    (0x0300)
+#define USB_HOST_DESCTYPE_INTERFACE                 (0x0400)
+#define USB_HOST_DESCTYPE_ENDPOINT                  (0x0500)
+#define USB_HOST_DESCTYPE_DEVICE_QUALIFIER          (0x0600)
+#define USB_HOST_DESCTYPE_OTHER_SPEED_CONFIGURATION (0x0700)
+#define USB_HOST_DESCTYPE_INTERFACE_POWER           (0x0800)
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+typedef struct
+{
+    uint16_t    pipe_number;
+    uint16_t    pipe_cfg;
+    uint16_t    pipe_buf;
+    uint16_t    pipe_max_pktsize;
+    uint16_t    pipe_cycle;
+    uint16_t    fifo_port;
+} USB_HOST_CFG_PIPETBL_t;
+
+typedef struct
+{
+    uint32_t    fifo;
+    uint32_t    buffer;
+    uint32_t    bytes;
+    uint32_t    dir;
+    uint32_t    size;
+} USB_HOST_DMA_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+uint16_t R_USB_api_host_init(uint16_t root, uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t R_USB_api_host_enumeration(uint16_t root, uint16_t devadr);
+int32_t R_USB_api_host_detach(uint16_t root);
+int32_t R_USB_api_host_data_in(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t R_USB_api_host_data_in2(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf, uint32_t *bytes);
+int32_t R_USB_api_host_data_out(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t R_USB_api_host_control_transfer(uint16_t root, uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t R_USB_api_host_set_endpoint(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t R_USB_api_host_clear_endpoint(uint16_t root, USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t R_USB_api_host_clear_endpoint_pipe(uint16_t root, uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t R_USB_api_host_SetEndpointTable(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table);
+
+int32_t R_USB_api_host_GetDeviceDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t R_USB_api_host_GetConfigDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t R_USB_api_host_SetConfig(uint16_t root, uint16_t devadr, uint16_t confignum);
+int32_t R_USB_api_host_SetInterface(uint16_t root, uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t R_USB_api_host_ClearStall(uint16_t root, uint16_t devadr, uint16_t ep_dir);
+uint16_t R_USB_api_host_GetUsbDeviceState(uint16_t root);
+
+void    R_USB_api_host_elt_clocksel(uint16_t clockmode);
+void    R_USB_api_host_elt_4_4(uint16_t root);
+void    R_USB_api_host_elt_4_5(uint16_t root);
+void    R_USB_api_host_elt_4_6(uint16_t root);
+void    R_USB_api_host_elt_4_7(uint16_t root);
+void    R_USB_api_host_elt_4_8(uint16_t root);
+void    R_USB_api_host_elt_4_9(uint16_t root);
+void    R_USB_api_host_elt_get_desc(uint16_t root);
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host_api.h"
+#include "usb1_host_api.h"
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+#ifdef USB0_HOST_API_H
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void);
+void     Userdef_USB_usb0_host_attach(void);
+void     Userdef_USB_usb0_host_detach(void);
+void     Userdef_USB_usb0_host_delay_1ms(void);
+void     Userdef_USB_usb0_host_delay_xms(uint32_t msec);
+void     Userdef_USB_usb0_host_delay_10us(uint32_t usec);
+void     Userdef_USB_usb0_host_delay_500ns(void);
+void     Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb0_host_stop_dma0(void);
+uint32_t Userdef_USB_usb0_host_stop_dma1(void);
+void     Userdef_USB_usb0_host_notice(const char * format);
+void     Userdef_USB_usb0_host_user_rdy(const char * format, uint16_t data);
+#endif
+
+#ifdef USB1_HOST_API_H
+uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid(void);
+void     Userdef_USB_usb1_host_attach(void);
+void     Userdef_USB_usb1_host_detach(void);
+void     Userdef_USB_usb1_host_delay_1ms(void);
+void     Userdef_USB_usb1_host_delay_xms(uint32_t msec);
+void     Userdef_USB_usb1_host_delay_10us(uint32_t usec);
+void     Userdef_USB_usb1_host_delay_500ns(void);
+void     Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb1_host_stop_dma0(void);
+uint32_t Userdef_USB_usb1_host_stop_dma1(void);
+void     Userdef_USB_usb1_host_notice(const char * format);
+void     Userdef_USB_usb1_host_user_rdy(const char * format, uint16_t data);
+#endif
+
+#endif /* USB_HOST_API_H */
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/usb_host.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,201 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_HOST_H
+#define USB_HOST_H
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_HOST_DEVICE_0               (0u)
+#define USB_HOST_DEVICE_1               (1u)
+#define USB_HOST_DEVICE_2               (2u)
+#define USB_HOST_DEVICE_3               (3u)
+#define USB_HOST_DEVICE_4               (4u)
+#define USB_HOST_DEVICE_5               (5u)
+#define USB_HOST_DEVICE_6               (6u)
+#define USB_HOST_DEVICE_7               (7u)
+#define USB_HOST_DEVICE_8               (8u)
+#define USB_HOST_DEVICE_9               (9u)
+#define USB_HOST_DEVICE_10              (10u)
+
+#define USB_HOST_ENDPOINT_DESC          (0x05)
+
+#define USB_HOST_BITUPLLE               (0x0002u)
+#define USB_HOST_BITUCKSEL              (0x0004u)
+#define USB_HOST_BITBWAIT               (0x003fu)
+
+#define USB_HOST_BUSWAIT_02             (0x0000u)
+#define USB_HOST_BUSWAIT_03             (0x0001u)
+#define USB_HOST_BUSWAIT_04             (0x0002u)
+#define USB_HOST_BUSWAIT_05             (0x0003u)
+#define USB_HOST_BUSWAIT_06             (0x0004u)
+#define USB_HOST_BUSWAIT_07             (0x0005u)
+#define USB_HOST_BUSWAIT_08             (0x0006u)
+#define USB_HOST_BUSWAIT_09             (0x0007u)
+#define USB_HOST_BUSWAIT_10             (0x0008u)
+#define USB_HOST_BUSWAIT_11             (0x0009u)
+#define USB_HOST_BUSWAIT_12             (0x000au)
+#define USB_HOST_BUSWAIT_13             (0x000bu)
+#define USB_HOST_BUSWAIT_14             (0x000cu)
+#define USB_HOST_BUSWAIT_15             (0x000du)
+#define USB_HOST_BUSWAIT_16             (0x000eu)
+#define USB_HOST_BUSWAIT_17             (0x000fu)
+
+#define USB_HOST_FS_JSTS                (0x0001u)
+#define USB_HOST_LS_JSTS                (0x0002u)
+
+#define USB_HOST_BITRST                 (0x0040u)
+#define USB_HOST_BITRESUME              (0x0020u)
+#define USB_HOST_BITUACT                (0x0010u)
+#define USB_HOST_HSPROC                 (0x0004u)
+#define USB_HOST_HSMODE                 (0x0003u)
+#define USB_HOST_FSMODE                 (0x0002u)
+#define USB_HOST_LSMODE                 (0x0001u)
+#define USB_HOST_UNDECID                (0x0000u)
+
+#define USB_HOST_BITRCNT                (0x8000u)
+#define USB_HOST_BITDREQE               (0x1000u)
+#define USB_HOST_BITMBW                 (0x0c00u)
+#define USB_HOST_BITMBW_8               (0x0000u)
+#define USB_HOST_BITMBW_16              (0x0400u)
+#define USB_HOST_BITMBW_32              (0x0800u)
+#define USB_HOST_BITBYTE_LITTLE         (0x0000u)
+#define USB_HOST_BITBYTE_BIG            (0x0100u)
+#define USB_HOST_BITISEL                (0x0020u)
+#define USB_HOST_BITCURPIPE             (0x000fu)
+
+#define USB_HOST_CFIFO_READ             (0x0000u)
+#define USB_HOST_CFIFO_WRITE            (0x0020u)
+
+#define USB_HOST_BITBVAL                (0x8000u)
+#define USB_HOST_BITBCLR                (0x4000u)
+#define USB_HOST_BITFRDY                (0x2000u)
+#define USB_HOST_BITDTLN                (0x0fffu)
+
+#define USB_HOST_BITBEMPE               (0x0400u)
+#define USB_HOST_BITNRDYE               (0x0200u)
+#define USB_HOST_BITBRDYE               (0x0100u)
+#define USB_HOST_BITBEMP                (0x0400u)
+#define USB_HOST_BITNRDY                (0x0200u)
+#define USB_HOST_BITBRDY                (0x0100u)
+
+#define USB_HOST_BITBCHGE               (0x4000u)
+#define USB_HOST_BITDTCHE               (0x1000u)
+#define USB_HOST_BITATTCHE              (0x0800u)
+#define USB_HOST_BITEOFERRE             (0x0040u)
+#define USB_HOST_BITBCHG                (0x4000u)
+#define USB_HOST_BITDTCH                (0x1000u)
+#define USB_HOST_BITATTCH               (0x0800u)
+#define USB_HOST_BITEOFERR              (0x0040u)
+
+#define USB_HOST_BITSIGNE               (0x0020u)
+#define USB_HOST_BITSACKE               (0x0010u)
+#define USB_HOST_BITSIGN                (0x0020u)
+#define USB_HOST_BITSACK                (0x0010u)
+
+#define USB_HOST_BITSUREQ               (0x4000u)
+#define USB_HOST_BITSQSET               (0x0080u)
+#define USB_HOST_PID_STALL2             (0x0003u)
+#define USB_HOST_PID_STALL              (0x0002u)
+#define USB_HOST_PID_BUF                (0x0001u)
+#define USB_HOST_PID_NAK                (0x0000u)
+
+#define USB_HOST_PIPExBUF               (64u)
+
+#define USB_HOST_D0FIFO                 (0)
+#define USB_HOST_D1FIFO                 (1)
+#define USB_HOST_DMA_READY              (0)
+#define USB_HOST_DMA_BUSY               (1)
+#define USB_HOST_DMA_BUSYEND            (2)
+
+#define USB_HOST_FIFO_USE               (0x7000)
+
+#define USB_HOST_FIFOERROR              (0xffff)
+#define USB_HOST_WRITEEND               (0)
+#define USB_HOST_WRITESHRT              (1)
+#define USB_HOST_WRITING                (2)
+#define USB_HOST_WRITEDMA               (3)
+#define USB_HOST_READEND                (0)
+#define USB_HOST_READSHRT               (1)
+#define USB_HOST_READING                (2)
+#define USB_HOST_READOVER               (3)
+#define USB_HOST_READZERO               (4)
+
+#define USB_HOST_CMD_IDLE               (0x0000)
+#define USB_HOST_CMD_DOING              (0x0001)
+#define USB_HOST_CMD_DONE               (0x0002)
+#define USB_HOST_CMD_NORES              (0x0003)
+#define USB_HOST_CMD_STALL              (0x0004)
+#define USB_HOST_CMD_FIELD              (0x000f)
+
+#if 0
+#define USB_HOST_CHG_CMDFIELD( r, v )   do { r &= ( ~USB_HOST_CMD_FIELD );  \
+                                         r |= v;                } while(0)
+#endif
+
+#define USB_HOST_MODE_WRITE             (0x0100)
+#define USB_HOST_MODE_READ              (0x0200)
+#define USB_HOST_MODE_NO_DATA           (0x0300)
+#define USB_HOST_MODE_FIELD             (0x0f00)
+
+#define USB_HOST_STAGE_SETUP            (0x0010)
+#define USB_HOST_STAGE_DATA             (0x0020)
+#define USB_HOST_STAGE_STATUS           (0x0030)
+#define USB_HOST_STAGE_FIELD            (0x00f0)
+
+#if 0
+#define USB_HOST_CHG_STAGEFIELD( r, v ) do { r &= ( ~USB_HOST_STAGE_FIELD );    \
+                                         r |= v;                } while(0)
+#endif
+
+#define USB_HOST_DEVADD_MASK            (0x7fc0)
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern uint16_t g_usb_host_elt_clockmode;
+
+#endif /* USB_HOST_H */
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/usb_host_version.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,32 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb_host_version.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+
+#define USB_HOST_LOCAL_Rev      "VER080_140709"
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/ohci_wrapp_RZ_A1.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1492 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include <string.h>
+#include "cmsis.h"
+#include "cmsis_os.h"
+#include "ohci_wrapp_RZ_A1.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+#include "rza_io_regrw.h"
+#include "usb_host_setting.h"
+
+/* ------------------ HcControl Register --------------------- */
+#define OR_CONTROL_PLE                  (0x00000004)
+#define OR_CONTROL_IE                   (0x00000008)
+#define OR_CONTROL_CLE                  (0x00000010)
+#define OR_CONTROL_BLE                  (0x00000020)
+/* ----------------- HcCommandStatus Register ----------------- */
+#define OR_CMD_STATUS_HCR               (0x00000001)
+#define OR_CMD_STATUS_CLF               (0x00000002)
+#define OR_CMD_STATUS_BLF               (0x00000004)
+#define OR_CMD_STATUS_OCR               (0x00000008)
+/* --------------- HcInterruptStatus Register ----------------- */
+#define OR_INTR_STATUS_WDH              (0x00000002)
+#define OR_INTR_STATUS_RHSC             (0x00000040)
+/* --------------- HcInterruptEnable Register ----------------- */
+#define OR_INTR_ENABLE_WDH              (0x00000002)
+#define OR_INTR_ENABLE_RHSC             (0x00000040)
+/* -------------- HcRhPortStatus[1:NDP] Register -------------- */
+#define OR_RH_PORT_CSC                  (0x00010000)
+#define OR_RH_PORT_LSDA                 (0x00000200)
+#define OR_RH_PORT_PRS                  (0x00000010)
+#define OR_RH_PORT_POCI                 (0x00000008)
+#define OR_RH_PORT_CCS                  (0x00000001)
+
+#define ED_FORMAT                       (0x00008000)   /* Format */
+#define ED_SKIP                         (0x00004000)   /* Skip this ep in queue */
+#define ED_TOGLE_CARRY                  (0x00000002)
+#define ED_HALTED                       (0x00000001)
+
+#define TD_SETUP                        (0x00000000)   /* Direction of Setup Packet */
+#define TD_OUT                          (0x00080000)   /* Direction Out */
+#define TD_TOGGLE_0                     (0x02000000)   /* Toggle 0 */
+#define TD_TOGGLE_1                     (0x03000000)   /* Toggle 1 */
+
+/* -------------- USB Standard Requests  -------------- */
+#define GET_STATUS                      (0x00)
+#define SET_FEATURE                     (0x03)
+#define SET_ADDRESS                     (0x05)
+
+#define TD_CTL_MSK_DP                   (0x00180000)
+#define TD_CTL_MSK_T                    (0x03000000)
+#define TD_CTL_MSK_CC                   (0xF0000000)
+#define TD_CTL_MSK_EC                   (0x0C000000)
+#define TD_CTL_SHFT_CC                  (28)
+#define TD_CTL_SHFT_EC                  (26)
+#define TD_CTL_SHFT_T                   (24)
+#define ED_SHFT_TOGLE_CARRY             (1)
+#define SIG_GEN_LIST_REQ                (1)
+#if (ISO_TRANS_MAX_NUM > 0)
+#define TD_PSW_MSK_CC                   (0xF000)
+#define TD_PSW_SHFT_CC                  (12)
+#define TD_CTL_MSK_FC                   (0x07000000)
+#define TD_CTL_SHFT_FC                  (24)
+#endif
+
+#define CTL_TRANS_TIMEOUT               (1000)
+#define BLK_TRANS_TIMEOUT               (5)
+#define TOTAL_SEM_NUM                   (5 + (2 * INT_TRANS_MAX_NUM) + (2 * ISO_TRANS_MAX_NUM))
+
+#define PORT_LOW_SPEED                  (0x00000200)
+#define PORT_HIGH_SPEED                 (0x00000400)
+#define PORT_NUM                        (16 + 1) /* num + root(1) */
+
+typedef struct tag_hctd {
+    uint32_t         control;        /* Transfer descriptor control */
+    uint8_t          *currBufPtr;    /* Physical address of current buffer pointer */
+    struct tag_hctd  *nextTD;        /* Physical pointer to next Transfer Descriptor */
+    uint8_t          *bufEnd;        /* Physical address of end of buffer */
+} hctd_t;
+
+#if (ISO_TRANS_MAX_NUM > 0)
+#define PSW_NUM                         (8)
+typedef struct tag_hcisotd {
+    uint32_t           control;      /* Transfer descriptor control */
+    uint8_t            *bufferPage0; /* Buffer Page 0 */
+    struct tag_hcisotd *nextTD;      /* Physical pointer to next Transfer Descriptor */
+    uint8_t            *bufEnd;      /* Physical address of end of buffer */
+    uint16_t           offsetPSW[PSW_NUM]; /* Offset/PSW */
+} hcisotd_t;
+#endif
+
+typedef struct tag_hced {
+    uint32_t         control;        /* Endpoint descriptor control */
+    uint32_t         tailTD;         /* Physical address of tail in Transfer descriptor list */
+    uint32_t         headTD;         /* Physcial address of head in Transfer descriptor list */
+    struct tag_hced  *nextED;        /* Physical address of next Endpoint descriptor */
+} hced_t;
+
+typedef struct tag_hcca {
+    uint32_t         IntTable[32];   /* Interrupt Table */
+    uint32_t         FrameNumber;    /* Frame Number */
+    uint32_t         DoneHead;       /* Done Head */
+    volatile uint8_t Reserved[116];  /* Reserved for future use */
+    volatile uint8_t Unknown[4];     /* Unused */
+} hcca_t;
+
+typedef struct tag_usb_ohci_reg {
+    volatile uint32_t HcRevision;
+    volatile uint32_t HcControl;
+    volatile uint32_t HcCommandStatus;
+    volatile uint32_t HcInterruptStatus;
+    volatile uint32_t HcInterruptEnable;
+    volatile uint32_t HcInterruptDisable;
+    volatile uint32_t HcHCCA;
+    volatile uint32_t HcPeriodCurrentED;
+    volatile uint32_t HcControlHeadED;
+    volatile uint32_t HcControlCurrentED;
+    volatile uint32_t HcBulkHeadED;
+    volatile uint32_t HcBulkCurrentED;
+    volatile uint32_t HcDoneHead;
+    volatile uint32_t HcFmInterval;
+    volatile uint32_t HcFmRemaining;
+    volatile uint32_t HcFmNumber;
+    volatile uint32_t HcPeriodicStart;
+    volatile uint32_t HcLSThreshold;
+    volatile uint32_t HcRhDescriptorA;
+    volatile uint32_t HcRhDescriptorB;
+    volatile uint32_t HcRhStatus;
+    volatile uint32_t HcRhPortStatus1;
+} usb_ohci_reg_t;
+
+typedef struct tag_genelal_ed {
+    osThreadId      tskid;
+    osSemaphoreId   semid_wait;
+    osSemaphoreId   semid_list;
+    void            *p_curr_td;     /* pointer of hctd_t or hcisotd_t */
+    hced_t          *p_curr_ed;
+    uint32_t        pipe_no;
+    uint32_t        trans_wait;
+    uint32_t        cycle_time;
+    uint8_t         *p_start_buf;
+#if (ISO_TRANS_MAX_NUM > 0)
+    uint32_t        psw_idx;
+#endif
+} genelal_ed_t;
+
+typedef struct tag_tdinfo {
+    uint32_t         count;
+    uint32_t         direction;
+    uint32_t         msp;
+    uint16_t         devadr;
+    uint16_t         speed;         /* 1:Speed = Low */
+    uint8_t          endpoint_no;
+} tdinfo_t;
+
+typedef struct tag_split_trans {
+    uint16_t        root_devadr;
+    uint16_t        get_port;
+    uint16_t        port_speed;
+    uint16_t        reset_port;
+    uint32_t        seq_cnt;
+    uint32_t        port_sts_bits[PORT_NUM];
+} split_trans_t;
+
+static void callback_task(void const * argument);
+static void control_ed_task(void const * argument);
+static void bulk_ed_task(void const * argument);
+static void int_ed_task(void const * argument);
+static int32_t int_trans_doing(hced_t *p_ed, uint32_t index);
+static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed);
+static void chk_genelal_td_done(genelal_ed_t *p_g_ed);
+static void chk_split_trans_setting(genelal_ed_t *p_g_ed);
+static void set_split_trans_setting(void);
+static void control_trans(genelal_ed_t *p_g_ed);
+static void bulk_trans(genelal_ed_t *p_g_ed);
+static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
+static uint32_t chk_cycle(hced_t *p_ed);
+static void int_trans(genelal_ed_t *p_g_ed);
+static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info);
+static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed);
+#if (ISO_TRANS_MAX_NUM > 0)
+static void iso_ed_task(void const * argument);
+static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index);
+static void chk_iso_td_done(genelal_ed_t *p_g_ed);
+static int32_t chk_iso_ed(genelal_ed_t *p_g_ed);
+static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
+static void iso_trans(genelal_ed_t *p_g_ed);
+#endif
+static void connect_check(void);
+
+extern USB_HOST_CFG_PIPETBL_t  usb_host_blk_ep_tbl1[];
+extern USB_HOST_CFG_PIPETBL_t  usb_host_int_ep_tbl1[];
+#if (ISO_TRANS_MAX_NUM > 0)
+extern USB_HOST_CFG_PIPETBL_t  usb_host_iso_ep_tbl1[];
+#endif
+
+static usb_ohci_reg_t usb_reg;
+static usb_ohci_reg_t *p_usb_reg     = &usb_reg;
+static usbisr_fnc_t   *p_usbisr_cb   = NULL;
+static osSemaphoreId  semid_cb       = NULL;
+static uint32_t       connect_change = 0xFFFFFFFF;
+static uint32_t       connect_status = 0;
+static uint32_t       init_end       = 0;
+static genelal_ed_t   ctl_ed;
+static genelal_ed_t   blk_ed;
+static genelal_ed_t   int_ed[INT_TRANS_MAX_NUM];
+static split_trans_t  split_ctl;
+
+#if (ISO_TRANS_MAX_NUM > 0)
+static genelal_ed_t   iso_ed[ISO_TRANS_MAX_NUM];
+#endif
+
+osSemaphoreDef(ohciwrapp_sem_01);
+osSemaphoreDef(ohciwrapp_sem_02);
+osSemaphoreDef(ohciwrapp_sem_03);
+osSemaphoreDef(ohciwrapp_sem_04);
+osSemaphoreDef(ohciwrapp_sem_05);
+osSemaphoreDef(ohciwrapp_sem_06);
+osSemaphoreDef(ohciwrapp_sem_07);
+#if (INT_TRANS_MAX_NUM >= 2)
+osSemaphoreDef(ohciwrapp_sem_08);
+osSemaphoreDef(ohciwrapp_sem_09);
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+osSemaphoreDef(ohciwrapp_sem_10);
+osSemaphoreDef(ohciwrapp_sem_11);
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+osSemaphoreDef(ohciwrapp_sem_12);
+osSemaphoreDef(ohciwrapp_sem_13);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 1)
+osSemaphoreDef(ohciwrapp_sem_14);
+osSemaphoreDef(ohciwrapp_sem_15);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+osSemaphoreDef(ohciwrapp_sem_16);
+osSemaphoreDef(ohciwrapp_sem_17);
+#endif
+
+osThreadDef(callback_task,   osPriorityHigh,        512);
+osThreadDef(control_ed_task, osPriorityNormal,      512);
+osThreadDef(bulk_ed_task,    osPriorityNormal,      512);
+static void int_ed_task_1(void const * argument) {
+    int_ed_task(argument);
+}
+osThreadDef(int_ed_task_1,   osPriorityNormal,      512);
+#if (INT_TRANS_MAX_NUM >= 2)
+static void int_ed_task_2(void const * argument) {
+    int_ed_task(argument);
+}
+osThreadDef(int_ed_task_2,   osPriorityNormal,      512);
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+static void int_ed_task_3(void const * argument) {
+    int_ed_task(argument);
+}
+osThreadDef(int_ed_task_3,   osPriorityNormal,      512);
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+static void int_ed_task_4(void const * argument) {
+    int_ed_task(argument);
+}
+osThreadDef(int_ed_task_4,   osPriorityNormal,      512);
+#endif
+
+#if (ISO_TRANS_MAX_NUM >= 1)
+static void iso_ed_task_1(void const * argument) {
+    iso_ed_task(argument);
+}
+osThreadDef(iso_ed_task_1,   osPriorityAboveNormal, 512);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+static void iso_ed_task_2(void const * argument) {
+    iso_ed_task(argument);
+}
+osThreadDef(iso_ed_task_2,   osPriorityAboveNormal, 512);
+#endif
+
+void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc) {
+    static const osSemaphoreDef_t * const sem_def_tbl[TOTAL_SEM_NUM] = {
+        osSemaphore(ohciwrapp_sem_01), osSemaphore(ohciwrapp_sem_02), osSemaphore(ohciwrapp_sem_03)
+      , osSemaphore(ohciwrapp_sem_04), osSemaphore(ohciwrapp_sem_05), osSemaphore(ohciwrapp_sem_06)
+      , osSemaphore(ohciwrapp_sem_07)
+#if (INT_TRANS_MAX_NUM >= 2)
+      , osSemaphore(ohciwrapp_sem_08), osSemaphore(ohciwrapp_sem_09)
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+      , osSemaphore(ohciwrapp_sem_10), osSemaphore(ohciwrapp_sem_11)
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+      , osSemaphore(ohciwrapp_sem_12), osSemaphore(ohciwrapp_sem_13)
+#endif
+#if (ISO_TRANS_MAX_NUM >= 1)
+      , osSemaphore(ohciwrapp_sem_14), osSemaphore(ohciwrapp_sem_15)
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+      , osSemaphore(ohciwrapp_sem_16), osSemaphore(ohciwrapp_sem_17)
+#endif
+    };
+    static const osThreadDef_t * const int_tsk_def_tbl[INT_TRANS_MAX_NUM] = {
+        osThread(int_ed_task_1)
+#if (INT_TRANS_MAX_NUM >= 2)
+      , osThread(int_ed_task_2)
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+      , osThread(int_ed_task_3)
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+      , osThread(int_ed_task_4)
+#endif
+    };
+#if (ISO_TRANS_MAX_NUM > 0)
+    static const osThreadDef_t * const iso_tsk_def_tbl[ISO_TRANS_MAX_NUM] = {
+        osThread(iso_ed_task_1)
+#if (ISO_TRANS_MAX_NUM >= 2)
+      , osThread(iso_ed_task_2)
+#endif
+    };
+#endif
+
+    uint32_t cnt;
+    uint32_t index = 0;
+
+    /* Disables interrupt for usb */
+    GIC_DisableIRQ(USBIXUSBIX);
+
+#if (USB_HOST_CH == 0)
+    /* P4_1(USB0_EN) */
+    GPIOP4      &= ~0x0002;         /* Outputs low level */
+    GPIOPMC4    &= ~0x0002;         /* Port mode */
+    GPIOPM4     &= ~0x0002;         /* Output mode */
+#endif
+
+    p_usbisr_cb = p_usbisr_fnc;
+#if (USB_HOST_HISPEED == 0)
+    g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_FULL_SPEED;
+#else
+    g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_HIGH_SPEED;
+#endif
+    p_usb_reg->HcRevision         = 0x00000010;
+    p_usb_reg->HcControl          = 0x00000000;
+    p_usb_reg->HcCommandStatus    = 0x00000000;
+    p_usb_reg->HcInterruptStatus  = 0x00000000;
+    p_usb_reg->HcInterruptEnable  = 0x00000000;
+    p_usb_reg->HcInterruptDisable = 0x00000000;
+    p_usb_reg->HcHCCA             = 0x00000000;
+    p_usb_reg->HcPeriodCurrentED  = 0x00000000;
+    p_usb_reg->HcControlHeadED    = 0x00000000;
+    p_usb_reg->HcControlCurrentED = 0x00000000;
+    p_usb_reg->HcBulkHeadED       = 0x00000000;
+    p_usb_reg->HcBulkCurrentED    = 0x00000000;
+    p_usb_reg->HcDoneHead         = 0x00000000;
+    p_usb_reg->HcFmInterval       = 0x00002EDF;
+    p_usb_reg->HcFmRemaining      = 0x00002EDF;
+    p_usb_reg->HcFmNumber         = 0x00000000;
+    p_usb_reg->HcPeriodicStart    = 0x00000000;
+    p_usb_reg->HcLSThreshold      = 0x00000628;
+    p_usb_reg->HcRhDescriptorA    = 0xFF000901;
+    p_usb_reg->HcRhDescriptorB    = 0x00020000;
+    p_usb_reg->HcRhStatus         = 0x00000000;
+    p_usb_reg->HcRhPortStatus1    = 0x00000000;
+
+#if (USB_HOST_CH == 0)
+    GPIOP4      |=  0x0002;         /* P4_1 Outputs high level */
+    osDelay(5);
+    GPIOP4      &= ~0x0002;         /* P4_1 Outputs low level */
+    osDelay(10);
+#else
+    osDelay(15);
+#endif
+
+    if (init_end == 0) {
+        (void)memset(&ctl_ed, 0, sizeof(ctl_ed));
+        (void)memset(&blk_ed, 0, sizeof(blk_ed));
+        (void)memset(&int_ed[0], 0, sizeof(int_ed));
+#if (ISO_TRANS_MAX_NUM > 0)
+        (void)memset(&iso_ed[0], 0, sizeof(iso_ed));
+#endif
+
+        /* callback */
+        semid_cb = osSemaphoreCreate(sem_def_tbl[index], 0);
+        index++;
+        (void)osThreadCreate(osThread(callback_task), 0);
+
+        /* control transfer */
+        ctl_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+        index++;
+        ctl_ed.semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+        index++;
+        ctl_ed.tskid = osThreadCreate(osThread(control_ed_task), 0);
+
+        /* bulk transfer */
+        blk_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+        index++;
+        blk_ed.semid_list =  osSemaphoreCreate(sem_def_tbl[index], 0);
+        index++;
+        blk_ed.tskid = osThreadCreate(osThread(bulk_ed_task), 0);
+
+        /* interrupt transfer */
+        for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+            int_ed[cnt].semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+            index++;
+            int_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+            index++;
+            int_ed[cnt].tskid = osThreadCreate(int_tsk_def_tbl[cnt], (void *)cnt);
+        }
+
+#if (ISO_TRANS_MAX_NUM > 0)
+        /* isochronous transfer */
+        for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+            iso_ed[cnt].semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+            index++;
+            iso_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+            index++;
+            iso_ed[cnt].tskid = osThreadCreate(iso_tsk_def_tbl[cnt], (void *)cnt);
+        }
+#endif
+        init_end = 1;
+    }
+}
+
+uint32_t ohciwrapp_reg_r(uint32_t reg_ofs) {
+    if (init_end == 0) {
+        return 0;
+    }
+
+    return *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs);
+}
+
+void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data) {
+    uint32_t cnt;
+    uint32_t last_data;
+    hcca_t   *p_hcca;
+
+    if (init_end == 0) {
+        return;
+    }
+
+    switch (reg_ofs) {
+        case OHCI_REG_CONTROL:
+            last_data            = p_usb_reg->HcControl;
+            p_usb_reg->HcControl = (set_data & 0x000007FF);
+            if ((last_data & OR_CONTROL_CLE) != (set_data & OR_CONTROL_CLE)) {
+                /* change CLE */
+                if ((set_data & OR_CONTROL_CLE) != 0) {
+                    (void)osSemaphoreRelease(ctl_ed.semid_list);
+                } else {
+                    if (ctl_ed.trans_wait == 1) {
+                        ctl_ed.trans_wait = 0;
+                        (void)osSemaphoreRelease(ctl_ed.semid_wait);
+                    }
+                    (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever);
+                }
+            }
+            if ((last_data & OR_CONTROL_BLE) != (set_data & OR_CONTROL_BLE)) {
+                /* change BLE */
+                if ((set_data & OR_CONTROL_BLE) != 0) {
+                    (void)osSemaphoreRelease(blk_ed.semid_list);
+                } else {
+                    if (blk_ed.trans_wait == 1) {
+                        blk_ed.trans_wait = 0;
+                        (void)osSemaphoreRelease(blk_ed.semid_wait);
+                    }
+                    (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever);
+                }
+            }
+#if (ISO_TRANS_MAX_NUM > 0)
+            if ((last_data & OR_CONTROL_IE) != (set_data & OR_CONTROL_IE)) {
+                /* change IE */
+                for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+                    if ((set_data & OR_CONTROL_IE) != 0) {
+                        (void)osSemaphoreRelease(iso_ed[cnt].semid_list);
+                    } else {
+                        if (iso_ed[cnt].trans_wait == 1) {
+                            iso_ed[cnt].trans_wait = 0;
+                            (void)osSemaphoreRelease(iso_ed[cnt].semid_wait);
+                        }
+                        (void)osSemaphoreWait(iso_ed[cnt].semid_list, osWaitForever);
+                    }
+                }
+            }
+#endif
+            if ((last_data & OR_CONTROL_PLE) != (set_data & OR_CONTROL_PLE)) {
+                /* change PLE */
+                for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+                    if ((set_data & OR_CONTROL_PLE) != 0) {
+                        (void)osSemaphoreRelease(int_ed[cnt].semid_list);
+                    } else {
+                        if (int_ed[cnt].trans_wait == 1) {
+                            int_ed[cnt].trans_wait = 0;
+                            (void)osSemaphoreRelease(int_ed[cnt].semid_wait);
+                        }
+                        (void)osSemaphoreWait(int_ed[cnt].semid_list, osWaitForever);
+                    }
+                }
+            }
+            break;
+        case OHCI_REG_COMMANDSTATUS:
+            if ((set_data & OR_CMD_STATUS_HCR) != 0) {    /* HostController Reset */
+                p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_HCR;
+                if (usbx_api_host_init(16, g_usbx_host_SupportUsbDeviceSpeed, USBHCLOCK_X1_48MHZ) == USB_HOST_ATTACH) {
+                    ohciwrapp_loc_Connect(1);
+                }
+                p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_HCR;
+            }
+            if ((set_data & OR_CMD_STATUS_CLF) != 0) {
+                p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
+                osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
+            }
+            if ((set_data & OR_CMD_STATUS_BLF) != 0) {
+                p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
+                osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
+            }
+            if ((set_data & OR_CMD_STATUS_OCR) != 0) {
+                p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_OCR;
+            } else {
+                p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_OCR;
+            }
+            break;
+        case OHCI_REG_INTERRUPTSTATUS:
+            if (((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) != 0)
+             && ((set_data & OR_INTR_STATUS_WDH) != 0)) {
+                if (p_usb_reg->HcDoneHead != 0x00000000) {
+                    p_hcca                       =  (hcca_t *)p_usb_reg->HcHCCA;
+                    p_hcca->DoneHead             =  p_usb_reg->HcDoneHead;
+                    p_usb_reg->HcDoneHead        =  0x00000000;
+                    p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+                    (void)osSemaphoreRelease(semid_cb);
+                } else {
+                    p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_WDH;
+                }
+            }
+            if ((set_data & OR_INTR_STATUS_RHSC) != 0) {
+                p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_RHSC;
+            }
+            break;
+        case OHCI_REG_INTERRUPTENABLE:
+        case OHCI_REG_INTERRUPTDISABLE:
+        case OHCI_REG_HCCA:
+        case OHCI_REG_CONTROLHEADED:
+        case OHCI_REG_CONTROLCURRENTED:
+        case OHCI_REG_BULKHEADED:
+        case OHCI_REG_BULKCURRENTED:
+        case OHCI_REG_FMINTERVAL:
+        case OHCI_REG_FMREMAINING:
+        case OHCI_REG_PERIODICSTART:
+        case OHCI_REG_LSTHRESHOLD:
+        case OHCI_REG_RHDESCRIPTORA:
+        case OHCI_REG_RHDESCRIPTORB:
+        case OHCI_REG_RHSTATUS:
+            *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs) = set_data;
+            break;
+        case OHCI_REG_RHPORTSTATUS1:
+            p_usb_reg->HcRhPortStatus1 &= ~(set_data & 0xFFFF0000);
+            if ((set_data & OR_RH_PORT_PRS) != 0) {    /* Set Port Reset */
+                p_usb_reg->HcRhPortStatus1 |= OR_RH_PORT_PRS;
+                usbx_host_UsbBusReset();
+                p_usb_reg->HcRhPortStatus1 &= ~OR_RH_PORT_PRS;
+            }
+            break;
+        case OHCI_REG_REVISION:
+        case OHCI_REG_PERIODCURRENTED:
+        case OHCI_REG_DONEHEADED:
+        case OHCI_REG_FMNUMBER:
+        default:
+            /* Do Nothing */
+            break;
+    }
+}
+
+static void callback_task(void const * argument) {
+    usbisr_fnc_t *p_wk_cb = p_usbisr_cb;
+
+    if (p_wk_cb == NULL) {
+        return;
+    }
+
+    while (1) {
+        osSemaphoreWait(semid_cb, osWaitForever);
+        if (connect_change != 0xFFFFFFFF) {
+            connect_change = 0xFFFFFFFF;
+            connect_check();
+        }
+        p_wk_cb();
+    }
+}
+
+static void control_ed_task(void const * argument) {
+    while (1) {
+        osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
+        (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever);
+        while ((p_usb_reg->HcControl & OR_CONTROL_CLE) != 0) {
+            if ((p_usb_reg->HcControlCurrentED == 0)
+             && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0)) {
+                p_usb_reg->HcControlCurrentED =  p_usb_reg->HcControlHeadED;
+                p_usb_reg->HcCommandStatus    &= ~OR_CMD_STATUS_CLF;
+            }
+            if (p_usb_reg->HcControlCurrentED != 0) {
+                ctl_ed.p_curr_ed = (hced_t *)p_usb_reg->HcControlCurrentED;
+                if (chk_genelal_ed(&ctl_ed) != 0) {
+                    control_trans(&ctl_ed);
+                    p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
+                }
+                p_usb_reg->HcControlCurrentED = (uint32_t)ctl_ed.p_curr_ed->nextED;
+            } else {
+                break;
+            }
+        }
+        if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0) {
+            osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
+        }
+        (void)osSemaphoreRelease(ctl_ed.semid_list);
+    }
+}
+
+static void bulk_ed_task(void const * argument) {
+    while (1) {
+        osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
+        (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever);
+        while ((p_usb_reg->HcControl & OR_CONTROL_BLE) != 0) {
+            if ((p_usb_reg->HcBulkCurrentED == 0)
+             && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0)) {
+                p_usb_reg->HcBulkCurrentED =  p_usb_reg->HcBulkHeadED;
+                p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_BLF;
+            }
+            if (p_usb_reg->HcBulkCurrentED != 0) {
+                blk_ed.p_curr_ed = (hced_t *)p_usb_reg->HcBulkCurrentED;
+                if (chk_genelal_ed(&blk_ed) != 0) {
+                    bulk_trans(&blk_ed);
+                    p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
+                }
+                p_usb_reg->HcBulkCurrentED = (uint32_t)blk_ed.p_curr_ed->nextED;
+            } else {
+                break;
+            }
+        }
+        if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0) {
+            osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
+        }
+        (void)osSemaphoreRelease(blk_ed.semid_list);
+    }
+}
+
+static void int_ed_task(void const * argument) {
+    genelal_ed_t *p_int_ed = &int_ed[(uint32_t)argument];
+    uint32_t     cnt;
+    uint32_t     wait_cnt = 0;
+    hcca_t       *p_hcca;
+    hced_t       *p_ed;
+
+    while (1) {
+        (void)osSemaphoreWait(p_int_ed->semid_list, osWaitForever);
+        if (p_int_ed->p_curr_ed == NULL) {
+            for (cnt = 0; (cnt < 32) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
+                                                 && (p_int_ed->p_curr_ed == NULL); cnt++) {
+                p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+                p_ed   = (hced_t *)p_hcca->IntTable[cnt];
+                while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
+                                                        && (p_int_ed->p_curr_ed == NULL)) {
+                    if (int_trans_doing(p_ed, (uint32_t)argument) == 0) {
+                        p_int_ed->p_curr_ed = p_ed;
+                        if (chk_genelal_ed(p_int_ed) != 0) {
+                            int_trans_setting(p_int_ed, (uint32_t)argument);
+                        } else {
+                            p_int_ed->p_curr_ed = NULL;
+                        }
+                    }
+                    p_ed = p_ed->nextED;
+                }
+            }
+        }
+        if (p_int_ed->p_curr_ed != NULL) {
+            while ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0) {
+                if (chk_genelal_ed(p_int_ed) != 0) {
+                    int_trans(p_int_ed);
+                    (void)osSemaphoreWait(p_int_ed->semid_wait, osWaitForever);
+                    usbx_host_stop_transfer(p_int_ed->pipe_no);
+                    wait_cnt = p_int_ed->cycle_time;
+                } else {
+                    if (wait_cnt > 0) {
+                        wait_cnt--;
+                    } else {
+                        p_int_ed->p_curr_ed = NULL;
+                    }
+                    break;
+                }
+            }
+        }
+        (void)osSemaphoreRelease(p_int_ed->semid_list);
+        if (p_int_ed->p_curr_ed == NULL) {
+            osDelay(10);
+        } else {
+            osDelay(1);
+        }
+    }
+}
+
+static int32_t int_trans_doing(hced_t *p_ed, uint32_t index) {
+    uint32_t cnt;
+    int32_t  ret = 0;
+
+    for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+        if ((index != cnt) && (int_ed[cnt].p_curr_ed == p_ed)) {
+            ret = 1;
+        }
+    }
+
+    return ret;
+}
+
+static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed){
+    int32_t ret   = 0;
+    hced_t  *p_ed = p_g_ed->p_curr_ed;
+
+    if (((p_ed->control & ED_SKIP)   != 0)
+     || ((p_ed->control & ED_FORMAT) != 0)
+     || ((p_ed->headTD & ED_HALTED)  != 0)
+     || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) {
+        /* Do Nothing */
+    } else if ((p_ed->control & 0x0000007F) > 10) {
+        p_ed->headTD |= ED_HALTED;
+    } else {
+        p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0);
+        if (p_g_ed->p_curr_td == NULL) {
+            p_ed->headTD |= ED_HALTED;
+        } else {
+            hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+            p_g_ed->p_start_buf = p_td->currBufPtr;
+            ret = 1;
+        }
+    }
+
+    return ret;
+}
+
+static void chk_genelal_td_done(genelal_ed_t *p_g_ed) {
+    hcca_t   *p_hcca;
+    hctd_t   *p_td = (hctd_t *)p_g_ed->p_curr_td;
+    uint32_t ConditionCode = RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+    if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) {
+        p_g_ed->p_curr_ed->headTD = ((uint32_t)p_td->nextTD & 0xFFFFFFF0)
+                                  | (p_g_ed->p_curr_ed->headTD & 0x0000000F);
+        p_td->nextTD              = (hctd_t *)p_usb_reg->HcDoneHead;
+        p_usb_reg->HcDoneHead     = (uint32_t)p_g_ed->p_curr_td;
+        if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) {
+            p_hcca                       =  (hcca_t *)p_usb_reg->HcHCCA;
+            p_hcca->DoneHead             =  p_usb_reg->HcDoneHead;
+            p_usb_reg->HcDoneHead        =  0x00000000;
+            p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+            (void)osSemaphoreRelease(semid_cb);
+        }
+    }
+}
+
+static void chk_split_trans_setting(genelal_ed_t *p_g_ed) {
+    uint8_t   *p_buf;
+    tdinfo_t  td_info;
+    hctd_t    *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+    /* Hi-Speed mode only */
+    if (g_usbx_host_UsbDeviceSpeed != USB_HOST_HIGH_SPEED) {
+        return;
+    }
+
+    if (RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC) != TD_CC_NOERROR) {
+        return;
+    }
+
+    get_td_info(p_g_ed, &td_info);
+    p_buf = p_g_ed->p_start_buf;
+
+    if (td_info.direction == 0) {
+        uint8_t  bRequest = p_buf[1];
+        uint16_t wValue   = (p_buf[3] << 8) + p_buf[2];
+        uint16_t wIndx    = (p_buf[5] << 8) + p_buf[4];
+        uint16_t devadd;
+
+        if ((td_info.devadr == 0) && (bRequest == SET_ADDRESS)) {
+            /* SET_ADDRESS */
+            usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+            usbx_host_set_devadd(wValue, &devadd);
+            if (split_ctl.root_devadr == 0) {
+                split_ctl.root_devadr = wValue; /* New Address */
+            }
+        } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == SET_FEATURE)
+                && (wValue == 0x0004) && (split_ctl.root_devadr != 0)) {
+            /* SET_FEATURE PORT_RESET */
+            split_ctl.reset_port = (wIndx & 0x00FF);
+        } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == GET_STATUS)) {
+            /* GET_STATUS */
+            split_ctl.get_port = wIndx;
+            split_ctl.seq_cnt = 1;
+        } else {
+            /* Do Nothing */
+        }
+    } else if (td_info.direction == 2) {
+        if ((td_info.devadr == split_ctl.root_devadr) && (split_ctl.seq_cnt == 1)) {
+            if (split_ctl.get_port < PORT_NUM) {
+                split_ctl.port_sts_bits[split_ctl.get_port] = (p_buf[1] << 8) + p_buf[0];
+            }
+            split_ctl.seq_cnt = 0;
+        }
+    } else {
+        /* Do Nothing */
+    }
+}
+
+static void set_split_trans_setting(void) {
+    uint16_t port_speed;
+    uint16_t devadd;
+
+    if ((split_ctl.root_devadr != 0) && (split_ctl.reset_port != 0) && (split_ctl.reset_port < PORT_NUM)) {
+        usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+        RZA_IO_RegWrite_16(&devadd, split_ctl.root_devadr, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
+        RZA_IO_RegWrite_16(&devadd, split_ctl.reset_port, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
+        if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_HIGH_SPEED) != 0) {
+            port_speed = USB_HOST_HIGH_SPEED;
+        } else if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_LOW_SPEED) != 0) {
+            port_speed = USB_HOST_LOW_SPEED;
+        } else {
+            port_speed = USB_HOST_FULL_SPEED;
+        }
+        RZA_IO_RegWrite_16(&devadd, port_speed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+        usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
+        split_ctl.reset_port = 0;
+    }
+}
+
+static void control_trans(genelal_ed_t *p_g_ed) {
+    hctd_t   *p_td = (hctd_t *)p_g_ed->p_curr_td;
+    tdinfo_t td_info;
+    uint16_t devadd;
+
+    get_td_info(p_g_ed, &td_info);
+
+    if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+        if (td_info.devadr == 0) {
+            set_split_trans_setting();
+        }
+    } else {
+        /* When a non-Hi-Speed, the communication speed is determined from the TD. */
+        usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+        if (td_info.speed == 1) {
+            RZA_IO_RegWrite_16(&devadd, USB_HOST_LOW_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+        } else {
+            RZA_IO_RegWrite_16(&devadd, USB_HOST_FULL_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+        }
+        usbx_host_set_devadd(td_info.devadr, &devadd);
+    }
+
+    USB20X.DCPMAXP  = (td_info.devadr << 12) + td_info.msp;
+    if (td_info.direction == 0) {
+        g_usbx_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+    } else  if (td_info.count != 0) {
+        g_usbx_host_CmdStage = (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE);
+    } else {
+        g_usbx_host_CmdStage = (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE);
+    }
+    g_usbx_host_pipe_status[USB_HOST_PIPE0]  = USB_HOST_PIPE_WAIT;
+    p_g_ed->pipe_no    = USB_HOST_PIPE0;
+
+    p_g_ed->trans_wait = 1;
+    if (connect_status == 0) {
+        ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
+    } else {
+        if (td_info.direction == 0) {
+            uint16_t Req  = (p_td->currBufPtr[1] << 8) + p_td->currBufPtr[0];
+            uint16_t Val  = (p_td->currBufPtr[3] << 8) + p_td->currBufPtr[2];
+            uint16_t Indx = (p_td->currBufPtr[5] << 8) + p_td->currBufPtr[4];
+            uint16_t Len  = (p_td->currBufPtr[7] << 8) + p_td->currBufPtr[6];
+
+            g_usbx_host_data_pointer[USB_HOST_PIPE0] = p_td->bufEnd;
+            usbx_host_SetupStage(Req, Val, Indx, Len);
+        } else if (td_info.direction == 1) {
+            usbx_host_CtrlWriteStart(td_info.count, p_td->currBufPtr);
+        } else {
+            usbx_host_CtrlReadStart(td_info.count, p_td->currBufPtr);
+        }
+
+        (void)osSemaphoreWait(p_g_ed->semid_wait, CTL_TRANS_TIMEOUT);
+        if (p_g_ed->trans_wait == 1) {
+            p_g_ed->trans_wait = 0;
+            RZA_IO_RegWrite_32(&p_td->control, TD_CC_DEVICENOTRESPONDING, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+        }
+    }
+
+    g_usbx_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usbx_host_CmdStage |= USB_HOST_CMD_IDLE;
+    g_usbx_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+}
+
+static void bulk_trans(genelal_ed_t *p_g_ed) {
+    hctd_t                 *p_td = (hctd_t *)p_g_ed->p_curr_td;
+    hced_t                 *p_ed = p_g_ed->p_curr_ed;
+    tdinfo_t               td_info;
+    USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_blk_ep_tbl1[0];
+    uint8_t                wk_table[6];
+
+    get_td_info(p_g_ed, &td_info);
+
+    wk_table[0] = 0;
+    wk_table[1] = USB_HOST_ENDPOINT_DESC;
+    wk_table[2] = td_info.endpoint_no;
+    if (td_info.direction == 2) {
+        wk_table[2] |= USB_HOST_EP_IN;
+    }
+    wk_table[3] = USB_HOST_EP_BULK;
+    wk_table[4] = (uint8_t)td_info.msp;
+    wk_table[5] = (uint8_t)(td_info.msp >> 8);
+    p_g_ed->pipe_no    = user_table->pipe_number;
+    usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+
+    set_togle(p_g_ed->pipe_no, p_td, p_ed);
+
+    p_g_ed->trans_wait = 1;
+    if (connect_status == 0) {
+        ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
+    } else {
+        if (td_info.direction == 1) {
+            usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+        } else {
+            usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+        }
+
+        (void)osSemaphoreWait(p_g_ed->semid_wait, BLK_TRANS_TIMEOUT);
+        usbx_host_stop_transfer(p_g_ed->pipe_no);
+    }
+}
+
+static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
+    hctd_t                 *p_td = (hctd_t *)p_g_ed->p_curr_td;
+    hced_t                 *p_ed = p_g_ed->p_curr_ed;
+    tdinfo_t               td_info;
+    USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_int_ep_tbl1[index];
+    uint8_t                wk_table[6];
+    uint32_t               cycle_time;
+    uint16_t               devadd;
+
+    get_td_info(p_g_ed, &td_info);
+
+    wk_table[0] = 0;
+    wk_table[1] = USB_HOST_ENDPOINT_DESC;
+    wk_table[2] = td_info.endpoint_no;
+    if (td_info.direction == 2) {
+        wk_table[2] |= USB_HOST_EP_IN;
+    }
+    wk_table[3] = USB_HOST_EP_INT;
+    wk_table[4] = (uint8_t)td_info.msp;
+    wk_table[5] = (uint8_t)(td_info.msp >> 8);
+    cycle_time  = chk_cycle(p_ed);
+    p_g_ed->cycle_time = cycle_time;
+    user_table->pipe_cycle = 0;
+    while (cycle_time > 1) {
+        cycle_time >>= 1;
+        user_table->pipe_cycle++;
+    }
+    if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+        usbx_host_get_devadd(td_info.devadr, &devadd);
+        if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) {
+            user_table->pipe_cycle += 3;
+            if (user_table->pipe_cycle > 7) {
+                user_table->pipe_cycle = 7;
+            }
+        }
+    }
+
+    p_g_ed->pipe_no    = user_table->pipe_number;
+    usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+
+    set_togle(p_g_ed->pipe_no, p_td, p_ed);
+}
+
+static uint32_t chk_cycle(hced_t *p_ed) {
+    uint32_t     cnt;
+    uint32_t     hit_cnt    = 0;
+    uint32_t     cycle_time = 1;
+    hcca_t       *p_hcca;
+    hced_t       *p_wk_ed;
+
+    p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+
+    for (cnt = 0; cnt < 32; cnt++) {
+        p_wk_ed = (hced_t *)p_hcca->IntTable[cnt];
+        while (p_wk_ed != NULL) {
+            if (p_wk_ed == p_ed) {
+                hit_cnt++;
+                break;
+            }
+            p_wk_ed = p_wk_ed->nextED;
+        }
+    }
+    if (hit_cnt < 2) {
+        cycle_time = 32;
+    } else if (hit_cnt < 4) {
+        cycle_time = 16;
+    } else if (hit_cnt < 8) {
+        cycle_time = 8;
+    } else if (hit_cnt < 16) {
+        cycle_time = 4;
+    } else if (hit_cnt < 32) {
+        cycle_time = 2;
+    } else{
+        cycle_time = 1;
+    }
+
+    return cycle_time;
+}
+
+static void int_trans(genelal_ed_t *p_g_ed) {
+    hctd_t   *p_td = (hctd_t *)p_g_ed->p_curr_td;
+    tdinfo_t td_info;
+
+    get_td_info(p_g_ed, &td_info);
+    p_g_ed->trans_wait = 1;
+    if (connect_status == 0) {
+        ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
+    } else {
+        if (td_info.direction == 1) {
+            usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+        } else {
+            usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+        }
+    }
+}
+
+static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info) {
+    hced_t *p_ed = p_g_ed->p_curr_ed;
+
+    p_td_info->endpoint_no = (uint8_t)((p_ed->control >> 7) & 0x0000000F);
+    p_td_info->msp         = (p_ed->control >> 16) & 0x000007FF;
+    p_td_info->devadr      = p_ed->control & 0x0000000F;
+    p_td_info->speed       = (p_ed->control >> 13) & 0x00000001;
+    p_td_info->direction   = (p_ed->control >> 11) & 0x00000003;
+
+    if ((p_ed->control & ED_FORMAT) == 0) {
+        hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+        if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) {
+            if ((p_td->control & TD_CTL_MSK_DP) == TD_SETUP) {
+                p_td_info->direction = 0;
+            } else if ((p_td->control & TD_CTL_MSK_DP) == TD_OUT) {
+                p_td_info->direction = 1;
+            } else {
+                p_td_info->direction = 2;
+            }
+        }
+        if (p_td->currBufPtr != NULL) {
+            p_td_info->count = (uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1;
+        } else {
+            p_td_info->count     = 0;
+        }
+    } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+        hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+
+        if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) {
+            if ((p_isotd->control & TD_CTL_MSK_DP) == TD_SETUP) {
+                p_td_info->direction = 0;
+            } else if ((p_isotd->control & TD_CTL_MSK_DP) == TD_OUT) {
+                p_td_info->direction = 1;
+            } else {
+                p_td_info->direction = 2;
+            }
+        }
+#endif
+    }
+}
+
+static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed) {
+    if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_0) {
+        usbx_host_set_sqclr(pipe);
+    } else if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_1) {
+        usbx_host_set_sqset(pipe);
+    } else if ((p_ed->headTD & ED_TOGLE_CARRY) == 0) {
+        usbx_host_set_sqclr(pipe);
+    } else {
+        usbx_host_set_sqset(pipe);
+    }
+}
+
+#if (ISO_TRANS_MAX_NUM > 0)
+static void iso_ed_task(void const * argument) {
+    genelal_ed_t *p_iso_ed = &iso_ed[(uint32_t)argument];
+    uint32_t     wait_cnt = 0;
+    hcca_t       *p_hcca;
+    hced_t       *p_ed;
+
+    while (1) {
+        (void)osSemaphoreWait(p_iso_ed->semid_list, osWaitForever);
+        if (p_iso_ed->p_curr_ed == NULL) {
+            p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+            p_ed   = (hced_t *)p_hcca->IntTable[0];
+            while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0)
+                                                    && (p_iso_ed->p_curr_ed == NULL)) {
+                if (iso_trans_doing(p_ed, (uint32_t)argument) == 0) {
+                    p_iso_ed->p_curr_ed = p_ed;
+                    if (chk_iso_ed(p_iso_ed) != 0) {
+                        iso_trans_setting(p_iso_ed, (uint32_t)argument);
+                    } else {
+                        p_iso_ed->p_curr_ed = NULL;
+                    }
+                }
+                p_ed = p_ed->nextED;
+            }
+            p_iso_ed->psw_idx = 0;
+        }
+        if (p_iso_ed->p_curr_ed != NULL) {
+            while ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0) {
+                if (chk_iso_ed(p_iso_ed) != 0) {
+                    hcisotd_t *p_isotd = (hcisotd_t *)p_iso_ed->p_curr_td;
+                    uint32_t  starting_frame = p_isotd->control & 0x0000FFFF;
+                    uint32_t  wait_time = 0;
+                    uint32_t  wk_HcFmNumber = p_usb_reg->HcFmNumber;
+
+                    if (starting_frame > wk_HcFmNumber) {
+                        wait_time = starting_frame - wk_HcFmNumber;
+                    } else {
+                        wait_time = (0xFFFF - wk_HcFmNumber) + starting_frame;
+                    }
+                    if ((wait_time >= 2) && (wait_time <= 1000)) {
+                        for (int cnt = 0; cnt < (wait_time - 1); cnt++) {
+                            osDelay(1);
+                            p_usb_reg->HcFmNumber = (wk_HcFmNumber + cnt) & 0x0000FFFF;
+                        }
+                    }
+                    p_iso_ed->psw_idx   = 0;
+                    iso_trans(p_iso_ed);
+                    (void)osSemaphoreWait(p_iso_ed->semid_wait, osWaitForever);
+                    wait_cnt = 8;
+                } else {
+                    if (wait_cnt > 0) {
+                        wait_cnt--;
+                    } else {
+                        p_iso_ed->p_curr_ed = NULL;
+                    }
+                    break;
+                }
+            }
+        }
+        (void)osSemaphoreRelease(p_iso_ed->semid_list);
+        if (p_iso_ed->p_curr_ed == NULL) {
+            osDelay(10);
+        } else {
+            osDelay(1);
+        }
+    }
+}
+
+static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index) {
+    uint32_t cnt;
+    int32_t  ret = 0;
+
+    for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+        if ((index != cnt) && (iso_ed[cnt].p_curr_ed == p_ed)) {
+            ret = 1;
+        }
+    }
+
+    return ret;
+}
+
+static void chk_iso_td_done(genelal_ed_t *p_g_ed) {
+    hcca_t    *p_hcca;
+    hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+    uint32_t  ConditionCode = RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+    if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) {
+        p_g_ed->p_curr_ed->headTD = ((uint32_t)p_isotd->nextTD & 0xFFFFFFF0)
+                                  | (p_g_ed->p_curr_ed->headTD & 0x0000000F);
+        p_isotd->nextTD           = (hcisotd_t *)p_usb_reg->HcDoneHead;
+        p_usb_reg->HcDoneHead     = (uint32_t)p_g_ed->p_curr_td;
+        if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) {
+            p_hcca                       =  (hcca_t *)p_usb_reg->HcHCCA;
+            p_hcca->DoneHead             =  p_usb_reg->HcDoneHead;
+            p_usb_reg->HcDoneHead        =  0x00000000;
+            p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+            (void)osSemaphoreRelease(semid_cb);
+        }
+    }
+}
+
+static int32_t chk_iso_ed(genelal_ed_t *p_g_ed){
+    int32_t ret   = 0;
+    hced_t  *p_ed = p_g_ed->p_curr_ed;
+
+    if (((p_ed->control & ED_SKIP)   != 0)
+     || ((p_ed->control & ED_FORMAT) == 0)
+     || ((p_ed->headTD & ED_HALTED)  != 0)
+     || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) {
+        /* Do Nothing */
+    } else if ((p_ed->control & 0x0000007F) > 10) {
+        p_ed->headTD |= ED_HALTED;
+    } else {
+        p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0);
+        if (p_g_ed->p_curr_td == NULL) {
+            p_ed->headTD |= ED_HALTED;
+        } else {
+            hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+
+            p_g_ed->p_start_buf = p_isotd->bufferPage0;
+            ret = 1;
+        }
+    }
+
+    return ret;
+}
+
+static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
+    tdinfo_t               td_info;
+    USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_iso_ep_tbl1[index];
+    uint8_t                wk_table[6];
+    uint16_t               devadd;
+
+    get_td_info(p_g_ed, &td_info);
+
+    wk_table[0] = 0;
+    wk_table[1] = USB_HOST_ENDPOINT_DESC;
+    wk_table[2] = td_info.endpoint_no;
+    if (td_info.direction == 2) {
+        wk_table[2] |= USB_HOST_EP_IN;
+    }
+    wk_table[3] = USB_HOST_EP_ISO;
+    wk_table[4] = (uint8_t)td_info.msp;
+    wk_table[5] = (uint8_t)(td_info.msp >> 8);
+    p_g_ed->cycle_time = 1;
+    user_table->pipe_cycle = 0;
+    if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+        usbx_host_get_devadd(td_info.devadr, &devadd);
+        if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) {
+            user_table->pipe_cycle += 3;
+        }
+    }
+
+    p_g_ed->pipe_no    = user_table->pipe_number;
+    usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+}
+
+static void iso_trans(genelal_ed_t *p_g_ed) {
+    hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+    tdinfo_t  td_info;
+    uint32_t  buff_addr;
+    uint32_t  data_size;
+
+    if (((uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00001000) == 0) {
+        buff_addr = (uint32_t)p_isotd->bufferPage0 & 0xFFFFF000;
+    } else {
+        buff_addr = (uint32_t)p_isotd->bufEnd & 0xFFFFF000;
+    }
+    buff_addr |= (uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00000FFF;
+
+    if (p_g_ed->psw_idx < RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) {
+        data_size = p_isotd->offsetPSW[p_g_ed->psw_idx + 1] - p_isotd->offsetPSW[p_g_ed->psw_idx];
+    } else {
+        data_size = (uint32_t)p_isotd->bufEnd - buff_addr + 1;
+    }
+    p_isotd->offsetPSW[p_g_ed->psw_idx] = (uint16_t)data_size;
+
+    get_td_info(p_g_ed, &td_info);
+    p_g_ed->trans_wait = 1;
+    if (connect_status == 0) {
+        ohciwrapp_loc_TransEnd(p_g_ed->pipe_no, TD_CC_DEVICENOTRESPONDING);
+    } else {
+        if (td_info.direction == 1) {
+            usbx_host_start_send_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
+        } else {
+            usbx_host_start_receive_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
+        }
+    }
+}
+#endif
+
+static void connect_check(void) {
+    uint32_t type = 0;
+    uint16_t stat;
+    uint16_t devadd = 0;
+    uint32_t wk_HcRhPortStatus1 = p_usb_reg->HcRhPortStatus1;
+
+    if (usbx_host_CheckAttach() == USB_HOST_ATTACH) {
+        type = 1;
+    }
+
+    if ((((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) == 0) && (type == 0))
+     || (((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) != 0) && (type != 0))) {
+        return;
+    }
+
+    if (type == 0) {
+        usbx_host_UsbDetach();
+        wk_HcRhPortStatus1 &= ~OR_RH_PORT_CCS;
+    } else {
+        usbx_host_UsbAttach();
+        stat = usbx_host_UsbBusReset();
+        RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
+        RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
+        if (stat == USB_HOST_HSMODE) {
+            wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
+            RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+            g_usbx_host_UsbDeviceSpeed = USB_HOST_HIGH_SPEED;
+        } else if (stat == USB_HOST_FSMODE) {
+            wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
+            RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+            g_usbx_host_UsbDeviceSpeed = USB_HOST_FULL_SPEED;
+        } else {
+            wk_HcRhPortStatus1 |= OR_RH_PORT_LSDA;
+            RZA_IO_RegWrite_16(&USB20X.SOFCFG, 1, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+            g_usbx_host_UsbDeviceSpeed = USB_HOST_LOW_SPEED;
+        }
+        RZA_IO_RegWrite_16(&devadd, g_usbx_host_UsbDeviceSpeed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+        usbx_host_init_pipe_status();
+        usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
+        wk_HcRhPortStatus1 |= OR_RH_PORT_CCS;
+    }
+    wk_HcRhPortStatus1           |= OR_RH_PORT_CSC;
+    p_usb_reg->HcRhPortStatus1   =  wk_HcRhPortStatus1;
+    p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_RHSC;
+    (void)memset(&split_ctl, 0, sizeof(split_ctl));
+}
+
+void ohciwrapp_loc_Connect(uint32_t type) {
+    uint32_t cnt;
+
+    connect_status = type;
+    connect_change = type;
+    if (type == 0) {
+        if (ctl_ed.trans_wait == 1) {
+            ohciwrapp_loc_TransEnd(ctl_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
+        }
+        if (blk_ed.trans_wait == 1) {
+            ohciwrapp_loc_TransEnd(blk_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
+        }
+        for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
+            if (int_ed[cnt].trans_wait == 1) {
+                ohciwrapp_loc_TransEnd(int_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING);
+            }
+        }
+#if (ISO_TRANS_MAX_NUM > 0)
+        for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) {
+            if (iso_ed[cnt].trans_wait == 1) {
+                hced_t  *p_ed = iso_ed[cnt].p_curr_ed;
+
+                p_ed->headTD |= ED_HALTED;
+                ohciwrapp_loc_TransEnd(iso_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING);
+            }
+        }
+#endif
+    }
+    (void)osSemaphoreRelease(semid_cb);
+}
+
+void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) {
+    uint32_t     periodic = 0;
+    uint32_t     cnt;
+    uint32_t     sqmon;
+    hced_t       *p_ed;
+    genelal_ed_t *p_wait_ed = NULL;
+
+    if (ctl_ed.pipe_no == pipe) {
+        p_wait_ed = &ctl_ed;
+    } else if (blk_ed.pipe_no == pipe) {
+        p_wait_ed = &blk_ed;
+    } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+        if (p_wait_ed == NULL) {
+            for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) {
+                if (iso_ed[cnt].pipe_no == pipe) {
+                    p_wait_ed = &iso_ed[cnt];
+                    break;
+                }
+            }
+        }
+#endif
+        if (p_wait_ed == NULL) {
+            for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
+                if (int_ed[cnt].pipe_no == pipe) {
+                    p_wait_ed = &int_ed[cnt];
+                    periodic = 1;
+                    break;
+                }
+            }
+        }
+    }
+
+    if (p_wait_ed == NULL) {
+        return;
+    }
+    p_ed  = p_wait_ed->p_curr_ed;
+    if (p_ed == NULL) {
+        return;
+    }
+
+    if ((p_ed->control & ED_FORMAT) == 0) {
+        hctd_t    *p_td = (hctd_t *)p_wait_ed->p_curr_td;
+
+        if (p_td != NULL) {
+            if (ConditionCode == TD_CC_NOERROR) {
+                /* ErrorCount */
+                RZA_IO_RegWrite_32(&p_td->control, 0, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
+
+                /* CurrentBufferPointer */
+                p_td->currBufPtr += ((uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1) - g_usbx_host_data_count[pipe];
+            } else {
+                /* ErrorCount */
+                RZA_IO_RegWrite_32(&p_td->control, 3, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
+            }
+
+            /* DataToggle */
+            sqmon = usbx_host_get_sqmon(pipe);
+            RZA_IO_RegWrite_32(&p_td->control, sqmon, TD_CTL_SHFT_T, TD_CTL_MSK_T);
+            if (sqmon == 0) {
+                p_ed->headTD &= ~ED_TOGLE_CARRY;
+            } else {
+                p_ed->headTD |= ED_TOGLE_CARRY;
+            }
+
+            /* ConditionCode */
+            RZA_IO_RegWrite_32(&p_td->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+            if (p_wait_ed == &ctl_ed) {
+                chk_split_trans_setting(&ctl_ed);
+            }
+            chk_genelal_td_done(p_wait_ed);
+
+            if (periodic != 0) {
+                if (chk_genelal_ed(p_wait_ed) != 0) {
+                    int_trans(p_wait_ed);
+                } else {
+                    p_wait_ed->trans_wait = 0;
+                    (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+                }
+            } else {
+                p_wait_ed->trans_wait = 0;
+                (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+            }
+        }
+    } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+        hcisotd_t *p_isotd = (hcisotd_t *)p_wait_ed->p_curr_td;
+        uint32_t  next_trans = 0;
+
+        if (p_isotd != NULL) {
+            usbx_host_stop_transfer(pipe);
+            p_usb_reg->HcFmNumber = ((p_isotd->control & 0x0000FFFF) + p_wait_ed->psw_idx) & 0x0000FFFF;
+
+            /* Size of packet */
+            p_isotd->offsetPSW[p_wait_ed->psw_idx] -= g_usbx_host_data_count[pipe];
+
+            /* ConditionCode */
+            RZA_IO_RegWrite_32(&p_isotd->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+            RZA_IO_RegWrite_16(&p_isotd->offsetPSW[p_wait_ed->psw_idx],
+                               (uint16_t)ConditionCode, TD_PSW_SHFT_CC, TD_PSW_MSK_CC);
+
+            if (usbx_host_CheckAttach() != USB_HOST_ATTACH) {
+                p_ed->headTD  |= ED_HALTED;
+            }
+            if (p_wait_ed->psw_idx >= RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) {
+                p_wait_ed->psw_idx = 0;
+                chk_iso_td_done(p_wait_ed);
+            } else {
+                p_wait_ed->psw_idx++;
+            }
+            if (chk_iso_ed(p_wait_ed) != 0) {
+                iso_trans(p_wait_ed);
+                next_trans = 1;
+            }
+            if (next_trans == 0) {
+                p_wait_ed->trans_wait = 0;
+                (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+            }
+        }
+#endif
+    }
+
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/ohci_wrapp_RZ_A1.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,60 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef OHCI_WRAPP_RZ_A1_H
+#define OHCI_WRAPP_RZ_A1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define OHCI_REG_REVISION           (0x00)    /* HcRevision         */
+#define OHCI_REG_CONTROL            (0x04)    /* HcControl          */
+#define OHCI_REG_COMMANDSTATUS      (0x08)    /* HcCommandStatus    */
+#define OHCI_REG_INTERRUPTSTATUS    (0x0C)    /* HcInterruptStatus  */
+#define OHCI_REG_INTERRUPTENABLE    (0x10)    /* HcInterruptEnable  */
+#define OHCI_REG_INTERRUPTDISABLE   (0x14)    /* HcInterruptDisable */
+#define OHCI_REG_HCCA               (0x18)    /* HcHCCA             */
+#define OHCI_REG_PERIODCURRENTED    (0x1C)    /* HcPeriodCurrentED  */
+#define OHCI_REG_CONTROLHEADED      (0x20)    /* HcControlHeadED    */
+#define OHCI_REG_CONTROLCURRENTED   (0x24)    /* HcControlCurrentED */
+#define OHCI_REG_BULKHEADED         (0x28)    /* HcBulkHeadED       */
+#define OHCI_REG_BULKCURRENTED      (0x2C)    /* HcBulkCurrentED    */
+#define OHCI_REG_DONEHEADED         (0x30)    /* HcDoneHead         */
+#define OHCI_REG_FMINTERVAL         (0x34)    /* HcFmInterval       */
+#define OHCI_REG_FMREMAINING        (0x38)    /* HcFmRemaining      */
+#define OHCI_REG_FMNUMBER           (0x3C)    /* HcFmNumber         */
+#define OHCI_REG_PERIODICSTART      (0x40)    /* HcPeriodicStart    */
+#define OHCI_REG_LSTHRESHOLD        (0x44)    /* HcLSThreshold      */
+#define OHCI_REG_RHDESCRIPTORA      (0x48)    /* HcRhDescriptorA    */
+#define OHCI_REG_RHDESCRIPTORB      (0x4C)    /* HcRhDescriptorB    */
+#define OHCI_REG_RHSTATUS           (0x50)    /* HcRhStatus         */
+#define OHCI_REG_RHPORTSTATUS1      (0x54)    /* HcRhPortStatus1    */
+
+typedef void (usbisr_fnc_t)(void);
+
+extern void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc);
+extern uint32_t ohciwrapp_reg_r(uint32_t reg_ofs);
+extern void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data);
+extern void ohciwrapp_interrupt(uint32_t int_sense);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* OHCI_WRAPP_RZ_A1_H */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/ohci_wrapp_RZ_A1_local.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,49 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef OHCI_WRAPP_RZ_A1_LOCAL_H
+#define OHCI_WRAPP_RZ_A1_LOCAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ConditionCode */
+#define TD_CC_NOERROR             (0)
+#define TD_CC_CRC                 (1)
+#define TD_CC_BITSTUFFING         (2)
+#define TD_CC_DATATOGGLEMISMATCH  (3)
+#define TD_CC_STALL               (4)
+#define TD_CC_DEVICENOTRESPONDING (5)
+#define TD_CC_PIDCHECKFAILURE     (6)
+#define TD_CC_UNEXPECTEDPID       (7)
+#define TD_CC_DATAOVERRUN         (8)
+#define TD_CC_DATAUNDERRUN        (9)
+#define TD_CC_BUFFEROVERRUN       (12)
+#define TD_CC_BUFFERUNDERRUN      (13)
+#define TD_CC_NOT_ACCESSED_1      (14)
+#define TD_CC_NOT_ACCESSED_2      (15)
+
+extern void ohciwrapp_loc_Connect(uint32_t type);
+extern void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* OHCI_WRAPP_RZ_A1_LOCAL_H */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/ohci_wrapp_pipe.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,189 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/********************************************************************************************************/
+/* Endpoint Configuration Data Format                                                                   */
+/********************************************************************************************************/
+/*  LINE1: Pipe Window Select Register                                                                  */
+/*      CPU Access PIPE                 : USB_HOST_PIPE1 to USB_HOST_PIPE9      [ ### SET ### ]         */
+/*  LINE2: Pipe Configuration Register                                                                  */
+/*      Transfer Type                   : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*      Buffer Ready interrupt          : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*      Double Buffer Mode              : USB_HOST_DBLBON / USB_HOST_DBLBOFF    [ ### SET ### ]         */
+/*      Continuous Transmit:            : USB_HOST_CNTMDON / USB_HOST_CNTMDOFF  [ ### SET ### ]         */
+/*      Short NAK                       : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*      Transfer Direction              : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*      Endpoint Number                 : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*  LINE3: Pipe Buffer Configuration Register                                                           */
+/*      Buffer Size                     : (uint16_t)((uint16_t)(((x) / 64) - 1) << 10)                  */
+/*                                                                              [ ### SET ### ]         */
+/*      Buffer Top Number               : (uint16_t)(x)                         [ ### SET ### ]         */
+/*  LINE4: Pipe Maxpacket Size Register                                                                 */
+/*      Max Packet Size                 : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*  LINE5: Pipe Cycle Configuration Register (0x6C)                                                     */
+/*      ISO Buffer Flush Mode           : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*      ISO Interval Value              : USB_HOST_NONE                         [ USB_HOST_NONE    ]    */
+/*  LINE6: use FIFO port                                                                                */
+/*                                      : USB_HOST_CUSE                         [ ### SET ### ]         */
+/*                                      : USB_HOST_D0USE / USB_HOST_D1USE                               */
+/*                                      : USB_HOST_D0DMA / USB_HOST_D0DMA                               */
+/********************************************************************************************************/
+
+/* Device Address 1 */
+USB_HOST_CFG_PIPETBL_t     usb_host_blk_ep_tbl1[ ] =
+{
+    {
+        USB_HOST_PIPE3,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(8),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D0USE
+    },
+
+    {
+        /* Pipe end */
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF
+    }
+};
+
+USB_HOST_CFG_PIPETBL_t     usb_host_int_ep_tbl1[ ] =
+{
+    {
+        USB_HOST_PIPE6,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(40),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        USB_HOST_PIPE7,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(41),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        USB_HOST_PIPE8,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(42),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        USB_HOST_PIPE9,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBOFF | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(43),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        /* Pipe end */
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF
+    }
+};
+
+USB_HOST_CFG_PIPETBL_t     usb_host_iso_ep_tbl1[ ] =
+{
+    {
+        USB_HOST_PIPE1,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBON | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(44),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        USB_HOST_PIPE2,
+        /* TYPE       / BFRE           / DBLB            / CNTMD            / SHTNAK        / DIR           / EPNUM */
+        USB_HOST_NONE | USB_HOST_NONE  | USB_HOST_DBLBON | USB_HOST_CNTMDOFF | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+        (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(76),
+        USB_HOST_NONE,
+        USB_HOST_NONE,
+        USB_HOST_D1USE
+    },
+
+    {
+        /* Pipe end */
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF,
+        0xFFFF
+    }
+};
+
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/inc/usb0_host.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,156 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_H
+#define USB0_HOST_H
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+#include "usb_host.h"
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t   g_usb0_host_bit_set[];
+extern uint32_t         g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+extern uint8_t          *g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+extern uint16_t         g_usb0_host_PipeIgnore[];
+extern uint16_t         g_usb0_host_PipeTbl[];
+extern uint16_t         g_usb0_host_pipe_status[];
+extern uint32_t         g_usb0_host_PipeDataSize[];
+
+extern USB_HOST_DMA_t   g_usb0_host_DmaInfo[];
+extern uint16_t         g_usb0_host_DmaPipe[];
+extern uint16_t         g_usb0_host_DmaBval[];
+extern uint16_t         g_usb0_host_DmaStatus[];
+
+extern uint16_t         g_usb0_host_driver_state;
+extern uint16_t         g_usb0_host_ConfigNum;
+extern uint16_t         g_usb0_host_CmdStage;
+extern uint16_t         g_usb0_host_bchg_flag;
+extern uint16_t         g_usb0_host_detach_flag;
+extern uint16_t         g_usb0_host_attach_flag;
+
+extern uint16_t         g_usb0_host_UsbAddress;
+extern uint16_t         g_usb0_host_setUsbAddress;
+extern uint16_t         g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+extern uint16_t         g_usb0_host_UsbDeviceSpeed;
+extern uint16_t         g_usb0_host_SupportUsbDeviceSpeed;
+
+extern uint16_t         g_usb0_host_SavReq;
+extern uint16_t         g_usb0_host_SavVal;
+extern uint16_t         g_usb0_host_SavIndx;
+extern uint16_t         g_usb0_host_SavLen;
+
+extern uint16_t  g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+/* ==== common ==== */
+void        usb0_host_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void        usb0_host_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t    usb0_host_is_hispeed(void);
+uint16_t    usb0_host_is_hispeed_enable(void);
+uint16_t    usb0_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t    usb0_host_write_buffer(uint16_t pipe);
+uint16_t    usb0_host_write_buffer_c(uint16_t pipe);
+uint16_t    usb0_host_write_buffer_d0(uint16_t pipe);
+uint16_t    usb0_host_write_buffer_d1(uint16_t pipe);
+void        usb0_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t    usb0_host_read_buffer(uint16_t pipe);
+uint16_t    usb0_host_read_buffer_c(uint16_t pipe);
+uint16_t    usb0_host_read_buffer_d0(uint16_t pipe);
+uint16_t    usb0_host_read_buffer_d1(uint16_t pipe);
+uint16_t    usb0_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void        usb0_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void        usb0_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t    usb0_host_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t    usb0_host_read_dma(uint16_t pipe);
+void        usb0_host_stop_transfer(uint16_t pipe);
+void        usb0_host_brdy_int(uint16_t status, uint16_t int_enb);
+void        usb0_host_nrdy_int(uint16_t status, uint16_t int_enb);
+void        usb0_host_bemp_int(uint16_t status, uint16_t int_enb);
+void        usb0_host_setting_interrupt(uint8_t level);
+void        usb0_host_reset_module(uint16_t clockmode);
+uint16_t    usb0_host_get_buf_size(uint16_t pipe);
+uint16_t    usb0_host_get_mxps(uint16_t pipe);
+void        usb0_host_enable_brdy_int(uint16_t pipe);
+void        usb0_host_disable_brdy_int(uint16_t pipe);
+void        usb0_host_clear_brdy_sts(uint16_t pipe);
+void        usb0_host_enable_bemp_int(uint16_t pipe);
+void        usb0_host_disable_bemp_int(uint16_t pipe);
+void        usb0_host_clear_bemp_sts(uint16_t pipe);
+void        usb0_host_enable_nrdy_int(uint16_t pipe);
+void        usb0_host_disable_nrdy_int(uint16_t pipe);
+void        usb0_host_clear_nrdy_sts(uint16_t pipe);
+void        usb0_host_set_pid_buf(uint16_t pipe);
+void        usb0_host_set_pid_nak(uint16_t pipe);
+void        usb0_host_set_pid_stall(uint16_t pipe);
+void        usb0_host_clear_pid_stall(uint16_t pipe);
+uint16_t    usb0_host_get_pid(uint16_t pipe);
+void        usb0_host_set_sqclr(uint16_t pipe);
+void        usb0_host_set_sqset(uint16_t pipe);
+void        usb0_host_set_csclr(uint16_t pipe);
+void        usb0_host_aclrm(uint16_t pipe);
+void        usb0_host_set_aclrm(uint16_t pipe);
+void        usb0_host_clr_aclrm(uint16_t pipe);
+uint16_t    usb0_host_get_sqmon(uint16_t pipe);
+uint16_t    usb0_host_get_inbuf(uint16_t pipe);
+
+/* ==== host ==== */
+void        usb0_host_init_pipe_status(void);
+int32_t     usb0_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+void        usb0_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void        usb0_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+uint16_t    usb0_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table);
+void        usb0_host_StatusStage(void);
+void        usb0_host_get_devadd(uint16_t addr, uint16_t *devadd);
+void        usb0_host_set_devadd(uint16_t addr, uint16_t *devadd);
+void        usb0_host_InitModule(void);
+uint16_t    usb0_host_CheckAttach(void);
+void        usb0_host_UsbDetach(void);
+void        usb0_host_UsbDetach2(void);
+void        usb0_host_UsbAttach(void);
+uint16_t    usb0_host_UsbBusReset(void);
+int32_t     usb0_host_UsbResume(void);
+int32_t     usb0_host_UsbSuspend(void);
+void        usb0_host_Enable_DetachINT(void);
+void        usb0_host_Disable_DetachINT(void);
+void        usb0_host_UsbStateManager(void);
+
+
+#endif /* USB0_HOST_H */
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/inc/usb0_host_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_API_H
+#define USB0_HOST_API_H
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void        usb0_host_interrupt(uint32_t int_sense);
+void        usb0_host_dma_interrupt_d0fifo(uint32_t int_sense);
+void        usb0_host_dma_interrupt_d1fifo(uint32_t int_sense);
+
+uint16_t    usb0_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t     usb0_api_host_enumeration(uint16_t devadr);
+int32_t     usb0_api_host_detach(void);
+int32_t     usb0_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t     usb0_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t     usb0_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t     usb0_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t     usb0_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t     usb0_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t    usb0_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table);
+int32_t     usb0_api_host_data_count(uint16_t pipe, uint32_t *data_count);
+
+int32_t     usb0_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t     usb0_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t     usb0_api_host_SetConfig(uint16_t devadr, uint16_t confignum);
+int32_t     usb0_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t     usb0_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir);
+uint16_t    usb0_api_host_GetUsbDeviceState(void);
+
+void        usb0_api_host_elt_4_4(void);
+void        usb0_api_host_elt_4_5(void);
+void        usb0_api_host_elt_4_6(void);
+void        usb0_api_host_elt_4_7(void);
+void        usb0_api_host_elt_4_8(void);
+void        usb0_api_host_elt_4_9(void);
+void        usb0_api_host_elt_get_desc(void);
+
+void        usb0_host_EL_ModeInit(void);
+void        usb0_host_EL_SetUACT(void);
+void        usb0_host_EL_ClearUACT(void);
+void        usb0_host_EL_SetTESTMODE(uint16_t mode);
+void        usb0_host_EL_ClearNRDYSTS(uint16_t pipe);
+uint16_t    usb0_host_EL_GetINTSTS1(void);
+void        usb0_host_EL_UsbBusReset(void);
+void        usb0_host_EL_UsbAttach(void);
+void        usb0_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void        usb0_host_EL_StatusStage(void);
+void        usb0_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+int32_t     usb0_host_EL_UsbSuspend(void);
+int32_t     usb0_host_EL_UsbResume(void);
+
+#if 0   /* prototype in devdrv_usb_host_api.h */
+uint16_t    Userdef_USB_usb0_host_d0fifo_dmaintid(void);
+uint16_t    Userdef_USB_usb0_host_d1fifo_dmaintid(void);
+void        Userdef_USB_usb0_host_attach(void);
+void        Userdef_USB_usb0_host_detach(void);
+void        Userdef_USB_usb0_host_delay_1ms(void);
+void        Userdef_USB_usb0_host_delay_xms(uint32_t msec);
+void        Userdef_USB_usb0_host_delay_10us(uint32_t usec);
+void        Userdef_USB_usb0_host_delay_500ns(void);
+void        Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc);
+uint32_t    Userdef_USB_usb0_host_stop_dma0(void);
+uint32_t    Userdef_USB_usb0_host_stop_dma1(void);
+#endif
+
+#endif /* USB0_HOST_API_H */
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,139 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_DMACDRV_H
+#define USB0_HOST_DMACDRV_H
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+    uint32_t src_addr;      /* Transfer source address                */
+    uint32_t dst_addr;      /* Transfer destination address           */
+    uint32_t count;         /* Transfer byte count                    */
+    uint32_t src_size;      /* Transfer source data size              */
+    uint32_t dst_size;      /* Transfer destination data size         */
+    uint32_t saddr_dir;     /* Transfer source address direction      */
+    uint32_t daddr_dir;     /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE          (0)     /* Single transfer                   */
+#define DMAC_SAMPLE_CONTINUATION    (1)     /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER          (0)     /* Register mode */
+#define DMAC_MODE_LINK              (1)     /* Link mode     */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT           (0)     /* External request                   */
+#define DMAC_REQ_MODE_PERI          (1)     /* On-chip peripheral module request  */
+#define DMAC_REQ_MODE_SOFT          (2)     /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8           (0)     /* 8 bits    */
+#define DMAC_TRANS_SIZE_16          (1)     /* 16 bits   */
+#define DMAC_TRANS_SIZE_32          (2)     /* 32 bits   */
+#define DMAC_TRANS_SIZE_64          (3)     /* 64 bits   */
+#define DMAC_TRANS_SIZE_128         (4)     /* 128 bits  */
+#define DMAC_TRANS_SIZE_256         (5)     /* 256 bits  */
+#define DMAC_TRANS_SIZE_512         (6)     /* 512 bits  */
+#define DMAC_TRANS_SIZE_1024        (7)     /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC       (1)     /* Not increment */
+#define DMAC_TRANS_ADR_INC          (0)     /* Increment     */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL           (0)     /* Falling edge detection */
+#define DMAC_REQ_DET_RISE           (1)     /* Rising edge detection  */
+#define DMAC_REQ_DET_LOW            (2)     /* Low level detection    */
+#define DMAC_REQ_DET_HIGH           (3)     /* High level detection   */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC            (0)     /* DMAREQ is the source/ DMAACK is active when reading      */
+#define DMAC_REQ_DIR_DST            (1)     /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER            (0)     /* Header              */
+#define DMAC_DESC_SRC_ADDR          (1)     /* Source Address      */
+#define DMAC_DESC_DST_ADDR          (2)     /* Destination Address */
+#define DMAC_DESC_COUNT             (3)     /* Transaction Byte    */
+#define DMAC_DESC_CHCFG             (4)     /* Channel Confg       */
+#define DMAC_DESC_CHITVL            (5)     /* Channel Interval    */
+#define DMAC_DESC_CHEXT             (6)     /* Channel Extension   */
+#define DMAC_DESC_LINK_ADDR         (7)     /* Link Address        */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+    DMAC_REQ_USB0_DMA0_TX,      /* USB_0 channel 0 transmit FIFO empty            */
+    DMAC_REQ_USB0_DMA0_RX,      /* USB_0 channel 0 receive FIFO full              */
+    DMAC_REQ_USB0_DMA1_TX,      /* USB_0 channel 1 transmit FIFO empty            */
+    DMAC_REQ_USB0_DMA1_RX,      /* USB_0 channel 1 receive FIFO full              */
+    DMAC_REQ_USB1_DMA0_TX,      /* USB_1 channel 0 transmit FIFO empty            */
+    DMAC_REQ_USB1_DMA0_RX,      /* USB_1 channel 0 receive FIFO full              */
+    DMAC_REQ_USB1_DMA1_TX,      /* USB_1 channel 1 transmit FIFO empty            */
+    DMAC_REQ_USB1_DMA1_RX,      /* USB_1 channel 1 receive FIFO full              */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb0_host_DMAC1_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                                 uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_host_DMAC1_Open(uint32_t req);
+void usb0_host_DMAC1_Close(uint32_t * remain);
+void usb0_host_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb0_host_DMAC2_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                                 uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_host_DMAC2_Open(uint32_t req);
+void usb0_host_DMAC2_Close(uint32_t * remain);
+void usb0_host_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#endif  /* USB0_HOST_DMACDRV_H */
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/common/usb0_host_dataio.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,2835 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb0_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)];
+
+static void     usb0_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb0_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb0_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb0_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb0_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb0_host_read_dma_d0(uint16_t pipe);
+static uint16_t usb0_host_read_dma_d1(uint16_t pipe);
+static uint16_t usb0_host_write_dma_d0(uint16_t pipe);
+static uint16_t usb0_host_write_dma_d1(uint16_t pipe);
+
+static void     usb0_host_read_c_fifo(uint16_t pipe, uint16_t count);
+static void     usb0_host_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void     usb0_host_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void     usb0_host_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void     usb0_host_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void     usb0_host_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void     usb0_host_clear_transaction_counter(uint16_t pipe);
+static void     usb0_host_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb0_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb0_host_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb0_host_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb0_host_start_send_transfer
+* Description  : Starts the USB data communication using pipe specified by the argument.
+* Arguments    : uint16_t  pipe    ; Pipe Number
+*              : uint32_t size     ; Data Size
+*              : uint8_t  *data    ; Data data Address
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t status;
+    uint16_t usefifo;
+    uint16_t mbw;
+
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    usb0_host_clear_bemp_sts(pipe);
+    usb0_host_clear_brdy_sts(pipe);
+    usb0_host_clear_nrdy_sts(pipe);
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+
+    usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+        case USB_HOST_D0FIFO_DMA:
+            usefifo = USB_HOST_D0USE;
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+        case USB_HOST_D1FIFO_DMA:
+            usefifo = USB_HOST_D1USE;
+        break;
+
+        default:
+            usefifo = USB_HOST_CUSE;
+        break;
+    };
+
+    usb0_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw);
+
+    usb0_host_clear_transaction_counter(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    status = usb0_host_write_buffer(pipe);
+
+    if (status != USB_HOST_FIFOERROR)
+    {
+        usb0_host_set_pid_buf(pipe);
+    }
+
+    return status;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer
+* Description  : Writes data in the buffer allocated in the pipe specified by
+*              : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer (uint16_t pipe)
+{
+    uint16_t status;
+    uint16_t usefifo;
+
+    g_usb0_host_PipeIgnore[pipe] = 0;
+    usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            status = usb0_host_write_buffer_d0(pipe);
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            status = usb0_host_write_buffer_d1(pipe);
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            status = usb0_host_write_dma_d0(pipe);
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            status = usb0_host_write_dma_d1(pipe);
+        break;
+
+        default:
+            status = usb0_host_write_buffer_c(pipe);
+        break;
+    };
+
+    switch (status)
+    {
+        case USB_HOST_WRITING:                      /* Continue of data write */
+            usb0_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+            usb0_host_enable_brdy_int(pipe);        /* Enable Ready Interrupt */
+        break;
+
+        case USB_HOST_WRITEEND:                     /* End of data write */
+        case USB_HOST_WRITESHRT:                    /* End of data write */
+            usb0_host_disable_brdy_int(pipe);       /* Disable Ready Interrupt */
+
+            usb0_host_clear_nrdy_sts(pipe);
+            usb0_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+
+            /* for last transfer */
+            usb0_host_enable_bemp_int(pipe);        /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_WRITEDMA:                     /* DMA write */
+            usb0_host_clear_nrdy_sts(pipe);
+            usb0_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+        break;
+
+        case USB_HOST_FIFOERROR:                    /* FIFO access status */
+        default:
+            usb0_host_disable_brdy_int(pipe);       /* Disable Ready Interrupt */
+            usb0_host_disable_bemp_int(pipe);       /* Disable Empty Interrupt */
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_c
+* Description  : Writes data in the buffer allocated in the pipe specified in
+*              : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_c (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw);
+    }
+    else
+    {
+        buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO,  mbw);
+    }
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb0_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count  = g_usb0_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb0_host_write_c_fifo(pipe, (uint16_t)count);
+
+    if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb0_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB200.CFIFOCTR,
+                                USB_CFIFOCTR_BVAL_SHIFT,
+                                USB_CFIFOCTR_BVAL) == 0)
+        {
+            USB200.CFIFOCTR = USB_HOST_BITBVAL;             /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb0_host_data_count[pipe] -= count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_d0
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by CPU transfer using D0FIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw    = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb0_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count = g_usb0_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb0_host_write_d0_fifo(pipe, (uint16_t)count);
+
+    if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb0_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            USB200.D0FIFOCTR = USB_HOST_BITBVAL;            /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb0_host_data_count[pipe] -= count;
+    }
+
+    return status;                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_d1
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by CPU transfer using D1FIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb0_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count  = g_usb0_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb0_host_write_d1_fifo(pipe, (uint16_t)count);
+
+    if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb0_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            USB200.D1FIFOCTR = USB_HOST_BITBVAL;            /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb0_host_data_count[pipe] -= count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_dma_d0
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by DMA transfer using D0FIFO.
+*              : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma().
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          : Write end
+*              : USB_HOST_WRITESHRT         : short data
+*              : USB_HOST_WRITING           : Continue of data write
+*              : USB_HOST_WRITEDMA          : Write DMA
+*              : USB_HOST_FIFOERROR         : FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_write_dma_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size  = usb0_host_get_buf_size(pipe);                   /* Data buffer size */
+    count = g_usb0_host_data_count[pipe];
+
+    if (count != 0)
+    {
+        g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe;
+
+        if ((count % size) != 0)
+        {
+            g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 1;
+        }
+        else
+        {
+            g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0;
+        }
+
+        dfacc = usb0_host_set_dfacc_d0(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo   = USB_HOST_D0FIFO_DMA;
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir    = USB_HOST_BUF2FIFO;
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes  = count;
+
+        Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+        usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+        RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+
+        g_usb0_host_data_count[pipe]    = 0;
+        g_usb0_host_data_pointer[pipe] += count;
+
+        status = USB_HOST_WRITEDMA;                         /* DMA write  */
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);        /* Short Packet */
+        }
+        status = USB_HOST_WRITESHRT;                        /* Short Packet is end of write */
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_dma_d1
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by DMA transfer using D1FIFO.
+*              : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma().
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          : Write end
+*              : USB_HOST_WRITESHRT         : short data
+*              : USB_HOST_WRITING           : Continue of data write
+*              : USB_HOST_WRITEDMA          : Write DMA
+*              : USB_HOST_FIFOERROR         : FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_write_dma_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size  = usb0_host_get_buf_size(pipe);                   /* Data buffer size */
+    count = g_usb0_host_data_count[pipe];
+
+    if (count != 0)
+    {
+        g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe;
+
+        if ((count % size) != 0)
+        {
+            g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 1;
+        }
+        else
+        {
+            g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0;
+        }
+
+        dfacc = usb0_host_set_dfacc_d1(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo   = USB_HOST_D1FIFO_DMA;
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir    = USB_HOST_BUF2FIFO;
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes  = count;
+
+        Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+        usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc);
+
+        RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+
+        g_usb0_host_data_count[pipe]    = 0;
+        g_usb0_host_data_pointer[pipe] += count;
+
+        status = USB_HOST_WRITEDMA;                         /* DMA write */
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);        /* Short Packet */
+        }
+        status = USB_HOST_WRITESHRT;                        /* Short Packet is end of write */
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_transfer
+* Description  : Starts USB data reception using the pipe specified in the argument.
+*              : The FIFO for using is set in the pipe definition table.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb0_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t usefifo;
+
+    usb0_host_clear_bemp_sts(pipe);
+    usb0_host_clear_brdy_sts(pipe);
+    usb0_host_clear_nrdy_sts(pipe);
+
+    usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            usb0_host_start_receive_trns_d0(pipe, size, data);
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            usb0_host_start_receive_trns_d1(pipe, size, data);
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            usb0_host_start_receive_dma_d0(pipe, size, data);
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            usb0_host_start_receive_dma_d1(pipe, size, data);
+        break;
+
+        default:
+            usb0_host_start_receive_trns_c(pipe, size, data);
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_c
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using CFIFO.
+*              : When storing data in the buffer allocated in the pipe specified in the
+*              : argument, BRDY interrupt is generated to read data
+*              : in the interrupt.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb0_host_set_pid_nak(pipe);
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_PipeIgnore[pipe]   = 0;
+
+    g_usb0_host_PipeDataSize[pipe] = size;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw);
+    USB200.CFIFOCTR = USB_HOST_BITBCLR;
+
+    usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    usb0_host_enable_nrdy_int(pipe);
+    usb0_host_enable_brdy_int(pipe);
+
+    usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, BRDY interrupt is generated to read data in the
+*              : interrupt.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb0_host_set_pid_nak(pipe);
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_PipeIgnore[pipe]   = 0;
+
+    g_usb0_host_PipeDataSize[pipe] = size;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    usb0_host_enable_nrdy_int(pipe);
+    usb0_host_enable_brdy_int(pipe);
+
+    usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_d1
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using D1FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, BRDY interrupt is generated to read data.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb0_host_set_pid_nak(pipe);
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_PipeIgnore[pipe]   = 0;
+
+    g_usb0_host_PipeDataSize[pipe] = size;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    usb0_host_enable_nrdy_int(pipe);
+    usb0_host_enable_brdy_int(pipe);
+
+    usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_dma_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, delivered read request to DMAC to read data from
+*              : the buffer by DMAC.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb0_host_set_pid_nak(pipe);
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_PipeIgnore[pipe]   = 0;
+
+    g_usb0_host_PipeDataSize[pipe] = 0;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        usb0_host_read_dma(pipe);
+
+        usb0_host_enable_nrdy_int(pipe);
+        usb0_host_enable_brdy_int(pipe);
+    }
+    else
+    {
+        usb0_host_enable_nrdy_int(pipe);
+        usb0_host_enable_brdy_int(pipe);
+    }
+
+    usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_dma_d1
+* Description  : Read data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, delivered read request to DMAC to read data from
+*              : the buffer by DMAC.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb0_host_set_pid_nak(pipe);
+    g_usb0_host_data_count[pipe]   = size;
+    g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb0_host_PipeIgnore[pipe]   = 0;
+
+    g_usb0_host_PipeDataSize[pipe] = 0;
+    g_usb0_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb0_host_get_mbw(size, (uint32_t)data);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        usb0_host_read_dma(pipe);
+
+        usb0_host_enable_nrdy_int(pipe);
+        usb0_host_enable_brdy_int(pipe);
+    }
+    else
+    {
+        usb0_host_enable_nrdy_int(pipe);
+        usb0_host_enable_brdy_int(pipe);
+    }
+
+    usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Uses FIF0 set in the pipe definition table.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer (uint16_t pipe)
+{
+    uint16_t status;
+
+    g_usb0_host_PipeIgnore[pipe] = 0;
+
+    if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+    {
+        status = usb0_host_read_buffer_d0(pipe);
+    }
+    else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+    {
+        status = usb0_host_read_buffer_d1(pipe);
+    }
+    else
+    {
+        status = usb0_host_read_buffer_c(pipe);
+    }
+
+    switch (status)
+    {
+        case USB_HOST_READING:                                  /* Continue of data read */
+        break;
+
+        case USB_HOST_READEND:                                  /* End of data read */
+        case USB_HOST_READSHRT:                                 /* End of data read */
+            usb0_host_disable_brdy_int(pipe);
+            g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+            g_usb0_host_pipe_status[pipe]   = USB_HOST_PIPE_DONE;
+        break;
+
+        case USB_HOST_READOVER:                                 /* buffer over */
+            if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+            {
+                USB200.D0FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+            }
+            else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+            {
+                USB200.D1FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+            }
+            else
+            {
+                USB200.CFIFOCTR = USB_HOST_BITBCLR;                 /* Clear BCLR */
+            }
+            usb0_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+#if(1) /* ohci_wrapp */
+            g_usb0_host_pipe_status[pipe]   = USB_HOST_PIPE_DONE;
+#else
+            g_usb0_host_pipe_status[pipe]   = USB_HOST_PIPE_ERROR;
+#endif
+            g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+        break;
+
+        case USB_HOST_FIFOERROR:                                    /* FIFO access status */
+        default:
+            usb0_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                      /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_c
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using CFIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_c (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw    = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb0_host_data_count[pipe];
+    }
+    else if (g_usb0_host_data_count[pipe] == dtln)          /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB200.CFIFOCTR = USB_HOST_BITBCLR;                 /* Clear BCLR */
+    }
+    else
+    {
+        usb0_host_read_c_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb0_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in
+*              : the argument.
+*              : Reads data by CPU transfer using D0FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t pipebuf_size;
+
+    mbw    = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb0_host_data_count[pipe];
+    }
+    else if (g_usb0_host_data_count[pipe] == dtln)      /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+        else
+        {
+            pipebuf_size = usb0_host_get_buf_size(pipe);    /* Data buffer size */
+
+            if (count != pipebuf_size)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+                usb0_host_set_pid_nak(pipe);                /* Set NAK */
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB200.D0FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+    }
+    else
+    {
+        usb0_host_read_d0_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb0_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_d1
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by CPU transfer using D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t pipebuf_size;
+
+    mbw    = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+    buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb0_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb0_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb0_host_data_count[pipe];
+    }
+    else if (g_usb0_host_data_count[pipe] == dtln)      /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb0_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) !=0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb0_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+        else
+        {
+            pipebuf_size = usb0_host_get_buf_size(pipe);    /* Data buffer size */
+            if (count != pipebuf_size)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+                usb0_host_set_pid_nak(pipe);                /* Set NAK */
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB200.D1FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+    }
+    else
+    {
+        usb0_host_read_d1_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb0_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_dma (uint16_t pipe)
+{
+    uint16_t status;
+
+    g_usb0_host_PipeIgnore[pipe] = 0;
+
+    if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+    {
+        status = usb0_host_read_dma_d0(pipe);
+    }
+    else
+    {
+        status = usb0_host_read_dma_d1(pipe);
+    }
+
+    switch (status)
+    {
+        case USB_HOST_READING:                                      /* Continue of data read */
+        break;
+
+        case USB_HOST_READZERO:                                     /* End of data read */
+            usb0_host_disable_brdy_int(pipe);
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+        break;
+
+        case USB_HOST_READEND:                                      /* End of data read */
+        case USB_HOST_READSHRT:                                     /* End of data read */
+            usb0_host_disable_brdy_int(pipe);
+
+            if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+            {
+                g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+            }
+        break;
+
+        case USB_HOST_READOVER:                                     /* buffer over */
+            usb0_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+
+            if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+            {
+                g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+            }
+#if(1) /* ohci_wrapp */
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+        break;
+
+        case USB_HOST_FIFOERROR:                                    /* FIFO access status */
+        default:
+            usb0_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma_d0
+* Description  : Writes data in the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_read_dma_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+    uint16_t pipebuf_size;
+
+    g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        count  = g_usb0_host_data_count[pipe];
+        status = USB_HOST_READING;
+    }
+    else
+    {
+        buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+        if (buffer == USB_HOST_FIFOERROR)                   /* FIFO access status */
+        {
+            return USB_HOST_FIFOERROR;
+        }
+
+        dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+        mxps = usb0_host_get_mxps(pipe);                    /* Max Packet Size */
+
+        if (g_usb0_host_data_count[pipe] < dtln)            /* Buffer Over ? */
+        {
+            status = USB_HOST_READOVER;
+            count  = g_usb0_host_data_count[pipe];
+        }
+        else if (g_usb0_host_data_count[pipe] == dtln)  /* just Receive Size */
+        {
+            status = USB_HOST_READEND;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+        }
+        else                                                /* continue Receive data */
+        {
+            status = USB_HOST_READING;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+            else
+            {
+                pipebuf_size = usb0_host_get_buf_size(pipe);    /* Data buffer size */
+
+                if (count != pipebuf_size)
+                {
+                    status = USB_HOST_READSHRT;             /* Short Packet receive */
+                }
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+        {
+            USB200.D0FIFOCTR = USB_HOST_BITBCLR;            /* Clear B_CLR */
+            status = USB_HOST_READZERO;                     /* Null Packet receive */
+        }
+        else
+        {
+            usb0_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+                                                            /* transaction counter No set */
+                                                            /* FRDY = 1, DTLN = 0 -> BRDY */
+        }
+    }
+    else
+    {
+        dfacc = usb0_host_set_dfacc_d0(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe;        /* not use in read operation */
+        g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0;           /* not use in read operation */
+
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo   = USB_HOST_D0FIFO_DMA;
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir    = USB_HOST_FIFO2BUF;
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+        g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes  = count;
+
+        if (status == USB_HOST_READING)
+        {
+            g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY;
+        }
+        else
+        {
+            g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND;
+        }
+
+        Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+        usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+        RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+    {
+        g_usb0_host_data_count[pipe]   -= count;
+        g_usb0_host_data_pointer[pipe] += count;
+        g_usb0_host_PipeDataSize[pipe] += count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma_d1
+* Description  : Reads data from the buffer allocated in the pipe specified in
+*              : the argument.
+*              : Reads data by DMA transfer using D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_read_dma_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+    uint16_t pipebuf_size;
+
+    g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        count  = g_usb0_host_data_count[pipe];
+        status = USB_HOST_READING;
+    }
+    else
+    {
+        buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+        if (buffer == USB_HOST_FIFOERROR)                   /* FIFO access status */
+        {
+            return USB_HOST_FIFOERROR;
+        }
+
+        dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+        mxps = usb0_host_get_mxps(pipe);                    /* Max Packet Size */
+
+        if (g_usb0_host_data_count[pipe] < dtln)            /* Buffer Over ? */
+        {
+            status = USB_HOST_READOVER;
+            count  = g_usb0_host_data_count[pipe];
+        }
+        else if (g_usb0_host_data_count[pipe] == dtln)  /* just Receive Size */
+        {
+            status = USB_HOST_READEND;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+        }
+        else                                                /* continue Receive data */
+        {
+            status = USB_HOST_READING;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+            else
+            {
+                pipebuf_size = usb0_host_get_buf_size(pipe);    /* Data buffer size */
+
+                if (count != pipebuf_size)
+                {
+                    status = USB_HOST_READSHRT;             /* Short Packet receive */
+                }
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+        {
+            USB200.D1FIFOCTR = USB_HOST_BITBCLR;            /* Clear BCLR */
+            status = USB_HOST_READZERO;                     /* Null Packet receive */
+        }
+        else
+        {
+            usb0_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+                                                            /* transaction counter No set */
+                                                            /* FRDY = 1, DTLN = 0 -> BRDY */
+        }
+    }
+    else
+    {
+        dfacc = usb0_host_set_dfacc_d1(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe;        /* not use in read operation */
+        g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0;           /* not use in read operation */
+
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo   = USB_HOST_D1FIFO_DMA;
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir    = USB_HOST_FIFO2BUF;
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+        g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes  = count;
+
+        if (status == USB_HOST_READING)
+        {
+            g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY;
+        }
+        else
+        {
+            g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND;
+        }
+
+        Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+        usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc);
+
+        RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+    {
+        g_usb0_host_data_count[pipe]   -= count;
+        g_usb0_host_data_pointer[pipe] += count;
+        g_usb0_host_PipeDataSize[pipe] += count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_change_fifo_port
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument. After allocating FIF0, waits in the software
+*              : till the corresponding pipe becomes ready.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+* Return Value : USB_HOST_FIFOERROR         ; Error
+*              : Others            ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb0_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+    uint16_t          buffer;
+    uint32_t          loop;
+    volatile uint32_t loop2;
+
+    usb0_host_set_curpipe(pipe, fifosel, isel, mbw);
+
+    for (loop = 0; loop < 4; loop++)
+    {
+        switch (fifosel)
+        {
+            case USB_HOST_CUSE:
+                buffer = USB200.CFIFOCTR;
+            break;
+
+            case USB_HOST_D0USE:
+            case USB_HOST_D0DMA:
+                buffer = USB200.D0FIFOCTR;
+            break;
+
+            case USB_HOST_D1USE:
+            case USB_HOST_D1DMA:
+                buffer = USB200.D1FIFOCTR;
+            break;
+
+            default:
+                buffer = 0;
+            break;
+        }
+
+        if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY)
+        {
+            return buffer;
+        }
+
+        loop2 = 25;
+
+        while (loop2-- > 0)
+        {
+            /* wait */
+        }
+    }
+
+    return USB_HOST_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_curpipe
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+    uint16_t          buffer;
+    uint32_t          loop;
+    volatile uint32_t loop2;
+
+    g_usb0_host_mbw[pipe] = mbw;
+
+    switch (fifosel)
+    {
+        case USB_HOST_CUSE:
+            buffer  = USB200.CFIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+            buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+            USB200.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(isel | pipe | mbw);
+            USB200.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D0DMA:
+        case USB_HOST_D0USE:
+            buffer  = USB200.D0FIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+            USB200.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB200.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D1DMA:
+        case USB_HOST_D1USE:
+            buffer  = USB200.D1FIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+            USB200.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB200.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        default:
+        break;
+    }
+
+    /* Cautions !!!
+     * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+     * For details, please look at the data sheet.   */
+    loop2 = 100;
+
+    while (loop2-- > 0)
+    {
+        /* wait */
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_curpipe2
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument.(DFACC)
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+*              : uint16_t dfacc     ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+    uint16_t buffer;
+    uint32_t loop;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+    uint32_t dummy;
+#endif
+    volatile uint32_t loop2;
+
+    g_usb0_host_mbw[pipe] = mbw;
+
+    switch (fifosel)
+    {
+        case USB_HOST_CUSE:
+            buffer  = USB200.CFIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+            buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+            USB200.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(isel | pipe | mbw);
+            USB200.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D0DMA:
+        case USB_HOST_D0USE:
+            buffer  = USB200.D0FIFOSEL;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+            if (dfacc != 0)
+            {
+                buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+            }
+#else
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+            USB200.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            if (dfacc != 0)
+            {
+                dummy = USB200.D0FIFO.UINT32;
+            }
+#endif
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB200.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D1DMA:
+        case USB_HOST_D1USE:
+            buffer  = USB200.D1FIFOSEL;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+            if (dfacc != 0)
+            {
+                buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+            }
+#else
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+            USB200.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            if (dfacc != 0)
+            {
+                dummy = USB200.D1FIFO.UINT32;
+                loop = dummy;                   // avoid warning.
+            }
+#endif
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB200.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        default:
+        break;
+    }
+
+    /* Cautions !!!
+     * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+     * For details, please look at the data sheet.   */
+    loop2 = 100;
+    while (loop2-- > 0)
+    {
+        /* wait */
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_c_fifo
+* Description  : Writes data in CFIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB200.CFIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_c_fifo
+* Description  : Reads data from CFIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb0_host_data_pointer[pipe] = USB200.CFIFO.UINT8[HH];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT16[H];
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT32;
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_d0_fifo
+* Description  : Writes data in D0FIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB200.D0FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_d0_fifo
+* Description  : Reads data from D0FIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating DOFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  Pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb0_host_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H];
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT32;
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_d1_fifo
+* Description  : Writes data in D1FIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating D1FIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB200.D1FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_d1_fifo
+* Description  : Reads data from D1FIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating D1FIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb0_host_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH];
+            g_usb0_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H];
+            g_usb0_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT32;
+            g_usb0_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_com_get_dmasize
+* Description  : Calculates access width of DMA transfer by the argument to
+                 return as the Return Value.
+* Arguments    : uint32_t trncount   : transfer byte
+*              : uint32_t dtptr      : transfer data pointer
+* Return Value : DMA transfer size    : 0   8bit
+*              :                      : 1  16bit
+*              :                      : 2  32bit
+*******************************************************************************/
+static uint32_t usb0_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+    uint32_t size;
+
+    if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+    {
+        /*  When transfer byte count is odd         */
+        /* or transfer data area is 8-bit alignment */
+        size = 0;           /* 8bit */
+    }
+    else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+    {
+        /* When the transfer byte count is multiples of 2 */
+        /* or the transfer data area is 16-bit alignment */
+        size = 1;           /* 16bit */
+    }
+    else
+    {
+        /* When the transfer byte count is multiples of 4 */
+        /* or the transfer data area is 32-bit alignment */
+        size = 2;           /* 32bit */
+    }
+
+    return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_mbw
+* Description  : Calculates access width of DMA to return the value set in MBW.
+* Arguments    : uint32_t trncount   : transfer byte
+*              : uint32_t dtptr      : transfer data pointer
+* Return Value : FIFO transfer size   : USB_HOST_BITMBW_8    8bit
+*              :                      : USB_HOST_BITMBW_16  16bit
+*              :                      : USB_HOST_BITMBW_32  32bit
+*******************************************************************************/
+uint16_t usb0_host_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+    uint32_t size;
+    uint16_t mbw;
+
+    size = usb0_host_com_get_dmasize(trncount, dtptr);
+
+    if (size == 0)
+    {
+        /* 8bit */
+        mbw = USB_HOST_BITMBW_8;
+    }
+    else if (size == 1)
+    {
+        /* 16bit */
+        mbw = USB_HOST_BITMBW_16;
+    }
+    else
+    {
+        /* 32bit */
+        mbw = USB_HOST_BITMBW_32;
+    }
+
+    return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_transaction_counter
+* Description  : Sets transaction counter by the argument(PIPEnTRN).
+*              : Clears transaction before setting to enable transaction counter setting.
+* Arguments    : uint16_t pipe     ; Pipe number
+*              : uint32_t bsize    : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+    uint16_t mxps;
+    uint16_t cnt;
+
+    if (bsize == 0)
+    {
+        return;
+    }
+
+    mxps = usb0_host_get_mxps(pipe);            /* Max Packet Size */
+
+    if ((bsize % mxps) == 0)
+    {
+        cnt = (uint16_t)(bsize / mxps);
+    }
+    else
+    {
+        cnt = (uint16_t)((bsize / mxps) + 1);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE1TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE2TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE3TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE4TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE5TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB200.PIPE9TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_transaction_counter
+* Description  : Clears the transaction counter by the argument.
+*              : After executing this function, the transaction counter is invalid.
+* Arguments    : uint16_t pipe     ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_transaction_counter (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_stop_transfer
+* Description  : Stops the USB transfer in the pipe specified by the argument.
+*              : After stopping the USB transfer, clears the buffer allocated in
+*              : the pipe.
+*              : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0;
+*              : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+*              : in the corresponding pipe becomes invalid. Sequence bit is also
+*              : cleared.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_stop_transfer (uint16_t pipe)
+{
+    uint16_t usefifo;
+    uint32_t remain;
+
+    usb0_host_set_pid_nak(pipe);
+
+    usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            usb0_host_clear_transaction_counter(pipe);
+            USB200.D0FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            usb0_host_clear_transaction_counter(pipe);
+            USB200.D1FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            remain = Userdef_USB_usb0_host_stop_dma0();
+            usb0_host_dma_stop_d0(pipe, remain);
+            usb0_host_clear_transaction_counter(pipe);
+            USB200.D0FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            remain = Userdef_USB_usb0_host_stop_dma1();
+            usb0_host_dma_stop_d1(pipe, remain);
+            usb0_host_clear_transaction_counter(pipe);
+            USB200.D1FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        default:
+            usb0_host_clear_transaction_counter(pipe);
+            USB200.CFIFOCTR =  USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+    }
+
+    /* Interrupt of pipe set is disabled */
+    usb0_host_disable_brdy_int(pipe);
+    usb0_host_disable_nrdy_int(pipe);
+    usb0_host_disable_bemp_int(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb0_host_aclrm(pipe);
+#endif
+    usb0_host_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_dfacc_d0
+* Description  : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments    : uint16_t mbw     ; MBW
+*              : uint16_t count   ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_host_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+    uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                        0,
+                        USB_DnFBCFG_DFACC_SHIFT,
+                        USB_DnFBCFG_DFACC);
+    RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                        0,
+                        USB_DnFBCFG_TENDE_SHIFT,
+                        USB_DnFBCFG_TENDE);
+    dfacc = 0;
+#else
+    if (mbw == USB_HOST_BITMBW_32)
+    {
+        if ((count % 32) == 0)
+        {
+            /* 32byte transfer */
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                2,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 2;
+        }
+        else if ((count % 16) == 0)
+        {
+            /* 16byte transfer */
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                1,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 1;
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 0;
+        }
+    }
+    else if (mbw == USB_HOST_BITMBW_16)
+    {
+        RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+#endif
+
+    return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_dfacc_d1
+* Description  : Sets the DFACC setting value in D1FIFO using the transfer size.
+* Arguments    : uint16_t mbw     ; MBW
+*              : uint16_t count   ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_host_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+    uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                        0,
+                        USB_DnFBCFG_DFACC_SHIFT,
+                        USB_DnFBCFG_DFACC);
+    RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                        0,
+                        USB_DnFBCFG_TENDE_SHIFT,
+                        USB_DnFBCFG_TENDE);
+    dfacc = 0;
+#else
+    if (mbw == USB_HOST_BITMBW_32)
+    {
+        if ((count % 32) == 0)
+        {
+            /* 32byte transfer */
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                2,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 2;
+        }
+        else if ((count % 16) == 0)
+        {
+            /* 16byte transfer */
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                1,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 1;
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 0;
+        }
+    }
+    else if (mbw == USB_HOST_BITMBW_16)
+    {
+        RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+#endif
+
+    return dfacc;
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/common/usb0_host_dma.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,355 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+/* #include "usb0_host_dmacdrv.h" */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb0_host_dmaint(uint16_t fifo);
+static void usb0_host_dmaint_buf2fifo(uint16_t pipe);
+static void usb0_host_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_stop_d0
+* Description  : D0FIFO DMA stop
+* Arguments    : uint16_t pipe     : pipe number
+*              : uint32_t remain   : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+    uint16_t dtln;
+    uint16_t dfacc;
+    uint16_t buffer;
+    uint16_t sds_b = 1;
+
+    dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+    if (dfacc == 2)
+    {
+        sds_b = 32;
+    }
+    else if (dfacc == 1)
+    {
+        sds_b = 16;
+    }
+    else
+    {
+        if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 2)
+        {
+            sds_b = 4;
+        }
+        else if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 1)
+        {
+            sds_b = 2;
+        }
+        else
+        {
+            sds_b = 1;
+        }
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+        {
+            buffer = USB200.D0FIFOCTR;
+            dtln   = (buffer & USB_HOST_BITDTLN);
+
+            if ((dtln % sds_b) != 0)
+            {
+                remain += (sds_b - (dtln % sds_b));
+            }
+            g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain);
+            g_usb0_host_data_count[pipe]   = remain;
+        }
+    }
+
+    RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+                        0,
+                        USB_DnFIFOSEL_DREQE_SHIFT,
+                        USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_stop_d1
+* Description  : D1FIFO DMA stop
+* Arguments    : uint16_t pipe     : pipe number
+*              : uint32_t remain   : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+    uint16_t dtln;
+    uint16_t dfacc;
+    uint16_t buffer;
+    uint16_t sds_b = 1;
+
+    dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+    if (dfacc == 2)
+    {
+        sds_b = 32;
+    }
+    else if (dfacc == 1)
+    {
+        sds_b = 16;
+    }
+    else
+    {
+        if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 2)
+        {
+            sds_b = 4;
+        }
+        else if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 1)
+        {
+            sds_b = 2;
+        }
+        else
+        {
+            sds_b = 1;
+        }
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+        {
+            buffer = USB200.D1FIFOCTR;
+            dtln   = (buffer & USB_HOST_BITDTLN);
+
+            if ((dtln % sds_b) != 0)
+            {
+                remain += (sds_b - (dtln % sds_b));
+            }
+            g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain);
+            g_usb0_host_data_count[pipe]   = remain;
+        }
+    }
+
+    RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+                        0,
+                        USB_DnFIFOSEL_DREQE_SHIFT,
+                        USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_interrupt_d0fifo
+* Description  : This function is DMA interrupt handler entry.
+*              : Execute usb1_host_dmaint() after disabling DMA interrupt in this function.
+*              : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is
+*              : specified by dma->fifo.
+*              : Register this function as DMA complete interrupt.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+    usb0_host_dmaint(USB_HOST_D0FIFO);
+    g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_interrupt_d1fifo
+* Description  : This function is DMA interrupt handler entry.
+*              : Execute usb0_host_dmaint() after disabling DMA interrupt in this function.
+*              : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is
+*              : specified by dma->fifo.
+*              : Register this function as DMA complete interrupt.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+    usb0_host_dmaint(USB_HOST_D1FIFO);
+    g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint
+* Description  : This function is DMA transfer end interrupt
+* Arguments    : uint16_t fifo  ; fifo number
+*              :                ;  USB_HOST_D0FIFO
+*              :                ;  USB_HOST_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint (uint16_t fifo)
+{
+    uint16_t pipe;
+
+    pipe = g_usb0_host_DmaPipe[fifo];
+
+    if (g_usb0_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO)
+    {
+        usb0_host_dmaint_buf2fifo(pipe);
+    }
+    else
+    {
+        usb0_host_dmaint_fifo2buf(pipe);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint_fifo2buf
+* Description  : Executes read completion from FIFO by DMAC.
+* Arguments    : uint16_t pipe       : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint_fifo2buf (uint16_t pipe)
+{
+    uint32_t remain;
+    uint16_t useport;
+
+    if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+    {
+        useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+        if (useport == USB_HOST_D0FIFO_DMA)
+        {
+            remain = Userdef_USB_usb0_host_stop_dma0();
+            usb0_host_dma_stop_d0(pipe, remain);
+
+            if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+            {
+                if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND)
+                {
+                    USB200.D0FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+                else
+                {
+                    usb0_host_enable_brdy_int(pipe);
+                }
+            }
+        }
+        else
+        {
+            remain = Userdef_USB_usb0_host_stop_dma1();
+            usb0_host_dma_stop_d1(pipe, remain);
+
+            if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+            {
+                if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND)
+                {
+                    USB200.D1FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+                else
+                {
+                    usb0_host_enable_brdy_int(pipe);
+                }
+            }
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint_buf2fifo
+* Description  : Executes write completion in FIFO by DMAC.
+* Arguments    : uint16_t pipe     : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint_buf2fifo (uint16_t pipe)
+{
+    uint16_t useport;
+    uint32_t remain;
+
+    useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    if (useport == USB_HOST_D0FIFO_DMA)
+    {
+        remain = Userdef_USB_usb0_host_stop_dma0();
+        usb0_host_dma_stop_d0(pipe, remain);
+
+        if (g_usb0_host_DmaBval[USB_HOST_D0FIFO] != 0)
+        {
+            RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);
+        }
+    }
+    else
+    {
+        remain = Userdef_USB_usb0_host_stop_dma1();
+        usb0_host_dma_stop_d1(pipe, remain);
+
+        if (g_usb0_host_DmaBval[USB_HOST_D1FIFO] != 0)
+        {
+            RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);
+        }
+    }
+
+    usb0_host_enable_bemp_int(pipe);
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/common/usb0_host_intrn.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,285 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_brdy_int
+* Description  : Executes BRDY interrupt(USB_HOST_PIPE1-9).
+*              : According to the pipe that interrupt is generated in,
+*              : reads/writes buffer allocated in the pipe.
+*              : This function is executed in the BRDY interrupt handler.
+*              : This function clears BRDY interrupt status and BEMP interrupt
+*              : status.
+* Arguments    : uint16_t status       ; BRDYSTS Register Value
+*              : uint16_t int_enb      ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_brdy_int (uint16_t status, uint16_t int_enb)
+{
+    uint32_t int_sense = 0;
+    uint16_t pipe;
+    uint16_t pipebit;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        pipebit = g_usb0_host_bit_set[pipe];
+
+        if ((status & pipebit) && (int_enb & pipebit))
+        {
+            USB200.BRDYSTS = (uint16_t)~pipebit;
+            USB200.BEMPSTS = (uint16_t)~pipebit;
+
+            if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+            {
+                if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY)
+                {
+                    usb0_host_dma_interrupt_d0fifo(int_sense);
+                }
+
+                if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+                {
+                    usb0_host_read_dma(pipe);
+                    usb0_host_disable_brdy_int(pipe);
+                }
+                else
+                {
+                    USB200.D0FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+            }
+            else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA)
+            {
+                if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY)
+                {
+                    usb0_host_dma_interrupt_d1fifo(int_sense);
+                }
+
+                if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+                {
+                    usb0_host_read_dma(pipe);
+                    usb0_host_disable_brdy_int(pipe);
+                }
+                else
+                {
+                    USB200.D1FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+            }
+            else
+            {
+                if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+                {
+                    usb0_host_read_buffer(pipe);
+                }
+                else
+                {
+                    usb0_host_write_buffer(pipe);
+                }
+            }
+#if(1) /* ohci_wrapp */
+            switch (g_usb0_host_pipe_status[pipe])
+            {
+                case USB_HOST_PIPE_DONE:
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+                break;
+                case USB_HOST_PIPE_NORES:
+                case USB_HOST_PIPE_STALL:
+                case USB_HOST_PIPE_ERROR:
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+                break;
+                default:
+                    /* Do Nothing */
+                break;
+            }
+#endif
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_nrdy_int
+* Description  : Executes NRDY interrupt(USB_HOST_PIPE1-9).
+*              : Checks NRDY interrupt cause by PID. When the cause if STALL,
+*              : regards the pipe state as STALL and ends the processing.
+*              : Then the cause is not STALL, increments the error count to
+*              : communicate again. When the error count is 3, determines
+*              : the pipe state as USB_HOST_PIPE_NORES and ends the processing.
+*              : This function is executed in the NRDY interrupt handler.
+*              : This function clears NRDY interrupt status.
+* Arguments    : uint16_t status       ; NRDYSTS Register Value
+*              : uint16_t int_enb      ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+    uint16_t pid;
+    uint16_t pipe;
+    uint16_t bitcheck;
+
+    bitcheck = (uint16_t)(status & int_enb);
+
+    USB200.NRDYSTS = (uint16_t)~status;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe])
+        {
+            if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+                                    USB_SYSCFG_DCFM_SHIFT,
+                                    USB_SYSCFG_DCFM) == 1)
+            {
+                if (g_usb0_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT)
+                {
+                    pid = usb0_host_get_pid(pipe);
+
+                    if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+                    {
+                        g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+                        ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+                    }
+                    else
+                    {
+#if(1) /* ohci_wrapp */
+                        g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+                        ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING);
+#else
+                        g_usb0_host_PipeIgnore[pipe]++;
+
+                        if (g_usb0_host_PipeIgnore[pipe] == 3)
+                        {
+                            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+                        }
+                        else
+                        {
+                            usb0_host_set_pid_buf(pipe);
+                        }
+#endif
+                    }
+                }
+            }
+            else
+            {
+                /* USB Function */
+            }
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_bemp_int
+* Description  : Executes BEMP interrupt(USB_HOST_PIPE1-9).
+* Arguments    : uint16_t status       ; BEMPSTS Register Value
+*              : uint16_t int_enb      ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_bemp_int (uint16_t status, uint16_t int_enb)
+{
+    uint16_t pid;
+    uint16_t pipe;
+    uint16_t bitcheck;
+    uint16_t inbuf;
+
+    bitcheck = (uint16_t)(status & int_enb);
+
+    USB200.BEMPSTS = (uint16_t)~status;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe])
+        {
+            pid = usb0_host_get_pid(pipe);
+
+            if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+            {
+                g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+                ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+            }
+            else
+            {
+                inbuf = usb0_host_get_inbuf(pipe);
+
+                if (inbuf == 0)
+                {
+                    usb0_host_disable_bemp_int(pipe);
+                    usb0_host_set_pid_nak(pipe);
+                    g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#if(1) /* ohci_wrapp */
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+#endif
+                }
+            }
+        }
+    }
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/common/usb0_host_lib.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1580 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "VKRZA1H.h"            /* INTC Driver Header   */
+#else
+#include "devdrv_intc.h"        /* INTC Driver Header   */
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_brdy_int
+* Description  : Enables BRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_brdy_int (uint16_t pipe)
+{
+    /* enable brdy interrupt */
+    USB200.BRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_brdy_int
+* Description  : Disables BRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After disabling BRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_brdy_int (uint16_t pipe)
+{
+    /* disable brdy interrupt */
+    USB200.BRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_brdy_sts
+* Description  : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_brdy_sts (uint16_t pipe)
+{
+    /* clear brdy status */
+    USB200.BRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_bemp_int
+* Description  : Enables BEMP interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BEMP, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_bemp_int (uint16_t pipe)
+{
+    /* enable bemp interrupt */
+    USB200.BEMPENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_bemp_int
+* Description  : Disables BEMP interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BEMP, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_bemp_int (uint16_t pipe)
+{
+    /* disable bemp interrupt */
+    USB200.BEMPENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_bemp_sts
+* Description  : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_bemp_sts (uint16_t pipe)
+{
+    /* clear bemp status */
+    USB200.BEMPSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_nrdy_int
+* Description  : Enables NRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling NRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe             ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_nrdy_int (uint16_t pipe)
+{
+    /* enable nrdy interrupt */
+    USB200.NRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_nrdy_int
+* Description  : Disables NRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After disabling NRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_nrdy_int (uint16_t pipe)
+{
+    /* disable nrdy interrupt */
+    USB200.NRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_nrdy_sts
+* Description  : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_nrdy_sts (uint16_t pipe)
+{
+    /* clear nrdy status */
+    USB200.NRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_is_hispeed
+* Description  : Returns the result of USB reset hand shake (RHST) as
+*              : return value.
+* Arguments    : none
+* Return Value : USB_HOST_HIGH_SPEED  ; Hi-Speed
+*              : USB_HOST_FULL_SPEED  ; Full-Speed
+*              : USB_HOST_LOW_SPEED   ; Low-Speed
+*              : USB_HOST_NON_SPEED   ; error
+*******************************************************************************/
+uint16_t usb0_host_is_hispeed (void)
+{
+    uint16_t rhst;
+    uint16_t speed;
+
+    rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+                                USB_DVSTCTR0_RHST_SHIFT,
+                                USB_DVSTCTR0_RHST);
+    if (rhst == USB_HOST_HSMODE)
+    {
+        speed = USB_HOST_HIGH_SPEED;
+    }
+    else if (rhst == USB_HOST_FSMODE)
+    {
+        speed = USB_HOST_FULL_SPEED;
+    }
+    else if (rhst == USB_HOST_LSMODE)
+    {
+        speed = USB_HOST_LOW_SPEED;
+    }
+    else
+    {
+        speed = USB_HOST_NON_SPEED;
+    }
+
+    return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_is_hispeed_enable
+* Description  : Returns the USB High-Speed connection enabled status as
+*              : return value.
+* Arguments    : none
+* Return Value : USB_HOST_YES : Hi-Speed Enable
+*              : USB_HOST_NO  : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb0_host_is_hispeed_enable (void)
+{
+    uint16_t ret;
+
+    ret = USB_HOST_NO;
+
+    if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+                                USB_SYSCFG_HSE_SHIFT,
+                                USB_SYSCFG_HSE) == 1)
+    {
+        ret = USB_HOST_YES;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_buf
+* Description  : Enables communicaqtion in the pipe specified by the argument
+*              : (BUF).
+* Arguments    : uint16_t pipe             ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_buf (uint16_t pipe)
+{
+    uint16_t pid;
+
+    pid = usb0_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_STALL2)
+    {
+        usb0_host_set_pid_nak(pipe);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                USB_HOST_PID_BUF,
+                                USB_DCPCTR_PID_SHIFT,
+                                USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_9_PID_SHIFT,
+                                USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_nak
+* Description  : Disables communication (NAK) in the pipe specified by the argument.
+*              : When the pipe status was enabling communication (BUF) before
+*              : executing before executing this function, waits in the software
+*              : until the pipe becomes ready after setting disabled.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_nak (uint16_t pipe)
+{
+    uint16_t pid;
+    uint16_t pbusy;
+    uint32_t loop;
+
+    pid = usb0_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_STALL2)
+    {
+        usb0_host_set_pid_stall(pipe);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                USB_HOST_PID_NAK,
+                                USB_DCPCTR_PID_SHIFT,
+                                USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_9_PID_SHIFT,
+                                USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+        break;
+    }
+
+    if (pid == USB_HOST_PID_BUF)
+    {
+        for (loop = 0; loop < 200; loop++)
+        {
+            switch (pipe)
+            {
+                case USB_HOST_PIPE0:
+                    pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR,
+                                                USB_DCPCTR_PBUSY_SHIFT,
+                                                USB_DCPCTR_PBUSY);
+                break;
+
+                case USB_HOST_PIPE1:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE2:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE3:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE4:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE5:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE6:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE7:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE8:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE9:
+                    pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+                                                USB_PIPEnCTR_9_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_9_PBUSY);
+                break;
+
+                default:
+                    pbusy = 1;
+                break;
+            }
+
+            if (pbusy == 0)
+            {
+                break;
+            }
+
+            Userdef_USB_usb0_host_delay_500ns();
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_stall
+* Description  : Disables communication (STALL) in the pipe specified by the
+*              : argument.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_stall (uint16_t pipe)
+{
+    uint16_t pid;
+
+    pid = usb0_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_BUF)
+    {
+        switch (pipe)
+        {
+            case USB_HOST_PIPE0:
+                RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+            break;
+
+            case USB_HOST_PIPE1:
+                RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE2:
+                RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE3:
+                RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE4:
+                RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE5:
+                RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE6:
+                RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE7:
+                RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE8:
+                RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE9:
+                RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+            break;
+
+            default:
+            break;
+        }
+    }
+    else
+    {
+        switch (pipe)
+        {
+            case USB_HOST_PIPE0:
+                RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+            break;
+
+            case USB_HOST_PIPE1:
+                RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE2:
+                RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE3:
+                RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE4:
+                RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE5:
+                RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE6:
+                RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE7:
+                RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE8:
+                RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE9:
+                RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+            break;
+
+            default:
+            break;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_pid_stall
+* Description  : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_pid_stall (uint16_t pipe)
+{
+    usb0_host_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_pid
+* Description  : Returns the pipe state specified by the argument.
+* Arguments    : uint16_t pipe          ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb0_host_get_pid (uint16_t pipe)
+{
+    uint16_t pid;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            pid = RZA_IO_RegRead_16(&USB200.DCPCTR,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+            pid = 0;
+        break;
+    }
+
+    return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_csclr
+* Description  : CSPLIT status clear setting of sprit transaction in specified
+*              : pipe is performed.
+*              : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+*              : in DCPCTR register are continuously changed (when the sequence
+*              : toggle bit of data PID is continuously changed over two or more pipes),
+*              : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+*              : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+*              : In addition, both bits should be operated after PID is set to NAK.
+*              : However, when it is set to the isochronous transfer as the transfer type
+*              : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments    : uint16_t pipe     ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_csclr (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                1,
+                                USB_DCPCTR_CSCLR_SHIFT,
+                                USB_DCPCTR_CSCLR);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_CSCLR_SHIFT,
+                                USB_PIPEnCTR_9_CSCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_sqclr
+* Description  : Sets the sequence bit of the pipe specified by the argument to
+*              : DATA0.
+* Arguments    : uint16_t pipe              ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_sqclr (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                1,
+                                USB_DCPCTR_SQCLR_SHIFT,
+                                USB_DCPCTR_SQCLR);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_SQCLR_SHIFT,
+                                USB_PIPEnCTR_9_SQCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_sqset
+* Description  : Sets the sequence bit of the pipe specified by the argument to
+*              : DATA1.
+* Arguments    : uint16_t pipe   ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_sqset (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB200.DCPCTR,
+                                1,
+                                USB_DCPCTR_SQSET_SHIFT,
+                                USB_DCPCTR_SQSET);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_SQSET_SHIFT,
+                                USB_PIPEnCTR_9_SQSET);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_sqmon
+* Description  : Toggle bit of specified pipe is obtained
+* Arguments    : uint16_t pipe   ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb0_host_get_sqmon (uint16_t pipe)
+{
+    uint16_t sqmon;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR,
+                                        USB_DCPCTR_SQMON_SHIFT,
+                                        USB_DCPCTR_SQMON);
+        break;
+
+        case USB_HOST_PIPE1:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE2:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE3:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE4:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE5:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE6:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE7:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE8:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE9:
+            sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+                                        USB_PIPEnCTR_9_SQMON_SHIFT,
+                                        USB_PIPEnCTR_9_SQMON);
+        break;
+
+        default:
+            sqmon = 0;
+        break;
+    }
+
+    return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_aclrm
+* Description  : The buffer of specified pipe is initialized
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_aclrm (uint16_t pipe)
+{
+    usb0_host_set_aclrm(pipe);
+    usb0_host_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_aclrm
+* Description  : The auto buffer clear mode of specified pipe is enabled
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_aclrm (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_ACLRM_SHIFT,
+                                USB_PIPEnCTR_9_ACLRM);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clr_aclrm
+* Description  : The auto buffer clear mode of specified pipe is enabled
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clr_aclrm (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+                                0,
+                                USB_PIPEnCTR_9_ACLRM_SHIFT,
+                                USB_PIPEnCTR_9_ACLRM);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_inbuf
+* Description  : Returns INBUFM of the pipe specified by the argument.
+* Arguments    : uint16_t pipe             ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb0_host_get_inbuf (uint16_t pipe)
+{
+    uint16_t inbuf;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE1:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE2:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE3:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE4:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE5:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE6:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE7:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE8:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE9:
+            inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+                                    USB_PIPEnCTR_9_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_9_INBUFM);
+        break;
+
+        default:
+            inbuf = 0;
+        break;
+    }
+
+    return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_setting_interrupt
+* Description  : Sets the USB module interrupt level.
+* Arguments    : uint8_t level ; interrupt level
+* Return Value : none
+*******************************************************************************/
+void usb0_host_setting_interrupt (uint8_t level)
+{
+#if(1) /* ohci_wrapp */
+    IRQn_Type d0fifo_dmaintid;
+    IRQn_Type d1fifo_dmaintid;
+
+    InterruptHandlerRegister(USBI0_IRQn, usb0_host_interrupt);
+    GIC_SetPriority(USBI0_IRQn, level);
+    GIC_EnableIRQ(USBI0_IRQn);
+
+    d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d0fifo_dmaintid();
+
+    if (d0fifo_dmaintid != 0xFFFF)
+    {
+        InterruptHandlerRegister(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo);
+        GIC_SetPriority(d0fifo_dmaintid, level);
+        GIC_EnableIRQ(d0fifo_dmaintid);
+    }
+
+    d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d1fifo_dmaintid();
+
+    if (d1fifo_dmaintid != 0xFFFF)
+    {
+        InterruptHandlerRegister(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo);
+        GIC_SetPriority(d1fifo_dmaintid, level);
+        GIC_EnableIRQ(d1fifo_dmaintid);
+    }
+#else
+    uint16_t d0fifo_dmaintid;
+    uint16_t d1fifo_dmaintid;
+
+    R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_host_interrupt);
+    R_INTC_SetPriority(INTC_ID_USBI0, level);
+    R_INTC_Enable(INTC_ID_USBI0);
+
+    d0fifo_dmaintid = Userdef_USB_usb0_host_d0fifo_dmaintid();
+
+    if (d0fifo_dmaintid != 0xFFFF)
+    {
+        R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo);
+        R_INTC_SetPriority(d0fifo_dmaintid, level);
+        R_INTC_Enable(d0fifo_dmaintid);
+    }
+
+    d1fifo_dmaintid = Userdef_USB_usb0_host_d1fifo_dmaintid();
+
+    if (d1fifo_dmaintid != 0xFFFF)
+    {
+        R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo);
+        R_INTC_SetPriority(d1fifo_dmaintid, level);
+        R_INTC_Enable(d1fifo_dmaintid);
+    }
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_reset_module
+* Description  : Initializes the USB module.
+*              : Enables providing clock to the USB module.
+*              : Sets USB bus wait register.
+* Arguments    : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ
+*              :                    ; 12MHz ; USBHCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb0_host_reset_module (uint16_t clockmode)
+{
+    if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+                                USB_SYSCFG_UPLLE_SHIFT,
+                                USB_SYSCFG_UPLLE) == 1)
+    {
+        if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode)
+        {
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                0,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            USB200.SYSCFG0 = 0;
+            USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+            Userdef_USB_usb0_host_delay_xms(1);
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                1,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                0,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            Userdef_USB_usb0_host_delay_xms(1);
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                1,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+        }
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                            0,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+        USB200.SYSCFG0 = 0;
+        USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+        Userdef_USB_usb0_host_delay_xms(1);
+        RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                            1,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+    }
+
+    USB200.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_buf_size
+* Description  : Obtains pipe buffer size specified by the argument and
+*              : maximum packet size of the USB device in use.
+*              : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum
+*              : packet size of the USB device using the corresponding pipe.
+*              : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the
+*              : corresponding pipe is in continuous transfer mode,
+*              : obtains the buffer size allocated in the corresponcing pipe,
+*              : when incontinuous transfer, obtains maximum packet size.
+* Arguments    : uint16_t ; pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb0_host_get_buf_size (uint16_t pipe)
+{
+    uint16_t size;
+    uint16_t bufsize;
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+                                USB_DCPMAXP_MXPS_SHIFT,
+                                USB_DCPMAXP_MXPS);
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+        {
+            bufsize = RZA_IO_RegRead_16(&g_usb0_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+            size    = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF);
+        }
+        else
+        {
+            size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+        }
+    }
+    return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_mxps
+* Description  : Obtains maximum packet size of the USB device using the pipe
+*              : specified by the argument.
+* Arguments    : uint16_t ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb0_host_get_mxps (uint16_t pipe)
+{
+    uint16_t size;
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+                                USB_DCPMAXP_MXPS_SHIFT,
+                                USB_DCPMAXP_MXPS);
+    }
+    else
+    {
+        size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+    }
+
+    return size;
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/host/usb0_host_controlrw.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,434 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlTransStart
+* Description  : Executes USB control transfer.
+* Arguments    : uint16_t devadr ; device address
+*              : uint16_t Req   ; bmRequestType & bRequest
+*              : uint16_t Val   ; wValue
+*              : uint16_t Indx  ; wIndex
+*              : uint16_t Len   ; wLength
+*              : uint8_t  *Buf  ; Data buffer
+* Return Value : DEVDRV_SUCCESS     ;   SUCCESS
+*              : DEVDRV_ERROR       ;   ERROR
+*******************************************************************************/
+int32_t usb0_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val,
+                            uint16_t Indx, uint16_t Len, uint8_t * Buf)
+{
+    if (g_usb0_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED)
+    {
+        RZA_IO_RegWrite_16(&USB200.SOFCFG,
+                            1,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB200.SOFCFG,
+                            0,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+
+    USB200.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb0_host_default_max_packet[devadr]);
+
+    if (g_usb0_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE)
+    {
+        g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+        g_usb0_host_PipeIgnore[USB_HOST_PIPE0]  = 0;                    /* Ignore count clear */
+        g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+
+        if (Len == 0)
+        {
+            g_usb0_host_CmdStage |= USB_HOST_MODE_NO_DATA;              /* No-data Control */
+        }
+        else
+        {
+            if ((Req & 0x0080) != 0)
+            {
+                g_usb0_host_CmdStage |= USB_HOST_MODE_READ;             /* Control Read */
+            }
+            else
+            {
+                g_usb0_host_CmdStage |= USB_HOST_MODE_WRITE;            /* Control Write */
+            }
+        }
+
+        g_usb0_host_SavReq  = Req;                                      /* save request */
+        g_usb0_host_SavVal  = Val;
+        g_usb0_host_SavIndx = Indx;
+        g_usb0_host_SavLen  = Len;
+    }
+    else
+    {
+        if ((g_usb0_host_SavReq  != Req)  || (g_usb0_host_SavVal != Val)
+         || (g_usb0_host_SavIndx != Indx) || (g_usb0_host_SavLen != Len))
+        {
+            return DEVDRV_ERROR;
+        }
+    }
+
+    switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+    {
+        /* --------------- SETUP STAGE --------------- */
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE):
+            usb0_host_SetupStage(Req, Val, Indx, Len);
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE):                /* goto next stage */
+            g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0;                 /* Ignore count clear */
+            switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+            {
+                case USB_HOST_MODE_WRITE:
+                    g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
+                break;
+
+                case USB_HOST_MODE_READ:
+                    g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
+                break;
+
+                case USB_HOST_MODE_NO_DATA:
+                    g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                break;
+
+                default:
+                break;
+            }
+            g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES):
+            if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+            }
+        break;
+
+        /* --------------- DATA STAGE --------------- */
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE):
+            switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+            {
+                case USB_HOST_MODE_WRITE:
+                    usb0_host_CtrlWriteStart((uint32_t)Len, Buf);
+                break;
+
+                case USB_HOST_MODE_READ:
+                    usb0_host_CtrlReadStart((uint32_t)Len, Buf);
+                break;
+
+                default:
+                break;
+            }
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE):                         /* goto next stage */
+            g_usb0_host_PipeIgnore[USB_HOST_PIPE0]  = 0;                        /* Ignore count clear */
+            g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+            g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES):
+            if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+                usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+                usb0_host_set_pid_buf(USB_HOST_PIPE0);
+            }
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL):
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+        break;
+
+        /* --------------- STATUS STAGE --------------- */
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE):
+            usb0_host_StatusStage();
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE):                       /* end of Control transfer */
+            usb0_host_set_pid_nak(USB_HOST_PIPE0);
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE;       /* exit DONE */
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES):
+            if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+                usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+                usb0_host_set_pid_buf(USB_HOST_PIPE0);
+            }
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL):
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+        break;
+
+        default:
+        break;
+    }
+
+    if (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)
+    {
+        RZA_IO_RegWrite_16(&USB200.SOFCFG,
+                            0,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_SetupStage
+* Description  : Executes USB control transfer/set up stage.
+* Arguments    : uint16_t Req           ; bmRequestType & bRequest
+*              : uint16_t Val           ; wValue
+*              : uint16_t Indx          ; wIndex
+*              : uint16_t Len           ; wLength
+* Return Value : none
+*******************************************************************************/
+void usb0_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len)
+{
+    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    USB200.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN);  /* Status Clear */
+    USB200.USBREQ  = Req;
+    USB200.USBVAL  = Val;
+    USB200.USBINDX = Indx;
+    USB200.USBLENG = Len;
+    USB200.DCPCTR  = USB_HOST_BITSUREQ;                                 /* PID=NAK & Send Setup */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_StatusStage
+* Description  : Executes USB control transfer/status stage.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_StatusStage (void)
+{
+    uint8_t Buf1[16];
+
+    switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+    {
+        case USB_HOST_MODE_READ:
+            usb0_host_CtrlWriteStart((uint32_t)0, (uint8_t *)&Buf1);
+        break;
+
+        case USB_HOST_MODE_WRITE:
+            usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1);
+        break;
+
+        case USB_HOST_MODE_NO_DATA:
+            usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlWriteStart
+* Description  : Executes USB control transfer/data stage(write).
+* Arguments    : uint32_t Bsize     ; Data Size
+*              : uint8_t  *Table    ; Data Table Address
+* Return Value : USB_HOST_WRITESHRT ; End of data write
+*              : USB_HOST_WRITEEND  ; End of data write (not null)
+*              : USB_HOST_WRITING   ; Continue of data write
+*              : USB_HOST_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb0_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table)
+{
+    uint16_t EndFlag_K;
+    uint16_t mbw;
+
+    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    usb0_host_set_pid_nak(USB_HOST_PIPE0);                              /* Set NAK */
+    g_usb0_host_data_count[USB_HOST_PIPE0]   = Bsize;                   /* Transfer size set */
+    g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table;                   /* Transfer address set */
+
+    USB200.DCPCTR = USB_HOST_BITSQSET;                                  /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+    Userdef_USB_usb0_host_delay_10us(3);
+#endif
+    RZA_IO_RegWrite_16(&USB200.DCPCFG,
+                        1,
+                        USB_DCPCFG_DIR_SHIFT,
+                        USB_DCPCFG_DIR);
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw);
+    USB200.CFIFOCTR = USB_HOST_BITBCLR;                                 /* Buffer Clear */
+
+    usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+    EndFlag_K   = usb0_host_write_buffer_c(USB_HOST_PIPE0);
+    /* Host Control sequence */
+    switch (EndFlag_K)
+    {
+        case USB_HOST_WRITESHRT:                                        /* End of data write */
+            g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+            usb0_host_enable_nrdy_int(USB_HOST_PIPE0);                  /* Error (NORES or STALL) */
+            usb0_host_enable_bemp_int(USB_HOST_PIPE0);                  /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_WRITEEND:                                         /* End of data write (not null) */
+        case USB_HOST_WRITING:                                          /* Continue of data write */
+            usb0_host_enable_nrdy_int(USB_HOST_PIPE0);                  /* Error (NORES or STALL) */
+            usb0_host_enable_bemp_int(USB_HOST_PIPE0);                  /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_FIFOERROR:                                        /* FIFO access error */
+        break;
+
+        default:
+        break;
+    }
+    usb0_host_set_pid_buf(USB_HOST_PIPE0);                              /* Set BUF */
+    return (EndFlag_K);                                                 /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlReadStart
+* Description  : Executes USB control transfer/data stage(read).
+* Arguments    : uint32_t Bsize     ; Data Size
+*              : uint8_t  *Table    ; Data Table Address
+* Return Value : none
+*******************************************************************************/
+void usb0_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table)
+{
+    uint16_t mbw;
+
+    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    usb0_host_set_pid_nak(USB_HOST_PIPE0);                  /* Set NAK */
+    g_usb0_host_data_count[USB_HOST_PIPE0]   = Bsize;       /* Transfer size set */
+    g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table;       /* Transfer address set */
+
+    USB200.DCPCTR = USB_HOST_BITSQSET;                      /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+    Userdef_USB_usb0_host_delay_10us(3);
+#endif
+    RZA_IO_RegWrite_16(&USB200.DCPCFG,
+                        0,
+                        USB_DCPCFG_DIR_SHIFT,
+                        USB_DCPCFG_DIR);
+
+    mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
+    usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw);
+    USB200.CFIFOCTR = USB_HOST_BITBCLR;                     /* Buffer Clear */
+
+    usb0_host_enable_nrdy_int(USB_HOST_PIPE0);              /* Error (NORES or STALL) */
+    usb0_host_enable_brdy_int(USB_HOST_PIPE0);              /* Ok */
+    usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+    usb0_host_set_pid_buf(USB_HOST_PIPE0);                  /* Set BUF */
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/host/usb0_host_drv_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,889 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_drv_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_api_host_init
+* Description  : Initializes USB module in the USB host mode.
+*              : USB connection is executed when executing this function in
+*              : the states that USB device isconnected to the USB port.
+* Arguments    : uint8_t int_level  : USB Module interrupt level
+*              : USBU16  mode       : USB_HOST_HIGH_SPEED
+*                                   : USB_HOST_FULL_SPEED
+*              : uint16_t clockmode : USB Clock mode
+* Return Value : USB detach or attach
+*              :  USB_HOST_ATTACH
+*              :  USB_HOST_DETACH
+*******************************************************************************/
+uint16_t usb0_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+    uint16_t         connect;
+    volatile uint8_t dummy_buf;
+
+    CPG.STBCR7 &= 0xfd;                         /*The clock of USB0 modules is permitted */
+    dummy_buf   = CPG.STBCR7;                   /* (Dummy read) */
+
+    g_usb0_host_SupportUsbDeviceSpeed = mode;
+
+    usb0_host_setting_interrupt(int_level);
+    usb0_host_reset_module(clockmode);
+
+    g_usb0_host_bchg_flag   = USB_HOST_NO;
+    g_usb0_host_detach_flag = USB_HOST_NO;
+    g_usb0_host_attach_flag = USB_HOST_NO;
+
+    g_usb0_host_driver_state = USB_HOST_DRV_DETACHED;
+    g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+    usb0_host_InitModule();
+
+    connect = usb0_host_CheckAttach();
+
+    if (connect == USB_HOST_ATTACH)
+    {
+        g_usb0_host_attach_flag = USB_HOST_YES;
+    }
+    else
+    {
+        usb0_host_UsbDetach2();
+    }
+
+    return connect;
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb0_api_host_enumeration
+* Description  : Initializes USB module in the USB host mode.
+*              : USB connection is executed when executing this function in
+*              : the states that USB device isconnected to the USB port.
+* Arguments    : uint16_t devadr : device address
+* Return Value : DEVDRV_USBH_DETACH_ERR       : device detach
+*              : DEVDRV_SUCCESS               : device enumeration success
+*              : DEVDRV_ERROR                 : device enumeration error
+*******************************************************************************/
+int32_t usb0_api_host_enumeration (uint16_t devadr)
+{
+    int32_t  ret;
+    uint16_t driver_sts;
+
+    g_usb0_host_setUsbAddress = devadr;
+
+    while (1)
+    {
+        driver_sts = usb0_api_host_GetUsbDeviceState();
+
+        if (driver_sts == USB_HOST_DRV_DETACHED)
+        {
+            ret = DEVDRV_USBH_DETACH_ERR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+        {
+            ret = DEVDRV_SUCCESS;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_STALL)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_NORES)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+
+    if (driver_sts == USB_HOST_DRV_NORES)
+    {
+        while (1)
+        {
+            driver_sts = usb0_api_host_GetUsbDeviceState();
+
+            if (driver_sts == USB_HOST_DRV_DETACHED)
+            {
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_detach
+* Description  : USB detach routine
+* Arguments    : none
+* Return Value : USB_HOST_DETACH : USB detach
+*              : USB_HOST_ATTACH : USB attach
+*              : DEVDRV_ERROR    : error
+*******************************************************************************/
+int32_t usb0_api_host_detach (void)
+{
+    int32_t  ret;
+    uint16_t driver_sts;
+
+    while (1)
+    {
+        driver_sts = usb0_api_host_GetUsbDeviceState();
+
+        if (driver_sts == USB_HOST_DRV_DETACHED)
+        {
+            ret = USB_HOST_DETACH;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+        {
+            ret = USB_HOST_ATTACH;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_STALL)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_NORES)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+
+    if (driver_sts == USB_HOST_DRV_NORES)
+    {
+        while (1)
+        {
+            driver_sts = usb0_api_host_GetUsbDeviceState();
+
+            if (driver_sts == USB_HOST_DRV_DETACHED)
+            {
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_data_in
+* Description  : Executes USB transfer as data-in in the argument specified pipe.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Pipe         ; Pipe Number
+*              : uint32_t Size         ; Data Size
+*              : uint8_t  *data_buf    ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+    int32_t ret;
+
+    if (Pipe == USB_HOST_PIPE0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+    {
+        usb0_host_start_receive_transfer(Pipe, Size, data_buf);
+    }
+    else
+    {
+        return DEVDRV_ERROR;              /* Now pipe is busy */
+    }
+
+    /* waiting for completing routine           */
+    do
+    {
+        if (g_usb0_host_detach_flag == USB_HOST_YES)
+        {
+            break;
+        }
+
+        if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+        {
+            break;
+        }
+
+    } while (1);
+
+    if (g_usb0_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb0_host_pipe_status[Pipe])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    usb0_host_stop_transfer(Pipe);
+
+    g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_data_out
+* Description  : Executes USB transfer as data-out in the argument specified pipe.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Pipe         ; Pipe Number
+*              : uint32_t Size         ; Data Size
+*              : uint8_t  *data_buf    ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+    int32_t ret;
+
+    if (Pipe == USB_HOST_PIPE0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+    {
+        usb0_host_start_send_transfer(Pipe, Size, data_buf);
+    }
+    else
+    {
+        return DEVDRV_ERROR;              /* Now pipe is busy */
+    }
+
+    /* waiting for completing routine           */
+    do
+    {
+        if (g_usb0_host_detach_flag == USB_HOST_YES)
+        {
+            break;
+        }
+
+        if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+        {
+            break;
+        }
+
+    } while (1);
+
+    if (g_usb0_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb0_host_pipe_status[Pipe])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    usb0_host_stop_transfer(Pipe);
+
+    g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_control_transfer
+* Description  : Executes USB control transfer.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Req          ; bmRequestType & bRequest
+*              : uint16_t Val          ; wValue
+*              : uint16_t Indx         ; wIndex
+*              : uint16_t Len          ; wLength
+*              : uint8_t  *buf         ; Buffer
+* Return Value : DEVDRV_SUCCESS           ; success
+*              : DEVDRV_USBH_DETACH_ERR   ; device detach
+*              : DEVDRV_USBH_CTRL_COM_ERR ; device no response
+*              : DEVDRV_USBH_STALL        ; STALL
+*              : DEVDRV_ERROR             ; error
+*******************************************************************************/
+int32_t usb0_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx,
+                                                     uint16_t Len, uint8_t * Buf)
+{
+    int32_t  ret;
+
+    do
+    {
+        ret = usb0_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf);
+
+        if (ret == DEVDRV_SUCCESS)
+        {
+            if (g_usb0_host_detach_flag == USB_HOST_YES)
+            {
+                break;
+            }
+
+            if ((g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE)
+                && (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT))
+            {
+                break;
+            }
+        }
+        else
+        {
+            return DEVDRV_ERROR;
+        }
+    } while (1);
+
+    if (g_usb0_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb0_host_pipe_status[USB_HOST_PIPE0])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_CTRL_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_set_endpoint
+* Description  : Sets end point on the information specified in the argument.
+* Arguments    : uint16_t                devadr           ; device address
+*              : uint8_t                *configdescriptor ; device configration descriptor
+*              : USB_HOST_CFG_PIPETBL_t *user_table       ; pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb0_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor)
+{
+    uint16_t                ret;
+    uint32_t                end_point;
+    uint32_t                offset;
+    uint32_t                totalLength;
+    USB_HOST_CFG_PIPETBL_t * pipe_table;
+
+    /*  End Point Search */
+    end_point   = 0;
+    offset      = configdescriptor[0];
+    totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8));
+
+    do
+    {
+        if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC)
+        {
+            pipe_table = &user_table[end_point];
+
+            if (pipe_table->pipe_number == 0xffff)
+            {
+                break;
+            }
+
+            ret = usb0_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]);
+
+            if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT))
+            {
+                return DEVDRV_ERROR;
+            }
+
+            ++end_point;
+        }
+
+        /* Next End Point Search */
+        offset += configdescriptor[offset];
+
+    } while (offset < totalLength);
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_clear_endpoint
+* Description  : Clears the pipe definition table specified in the argument.
+* Arguments    : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb0_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table)
+{
+    uint16_t pipe;
+
+    for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+    {
+        if (user_table->pipe_number == 0xffff)
+        {
+            break;
+        }
+        user_table->pipe_cfg         &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+        user_table->pipe_max_pktsize  = 0;
+        user_table->pipe_cycle        = 0;
+
+        user_table++;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_clear_endpoint_pipe
+* Description  : Clears the pipe definition table specified in the argument.
+* Arguments    : uint16_t pipe_sel                  : Pipe Number
+*              : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb0_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table)
+{
+    uint16_t pipe;
+
+    for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+    {
+        if (user_table->pipe_number == 0xffff)
+        {
+            break;
+        }
+
+        if (user_table->pipe_number == pipe_sel)
+        {
+            user_table->pipe_cfg         &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+            user_table->pipe_max_pktsize  = 0;
+            user_table->pipe_cycle        = 0;
+            break;
+        }
+
+        user_table++;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_api_host_SetEndpointTable
+* Description  : Sets the end point on the information specified by the argument.
+* Arguments    : uint16_t devadr                    : device address
+*              : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+*              : uint8_t                *Table      : Endpoint descriptor
+* Return Value : USB_HOST_DIR_H_IN           ; IN endpoint
+*              : USB_HOST_DIR_H_OUT          ; OUT endpoint
+*              : USB_END_POINT_ERROR         ; error
+*******************************************************************************/
+uint16_t usb0_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table)
+{
+    uint16_t PipeCfg;
+    uint16_t PipeMaxp;
+    uint16_t pipe_number;
+    uint16_t ret;
+    uint16_t ret_flag = 0;                                          // avoid warning.
+
+    pipe_number = user_table->pipe_number;
+
+    if (Table[1] != USB_HOST_ENDPOINT_DESC)
+    {
+        return USB_END_POINT_ERROR;
+    }
+
+    switch (Table[3] & USB_HOST_EP_TYPE)
+    {
+        case USB_HOST_EP_CNTRL:
+            ret_flag =  USB_END_POINT_ERROR;
+        break;
+
+        case USB_HOST_EP_ISO:
+            if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_ISO;
+        break;
+
+        case USB_HOST_EP_BULK:
+            if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_BULK;
+        break;
+
+        case USB_HOST_EP_INT:
+            if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_INTERRUPT;
+        break;
+
+        default:
+            ret_flag = USB_END_POINT_ERROR;
+        break;
+    }
+
+    if (ret_flag == USB_END_POINT_ERROR)
+    {
+        return ret_flag;
+    }
+
+    /* Set pipe configuration table */
+    if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN)        /* IN(receive) */
+    {
+        if (PipeCfg == USB_HOST_ISO)
+        {
+            /* Transfer Type is ISO*/
+            PipeCfg |= USB_HOST_DIR_H_IN;
+
+            switch (user_table->fifo_port)
+            {
+                case USB_HOST_CUSE:
+                case USB_HOST_D0USE:
+                case USB_HOST_D1USE:
+                case USB_HOST_D0DMA:
+                case USB_HOST_D1DMA:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+                break;
+
+                default:
+                    ret_flag = USB_END_POINT_ERROR;
+                break;
+            }
+
+            if (ret_flag == USB_END_POINT_ERROR)
+            {
+                return ret_flag;
+            }
+        }
+        else
+        {
+            /* Transfer Type is BULK or INT */
+            PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN);             /* Compulsory SHTNAK */
+
+            switch (user_table->fifo_port)
+            {
+                case USB_HOST_CUSE:
+                case USB_HOST_D0USE:
+                case USB_HOST_D1USE:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+                break;
+
+                case USB_HOST_D0DMA:
+                case USB_HOST_D1DMA:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+#ifdef  __USB_DMA_BFRE_ENABLE__
+                    /* this routine cannnot be perfomred if read operation is executed in buffer size */
+                    PipeCfg |= USB_HOST_BFREON;
+#endif
+                break;
+
+                default:
+                    ret_flag = USB_END_POINT_ERROR;
+                break;
+            }
+
+            if (ret_flag == USB_END_POINT_ERROR)
+            {
+                return ret_flag;
+            }
+        }
+        ret = USB_HOST_PIPE_IN;
+    }
+    else                                                            /* OUT(send)    */
+    {
+        if (PipeCfg == USB_HOST_ISO)
+        {
+            /* Transfer Type is ISO*/
+            PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+        }
+        else
+        {
+            /* Transfer Type is BULK or INT */
+            PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+        }
+        PipeCfg |= USB_HOST_DIR_H_OUT;
+        ret = USB_HOST_PIPE_OUT;
+    }
+
+    switch (user_table->fifo_port)
+    {
+        case USB_HOST_CUSE:
+            g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE;
+        break;
+
+        case USB_HOST_D0USE:
+            g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE;
+        break;
+
+        case USB_HOST_D1USE:
+            g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE;
+        break;
+
+        case USB_HOST_D0DMA:
+            g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA;
+        break;
+
+        case USB_HOST_D1DMA:
+            g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA;
+        break;
+
+        default:
+            ret_flag = USB_END_POINT_ERROR;
+        break;
+    }
+
+    if (ret_flag == USB_END_POINT_ERROR)
+    {
+        return ret_flag;
+    }
+
+    /* Endpoint number set              */
+    PipeCfg  |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+    g_usb0_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+
+    /* Max packet size set              */
+    PipeMaxp  = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8));
+
+    if (PipeMaxp == 0u)
+    {
+        return USB_END_POINT_ERROR;
+    }
+
+    /* Set device address               */
+    PipeMaxp |= (uint16_t)(devadr << 12);
+
+    user_table->pipe_cfg         = PipeCfg;
+    user_table->pipe_max_pktsize = PipeMaxp;
+
+    usb0_host_resetEP(user_table);
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_resetEP
+* Description  : Sets the end point on the information specified by the argument.
+* Arguments    : USB_HOST_CFG_PIPETBL_t *tbl : pipe table
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl)
+{
+
+    uint16_t pipe;
+
+    /* Host pipe */
+    /* The pipe number of pipe definition table is obtained */
+    pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE);  /* Pipe Number */
+
+    /* FIFO port access pipe is set to initial value */
+    /* The connection with FIFO should be cut before setting the pipe */
+    if (RZA_IO_RegRead_16(&USB200.CFIFOSEL,
+                            USB_CFIFOSEL_CURPIPE_SHIFT,
+                            USB_CFIFOSEL_CURPIPE) == pipe)
+    {
+        usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL,
+                            USB_DnFIFOSEL_CURPIPE_SHIFT,
+                            USB_DnFIFOSEL_CURPIPE) == pipe)
+    {
+        usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL,
+                            USB_DnFIFOSEL_CURPIPE_SHIFT,
+                            USB_DnFIFOSEL_CURPIPE) == pipe)
+    {
+        usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    /* Interrupt of pipe set is disabled */
+    usb0_host_disable_brdy_int(pipe);
+    usb0_host_disable_nrdy_int(pipe);
+    usb0_host_disable_bemp_int(pipe);
+
+    /* Pipe to set is set to NAK */
+    usb0_host_set_pid_nak(pipe);
+
+    /* Pipe is set */
+    USB200.PIPESEL  = pipe;
+
+    USB200.PIPECFG  = tbl->pipe_cfg;
+    USB200.PIPEBUF  = tbl->pipe_buf;
+    USB200.PIPEMAXP = tbl->pipe_max_pktsize;
+    USB200.PIPEPERI = tbl->pipe_cycle;
+
+    g_usb0_host_pipecfg[pipe]  = tbl->pipe_cfg;
+    g_usb0_host_pipebuf[pipe]  = tbl->pipe_buf;
+    g_usb0_host_pipemaxp[pipe] = tbl->pipe_max_pktsize;
+    g_usb0_host_pipeperi[pipe] = tbl->pipe_cycle;
+
+    /* Sequence bit clear */
+    usb0_host_set_sqclr(pipe);
+
+    usb0_host_aclrm(pipe);
+    usb0_host_set_csclr(pipe);
+
+    /* Pipe window selection is set to unused */
+    USB200.PIPESEL = USB_HOST_PIPE0;
+
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb0_api_host_data_count
+* Description  : Get g_usb0_host_data_count[pipe]
+* Arguments    : uint16_t pipe        ; Pipe Number
+*              : uint32_t *data_count ; return g_usb0_data_count[pipe]
+* Return Value : DEVDRV_SUCCESS    ; success
+*              : DEVDRV_ERROR      ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_count (uint16_t pipe, uint32_t * data_count)
+{
+    if (pipe > USB_HOST_MAX_PIPE_NO)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    *data_count = g_usb0_host_PipeDataSize[pipe];
+
+    return DEVDRV_SUCCESS;
+}
+#endif
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/host/usb0_host_global.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+const uint16_t g_usb0_host_bit_set[16] =
+{
+    0x0001, 0x0002, 0x0004, 0x0008,
+    0x0010, 0x0020, 0x0040, 0x0080,
+    0x0100, 0x0200, 0x0400, 0x0800,
+    0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t  g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+uint8_t * g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+uint16_t  g_usb0_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb0_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb0_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1];
+uint32_t  g_usb0_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1];
+
+USB_HOST_DMA_t g_usb0_host_DmaInfo[2];
+
+uint16_t  g_usb0_host_DmaPipe[2];
+uint16_t  g_usb0_host_DmaBval[2];
+uint16_t  g_usb0_host_DmaStatus[2];
+
+uint16_t  g_usb0_host_driver_state;
+uint16_t  g_usb0_host_ConfigNum;
+uint16_t  g_usb0_host_CmdStage;
+uint16_t  g_usb0_host_bchg_flag;
+uint16_t  g_usb0_host_detach_flag;
+uint16_t  g_usb0_host_attach_flag;
+
+uint16_t  g_usb0_host_UsbAddress;
+uint16_t  g_usb0_host_setUsbAddress;
+uint16_t  g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+uint16_t  g_usb0_host_UsbDeviceSpeed;
+uint16_t  g_usb0_host_SupportUsbDeviceSpeed;
+
+uint16_t  g_usb0_host_SavReq;
+uint16_t  g_usb0_host_SavVal;
+uint16_t  g_usb0_host_SavIndx;
+uint16_t  g_usb0_host_SavLen;
+
+uint16_t  g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_init_pipe_status
+* Description  : Initialize pipe status.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_init_pipe_status (void)
+{
+    uint16_t loop;
+
+    g_usb0_host_ConfigNum = 0;
+
+    for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop)
+    {
+        g_usb0_host_pipe_status[loop]   = USB_HOST_PIPE_IDLE;
+        g_usb0_host_PipeDataSize[loop]  = 0;
+
+        /* pipe configuration in usb0_host_resetEP() */
+        g_usb0_host_pipecfg[loop]  = 0;
+        g_usb0_host_pipebuf[loop]  = 0;
+        g_usb0_host_pipemaxp[loop] = 0;
+        g_usb0_host_pipeperi[loop] = 0;
+    }
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/host/usb0_host_usbint.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,496 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_usbint.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_interrupt1(void);
+static void usb0_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb0_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb0_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_interrupt
+* Description  : Executes USB interrupt.
+*              : Register this function in the USB interrupt handler.
+*              : Set CFIF0 in the pipe set before the interrupt after executing
+*              : this function.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_interrupt (uint32_t int_sense)
+{
+    uint16_t savepipe1;
+    uint16_t savepipe2;
+    uint16_t buffer;
+
+    savepipe1 = USB200.CFIFOSEL;
+    savepipe2 = USB200.PIPESEL;
+    usb0_host_interrupt1();
+
+    /* Control transmission changes ISEL within interruption processing. */
+    /* For this reason, write return of ISEL cannot be performed. */
+    buffer = USB200.CFIFOSEL;
+    buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+    buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE);
+    USB200.CFIFOSEL = buffer;
+    USB200.PIPESEL = savepipe2;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_interrupt1
+* Description  : Execue the USB interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_interrupt1 (void)
+{
+    uint16_t intsts0;
+    uint16_t intsts1;
+    uint16_t intenb0;
+    uint16_t intenb1;
+    uint16_t brdysts;
+    uint16_t nrdysts;
+    uint16_t bempsts;
+    uint16_t brdyenb;
+    uint16_t nrdyenb;
+    uint16_t bempenb;
+    volatile uint16_t dumy_sts;
+
+    intsts0 = USB200.INTSTS0;
+    intsts1 = USB200.INTSTS1;
+    intenb0 = USB200.INTENB0;
+    intenb1 = USB200.INTENB1;
+
+    if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
+    {
+            USB200.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
+            RZA_IO_RegWrite_16(&USB200.INTENB1,
+                                0,
+                                USB_INTENB1_BCHGE_SHIFT,
+                                USB_INTENB1_BCHGE);
+            g_usb0_host_bchg_flag = USB_HOST_YES;
+    }
+    else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
+    {
+        USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
+#if(1) /* ohci_wrapp */
+        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+#else
+        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+        g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+#endif
+    }
+    else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
+    {
+        USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
+#if(1) /* ohci_wrapp */
+        g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#else
+        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+        g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
+#endif
+    }
+    else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
+          && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
+    {
+        USB200.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
+        RZA_IO_RegWrite_16(&USB200.INTENB1,
+                            0,
+                            USB_INTENB1_DTCHE_SHIFT,
+                            USB_INTENB1_DTCHE);
+        g_usb0_host_detach_flag = USB_HOST_YES;
+
+        Userdef_USB_usb0_host_detach();
+
+        usb0_host_UsbDetach2();
+    }
+    else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
+          && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
+    {
+        USB200.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
+        RZA_IO_RegWrite_16(&USB200.INTENB1,
+                            0,
+                            USB_INTENB1_ATTCHE_SHIFT,
+                            USB_INTENB1_ATTCHE);
+        g_usb0_host_attach_flag = USB_HOST_YES;
+
+        Userdef_USB_usb0_host_attach();
+
+        usb0_host_UsbAttach();
+    }
+    else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
+    {
+        brdysts = USB200.BRDYSTS;
+        nrdysts = USB200.NRDYSTS;
+        bempsts = USB200.BEMPSTS;
+        brdyenb = USB200.BRDYENB;
+        nrdyenb = USB200.NRDYENB;
+        bempenb = USB200.BEMPENB;
+
+        if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
+        {
+            usb0_host_BRDYInterrupt(brdysts, brdyenb);
+        }
+        else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
+        {
+            usb0_host_BEMPInterrupt(bempsts, bempenb);
+        }
+        else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
+        {
+            usb0_host_NRDYInterrupt(nrdysts, nrdyenb);
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* Three dummy read for clearing interrupt requests */
+    dumy_sts = USB200.INTSTS0;
+    dumy_sts = USB200.INTSTS1;
+
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_BRDYInterrupt
+* Description  : Executes USB BRDY interrupt.
+* Arguments    : uint16_t Status   ; BRDYSTS Register Value
+*              : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          buffer;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB200.BRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+
+#if(1) /* ohci_wrapp */
+        switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+        {
+            case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+                usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+            break;
+
+            case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+                switch (buffer)
+                {
+                    case USB_HOST_READING:                  /* Continue of data read */
+                    break;
+
+                    case USB_HOST_READEND:                  /* End of data read */
+                    case USB_HOST_READSHRT:                 /* End of data read */
+                        usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                    break;
+
+                    case USB_HOST_READOVER:                 /* buffer over */
+                        USB200.CFIFOCTR = USB_HOST_BITBCLR;
+                        usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                    break;
+
+                    case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                    default:
+                    break;
+                }
+            break;
+
+            default:
+            break;
+        }
+#else
+        switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+        {
+            case (USB_HOST_MODE_WRITE   | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+            case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+                usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+            break;
+
+            case (USB_HOST_MODE_READ   | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                buffer  = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+
+                switch (buffer)
+                {
+                    case USB_HOST_READING:                  /* Continue of data read */
+                    break;
+
+                    case USB_HOST_READEND:                  /* End of data read */
+                    case USB_HOST_READSHRT:                 /* End of data read */
+                        usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                    break;
+
+                    case USB_HOST_READOVER:                 /* buffer over */
+                        USB200.CFIFOCTR = USB_HOST_BITBCLR;
+                        usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                    break;
+
+                    case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                    default:
+                    break;
+                }
+            break;
+
+            default:
+            break;
+        }
+#endif
+    }
+    else
+    {
+        usb0_host_brdy_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB200.BRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_NRDYInterrupt
+* Description  : Executes USB NRDY interrupt.
+* Arguments    : uint16_t Status        ; NRDYSTS Register Value
+*              : uint16_t Int_enbl      ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          pid;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB200.NRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+        pid = usb0_host_get_pid(USB_HOST_PIPE0);
+
+        if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+        {
+            g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+        }
+        else if (pid  == USB_HOST_PID_NAK)
+        {
+            g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
+#if(1) /* ohci_wrapp */
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else
+    {
+        usb0_host_nrdy_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB200.NRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_BEMPInterrupt
+* Description  : Executes USB BEMP interrupt.
+* Arguments    : uint16_t Status        ; BEMPSTS Register Value
+*              : uint16_t Int_enbl      ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          buffer;
+    uint16_t          pid;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB200.BEMPSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+        pid = usb0_host_get_pid(USB_HOST_PIPE0);
+
+        if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+        {
+            g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+            g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+        }
+        else
+        {
+#if(1) /* ohci_wrapp */
+            switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+            {
+                case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                    ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                break;
+
+                case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                    buffer  = usb0_host_write_buffer(USB_HOST_PIPE0);
+                    switch (buffer)
+                    {
+                        case USB_HOST_WRITING:                  /* Continue of data write */
+                        case USB_HOST_WRITEEND:                 /* End of data write (zero-length) */
+                        break;
+
+                        case USB_HOST_WRITESHRT:                    /* End of data write */
+                            g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                            g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                        break;
+
+                        case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                        default:
+                        break;
+                    }
+                break;
+
+                default:
+                    /* do nothing */
+                break;
+            }
+#else
+            switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+            {
+                case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+                break;
+
+                case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                    buffer  = usb0_host_write_buffer(USB_HOST_PIPE0);
+                    switch (buffer)
+                    {
+                        case USB_HOST_WRITING:                  /* Continue of data write */
+                        case USB_HOST_WRITEEND:                 /* End of data write (zero-length) */
+                        break;
+
+                        case USB_HOST_WRITESHRT:                    /* End of data write */
+                            g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                            g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                        break;
+
+                        case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                        default:
+                        break;
+                    }
+                break;
+
+                case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+                break;
+
+                default:
+                    /* do nothing */
+                break;
+            }
+#endif
+        }
+    }
+    else
+    {
+        usb0_host_bemp_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB200.BEMPSTS;
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/host/usb0_host_usbsig.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,637 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_usbsig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_EnableINT_Module(void);
+static void usb0_host_Enable_AttachINT(void);
+static void usb0_host_Disable_AttachINT(void);
+static void usb0_host_Disable_BchgINT(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_InitModule
+* Description  : Initializes the USB module in USB host module.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_InitModule (void)
+{
+    uint16_t buf1;
+    uint16_t buf2;
+    uint16_t buf3;
+
+    usb0_host_init_pipe_status();
+
+    RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                        1,
+                        USB_SYSCFG_DCFM_SHIFT,
+                        USB_SYSCFG_DCFM);       /* HOST mode */
+    RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                        1,
+                        USB_SYSCFG_DRPD_SHIFT,
+                        USB_SYSCFG_DRPD);       /* PORT0 D+, D- setting */
+
+    do
+    {
+        buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb0_host_delay_xms(50);
+        buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb0_host_delay_xms(50);
+        buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+
+    } while ((buf1 != buf2) || (buf1 != buf3));
+
+    RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                        1,
+                        USB_SYSCFG_USBE_SHIFT,
+                        USB_SYSCFG_USBE);
+
+    USB200.CFIFOSEL  = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+    USB200.D0FIFOSEL = (uint16_t)(                   USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+    USB200.D1FIFOSEL = (uint16_t)(                   USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CheckAttach
+* Description  : Returns the USB device connection state.
+* Arguments    : none
+* Return Value : uint16_t ; USB_HOST_ATTACH : Attached
+*              :          ; USB_HOST_DETACH : not Attached
+*******************************************************************************/
+uint16_t usb0_host_CheckAttach (void)
+{
+    uint16_t buf1;
+    uint16_t buf2;
+    uint16_t buf3;
+    uint16_t rhst;
+
+    do
+    {
+        buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb0_host_delay_xms(50);
+        buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb0_host_delay_xms(50);
+        buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+
+    } while ((buf1 != buf2) || (buf1 != buf3));
+
+    rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+                                USB_DVSTCTR0_RHST_SHIFT,
+                                USB_DVSTCTR0_RHST);
+    if (rhst == USB_HOST_UNDECID)
+    {
+        if (buf1 == USB_HOST_FS_JSTS)
+        {
+            if (g_usb0_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED)
+            {
+                RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                                    1,
+                                    USB_SYSCFG_HSE_SHIFT,
+                                    USB_SYSCFG_HSE);
+            }
+            else
+            {
+                RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                                    0,
+                                    USB_SYSCFG_HSE_SHIFT,
+                                    USB_SYSCFG_HSE);
+            }
+            return USB_HOST_ATTACH;
+        }
+        else if (buf1 == USB_HOST_LS_JSTS)
+        {
+            /* Low Speed Device */
+            RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+                                0,
+                                USB_SYSCFG_HSE_SHIFT,
+                                USB_SYSCFG_HSE);
+            return USB_HOST_ATTACH;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE))
+    {
+        return USB_HOST_ATTACH;
+    }
+    else if (rhst == USB_HOST_LSMODE)
+    {
+        return USB_HOST_ATTACH;
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    return USB_HOST_DETACH;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbAttach
+* Description  : Connects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbAttach (void)
+{
+    usb0_host_EnableINT_Module();
+    usb0_host_Disable_BchgINT();
+    usb0_host_Disable_AttachINT();
+    usb0_host_Enable_DetachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbDetach
+* Description  : Disconnects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbDetach (void)
+{
+    uint16_t pipe;
+    uint16_t devadr;
+
+    g_usb0_host_driver_state = USB_HOST_DRV_DETACHED;
+
+    /* Terminate all the pipes in which communications on port  */
+    /* are currently carried out                                */
+    for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe)
+    {
+        if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE)
+        {
+            if (pipe == USB_HOST_PIPE0)
+            {
+                devadr = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+                                            USB_DCPMAXP_DEVSEL_SHIFT,
+                                            USB_DCPMAXP_DEVSEL);
+            }
+            else
+            {
+                devadr = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL);
+            }
+
+            if (devadr == g_usb0_host_UsbAddress)
+            {
+                usb0_host_stop_transfer(pipe);
+            }
+
+            g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE;
+        }
+    }
+
+    g_usb0_host_ConfigNum  = 0;
+    g_usb0_host_UsbAddress = 0;
+    g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+    usb0_host_UsbDetach2();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbDetach2
+* Description  : Disconnects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbDetach2 (void)
+{
+    usb0_host_Disable_DetachINT();
+    usb0_host_Disable_BchgINT();
+    usb0_host_Enable_AttachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbBusReset
+* Description  : Issues the USB bus reset signal.
+* Arguments    : none
+* Return Value : uint16_t               ; RHST
+*******************************************************************************/
+uint16_t usb0_host_UsbBusReset (void)
+{
+    uint16_t buffer;
+    uint16_t loop;
+
+    RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+                        1,
+                        USB_DVSTCTR0_USBRST_SHIFT,
+                        USB_DVSTCTR0_USBRST);
+    RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+                        0,
+                        USB_DVSTCTR0_UACT_SHIFT,
+                        USB_DVSTCTR0_UACT);
+
+    Userdef_USB_usb0_host_delay_xms(50);
+
+    buffer  = USB200.DVSTCTR0;
+    buffer &= (uint16_t)(~(USB_HOST_BITRST));
+    buffer |= USB_HOST_BITUACT;
+    USB200.DVSTCTR0 = buffer;
+
+    Userdef_USB_usb0_host_delay_xms(20);
+
+    for (loop = 0, buffer = USB_HOST_HSPROC;  loop < 3; ++loop)
+    {
+        buffer = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+                                    USB_DVSTCTR0_RHST_SHIFT,
+                                    USB_DVSTCTR0_RHST);
+        if (buffer == USB_HOST_HSPROC)
+        {
+            Userdef_USB_usb0_host_delay_xms(10);
+        }
+        else
+        {
+            break;
+        }
+    }
+
+    return buffer;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbResume
+* Description  : Issues the USB resume signal.
+* Arguments    : none
+* Return Value : int32_t            ; DEVDRV_SUCCESS
+*              :                    ; DEVDRV_ERROR
+*******************************************************************************/
+int32_t usb0_host_UsbResume (void)
+{
+    uint16_t buf;
+
+    if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) == 0)
+    {
+        /* not SUSPEND */
+        return DEVDRV_ERROR;
+    }
+
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        0,
+                        USB_INTENB1_BCHGE_SHIFT,
+                        USB_INTENB1_BCHGE);
+    RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+                        1,
+                        USB_DVSTCTR0_RESUME_SHIFT,
+                        USB_DVSTCTR0_RESUME);
+    Userdef_USB_usb0_host_delay_xms(20);
+
+    buf  = USB200.DVSTCTR0;
+    buf &= (uint16_t)(~(USB_HOST_BITRESUME));
+    buf |= USB_HOST_BITUACT;
+    USB200.DVSTCTR0 = buf;
+
+    g_usb0_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND;
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbSuspend
+* Description  : Issues the USB suspend signal.
+* Arguments    : none
+* Return Value : int32_t            ; DEVDRV_SUCCESS   :not SUSPEND
+*              :                    ; DEVDRV_ERROR     :SUSPEND
+*******************************************************************************/
+int32_t usb0_host_UsbSuspend (void)
+{
+    uint16_t buf;
+
+    if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) != 0)
+    {
+        /* SUSPEND */
+        return DEVDRV_ERROR;
+    }
+
+    RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+                        0,
+                        USB_DVSTCTR0_UACT_SHIFT,
+                        USB_DVSTCTR0_UACT);
+
+    Userdef_USB_usb0_host_delay_xms(5);
+
+    buf = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+    if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS))
+    {
+        usb0_host_UsbDetach();
+    }
+    else
+    {
+        g_usb0_host_driver_state |= USB_HOST_DRV_SUSPEND;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Enable_DetachINT
+* Description  : Enables the USB disconnection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Enable_DetachINT (void)
+{
+    USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        1,
+                        USB_INTENB1_DTCHE_SHIFT,
+                        USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_DetachINT
+* Description  : Disables the USB disconnection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_DetachINT (void)
+{
+    USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        0,
+                        USB_INTENB1_DTCHE_SHIFT,
+                        USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Enable_AttachINT
+* Description  : Enables the USB connection detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Enable_AttachINT (void)
+{
+    USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        1,
+                        USB_INTENB1_ATTCHE_SHIFT,
+                        USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_AttachINT
+* Description  : Disables the USB connection detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_AttachINT (void)
+{
+    USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        0,
+                        USB_INTENB1_ATTCHE_SHIFT,
+                        USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_BchgINT
+* Description  : Disables the USB bus change detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_BchgINT (void)
+{
+    USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG));
+    RZA_IO_RegWrite_16(&USB200.INTENB1,
+                        0,
+                        USB_INTENB1_BCHGE_SHIFT,
+                        USB_INTENB1_BCHGE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_devadd
+* Description  : DEVADDn register is set by specified value
+* Arguments    : uint16_t addr             : Device address
+*              : uint16_t *devadd          : Set value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_devadd (uint16_t addr, uint16_t * devadd)
+{
+    uint16_t * ptr;
+    uint16_t ret_flag = DEVDRV_FLAG_ON;                             // avoid warning.
+
+    switch (addr)
+    {
+        case USB_HOST_DEVICE_0:
+            ptr = (uint16_t *)&USB200.DEVADD0;
+        break;
+
+        case USB_HOST_DEVICE_1:
+            ptr = (uint16_t *)&USB200.DEVADD1;
+        break;
+
+        case USB_HOST_DEVICE_2:
+            ptr = (uint16_t *)&USB200.DEVADD2;
+        break;
+
+        case USB_HOST_DEVICE_3:
+            ptr = (uint16_t *)&USB200.DEVADD3;
+        break;
+
+        case USB_HOST_DEVICE_4:
+            ptr = (uint16_t *)&USB200.DEVADD4;
+        break;
+
+        case USB_HOST_DEVICE_5:
+            ptr = (uint16_t *)&USB200.DEVADD5;
+        break;
+
+        case USB_HOST_DEVICE_6:
+            ptr = (uint16_t *)&USB200.DEVADD6;
+        break;
+
+        case USB_HOST_DEVICE_7:
+            ptr = (uint16_t *)&USB200.DEVADD7;
+        break;
+
+        case USB_HOST_DEVICE_8:
+            ptr = (uint16_t *)&USB200.DEVADD8;
+        break;
+
+        case USB_HOST_DEVICE_9:
+            ptr = (uint16_t *)&USB200.DEVADD9;
+        break;
+
+        case USB_HOST_DEVICE_10:
+            ptr = (uint16_t *)&USB200.DEVADDA;
+        break;
+
+        default:
+            ret_flag = DEVDRV_FLAG_OFF;
+        break;
+    }
+
+    if (ret_flag == DEVDRV_FLAG_ON)
+    {
+        *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_devadd
+* Description  : DEVADDn register is obtained
+* Arguments    : uint16_t addr      : Device address
+*              : uint16_t *devadd   : USB_HOST_DEVADD register value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_get_devadd (uint16_t addr, uint16_t * devadd)
+{
+    uint16_t * ptr;
+    uint16_t ret_flag = DEVDRV_FLAG_ON;                             // avoid warning.
+
+    switch (addr)
+    {
+        case USB_HOST_DEVICE_0:
+            ptr = (uint16_t *)&USB200.DEVADD0;
+        break;
+
+        case USB_HOST_DEVICE_1:
+            ptr = (uint16_t *)&USB200.DEVADD1;
+        break;
+
+        case USB_HOST_DEVICE_2:
+            ptr = (uint16_t *)&USB200.DEVADD2;
+        break;
+
+        case USB_HOST_DEVICE_3:
+            ptr = (uint16_t *)&USB200.DEVADD3;
+        break;
+
+        case USB_HOST_DEVICE_4:
+            ptr = (uint16_t *)&USB200.DEVADD4;
+        break;
+
+        case USB_HOST_DEVICE_5:
+            ptr = (uint16_t *)&USB200.DEVADD5;
+        break;
+
+        case USB_HOST_DEVICE_6:
+            ptr = (uint16_t *)&USB200.DEVADD6;
+        break;
+
+        case USB_HOST_DEVICE_7:
+            ptr = (uint16_t *)&USB200.DEVADD7;
+        break;
+
+        case USB_HOST_DEVICE_8:
+            ptr = (uint16_t *)&USB200.DEVADD8;
+        break;
+
+        case USB_HOST_DEVICE_9:
+            ptr = (uint16_t *)&USB200.DEVADD9;
+        break;
+
+        case USB_HOST_DEVICE_10:
+            ptr = (uint16_t *)&USB200.DEVADDA;
+        break;
+
+        default:
+            ret_flag = DEVDRV_FLAG_OFF;
+        break;
+    }
+
+    if (ret_flag == DEVDRV_FLAG_ON)
+    {
+        *devadd = *ptr;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_EnableINT_Module
+* Description  : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt.
+*              : Enables NRDY/BEMP interrupt in the pipe0.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_EnableINT_Module (void)
+{
+    uint16_t buf;
+
+    buf  = USB200.INTENB0;
+    buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE);
+    USB200.INTENB0 = buf;
+
+    buf  = USB200.INTENB1;
+    buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE);
+    USB200.INTENB1 = buf;
+
+    usb0_host_enable_nrdy_int(USB_HOST_PIPE0);
+    usb0_host_enable_bemp_int(USB_HOST_PIPE0);
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,698 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb0_host_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE   (255)       /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+    DMAC_REQ_MID,
+    DMAC_REQ_RID,
+    DMAC_REQ_AM,
+    DMAC_REQ_LVL,
+    DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] =
+{
+  /* MID,RID, AM,LVL,REQD */
+    { 32,  3,  2,  1,  1},      /* USB_0 channel 0 transmit FIFO empty */
+    { 32,  3,  2,  1,  0},      /* USB_0 channel 0 receive FIFO full   */
+    { 33,  3,  2,  1,  1},      /* USB_0 channel 1 transmit FIFO empty */
+    { 33,  3,  2,  1,  0},      /* USB_0 channel 1 receive FIFO full   */
+    { 34,  3,  2,  1,  1},      /* USB_1 channel 0 transmit FIFO empty */
+    { 34,  3,  2,  1,  0},      /* USB_1 channel 0 receive FIFO full   */
+    { 35,  3,  2,  1,  1},      /* USB_1 channel 1 transmit FIFO empty */
+    { 35,  3,  2,  1,  0},      /* USB_1 channel 1 receive FIFO full   */
+};
+
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_PeriReqInit
+* Description  : Sets the register mode for DMA mode and the on-chip peripheral
+*              : module request for transfer request for DMAC channel 1.
+*              : Executes DMAC initial setting using the DMA information
+*              : specified by the argument *trans_info and the enabled/disabled
+*              : continuous transfer specified by the argument continuation.
+*              : Registers DMAC channel 1 interrupt handler function and sets
+*              : the interrupt priority level. Then enables transfer completion
+*              : interrupt.
+* Arguments    : dmac_transinfo_t * trans_info : Setting information to DMAC
+*              :                               : register
+*              : uint32_t dmamode      : DMA mode (only for DMAC_MODE_REGISTER)
+*              : uint32_t continuation : Set continuous transfer to be valid
+*              :                       : after DMA transfer has been completed
+*              :         DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+*              :         DMAC_SAMPLE_SINGLE       : Do not execute continuous
+*              :                                  : transfer
+*              : uint32_t request_factor : Factor for on-chip peripheral module
+*              :                         : request
+*              :         DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+*              :         DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+*              :         DMAC_REQ_TGI0A     : MTU2_0 input capture/compare match
+*              :                 :
+*              : uint32_t req_direction : Setting value of CHCFG_n register
+*              :                        : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                              uint32_t request_factor, uint32_t req_direction)
+{
+    /* ==== Register mode ==== */
+    if (DMAC_MODE_REGISTER == dmamode)
+    {
+        /* ==== Next0 register set ==== */
+        DMAC1.N0SA_n = trans_info->src_addr;        /* Start address of transfer source      */
+        DMAC1.N0DA_n = trans_info->dst_addr;        /* Start address of transfer destination */
+        DMAC1.N0TB_n = trans_info->count;           /* Total transfer byte count             */
+
+        /* DAD : Transfer destination address counting direction */
+        /* SAD : Transfer source address counting direction      */
+        /* DDS : Transfer destination transfer size              */
+        /* SDS : Transfer source transfer size                   */
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            trans_info->daddr_dir,
+                            DMAC1_CHCFG_n_DAD_SHIFT,
+                            DMAC1_CHCFG_n_DAD);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            trans_info->saddr_dir,
+                            DMAC1_CHCFG_n_SAD_SHIFT,
+                            DMAC1_CHCFG_n_SAD);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            trans_info->dst_size,
+                            DMAC1_CHCFG_n_DDS_SHIFT,
+                            DMAC1_CHCFG_n_DDS);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            trans_info->src_size,
+                            DMAC1_CHCFG_n_SDS_SHIFT,
+                            DMAC1_CHCFG_n_SDS);
+
+        /* DMS  : Register mode                            */
+        /* RSEL : Select Next0 register set                */
+        /* SBE  : No discharge of buffer data when aborted */
+        /* DEM  : No DMA interrupt mask                    */
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_DMS_SHIFT,
+                            DMAC1_CHCFG_n_DMS);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_RSEL_SHIFT,
+                            DMAC1_CHCFG_n_RSEL);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_SBE_SHIFT,
+                            DMAC1_CHCFG_n_SBE);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_DEM_SHIFT,
+                            DMAC1_CHCFG_n_DEM);
+
+        /* ---- Continuous transfer ---- */
+        if (DMAC_SAMPLE_CONTINUATION == continuation)
+        {
+            /* REN : Execute continuous transfer                         */
+            /* RSW : Change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                1,
+                                DMAC1_CHCFG_n_REN_SHIFT,
+                                DMAC1_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                1,
+                                DMAC1_CHCFG_n_RSW_SHIFT,
+                                DMAC1_CHCFG_n_RSW);
+        }
+        /* ---- Single transfer ---- */
+        else
+        {
+            /* REN : Do not execute continuous transfer                         */
+            /* RSW : Do not change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                0,
+                                DMAC1_CHCFG_n_REN_SHIFT,
+                                DMAC1_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                0,
+                                DMAC1_CHCFG_n_RSW_SHIFT,
+                                DMAC1_CHCFG_n_RSW);
+        }
+
+        /* TM  : Single transfer                          */
+        /* SEL : Channel setting                          */
+        /* HIEN, LOEN : On-chip peripheral module request */
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_TM_SHIFT,
+                            DMAC1_CHCFG_n_TM);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            1,
+                            DMAC1_CHCFG_n_SEL_SHIFT,
+                            DMAC1_CHCFG_n_SEL);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            1,
+                            DMAC1_CHCFG_n_HIEN_SHIFT,
+                            DMAC1_CHCFG_n_HIEN);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            0,
+                            DMAC1_CHCFG_n_LOEN_SHIFT,
+                            DMAC1_CHCFG_n_LOEN);
+
+        /* ---- Set factor by specified on-chip peripheral module request ---- */
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+                            DMAC1_CHCFG_n_AM_SHIFT,
+                            DMAC1_CHCFG_n_AM);
+        RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+                            DMAC1_CHCFG_n_LVL_SHIFT,
+                            DMAC1_CHCFG_n_LVL);
+        if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+        {
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+                                DMAC1_CHCFG_n_REQD_SHIFT,
+                                DMAC1_CHCFG_n_REQD);
+        }
+        else
+        {
+            RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+                                req_direction,
+                                DMAC1_CHCFG_n_REQD_SHIFT,
+                                DMAC1_CHCFG_n_REQD);
+        }
+        RZA_IO_RegWrite_32(&DMAC01.DMARS,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+                            DMAC01_DMARS_CH1_RID_SHIFT,
+                            DMAC01_DMARS_CH1_RID);
+        RZA_IO_RegWrite_32(&DMAC01.DMARS,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+                            DMAC01_DMARS_CH1_MID_SHIFT,
+                            DMAC01_DMARS_CH1_MID);
+
+        /* PR : Round robin mode */
+        RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+                            1,
+                            DMAC07_DCTRL_0_7_PR_SHIFT,
+                            DMAC07_DCTRL_0_7_PR);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Open
+* Description  : Enables DMAC channel 1 transfer.
+* Arguments    : uint32_t req : DMAC request mode
+* Return Value :  0 : Succeeded in enabling DMA transfer
+*              : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_host_DMAC1_Open (uint32_t req)
+{
+    int32_t ret;
+    volatile uint8_t  dummy;
+
+    /* Transferable? */
+    if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+                                DMAC1_CHSTAT_n_EN_SHIFT,
+                                DMAC1_CHSTAT_n_EN)) &&
+        (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+                                DMAC1_CHSTAT_n_TACT_SHIFT,
+                                DMAC1_CHSTAT_n_TACT)))
+    {
+        /* Clear Channel Status Register */
+        RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+                            1,
+                            DMAC1_CHCTRL_n_SWRST_SHIFT,
+                            DMAC1_CHCTRL_n_SWRST);
+        dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
+                                DMAC1_CHCTRL_n_SWRST_SHIFT,
+                                DMAC1_CHCTRL_n_SWRST);
+        /* Enable DMA transfer */
+        RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+                            1,
+                            DMAC1_CHCTRL_n_SETEN_SHIFT,
+                            DMAC1_CHCTRL_n_SETEN);
+
+        /* ---- Request by software ---- */
+        if (DMAC_REQ_MODE_SOFT == req)
+        {
+            /* DMA transfer Request by software */
+            RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+                                1,
+                                DMAC1_CHCTRL_n_STG_SHIFT,
+                                DMAC1_CHCTRL_n_STG);
+        }
+
+        ret = 0;
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Close
+* Description  : Aborts DMAC channel 1 transfer. Returns the remaining transfer
+*              : byte count at the time of DMA transfer abort to the argument
+*              : *remain.
+* Arguments    : uint32_t * remain : Remaining transfer byte count when
+*              :                   : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_Close (uint32_t * remain)
+{
+
+    /* ==== Abort transfer ==== */
+    RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+                        1,
+                        DMAC1_CHCTRL_n_CLREN_SHIFT,
+                        DMAC1_CHCTRL_n_CLREN);
+
+    while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+                                DMAC1_CHSTAT_n_TACT_SHIFT,
+                                DMAC1_CHSTAT_n_TACT))
+    {
+        /* Loop until transfer is aborted */
+    }
+
+    while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+                                DMAC1_CHSTAT_n_EN_SHIFT,
+                                DMAC1_CHSTAT_n_EN))
+    {
+        /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+    }
+    /* ==== Obtain remaining transfer byte count ==== */
+    *remain = DMAC1.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Load_Set
+* Description  : Sets the transfer source address, transfer destination
+*              : address, and total transfer byte count respectively
+*              : specified by the argument src_addr, dst_addr, and count to
+*              : DMAC channel 1 as DMA transfer information.
+*              : Sets the register set selected by the CHCFG_n register
+*              : RSEL bit from the Next0 or Next1 register set.
+*              : This function should be called when DMA transfer of DMAC
+*              : channel 1 is aboted.
+* Arguments    : uint32_t src_addr : Transfer source address
+*              : uint32_t dst_addr : Transfer destination address
+*              : uint32_t count    : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+    uint8_t reg_set;
+
+    /* Obtain register set in use */
+    reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+                                DMAC1_CHSTAT_n_SR_SHIFT,
+                                DMAC1_CHSTAT_n_SR);
+
+    /* ==== Load ==== */
+    if (0 == reg_set)
+    {
+        /* ---- Next0 Register Set ---- */
+        DMAC1.N0SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC1.N0DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC1.N0TB_n = count;       /* Total transfer byte count             */
+    }
+    else
+    {
+        /* ---- Next1 Register Set ---- */
+        DMAC1.N1SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC1.N1DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC1.N1TB_n = count;       /* Total transfer byte count             */
+     }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_PeriReqInit
+* Description  : Sets the register mode for DMA mode and the on-chip peripheral
+*              : module request for transfer request for DMAC channel 2.
+*              : Executes DMAC initial setting using the DMA information
+*              : specified by the argument *trans_info and the enabled/disabled
+*              : continuous transfer specified by the argument continuation.
+*              : Registers DMAC channel 2 interrupt handler function and sets
+*              : the interrupt priority level. Then enables transfer completion
+*              : interrupt.
+* Arguments    : dmac_transinfo_t * trans_info : Setting information to DMAC
+*              :                               : register
+*              : uint32_t dmamode      : DMA mode (only for DMAC_MODE_REGISTER)
+*              : uint32_t continuation : Set continuous transfer to be valid
+*              :                       : after DMA transfer has been completed
+*              :         DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+*              :         DMAC_SAMPLE_SINGLE       : Do not execute continuous
+*              :                                  : transfer
+*              : uint32_t request_factor : Factor for on-chip peripheral module
+*              :                         : request
+*              :         DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+*              :         DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+*              :         DMAC_REQ_TGI0A     : MTU2_0 input capture/compare match
+*              :                 :
+*              : uint32_t req_direction : Setting value of CHCFG_n register
+*              :                        : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                              uint32_t request_factor, uint32_t req_direction)
+{
+    /* ==== Register mode ==== */
+    if (DMAC_MODE_REGISTER == dmamode)
+    {
+        /* ==== Next0 register set ==== */
+        DMAC2.N0SA_n = trans_info->src_addr;        /* Start address of transfer source      */
+        DMAC2.N0DA_n = trans_info->dst_addr;        /* Start address of transfer destination */
+        DMAC2.N0TB_n = trans_info->count;           /* Total transfer byte count             */
+
+        /* DAD : Transfer destination address counting direction */
+        /* SAD : Transfer source address counting direction      */
+        /* DDS : Transfer destination transfer size              */
+        /* SDS : Transfer source transfer size                   */
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            trans_info->daddr_dir,
+                            DMAC2_CHCFG_n_DAD_SHIFT,
+                            DMAC2_CHCFG_n_DAD);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            trans_info->saddr_dir,
+                            DMAC2_CHCFG_n_SAD_SHIFT,
+                            DMAC2_CHCFG_n_SAD);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            trans_info->dst_size,
+                            DMAC2_CHCFG_n_DDS_SHIFT,
+                            DMAC2_CHCFG_n_DDS);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            trans_info->src_size,
+                            DMAC2_CHCFG_n_SDS_SHIFT,
+                            DMAC2_CHCFG_n_SDS);
+
+        /* DMS  : Register mode                            */
+        /* RSEL : Select Next0 register set                */
+        /* SBE  : No discharge of buffer data when aborted */
+        /* DEM  : No DMA interrupt mask                    */
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_DMS_SHIFT,
+                            DMAC2_CHCFG_n_DMS);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_RSEL_SHIFT,
+                            DMAC2_CHCFG_n_RSEL);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_SBE_SHIFT,
+                            DMAC2_CHCFG_n_SBE);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_DEM_SHIFT,
+                            DMAC2_CHCFG_n_DEM);
+
+        /* ---- Continuous transfer ---- */
+        if (DMAC_SAMPLE_CONTINUATION == continuation)
+        {
+            /* REN : Execute continuous transfer                         */
+            /* RSW : Change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                1,
+                                DMAC2_CHCFG_n_REN_SHIFT,
+                                DMAC2_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                1,
+                                DMAC2_CHCFG_n_RSW_SHIFT,
+                                DMAC2_CHCFG_n_RSW);
+        }
+        /* ---- Single transfer ---- */
+        else
+        {
+            /* REN : Do not execute continuous transfer                         */
+            /* RSW : Do not change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                0,
+                                DMAC2_CHCFG_n_REN_SHIFT,
+                                DMAC2_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                0,
+                                DMAC2_CHCFG_n_RSW_SHIFT,
+                                DMAC2_CHCFG_n_RSW);
+        }
+
+        /* TM  : Single transfer                          */
+        /* SEL : Channel setting                          */
+        /* HIEN, LOEN : On-chip peripheral module request */
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_TM_SHIFT,
+                            DMAC2_CHCFG_n_TM);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            2,
+                            DMAC2_CHCFG_n_SEL_SHIFT,
+                            DMAC2_CHCFG_n_SEL);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            1,
+                            DMAC2_CHCFG_n_HIEN_SHIFT,
+                            DMAC2_CHCFG_n_HIEN);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            0,
+                            DMAC2_CHCFG_n_LOEN_SHIFT,
+                            DMAC2_CHCFG_n_LOEN);
+
+        /* ---- Set factor by specified on-chip peripheral module request ---- */
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+                            DMAC2_CHCFG_n_AM_SHIFT,
+                            DMAC2_CHCFG_n_AM);
+        RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+                            DMAC2_CHCFG_n_LVL_SHIFT,
+                            DMAC2_CHCFG_n_LVL);
+        if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+        {
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+                                DMAC2_CHCFG_n_REQD_SHIFT,
+                                DMAC2_CHCFG_n_REQD);
+        }
+        else
+        {
+            RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+                                req_direction,
+                                DMAC2_CHCFG_n_REQD_SHIFT,
+                                DMAC2_CHCFG_n_REQD);
+        }
+        RZA_IO_RegWrite_32(&DMAC23.DMARS,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+                            DMAC23_DMARS_CH2_RID_SHIFT,
+                            DMAC23_DMARS_CH2_RID);
+        RZA_IO_RegWrite_32(&DMAC23.DMARS,
+                            usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+                            DMAC23_DMARS_CH2_MID_SHIFT,
+                            DMAC23_DMARS_CH2_MID);
+
+        /* PR : Round robin mode */
+        RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+                            1,
+                            DMAC07_DCTRL_0_7_PR_SHIFT,
+                            DMAC07_DCTRL_0_7_PR);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Open
+* Description  : Enables DMAC channel 2 transfer.
+* Arguments    : uint32_t req : DMAC request mode
+* Return Value :  0 : Succeeded in enabling DMA transfer
+*              : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_host_DMAC2_Open (uint32_t req)
+{
+    int32_t ret;
+    volatile uint8_t  dummy;
+
+    /* Transferable? */
+    if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+                                DMAC2_CHSTAT_n_EN_SHIFT,
+                                DMAC2_CHSTAT_n_EN)) &&
+        (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+                                DMAC2_CHSTAT_n_TACT_SHIFT,
+                                DMAC2_CHSTAT_n_TACT)))
+    {
+        /* Clear Channel Status Register */
+        RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+                            1,
+                            DMAC2_CHCTRL_n_SWRST_SHIFT,
+                            DMAC2_CHCTRL_n_SWRST);
+        dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
+                                DMAC2_CHCTRL_n_SWRST_SHIFT,
+                                DMAC2_CHCTRL_n_SWRST);
+        /* Enable DMA transfer */
+        RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+                            1,
+                            DMAC2_CHCTRL_n_SETEN_SHIFT,
+                            DMAC2_CHCTRL_n_SETEN);
+
+        /* ---- Request by software ---- */
+        if (DMAC_REQ_MODE_SOFT == req)
+        {
+            /* DMA transfer Request by software */
+            RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+                                1,
+                                DMAC2_CHCTRL_n_STG_SHIFT,
+                                DMAC2_CHCTRL_n_STG);
+        }
+
+        ret = 0;
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Close
+* Description  : Aborts DMAC channel 2 transfer. Returns the remaining transfer
+*              : byte count at the time of DMA transfer abort to the argument
+*              : *remain.
+* Arguments    : uint32_t * remain : Remaining transfer byte count when
+*              :                   : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_Close (uint32_t * remain)
+{
+
+    /* ==== Abort transfer ==== */
+    RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+                        1,
+                        DMAC2_CHCTRL_n_CLREN_SHIFT,
+                        DMAC2_CHCTRL_n_CLREN);
+
+    while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+                                DMAC2_CHSTAT_n_TACT_SHIFT,
+                                DMAC2_CHSTAT_n_TACT))
+    {
+        /* Loop until transfer is aborted */
+    }
+
+    while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+                                DMAC2_CHSTAT_n_EN_SHIFT,
+                                DMAC2_CHSTAT_n_EN))
+    {
+        /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+    }
+    /* ==== Obtain remaining transfer byte count ==== */
+    *remain = DMAC2.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Load_Set
+* Description  : Sets the transfer source address, transfer destination
+*              : address, and total transfer byte count respectively
+*              : specified by the argument src_addr, dst_addr, and count to
+*              : DMAC channel 2 as DMA transfer information.
+*              : Sets the register set selected by the CHCFG_n register
+*              : RSEL bit from the Next0 or Next1 register set.
+*              : This function should be called when DMA transfer of DMAC
+*              : channel 2 is aboted.
+* Arguments    : uint32_t src_addr : Transfer source address
+*              : uint32_t dst_addr : Transfer destination address
+*              : uint32_t count    : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+    uint8_t reg_set;
+
+    /* Obtain register set in use */
+    reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+                                DMAC2_CHSTAT_n_SR_SHIFT,
+                                DMAC2_CHSTAT_n_SR);
+
+    /* ==== Load ==== */
+    if (0 == reg_set)
+    {
+        /* ---- Next0 Register Set ---- */
+        DMAC2.N0SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC2.N0DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC2.N0TB_n = count;       /* Total transfer byte count             */
+    }
+    else
+    {
+        /* ---- Next1 Register Set ---- */
+        DMAC2.N1SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC2.N1DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC2.N1TB_n = count;       /* Total transfer byte count             */
+     }
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,778 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb0_host_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_host_api.h"
+#include "usb0_host.h"
+#include "VKRZA1H.h"            /* INTC Driver Header   */
+#include "usb0_host_dmacdrv.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb0_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb0_host_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_d0fifo_dmaintid
+* Description  : get D0FIFO DMA Interrupt ID
+* Arguments    : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+    return 0xFFFF;
+#else
+    return DMAINT1_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_d1fifo_dmaintid
+* Description  : get D1FIFO DMA Interrupt ID
+* Arguments    : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+    return 0xFFFF;
+#else
+    return DMAINT2_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_attach
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_attach (void)
+{
+//    printf("\n");
+//    printf("channel 0 attach device\n");
+//    printf("\n");
+    ohciwrapp_loc_Connect(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_detach
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_detach (void)
+{
+//    printf("\n");
+//    printf("channel 0 detach device\n");
+//    printf("\n");
+    ohciwrapp_loc_Connect(0);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_1ms
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_1ms (void)
+{
+    osDelay(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_xms
+* Description  : Wait for the software in the period of time specified by the
+*              : argument.
+*              : Alter this function according to the user's system.
+* Arguments    : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_xms (uint32_t msec)
+{
+    osDelay(msec);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_10us
+* Description  : Waits for software for the period specified by the argument.
+*              : Alter this function according to the user's system.
+* Arguments    : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_10us (uint32_t usec)
+{
+    volatile int i;
+
+    /* Wait 10us (Please change for your MCU) */
+    for (i = 0; i < usec; ++i)
+    {
+        Userdef_USB_usb0_host_delay_10us_2();
+    }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_10us_2
+* Description  : Waits for software for the period specified by the argument.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb0_host_delay_10us_2 (void)
+{
+    volatile int i;
+    volatile unsigned long tmp;
+
+    /* Wait 1us (Please change for your MCU) */
+    for (i = 0; i < 14; ++i)
+    {
+        tmp = DUMMY_ACCESS;
+    }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_500ns
+* Description  : Wait for software for 500ns.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_500ns (void)
+{
+    volatile int i;
+    volatile unsigned long tmp;
+
+    /* Wait 500ns (Please change for your MCU) */
+    /* Wait 500ns I clock 266MHz */
+    tmp = DUMMY_ACCESS;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_start_dma
+* Description  : Enables DMA transfer on the information specified by the argument.
+*              : Set DMAC register by this function to enable DMA transfer.
+*              : After executing this function, USB module is set to start DMA
+*              : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments    : USB_HOST_DMA_t *dma   : DMA parameter
+*              :  typedef struct{
+*              :      uint32_t fifo;    FIFO for using
+*              :      uint32_t buffer;  Start address of transfer source/destination
+*              :      uint32_t bytes;   Transfer size(Byte)
+*              :      uint32_t dir;     Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+*              :      uint32_t size;    DMA transfer size
+*              :   } USB_HOST_DMA_t;
+*              : uint16_t dfacc ; 0 : cycle steal mode
+*              :                  1 : 16byte continuous mode
+*              :                  2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc)
+{
+    uint32_t trncount;
+    uint32_t src;
+    uint32_t dst;
+    uint32_t size;
+    uint32_t dir;
+#ifdef CACHE_WRITEBACK
+    uint32_t ptr;
+#endif
+
+    trncount = dma->bytes;
+    dir      = dma->dir;
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        /* DxFIFO determination */
+        dst = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+        if (dma->fifo == USB_HOST_D0FIFO_DMA)
+        {
+            src = (uint32_t)(&USB200.D0FIFO.UINT32);
+        }
+        else
+        {
+            src = (uint32_t)(&USB200.D1FIFO.UINT32);
+        }
+        size = dma->size;
+
+        if (size == 0)
+        {
+            src += 3;       /* byte access  */
+        }
+        else if (size == 1)
+        {
+            src += 2;       /* short access */
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+#else
+        size = dma->size;
+
+        if (size == 2)
+        {
+            /* 32bit access */
+            if (dfacc == 2)
+            {
+                /* 32byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB200.D0FIFOB0);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB200.D1FIFOB0);
+                }
+            }
+            else if (dfacc == 1)
+            {
+                /* 16byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB200.D0FIFOB0);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB200.D1FIFOB0);
+                }
+            }
+            else
+            {
+                /* normal access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB200.D0FIFO.UINT32);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB200.D1FIFO.UINT32);
+                }
+            }
+        }
+        else if (size == 1)
+        {
+            /* 16bit access */
+            dfacc = 0;      /* force normal access */
+
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                src = (uint32_t)(&USB200.D0FIFO.UINT32);
+            }
+            else
+            {
+                src = (uint32_t)(&USB200.D1FIFO.UINT32);
+            }
+            src += 2;       /* short access */
+        }
+        else
+        {
+            /* 8bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                src = (uint32_t)(&USB200.D0FIFO.UINT32);
+            }
+            else
+            {
+                src = (uint32_t)(&USB200.D1FIFO.UINT32);
+            }
+            src += 3;       /* byte access  */
+        }
+#endif
+    }
+    else
+    {
+        /* DxFIFO determination */
+        src = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+        if (dma->fifo == USB_HOST_D0FIFO_DMA)
+        {
+            dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+        }
+        else
+        {
+            dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+        }
+        size = dma->size;
+
+        if (size == 0)
+        {
+            dst += 3;       /* byte access  */
+        }
+        else if (size == 1)
+        {
+            dst += 2;       /* short access */
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+#else
+        size = dma->size;
+        if (size == 2)
+        {
+            /* 32bit access */
+            if (dfacc == 2)
+            {
+                /* 32byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB200.D0FIFOB0);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB200.D1FIFOB0);
+                }
+            }
+            else if (dfacc == 1)
+            {
+                /* 16byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB200.D0FIFOB0);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB200.D1FIFOB0);
+                }
+            }
+            else
+            {
+                /* normal access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+                }
+            }
+        }
+        else if (size == 1)
+        {
+            /* 16bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+            }
+            else
+            {
+                dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+            }
+            dst += 2;       /* short access */
+        }
+        else
+        {
+            /* 8bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+            }
+            else
+            {
+                dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+            }
+            dst += 3;       /* byte access  */
+        }
+#endif
+    }
+
+#ifdef CACHE_WRITEBACK
+    ptr = (uint32_t)dma->buffer;
+    if ((ptr & 0x20000000ul) == 0)
+    {
+        io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount);
+    }
+#endif
+
+    if (dma->fifo == USB_HOST_D0FIFO_DMA)
+    {
+        usb0_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+    }
+    else
+    {
+        usb0_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_dmac0
+* Description  : Enables DMA transfer on the information specified by the argument.
+* Arguments    : uint32_t src   : src address
+*              : uint32_t dst   : dst address
+*              : uint32_t count : transfer byte
+*              : uint32_t size  : transfer size
+*              : uint32_t dir   : direction
+*              : uint32_t fifo  : FIFO(D0FIFO or D1FIFO)
+*              : uint16_t dfacc : 0 : normal access
+*              :                : 1 : 16byte access
+*              :                : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+    dmac_transinfo_t trans_info;
+    uint32_t         request_factor = 0;
+    int32_t          ret;
+
+    /* ==== Variable setting for DMAC initialization ==== */
+    trans_info.src_addr  = (uint32_t)src;               /* Start address of transfer source */
+    trans_info.dst_addr  = (uint32_t)dst;               /* Start address of transfer destination */
+    trans_info.count     = (uint32_t)count;             /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    if (size == 0)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_8;        /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_8;        /* Transfer destination transfer size */
+    }
+    else if (size == 1)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_16;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_16;       /* Transfer destination transfer size */
+    }
+    else if (size == 2)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_32;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_32;       /* Transfer destination transfer size */
+    }
+    else
+    {
+//        printf("size error!!\n");
+    }
+#else
+    if (dfacc == 2)
+    {
+        /* 32byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_256;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_256;      /* Transfer destination transfer size */
+    }
+    else if (dfacc == 1)
+    {
+        /* 16byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_128;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_128;      /* Transfer destination transfer size */
+    }
+    else
+    {
+        /* normal access */
+        if (size == 0)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_8;    /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_8;    /* Transfer destination transfer size */
+        }
+        else if (size == 1)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_16;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_16;   /* Transfer destination transfer size */
+        }
+        else if (size == 2)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_32;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_32;   /* Transfer destination transfer size */
+        }
+        else
+        {
+//            printf("size error!!\n");
+        }
+    }
+#endif
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        request_factor       = DMAC_REQ_USB0_DMA0_RX;   /* USB_0 channel 0 receive FIFO full */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer destination address */
+    }
+    else if (dir == USB_HOST_BUF2FIFO)
+    {
+        request_factor       = DMAC_REQ_USB0_DMA0_TX;   /* USB_0 channel 0 receive FIFO empty */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer destination address */
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* ==== DMAC initialization ==== */
+    usb0_host_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+                                    DMAC_MODE_REGISTER,
+                                    DMAC_SAMPLE_SINGLE,
+                                    request_factor,
+                                    0);     /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */
+
+    /* ==== DMAC startup ==== */
+    ret = usb0_host_DMAC1_Open(DMAC_REQ_MODE_PERI);
+
+    if (ret != 0)
+    {
+//        printf("DMAC1 Open error!!\n");
+    }
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_dmac1
+* Description  : Enables DMA transfer on the information specified by the argument.
+* Arguments    : uint32_t src   : src address
+*              : uint32_t dst   : dst address
+*              : uint32_t count : transfer byte
+*              : uint32_t size  : transfer size
+*              : uint32_t dir   : direction
+*              : uint32_t fifo  : FIFO(D0FIFO or D1FIFO)
+*              : uint16_t dfacc : 0 : normal access
+*              :                : 1 : 16byte access
+*              :                : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+    dmac_transinfo_t trans_info;
+    uint32_t request_factor = 0;
+    int32_t  ret;
+
+    /* ==== Variable setting for DMAC initialization ==== */
+    trans_info.src_addr  = (uint32_t)src;               /* Start address of transfer source */
+    trans_info.dst_addr  = (uint32_t)dst;               /* Start address of transfer destination */
+    trans_info.count     = (uint32_t)count;             /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    if (size == 0)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_8;        /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_8;        /* Transfer destination transfer size */
+    }
+    else if (size == 1)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_16;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_16;       /* Transfer destination transfer size */
+    }
+    else if (size == 2)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_32;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_32;       /* Transfer destination transfer size */
+    }
+    else
+    {
+//        printf("size error!!\n");
+    }
+#else
+    if (dfacc == 2)
+    {
+        /* 32byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_256;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_256;      /* Transfer destination transfer size */
+    }
+    else if (dfacc == 1)
+    {
+        /* 16byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_128;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_128;      /* Transfer destination transfer size */
+    }
+    else
+    {
+        /* normal access */
+        if (size == 0)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_8;    /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_8;    /* Transfer destination transfer size */
+        }
+        else if (size == 1)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_16;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_16;   /* Transfer destination transfer size */
+        }
+        else if (size == 2)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_32;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_32;   /* Transfer destination transfer size */
+        }
+        else
+        {
+//            printf("size error!!\n");
+        }
+    }
+#endif
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        request_factor =DMAC_REQ_USB0_DMA1_RX;          /* USB_0 channel 0 receive FIFO full */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer destination address */
+    }
+    else if (dir == USB_HOST_BUF2FIFO)
+    {
+        request_factor =DMAC_REQ_USB0_DMA1_TX;          /* USB_0 channel 0 receive FIFO empty */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer destination address */
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* ==== DMAC initialization ==== */
+    usb0_host_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+                                    DMAC_MODE_REGISTER,
+                                    DMAC_SAMPLE_SINGLE,
+                                    request_factor,
+                                    0);     /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC2_PeriReqInit() */
+
+    /* ==== DMAC startup ==== */
+    ret = usb0_host_DMAC2_Open(DMAC_REQ_MODE_PERI);
+
+    if (ret != 0)
+    {
+//        printf("DMAC2 Open error!!\n");
+    }
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_stop_dma0
+* Description  : Disables DMA transfer.
+* Arguments    : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+*              : regarding to the bus width.
+* Notice       : This function should be executed to DMAC executed at the time
+*              : of specification of D0_FIF0_DMA in dma->fifo.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_host_stop_dma0 (void)
+{
+    uint32_t remain;
+
+    /* ==== DMAC release ==== */
+    usb0_host_DMAC1_Close(&remain);
+
+    return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_stop_dma1
+* Description  : Disables DMA transfer.
+*              : This function should be executed to DMAC executed at the time
+*              : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments    : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+*              : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_host_stop_dma1 (void)
+{
+    uint32_t remain;
+
+    /* ==== DMAC release ==== */
+    usb0_host_DMAC2_Close(&remain);
+
+    return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_notice
+* Description  : Notice of USER
+* Arguments    : const char *format
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_notice (const char * format)
+{
+//    printf(format);
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_user_rdy
+* Description  : This function notify a user and wait for trigger
+* Arguments    : const char *format
+*              :    uint16_t data
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_user_rdy (const char * format, uint16_t data)
+{
+//    printf(format, data);
+    getchar();
+
+    return;
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/inc/usb1_host.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,156 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_H
+#define USB1_HOST_H
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+#include "usb_host.h"
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t   g_usb1_host_bit_set[];
+extern uint32_t         g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+extern uint8_t          *g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+extern uint16_t         g_usb1_host_PipeIgnore[];
+extern uint16_t         g_usb1_host_PipeTbl[];
+extern uint16_t         g_usb1_host_pipe_status[];
+extern uint32_t         g_usb1_host_PipeDataSize[];
+
+extern USB_HOST_DMA_t   g_usb1_host_DmaInfo[];
+extern uint16_t         g_usb1_host_DmaPipe[];
+extern uint16_t         g_usb1_host_DmaBval[];
+extern uint16_t         g_usb1_host_DmaStatus[];
+
+extern uint16_t         g_usb1_host_driver_state;
+extern uint16_t         g_usb1_host_ConfigNum;
+extern uint16_t         g_usb1_host_CmdStage;
+extern uint16_t         g_usb1_host_bchg_flag;
+extern uint16_t         g_usb1_host_detach_flag;
+extern uint16_t         g_usb1_host_attach_flag;
+
+extern uint16_t         g_usb1_host_UsbAddress;
+extern uint16_t         g_usb1_host_setUsbAddress;
+extern uint16_t         g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+extern uint16_t         g_usb1_host_UsbDeviceSpeed;
+extern uint16_t         g_usb1_host_SupportUsbDeviceSpeed;
+
+extern uint16_t         g_usb1_host_SavReq;
+extern uint16_t         g_usb1_host_SavVal;
+extern uint16_t         g_usb1_host_SavIndx;
+extern uint16_t         g_usb1_host_SavLen;
+
+extern uint16_t  g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t  g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+/* ==== common ==== */
+void        usb1_host_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void        usb1_host_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t    usb1_host_is_hispeed(void);
+uint16_t    usb1_host_is_hispeed_enable(void);
+uint16_t    usb1_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t    usb1_host_write_buffer(uint16_t pipe);
+uint16_t    usb1_host_write_buffer_c(uint16_t pipe);
+uint16_t    usb1_host_write_buffer_d0(uint16_t pipe);
+uint16_t    usb1_host_write_buffer_d1(uint16_t pipe);
+void        usb1_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t    usb1_host_read_buffer(uint16_t pipe);
+uint16_t    usb1_host_read_buffer_c(uint16_t pipe);
+uint16_t    usb1_host_read_buffer_d0(uint16_t pipe);
+uint16_t    usb1_host_read_buffer_d1(uint16_t pipe);
+uint16_t    usb1_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void        usb1_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void        usb1_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t    usb1_host_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t    usb1_host_read_dma(uint16_t pipe);
+void        usb1_host_stop_transfer(uint16_t pipe);
+void        usb1_host_brdy_int(uint16_t status, uint16_t int_enb);
+void        usb1_host_nrdy_int(uint16_t status, uint16_t int_enb);
+void        usb1_host_bemp_int(uint16_t status, uint16_t int_enb);
+void        usb1_host_setting_interrupt(uint8_t level);
+void        usb1_host_reset_module(uint16_t clockmode);
+uint16_t    usb1_host_get_buf_size(uint16_t pipe);
+uint16_t    usb1_host_get_mxps(uint16_t pipe);
+void        usb1_host_enable_brdy_int(uint16_t pipe);
+void        usb1_host_disable_brdy_int(uint16_t pipe);
+void        usb1_host_clear_brdy_sts(uint16_t pipe);
+void        usb1_host_enable_bemp_int(uint16_t pipe);
+void        usb1_host_disable_bemp_int(uint16_t pipe);
+void        usb1_host_clear_bemp_sts(uint16_t pipe);
+void        usb1_host_enable_nrdy_int(uint16_t pipe);
+void        usb1_host_disable_nrdy_int(uint16_t pipe);
+void        usb1_host_clear_nrdy_sts(uint16_t pipe);
+void        usb1_host_set_pid_buf(uint16_t pipe);
+void        usb1_host_set_pid_nak(uint16_t pipe);
+void        usb1_host_set_pid_stall(uint16_t pipe);
+void        usb1_host_clear_pid_stall(uint16_t pipe);
+uint16_t    usb1_host_get_pid(uint16_t pipe);
+void        usb1_host_set_sqclr(uint16_t pipe);
+void        usb1_host_set_sqset(uint16_t pipe);
+void        usb1_host_set_csclr(uint16_t pipe);
+void        usb1_host_aclrm(uint16_t pipe);
+void        usb1_host_set_aclrm(uint16_t pipe);
+void        usb1_host_clr_aclrm(uint16_t pipe);
+uint16_t    usb1_host_get_sqmon(uint16_t pipe);
+uint16_t    usb1_host_get_inbuf(uint16_t pipe);
+
+/* ==== host ==== */
+void        usb1_host_init_pipe_status(void);
+int32_t     usb1_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+void        usb1_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void        usb1_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+uint16_t    usb1_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table);
+void        usb1_host_StatusStage(void);
+void        usb1_host_get_devadd(uint16_t addr, uint16_t *devadd);
+void        usb1_host_set_devadd(uint16_t addr, uint16_t *devadd);
+void        usb1_host_InitModule(void);
+uint16_t    usb1_host_CheckAttach(void);
+void        usb1_host_UsbDetach(void);
+void        usb1_host_UsbDetach2(void);
+void        usb1_host_UsbAttach(void);
+uint16_t    usb1_host_UsbBusReset(void);
+int32_t     usb1_host_UsbResume(void);
+int32_t     usb1_host_UsbSuspend(void);
+void        usb1_host_Enable_DetachINT(void);
+void        usb1_host_Disable_DetachINT(void);
+void        usb1_host_UsbStateManager(void);
+
+
+#endif /* USB1_HOST_H */
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/inc/usb1_host_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_API_H
+#define USB1_HOST_API_H
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void        usb1_host_interrupt(uint32_t int_sense);
+void        usb1_host_dma_interrupt_d0fifo(uint32_t int_sense);
+void        usb1_host_dma_interrupt_d1fifo(uint32_t int_sense);
+
+uint16_t    usb1_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t     usb1_api_host_enumeration(uint16_t devadr);
+int32_t     usb1_api_host_detach(void);
+int32_t     usb1_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t     usb1_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t     usb1_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t     usb1_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t     usb1_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t     usb1_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t    usb1_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *Table);
+int32_t     usb1_api_host_data_count(uint16_t pipe, uint32_t *data_count);
+
+int32_t     usb1_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t     usb1_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t     usb1_api_host_SetConfig(uint16_t devadr, uint16_t confignum);
+int32_t     usb1_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t     usb1_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir);
+uint16_t    usb1_api_host_GetUsbDeviceState(void);
+
+void        usb1_api_host_elt_4_4(void);
+void        usb1_api_host_elt_4_5(void);
+void        usb1_api_host_elt_4_6(void);
+void        usb1_api_host_elt_4_7(void);
+void        usb1_api_host_elt_4_8(void);
+void        usb1_api_host_elt_4_9(void);
+void        usb1_api_host_elt_get_desc(void);
+
+void        usb1_host_EL_ModeInit(void);
+void        usb1_host_EL_SetUACT(void);
+void        usb1_host_EL_ClearUACT(void);
+void        usb1_host_EL_SetTESTMODE(uint16_t mode);
+void        usb1_host_EL_ClearNRDYSTS(uint16_t pipe);
+uint16_t    usb1_host_EL_GetINTSTS1(void);
+void        usb1_host_EL_UsbBusReset(void);
+void        usb1_host_EL_UsbAttach(void);
+void        usb1_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void        usb1_host_EL_StatusStage(void);
+void        usb1_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+int32_t     usb1_host_EL_UsbSuspend(void);
+int32_t     usb1_host_EL_UsbResume(void);
+
+#if 0   /* prototype in devdrv_usb_host_api.h */
+uint16_t    Userdef_USB_usb1_host_d0fifo_dmaintid(void);
+uint16_t    Userdef_USB_usb1_host_d1fifo_dmaintid(void);
+void        Userdef_USB_usb1_host_attach(void);
+void        Userdef_USB_usb1_host_detach(void);
+void        Userdef_USB_usb1_host_delay_1ms(void);
+void        Userdef_USB_usb1_host_delay_xms(uint32_t msec);
+void        Userdef_USB_usb1_host_delay_10us(uint32_t usec);
+void        Userdef_USB_usb1_host_delay_500ns(void);
+void        Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc);
+uint32_t    Userdef_USB_usb1_host_stop_dma0(void);
+uint32_t    Userdef_USB_usb1_host_stop_dma1(void);
+#endif
+
+#endif /* USB1_HOST_API_H */
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,139 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description  : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_DMACDRV_H
+#define USB1_HOST_DMACDRV_H
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+    uint32_t src_addr;      /* Transfer source address                */
+    uint32_t dst_addr;      /* Transfer destination address           */
+    uint32_t count;         /* Transfer byte count                    */
+    uint32_t src_size;      /* Transfer source data size              */
+    uint32_t dst_size;      /* Transfer destination data size         */
+    uint32_t saddr_dir;     /* Transfer source address direction      */
+    uint32_t daddr_dir;     /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE          (0)     /* Single transfer                   */
+#define DMAC_SAMPLE_CONTINUATION    (1)     /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER          (0)     /* Register mode */
+#define DMAC_MODE_LINK              (1)     /* Link mode     */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT           (0)     /* External request                   */
+#define DMAC_REQ_MODE_PERI          (1)     /* On-chip peripheral module request  */
+#define DMAC_REQ_MODE_SOFT          (2)     /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8           (0)     /* 8 bits    */
+#define DMAC_TRANS_SIZE_16          (1)     /* 16 bits   */
+#define DMAC_TRANS_SIZE_32          (2)     /* 32 bits   */
+#define DMAC_TRANS_SIZE_64          (3)     /* 64 bits   */
+#define DMAC_TRANS_SIZE_128         (4)     /* 128 bits  */
+#define DMAC_TRANS_SIZE_256         (5)     /* 256 bits  */
+#define DMAC_TRANS_SIZE_512         (6)     /* 512 bits  */
+#define DMAC_TRANS_SIZE_1024        (7)     /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC       (1)     /* Not increment */
+#define DMAC_TRANS_ADR_INC          (0)     /* Increment     */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL           (0)     /* Falling edge detection */
+#define DMAC_REQ_DET_RISE           (1)     /* Rising edge detection  */
+#define DMAC_REQ_DET_LOW            (2)     /* Low level detection    */
+#define DMAC_REQ_DET_HIGH           (3)     /* High level detection   */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC            (0)     /* DMAREQ is the source/ DMAACK is active when reading      */
+#define DMAC_REQ_DIR_DST            (1)     /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER            (0)     /* Header              */
+#define DMAC_DESC_SRC_ADDR          (1)     /* Source Address      */
+#define DMAC_DESC_DST_ADDR          (2)     /* Destination Address */
+#define DMAC_DESC_COUNT             (3)     /* Transaction Byte    */
+#define DMAC_DESC_CHCFG             (4)     /* Channel Confg       */
+#define DMAC_DESC_CHITVL            (5)     /* Channel Interval    */
+#define DMAC_DESC_CHEXT             (6)     /* Channel Extension   */
+#define DMAC_DESC_LINK_ADDR         (7)     /* Link Address        */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+    DMAC_REQ_USB0_DMA0_TX,      /* USB_0 channel 0 transmit FIFO empty            */
+    DMAC_REQ_USB0_DMA0_RX,      /* USB_0 channel 0 receive FIFO full              */
+    DMAC_REQ_USB0_DMA1_TX,      /* USB_0 channel 1 transmit FIFO empty            */
+    DMAC_REQ_USB0_DMA1_RX,      /* USB_0 channel 1 receive FIFO full              */
+    DMAC_REQ_USB1_DMA0_TX,      /* USB_1 channel 0 transmit FIFO empty            */
+    DMAC_REQ_USB1_DMA0_RX,      /* USB_1 channel 0 receive FIFO full              */
+    DMAC_REQ_USB1_DMA1_TX,      /* USB_1 channel 1 transmit FIFO empty            */
+    DMAC_REQ_USB1_DMA1_RX,      /* USB_1 channel 1 receive FIFO full              */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb1_host_DMAC3_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+                                 uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_host_DMAC3_Open(uint32_t req);
+void usb1_host_DMAC3_Close(uint32_t *remain);
+void usb1_host_DMAC3_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb1_host_DMAC4_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+                                 uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_host_DMAC4_Open(uint32_t req);
+void usb1_host_DMAC4_Close(uint32_t *remain);
+void usb1_host_DMAC4_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#endif  /* USB1_HOST_DMACDRV_H */
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/common/usb1_host_dataio.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,2835 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb1_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)];
+
+static void     usb1_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb1_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb1_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb1_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void     usb1_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb1_host_read_dma_d0(uint16_t pipe);
+static uint16_t usb1_host_read_dma_d1(uint16_t pipe);
+static uint16_t usb1_host_write_dma_d0(uint16_t pipe);
+static uint16_t usb1_host_write_dma_d1(uint16_t pipe);
+
+static void     usb1_host_read_c_fifo(uint16_t pipe, uint16_t count);
+static void     usb1_host_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void     usb1_host_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void     usb1_host_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void     usb1_host_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void     usb1_host_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void     usb1_host_clear_transaction_counter(uint16_t pipe);
+static void     usb1_host_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb1_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb1_host_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb1_host_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb1_host_start_send_transfer
+* Description  : Starts the USB data communication using pipe specified by the argument.
+* Arguments    : uint16_t  pipe    ; Pipe Number
+*              : uint32_t size     ; Data Size
+*              : uint8_t  *data    ; Data data Address
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t status;
+    uint16_t usefifo;
+    uint16_t mbw;
+
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    usb1_host_clear_bemp_sts(pipe);
+    usb1_host_clear_brdy_sts(pipe);
+    usb1_host_clear_nrdy_sts(pipe);
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+
+    usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+        case USB_HOST_D0FIFO_DMA:
+            usefifo = USB_HOST_D0USE;
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+        case USB_HOST_D1FIFO_DMA:
+            usefifo = USB_HOST_D1USE;
+        break;
+
+        default:
+            usefifo = USB_HOST_CUSE;
+        break;
+    };
+
+    usb1_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw);
+
+    usb1_host_clear_transaction_counter(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    status = usb1_host_write_buffer(pipe);
+
+    if (status != USB_HOST_FIFOERROR)
+    {
+        usb1_host_set_pid_buf(pipe);
+    }
+
+    return status;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer
+* Description  : Writes data in the buffer allocated in the pipe specified by
+*              : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer (uint16_t pipe)
+{
+    uint16_t status;
+    uint16_t usefifo;
+
+    g_usb1_host_PipeIgnore[pipe] = 0;
+    usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            status = usb1_host_write_buffer_d0(pipe);
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            status = usb1_host_write_buffer_d1(pipe);
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            status = usb1_host_write_dma_d0(pipe);
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            status = usb1_host_write_dma_d1(pipe);
+        break;
+
+        default:
+            status = usb1_host_write_buffer_c(pipe);
+        break;
+    };
+
+    switch (status)
+    {
+        case USB_HOST_WRITING:                      /* Continue of data write */
+            usb1_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+            usb1_host_enable_brdy_int(pipe);        /* Enable Ready Interrupt */
+        break;
+
+        case USB_HOST_WRITEEND:                     /* End of data write */
+        case USB_HOST_WRITESHRT:                    /* End of data write */
+            usb1_host_disable_brdy_int(pipe);       /* Disable Ready Interrupt */
+
+            usb1_host_clear_nrdy_sts(pipe);
+            usb1_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+
+            /* for last transfer */
+            usb1_host_enable_bemp_int(pipe);        /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_WRITEDMA:                     /* DMA write */
+            usb1_host_clear_nrdy_sts(pipe);
+            usb1_host_enable_nrdy_int(pipe);        /* Error (NORES or STALL) */
+        break;
+
+        case USB_HOST_FIFOERROR:                    /* FIFO access status */
+        default:
+            usb1_host_disable_brdy_int(pipe);       /* Disable Ready Interrupt */
+            usb1_host_disable_bemp_int(pipe);       /* Disable Empty Interrupt */
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_c
+* Description  : Writes data in the buffer allocated in the pipe specified in
+*              : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_c (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw);
+    }
+    else
+    {
+        buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+    }
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb1_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count  = g_usb1_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb1_host_write_c_fifo(pipe, (uint16_t)count);
+
+    if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb1_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB201.CFIFOCTR,
+                                USB_CFIFOCTR_BVAL_SHIFT,
+                                USB_CFIFOCTR_BVAL) == 0)
+        {
+            USB201.CFIFOCTR = USB_HOST_BITBVAL;             /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb1_host_data_count[pipe] -= count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_d0
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by CPU transfer using D0FIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw    = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb1_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count = g_usb1_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb1_host_write_d0_fifo(pipe, (uint16_t)count);
+
+    if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb1_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            USB201.D0FIFOCTR = USB_HOST_BITBVAL;            /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb1_host_data_count[pipe] -= count;
+    }
+
+    return status;                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_d1
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by CPU transfer using D1FIFO.
+* Arguments    : uint16_t pipe      ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          ; Write end
+*              : USB_HOST_WRITESHRT         ; short data
+*              : USB_HOST_WRITING           ; Continue of data write
+*              : USB_HOST_WRITEDMA          ; Write DMA
+*              : USB_HOST_FIFOERROR         ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size = usb1_host_get_buf_size(pipe);                    /* Data buffer size */
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+    {
+        status = USB_HOST_WRITEEND;                         /* write continues */
+        count  = g_usb1_host_data_count[pipe];
+
+        if (count == 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Null Packet is end of write */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_WRITESHRT;                    /* Short Packet is end of write */
+        }
+    }
+    else
+    {
+        status = USB_HOST_WRITING;                          /* write continues */
+        count  = (uint32_t)size;
+    }
+
+    usb1_host_write_d1_fifo(pipe, (uint16_t)count);
+
+    if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+    {
+        g_usb1_host_data_count[pipe] = 0;
+
+        if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            USB201.D1FIFOCTR = USB_HOST_BITBVAL;            /* Short Packet */
+        }
+    }
+    else
+    {
+        g_usb1_host_data_count[pipe] -= count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_dma_d0
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by DMA transfer using D0FIFO.
+*              : The DMA-ch for using is specified by Userdef_USB_usb1_host_start_dma().
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          : Write end
+*              : USB_HOST_WRITESHRT         : short data
+*              : USB_HOST_WRITING           : Continue of data write
+*              : USB_HOST_WRITEDMA          : Write DMA
+*              : USB_HOST_FIFOERROR         : FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_write_dma_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size  = usb1_host_get_buf_size(pipe);                   /* Data buffer size */
+    count = g_usb1_host_data_count[pipe];
+
+    if (count != 0)
+    {
+        g_usb1_host_DmaPipe[USB_HOST_D0FIFO] = pipe;
+
+        if ((count % size) != 0)
+        {
+            g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 1;
+        }
+        else
+        {
+            g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 0;
+        }
+
+        dfacc = usb1_host_set_dfacc_d0(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].fifo   = USB_HOST_D0FIFO_DMA;
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].dir    = USB_HOST_BUF2FIFO;
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].bytes  = count;
+
+        Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+        usb1_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+        RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+
+        g_usb1_host_data_count[pipe]    = 0;
+        g_usb1_host_data_pointer[pipe] += count;
+
+        status = USB_HOST_WRITEDMA;                         /* DMA write  */
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);        /* Short Packet */
+        }
+        status = USB_HOST_WRITESHRT;                        /* Short Packet is end of write */
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_dma_d1
+* Description  : Writes data in the buffer allocated in the pipe specified in the argument.
+*              : Writes data by DMA transfer using D1FIFO.
+*              : The DMA-ch for using is specified by Userdef_USB_usb1_host_start_dma().
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_WRITEEND          : Write end
+*              : USB_HOST_WRITESHRT         : short data
+*              : USB_HOST_WRITING           : Continue of data write
+*              : USB_HOST_WRITEDMA          : Write DMA
+*              : USB_HOST_FIFOERROR         : FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_write_dma_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint16_t size;
+    uint16_t buffer;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    size  = usb1_host_get_buf_size(pipe);                   /* Data buffer size */
+    count = g_usb1_host_data_count[pipe];
+
+    if (count != 0)
+    {
+        g_usb1_host_DmaPipe[USB_HOST_D1FIFO] = pipe;
+
+        if ((count % size) != 0)
+        {
+            g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 1;
+        }
+        else
+        {
+            g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 0;
+        }
+
+        dfacc = usb1_host_set_dfacc_d1(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].fifo   = USB_HOST_D1FIFO_DMA;
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].dir    = USB_HOST_BUF2FIFO;
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].bytes  = count;
+
+        Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+        usb1_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw , dfacc);
+
+        RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+
+        g_usb1_host_data_count[pipe]    = 0;
+        g_usb1_host_data_pointer[pipe] += count;
+
+        status = USB_HOST_WRITEDMA;                         /* DMA write */
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL) == 0)
+        {
+            RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);        /* Short Packet */
+        }
+        status = USB_HOST_WRITESHRT;                        /* Short Packet is end of write */
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_transfer
+* Description  : Starts USB data reception using the pipe specified in the argument.
+*              : The FIFO for using is set in the pipe definition table.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb1_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t usefifo;
+
+    usb1_host_clear_bemp_sts(pipe);
+    usb1_host_clear_brdy_sts(pipe);
+    usb1_host_clear_nrdy_sts(pipe);
+
+    usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            usb1_host_start_receive_trns_d0(pipe, size, data);
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            usb1_host_start_receive_trns_d1(pipe, size, data);
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            usb1_host_start_receive_dma_d0(pipe, size, data);
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            usb1_host_start_receive_dma_d1(pipe, size, data);
+        break;
+
+        default:
+            usb1_host_start_receive_trns_c(pipe, size, data);
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_c
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using CFIFO.
+*              : When storing data in the buffer allocated in the pipe specified in the
+*              : argument, BRDY interrupt is generated to read data
+*              : in the interrupt.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb1_host_set_pid_nak(pipe);
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_PipeIgnore[pipe]   = 0;
+
+    g_usb1_host_PipeDataSize[pipe] = size;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw);
+    USB201.CFIFOCTR = USB_HOST_BITBCLR;
+
+    usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    usb1_host_enable_nrdy_int(pipe);
+    usb1_host_enable_brdy_int(pipe);
+
+    usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, BRDY interrupt is generated to read data in the
+*              : interrupt.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb1_host_set_pid_nak(pipe);
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_PipeIgnore[pipe]   = 0;
+
+    g_usb1_host_PipeDataSize[pipe] = size;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    usb1_host_enable_nrdy_int(pipe);
+    usb1_host_enable_brdy_int(pipe);
+
+    usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_d1
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using D1FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, BRDY interrupt is generated to read data.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb1_host_set_pid_nak(pipe);
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_PipeIgnore[pipe]   = 0;
+
+    g_usb1_host_PipeDataSize[pipe] = size;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    usb1_host_enable_nrdy_int(pipe);
+    usb1_host_enable_brdy_int(pipe);
+
+    usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_dma_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, delivered read request to DMAC to read data from
+*              : the buffer by DMAC.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb1_host_set_pid_nak(pipe);
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_PipeIgnore[pipe]   = 0;
+
+    g_usb1_host_PipeDataSize[pipe] = 0;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        usb1_host_read_dma(pipe);
+
+        usb1_host_enable_nrdy_int(pipe);
+        usb1_host_enable_brdy_int(pipe);
+    }
+    else
+    {
+        usb1_host_enable_nrdy_int(pipe);
+        usb1_host_enable_brdy_int(pipe);
+    }
+
+    usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_dma_d1
+* Description  : Read data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+*              : This function does not read data from the buffer.
+*              : When storing data in the buffer allocated in the pipe specified
+*              : in the argument, delivered read request to DMAC to read data from
+*              : the buffer by DMAC.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint32_t  size     ; Data Size
+*              : uint8_t  *data     ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+    uint16_t mbw;
+
+    usb1_host_set_pid_nak(pipe);
+    g_usb1_host_data_count[pipe]   = size;
+    g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+    g_usb1_host_PipeIgnore[pipe]   = 0;
+
+    g_usb1_host_PipeDataSize[pipe] = 0;
+    g_usb1_host_pipe_status[pipe]  = USB_HOST_PIPE_WAIT;
+
+    mbw = usb1_host_get_mbw(size, (uint32_t)data);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        usb1_host_read_dma(pipe);
+
+        usb1_host_enable_nrdy_int(pipe);
+        usb1_host_enable_brdy_int(pipe);
+    }
+    else
+    {
+        usb1_host_enable_nrdy_int(pipe);
+        usb1_host_enable_brdy_int(pipe);
+    }
+
+    usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Uses FIF0 set in the pipe definition table.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer (uint16_t pipe)
+{
+    uint16_t status;
+
+    g_usb1_host_PipeIgnore[pipe] = 0;
+
+    if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+    {
+        status = usb1_host_read_buffer_d0(pipe);
+    }
+    else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+    {
+        status = usb1_host_read_buffer_d1(pipe);
+    }
+    else
+    {
+        status = usb1_host_read_buffer_c(pipe);
+    }
+
+    switch (status)
+    {
+        case USB_HOST_READING:                                  /* Continue of data read */
+        break;
+
+        case USB_HOST_READEND:                                  /* End of data read */
+        case USB_HOST_READSHRT:                                 /* End of data read */
+            usb1_host_disable_brdy_int(pipe);
+            g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+            g_usb1_host_pipe_status[pipe]   = USB_HOST_PIPE_DONE;
+        break;
+
+        case USB_HOST_READOVER:                                 /* buffer over */
+            if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+            {
+                USB201.D0FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+            }
+            else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+            {
+                USB201.D1FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+            }
+            else
+            {
+                USB201.CFIFOCTR = USB_HOST_BITBCLR;                 /* Clear BCLR */
+            }
+            usb1_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+#if(1) /* ohci_wrapp */
+            g_usb1_host_pipe_status[pipe]   = USB_HOST_PIPE_DONE;
+#else
+            g_usb1_host_pipe_status[pipe]   = USB_HOST_PIPE_ERROR;
+#endif
+            g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+        break;
+
+        case USB_HOST_FIFOERROR:                                    /* FIFO access status */
+        default:
+            usb1_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                      /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_c
+* Description  : Reads data from the buffer allocated in the pipe specified in the argument.
+*              : Reads data by CPU transfer using CFIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_c (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+
+    mbw    = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb1_host_data_count[pipe];
+    }
+    else if (g_usb1_host_data_count[pipe] == dtln)          /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB201.CFIFOCTR = USB_HOST_BITBCLR;                 /* Clear BCLR */
+    }
+    else
+    {
+        usb1_host_read_c_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb1_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_d0
+* Description  : Reads data from the buffer allocated in the pipe specified in
+*              : the argument.
+*              : Reads data by CPU transfer using D0FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t pipebuf_size;
+
+    mbw    = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb1_host_data_count[pipe];
+    }
+    else if (g_usb1_host_data_count[pipe] == dtln)      /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+        else
+        {
+            pipebuf_size = usb1_host_get_buf_size(pipe);    /* Data buffer size */
+
+            if (count != pipebuf_size)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+                usb1_host_set_pid_nak(pipe);                /* Set NAK */
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB201.D0FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+    }
+    else
+    {
+        usb1_host_read_d0_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb1_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_d1
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by CPU transfer using D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t pipebuf_size;
+
+    mbw    = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+    buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+    if (buffer == USB_HOST_FIFOERROR)                       /* FIFO access status */
+    {
+        return USB_HOST_FIFOERROR;
+    }
+
+    dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+    mxps = usb1_host_get_mxps(pipe);                        /* Max Packet Size */
+
+    if (g_usb1_host_data_count[pipe] < dtln)                /* Buffer Over ? */
+    {
+        status = USB_HOST_READOVER;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = g_usb1_host_data_count[pipe];
+    }
+    else if (g_usb1_host_data_count[pipe] == dtln)      /* just Receive Size */
+    {
+        status = USB_HOST_READEND;
+        usb1_host_set_pid_nak(pipe);                        /* Set NAK */
+        count = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+        }
+
+        if ((count % mxps) !=0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+        }
+    }
+    else                                                    /* continue Receive data */
+    {
+        status = USB_HOST_READING;
+        count  = dtln;
+
+        if (count == 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Null Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+
+        if ((count % mxps) != 0)
+        {
+            status = USB_HOST_READSHRT;                     /* Short Packet receive */
+            usb1_host_set_pid_nak(pipe);                    /* Set NAK */
+        }
+        else
+        {
+            pipebuf_size = usb1_host_get_buf_size(pipe);    /* Data buffer size */
+            if (count != pipebuf_size)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+                usb1_host_set_pid_nak(pipe);                /* Set NAK */
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        USB201.D1FIFOCTR = USB_HOST_BITBCLR;                /* Clear BCLR */
+    }
+    else
+    {
+        usb1_host_read_d1_fifo(pipe, (uint16_t)count);
+    }
+
+    g_usb1_host_data_count[pipe] -= count;
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma
+* Description  : Reads data from the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_dma (uint16_t pipe)
+{
+    uint16_t status;
+
+    g_usb1_host_PipeIgnore[pipe] = 0;
+
+    if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+    {
+        status = usb1_host_read_dma_d0(pipe);
+    }
+    else
+    {
+        status = usb1_host_read_dma_d1(pipe);
+    }
+
+    switch (status)
+    {
+        case USB_HOST_READING:                                      /* Continue of data read */
+        break;
+
+        case USB_HOST_READZERO:                                     /* End of data read */
+            usb1_host_disable_brdy_int(pipe);
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+        break;
+
+        case USB_HOST_READEND:                                      /* End of data read */
+        case USB_HOST_READSHRT:                                     /* End of data read */
+            usb1_host_disable_brdy_int(pipe);
+
+            if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+            {
+                g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+            }
+        break;
+
+        case USB_HOST_READOVER:                                     /* buffer over */
+            usb1_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+
+            if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+            {
+                g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+            }
+#if(1) /* ohci_wrapp */
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+        break;
+
+        case USB_HOST_FIFOERROR:                                    /* FIFO access status */
+        default:
+            usb1_host_disable_brdy_int(pipe);                       /* Disable Ready Interrupt */
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+        break;
+    }
+
+    return status;                                                  /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma_d0
+* Description  : Writes data in the buffer allocated in the pipe specified
+*              : in the argument.
+*              : Reads data by DMA transfer using D0FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_read_dma_d0 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+    uint16_t pipebuf_size;
+
+    g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        count  = g_usb1_host_data_count[pipe];
+        status = USB_HOST_READING;
+    }
+    else
+    {
+        buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+        if (buffer == USB_HOST_FIFOERROR)                   /* FIFO access status */
+        {
+            return USB_HOST_FIFOERROR;
+        }
+
+        dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+        mxps = usb1_host_get_mxps(pipe);                    /* Max Packet Size */
+
+        if (g_usb1_host_data_count[pipe] < dtln)            /* Buffer Over ? */
+        {
+            status = USB_HOST_READOVER;
+            count  = g_usb1_host_data_count[pipe];
+        }
+        else if (g_usb1_host_data_count[pipe] == dtln)  /* just Receive Size */
+        {
+            status = USB_HOST_READEND;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+        }
+        else                                                /* continue Receive data */
+        {
+            status = USB_HOST_READING;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+            else
+            {
+                pipebuf_size = usb1_host_get_buf_size(pipe);    /* Data buffer size */
+
+                if (count != pipebuf_size)
+                {
+                    status = USB_HOST_READSHRT;             /* Short Packet receive */
+                }
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+        {
+            USB201.D0FIFOCTR = USB_HOST_BITBCLR;            /* Clear BCLR */
+            status = USB_HOST_READZERO;                     /* Null Packet receive */
+        }
+        else
+        {
+            usb1_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+                                                            /* transaction counter No set */
+                                                            /* FRDY = 1, DTLN = 0 -> BRDY */
+        }
+    }
+    else
+    {
+        dfacc = usb1_host_set_dfacc_d0(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb1_host_DmaPipe[USB_HOST_D0FIFO] = pipe;        /* not use in read operation */
+        g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 0;           /* not use in read operation */
+
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].fifo   = USB_HOST_D0FIFO_DMA;
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].dir    = USB_HOST_FIFO2BUF;
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+        g_usb1_host_DmaInfo[USB_HOST_D0FIFO].bytes  = count;
+
+        if (status == USB_HOST_READING)
+        {
+            g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY;
+        }
+        else
+        {
+            g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND;
+        }
+
+        Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+        usb1_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw , dfacc);
+
+        RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+    {
+        g_usb1_host_data_count[pipe]   -= count;
+        g_usb1_host_data_pointer[pipe] += count;
+        g_usb1_host_PipeDataSize[pipe] += count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma_d1
+* Description  : Reads data from the buffer allocated in the pipe specified in
+*              : the argument.
+*              : Reads data by DMA transfer using D1FIFO.
+* Arguments    : uint16_t pipe     ; Pipe Number
+* Return Value : USB_HOST_READEND          ; Read end
+*              : USB_HOST_READSHRT         ; short data
+*              : USB_HOST_READZERO         ; zero data
+*              : USB_HOST_READING          ; Continue of data read
+*              : USB_HOST_READOVER         ; buffer over
+*              : USB_HOST_FIFOERROR        ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_read_dma_d1 (uint16_t pipe)
+{
+    uint32_t count;
+    uint32_t dtln;
+    uint16_t buffer;
+    uint16_t mxps;
+    uint16_t status;
+    uint16_t mbw;
+    uint16_t dfacc = 0;
+    uint16_t pipebuf_size;
+
+    g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        count  = g_usb1_host_data_count[pipe];
+        status = USB_HOST_READING;
+    }
+    else
+    {
+        buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+        if (buffer == USB_HOST_FIFOERROR)                   /* FIFO access status */
+        {
+            return USB_HOST_FIFOERROR;
+        }
+
+        dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+        mxps = usb1_host_get_mxps(pipe);                    /* Max Packet Size */
+
+        if (g_usb1_host_data_count[pipe] < dtln)            /* Buffer Over ? */
+        {
+            status = USB_HOST_READOVER;
+            count  = g_usb1_host_data_count[pipe];
+        }
+        else if (g_usb1_host_data_count[pipe] == dtln)  /* just Receive Size */
+        {
+            status = USB_HOST_READEND;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+        }
+        else                                                /* continue Receive data */
+        {
+            status = USB_HOST_READING;
+            count  = dtln;
+
+            if (count == 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Null Packet receive */
+            }
+
+            if ((count % mxps) != 0)
+            {
+                status = USB_HOST_READSHRT;                 /* Short Packet receive */
+            }
+            else
+            {
+                pipebuf_size = usb1_host_get_buf_size(pipe);    /* Data buffer size */
+
+                if (count != pipebuf_size)
+                {
+                    status = USB_HOST_READSHRT;             /* Short Packet receive */
+                }
+            }
+        }
+    }
+
+    if (count == 0)                                         /* 0 length packet */
+    {
+        if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+        {
+            USB201.D1FIFOCTR = USB_HOST_BITBCLR;            /* Clear BCLR */
+            status = USB_HOST_READZERO;                     /* Null Packet receive */
+        }
+        else
+        {
+            usb1_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+                                                            /* transaction counter No set */
+                                                            /* FRDY = 1, DTLN = 0 -> BRDY */
+        }
+    }
+    else
+    {
+        dfacc = usb1_host_set_dfacc_d1(mbw, count);
+
+        if (mbw == USB_HOST_BITMBW_32)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 2;  /* 32bit transfer */
+        }
+        else if (mbw == USB_HOST_BITMBW_16)
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 1;  /* 16bit transfer */
+        }
+        else
+        {
+            g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 0;  /* 8bit transfer */
+        }
+
+        g_usb1_host_DmaPipe[USB_HOST_D1FIFO] = pipe;        /* not use in read operation */
+        g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 0;           /* not use in read operation */
+
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].fifo   = USB_HOST_D1FIFO_DMA;
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].dir    = USB_HOST_FIFO2BUF;
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+        g_usb1_host_DmaInfo[USB_HOST_D1FIFO].bytes  = count;
+
+        if (status == USB_HOST_READING)
+        {
+            g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY;
+        }
+        else
+        {
+            g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND;
+        }
+
+        Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+        usb1_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw , dfacc);
+
+        RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+                            1,
+                            USB_DnFIFOSEL_DREQE_SHIFT,
+                            USB_DnFIFOSEL_DREQE);
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+    {
+        g_usb1_host_data_count[pipe]   -= count;
+        g_usb1_host_data_pointer[pipe] += count;
+        g_usb1_host_PipeDataSize[pipe] += count;
+    }
+
+    return status;                                          /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_change_fifo_port
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument. After allocating FIF0, waits in the software
+*              : till the corresponding pipe becomes ready.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+* Return Value : USB_HOST_FIFOERROR         ; Error
+*              : Others            ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb1_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+    uint16_t          buffer;
+    uint32_t          loop;
+    volatile uint32_t loop2;
+
+    usb1_host_set_curpipe(pipe, fifosel, isel, mbw);
+
+    for (loop = 0; loop < 4; loop++)
+    {
+        switch (fifosel)
+        {
+            case USB_HOST_CUSE:
+                buffer = USB201.CFIFOCTR;
+            break;
+
+            case USB_HOST_D0USE:
+            case USB_HOST_D0DMA:
+                buffer = USB201.D0FIFOCTR;
+            break;
+
+            case USB_HOST_D1USE:
+            case USB_HOST_D1DMA:
+                buffer = USB201.D1FIFOCTR;
+            break;
+
+            default:
+                buffer = 0;
+            break;
+        }
+
+        if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY)
+        {
+            return buffer;
+        }
+
+        loop2 = 25;
+
+        while (loop2-- > 0)
+        {
+            /* wait */
+        }
+    }
+
+    return USB_HOST_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_curpipe
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+    uint16_t          buffer;
+    uint32_t          loop;
+    volatile uint32_t loop2;
+
+    g_usb1_host_mbw[pipe] = mbw;
+
+    switch (fifosel)
+    {
+        case USB_HOST_CUSE:
+            buffer  = USB201.CFIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+            buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+            USB201.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(isel | pipe | mbw);
+            USB201.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D0DMA:
+        case USB_HOST_D0USE:
+            buffer  = USB201.D0FIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+            USB201.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB201.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D1DMA:
+        case USB_HOST_D1USE:
+            buffer  = USB201.D1FIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+            USB201.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB201.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        default:
+        break;
+    }
+
+    /* Cautions !!!
+     * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+     * For details, please look at the data sheet.   */
+    loop2 = 100;
+
+    while (loop2-- > 0)
+    {
+        /* wait */
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_curpipe2
+* Description  : Allocates FIF0 specified by the argument in the pipe assigned
+*              : by the argument.(DFACC)
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t fifosel   ; Select FIFO
+*              : uint16_t isel      ; FIFO Access Direction
+*              : uint16_t mbw       ; FIFO Port Access Bit Width
+*              : uint16_t dfacc     ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+    uint16_t buffer;
+    uint32_t loop;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+    uint32_t dummy;
+#endif
+    volatile uint32_t loop2;
+
+    g_usb1_host_mbw[pipe] = mbw;
+
+    switch (fifosel)
+    {
+        case USB_HOST_CUSE:
+            buffer  = USB201.CFIFOSEL;
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+            buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+            USB201.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+            buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(isel | pipe | mbw);
+            USB201.CFIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+                        == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D0DMA:
+        case USB_HOST_D0USE:
+            buffer  = USB201.D0FIFOSEL;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+            if (dfacc != 0)
+            {
+                buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+            }
+#else
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+            USB201.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            if (dfacc != 0)
+            {
+                dummy = USB201.D0FIFO.UINT32;
+            }
+#endif
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB201.D0FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        case USB_HOST_D1DMA:
+        case USB_HOST_D1USE:
+            buffer  = USB201.D1FIFOSEL;
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+            if (dfacc != 0)
+            {
+                buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+            }
+#else
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+            USB201.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+
+#ifdef  __USB_HOST_DF_ACC_ENABLE__
+            if (dfacc != 0)
+            {
+                dummy = USB201.D1FIFO.UINT32;
+                loop = dummy;                   // avoid warning.
+            }
+#endif
+
+            buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+            buffer |= (uint16_t)(pipe | mbw);
+            USB201.D1FIFOSEL = buffer;
+
+            for (loop = 0; loop < 4; loop++)
+            {
+                if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+                {
+                    break;
+                }
+
+                loop2 = 100;
+                while (loop2-- > 0)
+                {
+                    /* wait */
+                }
+            }
+        break;
+
+        default:
+        break;
+    }
+
+    /* Cautions !!!
+     * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+     * For details, please look at the data sheet.   */
+    loop2 = 100;
+    while (loop2-- > 0)
+    {
+        /* wait */
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_c_fifo
+* Description  : Writes data in CFIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB201.CFIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB201.CFIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB201.CFIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_c_fifo
+* Description  : Reads data from CFIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb1_host_data_pointer[pipe] = USB201.CFIFO.UINT8[HH];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.CFIFO.UINT16[H];
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.CFIFO.UINT32;
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_d0_fifo
+* Description  : Writes data in D0FIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating CFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB201.D0FIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB201.D0FIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB201.D0FIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_d0_fifo
+* Description  : Reads data from D0FIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating DOFIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb0_host_mbw[].
+* Arguments    : uint16_t  Pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb1_host_data_pointer[pipe] = USB201.D0FIFO.UINT8[HH];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.D0FIFO.UINT16[H];
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.D0FIFO.UINT32;
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_d1_fifo
+* Description  : Writes data in D1FIFO.
+*              : Writes data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating D1FIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            USB201.D1FIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)(count / 2); even; --even)
+        {
+            USB201.D1FIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)(count / 4); even; --even)
+        {
+            USB201.D1FIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_d1_fifo
+* Description  : Reads data from D1FIFO.
+*              : Reads data by BYTE/WORD/LONG according to access size
+*              : to the pipe specified by the arguments.
+*              : Before executing this function, allocating D1FIF0 in the specified pipe
+*              : should be completed.
+*              : Before executing this function, access size to the specified pipe
+*              : should be fixed and set in g_usb1_host_mbw[].
+* Arguments    : uint16_t  pipe     ; Pipe Number
+*              : uint16_t count     ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+    uint16_t even;
+
+    if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+    {
+        for (even = count; even; --even)
+        {
+            *g_usb1_host_data_pointer[pipe] = USB201.D1FIFO.UINT8[HH];
+            g_usb1_host_data_pointer[pipe] += 1;
+        }
+    }
+    else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+    {
+        for (even = (uint16_t)((count + 1) / 2); even; --even)
+        {
+            *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.D1FIFO.UINT16[H];
+            g_usb1_host_data_pointer[pipe] += 2;
+        }
+    }
+    else
+    {
+        for (even = (uint16_t)((count + 3) / 4); even; --even)
+        {
+            *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.D1FIFO.UINT32;
+            g_usb1_host_data_pointer[pipe] += 4;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_com_get_dmasize
+* Description  : Calculates access width of DMA transfer by the argument to
+                 return as the Return Value.
+* Arguments    : uint32_t trncount   : transfer byte
+*              : uint32_t dtptr      : transfer data pointer
+* Return Value : DMA transfer size    : 0   8bit
+*              :                      : 1  16bit
+*              :                      : 2  32bit
+*******************************************************************************/
+static uint32_t usb1_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+    uint32_t size;
+
+    if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+    {
+        /*  When transfer byte count is odd         */
+        /* or transfer data area is 8-bit alignment */
+        size = 0;           /* 8bit */
+    }
+    else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+    {
+        /* When the transfer byte count is multiples of 2 */
+        /* or the transfer data area is 16-bit alignment */
+        size = 1;           /* 16bit */
+    }
+    else
+    {
+        /* When the transfer byte count is multiples of 4 */
+        /* or the transfer data area is 32-bit alignment */
+        size = 2;           /* 32bit */
+    }
+
+    return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_mbw
+* Description  : Calculates access width of DMA to return the value set in MBW.
+* Arguments    : uint32_t trncount   : transfer byte
+*              : uint32_t dtptr      : transfer data pointer
+* Return Value : FIFO transfer size   : USB_HOST_BITMBW_8    8bit
+*              :                      : USB_HOST_BITMBW_16  16bit
+*              :                      : USB_HOST_BITMBW_32  32bit
+*******************************************************************************/
+uint16_t usb1_host_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+    uint32_t size;
+    uint16_t mbw;
+
+    size = usb1_host_com_get_dmasize(trncount, dtptr);
+
+    if (size == 0)
+    {
+        /* 8bit */
+        mbw = USB_HOST_BITMBW_8;
+    }
+    else if (size == 1)
+    {
+        /* 16bit */
+        mbw = USB_HOST_BITMBW_16;
+    }
+    else
+    {
+        /* 32bit */
+        mbw = USB_HOST_BITMBW_32;
+    }
+
+    return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_transaction_counter
+* Description  : Sets transaction counter by the argument(PIPEnTRN).
+*              : Clears transaction before setting to enable transaction counter setting.
+* Arguments    : uint16_t pipe     ; Pipe number
+*              : uint32_t bsize    : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+    uint16_t mxps;
+    uint16_t cnt;
+
+    if (bsize == 0)
+    {
+        return;
+    }
+
+    mxps = usb1_host_get_mxps(pipe);            /* Max Packet Size */
+
+    if ((bsize % mxps) == 0)
+    {
+        cnt = (uint16_t)(bsize / mxps);
+    }
+    else
+    {
+        cnt = (uint16_t)((bsize / mxps) + 1);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE1TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE2TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE3TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE4TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE5TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+            USB201.PIPE9TRN             = cnt;
+            RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_transaction_counter
+* Description  : Clears the transaction counter by the argument.
+*              : After executing this function, the transaction counter is invalid.
+* Arguments    : uint16_t pipe     ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_transaction_counter (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+                                0,
+                                USB_PIPEnTRE_TRENB_SHIFT,
+                                USB_PIPEnTRE_TRENB);
+            RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+                                1,
+                                USB_PIPEnTRE_TRCLR_SHIFT,
+                                USB_PIPEnTRE_TRCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_stop_transfer
+* Description  : Stops the USB transfer in the pipe specified by the argument.
+*              : After stopping the USB transfer, clears the buffer allocated in
+*              : the pipe.
+*              : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0;
+*              : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+*              : in the corresponding pipe becomes invalid. Sequence bit is also
+*              : cleared.
+* Arguments    : uint16_t  pipe     ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_stop_transfer (uint16_t pipe)
+{
+    uint16_t usefifo;
+    uint32_t remain;
+
+    usb1_host_set_pid_nak(pipe);
+
+    usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    switch (usefifo)
+    {
+        case USB_HOST_D0FIFO_USE:
+            usb1_host_clear_transaction_counter(pipe);
+            USB201.D0FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D1FIFO_USE:
+            usb1_host_clear_transaction_counter(pipe);
+            USB201.D1FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D0FIFO_DMA:
+            remain = Userdef_USB_usb1_host_stop_dma0();
+            usb1_host_dma_stop_d0(pipe, remain);
+            usb1_host_clear_transaction_counter(pipe);
+            USB201.D0FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        case USB_HOST_D1FIFO_DMA:
+            remain = Userdef_USB_usb1_host_stop_dma1();
+            usb1_host_dma_stop_d1(pipe, remain);
+            usb1_host_clear_transaction_counter(pipe);
+            USB201.D1FIFOCTR = USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+
+        default:
+            usb1_host_clear_transaction_counter(pipe);
+            USB201.CFIFOCTR =  USB_HOST_BITBCLR;        /* Buffer Clear */
+        break;
+    }
+
+    /* Interrupt of pipe set is disabled */
+    usb1_host_disable_brdy_int(pipe);
+    usb1_host_disable_nrdy_int(pipe);
+    usb1_host_disable_bemp_int(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+    usb1_host_aclrm(pipe);
+#endif
+    usb1_host_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_dfacc_d0
+* Description  : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments    : uint16_t mbw     ; MBW
+*              : uint16_t count   ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_host_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+    uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                        0,
+                        USB_DnFBCFG_DFACC_SHIFT,
+                        USB_DnFBCFG_DFACC);
+    RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                        0,
+                        USB_DnFBCFG_TENDE_SHIFT,
+                        USB_DnFBCFG_TENDE);
+    dfacc = 0;
+#else
+    if (mbw == USB_HOST_BITMBW_32)
+    {
+        if ((count % 32) == 0)
+        {
+            /* 32byte transfer */
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                2,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 2;
+        }
+        else if ((count % 16) == 0)
+        {
+            /* 16byte transfer */
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                1,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 1;
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 0;
+        }
+    }
+    else if (mbw == USB_HOST_BITMBW_16)
+    {
+        RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+#endif
+
+    return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_dfacc_d1
+* Description  : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments    : uint16_t mbw     ; MBW
+*              : uint16_t count   ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_host_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+    uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                        0,
+                        USB_DnFBCFG_DFACC_SHIFT,
+                        USB_DnFBCFG_DFACC);
+    RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                        0,
+                        USB_DnFBCFG_TENDE_SHIFT,
+                        USB_DnFBCFG_TENDE);
+    dfacc = 0;
+#else
+    if (mbw == USB_HOST_BITMBW_32)
+    {
+        if ((count % 32) == 0)
+        {
+            /* 32byte transfer */
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                2,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 2;
+        }
+        else if ((count % 16) == 0)
+        {
+            /* 16byte transfer */
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                1,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 1;
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+            RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                                0,
+                                USB_DnFBCFG_TENDE_SHIFT,
+                                USB_DnFBCFG_TENDE);
+            dfacc = 0;
+        }
+    }
+    else if (mbw == USB_HOST_BITMBW_16)
+    {
+        RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_DFACC_SHIFT,
+                            USB_DnFBCFG_DFACC);
+        RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+                            0,
+                            USB_DnFBCFG_TENDE_SHIFT,
+                            USB_DnFBCFG_TENDE);
+        dfacc = 0;
+    }
+#endif
+
+    return dfacc;
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/common/usb1_host_dma.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,355 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+/* #include "usb1_host_dmacdrv.h" */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb1_host_dmaint(uint16_t fifo);
+static void usb1_host_dmaint_buf2fifo(uint16_t pipe);
+static void usb1_host_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_stop_d0
+* Description  : D0FIFO DMA stop
+* Arguments    : uint16_t pipe     : pipe number
+*              : uint32_t remain   : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+    uint16_t dtln;
+    uint16_t dfacc;
+    uint16_t buffer;
+    uint16_t sds_b = 1;
+
+    dfacc = RZA_IO_RegRead_16(&USB201.D0FBCFG,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+    if (dfacc == 2)
+    {
+        sds_b = 32;
+    }
+    else if (dfacc == 1)
+    {
+        sds_b = 16;
+    }
+    else
+    {
+        if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 2)
+        {
+            sds_b = 4;
+        }
+        else if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 1)
+        {
+            sds_b = 2;
+        }
+        else
+        {
+            sds_b = 1;
+        }
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+        {
+            buffer = USB201.D0FIFOCTR;
+            dtln   = (buffer & USB_HOST_BITDTLN);
+
+            if ((dtln % sds_b) != 0)
+            {
+                remain += (sds_b - (dtln % sds_b));
+            }
+            g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain);
+            g_usb1_host_data_count[pipe]   = remain;
+        }
+    }
+
+    RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+                        0,
+                        USB_DnFIFOSEL_DREQE_SHIFT,
+                        USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_stop_d1
+* Description  : D1FIFO DMA stop
+* Arguments    : uint16_t pipe     : pipe number
+*              : uint32_t remain   : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+    uint16_t dtln;
+    uint16_t dfacc;
+    uint16_t buffer;
+    uint16_t sds_b = 1;
+
+    dfacc = RZA_IO_RegRead_16(&USB201.D1FBCFG,
+                                USB_DnFBCFG_DFACC_SHIFT,
+                                USB_DnFBCFG_DFACC);
+    if (dfacc == 2)
+    {
+        sds_b = 32;
+    }
+    else if (dfacc == 1)
+    {
+        sds_b = 16;
+    }
+    else
+    {
+        if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 2)
+        {
+            sds_b = 4;
+        }
+        else if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 1)
+        {
+            sds_b = 2;
+        }
+        else
+        {
+            sds_b = 1;
+        }
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+    {
+        if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+        {
+            buffer = USB201.D1FIFOCTR;
+            dtln = (buffer & USB_HOST_BITDTLN);
+
+            if ((dtln % sds_b) != 0)
+            {
+                remain += (sds_b - (dtln % sds_b));
+            }
+            g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain);
+            g_usb1_host_data_count[pipe]   = remain;
+        }
+    }
+
+    RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+                        0,
+                        USB_DnFIFOSEL_DREQE_SHIFT,
+                        USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_interrupt_d0fifo
+* Description  : This function is DMA interrupt handler entry.
+*              : Execute usb1_host_dmaint() after disabling DMA interrupt in this function.
+*              : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is
+*              : specified by dma->fifo.
+*              : Register this function as DMA complete interrupt.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+    usb1_host_dmaint(USB_HOST_D0FIFO);
+    g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_interrupt_d1fifo
+* Description  : This function is DMA interrupt handler entry.
+*              : Execute usb0_host_dmaint() after disabling DMA interrupt in this function.
+*              : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is
+*              : specified by dma->fifo.
+*              : Register this function as DMA complete interrupt.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+    usb1_host_dmaint(USB_HOST_D1FIFO);
+    g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint
+* Description  : This function is DMA transfer end interrupt
+* Arguments    : uint16_t fifo  ; fifo number
+*              :                ;  USB_HOST_D0FIFO
+*              :                ;  USB_HOST_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint (uint16_t fifo)
+{
+    uint16_t pipe;
+
+    pipe = g_usb1_host_DmaPipe[fifo];
+
+    if (g_usb1_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO)
+    {
+        usb1_host_dmaint_buf2fifo(pipe);
+    }
+    else
+    {
+        usb1_host_dmaint_fifo2buf(pipe);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint_fifo2buf
+* Description  : Executes read completion from FIFO by DMAC.
+* Arguments    : uint16_t pipe       : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint_fifo2buf (uint16_t pipe)
+{
+    uint32_t remain;
+    uint16_t useport;
+
+    if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+    {
+        useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+        if (useport == USB_HOST_D0FIFO_DMA)
+        {
+            remain = Userdef_USB_usb1_host_stop_dma0();
+            usb1_host_dma_stop_d0(pipe, remain);
+
+            if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+            {
+                if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND)
+                {
+                    USB201.D0FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+                else
+                {
+                    usb1_host_enable_brdy_int(pipe);
+                }
+            }
+        }
+        else
+        {
+            remain = Userdef_USB_usb1_host_stop_dma1();
+            usb1_host_dma_stop_d1(pipe, remain);
+
+            if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+            {
+                if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND)
+                {
+                    USB201.D1FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+                else
+                {
+                    usb1_host_enable_brdy_int(pipe);
+                }
+            }
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint_buf2fifo
+* Description  : Executes write completion in FIFO by DMAC.
+* Arguments    : uint16_t pipe     : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint_buf2fifo (uint16_t pipe)
+{
+    uint16_t useport;
+    uint32_t remain;
+
+    useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+    if (useport == USB_HOST_D0FIFO_DMA)
+    {
+        remain = Userdef_USB_usb1_host_stop_dma0();
+        usb1_host_dma_stop_d0(pipe, remain);
+
+        if (g_usb1_host_DmaBval[USB_HOST_D0FIFO] != 0)
+        {
+            RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);
+        }
+    }
+    else
+    {
+        remain = Userdef_USB_usb1_host_stop_dma1();
+        usb1_host_dma_stop_d1(pipe, remain);
+
+        if (g_usb1_host_DmaBval[USB_HOST_D1FIFO] != 0)
+        {
+            RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
+                                1,
+                                USB_DnFIFOCTR_BVAL_SHIFT,
+                                USB_DnFIFOCTR_BVAL);
+        }
+    }
+
+    usb1_host_enable_bemp_int(pipe);
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/common/usb1_host_intrn.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,285 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_brdy_int
+* Description  : Executes BRDY interrupt(USB_HOST_PIPE1-9).
+*              : According to the pipe that interrupt is generated in,
+*              : reads/writes buffer allocated in the pipe.
+*              : This function is executed in the BRDY interrupt handler.
+*              : This function clears BRDY interrupt status and BEMP interrupt
+*              : status.
+* Arguments    : uint16_t status       ; BRDYSTS Register Value
+*              : uint16_t int_enb      ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_brdy_int (uint16_t status, uint16_t int_enb)
+{
+    uint32_t int_sense = 0;
+    uint16_t pipe;
+    uint16_t pipebit;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        pipebit = g_usb1_host_bit_set[pipe];
+
+        if ((status & pipebit) && (int_enb & pipebit))
+        {
+            USB201.BRDYSTS = (uint16_t)~pipebit;
+            USB201.BEMPSTS = (uint16_t)~pipebit;
+
+            if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+            {
+                if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY)
+                {
+                    usb1_host_dma_interrupt_d0fifo(int_sense);
+                }
+
+                if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+                {
+                    usb1_host_read_dma(pipe);
+                    usb1_host_disable_brdy_int(pipe);
+                }
+                else
+                {
+                    USB201.D0FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+            }
+            else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA)
+            {
+                if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY)
+                {
+                    usb1_host_dma_interrupt_d1fifo(int_sense);
+                }
+
+                if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+                {
+                    usb1_host_read_dma(pipe);
+                    usb1_host_disable_brdy_int(pipe);
+                }
+                else
+                {
+                    USB201.D1FIFOCTR = USB_HOST_BITBCLR;
+                    g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+                }
+            }
+            else
+            {
+                if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+                {
+                    usb1_host_read_buffer(pipe);
+                }
+                else
+                {
+                    usb1_host_write_buffer(pipe);
+                }
+            }
+#if(1) /* ohci_wrapp */
+            switch (g_usb1_host_pipe_status[pipe])
+            {
+                case USB_HOST_PIPE_DONE:
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+                break;
+                case USB_HOST_PIPE_NORES:
+                case USB_HOST_PIPE_STALL:
+                case USB_HOST_PIPE_ERROR:
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+                break;
+                default:
+                    /* Do Nothing */
+                break;
+            }
+#endif
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_nrdy_int
+* Description  : Executes NRDY interrupt(USB_HOST_PIPE1-9).
+*              : Checks NRDY interrupt cause by PID. When the cause if STALL,
+*              : regards the pipe state as STALL and ends the processing.
+*              : Then the cause is not STALL, increments the error count to
+*              : communicate again. When the error count is 3, determines
+*              : the pipe state as USB_HOST_PIPE_NORES and ends the processing.
+*              : This function is executed in the NRDY interrupt handler.
+*              : This function clears NRDY interrupt status.
+* Arguments    : uint16_t status       ; NRDYSTS Register Value
+*              : uint16_t int_enb      ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+    uint16_t pid;
+    uint16_t pipe;
+    uint16_t bitcheck;
+
+    bitcheck = (uint16_t)(status & int_enb);
+
+    USB201.NRDYSTS = (uint16_t)~status;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe])
+        {
+            if (RZA_IO_RegRead_16(&USB201.SYSCFG0,
+                                    USB_SYSCFG_DCFM_SHIFT,
+                                    USB_SYSCFG_DCFM) == 1)
+            {
+                if (g_usb1_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT)
+                {
+                    pid = usb1_host_get_pid(pipe);
+
+                    if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+                    {
+                        g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+                        ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+                    }
+                    else
+                    {
+#if(1) /* ohci_wrapp */
+                        g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+                        ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING);
+#else
+                        g_usb1_host_PipeIgnore[pipe]++;
+
+                        if (g_usb1_host_PipeIgnore[pipe] == 3)
+                        {
+                            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+                        }
+                        else
+                        {
+                            usb1_host_set_pid_buf(pipe);
+                        }
+#endif
+                    }
+                }
+            }
+            else
+            {
+                /* USB Function */
+            }
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_bemp_int
+* Description  : Executes BEMP interrupt(USB_HOST_PIPE1-9).
+* Arguments    : uint16_t status       ; BEMPSTS Register Value
+*              : uint16_t int_enb      ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_bemp_int (uint16_t status, uint16_t int_enb)
+{
+    uint16_t pid;
+    uint16_t pipe;
+    uint16_t bitcheck;
+    uint16_t inbuf;
+
+    bitcheck = (uint16_t)(status & int_enb);
+
+    USB201.BEMPSTS = (uint16_t)~status;
+
+    for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+    {
+        if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe])
+        {
+            pid = usb1_host_get_pid(pipe);
+
+            if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+            {
+                g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+                ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+            }
+            else
+            {
+                inbuf = usb1_host_get_inbuf(pipe);
+
+                if (inbuf == 0)
+                {
+                    usb1_host_disable_bemp_int(pipe);
+                    usb1_host_set_pid_nak(pipe);
+                    g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#if(1) /* ohci_wrapp */
+                    ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+#endif
+                }
+            }
+        }
+    }
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/common/usb1_host_lib.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1598 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#if(1) /* ohci_wrapp */
+#include "VKRZA1H.h"            /* INTC Driver Header   */
+#else
+#include "devdrv_intc.h"        /* INTC Driver Header   */
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_brdy_int
+* Description  : Enables BRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_brdy_int (uint16_t pipe)
+{
+    /* enable brdy interrupt */
+    USB201.BRDYENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_brdy_int
+* Description  : Disables BRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After disabling BRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_brdy_int (uint16_t pipe)
+{
+    /* disable brdy interrupt */
+    USB201.BRDYENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_brdy_sts
+* Description  : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_brdy_sts (uint16_t pipe)
+{
+    /* clear brdy status */
+    USB201.BRDYSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_bemp_int
+* Description  : Enables BEMP interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BEMP, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_bemp_int (uint16_t pipe)
+{
+    /* enable bemp interrupt */
+    USB201.BEMPENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_bemp_int
+* Description  : Disables BEMP interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling BEMP, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe           ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_bemp_int (uint16_t pipe)
+{
+    /* disable bemp interrupt */
+    USB201.BEMPENB  &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_bemp_sts
+* Description  : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_bemp_sts (uint16_t pipe)
+{
+    /* clear bemp status */
+    USB201.BEMPSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_nrdy_int
+* Description  : Enables NRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+*              : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After enabling NRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe             ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_nrdy_int (uint16_t pipe)
+{
+    /* enable nrdy interrupt */
+    USB201.NRDYENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_nrdy_int
+* Description  : Disables NRDY interrupt in the pipe spceified by the argument.
+*              : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+*              : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+*              : in the disabled status. After disabling NRDY, recover all
+*              : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_nrdy_int (uint16_t pipe)
+{
+    /* disable nrdy interrupt */
+    USB201.NRDYENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_nrdy_sts
+* Description  : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments    : uint16_t pipe        ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_nrdy_sts (uint16_t pipe)
+{
+    /* clear nrdy status */
+    USB201.NRDYSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_is_hispeed
+* Description  : Returns the result of USB reset hand shake (RHST) as
+*              : return value.
+* Arguments    : none
+* Return Value : USB_HOST_HIGH_SPEED  ; Hi-Speed
+*              : USB_HOST_FULL_SPEED  ; Full-Speed
+*              : USB_HOST_LOW_SPEED   ; Low-Speed
+*              : USB_HOST_NON_SPEED   ; error
+*******************************************************************************/
+uint16_t usb1_host_is_hispeed (void)
+{
+    uint16_t rhst;
+    uint16_t speed;
+
+    rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+                                USB_DVSTCTR0_RHST_SHIFT,
+                                USB_DVSTCTR0_RHST);
+    if (rhst == USB_HOST_HSMODE)
+    {
+        speed = USB_HOST_HIGH_SPEED;
+    }
+    else if (rhst == USB_HOST_FSMODE)
+    {
+        speed = USB_HOST_FULL_SPEED;
+    }
+    else if (rhst == USB_HOST_LSMODE)
+    {
+        speed = USB_HOST_LOW_SPEED;
+    }
+    else
+    {
+        speed = USB_HOST_NON_SPEED;
+    }
+
+    return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_is_hispeed_enable
+* Description  : Returns the USB High-Speed connection enabled status as
+*              : return value.
+* Arguments    : none
+* Return Value : USB_HOST_YES : Hi-Speed Enable
+*              : USB_HOST_NO  : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb1_host_is_hispeed_enable (void)
+{
+    uint16_t ret;
+
+    ret = USB_HOST_NO;
+
+    if (RZA_IO_RegRead_16(&USB201.SYSCFG0,
+                                USB_SYSCFG_HSE_SHIFT,
+                                USB_SYSCFG_HSE) == 1)
+    {
+        ret = USB_HOST_YES;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_buf
+* Description  : Enables communicaqtion in the pipe specified by the argument
+*              : (BUF).
+* Arguments    : uint16_t pipe             ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_buf (uint16_t pipe)
+{
+    uint16_t pid;
+
+    pid = usb1_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_STALL2)
+    {
+        usb1_host_set_pid_nak(pipe);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                USB_HOST_PID_BUF,
+                                USB_DCPCTR_PID_SHIFT,
+                                USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                USB_HOST_PID_BUF,
+                                USB_PIPEnCTR_9_PID_SHIFT,
+                                USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_nak
+* Description  : Disables communication (NAK) in the pipe specified by the argument.
+*              : When the pipe status was enabling communication (BUF) before
+*              : executing before executing this function, waits in the software
+*              : until the pipe becomes ready after setting disabled.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_nak (uint16_t pipe)
+{
+    uint16_t pid;
+    uint16_t pbusy;
+    uint32_t loop;
+
+    pid = usb1_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_STALL2)
+    {
+        usb1_host_set_pid_stall(pipe);
+    }
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                USB_HOST_PID_NAK,
+                                USB_DCPCTR_PID_SHIFT,
+                                USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_1_5_PID_SHIFT,
+                                USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_6_8_PID_SHIFT,
+                                USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                USB_HOST_PID_NAK,
+                                USB_PIPEnCTR_9_PID_SHIFT,
+                                USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+        break;
+    }
+
+    if (pid == USB_HOST_PID_BUF)
+    {
+        for (loop = 0; loop < 200; loop++)
+        {
+            switch (pipe)
+            {
+                case USB_HOST_PIPE0:
+                    pbusy = RZA_IO_RegRead_16(&USB201.DCPCTR,
+                                                USB_DCPCTR_PBUSY_SHIFT,
+                                                USB_DCPCTR_PBUSY);
+                break;
+
+                case USB_HOST_PIPE1:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE2:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE3:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE4:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE5:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+                                                USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_1_5_PBUSY);
+                break;
+
+                case USB_HOST_PIPE6:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE7:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE8:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+                                                USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_6_8_PBUSY);
+                break;
+
+                case USB_HOST_PIPE9:
+                    pbusy = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+                                                USB_PIPEnCTR_9_PBUSY_SHIFT,
+                                                USB_PIPEnCTR_9_PBUSY);
+                break;
+
+                default:
+                    pbusy = 1;
+                break;
+            }
+
+            if (pbusy == 0)
+            {
+                break;
+            }
+
+            Userdef_USB_usb1_host_delay_500ns();
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_stall
+* Description  : Disables communication (STALL) in the pipe specified by the
+*              : argument.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_stall (uint16_t pipe)
+{
+    uint16_t pid;
+
+    pid = usb1_host_get_pid(pipe);
+
+    if (pid == USB_HOST_PID_BUF)
+    {
+        switch (pipe)
+        {
+            case USB_HOST_PIPE0:
+                RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+            break;
+
+            case USB_HOST_PIPE1:
+                RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE2:
+                RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE3:
+                RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE4:
+                RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE5:
+                RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE6:
+                RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE7:
+                RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE8:
+                RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE9:
+                RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                    USB_HOST_PID_STALL2,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+            break;
+
+            default:
+            break;
+        }
+    }
+    else
+    {
+        switch (pipe)
+        {
+            case USB_HOST_PIPE0:
+                RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+            break;
+
+            case USB_HOST_PIPE1:
+                RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE2:
+                RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE3:
+                RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE4:
+                RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE5:
+                RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+            break;
+
+            case USB_HOST_PIPE6:
+                RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE7:
+                RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE8:
+                RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+            break;
+
+            case USB_HOST_PIPE9:
+                RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                    USB_HOST_PID_STALL,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+            break;
+
+            default:
+            break;
+        }
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_pid_stall
+* Description  : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments    : uint16_t pipe            ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_pid_stall (uint16_t pipe)
+{
+    usb1_host_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_pid
+* Description  : Returns the pipe state specified by the argument.
+* Arguments    : uint16_t pipe          ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb1_host_get_pid (uint16_t pipe)
+{
+    uint16_t pid;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            pid = RZA_IO_RegRead_16(&USB201.DCPCTR,
+                                    USB_DCPCTR_PID_SHIFT,
+                                    USB_DCPCTR_PID);
+        break;
+
+        case USB_HOST_PIPE1:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE2:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE3:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE4:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE5:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+                                    USB_PIPEnCTR_1_5_PID_SHIFT,
+                                    USB_PIPEnCTR_1_5_PID);
+        break;
+
+        case USB_HOST_PIPE6:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE7:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE8:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+                                    USB_PIPEnCTR_6_8_PID_SHIFT,
+                                    USB_PIPEnCTR_6_8_PID);
+        break;
+
+        case USB_HOST_PIPE9:
+            pid = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+                                    USB_PIPEnCTR_9_PID_SHIFT,
+                                    USB_PIPEnCTR_9_PID);
+        break;
+
+        default:
+            pid = 0;
+        break;
+    }
+
+    return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_csclr
+* Description  : CSPLIT status clear setting of sprit transaction in specified
+*              : pipe is performed.
+*              : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+*              : in DCPCTR register are continuously changed (when the sequence
+*              : toggle bit of data PID is continuously changed over two or more pipes),
+*              : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+*              : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+*              : In addition, both bits should be operated after PID is set to NAK.
+*              : However, when it is set to the isochronous transfer as the transfer type
+*              : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments    : uint16_t pipe     ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_csclr (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                1,
+                                USB_DCPCTR_CSCLR_SHIFT,
+                                USB_DCPCTR_CSCLR);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_CSCLR);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_CSCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_CSCLR_SHIFT,
+                                USB_PIPEnCTR_9_CSCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_sqclr
+* Description  : Sets the sequence bit of the pipe specified by the argument to
+*              : DATA0.
+* Arguments    : uint16_t pipe              ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_sqclr (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                1,
+                                USB_DCPCTR_SQCLR_SHIFT,
+                                USB_DCPCTR_SQCLR);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+                                USB_PIPEnCTR_1_5_SQCLR);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+                                USB_PIPEnCTR_6_8_SQCLR);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_SQCLR_SHIFT,
+                                USB_PIPEnCTR_9_SQCLR);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_sqset
+* Description  : Sets the sequence bit of the pipe specified by the argument to
+*              : DATA1.
+* Arguments    : uint16_t pipe   ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_sqset (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            RZA_IO_RegWrite_16(&USB201.DCPCTR,
+                                1,
+                                USB_DCPCTR_SQSET_SHIFT,
+                                USB_DCPCTR_SQSET);
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_SQSET_SHIFT,
+                                USB_PIPEnCTR_1_5_SQSET);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_SQSET_SHIFT,
+                                USB_PIPEnCTR_6_8_SQSET);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_SQSET_SHIFT,
+                                USB_PIPEnCTR_9_SQSET);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_sqmon
+* Description  : Toggle bit of specified pipe is obtained
+* Arguments    : uint16_t pipe   ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb1_host_get_sqmon (uint16_t pipe)
+{
+    uint16_t sqmon;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            sqmon = RZA_IO_RegRead_16(&USB201.DCPCTR,
+                                        USB_DCPCTR_SQMON_SHIFT,
+                                        USB_DCPCTR_SQMON);
+        break;
+
+        case USB_HOST_PIPE1:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE2:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE3:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE4:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE5:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+                                        USB_PIPEnCTR_1_5_SQMON_SHIFT,
+                                        USB_PIPEnCTR_1_5_SQMON);
+        break;
+
+        case USB_HOST_PIPE6:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE7:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE8:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+                                        USB_PIPEnCTR_6_8_SQMON_SHIFT,
+                                        USB_PIPEnCTR_6_8_SQMON);
+        break;
+
+        case USB_HOST_PIPE9:
+            sqmon = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+                                        USB_PIPEnCTR_9_SQMON_SHIFT,
+                                        USB_PIPEnCTR_9_SQMON);
+        break;
+
+        default:
+            sqmon = 0;
+        break;
+    }
+
+    return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_aclrm
+* Description  : The buffer of specified pipe is initialized
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_aclrm (uint16_t pipe)
+{
+    usb1_host_set_aclrm(pipe);
+    usb1_host_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_aclrm
+* Description  : The auto buffer clear mode of specified pipe is enabled
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_aclrm (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                1,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                1,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                1,
+                                USB_PIPEnCTR_9_ACLRM_SHIFT,
+                                USB_PIPEnCTR_9_ACLRM);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clr_aclrm
+* Description  : The auto buffer clear mode of specified pipe is enabled
+* Arguments    : uint16_t pipe    : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clr_aclrm (uint16_t pipe)
+{
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+        break;
+
+        case USB_HOST_PIPE1:
+            RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE2:
+            RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE3:
+            RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE4:
+            RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE5:
+            RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+                                0,
+                                USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+                                USB_PIPEnCTR_1_5_ACLRM);
+        break;
+
+        case USB_HOST_PIPE6:
+            RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE7:
+            RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE8:
+            RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+                                0,
+                                USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+                                USB_PIPEnCTR_6_8_ACLRM);
+        break;
+
+        case USB_HOST_PIPE9:
+            RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+                                0,
+                                USB_PIPEnCTR_9_ACLRM_SHIFT,
+                                USB_PIPEnCTR_9_ACLRM);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_inbuf
+* Description  : Returns INBUFM of the pipe specified by the argument.
+* Arguments    : uint16_t pipe             ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb1_host_get_inbuf (uint16_t pipe)
+{
+    uint16_t inbuf;
+
+    switch (pipe)
+    {
+        case USB_HOST_PIPE0:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE1:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE2:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE3:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE4:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE5:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+                                    USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_1_5_INBUFM);
+        break;
+
+        case USB_HOST_PIPE6:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE7:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE8:
+            inbuf = 0;
+        break;
+
+        case USB_HOST_PIPE9:
+            inbuf = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+                                    USB_PIPEnCTR_9_INBUFM_SHIFT,
+                                    USB_PIPEnCTR_9_INBUFM);
+        break;
+
+        default:
+            inbuf = 0;
+        break;
+    }
+
+    return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_setting_interrupt
+* Description  : Sets the USB module interrupt level.
+* Arguments    : uint8_t level ; interrupt level
+* Return Value : none
+*******************************************************************************/
+void usb1_host_setting_interrupt (uint8_t level)
+{
+#if(1) /* ohci_wrapp */
+    IRQn_Type d0fifo_dmaintid;
+    IRQn_Type d1fifo_dmaintid;
+
+    InterruptHandlerRegister(USBI1_IRQn, usb1_host_interrupt);
+    GIC_SetPriority(USBI1_IRQn, level);
+    GIC_EnableIRQ(USBI1_IRQn);
+
+    d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb1_host_d0fifo_dmaintid();
+
+    if (d0fifo_dmaintid != 0xFFFF)
+    {
+        InterruptHandlerRegister(d0fifo_dmaintid, usb1_host_dma_interrupt_d0fifo);
+        GIC_SetPriority(d0fifo_dmaintid, level);
+        GIC_EnableIRQ(d0fifo_dmaintid);
+    }
+
+    d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb1_host_d1fifo_dmaintid();
+
+    if (d1fifo_dmaintid != 0xFFFF)
+    {
+        InterruptHandlerRegister(d1fifo_dmaintid, usb1_host_dma_interrupt_d1fifo);
+        GIC_SetPriority(d1fifo_dmaintid, level);
+        GIC_EnableIRQ(d1fifo_dmaintid);
+    }
+#else
+    uint16_t d0fifo_dmaintid;
+    uint16_t d1fifo_dmaintid;
+
+    R_INTC_RegistIntFunc(INTC_ID_USBI1, usb1_host_interrupt);
+    R_INTC_SetPriority(INTC_ID_USBI1, level);
+    R_INTC_Enable(INTC_ID_USBI1);
+
+    d0fifo_dmaintid = Userdef_USB_usb1_host_d0fifo_dmaintid();
+
+    if (d0fifo_dmaintid != 0xFFFF)
+    {
+        R_INTC_RegistIntFunc(d0fifo_dmaintid, usb1_host_dma_interrupt_d0fifo);
+        R_INTC_SetPriority(d0fifo_dmaintid, level);
+        R_INTC_Enable(d0fifo_dmaintid);
+    }
+
+    d1fifo_dmaintid = Userdef_USB_usb1_host_d1fifo_dmaintid();
+
+    if (d1fifo_dmaintid != 0xFFFF)
+    {
+        R_INTC_RegistIntFunc(d1fifo_dmaintid, usb1_host_dma_interrupt_d1fifo);
+        R_INTC_SetPriority(d1fifo_dmaintid, level);
+        R_INTC_Enable(d1fifo_dmaintid);
+    }
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_reset_module
+* Description  : Initializes the USB module.
+*              : Enables providing clock to the USB module.
+*              : Sets USB bus wait register.
+* Arguments    : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ
+*              :                    ; 12MHz ; USBHCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb1_host_reset_module (uint16_t clockmode)
+{
+    if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+                                USB_SYSCFG_UPLLE_SHIFT,
+                                USB_SYSCFG_UPLLE) == 1)
+    {
+        if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode)
+        {
+            RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                                0,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                0,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            USB201.SYSCFG0 = 0;
+            USB200.SYSCFG0 = 0;
+            USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+            Userdef_USB_usb1_host_delay_xms(1);
+            RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                                1,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                                1,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+        }
+        else
+        {
+            RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                                0,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+            Userdef_USB_usb1_host_delay_xms(1);
+            RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                                1,
+                                USB_SUSPMODE_SUSPM_SHIFT,
+                                USB_SUSPMODE_SUSPM);
+        }
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                            0,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+        RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                            0,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+        USB201.SYSCFG0 = 0;
+        USB200.SYSCFG0 = 0;
+        USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+        Userdef_USB_usb1_host_delay_xms(1);
+        RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+                            1,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+        RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+                            1,
+                            USB_SUSPMODE_SUSPM_SHIFT,
+                            USB_SUSPMODE_SUSPM);
+    }
+
+    USB201.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_buf_size
+* Description  : Obtains pipe buffer size specified by the argument and
+*              : maximum packet size of the USB device in use.
+*              : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum
+*              : packet size of the USB device using the corresponding pipe.
+*              : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the
+*              : corresponding pipe is in continuous transfer mode,
+*              : obtains the buffer size allocated in the corresponcing pipe,
+*              : when incontinuous transfer, obtains maximum packet size.
+* Arguments    : uint16_t ; pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb1_host_get_buf_size (uint16_t pipe)
+{
+    uint16_t size;
+    uint16_t bufsize;
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+                                USB_DCPMAXP_MXPS_SHIFT,
+                                USB_DCPMAXP_MXPS);
+    }
+    else
+    {
+        if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+        {
+            bufsize = RZA_IO_RegRead_16(&g_usb1_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+            size    = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF);
+        }
+        else
+        {
+            size = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+        }
+    }
+    return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_mxps
+* Description  : Obtains maximum packet size of the USB device using the pipe
+*              : specified by the argument.
+* Arguments    : uint16_t ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb1_host_get_mxps (uint16_t pipe)
+{
+    uint16_t size;
+
+    if (pipe == USB_HOST_PIPE0)
+    {
+        size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+                                USB_DCPMAXP_MXPS_SHIFT,
+                                USB_DCPMAXP_MXPS);
+    }
+    else
+    {
+        size = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+    }
+
+    return size;
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/host/usb1_host_controlrw.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,434 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlTransStart
+* Description  : Executes USB control transfer.
+* Arguments    : uint16_t devadr ; device address
+*              : uint16_t Req   ; bmRequestType & bRequest
+*              : uint16_t Val   ; wValue
+*              : uint16_t Indx  ; wIndex
+*              : uint16_t Len   ; wLength
+*              : uint8_t  *Buf  ; Data buffer
+* Return Value : DEVDRV_SUCCESS     ;   SUCCESS
+*              : DEVDRV_ERROR       ;   ERROR
+*******************************************************************************/
+int32_t usb1_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val,
+                            uint16_t Indx, uint16_t Len, uint8_t * Buf)
+{
+    if (g_usb1_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED)
+    {
+        RZA_IO_RegWrite_16(&USB201.SOFCFG,
+                            1,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+    else
+    {
+        RZA_IO_RegWrite_16(&USB201.SOFCFG,
+                            0,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+
+    USB201.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb1_host_default_max_packet[devadr]);
+
+    if (g_usb1_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE)
+    {
+        g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+        g_usb1_host_PipeIgnore[USB_HOST_PIPE0]  = 0;                    /* Ignore count clear */
+        g_usb1_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+
+        if (Len == 0)
+        {
+            g_usb1_host_CmdStage |= USB_HOST_MODE_NO_DATA;              /* No-data Control */
+        }
+        else
+        {
+            if ((Req & 0x0080) != 0)
+            {
+                g_usb1_host_CmdStage |= USB_HOST_MODE_READ;             /* Control Read */
+            }
+            else
+            {
+                g_usb1_host_CmdStage |= USB_HOST_MODE_WRITE;            /* Control Write */
+            }
+        }
+
+        g_usb1_host_SavReq  = Req;                                      /* save request */
+        g_usb1_host_SavVal  = Val;
+        g_usb1_host_SavIndx = Indx;
+        g_usb1_host_SavLen  = Len;
+    }
+    else
+    {
+        if ((g_usb1_host_SavReq  != Req)  || (g_usb1_host_SavVal != Val)
+         || (g_usb1_host_SavIndx != Indx) || (g_usb1_host_SavLen != Len))
+        {
+            return DEVDRV_ERROR;
+        }
+    }
+
+    switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+    {
+        /* --------------- SETUP STAGE --------------- */
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE):
+            usb1_host_SetupStage(Req, Val, Indx, Len);
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE):                /* goto next stage */
+            g_usb1_host_PipeIgnore[USB_HOST_PIPE0]  = 0;                /* Ignore count clear */
+            switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+            {
+                case USB_HOST_MODE_WRITE:
+                    g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA;
+                break;
+
+                case USB_HOST_MODE_READ:
+                    g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA;
+                break;
+
+                case USB_HOST_MODE_NO_DATA:
+                    g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                break;
+
+                default:
+                break;
+            }
+            g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+        break;
+
+        case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES):
+            if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+            }
+        break;
+
+        /* --------------- DATA STAGE --------------- */
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE):
+            switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+            {
+                case USB_HOST_MODE_WRITE:
+                    usb1_host_CtrlWriteStart((uint32_t)Len, Buf);
+                break;
+
+                case USB_HOST_MODE_READ:
+                    usb1_host_CtrlReadStart((uint32_t)Len, Buf);
+                break;
+
+                default:
+                break;
+            }
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE):                         /* goto next stage */
+            g_usb1_host_PipeIgnore[USB_HOST_PIPE0]  = 0;                        /* Ignore count clear */
+            g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+            g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES):
+            if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+                usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+                usb1_host_set_pid_buf(USB_HOST_PIPE0);
+            }
+        break;
+
+        case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL):
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+        break;
+
+        /* --------------- STATUS STAGE --------------- */
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE):
+            usb1_host_StatusStage();
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+            /* do nothing */
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE):                       /* end of Control transfer */
+            usb1_host_set_pid_nak(USB_HOST_PIPE0);
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE;       /* exit DONE */
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES):
+            if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+            {
+                g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+            }
+            else
+            {
+                g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++;                       /* Ignore count */
+                g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+                usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+                usb1_host_set_pid_buf(USB_HOST_PIPE0);
+            }
+        break;
+
+        case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL):
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+        break;
+
+        default:
+        break;
+    }
+
+    if (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)
+    {
+        RZA_IO_RegWrite_16(&USB201.SOFCFG,
+                            0,
+                            USB_SOFCFG_TRNENSEL_SHIFT,
+                            USB_SOFCFG_TRNENSEL);
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_SetupStage
+* Description  : Executes USB control transfer/set up stage.
+* Arguments    : uint16_t Req           ; bmRequestType & bRequest
+*              : uint16_t Val           ; wValue
+*              : uint16_t Indx          ; wIndex
+*              : uint16_t Len           ; wLength
+* Return Value : none
+*******************************************************************************/
+void usb1_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len)
+{
+    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    USB201.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN);  /* Status Clear */
+    USB201.USBREQ  = Req;
+    USB201.USBVAL  = Val;
+    USB201.USBINDX = Indx;
+    USB201.USBLENG = Len;
+    USB201.DCPCTR  = USB_HOST_BITSUREQ;                                 /* PID=NAK & Send Setup */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_StatusStage
+* Description  : Executes USB control transfer/status stage.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_StatusStage (void)
+{
+    uint8_t Buf1[16];
+
+    switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+    {
+        case USB_HOST_MODE_READ:
+            usb1_host_CtrlWriteStart((uint32_t)0, (uint8_t*)&Buf1);
+        break;
+
+        case USB_HOST_MODE_WRITE:
+            usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1);
+        break;
+
+        case USB_HOST_MODE_NO_DATA:
+            usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1);
+        break;
+
+        default:
+        break;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlWriteStart
+* Description  : Executes USB control transfer/data stage(write).
+* Arguments    : uint32_t Bsize     ; Data Size
+*              : uint8_t  *Table    ; Data Table Address
+* Return Value : USB_HOST_WRITESHRT ; End of data write
+*              : USB_HOST_WRITEEND  ; End of data write (not null)
+*              : USB_HOST_WRITING   ; Continue of data write
+*              : USB_HOST_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb1_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table)
+{
+    uint16_t EndFlag_K;
+    uint16_t mbw;
+
+    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    usb1_host_set_pid_nak(USB_HOST_PIPE0);                              /* Set NAK */
+    g_usb1_host_data_count[USB_HOST_PIPE0]   = Bsize;                   /* Transfer size set */
+    g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table;                   /* Transfer address set */
+
+    USB201.DCPCTR = USB_HOST_BITSQSET;                                  /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+    Userdef_USB_usb1_host_delay_10us(3);
+#endif
+    RZA_IO_RegWrite_16(&USB201.DCPCFG,
+                        1,
+                        USB_DCPCFG_DIR_SHIFT,
+                        USB_DCPCFG_DIR);
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw);
+    USB201.CFIFOCTR = USB_HOST_BITBCLR;                                 /* Buffer Clear */
+
+    usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+    EndFlag_K = usb1_host_write_buffer_c(USB_HOST_PIPE0);
+    /* Host Control sequence */
+    switch (EndFlag_K)
+    {
+        case USB_HOST_WRITESHRT:                                        /* End of data write */
+            g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+            usb1_host_enable_nrdy_int(USB_HOST_PIPE0);                  /* Error (NORES or STALL) */
+            usb1_host_enable_bemp_int(USB_HOST_PIPE0);                  /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_WRITEEND:                                         /* End of data write (not null) */
+        case USB_HOST_WRITING:                                          /* Continue of data write */
+            usb1_host_enable_nrdy_int(USB_HOST_PIPE0);                  /* Error (NORES or STALL) */
+            usb1_host_enable_bemp_int(USB_HOST_PIPE0);                  /* Enable Empty Interrupt */
+        break;
+
+        case USB_HOST_FIFOERROR:                                        /* FIFO access error */
+        break;
+
+        default:
+        break;
+    }
+    usb1_host_set_pid_buf(USB_HOST_PIPE0);                              /* Set BUF */
+    return (EndFlag_K);                                                 /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlReadStart
+* Description  : Executes USB control transfer/data stage(read).
+* Arguments    : uint32_t Bsize     ; Data Size
+*              : uint8_t  *Table    ; Data Table Address
+* Return Value : none
+*******************************************************************************/
+void usb1_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table)
+{
+    uint16_t mbw;
+
+    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+    g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+    usb1_host_set_pid_nak(USB_HOST_PIPE0);                  /* Set NAK */
+    g_usb1_host_data_count[USB_HOST_PIPE0]   = Bsize;       /* Transfer size set */
+    g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table;       /* Transfer address set */
+
+    USB201.DCPCTR     = USB_HOST_BITSQSET;                  /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+    Userdef_USB_usb1_host_delay_10us(3);
+#endif
+    RZA_IO_RegWrite_16(&USB201.DCPCFG,
+                        0,
+                        USB_DCPCFG_DIR_SHIFT,
+                        USB_DCPCFG_DIR);
+
+    mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]);
+    usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw);
+    USB201.CFIFOCTR = USB_HOST_BITBCLR;                     /* Buffer Clear */
+
+    usb1_host_enable_nrdy_int(USB_HOST_PIPE0);              /* Error (NORES or STALL) */
+    usb1_host_enable_brdy_int(USB_HOST_PIPE0);              /* Ok */
+    usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+    usb1_host_set_pid_buf(USB_HOST_PIPE0);                  /* Set BUF */
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/host/usb1_host_drv_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,889 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_drv_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_api_host_init
+* Description  : Initializes USB module in the USB host mode.
+*              : USB connection is executed when executing this function in
+*              : the states that USB device isconnected to the USB port.
+* Arguments    : uint8_t int_level  : USB Module interrupt level
+*              : USBU16  mode       : USB_HOST_HIGH_SPEED
+*                                   : USB_HOST_FULL_SPEED
+*              : uint16_t clockmode : USB Clock mode
+* Return Value : USB detach or attach
+*              :  USB_HOST_ATTACH
+*              :  USB_HOST_DETACH
+*******************************************************************************/
+uint16_t usb1_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+    uint16_t         connect;
+    volatile uint8_t dummy_buf;
+
+    CPG.STBCR7 &= 0xfc;                         /*The clock of USB0/1 modules is permitted */
+    dummy_buf   = CPG.STBCR7;                   /* (Dummy read) */
+
+    g_usb1_host_SupportUsbDeviceSpeed = mode;
+
+    usb1_host_setting_interrupt(int_level);
+    usb1_host_reset_module(clockmode);
+
+    g_usb1_host_bchg_flag   = USB_HOST_NO;
+    g_usb1_host_detach_flag = USB_HOST_NO;
+    g_usb1_host_attach_flag = USB_HOST_NO;
+
+    g_usb1_host_driver_state = USB_HOST_DRV_DETACHED;
+    g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+    usb1_host_InitModule();
+
+    connect = usb1_host_CheckAttach();
+
+    if (connect == USB_HOST_ATTACH)
+    {
+        g_usb1_host_attach_flag = USB_HOST_YES;
+    }
+    else
+    {
+        usb1_host_UsbDetach2();
+    }
+
+    return connect;
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb1_api_host_enumeration
+* Description  : Initializes USB module in the USB host mode.
+*              : USB connection is executed when executing this function in
+*              : the states that USB device isconnected to the USB port.
+* Arguments    : uint16_t devadr : device address
+* Return Value : DEVDRV_USBH_DETACH_ERR       : device detach
+*              : DEVDRV_SUCCESS               : device enumeration success
+*              : DEVDRV_ERROR                 : device enumeration error
+*******************************************************************************/
+int32_t usb1_api_host_enumeration (uint16_t devadr)
+{
+    int32_t  ret;
+    uint16_t driver_sts;
+
+    g_usb1_host_setUsbAddress = devadr;
+
+    while (1)
+    {
+        driver_sts = usb1_api_host_GetUsbDeviceState();
+
+        if (driver_sts == USB_HOST_DRV_DETACHED)
+        {
+            ret = DEVDRV_USBH_DETACH_ERR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+        {
+            ret = DEVDRV_SUCCESS;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_STALL)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_NORES)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+
+    if (driver_sts == USB_HOST_DRV_NORES)
+    {
+        while (1)
+        {
+            driver_sts = usb1_api_host_GetUsbDeviceState();
+
+            if (driver_sts == USB_HOST_DRV_DETACHED)
+            {
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_detach
+* Description  : USB detach routine
+* Arguments    : none
+* Return Value : USB_HOST_DETACH : USB detach
+*              : USB_HOST_ATTACH : USB attach
+*              : DEVDRV_ERROR    : error
+*******************************************************************************/
+int32_t usb1_api_host_detach (void)
+{
+    int32_t  ret;
+    uint16_t driver_sts;
+
+    while (1)
+    {
+        driver_sts = usb1_api_host_GetUsbDeviceState();
+
+        if (driver_sts == USB_HOST_DRV_DETACHED)
+        {
+            ret = USB_HOST_DETACH;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+        {
+            ret = USB_HOST_ATTACH;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_STALL)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else if (driver_sts == USB_HOST_DRV_NORES)
+        {
+            ret = DEVDRV_ERROR;
+            break;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+
+    if (driver_sts == USB_HOST_DRV_NORES)
+    {
+        while (1)
+        {
+            driver_sts = usb1_api_host_GetUsbDeviceState();
+
+            if (driver_sts == USB_HOST_DRV_DETACHED)
+            {
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_data_in
+* Description  : Executes USB transfer as data-in in the argument specified pipe.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Pipe         ; Pipe Number
+*              : uint32_t Size         ; Data Size
+*              : uint8_t  *data_buf    ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+    int32_t ret;
+
+    if (Pipe == USB_HOST_PIPE0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+    {
+        usb1_host_start_receive_transfer(Pipe, Size, data_buf);
+    }
+    else
+    {
+        return DEVDRV_ERROR;                /* Now pipe is busy */
+    }
+
+    /* waiting for completing routine           */
+    do
+    {
+        if (g_usb1_host_detach_flag == USB_HOST_YES)
+        {
+            break;
+        }
+
+        if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+        {
+            break;
+        }
+
+    } while (1);
+
+    if (g_usb1_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb1_host_pipe_status[Pipe])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    usb1_host_stop_transfer(Pipe);
+
+    g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_data_out
+* Description  : Executes USB transfer as data-out in the argument specified pipe.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Pipe         ; Pipe Number
+*              : uint32_t Size         ; Data Size
+*              : uint8_t  *data_buf    ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+    int32_t ret;
+
+    if (Pipe == USB_HOST_PIPE0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+    {
+        usb1_host_start_send_transfer(Pipe, Size, data_buf);
+    }
+    else
+    {
+        return DEVDRV_ERROR;              /* Now pipe is busy */
+    }
+
+    /* waiting for completing routine           */
+    do
+    {
+        if (g_usb1_host_detach_flag == USB_HOST_YES)
+        {
+            break;
+        }
+
+        if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+        {
+            break;
+        }
+
+    } while (1);
+
+    if (g_usb1_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb1_host_pipe_status[Pipe])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    usb1_host_stop_transfer(Pipe);
+
+    g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_control_transfer
+* Description  : Executes USB control transfer.
+* Arguments    : uint16_t devadr       ; device address
+*              : uint16_t Req          ; bmRequestType & bRequest
+*              : uint16_t Val          ; wValue
+*              : uint16_t Indx         ; wIndex
+*              : uint16_t Len          ; wLength
+*              : uint8_t  *buf         ; Buffer
+* Return Value : DEVDRV_SUCCESS           ; success
+*              : DEVDRV_USBH_DETACH_ERR   ; device detach
+*              : DEVDRV_USBH_CTRL_COM_ERR ; device no response
+*              : DEVDRV_USBH_STALL        ; STALL
+*              : DEVDRV_ERROR             ; error
+*******************************************************************************/
+int32_t usb1_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx,
+                                                     uint16_t Len, uint8_t * Buf)
+{
+    int32_t  ret;
+
+    do
+    {
+        ret = usb1_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf);
+
+        if (ret == DEVDRV_SUCCESS)
+        {
+            if (g_usb1_host_detach_flag == USB_HOST_YES)
+            {
+                break;
+            }
+
+            if ((g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE)
+                && (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT))
+            {
+                break;
+            }
+        }
+        else
+        {
+            return DEVDRV_ERROR;
+        }
+    } while (1);
+
+    if (g_usb1_host_detach_flag == USB_HOST_YES)
+    {
+        return DEVDRV_USBH_DETACH_ERR;
+    }
+
+    switch (g_usb1_host_pipe_status[USB_HOST_PIPE0])
+    {
+        case USB_HOST_PIPE_DONE:
+            ret = DEVDRV_SUCCESS;
+        break;
+
+        case USB_HOST_PIPE_STALL:
+            ret = DEVDRV_USBH_STALL;
+        break;
+
+        case USB_HOST_PIPE_NORES:
+            ret = DEVDRV_USBH_CTRL_COM_ERR;
+        break;
+
+        default:
+            ret = DEVDRV_ERROR;
+        break;
+    }
+
+    g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_set_endpoint
+* Description  : Sets end point on the information specified in the argument.
+* Arguments    : uint16_t                devadr           ; device address
+*              : uint8_t                *configdescriptor ; device configration descriptor
+*              : USB_HOST_CFG_PIPETBL_t *user_table       ; pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb1_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor)
+{
+    uint16_t                ret;
+    uint32_t                end_point;
+    uint32_t                offset;
+    uint32_t                totalLength;
+    USB_HOST_CFG_PIPETBL_t * pipe_table;
+
+    /*  End Point Search */
+    end_point   = 0;
+    offset      = configdescriptor[0];
+    totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8));
+
+    do
+    {
+        if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC)
+        {
+            pipe_table = &user_table[end_point];
+
+            if (pipe_table->pipe_number == 0xffff)
+            {
+                break;
+            }
+
+            ret = usb1_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]);
+
+            if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT))
+            {
+                return DEVDRV_ERROR;
+            }
+
+            ++end_point;
+        }
+
+        /* Next End Point Search */
+        offset += configdescriptor[offset];
+
+    } while (offset < totalLength);
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_clear_endpoint
+* Description  : Clears the pipe definition table specified in the argument.
+* Arguments    : uint16_t pipe_sel                  : Pipe Number
+*              : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb1_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table)
+{
+    uint16_t pipe;
+
+    for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+    {
+        if (user_table->pipe_number == 0xffff)
+        {
+            break;
+        }
+        user_table->pipe_cfg         &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+        user_table->pipe_max_pktsize  = 0;
+        user_table->pipe_cycle        = 0;
+
+        user_table++;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_clear_endpoint_pipe
+* Description  : Clears the pipe definition table specified in the argument.
+* Arguments    : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS       ; success
+*              : DEVDRV_ERROR         ; error
+*******************************************************************************/
+int32_t usb1_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table)
+{
+    uint16_t pipe;
+
+    for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+    {
+        if (user_table->pipe_number == 0xffff)
+        {
+            break;
+        }
+
+        if (user_table->pipe_number == pipe_sel)
+        {
+            user_table->pipe_cfg         &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+            user_table->pipe_max_pktsize  = 0;
+            user_table->pipe_cycle        = 0;
+            break;
+        }
+
+        user_table++;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_api_host_SetEndpointTable
+* Description  : Sets the end point on the information specified by the argument.
+* Arguments    : uint16_t devadr                    : device address
+*              : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+*              : uint8_t                *Table      : Endpoint descriptor
+* Return Value : USB_HOST_DIR_H_IN           ; IN endpoint
+*              : USB_HOST_DIR_H_OUT          ; OUT endpoint
+*              : USB_END_POINT_ERROR         ; error
+*******************************************************************************/
+uint16_t usb1_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table)
+{
+    uint16_t PipeCfg;
+    uint16_t PipeMaxp;
+    uint16_t pipe_number;
+    uint16_t ret;
+    uint16_t ret_flag = 0;                                  // avoid warning.
+
+    pipe_number = user_table->pipe_number;
+
+    if (Table[1] != USB_HOST_ENDPOINT_DESC)
+    {
+        return USB_END_POINT_ERROR;
+    }
+
+    switch (Table[3] & USB_HOST_EP_TYPE)
+    {
+        case USB_HOST_EP_CNTRL:
+            ret_flag = USB_END_POINT_ERROR;
+        break;
+
+        case USB_HOST_EP_ISO:
+            if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_ISO;
+        break;
+
+        case USB_HOST_EP_BULK:
+            if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_BULK;
+        break;
+
+        case USB_HOST_EP_INT:
+            if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9))
+            {
+                return USB_END_POINT_ERROR;
+            }
+
+            PipeCfg = USB_HOST_INTERRUPT;
+        break;
+
+        default:
+            ret_flag = USB_END_POINT_ERROR;
+        break;
+    }
+
+    if (ret_flag == USB_END_POINT_ERROR)
+    {
+        return ret_flag;
+    }
+
+    /* Set pipe configuration table */
+    if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN)        /* IN(receive) */
+    {
+        if (PipeCfg == USB_HOST_ISO)
+        {
+            /* Transfer Type is ISO*/
+            PipeCfg |= USB_HOST_DIR_H_IN;
+
+            switch (user_table->fifo_port)
+            {
+                case USB_HOST_CUSE:
+                case USB_HOST_D0USE:
+                case USB_HOST_D1USE:
+                case USB_HOST_D0DMA:
+                case USB_HOST_D1DMA:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+                break;
+
+                default:
+                    ret_flag = USB_END_POINT_ERROR;
+                break;
+            }
+
+            if (ret_flag == USB_END_POINT_ERROR)
+            {
+                return ret_flag;
+            }
+        }
+        else
+        {
+            /* Transfer Type is BULK or INT */
+            PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN);             /* Compulsory SHTNAK */
+
+            switch (user_table->fifo_port)
+            {
+                case USB_HOST_CUSE:
+                case USB_HOST_D0USE:
+                case USB_HOST_D1USE:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+                break;
+
+                case USB_HOST_D0DMA:
+                case USB_HOST_D1DMA:
+                    PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+#ifdef  __USB_DMA_BFRE_ENABLE__
+                    /* this routine cannnot be perfomred if read operation is executed in buffer size */
+                    PipeCfg |= USB_HOST_BFREON;
+#endif
+                break;
+
+                default:
+                    ret_flag = USB_END_POINT_ERROR;
+                break;
+            }
+
+            if (ret_flag == USB_END_POINT_ERROR)
+            {
+                return ret_flag;
+            }
+        }
+        ret = USB_HOST_PIPE_IN;
+    }
+    else                                                            /* OUT(send)    */
+    {
+        if (PipeCfg == USB_HOST_ISO)
+        {
+            /* Transfer Type is ISO*/
+            PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+        }
+        else
+        {
+            /* Transfer Type is BULK or INT */
+            PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+        }
+        PipeCfg |= USB_HOST_DIR_H_OUT;
+        ret = USB_HOST_PIPE_OUT;
+    }
+
+    switch (user_table->fifo_port)
+    {
+        case USB_HOST_CUSE:
+            g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE;
+        break;
+
+        case USB_HOST_D0USE:
+            g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE;
+        break;
+
+        case USB_HOST_D1USE:
+            g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE;
+        break;
+
+        case USB_HOST_D0DMA:
+            g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA;
+        break;
+
+        case USB_HOST_D1DMA:
+            g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA;
+        break;
+
+        default:
+            ret_flag = USB_END_POINT_ERROR;
+        break;
+    }
+
+    if (ret_flag == USB_END_POINT_ERROR)
+    {
+        return ret_flag;
+    }
+
+    /* Endpoint number set              */
+    PipeCfg  |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+    g_usb1_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+
+    /* Max packet size set              */
+    PipeMaxp  = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8));
+
+    if (PipeMaxp == 0u)
+    {
+        return USB_END_POINT_ERROR;
+    }
+
+    /* Set device address               */
+    PipeMaxp |= (uint16_t)(devadr << 12);
+
+    user_table->pipe_cfg         = PipeCfg;
+    user_table->pipe_max_pktsize = PipeMaxp;
+
+    usb1_host_resetEP(user_table);
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_resetEP
+* Description  : Sets the end point on the information specified by the argument.
+* Arguments    : USB_HOST_CFG_PIPETBL_t *tbl : pipe table
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl)
+{
+
+    uint16_t pipe;
+
+    /* Host pipe */
+    /* The pipe number of pipe definition table is obtained */
+    pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE);  /* Pipe Number */
+
+    /* FIFO port access pipe is set to initial value */
+    /* The connection with FIFO should be cut before setting the pipe */
+    if (RZA_IO_RegRead_16(&USB201.CFIFOSEL,
+                            USB_CFIFOSEL_CURPIPE_SHIFT,
+                            USB_CFIFOSEL_CURPIPE) == pipe)
+    {
+        usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    if (RZA_IO_RegRead_16(&USB201.D0FIFOSEL,
+                            USB_DnFIFOSEL_CURPIPE_SHIFT,
+                            USB_DnFIFOSEL_CURPIPE) == pipe)
+    {
+        usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    if (RZA_IO_RegRead_16(&USB201.D1FIFOSEL,
+                            USB_DnFIFOSEL_CURPIPE_SHIFT,
+                            USB_DnFIFOSEL_CURPIPE) == pipe)
+    {
+        usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+    }
+
+    /* Interrupt of pipe set is disabled */
+    usb1_host_disable_brdy_int(pipe);
+    usb1_host_disable_nrdy_int(pipe);
+    usb1_host_disable_bemp_int(pipe);
+
+    /* Pipe to set is set to NAK */
+    usb1_host_set_pid_nak(pipe);
+
+    /* Pipe is set */
+    USB201.PIPESEL  = pipe;
+
+    USB201.PIPECFG  = tbl->pipe_cfg;
+    USB201.PIPEBUF  = tbl->pipe_buf;
+    USB201.PIPEMAXP = tbl->pipe_max_pktsize;
+    USB201.PIPEPERI = tbl->pipe_cycle;
+
+    g_usb1_host_pipecfg[pipe]  = tbl->pipe_cfg;
+    g_usb1_host_pipebuf[pipe]  = tbl->pipe_buf;
+    g_usb1_host_pipemaxp[pipe] = tbl->pipe_max_pktsize;
+    g_usb1_host_pipeperi[pipe] = tbl->pipe_cycle;
+
+    /* Sequence bit clear */
+    usb1_host_set_sqclr(pipe);
+
+    usb1_host_aclrm(pipe);
+    usb1_host_set_csclr(pipe);
+
+    /* Pipe window selection is set to unused */
+    USB201.PIPESEL = USB_HOST_PIPE0;
+
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb1_api_host_data_count
+* Description  : Get g_usb0_host_data_count[pipe]
+* Arguments    : uint16_t pipe        ; Pipe Number
+*              : uint32_t *data_count ; return g_usb0_data_count[pipe]
+* Return Value : DEVDRV_SUCCESS    ; success
+*              : DEVDRV_ERROR      ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_count (uint16_t pipe, uint32_t * data_count)
+{
+    if (pipe > USB_HOST_MAX_PIPE_NO)
+    {
+        return DEVDRV_ERROR;
+    }
+
+    *data_count = g_usb1_host_PipeDataSize[pipe];
+
+    return DEVDRV_SUCCESS;
+}
+#endif
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/host/usb1_host_global.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+const uint16_t g_usb1_host_bit_set[16] =
+{
+    0x0001, 0x0002, 0x0004, 0x0008,
+    0x0010, 0x0020, 0x0040, 0x0080,
+    0x0100, 0x0200, 0x0400, 0x0800,
+    0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t  g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+uint8_t * g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+uint16_t  g_usb1_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb1_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb1_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1];
+uint32_t  g_usb1_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1];
+
+USB_HOST_DMA_t g_usb1_host_DmaInfo[2];
+
+uint16_t  g_usb1_host_DmaPipe[2];
+uint16_t  g_usb1_host_DmaBval[2];
+uint16_t  g_usb1_host_DmaStatus[2];
+
+uint16_t  g_usb1_host_driver_state;
+uint16_t  g_usb1_host_ConfigNum;
+uint16_t  g_usb1_host_CmdStage;
+uint16_t  g_usb1_host_bchg_flag;
+uint16_t  g_usb1_host_detach_flag;
+uint16_t  g_usb1_host_attach_flag;
+
+uint16_t  g_usb1_host_UsbAddress;
+uint16_t  g_usb1_host_setUsbAddress;
+uint16_t  g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+uint16_t  g_usb1_host_UsbDeviceSpeed;
+uint16_t  g_usb1_host_SupportUsbDeviceSpeed;
+
+uint16_t  g_usb1_host_SavReq;
+uint16_t  g_usb1_host_SavVal;
+uint16_t  g_usb1_host_SavIndx;
+uint16_t  g_usb1_host_SavLen;
+
+uint16_t  g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t  g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_init_pipe_status
+* Description  : Initialize pipe status.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_init_pipe_status (void)
+{
+    uint16_t loop;
+
+    g_usb1_host_ConfigNum = 0;
+
+    for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop)
+    {
+        g_usb1_host_pipe_status[loop]   = USB_HOST_PIPE_IDLE;
+        g_usb1_host_PipeDataSize[loop]  = 0;
+
+        /* pipe configuration in usb1_host_resetEP() */
+        g_usb1_host_pipecfg[loop]  = 0;
+        g_usb1_host_pipebuf[loop]  = 0;
+        g_usb1_host_pipemaxp[loop] = 0;
+        g_usb1_host_pipeperi[loop] = 0;
+    }
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/host/usb1_host_usbint.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,497 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_usbint.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_interrupt1(void);
+static void usb1_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb1_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb1_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_interrupt
+* Description  : Executes USB interrupt.
+*              : Register this function in the USB interrupt handler.
+*              : Set CFIF0 in the pipe set before the interrupt after executing
+*              : this function.
+* Arguments    : uint32_t int_sense ; Interrupts detection mode
+*              :                    ;  INTC_LEVEL_SENSITIVE : Level sense
+*              :                    ;  INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_interrupt (uint32_t int_sense)
+{
+    uint16_t savepipe1;
+    uint16_t savepipe2;
+    uint16_t buffer;
+
+    savepipe1 = USB201.CFIFOSEL;
+    savepipe2 = USB201.PIPESEL;
+    usb1_host_interrupt1();
+
+    /* Control transmission changes ISEL within interruption processing. */
+    /* For this reason, write return of ISEL cannot be performed. */
+    buffer = USB201.CFIFOSEL;
+    buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+    buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE);
+    USB201.CFIFOSEL = buffer;
+    USB201.PIPESEL = savepipe2;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_interrupt1
+* Description  : Execue the USB interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_interrupt1 (void)
+{
+    uint16_t intsts0;
+    uint16_t intsts1;
+    uint16_t intenb0;
+    uint16_t intenb1;
+    uint16_t brdysts;
+    uint16_t nrdysts;
+    uint16_t bempsts;
+    uint16_t brdyenb;
+    uint16_t nrdyenb;
+    uint16_t bempenb;
+    volatile uint16_t dumy_sts;
+
+    intsts0 = USB201.INTSTS0;
+    intsts1 = USB201.INTSTS1;
+    intenb0 = USB201.INTENB0;
+    intenb1 = USB201.INTENB1;
+
+    if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
+    {
+            USB201.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
+            RZA_IO_RegWrite_16(&USB201.INTENB1,
+                                0,
+                                USB_INTENB1_BCHGE_SHIFT,
+                                USB_INTENB1_BCHGE);
+            g_usb1_host_bchg_flag = USB_HOST_YES;
+    }
+    else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
+    {
+        USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
+#if(1) /* ohci_wrapp */
+        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+#else
+        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+        g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+#endif
+    }
+    else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
+    {
+        USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
+#if(1) /* ohci_wrapp */
+        g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;  /* exit NORES */
+        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#else
+        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+        g_usb1_host_CmdStage |= USB_HOST_CMD_NORES;
+#endif
+    }
+    else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
+          && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
+    {
+        USB201.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
+        RZA_IO_RegWrite_16(&USB201.INTENB1,
+                            0,
+                            USB_INTENB1_DTCHE_SHIFT,
+                            USB_INTENB1_DTCHE);
+        g_usb1_host_detach_flag = USB_HOST_YES;
+
+        Userdef_USB_usb1_host_detach();
+
+        usb1_host_UsbDetach2();
+    }
+    else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
+          && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
+    {
+        USB201.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
+        RZA_IO_RegWrite_16(&USB201.INTENB1,
+                            0,
+                            USB_INTENB1_ATTCHE_SHIFT,
+                            USB_INTENB1_ATTCHE);
+        g_usb1_host_attach_flag = USB_HOST_YES;
+
+        Userdef_USB_usb1_host_attach();
+
+        usb1_host_UsbAttach();
+    }
+    else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
+    {
+        brdysts = USB201.BRDYSTS;
+        nrdysts = USB201.NRDYSTS;
+        bempsts = USB201.BEMPSTS;
+        brdyenb = USB201.BRDYENB;
+        nrdyenb = USB201.NRDYENB;
+        bempenb = USB201.BEMPENB;
+
+        if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
+        {
+            usb1_host_BRDYInterrupt(brdysts, brdyenb);
+        }
+        else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
+        {
+            usb1_host_BEMPInterrupt(bempsts, bempenb);
+        }
+        else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
+        {
+            usb1_host_NRDYInterrupt(nrdysts, nrdyenb);
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* Three dummy read for clearing interrupt requests */
+    dumy_sts = USB201.INTSTS0;
+    dumy_sts = USB201.INTSTS1;
+
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_BRDYInterrupt
+* Description  : Executes USB BRDY interrupt.
+* Arguments    : uint16_t Status   ; BRDYSTS Register Value
+*              : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          buffer;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB201.BRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+
+#if(1) /* ohci_wrapp */
+        switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+        {
+            case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                buffer  = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+                usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+            break;
+
+            case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                buffer  = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+                switch (buffer)
+                {
+                    case USB_HOST_READING:                  /* Continue of data read */
+                    break;
+
+                    case USB_HOST_READEND:                  /* End of data read */
+                    case USB_HOST_READSHRT:                 /* End of data read */
+                        usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                    break;
+
+                    case USB_HOST_READOVER:                 /* buffer over */
+                        USB201.CFIFOCTR = USB_HOST_BITBCLR;
+                        usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                        ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                    break;
+
+                    case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                    default:
+                    break;
+                }
+            break;
+
+            default:
+            break;
+        }
+#else
+        switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+        {
+            case (USB_HOST_MODE_WRITE   | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+            case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                buffer  = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+                usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+            break;
+
+            case (USB_HOST_MODE_READ   | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                buffer  = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+
+                switch (buffer)
+                {
+                    case USB_HOST_READING:                  /* Continue of data read */
+                    break;
+
+                    case USB_HOST_READEND:                  /* End of data read */
+                    case USB_HOST_READSHRT:                 /* End of data read */
+                        usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                    break;
+
+                    case USB_HOST_READOVER:                 /* buffer over */
+                        USB201.CFIFOCTR = USB_HOST_BITBCLR;
+                        usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+                        g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                        g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                    break;
+
+                    case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                    default:
+                    break;
+                }
+            break;
+
+            default:
+            break;
+        }
+#endif
+    }
+    else
+    {
+        usb1_host_brdy_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB201.BRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_NRDYInterrupt
+* Description  : Executes USB NRDY interrupt.
+* Arguments    : uint16_t Status        ; NRDYSTS Register Value
+*              : uint16_t Int_enbl      ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          pid;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB201.NRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+        pid = usb1_host_get_pid(USB_HOST_PIPE0);
+
+        if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+        {
+            g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+
+        }
+        else if (pid  == USB_HOST_PID_NAK)
+        {
+            g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_CMD_NORES;
+#if(1) /* ohci_wrapp */
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else
+    {
+        usb1_host_nrdy_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB201.NRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_BEMPInterrupt
+* Description  : Executes USB BEMP interrupt.
+* Arguments    : uint16_t Status        ; BEMPSTS Register Value
+*              : uint16_t Int_enbl      ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+    uint16_t          buffer;
+    uint16_t          pid;
+    volatile uint16_t dumy_sts;
+
+    if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+    {
+        USB201.BEMPSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+        pid = usb1_host_get_pid(USB_HOST_PIPE0);
+
+        if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+        {
+            g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+            g_usb1_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+            g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;      /* exit STALL */
+            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+        }
+        else
+        {
+#if(1) /* ohci_wrapp */
+            switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+            {
+                case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                    ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                break;
+
+                case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                    buffer  = usb1_host_write_buffer(USB_HOST_PIPE0);
+                    switch (buffer)
+                    {
+                        case USB_HOST_WRITING:                  /* Continue of data write */
+                        case USB_HOST_WRITEEND:                 /* End of data write (zero-length) */
+                        break;
+
+                        case USB_HOST_WRITESHRT:                    /* End of data write */
+                            g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                            g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                            ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+                        break;
+
+                        case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                        default:
+                        break;
+                    }
+                break;
+
+                default:
+                    /* do nothing */
+                break;
+            }
+#else
+            switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+            {
+                case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+                break;
+
+                case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+                    buffer  = usb1_host_write_buffer(USB_HOST_PIPE0);
+                    switch (buffer)
+                    {
+                        case USB_HOST_WRITING:                  /* Continue of data write */
+                        case USB_HOST_WRITEEND:                 /* End of data write (zero-length) */
+                        break;
+
+                        case USB_HOST_WRITESHRT:                    /* End of data write */
+                            g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+                            g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+                        break;
+
+                        case USB_HOST_FIFOERROR:                    /* FIFO access error */
+                        default:
+                        break;
+                    }
+                break;
+
+                case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+                    g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+                    g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+                break;
+
+                default:
+                    /* do nothing */
+                break;
+            }
+#endif
+        }
+    }
+    else
+    {
+        usb1_host_bemp_int(Status, Int_enbl);
+    }
+
+    /* Three dummy reads for clearing interrupt requests */
+    dumy_sts = USB201.BEMPSTS;
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/host/usb1_host_usbsig.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,637 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_usbsig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_EnableINT_Module(void);
+static void usb1_host_Enable_AttachINT(void);
+static void usb1_host_Disable_AttachINT(void);
+static void usb1_host_Disable_BchgINT(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_InitModule
+* Description  : Initializes the USB module in USB host module.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_InitModule (void)
+{
+    uint16_t buf1;
+    uint16_t buf2;
+    uint16_t buf3;
+
+    usb1_host_init_pipe_status();
+
+    RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                        1,
+                        USB_SYSCFG_DCFM_SHIFT,
+                        USB_SYSCFG_DCFM);       /* HOST mode */
+    RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                        1,
+                        USB_SYSCFG_DRPD_SHIFT,
+                        USB_SYSCFG_DRPD);       /* PORT0 D+, D- setting */
+
+    do
+    {
+        buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb1_host_delay_xms(50);
+        buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb1_host_delay_xms(50);
+        buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+
+    } while ((buf1 != buf2) || (buf1 != buf3));
+
+    RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                        1,
+                        USB_SYSCFG_USBE_SHIFT,
+                        USB_SYSCFG_USBE);
+
+    USB201.CFIFOSEL  = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+    USB201.D0FIFOSEL = (uint16_t)(                   USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+    USB201.D1FIFOSEL = (uint16_t)(                   USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CheckAttach
+* Description  : Returns the USB device connection state.
+* Arguments    : none
+* Return Value : uint16_t ; USB_HOST_ATTACH : Attached
+*              :          ; USB_HOST_DETACH : not Attached
+*******************************************************************************/
+uint16_t usb1_host_CheckAttach (void)
+{
+    uint16_t buf1;
+    uint16_t buf2;
+    uint16_t buf3;
+    uint16_t rhst;
+
+    do
+    {
+        buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb1_host_delay_xms(50);
+        buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+        Userdef_USB_usb1_host_delay_xms(50);
+        buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+
+    } while ((buf1 != buf2) || (buf1 != buf3));
+
+    rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+                                USB_DVSTCTR0_RHST_SHIFT,
+                                USB_DVSTCTR0_RHST);
+    if (rhst == USB_HOST_UNDECID)
+    {
+        if (buf1 == USB_HOST_FS_JSTS)
+        {
+            if (g_usb1_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED)
+            {
+                RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                                    1,
+                                    USB_SYSCFG_HSE_SHIFT,
+                                    USB_SYSCFG_HSE);
+            }
+            else
+            {
+                RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                                    0,
+                                    USB_SYSCFG_HSE_SHIFT,
+                                    USB_SYSCFG_HSE);
+            }
+            return USB_HOST_ATTACH;
+        }
+        else if (buf1 == USB_HOST_LS_JSTS)
+        {
+            /* Low Speed Device */
+            RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+                                0,
+                                USB_SYSCFG_HSE_SHIFT,
+                                USB_SYSCFG_HSE);
+            return USB_HOST_ATTACH;
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+    }
+    else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE))
+    {
+        return USB_HOST_ATTACH;
+    }
+    else if (rhst == USB_HOST_LSMODE)
+    {
+        return USB_HOST_ATTACH;
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    return USB_HOST_DETACH;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbAttach
+* Description  : Connects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbAttach (void)
+{
+    usb1_host_EnableINT_Module();
+    usb1_host_Disable_BchgINT();
+    usb1_host_Disable_AttachINT();
+    usb1_host_Enable_DetachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbDetach
+* Description  : Disconnects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbDetach (void)
+{
+    uint16_t pipe;
+    uint16_t devadr;
+
+    g_usb1_host_driver_state = USB_HOST_DRV_DETACHED;
+
+    /* Terminate all the pipes in which communications on port  */
+    /* are currently carried out                                */
+    for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe)
+    {
+        if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE)
+        {
+            if (pipe == USB_HOST_PIPE0)
+            {
+                devadr = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+                                            USB_DCPMAXP_DEVSEL_SHIFT,
+                                            USB_DCPMAXP_DEVSEL);
+            }
+            else
+            {
+                devadr = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL);
+            }
+
+            if (devadr == g_usb1_host_UsbAddress)
+            {
+                usb1_host_stop_transfer(pipe);
+            }
+
+            g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE;
+        }
+    }
+
+    g_usb1_host_ConfigNum  = 0;
+    g_usb1_host_UsbAddress = 0;
+    g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+    usb1_host_UsbDetach2();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbDetach2
+* Description  : Disconnects the USB device.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbDetach2 (void)
+{
+    usb1_host_Disable_DetachINT();
+    usb1_host_Disable_BchgINT();
+    usb1_host_Enable_AttachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbBusReset
+* Description  : Issues the USB bus reset signal.
+* Arguments    : none
+* Return Value : uint16_t               ; RHST
+*******************************************************************************/
+uint16_t usb1_host_UsbBusReset (void)
+{
+    uint16_t buffer;
+    uint16_t loop;
+
+    RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+                        1,
+                        USB_DVSTCTR0_USBRST_SHIFT,
+                        USB_DVSTCTR0_USBRST);
+    RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+                        0,
+                        USB_DVSTCTR0_UACT_SHIFT,
+                        USB_DVSTCTR0_UACT);
+
+    Userdef_USB_usb1_host_delay_xms(50);
+
+    buffer  = USB201.DVSTCTR0;
+    buffer &= (uint16_t)(~(USB_HOST_BITRST));
+    buffer |= USB_HOST_BITUACT;
+    USB201.DVSTCTR0 = buffer;
+
+    Userdef_USB_usb1_host_delay_xms(20);
+
+    for (loop = 0, buffer = USB_HOST_HSPROC;  loop < 3; ++loop)
+    {
+        buffer = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+                                    USB_DVSTCTR0_RHST_SHIFT,
+                                    USB_DVSTCTR0_RHST);
+        if (buffer == USB_HOST_HSPROC)
+        {
+            Userdef_USB_usb1_host_delay_xms(10);
+        }
+        else
+        {
+            break;
+        }
+    }
+
+    return buffer;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbResume
+* Description  : Issues the USB resume signal.
+* Arguments    : none
+* Return Value : int32_t            ; DEVDRV_SUCCESS
+*              :                    ; DEVDRV_ERROR
+*******************************************************************************/
+int32_t usb1_host_UsbResume (void)
+{
+    uint16_t buf;
+
+    if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) == 0)
+    {
+        /* not SUSPEND */
+        return DEVDRV_ERROR;
+    }
+
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        0,
+                        USB_INTENB1_BCHGE_SHIFT,
+                        USB_INTENB1_BCHGE);
+    RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+                        1,
+                        USB_DVSTCTR0_RESUME_SHIFT,
+                        USB_DVSTCTR0_RESUME);
+    Userdef_USB_usb1_host_delay_xms(20);
+
+    buf  = USB201.DVSTCTR0;
+    buf &= (uint16_t)(~(USB_HOST_BITRESUME));
+    buf |= USB_HOST_BITUACT;
+    USB201.DVSTCTR0 = buf;
+
+    g_usb1_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND;
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbSuspend
+* Description  : Issues the USB suspend signal.
+* Arguments    : none
+* Return Value : int32_t            ; DEVDRV_SUCCESS   :not SUSPEND
+*              :                    ; DEVDRV_ERROR     :SUSPEND
+*******************************************************************************/
+int32_t usb1_host_UsbSuspend (void)
+{
+    uint16_t buf;
+
+    if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) != 0)
+    {
+        /* SUSPEND */
+        return DEVDRV_ERROR;
+    }
+
+    RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+                        0,
+                        USB_DVSTCTR0_UACT_SHIFT,
+                        USB_DVSTCTR0_UACT);
+
+    Userdef_USB_usb1_host_delay_xms(5);
+
+    buf = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+                                USB_SYSSTS0_LNST_SHIFT,
+                                USB_SYSSTS0_LNST);
+    if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS))
+    {
+        usb1_host_UsbDetach();
+    }
+    else
+    {
+        g_usb1_host_driver_state |= USB_HOST_DRV_SUSPEND;
+    }
+
+    return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Enable_DetachINT
+* Description  : Enables the USB disconnection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Enable_DetachINT (void)
+{
+    USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        1,
+                        USB_INTENB1_DTCHE_SHIFT,
+                        USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_DetachINT
+* Description  : Disables the USB disconnection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_DetachINT (void)
+{
+    USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        0,
+                        USB_INTENB1_DTCHE_SHIFT,
+                        USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Enable_AttachINT
+* Description  : Enables the USB connection detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Enable_AttachINT (void)
+{
+    USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        1,
+                        USB_INTENB1_ATTCHE_SHIFT,
+                        USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_AttachINT
+* Description  : Disables the USB connection detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_AttachINT (void)
+{
+    USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        0,
+                        USB_INTENB1_ATTCHE_SHIFT,
+                        USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_BchgINT
+* Description  : Disables the USB bus change detection interrupt.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_BchgINT (void)
+{
+    USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG));
+    RZA_IO_RegWrite_16(&USB201.INTENB1,
+                        0,
+                        USB_INTENB1_BCHGE_SHIFT,
+                        USB_INTENB1_BCHGE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_devadd
+* Description  : DEVADDn register is set by specified value
+* Arguments    : uint16_t addr             : Device address
+*              : uint16_t *devadd          : Set value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_devadd (uint16_t addr, uint16_t * devadd)
+{
+    uint16_t * ptr;
+    uint16_t ret_flag = DEVDRV_FLAG_ON;                             // avoid warning.
+
+    switch (addr)
+    {
+        case USB_HOST_DEVICE_0:
+            ptr = (uint16_t *)&USB201.DEVADD0;
+        break;
+
+        case USB_HOST_DEVICE_1:
+            ptr = (uint16_t *)&USB201.DEVADD1;
+        break;
+
+        case USB_HOST_DEVICE_2:
+            ptr = (uint16_t *)&USB201.DEVADD2;
+        break;
+
+        case USB_HOST_DEVICE_3:
+            ptr = (uint16_t *)&USB201.DEVADD3;
+        break;
+
+        case USB_HOST_DEVICE_4:
+            ptr = (uint16_t *)&USB201.DEVADD4;
+        break;
+
+        case USB_HOST_DEVICE_5:
+            ptr = (uint16_t *)&USB201.DEVADD5;
+        break;
+
+        case USB_HOST_DEVICE_6:
+            ptr = (uint16_t *)&USB201.DEVADD6;
+        break;
+
+        case USB_HOST_DEVICE_7:
+            ptr = (uint16_t *)&USB201.DEVADD7;
+        break;
+
+        case USB_HOST_DEVICE_8:
+            ptr = (uint16_t *)&USB201.DEVADD8;
+        break;
+
+        case USB_HOST_DEVICE_9:
+            ptr = (uint16_t *)&USB201.DEVADD9;
+        break;
+
+        case USB_HOST_DEVICE_10:
+            ptr = (uint16_t *)&USB201.DEVADDA;
+        break;
+
+        default:
+            ret_flag = DEVDRV_FLAG_OFF;
+        break;
+    }
+
+    if (ret_flag == DEVDRV_FLAG_ON)
+    {
+        *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_devadd
+* Description  : DEVADDn register is obtained
+* Arguments    : uint16_t addr      : Device address
+*              : uint16_t *devadd   : USB_HOST_DEVADD register value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_get_devadd (uint16_t addr, uint16_t * devadd)
+{
+    uint16_t * ptr;
+    uint16_t ret_flag = DEVDRV_FLAG_ON;                             // avoid warning.
+
+    switch (addr)
+    {
+        case USB_HOST_DEVICE_0:
+            ptr = (uint16_t *)&USB201.DEVADD0;
+        break;
+
+        case USB_HOST_DEVICE_1:
+            ptr = (uint16_t *)&USB201.DEVADD1;
+        break;
+
+        case USB_HOST_DEVICE_2:
+            ptr = (uint16_t *)&USB201.DEVADD2;
+        break;
+
+        case USB_HOST_DEVICE_3:
+            ptr = (uint16_t *)&USB201.DEVADD3;
+        break;
+
+        case USB_HOST_DEVICE_4:
+            ptr = (uint16_t *)&USB201.DEVADD4;
+        break;
+
+        case USB_HOST_DEVICE_5:
+            ptr = (uint16_t *)&USB201.DEVADD5;
+        break;
+
+        case USB_HOST_DEVICE_6:
+            ptr = (uint16_t *)&USB201.DEVADD6;
+        break;
+
+        case USB_HOST_DEVICE_7:
+            ptr = (uint16_t *)&USB201.DEVADD7;
+        break;
+
+        case USB_HOST_DEVICE_8:
+            ptr = (uint16_t *)&USB201.DEVADD8;
+        break;
+
+        case USB_HOST_DEVICE_9:
+            ptr = (uint16_t *)&USB201.DEVADD9;
+        break;
+
+        case USB_HOST_DEVICE_10:
+            ptr = (uint16_t *)&USB201.DEVADDA;
+        break;
+
+        default:
+            ret_flag = DEVDRV_FLAG_OFF;
+        break;
+    }
+
+    if (ret_flag == DEVDRV_FLAG_ON)
+    {
+        *devadd = *ptr;
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_EnableINT_Module
+* Description  : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt.
+*              : Enables NRDY/BEMP interrupt in the pipe0.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_EnableINT_Module (void)
+{
+    uint16_t buf;
+
+    buf  = USB201.INTENB0;
+    buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE);
+    USB201.INTENB0 = buf;
+
+    buf  = USB201.INTENB1;
+    buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE);
+    USB201.INTENB1 = buf;
+
+    usb1_host_enable_nrdy_int(USB_HOST_PIPE0);
+    usb1_host_enable_bemp_int(USB_HOST_PIPE0);
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,698 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb1_host_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE   (255)       /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+    DMAC_REQ_MID,
+    DMAC_REQ_RID,
+    DMAC_REQ_AM,
+    DMAC_REQ_LVL,
+    DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb1_host_dmac_peri_req_init_table[8][5] =
+{
+  /* MID,RID, AM,LVL,REQD */
+    { 32,  3,  2,  1,  1},      /* USB_0 channel 0 transmit FIFO empty */
+    { 32,  3,  2,  1,  0},      /* USB_0 channel 0 receive FIFO full   */
+    { 33,  3,  2,  1,  1},      /* USB_0 channel 1 transmit FIFO empty */
+    { 33,  3,  2,  1,  0},      /* USB_0 channel 1 receive FIFO full   */
+    { 34,  3,  2,  1,  1},      /* USB_1 channel 0 transmit FIFO empty */
+    { 34,  3,  2,  1,  0},      /* USB_1 channel 0 receive FIFO full   */
+    { 35,  3,  2,  1,  1},      /* USB_1 channel 1 transmit FIFO empty */
+    { 35,  3,  2,  1,  0},      /* USB_1 channel 1 receive FIFO full   */
+};
+
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_PeriReqInit
+* Description  : Sets the register mode for DMA mode and the on-chip peripheral
+*              : module request for transfer request for DMAC channel 3.
+*              : Executes DMAC initial setting using the DMA information
+*              : specified by the argument *trans_info and the enabled/disabled
+*              : continuous transfer specified by the argument continuation.
+*              : Registers DMAC channel 3 interrupt handler function and sets
+*              : the interrupt priority level. Then enables transfer completion
+*              : interrupt.
+* Arguments    : dmac_transinfo_t * trans_info : Setting information to DMAC
+*              :                               : register
+*              : uint32_t dmamode      : DMA mode (only for DMAC_MODE_REGISTER)
+*              : uint32_t continuation : Set continuous transfer to be valid
+*              :                       : after DMA transfer has been completed
+*              :         DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+*              :         DMAC_SAMPLE_SINGLE       : Do not execute continuous
+*              :                                  : transfer
+*              : uint32_t request_factor : Factor for on-chip peripheral module
+*              :                         : request
+*              :         DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+*              :         DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+*              :         DMAC_REQ_TGI0A     : MTU2_0 input capture/compare match
+*              :                 :
+*              : uint32_t req_direction : Setting value of CHCFG_n register
+*              :                        : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                              uint32_t request_factor, uint32_t req_direction)
+{
+    /* ==== Register mode ==== */
+    if (DMAC_MODE_REGISTER == dmamode)
+    {
+        /* ==== Next0 register set ==== */
+        DMAC3.N0SA_n = trans_info->src_addr;        /* Start address of transfer source      */
+        DMAC3.N0DA_n = trans_info->dst_addr;        /* Start address of transfer destination */
+        DMAC3.N0TB_n = trans_info->count;           /* Total transfer byte count             */
+
+        /* DAD : Transfer destination address counting direction */
+        /* SAD : Transfer source address counting direction      */
+        /* DDS : Transfer destination transfer size              */
+        /* SDS : Transfer source transfer size                   */
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            trans_info->daddr_dir,
+                            DMAC3_CHCFG_n_DAD_SHIFT,
+                            DMAC3_CHCFG_n_DAD);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            trans_info->saddr_dir,
+                            DMAC3_CHCFG_n_SAD_SHIFT,
+                            DMAC3_CHCFG_n_SAD);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            trans_info->dst_size,
+                            DMAC3_CHCFG_n_DDS_SHIFT,
+                            DMAC3_CHCFG_n_DDS);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            trans_info->src_size,
+                            DMAC3_CHCFG_n_SDS_SHIFT,
+                            DMAC3_CHCFG_n_SDS);
+
+        /* DMS  : Register mode                            */
+        /* RSEL : Select Next0 register set                */
+        /* SBE  : No discharge of buffer data when aborted */
+        /* DEM  : No DMA interrupt mask                    */
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_DMS_SHIFT,
+                            DMAC3_CHCFG_n_DMS);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_RSEL_SHIFT,
+                            DMAC3_CHCFG_n_RSEL);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_SBE_SHIFT,
+                            DMAC3_CHCFG_n_SBE);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_DEM_SHIFT,
+                            DMAC3_CHCFG_n_DEM);
+
+        /* ---- Continuous transfer ---- */
+        if (DMAC_SAMPLE_CONTINUATION == continuation)
+        {
+            /* REN : Execute continuous transfer                         */
+            /* RSW : Change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                1,
+                                DMAC3_CHCFG_n_REN_SHIFT,
+                                DMAC3_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                1,
+                                DMAC3_CHCFG_n_RSW_SHIFT,
+                                DMAC3_CHCFG_n_RSW);
+        }
+        /* ---- Single transfer ---- */
+        else
+        {
+            /* REN : Do not execute continuous transfer                         */
+            /* RSW : Do not change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                0,
+                                DMAC3_CHCFG_n_REN_SHIFT,
+                                DMAC3_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                0,
+                                DMAC3_CHCFG_n_RSW_SHIFT,
+                                DMAC3_CHCFG_n_RSW);
+        }
+
+        /* TM  : Single transfer                          */
+        /* SEL : Channel setting                          */
+        /* HIEN, LOEN : On-chip peripheral module request */
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_TM_SHIFT,
+                            DMAC3_CHCFG_n_TM);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            3,
+                            DMAC3_CHCFG_n_SEL_SHIFT,
+                            DMAC3_CHCFG_n_SEL);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            1,
+                            DMAC3_CHCFG_n_HIEN_SHIFT,
+                            DMAC3_CHCFG_n_HIEN);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            0,
+                            DMAC3_CHCFG_n_LOEN_SHIFT,
+                            DMAC3_CHCFG_n_LOEN);
+
+        /* ---- Set factor by specified on-chip peripheral module request ---- */
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+                            DMAC3_CHCFG_n_AM_SHIFT,
+                            DMAC3_CHCFG_n_AM);
+        RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+                            DMAC3_CHCFG_n_LVL_SHIFT,
+                            DMAC3_CHCFG_n_LVL);
+        if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+        {
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+                                DMAC3_CHCFG_n_REQD_SHIFT,
+                                DMAC3_CHCFG_n_REQD);
+        }
+        else
+        {
+            RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+                                req_direction,
+                                DMAC3_CHCFG_n_REQD_SHIFT,
+                                DMAC3_CHCFG_n_REQD);
+        }
+        RZA_IO_RegWrite_32(&DMAC23.DMARS,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+                            DMAC23_DMARS_CH3_RID_SHIFT,
+                            DMAC23_DMARS_CH3_RID);
+        RZA_IO_RegWrite_32(&DMAC23.DMARS,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+                            DMAC23_DMARS_CH3_MID_SHIFT,
+                            DMAC23_DMARS_CH3_MID);
+
+        /* PR : Round robin mode */
+        RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+                            1,
+                            DMAC07_DCTRL_0_7_PR_SHIFT,
+                            DMAC07_DCTRL_0_7_PR);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Open
+* Description  : Enables DMAC channel 3 transfer.
+* Arguments    : uint32_t req : DMAC request mode
+* Return Value :  0 : Succeeded in enabling DMA transfer
+*              : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_host_DMAC3_Open (uint32_t req)
+{
+    int32_t ret;
+    volatile uint8_t  dummy;
+
+    /* Transferable? */
+    if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+                                DMAC3_CHSTAT_n_EN_SHIFT,
+                                DMAC3_CHSTAT_n_EN)) &&
+        (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+                                DMAC3_CHSTAT_n_TACT_SHIFT,
+                                DMAC3_CHSTAT_n_TACT)))
+    {
+        /* Clear Channel Status Register */
+        RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+                            1,
+                            DMAC3_CHCTRL_n_SWRST_SHIFT,
+                            DMAC3_CHCTRL_n_SWRST);
+        dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
+                                DMAC3_CHCTRL_n_SWRST_SHIFT,
+                                DMAC3_CHCTRL_n_SWRST);
+        /* Enable DMA transfer */
+        RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+                            1,
+                            DMAC3_CHCTRL_n_SETEN_SHIFT,
+                            DMAC3_CHCTRL_n_SETEN);
+
+        /* ---- Request by software ---- */
+        if (DMAC_REQ_MODE_SOFT == req)
+        {
+            /* DMA transfer Request by software */
+            RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+                                1,
+                                DMAC3_CHCTRL_n_STG_SHIFT,
+                                DMAC3_CHCTRL_n_STG);
+        }
+
+        ret = 0;
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Close
+* Description  : Aborts DMAC channel 3 transfer. Returns the remaining transfer
+*              : byte count at the time of DMA transfer abort to the argument
+*              : *remain.
+* Arguments    : uint32_t * remain : Remaining transfer byte count when
+*              :                   : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_Close (uint32_t * remain)
+{
+
+    /* ==== Abort transfer ==== */
+    RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+                        1,
+                        DMAC3_CHCTRL_n_CLREN_SHIFT,
+                        DMAC3_CHCTRL_n_CLREN);
+
+    while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+                                DMAC3_CHSTAT_n_TACT_SHIFT,
+                                DMAC3_CHSTAT_n_TACT))
+    {
+        /* Loop until transfer is aborted */
+    }
+
+    while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+                                DMAC3_CHSTAT_n_EN_SHIFT,
+                                DMAC3_CHSTAT_n_EN))
+    {
+        /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+    }
+    /* ==== Obtain remaining transfer byte count ==== */
+    *remain = DMAC3.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Load_Set
+* Description  : Sets the transfer source address, transfer destination
+*              : address, and total transfer byte count respectively
+*              : specified by the argument src_addr, dst_addr, and count to
+*              : DMAC channel 3 as DMA transfer information.
+*              : Sets the register set selected by the CHCFG_n register
+*              : RSEL bit from the Next0 or Next1 register set.
+*              : This function should be called when DMA transfer of DMAC
+*              : channel 3 is aboted.
+* Arguments    : uint32_t src_addr : Transfer source address
+*              : uint32_t dst_addr : Transfer destination address
+*              : uint32_t count    : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+    uint8_t reg_set;
+
+    /* Obtain register set in use */
+    reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+                                DMAC3_CHSTAT_n_SR_SHIFT,
+                                DMAC3_CHSTAT_n_SR);
+
+    /* ==== Load ==== */
+    if (0 == reg_set)
+    {
+        /* ---- Next0 Register Set ---- */
+        DMAC3.N0SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC3.N0DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC3.N0TB_n = count;       /* Total transfer byte count             */
+    }
+    else
+    {
+        /* ---- Next1 Register Set ---- */
+        DMAC3.N1SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC3.N1DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC3.N1TB_n = count;       /* Total transfer byte count             */
+     }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_PeriReqInit
+* Description  : Sets the register mode for DMA mode and the on-chip peripheral
+*              : module request for transfer request for DMAC channel 4.
+*              : Executes DMAC initial setting using the DMA information
+*              : specified by the argument *trans_info and the enabled/disabled
+*              : continuous transfer specified by the argument continuation.
+*              : Registers DMAC channel 4 interrupt handler function and sets
+*              : the interrupt priority level. Then enables transfer completion
+*              : interrupt.
+* Arguments    : dmac_transinfo_t * trans_info : Setting information to DMAC
+*              :                               : register
+*              : uint32_t dmamode      : DMA mode (only for DMAC_MODE_REGISTER)
+*              : uint32_t continuation : Set continuous transfer to be valid
+*              :                       : after DMA transfer has been completed
+*              :         DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+*              :         DMAC_SAMPLE_SINGLE       : Do not execute continuous
+*              :                                  : transfer
+*              : uint32_t request_factor : Factor for on-chip peripheral module
+*              :                         : request
+*              :         DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+*              :         DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+*              :         DMAC_REQ_TGI0A     : MTU2_0 input capture/compare match
+*              :                 :
+*              : uint32_t req_direction : Setting value of CHCFG_n register
+*              :                        : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+                              uint32_t request_factor, uint32_t req_direction)
+{
+    /* ==== Register mode ==== */
+    if (DMAC_MODE_REGISTER == dmamode)
+    {
+        /* ==== Next0 register set ==== */
+        DMAC4.N0SA_n = trans_info->src_addr;        /* Start address of transfer source      */
+        DMAC4.N0DA_n = trans_info->dst_addr;        /* Start address of transfer destination */
+        DMAC4.N0TB_n = trans_info->count;           /* Total transfer byte count             */
+
+        /* DAD : Transfer destination address counting direction */
+        /* SAD : Transfer source address counting direction      */
+        /* DDS : Transfer destination transfer size              */
+        /* SDS : Transfer source transfer size                   */
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            trans_info->daddr_dir,
+                            DMAC4_CHCFG_n_DAD_SHIFT,
+                            DMAC4_CHCFG_n_DAD);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            trans_info->saddr_dir,
+                            DMAC4_CHCFG_n_SAD_SHIFT,
+                            DMAC4_CHCFG_n_SAD);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            trans_info->dst_size,
+                            DMAC4_CHCFG_n_DDS_SHIFT,
+                            DMAC4_CHCFG_n_DDS);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            trans_info->src_size,
+                            DMAC4_CHCFG_n_SDS_SHIFT,
+                            DMAC4_CHCFG_n_SDS);
+
+        /* DMS  : Register mode                            */
+        /* RSEL : Select Next0 register set                */
+        /* SBE  : No discharge of buffer data when aborted */
+        /* DEM  : No DMA interrupt mask                    */
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_DMS_SHIFT,
+                            DMAC4_CHCFG_n_DMS);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_RSEL_SHIFT,
+                            DMAC4_CHCFG_n_RSEL);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_SBE_SHIFT,
+                            DMAC4_CHCFG_n_SBE);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_DEM_SHIFT,
+                            DMAC4_CHCFG_n_DEM);
+
+        /* ---- Continuous transfer ---- */
+        if (DMAC_SAMPLE_CONTINUATION == continuation)
+        {
+            /* REN : Execute continuous transfer                         */
+            /* RSW : Change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                1,
+                                DMAC4_CHCFG_n_REN_SHIFT,
+                                DMAC4_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                1,
+                                DMAC4_CHCFG_n_RSW_SHIFT,
+                                DMAC4_CHCFG_n_RSW);
+        }
+        /* ---- Single transfer ---- */
+        else
+        {
+            /* REN : Do not execute continuous transfer                         */
+            /* RSW : Do not change register set when DMA transfer is completed. */
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                0,
+                                DMAC4_CHCFG_n_REN_SHIFT,
+                                DMAC4_CHCFG_n_REN);
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                0,
+                                DMAC4_CHCFG_n_RSW_SHIFT,
+                                DMAC4_CHCFG_n_RSW);
+        }
+
+        /* TM  : Single transfer                          */
+        /* SEL : Channel setting                          */
+        /* HIEN, LOEN : On-chip peripheral module request */
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_TM_SHIFT,
+                            DMAC4_CHCFG_n_TM);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            4,
+                            DMAC4_CHCFG_n_SEL_SHIFT,
+                            DMAC4_CHCFG_n_SEL);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            1,
+                            DMAC4_CHCFG_n_HIEN_SHIFT,
+                            DMAC4_CHCFG_n_HIEN);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            0,
+                            DMAC4_CHCFG_n_LOEN_SHIFT,
+                            DMAC4_CHCFG_n_LOEN);
+
+        /* ---- Set factor by specified on-chip peripheral module request ---- */
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+                            DMAC4_CHCFG_n_AM_SHIFT,
+                            DMAC4_CHCFG_n_AM);
+        RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+                            DMAC4_CHCFG_n_LVL_SHIFT,
+                            DMAC4_CHCFG_n_LVL);
+        if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+        {
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+                                DMAC4_CHCFG_n_REQD_SHIFT,
+                                DMAC4_CHCFG_n_REQD);
+        }
+        else
+        {
+            RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+                                req_direction,
+                                DMAC4_CHCFG_n_REQD_SHIFT,
+                                DMAC4_CHCFG_n_REQD);
+        }
+        RZA_IO_RegWrite_32(&DMAC45.DMARS,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+                            DMAC45_DMARS_CH4_RID_SHIFT,
+                            DMAC45_DMARS_CH4_RID);
+        RZA_IO_RegWrite_32(&DMAC45.DMARS,
+                            usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+                            DMAC45_DMARS_CH4_MID_SHIFT,
+                            DMAC45_DMARS_CH4_MID);
+
+        /* PR : Round robin mode */
+        RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+                            1,
+                            DMAC07_DCTRL_0_7_PR_SHIFT,
+                            DMAC07_DCTRL_0_7_PR);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Open
+* Description  : Enables DMAC channel 4 transfer.
+* Arguments    : uint32_t req : DMAC request mode
+* Return Value :  0 : Succeeded in enabling DMA transfer
+*              : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_host_DMAC4_Open (uint32_t req)
+{
+    int32_t ret;
+    volatile uint8_t  dummy;
+
+    /* Transferable? */
+    if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+                                DMAC4_CHSTAT_n_EN_SHIFT,
+                                DMAC4_CHSTAT_n_EN)) &&
+        (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+                                DMAC4_CHSTAT_n_TACT_SHIFT,
+                                DMAC4_CHSTAT_n_TACT)))
+    {
+        /* Clear Channel Status Register */
+        RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+                            1,
+                            DMAC4_CHCTRL_n_SWRST_SHIFT,
+                            DMAC4_CHCTRL_n_SWRST);
+        dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
+                                DMAC4_CHCTRL_n_SWRST_SHIFT,
+                                DMAC4_CHCTRL_n_SWRST);
+        /* Enable DMA transfer */
+        RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+                            1,
+                            DMAC4_CHCTRL_n_SETEN_SHIFT,
+                            DMAC4_CHCTRL_n_SETEN);
+
+        /* ---- Request by software ---- */
+        if (DMAC_REQ_MODE_SOFT == req)
+        {
+            /* DMA transfer Request by software */
+            RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+                                1,
+                                DMAC4_CHCTRL_n_STG_SHIFT,
+                                DMAC4_CHCTRL_n_STG);
+        }
+
+        ret = 0;
+    }
+    else
+    {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Close
+* Description  : Aborts DMAC channel 4 transfer. Returns the remaining transfer
+*              : byte count at the time of DMA transfer abort to the argument
+*              : *remain.
+* Arguments    : uint32_t * remain : Remaining transfer byte count when
+*              :                   : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_Close (uint32_t * remain)
+{
+
+    /* ==== Abort transfer ==== */
+    RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+                        1,
+                        DMAC4_CHCTRL_n_CLREN_SHIFT,
+                        DMAC4_CHCTRL_n_CLREN);
+
+    while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+                                DMAC4_CHSTAT_n_TACT_SHIFT,
+                                DMAC4_CHSTAT_n_TACT))
+    {
+        /* Loop until transfer is aborted */
+    }
+
+    while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+                                DMAC4_CHSTAT_n_EN_SHIFT,
+                                DMAC4_CHSTAT_n_EN))
+    {
+        /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+    }
+    /* ==== Obtain remaining transfer byte count ==== */
+    *remain = DMAC4.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Load_Set
+* Description  : Sets the transfer source address, transfer destination
+*              : address, and total transfer byte count respectively
+*              : specified by the argument src_addr, dst_addr, and count to
+*              : DMAC channel 4 as DMA transfer information.
+*              : Sets the register set selected by the CHCFG_n register
+*              : RSEL bit from the Next0 or Next1 register set.
+*              : This function should be called when DMA transfer of DMAC
+*              : channel 4 is aboted.
+* Arguments    : uint32_t src_addr : Transfer source address
+*              : uint32_t dst_addr : Transfer destination address
+*              : uint32_t count    : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+    uint8_t reg_set;
+
+    /* Obtain register set in use */
+    reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+                                DMAC4_CHSTAT_n_SR_SHIFT,
+                                DMAC4_CHSTAT_n_SR);
+
+    /* ==== Load ==== */
+    if (0 == reg_set)
+    {
+        /* ---- Next0 Register Set ---- */
+        DMAC4.N0SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC4.N0DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC4.N0TB_n = count;       /* Total transfer byte count             */
+    }
+    else
+    {
+        /* ---- Next1 Register Set ---- */
+        DMAC4.N1SA_n = src_addr;    /* Start address of transfer source      */
+        DMAC4.N1DA_n = dst_addr;    /* Start address of transfer destination */
+        DMAC4.N1TB_n = count;       /* Total transfer byte count             */
+     }
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,778 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name    : usb1_host_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s)    : RZ/A1H
+* Tool-Chain   :
+* OS           : None
+* H/W Platform :
+* Description  : RZ/A1H R7S72100 USB Sample Program
+* Operation    :
+* Limitations  :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes   <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_host_api.h"
+#include "usb1_host.h"
+#include "VKRZA1H.h"            /* INTC Driver Header   */
+#include "usb1_host_dmacdrv.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb1_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb1_host_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_d0fifo_dmaintid
+* Description  : get D0FIFO DMA Interrupt ID
+* Arguments    : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+    return 0xFFFF;
+#else
+    return DMAINT1_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_d1fifo_dmaintid
+* Description  : get D1FIFO DMA Interrupt ID
+* Arguments    : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+    return 0xFFFF;
+#else
+    return DMAINT2_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_attach
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_attach (void)
+{
+//    printf("\n");
+//    printf("channel 1 attach device\n");
+//    printf("\n");
+    ohciwrapp_loc_Connect(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_detach
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_detach (void)
+{
+//    printf("\n");
+//    printf("channel 1 detach device\n");
+//    printf("\n");
+    ohciwrapp_loc_Connect(0);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_1ms
+* Description  : Wait for the software of 1ms.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_1ms (void)
+{
+    osDelay(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_xms
+* Description  : Wait for the software in the period of time specified by the
+*              : argument.
+*              : Alter this function according to the user's system.
+* Arguments    : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_xms (uint32_t msec)
+{
+    osDelay(msec);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_10us
+* Description  : Waits for software for the period specified by the argument.
+*              : Alter this function according to the user's system.
+* Arguments    : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_10us (uint32_t usec)
+{
+    volatile int i;
+
+    /* Wait 10us (Please change for your MCU) */
+    for (i = 0; i < usec; ++i)
+    {
+        Userdef_USB_usb1_host_delay_10us_2();
+    }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_10us_2
+* Description  : Waits for software for the period specified by the argument.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb1_host_delay_10us_2 (void)
+{
+    volatile int i;
+    volatile unsigned long tmp;
+
+    /* Wait 1us (Please change for your MCU) */
+    for (i = 0; i < 14; ++i)
+    {
+        tmp = DUMMY_ACCESS;
+    }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_500ns
+* Description  : Wait for software for 500ns.
+*              : Alter this function according to the user's system.
+* Arguments    : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_500ns (void)
+{
+    volatile int i;
+    volatile unsigned long tmp;
+
+    /* Wait 500ns (Please change for your MCU) */
+    /* Wait 500ns I clock 266MHz */
+    tmp = DUMMY_ACCESS;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_start_dma
+* Description  : Enables DMA transfer on the information specified by the argument.
+*              : Set DMAC register by this function to enable DMA transfer.
+*              : After executing this function, USB module is set to start DMA
+*              : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments    : USB_HOST_DMA_t *dma   : DMA parameter
+*              :  typedef struct{
+*              :      uint32_t fifo;    FIFO for using
+*              :      uint32_t buffer;  Start address of transfer source/destination
+*              :      uint32_t bytes;   Transfer size(Byte)
+*              :      uint32_t dir;     Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+*              :      uint32_t size;    DMA transfer size
+*              :   } USB_HOST_DMA_t;
+*              : uint16_t dfacc ; 0 : cycle steal mode
+*              :                  1 : 16byte continuous mode
+*              :                  2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc)
+{
+    uint32_t trncount;
+    uint32_t src;
+    uint32_t dst;
+    uint32_t size;
+    uint32_t dir;
+#ifdef CACHE_WRITEBACK
+    uint32_t ptr;
+#endif
+
+    trncount = dma->bytes;
+    dir      = dma->dir;
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        /* DxFIFO determination */
+        dst = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+        if (dma->fifo == USB_HOST_D0FIFO_DMA)
+        {
+            src = (uint32_t)(&USB201.D0FIFO.UINT32);
+        }
+        else
+        {
+            src = (uint32_t)(&USB201.D1FIFO.UINT32);
+        }
+        size = dma->size;
+
+        if (size == 0)
+        {
+            src += 3;       /* byte access  */
+        }
+        else if (size == 1)
+        {
+            src += 2;       /* short access */
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+#else
+        size = dma->size;
+
+        if (size == 2)
+        {
+            /* 32bit access */
+            if (dfacc == 2)
+            {
+                /* 32byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB201.D0FIFOB0);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB201.D1FIFOB0);
+                }
+            }
+            else if (dfacc == 1)
+            {
+                /* 16byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB201.D0FIFOB0);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB201.D1FIFOB0);
+                }
+            }
+            else
+            {
+                /* normal access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    src = (uint32_t)(&USB201.D0FIFO.UINT32);
+                }
+                else
+                {
+                    src = (uint32_t)(&USB201.D1FIFO.UINT32);
+                }
+            }
+        }
+        else if (size == 1)
+        {
+            /* 16bit access */
+            dfacc = 0;      /* force normal access */
+
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                src = (uint32_t)(&USB201.D0FIFO.UINT32);
+            }
+            else
+            {
+                src = (uint32_t)(&USB201.D1FIFO.UINT32);
+            }
+            src += 2;       /* short access */
+        }
+        else
+        {
+            /* 8bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                src = (uint32_t)(&USB201.D0FIFO.UINT32);
+            }
+            else
+            {
+                src = (uint32_t)(&USB201.D1FIFO.UINT32);
+            }
+            src += 3;       /* byte access  */
+        }
+#endif
+    }
+    else
+    {
+        /* DxFIFO determination */
+        src = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+        if (dma->fifo == USB_HOST_D0FIFO_DMA)
+        {
+            dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+        }
+        else
+        {
+            dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+        }
+        size = dma->size;
+
+        if (size == 0)
+        {
+            dst += 3;       /* byte access  */
+        }
+        else if (size == 1)
+        {
+            dst += 2;       /* short access */
+        }
+        else
+        {
+            /* Do Nothing */
+        }
+#else
+        size = dma->size;
+        if (size == 2)
+        {
+            /* 32bit access */
+            if (dfacc == 2)
+            {
+                /* 32byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB201.D0FIFOB0);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB201.D1FIFOB0);
+                }
+            }
+            else if (dfacc == 1)
+            {
+                /* 16byte access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB201.D0FIFOB0);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB201.D1FIFOB0);
+                }
+            }
+            else
+            {
+                /* normal access */
+                if (dma->fifo == USB_HOST_D0FIFO_DMA)
+                {
+                    dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+                }
+                else
+                {
+                    dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+                }
+            }
+        }
+        else if (size == 1)
+        {
+            /* 16bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+            }
+            else
+            {
+                dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+            }
+            dst += 2;       /* short access */
+        }
+        else
+        {
+            /* 8bit access */
+            dfacc = 0;      /* force normal access */
+            if (dma->fifo == USB_HOST_D0FIFO_DMA)
+            {
+                dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+            }
+            else
+            {
+                dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+            }
+            dst += 3;       /* byte access  */
+        }
+#endif
+    }
+
+#ifdef CACHE_WRITEBACK
+    ptr = (uint32_t)dma->buffer;
+    if ((ptr & 0x20000000ul) == 0)
+    {
+        io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount);
+    }
+#endif
+
+    if (dma->fifo == USB_HOST_D0FIFO_DMA)
+    {
+        usb1_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+    }
+    else
+    {
+        usb1_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+    }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_dmac0
+* Description  : Enables DMA transfer on the information specified by the argument.
+* Arguments    : uint32_t src   : src address
+*              : uint32_t dst   : dst address
+*              : uint32_t count : transfer byte
+*              : uint32_t size  : transfer size
+*              : uint32_t dir   : direction
+*              : uint32_t fifo  : FIFO(D0FIFO or D1FIFO)
+*              : uint16_t dfacc : 0 : normal access
+*              :                : 1 : 16byte access
+*              :                : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+    dmac_transinfo_t trans_info;
+    uint32_t         request_factor = 0;
+    int32_t          ret;
+
+    /* ==== Variable setting for DMAC initialization ==== */
+    trans_info.src_addr  = (uint32_t)src;               /* Start address of transfer source */
+    trans_info.dst_addr  = (uint32_t)dst;               /* Start address of transfer destination */
+    trans_info.count     = (uint32_t)count;             /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    if (size == 0)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_8;        /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_8;        /* Transfer destination transfer size */
+    }
+    else if (size == 1)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_16;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_16;       /* Transfer destination transfer size */
+    }
+    else if (size == 2)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_32;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_32;       /* Transfer destination transfer size */
+    }
+    else
+    {
+//        printf("size error!!\n");
+    }
+#else
+    if (dfacc == 2)
+    {
+        /* 32byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_256;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_256;      /* Transfer destination transfer size */
+    }
+    else if (dfacc == 1)
+    {
+        /* 16byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_128;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_128;      /* Transfer destination transfer size */
+    }
+    else
+    {
+        /* normal access */
+        if (size == 0)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_8;    /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_8;    /* Transfer destination transfer size */
+        }
+        else if (size == 1)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_16;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_16;   /* Transfer destination transfer size */
+        }
+        else if (size == 2)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_32;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_32;   /* Transfer destination transfer size */
+        }
+        else
+        {
+//            printf("size error!!\n");
+        }
+    }
+#endif
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        request_factor       = DMAC_REQ_USB1_DMA0_RX;   /* USB_0 channel 0 receive FIFO full */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer destination address */
+    }
+    else if (dir == USB_HOST_BUF2FIFO)
+    {
+        request_factor       = DMAC_REQ_USB1_DMA0_TX;   /* USB_0 channel 0 receive FIFO empty */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer destination address */
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* ==== DMAC initialization ==== */
+    usb1_host_DMAC3_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+                                    DMAC_MODE_REGISTER,
+                                    DMAC_SAMPLE_SINGLE,
+                                    request_factor,
+                                    0);     /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC3_PeriReqInit() */
+
+    /* ==== DMAC startup ==== */
+    ret = usb1_host_DMAC3_Open(DMAC_REQ_MODE_PERI);
+
+    if (ret != 0)
+    {
+//        printf("DMAC3 Open error!!\n");
+    }
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_dmac1
+* Description  : Enables DMA transfer on the information specified by the argument.
+* Arguments    : uint32_t src   : src address
+*              : uint32_t dst   : dst address
+*              : uint32_t count : transfer byte
+*              : uint32_t size  : transfer size
+*              : uint32_t dir   : direction
+*              : uint32_t fifo  : FIFO(D0FIFO or D1FIFO)
+*              : uint16_t dfacc : 0 : normal access
+*              :                : 1 : 16byte access
+*              :                : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+                             uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+    dmac_transinfo_t trans_info;
+    uint32_t request_factor = 0;
+    int32_t  ret;
+
+    /* ==== Variable setting for DMAC initialization ==== */
+    trans_info.src_addr  = (uint32_t)src;               /* Start address of transfer source */
+    trans_info.dst_addr  = (uint32_t)dst;               /* Start address of transfer destination */
+    trans_info.count     = (uint32_t)count;             /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+    if (size == 0)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_8;        /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_8;        /* Transfer destination transfer size */
+    }
+    else if (size == 1)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_16;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_16;       /* Transfer destination transfer size */
+    }
+    else if (size == 2)
+    {
+        trans_info.src_size = DMAC_TRANS_SIZE_32;       /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_32;       /* Transfer destination transfer size */
+    }
+    else
+    {
+//        printf("size error!!\n");
+    }
+#else
+    if (dfacc == 2)
+    {
+        /* 32byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_256;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_256;      /* Transfer destination transfer size */
+    }
+    else if (dfacc == 1)
+    {
+        /* 16byte access */
+        trans_info.src_size = DMAC_TRANS_SIZE_128;      /* Transfer source transfer size */
+        trans_info.dst_size = DMAC_TRANS_SIZE_128;      /* Transfer destination transfer size */
+    }
+    else
+    {
+        /* normal access */
+        if (size == 0)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_8;    /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_8;    /* Transfer destination transfer size */
+        }
+        else if (size == 1)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_16;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_16;   /* Transfer destination transfer size */
+        }
+        else if (size == 2)
+        {
+            trans_info.src_size = DMAC_TRANS_SIZE_32;   /* Transfer source transfer size */
+            trans_info.dst_size = DMAC_TRANS_SIZE_32;   /* Transfer destination transfer size */
+        }
+        else
+        {
+//            printf("size error!!\n");
+        }
+    }
+#endif
+
+    if (dir == USB_HOST_FIFO2BUF)
+    {
+        request_factor =DMAC_REQ_USB1_DMA1_RX;          /* USB_0 channel 0 receive FIFO full */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer destination address */
+    }
+    else if (dir == USB_HOST_BUF2FIFO)
+    {
+        request_factor =DMAC_REQ_USB1_DMA1_TX;          /* USB_0 channel 0 receive FIFO empty */
+        trans_info.saddr_dir = DMAC_TRANS_ADR_INC;      /* Count direction of transfer source address */
+        trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC;   /* Count direction of transfer destination address */
+    }
+    else
+    {
+        /* Do Nothing */
+    }
+
+    /* ==== DMAC initialization ==== */
+    usb1_host_DMAC4_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+                                    DMAC_MODE_REGISTER,
+                                    DMAC_SAMPLE_SINGLE,
+                                    request_factor,
+                                    0);     /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC4_PeriReqInit() */
+
+    /* ==== DMAC startup ==== */
+    ret = usb1_host_DMAC4_Open(DMAC_REQ_MODE_PERI);
+
+    if (ret != 0)
+    {
+//        printf("DMAC4 Open error!!\n");
+    }
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_stop_dma0
+* Description  : Disables DMA transfer.
+* Arguments    : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+*              : regarding to the bus width.
+* Notice       : This function should be executed to DMAC executed at the time
+*              : of specification of D0_FIF0_DMA in dma->fifo.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_host_stop_dma0 (void)
+{
+    uint32_t remain;
+
+    /* ==== DMAC release ==== */
+    usb1_host_DMAC3_Close(&remain);
+
+    return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_stop_dma1
+* Description  : Disables DMA transfer.
+*              : This function should be executed to DMAC executed at the time
+*              : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments    : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+*              : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_host_stop_dma1 (void)
+{
+    uint32_t remain;
+
+    /* ==== DMAC release ==== */
+    usb1_host_DMAC4_Close(&remain);
+
+    return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_notice
+* Description  : Notice of USER
+* Arguments    : const char *format
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_notice (const char * format)
+{
+//    printf(format);
+
+    return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_user_rdy
+* Description  : This function notify a user and wait for trigger
+* Arguments    : const char *format
+*              :    uint16_t data
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_user_rdy (const char * format, uint16_t data)
+{
+//    printf(format, data);
+    getchar();
+
+    return;
+}
+
+/* End of File */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/TARGET_RENESAS/TARGET_VK_RZ_A1H/usb_host_setting.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,100 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef USB_HOST_SETTING_H
+#define USB_HOST_SETTING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USB_HOST_CH                           0
+#define USB_HOST_HISPEED                      1
+
+#define INT_TRANS_MAX_NUM                     4    /* min:1 max:4 */
+#define ISO_TRANS_MAX_NUM                     2    /* min:0 max:2 */
+
+#if (USB_HOST_CH == 0)
+#include "usb0_host.h"
+#define USB20X                                USB200
+#define USBIXUSBIX                            USBI0_IRQn
+#define g_usbx_host_SupportUsbDeviceSpeed     g_usb0_host_SupportUsbDeviceSpeed
+#define g_usbx_host_UsbDeviceSpeed            g_usb0_host_UsbDeviceSpeed
+#define g_usbx_host_CmdStage                  g_usb0_host_CmdStage
+#define g_usbx_host_pipe_status               g_usb0_host_pipe_status
+#define g_usbx_host_data_pointer              g_usb0_host_data_pointer
+#define g_usbx_host_data_count                g_usb0_host_data_count
+#define usbx_api_host_init                    usb0_api_host_init
+#define usbx_host_UsbBusReset                 usb0_host_UsbBusReset
+#define usbx_host_get_devadd                  usb0_host_get_devadd
+#define usbx_host_set_devadd                  usb0_host_set_devadd
+#define usbx_host_SetupStage                  usb0_host_SetupStage
+#define usbx_host_CtrlWriteStart              usb0_host_CtrlWriteStart
+#define usbx_host_CtrlReadStart               usb0_host_CtrlReadStart
+#define usbx_api_host_SetEndpointTable        usb0_api_host_SetEndpointTable
+#define usbx_host_start_send_transfer         usb0_host_start_send_transfer
+#define usbx_host_start_receive_transfer      usb0_host_start_receive_transfer
+#define usbx_host_stop_transfer               usb0_host_stop_transfer
+#define usbx_host_set_sqclr                   usb0_host_set_sqclr
+#define usbx_host_set_sqset                   usb0_host_set_sqset
+#define usbx_host_CheckAttach                 usb0_host_CheckAttach
+#define usbx_host_UsbDetach                   usb0_host_UsbDetach
+#define usbx_host_UsbAttach                   usb0_host_UsbAttach
+#define usbx_host_init_pipe_status            usb0_host_init_pipe_status
+#define usbx_host_get_sqmon                   usb0_host_get_sqmon
+#else
+#include "usb1_host.h"
+#define USB20X                                USB201
+#define USBIXUSBIX                            USBI1_IRQn
+#define g_usbx_host_SupportUsbDeviceSpeed     g_usb1_host_SupportUsbDeviceSpeed
+#define g_usbx_host_UsbDeviceSpeed            g_usb1_host_UsbDeviceSpeed
+#define g_usbx_host_CmdStage                  g_usb1_host_CmdStage
+#define g_usbx_host_pipe_status               g_usb1_host_pipe_status
+#define g_usbx_host_data_pointer              g_usb1_host_data_pointer
+#define g_usbx_host_data_count                g_usb1_host_data_count
+#define usbx_api_host_init                    usb1_api_host_init
+#define usbx_host_UsbBusReset                 usb1_host_UsbBusReset
+#define usbx_host_get_devadd                  usb1_host_get_devadd
+#define usbx_host_set_devadd                  usb1_host_set_devadd
+#define usbx_host_SetupStage                  usb1_host_SetupStage
+#define usbx_host_CtrlWriteStart              usb1_host_CtrlWriteStart
+#define usbx_host_CtrlReadStart               usb1_host_CtrlReadStart
+#define usbx_api_host_SetEndpointTable        usb1_api_host_SetEndpointTable
+#define usbx_host_start_send_transfer         usb1_host_start_send_transfer
+#define usbx_host_start_receive_transfer      usb1_host_start_receive_transfer
+#define usbx_host_stop_transfer               usb1_host_stop_transfer
+#define usbx_host_set_sqclr                   usb1_host_set_sqclr
+#define usbx_host_set_sqset                   usb1_host_set_sqset
+#define usbx_host_CheckAttach                 usb1_host_CheckAttach
+#define usbx_host_UsbDetach                   usb1_host_UsbDetach
+#define usbx_host_UsbAttach                   usb1_host_UsbAttach
+#define usbx_host_init_pipe_status            usb1_host_init_pipe_status
+#define usbx_host_get_sqmon                   usb1_host_get_sqmon
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* USB_HOST_SETTING_H */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/USBDeviceConnected.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,124 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBDeviceConnected.h"
+#include "dbg.h"
+
+USBDeviceConnected::USBDeviceConnected() {
+    init();
+}
+
+void USBDeviceConnected::init() {
+    hub_nb = 0;
+    port = 0;
+    vid = 0;
+    pid = 0;
+    nb_interf = 0;
+    enumerated = false;
+    activeAddr = false;
+    sizeControlEndpoint = 8;
+    device_class = 0;
+    device_subclass = 0;
+    proto = 0;
+    speed = false;
+    for (int i = 0; i < MAX_INTF; i++) {
+        memset((void *)&intf[i], 0, sizeof(INTERFACE));
+        intf[i].in_use = false;
+        for (int j = 0; j < MAX_ENDPOINT_PER_INTERFACE; j++) {
+            intf[i].ep[j] = NULL;
+            strcpy(intf[i].name, "Unknown");
+        }
+    }
+    hub_parent = NULL;
+    hub = NULL;
+    nb_interf = 0;
+}
+
+INTERFACE * USBDeviceConnected::getInterface(uint8_t index) {
+    if (index >= MAX_INTF)
+        return NULL;
+
+    if (intf[index].in_use)
+        return &intf[index];
+
+    return NULL;
+}
+
+bool USBDeviceConnected::addInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) {
+    if ((intf_nb >= MAX_INTF) || (intf[intf_nb].in_use)) {
+        return false;
+    }
+    intf[intf_nb].in_use = true;
+    intf[intf_nb].intf_class = intf_class;
+    intf[intf_nb].intf_subclass = intf_subclass;
+    intf[intf_nb].intf_protocol = intf_protocol;
+    intf[intf_nb].nb_endpoint = 0;
+    return true;
+}
+
+bool USBDeviceConnected::addEndpoint(uint8_t intf_nb, USBEndpoint * ept) {
+    if ((intf_nb >= MAX_INTF) || (intf[intf_nb].in_use == false) || (intf[intf_nb].nb_endpoint >= MAX_ENDPOINT_PER_INTERFACE)) {
+        return false;
+    }
+    intf[intf_nb].nb_endpoint++;
+
+    for (int i = 0; i < MAX_ENDPOINT_PER_INTERFACE; i++) {
+        if (intf[intf_nb].ep[i] == NULL) {
+            intf[intf_nb].ep[i] = ept;
+            return true;
+        }
+    }
+    return false;
+}
+
+void USBDeviceConnected::init(uint8_t hub_, uint8_t port_, bool lowSpeed_) {
+    USB_DBG("init dev: %p", this);
+    init();
+    hub_nb = hub_;
+    port = port_;
+    speed = lowSpeed_;
+}
+
+void USBDeviceConnected::disconnect() {
+    for(int i = 0; i < MAX_INTF; i++) {
+        intf[i].detach.call();
+    }
+    init();
+}
+
+
+USBEndpoint * USBDeviceConnected::getEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint8_t index) {
+    if (intf_nb >= MAX_INTF) {
+        return NULL;
+    }
+    for (int i = 0; i < MAX_ENDPOINT_PER_INTERFACE; i++) {
+        if ((intf[intf_nb].ep[i]->getType() == type) && (intf[intf_nb].ep[i]->getDir() == dir)) {
+            if(index) {
+                index--;
+            } else {
+                return intf[intf_nb].ep[i];
+            }
+        }
+    }
+    return NULL;
+}
+
+USBEndpoint * USBDeviceConnected::getEndpoint(uint8_t intf_nb, uint8_t index) {
+    if ((intf_nb >= MAX_INTF) || (index >= MAX_ENDPOINT_PER_INTERFACE)) {
+        return NULL;
+    }
+    return intf[intf_nb].ep[index];
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/USBDeviceConnected.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,185 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBDEVICECONNECTED_H
+#define USBDEVICECONNECTED_H
+
+#include "stdint.h"
+#include "USBEndpoint.h"
+#include "USBHostConf.h"
+#include "rtos.h"
+
+class USBHostHub;
+
+typedef struct {
+    bool in_use;
+    uint8_t nb_endpoint;
+    uint8_t intf_class;
+    uint8_t intf_subclass;
+    uint8_t intf_protocol;
+    USBEndpoint * ep[MAX_ENDPOINT_PER_INTERFACE];
+    FunctionPointer detach;
+    char name[10];
+} INTERFACE;
+
+/**
+* USBDeviceConnected class
+*/
+class USBDeviceConnected
+{
+public:
+
+    /**
+    * Constructor
+    */
+    USBDeviceConnected();
+
+    /**
+    * Attach an USBEndpoint to this device
+    *
+    * @param intf_nb interface number
+    * @param ep pointeur on the USBEndpoint which will be attached
+    * @returns true if successful, false otherwise
+    */
+    bool addEndpoint(uint8_t intf_nb, USBEndpoint * ep);
+
+    /**
+    * Retrieve an USBEndpoint by its TYPE and DIRECTION
+    *
+    * @param intf_nb the interface on which to lookup the USBEndpoint
+    * @param type type of the USBEndpoint looked for
+    * @param dir direction of the USBEndpoint looked for
+    * @param index the index of the USBEndpoint whitin the interface
+    * @returns pointer on the USBEndpoint if found, NULL otherwise
+    */
+    USBEndpoint * getEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint8_t index = 0);
+
+    /**
+    * Retrieve an USBEndpoint by its index
+    *
+    * @param intf_nb interface number
+    * @param index index of the USBEndpoint
+    * @returns pointer on the USBEndpoint if found, NULL otherwise
+    */
+    USBEndpoint * getEndpoint(uint8_t intf_nb, uint8_t index);
+
+    /**
+    * Add a new interface to this device
+    *
+    * @param intf_nb interface number
+    * @param intf_class interface class
+    * @param intf_subclass interface subclass
+    * @param intf_protocol interface protocol
+    * @returns true if successful, false otherwise
+    */
+    bool addInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol);
+
+    /**
+    * Get a specific interface
+    *
+    * @param index index of the interface to be fetched
+    * @returns interface
+    */
+    INTERFACE * getInterface(uint8_t index);
+
+    /**
+     *  Attach a member function to call when a the device has been disconnected
+     *
+     *  @param intf_nb interface number
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     */
+    template<typename T>
+    inline void onDisconnect(uint8_t intf_nb, T* tptr, void (T::*mptr)(void)) {
+        if ((mptr != NULL) && (tptr != NULL)) {
+            intf[intf_nb].detach.attach(tptr, mptr);
+        }
+    }
+
+    /**
+     * Attach a callback called when the device has been disconnected
+     *
+     *  @param intf_nb interface number
+     *  @param fn function pointer
+     */
+    inline void onDisconnect(uint8_t intf_nb, void (*fn)(void)) {
+        if (fn != NULL) {
+            intf[intf_nb].detach.attach(fn);
+        }
+    }
+
+    /**
+    * Disconnect the device by calling a callback function registered by a driver
+    */
+    void disconnect();
+
+    // setters
+    void init(uint8_t hub, uint8_t port, bool lowSpeed);
+    inline void setAddress(uint8_t addr_) { addr = addr_; };
+    inline void setVid(uint16_t vid_) { vid = vid_; };
+    inline void setPid(uint16_t pid_) { pid = pid_; };
+    inline void setClass(uint8_t device_class_) { device_class = device_class_; };
+    inline void setSubClass(uint8_t device_subclass_) { device_subclass = device_subclass_; };
+    inline void setProtocol(uint8_t pr) { proto = pr; };
+    inline void setSizeControlEndpoint(uint32_t size) { sizeControlEndpoint = size; };
+    inline void activeAddress(bool active) { activeAddr = active; };
+    inline void setEnumerated() { enumerated = true; };
+    inline void setNbIntf(uint8_t nb_intf) {nb_interf = nb_intf; };
+    inline void setHubParent(USBHostHub * hub) { hub_parent = hub; };
+    inline void setName(const char * name_, uint8_t intf_nb) { strcpy(intf[intf_nb].name, name_); };
+
+    //getters
+    inline uint8_t     getPort() { return port; };
+    inline uint8_t     getHub() { return hub_nb; };
+    inline uint8_t     getAddress() { return addr; };
+    inline uint16_t    getVid() { return vid; };
+    inline uint16_t    getPid() { return pid; };
+    inline uint8_t     getClass() { return device_class; };
+    inline uint8_t     getSubClass() { return device_subclass; };
+    inline uint8_t     getProtocol() { return proto; };
+    inline bool        getSpeed() { return speed; };
+    inline uint32_t    getSizeControlEndpoint() { return sizeControlEndpoint; };
+    inline bool        isActiveAddress() { return activeAddr; };
+    inline bool        isEnumerated() { return enumerated; };
+    inline USBHostHub * getHubParent() { return hub_parent; };
+    inline uint8_t      getNbIntf() { return nb_interf; };
+    inline const char * getName(uint8_t intf_nb) { return intf[intf_nb].name; };
+
+    // in case this device is a hub
+    USBHostHub * hub;
+
+private:
+    USBHostHub * hub_parent;
+
+    INTERFACE intf[MAX_INTF];
+    uint32_t sizeControlEndpoint;
+    uint8_t hub_nb;
+    uint8_t port;
+    uint16_t vid;
+    uint16_t pid;
+    uint8_t addr;
+    uint8_t device_class;
+    uint8_t device_subclass;
+    uint8_t proto;
+    bool speed;
+    volatile bool activeAddr;
+    volatile bool enumerated;
+    uint8_t nb_interf;
+
+    void init();
+};
+
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/USBEndpoint.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,162 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "dbg.h"
+#include "USBEndpoint.h"
+
+void USBEndpoint::init(HCED * hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir_, uint32_t size, uint8_t ep_number, HCTD* td_list_[2])
+{
+    hced = hced_;
+    type = type_;
+    dir = dir_;
+    setup = (type == CONTROL_ENDPOINT) ? true : false;
+
+    //TDs have been allocated by the host
+    memcpy((HCTD**)td_list, td_list_, sizeof(HCTD*)*2); //TODO: Maybe should add a param for td_list size... at least a define
+    memset(td_list_[0], 0, sizeof(HCTD));
+    memset(td_list_[1], 0, sizeof(HCTD));
+
+    td_list[0]->ep = this;
+    td_list[1]->ep = this;
+
+    hced->control = 0;
+    //Empty queue
+    hced->tailTD = td_list[0];
+    hced->headTD = td_list[0];
+    hced->nextED = 0;
+
+    address = (ep_number & 0x7F) | ((dir - 1) << 7);
+
+    hced->control = ((ep_number & 0x7F) << 7)                         // Endpoint address
+                    | (type != CONTROL_ENDPOINT ? ( dir << 11) : 0 )  // direction : Out = 1, 2 = In
+                    | ((size & 0x3ff) << 16);                         // MaxPkt Size
+
+    transfer_len = 0;
+    transferred = 0;
+    buf_start = 0;
+    nextEp = NULL;
+
+    td_current = td_list[0];
+    td_next = td_list[1];
+
+    intf_nb = 0;
+
+    state = USB_TYPE_IDLE;
+}
+
+void USBEndpoint::setSize(uint32_t size)
+{
+    hced->control &= ~(0x3ff << 16);
+    hced->control |= (size << 16);
+}
+
+
+void USBEndpoint::setDeviceAddress(uint8_t addr)
+{
+    hced->control &= ~(0x7f);
+    hced->control |= (addr & 0x7F);
+}
+
+void USBEndpoint::setSpeed(uint8_t speed)
+{
+    hced->control &= ~(1 << 13);
+    hced->control |= (speed << 13);
+}
+
+//Only for control Eps
+void USBEndpoint::setNextToken(uint32_t token)
+{
+    switch (token) {
+        case TD_SETUP:
+            dir = OUT;
+            setup = true;
+            break;
+        case TD_IN:
+            dir = IN;
+            setup = false;
+            break;
+        case TD_OUT:
+            dir = OUT;
+            setup = false;
+            break;
+    }
+}
+
+struct {
+    USB_TYPE type;
+    const char * str;
+} static type_string[] = {
+/*0*/   {USB_TYPE_OK, "USB_TYPE_OK"},
+        {USB_TYPE_CRC_ERROR, "USB_TYPE_CRC_ERROR"},
+        {USB_TYPE_BIT_STUFFING_ERROR, "USB_TYPE_BIT_STUFFING_ERROR"},
+        {USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR, "USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR"},
+        {USB_TYPE_STALL_ERROR, "USB_TYPE_STALL_ERROR"},
+/*5*/   {USB_TYPE_DEVICE_NOT_RESPONDING_ERROR, "USB_TYPE_DEVICE_NOT_RESPONDING_ERROR"},
+        {USB_TYPE_PID_CHECK_FAILURE_ERROR, "USB_TYPE_PID_CHECK_FAILURE_ERROR"},
+        {USB_TYPE_UNEXPECTED_PID_ERROR, "USB_TYPE_UNEXPECTED_PID_ERROR"},
+        {USB_TYPE_DATA_OVERRUN_ERROR, "USB_TYPE_DATA_OVERRUN_ERROR"},
+        {USB_TYPE_DATA_UNDERRUN_ERROR, "USB_TYPE_DATA_UNDERRUN_ERROR"},
+/*10*/  {USB_TYPE_ERROR, "USB_TYPE_ERROR"},
+        {USB_TYPE_ERROR, "USB_TYPE_ERROR"},
+        {USB_TYPE_BUFFER_OVERRUN_ERROR, "USB_TYPE_BUFFER_OVERRUN_ERROR"},
+        {USB_TYPE_BUFFER_UNDERRUN_ERROR, "USB_TYPE_BUFFER_UNDERRUN_ERROR"},
+        {USB_TYPE_DISCONNECTED, "USB_TYPE_DISCONNECTED"},
+/*15*/  {USB_TYPE_FREE, "USB_TYPE_FREE"},
+        {USB_TYPE_IDLE, "USB_TYPE_IDLE"},
+        {USB_TYPE_PROCESSING, "USB_TYPE_PROCESSING"},
+        {USB_TYPE_ERROR, "USB_TYPE_ERROR"}
+};
+
+void USBEndpoint::setState(uint8_t st) {
+    if (st > 18)
+        return;
+    state = type_string[st].type;
+}
+
+
+const char * USBEndpoint::getStateString() {
+    return type_string[state].str;
+}
+
+void USBEndpoint::queueTransfer()
+{
+    transfer_len = (uint32_t)td_current->bufEnd - (uint32_t)td_current->currBufPtr + 1;
+    transferred = transfer_len;
+    buf_start = (uint8_t *)td_current->currBufPtr;
+
+    //Now add this free TD at this end of the queue
+    state = USB_TYPE_PROCESSING;
+    td_current->nextTD = (hcTd*)td_next;
+    hced->tailTD = td_next;
+}
+
+void USBEndpoint::unqueueTransfer(volatile HCTD * td)
+{
+    td->control=0;
+    td->currBufPtr=0;
+    td->bufEnd=0;
+    td->nextTD=0;
+    hced->headTD = (HCTD *)((uint32_t)hced->tailTD | ((uint32_t)hced->headTD & 0x2)); //Carry bit
+    td_current = td_next;
+    td_next = td;
+}
+
+void USBEndpoint::queueEndpoint(USBEndpoint * ed)
+{
+    nextEp = ed;
+    hced->nextED = (ed == NULL) ? 0 : (hcEd*)(ed->getHCED());
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/USBEndpoint.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,171 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBENDPOINT_H
+#define USBENDPOINT_H
+
+#include "FunctionPointer.h"
+#include "USBHostTypes.h"
+#include "rtos.h"
+
+class USBDeviceConnected;
+
+/**
+* USBEndpoint class
+*/
+class USBEndpoint
+{
+public:
+    /**
+    * Constructor
+    */
+    USBEndpoint() {
+        state = USB_TYPE_FREE;
+        nextEp = NULL;
+    };
+
+    /**
+    * Initialize an endpoint
+    *
+    * @param hced hced associated to the endpoint
+    * @param type endpoint type
+    * @param dir endpoint direction
+    * @param size endpoint size
+    * @param ep_number endpoint number
+    * @param td_list array of two allocated transfer descriptors
+    */
+    void init(HCED * hced, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t ep_number, HCTD* td_list[2]);
+
+    /**
+    * Set next token. Warning: only useful for the control endpoint
+    *
+    * @param token IN, OUT or SETUP token
+    */
+    void setNextToken(uint32_t token);
+
+    /**
+    * Queue an endpoint
+    *
+    * @param endpoint endpoint which will be queued in the linked list
+    */
+    void queueEndpoint(USBEndpoint * endpoint);
+
+
+    /**
+    * Queue a transfer on the endpoint
+    */
+    void queueTransfer();
+
+    /**
+    * Unqueue a transfer from the endpoint
+    *
+    * @param td hctd which will be unqueued
+    */
+    void unqueueTransfer(volatile HCTD * td);
+
+    /**
+     *  Attach a member function to call when a transfer is finished
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     */
+    template<typename T>
+    inline void attach(T* tptr, void (T::*mptr)(void)) {
+        if((mptr != NULL) && (tptr != NULL)) {
+            rx.attach(tptr, mptr);
+        }
+    }
+
+    /**
+     * Attach a callback called when a transfer is finished
+     *
+     * @param fptr function pointer
+     */
+    inline void attach(void (*fptr)(void)) {
+        if(fptr != NULL) {
+            rx.attach(fptr);
+        }
+    }
+
+    /**
+    * Call the handler associted to the end of a transfer
+    */
+    inline void call() {
+        rx.call();
+    };
+
+
+    // setters
+    inline void setState(USB_TYPE st) { state = st; }
+    void setState(uint8_t st);
+    void setDeviceAddress(uint8_t addr);
+    inline void setLengthTransferred(int len) { transferred = len; };
+    void setSpeed(uint8_t speed);
+    void setSize(uint32_t size);
+    inline void setDir(ENDPOINT_DIRECTION d) { dir = d; }
+    inline void setIntfNb(uint8_t intf_nb_) { intf_nb = intf_nb_; };
+
+    // getters
+    const char *                getStateString();
+    inline USB_TYPE             getState() { return state; }
+    inline ENDPOINT_TYPE        getType() { return type; };
+    inline uint8_t              getDeviceAddress() { return hced->control & 0x7f; };
+    inline int                  getLengthTransferred() { return transferred; }
+    inline uint8_t *            getBufStart() { return buf_start; }
+    inline uint8_t              getAddress(){ return address; };
+    inline uint32_t             getSize() { return (hced->control >> 16) & 0x3ff; };
+    inline volatile HCTD *      getHeadTD() { return (volatile HCTD*) ((uint32_t)hced->headTD & ~0xF); };
+    inline volatile HCTD**      getTDList() { return td_list; };
+    inline volatile HCED *      getHCED() { return hced; };
+    inline ENDPOINT_DIRECTION   getDir() { return dir; }
+    inline volatile HCTD *      getProcessedTD() { return td_current; };
+    inline volatile HCTD*       getNextTD() { return td_current; };
+    inline bool                 isSetup() { return setup; }
+    inline USBEndpoint *        nextEndpoint() { return (USBEndpoint*)nextEp; };
+    inline uint8_t              getIntfNb() { return intf_nb; };
+
+    USBDeviceConnected * dev;
+
+    Queue<uint8_t, 1> ep_queue;
+
+private:
+    ENDPOINT_TYPE type;
+    volatile USB_TYPE state;
+    ENDPOINT_DIRECTION dir;
+    bool setup;
+
+    uint8_t address;
+
+    int transfer_len;
+    int transferred;
+    uint8_t * buf_start;
+
+    FunctionPointer rx;
+
+    USBEndpoint* nextEp;
+
+    // USBEndpoint descriptor
+    volatile HCED * hced;
+
+    volatile HCTD * td_list[2];
+    volatile HCTD * td_current;
+    volatile HCTD * td_next;
+
+    uint8_t intf_nb;
+
+};
+
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/USBHALHost.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,172 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHALHOST_H
+#define USBHALHOST_H
+
+#include "USBHostTypes.h"
+#include "USBHostConf.h"
+
+class USBHostHub;
+
+/**
+* USBHALHost class
+*/
+class USBHALHost {
+protected:
+
+    /**
+    * Constructor
+    * init variables and memory where will be stored HCCA, ED and TD
+    */
+    USBHALHost();
+
+    /**
+    * Initialize host controller. Enable USB interrupts. This part is not in the constructor because,
+    * this function calls a virtual method if a device is already connected
+    */
+    void init();
+
+    /**
+    * reset the root hub
+    */
+    void resetRootHub();
+
+    /**
+    * return the value contained in the control HEAD ED register
+    *
+    * @returns address of the control Head ED
+    */
+    uint32_t controlHeadED();
+
+    /**
+    * return the value contained in the bulk HEAD ED register
+    *
+    * @returns address of the bulk head ED
+    */
+    uint32_t bulkHeadED();
+
+    /**
+    * return the value of the head interrupt ED contained in the HCCA
+    *
+    * @returns address of the head interrupt ED contained in the HCCA
+    */
+    uint32_t interruptHeadED();
+
+    /**
+    * Update the head ED for control transfers
+    */
+    void updateControlHeadED(uint32_t addr);
+
+    /**
+    * Update the head ED for bulk transfers
+    */
+    void updateBulkHeadED(uint32_t addr);
+
+    /**
+    * Update the head ED for interrupt transfers
+    */
+    void updateInterruptHeadED(uint32_t addr);
+
+    /**
+    * Enable List for the specified endpoint type
+    *
+    * @param type enable the list of ENDPOINT_TYPE type
+    */
+    void enableList(ENDPOINT_TYPE type);
+
+    /**
+    * Disable List for the specified endpoint type
+    *
+    * @param type disable the list of ENDPOINT_TYPE type
+    */
+    bool disableList(ENDPOINT_TYPE type);
+
+    /**
+    * Virtual method called when a device has been connected
+    *
+    * @param hub hub number of the device
+    * @param port port number of the device
+    * @param lowSpeed 1 if low speed, 0 otherwise
+    * @param hub_parent reference to the hub where the device is connected (NULL if the hub parent is the root hub)
+    */
+    virtual void deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent = NULL) = 0;
+
+    /**
+    * Virtual method called when a device has been disconnected
+    *
+    * @param hub hub number of the device
+    * @param port port number of the device
+    * @param hub_parent reference to the hub where the device is connected (NULL if the hub parent is the root hub)
+    * @param addr list of the TDs which have been completed to dequeue freed TDs
+    */
+    virtual void deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr) = 0;
+
+    /**
+    * Virtual method called when a transfer has been completed
+    *
+    * @param addr list of the TDs which have been completed
+    */
+    virtual void transferCompleted(volatile uint32_t addr) = 0;
+
+    /**
+    * Find a memory section for a new ED
+    *
+    * @returns the address of the new ED
+    */
+    volatile uint8_t * getED();
+
+    /**
+    * Find a memory section for a new TD
+    *
+    * @returns the address of the new TD
+    */
+    volatile uint8_t * getTD();
+#if(1) /* Isochronous */
+    bool isTD(volatile uint8_t* td);
+#endif
+
+    /**
+    * Release a previous memory section reserved for an ED
+    *
+    * @param ed address of the ED
+    */
+    void freeED(volatile uint8_t * ed);
+
+    /**
+    * Release a previous memory section reserved for an TD
+    *
+    * @param td address of the TD
+    */
+    void freeTD(volatile uint8_t * td);
+
+private:
+    static void _usbisr(void);
+    void UsbIrqhandler();
+
+    void memInit();
+
+    HCCA volatile * usb_hcca;           //256 bytes aligned
+    uint8_t volatile  * usb_edBuf;      //4 bytes aligned
+    uint8_t volatile  * usb_tdBuf;      //4 bytes aligned
+
+    static USBHALHost * instHost;
+
+    bool volatile  edBufAlloc[MAX_ENDPOINT];
+    bool volatile tdBufAlloc[MAX_TD];
+};
+
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/USBHALHost_LPC17.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,333 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_LPC1768) || defined(TARGET_LPC2460)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+
+// bits of the USB/OTG clock control register
+#define HOST_CLK_EN     (1<<0)
+#define DEV_CLK_EN      (1<<1)
+#define PORTSEL_CLK_EN  (1<<3)
+#define AHB_CLK_EN      (1<<4)
+
+// bits of the USB/OTG clock status register
+#define HOST_CLK_ON     (1<<0)
+#define DEV_CLK_ON      (1<<1)
+#define PORTSEL_CLK_ON  (1<<3)
+#define AHB_CLK_ON      (1<<4)
+
+// we need host clock, OTG/portsel clock and AHB clock
+#define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
+
+#define HCCA_SIZE sizeof(HCCA)
+#define ED_SIZE sizeof(HCED)
+#define TD_SIZE sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+
+static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256)));  //256 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost() {
+    instHost = this;
+    memInit();
+    memset((void*)usb_hcca, 0, HCCA_SIZE);
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        edBufAlloc[i] = false;
+    }
+    for (int i = 0; i < MAX_TD; i++) {
+        tdBufAlloc[i] = false;
+    }
+}
+
+void USBHALHost::init() {
+    NVIC_DisableIRQ(USB_IRQn);
+
+    //Cut power
+    LPC_SC->PCONP &= ~(1UL<<31);
+    wait_ms(100);
+
+    // turn on power for USB
+    LPC_SC->PCONP       |= (1UL<<31);
+
+    // Enable USB host clock, port selection and AHB clock
+    LPC_USB->USBClkCtrl |= CLOCK_MASK;
+
+    // Wait for clocks to become available
+    while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
+
+    // it seems the bits[0:1] mean the following
+    // 0: U1=device, U2=host
+    // 1: U1=host, U2=host
+    // 2: reserved
+    // 3: U1=host, U2=device
+    // NB: this register is only available if OTG clock (aka "port select") is enabled!!
+    // since we don't care about port 2, set just bit 0 to 1 (U1=host)
+    LPC_USB->OTGStCtrl |= 1;
+
+    // now that we've configured the ports, we can turn off the portsel clock
+    LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
+
+    // configure USB D+/D- pins
+    // P0[29] = USB_D+, 01
+    // P0[30] = USB_D-, 01
+    LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
+    LPC_PINCON->PINSEL1 |=  ((1<<26) | (1<<28));
+
+    LPC_USB->HcControl       = 0; // HARDWARE RESET
+    LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
+    LPC_USB->HcBulkHeadED    = 0; // Initialize Bulk list head to Zero
+
+    // Wait 100 ms before apply reset
+    wait_ms(100);
+
+    // software reset
+    LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
+
+    // Write Fm Interval and Largest Data Packet Counter
+    LPC_USB->HcFmInterval    = DEFAULT_FMINTERVAL;
+    LPC_USB->HcPeriodicStart = FI * 90 / 100;
+
+    // Put HC in operational state
+    LPC_USB->HcControl  = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
+    // Set Global Power
+    LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
+
+    LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
+
+    // Clear Interrrupt Status
+    LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
+
+    LPC_USB->HcInterruptEnable  = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
+
+    // Enable the USB Interrupt
+    NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
+    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
+    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+
+    NVIC_EnableIRQ(USB_IRQn);
+
+    // Check for any connected devices
+    if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
+        //Device connected
+        wait_ms(150);
+        USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
+        deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
+    }
+}
+
+uint32_t USBHALHost::controlHeadED() {
+    return LPC_USB->HcControlHeadED;
+}
+
+uint32_t USBHALHost::bulkHeadED() {
+    return LPC_USB->HcBulkHeadED;
+}
+
+uint32_t USBHALHost::interruptHeadED() {
+    return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr) {
+    LPC_USB->HcBulkHeadED = addr;
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr) {
+    LPC_USB->HcControlHeadED = addr;
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr) {
+    usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type) {
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
+            LPC_USB->HcControl |= OR_CONTROL_CLE;
+            break;
+        case ISOCHRONOUS_ENDPOINT:
+            break;
+        case BULK_ENDPOINT:
+            LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
+            LPC_USB->HcControl |= OR_CONTROL_BLE;
+            break;
+        case INTERRUPT_ENDPOINT:
+            LPC_USB->HcControl |= OR_CONTROL_PLE;
+            break;
+    }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type) {
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            if(LPC_USB->HcControl & OR_CONTROL_CLE) {
+                LPC_USB->HcControl &= ~OR_CONTROL_CLE;
+                return true;
+            }
+            return false;
+        case ISOCHRONOUS_ENDPOINT:
+            return false;
+        case BULK_ENDPOINT:
+            if(LPC_USB->HcControl & OR_CONTROL_BLE){
+                LPC_USB->HcControl &= ~OR_CONTROL_BLE;
+                return true;
+            }
+            return false;
+        case INTERRUPT_ENDPOINT:
+            if(LPC_USB->HcControl & OR_CONTROL_PLE) {
+                LPC_USB->HcControl &= ~OR_CONTROL_PLE;
+                return true;
+            }
+            return false;
+    }
+    return false;
+}
+
+
+void USBHALHost::memInit() {
+    usb_hcca = (volatile HCCA *)usb_buf;
+    usb_edBuf = usb_buf + HCCA_SIZE;
+    usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
+}
+
+volatile uint8_t * USBHALHost::getED() {
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        if ( !edBufAlloc[i] ) {
+            edBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+        }
+    }
+    perror("Could not allocate ED\r\n");
+    return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD() {
+    int i;
+    for (i = 0; i < MAX_TD; i++) {
+        if ( !tdBufAlloc[i] ) {
+            tdBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+        }
+    }
+    perror("Could not allocate TD\r\n");
+    return NULL; //Could not alloc TD
+}
+
+#if(1) /* Isochronous */
+bool USBHALHost::isTD(volatile uint8_t* td) {
+    if (td >= usb_tdBuf && td < (usb_tdBuf+TD_SIZE*MAX_TD)) {
+        return true;
+    }
+    return false;
+}
+#endif
+
+void USBHALHost::freeED(volatile uint8_t * ed) {
+    int i;
+    i = (ed - usb_edBuf) / ED_SIZE;
+    edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td) {
+    int i;
+    i = (td - usb_tdBuf) / TD_SIZE;
+    tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub() {
+    // Initiate port reset
+    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
+
+    while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
+
+    // ...and clear port reset signal
+    LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+}
+
+
+void USBHALHost::_usbisr(void) {
+    if (instHost) {
+        instHost->UsbIrqhandler();
+    }
+}
+
+void USBHALHost::UsbIrqhandler() {
+    if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
+    {
+
+        uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
+
+        // Root hub status change interrupt
+        if (int_status & OR_INTR_STATUS_RHSC) {
+            if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
+                if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
+                    // When DRWE is on, Connect Status Change
+                    // means a remote wakeup event.
+                } else {
+
+                    //Root device connected
+                    if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
+
+                        // wait 150ms to avoid bounce
+                        wait_ms(150);
+
+                        //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+                        deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
+                    }
+
+                    //Root device disconnected
+                    else {
+
+                        if (!(int_status & OR_INTR_STATUS_WDH)) {
+                            usb_hcca->DoneHead = 0;
+                        }
+
+                        // wait 200ms to avoid bounce
+                        wait_ms(200);
+
+                        deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+
+                        if (int_status & OR_INTR_STATUS_WDH) {
+                            usb_hcca->DoneHead = 0;
+                            LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
+                        }
+                    }
+                }
+                LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
+            }
+            if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
+                LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+            }
+            LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
+        }
+
+        // Writeback Done Head interrupt
+        if (int_status & OR_INTR_STATUS_WDH) {
+            transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+            LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
+        }
+    }
+}
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/USBHALHost_RZ_A1.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,290 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+
+#include "ohci_wrapp_RZ_A1.h"
+
+
+#define HCCA_SIZE sizeof(HCCA)
+#define ED_SIZE sizeof(HCED)
+#define TD_SIZE sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+#define ALIGNE_MSK (0x0000000F)
+
+static volatile uint8_t usb_buf[TOTAL_SIZE + ALIGNE_MSK];  //16 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost() {
+    instHost = this;
+    memInit();
+    memset((void*)usb_hcca, 0, HCCA_SIZE);
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        edBufAlloc[i] = false;
+    }
+    for (int i = 0; i < MAX_TD; i++) {
+        tdBufAlloc[i] = false;
+    }
+}
+
+void USBHALHost::init() {
+    ohciwrapp_init(&_usbisr);
+
+    ohciwrapp_reg_w(OHCI_REG_CONTROL, 1);       // HARDWARE RESET
+    ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, 0); // Initialize Control list head to Zero
+    ohciwrapp_reg_w(OHCI_REG_BULKHEADED, 0);    // Initialize Bulk list head to Zero
+
+    // Wait 100 ms before apply reset
+    wait_ms(100);
+
+    // software reset
+    ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_HCR);
+
+    // Write Fm Interval and Largest Data Packet Counter
+    ohciwrapp_reg_w(OHCI_REG_FMINTERVAL, DEFAULT_FMINTERVAL);
+    ohciwrapp_reg_w(OHCI_REG_PERIODICSTART,  FI * 90 / 100);
+
+    // Put HC in operational state
+    ohciwrapp_reg_w(OHCI_REG_CONTROL, (ohciwrapp_reg_r(OHCI_REG_CONTROL) & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER);
+    // Set Global Power
+    ohciwrapp_reg_w(OHCI_REG_RHSTATUS, OR_RH_STATUS_LPSC);
+
+    ohciwrapp_reg_w(OHCI_REG_HCCA, (uint32_t)(usb_hcca));
+
+    // Clear Interrrupt Status
+    ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS));
+
+    ohciwrapp_reg_w(OHCI_REG_INTERRUPTENABLE, OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC);
+
+    // Enable the USB Interrupt
+    ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
+    ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+
+    // Check for any connected devices
+    if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
+        //Device connected
+        wait_ms(150);
+        USB_DBG("Device connected (%08x)\n\r", ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1));
+        deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA);
+    }
+}
+
+uint32_t USBHALHost::controlHeadED() {
+    return ohciwrapp_reg_r(OHCI_REG_CONTROLHEADED);
+}
+
+uint32_t USBHALHost::bulkHeadED() {
+    return ohciwrapp_reg_r(OHCI_REG_BULKHEADED);
+}
+
+uint32_t USBHALHost::interruptHeadED() {
+    return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr) {
+    ohciwrapp_reg_w(OHCI_REG_BULKHEADED, addr);
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr) {
+    ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, addr);
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr) {
+    usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type) {
+    uint32_t wk_data;
+
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_CLF);
+            wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_CLE);
+            ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+            break;
+        case ISOCHRONOUS_ENDPOINT:
+            break;
+        case BULK_ENDPOINT:
+            ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_BLF);
+            wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_BLE);
+            ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+            break;
+        case INTERRUPT_ENDPOINT:
+            wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_PLE);
+            ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+            break;
+    }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type) {
+    uint32_t wk_data;
+
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+            if(wk_data & OR_CONTROL_CLE) {
+                wk_data &= ~OR_CONTROL_CLE;
+                ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+                return true;
+            }
+            return false;
+        case ISOCHRONOUS_ENDPOINT:
+            return false;
+        case BULK_ENDPOINT:
+            wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+            if(wk_data & OR_CONTROL_BLE) {
+                wk_data &= ~OR_CONTROL_BLE;
+                ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+                return true;
+            }
+            return false;
+        case INTERRUPT_ENDPOINT:
+            wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+            if(wk_data & OR_CONTROL_PLE) {
+                wk_data &= ~OR_CONTROL_PLE;
+                ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+                return true;
+            }
+            return false;
+    }
+    return false;
+}
+
+
+void USBHALHost::memInit() {
+    volatile uint8_t *p_wk_buf = (uint8_t *)(((uint32_t)usb_buf + ALIGNE_MSK) & ~ALIGNE_MSK);
+
+    usb_hcca = (volatile HCCA *)p_wk_buf;
+    usb_edBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE);
+    usb_tdBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE));
+}
+
+volatile uint8_t * USBHALHost::getED() {
+    for (int i = 0; i < MAX_ENDPOINT; i++) {
+        if ( !edBufAlloc[i] ) {
+            edBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+        }
+    }
+    perror("Could not allocate ED\r\n");
+    return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD() {
+    int i;
+    for (i = 0; i < MAX_TD; i++) {
+        if ( !tdBufAlloc[i] ) {
+            tdBufAlloc[i] = true;
+            return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+        }
+    }
+    perror("Could not allocate TD\r\n");
+    return NULL; //Could not alloc TD
+}
+
+#if(1) /* Isochronous */
+bool USBHALHost::isTD(volatile uint8_t* td) {
+    if (td >= usb_tdBuf && td < (usb_tdBuf+TD_SIZE*MAX_TD)) {
+        return true;
+    }
+    return false;
+}
+#endif
+
+void USBHALHost::freeED(volatile uint8_t * ed) {
+    int i;
+    i = (ed - usb_edBuf) / ED_SIZE;
+    edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td) {
+    int i;
+    i = (td - usb_tdBuf) / TD_SIZE;
+    tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub() {
+    // Initiate port reset
+    ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRS);
+
+    while (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRS);
+
+    // ...and clear port reset signal
+    ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+}
+
+
+void USBHALHost::_usbisr(void) {
+    if (instHost) {
+        instHost->UsbIrqhandler();
+    }
+}
+
+void USBHALHost::UsbIrqhandler() {
+    uint32_t int_status = ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS) & ohciwrapp_reg_r(OHCI_REG_INTERRUPTENABLE);
+    uint32_t data;
+
+    if (int_status != 0) { //Is there something to actually process?
+        // Root hub status change interrupt
+        if (int_status & OR_INTR_STATUS_RHSC) {
+            if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CSC) {
+                if (ohciwrapp_reg_r(OHCI_REG_RHSTATUS) & OR_RH_STATUS_DRWE) {
+                    // When DRWE is on, Connect Status Change
+                    // means a remote wakeup event.
+                } else {
+
+                    //Root device connected
+                    if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
+
+                        // wait 150ms to avoid bounce
+                        wait_ms(150);
+
+                        //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+                        data = ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA;
+                        deviceConnected(0, 1, data);
+                    }
+
+                    //Root device disconnected
+                    else {
+                        deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+                    }
+                }
+                ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
+            }
+            if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRSC) {
+                ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+            }
+            ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_RHSC);
+        }
+
+        // Writeback Done Head interrupt
+        if (int_status & OR_INTR_STATUS_WDH) {
+            transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+            ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH);
+        }
+    }
+}
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/USBHost.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1184 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "USBHost.h"
+#include "USBHostHub.h"
+#if(1) /* Isochronous */
+#include "USBIsochronous.h"
+#endif
+
+USBHost * USBHost::instHost = NULL;
+
+#define DEVICE_CONNECTED_EVENT      (1 << 0)
+#define DEVICE_DISCONNECTED_EVENT   (1 << 1)
+#define TD_PROCESSED_EVENT          (1 << 2)
+
+#define MAX_TRY_ENUMERATE_HUB       3
+
+#define MIN(a, b) ((a > b) ? b : a)
+
+/**
+* How interrupts are processed:
+*    - new device connected:
+*       - a message is queued in queue_usb_event with the id DEVICE_CONNECTED_EVENT
+*       - when the usb_thread receives the event, it:
+*           - resets the device
+*           - reads the device descriptor
+*           - sets the address of the device
+*           - if it is a hub, enumerates it
+*   - device disconnected:
+*       - a message is queued in queue_usb_event with the id DEVICE_DISCONNECTED_EVENT
+*       - when the usb_thread receives the event, it:
+*           - free the device and all its children (hub)
+*   - td processed
+*       - a message is queued in queue_usb_event with the id TD_PROCESSED_EVENT
+*       - when the usb_thread receives the event, it:
+*           - call the callback attached to the endpoint where the td is attached
+*/
+void USBHost::usb_process() {
+
+    bool controlListState;
+    bool bulkListState;
+    bool interruptListState;
+    USBEndpoint * ep;
+    uint8_t i, j, res, timeout_set_addr = 10;
+    uint8_t buf[8];
+    bool too_many_hub;
+    int idx;
+
+#if DEBUG_TRANSFER
+    uint8_t * buf_transfer;
+#endif
+
+#if MAX_HUB_NB
+    uint8_t k;
+#endif
+
+    while(1) {
+        osEvent evt = mail_usb_event.get();
+
+        if (evt.status == osEventMail) {
+
+            message_t * usb_msg = (message_t*)evt.value.p;
+
+            switch (usb_msg->event_id) {
+
+                // a new device has been connected
+                case DEVICE_CONNECTED_EVENT:
+                    too_many_hub = false;
+                    buf[4] = 0;
+
+                    do
+                    {
+                      Lock lock(this);
+
+                      for (i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+                          if (!deviceInUse[i]) {
+                              USB_DBG_EVENT("new device connected: %p\r\n", &devices[i]);
+                              devices[i].init(usb_msg->hub, usb_msg->port, usb_msg->lowSpeed);
+                              deviceReset[i] = false;
+                              deviceInited[i] = true;
+                              break;
+                          }
+                      }
+
+                      if (i == MAX_DEVICE_CONNECTED) {
+                          USB_ERR("Too many device connected!!\r\n");
+                          continue;
+                      }
+
+                      if (!controlEndpointAllocated) {
+                          control = newEndpoint(CONTROL_ENDPOINT, OUT, 0x08, 0x00);
+                          addEndpoint(NULL, 0, (USBEndpoint*)control);
+                          controlEndpointAllocated = true;
+                      }
+
+  #if MAX_HUB_NB
+                      if (usb_msg->hub_parent)
+                          devices[i].setHubParent((USBHostHub *)(usb_msg->hub_parent));
+  #endif
+
+                      for (j = 0; j < timeout_set_addr; j++) {
+
+                          resetDevice(&devices[i]);
+
+                          // set size of control endpoint
+                          devices[i].setSizeControlEndpoint(8);
+
+                          devices[i].activeAddress(false);
+
+                          // get first 8 bit of device descriptor
+                          // and check if we deal with a hub
+                          USB_DBG("usb_thread read device descriptor on dev: %p\r\n", &devices[i]);
+                          res = getDeviceDescriptor(&devices[i], buf, 8);
+
+                          if (res != USB_TYPE_OK) {
+                              USB_ERR("usb_thread could not read dev descr");
+                              continue;
+                          }
+
+                          // set size of control endpoint
+                          devices[i].setSizeControlEndpoint(buf[7]);
+
+                          // second step: set an address to the device
+                          res = setAddress(&devices[i], devices[i].getAddress());
+
+                          if (res != USB_TYPE_OK) {
+                              USB_ERR("SET ADDR FAILED");
+                              continue;
+                          }
+                          devices[i].activeAddress(true);
+                          USB_DBG("Address of %p: %d", &devices[i], devices[i].getAddress());
+
+                          // try to read again the device descriptor to check if the device
+                          // answers to its new address
+                          res = getDeviceDescriptor(&devices[i], buf, 8);
+
+                          if (res == USB_TYPE_OK) {
+                              break;
+                          }
+
+                          Thread::wait(100);
+                      }
+
+                      USB_INFO("New device connected: %p [hub: %d - port: %d]", &devices[i], usb_msg->hub, usb_msg->port);
+
+  #if MAX_HUB_NB
+                      if (buf[4] == HUB_CLASS) {
+                          for (k = 0; k < MAX_HUB_NB; k++) {
+                              if (hub_in_use[k] == false) {
+                                  for (uint8_t j = 0; j < MAX_TRY_ENUMERATE_HUB; j++) {
+                                      if (hubs[k].connect(&devices[i])) {
+                                          devices[i].hub = &hubs[k];
+                                          hub_in_use[k] = true;
+                                          break;
+                                      }
+                                  }
+                                  if (hub_in_use[k] == true)
+                                      break;
+                              }
+                          }
+
+                          if (k == MAX_HUB_NB) {
+                              USB_ERR("Too many hubs connected!!\r\n");
+                              too_many_hub = true;
+                          }
+                      }
+
+                      if (usb_msg->hub_parent)
+                          ((USBHostHub *)(usb_msg->hub_parent))->deviceConnected(&devices[i]);
+  #endif
+
+                      if ((i < MAX_DEVICE_CONNECTED) && !too_many_hub) {
+                          deviceInUse[i] = true;
+                      }
+
+                    } while(0);
+
+                    break;
+
+                // a device has been disconnected
+                case DEVICE_DISCONNECTED_EVENT:
+
+                    do
+                    {
+                      Lock lock(this);
+
+                      controlListState = disableList(CONTROL_ENDPOINT);
+                      bulkListState = disableList(BULK_ENDPOINT);
+                      interruptListState = disableList(INTERRUPT_ENDPOINT);
+
+                      idx = findDevice(usb_msg->hub, usb_msg->port, (USBHostHub *)(usb_msg->hub_parent));
+                      if (idx != -1) {
+                          freeDevice((USBDeviceConnected*)&devices[idx]);
+                      }
+
+                      if (controlListState) enableList(CONTROL_ENDPOINT);
+                      if (bulkListState) enableList(BULK_ENDPOINT);
+                      if (interruptListState) enableList(INTERRUPT_ENDPOINT);
+
+                    } while(0);
+
+                    break;
+
+                // a td has been processed
+                // call callback on the ed associated to the td
+                // we are not in ISR -> users can use printf in their callback method
+                case TD_PROCESSED_EVENT:
+                    ep = (USBEndpoint *) ((HCTD *)usb_msg->td_addr)->ep;
+                    if (usb_msg->td_state == USB_TYPE_IDLE) {
+                        USB_DBG_EVENT("call callback on td %p [ep: %p state: %s - dev: %p - %s]", usb_msg->td_addr, ep, ep->getStateString(), ep->dev, ep->dev->getName(ep->getIntfNb()));
+
+#if DEBUG_TRANSFER
+                        if (ep->getDir() == IN) {
+                            buf_transfer = ep->getBufStart();
+                            printf("READ SUCCESS [%d bytes transferred - td: 0x%08X] on ep: [%p - addr: %02X]: ",  ep->getLengthTransferred(), usb_msg->td_addr, ep, ep->getAddress());
+                            for (int i = 0; i < ep->getLengthTransferred(); i++)
+                                printf("%02X ", buf_transfer[i]);
+                            printf("\r\n\r\n");
+                        }
+#endif
+                        ep->call();
+                    } else {
+                        idx = findDevice(ep->dev);
+                        if (idx != -1) {
+                            if (deviceInUse[idx]) {
+                                USB_WARN("td %p processed but not in idle state: %s [ep: %p - dev: %p - %s]", usb_msg->td_addr, ep->getStateString(), ep, ep->dev, ep->dev->getName(ep->getIntfNb()));
+                                ep->setState(USB_TYPE_IDLE);
+                            }
+                        }
+                    }
+                    break;
+            }
+
+            mail_usb_event.free(usb_msg);
+        }
+    }
+}
+
+/* static */void USBHost::usb_process_static(void const * arg) {
+    ((USBHost *)arg)->usb_process();
+}
+
+USBHost::USBHost() : usbThread(USBHost::usb_process_static, (void *)this, osPriorityNormal, USB_THREAD_STACK)
+{
+    headControlEndpoint = NULL;
+    headBulkEndpoint = NULL;
+    headInterruptEndpoint = NULL;
+    tailControlEndpoint = NULL;
+    tailBulkEndpoint = NULL;
+    tailInterruptEndpoint = NULL;
+
+    lenReportDescr = 0;
+
+    controlEndpointAllocated = false;
+
+    for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+        deviceInUse[i] = false;
+        devices[i].setAddress(i + 1);
+        deviceReset[i] = false;
+        deviceInited[i] = false;
+        for (uint8_t j = 0; j < MAX_INTF; j++)
+            deviceAttachedDriver[i][j] = false;
+    }
+
+#if MAX_HUB_NB
+    for (uint8_t i = 0; i < MAX_HUB_NB; i++) {
+        hubs[i].setHost(this);
+        hub_in_use[i] = false;
+    }
+#endif
+    plug_status = false;
+}
+
+USBHost::Lock::Lock(USBHost* pHost) : m_pHost(pHost)
+{
+  m_pHost->usb_mutex.lock();
+}
+
+USBHost::Lock::~Lock()
+{
+  m_pHost->usb_mutex.unlock();
+}
+
+void USBHost::transferCompleted(volatile uint32_t addr)
+{
+    uint8_t state;
+
+    if(addr == 0)
+        return;
+
+    volatile HCTD* tdList = NULL;
+
+    //First we must reverse the list order and dequeue each TD
+    do {
+        volatile HCTD* td = (volatile HCTD*)addr;
+        addr = (uint32_t)td->nextTD; //Dequeue from physical list
+        td->nextTD = (hcTd*)tdList; //Enqueue into reversed list
+        tdList = td;
+    } while(addr);
+
+    while(tdList != NULL) {
+        volatile HCTD* td = tdList;
+        tdList = (volatile HCTD*)td->nextTD; //Dequeue element now as it could be modified below
+#if(1) /* Isochronous */
+        if (!isTD((uint8_t*)td)) { // ITD?
+            HCITD* itd = (HCITD*)td;
+            IsochronousEp* ep = itd->ep;
+            if (ep) {
+                ep->irqWdhHandler(itd);
+            }
+            continue;
+        }
+#endif
+        if (td->ep != NULL) {
+            USBEndpoint * ep = (USBEndpoint *)(td->ep);
+
+            if (((HCTD *)td)->control >> 28) {
+                state = ((HCTD *)td)->control >> 28;
+            } else {
+                if (td->currBufPtr)
+                    ep->setLengthTransferred((uint32_t)td->currBufPtr - (uint32_t)ep->getBufStart());
+                state = 16 /*USB_TYPE_IDLE*/;
+            }
+
+            ep->unqueueTransfer(td);
+
+            if (ep->getType() != CONTROL_ENDPOINT) {
+                // callback on the processed td will be called from the usb_thread (not in ISR)
+                message_t * usb_msg = mail_usb_event.alloc();
+                usb_msg->event_id = TD_PROCESSED_EVENT;
+                usb_msg->td_addr = (void *)td;
+                usb_msg->td_state = state;
+                mail_usb_event.put(usb_msg);
+            }
+            ep->setState(state);
+            ep->ep_queue.put((uint8_t*)1);
+        }
+    }
+}
+
+USBHost * USBHost::getHostInst()
+{
+    if (instHost == NULL) {
+        instHost = new USBHost();
+        instHost->init();
+    }
+    return instHost;
+}
+
+
+/*
+ * Called when a device has been connected
+ * Called in ISR!!!! (no printf)
+ */
+/* virtual */ void USBHost::deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent)
+{
+    // be sure that the new device connected is not already connected...
+    int idx = findDevice(hub, port, hub_parent);
+    if (idx != -1) {
+        if (deviceInited[idx])
+            return;
+    }
+
+    message_t * usb_msg = mail_usb_event.alloc();
+    usb_msg->event_id = DEVICE_CONNECTED_EVENT;
+    usb_msg->hub = hub;
+    usb_msg->port = port;
+    usb_msg->lowSpeed = lowSpeed;
+    usb_msg->hub_parent = hub_parent;
+    mail_usb_event.put(usb_msg);
+    plug_status = true;
+}
+
+/*
+ * Called when a device has been disconnected
+ * Called in ISR!!!! (no printf)
+ */
+/* virtual */ void USBHost::deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr)
+{
+    // be sure that the device disconnected is connected...
+    int idx = findDevice(hub, port, hub_parent);
+    if (idx != -1) {
+        if (!deviceInUse[idx])
+            return;
+    } else {
+        return;
+    }
+
+    message_t * usb_msg = mail_usb_event.alloc();
+    usb_msg->event_id = DEVICE_DISCONNECTED_EVENT;
+    usb_msg->hub = hub;
+    usb_msg->port = port;
+    usb_msg->hub_parent = hub_parent;
+    mail_usb_event.put(usb_msg);
+    plug_status = false;
+}
+
+void USBHost::freeDevice(USBDeviceConnected * dev)
+{
+    USBEndpoint * ep = NULL;
+    HCED * ed = NULL;
+
+#if MAX_HUB_NB
+    if (dev->getClass() == HUB_CLASS) {
+        if (dev->hub == NULL) {
+            USB_ERR("HUB NULL!!!!!\r\n");
+        } else {
+            dev->hub->hubDisconnected();
+            for (uint8_t i = 0; i < MAX_HUB_NB; i++) {
+                if (dev->hub == &hubs[i]) {
+                    hub_in_use[i] = false;
+                    break;
+                }
+            }
+        }
+    }
+
+    // notify hub parent that this device has been disconnected
+    if (dev->getHubParent())
+        dev->getHubParent()->deviceDisconnected(dev);
+
+#endif
+
+    int idx = findDevice(dev);
+    if (idx != -1) {
+        deviceInUse[idx] = false;
+        deviceReset[idx] = false;
+
+        for (uint8_t j = 0; j < MAX_INTF; j++) {
+            deviceAttachedDriver[idx][j] = false;
+            if (dev->getInterface(j) != NULL) {
+                USB_DBG("FREE INTF %d on dev: %p, %p, nb_endpot: %d, %s", j, (void *)dev->getInterface(j), dev, dev->getInterface(j)->nb_endpoint, dev->getName(j));
+                for (int i = 0; i < dev->getInterface(j)->nb_endpoint; i++) {
+                    if ((ep = dev->getEndpoint(j, i)) != NULL) {
+                        ed = (HCED *)ep->getHCED();
+                        ed->control |= (1 << 14); //sKip bit
+                        unqueueEndpoint(ep);
+
+                        freeTD((volatile uint8_t*)ep->getTDList()[0]);
+                        freeTD((volatile uint8_t*)ep->getTDList()[1]);
+
+                        freeED((uint8_t *)ep->getHCED());
+                    }
+                    printList(BULK_ENDPOINT);
+                    printList(INTERRUPT_ENDPOINT);
+                }
+                USB_INFO("Device disconnected [%p - %s - hub: %d - port: %d]", dev, dev->getName(j), dev->getHub(), dev->getPort());
+            }
+        }
+        dev->disconnect();
+    }
+}
+
+
+void USBHost::unqueueEndpoint(USBEndpoint * ep)
+{
+    USBEndpoint * prec = NULL;
+    USBEndpoint * current = NULL;
+
+    for (int i = 0; i < 2; i++) {
+        current = (i == 0) ? (USBEndpoint*)headBulkEndpoint : (USBEndpoint*)headInterruptEndpoint;
+        prec = current;
+        while (current != NULL) {
+            if (current == ep) {
+                if (current->nextEndpoint() != NULL) {
+                    prec->queueEndpoint(current->nextEndpoint());
+                    if (current == headBulkEndpoint) {
+                        updateBulkHeadED((uint32_t)current->nextEndpoint()->getHCED());
+                        headBulkEndpoint = current->nextEndpoint();
+                    } else if (current == headInterruptEndpoint) {
+                        updateInterruptHeadED((uint32_t)current->nextEndpoint()->getHCED());
+                        headInterruptEndpoint = current->nextEndpoint();
+                    }
+                }
+                // here we are dequeuing the queue of ed
+                // we need to update the tail pointer
+                else {
+                    prec->queueEndpoint(NULL);
+                    if (current == headBulkEndpoint) {
+                        updateBulkHeadED(0);
+                        headBulkEndpoint = current->nextEndpoint();
+                    } else if (current == headInterruptEndpoint) {
+                        updateInterruptHeadED(0);
+                        headInterruptEndpoint = current->nextEndpoint();
+                    }
+
+                    // modify tail
+                    switch (current->getType()) {
+                        case BULK_ENDPOINT:
+                            tailBulkEndpoint = prec;
+                            break;
+                        case INTERRUPT_ENDPOINT:
+                            tailInterruptEndpoint = prec;
+                            break;
+                        default:
+                            break;
+                    }
+                }
+                current->setState(USB_TYPE_FREE);
+                return;
+            }
+            prec = current;
+            current = current->nextEndpoint();
+        }
+    }
+}
+
+
+USBDeviceConnected * USBHost::getDevice(uint8_t index)
+{
+    if ((index >= MAX_DEVICE_CONNECTED) || (!deviceInUse[index])) {
+        return NULL;
+    }
+    return (USBDeviceConnected*)&devices[index];
+}
+
+// create an USBEndpoint descriptor. the USBEndpoint is not linked
+USBEndpoint * USBHost::newEndpoint(ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t addr)
+{
+    int i = 0;
+    HCED * ed = (HCED *)getED();
+    HCTD* td_list[2] = { (HCTD*)getTD(), (HCTD*)getTD() };
+
+    memset((void *)td_list[0], 0x00, sizeof(HCTD));
+    memset((void *)td_list[1], 0x00, sizeof(HCTD));
+
+    // search a free USBEndpoint
+    for (i = 0; i < MAX_ENDPOINT; i++) {
+        if (endpoints[i].getState() == USB_TYPE_FREE) {
+            endpoints[i].init(ed, type, dir, size, addr, td_list);
+            USB_DBG("USBEndpoint created (%p): type: %d, dir: %d, size: %d, addr: %d, state: %s", &endpoints[i], type, dir, size, addr, endpoints[i].getStateString());
+            return &endpoints[i];
+        }
+    }
+    USB_ERR("could not allocate more endpoints!!!!");
+    return NULL;
+}
+
+
+USB_TYPE USBHost::resetDevice(USBDeviceConnected * dev)
+{
+    int index = findDevice(dev);
+    if (index != -1) {
+        USB_DBG("Resetting hub %d, port %d\n", dev->getHub(), dev->getPort());
+        Thread::wait(100);
+        if (dev->getHub() == 0) {
+            resetRootHub();
+        }
+#if MAX_HUB_NB
+        else {
+            dev->getHubParent()->portReset(dev->getPort());
+        }
+#endif
+        Thread::wait(100);
+        deviceReset[index] = true;
+        return USB_TYPE_OK;
+    }
+
+    return USB_TYPE_ERROR;
+}
+
+// link the USBEndpoint to the linked list and attach an USBEndpoint to a device
+bool USBHost::addEndpoint(USBDeviceConnected * dev, uint8_t intf_nb, USBEndpoint * ep)
+{
+
+    if (ep == NULL) {
+        return false;
+    }
+
+    HCED * prevEd;
+
+    // set device address in the USBEndpoint descriptor
+    if (dev == NULL) {
+        ep->setDeviceAddress(0);
+    } else {
+        ep->setDeviceAddress(dev->getAddress());
+    }
+
+    if ((dev != NULL) && dev->getSpeed()) {
+        ep->setSpeed(dev->getSpeed());
+    }
+
+    ep->setIntfNb(intf_nb);
+
+    // queue the new USBEndpoint on the ED list
+    switch (ep->getType()) {
+
+        case CONTROL_ENDPOINT:
+            prevEd = ( HCED*) controlHeadED();
+            if (!prevEd) {
+                updateControlHeadED((uint32_t) ep->getHCED());
+                USB_DBG_TRANSFER("First control USBEndpoint: %08X", (uint32_t) ep->getHCED());
+                headControlEndpoint = ep;
+                tailControlEndpoint = ep;
+                return true;
+            }
+            tailControlEndpoint->queueEndpoint(ep);
+            tailControlEndpoint = ep;
+            return true;
+
+        case BULK_ENDPOINT:
+            prevEd = ( HCED*) bulkHeadED();
+            if (!prevEd) {
+                updateBulkHeadED((uint32_t) ep->getHCED());
+                USB_DBG_TRANSFER("First bulk USBEndpoint: %08X\r\n", (uint32_t) ep->getHCED());
+                headBulkEndpoint = ep;
+                tailBulkEndpoint = ep;
+                break;
+            }
+            USB_DBG_TRANSFER("Queue BULK Ed %p after %p\r\n",ep->getHCED(), prevEd);
+            tailBulkEndpoint->queueEndpoint(ep);
+            tailBulkEndpoint = ep;
+            break;
+
+        case INTERRUPT_ENDPOINT:
+            prevEd = ( HCED*) interruptHeadED();
+            if (!prevEd) {
+                updateInterruptHeadED((uint32_t) ep->getHCED());
+                USB_DBG_TRANSFER("First interrupt USBEndpoint: %08X\r\n", (uint32_t) ep->getHCED());
+                headInterruptEndpoint = ep;
+                tailInterruptEndpoint = ep;
+                break;
+            }
+            USB_DBG_TRANSFER("Queue INTERRUPT Ed %p after %p\r\n",ep->getHCED(), prevEd);
+            tailInterruptEndpoint->queueEndpoint(ep);
+            tailInterruptEndpoint = ep;
+            break;
+        default:
+            return false;
+    }
+
+    ep->dev = dev;
+    dev->addEndpoint(intf_nb, ep);
+
+    return true;
+}
+
+
+int USBHost::findDevice(USBDeviceConnected * dev)
+{
+    for (int i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+        if (dev == &devices[i]) {
+            return i;
+        }
+    }
+    return -1;
+}
+
+int USBHost::findDevice(uint8_t hub, uint8_t port, USBHostHub * hub_parent)
+{
+    for (int i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+        if (devices[i].getHub() == hub && devices[i].getPort() == port) {
+            if (hub_parent != NULL) {
+                if (hub_parent == devices[i].getHubParent())
+                    return i;
+            } else {
+                return i;
+            }
+        }
+    }
+    return -1;
+}
+
+void USBHost::printList(ENDPOINT_TYPE type)
+{
+#if DEBUG_EP_STATE
+    volatile HCED * hced;
+    switch(type) {
+        case CONTROL_ENDPOINT:
+            hced = (HCED *)controlHeadED();
+            break;
+        case BULK_ENDPOINT:
+            hced = (HCED *)bulkHeadED();
+            break;
+        case INTERRUPT_ENDPOINT:
+            hced = (HCED *)interruptHeadED();
+            break;
+    }
+    volatile HCTD * hctd = NULL;
+    const char * type_str = (type == BULK_ENDPOINT) ? "BULK" :
+                            ((type == INTERRUPT_ENDPOINT) ? "INTERRUPT" :
+                            ((type == CONTROL_ENDPOINT) ? "CONTROL" : "ISOCHRONOUS"));
+    printf("State of %s:\r\n", type_str);
+    while (hced != NULL) {
+        uint8_t dir = ((hced->control & (3 << 11)) >> 11);
+        printf("hced: %p [ADDR: %d, DIR: %s, EP_NB: 0x%X]\r\n", hced,
+                                                   hced->control & 0x7f,
+                                                   (dir == 1) ? "OUT" : ((dir == 0) ? "FROM_TD":"IN"),
+                                                    (hced->control & (0xf << 7)) >> 7);
+        hctd = (HCTD *)((uint32_t)(hced->headTD) & ~(0xf));
+        while (hctd != hced->tailTD) {
+            printf("\thctd: %p [DIR: %s]\r\n", hctd, ((hctd->control & (3 << 19)) >> 19) == 1 ? "OUT" : "IN");
+            hctd = hctd->nextTD;
+        }
+        printf("\thctd: %p\r\n", hctd);
+        hced = hced->nextED;
+    }
+    printf("\r\n\r\n");
+#endif
+}
+
+
+// add a transfer on the TD linked list
+USB_TYPE USBHost::addTransfer(USBEndpoint * ed, uint8_t * buf, uint32_t len)
+{
+    td_mutex.lock();
+
+    // allocate a TD which will be freed in TDcompletion
+    volatile HCTD * td = ed->getNextTD();
+    if (td == NULL) {
+        return USB_TYPE_ERROR;
+    }
+
+    uint32_t token = (ed->isSetup() ? TD_SETUP : ( (ed->getDir() == IN) ? TD_IN : TD_OUT ));
+
+    uint32_t td_toggle;
+
+    if (ed->getType() == CONTROL_ENDPOINT) {
+        if (ed->isSetup()) {
+            td_toggle = TD_TOGGLE_0;
+        } else {
+            td_toggle = TD_TOGGLE_1;
+        }
+    } else {
+        td_toggle = 0;
+    }
+
+    td->control      = (TD_ROUNDING | token | TD_DELAY_INT(0) | td_toggle | TD_CC);
+    td->currBufPtr   = buf;
+    td->bufEnd       = (buf + (len - 1));
+
+    ENDPOINT_TYPE type = ed->getType();
+
+    disableList(type);
+    ed->queueTransfer();
+    printList(type);
+    enableList(type);
+
+    td_mutex.unlock();
+
+    return USB_TYPE_PROCESSING;
+}
+
+
+
+USB_TYPE USBHost::getDeviceDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_dev_descr)
+{
+    USB_TYPE t = controlRead(  dev,
+                         USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+                         GET_DESCRIPTOR,
+                         (DEVICE_DESCRIPTOR << 8) | (0),
+                         0, buf, MIN(DEVICE_DESCRIPTOR_LENGTH, max_len_buf));
+    if (len_dev_descr)
+        *len_dev_descr = MIN(DEVICE_DESCRIPTOR_LENGTH, max_len_buf);
+
+    return t;
+}
+
+USB_TYPE USBHost::getConfigurationDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_conf_descr)
+{
+    USB_TYPE res;
+    uint16_t total_conf_descr_length = 0;
+
+    // fourth step: get the beginning of the configuration descriptor to have the total length of the conf descr
+    res = controlRead(  dev,
+                        USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+                        GET_DESCRIPTOR,
+                        (CONFIGURATION_DESCRIPTOR << 8) | (0),
+                        0, buf, CONFIGURATION_DESCRIPTOR_LENGTH);
+
+    if (res != USB_TYPE_OK) {
+        USB_ERR("GET CONF 1 DESCR FAILED");
+        return res;
+    }
+    total_conf_descr_length = buf[2] | (buf[3] << 8);
+    total_conf_descr_length = MIN(max_len_buf, total_conf_descr_length);
+
+    if (len_conf_descr)
+        *len_conf_descr = total_conf_descr_length;
+
+    USB_DBG("TOTAL_LENGTH: %d \t NUM_INTERF: %d", total_conf_descr_length, buf[4]);
+
+    return controlRead(  dev,
+                         USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+                         GET_DESCRIPTOR,
+                         (CONFIGURATION_DESCRIPTOR << 8) | (0),
+                         0, buf, total_conf_descr_length);
+}
+
+
+USB_TYPE USBHost::setAddress(USBDeviceConnected * dev, uint8_t address) {
+    return controlWrite(    dev,
+                            USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE,
+                            SET_ADDRESS,
+                            address,
+                            0, NULL, 0);
+
+}
+
+USB_TYPE USBHost::setConfiguration(USBDeviceConnected * dev, uint8_t conf)
+{
+    return controlWrite( dev,
+                         USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE,
+                         SET_CONFIGURATION,
+                         conf,
+                         0, NULL, 0);
+}
+
+uint8_t USBHost::numberDriverAttached(USBDeviceConnected * dev) {
+    int index = findDevice(dev);
+    uint8_t cnt = 0;
+    if (index == -1)
+        return 0;
+    for (uint8_t i = 0; i < MAX_INTF; i++) {
+        if (deviceAttachedDriver[index][i])
+            cnt++;
+    }
+    return cnt;
+}
+
+// enumerate a device with the control USBEndpoint
+USB_TYPE USBHost::enumerate(USBDeviceConnected * dev, IUSBEnumerator* pEnumerator)
+{
+    uint16_t total_conf_descr_length = 0;
+    USB_TYPE res;
+
+    do
+    {
+      Lock lock(this);
+
+      // don't enumerate a device which all interfaces are registered to a specific driver
+      int index = findDevice(dev);
+
+      if (index == -1) {
+          return USB_TYPE_ERROR;
+      }
+
+      uint8_t nb_intf_attached = numberDriverAttached(dev);
+      USB_DBG("dev: %p nb_intf: %d", dev, dev->getNbIntf());
+      USB_DBG("dev: %p nb_intf_attached: %d", dev, nb_intf_attached);
+      if ((nb_intf_attached != 0) && (dev->getNbIntf() == nb_intf_attached)) {
+          USB_DBG("Don't enumerate dev: %p because all intf are registered with a driver", dev);
+          return USB_TYPE_OK;
+      }
+
+      USB_DBG("Enumerate dev: %p", dev);
+
+      // third step: get the whole device descriptor to see vid, pid
+      res = getDeviceDescriptor(dev, data, DEVICE_DESCRIPTOR_LENGTH);
+
+      if (res != USB_TYPE_OK) {
+          USB_DBG("GET DEV DESCR FAILED");
+          return res;
+      }
+
+      dev->setClass(data[4]);
+      dev->setSubClass(data[5]);
+      dev->setProtocol(data[6]);
+      dev->setVid(data[8] | (data[9] << 8));
+      dev->setPid(data[10] | (data[11] << 8));
+      USB_DBG("CLASS: %02X \t VID: %04X \t PID: %04X", data[4], data[8] | (data[9] << 8), data[10] | (data[11] << 8));
+
+      pEnumerator->setVidPid( data[8] | (data[9] << 8), data[10] | (data[11] << 8) );
+
+      res = getConfigurationDescriptor(dev, data, sizeof(data), &total_conf_descr_length);
+      if (res != USB_TYPE_OK) {
+          return res;
+      }
+
+  #if (DEBUG > 3)
+      USB_DBG("CONFIGURATION DESCRIPTOR:\r\n");
+      for (int i = 0; i < total_conf_descr_length; i++)
+          printf("%02X ", data[i]);
+      printf("\r\n\r\n");
+  #endif
+
+      // Parse the configuration descriptor
+      parseConfDescr(dev, data, total_conf_descr_length, pEnumerator);
+
+      // only set configuration if not enumerated before
+      if (!dev->isEnumerated()) {
+
+          USB_DBG("Set configuration 1 on dev: %p", dev);
+          // sixth step: set configuration (only 1 supported)
+          res = setConfiguration(dev, 1);
+
+          if (res != USB_TYPE_OK) {
+              USB_DBG("SET CONF FAILED");
+              return res;
+          }
+      }
+
+      dev->setEnumerated();
+
+      // Now the device is enumerated!
+      USB_DBG("dev %p is enumerated\r\n", dev);
+
+    } while(0);
+
+    // Some devices may require this delay
+    Thread::wait(100);
+
+    return USB_TYPE_OK;
+}
+// this method fills the USBDeviceConnected object: class,.... . It also add endpoints found in the descriptor.
+void USBHost::parseConfDescr(USBDeviceConnected * dev, uint8_t * conf_descr, uint32_t len, IUSBEnumerator* pEnumerator)
+{
+    uint32_t index = 0;
+    uint32_t len_desc = 0;
+    uint8_t id = 0;
+    int nb_endpoints_used = 0;
+    USBEndpoint * ep = NULL;
+    uint8_t intf_nb = 0;
+    bool parsing_intf = false;
+    uint8_t current_intf = 0;
+
+#if(1) /* Isochronous */
+    lenCnfdDescr = len;
+    indexCnfdDescr = 0;
+#endif
+
+    while (index < len) {
+        len_desc = conf_descr[index];
+        id = conf_descr[index+1];
+        switch (id) {
+            case CONFIGURATION_DESCRIPTOR:
+                USB_DBG("dev: %p has %d intf", dev, conf_descr[4]);
+                dev->setNbIntf(conf_descr[4]);
+                break;
+            case INTERFACE_DESCRIPTOR:
+                if(pEnumerator->parseInterface(conf_descr[index + 2], conf_descr[index + 5], conf_descr[index + 6], conf_descr[index + 7])) {
+                    if (intf_nb++ <= MAX_INTF) {
+                        current_intf = conf_descr[index + 2];
+                        dev->addInterface(current_intf, conf_descr[index + 5], conf_descr[index + 6], conf_descr[index + 7]);
+                        nb_endpoints_used = 0;
+                        USB_DBG("ADD INTF %d on device %p: class: %d, subclass: %d, proto: %d", current_intf, dev, conf_descr[index + 5],conf_descr[index + 6],conf_descr[index + 7]);
+                    } else {
+                        USB_DBG("Drop intf...");
+                    }
+                    parsing_intf = true;
+                } else {
+                    parsing_intf = false;
+                }
+                break;
+            case ENDPOINT_DESCRIPTOR:
+                if (parsing_intf && (intf_nb <= MAX_INTF) ) {
+                    if (nb_endpoints_used < MAX_ENDPOINT_PER_INTERFACE) {
+                        if( pEnumerator->useEndpoint(current_intf, (ENDPOINT_TYPE)(conf_descr[index + 3] & 0x03), (ENDPOINT_DIRECTION)((conf_descr[index + 2] >> 7) + 1)) ) {
+                            // if the USBEndpoint is isochronous -> skip it (TODO: fix this)
+                            if ((conf_descr[index + 3] & 0x03) != ISOCHRONOUS_ENDPOINT) {
+                                ep = newEndpoint((ENDPOINT_TYPE)(conf_descr[index+3] & 0x03),
+                                                 (ENDPOINT_DIRECTION)((conf_descr[index + 2] >> 7) + 1),
+                                                 conf_descr[index + 4] | (conf_descr[index + 5] << 8),
+                                                 conf_descr[index + 2] & 0x0f);
+                                USB_DBG("ADD USBEndpoint %p, on interf %d on device %p", ep, current_intf, dev);
+                                if (ep != NULL && dev != NULL) {
+                                    addEndpoint(dev, current_intf, ep);
+                                } else {
+                                    USB_DBG("EP NULL");
+                                }
+                                nb_endpoints_used++;
+                            } else {
+                                USB_DBG("ISO USBEndpoint NOT SUPPORTED");
+                            }
+                        }
+                    }
+                }
+                break;
+            case HID_DESCRIPTOR:
+                lenReportDescr = conf_descr[index + 7] | (conf_descr[index + 8] << 8);
+                break;
+            default:
+                break;
+        }
+        index += len_desc;
+#if(1) /* Isochronous */
+       indexCnfdDescr = index;
+#endif
+    }
+}
+
+
+USB_TYPE USBHost::bulkWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+    return generalTransfer(dev, ep, buf, len, blocking, BULK_ENDPOINT, true);
+}
+
+USB_TYPE USBHost::bulkRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+    return generalTransfer(dev, ep, buf, len, blocking, BULK_ENDPOINT, false);
+}
+
+USB_TYPE USBHost::interruptWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+    return generalTransfer(dev, ep, buf, len, blocking, INTERRUPT_ENDPOINT, true);
+}
+
+USB_TYPE USBHost::interruptRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+    return generalTransfer(dev, ep, buf, len, blocking, INTERRUPT_ENDPOINT, false);
+}
+
+USB_TYPE USBHost::generalTransfer(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking, ENDPOINT_TYPE type, bool write) {
+
+#if DEBUG_TRANSFER
+    const char * type_str = (type == BULK_ENDPOINT) ? "BULK" : ((type == INTERRUPT_ENDPOINT) ? "INTERRUPT" : "ISOCHRONOUS");
+    USB_DBG_TRANSFER("----- %s %s [dev: %p - %s - hub: %d - port: %d - addr: %d - ep: %02X]------", type_str, (write) ? "WRITE" : "READ", dev, dev->getName(ep->getIntfNb()), dev->getHub(), dev->getPort(), dev->getAddress(), ep->getAddress());
+#endif
+
+    Lock lock(this);
+
+    USB_TYPE res;
+    ENDPOINT_DIRECTION dir = (write) ? OUT : IN;
+
+    if (dev == NULL) {
+        USB_ERR("dev NULL");
+        return USB_TYPE_ERROR;
+    }
+
+    if (ep == NULL) {
+        USB_ERR("ep NULL");
+        return USB_TYPE_ERROR;
+    }
+
+    if (ep->getState() != USB_TYPE_IDLE) {
+        USB_WARN("[ep: %p - dev: %p - %s] NOT IDLE: %s", ep, ep->dev, ep->dev->getName(ep->getIntfNb()), ep->getStateString());
+        return ep->getState();
+    }
+
+    if ((ep->getDir() != dir) || (ep->getType() != type)) {
+        USB_ERR("[ep: %p - dev: %p] wrong dir or bad USBEndpoint type", ep, ep->dev);
+        return USB_TYPE_ERROR;
+    }
+
+    if (dev->getAddress() != ep->getDeviceAddress()) {
+        USB_ERR("[ep: %p - dev: %p] USBEndpoint addr and device addr don't match", ep, ep->dev);
+        return USB_TYPE_ERROR;
+    }
+
+#if DEBUG_TRANSFER
+    if (write) {
+        USB_DBG_TRANSFER("%s WRITE buffer", type_str);
+        for (int i = 0; i < ep->getLengthTransferred(); i++)
+            printf("%02X ", buf[i]);
+        printf("\r\n\r\n");
+    }
+#endif
+    addTransfer(ep, buf, len);
+
+    if (blocking) {
+
+        ep->ep_queue.get();
+        res = ep->getState();
+
+        USB_DBG_TRANSFER("%s TRANSFER res: %s on ep: %p\r\n", type_str, ep->getStateString(), ep);
+
+        if (res != USB_TYPE_IDLE) {
+            return res;
+        }
+
+        return USB_TYPE_OK;
+    }
+
+    return USB_TYPE_PROCESSING;
+
+}
+
+
+USB_TYPE USBHost::controlRead(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len) {
+    return controlTransfer(dev, requestType, request, value, index, buf, len, false);
+}
+
+USB_TYPE USBHost::controlWrite(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len) {
+    return controlTransfer(dev, requestType, request, value, index, buf, len, true);
+}
+
+USB_TYPE USBHost::controlTransfer(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len, bool write)
+{
+    Lock lock(this);
+    USB_DBG_TRANSFER("----- CONTROL %s [dev: %p - hub: %d - port: %d] ------", (write) ? "WRITE" : "READ", dev, dev->getHub(), dev->getPort());
+
+    int length_transfer = len;
+    USB_TYPE res;
+    uint32_t token;
+
+    control->setSpeed(dev->getSpeed());
+    control->setSize(dev->getSizeControlEndpoint());
+    if (dev->isActiveAddress()) {
+        control->setDeviceAddress(dev->getAddress());
+    } else {
+        control->setDeviceAddress(0);
+    }
+
+    USB_DBG_TRANSFER("Control transfer on device: %d\r\n", control->getDeviceAddress());
+    fillControlBuf(requestType, request, value, index, len);
+
+#if DEBUG_TRANSFER
+    USB_DBG_TRANSFER("SETUP PACKET: ");
+    for (int i = 0; i < 8; i++)
+        printf("%01X ", setupPacket[i]);
+    printf("\r\n");
+#endif
+
+    control->setNextToken(TD_SETUP);
+    addTransfer(control, (uint8_t*)setupPacket, 8);
+
+    control->ep_queue.get();
+    res = control->getState();
+
+    USB_DBG_TRANSFER("CONTROL setup stage %s", control->getStateString());
+
+    if (res != USB_TYPE_IDLE) {
+        return res;
+    }
+
+    if (length_transfer) {
+        token = (write) ? TD_OUT : TD_IN;
+        control->setNextToken(token);
+        addTransfer(control, (uint8_t *)buf, length_transfer);
+
+        control->ep_queue.get();
+        res = control->getState();
+
+#if DEBUG_TRANSFER
+        USB_DBG_TRANSFER("CONTROL %s stage %s", (write) ? "WRITE" : "READ", control->getStateString());
+        if (write) {
+            USB_DBG_TRANSFER("CONTROL WRITE buffer");
+            for (int i = 0; i < control->getLengthTransferred(); i++)
+                printf("%02X ", buf[i]);
+            printf("\r\n\r\n");
+        } else {
+            USB_DBG_TRANSFER("CONTROL READ SUCCESS [%d bytes transferred]", control->getLengthTransferred());
+            for (int i = 0; i < control->getLengthTransferred(); i++)
+                printf("%02X ", buf[i]);
+            printf("\r\n\r\n");
+        }
+#endif
+
+        if (res != USB_TYPE_IDLE) {
+            return res;
+        }
+    }
+
+    token = (write) ? TD_IN : TD_OUT;
+    control->setNextToken(token);
+    addTransfer(control, NULL, 0);
+
+    control->ep_queue.get();
+    res = control->getState();
+
+    USB_DBG_TRANSFER("CONTROL ack stage %s", control->getStateString());
+
+    if (res != USB_TYPE_IDLE)
+        return res;
+
+    return USB_TYPE_OK;
+}
+
+
+void USBHost::fillControlBuf(uint8_t requestType, uint8_t request, uint16_t value, uint16_t index, int len)
+{
+    setupPacket[0] = requestType;
+    setupPacket[1] = request;
+    setupPacket[2] = (uint8_t) value;
+    setupPacket[3] = (uint8_t) (value >> 8);
+    setupPacket[4] = (uint8_t) index;
+    setupPacket[5] = (uint8_t) (index >> 8);
+    setupPacket[6] = (uint8_t) len;
+    setupPacket[7] = (uint8_t) (len >> 8);
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/USBHost.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,413 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOST_H
+#define USBHOST_H
+
+#include "USBHALHost.h"
+#include "USBDeviceConnected.h"
+#include "IUSBEnumerator.h"
+#include "USBHostConf.h"
+#include "rtos.h"
+#include "dbg.h"
+#include "USBHostHub.h"
+
+/**
+* USBHost class
+*   This class is a singleton. All drivers have a reference on the static USBHost instance
+*/
+class USBHost : public USBHALHost {
+public:
+    /**
+    * Static method to create or retrieve the single USBHost instance
+    */
+    static USBHost * getHostInst();
+
+    /**
+    * Control read: setup stage, data stage and status stage
+    *
+    * @param dev the control read will be done for this device
+    * @param requestType request type
+    * @param request request
+    * @param value value
+    * @param index index
+    * @param buf pointer on a buffer where will be store the data received
+    * @param len length of the transfer
+    *
+    * @returns status of the control read
+    */
+    USB_TYPE controlRead(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len);
+
+    /**
+    * Control write: setup stage, data stage and status stage
+    *
+    * @param dev the control write will be done for this device
+    * @param requestType request type
+    * @param request request
+    * @param value value
+    * @param index index
+    * @param buf pointer on a buffer which will be written
+    * @param len length of the transfer
+    *
+    * @returns status of the control write
+    */
+    USB_TYPE controlWrite(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len);
+
+    /**
+    * Bulk read
+    *
+    * @param dev the bulk transfer will be done for this device
+    * @param ep USBEndpoint which will be used to read a packet
+    * @param buf pointer on a buffer where will be store the data received
+    * @param len length of the transfer
+    * @param blocking if true, the read is blocking (wait for completion)
+    *
+    * @returns status of the bulk read
+    */
+    USB_TYPE bulkRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+    /**
+    * Bulk write
+    *
+    * @param dev the bulk transfer will be done for this device
+    * @param ep USBEndpoint which will be used to write a packet
+    * @param buf pointer on a buffer which will be written
+    * @param len length of the transfer
+    * @param blocking if true, the write is blocking (wait for completion)
+    *
+    * @returns status of the bulk write
+    */
+    USB_TYPE bulkWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+    /**
+    * Interrupt read
+    *
+    * @param dev the bulk transfer will be done for this device
+    * @param ep USBEndpoint which will be used to write a packet
+    * @param buf pointer on a buffer which will be written
+    * @param len length of the transfer
+    * @param blocking if true, the read is blocking (wait for completion)
+    *
+    * @returns status of the interrupt read
+    */
+    USB_TYPE interruptRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+    /**
+    * Interrupt write
+    *
+    * @param dev the bulk transfer will be done for this device
+    * @param ep USBEndpoint which will be used to write a packet
+    * @param buf pointer on a buffer which will be written
+    * @param len length of the transfer
+    * @param blocking if true, the write is blocking (wait for completion)
+    *
+    * @returns status of the interrupt write
+    */
+    USB_TYPE interruptWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+    /**
+    * Enumerate a device.
+    *
+    * @param dev device which will be enumerated
+    *
+    * @returns status of the enumeration
+    */
+    USB_TYPE enumerate(USBDeviceConnected * dev, IUSBEnumerator* pEnumerator);
+#if(1) /* Isochronous */
+    inline uint8_t * getConfDescrCurPtr() {
+        return &data[indexCnfdDescr];
+    };
+
+    inline uint16_t getConfDescrRestLen() {
+        return lenCnfdDescr - indexCnfdDescr;
+    };
+#endif
+
+    /**
+    * reset a specific device
+    *
+    * @param dev device which will be resetted
+    */
+    USB_TYPE resetDevice(USBDeviceConnected * dev);
+
+    /**
+    * Get a device
+    *
+    * @param index index of the device which will be returned
+    *
+    * @returns pointer on the "index" device
+    */
+    USBDeviceConnected * getDevice(uint8_t index);
+
+    /*
+    * If there is a HID device connected, the host stores the length of the report descriptor.
+    * This avoid to the driver to re-ask the configuration descriptor to request the report descriptor
+    *
+    * @returns length of the report descriptor
+    */
+    inline uint16_t getLengthReportDescr() {
+        return lenReportDescr;
+    };
+
+    /**
+     *  register a driver into the host associated with a callback function called when the device is disconnected
+     *
+     *  @param dev device
+     *  @param intf interface number
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     */
+    template<typename T>
+    inline void registerDriver(USBDeviceConnected * dev, uint8_t intf, T* tptr, void (T::*mptr)(void)) {
+        int index = findDevice(dev);
+        if ((index != -1) && (mptr != NULL) && (tptr != NULL)) {
+            USB_DBG("register driver for dev: %p on intf: %d", dev, intf);
+            deviceAttachedDriver[index][intf] = true;
+            dev->onDisconnect(intf, tptr, mptr);
+        }
+    }
+
+    /**
+     * register a driver into the host associated with a callback function called when the device is disconnected
+     *
+     * @param dev device
+     * @param intf interface number
+     * @param fn callback called when the specified device has been disconnected
+     */
+    inline void registerDriver(USBDeviceConnected * dev, uint8_t intf, void (*fn)(void)) {
+        int index = findDevice(dev);
+        if ((index != -1) && (fn != NULL)) {
+            USB_DBG("register driver for dev: %p on intf: %d", dev, intf);
+            deviceAttachedDriver[index][intf] = true;
+            dev->onDisconnect(intf, fn);
+        }
+    }
+
+    /**
+     * Instantiate to protect USB thread from accessing shared objects (USBConnectedDevices and Interfaces)
+     */
+    class Lock
+    {
+    public:
+      Lock(USBHost* pHost);
+      ~Lock();
+    private:
+      USBHost* m_pHost;
+    };
+
+    friend class USBHostHub;
+    bool plug_status;
+
+protected:
+
+    /**
+    * Virtual method called when a transfer has been completed
+    *
+    * @param addr list of the TDs which have been completed
+    */
+    virtual void transferCompleted(volatile uint32_t addr);
+
+    /**
+    * Virtual method called when a device has been connected
+    *
+    * @param hub hub number of the device
+    * @param port port number of the device
+    * @param lowSpeed 1 if low speed, 0 otherwise
+    * @param hub_parent reference on the parent hub
+    */
+    virtual void deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent = NULL);
+
+    /**
+    * Virtuel method called when a device has been disconnected
+    *
+    * @param hub hub number of the device
+    * @param port port number of the device
+    * @param addr list of the TDs which have been completed to dequeue freed TDs
+    */
+    virtual void deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr);
+
+
+private:
+    // singleton class -> constructor is private
+    USBHost();
+    static USBHost * instHost;
+    uint16_t  lenReportDescr;
+#if(1) /* Isochronous */
+    uint16_t  lenCnfdDescr;
+    uint16_t  indexCnfdDescr;
+#endif
+
+    // endpoints
+    void unqueueEndpoint(USBEndpoint * ep) ;
+    USBEndpoint  endpoints[MAX_ENDPOINT];
+    USBEndpoint* volatile  control;
+
+    USBEndpoint* volatile  headControlEndpoint;
+    USBEndpoint* volatile  headBulkEndpoint;
+    USBEndpoint* volatile  headInterruptEndpoint;
+
+    USBEndpoint* volatile  tailControlEndpoint;
+    USBEndpoint* volatile  tailBulkEndpoint;
+    USBEndpoint* volatile  tailInterruptEndpoint;
+
+    bool controlEndpointAllocated;
+
+    // devices connected
+    USBDeviceConnected devices[MAX_DEVICE_CONNECTED];
+    bool  deviceInUse[MAX_DEVICE_CONNECTED];
+    bool  deviceAttachedDriver[MAX_DEVICE_CONNECTED][MAX_INTF];
+    bool  deviceReset[MAX_DEVICE_CONNECTED];
+    bool  deviceInited[MAX_DEVICE_CONNECTED];
+
+#if MAX_HUB_NB
+    USBHostHub hubs[MAX_HUB_NB];
+    bool hub_in_use[MAX_HUB_NB];
+#endif
+
+    // to store a setup packet
+    uint8_t  setupPacket[8];
+
+    typedef struct {
+        uint8_t event_id;
+        void * td_addr;
+        uint8_t hub;
+        uint8_t port;
+        uint8_t lowSpeed;
+        uint8_t td_state;
+        void * hub_parent;
+    } message_t;
+
+    Thread usbThread;
+    void usb_process();
+    static void usb_process_static(void const * arg);
+    Mail<message_t, 10> mail_usb_event;
+    Mutex usb_mutex;
+    Mutex td_mutex;
+
+    // buffer for conf descriptor
+#if(1) /* Isochronous */
+    uint8_t data[1024];
+#else
+    uint8_t data[415];
+#endif
+
+    /**
+    * Add a transfer on the TD linked list associated to an ED
+    *
+    * @param ed the transfer is associated to this ed
+    * @param buf pointer on a buffer where will be read/write data to send or receive
+    * @param len transfer length
+    *
+    * @return status of the transfer
+    */
+    USB_TYPE addTransfer(USBEndpoint * ed, uint8_t * buf, uint32_t len) ;
+
+    /**
+    * Link the USBEndpoint to the linked list and attach an USBEndpoint this USBEndpoint to a device
+    *
+    * @param dev pointer on a USBDeviceConnected object
+    * @param ep pointer on the USBEndpoint which will be added
+    *
+    * return true if successful
+    */
+    bool addEndpoint(USBDeviceConnected * dev, uint8_t intf_nb, USBEndpoint * ep) ;
+
+    /**
+    * Create an USBEndpoint descriptor. Warning: the USBEndpoint is not linked.
+    *
+    * @param type USBEndpoint type (CONTROL_ENDPOINT, BULK_ENDPOINT, INTERRUPT_ENDPOINT)
+    * @param dir USBEndpoint direction (no meaning for CONTROL_ENDPOINT)
+    * @param size USBEndpoint max packet size
+    * @param addr USBEndpoint address
+    *
+    * @returns pointer on the USBEndpoint created
+    */
+    USBEndpoint * newEndpoint(ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t addr) ;
+
+    /**
+    * Request the device descriptor
+    *
+    * @param dev request the device descriptor on this device
+    * @param buf buffer to store the device descriptor
+    * @param max_len_buf maximum size of buf
+    * @param len_dev_descr pointer to store the length of the packet transferred
+    */
+    USB_TYPE getDeviceDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_dev_descr = NULL);
+
+    /**
+    * Request the configuration descriptor
+    *
+    * @param dev request the configuration descriptor on this device
+    * @param buf buffer to store the configuration descriptor
+    * @param max_len_buf maximum size of buf
+    * @param len_conf_descr pointer to store the length of the packet transferred
+    */
+    USB_TYPE getConfigurationDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_conf_descr = NULL);
+
+    /**
+    * Set the address of a specific device
+    *
+    * @param dev device to set the address
+    * @param address address
+    */
+    USB_TYPE setAddress(USBDeviceConnected * dev, uint8_t address);
+
+    /**
+    * Set the configuration of a device
+    *
+    * @param dev device on which the specified configuration will be activated
+    * @param conf configuration number to activate (usually 1)
+    */
+    USB_TYPE setConfiguration(USBDeviceConnected * dev, uint8_t conf);
+
+    /**
+    * Free a specific device
+    *
+    * @param dev device to be freed
+    */
+    void freeDevice(USBDeviceConnected * dev);
+
+    USB_TYPE controlTransfer(   USBDeviceConnected * dev,
+                                uint8_t requestType,
+                                uint8_t request,
+                                uint32_t value,
+                                uint32_t index,
+                                uint8_t * buf,
+                                uint32_t len,
+                                bool write);
+
+    USB_TYPE generalTransfer(   USBDeviceConnected * dev,
+                                USBEndpoint * ep,
+                                uint8_t * buf,
+                                uint32_t len,
+                                bool blocking,
+                                ENDPOINT_TYPE type,
+                                bool write) ;
+
+    void fillControlBuf(uint8_t requestType, uint8_t request, uint16_t value, uint16_t index, int len) ;
+    void parseConfDescr(USBDeviceConnected * dev, uint8_t * conf_descr, uint32_t len, IUSBEnumerator* pEnumerator) ;
+    int findDevice(USBDeviceConnected * dev) ;
+    int findDevice(uint8_t hub, uint8_t port, USBHostHub * hub_parent = NULL) ;
+    uint8_t numberDriverAttached(USBDeviceConnected * dev);
+
+    /////////////////////////
+    /// FOR DEBUG
+    /////////////////////////
+    void printList(ENDPOINT_TYPE type);
+
+};
+
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/USBHostConf.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,91 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOST_CONF_H
+#define USBHOST_CONF_H
+
+/*
+* Maximum number of devices that can be connected
+* to the usb host
+*/
+#define MAX_DEVICE_CONNECTED        5
+
+/*
+* Maximum of Hub connected to the usb host
+*/
+#define MAX_HUB_NB                  2
+
+/*
+* Maximum number of ports on a USB hub
+*/
+#define MAX_HUB_PORT                4
+
+/*
+* Enable USBHostMSD
+*/
+#define USBHOST_MSD                 1
+
+/*
+* Enable USBHostKeyboard
+*/
+#define USBHOST_KEYBOARD            1
+
+/*
+* Enable USBHostMouse
+*/
+#define USBHOST_MOUSE               1
+
+/*
+* Enable USBHostSerial or USBHostMultiSerial (if set > 1)
+*/
+#define USBHOST_SERIAL              1
+
+/*
+* Enable USB3Gmodule
+*/
+#define USBHOST_3GMODULE            1
+
+/*
+* Enable USB MIDI
+*/
+#define USBHOST_MIDI                1 
+
+/*
+* Maximum number of interfaces of a usb device
+*/
+#define MAX_INTF                    4
+
+/*
+* Maximum number of endpoints on each interface
+*/
+#define MAX_ENDPOINT_PER_INTERFACE  3
+
+/*
+* Maximum number of endpoint descriptors that can be allocated
+*/
+#define MAX_ENDPOINT                (MAX_DEVICE_CONNECTED * MAX_INTF * MAX_ENDPOINT_PER_INTERFACE)
+
+/*
+* Maximum number of transfer descriptors that can be allocated
+*/
+#define MAX_TD                      (MAX_ENDPOINT*2)
+
+/*
+* usb_thread stack size
+*/
+#define USB_THREAD_STACK            (256*4 + MAX_HUB_NB*256*4)
+
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/USBHostTypes.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,226 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USB_INC_H
+#define USB_INC_H
+
+#include "mbed.h"
+#include "toolchain.h"
+
+enum USB_TYPE {
+    USB_TYPE_OK = 0,
+
+    // completion code
+    USB_TYPE_CRC_ERROR = 1,
+    USB_TYPE_BIT_STUFFING_ERROR = 2,
+    USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR = 3,
+    USB_TYPE_STALL_ERROR = 4,
+    USB_TYPE_DEVICE_NOT_RESPONDING_ERROR = 5,
+    USB_TYPE_PID_CHECK_FAILURE_ERROR = 6,
+    USB_TYPE_UNEXPECTED_PID_ERROR = 7,
+    USB_TYPE_DATA_OVERRUN_ERROR = 8,
+    USB_TYPE_DATA_UNDERRUN_ERROR = 9,
+    USB_TYPE_RESERVED = 9,
+    USB_TYPE_RESERVED_ = 10,
+    USB_TYPE_BUFFER_OVERRUN_ERROR = 12,
+    USB_TYPE_BUFFER_UNDERRUN_ERROR = 13,
+
+    // general usb state
+    USB_TYPE_DISCONNECTED = 14,
+    USB_TYPE_FREE = 15,
+    USB_TYPE_IDLE = 16,
+    USB_TYPE_PROCESSING = 17,
+
+    USB_TYPE_ERROR = 18,
+};
+
+
+enum ENDPOINT_DIRECTION {
+    OUT = 1,
+    IN
+};
+
+enum ENDPOINT_TYPE {
+    CONTROL_ENDPOINT = 0,
+    ISOCHRONOUS_ENDPOINT,
+    BULK_ENDPOINT,
+    INTERRUPT_ENDPOINT
+};
+
+#define AUDIO_CLASS     0x01
+#define CDC_CLASS       0x02
+#define HID_CLASS       0x03
+#define MSD_CLASS       0x08
+#define HUB_CLASS       0x09
+#define SERIAL_CLASS    0x0A
+
+// ------------------ HcControl Register ---------------------
+#define  OR_CONTROL_PLE                 0x00000004
+#define  OR_CONTROL_CLE                 0x00000010
+#define  OR_CONTROL_BLE                 0x00000020
+#define  OR_CONTROL_HCFS                0x000000C0
+#define  OR_CONTROL_HC_OPER             0x00000080
+// ----------------- HcCommandStatus Register -----------------
+#define  OR_CMD_STATUS_HCR              0x00000001
+#define  OR_CMD_STATUS_CLF              0x00000002
+#define  OR_CMD_STATUS_BLF              0x00000004
+// --------------- HcInterruptStatus Register -----------------
+#define  OR_INTR_STATUS_WDH             0x00000002
+#define  OR_INTR_STATUS_RHSC            0x00000040
+#define  OR_INTR_STATUS_UE              0x00000010
+// --------------- HcInterruptEnable Register -----------------
+#define  OR_INTR_ENABLE_WDH             0x00000002
+#define  OR_INTR_ENABLE_RHSC            0x00000040
+#define  OR_INTR_ENABLE_MIE             0x80000000
+// ---------------- HcRhDescriptorA Register ------------------
+#define  OR_RH_STATUS_LPSC              0x00010000
+#define  OR_RH_STATUS_DRWE              0x00008000
+// -------------- HcRhPortStatus[1:NDP] Register --------------
+#define  OR_RH_PORT_CCS                 0x00000001
+#define  OR_RH_PORT_PRS                 0x00000010
+#define  OR_RH_PORT_CSC                 0x00010000
+#define  OR_RH_PORT_PRSC                0x00100000
+#define  OR_RH_PORT_LSDA                0x00000200
+
+#define  FI                     0x2EDF           // 12000 bits per frame (-1)
+#define  DEFAULT_FMINTERVAL     ((((6 * (FI - 210)) / 7) << 16) | FI)
+
+#define  ED_SKIP            (uint32_t) (0x00001000)        // Skip this ep in queue
+
+#define  TD_ROUNDING        (uint32_t) (0x00040000)        // Buffer Rounding
+#define  TD_SETUP           (uint32_t)(0)                  // Direction of Setup Packet
+#define  TD_IN              (uint32_t)(0x00100000)         // Direction In
+#define  TD_OUT             (uint32_t)(0x00080000)         // Direction Out
+#define  TD_DELAY_INT(x)    (uint32_t)((x) << 21)          // Delay Interrupt
+#define  TD_TOGGLE_0        (uint32_t)(0x02000000)         // Toggle 0
+#define  TD_TOGGLE_1        (uint32_t)(0x03000000)         // Toggle 1
+#define  TD_CC              (uint32_t)(0xF0000000)         // Completion Code
+
+#define  DEVICE_DESCRIPTOR                     (1)
+#define  CONFIGURATION_DESCRIPTOR              (2)
+#define  INTERFACE_DESCRIPTOR                  (4)
+#define  ENDPOINT_DESCRIPTOR                   (5)
+#define  HID_DESCRIPTOR                        (33)
+
+//  ----------- Control RequestType Fields  -----------
+#define  USB_DEVICE_TO_HOST         0x80
+#define  USB_HOST_TO_DEVICE         0x00
+#define  USB_REQUEST_TYPE_CLASS     0x20
+#define  USB_REQUEST_TYPE_STANDARD  0x00
+#define  USB_RECIPIENT_DEVICE       0x00
+#define  USB_RECIPIENT_INTERFACE    0x01
+#define  USB_RECIPIENT_ENDPOINT     0x02
+
+// -------------- USB Standard Requests  --------------
+#define  SET_ADDRESS                0x05
+#define  GET_DESCRIPTOR             0x06
+#define  SET_CONFIGURATION          0x09
+#define  SET_INTERFACE              0x0b
+#define  CLEAR_FEATURE              0x01
+
+// -------------- USB Descriptor Length  --------------
+#define DEVICE_DESCRIPTOR_LENGTH            0x12
+#define CONFIGURATION_DESCRIPTOR_LENGTH     0x09
+
+// ------------ HostController Transfer Descriptor ------------
+typedef struct hcTd {
+    __IO  uint32_t   control;        // Transfer descriptor control
+    __IO  uint8_t *  currBufPtr;    // Physical address of current buffer pointer
+    __IO  hcTd *     nextTD;         // Physical pointer to next Transfer Descriptor
+    __IO  uint8_t *  bufEnd;        // Physical address of end of buffer
+    void * ep;                      // ep address where a td is linked in
+    uint32_t dummy[3];              // padding
+} PACKED HCTD;
+
+// ----------- HostController EndPoint Descriptor -------------
+typedef struct hcEd {
+    __IO  uint32_t  control;        // Endpoint descriptor control
+    __IO  HCTD *  tailTD;           // Physical address of tail in Transfer descriptor list
+    __IO  HCTD *  headTD;           // Physcial address of head in Transfer descriptor list
+    __IO  hcEd *  nextED;         // Physical address of next Endpoint descriptor
+} PACKED HCED;
+
+
+// ----------- Host Controller Communication Area ------------
+typedef struct hcca {
+    __IO  uint32_t  IntTable[32];   // Interrupt Table
+    __IO  uint32_t  FrameNumber;    // Frame Number
+    __IO  uint32_t  DoneHead;       // Done Head
+    volatile  uint8_t   Reserved[116];  // Reserved for future use
+    volatile  uint8_t   Unknown[4];     // Unused
+} PACKED HCCA;
+
+typedef struct {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint16_t bcdUSB;
+    uint8_t bDeviceClass;
+    uint8_t bDeviceSubClass;
+    uint8_t bDeviceProtocol;
+    uint8_t bMaxPacketSize;
+    uint16_t idVendor;
+    uint16_t idProduct;
+    uint16_t bcdDevice;
+    uint8_t iManufacturer;
+    uint8_t iProduct;
+    uint8_t iSerialNumber;
+    uint8_t bNumConfigurations;
+} PACKED DeviceDescriptor;
+
+typedef struct {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint16_t wTotalLength;
+    uint8_t bNumInterfaces;
+    uint8_t bConfigurationValue;
+    uint8_t iConfiguration;
+    uint8_t bmAttributes;
+    uint8_t bMaxPower;
+} PACKED ConfigurationDescriptor;
+
+typedef struct {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bInterfaceNumber;
+    uint8_t bAlternateSetting;
+    uint8_t bNumEndpoints;
+    uint8_t bInterfaceClass;
+    uint8_t bInterfaceSubClass;
+    uint8_t bInterfaceProtocol;
+    uint8_t iInterface;
+} InterfaceDescriptor;
+
+typedef struct {
+    uint8_t bLength;
+    uint8_t bDescriptorType;
+    uint8_t bEndpointAddress;
+    uint8_t bmAttributes;
+    uint16_t wMaxPacketSize;
+    uint8_t bInterval;
+} EndpointDescriptor;
+
+typedef struct {
+    uint8_t bDescLength;
+    uint8_t bDescriptorType;
+    uint8_t bNbrPorts;
+    uint16_t wHubCharacteristics;
+    uint8_t bPwrOn2PwrGood;
+    uint8_t bHubContrCurrent;
+    uint8_t DeviceRemovable;
+    uint8_t PortPweCtrlMak;
+} HubDescriptor;
+
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHost/dbg.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,66 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USB_DEBUG_H
+#define USB_DEBUG_H
+
+//Debug is disabled by default
+#define DEBUG 3 /*INFO,ERR,WARN*/
+#define DEBUG_TRANSFER 0
+#define DEBUG_EP_STATE 0
+#define DEBUG_EVENT 0
+
+#if (DEBUG > 3)
+#define USB_DBG(x, ...) std::printf("[USB_DBG: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG(x, ...)
+#endif
+
+#if (DEBUG > 2)
+#define USB_INFO(x, ...) std::printf("[USB_INFO: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_INFO(x, ...)
+#endif
+
+#if (DEBUG > 1)
+#define USB_WARN(x, ...) std::printf("[USB_WARNING: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_WARN(x, ...)
+#endif
+
+#if (DEBUG > 0)
+#define USB_ERR(x, ...) std::printf("[USB_ERR: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_ERR(x, ...)
+#endif
+
+#if (DEBUG_TRANSFER)
+#define USB_DBG_TRANSFER(x, ...) std::printf("[USB_TRANSFER: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG_TRANSFER(x, ...)
+#endif
+
+#if (DEBUG_EVENT)
+#define USB_DBG_EVENT(x, ...) std::printf("[USB_EVENT: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG_EVENT(x, ...)
+#endif
+
+
+#endif
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHostCam/CamInfo.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,273 @@
+// CamInfo.cpp
+#include "USBHostCam.h"
+
+// Logitech C270
+#define C270_VID 0x046d
+#define C270_PID 0x0825
+#define C270_640x480 1
+#define C270_160x120 2
+#define C270_176x144 3
+#define C270_320x176 4
+#define C270_320x240 5
+#define C270_352x288 6
+#define C270_432x240 7
+#define C270_544x288 8
+#define C270_640x360 9
+//Needs HISPEED USB above 15 fps
+#define C270_752x416 10
+#define C270_800x448 11
+#define C270_800x600 12
+//Needs HISPEED USB
+#define C270_864x480 13
+#define C270_960x544 14
+#define C270_960x720 15
+#define C270_1024x576 16
+#define C270_1184x656 17
+#define C270_1280x720 18
+#define C270_1280x960 19
+
+#define C270_MJPEG 2
+#define C270_YUV2  1
+
+#define C270_EN  0x81
+#define C270_MPS  944
+#define C270_IF_ALT_192 1
+#define C270_IF_ALT_384 2
+#define C270_IF_ALT_512 3
+#define C270_IF_ALT_640 4
+#define C270_IF_ALT_800 5
+#define C270_IF_ALT_944 6
+//Needs HISPEED USB
+#define C270_IF_ALT_2x640  7
+#define C270_IF_ALT_2x800  8
+#define C270_IF_ALT_2x992  9
+#define C270_IF_ALT_3x896  10
+#define C270_IF_ALT_3x1020 11
+#define C270_IF_ALT(A) C270_IF_ALT_##A
+
+#define C270_INFO(SIZE) {C270_VID, C270_PID, _##SIZE, 0, \
+    "C270", \
+    C270_MJPEG, \
+    C270_##SIZE, \
+    _5FPS, \
+    C270_EN, \
+    944, \
+    C270_IF_ALT(944), \
+    4, \
+    3}
+
+#define C210_PID 0x819
+#define C210_INFO(SIZE) {C270_VID, C210_PID, _##SIZE, 0, \
+    "C210", \
+    C270_MJPEG, \
+    C270_##SIZE, \
+    _5FPS, \
+    C270_EN, \
+    192, \
+    C270_IF_ALT(192), \
+    4, \
+    3}
+
+
+// Logitech C170
+//#define C170_VID 0x046d
+#define C170_PID 0x082B
+#define C170_640x480  1
+#define C170_352x288  2
+#define C170_320x240  3
+#define C170_176x144  4
+#define C170_160x120  5
+#define C170_544x288  6
+#define C170_432x240  7
+#define C170_320x176  8
+#define C170_640x360  9
+//Needs HISPEED USB above 15 fps
+#define C170_800x480  10
+//Needs HISPEED USB
+#define C170_1024x768 11
+
+#define C170_EN  0x82
+#define C170_MPS  512
+#define C170_IF_ALT_512    4
+//Needs HISPEED USB
+#define C170_IF_ALT_1024   3
+#define C170_IF_ALT_2x1024 2
+#define C170_IF_ALT_3x1024 1
+#define C170_IF_ALT(A) C170_IF_ALT_##A
+
+#define C170_INFO(SIZE) {C270_VID, C170_PID, _##SIZE, 0, \
+    "C170", \
+    C270_MJPEG, \
+    C170_##SIZE, \
+    _15FPS, \
+    C170_EN, \
+    512, \
+    C170_IF_ALT(512), \
+    4, \
+    3}
+
+// Logitech Qcam Orbit AF QCAM-200R
+#define Q200R_VID 0x046d
+#define Q200R_PID 0x0994
+#define Q200R_160x120 1
+#define Q200R_176x144 2
+#define Q200R_320x240 3
+#define Q200R_352x288 4
+#define Q200R_640x480 5
+#define Q200R_800x600 6
+
+#define Q200R_MJPEG 1
+#define Q200R_YUV2  2
+
+#define Q200R_EN  0x81
+#define Q200R_MPS  192
+#define Q200R_IF_ALT_192 1
+#define Q200R_IF_ALT_384 2
+#define Q200R_IF_ALT_512 3
+#define Q200R_IF_ALT_640 4
+#define Q200R_IF_ALT_800 5
+#define Q200R_IF_ALT_944 6
+#define Q200R_IF_ALT(A) Q200R_IF_ALT_##A
+#define Q200R_INFO(SIZE) {Q200R_VID, Q200R_PID, _##SIZE, 0, \
+    "Q200R", \
+    Q200R_MJPEG, \
+    Q200R_##SIZE, \
+    _5FPS, \
+    Q200R_EN, \
+    192, \
+    Q200R_IF_ALT(192), \
+    4, \
+    3}
+
+//LifeCam VX700 / VX500
+#define VX700_VID 0x045e
+#define VX700_PID 0x074a
+
+#define VX700_160x120 5
+#define VX700_176x144 4
+#define VX700_320x240 3
+#define VX700_352x288 2
+#define VX700_640x480 1
+
+#define VX700_MJPEG 1
+
+#define VX700_EN  0x81
+#define VX700_MPS  128
+#define VX700_IF_ALT_128 1 
+#define VX700_IF_ALT(A) VX700_IF_ALT_##A
+#define VX700_INFO(SIZE) {VX700_VID, VX700_PID, _##SIZE, 0, \
+    "VX700", \
+    VX700_MJPEG, \
+    VX700_##SIZE, \
+    _5FPS, \
+    VX700_EN, \
+    128, \
+    VX700_IF_ALT(128), \
+    4, \
+    3}
+
+//Sonix USB 2.0 Camera
+#define SONIX_160x120 5
+#define SONIX_176x144 4
+#define SONIX_320x240 3
+#define SONIX_352x288 2
+#define SONIX_640x480 1
+
+#define SONIX_IF_ALT_128 1
+#define SONIX_IF_ALT_256 2
+#define SONIX_IF_ALT_512 3
+#define SONIX_IF_ALT_600 4
+#define SONIX_IF_ALT_800 5
+#define SONIX_IF_ALT_956 6
+#define SONIX_IF_ALT(A) SONIX_IF_ALT_##A
+#define SONIX_INFO(SIZE) {0x0c45, 0x62c0, _##SIZE, 0, \
+    "SONIX", \
+    1, \
+    SONIX_##SIZE, \
+    _5FPS, \
+    0x81, \
+    128, \
+    SONIX_IF_ALT(128), \
+    4, \
+    3}
+
+static const CamInfo CamInfoList[] = {
+// Logitech C270
+C270_INFO(640x480),
+C270_INFO(160x120),
+C270_INFO(176x144),
+C270_INFO(320x176),
+C270_INFO(320x240),
+C270_INFO(352x288),
+C270_INFO(432x240),
+C270_INFO(544x288),
+C270_INFO(640x360),
+//Needs HISPEED USB above 15 fps
+C270_INFO(752x416),
+C270_INFO(800x448),
+C270_INFO(800x600),
+//Needs HISPEED USB
+C270_INFO(864x480),
+C270_INFO(960x544),
+C270_INFO(960x720),
+C270_INFO(1024x576),
+C270_INFO(1184x656),
+C270_INFO(1280x720),
+C270_INFO(1280x960),
+
+// Logitech C210
+C210_INFO(160x120),
+C210_INFO(176x144),
+C210_INFO(320x176),
+C210_INFO(320x240),
+C210_INFO(352x288),
+C210_INFO(432x240),
+C210_INFO(640x480),
+C210_INFO(544x288),
+C210_INFO(640x360),
+C210_INFO(752x416),
+C210_INFO(800x448),
+C210_INFO(800x600),
+
+// Logitech C170
+C170_INFO(640x480),
+C170_INFO(352x288),
+C170_INFO(320x240),
+C170_INFO(176x144),
+C170_INFO(160x120),
+C170_INFO(544x288),
+C170_INFO(432x240),
+C170_INFO(320x176),
+C170_INFO(640x360),
+//C170_INFO(800x480),
+//C170_INFO(1024x768),
+
+// Logitech Qcam Orbit AF QCAM-200R
+Q200R_INFO(160x120),
+Q200R_INFO(176x144),
+Q200R_INFO(320x240),
+Q200R_INFO(352x288),
+Q200R_INFO(640x480),
+Q200R_INFO(800x600),
+
+// LifeCam VX700
+VX700_INFO(160x120),
+VX700_INFO(176x144),
+VX700_INFO(320x240),
+VX700_INFO(352x288),
+VX700_INFO(640x480),
+
+// Sonix USB 2.0 Camera
+SONIX_INFO(160x120),
+SONIX_INFO(176x144),
+SONIX_INFO(320x240),
+SONIX_INFO(352x288),
+SONIX_INFO(640x480),
+
+// Not found
+{0,0,0,0},
+};
+
+CamInfo* getCamInfoList() {
+    return const_cast<CamInfo*>(CamInfoList);
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHostCam/USBHostCam.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,179 @@
+// USBHostCam.cpp
+#include "USBHostCam.h"
+#include "dbg.h"
+
+//#define CAM_DEBUG 1
+#ifdef CAM_DEBUG
+#define CAM_DBG(x, ...) std::printf("[%s:%d]"x"\r\n", __PRETTY_FUNCTION__, __LINE__, ##__VA_ARGS__);
+#else
+#define CAM_DBG(...)  while(0);
+#endif
+
+// ------------------ HcControl Register ---------------------
+#define  OR_CONTROL_IE                  0x00000008
+
+CamInfo* getCamInfoList(); // CamInfo.cpp
+
+USBHostCam::USBHostCam(uint8_t size, uint8_t option, CamInfo* user_caminfo)
+{
+    CAM_DBG("size: %d, option: %d", size, option);
+    _caminfo_size = size;
+    _caminfo_option = option;
+    if (user_caminfo) {
+        CamInfoList = user_caminfo;
+    } else {
+        CamInfoList = getCamInfoList();
+    }
+    clearOnResult();
+    host = USBHost::getHostInst();
+    m_isoEp = new IsochronousEp;
+    init();
+}
+
+void USBHostCam::init()
+{
+    CAM_DBG("");
+    dev_connected = false;
+    dev = NULL;
+    cam_intf = -1;
+    device_found = false;
+    caminfo_found = false;
+}
+
+bool USBHostCam::connected()
+{
+    return dev_connected;
+}
+
+bool USBHostCam::plugged()
+{
+    return host->plug_status;
+}
+
+bool USBHostCam::connect()
+{
+    if (dev_connected) {
+        return true;
+    }
+
+    for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+        if ((dev = host->getDevice(i)) != NULL) {
+            
+            CAM_DBG("Trying to connect Cam device\r\n");
+            
+            if(host->enumerate(dev, this)) {
+                break;
+            }
+            if (device_found) {
+                USB_INFO("New Cam: %s device: VID:%04x PID:%04x [dev: %p - intf: %d]", caminfo->name, dev->getVid(), dev->getPid(), dev, cam_intf);
+                dev->setName(caminfo->name, cam_intf);
+                host->registerDriver(dev, cam_intf, this, &USBHostCam::onDisconnect);
+                int addr = dev->getAddress();
+                m_isoEp->init(addr, caminfo->en, caminfo->mps, caminfo->frameCount, caminfo->queueLimit);
+                uint8_t buf[26];
+                memset(buf, 0, sizeof(buf));
+                buf[2] = caminfo->formatIndex;
+                buf[3] = caminfo->frameIndex;
+                *reinterpret_cast<uint32_t*>(buf+4) = caminfo->interval;
+                USB_TYPE res = Control(SET_CUR, VS_COMMIT_CONTROL, 1, buf, sizeof(buf));
+                if (res != USB_TYPE_OK) {
+                    CAM_DBG("SET_CUR VS_COMMIT_CONTROL FAILED");
+                }
+                res = setInterfaceAlternate(1, caminfo->if_alt);
+                if (res != USB_TYPE_OK) {
+                    CAM_DBG("SET_INTERFACE FAILED");
+                }
+                for(int i = 0; i < 16; i++) {
+                    report_cc_count[i] = 0;
+                    report_ps_cc_count[i] = 0;
+                }
+
+                dev_connected = true;
+                return true;
+            }
+        }
+    }
+    init();
+    return false;
+}
+
+void USBHostCam::onDisconnect()
+{
+    CAM_DBG("dev_connected: %d", dev_connected);
+    if (dev_connected) {
+        m_isoEp->disconnect();
+        init();
+    }
+}
+
+/*virtual*/ void USBHostCam::setVidPid(uint16_t vid, uint16_t pid)
+{
+    CAM_DBG("vid:%04x,pid:%04x", vid, pid);
+    caminfo = CamInfoList;
+    while(caminfo->vid != 0) {
+        if (caminfo->vid == vid && caminfo->pid == pid && 
+            caminfo->size == _caminfo_size && caminfo->option == _caminfo_option) {
+            caminfo_found = true;
+            break;
+        }
+        caminfo++;
+    }
+}
+
+/*virtual*/ bool USBHostCam::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+    CAM_DBG("intf_nb=%d,intf_class=%02X,intf_subclass=%d,intf_protocol=%d", intf_nb, intf_class, intf_subclass, intf_protocol);
+    if ((cam_intf == -1) && caminfo_found) {
+        cam_intf = intf_nb;
+        device_found = true;
+        return true;
+    }
+    return false;
+}
+
+/*virtual*/ bool USBHostCam::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+    CAM_DBG("intf_nb:%d,type:%d,dir:%d",intf_nb, type, dir);
+    return false;
+}
+
+#define SEQ_READ_IDOL 0
+#define SEQ_READ_EXEC 1
+#define SEQ_READ_DONE 2
+
+int USBHostCam::readJPEG(uint8_t* buf, int size, int timeout_ms) {
+    _buf = buf;
+    _pos = 0;
+    _size = size;
+    _seq = SEQ_READ_IDOL;
+    setOnResult(this, &USBHostCam::callback_motion_jpeg);
+    Timer timeout_t;
+    timeout_t.reset();
+    timeout_t.start();
+    while(timeout_t.read_ms() < timeout_ms && _seq != SEQ_READ_DONE && connected()) {
+        poll();
+        Thread::wait(1);
+    }
+    return _pos;
+}
+
+/* virtual */ void USBHostCam::outputJPEG(uint8_t c, int status) { // from decodeMJPEG
+    if (_seq == SEQ_READ_IDOL) {
+        if (status == JPEG_START) {
+            _pos = 0;
+            _seq = SEQ_READ_EXEC;
+        }
+    }
+    if (_seq == SEQ_READ_EXEC) {
+        if (_pos < _size) {
+            _buf[_pos++] = c;  
+        }  
+        if (status == JPEG_END) {
+            _seq = SEQ_READ_DONE;
+        }
+    }
+}
+
+void USBHostCam::callback_motion_jpeg(uint16_t frame, uint8_t* buf, int len) {
+        inputPacket(buf, len);
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHostCam/USBHostCam.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,135 @@
+// USBHostCam.h
+#include "USBHostConf.h"
+#include "USBHost.h"
+#include "USBIsochronous.h"
+#include "BaseUvc.h"
+#include "decodeMJPEG.h"
+#pragma once
+
+#define _640x480 1
+#define _160x120 2
+#define _176x144 3
+#define _320x176 4
+#define _320x240 5
+#define _352x288 6
+#define _432x240 7
+#define _544x288 8
+#define _640x360 9
+//
+#define _752x416 10
+#define _800x448 11
+#define _800x600 12
+//
+#define _864x480 13
+#define _960x544 14
+#define _960x720 15
+//
+#define _1024x576 16
+#define _1184x656 17
+#define _1280x720 18
+#define _1280x960 19
+
+/*
+#define _640x480  1
+#define _352x288  2
+#define _320x240  3
+#define _176x144  4
+#define _160x120  5
+#define _544x288  6
+#define _432x240  7
+#define _320x176  8
+#define _640x360  9
+
+#define _800x480  10
+
+#define _1024x768 11
+*/
+
+
+#define TEST_ASSERT(A) while(!(A)){fprintf(stderr,"\n\n%s@%d %s ASSERT!\n\n",__PRETTY_FUNCTION__,__LINE__,#A);exit(1);};
+
+struct CamInfo {
+    uint16_t vid;
+    uint16_t pid;
+    uint8_t size;
+    uint8_t option;
+//
+    const char* name;
+    uint8_t formatIndex;
+    uint8_t frameIndex;
+    uint32_t interval;
+    uint8_t en;
+    uint16_t mps;
+    uint8_t if_alt;
+    uint8_t frameCount; // ITD frame count 1-8
+    uint8_t queueLimit; // ITD queue limit 1-3
+};
+
+/** 
+ * A class to communicate a Cam
+ */
+class USBHostCam : public IUSBEnumerator, public BaseUvc, public decodeMJPEG {
+public:
+    /**
+    * Constructor
+    *
+    */
+    USBHostCam(uint8_t size = _160x120, uint8_t option = 0, CamInfo* user_caminfo = NULL);
+
+    /**
+    * Check if a Cam device is connected
+    *
+    * @return true if a Cam device is connected
+    */
+    bool connected();
+
+    /**
+    * Check if a usb connector is plugged
+    *
+    * @return true if a connector is plugged
+    */
+    bool plugged();
+
+    /**
+     * Try to connect to a Cam device
+     *
+     * @return true if connection was successful
+     */
+    bool connect();
+
+    /**
+     * read jpeg image
+     *
+     * @param buf read buffer 
+     * @param size buffer size 
+     * @param timeout_ms timeout default 15sec
+     * @return jpeg size if read success else -1
+     */
+    int readJPEG(uint8_t* buf, int size, int timeout_ms = 15*1000);
+
+protected:
+    //From IUSBEnumerator
+    virtual void setVidPid(uint16_t vid, uint16_t pid);
+    virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+    virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+    bool dev_connected;
+
+    int cam_intf;
+    bool device_found;
+    bool caminfo_found;
+    uint8_t _seq;
+    uint8_t* _buf;
+    int _pos;
+    int _size;
+    CamInfo* CamInfoList;
+    CamInfo* caminfo;
+    uint8_t _caminfo_size;
+    uint8_t _caminfo_option;
+
+    virtual void outputJPEG(uint8_t c, int status); // from decodeMJPEG
+    void callback_motion_jpeg(uint16_t frame, uint8_t* buf, int len);
+    void init();
+    void onDisconnect();
+};
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHostHub/USBHostHub.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,274 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostHub.h"
+
+#if MAX_HUB_NB
+
+#include "USBHost.h"
+#include "dbg.h"
+
+#define GET_STATUS 0x00
+#define CLEAR_FEATURE 0x01
+#define GET_STATE 0x02
+#define SET_FEATURE 0x03
+#define GET_DESCRIPTOR 0x06
+
+#define PORT_CONNECTION_FEATURE     (0x00)
+#define PORT_ENABLE_FEATURE         (0x01)
+#define PORT_RESET_FEATURE          (0x04)
+#define PORT_POWER_FEATURE          (0x08)
+
+#define C_PORT_CONNECTION_FEATURE     (16)
+#define C_PORT_ENABLE_FEATURE         (17)
+#define C_PORT_RESET_FEATURE          (20)
+
+#define PORT_CONNECTION   (1 << 0)
+#define PORT_ENABLE       (1 << 1)
+#define PORT_SUSPEND      (1 << 2)
+#define PORT_OVER_CURRENT (1 << 3)
+#define PORT_RESET        (1 << 4)
+#define PORT_POWER        (1 << 8)
+#define PORT_LOW_SPEED    (1 << 9)
+
+#define C_PORT_CONNECTION   (1 << 16)
+#define C_PORT_ENABLE       (1 << 17)
+#define C_PORT_SUSPEND      (1 << 18)
+#define C_PORT_OVER_CURRENT (1 << 19)
+#define C_PORT_RESET        (1 << 20)
+
+USBHostHub::USBHostHub() {
+    host = NULL;
+    init();
+}
+
+void USBHostHub::init() {
+    dev_connected = false;
+    dev = NULL;
+    int_in = NULL;
+    dev_connected = false;
+    hub_intf = -1;
+    hub_device_found = false;
+    nb_port = 0;
+    hub_characteristics = 0;
+
+    for (int i = 0; i < MAX_HUB_PORT; i++) {
+        device_children[i] = NULL;
+    }
+}
+
+void USBHostHub::setHost(USBHost * host_) {
+    host = host_;
+}
+
+bool USBHostHub::connected()
+{
+    return dev_connected;
+}
+
+bool USBHostHub::connect(USBDeviceConnected * dev)
+{
+    if (dev_connected) {
+        return true;
+    }
+
+    if(host->enumerate(dev, this)) {
+        init();
+        return false;
+    }
+
+    if (hub_device_found) {
+        this->dev = dev;
+
+        int_in = dev->getEndpoint(hub_intf, INTERRUPT_ENDPOINT, IN);
+
+        if (!int_in) {
+            init();
+            return false;
+        }
+
+        USB_INFO("New HUB: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, hub_intf);
+        dev->setName("Hub", hub_intf);
+        host->registerDriver(dev, hub_intf, this, &USBHostHub::disconnect);
+
+        int_in->attach(this, &USBHostHub::rxHandler);
+
+        // get HUB descriptor
+        host->controlRead(  dev,
+                            USB_DEVICE_TO_HOST | USB_REQUEST_TYPE_CLASS,
+                            GET_DESCRIPTOR,
+                            0x29 << 8, 0, buf, sizeof(HubDescriptor));
+        nb_port = buf[2];
+        hub_characteristics = buf[3];
+
+        USB_DBG("Hub has %d port", nb_port);
+
+        for (uint8_t j = 1; j <= nb_port; j++) {
+            setPortFeature(PORT_POWER_FEATURE, j);
+        }
+        wait_ms(buf[5]*2);
+
+        host->interruptRead(dev, int_in, buf, 1, false);
+        dev_connected = true;
+        return true;
+    }
+
+    return false;
+}
+
+void USBHostHub::disconnect() {
+    init();
+}
+
+/*virtual*/ void USBHostHub::setVidPid(uint16_t vid, uint16_t pid)
+{
+    // we don't check VID/PID for MSD driver
+}
+
+/*virtual*/ bool USBHostHub::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+    if ((hub_intf == -1) &&
+        (intf_class == HUB_CLASS) &&
+        (intf_subclass == 0) &&
+        (intf_protocol == 0)) {
+        hub_intf = intf_nb;
+        return true;
+    }
+    return false;
+}
+
+/*virtual*/ bool USBHostHub::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+    if (intf_nb == hub_intf) {
+        if ((type == INTERRUPT_ENDPOINT) && (dir == IN)) {
+            hub_device_found = true;
+            return true;
+        }
+    }
+    return false;
+}
+
+void USBHostHub::deviceConnected(USBDeviceConnected * dev) {
+    device_children[dev->getPort() - 1] = dev;
+}
+
+void USBHostHub::deviceDisconnected(USBDeviceConnected * dev) {
+    device_children[dev->getPort() - 1] = NULL;
+}
+
+void USBHostHub::hubDisconnected() {
+    for (uint8_t i = 0; i < MAX_HUB_PORT; i++) {
+        if (device_children[i] != NULL) {
+            host->freeDevice(device_children[i]);
+        }
+    }
+}
+
+void USBHostHub::rxHandler() {
+    uint32_t status;
+    if (int_in) {
+        if (int_in->getState() == USB_TYPE_IDLE) {
+            for (int port = 1; port <= nb_port; port++) {
+                status = getPortStatus(port);
+                USB_DBG("[hub handler hub: %d] status port %d [hub: %p]: 0x%X", dev->getHub(), port, dev, status);
+
+                // if connection status has changed
+                if (status & C_PORT_CONNECTION) {
+                    if (status & PORT_CONNECTION) {
+                        USB_DBG("[hub handler hub: %d - port: %d] new device connected", dev->getHub(), port);
+                        host->deviceConnected(dev->getHub() + 1, port, status & PORT_LOW_SPEED, this);
+                    } else {
+                        USB_DBG("[hub handler hub: %d - port: %d] device disconnected", dev->getHub(), port);
+                        host->deviceDisconnected(dev->getHub() + 1, port, this, 0);
+                    }
+
+                    clearPortFeature(C_PORT_CONNECTION_FEATURE, port);
+                }
+
+                if (status & C_PORT_RESET) {
+                    clearPortFeature(C_PORT_RESET_FEATURE, port);
+                }
+
+                if (status & C_PORT_ENABLE) {
+                    clearPortFeature(C_PORT_ENABLE_FEATURE, port);
+                }
+
+                if ((status & PORT_OVER_CURRENT)) {
+                    USB_ERR("OVER CURRENT DETECTED\r\n");
+                    clearPortFeature(PORT_OVER_CURRENT, port);
+                    host->deviceDisconnected(dev->getHub() + 1, port, this, 0);
+                }
+            }
+        }
+        host->interruptRead(dev, int_in, buf, 1, false);
+    }
+}
+
+void USBHostHub::portReset(uint8_t port) {
+    // reset port
+    uint32_t status;
+    USB_DBG("reset port %d on hub: %p [this: %p]", port, dev, this)
+    setPortFeature(PORT_RESET_FEATURE, port);
+#if defined(TARGET_RZ_A1H)
+    Thread::wait(50);   // Reset release waiting for Hi-Speed check.
+#endif
+    while(1) {
+        status = getPortStatus(port);
+        if (status & (PORT_ENABLE | PORT_RESET))
+            break;
+        if (status & PORT_OVER_CURRENT) {
+            USB_ERR("OVER CURRENT DETECTED\r\n");
+            clearPortFeature(PORT_OVER_CURRENT, port);
+            host->deviceDisconnected(dev->getHub() + 1, port, this, 0);
+            break;
+        }
+        Thread::wait(10);
+    }
+}
+
+void USBHostHub::setPortFeature(uint32_t feature, uint8_t port) {
+    host->controlWrite( dev,
+                        USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE | USB_RECIPIENT_ENDPOINT,
+                        SET_FEATURE,
+                        feature,
+                        port,
+                        NULL,
+                        0);
+}
+
+void USBHostHub::clearPortFeature(uint32_t feature, uint8_t port) {
+    host->controlWrite( dev,
+                        USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE | USB_RECIPIENT_ENDPOINT,
+                        CLEAR_FEATURE,
+                        feature,
+                        port,
+                        NULL,
+                        0);
+}
+
+uint32_t USBHostHub::getPortStatus(uint8_t port) {
+    uint32_t st;
+    host->controlRead(  dev,
+                        USB_DEVICE_TO_HOST | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE | USB_RECIPIENT_ENDPOINT,
+                        GET_STATUS,
+                        0,
+                        port,
+                        (uint8_t *)&st,
+                        4);
+    return st;
+}
+
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBHostHub/USBHostHub.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,125 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTHUB_H
+#define USBHOSTHUB_H
+
+#include "USBHostConf.h"
+
+#if MAX_HUB_NB
+
+#include "USBHostTypes.h"
+#include "IUSBEnumerator.h"
+
+class USBHost;
+class USBDeviceConnected;
+class USBEndpoint;
+
+/**
+ * A class to use a USB Hub
+ */
+class USBHostHub : public IUSBEnumerator {
+public:
+    /**
+    * Constructor
+    */
+    USBHostHub();
+
+    /**
+    * Check if a USB Hub is connected
+    *
+    * @return true if a serial device is connected
+    */
+    bool connected();
+
+    /**
+     * Try to connect device
+     *
+     * @param dev device to connect
+     * @return true if connection was successful
+     */
+    bool connect(USBDeviceConnected * dev);
+
+    /**
+    * Automatically called by USBHost when a device
+    * has been enumerated by usb_thread
+    *
+    * @param dev device connected
+    */
+    void deviceConnected(USBDeviceConnected * dev);
+
+    /**
+    * Automatically called by USBHost when a device
+    * has been disconnected from this hub
+    *
+    * @param dev device disconnected
+    */
+    void deviceDisconnected(USBDeviceConnected * dev);
+
+    /**
+    * Rest a specific port
+    *
+    * @param port port number
+    */
+    void portReset(uint8_t port);
+
+    /*
+    * Called by USBHost to set the instance of USBHost
+    *
+    * @param host host instance
+    */
+    void setHost(USBHost * host);
+
+    /**
+    * Called by USBhost when a hub has been disconnected
+    */
+    void hubDisconnected();
+
+protected:
+    //From IUSBEnumerator
+    virtual void setVidPid(uint16_t vid, uint16_t pid);
+    virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+    virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+    USBHost * host;
+    USBDeviceConnected * dev;
+    bool dev_connected;
+    USBEndpoint * int_in;
+    uint8_t nb_port;
+    uint8_t hub_characteristics;
+
+    void rxHandler();
+
+    uint8_t buf[sizeof(HubDescriptor)];
+
+    int hub_intf;
+    bool hub_device_found;
+
+    void setPortFeature(uint32_t feature, uint8_t port);
+    void clearPortFeature(uint32_t feature, uint8_t port);
+    uint32_t getPortStatus(uint8_t port);
+
+    USBDeviceConnected * device_children[MAX_HUB_PORT];
+
+    void init();
+    void disconnect();
+
+};
+
+#endif
+
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBisochronous/USBIsochronous.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,225 @@
+// USBIsochronous.cpp
+#include "USBHostConf.h"
+#include "USBHost.h"
+#include "USBIsochronous.h"
+#if (defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H))
+#include "ohci_wrapp_RZ_A1.h"
+#endif
+
+#define  OR_CONTROL_PLE                 0x00000004
+#define  OR_CONTROL_IE                  0x00000008
+
+//#define ISO_DEBUG 1
+#ifdef ISO_DEBUG
+#define ISO_DBG(x, ...) std::printf("[%s:%d]"x"\r\n", __PRETTY_FUNCTION__, __LINE__, ##__VA_ARGS__);
+#else
+#define ISO_DBG(...)  while(0);
+#endif
+
+#define TEST_ASSERT(A) while(!(A)){fprintf(stderr,"\n\n%s@%d %s ASSERT!\n\n",__PRETTY_FUNCTION__,__LINE__,#A);exit(1);};
+
+HCITD::HCITD(IsochronousEp* obj, uint16_t FrameNumber, int FrameCount, uint16_t PacketSize) {
+    Control = 0xe0000000           | // CC ConditionCode NOT ACCESSED
+             ((FrameCount-1) << 24)| // FC FrameCount
+                  TD_DELAY_INT(0)  | // DI DelayInterrupt
+                 FrameNumber;        // SF StartingFrame
+    BufferPage0 = const_cast<uint8_t*>(buf);
+    BufferEnd = const_cast<uint8_t*>(buf) + PacketSize * FrameCount - 1;
+    Next = NULL; 
+    ep = obj;
+    uint32_t addr = reinterpret_cast<uint32_t>(buf);
+    for(int i = 0; i < FrameCount; i++) {
+        uint16_t offset = addr & 0x0fff;
+        if ((addr&0xfffff000) == (reinterpret_cast<uint32_t>(BufferEnd)&0xfffff000)) {
+            offset |= 0x1000;
+        }
+        OffsetPSW[i] = 0xe000|offset;
+        addr += PacketSize;
+    }
+}
+
+void IsochronousEp::init(int addr, uint8_t ep, uint16_t size, uint8_t frameCount, uint8_t queueLimit) {
+    //ISO_DBG("%p FA:%d EP:%02X MPS:%d\n", this, addr, ep, size);
+    TEST_ASSERT(addr >= 1);    
+    TEST_ASSERT(size >= 8 && size <= 1023);
+    m_pED  = new _HCED(addr, ep, size);
+    TEST_ASSERT(m_pED);
+
+    m_pED->setFormat(); // F Format ITD
+
+    m_PacketSize = size;
+    TEST_ASSERT(frameCount >= 1 && frameCount <= 8);
+    m_FrameCount = frameCount;
+    TEST_ASSERT(queueLimit >= 1 && queueLimit <= HCITD_QUEUE_SIZE);
+    m_itd_queue_limit = queueLimit;
+
+    m_itd_queue_count = 0;
+    reset();
+    HCITD* itd = new_HCITD(this);
+    m_pED->init_queue<HCITD>(itd); 
+    TEST_ASSERT(itd);
+    if (itd == NULL) {
+        return;
+    }
+#if defined(TARGET_LPC1768)
+    _HCCA* hcca = reinterpret_cast<_HCCA*>(LPC_USB->HcHCCA);
+#elif (defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H))
+    _HCCA* hcca = reinterpret_cast<_HCCA*>(ohciwrapp_reg_r(OHCI_REG_HCCA));
+#endif
+    TEST_ASSERT(hcca);
+    if (hcca == NULL) {
+        return;
+    }
+    hcca->enqueue(m_pED);
+}
+
+void IsochronousEp::reset(int delay_ms)
+{
+#if defined(TARGET_LPC1768)
+    m_FrameNumber = LPC_USB->HcFmNumber + delay_ms;
+#elif (defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H))
+    m_FrameNumber = ohciwrapp_reg_r(OHCI_REG_FMNUMBER) + delay_ms;
+#endif
+}
+
+HCITD* IsochronousEp::new_HCITD(IsochronousEp* obj) {
+    HCITD* itd = new(m_PacketSize*m_FrameCount)HCITD(obj, 0, m_FrameCount, m_PacketSize);
+    if (itd == NULL) {
+        return NULL;
+    } 
+    return itd;
+}
+
+HCITD* IsochronousEp::isochronousReceive(int timeout_ms) {
+    TEST_ASSERT(m_itd_queue_count >= 0);
+    while(m_itd_queue_count < m_itd_queue_limit) {
+        if (m_pED == NULL) {
+            ISO_DBG("m_pED is NULL");
+            break;
+        }
+        if (m_pED->Skip()) {
+            break;
+        }
+        HCITD* blank_itd = new_HCITD(this);
+        ((HCITD *)m_pED->TailTd)->SetStartingFrame(m_FrameNumber);
+        m_FrameNumber += m_FrameCount;
+        TEST_ASSERT(blank_itd);
+        if (m_pED->enqueue<HCITD>(blank_itd)) {
+            m_itd_queue_count++;
+        }
+        enable(); // Enable Periodic
+    }
+
+    HCITD* itd = get_queue_HCITD(timeout_ms);
+    if (itd) {
+        m_itd_queue_count--;
+    }
+    return itd;
+}
+
+int IsochronousEp::isochronousSend(uint8_t* buf, int len, int timeout_ms) {
+    //ISO_DBG("buf: %p, len: %d", buf, len);
+    HCITD* itd;
+
+    if (m_itd_queue_count >= m_itd_queue_limit) {
+        itd = get_queue_HCITD(timeout_ms);
+    } else {
+        itd = get_queue_HCITD(0);
+    }
+    if (itd) {
+        delete itd;
+        m_itd_queue_count--;
+        TEST_ASSERT(m_itd_queue_count >= 0);
+    }
+    TEST_ASSERT(m_itd_queue_count >= 0);
+    if(m_itd_queue_count < m_itd_queue_limit) {
+        if (m_pED == NULL) {
+            ISO_DBG("m_pED is NULL");
+            return 0;
+        }
+        if (m_pED->Skip()) {
+            return 0;
+        }
+        itd = new_HCITD(this);
+        TEST_ASSERT(itd);
+        //ISO_DBG("m_pED: %p itd: %p", m_pED, itd);
+        ((HCITD *)m_pED->TailTd)->SetStartingFrame(m_FrameNumber);
+        m_FrameNumber += m_FrameCount;
+        memcpy(const_cast<uint8_t*>(((HCITD *)m_pED->TailTd)->buf), buf, len);
+        if (m_pED->enqueue<HCITD>(itd)) {
+            m_itd_queue_count++;
+        }
+        enable(); // Enable Periodic
+        //ISO_DBG("m_itd_queue_count: %d", m_itd_queue_count);
+        return len;
+    }
+    return 0;
+}
+
+HCITD* IsochronousEp::get_queue_HCITD(int timeout_ms) {
+    osEvent evt = m_queue.get(timeout_ms);
+    if (evt.status == osEventMessage) {
+        HCITD* itd = reinterpret_cast<HCITD*>(evt.value.p);
+        TEST_ASSERT(itd);
+        return itd;
+    }
+    return NULL;
+}
+
+void IsochronousEp::enable() {
+#if defined(TARGET_LPC1768)
+    LPC_USB->HcControl |= (OR_CONTROL_PLE | OR_CONTROL_IE);
+#elif (defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H))
+    uint32_t data;
+
+    data = ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_PLE | OR_CONTROL_IE;
+    ohciwrapp_reg_w(OHCI_REG_CONTROL, data);
+#endif
+}
+
+void IsochronousEp::disconnect() {
+    m_pED->setSkip(); // skip bit on
+    ISO_DBG("rtos-queue: %d", m_itd_queue_count);
+    int queue_count = m_itd_queue_count;
+    Timer t;
+    t.reset();
+    t.start();
+    do {
+        HCITD* itd = get_queue_HCITD(10);
+        if (itd) {
+            ISO_DBG("delete ITD:%p from rtos-queue %d ms", itd, t.read_ms());
+            delete itd;
+            queue_count--;
+            t.reset();
+        }
+    } while(t.read_ms() < 50);
+    ISO_DBG("rtos-queue: %d, %d ms", queue_count, t.read_ms());
+    TEST_ASSERT(queue_count >= 0);
+    while(1) {
+        HCITD* itd = m_pED->dequeue<HCITD>();
+        if (itd == NULL) {
+            break;
+        }
+        ISO_DBG("delete ITD:%p from ED(%p)-queue", itd, m_pED);        
+        delete itd;
+        TEST_ASSERT(queue_count > 0);
+        queue_count--;
+    }            
+    TEST_ASSERT(queue_count == 0);
+    HCITD* tail = reinterpret_cast<HCITD*>(m_pED->TailTd);
+    ISO_DBG("delete ITD:%p from ED(%p)-tail", tail, m_pED);
+    TEST_ASSERT(tail);
+    delete tail;
+    m_pED->init_queue<HCITD>(NULL);
+    
+#if defined(TARGET_LPC1768)
+    _HCCA* hcca = reinterpret_cast<_HCCA*>(LPC_USB->HcHCCA);
+#elif (defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H))
+    _HCCA* hcca = reinterpret_cast<_HCCA*>(ohciwrapp_reg_r(OHCI_REG_HCCA));
+#endif
+    TEST_ASSERT(hcca);
+    hcca->dequeue(m_pED);
+    ISO_DBG("delete ED:%p", m_pED);
+    delete m_pED;
+    m_pED = NULL;
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/USBisochronous/USBIsochronous.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,249 @@
+// USBIsochronous.h
+#pragma once
+#if !defined (__CC_ARM) && (!defined (_POSIX_C_SOURCE) || (_POSIX_C_SOURCE < 200112L))
+#if defined(__ICCARM__)
+#include <iar_dlmalloc.h>
+#define memalign   __iar_dlmemalign
+#else
+#include <malloc.h>
+#endif
+#endif
+
+class IsochronousEp;
+struct HCITD {    // HostController Isochronous Transfer Descriptor
+    __IO uint32_t Control;      // +0 Transfer descriptor control
+    uint8_t*  BufferPage0;      // +4 Buffer Page 0
+    HCITD* Next;                // +8 Physical pointer to next Isochronous Transfer Descriptor
+    uint8_t*  BufferEnd;        // +12 buffer End
+    __IO uint16_t OffsetPSW[8]; // +16 Offset/PSW
+    IsochronousEp* ep;          // +32 endpoint object
+    uint8_t*  buf;              // +36 buffer
+                                // +40
+    HCITD(IsochronousEp* obj, uint16_t FrameNumber, int FrameCount, uint16_t PacketSize);
+    inline void* operator new(size_t size, int buf_size) {
+        void* p;
+        struct HCITD * wk_hcitd;
+        void* q;
+#if !defined (__CC_ARM) && (!defined (_POSIX_C_SOURCE) || (_POSIX_C_SOURCE < 200112L))
+        p = memalign(0x20, size);
+        if (p != NULL) {
+            q = memalign(0x1000, buf_size);
+            if (q != NULL) {
+                wk_hcitd = (struct HCITD *)p;
+                wk_hcitd->buf = (uint8_t*)q;
+            } else {
+                free(p);
+                p = NULL;
+            }
+        }
+        return p;
+#else
+        if (posix_memalign(&p, 0x20, size) == 0) {
+            if (posix_memalign(&q, 0x1000, buf_size) == 0) {
+                wk_hcitd = (struct HCITD *)p;
+                wk_hcitd->buf = (uint8_t*)q;
+            } else {
+                free(p);
+                p = NULL;
+            }
+            return p;
+        }
+        return NULL;
+#endif
+    }
+
+    inline void operator delete(void* p) {
+        struct HCITD * wk_hcitd = (struct HCITD *)p;
+        free((void *)wk_hcitd->buf);
+        free(p);
+    }
+
+    inline uint16_t StartingFrame() {
+        return Control & 0xffff;
+    }
+
+    inline void SetStartingFrame(uint16_t FrameNumber) {
+        Control = (Control & 0xffff0000) | FrameNumber;
+    }
+
+    inline uint8_t FrameCount() {
+        return ((Control>>24)&7)+1;
+    }    
+
+    inline uint8_t ConditionCode() {
+        return Control>>28;
+    }
+};
+
+struct _HCED {    // HostController EndPoint Descriptor
+    __IO uint32_t Control; // +0 Endpoint descriptor control
+    HCTD* TailTd;          // +4 Physical address of tail in Transfer descriptor list
+    __IO HCTD* HeadTd;     // +8 Physcial address of head in Transfer descriptor list
+    _HCED* Next;           // +12 Physical address of next Endpoint descriptor
+                           // +16
+    _HCED(int addr, uint8_t ep, uint16_t size, int lowSpeed = 0) {
+        Control =  addr            | /* USB address */
+        ((ep & 0x7F) << 7)         | /* Endpoint address */
+        (ep!=0?(((ep&0x80)?2:1) << 11):0)| /* direction : Out = 1, 2 = In */
+        ((lowSpeed?1:0) << 13)     | /* speed full=0 low=1 */
+        (size << 16);                /* MaxPkt Size */
+        Next = NULL;
+    }
+
+    inline void* operator new(size_t size) {
+        void* p;
+#if !defined (__CC_ARM) && (!defined (_POSIX_C_SOURCE) || (_POSIX_C_SOURCE < 200112L))
+        p = memalign(16, size);
+        return p;
+#else
+        if (posix_memalign(&p, 16, size) == 0) {
+            return p;
+        }
+        return NULL;
+#endif
+    }
+
+    inline void operator delete(void* p) {
+        free(p);
+    }
+
+    inline uint8_t FunctionAddress() {
+        return Control & 0x7f;
+    }
+
+    inline int Speed() {
+        return (Control>>13)&1;
+    }
+
+    inline void setFunctionAddress(int addr) {
+        Control &= ~0x7f;
+        Control |= addr;
+    }
+
+    inline void setMaxPacketSize(uint16_t size) {
+        Control &= ~0xffff0000;
+        Control |= size<<16;
+    }
+
+    int Skip() {
+        return (Control>>14) & 1;
+    }
+
+    void setSkip() {
+        Control |= (1<<14);
+    }
+
+    void setFormat() {
+        Control |= (1<<15);
+    }
+
+    template<typename T>
+    inline bool enqueue(T* td) {
+        if (td) {
+            T* tail = reinterpret_cast<T*>(TailTd);
+            if (tail) {
+                tail->Next = td;
+                TailTd = reinterpret_cast<HCTD*>(td);
+                return true;
+            }
+        }
+        return false;
+    }
+
+    template<typename T>
+    inline T* dequeue() {
+        T* head = reinterpret_cast<T*>(reinterpret_cast<uint32_t>(HeadTd)&~3); // delete Halted and Toggle Carry bit
+        T* tail = reinterpret_cast<T*>(TailTd);
+        if (head == NULL || tail == NULL || head == tail) {
+            return NULL;
+        }
+        HeadTd = reinterpret_cast<HCTD*>(head->Next);
+        return head;
+    }
+    template<typename T>
+    void init_queue(T* td) {
+        TailTd = reinterpret_cast<HCTD*>(td);
+        HeadTd = reinterpret_cast<HCTD*>(td); 
+    }
+};
+
+struct _HCCA {    // Host Controller Communication Area
+    _HCED* InterruptTable[32]; // +0 Interrupt Table
+    __IO uint16_t FrameNumber;// +128 Frame Number
+    __IO uint16_t Pad1;       // +130
+    __IO HCTD* DoneHead;      // +132 Done Head
+    uint8_t Reserved[116];    // +136 Reserved for future use
+    uint8_t Unknown[4];       // +252 Unused
+                              // +256
+    inline void* operator new(size_t size) {
+        void* p;
+#if !defined (__CC_ARM) && (!defined (_POSIX_C_SOURCE) || (_POSIX_C_SOURCE < 200112L))
+        p = memalign(256, size);
+        return p;
+#else
+        if (posix_memalign(&p, 256, size) == 0) {
+            return p;
+        }
+        return NULL;
+#endif
+    }
+
+    inline void operator delete(void* p) {
+        free(p);
+    }
+    
+    inline void enqueue(_HCED* ed) {
+        for(int i = 0; i < 32; i++) {
+            if (InterruptTable[i] == NULL) {
+                InterruptTable[i] = ed;
+            } else {
+                _HCED* nextEd = InterruptTable[i];
+                while(nextEd->Next && nextEd->Next != ed) {
+                    nextEd = nextEd->Next;
+                }
+                nextEd->Next = ed;
+            }
+        }
+    }
+    
+    inline void dequeue(_HCED* ed) {
+         for(int i = 0; i < 32; i++) {
+            if (InterruptTable[i] == ed) {
+                InterruptTable[i] = ed->Next;
+            } else if (InterruptTable[i]) {
+                _HCED* nextEd = InterruptTable[i];
+                while(nextEd) {
+                    if (nextEd->Next == ed) {
+                        nextEd->Next = ed->Next;
+                        break;
+                    }
+                    nextEd = nextEd->Next;
+                }
+            }
+         }
+    }
+};
+
+#define HCITD_QUEUE_SIZE 24
+
+class IsochronousEp {
+public:
+    void init(int addr, uint8_t ep, uint16_t size, uint8_t frameCount = 4, uint8_t queueLimit = 3);
+    void reset(int delay_ms = 100);
+    HCITD* isochronousReceive(int timeout_ms);
+    int isochronousSend(uint8_t* buf, int len, int timeout_ms);
+    HCITD* get_queue_HCITD(int timeout_ms);
+    uint16_t m_PacketSize;
+    void disconnect();
+    void irqWdhHandler(HCITD* itd) {m_queue.put(itd);} // WDH
+    int getQueueNum() {return m_itd_queue_count;}
+private:
+    HCITD* new_HCITD(IsochronousEp* obj);
+    Queue<HCITD, HCITD_QUEUE_SIZE> m_queue; // ITD done queue
+    int m_itd_queue_count;
+    int m_itd_queue_limit;
+    uint16_t m_FrameNumber;
+    int m_FrameCount; // 1-8
+    void enable();
+    _HCED* m_pED;
+};
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/uvc/BaseUvc.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,74 @@
+// BaseUvc.cpp
+#include "USBHostConf.h"
+#include "USBHost.h"
+#include "USBIsochronous.h"
+#include "BaseUvc.h"
+
+void BaseUvc::poll(int millisec)
+{
+    HCITD* itd = m_isoEp->isochronousReceive(millisec);
+    if (itd) {
+        uint8_t cc = itd->ConditionCode();
+        report_cc_count[cc]++;
+        if (cc == 0) {
+            uint16_t frame = itd->StartingFrame();
+            int fc = itd->FrameCount();
+            uint8_t* buf = const_cast<uint8_t*>(itd->buf); 
+            int mps = m_isoEp->m_PacketSize;
+            for(int i = 0; i < fc; i++) {
+                uint16_t psw = itd->OffsetPSW[i];
+                cc = psw>>12;
+                if (cc == 0 || cc == 9) {
+                    int len = psw & 0x7ff;
+                    onResult(frame, buf, len);
+               }
+               report_ps_cc_count[cc]++;
+               buf += mps;
+               frame++;
+            }
+        }
+        delete itd;
+    }
+}
+
+USB_TYPE BaseUvc::Control(int req, int cs, int index, uint8_t* buf, int size)
+{
+    if (req == SET_CUR) {    
+        return host->controlWrite(dev,
+                    USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE, 
+                    req, cs<<8, index, buf, size);
+    }
+    return host->controlRead(dev,
+                USB_DEVICE_TO_HOST | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE, 
+                req, cs<<8, index, buf, size);
+}
+
+USB_TYPE BaseUvc::setInterfaceAlternate(uint8_t intf, uint8_t alt)
+{
+    return host->controlWrite(dev, USB_HOST_TO_DEVICE | USB_RECIPIENT_INTERFACE,
+                                   SET_INTERFACE, alt, intf, NULL, 0);
+}
+
+void BaseUvc::onResult(uint16_t frame, uint8_t* buf, int len)
+{
+  if(m_pCbItem && m_pCbMeth)
+    (m_pCbItem->*m_pCbMeth)(frame, buf, len);
+  else if(m_pCb)
+    m_pCb(frame, buf, len);
+}
+
+void BaseUvc::setOnResult( void (*pMethod)(uint16_t, uint8_t*, int) )
+{
+    m_pCb = pMethod;
+    m_pCbItem = NULL;
+    m_pCbMeth = NULL;
+}
+    
+void BaseUvc::clearOnResult()
+{
+    m_pCb = NULL;
+    m_pCbItem = NULL;
+    m_pCbMeth = NULL;
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/uvc/BaseUvc.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,52 @@
+// BaseUvc.h
+#include "USBIsochronous.h"
+#pragma once
+
+// --- UVC --------------------------------------------------
+#define _30FPS  333333
+#define _25FPS  400000
+#define _20FPS  500000
+#define _15FPS  666666
+#define _10FPS 1000000
+#define _5FPS  2000000
+#define _1FPS 10000000
+
+#define SET_CUR  0x01
+#define GET_CUR  0x81
+#define GET_MIN  0x82
+#define GET_MAX  0x83
+#define GET_RES  0x84
+#define GET_LEN  0x85
+#define GET_INFO 0x86
+#define GET_DEF  0x87
+
+#define VS_PROBE_CONTROL  0x01
+#define VS_COMMIT_CONTROL 0x02
+
+class BaseUvc {
+public:
+    void poll(int millisec = 0);
+    USB_TYPE Control(int req, int cs, int index, uint8_t* buf, int size);
+    USB_TYPE setInterfaceAlternate(uint8_t intf, uint8_t alt);
+    IsochronousEp* m_isoEp;
+    uint32_t report_cc_count[16];  // ConditionCode
+    uint32_t report_ps_cc_count[16]; // Packt Status ConditionCode
+    // callback
+    void onResult(uint16_t frame, uint8_t* buf, int len);
+    void setOnResult( void (*pMethod)(uint16_t, uint8_t*, int) );
+    class CDummy;
+    template<class T> 
+    void setOnResult( T* pItem, void (T::*pMethod)(uint16_t, uint8_t*, int) )
+    {
+        m_pCb = NULL;
+        m_pCbItem = (CDummy*) pItem;
+        m_pCbMeth = (void (CDummy::*)(uint16_t, uint8_t*, int)) pMethod;
+    }
+    void clearOnResult();
+    CDummy* m_pCbItem;
+    void (CDummy::*m_pCbMeth)(uint16_t, uint8_t*, int);
+    void (*m_pCb)(uint16_t, uint8_t*, int);
+protected:
+    USBHost * host;
+    USBDeviceConnected * dev;
+};
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/uvc/decodeMJPEG.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,180 @@
+// decodeMJPEG.cpp 2012/12/8
+// decode motion-jpeg to jpeg
+#include "mbed.h"
+#include "decodeMJPEG.h"
+
+#define MARK_SOF0 0xc0
+#define MARK_DHT  0xc4
+#define MARK_RST0 0xd0
+#define MARK_RST7 0xd7
+#define MARK_SOI  0xd8
+#define MARK_EOI  0xd9
+#define MARK_SOS  0xda
+#define MARK_DQT  0xdb
+#define MARK_DRI  0xdd
+#define MARK_APP  0xe0
+ 
+#define SEQ_INIT      0
+#define SEQ_SOI       1
+#define SEQ_FRAME     2
+#define SEQ_MARK      3
+#define SEQ_SEG_LEN   4
+#define SEQ_SEG_LEN2  5
+#define SEQ_SEG_BODY  6
+#define SEQ_SOS       7
+#define SEQ_SOS2      8
+
+static const uint8_t dht[] = {
+0xFF,0xC4,0x01,0xA2,0x00,0x00,0x01,0x05,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,
+0x0B,0x01,0x00,0x03,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00,0x00,0x00,
+0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x10,0x00,
+0x02,0x01,0x03,0x03,0x02,0x04,0x03,0x05,0x05,0x04,0x04,0x00,0x00,0x01,0x7D,0x01,
+0x02,0x03,0x00,0x04,0x11,0x05,0x12,0x21,0x31,0x41,0x06,0x13,0x51,0x61,0x07,0x22,
+0x71,0x14,0x32,0x81,0x91,0xA1,0x08,0x23,0x42,0xB1,0xC1,0x15,0x52,0xD1,0xF0,0x24,
+0x33,0x62,0x72,0x82,0x09,0x0A,0x16,0x17,0x18,0x19,0x1A,0x25,0x26,0x27,0x28,0x29,
+0x2A,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,
+0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,
+0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,
+0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,
+0xA9,0xAA,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xC2,0xC3,0xC4,0xC5,0xC6,
+0xC7,0xC8,0xC9,0xCA,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xE1,0xE2,0xE3,
+0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,
+0xFA,0x11,0x00,0x02,0x01,0x02,0x04,0x04,0x03,0x04,0x07,0x05,0x04,0x04,0x00,0x01,
+0x02,0x77,0x00,0x01,0x02,0x03,0x11,0x04,0x05,0x21,0x31,0x06,0x12,0x41,0x51,0x07,
+0x61,0x71,0x13,0x22,0x32,0x81,0x08,0x14,0x42,0x91,0xA1,0xB1,0xC1,0x09,0x23,0x33,
+0x52,0xF0,0x15,0x62,0x72,0xD1,0x0A,0x16,0x24,0x34,0xE1,0x25,0xF1,0x17,0x18,0x19,
+0x1A,0x26,0x27,0x28,0x29,0x2A,0x35,0x36,0x37,0x38,0x39,0x3A,0x43,0x44,0x45,0x46,
+0x47,0x48,0x49,0x4A,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x63,0x64,0x65,0x66,
+0x67,0x68,0x69,0x6A,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x82,0x83,0x84,0x85,
+0x86,0x87,0x88,0x89,0x8A,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0xA2,0xA3,
+0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,
+0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,
+0xD9,0xDA,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xF2,0xF3,0xF4,0xF5,0xF6,
+0xF7,0xF8,0xF9,0xFA,
+};
+
+decodeMJPEG::decodeMJPEG()
+{
+    m_seq = SEQ_INIT;
+}
+
+void decodeMJPEG::inputPacket(const uint8_t* buf, int len)
+{
+    for(int i = 12; i < len; i++) {
+        input(buf[i]);
+    }
+}
+
+void decodeMJPEG::input(uint8_t c)
+{
+    switch(m_seq) {
+        case SEQ_INIT:
+            if (c == 0xff) {
+                m_seq = SEQ_SOI;
+            }
+            break;
+        case SEQ_SOI:
+            if (c == MARK_SOI) {
+                outputJPEG(0xff, JPEG_START); // start
+                outputJPEG(c);
+                m_bDHT = false;
+                m_seq = SEQ_FRAME;
+            } else {
+                m_seq = SEQ_INIT;
+            }
+            break;
+        case SEQ_FRAME:
+            if (c == 0xff) {
+                m_seq = SEQ_MARK;
+            } else {
+                m_seq = SEQ_INIT;
+            }
+            break;
+        case SEQ_MARK:
+            if (c == MARK_SOI || c == MARK_EOI || c == 0x00) {
+                m_seq = SEQ_INIT;
+                break;
+            }
+            m_mark = c;
+            m_seq = SEQ_SEG_LEN;
+            break;
+        case SEQ_SEG_LEN:
+            m_seg_len = c;
+            m_seq = SEQ_SEG_LEN2;
+            break;
+        case SEQ_SEG_LEN2:
+            m_seg_len <<= 8;
+            m_seg_len |= c;
+            m_seg_len -= 2;
+            m_seg_pos = 0;
+            m_seq = SEQ_SEG_BODY;
+            if (m_mark == MARK_SOS) {
+                if (m_bDHT == false) {
+                    for(int i = 0; i < sizeof(dht); i++) {
+                        outputJPEG(dht[i]);
+                    }    
+                }
+                m_output_desable = false;
+            } else if (m_mark == MARK_DHT) {
+                m_bDHT = true;
+                m_output_desable = false;
+            } else {
+                m_output_desable = false;
+            }
+            if (!m_output_desable) {
+                outputJPEG(0xff);
+                outputJPEG(m_mark);
+                outputJPEG((m_seg_len+2) >> 8);
+                outputJPEG((m_seg_len+2) & 0xff);
+            } 
+            break;
+        case SEQ_SEG_BODY:
+            if (!m_output_desable) {
+                outputJPEG(c);
+            }
+            if (++m_seg_pos < m_seg_len) {
+                break;
+            }
+            if (m_mark == MARK_SOS) {
+                m_seq = SEQ_SOS;
+                break;
+            }
+            m_seq = SEQ_FRAME;
+            break;
+        case SEQ_SOS:
+            if (c == 0xff) {
+                m_seq = SEQ_SOS2;
+                break;
+            }
+            outputJPEG(c);
+            break;
+        case SEQ_SOS2:
+            if (c == 0x00) {
+                outputJPEG(0xff);
+                outputJPEG(0x00);
+                m_seq = SEQ_SOS;
+                break;
+            } else if (c >= MARK_RST0 && c <= MARK_RST7) {
+                outputJPEG(0xff);
+                outputJPEG(c);
+                m_seq = SEQ_SOS;
+                break;
+            } else if (c == MARK_EOI) {
+                outputJPEG(0xff);
+                outputJPEG(c, JPEG_END);
+                m_seq = SEQ_INIT;
+                break;
+            } else if (c == MARK_SOI) {
+                outputJPEG(0xff);
+                outputJPEG(c);
+                m_seq = SEQ_INIT;
+                break;
+            }
+            m_seq = SEQ_INIT;
+            break;
+        default:
+            m_seq = SEQ_INIT;
+            break;
+    }
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/uvc/decodeMJPEG.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,25 @@
+// decodeMJPEG.h 2012/12/9
+#ifndef DECODE_MJPEG_H
+#define DECODE_MJPEG_H
+
+#define JPEG_NONE  0
+#define JPEG_START 1
+#define JPEG_END   2
+#define JPEG_ERROR 3
+
+class decodeMJPEG {
+public:
+    decodeMJPEG();
+    void inputPacket(const uint8_t* buf, int len);
+    virtual void outputJPEG(uint8_t c, int status = JPEG_NONE) = 0;
+protected:
+    void input(uint8_t c);
+    int m_seq;
+    uint8_t m_mark;
+    uint16_t m_seg_pos; 
+    uint16_t m_seg_len;
+    bool m_bDHT;
+    bool m_output_desable;
+};
+
+#endif // DECODE_MJPEG_H
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/uvc/jconfig.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,164 @@
+/*
+ * jconfig.doc
+ *
+ * Copyright (C) 1991-1994, Thomas G. Lane.
+ * This file is part of the Independent JPEG Group's software.
+ * For conditions of distribution and use, see the accompanying README file.
+ *
+ * This file documents the configuration options that are required to
+ * customize the JPEG software for a particular system.
+ *
+ * The actual configuration options for a particular installation are stored
+ * in jconfig.h.  On many machines, jconfig.h can be generated automatically
+ * or copied from one of the "canned" jconfig files that we supply.  But if
+ * you need to generate a jconfig.h file by hand, this file tells you how.
+ *
+ * DO NOT EDIT THIS FILE --- IT WON'T ACCOMPLISH ANYTHING.
+ * EDIT A COPY NAMED JCONFIG.H.
+ */
+
+
+/*
+ * These symbols indicate the properties of your machine or compiler.
+ * #define the symbol if yes, #undef it if no.
+ */
+
+/* Does your compiler support function prototypes?
+ * (If not, you also need to use ansi2knr, see install.doc)
+ */
+#define HAVE_PROTOTYPES
+
+/* Does your compiler support the declaration "unsigned char" ?
+ * How about "unsigned short" ?
+ */
+#define HAVE_UNSIGNED_CHAR
+#define HAVE_UNSIGNED_SHORT
+
+/* Define "void" as "char" if your compiler doesn't know about type void.
+ * NOTE: be sure to define void such that "void *" represents the most general
+ * pointer type, e.g., that returned by malloc().
+ */
+/* #define void char */
+
+/* Define "const" as empty if your compiler doesn't know the "const" keyword.
+ */
+/* #define const */
+
+/* Define this if an ordinary "char" type is unsigned.
+ * If you're not sure, leaving it undefined will work at some cost in speed.
+ * If you defined HAVE_UNSIGNED_CHAR then the speed difference is minimal.
+ */
+#undef CHAR_IS_UNSIGNED
+
+/* Define this if your system has an ANSI-conforming <stddef.h> file.
+ */
+#define HAVE_STDDEF_H
+
+/* Define this if your system has an ANSI-conforming <stdlib.h> file.
+ */
+#define HAVE_STDLIB_H
+
+/* Define this if your system has an FILE* type of <stdio.h>.
+ */
+/*#define HAVE_FILE_P_H*/
+
+/* Define this if your system does not have an ANSI/SysV <string.h>,
+ * but does have a BSD-style <strings.h>.
+ */
+#undef NEED_BSD_STRINGS
+
+/* Define this if your system does not provide typedef size_t in any of the
+ * ANSI-standard places (stddef.h, stdlib.h, or stdio.h), but places it in
+ * <sys/types.h> instead.
+ */
+#undef NEED_SYS_TYPES_H
+
+/* For 80x86 machines, you need to define NEED_FAR_POINTERS,
+ * unless you are using a large-data memory model or 80386 flat-memory mode.
+ * On less brain-damaged CPUs this symbol must not be defined.
+ * (Defining this symbol causes large data structures to be referenced through
+ * "far" pointers and to be allocated with a special version of malloc.)
+ */
+#undef NEED_FAR_POINTERS
+
+/* Define this if your linker needs global names to be unique in less
+ * than the first 15 characters.
+ */
+#undef NEED_SHORT_EXTERNAL_NAMES
+
+/* Although a real ANSI C compiler can deal perfectly well with pointers to
+ * unspecified structures (see "incomplete types" in the spec), a few pre-ANSI
+ * and pseudo-ANSI compilers get confused.  To keep one of these bozos happy,
+ * define INCOMPLETE_TYPES_BROKEN.  This is not recommended unless you
+ * actually get "missing structure definition" warnings or errors while
+ * compiling the JPEG code.
+ */
+#undef INCOMPLETE_TYPES_BROKEN
+
+
+/*
+ * The following options affect code selection within the JPEG library,
+ * but they don't need to be visible to applications using the library.
+ * To minimize application namespace pollution, the symbols won't be
+ * defined unless JPEG_INTERNALS has been defined.
+ */
+
+#ifdef JPEG_INTERNALS
+
+/* Define this if your compiler implements ">>" on signed values as a logical
+ * (unsigned) shift; leave it undefined if ">>" is a signed (arithmetic) shift,
+ * which is the normal and rational definition.
+ */
+#undef RIGHT_SHIFT_IS_UNSIGNED
+
+
+#endif /* JPEG_INTERNALS */
+
+
+/*
+ * The remaining options do not affect the JPEG library proper,
+ * but only the sample applications cjpeg/djpeg (see cjpeg.c, djpeg.c).
+ * Other applications can ignore these.
+ */
+
+#ifdef JPEG_CJPEG_DJPEG
+
+/* These defines indicate which image (non-JPEG) file formats are allowed. */
+
+#undef BMP_SUPPORTED		/* BMP image file format */
+#undef GIF_SUPPORTED		/* GIF image file format */
+#undef PPM_SUPPORTED		/* PBMPLUS PPM/PGM image file format */
+#undef RLE_SUPPORTED		/* Utah RLE image file format */
+#undef TARGA_SUPPORTED		/* Targa image file format */
+
+/* Define this if you want to name both input and output files on the command
+ * line, rather than using stdout and optionally stdin.  You MUST do this if
+ * your system can't cope with binary I/O to stdin/stdout.  See comments at
+ * head of cjpeg.c or djpeg.c.
+ */
+#undef TWO_FILE_COMMANDLINE
+
+/* Define this if your system needs explicit cleanup of temporary files.
+ * This is crucial under MS-DOS, where the temporary "files" may be areas
+ * of extended memory; on most other systems it's not as important.
+ */
+#undef NEED_SIGNAL_CATCHER
+
+/* By default, we open image files with fopen(...,"rb") or fopen(...,"wb").
+ * This is necessary on systems that distinguish text files from binary files,
+ * and is harmless on most systems that don't.  If you have one of the rare
+ * systems that complains about the "b" spec, define this symbol.
+ */
+#undef DONT_USE_B_MODE
+
+/* Define this if you want percent-done progress reports from cjpeg/djpeg.
+ */
+#undef PROGRESS_REPORT
+
+#endif /* JPEG_CJPEG_DJPEG */
+
+#define JDCT_DEFAULT  JDCT_IFAST
+#define JDCT_FASTEST  JDCT_IFAST
+#define NO_ZERO_ROW_TEST
+#include  "r_multi_compiler_typedef.h"  /* INLINE */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/uvc/jerror.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,304 @@
+/*
+ * jerror.h
+ *
+ * Copyright (C) 1994-1997, Thomas G. Lane.
+ * Modified 1997-2012 by Guido Vollbeding.
+ * This file is part of the Independent JPEG Group's software.
+ * For conditions of distribution and use, see the accompanying README file.
+ *
+ * This file defines the error and message codes for the JPEG library.
+ * Edit this file to add new codes, or to translate the message strings to
+ * some other language.
+ * A set of error-reporting macros are defined too.  Some applications using
+ * the JPEG library may wish to include this file to get the error codes
+ * and/or the macros.
+ */
+
+/*
+ * To define the enum list of message codes, include this file without
+ * defining macro JMESSAGE.  To create a message string table, include it
+ * again with a suitable JMESSAGE definition (see jerror.c for an example).
+ */
+#ifndef JMESSAGE
+#ifndef JERROR_H
+/* First time through, define the enum list */
+#define JMAKE_ENUM_LIST
+#else
+/* Repeated inclusions of this file are no-ops unless JMESSAGE is defined */
+#define JMESSAGE(code,string)
+#endif /* JERROR_H */
+#endif /* JMESSAGE */
+
+#ifdef JMAKE_ENUM_LIST
+
+typedef enum {
+
+#define JMESSAGE(code,string)	code ,
+
+#endif /* JMAKE_ENUM_LIST */
+
+JMESSAGE(JMSG_NOMESSAGE, "Bogus message code %d") /* Must be first entry! */
+
+/* For maintenance convenience, list is alphabetical by message code name */
+JMESSAGE(JERR_BAD_ALIGN_TYPE, "ALIGN_TYPE is wrong, please fix")
+JMESSAGE(JERR_BAD_ALLOC_CHUNK, "MAX_ALLOC_CHUNK is wrong, please fix")
+JMESSAGE(JERR_BAD_BUFFER_MODE, "Bogus buffer control mode")
+JMESSAGE(JERR_BAD_COMPONENT_ID, "Invalid component ID %d in SOS")
+JMESSAGE(JERR_BAD_CROP_SPEC, "Invalid crop request")
+JMESSAGE(JERR_BAD_DCT_COEF, "DCT coefficient out of range")
+JMESSAGE(JERR_BAD_DCTSIZE, "DCT scaled block size %dx%d not supported")
+JMESSAGE(JERR_BAD_DROP_SAMPLING,
+	 "Component index %d: mismatching sampling ratio %d:%d, %d:%d, %c")
+JMESSAGE(JERR_BAD_HUFF_TABLE, "Bogus Huffman table definition")
+JMESSAGE(JERR_BAD_IN_COLORSPACE, "Bogus input colorspace")
+JMESSAGE(JERR_BAD_J_COLORSPACE, "Bogus JPEG colorspace")
+JMESSAGE(JERR_BAD_LENGTH, "Bogus marker length")
+JMESSAGE(JERR_BAD_LIB_VERSION,
+	 "Wrong JPEG library version: library is %d, caller expects %d")
+JMESSAGE(JERR_BAD_MCU_SIZE, "Sampling factors too large for interleaved scan")
+JMESSAGE(JERR_BAD_POOL_ID, "Invalid memory pool code %d")
+JMESSAGE(JERR_BAD_PRECISION, "Unsupported JPEG data precision %d")
+JMESSAGE(JERR_BAD_PROGRESSION,
+	 "Invalid progressive parameters Ss=%d Se=%d Ah=%d Al=%d")
+JMESSAGE(JERR_BAD_PROG_SCRIPT,
+	 "Invalid progressive parameters at scan script entry %d")
+JMESSAGE(JERR_BAD_SAMPLING, "Bogus sampling factors")
+JMESSAGE(JERR_BAD_SCAN_SCRIPT, "Invalid scan script at entry %d")
+JMESSAGE(JERR_BAD_STATE, "Improper call to JPEG library in state %d")
+JMESSAGE(JERR_BAD_STRUCT_SIZE,
+	 "JPEG parameter struct mismatch: library thinks size is %u, caller expects %u")
+JMESSAGE(JERR_BAD_VIRTUAL_ACCESS, "Bogus virtual array access")
+JMESSAGE(JERR_BUFFER_SIZE, "Buffer passed to JPEG library is too small")
+JMESSAGE(JERR_CANT_SUSPEND, "Suspension not allowed here")
+JMESSAGE(JERR_CCIR601_NOTIMPL, "CCIR601 sampling not implemented yet")
+JMESSAGE(JERR_COMPONENT_COUNT, "Too many color components: %d, max %d")
+JMESSAGE(JERR_CONVERSION_NOTIMPL, "Unsupported color conversion request")
+JMESSAGE(JERR_DAC_INDEX, "Bogus DAC index %d")
+JMESSAGE(JERR_DAC_VALUE, "Bogus DAC value 0x%x")
+JMESSAGE(JERR_DHT_INDEX, "Bogus DHT index %d")
+JMESSAGE(JERR_DQT_INDEX, "Bogus DQT index %d")
+JMESSAGE(JERR_EMPTY_IMAGE, "Empty JPEG image (DNL not supported)")
+JMESSAGE(JERR_EMS_READ, "Read from EMS failed")
+JMESSAGE(JERR_EMS_WRITE, "Write to EMS failed")
+JMESSAGE(JERR_EOI_EXPECTED, "Didn't expect more than one scan")
+JMESSAGE(JERR_FILE_READ, "Input file read error")
+JMESSAGE(JERR_FILE_WRITE, "Output file write error --- out of disk space?")
+JMESSAGE(JERR_FRACT_SAMPLE_NOTIMPL, "Fractional sampling not implemented yet")
+JMESSAGE(JERR_HUFF_CLEN_OVERFLOW, "Huffman code size table overflow")
+JMESSAGE(JERR_HUFF_MISSING_CODE, "Missing Huffman code table entry")
+JMESSAGE(JERR_IMAGE_TOO_BIG, "Maximum supported image dimension is %u pixels")
+JMESSAGE(JERR_INPUT_EMPTY, "Empty input file")
+JMESSAGE(JERR_INPUT_EOF, "Premature end of input file")
+JMESSAGE(JERR_MISMATCHED_QUANT_TABLE,
+	 "Cannot transcode due to multiple use of quantization table %d")
+JMESSAGE(JERR_MISSING_DATA, "Scan script does not transmit all data")
+JMESSAGE(JERR_MODE_CHANGE, "Invalid color quantization mode change")
+JMESSAGE(JERR_NOTIMPL, "Not implemented yet")
+JMESSAGE(JERR_NOT_COMPILED, "Requested feature was omitted at compile time")
+JMESSAGE(JERR_NO_ARITH_TABLE, "Arithmetic table 0x%02x was not defined")
+JMESSAGE(JERR_NO_BACKING_STORE, "Backing store not supported")
+JMESSAGE(JERR_NO_HUFF_TABLE, "Huffman table 0x%02x was not defined")
+JMESSAGE(JERR_NO_IMAGE, "JPEG datastream contains no image")
+JMESSAGE(JERR_NO_QUANT_TABLE, "Quantization table 0x%02x was not defined")
+JMESSAGE(JERR_NO_SOI, "Not a JPEG file: starts with 0x%02x 0x%02x")
+JMESSAGE(JERR_OUT_OF_MEMORY, "Insufficient memory (case %d)")
+JMESSAGE(JERR_QUANT_COMPONENTS,
+	 "Cannot quantize more than %d color components")
+JMESSAGE(JERR_QUANT_FEW_COLORS, "Cannot quantize to fewer than %d colors")
+JMESSAGE(JERR_QUANT_MANY_COLORS, "Cannot quantize to more than %d colors")
+JMESSAGE(JERR_SOF_BEFORE, "Invalid JPEG file structure: %s before SOF")
+JMESSAGE(JERR_SOF_DUPLICATE, "Invalid JPEG file structure: two SOF markers")
+JMESSAGE(JERR_SOF_NO_SOS, "Invalid JPEG file structure: missing SOS marker")
+JMESSAGE(JERR_SOF_UNSUPPORTED, "Unsupported JPEG process: SOF type 0x%02x")
+JMESSAGE(JERR_SOI_DUPLICATE, "Invalid JPEG file structure: two SOI markers")
+JMESSAGE(JERR_TFILE_CREATE, "Failed to create temporary file %s")
+JMESSAGE(JERR_TFILE_READ, "Read failed on temporary file")
+JMESSAGE(JERR_TFILE_SEEK, "Seek failed on temporary file")
+JMESSAGE(JERR_TFILE_WRITE,
+	 "Write failed on temporary file --- out of disk space?")
+JMESSAGE(JERR_TOO_LITTLE_DATA, "Application transferred too few scanlines")
+JMESSAGE(JERR_UNKNOWN_MARKER, "Unsupported marker type 0x%02x")
+JMESSAGE(JERR_VIRTUAL_BUG, "Virtual array controller messed up")
+JMESSAGE(JERR_WIDTH_OVERFLOW, "Image too wide for this implementation")
+JMESSAGE(JERR_XMS_READ, "Read from XMS failed")
+JMESSAGE(JERR_XMS_WRITE, "Write to XMS failed")
+JMESSAGE(JMSG_COPYRIGHT, JCOPYRIGHT)
+JMESSAGE(JMSG_VERSION, JVERSION)
+JMESSAGE(JTRC_16BIT_TABLES,
+	 "Caution: quantization tables are too coarse for baseline JPEG")
+JMESSAGE(JTRC_ADOBE,
+	 "Adobe APP14 marker: version %d, flags 0x%04x 0x%04x, transform %d")
+JMESSAGE(JTRC_APP0, "Unknown APP0 marker (not JFIF), length %u")
+JMESSAGE(JTRC_APP14, "Unknown APP14 marker (not Adobe), length %u")
+JMESSAGE(JTRC_DAC, "Define Arithmetic Table 0x%02x: 0x%02x")
+JMESSAGE(JTRC_DHT, "Define Huffman Table 0x%02x")
+JMESSAGE(JTRC_DQT, "Define Quantization Table %d  precision %d")
+JMESSAGE(JTRC_DRI, "Define Restart Interval %u")
+JMESSAGE(JTRC_EMS_CLOSE, "Freed EMS handle %u")
+JMESSAGE(JTRC_EMS_OPEN, "Obtained EMS handle %u")
+JMESSAGE(JTRC_EOI, "End Of Image")
+JMESSAGE(JTRC_HUFFBITS, "        %3d %3d %3d %3d %3d %3d %3d %3d")
+JMESSAGE(JTRC_JFIF, "JFIF APP0 marker: version %d.%02d, density %dx%d  %d")
+JMESSAGE(JTRC_JFIF_BADTHUMBNAILSIZE,
+	 "Warning: thumbnail image size does not match data length %u")
+JMESSAGE(JTRC_JFIF_EXTENSION,
+	 "JFIF extension marker: type 0x%02x, length %u")
+JMESSAGE(JTRC_JFIF_THUMBNAIL, "    with %d x %d thumbnail image")
+JMESSAGE(JTRC_MISC_MARKER, "Miscellaneous marker 0x%02x, length %u")
+JMESSAGE(JTRC_PARMLESS_MARKER, "Unexpected marker 0x%02x")
+JMESSAGE(JTRC_QUANTVALS, "        %4u %4u %4u %4u %4u %4u %4u %4u")
+JMESSAGE(JTRC_QUANT_3_NCOLORS, "Quantizing to %d = %d*%d*%d colors")
+JMESSAGE(JTRC_QUANT_NCOLORS, "Quantizing to %d colors")
+JMESSAGE(JTRC_QUANT_SELECTED, "Selected %d colors for quantization")
+JMESSAGE(JTRC_RECOVERY_ACTION, "At marker 0x%02x, recovery action %d")
+JMESSAGE(JTRC_RST, "RST%d")
+JMESSAGE(JTRC_SMOOTH_NOTIMPL,
+	 "Smoothing not supported with nonstandard sampling ratios")
+JMESSAGE(JTRC_SOF, "Start Of Frame 0x%02x: width=%u, height=%u, components=%d")
+JMESSAGE(JTRC_SOF_COMPONENT, "    Component %d: %dhx%dv q=%d")
+JMESSAGE(JTRC_SOI, "Start of Image")
+JMESSAGE(JTRC_SOS, "Start Of Scan: %d components")
+JMESSAGE(JTRC_SOS_COMPONENT, "    Component %d: dc=%d ac=%d")
+JMESSAGE(JTRC_SOS_PARAMS, "  Ss=%d, Se=%d, Ah=%d, Al=%d")
+JMESSAGE(JTRC_TFILE_CLOSE, "Closed temporary file %s")
+JMESSAGE(JTRC_TFILE_OPEN, "Opened temporary file %s")
+JMESSAGE(JTRC_THUMB_JPEG,
+	 "JFIF extension marker: JPEG-compressed thumbnail image, length %u")
+JMESSAGE(JTRC_THUMB_PALETTE,
+	 "JFIF extension marker: palette thumbnail image, length %u")
+JMESSAGE(JTRC_THUMB_RGB,
+	 "JFIF extension marker: RGB thumbnail image, length %u")
+JMESSAGE(JTRC_UNKNOWN_IDS,
+	 "Unrecognized component IDs %d %d %d, assuming YCbCr")
+JMESSAGE(JTRC_XMS_CLOSE, "Freed XMS handle %u")
+JMESSAGE(JTRC_XMS_OPEN, "Obtained XMS handle %u")
+JMESSAGE(JWRN_ADOBE_XFORM, "Unknown Adobe color transform code %d")
+JMESSAGE(JWRN_ARITH_BAD_CODE, "Corrupt JPEG data: bad arithmetic code")
+JMESSAGE(JWRN_BOGUS_PROGRESSION,
+	 "Inconsistent progression sequence for component %d coefficient %d")
+JMESSAGE(JWRN_EXTRANEOUS_DATA,
+	 "Corrupt JPEG data: %u extraneous bytes before marker 0x%02x")
+JMESSAGE(JWRN_HIT_MARKER, "Corrupt JPEG data: premature end of data segment")
+JMESSAGE(JWRN_HUFF_BAD_CODE, "Corrupt JPEG data: bad Huffman code")
+JMESSAGE(JWRN_JFIF_MAJOR, "Warning: unknown JFIF revision number %d.%02d")
+JMESSAGE(JWRN_JPEG_EOF, "Premature end of JPEG file")
+JMESSAGE(JWRN_MUST_RESYNC,
+	 "Corrupt JPEG data: found marker 0x%02x instead of RST%d")
+JMESSAGE(JWRN_NOT_SEQUENTIAL, "Invalid SOS parameters for sequential JPEG")
+JMESSAGE(JWRN_TOO_MUCH_DATA, "Application transferred too many scanlines")
+
+#ifdef JMAKE_ENUM_LIST
+
+  JMSG_LASTMSGCODE
+} J_MESSAGE_CODE;
+
+#undef JMAKE_ENUM_LIST
+#endif /* JMAKE_ENUM_LIST */
+
+/* Zap JMESSAGE macro so that future re-inclusions do nothing by default */
+#undef JMESSAGE
+
+
+#ifndef JERROR_H
+#define JERROR_H
+
+/* Macros to simplify using the error and trace message stuff */
+/* The first parameter is either type of cinfo pointer */
+
+/* Fatal errors (print message and exit) */
+#define ERREXIT(cinfo,code)  \
+  ((cinfo)->err->msg_code = (code), \
+   (*(cinfo)->err->error_exit) ((j_common_ptr) (cinfo)))
+#define ERREXIT1(cinfo,code,p1)  \
+  ((cinfo)->err->msg_code = (code), \
+   (cinfo)->err->msg_parm.i[0] = (p1), \
+   (*(cinfo)->err->error_exit) ((j_common_ptr) (cinfo)))
+#define ERREXIT2(cinfo,code,p1,p2)  \
+  ((cinfo)->err->msg_code = (code), \
+   (cinfo)->err->msg_parm.i[0] = (p1), \
+   (cinfo)->err->msg_parm.i[1] = (p2), \
+   (*(cinfo)->err->error_exit) ((j_common_ptr) (cinfo)))
+#define ERREXIT3(cinfo,code,p1,p2,p3)  \
+  ((cinfo)->err->msg_code = (code), \
+   (cinfo)->err->msg_parm.i[0] = (p1), \
+   (cinfo)->err->msg_parm.i[1] = (p2), \
+   (cinfo)->err->msg_parm.i[2] = (p3), \
+   (*(cinfo)->err->error_exit) ((j_common_ptr) (cinfo)))
+#define ERREXIT4(cinfo,code,p1,p2,p3,p4)  \
+  ((cinfo)->err->msg_code = (code), \
+   (cinfo)->err->msg_parm.i[0] = (p1), \
+   (cinfo)->err->msg_parm.i[1] = (p2), \
+   (cinfo)->err->msg_parm.i[2] = (p3), \
+   (cinfo)->err->msg_parm.i[3] = (p4), \
+   (*(cinfo)->err->error_exit) ((j_common_ptr) (cinfo)))
+#define ERREXIT6(cinfo,code,p1,p2,p3,p4,p5,p6)  \
+  ((cinfo)->err->msg_code = (code), \
+   (cinfo)->err->msg_parm.i[0] = (p1), \
+   (cinfo)->err->msg_parm.i[1] = (p2), \
+   (cinfo)->err->msg_parm.i[2] = (p3), \
+   (cinfo)->err->msg_parm.i[3] = (p4), \
+   (cinfo)->err->msg_parm.i[4] = (p5), \
+   (cinfo)->err->msg_parm.i[5] = (p6), \
+   (*(cinfo)->err->error_exit) ((j_common_ptr) (cinfo)))
+#define ERREXITS(cinfo,code,str)  \
+  ((cinfo)->err->msg_code = (code), \
+   strncpy((cinfo)->err->msg_parm.s, (str), JMSG_STR_PARM_MAX), \
+   (*(cinfo)->err->error_exit) ((j_common_ptr) (cinfo)))
+
+#define MAKESTMT(stuff)		do { stuff } while (0)
+
+/* Nonfatal errors (we can keep going, but the data is probably corrupt) */
+#define WARNMS(cinfo,code)  \
+  ((cinfo)->err->msg_code = (code), \
+   (*(cinfo)->err->emit_message) ((j_common_ptr) (cinfo), -1))
+#define WARNMS1(cinfo,code,p1)  \
+  ((cinfo)->err->msg_code = (code), \
+   (cinfo)->err->msg_parm.i[0] = (p1), \
+   (*(cinfo)->err->emit_message) ((j_common_ptr) (cinfo), -1))
+#define WARNMS2(cinfo,code,p1,p2)  \
+  ((cinfo)->err->msg_code = (code), \
+   (cinfo)->err->msg_parm.i[0] = (p1), \
+   (cinfo)->err->msg_parm.i[1] = (p2), \
+   (*(cinfo)->err->emit_message) ((j_common_ptr) (cinfo), -1))
+
+/* Informational/debugging messages */
+#define TRACEMS(cinfo,lvl,code)  \
+  ((cinfo)->err->msg_code = (code), \
+   (*(cinfo)->err->emit_message) ((j_common_ptr) (cinfo), (lvl)))
+#define TRACEMS1(cinfo,lvl,code,p1)  \
+  ((cinfo)->err->msg_code = (code), \
+   (cinfo)->err->msg_parm.i[0] = (p1), \
+   (*(cinfo)->err->emit_message) ((j_common_ptr) (cinfo), (lvl)))
+#define TRACEMS2(cinfo,lvl,code,p1,p2)  \
+  ((cinfo)->err->msg_code = (code), \
+   (cinfo)->err->msg_parm.i[0] = (p1), \
+   (cinfo)->err->msg_parm.i[1] = (p2), \
+   (*(cinfo)->err->emit_message) ((j_common_ptr) (cinfo), (lvl)))
+#define TRACEMS3(cinfo,lvl,code,p1,p2,p3)  \
+  MAKESTMT(int * _mp = (cinfo)->err->msg_parm.i; \
+	   _mp[0] = (p1); _mp[1] = (p2); _mp[2] = (p3); \
+	   (cinfo)->err->msg_code = (code); \
+	   (*(cinfo)->err->emit_message) ((j_common_ptr) (cinfo), (lvl)); )
+#define TRACEMS4(cinfo,lvl,code,p1,p2,p3,p4)  \
+  MAKESTMT(int * _mp = (cinfo)->err->msg_parm.i; \
+	   _mp[0] = (p1); _mp[1] = (p2); _mp[2] = (p3); _mp[3] = (p4); \
+	   (cinfo)->err->msg_code = (code); \
+	   (*(cinfo)->err->emit_message) ((j_common_ptr) (cinfo), (lvl)); )
+#define TRACEMS5(cinfo,lvl,code,p1,p2,p3,p4,p5)  \
+  MAKESTMT(int * _mp = (cinfo)->err->msg_parm.i; \
+	   _mp[0] = (p1); _mp[1] = (p2); _mp[2] = (p3); _mp[3] = (p4); \
+	   _mp[4] = (p5); \
+	   (cinfo)->err->msg_code = (code); \
+	   (*(cinfo)->err->emit_message) ((j_common_ptr) (cinfo), (lvl)); )
+#define TRACEMS8(cinfo,lvl,code,p1,p2,p3,p4,p5,p6,p7,p8)  \
+  MAKESTMT(int * _mp = (cinfo)->err->msg_parm.i; \
+	   _mp[0] = (p1); _mp[1] = (p2); _mp[2] = (p3); _mp[3] = (p4); \
+	   _mp[4] = (p5); _mp[5] = (p6); _mp[6] = (p7); _mp[7] = (p8); \
+	   (cinfo)->err->msg_code = (code); \
+	   (*(cinfo)->err->emit_message) ((j_common_ptr) (cinfo), (lvl)); )
+#define TRACEMSS(cinfo,lvl,code,str)  \
+  ((cinfo)->err->msg_code = (code), \
+   strncpy((cinfo)->err->msg_parm.s, (str), JMSG_STR_PARM_MAX), \
+   (*(cinfo)->err->emit_message) ((j_common_ptr) (cinfo), (lvl)))
+
+#endif /* JERROR_H */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/uvc/jmorecfg.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,451 @@
+/*
+ * jmorecfg.h
+ *
+ * Copyright (C) 1991-1997, Thomas G. Lane.
+ * Modified 1997-2013 by Guido Vollbeding.
+ * This file is part of the Independent JPEG Group's software.
+ * For conditions of distribution and use, see the accompanying README file.
+ *
+ * This file contains additional configuration options that customize the
+ * JPEG software for special applications or support machine-dependent
+ * optimizations.  Most users will not need to touch this file.
+ */
+
+
+/*
+ * Define BITS_IN_JSAMPLE as either
+ *   8   for 8-bit sample values (the usual setting)
+ *   9   for 9-bit sample values
+ *   10  for 10-bit sample values
+ *   11  for 11-bit sample values
+ *   12  for 12-bit sample values
+ * Only 8, 9, 10, 11, and 12 bits sample data precision are supported for
+ * full-feature DCT processing.  Further depths up to 16-bit may be added
+ * later for the lossless modes of operation.
+ * Run-time selection and conversion of data precision will be added later
+ * and are currently not supported, sorry.
+ * Exception:  The transcoding part (jpegtran) supports all settings in a
+ * single instance, since it operates on the level of DCT coefficients and
+ * not sample values.  The DCT coefficients are of the same type (16 bits)
+ * in all cases (see below).
+ */
+
+#define BITS_IN_JSAMPLE  8	/* use 8, 9, 10, 11, or 12 */
+
+
+/*
+ * Maximum number of components (color channels) allowed in JPEG image.
+ * To meet the letter of the JPEG spec, set this to 255.  However, darn
+ * few applications need more than 4 channels (maybe 5 for CMYK + alpha
+ * mask).  We recommend 10 as a reasonable compromise; use 4 if you are
+ * really short on memory.  (Each allowed component costs a hundred or so
+ * bytes of storage, whether actually used in an image or not.)
+ */
+
+#define MAX_COMPONENTS  10	/* maximum number of image components */
+
+
+/*
+ * Basic data types.
+ * You may need to change these if you have a machine with unusual data
+ * type sizes; for example, "char" not 8 bits, "short" not 16 bits,
+ * or "long" not 32 bits.  We don't care whether "int" is 16 or 32 bits,
+ * but it had better be at least 16.
+ */
+
+/* Representation of a single sample (pixel element value).
+ * We frequently allocate large arrays of these, so it's important to keep
+ * them small.  But if you have memory to burn and access to char or short
+ * arrays is very slow on your hardware, you might want to change these.
+ */
+
+#if BITS_IN_JSAMPLE == 8
+/* JSAMPLE should be the smallest type that will hold the values 0..255.
+ * You can use a signed char by having GETJSAMPLE mask it with 0xFF.
+ */
+
+#ifdef HAVE_UNSIGNED_CHAR
+
+typedef unsigned char JSAMPLE;
+#define GETJSAMPLE(value)  ((int) (value))
+
+#else /* not HAVE_UNSIGNED_CHAR */
+
+typedef char JSAMPLE;
+#ifdef CHAR_IS_UNSIGNED
+#define GETJSAMPLE(value)  ((int) (value))
+#else
+#define GETJSAMPLE(value)  ((int) (value) & 0xFF)
+#endif /* CHAR_IS_UNSIGNED */
+
+#endif /* HAVE_UNSIGNED_CHAR */
+
+#define MAXJSAMPLE	255
+#define CENTERJSAMPLE	128
+
+#endif /* BITS_IN_JSAMPLE == 8 */
+
+
+#if BITS_IN_JSAMPLE == 9
+/* JSAMPLE should be the smallest type that will hold the values 0..511.
+ * On nearly all machines "short" will do nicely.
+ */
+
+typedef short JSAMPLE;
+#define GETJSAMPLE(value)  ((int) (value))
+
+#define MAXJSAMPLE	511
+#define CENTERJSAMPLE	256
+
+#endif /* BITS_IN_JSAMPLE == 9 */
+
+
+#if BITS_IN_JSAMPLE == 10
+/* JSAMPLE should be the smallest type that will hold the values 0..1023.
+ * On nearly all machines "short" will do nicely.
+ */
+
+typedef short JSAMPLE;
+#define GETJSAMPLE(value)  ((int) (value))
+
+#define MAXJSAMPLE	1023
+#define CENTERJSAMPLE	512
+
+#endif /* BITS_IN_JSAMPLE == 10 */
+
+
+#if BITS_IN_JSAMPLE == 11
+/* JSAMPLE should be the smallest type that will hold the values 0..2047.
+ * On nearly all machines "short" will do nicely.
+ */
+
+typedef short JSAMPLE;
+#define GETJSAMPLE(value)  ((int) (value))
+
+#define MAXJSAMPLE	2047
+#define CENTERJSAMPLE	1024
+
+#endif /* BITS_IN_JSAMPLE == 11 */
+
+
+#if BITS_IN_JSAMPLE == 12
+/* JSAMPLE should be the smallest type that will hold the values 0..4095.
+ * On nearly all machines "short" will do nicely.
+ */
+
+typedef short JSAMPLE;
+#define GETJSAMPLE(value)  ((int) (value))
+
+#define MAXJSAMPLE	4095
+#define CENTERJSAMPLE	2048
+
+#endif /* BITS_IN_JSAMPLE == 12 */
+
+
+/* Representation of a DCT frequency coefficient.
+ * This should be a signed value of at least 16 bits; "short" is usually OK.
+ * Again, we allocate large arrays of these, but you can change to int
+ * if you have memory to burn and "short" is really slow.
+ */
+
+typedef short JCOEF;
+
+
+/* Compressed datastreams are represented as arrays of JOCTET.
+ * These must be EXACTLY 8 bits wide, at least once they are written to
+ * external storage.  Note that when using the stdio data source/destination
+ * managers, this is also the data type passed to fread/fwrite.
+ */
+
+#ifdef HAVE_UNSIGNED_CHAR
+
+typedef unsigned char JOCTET;
+#define GETJOCTET(value)  (value)
+
+#else /* not HAVE_UNSIGNED_CHAR */
+
+typedef char JOCTET;
+#ifdef CHAR_IS_UNSIGNED
+#define GETJOCTET(value)  (value)
+#else
+#define GETJOCTET(value)  ((value) & 0xFF)
+#endif /* CHAR_IS_UNSIGNED */
+
+#endif /* HAVE_UNSIGNED_CHAR */
+
+
+/* These typedefs are used for various table entries and so forth.
+ * They must be at least as wide as specified; but making them too big
+ * won't cost a huge amount of memory, so we don't provide special
+ * extraction code like we did for JSAMPLE.  (In other words, these
+ * typedefs live at a different point on the speed/space tradeoff curve.)
+ */
+
+/* UINT8 must hold at least the values 0..255. */
+
+#ifdef HAVE_UNSIGNED_CHAR
+typedef unsigned char UINT8;
+#else /* not HAVE_UNSIGNED_CHAR */
+#ifdef CHAR_IS_UNSIGNED
+typedef char UINT8;
+#else /* not CHAR_IS_UNSIGNED */
+typedef short UINT8;
+#endif /* CHAR_IS_UNSIGNED */
+#endif /* HAVE_UNSIGNED_CHAR */
+
+/* UINT16 must hold at least the values 0..65535. */
+
+#ifdef HAVE_UNSIGNED_SHORT
+typedef unsigned short UINT16;
+#else /* not HAVE_UNSIGNED_SHORT */
+typedef unsigned int UINT16;
+#endif /* HAVE_UNSIGNED_SHORT */
+
+/* INT16 must hold at least the values -32768..32767. */
+
+#ifndef XMD_H			/* X11/xmd.h correctly defines INT16 */
+typedef short INT16;
+#endif
+
+/* INT32 must hold at least signed 32-bit values. */
+
+#ifndef XMD_H			/* X11/xmd.h correctly defines INT32 */
+#ifndef _BASETSD_H_		/* Microsoft defines it in basetsd.h */
+#ifndef _BASETSD_H		/* MinGW is slightly different */
+#ifndef QGLOBAL_H		/* Qt defines it in qglobal.h */
+typedef long INT32;
+#endif
+#endif
+#endif
+#endif
+
+/* Datatype used for image dimensions.  The JPEG standard only supports
+ * images up to 64K*64K due to 16-bit fields in SOF markers.  Therefore
+ * "unsigned int" is sufficient on all machines.  However, if you need to
+ * handle larger images and you don't mind deviating from the spec, you
+ * can change this datatype.
+ */
+
+typedef unsigned int JDIMENSION;
+
+#define JPEG_MAX_DIMENSION  65500L  /* a tad under 64K to prevent overflows */
+
+
+/* These macros are used in all function definitions and extern declarations.
+ * You could modify them if you need to change function linkage conventions;
+ * in particular, you'll need to do that to make the library a Windows DLL.
+ * Another application is to make all functions global for use with debuggers
+ * or code profilers that require it.
+ */
+
+/* a function called through method pointers: */
+#define METHODDEF(type)		static type
+/* a function used only in its module: */
+#define LOCAL(type)		static type
+/* a function referenced thru EXTERNs: */
+#define GLOBAL(type)		type
+/* a reference to a GLOBAL function: */
+#define EXTERN(type)		extern type
+
+
+/* This macro is used to declare a "method", that is, a function pointer.
+ * We want to supply prototype parameters if the compiler can cope.
+ * Note that the arglist parameter must be parenthesized!
+ * Again, you can customize this if you need special linkage keywords.
+ */
+
+#ifdef HAVE_PROTOTYPES
+#define JMETHOD(type,methodname,arglist)  type (*methodname) arglist
+#else
+#define JMETHOD(type,methodname,arglist)  type (*methodname) ()
+#endif
+
+
+/* The noreturn type identifier is used to declare functions
+ * which cannot return.
+ * Compilers can thus create more optimized code and perform
+ * better checks for warnings and errors.
+ * Static analyzer tools can make improved inferences about
+ * execution paths and are prevented from giving false alerts.
+ *
+ * Unfortunately, the proposed specifications of corresponding
+ * extensions in the Dec 2011 ISO C standard revision (C11),
+ * GCC, MSVC, etc. are not viable.
+ * Thus we introduce a user defined type to declare noreturn
+ * functions at least for clarity.  A proper compiler would
+ * have a suitable noreturn type to match in place of void.
+ */
+
+#ifndef HAVE_NORETURN_T
+typedef void noreturn_t;
+#endif
+
+
+/* Here is the pseudo-keyword for declaring pointers that must be "far"
+ * on 80x86 machines.  Most of the specialized coding for 80x86 is handled
+ * by just saying "FAR *" where such a pointer is needed.  In a few places
+ * explicit coding is needed; see uses of the NEED_FAR_POINTERS symbol.
+ */
+
+#ifndef FAR
+#ifdef NEED_FAR_POINTERS
+#define FAR  far
+#else
+#define FAR
+#endif
+#endif
+
+
+/*
+ * On a few systems, type boolean and/or its values FALSE, TRUE may appear
+ * in standard header files.  Or you may have conflicts with application-
+ * specific header files that you want to include together with these files.
+ * Defining HAVE_BOOLEAN before including jpeglib.h should make it work.
+ */
+
+#ifndef HAVE_BOOLEAN
+#if defined FALSE || defined TRUE || defined QGLOBAL_H
+/* Qt3 defines FALSE and TRUE as "const" variables in qglobal.h */
+typedef int boolean;
+#ifndef FALSE			/* in case these macros already exist */
+#define FALSE	0		/* values of boolean */
+#endif
+#ifndef TRUE
+#define TRUE	1
+#endif
+#else
+typedef enum { FALSE = 0, TRUE = 1 } boolean;
+#endif
+#endif
+
+
+/*
+ * The remaining options affect code selection within the JPEG library,
+ * but they don't need to be visible to most applications using the library.
+ * To minimize application namespace pollution, the symbols won't be
+ * defined unless JPEG_INTERNALS or JPEG_INTERNAL_OPTIONS has been defined.
+ */
+
+#ifdef JPEG_INTERNALS
+#define JPEG_INTERNAL_OPTIONS
+#endif
+
+#ifdef JPEG_INTERNAL_OPTIONS
+
+
+/*
+ * These defines indicate whether to include various optional functions.
+ * Undefining some of these symbols will produce a smaller but less capable
+ * library.  Note that you can leave certain source files out of the
+ * compilation/linking process if you've #undef'd the corresponding symbols.
+ * (You may HAVE to do that if your compiler doesn't like null source files.)
+ */
+
+/* Capability options common to encoder and decoder: */
+
+#define DCT_ISLOW_SUPPORTED	/* slow but accurate integer algorithm */
+#define DCT_IFAST_SUPPORTED	/* faster, less accurate integer method */
+#define DCT_FLOAT_SUPPORTED	/* floating-point: accurate, fast on fast HW */
+
+/* Encoder capability options: */
+
+#define C_ARITH_CODING_SUPPORTED    /* Arithmetic coding back end? */
+#define C_MULTISCAN_FILES_SUPPORTED /* Multiple-scan JPEG files? */
+#define C_PROGRESSIVE_SUPPORTED	    /* Progressive JPEG? (Requires MULTISCAN)*/
+#define DCT_SCALING_SUPPORTED	    /* Input rescaling via DCT? (Requires DCT_ISLOW)*/
+#define ENTROPY_OPT_SUPPORTED	    /* Optimization of entropy coding parms? */
+/* Note: if you selected more than 8-bit data precision, it is dangerous to
+ * turn off ENTROPY_OPT_SUPPORTED.  The standard Huffman tables are only
+ * good for 8-bit precision, so arithmetic coding is recommended for higher
+ * precision.  The Huffman encoder normally uses entropy optimization to
+ * compute usable tables for higher precision.  Otherwise, you'll have to
+ * supply different default Huffman tables.
+ * The exact same statements apply for progressive JPEG: the default tables
+ * don't work for progressive mode.  (This may get fixed, however.)
+ */
+#define INPUT_SMOOTHING_SUPPORTED   /* Input image smoothing option? */
+
+/* Decoder capability options: */
+
+#define D_ARITH_CODING_SUPPORTED    /* Arithmetic coding back end? */
+#define D_MULTISCAN_FILES_SUPPORTED /* Multiple-scan JPEG files? */
+#define D_PROGRESSIVE_SUPPORTED	    /* Progressive JPEG? (Requires MULTISCAN)*/
+#define IDCT_SCALING_SUPPORTED	    /* Output rescaling via IDCT? (Requires DCT_ISLOW)*/
+#define SAVE_MARKERS_SUPPORTED	    /* jpeg_save_markers() needed? */
+#define BLOCK_SMOOTHING_SUPPORTED   /* Block smoothing? (Progressive only) */
+#undef  UPSAMPLE_SCALING_SUPPORTED  /* Output rescaling at upsample stage? */
+#define UPSAMPLE_MERGING_SUPPORTED  /* Fast path for sloppy upsampling? */
+#define QUANT_1PASS_SUPPORTED	    /* 1-pass color quantization? */
+#define QUANT_2PASS_SUPPORTED	    /* 2-pass color quantization? */
+
+/* more capability options later, no doubt */
+
+
+/*
+ * Ordering of RGB data in scanlines passed to or from the application.
+ * If your application wants to deal with data in the order B,G,R, just
+ * change these macros.  You can also deal with formats such as R,G,B,X
+ * (one extra byte per pixel) by changing RGB_PIXELSIZE.  Note that changing
+ * the offsets will also change the order in which colormap data is organized.
+ * RESTRICTIONS:
+ * 1. The sample applications cjpeg,djpeg do NOT support modified RGB formats.
+ * 2. The color quantizer modules will not behave desirably if RGB_PIXELSIZE
+ *    is not 3 (they don't understand about dummy color components!).  So you
+ *    can't use color quantization if you change that value.
+ */
+
+#define RGB_RED		0	/* Offset of Red in an RGB scanline element */
+#define RGB_GREEN	1	/* Offset of Green */
+#define RGB_BLUE	2	/* Offset of Blue */
+#define RGB_PIXELSIZE	3	/* JSAMPLEs per RGB scanline element */
+
+
+/* Definitions for speed-related optimizations. */
+
+
+/* If your compiler supports inline functions, define INLINE
+ * as the inline keyword; otherwise define it as empty.
+ */
+
+#ifndef INLINE
+#ifdef __GNUC__			/* for instance, GNU C knows about inline */
+#define INLINE __inline__
+#endif
+#ifndef INLINE
+#define INLINE			/* default is to define it as empty */
+#endif
+#endif
+
+
+/* On some machines (notably 68000 series) "int" is 32 bits, but multiplying
+ * two 16-bit shorts is faster than multiplying two ints.  Define MULTIPLIER
+ * as short on such a machine.  MULTIPLIER must be at least 16 bits wide.
+ */
+
+#ifndef MULTIPLIER
+#define MULTIPLIER  int		/* type for fastest integer multiply */
+#endif
+
+
+/* FAST_FLOAT should be either float or double, whichever is done faster
+ * by your compiler.  (Note that this type is only used in the floating point
+ * DCT routines, so it only matters if you've defined DCT_FLOAT_SUPPORTED.)
+ * Typically, float is faster in ANSI C compilers, while double is faster in
+ * pre-ANSI compilers (because they insist on converting to double anyway).
+ * The code below therefore chooses float if we have ANSI-style prototypes.
+ */
+
+#ifndef FAST_FLOAT
+#ifdef HAVE_PROTOTYPES
+#define FAST_FLOAT  float
+#else
+#define FAST_FLOAT  double
+#endif
+#endif
+
+#ifdef __GNUC__ /* KPIT gcc, optlib */
+#define  NO_GETENV  1
+#endif
+
+
+#endif /* JPEG_INTERNAL_OPTIONS */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/USB/uvc/jpeglib.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1182 @@
+/*
+ * jpeglib.h
+ *
+ * Copyright (C) 1991-1998, Thomas G. Lane.
+ * Modified 2002-2013 by Guido Vollbeding.
+ * This file is part of the Independent JPEG Group's software.
+ * For conditions of distribution and use, see the accompanying README file.
+ *
+ * This file defines the application interface for the JPEG library.
+ * Most applications using the library need only include this file,
+ * and perhaps jerror.h if they want to know the exact error codes.
+ */
+
+#ifndef JPEGLIB_H
+#define JPEGLIB_H
+
+/*
+ * First we include the configuration files that record how this
+ * installation of the JPEG library is set up.  jconfig.h can be
+ * generated automatically for many systems.  jmorecfg.h contains
+ * manual configuration options that most people need not worry about.
+ */
+
+#ifndef JCONFIG_INCLUDED	/* in case jinclude.h already did */
+#include "jconfig.h"		/* widely used configuration options */
+#endif
+#include "jmorecfg.h"		/* seldom changed options */
+
+
+#ifdef __cplusplus
+#ifndef DONT_USE_EXTERN_C
+extern "C" {
+#endif
+#endif
+
+/* Version IDs for the JPEG library.
+ * Might be useful for tests like "#if JPEG_LIB_VERSION >= 90".
+ */
+
+#define JPEG_LIB_VERSION        90	/* Compatibility version 9.0 */
+#define JPEG_LIB_VERSION_MAJOR  9
+#define JPEG_LIB_VERSION_MINOR  1
+
+
+/* Various constants determining the sizes of things.
+ * All of these are specified by the JPEG standard,
+ * so don't change them if you want to be compatible.
+ */
+
+#define DCTSIZE		    8	/* The basic DCT block is 8x8 coefficients */
+#define DCTSIZE2	    64	/* DCTSIZE squared; # of elements in a block */
+#define NUM_QUANT_TBLS      4	/* Quantization tables are numbered 0..3 */
+#define NUM_HUFF_TBLS       4	/* Huffman tables are numbered 0..3 */
+#define NUM_ARITH_TBLS      16	/* Arith-coding tables are numbered 0..15 */
+#define MAX_COMPS_IN_SCAN   4	/* JPEG limit on # of components in one scan */
+#define MAX_SAMP_FACTOR     4	/* JPEG limit on sampling factors */
+/* Unfortunately, some bozo at Adobe saw no reason to be bound by the standard;
+ * the PostScript DCT filter can emit files with many more than 10 blocks/MCU.
+ * If you happen to run across such a file, you can up D_MAX_BLOCKS_IN_MCU
+ * to handle it.  We even let you do this from the jconfig.h file.  However,
+ * we strongly discourage changing C_MAX_BLOCKS_IN_MCU; just because Adobe
+ * sometimes emits noncompliant files doesn't mean you should too.
+ */
+#define C_MAX_BLOCKS_IN_MCU   10 /* compressor's limit on blocks per MCU */
+#ifndef D_MAX_BLOCKS_IN_MCU
+#define D_MAX_BLOCKS_IN_MCU   10 /* decompressor's limit on blocks per MCU */
+#endif
+
+
+/* Data structures for images (arrays of samples and of DCT coefficients).
+ * On 80x86 machines, the image arrays are too big for near pointers,
+ * but the pointer arrays can fit in near memory.
+ */
+
+typedef JSAMPLE FAR *JSAMPROW;	/* ptr to one image row of pixel samples. */
+typedef JSAMPROW *JSAMPARRAY;	/* ptr to some rows (a 2-D sample array) */
+typedef JSAMPARRAY *JSAMPIMAGE;	/* a 3-D sample array: top index is color */
+
+typedef JCOEF JBLOCK[DCTSIZE2];	/* one block of coefficients */
+typedef JBLOCK FAR *JBLOCKROW;	/* pointer to one row of coefficient blocks */
+typedef JBLOCKROW *JBLOCKARRAY;		/* a 2-D array of coefficient blocks */
+typedef JBLOCKARRAY *JBLOCKIMAGE;	/* a 3-D array of coefficient blocks */
+
+typedef JCOEF FAR *JCOEFPTR;	/* useful in a couple of places */
+
+
+/* Types for JPEG compression parameters and working tables. */
+
+
+/* DCT coefficient quantization tables. */
+
+typedef struct {
+  /* This array gives the coefficient quantizers in natural array order
+   * (not the zigzag order in which they are stored in a JPEG DQT marker).
+   * CAUTION: IJG versions prior to v6a kept this array in zigzag order.
+   */
+  UINT16 quantval[DCTSIZE2];	/* quantization step for each coefficient */
+  /* This field is used only during compression.  It's initialized FALSE when
+   * the table is created, and set TRUE when it's been output to the file.
+   * You could suppress output of a table by setting this to TRUE.
+   * (See jpeg_suppress_tables for an example.)
+   */
+  boolean sent_table;		/* TRUE when table has been output */
+} JQUANT_TBL;
+
+
+/* Huffman coding tables. */
+
+typedef struct {
+  /* These two fields directly represent the contents of a JPEG DHT marker */
+  UINT8 bits[17];		/* bits[k] = # of symbols with codes of */
+				/* length k bits; bits[0] is unused */
+  UINT8 huffval[256];		/* The symbols, in order of incr code length */
+  /* This field is used only during compression.  It's initialized FALSE when
+   * the table is created, and set TRUE when it's been output to the file.
+   * You could suppress output of a table by setting this to TRUE.
+   * (See jpeg_suppress_tables for an example.)
+   */
+  boolean sent_table;		/* TRUE when table has been output */
+} JHUFF_TBL;
+
+
+/* Basic info about one component (color channel). */
+
+typedef struct {
+  /* These values are fixed over the whole image. */
+  /* For compression, they must be supplied by parameter setup; */
+  /* for decompression, they are read from the SOF marker. */
+  int component_id;		/* identifier for this component (0..255) */
+  int component_index;		/* its index in SOF or cinfo->comp_info[] */
+  int h_samp_factor;		/* horizontal sampling factor (1..4) */
+  int v_samp_factor;		/* vertical sampling factor (1..4) */
+  int quant_tbl_no;		/* quantization table selector (0..3) */
+  /* These values may vary between scans. */
+  /* For compression, they must be supplied by parameter setup; */
+  /* for decompression, they are read from the SOS marker. */
+  /* The decompressor output side may not use these variables. */
+  int dc_tbl_no;		/* DC entropy table selector (0..3) */
+  int ac_tbl_no;		/* AC entropy table selector (0..3) */
+  
+  /* Remaining fields should be treated as private by applications. */
+  
+  /* These values are computed during compression or decompression startup: */
+  /* Component's size in DCT blocks.
+   * Any dummy blocks added to complete an MCU are not counted; therefore
+   * these values do not depend on whether a scan is interleaved or not.
+   */
+  JDIMENSION width_in_blocks;
+  JDIMENSION height_in_blocks;
+  /* Size of a DCT block in samples,
+   * reflecting any scaling we choose to apply during the DCT step.
+   * Values from 1 to 16 are supported.
+   * Note that different components may receive different DCT scalings.
+   */
+  int DCT_h_scaled_size;
+  int DCT_v_scaled_size;
+  /* The downsampled dimensions are the component's actual, unpadded number
+   * of samples at the main buffer (preprocessing/compression interface);
+   * DCT scaling is included, so
+   * downsampled_width =
+   *   ceil(image_width * Hi/Hmax * DCT_h_scaled_size/block_size)
+   * and similarly for height.
+   */
+  JDIMENSION downsampled_width;	 /* actual width in samples */
+  JDIMENSION downsampled_height; /* actual height in samples */
+  /* For decompression, in cases where some of the components will be
+   * ignored (eg grayscale output from YCbCr image), we can skip most
+   * computations for the unused components.
+   * For compression, some of the components will need further quantization
+   * scale by factor of 2 after DCT (eg BG_YCC output from normal RGB input).
+   * The field is first set TRUE for decompression, FALSE for compression
+   * in initial_setup, and then adapted in color conversion setup.
+   */
+  boolean component_needed;
+
+  /* These values are computed before starting a scan of the component. */
+  /* The decompressor output side may not use these variables. */
+  int MCU_width;		/* number of blocks per MCU, horizontally */
+  int MCU_height;		/* number of blocks per MCU, vertically */
+  int MCU_blocks;		/* MCU_width * MCU_height */
+  int MCU_sample_width;	/* MCU width in samples: MCU_width * DCT_h_scaled_size */
+  int last_col_width;		/* # of non-dummy blocks across in last MCU */
+  int last_row_height;		/* # of non-dummy blocks down in last MCU */
+
+  /* Saved quantization table for component; NULL if none yet saved.
+   * See jdinput.c comments about the need for this information.
+   * This field is currently used only for decompression.
+   */
+  JQUANT_TBL * quant_table;
+
+  /* Private per-component storage for DCT or IDCT subsystem. */
+  void * dct_table;
+} jpeg_component_info;
+
+
+/* The script for encoding a multiple-scan file is an array of these: */
+
+typedef struct {
+  int comps_in_scan;		/* number of components encoded in this scan */
+  int component_index[MAX_COMPS_IN_SCAN]; /* their SOF/comp_info[] indexes */
+  int Ss, Se;			/* progressive JPEG spectral selection parms */
+  int Ah, Al;			/* progressive JPEG successive approx. parms */
+} jpeg_scan_info;
+
+/* The decompressor can save APPn and COM markers in a list of these: */
+
+typedef struct jpeg_marker_struct FAR * jpeg_saved_marker_ptr;
+
+struct jpeg_marker_struct {
+  jpeg_saved_marker_ptr next;	/* next in list, or NULL */
+  UINT8 marker;			/* marker code: JPEG_COM, or JPEG_APP0+n */
+  unsigned int original_length;	/* # bytes of data in the file */
+  unsigned int data_length;	/* # bytes of data saved at data[] */
+  JOCTET FAR * data;		/* the data contained in the marker */
+  /* the marker length word is not counted in data_length or original_length */
+};
+
+/* Known color spaces. */
+
+typedef enum {
+	JCS_UNKNOWN,		/* error/unspecified */
+	JCS_GRAYSCALE,		/* monochrome */
+	JCS_RGB,		/* red/green/blue, standard RGB (sRGB) */
+	JCS_YCbCr,		/* Y/Cb/Cr (also known as YUV), standard YCC */
+	JCS_CMYK,		/* C/M/Y/K */
+	JCS_YCCK,		/* Y/Cb/Cr/K */
+	JCS_BG_RGB,		/* big gamut red/green/blue, bg-sRGB */
+	JCS_BG_YCC		/* big gamut Y/Cb/Cr, bg-sYCC */
+} J_COLOR_SPACE;
+
+/* Supported color transforms. */
+
+typedef enum {
+	JCT_NONE           = 0,
+	JCT_SUBTRACT_GREEN = 1
+} J_COLOR_TRANSFORM;
+
+/* DCT/IDCT algorithm options. */
+
+typedef enum {
+	JDCT_ISLOW,		/* slow but accurate integer algorithm */
+	JDCT_IFAST,		/* faster, less accurate integer method */
+	JDCT_FLOAT		/* floating-point: accurate, fast on fast HW */
+} J_DCT_METHOD;
+
+#ifndef JDCT_DEFAULT		/* may be overridden in jconfig.h */
+#define JDCT_DEFAULT  JDCT_ISLOW
+#endif
+#ifndef JDCT_FASTEST		/* may be overridden in jconfig.h */
+#define JDCT_FASTEST  JDCT_IFAST
+#endif
+
+/* Dithering options for decompression. */
+
+typedef enum {
+	JDITHER_NONE,		/* no dithering */
+	JDITHER_ORDERED,	/* simple ordered dither */
+	JDITHER_FS		/* Floyd-Steinberg error diffusion dither */
+} J_DITHER_MODE;
+
+
+/* Common fields between JPEG compression and decompression master structs. */
+
+#define jpeg_common_fields \
+  struct jpeg_error_mgr * err;	/* Error handler module */\
+  struct jpeg_memory_mgr * mem;	/* Memory manager module */\
+  struct jpeg_progress_mgr * progress; /* Progress monitor, or NULL if none */\
+  void * client_data;		/* Available for use by application */\
+  boolean is_decompressor;	/* So common code can tell which is which */\
+  int global_state		/* For checking call sequence validity */
+
+/* Routines that are to be used by both halves of the library are declared
+ * to receive a pointer to this structure.  There are no actual instances of
+ * jpeg_common_struct, only of jpeg_compress_struct and jpeg_decompress_struct.
+ */
+struct jpeg_common_struct {
+  jpeg_common_fields;		/* Fields common to both master struct types */
+  /* Additional fields follow in an actual jpeg_compress_struct or
+   * jpeg_decompress_struct.  All three structs must agree on these
+   * initial fields!  (This would be a lot cleaner in C++.)
+   */
+};
+
+typedef struct jpeg_common_struct * j_common_ptr;
+typedef struct jpeg_compress_struct * j_compress_ptr;
+typedef struct jpeg_decompress_struct * j_decompress_ptr;
+
+
+/* Master record for a compression instance */
+
+struct jpeg_compress_struct {
+  jpeg_common_fields;		/* Fields shared with jpeg_decompress_struct */
+
+  /* Destination for compressed data */
+  struct jpeg_destination_mgr * dest;
+
+  /* Description of source image --- these fields must be filled in by
+   * outer application before starting compression.  in_color_space must
+   * be correct before you can even call jpeg_set_defaults().
+   */
+
+  JDIMENSION image_width;	/* input image width */
+  JDIMENSION image_height;	/* input image height */
+  int input_components;		/* # of color components in input image */
+  J_COLOR_SPACE in_color_space;	/* colorspace of input image */
+
+  double input_gamma;		/* image gamma of input image */
+
+  /* Compression parameters --- these fields must be set before calling
+   * jpeg_start_compress().  We recommend calling jpeg_set_defaults() to
+   * initialize everything to reasonable defaults, then changing anything
+   * the application specifically wants to change.  That way you won't get
+   * burnt when new parameters are added.  Also note that there are several
+   * helper routines to simplify changing parameters.
+   */
+
+  unsigned int scale_num, scale_denom; /* fraction by which to scale image */
+
+  JDIMENSION jpeg_width;	/* scaled JPEG image width */
+  JDIMENSION jpeg_height;	/* scaled JPEG image height */
+  /* Dimensions of actual JPEG image that will be written to file,
+   * derived from input dimensions by scaling factors above.
+   * These fields are computed by jpeg_start_compress().
+   * You can also use jpeg_calc_jpeg_dimensions() to determine these values
+   * in advance of calling jpeg_start_compress().
+   */
+
+  int data_precision;		/* bits of precision in image data */
+
+  int num_components;		/* # of color components in JPEG image */
+  J_COLOR_SPACE jpeg_color_space; /* colorspace of JPEG image */
+
+  jpeg_component_info * comp_info;
+  /* comp_info[i] describes component that appears i'th in SOF */
+
+  JQUANT_TBL * quant_tbl_ptrs[NUM_QUANT_TBLS];
+  int q_scale_factor[NUM_QUANT_TBLS];
+  /* ptrs to coefficient quantization tables, or NULL if not defined,
+   * and corresponding scale factors (percentage, initialized 100).
+   */
+
+  JHUFF_TBL * dc_huff_tbl_ptrs[NUM_HUFF_TBLS];
+  JHUFF_TBL * ac_huff_tbl_ptrs[NUM_HUFF_TBLS];
+  /* ptrs to Huffman coding tables, or NULL if not defined */
+
+  UINT8 arith_dc_L[NUM_ARITH_TBLS]; /* L values for DC arith-coding tables */
+  UINT8 arith_dc_U[NUM_ARITH_TBLS]; /* U values for DC arith-coding tables */
+  UINT8 arith_ac_K[NUM_ARITH_TBLS]; /* Kx values for AC arith-coding tables */
+
+  int num_scans;		/* # of entries in scan_info array */
+  const jpeg_scan_info * scan_info; /* script for multi-scan file, or NULL */
+  /* The default value of scan_info is NULL, which causes a single-scan
+   * sequential JPEG file to be emitted.  To create a multi-scan file,
+   * set num_scans and scan_info to point to an array of scan definitions.
+   */
+
+  boolean raw_data_in;		/* TRUE=caller supplies downsampled data */
+  boolean arith_code;		/* TRUE=arithmetic coding, FALSE=Huffman */
+  boolean optimize_coding;	/* TRUE=optimize entropy encoding parms */
+  boolean CCIR601_sampling;	/* TRUE=first samples are cosited */
+  boolean do_fancy_downsampling; /* TRUE=apply fancy downsampling */
+  int smoothing_factor;		/* 1..100, or 0 for no input smoothing */
+  J_DCT_METHOD dct_method;	/* DCT algorithm selector */
+
+  /* The restart interval can be specified in absolute MCUs by setting
+   * restart_interval, or in MCU rows by setting restart_in_rows
+   * (in which case the correct restart_interval will be figured
+   * for each scan).
+   */
+  unsigned int restart_interval; /* MCUs per restart, or 0 for no restart */
+  int restart_in_rows;		/* if > 0, MCU rows per restart interval */
+
+  /* Parameters controlling emission of special markers. */
+
+  boolean write_JFIF_header;	/* should a JFIF marker be written? */
+  UINT8 JFIF_major_version;	/* What to write for the JFIF version number */
+  UINT8 JFIF_minor_version;
+  /* These three values are not used by the JPEG code, merely copied */
+  /* into the JFIF APP0 marker.  density_unit can be 0 for unknown, */
+  /* 1 for dots/inch, or 2 for dots/cm.  Note that the pixel aspect */
+  /* ratio is defined by X_density/Y_density even when density_unit=0. */
+  UINT8 density_unit;		/* JFIF code for pixel size units */
+  UINT16 X_density;		/* Horizontal pixel density */
+  UINT16 Y_density;		/* Vertical pixel density */
+  boolean write_Adobe_marker;	/* should an Adobe marker be written? */
+
+  J_COLOR_TRANSFORM color_transform;
+  /* Color transform identifier, writes LSE marker if nonzero */
+
+  /* State variable: index of next scanline to be written to
+   * jpeg_write_scanlines().  Application may use this to control its
+   * processing loop, e.g., "while (next_scanline < image_height)".
+   */
+
+  JDIMENSION next_scanline;	/* 0 .. image_height-1  */
+
+  /* Remaining fields are known throughout compressor, but generally
+   * should not be touched by a surrounding application.
+   */
+
+  /*
+   * These fields are computed during compression startup
+   */
+  boolean progressive_mode;	/* TRUE if scan script uses progressive mode */
+  int max_h_samp_factor;	/* largest h_samp_factor */
+  int max_v_samp_factor;	/* largest v_samp_factor */
+
+  int min_DCT_h_scaled_size;	/* smallest DCT_h_scaled_size of any component */
+  int min_DCT_v_scaled_size;	/* smallest DCT_v_scaled_size of any component */
+
+  JDIMENSION total_iMCU_rows;	/* # of iMCU rows to be input to coef ctlr */
+  /* The coefficient controller receives data in units of MCU rows as defined
+   * for fully interleaved scans (whether the JPEG file is interleaved or not).
+   * There are v_samp_factor * DCTSIZE sample rows of each component in an
+   * "iMCU" (interleaved MCU) row.
+   */
+  
+  /*
+   * These fields are valid during any one scan.
+   * They describe the components and MCUs actually appearing in the scan.
+   */
+  int comps_in_scan;		/* # of JPEG components in this scan */
+  jpeg_component_info * cur_comp_info[MAX_COMPS_IN_SCAN];
+  /* *cur_comp_info[i] describes component that appears i'th in SOS */
+  
+  JDIMENSION MCUs_per_row;	/* # of MCUs across the image */
+  JDIMENSION MCU_rows_in_scan;	/* # of MCU rows in the image */
+  
+  int blocks_in_MCU;		/* # of DCT blocks per MCU */
+  int MCU_membership[C_MAX_BLOCKS_IN_MCU];
+  /* MCU_membership[i] is index in cur_comp_info of component owning */
+  /* i'th block in an MCU */
+
+  int Ss, Se, Ah, Al;		/* progressive JPEG parameters for scan */
+
+  int block_size;		/* the basic DCT block size: 1..16 */
+  const int * natural_order;	/* natural-order position array */
+  int lim_Se;			/* min( Se, DCTSIZE2-1 ) */
+
+  /*
+   * Links to compression subobjects (methods and private variables of modules)
+   */
+  struct jpeg_comp_master * master;
+  struct jpeg_c_main_controller * main;
+  struct jpeg_c_prep_controller * prep;
+  struct jpeg_c_coef_controller * coef;
+  struct jpeg_marker_writer * marker;
+  struct jpeg_color_converter * cconvert;
+  struct jpeg_downsampler * downsample;
+  struct jpeg_forward_dct * fdct;
+  struct jpeg_entropy_encoder * entropy;
+  jpeg_scan_info * script_space; /* workspace for jpeg_simple_progression */
+  int script_space_size;
+};
+
+
+/* Master record for a decompression instance */
+
+struct jpeg_decompress_struct {
+  jpeg_common_fields;		/* Fields shared with jpeg_compress_struct */
+
+  /* Source of compressed data */
+  struct jpeg_source_mgr * src;
+
+  /* Basic description of image --- filled in by jpeg_read_header(). */
+  /* Application may inspect these values to decide how to process image. */
+
+  JDIMENSION image_width;	/* nominal image width (from SOF marker) */
+  JDIMENSION image_height;	/* nominal image height */
+  int num_components;		/* # of color components in JPEG image */
+  J_COLOR_SPACE jpeg_color_space; /* colorspace of JPEG image */
+
+  /* Decompression processing parameters --- these fields must be set before
+   * calling jpeg_start_decompress().  Note that jpeg_read_header() initializes
+   * them to default values.
+   */
+
+  J_COLOR_SPACE out_color_space; /* colorspace for output */
+
+  unsigned int scale_num, scale_denom; /* fraction by which to scale image */
+
+  double output_gamma;		/* image gamma wanted in output */
+
+  boolean buffered_image;	/* TRUE=multiple output passes */
+  boolean raw_data_out;		/* TRUE=downsampled data wanted */
+
+  J_DCT_METHOD dct_method;	/* IDCT algorithm selector */
+  boolean do_fancy_upsampling;	/* TRUE=apply fancy upsampling */
+  boolean do_block_smoothing;	/* TRUE=apply interblock smoothing */
+
+  boolean quantize_colors;	/* TRUE=colormapped output wanted */
+  /* the following are ignored if not quantize_colors: */
+  J_DITHER_MODE dither_mode;	/* type of color dithering to use */
+  boolean two_pass_quantize;	/* TRUE=use two-pass color quantization */
+  int desired_number_of_colors;	/* max # colors to use in created colormap */
+  /* these are significant only in buffered-image mode: */
+  boolean enable_1pass_quant;	/* enable future use of 1-pass quantizer */
+  boolean enable_external_quant;/* enable future use of external colormap */
+  boolean enable_2pass_quant;	/* enable future use of 2-pass quantizer */
+
+  /* Description of actual output image that will be returned to application.
+   * These fields are computed by jpeg_start_decompress().
+   * You can also use jpeg_calc_output_dimensions() to determine these values
+   * in advance of calling jpeg_start_decompress().
+   */
+
+  JDIMENSION output_width;	/* scaled image width */
+  JDIMENSION output_height;	/* scaled image height */
+  int out_color_components;	/* # of color components in out_color_space */
+  int output_components;	/* # of color components returned */
+  /* output_components is 1 (a colormap index) when quantizing colors;
+   * otherwise it equals out_color_components.
+   */
+  int rec_outbuf_height;	/* min recommended height of scanline buffer */
+  /* If the buffer passed to jpeg_read_scanlines() is less than this many rows
+   * high, space and time will be wasted due to unnecessary data copying.
+   * Usually rec_outbuf_height will be 1 or 2, at most 4.
+   */
+
+  /* When quantizing colors, the output colormap is described by these fields.
+   * The application can supply a colormap by setting colormap non-NULL before
+   * calling jpeg_start_decompress; otherwise a colormap is created during
+   * jpeg_start_decompress or jpeg_start_output.
+   * The map has out_color_components rows and actual_number_of_colors columns.
+   */
+  int actual_number_of_colors;	/* number of entries in use */
+  JSAMPARRAY colormap;		/* The color map as a 2-D pixel array */
+
+  /* State variables: these variables indicate the progress of decompression.
+   * The application may examine these but must not modify them.
+   */
+
+  /* Row index of next scanline to be read from jpeg_read_scanlines().
+   * Application may use this to control its processing loop, e.g.,
+   * "while (output_scanline < output_height)".
+   */
+  JDIMENSION output_scanline;	/* 0 .. output_height-1  */
+
+  /* Current input scan number and number of iMCU rows completed in scan.
+   * These indicate the progress of the decompressor input side.
+   */
+  int input_scan_number;	/* Number of SOS markers seen so far */
+  JDIMENSION input_iMCU_row;	/* Number of iMCU rows completed */
+
+  /* The "output scan number" is the notional scan being displayed by the
+   * output side.  The decompressor will not allow output scan/row number
+   * to get ahead of input scan/row, but it can fall arbitrarily far behind.
+   */
+  int output_scan_number;	/* Nominal scan number being displayed */
+  JDIMENSION output_iMCU_row;	/* Number of iMCU rows read */
+
+  /* Current progression status.  coef_bits[c][i] indicates the precision
+   * with which component c's DCT coefficient i (in zigzag order) is known.
+   * It is -1 when no data has yet been received, otherwise it is the point
+   * transform (shift) value for the most recent scan of the coefficient
+   * (thus, 0 at completion of the progression).
+   * This pointer is NULL when reading a non-progressive file.
+   */
+  int (*coef_bits)[DCTSIZE2];	/* -1 or current Al value for each coef */
+
+  /* Internal JPEG parameters --- the application usually need not look at
+   * these fields.  Note that the decompressor output side may not use
+   * any parameters that can change between scans.
+   */
+
+  /* Quantization and Huffman tables are carried forward across input
+   * datastreams when processing abbreviated JPEG datastreams.
+   */
+
+  JQUANT_TBL * quant_tbl_ptrs[NUM_QUANT_TBLS];
+  /* ptrs to coefficient quantization tables, or NULL if not defined */
+
+  JHUFF_TBL * dc_huff_tbl_ptrs[NUM_HUFF_TBLS];
+  JHUFF_TBL * ac_huff_tbl_ptrs[NUM_HUFF_TBLS];
+  /* ptrs to Huffman coding tables, or NULL if not defined */
+
+  /* These parameters are never carried across datastreams, since they
+   * are given in SOF/SOS markers or defined to be reset by SOI.
+   */
+
+  int data_precision;		/* bits of precision in image data */
+
+  jpeg_component_info * comp_info;
+  /* comp_info[i] describes component that appears i'th in SOF */
+
+  boolean is_baseline;		/* TRUE if Baseline SOF0 encountered */
+  boolean progressive_mode;	/* TRUE if SOFn specifies progressive mode */
+  boolean arith_code;		/* TRUE=arithmetic coding, FALSE=Huffman */
+
+  UINT8 arith_dc_L[NUM_ARITH_TBLS]; /* L values for DC arith-coding tables */
+  UINT8 arith_dc_U[NUM_ARITH_TBLS]; /* U values for DC arith-coding tables */
+  UINT8 arith_ac_K[NUM_ARITH_TBLS]; /* Kx values for AC arith-coding tables */
+
+  unsigned int restart_interval; /* MCUs per restart interval, or 0 for no restart */
+
+  /* These fields record data obtained from optional markers recognized by
+   * the JPEG library.
+   */
+  boolean saw_JFIF_marker;	/* TRUE iff a JFIF APP0 marker was found */
+  /* Data copied from JFIF marker; only valid if saw_JFIF_marker is TRUE: */
+  UINT8 JFIF_major_version;	/* JFIF version number */
+  UINT8 JFIF_minor_version;
+  UINT8 density_unit;		/* JFIF code for pixel size units */
+  UINT16 X_density;		/* Horizontal pixel density */
+  UINT16 Y_density;		/* Vertical pixel density */
+  boolean saw_Adobe_marker;	/* TRUE iff an Adobe APP14 marker was found */
+  UINT8 Adobe_transform;	/* Color transform code from Adobe marker */
+
+  J_COLOR_TRANSFORM color_transform;
+  /* Color transform identifier derived from LSE marker, otherwise zero */
+
+  boolean CCIR601_sampling;	/* TRUE=first samples are cosited */
+
+  /* Aside from the specific data retained from APPn markers known to the
+   * library, the uninterpreted contents of any or all APPn and COM markers
+   * can be saved in a list for examination by the application.
+   */
+  jpeg_saved_marker_ptr marker_list; /* Head of list of saved markers */
+
+  /* Remaining fields are known throughout decompressor, but generally
+   * should not be touched by a surrounding application.
+   */
+
+  /*
+   * These fields are computed during decompression startup
+   */
+  int max_h_samp_factor;	/* largest h_samp_factor */
+  int max_v_samp_factor;	/* largest v_samp_factor */
+
+  int min_DCT_h_scaled_size;	/* smallest DCT_h_scaled_size of any component */
+  int min_DCT_v_scaled_size;	/* smallest DCT_v_scaled_size of any component */
+
+  JDIMENSION total_iMCU_rows;	/* # of iMCU rows in image */
+  /* The coefficient controller's input and output progress is measured in
+   * units of "iMCU" (interleaved MCU) rows.  These are the same as MCU rows
+   * in fully interleaved JPEG scans, but are used whether the scan is
+   * interleaved or not.  We define an iMCU row as v_samp_factor DCT block
+   * rows of each component.  Therefore, the IDCT output contains
+   * v_samp_factor*DCT_v_scaled_size sample rows of a component per iMCU row.
+   */
+
+  JSAMPLE * sample_range_limit; /* table for fast range-limiting */
+
+  /*
+   * These fields are valid during any one scan.
+   * They describe the components and MCUs actually appearing in the scan.
+   * Note that the decompressor output side must not use these fields.
+   */
+  int comps_in_scan;		/* # of JPEG components in this scan */
+  jpeg_component_info * cur_comp_info[MAX_COMPS_IN_SCAN];
+  /* *cur_comp_info[i] describes component that appears i'th in SOS */
+
+  JDIMENSION MCUs_per_row;	/* # of MCUs across the image */
+  JDIMENSION MCU_rows_in_scan;	/* # of MCU rows in the image */
+
+  int blocks_in_MCU;		/* # of DCT blocks per MCU */
+  int MCU_membership[D_MAX_BLOCKS_IN_MCU];
+  /* MCU_membership[i] is index in cur_comp_info of component owning */
+  /* i'th block in an MCU */
+
+  int Ss, Se, Ah, Al;		/* progressive JPEG parameters for scan */
+
+  /* These fields are derived from Se of first SOS marker.
+   */
+  int block_size;		/* the basic DCT block size: 1..16 */
+  const int * natural_order; /* natural-order position array for entropy decode */
+  int lim_Se;			/* min( Se, DCTSIZE2-1 ) for entropy decode */
+
+  /* This field is shared between entropy decoder and marker parser.
+   * It is either zero or the code of a JPEG marker that has been
+   * read from the data source, but has not yet been processed.
+   */
+  int unread_marker;
+
+  /*
+   * Links to decompression subobjects (methods, private variables of modules)
+   */
+  struct jpeg_decomp_master * master;
+  struct jpeg_d_main_controller * main;
+  struct jpeg_d_coef_controller * coef;
+  struct jpeg_d_post_controller * post;
+  struct jpeg_input_controller * inputctl;
+  struct jpeg_marker_reader * marker;
+  struct jpeg_entropy_decoder * entropy;
+  struct jpeg_inverse_dct * idct;
+  struct jpeg_upsampler * upsample;
+  struct jpeg_color_deconverter * cconvert;
+  struct jpeg_color_quantizer * cquantize;
+};
+
+
+/* "Object" declarations for JPEG modules that may be supplied or called
+ * directly by the surrounding application.
+ * As with all objects in the JPEG library, these structs only define the
+ * publicly visible methods and state variables of a module.  Additional
+ * private fields may exist after the public ones.
+ */
+
+
+/* Error handler object */
+
+struct jpeg_error_mgr {
+  /* Error exit handler: does not return to caller */
+  JMETHOD(noreturn_t, error_exit, (j_common_ptr cinfo));
+  /* Conditionally emit a trace or warning message */
+  JMETHOD(void, emit_message, (j_common_ptr cinfo, int msg_level));
+  /* Routine that actually outputs a trace or error message */
+  JMETHOD(void, output_message, (j_common_ptr cinfo));
+  /* Format a message string for the most recent JPEG error or message */
+  JMETHOD(void, format_message, (j_common_ptr cinfo, char * buffer));
+#define JMSG_LENGTH_MAX  200	/* recommended size of format_message buffer */
+  /* Reset error state variables at start of a new image */
+  JMETHOD(void, reset_error_mgr, (j_common_ptr cinfo));
+  
+  /* The message ID code and any parameters are saved here.
+   * A message can have one string parameter or up to 8 int parameters.
+   */
+  int msg_code;
+#define JMSG_STR_PARM_MAX  80
+  union {
+    int i[8];
+    char s[JMSG_STR_PARM_MAX];
+  } msg_parm;
+  
+  /* Standard state variables for error facility */
+  
+  int trace_level;		/* max msg_level that will be displayed */
+  
+  /* For recoverable corrupt-data errors, we emit a warning message,
+   * but keep going unless emit_message chooses to abort.  emit_message
+   * should count warnings in num_warnings.  The surrounding application
+   * can check for bad data by seeing if num_warnings is nonzero at the
+   * end of processing.
+   */
+  long num_warnings;		/* number of corrupt-data warnings */
+
+  /* These fields point to the table(s) of error message strings.
+   * An application can change the table pointer to switch to a different
+   * message list (typically, to change the language in which errors are
+   * reported).  Some applications may wish to add additional error codes
+   * that will be handled by the JPEG library error mechanism; the second
+   * table pointer is used for this purpose.
+   *
+   * First table includes all errors generated by JPEG library itself.
+   * Error code 0 is reserved for a "no such error string" message.
+   */
+  const char * const * jpeg_message_table; /* Library errors */
+  int last_jpeg_message;    /* Table contains strings 0..last_jpeg_message */
+  /* Second table can be added by application (see cjpeg/djpeg for example).
+   * It contains strings numbered first_addon_message..last_addon_message.
+   */
+  const char * const * addon_message_table; /* Non-library errors */
+  int first_addon_message;	/* code for first string in addon table */
+  int last_addon_message;	/* code for last string in addon table */
+};
+
+
+/* Progress monitor object */
+
+struct jpeg_progress_mgr {
+  JMETHOD(void, progress_monitor, (j_common_ptr cinfo));
+
+  long pass_counter;		/* work units completed in this pass */
+  long pass_limit;		/* total number of work units in this pass */
+  int completed_passes;		/* passes completed so far */
+  int total_passes;		/* total number of passes expected */
+};
+
+
+/* Data destination object for compression */
+
+struct jpeg_destination_mgr {
+  JOCTET * next_output_byte;	/* => next byte to write in buffer */
+  size_t free_in_buffer;	/* # of byte spaces remaining in buffer */
+
+  JMETHOD(void, init_destination, (j_compress_ptr cinfo));
+  JMETHOD(boolean, empty_output_buffer, (j_compress_ptr cinfo));
+  JMETHOD(void, term_destination, (j_compress_ptr cinfo));
+};
+
+
+/* Data source object for decompression */
+
+struct jpeg_source_mgr {
+  const JOCTET * next_input_byte; /* => next byte to read from buffer */
+  size_t bytes_in_buffer;	/* # of bytes remaining in buffer */
+
+  JMETHOD(void, init_source, (j_decompress_ptr cinfo));
+  JMETHOD(boolean, fill_input_buffer, (j_decompress_ptr cinfo));
+  JMETHOD(void, skip_input_data, (j_decompress_ptr cinfo, long num_bytes));
+  JMETHOD(boolean, resync_to_restart, (j_decompress_ptr cinfo, int desired));
+  JMETHOD(void, term_source, (j_decompress_ptr cinfo));
+};
+
+
+/* Memory manager object.
+ * Allocates "small" objects (a few K total), "large" objects (tens of K),
+ * and "really big" objects (virtual arrays with backing store if needed).
+ * The memory manager does not allow individual objects to be freed; rather,
+ * each created object is assigned to a pool, and whole pools can be freed
+ * at once.  This is faster and more convenient than remembering exactly what
+ * to free, especially where malloc()/free() are not too speedy.
+ * NB: alloc routines never return NULL.  They exit to error_exit if not
+ * successful.
+ */
+
+#define JPOOL_PERMANENT	0	/* lasts until master record is destroyed */
+#define JPOOL_IMAGE	1	/* lasts until done with image/datastream */
+#define JPOOL_NUMPOOLS	2
+
+typedef struct jvirt_sarray_control * jvirt_sarray_ptr;
+typedef struct jvirt_barray_control * jvirt_barray_ptr;
+
+
+struct jpeg_memory_mgr {
+  /* Method pointers */
+  JMETHOD(void *, alloc_small, (j_common_ptr cinfo, int pool_id,
+				size_t sizeofobject));
+  JMETHOD(void FAR *, alloc_large, (j_common_ptr cinfo, int pool_id,
+				     size_t sizeofobject));
+  JMETHOD(JSAMPARRAY, alloc_sarray, (j_common_ptr cinfo, int pool_id,
+				     JDIMENSION samplesperrow,
+				     JDIMENSION numrows));
+  JMETHOD(JBLOCKARRAY, alloc_barray, (j_common_ptr cinfo, int pool_id,
+				      JDIMENSION blocksperrow,
+				      JDIMENSION numrows));
+  JMETHOD(jvirt_sarray_ptr, request_virt_sarray, (j_common_ptr cinfo,
+						  int pool_id,
+						  boolean pre_zero,
+						  JDIMENSION samplesperrow,
+						  JDIMENSION numrows,
+						  JDIMENSION maxaccess));
+  JMETHOD(jvirt_barray_ptr, request_virt_barray, (j_common_ptr cinfo,
+						  int pool_id,
+						  boolean pre_zero,
+						  JDIMENSION blocksperrow,
+						  JDIMENSION numrows,
+						  JDIMENSION maxaccess));
+  JMETHOD(void, realize_virt_arrays, (j_common_ptr cinfo));
+  JMETHOD(JSAMPARRAY, access_virt_sarray, (j_common_ptr cinfo,
+					   jvirt_sarray_ptr ptr,
+					   JDIMENSION start_row,
+					   JDIMENSION num_rows,
+					   boolean writable));
+  JMETHOD(JBLOCKARRAY, access_virt_barray, (j_common_ptr cinfo,
+					    jvirt_barray_ptr ptr,
+					    JDIMENSION start_row,
+					    JDIMENSION num_rows,
+					    boolean writable));
+  JMETHOD(void, free_pool, (j_common_ptr cinfo, int pool_id));
+  JMETHOD(void, self_destruct, (j_common_ptr cinfo));
+
+  /* Limit on memory allocation for this JPEG object.  (Note that this is
+   * merely advisory, not a guaranteed maximum; it only affects the space
+   * used for virtual-array buffers.)  May be changed by outer application
+   * after creating the JPEG object.
+   */
+  long max_memory_to_use;
+
+  /* Maximum allocation request accepted by alloc_large. */
+  long max_alloc_chunk;
+};
+
+
+/* Routine signature for application-supplied marker processing methods.
+ * Need not pass marker code since it is stored in cinfo->unread_marker.
+ */
+typedef JMETHOD(boolean, jpeg_marker_parser_method, (j_decompress_ptr cinfo));
+
+
+/* Declarations for routines called by application.
+ * The JPP macro hides prototype parameters from compilers that can't cope.
+ * Note JPP requires double parentheses.
+ */
+
+#ifdef HAVE_PROTOTYPES
+#define JPP(arglist)	arglist
+#else
+#define JPP(arglist)	()
+#endif
+
+
+/* Short forms of external names for systems with brain-damaged linkers.
+ * We shorten external names to be unique in the first six letters, which
+ * is good enough for all known systems.
+ * (If your compiler itself needs names to be unique in less than 15 
+ * characters, you are out of luck.  Get a better compiler.)
+ */
+
+#ifdef NEED_SHORT_EXTERNAL_NAMES
+#define jpeg_std_error		jStdError
+#define jpeg_CreateCompress	jCreaCompress
+#define jpeg_CreateDecompress	jCreaDecompress
+#define jpeg_destroy_compress	jDestCompress
+#define jpeg_destroy_decompress	jDestDecompress
+#define jpeg_stdio_dest		jStdDest
+#define jpeg_stdio_src		jStdSrc
+#define jpeg_mem_dest		jMemDest
+#define jpeg_mem_src		jMemSrc
+#define jpeg_set_defaults	jSetDefaults
+#define jpeg_set_colorspace	jSetColorspace
+#define jpeg_default_colorspace	jDefColorspace
+#define jpeg_set_quality	jSetQuality
+#define jpeg_set_linear_quality	jSetLQuality
+#define jpeg_default_qtables	jDefQTables
+#define jpeg_add_quant_table	jAddQuantTable
+#define jpeg_quality_scaling	jQualityScaling
+#define jpeg_simple_progression	jSimProgress
+#define jpeg_suppress_tables	jSuppressTables
+#define jpeg_alloc_quant_table	jAlcQTable
+#define jpeg_alloc_huff_table	jAlcHTable
+#define jpeg_start_compress	jStrtCompress
+#define jpeg_write_scanlines	jWrtScanlines
+#define jpeg_finish_compress	jFinCompress
+#define jpeg_calc_jpeg_dimensions	jCjpegDimensions
+#define jpeg_write_raw_data	jWrtRawData
+#define jpeg_write_marker	jWrtMarker
+#define jpeg_write_m_header	jWrtMHeader
+#define jpeg_write_m_byte	jWrtMByte
+#define jpeg_write_tables	jWrtTables
+#define jpeg_read_header	jReadHeader
+#define jpeg_start_decompress	jStrtDecompress
+#define jpeg_read_scanlines	jReadScanlines
+#define jpeg_finish_decompress	jFinDecompress
+#define jpeg_read_raw_data	jReadRawData
+#define jpeg_has_multiple_scans	jHasMultScn
+#define jpeg_start_output	jStrtOutput
+#define jpeg_finish_output	jFinOutput
+#define jpeg_input_complete	jInComplete
+#define jpeg_new_colormap	jNewCMap
+#define jpeg_consume_input	jConsumeInput
+#define jpeg_core_output_dimensions	jCoreDimensions
+#define jpeg_calc_output_dimensions	jCalcDimensions
+#define jpeg_save_markers	jSaveMarkers
+#define jpeg_set_marker_processor	jSetMarker
+#define jpeg_read_coefficients	jReadCoefs
+#define jpeg_write_coefficients	jWrtCoefs
+#define jpeg_copy_critical_parameters	jCopyCrit
+#define jpeg_abort_compress	jAbrtCompress
+#define jpeg_abort_decompress	jAbrtDecompress
+#define jpeg_abort		jAbort
+#define jpeg_destroy		jDestroy
+#define jpeg_resync_to_restart	jResyncRestart
+#endif /* NEED_SHORT_EXTERNAL_NAMES */
+
+
+/* Default error-management setup */
+EXTERN(struct jpeg_error_mgr *) jpeg_std_error
+	JPP((struct jpeg_error_mgr * err));
+
+/* Initialization of JPEG compression objects.
+ * jpeg_create_compress() and jpeg_create_decompress() are the exported
+ * names that applications should call.  These expand to calls on
+ * jpeg_CreateCompress and jpeg_CreateDecompress with additional information
+ * passed for version mismatch checking.
+ * NB: you must set up the error-manager BEFORE calling jpeg_create_xxx.
+ */
+#define jpeg_create_compress(cinfo) \
+    jpeg_CreateCompress((cinfo), JPEG_LIB_VERSION, \
+			(size_t) sizeof(struct jpeg_compress_struct))
+#define jpeg_create_decompress(cinfo) \
+    jpeg_CreateDecompress((cinfo), JPEG_LIB_VERSION, \
+			  (size_t) sizeof(struct jpeg_decompress_struct))
+EXTERN(void) jpeg_CreateCompress JPP((j_compress_ptr cinfo,
+				      int version, size_t structsize));
+EXTERN(void) jpeg_CreateDecompress JPP((j_decompress_ptr cinfo,
+					int version, size_t structsize));
+/* Destruction of JPEG compression objects */
+EXTERN(void) jpeg_destroy_compress JPP((j_compress_ptr cinfo));
+EXTERN(void) jpeg_destroy_decompress JPP((j_decompress_ptr cinfo));
+
+/* Standard data source and destination managers: stdio streams. */
+/* Caller is responsible for opening the file before and closing after. */
+#ifdef HAVE_FILE_P_H
+EXTERN(void) jpeg_stdio_dest JPP((j_compress_ptr cinfo, FILE * outfile));
+EXTERN(void) jpeg_stdio_src JPP((j_decompress_ptr cinfo, FILE * infile));
+#endif
+
+/* Data source and destination managers: memory buffers. */
+EXTERN(void) jpeg_mem_dest JPP((j_compress_ptr cinfo,
+			       unsigned char ** outbuffer,
+			       unsigned long * outsize));
+EXTERN(void) jpeg_mem_src JPP((j_decompress_ptr cinfo,
+			      unsigned char * inbuffer,
+			      unsigned long insize));
+
+/* Default parameter setup for compression */
+EXTERN(void) jpeg_set_defaults JPP((j_compress_ptr cinfo));
+/* Compression parameter setup aids */
+EXTERN(void) jpeg_set_colorspace JPP((j_compress_ptr cinfo,
+				      J_COLOR_SPACE colorspace));
+EXTERN(void) jpeg_default_colorspace JPP((j_compress_ptr cinfo));
+EXTERN(void) jpeg_set_quality JPP((j_compress_ptr cinfo, int quality,
+				   boolean force_baseline));
+EXTERN(void) jpeg_set_linear_quality JPP((j_compress_ptr cinfo,
+					  int scale_factor,
+					  boolean force_baseline));
+EXTERN(void) jpeg_default_qtables JPP((j_compress_ptr cinfo,
+				       boolean force_baseline));
+EXTERN(void) jpeg_add_quant_table JPP((j_compress_ptr cinfo, int which_tbl,
+				       const unsigned int *basic_table,
+				       int scale_factor,
+				       boolean force_baseline));
+EXTERN(int) jpeg_quality_scaling JPP((int quality));
+EXTERN(void) jpeg_simple_progression JPP((j_compress_ptr cinfo));
+EXTERN(void) jpeg_suppress_tables JPP((j_compress_ptr cinfo,
+				       boolean suppress));
+EXTERN(JQUANT_TBL *) jpeg_alloc_quant_table JPP((j_common_ptr cinfo));
+EXTERN(JHUFF_TBL *) jpeg_alloc_huff_table JPP((j_common_ptr cinfo));
+
+/* Main entry points for compression */
+EXTERN(void) jpeg_start_compress JPP((j_compress_ptr cinfo,
+				      boolean write_all_tables));
+EXTERN(JDIMENSION) jpeg_write_scanlines JPP((j_compress_ptr cinfo,
+					     JSAMPARRAY scanlines,
+					     JDIMENSION num_lines));
+EXTERN(void) jpeg_finish_compress JPP((j_compress_ptr cinfo));
+
+/* Precalculate JPEG dimensions for current compression parameters. */
+EXTERN(void) jpeg_calc_jpeg_dimensions JPP((j_compress_ptr cinfo));
+
+/* Replaces jpeg_write_scanlines when writing raw downsampled data. */
+EXTERN(JDIMENSION) jpeg_write_raw_data JPP((j_compress_ptr cinfo,
+					    JSAMPIMAGE data,
+					    JDIMENSION num_lines));
+
+/* Write a special marker.  See libjpeg.txt concerning safe usage. */
+EXTERN(void) jpeg_write_marker
+	JPP((j_compress_ptr cinfo, int marker,
+	     const JOCTET * dataptr, unsigned int datalen));
+/* Same, but piecemeal. */
+EXTERN(void) jpeg_write_m_header
+	JPP((j_compress_ptr cinfo, int marker, unsigned int datalen));
+EXTERN(void) jpeg_write_m_byte
+	JPP((j_compress_ptr cinfo, int val));
+
+/* Alternate compression function: just write an abbreviated table file */
+EXTERN(void) jpeg_write_tables JPP((j_compress_ptr cinfo));
+
+/* Decompression startup: read start of JPEG datastream to see what's there */
+EXTERN(int) jpeg_read_header JPP((j_decompress_ptr cinfo,
+				  boolean require_image));
+/* Return value is one of: */
+#define JPEG_SUSPENDED		0 /* Suspended due to lack of input data */
+#define JPEG_HEADER_OK		1 /* Found valid image datastream */
+#define JPEG_HEADER_TABLES_ONLY	2 /* Found valid table-specs-only datastream */
+/* If you pass require_image = TRUE (normal case), you need not check for
+ * a TABLES_ONLY return code; an abbreviated file will cause an error exit.
+ * JPEG_SUSPENDED is only possible if you use a data source module that can
+ * give a suspension return (the stdio source module doesn't).
+ */
+
+/* Main entry points for decompression */
+EXTERN(boolean) jpeg_start_decompress JPP((j_decompress_ptr cinfo));
+EXTERN(JDIMENSION) jpeg_read_scanlines JPP((j_decompress_ptr cinfo,
+					    JSAMPARRAY scanlines,
+					    JDIMENSION max_lines));
+EXTERN(boolean) jpeg_finish_decompress JPP((j_decompress_ptr cinfo));
+
+/* Replaces jpeg_read_scanlines when reading raw downsampled data. */
+EXTERN(JDIMENSION) jpeg_read_raw_data JPP((j_decompress_ptr cinfo,
+					   JSAMPIMAGE data,
+					   JDIMENSION max_lines));
+
+/* Additional entry points for buffered-image mode. */
+EXTERN(boolean) jpeg_has_multiple_scans JPP((j_decompress_ptr cinfo));
+EXTERN(boolean) jpeg_start_output JPP((j_decompress_ptr cinfo,
+				       int scan_number));
+EXTERN(boolean) jpeg_finish_output JPP((j_decompress_ptr cinfo));
+EXTERN(boolean) jpeg_input_complete JPP((j_decompress_ptr cinfo));
+EXTERN(void) jpeg_new_colormap JPP((j_decompress_ptr cinfo));
+EXTERN(int) jpeg_consume_input JPP((j_decompress_ptr cinfo));
+/* Return value is one of: */
+/* #define JPEG_SUSPENDED	0    Suspended due to lack of input data */
+#define JPEG_REACHED_SOS	1 /* Reached start of new scan */
+#define JPEG_REACHED_EOI	2 /* Reached end of image */
+#define JPEG_ROW_COMPLETED	3 /* Completed one iMCU row */
+#define JPEG_SCAN_COMPLETED	4 /* Completed last iMCU row of a scan */
+
+/* Precalculate output dimensions for current decompression parameters. */
+EXTERN(void) jpeg_core_output_dimensions JPP((j_decompress_ptr cinfo));
+EXTERN(void) jpeg_calc_output_dimensions JPP((j_decompress_ptr cinfo));
+
+/* Control saving of COM and APPn markers into marker_list. */
+EXTERN(void) jpeg_save_markers
+	JPP((j_decompress_ptr cinfo, int marker_code,
+	     unsigned int length_limit));
+
+/* Install a special processing method for COM or APPn markers. */
+EXTERN(void) jpeg_set_marker_processor
+	JPP((j_decompress_ptr cinfo, int marker_code,
+	     jpeg_marker_parser_method routine));
+
+/* Read or write raw DCT coefficients --- useful for lossless transcoding. */
+EXTERN(jvirt_barray_ptr *) jpeg_read_coefficients JPP((j_decompress_ptr cinfo));
+EXTERN(void) jpeg_write_coefficients JPP((j_compress_ptr cinfo,
+					  jvirt_barray_ptr * coef_arrays));
+EXTERN(void) jpeg_copy_critical_parameters JPP((j_decompress_ptr srcinfo,
+						j_compress_ptr dstinfo));
+
+/* If you choose to abort compression or decompression before completing
+ * jpeg_finish_(de)compress, then you need to clean up to release memory,
+ * temporary files, etc.  You can just call jpeg_destroy_(de)compress
+ * if you're done with the JPEG object, but if you want to clean it up and
+ * reuse it, call this:
+ */
+EXTERN(void) jpeg_abort_compress JPP((j_compress_ptr cinfo));
+EXTERN(void) jpeg_abort_decompress JPP((j_decompress_ptr cinfo));
+
+/* Generic versions of jpeg_abort and jpeg_destroy that work on either
+ * flavor of JPEG object.  These may be more convenient in some places.
+ */
+EXTERN(void) jpeg_abort JPP((j_common_ptr cinfo));
+EXTERN(void) jpeg_destroy JPP((j_common_ptr cinfo));
+
+/* Default restart-marker-resync procedure for use by data source modules */
+EXTERN(boolean) jpeg_resync_to_restart JPP((j_decompress_ptr cinfo,
+					    int desired));
+
+
+/* These marker codes are exported since applications and data source modules
+ * are likely to want to use them.
+ */
+
+#define JPEG_RST0	0xD0	/* RST0 marker code */
+#define JPEG_EOI	0xD9	/* EOI marker code */
+#define JPEG_APP0	0xE0	/* APP0 marker code */
+#define JPEG_COM	0xFE	/* COM marker code */
+
+
+/* If we have a brain-damaged compiler that emits warnings (or worse, errors)
+ * for structure definitions that are never filled in, keep it quiet by
+ * supplying dummy definitions for the various substructures.
+ */
+
+#ifdef INCOMPLETE_TYPES_BROKEN
+#ifndef JPEG_INTERNALS		/* will be defined in jpegint.h */
+struct jvirt_sarray_control { long dummy; };
+struct jvirt_barray_control { long dummy; };
+struct jpeg_comp_master { long dummy; };
+struct jpeg_c_main_controller { long dummy; };
+struct jpeg_c_prep_controller { long dummy; };
+struct jpeg_c_coef_controller { long dummy; };
+struct jpeg_marker_writer { long dummy; };
+struct jpeg_color_converter { long dummy; };
+struct jpeg_downsampler { long dummy; };
+struct jpeg_forward_dct { long dummy; };
+struct jpeg_entropy_encoder { long dummy; };
+struct jpeg_decomp_master { long dummy; };
+struct jpeg_d_main_controller { long dummy; };
+struct jpeg_d_coef_controller { long dummy; };
+struct jpeg_d_post_controller { long dummy; };
+struct jpeg_input_controller { long dummy; };
+struct jpeg_marker_reader { long dummy; };
+struct jpeg_entropy_decoder { long dummy; };
+struct jpeg_inverse_dct { long dummy; };
+struct jpeg_upsampler { long dummy; };
+struct jpeg_color_deconverter { long dummy; };
+struct jpeg_color_quantizer { long dummy; };
+#endif /* JPEG_INTERNALS */
+#endif /* INCOMPLETE_TYPES_BROKEN */
+
+
+/*
+ * The JPEG library modules define JPEG_INTERNALS before including this file.
+ * The internal structure declarations are read only when that is true.
+ * Applications using the library should not include jpegint.h, but may wish
+ * to include jerror.h.
+ */
+
+#ifdef JPEG_INTERNALS
+#include "jpegint.h"		/* fetch private declarations */
+#include "jerror.h"		/* fetch error codes too */
+#endif
+
+#ifdef __cplusplus
+#ifndef DONT_USE_EXTERN_C
+}
+#endif
+#endif
+
+#endif /* JPEGLIB_H */
Binary file USB/uvc/libjpeg.ar has changed
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/env/test_env.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,93 @@
+#include "test_env.h"
+
+// Const strings used in test_end
+const char* TEST_ENV_START = "start";
+const char* TEST_ENV_SUCCESS = "success";
+const char* TEST_ENV_FAILURE = "failure";
+const char* TEST_ENV_MEASURE = "measure";
+const char* TEST_ENV_END = "end";
+
+
+static void led_blink(PinName led, float delay)
+{
+    if (led != NC) {
+        DigitalOut myled(led);
+        while (1) {
+            myled = !myled;
+            wait(delay);
+        }
+    }
+    while(1);
+}
+
+void notify_start()
+{
+    printf("{{%s}}" NL, TEST_ENV_START);
+}
+
+void notify_performance_coefficient(const char* measurement_name, const int value)
+{
+    printf("{{%s;%s;%d}}" RCNL, TEST_ENV_MEASURE, measurement_name, value);
+}
+
+void notify_performance_coefficient(const char* measurement_name, const unsigned int value)
+{
+    printf("{{%s;%s;%u}}" RCNL, TEST_ENV_MEASURE, measurement_name, value);
+}
+
+void notify_performance_coefficient(const char* measurement_name, const double value)
+{
+    printf("{{%s;%s;%f}}" RCNL, TEST_ENV_MEASURE, measurement_name, value);
+}
+
+void notify_completion(bool success)
+{
+    printf("{{%s}}" NL "{{%s}}" NL, success ? TEST_ENV_SUCCESS : TEST_ENV_FAILURE, TEST_ENV_END);
+    led_blink(LED1, success ? 1.0 : 0.1);
+}
+
+bool notify_completion_str(bool success, char* buffer)
+{
+    bool result = false;
+    if (buffer) {
+        sprintf(buffer, "{{%s}}" NL "{{%s}}" NL, success ? TEST_ENV_SUCCESS : TEST_ENV_FAILURE, TEST_ENV_END);
+        result = true;
+    }
+    return result;
+}
+
+// Host test auto-detection API
+void notify_host_test_name(const char *host_test) {
+    if (host_test) {
+        printf("{{host_test_name;%s}}" NL, host_test);
+    }
+}
+
+void notify_timeout(int timeout) {
+    printf("{{timeout;%d}}" NL, timeout);
+}
+
+void notify_test_id(const char *test_id) {
+    if (test_id) {
+        printf("{{test_id;%s}}" NL, test_id);
+    }
+}
+
+void notify_test_description(const char *description) {
+    if (description) {
+        printf("{{description;%s}}" NL, description);
+    }
+}
+
+
+// -DMBED_BUILD_TIMESTAMP=1406208182.13
+unsigned int testenv_randseed()
+{
+    unsigned int seed = 0;
+#ifdef MBED_BUILD_TIMESTAMP
+    long long_seed = static_cast<long>(MBED_BUILD_TIMESTAMP);
+    seed = long_seed & 0xFFFFFFFF;
+#endif /* MBED_BUILD_TIMESTAMP */
+    return seed;
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/env/test_env.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,75 @@
+#ifndef TEST_ENV_H_
+#define TEST_ENV_H_
+
+#include <stdio.h>
+#include "mbed.h"
+
+#define NL "\n"
+#define RCNL "\r\n"
+
+// Const strings used in test_end
+extern const char* TEST_ENV_START;
+extern const char* TEST_ENV_SUCCESS;
+extern const char* TEST_ENV_FAILURE;
+extern const char* TEST_ENV_MEASURE;
+extern const char* TEST_ENV_END;
+
+// Test result related notification functions
+void notify_start();
+void notify_completion(bool success);
+bool notify_completion_str(bool success, char* buffer);
+void notify_performance_coefficient(const char* measurement_name, const int value);
+void notify_performance_coefficient(const char* measurement_name, const unsigned int value);
+void notify_performance_coefficient(const char* measurement_name, const double value);
+
+// Host test auto-detection API
+void notify_host_test_name(const char *host_test);
+void notify_timeout(int timeout);
+void notify_test_id(const char *test_id);
+void notify_test_description(const char *description);
+
+// Host test auto-detection API
+#define MBED_HOSTTEST_START(TESTID)      notify_test_id(TESTID); notify_start()
+#define MBED_HOSTTEST_SELECT(NAME)       notify_host_test_name(#NAME)
+#define MBED_HOSTTEST_TIMEOUT(SECONDS)   notify_timeout(SECONDS)
+#define MBED_HOSTTEST_DESCRIPTION(DESC)  notify_test_description(#DESC)
+#define MBED_HOSTTEST_RESULT(RESULT)     notify_completion(RESULT)
+
+/**
+    Test auto-detection preamble example:
+    main() {
+        MBED_HOSTTEST_TIMEOUT(10);
+        MBED_HOSTTEST_SELECT( host_test );
+        MBED_HOSTTEST_DESCRIPTION(Hello World);
+        MBED_HOSTTEST_START("MBED_10");
+        // Proper 'host_test.py' should take over supervising of this test
+
+        // Test code
+        bool result = ...;
+
+        MBED_HOSTTEST_RESULT(result);
+    }
+*/
+
+
+// Test functionality useful during testing
+unsigned int testenv_randseed();
+
+// Macros, unit test like to provide basic comparisons
+#define TESTENV_STRCMP(GIVEN,EXPECTED) (strcmp(GIVEN,EXPECTED) == 0)
+
+// macros passed via test suite
+#ifndef TEST_SUITE_TARGET_NAME
+#define TEST_SUITE_TARGET_NAME "Unknown"
+#endif
+
+#ifndef TEST_SUITE_TEST_ID
+#define TEST_SUITE_TEST_ID "Unknown"
+#endif
+
+#ifndef TEST_SUITE_UUID
+#define TEST_SUITE_UUID "Unknown"
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/AnalogIn.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,129 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_H
+#define MBED_ANALOGIN_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGIN
+
+#include "analogin_api.h"
+#include "SingletonPtr.h"
+#include "PlatformMutex.h"
+
+namespace mbed {
+
+/** An analog input, used for reading the voltage on a pin
+ *
+ * @Note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Print messages when the AnalogIn is greater than 50%
+ *
+ * #include "mbed.h"
+ *
+ * AnalogIn temperature(p20);
+ *
+ * int main() {
+ *     while(1) {
+ *         if(temperature > 0.5) {
+ *             printf("Too hot! (%f)", temperature.read());
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class AnalogIn {
+
+public:
+
+    /** Create an AnalogIn, connected to the specified pin
+     *
+     * @param pin AnalogIn pin to connect to
+     * @param name (optional) A string to identify the object
+     */
+    AnalogIn(PinName pin) {
+        lock();
+        analogin_init(&_adc, pin);
+        unlock();
+    }
+
+    /** Read the input voltage, represented as a float in the range [0.0, 1.0]
+     *
+     * @returns A floating-point value representing the current input voltage, measured as a percentage
+     */
+    float read() {
+        lock();
+        float ret = analogin_read(&_adc);
+        unlock();
+        return ret;
+    }
+
+    /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+     *
+     * @returns
+     *   16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
+     */
+    unsigned short read_u16() {
+        lock();
+        unsigned short ret = analogin_read_u16(&_adc);
+        unlock();
+        return ret;
+    }
+
+    /** An operator shorthand for read()
+     *
+     * The float() operator can be used as a shorthand for read() to simplify common code sequences
+     *
+     * Example:
+     * @code
+     * float x = volume.read();
+     * float x = volume;
+     *
+     * if(volume.read() > 0.25) { ... }
+     * if(volume > 0.25) { ... }
+     * @endcode
+     */
+    operator float() {
+        // Underlying call is thread safe
+        return read();
+    }
+
+    virtual ~AnalogIn() {
+        // Do nothing
+    }
+
+protected:
+
+    virtual void lock() {
+        _mutex->lock();
+    }
+
+    virtual void unlock() {
+        _mutex->unlock();
+    }
+
+    analogin_t _adc;
+    static SingletonPtr<PlatformMutex> _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/AnalogOut.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,147 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_H
+#define MBED_ANALOGOUT_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "analogout_api.h"
+#include "PlatformMutex.h"
+
+namespace mbed {
+
+/** An analog output, used for setting the voltage on a pin
+ *
+ * @Note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Make a sawtooth output
+ *
+ * #include "mbed.h"
+ *
+ * AnalogOut tri(p18);
+ * int main() {
+ *     while(1) {
+ *         tri = tri + 0.01;
+ *         wait_us(1);
+ *         if(tri == 1) {
+ *             tri = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class AnalogOut {
+
+public:
+
+    /** Create an AnalogOut connected to the specified pin
+     *
+     *  @param AnalogOut pin to connect to (18)
+     */
+    AnalogOut(PinName pin) {
+        analogout_init(&_dac, pin);
+    }
+
+    /** Set the output voltage, specified as a percentage (float)
+     *
+     *  @param value A floating-point value representing the output voltage,
+     *    specified as a percentage. The value should lie between
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
+     */
+    void write(float value) {
+        lock();
+        analogout_write(&_dac, value);
+        unlock();
+    }
+
+    /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+     *
+     *  @param value 16-bit unsigned short representing the output voltage,
+     *            normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
+     */
+    void write_u16(unsigned short value) {
+        lock();
+        analogout_write_u16(&_dac, value);
+        unlock();
+    }
+
+    /** Return the current output voltage setting, measured as a percentage (float)
+     *
+     *  @returns
+     *    A floating-point value representing the current voltage being output on the pin,
+     *    measured as a percentage. The returned value will lie between
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+     *
+     *  @note
+     *    This value may not match exactly the value set by a previous write().
+     */
+    float read() {
+        lock();
+        float ret = analogout_read(&_dac);
+        unlock();
+        return ret;
+    }
+
+    /** An operator shorthand for write()
+     */
+    AnalogOut& operator= (float percent) {
+        // Underlying write call is thread safe
+        write(percent);
+        return *this;
+    }
+
+    AnalogOut& operator= (AnalogOut& rhs) {
+        // Underlying write call is thread safe
+        write(rhs.read());
+        return *this;
+    }
+
+    /** An operator shorthand for read()
+     */
+    operator float() {
+        // Underlying read call is thread safe
+        return read();
+    }
+
+    virtual ~AnalogOut() {
+        // Do nothing
+    }
+
+protected:
+
+    virtual void lock() {
+        _mutex.lock();
+    }
+
+    virtual void unlock() {
+        _mutex.unlock();
+    }
+
+    dac_t _dac;
+    PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/BusIn.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,105 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSIN_H
+#define MBED_BUSIN_H
+
+#include "platform.h"
+#include "DigitalIn.h"
+#include "PlatformMutex.h"
+
+namespace mbed {
+
+/** A digital input bus, used for reading the state of a collection of pins
+ *
+ * @Note Synchronization level: Thread safe
+ */
+class BusIn {
+
+public:
+    /* Group: Configuration Methods */
+
+    /** Create an BusIn, connected to the specified pins
+     *
+     * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
+     *
+     * @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+          PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+          PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+          PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusIn(PinName pins[16]);
+
+    virtual ~BusIn();
+
+    /** Read the value of the input bus
+     *
+     *  @returns
+     *   An integer with each bit corresponding to the value read from the associated DigitalIn pin
+     */
+    int read();
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        // No lock needed since _nc_mask is not modified outside the constructor
+        return _nc_mask;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int();
+
+    /** Access to particular bit in random-iterator fashion
+     */
+    DigitalIn & operator[] (int index);
+
+protected:
+    DigitalIn* _pin[16];
+
+    /** Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
+    PlatformMutex _mutex;
+
+    /* disallow copy constructor and assignment operators */
+private:
+    virtual void lock();
+    virtual void unlock();
+    BusIn(const BusIn&);
+    BusIn & operator = (const BusIn&);
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/BusInOut.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,124 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSINOUT_H
+#define MBED_BUSINOUT_H
+
+#include "DigitalInOut.h"
+#include "PlatformMutex.h"
+
+namespace mbed {
+
+/** A digital input output bus, used for setting the state of a collection of pins
+ *
+ * @Note Synchronization level: Thread safe
+ */
+class BusInOut {
+
+public:
+
+    /** Create an BusInOut, connected to the specified pins
+     *
+     *  @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
+     *
+     *  @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+             PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+             PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+             PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusInOut(PinName pins[16]);
+
+    virtual ~BusInOut();
+
+    /* Group: Access Methods */
+
+    /** Write the value to the output bus
+     *
+     *  @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
+     */
+    void write(int value);
+
+    /** Read the value currently output on the bus
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated DigitalInOut pin setting
+     */
+    int read();
+
+    /** Set as an output
+     */
+    void output();
+
+    /** Set as an input
+     */
+    void input();
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        // No lock needed since _nc_mask is not modified outside the constructor
+        return _nc_mask;
+    }
+
+     /** A shorthand for write()
+     */
+    BusInOut& operator= (int v);
+    BusInOut& operator= (BusInOut& rhs);
+
+    /** Access to particular bit in random-iterator fashion
+    */
+    DigitalInOut& operator[] (int index);
+
+    /** A shorthand for read()
+     */
+    operator int();
+
+protected:
+    virtual void lock();
+    virtual void unlock();
+    DigitalInOut* _pin[16];
+
+    /** Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
+    PlatformMutex _mutex;
+
+    /* disallow copy constructor and assignment operators */
+private:
+    BusInOut(const BusInOut&);
+    BusInOut & operator = (const BusInOut&);
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/BusOut.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,108 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSOUT_H
+#define MBED_BUSOUT_H
+
+#include "DigitalOut.h"
+#include "PlatformMutex.h"
+
+namespace mbed {
+
+/** A digital output bus, used for setting the state of a collection of pins
+ */
+class BusOut {
+
+public:
+
+    /** Create an BusOut, connected to the specified pins
+     *
+     *  @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
+     *
+     *  @Note Synchronization level: Thread safe
+     *
+     *  @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+           PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+           PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+           PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusOut(PinName pins[16]);
+
+    virtual ~BusOut();
+
+    /** Write the value to the output bus
+     *
+     *  @param value An integer specifying a bit to write for every corresponding DigitalOut pin
+     */
+    void write(int value);
+
+    /** Read the value currently output on the bus
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated DigitalOut pin setting
+     */
+    int read();
+
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        // No lock needed since _nc_mask is not modified outside the constructor
+        return _nc_mask;
+    }
+
+    /** A shorthand for write()
+     */
+    BusOut& operator= (int v);
+    BusOut& operator= (BusOut& rhs);
+
+    /** Access to particular bit in random-iterator fashion
+     */
+    DigitalOut& operator[] (int index);
+
+    /** A shorthand for read()
+     */
+    operator int();
+
+protected:
+    virtual void lock();
+    virtual void unlock();
+    DigitalOut* _pin[16];
+
+    /** Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
+    PlatformMutex _mutex;
+
+   /* disallow copy constructor and assignment operators */
+private:
+    BusOut(const BusOut&);
+    BusOut & operator = (const BusOut&);
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/CAN.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,258 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_H
+#define MBED_CAN_H
+
+#include "platform.h"
+
+#if DEVICE_CAN
+
+#include "can_api.h"
+#include "can_helper.h"
+#include "Callback.h"
+#include "PlatformMutex.h"
+
+namespace mbed {
+
+/** CANMessage class
+ *
+ * @Note Synchronization level: Thread safe
+ */
+class CANMessage : public CAN_Message {
+
+public:
+    /** Creates empty CAN message.
+     */
+    CANMessage() : CAN_Message() {
+        len    = 8;
+        type   = CANData;
+        format = CANStandard;
+        id     = 0;
+        memset(data, 0, 8);
+    }
+
+    /** Creates CAN message with specific content.
+     */
+    CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
+      len    = _len & 0xF;
+      type   = _type;
+      format = _format;
+      id     = _id;
+      memcpy(data, _data, _len);
+    }
+
+    /** Creates CAN remote message.
+     */
+    CANMessage(int _id, CANFormat _format = CANStandard) {
+      len    = 0;
+      type   = CANRemote;
+      format = _format;
+      id     = _id;
+      memset(data, 0, 8);
+    }
+};
+
+/** A can bus client, used for communicating with can devices
+ */
+class CAN {
+
+public:
+    /** Creates an CAN interface connected to specific pins.
+     *
+     *  @param rd read from transmitter
+     *  @param td transmit to transmitter
+     *
+     * Example:
+     * @code
+     * #include "mbed.h"
+     *
+     * Ticker ticker;
+     * DigitalOut led1(LED1);
+     * DigitalOut led2(LED2);
+     * CAN can1(p9, p10);
+     * CAN can2(p30, p29);
+     *
+     * char counter = 0;
+     *
+     * void send() {
+     *     if(can1.write(CANMessage(1337, &counter, 1))) {
+     *         printf("Message sent: %d\n", counter);
+     *         counter++;
+     *     }
+     *     led1 = !led1;
+     * }
+     *
+     * int main() {
+     *     ticker.attach(&send, 1);
+     *    CANMessage msg;
+     *     while(1) {
+     *         if(can2.read(msg)) {
+     *             printf("Message received: %d\n\n", msg.data[0]);
+     *             led2 = !led2;
+     *         }
+     *         wait(0.2);
+     *     }
+     * }
+     * @endcode
+     */
+    CAN(PinName rd, PinName td);
+    virtual ~CAN();
+
+    /** Set the frequency of the CAN interface
+     *
+     *  @param hz The bus frequency in hertz
+     *
+     *  @returns
+     *    1 if successful,
+     *    0 otherwise
+     */
+    int frequency(int hz);
+
+    /** Write a CANMessage to the bus.
+     *
+     *  @param msg The CANMessage to write.
+     *
+     *  @returns
+     *    0 if write failed,
+     *    1 if write was successful
+     */
+    int write(CANMessage msg);
+
+    /** Read a CANMessage from the bus.
+     *
+     *  @param msg A CANMessage to read to.
+     *  @param handle message filter handle (0 for any message)
+     *
+     *  @returns
+     *    0 if no message arrived,
+     *    1 if message arrived
+     */
+    int read(CANMessage &msg, int handle = 0);
+
+    /** Reset CAN interface.
+     *
+     * To use after error overflow.
+     */
+    void reset();
+
+    /** Puts or removes the CAN interface into silent monitoring mode
+     *
+     *  @param silent boolean indicating whether to go into silent mode or not
+     */
+    void monitor(bool silent);
+
+    enum Mode {
+        Reset = 0,
+        Normal,
+        Silent,
+        LocalTest,
+        GlobalTest,
+        SilentTest
+    };
+
+    /** Change CAN operation to the specified mode
+     *
+     *  @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
+     *
+     *  @returns
+     *    0 if mode change failed or unsupported,
+     *    1 if mode change was successful
+     */
+    int mode(Mode mode);
+
+    /** Filter out incomming messages
+     *
+     *  @param id the id to filter on
+     *  @param mask the mask applied to the id
+     *  @param format format to filter on (Default CANAny)
+     *  @param handle message filter handle (Optional)
+     *
+     *  @returns
+     *    0 if filter change failed or unsupported,
+     *    new filter handle if successful
+     */
+    int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
+
+    /** Returns number of read errors to detect read overflow errors.
+     */
+    unsigned char rderror();
+
+    /** Returns number of write errors to detect write overflow errors.
+     */
+    unsigned char tderror();
+
+    enum IrqType {
+        RxIrq = 0,
+        TxIrq,
+        EwIrq,
+        DoIrq,
+        WuIrq,
+        EpIrq,
+        AlIrq,
+        BeIrq,
+        IdIrq
+    };
+
+    /** Attach a function to call whenever a CAN frame received interrupt is
+     *  generated.
+     *
+     *  @param func A pointer to a void function, or 0 to set as none
+     *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
+     */
+    void attach(Callback<void()> func, IrqType type=RxIrq);
+
+   /** Attach a member function to call whenever a CAN frame received interrupt
+    *  is generated.
+    *
+    *  @param obj pointer to the object to call the member function on
+    *  @param method pointer to the member function to be called
+    *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+    */
+    template<typename T>
+    void attach(T* obj, void (T::*method)(), IrqType type=RxIrq) {
+        // Underlying call thread safe
+        attach(Callback<void()>(obj, method), type);
+    }
+
+   /** Attach a member function to call whenever a CAN frame received interrupt
+    *  is generated.
+    *
+    *  @param obj pointer to the object to call the member function on
+    *  @param method pointer to the member function to be called
+    *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+    */
+    template<typename T>
+    void attach(T* obj, void (*method)(T*), IrqType type=RxIrq) {
+        // Underlying call thread safe
+        attach(Callback<void()>(obj, method), type);
+    }
+
+    static void _irq_handler(uint32_t id, CanIrqType type);
+
+protected:
+    virtual void lock();
+    virtual void unlock();
+    can_t               _can;
+    Callback<void()>    _irq[9];
+    PlatformMutex       _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif    // MBED_CAN_H
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/CThunk.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,235 @@
+/* General C++ Object Thunking class
+ *
+ * - allows direct callbacks to non-static C++ class functions
+ * - keeps track for the corresponding class instance
+ * - supports an optional context parameter for the called function
+ * - ideally suited for class object receiving interrupts (NVIC_SetVector)
+ *
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* General C++ Object Thunking class
+ *
+ * - allows direct callbacks to non-static C++ class functions
+ * - keeps track for the corresponding class instance
+ * - supports an optional context parameter for the called function
+ * - ideally suited for class object receiving interrupts (NVIC_SetVector)
+ */
+
+#ifndef __CTHUNK_H__
+#define __CTHUNK_H__
+
+#define CTHUNK_ADDRESS 1
+
+#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)) && ! defined(__CORTEX_A9)
+#define CTHUNK_VARIABLES volatile uint32_t code[1]
+/**
+* CTHUNK disassembly for Cortex-M3/M4 (thumb2):
+* * ldm.w pc,{r0,r1,r2,pc}
+*
+* This instruction loads the arguments for the static thunking function to r0-r2, and
+* branches to that function by loading its address into PC.
+*
+* This is safe for both regular calling and interrupt calling, since it only touches scratch registers
+* which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
+*/
+#define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F
+
+#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0) || defined(__CORTEX_A9)
+/*
+* CTHUNK disassembly for Cortex M0 (thumb):
+* * push {r0,r1,r2,r3,r4,lr} save touched registers and return address
+* * movs r4,#4 set up address to load arguments from (immediately following this code block) (1)
+* * add r4,pc set up address to load arguments from (immediately following this code block) (2)
+* * ldm r4!,{r0,r1,r2,r3} load arguments for static thunk function
+* * blx r3 call static thunk function
+* * pop {r0,r1,r2,r3,r4,pc} restore scratch registers and return from function
+*/
+#define CTHUNK_VARIABLES volatile uint32_t code[3]
+#define CTHUNK_ASSIGMENT do {                              \
+                             m_thunk.code[0] = 0x2404B51F; \
+                             m_thunk.code[1] = 0xCC0F447C; \
+                             m_thunk.code[2] = 0xBD1F4798; \
+                         } while (0)
+
+#else
+#error "Target is not currently suported."
+#endif
+
+/* IRQ/Exception compatible thunk entry function */
+typedef void (*CThunkEntry)(void);
+
+/**
+ * Class for created a pointer with data bound to it
+ *
+ * @Note Synchronization level: Not protected
+ */
+template<class T>
+class CThunk
+{
+    public:
+        typedef void (T::*CCallbackSimple)(void);
+        typedef void (T::*CCallback)(void* context);
+
+        inline CThunk(T *instance)
+        {
+            init(instance, NULL, NULL);
+        }
+
+        inline CThunk(T *instance, CCallback callback)
+        {
+            init(instance, callback, NULL);
+        }
+
+        ~CThunk() {
+
+        }
+
+        inline CThunk(T *instance, CCallbackSimple callback)
+        {
+            init(instance, (CCallback)callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallback callback)
+        {
+            init(instance, callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallbackSimple callback)
+        {
+            init(instance, (CCallback)callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallback callback, void* context)
+        {
+            init(instance, callback, context);
+        }
+
+        inline void callback(CCallback callback)
+        {
+            m_callback = callback;
+        }
+
+        inline void callback(CCallbackSimple callback)
+        {
+            m_callback = (CCallback)callback;
+        }
+
+        inline void context(void* context)
+        {
+            m_thunk.context = (uint32_t)context;
+        }
+
+        inline void context(uint32_t context)
+        {
+            m_thunk.context = context;
+        }
+        
+        inline uint32_t entry(void)
+        {
+            return (((uint32_t)&m_thunk)|CTHUNK_ADDRESS);
+        }
+
+        /* get thunk entry point for connecting rhunk to an IRQ table */
+        inline operator CThunkEntry(void)
+        {
+            return (CThunkEntry)entry();
+        }
+
+        /* get thunk entry point for connecting rhunk to an IRQ table */
+        inline operator uint32_t(void)
+        {
+            return entry();
+        }
+
+        /* simple test function */
+        inline void call(void)
+        {
+            (((CThunkEntry)(entry()))());
+        }
+
+    private:
+        T* m_instance;
+        volatile CCallback m_callback;
+
+// TODO: this needs proper fix, to refactor toolchain header file and all its use
+// PACKED there is not defined properly for IAR
+#if defined (__ICCARM__)
+        typedef __packed struct
+        {
+            CTHUNK_VARIABLES;
+            volatile uint32_t instance;
+            volatile uint32_t context;
+            volatile uint32_t callback;
+            volatile uint32_t trampoline;
+        }  CThunkTrampoline;
+#else
+        typedef struct
+        {
+            CTHUNK_VARIABLES;
+            volatile uint32_t instance;
+            volatile uint32_t context;
+            volatile uint32_t callback;
+            volatile uint32_t trampoline;
+        } __attribute__((__packed__)) CThunkTrampoline;
+#endif
+
+        static void trampoline(T* instance, void* context, CCallback* callback)
+        {
+            if(instance && *callback) {
+                (static_cast<T*>(instance)->**callback)(context);
+            }
+        }
+
+        volatile CThunkTrampoline m_thunk;
+
+        inline void init(T *instance, CCallback callback, void* context)
+        {
+            /* remember callback - need to add this level of redirection
+               as pointer size for member functions differs between platforms */
+            m_callback = callback;
+
+            /* populate thunking trampoline */
+            CTHUNK_ASSIGMENT;
+            m_thunk.context = (uint32_t)context;
+            m_thunk.instance = (uint32_t)instance;
+            m_thunk.callback = (uint32_t)&m_callback;
+            m_thunk.trampoline = (uint32_t)&trampoline;
+
+#if defined(__CORTEX_A9)
+            /* Data cache clean */
+            /* Cache control */
+            {
+                uint32_t start_addr = (uint32_t)&m_thunk & 0xFFFFFFE0;
+                uint32_t end_addr   = (uint32_t)&m_thunk + sizeof(m_thunk);
+                uint32_t addr;
+                
+                /* Data cache clean and invalid */
+                for (addr = start_addr; addr < end_addr; addr += 0x20) {
+                    __v7_clean_inv_dcache_mva((void *)addr);
+                }
+                /* Instruction cache invalid */
+                __v7_inv_icache_all();
+                __ca9u_inv_tlb_all();
+                __v7_inv_btac();
+            }
+#endif
+            __ISB();
+            __DSB();
+        }
+};
+
+#endif/*__CTHUNK_H__*/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/CallChain.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,174 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLCHAIN_H
+#define MBED_CALLCHAIN_H
+
+#include "Callback.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Group one or more functions in an instance of a CallChain, then call them in
+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
+ * but can be used for other purposes.
+ *
+ * @Note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * CallChain chain;
+ *
+ * void first(void) {
+ *     printf("'first' function.\n");
+ * }
+ *
+ * void second(void) {
+ *     printf("'second' function.\n");
+ * }
+ *
+ * class Test {
+ * public:
+ *     void f(void) {
+ *         printf("A::f (class member).\n");
+ *     }
+ * };
+ *
+ * int main() {
+ *     Test test;
+ *
+ *     chain.add(second);
+ *     chain.add_front(first);
+ *     chain.add(&test, &Test::f);
+ *     chain.call();
+ * }
+ * @endcode
+ */
+
+typedef Callback<void()> *pFunctionPointer_t;
+class CallChainLink;
+
+class CallChain {
+public:
+    /** Create an empty chain
+     *
+     *  @param size (optional) Initial size of the chain
+     */
+    CallChain(int size = 4);
+    virtual ~CallChain();
+
+    /** Add a function at the end of the chain
+     *
+     *  @param func A pointer to a void function
+     *
+     *  @returns
+     *  The function object created for 'func'
+     */
+    pFunctionPointer_t add(Callback<void()> func);
+
+    /** Add a function at the end of the chain
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *
+     *  @returns
+     *  The function object created for 'obj' and 'method'
+     */
+    template<typename T, typename M>
+    pFunctionPointer_t add(T *obj, M method) {
+        return add(Callback<void()>(obj, method));
+    }
+
+    /** Add a function at the beginning of the chain
+     *
+     *  @param func A pointer to a void function
+     *
+     *  @returns
+     *  The function object created for 'func'
+     */
+    pFunctionPointer_t add_front(Callback<void()> func);
+
+    /** Add a function at the beginning of the chain
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T, typename M>
+    pFunctionPointer_t add_front(T *obj, M method) {
+        return add_front(Callback<void()>(obj, method));
+    }
+
+    /** Get the number of functions in the chain
+     */
+    int size() const;
+
+    /** Get a function object from the chain
+     *
+     *  @param i function object index
+     *
+     *  @returns
+     *  The function object at position 'i' in the chain
+     */
+    pFunctionPointer_t get(int i) const;
+
+    /** Look for a function object in the call chain
+     *
+     *  @param f the function object to search
+     *
+     *  @returns
+     *  The index of the function object if found, -1 otherwise.
+     */
+    int find(pFunctionPointer_t f) const;
+
+    /** Clear the call chain (remove all functions in the chain).
+     */
+    void clear();
+
+    /** Remove a function object from the chain
+     *
+     *  @arg f the function object to remove
+     *
+     *  @returns
+     *  true if the function object was found and removed, false otherwise.
+     */
+    bool remove(pFunctionPointer_t f);
+
+    /** Call all the functions in the chain in sequence
+     */
+    void call();
+
+    void operator ()(void) {
+        call();
+    }
+    pFunctionPointer_t operator [](int i) const {
+        return get(i);
+    }
+
+    /* disallow copy constructor and assignment operators */
+private:
+    CallChain(const CallChain&);
+    CallChain & operator = (const CallChain&);
+    CallChainLink *_chain;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/Callback.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,884 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLBACK_H
+#define MBED_CALLBACK_H
+
+#include <string.h>
+#include <stdint.h>
+
+namespace mbed {
+
+
+/** Callback class based on template specialization
+ *
+ * @Note Synchronization level: Not protected
+ */
+template <typename F>
+class Callback;
+
+/** Templated function class
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
+class Callback<R(A0, A1, A2, A3, A4)> {
+public:
+    /** Create a Callback with a static function
+     *  @param func Static function to attach
+     */
+    Callback(R (*func)(A0, A1, A2, A3, A4) = 0) {
+        attach(func);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (*func)(T*, A0, A1, A2, A3, A4)) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (T::*func)(A0, A1, A2, A3, A4)) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with another Callback
+     *  @param func Callback to attach
+     */
+    Callback(const Callback<R(A0, A1, A2, A3, A4)> &func) {
+        attach(func);
+    }
+
+    /** Attach a static function
+     *  @param func Static function to attach
+     */
+    void attach(R (*func)(A0, A1, A2, A3, A4)) {
+        memcpy(&_func, &func, sizeof func);
+        _thunk = func ? &Callback::_staticthunk : 0;
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template <typename T>
+    void attach(T *obj, R (*func)(T*, A0, A1, A2, A3, A4)) {
+        _obj = (void*)obj;
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_boundthunk<T>;
+    }
+
+    /** Attach a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    void attach(T *obj, R (T::*func)(A0, A1, A2, A3, A4)) {
+        _obj = static_cast<void*>(obj);
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_methodthunk<T>;
+    }
+
+    /** Attach a Callback
+     *  @param func The Callback to attach
+     */
+    void attach(const Callback<R(A0, A1, A2, A3, A4)> &func) {
+        _obj = func._obj;
+        memcpy(&_func, &func._func, sizeof _func);
+        _thunk = func._thunk;
+    }
+
+    /** Call the attached function
+     */
+    R call(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        if (!_thunk) {
+            return (R)0;
+        }
+        return _thunk(_obj, &_func, a0, a1, a2, a3, a4);
+    }
+
+    /** Call the attached function
+     */
+    R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return call(a0, a1, a2, a3, a4);
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _thunk;
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     */
+    static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return static_cast<Callback<R(A0, A1, A2, A3, A4)>*>(func)
+                ->call(a0, a1, a2, a3, a4);
+    }
+
+private:
+    // Internal thunks for various function types
+    static R _staticthunk(void*, void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return (*reinterpret_cast<R (**)(A0, A1, A2, A3, A4)>(func))
+                (a0, a1, a2, a3, a4);
+    }
+
+    template<typename T>
+    static R _boundthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return (*reinterpret_cast<R (**)(T*, A0, A1, A2, A3, A4)>(func))
+                (static_cast<T*>(obj), a0, a1, a2, a3, a4);
+    }
+
+    template<typename T>
+    static R _methodthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) {
+        return (static_cast<T*>(obj)->*
+                (*reinterpret_cast<R (T::**)(A0, A1, A2, A3, A4)>(func)))
+                (a0, a1, a2, a3, a4);
+    }
+
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)();
+        void (*_boundfunc)(_class *);
+        void (_class::*_methodfunc)();
+    } _func;
+
+    void *_obj;
+
+    // Thunk registered on attach to dispatch calls
+    R (*_thunk)(void*, void*, A0, A1, A2, A3, A4); 
+};
+
+/** Templated function class
+ */
+template <typename R, typename A0, typename A1, typename A2, typename A3>
+class Callback<R(A0, A1, A2, A3)> {
+public:
+    /** Create a Callback with a static function
+     *  @param func Static function to attach
+     */
+    Callback(R (*func)(A0, A1, A2, A3) = 0) {
+        attach(func);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (*func)(T*, A0, A1, A2, A3)) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (T::*func)(A0, A1, A2, A3)) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with another Callback
+     *  @param func Callback to attach
+     */
+    Callback(const Callback<R(A0, A1, A2, A3)> &func) {
+        attach(func);
+    }
+
+    /** Attach a static function
+     *  @param func Static function to attach
+     */
+    void attach(R (*func)(A0, A1, A2, A3)) {
+        memcpy(&_func, &func, sizeof func);
+        _thunk = func ? &Callback::_staticthunk : 0;
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template <typename T>
+    void attach(T *obj, R (*func)(T*, A0, A1, A2, A3)) {
+        _obj = (void*)obj;
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_boundthunk<T>;
+    }
+
+    /** Attach a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    void attach(T *obj, R (T::*func)(A0, A1, A2, A3)) {
+        _obj = static_cast<void*>(obj);
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_methodthunk<T>;
+    }
+
+    /** Attach a Callback
+     *  @param func The Callback to attach
+     */
+    void attach(const Callback<R(A0, A1, A2, A3)> &func) {
+        _obj = func._obj;
+        memcpy(&_func, &func._func, sizeof _func);
+        _thunk = func._thunk;
+    }
+
+    /** Call the attached function
+     */
+    R call(A0 a0, A1 a1, A2 a2, A3 a3) {
+        if (!_thunk) {
+            return (R)0;
+        }
+        return _thunk(_obj, &_func, a0, a1, a2, a3);
+    }
+
+    /** Call the attached function
+     */
+    R operator()(A0 a0, A1 a1, A2 a2, A3 a3) {
+        return call(a0, a1, a2, a3);
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _thunk;
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     */
+    static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return static_cast<Callback<R(A0, A1, A2, A3)>*>(func)
+                ->call(a0, a1, a2, a3);
+    }
+
+private:
+    // Internal thunks for various function types
+    static R _staticthunk(void*, void *func, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return (*reinterpret_cast<R (**)(A0, A1, A2, A3)>(func))
+                (a0, a1, a2, a3);
+    }
+
+    template<typename T>
+    static R _boundthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return (*reinterpret_cast<R (**)(T*, A0, A1, A2, A3)>(func))
+                (static_cast<T*>(obj), a0, a1, a2, a3);
+    }
+
+    template<typename T>
+    static R _methodthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2, A3 a3) {
+        return (static_cast<T*>(obj)->*
+                (*reinterpret_cast<R (T::**)(A0, A1, A2, A3)>(func)))
+                (a0, a1, a2, a3);
+    }
+
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)();
+        void (*_boundfunc)(_class *);
+        void (_class::*_methodfunc)();
+    } _func;
+
+    void *_obj;
+
+    // Thunk registered on attach to dispatch calls
+    R (*_thunk)(void*, void*, A0, A1, A2, A3); 
+};
+
+/** Templated function class
+ */
+template <typename R, typename A0, typename A1, typename A2>
+class Callback<R(A0, A1, A2)> {
+public:
+    /** Create a Callback with a static function
+     *  @param func Static function to attach
+     */
+    Callback(R (*func)(A0, A1, A2) = 0) {
+        attach(func);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (*func)(T*, A0, A1, A2)) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (T::*func)(A0, A1, A2)) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with another Callback
+     *  @param func Callback to attach
+     */
+    Callback(const Callback<R(A0, A1, A2)> &func) {
+        attach(func);
+    }
+
+    /** Attach a static function
+     *  @param func Static function to attach
+     */
+    void attach(R (*func)(A0, A1, A2)) {
+        memcpy(&_func, &func, sizeof func);
+        _thunk = func ? &Callback::_staticthunk : 0;
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template <typename T>
+    void attach(T *obj, R (*func)(T*, A0, A1, A2)) {
+        _obj = (void*)obj;
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_boundthunk<T>;
+    }
+
+    /** Attach a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    void attach(T *obj, R (T::*func)(A0, A1, A2)) {
+        _obj = static_cast<void*>(obj);
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_methodthunk<T>;
+    }
+
+    /** Attach a Callback
+     *  @param func The Callback to attach
+     */
+    void attach(const Callback<R(A0, A1, A2)> &func) {
+        _obj = func._obj;
+        memcpy(&_func, &func._func, sizeof _func);
+        _thunk = func._thunk;
+    }
+
+    /** Call the attached function
+     */
+    R call(A0 a0, A1 a1, A2 a2) {
+        if (!_thunk) {
+            return (R)0;
+        }
+        return _thunk(_obj, &_func, a0, a1, a2);
+    }
+
+    /** Call the attached function
+     */
+    R operator()(A0 a0, A1 a1, A2 a2) {
+        return call(a0, a1, a2);
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _thunk;
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     */
+    static R thunk(void *func, A0 a0, A1 a1, A2 a2) {
+        return static_cast<Callback<R(A0, A1, A2)>*>(func)
+                ->call(a0, a1, a2);
+    }
+
+private:
+    // Internal thunks for various function types
+    static R _staticthunk(void*, void *func, A0 a0, A1 a1, A2 a2) {
+        return (*reinterpret_cast<R (**)(A0, A1, A2)>(func))
+                (a0, a1, a2);
+    }
+
+    template<typename T>
+    static R _boundthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2) {
+        return (*reinterpret_cast<R (**)(T*, A0, A1, A2)>(func))
+                (static_cast<T*>(obj), a0, a1, a2);
+    }
+
+    template<typename T>
+    static R _methodthunk(void *obj, void *func, A0 a0, A1 a1, A2 a2) {
+        return (static_cast<T*>(obj)->*
+                (*reinterpret_cast<R (T::**)(A0, A1, A2)>(func)))
+                (a0, a1, a2);
+    }
+
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)();
+        void (*_boundfunc)(_class *);
+        void (_class::*_methodfunc)();
+    } _func;
+
+    void *_obj;
+
+    // Thunk registered on attach to dispatch calls
+    R (*_thunk)(void*, void*, A0, A1, A2);
+};
+
+/** Templated function class
+ */
+template <typename R, typename A0, typename A1>
+class Callback<R(A0, A1)> {
+public:
+    /** Create a Callback with a static function
+     *  @param func Static function to attach
+     */
+    Callback(R (*func)(A0, A1) = 0) {
+        attach(func);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (*func)(T*, A0, A1)) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (T::*func)(A0, A1)) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with another Callback
+     *  @param func Callback to attach
+     */
+    Callback(const Callback<R(A0, A1)> &func) {
+        attach(func);
+    }
+
+    /** Attach a static function
+     *  @param func Static function to attach
+     */
+    void attach(R (*func)(A0, A1)) {
+        memcpy(&_func, &func, sizeof func);
+        _thunk = func ? &Callback::_staticthunk : 0;
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template <typename T>
+    void attach(T *obj, R (*func)(T*, A0, A1)) {
+        _obj = (void*)obj;
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_boundthunk<T>;
+    }
+
+    /** Attach a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    void attach(T *obj, R (T::*func)(A0, A1)) {
+        _obj = static_cast<void*>(obj);
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_methodthunk<T>;
+    }
+
+    /** Attach a Callback
+     *  @param func The Callback to attach
+     */
+    void attach(const Callback<R(A0, A1)> &func) {
+        _obj = func._obj;
+        memcpy(&_func, &func._func, sizeof _func);
+        _thunk = func._thunk;
+    }
+
+    /** Call the attached function
+     */
+    R call(A0 a0, A1 a1) {
+        if (!_thunk) {
+            return (R)0;
+        }
+        return _thunk(_obj, &_func, a0, a1);
+    }
+
+    /** Call the attached function
+     */
+    R operator()(A0 a0, A1 a1) {
+        return call(a0, a1);
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _thunk;
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     */
+    static R thunk(void *func, A0 a0, A1 a1) {
+        return static_cast<Callback<R(A0, A1)>*>(func)
+                ->call(a0, a1);
+    }
+
+private:
+    // Internal thunks for various function types
+    static R _staticthunk(void*, void *func, A0 a0, A1 a1) {
+        return (*reinterpret_cast<R (**)(A0, A1)>(func))
+                (a0, a1);
+    }
+
+    template<typename T>
+    static R _boundthunk(void *obj, void *func, A0 a0, A1 a1) {
+        return (*reinterpret_cast<R (**)(T*, A0, A1)>(func))
+                (static_cast<T*>(obj), a0, a1);
+    }
+
+    template<typename T>
+    static R _methodthunk(void *obj, void *func, A0 a0, A1 a1) {
+        return (static_cast<T*>(obj)->*
+                (*reinterpret_cast<R (T::**)(A0, A1)>(func)))
+                (a0, a1);
+    }
+
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)();
+        void (*_boundfunc)(_class *);
+        void (_class::*_methodfunc)();
+    } _func;
+
+    void *_obj;
+
+    // Thunk registered on attach to dispatch calls
+    R (*_thunk)(void*, void*, A0, A1); 
+};
+
+/** Templated function class
+ */
+template <typename R, typename A0>
+class Callback<R(A0)> {
+public:
+    /** Create a Callback with a static function
+     *  @param func Static function to attach
+     */
+    Callback(R (*func)(A0) = 0) {
+        attach(func);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (*func)(T*, A0)) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (T::*func)(A0)) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with another Callback
+     *  @param func Callback to attach
+     */
+    Callback(const Callback<R(A0)> &func) {
+        attach(func);
+    }
+
+    /** Attach a static function
+     *  @param func Static function to attach
+     */
+    void attach(R (*func)(A0)) {
+        memcpy(&_func, &func, sizeof func);
+        _thunk = func ? &Callback::_staticthunk : 0;
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template <typename T>
+    void attach(T *obj, R (*func)(T*, A0)) {
+        _obj = (void*)obj;
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_boundthunk<T>;
+    }
+
+    /** Attach a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    void attach(T *obj, R (T::*func)(A0)) {
+        _obj = static_cast<void*>(obj);
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_methodthunk<T>;
+    }
+
+    /** Attach a Callback
+     *  @param func The Callback to attach
+     */
+    void attach(const Callback<R(A0)> &func) {
+        _obj = func._obj;
+        memcpy(&_func, &func._func, sizeof _func);
+        _thunk = func._thunk;
+    }
+
+    /** Call the attached function
+     */
+    R call(A0 a0) {
+        if (!_thunk) {
+            return (R)0;
+        }
+        return _thunk(_obj, &_func, a0);
+    }
+
+    /** Call the attached function
+     */
+    R operator()(A0 a0) {
+        return call(a0);
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _thunk;
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     */
+    static R thunk(void *func, A0 a0) {
+        return static_cast<Callback<R(A0)>*>(func)
+                ->call(a0);
+    }
+
+private:
+    // Internal thunks for various function types
+    static R _staticthunk(void*, void *func, A0 a0) {
+        return (*reinterpret_cast<R (**)(A0)>(func))
+                (a0);
+    }
+
+    template<typename T>
+    static R _boundthunk(void *obj, void *func, A0 a0) {
+        return (*reinterpret_cast<R (**)(T*, A0)>(func))
+                (static_cast<T*>(obj), a0);
+    }
+
+    template<typename T>
+    static R _methodthunk(void *obj, void *func, A0 a0) {
+        return (static_cast<T*>(obj)->*
+                (*reinterpret_cast<R (T::**)(A0)>(func)))
+                (a0);
+    }
+
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)();
+        void (*_boundfunc)(_class *);
+        void (_class::*_methodfunc)();
+    } _func;
+
+    void *_obj;
+
+    // Thunk registered on attach to dispatch calls
+    R (*_thunk)(void*, void*, A0); 
+};
+
+/** Templated function class
+ */
+template <typename R>
+class Callback<R()> {
+public:
+    /** Create a Callback with a static function
+     *  @param func Static function to attach
+     */
+    Callback(R (*func)() = 0) {
+        attach(func);
+    }
+
+    /** Create a Callback with a static function and bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (*func)(T*)) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    Callback(T *obj, R (T::*func)()) {
+        attach(obj, func);
+    }
+
+    /** Create a Callback with another Callback
+     *  @param func Callback to attach
+     */
+    Callback(const Callback<R()> &func) {
+        attach(func);
+    }
+
+    /** Attach a static function
+     *  @param func Static function to attach
+     */
+    void attach(R (*func)()) {
+        memcpy(&_func, &func, sizeof func);
+        _thunk = func ? &Callback::_staticthunk : 0;
+    }
+
+    /** Attach a static function with a bound pointer
+     *  @param obj  Pointer to object to bind to function
+     *  @param func Static function to attach
+     */
+    template <typename T>
+    void attach(T *obj, R (*func)(T*)) {
+        _obj = (void*)obj;
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_boundthunk<T>;
+    }
+
+    /** Attach a member function
+     *  @param obj  Pointer to object to invoke member function on
+     *  @param func Member function to attach
+     */
+    template<typename T>
+    void attach(T *obj, R (T::*func)()) {
+        _obj = static_cast<void*>(obj);
+        memcpy(&_func, &func, sizeof func);
+        _thunk = &Callback::_methodthunk<T>;
+    }
+
+    /** Attach a Callback
+     *  @param func The Callback to attach
+     */
+    void attach(const Callback<R()> &func) {
+        _obj = func._obj;
+        memcpy(&_func, &func._func, sizeof _func);
+        _thunk = func._thunk;
+    }
+
+    /** Call the attached function
+     */
+    R call() {
+        if (!_thunk) {
+            return (R)0;
+        }
+        return _thunk(_obj, &_func);
+    }
+
+    /** Call the attached function
+     */
+    R operator()() {
+        return call();
+    }
+
+    /** Test if function has been attached
+     */
+    operator bool() const {
+        return _thunk;
+    }
+
+    /** Static thunk for passing as C-style function
+     *  @param func Callback to call passed as void pointer
+     */
+    static R thunk(void *func) {
+        return static_cast<Callback<R()>*>(func)
+                ->call();
+    }
+
+private:
+    // Internal thunks for various function types
+    static R _staticthunk(void*, void *func) {
+        return (*reinterpret_cast<R (**)()>(func))
+                ();
+    }
+
+    template<typename T>
+    static R _boundthunk(void *obj, void *func) {
+        return (*reinterpret_cast<R (**)(T*)>(func))
+                (static_cast<T*>(obj));
+    }
+
+    template<typename T>
+    static R _methodthunk(void *obj, void *func) {
+        return (static_cast<T*>(obj)->*
+                (*reinterpret_cast<R (T::**)()>(func)))
+                ();
+    }
+
+    // Stored as pointer to function and pointer to optional object
+    // Function pointer is stored as union of possible function types
+    // to garuntee proper size and alignment
+    struct _class;
+    union {
+        void (*_staticfunc)();
+        void (*_boundfunc)(_class *);
+        void (_class::*_methodfunc)();
+    } _func;
+
+    void *_obj;
+
+    // Thunk registered on attach to dispatch calls
+    R (*_thunk)(void*, void*); 
+};
+
+ typedef Callback<void(int)> event_callback_t;
+
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/CircularBuffer.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CIRCULARBUFFER_H
+#define MBED_CIRCULARBUFFER_H
+
+#include "critical.h"
+
+namespace mbed {
+
+/** Templated Circular buffer class
+ *
+ *  @Note Synchronization level: Interrupt safe
+ */
+template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
+class CircularBuffer {
+public:
+    CircularBuffer() : _head(0), _tail(0), _full(false) {
+    }
+
+    ~CircularBuffer() {
+    }
+
+    /** Push the transaction to the buffer. This overwrites the buffer if it's
+     *  full
+     *
+     * @param data Data to be pushed to the buffer
+     */
+    void push(const T& data) {
+        core_util_critical_section_enter();
+        if (full()) {
+            _tail++;
+            _tail %= BufferSize;
+        }
+        _pool[_head++] = data;
+        _head %= BufferSize;
+        if (_head == _tail) {
+            _full = true;
+        }
+        core_util_critical_section_exit();
+    }
+
+    /** Pop the transaction from the buffer
+     *
+     * @param data Data to be pushed to the buffer
+     * @return True if the buffer is not empty and data contains a transaction, false otherwise
+     */
+    bool pop(T& data) {
+        bool data_popped = false;
+        core_util_critical_section_enter();
+        if (!empty()) {
+            data = _pool[_tail++];
+            _tail %= BufferSize;
+            _full = false;
+            data_popped = true;
+        }
+        core_util_critical_section_exit();
+        return data_popped;
+    }
+
+    /** Check if the buffer is empty
+     *
+     * @return True if the buffer is empty, false if not
+     */
+    bool empty() {
+        core_util_critical_section_enter();
+        bool is_empty = (_head == _tail) && !_full;
+        core_util_critical_section_exit();
+        return is_empty;
+    }
+
+    /** Check if the buffer is full
+     *
+     * @return True if the buffer is full, false if not
+     */
+    bool full() {
+        core_util_critical_section_enter();
+        bool full = _full;
+        core_util_critical_section_exit();
+        return full;
+    }
+
+    /** Reset the buffer
+     *
+     */
+    void reset() {
+        core_util_critical_section_enter();
+        _head = 0;
+        _tail = 0;
+        _full = false;
+        core_util_critical_section_exit();
+    }
+
+private:
+    T _pool[BufferSize];
+    volatile CounterType _head;
+    volatile CounterType _tail;
+    volatile bool _full;
+};
+
+}
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/DigitalIn.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALIN_H
+#define MBED_DIGITALIN_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+#include "critical.h"
+
+namespace mbed {
+
+/** A digital input, used for reading the state of a pin
+ *
+ * @Note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Flash an LED while a DigitalIn is true
+ *
+ * #include "mbed.h"
+ *
+ * DigitalIn enable(p5);
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         if(enable) {
+ *             led = !led;
+ *         }
+ *         wait(0.25);
+ *     }
+ * }
+ * @endcode
+ */
+class DigitalIn {
+
+public:
+    /** Create a DigitalIn connected to the specified pin
+     *
+     *  @param pin DigitalIn pin to connect to
+     */
+    DigitalIn(PinName pin) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_in(&gpio, pin);
+    }
+
+    /** Create a DigitalIn connected to the specified pin
+     *
+     *  @param pin DigitalIn pin to connect to
+     *  @param mode the initial mode of the pin
+     */
+    DigitalIn(PinName pin, PinMode mode) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_in_ex(&gpio, pin, mode);
+    }
+    /** Read the input, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    An integer representing the state of the input pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read() {
+        // Thread safe / atomic HAL call
+        return gpio_read(&gpio);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode pull) {
+        core_util_critical_section_enter();
+        gpio_mode(&gpio, pull);
+        core_util_critical_section_exit();
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        // Thread safe / atomic HAL call
+        return gpio_is_connected(&gpio);
+    }
+
+    /** An operator shorthand for read()
+     */
+    operator int() {
+        // Underlying read is thread safe
+        return read();
+    }
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/DigitalInOut.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,141 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALINOUT_H
+#define MBED_DIGITALINOUT_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+#include "critical.h"
+
+namespace mbed {
+
+/** A digital input/output, used for setting or reading a bi-directional pin
+ *
+ * @Note Synchronization level: Interrupt safe
+ */
+class DigitalInOut {
+
+public:
+    /** Create a DigitalInOut connected to the specified pin
+     *
+     *  @param pin DigitalInOut pin to connect to
+     */
+    DigitalInOut(PinName pin) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_in(&gpio, pin);
+    }
+
+    /** Create a DigitalInOut connected to the specified pin
+     *
+     *  @param pin DigitalInOut pin to connect to
+     *  @param direction the initial direction of the pin
+     *  @param mode the initial mode of the pin
+     *  @param value the initial value of the pin if is an output
+     */
+    DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_inout(&gpio, pin, direction, mode, value);
+    }
+
+    /** Set the output, specified as 0 or 1 (int)
+     *
+     *  @param value An integer specifying the pin output value,
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
+     */
+    void write(int value) {
+        // Thread safe / atomic HAL call
+        gpio_write(&gpio, value);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    an integer representing the output setting of the pin if it is an output,
+     *    or read the input if set as an input
+     */
+    int read() {
+        // Thread safe / atomic HAL call
+        return gpio_read(&gpio);
+    }
+
+    /** Set as an output
+     */
+    void output() {
+        core_util_critical_section_enter();
+        gpio_dir(&gpio, PIN_OUTPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Set as an input
+     */
+    void input() {
+        core_util_critical_section_enter();
+        gpio_dir(&gpio, PIN_INPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode pull) {
+        core_util_critical_section_enter();
+        gpio_mode(&gpio, pull);
+        core_util_critical_section_exit();
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        // Thread safe / atomic HAL call
+        return gpio_is_connected(&gpio);
+    }
+
+    /** A shorthand for write()
+     */
+    DigitalInOut& operator= (int value) {
+        // Underlying write is thread safe
+        write(value);
+        return *this;
+    }
+
+    DigitalInOut& operator= (DigitalInOut& rhs) {
+        core_util_critical_section_enter();
+        write(rhs.read());
+        core_util_critical_section_exit();
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        // Underlying call is thread safe
+        return read();
+    }
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/DigitalOut.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALOUT_H
+#define MBED_DIGITALOUT_H
+
+#include "platform.h"
+#include "gpio_api.h"
+#include "critical.h"
+
+namespace mbed {
+
+/** A digital output, used for setting the state of a pin
+ *
+ * @Note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle a LED
+ * #include "mbed.h"
+ *
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         led = !led;
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class DigitalOut {
+
+public:
+    /** Create a DigitalOut connected to the specified pin
+     *
+     *  @param pin DigitalOut pin to connect to
+     */
+    DigitalOut(PinName pin) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_out(&gpio, pin);
+    }
+
+    /** Create a DigitalOut connected to the specified pin
+     *
+     *  @param pin DigitalOut pin to connect to
+     *  @param value the initial pin value
+     */
+    DigitalOut(PinName pin, int value) : gpio() {
+        // No lock needed in the constructor
+        gpio_init_out_ex(&gpio, pin, value);
+    }
+
+    /** Set the output, specified as 0 or 1 (int)
+     *
+     *  @param value An integer specifying the pin output value,
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
+     */
+    void write(int value) {
+        // Thread safe / atomic HAL call
+        gpio_write(&gpio, value);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    an integer representing the output setting of the pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read() {
+        // Thread safe / atomic HAL call
+        return gpio_read(&gpio);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        // Thread safe / atomic HAL call
+        return gpio_is_connected(&gpio);
+    }
+
+    /** A shorthand for write()
+     */
+    DigitalOut& operator= (int value) {
+        // Underlying write is thread safe
+        write(value);
+        return *this;
+    }
+
+    DigitalOut& operator= (DigitalOut& rhs) {
+        core_util_critical_section_enter();
+        write(rhs.read());
+        core_util_critical_section_exit();
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        // Underlying call is thread safe
+        return read();
+    }
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/DirHandle.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIRHANDLE_H
+#define MBED_DIRHANDLE_H
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+#   define NAME_MAX 255
+typedef int mode_t;
+
+#else
+#   include <sys/syslimits.h>
+#endif
+
+#include "FileHandle.h"
+
+struct dirent {
+    char d_name[NAME_MAX+1];
+};
+
+namespace mbed {
+
+/** Represents a directory stream. Objects of this type are returned
+ *  by a FileSystemLike's opendir method. Implementations must define
+ *  at least closedir, readdir and rewinddir.
+ *
+ *  If a FileSystemLike class defines the opendir method, then the
+ *  directories of an object of that type can be accessed by
+ *  DIR *d = opendir("/example/directory") (or opendir("/example")
+ *  to open the root of the filesystem), and then using readdir(d) etc.
+ *
+ *  The root directory is considered to contain all FileLike and
+ *  FileSystemLike objects, so the DIR* returned by opendir("/") will
+ *  reflect this.
+ *
+ *  @Note Synchronization level: Set by subclass
+ */
+class DirHandle {
+
+public:
+    /** Closes the directory.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on error.
+     */
+    virtual int closedir()=0;
+
+    /** Return the directory entry at the current position, and
+     *  advances the position to the next entry.
+     *
+     * @returns
+     *  A pointer to a dirent structure representing the
+     *  directory entry at the current position, or NULL on reaching
+     *  end of directory or error.
+     */
+    virtual struct dirent *readdir()=0;
+
+    /** Resets the position to the beginning of the directory.
+     */
+    virtual void rewinddir()=0;
+
+    /** Returns the current position of the DirHandle.
+     *
+     * @returns
+     *   the current position,
+     *  -1 on error.
+     */
+    virtual off_t telldir() { return -1; }
+
+    /** Sets the position of the DirHandle.
+     *
+     *  @param location The location to seek to. Must be a value returned by telldir.
+     */
+    virtual void seekdir(off_t location) { (void)location;}
+
+    virtual ~DirHandle() {}
+
+protected:
+
+    /** Acquire exclusive access to this object.
+     */
+    virtual void lock() {
+        // Stub
+    }
+
+    /** Release exclusive access to this object.
+     */
+    virtual void unlock() {
+        // Stub
+    }
+};
+
+} // namespace mbed
+
+typedef mbed::DirHandle DIR;
+
+extern "C" {
+    DIR *opendir(const char*);
+    struct dirent *readdir(DIR *);
+    int closedir(DIR*);
+    void rewinddir(DIR*);
+    long telldir(DIR*);
+    void seekdir(DIR*, long);
+    int mkdir(const char *name, mode_t n);
+};
+
+#endif /* MBED_DIRHANDLE_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/Ethernet.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,173 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_H
+#define MBED_ETHERNET_H
+
+#include "platform.h"
+
+#if DEVICE_ETHERNET
+
+namespace mbed {
+
+/** An ethernet interface, to use with the ethernet pins.
+ *
+ * @Note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Read destination and source from every ethernet packet
+ *
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ *     char buf[0x600];
+ *
+ *     while(1) {
+ *         int size = eth.receive();
+ *         if(size > 0) {
+ *             eth.read(buf, size);
+ *             printf("Destination:  %02X:%02X:%02X:%02X:%02X:%02X\n",
+ *                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ *             printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ *                     buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
+ *         }
+ *
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+class Ethernet {
+
+public:
+
+    /** Initialise the ethernet interface.
+     */
+    Ethernet();
+
+    /** Powers the hardware down.
+     */
+    virtual ~Ethernet();
+
+    enum Mode {
+        AutoNegotiate,
+        HalfDuplex10,
+        FullDuplex10,
+        HalfDuplex100,
+        FullDuplex100
+    };
+
+    /** Writes into an outgoing ethernet packet.
+     *
+     *  It will append size bytes of data to the previously written bytes.
+     *
+     *  @param data An array to write.
+     *  @param size The size of data.
+     *
+     *  @returns
+     *   The number of written bytes.
+     */
+    int write(const char *data, int size);
+
+    /** Send an outgoing ethernet packet.
+     *
+     *  After filling in the data in an ethernet packet it must be send.
+     *  Send will provide a new packet to write to.
+     *
+     *  @returns
+     *    0 if the sending was failed,
+     *    or the size of the packet successfully sent.
+     */
+    int send();
+
+    /** Recevies an arrived ethernet packet.
+     *
+     *  Receiving an ethernet packet will drop the last received ethernet packet
+     *  and make a new ethernet packet ready to read.
+     *  If no ethernet packet is arrived it will return 0.
+     *
+     *  @returns
+     *    0 if no ethernet packet is arrived,
+     *    or the size of the arrived packet.
+     */
+    int receive();
+
+    /** Read from an recevied ethernet packet.
+     *
+     *  After receive returnd a number bigger than 0it is
+     *  possible to read bytes from this packet.
+     *  Read will write up to size bytes into data.
+     *
+     *  It is possible to use read multible times.
+     *  Each time read will start reading after the last read byte before.
+     *
+     *  @returns
+     *  The number of byte read.
+     */
+    int read(char *data, int size);
+
+    /** Gives the ethernet address of the mbed.
+     *
+     *  @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
+     */
+    void address(char *mac);
+
+    /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
+     *
+     *  @returns
+     *   0 if no ethernet link is pressent,
+     *   1 if an ethernet link is pressent.
+     *
+     * Example:
+     * @code
+     * // Using the Ethernet link function
+     * #include "mbed.h"
+     *
+     * Ethernet eth;
+     *
+     * int main() {
+     *     wait(1); // Needed after startup.
+     *     if (eth.link()) {
+     *          printf("online\n");
+     *     } else {
+     *          printf("offline\n");
+     *     }
+     * }
+     * @endcode
+     */
+    int link();
+
+    /** Sets the speed and duplex parameters of an ethernet link
+     *
+     * - AutoNegotiate      Auto negotiate speed and duplex
+     * - HalfDuplex10       10 Mbit, half duplex
+     * - FullDuplex10       10 Mbit, full duplex
+     * - HalfDuplex100      100 Mbit, half duplex
+     * - FullDuplex100      100 Mbit, full duplex
+     *
+     *  @param mode the speed and duplex mode to set the link to:
+     */
+    void set_link(Mode mode);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/FileBase.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEBASE_H
+#define MBED_FILEBASE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+#    define O_RDONLY 0
+#    define O_WRONLY 1
+#    define O_RDWR   2
+#    define O_CREAT  0x0200
+#    define O_TRUNC  0x0400
+#    define O_APPEND 0x0008
+
+#    define NAME_MAX 255
+
+typedef int mode_t;
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+#    include <sys/fcntl.h>
+#    include <sys/types.h>
+#    include <sys/syslimits.h>
+#endif
+
+#include "platform.h"
+#include "SingletonPtr.h"
+#include "PlatformMutex.h"
+
+namespace mbed {
+
+typedef enum {
+    FilePathType,
+    FileSystemPathType
+} PathType;
+
+class FileBase {
+public:
+    FileBase(const char *name, PathType t);
+
+    virtual ~FileBase();
+
+    const char* getName(void);
+    PathType    getPathType(void);
+
+    static FileBase *lookup(const char *name, unsigned int len);
+
+    static FileBase *get(int n);
+
+    /* disallow copy constructor and assignment operators */
+private:
+    static FileBase *_head;
+    static SingletonPtr<PlatformMutex> _mutex;
+
+    FileBase   *_next;
+    const char * const _name;
+    const PathType _path_type;
+    FileBase(const FileBase&);
+    FileBase & operator = (const FileBase&);
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/FileHandle.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,141 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEHANDLE_H
+#define MBED_FILEHANDLE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+#   include <sys/types.h>
+#endif
+
+namespace mbed {
+
+/** An OO equivalent of the internal FILEHANDLE variable
+ *  and associated _sys_* functions.
+ *
+ * FileHandle is an abstract class, needing at least sys_write and
+ *  sys_read to be implmented for a simple interactive device.
+ *
+ * No one ever directly tals to/instanciates a FileHandle - it gets
+ *  created by FileSystem, and wrapped up by stdio.
+ *
+ * @Note Synchronization level: Set by subclass
+ */
+class FileHandle {
+
+public:
+    /** Write the contents of a buffer to the file
+     *
+     *  @param buffer the buffer to write from
+     *  @param length the number of characters to write
+     *
+     *  @returns
+     *  The number of characters written (possibly 0) on success, -1 on error.
+     */
+    virtual ssize_t write(const void* buffer, size_t length) = 0;
+
+    /** Close the file
+     *
+     *  @returns
+     *  Zero on success, -1 on error.
+     */
+    virtual int close() = 0;
+
+    /** Function read
+     *  Reads the contents of the file into a buffer
+     *
+     *  @param buffer the buffer to read in to
+     *  @param length the number of characters to read
+     *
+     *  @returns
+     *  The number of characters read (zero at end of file) on success, -1 on error.
+     */
+    virtual ssize_t read(void* buffer, size_t length) = 0;
+
+    /** Check if the handle is for a interactive terminal device.
+     * If so, line buffered behaviour is used by default
+     *
+     *  @returns
+     *    1 if it is a terminal,
+     *    0 otherwise
+     */
+    virtual int isatty() = 0;
+
+    /** Move the file position to a given offset from a given location.
+     *
+     *  @param offset The offset from whence to move to
+     *  @param whence SEEK_SET for the start of the file, SEEK_CUR for the
+     *   current file position, or SEEK_END for the end of the file.
+     *
+     *  @returns
+     *    new file position on success,
+     *    -1 on failure or unsupported
+     */
+    virtual off_t lseek(off_t offset, int whence) = 0;
+
+    /** Flush any buffers associated with the FileHandle, ensuring it
+     *  is up to date on disk
+     *
+     *  @returns
+     *    0 on success or un-needed,
+     *   -1 on error
+     */
+    virtual int fsync() = 0;
+
+    virtual off_t flen() {
+        lock();
+        /* remember our current position */
+        off_t pos = lseek(0, SEEK_CUR);
+        if(pos == -1) {
+            unlock();
+            return -1;
+        }
+        /* seek to the end to get the file length */
+        off_t res = lseek(0, SEEK_END);
+        /* return to our old position */
+        lseek(pos, SEEK_SET);
+        unlock();
+        return res;
+    }
+
+    virtual ~FileHandle();
+
+protected:
+
+    /** Acquire exclusive access to this object.
+     */
+    virtual void lock() {
+        // Stub
+    }
+
+    /** Release exclusive access to this object.
+     */
+    virtual void unlock() {
+        // Stub
+    }
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/FileLike.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILELIKE_H
+#define MBED_FILELIKE_H
+
+#include "FileBase.h"
+#include "FileHandle.h"
+
+namespace mbed {
+
+/* Class FileLike
+ *  A file-like object is one that can be opened with fopen by
+ *  fopen("/name", mode). It is intersection of the classes Base and
+ *  FileHandle.
+ *
+ *  @Note Synchronization level: Set by subclass
+ */
+class FileLike : public FileHandle, public FileBase {
+
+public:
+    /* Constructor FileLike
+     *
+     * Variables
+     *  name - The name to use to open the file.
+     */
+    FileLike(const char *name);
+
+    virtual ~FileLike();
+
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/FilePath.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEPATH_H
+#define MBED_FILEPATH_H
+
+#include "platform.h"
+
+#include "FileSystemLike.h"
+#include "FileLike.h"
+
+namespace mbed {
+
+class FilePath {
+public:
+    FilePath(const char* file_path);
+
+    const char* fileName(void);
+
+    bool          isFileSystem(void);
+    FileSystemLike* fileSystem(void);
+
+    bool    isFile(void);
+    FileLike* file(void);
+    bool    exists(void);
+
+private:
+    const char* file_name;
+    FileBase* fb;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/FileSystemLike.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILESYSTEMLIKE_H
+#define MBED_FILESYSTEMLIKE_H
+
+#include "platform.h"
+
+#include "FileBase.h"
+#include "FileHandle.h"
+#include "DirHandle.h"
+
+namespace mbed {
+
+/** A filesystem-like object is one that can be used to open files
+ *  though it by fopen("/name/filename", mode)
+ *
+ *  Implementations must define at least open (the default definitions
+ *  of the rest of the functions just return error values).
+ *
+ * @Note Synchronization level: Set by subclass
+ */
+class FileSystemLike : public FileBase {
+
+public:
+    /** FileSystemLike constructor
+     *
+     *  @param name The name to use for the filesystem.
+     */
+    FileSystemLike(const char *name);
+
+    virtual ~FileSystemLike();
+
+    static DirHandle *opendir();
+    friend class BaseDirHandle;
+
+    /** Opens a file from the filesystem
+     *
+     *  @param filename The name of the file to open.
+     *  @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
+     *    zero or more of O_CREAT, O_TRUNC, or O_APPEND.
+     *
+     *  @returns
+     *    A pointer to a FileHandle object representing the
+     *   file on success, or NULL on failure.
+     */
+    virtual FileHandle *open(const char *filename, int flags) = 0;
+
+    /** Remove a file from the filesystem.
+     *
+     *  @param filename the name of the file to remove.
+     *  @param returns 0 on success, -1 on failure.
+     */
+    virtual int remove(const char *filename) { (void) filename; return -1; };
+
+    /** Rename a file in the filesystem.
+     *
+     *  @param oldname the name of the file to rename.
+     *  @param newname the name to rename it to.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on failure.
+     */
+    virtual int rename(const char *oldname, const char *newname) { (void) oldname, (void) newname; return -1; };
+
+    /** Opens a directory in the filesystem and returns a DirHandle
+     *   representing the directory stream.
+     *
+     *  @param name The name of the directory to open.
+     *
+     *  @returns
+     *    A DirHandle representing the directory stream, or
+     *   NULL on failure.
+     */
+    virtual DirHandle *opendir(const char *name) { (void) name; return NULL; };
+
+    /** Creates a directory in the filesystem.
+     *
+     *  @param name The name of the directory to create.
+     *  @param mode The permissions to create the directory with.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on failure.
+     */
+    virtual int mkdir(const char *name, mode_t mode) { (void) name, (void) mode; return -1; }
+
+    // TODO other filesystem functions (mkdir, rm, rn, ls etc)
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/FunctionPointer.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FUNCTIONPOINTER_H
+#define MBED_FUNCTIONPOINTER_H
+
+#include "Callback.h"
+#include "toolchain.h"
+#include <string.h>
+#include <stdint.h>
+
+namespace mbed {
+
+
+// Declarations for backwards compatibility
+// To be foward compatible, code should adopt the Callback class
+template <typename R, typename A1>
+class FunctionPointerArg1 : public Callback<R(A1)> {
+public:
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
+    FunctionPointerArg1(R (*function)(A1) = 0)
+        : Callback<R(A1)>(function) {}
+
+    template<typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
+    FunctionPointerArg1(T *object, R (T::*member)(A1))
+        : Callback<R(A1)>(object, member) {}
+
+    R (*get_function())(A1) {
+        return *reinterpret_cast<R (**)(A1)>(this);
+    }
+};
+
+template <typename R>
+class FunctionPointerArg1<R, void> : public Callback<R()> {
+public:
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "FunctionPointer has been replaced by Callback<void()>")
+    FunctionPointerArg1(R (*function)() = 0)
+        : Callback<R()>(function) {}
+
+    template<typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "FunctionPointer has been replaced by Callback<void()>")
+    FunctionPointerArg1(T *object, R (T::*member)())
+        : Callback<R()>(object, member) {}
+
+    R (*get_function())() {
+        return *reinterpret_cast<R (**)()>(this);
+    }
+};
+
+typedef FunctionPointerArg1<void, void> FunctionPointer;
+
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/I2C.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,194 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_H
+#define MBED_I2C_H
+
+#include "platform.h"
+
+#if DEVICE_I2C
+
+#include "i2c_api.h"
+#include "SingletonPtr.h"
+#include "PlatformMutex.h"
+
+#if DEVICE_I2C_ASYNCH
+#include "CThunk.h"
+#include "dma_api.h"
+#include "FunctionPointer.h"
+#endif
+
+namespace mbed {
+
+/** An I2C Master, used for communicating with I2C slave devices
+ *
+ * @Note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Read from I2C slave at address 0x62
+ *
+ * #include "mbed.h"
+ *
+ * I2C i2c(p28, p27);
+ *
+ * int main() {
+ *     int address = 0x62;
+ *     char data[2];
+ *     i2c.read(address, data, 2);
+ * }
+ * @endcode
+ */
+class I2C {
+
+public:
+    enum RxStatus {
+        NoData,
+        MasterGeneralCall,
+        MasterWrite,
+        MasterRead
+    };
+
+    enum Acknowledge {
+        NoACK = 0,
+        ACK   = 1
+    };
+
+    /** Create an I2C Master interface, connected to the specified pins
+     *
+     *  @param sda I2C data line pin
+     *  @param scl I2C clock line pin
+     */
+    I2C(PinName sda, PinName scl);
+
+    /** Set the frequency of the I2C interface
+     *
+     *  @param hz The bus frequency in hertz
+     */
+    void frequency(int hz);
+
+    /** Read from an I2C slave
+     *
+     * Performs a complete read transaction. The bottom bit of
+     * the address is forced to 1 to indicate a read.
+     *
+     *  @param address 8-bit I2C slave address [ addr | 1 ]
+     *  @param data Pointer to the byte-array to read data in to
+     *  @param length Number of bytes to read
+     *  @param repeated Repeated start, true - don't send stop at end
+     *
+     *  @returns
+     *       0 on success (ack),
+     *   non-0 on failure (nack)
+     */
+    int read(int address, char *data, int length, bool repeated = false);
+
+    /** Read a single byte from the I2C bus
+     *
+     *  @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
+     *
+     *  @returns
+     *    the byte read
+     */
+    int read(int ack);
+
+    /** Write to an I2C slave
+     *
+     * Performs a complete write transaction. The bottom bit of
+     * the address is forced to 0 to indicate a write.
+     *
+     *  @param address 8-bit I2C slave address [ addr | 0 ]
+     *  @param data Pointer to the byte-array data to send
+     *  @param length Number of bytes to send
+     *  @param repeated Repeated start, true - do not send stop at end
+     *
+     *  @returns
+     *       0 on success (ack),
+     *   non-0 on failure (nack)
+     */
+    int write(int address, const char *data, int length, bool repeated = false);
+
+    /** Write single byte out on the I2C bus
+     *
+     *  @param data data to write out on bus
+     *
+     *  @returns
+     *    '1' if an ACK was received,
+     *    '0' otherwise
+     */
+    int write(int data);
+
+    /** Creates a start condition on the I2C bus
+     */
+
+    void start(void);
+
+    /** Creates a stop condition on the I2C bus
+     */
+    void stop(void);
+
+    /** Acquire exclusive access to this I2C bus
+     */
+    virtual void lock(void);
+
+    /** Release exclusive access to this I2C bus
+     */
+    virtual void unlock(void);
+
+    virtual ~I2C() {
+        // Do nothing
+    }
+
+#if DEVICE_I2C_ASYNCH
+
+    /** Start non-blocking I2C transfer.
+     *
+     * @param address   8/10 bit I2c slave address
+     * @param tx_buffer The TX buffer with data to be transfered
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data
+     * @param rx_length The length of RX buffer in bytes
+     * @param event     The logical OR of events to modify
+     * @param callback  The event callback function
+     * @param repeated Repeated start, true - do not send stop at end
+     * @return Zero if the transfer has started, or -1 if I2C peripheral is busy
+     */
+    int transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event = I2C_EVENT_TRANSFER_COMPLETE, bool repeated = false);
+
+    /** Abort the on-going I2C transfer
+     */
+    void abort_transfer();
+protected:
+    void irq_handler_asynch(void);
+    event_callback_t _callback;
+    CThunk<I2C> _irq;
+    DMAUsage _usage;
+#endif
+
+protected:
+    void aquire();
+
+    i2c_t _i2c;
+    static I2C  *_owner;
+    int         _hz;
+    static SingletonPtr<PlatformMutex> _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/I2CSlave.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,157 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_SLAVE_H
+#define MBED_I2C_SLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_I2CSLAVE
+
+#include "i2c_api.h"
+
+namespace mbed {
+
+/** An I2C Slave, used for communicating with an I2C Master device
+ *
+ * @Note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Simple I2C responder
+ * #include <mbed.h>
+ *
+ * I2CSlave slave(p9, p10);
+ *
+ * int main() {
+ *     char buf[10];
+ *     char msg[] = "Slave!";
+ *
+ *     slave.address(0xA0);
+ *     while (1) {
+ *         int i = slave.receive();
+ *         switch (i) {
+ *             case I2CSlave::ReadAddressed:
+ *                 slave.write(msg, strlen(msg) + 1); // Includes null char
+ *                 break;
+ *             case I2CSlave::WriteGeneral:
+ *                 slave.read(buf, 10);
+ *                 printf("Read G: %s\n", buf);
+ *                 break;
+ *             case I2CSlave::WriteAddressed:
+ *                 slave.read(buf, 10);
+ *                 printf("Read A: %s\n", buf);
+ *                 break;
+ *         }
+ *         for(int i = 0; i < 10; i++) buf[i] = 0;    // Clear buffer
+ *     }
+ * }
+ * @endcode
+ */
+class I2CSlave {
+
+public:
+    enum RxStatus {
+        NoData         = 0,
+        ReadAddressed  = 1,
+        WriteGeneral   = 2,
+        WriteAddressed = 3
+    };
+
+    /** Create an I2C Slave interface, connected to the specified pins.
+     *
+     *  @param sda I2C data line pin
+     *  @param scl I2C clock line pin
+     */
+    I2CSlave(PinName sda, PinName scl);
+
+    /** Set the frequency of the I2C interface
+     *
+     *  @param hz The bus frequency in hertz
+     */
+    void frequency(int hz);
+
+    /** Checks to see if this I2C Slave has been addressed.
+     *
+     *  @returns
+     *  A status indicating if the device has been addressed, and how
+     *  - NoData            - the slave has not been addressed
+     *  - ReadAddressed     - the master has requested a read from this slave
+     *  - WriteAddressed    - the master is writing to this slave
+     *  - WriteGeneral      - the master is writing to all slave
+     */
+    int receive(void);
+
+    /** Read from an I2C master.
+     *
+     *  @param data pointer to the byte array to read data in to
+     *  @param length maximum number of bytes to read
+     *
+     *  @returns
+     *       0 on success,
+     *   non-0 otherwise
+     */
+    int read(char *data, int length);
+
+    /** Read a single byte from an I2C master.
+     *
+     *  @returns
+     *    the byte read
+     */
+    int read(void);
+
+    /** Write to an I2C master.
+     *
+     *  @param data pointer to the byte array to be transmitted
+     *  @param length the number of bytes to transmite
+     *
+     *  @returns
+     *       0 on success,
+     *   non-0 otherwise
+     */
+    int write(const char *data, int length);
+
+    /** Write a single byte to an I2C master.
+     *
+     *  @data the byte to write
+     *
+     *  @returns
+     *    '1' if an ACK was received,
+     *    '0' otherwise
+     */
+    int write(int data);
+
+    /** Sets the I2C slave address.
+     *
+     *  @param address The address to set for the slave (ignoring the least
+     *  signifcant bit). If set to 0, the slave will only respond to the
+     *  general call address.
+     */
+    void address(int address);
+
+    /** Reset the I2C slave back into the known ready receiving state.
+     */
+    void stop(void);
+
+protected:
+    i2c_t _i2c;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/InterruptIn.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,148 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTIN_H
+#define MBED_INTERRUPTIN_H
+
+#include "platform.h"
+
+#if DEVICE_INTERRUPTIN
+
+#include "gpio_api.h"
+#include "gpio_irq_api.h"
+#include "Callback.h"
+#include "critical.h"
+
+namespace mbed {
+
+/** A digital interrupt input, used to call a function on a rising or falling edge
+ *
+ * @Note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Flash an LED while waiting for events
+ *
+ * #include "mbed.h"
+ *
+ * InterruptIn event(p16);
+ * DigitalOut led(LED1);
+ *
+ * void trigger() {
+ *     printf("triggered!\n");
+ * }
+ *
+ * int main() {
+ *     event.rise(&trigger);
+ *     while(1) {
+ *         led = !led;
+ *         wait(0.25);
+ *     }
+ * }
+ * @endcode
+ */
+class InterruptIn {
+
+public:
+
+    /** Create an InterruptIn connected to the specified pin
+     *
+     *  @param pin InterruptIn pin to connect to
+     *  @param name (optional) A string to identify the object
+     */
+    InterruptIn(PinName pin);
+    virtual ~InterruptIn();
+
+    /** Read the input, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    An integer representing the state of the input pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read();
+
+    /** An operator shorthand for read()
+     */
+    operator int();
+
+
+    /** Attach a function to call when a rising edge occurs on the input
+     *
+     *  @param func A pointer to a void function, or 0 to set as none
+     */
+    void rise(Callback<void()> func);
+
+    /** Attach a member function to call when a rising edge occurs on the input
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     */
+    template<typename T, typename M>
+    void rise(T *obj, M method) {
+        core_util_critical_section_enter();
+        rise(Callback<void()>(obj, method));
+        core_util_critical_section_exit();
+    }
+
+    /** Attach a function to call when a falling edge occurs on the input
+     *
+     *  @param func A pointer to a void function, or 0 to set as none
+     */
+    void fall(Callback<void()> func);
+
+    /** Attach a member function to call when a falling edge occurs on the input
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     */
+    template<typename T, typename M>
+    void fall(T *obj, M method) {
+        core_util_critical_section_enter();
+        fall(Callback<void()>(obj, method));
+        core_util_critical_section_exit();
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+    /** Enable IRQ. This method depends on hw implementation, might enable one
+     *  port interrupts. For further information, check gpio_irq_enable().
+     */
+    void enable_irq();
+
+    /** Disable IRQ. This method depends on hw implementation, might disable one
+     *  port interrupts. For further information, check gpio_irq_disable().
+     */
+    void disable_irq();
+
+    static void _irq_handler(uint32_t id, gpio_irq_event event);
+
+protected:
+    gpio_t gpio;
+    gpio_irq_t gpio_irq;
+
+    Callback<void()> _rise;
+    Callback<void()> _fall;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/InterruptManager.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,157 @@
+#ifndef MBED_INTERRUPTMANAGER_H
+#define MBED_INTERRUPTMANAGER_H
+
+#include "cmsis.h"
+#include "CallChain.h"
+#include "PlatformMutex.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Use this singleton if you need to chain interrupt handlers.
+ *
+ * @Note Synchronization level: Thread safe
+ *
+ * Example (for LPC1768):
+ * @code
+ * #include "InterruptManager.h"
+ * #include "mbed.h"
+ *
+ * Ticker flipper;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * void flip(void) {
+ *     led1 = !led1;
+ * }
+ *
+ * void handler(void) {
+ *     led2 = !led1;
+ * }
+ *
+ * int main() {
+ *     led1 = led2 = 0;
+ *     flipper.attach(&flip, 1.0);
+ *     InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
+ * }
+ * @endcode
+ */
+class InterruptManager {
+public:
+    /** Return the only instance of this class
+     */
+    static InterruptManager* get();
+
+    /** Destroy the current instance of the interrupt manager
+     */
+    static void destroy();
+
+    /** Add a handler for an interrupt at the end of the handler list
+     *
+     *  @param function the handler to add
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
+        // Underlying call is thread safe
+        return add_common(function, irq);
+    }
+
+    /** Add a handler for an interrupt at the beginning of the handler list
+     *
+     *  @param function the handler to add
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
+        // Underlying call is thread safe
+        return add_common(function, irq, true);
+    }
+
+    /** Add a handler for an interrupt at the end of the handler list
+     *
+     *  @param tptr pointer to the object that has the handler function
+     *  @param mptr pointer to the actual handler function
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+        // Underlying call is thread safe
+        return add_common(tptr, mptr, irq);
+    }
+
+    /** Add a handler for an interrupt at the beginning of the handler list
+     *
+     *  @param tptr pointer to the object that has the handler function
+     *  @param mptr pointer to the actual handler function
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+        // Underlying call is thread safe
+        return add_common(tptr, mptr, irq, true);
+    }
+
+    /** Remove a handler from an interrupt
+     *
+     *  @param handler the function object for the handler to remove
+     *  @param irq the interrupt number
+     *
+     *  @returns
+     *  true if the handler was found and removed, false otherwise
+     */
+    bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
+
+private:
+    InterruptManager();
+    ~InterruptManager();
+
+    void lock();
+    void unlock();
+
+    // We declare the copy contructor and the assignment operator, but we don't
+    // implement them. This way, if someone tries to copy/assign our instance,
+    // he will get an error at compile time.
+    InterruptManager(const InterruptManager&);
+    InterruptManager& operator =(const InterruptManager&);
+
+    template<typename T>
+    pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
+        _mutex.lock();
+        int irq_pos = get_irq_index(irq);
+        bool change = must_replace_vector(irq);
+
+        pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
+        if (change)
+            NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+        _mutex.unlock();
+        return pf;
+    }
+
+    pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
+    bool must_replace_vector(IRQn_Type irq);
+    int get_irq_index(IRQn_Type irq);
+    void irq_helper();
+    void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
+    static void static_irq_helper();
+
+    CallChain* _chains[NVIC_NUM_VECTORS];
+    static InterruptManager* _instance;
+    PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/LocalFileSystem.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,111 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOCALFILESYSTEM_H
+#define MBED_LOCALFILESYSTEM_H
+
+#include "platform.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "FileSystemLike.h"
+#include "PlatformMutex.h"
+
+namespace mbed {
+
+FILEHANDLE local_file_open(const char* name, int flags);
+
+class LocalFileHandle : public FileHandle {
+
+public:
+    LocalFileHandle(FILEHANDLE fh);
+
+    virtual int close();
+
+    virtual ssize_t write(const void *buffer, size_t length);
+
+    virtual ssize_t read(void *buffer, size_t length);
+
+    virtual int isatty();
+
+    virtual off_t lseek(off_t position, int whence);
+
+    virtual int fsync();
+
+    virtual off_t flen();
+
+protected:
+    virtual void lock();
+    virtual void unlock();
+    FILEHANDLE _fh;
+    int pos;
+    PlatformMutex _mutex;
+};
+
+/** A filesystem for accessing the local mbed Microcontroller USB disk drive
+ *
+ *  This allows programs to read and write files on the same disk drive that is used to program the
+ *  mbed Microcontroller. Once created, the standard C file access functions are used to open,
+ *  read and write files.
+ *
+ * @Note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * LocalFileSystem local("local");               // Create the local filesystem under the name "local"
+ *
+ * int main() {
+ *     FILE *fp = fopen("/local/out.txt", "w");  // Open "out.txt" on the local file system for writing
+ *     fprintf(fp, "Hello World!");
+ *     fclose(fp);
+ *     remove("/local/out.txt");                 // Removes the file "out.txt" from the local file system
+ *
+ *     DIR *d = opendir("/local");               // Opens the root directory of the local file system
+ *     struct dirent *p;
+ *     while((p = readdir(d)) != NULL) {         // Print the names of the files in the local file system
+ *       printf("%s\n", p->d_name);              // to stdout.
+ *     }
+ *     closedir(d);
+ * }
+ * @endcode
+ *
+ * @note
+ *  If the microcontroller program makes an access to the local drive, it will be marked as "removed"
+ *  on the Host computer. This means it is no longer accessible from the Host Computer.
+ *
+ *  The drive will only re-appear when the microcontroller program exists. Note that if the program does
+ *  not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
+ */
+class LocalFileSystem : public FileSystemLike {
+    // No modifiable state
+
+public:
+    LocalFileSystem(const char* n) : FileSystemLike(n) {
+
+    }
+
+    virtual FileHandle *open(const char* name, int flags);
+    virtual int remove(const char *filename);
+    virtual DirHandle *opendir(const char *name);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/LowPowerTicker.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTICKER_H
+#define MBED_LOWPOWERTICKER_H
+
+#include "platform.h"
+#include "Ticker.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "lp_ticker_api.h"
+
+namespace mbed {
+
+/** Low Power Ticker
+ *
+ * @Note Synchronization level: Interrupt safe
+ */
+class LowPowerTicker : public Ticker {
+
+public:
+    LowPowerTicker() : Ticker(get_lp_ticker_data()) {
+    }
+
+    virtual ~LowPowerTicker() {
+    }
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/LowPowerTimeout.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMEOUT_H
+#define MBED_LOWPOWERTIMEOUT_H
+
+#include "platform.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "lp_ticker_api.h"
+#include "LowPowerTicker.h"
+
+namespace mbed {
+
+/** Low Power Timout
+ *
+ * @Note Synchronization level: Interrupt safe
+ */
+class LowPowerTimeout : public LowPowerTicker {
+
+private:
+    virtual void handler(void) {
+        _function.call();
+    }
+};
+
+}
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/LowPowerTimer.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMER_H
+#define MBED_LOWPOWERTIMER_H
+
+#include "platform.h"
+#include "Timer.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "lp_ticker_api.h"
+
+namespace mbed {
+
+/** Low power timer
+ *
+ * @Note Synchronization level: Interrupt safe
+ */
+class LowPowerTimer : public Timer {
+
+public:
+    LowPowerTimer() : Timer(get_lp_ticker_data()) {
+    }
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/PlatformMutex.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef PLATFORM_MUTEX_H
+#define PLATFORM_MUTEX_H
+
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "Mutex.h"
+typedef rtos::Mutex PlatformMutex;
+#else
+/** A stub mutex for when an RTOS is not present
+*/
+class PlatformMutex {
+public:
+    PlatformMutex() {
+        // Stub
+
+    }
+    ~PlatformMutex() {
+        // Stub
+    }
+
+    void lock() {
+        // Do nothing
+    }
+
+    void unlock() {
+        // Do nothing
+    }
+};
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/PortIn.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTIN_H
+#define MBED_PORTIN_H
+
+#include "platform.h"
+
+#if DEVICE_PORTIN
+
+#include "port_api.h"
+#include "critical.h"
+
+namespace mbed {
+
+/** A multiple pin digital input
+ *
+ * @Note Synchronization level: Interrupt safe
+ *
+ *  Example:
+ * @code
+ * // Switch on an LED if any of mbed pins 21-26 is high
+ *
+ * #include "mbed.h"
+ *
+ * PortIn     p(Port2, 0x0000003F);   // p21-p26
+ * DigitalOut ind(LED4);
+ *
+ * int main() {
+ *     while(1) {
+ *         int pins = p.read();
+ *         if(pins) {
+ *             ind = 1;
+ *         } else {
+ *             ind = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class PortIn {
+public:
+
+    /** Create an PortIn, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+        */
+    PortIn(PortName port, int mask = 0xFFFFFFFF) {
+        core_util_critical_section_enter();
+        port_init(&_port, port, mask, PIN_INPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated port pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode mode) {
+        core_util_critical_section_enter();
+        port_mode(&_port, mode);
+        core_util_critical_section_exit();
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/PortInOut.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTINOUT_H
+#define MBED_PORTINOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTINOUT
+
+#include "port_api.h"
+#include "critical.h"
+
+namespace mbed {
+
+/** A multiple pin digital in/out used to set/read multiple bi-directional pins
+ *
+ * @Note Synchronization level: Interrupt safe
+ */
+class PortInOut {
+public:
+
+    /** Create an PortInOut, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+     */
+    PortInOut(PortName port, int mask = 0xFFFFFFFF) {
+        core_util_critical_section_enter();
+        port_init(&_port, port, mask, PIN_INPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Write the value to the output port
+     *
+     *  @param value An integer specifying a bit to write for every corresponding port pin
+     */
+    void write(int value) {
+        port_write(&_port, value);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated port pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** Set as an output
+     */
+    void output() {
+        core_util_critical_section_enter();
+        port_dir(&_port, PIN_OUTPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Set as an input
+     */
+    void input() {
+        core_util_critical_section_enter();
+        port_dir(&_port, PIN_INPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode mode) {
+        core_util_critical_section_enter();
+        port_mode(&_port, mode);
+        core_util_critical_section_exit();
+    }
+
+    /** A shorthand for write()
+     */
+    PortInOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    PortInOut& operator= (PortInOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/PortOut.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,110 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTOUT_H
+#define MBED_PORTOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTOUT
+
+#include "port_api.h"
+#include "critical.h"
+
+namespace mbed {
+/** A multiple pin digital out
+ *
+ * @Note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle all four LEDs
+ *
+ * #include "mbed.h"
+ *
+ * // LED1 = P1.18  LED2 = P1.20  LED3 = P1.21  LED4 = P1.23
+ * #define LED_MASK 0x00B40000
+ *
+ * PortOut ledport(Port1, LED_MASK);
+ *
+ * int main() {
+ *     while(1) {
+ *         ledport = LED_MASK;
+ *         wait(1);
+ *         ledport = 0;
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+class PortOut {
+public:
+
+    /** Create an PortOut, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+     */
+    PortOut(PortName port, int mask = 0xFFFFFFFF) {
+        core_util_critical_section_enter();
+        port_init(&_port, port, mask, PIN_OUTPUT);
+        core_util_critical_section_exit();
+    }
+
+    /** Write the value to the output port
+     *
+     *  @param value An integer specifying a bit to write for every corresponding PortOut pin
+     */
+    void write(int value) {
+        port_write(&_port, value);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated PortOut pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** A shorthand for write()
+     */
+    PortOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    PortOut& operator= (PortOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/PwmOut.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,182 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_H
+#define MBED_PWMOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PWMOUT
+#include "pwmout_api.h"
+#include "critical.h"
+
+namespace mbed {
+
+/** A pulse-width modulation digital output
+ *
+ * @Note Synchronization level: Interrupt safe
+ *
+ * Example
+ * @code
+ * // Fade a led on.
+ * #include "mbed.h"
+ *
+ * PwmOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         led = led + 0.01;
+ *         wait(0.2);
+ *         if(led == 1.0) {
+ *             led = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ *
+ * @note
+ *  On the LPC1768 and LPC2368, the PWMs all share the same
+ *  period - if you change the period for one, you change it for all.
+ *  Although routines that change the period maintain the duty cycle
+ *  for its PWM, all other PWMs will require their duty cycle to be
+ *  refreshed.
+ */
+class PwmOut {
+
+public:
+
+    /** Create a PwmOut connected to the specified pin
+     *
+     *  @param pin PwmOut pin to connect to
+     */
+    PwmOut(PinName pin) {
+        core_util_critical_section_enter();
+        pwmout_init(&_pwm, pin);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the ouput duty-cycle, specified as a percentage (float)
+     *
+     *  @param value A floating-point value representing the output duty-cycle,
+     *    specified as a percentage. The value should lie between
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
+     */
+    void write(float value) {
+        core_util_critical_section_enter();
+        pwmout_write(&_pwm, value);
+        core_util_critical_section_exit();
+    }
+
+    /** Return the current output duty-cycle setting, measured as a percentage (float)
+     *
+     *  @returns
+     *    A floating-point value representing the current duty-cycle being output on the pin,
+     *    measured as a percentage. The returned value will lie between
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
+     *
+     *  @note
+     *  This value may not match exactly the value set by a previous <write>.
+     */
+    float read() {
+        core_util_critical_section_enter();
+        float val = pwmout_read(&_pwm);
+        core_util_critical_section_exit();
+        return val;
+    }
+
+    /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
+     *
+     *  @note
+     *   The resolution is currently in microseconds; periods smaller than this
+     *   will be set to zero.
+     */
+    void period(float seconds) {
+        core_util_critical_section_enter();
+        pwmout_period(&_pwm, seconds);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
+     */
+    void period_ms(int ms) {
+        core_util_critical_section_enter();
+        pwmout_period_ms(&_pwm, ms);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
+     */
+    void period_us(int us) {
+        core_util_critical_section_enter();
+        pwmout_period_us(&_pwm, us);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
+     */
+    void pulsewidth(float seconds) {
+        core_util_critical_section_enter();
+        pwmout_pulsewidth(&_pwm, seconds);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
+     */
+    void pulsewidth_ms(int ms) {
+        core_util_critical_section_enter();
+        pwmout_pulsewidth_ms(&_pwm, ms);
+        core_util_critical_section_exit();
+    }
+
+    /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
+     */
+    void pulsewidth_us(int us) {
+        core_util_critical_section_enter();
+        pwmout_pulsewidth_us(&_pwm, us);
+        core_util_critical_section_exit();
+    }
+
+    /** A operator shorthand for write()
+     */
+    PwmOut& operator= (float value) {
+        // Underlying call is thread safe
+        write(value);
+        return *this;
+    }
+
+    PwmOut& operator= (PwmOut& rhs) {
+        // Underlying call is thread safe
+        write(rhs.read());
+        return *this;
+    }
+
+    /** An operator shorthand for read()
+     */
+    operator float() {
+        // Underlying call is thread safe
+        return read();
+    }
+
+protected:
+    pwmout_t _pwm;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/RawSerial.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RAW_SERIAL_H
+#define MBED_RAW_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "SerialBase.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ * This is a variation of the Serial class that doesn't use streams,
+ * thus making it safe to use in interrupt handlers with the RTOS.
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * @Note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Send a char to the PC
+ *
+ * #include "mbed.h"
+ *
+ * RawSerial pc(USBTX, USBRX);
+ *
+ * int main() {
+ *     pc.putc('A');
+ * }
+ * @endcode
+ */
+class RawSerial: public SerialBase {
+
+public:
+    /** Create a RawSerial port, connected to the specified transmit and receive pins
+     *
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *
+     *  @note
+     *    Either tx or rx may be specified as NC if unused
+     */
+    RawSerial(PinName tx, PinName rx);
+
+    /** Write a char to the serial port
+     *
+     * @param c The char to write
+     *
+     * @returns The written char or -1 if an error occured
+     */
+    int putc(int c);
+
+    /** Read a char from the serial port
+     *
+     * @returns The char read from the serial port
+     */
+    int getc();
+
+    /** Write a string to the serial port
+     *
+     * @param str The string to write
+     *
+     * @returns 0 if the write succeeds, EOF for error
+     */
+    int puts(const char *str);
+
+    int printf(const char *format, ...);
+
+protected:
+
+    /** Acquire exclusive access to this serial port
+     */
+    virtual void lock(void);
+
+    /** Release exclusive access to this serial port
+     */
+    virtual void unlock(void);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/SPI.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,262 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_H
+#define MBED_SPI_H
+
+#include "platform.h"
+
+#if DEVICE_SPI
+
+#include "PlatformMutex.h"
+#include "spi_api.h"
+#include "SingletonPtr.h"
+
+#if DEVICE_SPI_ASYNCH
+#include "CThunk.h"
+#include "dma_api.h"
+#include "CircularBuffer.h"
+#include "FunctionPointer.h"
+#include "Transaction.h"
+#endif
+
+namespace mbed {
+
+/** A SPI Master, used for communicating with SPI slave devices
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Most SPI devices will also require Chip Select and Reset signals. These
+ * can be controlled using <DigitalOut> pins
+ *
+ * @Note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Send a byte to a SPI slave, and record the response
+ *
+ * #include "mbed.h"
+ *
+ * // hardware ssel (where applicable)
+ * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * // software ssel
+ * SPI device(p5, p6, p7); // mosi, miso, sclk
+ * DigitalOut cs(p8); // ssel
+ *
+ * int main() {
+ *     // hardware ssel (where applicable)
+ *     //int response = device.write(0xFF);
+ *
+ *     device.lock();
+ *     // software ssel
+ *     cs = 0;
+ *     int response = device.write(0xFF);
+ *     cs = 1;
+ *     device.unlock();
+ *
+ * }
+ * @endcode
+ */
+class SPI {
+
+public:
+
+    /** Create a SPI master connected to the specified pins
+     *
+     *  mosi or miso can be specfied as NC if not used
+     *
+     *  @param mosi SPI Master Out, Slave In pin
+     *  @param miso SPI Master In, Slave Out pin
+     *  @param sclk SPI Clock pin
+     *  @param ssel SPI chip select pin
+     */
+    SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
+
+    /** Configure the data transmission format
+     *
+     *  @param bits Number of bits per SPI frame (4 - 16)
+     *  @param mode Clock polarity and phase mode (0 - 3)
+     *
+     * @code
+     * mode | POL PHA
+     * -----+--------
+     *   0  |  0   0
+     *   1  |  0   1
+     *   2  |  1   0
+     *   3  |  1   1
+     * @endcode
+     */
+    void format(int bits, int mode = 0);
+
+    /** Set the spi bus clock frequency
+     *
+     *  @param hz SCLK frequency in hz (default = 1MHz)
+     */
+    void frequency(int hz = 1000000);
+
+    /** Write to the SPI Slave and return the response
+     *
+     *  @param value Data to be sent to the SPI slave
+     *
+     *  @returns
+     *    Response from the SPI slave
+    */
+    virtual int write(int value);
+
+    /** Acquire exclusive access to this SPI bus
+     */
+    virtual void lock(void);
+
+    /** Release exclusive access to this SPI bus
+     */
+    virtual void unlock(void);
+
+#if DEVICE_SPI_ASYNCH
+
+    /** Start non-blocking SPI transfer using 8bit buffers.
+     *
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify. Look at spi hal header file for SPI events.
+     * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
+     */
+    template<typename Type>
+    int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
+        if (spi_active(&_spi)) {
+            return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
+        }
+        start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
+        return 0;
+    }
+
+    /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
+     */
+    void abort_transfer();
+
+    /** Clear the transaction buffer
+     */
+    void clear_transfer_buffer();
+
+    /** Clear the transaction buffer and abort on-going transfer.
+     */
+    void abort_all_transfers();
+
+    /** Configure DMA usage suggestion for non-blocking transfers
+     *
+     *  @param usage The usage DMA hint for peripheral
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
+    */
+    int set_dma_usage(DMAUsage usage);
+
+protected:
+    /** SPI IRQ handler
+     *
+    */
+    void irq_handler_asynch(void);
+
+    /** Common transfer method
+     *
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param bit_width The buffers element width
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify
+     * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
+    */
+    int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+    /**
+     *
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param bit_width The buffers element width
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify
+     * @return Zero if a transfer was added to the queue, or -1 if the queue is full
+    */
+    int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+    /** Configures a callback, spi peripheral and initiate a new transfer
+     *
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param bit_width The buffers element width
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify
+    */
+    void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+#if TRANSACTION_QUEUE_SIZE_SPI
+
+    /** Start a new transaction
+     *
+     *  @param data Transaction data
+    */
+    void start_transaction(transaction_t *data);
+
+    /** Dequeue a transaction
+     *
+    */
+    void dequeue_transaction();
+    static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
+#endif
+
+#endif
+
+public:
+    virtual ~SPI() {
+    }
+
+protected:
+    spi_t _spi;
+
+#if DEVICE_SPI_ASYNCH
+    CThunk<SPI> _irq;
+    event_callback_t _callback;
+    DMAUsage _usage;
+#endif
+
+    void aquire(void);
+    static SPI *_owner;
+    static SingletonPtr<PlatformMutex> _mutex;
+    int _bits;
+    int _mode;
+    int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/SPISlave.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,125 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPISLAVE_H
+#define MBED_SPISLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_SPISLAVE
+
+#include "spi_api.h"
+
+namespace mbed {
+
+/** A SPI slave, used for communicating with a SPI Master device
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * @Note Synchronization level: Not protected
+ *
+ * Example:
+ * @code
+ * // Reply to a SPI master as slave
+ *
+ * #include "mbed.h"
+ *
+ * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * int main() {
+ *     device.reply(0x00);              // Prime SPI with first reply
+ *     while(1) {
+ *         if(device.receive()) {
+ *             int v = device.read();   // Read byte from master
+ *             v = (v + 1) % 0x100;     // Add one to it, modulo 256
+ *             device.reply(v);         // Make this the next reply
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class SPISlave {
+
+public:
+
+    /** Create a SPI slave connected to the specified pins
+     *
+     *  mosi or miso can be specfied as NC if not used
+     *
+     *  @param mosi SPI Master Out, Slave In pin
+     *  @param miso SPI Master In, Slave Out pin
+     *  @param sclk SPI Clock pin
+     *  @param ssel SPI chip select pin
+     */
+    SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+    /** Configure the data transmission format
+     *
+     *  @param bits Number of bits per SPI frame (4 - 16)
+     *  @param mode Clock polarity and phase mode (0 - 3)
+     *
+     * @code
+     * mode | POL PHA
+     * -----+--------
+     *   0  |  0   0
+     *   1  |  0   1
+     *   2  |  1   0
+     *   3  |  1   1
+     * @endcode
+     */
+    void format(int bits, int mode = 0);
+
+    /** Set the spi bus clock frequency
+     *
+     *  @param hz SCLK frequency in hz (default = 1MHz)
+     */
+    void frequency(int hz = 1000000);
+
+    /** Polls the SPI to see if data has been received
+     *
+     *  @returns
+     *    0 if no data,
+     *    1 otherwise
+     */
+    int receive(void);
+
+    /** Retrieve  data from receive buffer as slave
+     *
+     *  @returns
+     *    the data in the receive buffer
+     */
+    int read(void);
+
+    /** Fill the transmission buffer with the value to be written out
+     *  as slave on the next received message from the master.
+     *
+     *  @param value the data to be transmitted next
+     */
+    void reply(int value);
+
+protected:
+    spi_t _spi;
+
+    int _bits;
+    int _mode;
+    int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/Serial.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_H
+#define MBED_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "SerialBase.h"
+#include "PlatformMutex.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * @Note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * // Print "Hello World" to the PC
+ *
+ * #include "mbed.h"
+ *
+ * Serial pc(USBTX, USBRX);
+ *
+ * int main() {
+ *     pc.printf("Hello World\n");
+ * }
+ * @endcode
+ */
+class Serial : public SerialBase, public Stream {
+
+public:
+#if DEVICE_SERIAL_ASYNCH
+    using SerialBase::read;
+    using SerialBase::write;
+#endif
+
+    /** Create a Serial port, connected to the specified transmit and receive pins
+     *
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *
+     *  @note
+     *    Either tx or rx may be specified as NC if unused
+     */
+    Serial(PinName tx, PinName rx, const char *name=NULL);
+
+protected:
+    virtual int _getc();
+    virtual int _putc(int c);
+    virtual void lock();
+    virtual void unlock();
+
+    PlatformMutex _mutex;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/SerialBase.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,244 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIALBASE_H
+#define MBED_SERIALBASE_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "Callback.h"
+#include "serial_api.h"
+
+#if DEVICE_SERIAL_ASYNCH
+#include "CThunk.h"
+#include "dma_api.h"
+#endif
+
+namespace mbed {
+
+/** A base class for serial port implementations
+ * Can't be instantiated directly (use Serial or RawSerial)
+ *
+ * @Note Synchronization level: Set by subclass
+ */
+class SerialBase {
+
+public:
+    /** Set the baud rate of the serial port
+     *
+     *  @param baudrate The baudrate of the serial port (default = 9600).
+     */
+    void baud(int baudrate);
+
+    enum Parity {
+        None = 0,
+        Odd,
+        Even,
+        Forced1,
+        Forced0
+    };
+
+    enum IrqType {
+        RxIrq = 0,
+        TxIrq
+    };
+
+    enum Flow {
+        Disabled = 0,
+        RTS,
+        CTS,
+        RTSCTS
+    };
+
+    /** Set the transmission format used by the serial port
+     *
+     *  @param bits The number of bits in a word (5-8; default = 8)
+     *  @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
+     *  @param stop The number of stop bits (1 or 2; default = 1)
+     */
+    void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
+
+    /** Determine if there is a character available to read
+     *
+     *  @returns
+     *    1 if there is a character available to read,
+     *    0 otherwise
+     */
+    int readable();
+
+    /** Determine if there is space available to write a character
+     *
+     *  @returns
+     *    1 if there is space to write a character,
+     *    0 otherwise
+     */
+    int writeable();
+
+    /** Attach a function to call whenever a serial interrupt is generated
+     *
+     *  @param func A pointer to a void function, or 0 to set as none
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    void attach(Callback<void()> func, IrqType type=RxIrq);
+
+    /** Attach a member function to call whenever a serial interrupt is generated
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    template<typename T>
+    void attach(T *obj, void (T::*method)(), IrqType type=RxIrq) {
+        attach(Callback<void()>(obj, method), type);
+    }
+
+    /** Attach a member function to call whenever a serial interrupt is generated
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    template<typename T>
+    void attach(T *obj, void (*method)(T*), IrqType type=RxIrq) {
+        attach(Callback<void()>(obj, method), type);
+    }
+
+    /** Generate a break condition on the serial line
+     */
+    void send_break();
+
+protected:
+
+    /** Acquire exclusive access to this serial port
+     */
+    virtual void lock(void);
+
+    /** Release exclusive access to this serial port
+     */
+    virtual void unlock(void);
+
+public:
+
+#if DEVICE_SERIAL_FC
+    /** Set the flow control type on the serial port
+     *
+     *  @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
+     *  @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
+     *  @param flow2 the second flow control pin (CTS for RTSCTS)
+     */
+    void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
+#endif
+
+    static void _irq_handler(uint32_t id, SerialIrq irq_type);
+
+#if DEVICE_SERIAL_ASYNCH
+
+    /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
+     *
+     *  @param buffer   The buffer where received data will be stored
+     *  @param length   The buffer length in bytes
+     *  @param callback The event callback function
+     *  @param event    The logical OR of TX events
+     */
+    int write(const uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+    /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
+     *
+     *  @param buffer   The buffer where received data will be stored
+     *  @param length   The buffer length in bytes
+     *  @param callback The event callback function
+     *  @param event    The logical OR of TX events
+     */
+    int write(const uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+    /** Abort the on-going write transfer
+     */
+    void abort_write();
+
+    /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
+     *
+     *  @param buffer     The buffer where received data will be stored
+     *  @param length     The buffer length in bytes
+     *  @param callback   The event callback function
+     *  @param event      The logical OR of RX events
+     *  @param char_match The matching character
+     */
+    int read(uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+    /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
+     *
+     *  @param buffer     The buffer where received data will be stored
+     *  @param length     The buffer length in bytes
+     *  @param callback   The event callback function
+     *  @param event      The logical OR of RX events
+     *  @param char_match The matching character
+     */
+    int read(uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+    /** Abort the on-going read transfer
+     */
+    void abort_read();
+
+    /** Configure DMA usage suggestion for non-blocking TX transfers
+     *
+     *  @param usage The usage DMA hint for peripheral
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
+     */
+    int set_dma_usage_tx(DMAUsage usage);
+
+    /** Configure DMA usage suggestion for non-blocking RX transfers
+     *
+     *  @param usage The usage DMA hint for peripheral
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
+     */
+    int set_dma_usage_rx(DMAUsage usage);
+
+protected:
+    void start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match);
+    void start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event);
+    void interrupt_handler_asynch(void);
+#endif
+
+protected:
+    SerialBase(PinName tx, PinName rx);
+    virtual ~SerialBase() {
+    }
+
+    int _base_getc();
+    int _base_putc(int c);
+
+#if DEVICE_SERIAL_ASYNCH
+    CThunk<SerialBase> _thunk_irq;
+    event_callback_t _tx_callback;
+    event_callback_t _rx_callback;
+    DMAUsage _tx_usage;
+    DMAUsage _rx_usage;
+#endif
+
+    serial_t         _serial;
+    Callback<void()> _irq[2];
+    int              _baud;
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/SingletonPtr.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef SINGLETONPTR_H
+#define SINGLETONPTR_H
+
+#include <stdint.h>
+#include <new>
+#include "mbed_assert.h"
+#ifdef MBED_CONF_RTOS_PRESENT
+#include "cmsis_os.h"
+#endif
+
+#ifdef MBED_CONF_RTOS_PRESENT
+extern osMutexId singleton_mutex_id;
+#endif
+
+/** Lock the singleton mutex
+ *
+ * This function is typically used to provide
+ * exclusive access when initializing a
+ * global object.
+ */
+inline static void singleton_lock(void)
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+    osMutexWait(singleton_mutex_id, osWaitForever);
+#endif
+}
+
+/** Unlock the singleton mutex
+ *
+ * This function is typically used to provide
+ * exclusive access when initializing a
+ * global object.
+ */
+inline static void singleton_unlock(void)
+{
+#ifdef MBED_CONF_RTOS_PRESENT
+    osMutexRelease (singleton_mutex_id);
+#endif
+}
+
+/** Utility class for creating an using a singleton
+ *
+ * @Note Synchronization level: Thread safe
+ *
+ * @Note: This class must only be used in a static context -
+ * this class must never be allocated or created on the
+ * stack.
+ *
+ * @Note: This class is lazily initialized on first use.
+ * This class is a POD type so if it is not used it will
+ * be garbage collected.
+ */
+template <class T>
+struct SingletonPtr {
+
+    /** Get a pointer to the underlying singleton
+     *
+     * @returns
+     *   A pointer to the singleton
+     */
+    T* get() {
+        if (NULL == _ptr) {
+            singleton_lock();
+            if (NULL == _ptr) {
+                _ptr = new (_data) T();
+            }
+            singleton_unlock();
+        }
+        // _ptr was not zero initialized or was
+        // corrupted if this assert is hit
+        MBED_ASSERT(_ptr == (T *)&_data);
+        return _ptr;
+    }
+
+    /** Get a pointer to the underlying singleton
+     *
+     * @returns
+     *   A pointer to the singleton
+     */
+    T* operator->() {
+        return get();
+    }
+
+    // This is zero initialized when in global scope
+    T *_ptr;
+    // Force data to be 4 byte aligned
+    uint32_t _data[(sizeof(T) + sizeof(uint32_t) - 1) / sizeof(uint32_t)];
+};
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/Stream.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STREAM_H
+#define MBED_STREAM_H
+
+#include "platform.h"
+#include "FileLike.h"
+#include <cstdarg>
+
+namespace mbed {
+
+extern void mbed_set_unbuffered_stream(FILE *_file);
+extern int mbed_getc(FILE *_file);
+extern char* mbed_gets(char *s, int size, FILE *_file);
+
+/** File stream
+ *
+ * @Note Synchronization level: Set by subclass
+ */
+class Stream : public FileLike {
+
+public:
+    Stream(const char *name=NULL);
+    virtual ~Stream();
+
+    int putc(int c);
+    int puts(const char *s);
+    int getc();
+    char *gets(char *s, int size);
+    int printf(const char* format, ...);
+    int scanf(const char* format, ...);
+    int vprintf(const char* format, std::va_list args);
+    int vscanf(const char* format, std::va_list args);
+
+    operator std::FILE*() {return _file;}
+
+protected:
+    virtual int close();
+    virtual ssize_t write(const void* buffer, size_t length);
+    virtual ssize_t read(void* buffer, size_t length);
+    virtual off_t lseek(off_t offset, int whence);
+    virtual int isatty();
+    virtual int fsync();
+    virtual off_t flen();
+
+    virtual int _putc(int c) = 0;
+    virtual int _getc() = 0;
+
+    std::FILE *_file;
+
+    /* disallow copy constructor and assignment operators */
+private:
+    Stream(const Stream&);
+    Stream & operator = (const Stream&);
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/Ticker.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,130 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_H
+#define MBED_TICKER_H
+
+#include "TimerEvent.h"
+#include "Callback.h"
+
+namespace mbed {
+
+/** A Ticker is used to call a function at a recurring interval
+ *
+ *  You can use as many seperate Ticker objects as you require.
+ *
+ * @Note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Toggle the blinking led after 5 seconds
+ *
+ * #include "mbed.h"
+ *
+ * Ticker timer;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * int flip = 0;
+ *
+ * void attime() {
+ *     flip = !flip;
+ * }
+ *
+ * int main() {
+ *     timer.attach(&attime, 5);
+ *     while(1) {
+ *         if(flip == 0) {
+ *             led1 = !led1;
+ *         } else {
+ *             led2 = !led2;
+ *         }
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class Ticker : public TimerEvent {
+
+public:
+    Ticker() : TimerEvent() {
+    }
+
+    Ticker(const ticker_data_t *data) : TimerEvent(data) {
+        data->interface->init();
+    }
+
+    /** Attach a function to be called by the Ticker, specifiying the interval in seconds
+     *
+     *  @param func pointer to the function to be called
+     *  @param t the time between calls in seconds
+     */
+    void attach(Callback<void()> func, float t) {
+        attach_us(func, t * 1000000.0f);
+    }
+
+    /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
+     *
+     *  @param obj pointer to the object to call the member function on
+     *  @param method pointer to the member function to be called
+     *  @param t the time between calls in seconds
+     */
+    template<typename T, typename M>
+    void attach(T *obj, M method, float t) {
+        attach(Callback<void()>(obj, method), t);
+    }
+
+    /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
+     *
+     *  @param fptr pointer to the function to be called
+     *  @param t the time between calls in micro-seconds
+     */
+    void attach_us(Callback<void()> func, timestamp_t t) {
+        _function.attach(func);
+        setup(t);
+    }
+
+    /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *  @param t the time between calls in micro-seconds
+     */
+    template<typename T, typename M>
+    void attach_us(T *obj, M method, timestamp_t t) {
+        attach_us(Callback<void()>(obj, method), t);
+    }
+
+    virtual ~Ticker() {
+        detach();
+    }
+
+    /** Detach the function
+     */
+    void detach();
+
+protected:
+    void setup(timestamp_t t);
+    virtual void handler();
+
+protected:
+    timestamp_t         _delay;     /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
+    Callback<void()>    _function;  /**< Callback. */
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/Timeout.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEOUT_H
+#define MBED_TIMEOUT_H
+
+#include "Ticker.h"
+
+namespace mbed {
+
+/** A Timeout is used to call a function at a point in the future
+ *
+ * You can use as many seperate Timeout objects as you require.
+ *
+ * @Note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Blink until timeout.
+ *
+ * #include "mbed.h"
+ *
+ * Timeout timeout;
+ * DigitalOut led(LED1);
+ *
+ * int on = 1;
+ *
+ * void attimeout() {
+ *     on = 0;
+ * }
+ *
+ * int main() {
+ *     timeout.attach(&attimeout, 5);
+ *     while(on) {
+ *         led = !led;
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class Timeout : public Ticker {
+
+protected:
+    virtual void handler();
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/Timer.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMER_H
+#define MBED_TIMER_H
+
+#include "platform.h"
+#include "ticker_api.h"
+
+namespace mbed {
+
+/** A general purpose timer
+ *
+ * @Note Synchronization level: Interrupt safe
+ *
+ * Example:
+ * @code
+ * // Count the time to toggle a LED
+ *
+ * #include "mbed.h"
+ *
+ * Timer timer;
+ * DigitalOut led(LED1);
+ * int begin, end;
+ *
+ * int main() {
+ *     timer.start();
+ *     begin = timer.read_us();
+ *     led = !led;
+ *     end = timer.read_us();
+ *     printf("Toggle the led takes %d us", end - begin);
+ * }
+ * @endcode
+ */
+class Timer {
+
+public:
+    Timer();
+    Timer(const ticker_data_t *data);
+
+    /** Start the timer
+     */
+    void start();
+
+    /** Stop the timer
+     */
+    void stop();
+
+    /** Reset the timer to 0.
+     *
+     * If it was already counting, it will continue
+     */
+    void reset();
+
+    /** Get the time passed in seconds
+     */
+    float read();
+
+    /** Get the time passed in mili-seconds
+     */
+    int read_ms();
+
+    /** Get the time passed in micro-seconds
+     */
+    int read_us();
+
+    /** An operator shorthand for read()
+     */
+    operator float();
+
+protected:
+    int slicetime();
+    int _running;          // whether the timer is running
+    unsigned int _start;   // the start time of the latest slice
+    int _time;             // any accumulated time from previous slices
+    const ticker_data_t *_ticker_data;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/TimerEvent.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEREVENT_H
+#define MBED_TIMEREVENT_H
+
+#include "ticker_api.h"
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+/** Base abstraction for timer interrupts
+ *
+ * @Note Synchronization level: Interrupt safe
+ */
+class TimerEvent {
+public:
+    TimerEvent();
+    TimerEvent(const ticker_data_t *data);
+
+    /** The handler registered with the underlying timer interrupt
+     */
+    static void irq(uint32_t id);
+
+    /** Destruction removes it...
+     */
+    virtual ~TimerEvent();
+
+protected:
+    // The handler called to service the timer event of the derived class
+    virtual void handler() = 0;
+
+    // insert in to linked list
+    void insert(timestamp_t timestamp);
+
+    // remove from linked list, if in it
+    void remove();
+
+    ticker_event_t event;
+
+    const ticker_data_t *_ticker_data;
+};
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/Transaction.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,76 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TRANSACTION_H
+#define MBED_TRANSACTION_H
+
+#include "platform.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** Transaction structure
+ */
+typedef struct {
+    void *tx_buffer;           /**< Tx buffer */
+    size_t tx_length;          /**< Length of Tx buffer*/
+    void *rx_buffer;           /**< Rx buffer */
+    size_t rx_length;          /**< Length of Rx buffer */
+    uint32_t event;            /**< Event for a transaction */
+    event_callback_t callback; /**< User's callback */
+    uint8_t width;             /**< Buffer's word width (8, 16, 32, 64) */
+} transaction_t;
+
+/** Transaction class defines a transaction.
+ *
+ * @Note Synchronization level: Not protected
+ */
+template<typename Class>
+class Transaction {
+public:
+    Transaction(Class *tpointer, const transaction_t& transaction) : _obj(tpointer), _data(transaction) {
+    }
+
+    Transaction() : _obj(), _data() {
+    }
+
+    ~Transaction() {
+    }
+
+    /** Get object's instance for the transaction
+     *
+     * @return The object which was stored
+     */
+    Class* get_object() {
+        return _obj;
+    }
+
+    /** Get the transaction
+     *
+     * @return The transaction which was stored
+     */
+    transaction_t* get_transaction() {
+        return &_data;
+    }
+
+private:
+    Class* _obj;
+    transaction_t _data;
+};
+
+}
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/can_helper.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_HELPER_H
+#define MBED_CAN_HELPER_H
+
+#if DEVICE_CAN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum CANFormat {
+    CANStandard = 0,
+    CANExtended = 1,
+    CANAny = 2
+};
+typedef enum CANFormat CANFormat;
+
+enum CANType {
+    CANData   = 0,
+    CANRemote = 1
+};
+typedef enum CANType CANType;
+
+struct CAN_Message {
+    unsigned int   id;                 // 29 bit identifier
+    unsigned char  data[8];            // Data field
+    unsigned char  len;                // Length of data field in bytes
+    CANFormat      format;             // 0 - STANDARD, 1- EXTENDED IDENTIFIER
+    CANType        type;               // 0 - DATA FRAME, 1 - REMOTE FRAME
+};
+typedef struct CAN_Message CAN_Message;
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+
+#endif // MBED_CAN_HELPER_H
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/critical.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,355 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MBED_UTIL_CRITICAL_H__
+#define __MBED_UTIL_CRITICAL_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** Determine the current interrupts enabled state
+  *
+  * This function can be called to determine whether or not interrupts are currently enabled.
+  * \note
+  * NOTE:
+  * This function works for both cortex-A and cortex-M, although the underlyng implementation
+  * differs.
+  * @return true if interrupts are enabled, false otherwise
+  */
+bool core_util_are_interrupts_enabled(void);
+
+/** Mark the start of a critical section
+  *
+  * This function should be called to mark the start of a critical section of code.
+  * \note
+  * NOTES:
+  * 1) The use of this style of critical section is targetted at C based implementations.
+  * 2) These critical sections can be nested.
+  * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
+  *    section) will be preserved on exit from the section.
+  * 4) This implementation will currently only work on code running in privileged mode.
+  */
+void core_util_critical_section_enter(void);
+
+/** Mark the end of a critical section
+  *
+  * This function should be called to mark the end of a critical section of code.
+  * \note
+  * NOTES:
+  * 1) The use of this style of critical section is targetted at C based implementations.
+  * 2) These critical sections can be nested.
+  * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
+  *    section) will be preserved on exit from the section.
+  * 4) This implementation will currently only work on code running in privileged mode.
+  */
+void core_util_critical_section_exit(void);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param  ptr                  The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ *                              expected current value of the data being set atomically.
+ *                              The computed 'desiredValue' should be a function of this current value.
+ *                              @Note: This is an in-out parameter. In the
+ *                              failure case of atomic_cas (where the
+ *                              destination isn't set), the pointee of expectedCurrentValue is
+ *                              updated with the current value.
+ * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return                      true if the memory location was atomically
+ *                              updated with the desired value (after verifying
+ *                              that it contained the expectedCurrentValue),
+ *                              false otherwise. In the failure case,
+ *                              exepctedCurrentValue is updated with the new
+ *                              value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ *     if *p != *old {
+ *         *old = *p
+ *         return false
+ *     }
+ *     *p = new
+ *     return true
+ * }
+ *
+ * @Note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ *     done = false
+ *     value = *p // This fetch operation need not be atomic.
+ *     while not done {
+ *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ *     }
+ *     return value + a
+ * }
+ */
+bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param  ptr                  The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ *                              expected current value of the data being set atomically.
+ *                              The computed 'desiredValue' should be a function of this current value.
+ *                              @Note: This is an in-out parameter. In the
+ *                              failure case of atomic_cas (where the
+ *                              destination isn't set), the pointee of expectedCurrentValue is
+ *                              updated with the current value.
+ * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return                      true if the memory location was atomically
+ *                              updated with the desired value (after verifying
+ *                              that it contained the expectedCurrentValue),
+ *                              false otherwise. In the failure case,
+ *                              exepctedCurrentValue is updated with the new
+ *                              value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ *     if *p != *old {
+ *         *old = *p
+ *         return false
+ *     }
+ *     *p = new
+ *     return true
+ * }
+ *
+ * @Note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ *     done = false
+ *     value = *p // This fetch operation need not be atomic.
+ *     while not done {
+ *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ *     }
+ *     return value + a
+ * }
+ */
+bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param  ptr                  The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ *                              expected current value of the data being set atomically.
+ *                              The computed 'desiredValue' should be a function of this current value.
+ *                              @Note: This is an in-out parameter. In the
+ *                              failure case of atomic_cas (where the
+ *                              destination isn't set), the pointee of expectedCurrentValue is
+ *                              updated with the current value.
+ * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return                      true if the memory location was atomically
+ *                              updated with the desired value (after verifying
+ *                              that it contained the expectedCurrentValue),
+ *                              false otherwise. In the failure case,
+ *                              exepctedCurrentValue is updated with the new
+ *                              value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ *     if *p != *old {
+ *         *old = *p
+ *         return false
+ *     }
+ *     *p = new
+ *     return true
+ * }
+ *
+ * @Note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ *     done = false
+ *     value = *p // This fetch operation need not be atomic.
+ *     while not done {
+ *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ *     }
+ *     return value + a
+ * }
+ */
+bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
+
+/**
+ * Atomic compare and set. It compares the contents of a memory location to a
+ * given value and, only if they are the same, modifies the contents of that
+ * memory location to a given new value. This is done as a single atomic
+ * operation. The atomicity guarantees that the new value is calculated based on
+ * up-to-date information; if the value had been updated by another thread in
+ * the meantime, the write would fail due to a mismatched expectedCurrentValue.
+ *
+ * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
+ * you to the article on compare-and swap].
+ *
+ * @param  ptr                  The target memory location.
+ * @param[in,out] expectedCurrentValue A pointer to some location holding the
+ *                              expected current value of the data being set atomically.
+ *                              The computed 'desiredValue' should be a function of this current value.
+ *                              @Note: This is an in-out parameter. In the
+ *                              failure case of atomic_cas (where the
+ *                              destination isn't set), the pointee of expectedCurrentValue is
+ *                              updated with the current value.
+ * @param[in] desiredValue      The new value computed based on '*expectedCurrentValue'.
+ *
+ * @return                      true if the memory location was atomically
+ *                              updated with the desired value (after verifying
+ *                              that it contained the expectedCurrentValue),
+ *                              false otherwise. In the failure case,
+ *                              exepctedCurrentValue is updated with the new
+ *                              value of the target memory location.
+ *
+ * pseudocode:
+ * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
+ *     if *p != *old {
+ *         *old = *p
+ *         return false
+ *     }
+ *     *p = new
+ *     return true
+ * }
+ *
+ * @Note: In the failure case (where the destination isn't set), the value
+ * pointed to by expectedCurrentValue is still updated with the current value.
+ * This property helps writing concise code for the following incr:
+ *
+ * function incr(p : pointer to int, a : int) returns int {
+ *     done = false
+ *     value = *p // This fetch operation need not be atomic.
+ *     while not done {
+ *         done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
+ *     }
+ *     return value + a
+ * }
+ */
+bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue);
+
+/**
+ * Atomic increment.
+ * @param  valuePtr Target memory location being incremented.
+ * @param  delta    The amount being incremented.
+ * @return          The new incremented value.
+ */
+uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta);
+
+/**
+ * Atomic increment.
+ * @param  valuePtr Target memory location being incremented.
+ * @param  delta    The amount being incremented.
+ * @return          The new incremented value.
+ */
+uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta);
+
+/**
+ * Atomic increment.
+ * @param  valuePtr Target memory location being incremented.
+ * @param  delta    The amount being incremented.
+ * @return          The new incremented value.
+ */
+uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta);
+
+/**
+ * Atomic increment.
+ * @param  valuePtr Target memory location being incremented.
+ * @param  delta    The amount being incremented in bytes.
+ * @return          The new incremented value.
+ *
+ * @note The type of the pointer argument is not taken into account
+ *       and the pointer is incremented by bytes.
+ */
+void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta);
+
+/**
+ * Atomic decrement.
+ * @param  valuePtr Target memory location being decremented.
+ * @param  delta    The amount being decremented.
+ * @return          The new decremented value.
+ */
+uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta);
+
+/**
+ * Atomic decrement.
+ * @param  valuePtr Target memory location being decremented.
+ * @param  delta    The amount being decremented.
+ * @return          The new decremented value.
+ */
+uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta);
+
+/**
+ * Atomic decrement.
+ * @param  valuePtr Target memory location being decremented.
+ * @param  delta    The amount being decremented.
+ * @return          The new decremented value.
+ */
+uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta);
+
+/**
+ * Atomic decrement.
+ * @param  valuePtr Target memory location being decremented.
+ * @param  delta    The amount being decremented in bytes.
+ * @return          The new decremented value.
+ *
+ * @note The type of the pointer argument is not taken into account
+ *       and the pointer is decremented by bytes
+ */
+void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+
+#endif // __MBED_UTIL_CRITICAL_H__
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/mbed.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,84 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_H
+#define MBED_H
+
+#define MBED_LIBRARY_VERSION 123
+
+#if MBED_CONF_RTOS_PRESENT
+#include "rtos/rtos.h"
+#endif
+
+#if MBED_CONF_NSAPI_PRESENT
+#include "network-socket/nsapi.h"
+#endif
+
+#include "toolchain.h"
+#include "platform.h"
+
+// Useful C libraries
+#include <math.h>
+#include <time.h>
+
+// mbed Debug libraries
+#include "mbed_error.h"
+#include "mbed_interface.h"
+#include "mbed_assert.h"
+
+// mbed Peripheral components
+#include "DigitalIn.h"
+#include "DigitalOut.h"
+#include "DigitalInOut.h"
+#include "BusIn.h"
+#include "BusOut.h"
+#include "BusInOut.h"
+#include "PortIn.h"
+#include "PortInOut.h"
+#include "PortOut.h"
+#include "AnalogIn.h"
+#include "AnalogOut.h"
+#include "PwmOut.h"
+#include "Serial.h"
+#include "SPI.h"
+#include "SPISlave.h"
+#include "I2C.h"
+#include "I2CSlave.h"
+#include "Ethernet.h"
+#include "CAN.h"
+#include "RawSerial.h"
+
+// mbed Internal components
+#include "Timer.h"
+#include "Ticker.h"
+#include "Timeout.h"
+#include "LowPowerTimeout.h"
+#include "LowPowerTicker.h"
+#include "LowPowerTimer.h"
+#include "LocalFileSystem.h"
+#include "InterruptIn.h"
+#include "wait_api.h"
+#include "sleep_api.h"
+#include "rtc_time.h"
+
+// mbed Non-hardware components
+#include "Callback.h"
+#include "FunctionPointer.h"
+
+using namespace mbed;
+using namespace std;
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/mbed_assert.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,50 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ASSERT_H
+#define MBED_ASSERT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
+ *  This function is active only if NDEBUG is not defined prior to including this
+ *  assert header file.
+ *  In case of MBED_ASSERT failing condition, error() is called with the assertation message.
+ *  @param expr Expresion to be checked.
+ *  @param file File where assertation failed.
+ *  @param line Failing assertation line number.
+ */
+void mbed_assert_internal(const char *expr, const char *file, int line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifdef NDEBUG
+#define MBED_ASSERT(expr) ((void)0)
+
+#else
+#define MBED_ASSERT(expr)                                \
+do {                                                     \
+    if (!(expr)) {                                       \
+        mbed_assert_internal(#expr, __FILE__, __LINE__); \
+    }                                                    \
+} while (0)
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/mbed_debug.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEBUG_H
+#define MBED_DEBUG_H
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#include <stdarg.h>
+
+/** Output a debug message
+ *
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug(const char *format, ...) {
+    va_list args;
+    va_start(args, format);
+    vfprintf(stderr, format, args);
+    va_end(args);
+}
+
+/** Conditionally output a debug message
+ *
+ * NOTE: If the condition is constant false (!= 1) and the compiler optimization
+ * level is greater than 0, then the whole function will be compiled away.
+ *
+ * @param condition output only if condition is true (== 1)
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug_if(int condition, const char *format, ...) {
+    if (condition == 1) {
+        va_list args;
+        va_start(args, format);
+        vfprintf(stderr, format, args);
+        va_end(args);
+    }
+}
+
+#else
+static inline void debug(const char *format, ...) {}
+static inline void debug_if(int condition, const char *format, ...) {}
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/mbed_error.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ERROR_H
+#define MBED_ERROR_H
+
+/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
+ *
+ * @code
+ * #error "That shouldn't have happened!"
+ * @endcode
+ *
+ * If the compiler evaluates this line, it will report the error and stop the compile.
+ *
+ * For example, you could use this to check some user-defined compile-time variables:
+ *
+ * @code
+ * #define NUM_PORTS 7
+ * #if (NUM_PORTS > 4)
+ *     #error "NUM_PORTS must be less than 4"
+ * #endif
+ * @endcode
+ *
+ * Reporting Run-Time Errors:
+ * To generate a fatal run-time error, you can use the mbed error() function.
+ *
+ * @code
+ * error("That shouldn't have happened!");
+ * @endcode
+ *
+ * If the mbed running the program executes this function, it will print the
+ * message via the USB serial port, and then die with the blue lights of death!
+ *
+ * The message can use printf-style formatting, so you can report variables in the
+ * message too. For example, you could use this to check a run-time condition:
+ *
+ * @code
+ * if(x >= 5) {
+ *     error("expected x to be less than 5, but got %d", x);
+ * }
+ * #endcode
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void error(const char* format, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/mbed_interface.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,131 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERFACE_H
+#define MBED_INTERFACE_H
+
+#include <stdarg.h>
+
+#include "device.h"
+
+/* Mbed interface mac address
+ * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
+ * otherwise MAC_ADD_x are used.
+ */
+#define MBED_MAC_ADDR_INTERFACE 0x00
+#define MBED_MAC_ADDR_0  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_1  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_2  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_3  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_4  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_5  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+/** Functions to control the mbed interface
+ *
+ * mbed Microcontrollers have a built-in interface to provide functionality such as
+ * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
+ * system. These functions provide means to control the interface suing semihost
+ * calls it supports.
+ */
+
+/** Determine whether the mbed interface is connected, based on whether debug is enabled
+ *
+ *  @returns
+ *    1 if interface is connected,
+ *    0 otherwise
+ */
+int mbed_interface_connected(void);
+
+/** Instruct the mbed interface to reset, as if the reset button had been pressed
+ *
+ *  @returns
+ *    1 if successful,
+ *    0 otherwise (e.g. interface not present)
+ */
+int mbed_interface_reset(void);
+
+/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
+ * The interface will still support the USB serial aspect
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_disconnect(void);
+
+/** This will disconnect the debug aspect of the interface, and if the USB cable is not
+ * connected, also power down the interface. If the USB cable is connected, the interface
+ * will remain powered up and visible to the host
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_powerdown(void);
+
+/** This returns a string containing the 32-character UID of the mbed interface
+ *  This is a weak function that can be overwritten if required
+ *
+ *  @param uid A 33-byte array to write the null terminated 32-byte string
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_uid(char *uid);
+
+#endif
+
+/** This returns a unique 6-byte MAC address, based on the interface UID
+ * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
+ *
+ * This is a weak function that can be overwritten if you want to provide your own mechanism to
+ * provide a MAC address.
+ *
+ *  @param mac A 6-byte array to write the MAC address
+ */
+void mbed_mac_address(char *mac);
+
+/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
+ */
+void mbed_die(void);
+
+/** Print out an error message.  This is typically called when
+ * hanlding a crash.
+ *
+ * @Note Synchronization level: Interrupt safe
+ */
+void mbed_error_printf(const char* format, ...);
+
+/** Print out an error message.  Similar to mbed_error_printf
+ * but uses a va_list.
+ *
+ * @Note Synchronization level: Interrupt safe
+ */
+void mbed_error_vfprintf(const char * format, va_list arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/mbed_mem_trace.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MBED_MEM_TRACE_H__
+#define __MBED_MEM_TRACE_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/* Operation types for tracer */
+enum {
+    MBED_MEM_TRACE_MALLOC,
+    MBED_MEM_TRACE_REALLOC,
+    MBED_MEM_TRACE_CALLOC,
+    MBED_MEM_TRACE_FREE
+};
+
+/* Prefix for the output of the default tracer */
+#define MBED_MEM_DEFAULT_TRACER_PREFIX  "#"
+
+/**
+ * Type of the callback used by the memory tracer. This callback is called when a memory
+ * allocation operation (malloc, realloc, calloc, free) is called and tracing is enabled
+ * for that memory allocation function.
+ *
+ * @param op the ID of the operation (MBED_MEM_TRACE_MALLOC, MBED_MEM_TRACE_REALLOC,
+ *           MBED_MEM_TRACE_CALLOC or MBED_MEM_TRACE_FREE).
+ * @param res the result that the memory operation returned (NULL for 'free').
+ * @param caller the caller of the memory operation. Note that the value of 'caller' might be
+ *               unreliable.
+ *
+ * The rest of the parameters passed 'mbed_mem_trace_cb_t' are the same as the memory operations
+ * that triggered its call (see 'man malloc' for details):
+ *
+ * - for malloc: cb(MBED_MEM_TRACE_MALLOC, res, caller, size).
+ * - for realloc: cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size).
+ * - for calloc: cb(MBED_MEM_TRACE_CALLOC, res, caller, nmemb, size).
+ * - for free: cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr).
+ */
+typedef void (*mbed_mem_trace_cb_t)(uint8_t op, void *res, void* caller, ...);
+
+/**
+ * Set the callback used by the memory tracer (use NULL for disable tracing).
+ *
+ * @param cb the callback to call on each memory operation.
+ */
+void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb);
+
+/**
+ * Trace a call to 'malloc'.
+ * @param res the result of running 'malloc'.
+ * @param size the 'size' argument given to 'malloc'.
+ * @param caller the caller of the memory operation.
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_malloc(void *res, size_t size, void *caller);
+
+/**
+ * Trace a call to 'realloc'.
+ * @param res the result of running 'realloc'.
+ * @param ptr the 'ptr' argument given to 'realloc'.
+ * @param size the 'size' argument given to 'realloc'.
+ *
+ * @return 'res' (the first argument).
+ */
+void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller);
+
+/**
+ * Trace a call to 'calloc'.
+ * @param res the result of running 'calloc'.
+ * @param nmemb the 'nmemb' argument given to 'calloc'.
+ * @param size the 'size' argument given to 'calloc'.
+ * @param caller the caller of the memory operation.
+ * @Return 'res' (the first argument).
+ */
+void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller);
+
+/**
+ * Trace a call to 'free'.
+ * @param ptr the 'ptr' argument given to 'free'.
+ * @param caller the caller of the memory operation.
+ */
+void mbed_mem_trace_free(void *ptr, void *caller);
+
+/**
+ * Default memory trace callback. DO NOT CALL DIRECTLY. It is meant to be used
+ * as the second argument of 'mbed_mem_trace_setup'.
+ *
+ * The default callback outputs trace data using 'printf', in a format that's
+ * easily parsable by an external tool. For each memory operation, the callback
+ * outputs a line that begins with '#<op>:<0xresult>;<0xcaller>-':
+ *
+ * - 'op' identifies the memory operation ('m' for 'malloc', 'r' for 'realloc',
+ *   'c' for 'calloc' and 'f' for 'free').
+ * - 'result' (base 16) is the result of the memor operation. This is always NULL
+ *   for 'free', since 'free' doesn't return anything.
+ * -'caller' (base 16) is the caller of the memory operation. Note that the value
+ *   of 'caller' might be unreliable.
+ *
+ * The rest of the output depends on the operation being traced:
+ *
+ * - for 'malloc': 'size', where 'size' is the original argument to 'malloc'.
+ * - for 'realloc': '0xptr;size', where 'ptr' (base 16) and 'size' are the original arguments to 'realloc'.
+ * - for 'calloc': 'nmemb;size', where 'nmemb' and 'size' are the original arguments to 'calloc'.
+ * - for 'free': '0xptr', where 'ptr' (base 16) is the original argument to 'free'.
+ *
+ * Examples:
+ *
+ * - '#m:0x20003240;0x600d-50' encodes a 'malloc' that returned 0x20003240, was called
+ *   by the instruction at 0x600D with a the 'size' argument equal to 50.
+ * - '#f:0x0;0x602f-0x20003240' encodes a 'free' that was called by the instruction at
+ *   0x602f with the 'ptr' argument equal to 0x20003240.
+ */
+void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif// #ifndef __MBED_MEM_TRACE_H__
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/mbed_stats.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2016-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STATS_H
+#define MBED_STATS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    uint32_t current_size;      /**< Bytes allocated currently. */
+    uint32_t max_size;          /**< Max bytes allocated at a given time. */
+    uint32_t total_size;        /**< Cumulative sum of bytes ever allocated. */
+    uint32_t alloc_cnt;         /**< Current number of allocations. */
+    uint32_t alloc_fail_cnt;    /**< Number of failed allocations. */
+} mbed_stats_heap_t;
+
+/**
+ * Fill the passed in structure with heap stats.
+ */
+void mbed_stats_heap_get(mbed_stats_heap_t *stats);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/platform.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,29 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PLATFORM_H
+#define MBED_PLATFORM_H
+
+#include "device.h"
+#include "PinNames.h"
+#include "PeripheralNames.h"
+
+#include <cstddef>
+#include <cstdlib>
+#include <cstdio>
+#include <cstring>
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/rtc_time.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,88 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Implementation of the C time.h functions
+ *
+ * Provides mechanisms to set and read the current time, based
+ * on the microcontroller Real-Time Clock (RTC), plus some
+ * standard C manipulation and formating functions.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ *     set_time(1256729737);  // Set RTC time to Wed, 28 Oct 2009 11:35:37
+ *
+ *     while(1) {
+ *         time_t seconds = time(NULL);
+ *
+ *         printf("Time as seconds since January 1, 1970 = %d\n", seconds);
+ *
+ *         printf("Time as a basic string = %s", ctime(&seconds));
+ *
+ *         char buffer[32];
+ *         strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
+ *         printf("Time as a custom formatted string = %s", buffer);
+ *
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+
+/** Set the current time
+ *
+ * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
+ * to the time represented by the number of seconds since January 1, 1970
+ * (the UNIX timestamp).
+ *
+ * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
+ *
+ * @Note Synchronization level: Thread safe
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ *     set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
+ * }
+ * @endcode
+ */
+void set_time(time_t t);
+
+/** Attach an external RTC to be used for the C time functions
+ *
+ * @Note Synchronization level: Thread safe
+ *
+ * @param read_rtc pointer to function which returns current UNIX timestamp
+ * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
+ * @param init_rtc pointer to funtion which initializes RTC, can be NULL
+ * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
+ */
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
+
+#ifdef __cplusplus
+}
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/semihost_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SEMIHOST_H
+#define MBED_SEMIHOST_H
+
+#include "device.h"
+#include "toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+#ifndef __CC_ARM
+
+#if defined(__ICCARM__)
+static inline int __semihost(int reason, const void *arg) {
+    return __semihosting(reason, (void*)arg);
+}
+#else
+
+#ifdef __thumb__
+#   define AngelSWI            0xAB
+#   define AngelSWIInsn        "bkpt"
+#   define AngelSWIAsm          bkpt
+#else
+#   define AngelSWI            0x123456
+#   define AngelSWIInsn        "swi"
+#   define AngelSWIAsm          swi
+#endif
+
+static inline int __semihost(int reason, const void *arg) {
+    int value;
+
+    asm volatile (
+       "mov r0, %1"          "\n\t"
+       "mov r1, %2"          "\n\t"
+       AngelSWIInsn " %a3"   "\n\t"
+       "mov %0, r0"
+       : "=r" (value)                                         /* output operands             */
+       : "r" (reason), "r" (arg), "i" (AngelSWI)              /* input operands              */
+       : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"   /* list of clobbered registers */
+    );
+
+    return value;
+}
+#endif
+#endif
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode);
+int semihost_close (FILEHANDLE fh);
+int semihost_read  (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
+int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
+int semihost_ensure(FILEHANDLE fh);
+long semihost_flen (FILEHANDLE fh);
+int semihost_seek  (FILEHANDLE fh, long position);
+int semihost_istty (FILEHANDLE fh);
+
+int semihost_remove(const char *name);
+int semihost_rename(const char *old_name, const char *new_name);
+#endif
+
+int semihost_uid(char *uid);
+int semihost_reset(void);
+int semihost_vbus(void);
+int semihost_powerdown(void);
+int semihost_exit(void);
+
+int semihost_connected(void);
+int semihost_disabledebug(void);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/toolchain.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,290 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TOOLCHAIN_H
+#define MBED_TOOLCHAIN_H
+
+
+// Warning for unsupported compilers
+#if !defined(__GNUC__)   /* GCC        */ \
+ && !defined(__CC_ARM)   /* ARMCC      */ \
+ && !defined(__clang__)  /* LLVM/Clang */ \
+ && !defined(__ICCARM__) /* IAR        */
+#warning "This compiler is not yet supported."
+#endif
+
+
+// Attributes
+
+/** MBED_PACKED
+ *  Pack a structure, preventing any padding from being added between fields.
+ *
+ *  @code
+ *  #include "toolchain.h"
+ *
+ *  MBED_PACKED(struct) foo {
+ *      char x;
+ *      int y;
+ *  };
+ *  @endcode
+ */
+#ifndef MBED_PACKED
+#if defined(__ICCARM__)
+#define MBED_PACKED(struct) __packed struct
+#else
+#define MBED_PACKED(struct) struct __attribute__((packed))
+#endif
+#endif
+
+/** MBED_ALIGN(N)
+ *  Declare a variable to be aligned on an N-byte boundary.
+ *
+ *  @note
+ *  IAR does not support alignment greater than word size on the stack
+ *  
+ *  @code
+ *  #include "toolchain.h"
+ *
+ *  MBED_ALIGN(16) char a;
+ *  @endcode
+ */
+#ifndef MBED_ALIGN
+#if defined(__ICCARM__)
+#define _MBED_ALIGN(N) _Pragma(#N)
+#define MBED_ALIGN(N) _MBED_ALIGN(data_alignment=N)
+#else
+#define MBED_ALIGN(N) __attribute__((aligned(N)))
+#endif
+#endif
+
+/** MBED_UNUSED
+ *  Declare a function argument to be unused, suppressing compiler warnings
+ *
+ *  @code
+ *  #include "toolchain.h"
+ *
+ *  void foo(MBED_UNUSED int arg) {
+ *
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_UNUSED
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_UNUSED __attribute__((__unused__))
+#else
+#define MBED_UNUSED
+#endif
+#endif
+
+/** MBED_WEAK
+ *  Mark a function as being weak.
+ *  
+ *  @note
+ *  weak functions are not friendly to making code re-usable, as they can only
+ *  be overridden once (and if they are multiply overridden the linker will emit
+ *  no warning). You should not normally use weak symbols as part of the API to
+ *  re-usable modules.
+ *  
+ *  @code
+ *  #include "toolchain.h"
+ *  
+ *  MBED_WEAK void foo() {
+ *      // a weak implementation of foo that can be overriden by a definition
+ *      // without  __weak
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_WEAK
+#if defined(__ICCARM__)
+#define MBED_WEAK __weak
+#else
+#define MBED_WEAK __attribute__((weak))
+#endif
+#endif
+
+/** MBED_PURE
+ *  Hint to the compiler that a function depends only on parameters
+ *
+ *  @code
+ *  #include "toolchain.h"
+ *
+ *  MBED_PURE int foo(int arg){
+ *      // no access to global variables
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_PURE
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_PURE __attribute__((const))
+#else
+#define MBED_PURE
+#endif
+#endif
+
+/** MBED_FORCEINLINE
+ *  Declare a function that must always be inlined. Failure to inline
+ *  such a function will result in an error.
+ *
+ *  @code
+ *  #include "toolchain.h"
+ *  
+ *  MBED_FORCEINLINE void foo() {
+ *  
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_FORCEINLINE
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_FORCEINLINE static inline __attribute__((always_inline))
+#elif defined(__ICCARM__)
+#define MBED_FORCEINLINE _Pragma("inline=forced") static
+#else
+#define MBED_FORCEINLINE static inline
+#endif
+#endif
+
+/** MBED_NORETURN
+ *  Declare a function that will never return.
+ *
+ *  @code
+ *  #include "toolchain.h"
+ *  
+ *  MBED_NORETURN void foo() {
+ *      // must never return
+ *      while (1) {}
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_NORETURN
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
+#define MBED_NORETURN __attribute__((noreturn))
+#elif defined(__ICCARM__)
+#define MBED_NORETURN __noreturn
+#else
+#define MBED_NORETURN
+#endif
+#endif
+
+/** MBED_UNREACHABLE
+ *  An unreachable statement. If the statement is reached,
+ *  behaviour is undefined. Useful in situations where the compiler
+ *  cannot deduce the unreachability of code.
+ *
+ *  @code
+ *  #include "toolchain.h"
+ *
+ *  void foo(int arg) {
+ *      switch (arg) {
+ *          case 1: return 1;
+ *          case 2: return 2;
+ *          ...
+ *      }
+ *      MBED_UNREACHABLE;
+ *  }
+ *  @endcode
+ */
+#ifndef MBED_UNREACHABLE
+#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
+#define MBED_UNREACHABLE __builtin_unreachable()
+#else
+#define MBED_UNREACHABLE while (1)
+#endif
+#endif
+
+/** MBED_DEPRECATED("message string")
+ *  Mark a function declaration as deprecated, if it used then a warning will be
+ *  issued by the compiler possibly including the provided message. Note that not
+ *  all compilers are able to display the message.
+ *
+ *  @code
+ *  #include "toolchain.h"
+ *  
+ *  MBED_DEPRECATED("don't foo any more, bar instead")
+ *  void foo(int arg);
+ *  @endcode
+ */
+#ifndef MBED_DEPRECATED
+#if defined(__GNUC__) || defined(__clang__)
+#define MBED_DEPRECATED(M) __attribute__((deprecated(M)))
+#elif defined(__CC_ARM)
+#define MBED_DEPRECATED(M) __attribute__((deprecated))
+#else
+#define MBED_DEPRECATED(M)
+#endif
+#endif
+
+/** MBED_DEPRECATED_SINCE("version", "message string")
+ *  Mark a function declaration as deprecated, noting that the declaration was
+ *  deprecated on the specified version. If the function is used then a warning
+ *  will be issued by the compiler possibly including the provided message.
+ *  Note that not all compilers are able to display this message.
+ *
+ *  @code
+ *  #include "toolchain.h"
+ *
+ *  MBED_DEPRECATED_SINCE("mbed-os-5.1", "don't foo any more, bar instead")
+ *  void foo(int arg);
+ *  @endcode
+ */
+#define MBED_DEPRECATED_SINCE(D, M) MBED_DEPRECATED(M " [since " D "]")
+
+/** MBED_CALLER_ADDR()
+ * Returns the caller of the current function.
+ *
+ * @note
+ * This macro is only implemented for GCC and ARMCC.
+ *
+ * @code
+ * #include "toolchain.h"
+ *
+ * printf("This function was called from %p", MBED_CALLER_ADDR());
+ * @endcode
+ *
+ * @return Address of the calling function
+ */
+#ifndef MBED_CALLER_ADDR
+#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
+#define MBED_CALLER_ADDR() __builtin_extract_return_addr(__builtin_return_address(0))
+#elif defined(__CC_ARM)
+#define MBED_CALLER_ADDR() __builtin_return_address(0)
+#else
+#define MBED_CALLER_ADDR() (NULL)
+#endif
+#endif
+
+// FILEHANDLE declaration
+#if defined(TOOLCHAIN_ARM)
+#include <rt_sys.h>
+#endif
+
+#ifndef FILEHANDLE
+typedef int FILEHANDLE;
+#endif
+
+// Backwards compatibility
+#ifndef WEAK
+#define WEAK MBED_WEAK
+#endif
+
+#ifndef PACKED
+#define PACKED MBED_PACKED()
+#endif
+
+#ifndef EXTERN
+#define EXTERN extern
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/api/wait_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_WAIT_API_H
+#define MBED_WAIT_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Generic wait functions.
+ *
+ * These provide simple NOP type wait capabilities.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * DigitalOut heartbeat(LED1);
+ *
+ * int main() {
+ *     while (1) {
+ *         heartbeat = 1;
+ *         wait(0.5);
+ *         heartbeat = 0;
+ *         wait(0.5);
+ *     }
+ * }
+ */
+
+/** Waits for a number of seconds, with microsecond resolution (within
+ *  the accuracy of single precision floating point).
+ *
+ *  @param s number of seconds to wait
+ */
+void wait(float s);
+
+/** Waits a number of milliseconds.
+ *
+ *  @param ms the whole number of milliseconds to wait
+ */
+void wait_ms(int ms);
+
+/** Waits a number of microseconds.
+ *
+ *  @param us the whole number of microseconds to wait
+ */
+void wait_us(int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/AnalogIn.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed.h"
+
+#include "AnalogIn.h"
+
+#if DEVICE_ANALOGIN
+
+namespace mbed {
+
+SingletonPtr<PlatformMutex> AnalogIn::_mutex;
+
+};
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/BusIn.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,97 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusIn.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusIn::BusIn(PinName pins[16]) {
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusIn::~BusIn() {
+    // No lock needed in the destructor
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+int BusIn::read() {
+    int v = 0;
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    unlock();
+    return v;
+}
+
+void BusIn::mode(PinMode pull) {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->mode(pull);
+        }
+    }
+    unlock();
+}
+
+void BusIn::lock() {
+    _mutex.lock();
+}
+
+void BusIn::unlock() {
+    _mutex.unlock();
+}
+
+BusIn::operator int() {
+    // Underlying read is thread safe
+    return read();
+}
+
+DigitalIn& BusIn::operator[] (int index) {
+    // No lock needed since _pin is not modified outside the constructor
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/BusInOut.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusInOut.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusInOut::BusInOut(PinName pins[16]) {
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusInOut::~BusInOut() {
+    // No lock needed in the destructor
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+void BusInOut::write(int value) {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->write((value >> i) & 1);
+        }
+    }
+    unlock();
+}
+
+int BusInOut::read() {
+    lock();
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    unlock();
+    return v;
+}
+
+void BusInOut::output() {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->output();
+        }
+    }
+    unlock();
+}
+
+void BusInOut::input() {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->input();
+        }
+    }
+    unlock();
+}
+
+void BusInOut::mode(PinMode pull) {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->mode(pull);
+        }
+    }
+    unlock();
+}
+
+BusInOut& BusInOut::operator= (int v) {
+    // Underlying write is thread safe
+    write(v);
+    return *this;
+}
+
+BusInOut& BusInOut::operator= (BusInOut& rhs) {
+    // Underlying read is thread safe
+    write(rhs.read());
+    return *this;
+}
+
+DigitalInOut& BusInOut::operator[] (int index) {
+    // No lock needed since _pin is not modified outside the constructor
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
+BusInOut::operator int() {
+    // Underlying read is thread safe
+    return read();
+}
+
+void BusInOut::lock() {
+    _mutex.lock();
+}
+
+void BusInOut::unlock() {
+    _mutex.unlock();
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/BusOut.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,109 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusOut.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusOut::BusOut(PinName pins[16]) {
+    // No lock needed in the constructor
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusOut::~BusOut() {
+    // No lock needed in the destructor
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+void BusOut::write(int value) {
+    lock();
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->write((value >> i) & 1);
+        }
+    }
+    unlock();
+}
+
+int BusOut::read() {
+    lock();
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    unlock();
+    return v;
+}
+
+BusOut& BusOut::operator= (int v) {
+    // Underlying write is thread safe
+    write(v);
+    return *this;
+}
+
+BusOut& BusOut::operator= (BusOut& rhs) {
+    // Underlying write is thread safe
+    write(rhs.read());
+    return *this;
+}
+
+DigitalOut& BusOut::operator[] (int index) {
+    // No lock needed since _pin is not modified outside the constructor
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
+BusOut::operator int() {
+    // Underlying read is thread safe
+    return read();
+}
+
+void BusOut::lock() {
+    _mutex.lock();
+}
+
+void BusOut::unlock() {
+    _mutex.unlock();
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/CAN.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,124 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "CAN.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+
+namespace mbed {
+
+CAN::CAN(PinName rd, PinName td) : _can(), _irq() {
+    // No lock needed in constructor
+    can_init(&_can, rd, td);
+    can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
+}
+
+CAN::~CAN() {
+    // No lock needed in destructor
+    can_irq_free(&_can);
+    can_free(&_can);
+}
+
+int CAN::frequency(int f) {
+    lock();
+    int ret = can_frequency(&_can, f);
+    unlock();
+    return ret;
+}
+
+int CAN::write(CANMessage msg) {
+    lock();
+    int ret = can_write(&_can, msg, 0);
+    unlock();
+    return ret;
+}
+
+int CAN::read(CANMessage &msg, int handle) {
+    lock();
+    int ret = can_read(&_can, &msg, handle);
+    unlock();
+    return ret;
+}
+
+void CAN::reset() {
+    lock();
+    can_reset(&_can);
+    unlock();
+}
+
+unsigned char CAN::rderror() {
+    lock();
+    int ret = can_rderror(&_can);
+    unlock();
+    return ret;
+}
+
+unsigned char CAN::tderror() {
+    lock();
+    int ret = can_tderror(&_can);
+    unlock();
+    return ret;
+}
+
+void CAN::monitor(bool silent) {
+    lock();
+    can_monitor(&_can, (silent) ? 1 : 0);
+    unlock();
+}
+
+int CAN::mode(Mode mode) {
+    lock();
+    int ret = can_mode(&_can, (CanMode)mode);
+    unlock();
+    return ret;
+}
+
+int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle) {
+    lock();
+    int ret = can_filter(&_can, id, mask, format, handle);
+    unlock();
+    return ret;
+}
+
+void CAN::attach(Callback<void()> func, IrqType type) {
+    lock();
+    if (func) {
+        _irq[(CanIrqType)type].attach(func);
+        can_irq_set(&_can, (CanIrqType)type, 1);
+    } else {
+        can_irq_set(&_can, (CanIrqType)type, 0);
+    }
+    unlock();
+}
+
+void CAN::_irq_handler(uint32_t id, CanIrqType type) {
+    CAN *handler = (CAN*)id;
+    handler->_irq[type].call();
+}
+
+void CAN::lock() {
+    _mutex.lock();
+}
+
+void CAN::unlock() {
+    _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/CallChain.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,117 @@
+#include "CallChain.h"
+#include "cmsis.h"
+#include "critical.h"
+
+namespace mbed {
+
+class CallChainLink {
+public:
+    CallChainLink(): cb(), next(NULL) {
+        // No work to do
+    }
+
+    CallChainLink(Callback<void()> &callback): cb(callback), next(NULL) {
+        // No work to do
+    }
+    Callback<void()> cb;
+    CallChainLink * next;
+};
+
+CallChain::CallChain(int size) : _chain(NULL) {
+    // No work to do
+}
+
+CallChain::~CallChain() {
+    clear();
+}
+
+pFunctionPointer_t CallChain::add(Callback<void()> func) {
+    CallChainLink *new_link = new CallChainLink(func);
+    if (NULL == _chain) {
+        _chain = new_link;
+        return &new_link->cb;
+    }
+
+    CallChainLink *link = _chain;
+    while (true) {
+        if (NULL == link->next) {
+            link->next = new_link;
+            return &new_link->cb;
+        }
+        link = link->next;
+    }
+}
+
+pFunctionPointer_t CallChain::add_front(Callback<void()> func) {
+    CallChainLink *link = new CallChainLink(func);
+    link->next = _chain;
+    _chain = link->next;
+    return &link->cb;
+}
+
+int CallChain::size() const {
+    CallChainLink *link = _chain;
+    int elements = 0;
+    while (link != NULL) {
+        elements++;
+        link = link->next;
+    }
+    return elements;
+}
+
+pFunctionPointer_t CallChain::get(int idx) const {
+    CallChainLink *link = _chain;
+    for (int i = 0; i < idx; i++) {
+        if (NULL == link) {
+            break;
+        }
+        link = link->next;
+    }
+    return &link->cb;
+}
+
+int CallChain::find(pFunctionPointer_t f) const {
+    CallChainLink *link = _chain;
+    int i = 0;
+    while (link != NULL) {
+        if (f == &link->cb) {
+            return i;
+        }
+        i++;
+        link = link->next;
+    }
+    return -1;
+}
+
+void CallChain::clear() {
+    CallChainLink *link = _chain;
+    _chain = NULL;
+    while (link != NULL) {
+        CallChainLink *temp = link->next;
+        delete link;
+        link = temp;
+    }
+}
+
+bool CallChain::remove(pFunctionPointer_t f) {
+    CallChainLink *link = _chain;
+    while (link != NULL) {
+        if (f == &link->cb) {
+            delete link;
+            return true;
+        }
+        link = link->next;
+    }
+    return false;
+}
+
+void CallChain::call() {
+    CallChainLink *link = _chain;
+    while (link != NULL) {
+        link->cb.call();
+        link = link->next;
+    }
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/Ethernet.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,74 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ethernet.h"
+
+#if DEVICE_ETHERNET
+
+#include "ethernet_api.h"
+
+namespace mbed {
+
+Ethernet::Ethernet() {
+    ethernet_init();
+}
+
+Ethernet::~Ethernet() {
+    ethernet_free();
+}
+
+int Ethernet::write(const char *data, int size) {
+    return ethernet_write(data, size);
+}
+
+int Ethernet::send() {
+    return ethernet_send();
+}
+
+int Ethernet::receive() {
+    return ethernet_receive();
+}
+
+int Ethernet::read(char *data, int size) {
+    return ethernet_read(data, size);
+}
+
+void Ethernet::address(char *mac) {
+    return ethernet_address(mac);
+}
+
+int Ethernet::link() {
+    return ethernet_link();
+}
+
+void Ethernet::set_link(Mode mode) {
+    int speed = -1;
+    int duplex = 0;
+
+    switch(mode) {
+        case AutoNegotiate : speed = -1; duplex = 0; break;
+        case HalfDuplex10  : speed = 0;  duplex = 0; break;
+        case FullDuplex10  : speed = 0;  duplex = 1; break;
+        case HalfDuplex100 : speed = 1;  duplex = 0; break;
+        case FullDuplex100 : speed = 1;  duplex = 1; break;
+    }
+
+    ethernet_set_link(speed, duplex);
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/FileBase.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileBase.h"
+
+namespace mbed {
+
+FileBase *FileBase::_head = NULL;
+SingletonPtr<PlatformMutex> FileBase::_mutex;
+
+FileBase::FileBase(const char *name, PathType t) : _next(NULL),
+                                                   _name(name),
+                                                   _path_type(t) {
+    _mutex->lock();
+    if (name != NULL) {
+        // put this object at head of the list
+        _next = _head;
+        _head = this;
+    } else {
+        _next = NULL;
+    }
+    _mutex->unlock();
+}
+
+FileBase::~FileBase() {
+    _mutex->lock();
+    if (_name != NULL) {
+        // remove this object from the list
+        if (_head == this) { // first in the list, so just drop me
+            _head = _next;
+        } else {             // find the object before me, then drop me
+            FileBase *p = _head;
+            while (p->_next != this) {
+                p = p->_next;
+            }
+            p->_next = _next;
+        }
+    }
+    _mutex->unlock();
+}
+
+FileBase *FileBase::lookup(const char *name, unsigned int len) {
+    _mutex->lock();
+    FileBase *p = _head;
+    while (p != NULL) {
+        /* Check that p->_name matches name and is the correct length */
+        if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
+            _mutex->unlock();
+            return p;
+        }
+        p = p->_next;
+    }
+    _mutex->unlock();
+    return NULL;
+}
+
+FileBase *FileBase::get(int n) {
+    _mutex->lock();
+    FileBase *p = _head;
+    int m = 0;
+    while (p != NULL) {
+        if (m == n) {
+            _mutex->unlock();
+            return p;
+        }
+
+        m++;
+        p = p->_next;
+    }
+    _mutex->unlock();
+    return NULL;
+}
+
+const char* FileBase::getName(void) {
+    // Constant read so no lock needed
+    return _name;
+}
+
+PathType FileBase::getPathType(void) {
+    // Constant read so no lock needed
+    return _path_type;
+}
+
+} // namespace mbed
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/FileLike.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,29 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileLike.h"
+
+namespace mbed {
+
+FileLike::FileLike(const char *name) : FileHandle(), FileBase(name, FilePathType) {
+
+}
+
+FileLike::~FileLike() {
+
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/FilePath.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FilePath.h"
+
+namespace mbed {
+
+FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) {
+    if ((file_path[0] != '/') || (file_path[1] == 0)) return;
+
+    const char* file_system = &file_path[1];
+    file_name = file_system;
+    int len = 0;
+    while (true) {
+        char c = *file_name;
+        if (c == '/') { // end of object name
+            file_name++; // point to one char after the '/'
+            break;
+        }
+        if (c == 0) { // end of object name, with no filename
+            break;
+        }
+        len++;
+        file_name++;
+    }
+
+    fb = FileBase::lookup(file_system, len);
+}
+
+const char* FilePath::fileName(void) {
+    return file_name;
+}
+
+bool FilePath::isFileSystem(void) {
+    if (NULL == fb)
+        return false;
+    return (fb->getPathType() == FileSystemPathType);
+}
+
+FileSystemLike* FilePath::fileSystem(void) {
+    if (isFileSystem()) {
+        return (FileSystemLike*)fb;
+    }
+    return NULL;
+}
+
+bool FilePath::isFile(void) {
+    if (NULL == fb)
+        return false;
+    return (fb->getPathType() == FilePathType);
+}
+
+FileLike* FilePath::file(void) {
+    if (isFile()) {
+        return (FileLike*)fb;
+    }
+    return NULL;
+}
+
+bool FilePath::exists(void) {
+    return fb != NULL;
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/FileSystemLike.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,102 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileSystemLike.h"
+
+namespace mbed {
+
+class BaseDirHandle : public DirHandle {
+public:
+    /*
+      We keep track of our current location as the n'th object in the
+      FileSystemLike list. Using a Base* instead would cause problems if that
+      object were to be destroyed between readdirs.
+      Using this method does mean though that destroying/creating objects can
+      give unusual results from readdir.
+    */
+    off_t n;
+    struct dirent cur_entry;
+
+    BaseDirHandle() : n(0), cur_entry() {
+    }
+
+    virtual int closedir() {
+        // No lock can be used in destructor
+        delete this;
+        return 0;
+    }
+
+    virtual struct dirent *readdir() {
+        lock();
+        FileBase *ptr = FileBase::get(n);
+        if (ptr == NULL) {
+            unlock();
+            return NULL;
+        }
+
+        /* Increment n, so next readdir gets the next item */
+        n++;
+
+        /* Setup cur entry and return a pointer to it */
+        std::strncpy(cur_entry.d_name, ptr->getName(), NAME_MAX);
+        unlock();
+        return &cur_entry;
+    }
+
+    virtual off_t telldir() {
+        lock();
+        off_t offset = n;
+        unlock();
+        return offset;
+    }
+
+    virtual void seekdir(off_t offset) {
+        lock();
+        n = offset;
+        unlock();
+    }
+
+    virtual void rewinddir() {
+        lock();
+        n = 0;
+        unlock();
+    }
+
+protected:
+    PlatformMutex _mutex;
+
+    virtual void lock() {
+        _mutex.lock();
+    }
+
+    virtual void unlock() {
+        _mutex.unlock();
+    }
+};
+
+FileSystemLike::FileSystemLike(const char *name) : FileBase(name, FileSystemPathType) {
+
+}
+
+FileSystemLike::~FileSystemLike() {
+
+}
+
+DirHandle *FileSystemLike::opendir() {
+    return new BaseDirHandle();
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/I2C.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,164 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "I2C.h"
+
+#if DEVICE_I2C
+
+namespace mbed {
+
+I2C *I2C::_owner = NULL;
+SingletonPtr<PlatformMutex> I2C::_mutex;
+
+I2C::I2C(PinName sda, PinName scl) :
+#if DEVICE_I2C_ASYNCH
+                                     _irq(this), _usage(DMA_USAGE_NEVER),
+#endif
+                                      _i2c(), _hz(100000) {
+    // No lock needed in the constructor
+
+    // The init function also set the frequency to 100000
+    i2c_init(&_i2c, sda, scl);
+
+    // Used to avoid unnecessary frequency updates
+    _owner = this;
+}
+
+void I2C::frequency(int hz) {
+    lock();
+    _hz = hz;
+
+    // We want to update the frequency even if we are already the bus owners
+    i2c_frequency(&_i2c, _hz);
+
+    // Updating the frequency of the bus we become the owners of it
+    _owner = this;
+    unlock();
+}
+
+void I2C::aquire() {
+    lock();
+    if (_owner != this) {
+        i2c_frequency(&_i2c, _hz);
+        _owner = this;
+    }
+    unlock();
+}
+
+// write - Master Transmitter Mode
+int I2C::write(int address, const char* data, int length, bool repeated) {
+    lock();
+    aquire();
+
+    int stop = (repeated) ? 0 : 1;
+    int written = i2c_write(&_i2c, address, data, length, stop);
+
+    unlock();
+    return length != written;
+}
+
+int I2C::write(int data) {
+    lock();
+    int ret = i2c_byte_write(&_i2c, data);
+    unlock();
+    return ret;
+}
+
+// read - Master Reciever Mode
+int I2C::read(int address, char* data, int length, bool repeated) {
+    lock();
+    aquire();
+
+    int stop = (repeated) ? 0 : 1;
+    int read = i2c_read(&_i2c, address, data, length, stop);
+
+    unlock();
+    return length != read;
+}
+
+int I2C::read(int ack) {
+    lock();
+    int ret;
+    if (ack) {
+        ret = i2c_byte_read(&_i2c, 0);
+    } else {
+        ret = i2c_byte_read(&_i2c, 1);
+    }
+    unlock();
+    return ret;
+}
+
+void I2C::start(void) {
+    lock();
+    i2c_start(&_i2c);
+    unlock();
+}
+
+void I2C::stop(void) {
+    lock();
+    i2c_stop(&_i2c);
+    unlock();
+}
+
+void I2C::lock() {
+    _mutex->lock();
+}
+
+void I2C::unlock() {
+    _mutex->unlock();
+}
+
+#if DEVICE_I2C_ASYNCH
+
+int I2C::transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event, bool repeated)
+{
+    lock();
+    if (i2c_active(&_i2c)) {
+        unlock();
+        return -1; // transaction ongoing
+    }
+    aquire();
+
+    _callback = callback;
+    int stop = (repeated) ? 0 : 1;
+    _irq.callback(&I2C::irq_handler_asynch);
+    i2c_transfer_asynch(&_i2c, (void *)tx_buffer, tx_length, (void *)rx_buffer, rx_length, address, stop, _irq.entry(), event, _usage);
+    unlock();
+    return 0;
+}
+
+void I2C::abort_transfer(void)
+{
+    lock();
+    i2c_abort_asynch(&_i2c);
+    unlock();
+}
+
+void I2C::irq_handler_asynch(void)
+{
+    int event = i2c_irq_handler_asynch(&_i2c);
+    if (_callback && event) {
+        _callback.call(event);
+    }
+
+}
+
+
+#endif
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/I2CSlave.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "I2CSlave.h"
+
+#if DEVICE_I2CSLAVE
+
+namespace mbed {
+
+I2CSlave::I2CSlave(PinName sda, PinName scl) : _i2c() {
+    i2c_init(&_i2c, sda, scl);
+    i2c_frequency(&_i2c, 100000);
+    i2c_slave_mode(&_i2c, 1);
+}
+
+void I2CSlave::frequency(int hz) {
+    i2c_frequency(&_i2c, hz);
+}
+
+void I2CSlave::address(int address) {
+    int addr = (address & 0xFF) | 1;
+    i2c_slave_address(&_i2c, 0, addr, 0);
+}
+
+int I2CSlave::receive(void) {
+    return i2c_slave_receive(&_i2c);
+}
+
+int I2CSlave::read(char *data, int length) {
+    return i2c_slave_read(&_i2c, data, length) != length;
+}
+
+int I2CSlave::read(void) {
+    return i2c_byte_read(&_i2c, 0);
+}
+
+int I2CSlave::write(const char *data, int length) {
+    return i2c_slave_write(&_i2c, data, length) != length;
+}
+
+int I2CSlave::write(int data) {
+    return i2c_byte_write(&_i2c, data);
+}
+
+void I2CSlave::stop(void) {
+    i2c_stop(&_i2c);
+}
+
+}
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/InterruptIn.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,100 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "InterruptIn.h"
+
+#if DEVICE_INTERRUPTIN
+
+namespace mbed {
+
+InterruptIn::InterruptIn(PinName pin) : gpio(),
+                                        gpio_irq(),
+                                        _rise(),
+                                        _fall() {
+    // No lock needed in the constructor
+    gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
+    gpio_init_in(&gpio, pin);
+}
+
+InterruptIn::~InterruptIn() {
+    // No lock needed in the destructor
+    gpio_irq_free(&gpio_irq);
+}
+
+int InterruptIn::read() {
+    // Read only
+    return gpio_read(&gpio);
+}
+
+void InterruptIn::mode(PinMode pull) {
+    core_util_critical_section_enter();
+    gpio_mode(&gpio, pull);
+    core_util_critical_section_exit();
+}
+
+void InterruptIn::rise(Callback<void()> func) {
+    core_util_critical_section_enter();
+    if (func) {
+        _rise.attach(func);
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+    } else {
+        _rise.attach(NULL);
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
+    }
+    core_util_critical_section_exit();
+}
+
+void InterruptIn::fall(Callback<void()> func) {
+    core_util_critical_section_enter();
+    if (func) {
+        _fall.attach(func);
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+    } else {
+        _fall.attach(NULL);
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
+    }
+    core_util_critical_section_exit();
+}
+
+void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
+    InterruptIn *handler = (InterruptIn*)id;
+    switch (event) {
+        case IRQ_RISE: handler->_rise.call(); break;
+        case IRQ_FALL: handler->_fall.call(); break;
+        case IRQ_NONE: break;
+    }
+}
+
+void InterruptIn::enable_irq() {
+    core_util_critical_section_enter();
+    gpio_irq_enable(&gpio_irq);
+    core_util_critical_section_exit();
+}
+
+void InterruptIn::disable_irq() {
+    core_util_critical_section_enter();
+    gpio_irq_disable(&gpio_irq);
+    core_util_critical_section_exit();
+}
+
+InterruptIn::operator int() {
+    // Underlying call is atomic
+    return read();
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/InterruptManager.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,123 @@
+#include "cmsis.h"
+#if defined(NVIC_NUM_VECTORS)
+
+#include "InterruptManager.h"
+#include "critical.h"
+#include <string.h>
+
+#define CHAIN_INITIAL_SIZE    4
+
+namespace mbed {
+
+typedef void (*pvoidf)(void);
+
+InterruptManager* InterruptManager::_instance = (InterruptManager*)NULL;
+
+InterruptManager* InterruptManager::get() {
+
+    if (NULL == _instance) {
+        InterruptManager* temp = new InterruptManager();
+
+        // Atomically set _instance
+        core_util_critical_section_enter();
+        if (NULL == _instance) {
+            _instance = temp;
+        }
+        core_util_critical_section_exit();
+
+        // Another thread got there first so delete ours
+        if (temp != _instance) {
+            delete temp;
+        }
+
+    }
+    return _instance;
+}
+
+InterruptManager::InterruptManager() {
+    // No mutex needed in constructor
+    memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain*));
+}
+
+void InterruptManager::destroy() {
+    // Not a good idea to call this unless NO interrupt at all
+    // is under the control of the handler; otherwise, a system crash
+    // is very likely to occur
+    if (NULL != _instance) {
+        delete _instance;
+        _instance = (InterruptManager*)NULL;
+    }
+}
+
+InterruptManager::~InterruptManager() {
+    for(int i = 0; i < NVIC_NUM_VECTORS; i++)
+        if (NULL != _chains[i])
+            delete _chains[i];
+}
+
+bool InterruptManager::must_replace_vector(IRQn_Type irq) {
+    lock();
+
+    int ret = false;
+    int irq_pos = get_irq_index(irq);
+    if (NULL == _chains[irq_pos]) {
+        _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE);
+        _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq));
+        ret = true;
+    }
+    unlock();
+    return ret;
+}
+
+pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front) {
+    lock();
+    int irq_pos = get_irq_index(irq);
+    bool change = must_replace_vector(irq);
+
+    pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function);
+    if (change)
+        NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+    unlock();
+    return pf;
+}
+
+bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq) {
+    int irq_pos = get_irq_index(irq);
+    bool ret = false;
+
+    lock();
+    if (_chains[irq_pos] != NULL) {
+        if (_chains[irq_pos]->remove(handler)) {
+            ret = true;
+        }
+    }
+    unlock();
+
+    return ret;
+}
+
+void InterruptManager::irq_helper() {
+    _chains[__get_IPSR()]->call();
+}
+
+int InterruptManager::get_irq_index(IRQn_Type irq) {
+    // Pure function - no lock needed
+    return (int)irq + NVIC_USER_IRQ_OFFSET;
+}
+
+void InterruptManager::static_irq_helper() {
+    InterruptManager::get()->irq_helper();
+}
+
+void InterruptManager::lock() {
+    _mutex.lock();
+}
+
+void InterruptManager::unlock() {
+    _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/LocalFileSystem.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,276 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "LocalFileSystem.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "semihost_api.h"
+#include <string.h>
+#include <stdio.h>
+
+namespace mbed {
+
+/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */
+typedef struct {
+    unsigned char  hr;   /* Hours    [0..23]                  */
+    unsigned char  min;  /* Minutes  [0..59]                  */
+    unsigned char  sec;  /* Seconds  [0..59]                  */
+    unsigned char  day;  /* Day      [1..31]                  */
+    unsigned char  mon;  /* Month    [1..12]                  */
+    unsigned short year; /* Year     [1980..2107]             */
+} FTIME;
+
+typedef struct {         /* File Search info record           */
+    char  name[32];      /* File name                         */
+    long  size;          /* File size in bytes                */
+    int   fileID;        /* System File Identification        */
+    FTIME create_time;   /* Date & time file was created      */
+    FTIME write_time;    /* Date & time of last write         */
+} XFINFO;
+
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+
+static int xffind (const char *pattern, XFINFO *info) {
+    unsigned param[4];
+
+    param[0] = (unsigned long)pattern;
+    param[1] = (unsigned long)strlen(pattern);
+    param[2] = (unsigned long)info;
+    param[3] = (unsigned long)sizeof(XFINFO);
+
+    return __semihost(USR_XFFIND, param);
+}
+
+#define OPEN_R          0
+#define OPEN_B          1
+#define OPEN_PLUS       2
+#define OPEN_W          4
+#define OPEN_A          8
+#define OPEN_INVALID   -1
+
+int posix_to_semihost_open_flags(int flags) {
+    /* POSIX flags -> semihosting open mode */
+    int openmode;
+    if (flags & O_RDWR) {
+        /* a plus mode */
+        openmode = OPEN_PLUS;
+        if (flags & O_APPEND) {
+            openmode |= OPEN_A;
+        } else if (flags & O_TRUNC) {
+            openmode |= OPEN_W;
+        } else {
+            openmode |= OPEN_R;
+        }
+    } else if (flags & O_WRONLY) {
+        /* write or append */
+        if (flags & O_APPEND) {
+            openmode = OPEN_A;
+        } else {
+            openmode = OPEN_W;
+        }
+    } else if (flags == O_RDONLY) {
+        /* read mode */
+        openmode = OPEN_R;
+    } else {
+        /* invalid flags */
+        openmode = OPEN_INVALID;
+    }
+
+    return openmode;
+}
+
+FILEHANDLE local_file_open(const char* name, int flags) {
+    int openmode = posix_to_semihost_open_flags(flags);
+    if (openmode == OPEN_INVALID) {
+        return (FILEHANDLE)NULL;
+    }
+
+    FILEHANDLE fh = semihost_open(name, openmode);
+    if (fh == -1) {
+        return (FILEHANDLE)NULL;
+    }
+
+    return fh;
+}
+
+LocalFileHandle::LocalFileHandle(FILEHANDLE fh) : _fh(fh), pos(0) {
+    // No lock needed in constructor
+}
+
+int LocalFileHandle::close() {
+    int retval = semihost_close(_fh);
+    delete this;
+    return retval;
+}
+
+ssize_t LocalFileHandle::write(const void *buffer, size_t length) {
+    lock();
+    ssize_t n = semihost_write(_fh, (const unsigned char*)buffer, length, 0); // number of characters not written
+    n = length - n; // number of characters written
+    pos += n;
+    unlock();
+    return n;
+}
+
+ssize_t LocalFileHandle::read(void *buffer, size_t length) {
+    lock();
+    ssize_t n = semihost_read(_fh, (unsigned char*)buffer, length, 0); // number of characters not read
+    n = length - n; // number of characters read
+    pos += n;
+    unlock();
+    return n;
+}
+
+int LocalFileHandle::isatty() {
+    lock();
+    int ret = semihost_istty(_fh);
+    unlock();
+    return ret;
+}
+
+off_t LocalFileHandle::lseek(off_t position, int whence) {
+    lock();
+    if (whence == SEEK_CUR) {
+        position += pos;
+    } else if (whence == SEEK_END) {
+        position += semihost_flen(_fh);
+    } /* otherwise SEEK_SET, so position is fine */
+
+    /* Always seems to return -1, so just ignore for now. */
+    semihost_seek(_fh, position);
+    pos = position;
+    unlock();
+    return position;
+}
+
+int LocalFileHandle::fsync() {
+    lock();
+    int ret = semihost_ensure(_fh);
+    unlock();
+    return ret;
+}
+
+off_t LocalFileHandle::flen() {
+    lock();
+    off_t off = semihost_flen(_fh);
+    unlock();
+    return off;
+}
+
+void LocalFileHandle::lock() {
+    _mutex.lock();
+}
+
+void LocalFileHandle::unlock() {
+    _mutex.unlock();
+}
+
+class LocalDirHandle : public DirHandle {
+
+public:
+    struct dirent cur_entry;
+    XFINFO info;
+
+    LocalDirHandle() : cur_entry(), info() {
+    }
+
+    virtual int closedir() {
+        // No lock can be used in destructor
+        delete this;
+        return 0;
+    }
+
+    virtual struct dirent *readdir() {
+        lock();
+        if (xffind("*", &info)!=0) {
+            unlock();
+            return NULL;
+        }
+        memcpy(cur_entry.d_name, info.name, sizeof(info.name));
+        unlock();
+        return &cur_entry;
+    }
+
+    virtual void rewinddir() {
+        lock();
+        info.fileID = 0;
+        unlock();
+    }
+
+    virtual off_t telldir() {
+        lock();
+        int fileId = info.fileID;
+        unlock();
+        return fileId;
+    }
+
+    virtual void seekdir(off_t offset) {
+        lock();
+        info.fileID = offset;
+        unlock();
+    }
+
+protected:
+    PlatformMutex _mutex;
+
+    virtual void lock() {
+        _mutex.lock();
+    }
+
+    virtual void unlock() {
+        _mutex.unlock();
+    }
+};
+
+FileHandle *LocalFileSystem::open(const char* name, int flags) {
+    // No global state modified so function is thread safe
+
+    /* reject filenames with / in them */
+    for (const char *tmp = name; *tmp; tmp++) {
+        if (*tmp == '/') {
+            return NULL;
+        }
+    }
+
+    int openmode = posix_to_semihost_open_flags(flags);
+    if (openmode == OPEN_INVALID) {
+        return NULL;
+    }
+
+    FILEHANDLE fh = semihost_open(name, openmode);
+    if (fh == -1) {
+        return NULL;
+    }
+    return new LocalFileHandle(fh);
+}
+
+int LocalFileSystem::remove(const char *filename) {
+    // No global state modified so function is thread safe
+
+    return semihost_remove(filename);
+}
+
+DirHandle *LocalFileSystem::opendir(const char *name) {
+    // No global state modified so function is thread safe
+
+    return new LocalDirHandle();
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/RawSerial.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "RawSerial.h"
+#include "wait_api.h"
+#include <cstdarg>
+
+#if DEVICE_SERIAL
+
+#define STRING_STACK_LIMIT    120
+
+namespace mbed {
+
+RawSerial::RawSerial(PinName tx, PinName rx) : SerialBase(tx, rx) {
+    // No lock needed in the constructor
+}
+
+int RawSerial::getc() {
+    lock();
+    int ret = _base_getc();
+    unlock();
+    return ret;
+}
+
+int RawSerial::putc(int c) {
+    lock();
+    int ret = _base_putc(c);
+    unlock();
+    return ret;
+}
+
+int RawSerial::puts(const char *str) {
+    lock();
+    while (*str)
+        putc(*str ++);
+    unlock();
+    return 0;
+}
+
+// Experimental support for printf in RawSerial. No Stream inheritance
+// means we can't call printf() directly, so we use sprintf() instead.
+// We only call malloc() for the sprintf() buffer if the buffer
+// length is above a certain threshold, otherwise we use just the stack.
+int RawSerial::printf(const char *format, ...) {
+    lock();
+    std::va_list arg;
+    va_start(arg, format);
+    // ARMCC microlib does not properly handle a size of 0.
+    // As a workaround supply a dummy buffer with a size of 1.
+    char dummy_buf[1];
+    int len = vsnprintf(dummy_buf, sizeof(dummy_buf), format, arg);
+    if (len < STRING_STACK_LIMIT) {
+        char temp[STRING_STACK_LIMIT];
+        vsprintf(temp, format, arg);
+        puts(temp);
+    } else {
+        char *temp = new char[len + 1];
+        vsprintf(temp, format, arg);
+        puts(temp);
+        delete[] temp;
+    }
+    va_end(arg);
+    unlock();
+    return len;
+}
+
+/** Acquire exclusive access to this serial port
+ */
+void RawSerial::lock() {
+    // No lock used - external synchronization required
+}
+
+/** Release exclusive access to this serial port
+ */
+void RawSerial::unlock() {
+    // No lock used - external synchronization required
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/SPI.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,206 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SPI.h"
+#include "critical.h"
+
+#if DEVICE_SPI
+
+namespace mbed {
+
+#if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
+CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
+#endif
+
+SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+        _spi(),
+#if DEVICE_SPI_ASYNCH
+        _irq(this),
+        _usage(DMA_USAGE_NEVER),
+#endif
+        _bits(8),
+        _mode(0),
+        _hz(1000000) {
+    // No lock needed in the constructor
+
+    spi_init(&_spi, mosi, miso, sclk, ssel);
+    aquire();
+}
+
+void SPI::format(int bits, int mode) {
+    lock();
+    _bits = bits;
+    _mode = mode;
+    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+    aquire();
+    unlock();
+}
+
+void SPI::frequency(int hz) {
+    lock();
+    _hz = hz;
+    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+    aquire();
+    unlock();
+}
+
+SPI* SPI::_owner = NULL;
+SingletonPtr<PlatformMutex> SPI::_mutex;
+
+// ignore the fact there are multiple physical spis, and always update if it wasnt us last
+void SPI::aquire() {
+    lock();
+     if (_owner != this) {
+        spi_format(&_spi, _bits, _mode, 0);
+        spi_frequency(&_spi, _hz);
+        _owner = this;
+    }
+    unlock();
+}
+
+int SPI::write(int value) {
+    lock();
+    aquire();
+    int ret = spi_master_write(&_spi, value);
+    unlock();
+    return ret;
+}
+
+void SPI::lock() {
+    _mutex->lock();
+}
+
+void SPI::unlock() {
+    _mutex->unlock();
+}
+
+#if DEVICE_SPI_ASYNCH
+
+int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+    if (spi_active(&_spi)) {
+        return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
+    }
+    start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
+    return 0;
+}
+
+void SPI::abort_transfer()
+{
+    spi_abort_asynch(&_spi);
+#if TRANSACTION_QUEUE_SIZE_SPI
+    dequeue_transaction();
+#endif
+}
+
+
+void SPI::clear_transfer_buffer()
+{
+#if TRANSACTION_QUEUE_SIZE_SPI
+    _transaction_buffer.reset();
+#endif
+}
+
+void SPI::abort_all_transfers()
+{
+    clear_transfer_buffer();
+    abort_transfer();
+}
+
+int SPI::set_dma_usage(DMAUsage usage)
+{
+    if (spi_active(&_spi)) {
+        return -1;
+    }
+    _usage = usage;
+    return  0;
+}
+
+int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+#if TRANSACTION_QUEUE_SIZE_SPI
+    transaction_t t;
+
+    t.tx_buffer = const_cast<void *>(tx_buffer);
+    t.tx_length = tx_length;
+    t.rx_buffer = rx_buffer;
+    t.rx_length = rx_length;
+    t.event = event;
+    t.callback = callback;
+    t.width = bit_width;
+    Transaction<SPI> transaction(this, t);
+    if (_transaction_buffer.full()) {
+        return -1; // the buffer is full
+    } else {
+        core_util_critical_section_enter();
+        _transaction_buffer.push(transaction);
+        if (!spi_active(&_spi)) {
+            dequeue_transaction();
+        }
+        core_util_critical_section_exit();
+        return 0;
+    }
+#else
+    return -1;
+#endif
+}
+
+void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+    aquire();
+    _callback = callback;
+    _irq.callback(&SPI::irq_handler_asynch);
+    spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
+}
+
+#if TRANSACTION_QUEUE_SIZE_SPI
+
+void SPI::start_transaction(transaction_t *data)
+{
+    start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
+}
+
+void SPI::dequeue_transaction()
+{
+    Transaction<SPI> t;
+    if (_transaction_buffer.pop(t)) {
+        SPI* obj = t.get_object();
+        transaction_t* data = t.get_transaction();
+        obj->start_transaction(data);
+    }
+}
+
+#endif
+
+void SPI::irq_handler_asynch(void)
+{
+    int event = spi_irq_handler_asynch(&_spi);
+    if (_callback && (event & SPI_EVENT_ALL)) {
+        _callback.call(event & SPI_EVENT_ALL);
+    }
+#if TRANSACTION_QUEUE_SIZE_SPI
+    if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
+        // SPI peripheral is free (event happend), dequeue transaction
+        dequeue_transaction();
+    }
+#endif
+}
+
+#endif
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/SPISlave.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SPISlave.h"
+
+#if DEVICE_SPISLAVE
+
+namespace mbed {
+
+SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+    _spi(),
+    _bits(8),
+    _mode(0),
+    _hz(1000000)
+ {
+    spi_init(&_spi, mosi, miso, sclk, ssel);
+    spi_format(&_spi, _bits, _mode, 1);
+    spi_frequency(&_spi, _hz);
+}
+
+void SPISlave::format(int bits, int mode) {
+    _bits = bits;
+    _mode = mode;
+    spi_format(&_spi, _bits, _mode, 1);
+}
+
+void SPISlave::frequency(int hz) {
+    _hz = hz;
+    spi_frequency(&_spi, _hz);
+}
+
+int SPISlave::receive(void) {
+    return(spi_slave_receive(&_spi));
+}
+
+int SPISlave::read(void) {
+    return(spi_slave_read(&_spi));
+}
+
+void SPISlave::reply(int value) {
+    spi_slave_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/Serial.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Serial.h"
+#include "wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+Serial::Serial(PinName tx, PinName rx, const char *name) : SerialBase(tx, rx), Stream(name) {
+}
+
+int Serial::_getc() {
+    // Mutex is already held
+    return _base_getc();
+}
+
+int Serial::_putc(int c) {
+    // Mutex is already held
+    return _base_putc(c);
+}
+
+void Serial::lock() {
+    _mutex.lock();
+}
+
+void Serial::unlock() {
+    _mutex.unlock();
+}
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/SerialBase.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,245 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SerialBase.h"
+#include "wait_api.h"
+#include "critical.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+SerialBase::SerialBase(PinName tx, PinName rx) :
+#if DEVICE_SERIAL_ASYNCH
+                                                 _thunk_irq(this), _tx_usage(DMA_USAGE_NEVER),
+                                                 _rx_usage(DMA_USAGE_NEVER),
+#endif
+                                                _serial(), _baud(9600) {
+    // No lock needed in the constructor
+
+    serial_init(&_serial, tx, rx);
+    serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this);
+}
+
+void SerialBase::baud(int baudrate) {
+    lock();
+    serial_baud(&_serial, baudrate);
+    _baud = baudrate;
+    unlock();
+}
+
+void SerialBase::format(int bits, Parity parity, int stop_bits) {
+    lock();
+    serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
+    unlock();
+}
+
+int SerialBase::readable() {
+    lock();
+    int ret = serial_readable(&_serial);
+    unlock();
+    return ret;
+}
+
+
+int SerialBase::writeable() {
+    lock();
+    int ret = serial_writable(&_serial);
+    unlock();
+    return ret;
+}
+
+void SerialBase::attach(Callback<void()> func, IrqType type) {
+    lock();
+    // Disable interrupts when attaching interrupt handler
+    core_util_critical_section_enter();
+    if (func) {
+        _irq[type].attach(func);
+        serial_irq_set(&_serial, (SerialIrq)type, 1);
+    } else {
+        serial_irq_set(&_serial, (SerialIrq)type, 0);
+    }
+    core_util_critical_section_exit();
+    unlock();
+}
+
+void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) {
+    SerialBase *handler = (SerialBase*)id;
+    handler->_irq[irq_type].call();
+}
+
+int SerialBase::_base_getc() {
+    // Mutex is already held
+    return serial_getc(&_serial);
+}
+
+int SerialBase::_base_putc(int c) {
+    // Mutex is already held
+    serial_putc(&_serial, c);
+    return c;
+}
+
+void SerialBase::send_break() {
+    lock();
+  // Wait for 1.5 frames before clearing the break condition
+  // This will have different effects on our platforms, but should
+  // ensure that we keep the break active for at least one frame.
+  // We consider a full frame (1 start bit + 8 data bits bits +
+  // 1 parity bit + 2 stop bits = 12 bits) for computation.
+  // One bit time (in us) = 1000000/_baud
+  // Twelve bits: 12000000/baud delay
+  // 1.5 frames: 18000000/baud delay
+  serial_break_set(&_serial);
+  wait_us(18000000/_baud);
+  serial_break_clear(&_serial);
+  unlock();
+}
+
+void SerialBase::lock() {
+    // Stub
+}
+
+void SerialBase:: unlock() {
+    // Stub
+}
+
+#if DEVICE_SERIAL_FC
+void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
+    lock();
+    FlowControl flow_type = (FlowControl)type;
+    switch(type) {
+        case RTS:
+            serial_set_flow_control(&_serial, flow_type, flow1, NC);
+            break;
+
+        case CTS:
+            serial_set_flow_control(&_serial, flow_type, NC, flow1);
+            break;
+
+        case RTSCTS:
+        case Disabled:
+            serial_set_flow_control(&_serial, flow_type, flow1, flow2);
+            break;
+
+        default:
+            break;
+    }
+    unlock();
+}
+#endif
+
+#if DEVICE_SERIAL_ASYNCH
+
+int SerialBase::write(const uint8_t *buffer, int length, const event_callback_t& callback, int event)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_write((void *)buffer, length, 8, callback, event);
+    return 0;
+}
+
+int SerialBase::write(const uint16_t *buffer, int length, const event_callback_t& callback, int event)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_write((void *)buffer, length, 16, callback, event);
+    return 0;
+}
+
+void SerialBase::start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event)
+{
+    _tx_callback = callback;
+
+    _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+    serial_tx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, _tx_usage);
+}
+
+void SerialBase::abort_write(void)
+{
+    serial_tx_abort_asynch(&_serial);
+}
+
+void SerialBase::abort_read(void)
+{
+    serial_rx_abort_asynch(&_serial);
+}
+
+int SerialBase::set_dma_usage_tx(DMAUsage usage)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1;
+    }
+    _tx_usage = usage;
+    return 0;
+}
+
+int SerialBase::set_dma_usage_rx(DMAUsage usage)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1;
+    }
+    _rx_usage = usage;
+    return 0;
+}
+
+int SerialBase::read(uint8_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match)
+{
+    if (serial_rx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_read((void*)buffer, length, 8, callback, event, char_match);
+    return 0;
+}
+
+
+int SerialBase::read(uint16_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match)
+{
+    if (serial_rx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_read((void*)buffer, length, 16, callback, event, char_match);
+    return 0;
+}
+
+
+void SerialBase::start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match)
+{
+    _rx_callback = callback;
+    _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+    serial_rx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, char_match, _rx_usage);
+}
+
+void SerialBase::interrupt_handler_asynch(void)
+{
+    int event = serial_irq_handler_asynch(&_serial);
+    int rx_event = event & SERIAL_EVENT_RX_MASK;
+    if (_rx_callback && rx_event) {
+        _rx_callback.call(rx_event);
+    }
+
+    int tx_event = event & SERIAL_EVENT_TX_MASK;
+    if (_tx_callback && tx_event) {
+        _tx_callback.call(tx_event);
+    }
+}
+
+#endif
+
+} // namespace mbed
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/Stream.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,152 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Stream.h"
+
+namespace mbed {
+
+Stream::Stream(const char *name) : FileLike(name), _file(NULL) {
+    // No lock needed in constructor
+    /* open ourselves */
+    char buf[12]; /* :0x12345678 + null byte */
+    std::sprintf(buf, ":%p", this);
+    _file = std::fopen(buf, "w+");
+    mbed_set_unbuffered_stream(_file);
+}
+
+Stream::~Stream() {
+    // No lock can be used in destructor
+    fclose(_file);
+}
+
+int Stream::putc(int c) {
+    lock();
+    fflush(_file);
+    int ret = std::fputc(c, _file);
+    unlock();
+    return ret;
+}
+int Stream::puts(const char *s) {
+    lock();
+    fflush(_file);
+    int ret = std::fputs(s, _file);
+    unlock();
+    return ret;
+}
+int Stream::getc() {
+    lock();
+    fflush(_file);
+    int ret = mbed_getc(_file);
+    unlock();
+    return ret;
+}
+char* Stream::gets(char *s, int size) {
+    lock();
+    fflush(_file);
+    char *ret = mbed_gets(s,size,_file);
+    unlock();
+    return ret;
+}
+
+int Stream::close() {
+    return 0;
+}
+
+ssize_t Stream::write(const void* buffer, size_t length) {
+    const char* ptr = (const char*)buffer;
+    const char* end = ptr + length;
+
+    lock();
+    while (ptr != end) {
+        if (_putc(*ptr++) == EOF) {
+            break;
+        }
+    }
+    unlock();
+
+    return ptr - (const char*)buffer;
+}
+
+ssize_t Stream::read(void* buffer, size_t length) {
+    char* ptr = (char*)buffer;
+    char* end = ptr + length;
+
+    lock();
+    while (ptr != end) {
+        int c = _getc();
+        if (c==EOF) break;
+        *ptr++ = c;
+    }
+    unlock();
+
+    return ptr - (const char*)buffer;
+}
+
+off_t Stream::lseek(off_t offset, int whence) {
+    return 0;
+}
+
+int Stream::isatty() {
+    return 0;
+}
+
+int Stream::fsync() {
+    return 0;
+}
+
+off_t Stream::flen() {
+    return 0;
+}
+
+int Stream::printf(const char* format, ...) {
+    lock();
+    std::va_list arg;
+    va_start(arg, format);
+    fflush(_file);
+    int r = vfprintf(_file, format, arg);
+    va_end(arg);
+    unlock();
+    return r;
+}
+
+int Stream::scanf(const char* format, ...) {
+    lock();
+    std::va_list arg;
+    va_start(arg, format);
+    fflush(_file);
+    int r = vfscanf(_file, format, arg);
+    va_end(arg);
+    unlock();
+    return r;
+}
+
+int Stream::vprintf(const char* format, std::va_list args) {
+    lock();
+    fflush(_file);
+    int r = vfprintf(_file, format, args);
+    unlock();
+    return r;
+}
+
+int Stream::vscanf(const char* format, std::va_list args) {
+    lock();
+    fflush(_file);
+    int r = vfscanf(_file, format, args);
+    unlock();
+    return r;
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/Ticker.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ticker.h"
+
+#include "TimerEvent.h"
+#include "FunctionPointer.h"
+#include "ticker_api.h"
+#include "critical.h"
+
+namespace mbed {
+
+void Ticker::detach() {
+    core_util_critical_section_enter();
+    remove();
+    _function.attach(0);
+    core_util_critical_section_exit();
+}
+
+void Ticker::setup(timestamp_t t) {
+    core_util_critical_section_enter();
+    remove();
+    _delay = t;
+    insert(_delay + ticker_read(_ticker_data));
+    core_util_critical_section_exit();
+}
+
+void Ticker::handler() {
+    insert(event.timestamp + _delay);
+    _function.call();
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/Timeout.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,25 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timeout.h"
+
+namespace mbed {
+
+void Timeout::handler() {
+    _function.call();
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/Timer.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,84 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timer.h"
+#include "ticker_api.h"
+#include "us_ticker_api.h"
+#include "critical.h"
+
+namespace mbed {
+
+Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data()) {
+    reset();
+}
+
+Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data) {
+    reset();
+}
+
+void Timer::start() {
+    core_util_critical_section_enter();
+    if (!_running) {
+        _start = ticker_read(_ticker_data);
+        _running = 1;
+    }
+    core_util_critical_section_exit();
+}
+
+void Timer::stop() {
+    core_util_critical_section_enter();
+    _time += slicetime();
+    _running = 0;
+    core_util_critical_section_exit();
+}
+
+int Timer::read_us() {
+    core_util_critical_section_enter();
+    int time = _time + slicetime();
+    core_util_critical_section_exit();
+    return time;
+}
+
+float Timer::read() {
+    return (float)read_us() / 1000000.0f;
+}
+
+int Timer::read_ms() {
+    return read_us() / 1000;
+}
+
+int Timer::slicetime() {
+    core_util_critical_section_enter();
+    int ret = 0;
+    if (_running) {
+        ret = ticker_read(_ticker_data) - _start;
+    }
+    core_util_critical_section_exit();
+    return ret;
+}
+
+void Timer::reset() {
+    core_util_critical_section_enter();
+    _start = ticker_read(_ticker_data);
+    _time = 0;
+    core_util_critical_section_exit();
+}
+
+Timer::operator float() {
+    return read();
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/TimerEvent.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "TimerEvent.h"
+#include "cmsis.h"
+
+#include <stddef.h>
+#include "ticker_api.h"
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+TimerEvent::TimerEvent() : event(), _ticker_data(get_us_ticker_data()) {
+    ticker_set_handler(_ticker_data, (&TimerEvent::irq));
+}
+
+TimerEvent::TimerEvent(const ticker_data_t *data) : event(), _ticker_data(data) {
+    ticker_set_handler(_ticker_data, (&TimerEvent::irq));
+}
+
+void TimerEvent::irq(uint32_t id) {
+    TimerEvent *timer_event = (TimerEvent*)id;
+    timer_event->handler();
+}
+
+TimerEvent::~TimerEvent() {
+    remove();
+}
+
+// insert in to linked list
+void TimerEvent::insert(timestamp_t timestamp) {
+    ticker_insert_event(_ticker_data, &event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::remove() {
+    ticker_remove_event(_ticker_data, &event);
+}
+
+} // namespace mbed
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_alloc_wrappers.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,330 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_mem_trace.h"
+#include "mbed_stats.h"
+#include "toolchain.h"
+#include "SingletonPtr.h"
+#include "PlatformMutex.h"
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+/* There are two memory tracers in mbed OS:
+
+- the first can be used to detect the maximum heap usage at runtime. It is
+  activated by defining the MBED_HEAP_STATS_ENABLED macro.
+- the second can be used to trace each memory call by automatically invoking
+  a callback on each memory operation (see hal/api/mbed_mem_trace.h). It is
+  activated by defining the MBED_MEM_TRACING_ENABLED macro.
+
+Both tracers can be activated and deactivated in any combination. If both tracers
+are active, the second one (MBED_MEM_TRACING_ENABLED) will trace the first one's
+(MBED_HEAP_STATS_ENABLED) memory calls.*/
+
+/******************************************************************************/
+/* Implementation of the runtime max heap usage checker                       */
+/******************************************************************************/
+
+/* Size must be a multiple of 8 to keep alignment */
+typedef struct {
+    uint32_t size;
+    uint32_t pad;
+} alloc_info_t;
+
+static SingletonPtr<PlatformMutex> malloc_stats_mutex;
+static SingletonPtr<PlatformMutex> mem_trace_mutex;
+static mbed_stats_heap_t heap_stats = {0, 0, 0, 0, 0};
+
+void mbed_stats_heap_get(mbed_stats_heap_t *stats)
+{
+    malloc_stats_mutex->lock();
+    memcpy(stats, &heap_stats, sizeof(mbed_stats_heap_t));
+    malloc_stats_mutex->unlock();
+}
+
+/******************************************************************************/
+/* GCC memory allocation wrappers                                             */
+/******************************************************************************/
+
+#if defined(TOOLCHAIN_GCC)
+
+#ifdef   FEATURE_UVISOR
+#include "uvisor-lib/uvisor-lib.h"
+#endif/* FEATURE_UVISOR */
+
+// TODO: memory tracing doesn't work with uVisor enabled.
+#if !defined(FEATURE_UVISOR)
+
+extern "C" {
+    void * __real__malloc_r(struct _reent * r, size_t size);
+    void * __real__realloc_r(struct _reent * r, void * ptr, size_t size);
+    void __real__free_r(struct _reent * r, void * ptr);
+    void* __real__calloc_r(struct _reent * r, size_t nmemb, size_t size);
+}
+
+extern "C" void * __wrap__malloc_r(struct _reent * r, size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = (alloc_info_t*)__real__malloc_r(r, size + sizeof(alloc_info_t));
+    if (alloc_info != NULL) {
+        alloc_info->size = size;
+        ptr = (void*)(alloc_info + 1);
+        heap_stats.current_size += size;
+        heap_stats.total_size += size;
+        heap_stats.alloc_cnt += 1;
+        if (heap_stats.current_size > heap_stats.max_size) {
+            heap_stats.max_size = heap_stats.current_size;
+        }
+    } else {
+        heap_stats.alloc_fail_cnt += 1;
+    }
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = __real__malloc_r(r, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+extern "C" void * __wrap__realloc_r(struct _reent * r, void * ptr, size_t size) {
+    void *new_ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Implement realloc_r with malloc and free.
+    // The function realloc_r can't be used here directly since
+    // it can call into __wrap__malloc_r (returns ptr + 4) or
+    // resize memory directly (returns ptr + 0).
+
+    // Note - no lock needed since malloc and free are thread safe
+
+    // Get old size
+    uint32_t old_size = 0;
+    if (ptr != NULL) {
+        alloc_info_t *alloc_info = ((alloc_info_t*)ptr) - 1;
+        old_size = alloc_info->size;
+    }
+
+    // Allocate space
+    if (size != 0) {
+        new_ptr = malloc(size);
+    }
+
+    // If the new buffer has been allocated copy the data to it
+    // and free the old buffer
+    if (new_ptr != NULL) {
+        uint32_t copy_size = (old_size < size) ? old_size : size;
+        memcpy(new_ptr, (void*)ptr, copy_size);
+        free(ptr);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    new_ptr = __real__realloc_r(r, ptr, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return new_ptr;
+}
+
+extern "C" void __wrap__free_r(struct _reent * r, void * ptr) {
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = NULL;
+    if (ptr != NULL) {
+        alloc_info = ((alloc_info_t*)ptr) - 1;
+        heap_stats.current_size -= alloc_info->size;
+        heap_stats.alloc_cnt -= 1;
+    }
+    __real__free_r(r, (void*)alloc_info);
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    __real__free_r(r, ptr);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_free(ptr, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+}
+
+extern "C" void * __wrap__calloc_r(struct _reent * r, size_t nmemb, size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Note - no lock needed since malloc is thread safe
+
+    ptr = malloc(nmemb * size);
+    if (ptr != NULL) {
+        memset(ptr, 0, nmemb * size);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = __real__calloc_r(r, nmemb, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+#endif // if !defined(FEATURE_UVISOR)
+
+/******************************************************************************/
+/* ARMCC memory allocation wrappers                                           */
+/******************************************************************************/
+
+#elif defined(TOOLCHAIN_ARM) // #if defined(TOOLCHAIN_GCC)
+
+/* Enable hooking of memory function only if tracing is also enabled */
+#if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
+
+extern "C" {
+    void *$Super$$malloc(size_t size);
+    void *$Super$$realloc(void *ptr, size_t size);
+    void *$Super$$calloc(size_t nmemb, size_t size);
+    void $Super$$free(void *ptr);
+}
+
+extern "C" void* $Sub$$malloc(size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = (alloc_info_t*)$Super$$malloc(size + sizeof(alloc_info_t));
+    if (alloc_info != NULL) {
+        alloc_info->size = size;
+        ptr = (void*)(alloc_info + 1);
+        heap_stats.current_size += size;
+        heap_stats.total_size += size;
+        heap_stats.alloc_cnt += 1;
+        if (heap_stats.current_size > heap_stats.max_size) {
+            heap_stats.max_size = heap_stats.current_size;
+        }
+    } else {
+        heap_stats.alloc_fail_cnt += 1;
+    }
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = $Super$$malloc(size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_malloc(ptr, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+extern "C" void* $Sub$$realloc(void *ptr, size_t size) {
+    void *new_ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Note - no lock needed since malloc and free are thread safe
+
+    // Get old size
+    uint32_t old_size = 0;
+    if (ptr != NULL) {
+        alloc_info_t *alloc_info = ((alloc_info_t*)ptr) - 1;
+        old_size = alloc_info->size;
+    }
+
+    // Allocate space
+    if (size != 0) {
+        new_ptr = malloc(size);
+    }
+
+    // If the new buffer has been allocated copy the data to it
+    // and free the old buffer
+    if (new_ptr != NULL) {
+        uint32_t copy_size = (old_size < size) ? old_size : size;
+        memcpy(new_ptr, (void*)ptr, copy_size);
+        free(ptr);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    mem_trace_mutex->lock();
+    new_ptr = $Super$$realloc(ptr, size);
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mbed_mem_trace_realloc(new_ptr, ptr, size, MBED_CALLER_ADDR());
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return new_ptr;
+}
+
+extern "C" void *$Sub$$calloc(size_t nmemb, size_t size) {
+    void *ptr = NULL;
+#ifdef MBED_HEAP_STATS_ENABLED
+    // Note - no lock needed since malloc is thread safe
+    ptr = malloc(nmemb * size);
+    if (ptr != NULL) {
+        memset(ptr, 0, nmemb * size);
+    }
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    ptr = $Super$$calloc(nmemb, size);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_calloc(ptr, nmemb, size, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+    return ptr;
+}
+
+extern "C" void $Sub$$free(void *ptr) {
+#ifdef MBED_HEAP_STATS_ENABLED
+    malloc_stats_mutex->lock();
+    alloc_info_t *alloc_info = NULL;
+    if (ptr != NULL) {
+        alloc_info = ((alloc_info_t*)ptr) - 1;
+        heap_stats.current_size -= alloc_info->size;
+        heap_stats.alloc_cnt -= 1;
+    }
+    $Super$$free((void*)alloc_info);
+    malloc_stats_mutex->unlock();
+#else // #ifdef MBED_HEAP_STATS_ENABLED
+    $Super$$free(ptr);
+#endif // #ifdef MBED_HEAP_STATS_ENABLED
+#ifdef MBED_MEM_TRACING_ENABLED
+    mem_trace_mutex->lock();
+    mbed_mem_trace_free(ptr, MBED_CALLER_ADDR());
+    mem_trace_mutex->unlock();
+#endif // #ifdef MBED_MEM_TRACING_ENABLED
+}
+
+#endif // #if defined(MBED_MEM_TRACING_ENABLED) || defined(MBED_HEAP_STATS_ENABLED)
+
+/******************************************************************************/
+/* Allocation wrappers for other toolchains are not supported yet             */
+/******************************************************************************/
+
+#else // #if defined(TOOLCHAIN_GCC)
+
+#ifdef MBED_MEM_TRACING_ENABLED
+#warning Memory tracing is not supported with the current toolchain.
+#endif
+
+#ifdef MBED_HEAP_STATS_ENABLED
+#warning Heap statistics are not supported with the current toolchain.
+#endif
+
+#endif // #if defined(TOOLCHAIN_GCC)
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_assert.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "device.h"
+
+#include "mbed_interface.h"
+#include "critical.h"
+
+void mbed_assert_internal(const char *expr, const char *file, int line)
+{
+    core_util_critical_section_enter();
+    mbed_error_printf("mbed assertation failed: %s, file: %s, line %d \n", expr, file, line);
+    mbed_die();
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_board.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,92 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "gpio_api.h"
+#include "wait_api.h"
+#include "toolchain.h"
+#include "mbed_interface.h"
+#include "critical.h"
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#endif
+
+WEAK void mbed_die(void) {
+#if !defined (NRF51_H) && !defined(TARGET_EFM32)
+    core_util_critical_section_enter();
+#endif
+#if   (DEVICE_ERROR_RED == 1)
+    gpio_t led_red; gpio_init_out(&led_red, LED_RED);
+#elif (DEVICE_ERROR_PATTERN == 1)
+    gpio_t led_1; gpio_init_out(&led_1, LED1);
+    gpio_t led_2; gpio_init_out(&led_2, LED2);
+    gpio_t led_3; gpio_init_out(&led_3, LED3);
+    gpio_t led_4; gpio_init_out(&led_4, LED4);
+#endif
+
+    while (1) {
+#if   (DEVICE_ERROR_RED == 1)
+        gpio_write(&led_red, 1);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+        gpio_write(&led_1, 1);
+        gpio_write(&led_2, 0);
+        gpio_write(&led_3, 0);
+        gpio_write(&led_4, 1);
+#endif
+
+        wait_ms(150);
+
+#if   (DEVICE_ERROR_RED == 1)
+        gpio_write(&led_red, 0);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+        gpio_write(&led_1, 0);
+        gpio_write(&led_2, 1);
+        gpio_write(&led_3, 1);
+        gpio_write(&led_4, 0);
+#endif
+
+        wait_ms(150);
+    }
+}
+
+void mbed_error_printf(const char* format, ...) {
+    va_list arg;
+    va_start(arg, format);
+    mbed_error_vfprintf(format, arg);
+    va_end(arg);
+}
+
+void mbed_error_vfprintf(const char * format, va_list arg) {
+#if DEVICE_SERIAL
+    core_util_critical_section_enter();
+    char buffer[128];
+    int size = vsprintf(buffer, format, arg);
+    if (size > 0) {
+        if (!stdio_uart_inited) {
+        serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+        }
+        for (int i = 0; i < size; i++) {
+            serial_putc(&stdio_uart, buffer[i]);
+        }
+    }
+    core_util_critical_section_exit();
+#endif
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_critical.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "critical.h"
+
+#include "cmsis.h"
+#include "mbed_assert.h"
+
+#define EXCLUSIVE_ACCESS (!defined (__CORTEX_M0) && !defined (__CORTEX_M0PLUS))
+
+static volatile uint32_t interrupt_enable_counter = 0;
+static volatile bool critical_interrupts_disabled = false;
+
+bool core_util_are_interrupts_enabled(void)
+{
+#if defined(__CORTEX_A9)
+    return ((__get_CPSR() & 0x80) == 0);
+#else
+    return ((__get_PRIMASK() & 0x1) == 0);
+#endif
+}
+
+void core_util_critical_section_enter(void)
+{
+    bool interrupts_disabled = !core_util_are_interrupts_enabled();
+    __disable_irq();
+
+    /* Save the interrupt disabled state as it was prior to any nested critical section lock use */
+    if (!interrupt_enable_counter) {
+        critical_interrupts_disabled = interrupts_disabled;
+    }
+
+    /* If the interrupt_enable_counter overflows or we are in a nested critical section and interrupts
+       are enabled, then something has gone badly wrong thus assert an error.
+    */
+    MBED_ASSERT(interrupt_enable_counter < UINT32_MAX); 
+// FIXME
+#ifndef   FEATURE_UVISOR
+    if (interrupt_enable_counter > 0) {
+        MBED_ASSERT(interrupts_disabled);
+    }
+#else
+#warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
+#endif /* FEATURE_UVISOR */
+    interrupt_enable_counter++;
+}
+
+void core_util_critical_section_exit(void)
+{
+    /* If critical_section_enter has not previously been called, do nothing */
+    if (interrupt_enable_counter) {
+
+// FIXME
+#ifndef   FEATURE_UVISOR
+        bool interrupts_disabled = !core_util_are_interrupts_enabled(); /* get the current interrupt disabled state */
+
+        MBED_ASSERT(interrupts_disabled); /* Interrupts must be disabled on invoking an exit from a critical section */
+#else
+#warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
+#endif /* FEATURE_UVISOR */
+
+        interrupt_enable_counter--;
+
+        /* Only re-enable interrupts if we are exiting the last of the nested critical sections and
+           interrupts were enabled on entry to the first critical section.
+        */
+        if (!interrupt_enable_counter && !critical_interrupts_disabled) {
+            __enable_irq();
+        }
+    }
+}
+
+#if EXCLUSIVE_ACCESS
+
+bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+{
+    uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr);
+    if (currentValue != *expectedCurrentValue) {
+        *expectedCurrentValue = currentValue;
+        __CLREX();
+        return false;
+    }
+
+    return !__STREXB(desiredValue, (volatile uint8_t*)ptr);
+}
+
+bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+{
+    uint16_t currentValue = __LDREXH((volatile uint16_t*)ptr);
+    if (currentValue != *expectedCurrentValue) {
+        *expectedCurrentValue = currentValue;
+        __CLREX();
+        return false;
+    }
+
+    return !__STREXH(desiredValue, (volatile uint16_t*)ptr);
+}
+
+
+bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+{
+    uint32_t currentValue = __LDREXW((volatile uint32_t*)ptr);
+    if (currentValue != *expectedCurrentValue) {
+        *expectedCurrentValue = currentValue;
+        __CLREX();
+        return false;
+    }
+
+    return !__STREXW(desiredValue, (volatile uint32_t*)ptr);
+}
+
+uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+    uint8_t newValue;
+    do {
+        newValue = __LDREXB((volatile uint8_t*)valuePtr) + delta;
+    } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
+    return newValue;
+}
+
+uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+    uint16_t newValue;
+    do {
+        newValue = __LDREXH((volatile uint16_t*)valuePtr) + delta;
+    } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
+    return newValue;
+}
+
+uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+    uint32_t newValue;
+    do {
+        newValue = __LDREXW((volatile uint32_t*)valuePtr) + delta;
+    } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
+    return newValue;
+}
+
+
+uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+    uint8_t newValue;
+    do {
+        newValue = __LDREXB((volatile uint8_t*)valuePtr) - delta;
+    } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
+    return newValue;
+}
+
+uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+    uint16_t newValue;
+    do {
+        newValue = __LDREXH((volatile uint16_t*)valuePtr) - delta;
+    } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
+    return newValue;
+}
+
+uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+    uint32_t newValue;
+    do {
+        newValue = __LDREXW((volatile uint32_t*)valuePtr) - delta;
+    } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
+    return newValue;
+}
+
+#else
+
+bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+{
+    bool success;
+    uint8_t currentValue;
+    core_util_critical_section_enter();
+    currentValue = *ptr;
+    if (currentValue == *expectedCurrentValue) {
+        *ptr = desiredValue;
+        success = true;
+    } else {
+        *expectedCurrentValue = currentValue;
+        success = false;
+    }
+    core_util_critical_section_exit();
+    return success;
+}
+
+bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+{
+    bool success;
+    uint16_t currentValue;
+    core_util_critical_section_enter();
+    currentValue = *ptr;
+    if (currentValue == *expectedCurrentValue) {
+        *ptr = desiredValue;
+        success = true;
+    } else {
+        *expectedCurrentValue = currentValue;
+        success = false;
+    }
+    core_util_critical_section_exit();
+    return success;
+}
+
+
+bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+{
+    bool success;
+    uint32_t currentValue;
+    core_util_critical_section_enter();
+    currentValue = *ptr;
+    if (currentValue == *expectedCurrentValue) {
+        *ptr = desiredValue;
+        success = true;
+    } else {
+        *expectedCurrentValue = currentValue;
+        success = false;
+    }
+    core_util_critical_section_exit();
+    return success;
+}
+
+
+uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+    uint8_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr + delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+    uint16_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr + delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+    uint32_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr + delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+
+uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
+{
+    uint8_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr - delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
+{
+    uint16_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr - delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
+{
+    uint32_t newValue;
+    core_util_critical_section_enter();
+    newValue = *valuePtr - delta;
+    *valuePtr = newValue;
+    core_util_critical_section_exit();
+    return newValue;
+}
+
+#endif
+
+
+bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue) {
+    return core_util_atomic_cas_u32(
+            (uint32_t *)ptr,
+            (uint32_t *)expectedCurrentValue,
+            (uint32_t)desiredValue);
+}
+
+void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta) {
+    return (void *)core_util_atomic_incr_u32((uint32_t *)valuePtr, (uint32_t)delta);
+}
+
+void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta) {
+    return (void *)core_util_atomic_decr_u32((uint32_t *)valuePtr, (uint32_t)delta);
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_error.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+#include "mbed_interface.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+WEAK void error(const char* format, ...) {
+    va_list arg;
+    va_start(arg, format);
+    mbed_error_vfprintf(format, arg);
+    va_end(arg);
+    exit(1);
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_gpio.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,62 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+
+static inline void _gpio_init_in(gpio_t* gpio, PinName pin, PinMode mode)
+{
+    gpio_init(gpio, pin);
+    if (pin != NC) {
+        gpio_dir(gpio, PIN_INPUT);
+        gpio_mode(gpio, mode);
+    }
+}
+
+static inline void _gpio_init_out(gpio_t* gpio, PinName pin, PinMode mode, int value)
+{
+    gpio_init(gpio, pin);
+    if (pin != NC) {
+        gpio_write(gpio, value);
+        gpio_dir(gpio, PIN_OUTPUT);
+        gpio_mode(gpio, mode);
+    }
+}
+
+void gpio_init_in(gpio_t* gpio, PinName pin) {
+    gpio_init_in_ex(gpio, pin, PullDefault);
+}
+
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) {
+    _gpio_init_in(gpio, pin, mode);
+}
+
+void gpio_init_out(gpio_t* gpio, PinName pin) {
+    gpio_init_out_ex(gpio, pin, 0);
+}
+
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) {
+    _gpio_init_out(gpio, pin, PullNone, value);
+}
+
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) {
+    if (direction == PIN_INPUT) {
+        _gpio_init_in(gpio, pin, mode);
+        if (pin != NC)
+            gpio_write(gpio, value); // we prepare the value in case it is switched later
+    } else {
+        _gpio_init_out(gpio, pin, mode, value);
+    }
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_interface.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "mbed_interface.h"
+
+#include "gpio_api.h"
+#include "wait_api.h"
+#include "semihost_api.h"
+#include "mbed_error.h"
+#include "toolchain.h"
+
+#if DEVICE_SEMIHOST
+
+// return true if a debugger is attached, indicating mbed interface is connected
+int mbed_interface_connected(void) {
+    return semihost_connected();
+}
+
+int mbed_interface_reset(void) {
+    if (mbed_interface_connected()) {
+        semihost_reset();
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+WEAK int mbed_interface_uid(char *uid) {
+    if (mbed_interface_connected()) {
+        return semihost_uid(uid); // Returns 0 if successful, -1 on failure
+    } else {
+        uid[0] = 0;
+        return -1;
+    }
+}
+
+int mbed_interface_disconnect(void) {
+    int res;
+    if (mbed_interface_connected()) {
+        if ((res = semihost_disabledebug()) != 0)
+            return res;
+        while (mbed_interface_connected());
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+int mbed_interface_powerdown(void) {
+    int res;
+    if (mbed_interface_connected()) {
+        if ((res = semihost_powerdown()) != 0)
+            return res;
+        while (mbed_interface_connected());
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+// for backward compatibility
+void mbed_reset(void) {
+    mbed_interface_reset();
+}
+
+WEAK int mbed_uid(char *uid) {
+    return mbed_interface_uid(uid);
+}
+#endif
+
+WEAK void mbed_mac_address(char *mac) {
+#if DEVICE_SEMIHOST
+    char uid[DEVICE_ID_LENGTH + 1];
+    int i;
+
+    // if we have a UID, extract the MAC
+    if (mbed_interface_uid(uid) == 0) {
+        char *p = uid;
+#if defined(DEVICE_MAC_OFFSET)
+        p += DEVICE_MAC_OFFSET;
+#endif
+        for (i=0; i<6; i++) {
+            int byte;
+            sscanf(p, "%2x", &byte);
+            mac[i] = byte;
+            p += 2;
+        }
+        mac[0] &= ~0x01;    // reset the IG bit in the address; see IEE 802.3-2002, Section 3.2.3(b)
+    } else {  // else return a default MAC
+#endif
+        mac[0] = 0x00;
+        mac[1] = 0x02;
+        mac[2] = 0xF7;
+        mac[3] = 0xF0;
+        mac[4] = 0x00;
+        mac[5] = 0x00;
+#if DEVICE_SEMIHOST
+    }
+#endif
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_lp_ticker_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "lp_ticker_api.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+static ticker_event_queue_t events;
+
+static const ticker_interface_t lp_interface = {
+    .init = lp_ticker_init,
+    .read = lp_ticker_read,
+    .disable_interrupt = lp_ticker_disable_interrupt,
+    .clear_interrupt = lp_ticker_clear_interrupt,
+    .set_interrupt = lp_ticker_set_interrupt,
+};
+
+static const ticker_data_t lp_data = {
+    .interface = &lp_interface,
+    .queue = &events,
+};
+
+const ticker_data_t* get_lp_ticker_data(void)
+{
+    return &lp_data;
+}
+
+void lp_ticker_irq_handler(void)
+{
+    ticker_irq_handler(&lp_data);
+}
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_mem_trace.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdlib.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include "mbed_mem_trace.h"
+#include "critical.h"
+
+/******************************************************************************
+ * Internal variables, functions and helpers
+ *****************************************************************************/
+
+/* The callback function that will be called after a traced memory operations finishes. */
+static mbed_mem_trace_cb_t mem_trace_cb;
+/* 'trave_level' guards "trace inside trace" situations (for example, the implementation
+ * of realloc() might call malloc() internally, and since malloc() is also traced, this could
+ * result in two calls to the callback function instead of one. */
+static uint8_t trace_level;
+
+/******************************************************************************
+ * Public interface
+ *****************************************************************************/
+
+void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb) {
+    mem_trace_cb = cb;
+}
+
+void *mbed_mem_trace_malloc(void *res, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_MALLOC, res, caller, size);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+    return res;
+}
+
+void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+    return res;
+}
+
+void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_CALLOC, res, caller, num, size);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+    return res;
+}
+
+void mbed_mem_trace_free(void *ptr, void *caller) {
+    if (mem_trace_cb) {
+        if (core_util_atomic_incr_u8(&trace_level, 1) == 1) {
+            mem_trace_cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr);
+        }
+        core_util_atomic_decr_u8(&trace_level, 1);
+    }
+}
+
+void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...) {
+    va_list va;
+    size_t temp_s1, temp_s2;
+    void *temp_ptr;
+
+    va_start(va, caller);
+    switch(op) {
+        case MBED_MEM_TRACE_MALLOC:
+            temp_s1 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "m:%p;%p-%u\n", res, caller, temp_s1);
+            break;
+
+        case MBED_MEM_TRACE_REALLOC:
+            temp_ptr = va_arg(va, void*);
+            temp_s1 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "r:%p;%p-%p;%u\n", res, caller, temp_ptr, temp_s1);
+            break;
+
+        case MBED_MEM_TRACE_CALLOC:
+            temp_s1 = va_arg(va, size_t);
+            temp_s2 = va_arg(va, size_t);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "c:%p;%p-%u;%u\n", res, caller, temp_s1, temp_s2);
+            break;
+
+        case MBED_MEM_TRACE_FREE:
+            temp_ptr = va_arg(va, void*);
+            printf(MBED_MEM_DEFAULT_TRACER_PREFIX "f:%p;%p-%p\n", res, caller, temp_ptr);
+            break;
+
+        default:
+            printf("?\n");
+    }
+    va_end(va);
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_pinmap_common.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "mbed_error.h"
+
+void pinmap_pinout(PinName pin, const PinMap *map) {
+    if (pin == NC)
+        return;
+
+    while (map->pin != NC) {
+        if (map->pin == pin) {
+            pin_function(pin, map->function);
+
+            pin_mode(pin, PullNone);
+            return;
+        }
+        map++;
+    }
+    error("could not pinout");
+}
+
+uint32_t pinmap_merge(uint32_t a, uint32_t b) {
+    // both are the same (inc both NC)
+    if (a == b)
+        return a;
+
+    // one (or both) is not connected
+    if (a == (uint32_t)NC)
+        return b;
+    if (b == (uint32_t)NC)
+        return a;
+
+    // mis-match error case
+    error("pinmap mis-match");
+    return (uint32_t)NC;
+}
+
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
+    while (map->pin != NC) {
+        if (map->pin == pin)
+            return map->peripheral;
+        map++;
+    }
+    return (uint32_t)NC;
+}
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
+    uint32_t peripheral = (uint32_t)NC;
+
+    if (pin == (PinName)NC)
+        return (uint32_t)NC;
+    peripheral = pinmap_find_peripheral(pin, map);
+    if ((uint32_t)NC == peripheral) // no mapping available
+        error("pinmap not found for peripheral");
+    return peripheral;
+}
+
+uint32_t pinmap_find_function(PinName pin, const PinMap* map) {
+    while (map->pin != NC) {
+        if (map->pin == pin)
+            return map->function;
+        map++;
+    }
+    return (uint32_t)NC;
+}
+
+uint32_t pinmap_function(PinName pin, const PinMap* map) {
+    uint32_t function = (uint32_t)NC;
+
+    if (pin == (PinName)NC)
+        return (uint32_t)NC;
+    function = pinmap_find_function(pin, map);
+    if ((uint32_t)NC == function) // no mapping available
+        error("pinmap not found for function");
+    return function;
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_rtc_time.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+#include <time.h>
+#include "critical.h"
+#include "rtc_time.h"
+#include "us_ticker_api.h"
+#include "SingletonPtr.h"
+#include "PlatformMutex.h"
+
+static SingletonPtr<PlatformMutex> _mutex;
+
+#if DEVICE_RTC
+static void (*_rtc_init)(void) = rtc_init;
+static int (*_rtc_isenabled)(void) = rtc_isenabled;
+static time_t (*_rtc_read)(void) = rtc_read;
+static void (*_rtc_write)(time_t t) = rtc_write;
+#else
+static void (*_rtc_init)(void) = NULL;
+static int (*_rtc_isenabled)(void) = NULL;
+static time_t (*_rtc_read)(void) = NULL;
+static void (*_rtc_write)(time_t t) = NULL;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if defined (__ICCARM__)
+time_t __time32(time_t *timer)
+#else
+time_t time(time_t *timer)
+#endif
+
+{
+    _mutex->lock();
+    if (_rtc_isenabled != NULL) {
+        if (!(_rtc_isenabled())) {
+            set_time(0);
+        }
+    }
+    
+    time_t t = 0;
+    if (_rtc_read != NULL) {
+        t = _rtc_read();
+    }
+
+    if (timer != NULL) {
+        *timer = t;
+    }
+    _mutex->unlock();
+    return t;
+}
+
+void set_time(time_t t) {
+    _mutex->lock();
+    if (_rtc_init != NULL) {
+        _rtc_init();
+    }
+    if (_rtc_write != NULL) {
+        _rtc_write(t);
+    }
+    _mutex->unlock();
+}
+
+clock_t clock() {
+    _mutex->lock();
+    clock_t t = us_ticker_read();
+    t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
+    _mutex->unlock();
+    return t;
+}
+
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) {
+    _mutex->lock();
+    _rtc_read = read_rtc;
+    _rtc_write = write_rtc;
+    _rtc_init = init_rtc;
+    _rtc_isenabled = isenabled_rtc;
+    _mutex->unlock();
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_semihost_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,163 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#include "semihost_api.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#if DEVICE_SEMIHOST
+
+// ARM Semihosting Commands
+#define SYS_OPEN   (0x1)
+#define SYS_CLOSE  (0x2)
+#define SYS_WRITE  (0x5)
+#define SYS_READ   (0x6)
+#define SYS_ISTTY  (0x9)
+#define SYS_SEEK   (0xa)
+#define SYS_ENSURE (0xb)
+#define SYS_FLEN   (0xc)
+#define SYS_REMOVE (0xe)
+#define SYS_RENAME (0xf)
+#define SYS_EXIT   (0x18)
+
+// mbed Semihosting Commands
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) // 0x100 - 0x1ff
+#define USR_XFFIND      (RESERVED_FOR_USER_APPLICATIONS + 0)
+#define USR_UID      (RESERVED_FOR_USER_APPLICATIONS + 1)
+#define USR_RESET     (RESERVED_FOR_USER_APPLICATIONS + 2)
+#define USR_VBUS     (RESERVED_FOR_USER_APPLICATIONS + 3)
+#define USR_POWERDOWN     (RESERVED_FOR_USER_APPLICATIONS + 4)
+#define USR_DISABLEDEBUG (RESERVED_FOR_USER_APPLICATIONS + 5)
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode) {
+    uint32_t args[3];
+    args[0] = (uint32_t)name;
+    args[1] = (uint32_t)openmode;
+    args[2] = (uint32_t)strlen(name);
+    return __semihost(SYS_OPEN, args);
+}
+
+int semihost_close(FILEHANDLE fh) {
+    return __semihost(SYS_CLOSE, &fh);
+}
+
+int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode) {
+    if (length == 0) return 0;
+
+    uint32_t args[3];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)buffer;
+    args[2] = (uint32_t)length;
+    return __semihost(SYS_WRITE, args);
+}
+
+int semihost_read(FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode) {
+    uint32_t args[3];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)buffer;
+    args[2] = (uint32_t)length;
+    return __semihost(SYS_READ, args);
+}
+
+int semihost_istty(FILEHANDLE fh) {
+    return __semihost(SYS_ISTTY, &fh);
+}
+
+int semihost_seek(FILEHANDLE fh, long position) {
+    uint32_t args[2];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)position;
+    return __semihost(SYS_SEEK, args);
+}
+
+int semihost_ensure(FILEHANDLE fh) {
+    return __semihost(SYS_ENSURE, &fh);
+}
+
+long semihost_flen(FILEHANDLE fh) {
+    return __semihost(SYS_FLEN, &fh);
+}
+
+int semihost_remove(const char *name) {
+    uint32_t args[2];
+    args[0] = (uint32_t)name;
+    args[1] = (uint32_t)strlen(name);
+    return __semihost(SYS_REMOVE, args);
+}
+
+int semihost_rename(const char *old_name, const char *new_name) {
+    uint32_t args[4];
+    args[0] = (uint32_t)old_name;
+    args[1] = (uint32_t)strlen(old_name);
+    args[0] = (uint32_t)new_name;
+    args[1] = (uint32_t)strlen(new_name);
+    return __semihost(SYS_RENAME, args);
+}
+#endif
+
+int semihost_exit(void) {
+    uint32_t args[4];
+    return __semihost(SYS_EXIT, args);
+}
+
+int semihost_uid(char *uid) {
+    uint32_t args[2];
+    args[0] = (uint32_t)uid;
+    args[1] = DEVICE_ID_LENGTH + 1;
+    return __semihost(USR_UID, &args);
+}
+
+int semihost_reset(void) {
+    // Does not normally return, however if used with older firmware versions
+    // that do not support this call it will return -1.
+    return __semihost(USR_RESET, NULL);
+}
+
+int semihost_vbus(void) {
+    return __semihost(USR_VBUS, NULL);
+}
+
+int semihost_powerdown(void) {
+    return __semihost(USR_POWERDOWN, NULL);
+}
+
+#if DEVICE_DEBUG_AWARENESS
+
+int semihost_connected(void) {
+    return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0;
+}
+
+#else
+// These processors cannot know if the interface is connect, assume so:
+static int is_debugger_attached = 1;
+
+int semihost_connected(void) {
+    return is_debugger_attached;
+}
+#endif
+
+int semihost_disabledebug(void) {
+#if !(DEVICE_DEBUG_AWARENESS)
+    is_debugger_attached = 0;
+#endif
+    return __semihost(USR_DISABLEDEBUG, NULL);
+}
+
+#endif
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_ticker_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,136 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "ticker_api.h"
+#include "critical.h"
+
+void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler) {
+    data->interface->init();
+
+    data->queue->event_handler = handler;
+}
+
+void ticker_irq_handler(const ticker_data_t *const data) {
+    data->interface->clear_interrupt();
+
+    /* Go through all the pending TimerEvents */
+    while (1) {
+        if (data->queue->head == NULL) {
+            // There are no more TimerEvents left, so disable matches.
+            data->interface->disable_interrupt();
+            return;
+        }
+
+        if ((int)(data->queue->head->timestamp - data->interface->read()) <= 0) {
+            // This event was in the past:
+            //      point to the following one and execute its handler
+            ticker_event_t *p = data->queue->head;
+            data->queue->head = data->queue->head->next;
+            if (data->queue->event_handler != NULL) {
+                (*data->queue->event_handler)(p->id); // NOTE: the handler can set new events
+            }
+            /* Note: We continue back to examining the head because calling the
+             * event handler may have altered the chain of pending events. */
+        } else {
+            // This event and the following ones in the list are in the future:
+            //      set it as next interrupt and return
+            data->interface->set_interrupt(data->queue->head->timestamp);
+            return;
+        }
+    }
+}
+
+void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id) {
+    /* disable interrupts for the duration of the function */
+    core_util_critical_section_enter();
+
+    // initialise our data
+    obj->timestamp = timestamp;
+    obj->id = id;
+
+    /* Go through the list until we either reach the end, or find
+       an element this should come before (which is possibly the
+       head). */
+    ticker_event_t *prev = NULL, *p = data->queue->head;
+    while (p != NULL) {
+        /* check if we come before p */
+        if ((int)(timestamp - p->timestamp) < 0) {
+            break;
+        }
+        /* go to the next element */
+        prev = p;
+        p = p->next;
+    }
+    /* if prev is NULL we're at the head */
+    if (prev == NULL) {
+        data->queue->head = obj;
+        data->interface->set_interrupt(timestamp);
+    } else {
+        prev->next = obj;
+    }
+    /* if we're at the end p will be NULL, which is correct */
+    obj->next = p;
+
+    core_util_critical_section_exit();
+}
+
+void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj) {
+    core_util_critical_section_enter();
+
+    // remove this object from the list
+    if (data->queue->head == obj) {
+        // first in the list, so just drop me
+        data->queue->head = obj->next;
+        if (data->queue->head == NULL) {
+            data->interface->disable_interrupt();
+        } else {
+            data->interface->set_interrupt(data->queue->head->timestamp);
+        }
+    } else {
+        // find the object before me, then drop me
+        ticker_event_t* p = data->queue->head;
+        while (p != NULL) {
+            if (p->next == obj) {
+                p->next = obj->next;
+                break;
+            }
+            p = p->next;
+        }
+    }
+
+    core_util_critical_section_exit();
+}
+
+timestamp_t ticker_read(const ticker_data_t *const data)
+{
+    return data->interface->read();
+}
+
+int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp)
+{
+    int ret = 0;
+
+    /* if head is NULL, there are no pending events */
+    core_util_critical_section_enter();
+    if (data->queue->head != NULL) {
+        *timestamp = data->queue->head->timestamp;
+        ret = 1;
+    }
+    core_util_critical_section_exit();
+
+    return ret;
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_us_ticker_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "us_ticker_api.h"
+
+static ticker_event_queue_t events;
+
+static const ticker_interface_t us_interface = {
+    .init = us_ticker_init,
+    .read = us_ticker_read,
+    .disable_interrupt = us_ticker_disable_interrupt,
+    .clear_interrupt = us_ticker_clear_interrupt,
+    .set_interrupt = us_ticker_set_interrupt,
+};
+
+static const ticker_data_t us_data = {
+    .interface = &us_interface,
+    .queue = &events,
+};
+
+const ticker_data_t* get_us_ticker_data(void)
+{
+    return &us_data;
+}
+
+void us_ticker_irq_handler(void)
+{
+    ticker_irq_handler(&us_data);
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_wait_api_no_rtos.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// This implementation of the wait functions will be compiled only
+// if the RTOS is not present.
+#ifndef MBED_CONF_RTOS_PRESENT
+
+#include "wait_api.h"
+#include "us_ticker_api.h"
+
+void wait(float s) {
+    wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms) {
+    wait_us(ms * 1000);
+}
+
+void wait_us(int us) {
+    uint32_t start = us_ticker_read();
+    while ((us_ticker_read() - start) < (uint32_t)us);
+}
+
+#endif // #ifndef MBED_CONF_RTOS_PRESENT
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/mbed_wait_api_rtos.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+// This implementation of the wait functions will be compiled only
+// if the RTOS is present.
+#ifdef MBED_CONF_RTOS_PRESENT
+
+#include "wait_api.h"
+#include "us_ticker_api.h"
+#include "rtos.h"
+#include "critical.h"
+
+void wait(float s) {
+    wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms) {
+    wait_us(ms * 1000);
+}
+
+void wait_us(int us) {
+    uint32_t start = us_ticker_read();
+    // Use the RTOS to wait for millisecond delays if possible
+    int ms = us / 1000;
+    if ((ms > 0) && core_util_are_interrupts_enabled()) {
+        Thread::wait((uint32_t)ms);
+        us -= ms * 1000;
+    }
+    // Use busy waiting for sub-millisecond delays, or for the whole
+    // interval if interrupts are not enabled
+    if (us > 0) {
+        while((us_ticker_read() - start) < (uint32_t)us);
+    }
+}
+
+#endif // #if MBED_CONF_RTOS_PRESENT
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/common/retarget.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,748 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform.h"
+#include "FileHandle.h"
+#include "FileSystemLike.h"
+#include "FilePath.h"
+#include "serial_api.h"
+#include "toolchain.h"
+#include "semihost_api.h"
+#include "mbed_interface.h"
+#include "SingletonPtr.h"
+#include "PlatformMutex.h"
+#include "mbed_error.h"
+#include "mbed_stats.h"
+#include <stdlib.h>
+#include <string.h>
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+#include <errno.h>
+
+#if defined(__ARMCC_VERSION)
+#   include <rt_sys.h>
+#   define PREFIX(x)    _sys##x
+#   define OPEN_MAX     _SYS_OPEN
+#   ifdef __MICROLIB
+#       pragma import(__use_full_stdio)
+#   endif
+
+#elif defined(__ICCARM__)
+#   include <yfuns.h>
+#   define PREFIX(x)        _##x
+#   define OPEN_MAX         16
+
+#   define STDIN_FILENO     0
+#   define STDOUT_FILENO    1
+#   define STDERR_FILENO    2
+
+#else
+#   include <sys/stat.h>
+#   include <sys/unistd.h>
+#   include <sys/syslimits.h>
+#   define PREFIX(x)    x
+#endif
+
+#define FILE_HANDLE_RESERVED    0xFFFFFFFF
+
+using namespace mbed;
+
+#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+// Before version 5.03, we were using a patched version of microlib with proper names
+extern const char __stdin_name[]  = ":tt";
+extern const char __stdout_name[] = ":tt";
+extern const char __stderr_name[] = ":tt";
+
+#else
+extern const char __stdin_name[]  = "/stdin";
+extern const char __stdout_name[] = "/stdout";
+extern const char __stderr_name[] = "/stderr";
+#endif
+
+// Heap limits - only used if set
+unsigned char *mbed_heap_start = 0;
+uint32_t mbed_heap_size = 0;
+
+/* newlib has the filehandle field in the FILE struct as a short, so
+ * we can't just return a Filehandle* from _open and instead have to
+ * put it in a filehandles array and return the index into that array
+ * (or rather index+3, as filehandles 0-2 are stdin/out/err).
+ */
+static FileHandle *filehandles[OPEN_MAX];
+static SingletonPtr<PlatformMutex> filehandle_mutex;
+
+FileHandle::~FileHandle() {
+    filehandle_mutex->lock();
+    /* Remove all open filehandles for this */
+    for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+        if (filehandles[fh_i] == this) {
+            filehandles[fh_i] = NULL;
+        }
+    }
+    filehandle_mutex->unlock();
+}
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#if MBED_CONF_CORE_STDIO_CONVERT_NEWLINES
+static char stdio_in_prev;
+static char stdio_out_prev;
+#endif
+#endif
+
+static void init_serial() {
+#if DEVICE_SERIAL
+    if (stdio_uart_inited) return;
+    serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+#if MBED_CONF_CORE_STDIO_BAUD_RATE
+    serial_baud(&stdio_uart, MBED_CONF_CORE_STDIO_BAUD_RATE);
+#endif
+#endif
+}
+
+static inline int openmode_to_posix(int openmode) {
+    int posix = openmode;
+#ifdef __ARMCC_VERSION
+    if (openmode & OPEN_PLUS) {
+        posix = O_RDWR;
+    } else if(openmode & OPEN_W) {
+        posix = O_WRONLY;
+    } else if(openmode & OPEN_A) {
+        posix = O_WRONLY|O_APPEND;
+    } else {
+        posix = O_RDONLY;
+    }
+    /* a, w, a+, w+ all create if file does not already exist */
+    if (openmode & (OPEN_A|OPEN_W)) {
+        posix |= O_CREAT;
+    }
+    /* w and w+ truncate */
+    if (openmode & OPEN_W) {
+        posix |= O_TRUNC;
+    }
+#elif defined(__ICCARM__)
+    switch (openmode & _LLIO_RDWRMASK) {
+        case _LLIO_RDONLY: posix = O_RDONLY; break;
+        case _LLIO_WRONLY: posix = O_WRONLY; break;
+        case _LLIO_RDWR  : posix = O_RDWR  ; break;
+    }
+    if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
+    if (openmode & _LLIO_APPEND) posix |= O_APPEND;
+    if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
+#elif defined(TOOLCHAIN_GCC)
+    posix &= ~O_BINARY;
+#endif
+    return posix;
+}
+
+extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
+    #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+    // Before version 5.03, we were using a patched version of microlib with proper names
+    // This is the workaround that the microlib author suggested us
+    static int n = 0;
+    if (!std::strcmp(name, ":tt")) return n++;
+
+    #else
+    /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
+     */
+    if (std::strcmp(name, __stdin_name) == 0) {
+        init_serial();
+        return 0;
+    } else if (std::strcmp(name, __stdout_name) == 0) {
+        init_serial();
+        return 1;
+    } else if (std::strcmp(name, __stderr_name) == 0) {
+        init_serial();
+        return 2;
+    }
+    #endif
+
+    // find the first empty slot in filehandles
+    filehandle_mutex->lock();
+    unsigned int fh_i;
+    for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+        if (filehandles[fh_i] == NULL) break;
+    }
+    if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
+        filehandle_mutex->unlock();
+        return -1;
+    }
+    filehandles[fh_i] = (FileHandle*)FILE_HANDLE_RESERVED;
+    filehandle_mutex->unlock();
+
+    FileHandle *res;
+
+    /* FILENAME: ":0x12345678" describes a FileLike* */
+    if (name[0] == ':') {
+        void *p;
+        sscanf(name, ":%p", &p);
+        res = (FileHandle*)p;
+
+    /* FILENAME: "/file_system/file_name" */
+    } else {
+        FilePath path(name);
+
+        if (!path.exists()) {
+            // Free file handle
+            filehandles[fh_i] = NULL;
+            return -1;
+        } else if (path.isFile()) {
+            res = path.file();
+        } else {
+            FileSystemLike *fs = path.fileSystem();
+            if (fs == NULL) {
+                // Free file handle
+                filehandles[fh_i] = NULL;
+                return -1;
+            }
+            int posix_mode = openmode_to_posix(openmode);
+            res = fs->open(path.fileName(), posix_mode); /* NULL if fails */
+        }
+    }
+
+    if (res == NULL) {
+        // Free file handle
+        filehandles[fh_i] = NULL;
+        return -1;
+    }
+    filehandles[fh_i] = res;
+
+    return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
+}
+
+extern "C" int PREFIX(_close)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    filehandles[fh-3] = NULL;
+    if (fhc == NULL) return -1;
+
+    return fhc->close();
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t    __write (int        fh, const unsigned char *buffer, size_t length) {
+#else
+extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
+#endif
+    int n; // n is the number of bytes written
+    if (fh < 3) {
+#if DEVICE_SERIAL
+        if (!stdio_uart_inited) init_serial();
+#if MBED_CONF_CORE_STDIO_CONVERT_NEWLINES
+        for (unsigned int i = 0; i < length; i++) {
+            if (buffer[i] == '\n' && stdio_out_prev != '\r') {
+                 serial_putc(&stdio_uart, '\r');
+            }
+            serial_putc(&stdio_uart, buffer[i]);
+            stdio_out_prev = buffer[i];
+        }
+#else
+        for (unsigned int i = 0; i < length; i++) {
+            serial_putc(&stdio_uart, buffer[i]);
+        }
+#endif
+#endif
+        n = length;
+    } else {
+        FileHandle* fhc = filehandles[fh-3];
+        if (fhc == NULL) return -1;
+
+        n = fhc->write(buffer, length);
+    }
+#ifdef __ARMCC_VERSION
+    return length-n;
+#else
+    return n;
+#endif
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t    __read (int        fh, unsigned char *buffer, size_t       length) {
+#else
+extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
+#endif
+    int n; // n is the number of bytes read
+    if (fh < 3) {
+        // only read a character at a time from stdin
+#if DEVICE_SERIAL
+        if (!stdio_uart_inited) init_serial();
+#if MBED_CONF_CORE_STDIO_CONVERT_NEWLINES
+        while (true) {
+            char c = serial_getc(&stdio_uart);
+            if ((c == '\r' && stdio_in_prev != '\n') ||
+                (c == '\n' && stdio_in_prev != '\r')) {
+                stdio_in_prev = c;
+                *buffer = '\n';
+                break;
+            } else if ((c == '\r' && stdio_in_prev == '\n') ||
+                       (c == '\n' && stdio_in_prev == '\r')) {
+                stdio_in_prev = c;
+                // onto next character
+                continue;
+            } else {
+                stdio_in_prev = c;
+                *buffer = c;
+                break;
+            }
+        }
+#else
+        *buffer = serial_getc(&stdio_uart);
+#endif
+#endif
+        n = 1;
+    } else {
+        FileHandle* fhc = filehandles[fh-3];
+        if (fhc == NULL) return -1;
+
+        n = fhc->read(buffer, length);
+    }
+#ifdef __ARMCC_VERSION
+    return length-n;
+#else
+    return n;
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_istty)(FILEHANDLE fh)
+#else
+extern "C" int _isatty(FILEHANDLE fh)
+#endif
+{
+    /* stdin, stdout and stderr should be tty */
+    if (fh < 3) return 1;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->isatty();
+}
+
+extern "C"
+#if defined(__ARMCC_VERSION)
+int _sys_seek(FILEHANDLE fh, long position)
+#elif defined(__ICCARM__)
+long __lseek(int fh, long offset, int whence)
+#else
+int _lseek(FILEHANDLE fh, int offset, int whence)
+#endif
+{
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+#if defined(__ARMCC_VERSION)
+    return fhc->lseek(position, SEEK_SET);
+#else
+    return fhc->lseek(offset, whence);
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->fsync();
+}
+
+extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->flen();
+}
+#endif
+
+
+#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
+extern "C" int _fstat(int fd, struct stat *st) {
+    if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd) || (STDIN_FILENO == fd)) {
+        st->st_mode = S_IFCHR;
+        return  0;
+    }
+
+    errno = EBADF;
+    return -1;
+}
+#endif
+
+namespace std {
+extern "C" int remove(const char *path) {
+    FilePath fp(path);
+    FileSystemLike *fs = fp.fileSystem();
+    if (fs == NULL) return -1;
+
+    return fs->remove(fp.fileName());
+}
+
+extern "C" int rename(const char *oldname, const char *newname) {
+    FilePath fpOld(oldname);
+    FilePath fpNew(newname);
+    FileSystemLike *fsOld = fpOld.fileSystem();
+    FileSystemLike *fsNew = fpNew.fileSystem();
+
+    /* rename only if both files are on the same FS */
+    if (fsOld != fsNew || fsOld == NULL) return -1;
+
+    return fsOld->rename(fpOld.fileName(), fpNew.fileName());
+}
+
+extern "C" char *tmpnam(char *s) {
+    return NULL;
+}
+
+extern "C" FILE *tmpfile() {
+    return NULL;
+}
+} // namespace std
+
+#ifdef __ARMCC_VERSION
+extern "C" char *_sys_command_string(char *cmd, int len) {
+    return NULL;
+}
+#endif
+
+extern "C" DIR *opendir(const char *path) {
+    /* root dir is FileSystemLike */
+    if (path[0] == '/' && path[1] == 0) {
+        return FileSystemLike::opendir();
+    }
+
+    FilePath fp(path);
+    FileSystemLike* fs = fp.fileSystem();
+    if (fs == NULL) return NULL;
+
+    return fs->opendir(fp.fileName());
+}
+
+extern "C" struct dirent *readdir(DIR *dir) {
+    return dir->readdir();
+}
+
+extern "C" int closedir(DIR *dir) {
+    return dir->closedir();
+}
+
+extern "C" void rewinddir(DIR *dir) {
+    dir->rewinddir();
+}
+
+extern "C" off_t telldir(DIR *dir) {
+    return dir->telldir();
+}
+
+extern "C" void seekdir(DIR *dir, off_t off) {
+    dir->seekdir(off);
+}
+
+extern "C" int mkdir(const char *path, mode_t mode) {
+    FilePath fp(path);
+    FileSystemLike *fs = fp.fileSystem();
+    if (fs == NULL) return -1;
+
+    return fs->mkdir(fp.fileName(), mode);
+}
+
+#if defined(TOOLCHAIN_GCC)
+/* prevents the exception handling name demangling code getting pulled in */
+#include "mbed_error.h"
+namespace __gnu_cxx {
+    void __verbose_terminate_handler() {
+        error("Exception");
+    }
+}
+extern "C" WEAK void __cxa_pure_virtual(void);
+extern "C" WEAK void __cxa_pure_virtual(void) {
+    exit(1);
+}
+
+#endif
+
+#if defined(TOOLCHAIN_GCC)
+/* uVisor wraps malloc_r, realloc_r and free_r, but not calloc_r! */
+#ifndef  FEATURE_UVISOR
+
+
+#endif/* FEATURE_UVISOR */
+
+
+extern "C" WEAK void software_init_hook_rtos(void)
+{
+    // Do nothing by default.
+}
+
+extern "C" void software_init_hook(void)
+{
+#ifdef   FEATURE_UVISOR
+    int return_code;
+
+    return_code = uvisor_lib_init();
+    if (return_code) {
+        mbed_die();
+    }
+#endif/* FEATURE_UVISOR */
+
+    software_init_hook_rtos();
+}
+#endif
+
+// ****************************************************************************
+// mbed_main is a function that is called before main()
+// mbed_sdk_init() is also a function that is called before main(), but unlike
+// mbed_main(), it is not meant for user code, but for the SDK itself to perform
+// initializations before main() is called.
+
+extern "C" WEAK void mbed_main(void);
+extern "C" WEAK void mbed_main(void) {
+}
+
+extern "C" WEAK void mbed_sdk_init(void);
+extern "C" WEAK void mbed_sdk_init(void) {
+}
+
+#if defined(TOOLCHAIN_ARM)
+extern "C" int $Super$$main(void);
+
+extern "C" int $Sub$$main(void) {
+    mbed_sdk_init();
+    mbed_main();
+    return $Super$$main();
+}
+#elif defined(TOOLCHAIN_GCC)
+extern "C" int __real_main(void);
+
+extern "C" int __wrap_main(void) {
+    mbed_sdk_init();
+    mbed_main();
+    return __real_main();
+}
+#elif defined(TOOLCHAIN_IAR)
+// IAR doesn't have the $Super/$Sub mechanism of armcc, nor something equivalent
+// to ld's --wrap. It does have a --redirect, but that doesn't help, since redirecting
+// 'main' to another symbol looses the original 'main' symbol. However, its startup
+// code will call a function to setup argc and argv (__iar_argc_argv) if it is defined.
+// Since mbed doesn't use argc/argv, we use this function to call our mbed_main.
+extern "C" void __iar_argc_argv() {
+    mbed_main();
+}
+#endif
+
+// Provide implementation of _sbrk (low-level dynamic memory allocation
+// routine) for GCC_ARM which compares new heap pointer with MSP instead of
+// SP.  This make it compatible with RTX RTOS thread stacks.
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR)
+// Linker defined symbol used by _sbrk to indicate where heap should start.
+extern "C" int __end__;
+
+#if defined(TARGET_CORTEX_A)
+extern "C" uint32_t  __HeapLimit;
+#endif
+
+// Turn off the errno macro and use actual global variable instead.
+#undef errno
+extern "C" int errno;
+
+// For ARM7 only
+register unsigned char * stack_ptr __asm ("sp");
+
+// Dynamic memory allocation related syscall.
+#if defined(TARGET_NUMAKER_PFM_NUC472)
+// Overwrite _sbrk() to support two region model.
+extern "C" void *__wrap__sbrk(int incr);
+extern "C" caddr_t _sbrk(int incr) {
+    return (caddr_t) __wrap__sbrk(incr);
+}
+#else
+extern "C" caddr_t _sbrk(int incr) {
+    static unsigned char* heap = (unsigned char*)&__end__;
+    unsigned char*        prev_heap = heap;
+    unsigned char*        new_heap = heap + incr;
+
+#if defined(TARGET_ARM7)
+    if (new_heap >= stack_ptr) {
+#elif defined(TARGET_CORTEX_A)
+    if (new_heap >= (unsigned char*)&__HeapLimit) {     /* __HeapLimit is end of heap section */
+#else
+    if (new_heap >= (unsigned char*)__get_MSP()) {
+#endif
+        errno = ENOMEM;
+        return (caddr_t)-1;
+    }
+
+    // Additional heap checking if set
+    if (mbed_heap_size && (new_heap >= mbed_heap_start + mbed_heap_size)) {
+        errno = ENOMEM;
+        return (caddr_t)-1;
+    }
+
+    heap = new_heap;
+    return (caddr_t) prev_heap;
+}
+#endif
+#endif
+
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR)
+extern "C" void _exit(int return_code) {
+#else
+namespace std {
+extern "C" void exit(int return_code) {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+    fflush(stdout);
+    fflush(stderr);
+#endif
+
+#if DEVICE_SEMIHOST
+    if (mbed_interface_connected()) {
+        semihost_exit();
+    }
+#endif
+    if (return_code) {
+        mbed_die();
+    }
+
+    while (1);
+}
+
+#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CR)
+} //namespace std
+#endif
+
+
+namespace mbed {
+
+void mbed_set_unbuffered_stream(FILE *_file) {
+#if defined (__ICCARM__)
+    char buf[2];
+    std::setvbuf(_file,buf,_IONBF,NULL);    
+#else
+    setbuf(_file, NULL);
+#endif
+}
+
+int mbed_getc(FILE *_file){
+#if defined (__ICCARM__)
+    /*This is only valid for unbuffered streams*/
+    int res = std::fgetc(_file);
+    if (res>=0){
+        _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+        _file->_Rend = _file->_Wend;
+        _file->_Next = _file->_Wend;
+    }    
+    return res;
+#else    
+    return std::fgetc(_file);
+#endif   
+}
+
+char* mbed_gets(char*s, int size, FILE *_file){
+#if defined (__ICCARM__)
+    /*This is only valid for unbuffered streams*/
+    char *str = fgets(s,size,_file);
+    if (str!=NULL){
+        _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+        _file->_Rend = _file->_Wend;
+        _file->_Next = _file->_Wend;
+    }
+    return str;
+#else    
+    return std::fgets(s,size,_file);
+#endif
+}
+
+} // namespace mbed
+
+#if defined (__ICCARM__)
+// Stub out locks when an rtos is not present
+extern "C" WEAK void __iar_system_Mtxinit(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxdst(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_system_Mtxunlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxinit(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxdst(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxlock(__iar_Rmtx *mutex) {}
+extern "C" WEAK void __iar_file_Mtxunlock(__iar_Rmtx *mutex) {}
+#elif defined(__CC_ARM)
+// Do nothing
+#elif defined (__GNUC__)
+struct _reent;
+// Stub out locks when an rtos is not present
+extern "C" WEAK void __rtos_malloc_lock( struct _reent *_r ) {}
+extern "C" WEAK void __rtos_malloc_unlock( struct _reent *_r ) {}
+extern "C" WEAK void __rtos_env_lock( struct _reent *_r ) {}
+extern "C" WEAK void __rtos_env_unlock( struct _reent *_r ) {}
+
+extern "C" void __malloc_lock( struct _reent *_r )
+{
+    __rtos_malloc_lock(_r);
+}
+
+extern "C" void __malloc_unlock( struct _reent *_r )
+{
+    __rtos_malloc_unlock(_r);
+}
+
+extern "C" void __env_lock( struct _reent *_r )
+{
+    __rtos_env_lock(_r);
+}
+
+extern "C" void __env_unlock( struct _reent *_r )
+{
+    __rtos_env_unlock(_r);
+}
+#endif
+
+void *operator new(std::size_t count)
+{
+    void *buffer = malloc(count);
+    if (NULL == buffer) {
+        error("Operator new out of memory\r\n");
+    }
+    return buffer;
+}
+
+void *operator new[](std::size_t count)
+{
+    void *buffer = malloc(count);
+    if (NULL == buffer) {
+        error("Operator new[] out of memory\r\n");
+    }
+    return buffer;
+}
+
+void operator delete(void *ptr)
+{
+    if (ptr != NULL) {
+        free(ptr);
+    }
+}
+void operator delete[](void *ptr)
+{
+    if (ptr != NULL) {
+        free(ptr);
+    }
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/analogin_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_API_H
+#define MBED_ANALOGIN_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Analogin hal structure. analogin_s is declared in the target's hal
+ */
+typedef struct analogin_s analogin_t;
+
+/**
+ * \defgroup hal_analogin Analogin hal functions
+ * @{
+ */
+
+/** Initialize the analogin peripheral
+ *
+ * Configures the pin used by analogin.
+ * @param obj The analogin object to initialize
+ * @param pin The analogin pin name
+ */
+void analogin_init(analogin_t *obj, PinName pin);
+
+/** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @param obj The analogin object
+ * @return A floating value representing the current input voltage
+ */
+float analogin_read(analogin_t *obj);
+
+/** Read the value from analogin pin, represented as an unsigned 16bit value
+ *
+ * @param obj The analogin object
+ * @return An unsigned 16bit value representing the current input voltage
+ */
+uint16_t analogin_read_u16(analogin_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/analogout_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_API_H
+#define MBED_ANALOGOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Analogout hal structure. dac_s is declared in the target's hal
+ */
+typedef struct dac_s dac_t;
+
+/**
+ * \defgroup hal_analogout Analogout hal functions
+ * @{
+ */
+
+/** Initialize the analogout peripheral
+ *
+ * Configures the pin used by analogout.
+ * @param obj The analogout object to initialize
+ * @param pin The analogout pin name
+ */
+void analogout_init(dac_t *obj, PinName pin);
+
+/** Release the analogout object
+ *
+ * Note: This is not currently used in the mbed-drivers
+ * @param obj The analogout object
+ */
+void analogout_free(dac_t *obj);
+
+/** Set the output voltage, specified as a percentage (float)
+ *
+ * @param obj The analogin object
+ * @param value The floating-point output voltage to be set
+ */
+void analogout_write(dac_t *obj, float value);
+
+/** Set the output voltage, specified as unsigned 16-bit
+ *
+ * @param obj The analogin object
+ * @param value The unsigned 16-bit output voltage to be set
+ */
+void analogout_write_u16(dac_t *obj, uint16_t value);
+
+/** Read the current voltage value on the pin
+ *
+ * @param obj The analogin object
+ * @return A floating-point value representing the current voltage on the pin,
+ *     measured as a percentage
+ */
+float analogout_read(dac_t *obj);
+
+/** Read the current voltage value on the pin, as a normalized unsigned 16bit value
+ *
+ * @param obj The analogin object
+ * @return An unsigned 16-bit value representing the current voltage on the pin
+ */
+uint16_t analogout_read_u16(dac_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/buffer.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUFFER_H
+#define MBED_BUFFER_H
+
+#include <stddef.h>
+
+/** Generic buffer structure
+ */
+typedef struct buffer_s {
+    void    *buffer; /**< the pointer to a buffer */
+    size_t   length; /**< the buffer length */
+    size_t   pos;    /**< actual buffer position */
+    uint8_t  width;  /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */
+} buffer_t;
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/can_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,81 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_API_H
+#define MBED_CAN_API_H
+
+#include "device.h"
+
+#if DEVICE_CAN
+
+#include "PinNames.h"
+#include "PeripheralNames.h"
+#include "can_helper.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    IRQ_RX,
+    IRQ_TX,
+    IRQ_ERROR,
+    IRQ_OVERRUN,
+    IRQ_WAKEUP,
+    IRQ_PASSIVE,
+    IRQ_ARB,
+    IRQ_BUS,
+    IRQ_READY
+} CanIrqType;
+
+
+typedef enum {
+    MODE_RESET,
+    MODE_NORMAL,
+    MODE_SILENT,
+    MODE_TEST_LOCAL,
+    MODE_TEST_GLOBAL,
+    MODE_TEST_SILENT
+} CanMode;
+
+typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
+
+typedef struct can_s can_t;
+
+void          can_init     (can_t *obj, PinName rd, PinName td);
+void          can_free     (can_t *obj);
+int           can_frequency(can_t *obj, int hz);
+
+void          can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
+void          can_irq_free (can_t *obj);
+void          can_irq_set  (can_t *obj, CanIrqType irq, uint32_t enable);
+
+int           can_write    (can_t *obj, CAN_Message, int cc);
+int           can_read     (can_t *obj, CAN_Message *msg, int handle);
+int           can_mode     (can_t *obj, CanMode mode);
+int           can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
+void          can_reset    (can_t *obj);
+unsigned char can_rderror  (can_t *obj);
+unsigned char can_tderror  (can_t *obj);
+void          can_monitor  (can_t *obj, int silent);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif    // MBED_CAN_API_H
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/dma_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DMA_API_H
+#define MBED_DMA_API_H
+
+#include <stdint.h>
+
+#define DMA_ERROR_OUT_OF_CHANNELS (-1)
+
+typedef enum {
+    DMA_USAGE_NEVER,
+    DMA_USAGE_OPPORTUNISTIC,
+    DMA_USAGE_ALWAYS,
+    DMA_USAGE_TEMPORARY_ALLOCATED,
+    DMA_USAGE_ALLOCATED
+} DMAUsage;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void dma_init(void);
+
+int dma_channel_allocate(uint32_t capabilities);
+
+int dma_channel_free(int channelid);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/ethernet_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_API_H
+#define MBED_ETHERNET_API_H
+
+#include "device.h"
+
+#if DEVICE_ETHERNET
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Connection constants
+
+int ethernet_init(void);
+void ethernet_free(void);
+
+// write size bytes from data to ethernet buffer
+// return num bytes written
+// or -1 if size is too big
+int ethernet_write(const char *data, int size);
+
+// send ethernet write buffer, returning the packet size sent
+int ethernet_send(void);
+
+// recieve from ethernet buffer, returning packet size, or 0 if no packet
+int ethernet_receive(void);
+
+// read size bytes in to data, return actual num bytes read (0..size)
+// if data == NULL, throw the bytes away
+int ethernet_read(char *data, int size);
+
+// get the ethernet address
+void ethernet_address(char *mac);
+
+// see if the link is up
+int ethernet_link(void);
+
+// force link settings
+void ethernet_set_link(int speed, int duplex);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/gpio_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,129 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_API_H
+#define MBED_GPIO_API_H
+
+#include <stdint.h>
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_gpio GPIO HAL functions
+ * @{
+ */
+
+/** Set the given pin as GPIO
+ *
+ * @param pin The pin to be set as GPIO
+ * @return The GPIO port mask for this pin
+ **/
+uint32_t gpio_set(PinName pin);
+/* Checks if gpio object is connected (pin was not initialized with NC)
+ * @param pin The pin to be set as GPIO
+ * @return 0 if port is initialized with NC
+ **/
+int gpio_is_connected(const gpio_t *obj);
+
+/** Initialize the GPIO pin
+ *
+ * @param obj The GPIO object to initialize
+ * @param pin The GPIO pin to initialize
+ */
+void gpio_init(gpio_t *obj, PinName pin);
+
+/** Set the input pin mode
+ *
+ * @param obj  The GPIO object
+ * @param mode The pin mode to be set
+ */
+void gpio_mode(gpio_t *obj, PinMode mode);
+
+/** Set the pin direction
+ *
+ * @param obj       The GPIO object
+ * @param direction The pin direction to be set
+ */
+void gpio_dir(gpio_t *obj, PinDirection direction);
+
+/** Set the output value
+ *
+ * @param obj   The GPIO object
+ * @param value The value to be set
+ */
+void gpio_write(gpio_t *obj, int value);
+
+/** Read the input value
+ *
+ * @param obj The GPIO object
+ * @return An integer value 1 or 0
+ */
+int gpio_read(gpio_t *obj);
+
+// the following functions are generic and implemented in the common gpio.c file
+// TODO: fix, will be moved to the common gpio header file
+
+/** Init the input pin and set mode to PullDefault
+ *
+ * @param obj The GPIO object
+ * @param pin The pin name
+ */
+void gpio_init_in(gpio_t* gpio, PinName pin);
+
+/** Init the input pin and set the mode
+ *
+ * @param obj  The GPIO object
+ * @param pin  The pin name
+ * @param mode The pin mode to be set
+ */
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
+
+/** Init the output pin as an output, with predefined output value 0
+ *
+ * @param obj The GPIO object
+ * @param pin The pin name
+ * @return An integer value 1 or 0
+ */
+void gpio_init_out(gpio_t* gpio, PinName pin);
+
+/** Init the pin as an output and set the output value
+ *
+ * @param obj   The GPIO object
+ * @param pin   The pin name
+ * @param value The value to be set
+ */
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
+
+/** Init the pin to be in/out
+ *
+ * @param obj       The GPIO object
+ * @param pin       The pin name
+ * @param direction The pin direction to be set
+ * @param mode      The pin mode to be set
+ * @param value     The value to be set for an output pin
+ */
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/gpio_irq_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_IRQ_API_H
+#define MBED_GPIO_IRQ_API_H
+
+#include "device.h"
+
+#if DEVICE_INTERRUPTIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIO IRQ events
+ */
+typedef enum {
+    IRQ_NONE,
+    IRQ_RISE,
+    IRQ_FALL
+} gpio_irq_event;
+
+/** GPIO IRQ HAL structure. gpio_irq_s is declared in the target's HAL
+ */
+typedef struct gpio_irq_s gpio_irq_t;
+
+typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
+
+/**
+ * \defgroup hal_gpioirq GPIO IRQ HAL functions
+ * @{
+ */
+
+/** Initialize the GPIO IRQ pin
+ *
+ * @param obj     The GPIO object to initialize
+ * @param pin     The GPIO pin name
+ * @param handler The handler to be attached to GPIO IRQ
+ * @param id      The object ID (id != 0, 0 is reserved)
+ * @return -1 if pin is NC, 0 otherwise
+ */
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
+
+/** Release the GPIO IRQ PIN
+ *
+ * @param obj The gpio object
+ */
+void gpio_irq_free(gpio_irq_t *obj);
+
+/** Enable/disable pin IRQ event
+ *
+ * @param obj    The GPIO object
+ * @param event  The GPIO IRQ event
+ * @param enable The enable flag
+ */
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
+
+/** Enable GPIO IRQ
+ *
+ * This is target dependent, as it might enable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_enable(gpio_irq_t *obj);
+
+/** Disable GPIO IRQ
+ *
+ * This is target dependent, as it might disable the entire port or just a pin
+ * @param obj The GPIO object
+ */
+void gpio_irq_disable(gpio_irq_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/i2c_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,242 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_API_H
+#define MBED_I2C_API_H
+
+#include "device.h"
+#include "buffer.h"
+
+#if DEVICE_I2C_ASYNCH
+#include "dma_api.h"
+#endif
+
+#if DEVICE_I2C
+
+/**
+ * @defgroup hal_I2CEvents I2C Events Macros
+ *
+ * @{
+ */
+#define I2C_EVENT_ERROR               (1 << 1)
+#define I2C_EVENT_ERROR_NO_SLAVE      (1 << 2)
+#define I2C_EVENT_TRANSFER_COMPLETE   (1 << 3)
+#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)
+#define I2C_EVENT_ALL                 (I2C_EVENT_ERROR |  I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
+
+/**@}*/
+
+#if DEVICE_I2C_ASYNCH
+/** Asynch I2C HAL structure
+ */
+typedef struct {
+    struct i2c_s    i2c;     /**< Target specific I2C structure */
+    struct buffer_s tx_buff; /**< Tx buffer */
+    struct buffer_s rx_buff; /**< Rx buffer */
+} i2c_t;
+
+#else
+/** Non-asynch I2C HAL structure
+ */
+typedef struct i2c_s i2c_t;
+
+#endif
+
+enum {
+  I2C_ERROR_NO_SLAVE = -1,
+  I2C_ERROR_BUS_BUSY = -2
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralI2C I2C Configuration Functions
+ * @{
+ */
+
+/** Initialize the I2C peripheral. It sets the default parameters for I2C
+ *  peripheral, and configures its specifieds pins.
+ *  
+ *  @param obj  The I2C object
+ *  @param sda  The sda pin
+ *  @param scl  The scl pin
+ */
+void i2c_init(i2c_t *obj, PinName sda, PinName scl);
+
+/** Configure the I2C frequency
+ *
+ *  @param obj The I2C object
+ *  @param hz  Frequency in Hz
+ */
+void i2c_frequency(i2c_t *obj, int hz);
+
+/** Send START command
+ *
+ *  @param obj The I2C object
+ */
+int  i2c_start(i2c_t *obj);
+
+/** Send STOP command
+ *
+ *  @param obj The I2C object
+ */
+int  i2c_stop(i2c_t *obj);
+
+/** Blocking reading data
+ *
+ *  @param obj     The I2C object
+ *  @param address 7-bit address (last bit is 1)
+ *  @param data    The buffer for receiving
+ *  @param length  Number of bytes to read
+ *  @param stop    Stop to be generated after the transfer is done
+ *  @return Number of read bytes
+ */
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop);
+
+/** Blocking sending data
+ *
+ *  @param obj     The I2C object
+ *  @param address 7-bit address (last bit is 0)
+ *  @param data    The buffer for sending
+ *  @param length  Number of bytes to write
+ *  @param stop    Stop to be generated after the transfer is done
+ *  @return Number of written bytes
+ */
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);
+
+/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop()
+ *
+ *  @param obj The I2C object
+ */
+void i2c_reset(i2c_t *obj);
+
+/** Read one byte
+ *
+ *  @param obj The I2C object
+ *  @param last Acknoledge
+ *  @return The read byte
+ */
+int i2c_byte_read(i2c_t *obj, int last);
+
+/** Write one byte
+ *
+ *  @param obj The I2C object
+ *  @param data Byte to be written
+ *  @return 0 if NAK was received, 1 if ACK was received, 2 for timeout.
+ */
+int i2c_byte_write(i2c_t *obj, int data);
+
+/**@}*/
+
+#if DEVICE_I2CSLAVE
+
+/**
+ * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
+ * @{
+ */
+
+/** Configure I2C as slave or master.
+ *  @param obj The I2C object
+ *  @return non-zero if a value is available
+ */
+void i2c_slave_mode(i2c_t *obj, int enable_slave);
+
+/** Check to see if the I2C slave has been addressed.
+ *  @param obj The I2C object
+ *  @return The status - 1 - read addresses, 2 - write to all slaves,
+ *         3 write addressed, 0 - the slave has not been addressed
+ */
+int  i2c_slave_receive(i2c_t *obj);
+
+/** Configure I2C as slave or master.
+ *  @param obj The I2C object
+ *  @return non-zero if a value is available
+ */
+int  i2c_slave_read(i2c_t *obj, char *data, int length);
+
+/** Configure I2C as slave or master.
+ *  @param obj The I2C object
+ *  @return non-zero if a value is available
+ */
+int  i2c_slave_write(i2c_t *obj, const char *data, int length);
+
+/** Configure I2C address.
+ *  @param obj     The I2C object
+ *  @param idx     Currently not used
+ *  @param address The address to be set
+ *  @param mask    Currently not used
+ */
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
+
+#endif
+
+/**@}*/
+
+#if DEVICE_I2C_ASYNCH
+
+/**
+ * \defgroup hal_AsynchI2C Asynchronous I2C Hardware Abstraction Layer
+ * @{
+ */
+
+/** Start I2C asynchronous transfer
+ *
+ *  @param obj       The I2C object
+ *  @param tx        The transmit buffer
+ *  @param tx_length The number of bytes to transmit
+ *  @param rx        The receive buffer
+ *  @param rx_length The number of bytes to receive
+ *  @param address   The address to be set - 7bit or 9bit
+ *  @param stop      If true, stop will be generated after the transfer is done
+ *  @param handler   The I2C IRQ handler to be set
+ *  @param hint      DMA hint usage
+ */
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** The asynchronous IRQ handler
+ *
+ *  @param obj The I2C object which holds the transfer information
+ *  @return Event flags if a transfer termination condition was met, otherwise return 0.
+ */
+uint32_t i2c_irq_handler_asynch(i2c_t *obj);
+
+/** Attempts to determine if the I2C peripheral is already in use
+ *
+ *  @param obj The I2C object
+ *  @return Non-zero if the I2C module is active or zero if it is not
+ */
+uint8_t i2c_active(i2c_t *obj);
+
+/** Abort asynchronous transfer
+ *
+ *  This function does not perform any check - that should happen in upper layers.
+ *  @param obj The I2C object
+ */
+void i2c_abort_asynch(i2c_t *obj);
+
+#endif
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/lp_ticker_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LPTICKER_API_H
+#define MBED_LPTICKER_API_H
+
+#include "device.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_LpTicker Low Power Ticker Functions
+ * @{
+ */
+
+/** Get low power ticker's data
+ *
+ * @return The low power ticker data
+ */
+const ticker_data_t* get_lp_ticker_data(void);
+
+/** The wrapper for ticker_irq_handler, to pass lp ticker's data
+ *
+ */
+void lp_ticker_irq_handler(void);
+
+/* HAL lp ticker */
+
+/** Initialize the low power ticker
+ *
+ */
+void lp_ticker_init(void);
+
+/** Read the current counter
+ *
+ * @return The current timer's counter value in microseconds
+ */
+uint32_t lp_ticker_read(void);
+
+/** Set interrupt for specified timestamp
+ *
+ * @param timestamp The time in microseconds to be set
+ */
+void lp_ticker_set_interrupt(timestamp_t timestamp);
+
+/** Disable low power ticker interrupt
+ *
+ */
+void lp_ticker_disable_interrupt(void);
+
+/** Clear the low power ticker interrupt
+ *
+ */
+void lp_ticker_clear_interrupt(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/pinmap.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINMAP_H
+#define MBED_PINMAP_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName pin;
+    int peripheral;
+    int function;
+} PinMap;
+
+void pin_function(PinName pin, int function);
+void pin_mode    (PinName pin, PinMode mode);
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_function(PinName pin, const PinMap* map);
+uint32_t pinmap_merge     (uint32_t a, uint32_t b);
+void     pinmap_pinout    (PinName pin, const PinMap *map);
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_find_function(PinName pin, const PinMap* map);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/port_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTMAP_H
+#define MBED_PORTMAP_H
+
+#include "device.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Port HAL structure. port_s is declared in the target's HAL
+ */
+typedef struct port_s port_t;
+
+/**
+ * \defgroup hal_port Port HAL functions
+ * @{
+ */
+
+/** Get the pin name from the port's pin number
+ *
+ * @param port  The port name
+ * @param pin_n The pin number within the specified port
+ * @return The pin name for the port's pin number
+ */
+PinName port_pin(PortName port, int pin_n);
+
+/** Initilize the port
+ *
+ * @param obj  The port object to initialize
+ * @param port The port name
+ * @param mask The bitmask to identify which bits in the port should be included (0 - ignore)
+ * @param dir  The port direction
+ */
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir);
+
+/** Set the input port mode
+ *
+ * @param obj  The port object
+ * @param mode THe port mode to be set
+ */
+void port_mode(port_t *obj, PinMode mode);
+
+/** Set port direction (in/out)
+ *
+ * @param obj The port object
+ * @param dir The port direction to be set
+ */
+void port_dir(port_t *obj, PinDirection dir);
+
+/** Write value to the port
+ *
+ * @param obj   The port object
+ * @param value The value to be set
+ */
+void port_write(port_t *obj, int value);
+
+/** Read the current value on the port
+ *
+ * @param obj The port object
+ * @return An integer with each bit corresponding to an associated port pin setting
+ */
+int port_read(port_t *obj);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/pwmout_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_API_H
+#define MBED_PWMOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_PWMOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Pwmout hal structure. pwmout_s is declared in the target's hal
+ */
+typedef struct pwmout_s pwmout_t;
+
+/**
+ * \defgroup hal_pwmout Pwmout hal functions
+ * @{
+ */
+
+/** Initialize the pwm out peripheral and configure the pin
+ *
+ * @param obj The pwmout object to initialize
+ * @param pin The pwmout pin to initialize
+ */
+void pwmout_init(pwmout_t *obj, PinName pin);
+
+/** Deinitialize the pwmout object
+ *
+ * @param obj The pwmout object
+ */
+void pwmout_free(pwmout_t *obj);
+
+/** Set the output duty-cycle in range <0.0f, 1.0f>
+ *
+ * Value 0.0f represents 0 percentage, 1.0f represents 100 percent.
+ * @param obj     The pwmout object
+ * @param percent The floating-point percentage number
+ */
+void pwmout_write(pwmout_t *obj, float percent);
+
+/** Read the current float-point output duty-cycle
+ *
+ * @param obj The pwmout object
+ * @return A floating-point output duty-cycle
+ */
+float pwmout_read(pwmout_t *obj);
+
+/** Set the PWM period specified in seconds, keeping the duty cycle the same
+ *
+ * Periods smaller than microseconds (the lowest resolution) are set to zero.
+ * @param obj     The pwmout object
+ * @param seconds The floating-point seconds period
+ */
+void pwmout_period(pwmout_t *obj, float seconds);
+
+/** Set the PWM period specified in miliseconds, keeping the duty cycle the same
+ *
+ * @param obj The pwmout object
+ * @param ms  The milisecond period
+ */
+void pwmout_period_ms(pwmout_t *obj, int ms);
+
+/** Set the PWM period specified in microseconds, keeping the duty cycle the same
+ *
+ * @param obj The pwmout object
+ * @param us  The microsecond period
+ */
+void pwmout_period_us(pwmout_t *obj, int us);
+
+/** Set the PWM pulsewidth specified in seconds, keeping the period the same.
+ *
+ * @param obj     The pwmout object
+ * @param seconds The floating-point pulsewidth in seconds
+ */
+void pwmout_pulsewidth(pwmout_t *obj, float seconds);
+
+/** Set the PWM pulsewidth specified in miliseconds, keeping the period the same.
+ *
+ * @param obj The pwmout object
+ * @param ms  The floating-point pulsewidth in miliseconds
+ */
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms);
+
+/** Set the PWM pulsewidth specified in microseconds, keeping the period the same.
+ *
+ * @param obj The pwmout object
+ * @param us  The floating-point pulsewidth in microseconds
+ */
+void pwmout_pulsewidth_us(pwmout_t *obj, int us);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/rtc_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RTC_API_H
+#define MBED_RTC_API_H
+
+#include "device.h"
+
+#if DEVICE_RTC
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_rtc RTC hal functions
+ * @{
+ */
+
+/** Initialize the RTC peripheral
+ *
+ */
+void rtc_init(void);
+
+/** Deinitialize RTC
+ *
+ * TODO: The function is not used by rtc api in mbed-drivers.
+ */
+void rtc_free(void);
+
+/** Get the RTC enable status
+ *
+ * @retval 0 disabled
+ * @retval 1 enabled
+ */
+int rtc_isenabled(void);
+
+/** Get the current time from the RTC peripheral
+ *
+ * @return The current time
+ */
+time_t rtc_read(void);
+
+/** Set the current time to the RTC peripheral
+ *
+ * @param t The current time to be set
+ */
+void rtc_write(time_t t);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/serial_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,303 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_API_H
+#define MBED_SERIAL_API_H
+
+#include "device.h"
+#include "buffer.h"
+#include "dma_api.h"
+
+#if DEVICE_SERIAL
+
+#define SERIAL_EVENT_TX_SHIFT (2)
+#define SERIAL_EVENT_RX_SHIFT (8)
+
+#define SERIAL_EVENT_TX_MASK (0x00FC)
+#define SERIAL_EVENT_RX_MASK (0x3F00)
+
+#define SERIAL_EVENT_ERROR (1 << 1)
+
+/**
+ * @defgroup SerialTXEvents Serial TX Events Macros
+ *
+ * @{
+ */
+#define SERIAL_EVENT_TX_COMPLETE (1 << (SERIAL_EVENT_TX_SHIFT + 0))
+#define SERIAL_EVENT_TX_ALL      (SERIAL_EVENT_TX_COMPLETE)
+/**@}*/
+
+/**
+ * @defgroup SerialRXEvents Serial RX Events Macros
+ *
+ * @{
+ */
+#define SERIAL_EVENT_RX_COMPLETE        (1 << (SERIAL_EVENT_RX_SHIFT + 0))
+#define SERIAL_EVENT_RX_OVERRUN_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 1))
+#define SERIAL_EVENT_RX_FRAMING_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 2))
+#define SERIAL_EVENT_RX_PARITY_ERROR    (1 << (SERIAL_EVENT_RX_SHIFT + 3))
+#define SERIAL_EVENT_RX_OVERFLOW        (1 << (SERIAL_EVENT_RX_SHIFT + 4))
+#define SERIAL_EVENT_RX_CHARACTER_MATCH (1 << (SERIAL_EVENT_RX_SHIFT + 5))
+#define SERIAL_EVENT_RX_ALL             (SERIAL_EVENT_RX_OVERFLOW | SERIAL_EVENT_RX_PARITY_ERROR | \
+                                         SERIAL_EVENT_RX_FRAMING_ERROR | SERIAL_EVENT_RX_OVERRUN_ERROR | \
+                                         SERIAL_EVENT_RX_COMPLETE | SERIAL_EVENT_RX_CHARACTER_MATCH)
+/**@}*/
+
+#define SERIAL_RESERVED_CHAR_MATCH (255)
+
+typedef enum {
+    ParityNone = 0,
+    ParityOdd = 1,
+    ParityEven = 2,
+    ParityForced1 = 3,
+    ParityForced0 = 4
+} SerialParity;
+
+typedef enum {
+    RxIrq,
+    TxIrq
+} SerialIrq;
+
+typedef enum {
+    FlowControlNone,
+    FlowControlRTS,
+    FlowControlCTS,
+    FlowControlRTSCTS
+} FlowControl;
+
+typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
+
+#if DEVICE_SERIAL_ASYNCH
+/** Asynch serial HAL structure
+ */
+typedef struct {
+    struct serial_s serial;  /**< Target specific serial structure */
+    struct buffer_s tx_buff; /**< TX buffer */
+    struct buffer_s rx_buff; /**< RX buffer */
+    uint8_t char_match;      /**< Character to be matched */
+    uint8_t char_found;      /**< State of the matched character */
+} serial_t;
+
+#else
+/** Non-asynch serial HAL structure
+ */
+typedef struct serial_s serial_t;
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralSerial Serial Configuration Functions
+ * @{
+ */
+
+/** Initialize the serial peripheral. It sets the default parameters for serial
+ *  peripheral, and configures its specifieds pins.
+ *
+ * @param obj The serial object
+ * @param tx  The TX pin name
+ * @param rx  The RX pin name
+ */
+void serial_init(serial_t *obj, PinName tx, PinName rx);
+
+/** Release the serial peripheral, not currently invoked. It requires further
+ *  resource management.
+ *
+ * @param obj The serial object
+ */
+void serial_free(serial_t *obj);
+
+/** Configure the baud rate
+ *
+ * @param obj      The serial object
+ * @param baudrate The baud rate to be configured
+ */
+void serial_baud(serial_t *obj, int baudrate);
+
+/** Configure the format. Set the number of bits, parity and the number of stop bits
+ *
+ * @param obj       The serial object
+ * @param data_bits The number of data bits
+ * @param parity    The parity
+ * @param stop_bits The number of stop bits
+ */
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
+
+/** The serial interrupt handler registration
+ *
+ * @param obj     The serial object
+ * @param handler The interrupt handler which will be invoked when the interrupt fires
+ * @param id      The SerialBase object
+ */
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
+
+/** Configure serial interrupt. This function is used for word-approach
+ *
+ * @param obj    The serial object
+ * @param irq    The serial IRQ type (RX or TX)
+ * @param enable Set to non-zero to enable events, or zero to disable them
+ */
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable);
+
+/** Get character. This is a blocking call, waiting for a character
+ *
+ * @param obj The serial object
+ */
+int  serial_getc(serial_t *obj);
+
+/** Send a character. This is a blocking call, waiting for a peripheral to be available
+ *  for writing
+ *
+ * @param obj The serial object
+ * @param c   The character to be sent
+ */
+void serial_putc(serial_t *obj, int c);
+
+/** Check if the serial peripheral is readable
+ *
+ * @param obj The serial object
+ * @return Non-zero value if a character can be read, 0 if nothing to read
+ */
+int  serial_readable(serial_t *obj);
+
+/** Check if the serial peripheral is writable
+ *
+ * @param obj The serial object
+ * @return Non-zero value if a character can be written, 0 otherwise.
+ */
+int  serial_writable(serial_t *obj);
+
+/** Clear the serial peripheral
+ *
+ * @param obj The serial object
+ */
+void serial_clear(serial_t *obj);
+
+/** Set the break
+ *
+ * @param obj The serial object
+ */
+void serial_break_set(serial_t *obj);
+
+/** Clear the break
+ *
+ * @param obj The serial object
+ */
+void serial_break_clear(serial_t *obj);
+
+/** Configure the TX pin for UART function.
+ *
+ * @param tx The pin name used for TX
+ */
+void serial_pinout_tx(PinName tx);
+
+/** Configure the serial for the flow control. It sets flow control in the hardware
+ *  if a serial peripheral supports it, otherwise software emulation is used.
+ *
+ * @param obj    The serial object
+ * @param type   The type of the flow control. Look at the available FlowControl types.
+ * @param rxflow The TX pin name
+ * @param txflow The RX pin name
+ */
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
+
+#if DEVICE_SERIAL_ASYNCH
+
+/**@}*/
+
+/**
+ * \defgroup hal_AsynchSerial Asynchronous Serial Hardware Abstraction Layer
+ * @{
+ */
+
+/** Begin asynchronous TX transfer. The used buffer is specified in the serial object,
+ *  tx_buff
+ *
+ * @param obj       The serial object
+ * @param tx        The transmit buffer
+ * @param tx_length The number of bytes to transmit
+ * @param tx_width  Deprecated argument
+ * @param handler   The serial handler
+ * @param event     The logical OR of events to be registered
+ * @param hint      A suggestion for how to use DMA with this transfer
+ * @return Returns number of data transfered, otherwise returns 0
+ */
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** Begin asynchronous RX transfer (enable interrupt for data collecting)
+ *  The used buffer is specified in the serial object - rx_buff
+ *
+ * @param obj        The serial object
+ * @param rx         The receive buffer
+ * @param rx_length  The number of bytes to receive
+ * @param rx_width   Deprecated argument
+ * @param handler    The serial handler
+ * @param event      The logical OR of events to be registered
+ * @param handler    The serial handler
+ * @param char_match A character in range 0-254 to be matched
+ * @param hint       A suggestion for how to use DMA with this transfer
+ */
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint);
+
+/** Attempts to determine if the serial peripheral is already in use for TX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_tx_active(serial_t *obj);
+
+/** Attempts to determine if the serial peripheral is already in use for RX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_rx_active(serial_t *obj);
+
+/** The asynchronous TX and RX handler.
+ *
+ * @param obj The serial object
+ * @return Returns event flags if an RX transfer termination condition was met; otherwise returns 0
+ */
+int serial_irq_handler_asynch(serial_t *obj);
+
+/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and
+ *  flushes the TX hardware buffer if TX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_tx_abort_asynch(serial_t *obj);
+
+/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and
+ *  flushes the RX hardware buffer if RX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_rx_abort_asynch(serial_t *obj);
+
+/**@}*/
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/sleep_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SLEEP_API_H
+#define MBED_SLEEP_API_H
+
+#include "device.h"
+
+#if DEVICE_SLEEP
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Send the microcontroller to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void sleep(void);
+
+/** Send the microcontroller to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void deepsleep(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/spi_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,215 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_API_H
+#define MBED_SPI_API_H
+
+#include "device.h"
+#include "dma_api.h"
+#include "buffer.h"
+
+#if DEVICE_SPI
+
+#define SPI_EVENT_ERROR       (1 << 1)
+#define SPI_EVENT_COMPLETE    (1 << 2)
+#define SPI_EVENT_RX_OVERFLOW (1 << 3)
+#define SPI_EVENT_ALL         (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
+
+#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
+
+#define SPI_FILL_WORD         (0xFFFF)
+
+#if DEVICE_SPI_ASYNCH
+/** Asynch SPI HAL structure
+ */
+typedef struct {
+    struct spi_s spi;        /**< Target specific SPI structure */
+    struct buffer_s tx_buff; /**< Tx buffer */
+    struct buffer_s rx_buff; /**< Rx buffer */
+} spi_t;
+
+#else
+/** Non-asynch SPI HAL structure
+ */
+typedef struct spi_s spi_t;
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_GeneralSPI SPI Configuration Functions
+ * @{
+ */
+
+/** Initialize the SPI peripheral
+ *
+ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
+ * @param[out] obj  The SPI object to initialize
+ * @param[in]  mosi The pin to use for MOSI
+ * @param[in]  miso The pin to use for MISO
+ * @param[in]  sclk The pin to use for SCLK
+ * @param[in]  ssel The pin to use for SSEL
+ */
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+/** Release a SPI object
+ *
+ * TODO: spi_free is currently unimplemented
+ * This will require reference counting at the C++ level to be safe
+ *
+ * Return the pins owned by the SPI object to their reset state
+ * Disable the SPI peripheral
+ * Disable the SPI clock
+ * @param[in] obj The SPI object to deinitialize
+ */
+void spi_free(spi_t *obj);
+
+/** Configure the SPI format
+ *
+ * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
+ * The default bit order is MSB.
+ * @param[in,out] obj   The SPI object to configure
+ * @param[in]     bits  The number of bits per frame
+ * @param[in]     mode  The SPI mode (clock polarity, phase, and shift direction)
+ * @param[in]     slave Zero for master mode or non-zero for slave mode
+ */
+void spi_format(spi_t *obj, int bits, int mode, int slave);
+
+/** Set the SPI baud rate
+ *
+ * Actual frequency may differ from the desired frequency due to available dividers and bus clock
+ * Configures the SPI peripheral's baud rate
+ * @param[in,out] obj The SPI object to configure
+ * @param[in]     hz  The baud rate in Hz
+ */
+void spi_frequency(spi_t *obj, int hz);
+
+/**@}*/
+/**
+ * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Write a byte out in master mode and receive a value
+ *
+ * @param[in] obj   The SPI peripheral to use for sending
+ * @param[in] value The value to send
+ * @return Returns the value received during send
+ */
+int  spi_master_write(spi_t *obj, int value);
+
+/** Check if a value is available to read
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if a value is available
+ */
+int  spi_slave_receive(spi_t *obj);
+
+/** Get a received value out of the SPI receive buffer in slave mode
+ *
+ * Blocks until a value is available
+ * @param[in] obj The SPI peripheral to read
+ * @return The value received
+ */
+int  spi_slave_read(spi_t *obj);
+
+/** Write a value to the SPI peripheral in slave mode
+ *
+ * Blocks until the SPI peripheral can be written to
+ * @param[in] obj   The SPI peripheral to write
+ * @param[in] value The value to write
+ */
+void spi_slave_write(spi_t *obj, int value);
+
+/** Checks if the specified SPI peripheral is in use
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if the peripheral is currently transmitting
+ */
+int  spi_busy(spi_t *obj);
+
+/** Get the module number
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return The module number
+ */
+uint8_t spi_get_module(spi_t *obj);
+
+/**@}*/
+
+#if DEVICE_SPI_ASYNCH
+/**
+ * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
+ *
+ * @param[in] obj       The SPI object that holds the transfer information
+ * @param[in] tx        The transmit buffer
+ * @param[in] tx_length The number of bytes to transmit
+ * @param[in] rx        The receive buffer
+ * @param[in] rx_length The number of bytes to receive
+ * @param[in] bit_width The bit width of buffer words
+ * @param[in] event     The logical OR of events to be registered
+ * @param[in] handler   SPI interrupt handler
+ * @param[in] hint      A suggestion for how to use DMA with this transfer
+ */
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** The asynchronous IRQ handler
+ *
+ * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
+ * conditions, such as buffer overflows or transfer complete.
+ * @param[in] obj     The SPI object that holds the transfer information
+ * @return Event flags if a transfer termination condition was met; otherwise 0.
+ */
+uint32_t spi_irq_handler_asynch(spi_t *obj);
+
+/** Attempts to determine if the SPI peripheral is already in use
+ *
+ * If a temporary DMA channel has been allocated, peripheral is in use.
+ * If a permanent DMA channel has been allocated, check if the DMA channel is in use.  If not, proceed as though no DMA
+ * channel were allocated.
+ * If no DMA channel is allocated, check whether tx and rx buffers have been assigned.  For each assigned buffer, check
+ * if the corresponding buffer position is less than the buffer length.  If buffers do not indicate activity, check if
+ * there are any bytes in the FIFOs.
+ * @param[in] obj The SPI object to check for activity
+ * @return Non-zero if the SPI port is active or zero if it is not.
+ */
+uint8_t spi_active(spi_t *obj);
+
+/** Abort an SPI transfer
+ *
+ * @param obj The SPI peripheral to stop
+ */
+void spi_abort_asynch(spi_t *obj);
+
+
+#endif
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // SPI_DEVICE
+
+#endif // MBED_SPI_API_H
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/storage_abstraction/Driver_Common.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_COMMON_H
+#define __DRIVER_COMMON_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct _ARM_DRIVER_VERSION {
+  uint16_t api;                         ///< API version
+  uint16_t drv;                         ///< Driver version
+} ARM_DRIVER_VERSION;
+
+/* General return codes */
+#define ARM_DRIVER_OK                 0 ///< Operation succeeded
+#define ARM_DRIVER_ERROR             -1 ///< Unspecified error
+#define ARM_DRIVER_ERROR_BUSY        -2 ///< Driver is busy
+#define ARM_DRIVER_ERROR_TIMEOUT     -3 ///< Timeout occurred
+#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
+#define ARM_DRIVER_ERROR_PARAMETER   -5 ///< Parameter error
+#define ARM_DRIVER_ERROR_SPECIFIC    -6 ///< Start of driver specific errors
+
+/**
+\brief General power states
+*/
+typedef enum _ARM_POWER_STATE {
+  ARM_POWER_OFF,                        ///< Power off: no operation possible
+  ARM_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+  ARM_POWER_FULL                        ///< Power on: full operation at maximum performance
+} ARM_POWER_STATE;
+
+#endif /* __DRIVER_COMMON_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/storage_abstraction/Driver_Storage.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,769 @@
+/*
+ * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DRIVER_STORAGE_H
+#define __DRIVER_STORAGE_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif // __cplusplus
+
+#include "Driver_Common.h"
+
+#define ARM_STORAGE_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,00)  /* API version */
+
+
+#define _ARM_Driver_Storage_(n)      Driver_Storage##n
+#define  ARM_Driver_Storage_(n) _ARM_Driver_Storage_(n)
+
+#define ARM_STORAGE_INVALID_OFFSET  (0xFFFFFFFFFFFFFFFFULL) ///< Invalid address (relative to a storage controller's
+                                                            ///< address space). A storage block may never start at this address.
+
+#define ARM_STORAGE_INVALID_ADDRESS (0xFFFFFFFFUL)          ///< Invalid address within the processor's memory address space.
+                                                            ///< Refer to memory-mapped storage, i.e. < \ref ARM_DRIVER_STORAGE::ResolveAddress().
+
+/****** Storage specific error codes *****/
+#define ARM_STORAGE_ERROR_NOT_ERASABLE      (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Part (or all) of the range provided to Erase() isn't erasable.
+#define ARM_STORAGE_ERROR_NOT_PROGRAMMABLE  (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Part (or all) of the range provided to ProgramData() isn't programmable.
+#define ARM_STORAGE_ERROR_PROTECTED         (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Part (or all) of the range to Erase() or ProgramData() is protected.
+#define ARM_STORAGE_ERROR_RUNTIME_OR_INTEGRITY_FAILURE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Runtime or sanity-check failure.
+
+/**
+ * \brief Attributes of the storage range within a storage block.
+ */
+typedef struct _ARM_STORAGE_BLOCK_ATTRIBUTES {
+  uint32_t erasable      :  1;   ///< Erasing blocks is permitted with a minimum granularity of 'erase_unit'.
+                                 ///<   @note: if 'erasable' is 0--i.e. the 'erase' operation isn't available--then
+                                 ///<   'erase_unit' (see below) is immaterial and should be 0.
+  uint32_t programmable  :  1;   ///< Writing to ranges is permitted with a minimum granularity of 'program_unit'.
+                                 ///<   Writes are typically achieved through the ProgramData operation (following an erase);
+                                 ///<   if storage isn't erasable (see 'erasable' above) but is memory-mapped
+                                 ///<   (i.e. 'memory_mapped'), it can be written directly using memory-store operations.
+  uint32_t executable    :  1;   ///< This storage block can hold program data; the processor can fetch and execute code
+                                 ///<   sourced from it. Often this is accompanied with the device being 'memory_mapped' (see \ref ARM_STORAGE_INFO).
+  uint32_t protectable   :  1;   ///< The entire block can be protected from program and erase operations. Once protection
+                                 ///<   is enabled for a block, its 'erasable' and 'programmable' bits are turned off.
+  uint32_t reserved      : 28;
+  uint32_t erase_unit;           ///< Minimum erase size in bytes.
+                                 ///<   The offset of the start of the erase-range should also be aligned with this value.
+                                 ///<   Applicable if the 'erasable' attribute is set for the block.
+                                 ///<   @note: if 'erasable' (see above) is 0--i.e. the 'erase' operation isn't available--then
+                                 ///<   'erase_unit' is immaterial and should be 0.
+  uint32_t protection_unit;      ///< Minimum protectable size in bytes. Applicable if the 'protectable'
+                                 ///<   attribute is set for the block. This should be a divisor of the block's size. A
+                                 ///<   block can be considered to be made up of consecutive, individually-protectable fragments.
+} ARM_STORAGE_BLOCK_ATTRIBUTES;
+
+/**
+ * \brief A storage block is a range of memory with uniform attributes. Storage blocks
+ * combine to make up the address map of a storage controller.
+ */
+typedef struct _ARM_STORAGE_BLOCK {
+  uint64_t                     addr;       ///< This is the start address of the storage block. It is
+                                           ///<   expressed as an offset from the start of the storage map
+                                           ///<   maintained by the owning storage controller.
+  uint64_t                     size;       ///< This is the size of the storage block, in units of bytes.
+                                           ///<   Together with addr, it describes a range [addr, addr+size).
+  ARM_STORAGE_BLOCK_ATTRIBUTES attributes; ///< Attributes for this block.
+} ARM_STORAGE_BLOCK;
+
+/**
+ * The check for a valid ARM_STORAGE_BLOCK.
+ */
+#define ARM_STORAGE_VALID_BLOCK(BLK) (((BLK)->addr != ARM_STORAGE_INVALID_OFFSET) && ((BLK)->size != 0))
+
+/**
+ * \brief Values for encoding storage memory-types with respect to programmability.
+ *
+ * Please ensure that the maximum of the following memory types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::programmability.
+ */
+#define ARM_STORAGE_PROGRAMMABILITY_RAM       (0x0)
+#define ARM_STORAGE_PROGRAMMABILITY_ROM       (0x1) ///< Read-only memory.
+#define ARM_STORAGE_PROGRAMMABILITY_WORM      (0x2) ///< write-once-read-only-memory (WORM).
+#define ARM_STORAGE_PROGRAMMABILITY_ERASABLE  (0x3) ///< re-programmable based on erase. Supports multiple writes.
+
+/**
+ * Values for encoding data-retention levels for storage blocks.
+ *
+ * Please ensure that the maximum of the following retention types doesn't exceed 16; we
+ * encode this in a 4-bit field within ARM_STORAGE_INFO::retention_level.
+ */
+#define ARM_RETENTION_WHILE_DEVICE_ACTIVE     (0x0) ///< Data is retained only during device activity.
+#define ARM_RETENTION_ACROSS_SLEEP            (0x1) ///< Data is retained across processor sleep.
+#define ARM_RETENTION_ACROSS_DEEP_SLEEP       (0x2) ///< Data is retained across processor deep-sleep.
+#define ARM_RETENTION_BATTERY_BACKED          (0x3) ///< Data is battery-backed. Device can be powered off.
+#define ARM_RETENTION_NVM                     (0x4) ///< Data is retained in non-volatile memory.
+
+/**
+ * Device Data Security Protection Features. Applicable mostly to EXTERNAL_NVM.
+ */
+typedef struct _ARM_STORAGE_SECURITY_FEATURES {
+  uint32_t acls                :  1; ///< Protection against internal software attacks using ACLs.
+  uint32_t rollback_protection :  1; ///< Roll-back protection. Set to true if the creator of the storage
+                                     ///<   can ensure that an external attacker can't force an
+                                     ///<   older firmware to run or to revert back to a previous state.
+  uint32_t tamper_proof        :  1; ///< Tamper-proof memory (will be deleted on tamper-attempts using board level or chip level sensors).
+  uint32_t internal_flash      :  1; ///< Internal flash.
+  uint32_t reserved1           : 12;
+
+  /**
+   * Encode support for hardening against various classes of attacks.
+   */
+  uint32_t software_attacks     :  1; ///< device software (malware running on the device).
+  uint32_t board_level_attacks  :  1; ///< board level attacks (debug probes, copy protection fuses.)
+  uint32_t chip_level_attacks   :  1; ///< chip level attacks (tamper-protection).
+  uint32_t side_channel_attacks :  1; ///< side channel attacks.
+  uint32_t reserved2            : 12;
+} ARM_STORAGE_SECURITY_FEATURES;
+
+#define ARM_STORAGE_PROGRAM_CYCLES_INFINITE (0UL) /**< Infinite or unknown endurance for reprogramming. */
+
+/**
+ * \brief Storage information. This contains device-metadata. It is the return
+ *     value from calling GetInfo() on the storage driver.
+ *
+ * \details These fields serve a different purpose than the ones contained in
+ *     \ref ARM_STORAGE_CAPABILITIES, which is another structure containing
+ *     device-level metadata. ARM_STORAGE_CAPABILITIES describes the API
+ *     capabilities, whereas ARM_STORAGE_INFO describes the device. Furthermore
+ *     ARM_STORAGE_CAPABILITIES fits within a single word, and is designed to be
+ *     passed around by value; ARM_STORAGE_INFO, on the other hand, contains
+ *     metadata which doesn't fit into a single word and requires the use of
+ *     pointers to be moved around.
+ */
+typedef struct _ARM_STORAGE_INFO {
+  uint64_t                      total_storage;        ///< Total available storage, in bytes.
+  uint32_t                      program_unit;         ///< Minimum programming size in bytes.
+                                                      ///<   The offset of the start of the program-range should also be aligned with this value.
+                                                      ///<   Applicable only if the 'programmable' attribute is set for a block.
+                                                      ///<   @note: setting program_unit to 0 has the effect of disabling the size and alignment
+                                                      ///<   restrictions (setting it to 1 also has the same effect).
+  uint32_t                      optimal_program_unit; ///< Optimal programming page-size in bytes. Some storage controllers
+                                                      ///<   have internal buffers into which to receive data. Writing in chunks of
+                                                      ///<   'optimal_program_unit' would achieve maximum programming speed.
+                                                      ///<   Applicable only if the 'programmable' attribute is set for the underlying block(s).
+  uint32_t                      program_cycles;       ///< A measure of endurance for reprogramming.
+                                                      ///<   Use ARM_STORAGE_PROGRAM_CYCLES_INFINITE for infinite or unknown endurance.
+  uint32_t                      erased_value    :  1; ///< Contents of erased memory (usually 1 to indicate erased bytes with state 0xFF).
+  uint32_t                      memory_mapped   :  1; ///< This storage device has a mapping onto the processor's memory address space.
+                                                      ///<   @note: For a memory-mapped block which isn't erasable but is programmable (i.e. if
+                                                      ///<   'erasable' is set to 0, but 'programmable' is 1), writes should be possible directly to
+                                                      ///<   the memory-mapped storage without going through the ProgramData operation.
+  uint32_t                      programmability :  4; ///< A value to indicate storage programmability.
+  uint32_t                      retention_level :  4;
+  uint32_t                      reserved        : 22;
+  ARM_STORAGE_SECURITY_FEATURES security;             ///< \ref ARM_STORAGE_SECURITY_FEATURES
+} ARM_STORAGE_INFO;
+
+/**
+\brief Operating status of the storage controller.
+*/
+typedef struct _ARM_STORAGE_STATUS {
+  uint32_t busy  : 1;                   ///< Controller busy flag
+  uint32_t error : 1;                   ///< Read/Program/Erase error flag (cleared on start of next operation)
+} ARM_STORAGE_STATUS;
+
+/**
+ * \brief Storage Driver API Capabilities.
+ *
+ * This data structure is designed to fit within a single word so that it can be
+ * fetched cheaply using a call to driver->GetCapabilities().
+ */
+typedef struct _ARM_STORAGE_CAPABILITIES {
+  uint32_t asynchronous_ops :  1; ///< Used to indicate if APIs like initialize,
+                                  ///<   read, erase, program, etc. can operate in asynchronous mode.
+                                  ///<   Setting this bit to 1 means that the driver is capable
+                                  ///<   of launching asynchronous operations; command completion is
+                                  ///<   signaled by the invocation of a completion callback. If
+                                  ///<   set to 1, drivers may still complete asynchronous
+                                  ///<   operations synchronously as necessary--in which case they
+                                  ///<   return a positive error code to indicate synchronous completion.
+  uint32_t erase_all        :  1; ///< Supports EraseAll operation.
+  uint32_t reserved         : 30;
+} ARM_STORAGE_CAPABILITIES;
+
+/**
+ * Command opcodes for Storage. Completion callbacks use these codes to refer to
+ * completing commands. Refer to \ref ARM_Storage_Callback_t.
+ */
+typedef enum _ARM_STORAGE_OPERATION {
+  ARM_STORAGE_OPERATION_GET_VERSION,
+  ARM_STORAGE_OPERATION_GET_CAPABILITIES,
+  ARM_STORAGE_OPERATION_INITIALIZE,
+  ARM_STORAGE_OPERATION_UNINITIALIZE,
+  ARM_STORAGE_OPERATION_POWER_CONTROL,
+  ARM_STORAGE_OPERATION_READ_DATA,
+  ARM_STORAGE_OPERATION_PROGRAM_DATA,
+  ARM_STORAGE_OPERATION_ERASE,
+  ARM_STORAGE_OPERATION_ERASE_ALL,
+  ARM_STORAGE_OPERATION_GET_STATUS,
+  ARM_STORAGE_OPERATION_GET_INFO,
+  ARM_STORAGE_OPERATION_RESOLVE_ADDRESS,
+  ARM_STORAGE_OPERATION_GET_NEXT_BLOCK,
+  ARM_STORAGE_OPERATION_GET_BLOCK
+} ARM_STORAGE_OPERATION;
+
+/**
+ * Declaration of the callback-type for command completion.
+ *
+ * @param [in] status
+ *               A code to indicate the status of the completed operation. For data
+ *               transfer operations, the status field is overloaded in case of
+ *               success to return the count of items successfully transferred; this
+ *               can be done safely because error codes are negative values.
+ *
+ * @param [in] operation
+ *               The command op-code. This value isn't essential for the callback in
+ *               the presence of the command instance-id, but it is expected that
+ *               this information could be a quick and useful filter.
+ */
+typedef void (*ARM_Storage_Callback_t)(int32_t status, ARM_STORAGE_OPERATION operation);
+
+/**
+ * This is the set of operations constituting the Storage driver. Their
+ * implementation is platform-specific, and needs to be supplied by the
+ * porting effort.
+ *
+ * Some APIs within `ARM_DRIVER_STORAGE` will always operate synchronously:
+ * GetVersion, GetCapabilities, GetStatus, GetInfo, ResolveAddress,
+ * GetNextBlock, and GetBlock. This means that control returns to the caller
+ * with a relevant status code only after the completion of the operation (or
+ * the discovery of a failure condition).
+ *
+ * The remainder of the APIs: Initialize, Uninitialize, PowerControl, ReadData,
+ * ProgramData, Erase, EraseAll, can function asynchronously if the underlying
+ * controller supports it--i.e. if ARM_STORAGE_CAPABILITIES::asynchronous_ops is
+ * set. In the case of asynchronous operation, the invocation returns early
+ * (with ARM_DRIVER_OK) and results in a completion callback later. If
+ * ARM_STORAGE_CAPABILITIES::asynchronous_ops is not set, then all such APIs
+ * execute synchronously, and control returns to the caller with a status code
+ * only after the completion of the operation (or the discovery of a failure
+ * condition).
+ *
+ * If ARM_STORAGE_CAPABILITIES::asynchronous_ops is set, a storage driver may
+ * still choose to execute asynchronous operations in a synchronous manner. If
+ * so, the driver returns a positive value to indicate successful synchronous
+ * completion (or an error code in case of failure) and no further invocation of
+ * completion callback should be expected. The expected return value for
+ * synchronous completion of such asynchronous operations varies depending on
+ * the operation. For operations involving data access, it often equals the
+ * amount of data transferred or affected. For non data-transfer operations,
+ * such as EraseAll or Initialize, it is usually 1.
+ *
+ * Here's a code snippet to suggest how asynchronous APIs might be used by
+ * callers to handle both synchronous and asynchronous execution by the
+ * underlying storage driver:
+ * \code
+ *     ASSERT(ARM_DRIVER_OK == 0); // this is a precondition; it doesn't need to be put in code
+ *     int32_t returnValue = drv->asynchronousAPI(...);
+ *     if (returnValue < ARM_DRIVER_OK) {
+ *         // handle error.
+ *     } else if (returnValue == ARM_DRIVER_OK) {
+ *         ASSERT(drv->GetCapabilities().asynchronous_ops == 1);
+ *         // handle early return from asynchronous execution; remainder of the work is done in the callback handler.
+ *     } else {
+ *         ASSERT(returnValue == EXPECTED_RETURN_VALUE_FOR_SYNCHRONOUS_COMPLETION);
+ *         // handle synchronous completion.
+ *     }
+ * \endcode
+ */
+typedef struct _ARM_DRIVER_STORAGE {
+  /**
+   * \brief Get driver version.
+   *
+   * The function GetVersion() returns version information of the driver implementation in ARM_DRIVER_VERSION.
+   *
+   *    - API version is the version of the CMSIS-Driver specification used to implement this driver.
+   *    - Driver version is source code version of the actual driver implementation.
+   *
+   * Example:
+   * \code
+   *     extern ARM_DRIVER_STORAGE *drv_info;
+   *
+   *     void read_version (void)  {
+   *       ARM_DRIVER_VERSION  version;
+   *
+   *       version = drv_info->GetVersion ();
+   *       if (version.api < 0x10A)   {      // requires at minimum API version 1.10 or higher
+   *         // error handling
+   *         return;
+   *       }
+   *     }
+   * \endcode
+   *
+   * @return \ref ARM_DRIVER_VERSION.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   *
+   * @note The function GetVersion() can be called any time to obtain the
+   *     required information from the driver (even before initialization). It
+   *     always returns the same information.
+   */
+  ARM_DRIVER_VERSION (*GetVersion)(void);
+
+  /**
+   * \brief Get driver capabilities.
+   *
+   * \details The function GetCapabilities() returns information about
+   * capabilities in this driver implementation. The data fields of the struct
+   * ARM_STORAGE_CAPABILITIES encode various capabilities, for example if the device
+   * is able to execute operations asynchronously.
+   *
+   * Example:
+   * \code
+   *     extern ARM_DRIVER_STORAGE *drv_info;
+   *
+   *     void read_capabilities (void)  {
+   *       ARM_STORAGE_CAPABILITIES drv_capabilities;
+   *
+   *       drv_capabilities = drv_info->GetCapabilities ();
+   *       // interrogate capabilities
+   *
+   *     }
+   * \endcode
+   *
+   * @return \ref ARM_STORAGE_CAPABILITIES.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   *
+   * @note The function GetCapabilities() can be called any time to obtain the
+   *     required information from the driver (even before initialization). It
+   *     always returns the same information.
+   */
+  ARM_STORAGE_CAPABILITIES (*GetCapabilities)(void);
+
+  /**
+   * \brief Initialize the Storage Interface.
+   *
+   * The function Initialize is called when the middleware component starts
+   * operation. In addition to bringing the controller to a ready state,
+   * Initialize() receives a callback handler to be invoked upon completion of
+   * asynchronous operations.
+   *
+   * Initialize() needs to be called explicitly before
+   * powering the peripheral using PowerControl(), and before initiating other
+   * accesses to the storage controller.
+   *
+   * The function performs the following operations:
+   *   - Initializes the resources needed for the Storage interface.
+   *   - Registers the \ref ARM_Storage_Callback_t callback function.
+   *
+   * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
+   *     drv->Initialize (...); // Allocate I/O pins
+   *     drv->PowerControl (ARM_POWER_FULL);        // Power up peripheral, setup IRQ/DMA
+   *
+   * - Initialize() typically allocates the I/O resources (pins) for the
+   *   peripheral. The function can be called multiple times; if the I/O resources
+   *   are already initialized it performs no operation and just returns with
+   *   ARM_DRIVER_OK.
+   *
+   * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
+   *   interrupt (NVIC) and optionally DMA. The function can be called multiple
+   *   times; if the registers are already set it performs no operation and just
+   *   returns with ARM_DRIVER_OK.
+   *
+   * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
+   *     drv->PowerControl (ARM_POWER_OFF);     // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
+   *     drv->Uninitialize (...);               // Release I/O pins
+   *
+   * The functions PowerControl and Uninitialize always execute and can be used
+   * to put the peripheral into a Safe State, for example after any data
+   * transmission errors. To restart the peripheral in an error condition,
+   * you should first execute the Stop Sequence and then the Start Sequence.
+   *
+   * @param [in] callback
+   *               Caller-defined callback to be invoked upon command completion
+   *               for asynchronous APIs (including the completion of
+   *               initialization). Use a NULL pointer when no callback
+   *               signals are required.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with a status value of ARM_DRIVER_OK or an error-code. In the
+   *     case of synchronous execution, control returns after completion with a
+   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*Initialize)(ARM_Storage_Callback_t callback);
+
+  /**
+   * \brief De-initialize the Storage Interface.
+   *
+   * The function Uninitialize() de-initializes the resources of Storage interface.
+   *
+   * It is called when the middleware component stops operation, and wishes to
+   * release the software resources used by the interface.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with a status value of ARM_DRIVER_OK or an error-code. In the
+   *     case of synchronous execution, control returns after completion with a
+   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*Uninitialize)(void);
+
+  /**
+   * \brief Control the Storage interface power.
+   *
+   * The function \b ARM_Storage_PowerControl operates the power modes of the Storage interface.
+   *
+   * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
+   *     drv->Initialize (...);                 // Allocate I/O pins
+   *     drv->PowerControl (ARM_POWER_FULL);    // Power up peripheral, setup IRQ/DMA
+   *
+   * - Initialize() typically allocates the I/O resources (pins) for the
+   *   peripheral. The function can be called multiple times; if the I/O resources
+   *   are already initialized it performs no operation and just returns with
+   *   ARM_DRIVER_OK.
+   *
+   * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
+   *   interrupt (NVIC) and optionally DMA. The function can be called multiple
+   *   times; if the registers are already set it performs no operation and just
+   *   returns with ARM_DRIVER_OK.
+   *
+   * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
+   *
+   *     drv->PowerControl (ARM_POWER_OFF);     // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
+   *     drv->Uninitialize (...);               // Release I/O pins
+   *
+   * The functions PowerControl and Uninitialize always execute and can be used
+   * to put the peripheral into a Safe State, for example after any data
+   * transmission errors. To restart the peripheral in an error condition,
+   * you should first execute the Stop Sequence and then the Start Sequence.
+   *
+   * @param state
+   *          \ref ARM_POWER_STATE. The target power-state for the storage controller.
+   *          The parameter state can have the following values:
+   *              - ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts
+   *                                 (NVIC) and optionally DMA. Can be called multiple times. If the peripheral
+   *                                 is already in this mode, then the function performs no operation and returns
+   *                                 with ARM_DRIVER_OK.
+   *              - ARM_POWER_LOW : may use power saving. Returns ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.
+   *              - ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with a status value of ARM_DRIVER_OK or an error-code. In the
+   *     case of synchronous execution, control returns after completion with a
+   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*PowerControl)(ARM_POWER_STATE state);
+
+  /**
+   * \brief read the contents of a given address range from the storage device.
+   *
+   * \details Read the contents of a range of storage memory into a buffer
+   *   supplied by the caller. The buffer is owned by the caller and should
+   *   remain accessible for the lifetime of this command.
+   *
+   * @param  [in] addr
+   *                This specifies the address from where to read data.
+   *
+   * @param [out] data
+   *                The destination of the read operation. The buffer
+   *                is owned by the caller and should remain accessible for the
+   *                lifetime of this command.
+   *
+   * @param  [in] size
+   *                The number of bytes requested to read. The data buffer
+   *                should be at least as large as this size.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with the number of successfully transferred bytes passed in as
+   *     the 'status' parameter. In the case of synchronous execution, control
+   *     returns after completion with a positive transfer-count. Return values
+   *     less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*ReadData)(uint64_t addr, void *data, uint32_t size);
+
+  /**
+   * \brief program (write into) the contents of a given address range of the storage device.
+   *
+   * \details Write the contents of a given memory buffer into a range of
+   *   storage memory. In the case of flash memory, the destination range in
+   *   storage memory typically has its contents in an erased state from a
+   *   preceding erase operation. The source memory buffer is owned by the
+   *   caller and should remain accessible for the lifetime of this command.
+   *
+   * @param [in] addr
+   *               This is the start address of the range to be written into. It
+   *               needs to be aligned to the device's \em program_unit
+   *               specified in \ref ARM_STORAGE_INFO.
+   *
+   * @param [in] data
+   *               The source of the write operation. The buffer is owned by the
+   *               caller and should remain accessible for the lifetime of this
+   *               command.
+   *
+   * @param [in] size
+   *               The number of bytes requested to be written. The buffer
+   *               should be at least as large as this size. \note 'size' should
+   *               be a multiple of the device's 'program_unit' (see \ref
+   *               ARM_STORAGE_INFO).
+   *
+   * @note It is best for the middleware to write in units of
+   *     'optimal_program_unit' (\ref ARM_STORAGE_INFO) of the device.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with the number of successfully transferred bytes passed in as
+   *     the 'status' parameter. In the case of synchronous execution, control
+   *     returns after completion with a positive transfer-count. Return values
+   *     less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*ProgramData)(uint64_t addr, const void *data, uint32_t size);
+
+  /**
+   * @brief Erase Storage range.
+   *
+   * @details This function erases a range of storage specified by [addr, addr +
+   *     size). Both 'addr' and 'addr + size' should align with the
+   *     'erase_unit'(s) of the respective owning storage block(s) (see \ref
+   *     ARM_STORAGE_BLOCK and \ref ARM_STORAGE_BLOCK_ATTRIBUTES). The range to
+   *     be erased will have its contents returned to the un-programmed state--
+   *     i.e. to 'erased_value' (see \ref ARM_STORAGE_BLOCK_ATTRIBUTES), which
+   *     is usually 1 to indicate the pattern of all ones: 0xFF.
+   *
+   * @param [in] addr
+   *               This is the start-address of the range to be erased. It must
+   *               start at an 'erase_unit' boundary of the underlying block.
+   *
+   * @param [in] size
+   *               Size (in bytes) of the range to be erased. 'addr + size'
+   *               must be aligned with the 'erase_unit' of the underlying
+   *               block.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return
+   *   If the range to be erased doesn't align with the erase_units of the
+   *   respective start and end blocks, ARM_DRIVER_ERROR_PARAMETER is returned.
+   *   If any part of the range is protected, ARM_STORAGE_ERROR_PROTECTED is
+   *   returned. If any part of the range is not erasable,
+   *   ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All such sanity-check
+   *   failures result in the error code being returned synchronously and the
+   *   storage bytes within the range remain unaffected.
+   *   Otherwise the function executes in the following ways:
+   *     If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with the number of successfully erased bytes passed in as
+   *     the 'status' parameter. In the case of synchronous execution, control
+   *     returns after completion with a positive erase-count. Return values
+   *     less than ARM_DRIVER_OK (0) signify errors.
+   *
+   * @note Erase() may return a smaller (positive) value than the size of the
+   *     requested range. The returned value indicates the actual number of bytes
+   *     erased. It is the caller's responsibility to follow up with an appropriate
+   *     request to complete the operation.
+   *
+   * @note in the case of a failed erase (except when
+   *     ARM_DRIVER_ERROR_PARAMETER, ARM_STORAGE_ERROR_PROTECTED, or
+   *     ARM_STORAGE_ERROR_NOT_ERASABLE is returned synchronously), the
+   *     requested range should be assumed to be in an unknown state. The
+   *     previous contents may not be retained.
+   */
+  int32_t (*Erase)(uint64_t addr, uint32_t size);
+
+  /**
+   * @brief Erase complete storage. Optional function for faster erase of the complete device.
+   *
+   * This optional function erases the complete device. If the device does not
+   *    support global erase then the function returns the error value \ref
+   *    ARM_DRIVER_ERROR_UNSUPPORTED. The data field \em 'erase_all' =
+   *    \token{1} of the structure \ref ARM_STORAGE_CAPABILITIES encodes that
+   *    \ref ARM_STORAGE_EraseAll is supported.
+   *
+   * @note This API may execute asynchronously if
+   *     ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
+   *     execution is optional even if 'asynchronous_ops' is set.
+   *
+   * @return
+   *   If any part of the storage range is protected,
+   *   ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the storage
+   *   range is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All
+   *   such sanity-check failures result in the error code being returned
+   *   synchronously and the storage bytes within the range remain unaffected.
+   *   Otherwise the function executes in the following ways:
+   *     If asynchronous activity is launched, an invocation returns
+   *     ARM_DRIVER_OK, and the caller can expect to receive a callback in the
+   *     future with ARM_DRIVER_OK passed in as the 'status' parameter. In the
+   *     case of synchronous execution, control returns after completion with a
+   *     value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
+   */
+  int32_t (*EraseAll)(void);
+
+  /**
+   * @brief Get the status of the current (or previous) command executed by the
+   *     storage controller; stored in the structure \ref ARM_STORAGE_STATUS.
+   *
+   * @return
+   *          The status of the underlying controller.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   */
+  ARM_STORAGE_STATUS (*GetStatus)(void);
+
+  /**
+   * @brief Get information about the Storage device; stored in the structure \ref ARM_STORAGE_INFO.
+   *
+   * @param [out] info
+   *                A caller-supplied buffer capable of being filled in with an
+   *                \ref ARM_STORAGE_INFO.
+   *
+   * @return ARM_DRIVER_OK if a ARM_STORAGE_INFO structure containing top level
+   *         metadata about the storage controller is filled into the supplied
+   *         buffer, else an appropriate error value.
+   *
+   * @note It is the caller's responsibility to ensure that the buffer passed in
+   *         is able to be initialized with a \ref ARM_STORAGE_INFO.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   */
+  int32_t (*GetInfo)(ARM_STORAGE_INFO *info);
+
+  /**
+   * \brief For memory-mapped storage, resolve an address relative to
+   *     the storage controller into a memory address.
+   *
+   * @param addr
+   *          This is the address for which we want a resolution to the
+   *          processor's physical address space. It is an offset from the
+   *          start of the storage map maintained by the owning storage
+   *          controller.
+   *
+   * @return
+   *          The resolved address in the processor's address space; else
+   *          ARM_STORAGE_INVALID_ADDRESS, if no resolution is possible.
+   *
+   * @note This API returns synchronously. The invocation should return quickly,
+   *     and result in a resolved address.
+   */
+  uint32_t (*ResolveAddress)(uint64_t addr);
+
+  /**
+   * @brief Advance to the successor of the current block (iterator), or fetch
+   *     the first block (if 'prev_block' is passed in as NULL).
+   *
+   * @details This helper function fetches (an iterator to) the next block (or
+   *     the first block if 'prev_block' is passed in as NULL). In the failure
+   *     case, a terminating, invalid block iterator is filled into the out
+   *     parameter: 'next_block'. In combination with \ref
+   *     ARM_STORAGE_VALID_BLOCK(), it can be used to iterate over the sequence
+   *     of blocks within the storage map:
+   *
+   * \code
+   *   ARM_STORAGE_BLOCK block;
+   *   for (drv->GetNextBlock(NULL, &block); ARM_STORAGE_VALID_BLOCK(&block); drv->GetNextBlock(&block, &block)) {
+   *       // make use of block
+   *   }
+   * \endcode
+   *
+   * @param[in]  prev_block
+   *               An existing block (iterator) within the same storage
+   *               controller. The memory buffer holding this block is owned
+   *               by the caller. This pointer may be NULL; if so, the
+   *               invocation fills in the first block into the out parameter:
+   *               'next_block'.
+   *
+   * @param[out] next_block
+   *               A caller-owned buffer large enough to be filled in with
+   *               the following ARM_STORAGE_BLOCK. It is legal to provide the
+   *               same buffer using 'next_block' as was passed in with 'prev_block'. It
+   *               is also legal to pass a NULL into this parameter if the
+   *               caller isn't interested in populating a buffer with the next
+   *               block--i.e. if the caller only wishes to establish the
+   *               presence of a next block.
+   *
+   * @return ARM_DRIVER_OK if a valid next block is found (or first block, if
+   *     prev_block is passed as NULL); upon successful operation, the contents
+   *     of the next (or first) block are filled into the buffer pointed to by
+   *     the parameter 'next_block' and ARM_STORAGE_VALID_BLOCK(next_block) is
+   *     guaranteed to be true. Upon reaching the end of the sequence of blocks
+   *     (iterators), or in case the driver is unable to fetch information about
+   *     the next (or first) block, an error (negative) value is returned and an
+   *     invalid StorageBlock is populated into the supplied buffer. If
+   *     prev_block is NULL, the first block is returned.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   */
+   int32_t (*GetNextBlock)(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block);
+
+  /**
+   * @brief Find the storage block (iterator) encompassing a given storage address.
+   *
+   * @param[in]  addr
+   *               Storage address in bytes.
+   *
+   * @param[out] block
+   *               A caller-owned buffer large enough to be filled in with the
+   *               ARM_STORAGE_BLOCK encapsulating the given address. This value
+   *               can also be passed in as NULL if the caller isn't interested
+   *               in populating a buffer with the block--if the caller only
+   *               wishes to establish the presence of a containing storage
+   *               block.
+   *
+   * @return ARM_DRIVER_OK if a containing storage-block is found. In this case,
+   *     if block is non-NULL, the buffer pointed to by it is populated with
+   *     the contents of the storage block--i.e. if block is valid and a block is
+   *     found, ARM_STORAGE_VALID_BLOCK(block) would return true following this
+   *     call. If there is no storage block containing the given offset, or in
+   *     case the driver is unable to resolve an address to a storage-block, an
+   *     error (negative) value is returned and an invalid StorageBlock is
+   *     populated into the supplied buffer.
+   *
+   * @note This API returns synchronously--it does not result in an invocation
+   *     of a completion callback.
+   */
+  int32_t (*GetBlock)(uint64_t addr, ARM_STORAGE_BLOCK *block);
+} const ARM_DRIVER_STORAGE;
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif /* __DRIVER_STORAGE_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/ticker_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,117 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_API_H
+#define MBED_TICKER_API_H
+
+#include <stdint.h>
+#include "device.h"
+
+typedef uint32_t timestamp_t;
+
+/** Ticker's event structure
+ */
+typedef struct ticker_event_s {
+    timestamp_t            timestamp; /**< Event's timestamp */
+    uint32_t               id;        /**< TimerEvent object */
+    struct ticker_event_s *next;      /**< Next event in the queue */
+} ticker_event_t;
+
+typedef void (*ticker_event_handler)(uint32_t id);
+
+/** Ticker's interface structure - required API for a ticker
+ */
+typedef struct {
+    void (*init)(void);                           /**< Init function */
+    uint32_t (*read)(void);                       /**< Read function */
+    void (*disable_interrupt)(void);              /**< Disable interrupt function */
+    void (*clear_interrupt)(void);                /**< Clear interrupt function */
+    void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
+} ticker_interface_t;
+
+/** Ticker's event queue structure
+ */
+typedef struct {
+    ticker_event_handler event_handler; /**< Event handler */
+    ticker_event_t *head;               /**< A pointer to head */
+} ticker_event_queue_t;
+
+/** Ticker's data structure
+ */
+typedef struct {
+    const ticker_interface_t *interface; /**< Ticker's interface */
+    ticker_event_queue_t *queue;         /**< Ticker's event queue */
+} ticker_data_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_ticker Ticker HAL functions
+ * @{
+ */
+
+/** Initialize a ticker and set the event handler
+ *
+ * @param data    The ticker's data
+ * @param handler A handler to be set
+ */
+void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler);
+
+/** IRQ handler that goes through the events to trigger overdue events.
+ *
+ * @param data    The ticker's data
+ */
+void ticker_irq_handler(const ticker_data_t *const data);
+
+/** Remove an event from the queue
+ *
+ * @param data The ticker's data
+ * @param obj  The event object to be removed from the queue
+ */
+void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj);
+
+/** Insert an event to the queue
+ *
+ * @param data      The ticker's data
+ * @param obj       The event object to be inserted to the queue
+ * @param timestamp The event's timestamp
+ * @param id        The event object
+ */
+void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
+
+/** Read the current ticker's timestamp
+ *
+ * @param data The ticker's data
+ * @return The current timestamp
+ */
+timestamp_t ticker_read(const ticker_data_t *const data);
+
+/** Read the next event's timestamp
+ *
+ * @param data The ticker's data
+ * @return 1 if timestamp is pending event, 0 if there's no event pending
+ */
+int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/hal/us_ticker_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_US_TICKER_API_H
+#define MBED_US_TICKER_API_H
+
+#include <stdint.h>
+#include "ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_UsTicker Microseconds Ticker Functions
+ * @{
+ */
+
+/** Get ticker's data
+ *
+ * @return The low power ticker data
+ */
+const ticker_data_t* get_us_ticker_data(void);
+
+
+/** The wrapper for ticker_irq_handler, to pass us ticker's data
+ *
+ */
+void us_ticker_irq_handler(void);
+
+/* HAL us ticker */
+
+/** Initialize the ticker
+ *
+ */
+void us_ticker_init(void);
+
+/** Read the current counter
+ *
+ * @return The current timer's counter value in microseconds
+ */
+uint32_t us_ticker_read(void);
+
+/** Set interrupt for specified timestamp
+ *
+ * @param timestamp The time in microseconds to be set
+ */
+void us_ticker_set_interrupt(timestamp_t timestamp);
+
+/** Disable us ticker interrupt
+ *
+ */
+void us_ticker_disable_interrupt(void);
+
+/** Clear us ticker interrupt
+ *
+ */
+void us_ticker_clear_interrupt(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/RZ_A1_Init.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,705 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         RZ_A1_Init.c
+* $Rev: 624 $
+* $Date:: 2013-04-24 13:37:48 +0900#$
+* @brief        RZ_A1 Initialize
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "VKRZA1H.h"
+#include "RZ_A1_Init.h"
+#include "rza_io_regrw.h"
+#include "gpio_iobitmask.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
+#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
+
+#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
+
+#ifndef __SD_BOOT__
+#define CS2_SDRAM
+#endif
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+static void PORT_Init(void)
+{
+    /* ==== BSC settings ==== */
+
+    /* ---- P7_2 : RAS# ---- */
+    /* Port initialize */
+    RZA_IO_RegWrite_16(&GPIO.PIBC7,  0, GPIO_PIBC7_PIBC72_SHIFT,   GPIO_PIBC7_PIBC72);
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC72_SHIFT,   GPIO_PBDC7_PBDC72);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    1, GPIO_PM7_PM72_SHIFT,       GPIO_PM7_PM72);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   0, GPIO_PMC7_PMC72_SHIFT,     GPIO_PMC7_PMC72);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  0, GPIO_PIPC7_PIPC72_SHIFT,   GPIO_PIPC7_PIPC72);
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    /* Bidirectional mode : Disable                   */
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC72_SHIFT,   GPIO_PBDC7_PBDC72);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC72_SHIFT,     GPIO_PFC7_PFC72);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE72_SHIFT,   GPIO_PFCE7_PFCE72);
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE72_SHIFT, GPIO_PFCAE7_PFCAE72);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC72_SHIFT,   GPIO_PIPC7_PIPC72);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC72_SHIFT,     GPIO_PMC7_PMC72);
+
+    /* ---- P7_3 : CAS# ---- */
+    /* Port initialize */
+    RZA_IO_RegWrite_16(&GPIO.PIBC7,  0, GPIO_PIBC7_PIBC73_SHIFT,   GPIO_PIBC7_PIBC73);
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC73_SHIFT,   GPIO_PBDC7_PBDC73);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    1, GPIO_PM7_PM73_SHIFT,       GPIO_PM7_PM73);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   0, GPIO_PMC7_PMC73_SHIFT,     GPIO_PMC7_PMC73);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  0, GPIO_PIPC7_PIPC73_SHIFT,   GPIO_PIPC7_PIPC73);
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    /* Bidirectional mode : Disable                   */
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC73_SHIFT,   GPIO_PBDC7_PBDC73);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC73_SHIFT,     GPIO_PFC7_PFC73);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE73_SHIFT,   GPIO_PFCE7_PFCE73);
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE73_SHIFT, GPIO_PFCAE7_PFCAE73);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC73_SHIFT,   GPIO_PIPC7_PIPC73);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC73_SHIFT,     GPIO_PMC7_PMC73);
+
+    /* ---- P7_4 : CKE ---- */
+    /* Port initialize */
+    RZA_IO_RegWrite_16(&GPIO.PIBC7,  0, GPIO_PIBC7_PIBC74_SHIFT,   GPIO_PIBC7_PIBC74);
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC74_SHIFT,   GPIO_PBDC7_PBDC74);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    1, GPIO_PM7_PM74_SHIFT,       GPIO_PM7_PM74);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   0, GPIO_PMC7_PMC74_SHIFT,     GPIO_PMC7_PMC74);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  0, GPIO_PIPC7_PIPC74_SHIFT,   GPIO_PIPC7_PIPC74);
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    /* Bidirectional mode : Disable                   */
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC74_SHIFT,   GPIO_PBDC7_PBDC74);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC74_SHIFT,     GPIO_PFC7_PFC74);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE74_SHIFT,   GPIO_PFCE7_PFCE74);
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE74_SHIFT, GPIO_PFCAE7_PFCAE74);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC74_SHIFT,   GPIO_PIPC7_PIPC74);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC74_SHIFT,     GPIO_PMC7_PMC74);
+
+    /* ---- P7_5 : RD/WR# ---- */
+    /* Port initialize */
+    RZA_IO_RegWrite_16(&GPIO.PIBC7,  0, GPIO_PIBC7_PIBC75_SHIFT,   GPIO_PIBC7_PIBC75);
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC75_SHIFT,   GPIO_PBDC7_PBDC75);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    1, GPIO_PM7_PM75_SHIFT,       GPIO_PM7_PM75);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   0, GPIO_PMC7_PMC75_SHIFT,     GPIO_PMC7_PMC75);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  0, GPIO_PIPC7_PIPC75_SHIFT,   GPIO_PIPC7_PIPC75);
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    /* Bidirectional mode : Disable                   */
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC75_SHIFT,   GPIO_PBDC7_PBDC75);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC75_SHIFT,     GPIO_PFC7_PFC75);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE75_SHIFT,   GPIO_PFCE7_PFCE75);
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE75_SHIFT, GPIO_PFCAE7_PFCAE75);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC75_SHIFT,   GPIO_PIPC7_PIPC75);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC75_SHIFT,     GPIO_PMC7_PMC75);
+
+    /* ---- P7_6 : DQMLL ---- */
+    /* Port initialize */
+    RZA_IO_RegWrite_16(&GPIO.PIBC7,  0, GPIO_PIBC7_PIBC76_SHIFT,   GPIO_PIBC7_PIBC76);
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC76_SHIFT,   GPIO_PBDC7_PBDC76);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    1, GPIO_PM7_PM76_SHIFT,       GPIO_PM7_PM76);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   0, GPIO_PMC7_PMC76_SHIFT,     GPIO_PMC7_PMC76);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  0, GPIO_PIPC7_PIPC76_SHIFT,   GPIO_PIPC7_PIPC76);
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    /* Bidirectional mode : Disable                   */
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC76_SHIFT,   GPIO_PBDC7_PBDC76);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC76_SHIFT,     GPIO_PFC7_PFC76);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE76_SHIFT,   GPIO_PFCE7_PFCE76);
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE76_SHIFT, GPIO_PFCAE7_PFCAE76);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC76_SHIFT,   GPIO_PIPC7_PIPC76);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC76_SHIFT,     GPIO_PMC7_PMC76);
+
+    /* ---- P7_7 : DQMLU ---- */
+    /* Port initialize */
+    RZA_IO_RegWrite_16(&GPIO.PIBC7,  0, GPIO_PIBC7_PIBC77_SHIFT,   GPIO_PIBC7_PIBC77);
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC77_SHIFT,   GPIO_PBDC7_PBDC77);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    1, GPIO_PM7_PM77_SHIFT,       GPIO_PM7_PM77);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   0, GPIO_PMC7_PMC77_SHIFT,     GPIO_PMC7_PMC77);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  0, GPIO_PIPC7_PIPC77_SHIFT,   GPIO_PIPC7_PIPC77);
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    /* Bidirectional mode : Disable                   */
+    RZA_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC77_SHIFT,   GPIO_PBDC7_PBDC77);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC77_SHIFT,     GPIO_PFC7_PFC77);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE77_SHIFT,   GPIO_PFCE7_PFCE77);
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE77_SHIFT, GPIO_PFCAE7_PFCAE77);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC77_SHIFT,   GPIO_PIPC7_PIPC77);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC77_SHIFT,     GPIO_PMC7_PMC77);
+
+    /* ---- P5_8 : CS2# ---- */
+    /* Port initialize */
+    RZA_IO_RegWrite_16(&GPIO.PIBC5,  0, GPIO_PIBC5_PIBC58_SHIFT,   GPIO_PIBC5_PIBC58);
+    RZA_IO_RegWrite_16(&GPIO.PBDC5,  0, GPIO_PBDC5_PBDC58_SHIFT,   GPIO_PBDC5_PBDC58);
+    RZA_IO_RegWrite_16(&GPIO.PM5,    1, GPIO_PM5_PM58_SHIFT,       GPIO_PM5_PM58);
+    RZA_IO_RegWrite_16(&GPIO.PMC5,   0, GPIO_PMC5_PMC58_SHIFT,     GPIO_PMC5_PMC58);
+    RZA_IO_RegWrite_16(&GPIO.PIPC5,  0, GPIO_PIPC5_PIPC58_SHIFT,   GPIO_PIPC5_PIPC58);
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 6th multiplex function */
+    /* I/O control mode : Peripheral function         */
+    /* Bidirectional mode : Disable                   */
+    RZA_IO_RegWrite_16(&GPIO.PBDC5,  0, GPIO_PBDC5_PBDC58_SHIFT,   GPIO_PBDC5_PBDC58);
+    RZA_IO_RegWrite_16(&GPIO.PFC5,   1, GPIO_PFC5_PFC58_SHIFT,     GPIO_PFC5_PFC58);
+    RZA_IO_RegWrite_16(&GPIO.PFCE5,  0, GPIO_PFCE5_PFCE58_SHIFT,   GPIO_PFCE5_PFCE58);
+    RZA_IO_RegWrite_16(&GPIO.PFCAE5, 1, GPIO_PFCAE5_PFCAE58_SHIFT, GPIO_PFCAE5_PFCAE58);
+    RZA_IO_RegWrite_16(&GPIO.PIPC5,  1, GPIO_PIPC5_PIPC58_SHIFT,   GPIO_PIPC5_PIPC58);
+    RZA_IO_RegWrite_16(&GPIO.PMC5,   1, GPIO_PMC5_PMC58_SHIFT,     GPIO_PMC5_PMC58);
+
+    /* ---- P7_1 : CS3# ---- */
+    /* Port initialize */
+//  RZA1_IO_RegWrite_16(&GPIO.PIBC7,  0, GPIO_PIBC7_PIBC71_SHIFT,   GPIO_PIBC7_PIBC71);
+//  RZA1_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC71_SHIFT,   GPIO_PBDC7_PBDC71);
+//  RZA1_IO_RegWrite_16(&GPIO.PM7,    1, GPIO_PM7_PM71_SHIFT,       GPIO_PM7_PM71);
+//  RZA1_IO_RegWrite_16(&GPIO.PMC7,   0, GPIO_PMC7_PMC71_SHIFT,     GPIO_PMC7_PMC71);
+//  RZA1_IO_RegWrite_16(&GPIO.PIPC7,  0, GPIO_PIPC7_PIPC71_SHIFT,   GPIO_PIPC7_PIPC71);
+//  /* Port mode : Multiplex mode                     */
+//  /* Port function setting : 1st multiplex function */
+//  /* I/O control mode : Peripheral function         */
+//  /* Bidirectional mode : Disable                   */
+//  RZA1_IO_RegWrite_16(&GPIO.PBDC7,  0, GPIO_PBDC7_PBDC71_SHIFT,   GPIO_PBDC7_PBDC71);
+//  RZA1_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC71_SHIFT,     GPIO_PFC7_PFC71);
+//  RZA1_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE71_SHIFT,   GPIO_PFCE7_PFCE71);
+//  RZA1_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE71_SHIFT, GPIO_PFCAE7_PFCAE71);
+//  RZA1_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC71_SHIFT,   GPIO_PIPC7_PIPC71);
+//  RZA1_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC71_SHIFT,     GPIO_PMC7_PMC71);
+}
+
+/******************************************************************************
+* Function Name: CS2_PORTInit
+* Description  : Sets the PORT multiplexed pin to use the CS2 and the CS3
+*              : spaces. In this sample code, the PORT setting is executed to
+*              : use the NOR flash memory in the CS0 and the CS1 spaces.
+* Arguments    : none
+* Return Value : none
+******************************************************************************/
+static void CS2_PORTInit(void)
+{
+    /* ---- P6_0 : D0 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE60_SHIFT, GPIO_PFCAE6_PFCAE60);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE60_SHIFT,   GPIO_PFCE6_PFCE60);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC60_SHIFT,     GPIO_PFC6_PFC60);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC60_SHIFT,     GPIO_PMC6_PMC60);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC60_SHIFT,   GPIO_PIPC6_PIPC60);
+
+    /* ---- P6_1 : D1 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE61_SHIFT, GPIO_PFCAE6_PFCAE61);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE61_SHIFT,   GPIO_PFCE6_PFCE61);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC61_SHIFT,     GPIO_PFC6_PFC61);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC61_SHIFT,     GPIO_PMC6_PMC61);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC61_SHIFT,   GPIO_PIPC6_PIPC61);
+
+    /* ---- P6_2 : D2 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE62_SHIFT, GPIO_PFCAE6_PFCAE62);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE62_SHIFT,   GPIO_PFCE6_PFCE62);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC62_SHIFT,     GPIO_PFC6_PFC62);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC62_SHIFT,     GPIO_PMC6_PMC62);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC62_SHIFT,   GPIO_PIPC6_PIPC62);
+
+    /* ---- P6_3 : D3 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE63_SHIFT, GPIO_PFCAE6_PFCAE63);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE63_SHIFT,   GPIO_PFCE6_PFCE63);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC63_SHIFT,     GPIO_PFC6_PFC63);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC63_SHIFT,     GPIO_PMC6_PMC63);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC63_SHIFT,   GPIO_PIPC6_PIPC63);
+
+    /* ---- P6_4 : D4 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE64_SHIFT, GPIO_PFCAE6_PFCAE64);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE64_SHIFT,   GPIO_PFCE6_PFCE64);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC64_SHIFT,     GPIO_PFC6_PFC64);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC64_SHIFT,     GPIO_PMC6_PMC64);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC64_SHIFT,   GPIO_PIPC6_PIPC64);
+
+    /* ---- P6_5 : D5 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE65_SHIFT, GPIO_PFCAE6_PFCAE65);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE65_SHIFT,   GPIO_PFCE6_PFCE65);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC65_SHIFT,     GPIO_PFC6_PFC65);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC65_SHIFT,     GPIO_PMC6_PMC65);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC65_SHIFT,   GPIO_PIPC6_PIPC65);
+
+    /* ---- P6_6 : D6 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE66_SHIFT, GPIO_PFCAE6_PFCAE66);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE66_SHIFT,   GPIO_PFCE6_PFCE66);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC66_SHIFT,     GPIO_PFC6_PFC66);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC66_SHIFT,     GPIO_PMC6_PMC66);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC66_SHIFT,   GPIO_PIPC6_PIPC66);
+
+    /* ---- P6_7 : D7 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE67_SHIFT, GPIO_PFCAE6_PFCAE67);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE67_SHIFT,   GPIO_PFCE6_PFCE67);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC67_SHIFT,     GPIO_PFC6_PFC67);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC67_SHIFT,     GPIO_PMC6_PMC67);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC67_SHIFT,   GPIO_PIPC6_PIPC67);
+
+    /* ---- P6_8 : D8 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE68_SHIFT, GPIO_PFCAE6_PFCAE68);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE68_SHIFT,   GPIO_PFCE6_PFCE68);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC68_SHIFT,     GPIO_PFC6_PFC68);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC68_SHIFT,     GPIO_PMC6_PMC68);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC68_SHIFT,   GPIO_PIPC6_PIPC68);
+
+    /* ---- P6_9 : D9 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE69_SHIFT, GPIO_PFCAE6_PFCAE69);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE69_SHIFT,   GPIO_PFCE6_PFCE69);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC69_SHIFT,     GPIO_PFC6_PFC69);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC69_SHIFT,     GPIO_PMC6_PMC69);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC69_SHIFT,   GPIO_PIPC6_PIPC69);
+
+    /* ---- P6_10 : D10 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE610_SHIFT, GPIO_PFCAE6_PFCAE610);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE610_SHIFT,   GPIO_PFCE6_PFCE610);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC610_SHIFT,     GPIO_PFC6_PFC610);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC610_SHIFT,     GPIO_PMC6_PMC610);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC610_SHIFT,   GPIO_PIPC6_PIPC610);
+
+    /* ---- P6_11 : D11 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE611_SHIFT, GPIO_PFCAE6_PFCAE611);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE611_SHIFT,   GPIO_PFCE6_PFCE611);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC611_SHIFT,     GPIO_PFC6_PFC611);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC611_SHIFT,     GPIO_PMC6_PMC611);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC611_SHIFT,   GPIO_PIPC6_PIPC611);
+
+    /* ---- P6_12 : D12 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE612_SHIFT, GPIO_PFCAE6_PFCAE612);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE612_SHIFT,   GPIO_PFCE6_PFCE612);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC612_SHIFT,     GPIO_PFC6_PFC612);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC612_SHIFT,     GPIO_PMC6_PMC612);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC612_SHIFT,   GPIO_PIPC6_PIPC612);
+
+    /* ---- P6_13 : D13 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE613_SHIFT, GPIO_PFCAE6_PFCAE613);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE613_SHIFT,   GPIO_PFCE6_PFCE613);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC613_SHIFT,     GPIO_PFC6_PFC613);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC613_SHIFT,     GPIO_PMC6_PMC613);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC613_SHIFT,   GPIO_PIPC6_PIPC613);
+
+    /* ---- P6_14 : D14 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE614_SHIFT, GPIO_PFCAE6_PFCAE614);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE614_SHIFT,   GPIO_PFCE6_PFCE614);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC614_SHIFT,     GPIO_PFC6_PFC614);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC614_SHIFT,     GPIO_PMC6_PMC614);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC614_SHIFT,   GPIO_PIPC6_PIPC614);
+
+    /* ---- P6_15 : D15 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE615_SHIFT, GPIO_PFCAE6_PFCAE615);
+    RZA_IO_RegWrite_16(&GPIO.PFCE6,  0, GPIO_PFCE6_PFCE615_SHIFT,   GPIO_PFCE6_PFCE615);
+    RZA_IO_RegWrite_16(&GPIO.PFC6,   0, GPIO_PFC6_PFC615_SHIFT,     GPIO_PFC6_PFC615);
+    RZA_IO_RegWrite_16(&GPIO.PMC6,   1, GPIO_PMC6_PMC615_SHIFT,     GPIO_PMC6_PMC615);
+    RZA_IO_RegWrite_16(&GPIO.PIPC6,  1, GPIO_PIPC6_PIPC615_SHIFT,   GPIO_PIPC6_PIPC615);
+
+    /* ---- P7_9 : A1 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE79_SHIFT, GPIO_PFCAE7_PFCAE79);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE79_SHIFT,   GPIO_PFCE7_PFCE79);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC79_SHIFT,     GPIO_PFC7_PFC79);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    0, GPIO_PM7_PM79_SHIFT,       GPIO_PM7_PM79);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC79_SHIFT,     GPIO_PMC7_PMC79);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC79_SHIFT,   GPIO_PIPC7_PIPC79);
+
+    /* ---- P7_10 : A2 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE710_SHIFT, GPIO_PFCAE7_PFCAE710);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE710_SHIFT,   GPIO_PFCE7_PFCE710);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC710_SHIFT,     GPIO_PFC7_PFC710);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    0, GPIO_PM7_PM710_SHIFT,       GPIO_PM7_PM710);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC710_SHIFT,     GPIO_PMC7_PMC710);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC710_SHIFT,   GPIO_PIPC7_PIPC710);
+
+    /* ---- P7_11 : A3 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE711_SHIFT, GPIO_PFCAE7_PFCAE711);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE711_SHIFT,   GPIO_PFCE7_PFCE711);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC711_SHIFT,     GPIO_PFC7_PFC711);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    0, GPIO_PM7_PM711_SHIFT,       GPIO_PM7_PM711);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC711_SHIFT,     GPIO_PMC7_PMC711);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC711_SHIFT,   GPIO_PIPC7_PIPC711);
+
+    /* ---- P7_12 : A4 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE712_SHIFT, GPIO_PFCAE7_PFCAE712);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE712_SHIFT,   GPIO_PFCE7_PFCE712);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC712_SHIFT,     GPIO_PFC7_PFC712);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    0, GPIO_PM7_PM712_SHIFT,       GPIO_PM7_PM712);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC712_SHIFT,     GPIO_PMC7_PMC712);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC712_SHIFT,   GPIO_PIPC7_PIPC712);
+
+    /* ---- P7_13 : A5 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE713_SHIFT, GPIO_PFCAE7_PFCAE713);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE713_SHIFT,   GPIO_PFCE7_PFCE713);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC713_SHIFT,     GPIO_PFC7_PFC713);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    0, GPIO_PM7_PM713_SHIFT,       GPIO_PM7_PM713);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC713_SHIFT,     GPIO_PMC7_PMC713);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC713_SHIFT,   GPIO_PIPC7_PIPC713);
+
+    /* ---- P7_14 : A6 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE714_SHIFT, GPIO_PFCAE7_PFCAE714);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE714_SHIFT,   GPIO_PFCE7_PFCE714);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC714_SHIFT,     GPIO_PFC7_PFC714);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    0, GPIO_PM7_PM714_SHIFT,       GPIO_PM7_PM714);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC714_SHIFT,     GPIO_PMC7_PMC714);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC714_SHIFT,   GPIO_PIPC7_PIPC714);
+
+    /* ---- P7_15 : A7 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE715_SHIFT, GPIO_PFCAE7_PFCAE715);
+    RZA_IO_RegWrite_16(&GPIO.PFCE7,  0, GPIO_PFCE7_PFCE715_SHIFT,   GPIO_PFCE7_PFCE715);
+    RZA_IO_RegWrite_16(&GPIO.PFC7,   0, GPIO_PFC7_PFC715_SHIFT,     GPIO_PFC7_PFC715);
+    RZA_IO_RegWrite_16(&GPIO.PM7,    0, GPIO_PM7_PM715_SHIFT,       GPIO_PM7_PM715);
+    RZA_IO_RegWrite_16(&GPIO.PMC7,   1, GPIO_PMC7_PMC715_SHIFT,     GPIO_PMC7_PMC715);
+    RZA_IO_RegWrite_16(&GPIO.PIPC7,  1, GPIO_PIPC7_PIPC715_SHIFT,   GPIO_PIPC7_PIPC715);
+
+    /* ---- P8_0 : A8 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE80_SHIFT, GPIO_PFCAE8_PFCAE80);
+    RZA_IO_RegWrite_16(&GPIO.PFCE8,  0, GPIO_PFCE8_PFCE80_SHIFT,   GPIO_PFCE8_PFCE80);
+    RZA_IO_RegWrite_16(&GPIO.PFC8,   0, GPIO_PFC8_PFC80_SHIFT,     GPIO_PFC8_PFC80);
+    RZA_IO_RegWrite_16(&GPIO.PMC8,   1, GPIO_PMC8_PMC80_SHIFT,     GPIO_PMC8_PMC80);
+    RZA_IO_RegWrite_16(&GPIO.PIPC8,  1, GPIO_PIPC8_PIPC80_SHIFT,   GPIO_PIPC8_PIPC80);
+
+    /* ---- P8_1 : A9 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE81_SHIFT, GPIO_PFCAE8_PFCAE81);
+    RZA_IO_RegWrite_16(&GPIO.PFCE8,  0, GPIO_PFCE8_PFCE81_SHIFT,   GPIO_PFCE8_PFCE81);
+    RZA_IO_RegWrite_16(&GPIO.PFC8,   0, GPIO_PFC8_PFC81_SHIFT,     GPIO_PFC8_PFC81);
+    RZA_IO_RegWrite_16(&GPIO.PM8,    0, GPIO_PM8_PM81_SHIFT,       GPIO_PM8_PM81);
+    RZA_IO_RegWrite_16(&GPIO.PMC8,   1, GPIO_PMC8_PMC81_SHIFT,     GPIO_PMC8_PMC81);
+    RZA_IO_RegWrite_16(&GPIO.PIPC8,  1, GPIO_PIPC8_PIPC81_SHIFT,   GPIO_PIPC8_PIPC81);
+
+    /* ---- P8_2 : A10 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE82_SHIFT, GPIO_PFCAE8_PFCAE82);
+    RZA_IO_RegWrite_16(&GPIO.PFCE8,  0, GPIO_PFCE8_PFCE82_SHIFT,   GPIO_PFCE8_PFCE82);
+    RZA_IO_RegWrite_16(&GPIO.PFC8,   0, GPIO_PFC8_PFC82_SHIFT,     GPIO_PFC8_PFC82);
+    RZA_IO_RegWrite_16(&GPIO.PM8,    0, GPIO_PM8_PM82_SHIFT,       GPIO_PM8_PM82);
+    RZA_IO_RegWrite_16(&GPIO.PMC8,   1, GPIO_PMC8_PMC82_SHIFT,     GPIO_PMC8_PMC82);
+    RZA_IO_RegWrite_16(&GPIO.PIPC8,  1, GPIO_PIPC8_PIPC82_SHIFT,   GPIO_PIPC8_PIPC82);
+
+    /* ---- P8_3 : A11 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE83_SHIFT, GPIO_PFCAE8_PFCAE83);
+    RZA_IO_RegWrite_16(&GPIO.PFCE8,  0, GPIO_PFCE8_PFCE83_SHIFT,   GPIO_PFCE8_PFCE83);
+    RZA_IO_RegWrite_16(&GPIO.PFC8,   0, GPIO_PFC8_PFC83_SHIFT,     GPIO_PFC8_PFC83);
+    RZA_IO_RegWrite_16(&GPIO.PM8,    0, GPIO_PM8_PM83_SHIFT,       GPIO_PM8_PM83);
+    RZA_IO_RegWrite_16(&GPIO.PMC8,   1, GPIO_PMC8_PMC83_SHIFT,     GPIO_PMC8_PMC83);
+    RZA_IO_RegWrite_16(&GPIO.PIPC8,  1, GPIO_PIPC8_PIPC83_SHIFT,   GPIO_PIPC8_PIPC83);
+
+    /* ---- P8_4 : A12 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE84_SHIFT, GPIO_PFCAE8_PFCAE84);
+    RZA_IO_RegWrite_16(&GPIO.PFCE8,  0, GPIO_PFCE8_PFCE84_SHIFT,   GPIO_PFCE8_PFCE84);
+    RZA_IO_RegWrite_16(&GPIO.PFC8,   0, GPIO_PFC8_PFC84_SHIFT,     GPIO_PFC8_PFC84);
+    RZA_IO_RegWrite_16(&GPIO.PM8,    0, GPIO_PM8_PM84_SHIFT,       GPIO_PM8_PM84);
+    RZA_IO_RegWrite_16(&GPIO.PMC8,   1, GPIO_PMC8_PMC84_SHIFT,     GPIO_PMC8_PMC84);
+    RZA_IO_RegWrite_16(&GPIO.PIPC8,  1, GPIO_PIPC8_PIPC84_SHIFT,   GPIO_PIPC8_PIPC84);
+
+    /* ---- P8_5 : A13 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE85_SHIFT, GPIO_PFCAE8_PFCAE85);
+    RZA_IO_RegWrite_16(&GPIO.PFCE8,  0, GPIO_PFCE8_PFCE85_SHIFT,   GPIO_PFCE8_PFCE85);
+    RZA_IO_RegWrite_16(&GPIO.PFC8,   0, GPIO_PFC8_PFC85_SHIFT,     GPIO_PFC8_PFC85);
+    RZA_IO_RegWrite_16(&GPIO.PM8,    0, GPIO_PM8_PM85_SHIFT,       GPIO_PM8_PM85);
+    RZA_IO_RegWrite_16(&GPIO.PMC8,   1, GPIO_PMC8_PMC85_SHIFT,     GPIO_PMC8_PMC85);
+    RZA_IO_RegWrite_16(&GPIO.PIPC8,  1, GPIO_PIPC8_PIPC85_SHIFT,   GPIO_PIPC8_PIPC85);
+
+    /* ---- P8_6 : A14 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+    RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE86_SHIFT, GPIO_PFCAE8_PFCAE86);
+    RZA_IO_RegWrite_16(&GPIO.PFCE8,  0, GPIO_PFCE8_PFCE86_SHIFT,   GPIO_PFCE8_PFCE86);
+    RZA_IO_RegWrite_16(&GPIO.PFC8,   0, GPIO_PFC8_PFC86_SHIFT,     GPIO_PFC8_PFC86);
+    RZA_IO_RegWrite_16(&GPIO.PM8,    0, GPIO_PM8_PM86_SHIFT,       GPIO_PM8_PM86);
+    RZA_IO_RegWrite_16(&GPIO.PMC8,   1, GPIO_PMC8_PMC86_SHIFT,     GPIO_PMC8_PMC86);
+    RZA_IO_RegWrite_16(&GPIO.PIPC8,  1, GPIO_PIPC8_PIPC86_SHIFT,   GPIO_PIPC8_PIPC86);
+
+    /* ---- P8_7 : A15 ---- */
+    /* Port mode : Multiplex mode                     */
+    /* Port function setting : 1st multiplex function */
+    /* I/O control mode : Peripheral function         */
+	RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE87_SHIFT, GPIO_PFCAE8_PFCAE87);
+    RZA_IO_RegWrite_16(&GPIO.PFCE8,  0, GPIO_PFCE8_PFCE87_SHIFT,   GPIO_PFCE8_PFCE87);
+    RZA_IO_RegWrite_16(&GPIO.PFC8,   0, GPIO_PFC8_PFC87_SHIFT,     GPIO_PFC8_PFC87);
+    RZA_IO_RegWrite_16(&GPIO.PM8,    0, GPIO_PM8_PM87_SHIFT,       GPIO_PM8_PM87);
+    RZA_IO_RegWrite_16(&GPIO.PMC8,   1, GPIO_PMC8_PMC87_SHIFT,     GPIO_PMC8_PMC87);
+    RZA_IO_RegWrite_16(&GPIO.PIPC8,  1, GPIO_PIPC8_PIPC87_SHIFT,   GPIO_PIPC8_PIPC87);
+}
+
+
+/******************************************************************************
+* Function Name: Userdef_BSC_CS2Init
+* Description  : This is the user-defined function called by the R_BSC_Init
+*              : function. The setting for initialization of the BSC in the CS2
+*              : space is required. In this sample code, the setting to use
+*              : the SDRAM in the CS2 space is executed. Sets the BSC to 
+*              : connect the ISSI IS42S16320B-75 to the CS2 space with 16-bit
+*              : bus width.
+* Arguments    : none
+* Return Value : none
+******************************************************************************/
+static void CS2_BSC_Init(void)
+{
+       /* ==== CS2BCR settings ==== */
+    /* Idle Cycles between Write-read Cycles  */
+    /* and Write-write Cycles : 0 idle cycles */
+    /* Memory type :SDRAM                     */
+    /* Data Bus Size : 16-bit                 */
+    BSC.CS2BCR = 0x00004C00ul;
+
+    /* ==== CS3BCR settings ==== */
+    /* SDRAM WORKAROUND - see Note */
+    /* Idle Cycles between Write-read Cycles  */
+    /* and Write-write Cycles : 0 idle cycles */
+    /* Memory type :SDRAM                     */
+    /* Data Bus Size : 16-bit                 */
+    BSC.CS3BCR = 0x00004C00ul;
+
+    /* ==== CS2/3WCR settings ==== */
+    /* Precharge completion wait cycles: 1 cycle     */
+    /* Wait cycles between ACTV command              */
+    /* and READ(A)/WRITE(A) command : 1 cycles       */
+    /* CAS latency for Area 3 : 2 cycles             */
+    /* Auto-precharge startup wait cycles : 2 cycles */
+    /* Idle cycles from REF command/self-refresh     */
+    /* Release to ACTV/REF/MRS command : 5 cycles    */
+    BSC.CS3WCR = 0x00002492ul;
+
+    /* SDRAM WORKAROUND - see Note */
+    BSC.CS2WCR = 0x00000480ul;
+
+    /* ==== SDCR settings ==== */
+    /* SDRAM WORKAROUND - see Note*/
+    /* Row address for Area 2 : 13-bit    */
+    /* Column Address for Area 2 : 9-bit  */
+    /* Refresh Control :Refresh           */
+    /* RMODE :Auto-refresh is performed   */
+    /* BACTV :Auto-precharge mode         */
+    /* Row address for Area 3 : 13-bit    */
+    /* Column Address for Area 3 : 9-bit  */
+    BSC.SDCR = 0x00110811ul;
+
+    /* ==== RTCOR settings ==== */
+    /* 7.8usec / 60nsec              */
+    /*   = 32(0x40)cycles per refresh */
+    BSC.RTCOR = 0xA55A0020ul;
+
+    /* ==== RTCSR settings ==== */
+    /* initialisation sequence start */
+    /* Clock select B-phy/16          */
+    /* Refresh count :Once           */
+    BSC.RTCSR = 0xA55A0010ul;
+
+
+    /* ==== SDRAM Mode Register ==== */
+    /* Burst read (burst length 1)./Burst write */
+    CS2_SDRAM_MODE_16BIT_CAS2_BR_BW = 0;
+
+    /* SDRAM WORKAROUND - see Note */
+    CS3_SDRAM_MODE_16BIT_CAS2_BR_BW = 0;
+
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_SetSramWriteEnable
+* @brief         Initialize Board settings
+*
+*                Description:<br>
+*                Set SRAM write enable
+* @param         none
+* @retval        none
+******************************************************************************/
+void RZ_A1_SetSramWriteEnable(void)
+{
+    /* Enable SRAM write access */
+    CPG.SYSCR3 = 0x0F;
+
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_InitClock
+* @brief         Initialize Board settings
+*
+*                Description:<br>
+*                Initialize Clock
+* @param         none
+* @retval        none
+******************************************************************************/
+void RZ_A1_InitClock(void)
+{
+    /* Cancel L2C standby status before clock change */
+    L2CREG15_POWER_CTRL = 0x00000001;
+
+    /* Clock settings */
+    /* ClockMode0 */
+    CPG.FRQCR  = 0x1035;    /* CPU Clock =399.99MHz */
+    CPG.FRQCR2 = 0x0001;    /* G Clock   =266.66MHz */
+
+    return;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_IsClockMode0
+* @brief         Query Clock Mode
+*
+*                Description:<br>
+*                Answer ClockMode0 or not
+* @param         none
+* @retval        true  : clock mode 0
+* @retval        false : clock mode 1
+******************************************************************************/
+int RZ_A1_IsClockMode0(void)
+{
+    /* ClockMode0 */
+    return true;
+}
+
+/**************************************************************************//**
+* Function Name: RZ_A1_InitBus
+* @brief         Initialize Bus
+*
+*                Description:<br>
+*                Initialize Pin Setting
+* @param         none
+* @retval        none
+******************************************************************************/
+void RZ_A1_InitBus(void)
+{
+    /*************************************************************************/
+    /* If need Pin Setting before run program, the setting will be wrote here*/
+    /*************************************************************************/
+#if defined(CS2_SDRAM)
+   PORT_Init();
+   CS2_PORTInit();
+   CS2_BSC_Init();
+#else
+    return;
+#endif
+}
+
+/******************************************************************************
+End of file
+******************************************************************************/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/RZ_A1_Init.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,72 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file          RZ_A1_Init.h
+* $Rev: 531 $
+* $Date:: 2013-04-16 13:07:35 +0900#$
+* @brief         RZ_A1 Initialize
+******************************************************************************/
+
+#ifndef RZ_A1_INIT_H
+#define RZ_A1_INIT_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stdio.h>
+#include <stdbool.h>
+#include "iodefine.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+void    RZ_A1_SetSramWriteEnable(void);
+void    RZ_A1_InitClock(void);
+int     RZ_A1_IsClockMode0(void);
+void    RZ_A1_InitBus(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RZ_A1_INIT_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/VKRZA1H_DOUBLE.sct	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,43 @@
+
+
+LOAD_TTB    0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
+{
+    TTB     +0 EMPTY 0x4000            
+    { }                           ; Level-1 Translation Table for MMU
+}
+
+SDRAM       0x08000000 0x02000000 ; 32MB External SDRAM region
+{
+}
+
+SFLASH_DUAL 0x18020000 (32*1024*1024-2*64*1024)
+{
+    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+    ; S-Flash ROM : Executable cached region
+    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+    VECTORS 0x18020000 FIXED
+    {
+        * (RESET, +FIRST)         ; Vector table and other (assembler) startup code
+        * (InRoot$$Sections)      ; All (library) code that must be in a root region
+        * (+RO-CODE)              ; Application RO code (.text)
+    }
+
+    RO_DATA    +0
+    { * (+RO-DATA) }              ; Application RO data (.constdata)
+
+    RW_DATA    0x20020000
+    { * (+RW) }                   ; Application RW data (.data)
+
+    ZI_DATA    +0 ALIGN 0x400
+    { * (+ZI) }                   ; Application ZI data (.bss)
+
+    RW_DATA_NC 0x60900000 0x00100000
+    { * (NC_DATA) }              ; Application RW data Non cached area
+
+    ZI_DATA_NC +0
+    { * (NC_BSS) }               ; Application ZI data Non cached area
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/VKRZA1H_RAM.sct	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,43 @@
+
+
+LOAD_TTB    0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
+{
+    TTB     +0 EMPTY 0x4000            
+    { }                           ; Level-1 Translation Table for MMU
+}
+
+SDRAM       0x08000000 0x02000000 ; 32MB External SDRAM region
+{
+}
+
+INTERNAL_SRAM 0x200A0000 (10*1024*1024-((16+28+596)*1024))
+{
+    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+    ; S-Flash ROM : Executable cached region
+    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+    VECTORS 0x200A0000 FIXED
+    {
+        * (RESET, +FIRST)         ; Vector table and other (assembler) startup code
+        * (InRoot$$Sections)      ; All (library) code that must be in a root region
+        * (+RO-CODE)              ; Application RO code (.text)
+    }
+
+    RO_DATA    +0
+    { * (+RO-DATA) }              ; Application RO data (.constdata)
+
+    RW_DATA    +0 NOCOMPRESS
+    { * (+RW) }                   ; Application RW data (.data)
+
+    ZI_DATA    +0 ALIGN 0x400
+    { * (+ZI) }                   ; Application ZI data (.bss)
+
+    RW_DATA_NC 0x60900000 0x00100000
+    { * (NC_DATA) }              ; Application RW data Non cached area
+
+    ZI_DATA_NC +0
+    { * (NC_BSS) }               ; Application ZI data Non cached area
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/VKRZA1H_SDRAM.sct	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,42 @@
+
+
+LOAD_TTB    0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
+{
+    TTB     +0 EMPTY 0x4000            
+    { }                           ; Level-1 Translation Table for MMU
+}
+
+EXTERNAL_SDRAM       0x08000000 0x02000000 ; 32MB External SDRAM region
+{
+    VECTORS 0x08000000 FIXED
+    {
+        * (RESET, +FIRST)         ; Vector table and other (assembler) startup code
+        * (InRoot$$Sections)      ; All (library) code that must be in a root region
+        * (+RO-CODE)              ; Application RO code (.text)
+    }
+
+    RO_DATA    +0
+    { * (+RO-DATA) }              ; Application RO data (.constdata)
+
+    RW_DATA    +0
+    { * (+RW) }                   ; Application RW data (.data)
+
+    ZI_DATA    +0 ALIGN 0x400
+    { * (+ZI) }                   ; Application ZI data (.bss)
+}
+
+INTERNAL_SRAM 0x200A0000 (10*1024*1024-((16+28+596)*1024))
+{
+    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+    ; S-Flash ROM : Executable cached region
+    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+    RW_DATA_NC 0x60900000 0x00100000
+    { * (NC_DATA) }              ; Application RW data Non cached area
+
+    ZI_DATA_NC +0
+    { * (NC_BSS) }               ; Application ZI data Non cached area
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/VKRZA1H_SINGLE.sct	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,43 @@
+
+
+LOAD_TTB    0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
+{
+    TTB     +0 EMPTY 0x4000            
+    { }                           ; Level-1 Translation Table for MMU
+}
+
+SDRAM       0x08000000 0x02000000 ; 32MB External SDRAM region
+{
+}
+
+SFLASH_SINGLE 0x18000000 (16*1024*1024)
+{
+    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+    ; S-Flash ROM : Executable cached region
+    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+    VECTORS 0x18000000 FIXED
+    {
+        * (RESET, +FIRST)         ; Vector table and other (assembler) startup code
+        * (InRoot$$Sections)      ; All (library) code that must be in a root region
+        * (+RO-CODE)              ; Application RO code (.text)
+    }
+
+    RO_DATA    +0
+    { * (+RO-DATA) }              ; Application RO data (.constdata)
+
+    RW_DATA    0x20020000
+    { * (+RW) }                   ; Application RW data (.data)
+
+    ZI_DATA    +0 ALIGN 0x400
+    { * (+ZI) }                   ; Application ZI data (.bss)
+
+    RW_DATA_NC 0x60900000 0x00100000
+    { * (NC_DATA) }              ; Application RW data Non cached area
+
+    ZI_DATA_NC +0
+    { * (NC_BSS) }               ; Application ZI data Non cached area
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,455 @@
+;/*****************************************************************************
+; * @file:    startup_VKRZA1H.s
+; * @purpose: CMSIS Cortex-A9 Core Device Startup File 
+; *           for the Renesas RZA1H Device Series
+; * @version: V1.02, modified for mbed
+; * @date:    27. July 2009, modified 3rd Aug 2009
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
+; * processor based microcontrollers.  This file can be freely distributed 
+; * within development tools that are supporting such ARM based processors. 
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+GICI_BASE       EQU     0xe8202000
+ICCIAR_OFFSET   EQU     0x0000000C
+ICCEOIR_OFFSET  EQU     0x00000010
+ICCHPIR_OFFSET  EQU     0x00000018
+
+GICD_BASE       EQU     0xe8201000
+ICDISER0_OFFSET EQU     0x00000100
+ICDICER0_OFFSET EQU     0x00000180
+ICDISPR0_OFFSET EQU     0x00000200
+ICDABR0_OFFSET  EQU     0x00000300
+ICDIPR0_OFFSET  EQU     0x00000400
+
+Mode_USR        EQU     0x10
+Mode_FIQ        EQU     0x11
+Mode_IRQ        EQU     0x12
+Mode_SVC        EQU     0x13
+Mode_ABT        EQU     0x17
+Mode_UND        EQU     0x1B
+Mode_SYS        EQU     0x1F
+
+I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
+F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled
+T_Bit           EQU     0x20            ; when T bit is set, core is in Thumb state
+
+GIC_ERRATA_CHECK_1     EQU     0x000003FE
+GIC_ERRATA_CHECK_2     EQU     0x000003FF
+
+
+Sect_Normal     EQU     0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+Sect_Normal_Cod EQU     0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+Sect_Normal_RO  EQU     0x0000dc16 ;as Sect_Normal_Cod, but not executable
+Sect_Normal_RW  EQU     0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable
+Sect_SO         EQU     0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+Sect_Device_RO  EQU     0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0
+Sect_Device_RW  EQU     0x00000c12 ;as Sect_Device_RO, but writeable
+Sect_Fault      EQU     0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored)
+
+RAM_BASE        EQU     0x80000000
+VRAM_BASE       EQU     0x18000000
+SRAM_BASE       EQU     0x2e000000
+ETHERNET        EQU     0x1a000000
+CS3_PERIPHERAL_BASE EQU 0x1c000000
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8>
+; </h>
+
+UND_Stack_Size  EQU     0x00000100
+SVC_Stack_Size  EQU     0x00008000
+ABT_Stack_Size  EQU     0x00000100
+FIQ_Stack_Size  EQU     0x00000100
+IRQ_Stack_Size  EQU     0x00008000
+USR_Stack_Size  EQU     0x00004000
+
+ISR_Stack_Size  EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                         FIQ_Stack_Size + IRQ_Stack_Size)
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   USR_Stack_Size
+__initial_sp    SPACE   ISR_Stack_Size
+
+Stack_Top
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00080000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                ARM
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, CODE, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       LDR     PC, Reset_Addr            ; Address of Reset Handler
+                LDR     PC, Undef_Addr            ; Address of Undef Handler
+                LDR     PC, SVC_Addr              ; Address of SVC Handler
+                LDR     PC, PAbt_Addr             ; Address of Prefetch Abort Handler
+                LDR     PC, DAbt_Addr             ; Address of Data Abort Handler
+                NOP                               ; Reserved Vector
+                LDR     PC, IRQ_Addr              ; Address of IRQ Handler
+                LDR     PC, FIQ_Addr              ; Address of FIQ Handler
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+Reset_Addr      DCD     Reset_Handler
+Undef_Addr      DCD     Undef_Handler
+SVC_Addr        DCD     SVC_Handler
+PAbt_Addr       DCD     PAbt_Handler
+DAbt_Addr       DCD     DAbt_Handler
+IRQ_Addr        DCD     IRQ_Handler
+FIQ_Addr        DCD     FIQ_Handler
+
+                AREA    |.text|, CODE, READONLY
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  InitMemorySubsystem
+                IMPORT  __main
+                IMPORT  RZ_A1_SetSramWriteEnable
+
+                ; Put any cores other than 0 to sleep
+                MRC     p15, 0, R0, c0, c0, 5     ; Read MPIDR
+                ANDS    R0, R0, #3
+goToSleep
+                WFINE
+                BNE     goToSleep
+
+; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
+; Enables Full Access i.e. in both privileged and non privileged modes
+                MRC     p15, 0, r0, c1, c0, 2       ; Read Coprocessor Access Control Register (CPACR)
+                ORR     r0, r0, #(0xF << 20)        ; Enable access to CP 10 & 11
+                MCR     p15, 0, r0, c1, c0, 2       ; Write Coprocessor Access Control Register (CPACR)
+                ISB
+
+; Switch on the VFP and NEON hardware
+                MOV     r0, #0x40000000
+                VMSR    FPEXC, r0                   ; Write FPEXC register, EN bit set
+
+                MRC     p15, 0, R0, c1, c0, 0       ; Read CP15 System Control register
+                BIC     R0, R0, #(0x1 << 12)        ; Clear I bit 12 to disable I Cache
+                BIC     R0, R0, #(0x1 <<  2)        ; Clear C bit  2 to disable D Cache
+                BIC     R0, R0, #0x1                ; Clear M bit  0 to disable MMU
+                BIC     R0, R0, #(0x1 << 11)        ; Clear Z bit 11 to disable branch prediction
+                BIC     R0, R0, #(0x1 << 13)        ; Clear V bit 13 to disable hivecs
+                MCR     p15, 0, R0, c1, c0, 0       ; Write value back to CP15 System Control register
+                ISB
+
+; Set Vector Base Address Register (VBAR) to point to this application's vector table
+                LDR     R0, =__Vectors
+                MCR     p15, 0, R0, c12, c0, 0
+
+;  Setup Stack for each exceptional mode
+                LDR     R0, =Stack_Top
+
+;  Enter Undefined Instruction Mode and set its Stack Pointer
+                MSR     CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit
+                MOV     SP, R0
+                SUB     R0, R0, #UND_Stack_Size
+
+;  Enter Abort Mode and set its Stack Pointer
+                MSR     CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit
+                MOV     SP, R0
+                SUB     R0, R0, #ABT_Stack_Size
+
+;  Enter FIQ Mode and set its Stack Pointer
+                MSR     CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit
+                MOV     SP, R0
+                SUB     R0, R0, #FIQ_Stack_Size
+
+;  Enter IRQ Mode and set its Stack Pointer
+                MSR     CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit
+                MOV     SP, R0
+                SUB     R0, R0, #IRQ_Stack_Size
+
+;  Enter Supervisor Mode and set its Stack Pointer
+                MSR     CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit
+                MOV     SP, R0
+
+;  Enter System Mode to complete initialization and enter kernel
+                MSR     CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit
+                MOV     SP, R0
+
+                ISB
+
+                LDR     R0, =RZ_A1_SetSramWriteEnable
+                BLX     R0
+
+                IMPORT  create_translation_table
+                BL      create_translation_table
+
+;  USR/SYS stack pointer will be set during kernel init
+
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =InitMemorySubsystem
+                BLX     R0
+                LDR     R0, =__main
+                BLX     R0
+
+                ENDP
+
+Undef_Handler\
+                PROC
+                EXPORT  Undef_Handler             [WEAK]
+                IMPORT  CUndefHandler
+                SRSFD   SP!, #Mode_UND
+                PUSH    {R0-R4, R12}              ; Save APCS corruptible registers to UND mode stack
+
+                MRS     R0, SPSR
+                TST     R0, #T_Bit                ; Check mode
+                MOVEQ   R1, #4                    ; R1 = 4 ARM mode
+                MOVNE   R1, #2                    ; R1 = 2 Thumb mode
+                SUB     R0, LR, R1
+                LDREQ   R0, [R0]                  ; ARM mode - R0 points to offending instruction
+                BEQ     undef_cont
+
+                ;Thumb instruction
+                ;Determine if it is a 32-bit Thumb instruction
+                LDRH    R0, [R0]
+                MOV     R2, #0x1c
+                CMP     R2, R0, LSR #11
+                BHS     undef_cont                ;16-bit Thumb instruction
+
+                ;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction.
+                LDRH    R2, [LR]
+                ORR     R0, R2, R0, LSL #16
+undef_cont
+                MOV     R2, LR                    ; Set LR to third argument
+                
+;               AND     R12, SP, #4               ; Ensure stack is 8-byte aligned
+                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
+                AND     R12, R3, #4
+                SUB     SP, SP, R12               ; Adjust stack
+                PUSH    {R12, LR}                 ; Store stack adjustment and dummy LR
+
+                ;R0 Offending instruction
+                ;R1 =2 (Thumb) or =4 (ARM)
+                BL      CUndefHandler
+
+                POP     {R12, LR}                 ; Get stack adjustment & discard dummy LR
+                ADD     SP, SP, R12               ; Unadjust stack
+
+                LDR     LR, [SP, #24]             ; Restore stacked LR and possibly adjust for retry
+                SUB     LR, LR, R0
+                LDR     R0, [SP, #28]             ; Restore stacked SPSR
+                MSR     SPSR_CXSF, R0
+                POP     {R0-R4, R12}              ; Restore stacked APCS registers
+                ADD     SP, SP, #8                ; Adjust SP for already-restored banked registers
+                MOVS    PC, LR
+                ENDP
+
+PAbt_Handler\
+                PROC
+                EXPORT  PAbt_Handler              [WEAK]
+                IMPORT  CPAbtHandler
+                SUB     LR, LR, #4                ; Pre-adjust LR
+                SRSFD   SP!, #Mode_ABT            ; Save LR and SPRS to ABT mode stack
+                PUSH    {R0-R4, R12}              ; Save APCS corruptible registers to ABT mode stack
+                MRC     p15, 0, R0, c5, c0, 1     ; IFSR
+                MRC     p15, 0, R1, c6, c0, 2     ; IFAR
+
+                MOV     R2, LR                    ; Set LR to third argument
+
+;               AND     R12, SP, #4               ; Ensure stack is 8-byte aligned
+                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
+                AND     R12, R3, #4
+                SUB     SP, SP, R12               ; Adjust stack
+                PUSH    {R12, LR}                 ; Store stack adjustment and dummy LR
+
+                BL      CPAbtHandler
+
+                POP     {R12, LR}                 ; Get stack adjustment & discard dummy LR
+                ADD     SP, SP, R12               ; Unadjust stack
+
+                POP     {R0-R4, R12}              ; Restore stack APCS registers
+                RFEFD   SP!                       ; Return from exception
+                ENDP
+
+
+DAbt_Handler\
+                PROC
+                EXPORT  DAbt_Handler              [WEAK]
+                IMPORT  CDAbtHandler
+                SUB     LR, LR, #8                ; Pre-adjust LR
+                SRSFD   SP!, #Mode_ABT            ; Save LR and SPRS to ABT mode stack
+                PUSH    {R0-R4, R12}              ; Save APCS corruptible registers to ABT mode stack
+                CLREX                             ; State of exclusive monitors unknown after taken data abort
+                MRC     p15, 0, R0, c5, c0, 0     ; DFSR
+                MRC     p15, 0, R1, c6, c0, 0     ; DFAR
+
+                MOV     R2, LR                    ; Set LR to third argument
+
+;               AND     R12, SP, #4               ; Ensure stack is 8-byte aligned
+                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
+                AND     R12, R3, #4
+                SUB     SP, SP, R12               ; Adjust stack
+                PUSH    {R12, LR}                 ; Store stack adjustment and dummy LR
+
+                BL      CDAbtHandler
+
+                POP     {R12, LR}                 ; Get stack adjustment & discard dummy LR
+                ADD     SP, SP, R12               ; Unadjust stack
+
+                POP     {R0-R4, R12}              ; Restore stacked APCS registers
+                RFEFD   SP!                       ; Return from exception
+                ENDP
+
+FIQ_Handler\
+                PROC
+                EXPORT  FIQ_Handler               [WEAK]
+                ;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
+                ;; so if a real FIQ Handler is implemented, this will be needed before returning:
+                ;; LDR     R1, =GICI_BASE
+                ;; LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
+                B       .
+                ENDP
+
+SVC_Handler\
+                PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+
+IRQ_Handler\
+                PROC
+                EXPORT  IRQ_Handler                [WEAK]
+                IMPORT  IRQCount
+                IMPORT  IRQTable
+                IMPORT  IRQNestLevel
+
+                ;prologue
+                SUB     LR, LR, #4                  ; Pre-adjust LR
+                SRSFD   SP!, #Mode_SVC              ; Save LR_IRQ and SPRS_IRQ to SVC mode stack
+                CPS     #Mode_SVC                   ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL
+                PUSH    {R0-R3, R12}                ; Save remaining APCS corruptible registers to SVC stack
+
+;               AND     R1, SP, #4                  ; Ensure stack is 8-byte aligned
+                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
+                AND     R1, R3, #4
+                SUB     SP, SP, R1                  ; Adjust stack
+                PUSH    {R1, LR}                    ; Store stack adjustment and LR_SVC to SVC stack
+
+                LDR     R0, =IRQNestLevel           ; Get address of nesting counter
+                LDR     R1, [R0]
+                ADD     R1, R1, #1                  ; Increment nesting counter
+                STR     R1, [R0]
+
+                ;identify and acknowledge interrupt
+                LDR     R1, =GICI_BASE
+                LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
+                LDR     R0, [R1, #ICCIAR_OFFSET]    ; Read ICCIAR (GIC CPU Interface register)
+                DSB                                 ; Ensure that interrupt acknowledge completes before re-enabling interrupts
+
+                ; Workaround GIC 390 errata 733075
+                ; If the ID is not 0, then service the interrupt as normal.
+                ; If the ID is 0 and active, then service interrupt ID 0 as normal.
+                ; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
+                ;   with a dummy write to ICDIPR0.  This interrupt should be treated as spurious and not serviced.
+                ;
+                LDR     R2, =GICD_BASE
+                LDR     R3, =GIC_ERRATA_CHECK_1
+                CMP     R0, R3
+                BEQ     unlock_cpu
+                LDR     R3, =GIC_ERRATA_CHECK_2
+                CMP     R0, R3
+                BEQ     unlock_cpu
+                CMP     R0, #0
+                BNE     int_active					; If the ID is not 0, then service the interrupt
+                LDR     R3, [R2, #ICDABR0_OFFSET]   ; Get the interrupt state
+                TST     R3, #1
+                BNE     int_active                  ; If active, then service the interrupt
+unlock_cpu
+                LDR     R3, [R2, #ICDIPR0_OFFSET]   ; Not active, so unlock the CPU interface
+                STR     R3, [R2, #ICDIPR0_OFFSET]   ;   with a dummy write
+                DSB                                 ; Ensure the write completes before continuing
+                B       ret_irq                     ; Do not service the spurious interrupt
+                ; End workaround
+
+int_active
+                LDR     R2, =IRQCount               ; Read number of IRQs
+                LDR     R2, [R2]
+                CMP     R0, R2                      ; Clean up and return if no handler
+                BHS     ret_irq                     ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling
+                LDR     R2, =IRQTable               ; Get address of handler
+                LDR     R2, [R2, R0, LSL #2]
+                CMP     R2, #0                      ; Clean up and return if handler address is 0
+                BEQ     ret_irq
+                PUSH    {R0,R1}
+
+                CPSIE   i                           ; Now safe to re-enable interrupts
+                BLX     R2                          ; Call handler. R0 will be IRQ number
+                CPSID   i                           ; Disable interrupts again
+
+                ;write EOIR (GIC CPU Interface register)
+                POP     {R0,R1}
+                DSB                                 ; Ensure that interrupt source is cleared before we write the EOIR
+ret_irq
+                ;epilogue
+                STR     R0, [R1, #ICCEOIR_OFFSET]
+
+                LDR     R0, =IRQNestLevel           ; Get address of nesting counter
+                LDR     R1, [R0]
+                SUB     R1, R1, #1                  ; Decrement nesting counter
+                STR     R1, [R0]
+
+                POP     {R1, LR}                    ; Get stack adjustment and restore LR_SVC
+                ADD     SP, SP, R1                  ; Unadjust stack
+
+                POP     {R0-R3,R12}                 ; Restore stacked APCS registers
+                RFEFD   SP!                         ; Return from exception
+                ENDP
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + USR_Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ENDIF
+
+
+                END
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/VKRZA1H.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1059 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+ * @file     VKRZA1H.h
+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File for 
+ *           Renesas RZA1H Device Series
+ * @version
+ * @date     19 Sept 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+
+#ifndef __VKRZA1H_H__
+#define __VKRZA1H_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+/******  SGI Interrupts Numbers                 ****************************************/
+  SGI0_IRQn           =  0,
+  SGI1_IRQn           =  1,
+  SGI2_IRQn           =  2,
+  SGI3_IRQn           =  3,
+  SGI4_IRQn           =  4,
+  SGI5_IRQn           =  5,
+  SGI6_IRQn           =  6,
+  SGI7_IRQn           =  7,
+  SGI8_IRQn           =  8,
+  SGI9_IRQn           =  9,
+  SGI10_IRQn          = 10,
+  SGI11_IRQn          = 11,
+  SGI12_IRQn          = 12,
+  SGI13_IRQn          = 13,
+  SGI14_IRQn          = 14,
+  SGI15_IRQn          = 15,
+
+/******  Cortex-A9 Processor Exceptions Numbers ****************************************/
+  /* 16 - 578 */
+  PMUIRQ0_IRQn         = 16,
+  COMMRX0_IRQn         = 17,
+  COMMTX0_IRQn         = 18,
+  CTIIRQ0_IRQn         = 19,
+
+  IRQ0_IRQn            = 32,
+  IRQ1_IRQn            = 33,
+  IRQ2_IRQn            = 34,
+  IRQ3_IRQn            = 35,
+  IRQ4_IRQn            = 36,
+  IRQ5_IRQn            = 37,
+  IRQ6_IRQn            = 38,
+  IRQ7_IRQn            = 39,
+
+  PL310ERR_IRQn        = 40,
+
+  DMAINT0_IRQn         = 41,        /*!< DMAC Interrupt         */
+  DMAINT1_IRQn         = 42,        /*!< DMAC Interrupt         */
+  DMAINT2_IRQn         = 43,        /*!< DMAC Interrupt         */
+  DMAINT3_IRQn         = 44,        /*!< DMAC Interrupt         */
+  DMAINT4_IRQn         = 45,        /*!< DMAC Interrupt         */
+  DMAINT5_IRQn         = 46,        /*!< DMAC Interrupt         */
+  DMAINT6_IRQn         = 47,        /*!< DMAC Interrupt         */
+  DMAINT7_IRQn         = 48,        /*!< DMAC Interrupt         */
+  DMAINT8_IRQn         = 49,        /*!< DMAC Interrupt         */
+  DMAINT9_IRQn         = 50,        /*!< DMAC Interrupt         */
+  DMAINT10_IRQn        = 51,        /*!< DMAC Interrupt         */
+  DMAINT11_IRQn        = 52,        /*!< DMAC Interrupt         */
+  DMAINT12_IRQn        = 53,        /*!< DMAC Interrupt         */
+  DMAINT13_IRQn        = 54,        /*!< DMAC Interrupt         */
+  DMAINT14_IRQn        = 55,        /*!< DMAC Interrupt         */
+  DMAINT15_IRQn        = 56,        /*!< DMAC Interrupt         */
+  DMAERR_IRQn          = 57,        /*!< DMAC Interrupt         */
+
+  /* 58-72 Reserved */
+
+  USBI0_IRQn           = 73,
+  USBI1_IRQn           = 74,
+
+  S0_VI_VSYNC0_IRQn    = 75,
+  S0_LO_VSYNC0_IRQn    = 76,
+  S0_VSYNCERR0_IRQn    = 77,
+  GR3_VLINE0_IRQn      = 78,
+  S0_VFIELD0_IRQn      = 79,
+  IV1_VBUFERR0_IRQn    = 80,
+  IV3_VBUFERR0_IRQn    = 81,
+  IV5_VBUFERR0_IRQn    = 82,
+  IV6_VBUFERR0_IRQn    = 83,
+  S0_WLINE0_IRQn       = 84,
+  S1_VI_VSYNC0_IRQn    = 85,
+  S1_LO_VSYNC0_IRQn    = 86,
+  S1_VSYNCERR0_IRQn    = 87,
+  S1_VFIELD0_IRQn      = 88,
+  IV2_VBUFERR0_IRQn    = 89,
+  IV4_VBUFERR0_IRQn    = 90,
+  S1_WLINE0_IRQn       = 91,
+  OIR_VI_VSYNC0_IRQn   = 92,
+  OIR_LO_VSYNC0_IRQn   = 93,
+  OIR_VSYNCERR0_IRQn   = 94,
+  OIR_VFIELD0_IRQn     = 95,
+  IV7_VBUFERR0_IRQn    = 96,
+  IV8_VBUFERR0_IRQn    = 97,
+  /* 98 Reserved */
+  S0_VI_VSYNC1_IRQn    = 99,
+  S0_LO_VSYNC1_IRQn    = 100,
+  S0_VSYNCERR1_IRQn    = 101,
+  GR3_VLINE1_IRQn      = 102,
+  S0_VFIELD1_IRQn      = 103,
+  IV1_VBUFERR1_IRQn    = 104,
+  IV3_VBUFERR1_IRQn    = 105,
+  IV5_VBUFERR1_IRQn    = 106,
+  IV6_VBUFERR1_IRQn    = 107,
+  S0_WLINE1_IRQn       = 108,
+  S1_VI_VSYNC1_IRQn    = 109,
+  S1_LO_VSYNC1_IRQn    = 110,
+  S1_VSYNCERR1_IRQn    = 111,
+  S1_VFIELD1_IRQn      = 112,
+  IV2_VBUFERR1_IRQn    = 113,
+  IV4_VBUFERR1_IRQn    = 114,
+  S1_WLINE1_IRQn       = 115,
+  OIR_VI_VSYNC1_IRQn   = 116,
+  OIR_LO_VSYNC1_IRQn   = 117,
+  OIR_VSYNCERR1_IRQn   = 118,
+  OIR_VFIELD1_IRQn     = 119,
+  IV7_VBUFERR1_IRQn    = 120,
+  IV8_VBUFERR1_IRQn    = 121,
+  /* Reserved = 122 */
+
+  IMRDI_IRQn           = 123,
+  IMR2I0_IRQn          = 124,
+  IMR2I1_IRQn          = 125,
+
+  JEDI_IRQn            = 126,
+  JDTI_IRQn            = 127,
+
+  CMP0_IRQn            = 128,
+  CMP1_IRQn            = 129,
+
+  INT0_IRQn            = 130,
+  INT1_IRQn            = 131,
+  INT2_IRQn            = 132,
+  INT3_IRQn            = 133,
+
+  OSTMI0TINT_IRQn      = 134,       /*!< OSTM Interrupt         */
+  OSTMI1TINT_IRQn      = 135,       /*!< OSTM Interrupt         */
+
+  CMI_IRQn             = 136,
+  WTOUT_IRQn           = 137,
+
+  ITI_IRQn             = 138,
+
+  TGI0A_IRQn           = 139,
+  TGI0B_IRQn           = 140,
+  TGI0C_IRQn           = 141,
+  TGI0D_IRQn           = 142,
+  TGI0V_IRQn           = 143,
+  TGI0E_IRQn           = 144,
+  TGI0F_IRQn           = 145,
+  TGI1A_IRQn           = 146,
+  TGI1B_IRQn           = 147,
+  TGI1V_IRQn           = 148,
+  TGI1U_IRQn           = 149,
+  TGI2A_IRQn           = 150,
+  TGI2B_IRQn           = 151,
+  TGI2V_IRQn           = 152,
+  TGI2U_IRQn           = 153,
+  TGI3A_IRQn           = 154,
+  TGI3B_IRQn           = 155,
+  TGI3C_IRQn           = 156,
+  TGI3D_IRQn           = 157,
+  TGI3V_IRQn           = 158,
+  TGI4A_IRQn           = 159,
+  TGI4B_IRQn           = 160,
+  TGI4C_IRQn           = 161,
+  TGI4D_IRQn           = 162,
+  TGI4V_IRQn           = 163,
+
+  CMI1_IRQn            = 164,
+  CMI2_IRQn            = 165,
+
+  SGDEI0_IRQn          = 166,
+  SGDEI1_IRQn          = 167,
+  SGDEI2_IRQn          = 168,
+  SGDEI3_IRQn          = 169,
+
+  ADI_IRQn             = 170,
+  LMTI_IRQn            = 171,
+
+  SSII0_IRQn           = 172,       /*!< SSIF Interrupt         */
+  SSIRXI0_IRQn         = 173,       /*!< SSIF Interrupt         */
+  SSITXI0_IRQn         = 174,       /*!< SSIF Interrupt         */
+  SSII1_IRQn           = 175,       /*!< SSIF Interrupt         */
+  SSIRXI1_IRQn         = 176,       /*!< SSIF Interrupt         */
+  SSITXI1_IRQn         = 177,       /*!< SSIF Interrupt         */
+  SSII2_IRQn           = 178,       /*!< SSIF Interrupt         */
+  SSIRTI2_IRQn         = 179,       /*!< SSIF Interrupt         */
+  SSII3_IRQn           = 180,       /*!< SSIF Interrupt         */
+  SSIRXI3_IRQn         = 181,       /*!< SSIF Interrupt         */
+  SSITXI3_IRQn         = 182,       /*!< SSIF Interrupt         */
+  SSII4_IRQn           = 183,       /*!< SSIF Interrupt         */
+  SSIRTI4_IRQn         = 184,       /*!< SSIF Interrupt         */
+  SSII5_IRQn           = 185,       /*!< SSIF Interrupt         */
+  SSIRXI5_IRQn         = 186,       /*!< SSIF Interrupt         */
+  SSITXI5_IRQn         = 187,       /*!< SSIF Interrupt         */
+
+  SPDIFI_IRQn          = 188,
+
+  INTIICTEI0_IRQn      = 189,       /*!< RIIC Interrupt         */
+  INTIICRI0_IRQn       = 190,       /*!< RIIC Interrupt         */
+  INTIICTI0_IRQn       = 191,       /*!< RIIC Interrupt         */
+  INTIICSPI0_IRQn      = 192,       /*!< RIIC Interrupt         */
+  INTIICSTI0_IRQn      = 193,       /*!< RIIC Interrupt         */
+  INTIICNAKI0_IRQn     = 194,       /*!< RIIC Interrupt         */
+  INTIICALI0_IRQn      = 195,       /*!< RIIC Interrupt         */
+  INTIICTMOI0_IRQn     = 196,       /*!< RIIC Interrupt         */
+  INTIICTEI1_IRQn      = 197,       /*!< RIIC Interrupt         */
+  INTIICRI1_IRQn       = 198,       /*!< RIIC Interrupt         */
+  INTIICTI1_IRQn       = 199,       /*!< RIIC Interrupt         */
+  INTIICSPI1_IRQn      = 200,       /*!< RIIC Interrupt         */
+  INTIICSTI1_IRQn      = 201,       /*!< RIIC Interrupt         */
+  INTIICNAKI1_IRQn     = 202,       /*!< RIIC Interrupt         */
+  INTIICALI1_IRQn      = 203,       /*!< RIIC Interrupt         */
+  INTIICTMOI1_IRQn     = 204,       /*!< RIIC Interrupt         */
+  INTIICTEI2_IRQn      = 205,       /*!< RIIC Interrupt         */
+  INTIICRI2_IRQn       = 206,       /*!< RIIC Interrupt         */
+  INTIICTI2_IRQn       = 207,       /*!< RIIC Interrupt         */
+  INTIICSPI2_IRQn      = 208,       /*!< RIIC Interrupt         */
+  INTIICSTI2_IRQn      = 209,       /*!< RIIC Interrupt         */
+  INTIICNAKI2_IRQn     = 210,       /*!< RIIC Interrupt         */
+  INTIICALI2_IRQn      = 211,       /*!< RIIC Interrupt         */
+  INTIICTMOI2_IRQn     = 212,       /*!< RIIC Interrupt         */
+  INTIICTEI3_IRQn      = 213,       /*!< RIIC Interrupt         */
+  INTIICRI3_IRQn       = 214,       /*!< RIIC Interrupt         */
+  INTIICTI3_IRQn       = 215,       /*!< RIIC Interrupt         */
+  INTIICSPI3_IRQn      = 216,       /*!< RIIC Interrupt         */
+  INTIICSTI3_IRQn      = 217,       /*!< RIIC Interrupt         */
+  INTIICNAKI3_IRQn     = 218,       /*!< RIIC Interrupt         */
+  INTIICALI3_IRQn      = 219,       /*!< RIIC Interrupt         */
+  INTIICTMOI3_IRQn     = 220,       /*!< RIIC Interrupt         */
+
+  SCIFBRI0_IRQn        = 221,       /*!< SCIF Interrupt         */
+  SCIFERI0_IRQn        = 222,       /*!< SCIF Interrupt         */
+  SCIFRXI0_IRQn        = 223,       /*!< SCIF Interrupt         */
+  SCIFTXI0_IRQn        = 224,       /*!< SCIF Interrupt         */
+  SCIFBRI1_IRQn        = 225,       /*!< SCIF Interrupt         */
+  SCIFERI1_IRQn        = 226,       /*!< SCIF Interrupt         */
+  SCIFRXI1_IRQn        = 227,       /*!< SCIF Interrupt         */
+  SCIFTXI1_IRQn        = 228,       /*!< SCIF Interrupt         */
+  SCIFBRI2_IRQn        = 229,       /*!< SCIF Interrupt         */
+  SCIFERI2_IRQn        = 230,       /*!< SCIF Interrupt         */
+  SCIFRXI2_IRQn        = 231,       /*!< SCIF Interrupt         */
+  SCIFTXI2_IRQn        = 232,       /*!< SCIF Interrupt         */
+  SCIFBRI3_IRQn        = 233,       /*!< SCIF Interrupt         */
+  SCIFERI3_IRQn        = 234,       /*!< SCIF Interrupt         */
+  SCIFRXI3_IRQn        = 235,       /*!< SCIF Interrupt         */
+  SCIFTXI3_IRQn        = 236,       /*!< SCIF Interrupt         */
+  SCIFBRI4_IRQn        = 237,       /*!< SCIF Interrupt         */
+  SCIFERI4_IRQn        = 238,       /*!< SCIF Interrupt         */
+  SCIFRXI4_IRQn        = 239,       /*!< SCIF Interrupt         */
+  SCIFTXI4_IRQn        = 240,       /*!< SCIF Interrupt         */
+  SCIFBRI5_IRQn        = 241,       /*!< SCIF Interrupt         */
+  SCIFERI5_IRQn        = 242,       /*!< SCIF Interrupt         */
+  SCIFRXI5_IRQn        = 243,       /*!< SCIF Interrupt         */
+  SCIFTXI5_IRQn        = 244,       /*!< SCIF Interrupt         */
+  SCIFBRI6_IRQn        = 245,       /*!< SCIF Interrupt         */
+  SCIFERI6_IRQn        = 246,       /*!< SCIF Interrupt         */
+  SCIFRXI6_IRQn        = 247,       /*!< SCIF Interrupt         */
+  SCIFTXI6_IRQn        = 248,       /*!< SCIF Interrupt         */
+  SCIFBRI7_IRQn        = 249,       /*!< SCIF Interrupt         */
+  SCIFERI7_IRQn        = 250,       /*!< SCIF Interrupt         */
+  SCIFRXI7_IRQn        = 251,       /*!< SCIF Interrupt         */
+  SCIFTXI7_IRQn        = 252,       /*!< SCIF Interrupt         */
+
+  INTRCANGERR_IRQn     = 253,
+  INTRCANGRECC_IRQn    = 254,
+  INTRCAN0REC_IRQn     = 255,
+  INTRCAN0ERR_IRQn     = 256,
+  INTRCAN0TRX_IRQn     = 257,
+  INTRCAN1REC_IRQn     = 258,
+  INTRCAN1ERR_IRQn     = 259,
+  INTRCAN1TRX_IRQn     = 260,
+  INTRCAN2REC_IRQn     = 261,
+  INTRCAN2ERR_IRQn     = 262,
+  INTRCAN2TRX_IRQn     = 263,
+  INTRCAN3REC_IRQn     = 264,
+  INTRCAN3ERR_IRQn     = 265,
+  INTRCAN3TRX_IRQn     = 266,
+  INTRCAN4REC_IRQn     = 267,
+  INTRCAN4ERR_IRQn     = 268,
+  INTRCAN4TRX_IRQn     = 269,
+
+  RSPISPEI0_IRQn       = 270,       /*!< RSPI Interrupt         */
+  RSPISPRI0_IRQn       = 271,       /*!< RSPI Interrupt         */
+  RSPISPTI0_IRQn       = 272,       /*!< RSPI Interrupt         */
+  RSPISPEI1_IRQn       = 273,       /*!< RSPI Interrupt         */
+  RSPISPRI1_IRQn       = 274,       /*!< RSPI Interrupt         */
+  RSPISPTI1_IRQn       = 275,       /*!< RSPI Interrupt         */
+  RSPISPEI2_IRQn       = 276,       /*!< RSPI Interrupt         */
+  RSPISPRI2_IRQn       = 277,       /*!< RSPI Interrupt         */
+  RSPISPTI2_IRQn       = 278,       /*!< RSPI Interrupt         */
+  RSPISPEI3_IRQn       = 279,       /*!< RSPI Interrupt         */
+  RSPISPRI3_IRQn       = 280,       /*!< RSPI Interrupt         */
+  RSPISPTI3_IRQn       = 281,       /*!< RSPI Interrupt         */
+  RSPISPEI4_IRQn       = 282,       /*!< RSPI Interrupt         */
+  RSPISPRI4_IRQn       = 283,       /*!< RSPI Interrupt         */
+  RSPISPTI4_IRQn       = 284,       /*!< RSPI Interrupt         */
+
+  IEBBTD_IRQn          = 285,
+  IEBBTERR_IRQn        = 286,
+  IEBBTSTA_IRQn        = 287,
+  IEBBTV_IRQn          = 288,
+
+  ISY_IRQn             = 289,
+  IERR_IRQn            = 290,
+  ITARG_IRQn           = 291,
+  ISEC_IRQn            = 292,
+  IBUF_IRQn            = 293,
+  IREADY_IRQn          = 294,
+
+  STERB_IRQn           = 295,
+  FLTENDI_IRQn         = 296,
+  FLTREQ0I_IRQn        = 297,
+  FLTREQ1I_IRQn        = 298,
+
+  MMC0_IRQn            = 299,
+  MMC1_IRQn            = 300,
+  MMC2_IRQn            = 301,
+
+  SCHI0_3_IRQn         = 302,
+  SDHI0_0_IRQn         = 303,
+  SDHI0_1_IRQn         = 304,
+  SCHI1_3_IRQn         = 305,
+  SDHI1_0_IRQn         = 306,
+  SDHI1_1_IRQn         = 307,
+
+  ARM_IRQn             = 308,
+  PRD_IRQn             = 309,
+  CUP_IRQn             = 310,
+
+  SCUAI0_IRQn          = 311,
+  SCUAI1_IRQn          = 312,
+  SCUFDI0_IRQn         = 313,
+  SCUFDI1_IRQn         = 314,
+  SCUFDI2_IRQn         = 315,
+  SCUFDI3_IRQn         = 316,
+  SCUFUI0_IRQn         = 317,
+  SCUFUI1_IRQn         = 318,
+  SCUFUI2_IRQn         = 319,
+  SCUFUI3_IRQn         = 320,
+  SCUDVI0_IRQn         = 321,
+  SCUDVI1_IRQn         = 322,
+  SCUDVI2_IRQn         = 323,
+  SCUDVI3_IRQn         = 324,
+
+  MLB_CINT_IRQn        = 325,
+  MLB_SINT_IRQn        = 326,
+
+  DRC10_IRQn           = 327,
+  DRC11_IRQn           = 328,
+
+  /* 329-330 Reserved  */
+
+  LINI0_INT_T_IRQn     = 331,
+  LINI0_INT_R_IRQn     = 332,
+  LINI0_INT_S_IRQn     = 333,
+  LINI0_INT_M_IRQn     = 334,
+  LINI1_INT_T_IRQn     = 335,
+  LINI1_INT_R_IRQn     = 336,
+  LINI1_INT_S_IRQn     = 337,
+  LINI1_INT_M_IRQn     = 338,
+
+  /* 339-346 Reserved */
+
+  SCIERI0_IRQn         = 347,
+  SCIRXI0_IRQn         = 348,
+  SCITXI0_IRQn         = 349,
+  SCITEI0_IRQn         = 350,
+  SCIERI1_IRQn         = 351,
+  SCIRXI1_IRQn         = 352,
+  SCITXI1_IRQn         = 353,
+  SCITEI1_IRQn         = 354,
+
+  AVBI_DATA            = 355,
+  AVBI_ERROR           = 356,
+  AVBI_MANAGE          = 357,
+  AVBI_MAC             = 358,
+
+  ETHERI_IRQn          = 359,
+
+  /* 360-363 Reserved */
+
+  CEUI_IRQn            = 364,
+
+  /* 365-380 Reserved */
+
+
+  H2XMLB_ERRINT_IRQn   = 381,
+  H2XIC1_ERRINT_IRQn   = 382,
+  X2HPERI1_ERRINT_IRQn = 383,
+  X2HPERR2_ERRINT_IRQn = 384,
+  X2HPERR34_ERRINT_IRQn= 385,
+  X2HPERR5_ERRINT_IRQn = 386,
+  X2HPERR67_ERRINT_IRQn= 387,
+  X2HDBGR_ERRINT_IRQn  = 388,
+  X2HBSC_ERRINT_IRQn   = 389,   
+  X2HSPI1_ERRINT_IRQn  = 390,   
+  X2HSPI2_ERRINT_IRQn  = 391,   
+  PRRI_IRQn            = 392,
+
+  IFEI0_IRQn           = 393,
+  OFFI0_IRQn           = 394,
+  PFVEI0_IRQn          = 395,
+  IFEI1_IRQn           = 396,
+  OFFI1_IRQn           = 397,
+  PFVEI1_IRQn          = 398,
+
+  /* 399-415 Reserved */
+  TINT0_IRQn           = 416,
+  TINT1_IRQn           = 417,
+  TINT2_IRQn           = 418,
+  TINT3_IRQn           = 419,
+  TINT4_IRQn           = 420,
+  TINT5_IRQn           = 421,
+  TINT6_IRQn           = 422,
+  TINT7_IRQn           = 423,
+  TINT8_IRQn           = 424,
+  TINT9_IRQn           = 425,
+  TINT10_IRQn          = 426,
+  TINT11_IRQn          = 427,
+  TINT12_IRQn          = 428,
+  TINT13_IRQn          = 429,
+  TINT14_IRQn          = 430,
+  TINT15_IRQn          = 431,
+  TINT16_IRQn          = 432,
+  TINT17_IRQn          = 433,
+  TINT18_IRQn          = 434,
+  TINT19_IRQn          = 435,
+  TINT20_IRQn          = 436,
+  TINT21_IRQn          = 437,
+  TINT22_IRQn          = 438,
+  TINT23_IRQn          = 439,
+  TINT24_IRQn          = 440,
+  TINT25_IRQn          = 441,
+  TINT26_IRQn          = 442,
+  TINT27_IRQn          = 443,
+  TINT28_IRQn          = 444,
+  TINT29_IRQn          = 445,
+  TINT30_IRQn          = 446,
+  TINT31_IRQn          = 447,
+  TINT32_IRQn          = 448,
+  TINT33_IRQn          = 449,
+  TINT34_IRQn          = 450,
+  TINT35_IRQn          = 451,
+  TINT36_IRQn          = 452,
+  TINT37_IRQn          = 453,
+  TINT38_IRQn          = 454,
+  TINT39_IRQn          = 455,
+  TINT40_IRQn          = 456,
+  TINT41_IRQn          = 457,
+  TINT42_IRQn          = 458,
+  TINT43_IRQn          = 459,
+  TINT44_IRQn          = 460,
+  TINT45_IRQn          = 461,
+  TINT46_IRQn          = 462,
+  TINT47_IRQn          = 463,
+  TINT48_IRQn          = 464,
+  TINT49_IRQn          = 465,
+  TINT50_IRQn          = 466,
+  TINT51_IRQn          = 467,
+  TINT52_IRQn          = 468,
+  TINT53_IRQn          = 469,
+  TINT54_IRQn          = 470,
+  TINT55_IRQn          = 471,
+  TINT56_IRQn          = 472,
+  TINT57_IRQn          = 473,
+  TINT58_IRQn          = 474,
+  TINT59_IRQn          = 475,
+  TINT60_IRQn          = 476,
+  TINT61_IRQn          = 477,
+  TINT62_IRQn          = 478,
+  TINT63_IRQn          = 479,
+  TINT64_IRQn          = 480,
+  TINT65_IRQn          = 481,
+  TINT66_IRQn          = 482,
+  TINT67_IRQn          = 483,
+  TINT68_IRQn          = 484,
+  TINT69_IRQn          = 485,
+  TINT70_IRQn          = 486,
+  TINT71_IRQn          = 487,
+  TINT72_IRQn          = 488,
+  TINT73_IRQn          = 489,
+  TINT74_IRQn          = 490,
+  TINT75_IRQn          = 491,
+  TINT76_IRQn          = 492,
+  TINT77_IRQn          = 493,
+  TINT78_IRQn          = 494,
+  TINT79_IRQn          = 495,
+  TINT80_IRQn          = 496,
+  TINT81_IRQn          = 497,
+  TINT82_IRQn          = 498,
+  TINT83_IRQn          = 499,
+  TINT84_IRQn          = 500,
+  TINT85_IRQn          = 501,
+  TINT86_IRQn          = 502,
+  TINT87_IRQn          = 503,
+  TINT88_IRQn          = 504,
+  TINT89_IRQn          = 505,
+  TINT90_IRQn          = 506,
+  TINT91_IRQn          = 507,
+  TINT92_IRQn          = 508,
+  TINT93_IRQn          = 509,
+  TINT94_IRQn          = 510,
+  TINT95_IRQn          = 511,
+  TINT96_IRQn          = 512,
+  TINT97_IRQn          = 513,
+  TINT98_IRQn          = 514,
+  TINT99_IRQn          = 515,
+  TINT100_IRQn         = 516,
+  TINT101_IRQn         = 517,
+  TINT102_IRQn         = 518,
+  TINT103_IRQn         = 519,
+  TINT104_IRQn         = 520,
+  TINT105_IRQn         = 521,
+  TINT106_IRQn         = 522,
+  TINT107_IRQn         = 523,
+  TINT108_IRQn         = 524,
+  TINT109_IRQn         = 525,
+  TINT110_IRQn         = 526,
+  TINT111_IRQn         = 527,
+  TINT112_IRQn         = 528,
+  TINT113_IRQn         = 529,
+  TINT114_IRQn         = 530,
+  TINT115_IRQn         = 531,
+  TINT116_IRQn         = 532,
+  TINT117_IRQn         = 533,
+  TINT118_IRQn         = 534,
+  TINT119_IRQn         = 535,
+  TINT120_IRQn         = 536,
+  TINT121_IRQn         = 537,
+  TINT122_IRQn         = 538,
+  TINT123_IRQn         = 539,
+  TINT124_IRQn         = 540,
+  TINT125_IRQn         = 541,
+  TINT126_IRQn         = 542,
+  TINT127_IRQn         = 543,
+  TINT128_IRQn         = 544,
+  TINT129_IRQn         = 545,
+  TINT130_IRQn         = 546,
+  TINT131_IRQn         = 547,
+  TINT132_IRQn         = 548,
+  TINT133_IRQn         = 549,
+  TINT134_IRQn         = 550,
+  TINT135_IRQn         = 551,
+  TINT136_IRQn         = 552,
+  TINT137_IRQn         = 553,
+  TINT138_IRQn         = 554,
+  TINT139_IRQn         = 555,
+  TINT140_IRQn         = 556,
+  TINT141_IRQn         = 557,
+  TINT142_IRQn         = 558,
+  TINT143_IRQn         = 559,
+  TINT144_IRQn         = 560,
+  TINT145_IRQn         = 561,
+  TINT146_IRQn         = 562,
+  TINT147_IRQn         = 563,
+  TINT148_IRQn         = 564,
+  TINT149_IRQn         = 565,
+  TINT150_IRQn         = 566,
+  TINT151_IRQn         = 567,
+  TINT152_IRQn         = 568,
+  TINT153_IRQn         = 569,
+  TINT154_IRQn         = 570,
+  TINT155_IRQn         = 571,
+  TINT156_IRQn         = 572,
+  TINT157_IRQn         = 573,
+  TINT158_IRQn         = 574,
+  TINT159_IRQn         = 575,
+  TINT160_IRQn         = 576,
+  TINT161_IRQn         = 577,
+  TINT162_IRQn         = 578,
+  TINT163_IRQn         = 579,
+  TINT164_IRQn         = 580,
+  TINT165_IRQn         = 581,
+  TINT166_IRQn         = 582,
+  TINT167_IRQn         = 583,
+  TINT168_IRQn         = 584,
+  TINT169_IRQn         = 585,
+  TINT170_IRQn         = 586
+
+} IRQn_Type;
+
+#define Renesas_RZ_A1_IRQ_MAX  TINT170_IRQn
+
+/* --------  Configuration of the Cortex-A9 Processor and Core Peripherals  ------- */
+#define __CA9_REV                 0x0000    /*!< Core revision r0                                */
+
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */
+
+#define __FPU_PRESENT             1         /*!< FPU present or not                               */
+
+#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+
+#include <core_ca9.h>
+#include "system_VKRZA1H.h"
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral Section                          */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals
+  Renesas_RZ_A1 Device Specific Peripheral registers structures
+  @{
+*/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+#include "pl310.h"
+#include "gic.h"
+#include "nvic_wrapper.h"
+#include "cmsis_nvic.h"
+
+#include "ostm_iodefine.h"
+#include "gpio_iodefine.h"
+#include "cpg_iodefine.h"
+#include "l2c_iodefine.h"
+
+#if defined ( __CC_ARM   )
+#pragma no_anon_unions
+#endif
+
+/*@}*/ /* end of group Renesas_RZ_A1_Peripherals */
+
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping
+  @{
+*/
+
+/* R7S72100 CPU board  */
+#define Renesas_RZ_A1_NORFLASH_BASE0               (0x00000000UL)                        /*!< (FLASH0    ) Base Address */
+#define Renesas_RZ_A1_NORFLASH_BASE1               (0x04000000UL)                        /*!< (FLASH1    ) Base Address */
+#define Renesas_RZ_A1_SDRAM_BASE0                  (0x08000000UL)                        /*!< (SDRAM0    ) Base Address */
+#define Renesas_RZ_A1_SDRAM_BASE1                  (0x0C000000UL)                        /*!< (SDRAM1    ) Base Address */
+#define Renesas_RZ_A1_USER_AREA0                   (0x10000000UL)                        /*!< (USER0     ) Base Address */
+#define Renesas_RZ_A1_USER_AREA1                   (0x14000000UL)                        /*!< (USER1     ) Base Address */
+#define Renesas_RZ_A1_SPI_IO0                      (0x18000000UL)                        /*!< (SPI_IO0   ) Base Address */
+#define Renesas_RZ_A1_SPI_IO1                      (0x1C000000UL)                        /*!< (SPI_IO1   ) Base Address */
+#define Renesas_RZ_A1_ONCHIP_SRAM_BASE             (0x20000000UL)                        /*!< (SRAM_OC   ) Base Address */
+#define Renesas_RZ_A1_SPI_MIO_BASE                 (0x3fe00000UL)                        /*!< (SPI_MIO   ) Base Address */
+#define Renesas_RZ_A1_BSC_BASE                     (0x3ff00000UL)                        /*!< (BSC       ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE0                 (0xe8000000UL)                        /*!< (PERIPH0   ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE1                 (0xfcf00000UL)                        /*!< (PERIPH1   ) Base Address */
+#define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE         (0xe8201000UL)                        /*!< (GIC DIST  ) Base Address */
+#define Renesas_RZ_A1_GIC_INTERFACE_BASE           (0xe8202000UL)                        /*!< (GIC CPU IF) Base Address */
+#define Renesas_RZ_A1_PL310_BASE                   (0x3ffff000UL)                        /*!< (PL310     ) Base Address */
+#define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE          (0x60000000UL)                        /*!< (SRAM_OC   ) Base Address */
+
+//Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map
+//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0.
+#define section_normal(descriptor_l1, region)     region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = NON_SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   __get_section_descriptor(&descriptor_l1, region);
+
+#define section_normal_nc(descriptor_l1, region)     region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0.
+#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = NON_SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Normal_RO. Sect_Normal_Cod, but not executable
+#define section_normal_ro(descriptor_l1, region)  region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = NON_SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Normal_RW. Sect_Normal_Cod, but writeable
+#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = WB_WA; \
+                                   region.outer_norm_t = WB_WA; \
+                                   region.mem_t = NORMAL; \
+                                   region.sec_t = NON_SECURE; \
+                                   region.xn_t = EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
+#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
+#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = READ; \
+                                   region.user_t = READ; \
+                                   region.sh_t = NON_SHARED; \
+                                   __get_section_descriptor(&descriptor_l1, region);
+
+//Sect_Device_RW. Sect_Device_RO, but writeable
+#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = STRONGLY_ORDERED; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   __get_section_descriptor(&descriptor_l1, region);
+//Page_4k_Device_RW.  Shared device, not executable, rw, domain 0
+#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = SHARED_DEVICE; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
+
+//Page_64k_Device_RW.  Shared device, not executable, rw, domain 0
+#define page64k_device_rw(descriptor_l1, descriptor_l2, region)  region.rg_t = PAGE_64k; \
+                                   region.domain = 0x0; \
+                                   region.e_t = ECC_DISABLED; \
+                                   region.g_t = GLOBAL; \
+                                   region.inner_norm_t = NON_CACHEABLE; \
+                                   region.outer_norm_t = NON_CACHEABLE; \
+                                   region.mem_t = SHARED_DEVICE; \
+                                   region.sec_t = SECURE; \
+                                   region.xn_t = NON_EXECUTE; \
+                                   region.priv_t = RW; \
+                                   region.user_t = RW; \
+                                   region.sh_t = NON_SHARED; \
+                                   __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
+
+/*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
+
+/******************************************************************************/
+/*                         Clock Settings                                     */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions
+  @{
+*/
+
+/*
+ * Clock Mode 0 settings
+ * SW1-4(MD_CLK):ON
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1035
+ *   CLKEN2    = 0b - unstable
+ *   CLKEN[1:0]=01b - Output, Low, Low
+ *   IFC[1:0]  =00b - CPU clock is 1/1 PLL clock
+ * FRQCR2=0x0001
+ *   GFC[1:0]  =01b - Graphic clock is 2/3 bus clock
+ */
+#define CM0_RENESAS_RZ_A1_CLKIN  ( 13333333u)
+#define CM0_RENESAS_RZ_A1_CLKO   ( 66666666u)
+#define CM0_RENESAS_RZ_A1_I_CLK  (400000000u)
+#define CM0_RENESAS_RZ_A1_G_CLK  (266666666u)
+#define CM0_RENESAS_RZ_A1_B_CLK  (133333333u)
+#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
+#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
+
+/*
+ * Clock Mode 1 settings
+ * SW1-4(MD_CLK):OFF
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1335
+ *   CLKEN2    = 0b - unstable
+ *   CLKEN[1:0]=01b - Output, Low, Low
+ *   IFC[1:0]  =11b - CPU clock is 1/3 PLL clock
+ * FRQCR2=0x0003
+ *   GFC[1:0]  =11b - graphic clock is 1/3 bus clock
+ */
+#define CM1_RENESAS_RZ_A1_CLKIN  ( 48000000u)
+#define CM1_RENESAS_RZ_A1_CLKO   ( 64000000u)
+#define CM1_RENESAS_RZ_A1_I_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_G_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_B_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
+#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
+
+/*@}*/ /* end of group Renesas_RZ_A1_Clocks */
+
+/******************************************************************************/
+/*                         CPG   Settings                                     */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions
+  @{
+*/
+
+#define CPG_FRQCR_SHIFT_CKOEN2  (14)
+#define CPG_FRQCR_BIT_CKOEN2    (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
+#define CPG_FRQCR_SHIFT_CKOEN0  (12)
+#define CPG_FRQCR_BITS_CKOEN0   (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
+#define CPG_FRQCR_SHIFT_IFC     (8)
+#define CPG_FRQCR_BITS_IFC      (0x3 << CPG_FRQCR_SHIFT_IFC)
+
+#define CPG_FRQCR2_SHIFT_GFC    (0)
+#define CPG_FRQCR2_BITS_GFC     (0x3 << CPG_FRQCR2_SHIFT_GFC)
+
+
+#define CPG_STBCR1_BIT_STBY     (0x80u)
+#define CPG_STBCR1_BIT_DEEP     (0x40u)
+#define CPG_STBCR2_BIT_HIZ      (0x80u)
+#define CPG_STBCR2_BIT_MSTP20   (0x01u) /* CoreSight */
+#define CPG_STBCR3_BIT_MSTP37   (0x80u) /* IEBus */
+#define CPG_STBCR3_BIT_MSTP36   (0x40u) /* IrDA */
+#define CPG_STBCR3_BIT_MSTP35   (0x20u) /* LIN0 */
+#define CPG_STBCR3_BIT_MSTP34   (0x10u) /* LIN1 */
+#define CPG_STBCR3_BIT_MSTP33   (0x08u) /* Multi-Function Timer */
+#define CPG_STBCR3_BIT_MSTP32   (0x04u) /* CAN */
+#define CPG_STBCR3_BIT_MSTP30   (0x01u) /* Motor Control PWM Timer */
+#define CPG_STBCR4_BIT_MSTP47   (0x80u) /* SCIF0 */
+#define CPG_STBCR4_BIT_MSTP46   (0x40u) /* SCIF1 */
+#define CPG_STBCR4_BIT_MSTP45   (0x20u) /* SCIF2 */
+#define CPG_STBCR4_BIT_MSTP44   (0x10u) /* SCIF3 */
+#define CPG_STBCR4_BIT_MSTP43   (0x08u) /* SCIF4 */
+#define CPG_STBCR4_BIT_MSTP42   (0x04u) /* SCIF5 */
+#define CPG_STBCR4_BIT_MSTP41   (0x02u) /* SCIF6 */
+#define CPG_STBCR4_BIT_MSTP40   (0x01u) /* SCIF7 */
+#define CPG_STBCR5_BIT_MSTP57   (0x80u) /* SCI0 */
+#define CPG_STBCR5_BIT_MSTP56   (0x40u) /* SCI1 */
+#define CPG_STBCR5_BIT_MSTP55   (0x20u) /* Sound Generator0 */
+#define CPG_STBCR5_BIT_MSTP54   (0x10u) /* Sound Generator1 */
+#define CPG_STBCR5_BIT_MSTP53   (0x08u) /* Sound Generator2 */
+#define CPG_STBCR5_BIT_MSTP52   (0x04u) /* Sound Generator3 */
+#define CPG_STBCR5_BIT_MSTP51   (0x02u) /* OSTM0 */
+#define CPG_STBCR5_BIT_MSTP50   (0x01u) /* OSTM1 */
+#define CPG_STBCR6_BIT_MSTP67   (0x80u) /* General A/D Comvertor */
+#define CPG_STBCR6_BIT_MSTP66   (0x40u) /* Capture Engine */
+#define CPG_STBCR6_BIT_MSTP65   (0x20u) /* Display out comparison0 */
+#define CPG_STBCR6_BIT_MSTP64   (0x10u) /* Display out comparison1 */   
+#define CPG_STBCR6_BIT_MSTP63   (0x08u) /* Dynamic Range Compalator0 */
+#define CPG_STBCR6_BIT_MSTP62   (0x04u) /* Dynamic Range Compalator1 */
+#define CPG_STBCR6_BIT_MSTP61   (0x02u) /* JPEG Decoder */
+#define CPG_STBCR6_BIT_MSTP60   (0x01u) /* Realtime Clock */
+#define CPG_STBCR7_BIT_MSTP77   (0x80u) /* Video Decoder0 */
+#define CPG_STBCR7_BIT_MSTP76   (0x40u) /* Video Decoder1 */
+#define CPG_STBCR7_BIT_MSTP74   (0x10u) /* Ether */
+#define CPG_STBCR7_BIT_MSTP73   (0x04u) /* NAND Flash Memory Controller */
+#define CPG_STBCR7_BIT_MSTP71   (0x02u) /* USB0 */
+#define CPG_STBCR7_BIT_MSTP70   (0x01u) /* USB1 */
+#define CPG_STBCR8_BIT_MSTP87   (0x80u) /* IMR-LS2_0 */
+#define CPG_STBCR8_BIT_MSTP86   (0x40u) /* IMR-LS2_1 */
+#define CPG_STBCR8_BIT_MSTP85   (0x20u) /* IMR-LSD */
+#define CPG_STBCR8_BIT_MSTP84   (0x10u) /* MMC Host Interface */
+#define CPG_STBCR8_BIT_MSTP83   (0x08u) /* MediaLB */
+#define CPG_STBCR8_BIT_MSTP81   (0x02u) /* SCUX */
+#define CPG_STBCR9_BIT_MSTP97   (0x80u) /* RIIC0 */
+#define CPG_STBCR9_BIT_MSTP96   (0x40u) /* RIIC1 */
+#define CPG_STBCR9_BIT_MSTP95   (0x20u) /* RIIC2 */
+#define CPG_STBCR9_BIT_MSTP94   (0x10u) /* RIIC3 */
+#define CPG_STBCR9_BIT_MSTP93   (0x08u) /* SPI Multi I/O Bus Controller0 */
+#define CPG_STBCR9_BIT_MSTP92   (0x04u) /* SPI Multi I/O Bus Controller1 */
+#define CPG_STBCR9_BIT_MSTP91   (0x02u) /* VDC5_0 */
+#define CPG_STBCR9_BIT_MSTP90   (0x01u) /* VDC5_1 */
+#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
+#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
+#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
+#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
+#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
+#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
+#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
+#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
+#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
+#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
+#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
+#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
+#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
+#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
+#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
+#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
+#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
+#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
+#define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */
+#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
+#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
+#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
+#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
+#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
+#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
+#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
+#define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */
+#define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */
+#define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */
+#define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */
+#define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */
+#define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */
+#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
+#define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */
+#define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */
+#define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */
+#define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */
+#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
+#define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */
+#define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */
+#define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */
+#define CPG_SYSCR1_BIT_VRAME4   (0x10u) /* VRAM E Page4 */
+#define CPG_SYSCR1_BIT_VRAME3   (0x08u) /* VRAM E Page3 */
+#define CPG_SYSCR1_BIT_VRAME2   (0x04u) /* VRAM E Page2 */
+#define CPG_SYSCR1_BIT_VRAME1   (0x02u) /* VRAM E Page1 */
+#define CPG_SYSCR1_BIT_VRAME0   (0x01u) /* VRAM E Page0 */
+#define CPG_SYSCR2_BIT_VRAMWE4  (0x10u) /* VRAM WE Page4 */
+#define CPG_SYSCR2_BIT_VRAMWE3  (0x08u) /* VRAM WE Page3 */
+#define CPG_SYSCR2_BIT_VRAMWE2  (0x04u) /* VRAM WE Page2 */
+#define CPG_SYSCR2_BIT_VRAMWE1  (0x02u) /* VRAM WE Page1 */
+#define CPG_SYSCR2_BIT_VRAMWE0  (0x01u) /* VRAM WE Page0 */
+#define CPG_SYSCR3_BIT_RRAMWE3  (0x08u) /* RRAM WE Page3 */
+#define CPG_SYSCR3_BIT_RRAMWE2  (0x04u) /* RRAM WE Page2 */
+#define CPG_SYSCR3_BIT_RRAMWE1  (0x02u) /* RRAM WE Page1 */
+#define CPG_SYSCR3_BIT_RRAMWE0  (0x01u) /* RRAM WE Page0 */
+
+/*@}*/ /* end of group Renesas_RZ_A1_CPG */
+
+/******************************************************************************/
+/*                        GPIO   Settings                                     */
+/******************************************************************************/
+/** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions
+  @{
+*/
+
+#define GPIO_BIT_N0  (1u <<  0)
+#define GPIO_BIT_N1  (1u <<  1)
+#define GPIO_BIT_N2  (1u <<  2)
+#define GPIO_BIT_N3  (1u <<  3)
+#define GPIO_BIT_N4  (1u <<  4)
+#define GPIO_BIT_N5  (1u <<  5)
+#define GPIO_BIT_N6  (1u <<  6)
+#define GPIO_BIT_N7  (1u <<  7)
+#define GPIO_BIT_N8  (1u <<  8)
+#define GPIO_BIT_N9  (1u <<  9)
+#define GPIO_BIT_N10 (1u << 10)
+#define GPIO_BIT_N11 (1u << 11)
+#define GPIO_BIT_N12 (1u << 12)
+#define GPIO_BIT_N13 (1u << 13)
+#define GPIO_BIT_N14 (1u << 14)
+#define GPIO_BIT_N15 (1u << 15)
+
+
+#define MD_BOOT10_MASK    (0x3)
+
+#define MD_BOOT10_BM0     (0x0)
+#define MD_BOOT10_BM1     (0x2)
+#define MD_BOOT10_BM3     (0x1)
+#define MD_BOOT10_BM4_5   (0x3)
+
+#define MD_CLK        (1u << 2)
+#define MD_CLKS       (1u << 3)
+
+/*@}*/ /* end of group Renesas_RZ_A1_GPIO */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __VKRZA1H_H__
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/cmsis.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC1768 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "VKRZA1H.h"
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/cmsis_nvic.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "VKRZA1H.h"
+
+extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    InterruptHandlerRegister(IRQn, (IRQHandler)vector);
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t vectors = (uint32_t)IRQTable[IRQn];
+    return vectors;
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/cmsis_nvic.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/dev_drv.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,86 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/******************************************************************************
+* File Name    : dev_drv.h
+* $Rev: 809 $
+* $Date:: 2014-04-09 15:06:36 +0900#$
+* Description  : Device driver header
+******************************************************************************/
+#ifndef DEV_DRV_H
+#define DEV_DRV_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+/* ==== Arguments, Return values ==== */
+#define DEVDRV_SUCCESS      (0)     /* Success */
+#define DEVDRV_ERROR        (-1)    /* Failure */
+
+/* ==== Flags ==== */
+#define DEVDRV_FLAG_OFF     (0)     /* Flag OFF */
+#define DEVDRV_FLAG_ON      (1)     /* Flag ON  */
+
+/* ==== Channels ==== */
+typedef enum devdrv_ch
+{
+    DEVDRV_CH_0,            /* Channel 0  */
+    DEVDRV_CH_1,            /* Channel 1  */
+    DEVDRV_CH_2,            /* Channel 2  */
+    DEVDRV_CH_3,            /* Channel 3  */
+    DEVDRV_CH_4,            /* Channel 4  */
+    DEVDRV_CH_5,            /* Channel 5  */
+    DEVDRV_CH_6,            /* Channel 6  */
+    DEVDRV_CH_7,            /* Channel 7  */
+    DEVDRV_CH_8,            /* Channel 8  */
+    DEVDRV_CH_9,            /* Channel 9  */
+    DEVDRV_CH_10,           /* Channel 10 */
+    DEVDRV_CH_11,           /* Channel 11 */
+    DEVDRV_CH_12,           /* Channel 12 */
+    DEVDRV_CH_13,           /* Channel 13 */
+    DEVDRV_CH_14,           /* Channel 14 */
+    DEVDRV_CH_15            /* Channel 15 */
+} devdrv_ch_t;
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+#endif  /* DEV_DRV_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/gic.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,306 @@
+/**************************************************************************//**
+ * @file     gic.c
+ * @brief    Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version
+ * @date     19 Sept 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#include "VKRZA1H.h"
+
+#define GICDistributor      ((GICDistributor_Type      *)     Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
+#define GICInterface        ((GICInterface_Type        *)     Renesas_RZ_A1_GIC_INTERFACE_BASE )   /*!< GIC Interface configuration struct */
+
+/* Globals for use of post-scatterloading code that must access GIC */
+const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE;
+const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE;
+
+void GIC_EnableDistributor(void)
+{
+    GICDistributor->ICDDCR |= 1; //enable distributor
+}
+
+void GIC_DisableDistributor(void)
+{
+    GICDistributor->ICDDCR &=~1; //disable distributor
+}
+
+uint32_t GIC_DistributorInfo(void)
+{
+    return (uint32_t)(GICDistributor->ICDICTR);
+}
+
+uint32_t GIC_DistributorImplementer(void)
+{
+    return (uint32_t)(GICDistributor->ICDIIDR);
+}
+
+void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
+{
+    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
+    field += IRQn % 4;
+    *field = (uint8_t)cpu_target & 0xf;
+}
+
+void GIC_SetICDICFR (const uint32_t *ICDICFRn)
+{
+    uint32_t i, num_irq;
+
+    //Get the maximum number of interrupts that the GIC supports
+    num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
+
+    for (i = 0; i < (num_irq/16); i++)
+    {
+        GICDistributor->ICDISPR[i] = *ICDICFRn++;
+    }
+}
+
+uint32_t GIC_GetTarget(IRQn_Type IRQn)
+{
+    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
+    field += IRQn % 4;
+    return ((uint32_t)*field & 0xf);
+}
+
+void GIC_EnableInterface(void)
+{
+    GICInterface->ICCICR |= 1; //enable interface
+}
+
+void GIC_DisableInterface(void)
+{
+    GICInterface->ICCICR &=~1; //disable distributor
+}
+
+IRQn_Type GIC_AcknowledgePending(void)
+{
+    return (IRQn_Type)(GICInterface->ICCIAR);
+}
+
+void GIC_EndInterrupt(IRQn_Type IRQn)
+{
+    GICInterface->ICCEOIR = IRQn;
+}
+
+void GIC_EnableIRQ(IRQn_Type IRQn)
+{
+    GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_DisableIRQ(IRQn_Type IRQn)
+{
+    GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
+{
+    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]);
+    int  bit_shift = (IRQn % 16)<<1;
+    uint8_t save_byte;
+
+    field += (bit_shift / 8);
+    bit_shift %= 8;
+
+    save_byte = *field;
+    save_byte &= ((uint8_t)~(3u << bit_shift));
+
+    *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift);
+}
+
+void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
+    field += (IRQn % 4);
+    *field = (uint8_t)priority;
+}
+
+uint32_t GIC_GetPriority(IRQn_Type IRQn)
+{
+    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
+    field += (IRQn % 4);
+    return (uint32_t)*field;
+}
+
+void GIC_InterfacePriorityMask(uint32_t priority)
+{
+    GICInterface->ICCPMR = priority & 0xff; //set priority mask
+}
+
+void GIC_SetBinaryPoint(uint32_t binary_point)
+{
+    GICInterface->ICCBPR = binary_point & 0x07; //set binary point
+}
+
+uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
+{
+    return (uint32_t)GICInterface->ICCBPR;
+}
+
+uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
+{
+    uint32_t pending, active;
+
+    active = ((GICDistributor->ICDABR[IRQn / 32])  >> (IRQn % 32)) & 0x1;
+    pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
+
+    return ((active<<1) | pending);
+}
+
+void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
+{
+    GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
+}
+
+void GIC_DistInit(void)
+{
+    //IRQn_Type i;
+    uint32_t i;
+    uint32_t num_irq = 0;
+    uint32_t priority_field;
+
+    //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+    //configuring all of the interrupts as Secure.
+
+    //Disable interrupt forwarding
+    GIC_DisableDistributor();
+    //Get the maximum number of interrupts that the GIC supports
+    num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
+
+    /* Priority level is implementation defined.
+     To determine the number of priority bits implemented write 0xFF to an ICDIPR
+     priority field and read back the value stored.*/
+    GIC_SetPriority((IRQn_Type)0, 0xff);
+    priority_field = GIC_GetPriority((IRQn_Type)0);
+
+    for (i = 32; i < num_irq; i++)
+    {
+        //Disable all SPI the interrupts
+        GIC_DisableIRQ((IRQn_Type)i);
+        //Set level-sensitive and N-N model
+        //GIC_SetLevelModel(i, 0, 0);
+        //Set priority
+        GIC_SetPriority((IRQn_Type)i, priority_field/2);
+        //Set target list to "all cpus"
+        GIC_SetTarget((IRQn_Type)i, 0xff);
+    }
+    /* Set level-edge and 1-N model */
+    /* GICDistributor->ICDICFR[ 0] is read only */
+    GICDistributor->ICDICFR[ 1] = 0x00000055;
+    GICDistributor->ICDICFR[ 2] = 0xFFFD5555;
+    GICDistributor->ICDICFR[ 3] = 0x555FFFFF;
+    GICDistributor->ICDICFR[ 4] = 0x55555555;
+    GICDistributor->ICDICFR[ 5] = 0x55555555;
+    GICDistributor->ICDICFR[ 6] = 0x55555555;
+    GICDistributor->ICDICFR[ 7] = 0x55555555;
+    GICDistributor->ICDICFR[ 8] = 0x5555F555;
+    GICDistributor->ICDICFR[ 9] = 0x55555555;
+    GICDistributor->ICDICFR[10] = 0x55555555;
+    GICDistributor->ICDICFR[11] = 0xF5555555;
+    GICDistributor->ICDICFR[12] = 0xF555F555;
+    GICDistributor->ICDICFR[13] = 0x5555F555;
+    GICDistributor->ICDICFR[14] = 0x55555555;
+    GICDistributor->ICDICFR[15] = 0x55555555;
+    GICDistributor->ICDICFR[16] = 0x55555555;
+    GICDistributor->ICDICFR[17] = 0xFD555555;
+    GICDistributor->ICDICFR[18] = 0x55555557;
+    GICDistributor->ICDICFR[19] = 0x55555555;
+    GICDistributor->ICDICFR[20] = 0xFFD55555;
+    GICDistributor->ICDICFR[21] = 0x5F55557F;
+    GICDistributor->ICDICFR[22] = 0xFD55555F;
+    GICDistributor->ICDICFR[23] = 0x55555557;
+    GICDistributor->ICDICFR[24] = 0x55555555;
+    GICDistributor->ICDICFR[25] = 0x55555555;
+    GICDistributor->ICDICFR[26] = 0x55555555;
+    GICDistributor->ICDICFR[27] = 0x55555555;
+    GICDistributor->ICDICFR[28] = 0x55555555;
+    GICDistributor->ICDICFR[29] = 0x55555555;
+    GICDistributor->ICDICFR[30] = 0x55555555;
+    GICDistributor->ICDICFR[31] = 0x55555555;
+    GICDistributor->ICDICFR[32] = 0x55555555;
+    GICDistributor->ICDICFR[33] = 0x55555555;
+
+    //Enable distributor
+    GIC_EnableDistributor();
+}
+
+void GIC_CPUInterfaceInit(void)
+{
+    IRQn_Type i;
+    uint32_t priority_field;
+
+    //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+    //configuring all of the interrupts as Secure.
+
+    //Disable interrupt forwarding
+    GIC_DisableInterface();
+
+    /* Priority level is implementation defined.
+     To determine the number of priority bits implemented write 0xFF to an ICDIPR
+     priority field and read back the value stored.*/
+    GIC_SetPriority((IRQn_Type)0, 0xff);
+    priority_field = GIC_GetPriority((IRQn_Type)0);
+
+    //SGI and PPI
+    for (i = (IRQn_Type)0; i < 32; i++)
+    {
+        //Set level-sensitive and N-N model for PPI
+        //if(i > 15)
+            //GIC_SetLevelModel(i, 0, 0);
+        //Disable SGI and PPI interrupts
+        GIC_DisableIRQ(i);
+        //Set priority
+        GIC_SetPriority(i, priority_field/2);
+    }
+    //Enable interface
+    GIC_EnableInterface();
+    //Set binary point to 0
+    GIC_SetBinaryPoint(0);
+    //Set priority mask
+    GIC_InterfacePriorityMask(0xff);
+}
+
+void GIC_Enable(void)
+{
+    GIC_DistInit();
+    GIC_CPUInterfaceInit(); //per CPU
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/gic.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,317 @@
+/**************************************************************************//**
+ * @file     gic.h
+ * @brief    Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version
+ * @date     29 August 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#ifndef GIC_H_
+#define GIC_H_
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/** \brief  Structure type to access the Generic Interrupt Controller Distributor (GICD)
+ */
+typedef struct
+{
+  __IO uint32_t ICDDCR;
+  __I  uint32_t ICDICTR;
+  __I  uint32_t ICDIIDR;
+       uint32_t RESERVED0[29];
+  __IO uint32_t ICDISR[32];
+  __IO uint32_t ICDISER[32];
+  __IO uint32_t ICDICER[32];
+  __IO uint32_t ICDISPR[32];
+  __IO uint32_t ICDICPR[32];
+  __I  uint32_t ICDABR[32];
+       uint32_t RESERVED1[32];
+  __IO uint32_t ICDIPR[256];
+  __IO uint32_t ICDIPTR[256];
+  __IO uint32_t ICDICFR[64];
+       uint32_t RESERVED2[128];
+  __IO uint32_t ICDSGIR;
+}  GICDistributor_Type;
+
+/** \brief  Structure type to access the Controller Interface (GICC)
+ */
+typedef struct
+{
+  __IO uint32_t ICCICR;          // +0x000 - RW - CPU Interface Control Register
+  __IO uint32_t ICCPMR;          // +0x004 - RW - Interrupt Priority Mask Register
+  __IO uint32_t ICCBPR;          // +0x008 - RW - Binary Point Register
+  __I  uint32_t ICCIAR;          // +0x00C - RO - Interrupt Acknowledge Register
+  __IO uint32_t ICCEOIR;         // +0x010 - WO - End of Interrupt Register
+  __I  uint32_t ICCRPR;          // +0x014 - RO - Running Priority Register
+  __I  uint32_t ICCHPIR;         // +0x018 - RO - Highest Pending Interrupt Register
+  __IO uint32_t ICCABPR;         // +0x01C - RW - Aliased Binary Point Register
+
+       uint32_t RESERVED[55];
+
+  __I  uint32_t ICCIIDR;         // +0x0FC - RO - CPU Interface Identification Register
+}  GICInterface_Type;
+
+/*@} end of GICD */
+
+/* ##########################   GIC functions  #################################### */
+/**  \brief      Functions that manage interrupts via the GIC.
+  @{
+ */
+
+/** \brief  Enable DistributorGICInterface->ICCICR |= 1; //enable interface
+
+   Enables the forwarding of pending interrupts to the CPU interfaces.
+
+ */
+void GIC_EnableDistributor(void);
+
+/** \brief  Disable Distributor
+
+   Disables the forwarding of pending interrupts to the CPU interfaces.
+
+ */
+void GIC_DisableDistributor(void);
+
+/** \brief  Provides information about the configuration of the GIC.
+   Provides information about the configuration of the GIC.
+   - whether the GIC implements the Security Extensions
+   - the maximum number of interrupt IDs that the GIC supports
+   - the number of CPU interfaces implemented
+   - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
+
+   \return Distributor Information.
+ */
+uint32_t GIC_DistributorInfo(void);
+
+/** \brief  Distributor Implementer Identification Register.
+
+   Distributor Implementer Identification Register
+
+   \return Implementer Information.
+ */
+uint32_t GIC_DistributorImplementer(void);
+
+/** \brief  Set list of processors that the interrupt is sent to if it is asserted.
+
+    The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
+    This field stores the list of processors that the interrupt is sent to if it is asserted.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]    target  CPU target
+ */
+void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
+
+/** \brief  Get list of processors that the interrupt is sent to if it is asserted.
+
+    The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
+    This field stores the list of processors that the interrupt is sent to if it is asserted.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]    target  CPU target
+*/
+uint32_t GIC_GetTarget(IRQn_Type IRQn);
+
+/** \brief  Enable Interface
+
+   Enables the signalling of interrupts to the target processors.
+
+ */
+void GIC_EnableInterface(void);
+
+/** \brief  Disable Interface
+
+   Disables the signalling of interrupts to the target processors.
+
+ */
+void GIC_DisableInterface(void);
+
+/** \brief  Acknowledge Interrupt
+
+    The function acknowledges the highest priority pending interrupt and returns its IRQ number.
+
+    \return             Interrupt number
+ */
+IRQn_Type GIC_AcknowledgePending(void);
+
+/** \brief  End Interrupt
+
+    The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
+
+    \param [in]   IRQn  Interrupt number.
+ */
+void GIC_EndInterrupt(IRQn_Type IRQn);
+
+
+/** \brief  Enable Interrupt
+
+    Set-enable bit for each interrupt supported by the GIC.
+
+    \param [in]      IRQn  External interrupt number.
+ */
+void GIC_EnableIRQ(IRQn_Type IRQn);
+
+/** \brief  Disable Interrupt
+
+    Clear-enable bit for each interrupt supported by the GIC.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+void GIC_DisableIRQ(IRQn_Type IRQn);
+
+/** \brief  Set Pending Interrupt
+
+    Set-pending bit for each interrupt supported by the GIC.
+
+    \param [in]      IRQn  Interrupt number.
+ */
+void GIC_SetPendingIRQ(IRQn_Type IRQn);
+
+/** \brief  Clear Pending Interrupt
+
+    Clear-pending bit for each interrupt supported by the GIC
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+void GIC_ClearPendingIRQ(IRQn_Type IRQn);
+
+/** \brief  Int_config field for each interrupt supported by the GIC.
+
+    This field identifies whether the corresponding interrupt is:
+    (1) edge-triggered or (0) level-sensitive
+    (1) 1-N model or (0) N-N model
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in] edge_level (1) edge-triggered or (0) level-sensitive
+    \param [in] model      (1) 1-N model or (0) N-N model
+ */
+void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt.
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority.
+ */
+uint32_t GIC_GetPriority(IRQn_Type IRQn);
+
+/** \brief  CPU Interface Priority Mask Register
+
+    The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
+    value indicated by this field, the interface signals the interrupt to the processor.
+
+    \param [in]   Mask.
+ */
+void GIC_InterfacePriorityMask(uint32_t priority);
+
+/** \brief  Set the binary point.
+
+     Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
+
+    \param [in]   Mask.
+ */
+void GIC_SetBinaryPoint(uint32_t binary_point);
+
+/** \brief  Get the binary point.
+
+     Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
+
+    \return  Binary point.
+ */
+uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
+
+/** \brief  Get Interrupt state.
+
+     Get the interrupt state, whether pending and/or active
+
+    \return  0 - inactive, 1 - pending, 2 - active, 3 - pending and active
+ */
+uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
+
+/** \brief  Send Software Generated interrupt
+
+    Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
+GIC_InterfacePriorityMask
+    \param [in]   IRQn         The Interrupt ID of the SGI.
+    \param [in]   target_list  CPUTargetList
+    \param [in]   filter_list  TargetListFilter
+ */
+void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
+
+/** \brief  API call to initialise the interrupt distributor
+
+   API call to initialise the interrupt distributor
+
+ */
+void GIC_DistInit(void);
+
+/** \brief  API call to initialise the CPU interface
+
+   API call to initialise the CPU interface
+
+ */
+void GIC_CPUInterfaceInit(void);
+
+/** \brief  API call to set the Interrupt Configuration Registers
+
+   API call to initialise the Interrupt Configuration Registers
+
+ */
+void GIC_SetICDICFR (const uint32_t *ICDICFRn);
+
+/** \brief  API call to  Enable the GIC
+
+   API call to  Enable the GIC
+
+ */
+void GIC_Enable(void);
+
+#endif /* GIC_H_ */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/bsc_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,358 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : bsc_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : BSC register define header
+*******************************************************************************/
+#ifndef BSC_IOBITMASK_H
+#define BSC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define BSC_CMNCR_HIZCNT                (0x00000001uL)
+#define BSC_CMNCR_HIZMEM                (0x00000002uL)
+#define BSC_CMNCR_DPRTY                 (0x00000600uL)
+#define BSC_CMNCR_AL0                   (0x01000000uL)
+#define BSC_CMNCR_TL0                   (0x10000000uL)
+
+#define BSC_CS0BCR_BSZ                  (0x00000600uL)
+#define BSC_CS0BCR_TYPE                 (0x00007000uL)
+#define BSC_CS0BCR_IWRRS                (0x00070000uL)
+#define BSC_CS0BCR_IWRRD                (0x00380000uL)
+#define BSC_CS0BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS0BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS0BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS1BCR_BSZ                  (0x00000600uL)
+#define BSC_CS1BCR_TYPE                 (0x00007000uL)
+#define BSC_CS1BCR_IWRRS                (0x00070000uL)
+#define BSC_CS1BCR_IWRRD                (0x00380000uL)
+#define BSC_CS1BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS1BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS1BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS2BCR_BSZ                  (0x00000600uL)
+#define BSC_CS2BCR_TYPE                 (0x00007000uL)
+#define BSC_CS2BCR_IWRRS                (0x00070000uL)
+#define BSC_CS2BCR_IWRRD                (0x00380000uL)
+#define BSC_CS2BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS2BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS2BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS3BCR_BSZ                  (0x00000600uL)
+#define BSC_CS3BCR_TYPE                 (0x00007000uL)
+#define BSC_CS3BCR_IWRRS                (0x00070000uL)
+#define BSC_CS3BCR_IWRRD                (0x00380000uL)
+#define BSC_CS3BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS3BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS3BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS4BCR_BSZ                  (0x00000600uL)
+#define BSC_CS4BCR_TYPE                 (0x00007000uL)
+#define BSC_CS4BCR_IWRRS                (0x00070000uL)
+#define BSC_CS4BCR_IWRRD                (0x00380000uL)
+#define BSC_CS4BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS4BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS4BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS5BCR_BSZ                  (0x00000600uL)
+#define BSC_CS5BCR_TYPE                 (0x00007000uL)
+#define BSC_CS5BCR_IWRRS                (0x00070000uL)
+#define BSC_CS5BCR_IWRRD                (0x00380000uL)
+#define BSC_CS5BCR_IWRWS                (0x01C00000uL)
+#define BSC_CS5BCR_IWRWD                (0x0E000000uL)
+#define BSC_CS5BCR_IWW                  (0x70000000uL)
+
+#define BSC_CS0WCR_NORMAL_HW            (0x00000003uL)
+#define BSC_CS0WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS0WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS0WCR_NORMAL_SW            (0x00001800uL)
+#define BSC_CS0WCR_NORMAL_BAS           (0x00100000uL)
+
+#define BSC_CS1WCR_NORMAL_HW            (0x00000003uL)
+#define BSC_CS1WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS1WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS1WCR_NORMAL_SW            (0x00001800uL)
+#define BSC_CS1WCR_NORMAL_WW            (0x00070000uL)
+#define BSC_CS1WCR_NORMAL_BAS           (0x00100000uL)
+
+#define BSC_CS2WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS2WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS2WCR_NORMAL_BAS           (0x00100000uL)
+
+#define BSC_CS3WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS3WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS3WCR_NORMAL_BAS           (0x00100000uL)
+
+#define BSC_CS4WCR_NORMAL_HW            (0x00000003uL)
+#define BSC_CS4WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS4WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS4WCR_NORMAL_SW            (0x00001800uL)
+#define BSC_CS4WCR_NORMAL_WW            (0x00070000uL)
+#define BSC_CS4WCR_NORMAL_BAS           (0x00100000uL)
+
+#define BSC_CS5WCR_NORMAL_HW            (0x00000003uL)
+#define BSC_CS5WCR_NORMAL_WM            (0x00000040uL)
+#define BSC_CS5WCR_NORMAL_WR            (0x00000780uL)
+#define BSC_CS5WCR_NORMAL_SW            (0x00001800uL)
+#define BSC_CS5WCR_NORMAL_WW            (0x00070000uL)
+#define BSC_CS5WCR_NORMAL_MPXWBAS       (0x00100000uL)
+#define BSC_CS5WCR_NORMAL_SZSEL         (0x00200000uL)
+
+#define BSC_CS0WCR_BROM_ASY_WM          (0x00000040uL)
+#define BSC_CS0WCR_BROM_ASY_W           (0x00000780uL)
+#define BSC_CS0WCR_BROM_ASY_BW          (0x00030000uL)
+#define BSC_CS0WCR_BROM_ASY_BST         (0x00300000uL)
+
+#define BSC_CS4WCR_BROM_ASY_HW          (0x00000003uL)
+#define BSC_CS4WCR_BROM_ASY_WM          (0x00000040uL)
+#define BSC_CS4WCR_BROM_ASY_W           (0x00000780uL)
+#define BSC_CS4WCR_BROM_ASY_SW          (0x00001800uL)
+#define BSC_CS4WCR_BROM_ASY_BW          (0x00030000uL)
+#define BSC_CS4WCR_BROM_ASY_BST         (0x00300000uL)
+
+#define BSC_CS2WCR_SDRAM_A2CL           (0x00000180uL)
+
+#define BSC_CS3WCR_SDRAM_WTRC           (0x00000003uL)
+#define BSC_CS3WCR_SDRAM_TRWL           (0x00000018uL)
+#define BSC_CS3WCR_SDRAM_A3CL           (0x00000180uL)
+#define BSC_CS3WCR_SDRAM_WTRCD          (0x00000C00uL)
+#define BSC_CS3WCR_SDRAM_WTRP           (0x00006000uL)
+
+#define BSC_CS0WCR_BROM_SY_WM           (0x00000040uL)
+#define BSC_CS0WCR_BROM_SY_W            (0x00000780uL)
+#define BSC_CS0WCR_BROM_SY_BW           (0x00030000uL)
+
+#define BSC_SDCR_A3COL                  (0x00000003uL)
+#define BSC_SDCR_A3ROW                  (0x00000018uL)
+#define BSC_SDCR_BACTV                  (0x00000100uL)
+#define BSC_SDCR_PDOWN                  (0x00000200uL)
+#define BSC_SDCR_RMODE                  (0x00000400uL)
+#define BSC_SDCR_RFSH                   (0x00000800uL)
+#define BSC_SDCR_DEEP                   (0x00002000uL)
+#define BSC_SDCR_A2COL                  (0x00030000uL)
+#define BSC_SDCR_A2ROW                  (0x00180000uL)
+
+#define BSC_RTCSR_RRC                   (0x00000007uL)
+#define BSC_RTCSR_CKS                   (0x00000038uL)
+#define BSC_RTCSR_CMIE                  (0x00000040uL)
+#define BSC_RTCSR_CMF                   (0x00000080uL)
+
+#define BSC_RTCNT_D                     (0xFFFFFFFFuL)
+
+#define BSC_RTCOR_D                     (0xFFFFFFFFuL)
+
+#define BSC_TOSCOR0_D                   (0x0000FFFFuL)
+
+#define BSC_TOSCOR1_D                   (0x0000FFFFuL)
+
+#define BSC_TOSCOR2_D                   (0x0000FFFFuL)
+
+#define BSC_TOSCOR3_D                   (0x0000FFFFuL)
+
+#define BSC_TOSCOR4_D                   (0x0000FFFFuL)
+
+#define BSC_TOSCOR5_D                   (0x0000FFFFuL)
+
+#define BSC_TOSTR_CS0TOSTF              (0x00000001uL)
+#define BSC_TOSTR_CS1TOSTF              (0x00000002uL)
+#define BSC_TOSTR_CS2TOSTF              (0x00000004uL)
+#define BSC_TOSTR_CS3TOSTF              (0x00000008uL)
+#define BSC_TOSTR_CS4TOSTF              (0x00000010uL)
+#define BSC_TOSTR_CS5TOSTF              (0x00000020uL)
+
+#define BSC_TOENR_CS0TOEN               (0x00000001uL)
+#define BSC_TOENR_CS1TOEN               (0x00000002uL)
+#define BSC_TOENR_CS2TOEN               (0x00000004uL)
+#define BSC_TOENR_CS3TOEN               (0x00000008uL)
+#define BSC_TOENR_CS4TOEN               (0x00000010uL)
+#define BSC_TOENR_CS5TOEN               (0x00000020uL)
+
+
+/* ==== Shift values for IO registers ==== */
+#define BSC_CMNCR_HIZCNT_SHIFT          (0u)
+#define BSC_CMNCR_HIZMEM_SHIFT          (1u)
+#define BSC_CMNCR_DPRTY_SHIFT           (9u)
+#define BSC_CMNCR_AL0_SHIFT             (24u)
+#define BSC_CMNCR_TL0_SHIFT             (28u)
+
+#define BSC_CS0BCR_BSZ_SHIFT            (9u)
+#define BSC_CS0BCR_TYPE_SHIFT           (12u)
+#define BSC_CS0BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS0BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS0BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS0BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS0BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS1BCR_BSZ_SHIFT            (9u)
+#define BSC_CS1BCR_TYPE_SHIFT           (12u)
+#define BSC_CS1BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS1BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS1BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS1BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS1BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS2BCR_BSZ_SHIFT            (9u)
+#define BSC_CS2BCR_TYPE_SHIFT           (12u)
+#define BSC_CS2BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS2BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS2BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS2BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS2BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS3BCR_BSZ_SHIFT            (9u)
+#define BSC_CS3BCR_TYPE_SHIFT           (12u)
+#define BSC_CS3BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS3BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS3BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS3BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS3BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS4BCR_BSZ_SHIFT            (9u)
+#define BSC_CS4BCR_TYPE_SHIFT           (12u)
+#define BSC_CS4BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS4BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS4BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS4BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS4BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS5BCR_BSZ_SHIFT            (9u)
+#define BSC_CS5BCR_TYPE_SHIFT           (12u)
+#define BSC_CS5BCR_IWRRS_SHIFT          (16u)
+#define BSC_CS5BCR_IWRRD_SHIFT          (19u)
+#define BSC_CS5BCR_IWRWS_SHIFT          (22u)
+#define BSC_CS5BCR_IWRWD_SHIFT          (25u)
+#define BSC_CS5BCR_IWW_SHIFT            (28u)
+
+#define BSC_CS0WCR_NORMAL_HW_SHIFT      (0u)
+#define BSC_CS0WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS0WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS0WCR_NORMAL_SW_SHIFT      (11u)
+#define BSC_CS0WCR_NORMAL_BAS_SHIFT     (20u)
+
+#define BSC_CS1WCR_NORMAL_HW_SHIFT      (0u)
+#define BSC_CS1WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS1WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS1WCR_NORMAL_SW_SHIFT      (11u)
+#define BSC_CS1WCR_NORMAL_WW_SHIFT      (16u)
+#define BSC_CS1WCR_NORMAL_BAS_SHIFT     (20u)
+
+#define BSC_CS2WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS2WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS2WCR_NORMAL_BAS_SHIFT     (20u)
+
+#define BSC_CS3WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS3WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS3WCR_NORMAL_BAS_SHIFT     (20u)
+
+#define BSC_CS4WCR_NORMAL_HW_SHIFT      (0u)
+#define BSC_CS4WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS4WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS4WCR_NORMAL_SW_SHIFT      (11u)
+#define BSC_CS4WCR_NORMAL_WW_SHIFT      (16u)
+#define BSC_CS4WCR_NORMAL_BAS_SHIFT     (20u)
+
+#define BSC_CS5WCR_NORMAL_HW_SHIFT      (0u)
+#define BSC_CS5WCR_NORMAL_WM_SHIFT      (6u)
+#define BSC_CS5WCR_NORMAL_WR_SHIFT      (7u)
+#define BSC_CS5WCR_NORMAL_SW_SHIFT      (11u)
+#define BSC_CS5WCR_NORMAL_WW_SHIFT      (16u)
+#define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u)
+#define BSC_CS5WCR_NORMAL_SZSEL_SHIFT   (21u)
+
+#define BSC_CS0WCR_BROM_ASY_WM_SHIFT    (6u)
+#define BSC_CS0WCR_BROM_ASY_W_SHIFT     (7u)
+#define BSC_CS0WCR_BROM_ASY_BW_SHIFT    (16u)
+#define BSC_CS0WCR_BROM_ASY_BST_SHIFT   (20u)
+
+#define BSC_CS4WCR_BROM_ASY_HW_SHIFT    (0u)
+#define BSC_CS4WCR_BROM_ASY_WM_SHIFT    (6u)
+#define BSC_CS4WCR_BROM_ASY_W_SHIFT     (7u)
+#define BSC_CS4WCR_BROM_ASY_SW_SHIFT    (11u)
+#define BSC_CS4WCR_BROM_ASY_BW_SHIFT    (16u)
+#define BSC_CS4WCR_BROM_ASY_BST_SHIFT   (20u)
+
+#define BSC_CS2WCR_SDRAM_A2CL_SHIFT     (7u)
+
+#define BSC_CS3WCR_SDRAM_WTRC_SHIFT     (0u)
+#define BSC_CS3WCR_SDRAM_TRWL_SHIFT     (3u)
+#define BSC_CS3WCR_SDRAM_A3CL_SHIFT     (7u)
+#define BSC_CS3WCR_SDRAM_WTRCD_SHIFT    (10u)
+#define BSC_CS3WCR_SDRAM_WTRP_SHIFT     (13u)
+
+#define BSC_CS0WCR_BROM_SY_WM_SHIFT     (6u)
+#define BSC_CS0WCR_BROM_SY_W_SHIFT      (7u)
+#define BSC_CS0WCR_BROM_SY_BW_SHIFT     (16u)
+
+#define BSC_SDCR_A3COL_SHIFT            (0u)
+#define BSC_SDCR_A3ROW_SHIFT            (3u)
+#define BSC_SDCR_BACTV_SHIFT            (8u)
+#define BSC_SDCR_PDOWN_SHIFT            (9u)
+#define BSC_SDCR_RMODE_SHIFT            (10u)
+#define BSC_SDCR_RFSH_SHIFT             (11u)
+#define BSC_SDCR_DEEP_SHIFT             (13u)
+#define BSC_SDCR_A2COL_SHIFT            (16u)
+#define BSC_SDCR_A2ROW_SHIFT            (19u)
+
+#define BSC_RTCSR_RRC_SHIFT             (0u)
+#define BSC_RTCSR_CKS_SHIFT             (3u)
+#define BSC_RTCSR_CMIE_SHIFT            (6u)
+#define BSC_RTCSR_CMF_SHIFT             (7u)
+
+#define BSC_RTCNT_D_SHIFT               (0u)
+
+#define BSC_RTCOR_D_SHIFT               (0u)
+
+#define BSC_TOSCOR0_D_SHIFT             (0u)
+
+#define BSC_TOSCOR1_D_SHIFT             (0u)
+
+#define BSC_TOSCOR2_D_SHIFT             (0u)
+
+#define BSC_TOSCOR3_D_SHIFT             (0u)
+
+#define BSC_TOSCOR4_D_SHIFT             (0u)
+
+#define BSC_TOSCOR5_D_SHIFT             (0u)
+
+#define BSC_TOSTR_CS0TOSTF_SHIFT        (0u)
+#define BSC_TOSTR_CS1TOSTF_SHIFT        (1u)
+#define BSC_TOSTR_CS2TOSTF_SHIFT        (2u)
+#define BSC_TOSTR_CS3TOSTF_SHIFT        (3u)
+#define BSC_TOSTR_CS4TOSTF_SHIFT        (4u)
+#define BSC_TOSTR_CS5TOSTF_SHIFT        (5u)
+
+#define BSC_TOENR_CS0TOEN_SHIFT         (0u)
+#define BSC_TOENR_CS1TOEN_SHIFT         (1u)
+#define BSC_TOENR_CS2TOEN_SHIFT         (2u)
+#define BSC_TOENR_CS3TOEN_SHIFT         (3u)
+#define BSC_TOENR_CS4TOEN_SHIFT         (4u)
+#define BSC_TOENR_CS5TOEN_SHIFT         (5u)
+
+
+#endif /* BSC_IOBITMASK_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/cpg_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,462 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : cpg_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : CPG register define header
+*******************************************************************************/
+#ifndef CPG_IOBITMASK_H
+#define CPG_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define CPG_FRQCR_IFC                   (0x0300u)
+#define CPG_FRQCR_CKOEN                 (0x3000u)
+#define CPG_FRQCR_CKOEN2                (0x4000u)
+
+#define CPG_FRQCR2_GFC                  (0x0003u)
+
+#define CPG_CPUSTS_ISBUSY               (0x10u)
+
+#define CPG_STBCR1_DEEP                 (0x40u)
+#define CPG_STBCR1_STBY                 (0x80u)
+
+#define CPG_STBCR2_MSTP20               (0x01u)
+#define CPG_STBCR2_HIZ                  (0x80u)
+
+#define CPG_STBREQ1_STBRQ10             (0x01u)
+#define CPG_STBREQ1_STBRQ12             (0x04u)
+#define CPG_STBREQ1_STBRQ13             (0x08u)
+#define CPG_STBREQ1_STBRQ15             (0x20u)
+
+#define CPG_STBREQ2_STBRQ20             (0x01u)
+#define CPG_STBREQ2_STBRQ21             (0x02u)
+#define CPG_STBREQ2_STBRQ22             (0x04u)
+#define CPG_STBREQ2_STBRQ23             (0x08u)
+#define CPG_STBREQ2_STBRQ24             (0x10u)
+#define CPG_STBREQ2_STBRQ25             (0x20u)
+#define CPG_STBREQ2_STBRQ26             (0x40u)
+#define CPG_STBREQ2_STBRQ27             (0x80u)
+
+#define CPG_STBACK1_STBAK10             (0x01u)
+#define CPG_STBACK1_STBAK12             (0x04u)
+#define CPG_STBACK1_STBAK13             (0x08u)
+#define CPG_STBACK1_STBAK15             (0x20u)
+
+#define CPG_STBACK2_STBAK20             (0x01u)
+#define CPG_STBACK2_STBAK21             (0x02u)
+#define CPG_STBACK2_STBAK22             (0x04u)
+#define CPG_STBACK2_STBAK23             (0x08u)
+#define CPG_STBACK2_STBAK24             (0x10u)
+#define CPG_STBACK2_STBAK25             (0x20u)
+#define CPG_STBACK2_STBAK26             (0x40u)
+#define CPG_STBACK2_STBAK27             (0x80u)
+
+#define CPG_SYSCR1_VRAME0               (0x01u)
+#define CPG_SYSCR1_VRAME1               (0x02u)
+#define CPG_SYSCR1_VRAME2               (0x04u)
+#define CPG_SYSCR1_VRAME3               (0x08u)
+#define CPG_SYSCR1_VRAME4               (0x10u)
+
+#define CPG_SYSCR2_VRAMWE0              (0x01u)
+#define CPG_SYSCR2_VRAMWE1              (0x02u)
+#define CPG_SYSCR2_VRAMWE2              (0x04u)
+#define CPG_SYSCR2_VRAMWE3              (0x08u)
+#define CPG_SYSCR2_VRAMWE4              (0x10u)
+
+#define CPG_SYSCR3_RRAMWE0              (0x01u)
+#define CPG_SYSCR3_RRAMWE1              (0x02u)
+#define CPG_SYSCR3_RRAMWE2              (0x04u)
+#define CPG_SYSCR3_RRAMWE3              (0x08u)
+
+#define CPG_STBCR3_MSTP30               (0x01u)
+#define CPG_STBCR3_MSTP31               (0x02u)
+#define CPG_STBCR3_MSTP32               (0x04u)
+#define CPG_STBCR3_MSTP33               (0x08u)
+#define CPG_STBCR3_MSTP34               (0x10u)
+#define CPG_STBCR3_MSTP35               (0x20u)
+#define CPG_STBCR3_MSTP36               (0x40u)
+#define CPG_STBCR3_MSTP37               (0x80u)
+
+#define CPG_STBCR4_MSTP40               (0x01u)
+#define CPG_STBCR4_MSTP41               (0x02u)
+#define CPG_STBCR4_MSTP42               (0x04u)
+#define CPG_STBCR4_MSTP43               (0x08u)
+#define CPG_STBCR4_MSTP44               (0x10u)
+#define CPG_STBCR4_MSTP45               (0x20u)
+#define CPG_STBCR4_MSTP46               (0x40u)
+#define CPG_STBCR4_MSTP47               (0x80u)
+
+#define CPG_STBCR5_MSTP50               (0x01u)
+#define CPG_STBCR5_MSTP51               (0x02u)
+#define CPG_STBCR5_MSTP52               (0x04u)
+#define CPG_STBCR5_MSTP53               (0x08u)
+#define CPG_STBCR5_MSTP54               (0x10u)
+#define CPG_STBCR5_MSTP55               (0x20u)
+#define CPG_STBCR5_MSTP56               (0x40u)
+#define CPG_STBCR5_MSTP57               (0x80u)
+
+#define CPG_STBCR6_MSTP60               (0x01u)
+#define CPG_STBCR6_MSTP61               (0x02u)
+#define CPG_STBCR6_MSTP62               (0x04u)
+#define CPG_STBCR6_MSTP63               (0x08u)
+#define CPG_STBCR6_MSTP64               (0x10u)
+#define CPG_STBCR6_MSTP65               (0x20u)
+#define CPG_STBCR6_MSTP66               (0x40u)
+#define CPG_STBCR6_MSTP67               (0x80u)
+
+#define CPG_STBCR7_MSTP70               (0x01u)
+#define CPG_STBCR7_MSTP71               (0x02u)
+#define CPG_STBCR7_MSTP73               (0x08u)
+#define CPG_STBCR7_MSTP74               (0x10u)
+#define CPG_STBCR7_MSTP76               (0x40u)
+#define CPG_STBCR7_MSTP77               (0x80u)
+
+#define CPG_STBCR8_MSTP81               (0x02u)
+#define CPG_STBCR8_MSTP82               (0x04u)
+#define CPG_STBCR8_MSTP83               (0x08u)
+#define CPG_STBCR8_MSTP84               (0x10u)
+#define CPG_STBCR8_MSTP85               (0x20u)
+#define CPG_STBCR8_MSTP86               (0x40u)
+#define CPG_STBCR8_MSTP87               (0x80u)
+
+#define CPG_STBCR9_MSTP90               (0x01u)
+#define CPG_STBCR9_MSTP91               (0x02u)
+#define CPG_STBCR9_MSTP92               (0x04u)
+#define CPG_STBCR9_MSTP93               (0x08u)
+#define CPG_STBCR9_MSTP94               (0x10u)
+#define CPG_STBCR9_MSTP95               (0x20u)
+#define CPG_STBCR9_MSTP96               (0x40u)
+#define CPG_STBCR9_MSTP97               (0x80u)
+
+#define CPG_STBCR10_MSTP100             (0x01u)
+#define CPG_STBCR10_MSTP101             (0x02u)
+#define CPG_STBCR10_MSTP102             (0x04u)
+#define CPG_STBCR10_MSTP103             (0x08u)
+#define CPG_STBCR10_MSTP104             (0x10u)
+#define CPG_STBCR10_MSTP105             (0x20u)
+#define CPG_STBCR10_MSTP106             (0x40u)
+#define CPG_STBCR10_MSTP107             (0x80u)
+
+#define CPG_STBCR11_MSTP110             (0x01u)
+#define CPG_STBCR11_MSTP111             (0x02u)
+#define CPG_STBCR11_MSTP112             (0x04u)
+#define CPG_STBCR11_MSTP113             (0x08u)
+#define CPG_STBCR11_MSTP114             (0x10u)
+#define CPG_STBCR11_MSTP115             (0x20u)
+
+#define CPG_STBCR12_MSTP120             (0x01u)
+#define CPG_STBCR12_MSTP121             (0x02u)
+#define CPG_STBCR12_MSTP122             (0x04u)
+#define CPG_STBCR12_MSTP123             (0x08u)
+
+#define CPG_STBCR13_MSTP131             (0x02u)
+#define CPG_STBCR13_MSTP132             (0x04u)
+
+#define CPG_SWRSTCR1_SRST11             (0x02u)
+#define CPG_SWRSTCR1_SRST12             (0x04u)
+#define CPG_SWRSTCR1_SRST13             (0x08u)
+#define CPG_SWRSTCR1_SRST14             (0x10u)
+#define CPG_SWRSTCR1_SRST15             (0x20u)
+#define CPG_SWRSTCR1_SRST16             (0x40u)
+#define CPG_SWRSTCR1_AXTALE             (0x80u)
+
+#define CPG_SWRSTCR2_SRST21             (0x02u)
+
+#define CPG_SWRSTCR3_SRST32             (0x04u)
+
+#define CPG_RRAMKP_RRAMKP0              (0x01u)
+#define CPG_RRAMKP_RRAMKP1              (0x02u)
+#define CPG_RRAMKP_RRAMKP2              (0x04u)
+#define CPG_RRAMKP_RRAMKP3              (0x08u)
+
+#define CPG_DSCTR_RAMBOOT               (0x40u)
+#define CPG_DSCTR_EBUSKEEPE             (0x80u)
+
+#define CPG_DSSSR_P8_2                  (0x0001u)
+#define CPG_DSSSR_P9_1                  (0x0002u)
+#define CPG_DSSSR_P2_15                 (0x0004u)
+#define CPG_DSSSR_P7_8                  (0x0008u)
+#define CPG_DSSSR_P5_9                  (0x0010u)
+#define CPG_DSSSR_P6_4                  (0x0020u)
+#define CPG_DSSSR_RTCAR                 (0x0040u)
+#define CPG_DSSSR_NMI                   (0x0100u)
+#define CPG_DSSSR_P3_3                  (0x0200u)
+#define CPG_DSSSR_P8_7                  (0x0400u)
+#define CPG_DSSSR_P2_12                 (0x0800u)
+#define CPG_DSSSR_P3_1                  (0x1000u)
+#define CPG_DSSSR_P3_9                  (0x2000u)
+#define CPG_DSSSR_P6_2                  (0x4000u)
+
+#define CPG_DSESR_P8_2E                 (0x0001u)
+#define CPG_DSESR_P9_1E                 (0x0002u)
+#define CPG_DSESR_P2_15E                (0x0004u)
+#define CPG_DSESR_P7_8E                 (0x0008u)
+#define CPG_DSESR_P5_9E                 (0x0010u)
+#define CPG_DSESR_P6_4E                 (0x0020u)
+#define CPG_DSESR_NMIE                  (0x0100u)
+#define CPG_DSESR_P3_3E                 (0x0200u)
+#define CPG_DSESR_P8_7E                 (0x0400u)
+#define CPG_DSESR_P2_12E                (0x0800u)
+#define CPG_DSESR_P3_1E                 (0x1000u)
+#define CPG_DSESR_P3_9E                 (0x2000u)
+#define CPG_DSESR_P6_2E                 (0x4000u)
+
+#define CPG_DSFR_P8_2F                  (0x0001u)
+#define CPG_DSFR_P9_1F                  (0x0002u)
+#define CPG_DSFR_P2_15F                 (0x0004u)
+#define CPG_DSFR_P7_8F                  (0x0008u)
+#define CPG_DSFR_P5_9F                  (0x0010u)
+#define CPG_DSFR_P6_4F                  (0x0020u)
+#define CPG_DSFR_RTCARF                 (0x0040u)
+#define CPG_DSFR_NMIF                   (0x0100u)
+#define CPG_DSFR_P3_3F                  (0x0200u)
+#define CPG_DSFR_P8_7F                  (0x0400u)
+#define CPG_DSFR_P2_12F                 (0x0800u)
+#define CPG_DSFR_P3_1F                  (0x1000u)
+#define CPG_DSFR_P3_9F                  (0x2000u)
+#define CPG_DSFR_P6_2F                  (0x4000u)
+#define CPG_DSFR_IOKEEP                 (0x8000u)
+
+#define CPG_XTALCTR_GAIN0               (0x01u)
+#define CPG_XTALCTR_GAIN1               (0x02u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define CPG_FRQCR_IFC_SHIFT             (8u)
+#define CPG_FRQCR_CKOEN_SHIFT           (12u)
+#define CPG_FRQCR_CKOEN2_SHIFT          (14u)
+
+#define CPG_FRQCR2_GFC_SHIFT            (0u)
+
+#define CPG_CPUSTS_ISBUSY_SHIFT         (4u)
+
+#define CPG_STBCR1_DEEP_SHIFT           (6u)
+#define CPG_STBCR1_STBY_SHIFT           (7u)
+
+#define CPG_STBCR2_MSTP20_SHIFT         (0u)
+#define CPG_STBCR2_HIZ_SHIFT            (7u)
+
+#define CPG_STBREQ1_STBRQ10_SHIFT       (0u)
+#define CPG_STBREQ1_STBRQ12_SHIFT       (2u)
+#define CPG_STBREQ1_STBRQ13_SHIFT       (3u)
+#define CPG_STBREQ1_STBRQ15_SHIFT       (5u)
+
+#define CPG_STBREQ2_STBRQ20_SHIFT       (0u)
+#define CPG_STBREQ2_STBRQ21_SHIFT       (1u)
+#define CPG_STBREQ2_STBRQ22_SHIFT       (2u)
+#define CPG_STBREQ2_STBRQ23_SHIFT       (3u)
+#define CPG_STBREQ2_STBRQ24_SHIFT       (4u)
+#define CPG_STBREQ2_STBRQ25_SHIFT       (5u)
+#define CPG_STBREQ2_STBRQ26_SHIFT       (6u)
+#define CPG_STBREQ2_STBRQ27_SHIFT       (7u)
+
+#define CPG_STBACK1_STBAK10_SHIFT       (0u)
+#define CPG_STBACK1_STBAK12_SHIFT       (2u)
+#define CPG_STBACK1_STBAK13_SHIFT       (3u)
+#define CPG_STBACK1_STBAK15_SHIFT       (5u)
+
+#define CPG_STBACK2_STBAK20_SHIFT       (0u)
+#define CPG_STBACK2_STBAK21_SHIFT       (1u)
+#define CPG_STBACK2_STBAK22_SHIFT       (2u)
+#define CPG_STBACK2_STBAK23_SHIFT       (3u)
+#define CPG_STBACK2_STBAK24_SHIFT       (4u)
+#define CPG_STBACK2_STBAK25_SHIFT       (5u)
+#define CPG_STBACK2_STBAK26_SHIFT       (6u)
+#define CPG_STBACK2_STBAK27_SHIFT       (7u)
+
+#define CPG_SYSCR1_VRAME0_SHIFT         (0u)
+#define CPG_SYSCR1_VRAME1_SHIFT         (1u)
+#define CPG_SYSCR1_VRAME2_SHIFT         (2u)
+#define CPG_SYSCR1_VRAME3_SHIFT         (3u)
+#define CPG_SYSCR1_VRAME4_SHIFT         (4u)
+
+#define CPG_SYSCR2_VRAMWE0_SHIFT        (0u)
+#define CPG_SYSCR2_VRAMWE1_SHIFT        (1u)
+#define CPG_SYSCR2_VRAMWE2_SHIFT        (2u)
+#define CPG_SYSCR2_VRAMWE3_SHIFT        (3u)
+#define CPG_SYSCR2_VRAMWE4_SHIFT        (4u)
+
+#define CPG_SYSCR3_RRAMWE0_SHIFT        (0u)
+#define CPG_SYSCR3_RRAMWE1_SHIFT        (1u)
+#define CPG_SYSCR3_RRAMWE2_SHIFT        (2u)
+#define CPG_SYSCR3_RRAMWE3_SHIFT        (3u)
+
+#define CPG_STBCR3_MSTP30_SHIFT         (0u)
+#define CPG_STBCR3_MSTP31_SHIFT         (1u)
+#define CPG_STBCR3_MSTP32_SHIFT         (2u)
+#define CPG_STBCR3_MSTP33_SHIFT         (3u)
+#define CPG_STBCR3_MSTP34_SHIFT         (4u)
+#define CPG_STBCR3_MSTP35_SHIFT         (5u)
+#define CPG_STBCR3_MSTP36_SHIFT         (6u)
+#define CPG_STBCR3_MSTP37_SHIFT         (7u)
+
+#define CPG_STBCR4_MSTP40_SHIFT         (0u)
+#define CPG_STBCR4_MSTP41_SHIFT         (1u)
+#define CPG_STBCR4_MSTP42_SHIFT         (2u)
+#define CPG_STBCR4_MSTP43_SHIFT         (3u)
+#define CPG_STBCR4_MSTP44_SHIFT         (4u)
+#define CPG_STBCR4_MSTP45_SHIFT         (5u)
+#define CPG_STBCR4_MSTP46_SHIFT         (6u)
+#define CPG_STBCR4_MSTP47_SHIFT         (7u)
+
+#define CPG_STBCR5_MSTP50_SHIFT         (0u)
+#define CPG_STBCR5_MSTP51_SHIFT         (1u)
+#define CPG_STBCR5_MSTP52_SHIFT         (2u)
+#define CPG_STBCR5_MSTP53_SHIFT         (3u)
+#define CPG_STBCR5_MSTP54_SHIFT         (4u)
+#define CPG_STBCR5_MSTP55_SHIFT         (5u)
+#define CPG_STBCR5_MSTP56_SHIFT         (6u)
+#define CPG_STBCR5_MSTP57_SHIFT         (7u)
+
+#define CPG_STBCR6_MSTP60_SHIFT         (0u)
+#define CPG_STBCR6_MSTP61_SHIFT         (1u)
+#define CPG_STBCR6_MSTP62_SHIFT         (2u)
+#define CPG_STBCR6_MSTP63_SHIFT         (3u)
+#define CPG_STBCR6_MSTP64_SHIFT         (4u)
+#define CPG_STBCR6_MSTP65_SHIFT         (5u)
+#define CPG_STBCR6_MSTP66_SHIFT         (6u)
+#define CPG_STBCR6_MSTP67_SHIFT         (7u)
+
+#define CPG_STBCR7_MSTP70_SHIFT         (0u)
+#define CPG_STBCR7_MSTP71_SHIFT         (1u)
+#define CPG_STBCR7_MSTP73_SHIFT         (3u)
+#define CPG_STBCR7_MSTP74_SHIFT         (4u)
+#define CPG_STBCR7_MSTP76_SHIFT         (6u)
+#define CPG_STBCR7_MSTP77_SHIFT         (7u)
+
+#define CPG_STBCR8_MSTP81_SHIFT         (1u)
+#define CPG_STBCR8_MSTP82_SHIFT         (2u)
+#define CPG_STBCR8_MSTP83_SHIFT         (3u)
+#define CPG_STBCR8_MSTP84_SHIFT         (4u)
+#define CPG_STBCR8_MSTP85_SHIFT         (5u)
+#define CPG_STBCR8_MSTP86_SHIFT         (6u)
+#define CPG_STBCR8_MSTP87_SHIFT         (7u)
+
+#define CPG_STBCR9_MSTP90_SHIFT         (0u)
+#define CPG_STBCR9_MSTP91_SHIFT         (1u)
+#define CPG_STBCR9_MSTP92_SHIFT         (2u)
+#define CPG_STBCR9_MSTP93_SHIFT         (3u)
+#define CPG_STBCR9_MSTP94_SHIFT         (4u)
+#define CPG_STBCR9_MSTP95_SHIFT         (5u)
+#define CPG_STBCR9_MSTP96_SHIFT         (6u)
+#define CPG_STBCR9_MSTP97_SHIFT         (7u)
+
+#define CPG_STBCR10_MSTP100_SHIFT       (0u)
+#define CPG_STBCR10_MSTP101_SHIFT       (1u)
+#define CPG_STBCR10_MSTP102_SHIFT       (2u)
+#define CPG_STBCR10_MSTP103_SHIFT       (3u)
+#define CPG_STBCR10_MSTP104_SHIFT       (4u)
+#define CPG_STBCR10_MSTP105_SHIFT       (5u)
+#define CPG_STBCR10_MSTP106_SHIFT       (6u)
+#define CPG_STBCR10_MSTP107_SHIFT       (7u)
+
+#define CPG_STBCR11_MSTP110_SHIFT       (0u)
+#define CPG_STBCR11_MSTP111_SHIFT       (1u)
+#define CPG_STBCR11_MSTP112_SHIFT       (2u)
+#define CPG_STBCR11_MSTP113_SHIFT       (3u)
+#define CPG_STBCR11_MSTP114_SHIFT       (4u)
+#define CPG_STBCR11_MSTP115_SHIFT       (5u)
+
+#define CPG_STBCR12_MSTP120_SHIFT       (0u)
+#define CPG_STBCR12_MSTP121_SHIFT       (1u)
+#define CPG_STBCR12_MSTP122_SHIFT       (2u)
+#define CPG_STBCR12_MSTP123_SHIFT       (3u)
+
+#define CPG_STBCR13_MSTP131_SHIFT       (1u)
+#define CPG_STBCR13_MSTP132_SHIFT       (2u)
+
+#define CPG_SWRSTCR1_SRST11_SHIFT       (1u)
+#define CPG_SWRSTCR1_SRST12_SHIFT       (2u)
+#define CPG_SWRSTCR1_SRST13_SHIFT       (3u)
+#define CPG_SWRSTCR1_SRST14_SHIFT       (4u)
+#define CPG_SWRSTCR1_SRST15_SHIFT       (5u)
+#define CPG_SWRSTCR1_SRST16_SHIFT       (6u)
+#define CPG_SWRSTCR1_AXTALE_SHIFT       (7u)
+
+#define CPG_SWRSTCR2_SRST21_SHIFT       (1u)
+
+#define CPG_SWRSTCR3_SRST32_SHIFT       (2u)
+
+#define CPG_RRAMKP_RRAMKP0_SHIFT        (0u)
+#define CPG_RRAMKP_RRAMKP1_SHIFT        (1u)
+#define CPG_RRAMKP_RRAMKP2_SHIFT        (2u)
+#define CPG_RRAMKP_RRAMKP3_SHIFT        (3u)
+
+#define CPG_DSCTR_RAMBOOT_SHIFT         (6u)
+#define CPG_DSCTR_EBUSKEEPE_SHIFT       (7u)
+
+#define CPG_DSSSR_P8_2_SHIFT            (0u)
+#define CPG_DSSSR_P9_1_SHIFT            (1u)
+#define CPG_DSSSR_P2_15_SHIFT           (2u)
+#define CPG_DSSSR_P7_8_SHIFT            (3u)
+#define CPG_DSSSR_P5_9_SHIFT            (4u)
+#define CPG_DSSSR_P6_4_SHIFT            (5u)
+#define CPG_DSSSR_RTCAR_SHIFT           (6u)
+#define CPG_DSSSR_NMI_SHIFT             (8u)
+#define CPG_DSSSR_P3_3_SHIFT            (9u)
+#define CPG_DSSSR_P8_7_SHIFT            (10u)
+#define CPG_DSSSR_P2_12_SHIFT           (11u)
+#define CPG_DSSSR_P3_1_SHIFT            (12u)
+#define CPG_DSSSR_P3_9_SHIFT            (13u)
+#define CPG_DSSSR_P6_2_SHIFT            (14u)
+
+#define CPG_DSESR_P8_2E_SHIFT           (0u)
+#define CPG_DSESR_P9_1E_SHIFT           (1u)
+#define CPG_DSESR_P2_15E_SHIFT          (2u)
+#define CPG_DSESR_P7_8E_SHIFT           (3u)
+#define CPG_DSESR_P5_9E_SHIFT           (4u)
+#define CPG_DSESR_P6_4E_SHIFT           (5u)
+#define CPG_DSESR_NMIE_SHIFT            (8u)
+#define CPG_DSESR_P3_3E_SHIFT           (9u)
+#define CPG_DSESR_P8_7E_SHIFT           (10u)
+#define CPG_DSESR_P2_12E_SHIFT          (11u)
+#define CPG_DSESR_P3_1E_SHIFT           (12u)
+#define CPG_DSESR_P3_9E_SHIFT           (13u)
+#define CPG_DSESR_P6_2E_SHIFT           (14u)
+
+#define CPG_DSFR_P8_2F_SHIFT            (0u)
+#define CPG_DSFR_P9_1F_SHIFT            (1u)
+#define CPG_DSFR_P2_15F_SHIFT           (2u)
+#define CPG_DSFR_P7_8F_SHIFT            (3u)
+#define CPG_DSFR_P5_9F_SHIFT            (4u)
+#define CPG_DSFR_P6_4F_SHIFT            (5u)
+#define CPG_DSFR_RTCARF_SHIFT           (6u)
+#define CPG_DSFR_NMIF_SHIFT             (8u)
+#define CPG_DSFR_P3_3F_SHIFT            (9u)
+#define CPG_DSFR_P8_7F_SHIFT            (10u)
+#define CPG_DSFR_P2_12F_SHIFT           (11u)
+#define CPG_DSFR_P3_1F_SHIFT            (12u)
+#define CPG_DSFR_P3_9F_SHIFT            (13u)
+#define CPG_DSFR_P6_2F_SHIFT            (14u)
+#define CPG_DSFR_IOKEEP_SHIFT           (15u)
+
+#define CPG_XTALCTR_GAIN0_SHIFT         (0u)
+#define CPG_XTALCTR_GAIN1_SHIFT         (1u)
+
+
+#endif /* CPG_IOBITMASK_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/dmac_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,2676 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : dmac_iobitmask.h
+* $Rev: 1114 $
+* $Date:: 2014-07-09 14:56:39 +0900#$
+* Description : DMAC register define header
+*******************************************************************************/
+#ifndef DMAC_IOBITMASK_H
+#define DMAC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- DMAC0 ---- */
+#define DMAC0_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC0_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC0_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC0_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC0_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC0_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC0_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC0_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC0_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC0_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC0_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC0_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC0_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC0_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC0_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC0_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC0_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC0_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC0_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC0_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC0_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC0_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC0_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC0_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC0_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC0_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC0_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC0_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC0_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC0_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC0_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC0_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC0_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC0_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC0_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC0_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC0_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC0_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC0_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC0_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC0_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC0_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC0_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC0_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC0_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC0_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC0_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC0_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC0_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC0_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC0_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC0_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC0_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC0_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC0_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC0_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC1 ---- */
+#define DMAC1_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC1_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC1_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC1_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC1_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC1_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC1_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC1_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC1_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC1_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC1_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC1_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC1_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC1_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC1_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC1_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC1_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC1_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC1_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC1_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC1_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC1_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC1_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC1_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC1_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC1_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC1_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC1_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC1_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC1_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC1_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC1_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC1_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC1_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC1_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC1_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC1_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC1_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC1_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC1_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC1_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC1_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC1_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC1_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC1_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC1_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC1_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC1_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC1_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC1_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC1_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC1_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC1_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC1_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC1_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC1_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC2 ---- */
+#define DMAC2_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC2_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC2_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC2_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC2_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC2_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC2_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC2_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC2_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC2_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC2_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC2_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC2_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC2_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC2_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC2_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC2_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC2_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC2_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC2_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC2_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC2_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC2_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC2_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC2_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC2_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC2_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC2_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC2_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC2_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC2_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC2_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC2_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC2_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC2_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC2_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC2_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC2_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC2_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC2_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC2_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC2_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC2_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC2_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC2_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC2_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC2_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC2_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC2_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC2_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC2_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC2_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC2_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC2_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC2_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC2_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC3 ---- */
+#define DMAC3_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC3_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC3_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC3_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC3_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC3_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC3_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC3_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC3_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC3_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC3_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC3_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC3_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC3_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC3_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC3_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC3_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC3_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC3_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC3_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC3_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC3_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC3_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC3_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC3_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC3_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC3_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC3_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC3_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC3_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC3_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC3_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC3_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC3_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC3_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC3_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC3_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC3_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC3_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC3_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC3_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC3_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC3_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC3_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC3_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC3_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC3_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC3_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC3_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC3_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC3_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC3_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC3_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC3_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC3_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC3_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC4 ---- */
+#define DMAC4_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC4_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC4_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC4_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC4_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC4_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC4_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC4_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC4_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC4_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC4_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC4_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC4_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC4_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC4_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC4_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC4_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC4_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC4_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC4_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC4_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC4_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC4_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC4_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC4_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC4_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC4_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC4_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC4_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC4_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC4_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC4_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC4_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC4_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC4_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC4_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC4_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC4_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC4_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC4_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC4_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC4_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC4_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC4_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC4_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC4_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC4_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC4_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC4_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC4_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC4_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC4_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC4_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC4_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC4_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC4_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC5 ---- */
+#define DMAC5_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC5_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC5_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC5_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC5_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC5_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC5_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC5_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC5_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC5_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC5_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC5_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC5_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC5_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC5_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC5_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC5_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC5_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC5_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC5_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC5_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC5_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC5_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC5_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC5_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC5_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC5_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC5_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC5_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC5_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC5_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC5_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC5_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC5_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC5_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC5_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC5_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC5_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC5_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC5_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC5_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC5_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC5_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC5_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC5_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC5_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC5_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC5_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC5_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC5_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC5_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC5_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC5_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC5_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC5_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC5_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC6 ---- */
+#define DMAC6_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC6_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC6_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC6_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC6_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC6_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC6_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC6_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC6_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC6_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC6_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC6_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC6_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC6_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC6_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC6_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC6_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC6_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC6_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC6_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC6_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC6_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC6_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC6_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC6_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC6_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC6_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC6_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC6_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC6_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC6_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC6_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC6_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC6_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC6_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC6_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC6_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC6_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC6_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC6_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC6_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC6_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC6_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC6_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC6_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC6_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC6_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC6_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC6_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC6_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC6_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC6_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC6_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC6_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC6_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC6_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC7 ---- */
+#define DMAC7_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC7_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC7_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC7_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC7_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC7_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC7_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC7_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC7_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC7_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC7_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC7_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC7_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC7_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC7_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC7_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC7_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC7_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC7_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC7_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC7_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC7_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC7_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC7_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC7_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC7_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC7_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC7_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC7_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC7_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC7_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC7_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC7_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC7_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC7_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC7_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC7_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC7_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC7_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC7_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC7_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC7_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC7_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC7_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC7_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC7_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC7_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC7_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC7_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC7_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC7_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC7_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC7_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC7_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC7_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC7_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC0-7 ---- */
+#define DMAC07_DCTRL_0_7_PR                 (0x00000001uL)
+#define DMAC07_DCTRL_0_7_LVINT              (0x00000002uL)
+#define DMAC07_DCTRL_0_7_LDCA               (0x0000003CuL)
+#define DMAC07_DCTRL_0_7_LWCA               (0x000003C0uL)
+
+#define DMAC07_DSTAT_EN_0_7_EN0             (0x00000001uL)
+#define DMAC07_DSTAT_EN_0_7_EN1             (0x00000002uL)
+#define DMAC07_DSTAT_EN_0_7_EN2             (0x00000004uL)
+#define DMAC07_DSTAT_EN_0_7_EN3             (0x00000008uL)
+#define DMAC07_DSTAT_EN_0_7_EN4             (0x00000010uL)
+#define DMAC07_DSTAT_EN_0_7_EN5             (0x00000020uL)
+#define DMAC07_DSTAT_EN_0_7_EN6             (0x00000040uL)
+#define DMAC07_DSTAT_EN_0_7_EN7             (0x00000080uL)
+
+#define DMAC07_DSTAT_ER_0_7_ER0             (0x00000001uL)
+#define DMAC07_DSTAT_ER_0_7_ER1             (0x00000002uL)
+#define DMAC07_DSTAT_ER_0_7_ER2             (0x00000004uL)
+#define DMAC07_DSTAT_ER_0_7_ER3             (0x00000008uL)
+#define DMAC07_DSTAT_ER_0_7_ER4             (0x00000010uL)
+#define DMAC07_DSTAT_ER_0_7_ER5             (0x00000020uL)
+#define DMAC07_DSTAT_ER_0_7_ER6             (0x00000040uL)
+#define DMAC07_DSTAT_ER_0_7_ER7             (0x00000080uL)
+
+#define DMAC07_DSTAT_END_0_7_END0           (0x00000001uL)
+#define DMAC07_DSTAT_END_0_7_END1           (0x00000002uL)
+#define DMAC07_DSTAT_END_0_7_END2           (0x00000004uL)
+#define DMAC07_DSTAT_END_0_7_END3           (0x00000008uL)
+#define DMAC07_DSTAT_END_0_7_END4           (0x00000010uL)
+#define DMAC07_DSTAT_END_0_7_END5           (0x00000020uL)
+#define DMAC07_DSTAT_END_0_7_END6           (0x00000040uL)
+#define DMAC07_DSTAT_END_0_7_END7           (0x00000080uL)
+
+#define DMAC07_DSTAT_TC_0_7_TC0             (0x00000001uL)
+#define DMAC07_DSTAT_TC_0_7_TC1             (0x00000002uL)
+#define DMAC07_DSTAT_TC_0_7_TC2             (0x00000004uL)
+#define DMAC07_DSTAT_TC_0_7_TC3             (0x00000008uL)
+#define DMAC07_DSTAT_TC_0_7_TC4             (0x00000010uL)
+#define DMAC07_DSTAT_TC_0_7_TC5             (0x00000020uL)
+#define DMAC07_DSTAT_TC_0_7_TC6             (0x00000040uL)
+#define DMAC07_DSTAT_TC_0_7_TC7             (0x00000080uL)
+
+#define DMAC07_DSTAT_SUS_0_7_SUS0           (0x00000001uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS1           (0x00000002uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS2           (0x00000004uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS3           (0x00000008uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS4           (0x00000010uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS5           (0x00000020uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS6           (0x00000040uL)
+#define DMAC07_DSTAT_SUS_0_7_SUS7           (0x00000080uL)
+
+/* ---- DMAC8 ---- */
+#define DMAC8_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC8_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC8_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC8_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC8_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC8_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC8_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC8_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC8_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC8_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC8_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC8_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC8_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC8_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC8_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC8_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC8_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC8_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC8_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC8_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC8_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC8_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC8_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC8_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC8_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC8_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC8_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC8_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC8_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC8_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC8_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC8_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC8_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC8_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC8_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC8_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC8_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC8_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC8_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC8_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC8_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC8_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC8_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC8_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC8_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC8_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC8_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC8_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC8_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC8_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC8_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC8_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC8_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC8_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC8_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC8_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC9 ---- */
+#define DMAC9_N0SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC9_N0DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC9_N0TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC9_N1SA_n_SA                     (0xFFFFFFFFuL)
+
+#define DMAC9_N1DA_n_DA                     (0xFFFFFFFFuL)
+
+#define DMAC9_N1TB_n_TB                     (0xFFFFFFFFuL)
+
+#define DMAC9_CRSA_n_CRSA                   (0xFFFFFFFFuL)
+
+#define DMAC9_CRDA_n_CRDA                   (0xFFFFFFFFuL)
+
+#define DMAC9_CRTB_n_CRTB                   (0xFFFFFFFFuL)
+
+#define DMAC9_CHSTAT_n_EN                   (0x00000001uL)
+#define DMAC9_CHSTAT_n_RQST                 (0x00000002uL)
+#define DMAC9_CHSTAT_n_TACT                 (0x00000004uL)
+#define DMAC9_CHSTAT_n_SUS                  (0x00000008uL)
+#define DMAC9_CHSTAT_n_ER                   (0x00000010uL)
+#define DMAC9_CHSTAT_n_END                  (0x00000020uL)
+#define DMAC9_CHSTAT_n_TC                   (0x00000040uL)
+#define DMAC9_CHSTAT_n_SR                   (0x00000080uL)
+#define DMAC9_CHSTAT_n_DL                   (0x00000100uL)
+#define DMAC9_CHSTAT_n_DW                   (0x00000200uL)
+#define DMAC9_CHSTAT_n_DER                  (0x00000400uL)
+#define DMAC9_CHSTAT_n_MODE                 (0x00000800uL)
+#define DMAC9_CHSTAT_n_INTMSK               (0x00010000uL)
+
+#define DMAC9_CHCTRL_n_SETEN                (0x00000001uL)
+#define DMAC9_CHCTRL_n_CLREN                (0x00000002uL)
+#define DMAC9_CHCTRL_n_STG                  (0x00000004uL)
+#define DMAC9_CHCTRL_n_SWRST                (0x00000008uL)
+#define DMAC9_CHCTRL_n_CLRRQ                (0x00000010uL)
+#define DMAC9_CHCTRL_n_CLREND               (0x00000020uL)
+#define DMAC9_CHCTRL_n_CLRTC                (0x00000040uL)
+#define DMAC9_CHCTRL_n_SETSUS               (0x00000100uL)
+#define DMAC9_CHCTRL_n_CLRSUS               (0x00000200uL)
+#define DMAC9_CHCTRL_n_SETINTMSK            (0x00010000uL)
+#define DMAC9_CHCTRL_n_CLRINTMSK            (0x00020000uL)
+
+#define DMAC9_CHCFG_n_SEL                   (0x00000007uL)
+#define DMAC9_CHCFG_n_REQD                  (0x00000008uL)
+#define DMAC9_CHCFG_n_LOEN                  (0x00000010uL)
+#define DMAC9_CHCFG_n_HIEN                  (0x00000020uL)
+#define DMAC9_CHCFG_n_LVL                   (0x00000040uL)
+#define DMAC9_CHCFG_n_AM                    (0x00000700uL)
+#define DMAC9_CHCFG_n_SDS                   (0x0000F000uL)
+#define DMAC9_CHCFG_n_DDS                   (0x000F0000uL)
+#define DMAC9_CHCFG_n_SAD                   (0x00100000uL)
+#define DMAC9_CHCFG_n_DAD                   (0x00200000uL)
+#define DMAC9_CHCFG_n_TM                    (0x00400000uL)
+#define DMAC9_CHCFG_n_DEM                   (0x01000000uL)
+#define DMAC9_CHCFG_n_TCM                   (0x02000000uL)
+#define DMAC9_CHCFG_n_SBE                   (0x08000000uL)
+#define DMAC9_CHCFG_n_RSEL                  (0x10000000uL)
+#define DMAC9_CHCFG_n_RSW                   (0x20000000uL)
+#define DMAC9_CHCFG_n_REN                   (0x40000000uL)
+#define DMAC9_CHCFG_n_DMS                   (0x80000000uL)
+
+#define DMAC9_CHITVL_n_ITVL                 (0x0000FFFFuL)
+
+#define DMAC9_CHEXT_n_SCA                   (0x000000F0uL)
+#define DMAC9_CHEXT_n_DCA                   (0x0000F000uL)
+
+#define DMAC9_NXLA_n_NXLA                   (0xFFFFFFFFuL)
+
+#define DMAC9_CRLA_n_CRLA                   (0xFFFFFFFFuL)
+
+/* ---- DMAC10 ---- */
+#define DMAC10_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC10_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC10_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC10_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC10_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC10_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC10_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC10_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC10_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC10_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC10_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC10_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC10_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC10_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC10_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC10_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC10_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC10_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC10_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC10_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC10_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC10_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC10_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC10_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC10_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC10_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC10_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC10_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC10_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC10_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC10_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC10_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC10_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC10_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC10_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC10_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC10_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC10_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC10_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC10_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC10_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC10_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC10_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC10_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC10_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC10_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC10_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC10_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC10_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC10_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC10_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC10_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC10_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC10_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC10_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC10_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC11 ---- */
+#define DMAC11_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC11_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC11_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC11_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC11_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC11_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC11_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC11_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC11_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC11_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC11_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC11_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC11_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC11_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC11_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC11_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC11_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC11_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC11_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC11_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC11_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC11_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC11_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC11_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC11_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC11_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC11_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC11_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC11_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC11_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC11_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC11_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC11_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC11_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC11_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC11_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC11_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC11_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC11_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC11_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC11_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC11_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC11_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC11_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC11_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC11_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC11_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC11_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC11_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC11_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC11_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC11_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC11_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC11_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC11_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC11_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC12 ---- */
+#define DMAC12_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC12_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC12_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC12_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC12_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC12_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC12_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC12_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC12_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC12_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC12_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC12_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC12_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC12_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC12_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC12_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC12_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC12_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC12_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC12_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC12_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC12_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC12_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC12_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC12_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC12_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC12_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC12_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC12_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC12_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC12_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC12_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC12_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC12_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC12_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC12_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC12_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC12_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC12_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC12_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC12_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC12_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC12_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC12_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC12_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC12_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC12_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC12_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC12_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC12_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC12_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC12_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC12_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC12_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC12_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC12_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC13 ---- */
+#define DMAC13_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC13_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC13_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC13_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC13_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC13_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC13_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC13_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC13_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC13_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC13_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC13_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC13_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC13_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC13_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC13_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC13_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC13_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC13_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC13_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC13_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC13_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC13_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC13_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC13_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC13_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC13_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC13_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC13_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC13_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC13_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC13_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC13_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC13_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC13_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC13_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC13_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC13_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC13_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC13_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC13_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC13_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC13_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC13_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC13_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC13_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC13_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC13_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC13_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC13_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC13_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC13_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC13_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC13_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC13_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC13_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC14 ---- */
+#define DMAC14_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC14_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC14_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC14_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC14_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC14_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC14_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC14_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC14_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC14_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC14_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC14_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC14_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC14_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC14_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC14_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC14_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC14_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC14_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC14_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC14_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC14_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC14_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC14_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC14_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC14_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC14_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC14_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC14_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC14_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC14_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC14_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC14_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC14_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC14_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC14_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC14_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC14_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC14_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC14_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC14_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC14_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC14_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC14_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC14_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC14_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC14_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC14_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC14_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC14_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC14_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC14_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC14_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC14_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC14_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC14_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC15 ---- */
+#define DMAC15_N0SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC15_N0DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC15_N0TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC15_N1SA_n_SA                    (0xFFFFFFFFuL)
+
+#define DMAC15_N1DA_n_DA                    (0xFFFFFFFFuL)
+
+#define DMAC15_N1TB_n_TB                    (0xFFFFFFFFuL)
+
+#define DMAC15_CRSA_n_CRSA                  (0xFFFFFFFFuL)
+
+#define DMAC15_CRDA_n_CRDA                  (0xFFFFFFFFuL)
+
+#define DMAC15_CRTB_n_CRTB                  (0xFFFFFFFFuL)
+
+#define DMAC15_CHSTAT_n_EN                  (0x00000001uL)
+#define DMAC15_CHSTAT_n_RQST                (0x00000002uL)
+#define DMAC15_CHSTAT_n_TACT                (0x00000004uL)
+#define DMAC15_CHSTAT_n_SUS                 (0x00000008uL)
+#define DMAC15_CHSTAT_n_ER                  (0x00000010uL)
+#define DMAC15_CHSTAT_n_END                 (0x00000020uL)
+#define DMAC15_CHSTAT_n_TC                  (0x00000040uL)
+#define DMAC15_CHSTAT_n_SR                  (0x00000080uL)
+#define DMAC15_CHSTAT_n_DL                  (0x00000100uL)
+#define DMAC15_CHSTAT_n_DW                  (0x00000200uL)
+#define DMAC15_CHSTAT_n_DER                 (0x00000400uL)
+#define DMAC15_CHSTAT_n_MODE                (0x00000800uL)
+#define DMAC15_CHSTAT_n_INTMSK              (0x00010000uL)
+
+#define DMAC15_CHCTRL_n_SETEN               (0x00000001uL)
+#define DMAC15_CHCTRL_n_CLREN               (0x00000002uL)
+#define DMAC15_CHCTRL_n_STG                 (0x00000004uL)
+#define DMAC15_CHCTRL_n_SWRST               (0x00000008uL)
+#define DMAC15_CHCTRL_n_CLRRQ               (0x00000010uL)
+#define DMAC15_CHCTRL_n_CLREND              (0x00000020uL)
+#define DMAC15_CHCTRL_n_CLRTC               (0x00000040uL)
+#define DMAC15_CHCTRL_n_SETSUS              (0x00000100uL)
+#define DMAC15_CHCTRL_n_CLRSUS              (0x00000200uL)
+#define DMAC15_CHCTRL_n_SETINTMSK           (0x00010000uL)
+#define DMAC15_CHCTRL_n_CLRINTMSK           (0x00020000uL)
+
+#define DMAC15_CHCFG_n_SEL                  (0x00000007uL)
+#define DMAC15_CHCFG_n_REQD                 (0x00000008uL)
+#define DMAC15_CHCFG_n_LOEN                 (0x00000010uL)
+#define DMAC15_CHCFG_n_HIEN                 (0x00000020uL)
+#define DMAC15_CHCFG_n_LVL                  (0x00000040uL)
+#define DMAC15_CHCFG_n_AM                   (0x00000700uL)
+#define DMAC15_CHCFG_n_SDS                  (0x0000F000uL)
+#define DMAC15_CHCFG_n_DDS                  (0x000F0000uL)
+#define DMAC15_CHCFG_n_SAD                  (0x00100000uL)
+#define DMAC15_CHCFG_n_DAD                  (0x00200000uL)
+#define DMAC15_CHCFG_n_TM                   (0x00400000uL)
+#define DMAC15_CHCFG_n_DEM                  (0x01000000uL)
+#define DMAC15_CHCFG_n_TCM                  (0x02000000uL)
+#define DMAC15_CHCFG_n_SBE                  (0x08000000uL)
+#define DMAC15_CHCFG_n_RSEL                 (0x10000000uL)
+#define DMAC15_CHCFG_n_RSW                  (0x20000000uL)
+#define DMAC15_CHCFG_n_REN                  (0x40000000uL)
+#define DMAC15_CHCFG_n_DMS                  (0x80000000uL)
+
+#define DMAC15_CHITVL_n_ITVL                (0x0000FFFFuL)
+
+#define DMAC15_CHEXT_n_SCA                  (0x000000F0uL)
+#define DMAC15_CHEXT_n_DCA                  (0x0000F000uL)
+
+#define DMAC15_NXLA_n_NXLA                  (0xFFFFFFFFuL)
+
+#define DMAC15_CRLA_n_CRLA                  (0xFFFFFFFFuL)
+
+/* ---- DMAC8-15 ---- */
+#define DMAC815_DCTRL_8_15_PR               (0x00000001uL)
+#define DMAC815_DCTRL_8_15_LVINT            (0x00000002uL)
+#define DMAC815_DCTRL_8_15_LDCA             (0x0000003CuL)
+#define DMAC815_DCTRL_8_15_LWCA             (0x00003C00uL)
+
+#define DMAC815_DSTAT_EN_8_15_EN8           (0x00000001uL)
+#define DMAC815_DSTAT_EN_8_15_EN9           (0x00000002uL)
+#define DMAC815_DSTAT_EN_8_15_EN10          (0x00000004uL)
+#define DMAC815_DSTAT_EN_8_15_EN11          (0x00000008uL)
+#define DMAC815_DSTAT_EN_8_15_EN12          (0x00000010uL)
+#define DMAC815_DSTAT_EN_8_15_EN13          (0x00000020uL)
+#define DMAC815_DSTAT_EN_8_15_EN14          (0x00000040uL)
+#define DMAC815_DSTAT_EN_8_15_EN15          (0x00000080uL)
+
+#define DMAC815_DSTAT_ER_8_15_ER8           (0x00000001uL)
+#define DMAC815_DSTAT_ER_8_15_ER9           (0x00000002uL)
+#define DMAC815_DSTAT_ER_8_15_ER10          (0x00000004uL)
+#define DMAC815_DSTAT_ER_8_15_ER11          (0x00000008uL)
+#define DMAC815_DSTAT_ER_8_15_ER12          (0x00000010uL)
+#define DMAC815_DSTAT_ER_8_15_ER13          (0x00000020uL)
+#define DMAC815_DSTAT_ER_8_15_ER14          (0x00000040uL)
+#define DMAC815_DSTAT_ER_8_15_ER15          (0x00000080uL)
+
+#define DMAC815_DSTAT_END_8_15_END8         (0x00000001uL)
+#define DMAC815_DSTAT_END_8_15_END9         (0x00000002uL)
+#define DMAC815_DSTAT_END_8_15_END10        (0x00000004uL)
+#define DMAC815_DSTAT_END_8_15_END11        (0x00000008uL)
+#define DMAC815_DSTAT_END_8_15_END12        (0x00000010uL)
+#define DMAC815_DSTAT_END_8_15_END13        (0x00000020uL)
+#define DMAC815_DSTAT_END_8_15_END14        (0x00000040uL)
+#define DMAC815_DSTAT_END_8_15_END15        (0x00000080uL)
+
+#define DMAC815_DSTAT_TC_8_15_TC8           (0x00000001uL)
+#define DMAC815_DSTAT_TC_8_15_TC9           (0x00000002uL)
+#define DMAC815_DSTAT_TC_8_15_TC10          (0x00000004uL)
+#define DMAC815_DSTAT_TC_8_15_TC11          (0x00000008uL)
+#define DMAC815_DSTAT_TC_8_15_TC12          (0x00000010uL)
+#define DMAC815_DSTAT_TC_8_15_TC13          (0x00000020uL)
+#define DMAC815_DSTAT_TC_8_15_TC14          (0x00000040uL)
+#define DMAC815_DSTAT_TC_8_15_TC15          (0x00000080uL)
+
+#define DMAC815_DSTAT_SUS_8_15_SUS8         (0x00000001uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS9         (0x00000002uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS10        (0x00000004uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS11        (0x00000008uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS12        (0x00000010uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS13        (0x00000020uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS14        (0x00000040uL)
+#define DMAC815_DSTAT_SUS_8_15_SUS15        (0x00000080uL)
+
+/* ---- DMAC0-1 ---- */
+#define DMAC01_DMARS_CH0_RID                (0x00000003uL)
+#define DMAC01_DMARS_CH0_MID                (0x000001FCuL)
+#define DMAC01_DMARS_CH1_RID                (0x00030000uL)
+#define DMAC01_DMARS_CH1_MID                (0x01FC0000uL)
+
+/* ---- DMAC2-3 ---- */
+#define DMAC23_DMARS_CH2_RID                (0x00000003uL)
+#define DMAC23_DMARS_CH2_MID                (0x000001FCuL)
+#define DMAC23_DMARS_CH3_RID                (0x00030000uL)
+#define DMAC23_DMARS_CH3_MID                (0x01FC0000uL)
+
+/* ---- DMAC4-5 ---- */
+#define DMAC45_DMARS_CH4_RID                (0x00000003uL)
+#define DMAC45_DMARS_CH4_MID                (0x000001FCuL)
+#define DMAC45_DMARS_CH5_RID                (0x00030000uL)
+#define DMAC45_DMARS_CH5_MID                (0x01FC0000uL)
+
+/* ---- DMAC6-7 ---- */
+#define DMAC67_DMARS_CH6_RID                (0x00000003uL)
+#define DMAC67_DMARS_CH6_MID                (0x000001FCuL)
+#define DMAC67_DMARS_CH7_RID                (0x00030000uL)
+#define DMAC67_DMARS_CH7_MID                (0x01FC0000uL)
+
+/* ---- DMAC8-9 ---- */
+#define DMAC89_DMARS_CH8_RID                (0x00000003uL)
+#define DMAC89_DMARS_CH8_MID                (0x000001FCuL)
+#define DMAC89_DMARS_CH9_RID                (0x00030000uL)
+#define DMAC89_DMARS_CH9_MID                (0x01FC0000uL)
+
+/* ---- DMAC10-11 ---- */
+#define DMAC1011_DMARS_CH10_RID             (0x00000003uL)
+#define DMAC1011_DMARS_CH10_MID             (0x000001FCuL)
+#define DMAC1011_DMARS_CH11_RID             (0x00030000uL)
+#define DMAC1011_DMARS_CH11_MID             (0x01FC0000uL)
+
+/* ---- DMAC12-13 ---- */
+#define DMAC1213_DMARS_CH12_RID             (0x00000003uL)
+#define DMAC1213_DMARS_CH12_MID             (0x000001FCuL)
+#define DMAC1213_DMARS_CH13_RID             (0x00030000uL)
+#define DMAC1213_DMARS_CH13_MID             (0x01FC0000uL)
+
+/* ---- DMAC14-15 ---- */
+#define DMAC1415_DMARS_CH14_RID             (0x00000003uL)
+#define DMAC1415_DMARS_CH14_MID             (0x000001FCuL)
+#define DMAC1415_DMARS_CH15_RID             (0x00030000uL)
+#define DMAC1415_DMARS_CH15_MID             (0x01FC0000uL)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- DMAC0 ---- */
+#define DMAC0_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC0_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC0_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC0_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC0_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC0_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC0_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC0_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC0_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC0_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC0_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC0_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC0_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC0_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC0_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC0_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC0_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC0_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC0_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC0_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC0_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC0_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC0_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC0_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC0_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC0_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC0_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC0_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC0_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC0_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC0_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC0_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC0_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC0_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC0_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC0_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC0_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC0_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC0_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC0_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC0_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC0_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC0_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC0_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC0_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC0_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC0_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC0_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC0_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC0_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC0_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC0_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC0_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC0_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC0_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC0_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC1 ---- */
+#define DMAC1_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC1_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC1_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC1_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC1_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC1_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC1_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC1_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC1_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC1_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC1_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC1_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC1_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC1_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC1_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC1_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC1_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC1_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC1_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC1_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC1_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC1_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC1_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC1_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC1_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC1_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC1_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC1_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC1_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC1_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC1_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC1_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC1_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC1_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC1_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC1_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC1_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC1_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC1_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC1_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC1_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC1_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC1_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC1_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC1_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC1_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC1_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC1_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC1_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC1_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC1_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC1_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC1_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC1_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC1_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC1_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC2 ---- */
+#define DMAC2_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC2_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC2_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC2_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC2_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC2_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC2_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC2_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC2_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC2_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC2_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC2_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC2_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC2_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC2_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC2_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC2_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC2_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC2_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC2_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC2_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC2_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC2_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC2_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC2_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC2_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC2_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC2_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC2_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC2_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC2_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC2_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC2_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC2_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC2_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC2_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC2_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC2_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC2_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC2_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC2_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC2_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC2_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC2_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC2_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC2_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC2_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC2_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC2_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC2_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC2_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC2_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC2_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC2_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC2_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC2_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC3 ---- */
+#define DMAC3_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC3_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC3_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC3_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC3_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC3_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC3_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC3_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC3_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC3_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC3_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC3_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC3_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC3_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC3_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC3_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC3_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC3_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC3_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC3_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC3_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC3_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC3_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC3_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC3_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC3_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC3_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC3_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC3_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC3_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC3_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC3_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC3_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC3_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC3_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC3_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC3_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC3_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC3_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC3_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC3_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC3_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC3_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC3_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC3_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC3_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC3_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC3_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC3_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC3_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC3_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC3_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC3_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC3_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC3_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC3_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC4 ---- */
+#define DMAC4_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC4_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC4_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC4_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC4_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC4_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC4_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC4_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC4_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC4_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC4_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC4_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC4_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC4_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC4_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC4_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC4_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC4_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC4_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC4_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC4_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC4_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC4_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC4_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC4_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC4_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC4_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC4_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC4_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC4_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC4_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC4_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC4_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC4_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC4_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC4_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC4_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC4_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC4_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC4_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC4_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC4_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC4_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC4_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC4_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC4_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC4_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC4_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC4_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC4_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC4_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC4_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC4_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC4_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC4_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC4_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC5 ---- */
+#define DMAC5_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC5_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC5_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC5_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC5_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC5_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC5_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC5_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC5_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC5_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC5_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC5_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC5_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC5_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC5_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC5_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC5_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC5_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC5_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC5_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC5_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC5_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC5_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC5_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC5_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC5_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC5_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC5_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC5_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC5_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC5_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC5_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC5_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC5_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC5_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC5_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC5_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC5_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC5_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC5_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC5_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC5_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC5_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC5_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC5_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC5_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC5_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC5_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC5_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC5_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC5_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC5_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC5_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC5_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC5_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC5_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC6 ---- */
+#define DMAC6_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC6_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC6_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC6_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC6_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC6_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC6_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC6_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC6_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC6_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC6_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC6_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC6_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC6_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC6_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC6_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC6_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC6_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC6_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC6_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC6_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC6_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC6_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC6_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC6_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC6_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC6_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC6_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC6_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC6_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC6_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC6_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC6_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC6_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC6_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC6_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC6_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC6_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC6_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC6_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC6_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC6_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC6_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC6_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC6_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC6_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC6_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC6_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC6_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC6_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC6_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC6_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC6_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC6_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC6_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC6_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC7 ---- */
+#define DMAC7_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC7_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC7_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC7_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC7_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC7_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC7_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC7_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC7_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC7_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC7_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC7_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC7_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC7_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC7_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC7_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC7_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC7_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC7_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC7_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC7_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC7_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC7_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC7_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC7_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC7_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC7_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC7_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC7_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC7_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC7_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC7_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC7_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC7_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC7_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC7_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC7_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC7_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC7_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC7_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC7_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC7_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC7_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC7_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC7_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC7_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC7_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC7_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC7_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC7_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC7_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC7_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC7_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC7_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC7_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC7_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC0-7 ---- */
+#define DMAC07_DCTRL_0_7_PR_SHIFT           (0u)
+#define DMAC07_DCTRL_0_7_LVINT_SHIFT        (1u)
+#define DMAC07_DCTRL_0_7_LDCA_SHIFT         (2u)
+#define DMAC07_DCTRL_0_7_LWCA_SHIFT         (6u)
+
+#define DMAC07_DSTAT_EN_0_7_EN0_SHIFT       (0u)
+#define DMAC07_DSTAT_EN_0_7_EN1_SHIFT       (1u)
+#define DMAC07_DSTAT_EN_0_7_EN2_SHIFT       (2u)
+#define DMAC07_DSTAT_EN_0_7_EN3_SHIFT       (3u)
+#define DMAC07_DSTAT_EN_0_7_EN4_SHIFT       (4u)
+#define DMAC07_DSTAT_EN_0_7_EN5_SHIFT       (5u)
+#define DMAC07_DSTAT_EN_0_7_EN6_SHIFT       (6u)
+#define DMAC07_DSTAT_EN_0_7_EN7_SHIFT       (7u)
+
+#define DMAC07_DSTAT_ER_0_7_ER0_SHIFT       (0u)
+#define DMAC07_DSTAT_ER_0_7_ER1_SHIFT       (1u)
+#define DMAC07_DSTAT_ER_0_7_ER2_SHIFT       (2u)
+#define DMAC07_DSTAT_ER_0_7_ER3_SHIFT       (3u)
+#define DMAC07_DSTAT_ER_0_7_ER4_SHIFT       (4u)
+#define DMAC07_DSTAT_ER_0_7_ER5_SHIFT       (5u)
+#define DMAC07_DSTAT_ER_0_7_ER6_SHIFT       (6u)
+#define DMAC07_DSTAT_ER_0_7_ER7_SHIFT       (7u)
+
+#define DMAC07_DSTAT_END_0_7_END0_SHIFT     (0u)
+#define DMAC07_DSTAT_END_0_7_END1_SHIFT     (1u)
+#define DMAC07_DSTAT_END_0_7_END2_SHIFT     (2u)
+#define DMAC07_DSTAT_END_0_7_END3_SHIFT     (3u)
+#define DMAC07_DSTAT_END_0_7_END4_SHIFT     (4u)
+#define DMAC07_DSTAT_END_0_7_END5_SHIFT     (5u)
+#define DMAC07_DSTAT_END_0_7_END6_SHIFT     (6u)
+#define DMAC07_DSTAT_END_0_7_END7_SHIFT     (7u)
+
+#define DMAC07_DSTAT_TC_0_7_TC0_SHIFT       (0u)
+#define DMAC07_DSTAT_TC_0_7_TC1_SHIFT       (1u)
+#define DMAC07_DSTAT_TC_0_7_TC2_SHIFT       (2u)
+#define DMAC07_DSTAT_TC_0_7_TC3_SHIFT       (3u)
+#define DMAC07_DSTAT_TC_0_7_TC4_SHIFT       (4u)
+#define DMAC07_DSTAT_TC_0_7_TC5_SHIFT       (5u)
+#define DMAC07_DSTAT_TC_0_7_TC6_SHIFT       (6u)
+#define DMAC07_DSTAT_TC_0_7_TC7_SHIFT       (7u)
+
+#define DMAC07_DSTAT_SUS_0_7_SUS0_SHIFT     (0u)
+#define DMAC07_DSTAT_SUS_0_7_SUS1_SHIFT     (1u)
+#define DMAC07_DSTAT_SUS_0_7_SUS2_SHIFT     (2u)
+#define DMAC07_DSTAT_SUS_0_7_SUS3_SHIFT     (3u)
+#define DMAC07_DSTAT_SUS_0_7_SUS4_SHIFT     (4u)
+#define DMAC07_DSTAT_SUS_0_7_SUS5_SHIFT     (5u)
+#define DMAC07_DSTAT_SUS_0_7_SUS6_SHIFT     (6u)
+#define DMAC07_DSTAT_SUS_0_7_SUS7_SHIFT     (7u)
+
+/* ---- DMAC8 ---- */
+#define DMAC8_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC8_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC8_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC8_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC8_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC8_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC8_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC8_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC8_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC8_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC8_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC8_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC8_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC8_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC8_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC8_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC8_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC8_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC8_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC8_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC8_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC8_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC8_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC8_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC8_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC8_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC8_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC8_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC8_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC8_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC8_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC8_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC8_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC8_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC8_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC8_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC8_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC8_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC8_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC8_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC8_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC8_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC8_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC8_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC8_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC8_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC8_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC8_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC8_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC8_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC8_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC8_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC8_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC8_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC8_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC8_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC9 ---- */
+#define DMAC9_N0SA_n_SA_SHIFT               (0u)
+
+#define DMAC9_N0DA_n_DA_SHIFT               (0u)
+
+#define DMAC9_N0TB_n_TB_SHIFT               (0u)
+
+#define DMAC9_N1SA_n_SA_SHIFT               (0u)
+
+#define DMAC9_N1DA_n_DA_SHIFT               (0u)
+
+#define DMAC9_N1TB_n_TB_SHIFT               (0u)
+
+#define DMAC9_CRSA_n_CRSA_SHIFT             (0u)
+
+#define DMAC9_CRDA_n_CRDA_SHIFT             (0u)
+
+#define DMAC9_CRTB_n_CRTB_SHIFT             (0u)
+
+#define DMAC9_CHSTAT_n_EN_SHIFT             (0u)
+#define DMAC9_CHSTAT_n_RQST_SHIFT           (1u)
+#define DMAC9_CHSTAT_n_TACT_SHIFT           (2u)
+#define DMAC9_CHSTAT_n_SUS_SHIFT            (3u)
+#define DMAC9_CHSTAT_n_ER_SHIFT             (4u)
+#define DMAC9_CHSTAT_n_END_SHIFT            (5u)
+#define DMAC9_CHSTAT_n_TC_SHIFT             (6u)
+#define DMAC9_CHSTAT_n_SR_SHIFT             (7u)
+#define DMAC9_CHSTAT_n_DL_SHIFT             (8u)
+#define DMAC9_CHSTAT_n_DW_SHIFT             (9u)
+#define DMAC9_CHSTAT_n_DER_SHIFT            (10u)
+#define DMAC9_CHSTAT_n_MODE_SHIFT           (11u)
+#define DMAC9_CHSTAT_n_INTMSK_SHIFT         (16u)
+
+#define DMAC9_CHCTRL_n_SETEN_SHIFT          (0u)
+#define DMAC9_CHCTRL_n_CLREN_SHIFT          (1u)
+#define DMAC9_CHCTRL_n_STG_SHIFT            (2u)
+#define DMAC9_CHCTRL_n_SWRST_SHIFT          (3u)
+#define DMAC9_CHCTRL_n_CLRRQ_SHIFT          (4u)
+#define DMAC9_CHCTRL_n_CLREND_SHIFT         (5u)
+#define DMAC9_CHCTRL_n_CLRTC_SHIFT          (6u)
+#define DMAC9_CHCTRL_n_SETSUS_SHIFT         (8u)
+#define DMAC9_CHCTRL_n_CLRSUS_SHIFT         (9u)
+#define DMAC9_CHCTRL_n_SETINTMSK_SHIFT      (16u)
+#define DMAC9_CHCTRL_n_CLRINTMSK_SHIFT      (17u)
+
+#define DMAC9_CHCFG_n_SEL_SHIFT             (0u)
+#define DMAC9_CHCFG_n_REQD_SHIFT            (3u)
+#define DMAC9_CHCFG_n_LOEN_SHIFT            (4u)
+#define DMAC9_CHCFG_n_HIEN_SHIFT            (5u)
+#define DMAC9_CHCFG_n_LVL_SHIFT             (6u)
+#define DMAC9_CHCFG_n_AM_SHIFT              (8u)
+#define DMAC9_CHCFG_n_SDS_SHIFT             (12u)
+#define DMAC9_CHCFG_n_DDS_SHIFT             (16u)
+#define DMAC9_CHCFG_n_SAD_SHIFT             (20u)
+#define DMAC9_CHCFG_n_DAD_SHIFT             (21u)
+#define DMAC9_CHCFG_n_TM_SHIFT              (22u)
+#define DMAC9_CHCFG_n_DEM_SHIFT             (24u)
+#define DMAC9_CHCFG_n_TCM_SHIFT             (25u)
+#define DMAC9_CHCFG_n_SBE_SHIFT             (27u)
+#define DMAC9_CHCFG_n_RSEL_SHIFT            (28u)
+#define DMAC9_CHCFG_n_RSW_SHIFT             (29u)
+#define DMAC9_CHCFG_n_REN_SHIFT             (30u)
+#define DMAC9_CHCFG_n_DMS_SHIFT             (31u)
+
+#define DMAC9_CHITVL_n_ITVL_SHIFT           (0u)
+
+#define DMAC9_CHEXT_n_SCA_SHIFT             (4u)
+#define DMAC9_CHEXT_n_DCA_SHIFT             (12u)
+
+#define DMAC9_NXLA_n_NXLA_SHIFT             (0u)
+
+#define DMAC9_CRLA_n_CRLA_SHIFT             (0u)
+
+/* ---- DMAC10 ---- */
+#define DMAC10_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC10_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC10_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC10_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC10_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC10_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC10_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC10_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC10_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC10_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC10_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC10_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC10_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC10_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC10_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC10_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC10_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC10_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC10_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC10_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC10_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC10_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC10_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC10_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC10_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC10_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC10_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC10_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC10_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC10_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC10_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC10_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC10_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC10_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC10_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC10_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC10_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC10_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC10_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC10_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC10_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC10_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC10_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC10_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC10_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC10_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC10_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC10_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC10_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC10_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC10_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC10_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC10_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC10_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC10_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC10_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC11 ---- */
+#define DMAC11_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC11_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC11_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC11_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC11_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC11_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC11_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC11_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC11_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC11_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC11_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC11_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC11_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC11_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC11_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC11_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC11_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC11_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC11_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC11_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC11_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC11_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC11_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC11_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC11_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC11_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC11_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC11_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC11_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC11_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC11_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC11_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC11_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC11_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC11_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC11_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC11_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC11_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC11_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC11_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC11_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC11_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC11_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC11_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC11_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC11_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC11_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC11_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC11_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC11_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC11_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC11_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC11_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC11_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC11_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC11_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC12 ---- */
+#define DMAC12_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC12_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC12_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC12_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC12_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC12_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC12_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC12_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC12_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC12_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC12_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC12_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC12_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC12_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC12_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC12_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC12_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC12_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC12_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC12_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC12_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC12_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC12_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC12_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC12_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC12_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC12_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC12_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC12_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC12_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC12_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC12_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC12_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC12_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC12_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC12_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC12_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC12_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC12_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC12_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC12_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC12_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC12_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC12_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC12_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC12_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC12_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC12_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC12_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC12_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC12_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC12_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC12_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC12_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC12_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC12_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC13 ---- */
+#define DMAC13_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC13_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC13_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC13_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC13_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC13_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC13_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC13_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC13_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC13_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC13_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC13_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC13_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC13_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC13_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC13_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC13_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC13_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC13_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC13_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC13_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC13_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC13_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC13_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC13_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC13_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC13_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC13_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC13_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC13_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC13_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC13_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC13_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC13_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC13_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC13_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC13_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC13_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC13_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC13_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC13_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC13_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC13_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC13_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC13_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC13_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC13_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC13_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC13_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC13_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC13_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC13_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC13_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC13_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC13_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC13_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC14 ---- */
+#define DMAC14_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC14_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC14_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC14_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC14_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC14_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC14_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC14_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC14_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC14_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC14_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC14_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC14_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC14_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC14_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC14_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC14_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC14_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC14_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC14_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC14_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC14_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC14_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC14_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC14_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC14_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC14_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC14_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC14_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC14_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC14_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC14_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC14_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC14_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC14_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC14_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC14_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC14_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC14_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC14_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC14_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC14_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC14_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC14_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC14_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC14_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC14_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC14_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC14_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC14_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC14_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC14_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC14_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC14_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC14_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC14_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC15 ---- */
+#define DMAC15_N0SA_n_SA_SHIFT              (0u)
+
+#define DMAC15_N0DA_n_DA_SHIFT              (0u)
+
+#define DMAC15_N0TB_n_TB_SHIFT              (0u)
+
+#define DMAC15_N1SA_n_SA_SHIFT              (0u)
+
+#define DMAC15_N1DA_n_DA_SHIFT              (0u)
+
+#define DMAC15_N1TB_n_TB_SHIFT              (0u)
+
+#define DMAC15_CRSA_n_CRSA_SHIFT            (0u)
+
+#define DMAC15_CRDA_n_CRDA_SHIFT            (0u)
+
+#define DMAC15_CRTB_n_CRTB_SHIFT            (0u)
+
+#define DMAC15_CHSTAT_n_EN_SHIFT            (0u)
+#define DMAC15_CHSTAT_n_RQST_SHIFT          (1u)
+#define DMAC15_CHSTAT_n_TACT_SHIFT          (2u)
+#define DMAC15_CHSTAT_n_SUS_SHIFT           (3u)
+#define DMAC15_CHSTAT_n_ER_SHIFT            (4u)
+#define DMAC15_CHSTAT_n_END_SHIFT           (5u)
+#define DMAC15_CHSTAT_n_TC_SHIFT            (6u)
+#define DMAC15_CHSTAT_n_SR_SHIFT            (7u)
+#define DMAC15_CHSTAT_n_DL_SHIFT            (8u)
+#define DMAC15_CHSTAT_n_DW_SHIFT            (9u)
+#define DMAC15_CHSTAT_n_DER_SHIFT           (10u)
+#define DMAC15_CHSTAT_n_MODE_SHIFT          (11u)
+#define DMAC15_CHSTAT_n_INTMSK_SHIFT        (16u)
+
+#define DMAC15_CHCTRL_n_SETEN_SHIFT         (0u)
+#define DMAC15_CHCTRL_n_CLREN_SHIFT         (1u)
+#define DMAC15_CHCTRL_n_STG_SHIFT           (2u)
+#define DMAC15_CHCTRL_n_SWRST_SHIFT         (3u)
+#define DMAC15_CHCTRL_n_CLRRQ_SHIFT         (4u)
+#define DMAC15_CHCTRL_n_CLREND_SHIFT        (5u)
+#define DMAC15_CHCTRL_n_CLRTC_SHIFT         (6u)
+#define DMAC15_CHCTRL_n_SETSUS_SHIFT        (8u)
+#define DMAC15_CHCTRL_n_CLRSUS_SHIFT        (9u)
+#define DMAC15_CHCTRL_n_SETINTMSK_SHIFT     (16u)
+#define DMAC15_CHCTRL_n_CLRINTMSK_SHIFT     (17u)
+
+#define DMAC15_CHCFG_n_SEL_SHIFT            (0u)
+#define DMAC15_CHCFG_n_REQD_SHIFT           (3u)
+#define DMAC15_CHCFG_n_LOEN_SHIFT           (4u)
+#define DMAC15_CHCFG_n_HIEN_SHIFT           (5u)
+#define DMAC15_CHCFG_n_LVL_SHIFT            (6u)
+#define DMAC15_CHCFG_n_AM_SHIFT             (8u)
+#define DMAC15_CHCFG_n_SDS_SHIFT            (12u)
+#define DMAC15_CHCFG_n_DDS_SHIFT            (16u)
+#define DMAC15_CHCFG_n_SAD_SHIFT            (20u)
+#define DMAC15_CHCFG_n_DAD_SHIFT            (21u)
+#define DMAC15_CHCFG_n_TM_SHIFT             (22u)
+#define DMAC15_CHCFG_n_DEM_SHIFT            (24u)
+#define DMAC15_CHCFG_n_TCM_SHIFT            (25u)
+#define DMAC15_CHCFG_n_SBE_SHIFT            (27u)
+#define DMAC15_CHCFG_n_RSEL_SHIFT           (28u)
+#define DMAC15_CHCFG_n_RSW_SHIFT            (29u)
+#define DMAC15_CHCFG_n_REN_SHIFT            (30u)
+#define DMAC15_CHCFG_n_DMS_SHIFT            (31u)
+
+#define DMAC15_CHITVL_n_ITVL_SHIFT          (0u)
+
+#define DMAC15_CHEXT_n_SCA_SHIFT            (4u)
+#define DMAC15_CHEXT_n_DCA_SHIFT            (12u)
+
+#define DMAC15_NXLA_n_NXLA_SHIFT            (0u)
+
+#define DMAC15_CRLA_n_CRLA_SHIFT            (0u)
+
+/* ---- DMAC8-15 ---- */
+#define DMAC815_DCTRL_8_15_PR_SHIFT         (0u)
+#define DMAC815_DCTRL_8_15_LVINT_SHIFT      (1u)
+#define DMAC815_DCTRL_8_15_LDCA_SHIFT       (2u)
+#define DMAC815_DCTRL_8_15_LWCA_SHIFT       (10u)
+
+#define DMAC815_DSTAT_EN_8_15_EN8_SHIFT     (0u)
+#define DMAC815_DSTAT_EN_8_15_EN9_SHIFT     (1u)
+#define DMAC815_DSTAT_EN_8_15_EN10_SHIFT    (2u)
+#define DMAC815_DSTAT_EN_8_15_EN11_SHIFT    (3u)
+#define DMAC815_DSTAT_EN_8_15_EN12_SHIFT    (4u)
+#define DMAC815_DSTAT_EN_8_15_EN13_SHIFT    (5u)
+#define DMAC815_DSTAT_EN_8_15_EN14_SHIFT    (6u)
+#define DMAC815_DSTAT_EN_8_15_EN15_SHIFT    (7u)
+
+#define DMAC815_DSTAT_ER_8_15_ER8_SHIFT     (0u)
+#define DMAC815_DSTAT_ER_8_15_ER9_SHIFT     (1u)
+#define DMAC815_DSTAT_ER_8_15_ER10_SHIFT    (2u)
+#define DMAC815_DSTAT_ER_8_15_ER11_SHIFT    (3u)
+#define DMAC815_DSTAT_ER_8_15_ER12_SHIFT    (4u)
+#define DMAC815_DSTAT_ER_8_15_ER13_SHIFT    (5u)
+#define DMAC815_DSTAT_ER_8_15_ER14_SHIFT    (6u)
+#define DMAC815_DSTAT_ER_8_15_ER15_SHIFT    (7u)
+
+#define DMAC815_DSTAT_END_8_15_END8_SHIFT   (0u)
+#define DMAC815_DSTAT_END_8_15_END9_SHIFT   (1u)
+#define DMAC815_DSTAT_END_8_15_END10_SHIFT  (2u)
+#define DMAC815_DSTAT_END_8_15_END11_SHIFT  (3u)
+#define DMAC815_DSTAT_END_8_15_END12_SHIFT  (4u)
+#define DMAC815_DSTAT_END_8_15_END13_SHIFT  (5u)
+#define DMAC815_DSTAT_END_8_15_END14_SHIFT  (6u)
+#define DMAC815_DSTAT_END_8_15_END15_SHIFT  (7u)
+
+#define DMAC815_DSTAT_TC_8_15_TC8_SHIFT     (0u)
+#define DMAC815_DSTAT_TC_8_15_TC9_SHIFT     (1u)
+#define DMAC815_DSTAT_TC_8_15_TC10_SHIFT    (2u)
+#define DMAC815_DSTAT_TC_8_15_TC11_SHIFT    (3u)
+#define DMAC815_DSTAT_TC_8_15_TC12_SHIFT    (4u)
+#define DMAC815_DSTAT_TC_8_15_TC13_SHIFT    (5u)
+#define DMAC815_DSTAT_TC_8_15_TC14_SHIFT    (6u)
+#define DMAC815_DSTAT_TC_8_15_TC15_SHIFT    (7u)
+
+#define DMAC815_DSTAT_SUS_8_15_SUS8_SHIFT   (0u)
+#define DMAC815_DSTAT_SUS_8_15_SUS9_SHIFT   (1u)
+#define DMAC815_DSTAT_SUS_8_15_SUS10_SHIFT  (2u)
+#define DMAC815_DSTAT_SUS_8_15_SUS11_SHIFT  (3u)
+#define DMAC815_DSTAT_SUS_8_15_SUS12_SHIFT  (4u)
+#define DMAC815_DSTAT_SUS_8_15_SUS13_SHIFT  (5u)
+#define DMAC815_DSTAT_SUS_8_15_SUS14_SHIFT  (6u)
+#define DMAC815_DSTAT_SUS_8_15_SUS15_SHIFT  (7u)
+
+/* ---- DMAC0-1 ---- */
+#define DMAC01_DMARS_CH0_RID_SHIFT          (0u)
+#define DMAC01_DMARS_CH0_MID_SHIFT          (2u)
+#define DMAC01_DMARS_CH1_RID_SHIFT          (16u)
+#define DMAC01_DMARS_CH1_MID_SHIFT          (18u)
+
+/* ---- DMAC2-3 ---- */
+#define DMAC23_DMARS_CH2_RID_SHIFT          (0u)
+#define DMAC23_DMARS_CH2_MID_SHIFT          (2u)
+#define DMAC23_DMARS_CH3_RID_SHIFT          (16u)
+#define DMAC23_DMARS_CH3_MID_SHIFT          (18u)
+
+/* ---- DMAC4-5 ---- */
+#define DMAC45_DMARS_CH4_RID_SHIFT          (0u)
+#define DMAC45_DMARS_CH4_MID_SHIFT          (2u)
+#define DMAC45_DMARS_CH5_RID_SHIFT          (16u)
+#define DMAC45_DMARS_CH5_MID_SHIFT          (18u)
+
+/* ---- DMAC6-7 ---- */
+#define DMAC67_DMARS_CH6_RID_SHIFT          (0u)
+#define DMAC67_DMARS_CH6_MID_SHIFT          (2u)
+#define DMAC67_DMARS_CH7_RID_SHIFT          (16u)
+#define DMAC67_DMARS_CH7_MID_SHIFT          (18u)
+
+/* ---- DMAC8-9 ---- */
+#define DMAC89_DMARS_CH8_RID_SHIFT          (0u)
+#define DMAC89_DMARS_CH8_MID_SHIFT          (2u)
+#define DMAC89_DMARS_CH9_RID_SHIFT          (16u)
+#define DMAC89_DMARS_CH9_MID_SHIFT          (18u)
+
+/* ---- DMAC10-11 ---- */
+#define DMAC1011_DMARS_CH10_RID_SHIFT       (0u)
+#define DMAC1011_DMARS_CH10_MID_SHIFT       (2u)
+#define DMAC1011_DMARS_CH11_RID_SHIFT       (16u)
+#define DMAC1011_DMARS_CH11_MID_SHIFT       (18u)
+
+/* ---- DMAC12-13 ---- */
+#define DMAC1213_DMARS_CH12_RID_SHIFT       (0u)
+#define DMAC1213_DMARS_CH12_MID_SHIFT       (2u)
+#define DMAC1213_DMARS_CH13_RID_SHIFT       (16u)
+#define DMAC1213_DMARS_CH13_MID_SHIFT       (18u)
+
+/* ---- DMAC14-15 ---- */
+#define DMAC1415_DMARS_CH14_RID_SHIFT       (0u)
+#define DMAC1415_DMARS_CH14_MID_SHIFT       (2u)
+#define DMAC1415_DMARS_CH15_RID_SHIFT       (16u)
+#define DMAC1415_DMARS_CH15_MID_SHIFT       (18u)
+
+
+#endif /* DMAC_IOBITMASK_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/gpio_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,5794 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : gpio_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : General purpose I/O ports register define header
+*******************************************************************************/
+#ifndef GPIO_IOBITMASK_H
+#define GPIO_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- P0 ---- */
+#define GPIO_PPR0_PPR00                         (0x0001u)
+#define GPIO_PPR0_PPR01                         (0x0002u)
+#define GPIO_PPR0_PPR02                         (0x0004u)
+#define GPIO_PPR0_PPR03                         (0x0008u)
+#define GPIO_PPR0_PPR04                         (0x0010u)
+#define GPIO_PPR0_PPR05                         (0x0020u)
+
+#define GPIO_PMC0_PMC04                         (0x0010u)
+#define GPIO_PMC0_PMC05                         (0x0020u)
+
+#define GPIO_PMCSR0_PMCSR04                     (0x00000010uL)
+#define GPIO_PMCSR0_PMCSR05                     (0x00000020uL)
+
+#define GPIO_PIBC0_PIBC00                       (0x0001u)
+#define GPIO_PIBC0_PIBC01                       (0x0002u)
+#define GPIO_PIBC0_PIBC02                       (0x0004u)
+#define GPIO_PIBC0_PIBC03                       (0x0008u)
+#define GPIO_PIBC0_PIBC04                       (0x0010u)
+#define GPIO_PIBC0_PIBC05                       (0x0020u)
+
+/* ---- P1 ---- */
+#define GPIO_P1_P10                             (0x0001u)
+#define GPIO_P1_P11                             (0x0002u)
+#define GPIO_P1_P12                             (0x0004u)
+#define GPIO_P1_P13                             (0x0008u)
+#define GPIO_P1_P14                             (0x0010u)
+#define GPIO_P1_P15                             (0x0020u)
+#define GPIO_P1_P16                             (0x0040u)
+#define GPIO_P1_P17                             (0x0080u)
+
+#define GPIO_PSR1_PSR10                         (0x00000001uL)
+#define GPIO_PSR1_PSR11                         (0x00000002uL)
+#define GPIO_PSR1_PSR12                         (0x00000004uL)
+#define GPIO_PSR1_PSR13                         (0x00000008uL)
+#define GPIO_PSR1_PSR14                         (0x00000010uL)
+#define GPIO_PSR1_PSR15                         (0x00000020uL)
+#define GPIO_PSR1_PSR16                         (0x00000040uL)
+#define GPIO_PSR1_PSR17                         (0x00000080uL)
+#define GPIO_PSR1_PSR116                        (0x00010000uL)
+#define GPIO_PSR1_PSR117                        (0x00020000uL)
+#define GPIO_PSR1_PSR118                        (0x00040000uL)
+#define GPIO_PSR1_PSR119                        (0x00080000uL)
+#define GPIO_PSR1_PSR120                        (0x00100000uL)
+#define GPIO_PSR1_PSR121                        (0x00200000uL)
+#define GPIO_PSR1_PSR122                        (0x00400000uL)
+#define GPIO_PSR1_PSR123                        (0x00800000uL)
+
+#define GPIO_PPR1_PPR10                         (0x0001u)
+#define GPIO_PPR1_PPR11                         (0x0002u)
+#define GPIO_PPR1_PPR12                         (0x0004u)
+#define GPIO_PPR1_PPR13                         (0x0008u)
+#define GPIO_PPR1_PPR14                         (0x0010u)
+#define GPIO_PPR1_PPR15                         (0x0020u)
+#define GPIO_PPR1_PPR16                         (0x0040u)
+#define GPIO_PPR1_PPR17                         (0x0080u)
+#define GPIO_PPR1_PPR18                         (0x0100u)
+#define GPIO_PPR1_PPR19                         (0x0200u)
+#define GPIO_PPR1_PPR110                        (0x0400u)
+#define GPIO_PPR1_PPR111                        (0x0800u)
+#define GPIO_PPR1_PPR112                        (0x1000u)
+#define GPIO_PPR1_PPR113                        (0x2000u)
+#define GPIO_PPR1_PPR114                        (0x4000u)
+#define GPIO_PPR1_PPR115                        (0x8000u)
+
+#define GPIO_PM1_PM10                           (0x0001u)
+#define GPIO_PM1_PM11                           (0x0002u)
+#define GPIO_PM1_PM12                           (0x0004u)
+#define GPIO_PM1_PM13                           (0x0008u)
+#define GPIO_PM1_PM14                           (0x0010u)
+#define GPIO_PM1_PM15                           (0x0020u)
+#define GPIO_PM1_PM16                           (0x0040u)
+#define GPIO_PM1_PM17                           (0x0080u)
+
+#define GPIO_PMC1_PMC10                         (0x0001u)
+#define GPIO_PMC1_PMC11                         (0x0002u)
+#define GPIO_PMC1_PMC12                         (0x0004u)
+#define GPIO_PMC1_PMC13                         (0x0008u)
+#define GPIO_PMC1_PMC14                         (0x0010u)
+#define GPIO_PMC1_PMC15                         (0x0020u)
+#define GPIO_PMC1_PMC16                         (0x0040u)
+#define GPIO_PMC1_PMC17                         (0x0080u)
+#define GPIO_PMC1_PMC18                         (0x0100u)
+#define GPIO_PMC1_PMC19                         (0x0200u)
+#define GPIO_PMC1_PMC110                        (0x0400u)
+#define GPIO_PMC1_PMC111                        (0x0800u)
+#define GPIO_PMC1_PMC112                        (0x1000u)
+#define GPIO_PMC1_PMC113                        (0x2000u)
+#define GPIO_PMC1_PMC114                        (0x4000u)
+#define GPIO_PMC1_PMC115                        (0x8000u)
+
+#define GPIO_PFC1_PFC10                         (0x0001u)
+#define GPIO_PFC1_PFC11                         (0x0002u)
+#define GPIO_PFC1_PFC12                         (0x0004u)
+#define GPIO_PFC1_PFC13                         (0x0008u)
+#define GPIO_PFC1_PFC14                         (0x0010u)
+#define GPIO_PFC1_PFC15                         (0x0020u)
+#define GPIO_PFC1_PFC16                         (0x0040u)
+#define GPIO_PFC1_PFC17                         (0x0080u)
+#define GPIO_PFC1_PFC18                         (0x0100u)
+#define GPIO_PFC1_PFC19                         (0x0200u)
+#define GPIO_PFC1_PFC110                        (0x0400u)
+#define GPIO_PFC1_PFC111                        (0x0800u)
+#define GPIO_PFC1_PFC112                        (0x1000u)
+#define GPIO_PFC1_PFC113                        (0x2000u)
+#define GPIO_PFC1_PFC114                        (0x4000u)
+#define GPIO_PFC1_PFC115                        (0x8000u)
+
+#define GPIO_PFCE1_PFCE10                       (0x0001u)
+#define GPIO_PFCE1_PFCE11                       (0x0002u)
+#define GPIO_PFCE1_PFCE12                       (0x0004u)
+#define GPIO_PFCE1_PFCE13                       (0x0008u)
+#define GPIO_PFCE1_PFCE14                       (0x0010u)
+#define GPIO_PFCE1_PFCE15                       (0x0020u)
+#define GPIO_PFCE1_PFCE16                       (0x0040u)
+#define GPIO_PFCE1_PFCE17                       (0x0080u)
+#define GPIO_PFCE1_PFCE18                       (0x0100u)
+#define GPIO_PFCE1_PFCE19                       (0x0200u)
+#define GPIO_PFCE1_PFCE110                      (0x0400u)
+#define GPIO_PFCE1_PFCE111                      (0x0800u)
+#define GPIO_PFCE1_PFCE112                      (0x1000u)
+#define GPIO_PFCE1_PFCE113                      (0x2000u)
+#define GPIO_PFCE1_PFCE114                      (0x4000u)
+#define GPIO_PFCE1_PFCE115                      (0x8000u)
+
+#define GPIO_PNOT1_PNOT10                       (0x0001u)
+#define GPIO_PNOT1_PNOT11                       (0x0002u)
+#define GPIO_PNOT1_PNOT12                       (0x0004u)
+#define GPIO_PNOT1_PNOT13                       (0x0008u)
+#define GPIO_PNOT1_PNOT14                       (0x0010u)
+#define GPIO_PNOT1_PNOT15                       (0x0020u)
+#define GPIO_PNOT1_PNOT16                       (0x0040u)
+#define GPIO_PNOT1_PNOT17                       (0x0080u)
+
+#define GPIO_PMSR1_PMSR10                       (0x00000001uL)
+#define GPIO_PMSR1_PMSR11                       (0x00000002uL)
+#define GPIO_PMSR1_PMSR12                       (0x00000004uL)
+#define GPIO_PMSR1_PMSR13                       (0x00000008uL)
+#define GPIO_PMSR1_PMSR14                       (0x00000010uL)
+#define GPIO_PMSR1_PMSR15                       (0x00000020uL)
+#define GPIO_PMSR1_PMSR16                       (0x00000040uL)
+#define GPIO_PMSR1_PMSR17                       (0x00000080uL)
+#define GPIO_PMSR1_PMSR116                      (0x00010000uL)
+#define GPIO_PMSR1_PMSR117                      (0x00020000uL)
+#define GPIO_PMSR1_PMSR118                      (0x00040000uL)
+#define GPIO_PMSR1_PMSR119                      (0x00080000uL)
+#define GPIO_PMSR1_PMSR120                      (0x00100000uL)
+#define GPIO_PMSR1_PMSR121                      (0x00200000uL)
+#define GPIO_PMSR1_PMSR122                      (0x00400000uL)
+#define GPIO_PMSR1_PMSR123                      (0x00800000uL)
+
+#define GPIO_PMCSR1_PMCSR10                     (0x00000001uL)
+#define GPIO_PMCSR1_PMCSR11                     (0x00000002uL)
+#define GPIO_PMCSR1_PMCSR12                     (0x00000004uL)
+#define GPIO_PMCSR1_PMCSR13                     (0x00000008uL)
+#define GPIO_PMCSR1_PMCSR14                     (0x00000010uL)
+#define GPIO_PMCSR1_PMCSR15                     (0x00000020uL)
+#define GPIO_PMCSR1_PMCSR16                     (0x00000040uL)
+#define GPIO_PMCSR1_PMCSR17                     (0x00000080uL)
+#define GPIO_PMCSR1_PMCSR116                    (0x00010000uL)
+#define GPIO_PMCSR1_PMCSR117                    (0x00020000uL)
+#define GPIO_PMCSR1_PMCSR118                    (0x00040000uL)
+#define GPIO_PMCSR1_PMCSR119                    (0x00080000uL)
+#define GPIO_PMCSR1_PMCSR120                    (0x00100000uL)
+#define GPIO_PMCSR1_PMCSR121                    (0x00200000uL)
+#define GPIO_PMCSR1_PMCSR122                    (0x00400000uL)
+#define GPIO_PMCSR1_PMCSR123                    (0x00800000uL)
+
+#define GPIO_PFCAE1_PFCAE10                     (0x0001u)
+#define GPIO_PFCAE1_PFCAE11                     (0x0002u)
+#define GPIO_PFCAE1_PFCAE12                     (0x0004u)
+#define GPIO_PFCAE1_PFCAE13                     (0x0008u)
+#define GPIO_PFCAE1_PFCAE14                     (0x0010u)
+#define GPIO_PFCAE1_PFCAE15                     (0x0020u)
+#define GPIO_PFCAE1_PFCAE16                     (0x0040u)
+#define GPIO_PFCAE1_PFCAE17                     (0x0080u)
+#define GPIO_PFCAE1_PFCAE18                     (0x0100u)
+#define GPIO_PFCAE1_PFCAE19                     (0x0200u)
+#define GPIO_PFCAE1_PFCAE110                    (0x0400u)
+#define GPIO_PFCAE1_PFCAE111                    (0x0800u)
+#define GPIO_PFCAE1_PFCAE112                    (0x1000u)
+#define GPIO_PFCAE1_PFCAE113                    (0x2000u)
+#define GPIO_PFCAE1_PFCAE114                    (0x4000u)
+#define GPIO_PFCAE1_PFCAE115                    (0x8000u)
+
+#define GPIO_PIBC1_PIBC10                       (0x0001u)
+#define GPIO_PIBC1_PIBC11                       (0x0002u)
+#define GPIO_PIBC1_PIBC12                       (0x0004u)
+#define GPIO_PIBC1_PIBC13                       (0x0008u)
+#define GPIO_PIBC1_PIBC14                       (0x0010u)
+#define GPIO_PIBC1_PIBC15                       (0x0020u)
+#define GPIO_PIBC1_PIBC16                       (0x0040u)
+#define GPIO_PIBC1_PIBC17                       (0x0080u)
+#define GPIO_PIBC1_PIBC18                       (0x0100u)
+#define GPIO_PIBC1_PIBC19                       (0x0200u)
+#define GPIO_PIBC1_PIBC110                      (0x0400u)
+#define GPIO_PIBC1_PIBC111                      (0x0800u)
+#define GPIO_PIBC1_PIBC112                      (0x1000u)
+#define GPIO_PIBC1_PIBC113                      (0x2000u)
+#define GPIO_PIBC1_PIBC114                      (0x4000u)
+#define GPIO_PIBC1_PIBC115                      (0x8000u)
+
+#define GPIO_PBDC1_PBDC10                       (0x0001u)
+#define GPIO_PBDC1_PBDC11                       (0x0002u)
+#define GPIO_PBDC1_PBDC12                       (0x0004u)
+#define GPIO_PBDC1_PBDC13                       (0x0008u)
+#define GPIO_PBDC1_PBDC14                       (0x0010u)
+#define GPIO_PBDC1_PBDC15                       (0x0020u)
+#define GPIO_PBDC1_PBDC16                       (0x0040u)
+#define GPIO_PBDC1_PBDC17                       (0x0080u)
+#define GPIO_PBDC1_PBDC18                       (0x0100u)
+#define GPIO_PBDC1_PBDC19                       (0x0200u)
+#define GPIO_PBDC1_PBDC110                      (0x0400u)
+#define GPIO_PBDC1_PBDC111                      (0x0800u)
+#define GPIO_PBDC1_PBDC112                      (0x1000u)
+#define GPIO_PBDC1_PBDC113                      (0x2000u)
+#define GPIO_PBDC1_PBDC114                      (0x4000u)
+#define GPIO_PBDC1_PBDC115                      (0x8000u)
+
+#define GPIO_PIPC1_PIPC10                       (0x0001u)
+#define GPIO_PIPC1_PIPC11                       (0x0002u)
+#define GPIO_PIPC1_PIPC12                       (0x0004u)
+#define GPIO_PIPC1_PIPC13                       (0x0008u)
+#define GPIO_PIPC1_PIPC14                       (0x0010u)
+#define GPIO_PIPC1_PIPC15                       (0x0020u)
+#define GPIO_PIPC1_PIPC16                       (0x0040u)
+#define GPIO_PIPC1_PIPC17                       (0x0080u)
+
+/* ---- P2 ---- */
+#define GPIO_P2_P20                             (0x0001u)
+#define GPIO_P2_P21                             (0x0002u)
+#define GPIO_P2_P22                             (0x0004u)
+#define GPIO_P2_P23                             (0x0008u)
+#define GPIO_P2_P24                             (0x0010u)
+#define GPIO_P2_P25                             (0x0020u)
+#define GPIO_P2_P26                             (0x0040u)
+#define GPIO_P2_P27                             (0x0080u)
+#define GPIO_P2_P28                             (0x0100u)
+#define GPIO_P2_P29                             (0x0200u)
+#define GPIO_P2_P210                            (0x0400u)
+#define GPIO_P2_P211                            (0x0800u)
+#define GPIO_P2_P212                            (0x1000u)
+#define GPIO_P2_P213                            (0x2000u)
+#define GPIO_P2_P214                            (0x4000u)
+#define GPIO_P2_P215                            (0x8000u)
+
+#define GPIO_PSR2_PSR20                         (0x00000001uL)
+#define GPIO_PSR2_PSR21                         (0x00000002uL)
+#define GPIO_PSR2_PSR22                         (0x00000004uL)
+#define GPIO_PSR2_PSR23                         (0x00000008uL)
+#define GPIO_PSR2_PSR24                         (0x00000010uL)
+#define GPIO_PSR2_PSR25                         (0x00000020uL)
+#define GPIO_PSR2_PSR26                         (0x00000040uL)
+#define GPIO_PSR2_PSR27                         (0x00000080uL)
+#define GPIO_PSR2_PSR28                         (0x00000100uL)
+#define GPIO_PSR2_PSR29                         (0x00000200uL)
+#define GPIO_PSR2_PSR210                        (0x00000400uL)
+#define GPIO_PSR2_PSR211                        (0x00000800uL)
+#define GPIO_PSR2_PSR212                        (0x00001000uL)
+#define GPIO_PSR2_PSR213                        (0x00002000uL)
+#define GPIO_PSR2_PSR214                        (0x00004000uL)
+#define GPIO_PSR2_PSR215                        (0x00008000uL)
+#define GPIO_PSR2_PSR216                        (0x00010000uL)
+#define GPIO_PSR2_PSR217                        (0x00020000uL)
+#define GPIO_PSR2_PSR218                        (0x00040000uL)
+#define GPIO_PSR2_PSR219                        (0x00080000uL)
+#define GPIO_PSR2_PSR220                        (0x00100000uL)
+#define GPIO_PSR2_PSR221                        (0x00200000uL)
+#define GPIO_PSR2_PSR222                        (0x00400000uL)
+#define GPIO_PSR2_PSR223                        (0x00800000uL)
+#define GPIO_PSR2_PSR224                        (0x01000000uL)
+#define GPIO_PSR2_PSR225                        (0x02000000uL)
+#define GPIO_PSR2_PSR226                        (0x04000000uL)
+#define GPIO_PSR2_PSR227                        (0x08000000uL)
+#define GPIO_PSR2_PSR228                        (0x10000000uL)
+#define GPIO_PSR2_PSR229                        (0x20000000uL)
+#define GPIO_PSR2_PSR230                        (0x40000000uL)
+#define GPIO_PSR2_PSR231                        (0x80000000uL)
+
+#define GPIO_PPR2_PPR20                         (0x0001u)
+#define GPIO_PPR2_PPR21                         (0x0002u)
+#define GPIO_PPR2_PPR22                         (0x0004u)
+#define GPIO_PPR2_PPR23                         (0x0008u)
+#define GPIO_PPR2_PPR24                         (0x0010u)
+#define GPIO_PPR2_PPR25                         (0x0020u)
+#define GPIO_PPR2_PPR26                         (0x0040u)
+#define GPIO_PPR2_PPR27                         (0x0080u)
+#define GPIO_PPR2_PPR28                         (0x0100u)
+#define GPIO_PPR2_PPR29                         (0x0200u)
+#define GPIO_PPR2_PPR210                        (0x0400u)
+#define GPIO_PPR2_PPR211                        (0x0800u)
+#define GPIO_PPR2_PPR212                        (0x1000u)
+#define GPIO_PPR2_PPR213                        (0x2000u)
+#define GPIO_PPR2_PPR214                        (0x4000u)
+#define GPIO_PPR2_PPR215                        (0x8000u)
+
+#define GPIO_PM2_PM20                           (0x0001u)
+#define GPIO_PM2_PM21                           (0x0002u)
+#define GPIO_PM2_PM22                           (0x0004u)
+#define GPIO_PM2_PM23                           (0x0008u)
+#define GPIO_PM2_PM24                           (0x0010u)
+#define GPIO_PM2_PM25                           (0x0020u)
+#define GPIO_PM2_PM26                           (0x0040u)
+#define GPIO_PM2_PM27                           (0x0080u)
+#define GPIO_PM2_PM28                           (0x0100u)
+#define GPIO_PM2_PM29                           (0x0200u)
+#define GPIO_PM2_PM210                          (0x0400u)
+#define GPIO_PM2_PM211                          (0x0800u)
+#define GPIO_PM2_PM212                          (0x1000u)
+#define GPIO_PM2_PM213                          (0x2000u)
+#define GPIO_PM2_PM214                          (0x4000u)
+#define GPIO_PM2_PM215                          (0x8000u)
+
+#define GPIO_PMC2_PMC20                         (0x0001u)
+#define GPIO_PMC2_PMC21                         (0x0002u)
+#define GPIO_PMC2_PMC22                         (0x0004u)
+#define GPIO_PMC2_PMC23                         (0x0008u)
+#define GPIO_PMC2_PMC24                         (0x0010u)
+#define GPIO_PMC2_PMC25                         (0x0020u)
+#define GPIO_PMC2_PMC26                         (0x0040u)
+#define GPIO_PMC2_PMC27                         (0x0080u)
+#define GPIO_PMC2_PMC28                         (0x0100u)
+#define GPIO_PMC2_PMC29                         (0x0200u)
+#define GPIO_PMC2_PMC210                        (0x0400u)
+#define GPIO_PMC2_PMC211                        (0x0800u)
+#define GPIO_PMC2_PMC212                        (0x1000u)
+#define GPIO_PMC2_PMC213                        (0x2000u)
+#define GPIO_PMC2_PMC214                        (0x4000u)
+#define GPIO_PMC2_PMC215                        (0x8000u)
+
+#define GPIO_PFC2_PFC20                         (0x0001u)
+#define GPIO_PFC2_PFC21                         (0x0002u)
+#define GPIO_PFC2_PFC22                         (0x0004u)
+#define GPIO_PFC2_PFC23                         (0x0008u)
+#define GPIO_PFC2_PFC24                         (0x0010u)
+#define GPIO_PFC2_PFC25                         (0x0020u)
+#define GPIO_PFC2_PFC26                         (0x0040u)
+#define GPIO_PFC2_PFC27                         (0x0080u)
+#define GPIO_PFC2_PFC28                         (0x0100u)
+#define GPIO_PFC2_PFC29                         (0x0200u)
+#define GPIO_PFC2_PFC210                        (0x0400u)
+#define GPIO_PFC2_PFC211                        (0x0800u)
+#define GPIO_PFC2_PFC212                        (0x1000u)
+#define GPIO_PFC2_PFC213                        (0x2000u)
+#define GPIO_PFC2_PFC214                        (0x4000u)
+#define GPIO_PFC2_PFC215                        (0x8000u)
+
+#define GPIO_PFCE2_PFCE20                       (0x0001u)
+#define GPIO_PFCE2_PFCE21                       (0x0002u)
+#define GPIO_PFCE2_PFCE22                       (0x0004u)
+#define GPIO_PFCE2_PFCE23                       (0x0008u)
+#define GPIO_PFCE2_PFCE24                       (0x0010u)
+#define GPIO_PFCE2_PFCE25                       (0x0020u)
+#define GPIO_PFCE2_PFCE26                       (0x0040u)
+#define GPIO_PFCE2_PFCE27                       (0x0080u)
+#define GPIO_PFCE2_PFCE28                       (0x0100u)
+#define GPIO_PFCE2_PFCE29                       (0x0200u)
+#define GPIO_PFCE2_PFCE210                      (0x0400u)
+#define GPIO_PFCE2_PFCE211                      (0x0800u)
+#define GPIO_PFCE2_PFCE212                      (0x1000u)
+#define GPIO_PFCE2_PFCE213                      (0x2000u)
+#define GPIO_PFCE2_PFCE214                      (0x4000u)
+#define GPIO_PFCE2_PFCE215                      (0x8000u)
+
+#define GPIO_PNOT2_PNOT20                       (0x0001u)
+#define GPIO_PNOT2_PNOT21                       (0x0002u)
+#define GPIO_PNOT2_PNOT22                       (0x0004u)
+#define GPIO_PNOT2_PNOT23                       (0x0008u)
+#define GPIO_PNOT2_PNOT24                       (0x0010u)
+#define GPIO_PNOT2_PNOT25                       (0x0020u)
+#define GPIO_PNOT2_PNOT26                       (0x0040u)
+#define GPIO_PNOT2_PNOT27                       (0x0080u)
+#define GPIO_PNOT2_PNOT28                       (0x0100u)
+#define GPIO_PNOT2_PNOT29                       (0x0200u)
+#define GPIO_PNOT2_PNOT210                      (0x0400u)
+#define GPIO_PNOT2_PNOT211                      (0x0800u)
+#define GPIO_PNOT2_PNOT212                      (0x1000u)
+#define GPIO_PNOT2_PNOT213                      (0x2000u)
+#define GPIO_PNOT2_PNOT214                      (0x4000u)
+#define GPIO_PNOT2_PNOT215                      (0x8000u)
+
+#define GPIO_PMSR2_PMSR20                       (0x00000001uL)
+#define GPIO_PMSR2_PMSR21                       (0x00000002uL)
+#define GPIO_PMSR2_PMSR22                       (0x00000004uL)
+#define GPIO_PMSR2_PMSR23                       (0x00000008uL)
+#define GPIO_PMSR2_PMSR24                       (0x00000010uL)
+#define GPIO_PMSR2_PMSR25                       (0x00000020uL)
+#define GPIO_PMSR2_PMSR26                       (0x00000040uL)
+#define GPIO_PMSR2_PMSR27                       (0x00000080uL)
+#define GPIO_PMSR2_PMSR28                       (0x00000100uL)
+#define GPIO_PMSR2_PMSR29                       (0x00000200uL)
+#define GPIO_PMSR2_PMSR210                      (0x00000400uL)
+#define GPIO_PMSR2_PMSR211                      (0x00000800uL)
+#define GPIO_PMSR2_PMSR212                      (0x00001000uL)
+#define GPIO_PMSR2_PMSR213                      (0x00002000uL)
+#define GPIO_PMSR2_PMSR214                      (0x00004000uL)
+#define GPIO_PMSR2_PMSR215                      (0x00008000uL)
+#define GPIO_PMSR2_PMSR216                      (0x00010000uL)
+#define GPIO_PMSR2_PMSR217                      (0x00020000uL)
+#define GPIO_PMSR2_PMSR218                      (0x00040000uL)
+#define GPIO_PMSR2_PMSR219                      (0x00080000uL)
+#define GPIO_PMSR2_PMSR220                      (0x00100000uL)
+#define GPIO_PMSR2_PMSR221                      (0x00200000uL)
+#define GPIO_PMSR2_PMSR222                      (0x00400000uL)
+#define GPIO_PMSR2_PMSR223                      (0x00800000uL)
+#define GPIO_PMSR2_PMSR224                      (0x01000000uL)
+#define GPIO_PMSR2_PMSR225                      (0x02000000uL)
+#define GPIO_PMSR2_PMSR226                      (0x04000000uL)
+#define GPIO_PMSR2_PMSR227                      (0x08000000uL)
+#define GPIO_PMSR2_PMSR228                      (0x10000000uL)
+#define GPIO_PMSR2_PMSR229                      (0x20000000uL)
+#define GPIO_PMSR2_PMSR230                      (0x40000000uL)
+#define GPIO_PMSR2_PMSR231                      (0x80000000uL)
+
+#define GPIO_PMCSR2_PMCSR20                     (0x00000001uL)
+#define GPIO_PMCSR2_PMCSR21                     (0x00000002uL)
+#define GPIO_PMCSR2_PMCSR22                     (0x00000004uL)
+#define GPIO_PMCSR2_PMCSR23                     (0x00000008uL)
+#define GPIO_PMCSR2_PMCSR24                     (0x00000010uL)
+#define GPIO_PMCSR2_PMCSR25                     (0x00000020uL)
+#define GPIO_PMCSR2_PMCSR26                     (0x00000040uL)
+#define GPIO_PMCSR2_PMCSR27                     (0x00000080uL)
+#define GPIO_PMCSR2_PMCSR28                     (0x00000100uL)
+#define GPIO_PMCSR2_PMCSR29                     (0x00000200uL)
+#define GPIO_PMCSR2_PMCSR210                    (0x00000400uL)
+#define GPIO_PMCSR2_PMCSR211                    (0x00000800uL)
+#define GPIO_PMCSR2_PMCSR212                    (0x00001000uL)
+#define GPIO_PMCSR2_PMCSR213                    (0x00002000uL)
+#define GPIO_PMCSR2_PMCSR214                    (0x00004000uL)
+#define GPIO_PMCSR2_PMCSR215                    (0x00008000uL)
+#define GPIO_PMCSR2_PMCSR216                    (0x00010000uL)
+#define GPIO_PMCSR2_PMCSR217                    (0x00020000uL)
+#define GPIO_PMCSR2_PMCSR218                    (0x00040000uL)
+#define GPIO_PMCSR2_PMCSR219                    (0x00080000uL)
+#define GPIO_PMCSR2_PMCSR220                    (0x00100000uL)
+#define GPIO_PMCSR2_PMCSR221                    (0x00200000uL)
+#define GPIO_PMCSR2_PMCSR222                    (0x00400000uL)
+#define GPIO_PMCSR2_PMCSR223                    (0x00800000uL)
+#define GPIO_PMCSR2_PMCSR224                    (0x01000000uL)
+#define GPIO_PMCSR2_PMCSR225                    (0x02000000uL)
+#define GPIO_PMCSR2_PMCSR226                    (0x04000000uL)
+#define GPIO_PMCSR2_PMCSR227                    (0x08000000uL)
+#define GPIO_PMCSR2_PMCSR228                    (0x10000000uL)
+#define GPIO_PMCSR2_PMCSR229                    (0x20000000uL)
+#define GPIO_PMCSR2_PMCSR230                    (0x40000000uL)
+#define GPIO_PMCSR2_PMCSR231                    (0x80000000uL)
+
+#define GPIO_PFCAE2_PFCAE20                     (0x0001u)
+#define GPIO_PFCAE2_PFCAE21                     (0x0002u)
+#define GPIO_PFCAE2_PFCAE22                     (0x0004u)
+#define GPIO_PFCAE2_PFCAE23                     (0x0008u)
+#define GPIO_PFCAE2_PFCAE24                     (0x0010u)
+#define GPIO_PFCAE2_PFCAE25                     (0x0020u)
+#define GPIO_PFCAE2_PFCAE26                     (0x0040u)
+#define GPIO_PFCAE2_PFCAE27                     (0x0080u)
+#define GPIO_PFCAE2_PFCAE28                     (0x0100u)
+#define GPIO_PFCAE2_PFCAE29                     (0x0200u)
+#define GPIO_PFCAE2_PFCAE210                    (0x0400u)
+#define GPIO_PFCAE2_PFCAE211                    (0x0800u)
+#define GPIO_PFCAE2_PFCAE212                    (0x1000u)
+#define GPIO_PFCAE2_PFCAE213                    (0x2000u)
+#define GPIO_PFCAE2_PFCAE214                    (0x4000u)
+#define GPIO_PFCAE2_PFCAE215                    (0x8000u)
+
+#define GPIO_PIBC2_PIBC20                       (0x0001u)
+#define GPIO_PIBC2_PIBC21                       (0x0002u)
+#define GPIO_PIBC2_PIBC22                       (0x0004u)
+#define GPIO_PIBC2_PIBC23                       (0x0008u)
+#define GPIO_PIBC2_PIBC24                       (0x0010u)
+#define GPIO_PIBC2_PIBC25                       (0x0020u)
+#define GPIO_PIBC2_PIBC26                       (0x0040u)
+#define GPIO_PIBC2_PIBC27                       (0x0080u)
+#define GPIO_PIBC2_PIBC28                       (0x0100u)
+#define GPIO_PIBC2_PIBC29                       (0x0200u)
+#define GPIO_PIBC2_PIBC210                      (0x0400u)
+#define GPIO_PIBC2_PIBC211                      (0x0800u)
+#define GPIO_PIBC2_PIBC212                      (0x1000u)
+#define GPIO_PIBC2_PIBC213                      (0x2000u)
+#define GPIO_PIBC2_PIBC214                      (0x4000u)
+#define GPIO_PIBC2_PIBC215                      (0x8000u)
+
+#define GPIO_PBDC2_PBDC20                       (0x0001u)
+#define GPIO_PBDC2_PBDC21                       (0x0002u)
+#define GPIO_PBDC2_PBDC22                       (0x0004u)
+#define GPIO_PBDC2_PBDC23                       (0x0008u)
+#define GPIO_PBDC2_PBDC24                       (0x0010u)
+#define GPIO_PBDC2_PBDC25                       (0x0020u)
+#define GPIO_PBDC2_PBDC26                       (0x0040u)
+#define GPIO_PBDC2_PBDC27                       (0x0080u)
+#define GPIO_PBDC2_PBDC28                       (0x0100u)
+#define GPIO_PBDC2_PBDC29                       (0x0200u)
+#define GPIO_PBDC2_PBDC210                      (0x0400u)
+#define GPIO_PBDC2_PBDC211                      (0x0800u)
+#define GPIO_PBDC2_PBDC212                      (0x1000u)
+#define GPIO_PBDC2_PBDC213                      (0x2000u)
+#define GPIO_PBDC2_PBDC214                      (0x4000u)
+#define GPIO_PBDC2_PBDC215                      (0x8000u)
+
+#define GPIO_PIPC2_PIPC20                       (0x0001u)
+#define GPIO_PIPC2_PIPC21                       (0x0002u)
+#define GPIO_PIPC2_PIPC22                       (0x0004u)
+#define GPIO_PIPC2_PIPC23                       (0x0008u)
+#define GPIO_PIPC2_PIPC24                       (0x0010u)
+#define GPIO_PIPC2_PIPC25                       (0x0020u)
+#define GPIO_PIPC2_PIPC26                       (0x0040u)
+#define GPIO_PIPC2_PIPC27                       (0x0080u)
+#define GPIO_PIPC2_PIPC28                       (0x0100u)
+#define GPIO_PIPC2_PIPC29                       (0x0200u)
+#define GPIO_PIPC2_PIPC210                      (0x0400u)
+#define GPIO_PIPC2_PIPC211                      (0x0800u)
+#define GPIO_PIPC2_PIPC212                      (0x1000u)
+#define GPIO_PIPC2_PIPC213                      (0x2000u)
+#define GPIO_PIPC2_PIPC214                      (0x4000u)
+#define GPIO_PIPC2_PIPC215                      (0x8000u)
+
+/* ---- P3 ---- */
+#define GPIO_P3_P30                             (0x0001u)
+#define GPIO_P3_P31                             (0x0002u)
+#define GPIO_P3_P32                             (0x0004u)
+#define GPIO_P3_P33                             (0x0008u)
+#define GPIO_P3_P34                             (0x0010u)
+#define GPIO_P3_P35                             (0x0020u)
+#define GPIO_P3_P36                             (0x0040u)
+#define GPIO_P3_P37                             (0x0080u)
+#define GPIO_P3_P38                             (0x0100u)
+#define GPIO_P3_P39                             (0x0200u)
+#define GPIO_P3_P310                            (0x0400u)
+#define GPIO_P3_P311                            (0x0800u)
+#define GPIO_P3_P312                            (0x1000u)
+#define GPIO_P3_P313                            (0x2000u)
+#define GPIO_P3_P314                            (0x4000u)
+#define GPIO_P3_P315                            (0x8000u)
+
+#define GPIO_PSR3_PSR30                         (0x00000001uL)
+#define GPIO_PSR3_PSR31                         (0x00000002uL)
+#define GPIO_PSR3_PSR32                         (0x00000004uL)
+#define GPIO_PSR3_PSR33                         (0x00000008uL)
+#define GPIO_PSR3_PSR34                         (0x00000010uL)
+#define GPIO_PSR3_PSR35                         (0x00000020uL)
+#define GPIO_PSR3_PSR36                         (0x00000040uL)
+#define GPIO_PSR3_PSR37                         (0x00000080uL)
+#define GPIO_PSR3_PSR38                         (0x00000100uL)
+#define GPIO_PSR3_PSR39                         (0x00000200uL)
+#define GPIO_PSR3_PSR310                        (0x00000400uL)
+#define GPIO_PSR3_PSR311                        (0x00000800uL)
+#define GPIO_PSR3_PSR312                        (0x00001000uL)
+#define GPIO_PSR3_PSR313                        (0x00002000uL)
+#define GPIO_PSR3_PSR314                        (0x00004000uL)
+#define GPIO_PSR3_PSR315                        (0x00008000uL)
+#define GPIO_PSR3_PSR316                        (0x00010000uL)
+#define GPIO_PSR3_PSR317                        (0x00020000uL)
+#define GPIO_PSR3_PSR318                        (0x00040000uL)
+#define GPIO_PSR3_PSR319                        (0x00080000uL)
+#define GPIO_PSR3_PSR320                        (0x00100000uL)
+#define GPIO_PSR3_PSR321                        (0x00200000uL)
+#define GPIO_PSR3_PSR322                        (0x00400000uL)
+#define GPIO_PSR3_PSR323                        (0x00800000uL)
+#define GPIO_PSR3_PSR324                        (0x01000000uL)
+#define GPIO_PSR3_PSR325                        (0x02000000uL)
+#define GPIO_PSR3_PSR326                        (0x04000000uL)
+#define GPIO_PSR3_PSR327                        (0x08000000uL)
+#define GPIO_PSR3_PSR328                        (0x10000000uL)
+#define GPIO_PSR3_PSR329                        (0x20000000uL)
+#define GPIO_PSR3_PSR330                        (0x40000000uL)
+#define GPIO_PSR3_PSR331                        (0x80000000uL)
+
+#define GPIO_PPR3_PPR30                         (0x0001u)
+#define GPIO_PPR3_PPR31                         (0x0002u)
+#define GPIO_PPR3_PPR32                         (0x0004u)
+#define GPIO_PPR3_PPR33                         (0x0008u)
+#define GPIO_PPR3_PPR34                         (0x0010u)
+#define GPIO_PPR3_PPR35                         (0x0020u)
+#define GPIO_PPR3_PPR36                         (0x0040u)
+#define GPIO_PPR3_PPR37                         (0x0080u)
+#define GPIO_PPR3_PPR38                         (0x0100u)
+#define GPIO_PPR3_PPR39                         (0x0200u)
+#define GPIO_PPR3_PPR310                        (0x0400u)
+#define GPIO_PPR3_PPR311                        (0x0800u)
+#define GPIO_PPR3_PPR312                        (0x1000u)
+#define GPIO_PPR3_PPR313                        (0x2000u)
+#define GPIO_PPR3_PPR314                        (0x4000u)
+#define GPIO_PPR3_PPR315                        (0x8000u)
+
+#define GPIO_PM3_PM30                           (0x0001u)
+#define GPIO_PM3_PM31                           (0x0002u)
+#define GPIO_PM3_PM32                           (0x0004u)
+#define GPIO_PM3_PM33                           (0x0008u)
+#define GPIO_PM3_PM34                           (0x0010u)
+#define GPIO_PM3_PM35                           (0x0020u)
+#define GPIO_PM3_PM36                           (0x0040u)
+#define GPIO_PM3_PM37                           (0x0080u)
+#define GPIO_PM3_PM38                           (0x0100u)
+#define GPIO_PM3_PM39                           (0x0200u)
+#define GPIO_PM3_PM310                          (0x0400u)
+#define GPIO_PM3_PM311                          (0x0800u)
+#define GPIO_PM3_PM312                          (0x1000u)
+#define GPIO_PM3_PM313                          (0x2000u)
+#define GPIO_PM3_PM314                          (0x4000u)
+#define GPIO_PM3_PM315                          (0x8000u)
+
+#define GPIO_PMC3_PMC30                         (0x0001u)
+#define GPIO_PMC3_PMC31                         (0x0002u)
+#define GPIO_PMC3_PMC32                         (0x0004u)
+#define GPIO_PMC3_PMC33                         (0x0008u)
+#define GPIO_PMC3_PMC34                         (0x0010u)
+#define GPIO_PMC3_PMC35                         (0x0020u)
+#define GPIO_PMC3_PMC36                         (0x0040u)
+#define GPIO_PMC3_PMC37                         (0x0080u)
+#define GPIO_PMC3_PMC38                         (0x0100u)
+#define GPIO_PMC3_PMC39                         (0x0200u)
+#define GPIO_PMC3_PMC310                        (0x0400u)
+#define GPIO_PMC3_PMC311                        (0x0800u)
+#define GPIO_PMC3_PMC312                        (0x1000u)
+#define GPIO_PMC3_PMC313                        (0x2000u)
+#define GPIO_PMC3_PMC314                        (0x4000u)
+#define GPIO_PMC3_PMC315                        (0x8000u)
+
+#define GPIO_PFC3_PFC30                         (0x0001u)
+#define GPIO_PFC3_PFC31                         (0x0002u)
+#define GPIO_PFC3_PFC32                         (0x0004u)
+#define GPIO_PFC3_PFC33                         (0x0008u)
+#define GPIO_PFC3_PFC34                         (0x0010u)
+#define GPIO_PFC3_PFC35                         (0x0020u)
+#define GPIO_PFC3_PFC36                         (0x0040u)
+#define GPIO_PFC3_PFC37                         (0x0080u)
+#define GPIO_PFC3_PFC38                         (0x0100u)
+#define GPIO_PFC3_PFC39                         (0x0200u)
+#define GPIO_PFC3_PFC310                        (0x0400u)
+#define GPIO_PFC3_PFC311                        (0x0800u)
+#define GPIO_PFC3_PFC312                        (0x1000u)
+#define GPIO_PFC3_PFC313                        (0x2000u)
+#define GPIO_PFC3_PFC314                        (0x4000u)
+#define GPIO_PFC3_PFC315                        (0x8000u)
+
+#define GPIO_PFCE3_PFCE30                       (0x0001u)
+#define GPIO_PFCE3_PFCE31                       (0x0002u)
+#define GPIO_PFCE3_PFCE32                       (0x0004u)
+#define GPIO_PFCE3_PFCE33                       (0x0008u)
+#define GPIO_PFCE3_PFCE34                       (0x0010u)
+#define GPIO_PFCE3_PFCE35                       (0x0020u)
+#define GPIO_PFCE3_PFCE36                       (0x0040u)
+#define GPIO_PFCE3_PFCE37                       (0x0080u)
+#define GPIO_PFCE3_PFCE38                       (0x0100u)
+#define GPIO_PFCE3_PFCE39                       (0x0200u)
+#define GPIO_PFCE3_PFCE310                      (0x0400u)
+#define GPIO_PFCE3_PFCE311                      (0x0800u)
+#define GPIO_PFCE3_PFCE312                      (0x1000u)
+#define GPIO_PFCE3_PFCE313                      (0x2000u)
+#define GPIO_PFCE3_PFCE314                      (0x4000u)
+#define GPIO_PFCE3_PFCE315                      (0x8000u)
+
+#define GPIO_PNOT3_PNOT30                       (0x0001u)
+#define GPIO_PNOT3_PNOT31                       (0x0002u)
+#define GPIO_PNOT3_PNOT32                       (0x0004u)
+#define GPIO_PNOT3_PNOT33                       (0x0008u)
+#define GPIO_PNOT3_PNOT34                       (0x0010u)
+#define GPIO_PNOT3_PNOT35                       (0x0020u)
+#define GPIO_PNOT3_PNOT36                       (0x0040u)
+#define GPIO_PNOT3_PNOT37                       (0x0080u)
+#define GPIO_PNOT3_PNOT38                       (0x0100u)
+#define GPIO_PNOT3_PNOT39                       (0x0200u)
+#define GPIO_PNOT3_PNOT310                      (0x0400u)
+#define GPIO_PNOT3_PNOT311                      (0x0800u)
+#define GPIO_PNOT3_PNOT312                      (0x1000u)
+#define GPIO_PNOT3_PNOT313                      (0x2000u)
+#define GPIO_PNOT3_PNOT314                      (0x4000u)
+#define GPIO_PNOT3_PNOT315                      (0x8000u)
+
+#define GPIO_PMSR3_PMSR30                       (0x00000001uL)
+#define GPIO_PMSR3_PMSR31                       (0x00000002uL)
+#define GPIO_PMSR3_PMSR32                       (0x00000004uL)
+#define GPIO_PMSR3_PMSR33                       (0x00000008uL)
+#define GPIO_PMSR3_PMSR34                       (0x00000010uL)
+#define GPIO_PMSR3_PMSR35                       (0x00000020uL)
+#define GPIO_PMSR3_PMSR36                       (0x00000040uL)
+#define GPIO_PMSR3_PMSR37                       (0x00000080uL)
+#define GPIO_PMSR3_PMSR38                       (0x00000100uL)
+#define GPIO_PMSR3_PMSR39                       (0x00000200uL)
+#define GPIO_PMSR3_PMSR310                      (0x00000400uL)
+#define GPIO_PMSR3_PMSR311                      (0x00000800uL)
+#define GPIO_PMSR3_PMSR312                      (0x00001000uL)
+#define GPIO_PMSR3_PMSR313                      (0x00002000uL)
+#define GPIO_PMSR3_PMSR314                      (0x00004000uL)
+#define GPIO_PMSR3_PMSR315                      (0x00008000uL)
+#define GPIO_PMSR3_PMSR316                      (0x00010000uL)
+#define GPIO_PMSR3_PMSR317                      (0x00020000uL)
+#define GPIO_PMSR3_PMSR318                      (0x00040000uL)
+#define GPIO_PMSR3_PMSR319                      (0x00080000uL)
+#define GPIO_PMSR3_PMSR320                      (0x00100000uL)
+#define GPIO_PMSR3_PMSR321                      (0x00200000uL)
+#define GPIO_PMSR3_PMSR322                      (0x00400000uL)
+#define GPIO_PMSR3_PMSR323                      (0x00800000uL)
+#define GPIO_PMSR3_PMSR324                      (0x01000000uL)
+#define GPIO_PMSR3_PMSR325                      (0x02000000uL)
+#define GPIO_PMSR3_PMSR326                      (0x04000000uL)
+#define GPIO_PMSR3_PMSR327                      (0x08000000uL)
+#define GPIO_PMSR3_PMSR328                      (0x10000000uL)
+#define GPIO_PMSR3_PMSR329                      (0x20000000uL)
+#define GPIO_PMSR3_PMSR330                      (0x40000000uL)
+#define GPIO_PMSR3_PMSR331                      (0x80000000uL)
+
+#define GPIO_PMCSR3_PMCSR30                     (0x00000001uL)
+#define GPIO_PMCSR3_PMCSR31                     (0x00000002uL)
+#define GPIO_PMCSR3_PMCSR32                     (0x00000004uL)
+#define GPIO_PMCSR3_PMCSR33                     (0x00000008uL)
+#define GPIO_PMCSR3_PMCSR34                     (0x00000010uL)
+#define GPIO_PMCSR3_PMCSR35                     (0x00000020uL)
+#define GPIO_PMCSR3_PMCSR36                     (0x00000040uL)
+#define GPIO_PMCSR3_PMCSR37                     (0x00000080uL)
+#define GPIO_PMCSR3_PMCSR38                     (0x00000100uL)
+#define GPIO_PMCSR3_PMCSR39                     (0x00000200uL)
+#define GPIO_PMCSR3_PMCSR310                    (0x00000400uL)
+#define GPIO_PMCSR3_PMCSR311                    (0x00000800uL)
+#define GPIO_PMCSR3_PMCSR312                    (0x00001000uL)
+#define GPIO_PMCSR3_PMCSR313                    (0x00002000uL)
+#define GPIO_PMCSR3_PMCSR314                    (0x00004000uL)
+#define GPIO_PMCSR3_PMCSR315                    (0x00008000uL)
+#define GPIO_PMCSR3_PMCSR316                    (0x00010000uL)
+#define GPIO_PMCSR3_PMCSR317                    (0x00020000uL)
+#define GPIO_PMCSR3_PMCSR318                    (0x00040000uL)
+#define GPIO_PMCSR3_PMCSR319                    (0x00080000uL)
+#define GPIO_PMCSR3_PMCSR320                    (0x00100000uL)
+#define GPIO_PMCSR3_PMCSR321                    (0x00200000uL)
+#define GPIO_PMCSR3_PMCSR322                    (0x00400000uL)
+#define GPIO_PMCSR3_PMCSR323                    (0x00800000uL)
+#define GPIO_PMCSR3_PMCSR324                    (0x01000000uL)
+#define GPIO_PMCSR3_PMCSR325                    (0x02000000uL)
+#define GPIO_PMCSR3_PMCSR326                    (0x04000000uL)
+#define GPIO_PMCSR3_PMCSR327                    (0x08000000uL)
+#define GPIO_PMCSR3_PMCSR328                    (0x10000000uL)
+#define GPIO_PMCSR3_PMCSR329                    (0x20000000uL)
+#define GPIO_PMCSR3_PMCSR330                    (0x40000000uL)
+#define GPIO_PMCSR3_PMCSR331                    (0x80000000uL)
+
+#define GPIO_PFCAE3_PFCAE30                     (0x0001u)
+#define GPIO_PFCAE3_PFCAE31                     (0x0002u)
+#define GPIO_PFCAE3_PFCAE32                     (0x0004u)
+#define GPIO_PFCAE3_PFCAE33                     (0x0008u)
+#define GPIO_PFCAE3_PFCAE34                     (0x0010u)
+#define GPIO_PFCAE3_PFCAE35                     (0x0020u)
+#define GPIO_PFCAE3_PFCAE36                     (0x0040u)
+#define GPIO_PFCAE3_PFCAE37                     (0x0080u)
+#define GPIO_PFCAE3_PFCAE38                     (0x0100u)
+#define GPIO_PFCAE3_PFCAE39                     (0x0200u)
+#define GPIO_PFCAE3_PFCAE310                    (0x0400u)
+#define GPIO_PFCAE3_PFCAE311                    (0x0800u)
+#define GPIO_PFCAE3_PFCAE312                    (0x1000u)
+#define GPIO_PFCAE3_PFCAE313                    (0x2000u)
+#define GPIO_PFCAE3_PFCAE314                    (0x4000u)
+#define GPIO_PFCAE3_PFCAE315                    (0x8000u)
+
+#define GPIO_PIBC3_PIBC30                       (0x0001u)
+#define GPIO_PIBC3_PIBC31                       (0x0002u)
+#define GPIO_PIBC3_PIBC32                       (0x0004u)
+#define GPIO_PIBC3_PIBC33                       (0x0008u)
+#define GPIO_PIBC3_PIBC34                       (0x0010u)
+#define GPIO_PIBC3_PIBC35                       (0x0020u)
+#define GPIO_PIBC3_PIBC36                       (0x0040u)
+#define GPIO_PIBC3_PIBC37                       (0x0080u)
+#define GPIO_PIBC3_PIBC38                       (0x0100u)
+#define GPIO_PIBC3_PIBC39                       (0x0200u)
+#define GPIO_PIBC3_PIBC310                      (0x0400u)
+#define GPIO_PIBC3_PIBC311                      (0x0800u)
+#define GPIO_PIBC3_PIBC312                      (0x1000u)
+#define GPIO_PIBC3_PIBC313                      (0x2000u)
+#define GPIO_PIBC3_PIBC314                      (0x4000u)
+#define GPIO_PIBC3_PIBC315                      (0x8000u)
+
+#define GPIO_PBDC3_PBDC30                       (0x0001u)
+#define GPIO_PBDC3_PBDC31                       (0x0002u)
+#define GPIO_PBDC3_PBDC32                       (0x0004u)
+#define GPIO_PBDC3_PBDC33                       (0x0008u)
+#define GPIO_PBDC3_PBDC34                       (0x0010u)
+#define GPIO_PBDC3_PBDC35                       (0x0020u)
+#define GPIO_PBDC3_PBDC36                       (0x0040u)
+#define GPIO_PBDC3_PBDC37                       (0x0080u)
+#define GPIO_PBDC3_PBDC38                       (0x0100u)
+#define GPIO_PBDC3_PBDC39                       (0x0200u)
+#define GPIO_PBDC3_PBDC310                      (0x0400u)
+#define GPIO_PBDC3_PBDC311                      (0x0800u)
+#define GPIO_PBDC3_PBDC312                      (0x1000u)
+#define GPIO_PBDC3_PBDC313                      (0x2000u)
+#define GPIO_PBDC3_PBDC314                      (0x4000u)
+#define GPIO_PBDC3_PBDC315                      (0x8000u)
+
+#define GPIO_PIPC3_PIPC30                       (0x0001u)
+#define GPIO_PIPC3_PIPC31                       (0x0002u)
+#define GPIO_PIPC3_PIPC32                       (0x0004u)
+#define GPIO_PIPC3_PIPC33                       (0x0008u)
+#define GPIO_PIPC3_PIPC34                       (0x0010u)
+#define GPIO_PIPC3_PIPC35                       (0x0020u)
+#define GPIO_PIPC3_PIPC36                       (0x0040u)
+#define GPIO_PIPC3_PIPC37                       (0x0080u)
+#define GPIO_PIPC3_PIPC38                       (0x0100u)
+#define GPIO_PIPC3_PIPC39                       (0x0200u)
+#define GPIO_PIPC3_PIPC310                      (0x0400u)
+#define GPIO_PIPC3_PIPC311                      (0x0800u)
+#define GPIO_PIPC3_PIPC312                      (0x1000u)
+#define GPIO_PIPC3_PIPC313                      (0x2000u)
+#define GPIO_PIPC3_PIPC314                      (0x4000u)
+#define GPIO_PIPC3_PIPC315                      (0x8000u)
+
+/* ---- P4 ---- */
+#define GPIO_P4_P40                             (0x0001u)
+#define GPIO_P4_P41                             (0x0002u)
+#define GPIO_P4_P42                             (0x0004u)
+#define GPIO_P4_P43                             (0x0008u)
+#define GPIO_P4_P44                             (0x0010u)
+#define GPIO_P4_P45                             (0x0020u)
+#define GPIO_P4_P46                             (0x0040u)
+#define GPIO_P4_P47                             (0x0080u)
+#define GPIO_P4_P48                             (0x0100u)
+#define GPIO_P4_P49                             (0x0200u)
+#define GPIO_P4_P410                            (0x0400u)
+#define GPIO_P4_P411                            (0x0800u)
+#define GPIO_P4_P412                            (0x1000u)
+#define GPIO_P4_P413                            (0x2000u)
+#define GPIO_P4_P414                            (0x4000u)
+#define GPIO_P4_P415                            (0x8000u)
+
+#define GPIO_PSR4_PSR40                         (0x00000001uL)
+#define GPIO_PSR4_PSR41                         (0x00000002uL)
+#define GPIO_PSR4_PSR42                         (0x00000004uL)
+#define GPIO_PSR4_PSR43                         (0x00000008uL)
+#define GPIO_PSR4_PSR44                         (0x00000010uL)
+#define GPIO_PSR4_PSR45                         (0x00000020uL)
+#define GPIO_PSR4_PSR46                         (0x00000040uL)
+#define GPIO_PSR4_PSR47                         (0x00000080uL)
+#define GPIO_PSR4_PSR48                         (0x00000100uL)
+#define GPIO_PSR4_PSR49                         (0x00000200uL)
+#define GPIO_PSR4_PSR410                        (0x00000400uL)
+#define GPIO_PSR4_PSR411                        (0x00000800uL)
+#define GPIO_PSR4_PSR412                        (0x00001000uL)
+#define GPIO_PSR4_PSR413                        (0x00002000uL)
+#define GPIO_PSR4_PSR414                        (0x00004000uL)
+#define GPIO_PSR4_PSR415                        (0x00008000uL)
+#define GPIO_PSR4_PSR416                        (0x00010000uL)
+#define GPIO_PSR4_PSR417                        (0x00020000uL)
+#define GPIO_PSR4_PSR418                        (0x00040000uL)
+#define GPIO_PSR4_PSR419                        (0x00080000uL)
+#define GPIO_PSR4_PSR420                        (0x00100000uL)
+#define GPIO_PSR4_PSR421                        (0x00200000uL)
+#define GPIO_PSR4_PSR422                        (0x00400000uL)
+#define GPIO_PSR4_PSR423                        (0x00800000uL)
+#define GPIO_PSR4_PSR424                        (0x01000000uL)
+#define GPIO_PSR4_PSR425                        (0x02000000uL)
+#define GPIO_PSR4_PSR426                        (0x04000000uL)
+#define GPIO_PSR4_PSR427                        (0x08000000uL)
+#define GPIO_PSR4_PSR428                        (0x10000000uL)
+#define GPIO_PSR4_PSR429                        (0x20000000uL)
+#define GPIO_PSR4_PSR430                        (0x40000000uL)
+#define GPIO_PSR4_PSR431                        (0x80000000uL)
+
+#define GPIO_PPR4_PPR40                         (0x0001u)
+#define GPIO_PPR4_PPR41                         (0x0002u)
+#define GPIO_PPR4_PPR42                         (0x0004u)
+#define GPIO_PPR4_PPR43                         (0x0008u)
+#define GPIO_PPR4_PPR44                         (0x0010u)
+#define GPIO_PPR4_PPR45                         (0x0020u)
+#define GPIO_PPR4_PPR46                         (0x0040u)
+#define GPIO_PPR4_PPR47                         (0x0080u)
+#define GPIO_PPR4_PPR48                         (0x0100u)
+#define GPIO_PPR4_PPR49                         (0x0200u)
+#define GPIO_PPR4_PPR410                        (0x0400u)
+#define GPIO_PPR4_PPR411                        (0x0800u)
+#define GPIO_PPR4_PPR412                        (0x1000u)
+#define GPIO_PPR4_PPR413                        (0x2000u)
+#define GPIO_PPR4_PPR414                        (0x4000u)
+#define GPIO_PPR4_PPR415                        (0x8000u)
+
+#define GPIO_PM4_PM40                           (0x0001u)
+#define GPIO_PM4_PM41                           (0x0002u)
+#define GPIO_PM4_PM42                           (0x0004u)
+#define GPIO_PM4_PM43                           (0x0008u)
+#define GPIO_PM4_PM44                           (0x0010u)
+#define GPIO_PM4_PM45                           (0x0020u)
+#define GPIO_PM4_PM46                           (0x0040u)
+#define GPIO_PM4_PM47                           (0x0080u)
+#define GPIO_PM4_PM48                           (0x0100u)
+#define GPIO_PM4_PM49                           (0x0200u)
+#define GPIO_PM4_PM410                          (0x0400u)
+#define GPIO_PM4_PM411                          (0x0800u)
+#define GPIO_PM4_PM412                          (0x1000u)
+#define GPIO_PM4_PM413                          (0x2000u)
+#define GPIO_PM4_PM414                          (0x4000u)
+#define GPIO_PM4_PM415                          (0x8000u)
+
+#define GPIO_PMC4_PMC40                         (0x0001u)
+#define GPIO_PMC4_PMC41                         (0x0002u)
+#define GPIO_PMC4_PMC42                         (0x0004u)
+#define GPIO_PMC4_PMC43                         (0x0008u)
+#define GPIO_PMC4_PMC44                         (0x0010u)
+#define GPIO_PMC4_PMC45                         (0x0020u)
+#define GPIO_PMC4_PMC46                         (0x0040u)
+#define GPIO_PMC4_PMC47                         (0x0080u)
+#define GPIO_PMC4_PMC48                         (0x0100u)
+#define GPIO_PMC4_PMC49                         (0x0200u)
+#define GPIO_PMC4_PMC410                        (0x0400u)
+#define GPIO_PMC4_PMC411                        (0x0800u)
+#define GPIO_PMC4_PMC412                        (0x1000u)
+#define GPIO_PMC4_PMC413                        (0x2000u)
+#define GPIO_PMC4_PMC414                        (0x4000u)
+#define GPIO_PMC4_PMC415                        (0x8000u)
+
+#define GPIO_PFC4_PFC40                         (0x0001u)
+#define GPIO_PFC4_PFC41                         (0x0002u)
+#define GPIO_PFC4_PFC42                         (0x0004u)
+#define GPIO_PFC4_PFC43                         (0x0008u)
+#define GPIO_PFC4_PFC44                         (0x0010u)
+#define GPIO_PFC4_PFC45                         (0x0020u)
+#define GPIO_PFC4_PFC46                         (0x0040u)
+#define GPIO_PFC4_PFC47                         (0x0080u)
+#define GPIO_PFC4_PFC48                         (0x0100u)
+#define GPIO_PFC4_PFC49                         (0x0200u)
+#define GPIO_PFC4_PFC410                        (0x0400u)
+#define GPIO_PFC4_PFC411                        (0x0800u)
+#define GPIO_PFC4_PFC412                        (0x1000u)
+#define GPIO_PFC4_PFC413                        (0x2000u)
+#define GPIO_PFC4_PFC414                        (0x4000u)
+#define GPIO_PFC4_PFC415                        (0x8000u)
+
+#define GPIO_PFCE4_PFCE40                       (0x0001u)
+#define GPIO_PFCE4_PFCE41                       (0x0002u)
+#define GPIO_PFCE4_PFCE42                       (0x0004u)
+#define GPIO_PFCE4_PFCE43                       (0x0008u)
+#define GPIO_PFCE4_PFCE44                       (0x0010u)
+#define GPIO_PFCE4_PFCE45                       (0x0020u)
+#define GPIO_PFCE4_PFCE46                       (0x0040u)
+#define GPIO_PFCE4_PFCE47                       (0x0080u)
+#define GPIO_PFCE4_PFCE48                       (0x0100u)
+#define GPIO_PFCE4_PFCE49                       (0x0200u)
+#define GPIO_PFCE4_PFCE410                      (0x0400u)
+#define GPIO_PFCE4_PFCE411                      (0x0800u)
+#define GPIO_PFCE4_PFCE412                      (0x1000u)
+#define GPIO_PFCE4_PFCE413                      (0x2000u)
+#define GPIO_PFCE4_PFCE414                      (0x4000u)
+#define GPIO_PFCE4_PFCE415                      (0x8000u)
+
+#define GPIO_PNOT4_PNOT40                       (0x0001u)
+#define GPIO_PNOT4_PNOT41                       (0x0002u)
+#define GPIO_PNOT4_PNOT42                       (0x0004u)
+#define GPIO_PNOT4_PNOT43                       (0x0008u)
+#define GPIO_PNOT4_PNOT44                       (0x0010u)
+#define GPIO_PNOT4_PNOT45                       (0x0020u)
+#define GPIO_PNOT4_PNOT46                       (0x0040u)
+#define GPIO_PNOT4_PNOT47                       (0x0080u)
+#define GPIO_PNOT4_PNOT48                       (0x0100u)
+#define GPIO_PNOT4_PNOT49                       (0x0200u)
+#define GPIO_PNOT4_PNOT410                      (0x0400u)
+#define GPIO_PNOT4_PNOT411                      (0x0800u)
+#define GPIO_PNOT4_PNOT412                      (0x1000u)
+#define GPIO_PNOT4_PNOT413                      (0x2000u)
+#define GPIO_PNOT4_PNOT414                      (0x4000u)
+#define GPIO_PNOT4_PNOT415                      (0x8000u)
+
+#define GPIO_PMSR4_PMSR40                       (0x00000001uL)
+#define GPIO_PMSR4_PMSR41                       (0x00000002uL)
+#define GPIO_PMSR4_PMSR42                       (0x00000004uL)
+#define GPIO_PMSR4_PMSR43                       (0x00000008uL)
+#define GPIO_PMSR4_PMSR44                       (0x00000010uL)
+#define GPIO_PMSR4_PMSR45                       (0x00000020uL)
+#define GPIO_PMSR4_PMSR46                       (0x00000040uL)
+#define GPIO_PMSR4_PMSR47                       (0x00000080uL)
+#define GPIO_PMSR4_PMSR48                       (0x00000100uL)
+#define GPIO_PMSR4_PMSR49                       (0x00000200uL)
+#define GPIO_PMSR4_PMSR410                      (0x00000400uL)
+#define GPIO_PMSR4_PMSR411                      (0x00000800uL)
+#define GPIO_PMSR4_PMSR412                      (0x00001000uL)
+#define GPIO_PMSR4_PMSR413                      (0x00002000uL)
+#define GPIO_PMSR4_PMSR414                      (0x00004000uL)
+#define GPIO_PMSR4_PMSR415                      (0x00008000uL)
+#define GPIO_PMSR4_PMSR416                      (0x00010000uL)
+#define GPIO_PMSR4_PMSR417                      (0x00020000uL)
+#define GPIO_PMSR4_PMSR418                      (0x00040000uL)
+#define GPIO_PMSR4_PMSR419                      (0x00080000uL)
+#define GPIO_PMSR4_PMSR420                      (0x00100000uL)
+#define GPIO_PMSR4_PMSR421                      (0x00200000uL)
+#define GPIO_PMSR4_PMSR422                      (0x00400000uL)
+#define GPIO_PMSR4_PMSR423                      (0x00800000uL)
+#define GPIO_PMSR4_PMSR424                      (0x01000000uL)
+#define GPIO_PMSR4_PMSR425                      (0x02000000uL)
+#define GPIO_PMSR4_PMSR426                      (0x04000000uL)
+#define GPIO_PMSR4_PMSR427                      (0x08000000uL)
+#define GPIO_PMSR4_PMSR428                      (0x10000000uL)
+#define GPIO_PMSR4_PMSR429                      (0x20000000uL)
+#define GPIO_PMSR4_PMSR430                      (0x40000000uL)
+#define GPIO_PMSR4_PMSR431                      (0x80000000uL)
+
+#define GPIO_PMCSR4_PMCSR40                     (0x00000001uL)
+#define GPIO_PMCSR4_PMCSR41                     (0x00000002uL)
+#define GPIO_PMCSR4_PMCSR42                     (0x00000004uL)
+#define GPIO_PMCSR4_PMCSR43                     (0x00000008uL)
+#define GPIO_PMCSR4_PMCSR44                     (0x00000010uL)
+#define GPIO_PMCSR4_PMCSR45                     (0x00000020uL)
+#define GPIO_PMCSR4_PMCSR46                     (0x00000040uL)
+#define GPIO_PMCSR4_PMCSR47                     (0x00000080uL)
+#define GPIO_PMCSR4_PMCSR48                     (0x00000100uL)
+#define GPIO_PMCSR4_PMCSR49                     (0x00000200uL)
+#define GPIO_PMCSR4_PMCSR410                    (0x00000400uL)
+#define GPIO_PMCSR4_PMCSR411                    (0x00000800uL)
+#define GPIO_PMCSR4_PMCSR412                    (0x00001000uL)
+#define GPIO_PMCSR4_PMCSR413                    (0x00002000uL)
+#define GPIO_PMCSR4_PMCSR414                    (0x00004000uL)
+#define GPIO_PMCSR4_PMCSR415                    (0x00008000uL)
+#define GPIO_PMCSR4_PMCSR416                    (0x00010000uL)
+#define GPIO_PMCSR4_PMCSR417                    (0x00020000uL)
+#define GPIO_PMCSR4_PMCSR418                    (0x00040000uL)
+#define GPIO_PMCSR4_PMCSR419                    (0x00080000uL)
+#define GPIO_PMCSR4_PMCSR420                    (0x00100000uL)
+#define GPIO_PMCSR4_PMCSR421                    (0x00200000uL)
+#define GPIO_PMCSR4_PMCSR422                    (0x00400000uL)
+#define GPIO_PMCSR4_PMCSR423                    (0x00800000uL)
+#define GPIO_PMCSR4_PMCSR424                    (0x01000000uL)
+#define GPIO_PMCSR4_PMCSR425                    (0x02000000uL)
+#define GPIO_PMCSR4_PMCSR426                    (0x04000000uL)
+#define GPIO_PMCSR4_PMCSR427                    (0x08000000uL)
+#define GPIO_PMCSR4_PMCSR428                    (0x10000000uL)
+#define GPIO_PMCSR4_PMCSR429                    (0x20000000uL)
+#define GPIO_PMCSR4_PMCSR430                    (0x40000000uL)
+#define GPIO_PMCSR4_PMCSR431                    (0x80000000uL)
+
+#define GPIO_PFCAE4_PFCAE40                     (0x0001u)
+#define GPIO_PFCAE4_PFCAE41                     (0x0002u)
+#define GPIO_PFCAE4_PFCAE42                     (0x0004u)
+#define GPIO_PFCAE4_PFCAE43                     (0x0008u)
+#define GPIO_PFCAE4_PFCAE44                     (0x0010u)
+#define GPIO_PFCAE4_PFCAE45                     (0x0020u)
+#define GPIO_PFCAE4_PFCAE46                     (0x0040u)
+#define GPIO_PFCAE4_PFCAE47                     (0x0080u)
+#define GPIO_PFCAE4_PFCAE48                     (0x0100u)
+#define GPIO_PFCAE4_PFCAE49                     (0x0200u)
+#define GPIO_PFCAE4_PFCAE410                    (0x0400u)
+#define GPIO_PFCAE4_PFCAE411                    (0x0800u)
+#define GPIO_PFCAE4_PFCAE412                    (0x1000u)
+#define GPIO_PFCAE4_PFCAE413                    (0x2000u)
+#define GPIO_PFCAE4_PFCAE414                    (0x4000u)
+#define GPIO_PFCAE4_PFCAE415                    (0x8000u)
+
+#define GPIO_PIBC4_PIBC40                       (0x0001u)
+#define GPIO_PIBC4_PIBC41                       (0x0002u)
+#define GPIO_PIBC4_PIBC42                       (0x0004u)
+#define GPIO_PIBC4_PIBC43                       (0x0008u)
+#define GPIO_PIBC4_PIBC44                       (0x0010u)
+#define GPIO_PIBC4_PIBC45                       (0x0020u)
+#define GPIO_PIBC4_PIBC46                       (0x0040u)
+#define GPIO_PIBC4_PIBC47                       (0x0080u)
+#define GPIO_PIBC4_PIBC48                       (0x0100u)
+#define GPIO_PIBC4_PIBC49                       (0x0200u)
+#define GPIO_PIBC4_PIBC410                      (0x0400u)
+#define GPIO_PIBC4_PIBC411                      (0x0800u)
+#define GPIO_PIBC4_PIBC412                      (0x1000u)
+#define GPIO_PIBC4_PIBC413                      (0x2000u)
+#define GPIO_PIBC4_PIBC414                      (0x4000u)
+#define GPIO_PIBC4_PIBC415                      (0x8000u)
+
+#define GPIO_PBDC4_PBDC40                       (0x0001u)
+#define GPIO_PBDC4_PBDC41                       (0x0002u)
+#define GPIO_PBDC4_PBDC42                       (0x0004u)
+#define GPIO_PBDC4_PBDC43                       (0x0008u)
+#define GPIO_PBDC4_PBDC44                       (0x0010u)
+#define GPIO_PBDC4_PBDC45                       (0x0020u)
+#define GPIO_PBDC4_PBDC46                       (0x0040u)
+#define GPIO_PBDC4_PBDC47                       (0x0080u)
+#define GPIO_PBDC4_PBDC48                       (0x0100u)
+#define GPIO_PBDC4_PBDC49                       (0x0200u)
+#define GPIO_PBDC4_PBDC410                      (0x0400u)
+#define GPIO_PBDC4_PBDC411                      (0x0800u)
+#define GPIO_PBDC4_PBDC412                      (0x1000u)
+#define GPIO_PBDC4_PBDC413                      (0x2000u)
+#define GPIO_PBDC4_PBDC414                      (0x4000u)
+#define GPIO_PBDC4_PBDC415                      (0x8000u)
+
+#define GPIO_PIPC4_PIPC40                       (0x0001u)
+#define GPIO_PIPC4_PIPC41                       (0x0002u)
+#define GPIO_PIPC4_PIPC42                       (0x0004u)
+#define GPIO_PIPC4_PIPC43                       (0x0008u)
+#define GPIO_PIPC4_PIPC44                       (0x0010u)
+#define GPIO_PIPC4_PIPC45                       (0x0020u)
+#define GPIO_PIPC4_PIPC46                       (0x0040u)
+#define GPIO_PIPC4_PIPC47                       (0x0080u)
+#define GPIO_PIPC4_PIPC48                       (0x0100u)
+#define GPIO_PIPC4_PIPC49                       (0x0200u)
+#define GPIO_PIPC4_PIPC410                      (0x0400u)
+#define GPIO_PIPC4_PIPC411                      (0x0800u)
+#define GPIO_PIPC4_PIPC412                      (0x1000u)
+#define GPIO_PIPC4_PIPC413                      (0x2000u)
+#define GPIO_PIPC4_PIPC414                      (0x4000u)
+#define GPIO_PIPC4_PIPC415                      (0x8000u)
+
+/* ---- P5 ---- */
+#define GPIO_P5_P50                             (0x0001u)
+#define GPIO_P5_P51                             (0x0002u)
+#define GPIO_P5_P52                             (0x0004u)
+#define GPIO_P5_P53                             (0x0008u)
+#define GPIO_P5_P54                             (0x0010u)
+#define GPIO_P5_P55                             (0x0020u)
+#define GPIO_P5_P56                             (0x0040u)
+#define GPIO_P5_P57                             (0x0080u)
+#define GPIO_P5_P58                             (0x0100u)
+#define GPIO_P5_P59                             (0x0200u)
+#define GPIO_P5_P510                            (0x0400u)
+
+#define GPIO_PSR5_PSR50                         (0x00000001uL)
+#define GPIO_PSR5_PSR51                         (0x00000002uL)
+#define GPIO_PSR5_PSR52                         (0x00000004uL)
+#define GPIO_PSR5_PSR53                         (0x00000008uL)
+#define GPIO_PSR5_PSR54                         (0x00000010uL)
+#define GPIO_PSR5_PSR55                         (0x00000020uL)
+#define GPIO_PSR5_PSR56                         (0x00000040uL)
+#define GPIO_PSR5_PSR57                         (0x00000080uL)
+#define GPIO_PSR5_PSR58                         (0x00000100uL)
+#define GPIO_PSR5_PSR59                         (0x00000200uL)
+#define GPIO_PSR5_PSR510                        (0x00000400uL)
+#define GPIO_PSR5_PSR516                        (0x00010000uL)
+#define GPIO_PSR5_PSR517                        (0x00020000uL)
+#define GPIO_PSR5_PSR518                        (0x00040000uL)
+#define GPIO_PSR5_PSR519                        (0x00080000uL)
+#define GPIO_PSR5_PSR520                        (0x00100000uL)
+#define GPIO_PSR5_PSR521                        (0x00200000uL)
+#define GPIO_PSR5_PSR522                        (0x00400000uL)
+#define GPIO_PSR5_PSR523                        (0x00800000uL)
+#define GPIO_PSR5_PSR524                        (0x01000000uL)
+#define GPIO_PSR5_PSR525                        (0x02000000uL)
+#define GPIO_PSR5_PSR526                        (0x04000000uL)
+
+#define GPIO_PPR5_PPR50                         (0x0001u)
+#define GPIO_PPR5_PPR51                         (0x0002u)
+#define GPIO_PPR5_PPR52                         (0x0004u)
+#define GPIO_PPR5_PPR53                         (0x0008u)
+#define GPIO_PPR5_PPR54                         (0x0010u)
+#define GPIO_PPR5_PPR55                         (0x0020u)
+#define GPIO_PPR5_PPR56                         (0x0040u)
+#define GPIO_PPR5_PPR57                         (0x0080u)
+#define GPIO_PPR5_PPR58                         (0x0100u)
+#define GPIO_PPR5_PPR59                         (0x0200u)
+#define GPIO_PPR5_PPR510                        (0x0400u)
+
+#define GPIO_PM5_PM50                           (0x0001u)
+#define GPIO_PM5_PM51                           (0x0002u)
+#define GPIO_PM5_PM52                           (0x0004u)
+#define GPIO_PM5_PM53                           (0x0008u)
+#define GPIO_PM5_PM54                           (0x0010u)
+#define GPIO_PM5_PM55                           (0x0020u)
+#define GPIO_PM5_PM56                           (0x0040u)
+#define GPIO_PM5_PM57                           (0x0080u)
+#define GPIO_PM5_PM58                           (0x0100u)
+#define GPIO_PM5_PM59                           (0x0200u)
+#define GPIO_PM5_PM510                          (0x0400u)
+
+#define GPIO_PMC5_PMC50                         (0x0001u)
+#define GPIO_PMC5_PMC51                         (0x0002u)
+#define GPIO_PMC5_PMC52                         (0x0004u)
+#define GPIO_PMC5_PMC53                         (0x0008u)
+#define GPIO_PMC5_PMC54                         (0x0010u)
+#define GPIO_PMC5_PMC55                         (0x0020u)
+#define GPIO_PMC5_PMC56                         (0x0040u)
+#define GPIO_PMC5_PMC57                         (0x0080u)
+#define GPIO_PMC5_PMC58                         (0x0100u)
+#define GPIO_PMC5_PMC59                         (0x0200u)
+#define GPIO_PMC5_PMC510                        (0x0400u)
+
+#define GPIO_PFC5_PFC50                         (0x0001u)
+#define GPIO_PFC5_PFC51                         (0x0002u)
+#define GPIO_PFC5_PFC52                         (0x0004u)
+#define GPIO_PFC5_PFC53                         (0x0008u)
+#define GPIO_PFC5_PFC54                         (0x0010u)
+#define GPIO_PFC5_PFC55                         (0x0020u)
+#define GPIO_PFC5_PFC56                         (0x0040u)
+#define GPIO_PFC5_PFC57                         (0x0080u)
+#define GPIO_PFC5_PFC58                         (0x0100u)
+#define GPIO_PFC5_PFC59                         (0x0200u)
+#define GPIO_PFC5_PFC510                        (0x0400u)
+
+#define GPIO_PFCE5_PFCE50                       (0x0001u)
+#define GPIO_PFCE5_PFCE51                       (0x0002u)
+#define GPIO_PFCE5_PFCE52                       (0x0004u)
+#define GPIO_PFCE5_PFCE53                       (0x0008u)
+#define GPIO_PFCE5_PFCE54                       (0x0010u)
+#define GPIO_PFCE5_PFCE55                       (0x0020u)
+#define GPIO_PFCE5_PFCE56                       (0x0040u)
+#define GPIO_PFCE5_PFCE57                       (0x0080u)
+#define GPIO_PFCE5_PFCE58                       (0x0100u)
+#define GPIO_PFCE5_PFCE59                       (0x0200u)
+#define GPIO_PFCE5_PFCE510                      (0x0400u)
+
+#define GPIO_PNOT5_PNOT50                       (0x0001u)
+#define GPIO_PNOT5_PNOT51                       (0x0002u)
+#define GPIO_PNOT5_PNOT52                       (0x0004u)
+#define GPIO_PNOT5_PNOT53                       (0x0008u)
+#define GPIO_PNOT5_PNOT54                       (0x0010u)
+#define GPIO_PNOT5_PNOT55                       (0x0020u)
+#define GPIO_PNOT5_PNOT56                       (0x0040u)
+#define GPIO_PNOT5_PNOT57                       (0x0080u)
+#define GPIO_PNOT5_PNOT58                       (0x0100u)
+#define GPIO_PNOT5_PNOT59                       (0x0200u)
+#define GPIO_PNOT5_PNOT510                      (0x0400u)
+
+#define GPIO_PMSR5_PMSR50                       (0x00000001uL)
+#define GPIO_PMSR5_PMSR51                       (0x00000002uL)
+#define GPIO_PMSR5_PMSR52                       (0x00000004uL)
+#define GPIO_PMSR5_PMSR53                       (0x00000008uL)
+#define GPIO_PMSR5_PMSR54                       (0x00000010uL)
+#define GPIO_PMSR5_PMSR55                       (0x00000020uL)
+#define GPIO_PMSR5_PMSR56                       (0x00000040uL)
+#define GPIO_PMSR5_PMSR57                       (0x00000080uL)
+#define GPIO_PMSR5_PMSR58                       (0x00000100uL)
+#define GPIO_PMSR5_PMSR59                       (0x00000200uL)
+#define GPIO_PMSR5_PMSR510                      (0x00000400uL)
+#define GPIO_PMSR5_PMSR516                      (0x00010000uL)
+#define GPIO_PMSR5_PMSR517                      (0x00020000uL)
+#define GPIO_PMSR5_PMSR518                      (0x00040000uL)
+#define GPIO_PMSR5_PMSR519                      (0x00080000uL)
+#define GPIO_PMSR5_PMSR520                      (0x00100000uL)
+#define GPIO_PMSR5_PMSR521                      (0x00200000uL)
+#define GPIO_PMSR5_PMSR522                      (0x00400000uL)
+#define GPIO_PMSR5_PMSR523                      (0x00800000uL)
+#define GPIO_PMSR5_PMSR524                      (0x01000000uL)
+#define GPIO_PMSR5_PMSR525                      (0x02000000uL)
+#define GPIO_PMSR5_PMSR526                      (0x04000000uL)
+
+#define GPIO_PMCSR5_PMCSR50                     (0x00000001uL)
+#define GPIO_PMCSR5_PMCSR51                     (0x00000002uL)
+#define GPIO_PMCSR5_PMCSR52                     (0x00000004uL)
+#define GPIO_PMCSR5_PMCSR53                     (0x00000008uL)
+#define GPIO_PMCSR5_PMCSR54                     (0x00000010uL)
+#define GPIO_PMCSR5_PMCSR55                     (0x00000020uL)
+#define GPIO_PMCSR5_PMCSR56                     (0x00000040uL)
+#define GPIO_PMCSR5_PMCSR57                     (0x00000080uL)
+#define GPIO_PMCSR5_PMCSR58                     (0x00000100uL)
+#define GPIO_PMCSR5_PMCSR59                     (0x00000200uL)
+#define GPIO_PMCSR5_PMCSR510                    (0x00000400uL)
+#define GPIO_PMCSR5_PMCSR516                    (0x00010000uL)
+#define GPIO_PMCSR5_PMCSR517                    (0x00020000uL)
+#define GPIO_PMCSR5_PMCSR518                    (0x00040000uL)
+#define GPIO_PMCSR5_PMCSR519                    (0x00080000uL)
+#define GPIO_PMCSR5_PMCSR520                    (0x00100000uL)
+#define GPIO_PMCSR5_PMCSR521                    (0x00200000uL)
+#define GPIO_PMCSR5_PMCSR522                    (0x00400000uL)
+#define GPIO_PMCSR5_PMCSR523                    (0x00800000uL)
+#define GPIO_PMCSR5_PMCSR524                    (0x01000000uL)
+#define GPIO_PMCSR5_PMCSR525                    (0x02000000uL)
+#define GPIO_PMCSR5_PMCSR526                    (0x04000000uL)
+
+#define GPIO_PFCAE5_PFCAE50                     (0x0001u)
+#define GPIO_PFCAE5_PFCAE51                     (0x0002u)
+#define GPIO_PFCAE5_PFCAE52                     (0x0004u)
+#define GPIO_PFCAE5_PFCAE53                     (0x0008u)
+#define GPIO_PFCAE5_PFCAE54                     (0x0010u)
+#define GPIO_PFCAE5_PFCAE55                     (0x0020u)
+#define GPIO_PFCAE5_PFCAE56                     (0x0040u)
+#define GPIO_PFCAE5_PFCAE57                     (0x0080u)
+#define GPIO_PFCAE5_PFCAE58                     (0x0100u)
+#define GPIO_PFCAE5_PFCAE59                     (0x0200u)
+#define GPIO_PFCAE5_PFCAE510                    (0x0400u)
+
+#define GPIO_PIBC5_PIBC50                       (0x0001u)
+#define GPIO_PIBC5_PIBC51                       (0x0002u)
+#define GPIO_PIBC5_PIBC52                       (0x0004u)
+#define GPIO_PIBC5_PIBC53                       (0x0008u)
+#define GPIO_PIBC5_PIBC54                       (0x0010u)
+#define GPIO_PIBC5_PIBC55                       (0x0020u)
+#define GPIO_PIBC5_PIBC56                       (0x0040u)
+#define GPIO_PIBC5_PIBC57                       (0x0080u)
+#define GPIO_PIBC5_PIBC58                       (0x0100u)
+#define GPIO_PIBC5_PIBC59                       (0x0200u)
+#define GPIO_PIBC5_PIBC510                      (0x0400u)
+
+#define GPIO_PBDC5_PBDC50                       (0x0001u)
+#define GPIO_PBDC5_PBDC51                       (0x0002u)
+#define GPIO_PBDC5_PBDC52                       (0x0004u)
+#define GPIO_PBDC5_PBDC53                       (0x0008u)
+#define GPIO_PBDC5_PBDC54                       (0x0010u)
+#define GPIO_PBDC5_PBDC55                       (0x0020u)
+#define GPIO_PBDC5_PBDC56                       (0x0040u)
+#define GPIO_PBDC5_PBDC57                       (0x0080u)
+#define GPIO_PBDC5_PBDC58                       (0x0100u)
+#define GPIO_PBDC5_PBDC59                       (0x0200u)
+#define GPIO_PBDC5_PBDC510                      (0x0400u)
+
+#define GPIO_PIPC5_PIPC50                       (0x0001u)
+#define GPIO_PIPC5_PIPC51                       (0x0002u)
+#define GPIO_PIPC5_PIPC52                       (0x0004u)
+#define GPIO_PIPC5_PIPC53                       (0x0008u)
+#define GPIO_PIPC5_PIPC54                       (0x0010u)
+#define GPIO_PIPC5_PIPC55                       (0x0020u)
+#define GPIO_PIPC5_PIPC56                       (0x0040u)
+#define GPIO_PIPC5_PIPC57                       (0x0080u)
+#define GPIO_PIPC5_PIPC58                       (0x0100u)
+#define GPIO_PIPC5_PIPC59                       (0x0200u)
+#define GPIO_PIPC5_PIPC510                      (0x0400u)
+
+/* ---- P6 ---- */
+#define GPIO_P6_P60                             (0x0001u)
+#define GPIO_P6_P61                             (0x0002u)
+#define GPIO_P6_P62                             (0x0004u)
+#define GPIO_P6_P63                             (0x0008u)
+#define GPIO_P6_P64                             (0x0010u)
+#define GPIO_P6_P65                             (0x0020u)
+#define GPIO_P6_P66                             (0x0040u)
+#define GPIO_P6_P67                             (0x0080u)
+#define GPIO_P6_P68                             (0x0100u)
+#define GPIO_P6_P69                             (0x0200u)
+#define GPIO_P6_P610                            (0x0400u)
+#define GPIO_P6_P611                            (0x0800u)
+#define GPIO_P6_P612                            (0x1000u)
+#define GPIO_P6_P613                            (0x2000u)
+#define GPIO_P6_P614                            (0x4000u)
+#define GPIO_P6_P615                            (0x8000u)
+
+#define GPIO_PSR6_PSR60                         (0x00000001uL)
+#define GPIO_PSR6_PSR61                         (0x00000002uL)
+#define GPIO_PSR6_PSR62                         (0x00000004uL)
+#define GPIO_PSR6_PSR63                         (0x00000008uL)
+#define GPIO_PSR6_PSR64                         (0x00000010uL)
+#define GPIO_PSR6_PSR65                         (0x00000020uL)
+#define GPIO_PSR6_PSR66                         (0x00000040uL)
+#define GPIO_PSR6_PSR67                         (0x00000080uL)
+#define GPIO_PSR6_PSR68                         (0x00000100uL)
+#define GPIO_PSR6_PSR69                         (0x00000200uL)
+#define GPIO_PSR6_PSR610                        (0x00000400uL)
+#define GPIO_PSR6_PSR611                        (0x00000800uL)
+#define GPIO_PSR6_PSR612                        (0x00001000uL)
+#define GPIO_PSR6_PSR613                        (0x00002000uL)
+#define GPIO_PSR6_PSR614                        (0x00004000uL)
+#define GPIO_PSR6_PSR615                        (0x00008000uL)
+#define GPIO_PSR6_PSR616                        (0x00010000uL)
+#define GPIO_PSR6_PSR617                        (0x00020000uL)
+#define GPIO_PSR6_PSR618                        (0x00040000uL)
+#define GPIO_PSR6_PSR619                        (0x00080000uL)
+#define GPIO_PSR6_PSR620                        (0x00100000uL)
+#define GPIO_PSR6_PSR621                        (0x00200000uL)
+#define GPIO_PSR6_PSR622                        (0x00400000uL)
+#define GPIO_PSR6_PSR623                        (0x00800000uL)
+#define GPIO_PSR6_PSR624                        (0x01000000uL)
+#define GPIO_PSR6_PSR625                        (0x02000000uL)
+#define GPIO_PSR6_PSR626                        (0x04000000uL)
+#define GPIO_PSR6_PSR627                        (0x08000000uL)
+#define GPIO_PSR6_PSR628                        (0x10000000uL)
+#define GPIO_PSR6_PSR629                        (0x20000000uL)
+#define GPIO_PSR6_PSR630                        (0x40000000uL)
+#define GPIO_PSR6_PSR631                        (0x80000000uL)
+
+#define GPIO_PPR6_PPR60                         (0x0001u)
+#define GPIO_PPR6_PPR61                         (0x0002u)
+#define GPIO_PPR6_PPR62                         (0x0004u)
+#define GPIO_PPR6_PPR63                         (0x0008u)
+#define GPIO_PPR6_PPR64                         (0x0010u)
+#define GPIO_PPR6_PPR65                         (0x0020u)
+#define GPIO_PPR6_PPR66                         (0x0040u)
+#define GPIO_PPR6_PPR67                         (0x0080u)
+#define GPIO_PPR6_PPR68                         (0x0100u)
+#define GPIO_PPR6_PPR69                         (0x0200u)
+#define GPIO_PPR6_PPR610                        (0x0400u)
+#define GPIO_PPR6_PPR611                        (0x0800u)
+#define GPIO_PPR6_PPR612                        (0x1000u)
+#define GPIO_PPR6_PPR613                        (0x2000u)
+#define GPIO_PPR6_PPR614                        (0x4000u)
+#define GPIO_PPR6_PPR615                        (0x8000u)
+
+#define GPIO_PM6_PM60                           (0x0001u)
+#define GPIO_PM6_PM61                           (0x0002u)
+#define GPIO_PM6_PM62                           (0x0004u)
+#define GPIO_PM6_PM63                           (0x0008u)
+#define GPIO_PM6_PM64                           (0x0010u)
+#define GPIO_PM6_PM65                           (0x0020u)
+#define GPIO_PM6_PM66                           (0x0040u)
+#define GPIO_PM6_PM67                           (0x0080u)
+#define GPIO_PM6_PM68                           (0x0100u)
+#define GPIO_PM6_PM69                           (0x0200u)
+#define GPIO_PM6_PM610                          (0x0400u)
+#define GPIO_PM6_PM611                          (0x0800u)
+#define GPIO_PM6_PM612                          (0x1000u)
+#define GPIO_PM6_PM613                          (0x2000u)
+#define GPIO_PM6_PM614                          (0x4000u)
+#define GPIO_PM6_PM615                          (0x8000u)
+
+#define GPIO_PMC6_PMC60                         (0x0001u)
+#define GPIO_PMC6_PMC61                         (0x0002u)
+#define GPIO_PMC6_PMC62                         (0x0004u)
+#define GPIO_PMC6_PMC63                         (0x0008u)
+#define GPIO_PMC6_PMC64                         (0x0010u)
+#define GPIO_PMC6_PMC65                         (0x0020u)
+#define GPIO_PMC6_PMC66                         (0x0040u)
+#define GPIO_PMC6_PMC67                         (0x0080u)
+#define GPIO_PMC6_PMC68                         (0x0100u)
+#define GPIO_PMC6_PMC69                         (0x0200u)
+#define GPIO_PMC6_PMC610                        (0x0400u)
+#define GPIO_PMC6_PMC611                        (0x0800u)
+#define GPIO_PMC6_PMC612                        (0x1000u)
+#define GPIO_PMC6_PMC613                        (0x2000u)
+#define GPIO_PMC6_PMC614                        (0x4000u)
+#define GPIO_PMC6_PMC615                        (0x8000u)
+
+#define GPIO_PFC6_PFC60                         (0x0001u)
+#define GPIO_PFC6_PFC61                         (0x0002u)
+#define GPIO_PFC6_PFC62                         (0x0004u)
+#define GPIO_PFC6_PFC63                         (0x0008u)
+#define GPIO_PFC6_PFC64                         (0x0010u)
+#define GPIO_PFC6_PFC65                         (0x0020u)
+#define GPIO_PFC6_PFC66                         (0x0040u)
+#define GPIO_PFC6_PFC67                         (0x0080u)
+#define GPIO_PFC6_PFC68                         (0x0100u)
+#define GPIO_PFC6_PFC69                         (0x0200u)
+#define GPIO_PFC6_PFC610                        (0x0400u)
+#define GPIO_PFC6_PFC611                        (0x0800u)
+#define GPIO_PFC6_PFC612                        (0x1000u)
+#define GPIO_PFC6_PFC613                        (0x2000u)
+#define GPIO_PFC6_PFC614                        (0x4000u)
+#define GPIO_PFC6_PFC615                        (0x8000u)
+
+#define GPIO_PFCE6_PFCE60                       (0x0001u)
+#define GPIO_PFCE6_PFCE61                       (0x0002u)
+#define GPIO_PFCE6_PFCE62                       (0x0004u)
+#define GPIO_PFCE6_PFCE63                       (0x0008u)
+#define GPIO_PFCE6_PFCE64                       (0x0010u)
+#define GPIO_PFCE6_PFCE65                       (0x0020u)
+#define GPIO_PFCE6_PFCE66                       (0x0040u)
+#define GPIO_PFCE6_PFCE67                       (0x0080u)
+#define GPIO_PFCE6_PFCE68                       (0x0100u)
+#define GPIO_PFCE6_PFCE69                       (0x0200u)
+#define GPIO_PFCE6_PFCE610                      (0x0400u)
+#define GPIO_PFCE6_PFCE611                      (0x0800u)
+#define GPIO_PFCE6_PFCE612                      (0x1000u)
+#define GPIO_PFCE6_PFCE613                      (0x2000u)
+#define GPIO_PFCE6_PFCE614                      (0x4000u)
+#define GPIO_PFCE6_PFCE615                      (0x8000u)
+
+#define GPIO_PNOT6_PNOT60                       (0x0001u)
+#define GPIO_PNOT6_PNOT61                       (0x0002u)
+#define GPIO_PNOT6_PNOT62                       (0x0004u)
+#define GPIO_PNOT6_PNOT63                       (0x0008u)
+#define GPIO_PNOT6_PNOT64                       (0x0010u)
+#define GPIO_PNOT6_PNOT65                       (0x0020u)
+#define GPIO_PNOT6_PNOT66                       (0x0040u)
+#define GPIO_PNOT6_PNOT67                       (0x0080u)
+#define GPIO_PNOT6_PNOT68                       (0x0100u)
+#define GPIO_PNOT6_PNOT69                       (0x0200u)
+#define GPIO_PNOT6_PNOT610                      (0x0400u)
+#define GPIO_PNOT6_PNOT611                      (0x0800u)
+#define GPIO_PNOT6_PNOT612                      (0x1000u)
+#define GPIO_PNOT6_PNOT613                      (0x2000u)
+#define GPIO_PNOT6_PNOT614                      (0x4000u)
+#define GPIO_PNOT6_PNOT615                      (0x8000u)
+
+#define GPIO_PMSR6_PMSR60                       (0x00000001uL)
+#define GPIO_PMSR6_PMSR61                       (0x00000002uL)
+#define GPIO_PMSR6_PMSR62                       (0x00000004uL)
+#define GPIO_PMSR6_PMSR63                       (0x00000008uL)
+#define GPIO_PMSR6_PMSR64                       (0x00000010uL)
+#define GPIO_PMSR6_PMSR65                       (0x00000020uL)
+#define GPIO_PMSR6_PMSR66                       (0x00000040uL)
+#define GPIO_PMSR6_PMSR67                       (0x00000080uL)
+#define GPIO_PMSR6_PMSR68                       (0x00000100uL)
+#define GPIO_PMSR6_PMSR69                       (0x00000200uL)
+#define GPIO_PMSR6_PMSR610                      (0x00000400uL)
+#define GPIO_PMSR6_PMSR611                      (0x00000800uL)
+#define GPIO_PMSR6_PMSR612                      (0x00001000uL)
+#define GPIO_PMSR6_PMSR613                      (0x00002000uL)
+#define GPIO_PMSR6_PMSR614                      (0x00004000uL)
+#define GPIO_PMSR6_PMSR615                      (0x00008000uL)
+#define GPIO_PMSR6_PMSR616                      (0x00010000uL)
+#define GPIO_PMSR6_PMSR617                      (0x00020000uL)
+#define GPIO_PMSR6_PMSR618                      (0x00040000uL)
+#define GPIO_PMSR6_PMSR619                      (0x00080000uL)
+#define GPIO_PMSR6_PMSR620                      (0x00100000uL)
+#define GPIO_PMSR6_PMSR621                      (0x00200000uL)
+#define GPIO_PMSR6_PMSR622                      (0x00400000uL)
+#define GPIO_PMSR6_PMSR623                      (0x00800000uL)
+#define GPIO_PMSR6_PMSR624                      (0x01000000uL)
+#define GPIO_PMSR6_PMSR625                      (0x02000000uL)
+#define GPIO_PMSR6_PMSR626                      (0x04000000uL)
+#define GPIO_PMSR6_PMSR627                      (0x08000000uL)
+#define GPIO_PMSR6_PMSR628                      (0x10000000uL)
+#define GPIO_PMSR6_PMSR629                      (0x20000000uL)
+#define GPIO_PMSR6_PMSR630                      (0x40000000uL)
+#define GPIO_PMSR6_PMSR631                      (0x80000000uL)
+
+#define GPIO_PMCSR6_PMCSR60                     (0x00000001uL)
+#define GPIO_PMCSR6_PMCSR61                     (0x00000002uL)
+#define GPIO_PMCSR6_PMCSR62                     (0x00000004uL)
+#define GPIO_PMCSR6_PMCSR63                     (0x00000008uL)
+#define GPIO_PMCSR6_PMCSR64                     (0x00000010uL)
+#define GPIO_PMCSR6_PMCSR65                     (0x00000020uL)
+#define GPIO_PMCSR6_PMCSR66                     (0x00000040uL)
+#define GPIO_PMCSR6_PMCSR67                     (0x00000080uL)
+#define GPIO_PMCSR6_PMCSR68                     (0x00000100uL)
+#define GPIO_PMCSR6_PMCSR69                     (0x00000200uL)
+#define GPIO_PMCSR6_PMCSR610                    (0x00000400uL)
+#define GPIO_PMCSR6_PMCSR611                    (0x00000800uL)
+#define GPIO_PMCSR6_PMCSR612                    (0x00001000uL)
+#define GPIO_PMCSR6_PMCSR613                    (0x00002000uL)
+#define GPIO_PMCSR6_PMCSR614                    (0x00004000uL)
+#define GPIO_PMCSR6_PMCSR615                    (0x00008000uL)
+#define GPIO_PMCSR6_PMCSR616                    (0x00010000uL)
+#define GPIO_PMCSR6_PMCSR617                    (0x00020000uL)
+#define GPIO_PMCSR6_PMCSR618                    (0x00040000uL)
+#define GPIO_PMCSR6_PMCSR619                    (0x00080000uL)
+#define GPIO_PMCSR6_PMCSR620                    (0x00100000uL)
+#define GPIO_PMCSR6_PMCSR621                    (0x00200000uL)
+#define GPIO_PMCSR6_PMCSR622                    (0x00400000uL)
+#define GPIO_PMCSR6_PMCSR623                    (0x00800000uL)
+#define GPIO_PMCSR6_PMCSR624                    (0x01000000uL)
+#define GPIO_PMCSR6_PMCSR625                    (0x02000000uL)
+#define GPIO_PMCSR6_PMCSR626                    (0x04000000uL)
+#define GPIO_PMCSR6_PMCSR627                    (0x08000000uL)
+#define GPIO_PMCSR6_PMCSR628                    (0x10000000uL)
+#define GPIO_PMCSR6_PMCSR629                    (0x20000000uL)
+#define GPIO_PMCSR6_PMCSR630                    (0x40000000uL)
+#define GPIO_PMCSR6_PMCSR631                    (0x80000000uL)
+
+#define GPIO_PFCAE6_PFCAE60                     (0x0001u)
+#define GPIO_PFCAE6_PFCAE61                     (0x0002u)
+#define GPIO_PFCAE6_PFCAE62                     (0x0004u)
+#define GPIO_PFCAE6_PFCAE63                     (0x0008u)
+#define GPIO_PFCAE6_PFCAE64                     (0x0010u)
+#define GPIO_PFCAE6_PFCAE65                     (0x0020u)
+#define GPIO_PFCAE6_PFCAE66                     (0x0040u)
+#define GPIO_PFCAE6_PFCAE67                     (0x0080u)
+#define GPIO_PFCAE6_PFCAE68                     (0x0100u)
+#define GPIO_PFCAE6_PFCAE69                     (0x0200u)
+#define GPIO_PFCAE6_PFCAE610                    (0x0400u)
+#define GPIO_PFCAE6_PFCAE611                    (0x0800u)
+#define GPIO_PFCAE6_PFCAE612                    (0x1000u)
+#define GPIO_PFCAE6_PFCAE613                    (0x2000u)
+#define GPIO_PFCAE6_PFCAE614                    (0x4000u)
+#define GPIO_PFCAE6_PFCAE615                    (0x8000u)
+
+#define GPIO_PIBC6_PIBC60                       (0x0001u)
+#define GPIO_PIBC6_PIBC61                       (0x0002u)
+#define GPIO_PIBC6_PIBC62                       (0x0004u)
+#define GPIO_PIBC6_PIBC63                       (0x0008u)
+#define GPIO_PIBC6_PIBC64                       (0x0010u)
+#define GPIO_PIBC6_PIBC65                       (0x0020u)
+#define GPIO_PIBC6_PIBC66                       (0x0040u)
+#define GPIO_PIBC6_PIBC67                       (0x0080u)
+#define GPIO_PIBC6_PIBC68                       (0x0100u)
+#define GPIO_PIBC6_PIBC69                       (0x0200u)
+#define GPIO_PIBC6_PIBC610                      (0x0400u)
+#define GPIO_PIBC6_PIBC611                      (0x0800u)
+#define GPIO_PIBC6_PIBC612                      (0x1000u)
+#define GPIO_PIBC6_PIBC613                      (0x2000u)
+#define GPIO_PIBC6_PIBC614                      (0x4000u)
+#define GPIO_PIBC6_PIBC615                      (0x8000u)
+
+#define GPIO_PBDC6_PBDC60                       (0x0001u)
+#define GPIO_PBDC6_PBDC61                       (0x0002u)
+#define GPIO_PBDC6_PBDC62                       (0x0004u)
+#define GPIO_PBDC6_PBDC63                       (0x0008u)
+#define GPIO_PBDC6_PBDC64                       (0x0010u)
+#define GPIO_PBDC6_PBDC65                       (0x0020u)
+#define GPIO_PBDC6_PBDC66                       (0x0040u)
+#define GPIO_PBDC6_PBDC67                       (0x0080u)
+#define GPIO_PBDC6_PBDC68                       (0x0100u)
+#define GPIO_PBDC6_PBDC69                       (0x0200u)
+#define GPIO_PBDC6_PBDC610                      (0x0400u)
+#define GPIO_PBDC6_PBDC611                      (0x0800u)
+#define GPIO_PBDC6_PBDC612                      (0x1000u)
+#define GPIO_PBDC6_PBDC613                      (0x2000u)
+#define GPIO_PBDC6_PBDC614                      (0x4000u)
+#define GPIO_PBDC6_PBDC615                      (0x8000u)
+
+#define GPIO_PIPC6_PIPC60                       (0x0001u)
+#define GPIO_PIPC6_PIPC61                       (0x0002u)
+#define GPIO_PIPC6_PIPC62                       (0x0004u)
+#define GPIO_PIPC6_PIPC63                       (0x0008u)
+#define GPIO_PIPC6_PIPC64                       (0x0010u)
+#define GPIO_PIPC6_PIPC65                       (0x0020u)
+#define GPIO_PIPC6_PIPC66                       (0x0040u)
+#define GPIO_PIPC6_PIPC67                       (0x0080u)
+#define GPIO_PIPC6_PIPC68                       (0x0100u)
+#define GPIO_PIPC6_PIPC69                       (0x0200u)
+#define GPIO_PIPC6_PIPC610                      (0x0400u)
+#define GPIO_PIPC6_PIPC611                      (0x0800u)
+#define GPIO_PIPC6_PIPC612                      (0x1000u)
+#define GPIO_PIPC6_PIPC613                      (0x2000u)
+#define GPIO_PIPC6_PIPC614                      (0x4000u)
+#define GPIO_PIPC6_PIPC615                      (0x8000u)
+
+/* ---- P7 ---- */
+#define GPIO_P7_P70                             (0x0001u)
+#define GPIO_P7_P71                             (0x0002u)
+#define GPIO_P7_P72                             (0x0004u)
+#define GPIO_P7_P73                             (0x0008u)
+#define GPIO_P7_P74                             (0x0010u)
+#define GPIO_P7_P75                             (0x0020u)
+#define GPIO_P7_P76                             (0x0040u)
+#define GPIO_P7_P77                             (0x0080u)
+#define GPIO_P7_P78                             (0x0100u)
+#define GPIO_P7_P79                             (0x0200u)
+#define GPIO_P7_P710                            (0x0400u)
+#define GPIO_P7_P711                            (0x0800u)
+#define GPIO_P7_P712                            (0x1000u)
+#define GPIO_P7_P713                            (0x2000u)
+#define GPIO_P7_P714                            (0x4000u)
+#define GPIO_P7_P715                            (0x8000u)
+
+#define GPIO_PSR7_PSR70                         (0x00000001uL)
+#define GPIO_PSR7_PSR71                         (0x00000002uL)
+#define GPIO_PSR7_PSR72                         (0x00000004uL)
+#define GPIO_PSR7_PSR73                         (0x00000008uL)
+#define GPIO_PSR7_PSR74                         (0x00000010uL)
+#define GPIO_PSR7_PSR75                         (0x00000020uL)
+#define GPIO_PSR7_PSR76                         (0x00000040uL)
+#define GPIO_PSR7_PSR77                         (0x00000080uL)
+#define GPIO_PSR7_PSR78                         (0x00000100uL)
+#define GPIO_PSR7_PSR79                         (0x00000200uL)
+#define GPIO_PSR7_PSR710                        (0x00000400uL)
+#define GPIO_PSR7_PSR711                        (0x00000800uL)
+#define GPIO_PSR7_PSR712                        (0x00001000uL)
+#define GPIO_PSR7_PSR713                        (0x00002000uL)
+#define GPIO_PSR7_PSR714                        (0x00004000uL)
+#define GPIO_PSR7_PSR715                        (0x00008000uL)
+#define GPIO_PSR7_PSR716                        (0x00010000uL)
+#define GPIO_PSR7_PSR717                        (0x00020000uL)
+#define GPIO_PSR7_PSR718                        (0x00040000uL)
+#define GPIO_PSR7_PSR719                        (0x00080000uL)
+#define GPIO_PSR7_PSR720                        (0x00100000uL)
+#define GPIO_PSR7_PSR721                        (0x00200000uL)
+#define GPIO_PSR7_PSR722                        (0x00400000uL)
+#define GPIO_PSR7_PSR723                        (0x00800000uL)
+#define GPIO_PSR7_PSR724                        (0x01000000uL)
+#define GPIO_PSR7_PSR725                        (0x02000000uL)
+#define GPIO_PSR7_PSR726                        (0x04000000uL)
+#define GPIO_PSR7_PSR727                        (0x08000000uL)
+#define GPIO_PSR7_PSR728                        (0x10000000uL)
+#define GPIO_PSR7_PSR729                        (0x20000000uL)
+#define GPIO_PSR7_PSR730                        (0x40000000uL)
+#define GPIO_PSR7_PSR731                        (0x80000000uL)
+
+#define GPIO_PPR7_PPR70                         (0x0001u)
+#define GPIO_PPR7_PPR71                         (0x0002u)
+#define GPIO_PPR7_PPR72                         (0x0004u)
+#define GPIO_PPR7_PPR73                         (0x0008u)
+#define GPIO_PPR7_PPR74                         (0x0010u)
+#define GPIO_PPR7_PPR75                         (0x0020u)
+#define GPIO_PPR7_PPR76                         (0x0040u)
+#define GPIO_PPR7_PPR77                         (0x0080u)
+#define GPIO_PPR7_PPR78                         (0x0100u)
+#define GPIO_PPR7_PPR79                         (0x0200u)
+#define GPIO_PPR7_PPR710                        (0x0400u)
+#define GPIO_PPR7_PPR711                        (0x0800u)
+#define GPIO_PPR7_PPR712                        (0x1000u)
+#define GPIO_PPR7_PPR713                        (0x2000u)
+#define GPIO_PPR7_PPR714                        (0x4000u)
+#define GPIO_PPR7_PPR715                        (0x8000u)
+
+#define GPIO_PM7_PM70                           (0x0001u)
+#define GPIO_PM7_PM71                           (0x0002u)
+#define GPIO_PM7_PM72                           (0x0004u)
+#define GPIO_PM7_PM73                           (0x0008u)
+#define GPIO_PM7_PM74                           (0x0010u)
+#define GPIO_PM7_PM75                           (0x0020u)
+#define GPIO_PM7_PM76                           (0x0040u)
+#define GPIO_PM7_PM77                           (0x0080u)
+#define GPIO_PM7_PM78                           (0x0100u)
+#define GPIO_PM7_PM79                           (0x0200u)
+#define GPIO_PM7_PM710                          (0x0400u)
+#define GPIO_PM7_PM711                          (0x0800u)
+#define GPIO_PM7_PM712                          (0x1000u)
+#define GPIO_PM7_PM713                          (0x2000u)
+#define GPIO_PM7_PM714                          (0x4000u)
+#define GPIO_PM7_PM715                          (0x8000u)
+
+#define GPIO_PMC7_PMC70                         (0x0001u)
+#define GPIO_PMC7_PMC71                         (0x0002u)
+#define GPIO_PMC7_PMC72                         (0x0004u)
+#define GPIO_PMC7_PMC73                         (0x0008u)
+#define GPIO_PMC7_PMC74                         (0x0010u)
+#define GPIO_PMC7_PMC75                         (0x0020u)
+#define GPIO_PMC7_PMC76                         (0x0040u)
+#define GPIO_PMC7_PMC77                         (0x0080u)
+#define GPIO_PMC7_PMC78                         (0x0100u)
+#define GPIO_PMC7_PMC79                         (0x0200u)
+#define GPIO_PMC7_PMC710                        (0x0400u)
+#define GPIO_PMC7_PMC711                        (0x0800u)
+#define GPIO_PMC7_PMC712                        (0x1000u)
+#define GPIO_PMC7_PMC713                        (0x2000u)
+#define GPIO_PMC7_PMC714                        (0x4000u)
+#define GPIO_PMC7_PMC715                        (0x8000u)
+
+#define GPIO_PFC7_PFC70                         (0x0001u)
+#define GPIO_PFC7_PFC71                         (0x0002u)
+#define GPIO_PFC7_PFC72                         (0x0004u)
+#define GPIO_PFC7_PFC73                         (0x0008u)
+#define GPIO_PFC7_PFC74                         (0x0010u)
+#define GPIO_PFC7_PFC75                         (0x0020u)
+#define GPIO_PFC7_PFC76                         (0x0040u)
+#define GPIO_PFC7_PFC77                         (0x0080u)
+#define GPIO_PFC7_PFC78                         (0x0100u)
+#define GPIO_PFC7_PFC79                         (0x0200u)
+#define GPIO_PFC7_PFC710                        (0x0400u)
+#define GPIO_PFC7_PFC711                        (0x0800u)
+#define GPIO_PFC7_PFC712                        (0x1000u)
+#define GPIO_PFC7_PFC713                        (0x2000u)
+#define GPIO_PFC7_PFC714                        (0x4000u)
+#define GPIO_PFC7_PFC715                        (0x8000u)
+
+#define GPIO_PFCE7_PFCE70                       (0x0001u)
+#define GPIO_PFCE7_PFCE71                       (0x0002u)
+#define GPIO_PFCE7_PFCE72                       (0x0004u)
+#define GPIO_PFCE7_PFCE73                       (0x0008u)
+#define GPIO_PFCE7_PFCE74                       (0x0010u)
+#define GPIO_PFCE7_PFCE75                       (0x0020u)
+#define GPIO_PFCE7_PFCE76                       (0x0040u)
+#define GPIO_PFCE7_PFCE77                       (0x0080u)
+#define GPIO_PFCE7_PFCE78                       (0x0100u)
+#define GPIO_PFCE7_PFCE79                       (0x0200u)
+#define GPIO_PFCE7_PFCE710                      (0x0400u)
+#define GPIO_PFCE7_PFCE711                      (0x0800u)
+#define GPIO_PFCE7_PFCE712                      (0x1000u)
+#define GPIO_PFCE7_PFCE713                      (0x2000u)
+#define GPIO_PFCE7_PFCE714                      (0x4000u)
+#define GPIO_PFCE7_PFCE715                      (0x8000u)
+
+#define GPIO_PNOT7_PNOT70                       (0x0001u)
+#define GPIO_PNOT7_PNOT71                       (0x0002u)
+#define GPIO_PNOT7_PNOT72                       (0x0004u)
+#define GPIO_PNOT7_PNOT73                       (0x0008u)
+#define GPIO_PNOT7_PNOT74                       (0x0010u)
+#define GPIO_PNOT7_PNOT75                       (0x0020u)
+#define GPIO_PNOT7_PNOT76                       (0x0040u)
+#define GPIO_PNOT7_PNOT77                       (0x0080u)
+#define GPIO_PNOT7_PNOT78                       (0x0100u)
+#define GPIO_PNOT7_PNOT79                       (0x0200u)
+#define GPIO_PNOT7_PNOT710                      (0x0400u)
+#define GPIO_PNOT7_PNOT711                      (0x0800u)
+#define GPIO_PNOT7_PNOT712                      (0x1000u)
+#define GPIO_PNOT7_PNOT713                      (0x2000u)
+#define GPIO_PNOT7_PNOT714                      (0x4000u)
+#define GPIO_PNOT7_PNOT715                      (0x8000u)
+
+#define GPIO_PMSR7_PMSR70                       (0x00000001uL)
+#define GPIO_PMSR7_PMSR71                       (0x00000002uL)
+#define GPIO_PMSR7_PMSR72                       (0x00000004uL)
+#define GPIO_PMSR7_PMSR73                       (0x00000008uL)
+#define GPIO_PMSR7_PMSR74                       (0x00000010uL)
+#define GPIO_PMSR7_PMSR75                       (0x00000020uL)
+#define GPIO_PMSR7_PMSR76                       (0x00000040uL)
+#define GPIO_PMSR7_PMSR77                       (0x00000080uL)
+#define GPIO_PMSR7_PMSR78                       (0x00000100uL)
+#define GPIO_PMSR7_PMSR79                       (0x00000200uL)
+#define GPIO_PMSR7_PMSR710                      (0x00000400uL)
+#define GPIO_PMSR7_PMSR711                      (0x00000800uL)
+#define GPIO_PMSR7_PMSR712                      (0x00001000uL)
+#define GPIO_PMSR7_PMSR713                      (0x00002000uL)
+#define GPIO_PMSR7_PMSR714                      (0x00004000uL)
+#define GPIO_PMSR7_PMSR715                      (0x00008000uL)
+#define GPIO_PMSR7_PMSR716                      (0x00010000uL)
+#define GPIO_PMSR7_PMSR717                      (0x00020000uL)
+#define GPIO_PMSR7_PMSR718                      (0x00040000uL)
+#define GPIO_PMSR7_PMSR719                      (0x00080000uL)
+#define GPIO_PMSR7_PMSR720                      (0x00100000uL)
+#define GPIO_PMSR7_PMSR721                      (0x00200000uL)
+#define GPIO_PMSR7_PMSR722                      (0x00400000uL)
+#define GPIO_PMSR7_PMSR723                      (0x00800000uL)
+#define GPIO_PMSR7_PMSR724                      (0x01000000uL)
+#define GPIO_PMSR7_PMSR725                      (0x02000000uL)
+#define GPIO_PMSR7_PMSR726                      (0x04000000uL)
+#define GPIO_PMSR7_PMSR727                      (0x08000000uL)
+#define GPIO_PMSR7_PMSR728                      (0x10000000uL)
+#define GPIO_PMSR7_PMSR729                      (0x20000000uL)
+#define GPIO_PMSR7_PMSR730                      (0x40000000uL)
+#define GPIO_PMSR7_PMSR731                      (0x80000000uL)
+
+#define GPIO_PMCSR7_PMCSR70                     (0x00000001uL)
+#define GPIO_PMCSR7_PMCSR71                     (0x00000002uL)
+#define GPIO_PMCSR7_PMCSR72                     (0x00000004uL)
+#define GPIO_PMCSR7_PMCSR73                     (0x00000008uL)
+#define GPIO_PMCSR7_PMCSR74                     (0x00000010uL)
+#define GPIO_PMCSR7_PMCSR75                     (0x00000020uL)
+#define GPIO_PMCSR7_PMCSR76                     (0x00000040uL)
+#define GPIO_PMCSR7_PMCSR77                     (0x00000080uL)
+#define GPIO_PMCSR7_PMCSR78                     (0x00000100uL)
+#define GPIO_PMCSR7_PMCSR79                     (0x00000200uL)
+#define GPIO_PMCSR7_PMCSR710                    (0x00000400uL)
+#define GPIO_PMCSR7_PMCSR711                    (0x00000800uL)
+#define GPIO_PMCSR7_PMCSR712                    (0x00001000uL)
+#define GPIO_PMCSR7_PMCSR713                    (0x00002000uL)
+#define GPIO_PMCSR7_PMCSR714                    (0x00004000uL)
+#define GPIO_PMCSR7_PMCSR715                    (0x00008000uL)
+#define GPIO_PMCSR7_PMCSR716                    (0x00010000uL)
+#define GPIO_PMCSR7_PMCSR717                    (0x00020000uL)
+#define GPIO_PMCSR7_PMCSR718                    (0x00040000uL)
+#define GPIO_PMCSR7_PMCSR719                    (0x00080000uL)
+#define GPIO_PMCSR7_PMCSR720                    (0x00100000uL)
+#define GPIO_PMCSR7_PMCSR721                    (0x00200000uL)
+#define GPIO_PMCSR7_PMCSR722                    (0x00400000uL)
+#define GPIO_PMCSR7_PMCSR723                    (0x00800000uL)
+#define GPIO_PMCSR7_PMCSR724                    (0x01000000uL)
+#define GPIO_PMCSR7_PMCSR725                    (0x02000000uL)
+#define GPIO_PMCSR7_PMCSR726                    (0x04000000uL)
+#define GPIO_PMCSR7_PMCSR727                    (0x08000000uL)
+#define GPIO_PMCSR7_PMCSR728                    (0x10000000uL)
+#define GPIO_PMCSR7_PMCSR729                    (0x20000000uL)
+#define GPIO_PMCSR7_PMCSR730                    (0x40000000uL)
+#define GPIO_PMCSR7_PMCSR731                    (0x80000000uL)
+
+#define GPIO_PFCAE7_PFCAE70                     (0x0001u)
+#define GPIO_PFCAE7_PFCAE71                     (0x0002u)
+#define GPIO_PFCAE7_PFCAE72                     (0x0004u)
+#define GPIO_PFCAE7_PFCAE73                     (0x0008u)
+#define GPIO_PFCAE7_PFCAE74                     (0x0010u)
+#define GPIO_PFCAE7_PFCAE75                     (0x0020u)
+#define GPIO_PFCAE7_PFCAE76                     (0x0040u)
+#define GPIO_PFCAE7_PFCAE77                     (0x0080u)
+#define GPIO_PFCAE7_PFCAE78                     (0x0100u)
+#define GPIO_PFCAE7_PFCAE79                     (0x0200u)
+#define GPIO_PFCAE7_PFCAE710                    (0x0400u)
+#define GPIO_PFCAE7_PFCAE711                    (0x0800u)
+#define GPIO_PFCAE7_PFCAE712                    (0x1000u)
+#define GPIO_PFCAE7_PFCAE713                    (0x2000u)
+#define GPIO_PFCAE7_PFCAE714                    (0x4000u)
+#define GPIO_PFCAE7_PFCAE715                    (0x8000u)
+
+#define GPIO_PIBC7_PIBC70                       (0x0001u)
+#define GPIO_PIBC7_PIBC71                       (0x0002u)
+#define GPIO_PIBC7_PIBC72                       (0x0004u)
+#define GPIO_PIBC7_PIBC73                       (0x0008u)
+#define GPIO_PIBC7_PIBC74                       (0x0010u)
+#define GPIO_PIBC7_PIBC75                       (0x0020u)
+#define GPIO_PIBC7_PIBC76                       (0x0040u)
+#define GPIO_PIBC7_PIBC77                       (0x0080u)
+#define GPIO_PIBC7_PIBC78                       (0x0100u)
+#define GPIO_PIBC7_PIBC79                       (0x0200u)
+#define GPIO_PIBC7_PIBC710                      (0x0400u)
+#define GPIO_PIBC7_PIBC711                      (0x0800u)
+#define GPIO_PIBC7_PIBC712                      (0x1000u)
+#define GPIO_PIBC7_PIBC713                      (0x2000u)
+#define GPIO_PIBC7_PIBC714                      (0x4000u)
+#define GPIO_PIBC7_PIBC715                      (0x8000u)
+
+#define GPIO_PBDC7_PBDC70                       (0x0001u)
+#define GPIO_PBDC7_PBDC71                       (0x0002u)
+#define GPIO_PBDC7_PBDC72                       (0x0004u)
+#define GPIO_PBDC7_PBDC73                       (0x0008u)
+#define GPIO_PBDC7_PBDC74                       (0x0010u)
+#define GPIO_PBDC7_PBDC75                       (0x0020u)
+#define GPIO_PBDC7_PBDC76                       (0x0040u)
+#define GPIO_PBDC7_PBDC77                       (0x0080u)
+#define GPIO_PBDC7_PBDC78                       (0x0100u)
+#define GPIO_PBDC7_PBDC79                       (0x0200u)
+#define GPIO_PBDC7_PBDC710                      (0x0400u)
+#define GPIO_PBDC7_PBDC711                      (0x0800u)
+#define GPIO_PBDC7_PBDC712                      (0x1000u)
+#define GPIO_PBDC7_PBDC713                      (0x2000u)
+#define GPIO_PBDC7_PBDC714                      (0x4000u)
+#define GPIO_PBDC7_PBDC715                      (0x8000u)
+
+#define GPIO_PIPC7_PIPC70                       (0x0001u)
+#define GPIO_PIPC7_PIPC71                       (0x0002u)
+#define GPIO_PIPC7_PIPC72                       (0x0004u)
+#define GPIO_PIPC7_PIPC73                       (0x0008u)
+#define GPIO_PIPC7_PIPC74                       (0x0010u)
+#define GPIO_PIPC7_PIPC75                       (0x0020u)
+#define GPIO_PIPC7_PIPC76                       (0x0040u)
+#define GPIO_PIPC7_PIPC77                       (0x0080u)
+#define GPIO_PIPC7_PIPC78                       (0x0100u)
+#define GPIO_PIPC7_PIPC79                       (0x0200u)
+#define GPIO_PIPC7_PIPC710                      (0x0400u)
+#define GPIO_PIPC7_PIPC711                      (0x0800u)
+#define GPIO_PIPC7_PIPC712                      (0x1000u)
+#define GPIO_PIPC7_PIPC713                      (0x2000u)
+#define GPIO_PIPC7_PIPC714                      (0x4000u)
+#define GPIO_PIPC7_PIPC715                      (0x8000u)
+
+/* ---- P8 ---- */
+#define GPIO_P8_P80                             (0x0001u)
+#define GPIO_P8_P81                             (0x0002u)
+#define GPIO_P8_P82                             (0x0004u)
+#define GPIO_P8_P83                             (0x0008u)
+#define GPIO_P8_P84                             (0x0010u)
+#define GPIO_P8_P85                             (0x0020u)
+#define GPIO_P8_P86                             (0x0040u)
+#define GPIO_P8_P87                             (0x0080u)
+#define GPIO_P8_P88                             (0x0100u)
+#define GPIO_P8_P89                             (0x0200u)
+#define GPIO_P8_P810                            (0x0400u)
+#define GPIO_P8_P811                            (0x0800u)
+#define GPIO_P8_P812                            (0x1000u)
+#define GPIO_P8_P813                            (0x2000u)
+#define GPIO_P8_P814                            (0x4000u)
+#define GPIO_P8_P815                            (0x8000u)
+
+#define GPIO_PSR8_PSR80                         (0x00000001uL)
+#define GPIO_PSR8_PSR81                         (0x00000002uL)
+#define GPIO_PSR8_PSR82                         (0x00000004uL)
+#define GPIO_PSR8_PSR83                         (0x00000008uL)
+#define GPIO_PSR8_PSR84                         (0x00000010uL)
+#define GPIO_PSR8_PSR85                         (0x00000020uL)
+#define GPIO_PSR8_PSR86                         (0x00000040uL)
+#define GPIO_PSR8_PSR87                         (0x00000080uL)
+#define GPIO_PSR8_PSR88                         (0x00000100uL)
+#define GPIO_PSR8_PSR89                         (0x00000200uL)
+#define GPIO_PSR8_PSR810                        (0x00000400uL)
+#define GPIO_PSR8_PSR811                        (0x00000800uL)
+#define GPIO_PSR8_PSR812                        (0x00001000uL)
+#define GPIO_PSR8_PSR813                        (0x00002000uL)
+#define GPIO_PSR8_PSR814                        (0x00004000uL)
+#define GPIO_PSR8_PSR815                        (0x00008000uL)
+#define GPIO_PSR8_PSR816                        (0x00010000uL)
+#define GPIO_PSR8_PSR817                        (0x00020000uL)
+#define GPIO_PSR8_PSR818                        (0x00040000uL)
+#define GPIO_PSR8_PSR819                        (0x00080000uL)
+#define GPIO_PSR8_PSR820                        (0x00100000uL)
+#define GPIO_PSR8_PSR821                        (0x00200000uL)
+#define GPIO_PSR8_PSR822                        (0x00400000uL)
+#define GPIO_PSR8_PSR823                        (0x00800000uL)
+#define GPIO_PSR8_PSR824                        (0x01000000uL)
+#define GPIO_PSR8_PSR825                        (0x02000000uL)
+#define GPIO_PSR8_PSR826                        (0x04000000uL)
+#define GPIO_PSR8_PSR827                        (0x08000000uL)
+#define GPIO_PSR8_PSR828                        (0x10000000uL)
+#define GPIO_PSR8_PSR829                        (0x20000000uL)
+#define GPIO_PSR8_PSR830                        (0x40000000uL)
+#define GPIO_PSR8_PSR831                        (0x80000000uL)
+
+#define GPIO_PPR8_PPR80                         (0x0001u)
+#define GPIO_PPR8_PPR81                         (0x0002u)
+#define GPIO_PPR8_PPR82                         (0x0004u)
+#define GPIO_PPR8_PPR83                         (0x0008u)
+#define GPIO_PPR8_PPR84                         (0x0010u)
+#define GPIO_PPR8_PPR85                         (0x0020u)
+#define GPIO_PPR8_PPR86                         (0x0040u)
+#define GPIO_PPR8_PPR87                         (0x0080u)
+#define GPIO_PPR8_PPR88                         (0x0100u)
+#define GPIO_PPR8_PPR89                         (0x0200u)
+#define GPIO_PPR8_PPR810                        (0x0400u)
+#define GPIO_PPR8_PPR811                        (0x0800u)
+#define GPIO_PPR8_PPR812                        (0x1000u)
+#define GPIO_PPR8_PPR813                        (0x2000u)
+#define GPIO_PPR8_PPR814                        (0x4000u)
+#define GPIO_PPR8_PPR815                        (0x8000u)
+
+#define GPIO_PM8_PM80                           (0x0001u)
+#define GPIO_PM8_PM81                           (0x0002u)
+#define GPIO_PM8_PM82                           (0x0004u)
+#define GPIO_PM8_PM83                           (0x0008u)
+#define GPIO_PM8_PM84                           (0x0010u)
+#define GPIO_PM8_PM85                           (0x0020u)
+#define GPIO_PM8_PM86                           (0x0040u)
+#define GPIO_PM8_PM87                           (0x0080u)
+#define GPIO_PM8_PM88                           (0x0100u)
+#define GPIO_PM8_PM89                           (0x0200u)
+#define GPIO_PM8_PM810                          (0x0400u)
+#define GPIO_PM8_PM811                          (0x0800u)
+#define GPIO_PM8_PM812                          (0x1000u)
+#define GPIO_PM8_PM813                          (0x2000u)
+#define GPIO_PM8_PM814                          (0x4000u)
+#define GPIO_PM8_PM815                          (0x8000u)
+
+#define GPIO_PMC8_PMC80                         (0x0001u)
+#define GPIO_PMC8_PMC81                         (0x0002u)
+#define GPIO_PMC8_PMC82                         (0x0004u)
+#define GPIO_PMC8_PMC83                         (0x0008u)
+#define GPIO_PMC8_PMC84                         (0x0010u)
+#define GPIO_PMC8_PMC85                         (0x0020u)
+#define GPIO_PMC8_PMC86                         (0x0040u)
+#define GPIO_PMC8_PMC87                         (0x0080u)
+#define GPIO_PMC8_PMC88                         (0x0100u)
+#define GPIO_PMC8_PMC89                         (0x0200u)
+#define GPIO_PMC8_PMC810                        (0x0400u)
+#define GPIO_PMC8_PMC811                        (0x0800u)
+#define GPIO_PMC8_PMC812                        (0x1000u)
+#define GPIO_PMC8_PMC813                        (0x2000u)
+#define GPIO_PMC8_PMC814                        (0x4000u)
+#define GPIO_PMC8_PMC815                        (0x8000u)
+
+#define GPIO_PFC8_PFC80                         (0x0001u)
+#define GPIO_PFC8_PFC81                         (0x0002u)
+#define GPIO_PFC8_PFC82                         (0x0004u)
+#define GPIO_PFC8_PFC83                         (0x0008u)
+#define GPIO_PFC8_PFC84                         (0x0010u)
+#define GPIO_PFC8_PFC85                         (0x0020u)
+#define GPIO_PFC8_PFC86                         (0x0040u)
+#define GPIO_PFC8_PFC87                         (0x0080u)
+#define GPIO_PFC8_PFC88                         (0x0100u)
+#define GPIO_PFC8_PFC89                         (0x0200u)
+#define GPIO_PFC8_PFC810                        (0x0400u)
+#define GPIO_PFC8_PFC811                        (0x0800u)
+#define GPIO_PFC8_PFC812                        (0x1000u)
+#define GPIO_PFC8_PFC813                        (0x2000u)
+#define GPIO_PFC8_PFC814                        (0x4000u)
+#define GPIO_PFC8_PFC815                        (0x8000u)
+
+#define GPIO_PFCE8_PFCE80                       (0x0001u)
+#define GPIO_PFCE8_PFCE81                       (0x0002u)
+#define GPIO_PFCE8_PFCE82                       (0x0004u)
+#define GPIO_PFCE8_PFCE83                       (0x0008u)
+#define GPIO_PFCE8_PFCE84                       (0x0010u)
+#define GPIO_PFCE8_PFCE85                       (0x0020u)
+#define GPIO_PFCE8_PFCE86                       (0x0040u)
+#define GPIO_PFCE8_PFCE87                       (0x0080u)
+#define GPIO_PFCE8_PFCE88                       (0x0100u)
+#define GPIO_PFCE8_PFCE89                       (0x0200u)
+#define GPIO_PFCE8_PFCE810                      (0x0400u)
+#define GPIO_PFCE8_PFCE811                      (0x0800u)
+#define GPIO_PFCE8_PFCE812                      (0x1000u)
+#define GPIO_PFCE8_PFCE813                      (0x2000u)
+#define GPIO_PFCE8_PFCE814                      (0x4000u)
+#define GPIO_PFCE8_PFCE815                      (0x8000u)
+
+#define GPIO_PNOT8_PNOT80                       (0x0001u)
+#define GPIO_PNOT8_PNOT81                       (0x0002u)
+#define GPIO_PNOT8_PNOT82                       (0x0004u)
+#define GPIO_PNOT8_PNOT83                       (0x0008u)
+#define GPIO_PNOT8_PNOT84                       (0x0010u)
+#define GPIO_PNOT8_PNOT85                       (0x0020u)
+#define GPIO_PNOT8_PNOT86                       (0x0040u)
+#define GPIO_PNOT8_PNOT87                       (0x0080u)
+#define GPIO_PNOT8_PNOT88                       (0x0100u)
+#define GPIO_PNOT8_PNOT89                       (0x0200u)
+#define GPIO_PNOT8_PNOT810                      (0x0400u)
+#define GPIO_PNOT8_PNOT811                      (0x0800u)
+#define GPIO_PNOT8_PNOT812                      (0x1000u)
+#define GPIO_PNOT8_PNOT813                      (0x2000u)
+#define GPIO_PNOT8_PNOT814                      (0x4000u)
+#define GPIO_PNOT8_PNOT815                      (0x8000u)
+
+#define GPIO_PMSR8_PMSR80                       (0x00000001uL)
+#define GPIO_PMSR8_PMSR81                       (0x00000002uL)
+#define GPIO_PMSR8_PMSR82                       (0x00000004uL)
+#define GPIO_PMSR8_PMSR83                       (0x00000008uL)
+#define GPIO_PMSR8_PMSR84                       (0x00000010uL)
+#define GPIO_PMSR8_PMSR85                       (0x00000020uL)
+#define GPIO_PMSR8_PMSR86                       (0x00000040uL)
+#define GPIO_PMSR8_PMSR87                       (0x00000080uL)
+#define GPIO_PMSR8_PMSR88                       (0x00000100uL)
+#define GPIO_PMSR8_PMSR89                       (0x00000200uL)
+#define GPIO_PMSR8_PMSR810                      (0x00000400uL)
+#define GPIO_PMSR8_PMSR811                      (0x00000800uL)
+#define GPIO_PMSR8_PMSR812                      (0x00001000uL)
+#define GPIO_PMSR8_PMSR813                      (0x00002000uL)
+#define GPIO_PMSR8_PMSR814                      (0x00004000uL)
+#define GPIO_PMSR8_PMSR815                      (0x00008000uL)
+#define GPIO_PMSR8_PMSR816                      (0x00010000uL)
+#define GPIO_PMSR8_PMSR817                      (0x00020000uL)
+#define GPIO_PMSR8_PMSR818                      (0x00040000uL)
+#define GPIO_PMSR8_PMSR819                      (0x00080000uL)
+#define GPIO_PMSR8_PMSR820                      (0x00100000uL)
+#define GPIO_PMSR8_PMSR821                      (0x00200000uL)
+#define GPIO_PMSR8_PMSR822                      (0x00400000uL)
+#define GPIO_PMSR8_PMSR823                      (0x00800000uL)
+#define GPIO_PMSR8_PMSR824                      (0x01000000uL)
+#define GPIO_PMSR8_PMSR825                      (0x02000000uL)
+#define GPIO_PMSR8_PMSR826                      (0x04000000uL)
+#define GPIO_PMSR8_PMSR827                      (0x08000000uL)
+#define GPIO_PMSR8_PMSR828                      (0x10000000uL)
+#define GPIO_PMSR8_PMSR829                      (0x20000000uL)
+#define GPIO_PMSR8_PMSR830                      (0x40000000uL)
+#define GPIO_PMSR8_PMSR831                      (0x80000000uL)
+
+#define GPIO_PMCSR8_PMCSR80                     (0x00000001uL)
+#define GPIO_PMCSR8_PMCSR81                     (0x00000002uL)
+#define GPIO_PMCSR8_PMCSR82                     (0x00000004uL)
+#define GPIO_PMCSR8_PMCSR83                     (0x00000008uL)
+#define GPIO_PMCSR8_PMCSR84                     (0x00000010uL)
+#define GPIO_PMCSR8_PMCSR85                     (0x00000020uL)
+#define GPIO_PMCSR8_PMCSR86                     (0x00000040uL)
+#define GPIO_PMCSR8_PMCSR87                     (0x00000080uL)
+#define GPIO_PMCSR8_PMCSR88                     (0x00000100uL)
+#define GPIO_PMCSR8_PMCSR89                     (0x00000200uL)
+#define GPIO_PMCSR8_PMCSR810                    (0x00000400uL)
+#define GPIO_PMCSR8_PMCSR811                    (0x00000800uL)
+#define GPIO_PMCSR8_PMCSR812                    (0x00001000uL)
+#define GPIO_PMCSR8_PMCSR813                    (0x00002000uL)
+#define GPIO_PMCSR8_PMCSR814                    (0x00004000uL)
+#define GPIO_PMCSR8_PMCSR815                    (0x00008000uL)
+#define GPIO_PMCSR8_PMCSR816                    (0x00010000uL)
+#define GPIO_PMCSR8_PMCSR817                    (0x00020000uL)
+#define GPIO_PMCSR8_PMCSR818                    (0x00040000uL)
+#define GPIO_PMCSR8_PMCSR819                    (0x00080000uL)
+#define GPIO_PMCSR8_PMCSR820                    (0x00100000uL)
+#define GPIO_PMCSR8_PMCSR821                    (0x00200000uL)
+#define GPIO_PMCSR8_PMCSR822                    (0x00400000uL)
+#define GPIO_PMCSR8_PMCSR823                    (0x00800000uL)
+#define GPIO_PMCSR8_PMCSR824                    (0x01000000uL)
+#define GPIO_PMCSR8_PMCSR825                    (0x02000000uL)
+#define GPIO_PMCSR8_PMCSR826                    (0x04000000uL)
+#define GPIO_PMCSR8_PMCSR827                    (0x08000000uL)
+#define GPIO_PMCSR8_PMCSR828                    (0x10000000uL)
+#define GPIO_PMCSR8_PMCSR829                    (0x20000000uL)
+#define GPIO_PMCSR8_PMCSR830                    (0x40000000uL)
+#define GPIO_PMCSR8_PMCSR831                    (0x80000000uL)
+
+#define GPIO_PFCAE8_PFCAE80                     (0x0001u)
+#define GPIO_PFCAE8_PFCAE81                     (0x0002u)
+#define GPIO_PFCAE8_PFCAE82                     (0x0004u)
+#define GPIO_PFCAE8_PFCAE83                     (0x0008u)
+#define GPIO_PFCAE8_PFCAE84                     (0x0010u)
+#define GPIO_PFCAE8_PFCAE85                     (0x0020u)
+#define GPIO_PFCAE8_PFCAE86                     (0x0040u)
+#define GPIO_PFCAE8_PFCAE87                     (0x0080u)
+#define GPIO_PFCAE8_PFCAE88                     (0x0100u)
+#define GPIO_PFCAE8_PFCAE89                     (0x0200u)
+#define GPIO_PFCAE8_PFCAE810                    (0x0400u)
+#define GPIO_PFCAE8_PFCAE811                    (0x0800u)
+#define GPIO_PFCAE8_PFCAE812                    (0x1000u)
+#define GPIO_PFCAE8_PFCAE813                    (0x2000u)
+#define GPIO_PFCAE8_PFCAE814                    (0x4000u)
+#define GPIO_PFCAE8_PFCAE815                    (0x8000u)
+
+#define GPIO_PIBC8_PIBC80                       (0x0001u)
+#define GPIO_PIBC8_PIBC81                       (0x0002u)
+#define GPIO_PIBC8_PIBC82                       (0x0004u)
+#define GPIO_PIBC8_PIBC83                       (0x0008u)
+#define GPIO_PIBC8_PIBC84                       (0x0010u)
+#define GPIO_PIBC8_PIBC85                       (0x0020u)
+#define GPIO_PIBC8_PIBC86                       (0x0040u)
+#define GPIO_PIBC8_PIBC87                       (0x0080u)
+#define GPIO_PIBC8_PIBC88                       (0x0100u)
+#define GPIO_PIBC8_PIBC89                       (0x0200u)
+#define GPIO_PIBC8_PIBC810                      (0x0400u)
+#define GPIO_PIBC8_PIBC811                      (0x0800u)
+#define GPIO_PIBC8_PIBC812                      (0x1000u)
+#define GPIO_PIBC8_PIBC813                      (0x2000u)
+#define GPIO_PIBC8_PIBC814                      (0x4000u)
+#define GPIO_PIBC8_PIBC815                      (0x8000u)
+
+#define GPIO_PBDC8_PBDC80                       (0x0001u)
+#define GPIO_PBDC8_PBDC81                       (0x0002u)
+#define GPIO_PBDC8_PBDC82                       (0x0004u)
+#define GPIO_PBDC8_PBDC83                       (0x0008u)
+#define GPIO_PBDC8_PBDC84                       (0x0010u)
+#define GPIO_PBDC8_PBDC85                       (0x0020u)
+#define GPIO_PBDC8_PBDC86                       (0x0040u)
+#define GPIO_PBDC8_PBDC87                       (0x0080u)
+#define GPIO_PBDC8_PBDC88                       (0x0100u)
+#define GPIO_PBDC8_PBDC89                       (0x0200u)
+#define GPIO_PBDC8_PBDC810                      (0x0400u)
+#define GPIO_PBDC8_PBDC811                      (0x0800u)
+#define GPIO_PBDC8_PBDC812                      (0x1000u)
+#define GPIO_PBDC8_PBDC813                      (0x2000u)
+#define GPIO_PBDC8_PBDC814                      (0x4000u)
+#define GPIO_PBDC8_PBDC815                      (0x8000u)
+
+#define GPIO_PIPC8_PIPC80                       (0x0001u)
+#define GPIO_PIPC8_PIPC81                       (0x0002u)
+#define GPIO_PIPC8_PIPC82                       (0x0004u)
+#define GPIO_PIPC8_PIPC83                       (0x0008u)
+#define GPIO_PIPC8_PIPC84                       (0x0010u)
+#define GPIO_PIPC8_PIPC85                       (0x0020u)
+#define GPIO_PIPC8_PIPC86                       (0x0040u)
+#define GPIO_PIPC8_PIPC87                       (0x0080u)
+#define GPIO_PIPC8_PIPC88                       (0x0100u)
+#define GPIO_PIPC8_PIPC89                       (0x0200u)
+#define GPIO_PIPC8_PIPC810                      (0x0400u)
+#define GPIO_PIPC8_PIPC811                      (0x0800u)
+#define GPIO_PIPC8_PIPC812                      (0x1000u)
+#define GPIO_PIPC8_PIPC813                      (0x2000u)
+#define GPIO_PIPC8_PIPC814                      (0x4000u)
+#define GPIO_PIPC8_PIPC815                      (0x8000u)
+
+/* ---- P9 ---- */
+#define GPIO_P9_P90                             (0x0001u)
+#define GPIO_P9_P91                             (0x0002u)
+#define GPIO_P9_P92                             (0x0004u)
+#define GPIO_P9_P93                             (0x0008u)
+#define GPIO_P9_P94                             (0x0010u)
+#define GPIO_P9_P95                             (0x0020u)
+#define GPIO_P9_P96                             (0x0040u)
+#define GPIO_P9_P97                             (0x0080u)
+
+#define GPIO_PSR9_PSR90                         (0x00000001uL)
+#define GPIO_PSR9_PSR91                         (0x00000002uL)
+#define GPIO_PSR9_PSR92                         (0x00000004uL)
+#define GPIO_PSR9_PSR93                         (0x00000008uL)
+#define GPIO_PSR9_PSR94                         (0x00000010uL)
+#define GPIO_PSR9_PSR95                         (0x00000020uL)
+#define GPIO_PSR9_PSR96                         (0x00000040uL)
+#define GPIO_PSR9_PSR97                         (0x00000080uL)
+#define GPIO_PSR9_PSR916                        (0x00010000uL)
+#define GPIO_PSR9_PSR917                        (0x00020000uL)
+#define GPIO_PSR9_PSR918                        (0x00040000uL)
+#define GPIO_PSR9_PSR919                        (0x00080000uL)
+#define GPIO_PSR9_PSR920                        (0x00100000uL)
+#define GPIO_PSR9_PSR921                        (0x00200000uL)
+#define GPIO_PSR9_PSR922                        (0x00400000uL)
+#define GPIO_PSR9_PSR923                        (0x00800000uL)
+
+#define GPIO_PPR9_PPR90                         (0x0001u)
+#define GPIO_PPR9_PPR91                         (0x0002u)
+#define GPIO_PPR9_PPR92                         (0x0004u)
+#define GPIO_PPR9_PPR93                         (0x0008u)
+#define GPIO_PPR9_PPR94                         (0x0010u)
+#define GPIO_PPR9_PPR95                         (0x0020u)
+#define GPIO_PPR9_PPR96                         (0x0040u)
+#define GPIO_PPR9_PPR97                         (0x0080u)
+
+#define GPIO_PM9_PM90                           (0x0001u)
+#define GPIO_PM9_PM91                           (0x0002u)
+#define GPIO_PM9_PM92                           (0x0004u)
+#define GPIO_PM9_PM93                           (0x0008u)
+#define GPIO_PM9_PM94                           (0x0010u)
+#define GPIO_PM9_PM95                           (0x0020u)
+#define GPIO_PM9_PM96                           (0x0040u)
+#define GPIO_PM9_PM97                           (0x0080u)
+
+#define GPIO_PMC9_PMC90                         (0x0001u)
+#define GPIO_PMC9_PMC91                         (0x0002u)
+#define GPIO_PMC9_PMC92                         (0x0004u)
+#define GPIO_PMC9_PMC93                         (0x0008u)
+#define GPIO_PMC9_PMC94                         (0x0010u)
+#define GPIO_PMC9_PMC95                         (0x0020u)
+#define GPIO_PMC9_PMC96                         (0x0040u)
+#define GPIO_PMC9_PMC97                         (0x0080u)
+
+#define GPIO_PFC9_PFC90                         (0x0001u)
+#define GPIO_PFC9_PFC91                         (0x0002u)
+#define GPIO_PFC9_PFC92                         (0x0004u)
+#define GPIO_PFC9_PFC93                         (0x0008u)
+#define GPIO_PFC9_PFC94                         (0x0010u)
+#define GPIO_PFC9_PFC95                         (0x0020u)
+#define GPIO_PFC9_PFC96                         (0x0040u)
+#define GPIO_PFC9_PFC97                         (0x0080u)
+
+#define GPIO_PFCE9_PFCE90                       (0x0001u)
+#define GPIO_PFCE9_PFCE91                       (0x0002u)
+#define GPIO_PFCE9_PFCE92                       (0x0004u)
+#define GPIO_PFCE9_PFCE93                       (0x0008u)
+#define GPIO_PFCE9_PFCE94                       (0x0010u)
+#define GPIO_PFCE9_PFCE95                       (0x0020u)
+#define GPIO_PFCE9_PFCE96                       (0x0040u)
+#define GPIO_PFCE9_PFCE97                       (0x0080u)
+
+#define GPIO_PNOT9_PNOT90                       (0x0001u)
+#define GPIO_PNOT9_PNOT91                       (0x0002u)
+#define GPIO_PNOT9_PNOT92                       (0x0004u)
+#define GPIO_PNOT9_PNOT93                       (0x0008u)
+#define GPIO_PNOT9_PNOT94                       (0x0010u)
+#define GPIO_PNOT9_PNOT95                       (0x0020u)
+#define GPIO_PNOT9_PNOT96                       (0x0040u)
+#define GPIO_PNOT9_PNOT97                       (0x0080u)
+
+#define GPIO_PMSR9_PMSR90                       (0x00000001uL)
+#define GPIO_PMSR9_PMSR91                       (0x00000002uL)
+#define GPIO_PMSR9_PMSR92                       (0x00000004uL)
+#define GPIO_PMSR9_PMSR93                       (0x00000008uL)
+#define GPIO_PMSR9_PMSR94                       (0x00000010uL)
+#define GPIO_PMSR9_PMSR95                       (0x00000020uL)
+#define GPIO_PMSR9_PMSR96                       (0x00000040uL)
+#define GPIO_PMSR9_PMSR97                       (0x00000080uL)
+#define GPIO_PMSR9_PMSR916                      (0x00010000uL)
+#define GPIO_PMSR9_PMSR917                      (0x00020000uL)
+#define GPIO_PMSR9_PMSR918                      (0x00040000uL)
+#define GPIO_PMSR9_PMSR919                      (0x00080000uL)
+#define GPIO_PMSR9_PMSR920                      (0x00100000uL)
+#define GPIO_PMSR9_PMSR921                      (0x00200000uL)
+#define GPIO_PMSR9_PMSR922                      (0x00400000uL)
+#define GPIO_PMSR9_PMSR923                      (0x00800000uL)
+
+#define GPIO_PMCSR9_PMCSR90                     (0x00000001uL)
+#define GPIO_PMCSR9_PMCSR91                     (0x00000002uL)
+#define GPIO_PMCSR9_PMCSR92                     (0x00000004uL)
+#define GPIO_PMCSR9_PMCSR93                     (0x00000008uL)
+#define GPIO_PMCSR9_PMCSR94                     (0x00000010uL)
+#define GPIO_PMCSR9_PMCSR95                     (0x00000020uL)
+#define GPIO_PMCSR9_PMCSR96                     (0x00000040uL)
+#define GPIO_PMCSR9_PMCSR97                     (0x00000080uL)
+#define GPIO_PMCSR9_PMCSR916                    (0x00010000uL)
+#define GPIO_PMCSR9_PMCSR917                    (0x00020000uL)
+#define GPIO_PMCSR9_PMCSR918                    (0x00040000uL)
+#define GPIO_PMCSR9_PMCSR919                    (0x00080000uL)
+#define GPIO_PMCSR9_PMCSR920                    (0x00100000uL)
+#define GPIO_PMCSR9_PMCSR921                    (0x00200000uL)
+#define GPIO_PMCSR9_PMCSR922                    (0x00400000uL)
+#define GPIO_PMCSR9_PMCSR923                    (0x00800000uL)
+
+#define GPIO_PFCAE9_PFCAE90                     (0x0001u)
+#define GPIO_PFCAE9_PFCAE91                     (0x0002u)
+#define GPIO_PFCAE9_PFCAE92                     (0x0004u)
+#define GPIO_PFCAE9_PFCAE93                     (0x0008u)
+#define GPIO_PFCAE9_PFCAE94                     (0x0010u)
+#define GPIO_PFCAE9_PFCAE95                     (0x0020u)
+#define GPIO_PFCAE9_PFCAE96                     (0x0040u)
+#define GPIO_PFCAE9_PFCAE97                     (0x0080u)
+
+#define GPIO_PIBC9_PIBC90                       (0x0001u)
+#define GPIO_PIBC9_PIBC91                       (0x0002u)
+#define GPIO_PIBC9_PIBC92                       (0x0004u)
+#define GPIO_PIBC9_PIBC93                       (0x0008u)
+#define GPIO_PIBC9_PIBC94                       (0x0010u)
+#define GPIO_PIBC9_PIBC95                       (0x0020u)
+#define GPIO_PIBC9_PIBC96                       (0x0040u)
+#define GPIO_PIBC9_PIBC97                       (0x0080u)
+
+#define GPIO_PBDC9_PBDC90                       (0x0001u)
+#define GPIO_PBDC9_PBDC91                       (0x0002u)
+#define GPIO_PBDC9_PBDC92                       (0x0004u)
+#define GPIO_PBDC9_PBDC93                       (0x0008u)
+#define GPIO_PBDC9_PBDC94                       (0x0010u)
+#define GPIO_PBDC9_PBDC95                       (0x0020u)
+#define GPIO_PBDC9_PBDC96                       (0x0040u)
+#define GPIO_PBDC9_PBDC97                       (0x0080u)
+
+#define GPIO_PIPC9_PIPC90                       (0x0001u)
+#define GPIO_PIPC9_PIPC91                       (0x0002u)
+#define GPIO_PIPC9_PIPC92                       (0x0004u)
+#define GPIO_PIPC9_PIPC93                       (0x0008u)
+#define GPIO_PIPC9_PIPC94                       (0x0010u)
+#define GPIO_PIPC9_PIPC95                       (0x0020u)
+#define GPIO_PIPC9_PIPC96                       (0x0040u)
+#define GPIO_PIPC9_PIPC97                       (0x0080u)
+
+/* ---- P10 ---- */
+#define GPIO_P10_P100                           (0x0001u)
+#define GPIO_P10_P101                           (0x0002u)
+#define GPIO_P10_P102                           (0x0004u)
+#define GPIO_P10_P103                           (0x0008u)
+#define GPIO_P10_P104                           (0x0010u)
+#define GPIO_P10_P105                           (0x0020u)
+#define GPIO_P10_P106                           (0x0040u)
+#define GPIO_P10_P107                           (0x0080u)
+#define GPIO_P10_P108                           (0x0100u)
+#define GPIO_P10_P109                           (0x0200u)
+#define GPIO_P10_P1010                          (0x0400u)
+#define GPIO_P10_P1011                          (0x0800u)
+#define GPIO_P10_P1012                          (0x1000u)
+#define GPIO_P10_P1013                          (0x2000u)
+#define GPIO_P10_P1014                          (0x4000u)
+#define GPIO_P10_P1015                          (0x8000u)
+
+#define GPIO_PSR10_PSR100                       (0x00000001uL)
+#define GPIO_PSR10_PSR101                       (0x00000002uL)
+#define GPIO_PSR10_PSR102                       (0x00000004uL)
+#define GPIO_PSR10_PSR103                       (0x00000008uL)
+#define GPIO_PSR10_PSR104                       (0x00000010uL)
+#define GPIO_PSR10_PSR105                       (0x00000020uL)
+#define GPIO_PSR10_PSR106                       (0x00000040uL)
+#define GPIO_PSR10_PSR107                       (0x00000080uL)
+#define GPIO_PSR10_PSR108                       (0x00000100uL)
+#define GPIO_PSR10_PSR109                       (0x00000200uL)
+#define GPIO_PSR10_PSR1010                      (0x00000400uL)
+#define GPIO_PSR10_PSR1011                      (0x00000800uL)
+#define GPIO_PSR10_PSR1012                      (0x00001000uL)
+#define GPIO_PSR10_PSR1013                      (0x00002000uL)
+#define GPIO_PSR10_PSR1014                      (0x00004000uL)
+#define GPIO_PSR10_PSR1015                      (0x00008000uL)
+#define GPIO_PSR10_PSR1016                      (0x00010000uL)
+#define GPIO_PSR10_PSR1017                      (0x00020000uL)
+#define GPIO_PSR10_PSR1018                      (0x00040000uL)
+#define GPIO_PSR10_PSR1019                      (0x00080000uL)
+#define GPIO_PSR10_PSR1020                      (0x00100000uL)
+#define GPIO_PSR10_PSR1021                      (0x00200000uL)
+#define GPIO_PSR10_PSR1022                      (0x00400000uL)
+#define GPIO_PSR10_PSR1023                      (0x00800000uL)
+#define GPIO_PSR10_PSR1024                      (0x01000000uL)
+#define GPIO_PSR10_PSR1025                      (0x02000000uL)
+#define GPIO_PSR10_PSR1026                      (0x04000000uL)
+#define GPIO_PSR10_PSR1027                      (0x08000000uL)
+#define GPIO_PSR10_PSR1028                      (0x10000000uL)
+#define GPIO_PSR10_PSR1029                      (0x20000000uL)
+#define GPIO_PSR10_PSR1030                      (0x40000000uL)
+#define GPIO_PSR10_PSR1031                      (0x80000000uL)
+
+#define GPIO_PPR10_PPR100                       (0x0001u)
+#define GPIO_PPR10_PPR101                       (0x0002u)
+#define GPIO_PPR10_PPR102                       (0x0004u)
+#define GPIO_PPR10_PPR103                       (0x0008u)
+#define GPIO_PPR10_PPR104                       (0x0010u)
+#define GPIO_PPR10_PPR105                       (0x0020u)
+#define GPIO_PPR10_PPR106                       (0x0040u)
+#define GPIO_PPR10_PPR107                       (0x0080u)
+#define GPIO_PPR10_PPR108                       (0x0100u)
+#define GPIO_PPR10_PPR109                       (0x0200u)
+#define GPIO_PPR10_PPR1010                      (0x0400u)
+#define GPIO_PPR10_PPR1011                      (0x0800u)
+#define GPIO_PPR10_PPR1012                      (0x1000u)
+#define GPIO_PPR10_PPR1013                      (0x2000u)
+#define GPIO_PPR10_PPR1014                      (0x4000u)
+#define GPIO_PPR10_PPR1015                      (0x8000u)
+
+#define GPIO_PM10_PM100                         (0x0001u)
+#define GPIO_PM10_PM101                         (0x0002u)
+#define GPIO_PM10_PM102                         (0x0004u)
+#define GPIO_PM10_PM103                         (0x0008u)
+#define GPIO_PM10_PM104                         (0x0010u)
+#define GPIO_PM10_PM105                         (0x0020u)
+#define GPIO_PM10_PM106                         (0x0040u)
+#define GPIO_PM10_PM107                         (0x0080u)
+#define GPIO_PM10_PM108                         (0x0100u)
+#define GPIO_PM10_PM109                         (0x0200u)
+#define GPIO_PM10_PM1010                        (0x0400u)
+#define GPIO_PM10_PM1011                        (0x0800u)
+#define GPIO_PM10_PM1012                        (0x1000u)
+#define GPIO_PM10_PM1013                        (0x2000u)
+#define GPIO_PM10_PM1014                        (0x4000u)
+#define GPIO_PM10_PM1015                        (0x8000u)
+
+#define GPIO_PMC10_PMC100                       (0x0001u)
+#define GPIO_PMC10_PMC101                       (0x0002u)
+#define GPIO_PMC10_PMC102                       (0x0004u)
+#define GPIO_PMC10_PMC103                       (0x0008u)
+#define GPIO_PMC10_PMC104                       (0x0010u)
+#define GPIO_PMC10_PMC105                       (0x0020u)
+#define GPIO_PMC10_PMC106                       (0x0040u)
+#define GPIO_PMC10_PMC107                       (0x0080u)
+#define GPIO_PMC10_PMC108                       (0x0100u)
+#define GPIO_PMC10_PMC109                       (0x0200u)
+#define GPIO_PMC10_PMC1010                      (0x0400u)
+#define GPIO_PMC10_PMC1011                      (0x0800u)
+#define GPIO_PMC10_PMC1012                      (0x1000u)
+#define GPIO_PMC10_PMC1013                      (0x2000u)
+#define GPIO_PMC10_PMC1014                      (0x4000u)
+#define GPIO_PMC10_PMC1015                      (0x8000u)
+
+#define GPIO_PFC10_PFC100                       (0x0001u)
+#define GPIO_PFC10_PFC101                       (0x0002u)
+#define GPIO_PFC10_PFC102                       (0x0004u)
+#define GPIO_PFC10_PFC103                       (0x0008u)
+#define GPIO_PFC10_PFC104                       (0x0010u)
+#define GPIO_PFC10_PFC105                       (0x0020u)
+#define GPIO_PFC10_PFC106                       (0x0040u)
+#define GPIO_PFC10_PFC107                       (0x0080u)
+#define GPIO_PFC10_PFC108                       (0x0100u)
+#define GPIO_PFC10_PFC109                       (0x0200u)
+#define GPIO_PFC10_PFC1010                      (0x0400u)
+#define GPIO_PFC10_PFC1011                      (0x0800u)
+#define GPIO_PFC10_PFC1012                      (0x1000u)
+#define GPIO_PFC10_PFC1013                      (0x2000u)
+#define GPIO_PFC10_PFC1014                      (0x4000u)
+#define GPIO_PFC10_PFC1015                      (0x8000u)
+
+#define GPIO_PFCE10_PFCE100                     (0x0001u)
+#define GPIO_PFCE10_PFCE101                     (0x0002u)
+#define GPIO_PFCE10_PFCE102                     (0x0004u)
+#define GPIO_PFCE10_PFCE103                     (0x0008u)
+#define GPIO_PFCE10_PFCE104                     (0x0010u)
+#define GPIO_PFCE10_PFCE105                     (0x0020u)
+#define GPIO_PFCE10_PFCE106                     (0x0040u)
+#define GPIO_PFCE10_PFCE107                     (0x0080u)
+#define GPIO_PFCE10_PFCE108                     (0x0100u)
+#define GPIO_PFCE10_PFCE109                     (0x0200u)
+#define GPIO_PFCE10_PFCE1010                    (0x0400u)
+#define GPIO_PFCE10_PFCE1011                    (0x0800u)
+#define GPIO_PFCE10_PFCE1012                    (0x1000u)
+#define GPIO_PFCE10_PFCE1013                    (0x2000u)
+#define GPIO_PFCE10_PFCE1014                    (0x4000u)
+#define GPIO_PFCE10_PFCE1015                    (0x8000u)
+
+#define GPIO_PNOT10_PNOT100                     (0x0001u)
+#define GPIO_PNOT10_PNOT101                     (0x0002u)
+#define GPIO_PNOT10_PNOT102                     (0x0004u)
+#define GPIO_PNOT10_PNOT103                     (0x0008u)
+#define GPIO_PNOT10_PNOT104                     (0x0010u)
+#define GPIO_PNOT10_PNOT105                     (0x0020u)
+#define GPIO_PNOT10_PNOT106                     (0x0040u)
+#define GPIO_PNOT10_PNOT107                     (0x0080u)
+#define GPIO_PNOT10_PNOT108                     (0x0100u)
+#define GPIO_PNOT10_PNOT109                     (0x0200u)
+#define GPIO_PNOT10_PNOT1010                    (0x0400u)
+#define GPIO_PNOT10_PNOT1011                    (0x0800u)
+#define GPIO_PNOT10_PNOT1012                    (0x1000u)
+#define GPIO_PNOT10_PNOT1013                    (0x2000u)
+#define GPIO_PNOT10_PNOT1014                    (0x4000u)
+#define GPIO_PNOT10_PNOT1015                    (0x8000u)
+
+#define GPIO_PMSR10_PMSR100                     (0x00000001uL)
+#define GPIO_PMSR10_PMSR101                     (0x00000002uL)
+#define GPIO_PMSR10_PMSR102                     (0x00000004uL)
+#define GPIO_PMSR10_PMSR103                     (0x00000008uL)
+#define GPIO_PMSR10_PMSR104                     (0x00000010uL)
+#define GPIO_PMSR10_PMSR105                     (0x00000020uL)
+#define GPIO_PMSR10_PMSR106                     (0x00000040uL)
+#define GPIO_PMSR10_PMSR107                     (0x00000080uL)
+#define GPIO_PMSR10_PMSR108                     (0x00000100uL)
+#define GPIO_PMSR10_PMSR109                     (0x00000200uL)
+#define GPIO_PMSR10_PMSR1010                    (0x00000400uL)
+#define GPIO_PMSR10_PMSR1011                    (0x00000800uL)
+#define GPIO_PMSR10_PMSR1012                    (0x00001000uL)
+#define GPIO_PMSR10_PMSR1013                    (0x00002000uL)
+#define GPIO_PMSR10_PMSR1014                    (0x00004000uL)
+#define GPIO_PMSR10_PMSR1015                    (0x00008000uL)
+#define GPIO_PMSR10_PMSR1016                    (0x00010000uL)
+#define GPIO_PMSR10_PMSR1017                    (0x00020000uL)
+#define GPIO_PMSR10_PMSR1018                    (0x00040000uL)
+#define GPIO_PMSR10_PMSR1019                    (0x00080000uL)
+#define GPIO_PMSR10_PMSR1020                    (0x00100000uL)
+#define GPIO_PMSR10_PMSR1021                    (0x00200000uL)
+#define GPIO_PMSR10_PMSR1022                    (0x00400000uL)
+#define GPIO_PMSR10_PMSR1023                    (0x00800000uL)
+#define GPIO_PMSR10_PMSR1024                    (0x01000000uL)
+#define GPIO_PMSR10_PMSR1025                    (0x02000000uL)
+#define GPIO_PMSR10_PMSR1026                    (0x04000000uL)
+#define GPIO_PMSR10_PMSR1027                    (0x08000000uL)
+#define GPIO_PMSR10_PMSR1028                    (0x10000000uL)
+#define GPIO_PMSR10_PMSR1029                    (0x20000000uL)
+#define GPIO_PMSR10_PMSR1030                    (0x40000000uL)
+#define GPIO_PMSR10_PMSR1031                    (0x80000000uL)
+
+#define GPIO_PMCSR10_PMCSR100                   (0x00000001uL)
+#define GPIO_PMCSR10_PMCSR101                   (0x00000002uL)
+#define GPIO_PMCSR10_PMCSR102                   (0x00000004uL)
+#define GPIO_PMCSR10_PMCSR103                   (0x00000008uL)
+#define GPIO_PMCSR10_PMCSR104                   (0x00000010uL)
+#define GPIO_PMCSR10_PMCSR105                   (0x00000020uL)
+#define GPIO_PMCSR10_PMCSR106                   (0x00000040uL)
+#define GPIO_PMCSR10_PMCSR107                   (0x00000080uL)
+#define GPIO_PMCSR10_PMCSR108                   (0x00000100uL)
+#define GPIO_PMCSR10_PMCSR109                   (0x00000200uL)
+#define GPIO_PMCSR10_PMCSR1010                  (0x00000400uL)
+#define GPIO_PMCSR10_PMCSR1011                  (0x00000800uL)
+#define GPIO_PMCSR10_PMCSR1012                  (0x00001000uL)
+#define GPIO_PMCSR10_PMCSR1013                  (0x00002000uL)
+#define GPIO_PMCSR10_PMCSR1014                  (0x00004000uL)
+#define GPIO_PMCSR10_PMCSR1015                  (0x00008000uL)
+#define GPIO_PMCSR10_PMCSR1016                  (0x00010000uL)
+#define GPIO_PMCSR10_PMCSR1017                  (0x00020000uL)
+#define GPIO_PMCSR10_PMCSR1018                  (0x00040000uL)
+#define GPIO_PMCSR10_PMCSR1019                  (0x00080000uL)
+#define GPIO_PMCSR10_PMCSR1020                  (0x00100000uL)
+#define GPIO_PMCSR10_PMCSR1021                  (0x00200000uL)
+#define GPIO_PMCSR10_PMCSR1022                  (0x00400000uL)
+#define GPIO_PMCSR10_PMCSR1023                  (0x00800000uL)
+#define GPIO_PMCSR10_PMCSR1024                  (0x01000000uL)
+#define GPIO_PMCSR10_PMCSR1025                  (0x02000000uL)
+#define GPIO_PMCSR10_PMCSR1026                  (0x04000000uL)
+#define GPIO_PMCSR10_PMCSR1027                  (0x08000000uL)
+#define GPIO_PMCSR10_PMCSR1028                  (0x10000000uL)
+#define GPIO_PMCSR10_PMCSR1029                  (0x20000000uL)
+#define GPIO_PMCSR10_PMCSR1030                  (0x40000000uL)
+#define GPIO_PMCSR10_PMCSR1031                  (0x80000000uL)
+
+#define GPIO_PFCAE10_PFCAE100                   (0x0001u)
+#define GPIO_PFCAE10_PFCAE101                   (0x0002u)
+#define GPIO_PFCAE10_PFCAE102                   (0x0004u)
+#define GPIO_PFCAE10_PFCAE103                   (0x0008u)
+#define GPIO_PFCAE10_PFCAE104                   (0x0010u)
+#define GPIO_PFCAE10_PFCAE105                   (0x0020u)
+#define GPIO_PFCAE10_PFCAE106                   (0x0040u)
+#define GPIO_PFCAE10_PFCAE107                   (0x0080u)
+#define GPIO_PFCAE10_PFCAE108                   (0x0100u)
+#define GPIO_PFCAE10_PFCAE109                   (0x0200u)
+#define GPIO_PFCAE10_PFCAE1010                  (0x0400u)
+#define GPIO_PFCAE10_PFCAE1011                  (0x0800u)
+#define GPIO_PFCAE10_PFCAE1012                  (0x1000u)
+#define GPIO_PFCAE10_PFCAE1013                  (0x2000u)
+#define GPIO_PFCAE10_PFCAE1014                  (0x4000u)
+#define GPIO_PFCAE10_PFCAE1015                  (0x8000u)
+
+#define GPIO_PIBC10_PIBC100                     (0x0001u)
+#define GPIO_PIBC10_PIBC101                     (0x0002u)
+#define GPIO_PIBC10_PIBC102                     (0x0004u)
+#define GPIO_PIBC10_PIBC103                     (0x0008u)
+#define GPIO_PIBC10_PIBC104                     (0x0010u)
+#define GPIO_PIBC10_PIBC105                     (0x0020u)
+#define GPIO_PIBC10_PIBC106                     (0x0040u)
+#define GPIO_PIBC10_PIBC107                     (0x0080u)
+#define GPIO_PIBC10_PIBC108                     (0x0100u)
+#define GPIO_PIBC10_PIBC109                     (0x0200u)
+#define GPIO_PIBC10_PIBC1010                    (0x0400u)
+#define GPIO_PIBC10_PIBC1011                    (0x0800u)
+#define GPIO_PIBC10_PIBC1012                    (0x1000u)
+#define GPIO_PIBC10_PIBC1013                    (0x2000u)
+#define GPIO_PIBC10_PIBC1014                    (0x4000u)
+#define GPIO_PIBC10_PIBC1015                    (0x8000u)
+
+#define GPIO_PBDC10_PBDC100                     (0x0001u)
+#define GPIO_PBDC10_PBDC101                     (0x0002u)
+#define GPIO_PBDC10_PBDC102                     (0x0004u)
+#define GPIO_PBDC10_PBDC103                     (0x0008u)
+#define GPIO_PBDC10_PBDC104                     (0x0010u)
+#define GPIO_PBDC10_PBDC105                     (0x0020u)
+#define GPIO_PBDC10_PBDC106                     (0x0040u)
+#define GPIO_PBDC10_PBDC107                     (0x0080u)
+#define GPIO_PBDC10_PBDC108                     (0x0100u)
+#define GPIO_PBDC10_PBDC109                     (0x0200u)
+#define GPIO_PBDC10_PBDC1010                    (0x0400u)
+#define GPIO_PBDC10_PBDC1011                    (0x0800u)
+#define GPIO_PBDC10_PBDC1012                    (0x1000u)
+#define GPIO_PBDC10_PBDC1013                    (0x2000u)
+#define GPIO_PBDC10_PBDC1014                    (0x4000u)
+#define GPIO_PBDC10_PBDC1015                    (0x8000u)
+
+#define GPIO_PIPC10_PIPC100                     (0x0001u)
+#define GPIO_PIPC10_PIPC101                     (0x0002u)
+#define GPIO_PIPC10_PIPC102                     (0x0004u)
+#define GPIO_PIPC10_PIPC103                     (0x0008u)
+#define GPIO_PIPC10_PIPC104                     (0x0010u)
+#define GPIO_PIPC10_PIPC105                     (0x0020u)
+#define GPIO_PIPC10_PIPC106                     (0x0040u)
+#define GPIO_PIPC10_PIPC107                     (0x0080u)
+#define GPIO_PIPC10_PIPC108                     (0x0100u)
+#define GPIO_PIPC10_PIPC109                     (0x0200u)
+#define GPIO_PIPC10_PIPC1010                    (0x0400u)
+#define GPIO_PIPC10_PIPC1011                    (0x0800u)
+#define GPIO_PIPC10_PIPC1012                    (0x1000u)
+#define GPIO_PIPC10_PIPC1013                    (0x2000u)
+#define GPIO_PIPC10_PIPC1014                    (0x4000u)
+#define GPIO_PIPC10_PIPC1015                    (0x8000u)
+
+/* ---- P11 ---- */
+#define GPIO_P11_P110                           (0x0001u)
+#define GPIO_P11_P111                           (0x0002u)
+#define GPIO_P11_P112                           (0x0004u)
+#define GPIO_P11_P113                           (0x0008u)
+#define GPIO_P11_P114                           (0x0010u)
+#define GPIO_P11_P115                           (0x0020u)
+#define GPIO_P11_P116                           (0x0040u)
+#define GPIO_P11_P117                           (0x0080u)
+#define GPIO_P11_P118                           (0x0100u)
+#define GPIO_P11_P119                           (0x0200u)
+#define GPIO_P11_P1110                          (0x0400u)
+#define GPIO_P11_P1111                          (0x0800u)
+#define GPIO_P11_P1112                          (0x1000u)
+#define GPIO_P11_P1113                          (0x2000u)
+#define GPIO_P11_P1114                          (0x4000u)
+#define GPIO_P11_P1115                          (0x8000u)
+
+#define GPIO_PSR11_PSR110                       (0x00000001uL)
+#define GPIO_PSR11_PSR111                       (0x00000002uL)
+#define GPIO_PSR11_PSR112                       (0x00000004uL)
+#define GPIO_PSR11_PSR113                       (0x00000008uL)
+#define GPIO_PSR11_PSR114                       (0x00000010uL)
+#define GPIO_PSR11_PSR115                       (0x00000020uL)
+#define GPIO_PSR11_PSR116                       (0x00000040uL)
+#define GPIO_PSR11_PSR117                       (0x00000080uL)
+#define GPIO_PSR11_PSR118                       (0x00000100uL)
+#define GPIO_PSR11_PSR119                       (0x00000200uL)
+#define GPIO_PSR11_PSR1110                      (0x00000400uL)
+#define GPIO_PSR11_PSR1111                      (0x00000800uL)
+#define GPIO_PSR11_PSR1112                      (0x00001000uL)
+#define GPIO_PSR11_PSR1113                      (0x00002000uL)
+#define GPIO_PSR11_PSR1114                      (0x00004000uL)
+#define GPIO_PSR11_PSR1115                      (0x00008000uL)
+#define GPIO_PSR11_PSR1116                      (0x00010000uL)
+#define GPIO_PSR11_PSR1117                      (0x00020000uL)
+#define GPIO_PSR11_PSR1118                      (0x00040000uL)
+#define GPIO_PSR11_PSR1119                      (0x00080000uL)
+#define GPIO_PSR11_PSR1120                      (0x00100000uL)
+#define GPIO_PSR11_PSR1121                      (0x00200000uL)
+#define GPIO_PSR11_PSR1122                      (0x00400000uL)
+#define GPIO_PSR11_PSR1123                      (0x00800000uL)
+#define GPIO_PSR11_PSR1124                      (0x01000000uL)
+#define GPIO_PSR11_PSR1125                      (0x02000000uL)
+#define GPIO_PSR11_PSR1126                      (0x04000000uL)
+#define GPIO_PSR11_PSR1127                      (0x08000000uL)
+#define GPIO_PSR11_PSR1128                      (0x10000000uL)
+#define GPIO_PSR11_PSR1129                      (0x20000000uL)
+#define GPIO_PSR11_PSR1130                      (0x40000000uL)
+#define GPIO_PSR11_PSR1131                      (0x80000000uL)
+
+#define GPIO_PPR11_PPR110                       (0x0001u)
+#define GPIO_PPR11_PPR111                       (0x0002u)
+#define GPIO_PPR11_PPR112                       (0x0004u)
+#define GPIO_PPR11_PPR113                       (0x0008u)
+#define GPIO_PPR11_PPR114                       (0x0010u)
+#define GPIO_PPR11_PPR115                       (0x0020u)
+#define GPIO_PPR11_PPR116                       (0x0040u)
+#define GPIO_PPR11_PPR117                       (0x0080u)
+#define GPIO_PPR11_PPR118                       (0x0100u)
+#define GPIO_PPR11_PPR119                       (0x0200u)
+#define GPIO_PPR11_PPR1110                      (0x0400u)
+#define GPIO_PPR11_PPR1111                      (0x0800u)
+#define GPIO_PPR11_PPR1112                      (0x1000u)
+#define GPIO_PPR11_PPR1113                      (0x2000u)
+#define GPIO_PPR11_PPR1114                      (0x4000u)
+#define GPIO_PPR11_PPR1115                      (0x8000u)
+
+#define GPIO_PM11_PM110                         (0x0001u)
+#define GPIO_PM11_PM111                         (0x0002u)
+#define GPIO_PM11_PM112                         (0x0004u)
+#define GPIO_PM11_PM113                         (0x0008u)
+#define GPIO_PM11_PM114                         (0x0010u)
+#define GPIO_PM11_PM115                         (0x0020u)
+#define GPIO_PM11_PM116                         (0x0040u)
+#define GPIO_PM11_PM117                         (0x0080u)
+#define GPIO_PM11_PM118                         (0x0100u)
+#define GPIO_PM11_PM119                         (0x0200u)
+#define GPIO_PM11_PM1110                        (0x0400u)
+#define GPIO_PM11_PM1111                        (0x0800u)
+#define GPIO_PM11_PM1112                        (0x1000u)
+#define GPIO_PM11_PM1113                        (0x2000u)
+#define GPIO_PM11_PM1114                        (0x4000u)
+#define GPIO_PM11_PM1115                        (0x8000u)
+
+#define GPIO_PMC11_PMC110                       (0x0001u)
+#define GPIO_PMC11_PMC111                       (0x0002u)
+#define GPIO_PMC11_PMC112                       (0x0004u)
+#define GPIO_PMC11_PMC113                       (0x0008u)
+#define GPIO_PMC11_PMC114                       (0x0010u)
+#define GPIO_PMC11_PMC115                       (0x0020u)
+#define GPIO_PMC11_PMC116                       (0x0040u)
+#define GPIO_PMC11_PMC117                       (0x0080u)
+#define GPIO_PMC11_PMC118                       (0x0100u)
+#define GPIO_PMC11_PMC119                       (0x0200u)
+#define GPIO_PMC11_PMC1110                      (0x0400u)
+#define GPIO_PMC11_PMC1111                      (0x0800u)
+#define GPIO_PMC11_PMC1112                      (0x1000u)
+#define GPIO_PMC11_PMC1113                      (0x2000u)
+#define GPIO_PMC11_PMC1114                      (0x4000u)
+#define GPIO_PMC11_PMC1115                      (0x8000u)
+
+#define GPIO_PFC11_PFC110                       (0x0001u)
+#define GPIO_PFC11_PFC111                       (0x0002u)
+#define GPIO_PFC11_PFC112                       (0x0004u)
+#define GPIO_PFC11_PFC113                       (0x0008u)
+#define GPIO_PFC11_PFC114                       (0x0010u)
+#define GPIO_PFC11_PFC115                       (0x0020u)
+#define GPIO_PFC11_PFC116                       (0x0040u)
+#define GPIO_PFC11_PFC117                       (0x0080u)
+#define GPIO_PFC11_PFC118                       (0x0100u)
+#define GPIO_PFC11_PFC119                       (0x0200u)
+#define GPIO_PFC11_PFC1110                      (0x0400u)
+#define GPIO_PFC11_PFC1111                      (0x0800u)
+#define GPIO_PFC11_PFC1112                      (0x1000u)
+#define GPIO_PFC11_PFC1113                      (0x2000u)
+#define GPIO_PFC11_PFC1114                      (0x4000u)
+#define GPIO_PFC11_PFC1115                      (0x8000u)
+
+#define GPIO_PFCE11_PFCE110                     (0x0001u)
+#define GPIO_PFCE11_PFCE111                     (0x0002u)
+#define GPIO_PFCE11_PFCE112                     (0x0004u)
+#define GPIO_PFCE11_PFCE113                     (0x0008u)
+#define GPIO_PFCE11_PFCE114                     (0x0010u)
+#define GPIO_PFCE11_PFCE115                     (0x0020u)
+#define GPIO_PFCE11_PFCE116                     (0x0040u)
+#define GPIO_PFCE11_PFCE117                     (0x0080u)
+#define GPIO_PFCE11_PFCE118                     (0x0100u)
+#define GPIO_PFCE11_PFCE119                     (0x0200u)
+#define GPIO_PFCE11_PFCE1110                    (0x0400u)
+#define GPIO_PFCE11_PFCE1111                    (0x0800u)
+#define GPIO_PFCE11_PFCE1112                    (0x1000u)
+#define GPIO_PFCE11_PFCE1113                    (0x2000u)
+#define GPIO_PFCE11_PFCE1114                    (0x4000u)
+#define GPIO_PFCE11_PFCE1115                    (0x8000u)
+
+#define GPIO_PNOT11_PNOT110                     (0x0001u)
+#define GPIO_PNOT11_PNOT111                     (0x0002u)
+#define GPIO_PNOT11_PNOT112                     (0x0004u)
+#define GPIO_PNOT11_PNOT113                     (0x0008u)
+#define GPIO_PNOT11_PNOT114                     (0x0010u)
+#define GPIO_PNOT11_PNOT115                     (0x0020u)
+#define GPIO_PNOT11_PNOT116                     (0x0040u)
+#define GPIO_PNOT11_PNOT117                     (0x0080u)
+#define GPIO_PNOT11_PNOT118                     (0x0100u)
+#define GPIO_PNOT11_PNOT119                     (0x0200u)
+#define GPIO_PNOT11_PNOT1110                    (0x0400u)
+#define GPIO_PNOT11_PNOT1111                    (0x0800u)
+#define GPIO_PNOT11_PNOT1112                    (0x1000u)
+#define GPIO_PNOT11_PNOT1113                    (0x2000u)
+#define GPIO_PNOT11_PNOT1114                    (0x4000u)
+#define GPIO_PNOT11_PNOT1115                    (0x8000u)
+
+#define GPIO_PMSR11_PMSR110                     (0x00000001uL)
+#define GPIO_PMSR11_PMSR111                     (0x00000002uL)
+#define GPIO_PMSR11_PMSR112                     (0x00000004uL)
+#define GPIO_PMSR11_PMSR113                     (0x00000008uL)
+#define GPIO_PMSR11_PMSR114                     (0x00000010uL)
+#define GPIO_PMSR11_PMSR115                     (0x00000020uL)
+#define GPIO_PMSR11_PMSR116                     (0x00000040uL)
+#define GPIO_PMSR11_PMSR117                     (0x00000080uL)
+#define GPIO_PMSR11_PMSR118                     (0x00000100uL)
+#define GPIO_PMSR11_PMSR119                     (0x00000200uL)
+#define GPIO_PMSR11_PMSR1110                    (0x00000400uL)
+#define GPIO_PMSR11_PMSR1111                    (0x00000800uL)
+#define GPIO_PMSR11_PMSR1112                    (0x00001000uL)
+#define GPIO_PMSR11_PMSR1113                    (0x00002000uL)
+#define GPIO_PMSR11_PMSR1114                    (0x00004000uL)
+#define GPIO_PMSR11_PMSR1115                    (0x00008000uL)
+#define GPIO_PMSR11_PMSR1116                    (0x00010000uL)
+#define GPIO_PMSR11_PMSR1117                    (0x00020000uL)
+#define GPIO_PMSR11_PMSR1118                    (0x00040000uL)
+#define GPIO_PMSR11_PMSR1119                    (0x00080000uL)
+#define GPIO_PMSR11_PMSR1120                    (0x00100000uL)
+#define GPIO_PMSR11_PMSR1121                    (0x00200000uL)
+#define GPIO_PMSR11_PMSR1122                    (0x00400000uL)
+#define GPIO_PMSR11_PMSR1123                    (0x00800000uL)
+#define GPIO_PMSR11_PMSR1124                    (0x01000000uL)
+#define GPIO_PMSR11_PMSR1125                    (0x02000000uL)
+#define GPIO_PMSR11_PMSR1126                    (0x04000000uL)
+#define GPIO_PMSR11_PMSR1127                    (0x08000000uL)
+#define GPIO_PMSR11_PMSR1128                    (0x10000000uL)
+#define GPIO_PMSR11_PMSR1129                    (0x20000000uL)
+#define GPIO_PMSR11_PMSR1130                    (0x40000000uL)
+#define GPIO_PMSR11_PMSR1131                    (0x80000000uL)
+
+#define GPIO_PMCSR11_PMCSR110                   (0x00000001uL)
+#define GPIO_PMCSR11_PMCSR111                   (0x00000002uL)
+#define GPIO_PMCSR11_PMCSR112                   (0x00000004uL)
+#define GPIO_PMCSR11_PMCSR113                   (0x00000008uL)
+#define GPIO_PMCSR11_PMCSR114                   (0x00000010uL)
+#define GPIO_PMCSR11_PMCSR115                   (0x00000020uL)
+#define GPIO_PMCSR11_PMCSR116                   (0x00000040uL)
+#define GPIO_PMCSR11_PMCSR117                   (0x00000080uL)
+#define GPIO_PMCSR11_PMCSR118                   (0x00000100uL)
+#define GPIO_PMCSR11_PMCSR119                   (0x00000200uL)
+#define GPIO_PMCSR11_PMCSR1110                  (0x00000400uL)
+#define GPIO_PMCSR11_PMCSR1111                  (0x00000800uL)
+#define GPIO_PMCSR11_PMCSR1112                  (0x00001000uL)
+#define GPIO_PMCSR11_PMCSR1113                  (0x00002000uL)
+#define GPIO_PMCSR11_PMCSR1114                  (0x00004000uL)
+#define GPIO_PMCSR11_PMCSR1115                  (0x00008000uL)
+#define GPIO_PMCSR11_PMCSR1116                  (0x00010000uL)
+#define GPIO_PMCSR11_PMCSR1117                  (0x00020000uL)
+#define GPIO_PMCSR11_PMCSR1118                  (0x00040000uL)
+#define GPIO_PMCSR11_PMCSR1119                  (0x00080000uL)
+#define GPIO_PMCSR11_PMCSR1120                  (0x00100000uL)
+#define GPIO_PMCSR11_PMCSR1121                  (0x00200000uL)
+#define GPIO_PMCSR11_PMCSR1122                  (0x00400000uL)
+#define GPIO_PMCSR11_PMCSR1123                  (0x00800000uL)
+#define GPIO_PMCSR11_PMCSR1124                  (0x01000000uL)
+#define GPIO_PMCSR11_PMCSR1125                  (0x02000000uL)
+#define GPIO_PMCSR11_PMCSR1126                  (0x04000000uL)
+#define GPIO_PMCSR11_PMCSR1127                  (0x08000000uL)
+#define GPIO_PMCSR11_PMCSR1128                  (0x10000000uL)
+#define GPIO_PMCSR11_PMCSR1129                  (0x20000000uL)
+#define GPIO_PMCSR11_PMCSR1130                  (0x40000000uL)
+#define GPIO_PMCSR11_PMCSR1131                  (0x80000000uL)
+
+#define GPIO_PFCAE11_PFCAE110                   (0x0001u)
+#define GPIO_PFCAE11_PFCAE111                   (0x0002u)
+#define GPIO_PFCAE11_PFCAE112                   (0x0004u)
+#define GPIO_PFCAE11_PFCAE113                   (0x0008u)
+#define GPIO_PFCAE11_PFCAE114                   (0x0010u)
+#define GPIO_PFCAE11_PFCAE115                   (0x0020u)
+#define GPIO_PFCAE11_PFCAE116                   (0x0040u)
+#define GPIO_PFCAE11_PFCAE117                   (0x0080u)
+#define GPIO_PFCAE11_PFCAE118                   (0x0100u)
+#define GPIO_PFCAE11_PFCAE119                   (0x0200u)
+#define GPIO_PFCAE11_PFCAE1110                  (0x0400u)
+#define GPIO_PFCAE11_PFCAE1111                  (0x0800u)
+#define GPIO_PFCAE11_PFCAE1112                  (0x1000u)
+#define GPIO_PFCAE11_PFCAE1113                  (0x2000u)
+#define GPIO_PFCAE11_PFCAE1114                  (0x4000u)
+#define GPIO_PFCAE11_PFCAE1115                  (0x8000u)
+
+#define GPIO_PIBC11_PIBC110                     (0x0001u)
+#define GPIO_PIBC11_PIBC111                     (0x0002u)
+#define GPIO_PIBC11_PIBC112                     (0x0004u)
+#define GPIO_PIBC11_PIBC113                     (0x0008u)
+#define GPIO_PIBC11_PIBC114                     (0x0010u)
+#define GPIO_PIBC11_PIBC115                     (0x0020u)
+#define GPIO_PIBC11_PIBC116                     (0x0040u)
+#define GPIO_PIBC11_PIBC117                     (0x0080u)
+#define GPIO_PIBC11_PIBC118                     (0x0100u)
+#define GPIO_PIBC11_PIBC119                     (0x0200u)
+#define GPIO_PIBC11_PIBC1110                    (0x0400u)
+#define GPIO_PIBC11_PIBC1111                    (0x0800u)
+#define GPIO_PIBC11_PIBC1112                    (0x1000u)
+#define GPIO_PIBC11_PIBC1113                    (0x2000u)
+#define GPIO_PIBC11_PIBC1114                    (0x4000u)
+#define GPIO_PIBC11_PIBC1115                    (0x8000u)
+
+#define GPIO_PBDC11_PBDC110                     (0x0001u)
+#define GPIO_PBDC11_PBDC111                     (0x0002u)
+#define GPIO_PBDC11_PBDC112                     (0x0004u)
+#define GPIO_PBDC11_PBDC113                     (0x0008u)
+#define GPIO_PBDC11_PBDC114                     (0x0010u)
+#define GPIO_PBDC11_PBDC115                     (0x0020u)
+#define GPIO_PBDC11_PBDC116                     (0x0040u)
+#define GPIO_PBDC11_PBDC117                     (0x0080u)
+#define GPIO_PBDC11_PBDC118                     (0x0100u)
+#define GPIO_PBDC11_PBDC119                     (0x0200u)
+#define GPIO_PBDC11_PBDC1110                    (0x0400u)
+#define GPIO_PBDC11_PBDC1111                    (0x0800u)
+#define GPIO_PBDC11_PBDC1112                    (0x1000u)
+#define GPIO_PBDC11_PBDC1113                    (0x2000u)
+#define GPIO_PBDC11_PBDC1114                    (0x4000u)
+#define GPIO_PBDC11_PBDC1115                    (0x8000u)
+
+#define GPIO_PIPC11_PIPC110                     (0x0001u)
+#define GPIO_PIPC11_PIPC111                     (0x0002u)
+#define GPIO_PIPC11_PIPC112                     (0x0004u)
+#define GPIO_PIPC11_PIPC113                     (0x0008u)
+#define GPIO_PIPC11_PIPC114                     (0x0010u)
+#define GPIO_PIPC11_PIPC115                     (0x0020u)
+#define GPIO_PIPC11_PIPC116                     (0x0040u)
+#define GPIO_PIPC11_PIPC117                     (0x0080u)
+#define GPIO_PIPC11_PIPC118                     (0x0100u)
+#define GPIO_PIPC11_PIPC119                     (0x0200u)
+#define GPIO_PIPC11_PIPC1110                    (0x0400u)
+#define GPIO_PIPC11_PIPC1111                    (0x0800u)
+#define GPIO_PIPC11_PIPC1112                    (0x1000u)
+#define GPIO_PIPC11_PIPC1113                    (0x2000u)
+#define GPIO_PIPC11_PIPC1114                    (0x4000u)
+#define GPIO_PIPC11_PIPC1115                    (0x8000u)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- P0 ---- */
+#define GPIO_PPR0_PPR00_SHIFT                   (0u)
+#define GPIO_PPR0_PPR01_SHIFT                   (1u)
+#define GPIO_PPR0_PPR02_SHIFT                   (2u)
+#define GPIO_PPR0_PPR03_SHIFT                   (3u)
+#define GPIO_PPR0_PPR04_SHIFT                   (4u)
+#define GPIO_PPR0_PPR05_SHIFT                   (5u)
+
+#define GPIO_PMC0_PMC04_SHIFT                   (4u)
+#define GPIO_PMC0_PMC05_SHIFT                   (5u)
+
+#define GPIO_PMCSR0_PMCSR04_SHIFT               (4u)
+#define GPIO_PMCSR0_PMCSR05_SHIFT               (5u)
+
+#define GPIO_PIBC0_PIBC00_SHIFT                 (0u)
+#define GPIO_PIBC0_PIBC01_SHIFT                 (1u)
+#define GPIO_PIBC0_PIBC02_SHIFT                 (2u)
+#define GPIO_PIBC0_PIBC03_SHIFT                 (3u)
+#define GPIO_PIBC0_PIBC04_SHIFT                 (4u)
+#define GPIO_PIBC0_PIBC05_SHIFT                 (5u)
+
+/* ---- P1 ---- */
+#define GPIO_P1_P10_SHIFT                       (0u)
+#define GPIO_P1_P11_SHIFT                       (1u)
+#define GPIO_P1_P12_SHIFT                       (2u)
+#define GPIO_P1_P13_SHIFT                       (3u)
+#define GPIO_P1_P14_SHIFT                       (4u)
+#define GPIO_P1_P15_SHIFT                       (5u)
+#define GPIO_P1_P16_SHIFT                       (6u)
+#define GPIO_P1_P17_SHIFT                       (7u)
+
+#define GPIO_PSR1_PSR10_SHIFT                   (0u)
+#define GPIO_PSR1_PSR11_SHIFT                   (1u)
+#define GPIO_PSR1_PSR12_SHIFT                   (2u)
+#define GPIO_PSR1_PSR13_SHIFT                   (3u)
+#define GPIO_PSR1_PSR14_SHIFT                   (4u)
+#define GPIO_PSR1_PSR15_SHIFT                   (5u)
+#define GPIO_PSR1_PSR16_SHIFT                   (6u)
+#define GPIO_PSR1_PSR17_SHIFT                   (7u)
+#define GPIO_PSR1_PSR116_SHIFT                  (16u)
+#define GPIO_PSR1_PSR117_SHIFT                  (17u)
+#define GPIO_PSR1_PSR118_SHIFT                  (18u)
+#define GPIO_PSR1_PSR119_SHIFT                  (19u)
+#define GPIO_PSR1_PSR120_SHIFT                  (20u)
+#define GPIO_PSR1_PSR121_SHIFT                  (21u)
+#define GPIO_PSR1_PSR122_SHIFT                  (22u)
+#define GPIO_PSR1_PSR123_SHIFT                  (23u)
+
+#define GPIO_PPR1_PPR10_SHIFT                   (0u)
+#define GPIO_PPR1_PPR11_SHIFT                   (1u)
+#define GPIO_PPR1_PPR12_SHIFT                   (2u)
+#define GPIO_PPR1_PPR13_SHIFT                   (3u)
+#define GPIO_PPR1_PPR14_SHIFT                   (4u)
+#define GPIO_PPR1_PPR15_SHIFT                   (5u)
+#define GPIO_PPR1_PPR16_SHIFT                   (6u)
+#define GPIO_PPR1_PPR17_SHIFT                   (7u)
+#define GPIO_PPR1_PPR18_SHIFT                   (8u)
+#define GPIO_PPR1_PPR19_SHIFT                   (9u)
+#define GPIO_PPR1_PPR110_SHIFT                  (10u)
+#define GPIO_PPR1_PPR111_SHIFT                  (11u)
+#define GPIO_PPR1_PPR112_SHIFT                  (12u)
+#define GPIO_PPR1_PPR113_SHIFT                  (13u)
+#define GPIO_PPR1_PPR114_SHIFT                  (14u)
+#define GPIO_PPR1_PPR115_SHIFT                  (15u)
+
+#define GPIO_PM1_PM10_SHIFT                     (0u)
+#define GPIO_PM1_PM11_SHIFT                     (1u)
+#define GPIO_PM1_PM12_SHIFT                     (2u)
+#define GPIO_PM1_PM13_SHIFT                     (3u)
+#define GPIO_PM1_PM14_SHIFT                     (4u)
+#define GPIO_PM1_PM15_SHIFT                     (5u)
+#define GPIO_PM1_PM16_SHIFT                     (6u)
+#define GPIO_PM1_PM17_SHIFT                     (7u)
+
+#define GPIO_PMC1_PMC10_SHIFT                   (0u)
+#define GPIO_PMC1_PMC11_SHIFT                   (1u)
+#define GPIO_PMC1_PMC12_SHIFT                   (2u)
+#define GPIO_PMC1_PMC13_SHIFT                   (3u)
+#define GPIO_PMC1_PMC14_SHIFT                   (4u)
+#define GPIO_PMC1_PMC15_SHIFT                   (5u)
+#define GPIO_PMC1_PMC16_SHIFT                   (6u)
+#define GPIO_PMC1_PMC17_SHIFT                   (7u)
+#define GPIO_PMC1_PMC18_SHIFT                   (8u)
+#define GPIO_PMC1_PMC19_SHIFT                   (9u)
+#define GPIO_PMC1_PMC110_SHIFT                  (10u)
+#define GPIO_PMC1_PMC111_SHIFT                  (11u)
+#define GPIO_PMC1_PMC112_SHIFT                  (12u)
+#define GPIO_PMC1_PMC113_SHIFT                  (13u)
+#define GPIO_PMC1_PMC114_SHIFT                  (14u)
+#define GPIO_PMC1_PMC115_SHIFT                  (15u)
+
+#define GPIO_PFC1_PFC10_SHIFT                   (0u)
+#define GPIO_PFC1_PFC11_SHIFT                   (1u)
+#define GPIO_PFC1_PFC12_SHIFT                   (2u)
+#define GPIO_PFC1_PFC13_SHIFT                   (3u)
+#define GPIO_PFC1_PFC14_SHIFT                   (4u)
+#define GPIO_PFC1_PFC15_SHIFT                   (5u)
+#define GPIO_PFC1_PFC16_SHIFT                   (6u)
+#define GPIO_PFC1_PFC17_SHIFT                   (7u)
+#define GPIO_PFC1_PFC18_SHIFT                   (8u)
+#define GPIO_PFC1_PFC19_SHIFT                   (9u)
+#define GPIO_PFC1_PFC110_SHIFT                  (10u)
+#define GPIO_PFC1_PFC111_SHIFT                  (11u)
+#define GPIO_PFC1_PFC112_SHIFT                  (12u)
+#define GPIO_PFC1_PFC113_SHIFT                  (13u)
+#define GPIO_PFC1_PFC114_SHIFT                  (14u)
+#define GPIO_PFC1_PFC115_SHIFT                  (15u)
+
+#define GPIO_PFCE1_PFCE10_SHIFT                 (0u)
+#define GPIO_PFCE1_PFCE11_SHIFT                 (1u)
+#define GPIO_PFCE1_PFCE12_SHIFT                 (2u)
+#define GPIO_PFCE1_PFCE13_SHIFT                 (3u)
+#define GPIO_PFCE1_PFCE14_SHIFT                 (4u)
+#define GPIO_PFCE1_PFCE15_SHIFT                 (5u)
+#define GPIO_PFCE1_PFCE16_SHIFT                 (6u)
+#define GPIO_PFCE1_PFCE17_SHIFT                 (7u)
+#define GPIO_PFCE1_PFCE18_SHIFT                 (8u)
+#define GPIO_PFCE1_PFCE19_SHIFT                 (9u)
+#define GPIO_PFCE1_PFCE110_SHIFT                (10u)
+#define GPIO_PFCE1_PFCE111_SHIFT                (11u)
+#define GPIO_PFCE1_PFCE112_SHIFT                (12u)
+#define GPIO_PFCE1_PFCE113_SHIFT                (13u)
+#define GPIO_PFCE1_PFCE114_SHIFT                (14u)
+#define GPIO_PFCE1_PFCE115_SHIFT                (15u)
+
+#define GPIO_PNOT1_PNOT10_SHIFT                 (0u)
+#define GPIO_PNOT1_PNOT11_SHIFT                 (1u)
+#define GPIO_PNOT1_PNOT12_SHIFT                 (2u)
+#define GPIO_PNOT1_PNOT13_SHIFT                 (3u)
+#define GPIO_PNOT1_PNOT14_SHIFT                 (4u)
+#define GPIO_PNOT1_PNOT15_SHIFT                 (5u)
+#define GPIO_PNOT1_PNOT16_SHIFT                 (6u)
+#define GPIO_PNOT1_PNOT17_SHIFT                 (7u)
+
+#define GPIO_PMSR1_PMSR10_SHIFT                 (0u)
+#define GPIO_PMSR1_PMSR11_SHIFT                 (1u)
+#define GPIO_PMSR1_PMSR12_SHIFT                 (2u)
+#define GPIO_PMSR1_PMSR13_SHIFT                 (3u)
+#define GPIO_PMSR1_PMSR14_SHIFT                 (4u)
+#define GPIO_PMSR1_PMSR15_SHIFT                 (5u)
+#define GPIO_PMSR1_PMSR16_SHIFT                 (6u)
+#define GPIO_PMSR1_PMSR17_SHIFT                 (7u)
+#define GPIO_PMSR1_PMSR116_SHIFT                (16u)
+#define GPIO_PMSR1_PMSR117_SHIFT                (17u)
+#define GPIO_PMSR1_PMSR118_SHIFT                (18u)
+#define GPIO_PMSR1_PMSR119_SHIFT                (19u)
+#define GPIO_PMSR1_PMSR120_SHIFT                (20u)
+#define GPIO_PMSR1_PMSR121_SHIFT                (21u)
+#define GPIO_PMSR1_PMSR122_SHIFT                (22u)
+#define GPIO_PMSR1_PMSR123_SHIFT                (23u)
+
+#define GPIO_PMCSR1_PMCSR10_SHIFT               (0u)
+#define GPIO_PMCSR1_PMCSR11_SHIFT               (1u)
+#define GPIO_PMCSR1_PMCSR12_SHIFT               (2u)
+#define GPIO_PMCSR1_PMCSR13_SHIFT               (3u)
+#define GPIO_PMCSR1_PMCSR14_SHIFT               (4u)
+#define GPIO_PMCSR1_PMCSR15_SHIFT               (5u)
+#define GPIO_PMCSR1_PMCSR16_SHIFT               (6u)
+#define GPIO_PMCSR1_PMCSR17_SHIFT               (7u)
+#define GPIO_PMCSR1_PMCSR116_SHIFT              (16u)
+#define GPIO_PMCSR1_PMCSR117_SHIFT              (17u)
+#define GPIO_PMCSR1_PMCSR118_SHIFT              (18u)
+#define GPIO_PMCSR1_PMCSR119_SHIFT              (19u)
+#define GPIO_PMCSR1_PMCSR120_SHIFT              (20u)
+#define GPIO_PMCSR1_PMCSR121_SHIFT              (21u)
+#define GPIO_PMCSR1_PMCSR122_SHIFT              (22u)
+#define GPIO_PMCSR1_PMCSR123_SHIFT              (23u)
+
+#define GPIO_PFCAE1_PFCAE10_SHIFT               (0u)
+#define GPIO_PFCAE1_PFCAE11_SHIFT               (1u)
+#define GPIO_PFCAE1_PFCAE12_SHIFT               (2u)
+#define GPIO_PFCAE1_PFCAE13_SHIFT               (3u)
+#define GPIO_PFCAE1_PFCAE14_SHIFT               (4u)
+#define GPIO_PFCAE1_PFCAE15_SHIFT               (5u)
+#define GPIO_PFCAE1_PFCAE16_SHIFT               (6u)
+#define GPIO_PFCAE1_PFCAE17_SHIFT               (7u)
+#define GPIO_PFCAE1_PFCAE18_SHIFT               (8u)
+#define GPIO_PFCAE1_PFCAE19_SHIFT               (9u)
+#define GPIO_PFCAE1_PFCAE110_SHIFT              (10u)
+#define GPIO_PFCAE1_PFCAE111_SHIFT              (11u)
+#define GPIO_PFCAE1_PFCAE112_SHIFT              (12u)
+#define GPIO_PFCAE1_PFCAE113_SHIFT              (13u)
+#define GPIO_PFCAE1_PFCAE114_SHIFT              (14u)
+#define GPIO_PFCAE1_PFCAE115_SHIFT              (15u)
+
+#define GPIO_PIBC1_PIBC10_SHIFT                 (0u)
+#define GPIO_PIBC1_PIBC11_SHIFT                 (1u)
+#define GPIO_PIBC1_PIBC12_SHIFT                 (2u)
+#define GPIO_PIBC1_PIBC13_SHIFT                 (3u)
+#define GPIO_PIBC1_PIBC14_SHIFT                 (4u)
+#define GPIO_PIBC1_PIBC15_SHIFT                 (5u)
+#define GPIO_PIBC1_PIBC16_SHIFT                 (6u)
+#define GPIO_PIBC1_PIBC17_SHIFT                 (7u)
+#define GPIO_PIBC1_PIBC18_SHIFT                 (8u)
+#define GPIO_PIBC1_PIBC19_SHIFT                 (9u)
+#define GPIO_PIBC1_PIBC110_SHIFT                (10u)
+#define GPIO_PIBC1_PIBC111_SHIFT                (11u)
+#define GPIO_PIBC1_PIBC112_SHIFT                (12u)
+#define GPIO_PIBC1_PIBC113_SHIFT                (13u)
+#define GPIO_PIBC1_PIBC114_SHIFT                (14u)
+#define GPIO_PIBC1_PIBC115_SHIFT                (15u)
+
+#define GPIO_PBDC1_PBDC10_SHIFT                 (0u)
+#define GPIO_PBDC1_PBDC11_SHIFT                 (1u)
+#define GPIO_PBDC1_PBDC12_SHIFT                 (2u)
+#define GPIO_PBDC1_PBDC13_SHIFT                 (3u)
+#define GPIO_PBDC1_PBDC14_SHIFT                 (4u)
+#define GPIO_PBDC1_PBDC15_SHIFT                 (5u)
+#define GPIO_PBDC1_PBDC16_SHIFT                 (6u)
+#define GPIO_PBDC1_PBDC17_SHIFT                 (7u)
+#define GPIO_PBDC1_PBDC18_SHIFT                 (8u)
+#define GPIO_PBDC1_PBDC19_SHIFT                 (9u)
+#define GPIO_PBDC1_PBDC110_SHIFT                (10u)
+#define GPIO_PBDC1_PBDC111_SHIFT                (11u)
+#define GPIO_PBDC1_PBDC112_SHIFT                (12u)
+#define GPIO_PBDC1_PBDC113_SHIFT                (13u)
+#define GPIO_PBDC1_PBDC114_SHIFT                (14u)
+#define GPIO_PBDC1_PBDC115_SHIFT                (15u)
+
+#define GPIO_PIPC1_PIPC10_SHIFT                 (0u)
+#define GPIO_PIPC1_PIPC11_SHIFT                 (1u)
+#define GPIO_PIPC1_PIPC12_SHIFT                 (2u)
+#define GPIO_PIPC1_PIPC13_SHIFT                 (3u)
+#define GPIO_PIPC1_PIPC14_SHIFT                 (4u)
+#define GPIO_PIPC1_PIPC15_SHIFT                 (5u)
+#define GPIO_PIPC1_PIPC16_SHIFT                 (6u)
+#define GPIO_PIPC1_PIPC17_SHIFT                 (7u)
+
+/* ---- P2 ---- */
+#define GPIO_P2_P20_SHIFT                       (0u)
+#define GPIO_P2_P21_SHIFT                       (1u)
+#define GPIO_P2_P22_SHIFT                       (2u)
+#define GPIO_P2_P23_SHIFT                       (3u)
+#define GPIO_P2_P24_SHIFT                       (4u)
+#define GPIO_P2_P25_SHIFT                       (5u)
+#define GPIO_P2_P26_SHIFT                       (6u)
+#define GPIO_P2_P27_SHIFT                       (7u)
+#define GPIO_P2_P28_SHIFT                       (8u)
+#define GPIO_P2_P29_SHIFT                       (9u)
+#define GPIO_P2_P210_SHIFT                      (10u)
+#define GPIO_P2_P211_SHIFT                      (11u)
+#define GPIO_P2_P212_SHIFT                      (12u)
+#define GPIO_P2_P213_SHIFT                      (13u)
+#define GPIO_P2_P214_SHIFT                      (14u)
+#define GPIO_P2_P215_SHIFT                      (15u)
+
+#define GPIO_PSR2_PSR20_SHIFT                   (0u)
+#define GPIO_PSR2_PSR21_SHIFT                   (1u)
+#define GPIO_PSR2_PSR22_SHIFT                   (2u)
+#define GPIO_PSR2_PSR23_SHIFT                   (3u)
+#define GPIO_PSR2_PSR24_SHIFT                   (4u)
+#define GPIO_PSR2_PSR25_SHIFT                   (5u)
+#define GPIO_PSR2_PSR26_SHIFT                   (6u)
+#define GPIO_PSR2_PSR27_SHIFT                   (7u)
+#define GPIO_PSR2_PSR28_SHIFT                   (8u)
+#define GPIO_PSR2_PSR29_SHIFT                   (9u)
+#define GPIO_PSR2_PSR210_SHIFT                  (10u)
+#define GPIO_PSR2_PSR211_SHIFT                  (11u)
+#define GPIO_PSR2_PSR212_SHIFT                  (12u)
+#define GPIO_PSR2_PSR213_SHIFT                  (13u)
+#define GPIO_PSR2_PSR214_SHIFT                  (14u)
+#define GPIO_PSR2_PSR215_SHIFT                  (15u)
+#define GPIO_PSR2_PSR216_SHIFT                  (16u)
+#define GPIO_PSR2_PSR217_SHIFT                  (17u)
+#define GPIO_PSR2_PSR218_SHIFT                  (18u)
+#define GPIO_PSR2_PSR219_SHIFT                  (19u)
+#define GPIO_PSR2_PSR220_SHIFT                  (20u)
+#define GPIO_PSR2_PSR221_SHIFT                  (21u)
+#define GPIO_PSR2_PSR222_SHIFT                  (22u)
+#define GPIO_PSR2_PSR223_SHIFT                  (23u)
+#define GPIO_PSR2_PSR224_SHIFT                  (24u)
+#define GPIO_PSR2_PSR225_SHIFT                  (25u)
+#define GPIO_PSR2_PSR226_SHIFT                  (26u)
+#define GPIO_PSR2_PSR227_SHIFT                  (27u)
+#define GPIO_PSR2_PSR228_SHIFT                  (28u)
+#define GPIO_PSR2_PSR229_SHIFT                  (29u)
+#define GPIO_PSR2_PSR230_SHIFT                  (30u)
+#define GPIO_PSR2_PSR231_SHIFT                  (31u)
+
+#define GPIO_PPR2_PPR20_SHIFT                   (0u)
+#define GPIO_PPR2_PPR21_SHIFT                   (1u)
+#define GPIO_PPR2_PPR22_SHIFT                   (2u)
+#define GPIO_PPR2_PPR23_SHIFT                   (3u)
+#define GPIO_PPR2_PPR24_SHIFT                   (4u)
+#define GPIO_PPR2_PPR25_SHIFT                   (5u)
+#define GPIO_PPR2_PPR26_SHIFT                   (6u)
+#define GPIO_PPR2_PPR27_SHIFT                   (7u)
+#define GPIO_PPR2_PPR28_SHIFT                   (8u)
+#define GPIO_PPR2_PPR29_SHIFT                   (9u)
+#define GPIO_PPR2_PPR210_SHIFT                  (10u)
+#define GPIO_PPR2_PPR211_SHIFT                  (11u)
+#define GPIO_PPR2_PPR212_SHIFT                  (12u)
+#define GPIO_PPR2_PPR213_SHIFT                  (13u)
+#define GPIO_PPR2_PPR214_SHIFT                  (14u)
+#define GPIO_PPR2_PPR215_SHIFT                  (15u)
+
+#define GPIO_PM2_PM20_SHIFT                     (0u)
+#define GPIO_PM2_PM21_SHIFT                     (1u)
+#define GPIO_PM2_PM22_SHIFT                     (2u)
+#define GPIO_PM2_PM23_SHIFT                     (3u)
+#define GPIO_PM2_PM24_SHIFT                     (4u)
+#define GPIO_PM2_PM25_SHIFT                     (5u)
+#define GPIO_PM2_PM26_SHIFT                     (6u)
+#define GPIO_PM2_PM27_SHIFT                     (7u)
+#define GPIO_PM2_PM28_SHIFT                     (8u)
+#define GPIO_PM2_PM29_SHIFT                     (9u)
+#define GPIO_PM2_PM210_SHIFT                    (10u)
+#define GPIO_PM2_PM211_SHIFT                    (11u)
+#define GPIO_PM2_PM212_SHIFT                    (12u)
+#define GPIO_PM2_PM213_SHIFT                    (13u)
+#define GPIO_PM2_PM214_SHIFT                    (14u)
+#define GPIO_PM2_PM215_SHIFT                    (15u)
+
+#define GPIO_PMC2_PMC20_SHIFT                   (0u)
+#define GPIO_PMC2_PMC21_SHIFT                   (1u)
+#define GPIO_PMC2_PMC22_SHIFT                   (2u)
+#define GPIO_PMC2_PMC23_SHIFT                   (3u)
+#define GPIO_PMC2_PMC24_SHIFT                   (4u)
+#define GPIO_PMC2_PMC25_SHIFT                   (5u)
+#define GPIO_PMC2_PMC26_SHIFT                   (6u)
+#define GPIO_PMC2_PMC27_SHIFT                   (7u)
+#define GPIO_PMC2_PMC28_SHIFT                   (8u)
+#define GPIO_PMC2_PMC29_SHIFT                   (9u)
+#define GPIO_PMC2_PMC210_SHIFT                  (10u)
+#define GPIO_PMC2_PMC211_SHIFT                  (11u)
+#define GPIO_PMC2_PMC212_SHIFT                  (12u)
+#define GPIO_PMC2_PMC213_SHIFT                  (13u)
+#define GPIO_PMC2_PMC214_SHIFT                  (14u)
+#define GPIO_PMC2_PMC215_SHIFT                  (15u)
+
+#define GPIO_PFC2_PFC20_SHIFT                   (0u)
+#define GPIO_PFC2_PFC21_SHIFT                   (1u)
+#define GPIO_PFC2_PFC22_SHIFT                   (2u)
+#define GPIO_PFC2_PFC23_SHIFT                   (3u)
+#define GPIO_PFC2_PFC24_SHIFT                   (4u)
+#define GPIO_PFC2_PFC25_SHIFT                   (5u)
+#define GPIO_PFC2_PFC26_SHIFT                   (6u)
+#define GPIO_PFC2_PFC27_SHIFT                   (7u)
+#define GPIO_PFC2_PFC28_SHIFT                   (8u)
+#define GPIO_PFC2_PFC29_SHIFT                   (9u)
+#define GPIO_PFC2_PFC210_SHIFT                  (10u)
+#define GPIO_PFC2_PFC211_SHIFT                  (11u)
+#define GPIO_PFC2_PFC212_SHIFT                  (12u)
+#define GPIO_PFC2_PFC213_SHIFT                  (13u)
+#define GPIO_PFC2_PFC214_SHIFT                  (14u)
+#define GPIO_PFC2_PFC215_SHIFT                  (15u)
+
+#define GPIO_PFCE2_PFCE20_SHIFT                 (0u)
+#define GPIO_PFCE2_PFCE21_SHIFT                 (1u)
+#define GPIO_PFCE2_PFCE22_SHIFT                 (2u)
+#define GPIO_PFCE2_PFCE23_SHIFT                 (3u)
+#define GPIO_PFCE2_PFCE24_SHIFT                 (4u)
+#define GPIO_PFCE2_PFCE25_SHIFT                 (5u)
+#define GPIO_PFCE2_PFCE26_SHIFT                 (6u)
+#define GPIO_PFCE2_PFCE27_SHIFT                 (7u)
+#define GPIO_PFCE2_PFCE28_SHIFT                 (8u)
+#define GPIO_PFCE2_PFCE29_SHIFT                 (9u)
+#define GPIO_PFCE2_PFCE210_SHIFT                (10u)
+#define GPIO_PFCE2_PFCE211_SHIFT                (11u)
+#define GPIO_PFCE2_PFCE212_SHIFT                (12u)
+#define GPIO_PFCE2_PFCE213_SHIFT                (13u)
+#define GPIO_PFCE2_PFCE214_SHIFT                (14u)
+#define GPIO_PFCE2_PFCE215_SHIFT                (15u)
+
+#define GPIO_PNOT2_PNOT20_SHIFT                 (0u)
+#define GPIO_PNOT2_PNOT21_SHIFT                 (1u)
+#define GPIO_PNOT2_PNOT22_SHIFT                 (2u)
+#define GPIO_PNOT2_PNOT23_SHIFT                 (3u)
+#define GPIO_PNOT2_PNOT24_SHIFT                 (4u)
+#define GPIO_PNOT2_PNOT25_SHIFT                 (5u)
+#define GPIO_PNOT2_PNOT26_SHIFT                 (6u)
+#define GPIO_PNOT2_PNOT27_SHIFT                 (7u)
+#define GPIO_PNOT2_PNOT28_SHIFT                 (8u)
+#define GPIO_PNOT2_PNOT29_SHIFT                 (9u)
+#define GPIO_PNOT2_PNOT210_SHIFT                (10u)
+#define GPIO_PNOT2_PNOT211_SHIFT                (11u)
+#define GPIO_PNOT2_PNOT212_SHIFT                (12u)
+#define GPIO_PNOT2_PNOT213_SHIFT                (13u)
+#define GPIO_PNOT2_PNOT214_SHIFT                (14u)
+#define GPIO_PNOT2_PNOT215_SHIFT                (15u)
+
+#define GPIO_PMSR2_PMSR20_SHIFT                 (0u)
+#define GPIO_PMSR2_PMSR21_SHIFT                 (1u)
+#define GPIO_PMSR2_PMSR22_SHIFT                 (2u)
+#define GPIO_PMSR2_PMSR23_SHIFT                 (3u)
+#define GPIO_PMSR2_PMSR24_SHIFT                 (4u)
+#define GPIO_PMSR2_PMSR25_SHIFT                 (5u)
+#define GPIO_PMSR2_PMSR26_SHIFT                 (6u)
+#define GPIO_PMSR2_PMSR27_SHIFT                 (7u)
+#define GPIO_PMSR2_PMSR28_SHIFT                 (8u)
+#define GPIO_PMSR2_PMSR29_SHIFT                 (9u)
+#define GPIO_PMSR2_PMSR210_SHIFT                (10u)
+#define GPIO_PMSR2_PMSR211_SHIFT                (11u)
+#define GPIO_PMSR2_PMSR212_SHIFT                (12u)
+#define GPIO_PMSR2_PMSR213_SHIFT                (13u)
+#define GPIO_PMSR2_PMSR214_SHIFT                (14u)
+#define GPIO_PMSR2_PMSR215_SHIFT                (15u)
+#define GPIO_PMSR2_PMSR216_SHIFT                (16u)
+#define GPIO_PMSR2_PMSR217_SHIFT                (17u)
+#define GPIO_PMSR2_PMSR218_SHIFT                (18u)
+#define GPIO_PMSR2_PMSR219_SHIFT                (19u)
+#define GPIO_PMSR2_PMSR220_SHIFT                (20u)
+#define GPIO_PMSR2_PMSR221_SHIFT                (21u)
+#define GPIO_PMSR2_PMSR222_SHIFT                (22u)
+#define GPIO_PMSR2_PMSR223_SHIFT                (23u)
+#define GPIO_PMSR2_PMSR224_SHIFT                (24u)
+#define GPIO_PMSR2_PMSR225_SHIFT                (25u)
+#define GPIO_PMSR2_PMSR226_SHIFT                (26u)
+#define GPIO_PMSR2_PMSR227_SHIFT                (27u)
+#define GPIO_PMSR2_PMSR228_SHIFT                (28u)
+#define GPIO_PMSR2_PMSR229_SHIFT                (29u)
+#define GPIO_PMSR2_PMSR230_SHIFT                (30u)
+#define GPIO_PMSR2_PMSR231_SHIFT                (31u)
+
+#define GPIO_PMCSR2_PMCSR20_SHIFT               (0u)
+#define GPIO_PMCSR2_PMCSR21_SHIFT               (1u)
+#define GPIO_PMCSR2_PMCSR22_SHIFT               (2u)
+#define GPIO_PMCSR2_PMCSR23_SHIFT               (3u)
+#define GPIO_PMCSR2_PMCSR24_SHIFT               (4u)
+#define GPIO_PMCSR2_PMCSR25_SHIFT               (5u)
+#define GPIO_PMCSR2_PMCSR26_SHIFT               (6u)
+#define GPIO_PMCSR2_PMCSR27_SHIFT               (7u)
+#define GPIO_PMCSR2_PMCSR28_SHIFT               (8u)
+#define GPIO_PMCSR2_PMCSR29_SHIFT               (9u)
+#define GPIO_PMCSR2_PMCSR210_SHIFT              (10u)
+#define GPIO_PMCSR2_PMCSR211_SHIFT              (11u)
+#define GPIO_PMCSR2_PMCSR212_SHIFT              (12u)
+#define GPIO_PMCSR2_PMCSR213_SHIFT              (13u)
+#define GPIO_PMCSR2_PMCSR214_SHIFT              (14u)
+#define GPIO_PMCSR2_PMCSR215_SHIFT              (15u)
+#define GPIO_PMCSR2_PMCSR216_SHIFT              (16u)
+#define GPIO_PMCSR2_PMCSR217_SHIFT              (17u)
+#define GPIO_PMCSR2_PMCSR218_SHIFT              (18u)
+#define GPIO_PMCSR2_PMCSR219_SHIFT              (19u)
+#define GPIO_PMCSR2_PMCSR220_SHIFT              (20u)
+#define GPIO_PMCSR2_PMCSR221_SHIFT              (21u)
+#define GPIO_PMCSR2_PMCSR222_SHIFT              (22u)
+#define GPIO_PMCSR2_PMCSR223_SHIFT              (23u)
+#define GPIO_PMCSR2_PMCSR224_SHIFT              (24u)
+#define GPIO_PMCSR2_PMCSR225_SHIFT              (25u)
+#define GPIO_PMCSR2_PMCSR226_SHIFT              (26u)
+#define GPIO_PMCSR2_PMCSR227_SHIFT              (27u)
+#define GPIO_PMCSR2_PMCSR228_SHIFT              (28u)
+#define GPIO_PMCSR2_PMCSR229_SHIFT              (29u)
+#define GPIO_PMCSR2_PMCSR230_SHIFT              (30u)
+#define GPIO_PMCSR2_PMCSR231_SHIFT              (31u)
+
+#define GPIO_PFCAE2_PFCAE20_SHIFT               (0u)
+#define GPIO_PFCAE2_PFCAE21_SHIFT               (1u)
+#define GPIO_PFCAE2_PFCAE22_SHIFT               (2u)
+#define GPIO_PFCAE2_PFCAE23_SHIFT               (3u)
+#define GPIO_PFCAE2_PFCAE24_SHIFT               (4u)
+#define GPIO_PFCAE2_PFCAE25_SHIFT               (5u)
+#define GPIO_PFCAE2_PFCAE26_SHIFT               (6u)
+#define GPIO_PFCAE2_PFCAE27_SHIFT               (7u)
+#define GPIO_PFCAE2_PFCAE28_SHIFT               (8u)
+#define GPIO_PFCAE2_PFCAE29_SHIFT               (9u)
+#define GPIO_PFCAE2_PFCAE210_SHIFT              (10u)
+#define GPIO_PFCAE2_PFCAE211_SHIFT              (11u)
+#define GPIO_PFCAE2_PFCAE212_SHIFT              (12u)
+#define GPIO_PFCAE2_PFCAE213_SHIFT              (13u)
+#define GPIO_PFCAE2_PFCAE214_SHIFT              (14u)
+#define GPIO_PFCAE2_PFCAE215_SHIFT              (15u)
+
+#define GPIO_PIBC2_PIBC20_SHIFT                 (0u)
+#define GPIO_PIBC2_PIBC21_SHIFT                 (1u)
+#define GPIO_PIBC2_PIBC22_SHIFT                 (2u)
+#define GPIO_PIBC2_PIBC23_SHIFT                 (3u)
+#define GPIO_PIBC2_PIBC24_SHIFT                 (4u)
+#define GPIO_PIBC2_PIBC25_SHIFT                 (5u)
+#define GPIO_PIBC2_PIBC26_SHIFT                 (6u)
+#define GPIO_PIBC2_PIBC27_SHIFT                 (7u)
+#define GPIO_PIBC2_PIBC28_SHIFT                 (8u)
+#define GPIO_PIBC2_PIBC29_SHIFT                 (9u)
+#define GPIO_PIBC2_PIBC210_SHIFT                (10u)
+#define GPIO_PIBC2_PIBC211_SHIFT                (11u)
+#define GPIO_PIBC2_PIBC212_SHIFT                (12u)
+#define GPIO_PIBC2_PIBC213_SHIFT                (13u)
+#define GPIO_PIBC2_PIBC214_SHIFT                (14u)
+#define GPIO_PIBC2_PIBC215_SHIFT                (15u)
+
+#define GPIO_PBDC2_PBDC20_SHIFT                 (0u)
+#define GPIO_PBDC2_PBDC21_SHIFT                 (1u)
+#define GPIO_PBDC2_PBDC22_SHIFT                 (2u)
+#define GPIO_PBDC2_PBDC23_SHIFT                 (3u)
+#define GPIO_PBDC2_PBDC24_SHIFT                 (4u)
+#define GPIO_PBDC2_PBDC25_SHIFT                 (5u)
+#define GPIO_PBDC2_PBDC26_SHIFT                 (6u)
+#define GPIO_PBDC2_PBDC27_SHIFT                 (7u)
+#define GPIO_PBDC2_PBDC28_SHIFT                 (8u)
+#define GPIO_PBDC2_PBDC29_SHIFT                 (9u)
+#define GPIO_PBDC2_PBDC210_SHIFT                (10u)
+#define GPIO_PBDC2_PBDC211_SHIFT                (11u)
+#define GPIO_PBDC2_PBDC212_SHIFT                (12u)
+#define GPIO_PBDC2_PBDC213_SHIFT                (13u)
+#define GPIO_PBDC2_PBDC214_SHIFT                (14u)
+#define GPIO_PBDC2_PBDC215_SHIFT                (15u)
+
+#define GPIO_PIPC2_PIPC20_SHIFT                 (0u)
+#define GPIO_PIPC2_PIPC21_SHIFT                 (1u)
+#define GPIO_PIPC2_PIPC22_SHIFT                 (2u)
+#define GPIO_PIPC2_PIPC23_SHIFT                 (3u)
+#define GPIO_PIPC2_PIPC24_SHIFT                 (4u)
+#define GPIO_PIPC2_PIPC25_SHIFT                 (5u)
+#define GPIO_PIPC2_PIPC26_SHIFT                 (6u)
+#define GPIO_PIPC2_PIPC27_SHIFT                 (7u)
+#define GPIO_PIPC2_PIPC28_SHIFT                 (8u)
+#define GPIO_PIPC2_PIPC29_SHIFT                 (9u)
+#define GPIO_PIPC2_PIPC210_SHIFT                (10u)
+#define GPIO_PIPC2_PIPC211_SHIFT                (11u)
+#define GPIO_PIPC2_PIPC212_SHIFT                (12u)
+#define GPIO_PIPC2_PIPC213_SHIFT                (13u)
+#define GPIO_PIPC2_PIPC214_SHIFT                (14u)
+#define GPIO_PIPC2_PIPC215_SHIFT                (15u)
+
+/* ---- P3 ---- */
+#define GPIO_P3_P30_SHIFT                       (0u)
+#define GPIO_P3_P31_SHIFT                       (1u)
+#define GPIO_P3_P32_SHIFT                       (2u)
+#define GPIO_P3_P33_SHIFT                       (3u)
+#define GPIO_P3_P34_SHIFT                       (4u)
+#define GPIO_P3_P35_SHIFT                       (5u)
+#define GPIO_P3_P36_SHIFT                       (6u)
+#define GPIO_P3_P37_SHIFT                       (7u)
+#define GPIO_P3_P38_SHIFT                       (8u)
+#define GPIO_P3_P39_SHIFT                       (9u)
+#define GPIO_P3_P310_SHIFT                      (10u)
+#define GPIO_P3_P311_SHIFT                      (11u)
+#define GPIO_P3_P312_SHIFT                      (12u)
+#define GPIO_P3_P313_SHIFT                      (13u)
+#define GPIO_P3_P314_SHIFT                      (14u)
+#define GPIO_P3_P315_SHIFT                      (15u)
+
+#define GPIO_PSR3_PSR30_SHIFT                   (0u)
+#define GPIO_PSR3_PSR31_SHIFT                   (1u)
+#define GPIO_PSR3_PSR32_SHIFT                   (2u)
+#define GPIO_PSR3_PSR33_SHIFT                   (3u)
+#define GPIO_PSR3_PSR34_SHIFT                   (4u)
+#define GPIO_PSR3_PSR35_SHIFT                   (5u)
+#define GPIO_PSR3_PSR36_SHIFT                   (6u)
+#define GPIO_PSR3_PSR37_SHIFT                   (7u)
+#define GPIO_PSR3_PSR38_SHIFT                   (8u)
+#define GPIO_PSR3_PSR39_SHIFT                   (9u)
+#define GPIO_PSR3_PSR310_SHIFT                  (10u)
+#define GPIO_PSR3_PSR311_SHIFT                  (11u)
+#define GPIO_PSR3_PSR312_SHIFT                  (12u)
+#define GPIO_PSR3_PSR313_SHIFT                  (13u)
+#define GPIO_PSR3_PSR314_SHIFT                  (14u)
+#define GPIO_PSR3_PSR315_SHIFT                  (15u)
+#define GPIO_PSR3_PSR316_SHIFT                  (16u)
+#define GPIO_PSR3_PSR317_SHIFT                  (17u)
+#define GPIO_PSR3_PSR318_SHIFT                  (18u)
+#define GPIO_PSR3_PSR319_SHIFT                  (19u)
+#define GPIO_PSR3_PSR320_SHIFT                  (20u)
+#define GPIO_PSR3_PSR321_SHIFT                  (21u)
+#define GPIO_PSR3_PSR322_SHIFT                  (22u)
+#define GPIO_PSR3_PSR323_SHIFT                  (23u)
+#define GPIO_PSR3_PSR324_SHIFT                  (24u)
+#define GPIO_PSR3_PSR325_SHIFT                  (25u)
+#define GPIO_PSR3_PSR326_SHIFT                  (26u)
+#define GPIO_PSR3_PSR327_SHIFT                  (27u)
+#define GPIO_PSR3_PSR328_SHIFT                  (28u)
+#define GPIO_PSR3_PSR329_SHIFT                  (29u)
+#define GPIO_PSR3_PSR330_SHIFT                  (30u)
+#define GPIO_PSR3_PSR331_SHIFT                  (31u)
+
+#define GPIO_PPR3_PPR30_SHIFT                   (0u)
+#define GPIO_PPR3_PPR31_SHIFT                   (1u)
+#define GPIO_PPR3_PPR32_SHIFT                   (2u)
+#define GPIO_PPR3_PPR33_SHIFT                   (3u)
+#define GPIO_PPR3_PPR34_SHIFT                   (4u)
+#define GPIO_PPR3_PPR35_SHIFT                   (5u)
+#define GPIO_PPR3_PPR36_SHIFT                   (6u)
+#define GPIO_PPR3_PPR37_SHIFT                   (7u)
+#define GPIO_PPR3_PPR38_SHIFT                   (8u)
+#define GPIO_PPR3_PPR39_SHIFT                   (9u)
+#define GPIO_PPR3_PPR310_SHIFT                  (10u)
+#define GPIO_PPR3_PPR311_SHIFT                  (11u)
+#define GPIO_PPR3_PPR312_SHIFT                  (12u)
+#define GPIO_PPR3_PPR313_SHIFT                  (13u)
+#define GPIO_PPR3_PPR314_SHIFT                  (14u)
+#define GPIO_PPR3_PPR315_SHIFT                  (15u)
+
+#define GPIO_PM3_PM30_SHIFT                     (0u)
+#define GPIO_PM3_PM31_SHIFT                     (1u)
+#define GPIO_PM3_PM32_SHIFT                     (2u)
+#define GPIO_PM3_PM33_SHIFT                     (3u)
+#define GPIO_PM3_PM34_SHIFT                     (4u)
+#define GPIO_PM3_PM35_SHIFT                     (5u)
+#define GPIO_PM3_PM36_SHIFT                     (6u)
+#define GPIO_PM3_PM37_SHIFT                     (7u)
+#define GPIO_PM3_PM38_SHIFT                     (8u)
+#define GPIO_PM3_PM39_SHIFT                     (9u)
+#define GPIO_PM3_PM310_SHIFT                    (10u)
+#define GPIO_PM3_PM311_SHIFT                    (11u)
+#define GPIO_PM3_PM312_SHIFT                    (12u)
+#define GPIO_PM3_PM313_SHIFT                    (13u)
+#define GPIO_PM3_PM314_SHIFT                    (14u)
+#define GPIO_PM3_PM315_SHIFT                    (15u)
+
+#define GPIO_PMC3_PMC30_SHIFT                   (0u)
+#define GPIO_PMC3_PMC31_SHIFT                   (1u)
+#define GPIO_PMC3_PMC32_SHIFT                   (2u)
+#define GPIO_PMC3_PMC33_SHIFT                   (3u)
+#define GPIO_PMC3_PMC34_SHIFT                   (4u)
+#define GPIO_PMC3_PMC35_SHIFT                   (5u)
+#define GPIO_PMC3_PMC36_SHIFT                   (6u)
+#define GPIO_PMC3_PMC37_SHIFT                   (7u)
+#define GPIO_PMC3_PMC38_SHIFT                   (8u)
+#define GPIO_PMC3_PMC39_SHIFT                   (9u)
+#define GPIO_PMC3_PMC310_SHIFT                  (10u)
+#define GPIO_PMC3_PMC311_SHIFT                  (11u)
+#define GPIO_PMC3_PMC312_SHIFT                  (12u)
+#define GPIO_PMC3_PMC313_SHIFT                  (13u)
+#define GPIO_PMC3_PMC314_SHIFT                  (14u)
+#define GPIO_PMC3_PMC315_SHIFT                  (15u)
+
+#define GPIO_PFC3_PFC30_SHIFT                   (0u)
+#define GPIO_PFC3_PFC31_SHIFT                   (1u)
+#define GPIO_PFC3_PFC32_SHIFT                   (2u)
+#define GPIO_PFC3_PFC33_SHIFT                   (3u)
+#define GPIO_PFC3_PFC34_SHIFT                   (4u)
+#define GPIO_PFC3_PFC35_SHIFT                   (5u)
+#define GPIO_PFC3_PFC36_SHIFT                   (6u)
+#define GPIO_PFC3_PFC37_SHIFT                   (7u)
+#define GPIO_PFC3_PFC38_SHIFT                   (8u)
+#define GPIO_PFC3_PFC39_SHIFT                   (9u)
+#define GPIO_PFC3_PFC310_SHIFT                  (10u)
+#define GPIO_PFC3_PFC311_SHIFT                  (11u)
+#define GPIO_PFC3_PFC312_SHIFT                  (12u)
+#define GPIO_PFC3_PFC313_SHIFT                  (13u)
+#define GPIO_PFC3_PFC314_SHIFT                  (14u)
+#define GPIO_PFC3_PFC315_SHIFT                  (15u)
+
+#define GPIO_PFCE3_PFCE30_SHIFT                 (0u)
+#define GPIO_PFCE3_PFCE31_SHIFT                 (1u)
+#define GPIO_PFCE3_PFCE32_SHIFT                 (2u)
+#define GPIO_PFCE3_PFCE33_SHIFT                 (3u)
+#define GPIO_PFCE3_PFCE34_SHIFT                 (4u)
+#define GPIO_PFCE3_PFCE35_SHIFT                 (5u)
+#define GPIO_PFCE3_PFCE36_SHIFT                 (6u)
+#define GPIO_PFCE3_PFCE37_SHIFT                 (7u)
+#define GPIO_PFCE3_PFCE38_SHIFT                 (8u)
+#define GPIO_PFCE3_PFCE39_SHIFT                 (9u)
+#define GPIO_PFCE3_PFCE310_SHIFT                (10u)
+#define GPIO_PFCE3_PFCE311_SHIFT                (11u)
+#define GPIO_PFCE3_PFCE312_SHIFT                (12u)
+#define GPIO_PFCE3_PFCE313_SHIFT                (13u)
+#define GPIO_PFCE3_PFCE314_SHIFT                (14u)
+#define GPIO_PFCE3_PFCE315_SHIFT                (15u)
+
+#define GPIO_PNOT3_PNOT30_SHIFT                 (0u)
+#define GPIO_PNOT3_PNOT31_SHIFT                 (1u)
+#define GPIO_PNOT3_PNOT32_SHIFT                 (2u)
+#define GPIO_PNOT3_PNOT33_SHIFT                 (3u)
+#define GPIO_PNOT3_PNOT34_SHIFT                 (4u)
+#define GPIO_PNOT3_PNOT35_SHIFT                 (5u)
+#define GPIO_PNOT3_PNOT36_SHIFT                 (6u)
+#define GPIO_PNOT3_PNOT37_SHIFT                 (7u)
+#define GPIO_PNOT3_PNOT38_SHIFT                 (8u)
+#define GPIO_PNOT3_PNOT39_SHIFT                 (9u)
+#define GPIO_PNOT3_PNOT310_SHIFT                (10u)
+#define GPIO_PNOT3_PNOT311_SHIFT                (11u)
+#define GPIO_PNOT3_PNOT312_SHIFT                (12u)
+#define GPIO_PNOT3_PNOT313_SHIFT                (13u)
+#define GPIO_PNOT3_PNOT314_SHIFT                (14u)
+#define GPIO_PNOT3_PNOT315_SHIFT                (15u)
+
+#define GPIO_PMSR3_PMSR30_SHIFT                 (0u)
+#define GPIO_PMSR3_PMSR31_SHIFT                 (1u)
+#define GPIO_PMSR3_PMSR32_SHIFT                 (2u)
+#define GPIO_PMSR3_PMSR33_SHIFT                 (3u)
+#define GPIO_PMSR3_PMSR34_SHIFT                 (4u)
+#define GPIO_PMSR3_PMSR35_SHIFT                 (5u)
+#define GPIO_PMSR3_PMSR36_SHIFT                 (6u)
+#define GPIO_PMSR3_PMSR37_SHIFT                 (7u)
+#define GPIO_PMSR3_PMSR38_SHIFT                 (8u)
+#define GPIO_PMSR3_PMSR39_SHIFT                 (9u)
+#define GPIO_PMSR3_PMSR310_SHIFT                (10u)
+#define GPIO_PMSR3_PMSR311_SHIFT                (11u)
+#define GPIO_PMSR3_PMSR312_SHIFT                (12u)
+#define GPIO_PMSR3_PMSR313_SHIFT                (13u)
+#define GPIO_PMSR3_PMSR314_SHIFT                (14u)
+#define GPIO_PMSR3_PMSR315_SHIFT                (15u)
+#define GPIO_PMSR3_PMSR316_SHIFT                (16u)
+#define GPIO_PMSR3_PMSR317_SHIFT                (17u)
+#define GPIO_PMSR3_PMSR318_SHIFT                (18u)
+#define GPIO_PMSR3_PMSR319_SHIFT                (19u)
+#define GPIO_PMSR3_PMSR320_SHIFT                (20u)
+#define GPIO_PMSR3_PMSR321_SHIFT                (21u)
+#define GPIO_PMSR3_PMSR322_SHIFT                (22u)
+#define GPIO_PMSR3_PMSR323_SHIFT                (23u)
+#define GPIO_PMSR3_PMSR324_SHIFT                (24u)
+#define GPIO_PMSR3_PMSR325_SHIFT                (25u)
+#define GPIO_PMSR3_PMSR326_SHIFT                (26u)
+#define GPIO_PMSR3_PMSR327_SHIFT                (27u)
+#define GPIO_PMSR3_PMSR328_SHIFT                (28u)
+#define GPIO_PMSR3_PMSR329_SHIFT                (29u)
+#define GPIO_PMSR3_PMSR330_SHIFT                (30u)
+#define GPIO_PMSR3_PMSR331_SHIFT                (31u)
+
+#define GPIO_PMCSR3_PMCSR30_SHIFT               (0u)
+#define GPIO_PMCSR3_PMCSR31_SHIFT               (1u)
+#define GPIO_PMCSR3_PMCSR32_SHIFT               (2u)
+#define GPIO_PMCSR3_PMCSR33_SHIFT               (3u)
+#define GPIO_PMCSR3_PMCSR34_SHIFT               (4u)
+#define GPIO_PMCSR3_PMCSR35_SHIFT               (5u)
+#define GPIO_PMCSR3_PMCSR36_SHIFT               (6u)
+#define GPIO_PMCSR3_PMCSR37_SHIFT               (7u)
+#define GPIO_PMCSR3_PMCSR38_SHIFT               (8u)
+#define GPIO_PMCSR3_PMCSR39_SHIFT               (9u)
+#define GPIO_PMCSR3_PMCSR310_SHIFT              (10u)
+#define GPIO_PMCSR3_PMCSR311_SHIFT              (11u)
+#define GPIO_PMCSR3_PMCSR312_SHIFT              (12u)
+#define GPIO_PMCSR3_PMCSR313_SHIFT              (13u)
+#define GPIO_PMCSR3_PMCSR314_SHIFT              (14u)
+#define GPIO_PMCSR3_PMCSR315_SHIFT              (15u)
+#define GPIO_PMCSR3_PMCSR316_SHIFT              (16u)
+#define GPIO_PMCSR3_PMCSR317_SHIFT              (17u)
+#define GPIO_PMCSR3_PMCSR318_SHIFT              (18u)
+#define GPIO_PMCSR3_PMCSR319_SHIFT              (19u)
+#define GPIO_PMCSR3_PMCSR320_SHIFT              (20u)
+#define GPIO_PMCSR3_PMCSR321_SHIFT              (21u)
+#define GPIO_PMCSR3_PMCSR322_SHIFT              (22u)
+#define GPIO_PMCSR3_PMCSR323_SHIFT              (23u)
+#define GPIO_PMCSR3_PMCSR324_SHIFT              (24u)
+#define GPIO_PMCSR3_PMCSR325_SHIFT              (25u)
+#define GPIO_PMCSR3_PMCSR326_SHIFT              (26u)
+#define GPIO_PMCSR3_PMCSR327_SHIFT              (27u)
+#define GPIO_PMCSR3_PMCSR328_SHIFT              (28u)
+#define GPIO_PMCSR3_PMCSR329_SHIFT              (29u)
+#define GPIO_PMCSR3_PMCSR330_SHIFT              (30u)
+#define GPIO_PMCSR3_PMCSR331_SHIFT              (31u)
+
+#define GPIO_PFCAE3_PFCAE30_SHIFT               (0u)
+#define GPIO_PFCAE3_PFCAE31_SHIFT               (1u)
+#define GPIO_PFCAE3_PFCAE32_SHIFT               (2u)
+#define GPIO_PFCAE3_PFCAE33_SHIFT               (3u)
+#define GPIO_PFCAE3_PFCAE34_SHIFT               (4u)
+#define GPIO_PFCAE3_PFCAE35_SHIFT               (5u)
+#define GPIO_PFCAE3_PFCAE36_SHIFT               (6u)
+#define GPIO_PFCAE3_PFCAE37_SHIFT               (7u)
+#define GPIO_PFCAE3_PFCAE38_SHIFT               (8u)
+#define GPIO_PFCAE3_PFCAE39_SHIFT               (9u)
+#define GPIO_PFCAE3_PFCAE310_SHIFT              (10u)
+#define GPIO_PFCAE3_PFCAE311_SHIFT              (11u)
+#define GPIO_PFCAE3_PFCAE312_SHIFT              (12u)
+#define GPIO_PFCAE3_PFCAE313_SHIFT              (13u)
+#define GPIO_PFCAE3_PFCAE314_SHIFT              (14u)
+#define GPIO_PFCAE3_PFCAE315_SHIFT              (15u)
+
+#define GPIO_PIBC3_PIBC30_SHIFT                 (0u)
+#define GPIO_PIBC3_PIBC31_SHIFT                 (1u)
+#define GPIO_PIBC3_PIBC32_SHIFT                 (2u)
+#define GPIO_PIBC3_PIBC33_SHIFT                 (3u)
+#define GPIO_PIBC3_PIBC34_SHIFT                 (4u)
+#define GPIO_PIBC3_PIBC35_SHIFT                 (5u)
+#define GPIO_PIBC3_PIBC36_SHIFT                 (6u)
+#define GPIO_PIBC3_PIBC37_SHIFT                 (7u)
+#define GPIO_PIBC3_PIBC38_SHIFT                 (8u)
+#define GPIO_PIBC3_PIBC39_SHIFT                 (9u)
+#define GPIO_PIBC3_PIBC310_SHIFT                (10u)
+#define GPIO_PIBC3_PIBC311_SHIFT                (11u)
+#define GPIO_PIBC3_PIBC312_SHIFT                (12u)
+#define GPIO_PIBC3_PIBC313_SHIFT                (13u)
+#define GPIO_PIBC3_PIBC314_SHIFT                (14u)
+#define GPIO_PIBC3_PIBC315_SHIFT                (15u)
+
+#define GPIO_PBDC3_PBDC30_SHIFT                 (0u)
+#define GPIO_PBDC3_PBDC31_SHIFT                 (1u)
+#define GPIO_PBDC3_PBDC32_SHIFT                 (2u)
+#define GPIO_PBDC3_PBDC33_SHIFT                 (3u)
+#define GPIO_PBDC3_PBDC34_SHIFT                 (4u)
+#define GPIO_PBDC3_PBDC35_SHIFT                 (5u)
+#define GPIO_PBDC3_PBDC36_SHIFT                 (6u)
+#define GPIO_PBDC3_PBDC37_SHIFT                 (7u)
+#define GPIO_PBDC3_PBDC38_SHIFT                 (8u)
+#define GPIO_PBDC3_PBDC39_SHIFT                 (9u)
+#define GPIO_PBDC3_PBDC310_SHIFT                (10u)
+#define GPIO_PBDC3_PBDC311_SHIFT                (11u)
+#define GPIO_PBDC3_PBDC312_SHIFT                (12u)
+#define GPIO_PBDC3_PBDC313_SHIFT                (13u)
+#define GPIO_PBDC3_PBDC314_SHIFT                (14u)
+#define GPIO_PBDC3_PBDC315_SHIFT                (15u)
+
+#define GPIO_PIPC3_PIPC30_SHIFT                 (0u)
+#define GPIO_PIPC3_PIPC31_SHIFT                 (1u)
+#define GPIO_PIPC3_PIPC32_SHIFT                 (2u)
+#define GPIO_PIPC3_PIPC33_SHIFT                 (3u)
+#define GPIO_PIPC3_PIPC34_SHIFT                 (4u)
+#define GPIO_PIPC3_PIPC35_SHIFT                 (5u)
+#define GPIO_PIPC3_PIPC36_SHIFT                 (6u)
+#define GPIO_PIPC3_PIPC37_SHIFT                 (7u)
+#define GPIO_PIPC3_PIPC38_SHIFT                 (8u)
+#define GPIO_PIPC3_PIPC39_SHIFT                 (9u)
+#define GPIO_PIPC3_PIPC310_SHIFT                (10u)
+#define GPIO_PIPC3_PIPC311_SHIFT                (11u)
+#define GPIO_PIPC3_PIPC312_SHIFT                (12u)
+#define GPIO_PIPC3_PIPC313_SHIFT                (13u)
+#define GPIO_PIPC3_PIPC314_SHIFT                (14u)
+#define GPIO_PIPC3_PIPC315_SHIFT                (15u)
+
+/* ---- P4 ---- */
+#define GPIO_P4_P40_SHIFT                       (0u)
+#define GPIO_P4_P41_SHIFT                       (1u)
+#define GPIO_P4_P42_SHIFT                       (2u)
+#define GPIO_P4_P43_SHIFT                       (3u)
+#define GPIO_P4_P44_SHIFT                       (4u)
+#define GPIO_P4_P45_SHIFT                       (5u)
+#define GPIO_P4_P46_SHIFT                       (6u)
+#define GPIO_P4_P47_SHIFT                       (7u)
+#define GPIO_P4_P48_SHIFT                       (8u)
+#define GPIO_P4_P49_SHIFT                       (9u)
+#define GPIO_P4_P410_SHIFT                      (10u)
+#define GPIO_P4_P411_SHIFT                      (11u)
+#define GPIO_P4_P412_SHIFT                      (12u)
+#define GPIO_P4_P413_SHIFT                      (13u)
+#define GPIO_P4_P414_SHIFT                      (14u)
+#define GPIO_P4_P415_SHIFT                      (15u)
+
+#define GPIO_PSR4_PSR40_SHIFT                   (0u)
+#define GPIO_PSR4_PSR41_SHIFT                   (1u)
+#define GPIO_PSR4_PSR42_SHIFT                   (2u)
+#define GPIO_PSR4_PSR43_SHIFT                   (3u)
+#define GPIO_PSR4_PSR44_SHIFT                   (4u)
+#define GPIO_PSR4_PSR45_SHIFT                   (5u)
+#define GPIO_PSR4_PSR46_SHIFT                   (6u)
+#define GPIO_PSR4_PSR47_SHIFT                   (7u)
+#define GPIO_PSR4_PSR48_SHIFT                   (8u)
+#define GPIO_PSR4_PSR49_SHIFT                   (9u)
+#define GPIO_PSR4_PSR410_SHIFT                  (10u)
+#define GPIO_PSR4_PSR411_SHIFT                  (11u)
+#define GPIO_PSR4_PSR412_SHIFT                  (12u)
+#define GPIO_PSR4_PSR413_SHIFT                  (13u)
+#define GPIO_PSR4_PSR414_SHIFT                  (14u)
+#define GPIO_PSR4_PSR415_SHIFT                  (15u)
+#define GPIO_PSR4_PSR416_SHIFT                  (16u)
+#define GPIO_PSR4_PSR417_SHIFT                  (17u)
+#define GPIO_PSR4_PSR418_SHIFT                  (18u)
+#define GPIO_PSR4_PSR419_SHIFT                  (19u)
+#define GPIO_PSR4_PSR420_SHIFT                  (20u)
+#define GPIO_PSR4_PSR421_SHIFT                  (21u)
+#define GPIO_PSR4_PSR422_SHIFT                  (22u)
+#define GPIO_PSR4_PSR423_SHIFT                  (23u)
+#define GPIO_PSR4_PSR424_SHIFT                  (24u)
+#define GPIO_PSR4_PSR425_SHIFT                  (25u)
+#define GPIO_PSR4_PSR426_SHIFT                  (26u)
+#define GPIO_PSR4_PSR427_SHIFT                  (27u)
+#define GPIO_PSR4_PSR428_SHIFT                  (28u)
+#define GPIO_PSR4_PSR429_SHIFT                  (29u)
+#define GPIO_PSR4_PSR430_SHIFT                  (30u)
+#define GPIO_PSR4_PSR431_SHIFT                  (31u)
+
+#define GPIO_PPR4_PPR40_SHIFT                   (0u)
+#define GPIO_PPR4_PPR41_SHIFT                   (1u)
+#define GPIO_PPR4_PPR42_SHIFT                   (2u)
+#define GPIO_PPR4_PPR43_SHIFT                   (3u)
+#define GPIO_PPR4_PPR44_SHIFT                   (4u)
+#define GPIO_PPR4_PPR45_SHIFT                   (5u)
+#define GPIO_PPR4_PPR46_SHIFT                   (6u)
+#define GPIO_PPR4_PPR47_SHIFT                   (7u)
+#define GPIO_PPR4_PPR48_SHIFT                   (8u)
+#define GPIO_PPR4_PPR49_SHIFT                   (9u)
+#define GPIO_PPR4_PPR410_SHIFT                  (10u)
+#define GPIO_PPR4_PPR411_SHIFT                  (11u)
+#define GPIO_PPR4_PPR412_SHIFT                  (12u)
+#define GPIO_PPR4_PPR413_SHIFT                  (13u)
+#define GPIO_PPR4_PPR414_SHIFT                  (14u)
+#define GPIO_PPR4_PPR415_SHIFT                  (15u)
+
+#define GPIO_PM4_PM40_SHIFT                     (0u)
+#define GPIO_PM4_PM41_SHIFT                     (1u)
+#define GPIO_PM4_PM42_SHIFT                     (2u)
+#define GPIO_PM4_PM43_SHIFT                     (3u)
+#define GPIO_PM4_PM44_SHIFT                     (4u)
+#define GPIO_PM4_PM45_SHIFT                     (5u)
+#define GPIO_PM4_PM46_SHIFT                     (6u)
+#define GPIO_PM4_PM47_SHIFT                     (7u)
+#define GPIO_PM4_PM48_SHIFT                     (8u)
+#define GPIO_PM4_PM49_SHIFT                     (9u)
+#define GPIO_PM4_PM410_SHIFT                    (10u)
+#define GPIO_PM4_PM411_SHIFT                    (11u)
+#define GPIO_PM4_PM412_SHIFT                    (12u)
+#define GPIO_PM4_PM413_SHIFT                    (13u)
+#define GPIO_PM4_PM414_SHIFT                    (14u)
+#define GPIO_PM4_PM415_SHIFT                    (15u)
+
+#define GPIO_PMC4_PMC40_SHIFT                   (0u)
+#define GPIO_PMC4_PMC41_SHIFT                   (1u)
+#define GPIO_PMC4_PMC42_SHIFT                   (2u)
+#define GPIO_PMC4_PMC43_SHIFT                   (3u)
+#define GPIO_PMC4_PMC44_SHIFT                   (4u)
+#define GPIO_PMC4_PMC45_SHIFT                   (5u)
+#define GPIO_PMC4_PMC46_SHIFT                   (6u)
+#define GPIO_PMC4_PMC47_SHIFT                   (7u)
+#define GPIO_PMC4_PMC48_SHIFT                   (8u)
+#define GPIO_PMC4_PMC49_SHIFT                   (9u)
+#define GPIO_PMC4_PMC410_SHIFT                  (10u)
+#define GPIO_PMC4_PMC411_SHIFT                  (11u)
+#define GPIO_PMC4_PMC412_SHIFT                  (12u)
+#define GPIO_PMC4_PMC413_SHIFT                  (13u)
+#define GPIO_PMC4_PMC414_SHIFT                  (14u)
+#define GPIO_PMC4_PMC415_SHIFT                  (15u)
+
+#define GPIO_PFC4_PFC40_SHIFT                   (0u)
+#define GPIO_PFC4_PFC41_SHIFT                   (1u)
+#define GPIO_PFC4_PFC42_SHIFT                   (2u)
+#define GPIO_PFC4_PFC43_SHIFT                   (3u)
+#define GPIO_PFC4_PFC44_SHIFT                   (4u)
+#define GPIO_PFC4_PFC45_SHIFT                   (5u)
+#define GPIO_PFC4_PFC46_SHIFT                   (6u)
+#define GPIO_PFC4_PFC47_SHIFT                   (7u)
+#define GPIO_PFC4_PFC48_SHIFT                   (8u)
+#define GPIO_PFC4_PFC49_SHIFT                   (9u)
+#define GPIO_PFC4_PFC410_SHIFT                  (10u)
+#define GPIO_PFC4_PFC411_SHIFT                  (11u)
+#define GPIO_PFC4_PFC412_SHIFT                  (12u)
+#define GPIO_PFC4_PFC413_SHIFT                  (13u)
+#define GPIO_PFC4_PFC414_SHIFT                  (14u)
+#define GPIO_PFC4_PFC415_SHIFT                  (15u)
+
+#define GPIO_PFCE4_PFCE40_SHIFT                 (0u)
+#define GPIO_PFCE4_PFCE41_SHIFT                 (1u)
+#define GPIO_PFCE4_PFCE42_SHIFT                 (2u)
+#define GPIO_PFCE4_PFCE43_SHIFT                 (3u)
+#define GPIO_PFCE4_PFCE44_SHIFT                 (4u)
+#define GPIO_PFCE4_PFCE45_SHIFT                 (5u)
+#define GPIO_PFCE4_PFCE46_SHIFT                 (6u)
+#define GPIO_PFCE4_PFCE47_SHIFT                 (7u)
+#define GPIO_PFCE4_PFCE48_SHIFT                 (8u)
+#define GPIO_PFCE4_PFCE49_SHIFT                 (9u)
+#define GPIO_PFCE4_PFCE410_SHIFT                (10u)
+#define GPIO_PFCE4_PFCE411_SHIFT                (11u)
+#define GPIO_PFCE4_PFCE412_SHIFT                (12u)
+#define GPIO_PFCE4_PFCE413_SHIFT                (13u)
+#define GPIO_PFCE4_PFCE414_SHIFT                (14u)
+#define GPIO_PFCE4_PFCE415_SHIFT                (15u)
+
+#define GPIO_PNOT4_PNOT40_SHIFT                 (0u)
+#define GPIO_PNOT4_PNOT41_SHIFT                 (1u)
+#define GPIO_PNOT4_PNOT42_SHIFT                 (2u)
+#define GPIO_PNOT4_PNOT43_SHIFT                 (3u)
+#define GPIO_PNOT4_PNOT44_SHIFT                 (4u)
+#define GPIO_PNOT4_PNOT45_SHIFT                 (5u)
+#define GPIO_PNOT4_PNOT46_SHIFT                 (6u)
+#define GPIO_PNOT4_PNOT47_SHIFT                 (7u)
+#define GPIO_PNOT4_PNOT48_SHIFT                 (8u)
+#define GPIO_PNOT4_PNOT49_SHIFT                 (9u)
+#define GPIO_PNOT4_PNOT410_SHIFT                (10u)
+#define GPIO_PNOT4_PNOT411_SHIFT                (11u)
+#define GPIO_PNOT4_PNOT412_SHIFT                (12u)
+#define GPIO_PNOT4_PNOT413_SHIFT                (13u)
+#define GPIO_PNOT4_PNOT414_SHIFT                (14u)
+#define GPIO_PNOT4_PNOT415_SHIFT                (15u)
+
+#define GPIO_PMSR4_PMSR40_SHIFT                 (0u)
+#define GPIO_PMSR4_PMSR41_SHIFT                 (1u)
+#define GPIO_PMSR4_PMSR42_SHIFT                 (2u)
+#define GPIO_PMSR4_PMSR43_SHIFT                 (3u)
+#define GPIO_PMSR4_PMSR44_SHIFT                 (4u)
+#define GPIO_PMSR4_PMSR45_SHIFT                 (5u)
+#define GPIO_PMSR4_PMSR46_SHIFT                 (6u)
+#define GPIO_PMSR4_PMSR47_SHIFT                 (7u)
+#define GPIO_PMSR4_PMSR48_SHIFT                 (8u)
+#define GPIO_PMSR4_PMSR49_SHIFT                 (9u)
+#define GPIO_PMSR4_PMSR410_SHIFT                (10u)
+#define GPIO_PMSR4_PMSR411_SHIFT                (11u)
+#define GPIO_PMSR4_PMSR412_SHIFT                (12u)
+#define GPIO_PMSR4_PMSR413_SHIFT                (13u)
+#define GPIO_PMSR4_PMSR414_SHIFT                (14u)
+#define GPIO_PMSR4_PMSR415_SHIFT                (15u)
+#define GPIO_PMSR4_PMSR416_SHIFT                (16u)
+#define GPIO_PMSR4_PMSR417_SHIFT                (17u)
+#define GPIO_PMSR4_PMSR418_SHIFT                (18u)
+#define GPIO_PMSR4_PMSR419_SHIFT                (19u)
+#define GPIO_PMSR4_PMSR420_SHIFT                (20u)
+#define GPIO_PMSR4_PMSR421_SHIFT                (21u)
+#define GPIO_PMSR4_PMSR422_SHIFT                (22u)
+#define GPIO_PMSR4_PMSR423_SHIFT                (23u)
+#define GPIO_PMSR4_PMSR424_SHIFT                (24u)
+#define GPIO_PMSR4_PMSR425_SHIFT                (25u)
+#define GPIO_PMSR4_PMSR426_SHIFT                (26u)
+#define GPIO_PMSR4_PMSR427_SHIFT                (27u)
+#define GPIO_PMSR4_PMSR428_SHIFT                (28u)
+#define GPIO_PMSR4_PMSR429_SHIFT                (29u)
+#define GPIO_PMSR4_PMSR430_SHIFT                (30u)
+#define GPIO_PMSR4_PMSR431_SHIFT                (31u)
+
+#define GPIO_PMCSR4_PMCSR40_SHIFT               (0u)
+#define GPIO_PMCSR4_PMCSR41_SHIFT               (1u)
+#define GPIO_PMCSR4_PMCSR42_SHIFT               (2u)
+#define GPIO_PMCSR4_PMCSR43_SHIFT               (3u)
+#define GPIO_PMCSR4_PMCSR44_SHIFT               (4u)
+#define GPIO_PMCSR4_PMCSR45_SHIFT               (5u)
+#define GPIO_PMCSR4_PMCSR46_SHIFT               (6u)
+#define GPIO_PMCSR4_PMCSR47_SHIFT               (7u)
+#define GPIO_PMCSR4_PMCSR48_SHIFT               (8u)
+#define GPIO_PMCSR4_PMCSR49_SHIFT               (9u)
+#define GPIO_PMCSR4_PMCSR410_SHIFT              (10u)
+#define GPIO_PMCSR4_PMCSR411_SHIFT              (11u)
+#define GPIO_PMCSR4_PMCSR412_SHIFT              (12u)
+#define GPIO_PMCSR4_PMCSR413_SHIFT              (13u)
+#define GPIO_PMCSR4_PMCSR414_SHIFT              (14u)
+#define GPIO_PMCSR4_PMCSR415_SHIFT              (15u)
+#define GPIO_PMCSR4_PMCSR416_SHIFT              (16u)
+#define GPIO_PMCSR4_PMCSR417_SHIFT              (17u)
+#define GPIO_PMCSR4_PMCSR418_SHIFT              (18u)
+#define GPIO_PMCSR4_PMCSR419_SHIFT              (19u)
+#define GPIO_PMCSR4_PMCSR420_SHIFT              (20u)
+#define GPIO_PMCSR4_PMCSR421_SHIFT              (21u)
+#define GPIO_PMCSR4_PMCSR422_SHIFT              (22u)
+#define GPIO_PMCSR4_PMCSR423_SHIFT              (23u)
+#define GPIO_PMCSR4_PMCSR424_SHIFT              (24u)
+#define GPIO_PMCSR4_PMCSR425_SHIFT              (25u)
+#define GPIO_PMCSR4_PMCSR426_SHIFT              (26u)
+#define GPIO_PMCSR4_PMCSR427_SHIFT              (27u)
+#define GPIO_PMCSR4_PMCSR428_SHIFT              (28u)
+#define GPIO_PMCSR4_PMCSR429_SHIFT              (29u)
+#define GPIO_PMCSR4_PMCSR430_SHIFT              (30u)
+#define GPIO_PMCSR4_PMCSR431_SHIFT              (31u)
+
+#define GPIO_PFCAE4_PFCAE40_SHIFT               (0u)
+#define GPIO_PFCAE4_PFCAE41_SHIFT               (1u)
+#define GPIO_PFCAE4_PFCAE42_SHIFT               (2u)
+#define GPIO_PFCAE4_PFCAE43_SHIFT               (3u)
+#define GPIO_PFCAE4_PFCAE44_SHIFT               (4u)
+#define GPIO_PFCAE4_PFCAE45_SHIFT               (5u)
+#define GPIO_PFCAE4_PFCAE46_SHIFT               (6u)
+#define GPIO_PFCAE4_PFCAE47_SHIFT               (7u)
+#define GPIO_PFCAE4_PFCAE48_SHIFT               (8u)
+#define GPIO_PFCAE4_PFCAE49_SHIFT               (9u)
+#define GPIO_PFCAE4_PFCAE410_SHIFT              (10u)
+#define GPIO_PFCAE4_PFCAE411_SHIFT              (11u)
+#define GPIO_PFCAE4_PFCAE412_SHIFT              (12u)
+#define GPIO_PFCAE4_PFCAE413_SHIFT              (13u)
+#define GPIO_PFCAE4_PFCAE414_SHIFT              (14u)
+#define GPIO_PFCAE4_PFCAE415_SHIFT              (15u)
+
+#define GPIO_PIBC4_PIBC40_SHIFT                 (0u)
+#define GPIO_PIBC4_PIBC41_SHIFT                 (1u)
+#define GPIO_PIBC4_PIBC42_SHIFT                 (2u)
+#define GPIO_PIBC4_PIBC43_SHIFT                 (3u)
+#define GPIO_PIBC4_PIBC44_SHIFT                 (4u)
+#define GPIO_PIBC4_PIBC45_SHIFT                 (5u)
+#define GPIO_PIBC4_PIBC46_SHIFT                 (6u)
+#define GPIO_PIBC4_PIBC47_SHIFT                 (7u)
+#define GPIO_PIBC4_PIBC48_SHIFT                 (8u)
+#define GPIO_PIBC4_PIBC49_SHIFT                 (9u)
+#define GPIO_PIBC4_PIBC410_SHIFT                (10u)
+#define GPIO_PIBC4_PIBC411_SHIFT                (11u)
+#define GPIO_PIBC4_PIBC412_SHIFT                (12u)
+#define GPIO_PIBC4_PIBC413_SHIFT                (13u)
+#define GPIO_PIBC4_PIBC414_SHIFT                (14u)
+#define GPIO_PIBC4_PIBC415_SHIFT                (15u)
+
+#define GPIO_PBDC4_PBDC40_SHIFT                 (0u)
+#define GPIO_PBDC4_PBDC41_SHIFT                 (1u)
+#define GPIO_PBDC4_PBDC42_SHIFT                 (2u)
+#define GPIO_PBDC4_PBDC43_SHIFT                 (3u)
+#define GPIO_PBDC4_PBDC44_SHIFT                 (4u)
+#define GPIO_PBDC4_PBDC45_SHIFT                 (5u)
+#define GPIO_PBDC4_PBDC46_SHIFT                 (6u)
+#define GPIO_PBDC4_PBDC47_SHIFT                 (7u)
+#define GPIO_PBDC4_PBDC48_SHIFT                 (8u)
+#define GPIO_PBDC4_PBDC49_SHIFT                 (9u)
+#define GPIO_PBDC4_PBDC410_SHIFT                (10u)
+#define GPIO_PBDC4_PBDC411_SHIFT                (11u)
+#define GPIO_PBDC4_PBDC412_SHIFT                (12u)
+#define GPIO_PBDC4_PBDC413_SHIFT                (13u)
+#define GPIO_PBDC4_PBDC414_SHIFT                (14u)
+#define GPIO_PBDC4_PBDC415_SHIFT                (15u)
+
+#define GPIO_PIPC4_PIPC40_SHIFT                 (0u)
+#define GPIO_PIPC4_PIPC41_SHIFT                 (1u)
+#define GPIO_PIPC4_PIPC42_SHIFT                 (2u)
+#define GPIO_PIPC4_PIPC43_SHIFT                 (3u)
+#define GPIO_PIPC4_PIPC44_SHIFT                 (4u)
+#define GPIO_PIPC4_PIPC45_SHIFT                 (5u)
+#define GPIO_PIPC4_PIPC46_SHIFT                 (6u)
+#define GPIO_PIPC4_PIPC47_SHIFT                 (7u)
+#define GPIO_PIPC4_PIPC48_SHIFT                 (8u)
+#define GPIO_PIPC4_PIPC49_SHIFT                 (9u)
+#define GPIO_PIPC4_PIPC410_SHIFT                (10u)
+#define GPIO_PIPC4_PIPC411_SHIFT                (11u)
+#define GPIO_PIPC4_PIPC412_SHIFT                (12u)
+#define GPIO_PIPC4_PIPC413_SHIFT                (13u)
+#define GPIO_PIPC4_PIPC414_SHIFT                (14u)
+#define GPIO_PIPC4_PIPC415_SHIFT                (15u)
+
+/* ---- P5 ---- */
+#define GPIO_P5_P50_SHIFT                       (0u)
+#define GPIO_P5_P51_SHIFT                       (1u)
+#define GPIO_P5_P52_SHIFT                       (2u)
+#define GPIO_P5_P53_SHIFT                       (3u)
+#define GPIO_P5_P54_SHIFT                       (4u)
+#define GPIO_P5_P55_SHIFT                       (5u)
+#define GPIO_P5_P56_SHIFT                       (6u)
+#define GPIO_P5_P57_SHIFT                       (7u)
+#define GPIO_P5_P58_SHIFT                       (8u)
+#define GPIO_P5_P59_SHIFT                       (9u)
+#define GPIO_P5_P510_SHIFT                      (10u)
+
+#define GPIO_PSR5_PSR50_SHIFT                   (0u)
+#define GPIO_PSR5_PSR51_SHIFT                   (1u)
+#define GPIO_PSR5_PSR52_SHIFT                   (2u)
+#define GPIO_PSR5_PSR53_SHIFT                   (3u)
+#define GPIO_PSR5_PSR54_SHIFT                   (4u)
+#define GPIO_PSR5_PSR55_SHIFT                   (5u)
+#define GPIO_PSR5_PSR56_SHIFT                   (6u)
+#define GPIO_PSR5_PSR57_SHIFT                   (7u)
+#define GPIO_PSR5_PSR58_SHIFT                   (8u)
+#define GPIO_PSR5_PSR59_SHIFT                   (9u)
+#define GPIO_PSR5_PSR510_SHIFT                  (10u)
+#define GPIO_PSR5_PSR516_SHIFT                  (16u)
+#define GPIO_PSR5_PSR517_SHIFT                  (17u)
+#define GPIO_PSR5_PSR518_SHIFT                  (18u)
+#define GPIO_PSR5_PSR519_SHIFT                  (19u)
+#define GPIO_PSR5_PSR520_SHIFT                  (20u)
+#define GPIO_PSR5_PSR521_SHIFT                  (21u)
+#define GPIO_PSR5_PSR522_SHIFT                  (22u)
+#define GPIO_PSR5_PSR523_SHIFT                  (23u)
+#define GPIO_PSR5_PSR524_SHIFT                  (24u)
+#define GPIO_PSR5_PSR525_SHIFT                  (25u)
+#define GPIO_PSR5_PSR526_SHIFT                  (26u)
+
+#define GPIO_PPR5_PPR50_SHIFT                   (0u)
+#define GPIO_PPR5_PPR51_SHIFT                   (1u)
+#define GPIO_PPR5_PPR52_SHIFT                   (2u)
+#define GPIO_PPR5_PPR53_SHIFT                   (3u)
+#define GPIO_PPR5_PPR54_SHIFT                   (4u)
+#define GPIO_PPR5_PPR55_SHIFT                   (5u)
+#define GPIO_PPR5_PPR56_SHIFT                   (6u)
+#define GPIO_PPR5_PPR57_SHIFT                   (7u)
+#define GPIO_PPR5_PPR58_SHIFT                   (8u)
+#define GPIO_PPR5_PPR59_SHIFT                   (9u)
+#define GPIO_PPR5_PPR510_SHIFT                  (10u)
+
+#define GPIO_PM5_PM50_SHIFT                     (0u)
+#define GPIO_PM5_PM51_SHIFT                     (1u)
+#define GPIO_PM5_PM52_SHIFT                     (2u)
+#define GPIO_PM5_PM53_SHIFT                     (3u)
+#define GPIO_PM5_PM54_SHIFT                     (4u)
+#define GPIO_PM5_PM55_SHIFT                     (5u)
+#define GPIO_PM5_PM56_SHIFT                     (6u)
+#define GPIO_PM5_PM57_SHIFT                     (7u)
+#define GPIO_PM5_PM58_SHIFT                     (8u)
+#define GPIO_PM5_PM59_SHIFT                     (9u)
+#define GPIO_PM5_PM510_SHIFT                    (10u)
+
+#define GPIO_PMC5_PMC50_SHIFT                   (0u)
+#define GPIO_PMC5_PMC51_SHIFT                   (1u)
+#define GPIO_PMC5_PMC52_SHIFT                   (2u)
+#define GPIO_PMC5_PMC53_SHIFT                   (3u)
+#define GPIO_PMC5_PMC54_SHIFT                   (4u)
+#define GPIO_PMC5_PMC55_SHIFT                   (5u)
+#define GPIO_PMC5_PMC56_SHIFT                   (6u)
+#define GPIO_PMC5_PMC57_SHIFT                   (7u)
+#define GPIO_PMC5_PMC58_SHIFT                   (8u)
+#define GPIO_PMC5_PMC59_SHIFT                   (9u)
+#define GPIO_PMC5_PMC510_SHIFT                  (10u)
+
+#define GPIO_PFC5_PFC50_SHIFT                   (0u)
+#define GPIO_PFC5_PFC51_SHIFT                   (1u)
+#define GPIO_PFC5_PFC52_SHIFT                   (2u)
+#define GPIO_PFC5_PFC53_SHIFT                   (3u)
+#define GPIO_PFC5_PFC54_SHIFT                   (4u)
+#define GPIO_PFC5_PFC55_SHIFT                   (5u)
+#define GPIO_PFC5_PFC56_SHIFT                   (6u)
+#define GPIO_PFC5_PFC57_SHIFT                   (7u)
+#define GPIO_PFC5_PFC58_SHIFT                   (8u)
+#define GPIO_PFC5_PFC59_SHIFT                   (9u)
+#define GPIO_PFC5_PFC510_SHIFT                  (10u)
+
+#define GPIO_PFCE5_PFCE50_SHIFT                 (0u)
+#define GPIO_PFCE5_PFCE51_SHIFT                 (1u)
+#define GPIO_PFCE5_PFCE52_SHIFT                 (2u)
+#define GPIO_PFCE5_PFCE53_SHIFT                 (3u)
+#define GPIO_PFCE5_PFCE54_SHIFT                 (4u)
+#define GPIO_PFCE5_PFCE55_SHIFT                 (5u)
+#define GPIO_PFCE5_PFCE56_SHIFT                 (6u)
+#define GPIO_PFCE5_PFCE57_SHIFT                 (7u)
+#define GPIO_PFCE5_PFCE58_SHIFT                 (8u)
+#define GPIO_PFCE5_PFCE59_SHIFT                 (9u)
+#define GPIO_PFCE5_PFCE510_SHIFT                (10u)
+
+#define GPIO_PNOT5_PNOT50_SHIFT                 (0u)
+#define GPIO_PNOT5_PNOT51_SHIFT                 (1u)
+#define GPIO_PNOT5_PNOT52_SHIFT                 (2u)
+#define GPIO_PNOT5_PNOT53_SHIFT                 (3u)
+#define GPIO_PNOT5_PNOT54_SHIFT                 (4u)
+#define GPIO_PNOT5_PNOT55_SHIFT                 (5u)
+#define GPIO_PNOT5_PNOT56_SHIFT                 (6u)
+#define GPIO_PNOT5_PNOT57_SHIFT                 (7u)
+#define GPIO_PNOT5_PNOT58_SHIFT                 (8u)
+#define GPIO_PNOT5_PNOT59_SHIFT                 (9u)
+#define GPIO_PNOT5_PNOT510_SHIFT                (10u)
+
+#define GPIO_PMSR5_PMSR50_SHIFT                 (0u)
+#define GPIO_PMSR5_PMSR51_SHIFT                 (1u)
+#define GPIO_PMSR5_PMSR52_SHIFT                 (2u)
+#define GPIO_PMSR5_PMSR53_SHIFT                 (3u)
+#define GPIO_PMSR5_PMSR54_SHIFT                 (4u)
+#define GPIO_PMSR5_PMSR55_SHIFT                 (5u)
+#define GPIO_PMSR5_PMSR56_SHIFT                 (6u)
+#define GPIO_PMSR5_PMSR57_SHIFT                 (7u)
+#define GPIO_PMSR5_PMSR58_SHIFT                 (8u)
+#define GPIO_PMSR5_PMSR59_SHIFT                 (9u)
+#define GPIO_PMSR5_PMSR510_SHIFT                (10u)
+#define GPIO_PMSR5_PMSR516_SHIFT                (16u)
+#define GPIO_PMSR5_PMSR517_SHIFT                (17u)
+#define GPIO_PMSR5_PMSR518_SHIFT                (18u)
+#define GPIO_PMSR5_PMSR519_SHIFT                (19u)
+#define GPIO_PMSR5_PMSR520_SHIFT                (20u)
+#define GPIO_PMSR5_PMSR521_SHIFT                (21u)
+#define GPIO_PMSR5_PMSR522_SHIFT                (22u)
+#define GPIO_PMSR5_PMSR523_SHIFT                (23u)
+#define GPIO_PMSR5_PMSR524_SHIFT                (24u)
+#define GPIO_PMSR5_PMSR525_SHIFT                (25u)
+#define GPIO_PMSR5_PMSR526_SHIFT                (26u)
+
+#define GPIO_PMCSR5_PMCSR50_SHIFT               (0u)
+#define GPIO_PMCSR5_PMCSR51_SHIFT               (1u)
+#define GPIO_PMCSR5_PMCSR52_SHIFT               (2u)
+#define GPIO_PMCSR5_PMCSR53_SHIFT               (3u)
+#define GPIO_PMCSR5_PMCSR54_SHIFT               (4u)
+#define GPIO_PMCSR5_PMCSR55_SHIFT               (5u)
+#define GPIO_PMCSR5_PMCSR56_SHIFT               (6u)
+#define GPIO_PMCSR5_PMCSR57_SHIFT               (7u)
+#define GPIO_PMCSR5_PMCSR58_SHIFT               (8u)
+#define GPIO_PMCSR5_PMCSR59_SHIFT               (9u)
+#define GPIO_PMCSR5_PMCSR510_SHIFT              (10u)
+#define GPIO_PMCSR5_PMCSR516_SHIFT              (16u)
+#define GPIO_PMCSR5_PMCSR517_SHIFT              (17u)
+#define GPIO_PMCSR5_PMCSR518_SHIFT              (18u)
+#define GPIO_PMCSR5_PMCSR519_SHIFT              (19u)
+#define GPIO_PMCSR5_PMCSR520_SHIFT              (20u)
+#define GPIO_PMCSR5_PMCSR521_SHIFT              (21u)
+#define GPIO_PMCSR5_PMCSR522_SHIFT              (22u)
+#define GPIO_PMCSR5_PMCSR523_SHIFT              (23u)
+#define GPIO_PMCSR5_PMCSR524_SHIFT              (24u)
+#define GPIO_PMCSR5_PMCSR525_SHIFT              (25u)
+#define GPIO_PMCSR5_PMCSR526_SHIFT              (26u)
+
+#define GPIO_PFCAE5_PFCAE50_SHIFT               (0u)
+#define GPIO_PFCAE5_PFCAE51_SHIFT               (1u)
+#define GPIO_PFCAE5_PFCAE52_SHIFT               (2u)
+#define GPIO_PFCAE5_PFCAE53_SHIFT               (3u)
+#define GPIO_PFCAE5_PFCAE54_SHIFT               (4u)
+#define GPIO_PFCAE5_PFCAE55_SHIFT               (5u)
+#define GPIO_PFCAE5_PFCAE56_SHIFT               (6u)
+#define GPIO_PFCAE5_PFCAE57_SHIFT               (7u)
+#define GPIO_PFCAE5_PFCAE58_SHIFT               (8u)
+#define GPIO_PFCAE5_PFCAE59_SHIFT               (9u)
+#define GPIO_PFCAE5_PFCAE510_SHIFT              (10u)
+
+#define GPIO_PIBC5_PIBC50_SHIFT                 (0u)
+#define GPIO_PIBC5_PIBC51_SHIFT                 (1u)
+#define GPIO_PIBC5_PIBC52_SHIFT                 (2u)
+#define GPIO_PIBC5_PIBC53_SHIFT                 (3u)
+#define GPIO_PIBC5_PIBC54_SHIFT                 (4u)
+#define GPIO_PIBC5_PIBC55_SHIFT                 (5u)
+#define GPIO_PIBC5_PIBC56_SHIFT                 (6u)
+#define GPIO_PIBC5_PIBC57_SHIFT                 (7u)
+#define GPIO_PIBC5_PIBC58_SHIFT                 (8u)
+#define GPIO_PIBC5_PIBC59_SHIFT                 (9u)
+#define GPIO_PIBC5_PIBC510_SHIFT                (10u)
+
+#define GPIO_PBDC5_PBDC50_SHIFT                 (0u)
+#define GPIO_PBDC5_PBDC51_SHIFT                 (1u)
+#define GPIO_PBDC5_PBDC52_SHIFT                 (2u)
+#define GPIO_PBDC5_PBDC53_SHIFT                 (3u)
+#define GPIO_PBDC5_PBDC54_SHIFT                 (4u)
+#define GPIO_PBDC5_PBDC55_SHIFT                 (5u)
+#define GPIO_PBDC5_PBDC56_SHIFT                 (6u)
+#define GPIO_PBDC5_PBDC57_SHIFT                 (7u)
+#define GPIO_PBDC5_PBDC58_SHIFT                 (8u)
+#define GPIO_PBDC5_PBDC59_SHIFT                 (9u)
+#define GPIO_PBDC5_PBDC510_SHIFT                (10u)
+
+#define GPIO_PIPC5_PIPC50_SHIFT                 (0u)
+#define GPIO_PIPC5_PIPC51_SHIFT                 (1u)
+#define GPIO_PIPC5_PIPC52_SHIFT                 (2u)
+#define GPIO_PIPC5_PIPC53_SHIFT                 (3u)
+#define GPIO_PIPC5_PIPC54_SHIFT                 (4u)
+#define GPIO_PIPC5_PIPC55_SHIFT                 (5u)
+#define GPIO_PIPC5_PIPC56_SHIFT                 (6u)
+#define GPIO_PIPC5_PIPC57_SHIFT                 (7u)
+#define GPIO_PIPC5_PIPC58_SHIFT                 (8u)
+#define GPIO_PIPC5_PIPC59_SHIFT                 (9u)
+#define GPIO_PIPC5_PIPC510_SHIFT                (10u)
+
+/* ---- P6 ---- */
+#define GPIO_P6_P60_SHIFT                       (0u)
+#define GPIO_P6_P61_SHIFT                       (1u)
+#define GPIO_P6_P62_SHIFT                       (2u)
+#define GPIO_P6_P63_SHIFT                       (3u)
+#define GPIO_P6_P64_SHIFT                       (4u)
+#define GPIO_P6_P65_SHIFT                       (5u)
+#define GPIO_P6_P66_SHIFT                       (6u)
+#define GPIO_P6_P67_SHIFT                       (7u)
+#define GPIO_P6_P68_SHIFT                       (8u)
+#define GPIO_P6_P69_SHIFT                       (9u)
+#define GPIO_P6_P610_SHIFT                      (10u)
+#define GPIO_P6_P611_SHIFT                      (11u)
+#define GPIO_P6_P612_SHIFT                      (12u)
+#define GPIO_P6_P613_SHIFT                      (13u)
+#define GPIO_P6_P614_SHIFT                      (14u)
+#define GPIO_P6_P615_SHIFT                      (15u)
+
+#define GPIO_PSR6_PSR60_SHIFT                   (0u)
+#define GPIO_PSR6_PSR61_SHIFT                   (1u)
+#define GPIO_PSR6_PSR62_SHIFT                   (2u)
+#define GPIO_PSR6_PSR63_SHIFT                   (3u)
+#define GPIO_PSR6_PSR64_SHIFT                   (4u)
+#define GPIO_PSR6_PSR65_SHIFT                   (5u)
+#define GPIO_PSR6_PSR66_SHIFT                   (6u)
+#define GPIO_PSR6_PSR67_SHIFT                   (7u)
+#define GPIO_PSR6_PSR68_SHIFT                   (8u)
+#define GPIO_PSR6_PSR69_SHIFT                   (9u)
+#define GPIO_PSR6_PSR610_SHIFT                  (10u)
+#define GPIO_PSR6_PSR611_SHIFT                  (11u)
+#define GPIO_PSR6_PSR612_SHIFT                  (12u)
+#define GPIO_PSR6_PSR613_SHIFT                  (13u)
+#define GPIO_PSR6_PSR614_SHIFT                  (14u)
+#define GPIO_PSR6_PSR615_SHIFT                  (15u)
+#define GPIO_PSR6_PSR616_SHIFT                  (16u)
+#define GPIO_PSR6_PSR617_SHIFT                  (17u)
+#define GPIO_PSR6_PSR618_SHIFT                  (18u)
+#define GPIO_PSR6_PSR619_SHIFT                  (19u)
+#define GPIO_PSR6_PSR620_SHIFT                  (20u)
+#define GPIO_PSR6_PSR621_SHIFT                  (21u)
+#define GPIO_PSR6_PSR622_SHIFT                  (22u)
+#define GPIO_PSR6_PSR623_SHIFT                  (23u)
+#define GPIO_PSR6_PSR624_SHIFT                  (24u)
+#define GPIO_PSR6_PSR625_SHIFT                  (25u)
+#define GPIO_PSR6_PSR626_SHIFT                  (26u)
+#define GPIO_PSR6_PSR627_SHIFT                  (27u)
+#define GPIO_PSR6_PSR628_SHIFT                  (28u)
+#define GPIO_PSR6_PSR629_SHIFT                  (29u)
+#define GPIO_PSR6_PSR630_SHIFT                  (30u)
+#define GPIO_PSR6_PSR631_SHIFT                  (31u)
+
+#define GPIO_PPR6_PPR60_SHIFT                   (0u)
+#define GPIO_PPR6_PPR61_SHIFT                   (1u)
+#define GPIO_PPR6_PPR62_SHIFT                   (2u)
+#define GPIO_PPR6_PPR63_SHIFT                   (3u)
+#define GPIO_PPR6_PPR64_SHIFT                   (4u)
+#define GPIO_PPR6_PPR65_SHIFT                   (5u)
+#define GPIO_PPR6_PPR66_SHIFT                   (6u)
+#define GPIO_PPR6_PPR67_SHIFT                   (7u)
+#define GPIO_PPR6_PPR68_SHIFT                   (8u)
+#define GPIO_PPR6_PPR69_SHIFT                   (9u)
+#define GPIO_PPR6_PPR610_SHIFT                  (10u)
+#define GPIO_PPR6_PPR611_SHIFT                  (11u)
+#define GPIO_PPR6_PPR612_SHIFT                  (12u)
+#define GPIO_PPR6_PPR613_SHIFT                  (13u)
+#define GPIO_PPR6_PPR614_SHIFT                  (14u)
+#define GPIO_PPR6_PPR615_SHIFT                  (15u)
+
+#define GPIO_PM6_PM60_SHIFT                     (0u)
+#define GPIO_PM6_PM61_SHIFT                     (1u)
+#define GPIO_PM6_PM62_SHIFT                     (2u)
+#define GPIO_PM6_PM63_SHIFT                     (3u)
+#define GPIO_PM6_PM64_SHIFT                     (4u)
+#define GPIO_PM6_PM65_SHIFT                     (5u)
+#define GPIO_PM6_PM66_SHIFT                     (6u)
+#define GPIO_PM6_PM67_SHIFT                     (7u)
+#define GPIO_PM6_PM68_SHIFT                     (8u)
+#define GPIO_PM6_PM69_SHIFT                     (9u)
+#define GPIO_PM6_PM610_SHIFT                    (10u)
+#define GPIO_PM6_PM611_SHIFT                    (11u)
+#define GPIO_PM6_PM612_SHIFT                    (12u)
+#define GPIO_PM6_PM613_SHIFT                    (13u)
+#define GPIO_PM6_PM614_SHIFT                    (14u)
+#define GPIO_PM6_PM615_SHIFT                    (15u)
+
+#define GPIO_PMC6_PMC60_SHIFT                   (0u)
+#define GPIO_PMC6_PMC61_SHIFT                   (1u)
+#define GPIO_PMC6_PMC62_SHIFT                   (2u)
+#define GPIO_PMC6_PMC63_SHIFT                   (3u)
+#define GPIO_PMC6_PMC64_SHIFT                   (4u)
+#define GPIO_PMC6_PMC65_SHIFT                   (5u)
+#define GPIO_PMC6_PMC66_SHIFT                   (6u)
+#define GPIO_PMC6_PMC67_SHIFT                   (7u)
+#define GPIO_PMC6_PMC68_SHIFT                   (8u)
+#define GPIO_PMC6_PMC69_SHIFT                   (9u)
+#define GPIO_PMC6_PMC610_SHIFT                  (10u)
+#define GPIO_PMC6_PMC611_SHIFT                  (11u)
+#define GPIO_PMC6_PMC612_SHIFT                  (12u)
+#define GPIO_PMC6_PMC613_SHIFT                  (13u)
+#define GPIO_PMC6_PMC614_SHIFT                  (14u)
+#define GPIO_PMC6_PMC615_SHIFT                  (15u)
+
+#define GPIO_PFC6_PFC60_SHIFT                   (0u)
+#define GPIO_PFC6_PFC61_SHIFT                   (1u)
+#define GPIO_PFC6_PFC62_SHIFT                   (2u)
+#define GPIO_PFC6_PFC63_SHIFT                   (3u)
+#define GPIO_PFC6_PFC64_SHIFT                   (4u)
+#define GPIO_PFC6_PFC65_SHIFT                   (5u)
+#define GPIO_PFC6_PFC66_SHIFT                   (6u)
+#define GPIO_PFC6_PFC67_SHIFT                   (7u)
+#define GPIO_PFC6_PFC68_SHIFT                   (8u)
+#define GPIO_PFC6_PFC69_SHIFT                   (9u)
+#define GPIO_PFC6_PFC610_SHIFT                  (10u)
+#define GPIO_PFC6_PFC611_SHIFT                  (11u)
+#define GPIO_PFC6_PFC612_SHIFT                  (12u)
+#define GPIO_PFC6_PFC613_SHIFT                  (13u)
+#define GPIO_PFC6_PFC614_SHIFT                  (14u)
+#define GPIO_PFC6_PFC615_SHIFT                  (15u)
+
+#define GPIO_PFCE6_PFCE60_SHIFT                 (0u)
+#define GPIO_PFCE6_PFCE61_SHIFT                 (1u)
+#define GPIO_PFCE6_PFCE62_SHIFT                 (2u)
+#define GPIO_PFCE6_PFCE63_SHIFT                 (3u)
+#define GPIO_PFCE6_PFCE64_SHIFT                 (4u)
+#define GPIO_PFCE6_PFCE65_SHIFT                 (5u)
+#define GPIO_PFCE6_PFCE66_SHIFT                 (6u)
+#define GPIO_PFCE6_PFCE67_SHIFT                 (7u)
+#define GPIO_PFCE6_PFCE68_SHIFT                 (8u)
+#define GPIO_PFCE6_PFCE69_SHIFT                 (9u)
+#define GPIO_PFCE6_PFCE610_SHIFT                (10u)
+#define GPIO_PFCE6_PFCE611_SHIFT                (11u)
+#define GPIO_PFCE6_PFCE612_SHIFT                (12u)
+#define GPIO_PFCE6_PFCE613_SHIFT                (13u)
+#define GPIO_PFCE6_PFCE614_SHIFT                (14u)
+#define GPIO_PFCE6_PFCE615_SHIFT                (15u)
+
+#define GPIO_PNOT6_PNOT60_SHIFT                 (0u)
+#define GPIO_PNOT6_PNOT61_SHIFT                 (1u)
+#define GPIO_PNOT6_PNOT62_SHIFT                 (2u)
+#define GPIO_PNOT6_PNOT63_SHIFT                 (3u)
+#define GPIO_PNOT6_PNOT64_SHIFT                 (4u)
+#define GPIO_PNOT6_PNOT65_SHIFT                 (5u)
+#define GPIO_PNOT6_PNOT66_SHIFT                 (6u)
+#define GPIO_PNOT6_PNOT67_SHIFT                 (7u)
+#define GPIO_PNOT6_PNOT68_SHIFT                 (8u)
+#define GPIO_PNOT6_PNOT69_SHIFT                 (9u)
+#define GPIO_PNOT6_PNOT610_SHIFT                (10u)
+#define GPIO_PNOT6_PNOT611_SHIFT                (11u)
+#define GPIO_PNOT6_PNOT612_SHIFT                (12u)
+#define GPIO_PNOT6_PNOT613_SHIFT                (13u)
+#define GPIO_PNOT6_PNOT614_SHIFT                (14u)
+#define GPIO_PNOT6_PNOT615_SHIFT                (15u)
+
+#define GPIO_PMSR6_PMSR60_SHIFT                 (0u)
+#define GPIO_PMSR6_PMSR61_SHIFT                 (1u)
+#define GPIO_PMSR6_PMSR62_SHIFT                 (2u)
+#define GPIO_PMSR6_PMSR63_SHIFT                 (3u)
+#define GPIO_PMSR6_PMSR64_SHIFT                 (4u)
+#define GPIO_PMSR6_PMSR65_SHIFT                 (5u)
+#define GPIO_PMSR6_PMSR66_SHIFT                 (6u)
+#define GPIO_PMSR6_PMSR67_SHIFT                 (7u)
+#define GPIO_PMSR6_PMSR68_SHIFT                 (8u)
+#define GPIO_PMSR6_PMSR69_SHIFT                 (9u)
+#define GPIO_PMSR6_PMSR610_SHIFT                (10u)
+#define GPIO_PMSR6_PMSR611_SHIFT                (11u)
+#define GPIO_PMSR6_PMSR612_SHIFT                (12u)
+#define GPIO_PMSR6_PMSR613_SHIFT                (13u)
+#define GPIO_PMSR6_PMSR614_SHIFT                (14u)
+#define GPIO_PMSR6_PMSR615_SHIFT                (15u)
+#define GPIO_PMSR6_PMSR616_SHIFT                (16u)
+#define GPIO_PMSR6_PMSR617_SHIFT                (17u)
+#define GPIO_PMSR6_PMSR618_SHIFT                (18u)
+#define GPIO_PMSR6_PMSR619_SHIFT                (19u)
+#define GPIO_PMSR6_PMSR620_SHIFT                (20u)
+#define GPIO_PMSR6_PMSR621_SHIFT                (21u)
+#define GPIO_PMSR6_PMSR622_SHIFT                (22u)
+#define GPIO_PMSR6_PMSR623_SHIFT                (23u)
+#define GPIO_PMSR6_PMSR624_SHIFT                (24u)
+#define GPIO_PMSR6_PMSR625_SHIFT                (25u)
+#define GPIO_PMSR6_PMSR626_SHIFT                (26u)
+#define GPIO_PMSR6_PMSR627_SHIFT                (27u)
+#define GPIO_PMSR6_PMSR628_SHIFT                (28u)
+#define GPIO_PMSR6_PMSR629_SHIFT                (29u)
+#define GPIO_PMSR6_PMSR630_SHIFT                (30u)
+#define GPIO_PMSR6_PMSR631_SHIFT                (31u)
+
+#define GPIO_PMCSR6_PMCSR60_SHIFT               (0u)
+#define GPIO_PMCSR6_PMCSR61_SHIFT               (1u)
+#define GPIO_PMCSR6_PMCSR62_SHIFT               (2u)
+#define GPIO_PMCSR6_PMCSR63_SHIFT               (3u)
+#define GPIO_PMCSR6_PMCSR64_SHIFT               (4u)
+#define GPIO_PMCSR6_PMCSR65_SHIFT               (5u)
+#define GPIO_PMCSR6_PMCSR66_SHIFT               (6u)
+#define GPIO_PMCSR6_PMCSR67_SHIFT               (7u)
+#define GPIO_PMCSR6_PMCSR68_SHIFT               (8u)
+#define GPIO_PMCSR6_PMCSR69_SHIFT               (9u)
+#define GPIO_PMCSR6_PMCSR610_SHIFT              (10u)
+#define GPIO_PMCSR6_PMCSR611_SHIFT              (11u)
+#define GPIO_PMCSR6_PMCSR612_SHIFT              (12u)
+#define GPIO_PMCSR6_PMCSR613_SHIFT              (13u)
+#define GPIO_PMCSR6_PMCSR614_SHIFT              (14u)
+#define GPIO_PMCSR6_PMCSR615_SHIFT              (15u)
+#define GPIO_PMCSR6_PMCSR616_SHIFT              (16u)
+#define GPIO_PMCSR6_PMCSR617_SHIFT              (17u)
+#define GPIO_PMCSR6_PMCSR618_SHIFT              (18u)
+#define GPIO_PMCSR6_PMCSR619_SHIFT              (19u)
+#define GPIO_PMCSR6_PMCSR620_SHIFT              (20u)
+#define GPIO_PMCSR6_PMCSR621_SHIFT              (21u)
+#define GPIO_PMCSR6_PMCSR622_SHIFT              (22u)
+#define GPIO_PMCSR6_PMCSR623_SHIFT              (23u)
+#define GPIO_PMCSR6_PMCSR624_SHIFT              (24u)
+#define GPIO_PMCSR6_PMCSR625_SHIFT              (25u)
+#define GPIO_PMCSR6_PMCSR626_SHIFT              (26u)
+#define GPIO_PMCSR6_PMCSR627_SHIFT              (27u)
+#define GPIO_PMCSR6_PMCSR628_SHIFT              (28u)
+#define GPIO_PMCSR6_PMCSR629_SHIFT              (29u)
+#define GPIO_PMCSR6_PMCSR630_SHIFT              (30u)
+#define GPIO_PMCSR6_PMCSR631_SHIFT              (31u)
+
+#define GPIO_PFCAE6_PFCAE60_SHIFT               (0u)
+#define GPIO_PFCAE6_PFCAE61_SHIFT               (1u)
+#define GPIO_PFCAE6_PFCAE62_SHIFT               (2u)
+#define GPIO_PFCAE6_PFCAE63_SHIFT               (3u)
+#define GPIO_PFCAE6_PFCAE64_SHIFT               (4u)
+#define GPIO_PFCAE6_PFCAE65_SHIFT               (5u)
+#define GPIO_PFCAE6_PFCAE66_SHIFT               (6u)
+#define GPIO_PFCAE6_PFCAE67_SHIFT               (7u)
+#define GPIO_PFCAE6_PFCAE68_SHIFT               (8u)
+#define GPIO_PFCAE6_PFCAE69_SHIFT               (9u)
+#define GPIO_PFCAE6_PFCAE610_SHIFT              (10u)
+#define GPIO_PFCAE6_PFCAE611_SHIFT              (11u)
+#define GPIO_PFCAE6_PFCAE612_SHIFT              (12u)
+#define GPIO_PFCAE6_PFCAE613_SHIFT              (13u)
+#define GPIO_PFCAE6_PFCAE614_SHIFT              (14u)
+#define GPIO_PFCAE6_PFCAE615_SHIFT              (15u)
+
+#define GPIO_PIBC6_PIBC60_SHIFT                 (0u)
+#define GPIO_PIBC6_PIBC61_SHIFT                 (1u)
+#define GPIO_PIBC6_PIBC62_SHIFT                 (2u)
+#define GPIO_PIBC6_PIBC63_SHIFT                 (3u)
+#define GPIO_PIBC6_PIBC64_SHIFT                 (4u)
+#define GPIO_PIBC6_PIBC65_SHIFT                 (5u)
+#define GPIO_PIBC6_PIBC66_SHIFT                 (6u)
+#define GPIO_PIBC6_PIBC67_SHIFT                 (7u)
+#define GPIO_PIBC6_PIBC68_SHIFT                 (8u)
+#define GPIO_PIBC6_PIBC69_SHIFT                 (9u)
+#define GPIO_PIBC6_PIBC610_SHIFT                (10u)
+#define GPIO_PIBC6_PIBC611_SHIFT                (11u)
+#define GPIO_PIBC6_PIBC612_SHIFT                (12u)
+#define GPIO_PIBC6_PIBC613_SHIFT                (13u)
+#define GPIO_PIBC6_PIBC614_SHIFT                (14u)
+#define GPIO_PIBC6_PIBC615_SHIFT                (15u)
+
+#define GPIO_PBDC6_PBDC60_SHIFT                 (0u)
+#define GPIO_PBDC6_PBDC61_SHIFT                 (1u)
+#define GPIO_PBDC6_PBDC62_SHIFT                 (2u)
+#define GPIO_PBDC6_PBDC63_SHIFT                 (3u)
+#define GPIO_PBDC6_PBDC64_SHIFT                 (4u)
+#define GPIO_PBDC6_PBDC65_SHIFT                 (5u)
+#define GPIO_PBDC6_PBDC66_SHIFT                 (6u)
+#define GPIO_PBDC6_PBDC67_SHIFT                 (7u)
+#define GPIO_PBDC6_PBDC68_SHIFT                 (8u)
+#define GPIO_PBDC6_PBDC69_SHIFT                 (9u)
+#define GPIO_PBDC6_PBDC610_SHIFT                (10u)
+#define GPIO_PBDC6_PBDC611_SHIFT                (11u)
+#define GPIO_PBDC6_PBDC612_SHIFT                (12u)
+#define GPIO_PBDC6_PBDC613_SHIFT                (13u)
+#define GPIO_PBDC6_PBDC614_SHIFT                (14u)
+#define GPIO_PBDC6_PBDC615_SHIFT                (15u)
+
+#define GPIO_PIPC6_PIPC60_SHIFT                 (0u)
+#define GPIO_PIPC6_PIPC61_SHIFT                 (1u)
+#define GPIO_PIPC6_PIPC62_SHIFT                 (2u)
+#define GPIO_PIPC6_PIPC63_SHIFT                 (3u)
+#define GPIO_PIPC6_PIPC64_SHIFT                 (4u)
+#define GPIO_PIPC6_PIPC65_SHIFT                 (5u)
+#define GPIO_PIPC6_PIPC66_SHIFT                 (6u)
+#define GPIO_PIPC6_PIPC67_SHIFT                 (7u)
+#define GPIO_PIPC6_PIPC68_SHIFT                 (8u)
+#define GPIO_PIPC6_PIPC69_SHIFT                 (9u)
+#define GPIO_PIPC6_PIPC610_SHIFT                (10u)
+#define GPIO_PIPC6_PIPC611_SHIFT                (11u)
+#define GPIO_PIPC6_PIPC612_SHIFT                (12u)
+#define GPIO_PIPC6_PIPC613_SHIFT                (13u)
+#define GPIO_PIPC6_PIPC614_SHIFT                (14u)
+#define GPIO_PIPC6_PIPC615_SHIFT                (15u)
+
+/* ---- P7 ---- */
+#define GPIO_P7_P70_SHIFT                       (0u)
+#define GPIO_P7_P71_SHIFT                       (1u)
+#define GPIO_P7_P72_SHIFT                       (2u)
+#define GPIO_P7_P73_SHIFT                       (3u)
+#define GPIO_P7_P74_SHIFT                       (4u)
+#define GPIO_P7_P75_SHIFT                       (5u)
+#define GPIO_P7_P76_SHIFT                       (6u)
+#define GPIO_P7_P77_SHIFT                       (7u)
+#define GPIO_P7_P78_SHIFT                       (8u)
+#define GPIO_P7_P79_SHIFT                       (9u)
+#define GPIO_P7_P710_SHIFT                      (10u)
+#define GPIO_P7_P711_SHIFT                      (11u)
+#define GPIO_P7_P712_SHIFT                      (12u)
+#define GPIO_P7_P713_SHIFT                      (13u)
+#define GPIO_P7_P714_SHIFT                      (14u)
+#define GPIO_P7_P715_SHIFT                      (15u)
+
+#define GPIO_PSR7_PSR70_SHIFT                   (0u)
+#define GPIO_PSR7_PSR71_SHIFT                   (1u)
+#define GPIO_PSR7_PSR72_SHIFT                   (2u)
+#define GPIO_PSR7_PSR73_SHIFT                   (3u)
+#define GPIO_PSR7_PSR74_SHIFT                   (4u)
+#define GPIO_PSR7_PSR75_SHIFT                   (5u)
+#define GPIO_PSR7_PSR76_SHIFT                   (6u)
+#define GPIO_PSR7_PSR77_SHIFT                   (7u)
+#define GPIO_PSR7_PSR78_SHIFT                   (8u)
+#define GPIO_PSR7_PSR79_SHIFT                   (9u)
+#define GPIO_PSR7_PSR710_SHIFT                  (10u)
+#define GPIO_PSR7_PSR711_SHIFT                  (11u)
+#define GPIO_PSR7_PSR712_SHIFT                  (12u)
+#define GPIO_PSR7_PSR713_SHIFT                  (13u)
+#define GPIO_PSR7_PSR714_SHIFT                  (14u)
+#define GPIO_PSR7_PSR715_SHIFT                  (15u)
+#define GPIO_PSR7_PSR716_SHIFT                  (16u)
+#define GPIO_PSR7_PSR717_SHIFT                  (17u)
+#define GPIO_PSR7_PSR718_SHIFT                  (18u)
+#define GPIO_PSR7_PSR719_SHIFT                  (19u)
+#define GPIO_PSR7_PSR720_SHIFT                  (20u)
+#define GPIO_PSR7_PSR721_SHIFT                  (21u)
+#define GPIO_PSR7_PSR722_SHIFT                  (22u)
+#define GPIO_PSR7_PSR723_SHIFT                  (23u)
+#define GPIO_PSR7_PSR724_SHIFT                  (24u)
+#define GPIO_PSR7_PSR725_SHIFT                  (25u)
+#define GPIO_PSR7_PSR726_SHIFT                  (26u)
+#define GPIO_PSR7_PSR727_SHIFT                  (27u)
+#define GPIO_PSR7_PSR728_SHIFT                  (28u)
+#define GPIO_PSR7_PSR729_SHIFT                  (29u)
+#define GPIO_PSR7_PSR730_SHIFT                  (30u)
+#define GPIO_PSR7_PSR731_SHIFT                  (31u)
+
+#define GPIO_PPR7_PPR70_SHIFT                   (0u)
+#define GPIO_PPR7_PPR71_SHIFT                   (1u)
+#define GPIO_PPR7_PPR72_SHIFT                   (2u)
+#define GPIO_PPR7_PPR73_SHIFT                   (3u)
+#define GPIO_PPR7_PPR74_SHIFT                   (4u)
+#define GPIO_PPR7_PPR75_SHIFT                   (5u)
+#define GPIO_PPR7_PPR76_SHIFT                   (6u)
+#define GPIO_PPR7_PPR77_SHIFT                   (7u)
+#define GPIO_PPR7_PPR78_SHIFT                   (8u)
+#define GPIO_PPR7_PPR79_SHIFT                   (9u)
+#define GPIO_PPR7_PPR710_SHIFT                  (10u)
+#define GPIO_PPR7_PPR711_SHIFT                  (11u)
+#define GPIO_PPR7_PPR712_SHIFT                  (12u)
+#define GPIO_PPR7_PPR713_SHIFT                  (13u)
+#define GPIO_PPR7_PPR714_SHIFT                  (14u)
+#define GPIO_PPR7_PPR715_SHIFT                  (15u)
+
+#define GPIO_PM7_PM70_SHIFT                     (0u)
+#define GPIO_PM7_PM71_SHIFT                     (1u)
+#define GPIO_PM7_PM72_SHIFT                     (2u)
+#define GPIO_PM7_PM73_SHIFT                     (3u)
+#define GPIO_PM7_PM74_SHIFT                     (4u)
+#define GPIO_PM7_PM75_SHIFT                     (5u)
+#define GPIO_PM7_PM76_SHIFT                     (6u)
+#define GPIO_PM7_PM77_SHIFT                     (7u)
+#define GPIO_PM7_PM78_SHIFT                     (8u)
+#define GPIO_PM7_PM79_SHIFT                     (9u)
+#define GPIO_PM7_PM710_SHIFT                    (10u)
+#define GPIO_PM7_PM711_SHIFT                    (11u)
+#define GPIO_PM7_PM712_SHIFT                    (12u)
+#define GPIO_PM7_PM713_SHIFT                    (13u)
+#define GPIO_PM7_PM714_SHIFT                    (14u)
+#define GPIO_PM7_PM715_SHIFT                    (15u)
+
+#define GPIO_PMC7_PMC70_SHIFT                   (0u)
+#define GPIO_PMC7_PMC71_SHIFT                   (1u)
+#define GPIO_PMC7_PMC72_SHIFT                   (2u)
+#define GPIO_PMC7_PMC73_SHIFT                   (3u)
+#define GPIO_PMC7_PMC74_SHIFT                   (4u)
+#define GPIO_PMC7_PMC75_SHIFT                   (5u)
+#define GPIO_PMC7_PMC76_SHIFT                   (6u)
+#define GPIO_PMC7_PMC77_SHIFT                   (7u)
+#define GPIO_PMC7_PMC78_SHIFT                   (8u)
+#define GPIO_PMC7_PMC79_SHIFT                   (9u)
+#define GPIO_PMC7_PMC710_SHIFT                  (10u)
+#define GPIO_PMC7_PMC711_SHIFT                  (11u)
+#define GPIO_PMC7_PMC712_SHIFT                  (12u)
+#define GPIO_PMC7_PMC713_SHIFT                  (13u)
+#define GPIO_PMC7_PMC714_SHIFT                  (14u)
+#define GPIO_PMC7_PMC715_SHIFT                  (15u)
+
+#define GPIO_PFC7_PFC70_SHIFT                   (0u)
+#define GPIO_PFC7_PFC71_SHIFT                   (1u)
+#define GPIO_PFC7_PFC72_SHIFT                   (2u)
+#define GPIO_PFC7_PFC73_SHIFT                   (3u)
+#define GPIO_PFC7_PFC74_SHIFT                   (4u)
+#define GPIO_PFC7_PFC75_SHIFT                   (5u)
+#define GPIO_PFC7_PFC76_SHIFT                   (6u)
+#define GPIO_PFC7_PFC77_SHIFT                   (7u)
+#define GPIO_PFC7_PFC78_SHIFT                   (8u)
+#define GPIO_PFC7_PFC79_SHIFT                   (9u)
+#define GPIO_PFC7_PFC710_SHIFT                  (10u)
+#define GPIO_PFC7_PFC711_SHIFT                  (11u)
+#define GPIO_PFC7_PFC712_SHIFT                  (12u)
+#define GPIO_PFC7_PFC713_SHIFT                  (13u)
+#define GPIO_PFC7_PFC714_SHIFT                  (14u)
+#define GPIO_PFC7_PFC715_SHIFT                  (15u)
+
+#define GPIO_PFCE7_PFCE70_SHIFT                 (0u)
+#define GPIO_PFCE7_PFCE71_SHIFT                 (1u)
+#define GPIO_PFCE7_PFCE72_SHIFT                 (2u)
+#define GPIO_PFCE7_PFCE73_SHIFT                 (3u)
+#define GPIO_PFCE7_PFCE74_SHIFT                 (4u)
+#define GPIO_PFCE7_PFCE75_SHIFT                 (5u)
+#define GPIO_PFCE7_PFCE76_SHIFT                 (6u)
+#define GPIO_PFCE7_PFCE77_SHIFT                 (7u)
+#define GPIO_PFCE7_PFCE78_SHIFT                 (8u)
+#define GPIO_PFCE7_PFCE79_SHIFT                 (9u)
+#define GPIO_PFCE7_PFCE710_SHIFT                (10u)
+#define GPIO_PFCE7_PFCE711_SHIFT                (11u)
+#define GPIO_PFCE7_PFCE712_SHIFT                (12u)
+#define GPIO_PFCE7_PFCE713_SHIFT                (13u)
+#define GPIO_PFCE7_PFCE714_SHIFT                (14u)
+#define GPIO_PFCE7_PFCE715_SHIFT                (15u)
+
+#define GPIO_PNOT7_PNOT70_SHIFT                 (0u)
+#define GPIO_PNOT7_PNOT71_SHIFT                 (1u)
+#define GPIO_PNOT7_PNOT72_SHIFT                 (2u)
+#define GPIO_PNOT7_PNOT73_SHIFT                 (3u)
+#define GPIO_PNOT7_PNOT74_SHIFT                 (4u)
+#define GPIO_PNOT7_PNOT75_SHIFT                 (5u)
+#define GPIO_PNOT7_PNOT76_SHIFT                 (6u)
+#define GPIO_PNOT7_PNOT77_SHIFT                 (7u)
+#define GPIO_PNOT7_PNOT78_SHIFT                 (8u)
+#define GPIO_PNOT7_PNOT79_SHIFT                 (9u)
+#define GPIO_PNOT7_PNOT710_SHIFT                (10u)
+#define GPIO_PNOT7_PNOT711_SHIFT                (11u)
+#define GPIO_PNOT7_PNOT712_SHIFT                (12u)
+#define GPIO_PNOT7_PNOT713_SHIFT                (13u)
+#define GPIO_PNOT7_PNOT714_SHIFT                (14u)
+#define GPIO_PNOT7_PNOT715_SHIFT                (15u)
+
+#define GPIO_PMSR7_PMSR70_SHIFT                 (0u)
+#define GPIO_PMSR7_PMSR71_SHIFT                 (1u)
+#define GPIO_PMSR7_PMSR72_SHIFT                 (2u)
+#define GPIO_PMSR7_PMSR73_SHIFT                 (3u)
+#define GPIO_PMSR7_PMSR74_SHIFT                 (4u)
+#define GPIO_PMSR7_PMSR75_SHIFT                 (5u)
+#define GPIO_PMSR7_PMSR76_SHIFT                 (6u)
+#define GPIO_PMSR7_PMSR77_SHIFT                 (7u)
+#define GPIO_PMSR7_PMSR78_SHIFT                 (8u)
+#define GPIO_PMSR7_PMSR79_SHIFT                 (9u)
+#define GPIO_PMSR7_PMSR710_SHIFT                (10u)
+#define GPIO_PMSR7_PMSR711_SHIFT                (11u)
+#define GPIO_PMSR7_PMSR712_SHIFT                (12u)
+#define GPIO_PMSR7_PMSR713_SHIFT                (13u)
+#define GPIO_PMSR7_PMSR714_SHIFT                (14u)
+#define GPIO_PMSR7_PMSR715_SHIFT                (15u)
+#define GPIO_PMSR7_PMSR716_SHIFT                (16u)
+#define GPIO_PMSR7_PMSR717_SHIFT                (17u)
+#define GPIO_PMSR7_PMSR718_SHIFT                (18u)
+#define GPIO_PMSR7_PMSR719_SHIFT                (19u)
+#define GPIO_PMSR7_PMSR720_SHIFT                (20u)
+#define GPIO_PMSR7_PMSR721_SHIFT                (21u)
+#define GPIO_PMSR7_PMSR722_SHIFT                (22u)
+#define GPIO_PMSR7_PMSR723_SHIFT                (23u)
+#define GPIO_PMSR7_PMSR724_SHIFT                (24u)
+#define GPIO_PMSR7_PMSR725_SHIFT                (25u)
+#define GPIO_PMSR7_PMSR726_SHIFT                (26u)
+#define GPIO_PMSR7_PMSR727_SHIFT                (27u)
+#define GPIO_PMSR7_PMSR728_SHIFT                (28u)
+#define GPIO_PMSR7_PMSR729_SHIFT                (29u)
+#define GPIO_PMSR7_PMSR730_SHIFT                (30u)
+#define GPIO_PMSR7_PMSR731_SHIFT                (31u)
+
+#define GPIO_PMCSR7_PMCSR70_SHIFT               (0u)
+#define GPIO_PMCSR7_PMCSR71_SHIFT               (1u)
+#define GPIO_PMCSR7_PMCSR72_SHIFT               (2u)
+#define GPIO_PMCSR7_PMCSR73_SHIFT               (3u)
+#define GPIO_PMCSR7_PMCSR74_SHIFT               (4u)
+#define GPIO_PMCSR7_PMCSR75_SHIFT               (5u)
+#define GPIO_PMCSR7_PMCSR76_SHIFT               (6u)
+#define GPIO_PMCSR7_PMCSR77_SHIFT               (7u)
+#define GPIO_PMCSR7_PMCSR78_SHIFT               (8u)
+#define GPIO_PMCSR7_PMCSR79_SHIFT               (9u)
+#define GPIO_PMCSR7_PMCSR710_SHIFT              (10u)
+#define GPIO_PMCSR7_PMCSR711_SHIFT              (11u)
+#define GPIO_PMCSR7_PMCSR712_SHIFT              (12u)
+#define GPIO_PMCSR7_PMCSR713_SHIFT              (13u)
+#define GPIO_PMCSR7_PMCSR714_SHIFT              (14u)
+#define GPIO_PMCSR7_PMCSR715_SHIFT              (15u)
+#define GPIO_PMCSR7_PMCSR716_SHIFT              (16u)
+#define GPIO_PMCSR7_PMCSR717_SHIFT              (17u)
+#define GPIO_PMCSR7_PMCSR718_SHIFT              (18u)
+#define GPIO_PMCSR7_PMCSR719_SHIFT              (19u)
+#define GPIO_PMCSR7_PMCSR720_SHIFT              (20u)
+#define GPIO_PMCSR7_PMCSR721_SHIFT              (21u)
+#define GPIO_PMCSR7_PMCSR722_SHIFT              (22u)
+#define GPIO_PMCSR7_PMCSR723_SHIFT              (23u)
+#define GPIO_PMCSR7_PMCSR724_SHIFT              (24u)
+#define GPIO_PMCSR7_PMCSR725_SHIFT              (25u)
+#define GPIO_PMCSR7_PMCSR726_SHIFT              (26u)
+#define GPIO_PMCSR7_PMCSR727_SHIFT              (27u)
+#define GPIO_PMCSR7_PMCSR728_SHIFT              (28u)
+#define GPIO_PMCSR7_PMCSR729_SHIFT              (29u)
+#define GPIO_PMCSR7_PMCSR730_SHIFT              (30u)
+#define GPIO_PMCSR7_PMCSR731_SHIFT              (31u)
+
+#define GPIO_PFCAE7_PFCAE70_SHIFT               (0u)
+#define GPIO_PFCAE7_PFCAE71_SHIFT               (1u)
+#define GPIO_PFCAE7_PFCAE72_SHIFT               (2u)
+#define GPIO_PFCAE7_PFCAE73_SHIFT               (3u)
+#define GPIO_PFCAE7_PFCAE74_SHIFT               (4u)
+#define GPIO_PFCAE7_PFCAE75_SHIFT               (5u)
+#define GPIO_PFCAE7_PFCAE76_SHIFT               (6u)
+#define GPIO_PFCAE7_PFCAE77_SHIFT               (7u)
+#define GPIO_PFCAE7_PFCAE78_SHIFT               (8u)
+#define GPIO_PFCAE7_PFCAE79_SHIFT               (9u)
+#define GPIO_PFCAE7_PFCAE710_SHIFT              (10u)
+#define GPIO_PFCAE7_PFCAE711_SHIFT              (11u)
+#define GPIO_PFCAE7_PFCAE712_SHIFT              (12u)
+#define GPIO_PFCAE7_PFCAE713_SHIFT              (13u)
+#define GPIO_PFCAE7_PFCAE714_SHIFT              (14u)
+#define GPIO_PFCAE7_PFCAE715_SHIFT              (15u)
+
+#define GPIO_PIBC7_PIBC70_SHIFT                 (0u)
+#define GPIO_PIBC7_PIBC71_SHIFT                 (1u)
+#define GPIO_PIBC7_PIBC72_SHIFT                 (2u)
+#define GPIO_PIBC7_PIBC73_SHIFT                 (3u)
+#define GPIO_PIBC7_PIBC74_SHIFT                 (4u)
+#define GPIO_PIBC7_PIBC75_SHIFT                 (5u)
+#define GPIO_PIBC7_PIBC76_SHIFT                 (6u)
+#define GPIO_PIBC7_PIBC77_SHIFT                 (7u)
+#define GPIO_PIBC7_PIBC78_SHIFT                 (8u)
+#define GPIO_PIBC7_PIBC79_SHIFT                 (9u)
+#define GPIO_PIBC7_PIBC710_SHIFT                (10u)
+#define GPIO_PIBC7_PIBC711_SHIFT                (11u)
+#define GPIO_PIBC7_PIBC712_SHIFT                (12u)
+#define GPIO_PIBC7_PIBC713_SHIFT                (13u)
+#define GPIO_PIBC7_PIBC714_SHIFT                (14u)
+#define GPIO_PIBC7_PIBC715_SHIFT                (15u)
+
+#define GPIO_PBDC7_PBDC70_SHIFT                 (0u)
+#define GPIO_PBDC7_PBDC71_SHIFT                 (1u)
+#define GPIO_PBDC7_PBDC72_SHIFT                 (2u)
+#define GPIO_PBDC7_PBDC73_SHIFT                 (3u)
+#define GPIO_PBDC7_PBDC74_SHIFT                 (4u)
+#define GPIO_PBDC7_PBDC75_SHIFT                 (5u)
+#define GPIO_PBDC7_PBDC76_SHIFT                 (6u)
+#define GPIO_PBDC7_PBDC77_SHIFT                 (7u)
+#define GPIO_PBDC7_PBDC78_SHIFT                 (8u)
+#define GPIO_PBDC7_PBDC79_SHIFT                 (9u)
+#define GPIO_PBDC7_PBDC710_SHIFT                (10u)
+#define GPIO_PBDC7_PBDC711_SHIFT                (11u)
+#define GPIO_PBDC7_PBDC712_SHIFT                (12u)
+#define GPIO_PBDC7_PBDC713_SHIFT                (13u)
+#define GPIO_PBDC7_PBDC714_SHIFT                (14u)
+#define GPIO_PBDC7_PBDC715_SHIFT                (15u)
+
+#define GPIO_PIPC7_PIPC70_SHIFT                 (0u)
+#define GPIO_PIPC7_PIPC71_SHIFT                 (1u)
+#define GPIO_PIPC7_PIPC72_SHIFT                 (2u)
+#define GPIO_PIPC7_PIPC73_SHIFT                 (3u)
+#define GPIO_PIPC7_PIPC74_SHIFT                 (4u)
+#define GPIO_PIPC7_PIPC75_SHIFT                 (5u)
+#define GPIO_PIPC7_PIPC76_SHIFT                 (6u)
+#define GPIO_PIPC7_PIPC77_SHIFT                 (7u)
+#define GPIO_PIPC7_PIPC78_SHIFT                 (8u)
+#define GPIO_PIPC7_PIPC79_SHIFT                 (9u)
+#define GPIO_PIPC7_PIPC710_SHIFT                (10u)
+#define GPIO_PIPC7_PIPC711_SHIFT                (11u)
+#define GPIO_PIPC7_PIPC712_SHIFT                (12u)
+#define GPIO_PIPC7_PIPC713_SHIFT                (13u)
+#define GPIO_PIPC7_PIPC714_SHIFT                (14u)
+#define GPIO_PIPC7_PIPC715_SHIFT                (15u)
+
+/* ---- P8 ---- */
+#define GPIO_P8_P80_SHIFT                       (0u)
+#define GPIO_P8_P81_SHIFT                       (1u)
+#define GPIO_P8_P82_SHIFT                       (2u)
+#define GPIO_P8_P83_SHIFT                       (3u)
+#define GPIO_P8_P84_SHIFT                       (4u)
+#define GPIO_P8_P85_SHIFT                       (5u)
+#define GPIO_P8_P86_SHIFT                       (6u)
+#define GPIO_P8_P87_SHIFT                       (7u)
+#define GPIO_P8_P88_SHIFT                       (8u)
+#define GPIO_P8_P89_SHIFT                       (9u)
+#define GPIO_P8_P810_SHIFT                      (10u)
+#define GPIO_P8_P811_SHIFT                      (11u)
+#define GPIO_P8_P812_SHIFT                      (12u)
+#define GPIO_P8_P813_SHIFT                      (13u)
+#define GPIO_P8_P814_SHIFT                      (14u)
+#define GPIO_P8_P815_SHIFT                      (15u)
+
+#define GPIO_PSR8_PSR80_SHIFT                   (0u)
+#define GPIO_PSR8_PSR81_SHIFT                   (1u)
+#define GPIO_PSR8_PSR82_SHIFT                   (2u)
+#define GPIO_PSR8_PSR83_SHIFT                   (3u)
+#define GPIO_PSR8_PSR84_SHIFT                   (4u)
+#define GPIO_PSR8_PSR85_SHIFT                   (5u)
+#define GPIO_PSR8_PSR86_SHIFT                   (6u)
+#define GPIO_PSR8_PSR87_SHIFT                   (7u)
+#define GPIO_PSR8_PSR88_SHIFT                   (8u)
+#define GPIO_PSR8_PSR89_SHIFT                   (9u)
+#define GPIO_PSR8_PSR810_SHIFT                  (10u)
+#define GPIO_PSR8_PSR811_SHIFT                  (11u)
+#define GPIO_PSR8_PSR812_SHIFT                  (12u)
+#define GPIO_PSR8_PSR813_SHIFT                  (13u)
+#define GPIO_PSR8_PSR814_SHIFT                  (14u)
+#define GPIO_PSR8_PSR815_SHIFT                  (15u)
+#define GPIO_PSR8_PSR816_SHIFT                  (16u)
+#define GPIO_PSR8_PSR817_SHIFT                  (17u)
+#define GPIO_PSR8_PSR818_SHIFT                  (18u)
+#define GPIO_PSR8_PSR819_SHIFT                  (19u)
+#define GPIO_PSR8_PSR820_SHIFT                  (20u)
+#define GPIO_PSR8_PSR821_SHIFT                  (21u)
+#define GPIO_PSR8_PSR822_SHIFT                  (22u)
+#define GPIO_PSR8_PSR823_SHIFT                  (23u)
+#define GPIO_PSR8_PSR824_SHIFT                  (24u)
+#define GPIO_PSR8_PSR825_SHIFT                  (25u)
+#define GPIO_PSR8_PSR826_SHIFT                  (26u)
+#define GPIO_PSR8_PSR827_SHIFT                  (27u)
+#define GPIO_PSR8_PSR828_SHIFT                  (28u)
+#define GPIO_PSR8_PSR829_SHIFT                  (29u)
+#define GPIO_PSR8_PSR830_SHIFT                  (30u)
+#define GPIO_PSR8_PSR831_SHIFT                  (31u)
+
+#define GPIO_PPR8_PPR80_SHIFT                   (0u)
+#define GPIO_PPR8_PPR81_SHIFT                   (1u)
+#define GPIO_PPR8_PPR82_SHIFT                   (2u)
+#define GPIO_PPR8_PPR83_SHIFT                   (3u)
+#define GPIO_PPR8_PPR84_SHIFT                   (4u)
+#define GPIO_PPR8_PPR85_SHIFT                   (5u)
+#define GPIO_PPR8_PPR86_SHIFT                   (6u)
+#define GPIO_PPR8_PPR87_SHIFT                   (7u)
+#define GPIO_PPR8_PPR88_SHIFT                   (8u)
+#define GPIO_PPR8_PPR89_SHIFT                   (9u)
+#define GPIO_PPR8_PPR810_SHIFT                  (10u)
+#define GPIO_PPR8_PPR811_SHIFT                  (11u)
+#define GPIO_PPR8_PPR812_SHIFT                  (12u)
+#define GPIO_PPR8_PPR813_SHIFT                  (13u)
+#define GPIO_PPR8_PPR814_SHIFT                  (14u)
+#define GPIO_PPR8_PPR815_SHIFT                  (15u)
+
+#define GPIO_PM8_PM80_SHIFT                     (0u)
+#define GPIO_PM8_PM81_SHIFT                     (1u)
+#define GPIO_PM8_PM82_SHIFT                     (2u)
+#define GPIO_PM8_PM83_SHIFT                     (3u)
+#define GPIO_PM8_PM84_SHIFT                     (4u)
+#define GPIO_PM8_PM85_SHIFT                     (5u)
+#define GPIO_PM8_PM86_SHIFT                     (6u)
+#define GPIO_PM8_PM87_SHIFT                     (7u)
+#define GPIO_PM8_PM88_SHIFT                     (8u)
+#define GPIO_PM8_PM89_SHIFT                     (9u)
+#define GPIO_PM8_PM810_SHIFT                    (10u)
+#define GPIO_PM8_PM811_SHIFT                    (11u)
+#define GPIO_PM8_PM812_SHIFT                    (12u)
+#define GPIO_PM8_PM813_SHIFT                    (13u)
+#define GPIO_PM8_PM814_SHIFT                    (14u)
+#define GPIO_PM8_PM815_SHIFT                    (15u)
+
+#define GPIO_PMC8_PMC80_SHIFT                   (0u)
+#define GPIO_PMC8_PMC81_SHIFT                   (1u)
+#define GPIO_PMC8_PMC82_SHIFT                   (2u)
+#define GPIO_PMC8_PMC83_SHIFT                   (3u)
+#define GPIO_PMC8_PMC84_SHIFT                   (4u)
+#define GPIO_PMC8_PMC85_SHIFT                   (5u)
+#define GPIO_PMC8_PMC86_SHIFT                   (6u)
+#define GPIO_PMC8_PMC87_SHIFT                   (7u)
+#define GPIO_PMC8_PMC88_SHIFT                   (8u)
+#define GPIO_PMC8_PMC89_SHIFT                   (9u)
+#define GPIO_PMC8_PMC810_SHIFT                  (10u)
+#define GPIO_PMC8_PMC811_SHIFT                  (11u)
+#define GPIO_PMC8_PMC812_SHIFT                  (12u)
+#define GPIO_PMC8_PMC813_SHIFT                  (13u)
+#define GPIO_PMC8_PMC814_SHIFT                  (14u)
+#define GPIO_PMC8_PMC815_SHIFT                  (15u)
+
+#define GPIO_PFC8_PFC80_SHIFT                   (0u)
+#define GPIO_PFC8_PFC81_SHIFT                   (1u)
+#define GPIO_PFC8_PFC82_SHIFT                   (2u)
+#define GPIO_PFC8_PFC83_SHIFT                   (3u)
+#define GPIO_PFC8_PFC84_SHIFT                   (4u)
+#define GPIO_PFC8_PFC85_SHIFT                   (5u)
+#define GPIO_PFC8_PFC86_SHIFT                   (6u)
+#define GPIO_PFC8_PFC87_SHIFT                   (7u)
+#define GPIO_PFC8_PFC88_SHIFT                   (8u)
+#define GPIO_PFC8_PFC89_SHIFT                   (9u)
+#define GPIO_PFC8_PFC810_SHIFT                  (10u)
+#define GPIO_PFC8_PFC811_SHIFT                  (11u)
+#define GPIO_PFC8_PFC812_SHIFT                  (12u)
+#define GPIO_PFC8_PFC813_SHIFT                  (13u)
+#define GPIO_PFC8_PFC814_SHIFT                  (14u)
+#define GPIO_PFC8_PFC815_SHIFT                  (15u)
+
+#define GPIO_PFCE8_PFCE80_SHIFT                 (0u)
+#define GPIO_PFCE8_PFCE81_SHIFT                 (1u)
+#define GPIO_PFCE8_PFCE82_SHIFT                 (2u)
+#define GPIO_PFCE8_PFCE83_SHIFT                 (3u)
+#define GPIO_PFCE8_PFCE84_SHIFT                 (4u)
+#define GPIO_PFCE8_PFCE85_SHIFT                 (5u)
+#define GPIO_PFCE8_PFCE86_SHIFT                 (6u)
+#define GPIO_PFCE8_PFCE87_SHIFT                 (7u)
+#define GPIO_PFCE8_PFCE88_SHIFT                 (8u)
+#define GPIO_PFCE8_PFCE89_SHIFT                 (9u)
+#define GPIO_PFCE8_PFCE810_SHIFT                (10u)
+#define GPIO_PFCE8_PFCE811_SHIFT                (11u)
+#define GPIO_PFCE8_PFCE812_SHIFT                (12u)
+#define GPIO_PFCE8_PFCE813_SHIFT                (13u)
+#define GPIO_PFCE8_PFCE814_SHIFT                (14u)
+#define GPIO_PFCE8_PFCE815_SHIFT                (15u)
+
+#define GPIO_PNOT8_PNOT80_SHIFT                 (0u)
+#define GPIO_PNOT8_PNOT81_SHIFT                 (1u)
+#define GPIO_PNOT8_PNOT82_SHIFT                 (2u)
+#define GPIO_PNOT8_PNOT83_SHIFT                 (3u)
+#define GPIO_PNOT8_PNOT84_SHIFT                 (4u)
+#define GPIO_PNOT8_PNOT85_SHIFT                 (5u)
+#define GPIO_PNOT8_PNOT86_SHIFT                 (6u)
+#define GPIO_PNOT8_PNOT87_SHIFT                 (7u)
+#define GPIO_PNOT8_PNOT88_SHIFT                 (8u)
+#define GPIO_PNOT8_PNOT89_SHIFT                 (9u)
+#define GPIO_PNOT8_PNOT810_SHIFT                (10u)
+#define GPIO_PNOT8_PNOT811_SHIFT                (11u)
+#define GPIO_PNOT8_PNOT812_SHIFT                (12u)
+#define GPIO_PNOT8_PNOT813_SHIFT                (13u)
+#define GPIO_PNOT8_PNOT814_SHIFT                (14u)
+#define GPIO_PNOT8_PNOT815_SHIFT                (15u)
+
+#define GPIO_PMSR8_PMSR80_SHIFT                 (0u)
+#define GPIO_PMSR8_PMSR81_SHIFT                 (1u)
+#define GPIO_PMSR8_PMSR82_SHIFT                 (2u)
+#define GPIO_PMSR8_PMSR83_SHIFT                 (3u)
+#define GPIO_PMSR8_PMSR84_SHIFT                 (4u)
+#define GPIO_PMSR8_PMSR85_SHIFT                 (5u)
+#define GPIO_PMSR8_PMSR86_SHIFT                 (6u)
+#define GPIO_PMSR8_PMSR87_SHIFT                 (7u)
+#define GPIO_PMSR8_PMSR88_SHIFT                 (8u)
+#define GPIO_PMSR8_PMSR89_SHIFT                 (9u)
+#define GPIO_PMSR8_PMSR810_SHIFT                (10u)
+#define GPIO_PMSR8_PMSR811_SHIFT                (11u)
+#define GPIO_PMSR8_PMSR812_SHIFT                (12u)
+#define GPIO_PMSR8_PMSR813_SHIFT                (13u)
+#define GPIO_PMSR8_PMSR814_SHIFT                (14u)
+#define GPIO_PMSR8_PMSR815_SHIFT                (15u)
+#define GPIO_PMSR8_PMSR816_SHIFT                (16u)
+#define GPIO_PMSR8_PMSR817_SHIFT                (17u)
+#define GPIO_PMSR8_PMSR818_SHIFT                (18u)
+#define GPIO_PMSR8_PMSR819_SHIFT                (19u)
+#define GPIO_PMSR8_PMSR820_SHIFT                (20u)
+#define GPIO_PMSR8_PMSR821_SHIFT                (21u)
+#define GPIO_PMSR8_PMSR822_SHIFT                (22u)
+#define GPIO_PMSR8_PMSR823_SHIFT                (23u)
+#define GPIO_PMSR8_PMSR824_SHIFT                (24u)
+#define GPIO_PMSR8_PMSR825_SHIFT                (25u)
+#define GPIO_PMSR8_PMSR826_SHIFT                (26u)
+#define GPIO_PMSR8_PMSR827_SHIFT                (27u)
+#define GPIO_PMSR8_PMSR828_SHIFT                (28u)
+#define GPIO_PMSR8_PMSR829_SHIFT                (29u)
+#define GPIO_PMSR8_PMSR830_SHIFT                (30u)
+#define GPIO_PMSR8_PMSR831_SHIFT                (31u)
+
+#define GPIO_PMCSR8_PMCSR80_SHIFT               (0u)
+#define GPIO_PMCSR8_PMCSR81_SHIFT               (1u)
+#define GPIO_PMCSR8_PMCSR82_SHIFT               (2u)
+#define GPIO_PMCSR8_PMCSR83_SHIFT               (3u)
+#define GPIO_PMCSR8_PMCSR84_SHIFT               (4u)
+#define GPIO_PMCSR8_PMCSR85_SHIFT               (5u)
+#define GPIO_PMCSR8_PMCSR86_SHIFT               (6u)
+#define GPIO_PMCSR8_PMCSR87_SHIFT               (7u)
+#define GPIO_PMCSR8_PMCSR88_SHIFT               (8u)
+#define GPIO_PMCSR8_PMCSR89_SHIFT               (9u)
+#define GPIO_PMCSR8_PMCSR810_SHIFT              (10u)
+#define GPIO_PMCSR8_PMCSR811_SHIFT              (11u)
+#define GPIO_PMCSR8_PMCSR812_SHIFT              (12u)
+#define GPIO_PMCSR8_PMCSR813_SHIFT              (13u)
+#define GPIO_PMCSR8_PMCSR814_SHIFT              (14u)
+#define GPIO_PMCSR8_PMCSR815_SHIFT              (15u)
+#define GPIO_PMCSR8_PMCSR816_SHIFT              (16u)
+#define GPIO_PMCSR8_PMCSR817_SHIFT              (17u)
+#define GPIO_PMCSR8_PMCSR818_SHIFT              (18u)
+#define GPIO_PMCSR8_PMCSR819_SHIFT              (19u)
+#define GPIO_PMCSR8_PMCSR820_SHIFT              (20u)
+#define GPIO_PMCSR8_PMCSR821_SHIFT              (21u)
+#define GPIO_PMCSR8_PMCSR822_SHIFT              (22u)
+#define GPIO_PMCSR8_PMCSR823_SHIFT              (23u)
+#define GPIO_PMCSR8_PMCSR824_SHIFT              (24u)
+#define GPIO_PMCSR8_PMCSR825_SHIFT              (25u)
+#define GPIO_PMCSR8_PMCSR826_SHIFT              (26u)
+#define GPIO_PMCSR8_PMCSR827_SHIFT              (27u)
+#define GPIO_PMCSR8_PMCSR828_SHIFT              (28u)
+#define GPIO_PMCSR8_PMCSR829_SHIFT              (29u)
+#define GPIO_PMCSR8_PMCSR830_SHIFT              (30u)
+#define GPIO_PMCSR8_PMCSR831_SHIFT              (31u)
+
+#define GPIO_PFCAE8_PFCAE80_SHIFT               (0u)
+#define GPIO_PFCAE8_PFCAE81_SHIFT               (1u)
+#define GPIO_PFCAE8_PFCAE82_SHIFT               (2u)
+#define GPIO_PFCAE8_PFCAE83_SHIFT               (3u)
+#define GPIO_PFCAE8_PFCAE84_SHIFT               (4u)
+#define GPIO_PFCAE8_PFCAE85_SHIFT               (5u)
+#define GPIO_PFCAE8_PFCAE86_SHIFT               (6u)
+#define GPIO_PFCAE8_PFCAE87_SHIFT               (7u)
+#define GPIO_PFCAE8_PFCAE88_SHIFT               (8u)
+#define GPIO_PFCAE8_PFCAE89_SHIFT               (9u)
+#define GPIO_PFCAE8_PFCAE810_SHIFT              (10u)
+#define GPIO_PFCAE8_PFCAE811_SHIFT              (11u)
+#define GPIO_PFCAE8_PFCAE812_SHIFT              (12u)
+#define GPIO_PFCAE8_PFCAE813_SHIFT              (13u)
+#define GPIO_PFCAE8_PFCAE814_SHIFT              (14u)
+#define GPIO_PFCAE8_PFCAE815_SHIFT              (15u)
+
+#define GPIO_PIBC8_PIBC80_SHIFT                 (0u)
+#define GPIO_PIBC8_PIBC81_SHIFT                 (1u)
+#define GPIO_PIBC8_PIBC82_SHIFT                 (2u)
+#define GPIO_PIBC8_PIBC83_SHIFT                 (3u)
+#define GPIO_PIBC8_PIBC84_SHIFT                 (4u)
+#define GPIO_PIBC8_PIBC85_SHIFT                 (5u)
+#define GPIO_PIBC8_PIBC86_SHIFT                 (6u)
+#define GPIO_PIBC8_PIBC87_SHIFT                 (7u)
+#define GPIO_PIBC8_PIBC88_SHIFT                 (8u)
+#define GPIO_PIBC8_PIBC89_SHIFT                 (9u)
+#define GPIO_PIBC8_PIBC810_SHIFT                (10u)
+#define GPIO_PIBC8_PIBC811_SHIFT                (11u)
+#define GPIO_PIBC8_PIBC812_SHIFT                (12u)
+#define GPIO_PIBC8_PIBC813_SHIFT                (13u)
+#define GPIO_PIBC8_PIBC814_SHIFT                (14u)
+#define GPIO_PIBC8_PIBC815_SHIFT                (15u)
+
+#define GPIO_PBDC8_PBDC80_SHIFT                 (0u)
+#define GPIO_PBDC8_PBDC81_SHIFT                 (1u)
+#define GPIO_PBDC8_PBDC82_SHIFT                 (2u)
+#define GPIO_PBDC8_PBDC83_SHIFT                 (3u)
+#define GPIO_PBDC8_PBDC84_SHIFT                 (4u)
+#define GPIO_PBDC8_PBDC85_SHIFT                 (5u)
+#define GPIO_PBDC8_PBDC86_SHIFT                 (6u)
+#define GPIO_PBDC8_PBDC87_SHIFT                 (7u)
+#define GPIO_PBDC8_PBDC88_SHIFT                 (8u)
+#define GPIO_PBDC8_PBDC89_SHIFT                 (9u)
+#define GPIO_PBDC8_PBDC810_SHIFT                (10u)
+#define GPIO_PBDC8_PBDC811_SHIFT                (11u)
+#define GPIO_PBDC8_PBDC812_SHIFT                (12u)
+#define GPIO_PBDC8_PBDC813_SHIFT                (13u)
+#define GPIO_PBDC8_PBDC814_SHIFT                (14u)
+#define GPIO_PBDC8_PBDC815_SHIFT                (15u)
+
+#define GPIO_PIPC8_PIPC80_SHIFT                 (0u)
+#define GPIO_PIPC8_PIPC81_SHIFT                 (1u)
+#define GPIO_PIPC8_PIPC82_SHIFT                 (2u)
+#define GPIO_PIPC8_PIPC83_SHIFT                 (3u)
+#define GPIO_PIPC8_PIPC84_SHIFT                 (4u)
+#define GPIO_PIPC8_PIPC85_SHIFT                 (5u)
+#define GPIO_PIPC8_PIPC86_SHIFT                 (6u)
+#define GPIO_PIPC8_PIPC87_SHIFT                 (7u)
+#define GPIO_PIPC8_PIPC88_SHIFT                 (8u)
+#define GPIO_PIPC8_PIPC89_SHIFT                 (9u)
+#define GPIO_PIPC8_PIPC810_SHIFT                (10u)
+#define GPIO_PIPC8_PIPC811_SHIFT                (11u)
+#define GPIO_PIPC8_PIPC812_SHIFT                (12u)
+#define GPIO_PIPC8_PIPC813_SHIFT                (13u)
+#define GPIO_PIPC8_PIPC814_SHIFT                (14u)
+#define GPIO_PIPC8_PIPC815_SHIFT                (15u)
+
+/* ---- P9 ---- */
+#define GPIO_P9_P90_SHIFT                       (0u)
+#define GPIO_P9_P91_SHIFT                       (1u)
+#define GPIO_P9_P92_SHIFT                       (2u)
+#define GPIO_P9_P93_SHIFT                       (3u)
+#define GPIO_P9_P94_SHIFT                       (4u)
+#define GPIO_P9_P95_SHIFT                       (5u)
+#define GPIO_P9_P96_SHIFT                       (6u)
+#define GPIO_P9_P97_SHIFT                       (7u)
+
+#define GPIO_PSR9_PSR90_SHIFT                   (0u)
+#define GPIO_PSR9_PSR91_SHIFT                   (1u)
+#define GPIO_PSR9_PSR92_SHIFT                   (2u)
+#define GPIO_PSR9_PSR93_SHIFT                   (3u)
+#define GPIO_PSR9_PSR94_SHIFT                   (4u)
+#define GPIO_PSR9_PSR95_SHIFT                   (5u)
+#define GPIO_PSR9_PSR96_SHIFT                   (6u)
+#define GPIO_PSR9_PSR97_SHIFT                   (7u)
+#define GPIO_PSR9_PSR916_SHIFT                  (16u)
+#define GPIO_PSR9_PSR917_SHIFT                  (17u)
+#define GPIO_PSR9_PSR918_SHIFT                  (18u)
+#define GPIO_PSR9_PSR919_SHIFT                  (19u)
+#define GPIO_PSR9_PSR920_SHIFT                  (20u)
+#define GPIO_PSR9_PSR921_SHIFT                  (21u)
+#define GPIO_PSR9_PSR922_SHIFT                  (22u)
+#define GPIO_PSR9_PSR923_SHIFT                  (23u)
+
+#define GPIO_PPR9_PPR90_SHIFT                   (0u)
+#define GPIO_PPR9_PPR91_SHIFT                   (1u)
+#define GPIO_PPR9_PPR92_SHIFT                   (2u)
+#define GPIO_PPR9_PPR93_SHIFT                   (3u)
+#define GPIO_PPR9_PPR94_SHIFT                   (4u)
+#define GPIO_PPR9_PPR95_SHIFT                   (5u)
+#define GPIO_PPR9_PPR96_SHIFT                   (6u)
+#define GPIO_PPR9_PPR97_SHIFT                   (7u)
+
+#define GPIO_PM9_PM90_SHIFT                     (0u)
+#define GPIO_PM9_PM91_SHIFT                     (1u)
+#define GPIO_PM9_PM92_SHIFT                     (2u)
+#define GPIO_PM9_PM93_SHIFT                     (3u)
+#define GPIO_PM9_PM94_SHIFT                     (4u)
+#define GPIO_PM9_PM95_SHIFT                     (5u)
+#define GPIO_PM9_PM96_SHIFT                     (6u)
+#define GPIO_PM9_PM97_SHIFT                     (7u)
+
+#define GPIO_PMC9_PMC90_SHIFT                   (0u)
+#define GPIO_PMC9_PMC91_SHIFT                   (1u)
+#define GPIO_PMC9_PMC92_SHIFT                   (2u)
+#define GPIO_PMC9_PMC93_SHIFT                   (3u)
+#define GPIO_PMC9_PMC94_SHIFT                   (4u)
+#define GPIO_PMC9_PMC95_SHIFT                   (5u)
+#define GPIO_PMC9_PMC96_SHIFT                   (6u)
+#define GPIO_PMC9_PMC97_SHIFT                   (7u)
+
+#define GPIO_PFC9_PFC90_SHIFT                   (0u)
+#define GPIO_PFC9_PFC91_SHIFT                   (1u)
+#define GPIO_PFC9_PFC92_SHIFT                   (2u)
+#define GPIO_PFC9_PFC93_SHIFT                   (3u)
+#define GPIO_PFC9_PFC94_SHIFT                   (4u)
+#define GPIO_PFC9_PFC95_SHIFT                   (5u)
+#define GPIO_PFC9_PFC96_SHIFT                   (6u)
+#define GPIO_PFC9_PFC97_SHIFT                   (7u)
+
+#define GPIO_PFCE9_PFCE90_SHIFT                 (0u)
+#define GPIO_PFCE9_PFCE91_SHIFT                 (1u)
+#define GPIO_PFCE9_PFCE92_SHIFT                 (2u)
+#define GPIO_PFCE9_PFCE93_SHIFT                 (3u)
+#define GPIO_PFCE9_PFCE94_SHIFT                 (4u)
+#define GPIO_PFCE9_PFCE95_SHIFT                 (5u)
+#define GPIO_PFCE9_PFCE96_SHIFT                 (6u)
+#define GPIO_PFCE9_PFCE97_SHIFT                 (7u)
+
+#define GPIO_PNOT9_PNOT90_SHIFT                 (0u)
+#define GPIO_PNOT9_PNOT91_SHIFT                 (1u)
+#define GPIO_PNOT9_PNOT92_SHIFT                 (2u)
+#define GPIO_PNOT9_PNOT93_SHIFT                 (3u)
+#define GPIO_PNOT9_PNOT94_SHIFT                 (4u)
+#define GPIO_PNOT9_PNOT95_SHIFT                 (5u)
+#define GPIO_PNOT9_PNOT96_SHIFT                 (6u)
+#define GPIO_PNOT9_PNOT97_SHIFT                 (7u)
+
+#define GPIO_PMSR9_PMSR90_SHIFT                 (0u)
+#define GPIO_PMSR9_PMSR91_SHIFT                 (1u)
+#define GPIO_PMSR9_PMSR92_SHIFT                 (2u)
+#define GPIO_PMSR9_PMSR93_SHIFT                 (3u)
+#define GPIO_PMSR9_PMSR94_SHIFT                 (4u)
+#define GPIO_PMSR9_PMSR95_SHIFT                 (5u)
+#define GPIO_PMSR9_PMSR96_SHIFT                 (6u)
+#define GPIO_PMSR9_PMSR97_SHIFT                 (7u)
+#define GPIO_PMSR9_PMSR916_SHIFT                (16u)
+#define GPIO_PMSR9_PMSR917_SHIFT                (17u)
+#define GPIO_PMSR9_PMSR918_SHIFT                (18u)
+#define GPIO_PMSR9_PMSR919_SHIFT                (19u)
+#define GPIO_PMSR9_PMSR920_SHIFT                (20u)
+#define GPIO_PMSR9_PMSR921_SHIFT                (21u)
+#define GPIO_PMSR9_PMSR922_SHIFT                (22u)
+#define GPIO_PMSR9_PMSR923_SHIFT                (23u)
+
+#define GPIO_PMCSR9_PMCSR90_SHIFT               (0u)
+#define GPIO_PMCSR9_PMCSR91_SHIFT               (1u)
+#define GPIO_PMCSR9_PMCSR92_SHIFT               (2u)
+#define GPIO_PMCSR9_PMCSR93_SHIFT               (3u)
+#define GPIO_PMCSR9_PMCSR94_SHIFT               (4u)
+#define GPIO_PMCSR9_PMCSR95_SHIFT               (5u)
+#define GPIO_PMCSR9_PMCSR96_SHIFT               (6u)
+#define GPIO_PMCSR9_PMCSR97_SHIFT               (7u)
+#define GPIO_PMCSR9_PMCSR916_SHIFT              (16u)
+#define GPIO_PMCSR9_PMCSR917_SHIFT              (17u)
+#define GPIO_PMCSR9_PMCSR918_SHIFT              (18u)
+#define GPIO_PMCSR9_PMCSR919_SHIFT              (19u)
+#define GPIO_PMCSR9_PMCSR920_SHIFT              (20u)
+#define GPIO_PMCSR9_PMCSR921_SHIFT              (21u)
+#define GPIO_PMCSR9_PMCSR922_SHIFT              (22u)
+#define GPIO_PMCSR9_PMCSR923_SHIFT              (23u)
+
+#define GPIO_PFCAE9_PFCAE90_SHIFT               (0u)
+#define GPIO_PFCAE9_PFCAE91_SHIFT               (1u)
+#define GPIO_PFCAE9_PFCAE92_SHIFT               (2u)
+#define GPIO_PFCAE9_PFCAE93_SHIFT               (3u)
+#define GPIO_PFCAE9_PFCAE94_SHIFT               (4u)
+#define GPIO_PFCAE9_PFCAE95_SHIFT               (5u)
+#define GPIO_PFCAE9_PFCAE96_SHIFT               (6u)
+#define GPIO_PFCAE9_PFCAE97_SHIFT               (7u)
+
+#define GPIO_PIBC9_PIBC90_SHIFT                 (0u)
+#define GPIO_PIBC9_PIBC91_SHIFT                 (1u)
+#define GPIO_PIBC9_PIBC92_SHIFT                 (2u)
+#define GPIO_PIBC9_PIBC93_SHIFT                 (3u)
+#define GPIO_PIBC9_PIBC94_SHIFT                 (4u)
+#define GPIO_PIBC9_PIBC95_SHIFT                 (5u)
+#define GPIO_PIBC9_PIBC96_SHIFT                 (6u)
+#define GPIO_PIBC9_PIBC97_SHIFT                 (7u)
+
+#define GPIO_PBDC9_PBDC90_SHIFT                 (0u)
+#define GPIO_PBDC9_PBDC91_SHIFT                 (1u)
+#define GPIO_PBDC9_PBDC92_SHIFT                 (2u)
+#define GPIO_PBDC9_PBDC93_SHIFT                 (3u)
+#define GPIO_PBDC9_PBDC94_SHIFT                 (4u)
+#define GPIO_PBDC9_PBDC95_SHIFT                 (5u)
+#define GPIO_PBDC9_PBDC96_SHIFT                 (6u)
+#define GPIO_PBDC9_PBDC97_SHIFT                 (7u)
+
+#define GPIO_PIPC9_PIPC90_SHIFT                 (0u)
+#define GPIO_PIPC9_PIPC91_SHIFT                 (1u)
+#define GPIO_PIPC9_PIPC92_SHIFT                 (2u)
+#define GPIO_PIPC9_PIPC93_SHIFT                 (3u)
+#define GPIO_PIPC9_PIPC94_SHIFT                 (4u)
+#define GPIO_PIPC9_PIPC95_SHIFT                 (5u)
+#define GPIO_PIPC9_PIPC96_SHIFT                 (6u)
+#define GPIO_PIPC9_PIPC97_SHIFT                 (7u)
+
+/* ---- P10 ---- */
+#define GPIO_P10_P100_SHIFT                     (0u)
+#define GPIO_P10_P101_SHIFT                     (1u)
+#define GPIO_P10_P102_SHIFT                     (2u)
+#define GPIO_P10_P103_SHIFT                     (3u)
+#define GPIO_P10_P104_SHIFT                     (4u)
+#define GPIO_P10_P105_SHIFT                     (5u)
+#define GPIO_P10_P106_SHIFT                     (6u)
+#define GPIO_P10_P107_SHIFT                     (7u)
+#define GPIO_P10_P108_SHIFT                     (8u)
+#define GPIO_P10_P109_SHIFT                     (9u)
+#define GPIO_P10_P1010_SHIFT                    (10u)
+#define GPIO_P10_P1011_SHIFT                    (11u)
+#define GPIO_P10_P1012_SHIFT                    (12u)
+#define GPIO_P10_P1013_SHIFT                    (13u)
+#define GPIO_P10_P1014_SHIFT                    (14u)
+#define GPIO_P10_P1015_SHIFT                    (15u)
+
+#define GPIO_PSR10_PSR100_SHIFT                 (0u)
+#define GPIO_PSR10_PSR101_SHIFT                 (1u)
+#define GPIO_PSR10_PSR102_SHIFT                 (2u)
+#define GPIO_PSR10_PSR103_SHIFT                 (3u)
+#define GPIO_PSR10_PSR104_SHIFT                 (4u)
+#define GPIO_PSR10_PSR105_SHIFT                 (5u)
+#define GPIO_PSR10_PSR106_SHIFT                 (6u)
+#define GPIO_PSR10_PSR107_SHIFT                 (7u)
+#define GPIO_PSR10_PSR108_SHIFT                 (8u)
+#define GPIO_PSR10_PSR109_SHIFT                 (9u)
+#define GPIO_PSR10_PSR1010_SHIFT                (10u)
+#define GPIO_PSR10_PSR1011_SHIFT                (11u)
+#define GPIO_PSR10_PSR1012_SHIFT                (12u)
+#define GPIO_PSR10_PSR1013_SHIFT                (13u)
+#define GPIO_PSR10_PSR1014_SHIFT                (14u)
+#define GPIO_PSR10_PSR1015_SHIFT                (15u)
+#define GPIO_PSR10_PSR1016_SHIFT                (16u)
+#define GPIO_PSR10_PSR1017_SHIFT                (17u)
+#define GPIO_PSR10_PSR1018_SHIFT                (18u)
+#define GPIO_PSR10_PSR1019_SHIFT                (19u)
+#define GPIO_PSR10_PSR1020_SHIFT                (20u)
+#define GPIO_PSR10_PSR1021_SHIFT                (21u)
+#define GPIO_PSR10_PSR1022_SHIFT                (22u)
+#define GPIO_PSR10_PSR1023_SHIFT                (23u)
+#define GPIO_PSR10_PSR1024_SHIFT                (24u)
+#define GPIO_PSR10_PSR1025_SHIFT                (25u)
+#define GPIO_PSR10_PSR1026_SHIFT                (26u)
+#define GPIO_PSR10_PSR1027_SHIFT                (27u)
+#define GPIO_PSR10_PSR1028_SHIFT                (28u)
+#define GPIO_PSR10_PSR1029_SHIFT                (29u)
+#define GPIO_PSR10_PSR1030_SHIFT                (30u)
+#define GPIO_PSR10_PSR1031_SHIFT                (31u)
+
+#define GPIO_PPR10_PPR100_SHIFT                 (0u)
+#define GPIO_PPR10_PPR101_SHIFT                 (1u)
+#define GPIO_PPR10_PPR102_SHIFT                 (2u)
+#define GPIO_PPR10_PPR103_SHIFT                 (3u)
+#define GPIO_PPR10_PPR104_SHIFT                 (4u)
+#define GPIO_PPR10_PPR105_SHIFT                 (5u)
+#define GPIO_PPR10_PPR106_SHIFT                 (6u)
+#define GPIO_PPR10_PPR107_SHIFT                 (7u)
+#define GPIO_PPR10_PPR108_SHIFT                 (8u)
+#define GPIO_PPR10_PPR109_SHIFT                 (9u)
+#define GPIO_PPR10_PPR1010_SHIFT                (10u)
+#define GPIO_PPR10_PPR1011_SHIFT                (11u)
+#define GPIO_PPR10_PPR1012_SHIFT                (12u)
+#define GPIO_PPR10_PPR1013_SHIFT                (13u)
+#define GPIO_PPR10_PPR1014_SHIFT                (14u)
+#define GPIO_PPR10_PPR1015_SHIFT                (15u)
+
+#define GPIO_PM10_PM100_SHIFT                   (0u)
+#define GPIO_PM10_PM101_SHIFT                   (1u)
+#define GPIO_PM10_PM102_SHIFT                   (2u)
+#define GPIO_PM10_PM103_SHIFT                   (3u)
+#define GPIO_PM10_PM104_SHIFT                   (4u)
+#define GPIO_PM10_PM105_SHIFT                   (5u)
+#define GPIO_PM10_PM106_SHIFT                   (6u)
+#define GPIO_PM10_PM107_SHIFT                   (7u)
+#define GPIO_PM10_PM108_SHIFT                   (8u)
+#define GPIO_PM10_PM109_SHIFT                   (9u)
+#define GPIO_PM10_PM1010_SHIFT                  (10u)
+#define GPIO_PM10_PM1011_SHIFT                  (11u)
+#define GPIO_PM10_PM1012_SHIFT                  (12u)
+#define GPIO_PM10_PM1013_SHIFT                  (13u)
+#define GPIO_PM10_PM1014_SHIFT                  (14u)
+#define GPIO_PM10_PM1015_SHIFT                  (15u)
+
+#define GPIO_PMC10_PMC100_SHIFT                 (0u)
+#define GPIO_PMC10_PMC101_SHIFT                 (1u)
+#define GPIO_PMC10_PMC102_SHIFT                 (2u)
+#define GPIO_PMC10_PMC103_SHIFT                 (3u)
+#define GPIO_PMC10_PMC104_SHIFT                 (4u)
+#define GPIO_PMC10_PMC105_SHIFT                 (5u)
+#define GPIO_PMC10_PMC106_SHIFT                 (6u)
+#define GPIO_PMC10_PMC107_SHIFT                 (7u)
+#define GPIO_PMC10_PMC108_SHIFT                 (8u)
+#define GPIO_PMC10_PMC109_SHIFT                 (9u)
+#define GPIO_PMC10_PMC1010_SHIFT                (10u)
+#define GPIO_PMC10_PMC1011_SHIFT                (11u)
+#define GPIO_PMC10_PMC1012_SHIFT                (12u)
+#define GPIO_PMC10_PMC1013_SHIFT                (13u)
+#define GPIO_PMC10_PMC1014_SHIFT                (14u)
+#define GPIO_PMC10_PMC1015_SHIFT                (15u)
+
+#define GPIO_PFC10_PFC100_SHIFT                 (0u)
+#define GPIO_PFC10_PFC101_SHIFT                 (1u)
+#define GPIO_PFC10_PFC102_SHIFT                 (2u)
+#define GPIO_PFC10_PFC103_SHIFT                 (3u)
+#define GPIO_PFC10_PFC104_SHIFT                 (4u)
+#define GPIO_PFC10_PFC105_SHIFT                 (5u)
+#define GPIO_PFC10_PFC106_SHIFT                 (6u)
+#define GPIO_PFC10_PFC107_SHIFT                 (7u)
+#define GPIO_PFC10_PFC108_SHIFT                 (8u)
+#define GPIO_PFC10_PFC109_SHIFT                 (9u)
+#define GPIO_PFC10_PFC1010_SHIFT                (10u)
+#define GPIO_PFC10_PFC1011_SHIFT                (11u)
+#define GPIO_PFC10_PFC1012_SHIFT                (12u)
+#define GPIO_PFC10_PFC1013_SHIFT                (13u)
+#define GPIO_PFC10_PFC1014_SHIFT                (14u)
+#define GPIO_PFC10_PFC1015_SHIFT                (15u)
+
+#define GPIO_PFCE10_PFCE100_SHIFT               (0u)
+#define GPIO_PFCE10_PFCE101_SHIFT               (1u)
+#define GPIO_PFCE10_PFCE102_SHIFT               (2u)
+#define GPIO_PFCE10_PFCE103_SHIFT               (3u)
+#define GPIO_PFCE10_PFCE104_SHIFT               (4u)
+#define GPIO_PFCE10_PFCE105_SHIFT               (5u)
+#define GPIO_PFCE10_PFCE106_SHIFT               (6u)
+#define GPIO_PFCE10_PFCE107_SHIFT               (7u)
+#define GPIO_PFCE10_PFCE108_SHIFT               (8u)
+#define GPIO_PFCE10_PFCE109_SHIFT               (9u)
+#define GPIO_PFCE10_PFCE1010_SHIFT              (10u)
+#define GPIO_PFCE10_PFCE1011_SHIFT              (11u)
+#define GPIO_PFCE10_PFCE1012_SHIFT              (12u)
+#define GPIO_PFCE10_PFCE1013_SHIFT              (13u)
+#define GPIO_PFCE10_PFCE1014_SHIFT              (14u)
+#define GPIO_PFCE10_PFCE1015_SHIFT              (15u)
+
+#define GPIO_PNOT10_PNOT100_SHIFT               (0u)
+#define GPIO_PNOT10_PNOT101_SHIFT               (1u)
+#define GPIO_PNOT10_PNOT102_SHIFT               (2u)
+#define GPIO_PNOT10_PNOT103_SHIFT               (3u)
+#define GPIO_PNOT10_PNOT104_SHIFT               (4u)
+#define GPIO_PNOT10_PNOT105_SHIFT               (5u)
+#define GPIO_PNOT10_PNOT106_SHIFT               (6u)
+#define GPIO_PNOT10_PNOT107_SHIFT               (7u)
+#define GPIO_PNOT10_PNOT108_SHIFT               (8u)
+#define GPIO_PNOT10_PNOT109_SHIFT               (9u)
+#define GPIO_PNOT10_PNOT1010_SHIFT              (10u)
+#define GPIO_PNOT10_PNOT1011_SHIFT              (11u)
+#define GPIO_PNOT10_PNOT1012_SHIFT              (12u)
+#define GPIO_PNOT10_PNOT1013_SHIFT              (13u)
+#define GPIO_PNOT10_PNOT1014_SHIFT              (14u)
+#define GPIO_PNOT10_PNOT1015_SHIFT              (15u)
+
+#define GPIO_PMSR10_PMSR100_SHIFT               (0u)
+#define GPIO_PMSR10_PMSR101_SHIFT               (1u)
+#define GPIO_PMSR10_PMSR102_SHIFT               (2u)
+#define GPIO_PMSR10_PMSR103_SHIFT               (3u)
+#define GPIO_PMSR10_PMSR104_SHIFT               (4u)
+#define GPIO_PMSR10_PMSR105_SHIFT               (5u)
+#define GPIO_PMSR10_PMSR106_SHIFT               (6u)
+#define GPIO_PMSR10_PMSR107_SHIFT               (7u)
+#define GPIO_PMSR10_PMSR108_SHIFT               (8u)
+#define GPIO_PMSR10_PMSR109_SHIFT               (9u)
+#define GPIO_PMSR10_PMSR1010_SHIFT              (10u)
+#define GPIO_PMSR10_PMSR1011_SHIFT              (11u)
+#define GPIO_PMSR10_PMSR1012_SHIFT              (12u)
+#define GPIO_PMSR10_PMSR1013_SHIFT              (13u)
+#define GPIO_PMSR10_PMSR1014_SHIFT              (14u)
+#define GPIO_PMSR10_PMSR1015_SHIFT              (15u)
+#define GPIO_PMSR10_PMSR1016_SHIFT              (16u)
+#define GPIO_PMSR10_PMSR1017_SHIFT              (17u)
+#define GPIO_PMSR10_PMSR1018_SHIFT              (18u)
+#define GPIO_PMSR10_PMSR1019_SHIFT              (19u)
+#define GPIO_PMSR10_PMSR1020_SHIFT              (20u)
+#define GPIO_PMSR10_PMSR1021_SHIFT              (21u)
+#define GPIO_PMSR10_PMSR1022_SHIFT              (22u)
+#define GPIO_PMSR10_PMSR1023_SHIFT              (23u)
+#define GPIO_PMSR10_PMSR1024_SHIFT              (24u)
+#define GPIO_PMSR10_PMSR1025_SHIFT              (25u)
+#define GPIO_PMSR10_PMSR1026_SHIFT              (26u)
+#define GPIO_PMSR10_PMSR1027_SHIFT              (27u)
+#define GPIO_PMSR10_PMSR1028_SHIFT              (28u)
+#define GPIO_PMSR10_PMSR1029_SHIFT              (29u)
+#define GPIO_PMSR10_PMSR1030_SHIFT              (30u)
+#define GPIO_PMSR10_PMSR1031_SHIFT              (31u)
+
+#define GPIO_PMCSR10_PMCSR100_SHIFT             (0u)
+#define GPIO_PMCSR10_PMCSR101_SHIFT             (1u)
+#define GPIO_PMCSR10_PMCSR102_SHIFT             (2u)
+#define GPIO_PMCSR10_PMCSR103_SHIFT             (3u)
+#define GPIO_PMCSR10_PMCSR104_SHIFT             (4u)
+#define GPIO_PMCSR10_PMCSR105_SHIFT             (5u)
+#define GPIO_PMCSR10_PMCSR106_SHIFT             (6u)
+#define GPIO_PMCSR10_PMCSR107_SHIFT             (7u)
+#define GPIO_PMCSR10_PMCSR108_SHIFT             (8u)
+#define GPIO_PMCSR10_PMCSR109_SHIFT             (9u)
+#define GPIO_PMCSR10_PMCSR1010_SHIFT            (10u)
+#define GPIO_PMCSR10_PMCSR1011_SHIFT            (11u)
+#define GPIO_PMCSR10_PMCSR1012_SHIFT            (12u)
+#define GPIO_PMCSR10_PMCSR1013_SHIFT            (13u)
+#define GPIO_PMCSR10_PMCSR1014_SHIFT            (14u)
+#define GPIO_PMCSR10_PMCSR1015_SHIFT            (15u)
+#define GPIO_PMCSR10_PMCSR1016_SHIFT            (16u)
+#define GPIO_PMCSR10_PMCSR1017_SHIFT            (17u)
+#define GPIO_PMCSR10_PMCSR1018_SHIFT            (18u)
+#define GPIO_PMCSR10_PMCSR1019_SHIFT            (19u)
+#define GPIO_PMCSR10_PMCSR1020_SHIFT            (20u)
+#define GPIO_PMCSR10_PMCSR1021_SHIFT            (21u)
+#define GPIO_PMCSR10_PMCSR1022_SHIFT            (22u)
+#define GPIO_PMCSR10_PMCSR1023_SHIFT            (23u)
+#define GPIO_PMCSR10_PMCSR1024_SHIFT            (24u)
+#define GPIO_PMCSR10_PMCSR1025_SHIFT            (25u)
+#define GPIO_PMCSR10_PMCSR1026_SHIFT            (26u)
+#define GPIO_PMCSR10_PMCSR1027_SHIFT            (27u)
+#define GPIO_PMCSR10_PMCSR1028_SHIFT            (28u)
+#define GPIO_PMCSR10_PMCSR1029_SHIFT            (29u)
+#define GPIO_PMCSR10_PMCSR1030_SHIFT            (30u)
+#define GPIO_PMCSR10_PMCSR1031_SHIFT            (31u)
+
+#define GPIO_PFCAE10_PFCAE100_SHIFT             (0u)
+#define GPIO_PFCAE10_PFCAE101_SHIFT             (1u)
+#define GPIO_PFCAE10_PFCAE102_SHIFT             (2u)
+#define GPIO_PFCAE10_PFCAE103_SHIFT             (3u)
+#define GPIO_PFCAE10_PFCAE104_SHIFT             (4u)
+#define GPIO_PFCAE10_PFCAE105_SHIFT             (5u)
+#define GPIO_PFCAE10_PFCAE106_SHIFT             (6u)
+#define GPIO_PFCAE10_PFCAE107_SHIFT             (7u)
+#define GPIO_PFCAE10_PFCAE108_SHIFT             (8u)
+#define GPIO_PFCAE10_PFCAE109_SHIFT             (9u)
+#define GPIO_PFCAE10_PFCAE1010_SHIFT            (10u)
+#define GPIO_PFCAE10_PFCAE1011_SHIFT            (11u)
+#define GPIO_PFCAE10_PFCAE1012_SHIFT            (12u)
+#define GPIO_PFCAE10_PFCAE1013_SHIFT            (13u)
+#define GPIO_PFCAE10_PFCAE1014_SHIFT            (14u)
+#define GPIO_PFCAE10_PFCAE1015_SHIFT            (15u)
+
+#define GPIO_PIBC10_PIBC100_SHIFT               (0u)
+#define GPIO_PIBC10_PIBC101_SHIFT               (1u)
+#define GPIO_PIBC10_PIBC102_SHIFT               (2u)
+#define GPIO_PIBC10_PIBC103_SHIFT               (3u)
+#define GPIO_PIBC10_PIBC104_SHIFT               (4u)
+#define GPIO_PIBC10_PIBC105_SHIFT               (5u)
+#define GPIO_PIBC10_PIBC106_SHIFT               (6u)
+#define GPIO_PIBC10_PIBC107_SHIFT               (7u)
+#define GPIO_PIBC10_PIBC108_SHIFT               (8u)
+#define GPIO_PIBC10_PIBC109_SHIFT               (9u)
+#define GPIO_PIBC10_PIBC1010_SHIFT              (10u)
+#define GPIO_PIBC10_PIBC1011_SHIFT              (11u)
+#define GPIO_PIBC10_PIBC1012_SHIFT              (12u)
+#define GPIO_PIBC10_PIBC1013_SHIFT              (13u)
+#define GPIO_PIBC10_PIBC1014_SHIFT              (14u)
+#define GPIO_PIBC10_PIBC1015_SHIFT              (15u)
+
+#define GPIO_PBDC10_PBDC100_SHIFT               (0u)
+#define GPIO_PBDC10_PBDC101_SHIFT               (1u)
+#define GPIO_PBDC10_PBDC102_SHIFT               (2u)
+#define GPIO_PBDC10_PBDC103_SHIFT               (3u)
+#define GPIO_PBDC10_PBDC104_SHIFT               (4u)
+#define GPIO_PBDC10_PBDC105_SHIFT               (5u)
+#define GPIO_PBDC10_PBDC106_SHIFT               (6u)
+#define GPIO_PBDC10_PBDC107_SHIFT               (7u)
+#define GPIO_PBDC10_PBDC108_SHIFT               (8u)
+#define GPIO_PBDC10_PBDC109_SHIFT               (9u)
+#define GPIO_PBDC10_PBDC1010_SHIFT              (10u)
+#define GPIO_PBDC10_PBDC1011_SHIFT              (11u)
+#define GPIO_PBDC10_PBDC1012_SHIFT              (12u)
+#define GPIO_PBDC10_PBDC1013_SHIFT              (13u)
+#define GPIO_PBDC10_PBDC1014_SHIFT              (14u)
+#define GPIO_PBDC10_PBDC1015_SHIFT              (15u)
+
+#define GPIO_PIPC10_PIPC100_SHIFT               (0u)
+#define GPIO_PIPC10_PIPC101_SHIFT               (1u)
+#define GPIO_PIPC10_PIPC102_SHIFT               (2u)
+#define GPIO_PIPC10_PIPC103_SHIFT               (3u)
+#define GPIO_PIPC10_PIPC104_SHIFT               (4u)
+#define GPIO_PIPC10_PIPC105_SHIFT               (5u)
+#define GPIO_PIPC10_PIPC106_SHIFT               (6u)
+#define GPIO_PIPC10_PIPC107_SHIFT               (7u)
+#define GPIO_PIPC10_PIPC108_SHIFT               (8u)
+#define GPIO_PIPC10_PIPC109_SHIFT               (9u)
+#define GPIO_PIPC10_PIPC1010_SHIFT              (10u)
+#define GPIO_PIPC10_PIPC1011_SHIFT              (11u)
+#define GPIO_PIPC10_PIPC1012_SHIFT              (12u)
+#define GPIO_PIPC10_PIPC1013_SHIFT              (13u)
+#define GPIO_PIPC10_PIPC1014_SHIFT              (14u)
+#define GPIO_PIPC10_PIPC1015_SHIFT              (15u)
+
+/* ---- P11 ---- */
+#define GPIO_P11_P110_SHIFT                     (0u)
+#define GPIO_P11_P111_SHIFT                     (1u)
+#define GPIO_P11_P112_SHIFT                     (2u)
+#define GPIO_P11_P113_SHIFT                     (3u)
+#define GPIO_P11_P114_SHIFT                     (4u)
+#define GPIO_P11_P115_SHIFT                     (5u)
+#define GPIO_P11_P116_SHIFT                     (6u)
+#define GPIO_P11_P117_SHIFT                     (7u)
+#define GPIO_P11_P118_SHIFT                     (8u)
+#define GPIO_P11_P119_SHIFT                     (9u)
+#define GPIO_P11_P1110_SHIFT                    (10u)
+#define GPIO_P11_P1111_SHIFT                    (11u)
+#define GPIO_P11_P1112_SHIFT                    (12u)
+#define GPIO_P11_P1113_SHIFT                    (13u)
+#define GPIO_P11_P1114_SHIFT                    (14u)
+#define GPIO_P11_P1115_SHIFT                    (15u)
+
+#define GPIO_PSR11_PSR110_SHIFT                 (0u)
+#define GPIO_PSR11_PSR111_SHIFT                 (1u)
+#define GPIO_PSR11_PSR112_SHIFT                 (2u)
+#define GPIO_PSR11_PSR113_SHIFT                 (3u)
+#define GPIO_PSR11_PSR114_SHIFT                 (4u)
+#define GPIO_PSR11_PSR115_SHIFT                 (5u)
+#define GPIO_PSR11_PSR116_SHIFT                 (6u)
+#define GPIO_PSR11_PSR117_SHIFT                 (7u)
+#define GPIO_PSR11_PSR118_SHIFT                 (8u)
+#define GPIO_PSR11_PSR119_SHIFT                 (9u)
+#define GPIO_PSR11_PSR1110_SHIFT                (10u)
+#define GPIO_PSR11_PSR1111_SHIFT                (11u)
+#define GPIO_PSR11_PSR1112_SHIFT                (12u)
+#define GPIO_PSR11_PSR1113_SHIFT                (13u)
+#define GPIO_PSR11_PSR1114_SHIFT                (14u)
+#define GPIO_PSR11_PSR1115_SHIFT                (15u)
+#define GPIO_PSR11_PSR1116_SHIFT                (16u)
+#define GPIO_PSR11_PSR1117_SHIFT                (17u)
+#define GPIO_PSR11_PSR1118_SHIFT                (18u)
+#define GPIO_PSR11_PSR1119_SHIFT                (19u)
+#define GPIO_PSR11_PSR1120_SHIFT                (20u)
+#define GPIO_PSR11_PSR1121_SHIFT                (21u)
+#define GPIO_PSR11_PSR1122_SHIFT                (22u)
+#define GPIO_PSR11_PSR1123_SHIFT                (23u)
+#define GPIO_PSR11_PSR1124_SHIFT                (24u)
+#define GPIO_PSR11_PSR1125_SHIFT                (25u)
+#define GPIO_PSR11_PSR1126_SHIFT                (26u)
+#define GPIO_PSR11_PSR1127_SHIFT                (27u)
+#define GPIO_PSR11_PSR1128_SHIFT                (28u)
+#define GPIO_PSR11_PSR1129_SHIFT                (29u)
+#define GPIO_PSR11_PSR1130_SHIFT                (30u)
+#define GPIO_PSR11_PSR1131_SHIFT                (31u)
+
+#define GPIO_PPR11_PPR110_SHIFT                 (0u)
+#define GPIO_PPR11_PPR111_SHIFT                 (1u)
+#define GPIO_PPR11_PPR112_SHIFT                 (2u)
+#define GPIO_PPR11_PPR113_SHIFT                 (3u)
+#define GPIO_PPR11_PPR114_SHIFT                 (4u)
+#define GPIO_PPR11_PPR115_SHIFT                 (5u)
+#define GPIO_PPR11_PPR116_SHIFT                 (6u)
+#define GPIO_PPR11_PPR117_SHIFT                 (7u)
+#define GPIO_PPR11_PPR118_SHIFT                 (8u)
+#define GPIO_PPR11_PPR119_SHIFT                 (9u)
+#define GPIO_PPR11_PPR1110_SHIFT                (10u)
+#define GPIO_PPR11_PPR1111_SHIFT                (11u)
+#define GPIO_PPR11_PPR1112_SHIFT                (12u)
+#define GPIO_PPR11_PPR1113_SHIFT                (13u)
+#define GPIO_PPR11_PPR1114_SHIFT                (14u)
+#define GPIO_PPR11_PPR1115_SHIFT                (15u)
+
+#define GPIO_PM11_PM110_SHIFT                   (0u)
+#define GPIO_PM11_PM111_SHIFT                   (1u)
+#define GPIO_PM11_PM112_SHIFT                   (2u)
+#define GPIO_PM11_PM113_SHIFT                   (3u)
+#define GPIO_PM11_PM114_SHIFT                   (4u)
+#define GPIO_PM11_PM115_SHIFT                   (5u)
+#define GPIO_PM11_PM116_SHIFT                   (6u)
+#define GPIO_PM11_PM117_SHIFT                   (7u)
+#define GPIO_PM11_PM118_SHIFT                   (8u)
+#define GPIO_PM11_PM119_SHIFT                   (9u)
+#define GPIO_PM11_PM1110_SHIFT                  (10u)
+#define GPIO_PM11_PM1111_SHIFT                  (11u)
+#define GPIO_PM11_PM1112_SHIFT                  (12u)
+#define GPIO_PM11_PM1113_SHIFT                  (13u)
+#define GPIO_PM11_PM1114_SHIFT                  (14u)
+#define GPIO_PM11_PM1115_SHIFT                  (15u)
+
+#define GPIO_PMC11_PMC110_SHIFT                 (0u)
+#define GPIO_PMC11_PMC111_SHIFT                 (1u)
+#define GPIO_PMC11_PMC112_SHIFT                 (2u)
+#define GPIO_PMC11_PMC113_SHIFT                 (3u)
+#define GPIO_PMC11_PMC114_SHIFT                 (4u)
+#define GPIO_PMC11_PMC115_SHIFT                 (5u)
+#define GPIO_PMC11_PMC116_SHIFT                 (6u)
+#define GPIO_PMC11_PMC117_SHIFT                 (7u)
+#define GPIO_PMC11_PMC118_SHIFT                 (8u)
+#define GPIO_PMC11_PMC119_SHIFT                 (9u)
+#define GPIO_PMC11_PMC1110_SHIFT                (10u)
+#define GPIO_PMC11_PMC1111_SHIFT                (11u)
+#define GPIO_PMC11_PMC1112_SHIFT                (12u)
+#define GPIO_PMC11_PMC1113_SHIFT                (13u)
+#define GPIO_PMC11_PMC1114_SHIFT                (14u)
+#define GPIO_PMC11_PMC1115_SHIFT                (15u)
+
+#define GPIO_PFC11_PFC110_SHIFT                 (0u)
+#define GPIO_PFC11_PFC111_SHIFT                 (1u)
+#define GPIO_PFC11_PFC112_SHIFT                 (2u)
+#define GPIO_PFC11_PFC113_SHIFT                 (3u)
+#define GPIO_PFC11_PFC114_SHIFT                 (4u)
+#define GPIO_PFC11_PFC115_SHIFT                 (5u)
+#define GPIO_PFC11_PFC116_SHIFT                 (6u)
+#define GPIO_PFC11_PFC117_SHIFT                 (7u)
+#define GPIO_PFC11_PFC118_SHIFT                 (8u)
+#define GPIO_PFC11_PFC119_SHIFT                 (9u)
+#define GPIO_PFC11_PFC1110_SHIFT                (10u)
+#define GPIO_PFC11_PFC1111_SHIFT                (11u)
+#define GPIO_PFC11_PFC1112_SHIFT                (12u)
+#define GPIO_PFC11_PFC1113_SHIFT                (13u)
+#define GPIO_PFC11_PFC1114_SHIFT                (14u)
+#define GPIO_PFC11_PFC1115_SHIFT                (15u)
+
+#define GPIO_PFCE11_PFCE110_SHIFT               (0u)
+#define GPIO_PFCE11_PFCE111_SHIFT               (1u)
+#define GPIO_PFCE11_PFCE112_SHIFT               (2u)
+#define GPIO_PFCE11_PFCE113_SHIFT               (3u)
+#define GPIO_PFCE11_PFCE114_SHIFT               (4u)
+#define GPIO_PFCE11_PFCE115_SHIFT               (5u)
+#define GPIO_PFCE11_PFCE116_SHIFT               (6u)
+#define GPIO_PFCE11_PFCE117_SHIFT               (7u)
+#define GPIO_PFCE11_PFCE118_SHIFT               (8u)
+#define GPIO_PFCE11_PFCE119_SHIFT               (9u)
+#define GPIO_PFCE11_PFCE1110_SHIFT              (10u)
+#define GPIO_PFCE11_PFCE1111_SHIFT              (11u)
+#define GPIO_PFCE11_PFCE1112_SHIFT              (12u)
+#define GPIO_PFCE11_PFCE1113_SHIFT              (13u)
+#define GPIO_PFCE11_PFCE1114_SHIFT              (14u)
+#define GPIO_PFCE11_PFCE1115_SHIFT              (15u)
+
+#define GPIO_PNOT11_PNOT110_SHIFT               (0u)
+#define GPIO_PNOT11_PNOT111_SHIFT               (1u)
+#define GPIO_PNOT11_PNOT112_SHIFT               (2u)
+#define GPIO_PNOT11_PNOT113_SHIFT               (3u)
+#define GPIO_PNOT11_PNOT114_SHIFT               (4u)
+#define GPIO_PNOT11_PNOT115_SHIFT               (5u)
+#define GPIO_PNOT11_PNOT116_SHIFT               (6u)
+#define GPIO_PNOT11_PNOT117_SHIFT               (7u)
+#define GPIO_PNOT11_PNOT118_SHIFT               (8u)
+#define GPIO_PNOT11_PNOT119_SHIFT               (9u)
+#define GPIO_PNOT11_PNOT1110_SHIFT              (10u)
+#define GPIO_PNOT11_PNOT1111_SHIFT              (11u)
+#define GPIO_PNOT11_PNOT1112_SHIFT              (12u)
+#define GPIO_PNOT11_PNOT1113_SHIFT              (13u)
+#define GPIO_PNOT11_PNOT1114_SHIFT              (14u)
+#define GPIO_PNOT11_PNOT1115_SHIFT              (15u)
+
+#define GPIO_PMSR11_PMSR110_SHIFT               (0u)
+#define GPIO_PMSR11_PMSR111_SHIFT               (1u)
+#define GPIO_PMSR11_PMSR112_SHIFT               (2u)
+#define GPIO_PMSR11_PMSR113_SHIFT               (3u)
+#define GPIO_PMSR11_PMSR114_SHIFT               (4u)
+#define GPIO_PMSR11_PMSR115_SHIFT               (5u)
+#define GPIO_PMSR11_PMSR116_SHIFT               (6u)
+#define GPIO_PMSR11_PMSR117_SHIFT               (7u)
+#define GPIO_PMSR11_PMSR118_SHIFT               (8u)
+#define GPIO_PMSR11_PMSR119_SHIFT               (9u)
+#define GPIO_PMSR11_PMSR1110_SHIFT              (10u)
+#define GPIO_PMSR11_PMSR1111_SHIFT              (11u)
+#define GPIO_PMSR11_PMSR1112_SHIFT              (12u)
+#define GPIO_PMSR11_PMSR1113_SHIFT              (13u)
+#define GPIO_PMSR11_PMSR1114_SHIFT              (14u)
+#define GPIO_PMSR11_PMSR1115_SHIFT              (15u)
+#define GPIO_PMSR11_PMSR1116_SHIFT              (16u)
+#define GPIO_PMSR11_PMSR1117_SHIFT              (17u)
+#define GPIO_PMSR11_PMSR1118_SHIFT              (18u)
+#define GPIO_PMSR11_PMSR1119_SHIFT              (19u)
+#define GPIO_PMSR11_PMSR1120_SHIFT              (20u)
+#define GPIO_PMSR11_PMSR1121_SHIFT              (21u)
+#define GPIO_PMSR11_PMSR1122_SHIFT              (22u)
+#define GPIO_PMSR11_PMSR1123_SHIFT              (23u)
+#define GPIO_PMSR11_PMSR1124_SHIFT              (24u)
+#define GPIO_PMSR11_PMSR1125_SHIFT              (25u)
+#define GPIO_PMSR11_PMSR1126_SHIFT              (26u)
+#define GPIO_PMSR11_PMSR1127_SHIFT              (27u)
+#define GPIO_PMSR11_PMSR1128_SHIFT              (28u)
+#define GPIO_PMSR11_PMSR1129_SHIFT              (29u)
+#define GPIO_PMSR11_PMSR1130_SHIFT              (30u)
+#define GPIO_PMSR11_PMSR1131_SHIFT              (31u)
+
+#define GPIO_PMCSR11_PMCSR110_SHIFT             (0u)
+#define GPIO_PMCSR11_PMCSR111_SHIFT             (1u)
+#define GPIO_PMCSR11_PMCSR112_SHIFT             (2u)
+#define GPIO_PMCSR11_PMCSR113_SHIFT             (3u)
+#define GPIO_PMCSR11_PMCSR114_SHIFT             (4u)
+#define GPIO_PMCSR11_PMCSR115_SHIFT             (5u)
+#define GPIO_PMCSR11_PMCSR116_SHIFT             (6u)
+#define GPIO_PMCSR11_PMCSR117_SHIFT             (7u)
+#define GPIO_PMCSR11_PMCSR118_SHIFT             (8u)
+#define GPIO_PMCSR11_PMCSR119_SHIFT             (9u)
+#define GPIO_PMCSR11_PMCSR1110_SHIFT            (10u)
+#define GPIO_PMCSR11_PMCSR1111_SHIFT            (11u)
+#define GPIO_PMCSR11_PMCSR1112_SHIFT            (12u)
+#define GPIO_PMCSR11_PMCSR1113_SHIFT            (13u)
+#define GPIO_PMCSR11_PMCSR1114_SHIFT            (14u)
+#define GPIO_PMCSR11_PMCSR1115_SHIFT            (15u)
+#define GPIO_PMCSR11_PMCSR1116_SHIFT            (16u)
+#define GPIO_PMCSR11_PMCSR1117_SHIFT            (17u)
+#define GPIO_PMCSR11_PMCSR1118_SHIFT            (18u)
+#define GPIO_PMCSR11_PMCSR1119_SHIFT            (19u)
+#define GPIO_PMCSR11_PMCSR1120_SHIFT            (20u)
+#define GPIO_PMCSR11_PMCSR1121_SHIFT            (21u)
+#define GPIO_PMCSR11_PMCSR1122_SHIFT            (22u)
+#define GPIO_PMCSR11_PMCSR1123_SHIFT            (23u)
+#define GPIO_PMCSR11_PMCSR1124_SHIFT            (24u)
+#define GPIO_PMCSR11_PMCSR1125_SHIFT            (25u)
+#define GPIO_PMCSR11_PMCSR1126_SHIFT            (26u)
+#define GPIO_PMCSR11_PMCSR1127_SHIFT            (27u)
+#define GPIO_PMCSR11_PMCSR1128_SHIFT            (28u)
+#define GPIO_PMCSR11_PMCSR1129_SHIFT            (29u)
+#define GPIO_PMCSR11_PMCSR1130_SHIFT            (30u)
+#define GPIO_PMCSR11_PMCSR1131_SHIFT            (31u)
+
+#define GPIO_PFCAE11_PFCAE110_SHIFT             (0u)
+#define GPIO_PFCAE11_PFCAE111_SHIFT             (1u)
+#define GPIO_PFCAE11_PFCAE112_SHIFT             (2u)
+#define GPIO_PFCAE11_PFCAE113_SHIFT             (3u)
+#define GPIO_PFCAE11_PFCAE114_SHIFT             (4u)
+#define GPIO_PFCAE11_PFCAE115_SHIFT             (5u)
+#define GPIO_PFCAE11_PFCAE116_SHIFT             (6u)
+#define GPIO_PFCAE11_PFCAE117_SHIFT             (7u)
+#define GPIO_PFCAE11_PFCAE118_SHIFT             (8u)
+#define GPIO_PFCAE11_PFCAE119_SHIFT             (9u)
+#define GPIO_PFCAE11_PFCAE1110_SHIFT            (10u)
+#define GPIO_PFCAE11_PFCAE1111_SHIFT            (11u)
+#define GPIO_PFCAE11_PFCAE1112_SHIFT            (12u)
+#define GPIO_PFCAE11_PFCAE1113_SHIFT            (13u)
+#define GPIO_PFCAE11_PFCAE1114_SHIFT            (14u)
+#define GPIO_PFCAE11_PFCAE1115_SHIFT            (15u)
+
+#define GPIO_PIBC11_PIBC110_SHIFT               (0u)
+#define GPIO_PIBC11_PIBC111_SHIFT               (1u)
+#define GPIO_PIBC11_PIBC112_SHIFT               (2u)
+#define GPIO_PIBC11_PIBC113_SHIFT               (3u)
+#define GPIO_PIBC11_PIBC114_SHIFT               (4u)
+#define GPIO_PIBC11_PIBC115_SHIFT               (5u)
+#define GPIO_PIBC11_PIBC116_SHIFT               (6u)
+#define GPIO_PIBC11_PIBC117_SHIFT               (7u)
+#define GPIO_PIBC11_PIBC118_SHIFT               (8u)
+#define GPIO_PIBC11_PIBC119_SHIFT               (9u)
+#define GPIO_PIBC11_PIBC1110_SHIFT              (10u)
+#define GPIO_PIBC11_PIBC1111_SHIFT              (11u)
+#define GPIO_PIBC11_PIBC1112_SHIFT              (12u)
+#define GPIO_PIBC11_PIBC1113_SHIFT              (13u)
+#define GPIO_PIBC11_PIBC1114_SHIFT              (14u)
+#define GPIO_PIBC11_PIBC1115_SHIFT              (15u)
+
+#define GPIO_PBDC11_PBDC110_SHIFT               (0u)
+#define GPIO_PBDC11_PBDC111_SHIFT               (1u)
+#define GPIO_PBDC11_PBDC112_SHIFT               (2u)
+#define GPIO_PBDC11_PBDC113_SHIFT               (3u)
+#define GPIO_PBDC11_PBDC114_SHIFT               (4u)
+#define GPIO_PBDC11_PBDC115_SHIFT               (5u)
+#define GPIO_PBDC11_PBDC116_SHIFT               (6u)
+#define GPIO_PBDC11_PBDC117_SHIFT               (7u)
+#define GPIO_PBDC11_PBDC118_SHIFT               (8u)
+#define GPIO_PBDC11_PBDC119_SHIFT               (9u)
+#define GPIO_PBDC11_PBDC1110_SHIFT              (10u)
+#define GPIO_PBDC11_PBDC1111_SHIFT              (11u)
+#define GPIO_PBDC11_PBDC1112_SHIFT              (12u)
+#define GPIO_PBDC11_PBDC1113_SHIFT              (13u)
+#define GPIO_PBDC11_PBDC1114_SHIFT              (14u)
+#define GPIO_PBDC11_PBDC1115_SHIFT              (15u)
+
+#define GPIO_PIPC11_PIPC110_SHIFT               (0u)
+#define GPIO_PIPC11_PIPC111_SHIFT               (1u)
+#define GPIO_PIPC11_PIPC112_SHIFT               (2u)
+#define GPIO_PIPC11_PIPC113_SHIFT               (3u)
+#define GPIO_PIPC11_PIPC114_SHIFT               (4u)
+#define GPIO_PIPC11_PIPC115_SHIFT               (5u)
+#define GPIO_PIPC11_PIPC116_SHIFT               (6u)
+#define GPIO_PIPC11_PIPC117_SHIFT               (7u)
+#define GPIO_PIPC11_PIPC118_SHIFT               (8u)
+#define GPIO_PIPC11_PIPC119_SHIFT               (9u)
+#define GPIO_PIPC11_PIPC1110_SHIFT              (10u)
+#define GPIO_PIPC11_PIPC1111_SHIFT              (11u)
+#define GPIO_PIPC11_PIPC1112_SHIFT              (12u)
+#define GPIO_PIPC11_PIPC1113_SHIFT              (13u)
+#define GPIO_PIPC11_PIPC1114_SHIFT              (14u)
+#define GPIO_PIPC11_PIPC1115_SHIFT              (15u)
+
+
+#endif /* GPIO_IOBITMASK_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/intc_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,11237 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : intc_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : INTC register define header
+*******************************************************************************/
+#ifndef INTC_IOBITMASK_H
+#define INTC_IOBITMASK_H
+
+/* ==== Mask values for IO registers ==== */
+#define INTC_ICDDCR_Enable                      (0x00000001uL)
+
+#define INTC_ICDICTR_ITLinesNumber              (0x0000001FuL)
+#define INTC_ICDICTR_CPUNumber                  (0x000000E0uL)
+#define INTC_ICDICTR_SecurityExtn               (0x00000400uL)
+#define INTC_ICDICTR_LSPI                       (0x0000F800uL)
+
+#define INTC_ICDIIDR_Implementer                (0x00000FFFuL)
+#define INTC_ICDIIDR_Revision                   (0x0000F000uL)
+#define INTC_ICDIIDR_Variant                    (0x000F0000uL)
+#define INTC_ICDIIDR_ProductID                  (0xFF000000uL)
+
+#define INTC_ICDISR0_SW0                        (0x00000001uL)
+#define INTC_ICDISR0_SW1                        (0x00000002uL)
+#define INTC_ICDISR0_SW2                        (0x00000004uL)
+#define INTC_ICDISR0_SW3                        (0x00000008uL)
+#define INTC_ICDISR0_SW4                        (0x00000010uL)
+#define INTC_ICDISR0_SW5                        (0x00000020uL)
+#define INTC_ICDISR0_SW6                        (0x00000040uL)
+#define INTC_ICDISR0_SW7                        (0x00000080uL)
+#define INTC_ICDISR0_SW8                        (0x00000100uL)
+#define INTC_ICDISR0_SW9                        (0x00000200uL)
+#define INTC_ICDISR0_SW10                       (0x00000400uL)
+#define INTC_ICDISR0_SW11                       (0x00000800uL)
+#define INTC_ICDISR0_SW12                       (0x00001000uL)
+#define INTC_ICDISR0_SW13                       (0x00002000uL)
+#define INTC_ICDISR0_SW14                       (0x00004000uL)
+#define INTC_ICDISR0_SW15                       (0x00008000uL)
+#define INTC_ICDISR0_PMUIRQ0                    (0x00010000uL)
+#define INTC_ICDISR0_COMMRX0                    (0x00020000uL)
+#define INTC_ICDISR0_COMMTX0                    (0x00040000uL)
+#define INTC_ICDISR0_CTIIRQ0                    (0x00080000uL)
+
+#define INTC_ICDISR1_IRQ0                       (0x00000001uL)
+#define INTC_ICDISR1_IRQ1                       (0x00000002uL)
+#define INTC_ICDISR1_IRQ2                       (0x00000004uL)
+#define INTC_ICDISR1_IRQ3                       (0x00000008uL)
+#define INTC_ICDISR1_IRQ4                       (0x00000010uL)
+#define INTC_ICDISR1_IRQ5                       (0x00000020uL)
+#define INTC_ICDISR1_IRQ6                       (0x00000040uL)
+#define INTC_ICDISR1_IRQ7                       (0x00000080uL)
+#define INTC_ICDISR1_PL310ERR                   (0x00000100uL)
+#define INTC_ICDISR1_DMAINT0                    (0x00000200uL)
+#define INTC_ICDISR1_DMAINT1                    (0x00000400uL)
+#define INTC_ICDISR1_DMAINT2                    (0x00000800uL)
+#define INTC_ICDISR1_DMAINT3                    (0x00001000uL)
+#define INTC_ICDISR1_DMAINT4                    (0x00002000uL)
+#define INTC_ICDISR1_DMAINT5                    (0x00004000uL)
+#define INTC_ICDISR1_DMAINT6                    (0x00008000uL)
+#define INTC_ICDISR1_DMAINT7                    (0x00010000uL)
+#define INTC_ICDISR1_DMAINT8                    (0x00020000uL)
+#define INTC_ICDISR1_DMAINT9                    (0x00040000uL)
+#define INTC_ICDISR1_DMAINT10                   (0x00080000uL)
+#define INTC_ICDISR1_DMAINT11                   (0x00100000uL)
+#define INTC_ICDISR1_DMAINT12                   (0x00200000uL)
+#define INTC_ICDISR1_DMAINT13                   (0x00400000uL)
+#define INTC_ICDISR1_DMAINT14                   (0x00800000uL)
+#define INTC_ICDISR1_DMAINT15                   (0x01000000uL)
+#define INTC_ICDISR1_DMAERR                     (0x02000000uL)
+
+#define INTC_ICDISR2_USBI0                      (0x00000200uL)
+#define INTC_ICDISR2_USBI1                      (0x00000400uL)
+#define INTC_ICDISR2_S0_VI_VSYNC0               (0x00000800uL)
+#define INTC_ICDISR2_S0_LO_VSYNC0               (0x00001000uL)
+#define INTC_ICDISR2_S0_VSYNCERR0               (0x00002000uL)
+#define INTC_ICDISR2_GR3_VLINE0                 (0x00004000uL)
+#define INTC_ICDISR2_S0_VFIELD0                 (0x00008000uL)
+#define INTC_ICDISR2_IV1_VBUFERR0               (0x00010000uL)
+#define INTC_ICDISR2_IV3_VBUFERR0               (0x00020000uL)
+#define INTC_ICDISR2_IV5_VBUFERR0               (0x00040000uL)
+#define INTC_ICDISR2_IV6_VBUFERR0               (0x00080000uL)
+#define INTC_ICDISR2_S0_WLINE0                  (0x00100000uL)
+#define INTC_ICDISR2_S1_VI_VSYNC0               (0x00200000uL)
+#define INTC_ICDISR2_S1_LO_VSYNC0               (0x00400000uL)
+#define INTC_ICDISR2_S1_VSYNCERR0               (0x00800000uL)
+#define INTC_ICDISR2_S1_VFIELD0                 (0x01000000uL)
+#define INTC_ICDISR2_IV2_VBUFERR0               (0x02000000uL)
+#define INTC_ICDISR2_IV4_VBUFERR0               (0x04000000uL)
+#define INTC_ICDISR2_S1_WLINE0                  (0x08000000uL)
+#define INTC_ICDISR2_OIR_VI_VSYNC0              (0x10000000uL)
+#define INTC_ICDISR2_OIR_LO_VSYNC0              (0x20000000uL)
+#define INTC_ICDISR2_OIR_VSYNCERR0              (0x40000000uL)
+#define INTC_ICDISR2_OIR_VFIELD0                (0x80000000uL)
+
+#define INTC_ICDISR3_IV7_VBUFERR0               (0x00000001uL)
+#define INTC_ICDISR3_IV8_VBUFERR0               (0x00000002uL)
+#define INTC_ICDISR3_S0_VI_VSYNC1               (0x00000008uL)
+#define INTC_ICDISR3_S0_LO_VSYNC1               (0x00000010uL)
+#define INTC_ICDISR3_S0_VSYNCERR1               (0x00000020uL)
+#define INTC_ICDISR3_GR3_VLINE1                 (0x00000040uL)
+#define INTC_ICDISR3_S0_VFIELD1                 (0x00000080uL)
+#define INTC_ICDISR3_IV1_VBUFERR1               (0x00000100uL)
+#define INTC_ICDISR3_IV3_VBUFERR1               (0x00000200uL)
+#define INTC_ICDISR3_IV5_VBUFERR1               (0x00000400uL)
+#define INTC_ICDISR3_IV6_VBUFERR1               (0x00000800uL)
+#define INTC_ICDISR3_S0_WLINE1                  (0x00001000uL)
+#define INTC_ICDISR3_S1_VI_VSYNC1               (0x00002000uL)
+#define INTC_ICDISR3_S1_LO_VSYNC1               (0x00004000uL)
+#define INTC_ICDISR3_S1_VSYNCERR1               (0x00008000uL)
+#define INTC_ICDISR3_S1_VFIELD1                 (0x00010000uL)
+#define INTC_ICDISR3_IV2_VBUFERR1               (0x00020000uL)
+#define INTC_ICDISR3_IV4_VBUFERR1               (0x00040000uL)
+#define INTC_ICDISR3_S1_WLINE1                  (0x00080000uL)
+#define INTC_ICDISR3_OIR_VI_VSYNC1              (0x00100000uL)
+#define INTC_ICDISR3_OIR_LO_VSYNC1              (0x00200000uL)
+#define INTC_ICDISR3_OIR_VLINE1                 (0x00400000uL)
+#define INTC_ICDISR3_OIR_VFIELD1                (0x00800000uL)
+#define INTC_ICDISR3_IV7_VBUFERR1               (0x01000000uL)
+#define INTC_ICDISR3_IV8_VBUFERR1               (0x02000000uL)
+#define INTC_ICDISR3_IMRDI                      (0x08000000uL)
+#define INTC_ICDISR3_IMR2I0                     (0x10000000uL)
+#define INTC_ICDISR3_IMR2I1                     (0x20000000uL)
+#define INTC_ICDISR3_JEDI                       (0x40000000uL)
+#define INTC_ICDISR3_JDTI                       (0x80000000uL)
+
+#define INTC_ICDISR4_CMP0                       (0x00000001uL)
+#define INTC_ICDISR4_CMP1                       (0x00000002uL)
+#define INTC_ICDISR4_INT0                       (0x00000004uL)
+#define INTC_ICDISR4_INT1                       (0x00000008uL)
+#define INTC_ICDISR4_INT2                       (0x00000010uL)
+#define INTC_ICDISR4_INT3                       (0x00000020uL)
+#define INTC_ICDISR4_OSTM0TINT                  (0x00000040uL)
+#define INTC_ICDISR4_OSTM1TINT                  (0x00000080uL)
+#define INTC_ICDISR4_CMI                        (0x00000100uL)
+#define INTC_ICDISR4_WTOUT                      (0x00000200uL)
+#define INTC_ICDISR4_ITI                        (0x00000400uL)
+#define INTC_ICDISR4_TGI0A                      (0x00000800uL)
+#define INTC_ICDISR4_TGI0B                      (0x00001000uL)
+#define INTC_ICDISR4_TGI0C                      (0x00002000uL)
+#define INTC_ICDISR4_TGI0D                      (0x00004000uL)
+#define INTC_ICDISR4_TGI0V                      (0x00008000uL)
+#define INTC_ICDISR4_TGI0E                      (0x00010000uL)
+#define INTC_ICDISR4_TGI0F                      (0x00020000uL)
+#define INTC_ICDISR4_TGI1A                      (0x00040000uL)
+#define INTC_ICDISR4_TGI1B                      (0x00080000uL)
+#define INTC_ICDISR4_TGI1V                      (0x00100000uL)
+#define INTC_ICDISR4_TGI1U                      (0x00200000uL)
+#define INTC_ICDISR4_TGI2A                      (0x00400000uL)
+#define INTC_ICDISR4_TGI2B                      (0x00800000uL)
+#define INTC_ICDISR4_TGI2V                      (0x01000000uL)
+#define INTC_ICDISR4_TGI2U                      (0x02000000uL)
+#define INTC_ICDISR4_TGI3A                      (0x04000000uL)
+#define INTC_ICDISR4_TGI3B                      (0x08000000uL)
+#define INTC_ICDISR4_TGI3C                      (0x10000000uL)
+#define INTC_ICDISR4_TGI3D                      (0x20000000uL)
+#define INTC_ICDISR4_TGI3V                      (0x40000000uL)
+#define INTC_ICDISR4_TGI4A                      (0x80000000uL)
+
+#define INTC_ICDISR5_TGI4B                      (0x00000001uL)
+#define INTC_ICDISR5_TGI4C                      (0x00000002uL)
+#define INTC_ICDISR5_TGI4D                      (0x00000004uL)
+#define INTC_ICDISR5_TGI4V                      (0x00000008uL)
+#define INTC_ICDISR5_CMI1                       (0x00000010uL)
+#define INTC_ICDISR5_CMI2                       (0x00000020uL)
+#define INTC_ICDISR5_SGDEI0                     (0x00000040uL)
+#define INTC_ICDISR5_SGDEI1                     (0x00000080uL)
+#define INTC_ICDISR5_SGDEI2                     (0x00000100uL)
+#define INTC_ICDISR5_SGDEI3                     (0x00000200uL)
+#define INTC_ICDISR5_ADI                        (0x00000400uL)
+#define INTC_ICDISR5_LMTI                       (0x00000800uL)
+#define INTC_ICDISR5_SSII0                      (0x00001000uL)
+#define INTC_ICDISR5_SSIRXI0                    (0x00002000uL)
+#define INTC_ICDISR5_SSITXI0                    (0x00004000uL)
+#define INTC_ICDISR5_SSII1                      (0x00008000uL)
+#define INTC_ICDISR5_SSIRXI1                    (0x00010000uL)
+#define INTC_ICDISR5_SSITXI1                    (0x00020000uL)
+#define INTC_ICDISR5_SSII2                      (0x00040000uL)
+#define INTC_ICDISR5_SSIRTI2                    (0x00080000uL)
+#define INTC_ICDISR5_SSII3                      (0x00100000uL)
+#define INTC_ICDISR5_SSIRXI3                    (0x00200000uL)
+#define INTC_ICDISR5_SSITXI3                    (0x00400000uL)
+#define INTC_ICDISR5_SSII4                      (0x00800000uL)
+#define INTC_ICDISR5_SSIRTI4                    (0x01000000uL)
+#define INTC_ICDISR5_SSII5                      (0x02000000uL)
+#define INTC_ICDISR5_SSIRXI5                    (0x04000000uL)
+#define INTC_ICDISR5_SSITXI5                    (0x08000000uL)
+#define INTC_ICDISR5_SPDIFI                     (0x10000000uL)
+#define INTC_ICDISR5_INTIICTEI0                 (0x20000000uL)
+#define INTC_ICDISR5_INTIICRI0                  (0x40000000uL)
+#define INTC_ICDISR5_INTIICTI0                  (0x80000000uL)
+
+#define INTC_ICDISR6_INTIICSPI0                 (0x00000001uL)
+#define INTC_ICDISR6_INTIICSTI0                 (0x00000002uL)
+#define INTC_ICDISR6_INTIICNAKI0                (0x00000004uL)
+#define INTC_ICDISR6_INTIICALI0                 (0x00000008uL)
+#define INTC_ICDISR6_INTIICTMOI0                (0x00000010uL)
+#define INTC_ICDISR6_INTIICTEI1                 (0x00000020uL)
+#define INTC_ICDISR6_INTIICRI1                  (0x00000040uL)
+#define INTC_ICDISR6_INTIICTI1                  (0x00000080uL)
+#define INTC_ICDISR6_INTIICSPI1                 (0x00000100uL)
+#define INTC_ICDISR6_INTIICSTI1                 (0x00000200uL)
+#define INTC_ICDISR6_INTIICNAKI1                (0x00000400uL)
+#define INTC_ICDISR6_INTIICALI1                 (0x00000800uL)
+#define INTC_ICDISR6_INTIICTMOI1                (0x00001000uL)
+#define INTC_ICDISR6_INTIICTEI2                 (0x00002000uL)
+#define INTC_ICDISR6_INTIICRI2                  (0x00004000uL)
+#define INTC_ICDISR6_INTIICTI2                  (0x00008000uL)
+#define INTC_ICDISR6_INTIICSPI2                 (0x00010000uL)
+#define INTC_ICDISR6_INTIICSTI2                 (0x00020000uL)
+#define INTC_ICDISR6_INTIICNAKI2                (0x00040000uL)
+#define INTC_ICDISR6_INTIICALI2                 (0x00080000uL)
+#define INTC_ICDISR6_INTIICTMOI2                (0x00100000uL)
+#define INTC_ICDISR6_INTIICTEI3                 (0x00200000uL)
+#define INTC_ICDISR6_INTIICRI3                  (0x00400000uL)
+#define INTC_ICDISR6_INTIICTI3                  (0x00800000uL)
+#define INTC_ICDISR6_INTIICSPI3                 (0x01000000uL)
+#define INTC_ICDISR6_INTIICSTI3                 (0x02000000uL)
+#define INTC_ICDISR6_INTIICNAKI3                (0x04000000uL)
+#define INTC_ICDISR6_INTIICALI3                 (0x08000000uL)
+#define INTC_ICDISR6_INTIICTMOI3                (0x10000000uL)
+#define INTC_ICDISR6_BRI0                       (0x20000000uL)
+#define INTC_ICDISR6_ERI0                       (0x40000000uL)
+#define INTC_ICDISR6_RXI0                       (0x80000000uL)
+
+#define INTC_ICDISR7_TXI0                       (0x00000001uL)
+#define INTC_ICDISR7_BRI1                       (0x00000002uL)
+#define INTC_ICDISR7_ERI1                       (0x00000004uL)
+#define INTC_ICDISR7_RXI1                       (0x00000008uL)
+#define INTC_ICDISR7_TXI1                       (0x00000010uL)
+#define INTC_ICDISR7_BRI2                       (0x00000020uL)
+#define INTC_ICDISR7_ERI2                       (0x00000040uL)
+#define INTC_ICDISR7_RXI2                       (0x00000080uL)
+#define INTC_ICDISR7_TXI2                       (0x00000100uL)
+#define INTC_ICDISR7_BRI3                       (0x00000200uL)
+#define INTC_ICDISR7_ERI3                       (0x00000400uL)
+#define INTC_ICDISR7_RXI3                       (0x00000800uL)
+#define INTC_ICDISR7_TXI3                       (0x00001000uL)
+#define INTC_ICDISR7_BRI4                       (0x00002000uL)
+#define INTC_ICDISR7_ERI4                       (0x00004000uL)
+#define INTC_ICDISR7_RXI4                       (0x00008000uL)
+#define INTC_ICDISR7_TXI4                       (0x00010000uL)
+#define INTC_ICDISR7_BRI5                       (0x00020000uL)
+#define INTC_ICDISR7_ERI5                       (0x00040000uL)
+#define INTC_ICDISR7_RXI5                       (0x00080000uL)
+#define INTC_ICDISR7_TXI5                       (0x00100000uL)
+#define INTC_ICDISR7_BRI6                       (0x00200000uL)
+#define INTC_ICDISR7_ERI6                       (0x00400000uL)
+#define INTC_ICDISR7_RXI6                       (0x00800000uL)
+#define INTC_ICDISR7_TXI6                       (0x01000000uL)
+#define INTC_ICDISR7_BRI7                       (0x02000000uL)
+#define INTC_ICDISR7_ERI7                       (0x04000000uL)
+#define INTC_ICDISR7_RXI7                       (0x08000000uL)
+#define INTC_ICDISR7_TXI7                       (0x10000000uL)
+#define INTC_ICDISR7_INTRCANGERR                (0x20000000uL)
+#define INTC_ICDISR7_INTRCANGRECC               (0x40000000uL)
+#define INTC_ICDISR7_INTRCAN0REC                (0x80000000uL)
+
+#define INTC_ICDISR8_INTRCAN0ERR                (0x00000001uL)
+#define INTC_ICDISR8_INTRCAN0TRX                (0x00000002uL)
+#define INTC_ICDISR8_INTRCAN1REC                (0x00000004uL)
+#define INTC_ICDISR8_INTRCAN1ERR                (0x00000008uL)
+#define INTC_ICDISR8_INTRCAN1TRX                (0x00000010uL)
+#define INTC_ICDISR8_INTRCAN2REC                (0x00000020uL)
+#define INTC_ICDISR8_INTRCAN2ERR                (0x00000040uL)
+#define INTC_ICDISR8_INTRCAN2TRX                (0x00000080uL)
+#define INTC_ICDISR8_INTRCAN3REC                (0x00000100uL)
+#define INTC_ICDISR8_INTRCAN3ERR                (0x00000200uL)
+#define INTC_ICDISR8_INTRCAN3TRX                (0x00000400uL)
+#define INTC_ICDISR8_INTRCAN4REC                (0x00000800uL)
+#define INTC_ICDISR8_INTRCAN4ERR                (0x00001000uL)
+#define INTC_ICDISR8_INTRCAN4TRX                (0x00002000uL)
+#define INTC_ICDISR8_SPEI0                      (0x00004000uL)
+#define INTC_ICDISR8_SPRI0                      (0x00008000uL)
+#define INTC_ICDISR8_SPTI0                      (0x00010000uL)
+#define INTC_ICDISR8_SPEI1                      (0x00020000uL)
+#define INTC_ICDISR8_SPRI1                      (0x00040000uL)
+#define INTC_ICDISR8_SPTI1                      (0x00080000uL)
+#define INTC_ICDISR8_SPEI2                      (0x00100000uL)
+#define INTC_ICDISR8_SPRI2                      (0x00200000uL)
+#define INTC_ICDISR8_SPTI2                      (0x00400000uL)
+#define INTC_ICDISR8_SPEI3                      (0x00800000uL)
+#define INTC_ICDISR8_SPRI3                      (0x01000000uL)
+#define INTC_ICDISR8_SPTI3                      (0x02000000uL)
+#define INTC_ICDISR8_SPEI4                      (0x04000000uL)
+#define INTC_ICDISR8_SPRI4                      (0x08000000uL)
+#define INTC_ICDISR8_SPTI4                      (0x10000000uL)
+#define INTC_ICDISR8_IEBBTD                     (0x20000000uL)
+#define INTC_ICDISR8_IEBBTERR                   (0x40000000uL)
+#define INTC_ICDISR8_IEBBTSTA                   (0x80000000uL)
+
+#define INTC_ICDISR9_IEBBTV                     (0x00000001uL)
+#define INTC_ICDISR9_ISY                        (0x00000002uL)
+#define INTC_ICDISR9_IERR                       (0x00000004uL)
+#define INTC_ICDISR9_ITARG                      (0x00000008uL)
+#define INTC_ICDISR9_ISEC                       (0x00000010uL)
+#define INTC_ICDISR9_IBUF                       (0x00000020uL)
+#define INTC_ICDISR9_IREADY                     (0x00000040uL)
+#define INTC_ICDISR9_FLSTE                      (0x00000080uL)
+#define INTC_ICDISR9_FLTENDI                    (0x00000100uL)
+#define INTC_ICDISR9_FLTREQ0I                   (0x00000200uL)
+#define INTC_ICDISR9_FLTREQ1I                   (0x00000400uL)
+#define INTC_ICDISR9_MMC0                       (0x00000800uL)
+#define INTC_ICDISR9_MMC1                       (0x00001000uL)
+#define INTC_ICDISR9_MMC2                       (0x00002000uL)
+#define INTC_ICDISR9_SDHI0_3                    (0x00004000uL)
+#define INTC_ICDISR9_SDHI0_0                    (0x00008000uL)
+#define INTC_ICDISR9_SDHI0_1                    (0x00010000uL)
+#define INTC_ICDISR9_SDHI1_3                    (0x00020000uL)
+#define INTC_ICDISR9_SDHI1_0                    (0x00040000uL)
+#define INTC_ICDISR9_SDHI1_1                    (0x00080000uL)
+#define INTC_ICDISR9_ARM                        (0x00100000uL)
+#define INTC_ICDISR9_PRD                        (0x00200000uL)
+#define INTC_ICDISR9_CUP                        (0x00400000uL)
+#define INTC_ICDISR9_SCUAI0                     (0x00800000uL)
+#define INTC_ICDISR9_SCUAI1                     (0x01000000uL)
+#define INTC_ICDISR9_SCUFDI0                    (0x02000000uL)
+#define INTC_ICDISR9_SCUFDI1                    (0x04000000uL)
+#define INTC_ICDISR9_SCUFDI2                    (0x08000000uL)
+#define INTC_ICDISR9_SCUFDI3                    (0x10000000uL)
+#define INTC_ICDISR9_SCUFUI0                    (0x20000000uL)
+#define INTC_ICDISR9_SCUFUI1                    (0x40000000uL)
+#define INTC_ICDISR9_SCUFUI2                    (0x80000000uL)
+
+#define INTC_ICDISR10_SCUFUI3                   (0x00000001uL)
+#define INTC_ICDISR10_SCUDVI0                   (0x00000002uL)
+#define INTC_ICDISR10_SCUDVI1                   (0x00000004uL)
+#define INTC_ICDISR10_SCUDVI2                   (0x00000008uL)
+#define INTC_ICDISR10_SCUDVI3                   (0x00000010uL)
+#define INTC_ICDISR10_MLB_CINT                  (0x00000020uL)
+#define INTC_ICDISR10_MLB_SINT                  (0x00000040uL)
+#define INTC_ICDISR10_DRC0                      (0x00000080uL)
+#define INTC_ICDISR10_DRC1                      (0x00000100uL)
+#define INTC_ICDISR10_LINI0_INT_T               (0x00000800uL)
+#define INTC_ICDISR10_LINI0_INT_R               (0x00001000uL)
+#define INTC_ICDISR10_LINI0_INT_S               (0x00002000uL)
+#define INTC_ICDISR10_LINI0_INT_M               (0x00004000uL)
+#define INTC_ICDISR10_LINI1_INT_T               (0x00008000uL)
+#define INTC_ICDISR10_LINI1_INT_R               (0x00010000uL)
+#define INTC_ICDISR10_LINI1_INT_S               (0x00020000uL)
+#define INTC_ICDISR10_LINI1_INT_M               (0x00040000uL)
+#define INTC_ICDISR10_ERI0                      (0x08000000uL)
+#define INTC_ICDISR10_RXI0                      (0x10000000uL)
+#define INTC_ICDISR10_TXI0                      (0x20000000uL)
+#define INTC_ICDISR10_TEI0                      (0x40000000uL)
+#define INTC_ICDISR10_ERI1                      (0x80000000uL)
+
+#define INTC_ICDISR11_RXI1                      (0x00000001uL)
+#define INTC_ICDISR11_TXI1                      (0x00000002uL)
+#define INTC_ICDISR11_TEI1                      (0x00000004uL)
+#define INTC_ICDISR11_AVBI_DATA                 (0x00000008uL)
+#define INTC_ICDISR11_AVBI_ERROR                (0x00000010uL)
+#define INTC_ICDISR11_AVBI_MANAGE               (0x00000020uL)
+#define INTC_ICDISR11_AVBI_MAC                  (0x00000040uL)
+#define INTC_ICDISR11_ETHERI                    (0x00000080uL)
+#define INTC_ICDISR11_CEUI                      (0x00001000uL)
+#define INTC_ICDISR11_H2XMLB_ERRINT             (0x20000000uL)
+#define INTC_ICDISR11_H2XIC1_ERRINT             (0x40000000uL)
+#define INTC_ICDISR11_X2HPERI1_ERRINT           (0x80000000uL)
+
+#define INTC_ICDISR12_X2HPERI2_ERRINT           (0x00000001uL)
+#define INTC_ICDISR12_X2HPERI34_ERRINT          (0x00000002uL)
+#define INTC_ICDISR12_X2HPERI5_ERRINT           (0x00000004uL)
+#define INTC_ICDISR12_X2HPERI67_ERRINT          (0x00000008uL)
+#define INTC_ICDISR12_X2HDBGR_ERRINT            (0x00000010uL)
+#define INTC_ICDISR12_X2HBSC_ERRINT             (0x00000020uL)
+#define INTC_ICDISR12_X2HSPI1_ERRINT            (0x00000040uL)
+#define INTC_ICDISR12_X2HSPI2_ERRINT            (0x00000080uL)
+#define INTC_ICDISR12_PRRI                      (0x00000100uL)
+#define INTC_ICDISR12_IFEI0                     (0x00000200uL)
+#define INTC_ICDISR12_OFFI0                     (0x00000400uL)
+#define INTC_ICDISR12_PFVEI0                    (0x00000800uL)
+#define INTC_ICDISR12_IFEI1                     (0x00001000uL)
+#define INTC_ICDISR12_OFFI1                     (0x00002000uL)
+#define INTC_ICDISR12_PFVEI1                    (0x00004000uL)
+
+#define INTC_ICDISR13_TINT0                     (0x00000001uL)
+#define INTC_ICDISR13_TINT1                     (0x00000002uL)
+#define INTC_ICDISR13_TINT2                     (0x00000004uL)
+#define INTC_ICDISR13_TINT3                     (0x00000008uL)
+#define INTC_ICDISR13_TINT4                     (0x00000010uL)
+#define INTC_ICDISR13_TINT5                     (0x00000020uL)
+#define INTC_ICDISR13_TINT6                     (0x00000040uL)
+#define INTC_ICDISR13_TINT7                     (0x00000080uL)
+#define INTC_ICDISR13_TINT8                     (0x00000100uL)
+#define INTC_ICDISR13_TINT9                     (0x00000200uL)
+#define INTC_ICDISR13_TINT10                    (0x00000400uL)
+#define INTC_ICDISR13_TINT11                    (0x00000800uL)
+#define INTC_ICDISR13_TINT12                    (0x00001000uL)
+#define INTC_ICDISR13_TINT13                    (0x00002000uL)
+#define INTC_ICDISR13_TINT14                    (0x00004000uL)
+#define INTC_ICDISR13_TINT15                    (0x00008000uL)
+#define INTC_ICDISR13_TINT16                    (0x00010000uL)
+#define INTC_ICDISR13_TINT17                    (0x00020000uL)
+#define INTC_ICDISR13_TINT18                    (0x00040000uL)
+#define INTC_ICDISR13_TINT19                    (0x00080000uL)
+#define INTC_ICDISR13_TINT20                    (0x00100000uL)
+#define INTC_ICDISR13_TINT21                    (0x00200000uL)
+#define INTC_ICDISR13_TINT22                    (0x00400000uL)
+#define INTC_ICDISR13_TINT23                    (0x00800000uL)
+#define INTC_ICDISR13_TINT24                    (0x01000000uL)
+#define INTC_ICDISR13_TINT25                    (0x02000000uL)
+#define INTC_ICDISR13_TINT26                    (0x04000000uL)
+#define INTC_ICDISR13_TINT27                    (0x08000000uL)
+#define INTC_ICDISR13_TINT28                    (0x10000000uL)
+#define INTC_ICDISR13_TINT29                    (0x20000000uL)
+#define INTC_ICDISR13_TINT30                    (0x40000000uL)
+#define INTC_ICDISR13_TINT31                    (0x80000000uL)
+
+#define INTC_ICDISR14_TINT32                    (0x00000001uL)
+#define INTC_ICDISR14_TINT33                    (0x00000002uL)
+#define INTC_ICDISR14_TINT34                    (0x00000004uL)
+#define INTC_ICDISR14_TINT35                    (0x00000008uL)
+#define INTC_ICDISR14_TINT36                    (0x00000010uL)
+#define INTC_ICDISR14_TINT37                    (0x00000020uL)
+#define INTC_ICDISR14_TINT38                    (0x00000040uL)
+#define INTC_ICDISR14_TINT39                    (0x00000080uL)
+#define INTC_ICDISR14_TINT40                    (0x00000100uL)
+#define INTC_ICDISR14_TINT41                    (0x00000200uL)
+#define INTC_ICDISR14_TINT42                    (0x00000400uL)
+#define INTC_ICDISR14_TINT43                    (0x00000800uL)
+#define INTC_ICDISR14_TINT44                    (0x00001000uL)
+#define INTC_ICDISR14_TINT45                    (0x00002000uL)
+#define INTC_ICDISR14_TINT46                    (0x00004000uL)
+#define INTC_ICDISR14_TINT47                    (0x00008000uL)
+#define INTC_ICDISR14_TINT48                    (0x00010000uL)
+#define INTC_ICDISR14_TINT49                    (0x00020000uL)
+#define INTC_ICDISR14_TINT50                    (0x00040000uL)
+#define INTC_ICDISR14_TINT51                    (0x00080000uL)
+#define INTC_ICDISR14_TINT52                    (0x00100000uL)
+#define INTC_ICDISR14_TINT53                    (0x00200000uL)
+#define INTC_ICDISR14_TINT54                    (0x00400000uL)
+#define INTC_ICDISR14_TINT55                    (0x00800000uL)
+#define INTC_ICDISR14_TINT56                    (0x01000000uL)
+#define INTC_ICDISR14_TINT57                    (0x02000000uL)
+#define INTC_ICDISR14_TINT58                    (0x04000000uL)
+#define INTC_ICDISR14_TINT59                    (0x08000000uL)
+#define INTC_ICDISR14_TINT60                    (0x10000000uL)
+#define INTC_ICDISR14_TINT61                    (0x20000000uL)
+#define INTC_ICDISR14_TINT62                    (0x40000000uL)
+#define INTC_ICDISR14_TINT63                    (0x80000000uL)
+
+#define INTC_ICDISR15_TINT64                    (0x00000001uL)
+#define INTC_ICDISR15_TINT65                    (0x00000002uL)
+#define INTC_ICDISR15_TINT66                    (0x00000004uL)
+#define INTC_ICDISR15_TINT67                    (0x00000008uL)
+#define INTC_ICDISR15_TINT68                    (0x00000010uL)
+#define INTC_ICDISR15_TINT69                    (0x00000020uL)
+#define INTC_ICDISR15_TINT70                    (0x00000040uL)
+#define INTC_ICDISR15_TINT71                    (0x00000080uL)
+#define INTC_ICDISR15_TINT72                    (0x00000100uL)
+#define INTC_ICDISR15_TINT73                    (0x00000200uL)
+#define INTC_ICDISR15_TINT74                    (0x00000400uL)
+#define INTC_ICDISR15_TINT75                    (0x00000800uL)
+#define INTC_ICDISR15_TINT76                    (0x00001000uL)
+#define INTC_ICDISR15_TINT77                    (0x00002000uL)
+#define INTC_ICDISR15_TINT78                    (0x00004000uL)
+#define INTC_ICDISR15_TINT79                    (0x00008000uL)
+#define INTC_ICDISR15_TINT80                    (0x00010000uL)
+#define INTC_ICDISR15_TINT81                    (0x00020000uL)
+#define INTC_ICDISR15_TINT82                    (0x00040000uL)
+#define INTC_ICDISR15_TINT83                    (0x00080000uL)
+#define INTC_ICDISR15_TINT84                    (0x00100000uL)
+#define INTC_ICDISR15_TINT85                    (0x00200000uL)
+#define INTC_ICDISR15_TINT86                    (0x00400000uL)
+#define INTC_ICDISR15_TINT87                    (0x00800000uL)
+#define INTC_ICDISR15_TINT88                    (0x01000000uL)
+#define INTC_ICDISR15_TINT89                    (0x02000000uL)
+#define INTC_ICDISR15_TINT90                    (0x04000000uL)
+#define INTC_ICDISR15_TINT91                    (0x08000000uL)
+#define INTC_ICDISR15_TINT92                    (0x10000000uL)
+#define INTC_ICDISR15_TINT93                    (0x20000000uL)
+#define INTC_ICDISR15_TINT94                    (0x40000000uL)
+#define INTC_ICDISR15_TINT95                    (0x80000000uL)
+
+#define INTC_ICDISR16_TINT96                    (0x00000001uL)
+#define INTC_ICDISR16_TINT97                    (0x00000002uL)
+#define INTC_ICDISR16_TINT98                    (0x00000004uL)
+#define INTC_ICDISR16_TINT99                    (0x00000008uL)
+#define INTC_ICDISR16_TINT100                   (0x00000010uL)
+#define INTC_ICDISR16_TINT101                   (0x00000020uL)
+#define INTC_ICDISR16_TINT102                   (0x00000040uL)
+#define INTC_ICDISR16_TINT103                   (0x00000080uL)
+#define INTC_ICDISR16_TINT104                   (0x00000100uL)
+#define INTC_ICDISR16_TINT105                   (0x00000200uL)
+#define INTC_ICDISR16_TINT106                   (0x00000400uL)
+#define INTC_ICDISR16_TINT107                   (0x00000800uL)
+#define INTC_ICDISR16_TINT108                   (0x00001000uL)
+#define INTC_ICDISR16_TINT109                   (0x00002000uL)
+#define INTC_ICDISR16_TINT110                   (0x00004000uL)
+#define INTC_ICDISR16_TINT111                   (0x00008000uL)
+#define INTC_ICDISR16_TINT112                   (0x00010000uL)
+#define INTC_ICDISR16_TINT113                   (0x00020000uL)
+#define INTC_ICDISR16_TINT114                   (0x00040000uL)
+#define INTC_ICDISR16_TINT115                   (0x00080000uL)
+#define INTC_ICDISR16_TINT116                   (0x00100000uL)
+#define INTC_ICDISR16_TINT117                   (0x00200000uL)
+#define INTC_ICDISR16_TINT118                   (0x00400000uL)
+#define INTC_ICDISR16_TINT119                   (0x00800000uL)
+#define INTC_ICDISR16_TINT120                   (0x01000000uL)
+#define INTC_ICDISR16_TINT121                   (0x02000000uL)
+#define INTC_ICDISR16_TINT122                   (0x04000000uL)
+#define INTC_ICDISR16_TINT123                   (0x08000000uL)
+#define INTC_ICDISR16_TINT124                   (0x10000000uL)
+#define INTC_ICDISR16_TINT125                   (0x20000000uL)
+#define INTC_ICDISR16_TINT126                   (0x40000000uL)
+#define INTC_ICDISR16_TINT127                   (0x80000000uL)
+
+#define INTC_ICDISR17_TINT128                   (0x00000001uL)
+#define INTC_ICDISR17_TINT129                   (0x00000002uL)
+#define INTC_ICDISR17_TINT130                   (0x00000004uL)
+#define INTC_ICDISR17_TINT131                   (0x00000008uL)
+#define INTC_ICDISR17_TINT132                   (0x00000010uL)
+#define INTC_ICDISR17_TINT133                   (0x00000020uL)
+#define INTC_ICDISR17_TINT134                   (0x00000040uL)
+#define INTC_ICDISR17_TINT135                   (0x00000080uL)
+#define INTC_ICDISR17_TINT136                   (0x00000100uL)
+#define INTC_ICDISR17_TINT137                   (0x00000200uL)
+#define INTC_ICDISR17_TINT138                   (0x00000400uL)
+#define INTC_ICDISR17_TINT139                   (0x00000800uL)
+#define INTC_ICDISR17_TINT140                   (0x00001000uL)
+#define INTC_ICDISR17_TINT141                   (0x00002000uL)
+#define INTC_ICDISR17_TINT142                   (0x00004000uL)
+#define INTC_ICDISR17_TINT143                   (0x00008000uL)
+#define INTC_ICDISR17_TINT144                   (0x00010000uL)
+#define INTC_ICDISR17_TINT145                   (0x00020000uL)
+#define INTC_ICDISR17_TINT146                   (0x00040000uL)
+#define INTC_ICDISR17_TINT147                   (0x00080000uL)
+#define INTC_ICDISR17_TINT148                   (0x00100000uL)
+#define INTC_ICDISR17_TINT149                   (0x00200000uL)
+#define INTC_ICDISR17_TINT150                   (0x00400000uL)
+#define INTC_ICDISR17_TINT151                   (0x00800000uL)
+#define INTC_ICDISR17_TINT152                   (0x01000000uL)
+#define INTC_ICDISR17_TINT153                   (0x02000000uL)
+#define INTC_ICDISR17_TINT154                   (0x04000000uL)
+#define INTC_ICDISR17_TINT155                   (0x08000000uL)
+#define INTC_ICDISR17_TINT156                   (0x10000000uL)
+#define INTC_ICDISR17_TINT157                   (0x20000000uL)
+#define INTC_ICDISR17_TINT158                   (0x40000000uL)
+#define INTC_ICDISR17_TINT159                   (0x80000000uL)
+
+#define INTC_ICDISR18_TINT160                   (0x00000001uL)
+#define INTC_ICDISR18_TINT161                   (0x00000002uL)
+#define INTC_ICDISR18_TINT162                   (0x00000004uL)
+#define INTC_ICDISR18_TINT163                   (0x00000008uL)
+#define INTC_ICDISR18_TINT164                   (0x00000010uL)
+#define INTC_ICDISR18_TINT165                   (0x00000020uL)
+#define INTC_ICDISR18_TINT166                   (0x00000040uL)
+#define INTC_ICDISR18_TINT167                   (0x00000080uL)
+#define INTC_ICDISR18_TINT168                   (0x00000100uL)
+#define INTC_ICDISR18_TINT169                   (0x00000200uL)
+#define INTC_ICDISR18_TINT170                   (0x00000400uL)
+
+#define INTC_ICDISER0_SW0                       (0x00000001uL)
+#define INTC_ICDISER0_SW1                       (0x00000002uL)
+#define INTC_ICDISER0_SW2                       (0x00000004uL)
+#define INTC_ICDISER0_SW3                       (0x00000008uL)
+#define INTC_ICDISER0_SW4                       (0x00000010uL)
+#define INTC_ICDISER0_SW5                       (0x00000020uL)
+#define INTC_ICDISER0_SW6                       (0x00000040uL)
+#define INTC_ICDISER0_SW7                       (0x00000080uL)
+#define INTC_ICDISER0_SW8                       (0x00000100uL)
+#define INTC_ICDISER0_SW9                       (0x00000200uL)
+#define INTC_ICDISER0_SW10                      (0x00000400uL)
+#define INTC_ICDISER0_SW11                      (0x00000800uL)
+#define INTC_ICDISER0_SW12                      (0x00001000uL)
+#define INTC_ICDISER0_SW13                      (0x00002000uL)
+#define INTC_ICDISER0_SW14                      (0x00004000uL)
+#define INTC_ICDISER0_SW15                      (0x00008000uL)
+#define INTC_ICDISER0_PMUIRQ0                   (0x00010000uL)
+#define INTC_ICDISER0_COMMRX0                   (0x00020000uL)
+#define INTC_ICDISER0_COMMTX0                   (0x00040000uL)
+#define INTC_ICDISER0_CTIIRQ0                   (0x00080000uL)
+
+#define INTC_ICDISER1_IRQ0                      (0x00000001uL)
+#define INTC_ICDISER1_IRQ1                      (0x00000002uL)
+#define INTC_ICDISER1_IRQ2                      (0x00000004uL)
+#define INTC_ICDISER1_IRQ3                      (0x00000008uL)
+#define INTC_ICDISER1_IRQ4                      (0x00000010uL)
+#define INTC_ICDISER1_IRQ5                      (0x00000020uL)
+#define INTC_ICDISER1_IRQ6                      (0x00000040uL)
+#define INTC_ICDISER1_IRQ7                      (0x00000080uL)
+#define INTC_ICDISER1_PL310ERR                  (0x00000100uL)
+#define INTC_ICDISER1_DMAINT0                   (0x00000200uL)
+#define INTC_ICDISER1_DMAINT1                   (0x00000400uL)
+#define INTC_ICDISER1_DMAINT2                   (0x00000800uL)
+#define INTC_ICDISER1_DMAINT3                   (0x00001000uL)
+#define INTC_ICDISER1_DMAINT4                   (0x00002000uL)
+#define INTC_ICDISER1_DMAINT5                   (0x00004000uL)
+#define INTC_ICDISER1_DMAINT6                   (0x00008000uL)
+#define INTC_ICDISER1_DMAINT7                   (0x00010000uL)
+#define INTC_ICDISER1_DMAINT8                   (0x00020000uL)
+#define INTC_ICDISER1_DMAINT9                   (0x00040000uL)
+#define INTC_ICDISER1_DMAINT10                  (0x00080000uL)
+#define INTC_ICDISER1_DMAINT11                  (0x00100000uL)
+#define INTC_ICDISER1_DMAINT12                  (0x00200000uL)
+#define INTC_ICDISER1_DMAINT13                  (0x00400000uL)
+#define INTC_ICDISER1_DMAINT14                  (0x00800000uL)
+#define INTC_ICDISER1_DMAINT15                  (0x01000000uL)
+#define INTC_ICDISER1_DMAERR                    (0x02000000uL)
+
+#define INTC_ICDISER2_USBI0                     (0x00000200uL)
+#define INTC_ICDISER2_USBI1                     (0x00000400uL)
+#define INTC_ICDISER2_S0_VI_VSYNC0              (0x00000800uL)
+#define INTC_ICDISER2_S0_LO_VSYNC0              (0x00001000uL)
+#define INTC_ICDISER2_S0_VSYNCERR0              (0x00002000uL)
+#define INTC_ICDISER2_GR3_VLINE0                (0x00004000uL)
+#define INTC_ICDISER2_S0_VFIELD0                (0x00008000uL)
+#define INTC_ICDISER2_IV1_VBUFERR0              (0x00010000uL)
+#define INTC_ICDISER2_IV3_VBUFERR0              (0x00020000uL)
+#define INTC_ICDISER2_IV5_VBUFERR0              (0x00040000uL)
+#define INTC_ICDISER2_IV6_VBUFERR0              (0x00080000uL)
+#define INTC_ICDISER2_S0_WLINE0                 (0x00100000uL)
+#define INTC_ICDISER2_S1_VI_VSYNC0              (0x00200000uL)
+#define INTC_ICDISER2_S1_LO_VSYNC0              (0x00400000uL)
+#define INTC_ICDISER2_S1_VSYNCERR0              (0x00800000uL)
+#define INTC_ICDISER2_S1_VFIELD0                (0x01000000uL)
+#define INTC_ICDISER2_IV2_VBUFERR0              (0x02000000uL)
+#define INTC_ICDISER2_IV4_VBUFERR0              (0x04000000uL)
+#define INTC_ICDISER2_S1_WLINE0                 (0x08000000uL)
+#define INTC_ICDISER2_OIR_VI_VSYNC0             (0x10000000uL)
+#define INTC_ICDISER2_OIR_LO_VSYNC0             (0x20000000uL)
+#define INTC_ICDISER2_OIR_VSYNCERR0             (0x40000000uL)
+#define INTC_ICDISER2_OIR_VFIELD0               (0x80000000uL)
+
+#define INTC_ICDISER3_IV7_VBUFERR0              (0x00000001uL)
+#define INTC_ICDISER3_IV8_VBUFERR0              (0x00000002uL)
+#define INTC_ICDISER3_S0_VI_VSYNC1              (0x00000008uL)
+#define INTC_ICDISER3_S0_LO_VSYNC1              (0x00000010uL)
+#define INTC_ICDISER3_S0_VSYNCERR1              (0x00000020uL)
+#define INTC_ICDISER3_GR3_VLINE1                (0x00000040uL)
+#define INTC_ICDISER3_S0_VFIELD1                (0x00000080uL)
+#define INTC_ICDISER3_IV1_VBUFERR1              (0x00000100uL)
+#define INTC_ICDISER3_IV3_VBUFERR1              (0x00000200uL)
+#define INTC_ICDISER3_IV5_VBUFERR1              (0x00000400uL)
+#define INTC_ICDISER3_IV6_VBUFERR1              (0x00000800uL)
+#define INTC_ICDISER3_S0_WLINE1                 (0x00001000uL)
+#define INTC_ICDISER3_S1_VI_VSYNC1              (0x00002000uL)
+#define INTC_ICDISER3_S1_LO_VSYNC1              (0x00004000uL)
+#define INTC_ICDISER3_S1_VSYNCERR1              (0x00008000uL)
+#define INTC_ICDISER3_S1_VFIELD1                (0x00010000uL)
+#define INTC_ICDISER3_IV2_VBUFERR1              (0x00020000uL)
+#define INTC_ICDISER3_IV4_VBUFERR1              (0x00040000uL)
+#define INTC_ICDISER3_S1_WLINE1                 (0x00080000uL)
+#define INTC_ICDISER3_OIR_VI_VSYNC1             (0x00100000uL)
+#define INTC_ICDISER3_OIR_LO_VSYNC1             (0x00200000uL)
+#define INTC_ICDISER3_OIR_VLINE1                (0x00400000uL)
+#define INTC_ICDISER3_OIR_VFIELD1               (0x00800000uL)
+#define INTC_ICDISER3_IV7_VBUFERR1              (0x01000000uL)
+#define INTC_ICDISER3_IV8_VBUFERR1              (0x02000000uL)
+#define INTC_ICDISER3_IMRDI                     (0x08000000uL)
+#define INTC_ICDISER3_IMR2I0                    (0x10000000uL)
+#define INTC_ICDISER3_IMR2I1                    (0x20000000uL)
+#define INTC_ICDISER3_JEDI                      (0x40000000uL)
+#define INTC_ICDISER3_JDTI                      (0x80000000uL)
+
+#define INTC_ICDISER4_CMP0                      (0x00000001uL)
+#define INTC_ICDISER4_CMP1                      (0x00000002uL)
+#define INTC_ICDISER4_INT0                      (0x00000004uL)
+#define INTC_ICDISER4_INT1                      (0x00000008uL)
+#define INTC_ICDISER4_INT2                      (0x00000010uL)
+#define INTC_ICDISER4_INT3                      (0x00000020uL)
+#define INTC_ICDISER4_OSTM0TINT                 (0x00000040uL)
+#define INTC_ICDISER4_OSTM1TINT                 (0x00000080uL)
+#define INTC_ICDISER4_CMI                       (0x00000100uL)
+#define INTC_ICDISER4_WTOUT                     (0x00000200uL)
+#define INTC_ICDISER4_ITI                       (0x00000400uL)
+#define INTC_ICDISER4_TGI0A                     (0x00000800uL)
+#define INTC_ICDISER4_TGI0B                     (0x00001000uL)
+#define INTC_ICDISER4_TGI0C                     (0x00002000uL)
+#define INTC_ICDISER4_TGI0D                     (0x00004000uL)
+#define INTC_ICDISER4_TGI0V                     (0x00008000uL)
+#define INTC_ICDISER4_TGI0E                     (0x00010000uL)
+#define INTC_ICDISER4_TGI0F                     (0x00020000uL)
+#define INTC_ICDISER4_TGI1A                     (0x00040000uL)
+#define INTC_ICDISER4_TGI1B                     (0x00080000uL)
+#define INTC_ICDISER4_TGI1V                     (0x00100000uL)
+#define INTC_ICDISER4_TGI1U                     (0x00200000uL)
+#define INTC_ICDISER4_TGI2A                     (0x00400000uL)
+#define INTC_ICDISER4_TGI2B                     (0x00800000uL)
+#define INTC_ICDISER4_TGI2V                     (0x01000000uL)
+#define INTC_ICDISER4_TGI2U                     (0x02000000uL)
+#define INTC_ICDISER4_TGI3A                     (0x04000000uL)
+#define INTC_ICDISER4_TGI3B                     (0x08000000uL)
+#define INTC_ICDISER4_TGI3C                     (0x10000000uL)
+#define INTC_ICDISER4_TGI3D                     (0x20000000uL)
+#define INTC_ICDISER4_TGI3V                     (0x40000000uL)
+#define INTC_ICDISER4_TGI4A                     (0x80000000uL)
+
+#define INTC_ICDISER5_TGI4B                     (0x00000001uL)
+#define INTC_ICDISER5_TGI4C                     (0x00000002uL)
+#define INTC_ICDISER5_TGI4D                     (0x00000004uL)
+#define INTC_ICDISER5_TGI4V                     (0x00000008uL)
+#define INTC_ICDISER5_CMI1                      (0x00000010uL)
+#define INTC_ICDISER5_CMI2                      (0x00000020uL)
+#define INTC_ICDISER5_SGDEI0                    (0x00000040uL)
+#define INTC_ICDISER5_SGDEI1                    (0x00000080uL)
+#define INTC_ICDISER5_SGDEI2                    (0x00000100uL)
+#define INTC_ICDISER5_SGDEI3                    (0x00000200uL)
+#define INTC_ICDISER5_ADI                       (0x00000400uL)
+#define INTC_ICDISER5_LMTI                      (0x00000800uL)
+#define INTC_ICDISER5_SSII0                     (0x00001000uL)
+#define INTC_ICDISER5_SSIRXI0                   (0x00002000uL)
+#define INTC_ICDISER5_SSITXI0                   (0x00004000uL)
+#define INTC_ICDISER5_SSII1                     (0x00008000uL)
+#define INTC_ICDISER5_SSIRXI1                   (0x00010000uL)
+#define INTC_ICDISER5_SSITXI1                   (0x00020000uL)
+#define INTC_ICDISER5_SSII2                     (0x00040000uL)
+#define INTC_ICDISER5_SSIRTI2                   (0x00080000uL)
+#define INTC_ICDISER5_SSII3                     (0x00100000uL)
+#define INTC_ICDISER5_SSIRXI3                   (0x00200000uL)
+#define INTC_ICDISER5_SSITXI3                   (0x00400000uL)
+#define INTC_ICDISER5_SSII4                     (0x00800000uL)
+#define INTC_ICDISER5_SSIRTI4                   (0x01000000uL)
+#define INTC_ICDISER5_SSII5                     (0x02000000uL)
+#define INTC_ICDISER5_SSIRXI5                   (0x04000000uL)
+#define INTC_ICDISER5_SSITXI5                   (0x08000000uL)
+#define INTC_ICDISER5_SPDIFI                    (0x10000000uL)
+#define INTC_ICDISER5_INTIICTEI0                (0x20000000uL)
+#define INTC_ICDISER5_INTIICRI0                 (0x40000000uL)
+#define INTC_ICDISER5_INTIICTI0                 (0x80000000uL)
+
+#define INTC_ICDISER6_INTIICSPI0                (0x00000001uL)
+#define INTC_ICDISER6_INTIICSTI0                (0x00000002uL)
+#define INTC_ICDISER6_INTIICNAKI0               (0x00000004uL)
+#define INTC_ICDISER6_INTIICALI0                (0x00000008uL)
+#define INTC_ICDISER6_INTIICTMOI0               (0x00000010uL)
+#define INTC_ICDISER6_INTIICTEI1                (0x00000020uL)
+#define INTC_ICDISER6_INTIICRI1                 (0x00000040uL)
+#define INTC_ICDISER6_INTIICTI1                 (0x00000080uL)
+#define INTC_ICDISER6_INTIICSPI1                (0x00000100uL)
+#define INTC_ICDISER6_INTIICSTI1                (0x00000200uL)
+#define INTC_ICDISER6_INTIICNAKI1               (0x00000400uL)
+#define INTC_ICDISER6_INTIICALI1                (0x00000800uL)
+#define INTC_ICDISER6_INTIICTMOI1               (0x00001000uL)
+#define INTC_ICDISER6_INTIICTEI2                (0x00002000uL)
+#define INTC_ICDISER6_INTIICRI2                 (0x00004000uL)
+#define INTC_ICDISER6_INTIICTI2                 (0x00008000uL)
+#define INTC_ICDISER6_INTIICSPI2                (0x00010000uL)
+#define INTC_ICDISER6_INTIICSTI2                (0x00020000uL)
+#define INTC_ICDISER6_INTIICNAKI2               (0x00040000uL)
+#define INTC_ICDISER6_INTIICALI2                (0x00080000uL)
+#define INTC_ICDISER6_INTIICTMOI2               (0x00100000uL)
+#define INTC_ICDISER6_INTIICTEI3                (0x00200000uL)
+#define INTC_ICDISER6_INTIICRI3                 (0x00400000uL)
+#define INTC_ICDISER6_INTIICTI3                 (0x00800000uL)
+#define INTC_ICDISER6_INTIICSPI3                (0x01000000uL)
+#define INTC_ICDISER6_INTIICSTI3                (0x02000000uL)
+#define INTC_ICDISER6_INTIICNAKI3               (0x04000000uL)
+#define INTC_ICDISER6_INTIICALI3                (0x08000000uL)
+#define INTC_ICDISER6_INTIICTMOI3               (0x10000000uL)
+#define INTC_ICDISER6_BRI0                      (0x20000000uL)
+#define INTC_ICDISER6_ERI0                      (0x40000000uL)
+#define INTC_ICDISER6_RXI0                      (0x80000000uL)
+
+#define INTC_ICDISER7_TXI0                      (0x00000001uL)
+#define INTC_ICDISER7_BRI1                      (0x00000002uL)
+#define INTC_ICDISER7_ERI1                      (0x00000004uL)
+#define INTC_ICDISER7_RXI1                      (0x00000008uL)
+#define INTC_ICDISER7_TXI1                      (0x00000010uL)
+#define INTC_ICDISER7_BRI2                      (0x00000020uL)
+#define INTC_ICDISER7_ERI2                      (0x00000040uL)
+#define INTC_ICDISER7_RXI2                      (0x00000080uL)
+#define INTC_ICDISER7_TXI2                      (0x00000100uL)
+#define INTC_ICDISER7_BRI3                      (0x00000200uL)
+#define INTC_ICDISER7_ERI3                      (0x00000400uL)
+#define INTC_ICDISER7_RXI3                      (0x00000800uL)
+#define INTC_ICDISER7_TXI3                      (0x00001000uL)
+#define INTC_ICDISER7_BRI4                      (0x00002000uL)
+#define INTC_ICDISER7_ERI4                      (0x00004000uL)
+#define INTC_ICDISER7_RXI4                      (0x00008000uL)
+#define INTC_ICDISER7_TXI4                      (0x00010000uL)
+#define INTC_ICDISER7_BRI5                      (0x00020000uL)
+#define INTC_ICDISER7_ERI5                      (0x00040000uL)
+#define INTC_ICDISER7_RXI5                      (0x00080000uL)
+#define INTC_ICDISER7_TXI5                      (0x00100000uL)
+#define INTC_ICDISER7_BRI6                      (0x00200000uL)
+#define INTC_ICDISER7_ERI6                      (0x00400000uL)
+#define INTC_ICDISER7_RXI6                      (0x00800000uL)
+#define INTC_ICDISER7_TXI6                      (0x01000000uL)
+#define INTC_ICDISER7_BRI7                      (0x02000000uL)
+#define INTC_ICDISER7_ERI7                      (0x04000000uL)
+#define INTC_ICDISER7_RXI7                      (0x08000000uL)
+#define INTC_ICDISER7_TXI7                      (0x10000000uL)
+#define INTC_ICDISER7_INTRCANGERR               (0x20000000uL)
+#define INTC_ICDISER7_INTRCANGRECC              (0x40000000uL)
+#define INTC_ICDISER7_INTRCAN0REC               (0x80000000uL)
+
+#define INTC_ICDISER8_INTRCAN0ERR               (0x00000001uL)
+#define INTC_ICDISER8_INTRCAN0TRX               (0x00000002uL)
+#define INTC_ICDISER8_INTRCAN1REC               (0x00000004uL)
+#define INTC_ICDISER8_INTRCAN1ERR               (0x00000008uL)
+#define INTC_ICDISER8_INTRCAN1TRX               (0x00000010uL)
+#define INTC_ICDISER8_INTRCAN2REC               (0x00000020uL)
+#define INTC_ICDISER8_INTRCAN2ERR               (0x00000040uL)
+#define INTC_ICDISER8_INTRCAN2TRX               (0x00000080uL)
+#define INTC_ICDISER8_INTRCAN3REC               (0x00000100uL)
+#define INTC_ICDISER8_INTRCAN3ERR               (0x00000200uL)
+#define INTC_ICDISER8_INTRCAN3TRX               (0x00000400uL)
+#define INTC_ICDISER8_INTRCAN4REC               (0x00000800uL)
+#define INTC_ICDISER8_INTRCAN4ERR               (0x00001000uL)
+#define INTC_ICDISER8_INTRCAN4TRX               (0x00002000uL)
+#define INTC_ICDISER8_SPEI0                     (0x00004000uL)
+#define INTC_ICDISER8_SPRI0                     (0x00008000uL)
+#define INTC_ICDISER8_SPTI0                     (0x00010000uL)
+#define INTC_ICDISER8_SPEI1                     (0x00020000uL)
+#define INTC_ICDISER8_SPRI1                     (0x00040000uL)
+#define INTC_ICDISER8_SPTI1                     (0x00080000uL)
+#define INTC_ICDISER8_SPEI2                     (0x00100000uL)
+#define INTC_ICDISER8_SPRI2                     (0x00200000uL)
+#define INTC_ICDISER8_SPTI2                     (0x00400000uL)
+#define INTC_ICDISER8_SPEI3                     (0x00800000uL)
+#define INTC_ICDISER8_SPRI3                     (0x01000000uL)
+#define INTC_ICDISER8_SPTI3                     (0x02000000uL)
+#define INTC_ICDISER8_SPEI4                     (0x04000000uL)
+#define INTC_ICDISER8_SPRI4                     (0x08000000uL)
+#define INTC_ICDISER8_SPTI4                     (0x10000000uL)
+#define INTC_ICDISER8_IEBBTD                    (0x20000000uL)
+#define INTC_ICDISER8_IEBBTERR                  (0x40000000uL)
+#define INTC_ICDISER8_IEBBTSTA                  (0x80000000uL)
+
+#define INTC_ICDISER9_IEBBTV                    (0x00000001uL)
+#define INTC_ICDISER9_ISY                       (0x00000002uL)
+#define INTC_ICDISER9_IERR                      (0x00000004uL)
+#define INTC_ICDISER9_ITARG                     (0x00000008uL)
+#define INTC_ICDISER9_ISEC                      (0x00000010uL)
+#define INTC_ICDISER9_IBUF                      (0x00000020uL)
+#define INTC_ICDISER9_IREADY                    (0x00000040uL)
+#define INTC_ICDISER9_FLSTE                     (0x00000080uL)
+#define INTC_ICDISER9_FLTENDI                   (0x00000100uL)
+#define INTC_ICDISER9_FLTREQ0I                  (0x00000200uL)
+#define INTC_ICDISER9_FLTREQ1I                  (0x00000400uL)
+#define INTC_ICDISER9_MMC0                      (0x00000800uL)
+#define INTC_ICDISER9_MMC1                      (0x00001000uL)
+#define INTC_ICDISER9_MMC2                      (0x00002000uL)
+#define INTC_ICDISER9_SDHI0_3                   (0x00004000uL)
+#define INTC_ICDISER9_SDHI0_0                   (0x00008000uL)
+#define INTC_ICDISER9_SDHI0_1                   (0x00010000uL)
+#define INTC_ICDISER9_SDHI1_3                   (0x00020000uL)
+#define INTC_ICDISER9_SDHI1_0                   (0x00040000uL)
+#define INTC_ICDISER9_SDHI1_1                   (0x00080000uL)
+#define INTC_ICDISER9_ARM                       (0x00100000uL)
+#define INTC_ICDISER9_PRD                       (0x00200000uL)
+#define INTC_ICDISER9_CUP                       (0x00400000uL)
+#define INTC_ICDISER9_SCUAI0                    (0x00800000uL)
+#define INTC_ICDISER9_SCUAI1                    (0x01000000uL)
+#define INTC_ICDISER9_SCUFDI0                   (0x02000000uL)
+#define INTC_ICDISER9_SCUFDI1                   (0x04000000uL)
+#define INTC_ICDISER9_SCUFDI2                   (0x08000000uL)
+#define INTC_ICDISER9_SCUFDI3                   (0x10000000uL)
+#define INTC_ICDISER9_SCUFUI0                   (0x20000000uL)
+#define INTC_ICDISER9_SCUFUI1                   (0x40000000uL)
+#define INTC_ICDISER9_SCUFUI2                   (0x80000000uL)
+
+#define INTC_ICDISER10_SCUFUI3                  (0x00000001uL)
+#define INTC_ICDISER10_SCUDVI0                  (0x00000002uL)
+#define INTC_ICDISER10_SCUDVI1                  (0x00000004uL)
+#define INTC_ICDISER10_SCUDVI2                  (0x00000008uL)
+#define INTC_ICDISER10_SCUDVI3                  (0x00000010uL)
+#define INTC_ICDISER10_MLB_CINT                 (0x00000020uL)
+#define INTC_ICDISER10_MLB_SINT                 (0x00000040uL)
+#define INTC_ICDISER10_DRC0                     (0x00000080uL)
+#define INTC_ICDISER10_DRC1                     (0x00000100uL)
+#define INTC_ICDISER10_LINI0_INT_T              (0x00000800uL)
+#define INTC_ICDISER10_LINI0_INT_R              (0x00001000uL)
+#define INTC_ICDISER10_LINI0_INT_S              (0x00002000uL)
+#define INTC_ICDISER10_LINI0_INT_M              (0x00004000uL)
+#define INTC_ICDISER10_LINI1_INT_T              (0x00008000uL)
+#define INTC_ICDISER10_LINI1_INT_R              (0x00010000uL)
+#define INTC_ICDISER10_LINI1_INT_S              (0x00020000uL)
+#define INTC_ICDISER10_LINI1_INT_M              (0x00040000uL)
+#define INTC_ICDISER10_ERI0                     (0x08000000uL)
+#define INTC_ICDISER10_RXI0                     (0x10000000uL)
+#define INTC_ICDISER10_TXI0                     (0x20000000uL)
+#define INTC_ICDISER10_TEI0                     (0x40000000uL)
+#define INTC_ICDISER10_ERI1                     (0x80000000uL)
+
+#define INTC_ICDISER11_RXI1                     (0x00000001uL)
+#define INTC_ICDISER11_TXI1                     (0x00000002uL)
+#define INTC_ICDISER11_TEI1                     (0x00000004uL)
+#define INTC_ICDISER11_AVBI_DATA                (0x00000008uL)
+#define INTC_ICDISER11_AVBI_ERROR               (0x00000010uL)
+#define INTC_ICDISER11_AVBI_MANAGE              (0x00000020uL)
+#define INTC_ICDISER11_AVBI_MAC                 (0x00000040uL)
+#define INTC_ICDISER11_ETHERI                   (0x00000080uL)
+#define INTC_ICDISER11_CEUI                     (0x00001000uL)
+#define INTC_ICDISER11_H2XMLB_ERRINT            (0x20000000uL)
+#define INTC_ICDISER11_H2XIC1_ERRINT            (0x40000000uL)
+#define INTC_ICDISER11_X2HPERI1_ERRINT          (0x80000000uL)
+
+#define INTC_ICDISER12_X2HPERI2_ERRINT          (0x00000001uL)
+#define INTC_ICDISER12_X2HPERI34_ERRINT         (0x00000002uL)
+#define INTC_ICDISER12_X2HPERI5_ERRINT          (0x00000004uL)
+#define INTC_ICDISER12_X2HPERI67_ERRINT         (0x00000008uL)
+#define INTC_ICDISER12_X2HDBGR_ERRINT           (0x00000010uL)
+#define INTC_ICDISER12_X2HBSC_ERRINT            (0x00000020uL)
+#define INTC_ICDISER12_X2HSPI1_ERRINT           (0x00000040uL)
+#define INTC_ICDISER12_X2HSPI2_ERRINT           (0x00000080uL)
+#define INTC_ICDISER12_PRRI                     (0x00000100uL)
+#define INTC_ICDISER12_IFEI0                    (0x00000200uL)
+#define INTC_ICDISER12_OFFI0                    (0x00000400uL)
+#define INTC_ICDISER12_PFVEI0                   (0x00000800uL)
+#define INTC_ICDISER12_IFEI1                    (0x00001000uL)
+#define INTC_ICDISER12_OFFI1                    (0x00002000uL)
+#define INTC_ICDISER12_PFVEI1                   (0x00004000uL)
+
+#define INTC_ICDISER13_TINT0                    (0x00000001uL)
+#define INTC_ICDISER13_TINT1                    (0x00000002uL)
+#define INTC_ICDISER13_TINT2                    (0x00000004uL)
+#define INTC_ICDISER13_TINT3                    (0x00000008uL)
+#define INTC_ICDISER13_TINT4                    (0x00000010uL)
+#define INTC_ICDISER13_TINT5                    (0x00000020uL)
+#define INTC_ICDISER13_TINT6                    (0x00000040uL)
+#define INTC_ICDISER13_TINT7                    (0x00000080uL)
+#define INTC_ICDISER13_TINT8                    (0x00000100uL)
+#define INTC_ICDISER13_TINT9                    (0x00000200uL)
+#define INTC_ICDISER13_TINT10                   (0x00000400uL)
+#define INTC_ICDISER13_TINT11                   (0x00000800uL)
+#define INTC_ICDISER13_TINT12                   (0x00001000uL)
+#define INTC_ICDISER13_TINT13                   (0x00002000uL)
+#define INTC_ICDISER13_TINT14                   (0x00004000uL)
+#define INTC_ICDISER13_TINT15                   (0x00008000uL)
+#define INTC_ICDISER13_TINT16                   (0x00010000uL)
+#define INTC_ICDISER13_TINT17                   (0x00020000uL)
+#define INTC_ICDISER13_TINT18                   (0x00040000uL)
+#define INTC_ICDISER13_TINT19                   (0x00080000uL)
+#define INTC_ICDISER13_TINT20                   (0x00100000uL)
+#define INTC_ICDISER13_TINT21                   (0x00200000uL)
+#define INTC_ICDISER13_TINT22                   (0x00400000uL)
+#define INTC_ICDISER13_TINT23                   (0x00800000uL)
+#define INTC_ICDISER13_TINT24                   (0x01000000uL)
+#define INTC_ICDISER13_TINT25                   (0x02000000uL)
+#define INTC_ICDISER13_TINT26                   (0x04000000uL)
+#define INTC_ICDISER13_TINT27                   (0x08000000uL)
+#define INTC_ICDISER13_TINT28                   (0x10000000uL)
+#define INTC_ICDISER13_TINT29                   (0x20000000uL)
+#define INTC_ICDISER13_TINT30                   (0x40000000uL)
+#define INTC_ICDISER13_TINT31                   (0x80000000uL)
+
+#define INTC_ICDISER14_TINT32                   (0x00000001uL)
+#define INTC_ICDISER14_TINT33                   (0x00000002uL)
+#define INTC_ICDISER14_TINT34                   (0x00000004uL)
+#define INTC_ICDISER14_TINT35                   (0x00000008uL)
+#define INTC_ICDISER14_TINT36                   (0x00000010uL)
+#define INTC_ICDISER14_TINT37                   (0x00000020uL)
+#define INTC_ICDISER14_TINT38                   (0x00000040uL)
+#define INTC_ICDISER14_TINT39                   (0x00000080uL)
+#define INTC_ICDISER14_TINT40                   (0x00000100uL)
+#define INTC_ICDISER14_TINT41                   (0x00000200uL)
+#define INTC_ICDISER14_TINT42                   (0x00000400uL)
+#define INTC_ICDISER14_TINT43                   (0x00000800uL)
+#define INTC_ICDISER14_TINT44                   (0x00001000uL)
+#define INTC_ICDISER14_TINT45                   (0x00002000uL)
+#define INTC_ICDISER14_TINT46                   (0x00004000uL)
+#define INTC_ICDISER14_TINT47                   (0x00008000uL)
+#define INTC_ICDISER14_TINT48                   (0x00010000uL)
+#define INTC_ICDISER14_TINT49                   (0x00020000uL)
+#define INTC_ICDISER14_TINT50                   (0x00040000uL)
+#define INTC_ICDISER14_TINT51                   (0x00080000uL)
+#define INTC_ICDISER14_TINT52                   (0x00100000uL)
+#define INTC_ICDISER14_TINT53                   (0x00200000uL)
+#define INTC_ICDISER14_TINT54                   (0x00400000uL)
+#define INTC_ICDISER14_TINT55                   (0x00800000uL)
+#define INTC_ICDISER14_TINT56                   (0x01000000uL)
+#define INTC_ICDISER14_TINT57                   (0x02000000uL)
+#define INTC_ICDISER14_TINT58                   (0x04000000uL)
+#define INTC_ICDISER14_TINT59                   (0x08000000uL)
+#define INTC_ICDISER14_TINT60                   (0x10000000uL)
+#define INTC_ICDISER14_TINT61                   (0x20000000uL)
+#define INTC_ICDISER14_TINT62                   (0x40000000uL)
+#define INTC_ICDISER14_TINT63                   (0x80000000uL)
+
+#define INTC_ICDISER15_TINT64                   (0x00000001uL)
+#define INTC_ICDISER15_TINT65                   (0x00000002uL)
+#define INTC_ICDISER15_TINT66                   (0x00000004uL)
+#define INTC_ICDISER15_TINT67                   (0x00000008uL)
+#define INTC_ICDISER15_TINT68                   (0x00000010uL)
+#define INTC_ICDISER15_TINT69                   (0x00000020uL)
+#define INTC_ICDISER15_TINT70                   (0x00000040uL)
+#define INTC_ICDISER15_TINT71                   (0x00000080uL)
+#define INTC_ICDISER15_TINT72                   (0x00000100uL)
+#define INTC_ICDISER15_TINT73                   (0x00000200uL)
+#define INTC_ICDISER15_TINT74                   (0x00000400uL)
+#define INTC_ICDISER15_TINT75                   (0x00000800uL)
+#define INTC_ICDISER15_TINT76                   (0x00001000uL)
+#define INTC_ICDISER15_TINT77                   (0x00002000uL)
+#define INTC_ICDISER15_TINT78                   (0x00004000uL)
+#define INTC_ICDISER15_TINT79                   (0x00008000uL)
+#define INTC_ICDISER15_TINT80                   (0x00010000uL)
+#define INTC_ICDISER15_TINT81                   (0x00020000uL)
+#define INTC_ICDISER15_TINT82                   (0x00040000uL)
+#define INTC_ICDISER15_TINT83                   (0x00080000uL)
+#define INTC_ICDISER15_TINT84                   (0x00100000uL)
+#define INTC_ICDISER15_TINT85                   (0x00200000uL)
+#define INTC_ICDISER15_TINT86                   (0x00400000uL)
+#define INTC_ICDISER15_TINT87                   (0x00800000uL)
+#define INTC_ICDISER15_TINT88                   (0x01000000uL)
+#define INTC_ICDISER15_TINT89                   (0x02000000uL)
+#define INTC_ICDISER15_TINT90                   (0x04000000uL)
+#define INTC_ICDISER15_TINT91                   (0x08000000uL)
+#define INTC_ICDISER15_TINT92                   (0x10000000uL)
+#define INTC_ICDISER15_TINT93                   (0x20000000uL)
+#define INTC_ICDISER15_TINT94                   (0x40000000uL)
+#define INTC_ICDISER15_TINT95                   (0x80000000uL)
+
+#define INTC_ICDISER16_TINT96                   (0x00000001uL)
+#define INTC_ICDISER16_TINT97                   (0x00000002uL)
+#define INTC_ICDISER16_TINT98                   (0x00000004uL)
+#define INTC_ICDISER16_TINT99                   (0x00000008uL)
+#define INTC_ICDISER16_TINT100                  (0x00000010uL)
+#define INTC_ICDISER16_TINT101                  (0x00000020uL)
+#define INTC_ICDISER16_TINT102                  (0x00000040uL)
+#define INTC_ICDISER16_TINT103                  (0x00000080uL)
+#define INTC_ICDISER16_TINT104                  (0x00000100uL)
+#define INTC_ICDISER16_TINT105                  (0x00000200uL)
+#define INTC_ICDISER16_TINT106                  (0x00000400uL)
+#define INTC_ICDISER16_TINT107                  (0x00000800uL)
+#define INTC_ICDISER16_TINT108                  (0x00001000uL)
+#define INTC_ICDISER16_TINT109                  (0x00002000uL)
+#define INTC_ICDISER16_TINT110                  (0x00004000uL)
+#define INTC_ICDISER16_TINT111                  (0x00008000uL)
+#define INTC_ICDISER16_TINT112                  (0x00010000uL)
+#define INTC_ICDISER16_TINT113                  (0x00020000uL)
+#define INTC_ICDISER16_TINT114                  (0x00040000uL)
+#define INTC_ICDISER16_TINT115                  (0x00080000uL)
+#define INTC_ICDISER16_TINT116                  (0x00100000uL)
+#define INTC_ICDISER16_TINT117                  (0x00200000uL)
+#define INTC_ICDISER16_TINT118                  (0x00400000uL)
+#define INTC_ICDISER16_TINT119                  (0x00800000uL)
+#define INTC_ICDISER16_TINT120                  (0x01000000uL)
+#define INTC_ICDISER16_TINT121                  (0x02000000uL)
+#define INTC_ICDISER16_TINT122                  (0x04000000uL)
+#define INTC_ICDISER16_TINT123                  (0x08000000uL)
+#define INTC_ICDISER16_TINT124                  (0x10000000uL)
+#define INTC_ICDISER16_TINT125                  (0x20000000uL)
+#define INTC_ICDISER16_TINT126                  (0x40000000uL)
+#define INTC_ICDISER16_TINT127                  (0x80000000uL)
+
+#define INTC_ICDISER17_TINT128                  (0x00000001uL)
+#define INTC_ICDISER17_TINT129                  (0x00000002uL)
+#define INTC_ICDISER17_TINT130                  (0x00000004uL)
+#define INTC_ICDISER17_TINT131                  (0x00000008uL)
+#define INTC_ICDISER17_TINT132                  (0x00000010uL)
+#define INTC_ICDISER17_TINT133                  (0x00000020uL)
+#define INTC_ICDISER17_TINT134                  (0x00000040uL)
+#define INTC_ICDISER17_TINT135                  (0x00000080uL)
+#define INTC_ICDISER17_TINT136                  (0x00000100uL)
+#define INTC_ICDISER17_TINT137                  (0x00000200uL)
+#define INTC_ICDISER17_TINT138                  (0x00000400uL)
+#define INTC_ICDISER17_TINT139                  (0x00000800uL)
+#define INTC_ICDISER17_TINT140                  (0x00001000uL)
+#define INTC_ICDISER17_TINT141                  (0x00002000uL)
+#define INTC_ICDISER17_TINT142                  (0x00004000uL)
+#define INTC_ICDISER17_TINT143                  (0x00008000uL)
+#define INTC_ICDISER17_TINT144                  (0x00010000uL)
+#define INTC_ICDISER17_TINT145                  (0x00020000uL)
+#define INTC_ICDISER17_TINT146                  (0x00040000uL)
+#define INTC_ICDISER17_TINT147                  (0x00080000uL)
+#define INTC_ICDISER17_TINT148                  (0x00100000uL)
+#define INTC_ICDISER17_TINT149                  (0x00200000uL)
+#define INTC_ICDISER17_TINT150                  (0x00400000uL)
+#define INTC_ICDISER17_TINT151                  (0x00800000uL)
+#define INTC_ICDISER17_TINT152                  (0x01000000uL)
+#define INTC_ICDISER17_TINT153                  (0x02000000uL)
+#define INTC_ICDISER17_TINT154                  (0x04000000uL)
+#define INTC_ICDISER17_TINT155                  (0x08000000uL)
+#define INTC_ICDISER17_TINT156                  (0x10000000uL)
+#define INTC_ICDISER17_TINT157                  (0x20000000uL)
+#define INTC_ICDISER17_TINT158                  (0x40000000uL)
+#define INTC_ICDISER17_TINT159                  (0x80000000uL)
+
+#define INTC_ICDISER18_TINT160                  (0x00000001uL)
+#define INTC_ICDISER18_TINT161                  (0x00000002uL)
+#define INTC_ICDISER18_TINT162                  (0x00000004uL)
+#define INTC_ICDISER18_TINT163                  (0x00000008uL)
+#define INTC_ICDISER18_TINT164                  (0x00000010uL)
+#define INTC_ICDISER18_TINT165                  (0x00000020uL)
+#define INTC_ICDISER18_TINT166                  (0x00000040uL)
+#define INTC_ICDISER18_TINT167                  (0x00000080uL)
+#define INTC_ICDISER18_TINT168                  (0x00000100uL)
+#define INTC_ICDISER18_TINT169                  (0x00000200uL)
+#define INTC_ICDISER18_TINT170                  (0x00000400uL)
+
+#define INTC_ICDICER0_SW0                       (0x00000001uL)
+#define INTC_ICDICER0_SW1                       (0x00000002uL)
+#define INTC_ICDICER0_SW2                       (0x00000004uL)
+#define INTC_ICDICER0_SW3                       (0x00000008uL)
+#define INTC_ICDICER0_SW4                       (0x00000010uL)
+#define INTC_ICDICER0_SW5                       (0x00000020uL)
+#define INTC_ICDICER0_SW6                       (0x00000040uL)
+#define INTC_ICDICER0_SW7                       (0x00000080uL)
+#define INTC_ICDICER0_SW8                       (0x00000100uL)
+#define INTC_ICDICER0_SW9                       (0x00000200uL)
+#define INTC_ICDICER0_SW10                      (0x00000400uL)
+#define INTC_ICDICER0_SW11                      (0x00000800uL)
+#define INTC_ICDICER0_SW12                      (0x00001000uL)
+#define INTC_ICDICER0_SW13                      (0x00002000uL)
+#define INTC_ICDICER0_SW14                      (0x00004000uL)
+#define INTC_ICDICER0_SW15                      (0x00008000uL)
+#define INTC_ICDICER0_PMUIRQ0                   (0x00010000uL)
+#define INTC_ICDICER0_COMMRX0                   (0x00020000uL)
+#define INTC_ICDICER0_COMMTX0                   (0x00040000uL)
+#define INTC_ICDICER0_CTIIRQ0                   (0x00080000uL)
+
+#define INTC_ICDICER1_IRQ0                      (0x00000001uL)
+#define INTC_ICDICER1_IRQ1                      (0x00000002uL)
+#define INTC_ICDICER1_IRQ2                      (0x00000004uL)
+#define INTC_ICDICER1_IRQ3                      (0x00000008uL)
+#define INTC_ICDICER1_IRQ4                      (0x00000010uL)
+#define INTC_ICDICER1_IRQ5                      (0x00000020uL)
+#define INTC_ICDICER1_IRQ6                      (0x00000040uL)
+#define INTC_ICDICER1_IRQ7                      (0x00000080uL)
+#define INTC_ICDICER1_PL310ERR                  (0x00000100uL)
+#define INTC_ICDICER1_DMAINT0                   (0x00000200uL)
+#define INTC_ICDICER1_DMAINT1                   (0x00000400uL)
+#define INTC_ICDICER1_DMAINT2                   (0x00000800uL)
+#define INTC_ICDICER1_DMAINT3                   (0x00001000uL)
+#define INTC_ICDICER1_DMAINT4                   (0x00002000uL)
+#define INTC_ICDICER1_DMAINT5                   (0x00004000uL)
+#define INTC_ICDICER1_DMAINT6                   (0x00008000uL)
+#define INTC_ICDICER1_DMAINT7                   (0x00010000uL)
+#define INTC_ICDICER1_DMAINT8                   (0x00020000uL)
+#define INTC_ICDICER1_DMAINT9                   (0x00040000uL)
+#define INTC_ICDICER1_DMAINT10                  (0x00080000uL)
+#define INTC_ICDICER1_DMAINT11                  (0x00100000uL)
+#define INTC_ICDICER1_DMAINT12                  (0x00200000uL)
+#define INTC_ICDICER1_DMAINT13                  (0x00400000uL)
+#define INTC_ICDICER1_DMAINT14                  (0x00800000uL)
+#define INTC_ICDICER1_DMAINT15                  (0x01000000uL)
+#define INTC_ICDICER1_DMAERR                    (0x02000000uL)
+
+#define INTC_ICDICER2_USBI0                     (0x00000200uL)
+#define INTC_ICDICER2_USBI1                     (0x00000400uL)
+#define INTC_ICDICER2_S0_VI_VSYNC0              (0x00000800uL)
+#define INTC_ICDICER2_S0_LO_VSYNC0              (0x00001000uL)
+#define INTC_ICDICER2_S0_VSYNCERR0              (0x00002000uL)
+#define INTC_ICDICER2_GR3_VLINE0                (0x00004000uL)
+#define INTC_ICDICER2_S0_VFIELD0                (0x00008000uL)
+#define INTC_ICDICER2_IV1_VBUFERR0              (0x00010000uL)
+#define INTC_ICDICER2_IV3_VBUFERR0              (0x00020000uL)
+#define INTC_ICDICER2_IV5_VBUFERR0              (0x00040000uL)
+#define INTC_ICDICER2_IV6_VBUFERR0              (0x00080000uL)
+#define INTC_ICDICER2_S0_WLINE0                 (0x00100000uL)
+#define INTC_ICDICER2_S1_VI_VSYNC0              (0x00200000uL)
+#define INTC_ICDICER2_S1_LO_VSYNC0              (0x00400000uL)
+#define INTC_ICDICER2_S1_VSYNCERR0              (0x00800000uL)
+#define INTC_ICDICER2_S1_VFIELD0                (0x01000000uL)
+#define INTC_ICDICER2_IV2_VBUFERR0              (0x02000000uL)
+#define INTC_ICDICER2_IV4_VBUFERR0              (0x04000000uL)
+#define INTC_ICDICER2_S1_WLINE0                 (0x08000000uL)
+#define INTC_ICDICER2_OIR_VI_VSYNC0             (0x10000000uL)
+#define INTC_ICDICER2_OIR_LO_VSYNC0             (0x20000000uL)
+#define INTC_ICDICER2_OIR_VSYNCERR0             (0x40000000uL)
+#define INTC_ICDICER2_OIR_VFIELD0               (0x80000000uL)
+
+#define INTC_ICDICER3_IV7_VBUFERR0              (0x00000001uL)
+#define INTC_ICDICER3_IV8_VBUFERR0              (0x00000002uL)
+#define INTC_ICDICER3_S0_VI_VSYNC1              (0x00000008uL)
+#define INTC_ICDICER3_S0_LO_VSYNC1              (0x00000010uL)
+#define INTC_ICDICER3_S0_VSYNCERR1              (0x00000020uL)
+#define INTC_ICDICER3_GR3_VLINE1                (0x00000040uL)
+#define INTC_ICDICER3_S0_VFIELD1                (0x00000080uL)
+#define INTC_ICDICER3_IV1_VBUFERR1              (0x00000100uL)
+#define INTC_ICDICER3_IV3_VBUFERR1              (0x00000200uL)
+#define INTC_ICDICER3_IV5_VBUFERR1              (0x00000400uL)
+#define INTC_ICDICER3_IV6_VBUFERR1              (0x00000800uL)
+#define INTC_ICDICER3_S0_WLINE1                 (0x00001000uL)
+#define INTC_ICDICER3_S1_VI_VSYNC1              (0x00002000uL)
+#define INTC_ICDICER3_S1_LO_VSYNC1              (0x00004000uL)
+#define INTC_ICDICER3_S1_VSYNCERR1              (0x00008000uL)
+#define INTC_ICDICER3_S1_VFIELD1                (0x00010000uL)
+#define INTC_ICDICER3_IV2_VBUFERR1              (0x00020000uL)
+#define INTC_ICDICER3_IV4_VBUFERR1              (0x00040000uL)
+#define INTC_ICDICER3_S1_WLINE1                 (0x00080000uL)
+#define INTC_ICDICER3_OIR_VI_VSYNC1             (0x00100000uL)
+#define INTC_ICDICER3_OIR_LO_VSYNC1             (0x00200000uL)
+#define INTC_ICDICER3_OIR_VLINE1                (0x00400000uL)
+#define INTC_ICDICER3_OIR_VFIELD1               (0x00800000uL)
+#define INTC_ICDICER3_IV7_VBUFERR1              (0x01000000uL)
+#define INTC_ICDICER3_IV8_VBUFERR1              (0x02000000uL)
+#define INTC_ICDICER3_IMRDI                     (0x08000000uL)
+#define INTC_ICDICER3_IMR2I0                    (0x10000000uL)
+#define INTC_ICDICER3_IMR2I1                    (0x20000000uL)
+#define INTC_ICDICER3_JEDI                      (0x40000000uL)
+#define INTC_ICDICER3_JDTI                      (0x80000000uL)
+
+#define INTC_ICDICER4_CMP0                      (0x00000001uL)
+#define INTC_ICDICER4_CMP1                      (0x00000002uL)
+#define INTC_ICDICER4_INT0                      (0x00000004uL)
+#define INTC_ICDICER4_INT1                      (0x00000008uL)
+#define INTC_ICDICER4_INT2                      (0x00000010uL)
+#define INTC_ICDICER4_INT3                      (0x00000020uL)
+#define INTC_ICDICER4_OSTM0TINT                 (0x00000040uL)
+#define INTC_ICDICER4_OSTM1TINT                 (0x00000080uL)
+#define INTC_ICDICER4_CMI                       (0x00000100uL)
+#define INTC_ICDICER4_WTOUT                     (0x00000200uL)
+#define INTC_ICDICER4_ITI                       (0x00000400uL)
+#define INTC_ICDICER4_TGI0A                     (0x00000800uL)
+#define INTC_ICDICER4_TGI0B                     (0x00001000uL)
+#define INTC_ICDICER4_TGI0C                     (0x00002000uL)
+#define INTC_ICDICER4_TGI0D                     (0x00004000uL)
+#define INTC_ICDICER4_TGI0V                     (0x00008000uL)
+#define INTC_ICDICER4_TGI0E                     (0x00010000uL)
+#define INTC_ICDICER4_TGI0F                     (0x00020000uL)
+#define INTC_ICDICER4_TGI1A                     (0x00040000uL)
+#define INTC_ICDICER4_TGI1B                     (0x00080000uL)
+#define INTC_ICDICER4_TGI1V                     (0x00100000uL)
+#define INTC_ICDICER4_TGI1U                     (0x00200000uL)
+#define INTC_ICDICER4_TGI2A                     (0x00400000uL)
+#define INTC_ICDICER4_TGI2B                     (0x00800000uL)
+#define INTC_ICDICER4_TGI2V                     (0x01000000uL)
+#define INTC_ICDICER4_TGI2U                     (0x02000000uL)
+#define INTC_ICDICER4_TGI3A                     (0x04000000uL)
+#define INTC_ICDICER4_TGI3B                     (0x08000000uL)
+#define INTC_ICDICER4_TGI3C                     (0x10000000uL)
+#define INTC_ICDICER4_TGI3D                     (0x20000000uL)
+#define INTC_ICDICER4_TGI3V                     (0x40000000uL)
+#define INTC_ICDICER4_TGI4A                     (0x80000000uL)
+
+#define INTC_ICDICER5_TGI4B                     (0x00000001uL)
+#define INTC_ICDICER5_TGI4C                     (0x00000002uL)
+#define INTC_ICDICER5_TGI4D                     (0x00000004uL)
+#define INTC_ICDICER5_TGI4V                     (0x00000008uL)
+#define INTC_ICDICER5_CMI1                      (0x00000010uL)
+#define INTC_ICDICER5_CMI2                      (0x00000020uL)
+#define INTC_ICDICER5_SGDEI0                    (0x00000040uL)
+#define INTC_ICDICER5_SGDEI1                    (0x00000080uL)
+#define INTC_ICDICER5_SGDEI2                    (0x00000100uL)
+#define INTC_ICDICER5_SGDEI3                    (0x00000200uL)
+#define INTC_ICDICER5_ADI                       (0x00000400uL)
+#define INTC_ICDICER5_LMTI                      (0x00000800uL)
+#define INTC_ICDICER5_SSII0                     (0x00001000uL)
+#define INTC_ICDICER5_SSIRXI0                   (0x00002000uL)
+#define INTC_ICDICER5_SSITXI0                   (0x00004000uL)
+#define INTC_ICDICER5_SSII1                     (0x00008000uL)
+#define INTC_ICDICER5_SSIRXI1                   (0x00010000uL)
+#define INTC_ICDICER5_SSITXI1                   (0x00020000uL)
+#define INTC_ICDICER5_SSII2                     (0x00040000uL)
+#define INTC_ICDICER5_SSIRTI2                   (0x00080000uL)
+#define INTC_ICDICER5_SSII3                     (0x00100000uL)
+#define INTC_ICDICER5_SSIRXI3                   (0x00200000uL)
+#define INTC_ICDICER5_SSITXI3                   (0x00400000uL)
+#define INTC_ICDICER5_SSII4                     (0x00800000uL)
+#define INTC_ICDICER5_SSIRTI4                   (0x01000000uL)
+#define INTC_ICDICER5_SSII5                     (0x02000000uL)
+#define INTC_ICDICER5_SSIRXI5                   (0x04000000uL)
+#define INTC_ICDICER5_SSITXI5                   (0x08000000uL)
+#define INTC_ICDICER5_SPDIFI                    (0x10000000uL)
+#define INTC_ICDICER5_INTIICTEI0                (0x20000000uL)
+#define INTC_ICDICER5_INTIICRI0                 (0x40000000uL)
+#define INTC_ICDICER5_INTIICTI0                 (0x80000000uL)
+
+#define INTC_ICDICER6_INTIICSPI0                (0x00000001uL)
+#define INTC_ICDICER6_INTIICSTI0                (0x00000002uL)
+#define INTC_ICDICER6_INTIICNAKI0               (0x00000004uL)
+#define INTC_ICDICER6_INTIICALI0                (0x00000008uL)
+#define INTC_ICDICER6_INTIICTMOI0               (0x00000010uL)
+#define INTC_ICDICER6_INTIICTEI1                (0x00000020uL)
+#define INTC_ICDICER6_INTIICRI1                 (0x00000040uL)
+#define INTC_ICDICER6_INTIICTI1                 (0x00000080uL)
+#define INTC_ICDICER6_INTIICSPI1                (0x00000100uL)
+#define INTC_ICDICER6_INTIICSTI1                (0x00000200uL)
+#define INTC_ICDICER6_INTIICNAKI1               (0x00000400uL)
+#define INTC_ICDICER6_INTIICALI1                (0x00000800uL)
+#define INTC_ICDICER6_INTIICTMOI1               (0x00001000uL)
+#define INTC_ICDICER6_INTIICTEI2                (0x00002000uL)
+#define INTC_ICDICER6_INTIICRI2                 (0x00004000uL)
+#define INTC_ICDICER6_INTIICTI2                 (0x00008000uL)
+#define INTC_ICDICER6_INTIICSPI2                (0x00010000uL)
+#define INTC_ICDICER6_INTIICSTI2                (0x00020000uL)
+#define INTC_ICDICER6_INTIICNAKI2               (0x00040000uL)
+#define INTC_ICDICER6_INTIICALI2                (0x00080000uL)
+#define INTC_ICDICER6_INTIICTMOI2               (0x00100000uL)
+#define INTC_ICDICER6_INTIICTEI3                (0x00200000uL)
+#define INTC_ICDICER6_INTIICRI3                 (0x00400000uL)
+#define INTC_ICDICER6_INTIICTI3                 (0x00800000uL)
+#define INTC_ICDICER6_INTIICSPI3                (0x01000000uL)
+#define INTC_ICDICER6_INTIICSTI3                (0x02000000uL)
+#define INTC_ICDICER6_INTIICNAKI3               (0x04000000uL)
+#define INTC_ICDICER6_INTIICALI3                (0x08000000uL)
+#define INTC_ICDICER6_INTIICTMOI3               (0x10000000uL)
+#define INTC_ICDICER6_BRI0                      (0x20000000uL)
+#define INTC_ICDICER6_ERI0                      (0x40000000uL)
+#define INTC_ICDICER6_RXI0                      (0x80000000uL)
+
+#define INTC_ICDICER7_TXI0                      (0x00000001uL)
+#define INTC_ICDICER7_BRI1                      (0x00000002uL)
+#define INTC_ICDICER7_ERI1                      (0x00000004uL)
+#define INTC_ICDICER7_RXI1                      (0x00000008uL)
+#define INTC_ICDICER7_TXI1                      (0x00000010uL)
+#define INTC_ICDICER7_BRI2                      (0x00000020uL)
+#define INTC_ICDICER7_ERI2                      (0x00000040uL)
+#define INTC_ICDICER7_RXI2                      (0x00000080uL)
+#define INTC_ICDICER7_TXI2                      (0x00000100uL)
+#define INTC_ICDICER7_BRI3                      (0x00000200uL)
+#define INTC_ICDICER7_ERI3                      (0x00000400uL)
+#define INTC_ICDICER7_RXI3                      (0x00000800uL)
+#define INTC_ICDICER7_TXI3                      (0x00001000uL)
+#define INTC_ICDICER7_BRI4                      (0x00002000uL)
+#define INTC_ICDICER7_ERI4                      (0x00004000uL)
+#define INTC_ICDICER7_RXI4                      (0x00008000uL)
+#define INTC_ICDICER7_TXI4                      (0x00010000uL)
+#define INTC_ICDICER7_BRI5                      (0x00020000uL)
+#define INTC_ICDICER7_ERI5                      (0x00040000uL)
+#define INTC_ICDICER7_RXI5                      (0x00080000uL)
+#define INTC_ICDICER7_TXI5                      (0x00100000uL)
+#define INTC_ICDICER7_BRI6                      (0x00200000uL)
+#define INTC_ICDICER7_ERI6                      (0x00400000uL)
+#define INTC_ICDICER7_RXI6                      (0x00800000uL)
+#define INTC_ICDICER7_TXI6                      (0x01000000uL)
+#define INTC_ICDICER7_BRI7                      (0x02000000uL)
+#define INTC_ICDICER7_ERI7                      (0x04000000uL)
+#define INTC_ICDICER7_RXI7                      (0x08000000uL)
+#define INTC_ICDICER7_TXI7                      (0x10000000uL)
+#define INTC_ICDICER7_INTRCANGERR               (0x20000000uL)
+#define INTC_ICDICER7_INTRCANGRECC              (0x40000000uL)
+#define INTC_ICDICER7_INTRCAN0REC               (0x80000000uL)
+
+#define INTC_ICDICER8_INTRCAN0ERR               (0x00000001uL)
+#define INTC_ICDICER8_INTRCAN0TRX               (0x00000002uL)
+#define INTC_ICDICER8_INTRCAN1REC               (0x00000004uL)
+#define INTC_ICDICER8_INTRCAN1ERR               (0x00000008uL)
+#define INTC_ICDICER8_INTRCAN1TRX               (0x00000010uL)
+#define INTC_ICDICER8_INTRCAN2REC               (0x00000020uL)
+#define INTC_ICDICER8_INTRCAN2ERR               (0x00000040uL)
+#define INTC_ICDICER8_INTRCAN2TRX               (0x00000080uL)
+#define INTC_ICDICER8_INTRCAN3REC               (0x00000100uL)
+#define INTC_ICDICER8_INTRCAN3ERR               (0x00000200uL)
+#define INTC_ICDICER8_INTRCAN3TRX               (0x00000400uL)
+#define INTC_ICDICER8_INTRCAN4REC               (0x00000800uL)
+#define INTC_ICDICER8_INTRCAN4ERR               (0x00001000uL)
+#define INTC_ICDICER8_INTRCAN4TRX               (0x00002000uL)
+#define INTC_ICDICER8_SPEI0                     (0x00004000uL)
+#define INTC_ICDICER8_SPRI0                     (0x00008000uL)
+#define INTC_ICDICER8_SPTI0                     (0x00010000uL)
+#define INTC_ICDICER8_SPEI1                     (0x00020000uL)
+#define INTC_ICDICER8_SPRI1                     (0x00040000uL)
+#define INTC_ICDICER8_SPTI1                     (0x00080000uL)
+#define INTC_ICDICER8_SPEI2                     (0x00100000uL)
+#define INTC_ICDICER8_SPRI2                     (0x00200000uL)
+#define INTC_ICDICER8_SPTI2                     (0x00400000uL)
+#define INTC_ICDICER8_SPEI3                     (0x00800000uL)
+#define INTC_ICDICER8_SPRI3                     (0x01000000uL)
+#define INTC_ICDICER8_SPTI3                     (0x02000000uL)
+#define INTC_ICDICER8_SPEI4                     (0x04000000uL)
+#define INTC_ICDICER8_SPRI4                     (0x08000000uL)
+#define INTC_ICDICER8_SPTI4                     (0x10000000uL)
+#define INTC_ICDICER8_IEBBTD                    (0x20000000uL)
+#define INTC_ICDICER8_IEBBTERR                  (0x40000000uL)
+#define INTC_ICDICER8_IEBBTSTA                  (0x80000000uL)
+
+#define INTC_ICDICER9_IEBBTV                    (0x00000001uL)
+#define INTC_ICDICER9_ISY                       (0x00000002uL)
+#define INTC_ICDICER9_IERR                      (0x00000004uL)
+#define INTC_ICDICER9_ITARG                     (0x00000008uL)
+#define INTC_ICDICER9_ISEC                      (0x00000010uL)
+#define INTC_ICDICER9_IBUF                      (0x00000020uL)
+#define INTC_ICDICER9_IREADY                    (0x00000040uL)
+#define INTC_ICDICER9_FLSTE                     (0x00000080uL)
+#define INTC_ICDICER9_FLTENDI                   (0x00000100uL)
+#define INTC_ICDICER9_FLTREQ0I                  (0x00000200uL)
+#define INTC_ICDICER9_FLTREQ1I                  (0x00000400uL)
+#define INTC_ICDICER9_MMC0                      (0x00000800uL)
+#define INTC_ICDICER9_MMC1                      (0x00001000uL)
+#define INTC_ICDICER9_MMC2                      (0x00002000uL)
+#define INTC_ICDICER9_SDHI0_3                   (0x00004000uL)
+#define INTC_ICDICER9_SDHI0_0                   (0x00008000uL)
+#define INTC_ICDICER9_SDHI0_1                   (0x00010000uL)
+#define INTC_ICDICER9_SDHI1_3                   (0x00020000uL)
+#define INTC_ICDICER9_SDHI1_0                   (0x00040000uL)
+#define INTC_ICDICER9_SDHI1_1                   (0x00080000uL)
+#define INTC_ICDICER9_ARM                       (0x00100000uL)
+#define INTC_ICDICER9_PRD                       (0x00200000uL)
+#define INTC_ICDICER9_CUP                       (0x00400000uL)
+#define INTC_ICDICER9_SCUAI0                    (0x00800000uL)
+#define INTC_ICDICER9_SCUAI1                    (0x01000000uL)
+#define INTC_ICDICER9_SCUFDI0                   (0x02000000uL)
+#define INTC_ICDICER9_SCUFDI1                   (0x04000000uL)
+#define INTC_ICDICER9_SCUFDI2                   (0x08000000uL)
+#define INTC_ICDICER9_SCUFDI3                   (0x10000000uL)
+#define INTC_ICDICER9_SCUFUI0                   (0x20000000uL)
+#define INTC_ICDICER9_SCUFUI1                   (0x40000000uL)
+#define INTC_ICDICER9_SCUFUI2                   (0x80000000uL)
+
+#define INTC_ICDICER10_SCUFUI3                  (0x00000001uL)
+#define INTC_ICDICER10_SCUDVI0                  (0x00000002uL)
+#define INTC_ICDICER10_SCUDVI1                  (0x00000004uL)
+#define INTC_ICDICER10_SCUDVI2                  (0x00000008uL)
+#define INTC_ICDICER10_SCUDVI3                  (0x00000010uL)
+#define INTC_ICDICER10_MLB_CINT                 (0x00000020uL)
+#define INTC_ICDICER10_MLB_SINT                 (0x00000040uL)
+#define INTC_ICDICER10_DRC0                     (0x00000080uL)
+#define INTC_ICDICER10_DRC1                     (0x00000100uL)
+#define INTC_ICDICER10_LINI0_INT_T              (0x00000800uL)
+#define INTC_ICDICER10_LINI0_INT_R              (0x00001000uL)
+#define INTC_ICDICER10_LINI0_INT_S              (0x00002000uL)
+#define INTC_ICDICER10_LINI0_INT_M              (0x00004000uL)
+#define INTC_ICDICER10_LINI1_INT_T              (0x00008000uL)
+#define INTC_ICDICER10_LINI1_INT_R              (0x00010000uL)
+#define INTC_ICDICER10_LINI1_INT_S              (0x00020000uL)
+#define INTC_ICDICER10_LINI1_INT_M              (0x00040000uL)
+#define INTC_ICDICER10_ERI0                     (0x08000000uL)
+#define INTC_ICDICER10_RXI0                     (0x10000000uL)
+#define INTC_ICDICER10_TXI0                     (0x20000000uL)
+#define INTC_ICDICER10_TEI0                     (0x40000000uL)
+#define INTC_ICDICER10_ERI1                     (0x80000000uL)
+
+#define INTC_ICDICER11_RXI1                     (0x00000001uL)
+#define INTC_ICDICER11_TXI1                     (0x00000002uL)
+#define INTC_ICDICER11_TEI1                     (0x00000004uL)
+#define INTC_ICDICER11_AVBI_DATA                (0x00000008uL)
+#define INTC_ICDICER11_AVBI_ERROR               (0x00000010uL)
+#define INTC_ICDICER11_AVBI_MANAGE              (0x00000020uL)
+#define INTC_ICDICER11_AVBI_MAC                 (0x00000040uL)
+#define INTC_ICDICER11_ETHERI                   (0x00000080uL)
+#define INTC_ICDICER11_CEUI                     (0x00001000uL)
+#define INTC_ICDICER11_H2XMLB_ERRINT            (0x20000000uL)
+#define INTC_ICDICER11_H2XIC1_ERRINT            (0x40000000uL)
+#define INTC_ICDICER11_X2HPERI1_ERRINT          (0x80000000uL)
+
+#define INTC_ICDICER12_X2HPERI2_ERRINT          (0x00000001uL)
+#define INTC_ICDICER12_X2HPERI34_ERRINT         (0x00000002uL)
+#define INTC_ICDICER12_X2HPERI5_ERRINT          (0x00000004uL)
+#define INTC_ICDICER12_X2HPERI67_ERRINT         (0x00000008uL)
+#define INTC_ICDICER12_X2HDBGR_ERRINT           (0x00000010uL)
+#define INTC_ICDICER12_X2HBSC_ERRINT            (0x00000020uL)
+#define INTC_ICDICER12_X2HSPI1_ERRINT           (0x00000040uL)
+#define INTC_ICDICER12_X2HSPI2_ERRINT           (0x00000080uL)
+#define INTC_ICDICER12_PRRI                     (0x00000100uL)
+#define INTC_ICDICER12_IFEI0                    (0x00000200uL)
+#define INTC_ICDICER12_OFFI0                    (0x00000400uL)
+#define INTC_ICDICER12_PFVEI0                   (0x00000800uL)
+#define INTC_ICDICER12_IFEI1                    (0x00001000uL)
+#define INTC_ICDICER12_OFFI1                    (0x00002000uL)
+#define INTC_ICDICER12_PFVEI1                   (0x00004000uL)
+
+#define INTC_ICDICER13_TINT0                    (0x00000001uL)
+#define INTC_ICDICER13_TINT1                    (0x00000002uL)
+#define INTC_ICDICER13_TINT2                    (0x00000004uL)
+#define INTC_ICDICER13_TINT3                    (0x00000008uL)
+#define INTC_ICDICER13_TINT4                    (0x00000010uL)
+#define INTC_ICDICER13_TINT5                    (0x00000020uL)
+#define INTC_ICDICER13_TINT6                    (0x00000040uL)
+#define INTC_ICDICER13_TINT7                    (0x00000080uL)
+#define INTC_ICDICER13_TINT8                    (0x00000100uL)
+#define INTC_ICDICER13_TINT9                    (0x00000200uL)
+#define INTC_ICDICER13_TINT10                   (0x00000400uL)
+#define INTC_ICDICER13_TINT11                   (0x00000800uL)
+#define INTC_ICDICER13_TINT12                   (0x00001000uL)
+#define INTC_ICDICER13_TINT13                   (0x00002000uL)
+#define INTC_ICDICER13_TINT14                   (0x00004000uL)
+#define INTC_ICDICER13_TINT15                   (0x00008000uL)
+#define INTC_ICDICER13_TINT16                   (0x00010000uL)
+#define INTC_ICDICER13_TINT17                   (0x00020000uL)
+#define INTC_ICDICER13_TINT18                   (0x00040000uL)
+#define INTC_ICDICER13_TINT19                   (0x00080000uL)
+#define INTC_ICDICER13_TINT20                   (0x00100000uL)
+#define INTC_ICDICER13_TINT21                   (0x00200000uL)
+#define INTC_ICDICER13_TINT22                   (0x00400000uL)
+#define INTC_ICDICER13_TINT23                   (0x00800000uL)
+#define INTC_ICDICER13_TINT24                   (0x01000000uL)
+#define INTC_ICDICER13_TINT25                   (0x02000000uL)
+#define INTC_ICDICER13_TINT26                   (0x04000000uL)
+#define INTC_ICDICER13_TINT27                   (0x08000000uL)
+#define INTC_ICDICER13_TINT28                   (0x10000000uL)
+#define INTC_ICDICER13_TINT29                   (0x20000000uL)
+#define INTC_ICDICER13_TINT30                   (0x40000000uL)
+#define INTC_ICDICER13_TINT31                   (0x80000000uL)
+
+#define INTC_ICDICER14_TINT32                   (0x00000001uL)
+#define INTC_ICDICER14_TINT33                   (0x00000002uL)
+#define INTC_ICDICER14_TINT34                   (0x00000004uL)
+#define INTC_ICDICER14_TINT35                   (0x00000008uL)
+#define INTC_ICDICER14_TINT36                   (0x00000010uL)
+#define INTC_ICDICER14_TINT37                   (0x00000020uL)
+#define INTC_ICDICER14_TINT38                   (0x00000040uL)
+#define INTC_ICDICER14_TINT39                   (0x00000080uL)
+#define INTC_ICDICER14_TINT40                   (0x00000100uL)
+#define INTC_ICDICER14_TINT41                   (0x00000200uL)
+#define INTC_ICDICER14_TINT42                   (0x00000400uL)
+#define INTC_ICDICER14_TINT43                   (0x00000800uL)
+#define INTC_ICDICER14_TINT44                   (0x00001000uL)
+#define INTC_ICDICER14_TINT45                   (0x00002000uL)
+#define INTC_ICDICER14_TINT46                   (0x00004000uL)
+#define INTC_ICDICER14_TINT47                   (0x00008000uL)
+#define INTC_ICDICER14_TINT48                   (0x00010000uL)
+#define INTC_ICDICER14_TINT49                   (0x00020000uL)
+#define INTC_ICDICER14_TINT50                   (0x00040000uL)
+#define INTC_ICDICER14_TINT51                   (0x00080000uL)
+#define INTC_ICDICER14_TINT52                   (0x00100000uL)
+#define INTC_ICDICER14_TINT53                   (0x00200000uL)
+#define INTC_ICDICER14_TINT54                   (0x00400000uL)
+#define INTC_ICDICER14_TINT55                   (0x00800000uL)
+#define INTC_ICDICER14_TINT56                   (0x01000000uL)
+#define INTC_ICDICER14_TINT57                   (0x02000000uL)
+#define INTC_ICDICER14_TINT58                   (0x04000000uL)
+#define INTC_ICDICER14_TINT59                   (0x08000000uL)
+#define INTC_ICDICER14_TINT60                   (0x10000000uL)
+#define INTC_ICDICER14_TINT61                   (0x20000000uL)
+#define INTC_ICDICER14_TINT62                   (0x40000000uL)
+#define INTC_ICDICER14_TINT63                   (0x80000000uL)
+
+#define INTC_ICDICER15_TINT64                   (0x00000001uL)
+#define INTC_ICDICER15_TINT65                   (0x00000002uL)
+#define INTC_ICDICER15_TINT66                   (0x00000004uL)
+#define INTC_ICDICER15_TINT67                   (0x00000008uL)
+#define INTC_ICDICER15_TINT68                   (0x00000010uL)
+#define INTC_ICDICER15_TINT69                   (0x00000020uL)
+#define INTC_ICDICER15_TINT70                   (0x00000040uL)
+#define INTC_ICDICER15_TINT71                   (0x00000080uL)
+#define INTC_ICDICER15_TINT72                   (0x00000100uL)
+#define INTC_ICDICER15_TINT73                   (0x00000200uL)
+#define INTC_ICDICER15_TINT74                   (0x00000400uL)
+#define INTC_ICDICER15_TINT75                   (0x00000800uL)
+#define INTC_ICDICER15_TINT76                   (0x00001000uL)
+#define INTC_ICDICER15_TINT77                   (0x00002000uL)
+#define INTC_ICDICER15_TINT78                   (0x00004000uL)
+#define INTC_ICDICER15_TINT79                   (0x00008000uL)
+#define INTC_ICDICER15_TINT80                   (0x00010000uL)
+#define INTC_ICDICER15_TINT81                   (0x00020000uL)
+#define INTC_ICDICER15_TINT82                   (0x00040000uL)
+#define INTC_ICDICER15_TINT83                   (0x00080000uL)
+#define INTC_ICDICER15_TINT84                   (0x00100000uL)
+#define INTC_ICDICER15_TINT85                   (0x00200000uL)
+#define INTC_ICDICER15_TINT86                   (0x00400000uL)
+#define INTC_ICDICER15_TINT87                   (0x00800000uL)
+#define INTC_ICDICER15_TINT88                   (0x01000000uL)
+#define INTC_ICDICER15_TINT89                   (0x02000000uL)
+#define INTC_ICDICER15_TINT90                   (0x04000000uL)
+#define INTC_ICDICER15_TINT91                   (0x08000000uL)
+#define INTC_ICDICER15_TINT92                   (0x10000000uL)
+#define INTC_ICDICER15_TINT93                   (0x20000000uL)
+#define INTC_ICDICER15_TINT94                   (0x40000000uL)
+#define INTC_ICDICER15_TINT95                   (0x80000000uL)
+
+#define INTC_ICDICER16_TINT96                   (0x00000001uL)
+#define INTC_ICDICER16_TINT97                   (0x00000002uL)
+#define INTC_ICDICER16_TINT98                   (0x00000004uL)
+#define INTC_ICDICER16_TINT99                   (0x00000008uL)
+#define INTC_ICDICER16_TINT100                  (0x00000010uL)
+#define INTC_ICDICER16_TINT101                  (0x00000020uL)
+#define INTC_ICDICER16_TINT102                  (0x00000040uL)
+#define INTC_ICDICER16_TINT103                  (0x00000080uL)
+#define INTC_ICDICER16_TINT104                  (0x00000100uL)
+#define INTC_ICDICER16_TINT105                  (0x00000200uL)
+#define INTC_ICDICER16_TINT106                  (0x00000400uL)
+#define INTC_ICDICER16_TINT107                  (0x00000800uL)
+#define INTC_ICDICER16_TINT108                  (0x00001000uL)
+#define INTC_ICDICER16_TINT109                  (0x00002000uL)
+#define INTC_ICDICER16_TINT110                  (0x00004000uL)
+#define INTC_ICDICER16_TINT111                  (0x00008000uL)
+#define INTC_ICDICER16_TINT112                  (0x00010000uL)
+#define INTC_ICDICER16_TINT113                  (0x00020000uL)
+#define INTC_ICDICER16_TINT114                  (0x00040000uL)
+#define INTC_ICDICER16_TINT115                  (0x00080000uL)
+#define INTC_ICDICER16_TINT116                  (0x00100000uL)
+#define INTC_ICDICER16_TINT117                  (0x00200000uL)
+#define INTC_ICDICER16_TINT118                  (0x00400000uL)
+#define INTC_ICDICER16_TINT119                  (0x00800000uL)
+#define INTC_ICDICER16_TINT120                  (0x01000000uL)
+#define INTC_ICDICER16_TINT121                  (0x02000000uL)
+#define INTC_ICDICER16_TINT122                  (0x04000000uL)
+#define INTC_ICDICER16_TINT123                  (0x08000000uL)
+#define INTC_ICDICER16_TINT124                  (0x10000000uL)
+#define INTC_ICDICER16_TINT125                  (0x20000000uL)
+#define INTC_ICDICER16_TINT126                  (0x40000000uL)
+#define INTC_ICDICER16_TINT127                  (0x80000000uL)
+
+#define INTC_ICDICER17_TINT128                  (0x00000001uL)
+#define INTC_ICDICER17_TINT129                  (0x00000002uL)
+#define INTC_ICDICER17_TINT130                  (0x00000004uL)
+#define INTC_ICDICER17_TINT131                  (0x00000008uL)
+#define INTC_ICDICER17_TINT132                  (0x00000010uL)
+#define INTC_ICDICER17_TINT133                  (0x00000020uL)
+#define INTC_ICDICER17_TINT134                  (0x00000040uL)
+#define INTC_ICDICER17_TINT135                  (0x00000080uL)
+#define INTC_ICDICER17_TINT136                  (0x00000100uL)
+#define INTC_ICDICER17_TINT137                  (0x00000200uL)
+#define INTC_ICDICER17_TINT138                  (0x00000400uL)
+#define INTC_ICDICER17_TINT139                  (0x00000800uL)
+#define INTC_ICDICER17_TINT140                  (0x00001000uL)
+#define INTC_ICDICER17_TINT141                  (0x00002000uL)
+#define INTC_ICDICER17_TINT142                  (0x00004000uL)
+#define INTC_ICDICER17_TINT143                  (0x00008000uL)
+#define INTC_ICDICER17_TINT144                  (0x00010000uL)
+#define INTC_ICDICER17_TINT145                  (0x00020000uL)
+#define INTC_ICDICER17_TINT146                  (0x00040000uL)
+#define INTC_ICDICER17_TINT147                  (0x00080000uL)
+#define INTC_ICDICER17_TINT148                  (0x00100000uL)
+#define INTC_ICDICER17_TINT149                  (0x00200000uL)
+#define INTC_ICDICER17_TINT150                  (0x00400000uL)
+#define INTC_ICDICER17_TINT151                  (0x00800000uL)
+#define INTC_ICDICER17_TINT152                  (0x01000000uL)
+#define INTC_ICDICER17_TINT153                  (0x02000000uL)
+#define INTC_ICDICER17_TINT154                  (0x04000000uL)
+#define INTC_ICDICER17_TINT155                  (0x08000000uL)
+#define INTC_ICDICER17_TINT156                  (0x10000000uL)
+#define INTC_ICDICER17_TINT157                  (0x20000000uL)
+#define INTC_ICDICER17_TINT158                  (0x40000000uL)
+#define INTC_ICDICER17_TINT159                  (0x80000000uL)
+
+#define INTC_ICDICER18_TINT160                  (0x00000001uL)
+#define INTC_ICDICER18_TINT161                  (0x00000002uL)
+#define INTC_ICDICER18_TINT162                  (0x00000004uL)
+#define INTC_ICDICER18_TINT163                  (0x00000008uL)
+#define INTC_ICDICER18_TINT164                  (0x00000010uL)
+#define INTC_ICDICER18_TINT165                  (0x00000020uL)
+#define INTC_ICDICER18_TINT166                  (0x00000040uL)
+#define INTC_ICDICER18_TINT167                  (0x00000080uL)
+#define INTC_ICDICER18_TINT168                  (0x00000100uL)
+#define INTC_ICDICER18_TINT169                  (0x00000200uL)
+#define INTC_ICDICER18_TINT170                  (0x00000400uL)
+
+#define INTC_ICDISPR0_SW0                       (0x00000001uL)
+#define INTC_ICDISPR0_SW1                       (0x00000002uL)
+#define INTC_ICDISPR0_SW2                       (0x00000004uL)
+#define INTC_ICDISPR0_SW3                       (0x00000008uL)
+#define INTC_ICDISPR0_SW4                       (0x00000010uL)
+#define INTC_ICDISPR0_SW5                       (0x00000020uL)
+#define INTC_ICDISPR0_SW6                       (0x00000040uL)
+#define INTC_ICDISPR0_SW7                       (0x00000080uL)
+#define INTC_ICDISPR0_SW8                       (0x00000100uL)
+#define INTC_ICDISPR0_SW9                       (0x00000200uL)
+#define INTC_ICDISPR0_SW10                      (0x00000400uL)
+#define INTC_ICDISPR0_SW11                      (0x00000800uL)
+#define INTC_ICDISPR0_SW12                      (0x00001000uL)
+#define INTC_ICDISPR0_SW13                      (0x00002000uL)
+#define INTC_ICDISPR0_SW14                      (0x00004000uL)
+#define INTC_ICDISPR0_SW15                      (0x00008000uL)
+#define INTC_ICDISPR0_PMUIRQ0                   (0x00010000uL)
+#define INTC_ICDISPR0_COMMRX0                   (0x00020000uL)
+#define INTC_ICDISPR0_COMMTX0                   (0x00040000uL)
+#define INTC_ICDISPR0_CTIIRQ0                   (0x00080000uL)
+
+#define INTC_ICDISPR1_IRQ0                      (0x00000001uL)
+#define INTC_ICDISPR1_IRQ1                      (0x00000002uL)
+#define INTC_ICDISPR1_IRQ2                      (0x00000004uL)
+#define INTC_ICDISPR1_IRQ3                      (0x00000008uL)
+#define INTC_ICDISPR1_IRQ4                      (0x00000010uL)
+#define INTC_ICDISPR1_IRQ5                      (0x00000020uL)
+#define INTC_ICDISPR1_IRQ6                      (0x00000040uL)
+#define INTC_ICDISPR1_IRQ7                      (0x00000080uL)
+#define INTC_ICDISPR1_PL310ERR                  (0x00000100uL)
+#define INTC_ICDISPR1_DMAINT0                   (0x00000200uL)
+#define INTC_ICDISPR1_DMAINT1                   (0x00000400uL)
+#define INTC_ICDISPR1_DMAINT2                   (0x00000800uL)
+#define INTC_ICDISPR1_DMAINT3                   (0x00001000uL)
+#define INTC_ICDISPR1_DMAINT4                   (0x00002000uL)
+#define INTC_ICDISPR1_DMAINT5                   (0x00004000uL)
+#define INTC_ICDISPR1_DMAINT6                   (0x00008000uL)
+#define INTC_ICDISPR1_DMAINT7                   (0x00010000uL)
+#define INTC_ICDISPR1_DMAINT8                   (0x00020000uL)
+#define INTC_ICDISPR1_DMAINT9                   (0x00040000uL)
+#define INTC_ICDISPR1_DMAINT10                  (0x00080000uL)
+#define INTC_ICDISPR1_DMAINT11                  (0x00100000uL)
+#define INTC_ICDISPR1_DMAINT12                  (0x00200000uL)
+#define INTC_ICDISPR1_DMAINT13                  (0x00400000uL)
+#define INTC_ICDISPR1_DMAINT14                  (0x00800000uL)
+#define INTC_ICDISPR1_DMAINT15                  (0x01000000uL)
+#define INTC_ICDISPR1_DMAERR                    (0x02000000uL)
+
+#define INTC_ICDISPR2_USBI0                     (0x00000200uL)
+#define INTC_ICDISPR2_USBI1                     (0x00000400uL)
+#define INTC_ICDISPR2_S0_VI_VSYNC0              (0x00000800uL)
+#define INTC_ICDISPR2_S0_LO_VSYNC0              (0x00001000uL)
+#define INTC_ICDISPR2_S0_VSYNCERR0              (0x00002000uL)
+#define INTC_ICDISPR2_GR3_VLINE0                (0x00004000uL)
+#define INTC_ICDISPR2_S0_VFIELD0                (0x00008000uL)
+#define INTC_ICDISPR2_IV1_VBUFERR0              (0x00010000uL)
+#define INTC_ICDISPR2_IV3_VBUFERR0              (0x00020000uL)
+#define INTC_ICDISPR2_IV5_VBUFERR0              (0x00040000uL)
+#define INTC_ICDISPR2_IV6_VBUFERR0              (0x00080000uL)
+#define INTC_ICDISPR2_S0_WLINE0                 (0x00100000uL)
+#define INTC_ICDISPR2_S1_VI_VSYNC0              (0x00200000uL)
+#define INTC_ICDISPR2_S1_LO_VSYNC0              (0x00400000uL)
+#define INTC_ICDISPR2_S1_VSYNCERR0              (0x00800000uL)
+#define INTC_ICDISPR2_S1_VFIELD0                (0x01000000uL)
+#define INTC_ICDISPR2_IV2_VBUFERR0              (0x02000000uL)
+#define INTC_ICDISPR2_IV4_VBUFERR0              (0x04000000uL)
+#define INTC_ICDISPR2_S1_WLINE0                 (0x08000000uL)
+#define INTC_ICDISPR2_OIR_VI_VSYNC0             (0x10000000uL)
+#define INTC_ICDISPR2_OIR_LO_VSYNC0             (0x20000000uL)
+#define INTC_ICDISPR2_OIR_VSYNCERR0             (0x40000000uL)
+#define INTC_ICDISPR2_OIR_VFIELD0               (0x80000000uL)
+
+#define INTC_ICDISPR3_IV7_VBUFERR0              (0x00000001uL)
+#define INTC_ICDISPR3_IV8_VBUFERR0              (0x00000002uL)
+#define INTC_ICDISPR3_S0_VI_VSYNC1              (0x00000008uL)
+#define INTC_ICDISPR3_S0_LO_VSYNC1              (0x00000010uL)
+#define INTC_ICDISPR3_S0_VSYNCERR1              (0x00000020uL)
+#define INTC_ICDISPR3_GR3_VLINE1                (0x00000040uL)
+#define INTC_ICDISPR3_S0_VFIELD1                (0x00000080uL)
+#define INTC_ICDISPR3_IV1_VBUFERR1              (0x00000100uL)
+#define INTC_ICDISPR3_IV3_VBUFERR1              (0x00000200uL)
+#define INTC_ICDISPR3_IV5_VBUFERR1              (0x00000400uL)
+#define INTC_ICDISPR3_IV6_VBUFERR1              (0x00000800uL)
+#define INTC_ICDISPR3_S0_WLINE1                 (0x00001000uL)
+#define INTC_ICDISPR3_S1_VI_VSYNC1              (0x00002000uL)
+#define INTC_ICDISPR3_S1_LO_VSYNC1              (0x00004000uL)
+#define INTC_ICDISPR3_S1_VSYNCERR1              (0x00008000uL)
+#define INTC_ICDISPR3_S1_VFIELD1                (0x00010000uL)
+#define INTC_ICDISPR3_IV2_VBUFERR1              (0x00020000uL)
+#define INTC_ICDISPR3_IV4_VBUFERR1              (0x00040000uL)
+#define INTC_ICDISPR3_S1_WLINE1                 (0x00080000uL)
+#define INTC_ICDISPR3_OIR_VI_VSYNC1             (0x00100000uL)
+#define INTC_ICDISPR3_OIR_LO_VSYNC1             (0x00200000uL)
+#define INTC_ICDISPR3_OIR_VLINE1                (0x00400000uL)
+#define INTC_ICDISPR3_OIR_VFIELD1               (0x00800000uL)
+#define INTC_ICDISPR3_IV7_VBUFERR1              (0x01000000uL)
+#define INTC_ICDISPR3_IV8_VBUFERR1              (0x02000000uL)
+#define INTC_ICDISPR3_IMRDI                     (0x08000000uL)
+#define INTC_ICDISPR3_IMR2I0                    (0x10000000uL)
+#define INTC_ICDISPR3_IMR2I1                    (0x20000000uL)
+#define INTC_ICDISPR3_JEDI                      (0x40000000uL)
+#define INTC_ICDISPR3_JDTI                      (0x80000000uL)
+
+#define INTC_ICDISPR4_CMP0                      (0x00000001uL)
+#define INTC_ICDISPR4_CMP1                      (0x00000002uL)
+#define INTC_ICDISPR4_INT0                      (0x00000004uL)
+#define INTC_ICDISPR4_INT1                      (0x00000008uL)
+#define INTC_ICDISPR4_INT2                      (0x00000010uL)
+#define INTC_ICDISPR4_INT3                      (0x00000020uL)
+#define INTC_ICDISPR4_OSTM0TINT                 (0x00000040uL)
+#define INTC_ICDISPR4_OSTM1TINT                 (0x00000080uL)
+#define INTC_ICDISPR4_CMI                       (0x00000100uL)
+#define INTC_ICDISPR4_WTOUT                     (0x00000200uL)
+#define INTC_ICDISPR4_ITI                       (0x00000400uL)
+#define INTC_ICDISPR4_TGI0A                     (0x00000800uL)
+#define INTC_ICDISPR4_TGI0B                     (0x00001000uL)
+#define INTC_ICDISPR4_TGI0C                     (0x00002000uL)
+#define INTC_ICDISPR4_TGI0D                     (0x00004000uL)
+#define INTC_ICDISPR4_TGI0V                     (0x00008000uL)
+#define INTC_ICDISPR4_TGI0E                     (0x00010000uL)
+#define INTC_ICDISPR4_TGI0F                     (0x00020000uL)
+#define INTC_ICDISPR4_TGI1A                     (0x00040000uL)
+#define INTC_ICDISPR4_TGI1B                     (0x00080000uL)
+#define INTC_ICDISPR4_TGI1V                     (0x00100000uL)
+#define INTC_ICDISPR4_TGI1U                     (0x00200000uL)
+#define INTC_ICDISPR4_TGI2A                     (0x00400000uL)
+#define INTC_ICDISPR4_TGI2B                     (0x00800000uL)
+#define INTC_ICDISPR4_TGI2V                     (0x01000000uL)
+#define INTC_ICDISPR4_TGI2U                     (0x02000000uL)
+#define INTC_ICDISPR4_TGI3A                     (0x04000000uL)
+#define INTC_ICDISPR4_TGI3B                     (0x08000000uL)
+#define INTC_ICDISPR4_TGI3C                     (0x10000000uL)
+#define INTC_ICDISPR4_TGI3D                     (0x20000000uL)
+#define INTC_ICDISPR4_TGI3V                     (0x40000000uL)
+#define INTC_ICDISPR4_TGI4A                     (0x80000000uL)
+
+#define INTC_ICDISPR5_TGI4B                     (0x00000001uL)
+#define INTC_ICDISPR5_TGI4C                     (0x00000002uL)
+#define INTC_ICDISPR5_TGI4D                     (0x00000004uL)
+#define INTC_ICDISPR5_TGI4V                     (0x00000008uL)
+#define INTC_ICDISPR5_CMI1                      (0x00000010uL)
+#define INTC_ICDISPR5_CMI2                      (0x00000020uL)
+#define INTC_ICDISPR5_SGDEI0                    (0x00000040uL)
+#define INTC_ICDISPR5_SGDEI1                    (0x00000080uL)
+#define INTC_ICDISPR5_SGDEI2                    (0x00000100uL)
+#define INTC_ICDISPR5_SGDEI3                    (0x00000200uL)
+#define INTC_ICDISPR5_ADI                       (0x00000400uL)
+#define INTC_ICDISPR5_LMTI                      (0x00000800uL)
+#define INTC_ICDISPR5_SSII0                     (0x00001000uL)
+#define INTC_ICDISPR5_SSIRXI0                   (0x00002000uL)
+#define INTC_ICDISPR5_SSITXI0                   (0x00004000uL)
+#define INTC_ICDISPR5_SSII1                     (0x00008000uL)
+#define INTC_ICDISPR5_SSIRXI1                   (0x00010000uL)
+#define INTC_ICDISPR5_SSITXI1                   (0x00020000uL)
+#define INTC_ICDISPR5_SSII2                     (0x00040000uL)
+#define INTC_ICDISPR5_SSIRTI2                   (0x00080000uL)
+#define INTC_ICDISPR5_SSII3                     (0x00100000uL)
+#define INTC_ICDISPR5_SSIRXI3                   (0x00200000uL)
+#define INTC_ICDISPR5_SSITXI3                   (0x00400000uL)
+#define INTC_ICDISPR5_SSII4                     (0x00800000uL)
+#define INTC_ICDISPR5_SSIRTI4                   (0x01000000uL)
+#define INTC_ICDISPR5_SSII5                     (0x02000000uL)
+#define INTC_ICDISPR5_SSIRXI5                   (0x04000000uL)
+#define INTC_ICDISPR5_SSITXI5                   (0x08000000uL)
+#define INTC_ICDISPR5_SPDIFI                    (0x10000000uL)
+#define INTC_ICDISPR5_INTIICTEI0                (0x20000000uL)
+#define INTC_ICDISPR5_INTIICRI0                 (0x40000000uL)
+#define INTC_ICDISPR5_INTIICTI0                 (0x80000000uL)
+
+#define INTC_ICDISPR6_INTIICSPI0                (0x00000001uL)
+#define INTC_ICDISPR6_INTIICSTI0                (0x00000002uL)
+#define INTC_ICDISPR6_INTIICNAKI0               (0x00000004uL)
+#define INTC_ICDISPR6_INTIICALI0                (0x00000008uL)
+#define INTC_ICDISPR6_INTIICTMOI0               (0x00000010uL)
+#define INTC_ICDISPR6_INTIICTEI1                (0x00000020uL)
+#define INTC_ICDISPR6_INTIICRI1                 (0x00000040uL)
+#define INTC_ICDISPR6_INTIICTI1                 (0x00000080uL)
+#define INTC_ICDISPR6_INTIICSPI1                (0x00000100uL)
+#define INTC_ICDISPR6_INTIICSTI1                (0x00000200uL)
+#define INTC_ICDISPR6_INTIICNAKI1               (0x00000400uL)
+#define INTC_ICDISPR6_INTIICALI1                (0x00000800uL)
+#define INTC_ICDISPR6_INTIICTMOI1               (0x00001000uL)
+#define INTC_ICDISPR6_INTIICTEI2                (0x00002000uL)
+#define INTC_ICDISPR6_INTIICRI2                 (0x00004000uL)
+#define INTC_ICDISPR6_INTIICTI2                 (0x00008000uL)
+#define INTC_ICDISPR6_INTIICSPI2                (0x00010000uL)
+#define INTC_ICDISPR6_INTIICSTI2                (0x00020000uL)
+#define INTC_ICDISPR6_INTIICNAKI2               (0x00040000uL)
+#define INTC_ICDISPR6_INTIICALI2                (0x00080000uL)
+#define INTC_ICDISPR6_INTIICTMOI2               (0x00100000uL)
+#define INTC_ICDISPR6_INTIICTEI3                (0x00200000uL)
+#define INTC_ICDISPR6_INTIICRI3                 (0x00400000uL)
+#define INTC_ICDISPR6_INTIICTI3                 (0x00800000uL)
+#define INTC_ICDISPR6_INTIICSPI3                (0x01000000uL)
+#define INTC_ICDISPR6_INTIICSTI3                (0x02000000uL)
+#define INTC_ICDISPR6_INTIICNAKI3               (0x04000000uL)
+#define INTC_ICDISPR6_INTIICALI3                (0x08000000uL)
+#define INTC_ICDISPR6_INTIICTMOI3               (0x10000000uL)
+#define INTC_ICDISPR6_BRI0                      (0x20000000uL)
+#define INTC_ICDISPR6_ERI0                      (0x40000000uL)
+#define INTC_ICDISPR6_RXI0                      (0x80000000uL)
+
+#define INTC_ICDISPR7_TXI0                      (0x00000001uL)
+#define INTC_ICDISPR7_BRI1                      (0x00000002uL)
+#define INTC_ICDISPR7_ERI1                      (0x00000004uL)
+#define INTC_ICDISPR7_RXI1                      (0x00000008uL)
+#define INTC_ICDISPR7_TXI1                      (0x00000010uL)
+#define INTC_ICDISPR7_BRI2                      (0x00000020uL)
+#define INTC_ICDISPR7_ERI2                      (0x00000040uL)
+#define INTC_ICDISPR7_RXI2                      (0x00000080uL)
+#define INTC_ICDISPR7_TXI2                      (0x00000100uL)
+#define INTC_ICDISPR7_BRI3                      (0x00000200uL)
+#define INTC_ICDISPR7_ERI3                      (0x00000400uL)
+#define INTC_ICDISPR7_RXI3                      (0x00000800uL)
+#define INTC_ICDISPR7_TXI3                      (0x00001000uL)
+#define INTC_ICDISPR7_BRI4                      (0x00002000uL)
+#define INTC_ICDISPR7_ERI4                      (0x00004000uL)
+#define INTC_ICDISPR7_RXI4                      (0x00008000uL)
+#define INTC_ICDISPR7_TXI4                      (0x00010000uL)
+#define INTC_ICDISPR7_BRI5                      (0x00020000uL)
+#define INTC_ICDISPR7_ERI5                      (0x00040000uL)
+#define INTC_ICDISPR7_RXI5                      (0x00080000uL)
+#define INTC_ICDISPR7_TXI5                      (0x00100000uL)
+#define INTC_ICDISPR7_BRI6                      (0x00200000uL)
+#define INTC_ICDISPR7_ERI6                      (0x00400000uL)
+#define INTC_ICDISPR7_RXI6                      (0x00800000uL)
+#define INTC_ICDISPR7_TXI6                      (0x01000000uL)
+#define INTC_ICDISPR7_BRI7                      (0x02000000uL)
+#define INTC_ICDISPR7_ERI7                      (0x04000000uL)
+#define INTC_ICDISPR7_RXI7                      (0x08000000uL)
+#define INTC_ICDISPR7_TXI7                      (0x10000000uL)
+#define INTC_ICDISPR7_INTRCANGERR               (0x20000000uL)
+#define INTC_ICDISPR7_INTRCANGRECC              (0x40000000uL)
+#define INTC_ICDISPR7_INTRCAN0REC               (0x80000000uL)
+
+#define INTC_ICDISPR8_INTRCAN0ERR               (0x00000001uL)
+#define INTC_ICDISPR8_INTRCAN0TRX               (0x00000002uL)
+#define INTC_ICDISPR8_INTRCAN1REC               (0x00000004uL)
+#define INTC_ICDISPR8_INTRCAN1ERR               (0x00000008uL)
+#define INTC_ICDISPR8_INTRCAN1TRX               (0x00000010uL)
+#define INTC_ICDISPR8_INTRCAN2REC               (0x00000020uL)
+#define INTC_ICDISPR8_INTRCAN2ERR               (0x00000040uL)
+#define INTC_ICDISPR8_INTRCAN2TRX               (0x00000080uL)
+#define INTC_ICDISPR8_INTRCAN3REC               (0x00000100uL)
+#define INTC_ICDISPR8_INTRCAN3ERR               (0x00000200uL)
+#define INTC_ICDISPR8_INTRCAN3TRX               (0x00000400uL)
+#define INTC_ICDISPR8_INTRCAN4REC               (0x00000800uL)
+#define INTC_ICDISPR8_INTRCAN4ERR               (0x00001000uL)
+#define INTC_ICDISPR8_INTRCAN4TRX               (0x00002000uL)
+#define INTC_ICDISPR8_SPEI0                     (0x00004000uL)
+#define INTC_ICDISPR8_SPRI0                     (0x00008000uL)
+#define INTC_ICDISPR8_SPTI0                     (0x00010000uL)
+#define INTC_ICDISPR8_SPEI1                     (0x00020000uL)
+#define INTC_ICDISPR8_SPRI1                     (0x00040000uL)
+#define INTC_ICDISPR8_SPTI1                     (0x00080000uL)
+#define INTC_ICDISPR8_SPEI2                     (0x00100000uL)
+#define INTC_ICDISPR8_SPRI2                     (0x00200000uL)
+#define INTC_ICDISPR8_SPTI2                     (0x00400000uL)
+#define INTC_ICDISPR8_SPEI3                     (0x00800000uL)
+#define INTC_ICDISPR8_SPRI3                     (0x01000000uL)
+#define INTC_ICDISPR8_SPTI3                     (0x02000000uL)
+#define INTC_ICDISPR8_SPEI4                     (0x04000000uL)
+#define INTC_ICDISPR8_SPRI4                     (0x08000000uL)
+#define INTC_ICDISPR8_SPTI4                     (0x10000000uL)
+#define INTC_ICDISPR8_IEBBTD                    (0x20000000uL)
+#define INTC_ICDISPR8_IEBBTERR                  (0x40000000uL)
+#define INTC_ICDISPR8_IEBBTSTA                  (0x80000000uL)
+
+#define INTC_ICDISPR9_IEBBTV                    (0x00000001uL)
+#define INTC_ICDISPR9_ISY                       (0x00000002uL)
+#define INTC_ICDISPR9_IERR                      (0x00000004uL)
+#define INTC_ICDISPR9_ITARG                     (0x00000008uL)
+#define INTC_ICDISPR9_ISEC                      (0x00000010uL)
+#define INTC_ICDISPR9_IBUF                      (0x00000020uL)
+#define INTC_ICDISPR9_IREADY                    (0x00000040uL)
+#define INTC_ICDISPR9_FLSTE                     (0x00000080uL)
+#define INTC_ICDISPR9_FLTENDI                   (0x00000100uL)
+#define INTC_ICDISPR9_FLTREQ0I                  (0x00000200uL)
+#define INTC_ICDISPR9_FLTREQ1I                  (0x00000400uL)
+#define INTC_ICDISPR9_MMC0                      (0x00000800uL)
+#define INTC_ICDISPR9_MMC1                      (0x00001000uL)
+#define INTC_ICDISPR9_MMC2                      (0x00002000uL)
+#define INTC_ICDISPR9_SDHI0_3                   (0x00004000uL)
+#define INTC_ICDISPR9_SDHI0_0                   (0x00008000uL)
+#define INTC_ICDISPR9_SDHI0_1                   (0x00010000uL)
+#define INTC_ICDISPR9_SDHI1_3                   (0x00020000uL)
+#define INTC_ICDISPR9_SDHI1_0                   (0x00040000uL)
+#define INTC_ICDISPR9_SDHI1_1                   (0x00080000uL)
+#define INTC_ICDISPR9_ARM                       (0x00100000uL)
+#define INTC_ICDISPR9_PRD                       (0x00200000uL)
+#define INTC_ICDISPR9_CUP                       (0x00400000uL)
+#define INTC_ICDISPR9_SCUAI0                    (0x00800000uL)
+#define INTC_ICDISPR9_SCUAI1                    (0x01000000uL)
+#define INTC_ICDISPR9_SCUFDI0                   (0x02000000uL)
+#define INTC_ICDISPR9_SCUFDI1                   (0x04000000uL)
+#define INTC_ICDISPR9_SCUFDI2                   (0x08000000uL)
+#define INTC_ICDISPR9_SCUFDI3                   (0x10000000uL)
+#define INTC_ICDISPR9_SCUFUI0                   (0x20000000uL)
+#define INTC_ICDISPR9_SCUFUI1                   (0x40000000uL)
+#define INTC_ICDISPR9_SCUFUI2                   (0x80000000uL)
+
+#define INTC_ICDISPR10_SCUFUI3                  (0x00000001uL)
+#define INTC_ICDISPR10_SCUDVI0                  (0x00000002uL)
+#define INTC_ICDISPR10_SCUDVI1                  (0x00000004uL)
+#define INTC_ICDISPR10_SCUDVI2                  (0x00000008uL)
+#define INTC_ICDISPR10_SCUDVI3                  (0x00000010uL)
+#define INTC_ICDISPR10_MLB_CINT                 (0x00000020uL)
+#define INTC_ICDISPR10_MLB_SINT                 (0x00000040uL)
+#define INTC_ICDISPR10_DRC0                     (0x00000080uL)
+#define INTC_ICDISPR10_DRC1                     (0x00000100uL)
+#define INTC_ICDISPR10_LINI0_INT_T              (0x00000800uL)
+#define INTC_ICDISPR10_LINI0_INT_R              (0x00001000uL)
+#define INTC_ICDISPR10_LINI0_INT_S              (0x00002000uL)
+#define INTC_ICDISPR10_LINI0_INT_M              (0x00004000uL)
+#define INTC_ICDISPR10_LINI1_INT_T              (0x00008000uL)
+#define INTC_ICDISPR10_LINI1_INT_R              (0x00010000uL)
+#define INTC_ICDISPR10_LINI1_INT_S              (0x00020000uL)
+#define INTC_ICDISPR10_LINI1_INT_M              (0x00040000uL)
+#define INTC_ICDISPR10_ERI0                     (0x08000000uL)
+#define INTC_ICDISPR10_RXI0                     (0x10000000uL)
+#define INTC_ICDISPR10_TXI0                     (0x20000000uL)
+#define INTC_ICDISPR10_TEI0                     (0x40000000uL)
+#define INTC_ICDISPR10_ERI1                     (0x80000000uL)
+
+#define INTC_ICDISPR11_RXI1                     (0x00000001uL)
+#define INTC_ICDISPR11_TXI1                     (0x00000002uL)
+#define INTC_ICDISPR11_TEI1                     (0x00000004uL)
+#define INTC_ICDISPR11_AVBI_DATA                (0x00000008uL)
+#define INTC_ICDISPR11_AVBI_ERROR               (0x00000010uL)
+#define INTC_ICDISPR11_AVBI_MANAGE              (0x00000020uL)
+#define INTC_ICDISPR11_AVBI_MAC                 (0x00000040uL)
+#define INTC_ICDISPR11_ETHERI                   (0x00000080uL)
+#define INTC_ICDISPR11_CEUI                     (0x00001000uL)
+#define INTC_ICDISPR11_H2XMLB_ERRINT            (0x20000000uL)
+#define INTC_ICDISPR11_H2XIC1_ERRINT            (0x40000000uL)
+#define INTC_ICDISPR11_X2HPERI1_ERRINT          (0x80000000uL)
+
+#define INTC_ICDISPR12_X2HPERI2_ERRINT          (0x00000001uL)
+#define INTC_ICDISPR12_X2HPERI34_ERRINT         (0x00000002uL)
+#define INTC_ICDISPR12_X2HPERI5_ERRINT          (0x00000004uL)
+#define INTC_ICDISPR12_X2HPERI67_ERRINT         (0x00000008uL)
+#define INTC_ICDISPR12_X2HDBGR_ERRINT           (0x00000010uL)
+#define INTC_ICDISPR12_X2HBSC_ERRINT            (0x00000020uL)
+#define INTC_ICDISPR12_X2HSPI1_ERRINT           (0x00000040uL)
+#define INTC_ICDISPR12_X2HSPI2_ERRINT           (0x00000080uL)
+#define INTC_ICDISPR12_PRRI                     (0x00000100uL)
+#define INTC_ICDISPR12_IFEI0                    (0x00000200uL)
+#define INTC_ICDISPR12_OFFI0                    (0x00000400uL)
+#define INTC_ICDISPR12_PFVEI0                   (0x00000800uL)
+#define INTC_ICDISPR12_IFEI1                    (0x00001000uL)
+#define INTC_ICDISPR12_OFFI1                    (0x00002000uL)
+#define INTC_ICDISPR12_PFVEI1                   (0x00004000uL)
+
+#define INTC_ICDISPR13_TINT0                    (0x00000001uL)
+#define INTC_ICDISPR13_TINT1                    (0x00000002uL)
+#define INTC_ICDISPR13_TINT2                    (0x00000004uL)
+#define INTC_ICDISPR13_TINT3                    (0x00000008uL)
+#define INTC_ICDISPR13_TINT4                    (0x00000010uL)
+#define INTC_ICDISPR13_TINT5                    (0x00000020uL)
+#define INTC_ICDISPR13_TINT6                    (0x00000040uL)
+#define INTC_ICDISPR13_TINT7                    (0x00000080uL)
+#define INTC_ICDISPR13_TINT8                    (0x00000100uL)
+#define INTC_ICDISPR13_TINT9                    (0x00000200uL)
+#define INTC_ICDISPR13_TINT10                   (0x00000400uL)
+#define INTC_ICDISPR13_TINT11                   (0x00000800uL)
+#define INTC_ICDISPR13_TINT12                   (0x00001000uL)
+#define INTC_ICDISPR13_TINT13                   (0x00002000uL)
+#define INTC_ICDISPR13_TINT14                   (0x00004000uL)
+#define INTC_ICDISPR13_TINT15                   (0x00008000uL)
+#define INTC_ICDISPR13_TINT16                   (0x00010000uL)
+#define INTC_ICDISPR13_TINT17                   (0x00020000uL)
+#define INTC_ICDISPR13_TINT18                   (0x00040000uL)
+#define INTC_ICDISPR13_TINT19                   (0x00080000uL)
+#define INTC_ICDISPR13_TINT20                   (0x00100000uL)
+#define INTC_ICDISPR13_TINT21                   (0x00200000uL)
+#define INTC_ICDISPR13_TINT22                   (0x00400000uL)
+#define INTC_ICDISPR13_TINT23                   (0x00800000uL)
+#define INTC_ICDISPR13_TINT24                   (0x01000000uL)
+#define INTC_ICDISPR13_TINT25                   (0x02000000uL)
+#define INTC_ICDISPR13_TINT26                   (0x04000000uL)
+#define INTC_ICDISPR13_TINT27                   (0x08000000uL)
+#define INTC_ICDISPR13_TINT28                   (0x10000000uL)
+#define INTC_ICDISPR13_TINT29                   (0x20000000uL)
+#define INTC_ICDISPR13_TINT30                   (0x40000000uL)
+#define INTC_ICDISPR13_TINT31                   (0x80000000uL)
+
+#define INTC_ICDISPR14_TINT32                   (0x00000001uL)
+#define INTC_ICDISPR14_TINT33                   (0x00000002uL)
+#define INTC_ICDISPR14_TINT34                   (0x00000004uL)
+#define INTC_ICDISPR14_TINT35                   (0x00000008uL)
+#define INTC_ICDISPR14_TINT36                   (0x00000010uL)
+#define INTC_ICDISPR14_TINT37                   (0x00000020uL)
+#define INTC_ICDISPR14_TINT38                   (0x00000040uL)
+#define INTC_ICDISPR14_TINT39                   (0x00000080uL)
+#define INTC_ICDISPR14_TINT40                   (0x00000100uL)
+#define INTC_ICDISPR14_TINT41                   (0x00000200uL)
+#define INTC_ICDISPR14_TINT42                   (0x00000400uL)
+#define INTC_ICDISPR14_TINT43                   (0x00000800uL)
+#define INTC_ICDISPR14_TINT44                   (0x00001000uL)
+#define INTC_ICDISPR14_TINT45                   (0x00002000uL)
+#define INTC_ICDISPR14_TINT46                   (0x00004000uL)
+#define INTC_ICDISPR14_TINT47                   (0x00008000uL)
+#define INTC_ICDISPR14_TINT48                   (0x00010000uL)
+#define INTC_ICDISPR14_TINT49                   (0x00020000uL)
+#define INTC_ICDISPR14_TINT50                   (0x00040000uL)
+#define INTC_ICDISPR14_TINT51                   (0x00080000uL)
+#define INTC_ICDISPR14_TINT52                   (0x00100000uL)
+#define INTC_ICDISPR14_TINT53                   (0x00200000uL)
+#define INTC_ICDISPR14_TINT54                   (0x00400000uL)
+#define INTC_ICDISPR14_TINT55                   (0x00800000uL)
+#define INTC_ICDISPR14_TINT56                   (0x01000000uL)
+#define INTC_ICDISPR14_TINT57                   (0x02000000uL)
+#define INTC_ICDISPR14_TINT58                   (0x04000000uL)
+#define INTC_ICDISPR14_TINT59                   (0x08000000uL)
+#define INTC_ICDISPR14_TINT60                   (0x10000000uL)
+#define INTC_ICDISPR14_TINT61                   (0x20000000uL)
+#define INTC_ICDISPR14_TINT62                   (0x40000000uL)
+#define INTC_ICDISPR14_TINT63                   (0x80000000uL)
+
+#define INTC_ICDISPR15_TINT64                   (0x00000001uL)
+#define INTC_ICDISPR15_TINT65                   (0x00000002uL)
+#define INTC_ICDISPR15_TINT66                   (0x00000004uL)
+#define INTC_ICDISPR15_TINT67                   (0x00000008uL)
+#define INTC_ICDISPR15_TINT68                   (0x00000010uL)
+#define INTC_ICDISPR15_TINT69                   (0x00000020uL)
+#define INTC_ICDISPR15_TINT70                   (0x00000040uL)
+#define INTC_ICDISPR15_TINT71                   (0x00000080uL)
+#define INTC_ICDISPR15_TINT72                   (0x00000100uL)
+#define INTC_ICDISPR15_TINT73                   (0x00000200uL)
+#define INTC_ICDISPR15_TINT74                   (0x00000400uL)
+#define INTC_ICDISPR15_TINT75                   (0x00000800uL)
+#define INTC_ICDISPR15_TINT76                   (0x00001000uL)
+#define INTC_ICDISPR15_TINT77                   (0x00002000uL)
+#define INTC_ICDISPR15_TINT78                   (0x00004000uL)
+#define INTC_ICDISPR15_TINT79                   (0x00008000uL)
+#define INTC_ICDISPR15_TINT80                   (0x00010000uL)
+#define INTC_ICDISPR15_TINT81                   (0x00020000uL)
+#define INTC_ICDISPR15_TINT82                   (0x00040000uL)
+#define INTC_ICDISPR15_TINT83                   (0x00080000uL)
+#define INTC_ICDISPR15_TINT84                   (0x00100000uL)
+#define INTC_ICDISPR15_TINT85                   (0x00200000uL)
+#define INTC_ICDISPR15_TINT86                   (0x00400000uL)
+#define INTC_ICDISPR15_TINT87                   (0x00800000uL)
+#define INTC_ICDISPR15_TINT88                   (0x01000000uL)
+#define INTC_ICDISPR15_TINT89                   (0x02000000uL)
+#define INTC_ICDISPR15_TINT90                   (0x04000000uL)
+#define INTC_ICDISPR15_TINT91                   (0x08000000uL)
+#define INTC_ICDISPR15_TINT92                   (0x10000000uL)
+#define INTC_ICDISPR15_TINT93                   (0x20000000uL)
+#define INTC_ICDISPR15_TINT94                   (0x40000000uL)
+#define INTC_ICDISPR15_TINT95                   (0x80000000uL)
+
+#define INTC_ICDISPR16_TINT96                   (0x00000001uL)
+#define INTC_ICDISPR16_TINT97                   (0x00000002uL)
+#define INTC_ICDISPR16_TINT98                   (0x00000004uL)
+#define INTC_ICDISPR16_TINT99                   (0x00000008uL)
+#define INTC_ICDISPR16_TINT100                  (0x00000010uL)
+#define INTC_ICDISPR16_TINT101                  (0x00000020uL)
+#define INTC_ICDISPR16_TINT102                  (0x00000040uL)
+#define INTC_ICDISPR16_TINT103                  (0x00000080uL)
+#define INTC_ICDISPR16_TINT104                  (0x00000100uL)
+#define INTC_ICDISPR16_TINT105                  (0x00000200uL)
+#define INTC_ICDISPR16_TINT106                  (0x00000400uL)
+#define INTC_ICDISPR16_TINT107                  (0x00000800uL)
+#define INTC_ICDISPR16_TINT108                  (0x00001000uL)
+#define INTC_ICDISPR16_TINT109                  (0x00002000uL)
+#define INTC_ICDISPR16_TINT110                  (0x00004000uL)
+#define INTC_ICDISPR16_TINT111                  (0x00008000uL)
+#define INTC_ICDISPR16_TINT112                  (0x00010000uL)
+#define INTC_ICDISPR16_TINT113                  (0x00020000uL)
+#define INTC_ICDISPR16_TINT114                  (0x00040000uL)
+#define INTC_ICDISPR16_TINT115                  (0x00080000uL)
+#define INTC_ICDISPR16_TINT116                  (0x00100000uL)
+#define INTC_ICDISPR16_TINT117                  (0x00200000uL)
+#define INTC_ICDISPR16_TINT118                  (0x00400000uL)
+#define INTC_ICDISPR16_TINT119                  (0x00800000uL)
+#define INTC_ICDISPR16_TINT120                  (0x01000000uL)
+#define INTC_ICDISPR16_TINT121                  (0x02000000uL)
+#define INTC_ICDISPR16_TINT122                  (0x04000000uL)
+#define INTC_ICDISPR16_TINT123                  (0x08000000uL)
+#define INTC_ICDISPR16_TINT124                  (0x10000000uL)
+#define INTC_ICDISPR16_TINT125                  (0x20000000uL)
+#define INTC_ICDISPR16_TINT126                  (0x40000000uL)
+#define INTC_ICDISPR16_TINT127                  (0x80000000uL)
+
+#define INTC_ICDISPR17_TINT128                  (0x00000001uL)
+#define INTC_ICDISPR17_TINT129                  (0x00000002uL)
+#define INTC_ICDISPR17_TINT130                  (0x00000004uL)
+#define INTC_ICDISPR17_TINT131                  (0x00000008uL)
+#define INTC_ICDISPR17_TINT132                  (0x00000010uL)
+#define INTC_ICDISPR17_TINT133                  (0x00000020uL)
+#define INTC_ICDISPR17_TINT134                  (0x00000040uL)
+#define INTC_ICDISPR17_TINT135                  (0x00000080uL)
+#define INTC_ICDISPR17_TINT136                  (0x00000100uL)
+#define INTC_ICDISPR17_TINT137                  (0x00000200uL)
+#define INTC_ICDISPR17_TINT138                  (0x00000400uL)
+#define INTC_ICDISPR17_TINT139                  (0x00000800uL)
+#define INTC_ICDISPR17_TINT140                  (0x00001000uL)
+#define INTC_ICDISPR17_TINT141                  (0x00002000uL)
+#define INTC_ICDISPR17_TINT142                  (0x00004000uL)
+#define INTC_ICDISPR17_TINT143                  (0x00008000uL)
+#define INTC_ICDISPR17_TINT144                  (0x00010000uL)
+#define INTC_ICDISPR17_TINT145                  (0x00020000uL)
+#define INTC_ICDISPR17_TINT146                  (0x00040000uL)
+#define INTC_ICDISPR17_TINT147                  (0x00080000uL)
+#define INTC_ICDISPR17_TINT148                  (0x00100000uL)
+#define INTC_ICDISPR17_TINT149                  (0x00200000uL)
+#define INTC_ICDISPR17_TINT150                  (0x00400000uL)
+#define INTC_ICDISPR17_TINT151                  (0x00800000uL)
+#define INTC_ICDISPR17_TINT152                  (0x01000000uL)
+#define INTC_ICDISPR17_TINT153                  (0x02000000uL)
+#define INTC_ICDISPR17_TINT154                  (0x04000000uL)
+#define INTC_ICDISPR17_TINT155                  (0x08000000uL)
+#define INTC_ICDISPR17_TINT156                  (0x10000000uL)
+#define INTC_ICDISPR17_TINT157                  (0x20000000uL)
+#define INTC_ICDISPR17_TINT158                  (0x40000000uL)
+#define INTC_ICDISPR17_TINT159                  (0x80000000uL)
+
+#define INTC_ICDISPR18_TINT160                  (0x00000001uL)
+#define INTC_ICDISPR18_TINT161                  (0x00000002uL)
+#define INTC_ICDISPR18_TINT162                  (0x00000004uL)
+#define INTC_ICDISPR18_TINT163                  (0x00000008uL)
+#define INTC_ICDISPR18_TINT164                  (0x00000010uL)
+#define INTC_ICDISPR18_TINT165                  (0x00000020uL)
+#define INTC_ICDISPR18_TINT166                  (0x00000040uL)
+#define INTC_ICDISPR18_TINT167                  (0x00000080uL)
+#define INTC_ICDISPR18_TINT168                  (0x00000100uL)
+#define INTC_ICDISPR18_TINT169                  (0x00000200uL)
+#define INTC_ICDISPR18_TINT170                  (0x00000400uL)
+
+#define INTC_ICDICPR0_SW0                       (0x00000001uL)
+#define INTC_ICDICPR0_SW1                       (0x00000002uL)
+#define INTC_ICDICPR0_SW2                       (0x00000004uL)
+#define INTC_ICDICPR0_SW3                       (0x00000008uL)
+#define INTC_ICDICPR0_SW4                       (0x00000010uL)
+#define INTC_ICDICPR0_SW5                       (0x00000020uL)
+#define INTC_ICDICPR0_SW6                       (0x00000040uL)
+#define INTC_ICDICPR0_SW7                       (0x00000080uL)
+#define INTC_ICDICPR0_SW8                       (0x00000100uL)
+#define INTC_ICDICPR0_SW9                       (0x00000200uL)
+#define INTC_ICDICPR0_SW10                      (0x00000400uL)
+#define INTC_ICDICPR0_SW11                      (0x00000800uL)
+#define INTC_ICDICPR0_SW12                      (0x00001000uL)
+#define INTC_ICDICPR0_SW13                      (0x00002000uL)
+#define INTC_ICDICPR0_SW14                      (0x00004000uL)
+#define INTC_ICDICPR0_SW15                      (0x00008000uL)
+#define INTC_ICDICPR0_PMUIRQ0                   (0x00010000uL)
+#define INTC_ICDICPR0_COMMRX0                   (0x00020000uL)
+#define INTC_ICDICPR0_COMMTX0                   (0x00040000uL)
+#define INTC_ICDICPR0_CTIIRQ0                   (0x00080000uL)
+
+#define INTC_ICDICPR1_IRQ0                      (0x00000001uL)
+#define INTC_ICDICPR1_IRQ1                      (0x00000002uL)
+#define INTC_ICDICPR1_IRQ2                      (0x00000004uL)
+#define INTC_ICDICPR1_IRQ3                      (0x00000008uL)
+#define INTC_ICDICPR1_IRQ4                      (0x00000010uL)
+#define INTC_ICDICPR1_IRQ5                      (0x00000020uL)
+#define INTC_ICDICPR1_IRQ6                      (0x00000040uL)
+#define INTC_ICDICPR1_IRQ7                      (0x00000080uL)
+#define INTC_ICDICPR1_PL310ERR                  (0x00000100uL)
+#define INTC_ICDICPR1_DMAINT0                   (0x00000200uL)
+#define INTC_ICDICPR1_DMAINT1                   (0x00000400uL)
+#define INTC_ICDICPR1_DMAINT2                   (0x00000800uL)
+#define INTC_ICDICPR1_DMAINT3                   (0x00001000uL)
+#define INTC_ICDICPR1_DMAINT4                   (0x00002000uL)
+#define INTC_ICDICPR1_DMAINT5                   (0x00004000uL)
+#define INTC_ICDICPR1_DMAINT6                   (0x00008000uL)
+#define INTC_ICDICPR1_DMAINT7                   (0x00010000uL)
+#define INTC_ICDICPR1_DMAINT8                   (0x00020000uL)
+#define INTC_ICDICPR1_DMAINT9                   (0x00040000uL)
+#define INTC_ICDICPR1_DMAINT10                  (0x00080000uL)
+#define INTC_ICDICPR1_DMAINT11                  (0x00100000uL)
+#define INTC_ICDICPR1_DMAINT12                  (0x00200000uL)
+#define INTC_ICDICPR1_DMAINT13                  (0x00400000uL)
+#define INTC_ICDICPR1_DMAINT14                  (0x00800000uL)
+#define INTC_ICDICPR1_DMAINT15                  (0x01000000uL)
+#define INTC_ICDICPR1_DMAERR                    (0x02000000uL)
+
+#define INTC_ICDICPR2_USBI0                     (0x00000200uL)
+#define INTC_ICDICPR2_USBI1                     (0x00000400uL)
+#define INTC_ICDICPR2_S0_VI_VSYNC0              (0x00000800uL)
+#define INTC_ICDICPR2_S0_LO_VSYNC0              (0x00001000uL)
+#define INTC_ICDICPR2_S0_VSYNCERR0              (0x00002000uL)
+#define INTC_ICDICPR2_GR3_VLINE0                (0x00004000uL)
+#define INTC_ICDICPR2_S0_VFIELD0                (0x00008000uL)
+#define INTC_ICDICPR2_IV1_VBUFERR0              (0x00010000uL)
+#define INTC_ICDICPR2_IV3_VBUFERR0              (0x00020000uL)
+#define INTC_ICDICPR2_IV5_VBUFERR0              (0x00040000uL)
+#define INTC_ICDICPR2_IV6_VBUFERR0              (0x00080000uL)
+#define INTC_ICDICPR2_S0_WLINE0                 (0x00100000uL)
+#define INTC_ICDICPR2_S1_VI_VSYNC0              (0x00200000uL)
+#define INTC_ICDICPR2_S1_LO_VSYNC0              (0x00400000uL)
+#define INTC_ICDICPR2_S1_VSYNCERR0              (0x00800000uL)
+#define INTC_ICDICPR2_S1_VFIELD0                (0x01000000uL)
+#define INTC_ICDICPR2_IV2_VBUFERR0              (0x02000000uL)
+#define INTC_ICDICPR2_IV4_VBUFERR0              (0x04000000uL)
+#define INTC_ICDICPR2_S1_WLINE0                 (0x08000000uL)
+#define INTC_ICDICPR2_OIR_VI_VSYNC0             (0x10000000uL)
+#define INTC_ICDICPR2_OIR_LO_VSYNC0             (0x20000000uL)
+#define INTC_ICDICPR2_OIR_VSYNCERR0             (0x40000000uL)
+#define INTC_ICDICPR2_OIR_VFIELD0               (0x80000000uL)
+
+#define INTC_ICDICPR3_IV7_VBUFERR0              (0x00000001uL)
+#define INTC_ICDICPR3_IV8_VBUFERR0              (0x00000002uL)
+#define INTC_ICDICPR3_S0_VI_VSYNC1              (0x00000008uL)
+#define INTC_ICDICPR3_S0_LO_VSYNC1              (0x00000010uL)
+#define INTC_ICDICPR3_S0_VSYNCERR1              (0x00000020uL)
+#define INTC_ICDICPR3_GR3_VLINE1                (0x00000040uL)
+#define INTC_ICDICPR3_S0_VFIELD1                (0x00000080uL)
+#define INTC_ICDICPR3_IV1_VBUFERR1              (0x00000100uL)
+#define INTC_ICDICPR3_IV3_VBUFERR1              (0x00000200uL)
+#define INTC_ICDICPR3_IV5_VBUFERR1              (0x00000400uL)
+#define INTC_ICDICPR3_IV6_VBUFERR1              (0x00000800uL)
+#define INTC_ICDICPR3_S0_WLINE1                 (0x00001000uL)
+#define INTC_ICDICPR3_S1_VI_VSYNC1              (0x00002000uL)
+#define INTC_ICDICPR3_S1_LO_VSYNC1              (0x00004000uL)
+#define INTC_ICDICPR3_S1_VSYNCERR1              (0x00008000uL)
+#define INTC_ICDICPR3_S1_VFIELD1                (0x00010000uL)
+#define INTC_ICDICPR3_IV2_VBUFERR1              (0x00020000uL)
+#define INTC_ICDICPR3_IV4_VBUFERR1              (0x00040000uL)
+#define INTC_ICDICPR3_S1_WLINE1                 (0x00080000uL)
+#define INTC_ICDICPR3_OIR_VI_VSYNC1             (0x00100000uL)
+#define INTC_ICDICPR3_OIR_LO_VSYNC1             (0x00200000uL)
+#define INTC_ICDICPR3_OIR_VLINE1                (0x00400000uL)
+#define INTC_ICDICPR3_OIR_VFIELD1               (0x00800000uL)
+#define INTC_ICDICPR3_IV7_VBUFERR1              (0x01000000uL)
+#define INTC_ICDICPR3_IV8_VBUFERR1              (0x02000000uL)
+#define INTC_ICDICPR3_IMRDI                     (0x08000000uL)
+#define INTC_ICDICPR3_IMR2I0                    (0x10000000uL)
+#define INTC_ICDICPR3_IMR2I1                    (0x20000000uL)
+#define INTC_ICDICPR3_JEDI                      (0x40000000uL)
+#define INTC_ICDICPR3_JDTI                      (0x80000000uL)
+
+#define INTC_ICDICPR4_CMP0                      (0x00000001uL)
+#define INTC_ICDICPR4_CMP1                      (0x00000002uL)
+#define INTC_ICDICPR4_INT0                      (0x00000004uL)
+#define INTC_ICDICPR4_INT1                      (0x00000008uL)
+#define INTC_ICDICPR4_INT2                      (0x00000010uL)
+#define INTC_ICDICPR4_INT3                      (0x00000020uL)
+#define INTC_ICDICPR4_OSTM0TINT                 (0x00000040uL)
+#define INTC_ICDICPR4_OSTM1TINT                 (0x00000080uL)
+#define INTC_ICDICPR4_CMI                       (0x00000100uL)
+#define INTC_ICDICPR4_WTOUT                     (0x00000200uL)
+#define INTC_ICDICPR4_ITI                       (0x00000400uL)
+#define INTC_ICDICPR4_TGI0A                     (0x00000800uL)
+#define INTC_ICDICPR4_TGI0B                     (0x00001000uL)
+#define INTC_ICDICPR4_TGI0C                     (0x00002000uL)
+#define INTC_ICDICPR4_TGI0D                     (0x00004000uL)
+#define INTC_ICDICPR4_TGI0V                     (0x00008000uL)
+#define INTC_ICDICPR4_TGI0E                     (0x00010000uL)
+#define INTC_ICDICPR4_TGI0F                     (0x00020000uL)
+#define INTC_ICDICPR4_TGI1A                     (0x00040000uL)
+#define INTC_ICDICPR4_TGI1B                     (0x00080000uL)
+#define INTC_ICDICPR4_TGI1V                     (0x00100000uL)
+#define INTC_ICDICPR4_TGI1U                     (0x00200000uL)
+#define INTC_ICDICPR4_TGI2A                     (0x00400000uL)
+#define INTC_ICDICPR4_TGI2B                     (0x00800000uL)
+#define INTC_ICDICPR4_TGI2V                     (0x01000000uL)
+#define INTC_ICDICPR4_TGI2U                     (0x02000000uL)
+#define INTC_ICDICPR4_TGI3A                     (0x04000000uL)
+#define INTC_ICDICPR4_TGI3B                     (0x08000000uL)
+#define INTC_ICDICPR4_TGI3C                     (0x10000000uL)
+#define INTC_ICDICPR4_TGI3D                     (0x20000000uL)
+#define INTC_ICDICPR4_TGI3V                     (0x40000000uL)
+#define INTC_ICDICPR4_TGI4A                     (0x80000000uL)
+
+#define INTC_ICDICPR5_TGI4B                     (0x00000001uL)
+#define INTC_ICDICPR5_TGI4C                     (0x00000002uL)
+#define INTC_ICDICPR5_TGI4D                     (0x00000004uL)
+#define INTC_ICDICPR5_TGI4V                     (0x00000008uL)
+#define INTC_ICDICPR5_CMI1                      (0x00000010uL)
+#define INTC_ICDICPR5_CMI2                      (0x00000020uL)
+#define INTC_ICDICPR5_SGDEI0                    (0x00000040uL)
+#define INTC_ICDICPR5_SGDEI1                    (0x00000080uL)
+#define INTC_ICDICPR5_SGDEI2                    (0x00000100uL)
+#define INTC_ICDICPR5_SGDEI3                    (0x00000200uL)
+#define INTC_ICDICPR5_ADI                       (0x00000400uL)
+#define INTC_ICDICPR5_LMTI                      (0x00000800uL)
+#define INTC_ICDICPR5_SSII0                     (0x00001000uL)
+#define INTC_ICDICPR5_SSIRXI0                   (0x00002000uL)
+#define INTC_ICDICPR5_SSITXI0                   (0x00004000uL)
+#define INTC_ICDICPR5_SSII1                     (0x00008000uL)
+#define INTC_ICDICPR5_SSIRXI1                   (0x00010000uL)
+#define INTC_ICDICPR5_SSITXI1                   (0x00020000uL)
+#define INTC_ICDICPR5_SSII2                     (0x00040000uL)
+#define INTC_ICDICPR5_SSIRTI2                   (0x00080000uL)
+#define INTC_ICDICPR5_SSII3                     (0x00100000uL)
+#define INTC_ICDICPR5_SSIRXI3                   (0x00200000uL)
+#define INTC_ICDICPR5_SSITXI3                   (0x00400000uL)
+#define INTC_ICDICPR5_SSII4                     (0x00800000uL)
+#define INTC_ICDICPR5_SSIRTI4                   (0x01000000uL)
+#define INTC_ICDICPR5_SSII5                     (0x02000000uL)
+#define INTC_ICDICPR5_SSIRXI5                   (0x04000000uL)
+#define INTC_ICDICPR5_SSITXI5                   (0x08000000uL)
+#define INTC_ICDICPR5_SPDIFI                    (0x10000000uL)
+#define INTC_ICDICPR5_INTIICTEI0                (0x20000000uL)
+#define INTC_ICDICPR5_INTIICRI0                 (0x40000000uL)
+#define INTC_ICDICPR5_INTIICTI0                 (0x80000000uL)
+
+#define INTC_ICDICPR6_INTIICSPI0                (0x00000001uL)
+#define INTC_ICDICPR6_INTIICSTI0                (0x00000002uL)
+#define INTC_ICDICPR6_INTIICNAKI0               (0x00000004uL)
+#define INTC_ICDICPR6_INTIICALI0                (0x00000008uL)
+#define INTC_ICDICPR6_INTIICTMOI0               (0x00000010uL)
+#define INTC_ICDICPR6_INTIICTEI1                (0x00000020uL)
+#define INTC_ICDICPR6_INTIICRI1                 (0x00000040uL)
+#define INTC_ICDICPR6_INTIICTI1                 (0x00000080uL)
+#define INTC_ICDICPR6_INTIICSPI1                (0x00000100uL)
+#define INTC_ICDICPR6_INTIICSTI1                (0x00000200uL)
+#define INTC_ICDICPR6_INTIICNAKI1               (0x00000400uL)
+#define INTC_ICDICPR6_INTIICALI1                (0x00000800uL)
+#define INTC_ICDICPR6_INTIICTMOI1               (0x00001000uL)
+#define INTC_ICDICPR6_INTIICTEI2                (0x00002000uL)
+#define INTC_ICDICPR6_INTIICRI2                 (0x00004000uL)
+#define INTC_ICDICPR6_INTIICTI2                 (0x00008000uL)
+#define INTC_ICDICPR6_INTIICSPI2                (0x00010000uL)
+#define INTC_ICDICPR6_INTIICSTI2                (0x00020000uL)
+#define INTC_ICDICPR6_INTIICNAKI2               (0x00040000uL)
+#define INTC_ICDICPR6_INTIICALI2                (0x00080000uL)
+#define INTC_ICDICPR6_INTIICTMOI2               (0x00100000uL)
+#define INTC_ICDICPR6_INTIICTEI3                (0x00200000uL)
+#define INTC_ICDICPR6_INTIICRI3                 (0x00400000uL)
+#define INTC_ICDICPR6_INTIICTI3                 (0x00800000uL)
+#define INTC_ICDICPR6_INTIICSPI3                (0x01000000uL)
+#define INTC_ICDICPR6_INTIICSTI3                (0x02000000uL)
+#define INTC_ICDICPR6_INTIICNAKI3               (0x04000000uL)
+#define INTC_ICDICPR6_INTIICALI3                (0x08000000uL)
+#define INTC_ICDICPR6_INTIICTMOI3               (0x10000000uL)
+#define INTC_ICDICPR6_BRI0                      (0x20000000uL)
+#define INTC_ICDICPR6_ERI0                      (0x40000000uL)
+#define INTC_ICDICPR6_RXI0                      (0x80000000uL)
+
+#define INTC_ICDICPR7_TXI0                      (0x00000001uL)
+#define INTC_ICDICPR7_BRI1                      (0x00000002uL)
+#define INTC_ICDICPR7_ERI1                      (0x00000004uL)
+#define INTC_ICDICPR7_RXI1                      (0x00000008uL)
+#define INTC_ICDICPR7_TXI1                      (0x00000010uL)
+#define INTC_ICDICPR7_BRI2                      (0x00000020uL)
+#define INTC_ICDICPR7_ERI2                      (0x00000040uL)
+#define INTC_ICDICPR7_RXI2                      (0x00000080uL)
+#define INTC_ICDICPR7_TXI2                      (0x00000100uL)
+#define INTC_ICDICPR7_BRI3                      (0x00000200uL)
+#define INTC_ICDICPR7_ERI3                      (0x00000400uL)
+#define INTC_ICDICPR7_RXI3                      (0x00000800uL)
+#define INTC_ICDICPR7_TXI3                      (0x00001000uL)
+#define INTC_ICDICPR7_BRI4                      (0x00002000uL)
+#define INTC_ICDICPR7_ERI4                      (0x00004000uL)
+#define INTC_ICDICPR7_RXI4                      (0x00008000uL)
+#define INTC_ICDICPR7_TXI4                      (0x00010000uL)
+#define INTC_ICDICPR7_BRI5                      (0x00020000uL)
+#define INTC_ICDICPR7_ERI5                      (0x00040000uL)
+#define INTC_ICDICPR7_RXI5                      (0x00080000uL)
+#define INTC_ICDICPR7_TXI5                      (0x00100000uL)
+#define INTC_ICDICPR7_BRI6                      (0x00200000uL)
+#define INTC_ICDICPR7_ERI6                      (0x00400000uL)
+#define INTC_ICDICPR7_RXI6                      (0x00800000uL)
+#define INTC_ICDICPR7_TXI6                      (0x01000000uL)
+#define INTC_ICDICPR7_BRI7                      (0x02000000uL)
+#define INTC_ICDICPR7_ERI7                      (0x04000000uL)
+#define INTC_ICDICPR7_RXI7                      (0x08000000uL)
+#define INTC_ICDICPR7_TXI7                      (0x10000000uL)
+#define INTC_ICDICPR7_INTRCANGERR               (0x20000000uL)
+#define INTC_ICDICPR7_INTRCANGRECC              (0x40000000uL)
+#define INTC_ICDICPR7_INTRCAN0REC               (0x80000000uL)
+
+#define INTC_ICDICPR8_INTRCAN0ERR               (0x00000001uL)
+#define INTC_ICDICPR8_INTRCAN0TRX               (0x00000002uL)
+#define INTC_ICDICPR8_INTRCAN1REC               (0x00000004uL)
+#define INTC_ICDICPR8_INTRCAN1ERR               (0x00000008uL)
+#define INTC_ICDICPR8_INTRCAN1TRX               (0x00000010uL)
+#define INTC_ICDICPR8_INTRCAN2REC               (0x00000020uL)
+#define INTC_ICDICPR8_INTRCAN2ERR               (0x00000040uL)
+#define INTC_ICDICPR8_INTRCAN2TRX               (0x00000080uL)
+#define INTC_ICDICPR8_INTRCAN3REC               (0x00000100uL)
+#define INTC_ICDICPR8_INTRCAN3ERR               (0x00000200uL)
+#define INTC_ICDICPR8_INTRCAN3TRX               (0x00000400uL)
+#define INTC_ICDICPR8_INTRCAN4REC               (0x00000800uL)
+#define INTC_ICDICPR8_INTRCAN4ERR               (0x00001000uL)
+#define INTC_ICDICPR8_INTRCAN4TRX               (0x00002000uL)
+#define INTC_ICDICPR8_SPEI0                     (0x00004000uL)
+#define INTC_ICDICPR8_SPRI0                     (0x00008000uL)
+#define INTC_ICDICPR8_SPTI0                     (0x00010000uL)
+#define INTC_ICDICPR8_SPEI1                     (0x00020000uL)
+#define INTC_ICDICPR8_SPRI1                     (0x00040000uL)
+#define INTC_ICDICPR8_SPTI1                     (0x00080000uL)
+#define INTC_ICDICPR8_SPEI2                     (0x00100000uL)
+#define INTC_ICDICPR8_SPRI2                     (0x00200000uL)
+#define INTC_ICDICPR8_SPTI2                     (0x00400000uL)
+#define INTC_ICDICPR8_SPEI3                     (0x00800000uL)
+#define INTC_ICDICPR8_SPRI3                     (0x01000000uL)
+#define INTC_ICDICPR8_SPTI3                     (0x02000000uL)
+#define INTC_ICDICPR8_SPEI4                     (0x04000000uL)
+#define INTC_ICDICPR8_SPRI4                     (0x08000000uL)
+#define INTC_ICDICPR8_SPTI4                     (0x10000000uL)
+#define INTC_ICDICPR8_IEBBTD                    (0x20000000uL)
+#define INTC_ICDICPR8_IEBBTERR                  (0x40000000uL)
+#define INTC_ICDICPR8_IEBBTSTA                  (0x80000000uL)
+
+#define INTC_ICDICPR9_IEBBTV                    (0x00000001uL)
+#define INTC_ICDICPR9_ISY                       (0x00000002uL)
+#define INTC_ICDICPR9_IERR                      (0x00000004uL)
+#define INTC_ICDICPR9_ITARG                     (0x00000008uL)
+#define INTC_ICDICPR9_ISEC                      (0x00000010uL)
+#define INTC_ICDICPR9_IBUF                      (0x00000020uL)
+#define INTC_ICDICPR9_IREADY                    (0x00000040uL)
+#define INTC_ICDICPR9_FLSTE                     (0x00000080uL)
+#define INTC_ICDICPR9_FLTENDI                   (0x00000100uL)
+#define INTC_ICDICPR9_FLTREQ0I                  (0x00000200uL)
+#define INTC_ICDICPR9_FLTREQ1I                  (0x00000400uL)
+#define INTC_ICDICPR9_MMC0                      (0x00000800uL)
+#define INTC_ICDICPR9_MMC1                      (0x00001000uL)
+#define INTC_ICDICPR9_MMC2                      (0x00002000uL)
+#define INTC_ICDICPR9_SDHI0_3                   (0x00004000uL)
+#define INTC_ICDICPR9_SDHI0_0                   (0x00008000uL)
+#define INTC_ICDICPR9_SDHI0_1                   (0x00010000uL)
+#define INTC_ICDICPR9_SDHI1_3                   (0x00020000uL)
+#define INTC_ICDICPR9_SDHI1_0                   (0x00040000uL)
+#define INTC_ICDICPR9_SDHI1_1                   (0x00080000uL)
+#define INTC_ICDICPR9_ARM                       (0x00100000uL)
+#define INTC_ICDICPR9_PRD                       (0x00200000uL)
+#define INTC_ICDICPR9_CUP                       (0x00400000uL)
+#define INTC_ICDICPR9_SCUAI0                    (0x00800000uL)
+#define INTC_ICDICPR9_SCUAI1                    (0x01000000uL)
+#define INTC_ICDICPR9_SCUFDI0                   (0x02000000uL)
+#define INTC_ICDICPR9_SCUFDI1                   (0x04000000uL)
+#define INTC_ICDICPR9_SCUFDI2                   (0x08000000uL)
+#define INTC_ICDICPR9_SCUFDI3                   (0x10000000uL)
+#define INTC_ICDICPR9_SCUFUI0                   (0x20000000uL)
+#define INTC_ICDICPR9_SCUFUI1                   (0x40000000uL)
+#define INTC_ICDICPR9_SCUFUI2                   (0x80000000uL)
+
+#define INTC_ICDICPR10_SCUFUI3                  (0x00000001uL)
+#define INTC_ICDICPR10_SCUDVI0                  (0x00000002uL)
+#define INTC_ICDICPR10_SCUDVI1                  (0x00000004uL)
+#define INTC_ICDICPR10_SCUDVI2                  (0x00000008uL)
+#define INTC_ICDICPR10_SCUDVI3                  (0x00000010uL)
+#define INTC_ICDICPR10_MLB_CINT                 (0x00000020uL)
+#define INTC_ICDICPR10_MLB_SINT                 (0x00000040uL)
+#define INTC_ICDICPR10_DRC0                     (0x00000080uL)
+#define INTC_ICDICPR10_DRC1                     (0x00000100uL)
+#define INTC_ICDICPR10_LINI0_INT_T              (0x00000800uL)
+#define INTC_ICDICPR10_LINI0_INT_R              (0x00001000uL)
+#define INTC_ICDICPR10_LINI0_INT_S              (0x00002000uL)
+#define INTC_ICDICPR10_LINI0_INT_M              (0x00004000uL)
+#define INTC_ICDICPR10_LINI1_INT_T              (0x00008000uL)
+#define INTC_ICDICPR10_LINI1_INT_R              (0x00010000uL)
+#define INTC_ICDICPR10_LINI1_INT_S              (0x00020000uL)
+#define INTC_ICDICPR10_LINI1_INT_M              (0x00040000uL)
+#define INTC_ICDICPR10_ERI0                     (0x08000000uL)
+#define INTC_ICDICPR10_RXI0                     (0x10000000uL)
+#define INTC_ICDICPR10_TXI0                     (0x20000000uL)
+#define INTC_ICDICPR10_TEI0                     (0x40000000uL)
+#define INTC_ICDICPR10_ERI1                     (0x80000000uL)
+
+#define INTC_ICDICPR11_RXI1                     (0x00000001uL)
+#define INTC_ICDICPR11_TXI1                     (0x00000002uL)
+#define INTC_ICDICPR11_TEI1                     (0x00000004uL)
+#define INTC_ICDICPR11_AVBI_DATA                (0x00000008uL)
+#define INTC_ICDICPR11_AVBI_ERROR               (0x00000010uL)
+#define INTC_ICDICPR11_AVBI_MANAGE              (0x00000020uL)
+#define INTC_ICDICPR11_AVBI_MAC                 (0x00000040uL)
+#define INTC_ICDICPR11_ETHERI                   (0x00000080uL)
+#define INTC_ICDICPR11_CEUI                     (0x00001000uL)
+#define INTC_ICDICPR11_H2XMLB_ERRINT            (0x20000000uL)
+#define INTC_ICDICPR11_H2XIC1_ERRINT            (0x40000000uL)
+#define INTC_ICDICPR11_X2HPERI1_ERRINT          (0x80000000uL)
+
+#define INTC_ICDICPR12_X2HPERI2_ERRINT          (0x00000001uL)
+#define INTC_ICDICPR12_X2HPERI34_ERRINT         (0x00000002uL)
+#define INTC_ICDICPR12_X2HPERI5_ERRINT          (0x00000004uL)
+#define INTC_ICDICPR12_X2HPERI67_ERRINT         (0x00000008uL)
+#define INTC_ICDICPR12_X2HDBGR_ERRINT           (0x00000010uL)
+#define INTC_ICDICPR12_X2HBSC_ERRINT            (0x00000020uL)
+#define INTC_ICDICPR12_X2HSPI1_ERRINT           (0x00000040uL)
+#define INTC_ICDICPR12_X2HSPI2_ERRINT           (0x00000080uL)
+#define INTC_ICDICPR12_PRRI                     (0x00000100uL)
+#define INTC_ICDICPR12_IFEI0                    (0x00000200uL)
+#define INTC_ICDICPR12_OFFI0                    (0x00000400uL)
+#define INTC_ICDICPR12_PFVEI0                   (0x00000800uL)
+#define INTC_ICDICPR12_IFEI1                    (0x00001000uL)
+#define INTC_ICDICPR12_OFFI1                    (0x00002000uL)
+#define INTC_ICDICPR12_PFVEI1                   (0x00004000uL)
+
+#define INTC_ICDICPR13_TINT0                    (0x00000001uL)
+#define INTC_ICDICPR13_TINT1                    (0x00000002uL)
+#define INTC_ICDICPR13_TINT2                    (0x00000004uL)
+#define INTC_ICDICPR13_TINT3                    (0x00000008uL)
+#define INTC_ICDICPR13_TINT4                    (0x00000010uL)
+#define INTC_ICDICPR13_TINT5                    (0x00000020uL)
+#define INTC_ICDICPR13_TINT6                    (0x00000040uL)
+#define INTC_ICDICPR13_TINT7                    (0x00000080uL)
+#define INTC_ICDICPR13_TINT8                    (0x00000100uL)
+#define INTC_ICDICPR13_TINT9                    (0x00000200uL)
+#define INTC_ICDICPR13_TINT10                   (0x00000400uL)
+#define INTC_ICDICPR13_TINT11                   (0x00000800uL)
+#define INTC_ICDICPR13_TINT12                   (0x00001000uL)
+#define INTC_ICDICPR13_TINT13                   (0x00002000uL)
+#define INTC_ICDICPR13_TINT14                   (0x00004000uL)
+#define INTC_ICDICPR13_TINT15                   (0x00008000uL)
+#define INTC_ICDICPR13_TINT16                   (0x00010000uL)
+#define INTC_ICDICPR13_TINT17                   (0x00020000uL)
+#define INTC_ICDICPR13_TINT18                   (0x00040000uL)
+#define INTC_ICDICPR13_TINT19                   (0x00080000uL)
+#define INTC_ICDICPR13_TINT20                   (0x00100000uL)
+#define INTC_ICDICPR13_TINT21                   (0x00200000uL)
+#define INTC_ICDICPR13_TINT22                   (0x00400000uL)
+#define INTC_ICDICPR13_TINT23                   (0x00800000uL)
+#define INTC_ICDICPR13_TINT24                   (0x01000000uL)
+#define INTC_ICDICPR13_TINT25                   (0x02000000uL)
+#define INTC_ICDICPR13_TINT26                   (0x04000000uL)
+#define INTC_ICDICPR13_TINT27                   (0x08000000uL)
+#define INTC_ICDICPR13_TINT28                   (0x10000000uL)
+#define INTC_ICDICPR13_TINT29                   (0x20000000uL)
+#define INTC_ICDICPR13_TINT30                   (0x40000000uL)
+#define INTC_ICDICPR13_TINT31                   (0x80000000uL)
+
+#define INTC_ICDICPR14_TINT32                   (0x00000001uL)
+#define INTC_ICDICPR14_TINT33                   (0x00000002uL)
+#define INTC_ICDICPR14_TINT34                   (0x00000004uL)
+#define INTC_ICDICPR14_TINT35                   (0x00000008uL)
+#define INTC_ICDICPR14_TINT36                   (0x00000010uL)
+#define INTC_ICDICPR14_TINT37                   (0x00000020uL)
+#define INTC_ICDICPR14_TINT38                   (0x00000040uL)
+#define INTC_ICDICPR14_TINT39                   (0x00000080uL)
+#define INTC_ICDICPR14_TINT40                   (0x00000100uL)
+#define INTC_ICDICPR14_TINT41                   (0x00000200uL)
+#define INTC_ICDICPR14_TINT42                   (0x00000400uL)
+#define INTC_ICDICPR14_TINT43                   (0x00000800uL)
+#define INTC_ICDICPR14_TINT44                   (0x00001000uL)
+#define INTC_ICDICPR14_TINT45                   (0x00002000uL)
+#define INTC_ICDICPR14_TINT46                   (0x00004000uL)
+#define INTC_ICDICPR14_TINT47                   (0x00008000uL)
+#define INTC_ICDICPR14_TINT48                   (0x00010000uL)
+#define INTC_ICDICPR14_TINT49                   (0x00020000uL)
+#define INTC_ICDICPR14_TINT50                   (0x00040000uL)
+#define INTC_ICDICPR14_TINT51                   (0x00080000uL)
+#define INTC_ICDICPR14_TINT52                   (0x00100000uL)
+#define INTC_ICDICPR14_TINT53                   (0x00200000uL)
+#define INTC_ICDICPR14_TINT54                   (0x00400000uL)
+#define INTC_ICDICPR14_TINT55                   (0x00800000uL)
+#define INTC_ICDICPR14_TINT56                   (0x01000000uL)
+#define INTC_ICDICPR14_TINT57                   (0x02000000uL)
+#define INTC_ICDICPR14_TINT58                   (0x04000000uL)
+#define INTC_ICDICPR14_TINT59                   (0x08000000uL)
+#define INTC_ICDICPR14_TINT60                   (0x10000000uL)
+#define INTC_ICDICPR14_TINT61                   (0x20000000uL)
+#define INTC_ICDICPR14_TINT62                   (0x40000000uL)
+#define INTC_ICDICPR14_TINT63                   (0x80000000uL)
+
+#define INTC_ICDICPR15_TINT64                   (0x00000001uL)
+#define INTC_ICDICPR15_TINT65                   (0x00000002uL)
+#define INTC_ICDICPR15_TINT66                   (0x00000004uL)
+#define INTC_ICDICPR15_TINT67                   (0x00000008uL)
+#define INTC_ICDICPR15_TINT68                   (0x00000010uL)
+#define INTC_ICDICPR15_TINT69                   (0x00000020uL)
+#define INTC_ICDICPR15_TINT70                   (0x00000040uL)
+#define INTC_ICDICPR15_TINT71                   (0x00000080uL)
+#define INTC_ICDICPR15_TINT72                   (0x00000100uL)
+#define INTC_ICDICPR15_TINT73                   (0x00000200uL)
+#define INTC_ICDICPR15_TINT74                   (0x00000400uL)
+#define INTC_ICDICPR15_TINT75                   (0x00000800uL)
+#define INTC_ICDICPR15_TINT76                   (0x00001000uL)
+#define INTC_ICDICPR15_TINT77                   (0x00002000uL)
+#define INTC_ICDICPR15_TINT78                   (0x00004000uL)
+#define INTC_ICDICPR15_TINT79                   (0x00008000uL)
+#define INTC_ICDICPR15_TINT80                   (0x00010000uL)
+#define INTC_ICDICPR15_TINT81                   (0x00020000uL)
+#define INTC_ICDICPR15_TINT82                   (0x00040000uL)
+#define INTC_ICDICPR15_TINT83                   (0x00080000uL)
+#define INTC_ICDICPR15_TINT84                   (0x00100000uL)
+#define INTC_ICDICPR15_TINT85                   (0x00200000uL)
+#define INTC_ICDICPR15_TINT86                   (0x00400000uL)
+#define INTC_ICDICPR15_TINT87                   (0x00800000uL)
+#define INTC_ICDICPR15_TINT88                   (0x01000000uL)
+#define INTC_ICDICPR15_TINT89                   (0x02000000uL)
+#define INTC_ICDICPR15_TINT90                   (0x04000000uL)
+#define INTC_ICDICPR15_TINT91                   (0x08000000uL)
+#define INTC_ICDICPR15_TINT92                   (0x10000000uL)
+#define INTC_ICDICPR15_TINT93                   (0x20000000uL)
+#define INTC_ICDICPR15_TINT94                   (0x40000000uL)
+#define INTC_ICDICPR15_TINT95                   (0x80000000uL)
+
+#define INTC_ICDICPR16_TINT96                   (0x00000001uL)
+#define INTC_ICDICPR16_TINT97                   (0x00000002uL)
+#define INTC_ICDICPR16_TINT98                   (0x00000004uL)
+#define INTC_ICDICPR16_TINT99                   (0x00000008uL)
+#define INTC_ICDICPR16_TINT100                  (0x00000010uL)
+#define INTC_ICDICPR16_TINT101                  (0x00000020uL)
+#define INTC_ICDICPR16_TINT102                  (0x00000040uL)
+#define INTC_ICDICPR16_TINT103                  (0x00000080uL)
+#define INTC_ICDICPR16_TINT104                  (0x00000100uL)
+#define INTC_ICDICPR16_TINT105                  (0x00000200uL)
+#define INTC_ICDICPR16_TINT106                  (0x00000400uL)
+#define INTC_ICDICPR16_TINT107                  (0x00000800uL)
+#define INTC_ICDICPR16_TINT108                  (0x00001000uL)
+#define INTC_ICDICPR16_TINT109                  (0x00002000uL)
+#define INTC_ICDICPR16_TINT110                  (0x00004000uL)
+#define INTC_ICDICPR16_TINT111                  (0x00008000uL)
+#define INTC_ICDICPR16_TINT112                  (0x00010000uL)
+#define INTC_ICDICPR16_TINT113                  (0x00020000uL)
+#define INTC_ICDICPR16_TINT114                  (0x00040000uL)
+#define INTC_ICDICPR16_TINT115                  (0x00080000uL)
+#define INTC_ICDICPR16_TINT116                  (0x00100000uL)
+#define INTC_ICDICPR16_TINT117                  (0x00200000uL)
+#define INTC_ICDICPR16_TINT118                  (0x00400000uL)
+#define INTC_ICDICPR16_TINT119                  (0x00800000uL)
+#define INTC_ICDICPR16_TINT120                  (0x01000000uL)
+#define INTC_ICDICPR16_TINT121                  (0x02000000uL)
+#define INTC_ICDICPR16_TINT122                  (0x04000000uL)
+#define INTC_ICDICPR16_TINT123                  (0x08000000uL)
+#define INTC_ICDICPR16_TINT124                  (0x10000000uL)
+#define INTC_ICDICPR16_TINT125                  (0x20000000uL)
+#define INTC_ICDICPR16_TINT126                  (0x40000000uL)
+#define INTC_ICDICPR16_TINT127                  (0x80000000uL)
+
+#define INTC_ICDICPR17_TINT128                  (0x00000001uL)
+#define INTC_ICDICPR17_TINT129                  (0x00000002uL)
+#define INTC_ICDICPR17_TINT130                  (0x00000004uL)
+#define INTC_ICDICPR17_TINT131                  (0x00000008uL)
+#define INTC_ICDICPR17_TINT132                  (0x00000010uL)
+#define INTC_ICDICPR17_TINT133                  (0x00000020uL)
+#define INTC_ICDICPR17_TINT134                  (0x00000040uL)
+#define INTC_ICDICPR17_TINT135                  (0x00000080uL)
+#define INTC_ICDICPR17_TINT136                  (0x00000100uL)
+#define INTC_ICDICPR17_TINT137                  (0x00000200uL)
+#define INTC_ICDICPR17_TINT138                  (0x00000400uL)
+#define INTC_ICDICPR17_TINT139                  (0x00000800uL)
+#define INTC_ICDICPR17_TINT140                  (0x00001000uL)
+#define INTC_ICDICPR17_TINT141                  (0x00002000uL)
+#define INTC_ICDICPR17_TINT142                  (0x00004000uL)
+#define INTC_ICDICPR17_TINT143                  (0x00008000uL)
+#define INTC_ICDICPR17_TINT144                  (0x00010000uL)
+#define INTC_ICDICPR17_TINT145                  (0x00020000uL)
+#define INTC_ICDICPR17_TINT146                  (0x00040000uL)
+#define INTC_ICDICPR17_TINT147                  (0x00080000uL)
+#define INTC_ICDICPR17_TINT148                  (0x00100000uL)
+#define INTC_ICDICPR17_TINT149                  (0x00200000uL)
+#define INTC_ICDICPR17_TINT150                  (0x00400000uL)
+#define INTC_ICDICPR17_TINT151                  (0x00800000uL)
+#define INTC_ICDICPR17_TINT152                  (0x01000000uL)
+#define INTC_ICDICPR17_TINT153                  (0x02000000uL)
+#define INTC_ICDICPR17_TINT154                  (0x04000000uL)
+#define INTC_ICDICPR17_TINT155                  (0x08000000uL)
+#define INTC_ICDICPR17_TINT156                  (0x10000000uL)
+#define INTC_ICDICPR17_TINT157                  (0x20000000uL)
+#define INTC_ICDICPR17_TINT158                  (0x40000000uL)
+#define INTC_ICDICPR17_TINT159                  (0x80000000uL)
+
+#define INTC_ICDICPR18_TINT160                  (0x00000001uL)
+#define INTC_ICDICPR18_TINT161                  (0x00000002uL)
+#define INTC_ICDICPR18_TINT162                  (0x00000004uL)
+#define INTC_ICDICPR18_TINT163                  (0x00000008uL)
+#define INTC_ICDICPR18_TINT164                  (0x00000010uL)
+#define INTC_ICDICPR18_TINT165                  (0x00000020uL)
+#define INTC_ICDICPR18_TINT166                  (0x00000040uL)
+#define INTC_ICDICPR18_TINT167                  (0x00000080uL)
+#define INTC_ICDICPR18_TINT168                  (0x00000100uL)
+#define INTC_ICDICPR18_TINT169                  (0x00000200uL)
+#define INTC_ICDICPR18_TINT170                  (0x00000400uL)
+
+#define INTC_ICDABR0_SW0                        (0x00000001uL)
+#define INTC_ICDABR0_SW1                        (0x00000002uL)
+#define INTC_ICDABR0_SW2                        (0x00000004uL)
+#define INTC_ICDABR0_SW3                        (0x00000008uL)
+#define INTC_ICDABR0_SW4                        (0x00000010uL)
+#define INTC_ICDABR0_SW5                        (0x00000020uL)
+#define INTC_ICDABR0_SW6                        (0x00000040uL)
+#define INTC_ICDABR0_SW7                        (0x00000080uL)
+#define INTC_ICDABR0_SW8                        (0x00000100uL)
+#define INTC_ICDABR0_SW9                        (0x00000200uL)
+#define INTC_ICDABR0_SW10                       (0x00000400uL)
+#define INTC_ICDABR0_SW11                       (0x00000800uL)
+#define INTC_ICDABR0_SW12                       (0x00001000uL)
+#define INTC_ICDABR0_SW13                       (0x00002000uL)
+#define INTC_ICDABR0_SW14                       (0x00004000uL)
+#define INTC_ICDABR0_SW15                       (0x00008000uL)
+#define INTC_ICDABR0_PMUIRQ0                    (0x00010000uL)
+#define INTC_ICDABR0_COMMRX0                    (0x00020000uL)
+#define INTC_ICDABR0_COMMTX0                    (0x00040000uL)
+#define INTC_ICDABR0_CTIIRQ0                    (0x00080000uL)
+
+#define INTC_ICDABR1_IRQ0                       (0x00000001uL)
+#define INTC_ICDABR1_IRQ1                       (0x00000002uL)
+#define INTC_ICDABR1_IRQ2                       (0x00000004uL)
+#define INTC_ICDABR1_IRQ3                       (0x00000008uL)
+#define INTC_ICDABR1_IRQ4                       (0x00000010uL)
+#define INTC_ICDABR1_IRQ5                       (0x00000020uL)
+#define INTC_ICDABR1_IRQ6                       (0x00000040uL)
+#define INTC_ICDABR1_IRQ7                       (0x00000080uL)
+#define INTC_ICDABR1_PL310ERR                   (0x00000100uL)
+#define INTC_ICDABR1_DMAINT0                    (0x00000200uL)
+#define INTC_ICDABR1_DMAINT1                    (0x00000400uL)
+#define INTC_ICDABR1_DMAINT2                    (0x00000800uL)
+#define INTC_ICDABR1_DMAINT3                    (0x00001000uL)
+#define INTC_ICDABR1_DMAINT4                    (0x00002000uL)
+#define INTC_ICDABR1_DMAINT5                    (0x00004000uL)
+#define INTC_ICDABR1_DMAINT6                    (0x00008000uL)
+#define INTC_ICDABR1_DMAINT7                    (0x00010000uL)
+#define INTC_ICDABR1_DMAINT8                    (0x00020000uL)
+#define INTC_ICDABR1_DMAINT9                    (0x00040000uL)
+#define INTC_ICDABR1_DMAINT10                   (0x00080000uL)
+#define INTC_ICDABR1_DMAINT11                   (0x00100000uL)
+#define INTC_ICDABR1_DMAINT12                   (0x00200000uL)
+#define INTC_ICDABR1_DMAINT13                   (0x00400000uL)
+#define INTC_ICDABR1_DMAINT14                   (0x00800000uL)
+#define INTC_ICDABR1_DMAINT15                   (0x01000000uL)
+#define INTC_ICDABR1_DMAERR                     (0x02000000uL)
+
+#define INTC_ICDABR2_USBI0                      (0x00000200uL)
+#define INTC_ICDABR2_USBI1                      (0x00000400uL)
+#define INTC_ICDABR2_S0_VI_VSYNC0               (0x00000800uL)
+#define INTC_ICDABR2_S0_LO_VSYNC0               (0x00001000uL)
+#define INTC_ICDABR2_S0_VSYNCERR0               (0x00002000uL)
+#define INTC_ICDABR2_GR3_VLINE0                 (0x00004000uL)
+#define INTC_ICDABR2_S0_VFIELD0                 (0x00008000uL)
+#define INTC_ICDABR2_IV1_VBUFERR0               (0x00010000uL)
+#define INTC_ICDABR2_IV3_VBUFERR0               (0x00020000uL)
+#define INTC_ICDABR2_IV5_VBUFERR0               (0x00040000uL)
+#define INTC_ICDABR2_IV6_VBUFERR0               (0x00080000uL)
+#define INTC_ICDABR2_S0_WLINE0                  (0x00100000uL)
+#define INTC_ICDABR2_S1_VI_VSYNC0               (0x00200000uL)
+#define INTC_ICDABR2_S1_LO_VSYNC0               (0x00400000uL)
+#define INTC_ICDABR2_S1_VSYNCERR0               (0x00800000uL)
+#define INTC_ICDABR2_S1_VFIELD0                 (0x01000000uL)
+#define INTC_ICDABR2_IV2_VBUFERR0               (0x02000000uL)
+#define INTC_ICDABR2_IV4_VBUFERR0               (0x04000000uL)
+#define INTC_ICDABR2_S1_WLINE0                  (0x08000000uL)
+#define INTC_ICDABR2_OIR_VI_VSYNC0              (0x10000000uL)
+#define INTC_ICDABR2_OIR_LO_VSYNC0              (0x20000000uL)
+#define INTC_ICDABR2_OIR_VSYNCERR0              (0x40000000uL)
+#define INTC_ICDABR2_OIR_VFIELD0                (0x80000000uL)
+
+#define INTC_ICDABR3_IV7_VBUFERR0               (0x00000001uL)
+#define INTC_ICDABR3_IV8_VBUFERR0               (0x00000002uL)
+#define INTC_ICDABR3_S0_VI_VSYNC1               (0x00000008uL)
+#define INTC_ICDABR3_S0_LO_VSYNC1               (0x00000010uL)
+#define INTC_ICDABR3_S0_VSYNCERR1               (0x00000020uL)
+#define INTC_ICDABR3_GR3_VLINE1                 (0x00000040uL)
+#define INTC_ICDABR3_S0_VFIELD1                 (0x00000080uL)
+#define INTC_ICDABR3_IV1_VBUFERR1               (0x00000100uL)
+#define INTC_ICDABR3_IV3_VBUFERR1               (0x00000200uL)
+#define INTC_ICDABR3_IV5_VBUFERR1               (0x00000400uL)
+#define INTC_ICDABR3_IV6_VBUFERR1               (0x00000800uL)
+#define INTC_ICDABR3_S0_WLINE1                  (0x00001000uL)
+#define INTC_ICDABR3_S1_VI_VSYNC1               (0x00002000uL)
+#define INTC_ICDABR3_S1_LO_VSYNC1               (0x00004000uL)
+#define INTC_ICDABR3_S1_VSYNCERR1               (0x00008000uL)
+#define INTC_ICDABR3_S1_VFIELD1                 (0x00010000uL)
+#define INTC_ICDABR3_IV2_VBUFERR1               (0x00020000uL)
+#define INTC_ICDABR3_IV4_VBUFERR1               (0x00040000uL)
+#define INTC_ICDABR3_S1_WLINE1                  (0x00080000uL)
+#define INTC_ICDABR3_OIR_VI_VSYNC1              (0x00100000uL)
+#define INTC_ICDABR3_OIR_LO_VSYNC1              (0x00200000uL)
+#define INTC_ICDABR3_OIR_VLINE1                 (0x00400000uL)
+#define INTC_ICDABR3_OIR_VFIELD1                (0x00800000uL)
+#define INTC_ICDABR3_IV7_VBUFERR1               (0x01000000uL)
+#define INTC_ICDABR3_IV8_VBUFERR1               (0x02000000uL)
+#define INTC_ICDABR3_IMRDI                      (0x08000000uL)
+#define INTC_ICDABR3_IMR2I0                     (0x10000000uL)
+#define INTC_ICDABR3_IMR2I1                     (0x20000000uL)
+#define INTC_ICDABR3_JEDI                       (0x40000000uL)
+#define INTC_ICDABR3_JDTI                       (0x80000000uL)
+
+#define INTC_ICDABR4_CMP0                       (0x00000001uL)
+#define INTC_ICDABR4_CMP1                       (0x00000002uL)
+#define INTC_ICDABR4_INT0                       (0x00000004uL)
+#define INTC_ICDABR4_INT1                       (0x00000008uL)
+#define INTC_ICDABR4_INT2                       (0x00000010uL)
+#define INTC_ICDABR4_INT3                       (0x00000020uL)
+#define INTC_ICDABR4_OSTM0TINT                  (0x00000040uL)
+#define INTC_ICDABR4_OSTM1TINT                  (0x00000080uL)
+#define INTC_ICDABR4_CMI                        (0x00000100uL)
+#define INTC_ICDABR4_WTOUT                      (0x00000200uL)
+#define INTC_ICDABR4_ITI                        (0x00000400uL)
+#define INTC_ICDABR4_TGI0A                      (0x00000800uL)
+#define INTC_ICDABR4_TGI0B                      (0x00001000uL)
+#define INTC_ICDABR4_TGI0C                      (0x00002000uL)
+#define INTC_ICDABR4_TGI0D                      (0x00004000uL)
+#define INTC_ICDABR4_TGI0V                      (0x00008000uL)
+#define INTC_ICDABR4_TGI0E                      (0x00010000uL)
+#define INTC_ICDABR4_TGI0F                      (0x00020000uL)
+#define INTC_ICDABR4_TGI1A                      (0x00040000uL)
+#define INTC_ICDABR4_TGI1B                      (0x00080000uL)
+#define INTC_ICDABR4_TGI1V                      (0x00100000uL)
+#define INTC_ICDABR4_TGI1U                      (0x00200000uL)
+#define INTC_ICDABR4_TGI2A                      (0x00400000uL)
+#define INTC_ICDABR4_TGI2B                      (0x00800000uL)
+#define INTC_ICDABR4_TGI2V                      (0x01000000uL)
+#define INTC_ICDABR4_TGI2U                      (0x02000000uL)
+#define INTC_ICDABR4_TGI3A                      (0x04000000uL)
+#define INTC_ICDABR4_TGI3B                      (0x08000000uL)
+#define INTC_ICDABR4_TGI3C                      (0x10000000uL)
+#define INTC_ICDABR4_TGI3D                      (0x20000000uL)
+#define INTC_ICDABR4_TGI3V                      (0x40000000uL)
+#define INTC_ICDABR4_TGI4A                      (0x80000000uL)
+
+#define INTC_ICDABR5_TGI4B                      (0x00000001uL)
+#define INTC_ICDABR5_TGI4C                      (0x00000002uL)
+#define INTC_ICDABR5_TGI4D                      (0x00000004uL)
+#define INTC_ICDABR5_TGI4V                      (0x00000008uL)
+#define INTC_ICDABR5_CMI1                       (0x00000010uL)
+#define INTC_ICDABR5_CMI2                       (0x00000020uL)
+#define INTC_ICDABR5_SGDEI0                     (0x00000040uL)
+#define INTC_ICDABR5_SGDEI1                     (0x00000080uL)
+#define INTC_ICDABR5_SGDEI2                     (0x00000100uL)
+#define INTC_ICDABR5_SGDEI3                     (0x00000200uL)
+#define INTC_ICDABR5_ADI                        (0x00000400uL)
+#define INTC_ICDABR5_LMTI                       (0x00000800uL)
+#define INTC_ICDABR5_SSII0                      (0x00001000uL)
+#define INTC_ICDABR5_SSIRXI0                    (0x00002000uL)
+#define INTC_ICDABR5_SSITXI0                    (0x00004000uL)
+#define INTC_ICDABR5_SSII1                      (0x00008000uL)
+#define INTC_ICDABR5_SSIRXI1                    (0x00010000uL)
+#define INTC_ICDABR5_SSITXI1                    (0x00020000uL)
+#define INTC_ICDABR5_SSII2                      (0x00040000uL)
+#define INTC_ICDABR5_SSIRTI2                    (0x00080000uL)
+#define INTC_ICDABR5_SSII3                      (0x00100000uL)
+#define INTC_ICDABR5_SSIRXI3                    (0x00200000uL)
+#define INTC_ICDABR5_SSITXI3                    (0x00400000uL)
+#define INTC_ICDABR5_SSII4                      (0x00800000uL)
+#define INTC_ICDABR5_SSIRTI4                    (0x01000000uL)
+#define INTC_ICDABR5_SSII5                      (0x02000000uL)
+#define INTC_ICDABR5_SSIRXI5                    (0x04000000uL)
+#define INTC_ICDABR5_SSITXI5                    (0x08000000uL)
+#define INTC_ICDABR5_SPDIFI                     (0x10000000uL)
+#define INTC_ICDABR5_INTIICTEI0                 (0x20000000uL)
+#define INTC_ICDABR5_INTIICRI0                  (0x40000000uL)
+#define INTC_ICDABR5_INTIICTI0                  (0x80000000uL)
+
+#define INTC_ICDABR6_INTIICSPI0                 (0x00000001uL)
+#define INTC_ICDABR6_INTIICSTI0                 (0x00000002uL)
+#define INTC_ICDABR6_INTIICNAKI0                (0x00000004uL)
+#define INTC_ICDABR6_INTIICALI0                 (0x00000008uL)
+#define INTC_ICDABR6_INTIICTMOI0                (0x00000010uL)
+#define INTC_ICDABR6_INTIICTEI1                 (0x00000020uL)
+#define INTC_ICDABR6_INTIICRI1                  (0x00000040uL)
+#define INTC_ICDABR6_INTIICTI1                  (0x00000080uL)
+#define INTC_ICDABR6_INTIICSPI1                 (0x00000100uL)
+#define INTC_ICDABR6_INTIICSTI1                 (0x00000200uL)
+#define INTC_ICDABR6_INTIICNAKI1                (0x00000400uL)
+#define INTC_ICDABR6_INTIICALI1                 (0x00000800uL)
+#define INTC_ICDABR6_INTIICTMOI1                (0x00001000uL)
+#define INTC_ICDABR6_INTIICTEI2                 (0x00002000uL)
+#define INTC_ICDABR6_INTIICRI2                  (0x00004000uL)
+#define INTC_ICDABR6_INTIICTI2                  (0x00008000uL)
+#define INTC_ICDABR6_INTIICSPI2                 (0x00010000uL)
+#define INTC_ICDABR6_INTIICSTI2                 (0x00020000uL)
+#define INTC_ICDABR6_INTIICNAKI2                (0x00040000uL)
+#define INTC_ICDABR6_INTIICALI2                 (0x00080000uL)
+#define INTC_ICDABR6_INTIICTMOI2                (0x00100000uL)
+#define INTC_ICDABR6_INTIICTEI3                 (0x00200000uL)
+#define INTC_ICDABR6_INTIICRI3                  (0x00400000uL)
+#define INTC_ICDABR6_INTIICTI3                  (0x00800000uL)
+#define INTC_ICDABR6_INTIICSPI3                 (0x01000000uL)
+#define INTC_ICDABR6_INTIICSTI3                 (0x02000000uL)
+#define INTC_ICDABR6_INTIICNAKI3                (0x04000000uL)
+#define INTC_ICDABR6_INTIICALI3                 (0x08000000uL)
+#define INTC_ICDABR6_INTIICTMOI3                (0x10000000uL)
+#define INTC_ICDABR6_BRI0                       (0x20000000uL)
+#define INTC_ICDABR6_ERI0                       (0x40000000uL)
+#define INTC_ICDABR6_RXI0                       (0x80000000uL)
+
+#define INTC_ICDABR7_TXI0                       (0x00000001uL)
+#define INTC_ICDABR7_BRI1                       (0x00000002uL)
+#define INTC_ICDABR7_ERI1                       (0x00000004uL)
+#define INTC_ICDABR7_RXI1                       (0x00000008uL)
+#define INTC_ICDABR7_TXI1                       (0x00000010uL)
+#define INTC_ICDABR7_BRI2                       (0x00000020uL)
+#define INTC_ICDABR7_ERI2                       (0x00000040uL)
+#define INTC_ICDABR7_RXI2                       (0x00000080uL)
+#define INTC_ICDABR7_TXI2                       (0x00000100uL)
+#define INTC_ICDABR7_BRI3                       (0x00000200uL)
+#define INTC_ICDABR7_ERI3                       (0x00000400uL)
+#define INTC_ICDABR7_RXI3                       (0x00000800uL)
+#define INTC_ICDABR7_TXI3                       (0x00001000uL)
+#define INTC_ICDABR7_BRI4                       (0x00002000uL)
+#define INTC_ICDABR7_ERI4                       (0x00004000uL)
+#define INTC_ICDABR7_RXI4                       (0x00008000uL)
+#define INTC_ICDABR7_TXI4                       (0x00010000uL)
+#define INTC_ICDABR7_BRI5                       (0x00020000uL)
+#define INTC_ICDABR7_ERI5                       (0x00040000uL)
+#define INTC_ICDABR7_RXI5                       (0x00080000uL)
+#define INTC_ICDABR7_TXI5                       (0x00100000uL)
+#define INTC_ICDABR7_BRI6                       (0x00200000uL)
+#define INTC_ICDABR7_ERI6                       (0x00400000uL)
+#define INTC_ICDABR7_RXI6                       (0x00800000uL)
+#define INTC_ICDABR7_TXI6                       (0x01000000uL)
+#define INTC_ICDABR7_BRI7                       (0x02000000uL)
+#define INTC_ICDABR7_ERI7                       (0x04000000uL)
+#define INTC_ICDABR7_RXI7                       (0x08000000uL)
+#define INTC_ICDABR7_TXI7                       (0x10000000uL)
+#define INTC_ICDABR7_INTRCANGERR                (0x20000000uL)
+#define INTC_ICDABR7_INTRCANGRECC               (0x40000000uL)
+#define INTC_ICDABR7_INTRCAN0REC                (0x80000000uL)
+
+#define INTC_ICDABR8_INTRCAN0ERR                (0x00000001uL)
+#define INTC_ICDABR8_INTRCAN0TRX                (0x00000002uL)
+#define INTC_ICDABR8_INTRCAN1REC                (0x00000004uL)
+#define INTC_ICDABR8_INTRCAN1ERR                (0x00000008uL)
+#define INTC_ICDABR8_INTRCAN1TRX                (0x00000010uL)
+#define INTC_ICDABR8_INTRCAN2REC                (0x00000020uL)
+#define INTC_ICDABR8_INTRCAN2ERR                (0x00000040uL)
+#define INTC_ICDABR8_INTRCAN2TRX                (0x00000080uL)
+#define INTC_ICDABR8_INTRCAN3REC                (0x00000100uL)
+#define INTC_ICDABR8_INTRCAN3ERR                (0x00000200uL)
+#define INTC_ICDABR8_INTRCAN3TRX                (0x00000400uL)
+#define INTC_ICDABR8_INTRCAN4REC                (0x00000800uL)
+#define INTC_ICDABR8_INTRCAN4ERR                (0x00001000uL)
+#define INTC_ICDABR8_INTRCAN4TRX                (0x00002000uL)
+#define INTC_ICDABR8_SPEI0                      (0x00004000uL)
+#define INTC_ICDABR8_SPRI0                      (0x00008000uL)
+#define INTC_ICDABR8_SPTI0                      (0x00010000uL)
+#define INTC_ICDABR8_SPEI1                      (0x00020000uL)
+#define INTC_ICDABR8_SPRI1                      (0x00040000uL)
+#define INTC_ICDABR8_SPTI1                      (0x00080000uL)
+#define INTC_ICDABR8_SPEI2                      (0x00100000uL)
+#define INTC_ICDABR8_SPRI2                      (0x00200000uL)
+#define INTC_ICDABR8_SPTI2                      (0x00400000uL)
+#define INTC_ICDABR8_SPEI3                      (0x00800000uL)
+#define INTC_ICDABR8_SPRI3                      (0x01000000uL)
+#define INTC_ICDABR8_SPTI3                      (0x02000000uL)
+#define INTC_ICDABR8_SPEI4                      (0x04000000uL)
+#define INTC_ICDABR8_SPRI4                      (0x08000000uL)
+#define INTC_ICDABR8_SPTI4                      (0x10000000uL)
+#define INTC_ICDABR8_IEBBTD                     (0x20000000uL)
+#define INTC_ICDABR8_IEBBTERR                   (0x40000000uL)
+#define INTC_ICDABR8_IEBBTSTA                   (0x80000000uL)
+
+#define INTC_ICDABR9_IEBBTV                     (0x00000001uL)
+#define INTC_ICDABR9_ISY                        (0x00000002uL)
+#define INTC_ICDABR9_IERR                       (0x00000004uL)
+#define INTC_ICDABR9_ITARG                      (0x00000008uL)
+#define INTC_ICDABR9_ISEC                       (0x00000010uL)
+#define INTC_ICDABR9_IBUF                       (0x00000020uL)
+#define INTC_ICDABR9_IREADY                     (0x00000040uL)
+#define INTC_ICDABR9_FLSTE                      (0x00000080uL)
+#define INTC_ICDABR9_FLTENDI                    (0x00000100uL)
+#define INTC_ICDABR9_FLTREQ0I                   (0x00000200uL)
+#define INTC_ICDABR9_FLTREQ1I                   (0x00000400uL)
+#define INTC_ICDABR9_MMC0                       (0x00000800uL)
+#define INTC_ICDABR9_MMC1                       (0x00001000uL)
+#define INTC_ICDABR9_MMC2                       (0x00002000uL)
+#define INTC_ICDABR9_SDHI0_3                    (0x00004000uL)
+#define INTC_ICDABR9_SDHI0_0                    (0x00008000uL)
+#define INTC_ICDABR9_SDHI0_1                    (0x00010000uL)
+#define INTC_ICDABR9_SDHI1_3                    (0x00020000uL)
+#define INTC_ICDABR9_SDHI1_0                    (0x00040000uL)
+#define INTC_ICDABR9_SDHI1_1                    (0x00080000uL)
+#define INTC_ICDABR9_ARM                        (0x00100000uL)
+#define INTC_ICDABR9_PRD                        (0x00200000uL)
+#define INTC_ICDABR9_CUP                        (0x00400000uL)
+#define INTC_ICDABR9_SCUAI0                     (0x00800000uL)
+#define INTC_ICDABR9_SCUAI1                     (0x01000000uL)
+#define INTC_ICDABR9_SCUFDI0                    (0x02000000uL)
+#define INTC_ICDABR9_SCUFDI1                    (0x04000000uL)
+#define INTC_ICDABR9_SCUFDI2                    (0x08000000uL)
+#define INTC_ICDABR9_SCUFDI3                    (0x10000000uL)
+#define INTC_ICDABR9_SCUFUI0                    (0x20000000uL)
+#define INTC_ICDABR9_SCUFUI1                    (0x40000000uL)
+#define INTC_ICDABR9_SCUFUI2                    (0x80000000uL)
+
+#define INTC_ICDABR10_SCUFUI3                   (0x00000001uL)
+#define INTC_ICDABR10_SCUDVI0                   (0x00000002uL)
+#define INTC_ICDABR10_SCUDVI1                   (0x00000004uL)
+#define INTC_ICDABR10_SCUDVI2                   (0x00000008uL)
+#define INTC_ICDABR10_SCUDVI3                   (0x00000010uL)
+#define INTC_ICDABR10_MLB_CINT                  (0x00000020uL)
+#define INTC_ICDABR10_MLB_SINT                  (0x00000040uL)
+#define INTC_ICDABR10_DRC0                      (0x00000080uL)
+#define INTC_ICDABR10_DRC1                      (0x00000100uL)
+#define INTC_ICDABR10_LINI0_INT_T               (0x00000800uL)
+#define INTC_ICDABR10_LINI0_INT_R               (0x00001000uL)
+#define INTC_ICDABR10_LINI0_INT_S               (0x00002000uL)
+#define INTC_ICDABR10_LINI0_INT_M               (0x00004000uL)
+#define INTC_ICDABR10_LINI1_INT_T               (0x00008000uL)
+#define INTC_ICDABR10_LINI1_INT_R               (0x00010000uL)
+#define INTC_ICDABR10_LINI1_INT_S               (0x00020000uL)
+#define INTC_ICDABR10_LINI1_INT_M               (0x00040000uL)
+#define INTC_ICDABR10_ERI0                      (0x08000000uL)
+#define INTC_ICDABR10_RXI0                      (0x10000000uL)
+#define INTC_ICDABR10_TXI0                      (0x20000000uL)
+#define INTC_ICDABR10_TEI0                      (0x40000000uL)
+#define INTC_ICDABR10_ERI1                      (0x80000000uL)
+
+#define INTC_ICDABR11_RXI1                      (0x00000001uL)
+#define INTC_ICDABR11_TXI1                      (0x00000002uL)
+#define INTC_ICDABR11_TEI1                      (0x00000004uL)
+#define INTC_ICDABR11_AVBI_DATA                 (0x00000008uL)
+#define INTC_ICDABR11_AVBI_ERROR                (0x00000010uL)
+#define INTC_ICDABR11_AVBI_MANAGE               (0x00000020uL)
+#define INTC_ICDABR11_AVBI_MAC                  (0x00000040uL)
+#define INTC_ICDABR11_ETHERI                    (0x00000080uL)
+#define INTC_ICDABR11_CEUI                      (0x00001000uL)
+#define INTC_ICDABR11_H2XMLB_ERRINT             (0x20000000uL)
+#define INTC_ICDABR11_H2XIC1_ERRINT             (0x40000000uL)
+#define INTC_ICDABR11_X2HPERI1_ERRINT           (0x80000000uL)
+
+#define INTC_ICDABR12_X2HPERI2_ERRINT           (0x00000001uL)
+#define INTC_ICDABR12_X2HPERI34_ERRINT          (0x00000002uL)
+#define INTC_ICDABR12_X2HPERI5_ERRINT           (0x00000004uL)
+#define INTC_ICDABR12_X2HPERI67_ERRINT          (0x00000008uL)
+#define INTC_ICDABR12_X2HDBGR_ERRINT            (0x00000010uL)
+#define INTC_ICDABR12_X2HBSC_ERRINT             (0x00000020uL)
+#define INTC_ICDABR12_X2HSPI1_ERRINT            (0x00000040uL)
+#define INTC_ICDABR12_X2HSPI2_ERRINT            (0x00000080uL)
+#define INTC_ICDABR12_PRRI                      (0x00000100uL)
+#define INTC_ICDABR12_IFEI0                     (0x00000200uL)
+#define INTC_ICDABR12_OFFI0                     (0x00000400uL)
+#define INTC_ICDABR12_PFVEI0                    (0x00000800uL)
+#define INTC_ICDABR12_IFEI1                     (0x00001000uL)
+#define INTC_ICDABR12_OFFI1                     (0x00002000uL)
+#define INTC_ICDABR12_PFVEI1                    (0x00004000uL)
+
+#define INTC_ICDABR13_TINT0                     (0x00000001uL)
+#define INTC_ICDABR13_TINT1                     (0x00000002uL)
+#define INTC_ICDABR13_TINT2                     (0x00000004uL)
+#define INTC_ICDABR13_TINT3                     (0x00000008uL)
+#define INTC_ICDABR13_TINT4                     (0x00000010uL)
+#define INTC_ICDABR13_TINT5                     (0x00000020uL)
+#define INTC_ICDABR13_TINT6                     (0x00000040uL)
+#define INTC_ICDABR13_TINT7                     (0x00000080uL)
+#define INTC_ICDABR13_TINT8                     (0x00000100uL)
+#define INTC_ICDABR13_TINT9                     (0x00000200uL)
+#define INTC_ICDABR13_TINT10                    (0x00000400uL)
+#define INTC_ICDABR13_TINT11                    (0x00000800uL)
+#define INTC_ICDABR13_TINT12                    (0x00001000uL)
+#define INTC_ICDABR13_TINT13                    (0x00002000uL)
+#define INTC_ICDABR13_TINT14                    (0x00004000uL)
+#define INTC_ICDABR13_TINT15                    (0x00008000uL)
+#define INTC_ICDABR13_TINT16                    (0x00010000uL)
+#define INTC_ICDABR13_TINT17                    (0x00020000uL)
+#define INTC_ICDABR13_TINT18                    (0x00040000uL)
+#define INTC_ICDABR13_TINT19                    (0x00080000uL)
+#define INTC_ICDABR13_TINT20                    (0x00100000uL)
+#define INTC_ICDABR13_TINT21                    (0x00200000uL)
+#define INTC_ICDABR13_TINT22                    (0x00400000uL)
+#define INTC_ICDABR13_TINT23                    (0x00800000uL)
+#define INTC_ICDABR13_TINT24                    (0x01000000uL)
+#define INTC_ICDABR13_TINT25                    (0x02000000uL)
+#define INTC_ICDABR13_TINT26                    (0x04000000uL)
+#define INTC_ICDABR13_TINT27                    (0x08000000uL)
+#define INTC_ICDABR13_TINT28                    (0x10000000uL)
+#define INTC_ICDABR13_TINT29                    (0x20000000uL)
+#define INTC_ICDABR13_TINT30                    (0x40000000uL)
+#define INTC_ICDABR13_TINT31                    (0x80000000uL)
+
+#define INTC_ICDABR14_TINT32                    (0x00000001uL)
+#define INTC_ICDABR14_TINT33                    (0x00000002uL)
+#define INTC_ICDABR14_TINT34                    (0x00000004uL)
+#define INTC_ICDABR14_TINT35                    (0x00000008uL)
+#define INTC_ICDABR14_TINT36                    (0x00000010uL)
+#define INTC_ICDABR14_TINT37                    (0x00000020uL)
+#define INTC_ICDABR14_TINT38                    (0x00000040uL)
+#define INTC_ICDABR14_TINT39                    (0x00000080uL)
+#define INTC_ICDABR14_TINT40                    (0x00000100uL)
+#define INTC_ICDABR14_TINT41                    (0x00000200uL)
+#define INTC_ICDABR14_TINT42                    (0x00000400uL)
+#define INTC_ICDABR14_TINT43                    (0x00000800uL)
+#define INTC_ICDABR14_TINT44                    (0x00001000uL)
+#define INTC_ICDABR14_TINT45                    (0x00002000uL)
+#define INTC_ICDABR14_TINT46                    (0x00004000uL)
+#define INTC_ICDABR14_TINT47                    (0x00008000uL)
+#define INTC_ICDABR14_TINT48                    (0x00010000uL)
+#define INTC_ICDABR14_TINT49                    (0x00020000uL)
+#define INTC_ICDABR14_TINT50                    (0x00040000uL)
+#define INTC_ICDABR14_TINT51                    (0x00080000uL)
+#define INTC_ICDABR14_TINT52                    (0x00100000uL)
+#define INTC_ICDABR14_TINT53                    (0x00200000uL)
+#define INTC_ICDABR14_TINT54                    (0x00400000uL)
+#define INTC_ICDABR14_TINT55                    (0x00800000uL)
+#define INTC_ICDABR14_TINT56                    (0x01000000uL)
+#define INTC_ICDABR14_TINT57                    (0x02000000uL)
+#define INTC_ICDABR14_TINT58                    (0x04000000uL)
+#define INTC_ICDABR14_TINT59                    (0x08000000uL)
+#define INTC_ICDABR14_TINT60                    (0x10000000uL)
+#define INTC_ICDABR14_TINT61                    (0x20000000uL)
+#define INTC_ICDABR14_TINT62                    (0x40000000uL)
+#define INTC_ICDABR14_TINT63                    (0x80000000uL)
+
+#define INTC_ICDABR15_TINT64                    (0x00000001uL)
+#define INTC_ICDABR15_TINT65                    (0x00000002uL)
+#define INTC_ICDABR15_TINT66                    (0x00000004uL)
+#define INTC_ICDABR15_TINT67                    (0x00000008uL)
+#define INTC_ICDABR15_TINT68                    (0x00000010uL)
+#define INTC_ICDABR15_TINT69                    (0x00000020uL)
+#define INTC_ICDABR15_TINT70                    (0x00000040uL)
+#define INTC_ICDABR15_TINT71                    (0x00000080uL)
+#define INTC_ICDABR15_TINT72                    (0x00000100uL)
+#define INTC_ICDABR15_TINT73                    (0x00000200uL)
+#define INTC_ICDABR15_TINT74                    (0x00000400uL)
+#define INTC_ICDABR15_TINT75                    (0x00000800uL)
+#define INTC_ICDABR15_TINT76                    (0x00001000uL)
+#define INTC_ICDABR15_TINT77                    (0x00002000uL)
+#define INTC_ICDABR15_TINT78                    (0x00004000uL)
+#define INTC_ICDABR15_TINT79                    (0x00008000uL)
+#define INTC_ICDABR15_TINT80                    (0x00010000uL)
+#define INTC_ICDABR15_TINT81                    (0x00020000uL)
+#define INTC_ICDABR15_TINT82                    (0x00040000uL)
+#define INTC_ICDABR15_TINT83                    (0x00080000uL)
+#define INTC_ICDABR15_TINT84                    (0x00100000uL)
+#define INTC_ICDABR15_TINT85                    (0x00200000uL)
+#define INTC_ICDABR15_TINT86                    (0x00400000uL)
+#define INTC_ICDABR15_TINT87                    (0x00800000uL)
+#define INTC_ICDABR15_TINT88                    (0x01000000uL)
+#define INTC_ICDABR15_TINT89                    (0x02000000uL)
+#define INTC_ICDABR15_TINT90                    (0x04000000uL)
+#define INTC_ICDABR15_TINT91                    (0x08000000uL)
+#define INTC_ICDABR15_TINT92                    (0x10000000uL)
+#define INTC_ICDABR15_TINT93                    (0x20000000uL)
+#define INTC_ICDABR15_TINT94                    (0x40000000uL)
+#define INTC_ICDABR15_TINT95                    (0x80000000uL)
+
+#define INTC_ICDABR16_TINT96                    (0x00000001uL)
+#define INTC_ICDABR16_TINT97                    (0x00000002uL)
+#define INTC_ICDABR16_TINT98                    (0x00000004uL)
+#define INTC_ICDABR16_TINT99                    (0x00000008uL)
+#define INTC_ICDABR16_TINT100                   (0x00000010uL)
+#define INTC_ICDABR16_TINT101                   (0x00000020uL)
+#define INTC_ICDABR16_TINT102                   (0x00000040uL)
+#define INTC_ICDABR16_TINT103                   (0x00000080uL)
+#define INTC_ICDABR16_TINT104                   (0x00000100uL)
+#define INTC_ICDABR16_TINT105                   (0x00000200uL)
+#define INTC_ICDABR16_TINT106                   (0x00000400uL)
+#define INTC_ICDABR16_TINT107                   (0x00000800uL)
+#define INTC_ICDABR16_TINT108                   (0x00001000uL)
+#define INTC_ICDABR16_TINT109                   (0x00002000uL)
+#define INTC_ICDABR16_TINT110                   (0x00004000uL)
+#define INTC_ICDABR16_TINT111                   (0x00008000uL)
+#define INTC_ICDABR16_TINT112                   (0x00010000uL)
+#define INTC_ICDABR16_TINT113                   (0x00020000uL)
+#define INTC_ICDABR16_TINT114                   (0x00040000uL)
+#define INTC_ICDABR16_TINT115                   (0x00080000uL)
+#define INTC_ICDABR16_TINT116                   (0x00100000uL)
+#define INTC_ICDABR16_TINT117                   (0x00200000uL)
+#define INTC_ICDABR16_TINT118                   (0x00400000uL)
+#define INTC_ICDABR16_TINT119                   (0x00800000uL)
+#define INTC_ICDABR16_TINT120                   (0x01000000uL)
+#define INTC_ICDABR16_TINT121                   (0x02000000uL)
+#define INTC_ICDABR16_TINT122                   (0x04000000uL)
+#define INTC_ICDABR16_TINT123                   (0x08000000uL)
+#define INTC_ICDABR16_TINT124                   (0x10000000uL)
+#define INTC_ICDABR16_TINT125                   (0x20000000uL)
+#define INTC_ICDABR16_TINT126                   (0x40000000uL)
+#define INTC_ICDABR16_TINT127                   (0x80000000uL)
+
+#define INTC_ICDABR17_TINT128                   (0x00000001uL)
+#define INTC_ICDABR17_TINT129                   (0x00000002uL)
+#define INTC_ICDABR17_TINT130                   (0x00000004uL)
+#define INTC_ICDABR17_TINT131                   (0x00000008uL)
+#define INTC_ICDABR17_TINT132                   (0x00000010uL)
+#define INTC_ICDABR17_TINT133                   (0x00000020uL)
+#define INTC_ICDABR17_TINT134                   (0x00000040uL)
+#define INTC_ICDABR17_TINT135                   (0x00000080uL)
+#define INTC_ICDABR17_TINT136                   (0x00000100uL)
+#define INTC_ICDABR17_TINT137                   (0x00000200uL)
+#define INTC_ICDABR17_TINT138                   (0x00000400uL)
+#define INTC_ICDABR17_TINT139                   (0x00000800uL)
+#define INTC_ICDABR17_TINT140                   (0x00001000uL)
+#define INTC_ICDABR17_TINT141                   (0x00002000uL)
+#define INTC_ICDABR17_TINT142                   (0x00004000uL)
+#define INTC_ICDABR17_TINT143                   (0x00008000uL)
+#define INTC_ICDABR17_TINT144                   (0x00010000uL)
+#define INTC_ICDABR17_TINT145                   (0x00020000uL)
+#define INTC_ICDABR17_TINT146                   (0x00040000uL)
+#define INTC_ICDABR17_TINT147                   (0x00080000uL)
+#define INTC_ICDABR17_TINT148                   (0x00100000uL)
+#define INTC_ICDABR17_TINT149                   (0x00200000uL)
+#define INTC_ICDABR17_TINT150                   (0x00400000uL)
+#define INTC_ICDABR17_TINT151                   (0x00800000uL)
+#define INTC_ICDABR17_TINT152                   (0x01000000uL)
+#define INTC_ICDABR17_TINT153                   (0x02000000uL)
+#define INTC_ICDABR17_TINT154                   (0x04000000uL)
+#define INTC_ICDABR17_TINT155                   (0x08000000uL)
+#define INTC_ICDABR17_TINT156                   (0x10000000uL)
+#define INTC_ICDABR17_TINT157                   (0x20000000uL)
+#define INTC_ICDABR17_TINT158                   (0x40000000uL)
+#define INTC_ICDABR17_TINT159                   (0x80000000uL)
+
+#define INTC_ICDABR18_TINT160                   (0x00000001uL)
+#define INTC_ICDABR18_TINT161                   (0x00000002uL)
+#define INTC_ICDABR18_TINT162                   (0x00000004uL)
+#define INTC_ICDABR18_TINT163                   (0x00000008uL)
+#define INTC_ICDABR18_TINT164                   (0x00000010uL)
+#define INTC_ICDABR18_TINT165                   (0x00000020uL)
+#define INTC_ICDABR18_TINT166                   (0x00000040uL)
+#define INTC_ICDABR18_TINT167                   (0x00000080uL)
+#define INTC_ICDABR18_TINT168                   (0x00000100uL)
+#define INTC_ICDABR18_TINT169                   (0x00000200uL)
+#define INTC_ICDABR18_TINT170                   (0x00000400uL)
+
+#define INTC_ICDIPR0_SW0                        (0x000000FFuL)
+#define INTC_ICDIPR0_SW1                        (0x0000FF00uL)
+#define INTC_ICDIPR0_SW2                        (0x00FF0000uL)
+#define INTC_ICDIPR0_SW3                        (0xFF000000uL)
+
+#define INTC_ICDIPR1_SW4                        (0x000000FFuL)
+#define INTC_ICDIPR1_SW5                        (0x0000FF00uL)
+#define INTC_ICDIPR1_SW6                        (0x00FF0000uL)
+#define INTC_ICDIPR1_SW7                        (0xFF000000uL)
+
+#define INTC_ICDIPR2_SW8                        (0x000000FFuL)
+#define INTC_ICDIPR2_SW9                        (0x0000FF00uL)
+#define INTC_ICDIPR2_SW10                       (0x00FF0000uL)
+#define INTC_ICDIPR2_SW11                       (0xFF000000uL)
+
+#define INTC_ICDIPR3_SW12                       (0x000000FFuL)
+#define INTC_ICDIPR3_SW13                       (0x0000FF00uL)
+#define INTC_ICDIPR3_SW14                       (0x00FF0000uL)
+#define INTC_ICDIPR3_SW15                       (0xFF000000uL)
+
+#define INTC_ICDIPR4_PMUIRQ0                    (0x000000FFuL)
+#define INTC_ICDIPR4_COMMRX0                    (0x0000FF00uL)
+#define INTC_ICDIPR4_COMMTX0                    (0x00FF0000uL)
+#define INTC_ICDIPR4_CTIIRQ0                    (0xFF000000uL)
+
+#define INTC_ICDIPR8_IRQ0                       (0x000000FFuL)
+#define INTC_ICDIPR8_IRQ1                       (0x0000FF00uL)
+#define INTC_ICDIPR8_IRQ2                       (0x00FF0000uL)
+#define INTC_ICDIPR8_IRQ3                       (0xFF000000uL)
+
+#define INTC_ICDIPR9_IRQ4                       (0x000000FFuL)
+#define INTC_ICDIPR9_IRQ5                       (0x0000FF00uL)
+#define INTC_ICDIPR9_IRQ6                       (0x00FF0000uL)
+#define INTC_ICDIPR9_IRQ7                       (0xFF000000uL)
+
+#define INTC_ICDIPR10_PL310ERR                  (0x000000FFuL)
+#define INTC_ICDIPR10_DMAINT0                   (0x0000FF00uL)
+#define INTC_ICDIPR10_DMAINT1                   (0x00FF0000uL)
+#define INTC_ICDIPR10_DMAINT2                   (0xFF000000uL)
+
+#define INTC_ICDIPR11_DMAINT3                   (0x000000FFuL)
+#define INTC_ICDIPR11_DMAINT4                   (0x0000FF00uL)
+#define INTC_ICDIPR11_DMAINT5                   (0x00FF0000uL)
+#define INTC_ICDIPR11_DMAINT6                   (0xFF000000uL)
+
+#define INTC_ICDIPR12_DMAINT7                   (0x000000FFuL)
+#define INTC_ICDIPR12_DMAINT8                   (0x0000FF00uL)
+#define INTC_ICDIPR12_DMAINT9                   (0x00FF0000uL)
+#define INTC_ICDIPR12_DMAINT10                  (0xFF000000uL)
+
+#define INTC_ICDIPR13_DMAINT11                  (0x000000FFuL)
+#define INTC_ICDIPR13_DMAINT12                  (0x0000FF00uL)
+#define INTC_ICDIPR13_DMAINT13                  (0x00FF0000uL)
+#define INTC_ICDIPR13_DMAINT14                  (0xFF000000uL)
+
+#define INTC_ICDIPR14_DMAINT15                  (0x000000FFuL)
+#define INTC_ICDIPR14_DMAERR                    (0x0000FF00uL)
+
+#define INTC_ICDIPR18_USBI0                     (0x0000FF00uL)
+#define INTC_ICDIPR18_USBI1                     (0x00FF0000uL)
+#define INTC_ICDIPR18_S0_VI_VSYNC0              (0xFF000000uL)
+
+#define INTC_ICDIPR19_S0_LO_VSYNC0              (0x000000FFuL)
+#define INTC_ICDIPR19_S0_VSYNCERR0              (0x0000FF00uL)
+#define INTC_ICDIPR19_GR3_VLINE0                (0x00FF0000uL)
+#define INTC_ICDIPR19_S0_VFIELD0                (0xFF000000uL)
+
+#define INTC_ICDIPR20_IV1_VBUFERR0              (0x000000FFuL)
+#define INTC_ICDIPR20_IV3_VBUFERR0              (0x0000FF00uL)
+#define INTC_ICDIPR20_IV5_VBUFERR0              (0x00FF0000uL)
+#define INTC_ICDIPR20_IV6_VBUFERR0              (0xFF000000uL)
+
+#define INTC_ICDIPR21_S0_WLINE0                 (0x000000FFuL)
+#define INTC_ICDIPR21_S1_VI_VSYNC0              (0x0000FF00uL)
+#define INTC_ICDIPR21_S1_LO_VSYNC0              (0x00FF0000uL)
+#define INTC_ICDIPR21_S1_VSYNCERR0              (0xFF000000uL)
+
+#define INTC_ICDIPR22_S1_VFIELD0                (0x000000FFuL)
+#define INTC_ICDIPR22_IV2_VBUFERR0              (0x0000FF00uL)
+#define INTC_ICDIPR22_IV4_VBUFERR0              (0x00FF0000uL)
+#define INTC_ICDIPR22_S1_WLINE0                 (0xFF000000uL)
+
+#define INTC_ICDIPR23_OIR_VI_VSYNC0             (0x000000FFuL)
+#define INTC_ICDIPR23_OIR_LO_VSYNC0             (0x0000FF00uL)
+#define INTC_ICDIPR23_OIR_VSYNCERR0             (0x00FF0000uL)
+#define INTC_ICDIPR23_OIR_VFIELD0               (0xFF000000uL)
+
+#define INTC_ICDIPR24_IV7_VBUFERR0              (0x000000FFuL)
+#define INTC_ICDIPR24_IV8_VBUFERR0              (0x0000FF00uL)
+#define INTC_ICDIPR24_S0_VI_VSYNC1              (0xFF000000uL)
+
+#define INTC_ICDIPR25_S0_LO_VSYNC1              (0x000000FFuL)
+#define INTC_ICDIPR25_S0_VSYNCERR1              (0x0000FF00uL)
+#define INTC_ICDIPR25_GR3_VLINE1                (0x00FF0000uL)
+#define INTC_ICDIPR25_S0_VFIELD1                (0xFF000000uL)
+
+#define INTC_ICDIPR26_IV1_VBUFERR1              (0x000000FFuL)
+#define INTC_ICDIPR26_IV3_VBUFERR1              (0x0000FF00uL)
+#define INTC_ICDIPR26_IV5_VBUFERR1              (0x00FF0000uL)
+#define INTC_ICDIPR26_IV6_VBUFERR1              (0xFF000000uL)
+
+#define INTC_ICDIPR27_S0_WLINE1                 (0x000000FFuL)
+#define INTC_ICDIPR27_S1_VI_VSYNC1              (0x0000FF00uL)
+#define INTC_ICDIPR27_S1_LO_VSYNC1              (0x00FF0000uL)
+#define INTC_ICDIPR27_S1_VSYNCERR1              (0xFF000000uL)
+
+#define INTC_ICDIPR28_S1_VFIELD1                (0x000000FFuL)
+#define INTC_ICDIPR28_IV2_VBUFERR1              (0x0000FF00uL)
+#define INTC_ICDIPR28_IV4_VBUFERR1              (0x00FF0000uL)
+#define INTC_ICDIPR28_S1_WLINE1                 (0xFF000000uL)
+
+#define INTC_ICDIPR29_OIR_VI_VSYNC1             (0x000000FFuL)
+#define INTC_ICDIPR29_OIR_LO_VSYNC1             (0x0000FF00uL)
+#define INTC_ICDIPR29_OIR_VLINE1                (0x00FF0000uL)
+#define INTC_ICDIPR29_OIR_VFIELD1               (0xFF000000uL)
+
+#define INTC_ICDIPR30_IV7_VBUFERR1              (0x000000FFuL)
+#define INTC_ICDIPR30_IV8_VBUFERR1              (0x0000FF00uL)
+#define INTC_ICDIPR30_IMRDI                     (0xFF000000uL)
+
+#define INTC_ICDIPR31_IMR2I0                    (0x000000FFuL)
+#define INTC_ICDIPR31_IMR2I1                    (0x0000FF00uL)
+#define INTC_ICDIPR31_JEDI                      (0x00FF0000uL)
+#define INTC_ICDIPR31_JDTI                      (0xFF000000uL)
+
+#define INTC_ICDIPR32_CMP0                      (0x000000FFuL)
+#define INTC_ICDIPR32_CMP1                      (0x0000FF00uL)
+#define INTC_ICDIPR32_INT0                      (0x00FF0000uL)
+#define INTC_ICDIPR32_INT1                      (0xFF000000uL)
+
+#define INTC_ICDIPR33_INT2                      (0x000000FFuL)
+#define INTC_ICDIPR33_INT3                      (0x0000FF00uL)
+#define INTC_ICDIPR33_OSTM0TINT                 (0x00FF0000uL)
+#define INTC_ICDIPR33_OSTM1TINT                 (0xFF000000uL)
+
+#define INTC_ICDIPR34_CMI                       (0x000000FFuL)
+#define INTC_ICDIPR34_WTOUT                     (0x0000FF00uL)
+#define INTC_ICDIPR34_ITI                       (0x00FF0000uL)
+#define INTC_ICDIPR34_TGI0A                     (0xFF000000uL)
+
+#define INTC_ICDIPR35_TGI0B                     (0x000000FFuL)
+#define INTC_ICDIPR35_TGI0C                     (0x0000FF00uL)
+#define INTC_ICDIPR35_TGI0D                     (0x00FF0000uL)
+#define INTC_ICDIPR35_TGI0V                     (0xFF000000uL)
+
+#define INTC_ICDIPR36_TGI0E                     (0x000000FFuL)
+#define INTC_ICDIPR36_TGI0F                     (0x0000FF00uL)
+#define INTC_ICDIPR36_TGI1A                     (0x00FF0000uL)
+#define INTC_ICDIPR36_TGI1B                     (0xFF000000uL)
+
+#define INTC_ICDIPR37_TGI1V                     (0x000000FFuL)
+#define INTC_ICDIPR37_TGI1U                     (0x0000FF00uL)
+#define INTC_ICDIPR37_TGI2A                     (0x00FF0000uL)
+#define INTC_ICDIPR37_TGI2B                     (0xFF000000uL)
+
+#define INTC_ICDIPR38_TGI2V                     (0x000000FFuL)
+#define INTC_ICDIPR38_TGI2U                     (0x0000FF00uL)
+#define INTC_ICDIPR38_TGI3A                     (0x00FF0000uL)
+#define INTC_ICDIPR38_TGI3B                     (0xFF000000uL)
+
+#define INTC_ICDIPR39_TGI3C                     (0x000000FFuL)
+#define INTC_ICDIPR39_TGI3D                     (0x0000FF00uL)
+#define INTC_ICDIPR39_TGI3V                     (0x00FF0000uL)
+#define INTC_ICDIPR39_TGI4A                     (0xFF000000uL)
+
+#define INTC_ICDIPR40_TGI4B                     (0x000000FFuL)
+#define INTC_ICDIPR40_TGI4C                     (0x0000FF00uL)
+#define INTC_ICDIPR40_TGI4D                     (0x00FF0000uL)
+#define INTC_ICDIPR40_TGI4V                     (0xFF000000uL)
+
+#define INTC_ICDIPR41_CMI1                      (0x000000FFuL)
+#define INTC_ICDIPR41_CMI2                      (0x0000FF00uL)
+#define INTC_ICDIPR41_SGDEI0                    (0x00FF0000uL)
+#define INTC_ICDIPR41_SGDEI1                    (0xFF000000uL)
+
+#define INTC_ICDIPR42_SGDEI2                    (0x000000FFuL)
+#define INTC_ICDIPR42_SGDEI3                    (0x0000FF00uL)
+#define INTC_ICDIPR42_ADI                       (0x00FF0000uL)
+#define INTC_ICDIPR42_LMTI                      (0xFF000000uL)
+
+#define INTC_ICDIPR43_SSII0                     (0x000000FFuL)
+#define INTC_ICDIPR43_SSIRXI0                   (0x0000FF00uL)
+#define INTC_ICDIPR43_SSITXI0                   (0x00FF0000uL)
+#define INTC_ICDIPR43_SSII1                     (0xFF000000uL)
+
+#define INTC_ICDIPR44_SSIRXI1                   (0x000000FFuL)
+#define INTC_ICDIPR44_SSITXI1                   (0x0000FF00uL)
+#define INTC_ICDIPR44_SSII2                     (0x00FF0000uL)
+#define INTC_ICDIPR44_SSIRTI2                   (0xFF000000uL)
+
+#define INTC_ICDIPR45_SSII3                     (0x000000FFuL)
+#define INTC_ICDIPR45_SSIRXI3                   (0x0000FF00uL)
+#define INTC_ICDIPR45_SSITXI3                   (0x00FF0000uL)
+#define INTC_ICDIPR45_SSII4                     (0xFF000000uL)
+
+#define INTC_ICDIPR46_SSIRTI4                   (0x000000FFuL)
+#define INTC_ICDIPR46_SSII5                     (0x0000FF00uL)
+#define INTC_ICDIPR46_SSIRXI5                   (0x00FF0000uL)
+#define INTC_ICDIPR46_SSITXI5                   (0xFF000000uL)
+
+#define INTC_ICDIPR47_SPDIFI                    (0x000000FFuL)
+#define INTC_ICDIPR47_INTIICTEI0                (0x0000FF00uL)
+#define INTC_ICDIPR47_INTIICRI0                 (0x00FF0000uL)
+#define INTC_ICDIPR47_INTIICTI0                 (0xFF000000uL)
+
+#define INTC_ICDIPR48_INTIICSPI0                (0x000000FFuL)
+#define INTC_ICDIPR48_INTIICSTI0                (0x0000FF00uL)
+#define INTC_ICDIPR48_INTIICNAKI0               (0x00FF0000uL)
+#define INTC_ICDIPR48_INTIICALI0                (0xFF000000uL)
+
+#define INTC_ICDIPR49_INTIICTMOI0               (0x000000FFuL)
+#define INTC_ICDIPR49_INTIICTEI1                (0x0000FF00uL)
+#define INTC_ICDIPR49_INTIICRI1                 (0x00FF0000uL)
+#define INTC_ICDIPR49_INTIICTI1                 (0xFF000000uL)
+
+#define INTC_ICDIPR50_INTIICSPI1                (0x000000FFuL)
+#define INTC_ICDIPR50_INTIICSTI1                (0x0000FF00uL)
+#define INTC_ICDIPR50_INTIICNAKI1               (0x00FF0000uL)
+#define INTC_ICDIPR50_INTIICALI1                (0xFF000000uL)
+
+#define INTC_ICDIPR51_INTIICTMOI1               (0x000000FFuL)
+#define INTC_ICDIPR51_INTIICTEI2                (0x0000FF00uL)
+#define INTC_ICDIPR51_INTIICRI2                 (0x00FF0000uL)
+#define INTC_ICDIPR51_INTIICTI2                 (0xFF000000uL)
+
+#define INTC_ICDIPR52_INTIICSPI2                (0x000000FFuL)
+#define INTC_ICDIPR52_INTIICSTI2                (0x0000FF00uL)
+#define INTC_ICDIPR52_INTIICNAKI2               (0x00FF0000uL)
+#define INTC_ICDIPR52_INTIICALI2                (0xFF000000uL)
+
+#define INTC_ICDIPR53_INTIICTMOI2               (0x000000FFuL)
+#define INTC_ICDIPR53_INTIICTEI3                (0x0000FF00uL)
+#define INTC_ICDIPR53_INTIICRI3                 (0x00FF0000uL)
+#define INTC_ICDIPR53_INTIICTI3                 (0xFF000000uL)
+
+#define INTC_ICDIPR54_INTIICSPI3                (0x000000FFuL)
+#define INTC_ICDIPR54_INTIICSTI3                (0x0000FF00uL)
+#define INTC_ICDIPR54_INTIICNAKI3               (0x00FF0000uL)
+#define INTC_ICDIPR54_INTIICALI3                (0xFF000000uL)
+
+#define INTC_ICDIPR55_INTIICTMOI3               (0x000000FFuL)
+#define INTC_ICDIPR55_BRI0                      (0x0000FF00uL)
+#define INTC_ICDIPR55_ERI0                      (0x00FF0000uL)
+#define INTC_ICDIPR55_RXI0                      (0xFF000000uL)
+
+#define INTC_ICDIPR56_TXI0                      (0x000000FFuL)
+#define INTC_ICDIPR56_BRI1                      (0x0000FF00uL)
+#define INTC_ICDIPR56_ERI1                      (0x00FF0000uL)
+#define INTC_ICDIPR56_RXI1                      (0xFF000000uL)
+
+#define INTC_ICDIPR57_TXI1                      (0x000000FFuL)
+#define INTC_ICDIPR57_BRI2                      (0x0000FF00uL)
+#define INTC_ICDIPR57_ERI2                      (0x00FF0000uL)
+#define INTC_ICDIPR57_RXI2                      (0xFF000000uL)
+
+#define INTC_ICDIPR58_TXI2                      (0x000000FFuL)
+#define INTC_ICDIPR58_BRI3                      (0x0000FF00uL)
+#define INTC_ICDIPR58_ERI3                      (0x00FF0000uL)
+#define INTC_ICDIPR58_RXI3                      (0xFF000000uL)
+
+#define INTC_ICDIPR59_TXI3                      (0x000000FFuL)
+#define INTC_ICDIPR59_BRI4                      (0x0000FF00uL)
+#define INTC_ICDIPR59_ERI4                      (0x00FF0000uL)
+#define INTC_ICDIPR59_RXI4                      (0xFF000000uL)
+
+#define INTC_ICDIPR60_TXI4                      (0x000000FFuL)
+#define INTC_ICDIPR60_BRI5                      (0x0000FF00uL)
+#define INTC_ICDIPR60_ERI5                      (0x00FF0000uL)
+#define INTC_ICDIPR60_RXI5                      (0xFF000000uL)
+
+#define INTC_ICDIPR61_TXI5                      (0x000000FFuL)
+#define INTC_ICDIPR61_BRI6                      (0x0000FF00uL)
+#define INTC_ICDIPR61_ERI6                      (0x00FF0000uL)
+#define INTC_ICDIPR61_RXI6                      (0xFF000000uL)
+
+#define INTC_ICDIPR62_TXI6                      (0x000000FFuL)
+#define INTC_ICDIPR62_BRI7                      (0x0000FF00uL)
+#define INTC_ICDIPR62_ERI7                      (0x00FF0000uL)
+#define INTC_ICDIPR62_RXI7                      (0xFF000000uL)
+
+#define INTC_ICDIPR63_TXI7                      (0x000000FFuL)
+#define INTC_ICDIPR63_INTRCANGERR               (0x0000FF00uL)
+#define INTC_ICDIPR63_INTRCANGRECC              (0x00FF0000uL)
+#define INTC_ICDIPR63_INTRCAN0REC               (0xFF000000uL)
+
+#define INTC_ICDIPR64_INTRCAN0ERR               (0x000000FFuL)
+#define INTC_ICDIPR64_INTRCAN0TRX               (0x0000FF00uL)
+#define INTC_ICDIPR64_INTRCAN1REC               (0x00FF0000uL)
+#define INTC_ICDIPR64_INTRCAN1ERR               (0xFF000000uL)
+
+#define INTC_ICDIPR65_INTRCAN1TRX               (0x000000FFuL)
+#define INTC_ICDIPR65_INTRCAN2REC               (0x0000FF00uL)
+#define INTC_ICDIPR65_INTRCAN2ERR               (0x00FF0000uL)
+#define INTC_ICDIPR65_INTRCAN2TRX               (0xFF000000uL)
+
+#define INTC_ICDIPR66_INTRCAN3REC               (0x000000FFuL)
+#define INTC_ICDIPR66_INTRCAN3ERR               (0x0000FF00uL)
+#define INTC_ICDIPR66_INTRCAN3TRX               (0x00FF0000uL)
+#define INTC_ICDIPR66_INTRCAN4REC               (0xFF000000uL)
+
+#define INTC_ICDIPR67_INTRCAN4ERR               (0x000000FFuL)
+#define INTC_ICDIPR67_INTRCAN4TRX               (0x0000FF00uL)
+#define INTC_ICDIPR67_SPEI0                     (0x00FF0000uL)
+#define INTC_ICDIPR67_SPRI0                     (0xFF000000uL)
+
+#define INTC_ICDIPR68_SPTI0                     (0x000000FFuL)
+#define INTC_ICDIPR68_SPEI1                     (0x0000FF00uL)
+#define INTC_ICDIPR68_SPRI1                     (0x00FF0000uL)
+#define INTC_ICDIPR68_SPTI1                     (0xFF000000uL)
+
+#define INTC_ICDIPR69_SPEI2                     (0x000000FFuL)
+#define INTC_ICDIPR69_SPRI2                     (0x0000FF00uL)
+#define INTC_ICDIPR69_SPTI2                     (0x00FF0000uL)
+#define INTC_ICDIPR69_SPEI3                     (0xFF000000uL)
+
+#define INTC_ICDIPR70_SPRI3                     (0x000000FFuL)
+#define INTC_ICDIPR70_SPTI3                     (0x0000FF00uL)
+#define INTC_ICDIPR70_SPEI4                     (0x00FF0000uL)
+#define INTC_ICDIPR70_SPRI4                     (0xFF000000uL)
+
+#define INTC_ICDIPR71_SPTI4                     (0x000000FFuL)
+#define INTC_ICDIPR71_IEBBTD                    (0x0000FF00uL)
+#define INTC_ICDIPR71_IEBBTERR                  (0x00FF0000uL)
+#define INTC_ICDIPR71_IEBBTSTA                  (0xFF000000uL)
+
+#define INTC_ICDIPR72_IEBBTV                    (0x000000FFuL)
+#define INTC_ICDIPR72_ISY                       (0x0000FF00uL)
+#define INTC_ICDIPR72_IERR                      (0x00FF0000uL)
+#define INTC_ICDIPR72_ITARG                     (0xFF000000uL)
+
+#define INTC_ICDIPR73_ISEC                      (0x000000FFuL)
+#define INTC_ICDIPR73_IBUF                      (0x0000FF00uL)
+#define INTC_ICDIPR73_IREADY                    (0x00FF0000uL)
+#define INTC_ICDIPR73_FLSTE                     (0xFF000000uL)
+
+#define INTC_ICDIPR74_FLTENDI                   (0x000000FFuL)
+#define INTC_ICDIPR74_FLTREQ0I                  (0x0000FF00uL)
+#define INTC_ICDIPR74_FLTREQ1I                  (0x00FF0000uL)
+#define INTC_ICDIPR74_MMC0                      (0xFF000000uL)
+
+#define INTC_ICDIPR75_MMC1                      (0x000000FFuL)
+#define INTC_ICDIPR75_MMC2                      (0x0000FF00uL)
+#define INTC_ICDIPR75_SDHI0_3                   (0x00FF0000uL)
+#define INTC_ICDIPR75_SDHI0_0                   (0xFF000000uL)
+
+#define INTC_ICDIPR76_SDHI0_1                   (0x000000FFuL)
+#define INTC_ICDIPR76_SDHI1_3                   (0x0000FF00uL)
+#define INTC_ICDIPR76_SDHI1_0                   (0x00FF0000uL)
+#define INTC_ICDIPR76_SDHI1_1                   (0xFF000000uL)
+
+#define INTC_ICDIPR77_ARM                       (0x000000FFuL)
+#define INTC_ICDIPR77_PRD                       (0x0000FF00uL)
+#define INTC_ICDIPR77_CUP                       (0x00FF0000uL)
+#define INTC_ICDIPR77_SCUAI0                    (0xFF000000uL)
+
+#define INTC_ICDIPR78_SCUAI1                    (0x000000FFuL)
+#define INTC_ICDIPR78_SCUFDI0                   (0x0000FF00uL)
+#define INTC_ICDIPR78_SCUFDI1                   (0x00FF0000uL)
+#define INTC_ICDIPR78_SCUFDI2                   (0xFF000000uL)
+
+#define INTC_ICDIPR79_SCUFDI3                   (0x000000FFuL)
+#define INTC_ICDIPR79_SCUFUI0                   (0x0000FF00uL)
+#define INTC_ICDIPR79_SCUFUI1                   (0x00FF0000uL)
+#define INTC_ICDIPR79_SCUFUI2                   (0xFF000000uL)
+
+#define INTC_ICDIPR80_SCUFUI3                   (0x000000FFuL)
+#define INTC_ICDIPR80_SCUDVI0                   (0x0000FF00uL)
+#define INTC_ICDIPR80_SCUDVI1                   (0x00FF0000uL)
+#define INTC_ICDIPR80_SCUDVI2                   (0xFF000000uL)
+
+#define INTC_ICDIPR81_SCUDVI3                   (0x000000FFuL)
+#define INTC_ICDIPR81_MLB_CINT                  (0x0000FF00uL)
+#define INTC_ICDIPR81_MLB_SINT                  (0x00FF0000uL)
+#define INTC_ICDIPR81_DRC0                      (0xFF000000uL)
+
+#define INTC_ICDIPR82_DRC1                      (0x000000FFuL)
+#define INTC_ICDIPR82_LINI0_INT_T               (0xFF000000uL)
+
+#define INTC_ICDIPR83_LINI0_INT_R               (0x000000FFuL)
+#define INTC_ICDIPR83_LINI0_INT_S               (0x0000FF00uL)
+#define INTC_ICDIPR83_LINI0_INT_M               (0x00FF0000uL)
+#define INTC_ICDIPR83_LINI1_INT_T               (0xFF000000uL)
+
+#define INTC_ICDIPR84_LINI1_INT_R               (0x000000FFuL)
+#define INTC_ICDIPR84_LINI1_INT_S               (0x0000FF00uL)
+#define INTC_ICDIPR84_LINI1_INT_M               (0x00FF0000uL)
+
+#define INTC_ICDIPR86_ERI0                      (0xFF000000uL)
+
+#define INTC_ICDIPR87_RXI0                      (0x000000FFuL)
+#define INTC_ICDIPR87_TXI0                      (0x0000FF00uL)
+#define INTC_ICDIPR87_TEI0                      (0x00FF0000uL)
+#define INTC_ICDIPR87_ERI1                      (0xFF000000uL)
+
+#define INTC_ICDIPR88_RXI1                      (0x000000FFuL)
+#define INTC_ICDIPR88_TXI1                      (0x0000FF00uL)
+#define INTC_ICDIPR88_TEI1                      (0x00FF0000uL)
+#define INTC_ICDIPR88_AVBI_DATA                 (0xFF000000uL)
+
+#define INTC_ICDIPR89_AVBI_ERROR                (0x000000FFuL)
+#define INTC_ICDIPR89_AVBI_MANAGE               (0x0000FF00uL)
+#define INTC_ICDIPR89_AVBI_MAC                  (0x00FF0000uL)
+#define INTC_ICDIPR89_ETHERI                    (0xFF000000uL)
+
+#define INTC_ICDIPR91_CEUI                      (0x000000FFuL)
+
+#define INTC_ICDIPR95_H2XMLB_ERRINT             (0x0000FF00uL)
+#define INTC_ICDIPR95_H2XIC1_ERRINT             (0x00FF0000uL)
+#define INTC_ICDIPR95_X2HPERI1_ERRINT           (0xFF000000uL)
+
+#define INTC_ICDIPR96_X2HPERI2_ERRINT           (0x000000FFuL)
+#define INTC_ICDIPR96_X2HPERI34_ERRINT          (0x0000FF00uL)
+#define INTC_ICDIPR96_X2HPERI5_ERRINT           (0x00FF0000uL)
+#define INTC_ICDIPR96_X2HPERI67_ERRINT          (0xFF000000uL)
+
+#define INTC_ICDIPR97_X2HDBGR_ERRINT            (0x000000FFuL)
+#define INTC_ICDIPR97_X2HBSC_ERRINT             (0x0000FF00uL)
+#define INTC_ICDIPR97_X2HSPI1_ERRINT            (0x00FF0000uL)
+#define INTC_ICDIPR97_X2HSPI2_ERRINT            (0xFF000000uL)
+
+#define INTC_ICDIPR98_PRRI                      (0x000000FFuL)
+#define INTC_ICDIPR98_IFEI0                     (0x0000FF00uL)
+#define INTC_ICDIPR98_OFFI0                     (0x00FF0000uL)
+#define INTC_ICDIPR98_PFVEI0                    (0xFF000000uL)
+
+#define INTC_ICDIPR99_IFEI1                     (0x000000FFuL)
+#define INTC_ICDIPR99_OFFI1                     (0x0000FF00uL)
+#define INTC_ICDIPR99_PFVEI1                    (0x00FF0000uL)
+
+#define INTC_ICDIPR104_TINT0                    (0x000000FFuL)
+#define INTC_ICDIPR104_TINT1                    (0x0000FF00uL)
+#define INTC_ICDIPR104_TINT2                    (0x00FF0000uL)
+#define INTC_ICDIPR104_TINT3                    (0xFF000000uL)
+
+#define INTC_ICDIPR105_TINT4                    (0x000000FFuL)
+#define INTC_ICDIPR105_TINT5                    (0x0000FF00uL)
+#define INTC_ICDIPR105_TINT6                    (0x00FF0000uL)
+#define INTC_ICDIPR105_TINT7                    (0xFF000000uL)
+
+#define INTC_ICDIPR106_TINT8                    (0x000000FFuL)
+#define INTC_ICDIPR106_TINT9                    (0x0000FF00uL)
+#define INTC_ICDIPR106_TINT10                   (0x00FF0000uL)
+#define INTC_ICDIPR106_TINT11                   (0xFF000000uL)
+
+#define INTC_ICDIPR107_TINT12                   (0x000000FFuL)
+#define INTC_ICDIPR107_TINT13                   (0x0000FF00uL)
+#define INTC_ICDIPR107_TINT14                   (0x00FF0000uL)
+#define INTC_ICDIPR107_TINT15                   (0xFF000000uL)
+
+#define INTC_ICDIPR108_TINT16                   (0x000000FFuL)
+#define INTC_ICDIPR108_TINT17                   (0x0000FF00uL)
+#define INTC_ICDIPR108_TINT18                   (0x00FF0000uL)
+#define INTC_ICDIPR108_TINT19                   (0xFF000000uL)
+
+#define INTC_ICDIPR109_TINT20                   (0x000000FFuL)
+#define INTC_ICDIPR109_TINT21                   (0x0000FF00uL)
+#define INTC_ICDIPR109_TINT22                   (0x00FF0000uL)
+#define INTC_ICDIPR109_TINT23                   (0xFF000000uL)
+
+#define INTC_ICDIPR110_TINT24                   (0x000000FFuL)
+#define INTC_ICDIPR110_TINT25                   (0x0000FF00uL)
+#define INTC_ICDIPR110_TINT26                   (0x00FF0000uL)
+#define INTC_ICDIPR110_TINT27                   (0xFF000000uL)
+
+#define INTC_ICDIPR111_TINT28                   (0x000000FFuL)
+#define INTC_ICDIPR111_TINT29                   (0x0000FF00uL)
+#define INTC_ICDIPR111_TINT30                   (0x00FF0000uL)
+#define INTC_ICDIPR111_TINT31                   (0xFF000000uL)
+
+#define INTC_ICDIPR112_TINT32                   (0x000000FFuL)
+#define INTC_ICDIPR112_TINT33                   (0x0000FF00uL)
+#define INTC_ICDIPR112_TINT34                   (0x00FF0000uL)
+#define INTC_ICDIPR112_TINT35                   (0xFF000000uL)
+
+#define INTC_ICDIPR113_TINT36                   (0x000000FFuL)
+#define INTC_ICDIPR113_TINT37                   (0x0000FF00uL)
+#define INTC_ICDIPR113_TINT38                   (0x00FF0000uL)
+#define INTC_ICDIPR113_TINT39                   (0xFF000000uL)
+
+#define INTC_ICDIPR114_TINT40                   (0x000000FFuL)
+#define INTC_ICDIPR114_TINT41                   (0x0000FF00uL)
+#define INTC_ICDIPR114_TINT42                   (0x00FF0000uL)
+#define INTC_ICDIPR114_TINT43                   (0xFF000000uL)
+
+#define INTC_ICDIPR115_TINT44                   (0x000000FFuL)
+#define INTC_ICDIPR115_TINT45                   (0x0000FF00uL)
+#define INTC_ICDIPR115_TINT46                   (0x00FF0000uL)
+#define INTC_ICDIPR115_TINT47                   (0xFF000000uL)
+
+#define INTC_ICDIPR116_TINT48                   (0x000000FFuL)
+#define INTC_ICDIPR116_TINT49                   (0x0000FF00uL)
+#define INTC_ICDIPR116_TINT50                   (0x00FF0000uL)
+#define INTC_ICDIPR116_TINT51                   (0xFF000000uL)
+
+#define INTC_ICDIPR117_TINT52                   (0x000000FFuL)
+#define INTC_ICDIPR117_TINT53                   (0x0000FF00uL)
+#define INTC_ICDIPR117_TINT54                   (0x00FF0000uL)
+#define INTC_ICDIPR117_TINT55                   (0xFF000000uL)
+
+#define INTC_ICDIPR118_TINT56                   (0x000000FFuL)
+#define INTC_ICDIPR118_TINT57                   (0x0000FF00uL)
+#define INTC_ICDIPR118_TINT58                   (0x00FF0000uL)
+#define INTC_ICDIPR118_TINT59                   (0xFF000000uL)
+
+#define INTC_ICDIPR119_TINT60                   (0x000000FFuL)
+#define INTC_ICDIPR119_TINT61                   (0x0000FF00uL)
+#define INTC_ICDIPR119_TINT62                   (0x00FF0000uL)
+#define INTC_ICDIPR119_TINT63                   (0xFF000000uL)
+
+#define INTC_ICDIPR120_TINT64                   (0x000000FFuL)
+#define INTC_ICDIPR120_TINT65                   (0x0000FF00uL)
+#define INTC_ICDIPR120_TINT66                   (0x00FF0000uL)
+#define INTC_ICDIPR120_TINT67                   (0xFF000000uL)
+
+#define INTC_ICDIPR121_TINT68                   (0x000000FFuL)
+#define INTC_ICDIPR121_TINT69                   (0x0000FF00uL)
+#define INTC_ICDIPR121_TINT70                   (0x00FF0000uL)
+#define INTC_ICDIPR121_TINT71                   (0xFF000000uL)
+
+#define INTC_ICDIPR122_TINT72                   (0x000000FFuL)
+#define INTC_ICDIPR122_TINT73                   (0x0000FF00uL)
+#define INTC_ICDIPR122_TINT74                   (0x00FF0000uL)
+#define INTC_ICDIPR122_TINT75                   (0xFF000000uL)
+
+#define INTC_ICDIPR123_TINT76                   (0x000000FFuL)
+#define INTC_ICDIPR123_TINT77                   (0x0000FF00uL)
+#define INTC_ICDIPR123_TINT78                   (0x00FF0000uL)
+#define INTC_ICDIPR123_TINT79                   (0xFF000000uL)
+
+#define INTC_ICDIPR124_TINT80                   (0x000000FFuL)
+#define INTC_ICDIPR124_TINT81                   (0x0000FF00uL)
+#define INTC_ICDIPR124_TINT82                   (0x00FF0000uL)
+#define INTC_ICDIPR124_TINT83                   (0xFF000000uL)
+
+#define INTC_ICDIPR125_TINT84                   (0x000000FFuL)
+#define INTC_ICDIPR125_TINT85                   (0x0000FF00uL)
+#define INTC_ICDIPR125_TINT86                   (0x00FF0000uL)
+#define INTC_ICDIPR125_TINT87                   (0xFF000000uL)
+
+#define INTC_ICDIPR126_TINT88                   (0x000000FFuL)
+#define INTC_ICDIPR126_TINT89                   (0x0000FF00uL)
+#define INTC_ICDIPR126_TINT90                   (0x00FF0000uL)
+#define INTC_ICDIPR126_TINT91                   (0xFF000000uL)
+
+#define INTC_ICDIPR127_TINT92                   (0x000000FFuL)
+#define INTC_ICDIPR127_TINT93                   (0x0000FF00uL)
+#define INTC_ICDIPR127_TINT94                   (0x00FF0000uL)
+#define INTC_ICDIPR127_TINT95                   (0xFF000000uL)
+
+#define INTC_ICDIPR128_TINT96                   (0x000000FFuL)
+#define INTC_ICDIPR128_TINT97                   (0x0000FF00uL)
+#define INTC_ICDIPR128_TINT98                   (0x00FF0000uL)
+#define INTC_ICDIPR128_TINT99                   (0xFF000000uL)
+
+#define INTC_ICDIPR129_TINT100                  (0x000000FFuL)
+#define INTC_ICDIPR129_TINT101                  (0x0000FF00uL)
+#define INTC_ICDIPR129_TINT102                  (0x00FF0000uL)
+#define INTC_ICDIPR129_TINT103                  (0xFF000000uL)
+
+#define INTC_ICDIPR130_TINT104                  (0x000000FFuL)
+#define INTC_ICDIPR130_TINT105                  (0x0000FF00uL)
+#define INTC_ICDIPR130_TINT106                  (0x00FF0000uL)
+#define INTC_ICDIPR130_TINT107                  (0xFF000000uL)
+
+#define INTC_ICDIPR131_TINT108                  (0x000000FFuL)
+#define INTC_ICDIPR131_TINT109                  (0x0000FF00uL)
+#define INTC_ICDIPR131_TINT110                  (0x00FF0000uL)
+#define INTC_ICDIPR131_TINT111                  (0xFF000000uL)
+
+#define INTC_ICDIPR132_TINT112                  (0x000000FFuL)
+#define INTC_ICDIPR132_TINT113                  (0x0000FF00uL)
+#define INTC_ICDIPR132_TINT114                  (0x00FF0000uL)
+#define INTC_ICDIPR132_TINT115                  (0xFF000000uL)
+
+#define INTC_ICDIPR133_TINT116                  (0x000000FFuL)
+#define INTC_ICDIPR133_TINT117                  (0x0000FF00uL)
+#define INTC_ICDIPR133_TINT118                  (0x00FF0000uL)
+#define INTC_ICDIPR133_TINT119                  (0xFF000000uL)
+
+#define INTC_ICDIPR134_TINT120                  (0x000000FFuL)
+#define INTC_ICDIPR134_TINT121                  (0x0000FF00uL)
+#define INTC_ICDIPR134_TINT122                  (0x00FF0000uL)
+#define INTC_ICDIPR134_TINT123                  (0xFF000000uL)
+
+#define INTC_ICDIPR135_TINT124                  (0x000000FFuL)
+#define INTC_ICDIPR135_TINT125                  (0x0000FF00uL)
+#define INTC_ICDIPR135_TINT126                  (0x00FF0000uL)
+#define INTC_ICDIPR135_TINT127                  (0xFF000000uL)
+
+#define INTC_ICDIPR136_TINT128                  (0x000000FFuL)
+#define INTC_ICDIPR136_TINT129                  (0x0000FF00uL)
+#define INTC_ICDIPR136_TINT130                  (0x00FF0000uL)
+#define INTC_ICDIPR136_TINT131                  (0xFF000000uL)
+
+#define INTC_ICDIPR137_TINT132                  (0x000000FFuL)
+#define INTC_ICDIPR137_TINT133                  (0x0000FF00uL)
+#define INTC_ICDIPR137_TINT134                  (0x00FF0000uL)
+#define INTC_ICDIPR137_TINT135                  (0xFF000000uL)
+
+#define INTC_ICDIPR138_TINT136                  (0x000000FFuL)
+#define INTC_ICDIPR138_TINT137                  (0x0000FF00uL)
+#define INTC_ICDIPR138_TINT138                  (0x00FF0000uL)
+#define INTC_ICDIPR138_TINT139                  (0xFF000000uL)
+
+#define INTC_ICDIPR139_TINT140                  (0x000000FFuL)
+#define INTC_ICDIPR139_TINT141                  (0x0000FF00uL)
+#define INTC_ICDIPR139_TINT142                  (0x00FF0000uL)
+#define INTC_ICDIPR139_TINT143                  (0xFF000000uL)
+
+#define INTC_ICDIPR140_TINT144                  (0x000000FFuL)
+#define INTC_ICDIPR140_TINT145                  (0x0000FF00uL)
+#define INTC_ICDIPR140_TINT146                  (0x00FF0000uL)
+#define INTC_ICDIPR140_TINT147                  (0xFF000000uL)
+
+#define INTC_ICDIPR141_TINT148                  (0x000000FFuL)
+#define INTC_ICDIPR141_TINT149                  (0x0000FF00uL)
+#define INTC_ICDIPR141_TINT150                  (0x00FF0000uL)
+#define INTC_ICDIPR141_TINT151                  (0xFF000000uL)
+
+#define INTC_ICDIPR142_TINT152                  (0x000000FFuL)
+#define INTC_ICDIPR142_TINT153                  (0x0000FF00uL)
+#define INTC_ICDIPR142_TINT154                  (0x00FF0000uL)
+#define INTC_ICDIPR142_TINT155                  (0xFF000000uL)
+
+#define INTC_ICDIPR143_TINT156                  (0x000000FFuL)
+#define INTC_ICDIPR143_TINT157                  (0x0000FF00uL)
+#define INTC_ICDIPR143_TINT158                  (0x00FF0000uL)
+#define INTC_ICDIPR143_TINT159                  (0xFF000000uL)
+
+#define INTC_ICDIPR144_TINT160                  (0x000000FFuL)
+#define INTC_ICDIPR144_TINT161                  (0x0000FF00uL)
+#define INTC_ICDIPR144_TINT162                  (0x00FF0000uL)
+#define INTC_ICDIPR144_TINT163                  (0xFF000000uL)
+
+#define INTC_ICDIPR145_TINT164                  (0x000000FFuL)
+#define INTC_ICDIPR145_TINT165                  (0x0000FF00uL)
+#define INTC_ICDIPR145_TINT166                  (0x00FF0000uL)
+#define INTC_ICDIPR145_TINT167                  (0xFF000000uL)
+
+#define INTC_ICDIPR146_TINT168                  (0x000000FFuL)
+#define INTC_ICDIPR146_TINT169                  (0x0000FF00uL)
+#define INTC_ICDIPR146_TINT170                  (0x00FF0000uL)
+
+#define INTC_ICDIPTR0_SW0                       (0x000000FFuL)
+#define INTC_ICDIPTR0_SW1                       (0x0000FF00uL)
+#define INTC_ICDIPTR0_SW2                       (0x00FF0000uL)
+#define INTC_ICDIPTR0_SW3                       (0xFF000000uL)
+
+#define INTC_ICDIPTR1_SW4                       (0x000000FFuL)
+#define INTC_ICDIPTR1_SW5                       (0x0000FF00uL)
+#define INTC_ICDIPTR1_SW6                       (0x00FF0000uL)
+#define INTC_ICDIPTR1_SW7                       (0xFF000000uL)
+
+#define INTC_ICDIPTR2_SW8                       (0x000000FFuL)
+#define INTC_ICDIPTR2_SW9                       (0x0000FF00uL)
+#define INTC_ICDIPTR2_SW10                      (0x00FF0000uL)
+#define INTC_ICDIPTR2_SW11                      (0xFF000000uL)
+
+#define INTC_ICDIPTR3_SW12                      (0x000000FFuL)
+#define INTC_ICDIPTR3_SW13                      (0x0000FF00uL)
+#define INTC_ICDIPTR3_SW14                      (0x00FF0000uL)
+#define INTC_ICDIPTR3_SW15                      (0xFF000000uL)
+
+#define INTC_ICDIPTR4_PMUIRQ0                   (0x000000FFuL)
+#define INTC_ICDIPTR4_COMMRX0                   (0x0000FF00uL)
+#define INTC_ICDIPTR4_COMMTX0                   (0x00FF0000uL)
+#define INTC_ICDIPTR4_CTIIRQ0                   (0xFF000000uL)
+
+#define INTC_ICDIPTR8_IRQ0                      (0x000000FFuL)
+#define INTC_ICDIPTR8_IRQ1                      (0x0000FF00uL)
+#define INTC_ICDIPTR8_IRQ2                      (0x00FF0000uL)
+#define INTC_ICDIPTR8_IRQ3                      (0xFF000000uL)
+
+#define INTC_ICDIPTR9_IRQ4                      (0x000000FFuL)
+#define INTC_ICDIPTR9_IRQ5                      (0x0000FF00uL)
+#define INTC_ICDIPTR9_IRQ6                      (0x00FF0000uL)
+#define INTC_ICDIPTR9_IRQ7                      (0xFF000000uL)
+
+#define INTC_ICDIPTR10_PL310ERR                 (0x000000FFuL)
+#define INTC_ICDIPTR10_DMAINT0                  (0x0000FF00uL)
+#define INTC_ICDIPTR10_DMAINT1                  (0x00FF0000uL)
+#define INTC_ICDIPTR10_DMAINT2                  (0xFF000000uL)
+
+#define INTC_ICDIPTR11_DMAINT3                  (0x000000FFuL)
+#define INTC_ICDIPTR11_DMAINT4                  (0x0000FF00uL)
+#define INTC_ICDIPTR11_DMAINT5                  (0x00FF0000uL)
+#define INTC_ICDIPTR11_DMAINT6                  (0xFF000000uL)
+
+#define INTC_ICDIPTR12_DMAINT7                  (0x000000FFuL)
+#define INTC_ICDIPTR12_DMAINT8                  (0x0000FF00uL)
+#define INTC_ICDIPTR12_DMAINT9                  (0x00FF0000uL)
+#define INTC_ICDIPTR12_DMAINT10                 (0xFF000000uL)
+
+#define INTC_ICDIPTR13_DMAINT11                 (0x000000FFuL)
+#define INTC_ICDIPTR13_DMAINT12                 (0x0000FF00uL)
+#define INTC_ICDIPTR13_DMAINT13                 (0x00FF0000uL)
+#define INTC_ICDIPTR13_DMAINT14                 (0xFF000000uL)
+
+#define INTC_ICDIPTR14_DMAINT15                 (0x000000FFuL)
+#define INTC_ICDIPTR14_DMAERR                   (0x0000FF00uL)
+
+#define INTC_ICDIPTR18_USBI0                    (0x0000FF00uL)
+#define INTC_ICDIPTR18_USBI1                    (0x00FF0000uL)
+#define INTC_ICDIPTR18_S0_VI_VSYNC0             (0xFF000000uL)
+
+#define INTC_ICDIPTR19_S0_LO_VSYNC0             (0x000000FFuL)
+#define INTC_ICDIPTR19_S0_VSYNCERR0             (0x0000FF00uL)
+#define INTC_ICDIPTR19_GR3_VLINE0               (0x00FF0000uL)
+#define INTC_ICDIPTR19_S0_VFIELD0               (0xFF000000uL)
+
+#define INTC_ICDIPTR20_IV1_VBUFERR0             (0x000000FFuL)
+#define INTC_ICDIPTR20_IV3_VBUFERR0             (0x0000FF00uL)
+#define INTC_ICDIPTR20_IV5_VBUFERR0             (0x00FF0000uL)
+#define INTC_ICDIPTR20_IV6_VBUFERR0             (0xFF000000uL)
+
+#define INTC_ICDIPTR21_S0_WLINE0                (0x000000FFuL)
+#define INTC_ICDIPTR21_S1_VI_VSYNC0             (0x0000FF00uL)
+#define INTC_ICDIPTR21_S1_LO_VSYNC0             (0x00FF0000uL)
+#define INTC_ICDIPTR21_S1_VSYNCERR0             (0xFF000000uL)
+
+#define INTC_ICDIPTR22_S1_VFIELD0               (0x000000FFuL)
+#define INTC_ICDIPTR22_IV2_VBUFERR0             (0x0000FF00uL)
+#define INTC_ICDIPTR22_IV4_VBUFERR0             (0x00FF0000uL)
+#define INTC_ICDIPTR22_S1_WLINE0                (0xFF000000uL)
+
+#define INTC_ICDIPTR23_OIR_VI_VSYNC0            (0x000000FFuL)
+#define INTC_ICDIPTR23_OIR_LO_VSYNC0            (0x0000FF00uL)
+#define INTC_ICDIPTR23_OIR_VSYNCERR0            (0x00FF0000uL)
+#define INTC_ICDIPTR23_OIR_VFIELD0              (0xFF000000uL)
+
+#define INTC_ICDIPTR24_IV7_VBUFERR0             (0x000000FFuL)
+#define INTC_ICDIPTR24_IV8_VBUFERR0             (0x0000FF00uL)
+#define INTC_ICDIPTR24_S0_VI_VSYNC1             (0xFF000000uL)
+
+#define INTC_ICDIPTR25_S0_LO_VSYNC1             (0x000000FFuL)
+#define INTC_ICDIPTR25_S0_VSYNCERR1             (0x0000FF00uL)
+#define INTC_ICDIPTR25_GR3_VLINE1               (0x00FF0000uL)
+#define INTC_ICDIPTR25_S0_VFIELD1               (0xFF000000uL)
+
+#define INTC_ICDIPTR26_IV1_VBUFERR1             (0x000000FFuL)
+#define INTC_ICDIPTR26_IV3_VBUFERR1             (0x0000FF00uL)
+#define INTC_ICDIPTR26_IV5_VBUFERR1             (0x00FF0000uL)
+#define INTC_ICDIPTR26_IV6_VBUFERR1             (0xFF000000uL)
+
+#define INTC_ICDIPTR27_S0_WLINE1                (0x000000FFuL)
+#define INTC_ICDIPTR27_S1_VI_VSYNC1             (0x0000FF00uL)
+#define INTC_ICDIPTR27_S1_LO_VSYNC1             (0x00FF0000uL)
+#define INTC_ICDIPTR27_S1_VSYNCERR1             (0xFF000000uL)
+
+#define INTC_ICDIPTR28_S1_VFIELD1               (0x000000FFuL)
+#define INTC_ICDIPTR28_IV2_VBUFERR1             (0x0000FF00uL)
+#define INTC_ICDIPTR28_IV4_VBUFERR1             (0x00FF0000uL)
+#define INTC_ICDIPTR28_S1_WLINE1                (0xFF000000uL)
+
+#define INTC_ICDIPTR29_OIR_VI_VSYNC1            (0x000000FFuL)
+#define INTC_ICDIPTR29_OIR_LO_VSYNC1            (0x0000FF00uL)
+#define INTC_ICDIPTR29_OIR_VLINE1               (0x00FF0000uL)
+#define INTC_ICDIPTR29_OIR_VFIELD1              (0xFF000000uL)
+
+#define INTC_ICDIPTR30_IV7_VBUFERR1             (0x000000FFuL)
+#define INTC_ICDIPTR30_IV8_VBUFERR1             (0x0000FF00uL)
+#define INTC_ICDIPTR30_IMRDI                    (0xFF000000uL)
+
+#define INTC_ICDIPTR31_IMR2I0                   (0x000000FFuL)
+#define INTC_ICDIPTR31_IMR2I1                   (0x0000FF00uL)
+#define INTC_ICDIPTR31_JEDI                     (0x00FF0000uL)
+#define INTC_ICDIPTR31_JDTI                     (0xFF000000uL)
+
+#define INTC_ICDIPTR32_CMP0                     (0x000000FFuL)
+#define INTC_ICDIPTR32_CMP1                     (0x0000FF00uL)
+#define INTC_ICDIPTR32_INT0                     (0x00FF0000uL)
+#define INTC_ICDIPTR32_INT1                     (0xFF000000uL)
+
+#define INTC_ICDIPTR33_INT2                     (0x000000FFuL)
+#define INTC_ICDIPTR33_INT3                     (0x0000FF00uL)
+#define INTC_ICDIPTR33_OSTM0TINT                (0x00FF0000uL)
+#define INTC_ICDIPTR33_OSTM1TINT                (0xFF000000uL)
+
+#define INTC_ICDIPTR34_CMI                      (0x000000FFuL)
+#define INTC_ICDIPTR34_WTOUT                    (0x0000FF00uL)
+#define INTC_ICDIPTR34_ITI                      (0x00FF0000uL)
+#define INTC_ICDIPTR34_TGI0A                    (0xFF000000uL)
+
+#define INTC_ICDIPTR35_TGI0B                    (0x000000FFuL)
+#define INTC_ICDIPTR35_TGI0C                    (0x0000FF00uL)
+#define INTC_ICDIPTR35_TGI0D                    (0x00FF0000uL)
+#define INTC_ICDIPTR35_TGI0V                    (0xFF000000uL)
+
+#define INTC_ICDIPTR36_TGI0E                    (0x000000FFuL)
+#define INTC_ICDIPTR36_TGI0F                    (0x0000FF00uL)
+#define INTC_ICDIPTR36_TGI1A                    (0x00FF0000uL)
+#define INTC_ICDIPTR36_TGI1B                    (0xFF000000uL)
+
+#define INTC_ICDIPTR37_TGI1V                    (0x000000FFuL)
+#define INTC_ICDIPTR37_TGI1U                    (0x0000FF00uL)
+#define INTC_ICDIPTR37_TGI2A                    (0x00FF0000uL)
+#define INTC_ICDIPTR37_TGI2B                    (0xFF000000uL)
+
+#define INTC_ICDIPTR38_TGI2V                    (0x000000FFuL)
+#define INTC_ICDIPTR38_TGI2U                    (0x0000FF00uL)
+#define INTC_ICDIPTR38_TGI3A                    (0x00FF0000uL)
+#define INTC_ICDIPTR38_TGI3B                    (0xFF000000uL)
+
+#define INTC_ICDIPTR39_TGI3C                    (0x000000FFuL)
+#define INTC_ICDIPTR39_TGI3D                    (0x0000FF00uL)
+#define INTC_ICDIPTR39_TGI3V                    (0x00FF0000uL)
+#define INTC_ICDIPTR39_TGI4A                    (0xFF000000uL)
+
+#define INTC_ICDIPTR40_TGI4B                    (0x000000FFuL)
+#define INTC_ICDIPTR40_TGI4C                    (0x0000FF00uL)
+#define INTC_ICDIPTR40_TGI4D                    (0x00FF0000uL)
+#define INTC_ICDIPTR40_TGI4V                    (0xFF000000uL)
+
+#define INTC_ICDIPTR41_CMI1                     (0x000000FFuL)
+#define INTC_ICDIPTR41_CMI2                     (0x0000FF00uL)
+#define INTC_ICDIPTR41_SGDEI0                   (0x00FF0000uL)
+#define INTC_ICDIPTR41_SGDEI1                   (0xFF000000uL)
+
+#define INTC_ICDIPTR42_SGDEI2                   (0x000000FFuL)
+#define INTC_ICDIPTR42_SGDEI3                   (0x0000FF00uL)
+#define INTC_ICDIPTR42_ADI                      (0x00FF0000uL)
+#define INTC_ICDIPTR42_LMTI                     (0xFF000000uL)
+
+#define INTC_ICDIPTR43_SSII0                    (0x000000FFuL)
+#define INTC_ICDIPTR43_SSIRXI0                  (0x0000FF00uL)
+#define INTC_ICDIPTR43_SSITXI0                  (0x00FF0000uL)
+#define INTC_ICDIPTR43_SSII1                    (0xFF000000uL)
+
+#define INTC_ICDIPTR44_SSIRXI1                  (0x000000FFuL)
+#define INTC_ICDIPTR44_SSITXI1                  (0x0000FF00uL)
+#define INTC_ICDIPTR44_SSII2                    (0x00FF0000uL)
+#define INTC_ICDIPTR44_SSIRTI2                  (0xFF000000uL)
+
+#define INTC_ICDIPTR45_SSII3                    (0x000000FFuL)
+#define INTC_ICDIPTR45_SSIRXI3                  (0x0000FF00uL)
+#define INTC_ICDIPTR45_SSITXI3                  (0x00FF0000uL)
+#define INTC_ICDIPTR45_SSII4                    (0xFF000000uL)
+
+#define INTC_ICDIPTR46_SSIRTI4                  (0x000000FFuL)
+#define INTC_ICDIPTR46_SSII5                    (0x0000FF00uL)
+#define INTC_ICDIPTR46_SSIRXI5                  (0x00FF0000uL)
+#define INTC_ICDIPTR46_SSITXI5                  (0xFF000000uL)
+
+#define INTC_ICDIPTR47_SPDIFI                   (0x000000FFuL)
+#define INTC_ICDIPTR47_INTIICTEI0               (0x0000FF00uL)
+#define INTC_ICDIPTR47_INTIICRI0                (0x00FF0000uL)
+#define INTC_ICDIPTR47_INTIICTI0                (0xFF000000uL)
+
+#define INTC_ICDIPTR48_INTIICSPI0               (0x000000FFuL)
+#define INTC_ICDIPTR48_INTIICSTI0               (0x0000FF00uL)
+#define INTC_ICDIPTR48_INTIICNAKI0              (0x00FF0000uL)
+#define INTC_ICDIPTR48_INTIICALI0               (0xFF000000uL)
+
+#define INTC_ICDIPTR49_INTIICTMOI0              (0x000000FFuL)
+#define INTC_ICDIPTR49_INTIICTEI1               (0x0000FF00uL)
+#define INTC_ICDIPTR49_INTIICRI1                (0x00FF0000uL)
+#define INTC_ICDIPTR49_INTIICTI1                (0xFF000000uL)
+
+#define INTC_ICDIPTR50_INTIICSPI1               (0x000000FFuL)
+#define INTC_ICDIPTR50_INTIICSTI1               (0x0000FF00uL)
+#define INTC_ICDIPTR50_INTIICNAKI1              (0x00FF0000uL)
+#define INTC_ICDIPTR50_INTIICALI1               (0xFF000000uL)
+
+#define INTC_ICDIPTR51_INTIICTMOI1              (0x000000FFuL)
+#define INTC_ICDIPTR51_INTIICTEI2               (0x0000FF00uL)
+#define INTC_ICDIPTR51_INTIICRI2                (0x00FF0000uL)
+#define INTC_ICDIPTR51_INTIICTI2                (0xFF000000uL)
+
+#define INTC_ICDIPTR52_INTIICSPI2               (0x000000FFuL)
+#define INTC_ICDIPTR52_INTIICSTI2               (0x0000FF00uL)
+#define INTC_ICDIPTR52_INTIICNAKI2              (0x00FF0000uL)
+#define INTC_ICDIPTR52_INTIICALI2               (0xFF000000uL)
+
+#define INTC_ICDIPTR53_INTIICTMOI2              (0x000000FFuL)
+#define INTC_ICDIPTR53_INTIICTEI3               (0x0000FF00uL)
+#define INTC_ICDIPTR53_INTIICRI3                (0x00FF0000uL)
+#define INTC_ICDIPTR53_INTIICTI3                (0xFF000000uL)
+
+#define INTC_ICDIPTR54_INTIICSPI3               (0x000000FFuL)
+#define INTC_ICDIPTR54_INTIICSTI3               (0x0000FF00uL)
+#define INTC_ICDIPTR54_INTIICNAKI3              (0x00FF0000uL)
+#define INTC_ICDIPTR54_INTIICALI3               (0xFF000000uL)
+
+#define INTC_ICDIPTR55_INTIICTMOI3              (0x000000FFuL)
+#define INTC_ICDIPTR55_BRI0                     (0x0000FF00uL)
+#define INTC_ICDIPTR55_ERI0                     (0x00FF0000uL)
+#define INTC_ICDIPTR55_RXI0                     (0xFF000000uL)
+
+#define INTC_ICDIPTR56_TXI0                     (0x000000FFuL)
+#define INTC_ICDIPTR56_BRI1                     (0x0000FF00uL)
+#define INTC_ICDIPTR56_ERI1                     (0x00FF0000uL)
+#define INTC_ICDIPTR56_RXI1                     (0xFF000000uL)
+
+#define INTC_ICDIPTR57_TXI1                     (0x000000FFuL)
+#define INTC_ICDIPTR57_BRI2                     (0x0000FF00uL)
+#define INTC_ICDIPTR57_ERI2                     (0x00FF0000uL)
+#define INTC_ICDIPTR57_RXI2                     (0xFF000000uL)
+
+#define INTC_ICDIPTR58_TXI2                     (0x000000FFuL)
+#define INTC_ICDIPTR58_BRI3                     (0x0000FF00uL)
+#define INTC_ICDIPTR58_ERI3                     (0x00FF0000uL)
+#define INTC_ICDIPTR58_RXI3                     (0xFF000000uL)
+
+#define INTC_ICDIPTR59_TXI3                     (0x000000FFuL)
+#define INTC_ICDIPTR59_BRI4                     (0x0000FF00uL)
+#define INTC_ICDIPTR59_ERI4                     (0x00FF0000uL)
+#define INTC_ICDIPTR59_RXI4                     (0xFF000000uL)
+
+#define INTC_ICDIPTR60_TXI4                     (0x000000FFuL)
+#define INTC_ICDIPTR60_BRI5                     (0x0000FF00uL)
+#define INTC_ICDIPTR60_ERI5                     (0x00FF0000uL)
+#define INTC_ICDIPTR60_RXI5                     (0xFF000000uL)
+
+#define INTC_ICDIPTR61_TXI5                     (0x000000FFuL)
+#define INTC_ICDIPTR61_BRI6                     (0x0000FF00uL)
+#define INTC_ICDIPTR61_ERI6                     (0x00FF0000uL)
+#define INTC_ICDIPTR61_RXI6                     (0xFF000000uL)
+
+#define INTC_ICDIPTR62_TXI6                     (0x000000FFuL)
+#define INTC_ICDIPTR62_BRI7                     (0x0000FF00uL)
+#define INTC_ICDIPTR62_ERI7                     (0x00FF0000uL)
+#define INTC_ICDIPTR62_RXI7                     (0xFF000000uL)
+
+#define INTC_ICDIPTR63_TXI7                     (0x000000FFuL)
+#define INTC_ICDIPTR63_INTRCANGERR              (0x0000FF00uL)
+#define INTC_ICDIPTR63_INTRCANGRECC             (0x00FF0000uL)
+#define INTC_ICDIPTR63_INTRCAN0REC              (0xFF000000uL)
+
+#define INTC_ICDIPTR64_INTRCAN0ERR              (0x000000FFuL)
+#define INTC_ICDIPTR64_INTRCAN0TRX              (0x0000FF00uL)
+#define INTC_ICDIPTR64_INTRCAN1REC              (0x00FF0000uL)
+#define INTC_ICDIPTR64_INTRCAN1ERR              (0xFF000000uL)
+
+#define INTC_ICDIPTR65_INTRCAN1TRX              (0x000000FFuL)
+#define INTC_ICDIPTR65_INTRCAN2REC              (0x0000FF00uL)
+#define INTC_ICDIPTR65_INTRCAN2ERR              (0x00FF0000uL)
+#define INTC_ICDIPTR65_INTRCAN2TRX              (0xFF000000uL)
+
+#define INTC_ICDIPTR66_INTRCAN3REC              (0x000000FFuL)
+#define INTC_ICDIPTR66_INTRCAN3ERR              (0x0000FF00uL)
+#define INTC_ICDIPTR66_INTRCAN3TRX              (0x00FF0000uL)
+#define INTC_ICDIPTR66_INTRCAN4REC              (0xFF000000uL)
+
+#define INTC_ICDIPTR67_INTRCAN4ERR              (0x000000FFuL)
+#define INTC_ICDIPTR67_INTRCAN4TRX              (0x0000FF00uL)
+#define INTC_ICDIPTR67_SPEI0                    (0x00FF0000uL)
+#define INTC_ICDIPTR67_SPRI0                    (0xFF000000uL)
+
+#define INTC_ICDIPTR68_SPTI0                    (0x000000FFuL)
+#define INTC_ICDIPTR68_SPEI1                    (0x0000FF00uL)
+#define INTC_ICDIPTR68_SPRI1                    (0x00FF0000uL)
+#define INTC_ICDIPTR68_SPTI1                    (0xFF000000uL)
+
+#define INTC_ICDIPTR69_SPEI2                    (0x000000FFuL)
+#define INTC_ICDIPTR69_SPRI2                    (0x0000FF00uL)
+#define INTC_ICDIPTR69_SPTI2                    (0x00FF0000uL)
+#define INTC_ICDIPTR69_SPEI3                    (0xFF000000uL)
+
+#define INTC_ICDIPTR70_SPRI3                    (0x000000FFuL)
+#define INTC_ICDIPTR70_SPTI3                    (0x0000FF00uL)
+#define INTC_ICDIPTR70_SPEI4                    (0x00FF0000uL)
+#define INTC_ICDIPTR70_SPRI4                    (0xFF000000uL)
+
+#define INTC_ICDIPTR71_SPTI4                    (0x000000FFuL)
+#define INTC_ICDIPTR71_IEBBTD                   (0x0000FF00uL)
+#define INTC_ICDIPTR71_IEBBTERR                 (0x00FF0000uL)
+#define INTC_ICDIPTR71_IEBBTSTA                 (0xFF000000uL)
+
+#define INTC_ICDIPTR72_IEBBTV                   (0x000000FFuL)
+#define INTC_ICDIPTR72_ISY                      (0x0000FF00uL)
+#define INTC_ICDIPTR72_IERR                     (0x00FF0000uL)
+#define INTC_ICDIPTR72_ITARG                    (0xFF000000uL)
+
+#define INTC_ICDIPTR73_ISEC                     (0x000000FFuL)
+#define INTC_ICDIPTR73_IBUF                     (0x0000FF00uL)
+#define INTC_ICDIPTR73_IREADY                   (0x00FF0000uL)
+#define INTC_ICDIPTR73_FLSTE                    (0xFF000000uL)
+
+#define INTC_ICDIPTR74_FLTENDI                  (0x000000FFuL)
+#define INTC_ICDIPTR74_FLTREQ0I                 (0x0000FF00uL)
+#define INTC_ICDIPTR74_FLTREQ1I                 (0x00FF0000uL)
+#define INTC_ICDIPTR74_MMC0                     (0xFF000000uL)
+
+#define INTC_ICDIPTR75_MMC1                     (0x000000FFuL)
+#define INTC_ICDIPTR75_MMC2                     (0x0000FF00uL)
+#define INTC_ICDIPTR75_SDHI0_3                  (0x00FF0000uL)
+#define INTC_ICDIPTR75_SDHI0_0                  (0xFF000000uL)
+
+#define INTC_ICDIPTR76_SDHI0_1                  (0x000000FFuL)
+#define INTC_ICDIPTR76_SDHI1_3                  (0x0000FF00uL)
+#define INTC_ICDIPTR76_SDHI1_0                  (0x00FF0000uL)
+#define INTC_ICDIPTR76_SDHI1_1                  (0xFF000000uL)
+
+#define INTC_ICDIPTR77_ARM                      (0x000000FFuL)
+#define INTC_ICDIPTR77_PRD                      (0x0000FF00uL)
+#define INTC_ICDIPTR77_CUP                      (0x00FF0000uL)
+#define INTC_ICDIPTR77_SCUAI0                   (0xFF000000uL)
+
+#define INTC_ICDIPTR78_SCUAI1                   (0x000000FFuL)
+#define INTC_ICDIPTR78_SCUFDI0                  (0x0000FF00uL)
+#define INTC_ICDIPTR78_SCUFDI1                  (0x00FF0000uL)
+#define INTC_ICDIPTR78_SCUFDI2                  (0xFF000000uL)
+
+#define INTC_ICDIPTR79_SCUFDI3                  (0x000000FFuL)
+#define INTC_ICDIPTR79_SCUFUI0                  (0x0000FF00uL)
+#define INTC_ICDIPTR79_SCUFUI1                  (0x00FF0000uL)
+#define INTC_ICDIPTR79_SCUFUI2                  (0xFF000000uL)
+
+#define INTC_ICDIPTR80_SCUFUI3                  (0x000000FFuL)
+#define INTC_ICDIPTR80_SCUDVI0                  (0x0000FF00uL)
+#define INTC_ICDIPTR80_SCUDVI1                  (0x00FF0000uL)
+#define INTC_ICDIPTR80_SCUDVI2                  (0xFF000000uL)
+
+#define INTC_ICDIPTR81_SCUDVI3                  (0x000000FFuL)
+#define INTC_ICDIPTR81_MLB_CINT                 (0x0000FF00uL)
+#define INTC_ICDIPTR81_MLB_SINT                 (0x00FF0000uL)
+#define INTC_ICDIPTR81_DRC0                     (0xFF000000uL)
+
+#define INTC_ICDIPTR82_DRC1                     (0x000000FFuL)
+#define INTC_ICDIPTR82_LINI0_INT_T              (0xFF000000uL)
+
+#define INTC_ICDIPTR83_LINI0_INT_R              (0x000000FFuL)
+#define INTC_ICDIPTR83_LINI0_INT_S              (0x0000FF00uL)
+#define INTC_ICDIPTR83_LINI0_INT_M              (0x00FF0000uL)
+#define INTC_ICDIPTR83_LINI1_INT_T              (0xFF000000uL)
+
+#define INTC_ICDIPTR84_LINI1_INT_R              (0x000000FFuL)
+#define INTC_ICDIPTR84_LINI1_INT_S              (0x0000FF00uL)
+#define INTC_ICDIPTR84_LINI1_INT_M              (0x00FF0000uL)
+
+#define INTC_ICDIPTR86_ERI0                     (0xFF000000uL)
+
+#define INTC_ICDIPTR87_RXI0                     (0x000000FFuL)
+#define INTC_ICDIPTR87_TXI0                     (0x0000FF00uL)
+#define INTC_ICDIPTR87_TEI0                     (0x00FF0000uL)
+#define INTC_ICDIPTR87_ERI1                     (0xFF000000uL)
+
+#define INTC_ICDIPTR88_RXI1                     (0x000000FFuL)
+#define INTC_ICDIPTR88_TXI1                     (0x0000FF00uL)
+#define INTC_ICDIPTR88_TEI1                     (0x00FF0000uL)
+#define INTC_ICDIPTR88_AVBI_DATA                (0xFF000000uL)
+
+#define INTC_ICDIPTR89_AVBI_ERROR               (0x000000FFuL)
+#define INTC_ICDIPTR89_AVBI_MANAGE              (0x0000FF00uL)
+#define INTC_ICDIPTR89_AVBI_MAC                 (0x00FF0000uL)
+#define INTC_ICDIPTR89_ETHERI                   (0xFF000000uL)
+
+#define INTC_ICDIPTR91_CEUI                     (0x000000FFuL)
+
+#define INTC_ICDIPTR95_H2XMLB_ERRINT            (0x0000FF00uL)
+#define INTC_ICDIPTR95_H2XIC1_ERRINT            (0x00FF0000uL)
+#define INTC_ICDIPTR95_X2HPERI1_ERRINT          (0xFF000000uL)
+
+#define INTC_ICDIPTR96_X2HPERI2_ERRINT          (0x000000FFuL)
+#define INTC_ICDIPTR96_X2HPERI34_ERRINT         (0x0000FF00uL)
+#define INTC_ICDIPTR96_X2HPERI5_ERRINT          (0x00FF0000uL)
+#define INTC_ICDIPTR96_X2HPERI67_ERRINT         (0xFF000000uL)
+
+#define INTC_ICDIPTR97_X2HDBGR_ERRINT           (0x000000FFuL)
+#define INTC_ICDIPTR97_X2HBSC_ERRINT            (0x0000FF00uL)
+#define INTC_ICDIPTR97_X2HSPI1_ERRINT           (0x00FF0000uL)
+#define INTC_ICDIPTR97_X2HSPI2_ERRINT           (0xFF000000uL)
+
+#define INTC_ICDIPTR98_PRRI                     (0x000000FFuL)
+#define INTC_ICDIPTR98_IFEI0                    (0x0000FF00uL)
+#define INTC_ICDIPTR98_OFFI0                    (0x00FF0000uL)
+#define INTC_ICDIPTR98_PFVEI0                   (0xFF000000uL)
+
+#define INTC_ICDIPTR99_IFEI1                    (0x000000FFuL)
+#define INTC_ICDIPTR99_OFFI1                    (0x0000FF00uL)
+#define INTC_ICDIPTR99_PFVEI1                   (0x00FF0000uL)
+
+#define INTC_ICDIPTR104_TINT0                   (0x000000FFuL)
+#define INTC_ICDIPTR104_TINT1                   (0x0000FF00uL)
+#define INTC_ICDIPTR104_TINT2                   (0x00FF0000uL)
+#define INTC_ICDIPTR104_TINT3                   (0xFF000000uL)
+
+#define INTC_ICDIPTR105_TINT4                   (0x000000FFuL)
+#define INTC_ICDIPTR105_TINT5                   (0x0000FF00uL)
+#define INTC_ICDIPTR105_TINT6                   (0x00FF0000uL)
+#define INTC_ICDIPTR105_TINT7                   (0xFF000000uL)
+
+#define INTC_ICDIPTR106_TINT8                   (0x000000FFuL)
+#define INTC_ICDIPTR106_TINT9                   (0x0000FF00uL)
+#define INTC_ICDIPTR106_TINT10                  (0x00FF0000uL)
+#define INTC_ICDIPTR106_TINT11                  (0xFF000000uL)
+
+#define INTC_ICDIPTR107_TINT12                  (0x000000FFuL)
+#define INTC_ICDIPTR107_TINT13                  (0x0000FF00uL)
+#define INTC_ICDIPTR107_TINT14                  (0x00FF0000uL)
+#define INTC_ICDIPTR107_TINT15                  (0xFF000000uL)
+
+#define INTC_ICDIPTR108_TINT16                  (0x000000FFuL)
+#define INTC_ICDIPTR108_TINT17                  (0x0000FF00uL)
+#define INTC_ICDIPTR108_TINT18                  (0x00FF0000uL)
+#define INTC_ICDIPTR108_TINT19                  (0xFF000000uL)
+
+#define INTC_ICDIPTR109_TINT20                  (0x000000FFuL)
+#define INTC_ICDIPTR109_TINT21                  (0x0000FF00uL)
+#define INTC_ICDIPTR109_TINT22                  (0x00FF0000uL)
+#define INTC_ICDIPTR109_TINT23                  (0xFF000000uL)
+
+#define INTC_ICDIPTR110_TINT24                  (0x000000FFuL)
+#define INTC_ICDIPTR110_TINT25                  (0x0000FF00uL)
+#define INTC_ICDIPTR110_TINT26                  (0x00FF0000uL)
+#define INTC_ICDIPTR110_TINT27                  (0xFF000000uL)
+
+#define INTC_ICDIPTR111_TINT28                  (0x000000FFuL)
+#define INTC_ICDIPTR111_TINT29                  (0x0000FF00uL)
+#define INTC_ICDIPTR111_TINT30                  (0x00FF0000uL)
+#define INTC_ICDIPTR111_TINT31                  (0xFF000000uL)
+
+#define INTC_ICDIPTR112_TINT32                  (0x000000FFuL)
+#define INTC_ICDIPTR112_TINT33                  (0x0000FF00uL)
+#define INTC_ICDIPTR112_TINT34                  (0x00FF0000uL)
+#define INTC_ICDIPTR112_TINT35                  (0xFF000000uL)
+
+#define INTC_ICDIPTR113_TINT36                  (0x000000FFuL)
+#define INTC_ICDIPTR113_TINT37                  (0x0000FF00uL)
+#define INTC_ICDIPTR113_TINT38                  (0x00FF0000uL)
+#define INTC_ICDIPTR113_TINT39                  (0xFF000000uL)
+
+#define INTC_ICDIPTR114_TINT40                  (0x000000FFuL)
+#define INTC_ICDIPTR114_TINT41                  (0x0000FF00uL)
+#define INTC_ICDIPTR114_TINT42                  (0x00FF0000uL)
+#define INTC_ICDIPTR114_TINT43                  (0xFF000000uL)
+
+#define INTC_ICDIPTR115_TINT44                  (0x000000FFuL)
+#define INTC_ICDIPTR115_TINT45                  (0x0000FF00uL)
+#define INTC_ICDIPTR115_TINT46                  (0x00FF0000uL)
+#define INTC_ICDIPTR115_TINT47                  (0xFF000000uL)
+
+#define INTC_ICDIPTR116_TINT48                  (0x000000FFuL)
+#define INTC_ICDIPTR116_TINT49                  (0x0000FF00uL)
+#define INTC_ICDIPTR116_TINT50                  (0x00FF0000uL)
+#define INTC_ICDIPTR116_TINT51                  (0xFF000000uL)
+
+#define INTC_ICDIPTR117_TINT52                  (0x000000FFuL)
+#define INTC_ICDIPTR117_TINT53                  (0x0000FF00uL)
+#define INTC_ICDIPTR117_TINT54                  (0x00FF0000uL)
+#define INTC_ICDIPTR117_TINT55                  (0xFF000000uL)
+
+#define INTC_ICDIPTR118_TINT56                  (0x000000FFuL)
+#define INTC_ICDIPTR118_TINT57                  (0x0000FF00uL)
+#define INTC_ICDIPTR118_TINT58                  (0x00FF0000uL)
+#define INTC_ICDIPTR118_TINT59                  (0xFF000000uL)
+
+#define INTC_ICDIPTR119_TINT60                  (0x000000FFuL)
+#define INTC_ICDIPTR119_TINT61                  (0x0000FF00uL)
+#define INTC_ICDIPTR119_TINT62                  (0x00FF0000uL)
+#define INTC_ICDIPTR119_TINT63                  (0xFF000000uL)
+
+#define INTC_ICDIPTR120_TINT64                  (0x000000FFuL)
+#define INTC_ICDIPTR120_TINT65                  (0x0000FF00uL)
+#define INTC_ICDIPTR120_TINT66                  (0x00FF0000uL)
+#define INTC_ICDIPTR120_TINT67                  (0xFF000000uL)
+
+#define INTC_ICDIPTR121_TINT68                  (0x000000FFuL)
+#define INTC_ICDIPTR121_TINT69                  (0x0000FF00uL)
+#define INTC_ICDIPTR121_TINT70                  (0x00FF0000uL)
+#define INTC_ICDIPTR121_TINT71                  (0xFF000000uL)
+
+#define INTC_ICDIPTR122_TINT72                  (0x000000FFuL)
+#define INTC_ICDIPTR122_TINT73                  (0x0000FF00uL)
+#define INTC_ICDIPTR122_TINT74                  (0x00FF0000uL)
+#define INTC_ICDIPTR122_TINT75                  (0xFF000000uL)
+
+#define INTC_ICDIPTR123_TINT76                  (0x000000FFuL)
+#define INTC_ICDIPTR123_TINT77                  (0x0000FF00uL)
+#define INTC_ICDIPTR123_TINT78                  (0x00FF0000uL)
+#define INTC_ICDIPTR123_TINT79                  (0xFF000000uL)
+
+#define INTC_ICDIPTR124_TINT80                  (0x000000FFuL)
+#define INTC_ICDIPTR124_TINT81                  (0x0000FF00uL)
+#define INTC_ICDIPTR124_TINT82                  (0x00FF0000uL)
+#define INTC_ICDIPTR124_TINT83                  (0xFF000000uL)
+
+#define INTC_ICDIPTR125_TINT84                  (0x000000FFuL)
+#define INTC_ICDIPTR125_TINT85                  (0x0000FF00uL)
+#define INTC_ICDIPTR125_TINT86                  (0x00FF0000uL)
+#define INTC_ICDIPTR125_TINT87                  (0xFF000000uL)
+
+#define INTC_ICDIPTR126_TINT88                  (0x000000FFuL)
+#define INTC_ICDIPTR126_TINT89                  (0x0000FF00uL)
+#define INTC_ICDIPTR126_TINT90                  (0x00FF0000uL)
+#define INTC_ICDIPTR126_TINT91                  (0xFF000000uL)
+
+#define INTC_ICDIPTR127_TINT92                  (0x000000FFuL)
+#define INTC_ICDIPTR127_TINT93                  (0x0000FF00uL)
+#define INTC_ICDIPTR127_TINT94                  (0x00FF0000uL)
+#define INTC_ICDIPTR127_TINT95                  (0xFF000000uL)
+
+#define INTC_ICDIPTR128_TINT96                  (0x000000FFuL)
+#define INTC_ICDIPTR128_TINT97                  (0x0000FF00uL)
+#define INTC_ICDIPTR128_TINT98                  (0x00FF0000uL)
+#define INTC_ICDIPTR128_TINT99                  (0xFF000000uL)
+
+#define INTC_ICDIPTR129_TINT100                 (0x000000FFuL)
+#define INTC_ICDIPTR129_TINT101                 (0x0000FF00uL)
+#define INTC_ICDIPTR129_TINT102                 (0x00FF0000uL)
+#define INTC_ICDIPTR129_TINT103                 (0xFF000000uL)
+
+#define INTC_ICDIPTR130_TINT104                 (0x000000FFuL)
+#define INTC_ICDIPTR130_TINT105                 (0x0000FF00uL)
+#define INTC_ICDIPTR130_TINT106                 (0x00FF0000uL)
+#define INTC_ICDIPTR130_TINT107                 (0xFF000000uL)
+
+#define INTC_ICDIPTR131_TINT108                 (0x000000FFuL)
+#define INTC_ICDIPTR131_TINT109                 (0x0000FF00uL)
+#define INTC_ICDIPTR131_TINT110                 (0x00FF0000uL)
+#define INTC_ICDIPTR131_TINT111                 (0xFF000000uL)
+
+#define INTC_ICDIPTR132_TINT112                 (0x000000FFuL)
+#define INTC_ICDIPTR132_TINT113                 (0x0000FF00uL)
+#define INTC_ICDIPTR132_TINT114                 (0x00FF0000uL)
+#define INTC_ICDIPTR132_TINT115                 (0xFF000000uL)
+
+#define INTC_ICDIPTR133_TINT116                 (0x000000FFuL)
+#define INTC_ICDIPTR133_TINT117                 (0x0000FF00uL)
+#define INTC_ICDIPTR133_TINT118                 (0x00FF0000uL)
+#define INTC_ICDIPTR133_TINT119                 (0xFF000000uL)
+
+#define INTC_ICDIPTR134_TINT120                 (0x000000FFuL)
+#define INTC_ICDIPTR134_TINT121                 (0x0000FF00uL)
+#define INTC_ICDIPTR134_TINT122                 (0x00FF0000uL)
+#define INTC_ICDIPTR134_TINT123                 (0xFF000000uL)
+
+#define INTC_ICDIPTR135_TINT124                 (0x000000FFuL)
+#define INTC_ICDIPTR135_TINT125                 (0x0000FF00uL)
+#define INTC_ICDIPTR135_TINT126                 (0x00FF0000uL)
+#define INTC_ICDIPTR135_TINT127                 (0xFF000000uL)
+
+#define INTC_ICDIPTR136_TINT128                 (0x000000FFuL)
+#define INTC_ICDIPTR136_TINT129                 (0x0000FF00uL)
+#define INTC_ICDIPTR136_TINT130                 (0x00FF0000uL)
+#define INTC_ICDIPTR136_TINT131                 (0xFF000000uL)
+
+#define INTC_ICDIPTR137_TINT132                 (0x000000FFuL)
+#define INTC_ICDIPTR137_TINT133                 (0x0000FF00uL)
+#define INTC_ICDIPTR137_TINT134                 (0x00FF0000uL)
+#define INTC_ICDIPTR137_TINT135                 (0xFF000000uL)
+
+#define INTC_ICDIPTR138_TINT136                 (0x000000FFuL)
+#define INTC_ICDIPTR138_TINT137                 (0x0000FF00uL)
+#define INTC_ICDIPTR138_TINT138                 (0x00FF0000uL)
+#define INTC_ICDIPTR138_TINT139                 (0xFF000000uL)
+
+#define INTC_ICDIPTR139_TINT140                 (0x000000FFuL)
+#define INTC_ICDIPTR139_TINT141                 (0x0000FF00uL)
+#define INTC_ICDIPTR139_TINT142                 (0x00FF0000uL)
+#define INTC_ICDIPTR139_TINT143                 (0xFF000000uL)
+
+#define INTC_ICDIPTR140_TINT144                 (0x000000FFuL)
+#define INTC_ICDIPTR140_TINT145                 (0x0000FF00uL)
+#define INTC_ICDIPTR140_TINT146                 (0x00FF0000uL)
+#define INTC_ICDIPTR140_TINT147                 (0xFF000000uL)
+
+#define INTC_ICDIPTR141_TINT148                 (0x000000FFuL)
+#define INTC_ICDIPTR141_TINT149                 (0x0000FF00uL)
+#define INTC_ICDIPTR141_TINT150                 (0x00FF0000uL)
+#define INTC_ICDIPTR141_TINT151                 (0xFF000000uL)
+
+#define INTC_ICDIPTR142_TINT152                 (0x000000FFuL)
+#define INTC_ICDIPTR142_TINT153                 (0x0000FF00uL)
+#define INTC_ICDIPTR142_TINT154                 (0x00FF0000uL)
+#define INTC_ICDIPTR142_TINT155                 (0xFF000000uL)
+
+#define INTC_ICDIPTR143_TINT156                 (0x000000FFuL)
+#define INTC_ICDIPTR143_TINT157                 (0x0000FF00uL)
+#define INTC_ICDIPTR143_TINT158                 (0x00FF0000uL)
+#define INTC_ICDIPTR143_TINT159                 (0xFF000000uL)
+
+#define INTC_ICDIPTR144_TINT160                 (0x000000FFuL)
+#define INTC_ICDIPTR144_TINT161                 (0x0000FF00uL)
+#define INTC_ICDIPTR144_TINT162                 (0x00FF0000uL)
+#define INTC_ICDIPTR144_TINT163                 (0xFF000000uL)
+
+#define INTC_ICDIPTR145_TINT164                 (0x000000FFuL)
+#define INTC_ICDIPTR145_TINT165                 (0x0000FF00uL)
+#define INTC_ICDIPTR145_TINT166                 (0x00FF0000uL)
+#define INTC_ICDIPTR145_TINT167                 (0xFF000000uL)
+
+#define INTC_ICDIPTR146_TINT168                 (0x000000FFuL)
+#define INTC_ICDIPTR146_TINT169                 (0x0000FF00uL)
+#define INTC_ICDIPTR146_TINT170                 (0x00FF0000uL)
+
+#define INTC_ICDICFR0_SW0_0                     (0x00000001uL)
+#define INTC_ICDICFR0_SW0_1                     (0x00000002uL)
+#define INTC_ICDICFR0_SW1_0                     (0x00000004uL)
+#define INTC_ICDICFR0_SW1_1                     (0x00000008uL)
+#define INTC_ICDICFR0_SW2_0                     (0x00000010uL)
+#define INTC_ICDICFR0_SW2_1                     (0x00000020uL)
+#define INTC_ICDICFR0_SW3_0                     (0x00000040uL)
+#define INTC_ICDICFR0_SW3_1                     (0x00000080uL)
+#define INTC_ICDICFR0_SW4_0                     (0x00000100uL)
+#define INTC_ICDICFR0_SW4_1                     (0x00000200uL)
+#define INTC_ICDICFR0_SW5_0                     (0x00000400uL)
+#define INTC_ICDICFR0_SW5_1                     (0x00000800uL)
+#define INTC_ICDICFR0_SW6_0                     (0x00001000uL)
+#define INTC_ICDICFR0_SW6_1                     (0x00002000uL)
+#define INTC_ICDICFR0_SW7_0                     (0x00004000uL)
+#define INTC_ICDICFR0_SW7_1                     (0x00008000uL)
+#define INTC_ICDICFR0_SW8_0                     (0x00010000uL)
+#define INTC_ICDICFR0_SW8_1                     (0x00020000uL)
+#define INTC_ICDICFR0_SW9_0                     (0x00040000uL)
+#define INTC_ICDICFR0_SW9_1                     (0x00080000uL)
+#define INTC_ICDICFR0_SW10_0                    (0x00100000uL)
+#define INTC_ICDICFR0_SW10_1                    (0x00200000uL)
+#define INTC_ICDICFR0_SW11_0                    (0x00400000uL)
+#define INTC_ICDICFR0_SW11_1                    (0x00800000uL)
+#define INTC_ICDICFR0_SW12_0                    (0x01000000uL)
+#define INTC_ICDICFR0_SW12_1                    (0x02000000uL)
+#define INTC_ICDICFR0_SW13_0                    (0x04000000uL)
+#define INTC_ICDICFR0_SW13_1                    (0x08000000uL)
+#define INTC_ICDICFR0_SW14_0                    (0x10000000uL)
+#define INTC_ICDICFR0_SW14_1                    (0x20000000uL)
+#define INTC_ICDICFR0_SW15_0                    (0x40000000uL)
+#define INTC_ICDICFR0_SW15_1                    (0x80000000uL)
+
+#define INTC_ICDICFR1_PMUIRQ0_0                 (0x00000001uL)
+#define INTC_ICDICFR1_PMUIRQ0_1                 (0x00000002uL)
+#define INTC_ICDICFR1_COMMRX0_0                 (0x00000004uL)
+#define INTC_ICDICFR1_COMMRX0_1                 (0x00000008uL)
+#define INTC_ICDICFR1_COMMTX0_0                 (0x00000010uL)
+#define INTC_ICDICFR1_COMMTX0_1                 (0x00000020uL)
+#define INTC_ICDICFR1_CTIIRQ0_0                 (0x00000040uL)
+#define INTC_ICDICFR1_CTIIRQ0_1                 (0x00000080uL)
+
+#define INTC_ICDICFR2_IRQ0_0                    (0x00000001uL)
+#define INTC_ICDICFR2_IRQ0_1                    (0x00000002uL)
+#define INTC_ICDICFR2_IRQ1_0                    (0x00000004uL)
+#define INTC_ICDICFR2_IRQ1_1                    (0x00000008uL)
+#define INTC_ICDICFR2_IRQ2_0                    (0x00000010uL)
+#define INTC_ICDICFR2_IRQ2_1                    (0x00000020uL)
+#define INTC_ICDICFR2_IRQ3_0                    (0x00000040uL)
+#define INTC_ICDICFR2_IRQ3_1                    (0x00000080uL)
+#define INTC_ICDICFR2_IRQ4_0                    (0x00000100uL)
+#define INTC_ICDICFR2_IRQ4_1                    (0x00000200uL)
+#define INTC_ICDICFR2_IRQ5_0                    (0x00000400uL)
+#define INTC_ICDICFR2_IRQ5_1                    (0x00000800uL)
+#define INTC_ICDICFR2_IRQ6_0                    (0x00001000uL)
+#define INTC_ICDICFR2_IRQ6_1                    (0x00002000uL)
+#define INTC_ICDICFR2_IRQ7_0                    (0x00004000uL)
+#define INTC_ICDICFR2_IRQ7_1                    (0x00008000uL)
+#define INTC_ICDICFR2_PL310ERR_0                (0x00010000uL)
+#define INTC_ICDICFR2_PL310ERR_1                (0x00020000uL)
+#define INTC_ICDICFR2_DMAINT0_0                 (0x00040000uL)
+#define INTC_ICDICFR2_DMAINT0_1                 (0x00080000uL)
+#define INTC_ICDICFR2_DMAINT1_0                 (0x00100000uL)
+#define INTC_ICDICFR2_DMAINT1_1                 (0x00200000uL)
+#define INTC_ICDICFR2_DMAINT2_0                 (0x00400000uL)
+#define INTC_ICDICFR2_DMAINT2_1                 (0x00800000uL)
+#define INTC_ICDICFR2_DMAINT3_0                 (0x01000000uL)
+#define INTC_ICDICFR2_DMAINT3_1                 (0x02000000uL)
+#define INTC_ICDICFR2_DMAINT4_0                 (0x04000000uL)
+#define INTC_ICDICFR2_DMAINT4_1                 (0x08000000uL)
+#define INTC_ICDICFR2_DMAINT5_0                 (0x10000000uL)
+#define INTC_ICDICFR2_DMAINT5_1                 (0x20000000uL)
+#define INTC_ICDICFR2_DMAINT6_0                 (0x40000000uL)
+#define INTC_ICDICFR2_DMAINT6_1                 (0x80000000uL)
+
+#define INTC_ICDICFR3_DMAINT7_0                 (0x00000001uL)
+#define INTC_ICDICFR3_DMAINT7_1                 (0x00000002uL)
+#define INTC_ICDICFR3_DMAINT8_0                 (0x00000004uL)
+#define INTC_ICDICFR3_DMAINT8_1                 (0x00000008uL)
+#define INTC_ICDICFR3_DMAINT9_0                 (0x00000010uL)
+#define INTC_ICDICFR3_DMAINT9_1                 (0x00000020uL)
+#define INTC_ICDICFR3_DMAINT10_0                (0x00000040uL)
+#define INTC_ICDICFR3_DMAINT10_1                (0x00000080uL)
+#define INTC_ICDICFR3_DMAINT11_0                (0x00000100uL)
+#define INTC_ICDICFR3_DMAINT11_1                (0x00000200uL)
+#define INTC_ICDICFR3_DMAINT12_0                (0x00000400uL)
+#define INTC_ICDICFR3_DMAINT12_1                (0x00000800uL)
+#define INTC_ICDICFR3_DMAINT13_0                (0x00001000uL)
+#define INTC_ICDICFR3_DMAINT13_1                (0x00002000uL)
+#define INTC_ICDICFR3_DMAINT14_0                (0x00004000uL)
+#define INTC_ICDICFR3_DMAINT14_1                (0x00008000uL)
+#define INTC_ICDICFR3_DMAINT15_0                (0x00010000uL)
+#define INTC_ICDICFR3_DMAINT15_1                (0x00020000uL)
+#define INTC_ICDICFR3_DMAERR_0                  (0x00040000uL)
+#define INTC_ICDICFR3_DMAERR_1                  (0x00080000uL)
+
+#define INTC_ICDICFR4_USBI0_0                   (0x00040000uL)
+#define INTC_ICDICFR4_USBI0_1                   (0x00080000uL)
+#define INTC_ICDICFR4_USBI1_0                   (0x00100000uL)
+#define INTC_ICDICFR4_USBI1_1                   (0x00200000uL)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_0            (0x00400000uL)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_1            (0x00800000uL)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_0            (0x01000000uL)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_1            (0x02000000uL)
+#define INTC_ICDICFR4_S0_VSYNCERR0_0            (0x04000000uL)
+#define INTC_ICDICFR4_S0_VSYNCERR0_1            (0x08000000uL)
+#define INTC_ICDICFR4_GR3_VLINE0_0              (0x10000000uL)
+#define INTC_ICDICFR4_GR3_VLINE0_1              (0x20000000uL)
+#define INTC_ICDICFR4_S0_VFIELD0_0              (0x40000000uL)
+#define INTC_ICDICFR4_S0_VFIELD0_1              (0x80000000uL)
+
+#define INTC_ICDICFR5_IV1_VBUFERR0_0            (0x00000001uL)
+#define INTC_ICDICFR5_IV1_VBUFERR0_1            (0x00000002uL)
+#define INTC_ICDICFR5_IV3_VBUFERR0_0            (0x00000004uL)
+#define INTC_ICDICFR5_IV3_VBUFERR0_1            (0x00000008uL)
+#define INTC_ICDICFR5_IV5_VBUFERR0_0            (0x00000010uL)
+#define INTC_ICDICFR5_IV5_VBUFERR0_1            (0x00000020uL)
+#define INTC_ICDICFR5_IV6_VBUFERR0_0            (0x00000040uL)
+#define INTC_ICDICFR5_IV6_VBUFERR0_1            (0x00000080uL)
+#define INTC_ICDICFR5_S0_WLINE0_0               (0x00000100uL)
+#define INTC_ICDICFR5_S0_WLINE0_1               (0x00000200uL)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_0            (0x00000400uL)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_1            (0x00000800uL)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_0            (0x00001000uL)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_1            (0x00002000uL)
+#define INTC_ICDICFR5_S1_VSYNCERR0_0            (0x00004000uL)
+#define INTC_ICDICFR5_S1_VSYNCERR0_1            (0x00008000uL)
+#define INTC_ICDICFR5_S1_VFIELD0_0              (0x00010000uL)
+#define INTC_ICDICFR5_S1_VFIELD0_1              (0x00020000uL)
+#define INTC_ICDICFR5_IV2_VBUFERR0_0            (0x00040000uL)
+#define INTC_ICDICFR5_IV2_VBUFERR0_1            (0x00080000uL)
+#define INTC_ICDICFR5_IV4_VBUFERR0_0            (0x00100000uL)
+#define INTC_ICDICFR5_IV4_VBUFERR0_1            (0x00200000uL)
+#define INTC_ICDICFR5_S1_WLINE0_0               (0x00400000uL)
+#define INTC_ICDICFR5_S1_WLINE0_1               (0x00800000uL)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_0           (0x01000000uL)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_1           (0x02000000uL)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_0           (0x04000000uL)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_1           (0x08000000uL)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_0           (0x10000000uL)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_1           (0x20000000uL)
+#define INTC_ICDICFR5_OIR_VFIELD0_0             (0x40000000uL)
+#define INTC_ICDICFR5_OIR_VFIELD0_1             (0x80000000uL)
+
+#define INTC_ICDICFR6_IV7_VBUFERR0_0            (0x00000001uL)
+#define INTC_ICDICFR6_IV7_VBUFERR0_1            (0x00000002uL)
+#define INTC_ICDICFR6_IV8_VBUFERR0_0            (0x00000004uL)
+#define INTC_ICDICFR6_IV8_VBUFERR0_1            (0x00000008uL)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_0            (0x00000040uL)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_1            (0x00000080uL)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_0            (0x00000100uL)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_1            (0x00000200uL)
+#define INTC_ICDICFR6_S0_VSYNCERR1_0            (0x00000400uL)
+#define INTC_ICDICFR6_S0_VSYNCERR1_1            (0x00000800uL)
+#define INTC_ICDICFR6_GR3_VLINE1_0              (0x00001000uL)
+#define INTC_ICDICFR6_GR3_VLINE1_1              (0x00002000uL)
+#define INTC_ICDICFR6_S0_VFIELD1_0              (0x00004000uL)
+#define INTC_ICDICFR6_S0_VFIELD1_1              (0x00008000uL)
+#define INTC_ICDICFR6_IV1_VBUFERR1_0            (0x00010000uL)
+#define INTC_ICDICFR6_IV1_VBUFERR1_1            (0x00020000uL)
+#define INTC_ICDICFR6_IV3_VBUFERR1_0            (0x00040000uL)
+#define INTC_ICDICFR6_IV3_VBUFERR1_1            (0x00080000uL)
+#define INTC_ICDICFR6_IV5_VBUFERR1_0            (0x00100000uL)
+#define INTC_ICDICFR6_IV5_VBUFERR1_1            (0x00200000uL)
+#define INTC_ICDICFR6_IV6_VBUFERR1_0            (0x00400000uL)
+#define INTC_ICDICFR6_IV6_VBUFERR1_1            (0x00800000uL)
+#define INTC_ICDICFR6_S0_WLINE1_0               (0x01000000uL)
+#define INTC_ICDICFR6_S0_WLINE1_1               (0x02000000uL)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_0            (0x04000000uL)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_1            (0x08000000uL)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_0            (0x10000000uL)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_1            (0x20000000uL)
+#define INTC_ICDICFR6_S1_VSYNCERR1_0            (0x40000000uL)
+#define INTC_ICDICFR6_S1_VSYNCERR1_1            (0x80000000uL)
+
+#define INTC_ICDICFR7_S1_VFIELD1_0              (0x00000001uL)
+#define INTC_ICDICFR7_S1_VFIELD1_1              (0x00000002uL)
+#define INTC_ICDICFR7_IV2_VBUFERR1_0            (0x00000004uL)
+#define INTC_ICDICFR7_IV2_VBUFERR1_1            (0x00000008uL)
+#define INTC_ICDICFR7_IV4_VBUFERR1_0            (0x00000010uL)
+#define INTC_ICDICFR7_IV4_VBUFERR1_1            (0x00000020uL)
+#define INTC_ICDICFR7_S1_WLINE1_0               (0x00000040uL)
+#define INTC_ICDICFR7_S1_WLINE1_1               (0x00000080uL)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_0           (0x00000100uL)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_1           (0x00000200uL)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_0           (0x00000400uL)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_1           (0x00000800uL)
+#define INTC_ICDICFR7_OIR_VLINE1_0              (0x00001000uL)
+#define INTC_ICDICFR7_OIR_VLINE1_1              (0x00002000uL)
+#define INTC_ICDICFR7_OIR_VFIELD1_0             (0x00004000uL)
+#define INTC_ICDICFR7_OIR_VFIELD1_1             (0x00008000uL)
+#define INTC_ICDICFR7_IV7_VBUFERR1_0            (0x00010000uL)
+#define INTC_ICDICFR7_IV7_VBUFERR1_1            (0x00020000uL)
+#define INTC_ICDICFR7_IV8_VBUFERR1_0            (0x00040000uL)
+#define INTC_ICDICFR7_IV8_VBUFERR1_1            (0x00080000uL)
+#define INTC_ICDICFR7_IMRDI_0                   (0x00400000uL)
+#define INTC_ICDICFR7_IMRDI_1                   (0x00800000uL)
+#define INTC_ICDICFR7_IMR2I0_0                  (0x01000000uL)
+#define INTC_ICDICFR7_IMR2I0_1                  (0x02000000uL)
+#define INTC_ICDICFR7_IMR2I1_0                  (0x04000000uL)
+#define INTC_ICDICFR7_IMR2I1_1                  (0x08000000uL)
+#define INTC_ICDICFR7_JEDI_0                    (0x10000000uL)
+#define INTC_ICDICFR7_JEDI_1                    (0x20000000uL)
+#define INTC_ICDICFR7_JDTI_0                    (0x40000000uL)
+#define INTC_ICDICFR7_JDTI_1                    (0x80000000uL)
+
+#define INTC_ICDICFR8_CMP0_0                    (0x00000001uL)
+#define INTC_ICDICFR8_CMP0_1                    (0x00000002uL)
+#define INTC_ICDICFR8_CMP1_0                    (0x00000004uL)
+#define INTC_ICDICFR8_CMP1_1                    (0x00000008uL)
+#define INTC_ICDICFR8_INT0_0                    (0x00000010uL)
+#define INTC_ICDICFR8_INT0_1                    (0x00000020uL)
+#define INTC_ICDICFR8_INT1_0                    (0x00000040uL)
+#define INTC_ICDICFR8_INT1_1                    (0x00000080uL)
+#define INTC_ICDICFR8_INT2_0                    (0x00000100uL)
+#define INTC_ICDICFR8_INT2_1                    (0x00000200uL)
+#define INTC_ICDICFR8_INT3_0                    (0x00000400uL)
+#define INTC_ICDICFR8_INT3_1                    (0x00000800uL)
+#define INTC_ICDICFR8_OSTM0TINT_0               (0x00001000uL)
+#define INTC_ICDICFR8_OSTM0TINT_1               (0x00002000uL)
+#define INTC_ICDICFR8_OSTM1TINT_0               (0x00004000uL)
+#define INTC_ICDICFR8_OSTM1TINT_1               (0x00008000uL)
+#define INTC_ICDICFR8_CMI_0                     (0x00010000uL)
+#define INTC_ICDICFR8_CMI_1                     (0x00020000uL)
+#define INTC_ICDICFR8_WTOUT_0                   (0x00040000uL)
+#define INTC_ICDICFR8_WTOUT_1                   (0x00080000uL)
+#define INTC_ICDICFR8_ITI_0                     (0x00100000uL)
+#define INTC_ICDICFR8_ITI_1                     (0x00200000uL)
+#define INTC_ICDICFR8_TGI0A_0                   (0x00400000uL)
+#define INTC_ICDICFR8_TGI0A_1                   (0x00800000uL)
+#define INTC_ICDICFR8_TGI0B_0                   (0x01000000uL)
+#define INTC_ICDICFR8_TGI0B_1                   (0x02000000uL)
+#define INTC_ICDICFR8_TGI0C_0                   (0x04000000uL)
+#define INTC_ICDICFR8_TGI0C_1                   (0x08000000uL)
+#define INTC_ICDICFR8_TGI0D_0                   (0x10000000uL)
+#define INTC_ICDICFR8_TGI0D_1                   (0x20000000uL)
+#define INTC_ICDICFR8_TGI0V_0                   (0x40000000uL)
+#define INTC_ICDICFR8_TGI0V_1                   (0x80000000uL)
+
+#define INTC_ICDICFR9_TGI0E_0                   (0x00000001uL)
+#define INTC_ICDICFR9_TGI0E_1                   (0x00000002uL)
+#define INTC_ICDICFR9_TGI0F_0                   (0x00000004uL)
+#define INTC_ICDICFR9_TGI0F_1                   (0x00000008uL)
+#define INTC_ICDICFR9_TGI1A_0                   (0x00000010uL)
+#define INTC_ICDICFR9_TGI1A_1                   (0x00000020uL)
+#define INTC_ICDICFR9_TGI1B_0                   (0x00000040uL)
+#define INTC_ICDICFR9_TGI1B_1                   (0x00000080uL)
+#define INTC_ICDICFR9_TGI1V_0                   (0x00000100uL)
+#define INTC_ICDICFR9_TGI1V_1                   (0x00000200uL)
+#define INTC_ICDICFR9_TGI1U_0                   (0x00000400uL)
+#define INTC_ICDICFR9_TGI1U_1                   (0x00000800uL)
+#define INTC_ICDICFR9_TGI2A_0                   (0x00001000uL)
+#define INTC_ICDICFR9_TGI2A_1                   (0x00002000uL)
+#define INTC_ICDICFR9_TGI2B_0                   (0x00004000uL)
+#define INTC_ICDICFR9_TGI2B_1                   (0x00008000uL)
+#define INTC_ICDICFR9_TGI2V_0                   (0x00010000uL)
+#define INTC_ICDICFR9_TGI2V_1                   (0x00020000uL)
+#define INTC_ICDICFR9_TGI2U_0                   (0x00040000uL)
+#define INTC_ICDICFR9_TGI2U_1                   (0x00080000uL)
+#define INTC_ICDICFR9_TGI3A_0                   (0x00100000uL)
+#define INTC_ICDICFR9_TGI3A_1                   (0x00200000uL)
+#define INTC_ICDICFR9_TGI3B_0                   (0x00400000uL)
+#define INTC_ICDICFR9_TGI3B_1                   (0x00800000uL)
+#define INTC_ICDICFR9_TGI3C_0                   (0x01000000uL)
+#define INTC_ICDICFR9_TGI3C_1                   (0x02000000uL)
+#define INTC_ICDICFR9_TGI3D_0                   (0x04000000uL)
+#define INTC_ICDICFR9_TGI3D_1                   (0x08000000uL)
+#define INTC_ICDICFR9_TGI3V_0                   (0x10000000uL)
+#define INTC_ICDICFR9_TGI3V_1                   (0x20000000uL)
+#define INTC_ICDICFR9_TGI4A_0                   (0x40000000uL)
+#define INTC_ICDICFR9_TGI4A_1                   (0x80000000uL)
+
+#define INTC_ICDICFR10_TGI4B_0                  (0x00000001uL)
+#define INTC_ICDICFR10_TGI4B_1                  (0x00000002uL)
+#define INTC_ICDICFR10_TGI4C_0                  (0x00000004uL)
+#define INTC_ICDICFR10_TGI4C_1                  (0x00000008uL)
+#define INTC_ICDICFR10_TGI4D_0                  (0x00000010uL)
+#define INTC_ICDICFR10_TGI4D_1                  (0x00000020uL)
+#define INTC_ICDICFR10_TGI4V_0                  (0x00000040uL)
+#define INTC_ICDICFR10_TGI4V_1                  (0x00000080uL)
+#define INTC_ICDICFR10_CMI1_0                   (0x00000100uL)
+#define INTC_ICDICFR10_CMI1_1                   (0x00000200uL)
+#define INTC_ICDICFR10_CMI2_0                   (0x00000400uL)
+#define INTC_ICDICFR10_CMI2_1                   (0x00000800uL)
+#define INTC_ICDICFR10_SGDEI0_0                 (0x00001000uL)
+#define INTC_ICDICFR10_SGDEI0_1                 (0x00002000uL)
+#define INTC_ICDICFR10_SGDEI1_0                 (0x00004000uL)
+#define INTC_ICDICFR10_SGDEI1_1                 (0x00008000uL)
+#define INTC_ICDICFR10_SGDEI2_0                 (0x00010000uL)
+#define INTC_ICDICFR10_SGDEI2_1                 (0x00020000uL)
+#define INTC_ICDICFR10_SGDEI3_0                 (0x00040000uL)
+#define INTC_ICDICFR10_SGDEI3_1                 (0x00080000uL)
+#define INTC_ICDICFR10_ADI_0                    (0x00100000uL)
+#define INTC_ICDICFR10_ADI_1                    (0x00200000uL)
+#define INTC_ICDICFR10_LMTI_0                   (0x00400000uL)
+#define INTC_ICDICFR10_LMTI_1                   (0x00800000uL)
+#define INTC_ICDICFR10_SSII0_0                  (0x01000000uL)
+#define INTC_ICDICFR10_SSII0_1                  (0x02000000uL)
+#define INTC_ICDICFR10_SSIRXI0_0                (0x04000000uL)
+#define INTC_ICDICFR10_SSIRXI0_1                (0x08000000uL)
+#define INTC_ICDICFR10_SSITXI0_0                (0x10000000uL)
+#define INTC_ICDICFR10_SSITXI0_1                (0x20000000uL)
+#define INTC_ICDICFR10_SSII1_0                  (0x40000000uL)
+#define INTC_ICDICFR10_SSII1_1                  (0x80000000uL)
+
+#define INTC_ICDICFR11_SSIRXI1_0                (0x00000001uL)
+#define INTC_ICDICFR11_SSIRXI1_1                (0x00000002uL)
+#define INTC_ICDICFR11_SSITXI1_0                (0x00000004uL)
+#define INTC_ICDICFR11_SSITXI1_1                (0x00000008uL)
+#define INTC_ICDICFR11_SSII2_0                  (0x00000010uL)
+#define INTC_ICDICFR11_SSII2_1                  (0x00000020uL)
+#define INTC_ICDICFR11_SSIRTI2_0                (0x00000040uL)
+#define INTC_ICDICFR11_SSIRTI2_1                (0x00000080uL)
+#define INTC_ICDICFR11_SSII3_0                  (0x00000100uL)
+#define INTC_ICDICFR11_SSII3_1                  (0x00000200uL)
+#define INTC_ICDICFR11_SSIRXI3_0                (0x00000400uL)
+#define INTC_ICDICFR11_SSIRXI3_1                (0x00000800uL)
+#define INTC_ICDICFR11_SSITXI3_0                (0x00001000uL)
+#define INTC_ICDICFR11_SSITXI3_1                (0x00002000uL)
+#define INTC_ICDICFR11_SSII4_0                  (0x00004000uL)
+#define INTC_ICDICFR11_SSII4_1                  (0x00008000uL)
+#define INTC_ICDICFR11_SSIRTI4_0                (0x00010000uL)
+#define INTC_ICDICFR11_SSIRTI4_1                (0x00020000uL)
+#define INTC_ICDICFR11_SSII5_0                  (0x00040000uL)
+#define INTC_ICDICFR11_SSII5_1                  (0x00080000uL)
+#define INTC_ICDICFR11_SSIRXI5_0                (0x00100000uL)
+#define INTC_ICDICFR11_SSIRXI5_1                (0x00200000uL)
+#define INTC_ICDICFR11_SSITXI5_0                (0x00400000uL)
+#define INTC_ICDICFR11_SSITXI5_1                (0x00800000uL)
+#define INTC_ICDICFR11_SPDIFI_0                 (0x01000000uL)
+#define INTC_ICDICFR11_SPDIFI_1                 (0x02000000uL)
+#define INTC_ICDICFR11_INTIICTEI0_0             (0x04000000uL)
+#define INTC_ICDICFR11_INTIICTEI0_1             (0x08000000uL)
+#define INTC_ICDICFR11_INTIICRI0_0              (0x10000000uL)
+#define INTC_ICDICFR11_INTIICRI0_1              (0x20000000uL)
+#define INTC_ICDICFR11_INTIICTI0_0              (0x40000000uL)
+#define INTC_ICDICFR11_INTIICTI0_1              (0x80000000uL)
+
+#define INTC_ICDICFR12_INTIICSPI0_0             (0x00000001uL)
+#define INTC_ICDICFR12_INTIICSPI0_1             (0x00000002uL)
+#define INTC_ICDICFR12_INTIICSTI0_0             (0x00000004uL)
+#define INTC_ICDICFR12_INTIICSTI0_1             (0x00000008uL)
+#define INTC_ICDICFR12_INTIICNAKI0_0            (0x00000010uL)
+#define INTC_ICDICFR12_INTIICNAKI0_1            (0x00000020uL)
+#define INTC_ICDICFR12_INTIICALI0_0             (0x00000040uL)
+#define INTC_ICDICFR12_INTIICALI0_1             (0x00000080uL)
+#define INTC_ICDICFR12_INTIICTMOI0_0            (0x00000100uL)
+#define INTC_ICDICFR12_INTIICTMOI0_1            (0x00000200uL)
+#define INTC_ICDICFR12_INTIICTEI1_0             (0x00000400uL)
+#define INTC_ICDICFR12_INTIICTEI1_1             (0x00000800uL)
+#define INTC_ICDICFR12_INTIICRI1_0              (0x00001000uL)
+#define INTC_ICDICFR12_INTIICRI1_1              (0x00002000uL)
+#define INTC_ICDICFR12_INTIICTI1_0              (0x00004000uL)
+#define INTC_ICDICFR12_INTIICTI1_1              (0x00008000uL)
+#define INTC_ICDICFR12_INTIICSPI1_0             (0x00010000uL)
+#define INTC_ICDICFR12_INTIICSPI1_1             (0x00020000uL)
+#define INTC_ICDICFR12_INTIICSTI1_0             (0x00040000uL)
+#define INTC_ICDICFR12_INTIICSTI1_1             (0x00080000uL)
+#define INTC_ICDICFR12_INTIICNAKI1_0            (0x00100000uL)
+#define INTC_ICDICFR12_INTIICNAKI1_1            (0x00200000uL)
+#define INTC_ICDICFR12_INTIICALI1_0             (0x00400000uL)
+#define INTC_ICDICFR12_INTIICALI1_1             (0x00800000uL)
+#define INTC_ICDICFR12_INTIICTMOI1_0            (0x01000000uL)
+#define INTC_ICDICFR12_INTIICTMOI1_1            (0x02000000uL)
+#define INTC_ICDICFR12_INTIICTEI2_0             (0x04000000uL)
+#define INTC_ICDICFR12_INTIICTEI2_1             (0x08000000uL)
+#define INTC_ICDICFR12_INTIICRI2_0              (0x10000000uL)
+#define INTC_ICDICFR12_INTIICRI2_1              (0x20000000uL)
+#define INTC_ICDICFR12_INTIICTI2_0              (0x40000000uL)
+#define INTC_ICDICFR12_INTIICTI2_1              (0x80000000uL)
+
+#define INTC_ICDICFR13_INTIICSPI2_0             (0x00000001uL)
+#define INTC_ICDICFR13_INTIICSPI2_1             (0x00000002uL)
+#define INTC_ICDICFR13_INTIICSTI2_0             (0x00000004uL)
+#define INTC_ICDICFR13_INTIICSTI2_1             (0x00000008uL)
+#define INTC_ICDICFR13_INTIICNAKI2_0            (0x00000010uL)
+#define INTC_ICDICFR13_INTIICNAKI2_1            (0x00000020uL)
+#define INTC_ICDICFR13_INTIICALI2_0             (0x00000040uL)
+#define INTC_ICDICFR13_INTIICALI2_1             (0x00000080uL)
+#define INTC_ICDICFR13_INTIICTMOI2_0            (0x00000100uL)
+#define INTC_ICDICFR13_INTIICTMOI2_1            (0x00000200uL)
+#define INTC_ICDICFR13_INTIICTEI3_0             (0x00000400uL)
+#define INTC_ICDICFR13_INTIICTEI3_1             (0x00000800uL)
+#define INTC_ICDICFR13_INTIICRI3_0              (0x00001000uL)
+#define INTC_ICDICFR13_INTIICRI3_1              (0x00002000uL)
+#define INTC_ICDICFR13_INTIICTI3_0              (0x00004000uL)
+#define INTC_ICDICFR13_INTIICTI3_1              (0x00008000uL)
+#define INTC_ICDICFR13_INTIICSPI3_0             (0x00010000uL)
+#define INTC_ICDICFR13_INTIICSPI3_1             (0x00020000uL)
+#define INTC_ICDICFR13_INTIICSTI3_0             (0x00040000uL)
+#define INTC_ICDICFR13_INTIICSTI3_1             (0x00080000uL)
+#define INTC_ICDICFR13_INTIICNAKI3_0            (0x00100000uL)
+#define INTC_ICDICFR13_INTIICNAKI3_1            (0x00200000uL)
+#define INTC_ICDICFR13_INTIICALI3_0             (0x00400000uL)
+#define INTC_ICDICFR13_INTIICALI3_1             (0x00800000uL)
+#define INTC_ICDICFR13_INTIICTMOI3_0            (0x01000000uL)
+#define INTC_ICDICFR13_INTIICTMOI3_1            (0x02000000uL)
+#define INTC_ICDICFR13_BRI0_0                   (0x04000000uL)
+#define INTC_ICDICFR13_BRI0_1                   (0x08000000uL)
+#define INTC_ICDICFR13_ERI0_0                   (0x10000000uL)
+#define INTC_ICDICFR13_ERI0_1                   (0x20000000uL)
+#define INTC_ICDICFR13_RXI0_0                   (0x40000000uL)
+#define INTC_ICDICFR13_RXI0_1                   (0x80000000uL)
+
+#define INTC_ICDICFR14_TXI0_0                   (0x00000001uL)
+#define INTC_ICDICFR14_TXI0_1                   (0x00000002uL)
+#define INTC_ICDICFR14_BRI1_0                   (0x00000004uL)
+#define INTC_ICDICFR14_BRI1_1                   (0x00000008uL)
+#define INTC_ICDICFR14_ERI1_0                   (0x00000010uL)
+#define INTC_ICDICFR14_ERI1_1                   (0x00000020uL)
+#define INTC_ICDICFR14_RXI1_0                   (0x00000040uL)
+#define INTC_ICDICFR14_RXI1_1                   (0x00000080uL)
+#define INTC_ICDICFR14_TXI1_0                   (0x00000100uL)
+#define INTC_ICDICFR14_TXI1_1                   (0x00000200uL)
+#define INTC_ICDICFR14_BRI2_0                   (0x00000400uL)
+#define INTC_ICDICFR14_BRI2_1                   (0x00000800uL)
+#define INTC_ICDICFR14_ERI2_0                   (0x00001000uL)
+#define INTC_ICDICFR14_ERI2_1                   (0x00002000uL)
+#define INTC_ICDICFR14_RXI2_0                   (0x00004000uL)
+#define INTC_ICDICFR14_RXI2_1                   (0x00008000uL)
+#define INTC_ICDICFR14_TXI2_0                   (0x00010000uL)
+#define INTC_ICDICFR14_TXI2_1                   (0x00020000uL)
+#define INTC_ICDICFR14_BRI3_0                   (0x00040000uL)
+#define INTC_ICDICFR14_BRI3_1                   (0x00080000uL)
+#define INTC_ICDICFR14_ERI3_0                   (0x00100000uL)
+#define INTC_ICDICFR14_ERI3_1                   (0x00200000uL)
+#define INTC_ICDICFR14_RXI3_0                   (0x00400000uL)
+#define INTC_ICDICFR14_RXI3_1                   (0x00800000uL)
+#define INTC_ICDICFR14_TXI3_0                   (0x01000000uL)
+#define INTC_ICDICFR14_TXI3_1                   (0x02000000uL)
+#define INTC_ICDICFR14_BRI4_0                   (0x04000000uL)
+#define INTC_ICDICFR14_BRI4_1                   (0x08000000uL)
+#define INTC_ICDICFR14_ERI4_0                   (0x10000000uL)
+#define INTC_ICDICFR14_ERI4_1                   (0x20000000uL)
+#define INTC_ICDICFR14_RXI4_0                   (0x40000000uL)
+#define INTC_ICDICFR14_RXI4_1                   (0x80000000uL)
+
+#define INTC_ICDICFR15_TXI4_0                   (0x00000001uL)
+#define INTC_ICDICFR15_TXI4_1                   (0x00000002uL)
+#define INTC_ICDICFR15_BRI5_0                   (0x00000004uL)
+#define INTC_ICDICFR15_BRI5_1                   (0x00000008uL)
+#define INTC_ICDICFR15_ERI5_0                   (0x00000010uL)
+#define INTC_ICDICFR15_ERI5_1                   (0x00000020uL)
+#define INTC_ICDICFR15_RXI5_0                   (0x00000040uL)
+#define INTC_ICDICFR15_RXI5_1                   (0x00000080uL)
+#define INTC_ICDICFR15_TXI5_0                   (0x00000100uL)
+#define INTC_ICDICFR15_TXI5_1                   (0x00000200uL)
+#define INTC_ICDICFR15_BRI6_0                   (0x00000400uL)
+#define INTC_ICDICFR15_BRI6_1                   (0x00000800uL)
+#define INTC_ICDICFR15_ERI6_0                   (0x00001000uL)
+#define INTC_ICDICFR15_ERI6_1                   (0x00002000uL)
+#define INTC_ICDICFR15_RXI6_0                   (0x00004000uL)
+#define INTC_ICDICFR15_RXI6_1                   (0x00008000uL)
+#define INTC_ICDICFR15_TXI6_0                   (0x00010000uL)
+#define INTC_ICDICFR15_TXI6_1                   (0x00020000uL)
+#define INTC_ICDICFR15_BRI7_0                   (0x00040000uL)
+#define INTC_ICDICFR15_BRI7_1                   (0x00080000uL)
+#define INTC_ICDICFR15_ERI7_0                   (0x00100000uL)
+#define INTC_ICDICFR15_ERI7_1                   (0x00200000uL)
+#define INTC_ICDICFR15_RXI7_0                   (0x00400000uL)
+#define INTC_ICDICFR15_RXI7_1                   (0x00800000uL)
+#define INTC_ICDICFR15_TXI7_0                   (0x01000000uL)
+#define INTC_ICDICFR15_TXI7_1                   (0x02000000uL)
+#define INTC_ICDICFR15_INTRCANGERR_0            (0x04000000uL)
+#define INTC_ICDICFR15_INTRCANGERR_1            (0x08000000uL)
+#define INTC_ICDICFR15_INTRCANGRECC_0           (0x10000000uL)
+#define INTC_ICDICFR15_INTRCANGRECC_1           (0x20000000uL)
+#define INTC_ICDICFR15_INTRCAN0REC_0            (0x40000000uL)
+#define INTC_ICDICFR15_INTRCAN0REC_1            (0x80000000uL)
+
+#define INTC_ICDICFR16_INTRCAN0ERR_0            (0x00000001uL)
+#define INTC_ICDICFR16_INTRCAN0ERR_1            (0x00000002uL)
+#define INTC_ICDICFR16_INTRCAN0TRX_0            (0x00000004uL)
+#define INTC_ICDICFR16_INTRCAN0TRX_1            (0x00000008uL)
+#define INTC_ICDICFR16_INTRCAN1REC_0            (0x00000010uL)
+#define INTC_ICDICFR16_INTRCAN1REC_1            (0x00000020uL)
+#define INTC_ICDICFR16_INTRCAN1ERR_0            (0x00000040uL)
+#define INTC_ICDICFR16_INTRCAN1ERR_1            (0x00000080uL)
+#define INTC_ICDICFR16_INTRCAN1TRX_0            (0x00000100uL)
+#define INTC_ICDICFR16_INTRCAN1TRX_1            (0x00000200uL)
+#define INTC_ICDICFR16_INTRCAN2REC_0            (0x00000400uL)
+#define INTC_ICDICFR16_INTRCAN2REC_1            (0x00000800uL)
+#define INTC_ICDICFR16_INTRCAN2ERR_0            (0x00001000uL)
+#define INTC_ICDICFR16_INTRCAN2ERR_1            (0x00002000uL)
+#define INTC_ICDICFR16_INTRCAN2TRX_0            (0x00004000uL)
+#define INTC_ICDICFR16_INTRCAN2TRX_1            (0x00008000uL)
+#define INTC_ICDICFR16_INTRCAN3REC_0            (0x00010000uL)
+#define INTC_ICDICFR16_INTRCAN3REC_1            (0x00020000uL)
+#define INTC_ICDICFR16_INTRCAN3ERR_0            (0x00040000uL)
+#define INTC_ICDICFR16_INTRCAN3ERR_1            (0x00080000uL)
+#define INTC_ICDICFR16_INTRCAN3TRX_0            (0x00100000uL)
+#define INTC_ICDICFR16_INTRCAN3TRX_1            (0x00200000uL)
+#define INTC_ICDICFR16_INTRCAN4REC_0            (0x00400000uL)
+#define INTC_ICDICFR16_INTRCAN4REC_1            (0x00800000uL)
+#define INTC_ICDICFR16_INTRCAN4ERR_0            (0x01000000uL)
+#define INTC_ICDICFR16_INTRCAN4ERR_1            (0x02000000uL)
+#define INTC_ICDICFR16_INTRCAN4TRX_0            (0x04000000uL)
+#define INTC_ICDICFR16_INTRCAN4TRX_1            (0x08000000uL)
+#define INTC_ICDICFR16_SPEI0_0                  (0x10000000uL)
+#define INTC_ICDICFR16_SPEI0_1                  (0x20000000uL)
+#define INTC_ICDICFR16_SPRI0_0                  (0x40000000uL)
+#define INTC_ICDICFR16_SPRI0_1                  (0x80000000uL)
+
+#define INTC_ICDICFR17_SPTI0_0                  (0x00000001uL)
+#define INTC_ICDICFR17_SPTI0_1                  (0x00000002uL)
+#define INTC_ICDICFR17_SPEI1_0                  (0x00000004uL)
+#define INTC_ICDICFR17_SPEI1_1                  (0x00000008uL)
+#define INTC_ICDICFR17_SPRI1_0                  (0x00000010uL)
+#define INTC_ICDICFR17_SPRI1_1                  (0x00000020uL)
+#define INTC_ICDICFR17_SPTI1_0                  (0x00000040uL)
+#define INTC_ICDICFR17_SPTI1_1                  (0x00000080uL)
+#define INTC_ICDICFR17_SPEI2_0                  (0x00000100uL)
+#define INTC_ICDICFR17_SPEI2_1                  (0x00000200uL)
+#define INTC_ICDICFR17_SPRI2_0                  (0x00000400uL)
+#define INTC_ICDICFR17_SPRI2_1                  (0x00000800uL)
+#define INTC_ICDICFR17_SPTI2_0                  (0x00001000uL)
+#define INTC_ICDICFR17_SPTI2_1                  (0x00002000uL)
+#define INTC_ICDICFR17_SPEI3_0                  (0x00004000uL)
+#define INTC_ICDICFR17_SPEI3_1                  (0x00008000uL)
+#define INTC_ICDICFR17_SPRI3_0                  (0x00010000uL)
+#define INTC_ICDICFR17_SPRI3_1                  (0x00020000uL)
+#define INTC_ICDICFR17_SPTI3_0                  (0x00040000uL)
+#define INTC_ICDICFR17_SPTI3_1                  (0x00080000uL)
+#define INTC_ICDICFR17_SPEI4_0                  (0x00100000uL)
+#define INTC_ICDICFR17_SPEI4_1                  (0x00200000uL)
+#define INTC_ICDICFR17_SPRI4_0                  (0x00400000uL)
+#define INTC_ICDICFR17_SPRI4_1                  (0x00800000uL)
+#define INTC_ICDICFR17_SPTI4_0                  (0x01000000uL)
+#define INTC_ICDICFR17_SPTI4_1                  (0x02000000uL)
+#define INTC_ICDICFR17_IEBBTD_0                 (0x04000000uL)
+#define INTC_ICDICFR17_IEBBTD_1                 (0x08000000uL)
+#define INTC_ICDICFR17_IEBBTERR_0               (0x10000000uL)
+#define INTC_ICDICFR17_IEBBTERR_1               (0x20000000uL)
+#define INTC_ICDICFR17_IEBBTSTA_0               (0x40000000uL)
+#define INTC_ICDICFR17_IEBBTSTA_1               (0x80000000uL)
+
+#define INTC_ICDICFR18_IEBBTV_0                 (0x00000001uL)
+#define INTC_ICDICFR18_IEBBTV_1                 (0x00000002uL)
+#define INTC_ICDICFR18_ISY_0                    (0x00000004uL)
+#define INTC_ICDICFR18_ISY_1                    (0x00000008uL)
+#define INTC_ICDICFR18_IERR_0                   (0x00000010uL)
+#define INTC_ICDICFR18_IERR_1                   (0x00000020uL)
+#define INTC_ICDICFR18_ITARG_0                  (0x00000040uL)
+#define INTC_ICDICFR18_ITARG_1                  (0x00000080uL)
+#define INTC_ICDICFR18_ISEC_0                   (0x00000100uL)
+#define INTC_ICDICFR18_ISEC_1                   (0x00000200uL)
+#define INTC_ICDICFR18_IBUF_0                   (0x00000400uL)
+#define INTC_ICDICFR18_IBUF_1                   (0x00000800uL)
+#define INTC_ICDICFR18_IREADY_0                 (0x00001000uL)
+#define INTC_ICDICFR18_IREADY_1                 (0x00002000uL)
+#define INTC_ICDICFR18_FLSTE_0                  (0x00004000uL)
+#define INTC_ICDICFR18_FLSTE_1                  (0x00008000uL)
+#define INTC_ICDICFR18_FLTENDI_0                (0x00010000uL)
+#define INTC_ICDICFR18_FLTENDI_1                (0x00020000uL)
+#define INTC_ICDICFR18_FLTREQ0I_0               (0x00040000uL)
+#define INTC_ICDICFR18_FLTREQ0I_1               (0x00080000uL)
+#define INTC_ICDICFR18_FLTREQ1I_0               (0x00100000uL)
+#define INTC_ICDICFR18_FLTREQ1I_1               (0x00200000uL)
+#define INTC_ICDICFR18_MMC0_0                   (0x00400000uL)
+#define INTC_ICDICFR18_MMC0_1                   (0x00800000uL)
+#define INTC_ICDICFR18_MMC1_0                   (0x01000000uL)
+#define INTC_ICDICFR18_MMC1_1                   (0x02000000uL)
+#define INTC_ICDICFR18_MMC2_0                   (0x04000000uL)
+#define INTC_ICDICFR18_MMC2_1                   (0x08000000uL)
+#define INTC_ICDICFR18_SDHI0_3_0                (0x10000000uL)
+#define INTC_ICDICFR18_SDHI0_3_1                (0x20000000uL)
+#define INTC_ICDICFR18_SDHI0_0_0                (0x40000000uL)
+#define INTC_ICDICFR18_SDHI0_0_1                (0x80000000uL)
+
+#define INTC_ICDICFR19_SDHI0_1_0                (0x00000001uL)
+#define INTC_ICDICFR19_SDHI0_1_1                (0x00000002uL)
+#define INTC_ICDICFR19_SDHI1_3_0                (0x00000004uL)
+#define INTC_ICDICFR19_SDHI1_3_1                (0x00000008uL)
+#define INTC_ICDICFR19_SDHI1_0_0                (0x00000010uL)
+#define INTC_ICDICFR19_SDHI1_0_1                (0x00000020uL)
+#define INTC_ICDICFR19_SDHI1_1_0                (0x00000040uL)
+#define INTC_ICDICFR19_SDHI1_1_1                (0x00000080uL)
+#define INTC_ICDICFR19_ARM_0                    (0x00000100uL)
+#define INTC_ICDICFR19_ARM_1                    (0x00000200uL)
+#define INTC_ICDICFR19_PRD_0                    (0x00000400uL)
+#define INTC_ICDICFR19_PRD_1                    (0x00000800uL)
+#define INTC_ICDICFR19_CUP_0                    (0x00001000uL)
+#define INTC_ICDICFR19_CUP_1                    (0x00002000uL)
+#define INTC_ICDICFR19_SCUAI0_0                 (0x00004000uL)
+#define INTC_ICDICFR19_SCUAI0_1                 (0x00008000uL)
+#define INTC_ICDICFR19_SCUAI1_0                 (0x00010000uL)
+#define INTC_ICDICFR19_SCUAI1_1                 (0x00020000uL)
+#define INTC_ICDICFR19_SCUFDI0_0                (0x00040000uL)
+#define INTC_ICDICFR19_SCUFDI0_1                (0x00080000uL)
+#define INTC_ICDICFR19_SCUFDI1_0                (0x00100000uL)
+#define INTC_ICDICFR19_SCUFDI1_1                (0x00200000uL)
+#define INTC_ICDICFR19_SCUFDI2_0                (0x00400000uL)
+#define INTC_ICDICFR19_SCUFDI2_1                (0x00800000uL)
+#define INTC_ICDICFR19_SCUFDI3_0                (0x01000000uL)
+#define INTC_ICDICFR19_SCUFDI3_1                (0x02000000uL)
+#define INTC_ICDICFR19_SCUFUI0_0                (0x04000000uL)
+#define INTC_ICDICFR19_SCUFUI0_1                (0x08000000uL)
+#define INTC_ICDICFR19_SCUFUI1_0                (0x10000000uL)
+#define INTC_ICDICFR19_SCUFUI1_1                (0x20000000uL)
+#define INTC_ICDICFR19_SCUFUI2_0                (0x40000000uL)
+#define INTC_ICDICFR19_SCUFUI2_1                (0x80000000uL)
+
+#define INTC_ICDICFR20_SCUFUI3_0                (0x00000001uL)
+#define INTC_ICDICFR20_SCUFUI3_1                (0x00000002uL)
+#define INTC_ICDICFR20_SCUDVI0_0                (0x00000004uL)
+#define INTC_ICDICFR20_SCUDVI0_1                (0x00000008uL)
+#define INTC_ICDICFR20_SCUDVI1_0                (0x00000010uL)
+#define INTC_ICDICFR20_SCUDVI1_1                (0x00000020uL)
+#define INTC_ICDICFR20_SCUDVI2_0                (0x00000040uL)
+#define INTC_ICDICFR20_SCUDVI2_1                (0x00000080uL)
+#define INTC_ICDICFR20_SCUDVI3_0                (0x00000100uL)
+#define INTC_ICDICFR20_SCUDVI3_1                (0x00000200uL)
+#define INTC_ICDICFR20_MLB_CINT_0               (0x00000400uL)
+#define INTC_ICDICFR20_MLB_CINT_1               (0x00000800uL)
+#define INTC_ICDICFR20_MLB_SINT_0               (0x00001000uL)
+#define INTC_ICDICFR20_MLB_SINT_1               (0x00002000uL)
+#define INTC_ICDICFR20_DRC0_0                   (0x00004000uL)
+#define INTC_ICDICFR20_DRC0_1                   (0x00008000uL)
+#define INTC_ICDICFR20_DRC1_0                   (0x00010000uL)
+#define INTC_ICDICFR20_DRC1_1                   (0x00020000uL)
+#define INTC_ICDICFR20_LINI0_INT_T_0            (0x00400000uL)
+#define INTC_ICDICFR20_LINI0_INT_T_1            (0x00800000uL)
+#define INTC_ICDICFR20_LINI0_INT_R_0            (0x01000000uL)
+#define INTC_ICDICFR20_LINI0_INT_R_1            (0x02000000uL)
+#define INTC_ICDICFR20_LINI0_INT_S_0            (0x04000000uL)
+#define INTC_ICDICFR20_LINI0_INT_S_1            (0x08000000uL)
+#define INTC_ICDICFR20_LINI0_INT_M_0            (0x10000000uL)
+#define INTC_ICDICFR20_LINI0_INT_M_1            (0x20000000uL)
+#define INTC_ICDICFR20_LINI1_INT_T_0            (0x40000000uL)
+#define INTC_ICDICFR20_LINI1_INT_T_1            (0x80000000uL)
+
+#define INTC_ICDICFR21_LINI1_INT_R_0            (0x00000001uL)
+#define INTC_ICDICFR21_LINI1_INT_R_1            (0x00000002uL)
+#define INTC_ICDICFR21_LINI1_INT_S_0            (0x00000004uL)
+#define INTC_ICDICFR21_LINI1_INT_S_1            (0x00000008uL)
+#define INTC_ICDICFR21_LINI1_INT_M_0            (0x00000010uL)
+#define INTC_ICDICFR21_LINI1_INT_M_1            (0x00000020uL)
+#define INTC_ICDICFR21_ERI0_0                   (0x00400000uL)
+#define INTC_ICDICFR21_ERI0_1                   (0x00800000uL)
+#define INTC_ICDICFR21_RXI0_0                   (0x01000000uL)
+#define INTC_ICDICFR21_RXI0_1                   (0x02000000uL)
+#define INTC_ICDICFR21_TXI0_0                   (0x04000000uL)
+#define INTC_ICDICFR21_TXI0_1                   (0x08000000uL)
+#define INTC_ICDICFR21_TEI0_0                   (0x10000000uL)
+#define INTC_ICDICFR21_TEI0_1                   (0x20000000uL)
+#define INTC_ICDICFR21_ERI1_0                   (0x40000000uL)
+#define INTC_ICDICFR21_ERI1_1                   (0x80000000uL)
+
+#define INTC_ICDICFR22_RXI1_0                   (0x00000001uL)
+#define INTC_ICDICFR22_RXI1_1                   (0x00000002uL)
+#define INTC_ICDICFR22_TXI1_0                   (0x00000004uL)
+#define INTC_ICDICFR22_TXI1_1                   (0x00000008uL)
+#define INTC_ICDICFR22_TEI1_0                   (0x00000010uL)
+#define INTC_ICDICFR22_TEI1_1                   (0x00000020uL)
+#define INTC_ICDICFR22_AVBI_DATA_0              (0x00000040uL)
+#define INTC_ICDICFR22_AVBI_DATA_1              (0x00000080uL)
+#define INTC_ICDICFR22_AVBI_ERROR_0             (0x00000100uL)
+#define INTC_ICDICFR22_AVBI_ERROR_1             (0x00000200uL)
+#define INTC_ICDICFR22_AVBI_MANAGE_0            (0x00000400uL)
+#define INTC_ICDICFR22_AVBI_MANAGE_1            (0x00000800uL)
+#define INTC_ICDICFR22_AVBI_MAC_0               (0x00001000uL)
+#define INTC_ICDICFR22_AVBI_MAC_1               (0x00002000uL)
+#define INTC_ICDICFR22_ETHERI_0                 (0x00004000uL)
+#define INTC_ICDICFR22_ETHERI_1                 (0x00008000uL)
+#define INTC_ICDICFR22_CEUI_0                   (0x01000000uL)
+#define INTC_ICDICFR22_CEUI_1                   (0x02000000uL)
+
+#define INTC_ICDICFR23_H2XMLB_ERRINT_0          (0x04000000uL)
+#define INTC_ICDICFR23_H2XMLB_ERRINT_1          (0x08000000uL)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_0          (0x10000000uL)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_1          (0x20000000uL)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_0        (0x40000000uL)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_1        (0x80000000uL)
+
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_0        (0x00000001uL)
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_1        (0x00000002uL)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_0       (0x00000004uL)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_1       (0x00000008uL)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_0        (0x00000010uL)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_1        (0x00000020uL)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_0       (0x00000040uL)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_1       (0x00000080uL)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_0         (0x00000100uL)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_1         (0x00000200uL)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_0          (0x00000400uL)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_1          (0x00000800uL)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_0         (0x00001000uL)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_1         (0x00002000uL)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_0         (0x00004000uL)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_1         (0x00008000uL)
+#define INTC_ICDICFR24_PRRI_0                   (0x00010000uL)
+#define INTC_ICDICFR24_PRRI_1                   (0x00020000uL)
+#define INTC_ICDICFR24_IFEI0_0                  (0x00040000uL)
+#define INTC_ICDICFR24_IFEI0_1                  (0x00080000uL)
+#define INTC_ICDICFR24_OFFI0_0                  (0x00100000uL)
+#define INTC_ICDICFR24_OFFI0_1                  (0x00200000uL)
+#define INTC_ICDICFR24_PFVEI0_0                 (0x00400000uL)
+#define INTC_ICDICFR24_PFVEI0_1                 (0x00800000uL)
+#define INTC_ICDICFR24_IFEI1_0                  (0x01000000uL)
+#define INTC_ICDICFR24_IFEI1_1                  (0x02000000uL)
+#define INTC_ICDICFR24_OFFI1_0                  (0x04000000uL)
+#define INTC_ICDICFR24_OFFI1_1                  (0x08000000uL)
+#define INTC_ICDICFR24_PFVEI1_0                 (0x10000000uL)
+#define INTC_ICDICFR24_PFVEI1_1                 (0x20000000uL)
+
+#define INTC_ICDICFR26_TINT0_0                  (0x00000001uL)
+#define INTC_ICDICFR26_TINT0_1                  (0x00000002uL)
+#define INTC_ICDICFR26_TINT1_0                  (0x00000004uL)
+#define INTC_ICDICFR26_TINT1_1                  (0x00000008uL)
+#define INTC_ICDICFR26_TINT2_0                  (0x00000010uL)
+#define INTC_ICDICFR26_TINT2_1                  (0x00000020uL)
+#define INTC_ICDICFR26_TINT3_0                  (0x00000040uL)
+#define INTC_ICDICFR26_TINT3_1                  (0x00000080uL)
+#define INTC_ICDICFR26_TINT4_0                  (0x00000100uL)
+#define INTC_ICDICFR26_TINT4_1                  (0x00000200uL)
+#define INTC_ICDICFR26_TINT5_0                  (0x00000400uL)
+#define INTC_ICDICFR26_TINT5_1                  (0x00000800uL)
+#define INTC_ICDICFR26_TINT6_0                  (0x00001000uL)
+#define INTC_ICDICFR26_TINT6_1                  (0x00002000uL)
+#define INTC_ICDICFR26_TINT7_0                  (0x00004000uL)
+#define INTC_ICDICFR26_TINT7_1                  (0x00008000uL)
+#define INTC_ICDICFR26_TINT8_0                  (0x00010000uL)
+#define INTC_ICDICFR26_TINT8_1                  (0x00020000uL)
+#define INTC_ICDICFR26_TINT9_0                  (0x00040000uL)
+#define INTC_ICDICFR26_TINT9_1                  (0x00080000uL)
+#define INTC_ICDICFR26_TINT10_0                 (0x00100000uL)
+#define INTC_ICDICFR26_TINT10_1                 (0x00200000uL)
+#define INTC_ICDICFR26_TINT11_0                 (0x00400000uL)
+#define INTC_ICDICFR26_TINT11_1                 (0x00800000uL)
+#define INTC_ICDICFR26_TINT12_0                 (0x01000000uL)
+#define INTC_ICDICFR26_TINT12_1                 (0x02000000uL)
+#define INTC_ICDICFR26_TINT13_0                 (0x04000000uL)
+#define INTC_ICDICFR26_TINT13_1                 (0x08000000uL)
+#define INTC_ICDICFR26_TINT14_0                 (0x10000000uL)
+#define INTC_ICDICFR26_TINT14_1                 (0x20000000uL)
+#define INTC_ICDICFR26_TINT15_0                 (0x40000000uL)
+#define INTC_ICDICFR26_TINT15_1                 (0x80000000uL)
+
+#define INTC_ICDICFR27_TINT16_0                 (0x00000001uL)
+#define INTC_ICDICFR27_TINT16_1                 (0x00000002uL)
+#define INTC_ICDICFR27_TINT17_0                 (0x00000004uL)
+#define INTC_ICDICFR27_TINT17_1                 (0x00000008uL)
+#define INTC_ICDICFR27_TINT18_0                 (0x00000010uL)
+#define INTC_ICDICFR27_TINT18_1                 (0x00000020uL)
+#define INTC_ICDICFR27_TINT19_0                 (0x00000040uL)
+#define INTC_ICDICFR27_TINT19_1                 (0x00000080uL)
+#define INTC_ICDICFR27_TINT20_0                 (0x00000100uL)
+#define INTC_ICDICFR27_TINT20_1                 (0x00000200uL)
+#define INTC_ICDICFR27_TINT21_0                 (0x00000400uL)
+#define INTC_ICDICFR27_TINT21_1                 (0x00000800uL)
+#define INTC_ICDICFR27_TINT22_0                 (0x00001000uL)
+#define INTC_ICDICFR27_TINT22_1                 (0x00002000uL)
+#define INTC_ICDICFR27_TINT23_0                 (0x00004000uL)
+#define INTC_ICDICFR27_TINT23_1                 (0x00008000uL)
+#define INTC_ICDICFR27_TINT24_0                 (0x00010000uL)
+#define INTC_ICDICFR27_TINT24_1                 (0x00020000uL)
+#define INTC_ICDICFR27_TINT25_0                 (0x00040000uL)
+#define INTC_ICDICFR27_TINT25_1                 (0x00080000uL)
+#define INTC_ICDICFR27_TINT26_0                 (0x00100000uL)
+#define INTC_ICDICFR27_TINT26_1                 (0x00200000uL)
+#define INTC_ICDICFR27_TINT27_0                 (0x00400000uL)
+#define INTC_ICDICFR27_TINT27_1                 (0x00800000uL)
+#define INTC_ICDICFR27_TINT28_0                 (0x01000000uL)
+#define INTC_ICDICFR27_TINT28_1                 (0x02000000uL)
+#define INTC_ICDICFR27_TINT29_0                 (0x04000000uL)
+#define INTC_ICDICFR27_TINT29_1                 (0x08000000uL)
+#define INTC_ICDICFR27_TINT30_0                 (0x10000000uL)
+#define INTC_ICDICFR27_TINT30_1                 (0x20000000uL)
+#define INTC_ICDICFR27_TINT31_0                 (0x40000000uL)
+#define INTC_ICDICFR27_TINT31_1                 (0x80000000uL)
+
+#define INTC_ICDICFR28_TINT32_0                 (0x00000001uL)
+#define INTC_ICDICFR28_TINT32_1                 (0x00000002uL)
+#define INTC_ICDICFR28_TINT33_0                 (0x00000004uL)
+#define INTC_ICDICFR28_TINT33_1                 (0x00000008uL)
+#define INTC_ICDICFR28_TINT34_0                 (0x00000010uL)
+#define INTC_ICDICFR28_TINT34_1                 (0x00000020uL)
+#define INTC_ICDICFR28_TINT35_0                 (0x00000040uL)
+#define INTC_ICDICFR28_TINT35_1                 (0x00000080uL)
+#define INTC_ICDICFR28_TINT36_0                 (0x00000100uL)
+#define INTC_ICDICFR28_TINT36_1                 (0x00000200uL)
+#define INTC_ICDICFR28_TINT37_0                 (0x00000400uL)
+#define INTC_ICDICFR28_TINT37_1                 (0x00000800uL)
+#define INTC_ICDICFR28_TINT38_0                 (0x00001000uL)
+#define INTC_ICDICFR28_TINT38_1                 (0x00002000uL)
+#define INTC_ICDICFR28_TINT39_0                 (0x00004000uL)
+#define INTC_ICDICFR28_TINT39_1                 (0x00008000uL)
+#define INTC_ICDICFR28_TINT40_0                 (0x00010000uL)
+#define INTC_ICDICFR28_TINT40_1                 (0x00020000uL)
+#define INTC_ICDICFR28_TINT41_0                 (0x00040000uL)
+#define INTC_ICDICFR28_TINT41_1                 (0x00080000uL)
+#define INTC_ICDICFR28_TINT42_0                 (0x00100000uL)
+#define INTC_ICDICFR28_TINT42_1                 (0x00200000uL)
+#define INTC_ICDICFR28_TINT43_0                 (0x00400000uL)
+#define INTC_ICDICFR28_TINT43_1                 (0x00800000uL)
+#define INTC_ICDICFR28_TINT44_0                 (0x01000000uL)
+#define INTC_ICDICFR28_TINT44_1                 (0x02000000uL)
+#define INTC_ICDICFR28_TINT45_0                 (0x04000000uL)
+#define INTC_ICDICFR28_TINT45_1                 (0x08000000uL)
+#define INTC_ICDICFR28_TINT46_0                 (0x10000000uL)
+#define INTC_ICDICFR28_TINT46_1                 (0x20000000uL)
+#define INTC_ICDICFR28_TINT47_0                 (0x40000000uL)
+#define INTC_ICDICFR28_TINT47_1                 (0x80000000uL)
+
+#define INTC_ICDICFR29_TINT48_0                 (0x00000001uL)
+#define INTC_ICDICFR29_TINT48_1                 (0x00000002uL)
+#define INTC_ICDICFR29_TINT49_0                 (0x00000004uL)
+#define INTC_ICDICFR29_TINT49_1                 (0x00000008uL)
+#define INTC_ICDICFR29_TINT50_0                 (0x00000010uL)
+#define INTC_ICDICFR29_TINT50_1                 (0x00000020uL)
+#define INTC_ICDICFR29_TINT51_0                 (0x00000040uL)
+#define INTC_ICDICFR29_TINT51_1                 (0x00000080uL)
+#define INTC_ICDICFR29_TINT52_0                 (0x00000100uL)
+#define INTC_ICDICFR29_TINT52_1                 (0x00000200uL)
+#define INTC_ICDICFR29_TINT53_0                 (0x00000400uL)
+#define INTC_ICDICFR29_TINT53_1                 (0x00000800uL)
+#define INTC_ICDICFR29_TINT54_0                 (0x00001000uL)
+#define INTC_ICDICFR29_TINT54_1                 (0x00002000uL)
+#define INTC_ICDICFR29_TINT55_0                 (0x00004000uL)
+#define INTC_ICDICFR29_TINT55_1                 (0x00008000uL)
+#define INTC_ICDICFR29_TINT56_0                 (0x00010000uL)
+#define INTC_ICDICFR29_TINT56_1                 (0x00020000uL)
+#define INTC_ICDICFR29_TINT57_0                 (0x00040000uL)
+#define INTC_ICDICFR29_TINT57_1                 (0x00080000uL)
+#define INTC_ICDICFR29_TINT58_0                 (0x00100000uL)
+#define INTC_ICDICFR29_TINT58_1                 (0x00200000uL)
+#define INTC_ICDICFR29_TINT59_0                 (0x00400000uL)
+#define INTC_ICDICFR29_TINT59_1                 (0x00800000uL)
+#define INTC_ICDICFR29_TINT60_0                 (0x01000000uL)
+#define INTC_ICDICFR29_TINT60_1                 (0x02000000uL)
+#define INTC_ICDICFR29_TINT61_0                 (0x04000000uL)
+#define INTC_ICDICFR29_TINT61_1                 (0x08000000uL)
+#define INTC_ICDICFR29_TINT62_0                 (0x10000000uL)
+#define INTC_ICDICFR29_TINT62_1                 (0x20000000uL)
+#define INTC_ICDICFR29_TINT63_0                 (0x40000000uL)
+#define INTC_ICDICFR29_TINT63_1                 (0x80000000uL)
+
+#define INTC_ICDICFR30_TINT64_0                 (0x00000001uL)
+#define INTC_ICDICFR30_TINT64_1                 (0x00000002uL)
+#define INTC_ICDICFR30_TINT65_0                 (0x00000004uL)
+#define INTC_ICDICFR30_TINT65_1                 (0x00000008uL)
+#define INTC_ICDICFR30_TINT66_0                 (0x00000010uL)
+#define INTC_ICDICFR30_TINT66_1                 (0x00000020uL)
+#define INTC_ICDICFR30_TINT67_0                 (0x00000040uL)
+#define INTC_ICDICFR30_TINT67_1                 (0x00000080uL)
+#define INTC_ICDICFR30_TINT68_0                 (0x00000100uL)
+#define INTC_ICDICFR30_TINT68_1                 (0x00000200uL)
+#define INTC_ICDICFR30_TINT69_0                 (0x00000400uL)
+#define INTC_ICDICFR30_TINT69_1                 (0x00000800uL)
+#define INTC_ICDICFR30_TINT70_0                 (0x00001000uL)
+#define INTC_ICDICFR30_TINT70_1                 (0x00002000uL)
+#define INTC_ICDICFR30_TINT71_0                 (0x00004000uL)
+#define INTC_ICDICFR30_TINT71_1                 (0x00008000uL)
+#define INTC_ICDICFR30_TINT72_0                 (0x00010000uL)
+#define INTC_ICDICFR30_TINT72_1                 (0x00020000uL)
+#define INTC_ICDICFR30_TINT73_0                 (0x00040000uL)
+#define INTC_ICDICFR30_TINT73_1                 (0x00080000uL)
+#define INTC_ICDICFR30_TINT74_0                 (0x00100000uL)
+#define INTC_ICDICFR30_TINT74_1                 (0x00200000uL)
+#define INTC_ICDICFR30_TINT75_0                 (0x00400000uL)
+#define INTC_ICDICFR30_TINT75_1                 (0x00800000uL)
+#define INTC_ICDICFR30_TINT76_0                 (0x01000000uL)
+#define INTC_ICDICFR30_TINT76_1                 (0x02000000uL)
+#define INTC_ICDICFR30_TINT77_0                 (0x04000000uL)
+#define INTC_ICDICFR30_TINT77_1                 (0x08000000uL)
+#define INTC_ICDICFR30_TINT78_0                 (0x10000000uL)
+#define INTC_ICDICFR30_TINT78_1                 (0x20000000uL)
+#define INTC_ICDICFR30_TINT79_0                 (0x40000000uL)
+#define INTC_ICDICFR30_TINT79_1                 (0x80000000uL)
+
+#define INTC_ICDICFR31_TINT80_0                 (0x00000001uL)
+#define INTC_ICDICFR31_TINT80_1                 (0x00000002uL)
+#define INTC_ICDICFR31_TINT81_0                 (0x00000004uL)
+#define INTC_ICDICFR31_TINT81_1                 (0x00000008uL)
+#define INTC_ICDICFR31_TINT82_0                 (0x00000010uL)
+#define INTC_ICDICFR31_TINT82_1                 (0x00000020uL)
+#define INTC_ICDICFR31_TINT83_0                 (0x00000040uL)
+#define INTC_ICDICFR31_TINT83_1                 (0x00000080uL)
+#define INTC_ICDICFR31_TINT84_0                 (0x00000100uL)
+#define INTC_ICDICFR31_TINT84_1                 (0x00000200uL)
+#define INTC_ICDICFR31_TINT85_0                 (0x00000400uL)
+#define INTC_ICDICFR31_TINT85_1                 (0x00000800uL)
+#define INTC_ICDICFR31_TINT86_0                 (0x00001000uL)
+#define INTC_ICDICFR31_TINT86_1                 (0x00002000uL)
+#define INTC_ICDICFR31_TINT87_0                 (0x00004000uL)
+#define INTC_ICDICFR31_TINT87_1                 (0x00008000uL)
+#define INTC_ICDICFR31_TINT88_0                 (0x00010000uL)
+#define INTC_ICDICFR31_TINT88_1                 (0x00020000uL)
+#define INTC_ICDICFR31_TINT89_0                 (0x00040000uL)
+#define INTC_ICDICFR31_TINT89_1                 (0x00080000uL)
+#define INTC_ICDICFR31_TINT90_0                 (0x00100000uL)
+#define INTC_ICDICFR31_TINT90_1                 (0x00200000uL)
+#define INTC_ICDICFR31_TINT91_0                 (0x00400000uL)
+#define INTC_ICDICFR31_TINT91_1                 (0x00800000uL)
+#define INTC_ICDICFR31_TINT92_0                 (0x01000000uL)
+#define INTC_ICDICFR31_TINT92_1                 (0x02000000uL)
+#define INTC_ICDICFR31_TINT93_0                 (0x04000000uL)
+#define INTC_ICDICFR31_TINT93_1                 (0x08000000uL)
+#define INTC_ICDICFR31_TINT94_0                 (0x10000000uL)
+#define INTC_ICDICFR31_TINT94_1                 (0x20000000uL)
+#define INTC_ICDICFR31_TINT95_0                 (0x40000000uL)
+#define INTC_ICDICFR31_TINT95_1                 (0x80000000uL)
+
+#define INTC_ICDICFR32_TINT96_0                 (0x00000001uL)
+#define INTC_ICDICFR32_TINT96_1                 (0x00000002uL)
+#define INTC_ICDICFR32_TINT97_0                 (0x00000004uL)
+#define INTC_ICDICFR32_TINT97_1                 (0x00000008uL)
+#define INTC_ICDICFR32_TINT98_0                 (0x00000010uL)
+#define INTC_ICDICFR32_TINT98_1                 (0x00000020uL)
+#define INTC_ICDICFR32_TINT99_0                 (0x00000040uL)
+#define INTC_ICDICFR32_TINT99_1                 (0x00000080uL)
+#define INTC_ICDICFR32_TINT100_0                (0x00000100uL)
+#define INTC_ICDICFR32_TINT100_1                (0x00000200uL)
+#define INTC_ICDICFR32_TINT101_0                (0x00000400uL)
+#define INTC_ICDICFR32_TINT101_1                (0x00000800uL)
+#define INTC_ICDICFR32_TINT102_0                (0x00001000uL)
+#define INTC_ICDICFR32_TINT102_1                (0x00002000uL)
+#define INTC_ICDICFR32_TINT103_0                (0x00004000uL)
+#define INTC_ICDICFR32_TINT103_1                (0x00008000uL)
+#define INTC_ICDICFR32_TINT104_0                (0x00010000uL)
+#define INTC_ICDICFR32_TINT104_1                (0x00020000uL)
+#define INTC_ICDICFR32_TINT105_0                (0x00040000uL)
+#define INTC_ICDICFR32_TINT105_1                (0x00080000uL)
+#define INTC_ICDICFR32_TINT106_0                (0x00100000uL)
+#define INTC_ICDICFR32_TINT106_1                (0x00200000uL)
+#define INTC_ICDICFR32_TINT107_0                (0x00400000uL)
+#define INTC_ICDICFR32_TINT107_1                (0x00800000uL)
+#define INTC_ICDICFR32_TINT108_0                (0x01000000uL)
+#define INTC_ICDICFR32_TINT108_1                (0x02000000uL)
+#define INTC_ICDICFR32_TINT109_0                (0x04000000uL)
+#define INTC_ICDICFR32_TINT109_1                (0x08000000uL)
+#define INTC_ICDICFR32_TINT110_0                (0x10000000uL)
+#define INTC_ICDICFR32_TINT110_1                (0x20000000uL)
+#define INTC_ICDICFR32_TINT111_0                (0x40000000uL)
+#define INTC_ICDICFR32_TINT111_1                (0x80000000uL)
+
+#define INTC_ICDICFR33_TINT112_0                (0x00000001uL)
+#define INTC_ICDICFR33_TINT112_1                (0x00000002uL)
+#define INTC_ICDICFR33_TINT113_0                (0x00000004uL)
+#define INTC_ICDICFR33_TINT113_1                (0x00000008uL)
+#define INTC_ICDICFR33_TINT114_0                (0x00000010uL)
+#define INTC_ICDICFR33_TINT114_1                (0x00000020uL)
+#define INTC_ICDICFR33_TINT115_0                (0x00000040uL)
+#define INTC_ICDICFR33_TINT115_1                (0x00000080uL)
+#define INTC_ICDICFR33_TINT116_0                (0x00000100uL)
+#define INTC_ICDICFR33_TINT116_1                (0x00000200uL)
+#define INTC_ICDICFR33_TINT117_0                (0x00000400uL)
+#define INTC_ICDICFR33_TINT117_1                (0x00000800uL)
+#define INTC_ICDICFR33_TINT118_0                (0x00001000uL)
+#define INTC_ICDICFR33_TINT118_1                (0x00002000uL)
+#define INTC_ICDICFR33_TINT119_0                (0x00004000uL)
+#define INTC_ICDICFR33_TINT119_1                (0x00008000uL)
+#define INTC_ICDICFR33_TINT120_0                (0x00010000uL)
+#define INTC_ICDICFR33_TINT120_1                (0x00020000uL)
+#define INTC_ICDICFR33_TINT121_0                (0x00040000uL)
+#define INTC_ICDICFR33_TINT121_1                (0x00080000uL)
+#define INTC_ICDICFR33_TINT122_0                (0x00100000uL)
+#define INTC_ICDICFR33_TINT122_1                (0x00200000uL)
+#define INTC_ICDICFR33_TINT123_0                (0x00400000uL)
+#define INTC_ICDICFR33_TINT123_1                (0x00800000uL)
+#define INTC_ICDICFR33_TINT124_0                (0x01000000uL)
+#define INTC_ICDICFR33_TINT124_1                (0x02000000uL)
+#define INTC_ICDICFR33_TINT125_0                (0x04000000uL)
+#define INTC_ICDICFR33_TINT125_1                (0x08000000uL)
+#define INTC_ICDICFR33_TINT126_0                (0x10000000uL)
+#define INTC_ICDICFR33_TINT126_1                (0x20000000uL)
+#define INTC_ICDICFR33_TINT127_0                (0x40000000uL)
+#define INTC_ICDICFR33_TINT127_1                (0x80000000uL)
+
+#define INTC_ICDICFR34_TINT128_0                (0x00000001uL)
+#define INTC_ICDICFR34_TINT128_1                (0x00000002uL)
+#define INTC_ICDICFR34_TINT129_0                (0x00000004uL)
+#define INTC_ICDICFR34_TINT129_1                (0x00000008uL)
+#define INTC_ICDICFR34_TINT130_0                (0x00000010uL)
+#define INTC_ICDICFR34_TINT130_1                (0x00000020uL)
+#define INTC_ICDICFR34_TINT131_0                (0x00000040uL)
+#define INTC_ICDICFR34_TINT131_1                (0x00000080uL)
+#define INTC_ICDICFR34_TINT132_0                (0x00000100uL)
+#define INTC_ICDICFR34_TINT132_1                (0x00000200uL)
+#define INTC_ICDICFR34_TINT133_0                (0x00000400uL)
+#define INTC_ICDICFR34_TINT133_1                (0x00000800uL)
+#define INTC_ICDICFR34_TINT134_0                (0x00001000uL)
+#define INTC_ICDICFR34_TINT134_1                (0x00002000uL)
+#define INTC_ICDICFR34_TINT135_0                (0x00004000uL)
+#define INTC_ICDICFR34_TINT135_1                (0x00008000uL)
+#define INTC_ICDICFR34_TINT136_0                (0x00010000uL)
+#define INTC_ICDICFR34_TINT136_1                (0x00020000uL)
+#define INTC_ICDICFR34_TINT137_0                (0x00040000uL)
+#define INTC_ICDICFR34_TINT137_1                (0x00080000uL)
+#define INTC_ICDICFR34_TINT138_0                (0x00100000uL)
+#define INTC_ICDICFR34_TINT138_1                (0x00200000uL)
+#define INTC_ICDICFR34_TINT139_0                (0x00400000uL)
+#define INTC_ICDICFR34_TINT139_1                (0x00800000uL)
+#define INTC_ICDICFR34_TINT140_0                (0x01000000uL)
+#define INTC_ICDICFR34_TINT140_1                (0x02000000uL)
+#define INTC_ICDICFR34_TINT141_0                (0x04000000uL)
+#define INTC_ICDICFR34_TINT141_1                (0x08000000uL)
+#define INTC_ICDICFR34_TINT142_0                (0x10000000uL)
+#define INTC_ICDICFR34_TINT142_1                (0x20000000uL)
+#define INTC_ICDICFR34_TINT143_0                (0x40000000uL)
+#define INTC_ICDICFR34_TINT143_1                (0x80000000uL)
+
+#define INTC_ICDICFR35_TINT144_0                (0x00000001uL)
+#define INTC_ICDICFR35_TINT144_1                (0x00000002uL)
+#define INTC_ICDICFR35_TINT145_0                (0x00000004uL)
+#define INTC_ICDICFR35_TINT145_1                (0x00000008uL)
+#define INTC_ICDICFR35_TINT146_0                (0x00000010uL)
+#define INTC_ICDICFR35_TINT146_1                (0x00000020uL)
+#define INTC_ICDICFR35_TINT147_0                (0x00000040uL)
+#define INTC_ICDICFR35_TINT147_1                (0x00000080uL)
+#define INTC_ICDICFR35_TINT148_0                (0x00000100uL)
+#define INTC_ICDICFR35_TINT148_1                (0x00000200uL)
+#define INTC_ICDICFR35_TINT149_0                (0x00000400uL)
+#define INTC_ICDICFR35_TINT149_1                (0x00000800uL)
+#define INTC_ICDICFR35_TINT150_0                (0x00001000uL)
+#define INTC_ICDICFR35_TINT150_1                (0x00002000uL)
+#define INTC_ICDICFR35_TINT151_0                (0x00004000uL)
+#define INTC_ICDICFR35_TINT151_1                (0x00008000uL)
+#define INTC_ICDICFR35_TINT152_0                (0x00010000uL)
+#define INTC_ICDICFR35_TINT152_1                (0x00020000uL)
+#define INTC_ICDICFR35_TINT153_0                (0x00040000uL)
+#define INTC_ICDICFR35_TINT153_1                (0x00080000uL)
+#define INTC_ICDICFR35_TINT154_0                (0x00100000uL)
+#define INTC_ICDICFR35_TINT154_1                (0x00200000uL)
+#define INTC_ICDICFR35_TINT155_0                (0x00400000uL)
+#define INTC_ICDICFR35_TINT155_1                (0x00800000uL)
+#define INTC_ICDICFR35_TINT156_0                (0x01000000uL)
+#define INTC_ICDICFR35_TINT156_1                (0x02000000uL)
+#define INTC_ICDICFR35_TINT157_0                (0x04000000uL)
+#define INTC_ICDICFR35_TINT157_1                (0x08000000uL)
+#define INTC_ICDICFR35_TINT158_0                (0x10000000uL)
+#define INTC_ICDICFR35_TINT158_1                (0x20000000uL)
+#define INTC_ICDICFR35_TINT159_0                (0x40000000uL)
+#define INTC_ICDICFR35_TINT159_1                (0x80000000uL)
+
+#define INTC_ICDICFR36_TINT160_0                (0x00000001uL)
+#define INTC_ICDICFR36_TINT160_1                (0x00000002uL)
+#define INTC_ICDICFR36_TINT161_0                (0x00000004uL)
+#define INTC_ICDICFR36_TINT161_1                (0x00000008uL)
+#define INTC_ICDICFR36_TINT162_0                (0x00000010uL)
+#define INTC_ICDICFR36_TINT162_1                (0x00000020uL)
+#define INTC_ICDICFR36_TINT163_0                (0x00000040uL)
+#define INTC_ICDICFR36_TINT163_1                (0x00000080uL)
+#define INTC_ICDICFR36_TINT164_0                (0x00000100uL)
+#define INTC_ICDICFR36_TINT164_1                (0x00000200uL)
+#define INTC_ICDICFR36_TINT165_0                (0x00000400uL)
+#define INTC_ICDICFR36_TINT165_1                (0x00000800uL)
+#define INTC_ICDICFR36_TINT166_0                (0x00001000uL)
+#define INTC_ICDICFR36_TINT166_1                (0x00002000uL)
+#define INTC_ICDICFR36_TINT167_0                (0x00004000uL)
+#define INTC_ICDICFR36_TINT167_1                (0x00008000uL)
+#define INTC_ICDICFR36_TINT168_0                (0x00010000uL)
+#define INTC_ICDICFR36_TINT168_1                (0x00020000uL)
+#define INTC_ICDICFR36_TINT169_0                (0x00040000uL)
+#define INTC_ICDICFR36_TINT169_1                (0x00080000uL)
+#define INTC_ICDICFR36_TINT170_0                (0x00100000uL)
+#define INTC_ICDICFR36_TINT170_1                (0x00200000uL)
+
+#define INTC_ICDSGIR_SGIINTID                   (0x0000000FuL)
+#define INTC_ICDSGIR_SATT                       (0x00008000uL)
+#define INTC_ICDSGIR_CPUTargetList              (0x00FF0000uL)
+#define INTC_ICDSGIR_TargetListFilter           (0x03000000uL)
+
+#define INTC_ICCICR_EnableS                     (0x00000001uL)
+#define INTC_ICCICR_EnableNS                    (0x00000002uL)
+#define INTC_ICCICR_AckCtl                      (0x00000004uL)
+#define INTC_ICCICR_FIQEn                       (0x00000008uL)
+#define INTC_ICCICR_SBPR                        (0x00000010uL)
+
+#define INTC_ICCPMR_Priority                    (0x000000FFuL)
+
+#define INTC_ICCBPR_Binarypoint                 (0x00000007uL)
+
+#define INTC_ICCIAR_ACKINTID                    (0x000003FFuL)
+#define INTC_ICCIAR_CPUID                       (0x00001C00uL)
+
+#define INTC_ICCEOIR_EOIINTID                   (0x000003FFuL)
+#define INTC_ICCEOIR_CPUID                      (0x00001C00uL)
+
+#define INTC_ICCRPR_Priority                    (0x000000FFuL)
+
+#define INTC_ICCHPIR_PENDINTID                  (0x000003FFuL)
+#define INTC_ICCHPIR_CPUID                      (0x00001C00uL)
+
+#define INTC_ICCABPR_Binarypoint                (0x00000007uL)
+
+#define INTC_ICCIIDR_Implementer                (0x00000FFFuL)
+#define INTC_ICCIIDR_Revision                   (0x0000F000uL)
+#define INTC_ICCIIDR_Architecture_version       (0x000F0000uL)
+#define INTC_ICCIIDR_ProductID                  (0xFFF00000uL)
+
+#define INTC_ICR0_NMIF                          (0x0002u)
+#define INTC_ICR0_NMIE                          (0x0100u)
+#define INTC_ICR0_NMIL                          (0x8000u)
+
+#define INTC_ICR1_IRQ00S                        (0x0001u)
+#define INTC_ICR1_IRQ01S                        (0x0002u)
+#define INTC_ICR1_IRQ10S                        (0x0004u)
+#define INTC_ICR1_IRQ11S                        (0x0008u)
+#define INTC_ICR1_IRQ20S                        (0x0010u)
+#define INTC_ICR1_IRQ21S                        (0x0020u)
+#define INTC_ICR1_IRQ30S                        (0x0040u)
+#define INTC_ICR1_IRQ31S                        (0x0080u)
+#define INTC_ICR1_IRQ40S                        (0x0100u)
+#define INTC_ICR1_IRQ41S                        (0x0200u)
+#define INTC_ICR1_IRQ50S                        (0x0400u)
+#define INTC_ICR1_IRQ51S                        (0x0800u)
+#define INTC_ICR1_IRQ60S                        (0x1000u)
+#define INTC_ICR1_IRQ61S                        (0x2000u)
+#define INTC_ICR1_IRQ70S                        (0x4000u)
+#define INTC_ICR1_IRQ71S                        (0x8000u)
+
+#define INTC_IRQRR_IRQ0F                        (0x0001u)
+#define INTC_IRQRR_IRQ1F                        (0x0002u)
+#define INTC_IRQRR_IRQ2F                        (0x0004u)
+#define INTC_IRQRR_IRQ3F                        (0x0008u)
+#define INTC_IRQRR_IRQ4F                        (0x0010u)
+#define INTC_IRQRR_IRQ5F                        (0x0020u)
+#define INTC_IRQRR_IRQ6F                        (0x0040u)
+#define INTC_IRQRR_IRQ7F                        (0x0080u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define INTC_ICDDCR_Enable_SHIFT                (0u)
+
+#define INTC_ICDICTR_ITLinesNumber_SHIFT        (0u)
+#define INTC_ICDICTR_CPUNumber_SHIFT            (5u)
+#define INTC_ICDICTR_SecurityExtn_SHIFT         (10u)
+#define INTC_ICDICTR_LSPI_SHIFT                 (11u)
+
+#define INTC_ICDIIDR_Implementer_SHIFT          (0u)
+#define INTC_ICDIIDR_Revision_SHIFT             (12u)
+#define INTC_ICDIIDR_Variant_SHIFT              (16u)
+#define INTC_ICDIIDR_ProductID_SHIFT            (24u)
+
+#define INTC_ICDISR0_SW0_SHIFT                  (0u)
+#define INTC_ICDISR0_SW1_SHIFT                  (1u)
+#define INTC_ICDISR0_SW2_SHIFT                  (2u)
+#define INTC_ICDISR0_SW3_SHIFT                  (3u)
+#define INTC_ICDISR0_SW4_SHIFT                  (4u)
+#define INTC_ICDISR0_SW5_SHIFT                  (5u)
+#define INTC_ICDISR0_SW6_SHIFT                  (6u)
+#define INTC_ICDISR0_SW7_SHIFT                  (7u)
+#define INTC_ICDISR0_SW8_SHIFT                  (8u)
+#define INTC_ICDISR0_SW9_SHIFT                  (9u)
+#define INTC_ICDISR0_SW10_SHIFT                 (10u)
+#define INTC_ICDISR0_SW11_SHIFT                 (11u)
+#define INTC_ICDISR0_SW12_SHIFT                 (12u)
+#define INTC_ICDISR0_SW13_SHIFT                 (13u)
+#define INTC_ICDISR0_SW14_SHIFT                 (14u)
+#define INTC_ICDISR0_SW15_SHIFT                 (15u)
+#define INTC_ICDISR0_PMUIRQ0_SHIFT              (16u)
+#define INTC_ICDISR0_COMMRX0_SHIFT              (17u)
+#define INTC_ICDISR0_COMMTX0_SHIFT              (18u)
+#define INTC_ICDISR0_CTIIRQ0_SHIFT              (19u)
+
+#define INTC_ICDISR1_IRQ0_SHIFT                 (0u)
+#define INTC_ICDISR1_IRQ1_SHIFT                 (1u)
+#define INTC_ICDISR1_IRQ2_SHIFT                 (2u)
+#define INTC_ICDISR1_IRQ3_SHIFT                 (3u)
+#define INTC_ICDISR1_IRQ4_SHIFT                 (4u)
+#define INTC_ICDISR1_IRQ5_SHIFT                 (5u)
+#define INTC_ICDISR1_IRQ6_SHIFT                 (6u)
+#define INTC_ICDISR1_IRQ7_SHIFT                 (7u)
+#define INTC_ICDISR1_PL310ERR_SHIFT             (8u)
+#define INTC_ICDISR1_DMAINT0_SHIFT              (9u)
+#define INTC_ICDISR1_DMAINT1_SHIFT              (10u)
+#define INTC_ICDISR1_DMAINT2_SHIFT              (11u)
+#define INTC_ICDISR1_DMAINT3_SHIFT              (12u)
+#define INTC_ICDISR1_DMAINT4_SHIFT              (13u)
+#define INTC_ICDISR1_DMAINT5_SHIFT              (14u)
+#define INTC_ICDISR1_DMAINT6_SHIFT              (15u)
+#define INTC_ICDISR1_DMAINT7_SHIFT              (16u)
+#define INTC_ICDISR1_DMAINT8_SHIFT              (17u)
+#define INTC_ICDISR1_DMAINT9_SHIFT              (18u)
+#define INTC_ICDISR1_DMAINT10_SHIFT             (19u)
+#define INTC_ICDISR1_DMAINT11_SHIFT             (20u)
+#define INTC_ICDISR1_DMAINT12_SHIFT             (21u)
+#define INTC_ICDISR1_DMAINT13_SHIFT             (22u)
+#define INTC_ICDISR1_DMAINT14_SHIFT             (23u)
+#define INTC_ICDISR1_DMAINT15_SHIFT             (24u)
+#define INTC_ICDISR1_DMAERR_SHIFT               (25u)
+
+#define INTC_ICDISR2_USBI0_SHIFT                (9u)
+#define INTC_ICDISR2_USBI1_SHIFT                (10u)
+#define INTC_ICDISR2_S0_VI_VSYNC0_SHIFT         (11u)
+#define INTC_ICDISR2_S0_LO_VSYNC0_SHIFT         (12u)
+#define INTC_ICDISR2_S0_VSYNCERR0_SHIFT         (13u)
+#define INTC_ICDISR2_GR3_VLINE0_SHIFT           (14u)
+#define INTC_ICDISR2_S0_VFIELD0_SHIFT           (15u)
+#define INTC_ICDISR2_IV1_VBUFERR0_SHIFT         (16u)
+#define INTC_ICDISR2_IV3_VBUFERR0_SHIFT         (17u)
+#define INTC_ICDISR2_IV5_VBUFERR0_SHIFT         (18u)
+#define INTC_ICDISR2_IV6_VBUFERR0_SHIFT         (19u)
+#define INTC_ICDISR2_S0_WLINE0_SHIFT            (20u)
+#define INTC_ICDISR2_S1_VI_VSYNC0_SHIFT         (21u)
+#define INTC_ICDISR2_S1_LO_VSYNC0_SHIFT         (22u)
+#define INTC_ICDISR2_S1_VSYNCERR0_SHIFT         (23u)
+#define INTC_ICDISR2_S1_VFIELD0_SHIFT           (24u)
+#define INTC_ICDISR2_IV2_VBUFERR0_SHIFT         (25u)
+#define INTC_ICDISR2_IV4_VBUFERR0_SHIFT         (26u)
+#define INTC_ICDISR2_S1_WLINE0_SHIFT            (27u)
+#define INTC_ICDISR2_OIR_VI_VSYNC0_SHIFT        (28u)
+#define INTC_ICDISR2_OIR_LO_VSYNC0_SHIFT        (29u)
+#define INTC_ICDISR2_OIR_VSYNCERR0_SHIFT        (30u)
+#define INTC_ICDISR2_OIR_VFIELD0_SHIFT          (31u)
+
+#define INTC_ICDISR3_IV7_VBUFERR0_SHIFT         (0u)
+#define INTC_ICDISR3_IV8_VBUFERR0_SHIFT         (1u)
+#define INTC_ICDISR3_S0_VI_VSYNC1_SHIFT         (3u)
+#define INTC_ICDISR3_S0_LO_VSYNC1_SHIFT         (4u)
+#define INTC_ICDISR3_S0_VSYNCERR1_SHIFT         (5u)
+#define INTC_ICDISR3_GR3_VLINE1_SHIFT           (6u)
+#define INTC_ICDISR3_S0_VFIELD1_SHIFT           (7u)
+#define INTC_ICDISR3_IV1_VBUFERR1_SHIFT         (8u)
+#define INTC_ICDISR3_IV3_VBUFERR1_SHIFT         (9u)
+#define INTC_ICDISR3_IV5_VBUFERR1_SHIFT         (10u)
+#define INTC_ICDISR3_IV6_VBUFERR1_SHIFT         (11u)
+#define INTC_ICDISR3_S0_WLINE1_SHIFT            (12u)
+#define INTC_ICDISR3_S1_VI_VSYNC1_SHIFT         (13u)
+#define INTC_ICDISR3_S1_LO_VSYNC1_SHIFT         (14u)
+#define INTC_ICDISR3_S1_VSYNCERR1_SHIFT         (15u)
+#define INTC_ICDISR3_S1_VFIELD1_SHIFT           (16u)
+#define INTC_ICDISR3_IV2_VBUFERR1_SHIFT         (17u)
+#define INTC_ICDISR3_IV4_VBUFERR1_SHIFT         (18u)
+#define INTC_ICDISR3_S1_WLINE1_SHIFT            (19u)
+#define INTC_ICDISR3_OIR_VI_VSYNC1_SHIFT        (20u)
+#define INTC_ICDISR3_OIR_LO_VSYNC1_SHIFT        (21u)
+#define INTC_ICDISR3_OIR_VLINE1_SHIFT           (22u)
+#define INTC_ICDISR3_OIR_VFIELD1_SHIFT          (23u)
+#define INTC_ICDISR3_IV7_VBUFERR1_SHIFT         (24u)
+#define INTC_ICDISR3_IV8_VBUFERR1_SHIFT         (25u)
+#define INTC_ICDISR3_IMRDI_SHIFT                (27u)
+#define INTC_ICDISR3_IMR2I0_SHIFT               (28u)
+#define INTC_ICDISR3_IMR2I1_SHIFT               (29u)
+#define INTC_ICDISR3_JEDI_SHIFT                 (30u)
+#define INTC_ICDISR3_JDTI_SHIFT                 (31u)
+
+#define INTC_ICDISR4_CMP0_SHIFT                 (0u)
+#define INTC_ICDISR4_CMP1_SHIFT                 (1u)
+#define INTC_ICDISR4_INT0_SHIFT                 (2u)
+#define INTC_ICDISR4_INT1_SHIFT                 (3u)
+#define INTC_ICDISR4_INT2_SHIFT                 (4u)
+#define INTC_ICDISR4_INT3_SHIFT                 (5u)
+#define INTC_ICDISR4_OSTM0TINT_SHIFT            (6u)
+#define INTC_ICDISR4_OSTM1TINT_SHIFT            (7u)
+#define INTC_ICDISR4_CMI_SHIFT                  (8u)
+#define INTC_ICDISR4_WTOUT_SHIFT                (9u)
+#define INTC_ICDISR4_ITI_SHIFT                  (10u)
+#define INTC_ICDISR4_TGI0A_SHIFT                (11u)
+#define INTC_ICDISR4_TGI0B_SHIFT                (12u)
+#define INTC_ICDISR4_TGI0C_SHIFT                (13u)
+#define INTC_ICDISR4_TGI0D_SHIFT                (14u)
+#define INTC_ICDISR4_TGI0V_SHIFT                (15u)
+#define INTC_ICDISR4_TGI0E_SHIFT                (16u)
+#define INTC_ICDISR4_TGI0F_SHIFT                (17u)
+#define INTC_ICDISR4_TGI1A_SHIFT                (18u)
+#define INTC_ICDISR4_TGI1B_SHIFT                (19u)
+#define INTC_ICDISR4_TGI1V_SHIFT                (20u)
+#define INTC_ICDISR4_TGI1U_SHIFT                (21u)
+#define INTC_ICDISR4_TGI2A_SHIFT                (22u)
+#define INTC_ICDISR4_TGI2B_SHIFT                (23u)
+#define INTC_ICDISR4_TGI2V_SHIFT                (24u)
+#define INTC_ICDISR4_TGI2U_SHIFT                (25u)
+#define INTC_ICDISR4_TGI3A_SHIFT                (26u)
+#define INTC_ICDISR4_TGI3B_SHIFT                (27u)
+#define INTC_ICDISR4_TGI3C_SHIFT                (28u)
+#define INTC_ICDISR4_TGI3D_SHIFT                (29u)
+#define INTC_ICDISR4_TGI3V_SHIFT                (30u)
+#define INTC_ICDISR4_TGI4A_SHIFT                (31u)
+
+#define INTC_ICDISR5_TGI4B_SHIFT                (0u)
+#define INTC_ICDISR5_TGI4C_SHIFT                (1u)
+#define INTC_ICDISR5_TGI4D_SHIFT                (2u)
+#define INTC_ICDISR5_TGI4V_SHIFT                (3u)
+#define INTC_ICDISR5_CMI1_SHIFT                 (4u)
+#define INTC_ICDISR5_CMI2_SHIFT                 (5u)
+#define INTC_ICDISR5_SGDEI0_SHIFT               (6u)
+#define INTC_ICDISR5_SGDEI1_SHIFT               (7u)
+#define INTC_ICDISR5_SGDEI2_SHIFT               (8u)
+#define INTC_ICDISR5_SGDEI3_SHIFT               (9u)
+#define INTC_ICDISR5_ADI_SHIFT                  (10u)
+#define INTC_ICDISR5_LMTI_SHIFT                 (11u)
+#define INTC_ICDISR5_SSII0_SHIFT                (12u)
+#define INTC_ICDISR5_SSIRXI0_SHIFT              (13u)
+#define INTC_ICDISR5_SSITXI0_SHIFT              (14u)
+#define INTC_ICDISR5_SSII1_SHIFT                (15u)
+#define INTC_ICDISR5_SSIRXI1_SHIFT              (16u)
+#define INTC_ICDISR5_SSITXI1_SHIFT              (17u)
+#define INTC_ICDISR5_SSII2_SHIFT                (18u)
+#define INTC_ICDISR5_SSIRTI2_SHIFT              (19u)
+#define INTC_ICDISR5_SSII3_SHIFT                (20u)
+#define INTC_ICDISR5_SSIRXI3_SHIFT              (21u)
+#define INTC_ICDISR5_SSITXI3_SHIFT              (22u)
+#define INTC_ICDISR5_SSII4_SHIFT                (23u)
+#define INTC_ICDISR5_SSIRTI4_SHIFT              (24u)
+#define INTC_ICDISR5_SSII5_SHIFT                (25u)
+#define INTC_ICDISR5_SSIRXI5_SHIFT              (26u)
+#define INTC_ICDISR5_SSITXI5_SHIFT              (27u)
+#define INTC_ICDISR5_SPDIFI_SHIFT               (28u)
+#define INTC_ICDISR5_INTIICTEI0_SHIFT           (29u)
+#define INTC_ICDISR5_INTIICRI0_SHIFT            (30u)
+#define INTC_ICDISR5_INTIICTI0_SHIFT            (31u)
+
+#define INTC_ICDISR6_INTIICSPI0_SHIFT           (0u)
+#define INTC_ICDISR6_INTIICSTI0_SHIFT           (1u)
+#define INTC_ICDISR6_INTIICNAKI0_SHIFT          (2u)
+#define INTC_ICDISR6_INTIICALI0_SHIFT           (3u)
+#define INTC_ICDISR6_INTIICTMOI0_SHIFT          (4u)
+#define INTC_ICDISR6_INTIICTEI1_SHIFT           (5u)
+#define INTC_ICDISR6_INTIICRI1_SHIFT            (6u)
+#define INTC_ICDISR6_INTIICTI1_SHIFT            (7u)
+#define INTC_ICDISR6_INTIICSPI1_SHIFT           (8u)
+#define INTC_ICDISR6_INTIICSTI1_SHIFT           (9u)
+#define INTC_ICDISR6_INTIICNAKI1_SHIFT          (10u)
+#define INTC_ICDISR6_INTIICALI1_SHIFT           (11u)
+#define INTC_ICDISR6_INTIICTMOI1_SHIFT          (12u)
+#define INTC_ICDISR6_INTIICTEI2_SHIFT           (13u)
+#define INTC_ICDISR6_INTIICRI2_SHIFT            (14u)
+#define INTC_ICDISR6_INTIICTI2_SHIFT            (15u)
+#define INTC_ICDISR6_INTIICSPI2_SHIFT           (16u)
+#define INTC_ICDISR6_INTIICSTI2_SHIFT           (17u)
+#define INTC_ICDISR6_INTIICNAKI2_SHIFT          (18u)
+#define INTC_ICDISR6_INTIICALI2_SHIFT           (19u)
+#define INTC_ICDISR6_INTIICTMOI2_SHIFT          (20u)
+#define INTC_ICDISR6_INTIICTEI3_SHIFT           (21u)
+#define INTC_ICDISR6_INTIICRI3_SHIFT            (22u)
+#define INTC_ICDISR6_INTIICTI3_SHIFT            (23u)
+#define INTC_ICDISR6_INTIICSPI3_SHIFT           (24u)
+#define INTC_ICDISR6_INTIICSTI3_SHIFT           (25u)
+#define INTC_ICDISR6_INTIICNAKI3_SHIFT          (26u)
+#define INTC_ICDISR6_INTIICALI3_SHIFT           (27u)
+#define INTC_ICDISR6_INTIICTMOI3_SHIFT          (28u)
+#define INTC_ICDISR6_BRI0_SHIFT                 (29u)
+#define INTC_ICDISR6_ERI0_SHIFT                 (30u)
+#define INTC_ICDISR6_RXI0_SHIFT                 (31u)
+
+#define INTC_ICDISR7_TXI0_SHIFT                 (0u)
+#define INTC_ICDISR7_BRI1_SHIFT                 (1u)
+#define INTC_ICDISR7_ERI1_SHIFT                 (2u)
+#define INTC_ICDISR7_RXI1_SHIFT                 (3u)
+#define INTC_ICDISR7_TXI1_SHIFT                 (4u)
+#define INTC_ICDISR7_BRI2_SHIFT                 (5u)
+#define INTC_ICDISR7_ERI2_SHIFT                 (6u)
+#define INTC_ICDISR7_RXI2_SHIFT                 (7u)
+#define INTC_ICDISR7_TXI2_SHIFT                 (8u)
+#define INTC_ICDISR7_BRI3_SHIFT                 (9u)
+#define INTC_ICDISR7_ERI3_SHIFT                 (10u)
+#define INTC_ICDISR7_RXI3_SHIFT                 (11u)
+#define INTC_ICDISR7_TXI3_SHIFT                 (12u)
+#define INTC_ICDISR7_BRI4_SHIFT                 (13u)
+#define INTC_ICDISR7_ERI4_SHIFT                 (14u)
+#define INTC_ICDISR7_RXI4_SHIFT                 (15u)
+#define INTC_ICDISR7_TXI4_SHIFT                 (16u)
+#define INTC_ICDISR7_BRI5_SHIFT                 (17u)
+#define INTC_ICDISR7_ERI5_SHIFT                 (18u)
+#define INTC_ICDISR7_RXI5_SHIFT                 (19u)
+#define INTC_ICDISR7_TXI5_SHIFT                 (20u)
+#define INTC_ICDISR7_BRI6_SHIFT                 (21u)
+#define INTC_ICDISR7_ERI6_SHIFT                 (22u)
+#define INTC_ICDISR7_RXI6_SHIFT                 (23u)
+#define INTC_ICDISR7_TXI6_SHIFT                 (24u)
+#define INTC_ICDISR7_BRI7_SHIFT                 (25u)
+#define INTC_ICDISR7_ERI7_SHIFT                 (26u)
+#define INTC_ICDISR7_RXI7_SHIFT                 (27u)
+#define INTC_ICDISR7_TXI7_SHIFT                 (28u)
+#define INTC_ICDISR7_INTRCANGERR_SHIFT          (29u)
+#define INTC_ICDISR7_INTRCANGRECC_SHIFT         (30u)
+#define INTC_ICDISR7_INTRCAN0REC_SHIFT          (31u)
+
+#define INTC_ICDISR8_INTRCAN0ERR_SHIFT          (0u)
+#define INTC_ICDISR8_INTRCAN0TRX_SHIFT          (1u)
+#define INTC_ICDISR8_INTRCAN1REC_SHIFT          (2u)
+#define INTC_ICDISR8_INTRCAN1ERR_SHIFT          (3u)
+#define INTC_ICDISR8_INTRCAN1TRX_SHIFT          (4u)
+#define INTC_ICDISR8_INTRCAN2REC_SHIFT          (5u)
+#define INTC_ICDISR8_INTRCAN2ERR_SHIFT          (6u)
+#define INTC_ICDISR8_INTRCAN2TRX_SHIFT          (7u)
+#define INTC_ICDISR8_INTRCAN3REC_SHIFT          (8u)
+#define INTC_ICDISR8_INTRCAN3ERR_SHIFT          (9u)
+#define INTC_ICDISR8_INTRCAN3TRX_SHIFT          (10u)
+#define INTC_ICDISR8_INTRCAN4REC_SHIFT          (11u)
+#define INTC_ICDISR8_INTRCAN4ERR_SHIFT          (12u)
+#define INTC_ICDISR8_INTRCAN4TRX_SHIFT          (13u)
+#define INTC_ICDISR8_SPEI0_SHIFT                (14u)
+#define INTC_ICDISR8_SPRI0_SHIFT                (15u)
+#define INTC_ICDISR8_SPTI0_SHIFT                (16u)
+#define INTC_ICDISR8_SPEI1_SHIFT                (17u)
+#define INTC_ICDISR8_SPRI1_SHIFT                (18u)
+#define INTC_ICDISR8_SPTI1_SHIFT                (19u)
+#define INTC_ICDISR8_SPEI2_SHIFT                (20u)
+#define INTC_ICDISR8_SPRI2_SHIFT                (21u)
+#define INTC_ICDISR8_SPTI2_SHIFT                (22u)
+#define INTC_ICDISR8_SPEI3_SHIFT                (23u)
+#define INTC_ICDISR8_SPRI3_SHIFT                (24u)
+#define INTC_ICDISR8_SPTI3_SHIFT                (25u)
+#define INTC_ICDISR8_SPEI4_SHIFT                (26u)
+#define INTC_ICDISR8_SPRI4_SHIFT                (27u)
+#define INTC_ICDISR8_SPTI4_SHIFT                (28u)
+#define INTC_ICDISR8_IEBBTD_SHIFT               (29u)
+#define INTC_ICDISR8_IEBBTERR_SHIFT             (30u)
+#define INTC_ICDISR8_IEBBTSTA_SHIFT             (31u)
+
+#define INTC_ICDISR9_IEBBTV_SHIFT               (0u)
+#define INTC_ICDISR9_ISY_SHIFT                  (1u)
+#define INTC_ICDISR9_IERR_SHIFT                 (2u)
+#define INTC_ICDISR9_ITARG_SHIFT                (3u)
+#define INTC_ICDISR9_ISEC_SHIFT                 (4u)
+#define INTC_ICDISR9_IBUF_SHIFT                 (5u)
+#define INTC_ICDISR9_IREADY_SHIFT               (6u)
+#define INTC_ICDISR9_FLSTE_SHIFT                (7u)
+#define INTC_ICDISR9_FLTENDI_SHIFT              (8u)
+#define INTC_ICDISR9_FLTREQ0I_SHIFT             (9u)
+#define INTC_ICDISR9_FLTREQ1I_SHIFT             (10u)
+#define INTC_ICDISR9_MMC0_SHIFT                 (11u)
+#define INTC_ICDISR9_MMC1_SHIFT                 (12u)
+#define INTC_ICDISR9_MMC2_SHIFT                 (13u)
+#define INTC_ICDISR9_SDHI0_3_SHIFT              (14u)
+#define INTC_ICDISR9_SDHI0_0_SHIFT              (15u)
+#define INTC_ICDISR9_SDHI0_1_SHIFT              (16u)
+#define INTC_ICDISR9_SDHI1_3_SHIFT              (17u)
+#define INTC_ICDISR9_SDHI1_0_SHIFT              (18u)
+#define INTC_ICDISR9_SDHI1_1_SHIFT              (19u)
+#define INTC_ICDISR9_ARM_SHIFT                  (20u)
+#define INTC_ICDISR9_PRD_SHIFT                  (21u)
+#define INTC_ICDISR9_CUP_SHIFT                  (22u)
+#define INTC_ICDISR9_SCUAI0_SHIFT               (23u)
+#define INTC_ICDISR9_SCUAI1_SHIFT               (24u)
+#define INTC_ICDISR9_SCUFDI0_SHIFT              (25u)
+#define INTC_ICDISR9_SCUFDI1_SHIFT              (26u)
+#define INTC_ICDISR9_SCUFDI2_SHIFT              (27u)
+#define INTC_ICDISR9_SCUFDI3_SHIFT              (28u)
+#define INTC_ICDISR9_SCUFUI0_SHIFT              (29u)
+#define INTC_ICDISR9_SCUFUI1_SHIFT              (30u)
+#define INTC_ICDISR9_SCUFUI2_SHIFT              (31u)
+
+#define INTC_ICDISR10_SCUFUI3_SHIFT             (0u)
+#define INTC_ICDISR10_SCUDVI0_SHIFT             (1u)
+#define INTC_ICDISR10_SCUDVI1_SHIFT             (2u)
+#define INTC_ICDISR10_SCUDVI2_SHIFT             (3u)
+#define INTC_ICDISR10_SCUDVI3_SHIFT             (4u)
+#define INTC_ICDISR10_MLB_CINT_SHIFT            (5u)
+#define INTC_ICDISR10_MLB_SINT_SHIFT            (6u)
+#define INTC_ICDISR10_DRC0_SHIFT                (7u)
+#define INTC_ICDISR10_DRC1_SHIFT                (8u)
+#define INTC_ICDISR10_LINI0_INT_T_SHIFT         (11u)
+#define INTC_ICDISR10_LINI0_INT_R_SHIFT         (12u)
+#define INTC_ICDISR10_LINI0_INT_S_SHIFT         (13u)
+#define INTC_ICDISR10_LINI0_INT_M_SHIFT         (14u)
+#define INTC_ICDISR10_LINI1_INT_T_SHIFT         (15u)
+#define INTC_ICDISR10_LINI1_INT_R_SHIFT         (16u)
+#define INTC_ICDISR10_LINI1_INT_S_SHIFT         (17u)
+#define INTC_ICDISR10_LINI1_INT_M_SHIFT         (18u)
+#define INTC_ICDISR10_ERI0_SHIFT                (27u)
+#define INTC_ICDISR10_RXI0_SHIFT                (28u)
+#define INTC_ICDISR10_TXI0_SHIFT                (29u)
+#define INTC_ICDISR10_TEI0_SHIFT                (30u)
+#define INTC_ICDISR10_ERI1_SHIFT                (31u)
+
+#define INTC_ICDISR11_RXI1_SHIFT                (0u)
+#define INTC_ICDISR11_TXI1_SHIFT                (1u)
+#define INTC_ICDISR11_TEI1_SHIFT                (2u)
+#define INTC_ICDISR11_AVBI_DATA_SHIFT           (3u)
+#define INTC_ICDISR11_AVBI_ERROR_SHIFT          (4u)
+#define INTC_ICDISR11_AVBI_MANAGE_SHIFT         (5u)
+#define INTC_ICDISR11_AVBI_MAC_SHIFT            (6u)
+#define INTC_ICDISR11_ETHERI_SHIFT              (7u)
+#define INTC_ICDISR11_CEUI_SHIFT                (12u)
+#define INTC_ICDISR11_H2XMLB_ERRINT_SHIFT       (29u)
+#define INTC_ICDISR11_H2XIC1_ERRINT_SHIFT       (30u)
+#define INTC_ICDISR11_X2HPERI1_ERRINT_SHIFT     (31u)
+
+#define INTC_ICDISR12_X2HPERI2_ERRINT_SHIFT     (0u)
+#define INTC_ICDISR12_X2HPERI34_ERRINT_SHIFT    (1u)
+#define INTC_ICDISR12_X2HPERI5_ERRINT_SHIFT     (2u)
+#define INTC_ICDISR12_X2HPERI67_ERRINT_SHIFT    (3u)
+#define INTC_ICDISR12_X2HDBGR_ERRINT_SHIFT      (4u)
+#define INTC_ICDISR12_X2HBSC_ERRINT_SHIFT       (5u)
+#define INTC_ICDISR12_X2HSPI1_ERRINT_SHIFT      (6u)
+#define INTC_ICDISR12_X2HSPI2_ERRINT_SHIFT      (7u)
+#define INTC_ICDISR12_PRRI_SHIFT                (8u)
+#define INTC_ICDISR12_IFEI0_SHIFT               (9u)
+#define INTC_ICDISR12_OFFI0_SHIFT               (10u)
+#define INTC_ICDISR12_PFVEI0_SHIFT              (11u)
+#define INTC_ICDISR12_IFEI1_SHIFT               (12u)
+#define INTC_ICDISR12_OFFI1_SHIFT               (13u)
+#define INTC_ICDISR12_PFVEI1_SHIFT              (14u)
+
+#define INTC_ICDISR13_TINT0_SHIFT               (0u)
+#define INTC_ICDISR13_TINT1_SHIFT               (1u)
+#define INTC_ICDISR13_TINT2_SHIFT               (2u)
+#define INTC_ICDISR13_TINT3_SHIFT               (3u)
+#define INTC_ICDISR13_TINT4_SHIFT               (4u)
+#define INTC_ICDISR13_TINT5_SHIFT               (5u)
+#define INTC_ICDISR13_TINT6_SHIFT               (6u)
+#define INTC_ICDISR13_TINT7_SHIFT               (7u)
+#define INTC_ICDISR13_TINT8_SHIFT               (8u)
+#define INTC_ICDISR13_TINT9_SHIFT               (9u)
+#define INTC_ICDISR13_TINT10_SHIFT              (10u)
+#define INTC_ICDISR13_TINT11_SHIFT              (11u)
+#define INTC_ICDISR13_TINT12_SHIFT              (12u)
+#define INTC_ICDISR13_TINT13_SHIFT              (13u)
+#define INTC_ICDISR13_TINT14_SHIFT              (14u)
+#define INTC_ICDISR13_TINT15_SHIFT              (15u)
+#define INTC_ICDISR13_TINT16_SHIFT              (16u)
+#define INTC_ICDISR13_TINT17_SHIFT              (17u)
+#define INTC_ICDISR13_TINT18_SHIFT              (18u)
+#define INTC_ICDISR13_TINT19_SHIFT              (19u)
+#define INTC_ICDISR13_TINT20_SHIFT              (20u)
+#define INTC_ICDISR13_TINT21_SHIFT              (21u)
+#define INTC_ICDISR13_TINT22_SHIFT              (22u)
+#define INTC_ICDISR13_TINT23_SHIFT              (23u)
+#define INTC_ICDISR13_TINT24_SHIFT              (24u)
+#define INTC_ICDISR13_TINT25_SHIFT              (25u)
+#define INTC_ICDISR13_TINT26_SHIFT              (26u)
+#define INTC_ICDISR13_TINT27_SHIFT              (27u)
+#define INTC_ICDISR13_TINT28_SHIFT              (28u)
+#define INTC_ICDISR13_TINT29_SHIFT              (29u)
+#define INTC_ICDISR13_TINT30_SHIFT              (30u)
+#define INTC_ICDISR13_TINT31_SHIFT              (31u)
+
+#define INTC_ICDISR14_TINT32_SHIFT              (0u)
+#define INTC_ICDISR14_TINT33_SHIFT              (1u)
+#define INTC_ICDISR14_TINT34_SHIFT              (2u)
+#define INTC_ICDISR14_TINT35_SHIFT              (3u)
+#define INTC_ICDISR14_TINT36_SHIFT              (4u)
+#define INTC_ICDISR14_TINT37_SHIFT              (5u)
+#define INTC_ICDISR14_TINT38_SHIFT              (6u)
+#define INTC_ICDISR14_TINT39_SHIFT              (7u)
+#define INTC_ICDISR14_TINT40_SHIFT              (8u)
+#define INTC_ICDISR14_TINT41_SHIFT              (9u)
+#define INTC_ICDISR14_TINT42_SHIFT              (10u)
+#define INTC_ICDISR14_TINT43_SHIFT              (11u)
+#define INTC_ICDISR14_TINT44_SHIFT              (12u)
+#define INTC_ICDISR14_TINT45_SHIFT              (13u)
+#define INTC_ICDISR14_TINT46_SHIFT              (14u)
+#define INTC_ICDISR14_TINT47_SHIFT              (15u)
+#define INTC_ICDISR14_TINT48_SHIFT              (16u)
+#define INTC_ICDISR14_TINT49_SHIFT              (17u)
+#define INTC_ICDISR14_TINT50_SHIFT              (18u)
+#define INTC_ICDISR14_TINT51_SHIFT              (19u)
+#define INTC_ICDISR14_TINT52_SHIFT              (20u)
+#define INTC_ICDISR14_TINT53_SHIFT              (21u)
+#define INTC_ICDISR14_TINT54_SHIFT              (22u)
+#define INTC_ICDISR14_TINT55_SHIFT              (23u)
+#define INTC_ICDISR14_TINT56_SHIFT              (24u)
+#define INTC_ICDISR14_TINT57_SHIFT              (25u)
+#define INTC_ICDISR14_TINT58_SHIFT              (26u)
+#define INTC_ICDISR14_TINT59_SHIFT              (27u)
+#define INTC_ICDISR14_TINT60_SHIFT              (28u)
+#define INTC_ICDISR14_TINT61_SHIFT              (29u)
+#define INTC_ICDISR14_TINT62_SHIFT              (30u)
+#define INTC_ICDISR14_TINT63_SHIFT              (31u)
+
+#define INTC_ICDISR15_TINT64_SHIFT              (0u)
+#define INTC_ICDISR15_TINT65_SHIFT              (1u)
+#define INTC_ICDISR15_TINT66_SHIFT              (2u)
+#define INTC_ICDISR15_TINT67_SHIFT              (3u)
+#define INTC_ICDISR15_TINT68_SHIFT              (4u)
+#define INTC_ICDISR15_TINT69_SHIFT              (5u)
+#define INTC_ICDISR15_TINT70_SHIFT              (6u)
+#define INTC_ICDISR15_TINT71_SHIFT              (7u)
+#define INTC_ICDISR15_TINT72_SHIFT              (8u)
+#define INTC_ICDISR15_TINT73_SHIFT              (9u)
+#define INTC_ICDISR15_TINT74_SHIFT              (10u)
+#define INTC_ICDISR15_TINT75_SHIFT              (11u)
+#define INTC_ICDISR15_TINT76_SHIFT              (12u)
+#define INTC_ICDISR15_TINT77_SHIFT              (13u)
+#define INTC_ICDISR15_TINT78_SHIFT              (14u)
+#define INTC_ICDISR15_TINT79_SHIFT              (15u)
+#define INTC_ICDISR15_TINT80_SHIFT              (16u)
+#define INTC_ICDISR15_TINT81_SHIFT              (17u)
+#define INTC_ICDISR15_TINT82_SHIFT              (18u)
+#define INTC_ICDISR15_TINT83_SHIFT              (19u)
+#define INTC_ICDISR15_TINT84_SHIFT              (20u)
+#define INTC_ICDISR15_TINT85_SHIFT              (21u)
+#define INTC_ICDISR15_TINT86_SHIFT              (22u)
+#define INTC_ICDISR15_TINT87_SHIFT              (23u)
+#define INTC_ICDISR15_TINT88_SHIFT              (24u)
+#define INTC_ICDISR15_TINT89_SHIFT              (25u)
+#define INTC_ICDISR15_TINT90_SHIFT              (26u)
+#define INTC_ICDISR15_TINT91_SHIFT              (27u)
+#define INTC_ICDISR15_TINT92_SHIFT              (28u)
+#define INTC_ICDISR15_TINT93_SHIFT              (29u)
+#define INTC_ICDISR15_TINT94_SHIFT              (30u)
+#define INTC_ICDISR15_TINT95_SHIFT              (31u)
+
+#define INTC_ICDISR16_TINT96_SHIFT              (0u)
+#define INTC_ICDISR16_TINT97_SHIFT              (1u)
+#define INTC_ICDISR16_TINT98_SHIFT              (2u)
+#define INTC_ICDISR16_TINT99_SHIFT              (3u)
+#define INTC_ICDISR16_TINT100_SHIFT             (4u)
+#define INTC_ICDISR16_TINT101_SHIFT             (5u)
+#define INTC_ICDISR16_TINT102_SHIFT             (6u)
+#define INTC_ICDISR16_TINT103_SHIFT             (7u)
+#define INTC_ICDISR16_TINT104_SHIFT             (8u)
+#define INTC_ICDISR16_TINT105_SHIFT             (9u)
+#define INTC_ICDISR16_TINT106_SHIFT             (10u)
+#define INTC_ICDISR16_TINT107_SHIFT             (11u)
+#define INTC_ICDISR16_TINT108_SHIFT             (12u)
+#define INTC_ICDISR16_TINT109_SHIFT             (13u)
+#define INTC_ICDISR16_TINT110_SHIFT             (14u)
+#define INTC_ICDISR16_TINT111_SHIFT             (15u)
+#define INTC_ICDISR16_TINT112_SHIFT             (16u)
+#define INTC_ICDISR16_TINT113_SHIFT             (17u)
+#define INTC_ICDISR16_TINT114_SHIFT             (18u)
+#define INTC_ICDISR16_TINT115_SHIFT             (19u)
+#define INTC_ICDISR16_TINT116_SHIFT             (20u)
+#define INTC_ICDISR16_TINT117_SHIFT             (21u)
+#define INTC_ICDISR16_TINT118_SHIFT             (22u)
+#define INTC_ICDISR16_TINT119_SHIFT             (23u)
+#define INTC_ICDISR16_TINT120_SHIFT             (24u)
+#define INTC_ICDISR16_TINT121_SHIFT             (25u)
+#define INTC_ICDISR16_TINT122_SHIFT             (26u)
+#define INTC_ICDISR16_TINT123_SHIFT             (27u)
+#define INTC_ICDISR16_TINT124_SHIFT             (28u)
+#define INTC_ICDISR16_TINT125_SHIFT             (29u)
+#define INTC_ICDISR16_TINT126_SHIFT             (30u)
+#define INTC_ICDISR16_TINT127_SHIFT             (31u)
+
+#define INTC_ICDISR17_TINT128_SHIFT             (0u)
+#define INTC_ICDISR17_TINT129_SHIFT             (1u)
+#define INTC_ICDISR17_TINT130_SHIFT             (2u)
+#define INTC_ICDISR17_TINT131_SHIFT             (3u)
+#define INTC_ICDISR17_TINT132_SHIFT             (4u)
+#define INTC_ICDISR17_TINT133_SHIFT             (5u)
+#define INTC_ICDISR17_TINT134_SHIFT             (6u)
+#define INTC_ICDISR17_TINT135_SHIFT             (7u)
+#define INTC_ICDISR17_TINT136_SHIFT             (8u)
+#define INTC_ICDISR17_TINT137_SHIFT             (9u)
+#define INTC_ICDISR17_TINT138_SHIFT             (10u)
+#define INTC_ICDISR17_TINT139_SHIFT             (11u)
+#define INTC_ICDISR17_TINT140_SHIFT             (12u)
+#define INTC_ICDISR17_TINT141_SHIFT             (13u)
+#define INTC_ICDISR17_TINT142_SHIFT             (14u)
+#define INTC_ICDISR17_TINT143_SHIFT             (15u)
+#define INTC_ICDISR17_TINT144_SHIFT             (16u)
+#define INTC_ICDISR17_TINT145_SHIFT             (17u)
+#define INTC_ICDISR17_TINT146_SHIFT             (18u)
+#define INTC_ICDISR17_TINT147_SHIFT             (19u)
+#define INTC_ICDISR17_TINT148_SHIFT             (20u)
+#define INTC_ICDISR17_TINT149_SHIFT             (21u)
+#define INTC_ICDISR17_TINT150_SHIFT             (22u)
+#define INTC_ICDISR17_TINT151_SHIFT             (23u)
+#define INTC_ICDISR17_TINT152_SHIFT             (24u)
+#define INTC_ICDISR17_TINT153_SHIFT             (25u)
+#define INTC_ICDISR17_TINT154_SHIFT             (26u)
+#define INTC_ICDISR17_TINT155_SHIFT             (27u)
+#define INTC_ICDISR17_TINT156_SHIFT             (28u)
+#define INTC_ICDISR17_TINT157_SHIFT             (29u)
+#define INTC_ICDISR17_TINT158_SHIFT             (30u)
+#define INTC_ICDISR17_TINT159_SHIFT             (31u)
+
+#define INTC_ICDISR18_TINT160_SHIFT             (0u)
+#define INTC_ICDISR18_TINT161_SHIFT             (1u)
+#define INTC_ICDISR18_TINT162_SHIFT             (2u)
+#define INTC_ICDISR18_TINT163_SHIFT             (3u)
+#define INTC_ICDISR18_TINT164_SHIFT             (4u)
+#define INTC_ICDISR18_TINT165_SHIFT             (5u)
+#define INTC_ICDISR18_TINT166_SHIFT             (6u)
+#define INTC_ICDISR18_TINT167_SHIFT             (7u)
+#define INTC_ICDISR18_TINT168_SHIFT             (8u)
+#define INTC_ICDISR18_TINT169_SHIFT             (9u)
+#define INTC_ICDISR18_TINT170_SHIFT             (10u)
+
+#define INTC_ICDISER0_SW0_SHIFT                 (0u)
+#define INTC_ICDISER0_SW1_SHIFT                 (1u)
+#define INTC_ICDISER0_SW2_SHIFT                 (2u)
+#define INTC_ICDISER0_SW3_SHIFT                 (3u)
+#define INTC_ICDISER0_SW4_SHIFT                 (4u)
+#define INTC_ICDISER0_SW5_SHIFT                 (5u)
+#define INTC_ICDISER0_SW6_SHIFT                 (6u)
+#define INTC_ICDISER0_SW7_SHIFT                 (7u)
+#define INTC_ICDISER0_SW8_SHIFT                 (8u)
+#define INTC_ICDISER0_SW9_SHIFT                 (9u)
+#define INTC_ICDISER0_SW10_SHIFT                (10u)
+#define INTC_ICDISER0_SW11_SHIFT                (11u)
+#define INTC_ICDISER0_SW12_SHIFT                (12u)
+#define INTC_ICDISER0_SW13_SHIFT                (13u)
+#define INTC_ICDISER0_SW14_SHIFT                (14u)
+#define INTC_ICDISER0_SW15_SHIFT                (15u)
+#define INTC_ICDISER0_PMUIRQ0_SHIFT             (16u)
+#define INTC_ICDISER0_COMMRX0_SHIFT             (17u)
+#define INTC_ICDISER0_COMMTX0_SHIFT             (18u)
+#define INTC_ICDISER0_CTIIRQ0_SHIFT             (19u)
+
+#define INTC_ICDISER1_IRQ0_SHIFT                (0u)
+#define INTC_ICDISER1_IRQ1_SHIFT                (1u)
+#define INTC_ICDISER1_IRQ2_SHIFT                (2u)
+#define INTC_ICDISER1_IRQ3_SHIFT                (3u)
+#define INTC_ICDISER1_IRQ4_SHIFT                (4u)
+#define INTC_ICDISER1_IRQ5_SHIFT                (5u)
+#define INTC_ICDISER1_IRQ6_SHIFT                (6u)
+#define INTC_ICDISER1_IRQ7_SHIFT                (7u)
+#define INTC_ICDISER1_PL310ERR_SHIFT            (8u)
+#define INTC_ICDISER1_DMAINT0_SHIFT             (9u)
+#define INTC_ICDISER1_DMAINT1_SHIFT             (10u)
+#define INTC_ICDISER1_DMAINT2_SHIFT             (11u)
+#define INTC_ICDISER1_DMAINT3_SHIFT             (12u)
+#define INTC_ICDISER1_DMAINT4_SHIFT             (13u)
+#define INTC_ICDISER1_DMAINT5_SHIFT             (14u)
+#define INTC_ICDISER1_DMAINT6_SHIFT             (15u)
+#define INTC_ICDISER1_DMAINT7_SHIFT             (16u)
+#define INTC_ICDISER1_DMAINT8_SHIFT             (17u)
+#define INTC_ICDISER1_DMAINT9_SHIFT             (18u)
+#define INTC_ICDISER1_DMAINT10_SHIFT            (19u)
+#define INTC_ICDISER1_DMAINT11_SHIFT            (20u)
+#define INTC_ICDISER1_DMAINT12_SHIFT            (21u)
+#define INTC_ICDISER1_DMAINT13_SHIFT            (22u)
+#define INTC_ICDISER1_DMAINT14_SHIFT            (23u)
+#define INTC_ICDISER1_DMAINT15_SHIFT            (24u)
+#define INTC_ICDISER1_DMAERR_SHIFT              (25u)
+
+#define INTC_ICDISER2_USBI0_SHIFT               (9u)
+#define INTC_ICDISER2_USBI1_SHIFT               (10u)
+#define INTC_ICDISER2_S0_VI_VSYNC0_SHIFT        (11u)
+#define INTC_ICDISER2_S0_LO_VSYNC0_SHIFT        (12u)
+#define INTC_ICDISER2_S0_VSYNCERR0_SHIFT        (13u)
+#define INTC_ICDISER2_GR3_VLINE0_SHIFT          (14u)
+#define INTC_ICDISER2_S0_VFIELD0_SHIFT          (15u)
+#define INTC_ICDISER2_IV1_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDISER2_IV3_VBUFERR0_SHIFT        (17u)
+#define INTC_ICDISER2_IV5_VBUFERR0_SHIFT        (18u)
+#define INTC_ICDISER2_IV6_VBUFERR0_SHIFT        (19u)
+#define INTC_ICDISER2_S0_WLINE0_SHIFT           (20u)
+#define INTC_ICDISER2_S1_VI_VSYNC0_SHIFT        (21u)
+#define INTC_ICDISER2_S1_LO_VSYNC0_SHIFT        (22u)
+#define INTC_ICDISER2_S1_VSYNCERR0_SHIFT        (23u)
+#define INTC_ICDISER2_S1_VFIELD0_SHIFT          (24u)
+#define INTC_ICDISER2_IV2_VBUFERR0_SHIFT        (25u)
+#define INTC_ICDISER2_IV4_VBUFERR0_SHIFT        (26u)
+#define INTC_ICDISER2_S1_WLINE0_SHIFT           (27u)
+#define INTC_ICDISER2_OIR_VI_VSYNC0_SHIFT       (28u)
+#define INTC_ICDISER2_OIR_LO_VSYNC0_SHIFT       (29u)
+#define INTC_ICDISER2_OIR_VSYNCERR0_SHIFT       (30u)
+#define INTC_ICDISER2_OIR_VFIELD0_SHIFT         (31u)
+
+#define INTC_ICDISER3_IV7_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDISER3_IV8_VBUFERR0_SHIFT        (1u)
+#define INTC_ICDISER3_S0_VI_VSYNC1_SHIFT        (3u)
+#define INTC_ICDISER3_S0_LO_VSYNC1_SHIFT        (4u)
+#define INTC_ICDISER3_S0_VSYNCERR1_SHIFT        (5u)
+#define INTC_ICDISER3_GR3_VLINE1_SHIFT          (6u)
+#define INTC_ICDISER3_S0_VFIELD1_SHIFT          (7u)
+#define INTC_ICDISER3_IV1_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDISER3_IV3_VBUFERR1_SHIFT        (9u)
+#define INTC_ICDISER3_IV5_VBUFERR1_SHIFT        (10u)
+#define INTC_ICDISER3_IV6_VBUFERR1_SHIFT        (11u)
+#define INTC_ICDISER3_S0_WLINE1_SHIFT           (12u)
+#define INTC_ICDISER3_S1_VI_VSYNC1_SHIFT        (13u)
+#define INTC_ICDISER3_S1_LO_VSYNC1_SHIFT        (14u)
+#define INTC_ICDISER3_S1_VSYNCERR1_SHIFT        (15u)
+#define INTC_ICDISER3_S1_VFIELD1_SHIFT          (16u)
+#define INTC_ICDISER3_IV2_VBUFERR1_SHIFT        (17u)
+#define INTC_ICDISER3_IV4_VBUFERR1_SHIFT        (18u)
+#define INTC_ICDISER3_S1_WLINE1_SHIFT           (19u)
+#define INTC_ICDISER3_OIR_VI_VSYNC1_SHIFT       (20u)
+#define INTC_ICDISER3_OIR_LO_VSYNC1_SHIFT       (21u)
+#define INTC_ICDISER3_OIR_VLINE1_SHIFT          (22u)
+#define INTC_ICDISER3_OIR_VFIELD1_SHIFT         (23u)
+#define INTC_ICDISER3_IV7_VBUFERR1_SHIFT        (24u)
+#define INTC_ICDISER3_IV8_VBUFERR1_SHIFT        (25u)
+#define INTC_ICDISER3_IMRDI_SHIFT               (27u)
+#define INTC_ICDISER3_IMR2I0_SHIFT              (28u)
+#define INTC_ICDISER3_IMR2I1_SHIFT              (29u)
+#define INTC_ICDISER3_JEDI_SHIFT                (30u)
+#define INTC_ICDISER3_JDTI_SHIFT                (31u)
+
+#define INTC_ICDISER4_CMP0_SHIFT                (0u)
+#define INTC_ICDISER4_CMP1_SHIFT                (1u)
+#define INTC_ICDISER4_INT0_SHIFT                (2u)
+#define INTC_ICDISER4_INT1_SHIFT                (3u)
+#define INTC_ICDISER4_INT2_SHIFT                (4u)
+#define INTC_ICDISER4_INT3_SHIFT                (5u)
+#define INTC_ICDISER4_OSTM0TINT_SHIFT           (6u)
+#define INTC_ICDISER4_OSTM1TINT_SHIFT           (7u)
+#define INTC_ICDISER4_CMI_SHIFT                 (8u)
+#define INTC_ICDISER4_WTOUT_SHIFT               (9u)
+#define INTC_ICDISER4_ITI_SHIFT                 (10u)
+#define INTC_ICDISER4_TGI0A_SHIFT               (11u)
+#define INTC_ICDISER4_TGI0B_SHIFT               (12u)
+#define INTC_ICDISER4_TGI0C_SHIFT               (13u)
+#define INTC_ICDISER4_TGI0D_SHIFT               (14u)
+#define INTC_ICDISER4_TGI0V_SHIFT               (15u)
+#define INTC_ICDISER4_TGI0E_SHIFT               (16u)
+#define INTC_ICDISER4_TGI0F_SHIFT               (17u)
+#define INTC_ICDISER4_TGI1A_SHIFT               (18u)
+#define INTC_ICDISER4_TGI1B_SHIFT               (19u)
+#define INTC_ICDISER4_TGI1V_SHIFT               (20u)
+#define INTC_ICDISER4_TGI1U_SHIFT               (21u)
+#define INTC_ICDISER4_TGI2A_SHIFT               (22u)
+#define INTC_ICDISER4_TGI2B_SHIFT               (23u)
+#define INTC_ICDISER4_TGI2V_SHIFT               (24u)
+#define INTC_ICDISER4_TGI2U_SHIFT               (25u)
+#define INTC_ICDISER4_TGI3A_SHIFT               (26u)
+#define INTC_ICDISER4_TGI3B_SHIFT               (27u)
+#define INTC_ICDISER4_TGI3C_SHIFT               (28u)
+#define INTC_ICDISER4_TGI3D_SHIFT               (29u)
+#define INTC_ICDISER4_TGI3V_SHIFT               (30u)
+#define INTC_ICDISER4_TGI4A_SHIFT               (31u)
+
+#define INTC_ICDISER5_TGI4B_SHIFT               (0u)
+#define INTC_ICDISER5_TGI4C_SHIFT               (1u)
+#define INTC_ICDISER5_TGI4D_SHIFT               (2u)
+#define INTC_ICDISER5_TGI4V_SHIFT               (3u)
+#define INTC_ICDISER5_CMI1_SHIFT                (4u)
+#define INTC_ICDISER5_CMI2_SHIFT                (5u)
+#define INTC_ICDISER5_SGDEI0_SHIFT              (6u)
+#define INTC_ICDISER5_SGDEI1_SHIFT              (7u)
+#define INTC_ICDISER5_SGDEI2_SHIFT              (8u)
+#define INTC_ICDISER5_SGDEI3_SHIFT              (9u)
+#define INTC_ICDISER5_ADI_SHIFT                 (10u)
+#define INTC_ICDISER5_LMTI_SHIFT                (11u)
+#define INTC_ICDISER5_SSII0_SHIFT               (12u)
+#define INTC_ICDISER5_SSIRXI0_SHIFT             (13u)
+#define INTC_ICDISER5_SSITXI0_SHIFT             (14u)
+#define INTC_ICDISER5_SSII1_SHIFT               (15u)
+#define INTC_ICDISER5_SSIRXI1_SHIFT             (16u)
+#define INTC_ICDISER5_SSITXI1_SHIFT             (17u)
+#define INTC_ICDISER5_SSII2_SHIFT               (18u)
+#define INTC_ICDISER5_SSIRTI2_SHIFT             (19u)
+#define INTC_ICDISER5_SSII3_SHIFT               (20u)
+#define INTC_ICDISER5_SSIRXI3_SHIFT             (21u)
+#define INTC_ICDISER5_SSITXI3_SHIFT             (22u)
+#define INTC_ICDISER5_SSII4_SHIFT               (23u)
+#define INTC_ICDISER5_SSIRTI4_SHIFT             (24u)
+#define INTC_ICDISER5_SSII5_SHIFT               (25u)
+#define INTC_ICDISER5_SSIRXI5_SHIFT             (26u)
+#define INTC_ICDISER5_SSITXI5_SHIFT             (27u)
+#define INTC_ICDISER5_SPDIFI_SHIFT              (28u)
+#define INTC_ICDISER5_INTIICTEI0_SHIFT          (29u)
+#define INTC_ICDISER5_INTIICRI0_SHIFT           (30u)
+#define INTC_ICDISER5_INTIICTI0_SHIFT           (31u)
+
+#define INTC_ICDISER6_INTIICSPI0_SHIFT          (0u)
+#define INTC_ICDISER6_INTIICSTI0_SHIFT          (1u)
+#define INTC_ICDISER6_INTIICNAKI0_SHIFT         (2u)
+#define INTC_ICDISER6_INTIICALI0_SHIFT          (3u)
+#define INTC_ICDISER6_INTIICTMOI0_SHIFT         (4u)
+#define INTC_ICDISER6_INTIICTEI1_SHIFT          (5u)
+#define INTC_ICDISER6_INTIICRI1_SHIFT           (6u)
+#define INTC_ICDISER6_INTIICTI1_SHIFT           (7u)
+#define INTC_ICDISER6_INTIICSPI1_SHIFT          (8u)
+#define INTC_ICDISER6_INTIICSTI1_SHIFT          (9u)
+#define INTC_ICDISER6_INTIICNAKI1_SHIFT         (10u)
+#define INTC_ICDISER6_INTIICALI1_SHIFT          (11u)
+#define INTC_ICDISER6_INTIICTMOI1_SHIFT         (12u)
+#define INTC_ICDISER6_INTIICTEI2_SHIFT          (13u)
+#define INTC_ICDISER6_INTIICRI2_SHIFT           (14u)
+#define INTC_ICDISER6_INTIICTI2_SHIFT           (15u)
+#define INTC_ICDISER6_INTIICSPI2_SHIFT          (16u)
+#define INTC_ICDISER6_INTIICSTI2_SHIFT          (17u)
+#define INTC_ICDISER6_INTIICNAKI2_SHIFT         (18u)
+#define INTC_ICDISER6_INTIICALI2_SHIFT          (19u)
+#define INTC_ICDISER6_INTIICTMOI2_SHIFT         (20u)
+#define INTC_ICDISER6_INTIICTEI3_SHIFT          (21u)
+#define INTC_ICDISER6_INTIICRI3_SHIFT           (22u)
+#define INTC_ICDISER6_INTIICTI3_SHIFT           (23u)
+#define INTC_ICDISER6_INTIICSPI3_SHIFT          (24u)
+#define INTC_ICDISER6_INTIICSTI3_SHIFT          (25u)
+#define INTC_ICDISER6_INTIICNAKI3_SHIFT         (26u)
+#define INTC_ICDISER6_INTIICALI3_SHIFT          (27u)
+#define INTC_ICDISER6_INTIICTMOI3_SHIFT         (28u)
+#define INTC_ICDISER6_BRI0_SHIFT                (29u)
+#define INTC_ICDISER6_ERI0_SHIFT                (30u)
+#define INTC_ICDISER6_RXI0_SHIFT                (31u)
+
+#define INTC_ICDISER7_TXI0_SHIFT                (0u)
+#define INTC_ICDISER7_BRI1_SHIFT                (1u)
+#define INTC_ICDISER7_ERI1_SHIFT                (2u)
+#define INTC_ICDISER7_RXI1_SHIFT                (3u)
+#define INTC_ICDISER7_TXI1_SHIFT                (4u)
+#define INTC_ICDISER7_BRI2_SHIFT                (5u)
+#define INTC_ICDISER7_ERI2_SHIFT                (6u)
+#define INTC_ICDISER7_RXI2_SHIFT                (7u)
+#define INTC_ICDISER7_TXI2_SHIFT                (8u)
+#define INTC_ICDISER7_BRI3_SHIFT                (9u)
+#define INTC_ICDISER7_ERI3_SHIFT                (10u)
+#define INTC_ICDISER7_RXI3_SHIFT                (11u)
+#define INTC_ICDISER7_TXI3_SHIFT                (12u)
+#define INTC_ICDISER7_BRI4_SHIFT                (13u)
+#define INTC_ICDISER7_ERI4_SHIFT                (14u)
+#define INTC_ICDISER7_RXI4_SHIFT                (15u)
+#define INTC_ICDISER7_TXI4_SHIFT                (16u)
+#define INTC_ICDISER7_BRI5_SHIFT                (17u)
+#define INTC_ICDISER7_ERI5_SHIFT                (18u)
+#define INTC_ICDISER7_RXI5_SHIFT                (19u)
+#define INTC_ICDISER7_TXI5_SHIFT                (20u)
+#define INTC_ICDISER7_BRI6_SHIFT                (21u)
+#define INTC_ICDISER7_ERI6_SHIFT                (22u)
+#define INTC_ICDISER7_RXI6_SHIFT                (23u)
+#define INTC_ICDISER7_TXI6_SHIFT                (24u)
+#define INTC_ICDISER7_BRI7_SHIFT                (25u)
+#define INTC_ICDISER7_ERI7_SHIFT                (26u)
+#define INTC_ICDISER7_RXI7_SHIFT                (27u)
+#define INTC_ICDISER7_TXI7_SHIFT                (28u)
+#define INTC_ICDISER7_INTRCANGERR_SHIFT         (29u)
+#define INTC_ICDISER7_INTRCANGRECC_SHIFT        (30u)
+#define INTC_ICDISER7_INTRCAN0REC_SHIFT         (31u)
+
+#define INTC_ICDISER8_INTRCAN0ERR_SHIFT         (0u)
+#define INTC_ICDISER8_INTRCAN0TRX_SHIFT         (1u)
+#define INTC_ICDISER8_INTRCAN1REC_SHIFT         (2u)
+#define INTC_ICDISER8_INTRCAN1ERR_SHIFT         (3u)
+#define INTC_ICDISER8_INTRCAN1TRX_SHIFT         (4u)
+#define INTC_ICDISER8_INTRCAN2REC_SHIFT         (5u)
+#define INTC_ICDISER8_INTRCAN2ERR_SHIFT         (6u)
+#define INTC_ICDISER8_INTRCAN2TRX_SHIFT         (7u)
+#define INTC_ICDISER8_INTRCAN3REC_SHIFT         (8u)
+#define INTC_ICDISER8_INTRCAN3ERR_SHIFT         (9u)
+#define INTC_ICDISER8_INTRCAN3TRX_SHIFT         (10u)
+#define INTC_ICDISER8_INTRCAN4REC_SHIFT         (11u)
+#define INTC_ICDISER8_INTRCAN4ERR_SHIFT         (12u)
+#define INTC_ICDISER8_INTRCAN4TRX_SHIFT         (13u)
+#define INTC_ICDISER8_SPEI0_SHIFT               (14u)
+#define INTC_ICDISER8_SPRI0_SHIFT               (15u)
+#define INTC_ICDISER8_SPTI0_SHIFT               (16u)
+#define INTC_ICDISER8_SPEI1_SHIFT               (17u)
+#define INTC_ICDISER8_SPRI1_SHIFT               (18u)
+#define INTC_ICDISER8_SPTI1_SHIFT               (19u)
+#define INTC_ICDISER8_SPEI2_SHIFT               (20u)
+#define INTC_ICDISER8_SPRI2_SHIFT               (21u)
+#define INTC_ICDISER8_SPTI2_SHIFT               (22u)
+#define INTC_ICDISER8_SPEI3_SHIFT               (23u)
+#define INTC_ICDISER8_SPRI3_SHIFT               (24u)
+#define INTC_ICDISER8_SPTI3_SHIFT               (25u)
+#define INTC_ICDISER8_SPEI4_SHIFT               (26u)
+#define INTC_ICDISER8_SPRI4_SHIFT               (27u)
+#define INTC_ICDISER8_SPTI4_SHIFT               (28u)
+#define INTC_ICDISER8_IEBBTD_SHIFT              (29u)
+#define INTC_ICDISER8_IEBBTERR_SHIFT            (30u)
+#define INTC_ICDISER8_IEBBTSTA_SHIFT            (31u)
+
+#define INTC_ICDISER9_IEBBTV_SHIFT              (0u)
+#define INTC_ICDISER9_ISY_SHIFT                 (1u)
+#define INTC_ICDISER9_IERR_SHIFT                (2u)
+#define INTC_ICDISER9_ITARG_SHIFT               (3u)
+#define INTC_ICDISER9_ISEC_SHIFT                (4u)
+#define INTC_ICDISER9_IBUF_SHIFT                (5u)
+#define INTC_ICDISER9_IREADY_SHIFT              (6u)
+#define INTC_ICDISER9_FLSTE_SHIFT               (7u)
+#define INTC_ICDISER9_FLTENDI_SHIFT             (8u)
+#define INTC_ICDISER9_FLTREQ0I_SHIFT            (9u)
+#define INTC_ICDISER9_FLTREQ1I_SHIFT            (10u)
+#define INTC_ICDISER9_MMC0_SHIFT                (11u)
+#define INTC_ICDISER9_MMC1_SHIFT                (12u)
+#define INTC_ICDISER9_MMC2_SHIFT                (13u)
+#define INTC_ICDISER9_SDHI0_3_SHIFT             (14u)
+#define INTC_ICDISER9_SDHI0_0_SHIFT             (15u)
+#define INTC_ICDISER9_SDHI0_1_SHIFT             (16u)
+#define INTC_ICDISER9_SDHI1_3_SHIFT             (17u)
+#define INTC_ICDISER9_SDHI1_0_SHIFT             (18u)
+#define INTC_ICDISER9_SDHI1_1_SHIFT             (19u)
+#define INTC_ICDISER9_ARM_SHIFT                 (20u)
+#define INTC_ICDISER9_PRD_SHIFT                 (21u)
+#define INTC_ICDISER9_CUP_SHIFT                 (22u)
+#define INTC_ICDISER9_SCUAI0_SHIFT              (23u)
+#define INTC_ICDISER9_SCUAI1_SHIFT              (24u)
+#define INTC_ICDISER9_SCUFDI0_SHIFT             (25u)
+#define INTC_ICDISER9_SCUFDI1_SHIFT             (26u)
+#define INTC_ICDISER9_SCUFDI2_SHIFT             (27u)
+#define INTC_ICDISER9_SCUFDI3_SHIFT             (28u)
+#define INTC_ICDISER9_SCUFUI0_SHIFT             (29u)
+#define INTC_ICDISER9_SCUFUI1_SHIFT             (30u)
+#define INTC_ICDISER9_SCUFUI2_SHIFT             (31u)
+
+#define INTC_ICDISER10_SCUFUI3_SHIFT            (0u)
+#define INTC_ICDISER10_SCUDVI0_SHIFT            (1u)
+#define INTC_ICDISER10_SCUDVI1_SHIFT            (2u)
+#define INTC_ICDISER10_SCUDVI2_SHIFT            (3u)
+#define INTC_ICDISER10_SCUDVI3_SHIFT            (4u)
+#define INTC_ICDISER10_MLB_CINT_SHIFT           (5u)
+#define INTC_ICDISER10_MLB_SINT_SHIFT           (6u)
+#define INTC_ICDISER10_DRC0_SHIFT               (7u)
+#define INTC_ICDISER10_DRC1_SHIFT               (8u)
+#define INTC_ICDISER10_LINI0_INT_T_SHIFT        (11u)
+#define INTC_ICDISER10_LINI0_INT_R_SHIFT        (12u)
+#define INTC_ICDISER10_LINI0_INT_S_SHIFT        (13u)
+#define INTC_ICDISER10_LINI0_INT_M_SHIFT        (14u)
+#define INTC_ICDISER10_LINI1_INT_T_SHIFT        (15u)
+#define INTC_ICDISER10_LINI1_INT_R_SHIFT        (16u)
+#define INTC_ICDISER10_LINI1_INT_S_SHIFT        (17u)
+#define INTC_ICDISER10_LINI1_INT_M_SHIFT        (18u)
+#define INTC_ICDISER10_ERI0_SHIFT               (27u)
+#define INTC_ICDISER10_RXI0_SHIFT               (28u)
+#define INTC_ICDISER10_TXI0_SHIFT               (29u)
+#define INTC_ICDISER10_TEI0_SHIFT               (30u)
+#define INTC_ICDISER10_ERI1_SHIFT               (31u)
+
+#define INTC_ICDISER11_RXI1_SHIFT               (0u)
+#define INTC_ICDISER11_TXI1_SHIFT               (1u)
+#define INTC_ICDISER11_TEI1_SHIFT               (2u)
+#define INTC_ICDISER11_AVBI_DATA_SHIFT          (3u)
+#define INTC_ICDISER11_AVBI_ERROR_SHIFT         (4u)
+#define INTC_ICDISER11_AVBI_MANAGE_SHIFT        (5u)
+#define INTC_ICDISER11_AVBI_MAC_SHIFT           (6u)
+#define INTC_ICDISER11_ETHERI_SHIFT             (7u)
+#define INTC_ICDISER11_CEUI_SHIFT               (12u)
+#define INTC_ICDISER11_H2XMLB_ERRINT_SHIFT      (29u)
+#define INTC_ICDISER11_H2XIC1_ERRINT_SHIFT      (30u)
+#define INTC_ICDISER11_X2HPERI1_ERRINT_SHIFT    (31u)
+
+#define INTC_ICDISER12_X2HPERI2_ERRINT_SHIFT    (0u)
+#define INTC_ICDISER12_X2HPERI34_ERRINT_SHIFT   (1u)
+#define INTC_ICDISER12_X2HPERI5_ERRINT_SHIFT    (2u)
+#define INTC_ICDISER12_X2HPERI67_ERRINT_SHIFT   (3u)
+#define INTC_ICDISER12_X2HDBGR_ERRINT_SHIFT     (4u)
+#define INTC_ICDISER12_X2HBSC_ERRINT_SHIFT      (5u)
+#define INTC_ICDISER12_X2HSPI1_ERRINT_SHIFT     (6u)
+#define INTC_ICDISER12_X2HSPI2_ERRINT_SHIFT     (7u)
+#define INTC_ICDISER12_PRRI_SHIFT               (8u)
+#define INTC_ICDISER12_IFEI0_SHIFT              (9u)
+#define INTC_ICDISER12_OFFI0_SHIFT              (10u)
+#define INTC_ICDISER12_PFVEI0_SHIFT             (11u)
+#define INTC_ICDISER12_IFEI1_SHIFT              (12u)
+#define INTC_ICDISER12_OFFI1_SHIFT              (13u)
+#define INTC_ICDISER12_PFVEI1_SHIFT             (14u)
+
+#define INTC_ICDISER13_TINT0_SHIFT              (0u)
+#define INTC_ICDISER13_TINT1_SHIFT              (1u)
+#define INTC_ICDISER13_TINT2_SHIFT              (2u)
+#define INTC_ICDISER13_TINT3_SHIFT              (3u)
+#define INTC_ICDISER13_TINT4_SHIFT              (4u)
+#define INTC_ICDISER13_TINT5_SHIFT              (5u)
+#define INTC_ICDISER13_TINT6_SHIFT              (6u)
+#define INTC_ICDISER13_TINT7_SHIFT              (7u)
+#define INTC_ICDISER13_TINT8_SHIFT              (8u)
+#define INTC_ICDISER13_TINT9_SHIFT              (9u)
+#define INTC_ICDISER13_TINT10_SHIFT             (10u)
+#define INTC_ICDISER13_TINT11_SHIFT             (11u)
+#define INTC_ICDISER13_TINT12_SHIFT             (12u)
+#define INTC_ICDISER13_TINT13_SHIFT             (13u)
+#define INTC_ICDISER13_TINT14_SHIFT             (14u)
+#define INTC_ICDISER13_TINT15_SHIFT             (15u)
+#define INTC_ICDISER13_TINT16_SHIFT             (16u)
+#define INTC_ICDISER13_TINT17_SHIFT             (17u)
+#define INTC_ICDISER13_TINT18_SHIFT             (18u)
+#define INTC_ICDISER13_TINT19_SHIFT             (19u)
+#define INTC_ICDISER13_TINT20_SHIFT             (20u)
+#define INTC_ICDISER13_TINT21_SHIFT             (21u)
+#define INTC_ICDISER13_TINT22_SHIFT             (22u)
+#define INTC_ICDISER13_TINT23_SHIFT             (23u)
+#define INTC_ICDISER13_TINT24_SHIFT             (24u)
+#define INTC_ICDISER13_TINT25_SHIFT             (25u)
+#define INTC_ICDISER13_TINT26_SHIFT             (26u)
+#define INTC_ICDISER13_TINT27_SHIFT             (27u)
+#define INTC_ICDISER13_TINT28_SHIFT             (28u)
+#define INTC_ICDISER13_TINT29_SHIFT             (29u)
+#define INTC_ICDISER13_TINT30_SHIFT             (30u)
+#define INTC_ICDISER13_TINT31_SHIFT             (31u)
+
+#define INTC_ICDISER14_TINT32_SHIFT             (0u)
+#define INTC_ICDISER14_TINT33_SHIFT             (1u)
+#define INTC_ICDISER14_TINT34_SHIFT             (2u)
+#define INTC_ICDISER14_TINT35_SHIFT             (3u)
+#define INTC_ICDISER14_TINT36_SHIFT             (4u)
+#define INTC_ICDISER14_TINT37_SHIFT             (5u)
+#define INTC_ICDISER14_TINT38_SHIFT             (6u)
+#define INTC_ICDISER14_TINT39_SHIFT             (7u)
+#define INTC_ICDISER14_TINT40_SHIFT             (8u)
+#define INTC_ICDISER14_TINT41_SHIFT             (9u)
+#define INTC_ICDISER14_TINT42_SHIFT             (10u)
+#define INTC_ICDISER14_TINT43_SHIFT             (11u)
+#define INTC_ICDISER14_TINT44_SHIFT             (12u)
+#define INTC_ICDISER14_TINT45_SHIFT             (13u)
+#define INTC_ICDISER14_TINT46_SHIFT             (14u)
+#define INTC_ICDISER14_TINT47_SHIFT             (15u)
+#define INTC_ICDISER14_TINT48_SHIFT             (16u)
+#define INTC_ICDISER14_TINT49_SHIFT             (17u)
+#define INTC_ICDISER14_TINT50_SHIFT             (18u)
+#define INTC_ICDISER14_TINT51_SHIFT             (19u)
+#define INTC_ICDISER14_TINT52_SHIFT             (20u)
+#define INTC_ICDISER14_TINT53_SHIFT             (21u)
+#define INTC_ICDISER14_TINT54_SHIFT             (22u)
+#define INTC_ICDISER14_TINT55_SHIFT             (23u)
+#define INTC_ICDISER14_TINT56_SHIFT             (24u)
+#define INTC_ICDISER14_TINT57_SHIFT             (25u)
+#define INTC_ICDISER14_TINT58_SHIFT             (26u)
+#define INTC_ICDISER14_TINT59_SHIFT             (27u)
+#define INTC_ICDISER14_TINT60_SHIFT             (28u)
+#define INTC_ICDISER14_TINT61_SHIFT             (29u)
+#define INTC_ICDISER14_TINT62_SHIFT             (30u)
+#define INTC_ICDISER14_TINT63_SHIFT             (31u)
+
+#define INTC_ICDISER15_TINT64_SHIFT             (0u)
+#define INTC_ICDISER15_TINT65_SHIFT             (1u)
+#define INTC_ICDISER15_TINT66_SHIFT             (2u)
+#define INTC_ICDISER15_TINT67_SHIFT             (3u)
+#define INTC_ICDISER15_TINT68_SHIFT             (4u)
+#define INTC_ICDISER15_TINT69_SHIFT             (5u)
+#define INTC_ICDISER15_TINT70_SHIFT             (6u)
+#define INTC_ICDISER15_TINT71_SHIFT             (7u)
+#define INTC_ICDISER15_TINT72_SHIFT             (8u)
+#define INTC_ICDISER15_TINT73_SHIFT             (9u)
+#define INTC_ICDISER15_TINT74_SHIFT             (10u)
+#define INTC_ICDISER15_TINT75_SHIFT             (11u)
+#define INTC_ICDISER15_TINT76_SHIFT             (12u)
+#define INTC_ICDISER15_TINT77_SHIFT             (13u)
+#define INTC_ICDISER15_TINT78_SHIFT             (14u)
+#define INTC_ICDISER15_TINT79_SHIFT             (15u)
+#define INTC_ICDISER15_TINT80_SHIFT             (16u)
+#define INTC_ICDISER15_TINT81_SHIFT             (17u)
+#define INTC_ICDISER15_TINT82_SHIFT             (18u)
+#define INTC_ICDISER15_TINT83_SHIFT             (19u)
+#define INTC_ICDISER15_TINT84_SHIFT             (20u)
+#define INTC_ICDISER15_TINT85_SHIFT             (21u)
+#define INTC_ICDISER15_TINT86_SHIFT             (22u)
+#define INTC_ICDISER15_TINT87_SHIFT             (23u)
+#define INTC_ICDISER15_TINT88_SHIFT             (24u)
+#define INTC_ICDISER15_TINT89_SHIFT             (25u)
+#define INTC_ICDISER15_TINT90_SHIFT             (26u)
+#define INTC_ICDISER15_TINT91_SHIFT             (27u)
+#define INTC_ICDISER15_TINT92_SHIFT             (28u)
+#define INTC_ICDISER15_TINT93_SHIFT             (29u)
+#define INTC_ICDISER15_TINT94_SHIFT             (30u)
+#define INTC_ICDISER15_TINT95_SHIFT             (31u)
+
+#define INTC_ICDISER16_TINT96_SHIFT             (0u)
+#define INTC_ICDISER16_TINT97_SHIFT             (1u)
+#define INTC_ICDISER16_TINT98_SHIFT             (2u)
+#define INTC_ICDISER16_TINT99_SHIFT             (3u)
+#define INTC_ICDISER16_TINT100_SHIFT            (4u)
+#define INTC_ICDISER16_TINT101_SHIFT            (5u)
+#define INTC_ICDISER16_TINT102_SHIFT            (6u)
+#define INTC_ICDISER16_TINT103_SHIFT            (7u)
+#define INTC_ICDISER16_TINT104_SHIFT            (8u)
+#define INTC_ICDISER16_TINT105_SHIFT            (9u)
+#define INTC_ICDISER16_TINT106_SHIFT            (10u)
+#define INTC_ICDISER16_TINT107_SHIFT            (11u)
+#define INTC_ICDISER16_TINT108_SHIFT            (12u)
+#define INTC_ICDISER16_TINT109_SHIFT            (13u)
+#define INTC_ICDISER16_TINT110_SHIFT            (14u)
+#define INTC_ICDISER16_TINT111_SHIFT            (15u)
+#define INTC_ICDISER16_TINT112_SHIFT            (16u)
+#define INTC_ICDISER16_TINT113_SHIFT            (17u)
+#define INTC_ICDISER16_TINT114_SHIFT            (18u)
+#define INTC_ICDISER16_TINT115_SHIFT            (19u)
+#define INTC_ICDISER16_TINT116_SHIFT            (20u)
+#define INTC_ICDISER16_TINT117_SHIFT            (21u)
+#define INTC_ICDISER16_TINT118_SHIFT            (22u)
+#define INTC_ICDISER16_TINT119_SHIFT            (23u)
+#define INTC_ICDISER16_TINT120_SHIFT            (24u)
+#define INTC_ICDISER16_TINT121_SHIFT            (25u)
+#define INTC_ICDISER16_TINT122_SHIFT            (26u)
+#define INTC_ICDISER16_TINT123_SHIFT            (27u)
+#define INTC_ICDISER16_TINT124_SHIFT            (28u)
+#define INTC_ICDISER16_TINT125_SHIFT            (29u)
+#define INTC_ICDISER16_TINT126_SHIFT            (30u)
+#define INTC_ICDISER16_TINT127_SHIFT            (31u)
+
+#define INTC_ICDISER17_TINT128_SHIFT            (0u)
+#define INTC_ICDISER17_TINT129_SHIFT            (1u)
+#define INTC_ICDISER17_TINT130_SHIFT            (2u)
+#define INTC_ICDISER17_TINT131_SHIFT            (3u)
+#define INTC_ICDISER17_TINT132_SHIFT            (4u)
+#define INTC_ICDISER17_TINT133_SHIFT            (5u)
+#define INTC_ICDISER17_TINT134_SHIFT            (6u)
+#define INTC_ICDISER17_TINT135_SHIFT            (7u)
+#define INTC_ICDISER17_TINT136_SHIFT            (8u)
+#define INTC_ICDISER17_TINT137_SHIFT            (9u)
+#define INTC_ICDISER17_TINT138_SHIFT            (10u)
+#define INTC_ICDISER17_TINT139_SHIFT            (11u)
+#define INTC_ICDISER17_TINT140_SHIFT            (12u)
+#define INTC_ICDISER17_TINT141_SHIFT            (13u)
+#define INTC_ICDISER17_TINT142_SHIFT            (14u)
+#define INTC_ICDISER17_TINT143_SHIFT            (15u)
+#define INTC_ICDISER17_TINT144_SHIFT            (16u)
+#define INTC_ICDISER17_TINT145_SHIFT            (17u)
+#define INTC_ICDISER17_TINT146_SHIFT            (18u)
+#define INTC_ICDISER17_TINT147_SHIFT            (19u)
+#define INTC_ICDISER17_TINT148_SHIFT            (20u)
+#define INTC_ICDISER17_TINT149_SHIFT            (21u)
+#define INTC_ICDISER17_TINT150_SHIFT            (22u)
+#define INTC_ICDISER17_TINT151_SHIFT            (23u)
+#define INTC_ICDISER17_TINT152_SHIFT            (24u)
+#define INTC_ICDISER17_TINT153_SHIFT            (25u)
+#define INTC_ICDISER17_TINT154_SHIFT            (26u)
+#define INTC_ICDISER17_TINT155_SHIFT            (27u)
+#define INTC_ICDISER17_TINT156_SHIFT            (28u)
+#define INTC_ICDISER17_TINT157_SHIFT            (29u)
+#define INTC_ICDISER17_TINT158_SHIFT            (30u)
+#define INTC_ICDISER17_TINT159_SHIFT            (31u)
+
+#define INTC_ICDISER18_TINT160_SHIFT            (0u)
+#define INTC_ICDISER18_TINT161_SHIFT            (1u)
+#define INTC_ICDISER18_TINT162_SHIFT            (2u)
+#define INTC_ICDISER18_TINT163_SHIFT            (3u)
+#define INTC_ICDISER18_TINT164_SHIFT            (4u)
+#define INTC_ICDISER18_TINT165_SHIFT            (5u)
+#define INTC_ICDISER18_TINT166_SHIFT            (6u)
+#define INTC_ICDISER18_TINT167_SHIFT            (7u)
+#define INTC_ICDISER18_TINT168_SHIFT            (8u)
+#define INTC_ICDISER18_TINT169_SHIFT            (9u)
+#define INTC_ICDISER18_TINT170_SHIFT            (10u)
+
+#define INTC_ICDICER0_SW0_SHIFT                 (0u)
+#define INTC_ICDICER0_SW1_SHIFT                 (1u)
+#define INTC_ICDICER0_SW2_SHIFT                 (2u)
+#define INTC_ICDICER0_SW3_SHIFT                 (3u)
+#define INTC_ICDICER0_SW4_SHIFT                 (4u)
+#define INTC_ICDICER0_SW5_SHIFT                 (5u)
+#define INTC_ICDICER0_SW6_SHIFT                 (6u)
+#define INTC_ICDICER0_SW7_SHIFT                 (7u)
+#define INTC_ICDICER0_SW8_SHIFT                 (8u)
+#define INTC_ICDICER0_SW9_SHIFT                 (9u)
+#define INTC_ICDICER0_SW10_SHIFT                (10u)
+#define INTC_ICDICER0_SW11_SHIFT                (11u)
+#define INTC_ICDICER0_SW12_SHIFT                (12u)
+#define INTC_ICDICER0_SW13_SHIFT                (13u)
+#define INTC_ICDICER0_SW14_SHIFT                (14u)
+#define INTC_ICDICER0_SW15_SHIFT                (15u)
+#define INTC_ICDICER0_PMUIRQ0_SHIFT             (16u)
+#define INTC_ICDICER0_COMMRX0_SHIFT             (17u)
+#define INTC_ICDICER0_COMMTX0_SHIFT             (18u)
+#define INTC_ICDICER0_CTIIRQ0_SHIFT             (19u)
+
+#define INTC_ICDICER1_IRQ0_SHIFT                (0u)
+#define INTC_ICDICER1_IRQ1_SHIFT                (1u)
+#define INTC_ICDICER1_IRQ2_SHIFT                (2u)
+#define INTC_ICDICER1_IRQ3_SHIFT                (3u)
+#define INTC_ICDICER1_IRQ4_SHIFT                (4u)
+#define INTC_ICDICER1_IRQ5_SHIFT                (5u)
+#define INTC_ICDICER1_IRQ6_SHIFT                (6u)
+#define INTC_ICDICER1_IRQ7_SHIFT                (7u)
+#define INTC_ICDICER1_PL310ERR_SHIFT            (8u)
+#define INTC_ICDICER1_DMAINT0_SHIFT             (9u)
+#define INTC_ICDICER1_DMAINT1_SHIFT             (10u)
+#define INTC_ICDICER1_DMAINT2_SHIFT             (11u)
+#define INTC_ICDICER1_DMAINT3_SHIFT             (12u)
+#define INTC_ICDICER1_DMAINT4_SHIFT             (13u)
+#define INTC_ICDICER1_DMAINT5_SHIFT             (14u)
+#define INTC_ICDICER1_DMAINT6_SHIFT             (15u)
+#define INTC_ICDICER1_DMAINT7_SHIFT             (16u)
+#define INTC_ICDICER1_DMAINT8_SHIFT             (17u)
+#define INTC_ICDICER1_DMAINT9_SHIFT             (18u)
+#define INTC_ICDICER1_DMAINT10_SHIFT            (19u)
+#define INTC_ICDICER1_DMAINT11_SHIFT            (20u)
+#define INTC_ICDICER1_DMAINT12_SHIFT            (21u)
+#define INTC_ICDICER1_DMAINT13_SHIFT            (22u)
+#define INTC_ICDICER1_DMAINT14_SHIFT            (23u)
+#define INTC_ICDICER1_DMAINT15_SHIFT            (24u)
+#define INTC_ICDICER1_DMAERR_SHIFT              (25u)
+
+#define INTC_ICDICER2_USBI0_SHIFT               (9u)
+#define INTC_ICDICER2_USBI1_SHIFT               (10u)
+#define INTC_ICDICER2_S0_VI_VSYNC0_SHIFT        (11u)
+#define INTC_ICDICER2_S0_LO_VSYNC0_SHIFT        (12u)
+#define INTC_ICDICER2_S0_VSYNCERR0_SHIFT        (13u)
+#define INTC_ICDICER2_GR3_VLINE0_SHIFT          (14u)
+#define INTC_ICDICER2_S0_VFIELD0_SHIFT          (15u)
+#define INTC_ICDICER2_IV1_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDICER2_IV3_VBUFERR0_SHIFT        (17u)
+#define INTC_ICDICER2_IV5_VBUFERR0_SHIFT        (18u)
+#define INTC_ICDICER2_IV6_VBUFERR0_SHIFT        (19u)
+#define INTC_ICDICER2_S0_WLINE0_SHIFT           (20u)
+#define INTC_ICDICER2_S1_VI_VSYNC0_SHIFT        (21u)
+#define INTC_ICDICER2_S1_LO_VSYNC0_SHIFT        (22u)
+#define INTC_ICDICER2_S1_VSYNCERR0_SHIFT        (23u)
+#define INTC_ICDICER2_S1_VFIELD0_SHIFT          (24u)
+#define INTC_ICDICER2_IV2_VBUFERR0_SHIFT        (25u)
+#define INTC_ICDICER2_IV4_VBUFERR0_SHIFT        (26u)
+#define INTC_ICDICER2_S1_WLINE0_SHIFT           (27u)
+#define INTC_ICDICER2_OIR_VI_VSYNC0_SHIFT       (28u)
+#define INTC_ICDICER2_OIR_LO_VSYNC0_SHIFT       (29u)
+#define INTC_ICDICER2_OIR_VSYNCERR0_SHIFT       (30u)
+#define INTC_ICDICER2_OIR_VFIELD0_SHIFT         (31u)
+
+#define INTC_ICDICER3_IV7_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDICER3_IV8_VBUFERR0_SHIFT        (1u)
+#define INTC_ICDICER3_S0_VI_VSYNC1_SHIFT        (3u)
+#define INTC_ICDICER3_S0_LO_VSYNC1_SHIFT        (4u)
+#define INTC_ICDICER3_S0_VSYNCERR1_SHIFT        (5u)
+#define INTC_ICDICER3_GR3_VLINE1_SHIFT          (6u)
+#define INTC_ICDICER3_S0_VFIELD1_SHIFT          (7u)
+#define INTC_ICDICER3_IV1_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDICER3_IV3_VBUFERR1_SHIFT        (9u)
+#define INTC_ICDICER3_IV5_VBUFERR1_SHIFT        (10u)
+#define INTC_ICDICER3_IV6_VBUFERR1_SHIFT        (11u)
+#define INTC_ICDICER3_S0_WLINE1_SHIFT           (12u)
+#define INTC_ICDICER3_S1_VI_VSYNC1_SHIFT        (13u)
+#define INTC_ICDICER3_S1_LO_VSYNC1_SHIFT        (14u)
+#define INTC_ICDICER3_S1_VSYNCERR1_SHIFT        (15u)
+#define INTC_ICDICER3_S1_VFIELD1_SHIFT          (16u)
+#define INTC_ICDICER3_IV2_VBUFERR1_SHIFT        (17u)
+#define INTC_ICDICER3_IV4_VBUFERR1_SHIFT        (18u)
+#define INTC_ICDICER3_S1_WLINE1_SHIFT           (19u)
+#define INTC_ICDICER3_OIR_VI_VSYNC1_SHIFT       (20u)
+#define INTC_ICDICER3_OIR_LO_VSYNC1_SHIFT       (21u)
+#define INTC_ICDICER3_OIR_VLINE1_SHIFT          (22u)
+#define INTC_ICDICER3_OIR_VFIELD1_SHIFT         (23u)
+#define INTC_ICDICER3_IV7_VBUFERR1_SHIFT        (24u)
+#define INTC_ICDICER3_IV8_VBUFERR1_SHIFT        (25u)
+#define INTC_ICDICER3_IMRDI_SHIFT               (27u)
+#define INTC_ICDICER3_IMR2I0_SHIFT              (28u)
+#define INTC_ICDICER3_IMR2I1_SHIFT              (29u)
+#define INTC_ICDICER3_JEDI_SHIFT                (30u)
+#define INTC_ICDICER3_JDTI_SHIFT                (31u)
+
+#define INTC_ICDICER4_CMP0_SHIFT                (0u)
+#define INTC_ICDICER4_CMP1_SHIFT                (1u)
+#define INTC_ICDICER4_INT0_SHIFT                (2u)
+#define INTC_ICDICER4_INT1_SHIFT                (3u)
+#define INTC_ICDICER4_INT2_SHIFT                (4u)
+#define INTC_ICDICER4_INT3_SHIFT                (5u)
+#define INTC_ICDICER4_OSTM0TINT_SHIFT           (6u)
+#define INTC_ICDICER4_OSTM1TINT_SHIFT           (7u)
+#define INTC_ICDICER4_CMI_SHIFT                 (8u)
+#define INTC_ICDICER4_WTOUT_SHIFT               (9u)
+#define INTC_ICDICER4_ITI_SHIFT                 (10u)
+#define INTC_ICDICER4_TGI0A_SHIFT               (11u)
+#define INTC_ICDICER4_TGI0B_SHIFT               (12u)
+#define INTC_ICDICER4_TGI0C_SHIFT               (13u)
+#define INTC_ICDICER4_TGI0D_SHIFT               (14u)
+#define INTC_ICDICER4_TGI0V_SHIFT               (15u)
+#define INTC_ICDICER4_TGI0E_SHIFT               (16u)
+#define INTC_ICDICER4_TGI0F_SHIFT               (17u)
+#define INTC_ICDICER4_TGI1A_SHIFT               (18u)
+#define INTC_ICDICER4_TGI1B_SHIFT               (19u)
+#define INTC_ICDICER4_TGI1V_SHIFT               (20u)
+#define INTC_ICDICER4_TGI1U_SHIFT               (21u)
+#define INTC_ICDICER4_TGI2A_SHIFT               (22u)
+#define INTC_ICDICER4_TGI2B_SHIFT               (23u)
+#define INTC_ICDICER4_TGI2V_SHIFT               (24u)
+#define INTC_ICDICER4_TGI2U_SHIFT               (25u)
+#define INTC_ICDICER4_TGI3A_SHIFT               (26u)
+#define INTC_ICDICER4_TGI3B_SHIFT               (27u)
+#define INTC_ICDICER4_TGI3C_SHIFT               (28u)
+#define INTC_ICDICER4_TGI3D_SHIFT               (29u)
+#define INTC_ICDICER4_TGI3V_SHIFT               (30u)
+#define INTC_ICDICER4_TGI4A_SHIFT               (31u)
+
+#define INTC_ICDICER5_TGI4B_SHIFT               (0u)
+#define INTC_ICDICER5_TGI4C_SHIFT               (1u)
+#define INTC_ICDICER5_TGI4D_SHIFT               (2u)
+#define INTC_ICDICER5_TGI4V_SHIFT               (3u)
+#define INTC_ICDICER5_CMI1_SHIFT                (4u)
+#define INTC_ICDICER5_CMI2_SHIFT                (5u)
+#define INTC_ICDICER5_SGDEI0_SHIFT              (6u)
+#define INTC_ICDICER5_SGDEI1_SHIFT              (7u)
+#define INTC_ICDICER5_SGDEI2_SHIFT              (8u)
+#define INTC_ICDICER5_SGDEI3_SHIFT              (9u)
+#define INTC_ICDICER5_ADI_SHIFT                 (10u)
+#define INTC_ICDICER5_LMTI_SHIFT                (11u)
+#define INTC_ICDICER5_SSII0_SHIFT               (12u)
+#define INTC_ICDICER5_SSIRXI0_SHIFT             (13u)
+#define INTC_ICDICER5_SSITXI0_SHIFT             (14u)
+#define INTC_ICDICER5_SSII1_SHIFT               (15u)
+#define INTC_ICDICER5_SSIRXI1_SHIFT             (16u)
+#define INTC_ICDICER5_SSITXI1_SHIFT             (17u)
+#define INTC_ICDICER5_SSII2_SHIFT               (18u)
+#define INTC_ICDICER5_SSIRTI2_SHIFT             (19u)
+#define INTC_ICDICER5_SSII3_SHIFT               (20u)
+#define INTC_ICDICER5_SSIRXI3_SHIFT             (21u)
+#define INTC_ICDICER5_SSITXI3_SHIFT             (22u)
+#define INTC_ICDICER5_SSII4_SHIFT               (23u)
+#define INTC_ICDICER5_SSIRTI4_SHIFT             (24u)
+#define INTC_ICDICER5_SSII5_SHIFT               (25u)
+#define INTC_ICDICER5_SSIRXI5_SHIFT             (26u)
+#define INTC_ICDICER5_SSITXI5_SHIFT             (27u)
+#define INTC_ICDICER5_SPDIFI_SHIFT              (28u)
+#define INTC_ICDICER5_INTIICTEI0_SHIFT          (29u)
+#define INTC_ICDICER5_INTIICRI0_SHIFT           (30u)
+#define INTC_ICDICER5_INTIICTI0_SHIFT           (31u)
+
+#define INTC_ICDICER6_INTIICSPI0_SHIFT          (0u)
+#define INTC_ICDICER6_INTIICSTI0_SHIFT          (1u)
+#define INTC_ICDICER6_INTIICNAKI0_SHIFT         (2u)
+#define INTC_ICDICER6_INTIICALI0_SHIFT          (3u)
+#define INTC_ICDICER6_INTIICTMOI0_SHIFT         (4u)
+#define INTC_ICDICER6_INTIICTEI1_SHIFT          (5u)
+#define INTC_ICDICER6_INTIICRI1_SHIFT           (6u)
+#define INTC_ICDICER6_INTIICTI1_SHIFT           (7u)
+#define INTC_ICDICER6_INTIICSPI1_SHIFT          (8u)
+#define INTC_ICDICER6_INTIICSTI1_SHIFT          (9u)
+#define INTC_ICDICER6_INTIICNAKI1_SHIFT         (10u)
+#define INTC_ICDICER6_INTIICALI1_SHIFT          (11u)
+#define INTC_ICDICER6_INTIICTMOI1_SHIFT         (12u)
+#define INTC_ICDICER6_INTIICTEI2_SHIFT          (13u)
+#define INTC_ICDICER6_INTIICRI2_SHIFT           (14u)
+#define INTC_ICDICER6_INTIICTI2_SHIFT           (15u)
+#define INTC_ICDICER6_INTIICSPI2_SHIFT          (16u)
+#define INTC_ICDICER6_INTIICSTI2_SHIFT          (17u)
+#define INTC_ICDICER6_INTIICNAKI2_SHIFT         (18u)
+#define INTC_ICDICER6_INTIICALI2_SHIFT          (19u)
+#define INTC_ICDICER6_INTIICTMOI2_SHIFT         (20u)
+#define INTC_ICDICER6_INTIICTEI3_SHIFT          (21u)
+#define INTC_ICDICER6_INTIICRI3_SHIFT           (22u)
+#define INTC_ICDICER6_INTIICTI3_SHIFT           (23u)
+#define INTC_ICDICER6_INTIICSPI3_SHIFT          (24u)
+#define INTC_ICDICER6_INTIICSTI3_SHIFT          (25u)
+#define INTC_ICDICER6_INTIICNAKI3_SHIFT         (26u)
+#define INTC_ICDICER6_INTIICALI3_SHIFT          (27u)
+#define INTC_ICDICER6_INTIICTMOI3_SHIFT         (28u)
+#define INTC_ICDICER6_BRI0_SHIFT                (29u)
+#define INTC_ICDICER6_ERI0_SHIFT                (30u)
+#define INTC_ICDICER6_RXI0_SHIFT                (31u)
+
+#define INTC_ICDICER7_TXI0_SHIFT                (0u)
+#define INTC_ICDICER7_BRI1_SHIFT                (1u)
+#define INTC_ICDICER7_ERI1_SHIFT                (2u)
+#define INTC_ICDICER7_RXI1_SHIFT                (3u)
+#define INTC_ICDICER7_TXI1_SHIFT                (4u)
+#define INTC_ICDICER7_BRI2_SHIFT                (5u)
+#define INTC_ICDICER7_ERI2_SHIFT                (6u)
+#define INTC_ICDICER7_RXI2_SHIFT                (7u)
+#define INTC_ICDICER7_TXI2_SHIFT                (8u)
+#define INTC_ICDICER7_BRI3_SHIFT                (9u)
+#define INTC_ICDICER7_ERI3_SHIFT                (10u)
+#define INTC_ICDICER7_RXI3_SHIFT                (11u)
+#define INTC_ICDICER7_TXI3_SHIFT                (12u)
+#define INTC_ICDICER7_BRI4_SHIFT                (13u)
+#define INTC_ICDICER7_ERI4_SHIFT                (14u)
+#define INTC_ICDICER7_RXI4_SHIFT                (15u)
+#define INTC_ICDICER7_TXI4_SHIFT                (16u)
+#define INTC_ICDICER7_BRI5_SHIFT                (17u)
+#define INTC_ICDICER7_ERI5_SHIFT                (18u)
+#define INTC_ICDICER7_RXI5_SHIFT                (19u)
+#define INTC_ICDICER7_TXI5_SHIFT                (20u)
+#define INTC_ICDICER7_BRI6_SHIFT                (21u)
+#define INTC_ICDICER7_ERI6_SHIFT                (22u)
+#define INTC_ICDICER7_RXI6_SHIFT                (23u)
+#define INTC_ICDICER7_TXI6_SHIFT                (24u)
+#define INTC_ICDICER7_BRI7_SHIFT                (25u)
+#define INTC_ICDICER7_ERI7_SHIFT                (26u)
+#define INTC_ICDICER7_RXI7_SHIFT                (27u)
+#define INTC_ICDICER7_TXI7_SHIFT                (28u)
+#define INTC_ICDICER7_INTRCANGERR_SHIFT         (29u)
+#define INTC_ICDICER7_INTRCANGRECC_SHIFT        (30u)
+#define INTC_ICDICER7_INTRCAN0REC_SHIFT         (31u)
+
+#define INTC_ICDICER8_INTRCAN0ERR_SHIFT         (0u)
+#define INTC_ICDICER8_INTRCAN0TRX_SHIFT         (1u)
+#define INTC_ICDICER8_INTRCAN1REC_SHIFT         (2u)
+#define INTC_ICDICER8_INTRCAN1ERR_SHIFT         (3u)
+#define INTC_ICDICER8_INTRCAN1TRX_SHIFT         (4u)
+#define INTC_ICDICER8_INTRCAN2REC_SHIFT         (5u)
+#define INTC_ICDICER8_INTRCAN2ERR_SHIFT         (6u)
+#define INTC_ICDICER8_INTRCAN2TRX_SHIFT         (7u)
+#define INTC_ICDICER8_INTRCAN3REC_SHIFT         (8u)
+#define INTC_ICDICER8_INTRCAN3ERR_SHIFT         (9u)
+#define INTC_ICDICER8_INTRCAN3TRX_SHIFT         (10u)
+#define INTC_ICDICER8_INTRCAN4REC_SHIFT         (11u)
+#define INTC_ICDICER8_INTRCAN4ERR_SHIFT         (12u)
+#define INTC_ICDICER8_INTRCAN4TRX_SHIFT         (13u)
+#define INTC_ICDICER8_SPEI0_SHIFT               (14u)
+#define INTC_ICDICER8_SPRI0_SHIFT               (15u)
+#define INTC_ICDICER8_SPTI0_SHIFT               (16u)
+#define INTC_ICDICER8_SPEI1_SHIFT               (17u)
+#define INTC_ICDICER8_SPRI1_SHIFT               (18u)
+#define INTC_ICDICER8_SPTI1_SHIFT               (19u)
+#define INTC_ICDICER8_SPEI2_SHIFT               (20u)
+#define INTC_ICDICER8_SPRI2_SHIFT               (21u)
+#define INTC_ICDICER8_SPTI2_SHIFT               (22u)
+#define INTC_ICDICER8_SPEI3_SHIFT               (23u)
+#define INTC_ICDICER8_SPRI3_SHIFT               (24u)
+#define INTC_ICDICER8_SPTI3_SHIFT               (25u)
+#define INTC_ICDICER8_SPEI4_SHIFT               (26u)
+#define INTC_ICDICER8_SPRI4_SHIFT               (27u)
+#define INTC_ICDICER8_SPTI4_SHIFT               (28u)
+#define INTC_ICDICER8_IEBBTD_SHIFT              (29u)
+#define INTC_ICDICER8_IEBBTERR_SHIFT            (30u)
+#define INTC_ICDICER8_IEBBTSTA_SHIFT            (31u)
+
+#define INTC_ICDICER9_IEBBTV_SHIFT              (0u)
+#define INTC_ICDICER9_ISY_SHIFT                 (1u)
+#define INTC_ICDICER9_IERR_SHIFT                (2u)
+#define INTC_ICDICER9_ITARG_SHIFT               (3u)
+#define INTC_ICDICER9_ISEC_SHIFT                (4u)
+#define INTC_ICDICER9_IBUF_SHIFT                (5u)
+#define INTC_ICDICER9_IREADY_SHIFT              (6u)
+#define INTC_ICDICER9_FLSTE_SHIFT               (7u)
+#define INTC_ICDICER9_FLTENDI_SHIFT             (8u)
+#define INTC_ICDICER9_FLTREQ0I_SHIFT            (9u)
+#define INTC_ICDICER9_FLTREQ1I_SHIFT            (10u)
+#define INTC_ICDICER9_MMC0_SHIFT                (11u)
+#define INTC_ICDICER9_MMC1_SHIFT                (12u)
+#define INTC_ICDICER9_MMC2_SHIFT                (13u)
+#define INTC_ICDICER9_SDHI0_3_SHIFT             (14u)
+#define INTC_ICDICER9_SDHI0_0_SHIFT             (15u)
+#define INTC_ICDICER9_SDHI0_1_SHIFT             (16u)
+#define INTC_ICDICER9_SDHI1_3_SHIFT             (17u)
+#define INTC_ICDICER9_SDHI1_0_SHIFT             (18u)
+#define INTC_ICDICER9_SDHI1_1_SHIFT             (19u)
+#define INTC_ICDICER9_ARM_SHIFT                 (20u)
+#define INTC_ICDICER9_PRD_SHIFT                 (21u)
+#define INTC_ICDICER9_CUP_SHIFT                 (22u)
+#define INTC_ICDICER9_SCUAI0_SHIFT              (23u)
+#define INTC_ICDICER9_SCUAI1_SHIFT              (24u)
+#define INTC_ICDICER9_SCUFDI0_SHIFT             (25u)
+#define INTC_ICDICER9_SCUFDI1_SHIFT             (26u)
+#define INTC_ICDICER9_SCUFDI2_SHIFT             (27u)
+#define INTC_ICDICER9_SCUFDI3_SHIFT             (28u)
+#define INTC_ICDICER9_SCUFUI0_SHIFT             (29u)
+#define INTC_ICDICER9_SCUFUI1_SHIFT             (30u)
+#define INTC_ICDICER9_SCUFUI2_SHIFT             (31u)
+
+#define INTC_ICDICER10_SCUFUI3_SHIFT            (0u)
+#define INTC_ICDICER10_SCUDVI0_SHIFT            (1u)
+#define INTC_ICDICER10_SCUDVI1_SHIFT            (2u)
+#define INTC_ICDICER10_SCUDVI2_SHIFT            (3u)
+#define INTC_ICDICER10_SCUDVI3_SHIFT            (4u)
+#define INTC_ICDICER10_MLB_CINT_SHIFT           (5u)
+#define INTC_ICDICER10_MLB_SINT_SHIFT           (6u)
+#define INTC_ICDICER10_DRC0_SHIFT               (7u)
+#define INTC_ICDICER10_DRC1_SHIFT               (8u)
+#define INTC_ICDICER10_LINI0_INT_T_SHIFT        (11u)
+#define INTC_ICDICER10_LINI0_INT_R_SHIFT        (12u)
+#define INTC_ICDICER10_LINI0_INT_S_SHIFT        (13u)
+#define INTC_ICDICER10_LINI0_INT_M_SHIFT        (14u)
+#define INTC_ICDICER10_LINI1_INT_T_SHIFT        (15u)
+#define INTC_ICDICER10_LINI1_INT_R_SHIFT        (16u)
+#define INTC_ICDICER10_LINI1_INT_S_SHIFT        (17u)
+#define INTC_ICDICER10_LINI1_INT_M_SHIFT        (18u)
+#define INTC_ICDICER10_ERI0_SHIFT               (27u)
+#define INTC_ICDICER10_RXI0_SHIFT               (28u)
+#define INTC_ICDICER10_TXI0_SHIFT               (29u)
+#define INTC_ICDICER10_TEI0_SHIFT               (30u)
+#define INTC_ICDICER10_ERI1_SHIFT               (31u)
+
+#define INTC_ICDICER11_RXI1_SHIFT               (0u)
+#define INTC_ICDICER11_TXI1_SHIFT               (1u)
+#define INTC_ICDICER11_TEI1_SHIFT               (2u)
+#define INTC_ICDICER11_AVBI_DATA_SHIFT          (3u)
+#define INTC_ICDICER11_AVBI_ERROR_SHIFT         (4u)
+#define INTC_ICDICER11_AVBI_MANAGE_SHIFT        (5u)
+#define INTC_ICDICER11_AVBI_MAC_SHIFT           (6u)
+#define INTC_ICDICER11_ETHERI_SHIFT             (7u)
+#define INTC_ICDICER11_CEUI_SHIFT               (12u)
+#define INTC_ICDICER11_H2XMLB_ERRINT_SHIFT      (29u)
+#define INTC_ICDICER11_H2XIC1_ERRINT_SHIFT      (30u)
+#define INTC_ICDICER11_X2HPERI1_ERRINT_SHIFT    (31u)
+
+#define INTC_ICDICER12_X2HPERI2_ERRINT_SHIFT    (0u)
+#define INTC_ICDICER12_X2HPERI34_ERRINT_SHIFT   (1u)
+#define INTC_ICDICER12_X2HPERI5_ERRINT_SHIFT    (2u)
+#define INTC_ICDICER12_X2HPERI67_ERRINT_SHIFT   (3u)
+#define INTC_ICDICER12_X2HDBGR_ERRINT_SHIFT     (4u)
+#define INTC_ICDICER12_X2HBSC_ERRINT_SHIFT      (5u)
+#define INTC_ICDICER12_X2HSPI1_ERRINT_SHIFT     (6u)
+#define INTC_ICDICER12_X2HSPI2_ERRINT_SHIFT     (7u)
+#define INTC_ICDICER12_PRRI_SHIFT               (8u)
+#define INTC_ICDICER12_IFEI0_SHIFT              (9u)
+#define INTC_ICDICER12_OFFI0_SHIFT              (10u)
+#define INTC_ICDICER12_PFVEI0_SHIFT             (11u)
+#define INTC_ICDICER12_IFEI1_SHIFT              (12u)
+#define INTC_ICDICER12_OFFI1_SHIFT              (13u)
+#define INTC_ICDICER12_PFVEI1_SHIFT             (14u)
+
+#define INTC_ICDICER13_TINT0_SHIFT              (0u)
+#define INTC_ICDICER13_TINT1_SHIFT              (1u)
+#define INTC_ICDICER13_TINT2_SHIFT              (2u)
+#define INTC_ICDICER13_TINT3_SHIFT              (3u)
+#define INTC_ICDICER13_TINT4_SHIFT              (4u)
+#define INTC_ICDICER13_TINT5_SHIFT              (5u)
+#define INTC_ICDICER13_TINT6_SHIFT              (6u)
+#define INTC_ICDICER13_TINT7_SHIFT              (7u)
+#define INTC_ICDICER13_TINT8_SHIFT              (8u)
+#define INTC_ICDICER13_TINT9_SHIFT              (9u)
+#define INTC_ICDICER13_TINT10_SHIFT             (10u)
+#define INTC_ICDICER13_TINT11_SHIFT             (11u)
+#define INTC_ICDICER13_TINT12_SHIFT             (12u)
+#define INTC_ICDICER13_TINT13_SHIFT             (13u)
+#define INTC_ICDICER13_TINT14_SHIFT             (14u)
+#define INTC_ICDICER13_TINT15_SHIFT             (15u)
+#define INTC_ICDICER13_TINT16_SHIFT             (16u)
+#define INTC_ICDICER13_TINT17_SHIFT             (17u)
+#define INTC_ICDICER13_TINT18_SHIFT             (18u)
+#define INTC_ICDICER13_TINT19_SHIFT             (19u)
+#define INTC_ICDICER13_TINT20_SHIFT             (20u)
+#define INTC_ICDICER13_TINT21_SHIFT             (21u)
+#define INTC_ICDICER13_TINT22_SHIFT             (22u)
+#define INTC_ICDICER13_TINT23_SHIFT             (23u)
+#define INTC_ICDICER13_TINT24_SHIFT             (24u)
+#define INTC_ICDICER13_TINT25_SHIFT             (25u)
+#define INTC_ICDICER13_TINT26_SHIFT             (26u)
+#define INTC_ICDICER13_TINT27_SHIFT             (27u)
+#define INTC_ICDICER13_TINT28_SHIFT             (28u)
+#define INTC_ICDICER13_TINT29_SHIFT             (29u)
+#define INTC_ICDICER13_TINT30_SHIFT             (30u)
+#define INTC_ICDICER13_TINT31_SHIFT             (31u)
+
+#define INTC_ICDICER14_TINT32_SHIFT             (0u)
+#define INTC_ICDICER14_TINT33_SHIFT             (1u)
+#define INTC_ICDICER14_TINT34_SHIFT             (2u)
+#define INTC_ICDICER14_TINT35_SHIFT             (3u)
+#define INTC_ICDICER14_TINT36_SHIFT             (4u)
+#define INTC_ICDICER14_TINT37_SHIFT             (5u)
+#define INTC_ICDICER14_TINT38_SHIFT             (6u)
+#define INTC_ICDICER14_TINT39_SHIFT             (7u)
+#define INTC_ICDICER14_TINT40_SHIFT             (8u)
+#define INTC_ICDICER14_TINT41_SHIFT             (9u)
+#define INTC_ICDICER14_TINT42_SHIFT             (10u)
+#define INTC_ICDICER14_TINT43_SHIFT             (11u)
+#define INTC_ICDICER14_TINT44_SHIFT             (12u)
+#define INTC_ICDICER14_TINT45_SHIFT             (13u)
+#define INTC_ICDICER14_TINT46_SHIFT             (14u)
+#define INTC_ICDICER14_TINT47_SHIFT             (15u)
+#define INTC_ICDICER14_TINT48_SHIFT             (16u)
+#define INTC_ICDICER14_TINT49_SHIFT             (17u)
+#define INTC_ICDICER14_TINT50_SHIFT             (18u)
+#define INTC_ICDICER14_TINT51_SHIFT             (19u)
+#define INTC_ICDICER14_TINT52_SHIFT             (20u)
+#define INTC_ICDICER14_TINT53_SHIFT             (21u)
+#define INTC_ICDICER14_TINT54_SHIFT             (22u)
+#define INTC_ICDICER14_TINT55_SHIFT             (23u)
+#define INTC_ICDICER14_TINT56_SHIFT             (24u)
+#define INTC_ICDICER14_TINT57_SHIFT             (25u)
+#define INTC_ICDICER14_TINT58_SHIFT             (26u)
+#define INTC_ICDICER14_TINT59_SHIFT             (27u)
+#define INTC_ICDICER14_TINT60_SHIFT             (28u)
+#define INTC_ICDICER14_TINT61_SHIFT             (29u)
+#define INTC_ICDICER14_TINT62_SHIFT             (30u)
+#define INTC_ICDICER14_TINT63_SHIFT             (31u)
+
+#define INTC_ICDICER15_TINT64_SHIFT             (0u)
+#define INTC_ICDICER15_TINT65_SHIFT             (1u)
+#define INTC_ICDICER15_TINT66_SHIFT             (2u)
+#define INTC_ICDICER15_TINT67_SHIFT             (3u)
+#define INTC_ICDICER15_TINT68_SHIFT             (4u)
+#define INTC_ICDICER15_TINT69_SHIFT             (5u)
+#define INTC_ICDICER15_TINT70_SHIFT             (6u)
+#define INTC_ICDICER15_TINT71_SHIFT             (7u)
+#define INTC_ICDICER15_TINT72_SHIFT             (8u)
+#define INTC_ICDICER15_TINT73_SHIFT             (9u)
+#define INTC_ICDICER15_TINT74_SHIFT             (10u)
+#define INTC_ICDICER15_TINT75_SHIFT             (11u)
+#define INTC_ICDICER15_TINT76_SHIFT             (12u)
+#define INTC_ICDICER15_TINT77_SHIFT             (13u)
+#define INTC_ICDICER15_TINT78_SHIFT             (14u)
+#define INTC_ICDICER15_TINT79_SHIFT             (15u)
+#define INTC_ICDICER15_TINT80_SHIFT             (16u)
+#define INTC_ICDICER15_TINT81_SHIFT             (17u)
+#define INTC_ICDICER15_TINT82_SHIFT             (18u)
+#define INTC_ICDICER15_TINT83_SHIFT             (19u)
+#define INTC_ICDICER15_TINT84_SHIFT             (20u)
+#define INTC_ICDICER15_TINT85_SHIFT             (21u)
+#define INTC_ICDICER15_TINT86_SHIFT             (22u)
+#define INTC_ICDICER15_TINT87_SHIFT             (23u)
+#define INTC_ICDICER15_TINT88_SHIFT             (24u)
+#define INTC_ICDICER15_TINT89_SHIFT             (25u)
+#define INTC_ICDICER15_TINT90_SHIFT             (26u)
+#define INTC_ICDICER15_TINT91_SHIFT             (27u)
+#define INTC_ICDICER15_TINT92_SHIFT             (28u)
+#define INTC_ICDICER15_TINT93_SHIFT             (29u)
+#define INTC_ICDICER15_TINT94_SHIFT             (30u)
+#define INTC_ICDICER15_TINT95_SHIFT             (31u)
+
+#define INTC_ICDICER16_TINT96_SHIFT             (0u)
+#define INTC_ICDICER16_TINT97_SHIFT             (1u)
+#define INTC_ICDICER16_TINT98_SHIFT             (2u)
+#define INTC_ICDICER16_TINT99_SHIFT             (3u)
+#define INTC_ICDICER16_TINT100_SHIFT            (4u)
+#define INTC_ICDICER16_TINT101_SHIFT            (5u)
+#define INTC_ICDICER16_TINT102_SHIFT            (6u)
+#define INTC_ICDICER16_TINT103_SHIFT            (7u)
+#define INTC_ICDICER16_TINT104_SHIFT            (8u)
+#define INTC_ICDICER16_TINT105_SHIFT            (9u)
+#define INTC_ICDICER16_TINT106_SHIFT            (10u)
+#define INTC_ICDICER16_TINT107_SHIFT            (11u)
+#define INTC_ICDICER16_TINT108_SHIFT            (12u)
+#define INTC_ICDICER16_TINT109_SHIFT            (13u)
+#define INTC_ICDICER16_TINT110_SHIFT            (14u)
+#define INTC_ICDICER16_TINT111_SHIFT            (15u)
+#define INTC_ICDICER16_TINT112_SHIFT            (16u)
+#define INTC_ICDICER16_TINT113_SHIFT            (17u)
+#define INTC_ICDICER16_TINT114_SHIFT            (18u)
+#define INTC_ICDICER16_TINT115_SHIFT            (19u)
+#define INTC_ICDICER16_TINT116_SHIFT            (20u)
+#define INTC_ICDICER16_TINT117_SHIFT            (21u)
+#define INTC_ICDICER16_TINT118_SHIFT            (22u)
+#define INTC_ICDICER16_TINT119_SHIFT            (23u)
+#define INTC_ICDICER16_TINT120_SHIFT            (24u)
+#define INTC_ICDICER16_TINT121_SHIFT            (25u)
+#define INTC_ICDICER16_TINT122_SHIFT            (26u)
+#define INTC_ICDICER16_TINT123_SHIFT            (27u)
+#define INTC_ICDICER16_TINT124_SHIFT            (28u)
+#define INTC_ICDICER16_TINT125_SHIFT            (29u)
+#define INTC_ICDICER16_TINT126_SHIFT            (30u)
+#define INTC_ICDICER16_TINT127_SHIFT            (31u)
+
+#define INTC_ICDICER17_TINT128_SHIFT            (0u)
+#define INTC_ICDICER17_TINT129_SHIFT            (1u)
+#define INTC_ICDICER17_TINT130_SHIFT            (2u)
+#define INTC_ICDICER17_TINT131_SHIFT            (3u)
+#define INTC_ICDICER17_TINT132_SHIFT            (4u)
+#define INTC_ICDICER17_TINT133_SHIFT            (5u)
+#define INTC_ICDICER17_TINT134_SHIFT            (6u)
+#define INTC_ICDICER17_TINT135_SHIFT            (7u)
+#define INTC_ICDICER17_TINT136_SHIFT            (8u)
+#define INTC_ICDICER17_TINT137_SHIFT            (9u)
+#define INTC_ICDICER17_TINT138_SHIFT            (10u)
+#define INTC_ICDICER17_TINT139_SHIFT            (11u)
+#define INTC_ICDICER17_TINT140_SHIFT            (12u)
+#define INTC_ICDICER17_TINT141_SHIFT            (13u)
+#define INTC_ICDICER17_TINT142_SHIFT            (14u)
+#define INTC_ICDICER17_TINT143_SHIFT            (15u)
+#define INTC_ICDICER17_TINT144_SHIFT            (16u)
+#define INTC_ICDICER17_TINT145_SHIFT            (17u)
+#define INTC_ICDICER17_TINT146_SHIFT            (18u)
+#define INTC_ICDICER17_TINT147_SHIFT            (19u)
+#define INTC_ICDICER17_TINT148_SHIFT            (20u)
+#define INTC_ICDICER17_TINT149_SHIFT            (21u)
+#define INTC_ICDICER17_TINT150_SHIFT            (22u)
+#define INTC_ICDICER17_TINT151_SHIFT            (23u)
+#define INTC_ICDICER17_TINT152_SHIFT            (24u)
+#define INTC_ICDICER17_TINT153_SHIFT            (25u)
+#define INTC_ICDICER17_TINT154_SHIFT            (26u)
+#define INTC_ICDICER17_TINT155_SHIFT            (27u)
+#define INTC_ICDICER17_TINT156_SHIFT            (28u)
+#define INTC_ICDICER17_TINT157_SHIFT            (29u)
+#define INTC_ICDICER17_TINT158_SHIFT            (30u)
+#define INTC_ICDICER17_TINT159_SHIFT            (31u)
+
+#define INTC_ICDICER18_TINT160_SHIFT            (0u)
+#define INTC_ICDICER18_TINT161_SHIFT            (1u)
+#define INTC_ICDICER18_TINT162_SHIFT            (2u)
+#define INTC_ICDICER18_TINT163_SHIFT            (3u)
+#define INTC_ICDICER18_TINT164_SHIFT            (4u)
+#define INTC_ICDICER18_TINT165_SHIFT            (5u)
+#define INTC_ICDICER18_TINT166_SHIFT            (6u)
+#define INTC_ICDICER18_TINT167_SHIFT            (7u)
+#define INTC_ICDICER18_TINT168_SHIFT            (8u)
+#define INTC_ICDICER18_TINT169_SHIFT            (9u)
+#define INTC_ICDICER18_TINT170_SHIFT            (10u)
+
+#define INTC_ICDISPR0_SW0_SHIFT                 (0u)
+#define INTC_ICDISPR0_SW1_SHIFT                 (1u)
+#define INTC_ICDISPR0_SW2_SHIFT                 (2u)
+#define INTC_ICDISPR0_SW3_SHIFT                 (3u)
+#define INTC_ICDISPR0_SW4_SHIFT                 (4u)
+#define INTC_ICDISPR0_SW5_SHIFT                 (5u)
+#define INTC_ICDISPR0_SW6_SHIFT                 (6u)
+#define INTC_ICDISPR0_SW7_SHIFT                 (7u)
+#define INTC_ICDISPR0_SW8_SHIFT                 (8u)
+#define INTC_ICDISPR0_SW9_SHIFT                 (9u)
+#define INTC_ICDISPR0_SW10_SHIFT                (10u)
+#define INTC_ICDISPR0_SW11_SHIFT                (11u)
+#define INTC_ICDISPR0_SW12_SHIFT                (12u)
+#define INTC_ICDISPR0_SW13_SHIFT                (13u)
+#define INTC_ICDISPR0_SW14_SHIFT                (14u)
+#define INTC_ICDISPR0_SW15_SHIFT                (15u)
+#define INTC_ICDISPR0_PMUIRQ0_SHIFT             (16u)
+#define INTC_ICDISPR0_COMMRX0_SHIFT             (17u)
+#define INTC_ICDISPR0_COMMTX0_SHIFT             (18u)
+#define INTC_ICDISPR0_CTIIRQ0_SHIFT             (19u)
+
+#define INTC_ICDISPR1_IRQ0_SHIFT                (0u)
+#define INTC_ICDISPR1_IRQ1_SHIFT                (1u)
+#define INTC_ICDISPR1_IRQ2_SHIFT                (2u)
+#define INTC_ICDISPR1_IRQ3_SHIFT                (3u)
+#define INTC_ICDISPR1_IRQ4_SHIFT                (4u)
+#define INTC_ICDISPR1_IRQ5_SHIFT                (5u)
+#define INTC_ICDISPR1_IRQ6_SHIFT                (6u)
+#define INTC_ICDISPR1_IRQ7_SHIFT                (7u)
+#define INTC_ICDISPR1_PL310ERR_SHIFT            (8u)
+#define INTC_ICDISPR1_DMAINT0_SHIFT             (9u)
+#define INTC_ICDISPR1_DMAINT1_SHIFT             (10u)
+#define INTC_ICDISPR1_DMAINT2_SHIFT             (11u)
+#define INTC_ICDISPR1_DMAINT3_SHIFT             (12u)
+#define INTC_ICDISPR1_DMAINT4_SHIFT             (13u)
+#define INTC_ICDISPR1_DMAINT5_SHIFT             (14u)
+#define INTC_ICDISPR1_DMAINT6_SHIFT             (15u)
+#define INTC_ICDISPR1_DMAINT7_SHIFT             (16u)
+#define INTC_ICDISPR1_DMAINT8_SHIFT             (17u)
+#define INTC_ICDISPR1_DMAINT9_SHIFT             (18u)
+#define INTC_ICDISPR1_DMAINT10_SHIFT            (19u)
+#define INTC_ICDISPR1_DMAINT11_SHIFT            (20u)
+#define INTC_ICDISPR1_DMAINT12_SHIFT            (21u)
+#define INTC_ICDISPR1_DMAINT13_SHIFT            (22u)
+#define INTC_ICDISPR1_DMAINT14_SHIFT            (23u)
+#define INTC_ICDISPR1_DMAINT15_SHIFT            (24u)
+#define INTC_ICDISPR1_DMAERR_SHIFT              (25u)
+
+#define INTC_ICDISPR2_USBI0_SHIFT               (9u)
+#define INTC_ICDISPR2_USBI1_SHIFT               (10u)
+#define INTC_ICDISPR2_S0_VI_VSYNC0_SHIFT        (11u)
+#define INTC_ICDISPR2_S0_LO_VSYNC0_SHIFT        (12u)
+#define INTC_ICDISPR2_S0_VSYNCERR0_SHIFT        (13u)
+#define INTC_ICDISPR2_GR3_VLINE0_SHIFT          (14u)
+#define INTC_ICDISPR2_S0_VFIELD0_SHIFT          (15u)
+#define INTC_ICDISPR2_IV1_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDISPR2_IV3_VBUFERR0_SHIFT        (17u)
+#define INTC_ICDISPR2_IV5_VBUFERR0_SHIFT        (18u)
+#define INTC_ICDISPR2_IV6_VBUFERR0_SHIFT        (19u)
+#define INTC_ICDISPR2_S0_WLINE0_SHIFT           (20u)
+#define INTC_ICDISPR2_S1_VI_VSYNC0_SHIFT        (21u)
+#define INTC_ICDISPR2_S1_LO_VSYNC0_SHIFT        (22u)
+#define INTC_ICDISPR2_S1_VSYNCERR0_SHIFT        (23u)
+#define INTC_ICDISPR2_S1_VFIELD0_SHIFT          (24u)
+#define INTC_ICDISPR2_IV2_VBUFERR0_SHIFT        (25u)
+#define INTC_ICDISPR2_IV4_VBUFERR0_SHIFT        (26u)
+#define INTC_ICDISPR2_S1_WLINE0_SHIFT           (27u)
+#define INTC_ICDISPR2_OIR_VI_VSYNC0_SHIFT       (28u)
+#define INTC_ICDISPR2_OIR_LO_VSYNC0_SHIFT       (29u)
+#define INTC_ICDISPR2_OIR_VSYNCERR0_SHIFT       (30u)
+#define INTC_ICDISPR2_OIR_VFIELD0_SHIFT         (31u)
+
+#define INTC_ICDISPR3_IV7_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDISPR3_IV8_VBUFERR0_SHIFT        (1u)
+#define INTC_ICDISPR3_S0_VI_VSYNC1_SHIFT        (3u)
+#define INTC_ICDISPR3_S0_LO_VSYNC1_SHIFT        (4u)
+#define INTC_ICDISPR3_S0_VSYNCERR1_SHIFT        (5u)
+#define INTC_ICDISPR3_GR3_VLINE1_SHIFT          (6u)
+#define INTC_ICDISPR3_S0_VFIELD1_SHIFT          (7u)
+#define INTC_ICDISPR3_IV1_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDISPR3_IV3_VBUFERR1_SHIFT        (9u)
+#define INTC_ICDISPR3_IV5_VBUFERR1_SHIFT        (10u)
+#define INTC_ICDISPR3_IV6_VBUFERR1_SHIFT        (11u)
+#define INTC_ICDISPR3_S0_WLINE1_SHIFT           (12u)
+#define INTC_ICDISPR3_S1_VI_VSYNC1_SHIFT        (13u)
+#define INTC_ICDISPR3_S1_LO_VSYNC1_SHIFT        (14u)
+#define INTC_ICDISPR3_S1_VSYNCERR1_SHIFT        (15u)
+#define INTC_ICDISPR3_S1_VFIELD1_SHIFT          (16u)
+#define INTC_ICDISPR3_IV2_VBUFERR1_SHIFT        (17u)
+#define INTC_ICDISPR3_IV4_VBUFERR1_SHIFT        (18u)
+#define INTC_ICDISPR3_S1_WLINE1_SHIFT           (19u)
+#define INTC_ICDISPR3_OIR_VI_VSYNC1_SHIFT       (20u)
+#define INTC_ICDISPR3_OIR_LO_VSYNC1_SHIFT       (21u)
+#define INTC_ICDISPR3_OIR_VLINE1_SHIFT          (22u)
+#define INTC_ICDISPR3_OIR_VFIELD1_SHIFT         (23u)
+#define INTC_ICDISPR3_IV7_VBUFERR1_SHIFT        (24u)
+#define INTC_ICDISPR3_IV8_VBUFERR1_SHIFT        (25u)
+#define INTC_ICDISPR3_IMRDI_SHIFT               (27u)
+#define INTC_ICDISPR3_IMR2I0_SHIFT              (28u)
+#define INTC_ICDISPR3_IMR2I1_SHIFT              (29u)
+#define INTC_ICDISPR3_JEDI_SHIFT                (30u)
+#define INTC_ICDISPR3_JDTI_SHIFT                (31u)
+
+#define INTC_ICDISPR4_CMP0_SHIFT                (0u)
+#define INTC_ICDISPR4_CMP1_SHIFT                (1u)
+#define INTC_ICDISPR4_INT0_SHIFT                (2u)
+#define INTC_ICDISPR4_INT1_SHIFT                (3u)
+#define INTC_ICDISPR4_INT2_SHIFT                (4u)
+#define INTC_ICDISPR4_INT3_SHIFT                (5u)
+#define INTC_ICDISPR4_OSTM0TINT_SHIFT           (6u)
+#define INTC_ICDISPR4_OSTM1TINT_SHIFT           (7u)
+#define INTC_ICDISPR4_CMI_SHIFT                 (8u)
+#define INTC_ICDISPR4_WTOUT_SHIFT               (9u)
+#define INTC_ICDISPR4_ITI_SHIFT                 (10u)
+#define INTC_ICDISPR4_TGI0A_SHIFT               (11u)
+#define INTC_ICDISPR4_TGI0B_SHIFT               (12u)
+#define INTC_ICDISPR4_TGI0C_SHIFT               (13u)
+#define INTC_ICDISPR4_TGI0D_SHIFT               (14u)
+#define INTC_ICDISPR4_TGI0V_SHIFT               (15u)
+#define INTC_ICDISPR4_TGI0E_SHIFT               (16u)
+#define INTC_ICDISPR4_TGI0F_SHIFT               (17u)
+#define INTC_ICDISPR4_TGI1A_SHIFT               (18u)
+#define INTC_ICDISPR4_TGI1B_SHIFT               (19u)
+#define INTC_ICDISPR4_TGI1V_SHIFT               (20u)
+#define INTC_ICDISPR4_TGI1U_SHIFT               (21u)
+#define INTC_ICDISPR4_TGI2A_SHIFT               (22u)
+#define INTC_ICDISPR4_TGI2B_SHIFT               (23u)
+#define INTC_ICDISPR4_TGI2V_SHIFT               (24u)
+#define INTC_ICDISPR4_TGI2U_SHIFT               (25u)
+#define INTC_ICDISPR4_TGI3A_SHIFT               (26u)
+#define INTC_ICDISPR4_TGI3B_SHIFT               (27u)
+#define INTC_ICDISPR4_TGI3C_SHIFT               (28u)
+#define INTC_ICDISPR4_TGI3D_SHIFT               (29u)
+#define INTC_ICDISPR4_TGI3V_SHIFT               (30u)
+#define INTC_ICDISPR4_TGI4A_SHIFT               (31u)
+
+#define INTC_ICDISPR5_TGI4B_SHIFT               (0u)
+#define INTC_ICDISPR5_TGI4C_SHIFT               (1u)
+#define INTC_ICDISPR5_TGI4D_SHIFT               (2u)
+#define INTC_ICDISPR5_TGI4V_SHIFT               (3u)
+#define INTC_ICDISPR5_CMI1_SHIFT                (4u)
+#define INTC_ICDISPR5_CMI2_SHIFT                (5u)
+#define INTC_ICDISPR5_SGDEI0_SHIFT              (6u)
+#define INTC_ICDISPR5_SGDEI1_SHIFT              (7u)
+#define INTC_ICDISPR5_SGDEI2_SHIFT              (8u)
+#define INTC_ICDISPR5_SGDEI3_SHIFT              (9u)
+#define INTC_ICDISPR5_ADI_SHIFT                 (10u)
+#define INTC_ICDISPR5_LMTI_SHIFT                (11u)
+#define INTC_ICDISPR5_SSII0_SHIFT               (12u)
+#define INTC_ICDISPR5_SSIRXI0_SHIFT             (13u)
+#define INTC_ICDISPR5_SSITXI0_SHIFT             (14u)
+#define INTC_ICDISPR5_SSII1_SHIFT               (15u)
+#define INTC_ICDISPR5_SSIRXI1_SHIFT             (16u)
+#define INTC_ICDISPR5_SSITXI1_SHIFT             (17u)
+#define INTC_ICDISPR5_SSII2_SHIFT               (18u)
+#define INTC_ICDISPR5_SSIRTI2_SHIFT             (19u)
+#define INTC_ICDISPR5_SSII3_SHIFT               (20u)
+#define INTC_ICDISPR5_SSIRXI3_SHIFT             (21u)
+#define INTC_ICDISPR5_SSITXI3_SHIFT             (22u)
+#define INTC_ICDISPR5_SSII4_SHIFT               (23u)
+#define INTC_ICDISPR5_SSIRTI4_SHIFT             (24u)
+#define INTC_ICDISPR5_SSII5_SHIFT               (25u)
+#define INTC_ICDISPR5_SSIRXI5_SHIFT             (26u)
+#define INTC_ICDISPR5_SSITXI5_SHIFT             (27u)
+#define INTC_ICDISPR5_SPDIFI_SHIFT              (28u)
+#define INTC_ICDISPR5_INTIICTEI0_SHIFT          (29u)
+#define INTC_ICDISPR5_INTIICRI0_SHIFT           (30u)
+#define INTC_ICDISPR5_INTIICTI0_SHIFT           (31u)
+
+#define INTC_ICDISPR6_INTIICSPI0_SHIFT          (0u)
+#define INTC_ICDISPR6_INTIICSTI0_SHIFT          (1u)
+#define INTC_ICDISPR6_INTIICNAKI0_SHIFT         (2u)
+#define INTC_ICDISPR6_INTIICALI0_SHIFT          (3u)
+#define INTC_ICDISPR6_INTIICTMOI0_SHIFT         (4u)
+#define INTC_ICDISPR6_INTIICTEI1_SHIFT          (5u)
+#define INTC_ICDISPR6_INTIICRI1_SHIFT           (6u)
+#define INTC_ICDISPR6_INTIICTI1_SHIFT           (7u)
+#define INTC_ICDISPR6_INTIICSPI1_SHIFT          (8u)
+#define INTC_ICDISPR6_INTIICSTI1_SHIFT          (9u)
+#define INTC_ICDISPR6_INTIICNAKI1_SHIFT         (10u)
+#define INTC_ICDISPR6_INTIICALI1_SHIFT          (11u)
+#define INTC_ICDISPR6_INTIICTMOI1_SHIFT         (12u)
+#define INTC_ICDISPR6_INTIICTEI2_SHIFT          (13u)
+#define INTC_ICDISPR6_INTIICRI2_SHIFT           (14u)
+#define INTC_ICDISPR6_INTIICTI2_SHIFT           (15u)
+#define INTC_ICDISPR6_INTIICSPI2_SHIFT          (16u)
+#define INTC_ICDISPR6_INTIICSTI2_SHIFT          (17u)
+#define INTC_ICDISPR6_INTIICNAKI2_SHIFT         (18u)
+#define INTC_ICDISPR6_INTIICALI2_SHIFT          (19u)
+#define INTC_ICDISPR6_INTIICTMOI2_SHIFT         (20u)
+#define INTC_ICDISPR6_INTIICTEI3_SHIFT          (21u)
+#define INTC_ICDISPR6_INTIICRI3_SHIFT           (22u)
+#define INTC_ICDISPR6_INTIICTI3_SHIFT           (23u)
+#define INTC_ICDISPR6_INTIICSPI3_SHIFT          (24u)
+#define INTC_ICDISPR6_INTIICSTI3_SHIFT          (25u)
+#define INTC_ICDISPR6_INTIICNAKI3_SHIFT         (26u)
+#define INTC_ICDISPR6_INTIICALI3_SHIFT          (27u)
+#define INTC_ICDISPR6_INTIICTMOI3_SHIFT         (28u)
+#define INTC_ICDISPR6_BRI0_SHIFT                (29u)
+#define INTC_ICDISPR6_ERI0_SHIFT                (30u)
+#define INTC_ICDISPR6_RXI0_SHIFT                (31u)
+
+#define INTC_ICDISPR7_TXI0_SHIFT                (0u)
+#define INTC_ICDISPR7_BRI1_SHIFT                (1u)
+#define INTC_ICDISPR7_ERI1_SHIFT                (2u)
+#define INTC_ICDISPR7_RXI1_SHIFT                (3u)
+#define INTC_ICDISPR7_TXI1_SHIFT                (4u)
+#define INTC_ICDISPR7_BRI2_SHIFT                (5u)
+#define INTC_ICDISPR7_ERI2_SHIFT                (6u)
+#define INTC_ICDISPR7_RXI2_SHIFT                (7u)
+#define INTC_ICDISPR7_TXI2_SHIFT                (8u)
+#define INTC_ICDISPR7_BRI3_SHIFT                (9u)
+#define INTC_ICDISPR7_ERI3_SHIFT                (10u)
+#define INTC_ICDISPR7_RXI3_SHIFT                (11u)
+#define INTC_ICDISPR7_TXI3_SHIFT                (12u)
+#define INTC_ICDISPR7_BRI4_SHIFT                (13u)
+#define INTC_ICDISPR7_ERI4_SHIFT                (14u)
+#define INTC_ICDISPR7_RXI4_SHIFT                (15u)
+#define INTC_ICDISPR7_TXI4_SHIFT                (16u)
+#define INTC_ICDISPR7_BRI5_SHIFT                (17u)
+#define INTC_ICDISPR7_ERI5_SHIFT                (18u)
+#define INTC_ICDISPR7_RXI5_SHIFT                (19u)
+#define INTC_ICDISPR7_TXI5_SHIFT                (20u)
+#define INTC_ICDISPR7_BRI6_SHIFT                (21u)
+#define INTC_ICDISPR7_ERI6_SHIFT                (22u)
+#define INTC_ICDISPR7_RXI6_SHIFT                (23u)
+#define INTC_ICDISPR7_TXI6_SHIFT                (24u)
+#define INTC_ICDISPR7_BRI7_SHIFT                (25u)
+#define INTC_ICDISPR7_ERI7_SHIFT                (26u)
+#define INTC_ICDISPR7_RXI7_SHIFT                (27u)
+#define INTC_ICDISPR7_TXI7_SHIFT                (28u)
+#define INTC_ICDISPR7_INTRCANGERR_SHIFT         (29u)
+#define INTC_ICDISPR7_INTRCANGRECC_SHIFT        (30u)
+#define INTC_ICDISPR7_INTRCAN0REC_SHIFT         (31u)
+
+#define INTC_ICDISPR8_INTRCAN0ERR_SHIFT         (0u)
+#define INTC_ICDISPR8_INTRCAN0TRX_SHIFT         (1u)
+#define INTC_ICDISPR8_INTRCAN1REC_SHIFT         (2u)
+#define INTC_ICDISPR8_INTRCAN1ERR_SHIFT         (3u)
+#define INTC_ICDISPR8_INTRCAN1TRX_SHIFT         (4u)
+#define INTC_ICDISPR8_INTRCAN2REC_SHIFT         (5u)
+#define INTC_ICDISPR8_INTRCAN2ERR_SHIFT         (6u)
+#define INTC_ICDISPR8_INTRCAN2TRX_SHIFT         (7u)
+#define INTC_ICDISPR8_INTRCAN3REC_SHIFT         (8u)
+#define INTC_ICDISPR8_INTRCAN3ERR_SHIFT         (9u)
+#define INTC_ICDISPR8_INTRCAN3TRX_SHIFT         (10u)
+#define INTC_ICDISPR8_INTRCAN4REC_SHIFT         (11u)
+#define INTC_ICDISPR8_INTRCAN4ERR_SHIFT         (12u)
+#define INTC_ICDISPR8_INTRCAN4TRX_SHIFT         (13u)
+#define INTC_ICDISPR8_SPEI0_SHIFT               (14u)
+#define INTC_ICDISPR8_SPRI0_SHIFT               (15u)
+#define INTC_ICDISPR8_SPTI0_SHIFT               (16u)
+#define INTC_ICDISPR8_SPEI1_SHIFT               (17u)
+#define INTC_ICDISPR8_SPRI1_SHIFT               (18u)
+#define INTC_ICDISPR8_SPTI1_SHIFT               (19u)
+#define INTC_ICDISPR8_SPEI2_SHIFT               (20u)
+#define INTC_ICDISPR8_SPRI2_SHIFT               (21u)
+#define INTC_ICDISPR8_SPTI2_SHIFT               (22u)
+#define INTC_ICDISPR8_SPEI3_SHIFT               (23u)
+#define INTC_ICDISPR8_SPRI3_SHIFT               (24u)
+#define INTC_ICDISPR8_SPTI3_SHIFT               (25u)
+#define INTC_ICDISPR8_SPEI4_SHIFT               (26u)
+#define INTC_ICDISPR8_SPRI4_SHIFT               (27u)
+#define INTC_ICDISPR8_SPTI4_SHIFT               (28u)
+#define INTC_ICDISPR8_IEBBTD_SHIFT              (29u)
+#define INTC_ICDISPR8_IEBBTERR_SHIFT            (30u)
+#define INTC_ICDISPR8_IEBBTSTA_SHIFT            (31u)
+
+#define INTC_ICDISPR9_IEBBTV_SHIFT              (0u)
+#define INTC_ICDISPR9_ISY_SHIFT                 (1u)
+#define INTC_ICDISPR9_IERR_SHIFT                (2u)
+#define INTC_ICDISPR9_ITARG_SHIFT               (3u)
+#define INTC_ICDISPR9_ISEC_SHIFT                (4u)
+#define INTC_ICDISPR9_IBUF_SHIFT                (5u)
+#define INTC_ICDISPR9_IREADY_SHIFT              (6u)
+#define INTC_ICDISPR9_FLSTE_SHIFT               (7u)
+#define INTC_ICDISPR9_FLTENDI_SHIFT             (8u)
+#define INTC_ICDISPR9_FLTREQ0I_SHIFT            (9u)
+#define INTC_ICDISPR9_FLTREQ1I_SHIFT            (10u)
+#define INTC_ICDISPR9_MMC0_SHIFT                (11u)
+#define INTC_ICDISPR9_MMC1_SHIFT                (12u)
+#define INTC_ICDISPR9_MMC2_SHIFT                (13u)
+#define INTC_ICDISPR9_SDHI0_3_SHIFT             (14u)
+#define INTC_ICDISPR9_SDHI0_0_SHIFT             (15u)
+#define INTC_ICDISPR9_SDHI0_1_SHIFT             (16u)
+#define INTC_ICDISPR9_SDHI1_3_SHIFT             (17u)
+#define INTC_ICDISPR9_SDHI1_0_SHIFT             (18u)
+#define INTC_ICDISPR9_SDHI1_1_SHIFT             (19u)
+#define INTC_ICDISPR9_ARM_SHIFT                 (20u)
+#define INTC_ICDISPR9_PRD_SHIFT                 (21u)
+#define INTC_ICDISPR9_CUP_SHIFT                 (22u)
+#define INTC_ICDISPR9_SCUAI0_SHIFT              (23u)
+#define INTC_ICDISPR9_SCUAI1_SHIFT              (24u)
+#define INTC_ICDISPR9_SCUFDI0_SHIFT             (25u)
+#define INTC_ICDISPR9_SCUFDI1_SHIFT             (26u)
+#define INTC_ICDISPR9_SCUFDI2_SHIFT             (27u)
+#define INTC_ICDISPR9_SCUFDI3_SHIFT             (28u)
+#define INTC_ICDISPR9_SCUFUI0_SHIFT             (29u)
+#define INTC_ICDISPR9_SCUFUI1_SHIFT             (30u)
+#define INTC_ICDISPR9_SCUFUI2_SHIFT             (31u)
+
+#define INTC_ICDISPR10_SCUFUI3_SHIFT            (0u)
+#define INTC_ICDISPR10_SCUDVI0_SHIFT            (1u)
+#define INTC_ICDISPR10_SCUDVI1_SHIFT            (2u)
+#define INTC_ICDISPR10_SCUDVI2_SHIFT            (3u)
+#define INTC_ICDISPR10_SCUDVI3_SHIFT            (4u)
+#define INTC_ICDISPR10_MLB_CINT_SHIFT           (5u)
+#define INTC_ICDISPR10_MLB_SINT_SHIFT           (6u)
+#define INTC_ICDISPR10_DRC0_SHIFT               (7u)
+#define INTC_ICDISPR10_DRC1_SHIFT               (8u)
+#define INTC_ICDISPR10_LINI0_INT_T_SHIFT        (11u)
+#define INTC_ICDISPR10_LINI0_INT_R_SHIFT        (12u)
+#define INTC_ICDISPR10_LINI0_INT_S_SHIFT        (13u)
+#define INTC_ICDISPR10_LINI0_INT_M_SHIFT        (14u)
+#define INTC_ICDISPR10_LINI1_INT_T_SHIFT        (15u)
+#define INTC_ICDISPR10_LINI1_INT_R_SHIFT        (16u)
+#define INTC_ICDISPR10_LINI1_INT_S_SHIFT        (17u)
+#define INTC_ICDISPR10_LINI1_INT_M_SHIFT        (18u)
+#define INTC_ICDISPR10_ERI0_SHIFT               (27u)
+#define INTC_ICDISPR10_RXI0_SHIFT               (28u)
+#define INTC_ICDISPR10_TXI0_SHIFT               (29u)
+#define INTC_ICDISPR10_TEI0_SHIFT               (30u)
+#define INTC_ICDISPR10_ERI1_SHIFT               (31u)
+
+#define INTC_ICDISPR11_RXI1_SHIFT               (0u)
+#define INTC_ICDISPR11_TXI1_SHIFT               (1u)
+#define INTC_ICDISPR11_TEI1_SHIFT               (2u)
+#define INTC_ICDISPR11_AVBI_DATA_SHIFT          (3u)
+#define INTC_ICDISPR11_AVBI_ERROR_SHIFT         (4u)
+#define INTC_ICDISPR11_AVBI_MANAGE_SHIFT        (5u)
+#define INTC_ICDISPR11_AVBI_MAC_SHIFT           (6u)
+#define INTC_ICDISPR11_ETHERI_SHIFT             (7u)
+#define INTC_ICDISPR11_CEUI_SHIFT               (12u)
+#define INTC_ICDISPR11_H2XMLB_ERRINT_SHIFT      (29u)
+#define INTC_ICDISPR11_H2XIC1_ERRINT_SHIFT      (30u)
+#define INTC_ICDISPR11_X2HPERI1_ERRINT_SHIFT    (31u)
+
+#define INTC_ICDISPR12_X2HPERI2_ERRINT_SHIFT    (0u)
+#define INTC_ICDISPR12_X2HPERI34_ERRINT_SHIFT   (1u)
+#define INTC_ICDISPR12_X2HPERI5_ERRINT_SHIFT    (2u)
+#define INTC_ICDISPR12_X2HPERI67_ERRINT_SHIFT   (3u)
+#define INTC_ICDISPR12_X2HDBGR_ERRINT_SHIFT     (4u)
+#define INTC_ICDISPR12_X2HBSC_ERRINT_SHIFT      (5u)
+#define INTC_ICDISPR12_X2HSPI1_ERRINT_SHIFT     (6u)
+#define INTC_ICDISPR12_X2HSPI2_ERRINT_SHIFT     (7u)
+#define INTC_ICDISPR12_PRRI_SHIFT               (8u)
+#define INTC_ICDISPR12_IFEI0_SHIFT              (9u)
+#define INTC_ICDISPR12_OFFI0_SHIFT              (10u)
+#define INTC_ICDISPR12_PFVEI0_SHIFT             (11u)
+#define INTC_ICDISPR12_IFEI1_SHIFT              (12u)
+#define INTC_ICDISPR12_OFFI1_SHIFT              (13u)
+#define INTC_ICDISPR12_PFVEI1_SHIFT             (14u)
+
+#define INTC_ICDISPR13_TINT0_SHIFT              (0u)
+#define INTC_ICDISPR13_TINT1_SHIFT              (1u)
+#define INTC_ICDISPR13_TINT2_SHIFT              (2u)
+#define INTC_ICDISPR13_TINT3_SHIFT              (3u)
+#define INTC_ICDISPR13_TINT4_SHIFT              (4u)
+#define INTC_ICDISPR13_TINT5_SHIFT              (5u)
+#define INTC_ICDISPR13_TINT6_SHIFT              (6u)
+#define INTC_ICDISPR13_TINT7_SHIFT              (7u)
+#define INTC_ICDISPR13_TINT8_SHIFT              (8u)
+#define INTC_ICDISPR13_TINT9_SHIFT              (9u)
+#define INTC_ICDISPR13_TINT10_SHIFT             (10u)
+#define INTC_ICDISPR13_TINT11_SHIFT             (11u)
+#define INTC_ICDISPR13_TINT12_SHIFT             (12u)
+#define INTC_ICDISPR13_TINT13_SHIFT             (13u)
+#define INTC_ICDISPR13_TINT14_SHIFT             (14u)
+#define INTC_ICDISPR13_TINT15_SHIFT             (15u)
+#define INTC_ICDISPR13_TINT16_SHIFT             (16u)
+#define INTC_ICDISPR13_TINT17_SHIFT             (17u)
+#define INTC_ICDISPR13_TINT18_SHIFT             (18u)
+#define INTC_ICDISPR13_TINT19_SHIFT             (19u)
+#define INTC_ICDISPR13_TINT20_SHIFT             (20u)
+#define INTC_ICDISPR13_TINT21_SHIFT             (21u)
+#define INTC_ICDISPR13_TINT22_SHIFT             (22u)
+#define INTC_ICDISPR13_TINT23_SHIFT             (23u)
+#define INTC_ICDISPR13_TINT24_SHIFT             (24u)
+#define INTC_ICDISPR13_TINT25_SHIFT             (25u)
+#define INTC_ICDISPR13_TINT26_SHIFT             (26u)
+#define INTC_ICDISPR13_TINT27_SHIFT             (27u)
+#define INTC_ICDISPR13_TINT28_SHIFT             (28u)
+#define INTC_ICDISPR13_TINT29_SHIFT             (29u)
+#define INTC_ICDISPR13_TINT30_SHIFT             (30u)
+#define INTC_ICDISPR13_TINT31_SHIFT             (31u)
+
+#define INTC_ICDISPR14_TINT32_SHIFT             (0u)
+#define INTC_ICDISPR14_TINT33_SHIFT             (1u)
+#define INTC_ICDISPR14_TINT34_SHIFT             (2u)
+#define INTC_ICDISPR14_TINT35_SHIFT             (3u)
+#define INTC_ICDISPR14_TINT36_SHIFT             (4u)
+#define INTC_ICDISPR14_TINT37_SHIFT             (5u)
+#define INTC_ICDISPR14_TINT38_SHIFT             (6u)
+#define INTC_ICDISPR14_TINT39_SHIFT             (7u)
+#define INTC_ICDISPR14_TINT40_SHIFT             (8u)
+#define INTC_ICDISPR14_TINT41_SHIFT             (9u)
+#define INTC_ICDISPR14_TINT42_SHIFT             (10u)
+#define INTC_ICDISPR14_TINT43_SHIFT             (11u)
+#define INTC_ICDISPR14_TINT44_SHIFT             (12u)
+#define INTC_ICDISPR14_TINT45_SHIFT             (13u)
+#define INTC_ICDISPR14_TINT46_SHIFT             (14u)
+#define INTC_ICDISPR14_TINT47_SHIFT             (15u)
+#define INTC_ICDISPR14_TINT48_SHIFT             (16u)
+#define INTC_ICDISPR14_TINT49_SHIFT             (17u)
+#define INTC_ICDISPR14_TINT50_SHIFT             (18u)
+#define INTC_ICDISPR14_TINT51_SHIFT             (19u)
+#define INTC_ICDISPR14_TINT52_SHIFT             (20u)
+#define INTC_ICDISPR14_TINT53_SHIFT             (21u)
+#define INTC_ICDISPR14_TINT54_SHIFT             (22u)
+#define INTC_ICDISPR14_TINT55_SHIFT             (23u)
+#define INTC_ICDISPR14_TINT56_SHIFT             (24u)
+#define INTC_ICDISPR14_TINT57_SHIFT             (25u)
+#define INTC_ICDISPR14_TINT58_SHIFT             (26u)
+#define INTC_ICDISPR14_TINT59_SHIFT             (27u)
+#define INTC_ICDISPR14_TINT60_SHIFT             (28u)
+#define INTC_ICDISPR14_TINT61_SHIFT             (29u)
+#define INTC_ICDISPR14_TINT62_SHIFT             (30u)
+#define INTC_ICDISPR14_TINT63_SHIFT             (31u)
+
+#define INTC_ICDISPR15_TINT64_SHIFT             (0u)
+#define INTC_ICDISPR15_TINT65_SHIFT             (1u)
+#define INTC_ICDISPR15_TINT66_SHIFT             (2u)
+#define INTC_ICDISPR15_TINT67_SHIFT             (3u)
+#define INTC_ICDISPR15_TINT68_SHIFT             (4u)
+#define INTC_ICDISPR15_TINT69_SHIFT             (5u)
+#define INTC_ICDISPR15_TINT70_SHIFT             (6u)
+#define INTC_ICDISPR15_TINT71_SHIFT             (7u)
+#define INTC_ICDISPR15_TINT72_SHIFT             (8u)
+#define INTC_ICDISPR15_TINT73_SHIFT             (9u)
+#define INTC_ICDISPR15_TINT74_SHIFT             (10u)
+#define INTC_ICDISPR15_TINT75_SHIFT             (11u)
+#define INTC_ICDISPR15_TINT76_SHIFT             (12u)
+#define INTC_ICDISPR15_TINT77_SHIFT             (13u)
+#define INTC_ICDISPR15_TINT78_SHIFT             (14u)
+#define INTC_ICDISPR15_TINT79_SHIFT             (15u)
+#define INTC_ICDISPR15_TINT80_SHIFT             (16u)
+#define INTC_ICDISPR15_TINT81_SHIFT             (17u)
+#define INTC_ICDISPR15_TINT82_SHIFT             (18u)
+#define INTC_ICDISPR15_TINT83_SHIFT             (19u)
+#define INTC_ICDISPR15_TINT84_SHIFT             (20u)
+#define INTC_ICDISPR15_TINT85_SHIFT             (21u)
+#define INTC_ICDISPR15_TINT86_SHIFT             (22u)
+#define INTC_ICDISPR15_TINT87_SHIFT             (23u)
+#define INTC_ICDISPR15_TINT88_SHIFT             (24u)
+#define INTC_ICDISPR15_TINT89_SHIFT             (25u)
+#define INTC_ICDISPR15_TINT90_SHIFT             (26u)
+#define INTC_ICDISPR15_TINT91_SHIFT             (27u)
+#define INTC_ICDISPR15_TINT92_SHIFT             (28u)
+#define INTC_ICDISPR15_TINT93_SHIFT             (29u)
+#define INTC_ICDISPR15_TINT94_SHIFT             (30u)
+#define INTC_ICDISPR15_TINT95_SHIFT             (31u)
+
+#define INTC_ICDISPR16_TINT96_SHIFT             (0u)
+#define INTC_ICDISPR16_TINT97_SHIFT             (1u)
+#define INTC_ICDISPR16_TINT98_SHIFT             (2u)
+#define INTC_ICDISPR16_TINT99_SHIFT             (3u)
+#define INTC_ICDISPR16_TINT100_SHIFT            (4u)
+#define INTC_ICDISPR16_TINT101_SHIFT            (5u)
+#define INTC_ICDISPR16_TINT102_SHIFT            (6u)
+#define INTC_ICDISPR16_TINT103_SHIFT            (7u)
+#define INTC_ICDISPR16_TINT104_SHIFT            (8u)
+#define INTC_ICDISPR16_TINT105_SHIFT            (9u)
+#define INTC_ICDISPR16_TINT106_SHIFT            (10u)
+#define INTC_ICDISPR16_TINT107_SHIFT            (11u)
+#define INTC_ICDISPR16_TINT108_SHIFT            (12u)
+#define INTC_ICDISPR16_TINT109_SHIFT            (13u)
+#define INTC_ICDISPR16_TINT110_SHIFT            (14u)
+#define INTC_ICDISPR16_TINT111_SHIFT            (15u)
+#define INTC_ICDISPR16_TINT112_SHIFT            (16u)
+#define INTC_ICDISPR16_TINT113_SHIFT            (17u)
+#define INTC_ICDISPR16_TINT114_SHIFT            (18u)
+#define INTC_ICDISPR16_TINT115_SHIFT            (19u)
+#define INTC_ICDISPR16_TINT116_SHIFT            (20u)
+#define INTC_ICDISPR16_TINT117_SHIFT            (21u)
+#define INTC_ICDISPR16_TINT118_SHIFT            (22u)
+#define INTC_ICDISPR16_TINT119_SHIFT            (23u)
+#define INTC_ICDISPR16_TINT120_SHIFT            (24u)
+#define INTC_ICDISPR16_TINT121_SHIFT            (25u)
+#define INTC_ICDISPR16_TINT122_SHIFT            (26u)
+#define INTC_ICDISPR16_TINT123_SHIFT            (27u)
+#define INTC_ICDISPR16_TINT124_SHIFT            (28u)
+#define INTC_ICDISPR16_TINT125_SHIFT            (29u)
+#define INTC_ICDISPR16_TINT126_SHIFT            (30u)
+#define INTC_ICDISPR16_TINT127_SHIFT            (31u)
+
+#define INTC_ICDISPR17_TINT128_SHIFT            (0u)
+#define INTC_ICDISPR17_TINT129_SHIFT            (1u)
+#define INTC_ICDISPR17_TINT130_SHIFT            (2u)
+#define INTC_ICDISPR17_TINT131_SHIFT            (3u)
+#define INTC_ICDISPR17_TINT132_SHIFT            (4u)
+#define INTC_ICDISPR17_TINT133_SHIFT            (5u)
+#define INTC_ICDISPR17_TINT134_SHIFT            (6u)
+#define INTC_ICDISPR17_TINT135_SHIFT            (7u)
+#define INTC_ICDISPR17_TINT136_SHIFT            (8u)
+#define INTC_ICDISPR17_TINT137_SHIFT            (9u)
+#define INTC_ICDISPR17_TINT138_SHIFT            (10u)
+#define INTC_ICDISPR17_TINT139_SHIFT            (11u)
+#define INTC_ICDISPR17_TINT140_SHIFT            (12u)
+#define INTC_ICDISPR17_TINT141_SHIFT            (13u)
+#define INTC_ICDISPR17_TINT142_SHIFT            (14u)
+#define INTC_ICDISPR17_TINT143_SHIFT            (15u)
+#define INTC_ICDISPR17_TINT144_SHIFT            (16u)
+#define INTC_ICDISPR17_TINT145_SHIFT            (17u)
+#define INTC_ICDISPR17_TINT146_SHIFT            (18u)
+#define INTC_ICDISPR17_TINT147_SHIFT            (19u)
+#define INTC_ICDISPR17_TINT148_SHIFT            (20u)
+#define INTC_ICDISPR17_TINT149_SHIFT            (21u)
+#define INTC_ICDISPR17_TINT150_SHIFT            (22u)
+#define INTC_ICDISPR17_TINT151_SHIFT            (23u)
+#define INTC_ICDISPR17_TINT152_SHIFT            (24u)
+#define INTC_ICDISPR17_TINT153_SHIFT            (25u)
+#define INTC_ICDISPR17_TINT154_SHIFT            (26u)
+#define INTC_ICDISPR17_TINT155_SHIFT            (27u)
+#define INTC_ICDISPR17_TINT156_SHIFT            (28u)
+#define INTC_ICDISPR17_TINT157_SHIFT            (29u)
+#define INTC_ICDISPR17_TINT158_SHIFT            (30u)
+#define INTC_ICDISPR17_TINT159_SHIFT            (31u)
+
+#define INTC_ICDISPR18_TINT160_SHIFT            (0u)
+#define INTC_ICDISPR18_TINT161_SHIFT            (1u)
+#define INTC_ICDISPR18_TINT162_SHIFT            (2u)
+#define INTC_ICDISPR18_TINT163_SHIFT            (3u)
+#define INTC_ICDISPR18_TINT164_SHIFT            (4u)
+#define INTC_ICDISPR18_TINT165_SHIFT            (5u)
+#define INTC_ICDISPR18_TINT166_SHIFT            (6u)
+#define INTC_ICDISPR18_TINT167_SHIFT            (7u)
+#define INTC_ICDISPR18_TINT168_SHIFT            (8u)
+#define INTC_ICDISPR18_TINT169_SHIFT            (9u)
+#define INTC_ICDISPR18_TINT170_SHIFT            (10u)
+
+#define INTC_ICDICPR0_SW0_SHIFT                 (0u)
+#define INTC_ICDICPR0_SW1_SHIFT                 (1u)
+#define INTC_ICDICPR0_SW2_SHIFT                 (2u)
+#define INTC_ICDICPR0_SW3_SHIFT                 (3u)
+#define INTC_ICDICPR0_SW4_SHIFT                 (4u)
+#define INTC_ICDICPR0_SW5_SHIFT                 (5u)
+#define INTC_ICDICPR0_SW6_SHIFT                 (6u)
+#define INTC_ICDICPR0_SW7_SHIFT                 (7u)
+#define INTC_ICDICPR0_SW8_SHIFT                 (8u)
+#define INTC_ICDICPR0_SW9_SHIFT                 (9u)
+#define INTC_ICDICPR0_SW10_SHIFT                (10u)
+#define INTC_ICDICPR0_SW11_SHIFT                (11u)
+#define INTC_ICDICPR0_SW12_SHIFT                (12u)
+#define INTC_ICDICPR0_SW13_SHIFT                (13u)
+#define INTC_ICDICPR0_SW14_SHIFT                (14u)
+#define INTC_ICDICPR0_SW15_SHIFT                (15u)
+#define INTC_ICDICPR0_PMUIRQ0_SHIFT             (16u)
+#define INTC_ICDICPR0_COMMRX0_SHIFT             (17u)
+#define INTC_ICDICPR0_COMMTX0_SHIFT             (18u)
+#define INTC_ICDICPR0_CTIIRQ0_SHIFT             (19u)
+
+#define INTC_ICDICPR1_IRQ0_SHIFT                (0u)
+#define INTC_ICDICPR1_IRQ1_SHIFT                (1u)
+#define INTC_ICDICPR1_IRQ2_SHIFT                (2u)
+#define INTC_ICDICPR1_IRQ3_SHIFT                (3u)
+#define INTC_ICDICPR1_IRQ4_SHIFT                (4u)
+#define INTC_ICDICPR1_IRQ5_SHIFT                (5u)
+#define INTC_ICDICPR1_IRQ6_SHIFT                (6u)
+#define INTC_ICDICPR1_IRQ7_SHIFT                (7u)
+#define INTC_ICDICPR1_PL310ERR_SHIFT            (8u)
+#define INTC_ICDICPR1_DMAINT0_SHIFT             (9u)
+#define INTC_ICDICPR1_DMAINT1_SHIFT             (10u)
+#define INTC_ICDICPR1_DMAINT2_SHIFT             (11u)
+#define INTC_ICDICPR1_DMAINT3_SHIFT             (12u)
+#define INTC_ICDICPR1_DMAINT4_SHIFT             (13u)
+#define INTC_ICDICPR1_DMAINT5_SHIFT             (14u)
+#define INTC_ICDICPR1_DMAINT6_SHIFT             (15u)
+#define INTC_ICDICPR1_DMAINT7_SHIFT             (16u)
+#define INTC_ICDICPR1_DMAINT8_SHIFT             (17u)
+#define INTC_ICDICPR1_DMAINT9_SHIFT             (18u)
+#define INTC_ICDICPR1_DMAINT10_SHIFT            (19u)
+#define INTC_ICDICPR1_DMAINT11_SHIFT            (20u)
+#define INTC_ICDICPR1_DMAINT12_SHIFT            (21u)
+#define INTC_ICDICPR1_DMAINT13_SHIFT            (22u)
+#define INTC_ICDICPR1_DMAINT14_SHIFT            (23u)
+#define INTC_ICDICPR1_DMAINT15_SHIFT            (24u)
+#define INTC_ICDICPR1_DMAERR_SHIFT              (25u)
+
+#define INTC_ICDICPR2_USBI0_SHIFT               (9u)
+#define INTC_ICDICPR2_USBI1_SHIFT               (10u)
+#define INTC_ICDICPR2_S0_VI_VSYNC0_SHIFT        (11u)
+#define INTC_ICDICPR2_S0_LO_VSYNC0_SHIFT        (12u)
+#define INTC_ICDICPR2_S0_VSYNCERR0_SHIFT        (13u)
+#define INTC_ICDICPR2_GR3_VLINE0_SHIFT          (14u)
+#define INTC_ICDICPR2_S0_VFIELD0_SHIFT          (15u)
+#define INTC_ICDICPR2_IV1_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDICPR2_IV3_VBUFERR0_SHIFT        (17u)
+#define INTC_ICDICPR2_IV5_VBUFERR0_SHIFT        (18u)
+#define INTC_ICDICPR2_IV6_VBUFERR0_SHIFT        (19u)
+#define INTC_ICDICPR2_S0_WLINE0_SHIFT           (20u)
+#define INTC_ICDICPR2_S1_VI_VSYNC0_SHIFT        (21u)
+#define INTC_ICDICPR2_S1_LO_VSYNC0_SHIFT        (22u)
+#define INTC_ICDICPR2_S1_VSYNCERR0_SHIFT        (23u)
+#define INTC_ICDICPR2_S1_VFIELD0_SHIFT          (24u)
+#define INTC_ICDICPR2_IV2_VBUFERR0_SHIFT        (25u)
+#define INTC_ICDICPR2_IV4_VBUFERR0_SHIFT        (26u)
+#define INTC_ICDICPR2_S1_WLINE0_SHIFT           (27u)
+#define INTC_ICDICPR2_OIR_VI_VSYNC0_SHIFT       (28u)
+#define INTC_ICDICPR2_OIR_LO_VSYNC0_SHIFT       (29u)
+#define INTC_ICDICPR2_OIR_VSYNCERR0_SHIFT       (30u)
+#define INTC_ICDICPR2_OIR_VFIELD0_SHIFT         (31u)
+
+#define INTC_ICDICPR3_IV7_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDICPR3_IV8_VBUFERR0_SHIFT        (1u)
+#define INTC_ICDICPR3_S0_VI_VSYNC1_SHIFT        (3u)
+#define INTC_ICDICPR3_S0_LO_VSYNC1_SHIFT        (4u)
+#define INTC_ICDICPR3_S0_VSYNCERR1_SHIFT        (5u)
+#define INTC_ICDICPR3_GR3_VLINE1_SHIFT          (6u)
+#define INTC_ICDICPR3_S0_VFIELD1_SHIFT          (7u)
+#define INTC_ICDICPR3_IV1_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDICPR3_IV3_VBUFERR1_SHIFT        (9u)
+#define INTC_ICDICPR3_IV5_VBUFERR1_SHIFT        (10u)
+#define INTC_ICDICPR3_IV6_VBUFERR1_SHIFT        (11u)
+#define INTC_ICDICPR3_S0_WLINE1_SHIFT           (12u)
+#define INTC_ICDICPR3_S1_VI_VSYNC1_SHIFT        (13u)
+#define INTC_ICDICPR3_S1_LO_VSYNC1_SHIFT        (14u)
+#define INTC_ICDICPR3_S1_VSYNCERR1_SHIFT        (15u)
+#define INTC_ICDICPR3_S1_VFIELD1_SHIFT          (16u)
+#define INTC_ICDICPR3_IV2_VBUFERR1_SHIFT        (17u)
+#define INTC_ICDICPR3_IV4_VBUFERR1_SHIFT        (18u)
+#define INTC_ICDICPR3_S1_WLINE1_SHIFT           (19u)
+#define INTC_ICDICPR3_OIR_VI_VSYNC1_SHIFT       (20u)
+#define INTC_ICDICPR3_OIR_LO_VSYNC1_SHIFT       (21u)
+#define INTC_ICDICPR3_OIR_VLINE1_SHIFT          (22u)
+#define INTC_ICDICPR3_OIR_VFIELD1_SHIFT         (23u)
+#define INTC_ICDICPR3_IV7_VBUFERR1_SHIFT        (24u)
+#define INTC_ICDICPR3_IV8_VBUFERR1_SHIFT        (25u)
+#define INTC_ICDICPR3_IMRDI_SHIFT               (27u)
+#define INTC_ICDICPR3_IMR2I0_SHIFT              (28u)
+#define INTC_ICDICPR3_IMR2I1_SHIFT              (29u)
+#define INTC_ICDICPR3_JEDI_SHIFT                (30u)
+#define INTC_ICDICPR3_JDTI_SHIFT                (31u)
+
+#define INTC_ICDICPR4_CMP0_SHIFT                (0u)
+#define INTC_ICDICPR4_CMP1_SHIFT                (1u)
+#define INTC_ICDICPR4_INT0_SHIFT                (2u)
+#define INTC_ICDICPR4_INT1_SHIFT                (3u)
+#define INTC_ICDICPR4_INT2_SHIFT                (4u)
+#define INTC_ICDICPR4_INT3_SHIFT                (5u)
+#define INTC_ICDICPR4_OSTM0TINT_SHIFT           (6u)
+#define INTC_ICDICPR4_OSTM1TINT_SHIFT           (7u)
+#define INTC_ICDICPR4_CMI_SHIFT                 (8u)
+#define INTC_ICDICPR4_WTOUT_SHIFT               (9u)
+#define INTC_ICDICPR4_ITI_SHIFT                 (10u)
+#define INTC_ICDICPR4_TGI0A_SHIFT               (11u)
+#define INTC_ICDICPR4_TGI0B_SHIFT               (12u)
+#define INTC_ICDICPR4_TGI0C_SHIFT               (13u)
+#define INTC_ICDICPR4_TGI0D_SHIFT               (14u)
+#define INTC_ICDICPR4_TGI0V_SHIFT               (15u)
+#define INTC_ICDICPR4_TGI0E_SHIFT               (16u)
+#define INTC_ICDICPR4_TGI0F_SHIFT               (17u)
+#define INTC_ICDICPR4_TGI1A_SHIFT               (18u)
+#define INTC_ICDICPR4_TGI1B_SHIFT               (19u)
+#define INTC_ICDICPR4_TGI1V_SHIFT               (20u)
+#define INTC_ICDICPR4_TGI1U_SHIFT               (21u)
+#define INTC_ICDICPR4_TGI2A_SHIFT               (22u)
+#define INTC_ICDICPR4_TGI2B_SHIFT               (23u)
+#define INTC_ICDICPR4_TGI2V_SHIFT               (24u)
+#define INTC_ICDICPR4_TGI2U_SHIFT               (25u)
+#define INTC_ICDICPR4_TGI3A_SHIFT               (26u)
+#define INTC_ICDICPR4_TGI3B_SHIFT               (27u)
+#define INTC_ICDICPR4_TGI3C_SHIFT               (28u)
+#define INTC_ICDICPR4_TGI3D_SHIFT               (29u)
+#define INTC_ICDICPR4_TGI3V_SHIFT               (30u)
+#define INTC_ICDICPR4_TGI4A_SHIFT               (31u)
+
+#define INTC_ICDICPR5_TGI4B_SHIFT               (0u)
+#define INTC_ICDICPR5_TGI4C_SHIFT               (1u)
+#define INTC_ICDICPR5_TGI4D_SHIFT               (2u)
+#define INTC_ICDICPR5_TGI4V_SHIFT               (3u)
+#define INTC_ICDICPR5_CMI1_SHIFT                (4u)
+#define INTC_ICDICPR5_CMI2_SHIFT                (5u)
+#define INTC_ICDICPR5_SGDEI0_SHIFT              (6u)
+#define INTC_ICDICPR5_SGDEI1_SHIFT              (7u)
+#define INTC_ICDICPR5_SGDEI2_SHIFT              (8u)
+#define INTC_ICDICPR5_SGDEI3_SHIFT              (9u)
+#define INTC_ICDICPR5_ADI_SHIFT                 (10u)
+#define INTC_ICDICPR5_LMTI_SHIFT                (11u)
+#define INTC_ICDICPR5_SSII0_SHIFT               (12u)
+#define INTC_ICDICPR5_SSIRXI0_SHIFT             (13u)
+#define INTC_ICDICPR5_SSITXI0_SHIFT             (14u)
+#define INTC_ICDICPR5_SSII1_SHIFT               (15u)
+#define INTC_ICDICPR5_SSIRXI1_SHIFT             (16u)
+#define INTC_ICDICPR5_SSITXI1_SHIFT             (17u)
+#define INTC_ICDICPR5_SSII2_SHIFT               (18u)
+#define INTC_ICDICPR5_SSIRTI2_SHIFT             (19u)
+#define INTC_ICDICPR5_SSII3_SHIFT               (20u)
+#define INTC_ICDICPR5_SSIRXI3_SHIFT             (21u)
+#define INTC_ICDICPR5_SSITXI3_SHIFT             (22u)
+#define INTC_ICDICPR5_SSII4_SHIFT               (23u)
+#define INTC_ICDICPR5_SSIRTI4_SHIFT             (24u)
+#define INTC_ICDICPR5_SSII5_SHIFT               (25u)
+#define INTC_ICDICPR5_SSIRXI5_SHIFT             (26u)
+#define INTC_ICDICPR5_SSITXI5_SHIFT             (27u)
+#define INTC_ICDICPR5_SPDIFI_SHIFT              (28u)
+#define INTC_ICDICPR5_INTIICTEI0_SHIFT          (29u)
+#define INTC_ICDICPR5_INTIICRI0_SHIFT           (30u)
+#define INTC_ICDICPR5_INTIICTI0_SHIFT           (31u)
+
+#define INTC_ICDICPR6_INTIICSPI0_SHIFT          (0u)
+#define INTC_ICDICPR6_INTIICSTI0_SHIFT          (1u)
+#define INTC_ICDICPR6_INTIICNAKI0_SHIFT         (2u)
+#define INTC_ICDICPR6_INTIICALI0_SHIFT          (3u)
+#define INTC_ICDICPR6_INTIICTMOI0_SHIFT         (4u)
+#define INTC_ICDICPR6_INTIICTEI1_SHIFT          (5u)
+#define INTC_ICDICPR6_INTIICRI1_SHIFT           (6u)
+#define INTC_ICDICPR6_INTIICTI1_SHIFT           (7u)
+#define INTC_ICDICPR6_INTIICSPI1_SHIFT          (8u)
+#define INTC_ICDICPR6_INTIICSTI1_SHIFT          (9u)
+#define INTC_ICDICPR6_INTIICNAKI1_SHIFT         (10u)
+#define INTC_ICDICPR6_INTIICALI1_SHIFT          (11u)
+#define INTC_ICDICPR6_INTIICTMOI1_SHIFT         (12u)
+#define INTC_ICDICPR6_INTIICTEI2_SHIFT          (13u)
+#define INTC_ICDICPR6_INTIICRI2_SHIFT           (14u)
+#define INTC_ICDICPR6_INTIICTI2_SHIFT           (15u)
+#define INTC_ICDICPR6_INTIICSPI2_SHIFT          (16u)
+#define INTC_ICDICPR6_INTIICSTI2_SHIFT          (17u)
+#define INTC_ICDICPR6_INTIICNAKI2_SHIFT         (18u)
+#define INTC_ICDICPR6_INTIICALI2_SHIFT          (19u)
+#define INTC_ICDICPR6_INTIICTMOI2_SHIFT         (20u)
+#define INTC_ICDICPR6_INTIICTEI3_SHIFT          (21u)
+#define INTC_ICDICPR6_INTIICRI3_SHIFT           (22u)
+#define INTC_ICDICPR6_INTIICTI3_SHIFT           (23u)
+#define INTC_ICDICPR6_INTIICSPI3_SHIFT          (24u)
+#define INTC_ICDICPR6_INTIICSTI3_SHIFT          (25u)
+#define INTC_ICDICPR6_INTIICNAKI3_SHIFT         (26u)
+#define INTC_ICDICPR6_INTIICALI3_SHIFT          (27u)
+#define INTC_ICDICPR6_INTIICTMOI3_SHIFT         (28u)
+#define INTC_ICDICPR6_BRI0_SHIFT                (29u)
+#define INTC_ICDICPR6_ERI0_SHIFT                (30u)
+#define INTC_ICDICPR6_RXI0_SHIFT                (31u)
+
+#define INTC_ICDICPR7_TXI0_SHIFT                (0u)
+#define INTC_ICDICPR7_BRI1_SHIFT                (1u)
+#define INTC_ICDICPR7_ERI1_SHIFT                (2u)
+#define INTC_ICDICPR7_RXI1_SHIFT                (3u)
+#define INTC_ICDICPR7_TXI1_SHIFT                (4u)
+#define INTC_ICDICPR7_BRI2_SHIFT                (5u)
+#define INTC_ICDICPR7_ERI2_SHIFT                (6u)
+#define INTC_ICDICPR7_RXI2_SHIFT                (7u)
+#define INTC_ICDICPR7_TXI2_SHIFT                (8u)
+#define INTC_ICDICPR7_BRI3_SHIFT                (9u)
+#define INTC_ICDICPR7_ERI3_SHIFT                (10u)
+#define INTC_ICDICPR7_RXI3_SHIFT                (11u)
+#define INTC_ICDICPR7_TXI3_SHIFT                (12u)
+#define INTC_ICDICPR7_BRI4_SHIFT                (13u)
+#define INTC_ICDICPR7_ERI4_SHIFT                (14u)
+#define INTC_ICDICPR7_RXI4_SHIFT                (15u)
+#define INTC_ICDICPR7_TXI4_SHIFT                (16u)
+#define INTC_ICDICPR7_BRI5_SHIFT                (17u)
+#define INTC_ICDICPR7_ERI5_SHIFT                (18u)
+#define INTC_ICDICPR7_RXI5_SHIFT                (19u)
+#define INTC_ICDICPR7_TXI5_SHIFT                (20u)
+#define INTC_ICDICPR7_BRI6_SHIFT                (21u)
+#define INTC_ICDICPR7_ERI6_SHIFT                (22u)
+#define INTC_ICDICPR7_RXI6_SHIFT                (23u)
+#define INTC_ICDICPR7_TXI6_SHIFT                (24u)
+#define INTC_ICDICPR7_BRI7_SHIFT                (25u)
+#define INTC_ICDICPR7_ERI7_SHIFT                (26u)
+#define INTC_ICDICPR7_RXI7_SHIFT                (27u)
+#define INTC_ICDICPR7_TXI7_SHIFT                (28u)
+#define INTC_ICDICPR7_INTRCANGERR_SHIFT         (29u)
+#define INTC_ICDICPR7_INTRCANGRECC_SHIFT        (30u)
+#define INTC_ICDICPR7_INTRCAN0REC_SHIFT         (31u)
+
+#define INTC_ICDICPR8_INTRCAN0ERR_SHIFT         (0u)
+#define INTC_ICDICPR8_INTRCAN0TRX_SHIFT         (1u)
+#define INTC_ICDICPR8_INTRCAN1REC_SHIFT         (2u)
+#define INTC_ICDICPR8_INTRCAN1ERR_SHIFT         (3u)
+#define INTC_ICDICPR8_INTRCAN1TRX_SHIFT         (4u)
+#define INTC_ICDICPR8_INTRCAN2REC_SHIFT         (5u)
+#define INTC_ICDICPR8_INTRCAN2ERR_SHIFT         (6u)
+#define INTC_ICDICPR8_INTRCAN2TRX_SHIFT         (7u)
+#define INTC_ICDICPR8_INTRCAN3REC_SHIFT         (8u)
+#define INTC_ICDICPR8_INTRCAN3ERR_SHIFT         (9u)
+#define INTC_ICDICPR8_INTRCAN3TRX_SHIFT         (10u)
+#define INTC_ICDICPR8_INTRCAN4REC_SHIFT         (11u)
+#define INTC_ICDICPR8_INTRCAN4ERR_SHIFT         (12u)
+#define INTC_ICDICPR8_INTRCAN4TRX_SHIFT         (13u)
+#define INTC_ICDICPR8_SPEI0_SHIFT               (14u)
+#define INTC_ICDICPR8_SPRI0_SHIFT               (15u)
+#define INTC_ICDICPR8_SPTI0_SHIFT               (16u)
+#define INTC_ICDICPR8_SPEI1_SHIFT               (17u)
+#define INTC_ICDICPR8_SPRI1_SHIFT               (18u)
+#define INTC_ICDICPR8_SPTI1_SHIFT               (19u)
+#define INTC_ICDICPR8_SPEI2_SHIFT               (20u)
+#define INTC_ICDICPR8_SPRI2_SHIFT               (21u)
+#define INTC_ICDICPR8_SPTI2_SHIFT               (22u)
+#define INTC_ICDICPR8_SPEI3_SHIFT               (23u)
+#define INTC_ICDICPR8_SPRI3_SHIFT               (24u)
+#define INTC_ICDICPR8_SPTI3_SHIFT               (25u)
+#define INTC_ICDICPR8_SPEI4_SHIFT               (26u)
+#define INTC_ICDICPR8_SPRI4_SHIFT               (27u)
+#define INTC_ICDICPR8_SPTI4_SHIFT               (28u)
+#define INTC_ICDICPR8_IEBBTD_SHIFT              (29u)
+#define INTC_ICDICPR8_IEBBTERR_SHIFT            (30u)
+#define INTC_ICDICPR8_IEBBTSTA_SHIFT            (31u)
+
+#define INTC_ICDICPR9_IEBBTV_SHIFT              (0u)
+#define INTC_ICDICPR9_ISY_SHIFT                 (1u)
+#define INTC_ICDICPR9_IERR_SHIFT                (2u)
+#define INTC_ICDICPR9_ITARG_SHIFT               (3u)
+#define INTC_ICDICPR9_ISEC_SHIFT                (4u)
+#define INTC_ICDICPR9_IBUF_SHIFT                (5u)
+#define INTC_ICDICPR9_IREADY_SHIFT              (6u)
+#define INTC_ICDICPR9_FLSTE_SHIFT               (7u)
+#define INTC_ICDICPR9_FLTENDI_SHIFT             (8u)
+#define INTC_ICDICPR9_FLTREQ0I_SHIFT            (9u)
+#define INTC_ICDICPR9_FLTREQ1I_SHIFT            (10u)
+#define INTC_ICDICPR9_MMC0_SHIFT                (11u)
+#define INTC_ICDICPR9_MMC1_SHIFT                (12u)
+#define INTC_ICDICPR9_MMC2_SHIFT                (13u)
+#define INTC_ICDICPR9_SDHI0_3_SHIFT             (14u)
+#define INTC_ICDICPR9_SDHI0_0_SHIFT             (15u)
+#define INTC_ICDICPR9_SDHI0_1_SHIFT             (16u)
+#define INTC_ICDICPR9_SDHI1_3_SHIFT             (17u)
+#define INTC_ICDICPR9_SDHI1_0_SHIFT             (18u)
+#define INTC_ICDICPR9_SDHI1_1_SHIFT             (19u)
+#define INTC_ICDICPR9_ARM_SHIFT                 (20u)
+#define INTC_ICDICPR9_PRD_SHIFT                 (21u)
+#define INTC_ICDICPR9_CUP_SHIFT                 (22u)
+#define INTC_ICDICPR9_SCUAI0_SHIFT              (23u)
+#define INTC_ICDICPR9_SCUAI1_SHIFT              (24u)
+#define INTC_ICDICPR9_SCUFDI0_SHIFT             (25u)
+#define INTC_ICDICPR9_SCUFDI1_SHIFT             (26u)
+#define INTC_ICDICPR9_SCUFDI2_SHIFT             (27u)
+#define INTC_ICDICPR9_SCUFDI3_SHIFT             (28u)
+#define INTC_ICDICPR9_SCUFUI0_SHIFT             (29u)
+#define INTC_ICDICPR9_SCUFUI1_SHIFT             (30u)
+#define INTC_ICDICPR9_SCUFUI2_SHIFT             (31u)
+
+#define INTC_ICDICPR10_SCUFUI3_SHIFT            (0u)
+#define INTC_ICDICPR10_SCUDVI0_SHIFT            (1u)
+#define INTC_ICDICPR10_SCUDVI1_SHIFT            (2u)
+#define INTC_ICDICPR10_SCUDVI2_SHIFT            (3u)
+#define INTC_ICDICPR10_SCUDVI3_SHIFT            (4u)
+#define INTC_ICDICPR10_MLB_CINT_SHIFT           (5u)
+#define INTC_ICDICPR10_MLB_SINT_SHIFT           (6u)
+#define INTC_ICDICPR10_DRC0_SHIFT               (7u)
+#define INTC_ICDICPR10_DRC1_SHIFT               (8u)
+#define INTC_ICDICPR10_LINI0_INT_T_SHIFT        (11u)
+#define INTC_ICDICPR10_LINI0_INT_R_SHIFT        (12u)
+#define INTC_ICDICPR10_LINI0_INT_S_SHIFT        (13u)
+#define INTC_ICDICPR10_LINI0_INT_M_SHIFT        (14u)
+#define INTC_ICDICPR10_LINI1_INT_T_SHIFT        (15u)
+#define INTC_ICDICPR10_LINI1_INT_R_SHIFT        (16u)
+#define INTC_ICDICPR10_LINI1_INT_S_SHIFT        (17u)
+#define INTC_ICDICPR10_LINI1_INT_M_SHIFT        (18u)
+#define INTC_ICDICPR10_ERI0_SHIFT               (27u)
+#define INTC_ICDICPR10_RXI0_SHIFT               (28u)
+#define INTC_ICDICPR10_TXI0_SHIFT               (29u)
+#define INTC_ICDICPR10_TEI0_SHIFT               (30u)
+#define INTC_ICDICPR10_ERI1_SHIFT               (31u)
+
+#define INTC_ICDICPR11_RXI1_SHIFT               (0u)
+#define INTC_ICDICPR11_TXI1_SHIFT               (1u)
+#define INTC_ICDICPR11_TEI1_SHIFT               (2u)
+#define INTC_ICDICPR11_AVBI_DATA_SHIFT          (3u)
+#define INTC_ICDICPR11_AVBI_ERROR_SHIFT         (4u)
+#define INTC_ICDICPR11_AVBI_MANAGE_SHIFT        (5u)
+#define INTC_ICDICPR11_AVBI_MAC_SHIFT           (6u)
+#define INTC_ICDICPR11_ETHERI_SHIFT             (7u)
+#define INTC_ICDICPR11_CEUI_SHIFT               (12u)
+#define INTC_ICDICPR11_H2XMLB_ERRINT_SHIFT      (29u)
+#define INTC_ICDICPR11_H2XIC1_ERRINT_SHIFT      (30u)
+#define INTC_ICDICPR11_X2HPERI1_ERRINT_SHIFT    (31u)
+
+#define INTC_ICDICPR12_X2HPERI2_ERRINT_SHIFT    (0u)
+#define INTC_ICDICPR12_X2HPERI34_ERRINT_SHIFT   (1u)
+#define INTC_ICDICPR12_X2HPERI5_ERRINT_SHIFT    (2u)
+#define INTC_ICDICPR12_X2HPERI67_ERRINT_SHIFT   (3u)
+#define INTC_ICDICPR12_X2HDBGR_ERRINT_SHIFT     (4u)
+#define INTC_ICDICPR12_X2HBSC_ERRINT_SHIFT      (5u)
+#define INTC_ICDICPR12_X2HSPI1_ERRINT_SHIFT     (6u)
+#define INTC_ICDICPR12_X2HSPI2_ERRINT_SHIFT     (7u)
+#define INTC_ICDICPR12_PRRI_SHIFT               (8u)
+#define INTC_ICDICPR12_IFEI0_SHIFT              (9u)
+#define INTC_ICDICPR12_OFFI0_SHIFT              (10u)
+#define INTC_ICDICPR12_PFVEI0_SHIFT             (11u)
+#define INTC_ICDICPR12_IFEI1_SHIFT              (12u)
+#define INTC_ICDICPR12_OFFI1_SHIFT              (13u)
+#define INTC_ICDICPR12_PFVEI1_SHIFT             (14u)
+
+#define INTC_ICDICPR13_TINT0_SHIFT              (0u)
+#define INTC_ICDICPR13_TINT1_SHIFT              (1u)
+#define INTC_ICDICPR13_TINT2_SHIFT              (2u)
+#define INTC_ICDICPR13_TINT3_SHIFT              (3u)
+#define INTC_ICDICPR13_TINT4_SHIFT              (4u)
+#define INTC_ICDICPR13_TINT5_SHIFT              (5u)
+#define INTC_ICDICPR13_TINT6_SHIFT              (6u)
+#define INTC_ICDICPR13_TINT7_SHIFT              (7u)
+#define INTC_ICDICPR13_TINT8_SHIFT              (8u)
+#define INTC_ICDICPR13_TINT9_SHIFT              (9u)
+#define INTC_ICDICPR13_TINT10_SHIFT             (10u)
+#define INTC_ICDICPR13_TINT11_SHIFT             (11u)
+#define INTC_ICDICPR13_TINT12_SHIFT             (12u)
+#define INTC_ICDICPR13_TINT13_SHIFT             (13u)
+#define INTC_ICDICPR13_TINT14_SHIFT             (14u)
+#define INTC_ICDICPR13_TINT15_SHIFT             (15u)
+#define INTC_ICDICPR13_TINT16_SHIFT             (16u)
+#define INTC_ICDICPR13_TINT17_SHIFT             (17u)
+#define INTC_ICDICPR13_TINT18_SHIFT             (18u)
+#define INTC_ICDICPR13_TINT19_SHIFT             (19u)
+#define INTC_ICDICPR13_TINT20_SHIFT             (20u)
+#define INTC_ICDICPR13_TINT21_SHIFT             (21u)
+#define INTC_ICDICPR13_TINT22_SHIFT             (22u)
+#define INTC_ICDICPR13_TINT23_SHIFT             (23u)
+#define INTC_ICDICPR13_TINT24_SHIFT             (24u)
+#define INTC_ICDICPR13_TINT25_SHIFT             (25u)
+#define INTC_ICDICPR13_TINT26_SHIFT             (26u)
+#define INTC_ICDICPR13_TINT27_SHIFT             (27u)
+#define INTC_ICDICPR13_TINT28_SHIFT             (28u)
+#define INTC_ICDICPR13_TINT29_SHIFT             (29u)
+#define INTC_ICDICPR13_TINT30_SHIFT             (30u)
+#define INTC_ICDICPR13_TINT31_SHIFT             (31u)
+
+#define INTC_ICDICPR14_TINT32_SHIFT             (0u)
+#define INTC_ICDICPR14_TINT33_SHIFT             (1u)
+#define INTC_ICDICPR14_TINT34_SHIFT             (2u)
+#define INTC_ICDICPR14_TINT35_SHIFT             (3u)
+#define INTC_ICDICPR14_TINT36_SHIFT             (4u)
+#define INTC_ICDICPR14_TINT37_SHIFT             (5u)
+#define INTC_ICDICPR14_TINT38_SHIFT             (6u)
+#define INTC_ICDICPR14_TINT39_SHIFT             (7u)
+#define INTC_ICDICPR14_TINT40_SHIFT             (8u)
+#define INTC_ICDICPR14_TINT41_SHIFT             (9u)
+#define INTC_ICDICPR14_TINT42_SHIFT             (10u)
+#define INTC_ICDICPR14_TINT43_SHIFT             (11u)
+#define INTC_ICDICPR14_TINT44_SHIFT             (12u)
+#define INTC_ICDICPR14_TINT45_SHIFT             (13u)
+#define INTC_ICDICPR14_TINT46_SHIFT             (14u)
+#define INTC_ICDICPR14_TINT47_SHIFT             (15u)
+#define INTC_ICDICPR14_TINT48_SHIFT             (16u)
+#define INTC_ICDICPR14_TINT49_SHIFT             (17u)
+#define INTC_ICDICPR14_TINT50_SHIFT             (18u)
+#define INTC_ICDICPR14_TINT51_SHIFT             (19u)
+#define INTC_ICDICPR14_TINT52_SHIFT             (20u)
+#define INTC_ICDICPR14_TINT53_SHIFT             (21u)
+#define INTC_ICDICPR14_TINT54_SHIFT             (22u)
+#define INTC_ICDICPR14_TINT55_SHIFT             (23u)
+#define INTC_ICDICPR14_TINT56_SHIFT             (24u)
+#define INTC_ICDICPR14_TINT57_SHIFT             (25u)
+#define INTC_ICDICPR14_TINT58_SHIFT             (26u)
+#define INTC_ICDICPR14_TINT59_SHIFT             (27u)
+#define INTC_ICDICPR14_TINT60_SHIFT             (28u)
+#define INTC_ICDICPR14_TINT61_SHIFT             (29u)
+#define INTC_ICDICPR14_TINT62_SHIFT             (30u)
+#define INTC_ICDICPR14_TINT63_SHIFT             (31u)
+
+#define INTC_ICDICPR15_TINT64_SHIFT             (0u)
+#define INTC_ICDICPR15_TINT65_SHIFT             (1u)
+#define INTC_ICDICPR15_TINT66_SHIFT             (2u)
+#define INTC_ICDICPR15_TINT67_SHIFT             (3u)
+#define INTC_ICDICPR15_TINT68_SHIFT             (4u)
+#define INTC_ICDICPR15_TINT69_SHIFT             (5u)
+#define INTC_ICDICPR15_TINT70_SHIFT             (6u)
+#define INTC_ICDICPR15_TINT71_SHIFT             (7u)
+#define INTC_ICDICPR15_TINT72_SHIFT             (8u)
+#define INTC_ICDICPR15_TINT73_SHIFT             (9u)
+#define INTC_ICDICPR15_TINT74_SHIFT             (10u)
+#define INTC_ICDICPR15_TINT75_SHIFT             (11u)
+#define INTC_ICDICPR15_TINT76_SHIFT             (12u)
+#define INTC_ICDICPR15_TINT77_SHIFT             (13u)
+#define INTC_ICDICPR15_TINT78_SHIFT             (14u)
+#define INTC_ICDICPR15_TINT79_SHIFT             (15u)
+#define INTC_ICDICPR15_TINT80_SHIFT             (16u)
+#define INTC_ICDICPR15_TINT81_SHIFT             (17u)
+#define INTC_ICDICPR15_TINT82_SHIFT             (18u)
+#define INTC_ICDICPR15_TINT83_SHIFT             (19u)
+#define INTC_ICDICPR15_TINT84_SHIFT             (20u)
+#define INTC_ICDICPR15_TINT85_SHIFT             (21u)
+#define INTC_ICDICPR15_TINT86_SHIFT             (22u)
+#define INTC_ICDICPR15_TINT87_SHIFT             (23u)
+#define INTC_ICDICPR15_TINT88_SHIFT             (24u)
+#define INTC_ICDICPR15_TINT89_SHIFT             (25u)
+#define INTC_ICDICPR15_TINT90_SHIFT             (26u)
+#define INTC_ICDICPR15_TINT91_SHIFT             (27u)
+#define INTC_ICDICPR15_TINT92_SHIFT             (28u)
+#define INTC_ICDICPR15_TINT93_SHIFT             (29u)
+#define INTC_ICDICPR15_TINT94_SHIFT             (30u)
+#define INTC_ICDICPR15_TINT95_SHIFT             (31u)
+
+#define INTC_ICDICPR16_TINT96_SHIFT             (0u)
+#define INTC_ICDICPR16_TINT97_SHIFT             (1u)
+#define INTC_ICDICPR16_TINT98_SHIFT             (2u)
+#define INTC_ICDICPR16_TINT99_SHIFT             (3u)
+#define INTC_ICDICPR16_TINT100_SHIFT            (4u)
+#define INTC_ICDICPR16_TINT101_SHIFT            (5u)
+#define INTC_ICDICPR16_TINT102_SHIFT            (6u)
+#define INTC_ICDICPR16_TINT103_SHIFT            (7u)
+#define INTC_ICDICPR16_TINT104_SHIFT            (8u)
+#define INTC_ICDICPR16_TINT105_SHIFT            (9u)
+#define INTC_ICDICPR16_TINT106_SHIFT            (10u)
+#define INTC_ICDICPR16_TINT107_SHIFT            (11u)
+#define INTC_ICDICPR16_TINT108_SHIFT            (12u)
+#define INTC_ICDICPR16_TINT109_SHIFT            (13u)
+#define INTC_ICDICPR16_TINT110_SHIFT            (14u)
+#define INTC_ICDICPR16_TINT111_SHIFT            (15u)
+#define INTC_ICDICPR16_TINT112_SHIFT            (16u)
+#define INTC_ICDICPR16_TINT113_SHIFT            (17u)
+#define INTC_ICDICPR16_TINT114_SHIFT            (18u)
+#define INTC_ICDICPR16_TINT115_SHIFT            (19u)
+#define INTC_ICDICPR16_TINT116_SHIFT            (20u)
+#define INTC_ICDICPR16_TINT117_SHIFT            (21u)
+#define INTC_ICDICPR16_TINT118_SHIFT            (22u)
+#define INTC_ICDICPR16_TINT119_SHIFT            (23u)
+#define INTC_ICDICPR16_TINT120_SHIFT            (24u)
+#define INTC_ICDICPR16_TINT121_SHIFT            (25u)
+#define INTC_ICDICPR16_TINT122_SHIFT            (26u)
+#define INTC_ICDICPR16_TINT123_SHIFT            (27u)
+#define INTC_ICDICPR16_TINT124_SHIFT            (28u)
+#define INTC_ICDICPR16_TINT125_SHIFT            (29u)
+#define INTC_ICDICPR16_TINT126_SHIFT            (30u)
+#define INTC_ICDICPR16_TINT127_SHIFT            (31u)
+
+#define INTC_ICDICPR17_TINT128_SHIFT            (0u)
+#define INTC_ICDICPR17_TINT129_SHIFT            (1u)
+#define INTC_ICDICPR17_TINT130_SHIFT            (2u)
+#define INTC_ICDICPR17_TINT131_SHIFT            (3u)
+#define INTC_ICDICPR17_TINT132_SHIFT            (4u)
+#define INTC_ICDICPR17_TINT133_SHIFT            (5u)
+#define INTC_ICDICPR17_TINT134_SHIFT            (6u)
+#define INTC_ICDICPR17_TINT135_SHIFT            (7u)
+#define INTC_ICDICPR17_TINT136_SHIFT            (8u)
+#define INTC_ICDICPR17_TINT137_SHIFT            (9u)
+#define INTC_ICDICPR17_TINT138_SHIFT            (10u)
+#define INTC_ICDICPR17_TINT139_SHIFT            (11u)
+#define INTC_ICDICPR17_TINT140_SHIFT            (12u)
+#define INTC_ICDICPR17_TINT141_SHIFT            (13u)
+#define INTC_ICDICPR17_TINT142_SHIFT            (14u)
+#define INTC_ICDICPR17_TINT143_SHIFT            (15u)
+#define INTC_ICDICPR17_TINT144_SHIFT            (16u)
+#define INTC_ICDICPR17_TINT145_SHIFT            (17u)
+#define INTC_ICDICPR17_TINT146_SHIFT            (18u)
+#define INTC_ICDICPR17_TINT147_SHIFT            (19u)
+#define INTC_ICDICPR17_TINT148_SHIFT            (20u)
+#define INTC_ICDICPR17_TINT149_SHIFT            (21u)
+#define INTC_ICDICPR17_TINT150_SHIFT            (22u)
+#define INTC_ICDICPR17_TINT151_SHIFT            (23u)
+#define INTC_ICDICPR17_TINT152_SHIFT            (24u)
+#define INTC_ICDICPR17_TINT153_SHIFT            (25u)
+#define INTC_ICDICPR17_TINT154_SHIFT            (26u)
+#define INTC_ICDICPR17_TINT155_SHIFT            (27u)
+#define INTC_ICDICPR17_TINT156_SHIFT            (28u)
+#define INTC_ICDICPR17_TINT157_SHIFT            (29u)
+#define INTC_ICDICPR17_TINT158_SHIFT            (30u)
+#define INTC_ICDICPR17_TINT159_SHIFT            (31u)
+
+#define INTC_ICDICPR18_TINT160_SHIFT            (0u)
+#define INTC_ICDICPR18_TINT161_SHIFT            (1u)
+#define INTC_ICDICPR18_TINT162_SHIFT            (2u)
+#define INTC_ICDICPR18_TINT163_SHIFT            (3u)
+#define INTC_ICDICPR18_TINT164_SHIFT            (4u)
+#define INTC_ICDICPR18_TINT165_SHIFT            (5u)
+#define INTC_ICDICPR18_TINT166_SHIFT            (6u)
+#define INTC_ICDICPR18_TINT167_SHIFT            (7u)
+#define INTC_ICDICPR18_TINT168_SHIFT            (8u)
+#define INTC_ICDICPR18_TINT169_SHIFT            (9u)
+#define INTC_ICDICPR18_TINT170_SHIFT            (10u)
+
+#define INTC_ICDABR0_SW0_SHIFT                  (0u)
+#define INTC_ICDABR0_SW1_SHIFT                  (1u)
+#define INTC_ICDABR0_SW2_SHIFT                  (2u)
+#define INTC_ICDABR0_SW3_SHIFT                  (3u)
+#define INTC_ICDABR0_SW4_SHIFT                  (4u)
+#define INTC_ICDABR0_SW5_SHIFT                  (5u)
+#define INTC_ICDABR0_SW6_SHIFT                  (6u)
+#define INTC_ICDABR0_SW7_SHIFT                  (7u)
+#define INTC_ICDABR0_SW8_SHIFT                  (8u)
+#define INTC_ICDABR0_SW9_SHIFT                  (9u)
+#define INTC_ICDABR0_SW10_SHIFT                 (10u)
+#define INTC_ICDABR0_SW11_SHIFT                 (11u)
+#define INTC_ICDABR0_SW12_SHIFT                 (12u)
+#define INTC_ICDABR0_SW13_SHIFT                 (13u)
+#define INTC_ICDABR0_SW14_SHIFT                 (14u)
+#define INTC_ICDABR0_SW15_SHIFT                 (15u)
+#define INTC_ICDABR0_PMUIRQ0_SHIFT              (16u)
+#define INTC_ICDABR0_COMMRX0_SHIFT              (17u)
+#define INTC_ICDABR0_COMMTX0_SHIFT              (18u)
+#define INTC_ICDABR0_CTIIRQ0_SHIFT              (19u)
+
+#define INTC_ICDABR1_IRQ0_SHIFT                 (0u)
+#define INTC_ICDABR1_IRQ1_SHIFT                 (1u)
+#define INTC_ICDABR1_IRQ2_SHIFT                 (2u)
+#define INTC_ICDABR1_IRQ3_SHIFT                 (3u)
+#define INTC_ICDABR1_IRQ4_SHIFT                 (4u)
+#define INTC_ICDABR1_IRQ5_SHIFT                 (5u)
+#define INTC_ICDABR1_IRQ6_SHIFT                 (6u)
+#define INTC_ICDABR1_IRQ7_SHIFT                 (7u)
+#define INTC_ICDABR1_PL310ERR_SHIFT             (8u)
+#define INTC_ICDABR1_DMAINT0_SHIFT              (9u)
+#define INTC_ICDABR1_DMAINT1_SHIFT              (10u)
+#define INTC_ICDABR1_DMAINT2_SHIFT              (11u)
+#define INTC_ICDABR1_DMAINT3_SHIFT              (12u)
+#define INTC_ICDABR1_DMAINT4_SHIFT              (13u)
+#define INTC_ICDABR1_DMAINT5_SHIFT              (14u)
+#define INTC_ICDABR1_DMAINT6_SHIFT              (15u)
+#define INTC_ICDABR1_DMAINT7_SHIFT              (16u)
+#define INTC_ICDABR1_DMAINT8_SHIFT              (17u)
+#define INTC_ICDABR1_DMAINT9_SHIFT              (18u)
+#define INTC_ICDABR1_DMAINT10_SHIFT             (19u)
+#define INTC_ICDABR1_DMAINT11_SHIFT             (20u)
+#define INTC_ICDABR1_DMAINT12_SHIFT             (21u)
+#define INTC_ICDABR1_DMAINT13_SHIFT             (22u)
+#define INTC_ICDABR1_DMAINT14_SHIFT             (23u)
+#define INTC_ICDABR1_DMAINT15_SHIFT             (24u)
+#define INTC_ICDABR1_DMAERR_SHIFT               (25u)
+
+#define INTC_ICDABR2_USBI0_SHIFT                (9u)
+#define INTC_ICDABR2_USBI1_SHIFT                (10u)
+#define INTC_ICDABR2_S0_VI_VSYNC0_SHIFT         (11u)
+#define INTC_ICDABR2_S0_LO_VSYNC0_SHIFT         (12u)
+#define INTC_ICDABR2_S0_VSYNCERR0_SHIFT         (13u)
+#define INTC_ICDABR2_GR3_VLINE0_SHIFT           (14u)
+#define INTC_ICDABR2_S0_VFIELD0_SHIFT           (15u)
+#define INTC_ICDABR2_IV1_VBUFERR0_SHIFT         (16u)
+#define INTC_ICDABR2_IV3_VBUFERR0_SHIFT         (17u)
+#define INTC_ICDABR2_IV5_VBUFERR0_SHIFT         (18u)
+#define INTC_ICDABR2_IV6_VBUFERR0_SHIFT         (19u)
+#define INTC_ICDABR2_S0_WLINE0_SHIFT            (20u)
+#define INTC_ICDABR2_S1_VI_VSYNC0_SHIFT         (21u)
+#define INTC_ICDABR2_S1_LO_VSYNC0_SHIFT         (22u)
+#define INTC_ICDABR2_S1_VSYNCERR0_SHIFT         (23u)
+#define INTC_ICDABR2_S1_VFIELD0_SHIFT           (24u)
+#define INTC_ICDABR2_IV2_VBUFERR0_SHIFT         (25u)
+#define INTC_ICDABR2_IV4_VBUFERR0_SHIFT         (26u)
+#define INTC_ICDABR2_S1_WLINE0_SHIFT            (27u)
+#define INTC_ICDABR2_OIR_VI_VSYNC0_SHIFT        (28u)
+#define INTC_ICDABR2_OIR_LO_VSYNC0_SHIFT        (29u)
+#define INTC_ICDABR2_OIR_VSYNCERR0_SHIFT        (30u)
+#define INTC_ICDABR2_OIR_VFIELD0_SHIFT          (31u)
+
+#define INTC_ICDABR3_IV7_VBUFERR0_SHIFT         (0u)
+#define INTC_ICDABR3_IV8_VBUFERR0_SHIFT         (1u)
+#define INTC_ICDABR3_S0_VI_VSYNC1_SHIFT         (3u)
+#define INTC_ICDABR3_S0_LO_VSYNC1_SHIFT         (4u)
+#define INTC_ICDABR3_S0_VSYNCERR1_SHIFT         (5u)
+#define INTC_ICDABR3_GR3_VLINE1_SHIFT           (6u)
+#define INTC_ICDABR3_S0_VFIELD1_SHIFT           (7u)
+#define INTC_ICDABR3_IV1_VBUFERR1_SHIFT         (8u)
+#define INTC_ICDABR3_IV3_VBUFERR1_SHIFT         (9u)
+#define INTC_ICDABR3_IV5_VBUFERR1_SHIFT         (10u)
+#define INTC_ICDABR3_IV6_VBUFERR1_SHIFT         (11u)
+#define INTC_ICDABR3_S0_WLINE1_SHIFT            (12u)
+#define INTC_ICDABR3_S1_VI_VSYNC1_SHIFT         (13u)
+#define INTC_ICDABR3_S1_LO_VSYNC1_SHIFT         (14u)
+#define INTC_ICDABR3_S1_VSYNCERR1_SHIFT         (15u)
+#define INTC_ICDABR3_S1_VFIELD1_SHIFT           (16u)
+#define INTC_ICDABR3_IV2_VBUFERR1_SHIFT         (17u)
+#define INTC_ICDABR3_IV4_VBUFERR1_SHIFT         (18u)
+#define INTC_ICDABR3_S1_WLINE1_SHIFT            (19u)
+#define INTC_ICDABR3_OIR_VI_VSYNC1_SHIFT        (20u)
+#define INTC_ICDABR3_OIR_LO_VSYNC1_SHIFT        (21u)
+#define INTC_ICDABR3_OIR_VLINE1_SHIFT           (22u)
+#define INTC_ICDABR3_OIR_VFIELD1_SHIFT          (23u)
+#define INTC_ICDABR3_IV7_VBUFERR1_SHIFT         (24u)
+#define INTC_ICDABR3_IV8_VBUFERR1_SHIFT         (25u)
+#define INTC_ICDABR3_IMRDI_SHIFT                (27u)
+#define INTC_ICDABR3_IMR2I0_SHIFT               (28u)
+#define INTC_ICDABR3_IMR2I1_SHIFT               (29u)
+#define INTC_ICDABR3_JEDI_SHIFT                 (30u)
+#define INTC_ICDABR3_JDTI_SHIFT                 (31u)
+
+#define INTC_ICDABR4_CMP0_SHIFT                 (0u)
+#define INTC_ICDABR4_CMP1_SHIFT                 (1u)
+#define INTC_ICDABR4_INT0_SHIFT                 (2u)
+#define INTC_ICDABR4_INT1_SHIFT                 (3u)
+#define INTC_ICDABR4_INT2_SHIFT                 (4u)
+#define INTC_ICDABR4_INT3_SHIFT                 (5u)
+#define INTC_ICDABR4_OSTM0TINT_SHIFT            (6u)
+#define INTC_ICDABR4_OSTM1TINT_SHIFT            (7u)
+#define INTC_ICDABR4_CMI_SHIFT                  (8u)
+#define INTC_ICDABR4_WTOUT_SHIFT                (9u)
+#define INTC_ICDABR4_ITI_SHIFT                  (10u)
+#define INTC_ICDABR4_TGI0A_SHIFT                (11u)
+#define INTC_ICDABR4_TGI0B_SHIFT                (12u)
+#define INTC_ICDABR4_TGI0C_SHIFT                (13u)
+#define INTC_ICDABR4_TGI0D_SHIFT                (14u)
+#define INTC_ICDABR4_TGI0V_SHIFT                (15u)
+#define INTC_ICDABR4_TGI0E_SHIFT                (16u)
+#define INTC_ICDABR4_TGI0F_SHIFT                (17u)
+#define INTC_ICDABR4_TGI1A_SHIFT                (18u)
+#define INTC_ICDABR4_TGI1B_SHIFT                (19u)
+#define INTC_ICDABR4_TGI1V_SHIFT                (20u)
+#define INTC_ICDABR4_TGI1U_SHIFT                (21u)
+#define INTC_ICDABR4_TGI2A_SHIFT                (22u)
+#define INTC_ICDABR4_TGI2B_SHIFT                (23u)
+#define INTC_ICDABR4_TGI2V_SHIFT                (24u)
+#define INTC_ICDABR4_TGI2U_SHIFT                (25u)
+#define INTC_ICDABR4_TGI3A_SHIFT                (26u)
+#define INTC_ICDABR4_TGI3B_SHIFT                (27u)
+#define INTC_ICDABR4_TGI3C_SHIFT                (28u)
+#define INTC_ICDABR4_TGI3D_SHIFT                (29u)
+#define INTC_ICDABR4_TGI3V_SHIFT                (30u)
+#define INTC_ICDABR4_TGI4A_SHIFT                (31u)
+
+#define INTC_ICDABR5_TGI4B_SHIFT                (0u)
+#define INTC_ICDABR5_TGI4C_SHIFT                (1u)
+#define INTC_ICDABR5_TGI4D_SHIFT                (2u)
+#define INTC_ICDABR5_TGI4V_SHIFT                (3u)
+#define INTC_ICDABR5_CMI1_SHIFT                 (4u)
+#define INTC_ICDABR5_CMI2_SHIFT                 (5u)
+#define INTC_ICDABR5_SGDEI0_SHIFT               (6u)
+#define INTC_ICDABR5_SGDEI1_SHIFT               (7u)
+#define INTC_ICDABR5_SGDEI2_SHIFT               (8u)
+#define INTC_ICDABR5_SGDEI3_SHIFT               (9u)
+#define INTC_ICDABR5_ADI_SHIFT                  (10u)
+#define INTC_ICDABR5_LMTI_SHIFT                 (11u)
+#define INTC_ICDABR5_SSII0_SHIFT                (12u)
+#define INTC_ICDABR5_SSIRXI0_SHIFT              (13u)
+#define INTC_ICDABR5_SSITXI0_SHIFT              (14u)
+#define INTC_ICDABR5_SSII1_SHIFT                (15u)
+#define INTC_ICDABR5_SSIRXI1_SHIFT              (16u)
+#define INTC_ICDABR5_SSITXI1_SHIFT              (17u)
+#define INTC_ICDABR5_SSII2_SHIFT                (18u)
+#define INTC_ICDABR5_SSIRTI2_SHIFT              (19u)
+#define INTC_ICDABR5_SSII3_SHIFT                (20u)
+#define INTC_ICDABR5_SSIRXI3_SHIFT              (21u)
+#define INTC_ICDABR5_SSITXI3_SHIFT              (22u)
+#define INTC_ICDABR5_SSII4_SHIFT                (23u)
+#define INTC_ICDABR5_SSIRTI4_SHIFT              (24u)
+#define INTC_ICDABR5_SSII5_SHIFT                (25u)
+#define INTC_ICDABR5_SSIRXI5_SHIFT              (26u)
+#define INTC_ICDABR5_SSITXI5_SHIFT              (27u)
+#define INTC_ICDABR5_SPDIFI_SHIFT               (28u)
+#define INTC_ICDABR5_INTIICTEI0_SHIFT           (29u)
+#define INTC_ICDABR5_INTIICRI0_SHIFT            (30u)
+#define INTC_ICDABR5_INTIICTI0_SHIFT            (31u)
+
+#define INTC_ICDABR6_INTIICSPI0_SHIFT           (0u)
+#define INTC_ICDABR6_INTIICSTI0_SHIFT           (1u)
+#define INTC_ICDABR6_INTIICNAKI0_SHIFT          (2u)
+#define INTC_ICDABR6_INTIICALI0_SHIFT           (3u)
+#define INTC_ICDABR6_INTIICTMOI0_SHIFT          (4u)
+#define INTC_ICDABR6_INTIICTEI1_SHIFT           (5u)
+#define INTC_ICDABR6_INTIICRI1_SHIFT            (6u)
+#define INTC_ICDABR6_INTIICTI1_SHIFT            (7u)
+#define INTC_ICDABR6_INTIICSPI1_SHIFT           (8u)
+#define INTC_ICDABR6_INTIICSTI1_SHIFT           (9u)
+#define INTC_ICDABR6_INTIICNAKI1_SHIFT          (10u)
+#define INTC_ICDABR6_INTIICALI1_SHIFT           (11u)
+#define INTC_ICDABR6_INTIICTMOI1_SHIFT          (12u)
+#define INTC_ICDABR6_INTIICTEI2_SHIFT           (13u)
+#define INTC_ICDABR6_INTIICRI2_SHIFT            (14u)
+#define INTC_ICDABR6_INTIICTI2_SHIFT            (15u)
+#define INTC_ICDABR6_INTIICSPI2_SHIFT           (16u)
+#define INTC_ICDABR6_INTIICSTI2_SHIFT           (17u)
+#define INTC_ICDABR6_INTIICNAKI2_SHIFT          (18u)
+#define INTC_ICDABR6_INTIICALI2_SHIFT           (19u)
+#define INTC_ICDABR6_INTIICTMOI2_SHIFT          (20u)
+#define INTC_ICDABR6_INTIICTEI3_SHIFT           (21u)
+#define INTC_ICDABR6_INTIICRI3_SHIFT            (22u)
+#define INTC_ICDABR6_INTIICTI3_SHIFT            (23u)
+#define INTC_ICDABR6_INTIICSPI3_SHIFT           (24u)
+#define INTC_ICDABR6_INTIICSTI3_SHIFT           (25u)
+#define INTC_ICDABR6_INTIICNAKI3_SHIFT          (26u)
+#define INTC_ICDABR6_INTIICALI3_SHIFT           (27u)
+#define INTC_ICDABR6_INTIICTMOI3_SHIFT          (28u)
+#define INTC_ICDABR6_BRI0_SHIFT                 (29u)
+#define INTC_ICDABR6_ERI0_SHIFT                 (30u)
+#define INTC_ICDABR6_RXI0_SHIFT                 (31u)
+
+#define INTC_ICDABR7_TXI0_SHIFT                 (0u)
+#define INTC_ICDABR7_BRI1_SHIFT                 (1u)
+#define INTC_ICDABR7_ERI1_SHIFT                 (2u)
+#define INTC_ICDABR7_RXI1_SHIFT                 (3u)
+#define INTC_ICDABR7_TXI1_SHIFT                 (4u)
+#define INTC_ICDABR7_BRI2_SHIFT                 (5u)
+#define INTC_ICDABR7_ERI2_SHIFT                 (6u)
+#define INTC_ICDABR7_RXI2_SHIFT                 (7u)
+#define INTC_ICDABR7_TXI2_SHIFT                 (8u)
+#define INTC_ICDABR7_BRI3_SHIFT                 (9u)
+#define INTC_ICDABR7_ERI3_SHIFT                 (10u)
+#define INTC_ICDABR7_RXI3_SHIFT                 (11u)
+#define INTC_ICDABR7_TXI3_SHIFT                 (12u)
+#define INTC_ICDABR7_BRI4_SHIFT                 (13u)
+#define INTC_ICDABR7_ERI4_SHIFT                 (14u)
+#define INTC_ICDABR7_RXI4_SHIFT                 (15u)
+#define INTC_ICDABR7_TXI4_SHIFT                 (16u)
+#define INTC_ICDABR7_BRI5_SHIFT                 (17u)
+#define INTC_ICDABR7_ERI5_SHIFT                 (18u)
+#define INTC_ICDABR7_RXI5_SHIFT                 (19u)
+#define INTC_ICDABR7_TXI5_SHIFT                 (20u)
+#define INTC_ICDABR7_BRI6_SHIFT                 (21u)
+#define INTC_ICDABR7_ERI6_SHIFT                 (22u)
+#define INTC_ICDABR7_RXI6_SHIFT                 (23u)
+#define INTC_ICDABR7_TXI6_SHIFT                 (24u)
+#define INTC_ICDABR7_BRI7_SHIFT                 (25u)
+#define INTC_ICDABR7_ERI7_SHIFT                 (26u)
+#define INTC_ICDABR7_RXI7_SHIFT                 (27u)
+#define INTC_ICDABR7_TXI7_SHIFT                 (28u)
+#define INTC_ICDABR7_INTRCANGERR_SHIFT          (29u)
+#define INTC_ICDABR7_INTRCANGRECC_SHIFT         (30u)
+#define INTC_ICDABR7_INTRCAN0REC_SHIFT          (31u)
+
+#define INTC_ICDABR8_INTRCAN0ERR_SHIFT          (0u)
+#define INTC_ICDABR8_INTRCAN0TRX_SHIFT          (1u)
+#define INTC_ICDABR8_INTRCAN1REC_SHIFT          (2u)
+#define INTC_ICDABR8_INTRCAN1ERR_SHIFT          (3u)
+#define INTC_ICDABR8_INTRCAN1TRX_SHIFT          (4u)
+#define INTC_ICDABR8_INTRCAN2REC_SHIFT          (5u)
+#define INTC_ICDABR8_INTRCAN2ERR_SHIFT          (6u)
+#define INTC_ICDABR8_INTRCAN2TRX_SHIFT          (7u)
+#define INTC_ICDABR8_INTRCAN3REC_SHIFT          (8u)
+#define INTC_ICDABR8_INTRCAN3ERR_SHIFT          (9u)
+#define INTC_ICDABR8_INTRCAN3TRX_SHIFT          (10u)
+#define INTC_ICDABR8_INTRCAN4REC_SHIFT          (11u)
+#define INTC_ICDABR8_INTRCAN4ERR_SHIFT          (12u)
+#define INTC_ICDABR8_INTRCAN4TRX_SHIFT          (13u)
+#define INTC_ICDABR8_SPEI0_SHIFT                (14u)
+#define INTC_ICDABR8_SPRI0_SHIFT                (15u)
+#define INTC_ICDABR8_SPTI0_SHIFT                (16u)
+#define INTC_ICDABR8_SPEI1_SHIFT                (17u)
+#define INTC_ICDABR8_SPRI1_SHIFT                (18u)
+#define INTC_ICDABR8_SPTI1_SHIFT                (19u)
+#define INTC_ICDABR8_SPEI2_SHIFT                (20u)
+#define INTC_ICDABR8_SPRI2_SHIFT                (21u)
+#define INTC_ICDABR8_SPTI2_SHIFT                (22u)
+#define INTC_ICDABR8_SPEI3_SHIFT                (23u)
+#define INTC_ICDABR8_SPRI3_SHIFT                (24u)
+#define INTC_ICDABR8_SPTI3_SHIFT                (25u)
+#define INTC_ICDABR8_SPEI4_SHIFT                (26u)
+#define INTC_ICDABR8_SPRI4_SHIFT                (27u)
+#define INTC_ICDABR8_SPTI4_SHIFT                (28u)
+#define INTC_ICDABR8_IEBBTD_SHIFT               (29u)
+#define INTC_ICDABR8_IEBBTERR_SHIFT             (30u)
+#define INTC_ICDABR8_IEBBTSTA_SHIFT             (31u)
+
+#define INTC_ICDABR9_IEBBTV_SHIFT               (0u)
+#define INTC_ICDABR9_ISY_SHIFT                  (1u)
+#define INTC_ICDABR9_IERR_SHIFT                 (2u)
+#define INTC_ICDABR9_ITARG_SHIFT                (3u)
+#define INTC_ICDABR9_ISEC_SHIFT                 (4u)
+#define INTC_ICDABR9_IBUF_SHIFT                 (5u)
+#define INTC_ICDABR9_IREADY_SHIFT               (6u)
+#define INTC_ICDABR9_FLSTE_SHIFT                (7u)
+#define INTC_ICDABR9_FLTENDI_SHIFT              (8u)
+#define INTC_ICDABR9_FLTREQ0I_SHIFT             (9u)
+#define INTC_ICDABR9_FLTREQ1I_SHIFT             (10u)
+#define INTC_ICDABR9_MMC0_SHIFT                 (11u)
+#define INTC_ICDABR9_MMC1_SHIFT                 (12u)
+#define INTC_ICDABR9_MMC2_SHIFT                 (13u)
+#define INTC_ICDABR9_SDHI0_3_SHIFT              (14u)
+#define INTC_ICDABR9_SDHI0_0_SHIFT              (15u)
+#define INTC_ICDABR9_SDHI0_1_SHIFT              (16u)
+#define INTC_ICDABR9_SDHI1_3_SHIFT              (17u)
+#define INTC_ICDABR9_SDHI1_0_SHIFT              (18u)
+#define INTC_ICDABR9_SDHI1_1_SHIFT              (19u)
+#define INTC_ICDABR9_ARM_SHIFT                  (20u)
+#define INTC_ICDABR9_PRD_SHIFT                  (21u)
+#define INTC_ICDABR9_CUP_SHIFT                  (22u)
+#define INTC_ICDABR9_SCUAI0_SHIFT               (23u)
+#define INTC_ICDABR9_SCUAI1_SHIFT               (24u)
+#define INTC_ICDABR9_SCUFDI0_SHIFT              (25u)
+#define INTC_ICDABR9_SCUFDI1_SHIFT              (26u)
+#define INTC_ICDABR9_SCUFDI2_SHIFT              (27u)
+#define INTC_ICDABR9_SCUFDI3_SHIFT              (28u)
+#define INTC_ICDABR9_SCUFUI0_SHIFT              (29u)
+#define INTC_ICDABR9_SCUFUI1_SHIFT              (30u)
+#define INTC_ICDABR9_SCUFUI2_SHIFT              (31u)
+
+#define INTC_ICDABR10_SCUFUI3_SHIFT             (0u)
+#define INTC_ICDABR10_SCUDVI0_SHIFT             (1u)
+#define INTC_ICDABR10_SCUDVI1_SHIFT             (2u)
+#define INTC_ICDABR10_SCUDVI2_SHIFT             (3u)
+#define INTC_ICDABR10_SCUDVI3_SHIFT             (4u)
+#define INTC_ICDABR10_MLB_CINT_SHIFT            (5u)
+#define INTC_ICDABR10_MLB_SINT_SHIFT            (6u)
+#define INTC_ICDABR10_DRC0_SHIFT                (7u)
+#define INTC_ICDABR10_DRC1_SHIFT                (8u)
+#define INTC_ICDABR10_LINI0_INT_T_SHIFT         (11u)
+#define INTC_ICDABR10_LINI0_INT_R_SHIFT         (12u)
+#define INTC_ICDABR10_LINI0_INT_S_SHIFT         (13u)
+#define INTC_ICDABR10_LINI0_INT_M_SHIFT         (14u)
+#define INTC_ICDABR10_LINI1_INT_T_SHIFT         (15u)
+#define INTC_ICDABR10_LINI1_INT_R_SHIFT         (16u)
+#define INTC_ICDABR10_LINI1_INT_S_SHIFT         (17u)
+#define INTC_ICDABR10_LINI1_INT_M_SHIFT         (18u)
+#define INTC_ICDABR10_ERI0_SHIFT                (27u)
+#define INTC_ICDABR10_RXI0_SHIFT                (28u)
+#define INTC_ICDABR10_TXI0_SHIFT                (29u)
+#define INTC_ICDABR10_TEI0_SHIFT                (30u)
+#define INTC_ICDABR10_ERI1_SHIFT                (31u)
+
+#define INTC_ICDABR11_RXI1_SHIFT                (0u)
+#define INTC_ICDABR11_TXI1_SHIFT                (1u)
+#define INTC_ICDABR11_TEI1_SHIFT                (2u)
+#define INTC_ICDABR11_AVBI_DATA_SHIFT           (3u)
+#define INTC_ICDABR11_AVBI_ERROR_SHIFT          (4u)
+#define INTC_ICDABR11_AVBI_MANAGE_SHIFT         (5u)
+#define INTC_ICDABR11_AVBI_MAC_SHIFT            (6u)
+#define INTC_ICDABR11_ETHERI_SHIFT              (7u)
+#define INTC_ICDABR11_CEUI_SHIFT                (12u)
+#define INTC_ICDABR11_H2XMLB_ERRINT_SHIFT       (29u)
+#define INTC_ICDABR11_H2XIC1_ERRINT_SHIFT       (30u)
+#define INTC_ICDABR11_X2HPERI1_ERRINT_SHIFT     (31u)
+
+#define INTC_ICDABR12_X2HPERI2_ERRINT_SHIFT     (0u)
+#define INTC_ICDABR12_X2HPERI34_ERRINT_SHIFT    (1u)
+#define INTC_ICDABR12_X2HPERI5_ERRINT_SHIFT     (2u)
+#define INTC_ICDABR12_X2HPERI67_ERRINT_SHIFT    (3u)
+#define INTC_ICDABR12_X2HDBGR_ERRINT_SHIFT      (4u)
+#define INTC_ICDABR12_X2HBSC_ERRINT_SHIFT       (5u)
+#define INTC_ICDABR12_X2HSPI1_ERRINT_SHIFT      (6u)
+#define INTC_ICDABR12_X2HSPI2_ERRINT_SHIFT      (7u)
+#define INTC_ICDABR12_PRRI_SHIFT                (8u)
+#define INTC_ICDABR12_IFEI0_SHIFT               (9u)
+#define INTC_ICDABR12_OFFI0_SHIFT               (10u)
+#define INTC_ICDABR12_PFVEI0_SHIFT              (11u)
+#define INTC_ICDABR12_IFEI1_SHIFT               (12u)
+#define INTC_ICDABR12_OFFI1_SHIFT               (13u)
+#define INTC_ICDABR12_PFVEI1_SHIFT              (14u)
+
+#define INTC_ICDABR13_TINT0_SHIFT               (0u)
+#define INTC_ICDABR13_TINT1_SHIFT               (1u)
+#define INTC_ICDABR13_TINT2_SHIFT               (2u)
+#define INTC_ICDABR13_TINT3_SHIFT               (3u)
+#define INTC_ICDABR13_TINT4_SHIFT               (4u)
+#define INTC_ICDABR13_TINT5_SHIFT               (5u)
+#define INTC_ICDABR13_TINT6_SHIFT               (6u)
+#define INTC_ICDABR13_TINT7_SHIFT               (7u)
+#define INTC_ICDABR13_TINT8_SHIFT               (8u)
+#define INTC_ICDABR13_TINT9_SHIFT               (9u)
+#define INTC_ICDABR13_TINT10_SHIFT              (10u)
+#define INTC_ICDABR13_TINT11_SHIFT              (11u)
+#define INTC_ICDABR13_TINT12_SHIFT              (12u)
+#define INTC_ICDABR13_TINT13_SHIFT              (13u)
+#define INTC_ICDABR13_TINT14_SHIFT              (14u)
+#define INTC_ICDABR13_TINT15_SHIFT              (15u)
+#define INTC_ICDABR13_TINT16_SHIFT              (16u)
+#define INTC_ICDABR13_TINT17_SHIFT              (17u)
+#define INTC_ICDABR13_TINT18_SHIFT              (18u)
+#define INTC_ICDABR13_TINT19_SHIFT              (19u)
+#define INTC_ICDABR13_TINT20_SHIFT              (20u)
+#define INTC_ICDABR13_TINT21_SHIFT              (21u)
+#define INTC_ICDABR13_TINT22_SHIFT              (22u)
+#define INTC_ICDABR13_TINT23_SHIFT              (23u)
+#define INTC_ICDABR13_TINT24_SHIFT              (24u)
+#define INTC_ICDABR13_TINT25_SHIFT              (25u)
+#define INTC_ICDABR13_TINT26_SHIFT              (26u)
+#define INTC_ICDABR13_TINT27_SHIFT              (27u)
+#define INTC_ICDABR13_TINT28_SHIFT              (28u)
+#define INTC_ICDABR13_TINT29_SHIFT              (29u)
+#define INTC_ICDABR13_TINT30_SHIFT              (30u)
+#define INTC_ICDABR13_TINT31_SHIFT              (31u)
+
+#define INTC_ICDABR14_TINT32_SHIFT              (0u)
+#define INTC_ICDABR14_TINT33_SHIFT              (1u)
+#define INTC_ICDABR14_TINT34_SHIFT              (2u)
+#define INTC_ICDABR14_TINT35_SHIFT              (3u)
+#define INTC_ICDABR14_TINT36_SHIFT              (4u)
+#define INTC_ICDABR14_TINT37_SHIFT              (5u)
+#define INTC_ICDABR14_TINT38_SHIFT              (6u)
+#define INTC_ICDABR14_TINT39_SHIFT              (7u)
+#define INTC_ICDABR14_TINT40_SHIFT              (8u)
+#define INTC_ICDABR14_TINT41_SHIFT              (9u)
+#define INTC_ICDABR14_TINT42_SHIFT              (10u)
+#define INTC_ICDABR14_TINT43_SHIFT              (11u)
+#define INTC_ICDABR14_TINT44_SHIFT              (12u)
+#define INTC_ICDABR14_TINT45_SHIFT              (13u)
+#define INTC_ICDABR14_TINT46_SHIFT              (14u)
+#define INTC_ICDABR14_TINT47_SHIFT              (15u)
+#define INTC_ICDABR14_TINT48_SHIFT              (16u)
+#define INTC_ICDABR14_TINT49_SHIFT              (17u)
+#define INTC_ICDABR14_TINT50_SHIFT              (18u)
+#define INTC_ICDABR14_TINT51_SHIFT              (19u)
+#define INTC_ICDABR14_TINT52_SHIFT              (20u)
+#define INTC_ICDABR14_TINT53_SHIFT              (21u)
+#define INTC_ICDABR14_TINT54_SHIFT              (22u)
+#define INTC_ICDABR14_TINT55_SHIFT              (23u)
+#define INTC_ICDABR14_TINT56_SHIFT              (24u)
+#define INTC_ICDABR14_TINT57_SHIFT              (25u)
+#define INTC_ICDABR14_TINT58_SHIFT              (26u)
+#define INTC_ICDABR14_TINT59_SHIFT              (27u)
+#define INTC_ICDABR14_TINT60_SHIFT              (28u)
+#define INTC_ICDABR14_TINT61_SHIFT              (29u)
+#define INTC_ICDABR14_TINT62_SHIFT              (30u)
+#define INTC_ICDABR14_TINT63_SHIFT              (31u)
+
+#define INTC_ICDABR15_TINT64_SHIFT              (0u)
+#define INTC_ICDABR15_TINT65_SHIFT              (1u)
+#define INTC_ICDABR15_TINT66_SHIFT              (2u)
+#define INTC_ICDABR15_TINT67_SHIFT              (3u)
+#define INTC_ICDABR15_TINT68_SHIFT              (4u)
+#define INTC_ICDABR15_TINT69_SHIFT              (5u)
+#define INTC_ICDABR15_TINT70_SHIFT              (6u)
+#define INTC_ICDABR15_TINT71_SHIFT              (7u)
+#define INTC_ICDABR15_TINT72_SHIFT              (8u)
+#define INTC_ICDABR15_TINT73_SHIFT              (9u)
+#define INTC_ICDABR15_TINT74_SHIFT              (10u)
+#define INTC_ICDABR15_TINT75_SHIFT              (11u)
+#define INTC_ICDABR15_TINT76_SHIFT              (12u)
+#define INTC_ICDABR15_TINT77_SHIFT              (13u)
+#define INTC_ICDABR15_TINT78_SHIFT              (14u)
+#define INTC_ICDABR15_TINT79_SHIFT              (15u)
+#define INTC_ICDABR15_TINT80_SHIFT              (16u)
+#define INTC_ICDABR15_TINT81_SHIFT              (17u)
+#define INTC_ICDABR15_TINT82_SHIFT              (18u)
+#define INTC_ICDABR15_TINT83_SHIFT              (19u)
+#define INTC_ICDABR15_TINT84_SHIFT              (20u)
+#define INTC_ICDABR15_TINT85_SHIFT              (21u)
+#define INTC_ICDABR15_TINT86_SHIFT              (22u)
+#define INTC_ICDABR15_TINT87_SHIFT              (23u)
+#define INTC_ICDABR15_TINT88_SHIFT              (24u)
+#define INTC_ICDABR15_TINT89_SHIFT              (25u)
+#define INTC_ICDABR15_TINT90_SHIFT              (26u)
+#define INTC_ICDABR15_TINT91_SHIFT              (27u)
+#define INTC_ICDABR15_TINT92_SHIFT              (28u)
+#define INTC_ICDABR15_TINT93_SHIFT              (29u)
+#define INTC_ICDABR15_TINT94_SHIFT              (30u)
+#define INTC_ICDABR15_TINT95_SHIFT              (31u)
+
+#define INTC_ICDABR16_TINT96_SHIFT              (0u)
+#define INTC_ICDABR16_TINT97_SHIFT              (1u)
+#define INTC_ICDABR16_TINT98_SHIFT              (2u)
+#define INTC_ICDABR16_TINT99_SHIFT              (3u)
+#define INTC_ICDABR16_TINT100_SHIFT             (4u)
+#define INTC_ICDABR16_TINT101_SHIFT             (5u)
+#define INTC_ICDABR16_TINT102_SHIFT             (6u)
+#define INTC_ICDABR16_TINT103_SHIFT             (7u)
+#define INTC_ICDABR16_TINT104_SHIFT             (8u)
+#define INTC_ICDABR16_TINT105_SHIFT             (9u)
+#define INTC_ICDABR16_TINT106_SHIFT             (10u)
+#define INTC_ICDABR16_TINT107_SHIFT             (11u)
+#define INTC_ICDABR16_TINT108_SHIFT             (12u)
+#define INTC_ICDABR16_TINT109_SHIFT             (13u)
+#define INTC_ICDABR16_TINT110_SHIFT             (14u)
+#define INTC_ICDABR16_TINT111_SHIFT             (15u)
+#define INTC_ICDABR16_TINT112_SHIFT             (16u)
+#define INTC_ICDABR16_TINT113_SHIFT             (17u)
+#define INTC_ICDABR16_TINT114_SHIFT             (18u)
+#define INTC_ICDABR16_TINT115_SHIFT             (19u)
+#define INTC_ICDABR16_TINT116_SHIFT             (20u)
+#define INTC_ICDABR16_TINT117_SHIFT             (21u)
+#define INTC_ICDABR16_TINT118_SHIFT             (22u)
+#define INTC_ICDABR16_TINT119_SHIFT             (23u)
+#define INTC_ICDABR16_TINT120_SHIFT             (24u)
+#define INTC_ICDABR16_TINT121_SHIFT             (25u)
+#define INTC_ICDABR16_TINT122_SHIFT             (26u)
+#define INTC_ICDABR16_TINT123_SHIFT             (27u)
+#define INTC_ICDABR16_TINT124_SHIFT             (28u)
+#define INTC_ICDABR16_TINT125_SHIFT             (29u)
+#define INTC_ICDABR16_TINT126_SHIFT             (30u)
+#define INTC_ICDABR16_TINT127_SHIFT             (31u)
+
+#define INTC_ICDABR17_TINT128_SHIFT             (0u)
+#define INTC_ICDABR17_TINT129_SHIFT             (1u)
+#define INTC_ICDABR17_TINT130_SHIFT             (2u)
+#define INTC_ICDABR17_TINT131_SHIFT             (3u)
+#define INTC_ICDABR17_TINT132_SHIFT             (4u)
+#define INTC_ICDABR17_TINT133_SHIFT             (5u)
+#define INTC_ICDABR17_TINT134_SHIFT             (6u)
+#define INTC_ICDABR17_TINT135_SHIFT             (7u)
+#define INTC_ICDABR17_TINT136_SHIFT             (8u)
+#define INTC_ICDABR17_TINT137_SHIFT             (9u)
+#define INTC_ICDABR17_TINT138_SHIFT             (10u)
+#define INTC_ICDABR17_TINT139_SHIFT             (11u)
+#define INTC_ICDABR17_TINT140_SHIFT             (12u)
+#define INTC_ICDABR17_TINT141_SHIFT             (13u)
+#define INTC_ICDABR17_TINT142_SHIFT             (14u)
+#define INTC_ICDABR17_TINT143_SHIFT             (15u)
+#define INTC_ICDABR17_TINT144_SHIFT             (16u)
+#define INTC_ICDABR17_TINT145_SHIFT             (17u)
+#define INTC_ICDABR17_TINT146_SHIFT             (18u)
+#define INTC_ICDABR17_TINT147_SHIFT             (19u)
+#define INTC_ICDABR17_TINT148_SHIFT             (20u)
+#define INTC_ICDABR17_TINT149_SHIFT             (21u)
+#define INTC_ICDABR17_TINT150_SHIFT             (22u)
+#define INTC_ICDABR17_TINT151_SHIFT             (23u)
+#define INTC_ICDABR17_TINT152_SHIFT             (24u)
+#define INTC_ICDABR17_TINT153_SHIFT             (25u)
+#define INTC_ICDABR17_TINT154_SHIFT             (26u)
+#define INTC_ICDABR17_TINT155_SHIFT             (27u)
+#define INTC_ICDABR17_TINT156_SHIFT             (28u)
+#define INTC_ICDABR17_TINT157_SHIFT             (29u)
+#define INTC_ICDABR17_TINT158_SHIFT             (30u)
+#define INTC_ICDABR17_TINT159_SHIFT             (31u)
+
+#define INTC_ICDABR18_TINT160_SHIFT             (0u)
+#define INTC_ICDABR18_TINT161_SHIFT             (1u)
+#define INTC_ICDABR18_TINT162_SHIFT             (2u)
+#define INTC_ICDABR18_TINT163_SHIFT             (3u)
+#define INTC_ICDABR18_TINT164_SHIFT             (4u)
+#define INTC_ICDABR18_TINT165_SHIFT             (5u)
+#define INTC_ICDABR18_TINT166_SHIFT             (6u)
+#define INTC_ICDABR18_TINT167_SHIFT             (7u)
+#define INTC_ICDABR18_TINT168_SHIFT             (8u)
+#define INTC_ICDABR18_TINT169_SHIFT             (9u)
+#define INTC_ICDABR18_TINT170_SHIFT             (10u)
+
+#define INTC_ICDIPR0_SW0_SHIFT                  (0u)
+#define INTC_ICDIPR0_SW1_SHIFT                  (8u)
+#define INTC_ICDIPR0_SW2_SHIFT                  (16u)
+#define INTC_ICDIPR0_SW3_SHIFT                  (24u)
+
+#define INTC_ICDIPR1_SW4_SHIFT                  (0u)
+#define INTC_ICDIPR1_SW5_SHIFT                  (8u)
+#define INTC_ICDIPR1_SW6_SHIFT                  (16u)
+#define INTC_ICDIPR1_SW7_SHIFT                  (24u)
+
+#define INTC_ICDIPR2_SW8_SHIFT                  (0u)
+#define INTC_ICDIPR2_SW9_SHIFT                  (8u)
+#define INTC_ICDIPR2_SW10_SHIFT                 (16u)
+#define INTC_ICDIPR2_SW11_SHIFT                 (24u)
+
+#define INTC_ICDIPR3_SW12_SHIFT                 (0u)
+#define INTC_ICDIPR3_SW13_SHIFT                 (8u)
+#define INTC_ICDIPR3_SW14_SHIFT                 (16u)
+#define INTC_ICDIPR3_SW15_SHIFT                 (24u)
+
+#define INTC_ICDIPR4_PMUIRQ0_SHIFT              (0u)
+#define INTC_ICDIPR4_COMMRX0_SHIFT              (8u)
+#define INTC_ICDIPR4_COMMTX0_SHIFT              (16u)
+#define INTC_ICDIPR4_CTIIRQ0_SHIFT              (24u)
+
+#define INTC_ICDIPR8_IRQ0_SHIFT                 (0u)
+#define INTC_ICDIPR8_IRQ1_SHIFT                 (8u)
+#define INTC_ICDIPR8_IRQ2_SHIFT                 (16u)
+#define INTC_ICDIPR8_IRQ3_SHIFT                 (24u)
+
+#define INTC_ICDIPR9_IRQ4_SHIFT                 (0u)
+#define INTC_ICDIPR9_IRQ5_SHIFT                 (8u)
+#define INTC_ICDIPR9_IRQ6_SHIFT                 (16u)
+#define INTC_ICDIPR9_IRQ7_SHIFT                 (24u)
+
+#define INTC_ICDIPR10_PL310ERR_SHIFT            (0u)
+#define INTC_ICDIPR10_DMAINT0_SHIFT             (8u)
+#define INTC_ICDIPR10_DMAINT1_SHIFT             (16u)
+#define INTC_ICDIPR10_DMAINT2_SHIFT             (24u)
+
+#define INTC_ICDIPR11_DMAINT3_SHIFT             (0u)
+#define INTC_ICDIPR11_DMAINT4_SHIFT             (8u)
+#define INTC_ICDIPR11_DMAINT5_SHIFT             (16u)
+#define INTC_ICDIPR11_DMAINT6_SHIFT             (24u)
+
+#define INTC_ICDIPR12_DMAINT7_SHIFT             (0u)
+#define INTC_ICDIPR12_DMAINT8_SHIFT             (8u)
+#define INTC_ICDIPR12_DMAINT9_SHIFT             (16u)
+#define INTC_ICDIPR12_DMAINT10_SHIFT            (24u)
+
+#define INTC_ICDIPR13_DMAINT11_SHIFT            (0u)
+#define INTC_ICDIPR13_DMAINT12_SHIFT            (8u)
+#define INTC_ICDIPR13_DMAINT13_SHIFT            (16u)
+#define INTC_ICDIPR13_DMAINT14_SHIFT            (24u)
+
+#define INTC_ICDIPR14_DMAINT15_SHIFT            (0u)
+#define INTC_ICDIPR14_DMAERR_SHIFT              (8u)
+
+#define INTC_ICDIPR18_USBI0_SHIFT               (8u)
+#define INTC_ICDIPR18_USBI1_SHIFT               (16u)
+#define INTC_ICDIPR18_S0_VI_VSYNC0_SHIFT        (24u)
+
+#define INTC_ICDIPR19_S0_LO_VSYNC0_SHIFT        (0u)
+#define INTC_ICDIPR19_S0_VSYNCERR0_SHIFT        (8u)
+#define INTC_ICDIPR19_GR3_VLINE0_SHIFT          (16u)
+#define INTC_ICDIPR19_S0_VFIELD0_SHIFT          (24u)
+
+#define INTC_ICDIPR20_IV1_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDIPR20_IV3_VBUFERR0_SHIFT        (8u)
+#define INTC_ICDIPR20_IV5_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDIPR20_IV6_VBUFERR0_SHIFT        (24u)
+
+#define INTC_ICDIPR21_S0_WLINE0_SHIFT           (0u)
+#define INTC_ICDIPR21_S1_VI_VSYNC0_SHIFT        (8u)
+#define INTC_ICDIPR21_S1_LO_VSYNC0_SHIFT        (16u)
+#define INTC_ICDIPR21_S1_VSYNCERR0_SHIFT        (24u)
+
+#define INTC_ICDIPR22_S1_VFIELD0_SHIFT          (0u)
+#define INTC_ICDIPR22_IV2_VBUFERR0_SHIFT        (8u)
+#define INTC_ICDIPR22_IV4_VBUFERR0_SHIFT        (16u)
+#define INTC_ICDIPR22_S1_WLINE0_SHIFT           (24u)
+
+#define INTC_ICDIPR23_OIR_VI_VSYNC0_SHIFT       (0u)
+#define INTC_ICDIPR23_OIR_LO_VSYNC0_SHIFT       (8u)
+#define INTC_ICDIPR23_OIR_VSYNCERR0_SHIFT       (16u)
+#define INTC_ICDIPR23_OIR_VFIELD0_SHIFT         (24u)
+
+#define INTC_ICDIPR24_IV7_VBUFERR0_SHIFT        (0u)
+#define INTC_ICDIPR24_IV8_VBUFERR0_SHIFT        (8u)
+#define INTC_ICDIPR24_S0_VI_VSYNC1_SHIFT        (24u)
+
+#define INTC_ICDIPR25_S0_LO_VSYNC1_SHIFT        (0u)
+#define INTC_ICDIPR25_S0_VSYNCERR1_SHIFT        (8u)
+#define INTC_ICDIPR25_GR3_VLINE1_SHIFT          (16u)
+#define INTC_ICDIPR25_S0_VFIELD1_SHIFT          (24u)
+
+#define INTC_ICDIPR26_IV1_VBUFERR1_SHIFT        (0u)
+#define INTC_ICDIPR26_IV3_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDIPR26_IV5_VBUFERR1_SHIFT        (16u)
+#define INTC_ICDIPR26_IV6_VBUFERR1_SHIFT        (24u)
+
+#define INTC_ICDIPR27_S0_WLINE1_SHIFT           (0u)
+#define INTC_ICDIPR27_S1_VI_VSYNC1_SHIFT        (8u)
+#define INTC_ICDIPR27_S1_LO_VSYNC1_SHIFT        (16u)
+#define INTC_ICDIPR27_S1_VSYNCERR1_SHIFT        (24u)
+
+#define INTC_ICDIPR28_S1_VFIELD1_SHIFT          (0u)
+#define INTC_ICDIPR28_IV2_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDIPR28_IV4_VBUFERR1_SHIFT        (16u)
+#define INTC_ICDIPR28_S1_WLINE1_SHIFT           (24u)
+
+#define INTC_ICDIPR29_OIR_VI_VSYNC1_SHIFT       (0u)
+#define INTC_ICDIPR29_OIR_LO_VSYNC1_SHIFT       (8u)
+#define INTC_ICDIPR29_OIR_VLINE1_SHIFT          (16u)
+#define INTC_ICDIPR29_OIR_VFIELD1_SHIFT         (24u)
+
+#define INTC_ICDIPR30_IV7_VBUFERR1_SHIFT        (0u)
+#define INTC_ICDIPR30_IV8_VBUFERR1_SHIFT        (8u)
+#define INTC_ICDIPR30_IMRDI_SHIFT               (24u)
+
+#define INTC_ICDIPR31_IMR2I0_SHIFT              (0u)
+#define INTC_ICDIPR31_IMR2I1_SHIFT              (8u)
+#define INTC_ICDIPR31_JEDI_SHIFT                (16u)
+#define INTC_ICDIPR31_JDTI_SHIFT                (24u)
+
+#define INTC_ICDIPR32_CMP0_SHIFT                (0u)
+#define INTC_ICDIPR32_CMP1_SHIFT                (8u)
+#define INTC_ICDIPR32_INT0_SHIFT                (16u)
+#define INTC_ICDIPR32_INT1_SHIFT                (24u)
+
+#define INTC_ICDIPR33_INT2_SHIFT                (0u)
+#define INTC_ICDIPR33_INT3_SHIFT                (8u)
+#define INTC_ICDIPR33_OSTM0TINT_SHIFT           (16u)
+#define INTC_ICDIPR33_OSTM1TINT_SHIFT           (24u)
+
+#define INTC_ICDIPR34_CMI_SHIFT                 (0u)
+#define INTC_ICDIPR34_WTOUT_SHIFT               (8u)
+#define INTC_ICDIPR34_ITI_SHIFT                 (16u)
+#define INTC_ICDIPR34_TGI0A_SHIFT               (24u)
+
+#define INTC_ICDIPR35_TGI0B_SHIFT               (0u)
+#define INTC_ICDIPR35_TGI0C_SHIFT               (8u)
+#define INTC_ICDIPR35_TGI0D_SHIFT               (16u)
+#define INTC_ICDIPR35_TGI0V_SHIFT               (24u)
+
+#define INTC_ICDIPR36_TGI0E_SHIFT               (0u)
+#define INTC_ICDIPR36_TGI0F_SHIFT               (8u)
+#define INTC_ICDIPR36_TGI1A_SHIFT               (16u)
+#define INTC_ICDIPR36_TGI1B_SHIFT               (24u)
+
+#define INTC_ICDIPR37_TGI1V_SHIFT               (0u)
+#define INTC_ICDIPR37_TGI1U_SHIFT               (8u)
+#define INTC_ICDIPR37_TGI2A_SHIFT               (16u)
+#define INTC_ICDIPR37_TGI2B_SHIFT               (24u)
+
+#define INTC_ICDIPR38_TGI2V_SHIFT               (0u)
+#define INTC_ICDIPR38_TGI2U_SHIFT               (8u)
+#define INTC_ICDIPR38_TGI3A_SHIFT               (16u)
+#define INTC_ICDIPR38_TGI3B_SHIFT               (24u)
+
+#define INTC_ICDIPR39_TGI3C_SHIFT               (0u)
+#define INTC_ICDIPR39_TGI3D_SHIFT               (8u)
+#define INTC_ICDIPR39_TGI3V_SHIFT               (16u)
+#define INTC_ICDIPR39_TGI4A_SHIFT               (24u)
+
+#define INTC_ICDIPR40_TGI4B_SHIFT               (0u)
+#define INTC_ICDIPR40_TGI4C_SHIFT               (8u)
+#define INTC_ICDIPR40_TGI4D_SHIFT               (16u)
+#define INTC_ICDIPR40_TGI4V_SHIFT               (24u)
+
+#define INTC_ICDIPR41_CMI1_SHIFT                (0u)
+#define INTC_ICDIPR41_CMI2_SHIFT                (8u)
+#define INTC_ICDIPR41_SGDEI0_SHIFT              (16u)
+#define INTC_ICDIPR41_SGDEI1_SHIFT              (24u)
+
+#define INTC_ICDIPR42_SGDEI2_SHIFT              (0u)
+#define INTC_ICDIPR42_SGDEI3_SHIFT              (8u)
+#define INTC_ICDIPR42_ADI_SHIFT                 (16u)
+#define INTC_ICDIPR42_LMTI_SHIFT                (24u)
+
+#define INTC_ICDIPR43_SSII0_SHIFT               (0u)
+#define INTC_ICDIPR43_SSIRXI0_SHIFT             (8u)
+#define INTC_ICDIPR43_SSITXI0_SHIFT             (16u)
+#define INTC_ICDIPR43_SSII1_SHIFT               (24u)
+
+#define INTC_ICDIPR44_SSIRXI1_SHIFT             (0u)
+#define INTC_ICDIPR44_SSITXI1_SHIFT             (8u)
+#define INTC_ICDIPR44_SSII2_SHIFT               (16u)
+#define INTC_ICDIPR44_SSIRTI2_SHIFT             (24u)
+
+#define INTC_ICDIPR45_SSII3_SHIFT               (0u)
+#define INTC_ICDIPR45_SSIRXI3_SHIFT             (8u)
+#define INTC_ICDIPR45_SSITXI3_SHIFT             (16u)
+#define INTC_ICDIPR45_SSII4_SHIFT               (24u)
+
+#define INTC_ICDIPR46_SSIRTI4_SHIFT             (0u)
+#define INTC_ICDIPR46_SSII5_SHIFT               (8u)
+#define INTC_ICDIPR46_SSIRXI5_SHIFT             (16u)
+#define INTC_ICDIPR46_SSITXI5_SHIFT             (24u)
+
+#define INTC_ICDIPR47_SPDIFI_SHIFT              (0u)
+#define INTC_ICDIPR47_INTIICTEI0_SHIFT          (8u)
+#define INTC_ICDIPR47_INTIICRI0_SHIFT           (16u)
+#define INTC_ICDIPR47_INTIICTI0_SHIFT           (24u)
+
+#define INTC_ICDIPR48_INTIICSPI0_SHIFT          (0u)
+#define INTC_ICDIPR48_INTIICSTI0_SHIFT          (8u)
+#define INTC_ICDIPR48_INTIICNAKI0_SHIFT         (16u)
+#define INTC_ICDIPR48_INTIICALI0_SHIFT          (24u)
+
+#define INTC_ICDIPR49_INTIICTMOI0_SHIFT         (0u)
+#define INTC_ICDIPR49_INTIICTEI1_SHIFT          (8u)
+#define INTC_ICDIPR49_INTIICRI1_SHIFT           (16u)
+#define INTC_ICDIPR49_INTIICTI1_SHIFT           (24u)
+
+#define INTC_ICDIPR50_INTIICSPI1_SHIFT          (0u)
+#define INTC_ICDIPR50_INTIICSTI1_SHIFT          (8u)
+#define INTC_ICDIPR50_INTIICNAKI1_SHIFT         (16u)
+#define INTC_ICDIPR50_INTIICALI1_SHIFT          (24u)
+
+#define INTC_ICDIPR51_INTIICTMOI1_SHIFT         (0u)
+#define INTC_ICDIPR51_INTIICTEI2_SHIFT          (8u)
+#define INTC_ICDIPR51_INTIICRI2_SHIFT           (16u)
+#define INTC_ICDIPR51_INTIICTI2_SHIFT           (24u)
+
+#define INTC_ICDIPR52_INTIICSPI2_SHIFT          (0u)
+#define INTC_ICDIPR52_INTIICSTI2_SHIFT          (8u)
+#define INTC_ICDIPR52_INTIICNAKI2_SHIFT         (16u)
+#define INTC_ICDIPR52_INTIICALI2_SHIFT          (24u)
+
+#define INTC_ICDIPR53_INTIICTMOI2_SHIFT         (0u)
+#define INTC_ICDIPR53_INTIICTEI3_SHIFT          (8u)
+#define INTC_ICDIPR53_INTIICRI3_SHIFT           (16u)
+#define INTC_ICDIPR53_INTIICTI3_SHIFT           (24u)
+
+#define INTC_ICDIPR54_INTIICSPI3_SHIFT          (0u)
+#define INTC_ICDIPR54_INTIICSTI3_SHIFT          (8u)
+#define INTC_ICDIPR54_INTIICNAKI3_SHIFT         (16u)
+#define INTC_ICDIPR54_INTIICALI3_SHIFT          (24u)
+
+#define INTC_ICDIPR55_INTIICTMOI3_SHIFT         (0u)
+#define INTC_ICDIPR55_BRI0_SHIFT                (8u)
+#define INTC_ICDIPR55_ERI0_SHIFT                (16u)
+#define INTC_ICDIPR55_RXI0_SHIFT                (24u)
+
+#define INTC_ICDIPR56_TXI0_SHIFT                (0u)
+#define INTC_ICDIPR56_BRI1_SHIFT                (8u)
+#define INTC_ICDIPR56_ERI1_SHIFT                (16u)
+#define INTC_ICDIPR56_RXI1_SHIFT                (24u)
+
+#define INTC_ICDIPR57_TXI1_SHIFT                (0u)
+#define INTC_ICDIPR57_BRI2_SHIFT                (8u)
+#define INTC_ICDIPR57_ERI2_SHIFT                (16u)
+#define INTC_ICDIPR57_RXI2_SHIFT                (24u)
+
+#define INTC_ICDIPR58_TXI2_SHIFT                (0u)
+#define INTC_ICDIPR58_BRI3_SHIFT                (8u)
+#define INTC_ICDIPR58_ERI3_SHIFT                (16u)
+#define INTC_ICDIPR58_RXI3_SHIFT                (24u)
+
+#define INTC_ICDIPR59_TXI3_SHIFT                (0u)
+#define INTC_ICDIPR59_BRI4_SHIFT                (8u)
+#define INTC_ICDIPR59_ERI4_SHIFT                (16u)
+#define INTC_ICDIPR59_RXI4_SHIFT                (24u)
+
+#define INTC_ICDIPR60_TXI4_SHIFT                (0u)
+#define INTC_ICDIPR60_BRI5_SHIFT                (8u)
+#define INTC_ICDIPR60_ERI5_SHIFT                (16u)
+#define INTC_ICDIPR60_RXI5_SHIFT                (24u)
+
+#define INTC_ICDIPR61_TXI5_SHIFT                (0u)
+#define INTC_ICDIPR61_BRI6_SHIFT                (8u)
+#define INTC_ICDIPR61_ERI6_SHIFT                (16u)
+#define INTC_ICDIPR61_RXI6_SHIFT                (24u)
+
+#define INTC_ICDIPR62_TXI6_SHIFT                (0u)
+#define INTC_ICDIPR62_BRI7_SHIFT                (8u)
+#define INTC_ICDIPR62_ERI7_SHIFT                (16u)
+#define INTC_ICDIPR62_RXI7_SHIFT                (24u)
+
+#define INTC_ICDIPR63_TXI7_SHIFT                (0u)
+#define INTC_ICDIPR63_INTRCANGERR_SHIFT         (8u)
+#define INTC_ICDIPR63_INTRCANGRECC_SHIFT        (16u)
+#define INTC_ICDIPR63_INTRCAN0REC_SHIFT         (24u)
+
+#define INTC_ICDIPR64_INTRCAN0ERR_SHIFT         (0u)
+#define INTC_ICDIPR64_INTRCAN0TRX_SHIFT         (8u)
+#define INTC_ICDIPR64_INTRCAN1REC_SHIFT         (16u)
+#define INTC_ICDIPR64_INTRCAN1ERR_SHIFT         (24u)
+
+#define INTC_ICDIPR65_INTRCAN1TRX_SHIFT         (0u)
+#define INTC_ICDIPR65_INTRCAN2REC_SHIFT         (8u)
+#define INTC_ICDIPR65_INTRCAN2ERR_SHIFT         (16u)
+#define INTC_ICDIPR65_INTRCAN2TRX_SHIFT         (24u)
+
+#define INTC_ICDIPR66_INTRCAN3REC_SHIFT         (0u)
+#define INTC_ICDIPR66_INTRCAN3ERR_SHIFT         (8u)
+#define INTC_ICDIPR66_INTRCAN3TRX_SHIFT         (16u)
+#define INTC_ICDIPR66_INTRCAN4REC_SHIFT         (24u)
+
+#define INTC_ICDIPR67_INTRCAN4ERR_SHIFT         (0u)
+#define INTC_ICDIPR67_INTRCAN4TRX_SHIFT         (8u)
+#define INTC_ICDIPR67_SPEI0_SHIFT               (16u)
+#define INTC_ICDIPR67_SPRI0_SHIFT               (24u)
+
+#define INTC_ICDIPR68_SPTI0_SHIFT               (0u)
+#define INTC_ICDIPR68_SPEI1_SHIFT               (8u)
+#define INTC_ICDIPR68_SPRI1_SHIFT               (16u)
+#define INTC_ICDIPR68_SPTI1_SHIFT               (24u)
+
+#define INTC_ICDIPR69_SPEI2_SHIFT               (0u)
+#define INTC_ICDIPR69_SPRI2_SHIFT               (8u)
+#define INTC_ICDIPR69_SPTI2_SHIFT               (16u)
+#define INTC_ICDIPR69_SPEI3_SHIFT               (24u)
+
+#define INTC_ICDIPR70_SPRI3_SHIFT               (0u)
+#define INTC_ICDIPR70_SPTI3_SHIFT               (8u)
+#define INTC_ICDIPR70_SPEI4_SHIFT               (16u)
+#define INTC_ICDIPR70_SPRI4_SHIFT               (24u)
+
+#define INTC_ICDIPR71_SPTI4_SHIFT               (0u)
+#define INTC_ICDIPR71_IEBBTD_SHIFT              (8u)
+#define INTC_ICDIPR71_IEBBTERR_SHIFT            (16u)
+#define INTC_ICDIPR71_IEBBTSTA_SHIFT            (24u)
+
+#define INTC_ICDIPR72_IEBBTV_SHIFT              (0u)
+#define INTC_ICDIPR72_ISY_SHIFT                 (8u)
+#define INTC_ICDIPR72_IERR_SHIFT                (16u)
+#define INTC_ICDIPR72_ITARG_SHIFT               (24u)
+
+#define INTC_ICDIPR73_ISEC_SHIFT                (0u)
+#define INTC_ICDIPR73_IBUF_SHIFT                (8u)
+#define INTC_ICDIPR73_IREADY_SHIFT              (16u)
+#define INTC_ICDIPR73_FLSTE_SHIFT               (24u)
+
+#define INTC_ICDIPR74_FLTENDI_SHIFT             (0u)
+#define INTC_ICDIPR74_FLTREQ0I_SHIFT            (8u)
+#define INTC_ICDIPR74_FLTREQ1I_SHIFT            (16u)
+#define INTC_ICDIPR74_MMC0_SHIFT                (24u)
+
+#define INTC_ICDIPR75_MMC1_SHIFT                (0u)
+#define INTC_ICDIPR75_MMC2_SHIFT                (8u)
+#define INTC_ICDIPR75_SDHI0_3_SHIFT             (16u)
+#define INTC_ICDIPR75_SDHI0_0_SHIFT             (24u)
+
+#define INTC_ICDIPR76_SDHI0_1_SHIFT             (0u)
+#define INTC_ICDIPR76_SDHI1_3_SHIFT             (8u)
+#define INTC_ICDIPR76_SDHI1_0_SHIFT             (16u)
+#define INTC_ICDIPR76_SDHI1_1_SHIFT             (24u)
+
+#define INTC_ICDIPR77_ARM_SHIFT                 (0u)
+#define INTC_ICDIPR77_PRD_SHIFT                 (8u)
+#define INTC_ICDIPR77_CUP_SHIFT                 (16u)
+#define INTC_ICDIPR77_SCUAI0_SHIFT              (24u)
+
+#define INTC_ICDIPR78_SCUAI1_SHIFT              (0u)
+#define INTC_ICDIPR78_SCUFDI0_SHIFT             (8u)
+#define INTC_ICDIPR78_SCUFDI1_SHIFT             (16u)
+#define INTC_ICDIPR78_SCUFDI2_SHIFT             (24u)
+
+#define INTC_ICDIPR79_SCUFDI3_SHIFT             (0u)
+#define INTC_ICDIPR79_SCUFUI0_SHIFT             (8u)
+#define INTC_ICDIPR79_SCUFUI1_SHIFT             (16u)
+#define INTC_ICDIPR79_SCUFUI2_SHIFT             (24u)
+
+#define INTC_ICDIPR80_SCUFUI3_SHIFT             (0u)
+#define INTC_ICDIPR80_SCUDVI0_SHIFT             (8u)
+#define INTC_ICDIPR80_SCUDVI1_SHIFT             (16u)
+#define INTC_ICDIPR80_SCUDVI2_SHIFT             (24u)
+
+#define INTC_ICDIPR81_SCUDVI3_SHIFT             (0u)
+#define INTC_ICDIPR81_MLB_CINT_SHIFT            (8u)
+#define INTC_ICDIPR81_MLB_SINT_SHIFT            (16u)
+#define INTC_ICDIPR81_DRC0_SHIFT                (24u)
+
+#define INTC_ICDIPR82_DRC1_SHIFT                (0u)
+#define INTC_ICDIPR82_LINI0_INT_T_SHIFT         (24u)
+
+#define INTC_ICDIPR83_LINI0_INT_R_SHIFT         (0u)
+#define INTC_ICDIPR83_LINI0_INT_S_SHIFT         (8u)
+#define INTC_ICDIPR83_LINI0_INT_M_SHIFT         (16u)
+#define INTC_ICDIPR83_LINI1_INT_T_SHIFT         (24u)
+
+#define INTC_ICDIPR84_LINI1_INT_R_SHIFT         (0u)
+#define INTC_ICDIPR84_LINI1_INT_S_SHIFT         (8u)
+#define INTC_ICDIPR84_LINI1_INT_M_SHIFT         (16u)
+
+#define INTC_ICDIPR86_ERI0_SHIFT                (24u)
+
+#define INTC_ICDIPR87_RXI0_SHIFT                (0u)
+#define INTC_ICDIPR87_TXI0_SHIFT                (8u)
+#define INTC_ICDIPR87_TEI0_SHIFT                (16u)
+#define INTC_ICDIPR87_ERI1_SHIFT                (24u)
+
+#define INTC_ICDIPR88_RXI1_SHIFT                (0u)
+#define INTC_ICDIPR88_TXI1_SHIFT                (8u)
+#define INTC_ICDIPR88_TEI1_SHIFT                (16u)
+#define INTC_ICDIPR88_AVBI_DATA_SHIFT           (24u)
+
+#define INTC_ICDIPR89_AVBI_ERROR_SHIFT          (0u)
+#define INTC_ICDIPR89_AVBI_MANAGE_SHIFT         (8u)
+#define INTC_ICDIPR89_AVBI_MAC_SHIFT            (16u)
+#define INTC_ICDIPR89_ETHERI_SHIFT              (24u)
+
+#define INTC_ICDIPR91_CEUI_SHIFT                (0u)
+
+#define INTC_ICDIPR95_H2XMLB_ERRINT_SHIFT       (8u)
+#define INTC_ICDIPR95_H2XIC1_ERRINT_SHIFT       (16u)
+#define INTC_ICDIPR95_X2HPERI1_ERRINT_SHIFT     (24u)
+
+#define INTC_ICDIPR96_X2HPERI2_ERRINT_SHIFT     (0u)
+#define INTC_ICDIPR96_X2HPERI34_ERRINT_SHIFT    (8u)
+#define INTC_ICDIPR96_X2HPERI5_ERRINT_SHIFT     (16u)
+#define INTC_ICDIPR96_X2HPERI67_ERRINT_SHIFT    (24u)
+
+#define INTC_ICDIPR97_X2HDBGR_ERRINT_SHIFT      (0u)
+#define INTC_ICDIPR97_X2HBSC_ERRINT_SHIFT       (8u)
+#define INTC_ICDIPR97_X2HSPI1_ERRINT_SHIFT      (16u)
+#define INTC_ICDIPR97_X2HSPI2_ERRINT_SHIFT      (24u)
+
+#define INTC_ICDIPR98_PRRI_SHIFT                (0u)
+#define INTC_ICDIPR98_IFEI0_SHIFT               (8u)
+#define INTC_ICDIPR98_OFFI0_SHIFT               (16u)
+#define INTC_ICDIPR98_PFVEI0_SHIFT              (24u)
+
+#define INTC_ICDIPR99_IFEI1_SHIFT               (0u)
+#define INTC_ICDIPR99_OFFI1_SHIFT               (8u)
+#define INTC_ICDIPR99_PFVEI1_SHIFT              (16u)
+
+#define INTC_ICDIPR104_TINT0_SHIFT              (0u)
+#define INTC_ICDIPR104_TINT1_SHIFT              (8u)
+#define INTC_ICDIPR104_TINT2_SHIFT              (16u)
+#define INTC_ICDIPR104_TINT3_SHIFT              (24u)
+
+#define INTC_ICDIPR105_TINT4_SHIFT              (0u)
+#define INTC_ICDIPR105_TINT5_SHIFT              (8u)
+#define INTC_ICDIPR105_TINT6_SHIFT              (16u)
+#define INTC_ICDIPR105_TINT7_SHIFT              (24u)
+
+#define INTC_ICDIPR106_TINT8_SHIFT              (0u)
+#define INTC_ICDIPR106_TINT9_SHIFT              (8u)
+#define INTC_ICDIPR106_TINT10_SHIFT             (16u)
+#define INTC_ICDIPR106_TINT11_SHIFT             (24u)
+
+#define INTC_ICDIPR107_TINT12_SHIFT             (0u)
+#define INTC_ICDIPR107_TINT13_SHIFT             (8u)
+#define INTC_ICDIPR107_TINT14_SHIFT             (16u)
+#define INTC_ICDIPR107_TINT15_SHIFT             (24u)
+
+#define INTC_ICDIPR108_TINT16_SHIFT             (0u)
+#define INTC_ICDIPR108_TINT17_SHIFT             (8u)
+#define INTC_ICDIPR108_TINT18_SHIFT             (16u)
+#define INTC_ICDIPR108_TINT19_SHIFT             (24u)
+
+#define INTC_ICDIPR109_TINT20_SHIFT             (0u)
+#define INTC_ICDIPR109_TINT21_SHIFT             (8u)
+#define INTC_ICDIPR109_TINT22_SHIFT             (16u)
+#define INTC_ICDIPR109_TINT23_SHIFT             (24u)
+
+#define INTC_ICDIPR110_TINT24_SHIFT             (0u)
+#define INTC_ICDIPR110_TINT25_SHIFT             (8u)
+#define INTC_ICDIPR110_TINT26_SHIFT             (16u)
+#define INTC_ICDIPR110_TINT27_SHIFT             (24u)
+
+#define INTC_ICDIPR111_TINT28_SHIFT             (0u)
+#define INTC_ICDIPR111_TINT29_SHIFT             (8u)
+#define INTC_ICDIPR111_TINT30_SHIFT             (16u)
+#define INTC_ICDIPR111_TINT31_SHIFT             (24u)
+
+#define INTC_ICDIPR112_TINT32_SHIFT             (0u)
+#define INTC_ICDIPR112_TINT33_SHIFT             (8u)
+#define INTC_ICDIPR112_TINT34_SHIFT             (16u)
+#define INTC_ICDIPR112_TINT35_SHIFT             (24u)
+
+#define INTC_ICDIPR113_TINT36_SHIFT             (0u)
+#define INTC_ICDIPR113_TINT37_SHIFT             (8u)
+#define INTC_ICDIPR113_TINT38_SHIFT             (16u)
+#define INTC_ICDIPR113_TINT39_SHIFT             (24u)
+
+#define INTC_ICDIPR114_TINT40_SHIFT             (0u)
+#define INTC_ICDIPR114_TINT41_SHIFT             (8u)
+#define INTC_ICDIPR114_TINT42_SHIFT             (16u)
+#define INTC_ICDIPR114_TINT43_SHIFT             (24u)
+
+#define INTC_ICDIPR115_TINT44_SHIFT             (0u)
+#define INTC_ICDIPR115_TINT45_SHIFT             (8u)
+#define INTC_ICDIPR115_TINT46_SHIFT             (16u)
+#define INTC_ICDIPR115_TINT47_SHIFT             (24u)
+
+#define INTC_ICDIPR116_TINT48_SHIFT             (0u)
+#define INTC_ICDIPR116_TINT49_SHIFT             (8u)
+#define INTC_ICDIPR116_TINT50_SHIFT             (16u)
+#define INTC_ICDIPR116_TINT51_SHIFT             (24u)
+
+#define INTC_ICDIPR117_TINT52_SHIFT             (0u)
+#define INTC_ICDIPR117_TINT53_SHIFT             (8u)
+#define INTC_ICDIPR117_TINT54_SHIFT             (16u)
+#define INTC_ICDIPR117_TINT55_SHIFT             (24u)
+
+#define INTC_ICDIPR118_TINT56_SHIFT             (0u)
+#define INTC_ICDIPR118_TINT57_SHIFT             (8u)
+#define INTC_ICDIPR118_TINT58_SHIFT             (16u)
+#define INTC_ICDIPR118_TINT59_SHIFT             (24u)
+
+#define INTC_ICDIPR119_TINT60_SHIFT             (0u)
+#define INTC_ICDIPR119_TINT61_SHIFT             (8u)
+#define INTC_ICDIPR119_TINT62_SHIFT             (16u)
+#define INTC_ICDIPR119_TINT63_SHIFT             (24u)
+
+#define INTC_ICDIPR120_TINT64_SHIFT             (0u)
+#define INTC_ICDIPR120_TINT65_SHIFT             (8u)
+#define INTC_ICDIPR120_TINT66_SHIFT             (16u)
+#define INTC_ICDIPR120_TINT67_SHIFT             (24u)
+
+#define INTC_ICDIPR121_TINT68_SHIFT             (0u)
+#define INTC_ICDIPR121_TINT69_SHIFT             (8u)
+#define INTC_ICDIPR121_TINT70_SHIFT             (16u)
+#define INTC_ICDIPR121_TINT71_SHIFT             (24u)
+
+#define INTC_ICDIPR122_TINT72_SHIFT             (0u)
+#define INTC_ICDIPR122_TINT73_SHIFT             (8u)
+#define INTC_ICDIPR122_TINT74_SHIFT             (16u)
+#define INTC_ICDIPR122_TINT75_SHIFT             (24u)
+
+#define INTC_ICDIPR123_TINT76_SHIFT             (0u)
+#define INTC_ICDIPR123_TINT77_SHIFT             (8u)
+#define INTC_ICDIPR123_TINT78_SHIFT             (16u)
+#define INTC_ICDIPR123_TINT79_SHIFT             (24u)
+
+#define INTC_ICDIPR124_TINT80_SHIFT             (0u)
+#define INTC_ICDIPR124_TINT81_SHIFT             (8u)
+#define INTC_ICDIPR124_TINT82_SHIFT             (16u)
+#define INTC_ICDIPR124_TINT83_SHIFT             (24u)
+
+#define INTC_ICDIPR125_TINT84_SHIFT             (0u)
+#define INTC_ICDIPR125_TINT85_SHIFT             (8u)
+#define INTC_ICDIPR125_TINT86_SHIFT             (16u)
+#define INTC_ICDIPR125_TINT87_SHIFT             (24u)
+
+#define INTC_ICDIPR126_TINT88_SHIFT             (0u)
+#define INTC_ICDIPR126_TINT89_SHIFT             (8u)
+#define INTC_ICDIPR126_TINT90_SHIFT             (16u)
+#define INTC_ICDIPR126_TINT91_SHIFT             (24u)
+
+#define INTC_ICDIPR127_TINT92_SHIFT             (0u)
+#define INTC_ICDIPR127_TINT93_SHIFT             (8u)
+#define INTC_ICDIPR127_TINT94_SHIFT             (16u)
+#define INTC_ICDIPR127_TINT95_SHIFT             (24u)
+
+#define INTC_ICDIPR128_TINT96_SHIFT             (0u)
+#define INTC_ICDIPR128_TINT97_SHIFT             (8u)
+#define INTC_ICDIPR128_TINT98_SHIFT             (16u)
+#define INTC_ICDIPR128_TINT99_SHIFT             (24u)
+
+#define INTC_ICDIPR129_TINT100_SHIFT            (0u)
+#define INTC_ICDIPR129_TINT101_SHIFT            (8u)
+#define INTC_ICDIPR129_TINT102_SHIFT            (16u)
+#define INTC_ICDIPR129_TINT103_SHIFT            (24u)
+
+#define INTC_ICDIPR130_TINT104_SHIFT            (0u)
+#define INTC_ICDIPR130_TINT105_SHIFT            (8u)
+#define INTC_ICDIPR130_TINT106_SHIFT            (16u)
+#define INTC_ICDIPR130_TINT107_SHIFT            (24u)
+
+#define INTC_ICDIPR131_TINT108_SHIFT            (0u)
+#define INTC_ICDIPR131_TINT109_SHIFT            (8u)
+#define INTC_ICDIPR131_TINT110_SHIFT            (16u)
+#define INTC_ICDIPR131_TINT111_SHIFT            (24u)
+
+#define INTC_ICDIPR132_TINT112_SHIFT            (0u)
+#define INTC_ICDIPR132_TINT113_SHIFT            (8u)
+#define INTC_ICDIPR132_TINT114_SHIFT            (16u)
+#define INTC_ICDIPR132_TINT115_SHIFT            (24u)
+
+#define INTC_ICDIPR133_TINT116_SHIFT            (0u)
+#define INTC_ICDIPR133_TINT117_SHIFT            (8u)
+#define INTC_ICDIPR133_TINT118_SHIFT            (16u)
+#define INTC_ICDIPR133_TINT119_SHIFT            (24u)
+
+#define INTC_ICDIPR134_TINT120_SHIFT            (0u)
+#define INTC_ICDIPR134_TINT121_SHIFT            (8u)
+#define INTC_ICDIPR134_TINT122_SHIFT            (16u)
+#define INTC_ICDIPR134_TINT123_SHIFT            (24u)
+
+#define INTC_ICDIPR135_TINT124_SHIFT            (0u)
+#define INTC_ICDIPR135_TINT125_SHIFT            (8u)
+#define INTC_ICDIPR135_TINT126_SHIFT            (16u)
+#define INTC_ICDIPR135_TINT127_SHIFT            (24u)
+
+#define INTC_ICDIPR136_TINT128_SHIFT            (0u)
+#define INTC_ICDIPR136_TINT129_SHIFT            (8u)
+#define INTC_ICDIPR136_TINT130_SHIFT            (16u)
+#define INTC_ICDIPR136_TINT131_SHIFT            (24u)
+
+#define INTC_ICDIPR137_TINT132_SHIFT            (0u)
+#define INTC_ICDIPR137_TINT133_SHIFT            (8u)
+#define INTC_ICDIPR137_TINT134_SHIFT            (16u)
+#define INTC_ICDIPR137_TINT135_SHIFT            (24u)
+
+#define INTC_ICDIPR138_TINT136_SHIFT            (0u)
+#define INTC_ICDIPR138_TINT137_SHIFT            (8u)
+#define INTC_ICDIPR138_TINT138_SHIFT            (16u)
+#define INTC_ICDIPR138_TINT139_SHIFT            (24u)
+
+#define INTC_ICDIPR139_TINT140_SHIFT            (0u)
+#define INTC_ICDIPR139_TINT141_SHIFT            (8u)
+#define INTC_ICDIPR139_TINT142_SHIFT            (16u)
+#define INTC_ICDIPR139_TINT143_SHIFT            (24u)
+
+#define INTC_ICDIPR140_TINT144_SHIFT            (0u)
+#define INTC_ICDIPR140_TINT145_SHIFT            (8u)
+#define INTC_ICDIPR140_TINT146_SHIFT            (16u)
+#define INTC_ICDIPR140_TINT147_SHIFT            (24u)
+
+#define INTC_ICDIPR141_TINT148_SHIFT            (0u)
+#define INTC_ICDIPR141_TINT149_SHIFT            (8u)
+#define INTC_ICDIPR141_TINT150_SHIFT            (16u)
+#define INTC_ICDIPR141_TINT151_SHIFT            (24u)
+
+#define INTC_ICDIPR142_TINT152_SHIFT            (0u)
+#define INTC_ICDIPR142_TINT153_SHIFT            (8u)
+#define INTC_ICDIPR142_TINT154_SHIFT            (16u)
+#define INTC_ICDIPR142_TINT155_SHIFT            (24u)
+
+#define INTC_ICDIPR143_TINT156_SHIFT            (0u)
+#define INTC_ICDIPR143_TINT157_SHIFT            (8u)
+#define INTC_ICDIPR143_TINT158_SHIFT            (16u)
+#define INTC_ICDIPR143_TINT159_SHIFT            (24u)
+
+#define INTC_ICDIPR144_TINT160_SHIFT            (0u)
+#define INTC_ICDIPR144_TINT161_SHIFT            (8u)
+#define INTC_ICDIPR144_TINT162_SHIFT            (16u)
+#define INTC_ICDIPR144_TINT163_SHIFT            (24u)
+
+#define INTC_ICDIPR145_TINT164_SHIFT            (0u)
+#define INTC_ICDIPR145_TINT165_SHIFT            (8u)
+#define INTC_ICDIPR145_TINT166_SHIFT            (16u)
+#define INTC_ICDIPR145_TINT167_SHIFT            (24u)
+
+#define INTC_ICDIPR146_TINT168_SHIFT            (0u)
+#define INTC_ICDIPR146_TINT169_SHIFT            (8u)
+#define INTC_ICDIPR146_TINT170_SHIFT            (16u)
+
+#define INTC_ICDIPTR0_SW0_SHIFT                 (0u)
+#define INTC_ICDIPTR0_SW1_SHIFT                 (8u)
+#define INTC_ICDIPTR0_SW2_SHIFT                 (16u)
+#define INTC_ICDIPTR0_SW3_SHIFT                 (24u)
+
+#define INTC_ICDIPTR1_SW4_SHIFT                 (0u)
+#define INTC_ICDIPTR1_SW5_SHIFT                 (8u)
+#define INTC_ICDIPTR1_SW6_SHIFT                 (16u)
+#define INTC_ICDIPTR1_SW7_SHIFT                 (24u)
+
+#define INTC_ICDIPTR2_SW8_SHIFT                 (0u)
+#define INTC_ICDIPTR2_SW9_SHIFT                 (8u)
+#define INTC_ICDIPTR2_SW10_SHIFT                (16u)
+#define INTC_ICDIPTR2_SW11_SHIFT                (24u)
+
+#define INTC_ICDIPTR3_SW12_SHIFT                (0u)
+#define INTC_ICDIPTR3_SW13_SHIFT                (8u)
+#define INTC_ICDIPTR3_SW14_SHIFT                (16u)
+#define INTC_ICDIPTR3_SW15_SHIFT                (24u)
+
+#define INTC_ICDIPTR4_PMUIRQ0_SHIFT             (0u)
+#define INTC_ICDIPTR4_COMMRX0_SHIFT             (8u)
+#define INTC_ICDIPTR4_COMMTX0_SHIFT             (16u)
+#define INTC_ICDIPTR4_CTIIRQ0_SHIFT             (24u)
+
+#define INTC_ICDIPTR8_IRQ0_SHIFT                (0u)
+#define INTC_ICDIPTR8_IRQ1_SHIFT                (8u)
+#define INTC_ICDIPTR8_IRQ2_SHIFT                (16u)
+#define INTC_ICDIPTR8_IRQ3_SHIFT                (24u)
+
+#define INTC_ICDIPTR9_IRQ4_SHIFT                (0u)
+#define INTC_ICDIPTR9_IRQ5_SHIFT                (8u)
+#define INTC_ICDIPTR9_IRQ6_SHIFT                (16u)
+#define INTC_ICDIPTR9_IRQ7_SHIFT                (24u)
+
+#define INTC_ICDIPTR10_PL310ERR_SHIFT           (0u)
+#define INTC_ICDIPTR10_DMAINT0_SHIFT            (8u)
+#define INTC_ICDIPTR10_DMAINT1_SHIFT            (16u)
+#define INTC_ICDIPTR10_DMAINT2_SHIFT            (24u)
+
+#define INTC_ICDIPTR11_DMAINT3_SHIFT            (0u)
+#define INTC_ICDIPTR11_DMAINT4_SHIFT            (8u)
+#define INTC_ICDIPTR11_DMAINT5_SHIFT            (16u)
+#define INTC_ICDIPTR11_DMAINT6_SHIFT            (24u)
+
+#define INTC_ICDIPTR12_DMAINT7_SHIFT            (0u)
+#define INTC_ICDIPTR12_DMAINT8_SHIFT            (8u)
+#define INTC_ICDIPTR12_DMAINT9_SHIFT            (16u)
+#define INTC_ICDIPTR12_DMAINT10_SHIFT           (24u)
+
+#define INTC_ICDIPTR13_DMAINT11_SHIFT           (0u)
+#define INTC_ICDIPTR13_DMAINT12_SHIFT           (8u)
+#define INTC_ICDIPTR13_DMAINT13_SHIFT           (16u)
+#define INTC_ICDIPTR13_DMAINT14_SHIFT           (24u)
+
+#define INTC_ICDIPTR14_DMAINT15_SHIFT           (0u)
+#define INTC_ICDIPTR14_DMAERR_SHIFT             (8u)
+
+#define INTC_ICDIPTR18_USBI0_SHIFT              (8u)
+#define INTC_ICDIPTR18_USBI1_SHIFT              (16u)
+#define INTC_ICDIPTR18_S0_VI_VSYNC0_SHIFT       (24u)
+
+#define INTC_ICDIPTR19_S0_LO_VSYNC0_SHIFT       (0u)
+#define INTC_ICDIPTR19_S0_VSYNCERR0_SHIFT       (8u)
+#define INTC_ICDIPTR19_GR3_VLINE0_SHIFT         (16u)
+#define INTC_ICDIPTR19_S0_VFIELD0_SHIFT         (24u)
+
+#define INTC_ICDIPTR20_IV1_VBUFERR0_SHIFT       (0u)
+#define INTC_ICDIPTR20_IV3_VBUFERR0_SHIFT       (8u)
+#define INTC_ICDIPTR20_IV5_VBUFERR0_SHIFT       (16u)
+#define INTC_ICDIPTR20_IV6_VBUFERR0_SHIFT       (24u)
+
+#define INTC_ICDIPTR21_S0_WLINE0_SHIFT          (0u)
+#define INTC_ICDIPTR21_S1_VI_VSYNC0_SHIFT       (8u)
+#define INTC_ICDIPTR21_S1_LO_VSYNC0_SHIFT       (16u)
+#define INTC_ICDIPTR21_S1_VSYNCERR0_SHIFT       (24u)
+
+#define INTC_ICDIPTR22_S1_VFIELD0_SHIFT         (0u)
+#define INTC_ICDIPTR22_IV2_VBUFERR0_SHIFT       (8u)
+#define INTC_ICDIPTR22_IV4_VBUFERR0_SHIFT       (16u)
+#define INTC_ICDIPTR22_S1_WLINE0_SHIFT          (24u)
+
+#define INTC_ICDIPTR23_OIR_VI_VSYNC0_SHIFT      (0u)
+#define INTC_ICDIPTR23_OIR_LO_VSYNC0_SHIFT      (8u)
+#define INTC_ICDIPTR23_OIR_VSYNCERR0_SHIFT      (16u)
+#define INTC_ICDIPTR23_OIR_VFIELD0_SHIFT        (24u)
+
+#define INTC_ICDIPTR24_IV7_VBUFERR0_SHIFT       (0u)
+#define INTC_ICDIPTR24_IV8_VBUFERR0_SHIFT       (8u)
+#define INTC_ICDIPTR24_S0_VI_VSYNC1_SHIFT       (24u)
+
+#define INTC_ICDIPTR25_S0_LO_VSYNC1_SHIFT       (0u)
+#define INTC_ICDIPTR25_S0_VSYNCERR1_SHIFT       (8u)
+#define INTC_ICDIPTR25_GR3_VLINE1_SHIFT         (16u)
+#define INTC_ICDIPTR25_S0_VFIELD1_SHIFT         (24u)
+
+#define INTC_ICDIPTR26_IV1_VBUFERR1_SHIFT       (0u)
+#define INTC_ICDIPTR26_IV3_VBUFERR1_SHIFT       (8u)
+#define INTC_ICDIPTR26_IV5_VBUFERR1_SHIFT       (16u)
+#define INTC_ICDIPTR26_IV6_VBUFERR1_SHIFT       (24u)
+
+#define INTC_ICDIPTR27_S0_WLINE1_SHIFT          (0u)
+#define INTC_ICDIPTR27_S1_VI_VSYNC1_SHIFT       (8u)
+#define INTC_ICDIPTR27_S1_LO_VSYNC1_SHIFT       (16u)
+#define INTC_ICDIPTR27_S1_VSYNCERR1_SHIFT       (24u)
+
+#define INTC_ICDIPTR28_S1_VFIELD1_SHIFT         (0u)
+#define INTC_ICDIPTR28_IV2_VBUFERR1_SHIFT       (8u)
+#define INTC_ICDIPTR28_IV4_VBUFERR1_SHIFT       (16u)
+#define INTC_ICDIPTR28_S1_WLINE1_SHIFT          (24u)
+
+#define INTC_ICDIPTR29_OIR_VI_VSYNC1_SHIFT      (0u)
+#define INTC_ICDIPTR29_OIR_LO_VSYNC1_SHIFT      (8u)
+#define INTC_ICDIPTR29_OIR_VLINE1_SHIFT         (16u)
+#define INTC_ICDIPTR29_OIR_VFIELD1_SHIFT        (24u)
+
+#define INTC_ICDIPTR30_IV7_VBUFERR1_SHIFT       (0u)
+#define INTC_ICDIPTR30_IV8_VBUFERR1_SHIFT       (8u)
+#define INTC_ICDIPTR30_IMRDI_SHIFT              (24u)
+
+#define INTC_ICDIPTR31_IMR2I0_SHIFT             (0u)
+#define INTC_ICDIPTR31_IMR2I1_SHIFT             (8u)
+#define INTC_ICDIPTR31_JEDI_SHIFT               (16u)
+#define INTC_ICDIPTR31_JDTI_SHIFT               (24u)
+
+#define INTC_ICDIPTR32_CMP0_SHIFT               (0u)
+#define INTC_ICDIPTR32_CMP1_SHIFT               (8u)
+#define INTC_ICDIPTR32_INT0_SHIFT               (16u)
+#define INTC_ICDIPTR32_INT1_SHIFT               (24u)
+
+#define INTC_ICDIPTR33_INT2_SHIFT               (0u)
+#define INTC_ICDIPTR33_INT3_SHIFT               (8u)
+#define INTC_ICDIPTR33_OSTM0TINT_SHIFT          (16u)
+#define INTC_ICDIPTR33_OSTM1TINT_SHIFT          (24u)
+
+#define INTC_ICDIPTR34_CMI_SHIFT                (0u)
+#define INTC_ICDIPTR34_WTOUT_SHIFT              (8u)
+#define INTC_ICDIPTR34_ITI_SHIFT                (16u)
+#define INTC_ICDIPTR34_TGI0A_SHIFT              (24u)
+
+#define INTC_ICDIPTR35_TGI0B_SHIFT              (0u)
+#define INTC_ICDIPTR35_TGI0C_SHIFT              (8u)
+#define INTC_ICDIPTR35_TGI0D_SHIFT              (16u)
+#define INTC_ICDIPTR35_TGI0V_SHIFT              (24u)
+
+#define INTC_ICDIPTR36_TGI0E_SHIFT              (0u)
+#define INTC_ICDIPTR36_TGI0F_SHIFT              (8u)
+#define INTC_ICDIPTR36_TGI1A_SHIFT              (16u)
+#define INTC_ICDIPTR36_TGI1B_SHIFT              (24u)
+
+#define INTC_ICDIPTR37_TGI1V_SHIFT              (0u)
+#define INTC_ICDIPTR37_TGI1U_SHIFT              (8u)
+#define INTC_ICDIPTR37_TGI2A_SHIFT              (16u)
+#define INTC_ICDIPTR37_TGI2B_SHIFT              (24u)
+
+#define INTC_ICDIPTR38_TGI2V_SHIFT              (0u)
+#define INTC_ICDIPTR38_TGI2U_SHIFT              (8u)
+#define INTC_ICDIPTR38_TGI3A_SHIFT              (16u)
+#define INTC_ICDIPTR38_TGI3B_SHIFT              (24u)
+
+#define INTC_ICDIPTR39_TGI3C_SHIFT              (0u)
+#define INTC_ICDIPTR39_TGI3D_SHIFT              (8u)
+#define INTC_ICDIPTR39_TGI3V_SHIFT              (16u)
+#define INTC_ICDIPTR39_TGI4A_SHIFT              (24u)
+
+#define INTC_ICDIPTR40_TGI4B_SHIFT              (0u)
+#define INTC_ICDIPTR40_TGI4C_SHIFT              (8u)
+#define INTC_ICDIPTR40_TGI4D_SHIFT              (16u)
+#define INTC_ICDIPTR40_TGI4V_SHIFT              (24u)
+
+#define INTC_ICDIPTR41_CMI1_SHIFT               (0u)
+#define INTC_ICDIPTR41_CMI2_SHIFT               (8u)
+#define INTC_ICDIPTR41_SGDEI0_SHIFT             (16u)
+#define INTC_ICDIPTR41_SGDEI1_SHIFT             (24u)
+
+#define INTC_ICDIPTR42_SGDEI2_SHIFT             (0u)
+#define INTC_ICDIPTR42_SGDEI3_SHIFT             (8u)
+#define INTC_ICDIPTR42_ADI_SHIFT                (16u)
+#define INTC_ICDIPTR42_LMTI_SHIFT               (24u)
+
+#define INTC_ICDIPTR43_SSII0_SHIFT              (0u)
+#define INTC_ICDIPTR43_SSIRXI0_SHIFT            (8u)
+#define INTC_ICDIPTR43_SSITXI0_SHIFT            (16u)
+#define INTC_ICDIPTR43_SSII1_SHIFT              (24u)
+
+#define INTC_ICDIPTR44_SSIRXI1_SHIFT            (0u)
+#define INTC_ICDIPTR44_SSITXI1_SHIFT            (8u)
+#define INTC_ICDIPTR44_SSII2_SHIFT              (16u)
+#define INTC_ICDIPTR44_SSIRTI2_SHIFT            (24u)
+
+#define INTC_ICDIPTR45_SSII3_SHIFT              (0u)
+#define INTC_ICDIPTR45_SSIRXI3_SHIFT            (8u)
+#define INTC_ICDIPTR45_SSITXI3_SHIFT            (16u)
+#define INTC_ICDIPTR45_SSII4_SHIFT              (24u)
+
+#define INTC_ICDIPTR46_SSIRTI4_SHIFT            (0u)
+#define INTC_ICDIPTR46_SSII5_SHIFT              (8u)
+#define INTC_ICDIPTR46_SSIRXI5_SHIFT            (16u)
+#define INTC_ICDIPTR46_SSITXI5_SHIFT            (24u)
+
+#define INTC_ICDIPTR47_SPDIFI_SHIFT             (0u)
+#define INTC_ICDIPTR47_INTIICTEI0_SHIFT         (8u)
+#define INTC_ICDIPTR47_INTIICRI0_SHIFT          (16u)
+#define INTC_ICDIPTR47_INTIICTI0_SHIFT          (24u)
+
+#define INTC_ICDIPTR48_INTIICSPI0_SHIFT         (0u)
+#define INTC_ICDIPTR48_INTIICSTI0_SHIFT         (8u)
+#define INTC_ICDIPTR48_INTIICNAKI0_SHIFT        (16u)
+#define INTC_ICDIPTR48_INTIICALI0_SHIFT         (24u)
+
+#define INTC_ICDIPTR49_INTIICTMOI0_SHIFT        (0u)
+#define INTC_ICDIPTR49_INTIICTEI1_SHIFT         (8u)
+#define INTC_ICDIPTR49_INTIICRI1_SHIFT          (16u)
+#define INTC_ICDIPTR49_INTIICTI1_SHIFT          (24u)
+
+#define INTC_ICDIPTR50_INTIICSPI1_SHIFT         (0u)
+#define INTC_ICDIPTR50_INTIICSTI1_SHIFT         (8u)
+#define INTC_ICDIPTR50_INTIICNAKI1_SHIFT        (16u)
+#define INTC_ICDIPTR50_INTIICALI1_SHIFT         (24u)
+
+#define INTC_ICDIPTR51_INTIICTMOI1_SHIFT        (0u)
+#define INTC_ICDIPTR51_INTIICTEI2_SHIFT         (8u)
+#define INTC_ICDIPTR51_INTIICRI2_SHIFT          (16u)
+#define INTC_ICDIPTR51_INTIICTI2_SHIFT          (24u)
+
+#define INTC_ICDIPTR52_INTIICSPI2_SHIFT         (0u)
+#define INTC_ICDIPTR52_INTIICSTI2_SHIFT         (8u)
+#define INTC_ICDIPTR52_INTIICNAKI2_SHIFT        (16u)
+#define INTC_ICDIPTR52_INTIICALI2_SHIFT         (24u)
+
+#define INTC_ICDIPTR53_INTIICTMOI2_SHIFT        (0u)
+#define INTC_ICDIPTR53_INTIICTEI3_SHIFT         (8u)
+#define INTC_ICDIPTR53_INTIICRI3_SHIFT          (16u)
+#define INTC_ICDIPTR53_INTIICTI3_SHIFT          (24u)
+
+#define INTC_ICDIPTR54_INTIICSPI3_SHIFT         (0u)
+#define INTC_ICDIPTR54_INTIICSTI3_SHIFT         (8u)
+#define INTC_ICDIPTR54_INTIICNAKI3_SHIFT        (16u)
+#define INTC_ICDIPTR54_INTIICALI3_SHIFT         (24u)
+
+#define INTC_ICDIPTR55_INTIICTMOI3_SHIFT        (0u)
+#define INTC_ICDIPTR55_BRI0_SHIFT               (8u)
+#define INTC_ICDIPTR55_ERI0_SHIFT               (16u)
+#define INTC_ICDIPTR55_RXI0_SHIFT               (24u)
+
+#define INTC_ICDIPTR56_TXI0_SHIFT               (0u)
+#define INTC_ICDIPTR56_BRI1_SHIFT               (8u)
+#define INTC_ICDIPTR56_ERI1_SHIFT               (16u)
+#define INTC_ICDIPTR56_RXI1_SHIFT               (24u)
+
+#define INTC_ICDIPTR57_TXI1_SHIFT               (0u)
+#define INTC_ICDIPTR57_BRI2_SHIFT               (8u)
+#define INTC_ICDIPTR57_ERI2_SHIFT               (16u)
+#define INTC_ICDIPTR57_RXI2_SHIFT               (24u)
+
+#define INTC_ICDIPTR58_TXI2_SHIFT               (0u)
+#define INTC_ICDIPTR58_BRI3_SHIFT               (8u)
+#define INTC_ICDIPTR58_ERI3_SHIFT               (16u)
+#define INTC_ICDIPTR58_RXI3_SHIFT               (24u)
+
+#define INTC_ICDIPTR59_TXI3_SHIFT               (0u)
+#define INTC_ICDIPTR59_BRI4_SHIFT               (8u)
+#define INTC_ICDIPTR59_ERI4_SHIFT               (16u)
+#define INTC_ICDIPTR59_RXI4_SHIFT               (24u)
+
+#define INTC_ICDIPTR60_TXI4_SHIFT               (0u)
+#define INTC_ICDIPTR60_BRI5_SHIFT               (8u)
+#define INTC_ICDIPTR60_ERI5_SHIFT               (16u)
+#define INTC_ICDIPTR60_RXI5_SHIFT               (24u)
+
+#define INTC_ICDIPTR61_TXI5_SHIFT               (0u)
+#define INTC_ICDIPTR61_BRI6_SHIFT               (8u)
+#define INTC_ICDIPTR61_ERI6_SHIFT               (16u)
+#define INTC_ICDIPTR61_RXI6_SHIFT               (24u)
+
+#define INTC_ICDIPTR62_TXI6_SHIFT               (0u)
+#define INTC_ICDIPTR62_BRI7_SHIFT               (8u)
+#define INTC_ICDIPTR62_ERI7_SHIFT               (16u)
+#define INTC_ICDIPTR62_RXI7_SHIFT               (24u)
+
+#define INTC_ICDIPTR63_TXI7_SHIFT               (0u)
+#define INTC_ICDIPTR63_INTRCANGERR_SHIFT        (8u)
+#define INTC_ICDIPTR63_INTRCANGRECC_SHIFT       (16u)
+#define INTC_ICDIPTR63_INTRCAN0REC_SHIFT        (24u)
+
+#define INTC_ICDIPTR64_INTRCAN0ERR_SHIFT        (0u)
+#define INTC_ICDIPTR64_INTRCAN0TRX_SHIFT        (8u)
+#define INTC_ICDIPTR64_INTRCAN1REC_SHIFT        (16u)
+#define INTC_ICDIPTR64_INTRCAN1ERR_SHIFT        (24u)
+
+#define INTC_ICDIPTR65_INTRCAN1TRX_SHIFT        (0u)
+#define INTC_ICDIPTR65_INTRCAN2REC_SHIFT        (8u)
+#define INTC_ICDIPTR65_INTRCAN2ERR_SHIFT        (16u)
+#define INTC_ICDIPTR65_INTRCAN2TRX_SHIFT        (24u)
+
+#define INTC_ICDIPTR66_INTRCAN3REC_SHIFT        (0u)
+#define INTC_ICDIPTR66_INTRCAN3ERR_SHIFT        (8u)
+#define INTC_ICDIPTR66_INTRCAN3TRX_SHIFT        (16u)
+#define INTC_ICDIPTR66_INTRCAN4REC_SHIFT        (24u)
+
+#define INTC_ICDIPTR67_INTRCAN4ERR_SHIFT        (0u)
+#define INTC_ICDIPTR67_INTRCAN4TRX_SHIFT        (8u)
+#define INTC_ICDIPTR67_SPEI0_SHIFT              (16u)
+#define INTC_ICDIPTR67_SPRI0_SHIFT              (24u)
+
+#define INTC_ICDIPTR68_SPTI0_SHIFT              (0u)
+#define INTC_ICDIPTR68_SPEI1_SHIFT              (8u)
+#define INTC_ICDIPTR68_SPRI1_SHIFT              (16u)
+#define INTC_ICDIPTR68_SPTI1_SHIFT              (24u)
+
+#define INTC_ICDIPTR69_SPEI2_SHIFT              (0u)
+#define INTC_ICDIPTR69_SPRI2_SHIFT              (8u)
+#define INTC_ICDIPTR69_SPTI2_SHIFT              (16u)
+#define INTC_ICDIPTR69_SPEI3_SHIFT              (24u)
+
+#define INTC_ICDIPTR70_SPRI3_SHIFT              (0u)
+#define INTC_ICDIPTR70_SPTI3_SHIFT              (8u)
+#define INTC_ICDIPTR70_SPEI4_SHIFT              (16u)
+#define INTC_ICDIPTR70_SPRI4_SHIFT              (24u)
+
+#define INTC_ICDIPTR71_SPTI4_SHIFT              (0u)
+#define INTC_ICDIPTR71_IEBBTD_SHIFT             (8u)
+#define INTC_ICDIPTR71_IEBBTERR_SHIFT           (16u)
+#define INTC_ICDIPTR71_IEBBTSTA_SHIFT           (24u)
+
+#define INTC_ICDIPTR72_IEBBTV_SHIFT             (0u)
+#define INTC_ICDIPTR72_ISY_SHIFT                (8u)
+#define INTC_ICDIPTR72_IERR_SHIFT               (16u)
+#define INTC_ICDIPTR72_ITARG_SHIFT              (24u)
+
+#define INTC_ICDIPTR73_ISEC_SHIFT               (0u)
+#define INTC_ICDIPTR73_IBUF_SHIFT               (8u)
+#define INTC_ICDIPTR73_IREADY_SHIFT             (16u)
+#define INTC_ICDIPTR73_FLSTE_SHIFT              (24u)
+
+#define INTC_ICDIPTR74_FLTENDI_SHIFT            (0u)
+#define INTC_ICDIPTR74_FLTREQ0I_SHIFT           (8u)
+#define INTC_ICDIPTR74_FLTREQ1I_SHIFT           (16u)
+#define INTC_ICDIPTR74_MMC0_SHIFT               (24u)
+
+#define INTC_ICDIPTR75_MMC1_SHIFT               (0u)
+#define INTC_ICDIPTR75_MMC2_SHIFT               (8u)
+#define INTC_ICDIPTR75_SDHI0_3_SHIFT            (16u)
+#define INTC_ICDIPTR75_SDHI0_0_SHIFT            (24u)
+
+#define INTC_ICDIPTR76_SDHI0_1_SHIFT            (0u)
+#define INTC_ICDIPTR76_SDHI1_3_SHIFT            (8u)
+#define INTC_ICDIPTR76_SDHI1_0_SHIFT            (16u)
+#define INTC_ICDIPTR76_SDHI1_1_SHIFT            (24u)
+
+#define INTC_ICDIPTR77_ARM_SHIFT                (0u)
+#define INTC_ICDIPTR77_PRD_SHIFT                (8u)
+#define INTC_ICDIPTR77_CUP_SHIFT                (16u)
+#define INTC_ICDIPTR77_SCUAI0_SHIFT             (24u)
+
+#define INTC_ICDIPTR78_SCUAI1_SHIFT             (0u)
+#define INTC_ICDIPTR78_SCUFDI0_SHIFT            (8u)
+#define INTC_ICDIPTR78_SCUFDI1_SHIFT            (16u)
+#define INTC_ICDIPTR78_SCUFDI2_SHIFT            (24u)
+
+#define INTC_ICDIPTR79_SCUFDI3_SHIFT            (0u)
+#define INTC_ICDIPTR79_SCUFUI0_SHIFT            (8u)
+#define INTC_ICDIPTR79_SCUFUI1_SHIFT            (16u)
+#define INTC_ICDIPTR79_SCUFUI2_SHIFT            (24u)
+
+#define INTC_ICDIPTR80_SCUFUI3_SHIFT            (0u)
+#define INTC_ICDIPTR80_SCUDVI0_SHIFT            (8u)
+#define INTC_ICDIPTR80_SCUDVI1_SHIFT            (16u)
+#define INTC_ICDIPTR80_SCUDVI2_SHIFT            (24u)
+
+#define INTC_ICDIPTR81_SCUDVI3_SHIFT            (0u)
+#define INTC_ICDIPTR81_MLB_CINT_SHIFT           (8u)
+#define INTC_ICDIPTR81_MLB_SINT_SHIFT           (16u)
+#define INTC_ICDIPTR81_DRC0_SHIFT               (24u)
+
+#define INTC_ICDIPTR82_DRC1_SHIFT               (0u)
+#define INTC_ICDIPTR82_LINI0_INT_T_SHIFT        (24u)
+
+#define INTC_ICDIPTR83_LINI0_INT_R_SHIFT        (0u)
+#define INTC_ICDIPTR83_LINI0_INT_S_SHIFT        (8u)
+#define INTC_ICDIPTR83_LINI0_INT_M_SHIFT        (16u)
+#define INTC_ICDIPTR83_LINI1_INT_T_SHIFT        (24u)
+
+#define INTC_ICDIPTR84_LINI1_INT_R_SHIFT        (0u)
+#define INTC_ICDIPTR84_LINI1_INT_S_SHIFT        (8u)
+#define INTC_ICDIPTR84_LINI1_INT_M_SHIFT        (16u)
+
+#define INTC_ICDIPTR86_ERI0_SHIFT               (24u)
+
+#define INTC_ICDIPTR87_RXI0_SHIFT               (0u)
+#define INTC_ICDIPTR87_TXI0_SHIFT               (8u)
+#define INTC_ICDIPTR87_TEI0_SHIFT               (16u)
+#define INTC_ICDIPTR87_ERI1_SHIFT               (24u)
+
+#define INTC_ICDIPTR88_RXI1_SHIFT               (0u)
+#define INTC_ICDIPTR88_TXI1_SHIFT               (8u)
+#define INTC_ICDIPTR88_TEI1_SHIFT               (16u)
+#define INTC_ICDIPTR88_AVBI_DATA_SHIFT          (24u)
+
+#define INTC_ICDIPTR89_AVBI_ERROR_SHIFT         (0u)
+#define INTC_ICDIPTR89_AVBI_MANAGE_SHIFT        (8u)
+#define INTC_ICDIPTR89_AVBI_MAC_SHIFT           (16u)
+#define INTC_ICDIPTR89_ETHERI_SHIFT             (24u)
+
+#define INTC_ICDIPTR91_CEUI_SHIFT               (0u)
+
+#define INTC_ICDIPTR95_H2XMLB_ERRINT_SHIFT      (8u)
+#define INTC_ICDIPTR95_H2XIC1_ERRINT_SHIFT      (16u)
+#define INTC_ICDIPTR95_X2HPERI1_ERRINT_SHIFT    (24u)
+
+#define INTC_ICDIPTR96_X2HPERI2_ERRINT_SHIFT    (0u)
+#define INTC_ICDIPTR96_X2HPERI34_ERRINT_SHIFT   (8u)
+#define INTC_ICDIPTR96_X2HPERI5_ERRINT_SHIFT    (16u)
+#define INTC_ICDIPTR96_X2HPERI67_ERRINT_SHIFT   (24u)
+
+#define INTC_ICDIPTR97_X2HDBGR_ERRINT_SHIFT     (0u)
+#define INTC_ICDIPTR97_X2HBSC_ERRINT_SHIFT      (8u)
+#define INTC_ICDIPTR97_X2HSPI1_ERRINT_SHIFT     (16u)
+#define INTC_ICDIPTR97_X2HSPI2_ERRINT_SHIFT     (24u)
+
+#define INTC_ICDIPTR98_PRRI_SHIFT               (0u)
+#define INTC_ICDIPTR98_IFEI0_SHIFT              (8u)
+#define INTC_ICDIPTR98_OFFI0_SHIFT              (16u)
+#define INTC_ICDIPTR98_PFVEI0_SHIFT             (24u)
+
+#define INTC_ICDIPTR99_IFEI1_SHIFT              (0u)
+#define INTC_ICDIPTR99_OFFI1_SHIFT              (8u)
+#define INTC_ICDIPTR99_PFVEI1_SHIFT             (16u)
+
+#define INTC_ICDIPTR104_TINT0_SHIFT             (0u)
+#define INTC_ICDIPTR104_TINT1_SHIFT             (8u)
+#define INTC_ICDIPTR104_TINT2_SHIFT             (16u)
+#define INTC_ICDIPTR104_TINT3_SHIFT             (24u)
+
+#define INTC_ICDIPTR105_TINT4_SHIFT             (0u)
+#define INTC_ICDIPTR105_TINT5_SHIFT             (8u)
+#define INTC_ICDIPTR105_TINT6_SHIFT             (16u)
+#define INTC_ICDIPTR105_TINT7_SHIFT             (24u)
+
+#define INTC_ICDIPTR106_TINT8_SHIFT             (0u)
+#define INTC_ICDIPTR106_TINT9_SHIFT             (8u)
+#define INTC_ICDIPTR106_TINT10_SHIFT            (16u)
+#define INTC_ICDIPTR106_TINT11_SHIFT            (24u)
+
+#define INTC_ICDIPTR107_TINT12_SHIFT            (0u)
+#define INTC_ICDIPTR107_TINT13_SHIFT            (8u)
+#define INTC_ICDIPTR107_TINT14_SHIFT            (16u)
+#define INTC_ICDIPTR107_TINT15_SHIFT            (24u)
+
+#define INTC_ICDIPTR108_TINT16_SHIFT            (0u)
+#define INTC_ICDIPTR108_TINT17_SHIFT            (8u)
+#define INTC_ICDIPTR108_TINT18_SHIFT            (16u)
+#define INTC_ICDIPTR108_TINT19_SHIFT            (24u)
+
+#define INTC_ICDIPTR109_TINT20_SHIFT            (0u)
+#define INTC_ICDIPTR109_TINT21_SHIFT            (8u)
+#define INTC_ICDIPTR109_TINT22_SHIFT            (16u)
+#define INTC_ICDIPTR109_TINT23_SHIFT            (24u)
+
+#define INTC_ICDIPTR110_TINT24_SHIFT            (0u)
+#define INTC_ICDIPTR110_TINT25_SHIFT            (8u)
+#define INTC_ICDIPTR110_TINT26_SHIFT            (16u)
+#define INTC_ICDIPTR110_TINT27_SHIFT            (24u)
+
+#define INTC_ICDIPTR111_TINT28_SHIFT            (0u)
+#define INTC_ICDIPTR111_TINT29_SHIFT            (8u)
+#define INTC_ICDIPTR111_TINT30_SHIFT            (16u)
+#define INTC_ICDIPTR111_TINT31_SHIFT            (24u)
+
+#define INTC_ICDIPTR112_TINT32_SHIFT            (0u)
+#define INTC_ICDIPTR112_TINT33_SHIFT            (8u)
+#define INTC_ICDIPTR112_TINT34_SHIFT            (16u)
+#define INTC_ICDIPTR112_TINT35_SHIFT            (24u)
+
+#define INTC_ICDIPTR113_TINT36_SHIFT            (0u)
+#define INTC_ICDIPTR113_TINT37_SHIFT            (8u)
+#define INTC_ICDIPTR113_TINT38_SHIFT            (16u)
+#define INTC_ICDIPTR113_TINT39_SHIFT            (24u)
+
+#define INTC_ICDIPTR114_TINT40_SHIFT            (0u)
+#define INTC_ICDIPTR114_TINT41_SHIFT            (8u)
+#define INTC_ICDIPTR114_TINT42_SHIFT            (16u)
+#define INTC_ICDIPTR114_TINT43_SHIFT            (24u)
+
+#define INTC_ICDIPTR115_TINT44_SHIFT            (0u)
+#define INTC_ICDIPTR115_TINT45_SHIFT            (8u)
+#define INTC_ICDIPTR115_TINT46_SHIFT            (16u)
+#define INTC_ICDIPTR115_TINT47_SHIFT            (24u)
+
+#define INTC_ICDIPTR116_TINT48_SHIFT            (0u)
+#define INTC_ICDIPTR116_TINT49_SHIFT            (8u)
+#define INTC_ICDIPTR116_TINT50_SHIFT            (16u)
+#define INTC_ICDIPTR116_TINT51_SHIFT            (24u)
+
+#define INTC_ICDIPTR117_TINT52_SHIFT            (0u)
+#define INTC_ICDIPTR117_TINT53_SHIFT            (8u)
+#define INTC_ICDIPTR117_TINT54_SHIFT            (16u)
+#define INTC_ICDIPTR117_TINT55_SHIFT            (24u)
+
+#define INTC_ICDIPTR118_TINT56_SHIFT            (0u)
+#define INTC_ICDIPTR118_TINT57_SHIFT            (8u)
+#define INTC_ICDIPTR118_TINT58_SHIFT            (16u)
+#define INTC_ICDIPTR118_TINT59_SHIFT            (24u)
+
+#define INTC_ICDIPTR119_TINT60_SHIFT            (0u)
+#define INTC_ICDIPTR119_TINT61_SHIFT            (8u)
+#define INTC_ICDIPTR119_TINT62_SHIFT            (16u)
+#define INTC_ICDIPTR119_TINT63_SHIFT            (24u)
+
+#define INTC_ICDIPTR120_TINT64_SHIFT            (0u)
+#define INTC_ICDIPTR120_TINT65_SHIFT            (8u)
+#define INTC_ICDIPTR120_TINT66_SHIFT            (16u)
+#define INTC_ICDIPTR120_TINT67_SHIFT            (24u)
+
+#define INTC_ICDIPTR121_TINT68_SHIFT            (0u)
+#define INTC_ICDIPTR121_TINT69_SHIFT            (8u)
+#define INTC_ICDIPTR121_TINT70_SHIFT            (16u)
+#define INTC_ICDIPTR121_TINT71_SHIFT            (24u)
+
+#define INTC_ICDIPTR122_TINT72_SHIFT            (0u)
+#define INTC_ICDIPTR122_TINT73_SHIFT            (8u)
+#define INTC_ICDIPTR122_TINT74_SHIFT            (16u)
+#define INTC_ICDIPTR122_TINT75_SHIFT            (24u)
+
+#define INTC_ICDIPTR123_TINT76_SHIFT            (0u)
+#define INTC_ICDIPTR123_TINT77_SHIFT            (8u)
+#define INTC_ICDIPTR123_TINT78_SHIFT            (16u)
+#define INTC_ICDIPTR123_TINT79_SHIFT            (24u)
+
+#define INTC_ICDIPTR124_TINT80_SHIFT            (0u)
+#define INTC_ICDIPTR124_TINT81_SHIFT            (8u)
+#define INTC_ICDIPTR124_TINT82_SHIFT            (16u)
+#define INTC_ICDIPTR124_TINT83_SHIFT            (24u)
+
+#define INTC_ICDIPTR125_TINT84_SHIFT            (0u)
+#define INTC_ICDIPTR125_TINT85_SHIFT            (8u)
+#define INTC_ICDIPTR125_TINT86_SHIFT            (16u)
+#define INTC_ICDIPTR125_TINT87_SHIFT            (24u)
+
+#define INTC_ICDIPTR126_TINT88_SHIFT            (0u)
+#define INTC_ICDIPTR126_TINT89_SHIFT            (8u)
+#define INTC_ICDIPTR126_TINT90_SHIFT            (16u)
+#define INTC_ICDIPTR126_TINT91_SHIFT            (24u)
+
+#define INTC_ICDIPTR127_TINT92_SHIFT            (0u)
+#define INTC_ICDIPTR127_TINT93_SHIFT            (8u)
+#define INTC_ICDIPTR127_TINT94_SHIFT            (16u)
+#define INTC_ICDIPTR127_TINT95_SHIFT            (24u)
+
+#define INTC_ICDIPTR128_TINT96_SHIFT            (0u)
+#define INTC_ICDIPTR128_TINT97_SHIFT            (8u)
+#define INTC_ICDIPTR128_TINT98_SHIFT            (16u)
+#define INTC_ICDIPTR128_TINT99_SHIFT            (24u)
+
+#define INTC_ICDIPTR129_TINT100_SHIFT           (0u)
+#define INTC_ICDIPTR129_TINT101_SHIFT           (8u)
+#define INTC_ICDIPTR129_TINT102_SHIFT           (16u)
+#define INTC_ICDIPTR129_TINT103_SHIFT           (24u)
+
+#define INTC_ICDIPTR130_TINT104_SHIFT           (0u)
+#define INTC_ICDIPTR130_TINT105_SHIFT           (8u)
+#define INTC_ICDIPTR130_TINT106_SHIFT           (16u)
+#define INTC_ICDIPTR130_TINT107_SHIFT           (24u)
+
+#define INTC_ICDIPTR131_TINT108_SHIFT           (0u)
+#define INTC_ICDIPTR131_TINT109_SHIFT           (8u)
+#define INTC_ICDIPTR131_TINT110_SHIFT           (16u)
+#define INTC_ICDIPTR131_TINT111_SHIFT           (24u)
+
+#define INTC_ICDIPTR132_TINT112_SHIFT           (0u)
+#define INTC_ICDIPTR132_TINT113_SHIFT           (8u)
+#define INTC_ICDIPTR132_TINT114_SHIFT           (16u)
+#define INTC_ICDIPTR132_TINT115_SHIFT           (24u)
+
+#define INTC_ICDIPTR133_TINT116_SHIFT           (0u)
+#define INTC_ICDIPTR133_TINT117_SHIFT           (8u)
+#define INTC_ICDIPTR133_TINT118_SHIFT           (16u)
+#define INTC_ICDIPTR133_TINT119_SHIFT           (24u)
+
+#define INTC_ICDIPTR134_TINT120_SHIFT           (0u)
+#define INTC_ICDIPTR134_TINT121_SHIFT           (8u)
+#define INTC_ICDIPTR134_TINT122_SHIFT           (16u)
+#define INTC_ICDIPTR134_TINT123_SHIFT           (24u)
+
+#define INTC_ICDIPTR135_TINT124_SHIFT           (0u)
+#define INTC_ICDIPTR135_TINT125_SHIFT           (8u)
+#define INTC_ICDIPTR135_TINT126_SHIFT           (16u)
+#define INTC_ICDIPTR135_TINT127_SHIFT           (24u)
+
+#define INTC_ICDIPTR136_TINT128_SHIFT           (0u)
+#define INTC_ICDIPTR136_TINT129_SHIFT           (8u)
+#define INTC_ICDIPTR136_TINT130_SHIFT           (16u)
+#define INTC_ICDIPTR136_TINT131_SHIFT           (24u)
+
+#define INTC_ICDIPTR137_TINT132_SHIFT           (0u)
+#define INTC_ICDIPTR137_TINT133_SHIFT           (8u)
+#define INTC_ICDIPTR137_TINT134_SHIFT           (16u)
+#define INTC_ICDIPTR137_TINT135_SHIFT           (24u)
+
+#define INTC_ICDIPTR138_TINT136_SHIFT           (0u)
+#define INTC_ICDIPTR138_TINT137_SHIFT           (8u)
+#define INTC_ICDIPTR138_TINT138_SHIFT           (16u)
+#define INTC_ICDIPTR138_TINT139_SHIFT           (24u)
+
+#define INTC_ICDIPTR139_TINT140_SHIFT           (0u)
+#define INTC_ICDIPTR139_TINT141_SHIFT           (8u)
+#define INTC_ICDIPTR139_TINT142_SHIFT           (16u)
+#define INTC_ICDIPTR139_TINT143_SHIFT           (24u)
+
+#define INTC_ICDIPTR140_TINT144_SHIFT           (0u)
+#define INTC_ICDIPTR140_TINT145_SHIFT           (8u)
+#define INTC_ICDIPTR140_TINT146_SHIFT           (16u)
+#define INTC_ICDIPTR140_TINT147_SHIFT           (24u)
+
+#define INTC_ICDIPTR141_TINT148_SHIFT           (0u)
+#define INTC_ICDIPTR141_TINT149_SHIFT           (8u)
+#define INTC_ICDIPTR141_TINT150_SHIFT           (16u)
+#define INTC_ICDIPTR141_TINT151_SHIFT           (24u)
+
+#define INTC_ICDIPTR142_TINT152_SHIFT           (0u)
+#define INTC_ICDIPTR142_TINT153_SHIFT           (8u)
+#define INTC_ICDIPTR142_TINT154_SHIFT           (16u)
+#define INTC_ICDIPTR142_TINT155_SHIFT           (24u)
+
+#define INTC_ICDIPTR143_TINT156_SHIFT           (0u)
+#define INTC_ICDIPTR143_TINT157_SHIFT           (8u)
+#define INTC_ICDIPTR143_TINT158_SHIFT           (16u)
+#define INTC_ICDIPTR143_TINT159_SHIFT           (24u)
+
+#define INTC_ICDIPTR144_TINT160_SHIFT           (0u)
+#define INTC_ICDIPTR144_TINT161_SHIFT           (8u)
+#define INTC_ICDIPTR144_TINT162_SHIFT           (16u)
+#define INTC_ICDIPTR144_TINT163_SHIFT           (24u)
+
+#define INTC_ICDIPTR145_TINT164_SHIFT           (0u)
+#define INTC_ICDIPTR145_TINT165_SHIFT           (8u)
+#define INTC_ICDIPTR145_TINT166_SHIFT           (16u)
+#define INTC_ICDIPTR145_TINT167_SHIFT           (24u)
+
+#define INTC_ICDIPTR146_TINT168_SHIFT           (0u)
+#define INTC_ICDIPTR146_TINT169_SHIFT           (8u)
+#define INTC_ICDIPTR146_TINT170_SHIFT           (16u)
+
+#define INTC_ICDICFR0_SW0_0_SHIFT               (0u)
+#define INTC_ICDICFR0_SW0_1_SHIFT               (1u)
+#define INTC_ICDICFR0_SW1_0_SHIFT               (2u)
+#define INTC_ICDICFR0_SW1_1_SHIFT               (3u)
+#define INTC_ICDICFR0_SW2_0_SHIFT               (4u)
+#define INTC_ICDICFR0_SW2_1_SHIFT               (5u)
+#define INTC_ICDICFR0_SW3_0_SHIFT               (6u)
+#define INTC_ICDICFR0_SW3_1_SHIFT               (7u)
+#define INTC_ICDICFR0_SW4_0_SHIFT               (8u)
+#define INTC_ICDICFR0_SW4_1_SHIFT               (9u)
+#define INTC_ICDICFR0_SW5_0_SHIFT               (10u)
+#define INTC_ICDICFR0_SW5_1_SHIFT               (11u)
+#define INTC_ICDICFR0_SW6_0_SHIFT               (12u)
+#define INTC_ICDICFR0_SW6_1_SHIFT               (13u)
+#define INTC_ICDICFR0_SW7_0_SHIFT               (14u)
+#define INTC_ICDICFR0_SW7_1_SHIFT               (15u)
+#define INTC_ICDICFR0_SW8_0_SHIFT               (16u)
+#define INTC_ICDICFR0_SW8_1_SHIFT               (17u)
+#define INTC_ICDICFR0_SW9_0_SHIFT               (18u)
+#define INTC_ICDICFR0_SW9_1_SHIFT               (19u)
+#define INTC_ICDICFR0_SW10_0_SHIFT              (20u)
+#define INTC_ICDICFR0_SW10_1_SHIFT              (21u)
+#define INTC_ICDICFR0_SW11_0_SHIFT              (22u)
+#define INTC_ICDICFR0_SW11_1_SHIFT              (23u)
+#define INTC_ICDICFR0_SW12_0_SHIFT              (24u)
+#define INTC_ICDICFR0_SW12_1_SHIFT              (25u)
+#define INTC_ICDICFR0_SW13_0_SHIFT              (26u)
+#define INTC_ICDICFR0_SW13_1_SHIFT              (27u)
+#define INTC_ICDICFR0_SW14_0_SHIFT              (28u)
+#define INTC_ICDICFR0_SW14_1_SHIFT              (29u)
+#define INTC_ICDICFR0_SW15_0_SHIFT              (30u)
+#define INTC_ICDICFR0_SW15_1_SHIFT              (31u)
+
+#define INTC_ICDICFR1_PMUIRQ0_0_SHIFT           (0u)
+#define INTC_ICDICFR1_PMUIRQ0_1_SHIFT           (1u)
+#define INTC_ICDICFR1_COMMRX0_0_SHIFT           (2u)
+#define INTC_ICDICFR1_COMMRX0_1_SHIFT           (3u)
+#define INTC_ICDICFR1_COMMTX0_0_SHIFT           (4u)
+#define INTC_ICDICFR1_COMMTX0_1_SHIFT           (5u)
+#define INTC_ICDICFR1_CTIIRQ0_0_SHIFT           (6u)
+#define INTC_ICDICFR1_CTIIRQ0_1_SHIFT           (7u)
+
+#define INTC_ICDICFR2_IRQ0_0_SHIFT              (0u)
+#define INTC_ICDICFR2_IRQ0_1_SHIFT              (1u)
+#define INTC_ICDICFR2_IRQ1_0_SHIFT              (2u)
+#define INTC_ICDICFR2_IRQ1_1_SHIFT              (3u)
+#define INTC_ICDICFR2_IRQ2_0_SHIFT              (4u)
+#define INTC_ICDICFR2_IRQ2_1_SHIFT              (5u)
+#define INTC_ICDICFR2_IRQ3_0_SHIFT              (6u)
+#define INTC_ICDICFR2_IRQ3_1_SHIFT              (7u)
+#define INTC_ICDICFR2_IRQ4_0_SHIFT              (8u)
+#define INTC_ICDICFR2_IRQ4_1_SHIFT              (9u)
+#define INTC_ICDICFR2_IRQ5_0_SHIFT              (10u)
+#define INTC_ICDICFR2_IRQ5_1_SHIFT              (11u)
+#define INTC_ICDICFR2_IRQ6_0_SHIFT              (12u)
+#define INTC_ICDICFR2_IRQ6_1_SHIFT              (13u)
+#define INTC_ICDICFR2_IRQ7_0_SHIFT              (14u)
+#define INTC_ICDICFR2_IRQ7_1_SHIFT              (15u)
+#define INTC_ICDICFR2_PL310ERR_0_SHIFT          (16u)
+#define INTC_ICDICFR2_PL310ERR_1_SHIFT          (17u)
+#define INTC_ICDICFR2_DMAINT0_0_SHIFT           (18u)
+#define INTC_ICDICFR2_DMAINT0_1_SHIFT           (19u)
+#define INTC_ICDICFR2_DMAINT1_0_SHIFT           (20u)
+#define INTC_ICDICFR2_DMAINT1_1_SHIFT           (21u)
+#define INTC_ICDICFR2_DMAINT2_0_SHIFT           (22u)
+#define INTC_ICDICFR2_DMAINT2_1_SHIFT           (23u)
+#define INTC_ICDICFR2_DMAINT3_0_SHIFT           (24u)
+#define INTC_ICDICFR2_DMAINT3_1_SHIFT           (25u)
+#define INTC_ICDICFR2_DMAINT4_0_SHIFT           (26u)
+#define INTC_ICDICFR2_DMAINT4_1_SHIFT           (27u)
+#define INTC_ICDICFR2_DMAINT5_0_SHIFT           (28u)
+#define INTC_ICDICFR2_DMAINT5_1_SHIFT           (29u)
+#define INTC_ICDICFR2_DMAINT6_0_SHIFT           (30u)
+#define INTC_ICDICFR2_DMAINT6_1_SHIFT           (31u)
+
+#define INTC_ICDICFR3_DMAINT7_0_SHIFT           (0u)
+#define INTC_ICDICFR3_DMAINT7_1_SHIFT           (1u)
+#define INTC_ICDICFR3_DMAINT8_0_SHIFT           (2u)
+#define INTC_ICDICFR3_DMAINT8_1_SHIFT           (3u)
+#define INTC_ICDICFR3_DMAINT9_0_SHIFT           (4u)
+#define INTC_ICDICFR3_DMAINT9_1_SHIFT           (5u)
+#define INTC_ICDICFR3_DMAINT10_0_SHIFT          (6u)
+#define INTC_ICDICFR3_DMAINT10_1_SHIFT          (7u)
+#define INTC_ICDICFR3_DMAINT11_0_SHIFT          (8u)
+#define INTC_ICDICFR3_DMAINT11_1_SHIFT          (9u)
+#define INTC_ICDICFR3_DMAINT12_0_SHIFT          (10u)
+#define INTC_ICDICFR3_DMAINT12_1_SHIFT          (11u)
+#define INTC_ICDICFR3_DMAINT13_0_SHIFT          (12u)
+#define INTC_ICDICFR3_DMAINT13_1_SHIFT          (13u)
+#define INTC_ICDICFR3_DMAINT14_0_SHIFT          (14u)
+#define INTC_ICDICFR3_DMAINT14_1_SHIFT          (15u)
+#define INTC_ICDICFR3_DMAINT15_0_SHIFT          (16u)
+#define INTC_ICDICFR3_DMAINT15_1_SHIFT          (17u)
+#define INTC_ICDICFR3_DMAERR_0_SHIFT            (18u)
+#define INTC_ICDICFR3_DMAERR_1_SHIFT            (19u)
+
+#define INTC_ICDICFR4_USBI0_0_SHIFT             (18u)
+#define INTC_ICDICFR4_USBI0_1_SHIFT             (19u)
+#define INTC_ICDICFR4_USBI1_0_SHIFT             (20u)
+#define INTC_ICDICFR4_USBI1_1_SHIFT             (21u)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_0_SHIFT      (22u)
+#define INTC_ICDICFR4_S0_VI_VSYNC0_1_SHIFT      (23u)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_0_SHIFT      (24u)
+#define INTC_ICDICFR4_S0_LO_VSYNC0_1_SHIFT      (25u)
+#define INTC_ICDICFR4_S0_VSYNCERR0_0_SHIFT      (26u)
+#define INTC_ICDICFR4_S0_VSYNCERR0_1_SHIFT      (27u)
+#define INTC_ICDICFR4_GR3_VLINE0_0_SHIFT        (28u)
+#define INTC_ICDICFR4_GR3_VLINE0_1_SHIFT        (29u)
+#define INTC_ICDICFR4_S0_VFIELD0_0_SHIFT        (30u)
+#define INTC_ICDICFR4_S0_VFIELD0_1_SHIFT        (31u)
+
+#define INTC_ICDICFR5_IV1_VBUFERR0_0_SHIFT      (0u)
+#define INTC_ICDICFR5_IV1_VBUFERR0_1_SHIFT      (1u)
+#define INTC_ICDICFR5_IV3_VBUFERR0_0_SHIFT      (2u)
+#define INTC_ICDICFR5_IV3_VBUFERR0_1_SHIFT      (3u)
+#define INTC_ICDICFR5_IV5_VBUFERR0_0_SHIFT      (4u)
+#define INTC_ICDICFR5_IV5_VBUFERR0_1_SHIFT      (5u)
+#define INTC_ICDICFR5_IV6_VBUFERR0_0_SHIFT      (6u)
+#define INTC_ICDICFR5_IV6_VBUFERR0_1_SHIFT      (7u)
+#define INTC_ICDICFR5_S0_WLINE0_0_SHIFT         (8u)
+#define INTC_ICDICFR5_S0_WLINE0_1_SHIFT         (9u)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_0_SHIFT      (10u)
+#define INTC_ICDICFR5_S1_VI_VSYNC0_1_SHIFT      (11u)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_0_SHIFT      (12u)
+#define INTC_ICDICFR5_S1_LO_VSYNC0_1_SHIFT      (13u)
+#define INTC_ICDICFR5_S1_VSYNCERR0_0_SHIFT      (14u)
+#define INTC_ICDICFR5_S1_VSYNCERR0_1_SHIFT      (15u)
+#define INTC_ICDICFR5_S1_VFIELD0_0_SHIFT        (16u)
+#define INTC_ICDICFR5_S1_VFIELD0_1_SHIFT        (17u)
+#define INTC_ICDICFR5_IV2_VBUFERR0_0_SHIFT      (18u)
+#define INTC_ICDICFR5_IV2_VBUFERR0_1_SHIFT      (19u)
+#define INTC_ICDICFR5_IV4_VBUFERR0_0_SHIFT      (20u)
+#define INTC_ICDICFR5_IV4_VBUFERR0_1_SHIFT      (21u)
+#define INTC_ICDICFR5_S1_WLINE0_0_SHIFT         (22u)
+#define INTC_ICDICFR5_S1_WLINE0_1_SHIFT         (23u)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_0_SHIFT     (24u)
+#define INTC_ICDICFR5_OIR_VI_VSYNC0_1_SHIFT     (25u)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_0_SHIFT     (26u)
+#define INTC_ICDICFR5_OIR_LO_VSYNC0_1_SHIFT     (27u)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_0_SHIFT     (28u)
+#define INTC_ICDICFR5_OIR_VSYNCERR0_1_SHIFT     (29u)
+#define INTC_ICDICFR5_OIR_VFIELD0_0_SHIFT       (30u)
+#define INTC_ICDICFR5_OIR_VFIELD0_1_SHIFT       (31u)
+
+#define INTC_ICDICFR6_IV7_VBUFERR0_0_SHIFT      (0u)
+#define INTC_ICDICFR6_IV7_VBUFERR0_1_SHIFT      (1u)
+#define INTC_ICDICFR6_IV8_VBUFERR0_0_SHIFT      (2u)
+#define INTC_ICDICFR6_IV8_VBUFERR0_1_SHIFT      (3u)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_0_SHIFT      (6u)
+#define INTC_ICDICFR6_S0_VI_VSYNC1_1_SHIFT      (7u)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_0_SHIFT      (8u)
+#define INTC_ICDICFR6_S0_LO_VSYNC1_1_SHIFT      (9u)
+#define INTC_ICDICFR6_S0_VSYNCERR1_0_SHIFT      (10u)
+#define INTC_ICDICFR6_S0_VSYNCERR1_1_SHIFT      (11u)
+#define INTC_ICDICFR6_GR3_VLINE1_0_SHIFT        (12u)
+#define INTC_ICDICFR6_GR3_VLINE1_1_SHIFT        (13u)
+#define INTC_ICDICFR6_S0_VFIELD1_0_SHIFT        (14u)
+#define INTC_ICDICFR6_S0_VFIELD1_1_SHIFT        (15u)
+#define INTC_ICDICFR6_IV1_VBUFERR1_0_SHIFT      (16u)
+#define INTC_ICDICFR6_IV1_VBUFERR1_1_SHIFT      (17u)
+#define INTC_ICDICFR6_IV3_VBUFERR1_0_SHIFT      (18u)
+#define INTC_ICDICFR6_IV3_VBUFERR1_1_SHIFT      (19u)
+#define INTC_ICDICFR6_IV5_VBUFERR1_0_SHIFT      (20u)
+#define INTC_ICDICFR6_IV5_VBUFERR1_1_SHIFT      (21u)
+#define INTC_ICDICFR6_IV6_VBUFERR1_0_SHIFT      (22u)
+#define INTC_ICDICFR6_IV6_VBUFERR1_1_SHIFT      (23u)
+#define INTC_ICDICFR6_S0_WLINE1_0_SHIFT         (24u)
+#define INTC_ICDICFR6_S0_WLINE1_1_SHIFT         (25u)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_0_SHIFT      (26u)
+#define INTC_ICDICFR6_S1_VI_VSYNC1_1_SHIFT      (27u)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_0_SHIFT      (28u)
+#define INTC_ICDICFR6_S1_LO_VSYNC1_1_SHIFT      (29u)
+#define INTC_ICDICFR6_S1_VSYNCERR1_0_SHIFT      (30u)
+#define INTC_ICDICFR6_S1_VSYNCERR1_1_SHIFT      (31u)
+
+#define INTC_ICDICFR7_S1_VFIELD1_0_SHIFT        (0u)
+#define INTC_ICDICFR7_S1_VFIELD1_1_SHIFT        (1u)
+#define INTC_ICDICFR7_IV2_VBUFERR1_0_SHIFT      (2u)
+#define INTC_ICDICFR7_IV2_VBUFERR1_1_SHIFT      (3u)
+#define INTC_ICDICFR7_IV4_VBUFERR1_0_SHIFT      (4u)
+#define INTC_ICDICFR7_IV4_VBUFERR1_1_SHIFT      (5u)
+#define INTC_ICDICFR7_S1_WLINE1_0_SHIFT         (6u)
+#define INTC_ICDICFR7_S1_WLINE1_1_SHIFT         (7u)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_0_SHIFT     (8u)
+#define INTC_ICDICFR7_OIR_VI_VSYNC1_1_SHIFT     (9u)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_0_SHIFT     (10u)
+#define INTC_ICDICFR7_OIR_LO_VSYNC1_1_SHIFT     (11u)
+#define INTC_ICDICFR7_OIR_VLINE1_0_SHIFT        (12u)
+#define INTC_ICDICFR7_OIR_VLINE1_1_SHIFT        (13u)
+#define INTC_ICDICFR7_OIR_VFIELD1_0_SHIFT       (14u)
+#define INTC_ICDICFR7_OIR_VFIELD1_1_SHIFT       (15u)
+#define INTC_ICDICFR7_IV7_VBUFERR1_0_SHIFT      (16u)
+#define INTC_ICDICFR7_IV7_VBUFERR1_1_SHIFT      (17u)
+#define INTC_ICDICFR7_IV8_VBUFERR1_0_SHIFT      (18u)
+#define INTC_ICDICFR7_IV8_VBUFERR1_1_SHIFT      (19u)
+#define INTC_ICDICFR7_IMRDI_0_SHIFT             (22u)
+#define INTC_ICDICFR7_IMRDI_1_SHIFT             (23u)
+#define INTC_ICDICFR7_IMR2I0_0_SHIFT            (24u)
+#define INTC_ICDICFR7_IMR2I0_1_SHIFT            (25u)
+#define INTC_ICDICFR7_IMR2I1_0_SHIFT            (26u)
+#define INTC_ICDICFR7_IMR2I1_1_SHIFT            (27u)
+#define INTC_ICDICFR7_JEDI_0_SHIFT              (28u)
+#define INTC_ICDICFR7_JEDI_1_SHIFT              (29u)
+#define INTC_ICDICFR7_JDTI_0_SHIFT              (30u)
+#define INTC_ICDICFR7_JDTI_1_SHIFT              (31u)
+
+#define INTC_ICDICFR8_CMP0_0_SHIFT              (0u)
+#define INTC_ICDICFR8_CMP0_1_SHIFT              (1u)
+#define INTC_ICDICFR8_CMP1_0_SHIFT              (2u)
+#define INTC_ICDICFR8_CMP1_1_SHIFT              (3u)
+#define INTC_ICDICFR8_INT0_0_SHIFT              (4u)
+#define INTC_ICDICFR8_INT0_1_SHIFT              (5u)
+#define INTC_ICDICFR8_INT1_0_SHIFT              (6u)
+#define INTC_ICDICFR8_INT1_1_SHIFT              (7u)
+#define INTC_ICDICFR8_INT2_0_SHIFT              (8u)
+#define INTC_ICDICFR8_INT2_1_SHIFT              (9u)
+#define INTC_ICDICFR8_INT3_0_SHIFT              (10u)
+#define INTC_ICDICFR8_INT3_1_SHIFT              (11u)
+#define INTC_ICDICFR8_OSTM0TINT_0_SHIFT         (12u)
+#define INTC_ICDICFR8_OSTM0TINT_1_SHIFT         (13u)
+#define INTC_ICDICFR8_OSTM1TINT_0_SHIFT         (14u)
+#define INTC_ICDICFR8_OSTM1TINT_1_SHIFT         (15u)
+#define INTC_ICDICFR8_CMI_0_SHIFT               (16u)
+#define INTC_ICDICFR8_CMI_1_SHIFT               (17u)
+#define INTC_ICDICFR8_WTOUT_0_SHIFT             (18u)
+#define INTC_ICDICFR8_WTOUT_1_SHIFT             (19u)
+#define INTC_ICDICFR8_ITI_0_SHIFT               (20u)
+#define INTC_ICDICFR8_ITI_1_SHIFT               (21u)
+#define INTC_ICDICFR8_TGI0A_0_SHIFT             (22u)
+#define INTC_ICDICFR8_TGI0A_1_SHIFT             (23u)
+#define INTC_ICDICFR8_TGI0B_0_SHIFT             (24u)
+#define INTC_ICDICFR8_TGI0B_1_SHIFT             (25u)
+#define INTC_ICDICFR8_TGI0C_0_SHIFT             (26u)
+#define INTC_ICDICFR8_TGI0C_1_SHIFT             (27u)
+#define INTC_ICDICFR8_TGI0D_0_SHIFT             (28u)
+#define INTC_ICDICFR8_TGI0D_1_SHIFT             (29u)
+#define INTC_ICDICFR8_TGI0V_0_SHIFT             (30u)
+#define INTC_ICDICFR8_TGI0V_1_SHIFT             (31u)
+
+#define INTC_ICDICFR9_TGI0E_0_SHIFT             (0u)
+#define INTC_ICDICFR9_TGI0E_1_SHIFT             (1u)
+#define INTC_ICDICFR9_TGI0F_0_SHIFT             (2u)
+#define INTC_ICDICFR9_TGI0F_1_SHIFT             (3u)
+#define INTC_ICDICFR9_TGI1A_0_SHIFT             (4u)
+#define INTC_ICDICFR9_TGI1A_1_SHIFT             (5u)
+#define INTC_ICDICFR9_TGI1B_0_SHIFT             (6u)
+#define INTC_ICDICFR9_TGI1B_1_SHIFT             (7u)
+#define INTC_ICDICFR9_TGI1V_0_SHIFT             (8u)
+#define INTC_ICDICFR9_TGI1V_1_SHIFT             (9u)
+#define INTC_ICDICFR9_TGI1U_0_SHIFT             (10u)
+#define INTC_ICDICFR9_TGI1U_1_SHIFT             (11u)
+#define INTC_ICDICFR9_TGI2A_0_SHIFT             (12u)
+#define INTC_ICDICFR9_TGI2A_1_SHIFT             (13u)
+#define INTC_ICDICFR9_TGI2B_0_SHIFT             (14u)
+#define INTC_ICDICFR9_TGI2B_1_SHIFT             (15u)
+#define INTC_ICDICFR9_TGI2V_0_SHIFT             (16u)
+#define INTC_ICDICFR9_TGI2V_1_SHIFT             (17u)
+#define INTC_ICDICFR9_TGI2U_0_SHIFT             (18u)
+#define INTC_ICDICFR9_TGI2U_1_SHIFT             (19u)
+#define INTC_ICDICFR9_TGI3A_0_SHIFT             (20u)
+#define INTC_ICDICFR9_TGI3A_1_SHIFT             (21u)
+#define INTC_ICDICFR9_TGI3B_0_SHIFT             (22u)
+#define INTC_ICDICFR9_TGI3B_1_SHIFT             (23u)
+#define INTC_ICDICFR9_TGI3C_0_SHIFT             (24u)
+#define INTC_ICDICFR9_TGI3C_1_SHIFT             (25u)
+#define INTC_ICDICFR9_TGI3D_0_SHIFT             (26u)
+#define INTC_ICDICFR9_TGI3D_1_SHIFT             (27u)
+#define INTC_ICDICFR9_TGI3V_0_SHIFT             (28u)
+#define INTC_ICDICFR9_TGI3V_1_SHIFT             (29u)
+#define INTC_ICDICFR9_TGI4A_0_SHIFT             (30u)
+#define INTC_ICDICFR9_TGI4A_1_SHIFT             (31u)
+
+#define INTC_ICDICFR10_TGI4B_0_SHIFT            (0u)
+#define INTC_ICDICFR10_TGI4B_1_SHIFT            (1u)
+#define INTC_ICDICFR10_TGI4C_0_SHIFT            (2u)
+#define INTC_ICDICFR10_TGI4C_1_SHIFT            (3u)
+#define INTC_ICDICFR10_TGI4D_0_SHIFT            (4u)
+#define INTC_ICDICFR10_TGI4D_1_SHIFT            (5u)
+#define INTC_ICDICFR10_TGI4V_0_SHIFT            (6u)
+#define INTC_ICDICFR10_TGI4V_1_SHIFT            (7u)
+#define INTC_ICDICFR10_CMI1_0_SHIFT             (8u)
+#define INTC_ICDICFR10_CMI1_1_SHIFT             (9u)
+#define INTC_ICDICFR10_CMI2_0_SHIFT             (10u)
+#define INTC_ICDICFR10_CMI2_1_SHIFT             (11u)
+#define INTC_ICDICFR10_SGDEI0_0_SHIFT           (12u)
+#define INTC_ICDICFR10_SGDEI0_1_SHIFT           (13u)
+#define INTC_ICDICFR10_SGDEI1_0_SHIFT           (14u)
+#define INTC_ICDICFR10_SGDEI1_1_SHIFT           (15u)
+#define INTC_ICDICFR10_SGDEI2_0_SHIFT           (16u)
+#define INTC_ICDICFR10_SGDEI2_1_SHIFT           (17u)
+#define INTC_ICDICFR10_SGDEI3_0_SHIFT           (18u)
+#define INTC_ICDICFR10_SGDEI3_1_SHIFT           (19u)
+#define INTC_ICDICFR10_ADI_0_SHIFT              (20u)
+#define INTC_ICDICFR10_ADI_1_SHIFT              (21u)
+#define INTC_ICDICFR10_LMTI_0_SHIFT             (22u)
+#define INTC_ICDICFR10_LMTI_1_SHIFT             (23u)
+#define INTC_ICDICFR10_SSII0_0_SHIFT            (24u)
+#define INTC_ICDICFR10_SSII0_1_SHIFT            (25u)
+#define INTC_ICDICFR10_SSIRXI0_0_SHIFT          (26u)
+#define INTC_ICDICFR10_SSIRXI0_1_SHIFT          (27u)
+#define INTC_ICDICFR10_SSITXI0_0_SHIFT          (28u)
+#define INTC_ICDICFR10_SSITXI0_1_SHIFT          (29u)
+#define INTC_ICDICFR10_SSII1_0_SHIFT            (30u)
+#define INTC_ICDICFR10_SSII1_1_SHIFT            (31u)
+
+#define INTC_ICDICFR11_SSIRXI1_0_SHIFT          (0u)
+#define INTC_ICDICFR11_SSIRXI1_1_SHIFT          (1u)
+#define INTC_ICDICFR11_SSITXI1_0_SHIFT          (2u)
+#define INTC_ICDICFR11_SSITXI1_1_SHIFT          (3u)
+#define INTC_ICDICFR11_SSII2_0_SHIFT            (4u)
+#define INTC_ICDICFR11_SSII2_1_SHIFT            (5u)
+#define INTC_ICDICFR11_SSIRTI2_0_SHIFT          (6u)
+#define INTC_ICDICFR11_SSIRTI2_1_SHIFT          (7u)
+#define INTC_ICDICFR11_SSII3_0_SHIFT            (8u)
+#define INTC_ICDICFR11_SSII3_1_SHIFT            (9u)
+#define INTC_ICDICFR11_SSIRXI3_0_SHIFT          (10u)
+#define INTC_ICDICFR11_SSIRXI3_1_SHIFT          (11u)
+#define INTC_ICDICFR11_SSITXI3_0_SHIFT          (12u)
+#define INTC_ICDICFR11_SSITXI3_1_SHIFT          (13u)
+#define INTC_ICDICFR11_SSII4_0_SHIFT            (14u)
+#define INTC_ICDICFR11_SSII4_1_SHIFT            (15u)
+#define INTC_ICDICFR11_SSIRTI4_0_SHIFT          (16u)
+#define INTC_ICDICFR11_SSIRTI4_1_SHIFT          (17u)
+#define INTC_ICDICFR11_SSII5_0_SHIFT            (18u)
+#define INTC_ICDICFR11_SSII5_1_SHIFT            (19u)
+#define INTC_ICDICFR11_SSIRXI5_0_SHIFT          (20u)
+#define INTC_ICDICFR11_SSIRXI5_1_SHIFT          (21u)
+#define INTC_ICDICFR11_SSITXI5_0_SHIFT          (22u)
+#define INTC_ICDICFR11_SSITXI5_1_SHIFT          (23u)
+#define INTC_ICDICFR11_SPDIFI_0_SHIFT           (24u)
+#define INTC_ICDICFR11_SPDIFI_1_SHIFT           (25u)
+#define INTC_ICDICFR11_INTIICTEI0_0_SHIFT       (26u)
+#define INTC_ICDICFR11_INTIICTEI0_1_SHIFT       (27u)
+#define INTC_ICDICFR11_INTIICRI0_0_SHIFT        (28u)
+#define INTC_ICDICFR11_INTIICRI0_1_SHIFT        (29u)
+#define INTC_ICDICFR11_INTIICTI0_0_SHIFT        (30u)
+#define INTC_ICDICFR11_INTIICTI0_1_SHIFT        (31u)
+
+#define INTC_ICDICFR12_INTIICSPI0_0_SHIFT       (0u)
+#define INTC_ICDICFR12_INTIICSPI0_1_SHIFT       (1u)
+#define INTC_ICDICFR12_INTIICSTI0_0_SHIFT       (2u)
+#define INTC_ICDICFR12_INTIICSTI0_1_SHIFT       (3u)
+#define INTC_ICDICFR12_INTIICNAKI0_0_SHIFT      (4u)
+#define INTC_ICDICFR12_INTIICNAKI0_1_SHIFT      (5u)
+#define INTC_ICDICFR12_INTIICALI0_0_SHIFT       (6u)
+#define INTC_ICDICFR12_INTIICALI0_1_SHIFT       (7u)
+#define INTC_ICDICFR12_INTIICTMOI0_0_SHIFT      (8u)
+#define INTC_ICDICFR12_INTIICTMOI0_1_SHIFT      (9u)
+#define INTC_ICDICFR12_INTIICTEI1_0_SHIFT       (10u)
+#define INTC_ICDICFR12_INTIICTEI1_1_SHIFT       (11u)
+#define INTC_ICDICFR12_INTIICRI1_0_SHIFT        (12u)
+#define INTC_ICDICFR12_INTIICRI1_1_SHIFT        (13u)
+#define INTC_ICDICFR12_INTIICTI1_0_SHIFT        (14u)
+#define INTC_ICDICFR12_INTIICTI1_1_SHIFT        (15u)
+#define INTC_ICDICFR12_INTIICSPI1_0_SHIFT       (16u)
+#define INTC_ICDICFR12_INTIICSPI1_1_SHIFT       (17u)
+#define INTC_ICDICFR12_INTIICSTI1_0_SHIFT       (18u)
+#define INTC_ICDICFR12_INTIICSTI1_1_SHIFT       (19u)
+#define INTC_ICDICFR12_INTIICNAKI1_0_SHIFT      (20u)
+#define INTC_ICDICFR12_INTIICNAKI1_1_SHIFT      (21u)
+#define INTC_ICDICFR12_INTIICALI1_0_SHIFT       (22u)
+#define INTC_ICDICFR12_INTIICALI1_1_SHIFT       (23u)
+#define INTC_ICDICFR12_INTIICTMOI1_0_SHIFT      (24u)
+#define INTC_ICDICFR12_INTIICTMOI1_1_SHIFT      (25u)
+#define INTC_ICDICFR12_INTIICTEI2_0_SHIFT       (26u)
+#define INTC_ICDICFR12_INTIICTEI2_1_SHIFT       (27u)
+#define INTC_ICDICFR12_INTIICRI2_0_SHIFT        (28u)
+#define INTC_ICDICFR12_INTIICRI2_1_SHIFT        (29u)
+#define INTC_ICDICFR12_INTIICTI2_0_SHIFT        (30u)
+#define INTC_ICDICFR12_INTIICTI2_1_SHIFT        (31u)
+
+#define INTC_ICDICFR13_INTIICSPI2_0_SHIFT       (0u)
+#define INTC_ICDICFR13_INTIICSPI2_1_SHIFT       (1u)
+#define INTC_ICDICFR13_INTIICSTI2_0_SHIFT       (2u)
+#define INTC_ICDICFR13_INTIICSTI2_1_SHIFT       (3u)
+#define INTC_ICDICFR13_INTIICNAKI2_0_SHIFT      (4u)
+#define INTC_ICDICFR13_INTIICNAKI2_1_SHIFT      (5u)
+#define INTC_ICDICFR13_INTIICALI2_0_SHIFT       (6u)
+#define INTC_ICDICFR13_INTIICALI2_1_SHIFT       (7u)
+#define INTC_ICDICFR13_INTIICTMOI2_0_SHIFT      (8u)
+#define INTC_ICDICFR13_INTIICTMOI2_1_SHIFT      (9u)
+#define INTC_ICDICFR13_INTIICTEI3_0_SHIFT       (10u)
+#define INTC_ICDICFR13_INTIICTEI3_1_SHIFT       (11u)
+#define INTC_ICDICFR13_INTIICRI3_0_SHIFT        (12u)
+#define INTC_ICDICFR13_INTIICRI3_1_SHIFT        (13u)
+#define INTC_ICDICFR13_INTIICTI3_0_SHIFT        (14u)
+#define INTC_ICDICFR13_INTIICTI3_1_SHIFT        (15u)
+#define INTC_ICDICFR13_INTIICSPI3_0_SHIFT       (16u)
+#define INTC_ICDICFR13_INTIICSPI3_1_SHIFT       (17u)
+#define INTC_ICDICFR13_INTIICSTI3_0_SHIFT       (18u)
+#define INTC_ICDICFR13_INTIICSTI3_1_SHIFT       (19u)
+#define INTC_ICDICFR13_INTIICNAKI3_0_SHIFT      (20u)
+#define INTC_ICDICFR13_INTIICNAKI3_1_SHIFT      (21u)
+#define INTC_ICDICFR13_INTIICALI3_0_SHIFT       (22u)
+#define INTC_ICDICFR13_INTIICALI3_1_SHIFT       (23u)
+#define INTC_ICDICFR13_INTIICTMOI3_0_SHIFT      (24u)
+#define INTC_ICDICFR13_INTIICTMOI3_1_SHIFT      (25u)
+#define INTC_ICDICFR13_BRI0_0_SHIFT             (26u)
+#define INTC_ICDICFR13_BRI0_1_SHIFT             (27u)
+#define INTC_ICDICFR13_ERI0_0_SHIFT             (28u)
+#define INTC_ICDICFR13_ERI0_1_SHIFT             (29u)
+#define INTC_ICDICFR13_RXI0_0_SHIFT             (30u)
+#define INTC_ICDICFR13_RXI0_1_SHIFT             (31u)
+
+#define INTC_ICDICFR14_TXI0_0_SHIFT             (0u)
+#define INTC_ICDICFR14_TXI0_1_SHIFT             (1u)
+#define INTC_ICDICFR14_BRI1_0_SHIFT             (2u)
+#define INTC_ICDICFR14_BRI1_1_SHIFT             (3u)
+#define INTC_ICDICFR14_ERI1_0_SHIFT             (4u)
+#define INTC_ICDICFR14_ERI1_1_SHIFT             (5u)
+#define INTC_ICDICFR14_RXI1_0_SHIFT             (6u)
+#define INTC_ICDICFR14_RXI1_1_SHIFT             (7u)
+#define INTC_ICDICFR14_TXI1_0_SHIFT             (8u)
+#define INTC_ICDICFR14_TXI1_1_SHIFT             (9u)
+#define INTC_ICDICFR14_BRI2_0_SHIFT             (10u)
+#define INTC_ICDICFR14_BRI2_1_SHIFT             (11u)
+#define INTC_ICDICFR14_ERI2_0_SHIFT             (12u)
+#define INTC_ICDICFR14_ERI2_1_SHIFT             (13u)
+#define INTC_ICDICFR14_RXI2_0_SHIFT             (14u)
+#define INTC_ICDICFR14_RXI2_1_SHIFT             (15u)
+#define INTC_ICDICFR14_TXI2_0_SHIFT             (16u)
+#define INTC_ICDICFR14_TXI2_1_SHIFT             (17u)
+#define INTC_ICDICFR14_BRI3_0_SHIFT             (18u)
+#define INTC_ICDICFR14_BRI3_1_SHIFT             (19u)
+#define INTC_ICDICFR14_ERI3_0_SHIFT             (20u)
+#define INTC_ICDICFR14_ERI3_1_SHIFT             (21u)
+#define INTC_ICDICFR14_RXI3_0_SHIFT             (22u)
+#define INTC_ICDICFR14_RXI3_1_SHIFT             (23u)
+#define INTC_ICDICFR14_TXI3_0_SHIFT             (24u)
+#define INTC_ICDICFR14_TXI3_1_SHIFT             (25u)
+#define INTC_ICDICFR14_BRI4_0_SHIFT             (26u)
+#define INTC_ICDICFR14_BRI4_1_SHIFT             (27u)
+#define INTC_ICDICFR14_ERI4_0_SHIFT             (28u)
+#define INTC_ICDICFR14_ERI4_1_SHIFT             (29u)
+#define INTC_ICDICFR14_RXI4_0_SHIFT             (30u)
+#define INTC_ICDICFR14_RXI4_1_SHIFT             (31u)
+
+#define INTC_ICDICFR15_TXI4_0_SHIFT             (0u)
+#define INTC_ICDICFR15_TXI4_1_SHIFT             (1u)
+#define INTC_ICDICFR15_BRI5_0_SHIFT             (2u)
+#define INTC_ICDICFR15_BRI5_1_SHIFT             (3u)
+#define INTC_ICDICFR15_ERI5_0_SHIFT             (4u)
+#define INTC_ICDICFR15_ERI5_1_SHIFT             (5u)
+#define INTC_ICDICFR15_RXI5_0_SHIFT             (6u)
+#define INTC_ICDICFR15_RXI5_1_SHIFT             (7u)
+#define INTC_ICDICFR15_TXI5_0_SHIFT             (8u)
+#define INTC_ICDICFR15_TXI5_1_SHIFT             (9u)
+#define INTC_ICDICFR15_BRI6_0_SHIFT             (10u)
+#define INTC_ICDICFR15_BRI6_1_SHIFT             (11u)
+#define INTC_ICDICFR15_ERI6_0_SHIFT             (12u)
+#define INTC_ICDICFR15_ERI6_1_SHIFT             (13u)
+#define INTC_ICDICFR15_RXI6_0_SHIFT             (14u)
+#define INTC_ICDICFR15_RXI6_1_SHIFT             (15u)
+#define INTC_ICDICFR15_TXI6_0_SHIFT             (16u)
+#define INTC_ICDICFR15_TXI6_1_SHIFT             (17u)
+#define INTC_ICDICFR15_BRI7_0_SHIFT             (18u)
+#define INTC_ICDICFR15_BRI7_1_SHIFT             (19u)
+#define INTC_ICDICFR15_ERI7_0_SHIFT             (20u)
+#define INTC_ICDICFR15_ERI7_1_SHIFT             (21u)
+#define INTC_ICDICFR15_RXI7_0_SHIFT             (22u)
+#define INTC_ICDICFR15_RXI7_1_SHIFT             (23u)
+#define INTC_ICDICFR15_TXI7_0_SHIFT             (24u)
+#define INTC_ICDICFR15_TXI7_1_SHIFT             (25u)
+#define INTC_ICDICFR15_INTRCANGERR_0_SHIFT      (26u)
+#define INTC_ICDICFR15_INTRCANGERR_1_SHIFT      (27u)
+#define INTC_ICDICFR15_INTRCANGRECC_0_SHIFT     (28u)
+#define INTC_ICDICFR15_INTRCANGRECC_1_SHIFT     (29u)
+#define INTC_ICDICFR15_INTRCAN0REC_0_SHIFT      (30u)
+#define INTC_ICDICFR15_INTRCAN0REC_1_SHIFT      (31u)
+
+#define INTC_ICDICFR16_INTRCAN0ERR_0_SHIFT      (0u)
+#define INTC_ICDICFR16_INTRCAN0ERR_1_SHIFT      (1u)
+#define INTC_ICDICFR16_INTRCAN0TRX_0_SHIFT      (2u)
+#define INTC_ICDICFR16_INTRCAN0TRX_1_SHIFT      (3u)
+#define INTC_ICDICFR16_INTRCAN1REC_0_SHIFT      (4u)
+#define INTC_ICDICFR16_INTRCAN1REC_1_SHIFT      (5u)
+#define INTC_ICDICFR16_INTRCAN1ERR_0_SHIFT      (6u)
+#define INTC_ICDICFR16_INTRCAN1ERR_1_SHIFT      (7u)
+#define INTC_ICDICFR16_INTRCAN1TRX_0_SHIFT      (8u)
+#define INTC_ICDICFR16_INTRCAN1TRX_1_SHIFT      (9u)
+#define INTC_ICDICFR16_INTRCAN2REC_0_SHIFT      (10u)
+#define INTC_ICDICFR16_INTRCAN2REC_1_SHIFT      (11u)
+#define INTC_ICDICFR16_INTRCAN2ERR_0_SHIFT      (12u)
+#define INTC_ICDICFR16_INTRCAN2ERR_1_SHIFT      (13u)
+#define INTC_ICDICFR16_INTRCAN2TRX_0_SHIFT      (14u)
+#define INTC_ICDICFR16_INTRCAN2TRX_1_SHIFT      (15u)
+#define INTC_ICDICFR16_INTRCAN3REC_0_SHIFT      (16u)
+#define INTC_ICDICFR16_INTRCAN3REC_1_SHIFT      (17u)
+#define INTC_ICDICFR16_INTRCAN3ERR_0_SHIFT      (18u)
+#define INTC_ICDICFR16_INTRCAN3ERR_1_SHIFT      (19u)
+#define INTC_ICDICFR16_INTRCAN3TRX_0_SHIFT      (20u)
+#define INTC_ICDICFR16_INTRCAN3TRX_1_SHIFT      (21u)
+#define INTC_ICDICFR16_INTRCAN4REC_0_SHIFT      (22u)
+#define INTC_ICDICFR16_INTRCAN4REC_1_SHIFT      (23u)
+#define INTC_ICDICFR16_INTRCAN4ERR_0_SHIFT      (24u)
+#define INTC_ICDICFR16_INTRCAN4ERR_1_SHIFT      (25u)
+#define INTC_ICDICFR16_INTRCAN4TRX_0_SHIFT      (26u)
+#define INTC_ICDICFR16_INTRCAN4TRX_1_SHIFT      (27u)
+#define INTC_ICDICFR16_SPEI0_0_SHIFT            (28u)
+#define INTC_ICDICFR16_SPEI0_1_SHIFT            (29u)
+#define INTC_ICDICFR16_SPRI0_0_SHIFT            (30u)
+#define INTC_ICDICFR16_SPRI0_1_SHIFT            (31u)
+
+#define INTC_ICDICFR17_SPTI0_0_SHIFT            (0u)
+#define INTC_ICDICFR17_SPTI0_1_SHIFT            (1u)
+#define INTC_ICDICFR17_SPEI1_0_SHIFT            (2u)
+#define INTC_ICDICFR17_SPEI1_1_SHIFT            (3u)
+#define INTC_ICDICFR17_SPRI1_0_SHIFT            (4u)
+#define INTC_ICDICFR17_SPRI1_1_SHIFT            (5u)
+#define INTC_ICDICFR17_SPTI1_0_SHIFT            (6u)
+#define INTC_ICDICFR17_SPTI1_1_SHIFT            (7u)
+#define INTC_ICDICFR17_SPEI2_0_SHIFT            (8u)
+#define INTC_ICDICFR17_SPEI2_1_SHIFT            (9u)
+#define INTC_ICDICFR17_SPRI2_0_SHIFT            (10u)
+#define INTC_ICDICFR17_SPRI2_1_SHIFT            (11u)
+#define INTC_ICDICFR17_SPTI2_0_SHIFT            (12u)
+#define INTC_ICDICFR17_SPTI2_1_SHIFT            (13u)
+#define INTC_ICDICFR17_SPEI3_0_SHIFT            (14u)
+#define INTC_ICDICFR17_SPEI3_1_SHIFT            (15u)
+#define INTC_ICDICFR17_SPRI3_0_SHIFT            (16u)
+#define INTC_ICDICFR17_SPRI3_1_SHIFT            (17u)
+#define INTC_ICDICFR17_SPTI3_0_SHIFT            (18u)
+#define INTC_ICDICFR17_SPTI3_1_SHIFT            (19u)
+#define INTC_ICDICFR17_SPEI4_0_SHIFT            (20u)
+#define INTC_ICDICFR17_SPEI4_1_SHIFT            (21u)
+#define INTC_ICDICFR17_SPRI4_0_SHIFT            (22u)
+#define INTC_ICDICFR17_SPRI4_1_SHIFT            (23u)
+#define INTC_ICDICFR17_SPTI4_0_SHIFT            (24u)
+#define INTC_ICDICFR17_SPTI4_1_SHIFT            (25u)
+#define INTC_ICDICFR17_IEBBTD_0_SHIFT           (26u)
+#define INTC_ICDICFR17_IEBBTD_1_SHIFT           (27u)
+#define INTC_ICDICFR17_IEBBTERR_0_SHIFT         (28u)
+#define INTC_ICDICFR17_IEBBTERR_1_SHIFT         (29u)
+#define INTC_ICDICFR17_IEBBTSTA_0_SHIFT         (30u)
+#define INTC_ICDICFR17_IEBBTSTA_1_SHIFT         (31u)
+
+#define INTC_ICDICFR18_IEBBTV_0_SHIFT           (0u)
+#define INTC_ICDICFR18_IEBBTV_1_SHIFT           (1u)
+#define INTC_ICDICFR18_ISY_0_SHIFT              (2u)
+#define INTC_ICDICFR18_ISY_1_SHIFT              (3u)
+#define INTC_ICDICFR18_IERR_0_SHIFT             (4u)
+#define INTC_ICDICFR18_IERR_1_SHIFT             (5u)
+#define INTC_ICDICFR18_ITARG_0_SHIFT            (6u)
+#define INTC_ICDICFR18_ITARG_1_SHIFT            (7u)
+#define INTC_ICDICFR18_ISEC_0_SHIFT             (8u)
+#define INTC_ICDICFR18_ISEC_1_SHIFT             (9u)
+#define INTC_ICDICFR18_IBUF_0_SHIFT             (10u)
+#define INTC_ICDICFR18_IBUF_1_SHIFT             (11u)
+#define INTC_ICDICFR18_IREADY_0_SHIFT           (12u)
+#define INTC_ICDICFR18_IREADY_1_SHIFT           (13u)
+#define INTC_ICDICFR18_FLSTE_0_SHIFT            (14u)
+#define INTC_ICDICFR18_FLSTE_1_SHIFT            (15u)
+#define INTC_ICDICFR18_FLTENDI_0_SHIFT          (16u)
+#define INTC_ICDICFR18_FLTENDI_1_SHIFT          (17u)
+#define INTC_ICDICFR18_FLTREQ0I_0_SHIFT         (18u)
+#define INTC_ICDICFR18_FLTREQ0I_1_SHIFT         (19u)
+#define INTC_ICDICFR18_FLTREQ1I_0_SHIFT         (20u)
+#define INTC_ICDICFR18_FLTREQ1I_1_SHIFT         (21u)
+#define INTC_ICDICFR18_MMC0_0_SHIFT             (22u)
+#define INTC_ICDICFR18_MMC0_1_SHIFT             (23u)
+#define INTC_ICDICFR18_MMC1_0_SHIFT             (24u)
+#define INTC_ICDICFR18_MMC1_1_SHIFT             (25u)
+#define INTC_ICDICFR18_MMC2_0_SHIFT             (26u)
+#define INTC_ICDICFR18_MMC2_1_SHIFT             (27u)
+#define INTC_ICDICFR18_SDHI0_3_0_SHIFT          (28u)
+#define INTC_ICDICFR18_SDHI0_3_1_SHIFT          (29u)
+#define INTC_ICDICFR18_SDHI0_0_0_SHIFT          (30u)
+#define INTC_ICDICFR18_SDHI0_0_1_SHIFT          (31u)
+
+#define INTC_ICDICFR19_SDHI0_1_0_SHIFT          (0u)
+#define INTC_ICDICFR19_SDHI0_1_1_SHIFT          (1u)
+#define INTC_ICDICFR19_SDHI1_3_0_SHIFT          (2u)
+#define INTC_ICDICFR19_SDHI1_3_1_SHIFT          (3u)
+#define INTC_ICDICFR19_SDHI1_0_0_SHIFT          (4u)
+#define INTC_ICDICFR19_SDHI1_0_1_SHIFT          (5u)
+#define INTC_ICDICFR19_SDHI1_1_0_SHIFT          (6u)
+#define INTC_ICDICFR19_SDHI1_1_1_SHIFT          (7u)
+#define INTC_ICDICFR19_ARM_0_SHIFT              (8u)
+#define INTC_ICDICFR19_ARM_1_SHIFT              (9u)
+#define INTC_ICDICFR19_PRD_0_SHIFT              (10u)
+#define INTC_ICDICFR19_PRD_1_SHIFT              (11u)
+#define INTC_ICDICFR19_CUP_0_SHIFT              (12u)
+#define INTC_ICDICFR19_CUP_1_SHIFT              (13u)
+#define INTC_ICDICFR19_SCUAI0_0_SHIFT           (14u)
+#define INTC_ICDICFR19_SCUAI0_1_SHIFT           (15u)
+#define INTC_ICDICFR19_SCUAI1_0_SHIFT           (16u)
+#define INTC_ICDICFR19_SCUAI1_1_SHIFT           (17u)
+#define INTC_ICDICFR19_SCUFDI0_0_SHIFT          (18u)
+#define INTC_ICDICFR19_SCUFDI0_1_SHIFT          (19u)
+#define INTC_ICDICFR19_SCUFDI1_0_SHIFT          (20u)
+#define INTC_ICDICFR19_SCUFDI1_1_SHIFT          (21u)
+#define INTC_ICDICFR19_SCUFDI2_0_SHIFT          (22u)
+#define INTC_ICDICFR19_SCUFDI2_1_SHIFT          (23u)
+#define INTC_ICDICFR19_SCUFDI3_0_SHIFT          (24u)
+#define INTC_ICDICFR19_SCUFDI3_1_SHIFT          (25u)
+#define INTC_ICDICFR19_SCUFUI0_0_SHIFT          (26u)
+#define INTC_ICDICFR19_SCUFUI0_1_SHIFT          (27u)
+#define INTC_ICDICFR19_SCUFUI1_0_SHIFT          (28u)
+#define INTC_ICDICFR19_SCUFUI1_1_SHIFT          (29u)
+#define INTC_ICDICFR19_SCUFUI2_0_SHIFT          (30u)
+#define INTC_ICDICFR19_SCUFUI2_1_SHIFT          (31u)
+
+#define INTC_ICDICFR20_SCUFUI3_0_SHIFT          (0u)
+#define INTC_ICDICFR20_SCUFUI3_1_SHIFT          (1u)
+#define INTC_ICDICFR20_SCUDVI0_0_SHIFT          (2u)
+#define INTC_ICDICFR20_SCUDVI0_1_SHIFT          (3u)
+#define INTC_ICDICFR20_SCUDVI1_0_SHIFT          (4u)
+#define INTC_ICDICFR20_SCUDVI1_1_SHIFT          (5u)
+#define INTC_ICDICFR20_SCUDVI2_0_SHIFT          (6u)
+#define INTC_ICDICFR20_SCUDVI2_1_SHIFT          (7u)
+#define INTC_ICDICFR20_SCUDVI3_0_SHIFT          (8u)
+#define INTC_ICDICFR20_SCUDVI3_1_SHIFT          (9u)
+#define INTC_ICDICFR20_MLB_CINT_0_SHIFT         (10u)
+#define INTC_ICDICFR20_MLB_CINT_1_SHIFT         (11u)
+#define INTC_ICDICFR20_MLB_SINT_0_SHIFT         (12u)
+#define INTC_ICDICFR20_MLB_SINT_1_SHIFT         (13u)
+#define INTC_ICDICFR20_DRC0_0_SHIFT             (14u)
+#define INTC_ICDICFR20_DRC0_1_SHIFT             (15u)
+#define INTC_ICDICFR20_DRC1_0_SHIFT             (16u)
+#define INTC_ICDICFR20_DRC1_1_SHIFT             (17u)
+#define INTC_ICDICFR20_LINI0_INT_T_0_SHIFT      (22u)
+#define INTC_ICDICFR20_LINI0_INT_T_1_SHIFT      (23u)
+#define INTC_ICDICFR20_LINI0_INT_R_0_SHIFT      (24u)
+#define INTC_ICDICFR20_LINI0_INT_R_1_SHIFT      (25u)
+#define INTC_ICDICFR20_LINI0_INT_S_0_SHIFT      (26u)
+#define INTC_ICDICFR20_LINI0_INT_S_1_SHIFT      (27u)
+#define INTC_ICDICFR20_LINI0_INT_M_0_SHIFT      (28u)
+#define INTC_ICDICFR20_LINI0_INT_M_1_SHIFT      (29u)
+#define INTC_ICDICFR20_LINI1_INT_T_0_SHIFT      (30u)
+#define INTC_ICDICFR20_LINI1_INT_T_1_SHIFT      (31u)
+
+#define INTC_ICDICFR21_LINI1_INT_R_0_SHIFT      (0u)
+#define INTC_ICDICFR21_LINI1_INT_R_1_SHIFT      (1u)
+#define INTC_ICDICFR21_LINI1_INT_S_0_SHIFT      (2u)
+#define INTC_ICDICFR21_LINI1_INT_S_1_SHIFT      (3u)
+#define INTC_ICDICFR21_LINI1_INT_M_0_SHIFT      (4u)
+#define INTC_ICDICFR21_LINI1_INT_M_1_SHIFT      (5u)
+#define INTC_ICDICFR21_ERI0_0_SHIFT             (22u)
+#define INTC_ICDICFR21_ERI0_1_SHIFT             (23u)
+#define INTC_ICDICFR21_RXI0_0_SHIFT             (24u)
+#define INTC_ICDICFR21_RXI0_1_SHIFT             (25u)
+#define INTC_ICDICFR21_TXI0_0_SHIFT             (26u)
+#define INTC_ICDICFR21_TXI0_1_SHIFT             (27u)
+#define INTC_ICDICFR21_TEI0_0_SHIFT             (28u)
+#define INTC_ICDICFR21_TEI0_1_SHIFT             (29u)
+#define INTC_ICDICFR21_ERI1_0_SHIFT             (30u)
+#define INTC_ICDICFR21_ERI1_1_SHIFT             (31u)
+
+#define INTC_ICDICFR22_RXI1_0_SHIFT             (0u)
+#define INTC_ICDICFR22_RXI1_1_SHIFT             (1u)
+#define INTC_ICDICFR22_TXI1_0_SHIFT             (2u)
+#define INTC_ICDICFR22_TXI1_1_SHIFT             (3u)
+#define INTC_ICDICFR22_TEI1_0_SHIFT             (4u)
+#define INTC_ICDICFR22_TEI1_1_SHIFT             (5u)
+#define INTC_ICDICFR22_AVBI_DATA_0_SHIFT        (6u)
+#define INTC_ICDICFR22_AVBI_DATA_1_SHIFT        (7u)
+#define INTC_ICDICFR22_AVBI_ERROR_0_SHIFT       (8u)
+#define INTC_ICDICFR22_AVBI_ERROR_1_SHIFT       (9u)
+#define INTC_ICDICFR22_AVBI_MANAGE_0_SHIFT      (10u)
+#define INTC_ICDICFR22_AVBI_MANAGE_1_SHIFT      (11u)
+#define INTC_ICDICFR22_AVBI_MAC_0_SHIFT         (12u)
+#define INTC_ICDICFR22_AVBI_MAC_1_SHIFT         (13u)
+#define INTC_ICDICFR22_ETHERI_0_SHIFT           (14u)
+#define INTC_ICDICFR22_ETHERI_1_SHIFT           (15u)
+#define INTC_ICDICFR22_CEUI_0_SHIFT             (24u)
+#define INTC_ICDICFR22_CEUI_1_SHIFT             (25u)
+
+#define INTC_ICDICFR23_H2XMLB_ERRINT_0_SHIFT    (26u)
+#define INTC_ICDICFR23_H2XMLB_ERRINT_1_SHIFT    (27u)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_0_SHIFT    (28u)
+#define INTC_ICDICFR23_H2XIC1_ERRINT_1_SHIFT    (29u)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_0_SHIFT  (30u)
+#define INTC_ICDICFR23_X2HPERI1_ERRINT_1_SHIFT  (31u)
+
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_0_SHIFT  (0u)
+#define INTC_ICDICFR24_X2HPERI2_ERRINT_1_SHIFT  (1u)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_0_SHIFT (2u)
+#define INTC_ICDICFR24_X2HPERI34_ERRINT_1_SHIFT (3u)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_0_SHIFT  (4u)
+#define INTC_ICDICFR24_X2HPERI5_ERRINT_1_SHIFT  (5u)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_0_SHIFT (6u)
+#define INTC_ICDICFR24_X2HPERI67_ERRINT_1_SHIFT (7u)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_0_SHIFT   (8u)
+#define INTC_ICDICFR24_X2HDBGR_ERRINT_1_SHIFT   (9u)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_0_SHIFT    (10u)
+#define INTC_ICDICFR24_X2HBSC_ERRINT_1_SHIFT    (11u)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_0_SHIFT   (12u)
+#define INTC_ICDICFR24_X2HSPI1_ERRINT_1_SHIFT   (13u)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_0_SHIFT   (14u)
+#define INTC_ICDICFR24_X2HSPI2_ERRINT_1_SHIFT   (15u)
+#define INTC_ICDICFR24_PRRI_0_SHIFT             (16u)
+#define INTC_ICDICFR24_PRRI_1_SHIFT             (17u)
+#define INTC_ICDICFR24_IFEI0_0_SHIFT            (18u)
+#define INTC_ICDICFR24_IFEI0_1_SHIFT            (19u)
+#define INTC_ICDICFR24_OFFI0_0_SHIFT            (20u)
+#define INTC_ICDICFR24_OFFI0_1_SHIFT            (21u)
+#define INTC_ICDICFR24_PFVEI0_0_SHIFT           (22u)
+#define INTC_ICDICFR24_PFVEI0_1_SHIFT           (23u)
+#define INTC_ICDICFR24_IFEI1_0_SHIFT            (24u)
+#define INTC_ICDICFR24_IFEI1_1_SHIFT            (25u)
+#define INTC_ICDICFR24_OFFI1_0_SHIFT            (26u)
+#define INTC_ICDICFR24_OFFI1_1_SHIFT            (27u)
+#define INTC_ICDICFR24_PFVEI1_0_SHIFT           (28u)
+#define INTC_ICDICFR24_PFVEI1_1_SHIFT           (29u)
+
+#define INTC_ICDICFR26_TINT0_0_SHIFT            (0u)
+#define INTC_ICDICFR26_TINT0_1_SHIFT            (1u)
+#define INTC_ICDICFR26_TINT1_0_SHIFT            (2u)
+#define INTC_ICDICFR26_TINT1_1_SHIFT            (3u)
+#define INTC_ICDICFR26_TINT2_0_SHIFT            (4u)
+#define INTC_ICDICFR26_TINT2_1_SHIFT            (5u)
+#define INTC_ICDICFR26_TINT3_0_SHIFT            (6u)
+#define INTC_ICDICFR26_TINT3_1_SHIFT            (7u)
+#define INTC_ICDICFR26_TINT4_0_SHIFT            (8u)
+#define INTC_ICDICFR26_TINT4_1_SHIFT            (9u)
+#define INTC_ICDICFR26_TINT5_0_SHIFT            (10u)
+#define INTC_ICDICFR26_TINT5_1_SHIFT            (11u)
+#define INTC_ICDICFR26_TINT6_0_SHIFT            (12u)
+#define INTC_ICDICFR26_TINT6_1_SHIFT            (13u)
+#define INTC_ICDICFR26_TINT7_0_SHIFT            (14u)
+#define INTC_ICDICFR26_TINT7_1_SHIFT            (15u)
+#define INTC_ICDICFR26_TINT8_0_SHIFT            (16u)
+#define INTC_ICDICFR26_TINT8_1_SHIFT            (17u)
+#define INTC_ICDICFR26_TINT9_0_SHIFT            (18u)
+#define INTC_ICDICFR26_TINT9_1_SHIFT            (19u)
+#define INTC_ICDICFR26_TINT10_0_SHIFT           (20u)
+#define INTC_ICDICFR26_TINT10_1_SHIFT           (21u)
+#define INTC_ICDICFR26_TINT11_0_SHIFT           (22u)
+#define INTC_ICDICFR26_TINT11_1_SHIFT           (23u)
+#define INTC_ICDICFR26_TINT12_0_SHIFT           (24u)
+#define INTC_ICDICFR26_TINT12_1_SHIFT           (25u)
+#define INTC_ICDICFR26_TINT13_0_SHIFT           (26u)
+#define INTC_ICDICFR26_TINT13_1_SHIFT           (27u)
+#define INTC_ICDICFR26_TINT14_0_SHIFT           (28u)
+#define INTC_ICDICFR26_TINT14_1_SHIFT           (29u)
+#define INTC_ICDICFR26_TINT15_0_SHIFT           (30u)
+#define INTC_ICDICFR26_TINT15_1_SHIFT           (31u)
+
+#define INTC_ICDICFR27_TINT16_0_SHIFT           (0u)
+#define INTC_ICDICFR27_TINT16_1_SHIFT           (1u)
+#define INTC_ICDICFR27_TINT17_0_SHIFT           (2u)
+#define INTC_ICDICFR27_TINT17_1_SHIFT           (3u)
+#define INTC_ICDICFR27_TINT18_0_SHIFT           (4u)
+#define INTC_ICDICFR27_TINT18_1_SHIFT           (5u)
+#define INTC_ICDICFR27_TINT19_0_SHIFT           (6u)
+#define INTC_ICDICFR27_TINT19_1_SHIFT           (7u)
+#define INTC_ICDICFR27_TINT20_0_SHIFT           (8u)
+#define INTC_ICDICFR27_TINT20_1_SHIFT           (9u)
+#define INTC_ICDICFR27_TINT21_0_SHIFT           (10u)
+#define INTC_ICDICFR27_TINT21_1_SHIFT           (11u)
+#define INTC_ICDICFR27_TINT22_0_SHIFT           (12u)
+#define INTC_ICDICFR27_TINT22_1_SHIFT           (13u)
+#define INTC_ICDICFR27_TINT23_0_SHIFT           (14u)
+#define INTC_ICDICFR27_TINT23_1_SHIFT           (15u)
+#define INTC_ICDICFR27_TINT24_0_SHIFT           (16u)
+#define INTC_ICDICFR27_TINT24_1_SHIFT           (17u)
+#define INTC_ICDICFR27_TINT25_0_SHIFT           (18u)
+#define INTC_ICDICFR27_TINT25_1_SHIFT           (19u)
+#define INTC_ICDICFR27_TINT26_0_SHIFT           (20u)
+#define INTC_ICDICFR27_TINT26_1_SHIFT           (21u)
+#define INTC_ICDICFR27_TINT27_0_SHIFT           (22u)
+#define INTC_ICDICFR27_TINT27_1_SHIFT           (23u)
+#define INTC_ICDICFR27_TINT28_0_SHIFT           (24u)
+#define INTC_ICDICFR27_TINT28_1_SHIFT           (25u)
+#define INTC_ICDICFR27_TINT29_0_SHIFT           (26u)
+#define INTC_ICDICFR27_TINT29_1_SHIFT           (27u)
+#define INTC_ICDICFR27_TINT30_0_SHIFT           (28u)
+#define INTC_ICDICFR27_TINT30_1_SHIFT           (29u)
+#define INTC_ICDICFR27_TINT31_0_SHIFT           (30u)
+#define INTC_ICDICFR27_TINT31_1_SHIFT           (31u)
+
+#define INTC_ICDICFR28_TINT32_0_SHIFT           (0u)
+#define INTC_ICDICFR28_TINT32_1_SHIFT           (1u)
+#define INTC_ICDICFR28_TINT33_0_SHIFT           (2u)
+#define INTC_ICDICFR28_TINT33_1_SHIFT           (3u)
+#define INTC_ICDICFR28_TINT34_0_SHIFT           (4u)
+#define INTC_ICDICFR28_TINT34_1_SHIFT           (5u)
+#define INTC_ICDICFR28_TINT35_0_SHIFT           (6u)
+#define INTC_ICDICFR28_TINT35_1_SHIFT           (7u)
+#define INTC_ICDICFR28_TINT36_0_SHIFT           (8u)
+#define INTC_ICDICFR28_TINT36_1_SHIFT           (9u)
+#define INTC_ICDICFR28_TINT37_0_SHIFT           (10u)
+#define INTC_ICDICFR28_TINT37_1_SHIFT           (11u)
+#define INTC_ICDICFR28_TINT38_0_SHIFT           (12u)
+#define INTC_ICDICFR28_TINT38_1_SHIFT           (13u)
+#define INTC_ICDICFR28_TINT39_0_SHIFT           (14u)
+#define INTC_ICDICFR28_TINT39_1_SHIFT           (15u)
+#define INTC_ICDICFR28_TINT40_0_SHIFT           (16u)
+#define INTC_ICDICFR28_TINT40_1_SHIFT           (17u)
+#define INTC_ICDICFR28_TINT41_0_SHIFT           (18u)
+#define INTC_ICDICFR28_TINT41_1_SHIFT           (19u)
+#define INTC_ICDICFR28_TINT42_0_SHIFT           (20u)
+#define INTC_ICDICFR28_TINT42_1_SHIFT           (21u)
+#define INTC_ICDICFR28_TINT43_0_SHIFT           (22u)
+#define INTC_ICDICFR28_TINT43_1_SHIFT           (23u)
+#define INTC_ICDICFR28_TINT44_0_SHIFT           (24u)
+#define INTC_ICDICFR28_TINT44_1_SHIFT           (25u)
+#define INTC_ICDICFR28_TINT45_0_SHIFT           (26u)
+#define INTC_ICDICFR28_TINT45_1_SHIFT           (27u)
+#define INTC_ICDICFR28_TINT46_0_SHIFT           (28u)
+#define INTC_ICDICFR28_TINT46_1_SHIFT           (29u)
+#define INTC_ICDICFR28_TINT47_0_SHIFT           (30u)
+#define INTC_ICDICFR28_TINT47_1_SHIFT           (31u)
+
+#define INTC_ICDICFR29_TINT48_0_SHIFT           (0u)
+#define INTC_ICDICFR29_TINT48_1_SHIFT           (1u)
+#define INTC_ICDICFR29_TINT49_0_SHIFT           (2u)
+#define INTC_ICDICFR29_TINT49_1_SHIFT           (3u)
+#define INTC_ICDICFR29_TINT50_0_SHIFT           (4u)
+#define INTC_ICDICFR29_TINT50_1_SHIFT           (5u)
+#define INTC_ICDICFR29_TINT51_0_SHIFT           (6u)
+#define INTC_ICDICFR29_TINT51_1_SHIFT           (7u)
+#define INTC_ICDICFR29_TINT52_0_SHIFT           (8u)
+#define INTC_ICDICFR29_TINT52_1_SHIFT           (9u)
+#define INTC_ICDICFR29_TINT53_0_SHIFT           (10u)
+#define INTC_ICDICFR29_TINT53_1_SHIFT           (11u)
+#define INTC_ICDICFR29_TINT54_0_SHIFT           (12u)
+#define INTC_ICDICFR29_TINT54_1_SHIFT           (13u)
+#define INTC_ICDICFR29_TINT55_0_SHIFT           (14u)
+#define INTC_ICDICFR29_TINT55_1_SHIFT           (15u)
+#define INTC_ICDICFR29_TINT56_0_SHIFT           (16u)
+#define INTC_ICDICFR29_TINT56_1_SHIFT           (17u)
+#define INTC_ICDICFR29_TINT57_0_SHIFT           (18u)
+#define INTC_ICDICFR29_TINT57_1_SHIFT           (19u)
+#define INTC_ICDICFR29_TINT58_0_SHIFT           (20u)
+#define INTC_ICDICFR29_TINT58_1_SHIFT           (21u)
+#define INTC_ICDICFR29_TINT59_0_SHIFT           (22u)
+#define INTC_ICDICFR29_TINT59_1_SHIFT           (23u)
+#define INTC_ICDICFR29_TINT60_0_SHIFT           (24u)
+#define INTC_ICDICFR29_TINT60_1_SHIFT           (25u)
+#define INTC_ICDICFR29_TINT61_0_SHIFT           (26u)
+#define INTC_ICDICFR29_TINT61_1_SHIFT           (27u)
+#define INTC_ICDICFR29_TINT62_0_SHIFT           (28u)
+#define INTC_ICDICFR29_TINT62_1_SHIFT           (29u)
+#define INTC_ICDICFR29_TINT63_0_SHIFT           (30u)
+#define INTC_ICDICFR29_TINT63_1_SHIFT           (31u)
+
+#define INTC_ICDICFR30_TINT64_0_SHIFT           (0u)
+#define INTC_ICDICFR30_TINT64_1_SHIFT           (1u)
+#define INTC_ICDICFR30_TINT65_0_SHIFT           (2u)
+#define INTC_ICDICFR30_TINT65_1_SHIFT           (3u)
+#define INTC_ICDICFR30_TINT66_0_SHIFT           (4u)
+#define INTC_ICDICFR30_TINT66_1_SHIFT           (5u)
+#define INTC_ICDICFR30_TINT67_0_SHIFT           (6u)
+#define INTC_ICDICFR30_TINT67_1_SHIFT           (7u)
+#define INTC_ICDICFR30_TINT68_0_SHIFT           (8u)
+#define INTC_ICDICFR30_TINT68_1_SHIFT           (9u)
+#define INTC_ICDICFR30_TINT69_0_SHIFT           (10u)
+#define INTC_ICDICFR30_TINT69_1_SHIFT           (11u)
+#define INTC_ICDICFR30_TINT70_0_SHIFT           (12u)
+#define INTC_ICDICFR30_TINT70_1_SHIFT           (13u)
+#define INTC_ICDICFR30_TINT71_0_SHIFT           (14u)
+#define INTC_ICDICFR30_TINT71_1_SHIFT           (15u)
+#define INTC_ICDICFR30_TINT72_0_SHIFT           (16u)
+#define INTC_ICDICFR30_TINT72_1_SHIFT           (17u)
+#define INTC_ICDICFR30_TINT73_0_SHIFT           (18u)
+#define INTC_ICDICFR30_TINT73_1_SHIFT           (19u)
+#define INTC_ICDICFR30_TINT74_0_SHIFT           (20u)
+#define INTC_ICDICFR30_TINT74_1_SHIFT           (21u)
+#define INTC_ICDICFR30_TINT75_0_SHIFT           (22u)
+#define INTC_ICDICFR30_TINT75_1_SHIFT           (23u)
+#define INTC_ICDICFR30_TINT76_0_SHIFT           (24u)
+#define INTC_ICDICFR30_TINT76_1_SHIFT           (25u)
+#define INTC_ICDICFR30_TINT77_0_SHIFT           (26u)
+#define INTC_ICDICFR30_TINT77_1_SHIFT           (27u)
+#define INTC_ICDICFR30_TINT78_0_SHIFT           (28u)
+#define INTC_ICDICFR30_TINT78_1_SHIFT           (29u)
+#define INTC_ICDICFR30_TINT79_0_SHIFT           (30u)
+#define INTC_ICDICFR30_TINT79_1_SHIFT           (31u)
+
+#define INTC_ICDICFR31_TINT80_0_SHIFT           (0u)
+#define INTC_ICDICFR31_TINT80_1_SHIFT           (1u)
+#define INTC_ICDICFR31_TINT81_0_SHIFT           (2u)
+#define INTC_ICDICFR31_TINT81_1_SHIFT           (3u)
+#define INTC_ICDICFR31_TINT82_0_SHIFT           (4u)
+#define INTC_ICDICFR31_TINT82_1_SHIFT           (5u)
+#define INTC_ICDICFR31_TINT83_0_SHIFT           (6u)
+#define INTC_ICDICFR31_TINT83_1_SHIFT           (7u)
+#define INTC_ICDICFR31_TINT84_0_SHIFT           (8u)
+#define INTC_ICDICFR31_TINT84_1_SHIFT           (9u)
+#define INTC_ICDICFR31_TINT85_0_SHIFT           (10u)
+#define INTC_ICDICFR31_TINT85_1_SHIFT           (11u)
+#define INTC_ICDICFR31_TINT86_0_SHIFT           (12u)
+#define INTC_ICDICFR31_TINT86_1_SHIFT           (13u)
+#define INTC_ICDICFR31_TINT87_0_SHIFT           (14u)
+#define INTC_ICDICFR31_TINT87_1_SHIFT           (15u)
+#define INTC_ICDICFR31_TINT88_0_SHIFT           (16u)
+#define INTC_ICDICFR31_TINT88_1_SHIFT           (17u)
+#define INTC_ICDICFR31_TINT89_0_SHIFT           (18u)
+#define INTC_ICDICFR31_TINT89_1_SHIFT           (19u)
+#define INTC_ICDICFR31_TINT90_0_SHIFT           (20u)
+#define INTC_ICDICFR31_TINT90_1_SHIFT           (21u)
+#define INTC_ICDICFR31_TINT91_0_SHIFT           (22u)
+#define INTC_ICDICFR31_TINT91_1_SHIFT           (23u)
+#define INTC_ICDICFR31_TINT92_0_SHIFT           (24u)
+#define INTC_ICDICFR31_TINT92_1_SHIFT           (25u)
+#define INTC_ICDICFR31_TINT93_0_SHIFT           (26u)
+#define INTC_ICDICFR31_TINT93_1_SHIFT           (27u)
+#define INTC_ICDICFR31_TINT94_0_SHIFT           (28u)
+#define INTC_ICDICFR31_TINT94_1_SHIFT           (29u)
+#define INTC_ICDICFR31_TINT95_0_SHIFT           (30u)
+#define INTC_ICDICFR31_TINT95_1_SHIFT           (31u)
+
+#define INTC_ICDICFR32_TINT96_0_SHIFT           (0u)
+#define INTC_ICDICFR32_TINT96_1_SHIFT           (1u)
+#define INTC_ICDICFR32_TINT97_0_SHIFT           (2u)
+#define INTC_ICDICFR32_TINT97_1_SHIFT           (3u)
+#define INTC_ICDICFR32_TINT98_0_SHIFT           (4u)
+#define INTC_ICDICFR32_TINT98_1_SHIFT           (5u)
+#define INTC_ICDICFR32_TINT99_0_SHIFT           (6u)
+#define INTC_ICDICFR32_TINT99_1_SHIFT           (7u)
+#define INTC_ICDICFR32_TINT100_0_SHIFT          (8u)
+#define INTC_ICDICFR32_TINT100_1_SHIFT          (9u)
+#define INTC_ICDICFR32_TINT101_0_SHIFT          (10u)
+#define INTC_ICDICFR32_TINT101_1_SHIFT          (11u)
+#define INTC_ICDICFR32_TINT102_0_SHIFT          (12u)
+#define INTC_ICDICFR32_TINT102_1_SHIFT          (13u)
+#define INTC_ICDICFR32_TINT103_0_SHIFT          (14u)
+#define INTC_ICDICFR32_TINT103_1_SHIFT          (15u)
+#define INTC_ICDICFR32_TINT104_0_SHIFT          (16u)
+#define INTC_ICDICFR32_TINT104_1_SHIFT          (17u)
+#define INTC_ICDICFR32_TINT105_0_SHIFT          (18u)
+#define INTC_ICDICFR32_TINT105_1_SHIFT          (19u)
+#define INTC_ICDICFR32_TINT106_0_SHIFT          (20u)
+#define INTC_ICDICFR32_TINT106_1_SHIFT          (21u)
+#define INTC_ICDICFR32_TINT107_0_SHIFT          (22u)
+#define INTC_ICDICFR32_TINT107_1_SHIFT          (23u)
+#define INTC_ICDICFR32_TINT108_0_SHIFT          (24u)
+#define INTC_ICDICFR32_TINT108_1_SHIFT          (25u)
+#define INTC_ICDICFR32_TINT109_0_SHIFT          (26u)
+#define INTC_ICDICFR32_TINT109_1_SHIFT          (27u)
+#define INTC_ICDICFR32_TINT110_0_SHIFT          (28u)
+#define INTC_ICDICFR32_TINT110_1_SHIFT          (29u)
+#define INTC_ICDICFR32_TINT111_0_SHIFT          (30u)
+#define INTC_ICDICFR32_TINT111_1_SHIFT          (31u)
+
+#define INTC_ICDICFR33_TINT112_0_SHIFT          (0u)
+#define INTC_ICDICFR33_TINT112_1_SHIFT          (1u)
+#define INTC_ICDICFR33_TINT113_0_SHIFT          (2u)
+#define INTC_ICDICFR33_TINT113_1_SHIFT          (3u)
+#define INTC_ICDICFR33_TINT114_0_SHIFT          (4u)
+#define INTC_ICDICFR33_TINT114_1_SHIFT          (5u)
+#define INTC_ICDICFR33_TINT115_0_SHIFT          (6u)
+#define INTC_ICDICFR33_TINT115_1_SHIFT          (7u)
+#define INTC_ICDICFR33_TINT116_0_SHIFT          (8u)
+#define INTC_ICDICFR33_TINT116_1_SHIFT          (9u)
+#define INTC_ICDICFR33_TINT117_0_SHIFT          (10u)
+#define INTC_ICDICFR33_TINT117_1_SHIFT          (11u)
+#define INTC_ICDICFR33_TINT118_0_SHIFT          (12u)
+#define INTC_ICDICFR33_TINT118_1_SHIFT          (13u)
+#define INTC_ICDICFR33_TINT119_0_SHIFT          (14u)
+#define INTC_ICDICFR33_TINT119_1_SHIFT          (15u)
+#define INTC_ICDICFR33_TINT120_0_SHIFT          (16u)
+#define INTC_ICDICFR33_TINT120_1_SHIFT          (17u)
+#define INTC_ICDICFR33_TINT121_0_SHIFT          (18u)
+#define INTC_ICDICFR33_TINT121_1_SHIFT          (19u)
+#define INTC_ICDICFR33_TINT122_0_SHIFT          (20u)
+#define INTC_ICDICFR33_TINT122_1_SHIFT          (21u)
+#define INTC_ICDICFR33_TINT123_0_SHIFT          (22u)
+#define INTC_ICDICFR33_TINT123_1_SHIFT          (23u)
+#define INTC_ICDICFR33_TINT124_0_SHIFT          (24u)
+#define INTC_ICDICFR33_TINT124_1_SHIFT          (25u)
+#define INTC_ICDICFR33_TINT125_0_SHIFT          (26u)
+#define INTC_ICDICFR33_TINT125_1_SHIFT          (27u)
+#define INTC_ICDICFR33_TINT126_0_SHIFT          (28u)
+#define INTC_ICDICFR33_TINT126_1_SHIFT          (29u)
+#define INTC_ICDICFR33_TINT127_0_SHIFT          (30u)
+#define INTC_ICDICFR33_TINT127_1_SHIFT          (31u)
+
+#define INTC_ICDICFR34_TINT128_0_SHIFT          (0u)
+#define INTC_ICDICFR34_TINT128_1_SHIFT          (1u)
+#define INTC_ICDICFR34_TINT129_0_SHIFT          (2u)
+#define INTC_ICDICFR34_TINT129_1_SHIFT          (3u)
+#define INTC_ICDICFR34_TINT130_0_SHIFT          (4u)
+#define INTC_ICDICFR34_TINT130_1_SHIFT          (5u)
+#define INTC_ICDICFR34_TINT131_0_SHIFT          (6u)
+#define INTC_ICDICFR34_TINT131_1_SHIFT          (7u)
+#define INTC_ICDICFR34_TINT132_0_SHIFT          (8u)
+#define INTC_ICDICFR34_TINT132_1_SHIFT          (9u)
+#define INTC_ICDICFR34_TINT133_0_SHIFT          (10u)
+#define INTC_ICDICFR34_TINT133_1_SHIFT          (11u)
+#define INTC_ICDICFR34_TINT134_0_SHIFT          (12u)
+#define INTC_ICDICFR34_TINT134_1_SHIFT          (13u)
+#define INTC_ICDICFR34_TINT135_0_SHIFT          (14u)
+#define INTC_ICDICFR34_TINT135_1_SHIFT          (15u)
+#define INTC_ICDICFR34_TINT136_0_SHIFT          (16u)
+#define INTC_ICDICFR34_TINT136_1_SHIFT          (17u)
+#define INTC_ICDICFR34_TINT137_0_SHIFT          (18u)
+#define INTC_ICDICFR34_TINT137_1_SHIFT          (19u)
+#define INTC_ICDICFR34_TINT138_0_SHIFT          (20u)
+#define INTC_ICDICFR34_TINT138_1_SHIFT          (21u)
+#define INTC_ICDICFR34_TINT139_0_SHIFT          (22u)
+#define INTC_ICDICFR34_TINT139_1_SHIFT          (23u)
+#define INTC_ICDICFR34_TINT140_0_SHIFT          (24u)
+#define INTC_ICDICFR34_TINT140_1_SHIFT          (25u)
+#define INTC_ICDICFR34_TINT141_0_SHIFT          (26u)
+#define INTC_ICDICFR34_TINT141_1_SHIFT          (27u)
+#define INTC_ICDICFR34_TINT142_0_SHIFT          (28u)
+#define INTC_ICDICFR34_TINT142_1_SHIFT          (29u)
+#define INTC_ICDICFR34_TINT143_0_SHIFT          (30u)
+#define INTC_ICDICFR34_TINT143_1_SHIFT          (31u)
+
+#define INTC_ICDICFR35_TINT144_0_SHIFT          (0u)
+#define INTC_ICDICFR35_TINT144_1_SHIFT          (1u)
+#define INTC_ICDICFR35_TINT145_0_SHIFT          (2u)
+#define INTC_ICDICFR35_TINT145_1_SHIFT          (3u)
+#define INTC_ICDICFR35_TINT146_0_SHIFT          (4u)
+#define INTC_ICDICFR35_TINT146_1_SHIFT          (5u)
+#define INTC_ICDICFR35_TINT147_0_SHIFT          (6u)
+#define INTC_ICDICFR35_TINT147_1_SHIFT          (7u)
+#define INTC_ICDICFR35_TINT148_0_SHIFT          (8u)
+#define INTC_ICDICFR35_TINT148_1_SHIFT          (9u)
+#define INTC_ICDICFR35_TINT149_0_SHIFT          (10u)
+#define INTC_ICDICFR35_TINT149_1_SHIFT          (11u)
+#define INTC_ICDICFR35_TINT150_0_SHIFT          (12u)
+#define INTC_ICDICFR35_TINT150_1_SHIFT          (13u)
+#define INTC_ICDICFR35_TINT151_0_SHIFT          (14u)
+#define INTC_ICDICFR35_TINT151_1_SHIFT          (15u)
+#define INTC_ICDICFR35_TINT152_0_SHIFT          (16u)
+#define INTC_ICDICFR35_TINT152_1_SHIFT          (17u)
+#define INTC_ICDICFR35_TINT153_0_SHIFT          (18u)
+#define INTC_ICDICFR35_TINT153_1_SHIFT          (19u)
+#define INTC_ICDICFR35_TINT154_0_SHIFT          (20u)
+#define INTC_ICDICFR35_TINT154_1_SHIFT          (21u)
+#define INTC_ICDICFR35_TINT155_0_SHIFT          (22u)
+#define INTC_ICDICFR35_TINT155_1_SHIFT          (23u)
+#define INTC_ICDICFR35_TINT156_0_SHIFT          (24u)
+#define INTC_ICDICFR35_TINT156_1_SHIFT          (25u)
+#define INTC_ICDICFR35_TINT157_0_SHIFT          (26u)
+#define INTC_ICDICFR35_TINT157_1_SHIFT          (27u)
+#define INTC_ICDICFR35_TINT158_0_SHIFT          (28u)
+#define INTC_ICDICFR35_TINT158_1_SHIFT          (29u)
+#define INTC_ICDICFR35_TINT159_0_SHIFT          (30u)
+#define INTC_ICDICFR35_TINT159_1_SHIFT          (31u)
+
+#define INTC_ICDICFR36_TINT160_0_SHIFT          (0u)
+#define INTC_ICDICFR36_TINT160_1_SHIFT          (1u)
+#define INTC_ICDICFR36_TINT161_0_SHIFT          (2u)
+#define INTC_ICDICFR36_TINT161_1_SHIFT          (3u)
+#define INTC_ICDICFR36_TINT162_0_SHIFT          (4u)
+#define INTC_ICDICFR36_TINT162_1_SHIFT          (5u)
+#define INTC_ICDICFR36_TINT163_0_SHIFT          (6u)
+#define INTC_ICDICFR36_TINT163_1_SHIFT          (7u)
+#define INTC_ICDICFR36_TINT164_0_SHIFT          (8u)
+#define INTC_ICDICFR36_TINT164_1_SHIFT          (9u)
+#define INTC_ICDICFR36_TINT165_0_SHIFT          (10u)
+#define INTC_ICDICFR36_TINT165_1_SHIFT          (11u)
+#define INTC_ICDICFR36_TINT166_0_SHIFT          (12u)
+#define INTC_ICDICFR36_TINT166_1_SHIFT          (13u)
+#define INTC_ICDICFR36_TINT167_0_SHIFT          (14u)
+#define INTC_ICDICFR36_TINT167_1_SHIFT          (15u)
+#define INTC_ICDICFR36_TINT168_0_SHIFT          (16u)
+#define INTC_ICDICFR36_TINT168_1_SHIFT          (17u)
+#define INTC_ICDICFR36_TINT169_0_SHIFT          (18u)
+#define INTC_ICDICFR36_TINT169_1_SHIFT          (19u)
+#define INTC_ICDICFR36_TINT170_0_SHIFT          (20u)
+#define INTC_ICDICFR36_TINT170_1_SHIFT          (21u)
+
+#define INTC_ICDSGIR_SGIINTID_SHIFT             (0u)
+#define INTC_ICDSGIR_SATT_SHIFT                 (15u)
+#define INTC_ICDSGIR_CPUTargetList_SHIFT        (16u)
+#define INTC_ICDSGIR_TargetListFilter_SHIFT     (24u)
+
+#define INTC_ICCICR_EnableS_SHIFT               (0u)
+#define INTC_ICCICR_EnableNS_SHIFT              (1u)
+#define INTC_ICCICR_AckCtl_SHIFT                (2u)
+#define INTC_ICCICR_FIQEn_SHIFT                 (3u)
+#define INTC_ICCICR_SBPR_SHIFT                  (4u)
+
+#define INTC_ICCPMR_Priority_SHIFT              (0u)
+
+#define INTC_ICCBPR_Binarypoint_SHIFT           (0u)
+
+#define INTC_ICCIAR_ACKINTID_SHIFT              (0u)
+#define INTC_ICCIAR_CPUID_SHIFT                 (10u)
+
+#define INTC_ICCEOIR_EOIINTID_SHIFT             (0u)
+#define INTC_ICCEOIR_CPUID_SHIFT                (10u)
+
+#define INTC_ICCRPR_Priority_SHIFT              (0u)
+
+#define INTC_ICCHPIR_PENDINTID_SHIFT            (0u)
+#define INTC_ICCHPIR_CPUID_SHIFT                (10u)
+
+#define INTC_ICCABPR_Binarypoint_SHIFT          (0u)
+
+#define INTC_ICCIIDR_Implementer_SHIFT          (0u)
+#define INTC_ICCIIDR_Revision_SHIFT             (12u)
+#define INTC_ICCIIDR_Architecture_version_SHIFT (16u)
+#define INTC_ICCIIDR_ProductID_SHIFT            (20u)
+
+#define INTC_ICR0_NMIF_SHIFT                    (1u)
+#define INTC_ICR0_NMIE_SHIFT                    (8u)
+#define INTC_ICR0_NMIL_SHIFT                    (15u)
+
+#define INTC_ICR1_IRQ00S_SHIFT                  (0u)
+#define INTC_ICR1_IRQ01S_SHIFT                  (1u)
+#define INTC_ICR1_IRQ10S_SHIFT                  (2u)
+#define INTC_ICR1_IRQ11S_SHIFT                  (3u)
+#define INTC_ICR1_IRQ20S_SHIFT                  (4u)
+#define INTC_ICR1_IRQ21S_SHIFT                  (5u)
+#define INTC_ICR1_IRQ30S_SHIFT                  (6u)
+#define INTC_ICR1_IRQ31S_SHIFT                  (7u)
+#define INTC_ICR1_IRQ40S_SHIFT                  (8u)
+#define INTC_ICR1_IRQ41S_SHIFT                  (9u)
+#define INTC_ICR1_IRQ50S_SHIFT                  (10u)
+#define INTC_ICR1_IRQ51S_SHIFT                  (11u)
+#define INTC_ICR1_IRQ60S_SHIFT                  (12u)
+#define INTC_ICR1_IRQ61S_SHIFT                  (13u)
+#define INTC_ICR1_IRQ70S_SHIFT                  (14u)
+#define INTC_ICR1_IRQ71S_SHIFT                  (15u)
+
+#define INTC_IRQRR_IRQ0F_SHIFT                  (0u)
+#define INTC_IRQRR_IRQ1F_SHIFT                  (1u)
+#define INTC_IRQRR_IRQ2F_SHIFT                  (2u)
+#define INTC_IRQRR_IRQ3F_SHIFT                  (3u)
+#define INTC_IRQRR_IRQ4F_SHIFT                  (4u)
+#define INTC_IRQRR_IRQ5F_SHIFT                  (5u)
+#define INTC_IRQRR_IRQ6F_SHIFT                  (6u)
+#define INTC_IRQRR_IRQ7F_SHIFT                  (7u)
+
+
+#endif /* INTC_IOBITMASK_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/mtu2_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,463 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : mtu2_iobitmask.h
+* $Rev: 1138 $
+* $Date:: 2014-08-08 11:03:56 +0900#$
+* Description : MTU2 register define header
+*******************************************************************************/
+#ifndef MTU2_IOBITMASK_H
+#define MTU2_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define MTU2_TCR_n_TPSC                         (0x07u)
+#define MTU2_TCR_n_CKEG                         (0x18u)
+#define MTU2_TCR_n_CCLR                         (0xE0u)
+
+#define MTU2_TMDR_n_MD                          (0x0Fu)
+
+#define MTU2_TIOR_2_IOA                         (0x0Fu)
+#define MTU2_TIOR_2_IOB                         (0xF0u)
+
+#define MTU2_TIER_n_TGIEA                       (0x01u)
+#define MTU2_TIER_n_TGIEB                       (0x02u)
+#define MTU2_TIER_n_TCIEV                       (0x10u)
+#define MTU2_TIER_2_TCIEU                       (0x20u)
+#define MTU2_TIER_n_TTGE                        (0x80u)
+
+#define MTU2_TSR_n_TGFA                         (0x01u)
+#define MTU2_TSR_n_TGFB                         (0x02u)
+#define MTU2_TSR_n_TCFV                         (0x10u)
+#define MTU2_TSR_2_TCFU                         (0x20u)
+#define MTU2_TSR_2_TCFD                         (0x80u)
+
+#define MTU2_TCNT_n_D                           (0xFFFFu)
+
+#define MTU2_TGRA_n_D                           (0xFFFFu)
+
+#define MTU2_TGRB_n_D                           (0xFFFFu)
+
+#define MTU2_TMDR_3_BFA                         (0x10u)
+#define MTU2_TMDR_3_BFB                         (0x20u)
+
+#define MTU2_TMDR_4_BFA                         (0x10u)
+#define MTU2_TMDR_4_BFB                         (0x20u)
+
+#define MTU2_TIORH_3_IOA                        (0x0Fu)
+#define MTU2_TIORH_3_IOB                        (0xF0u)
+
+#define MTU2_TIORL_3_IOC                        (0x0Fu)
+#define MTU2_TIORL_3_IOD                        (0xF0u)
+
+#define MTU2_TIORH_4_IOA                        (0x0Fu)
+#define MTU2_TIORH_4_IOB                        (0xF0u)
+
+#define MTU2_TIORL_4_IOC                        (0x0Fu)
+#define MTU2_TIORL_4_IOD                        (0xF0u)
+
+#define MTU2_TIER_3_TGIEC                       (0x04u)
+#define MTU2_TIER_3_TGIED                       (0x08u)
+
+#define MTU2_TIER_4_TGIEC                       (0x04u)
+#define MTU2_TIER_4_TGIED                       (0x08u)
+#define MTU2_TIER_4_TTGE2                       (0x40u)
+
+#define MTU2_TOER_OE3B                          (0x01u)
+#define MTU2_TOER_OE4A                          (0x02u)
+#define MTU2_TOER_OE4B                          (0x04u)
+#define MTU2_TOER_OE3D                          (0x08u)
+#define MTU2_TOER_OE4C                          (0x10u)
+#define MTU2_TOER_OE4D                          (0x20u)
+
+#define MTU2_TGCR_UF                            (0x01u)
+#define MTU2_TGCR_VF                            (0x02u)
+#define MTU2_TGCR_WF                            (0x04u)
+#define MTU2_TGCR_FB                            (0x08u)
+#define MTU2_TGCR_P                             (0x10u)
+#define MTU2_TGCR_N                             (0x20u)
+#define MTU2_TGCR_BDC                           (0x40u)
+
+#define MTU2_TOCR1_OLSP                         (0x01u)
+#define MTU2_TOCR1_OLSN                         (0x02u)
+#define MTU2_TOCR1_TOCS                         (0x04u)
+#define MTU2_TOCR1_TOCL                         (0x08u)
+#define MTU2_TOCR1_PSYE                         (0x40u)
+
+#define MTU2_TOCR2_OLS1P                        (0x01u)
+#define MTU2_TOCR2_OLS1N                        (0x02u)
+#define MTU2_TOCR2_OLS2P                        (0x04u)
+#define MTU2_TOCR2_OLS2N                        (0x08u)
+#define MTU2_TOCR2_OLS3P                        (0x10u)
+#define MTU2_TOCR2_OLS3N                        (0x20u)
+#define MTU2_TOCR2_BF                           (0xC0u)
+
+#define MTU2_TCDR_D                             (0xFFFFu)
+
+#define MTU2_TDDR_D                             (0xFFFFu)
+
+#define MTU2_TCNTS_D                            (0xFFFFu)
+
+#define MTU2_TCBR_D                             (0xFFFFu)
+
+#define MTU2_TGRC_3_D                           (0xFFFFu)
+
+#define MTU2_TGRD_3_D                           (0xFFFFu)
+
+#define MTU2_TGRC_4_D                           (0xFFFFu)
+
+#define MTU2_TGRD_4_D                           (0xFFFFu)
+
+#define MTU2_TSR_3_TGFC                         (0x04u)
+#define MTU2_TSR_3_TGFD                         (0x08u)
+#define MTU2_TSR_3_TCFD                         (0x80u)
+
+#define MTU2_TSR_4_TGFC                         (0x04u)
+#define MTU2_TSR_4_TGFD                         (0x08u)
+#define MTU2_TSR_4_TCFD                         (0x80u)
+
+#define MTU2_TITCR_4VCOR                        (0x07u)
+#define MTU2_TITCR_T4VEN                        (0x08u)
+#define MTU2_TITCR_3ACOR                        (0x70u)
+#define MTU2_TITCR_T3AEN                        (0x80u)
+
+#define MTU2_TITCNT_4VCNT                       (0x07u)
+#define MTU2_TITCNT_3ACNT                       (0x70u)
+
+#define MTU2_TBTER_BTE                          (0x03u)
+
+#define MTU2_TDER_TDER                          (0x01u)
+
+#define MTU2_TOLBR_OLS1P                        (0x01u)
+#define MTU2_TOLBR_OLS1N                        (0x02u)
+#define MTU2_TOLBR_OLS2P                        (0x04u)
+#define MTU2_TOLBR_OLS2N                        (0x08u)
+#define MTU2_TOLBR_OLS3P                        (0x10u)
+#define MTU2_TOLBR_OLS3N                        (0x20u)
+
+#define MTU2_TBTM_3_TTSA                        (0x01u)
+#define MTU2_TBTM_3_TTSB                        (0x02u)
+
+#define MTU2_TBTM_4_TTSA                        (0x01u)
+#define MTU2_TBTM_4_TTSB                        (0x02u)
+
+#define MTU2_TADCR_ITB4VE                       (0x0001u)
+#define MTU2_TADCR_ITB3AE                       (0x0002u)
+#define MTU2_TADCR_ITA4VE                       (0x0004u)
+#define MTU2_TADCR_ITA3AE                       (0x0008u)
+#define MTU2_TADCR_DT4BE                        (0x0010u)
+#define MTU2_TADCR_UT4BE                        (0x0020u)
+#define MTU2_TADCR_DT4AE                        (0x0040u)
+#define MTU2_TADCR_UT4AE                        (0x0080u)
+#define MTU2_TADCR_BF                           (0xC000u)
+
+#define MTU2_TADCORA_4_D                        (0xFFFFu)
+
+#define MTU2_TADCORB_4_D                        (0xFFFFu)
+
+#define MTU2_TADCOBRA_4_D                       (0xFFFFu)
+
+#define MTU2_TADCOBRB_4_D                       (0xFFFFu)
+
+#define MTU2_TWCR_WRE                           (0x01u)
+#define MTU2_TWCR_CCE                           (0x80u)
+
+#define MTU2_TSTR_CST0                          (0x01u)
+#define MTU2_TSTR_CST1                          (0x02u)
+#define MTU2_TSTR_CST2                          (0x04u)
+#define MTU2_TSTR_CST3                          (0x40u)
+#define MTU2_TSTR_CST4                          (0x80u)
+
+#define MTU2_TSYR_SYNC0                         (0x01u)
+#define MTU2_TSYR_SYNC1                         (0x02u)
+#define MTU2_TSYR_SYNC2                         (0x04u)
+#define MTU2_TSYR_SYNC3                         (0x40u)
+#define MTU2_TSYR_SYNC4                         (0x80u)
+
+#define MTU2_TRWER_RWE                          (0x01u)
+
+#define MTU2_TMDR_0_BFA                         (0x10u)
+#define MTU2_TMDR_0_BFB                         (0x20u)
+#define MTU2_TMDR_0_BFE                         (0x40u)
+
+#define MTU2_TIORH_0_IOA                        (0x0Fu)
+#define MTU2_TIORH_0_IOB                        (0xF0u)
+
+#define MTU2_TIORL_0_IOC                        (0x0Fu)
+#define MTU2_TIORL_0_IOD                        (0xF0u)
+
+#define MTU2_TIER_0_TGIEC                       (0x04u)
+#define MTU2_TIER_0_TGIED                       (0x08u)
+
+#define MTU2_TSR_0_TGFC                         (0x04u)
+#define MTU2_TSR_0_TGFD                         (0x08u)
+
+#define MTU2_TGRC_0_D                           (0xFFFFu)
+
+#define MTU2_TGRD_0_D                           (0xFFFFu)
+
+#define MTU2_TGRE_0_D                           (0xFFFFu)
+
+#define MTU2_TGRF_0_D                           (0xFFFFu)
+
+#define MTU2_TIER2_0_TGIEE                      (0x01u)
+#define MTU2_TIER2_0_TGIEF                      (0x02u)
+
+#define MTU2_TSR2_0_TGFE                        (0x01u)
+#define MTU2_TSR2_0_TGFF                        (0x02u)
+
+#define MTU2_TBTM_0_TTSA                        (0x01u)
+#define MTU2_TBTM_0_TTSB                        (0x02u)
+#define MTU2_TBTM_0_TTSE                        (0x04u)
+
+#define MTU2_TIOR_1_IOA                         (0x0Fu)
+#define MTU2_TIOR_1_IOB                         (0xF0u)
+
+#define MTU2_TIER_1_TCIEU                       (0x20u)
+
+#define MTU2_TSR_1_TCFU                         (0x20u)
+#define MTU2_TSR_1_TCFD                         (0x80u)
+
+#define MTU2_TICCR_I1AE                         (0x01u)
+#define MTU2_TICCR_I1BE                         (0x02u)
+#define MTU2_TICCR_I2AE                         (0x04u)
+#define MTU2_TICCR_I2BE                         (0x08u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define MTU2_TCR_n_TPSC_SHIFT                   (0u)
+#define MTU2_TCR_n_CKEG_SHIFT                   (3u)
+#define MTU2_TCR_n_CCLR_SHIFT                   (5u)
+
+#define MTU2_TMDR_n_MD_SHIFT                    (0u)
+
+#define MTU2_TIOR_2_IOA_SHIFT                   (0u)
+#define MTU2_TIOR_2_IOB_SHIFT                   (4u)
+
+#define MTU2_TIER_n_TGIEA_SHIFT                 (0u)
+#define MTU2_TIER_n_TGIEB_SHIFT                 (1u)
+#define MTU2_TIER_n_TCIEV_SHIFT                 (4u)
+#define MTU2_TIER_2_TCIEU_SHIFT                 (5u)
+#define MTU2_TIER_n_TTGE_SHIFT                  (7u)
+
+#define MTU2_TSR_n_TGFA_SHIFT                   (0u)
+#define MTU2_TSR_n_TGFB_SHIFT                   (1u)
+#define MTU2_TSR_n_TCFV_SHIFT                   (4u)
+#define MTU2_TSR_2_TCFU_SHIFT                   (5u)
+#define MTU2_TSR_2_TCFD_SHIFT                   (7u)
+
+#define MTU2_TCNT_n_D_SHIFT                     (0u)
+
+#define MTU2_TGRA_n_D_SHIFT                     (0u)
+
+#define MTU2_TGRB_n_D_SHIFT                     (0u)
+
+#define MTU2_TMDR_3_BFA_SHIFT                   (4u)
+#define MTU2_TMDR_3_BFB_SHIFT                   (5u)
+
+#define MTU2_TMDR_4_BFA_SHIFT                   (4u)
+#define MTU2_TMDR_4_BFB_SHIFT                   (5u)
+
+#define MTU2_TIORH_3_IOA_SHIFT                  (0u)
+#define MTU2_TIORH_3_IOB_SHIFT                  (4u)
+
+#define MTU2_TIORL_3_IOC_SHIFT                  (0u)
+#define MTU2_TIORL_3_IOD_SHIFT                  (4u)
+
+#define MTU2_TIORH_4_IOA_SHIFT                  (0u)
+#define MTU2_TIORH_4_IOB_SHIFT                  (4u)
+
+#define MTU2_TIORL_4_IOC_SHIFT                  (0u)
+#define MTU2_TIORL_4_IOD_SHIFT                  (4u)
+
+#define MTU2_TIER_3_TGIEC_SHIFT                 (2u)
+#define MTU2_TIER_3_TGIED_SHIFT                 (3u)
+
+#define MTU2_TIER_4_TGIEC_SHIFT                 (2u)
+#define MTU2_TIER_4_TGIED_SHIFT                 (3u)
+#define MTU2_TIER_4_TTGE2_SHIFT                 (6u)
+
+#define MTU2_TOER_OE3B_SHIFT                    (0u)
+#define MTU2_TOER_OE4A_SHIFT                    (1u)
+#define MTU2_TOER_OE4B_SHIFT                    (2u)
+#define MTU2_TOER_OE3D_SHIFT                    (3u)
+#define MTU2_TOER_OE4C_SHIFT                    (4u)
+#define MTU2_TOER_OE4D_SHIFT                    (5u)
+
+#define MTU2_TGCR_UF_SHIFT                      (0u)
+#define MTU2_TGCR_VF_SHIFT                      (1u)
+#define MTU2_TGCR_WF_SHIFT                      (2u)
+#define MTU2_TGCR_FB_SHIFT                      (3u)
+#define MTU2_TGCR_P_SHIFT                       (4u)
+#define MTU2_TGCR_N_SHIFT                       (5u)
+#define MTU2_TGCR_BDC_SHIFT                     (6u)
+
+#define MTU2_TOCR1_OLSP_SHIFT                   (0u)
+#define MTU2_TOCR1_OLSN_SHIFT                   (1u)
+#define MTU2_TOCR1_TOCS_SHIFT                   (2u)
+#define MTU2_TOCR1_TOCL_SHIFT                   (3u)
+#define MTU2_TOCR1_PSYE_SHIFT                   (6u)
+
+#define MTU2_TOCR2_OLS1P_SHIFT                  (0u)
+#define MTU2_TOCR2_OLS1N_SHIFT                  (1u)
+#define MTU2_TOCR2_OLS2P_SHIFT                  (2u)
+#define MTU2_TOCR2_OLS2N_SHIFT                  (3u)
+#define MTU2_TOCR2_OLS3P_SHIFT                  (4u)
+#define MTU2_TOCR2_OLS3N_SHIFT                  (5u)
+#define MTU2_TOCR2_BF_SHIFT                     (6u)
+
+#define MTU2_TCDR_D_SHIFT                       (0u)
+
+#define MTU2_TDDR_D_SHIFT                       (0u)
+
+#define MTU2_TCNTS_D_SHIFT                      (0u)
+
+#define MTU2_TCBR_D_SHIFT                       (0u)
+
+#define MTU2_TGRC_3_D_SHIFT                     (0u)
+
+#define MTU2_TGRD_3_D_SHIFT                     (0u)
+
+#define MTU2_TGRC_4_D_SHIFT                     (0u)
+
+#define MTU2_TGRD_4_D_SHIFT                     (0u)
+
+#define MTU2_TSR_3_TGFC_SHIFT                   (2u)
+#define MTU2_TSR_3_TGFD_SHIFT                   (3u)
+#define MTU2_TSR_3_TCFD_SHIFT                   (7u)
+
+#define MTU2_TSR_4_TGFC_SHIFT                   (2u)
+#define MTU2_TSR_4_TGFD_SHIFT                   (3u)
+#define MTU2_TSR_4_TCFD_SHIFT                   (7u)
+
+#define MTU2_TITCR_4VCOR_SHIFT                  (0u)
+#define MTU2_TITCR_T4VEN_SHIFT                  (3u)
+#define MTU2_TITCR_3ACOR_SHIFT                  (4u)
+#define MTU2_TITCR_T3AEN_SHIFT                  (7u)
+
+#define MTU2_TITCNT_4VCNT_SHIFT                 (0u)
+#define MTU2_TITCNT_3ACNT_SHIFT                 (4u)
+
+#define MTU2_TBTER_BTE_SHIFT                    (0u)
+
+#define MTU2_TDER_TDER_SHIFT                    (0u)
+
+#define MTU2_TOLBR_OLS1P_SHIFT                  (0u)
+#define MTU2_TOLBR_OLS1N_SHIFT                  (1u)
+#define MTU2_TOLBR_OLS2P_SHIFT                  (2u)
+#define MTU2_TOLBR_OLS2N_SHIFT                  (3u)
+#define MTU2_TOLBR_OLS3P_SHIFT                  (4u)
+#define MTU2_TOLBR_OLS3N_SHIFT                  (5u)
+
+#define MTU2_TBTM_3_TTSA_SHIFT                  (0u)
+#define MTU2_TBTM_3_TTSB_SHIFT                  (1u)
+
+#define MTU2_TBTM_4_TTSA_SHIFT                  (0u)
+#define MTU2_TBTM_4_TTSB_SHIFT                  (1u)
+
+#define MTU2_TADCR_ITB4VE_SHIFT                 (0u)
+#define MTU2_TADCR_ITB3AE_SHIFT                 (1u)
+#define MTU2_TADCR_ITA4VE_SHIFT                 (2u)
+#define MTU2_TADCR_ITA3AE_SHIFT                 (3u)
+#define MTU2_TADCR_DT4BE_SHIFT                  (4u)
+#define MTU2_TADCR_UT4BE_SHIFT                  (5u)
+#define MTU2_TADCR_DT4AE_SHIFT                  (6u)
+#define MTU2_TADCR_UT4AE_SHIFT                  (7u)
+#define MTU2_TADCR_BF_SHIFT                     (14u)
+
+#define MTU2_TADCORA_4_D_SHIFT                  (0u)
+
+#define MTU2_TADCORB_4_D_SHIFT                  (0u)
+
+#define MTU2_TADCOBRA_4_D_SHIFT                 (0u)
+
+#define MTU2_TADCOBRB_4_D_SHIFT                 (0u)
+
+#define MTU2_TWCR_WRE_SHIFT                     (0u)
+#define MTU2_TWCR_CCE_SHIFT                     (7u)
+
+#define MTU2_TSTR_CST0_SHIFT                    (0u)
+#define MTU2_TSTR_CST1_SHIFT                    (1u)
+#define MTU2_TSTR_CST2_SHIFT                    (2u)
+#define MTU2_TSTR_CST3_SHIFT                    (6u)
+#define MTU2_TSTR_CST4_SHIFT                    (7u)
+
+#define MTU2_TSYR_SYNC0_SHIFT                   (0u)
+#define MTU2_TSYR_SYNC1_SHIFT                   (1u)
+#define MTU2_TSYR_SYNC2_SHIFT                   (2u)
+#define MTU2_TSYR_SYNC3_SHIFT                   (6u)
+#define MTU2_TSYR_SYNC4_SHIFT                   (7u)
+
+#define MTU2_TRWER_RWE_SHIFT                    (0u)
+
+#define MTU2_TMDR_0_BFA_SHIFT                   (4u)
+#define MTU2_TMDR_0_BFB_SHIFT                   (5u)
+#define MTU2_TMDR_0_BFE_SHIFT                   (6u)
+
+#define MTU2_TIORH_0_IOA_SHIFT                  (0u)
+#define MTU2_TIORH_0_IOB_SHIFT                  (4u)
+
+#define MTU2_TIORL_0_IOC_SHIFT                  (0u)
+#define MTU2_TIORL_0_IOD_SHIFT                  (4u)
+
+#define MTU2_TIER_0_TGIEC_SHIFT                 (2u)
+#define MTU2_TIER_0_TGIED_SHIFT                 (3u)
+
+#define MTU2_TSR_0_TGFC_SHIFT                   (2u)
+#define MTU2_TSR_0_TGFD_SHIFT                   (3u)
+
+#define MTU2_TGRC_0_D_SHIFT                     (0u)
+
+#define MTU2_TGRD_0_D_SHIFT                     (0u)
+
+#define MTU2_TGRE_0_D_SHIFT                     (0u)
+
+#define MTU2_TGRF_0_D_SHIFT                     (0u)
+
+#define MTU2_TIER2_0_TGIEE_SHIFT                (0u)
+#define MTU2_TIER2_0_TGIEF_SHIFT                (1u)
+
+#define MTU2_TSR2_0_TGFE_SHIFT                  (0u)
+#define MTU2_TSR2_0_TGFF_SHIFT                  (1u)
+
+#define MTU2_TBTM_0_TTSA_SHIFT                  (0u)
+#define MTU2_TBTM_0_TTSB_SHIFT                  (1u)
+#define MTU2_TBTM_0_TTSE_SHIFT                  (2u)
+
+#define MTU2_TIOR_1_IOA_SHIFT                   (0u)
+#define MTU2_TIOR_1_IOB_SHIFT                   (4u)
+
+#define MTU2_TIER_1_TCIEU_SHIFT                 (5u)
+
+#define MTU2_TSR_1_TCFU_SHIFT                   (5u)
+#define MTU2_TSR_1_TCFD_SHIFT                   (7u)
+
+#define MTU2_TICCR_I1AE_SHIFT                   (0u)
+#define MTU2_TICCR_I1BE_SHIFT                   (1u)
+#define MTU2_TICCR_I2AE_SHIFT                   (2u)
+#define MTU2_TICCR_I2BE_SHIFT                   (3u)
+
+
+#endif /* MTU2_IOBITMASK_H */
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/ostm_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,124 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : ostm_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : OSTM register define header
+*******************************************************************************/
+#ifndef OSTM_IOBITMASK_H
+#define OSTM_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- OSTM0 ---- */
+#define OSTM0_OSTMnCMP_OSTMnCMP                 (0xFFFFFFFFuL)
+
+#define OSTM0_OSTMnCNT_OSTMnCNT                 (0xFFFFFFFFuL)
+
+#define OSTM0_OSTMnTE_OSTMnTE                   (0x01u)
+
+#define OSTM0_OSTMnTS_OSTMnTS                   (0x01u)
+
+#define OSTM0_OSTMnTT_OSTMnTT                   (0x01u)
+
+#define OSTM0_OSTMnCTL_MD0                      (0x00000001uL)
+#define OSTM0_OSTMnCTL_MD1                      (0x00000002uL)
+
+/* ---- OSTM1 ---- */
+#define OSTM1_OSTMnCMP_OSTMnCMP                 (0xFFFFFFFFuL)
+
+#define OSTM1_OSTMnCNT_OSTMnCNT                 (0xFFFFFFFFuL)
+
+#define OSTM1_OSTMnTE_OSTMnTE                   (0x01u)
+
+#define OSTM1_OSTMnTS_OSTMnTS                   (0x01u)
+
+#define OSTM1_OSTMnTT_OSTMnTT                   (0x01u)
+
+#define OSTM1_OSTMnCTL_MD0                      (0x00000001uL)
+#define OSTM1_OSTMnCTL_MD1                      (0x00000002uL)
+
+/* ---- OSTMn ---- */
+#define OSTMn_OSTMnCMP_OSTMnCMP                 (0xFFFFFFFFuL)
+
+#define OSTMn_OSTMnCNT_OSTMnCNT                 (0xFFFFFFFFuL)
+
+#define OSTMn_OSTMnTE_OSTMnTE                   (0x01u)
+
+#define OSTMn_OSTMnTS_OSTMnTS                   (0x01u)
+
+#define OSTMn_OSTMnTT_OSTMnTT                   (0x01u)
+
+#define OSTMn_OSTMnCTL_MD0                      (0x00000001uL)
+#define OSTMn_OSTMnCTL_MD1                      (0x00000002uL)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- OSTM0 ---- */
+#define OSTM0_OSTMnCMP_OSTMnCMP_SHIFT           (0u)
+
+#define OSTM0_OSTMnCNT_OSTMnCNT_SHIFT           (0u)
+
+#define OSTM0_OSTMnTE_OSTMnTE_SHIFT             (0u)
+
+#define OSTM0_OSTMnTS_OSTMnTS_SHIFT             (0u)
+
+#define OSTM0_OSTMnTT_OSTMnTT_SHIFT             (0u)
+
+#define OSTM0_OSTMnCTL_MD0_SHIFT                (0u)
+#define OSTM0_OSTMnCTL_MD1_SHIFT                (1u)
+
+/* ---- OSTM1 ---- */
+#define OSTM1_OSTMnCMP_OSTMnCMP_SHIFT           (0u)
+
+#define OSTM1_OSTMnCNT_OSTMnCNT_SHIFT           (0u)
+
+#define OSTM1_OSTMnTE_OSTMnTE_SHIFT             (0u)
+
+#define OSTM1_OSTMnTS_OSTMnTS_SHIFT             (0u)
+
+#define OSTM1_OSTMnTT_OSTMnTT_SHIFT             (0u)
+
+#define OSTM1_OSTMnCTL_MD0_SHIFT                (0u)
+#define OSTM1_OSTMnCTL_MD1_SHIFT                (1u)
+
+/* ---- OSTMn ---- */
+#define OSTMn_OSTMnCMP_OSTMnCMP_SHIFT           (0u)
+
+#define OSTMn_OSTMnCNT_OSTMnCNT_SHIFT           (0u)
+
+#define OSTMn_OSTMnTE_OSTMnTE_SHIFT             (0u)
+
+#define OSTMn_OSTMnTS_OSTMnTS_SHIFT             (0u)
+
+#define OSTMn_OSTMnTT_OSTMnTT_SHIFT             (0u)
+
+#define OSTMn_OSTMnCTL_MD0_SHIFT                (0u)
+#define OSTMn_OSTMnCTL_MD1_SHIFT                (1u)
+
+
+#endif /* OSTM_IOBITMASK_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/riic_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,232 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : riic_iobitmask.h
+* $Rev: 1114 $
+* $Date:: 2014-07-09 14:56:39 +0900#$
+* Description : RIIC register define header
+*******************************************************************************/
+#ifndef RIIC_IOBITMASK_H
+#define RIIC_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define RIICn_RIICnCR1_SDAI                     (0x01u)
+#define RIICn_RIICnCR1_SCLI                     (0x02u)
+#define RIICn_RIICnCR1_SDAO                     (0x04u)
+#define RIICn_RIICnCR1_SCLO                     (0x08u)
+#define RIICn_RIICnCR1_SOWP                     (0x10u)
+#define RIICn_RIICnCR1_CLO                      (0x20u)
+#define RIICn_RIICnCR1_IICRST                   (0x40u)
+#define RIICn_RIICnCR1_ICE                      (0x80u)
+
+#define RIICn_RIICnCR2_ST                       (0x02u)
+#define RIICn_RIICnCR2_RS                       (0x04u)
+#define RIICn_RIICnCR2_SP                       (0x08u)
+#define RIICn_RIICnCR2_TRS                      (0x20u)
+#define RIICn_RIICnCR2_MST                      (0x40u)
+#define RIICn_RIICnCR2_BBSY                     (0x80u)
+
+#define RIICn_RIICnMR1_BC                       (0x07u)
+#define RIICn_RIICnMR1_BCWP                     (0x08u)
+#define RIICn_RIICnMR1_CKS                      (0x70u)
+#define RIICn_RIICnMR1_MTWP                     (0x80u)
+
+#define RIICn_RIICnMR2_TMOS                     (0x01u)
+#define RIICn_RIICnMR2_TMOL                     (0x02u)
+#define RIICn_RIICnMR2_TMOH                     (0x04u)
+#define RIICn_RIICnMR2_SDDL                     (0x70u)
+#define RIICn_RIICnMR2_DLCS                     (0x80u)
+
+#define RIICn_RIICnMR3_NF                       (0x03u)
+#define RIICn_RIICnMR3_ACKBR                    (0x04u)
+#define RIICn_RIICnMR3_ACKBT                    (0x08u)
+#define RIICn_RIICnMR3_ACKWP                    (0x10u)
+#define RIICn_RIICnMR3_RDRFS                    (0x20u)
+#define RIICn_RIICnMR3_WAIT                     (0x40u)
+#define RIICn_RIICnMR3_SMBS                     (0x80u)
+
+#define RIICn_RIICnFER_TMOE                     (0x01u)
+#define RIICn_RIICnFER_MALE                     (0x02u)
+#define RIICn_RIICnFER_NALE                     (0x04u)
+#define RIICn_RIICnFER_SALE                     (0x08u)
+#define RIICn_RIICnFER_NACKE                    (0x10u)
+#define RIICn_RIICnFER_NFE                      (0x20u)
+#define RIICn_RIICnFER_SCLE                     (0x40u)
+#define RIICn_RIICnFER_FMPE                     (0x80u)
+
+#define RIICn_RIICnSER_SAR0E                    (0x01u)
+#define RIICn_RIICnSER_SAR1E                    (0x02u)
+#define RIICn_RIICnSER_SAR2E                    (0x04u)
+#define RIICn_RIICnSER_GCAE                     (0x08u)
+#define RIICn_RIICnSER_DIDE                     (0x20u)
+#define RIICn_RIICnSER_HOAE                     (0x80u)
+
+#define RIICn_RIICnIER_TMOIE                    (0x01u)
+#define RIICn_RIICnIER_ALIE                     (0x02u)
+#define RIICn_RIICnIER_STIE                     (0x04u)
+#define RIICn_RIICnIER_SPIE                     (0x08u)
+#define RIICn_RIICnIER_NAKIE                    (0x10u)
+#define RIICn_RIICnIER_RIE                      (0x20u)
+#define RIICn_RIICnIER_TEIE                     (0x40u)
+#define RIICn_RIICnIER_TIE                      (0x80u)
+
+#define RIICn_RIICnSR1_AAS0                     (0x01u)
+#define RIICn_RIICnSR1_AAS1                     (0x02u)
+#define RIICn_RIICnSR1_AAS2                     (0x04u)
+#define RIICn_RIICnSR1_GCA                      (0x08u)
+#define RIICn_RIICnSR1_DID                      (0x20u)
+#define RIICn_RIICnSR1_HOA                      (0x80u)
+
+#define RIICn_RIICnSR2_TMOF                     (0x01u)
+#define RIICn_RIICnSR2_AL                       (0x02u)
+#define RIICn_RIICnSR2_START                    (0x04u)
+#define RIICn_RIICnSR2_STOP                     (0x08u)
+#define RIICn_RIICnSR2_NACKF                    (0x10u)
+#define RIICn_RIICnSR2_RDRF                     (0x20u)
+#define RIICn_RIICnSR2_TEND                     (0x40u)
+#define RIICn_RIICnSR2_TDRE                     (0x80u)
+
+#define RIICn_RIICnSAR0_SVA0                    (0x0001u)
+#define RIICn_RIICnSAR0_SVA                     (0x03FEu)
+#define RIICn_RIICnSAR0_FSy                     (0x8000u)
+
+#define RIICn_RIICnSAR1_SVA0                    (0x0001u)
+#define RIICn_RIICnSAR1_SVA                     (0x03FEu)
+#define RIICn_RIICnSAR1_FSy                     (0x8000u)
+
+#define RIICn_RIICnSAR2_SVA0                    (0x0001u)
+#define RIICn_RIICnSAR2_SVA                     (0x03FEu)
+#define RIICn_RIICnSAR2_FSy                     (0x8000u)
+
+#define RIICn_RIICnBRL_BRL                      (0x1Fu)
+
+#define RIICn_RIICnBRH_BRH                      (0x1Fu)
+
+#define RIICn_RIICnDRT_DRT                      (0xFFu)
+
+#define RIICn_RIICnDRR_DRR                      (0xFFu)
+
+
+/* ==== Shift values for IO registers ==== */
+#define RIICn_RIICnCR1_SDAI_SHIFT               (0u)
+#define RIICn_RIICnCR1_SCLI_SHIFT               (1u)
+#define RIICn_RIICnCR1_SDAO_SHIFT               (2u)
+#define RIICn_RIICnCR1_SCLO_SHIFT               (3u)
+#define RIICn_RIICnCR1_SOWP_SHIFT               (4u)
+#define RIICn_RIICnCR1_CLO_SHIFT                (5u)
+#define RIICn_RIICnCR1_IICRST_SHIFT             (6u)
+#define RIICn_RIICnCR1_ICE_SHIFT                (7u)
+
+#define RIICn_RIICnCR2_ST_SHIFT                 (1u)
+#define RIICn_RIICnCR2_RS_SHIFT                 (2u)
+#define RIICn_RIICnCR2_SP_SHIFT                 (3u)
+#define RIICn_RIICnCR2_TRS_SHIFT                (5u)
+#define RIICn_RIICnCR2_MST_SHIFT                (6u)
+#define RIICn_RIICnCR2_BBSY_SHIFT               (7u)
+
+#define RIICn_RIICnMR1_BC_SHIFT                 (0u)
+#define RIICn_RIICnMR1_BCWP_SHIFT               (3u)
+#define RIICn_RIICnMR1_CKS_SHIFT                (4u)
+#define RIICn_RIICnMR1_MTWP_SHIFT               (7u)
+
+#define RIICn_RIICnMR2_TMOS_SHIFT               (0u)
+#define RIICn_RIICnMR2_TMOL_SHIFT               (1u)
+#define RIICn_RIICnMR2_TMOH_SHIFT               (2u)
+#define RIICn_RIICnMR2_SDDL_SHIFT               (4u)
+#define RIICn_RIICnMR2_DLCS_SHIFT               (7u)
+
+#define RIICn_RIICnMR3_NF_SHIFT                 (0u)
+#define RIICn_RIICnMR3_ACKBR_SHIFT              (2u)
+#define RIICn_RIICnMR3_ACKBT_SHIFT              (3u)
+#define RIICn_RIICnMR3_ACKWP_SHIFT              (4u)
+#define RIICn_RIICnMR3_RDRFS_SHIFT              (5u)
+#define RIICn_RIICnMR3_WAIT_SHIFT               (6u)
+#define RIICn_RIICnMR3_SMBS_SHIFT               (7u)
+
+#define RIICn_RIICnFER_TMOE_SHIFT               (0u)
+#define RIICn_RIICnFER_MALE_SHIFT               (1u)
+#define RIICn_RIICnFER_NALE_SHIFT               (2u)
+#define RIICn_RIICnFER_SALE_SHIFT               (3u)
+#define RIICn_RIICnFER_NACKE_SHIFT              (4u)
+#define RIICn_RIICnFER_NFE_SHIFT                (5u)
+#define RIICn_RIICnFER_SCLE_SHIFT               (6u)
+#define RIICn_RIICnFER_FMPE_SHIFT               (7u)
+
+#define RIICn_RIICnSER_SAR0E_SHIFT              (0u)
+#define RIICn_RIICnSER_SAR1E_SHIFT              (1u)
+#define RIICn_RIICnSER_SAR2E_SHIFT              (2u)
+#define RIICn_RIICnSER_GCAE_SHIFT               (3u)
+#define RIICn_RIICnSER_DIDE_SHIFT               (5u)
+#define RIICn_RIICnSER_HOAE_SHIFT               (7u)
+
+#define RIICn_RIICnIER_TMOIE_SHIFT              (0u)
+#define RIICn_RIICnIER_ALIE_SHIFT               (1u)
+#define RIICn_RIICnIER_STIE_SHIFT               (2u)
+#define RIICn_RIICnIER_SPIE_SHIFT               (3u)
+#define RIICn_RIICnIER_NAKIE_SHIFT              (4u)
+#define RIICn_RIICnIER_RIE_SHIFT                (5u)
+#define RIICn_RIICnIER_TEIE_SHIFT               (6u)
+#define RIICn_RIICnIER_TIE_SHIFT                (7u)
+
+#define RIICn_RIICnSR1_AAS0_SHIFT               (0u)
+#define RIICn_RIICnSR1_AAS1_SHIFT               (1u)
+#define RIICn_RIICnSR1_AAS2_SHIFT               (2u)
+#define RIICn_RIICnSR1_GCA_SHIFT                (3u)
+#define RIICn_RIICnSR1_DID_SHIFT                (5u)
+#define RIICn_RIICnSR1_HOA_SHIFT                (7u)
+
+#define RIICn_RIICnSR2_TMOF_SHIFT               (0u)
+#define RIICn_RIICnSR2_AL_SHIFT                 (1u)
+#define RIICn_RIICnSR2_START_SHIFT              (2u)
+#define RIICn_RIICnSR2_STOP_SHIFT               (3u)
+#define RIICn_RIICnSR2_NACKF_SHIFT              (4u)
+#define RIICn_RIICnSR2_RDRF_SHIFT               (5u)
+#define RIICn_RIICnSR2_TEND_SHIFT               (6u)
+#define RIICn_RIICnSR2_TDRE_SHIFT               (7u)
+
+#define RIICn_RIICnSAR0_SVA0_SHIFT              (0u)
+#define RIICn_RIICnSAR0_SVA_SHIFT               (1u)
+#define RIICn_RIICnSAR0_FSy_SHIFT               (15u)
+
+#define RIICn_RIICnSAR1_SVA0_SHIFT              (0u)
+#define RIICn_RIICnSAR1_SVA_SHIFT               (1u)
+#define RIICn_RIICnSAR1_FSy_SHIFT               (15u)
+
+#define RIICn_RIICnSAR2_SVA0_SHIFT              (0u)
+#define RIICn_RIICnSAR2_SVA_SHIFT               (1u)
+#define RIICn_RIICnSAR2_FSy_SHIFT               (15u)
+
+#define RIICn_RIICnBRL_BRL_SHIFT                (0u)
+
+#define RIICn_RIICnBRH_BRH_SHIFT                (0u)
+
+#define RIICn_RIICnDRT_DRT_SHIFT                (0u)
+
+#define RIICn_RIICnDRR_DRR_SHIFT                (0u)
+
+
+#endif /* RIIC_IOBITMASK_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/rspi_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,216 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : rspi_iobitmask.h
+* $Rev: 1114 $
+* $Date:: 2014-07-09 14:56:39 +0900#$
+* Description : Renesas Serial Peripheral Interface register define header
+*******************************************************************************/
+#ifndef RSPI_IOBITMASK_H
+#define RSPI_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+#define RSPIn_SPCR_MODFEN                   (0x04u)
+#define RSPIn_SPCR_MSTR                     (0x08u)
+#define RSPIn_SPCR_SPEIE                    (0x10u)
+#define RSPIn_SPCR_SPTIE                    (0x20u)
+#define RSPIn_SPCR_SPE                      (0x40u)
+#define RSPIn_SPCR_SPRIE                    (0x80u)
+
+#define RSPIn_SSLP_SSL0P                    (0x01u)
+
+#define RSPIn_SPPCR_SPLP                    (0x01u)
+#define RSPIn_SPPCR_MOIFV                   (0x10u)
+#define RSPIn_SPPCR_MOIFE                   (0x20u)
+
+#define RSPIn_SPSR_OVRF                     (0x01u)
+#define RSPIn_SPSR_MODF                     (0x04u)
+#define RSPIn_SPSR_SPTEF                    (0x20u)
+#define RSPIn_SPSR_TEND                     (0x40u)
+#define RSPIn_SPSR_SPRF                     (0x80u)
+
+#define RSPIn_SPDR_UINT32                   (0xFFFFFFFFuL)
+
+#define RSPIn_SPDR_UINT16                   (0xFFFFu)
+
+#define RSPIn_SPDR_UINT8                    (0xFFu)
+
+#define RSPIn_SPSCR_SPSLN                   (0x03u)
+
+#define RSPIn_SPSSR_SPCP                    (0x03u)
+
+#define RSPIn_SPBR_SPR                      (0xFFu)
+
+#define RSPIn_SPDCR_SPLW                    (0x60u)
+#define RSPIn_SPDCR_TXDMY                   (0x80u)
+
+#define RSPIn_SPCKD_SCKDL                   (0x07u)
+
+#define RSPIn_SSLND_SLNDL                   (0x07u)
+
+#define RSPIn_SPND_SPNDL                    (0x07u)
+
+#define RSPIn_SPCMD0_CPHA                   (0x0001u)
+#define RSPIn_SPCMD0_CPOL                   (0x0002u)
+#define RSPIn_SPCMD0_BRDV                   (0x000Cu)
+#define RSPIn_SPCMD0_SSLKP                  (0x0080u)
+#define RSPIn_SPCMD0_SPB                    (0x0F00u)
+#define RSPIn_SPCMD0_LSBF                   (0x1000u)
+#define RSPIn_SPCMD0_SPNDEN                 (0x2000u)
+#define RSPIn_SPCMD0_SLNDEN                 (0x4000u)
+#define RSPIn_SPCMD0_SCKDEN                 (0x8000u)
+
+#define RSPIn_SPCMD1_CPHA                   (0x0001u)
+#define RSPIn_SPCMD1_CPOL                   (0x0002u)
+#define RSPIn_SPCMD1_BRDV                   (0x000Cu)
+#define RSPIn_SPCMD1_SSLKP                  (0x0080u)
+#define RSPIn_SPCMD1_SPB                    (0x0F00u)
+#define RSPIn_SPCMD1_LSBF                   (0x1000u)
+#define RSPIn_SPCMD1_SPNDEN                 (0x2000u)
+#define RSPIn_SPCMD1_SLNDEN                 (0x4000u)
+#define RSPIn_SPCMD1_SCKDEN                 (0x8000u)
+
+#define RSPIn_SPCMD2_CPHA                   (0x0001u)
+#define RSPIn_SPCMD2_CPOL                   (0x0002u)
+#define RSPIn_SPCMD2_BRDV                   (0x000Cu)
+#define RSPIn_SPCMD2_SSLKP                  (0x0080u)
+#define RSPIn_SPCMD2_SPB                    (0x0F00u)
+#define RSPIn_SPCMD2_LSBF                   (0x1000u)
+#define RSPIn_SPCMD2_SPNDEN                 (0x2000u)
+#define RSPIn_SPCMD2_SLNDEN                 (0x4000u)
+#define RSPIn_SPCMD2_SCKDEN                 (0x8000u)
+
+#define RSPIn_SPCMD3_CPHA                   (0x0001u)
+#define RSPIn_SPCMD3_CPOL                   (0x0002u)
+#define RSPIn_SPCMD3_BRDV                   (0x000Cu)
+#define RSPIn_SPCMD3_SSLKP                  (0x0080u)
+#define RSPIn_SPCMD3_SPB                    (0x0F00u)
+#define RSPIn_SPCMD3_LSBF                   (0x1000u)
+#define RSPIn_SPCMD3_SPNDEN                 (0x2000u)
+#define RSPIn_SPCMD3_SLNDEN                 (0x4000u)
+#define RSPIn_SPCMD3_SCKDEN                 (0x8000u)
+
+#define RSPIn_SPBFCR_RXTRG                  (0x07u)
+#define RSPIn_SPBFCR_TXTRG                  (0x30u)
+#define RSPIn_SPBFCR_RXRST                  (0x40u)
+#define RSPIn_SPBFCR_TXRST                  (0x80u)
+
+#define RSPIn_SPBFDR_R                      (0x003Fu)
+#define RSPIn_SPBFDR_T                      (0x0F00u)
+
+
+/* ==== Shift values for IO registers ==== */
+#define RSPIn_SPCR_MODFEN_SHIFT             (2u)
+#define RSPIn_SPCR_MSTR_SHIFT               (3u)
+#define RSPIn_SPCR_SPEIE_SHIFT              (4u)
+#define RSPIn_SPCR_SPTIE_SHIFT              (5u)
+#define RSPIn_SPCR_SPE_SHIFT                (6u)
+#define RSPIn_SPCR_SPRIE_SHIFT              (7u)
+
+#define RSPIn_SSLP_SSL0P_SHIFT              (0u)
+
+#define RSPIn_SPPCR_SPLP_SHIFT              (0u)
+#define RSPIn_SPPCR_MOIFV_SHIFT             (4u)
+#define RSPIn_SPPCR_MOIFE_SHIFT             (5u)
+
+#define RSPIn_SPSR_OVRF_SHIFT               (0u)
+#define RSPIn_SPSR_MODF_SHIFT               (2u)
+#define RSPIn_SPSR_SPTEF_SHIFT              (5u)
+#define RSPIn_SPSR_TEND_SHIFT               (6u)
+#define RSPIn_SPSR_SPRF_SHIFT               (7u)
+
+#define RSPIn_SPDR_UINT32_SHIFT             (0u)
+
+#define RSPIn_SPDR_UINT16_SHIFT             (0u)
+
+#define RSPIn_SPDR_UINT8_SHIFT              (0u)
+
+#define RSPIn_SPSCR_SPSLN_SHIFT             (0u)
+
+#define RSPIn_SPSSR_SPCP_SHIFT              (0u)
+
+#define RSPIn_SPBR_SPR_SHIFT                (0u)
+
+#define RSPIn_SPDCR_SPLW_SHIFT              (5u)
+#define RSPIn_SPDCR_TXDMY_SHIFT             (7u)
+
+#define RSPIn_SPCKD_SCKDL_SHIFT             (0u)
+
+#define RSPIn_SSLND_SLNDL_SHIFT             (0u)
+
+#define RSPIn_SPND_SPNDL_SHIFT              (0u)
+
+#define RSPIn_SPCMD0_CPHA_SHIFT             (0u)
+#define RSPIn_SPCMD0_CPOL_SHIFT             (1u)
+#define RSPIn_SPCMD0_BRDV_SHIFT             (2u)
+#define RSPIn_SPCMD0_SSLKP_SHIFT            (7u)
+#define RSPIn_SPCMD0_SPB_SHIFT              (8u)
+#define RSPIn_SPCMD0_LSBF_SHIFT             (12u)
+#define RSPIn_SPCMD0_SPNDEN_SHIFT           (13u)
+#define RSPIn_SPCMD0_SLNDEN_SHIFT           (14u)
+#define RSPIn_SPCMD0_SCKDEN_SHIFT           (15u)
+
+#define RSPIn_SPCMD1_CPHA_SHIFT             (0u)
+#define RSPIn_SPCMD1_CPOL_SHIFT             (1u)
+#define RSPIn_SPCMD1_BRDV_SHIFT             (2u)
+#define RSPIn_SPCMD1_SSLKP_SHIFT            (7u)
+#define RSPIn_SPCMD1_SPB_SHIFT              (8u)
+#define RSPIn_SPCMD1_LSBF_SHIFT             (12u)
+#define RSPIn_SPCMD1_SPNDEN_SHIFT           (13u)
+#define RSPIn_SPCMD1_SLNDEN_SHIFT           (14u)
+#define RSPIn_SPCMD1_SCKDEN_SHIFT           (15u)
+
+#define RSPIn_SPCMD2_CPHA_SHIFT             (0u)
+#define RSPIn_SPCMD2_CPOL_SHIFT             (1u)
+#define RSPIn_SPCMD2_BRDV_SHIFT             (2u)
+#define RSPIn_SPCMD2_SSLKP_SHIFT            (7u)
+#define RSPIn_SPCMD2_SPB_SHIFT              (8u)
+#define RSPIn_SPCMD2_LSBF_SHIFT             (12u)
+#define RSPIn_SPCMD2_SPNDEN_SHIFT           (13u)
+#define RSPIn_SPCMD2_SLNDEN_SHIFT           (14u)
+#define RSPIn_SPCMD2_SCKDEN_SHIFT           (15u)
+
+#define RSPIn_SPCMD3_CPHA_SHIFT             (0u)
+#define RSPIn_SPCMD3_CPOL_SHIFT             (1u)
+#define RSPIn_SPCMD3_BRDV_SHIFT             (2u)
+#define RSPIn_SPCMD3_SSLKP_SHIFT            (7u)
+#define RSPIn_SPCMD3_SPB_SHIFT              (8u)
+#define RSPIn_SPCMD3_LSBF_SHIFT             (12u)
+#define RSPIn_SPCMD3_SPNDEN_SHIFT           (13u)
+#define RSPIn_SPCMD3_SLNDEN_SHIFT           (14u)
+#define RSPIn_SPCMD3_SCKDEN_SHIFT           (15u)
+
+#define RSPIn_SPBFCR_RXTRG_SHIFT            (0u)
+#define RSPIn_SPBFCR_TXTRG_SHIFT            (4u)
+#define RSPIn_SPBFCR_RXRST_SHIFT            (6u)
+#define RSPIn_SPBFCR_TXRST_SHIFT            (7u)
+
+#define RSPIn_SPBFDR_R_SHIFT                (0u)
+#define RSPIn_SPBFDR_T_SHIFT                (8u)
+
+
+#endif /* RSPI_IOBITMASK_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/scif_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1066 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : scif_iobitmask.h
+* $Rev: 1115 $
+* $Date:: 2014-07-09 15:35:02 +0900#$
+* Description : SCIF register define header
+*******************************************************************************/
+#ifndef SCIF_IOBITMASK_H
+#define SCIF_IOBITMASK_H
+
+
+/* ==== Mask values for IO registers ==== */
+/* ---- SCIF0 ---- */
+#define SCIF0_SCSMR_CKS                         (0x0003u)
+#define SCIF0_SCSMR_STOP                        (0x0008u)
+#define SCIF0_SCSMR_OE                          (0x0010u)
+#define SCIF0_SCSMR_PE                          (0x0020u)
+#define SCIF0_SCSMR_CHR                         (0x0040u)
+#define SCIF0_SCSMR_CA                          (0x0080u)
+
+#define SCIF0_SCBRR_D                           (0xFFu)
+
+#define SCIF0_SCSCR_CKE                         (0x0003u)
+#define SCIF0_SCSCR_REIE                        (0x0008u)
+#define SCIF0_SCSCR_RE                          (0x0010u)
+#define SCIF0_SCSCR_TE                          (0x0020u)
+#define SCIF0_SCSCR_RIE                         (0x0040u)
+#define SCIF0_SCSCR_TIE                         (0x0080u)
+
+#define SCIF0_SCFTDR_D                          (0xFFu)
+
+#define SCIF0_SCFSR_DR                          (0x0001u)
+#define SCIF0_SCFSR_RDF                         (0x0002u)
+#define SCIF0_SCFSR_PER                         (0x0004u)
+#define SCIF0_SCFSR_FER                         (0x0008u)
+#define SCIF0_SCFSR_BRK                         (0x0010u)
+#define SCIF0_SCFSR_TDFE                        (0x0020u)
+#define SCIF0_SCFSR_TEND                        (0x0040u)
+#define SCIF0_SCFSR_ER                          (0x0080u)
+#define SCIF0_SCFSR_FERN                        (0x0F00u)
+#define SCIF0_SCFSR_PERN                        (0xF000u)
+
+#define SCIF0_SCFRDR_D                          (0xFFu)
+
+#define SCIF0_SCFCR_LOOP                        (0x0001u)
+#define SCIF0_SCFCR_RFRST                       (0x0002u)
+#define SCIF0_SCFCR_TFRST                       (0x0004u)
+#define SCIF0_SCFCR_MCE                         (0x0008u)
+#define SCIF0_SCFCR_TTRG                        (0x0030u)
+#define SCIF0_SCFCR_RTRG                        (0x00C0u)
+#define SCIF0_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF0_SCFDR_R                           (0x001Fu)
+#define SCIF0_SCFDR_T                           (0x1F00u)
+
+#define SCIF0_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF0_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF0_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF0_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF0_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF0_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF0_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF0_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF0_SCLSR_ORER                        (0x0001u)
+
+#define SCIF0_SCEMR_ABCS                        (0x0001u)
+#define SCIF0_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF1 ---- */
+#define SCIF1_SCSMR_CKS                         (0x0003u)
+#define SCIF1_SCSMR_STOP                        (0x0008u)
+#define SCIF1_SCSMR_OE                          (0x0010u)
+#define SCIF1_SCSMR_PE                          (0x0020u)
+#define SCIF1_SCSMR_CHR                         (0x0040u)
+#define SCIF1_SCSMR_CA                          (0x0080u)
+
+#define SCIF1_SCBRR_D                           (0xFFu)
+
+#define SCIF1_SCSCR_CKE                         (0x0003u)
+#define SCIF1_SCSCR_REIE                        (0x0008u)
+#define SCIF1_SCSCR_RE                          (0x0010u)
+#define SCIF1_SCSCR_TE                          (0x0020u)
+#define SCIF1_SCSCR_RIE                         (0x0040u)
+#define SCIF1_SCSCR_TIE                         (0x0080u)
+
+#define SCIF1_SCFTDR_D                          (0xFFu)
+
+#define SCIF1_SCFSR_DR                          (0x0001u)
+#define SCIF1_SCFSR_RDF                         (0x0002u)
+#define SCIF1_SCFSR_PER                         (0x0004u)
+#define SCIF1_SCFSR_FER                         (0x0008u)
+#define SCIF1_SCFSR_BRK                         (0x0010u)
+#define SCIF1_SCFSR_TDFE                        (0x0020u)
+#define SCIF1_SCFSR_TEND                        (0x0040u)
+#define SCIF1_SCFSR_ER                          (0x0080u)
+#define SCIF1_SCFSR_FERN                        (0x0F00u)
+#define SCIF1_SCFSR_PERN                        (0xF000u)
+
+#define SCIF1_SCFRDR_D                          (0xFFu)
+
+#define SCIF1_SCFCR_LOOP                        (0x0001u)
+#define SCIF1_SCFCR_RFRST                       (0x0002u)
+#define SCIF1_SCFCR_TFRST                       (0x0004u)
+#define SCIF1_SCFCR_MCE                         (0x0008u)
+#define SCIF1_SCFCR_TTRG                        (0x0030u)
+#define SCIF1_SCFCR_RTRG                        (0x00C0u)
+#define SCIF1_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF1_SCFDR_R                           (0x001Fu)
+#define SCIF1_SCFDR_T                           (0x1F00u)
+
+#define SCIF1_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF1_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF1_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF1_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF1_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF1_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF1_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF1_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF1_SCLSR_ORER                        (0x0001u)
+
+#define SCIF1_SCEMR_ABCS                        (0x0001u)
+#define SCIF1_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF2 ---- */
+#define SCIF2_SCSMR_CKS                         (0x0003u)
+#define SCIF2_SCSMR_STOP                        (0x0008u)
+#define SCIF2_SCSMR_OE                          (0x0010u)
+#define SCIF2_SCSMR_PE                          (0x0020u)
+#define SCIF2_SCSMR_CHR                         (0x0040u)
+#define SCIF2_SCSMR_CA                          (0x0080u)
+
+#define SCIF2_SCBRR_D                           (0xFFu)
+
+#define SCIF2_SCSCR_CKE                         (0x0003u)
+#define SCIF2_SCSCR_REIE                        (0x0008u)
+#define SCIF2_SCSCR_RE                          (0x0010u)
+#define SCIF2_SCSCR_TE                          (0x0020u)
+#define SCIF2_SCSCR_RIE                         (0x0040u)
+#define SCIF2_SCSCR_TIE                         (0x0080u)
+
+#define SCIF2_SCFTDR_D                          (0xFFu)
+
+#define SCIF2_SCFSR_DR                          (0x0001u)
+#define SCIF2_SCFSR_RDF                         (0x0002u)
+#define SCIF2_SCFSR_PER                         (0x0004u)
+#define SCIF2_SCFSR_FER                         (0x0008u)
+#define SCIF2_SCFSR_BRK                         (0x0010u)
+#define SCIF2_SCFSR_TDFE                        (0x0020u)
+#define SCIF2_SCFSR_TEND                        (0x0040u)
+#define SCIF2_SCFSR_ER                          (0x0080u)
+#define SCIF2_SCFSR_FERN                        (0x0F00u)
+#define SCIF2_SCFSR_PERN                        (0xF000u)
+
+#define SCIF2_SCFRDR_D                          (0xFFu)
+
+#define SCIF2_SCFCR_LOOP                        (0x0001u)
+#define SCIF2_SCFCR_RFRST                       (0x0002u)
+#define SCIF2_SCFCR_TFRST                       (0x0004u)
+#define SCIF2_SCFCR_MCE                         (0x0008u)
+#define SCIF2_SCFCR_TTRG                        (0x0030u)
+#define SCIF2_SCFCR_RTRG                        (0x00C0u)
+#define SCIF2_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF2_SCFDR_R                           (0x001Fu)
+#define SCIF2_SCFDR_T                           (0x1F00u)
+
+#define SCIF2_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF2_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF2_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF2_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF2_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF2_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF2_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF2_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF2_SCLSR_ORER                        (0x0001u)
+
+#define SCIF2_SCEMR_ABCS                        (0x0001u)
+#define SCIF2_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF3 ---- */
+#define SCIF3_SCSMR_CKS                         (0x0003u)
+#define SCIF3_SCSMR_STOP                        (0x0008u)
+#define SCIF3_SCSMR_OE                          (0x0010u)
+#define SCIF3_SCSMR_PE                          (0x0020u)
+#define SCIF3_SCSMR_CHR                         (0x0040u)
+#define SCIF3_SCSMR_CA                          (0x0080u)
+
+#define SCIF3_SCBRR_D                           (0xFFu)
+
+#define SCIF3_SCSCR_CKE                         (0x0003u)
+#define SCIF3_SCSCR_REIE                        (0x0008u)
+#define SCIF3_SCSCR_RE                          (0x0010u)
+#define SCIF3_SCSCR_TE                          (0x0020u)
+#define SCIF3_SCSCR_RIE                         (0x0040u)
+#define SCIF3_SCSCR_TIE                         (0x0080u)
+
+#define SCIF3_SCFTDR_D                          (0xFFu)
+
+#define SCIF3_SCFSR_DR                          (0x0001u)
+#define SCIF3_SCFSR_RDF                         (0x0002u)
+#define SCIF3_SCFSR_PER                         (0x0004u)
+#define SCIF3_SCFSR_FER                         (0x0008u)
+#define SCIF3_SCFSR_BRK                         (0x0010u)
+#define SCIF3_SCFSR_TDFE                        (0x0020u)
+#define SCIF3_SCFSR_TEND                        (0x0040u)
+#define SCIF3_SCFSR_ER                          (0x0080u)
+#define SCIF3_SCFSR_FERN                        (0x0F00u)
+#define SCIF3_SCFSR_PERN                        (0xF000u)
+
+#define SCIF3_SCFRDR_D                          (0xFFu)
+
+#define SCIF3_SCFCR_LOOP                        (0x0001u)
+#define SCIF3_SCFCR_RFRST                       (0x0002u)
+#define SCIF3_SCFCR_TFRST                       (0x0004u)
+#define SCIF3_SCFCR_MCE                         (0x0008u)
+#define SCIF3_SCFCR_TTRG                        (0x0030u)
+#define SCIF3_SCFCR_RTRG                        (0x00C0u)
+#define SCIF3_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF3_SCFDR_R                           (0x001Fu)
+#define SCIF3_SCFDR_T                           (0x1F00u)
+
+#define SCIF3_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF3_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF3_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF3_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF3_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF3_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF3_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF3_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF3_SCLSR_ORER                        (0x0001u)
+
+#define SCIF3_SCEMR_ABCS                        (0x0001u)
+#define SCIF3_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF4 ---- */
+#define SCIF4_SCSMR_CKS                         (0x0003u)
+#define SCIF4_SCSMR_STOP                        (0x0008u)
+#define SCIF4_SCSMR_OE                          (0x0010u)
+#define SCIF4_SCSMR_PE                          (0x0020u)
+#define SCIF4_SCSMR_CHR                         (0x0040u)
+#define SCIF4_SCSMR_CA                          (0x0080u)
+
+#define SCIF4_SCBRR_D                           (0xFFu)
+
+#define SCIF4_SCSCR_CKE                         (0x0003u)
+#define SCIF4_SCSCR_REIE                        (0x0008u)
+#define SCIF4_SCSCR_RE                          (0x0010u)
+#define SCIF4_SCSCR_TE                          (0x0020u)
+#define SCIF4_SCSCR_RIE                         (0x0040u)
+#define SCIF4_SCSCR_TIE                         (0x0080u)
+
+#define SCIF4_SCFTDR_D                          (0xFFu)
+
+#define SCIF4_SCFSR_DR                          (0x0001u)
+#define SCIF4_SCFSR_RDF                         (0x0002u)
+#define SCIF4_SCFSR_PER                         (0x0004u)
+#define SCIF4_SCFSR_FER                         (0x0008u)
+#define SCIF4_SCFSR_BRK                         (0x0010u)
+#define SCIF4_SCFSR_TDFE                        (0x0020u)
+#define SCIF4_SCFSR_TEND                        (0x0040u)
+#define SCIF4_SCFSR_ER                          (0x0080u)
+#define SCIF4_SCFSR_FERN                        (0x0F00u)
+#define SCIF4_SCFSR_PERN                        (0xF000u)
+
+#define SCIF4_SCFRDR_D                          (0xFFu)
+
+#define SCIF4_SCFCR_LOOP                        (0x0001u)
+#define SCIF4_SCFCR_RFRST                       (0x0002u)
+#define SCIF4_SCFCR_TFRST                       (0x0004u)
+#define SCIF4_SCFCR_MCE                         (0x0008u)
+#define SCIF4_SCFCR_TTRG                        (0x0030u)
+#define SCIF4_SCFCR_RTRG                        (0x00C0u)
+#define SCIF4_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF4_SCFDR_R                           (0x001Fu)
+#define SCIF4_SCFDR_T                           (0x1F00u)
+
+#define SCIF4_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF4_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF4_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF4_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF4_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF4_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF4_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF4_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF4_SCLSR_ORER                        (0x0001u)
+
+#define SCIF4_SCEMR_ABCS                        (0x0001u)
+#define SCIF4_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF5 ---- */
+#define SCIF5_SCSMR_CKS                         (0x0003u)
+#define SCIF5_SCSMR_STOP                        (0x0008u)
+#define SCIF5_SCSMR_OE                          (0x0010u)
+#define SCIF5_SCSMR_PE                          (0x0020u)
+#define SCIF5_SCSMR_CHR                         (0x0040u)
+#define SCIF5_SCSMR_CA                          (0x0080u)
+
+#define SCIF5_SCBRR_D                           (0xFFu)
+
+#define SCIF5_SCSCR_CKE                         (0x0003u)
+#define SCIF5_SCSCR_REIE                        (0x0008u)
+#define SCIF5_SCSCR_RE                          (0x0010u)
+#define SCIF5_SCSCR_TE                          (0x0020u)
+#define SCIF5_SCSCR_RIE                         (0x0040u)
+#define SCIF5_SCSCR_TIE                         (0x0080u)
+
+#define SCIF5_SCFTDR_D                          (0xFFu)
+
+#define SCIF5_SCFSR_DR                          (0x0001u)
+#define SCIF5_SCFSR_RDF                         (0x0002u)
+#define SCIF5_SCFSR_PER                         (0x0004u)
+#define SCIF5_SCFSR_FER                         (0x0008u)
+#define SCIF5_SCFSR_BRK                         (0x0010u)
+#define SCIF5_SCFSR_TDFE                        (0x0020u)
+#define SCIF5_SCFSR_TEND                        (0x0040u)
+#define SCIF5_SCFSR_ER                          (0x0080u)
+#define SCIF5_SCFSR_FERN                        (0x0F00u)
+#define SCIF5_SCFSR_PERN                        (0xF000u)
+
+#define SCIF5_SCFRDR_D                          (0xFFu)
+
+#define SCIF5_SCFCR_LOOP                        (0x0001u)
+#define SCIF5_SCFCR_RFRST                       (0x0002u)
+#define SCIF5_SCFCR_TFRST                       (0x0004u)
+#define SCIF5_SCFCR_MCE                         (0x0008u)
+#define SCIF5_SCFCR_TTRG                        (0x0030u)
+#define SCIF5_SCFCR_RTRG                        (0x00C0u)
+#define SCIF5_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF5_SCFDR_R                           (0x001Fu)
+#define SCIF5_SCFDR_T                           (0x1F00u)
+
+#define SCIF5_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF5_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF5_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF5_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF5_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF5_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF5_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF5_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF5_SCLSR_ORER                        (0x0001u)
+
+#define SCIF5_SCEMR_ABCS                        (0x0001u)
+#define SCIF5_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF6 ---- */
+#define SCIF6_SCSMR_CKS                         (0x0003u)
+#define SCIF6_SCSMR_STOP                        (0x0008u)
+#define SCIF6_SCSMR_OE                          (0x0010u)
+#define SCIF6_SCSMR_PE                          (0x0020u)
+#define SCIF6_SCSMR_CHR                         (0x0040u)
+#define SCIF6_SCSMR_CA                          (0x0080u)
+
+#define SCIF6_SCBRR_D                           (0xFFu)
+
+#define SCIF6_SCSCR_CKE                         (0x0003u)
+#define SCIF6_SCSCR_REIE                        (0x0008u)
+#define SCIF6_SCSCR_RE                          (0x0010u)
+#define SCIF6_SCSCR_TE                          (0x0020u)
+#define SCIF6_SCSCR_RIE                         (0x0040u)
+#define SCIF6_SCSCR_TIE                         (0x0080u)
+
+#define SCIF6_SCFTDR_D                          (0xFFu)
+
+#define SCIF6_SCFSR_DR                          (0x0001u)
+#define SCIF6_SCFSR_RDF                         (0x0002u)
+#define SCIF6_SCFSR_PER                         (0x0004u)
+#define SCIF6_SCFSR_FER                         (0x0008u)
+#define SCIF6_SCFSR_BRK                         (0x0010u)
+#define SCIF6_SCFSR_TDFE                        (0x0020u)
+#define SCIF6_SCFSR_TEND                        (0x0040u)
+#define SCIF6_SCFSR_ER                          (0x0080u)
+#define SCIF6_SCFSR_FERN                        (0x0F00u)
+#define SCIF6_SCFSR_PERN                        (0xF000u)
+
+#define SCIF6_SCFRDR_D                          (0xFFu)
+
+#define SCIF6_SCFCR_LOOP                        (0x0001u)
+#define SCIF6_SCFCR_RFRST                       (0x0002u)
+#define SCIF6_SCFCR_TFRST                       (0x0004u)
+#define SCIF6_SCFCR_MCE                         (0x0008u)
+#define SCIF6_SCFCR_TTRG                        (0x0030u)
+#define SCIF6_SCFCR_RTRG                        (0x00C0u)
+#define SCIF6_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF6_SCFDR_R                           (0x001Fu)
+#define SCIF6_SCFDR_T                           (0x1F00u)
+
+#define SCIF6_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF6_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF6_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF6_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF6_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF6_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF6_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF6_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF6_SCLSR_ORER                        (0x0001u)
+
+#define SCIF6_SCEMR_ABCS                        (0x0001u)
+#define SCIF6_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIF7 ---- */
+#define SCIF7_SCSMR_CKS                         (0x0003u)
+#define SCIF7_SCSMR_STOP                        (0x0008u)
+#define SCIF7_SCSMR_OE                          (0x0010u)
+#define SCIF7_SCSMR_PE                          (0x0020u)
+#define SCIF7_SCSMR_CHR                         (0x0040u)
+#define SCIF7_SCSMR_CA                          (0x0080u)
+
+#define SCIF7_SCBRR_D                           (0xFFu)
+
+#define SCIF7_SCSCR_CKE                         (0x0003u)
+#define SCIF7_SCSCR_REIE                        (0x0008u)
+#define SCIF7_SCSCR_RE                          (0x0010u)
+#define SCIF7_SCSCR_TE                          (0x0020u)
+#define SCIF7_SCSCR_RIE                         (0x0040u)
+#define SCIF7_SCSCR_TIE                         (0x0080u)
+
+#define SCIF7_SCFTDR_D                          (0xFFu)
+
+#define SCIF7_SCFSR_DR                          (0x0001u)
+#define SCIF7_SCFSR_RDF                         (0x0002u)
+#define SCIF7_SCFSR_PER                         (0x0004u)
+#define SCIF7_SCFSR_FER                         (0x0008u)
+#define SCIF7_SCFSR_BRK                         (0x0010u)
+#define SCIF7_SCFSR_TDFE                        (0x0020u)
+#define SCIF7_SCFSR_TEND                        (0x0040u)
+#define SCIF7_SCFSR_ER                          (0x0080u)
+#define SCIF7_SCFSR_FERN                        (0x0F00u)
+#define SCIF7_SCFSR_PERN                        (0xF000u)
+
+#define SCIF7_SCFRDR_D                          (0xFFu)
+
+#define SCIF7_SCFCR_LOOP                        (0x0001u)
+#define SCIF7_SCFCR_RFRST                       (0x0002u)
+#define SCIF7_SCFCR_TFRST                       (0x0004u)
+#define SCIF7_SCFCR_MCE                         (0x0008u)
+#define SCIF7_SCFCR_TTRG                        (0x0030u)
+#define SCIF7_SCFCR_RTRG                        (0x00C0u)
+#define SCIF7_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIF7_SCFDR_R                           (0x001Fu)
+#define SCIF7_SCFDR_T                           (0x1F00u)
+
+#define SCIF7_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIF7_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIF7_SCSPTR_SCKDT                      (0x0004u)
+#define SCIF7_SCSPTR_SCKIO                      (0x0008u)
+#define SCIF7_SCSPTR_CTSDT                      (0x0010u)
+#define SCIF7_SCSPTR_CTSIO                      (0x0020u)
+#define SCIF7_SCSPTR_RTSDT                      (0x0040u)
+#define SCIF7_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIF7_SCLSR_ORER                        (0x0001u)
+
+#define SCIF7_SCEMR_ABCS                        (0x0001u)
+#define SCIF7_SCEMR_BGDM                        (0x0080u)
+
+/* ---- SCIFn ---- */
+#define SCIFn_SCSMR_CKS                         (0x0003u)
+#define SCIFn_SCSMR_STOP                        (0x0008u)
+#define SCIFn_SCSMR_OE                          (0x0010u)
+#define SCIFn_SCSMR_PE                          (0x0020u)
+#define SCIFn_SCSMR_CHR                         (0x0040u)
+#define SCIFn_SCSMR_CA                          (0x0080u)
+
+#define SCIFn_SCBRR_D                           (0xFFu)
+
+#define SCIFn_SCSCR_CKE                         (0x0003u)
+#define SCIFn_SCSCR_REIE                        (0x0008u)
+#define SCIFn_SCSCR_RE                          (0x0010u)
+#define SCIFn_SCSCR_TE                          (0x0020u)
+#define SCIFn_SCSCR_RIE                         (0x0040u)
+#define SCIFn_SCSCR_TIE                         (0x0080u)
+
+#define SCIFn_SCFTDR_D                          (0xFFu)
+
+#define SCIFn_SCFSR_DR                          (0x0001u)
+#define SCIFn_SCFSR_RDF                         (0x0002u)
+#define SCIFn_SCFSR_PER                         (0x0004u)
+#define SCIFn_SCFSR_FER                         (0x0008u)
+#define SCIFn_SCFSR_BRK                         (0x0010u)
+#define SCIFn_SCFSR_TDFE                        (0x0020u)
+#define SCIFn_SCFSR_TEND                        (0x0040u)
+#define SCIFn_SCFSR_ER                          (0x0080u)
+#define SCIFn_SCFSR_FERN                        (0x0F00u)
+#define SCIFn_SCFSR_PERN                        (0xF000u)
+
+#define SCIFn_SCFRDR_D                          (0xFFu)
+
+#define SCIFn_SCFCR_LOOP                        (0x0001u)
+#define SCIFn_SCFCR_RFRST                       (0x0002u)
+#define SCIFn_SCFCR_TFRST                       (0x0004u)
+#define SCIFn_SCFCR_MCE                         (0x0008u)
+#define SCIFn_SCFCR_TTRG                        (0x0030u)
+#define SCIFn_SCFCR_RTRG                        (0x00C0u)
+#define SCIFn_SCFCR_RSTRG                       (0x0700u)
+
+#define SCIFn_SCFDR_R                           (0x001Fu)
+#define SCIFn_SCFDR_T                           (0x1F00u)
+
+#define SCIFn_SCSPTR_SPB2DT                     (0x0001u)
+#define SCIFn_SCSPTR_SPB2IO                     (0x0002u)
+#define SCIFn_SCSPTR_SCKDT                      (0x0004u)
+#define SCIFn_SCSPTR_SCKIO                      (0x0008u)
+#define SCIFn_SCSPTR_CTSDT                      (0x0010u)
+#define SCIFn_SCSPTR_CTSIO                      (0x0020u)
+#define SCIFn_SCSPTR_RTSDT                      (0x0040u)
+#define SCIFn_SCSPTR_RTSIO                      (0x0080u)
+
+#define SCIFn_SCLSR_ORER                        (0x0001u)
+
+#define SCIFn_SCEMR_ABCS                        (0x0001u)
+#define SCIFn_SCEMR_BGDM                        (0x0080u)
+
+
+/* ==== Shift values for IO registers ==== */
+/* ---- SCIF0 ---- */
+#define SCIF0_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF0_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF0_SCSMR_OE_SHIFT                    (4u)
+#define SCIF0_SCSMR_PE_SHIFT                    (5u)
+#define SCIF0_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF0_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF0_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF0_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF0_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF0_SCSCR_RE_SHIFT                    (4u)
+#define SCIF0_SCSCR_TE_SHIFT                    (5u)
+#define SCIF0_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF0_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF0_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF0_SCFSR_DR_SHIFT                    (0u)
+#define SCIF0_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF0_SCFSR_PER_SHIFT                   (2u)
+#define SCIF0_SCFSR_FER_SHIFT                   (3u)
+#define SCIF0_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF0_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF0_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF0_SCFSR_ER_SHIFT                    (7u)
+#define SCIF0_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF0_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF0_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF0_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF0_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF0_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF0_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF0_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF0_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF0_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF0_SCFDR_R_SHIFT                     (0u)
+#define SCIF0_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF0_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF0_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF0_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF0_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF0_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF0_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF0_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF0_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF0_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF0_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF0_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF1 ---- */
+#define SCIF1_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF1_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF1_SCSMR_OE_SHIFT                    (4u)
+#define SCIF1_SCSMR_PE_SHIFT                    (5u)
+#define SCIF1_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF1_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF1_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF1_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF1_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF1_SCSCR_RE_SHIFT                    (4u)
+#define SCIF1_SCSCR_TE_SHIFT                    (5u)
+#define SCIF1_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF1_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF1_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF1_SCFSR_DR_SHIFT                    (0u)
+#define SCIF1_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF1_SCFSR_PER_SHIFT                   (2u)
+#define SCIF1_SCFSR_FER_SHIFT                   (3u)
+#define SCIF1_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF1_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF1_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF1_SCFSR_ER_SHIFT                    (7u)
+#define SCIF1_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF1_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF1_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF1_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF1_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF1_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF1_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF1_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF1_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF1_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF1_SCFDR_R_SHIFT                     (0u)
+#define SCIF1_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF1_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF1_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF1_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF1_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF1_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF1_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF1_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF1_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF1_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF1_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF1_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF2 ---- */
+#define SCIF2_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF2_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF2_SCSMR_OE_SHIFT                    (4u)
+#define SCIF2_SCSMR_PE_SHIFT                    (5u)
+#define SCIF2_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF2_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF2_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF2_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF2_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF2_SCSCR_RE_SHIFT                    (4u)
+#define SCIF2_SCSCR_TE_SHIFT                    (5u)
+#define SCIF2_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF2_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF2_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF2_SCFSR_DR_SHIFT                    (0u)
+#define SCIF2_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF2_SCFSR_PER_SHIFT                   (2u)
+#define SCIF2_SCFSR_FER_SHIFT                   (3u)
+#define SCIF2_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF2_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF2_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF2_SCFSR_ER_SHIFT                    (7u)
+#define SCIF2_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF2_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF2_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF2_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF2_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF2_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF2_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF2_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF2_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF2_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF2_SCFDR_R_SHIFT                     (0u)
+#define SCIF2_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF2_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF2_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF2_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF2_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF2_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF2_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF2_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF2_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF2_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF2_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF2_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF3 ---- */
+#define SCIF3_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF3_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF3_SCSMR_OE_SHIFT                    (4u)
+#define SCIF3_SCSMR_PE_SHIFT                    (5u)
+#define SCIF3_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF3_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF3_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF3_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF3_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF3_SCSCR_RE_SHIFT                    (4u)
+#define SCIF3_SCSCR_TE_SHIFT                    (5u)
+#define SCIF3_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF3_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF3_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF3_SCFSR_DR_SHIFT                    (0u)
+#define SCIF3_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF3_SCFSR_PER_SHIFT                   (2u)
+#define SCIF3_SCFSR_FER_SHIFT                   (3u)
+#define SCIF3_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF3_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF3_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF3_SCFSR_ER_SHIFT                    (7u)
+#define SCIF3_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF3_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF3_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF3_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF3_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF3_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF3_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF3_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF3_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF3_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF3_SCFDR_R_SHIFT                     (0u)
+#define SCIF3_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF3_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF3_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF3_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF3_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF3_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF3_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF3_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF3_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF3_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF3_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF3_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF4 ---- */
+#define SCIF4_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF4_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF4_SCSMR_OE_SHIFT                    (4u)
+#define SCIF4_SCSMR_PE_SHIFT                    (5u)
+#define SCIF4_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF4_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF4_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF4_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF4_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF4_SCSCR_RE_SHIFT                    (4u)
+#define SCIF4_SCSCR_TE_SHIFT                    (5u)
+#define SCIF4_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF4_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF4_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF4_SCFSR_DR_SHIFT                    (0u)
+#define SCIF4_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF4_SCFSR_PER_SHIFT                   (2u)
+#define SCIF4_SCFSR_FER_SHIFT                   (3u)
+#define SCIF4_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF4_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF4_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF4_SCFSR_ER_SHIFT                    (7u)
+#define SCIF4_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF4_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF4_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF4_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF4_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF4_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF4_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF4_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF4_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF4_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF4_SCFDR_R_SHIFT                     (0u)
+#define SCIF4_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF4_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF4_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF4_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF4_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF4_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF4_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF4_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF4_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF4_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF4_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF4_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF5 ---- */
+#define SCIF5_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF5_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF5_SCSMR_OE_SHIFT                    (4u)
+#define SCIF5_SCSMR_PE_SHIFT                    (5u)
+#define SCIF5_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF5_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF5_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF5_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF5_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF5_SCSCR_RE_SHIFT                    (4u)
+#define SCIF5_SCSCR_TE_SHIFT                    (5u)
+#define SCIF5_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF5_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF5_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF5_SCFSR_DR_SHIFT                    (0u)
+#define SCIF5_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF5_SCFSR_PER_SHIFT                   (2u)
+#define SCIF5_SCFSR_FER_SHIFT                   (3u)
+#define SCIF5_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF5_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF5_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF5_SCFSR_ER_SHIFT                    (7u)
+#define SCIF5_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF5_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF5_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF5_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF5_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF5_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF5_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF5_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF5_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF5_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF5_SCFDR_R_SHIFT                     (0u)
+#define SCIF5_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF5_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF5_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF5_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF5_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF5_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF5_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF5_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF5_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF5_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF5_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF5_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF6 ---- */
+#define SCIF6_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF6_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF6_SCSMR_OE_SHIFT                    (4u)
+#define SCIF6_SCSMR_PE_SHIFT                    (5u)
+#define SCIF6_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF6_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF6_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF6_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF6_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF6_SCSCR_RE_SHIFT                    (4u)
+#define SCIF6_SCSCR_TE_SHIFT                    (5u)
+#define SCIF6_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF6_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF6_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF6_SCFSR_DR_SHIFT                    (0u)
+#define SCIF6_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF6_SCFSR_PER_SHIFT                   (2u)
+#define SCIF6_SCFSR_FER_SHIFT                   (3u)
+#define SCIF6_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF6_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF6_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF6_SCFSR_ER_SHIFT                    (7u)
+#define SCIF6_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF6_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF6_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF6_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF6_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF6_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF6_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF6_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF6_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF6_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF6_SCFDR_R_SHIFT                     (0u)
+#define SCIF6_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF6_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF6_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF6_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF6_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF6_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF6_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF6_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF6_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF6_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF6_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF6_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIF7 ---- */
+#define SCIF7_SCSMR_CKS_SHIFT                   (0u)
+#define SCIF7_SCSMR_STOP_SHIFT                  (3u)
+#define SCIF7_SCSMR_OE_SHIFT                    (4u)
+#define SCIF7_SCSMR_PE_SHIFT                    (5u)
+#define SCIF7_SCSMR_CHR_SHIFT                   (6u)
+#define SCIF7_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIF7_SCBRR_D_SHIFT                     (0u)
+
+#define SCIF7_SCSCR_CKE_SHIFT                   (0u)
+#define SCIF7_SCSCR_REIE_SHIFT                  (3u)
+#define SCIF7_SCSCR_RE_SHIFT                    (4u)
+#define SCIF7_SCSCR_TE_SHIFT                    (5u)
+#define SCIF7_SCSCR_RIE_SHIFT                   (6u)
+#define SCIF7_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIF7_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIF7_SCFSR_DR_SHIFT                    (0u)
+#define SCIF7_SCFSR_RDF_SHIFT                   (1u)
+#define SCIF7_SCFSR_PER_SHIFT                   (2u)
+#define SCIF7_SCFSR_FER_SHIFT                   (3u)
+#define SCIF7_SCFSR_BRK_SHIFT                   (4u)
+#define SCIF7_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIF7_SCFSR_TEND_SHIFT                  (6u)
+#define SCIF7_SCFSR_ER_SHIFT                    (7u)
+#define SCIF7_SCFSR_FERN_SHIFT                  (8u)
+#define SCIF7_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIF7_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIF7_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIF7_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIF7_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIF7_SCFCR_MCE_SHIFT                   (3u)
+#define SCIF7_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIF7_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIF7_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIF7_SCFDR_R_SHIFT                     (0u)
+#define SCIF7_SCFDR_T_SHIFT                     (8u)
+
+#define SCIF7_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIF7_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIF7_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIF7_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIF7_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIF7_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIF7_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIF7_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIF7_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIF7_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIF7_SCEMR_BGDM_SHIFT                  (7u)
+
+/* ---- SCIFn ---- */
+#define SCIFn_SCSMR_CKS_SHIFT                   (0u)
+#define SCIFn_SCSMR_STOP_SHIFT                  (3u)
+#define SCIFn_SCSMR_OE_SHIFT                    (4u)
+#define SCIFn_SCSMR_PE_SHIFT                    (5u)
+#define SCIFn_SCSMR_CHR_SHIFT                   (6u)
+#define SCIFn_SCSMR_CA_SHIFT                    (7u)
+
+#define SCIFn_SCBRR_D_SHIFT                     (0u)
+
+#define SCIFn_SCSCR_CKE_SHIFT                   (0u)
+#define SCIFn_SCSCR_REIE_SHIFT                  (3u)
+#define SCIFn_SCSCR_RE_SHIFT                    (4u)
+#define SCIFn_SCSCR_TE_SHIFT                    (5u)
+#define SCIFn_SCSCR_RIE_SHIFT                   (6u)
+#define SCIFn_SCSCR_TIE_SHIFT                   (7u)
+
+#define SCIFn_SCFTDR_D_SHIFT                    (0u)
+
+#define SCIFn_SCFSR_DR_SHIFT                    (0u)
+#define SCIFn_SCFSR_RDF_SHIFT                   (1u)
+#define SCIFn_SCFSR_PER_SHIFT                   (2u)
+#define SCIFn_SCFSR_FER_SHIFT                   (3u)
+#define SCIFn_SCFSR_BRK_SHIFT                   (4u)
+#define SCIFn_SCFSR_TDFE_SHIFT                  (5u)
+#define SCIFn_SCFSR_TEND_SHIFT                  (6u)
+#define SCIFn_SCFSR_ER_SHIFT                    (7u)
+#define SCIFn_SCFSR_FERN_SHIFT                  (8u)
+#define SCIFn_SCFSR_PERN_SHIFT                  (12u)
+
+#define SCIFn_SCFRDR_D_SHIFT                    (0u)
+
+#define SCIFn_SCFCR_LOOP_SHIFT                  (0u)
+#define SCIFn_SCFCR_RFRST_SHIFT                 (1u)
+#define SCIFn_SCFCR_TFRST_SHIFT                 (2u)
+#define SCIFn_SCFCR_MCE_SHIFT                   (3u)
+#define SCIFn_SCFCR_TTRG_SHIFT                  (4u)
+#define SCIFn_SCFCR_RTRG_SHIFT                  (6u)
+#define SCIFn_SCFCR_RSTRG_SHIFT                 (8u)
+
+#define SCIFn_SCFDR_R_SHIFT                     (0u)
+#define SCIFn_SCFDR_T_SHIFT                     (8u)
+
+#define SCIFn_SCSPTR_SPB2DT_SHIFT               (0u)
+#define SCIFn_SCSPTR_SPB2IO_SHIFT               (1u)
+#define SCIFn_SCSPTR_SCKDT_SHIFT                (2u)
+#define SCIFn_SCSPTR_SCKIO_SHIFT                (3u)
+#define SCIFn_SCSPTR_CTSDT_SHIFT                (4u)
+#define SCIFn_SCSPTR_CTSIO_SHIFT                (5u)
+#define SCIFn_SCSPTR_RTSDT_SHIFT                (6u)
+#define SCIFn_SCSPTR_RTSIO_SHIFT                (7u)
+
+#define SCIFn_SCLSR_ORER_SHIFT                  (0u)
+
+#define SCIFn_SCEMR_ABCS_SHIFT                  (0u)
+#define SCIFn_SCEMR_BGDM_SHIFT                  (7u)
+
+
+#endif /* SCIF_IOBITMASK_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iobitmasks/usb_iobitmask.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,732 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : usb_iobitmask.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : USB register define header
+*******************************************************************************/
+#ifndef USB_IOBITMASK_H
+#define USB_IOBITMASK_H
+
+/*==============================================*/
+/* SYSCFG                                       */
+/*==============================================*/
+#define     USB_SYSCFG_USBE                 (0x0001u)
+#define     USB_SYSCFG_UPLLE                (0x0002u)
+#define     USB_SYSCFG_UCKSEL               (0x0004u)
+/* #define  USB_SYSCFG_RESERVED1            (0x0008u) */
+#define     USB_SYSCFG_DPRPU                (0x0010u)
+#define     USB_SYSCFG_DRPD                 (0x0020u)
+#define     USB_SYSCFG_DCFM                 (0x0040u)
+#define     USB_SYSCFG_HSE                  (0x0080u)
+/* #define  USB_SYSCFG_RESERVED2            (0xFF00u) */
+
+#define     USB_SYSCFG_USBE_SHIFT           (0)
+#define     USB_SYSCFG_UPLLE_SHIFT          (1)
+#define     USB_SYSCFG_UCKSEL_SHIFT         (2)
+/* #define  USB_SYSCFG_RESERVED1_SHIFT      (3) */
+#define     USB_SYSCFG_DPRPU_SHIFT          (4)
+#define     USB_SYSCFG_DRPD_SHIFT           (5)
+#define     USB_SYSCFG_DCFM_SHIFT           (6)
+#define     USB_SYSCFG_HSE_SHIFT            (7)
+/* #define  USB_SYSCFG_RESERVED2_SHIFT      (8) */
+
+/*==============================================*/
+/* BUSWAIT                                      */
+/*==============================================*/
+#define     USB_BUSWAIT_BWAIT               (0x003Fu)
+
+#define     USB_BUSWAIT_BWAIT_SHIFT         (0)
+
+/*==============================================*/
+/* SYSSTS0                                      */
+/*==============================================*/
+#define     USB_SYSSTS0_LNST                (0x0003u)
+#define     USB_SYSSTS0_SOFEA               (0x0020u)
+#define     USB_SYSSTS0_HTACT               (0x0040u)
+
+#define     USB_SYSSTS0_LNST_SHIFT          (0)
+#define     USB_SYSSTS0_SOFEA_SHIFT         (5)
+#define     USB_SYSSTS0_HTACT_SHIFT         (6)
+
+/*==============================================*/
+/* DVSTCTR0                                     */
+/*==============================================*/
+#define     USB_DVSTCTR0_RHST               (0x0007u)
+/* #define  USB_DVSTCTR0_RESERVED           (0x0008u) */
+#define     USB_DVSTCTR0_UACT               (0x0010u)
+#define     USB_DVSTCTR0_RESUME             (0x0020u)
+#define     USB_DVSTCTR0_USBRST             (0x0040u)
+#define     USB_DVSTCTR0_RWUPE              (0x0080u)
+#define     USB_DVSTCTR0_WKUP               (0x0100u)
+
+#define     USB_DVSTCTR0_RHST_SHIFT         (0)
+/* #define  USB_DVSTCTR0_RESERVED_SHIFT     (3) */
+#define     USB_DVSTCTR0_UACT_SHIFT         (4)
+#define     USB_DVSTCTR0_RESUME_SHIFT       (5)
+#define     USB_DVSTCTR0_USBRST_SHIFT       (6)
+#define     USB_DVSTCTR0_RWUPE_SHIFT        (7)
+#define     USB_DVSTCTR0_WKUP_SHIFT         (8)
+
+/*==============================================*/
+/* TESTMODE                                     */
+/*==============================================*/
+#define     USB_TESTMODE_UTST               (0x000Fu)
+/* #define  USB_TESTMODE_RESERVED           (0xFFF0u) */
+
+#define     USB_TESTMODE_UTST_SHIFT         (0)
+/* #define  USB_TESTMODE_RESERVED_SHIFT     (4) */
+
+/*==============================================*/
+/* DnFBCFG                                      */
+/*==============================================*/
+/* #define      USB_DnFBCFG_RESERVED1       (0x000Fu) */
+#define     USB_DnFBCFG_TENDE               (0x0010u)
+/* #define      USB_DnFBCFG_RESERVED2       (0x0FE0u) */
+#define     USB_DnFBCFG_DFACC               (0x3000u)
+/* #define      USB_DnFBCFG_RESERVED3       (0xC000u) */
+
+/* #define  USB_DnFBCFG_RESERVED1_SHIFT     (0) */
+#define     USB_DnFBCFG_TENDE_SHIFT         (4)
+/* #define  USB_DnFBCFG_RESERVED2_SHIFT     (5) */
+#define     USB_DnFBCFG_DFACC_SHIFT         (12)
+/* #define  USB_DnFBCFG_RESERVED3_SHIFT     (14) */
+
+/*==============================================*/
+/* CFIFO                                        */
+/*==============================================*/
+#define     USB_CFIFO_FIFOPORT              (0xFFFFFFFFuL)
+
+#define     USB_CFIFO_FIFOPORT_SHIFT        (0)
+
+/*==============================================*/
+/* DnFIFO                                       */
+/*==============================================*/
+#define     USB_DnFIFO_FIFOPORT             (0xFFFFFFFFuL)
+
+#define     USB_DnFIFO_FIFOPORT_SHIFT       (0)
+
+/*==============================================*/
+/* CFIFOSEL                                     */
+/*==============================================*/
+#define     USB_CFIFOSEL_CURPIPE            (0x000Fu)
+/* #define  USB_CFIFOSEL_RESERVED1          (0x0010u) */
+#define     USB_CFIFOSEL_ISEL_              (0x0020u)
+/* #define  USB_CFIFOSEL_RESERVED2          (0x00C0u) */
+#define     USB_CFIFOSEL_BIGEND             (0x0100u)
+/* #define  USB_CFIFOSEL_RESERVED3          (0x0200u) */
+#define     USB_CFIFOSEL_MBW                (0x0C00u)
+/* #define  USB_CFIFOSEL_RESERVED4          (0x3000u) */
+#define     USB_CFIFOSEL_REW                (0x4000u)
+#define     USB_CFIFOSEL_RCNT               (0x8000u)
+
+#define     USB_CFIFOSEL_CURPIPE_SHIFT      (0)
+/* #define  USB_CFIFOSEL_RESERVED1_SHIFT    (4) */
+#define     USB_CFIFOSEL_ISEL_SHIFT_        (5)
+/* #define  USB_CFIFOSEL_RESERVED2_SHIFT    (6) */
+#define     USB_CFIFOSEL_BIGEND_SHIFT       (8)
+/* #define  USB_CFIFOSEL_RESERVED3_SHIFT    (9) */
+#define     USB_CFIFOSEL_MBW_SHIFT          (10)
+/* #define  USB_CFIFOSEL_RESERVED4_SHIFT    (12) */
+#define     USB_CFIFOSEL_REW_SHIFT          (14)
+#define     USB_CFIFOSEL_RCNT_SHIFT         (15)
+
+/*==============================================*/
+/* DnFIFOSEL                                    */
+/*==============================================*/
+#define     USB_DnFIFOSEL_CURPIPE           (0x000Fu)
+/* #define  USB_DnFIFOSEL_RESERVED1         (0x00F0u) */
+#define     USB_DnFIFOSEL_BIGEND            (0x0100u)
+/* #define  USB_DnFIFOSEL_RESERVED2         (0x0200u) */
+#define     USB_DnFIFOSEL_MBW               (0x0C00u)
+#define     USB_DnFIFOSEL_DREQE             (0x1000u)
+#define     USB_DnFIFOSEL_DCLRM             (0x2000u)
+#define     USB_DnFIFOSEL_REW               (0x4000u)
+#define     USB_DnFIFOSEL_RCNT              (0x8000u)
+
+#define     USB_DnFIFOSEL_CURPIPE_SHIFT     (0)
+/* #define  USB_DnFIFOSEL_RESERVED1_SHIFT   (4) */
+#define     USB_DnFIFOSEL_BIGEND_SHIFT      (8)
+/* #define  USB_DnFIFOSEL_RESERVED2_SHIFT   (9) */
+#define     USB_DnFIFOSEL_MBW_SHIFT         (10)
+#define     USB_DnFIFOSEL_DREQE_SHIFT       (12)
+#define     USB_DnFIFOSEL_DCLRM_SHIFT       (13)
+#define     USB_DnFIFOSEL_REW_SHIFT         (14)
+#define     USB_DnFIFOSEL_RCNT_SHIFT        (15)
+
+/*==============================================*/
+/* CFIFOCTR                                     */
+/*==============================================*/
+#define     USB_CFIFOCTR_DTLN               (0x0FFFu)
+/* #define  USB_CFIFOCTR_RESERVED           (0x1000u) */
+#define     USB_CFIFOCTR_FRDY               (0x2000u)
+#define     USB_CFIFOCTR_BCLR               (0x4000u)
+#define     USB_CFIFOCTR_BVAL               (0x8000u)
+
+#define     USB_CFIFOCTR_DTLN_SHIFT         (0)
+/* #define  USB_CFIFOCTR_RESERVED_SHIFT     (12) */
+#define     USB_CFIFOCTR_FRDY_SHIFT         (13)
+#define     USB_CFIFOCTR_BCLR_SHIFT         (14)
+#define     USB_CFIFOCTR_BVAL_SHIFT         (15)
+
+/*==============================================*/
+/* DnFIFOCTR                                    */
+/*==============================================*/
+#define     USB_DnFIFOCTR_DTLN              (0x0FFFu)
+/* #define  USB_DnFIFOCTR_RESERVED          (0x1000u) */
+#define     USB_DnFIFOCTR_FRDY              (0x2000u)
+#define     USB_DnFIFOCTR_BCLR              (0x4000u)
+#define     USB_DnFIFOCTR_BVAL              (0x8000u)
+
+#define     USB_DnFIFOCTR_DTLN_SHIFT        (0)
+/* #define  USB_DnFIFOCTR_RESERVED_SHIFT    (12) */
+#define     USB_DnFIFOCTR_FRDY_SHIFT        (13)
+#define     USB_DnFIFOCTR_BCLR_SHIFT        (14)
+#define     USB_DnFIFOCTR_BVAL_SHIFT        (15)
+
+/*==============================================*/
+/* INTENB0                                      */
+/*==============================================*/
+/* #define  USB_INTENB0_RESERVED            (0x00FFu) */
+#define     USB_INTENB0_BRDYE               (0x0100u)
+#define     USB_INTENB0_NRDYE               (0x0200u)
+#define     USB_INTENB0_BEMPE               (0x0400u)
+#define     USB_INTENB0_CTRE                (0x0800u)
+#define     USB_INTENB0_DVSE                (0x1000u)
+#define     USB_INTENB0_SOFE                (0x2000u)
+#define     USB_INTENB0_RSME                (0x4000u)
+#define     USB_INTENB0_VBSE                (0x8000u)
+
+/* #define  USB_INTENB0_RESERVED_SHIFT      (0) */
+#define     USB_INTENB0_BRDYE_SHIFT         (8)
+#define     USB_INTENB0_NRDYE_SHIFT         (9)
+#define     USB_INTENB0_BEMPE_SHIFT         (10)
+#define     USB_INTENB0_CTRE_SHIFT          (11)
+#define     USB_INTENB0_DVSE_SHIFT          (12)
+#define     USB_INTENB0_SOFE_SHIFT          (13)
+#define     USB_INTENB0_RSME_SHIFT          (14)
+#define     USB_INTENB0_VBSE_SHIFT          (15)
+
+/*==============================================*/
+/* INTENB1                                      */
+/*==============================================*/
+/* #define  USB_INTENB1_RESERVED1           (0x000Fu) */
+#define     USB_INTENB1_SACKE               (0x0010u)
+#define     USB_INTENB1_SIGNE               (0x0020u)
+#define     USB_INTENB1_EOFERRE             (0x0040u)
+/* #define  USB_INTENB1_RESERVED2           (0x0780u) */
+#define     USB_INTENB1_ATTCHE              (0x0800u)
+#define     USB_INTENB1_DTCHE               (0x1000u)
+/* #define  USB_INTENB1_RESERVED3           (0x2000u) */
+#define     USB_INTENB1_BCHGE               (0x4000u)
+/* #define  USB_INTENB1_RESERVED4           (0x8000u) */
+
+/* #define  USB_INTENB1_RESERVED1_SHIFT     (0) */
+#define     USB_INTENB1_SACKE_SHIFT         (4)
+#define     USB_INTENB1_SIGNE_SHIFT         (5)
+#define     USB_INTENB1_EOFERRE_SHIFT       (6)
+/* #define  USB_INTENB1_RESERVED2_SHIFT     (7) */
+#define     USB_INTENB1_ATTCHE_SHIFT        (11)
+#define     USB_INTENB1_DTCHE_SHIFT         (12)
+/* #define  USB_INTENB1_RESERVED3_SHIFT     (13) */
+#define     USB_INTENB1_BCHGE_SHIFT         (14)
+/* #define  USB_INTENB1_RESERVED4_SHIFT     (15) */
+
+/*==============================================*/
+/* BRDYENB                                      */
+/*==============================================*/
+#define     USB_BRDYENB                     (0xFFFFu)
+
+#define     USB_BRDYENB_SHIFT               (0)
+
+/*==============================================*/
+/* NRDYENB                                      */
+/*==============================================*/
+#define     USB_NRDYENB                     (0xFFFFu)
+
+#define     USB_NRDYENB_SHIFT               (0)
+
+/*==============================================*/
+/* BEMPENB                                      */
+/*==============================================*/
+#define     USB_BEMPENB                     (0xFFFFu)
+
+#define     USB_BEMPENB_SHIFT               (0)
+
+/*==============================================*/
+/* SOFCFG                                       */
+/*==============================================*/
+/* #define  USB_SOFCFG_RESERVED1            (0x003Fu) */
+#define     USB_SOFCFG_BRDYM                (0x0040u)
+/* #define  USB_SOFCFG_RESERVED2            (0x0080u) */
+#define     USB_SOFCFG_TRNENSEL             (0x0100u)
+/* #define  USB_SOFCFG_RESERVED3            (0xFE00u) */
+
+/* #define  USB_SOFCFG_RESERVED1_SHIFT      (0) */
+#define     USB_SOFCFG_BRDYM_SHIFT          (6)
+/* #define  USB_SOFCFG_RESERVED2_SHIFT      (7) */
+#define     USB_SOFCFG_TRNENSEL_SHIFT       (8)
+/* #define  USB_SOFCFG_RESERVED3_SHIFT      (9) */
+
+/*==============================================*/
+/* INTSTS0                                      */
+/*==============================================*/
+#define     USB_INTSTS0_CTSQ                (0x0007u)
+#define     USB_INTSTS0_VALID               (0x0008u)
+#define     USB_INTSTS0_DVSQ                (0x0070u)
+#define     USB_INTSTS0_VBSTS               (0x0080u)
+#define     USB_INTSTS0_BRDY                (0x0100u)
+#define     USB_INTSTS0_NRDY                (0x0200u)
+#define     USB_INTSTS0_BEMP                (0x0400u)
+#define     USB_INTSTS0_CTRT                (0x0800u)
+#define     USB_INTSTS0_DVST                (0x1000u)
+#define     USB_INTSTS0_SOFR                (0x2000u)
+#define     USB_INTSTS0_RESM                (0x4000u)
+#define     USB_INTSTS0_VBINT               (0x8000u)
+
+#define     USB_INTSTS0_CTSQ_SHIFT          (0)
+#define     USB_INTSTS0_VALID_SHIFT         (3)
+#define     USB_INTSTS0_DVSQ_SHIFT          (4)
+#define     USB_INTSTS0_VBSTS_SHIFT         (7)
+#define     USB_INTSTS0_BRDY_SHIFT          (8)
+#define     USB_INTSTS0_NRDY_SHIFT          (9)
+#define     USB_INTSTS0_BEMP_SHIFT          (10)
+#define     USB_INTSTS0_CTRT_SHIFT          (11)
+#define     USB_INTSTS0_DVST_SHIFT          (12)
+#define     USB_INTSTS0_SOFR_SHIFT          (13)
+#define     USB_INTSTS0_RESM_SHIFT          (14)
+#define     USB_INTSTS0_VBINT_SHIFT         (15)
+
+/*==============================================*/
+/* INTSTS1                                      */
+/*==============================================*/
+/* #define  USB_INTSTS1_RESERVED1           (0x000Fu) */
+#define     USB_INTSTS1_SACK                (0x0010u)
+#define     USB_INTSTS1_SIGN                (0x0020u)
+#define     USB_INTSTS1_EOFERR              (0x0040u)
+/* #define  USB_INTSTS1_RESERVED2           (0x0780u) */
+#define     USB_INTSTS1_ATTCH               (0x0800u)
+#define     USB_INTSTS1_DTCH                (0x1000u)
+/* #define  USB_INTSTS1_RESERVED3           (0x2000u) */
+#define     USB_INTSTS1_BCHG                (0x4000u)
+/* #define  USB_INTSTS1_RESERVED4           (0x8000u) */
+
+/* #define  USB_INTSTS1_RESERVED1_SHIFT     (0) */
+#define     USB_INTSTS1_SACK_SHIFT          (4)
+#define     USB_INTSTS1_SIGN_SHIFT          (5)
+#define     USB_INTSTS1_EOFERR_SHIFT        (6)
+/* #define  USB_INTSTS1_RESERVED2_SHIFT     (7) */
+#define     USB_INTSTS1_ATTCH_SHIFT         (11)
+#define     USB_INTSTS1_DTCH_SHIFT          (12)
+/* #define  USB_INTSTS1_RESERVED3_SHIFT     (13) */
+#define     USB_INTSTS1_BCHG_SHIFT          (14)
+/* #define  USB_INTSTS1_RESERVED4_SHIFT     (15) */
+
+/*==============================================*/
+/* BRDYSTS                                      */
+/*==============================================*/
+#define     USB_BRDYSTS                     (0xFFFFu)
+
+#define     USB_BRDYSTS_SHIFT               (0)
+
+/*==============================================*/
+/* NRDYSTS                                      */
+/*==============================================*/
+#define     USB_NRDYSTS                     (0xFFFFu)
+
+#define     USB_NRDYSTS_SHIFT               (0)
+
+/*==============================================*/
+/* BEMPSTS                                      */
+/*==============================================*/
+#define     USB_BEMPSTS                     (0xFFFFu)
+
+#define     USB_BEMPSTS_SHIFT               (0)
+
+/*==============================================*/
+/* FRMNUM                                       */
+/*==============================================*/
+#define     USB_FRMNUM_FRNM                 (0x07FFu)
+/* #define  USB_FRMNUM_RESERVED             (0x3800u) */
+#define     USB_FRMNUM_CRCE                 (0x4000u)
+#define     USB_FRMNUM_OVRN                 (0x8000u)
+
+#define     USB_FRMNUM_FRNM_SHIFT           (0)
+/* #define  USB_FRMNUM_RESERVED_SHIFT       (11) */
+#define     USB_FRMNUM_CRCE_SHIFT           (14)
+#define     USB_FRMNUM_OVRN_SHIFT           (15)
+
+/*==============================================*/
+/* UFRMNUM                                      */
+/*==============================================*/
+#define     USB_UFRMNUM_UFRNM               (0x0007u)
+/* #define  USB_UFRMNUM_RESERVED            (0xFFF8u) */
+
+#define     USB_UFRMNUM_UFRNM_SHIFT         (0)
+/* #define  USB_UFRMNUM_RESERVED_SHIFT      (3) */
+
+/*==============================================*/
+/* USBADDR                                      */
+/*==============================================*/
+#define     USB_USBADDR_USBADDR             (0x007Fu)
+/* #define  USB_USBADDR_RESERVED            (0xFF80u) */
+
+#define     USB_USBADDR_USBADDR_SHIFT       (0)
+/* #define  USB_USBADDR_RESERVED_SHIFT      (7) */
+
+/*==============================================*/
+/* USBREQ                                       */
+/*==============================================*/
+#define     USB_USBREQ_BMREQUESTTYPE        (0x00FFu)
+#define     USB_USBREQ_BREQUEST             (0xFF00u)
+
+#define     USB_USBREQ_BMREQUESTTYPE_SHIFT  (0)
+#define     USB_USBREQ_BREQUEST_SHIFT       (8)
+
+/*==============================================*/
+/* USBVAL                                       */
+/*==============================================*/
+#define     USB_USBVAL                      (0xFFFFu)
+
+#define     USB_USBVAL_SHIFT                (0)
+
+/*==============================================*/
+/* USBINDX                                      */
+/*==============================================*/
+#define     USB_USBINDX                     (0xFFFFu)
+
+#define     USB_USBINDX_SHIFT               (0)
+
+/*==============================================*/
+/* USBLENG                                      */
+/*==============================================*/
+#define     USB_USBLENG                     (0xFFFFu)
+
+#define     USB_USBLENG_SHIFT               (0)
+
+/*==============================================*/
+/* DCPCFG                                       */
+/*==============================================*/
+/* #define  USB_DCPCFG_RESERVED1            (0x000Fu) */
+#define     USB_DCPCFG_DIR                  (0x0010u)
+/* #define  USB_DCPCFG_RESERVED2            (0x0060u) */
+#define     USB_DCPCFG_SHTNAK               (0x0080u)
+#define     USB_DCPCFG_CNTMD                (0x0100u)
+/* #define  USB_DCPCFG_RESERVED3            (0xFE00u) */
+
+/* #define  USB_DCPCFG_RESERVED1_SHIFT      (0) */
+#define     USB_DCPCFG_DIR_SHIFT            (4)
+/* #define  USB_DCPCFG_RESERVED2_SHIFT      (5) */
+#define     USB_DCPCFG_SHTNK_SHIFT          (7)
+#define     USB_DCPCFG_CNTMD_SHIFT          (8)
+/* #define  USB_DCPCFG_RESERVED3            (9) */
+
+/*==============================================*/
+/* DCPMAXP                                      */
+/*==============================================*/
+#define     USB_DCPMAXP_MXPS                (0x007Fu)
+/* #define  USB_DCPMAXP_RESERVED            (0x0F80u) */
+#define     USB_DCPMAXP_DEVSEL              (0xF000u)
+
+#define     USB_DCPMAXP_MXPS_SHIFT          (0)
+/* #define  USB_DCPMAXP_RESERVED_SHIFT      (7) */
+#define     USB_DCPMAXP_DEVSEL_SHIFT        (12)
+
+/*==============================================*/
+/* DCPCTR                                       */
+/*==============================================*/
+#define     USB_DCPCTR_PID                  (0x0003u)
+#define     USB_DCPCTR_CCPL                 (0x0004u)
+/* #define  USB_DCPCTR_RESERVED1            (0x0008u) */
+#define     USB_DCPCTR_PINGE                (0x0010u)
+#define     USB_DCPCTR_PBUSY                (0x0020u)
+#define     USB_DCPCTR_SQMON                (0x0040u)
+#define     USB_DCPCTR_SQSET                (0x0080u)
+#define     USB_DCPCTR_SQCLR                (0x0100u)
+/* #define  USB_DCPCTR_RESERVED2            (0x0600u) */
+#define     USB_DCPCTR_SUREQCLR             (0x0800u)
+#define     USB_DCPCTR_CSSTS                (0x1000u)
+#define     USB_DCPCTR_CSCLR                (0x2000u)
+#define     USB_DCPCTR_SUREQ                (0x4000u)
+#define     USB_DCPCTR_BSTS                 (0x8000u)
+
+#define     USB_DCPCTR_PID_SHIFT            (0)
+#define     USB_DCPCTR_CCPL_SHIFT           (2)
+/* #define  USB_DCPCTR_RESERVED1_SHIFT      (3) */
+#define     USB_DCPCTR_PINGE_SHIFT          (4)
+#define     USB_DCPCTR_PBUSY_SHIFT          (5)
+#define     USB_DCPCTR_SQMON_SHIFT          (6)
+#define     USB_DCPCTR_SQSET_SHIFT          (7)
+#define     USB_DCPCTR_SQCLR_SHIFT          (8)
+/* #define  USB_DCPCTR_RESERVED2_SHIFT      (9) */
+#define     USB_DCPCTR_SUREQCLR_SHIFT       (11)
+#define     USB_DCPCTR_CSSTS_SHIFT          (12)
+#define     USB_DCPCTR_CSCLR_SHIFT          (13)
+#define     USB_DCPCTR_SUREQ_SHIFT          (14)
+#define     USB_DCPCTR_BSTS_SHIFT           (15)
+
+/*==============================================*/
+/* PIPESEL                                      */
+/*==============================================*/
+#define     USB_PIPESEL_PIPESEL             (0x000Fu)
+/* #define  USB_PIPESEL_RESERVED            (0xFFF0u) */
+
+#define     USB_PIPESEL_PIPESEL_SHIFT       (0)
+/* #define  USB_PIPESEL_RESERVED_SHIFT      (4) */
+
+/*==============================================*/
+/* PIPECFG                                      */
+/*==============================================*/
+#define     USB_PIPECFG_EPNUM               (0x000Fu)
+#define     USB_PIPECFG_DIR                 (0x0010u)
+/* #define  USB_PIPECFG_RESERVED1           (0x0060u) */
+#define     USB_PIPECFG_SHTNAK              (0x0080u)
+#define     USB_PIPECFG_CNTMD               (0x0100u)
+#define     USB_PIPECFG_DBLB                (0x0200u)
+#define     USB_PIPECFG_BFRE                (0x0400u)
+/* #define  USB_PIPECFG_RESERVED2           (0x3800u) */
+#define     USB_PIPECFG_TYPE                (0xC000u)
+
+#define     USB_PIPECFG_EPNUM_SHIFT         (0)
+#define     USB_PIPECFG_DIR_SHIFT           (4)
+/* #define  USB_PIPECFG_RESERVED1_SHIFT     (5) */
+#define     USB_PIPECFG_SHTNAK_SHIFT        (7)
+#define     USB_PIPECFG_CNTMD_SHIFT         (8)
+#define     USB_PIPECFG_DBLB_SHIFT          (9)
+#define     USB_PIPECFG_BFRE_SHIFT          (10)
+/* #define  USB_PIPECFG_RESERVED2_SHIFT     (11) */
+#define     USB_PIPECFG_TYPE_SHIFT          (14)
+
+/*==============================================*/
+/* PIPEBUF                                      */
+/*==============================================*/
+#define     USB_PIPEBUF_BUFNMB              (0x00FFu)
+/* #define  USB_PIPEBUF_RESERVED1           (0x0300u) */
+#define     USB_PIPEBUF_BUFSIZE             (0x7C00u)
+/* #define  USB_PIPEBUF_RESERVED2           (0x8000u) */
+
+#define     USB_PIPEBUF_BUFNMB_SHIFT        (0)
+/* #define  USB_PIPEBUF_RESERVED1_SHIFT     (8) */
+#define     USB_PIPEBUF_BUFSIZE_SHIFT       (10)
+/* #define  USB_PIPEBUF_RESERVED2_SHIFT     (15) */
+
+/*==============================================*/
+/* PIPEMAXP                                     */
+/*==============================================*/
+#define     USB_PIPEMAXP_MXPS               (0x07FFu)
+/* #define  USB_PIPEMAXP_RESERVED           (0x0800u) */
+#define     USB_PIPEMAXP_DEVSEL             (0xF000u)
+
+#define     USB_PIPEMAXP_MXPS_SHIFT         (0)
+/* #define  USB_PIPEMAXP_RESERVED_SHIFT     (11) */
+#define     USB_PIPEMAXP_DEVSEL_SHIFT       (12)
+
+/*==============================================*/
+/* PIPEPERI                                     */
+/*==============================================*/
+#define     USB_PIPEPERI_IITV               (0x0007u)
+/* #define  USB_PIPEPERI_RESERVED1          (0x0FF8u) */
+#define     USB_PIPEPERI_IFIS               (0x1000u)
+/* #define  USB_PIPEPERI_RESERVED2          (0xE000u) */
+
+#define     USB_PIPEPERI_IITV_SHIFT         (0)
+/* #define  USB_PIPEPERI_RESERVED1_SHIFT    (3) */
+#define     USB_PIPEPERI_IFIS_SHIFT         (12)
+/* #define  USB_PIPEPERI_RESERVED2_SHIFT    (13) */
+
+/*==============================================*/
+/* PIPEnCTR_1_5                                 */
+/*==============================================*/
+#define     USB_PIPEnCTR_1_5_PID                (0x0003u)
+/* #define  USB_PIPEnCTR_1_5_RESERVED1          (0x001Cu) */
+#define     USB_PIPEnCTR_1_5_PBUSY              (0x0020u)
+#define     USB_PIPEnCTR_1_5_SQMON              (0x0040u)
+#define     USB_PIPEnCTR_1_5_SQSET              (0x0080u)
+#define     USB_PIPEnCTR_1_5_SQCLR              (0x0100u)
+#define     USB_PIPEnCTR_1_5_ACLRM              (0x0200u)
+#define     USB_PIPEnCTR_1_5_ATREPM             (0x0400u)
+/* #define  USB_PIPEnCTR_1_5_RESERVED2          (0x0800u) */
+#define     USB_PIPEnCTR_1_5_CSSTS              (0x1000u)
+#define     USB_PIPEnCTR_1_5_CSCLR              (0x2000u)
+#define     USB_PIPEnCTR_1_5_INBUFM             (0x4000u)
+#define     USB_PIPEnCTR_1_5_BSTS               (0x8000u)
+
+#define     USB_PIPEnCTR_1_5_PID_SHIFT          (0)
+/* #define  USB_PIPEnCTR_1_5_RESERVED1_SHIFT    (2) */
+#define     USB_PIPEnCTR_1_5_PBUSY_SHIFT        (5)
+#define     USB_PIPEnCTR_1_5_SQMON_SHIFT        (6)
+#define     USB_PIPEnCTR_1_5_SQSET_SHIFT        (7)
+#define     USB_PIPEnCTR_1_5_SQCLR_SHIFT        (8)
+#define     USB_PIPEnCTR_1_5_ACLRM_SHIFT        (9)
+#define     USB_PIPEnCTR_1_5_ATREPM_SHIFT       (10)
+/* #define  USB_PIPEnCTR_1_5_RESERVED2_SHIFT    (11) */
+#define     USB_PIPEnCTR_1_5_CSSTS_SHIFT        (12)
+#define     USB_PIPEnCTR_1_5_CSCLR_SHIFT        (13)
+#define     USB_PIPEnCTR_1_5_INBUFM_SHIFT       (14)
+#define     USB_PIPEnCTR_1_5_BSTS_SHIFT         (15)
+
+/*==============================================*/
+/* PIPEnCTR_6_8                                 */
+/*==============================================*/
+#define     USB_PIPEnCTR_6_8_PID                (0x0003u)
+/* #define  USB_PIPEnCTR_6_8_RESERVED1          (0x001Cu) */
+#define     USB_PIPEnCTR_6_8_PBUSY              (0x0020u)
+#define     USB_PIPEnCTR_6_8_SQMON              (0x0040u)
+#define     USB_PIPEnCTR_6_8_SQSET              (0x0080u)
+#define     USB_PIPEnCTR_6_8_SQCLR              (0x0100u)
+#define     USB_PIPEnCTR_6_8_ACLRM              (0x0200u)
+/* #define  USB_PIPEnCTR_6_8_RESERVED2          (0x0C00u) */
+#define     USB_PIPEnCTR_6_8_CSSTS              (0x1000u)
+#define     USB_PIPEnCTR_6_8_CSCLR              (0x2000u)
+/* #define  USB_PIPEnCTR_6_8_RESERVED3          (0x4000u) */
+#define     USB_PIPEnCTR_6_8_BSTS               (0x8000u)
+
+#define     USB_PIPEnCTR_6_8_PID_SHIFT          (0)
+/* #define  USB_PIPEnCTR_6_8_RESERVED1_SHIFT    (2) */
+#define     USB_PIPEnCTR_6_8_PBUSY_SHIFT        (5)
+#define     USB_PIPEnCTR_6_8_SQMON_SHIFT        (6)
+#define     USB_PIPEnCTR_6_8_SQSET_SHIFT        (7)
+#define     USB_PIPEnCTR_6_8_SQCLR_SHIFT        (8)
+#define     USB_PIPEnCTR_6_8_ACLRM_SHIFT        (9)
+/* #define  USB_PIPEnCTR_6_8_RESERVED2_SHIFT    (10) */
+#define     USB_PIPEnCTR_6_8_CSSTS_SHIFT        (12)
+#define     USB_PIPEnCTR_6_8_CSCLR_SHIFT        (13)
+/* #define  USB_PIPEnCTR_6_8_RESERVED3_SHIFT    (14) */
+#define     USB_PIPEnCTR_6_8_BSTS_SHIFT         (15)
+
+/*==============================================*/
+/* PIPEnCTR_9                                   */
+/*==============================================*/
+#define     USB_PIPEnCTR_9_PID                  (0x0003u)
+/* #define  USB_PIPEnCTR_9_RESERVED1            (0x001Cu) */
+#define     USB_PIPEnCTR_9_PBUSY                (0x0020u)
+#define     USB_PIPEnCTR_9_SQMON                (0x0040u)
+#define     USB_PIPEnCTR_9_SQSET                (0x0080u)
+#define     USB_PIPEnCTR_9_SQCLR                (0x0100u)
+#define     USB_PIPEnCTR_9_ACLRM                (0x0200u)
+#define     USB_PIPEnCTR_9_ATREPM               (0x0400u)
+/* #define  USB_PIPEnCTR_9_RESERVED2            (0x0800u) */
+#define     USB_PIPEnCTR_9_CSSTS                (0x1000u)
+#define     USB_PIPEnCTR_9_CSCLR                (0x2000u)
+#define     USB_PIPEnCTR_9_INBUFM               (0x4000u)
+#define     USB_PIPEnCTR_9_BSTS                 (0x8000u)
+
+#define     USB_PIPEnCTR_9_PID_SHIFT            (0)
+/* #define  USB_PIPEnCTR_9_RESERVED1_SHIFT      (2) */
+#define     USB_PIPEnCTR_9_PBUSY_SHIFT          (5)
+#define     USB_PIPEnCTR_9_SQMON_SHIFT          (6)
+#define     USB_PIPEnCTR_9_SQSET_SHIFT          (7)
+#define     USB_PIPEnCTR_9_SQCLR_SHIFT          (8)
+#define     USB_PIPEnCTR_9_ACLRM_SHIFT          (9)
+#define     USB_PIPEnCTR_9_ATREPM_SHIFT         (10)
+/* #define  USB_PIPEnCTR_9_RESERVED2_SHIFT      (11) */
+#define     USB_PIPEnCTR_9_CSSTS_SHIFT          (12)
+#define     USB_PIPEnCTR_9_CSCLR_SHIFT          (13)
+#define     USB_PIPEnCTR_9_INBUFM_SHIFT         (14)
+#define     USB_PIPEnCTR_9_BSTS_SHIFT           (15)
+
+/*==============================================*/
+/* PIPEnCTR_A_F                                 */
+/*==============================================*/
+#define     USB_PIPEnCTR_A_F_PID                (0x0003u)
+/* #define  USB_PIPEnCTR_A_F_RESERVED1          (0x001Cu) */
+#define     USB_PIPEnCTR_A_F_PBUSY              (0x0020u)
+#define     USB_PIPEnCTR_A_F_SQMON              (0x0040u)
+#define     USB_PIPEnCTR_A_F_SQSET              (0x0080u)
+#define     USB_PIPEnCTR_A_F_SQCLR              (0x0100u)
+#define     USB_PIPEnCTR_A_F_ACLRM              (0x0200u)
+#define     USB_PIPEnCTR_A_F_ATREPM             (0x0400u)
+/* #define  USB_PIPEnCTR_A_F_RESERVED2          (0x3800u) */
+#define     USB_PIPEnCTR_A_F_INBUFM             (0x4000u)
+#define     USB_PIPEnCTR_A_F_BSTS               (0x8000u)
+
+#define     USB_PIPEnCTR_A_F_PID_SHIFT          (0)
+/* #define  USB_PIPEnCTR_A_F_RESERVED1_SHIFT    (2) */
+#define     USB_PIPEnCTR_A_F_PBUSY_SHIFT        (5)
+#define     USB_PIPEnCTR_A_F_SQMON_SHIFT        (6)
+#define     USB_PIPEnCTR_A_F_SQSET_SHIFT        (7)
+#define     USB_PIPEnCTR_A_F_SQCLR_SHIFT        (8)
+#define     USB_PIPEnCTR_A_F_ACLRM_SHIFT        (9)
+#define     USB_PIPEnCTR_A_F_ATREPM_SHIFT       (10)
+/* #define  USB_PIPEnCTR_A_F_RESERVED2_SHIFT    (11) */
+#define     USB_PIPEnCTR_A_F_INBUFM_SHIFT       (14)
+#define     USB_PIPEnCTR_A_F_BSTS_SHIFT         (15)
+
+/*==============================================*/
+/* PIPEnTRE                                     */
+/*==============================================*/
+/* #define  USB_PIPEnTRE_RESERVED1              (0x00FFu) */
+#define     USB_PIPEnTRE_TRCLR                  (0x0100u)
+#define     USB_PIPEnTRE_TRENB                  (0x0200u)
+/* #define  USB_PIPEnTRE_RESERVED2              (0xFC00u) */
+
+/* #define  USB_PIPEnTRE_RESERVED1_SHIFT        (0) */
+#define     USB_PIPEnTRE_TRCLR_SHIFT            (8)
+#define     USB_PIPEnTRE_TRENB_SHIFT            (9)
+/* #define  USB_PIPEnTRE_RESERVED2_SHIFT        (10) */
+
+/*==============================================*/
+/* PIPEnTRN                                     */
+/*==============================================*/
+#define     USB_PIPEnTRN                        (0xFFFFu)
+
+#define     USB_PIPEnTRN_SHIFT                  (0)
+
+/*==============================================*/
+/* DEVADDn                                      */
+/*==============================================*/
+/* #define  USB_DEVADDn_RESERVED1               (0x003Fu) */
+#define     USB_DEVADDn_USBSPD                  (0x00C0u)
+#define     USB_DEVADDn_HUBPORT                 (0x0700u)
+#define     USB_DEVADDn_UPPHUB                  (0x7800u)
+/* #define  USB_DEVADDn_RESERVED2               (0x8000u) */
+
+/* #define  USB_DEVADDn_RESERVED1_SHIFT         (0) */
+#define     USB_DEVADDn_USBSPD_SHIFT            (6)
+#define     USB_DEVADDn_HUBPORT_SHIFT           (8)
+#define     USB_DEVADDn_UPPHUB_SHIFT            (11)
+/* #define  USB_DEVADDn_RESERVED2_SHIFT         (15) */
+
+/*==============================================*/
+/* SUSPMODE                                     */
+/*==============================================*/
+/* #define  USB_SUSPMODE_RESERVED1              (0x3FFFu) */
+#define     USB_SUSPMODE_SUSPM                  (0x4000u)
+/* #define  USB_SUSPMODE_RESERVED2              (0x8000u) */
+
+/* #define  USB_SUSPMODE_RESERVED1_SHIFT        (0) */
+#define     USB_SUSPMODE_SUSPM_SHIFT            (14)
+/* #define  USB_SUSPMODE_RESERVED2_SHIFT        (15) */
+
+/*==============================================*/
+/* DnFIFOBm                                     */
+/*==============================================*/
+#define     USB_DnFIFOBm                        (0xFFFFu)
+
+#define     USB_DnFIFOBm_SHIFT                  (0)
+
+#endif /* USB_IOBITMASK_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef R7S72100_IODEFINE_H
+#define R7S72100_IODEFINE_H
+#define IODEFINE_H_VERSION  100
+
+enum iodefine_byte_select_t
+{
+    L = 0, H = 1,
+    LL= 0, LH = 1, HL = 2, HH = 3
+};
+
+/***********************************************************************
+  <<< [iodefine_reg32_t] >>> 
+- Padding : sizeof(iodefine_reg32_t) == 4
+- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+-                     &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
+- Endian : Independent (Same as CPU endian as register endian)
+- Bit-Order : Independent
+************************************************************************/
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+union iodefine_reg32_t
+{
+    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
+    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
+    volatile uint8_t   UINT8[4];                                /*  8-bit Access    */
+};
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+
+/***********************************************************************
+  <<< [iodefine_reg32_16_t] >>> 
+- Padding : sizeof(iodefine_reg32_16_t) == 4
+- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+- Endian : Independent (Same as CPU endian as register endian)
+- Bit-Order : Independent
+************************************************************************/
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+union iodefine_reg32_16_t
+{
+    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
+    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
+};
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+
+/***********************************************************************
+  <<< [iodefine_reg16_8_t] >>> 
+- Padding : sizeof(iodefine_reg16_8_t) == 2
+- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
+- Endian : Independent (Same as CPU endian as register endian)
+- Bit-Order : Independent
+************************************************************************/
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+union iodefine_reg16_8_t
+{
+    volatile uint16_t  UINT16;                                  /*  16-bit Access   */
+    volatile uint8_t   UINT8[2];                                /*  8-bit Access    */
+};
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+
+
+
+
+
+
+#include "adc_iodefine.h"                             /* (V1.00a) */
+#include "bsc_iodefine.h"                             /* (V1.00a) */
+#include "ceu_iodefine.h"                             /* (V1.00a) */
+#include "cpg_iodefine.h"                             /* (V1.00a) */
+#include "disc_iodefine.h"                            /* (V1.00a) */
+#include "dmac_iodefine.h"                            /* (V1.00a) */
+#include "dvdec_iodefine.h"                           /* (V1.00a) */
+#include "ether_iodefine.h"                           /* (V1.00a) */
+#include "flctl_iodefine.h"                           /* (V1.00a) */
+#include "gpio_iodefine.h"                            /* (V1.00a) */
+#include "ieb_iodefine.h"                             /* (V1.00a) */
+#include "inb_iodefine.h"                             /* (V1.00a) */
+#include "intc_iodefine.h"                            /* (V1.00a) */
+#include "irda_iodefine.h"                            /* (V1.00a) */
+#include "jcu_iodefine.h"                             /* (V1.00a) */
+#include "l2c_iodefine.h"                             /* (V1.00a) */
+#include "lin_iodefine.h"                             /* (V1.00a) */
+#include "lvds_iodefine.h"                            /* (V1.00a) */
+#include "mlb_iodefine.h"                             /* (V1.00a) */
+#include "mmc_iodefine.h"                             /* (V1.00a) */
+#include "mtu2_iodefine.h"                            /* (V1.00a) */
+#include "ostm_iodefine.h"                            /* (V1.00a) */
+#include "pfv_iodefine.h"                             /* (V1.00a) */
+#include "pwm_iodefine.h"                             /* (V1.00a) */
+#include "riic_iodefine.h"                            /* (V1.00a) */
+#include "romdec_iodefine.h"                          /* (V1.00a) */
+#include "rscan0_iodefine.h"                          /* (V1.00a) */
+#include "rspi_iodefine.h"                            /* (V1.00a) */
+#include "rtc_iodefine.h"                             /* (V1.00a) */
+#include "scif_iodefine.h"                            /* (V1.00a) */
+#include "scim_iodefine.h"                            /* (V1.00a) */
+#include "scux_iodefine.h"                            /* (V1.00a) */
+#include "sdg_iodefine.h"                             /* (V1.00a) */
+#include "spdif_iodefine.h"                           /* (V1.00a) */
+#include "spibsc_iodefine.h"                          /* (V1.00a) */
+#include "ssif_iodefine.h"                            /* (V1.00a) */
+#include "usb20_iodefine.h"                           /* (V1.00a) */
+#include "vdc5_iodefine.h"                            /* (V1.00a) */
+#include "wdt_iodefine.h"                             /* (V1.00a) */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/adc_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,99 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : adc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef ADC_IODEFINE_H
+#define ADC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_adc
+{                                                          /* ADC              */
+    volatile uint16_t ADDRA;                                  /*  ADDRA           */
+    volatile uint16_t ADDRB;                                  /*  ADDRB           */
+    volatile uint16_t ADDRC;                                  /*  ADDRC           */
+    volatile uint16_t ADDRD;                                  /*  ADDRD           */
+    volatile uint16_t ADDRE;                                  /*  ADDRE           */
+    volatile uint16_t ADDRF;                                  /*  ADDRF           */
+    volatile uint16_t ADDRG;                                  /*  ADDRG           */
+    volatile uint16_t ADDRH;                                  /*  ADDRH           */
+    volatile uint8_t   dummy32[16];                            /*                  */
+    volatile uint16_t ADCMPHA;                                /*  ADCMPHA         */
+    volatile uint16_t ADCMPLA;                                /*  ADCMPLA         */
+    volatile uint16_t ADCMPHB;                                /*  ADCMPHB         */
+    volatile uint16_t ADCMPLB;                                /*  ADCMPLB         */
+    volatile uint16_t ADCMPHC;                                /*  ADCMPHC         */
+    volatile uint16_t ADCMPLC;                                /*  ADCMPLC         */
+    volatile uint16_t ADCMPHD;                                /*  ADCMPHD         */
+    volatile uint16_t ADCMPLD;                                /*  ADCMPLD         */
+    volatile uint16_t ADCMPHE;                                /*  ADCMPHE         */
+    volatile uint16_t ADCMPLE;                                /*  ADCMPLE         */
+    volatile uint16_t ADCMPHF;                                /*  ADCMPHF         */
+    volatile uint16_t ADCMPLF;                                /*  ADCMPLF         */
+    volatile uint16_t ADCMPHG;                                /*  ADCMPHG         */
+    volatile uint16_t ADCMPLG;                                /*  ADCMPLG         */
+    volatile uint16_t ADCMPHH;                                /*  ADCMPHH         */
+    volatile uint16_t ADCMPLH;                                /*  ADCMPLH         */
+    volatile uint8_t   dummy33[32];                            /*                  */
+    volatile uint16_t ADCSR;                                  /*  ADCSR           */
+    volatile uint16_t ADCMPER;                                /*  ADCMPER         */
+    volatile uint16_t ADCMPSR;                                /*  ADCMPSR         */
+};
+
+
+#define ADC     (*(struct st_adc     *)0xE8005800uL) /* ADC */
+
+
+#define ADCADDRA ADC.ADDRA
+#define ADCADDRB ADC.ADDRB
+#define ADCADDRC ADC.ADDRC
+#define ADCADDRD ADC.ADDRD
+#define ADCADDRE ADC.ADDRE
+#define ADCADDRF ADC.ADDRF
+#define ADCADDRG ADC.ADDRG
+#define ADCADDRH ADC.ADDRH
+#define ADCADCMPHA ADC.ADCMPHA
+#define ADCADCMPLA ADC.ADCMPLA
+#define ADCADCMPHB ADC.ADCMPHB
+#define ADCADCMPLB ADC.ADCMPLB
+#define ADCADCMPHC ADC.ADCMPHC
+#define ADCADCMPLC ADC.ADCMPLC
+#define ADCADCMPHD ADC.ADCMPHD
+#define ADCADCMPLD ADC.ADCMPLD
+#define ADCADCMPHE ADC.ADCMPHE
+#define ADCADCMPLE ADC.ADCMPLE
+#define ADCADCMPHF ADC.ADCMPHF
+#define ADCADCMPLF ADC.ADCMPLF
+#define ADCADCMPHG ADC.ADCMPHG
+#define ADCADCMPLG ADC.ADCMPLG
+#define ADCADCMPHH ADC.ADCMPHH
+#define ADCADCMPLH ADC.ADCMPLH
+#define ADCADCSR ADC.ADCSR
+#define ADCADCMPER ADC.ADCMPER
+#define ADCADCMPSR ADC.ADCMPSR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/bsc_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,100 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : bsc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef BSC_IODEFINE_H
+#define BSC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_bsc
+{                                                          /* BSC              */
+    volatile uint32_t  CMNCR;                                  /*  CMNCR           */
+#define BSC_CSnBCR_COUNT 6
+    volatile uint32_t  CS0BCR;                                 /*  CS0BCR          */
+    volatile uint32_t  CS1BCR;                                 /*  CS1BCR          */
+    volatile uint32_t  CS2BCR;                                 /*  CS2BCR          */
+    volatile uint32_t  CS3BCR;                                 /*  CS3BCR          */
+    volatile uint32_t  CS4BCR;                                 /*  CS4BCR          */
+    volatile uint32_t  CS5BCR;                                 /*  CS5BCR          */
+    volatile uint8_t   dummy4[12];                             /*                  */
+#define BSC_CSnWCR_COUNT 6
+    volatile uint32_t  CS0WCR;                                 /*  CS0WCR          */
+    volatile uint32_t  CS1WCR;                                 /*  CS1WCR          */
+    volatile uint32_t  CS2WCR;                                 /*  CS2WCR          */
+    volatile uint32_t  CS3WCR;                                 /*  CS3WCR          */
+    volatile uint32_t  CS4WCR;                                 /*  CS4WCR          */
+    volatile uint32_t  CS5WCR;                                 /*  CS5WCR          */
+    volatile uint8_t   dummy5[12];                             /*                  */
+    volatile uint32_t  SDCR;                                   /*  SDCR            */
+    volatile uint32_t  RTCSR;                                  /*  RTCSR           */
+    volatile uint32_t  RTCNT;                                  /*  RTCNT           */
+    volatile uint32_t  RTCOR;                                  /*  RTCOR           */
+    volatile uint8_t   dummy6[4];                              /*                  */
+#define BSC_TOSCORn_COUNT 6
+    volatile uint32_t  TOSCOR0;                                /*  TOSCOR0         */
+    volatile uint32_t  TOSCOR1;                                /*  TOSCOR1         */
+    volatile uint32_t  TOSCOR2;                                /*  TOSCOR2         */
+    volatile uint32_t  TOSCOR3;                                /*  TOSCOR3         */
+    volatile uint32_t  TOSCOR4;                                /*  TOSCOR4         */
+    volatile uint32_t  TOSCOR5;                                /*  TOSCOR5         */
+    volatile uint8_t   dummy7[8];                              /*                  */
+    volatile uint32_t  TOSTR;                                  /*  TOSTR           */
+    volatile uint32_t  TOENR;                                  /*  TOENR           */
+};
+
+
+#define BSC     (*(struct st_bsc     *)0x3FFFC000uL) /* BSC */
+
+
+#define BSCCMNCR BSC.CMNCR
+#define BSCCS0BCR BSC.CS0BCR
+#define BSCCS1BCR BSC.CS1BCR
+#define BSCCS2BCR BSC.CS2BCR
+#define BSCCS3BCR BSC.CS3BCR
+#define BSCCS4BCR BSC.CS4BCR
+#define BSCCS5BCR BSC.CS5BCR
+#define BSCCS0WCR BSC.CS0WCR
+#define BSCCS1WCR BSC.CS1WCR
+#define BSCCS2WCR BSC.CS2WCR
+#define BSCCS3WCR BSC.CS3WCR
+#define BSCCS4WCR BSC.CS4WCR
+#define BSCCS5WCR BSC.CS5WCR
+#define BSCSDCR BSC.SDCR
+#define BSCRTCSR BSC.RTCSR
+#define BSCRTCNT BSC.RTCNT
+#define BSCRTCOR BSC.RTCOR
+#define BSCTOSCOR0 BSC.TOSCOR0
+#define BSCTOSCOR1 BSC.TOSCOR1
+#define BSCTOSCOR2 BSC.TOSCOR2
+#define BSCTOSCOR3 BSC.TOSCOR3
+#define BSCTOSCOR4 BSC.TOSCOR4
+#define BSCTOSCOR5 BSC.TOSCOR5
+#define BSCTOSTR BSC.TOSTR
+#define BSCTOENR BSC.TOENR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ceu_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,270 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ceu_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef CEU_IODEFINE_H
+#define CEU_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ceu
+{                                                          /* CEU              */
+/* start of struct st_ceu_n */
+    volatile uint32_t  CAPSR;                                  /*  CAPSR           */
+    volatile uint32_t  CAPCR;                                  /*  CAPCR           */
+    volatile uint32_t  CAMCR;                                  /*  CAMCR           */
+    volatile uint32_t  CMCYR;                                  /*  CMCYR           */
+    volatile uint32_t  CAMOR_A;                                /*  CAMOR_A         */
+    volatile uint32_t  CAPWR_A;                                /*  CAPWR_A         */
+    volatile uint32_t  CAIFR;                                  /*  CAIFR           */
+    volatile uint8_t   dummy305[12];                           /*                  */
+    volatile uint32_t  CRCNTR;                                 /*  CRCNTR          */
+    volatile uint32_t  CRCMPR;                                 /*  CRCMPR          */
+    volatile uint32_t  CFLCR_A;                                /*  CFLCR_A         */
+    volatile uint32_t  CFSZR_A;                                /*  CFSZR_A         */
+    volatile uint32_t  CDWDR_A;                                /*  CDWDR_A         */
+    volatile uint32_t  CDAYR_A;                                /*  CDAYR_A         */
+    volatile uint32_t  CDACR_A;                                /*  CDACR_A         */
+    volatile uint32_t  CDBYR_A;                                /*  CDBYR_A         */
+    volatile uint32_t  CDBCR_A;                                /*  CDBCR_A         */
+    volatile uint32_t  CBDSR_A;                                /*  CBDSR_A         */
+    volatile uint8_t   dummy306[12];                           /*                  */
+    volatile uint32_t  CFWCR;                                  /*  CFWCR           */
+    volatile uint32_t  CLFCR_A;                                /*  CLFCR_A         */
+    volatile uint32_t  CDOCR_A;                                /*  CDOCR_A         */
+    volatile uint8_t   dummy307[8];                            /*                  */
+    volatile uint32_t  CEIER;                                  /*  CEIER           */
+    volatile uint32_t  CETCR;                                  /*  CETCR           */
+    volatile uint8_t   dummy308[4];                            /*                  */
+    volatile uint32_t  CSTSR;                                  /*  CSTSR           */
+    volatile uint8_t   dummy309[4];                            /*                  */
+    volatile uint32_t  CDSSR;                                  /*  CDSSR           */
+    volatile uint8_t   dummy310[8];                            /*                  */
+    volatile uint32_t  CDAYR2_A;                               /*  CDAYR2_A        */
+    volatile uint32_t  CDACR2_A;                               /*  CDACR2_A        */
+    volatile uint32_t  CDBYR2_A;                               /*  CDBYR2_A        */
+    volatile uint32_t  CDBCR2_A;                               /*  CDBCR2_A        */
+/* end of struct st_ceu_n */
+    volatile uint8_t   dummy3110[3936];                        /*                  */
+/* start of struct st_ceu_n */
+    volatile uint8_t   dummy3111[4];                           /*                  */
+    volatile uint8_t   dummy3112[4];                           /*                  */
+    volatile uint8_t   dummy3113[4];                           /*                  */
+    volatile uint8_t   dummy3114[4];                           /*                  */
+    volatile uint32_t  CAMOR_B;                                /*  CAMOR_B         */
+    volatile uint32_t  CAPWR_B;                                /*  CAPWR_B         */
+    volatile uint8_t   dummy3120[4];                           /*                  */
+    volatile uint8_t   dummy3121[12];                          /*                  */
+    volatile uint8_t   dummy3122[4];                           /*                  */
+    volatile uint8_t   dummy3123[4];                           /*                  */
+    volatile uint32_t  CFLCR_B;                                /*  CFLCR_B         */
+    volatile uint32_t  CFSZR_B;                                /*  CFSZR_B         */
+    volatile uint32_t  CDWDR_B;                                /*  CDWDR_B         */
+    volatile uint32_t  CDAYR_B;                                /*  CDAYR_B         */
+    volatile uint32_t  CDACR_B;                                /*  CDACR_B         */
+    volatile uint32_t  CDBYR_B;                                /*  CDBYR_B         */
+    volatile uint32_t  CDBCR_B;                                /*  CDBCR_B         */
+    volatile uint32_t  CBDSR_B;                                /*  CBDSR_B         */
+    volatile uint8_t   dummy3130[12];                          /*                  */
+    volatile uint8_t   dummy3131[4];                           /*                  */
+    volatile uint32_t  CLFCR_B;                                /*  CLFCR_B         */
+    volatile uint32_t  CDOCR_B;                                /*  CDOCR_B         */
+    volatile uint8_t   dummy3140[8];                           /*                  */
+    volatile uint8_t   dummy3141[4];                           /*                  */
+    volatile uint8_t   dummy3142[4];                           /*                  */
+    volatile uint8_t   dummy3143[4];                           /*                  */
+    volatile uint8_t   dummy3144[4];                           /*                  */
+    volatile uint8_t   dummy3145[4];                           /*                  */
+    volatile uint8_t   dummy3146[4];                           /*                  */
+    volatile uint8_t   dummy3147[8];                           /*                  */
+    volatile uint32_t  CDAYR2_B;                               /*  CDAYR2_B        */
+    volatile uint32_t  CDACR2_B;                               /*  CDACR2_B        */
+    volatile uint32_t  CDBYR2_B;                               /*  CDBYR2_B        */
+    volatile uint32_t  CDBCR2_B;                               /*  CDBCR2_B        */
+/* end of struct st_ceu_n */
+    volatile uint8_t   dummy3150[3936];                        /*                  */
+/* start of struct st_ceu_n */
+    volatile uint8_t   dummy3151[4];                           /*                  */
+    volatile uint8_t   dummy3152[4];                           /*                  */
+    volatile uint8_t   dummy3153[4];                           /*                  */
+    volatile uint8_t   dummy3154[4];                           /*                  */
+    volatile uint32_t  CAMOR_M;                                /*  CAMOR_M         */
+    volatile uint32_t  CAPWR_M;                                /*  CAPWR_M         */
+    volatile uint8_t   dummy3160[4];                           /*                  */
+    volatile uint8_t   dummy3161[12];                          /*                  */
+    volatile uint8_t   dummy3162[4];                           /*                  */
+    volatile uint8_t   dummy3163[4];                           /*                  */
+    volatile uint32_t  CFLCR_M;                                /*  CFLCR_M         */
+    volatile uint32_t  CFSZR_M;                                /*  CFSZR_M         */
+    volatile uint32_t  CDWDR_M;                                /*  CDWDR_M         */
+    volatile uint32_t  CDAYR_M;                                /*  CDAYR_M         */
+    volatile uint32_t  CDACR_M;                                /*  CDACR_M         */
+    volatile uint32_t  CDBYR_M;                                /*  CDBYR_M         */
+    volatile uint32_t  CDBCR_M;                                /*  CDBCR_M         */
+    volatile uint32_t  CBDSR_M;                                /*  CBDSR_M         */
+    volatile uint8_t   dummy3170[12];                          /*                  */
+    volatile uint8_t   dummy3171[4];                           /*                  */
+    volatile uint32_t  CLFCR_M;                                /*  CLFCR_M         */
+    volatile uint32_t  CDOCR_M;                                /*  CDOCR_M         */
+    volatile uint8_t   dummy3180[8];                           /*                  */
+    volatile uint8_t   dummy3181[4];                           /*                  */
+    volatile uint8_t   dummy3182[4];                           /*                  */
+    volatile uint8_t   dummy3183[4];                           /*                  */
+    volatile uint8_t   dummy3184[4];                           /*                  */
+    volatile uint8_t   dummy3185[4];                           /*                  */
+    volatile uint8_t   dummy3186[4];                           /*                  */
+    volatile uint8_t   dummy3187[8];                           /*                  */
+    volatile uint32_t  CDAYR2_M;                               /*  CDAYR2_M        */
+    volatile uint32_t  CDACR2_M;                               /*  CDACR2_M        */
+    volatile uint32_t  CDBYR2_M;                               /*  CDBYR2_M        */
+    volatile uint32_t  CDBCR2_M;                               /*  CDBCR2_M        */
+/* end of struct st_ceu_n */
+};
+
+
+struct st_ceu_n
+{
+    volatile uint32_t  not_common1;                            /*                  */
+    volatile uint32_t  not_common2;                            /*                  */
+    volatile uint32_t  not_common3;                            /*                  */
+    volatile uint32_t  not_common4;                            /*                  */
+    volatile uint32_t  CAMOR;                                  /*  CAMOR           */
+    volatile uint32_t  CAPWR;                                  /*  CAPWR           */
+    volatile uint32_t  not_common5;                            /*                  */
+    volatile uint8_t   dummy322[12];                           /*                  */
+    volatile uint32_t  not_common6;                            /*                  */
+    volatile uint32_t  not_common7;                            /*                  */
+    volatile uint32_t  CFLCR;                                  /*  CFLCR           */
+    volatile uint32_t  CFSZR;                                  /*  CFSZR           */
+    volatile uint32_t  CDWDR;                                  /*  CDWDR           */
+    volatile uint32_t  CDAYR;                                  /*  CDAYR           */
+    volatile uint32_t  CDACR;                                  /*  CDACR           */
+    volatile uint32_t  CDBYR;                                  /*  CDBYR           */
+    volatile uint32_t  CDBCR;                                  /*  CDBCR           */
+    volatile uint32_t  CBDSR;                                  /*  CBDSR           */
+    volatile uint8_t   dummy323[12];                           /*                  */
+    volatile uint32_t  not_common8;                            /*                  */
+    volatile uint32_t  CLFCR;                                  /*  CLFCR           */
+    volatile uint32_t  CDOCR;                                  /*  CDOCR           */
+    volatile uint8_t   dummy324[8];                            /*                  */
+    volatile uint32_t  not_common9;                            /*                  */
+    volatile uint32_t  not_common10;                           /*                  */
+    volatile uint8_t   dummy325[4];                            /*                  */
+    volatile uint32_t  not_common11;                           /*                  */
+    volatile uint8_t   dummy326[4];                            /*                  */
+    volatile uint32_t  not_common12;                           /*                  */
+    volatile uint8_t   dummy327[8];                            /*                  */
+    volatile uint32_t  CDAYR2;                                 /*  CDAYR2          */
+    volatile uint32_t  CDACR2;                                 /*  CDACR2          */
+    volatile uint32_t  CDBYR2;                                 /*  CDBYR2          */
+    volatile uint32_t  CDBCR2;                                 /*  CDBCR2          */
+};
+
+
+#define CEU     (*(struct st_ceu     *)0xE8210000uL) /* CEU */
+
+
+/* Start of channnel array defines of CEU */
+
+/* Channnel array defines of CEUn */
+/*(Sample) value = CEUn[ channel ]->CAMOR; */
+#define CEUn_COUNT  3
+#define CEUn_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    (volatile struct st_ceu_n*)&CEU_A, \
+    (volatile struct st_ceu_n*)&CEU_B, \
+    (volatile struct st_ceu_n*)&CEU_M \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CEU_A   (*(struct st_ceu_n *)&CEU.CAPSR)                 /* CEU_A */
+#define CEU_B   (*(struct st_ceu_n *)&CEU.dummy3111)             /* CEU_B */
+#define CEU_M   (*(struct st_ceu_n *)&CEU.dummy3151)             /* CEU_M */
+
+/* End of channnel array defines of CEU */
+
+
+#define CEUCAPSR CEU.CAPSR
+#define CEUCAPCR CEU.CAPCR
+#define CEUCAMCR CEU.CAMCR
+#define CEUCMCYR CEU.CMCYR
+#define CEUCAMOR_A CEU.CAMOR_A
+#define CEUCAPWR_A CEU.CAPWR_A
+#define CEUCAIFR CEU.CAIFR
+#define CEUCRCNTR CEU.CRCNTR
+#define CEUCRCMPR CEU.CRCMPR
+#define CEUCFLCR_A CEU.CFLCR_A
+#define CEUCFSZR_A CEU.CFSZR_A
+#define CEUCDWDR_A CEU.CDWDR_A
+#define CEUCDAYR_A CEU.CDAYR_A
+#define CEUCDACR_A CEU.CDACR_A
+#define CEUCDBYR_A CEU.CDBYR_A
+#define CEUCDBCR_A CEU.CDBCR_A
+#define CEUCBDSR_A CEU.CBDSR_A
+#define CEUCFWCR CEU.CFWCR
+#define CEUCLFCR_A CEU.CLFCR_A
+#define CEUCDOCR_A CEU.CDOCR_A
+#define CEUCEIER CEU.CEIER
+#define CEUCETCR CEU.CETCR
+#define CEUCSTSR CEU.CSTSR
+#define CEUCDSSR CEU.CDSSR
+#define CEUCDAYR2_A CEU.CDAYR2_A
+#define CEUCDACR2_A CEU.CDACR2_A
+#define CEUCDBYR2_A CEU.CDBYR2_A
+#define CEUCDBCR2_A CEU.CDBCR2_A
+#define CEUCAMOR_B CEU.CAMOR_B
+#define CEUCAPWR_B CEU.CAPWR_B
+#define CEUCFLCR_B CEU.CFLCR_B
+#define CEUCFSZR_B CEU.CFSZR_B
+#define CEUCDWDR_B CEU.CDWDR_B
+#define CEUCDAYR_B CEU.CDAYR_B
+#define CEUCDACR_B CEU.CDACR_B
+#define CEUCDBYR_B CEU.CDBYR_B
+#define CEUCDBCR_B CEU.CDBCR_B
+#define CEUCBDSR_B CEU.CBDSR_B
+#define CEUCLFCR_B CEU.CLFCR_B
+#define CEUCDOCR_B CEU.CDOCR_B
+#define CEUCDAYR2_B CEU.CDAYR2_B
+#define CEUCDACR2_B CEU.CDACR2_B
+#define CEUCDBYR2_B CEU.CDBYR2_B
+#define CEUCDBCR2_B CEU.CDBCR2_B
+#define CEUCAMOR_M CEU.CAMOR_M
+#define CEUCAPWR_M CEU.CAPWR_M
+#define CEUCFLCR_M CEU.CFLCR_M
+#define CEUCFSZR_M CEU.CFSZR_M
+#define CEUCDWDR_M CEU.CDWDR_M
+#define CEUCDAYR_M CEU.CDAYR_M
+#define CEUCDACR_M CEU.CDACR_M
+#define CEUCDBYR_M CEU.CDBYR_M
+#define CEUCDBCR_M CEU.CDBCR_M
+#define CEUCBDSR_M CEU.CBDSR_M
+#define CEUCLFCR_M CEU.CLFCR_M
+#define CEUCDOCR_M CEU.CDOCR_M
+#define CEUCDAYR2_M CEU.CDAYR2_M
+#define CEUCDACR2_M CEU.CDACR2_M
+#define CEUCDBYR2_M CEU.CDBYR2_M
+#define CEUCDBCR2_M CEU.CDBCR2_M
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/cpg_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,240 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : cpg_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef CPG_IODEFINE_H
+#define CPG_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_cpg
+{                                                          /* CPG              */
+    volatile uint16_t FRQCR;                                  /*  FRQCR           */
+    volatile uint8_t   dummy319[2];                            /*                  */
+    volatile uint16_t FRQCR2;                                 /*  FRQCR2          */
+    volatile uint8_t   dummy320[2];                            /*                  */
+    volatile uint8_t   CPUSTS;                                 /*  CPUSTS          */
+    volatile uint8_t   dummy321[7];                            /*                  */
+    volatile uint8_t   STBCR1;                                 /*  STBCR1          */
+    volatile uint8_t   dummy322[3];                            /*                  */
+    volatile uint8_t   STBCR2;                                 /*  STBCR2          */
+    volatile uint8_t   dummy323[11];                           /*                  */
+    volatile uint8_t   STBREQ1;                                /*  STBREQ1         */
+    volatile uint8_t   dummy324[3];                            /*                  */
+    volatile uint8_t   STBREQ2;                                /*  STBREQ2         */
+    volatile uint8_t   dummy325[11];                           /*                  */
+    volatile uint8_t   STBACK1;                                /*  STBACK1         */
+    volatile uint8_t   dummy326[3];                            /*                  */
+    volatile uint8_t   STBACK2;                                /*  STBACK2         */
+    volatile uint8_t   dummy327[955];                          /*                  */
+/* start of struct st_cpg_from_syscr1 */
+    volatile uint8_t   SYSCR1;                                 /*  SYSCR1          */
+    volatile uint8_t   dummy328[3];                            /*                  */
+/* end of struct st_cpg_from_syscr1 */
+/* start of struct st_cpg_from_syscr1 */
+    volatile uint8_t   SYSCR2;                                 /*  SYSCR2          */
+    volatile uint8_t   dummy329[3];                            /*                  */
+/* end of struct st_cpg_from_syscr1 */
+/* start of struct st_cpg_from_syscr1 */
+    volatile uint8_t   SYSCR3;                                 /*  SYSCR3          */
+    volatile uint8_t   dummy3300[3];                           /*                  */
+/* end of struct st_cpg_from_syscr1 */
+    volatile uint8_t   dummy3301[20];                          /*                  */
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR3;                                 /*  STBCR3          */
+    volatile uint8_t   dummy331[3];                            /*                  */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR4;                                 /*  STBCR4          */
+    volatile uint8_t   dummy332[3];                            /*                  */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR5;                                 /*  STBCR5          */
+    volatile uint8_t   dummy333[3];                            /*                  */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR6;                                 /*  STBCR6          */
+    volatile uint8_t   dummy334[3];                            /*                  */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR7;                                 /*  STBCR7          */
+    volatile uint8_t   dummy335[3];                            /*                  */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR8;                                 /*  STBCR8          */
+    volatile uint8_t   dummy336[3];                            /*                  */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR9;                                 /*  STBCR9          */
+    volatile uint8_t   dummy337[3];                            /*                  */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR10;                                /*  STBCR10         */
+    volatile uint8_t   dummy338[3];                            /*                  */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR11;                                /*  STBCR11         */
+    volatile uint8_t   dummy339[3];                            /*                  */
+/* end of struct st_cpg_from_stbcr3 */
+/* start of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   STBCR12;                                /*  STBCR12         */
+    volatile uint8_t   dummy3400[3];                           /*                  */
+/* end of struct st_cpg_from_stbcr3 */
+    volatile uint8_t   dummy3401[24];                          /*                  */
+/* start of struct st_cpg_from_swrstcr1 */
+    volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
+    volatile uint8_t   dummy341[3];                            /*                  */
+/* end of struct st_cpg_from_swrstcr1 */
+/* start of struct st_cpg_from_swrstcr1 */
+    volatile uint8_t   SWRSTCR2;                               /*  SWRSTCR2        */
+    volatile uint8_t   dummy342[3];                            /*                  */
+/* end of struct st_cpg_from_swrstcr1 */
+/* start of struct st_cpg_from_swrstcr1 */
+    volatile uint8_t   SWRSTCR3;                               /*  SWRSTCR3        */
+    volatile uint8_t   dummy3430[3];                           /*                  */
+/* end of struct st_cpg_from_swrstcr1 */
+    volatile uint8_t   dummy3431[4];                           /*                  */
+    volatile uint8_t   STBCR13;                                /*  STBCR13         */
+    volatile uint8_t   dummy344[70543];                        /*                  */
+    volatile uint8_t   RRAMKP;                                 /*  RRAMKP          */
+    volatile uint8_t   dummy345[1];                            /*                  */
+    volatile uint8_t   DSCTR;                                  /*  DSCTR           */
+    volatile uint8_t   dummy346[1];                            /*                  */
+    volatile uint16_t DSSSR;                                  /*  DSSSR           */
+    volatile uint16_t DSESR;                                  /*  DSESR           */
+    volatile uint16_t DSFR;                                   /*  DSFR            */
+    volatile uint8_t   dummy347[6];                            /*                  */
+    volatile uint8_t   XTALCTR;                                /*  XTALCTR         */
+};
+
+
+struct st_cpg_from_syscr1
+{
+    volatile uint8_t   SYSCR1;                                 /*  SYSCR1          */
+    volatile uint8_t   dummy1[3];                              /*                  */
+};
+
+
+struct st_cpg_from_stbcr3
+{
+    volatile uint8_t   STBCR3;                                 /*  STBCR3          */
+    volatile uint8_t   dummy1[3];                              /*                  */
+};
+
+
+struct st_cpg_from_swrstcr1
+{
+    volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
+    volatile uint8_t   dummy1[3];                              /*                  */
+};
+
+
+#define CPG     (*(struct st_cpg     *)0xFCFE0010uL) /* CPG */
+
+
+/* Start of channnel array defines of CPG */
+
+/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
+#define CPG_FROM_SWRSTCR1_ARRAY_COUNT  3
+#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
+#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
+#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
+
+
+/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */
+/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
+#define CPG_FROM_STBCR3_ARRAY_COUNT  10
+#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
+    &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
+#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
+#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
+#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
+#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
+#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
+#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
+#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
+#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
+#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
+
+
+/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
+#define CPG_FROM_SYSCR1_ARRAY_COUNT  3
+#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
+#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
+#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
+
+/* End of channnel array defines of CPG */
+
+
+#define CPGFRQCR CPG.FRQCR
+#define CPGFRQCR2 CPG.FRQCR2
+#define CPGCPUSTS CPG.CPUSTS
+#define CPGSTBCR1 CPG.STBCR1
+#define CPGSTBCR2 CPG.STBCR2
+#define CPGSTBREQ1 CPG.STBREQ1
+#define CPGSTBREQ2 CPG.STBREQ2
+#define CPGSTBACK1 CPG.STBACK1
+#define CPGSTBACK2 CPG.STBACK2
+#define CPGSYSCR1 CPG.SYSCR1
+#define CPGSYSCR2 CPG.SYSCR2
+#define CPGSYSCR3 CPG.SYSCR3
+#define CPGSTBCR3 CPG.STBCR3
+#define CPGSTBCR4 CPG.STBCR4
+#define CPGSTBCR5 CPG.STBCR5
+#define CPGSTBCR6 CPG.STBCR6
+#define CPGSTBCR7 CPG.STBCR7
+#define CPGSTBCR8 CPG.STBCR8
+#define CPGSTBCR9 CPG.STBCR9
+#define CPGSTBCR10 CPG.STBCR10
+#define CPGSTBCR11 CPG.STBCR11
+#define CPGSTBCR12 CPG.STBCR12
+#define CPGSWRSTCR1 CPG.SWRSTCR1
+#define CPGSWRSTCR2 CPG.SWRSTCR2
+#define CPGSWRSTCR3 CPG.SWRSTCR3
+#define CPGSTBCR13 CPG.STBCR13
+#define CPGRRAMKP CPG.RRAMKP
+#define CPGDSCTR CPG.DSCTR
+#define CPGDSSSR CPG.DSSSR
+#define CPGDSESR CPG.DSESR
+#define CPGDSFR CPG.DSFR
+#define CPGXTALCTR CPG.XTALCTR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/disc_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,94 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : disc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef DISC_IODEFINE_H
+#define DISC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_disc
+{                                                          /* DISC             */
+    volatile uint32_t  DOCMCR;                                 /*  DOCMCR          */
+    volatile uint32_t  DOCMSTR;                                /*  DOCMSTR         */
+    volatile uint32_t  DOCMCLSTR;                              /*  DOCMCLSTR       */
+    volatile uint32_t  DOCMIENR;                               /*  DOCMIENR        */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint32_t  DOCMPMR;                                /*  DOCMPMR         */
+    volatile uint32_t  DOCMECRCR;                              /*  DOCMECRCR       */
+    volatile uint32_t  DOCMCCRCR;                              /*  DOCMCCRCR       */
+    volatile uint32_t  DOCMSPXR;                               /*  DOCMSPXR        */
+    volatile uint32_t  DOCMSPYR;                               /*  DOCMSPYR        */
+    volatile uint32_t  DOCMSZXR;                               /*  DOCMSZXR        */
+    volatile uint32_t  DOCMSZYR;                               /*  DOCMSZYR        */
+    volatile uint32_t  DOCMCRCIR;                              /*  DOCMCRCIR       */
+};
+
+
+#define DISC0   (*(struct st_disc    *)0xFCFFA800uL) /* DISC0 */
+#define DISC1   (*(struct st_disc    *)0xFCFFB000uL) /* DISC1 */
+
+
+/* Start of channnel array defines of DISC */
+
+/* Channnel array defines of DISC */
+/*(Sample) value = DISC[ channel ]->DOCMCR; */
+#define DISC_COUNT  2
+#define DISC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DISC0, &DISC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of DISC */
+
+
+#define DISC0DOCMCR DISC0.DOCMCR
+#define DISC0DOCMSTR DISC0.DOCMSTR
+#define DISC0DOCMCLSTR DISC0.DOCMCLSTR
+#define DISC0DOCMIENR DISC0.DOCMIENR
+#define DISC0DOCMPMR DISC0.DOCMPMR
+#define DISC0DOCMECRCR DISC0.DOCMECRCR
+#define DISC0DOCMCCRCR DISC0.DOCMCCRCR
+#define DISC0DOCMSPXR DISC0.DOCMSPXR
+#define DISC0DOCMSPYR DISC0.DOCMSPYR
+#define DISC0DOCMSZXR DISC0.DOCMSZXR
+#define DISC0DOCMSZYR DISC0.DOCMSZYR
+#define DISC0DOCMCRCIR DISC0.DOCMCRCIR
+#define DISC1DOCMCR DISC1.DOCMCR
+#define DISC1DOCMSTR DISC1.DOCMSTR
+#define DISC1DOCMCLSTR DISC1.DOCMCLSTR
+#define DISC1DOCMIENR DISC1.DOCMIENR
+#define DISC1DOCMPMR DISC1.DOCMPMR
+#define DISC1DOCMECRCR DISC1.DOCMECRCR
+#define DISC1DOCMCCRCR DISC1.DOCMCCRCR
+#define DISC1DOCMSPXR DISC1.DOCMSPXR
+#define DISC1DOCMSPYR DISC1.DOCMSPYR
+#define DISC1DOCMSZXR DISC1.DOCMSZXR
+#define DISC1DOCMSZYR DISC1.DOCMSZYR
+#define DISC1DOCMCRCIR DISC1.DOCMCRCIR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/dmac_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,734 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : dmac_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef DMAC_IODEFINE_H
+#define DMAC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_dmac
+{                                                          /* DMAC             */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_0;                                 /*  N0SA_0          */
+    volatile uint32_t  N0DA_0;                                 /*  N0DA_0          */
+    volatile uint32_t  N0TB_0;                                 /*  N0TB_0          */
+    volatile uint32_t  N1SA_0;                                 /*  N1SA_0          */
+    volatile uint32_t  N1DA_0;                                 /*  N1DA_0          */
+    volatile uint32_t  N1TB_0;                                 /*  N1TB_0          */
+    volatile uint32_t  CRSA_0;                                 /*  CRSA_0          */
+    volatile uint32_t  CRDA_0;                                 /*  CRDA_0          */
+    volatile uint32_t  CRTB_0;                                 /*  CRTB_0          */
+    volatile uint32_t  CHSTAT_0;                               /*  CHSTAT_0        */
+    volatile uint32_t  CHCTRL_0;                               /*  CHCTRL_0        */
+    volatile uint32_t  CHCFG_0;                                /*  CHCFG_0         */
+    volatile uint32_t  CHITVL_0;                               /*  CHITVL_0        */
+    volatile uint32_t  CHEXT_0;                                /*  CHEXT_0         */
+    volatile uint32_t  NXLA_0;                                 /*  NXLA_0          */
+    volatile uint32_t  CRLA_0;                                 /*  CRLA_0          */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_1;                                 /*  N0SA_1          */
+    volatile uint32_t  N0DA_1;                                 /*  N0DA_1          */
+    volatile uint32_t  N0TB_1;                                 /*  N0TB_1          */
+    volatile uint32_t  N1SA_1;                                 /*  N1SA_1          */
+    volatile uint32_t  N1DA_1;                                 /*  N1DA_1          */
+    volatile uint32_t  N1TB_1;                                 /*  N1TB_1          */
+    volatile uint32_t  CRSA_1;                                 /*  CRSA_1          */
+    volatile uint32_t  CRDA_1;                                 /*  CRDA_1          */
+    volatile uint32_t  CRTB_1;                                 /*  CRTB_1          */
+    volatile uint32_t  CHSTAT_1;                               /*  CHSTAT_1        */
+    volatile uint32_t  CHCTRL_1;                               /*  CHCTRL_1        */
+    volatile uint32_t  CHCFG_1;                                /*  CHCFG_1         */
+    volatile uint32_t  CHITVL_1;                               /*  CHITVL_1        */
+    volatile uint32_t  CHEXT_1;                                /*  CHEXT_1         */
+    volatile uint32_t  NXLA_1;                                 /*  NXLA_1          */
+    volatile uint32_t  CRLA_1;                                 /*  CRLA_1          */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_2;                                 /*  N0SA_2          */
+    volatile uint32_t  N0DA_2;                                 /*  N0DA_2          */
+    volatile uint32_t  N0TB_2;                                 /*  N0TB_2          */
+    volatile uint32_t  N1SA_2;                                 /*  N1SA_2          */
+    volatile uint32_t  N1DA_2;                                 /*  N1DA_2          */
+    volatile uint32_t  N1TB_2;                                 /*  N1TB_2          */
+    volatile uint32_t  CRSA_2;                                 /*  CRSA_2          */
+    volatile uint32_t  CRDA_2;                                 /*  CRDA_2          */
+    volatile uint32_t  CRTB_2;                                 /*  CRTB_2          */
+    volatile uint32_t  CHSTAT_2;                               /*  CHSTAT_2        */
+    volatile uint32_t  CHCTRL_2;                               /*  CHCTRL_2        */
+    volatile uint32_t  CHCFG_2;                                /*  CHCFG_2         */
+    volatile uint32_t  CHITVL_2;                               /*  CHITVL_2        */
+    volatile uint32_t  CHEXT_2;                                /*  CHEXT_2         */
+    volatile uint32_t  NXLA_2;                                 /*  NXLA_2          */
+    volatile uint32_t  CRLA_2;                                 /*  CRLA_2          */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_3;                                 /*  N0SA_3          */
+    volatile uint32_t  N0DA_3;                                 /*  N0DA_3          */
+    volatile uint32_t  N0TB_3;                                 /*  N0TB_3          */
+    volatile uint32_t  N1SA_3;                                 /*  N1SA_3          */
+    volatile uint32_t  N1DA_3;                                 /*  N1DA_3          */
+    volatile uint32_t  N1TB_3;                                 /*  N1TB_3          */
+    volatile uint32_t  CRSA_3;                                 /*  CRSA_3          */
+    volatile uint32_t  CRDA_3;                                 /*  CRDA_3          */
+    volatile uint32_t  CRTB_3;                                 /*  CRTB_3          */
+    volatile uint32_t  CHSTAT_3;                               /*  CHSTAT_3        */
+    volatile uint32_t  CHCTRL_3;                               /*  CHCTRL_3        */
+    volatile uint32_t  CHCFG_3;                                /*  CHCFG_3         */
+    volatile uint32_t  CHITVL_3;                               /*  CHITVL_3        */
+    volatile uint32_t  CHEXT_3;                                /*  CHEXT_3         */
+    volatile uint32_t  NXLA_3;                                 /*  NXLA_3          */
+    volatile uint32_t  CRLA_3;                                 /*  CRLA_3          */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_4;                                 /*  N0SA_4          */
+    volatile uint32_t  N0DA_4;                                 /*  N0DA_4          */
+    volatile uint32_t  N0TB_4;                                 /*  N0TB_4          */
+    volatile uint32_t  N1SA_4;                                 /*  N1SA_4          */
+    volatile uint32_t  N1DA_4;                                 /*  N1DA_4          */
+    volatile uint32_t  N1TB_4;                                 /*  N1TB_4          */
+    volatile uint32_t  CRSA_4;                                 /*  CRSA_4          */
+    volatile uint32_t  CRDA_4;                                 /*  CRDA_4          */
+    volatile uint32_t  CRTB_4;                                 /*  CRTB_4          */
+    volatile uint32_t  CHSTAT_4;                               /*  CHSTAT_4        */
+    volatile uint32_t  CHCTRL_4;                               /*  CHCTRL_4        */
+    volatile uint32_t  CHCFG_4;                                /*  CHCFG_4         */
+    volatile uint32_t  CHITVL_4;                               /*  CHITVL_4        */
+    volatile uint32_t  CHEXT_4;                                /*  CHEXT_4         */
+    volatile uint32_t  NXLA_4;                                 /*  NXLA_4          */
+    volatile uint32_t  CRLA_4;                                 /*  CRLA_4          */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_5;                                 /*  N0SA_5          */
+    volatile uint32_t  N0DA_5;                                 /*  N0DA_5          */
+    volatile uint32_t  N0TB_5;                                 /*  N0TB_5          */
+    volatile uint32_t  N1SA_5;                                 /*  N1SA_5          */
+    volatile uint32_t  N1DA_5;                                 /*  N1DA_5          */
+    volatile uint32_t  N1TB_5;                                 /*  N1TB_5          */
+    volatile uint32_t  CRSA_5;                                 /*  CRSA_5          */
+    volatile uint32_t  CRDA_5;                                 /*  CRDA_5          */
+    volatile uint32_t  CRTB_5;                                 /*  CRTB_5          */
+    volatile uint32_t  CHSTAT_5;                               /*  CHSTAT_5        */
+    volatile uint32_t  CHCTRL_5;                               /*  CHCTRL_5        */
+    volatile uint32_t  CHCFG_5;                                /*  CHCFG_5         */
+    volatile uint32_t  CHITVL_5;                               /*  CHITVL_5        */
+    volatile uint32_t  CHEXT_5;                                /*  CHEXT_5         */
+    volatile uint32_t  NXLA_5;                                 /*  NXLA_5          */
+    volatile uint32_t  CRLA_5;                                 /*  CRLA_5          */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_6;                                 /*  N0SA_6          */
+    volatile uint32_t  N0DA_6;                                 /*  N0DA_6          */
+    volatile uint32_t  N0TB_6;                                 /*  N0TB_6          */
+    volatile uint32_t  N1SA_6;                                 /*  N1SA_6          */
+    volatile uint32_t  N1DA_6;                                 /*  N1DA_6          */
+    volatile uint32_t  N1TB_6;                                 /*  N1TB_6          */
+    volatile uint32_t  CRSA_6;                                 /*  CRSA_6          */
+    volatile uint32_t  CRDA_6;                                 /*  CRDA_6          */
+    volatile uint32_t  CRTB_6;                                 /*  CRTB_6          */
+    volatile uint32_t  CHSTAT_6;                               /*  CHSTAT_6        */
+    volatile uint32_t  CHCTRL_6;                               /*  CHCTRL_6        */
+    volatile uint32_t  CHCFG_6;                                /*  CHCFG_6         */
+    volatile uint32_t  CHITVL_6;                               /*  CHITVL_6        */
+    volatile uint32_t  CHEXT_6;                                /*  CHEXT_6         */
+    volatile uint32_t  NXLA_6;                                 /*  NXLA_6          */
+    volatile uint32_t  CRLA_6;                                 /*  CRLA_6          */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_7;                                 /*  N0SA_7          */
+    volatile uint32_t  N0DA_7;                                 /*  N0DA_7          */
+    volatile uint32_t  N0TB_7;                                 /*  N0TB_7          */
+    volatile uint32_t  N1SA_7;                                 /*  N1SA_7          */
+    volatile uint32_t  N1DA_7;                                 /*  N1DA_7          */
+    volatile uint32_t  N1TB_7;                                 /*  N1TB_7          */
+    volatile uint32_t  CRSA_7;                                 /*  CRSA_7          */
+    volatile uint32_t  CRDA_7;                                 /*  CRDA_7          */
+    volatile uint32_t  CRTB_7;                                 /*  CRTB_7          */
+    volatile uint32_t  CHSTAT_7;                               /*  CHSTAT_7        */
+    volatile uint32_t  CHCTRL_7;                               /*  CHCTRL_7        */
+    volatile uint32_t  CHCFG_7;                                /*  CHCFG_7         */
+    volatile uint32_t  CHITVL_7;                               /*  CHITVL_7        */
+    volatile uint32_t  CHEXT_7;                                /*  CHEXT_7         */
+    volatile uint32_t  NXLA_7;                                 /*  NXLA_7          */
+    volatile uint32_t  CRLA_7;                                 /*  CRLA_7          */
+/* end of struct st_dmac_n */
+    volatile uint8_t   dummy187[256];                          /*                  */
+/* start of struct st_dmaccommon_n */
+    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
+    volatile uint8_t   dummy188[12];                           /*                  */
+    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
+    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
+    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
+    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
+    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
+/* end of struct st_dmaccommon_n */
+    volatile uint8_t   dummy189[220];                          /*                  */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_8;                                 /*  N0SA_8          */
+    volatile uint32_t  N0DA_8;                                 /*  N0DA_8          */
+    volatile uint32_t  N0TB_8;                                 /*  N0TB_8          */
+    volatile uint32_t  N1SA_8;                                 /*  N1SA_8          */
+    volatile uint32_t  N1DA_8;                                 /*  N1DA_8          */
+    volatile uint32_t  N1TB_8;                                 /*  N1TB_8          */
+    volatile uint32_t  CRSA_8;                                 /*  CRSA_8          */
+    volatile uint32_t  CRDA_8;                                 /*  CRDA_8          */
+    volatile uint32_t  CRTB_8;                                 /*  CRTB_8          */
+    volatile uint32_t  CHSTAT_8;                               /*  CHSTAT_8        */
+    volatile uint32_t  CHCTRL_8;                               /*  CHCTRL_8        */
+    volatile uint32_t  CHCFG_8;                                /*  CHCFG_8         */
+    volatile uint32_t  CHITVL_8;                               /*  CHITVL_8        */
+    volatile uint32_t  CHEXT_8;                                /*  CHEXT_8         */
+    volatile uint32_t  NXLA_8;                                 /*  NXLA_8          */
+    volatile uint32_t  CRLA_8;                                 /*  CRLA_8          */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_9;                                 /*  N0SA_9          */
+    volatile uint32_t  N0DA_9;                                 /*  N0DA_9          */
+    volatile uint32_t  N0TB_9;                                 /*  N0TB_9          */
+    volatile uint32_t  N1SA_9;                                 /*  N1SA_9          */
+    volatile uint32_t  N1DA_9;                                 /*  N1DA_9          */
+    volatile uint32_t  N1TB_9;                                 /*  N1TB_9          */
+    volatile uint32_t  CRSA_9;                                 /*  CRSA_9          */
+    volatile uint32_t  CRDA_9;                                 /*  CRDA_9          */
+    volatile uint32_t  CRTB_9;                                 /*  CRTB_9          */
+    volatile uint32_t  CHSTAT_9;                               /*  CHSTAT_9        */
+    volatile uint32_t  CHCTRL_9;                               /*  CHCTRL_9        */
+    volatile uint32_t  CHCFG_9;                                /*  CHCFG_9         */
+    volatile uint32_t  CHITVL_9;                               /*  CHITVL_9        */
+    volatile uint32_t  CHEXT_9;                                /*  CHEXT_9         */
+    volatile uint32_t  NXLA_9;                                 /*  NXLA_9          */
+    volatile uint32_t  CRLA_9;                                 /*  CRLA_9          */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_10;                                /*  N0SA_10         */
+    volatile uint32_t  N0DA_10;                                /*  N0DA_10         */
+    volatile uint32_t  N0TB_10;                                /*  N0TB_10         */
+    volatile uint32_t  N1SA_10;                                /*  N1SA_10         */
+    volatile uint32_t  N1DA_10;                                /*  N1DA_10         */
+    volatile uint32_t  N1TB_10;                                /*  N1TB_10         */
+    volatile uint32_t  CRSA_10;                                /*  CRSA_10         */
+    volatile uint32_t  CRDA_10;                                /*  CRDA_10         */
+    volatile uint32_t  CRTB_10;                                /*  CRTB_10         */
+    volatile uint32_t  CHSTAT_10;                              /*  CHSTAT_10       */
+    volatile uint32_t  CHCTRL_10;                              /*  CHCTRL_10       */
+    volatile uint32_t  CHCFG_10;                               /*  CHCFG_10        */
+    volatile uint32_t  CHITVL_10;                              /*  CHITVL_10       */
+    volatile uint32_t  CHEXT_10;                               /*  CHEXT_10        */
+    volatile uint32_t  NXLA_10;                                /*  NXLA_10         */
+    volatile uint32_t  CRLA_10;                                /*  CRLA_10         */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_11;                                /*  N0SA_11         */
+    volatile uint32_t  N0DA_11;                                /*  N0DA_11         */
+    volatile uint32_t  N0TB_11;                                /*  N0TB_11         */
+    volatile uint32_t  N1SA_11;                                /*  N1SA_11         */
+    volatile uint32_t  N1DA_11;                                /*  N1DA_11         */
+    volatile uint32_t  N1TB_11;                                /*  N1TB_11         */
+    volatile uint32_t  CRSA_11;                                /*  CRSA_11         */
+    volatile uint32_t  CRDA_11;                                /*  CRDA_11         */
+    volatile uint32_t  CRTB_11;                                /*  CRTB_11         */
+    volatile uint32_t  CHSTAT_11;                              /*  CHSTAT_11       */
+    volatile uint32_t  CHCTRL_11;                              /*  CHCTRL_11       */
+    volatile uint32_t  CHCFG_11;                               /*  CHCFG_11        */
+    volatile uint32_t  CHITVL_11;                              /*  CHITVL_11       */
+    volatile uint32_t  CHEXT_11;                               /*  CHEXT_11        */
+    volatile uint32_t  NXLA_11;                                /*  NXLA_11         */
+    volatile uint32_t  CRLA_11;                                /*  CRLA_11         */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_12;                                /*  N0SA_12         */
+    volatile uint32_t  N0DA_12;                                /*  N0DA_12         */
+    volatile uint32_t  N0TB_12;                                /*  N0TB_12         */
+    volatile uint32_t  N1SA_12;                                /*  N1SA_12         */
+    volatile uint32_t  N1DA_12;                                /*  N1DA_12         */
+    volatile uint32_t  N1TB_12;                                /*  N1TB_12         */
+    volatile uint32_t  CRSA_12;                                /*  CRSA_12         */
+    volatile uint32_t  CRDA_12;                                /*  CRDA_12         */
+    volatile uint32_t  CRTB_12;                                /*  CRTB_12         */
+    volatile uint32_t  CHSTAT_12;                              /*  CHSTAT_12       */
+    volatile uint32_t  CHCTRL_12;                              /*  CHCTRL_12       */
+    volatile uint32_t  CHCFG_12;                               /*  CHCFG_12        */
+    volatile uint32_t  CHITVL_12;                              /*  CHITVL_12       */
+    volatile uint32_t  CHEXT_12;                               /*  CHEXT_12        */
+    volatile uint32_t  NXLA_12;                                /*  NXLA_12         */
+    volatile uint32_t  CRLA_12;                                /*  CRLA_12         */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_13;                                /*  N0SA_13         */
+    volatile uint32_t  N0DA_13;                                /*  N0DA_13         */
+    volatile uint32_t  N0TB_13;                                /*  N0TB_13         */
+    volatile uint32_t  N1SA_13;                                /*  N1SA_13         */
+    volatile uint32_t  N1DA_13;                                /*  N1DA_13         */
+    volatile uint32_t  N1TB_13;                                /*  N1TB_13         */
+    volatile uint32_t  CRSA_13;                                /*  CRSA_13         */
+    volatile uint32_t  CRDA_13;                                /*  CRDA_13         */
+    volatile uint32_t  CRTB_13;                                /*  CRTB_13         */
+    volatile uint32_t  CHSTAT_13;                              /*  CHSTAT_13       */
+    volatile uint32_t  CHCTRL_13;                              /*  CHCTRL_13       */
+    volatile uint32_t  CHCFG_13;                               /*  CHCFG_13        */
+    volatile uint32_t  CHITVL_13;                              /*  CHITVL_13       */
+    volatile uint32_t  CHEXT_13;                               /*  CHEXT_13        */
+    volatile uint32_t  NXLA_13;                                /*  NXLA_13         */
+    volatile uint32_t  CRLA_13;                                /*  CRLA_13         */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_14;                                /*  N0SA_14         */
+    volatile uint32_t  N0DA_14;                                /*  N0DA_14         */
+    volatile uint32_t  N0TB_14;                                /*  N0TB_14         */
+    volatile uint32_t  N1SA_14;                                /*  N1SA_14         */
+    volatile uint32_t  N1DA_14;                                /*  N1DA_14         */
+    volatile uint32_t  N1TB_14;                                /*  N1TB_14         */
+    volatile uint32_t  CRSA_14;                                /*  CRSA_14         */
+    volatile uint32_t  CRDA_14;                                /*  CRDA_14         */
+    volatile uint32_t  CRTB_14;                                /*  CRTB_14         */
+    volatile uint32_t  CHSTAT_14;                              /*  CHSTAT_14       */
+    volatile uint32_t  CHCTRL_14;                              /*  CHCTRL_14       */
+    volatile uint32_t  CHCFG_14;                               /*  CHCFG_14        */
+    volatile uint32_t  CHITVL_14;                              /*  CHITVL_14       */
+    volatile uint32_t  CHEXT_14;                               /*  CHEXT_14        */
+    volatile uint32_t  NXLA_14;                                /*  NXLA_14         */
+    volatile uint32_t  CRLA_14;                                /*  CRLA_14         */
+/* end of struct st_dmac_n */
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_15;                                /*  N0SA_15         */
+    volatile uint32_t  N0DA_15;                                /*  N0DA_15         */
+    volatile uint32_t  N0TB_15;                                /*  N0TB_15         */
+    volatile uint32_t  N1SA_15;                                /*  N1SA_15         */
+    volatile uint32_t  N1DA_15;                                /*  N1DA_15         */
+    volatile uint32_t  N1TB_15;                                /*  N1TB_15         */
+    volatile uint32_t  CRSA_15;                                /*  CRSA_15         */
+    volatile uint32_t  CRDA_15;                                /*  CRDA_15         */
+    volatile uint32_t  CRTB_15;                                /*  CRTB_15         */
+    volatile uint32_t  CHSTAT_15;                              /*  CHSTAT_15       */
+    volatile uint32_t  CHCTRL_15;                              /*  CHCTRL_15       */
+    volatile uint32_t  CHCFG_15;                               /*  CHCFG_15        */
+    volatile uint32_t  CHITVL_15;                              /*  CHITVL_15       */
+    volatile uint32_t  CHEXT_15;                               /*  CHEXT_15        */
+    volatile uint32_t  NXLA_15;                                /*  NXLA_15         */
+    volatile uint32_t  CRLA_15;                                /*  CRLA_15         */
+/* end of struct st_dmac_n */
+    volatile uint8_t   dummy190[256];                          /*                  */
+/* start of struct st_dmaccommon_n */
+    volatile uint32_t  DCTRL_8_15;                             /*  DCTRL_8_15      */
+    volatile uint8_t   dummy191[12];                           /*                  */
+    volatile uint32_t  DSTAT_EN_8_15;                          /*  DSTAT_EN_8_15   */
+    volatile uint32_t  DSTAT_ER_8_15;                          /*  DSTAT_ER_8_15   */
+    volatile uint32_t  DSTAT_END_8_15;                         /*  DSTAT_END_8_15  */
+    volatile uint32_t  DSTAT_TC_8_15;                          /*  DSTAT_TC_8_15   */
+    volatile uint32_t  DSTAT_SUS_8_15;                         /*  DSTAT_SUS_8_15  */
+/* end of struct st_dmaccommon_n */
+    volatile uint8_t   dummy192[350095580];                    /*                  */
+    volatile uint32_t  DMARS0;                                 /*  DMARS0          */
+    volatile uint32_t  DMARS1;                                 /*  DMARS1          */
+    volatile uint32_t  DMARS2;                                 /*  DMARS2          */
+    volatile uint32_t  DMARS3;                                 /*  DMARS3          */
+    volatile uint32_t  DMARS4;                                 /*  DMARS4          */
+    volatile uint32_t  DMARS5;                                 /*  DMARS5          */
+    volatile uint32_t  DMARS6;                                 /*  DMARS6          */
+    volatile uint32_t  DMARS7;                                 /*  DMARS7          */
+};
+
+
+struct st_dmaccommon_n
+{
+    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
+    volatile uint8_t   dummy1[12];                             /*                  */
+    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
+    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
+    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
+    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
+    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
+};
+
+
+struct st_dmac_n
+{
+    volatile uint32_t  N0SA_n;                                 /*  N0SA_n          */
+    volatile uint32_t  N0DA_n;                                 /*  N0DA_n          */
+    volatile uint32_t  N0TB_n;                                 /*  N0TB_n          */
+    volatile uint32_t  N1SA_n;                                 /*  N1SA_n          */
+    volatile uint32_t  N1DA_n;                                 /*  N1DA_n          */
+    volatile uint32_t  N1TB_n;                                 /*  N1TB_n          */
+    volatile uint32_t  CRSA_n;                                 /*  CRSA_n          */
+    volatile uint32_t  CRDA_n;                                 /*  CRDA_n          */
+    volatile uint32_t  CRTB_n;                                 /*  CRTB_n          */
+    volatile uint32_t  CHSTAT_n;                               /*  CHSTAT_n        */
+    volatile uint32_t  CHCTRL_n;                               /*  CHCTRL_n        */
+    volatile uint32_t  CHCFG_n;                                /*  CHCFG_n         */
+    volatile uint32_t  CHITVL_n;                               /*  CHITVL_n        */
+    volatile uint32_t  CHEXT_n;                                /*  CHEXT_n         */
+    volatile uint32_t  NXLA_n;                                 /*  NXLA_n          */
+    volatile uint32_t  CRLA_n;                                 /*  CRLA_n          */
+};
+
+
+#define DMAC    (*(struct st_dmac    *)0xE8200000uL) /* DMAC */
+
+
+/* Start of channnel array defines of DMAC */
+
+/* Channnel array defines of DMACn */
+/*(Sample) value = DMACn[ channel ]->N0SA_n; */
+#define DMACn_COUNT  16
+#define DMACn_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \
+    &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC0   (*(struct st_dmac_n *)&DMAC.N0SA_0)              /* DMAC0 */
+#define DMAC1   (*(struct st_dmac_n *)&DMAC.N0SA_1)              /* DMAC1 */
+#define DMAC2   (*(struct st_dmac_n *)&DMAC.N0SA_2)              /* DMAC2 */
+#define DMAC3   (*(struct st_dmac_n *)&DMAC.N0SA_3)              /* DMAC3 */
+#define DMAC4   (*(struct st_dmac_n *)&DMAC.N0SA_4)              /* DMAC4 */
+#define DMAC5   (*(struct st_dmac_n *)&DMAC.N0SA_5)              /* DMAC5 */
+#define DMAC6   (*(struct st_dmac_n *)&DMAC.N0SA_6)              /* DMAC6 */
+#define DMAC7   (*(struct st_dmac_n *)&DMAC.N0SA_7)              /* DMAC7 */
+#define DMAC8   (*(struct st_dmac_n *)&DMAC.N0SA_8)              /* DMAC8 */
+#define DMAC9   (*(struct st_dmac_n *)&DMAC.N0SA_9)              /* DMAC9 */
+#define DMAC10  (*(struct st_dmac_n *)&DMAC.N0SA_10)             /* DMAC10 */
+#define DMAC11  (*(struct st_dmac_n *)&DMAC.N0SA_11)             /* DMAC11 */
+#define DMAC12  (*(struct st_dmac_n *)&DMAC.N0SA_12)             /* DMAC12 */
+#define DMAC13  (*(struct st_dmac_n *)&DMAC.N0SA_13)             /* DMAC13 */
+#define DMAC14  (*(struct st_dmac_n *)&DMAC.N0SA_14)             /* DMAC14 */
+#define DMAC15  (*(struct st_dmac_n *)&DMAC.N0SA_15)             /* DMAC15 */
+
+
+/* Channnel array defines of DMACnn */
+/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */
+#define DMACnn_COUNT  2
+#define DMACnn_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DMAC07, &DMAC815 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC07  (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7)     /* DMAC07 */
+#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15)    /* DMAC815 */
+
+
+/* Channnel array defines of DMACmm */
+/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
+struct st_dmars_mm
+{
+    uint32_t       DMARS;                                        /*  DMARS     */
+};
+#define DMACmm_COUNT  8
+#define DMACmm_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC01    (*(struct st_dmars_mm *)&DMAC.DMARS0)  /* DMAC0-1   */
+#define DMAC23    (*(struct st_dmars_mm *)&DMAC.DMARS1)  /* DMAC2-3   */
+#define DMAC45    (*(struct st_dmars_mm *)&DMAC.DMARS2)  /* DMAC4-5   */
+#define DMAC67    (*(struct st_dmars_mm *)&DMAC.DMARS3)  /* DMAC6-7   */
+#define DMAC89    (*(struct st_dmars_mm *)&DMAC.DMARS4)  /* DMAC8-9   */
+#define DMAC1011  (*(struct st_dmars_mm *)&DMAC.DMARS5)  /* DMAC10-11 */
+#define DMAC1213  (*(struct st_dmars_mm *)&DMAC.DMARS6)  /* DMAC12-13 */
+#define DMAC1415  (*(struct st_dmars_mm *)&DMAC.DMARS7)  /* DMAC14-15 */
+
+/* End of channnel array defines of DMAC */
+
+
+#define DMACN0SA_0 DMAC.N0SA_0
+#define DMACN0DA_0 DMAC.N0DA_0
+#define DMACN0TB_0 DMAC.N0TB_0
+#define DMACN1SA_0 DMAC.N1SA_0
+#define DMACN1DA_0 DMAC.N1DA_0
+#define DMACN1TB_0 DMAC.N1TB_0
+#define DMACCRSA_0 DMAC.CRSA_0
+#define DMACCRDA_0 DMAC.CRDA_0
+#define DMACCRTB_0 DMAC.CRTB_0
+#define DMACCHSTAT_0 DMAC.CHSTAT_0
+#define DMACCHCTRL_0 DMAC.CHCTRL_0
+#define DMACCHCFG_0 DMAC.CHCFG_0
+#define DMACCHITVL_0 DMAC.CHITVL_0
+#define DMACCHEXT_0 DMAC.CHEXT_0
+#define DMACNXLA_0 DMAC.NXLA_0
+#define DMACCRLA_0 DMAC.CRLA_0
+#define DMACN0SA_1 DMAC.N0SA_1
+#define DMACN0DA_1 DMAC.N0DA_1
+#define DMACN0TB_1 DMAC.N0TB_1
+#define DMACN1SA_1 DMAC.N1SA_1
+#define DMACN1DA_1 DMAC.N1DA_1
+#define DMACN1TB_1 DMAC.N1TB_1
+#define DMACCRSA_1 DMAC.CRSA_1
+#define DMACCRDA_1 DMAC.CRDA_1
+#define DMACCRTB_1 DMAC.CRTB_1
+#define DMACCHSTAT_1 DMAC.CHSTAT_1
+#define DMACCHCTRL_1 DMAC.CHCTRL_1
+#define DMACCHCFG_1 DMAC.CHCFG_1
+#define DMACCHITVL_1 DMAC.CHITVL_1
+#define DMACCHEXT_1 DMAC.CHEXT_1
+#define DMACNXLA_1 DMAC.NXLA_1
+#define DMACCRLA_1 DMAC.CRLA_1
+#define DMACN0SA_2 DMAC.N0SA_2
+#define DMACN0DA_2 DMAC.N0DA_2
+#define DMACN0TB_2 DMAC.N0TB_2
+#define DMACN1SA_2 DMAC.N1SA_2
+#define DMACN1DA_2 DMAC.N1DA_2
+#define DMACN1TB_2 DMAC.N1TB_2
+#define DMACCRSA_2 DMAC.CRSA_2
+#define DMACCRDA_2 DMAC.CRDA_2
+#define DMACCRTB_2 DMAC.CRTB_2
+#define DMACCHSTAT_2 DMAC.CHSTAT_2
+#define DMACCHCTRL_2 DMAC.CHCTRL_2
+#define DMACCHCFG_2 DMAC.CHCFG_2
+#define DMACCHITVL_2 DMAC.CHITVL_2
+#define DMACCHEXT_2 DMAC.CHEXT_2
+#define DMACNXLA_2 DMAC.NXLA_2
+#define DMACCRLA_2 DMAC.CRLA_2
+#define DMACN0SA_3 DMAC.N0SA_3
+#define DMACN0DA_3 DMAC.N0DA_3
+#define DMACN0TB_3 DMAC.N0TB_3
+#define DMACN1SA_3 DMAC.N1SA_3
+#define DMACN1DA_3 DMAC.N1DA_3
+#define DMACN1TB_3 DMAC.N1TB_3
+#define DMACCRSA_3 DMAC.CRSA_3
+#define DMACCRDA_3 DMAC.CRDA_3
+#define DMACCRTB_3 DMAC.CRTB_3
+#define DMACCHSTAT_3 DMAC.CHSTAT_3
+#define DMACCHCTRL_3 DMAC.CHCTRL_3
+#define DMACCHCFG_3 DMAC.CHCFG_3
+#define DMACCHITVL_3 DMAC.CHITVL_3
+#define DMACCHEXT_3 DMAC.CHEXT_3
+#define DMACNXLA_3 DMAC.NXLA_3
+#define DMACCRLA_3 DMAC.CRLA_3
+#define DMACN0SA_4 DMAC.N0SA_4
+#define DMACN0DA_4 DMAC.N0DA_4
+#define DMACN0TB_4 DMAC.N0TB_4
+#define DMACN1SA_4 DMAC.N1SA_4
+#define DMACN1DA_4 DMAC.N1DA_4
+#define DMACN1TB_4 DMAC.N1TB_4
+#define DMACCRSA_4 DMAC.CRSA_4
+#define DMACCRDA_4 DMAC.CRDA_4
+#define DMACCRTB_4 DMAC.CRTB_4
+#define DMACCHSTAT_4 DMAC.CHSTAT_4
+#define DMACCHCTRL_4 DMAC.CHCTRL_4
+#define DMACCHCFG_4 DMAC.CHCFG_4
+#define DMACCHITVL_4 DMAC.CHITVL_4
+#define DMACCHEXT_4 DMAC.CHEXT_4
+#define DMACNXLA_4 DMAC.NXLA_4
+#define DMACCRLA_4 DMAC.CRLA_4
+#define DMACN0SA_5 DMAC.N0SA_5
+#define DMACN0DA_5 DMAC.N0DA_5
+#define DMACN0TB_5 DMAC.N0TB_5
+#define DMACN1SA_5 DMAC.N1SA_5
+#define DMACN1DA_5 DMAC.N1DA_5
+#define DMACN1TB_5 DMAC.N1TB_5
+#define DMACCRSA_5 DMAC.CRSA_5
+#define DMACCRDA_5 DMAC.CRDA_5
+#define DMACCRTB_5 DMAC.CRTB_5
+#define DMACCHSTAT_5 DMAC.CHSTAT_5
+#define DMACCHCTRL_5 DMAC.CHCTRL_5
+#define DMACCHCFG_5 DMAC.CHCFG_5
+#define DMACCHITVL_5 DMAC.CHITVL_5
+#define DMACCHEXT_5 DMAC.CHEXT_5
+#define DMACNXLA_5 DMAC.NXLA_5
+#define DMACCRLA_5 DMAC.CRLA_5
+#define DMACN0SA_6 DMAC.N0SA_6
+#define DMACN0DA_6 DMAC.N0DA_6
+#define DMACN0TB_6 DMAC.N0TB_6
+#define DMACN1SA_6 DMAC.N1SA_6
+#define DMACN1DA_6 DMAC.N1DA_6
+#define DMACN1TB_6 DMAC.N1TB_6
+#define DMACCRSA_6 DMAC.CRSA_6
+#define DMACCRDA_6 DMAC.CRDA_6
+#define DMACCRTB_6 DMAC.CRTB_6
+#define DMACCHSTAT_6 DMAC.CHSTAT_6
+#define DMACCHCTRL_6 DMAC.CHCTRL_6
+#define DMACCHCFG_6 DMAC.CHCFG_6
+#define DMACCHITVL_6 DMAC.CHITVL_6
+#define DMACCHEXT_6 DMAC.CHEXT_6
+#define DMACNXLA_6 DMAC.NXLA_6
+#define DMACCRLA_6 DMAC.CRLA_6
+#define DMACN0SA_7 DMAC.N0SA_7
+#define DMACN0DA_7 DMAC.N0DA_7
+#define DMACN0TB_7 DMAC.N0TB_7
+#define DMACN1SA_7 DMAC.N1SA_7
+#define DMACN1DA_7 DMAC.N1DA_7
+#define DMACN1TB_7 DMAC.N1TB_7
+#define DMACCRSA_7 DMAC.CRSA_7
+#define DMACCRDA_7 DMAC.CRDA_7
+#define DMACCRTB_7 DMAC.CRTB_7
+#define DMACCHSTAT_7 DMAC.CHSTAT_7
+#define DMACCHCTRL_7 DMAC.CHCTRL_7
+#define DMACCHCFG_7 DMAC.CHCFG_7
+#define DMACCHITVL_7 DMAC.CHITVL_7
+#define DMACCHEXT_7 DMAC.CHEXT_7
+#define DMACNXLA_7 DMAC.NXLA_7
+#define DMACCRLA_7 DMAC.CRLA_7
+#define DMACDCTRL_0_7 DMAC.DCTRL_0_7
+#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7
+#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7
+#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7
+#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7
+#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7
+#define DMACN0SA_8 DMAC.N0SA_8
+#define DMACN0DA_8 DMAC.N0DA_8
+#define DMACN0TB_8 DMAC.N0TB_8
+#define DMACN1SA_8 DMAC.N1SA_8
+#define DMACN1DA_8 DMAC.N1DA_8
+#define DMACN1TB_8 DMAC.N1TB_8
+#define DMACCRSA_8 DMAC.CRSA_8
+#define DMACCRDA_8 DMAC.CRDA_8
+#define DMACCRTB_8 DMAC.CRTB_8
+#define DMACCHSTAT_8 DMAC.CHSTAT_8
+#define DMACCHCTRL_8 DMAC.CHCTRL_8
+#define DMACCHCFG_8 DMAC.CHCFG_8
+#define DMACCHITVL_8 DMAC.CHITVL_8
+#define DMACCHEXT_8 DMAC.CHEXT_8
+#define DMACNXLA_8 DMAC.NXLA_8
+#define DMACCRLA_8 DMAC.CRLA_8
+#define DMACN0SA_9 DMAC.N0SA_9
+#define DMACN0DA_9 DMAC.N0DA_9
+#define DMACN0TB_9 DMAC.N0TB_9
+#define DMACN1SA_9 DMAC.N1SA_9
+#define DMACN1DA_9 DMAC.N1DA_9
+#define DMACN1TB_9 DMAC.N1TB_9
+#define DMACCRSA_9 DMAC.CRSA_9
+#define DMACCRDA_9 DMAC.CRDA_9
+#define DMACCRTB_9 DMAC.CRTB_9
+#define DMACCHSTAT_9 DMAC.CHSTAT_9
+#define DMACCHCTRL_9 DMAC.CHCTRL_9
+#define DMACCHCFG_9 DMAC.CHCFG_9
+#define DMACCHITVL_9 DMAC.CHITVL_9
+#define DMACCHEXT_9 DMAC.CHEXT_9
+#define DMACNXLA_9 DMAC.NXLA_9
+#define DMACCRLA_9 DMAC.CRLA_9
+#define DMACN0SA_10 DMAC.N0SA_10
+#define DMACN0DA_10 DMAC.N0DA_10
+#define DMACN0TB_10 DMAC.N0TB_10
+#define DMACN1SA_10 DMAC.N1SA_10
+#define DMACN1DA_10 DMAC.N1DA_10
+#define DMACN1TB_10 DMAC.N1TB_10
+#define DMACCRSA_10 DMAC.CRSA_10
+#define DMACCRDA_10 DMAC.CRDA_10
+#define DMACCRTB_10 DMAC.CRTB_10
+#define DMACCHSTAT_10 DMAC.CHSTAT_10
+#define DMACCHCTRL_10 DMAC.CHCTRL_10
+#define DMACCHCFG_10 DMAC.CHCFG_10
+#define DMACCHITVL_10 DMAC.CHITVL_10
+#define DMACCHEXT_10 DMAC.CHEXT_10
+#define DMACNXLA_10 DMAC.NXLA_10
+#define DMACCRLA_10 DMAC.CRLA_10
+#define DMACN0SA_11 DMAC.N0SA_11
+#define DMACN0DA_11 DMAC.N0DA_11
+#define DMACN0TB_11 DMAC.N0TB_11
+#define DMACN1SA_11 DMAC.N1SA_11
+#define DMACN1DA_11 DMAC.N1DA_11
+#define DMACN1TB_11 DMAC.N1TB_11
+#define DMACCRSA_11 DMAC.CRSA_11
+#define DMACCRDA_11 DMAC.CRDA_11
+#define DMACCRTB_11 DMAC.CRTB_11
+#define DMACCHSTAT_11 DMAC.CHSTAT_11
+#define DMACCHCTRL_11 DMAC.CHCTRL_11
+#define DMACCHCFG_11 DMAC.CHCFG_11
+#define DMACCHITVL_11 DMAC.CHITVL_11
+#define DMACCHEXT_11 DMAC.CHEXT_11
+#define DMACNXLA_11 DMAC.NXLA_11
+#define DMACCRLA_11 DMAC.CRLA_11
+#define DMACN0SA_12 DMAC.N0SA_12
+#define DMACN0DA_12 DMAC.N0DA_12
+#define DMACN0TB_12 DMAC.N0TB_12
+#define DMACN1SA_12 DMAC.N1SA_12
+#define DMACN1DA_12 DMAC.N1DA_12
+#define DMACN1TB_12 DMAC.N1TB_12
+#define DMACCRSA_12 DMAC.CRSA_12
+#define DMACCRDA_12 DMAC.CRDA_12
+#define DMACCRTB_12 DMAC.CRTB_12
+#define DMACCHSTAT_12 DMAC.CHSTAT_12
+#define DMACCHCTRL_12 DMAC.CHCTRL_12
+#define DMACCHCFG_12 DMAC.CHCFG_12
+#define DMACCHITVL_12 DMAC.CHITVL_12
+#define DMACCHEXT_12 DMAC.CHEXT_12
+#define DMACNXLA_12 DMAC.NXLA_12
+#define DMACCRLA_12 DMAC.CRLA_12
+#define DMACN0SA_13 DMAC.N0SA_13
+#define DMACN0DA_13 DMAC.N0DA_13
+#define DMACN0TB_13 DMAC.N0TB_13
+#define DMACN1SA_13 DMAC.N1SA_13
+#define DMACN1DA_13 DMAC.N1DA_13
+#define DMACN1TB_13 DMAC.N1TB_13
+#define DMACCRSA_13 DMAC.CRSA_13
+#define DMACCRDA_13 DMAC.CRDA_13
+#define DMACCRTB_13 DMAC.CRTB_13
+#define DMACCHSTAT_13 DMAC.CHSTAT_13
+#define DMACCHCTRL_13 DMAC.CHCTRL_13
+#define DMACCHCFG_13 DMAC.CHCFG_13
+#define DMACCHITVL_13 DMAC.CHITVL_13
+#define DMACCHEXT_13 DMAC.CHEXT_13
+#define DMACNXLA_13 DMAC.NXLA_13
+#define DMACCRLA_13 DMAC.CRLA_13
+#define DMACN0SA_14 DMAC.N0SA_14
+#define DMACN0DA_14 DMAC.N0DA_14
+#define DMACN0TB_14 DMAC.N0TB_14
+#define DMACN1SA_14 DMAC.N1SA_14
+#define DMACN1DA_14 DMAC.N1DA_14
+#define DMACN1TB_14 DMAC.N1TB_14
+#define DMACCRSA_14 DMAC.CRSA_14
+#define DMACCRDA_14 DMAC.CRDA_14
+#define DMACCRTB_14 DMAC.CRTB_14
+#define DMACCHSTAT_14 DMAC.CHSTAT_14
+#define DMACCHCTRL_14 DMAC.CHCTRL_14
+#define DMACCHCFG_14 DMAC.CHCFG_14
+#define DMACCHITVL_14 DMAC.CHITVL_14
+#define DMACCHEXT_14 DMAC.CHEXT_14
+#define DMACNXLA_14 DMAC.NXLA_14
+#define DMACCRLA_14 DMAC.CRLA_14
+#define DMACN0SA_15 DMAC.N0SA_15
+#define DMACN0DA_15 DMAC.N0DA_15
+#define DMACN0TB_15 DMAC.N0TB_15
+#define DMACN1SA_15 DMAC.N1SA_15
+#define DMACN1DA_15 DMAC.N1DA_15
+#define DMACN1TB_15 DMAC.N1TB_15
+#define DMACCRSA_15 DMAC.CRSA_15
+#define DMACCRDA_15 DMAC.CRDA_15
+#define DMACCRTB_15 DMAC.CRTB_15
+#define DMACCHSTAT_15 DMAC.CHSTAT_15
+#define DMACCHCTRL_15 DMAC.CHCTRL_15
+#define DMACCHCFG_15 DMAC.CHCFG_15
+#define DMACCHITVL_15 DMAC.CHITVL_15
+#define DMACCHEXT_15 DMAC.CHEXT_15
+#define DMACNXLA_15 DMAC.NXLA_15
+#define DMACCRLA_15 DMAC.CRLA_15
+#define DMACDCTRL_8_15 DMAC.DCTRL_8_15
+#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15
+#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15
+#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15
+#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15
+#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15
+#define DMACDMARS0 DMAC.DMARS0
+#define DMACDMARS1 DMAC.DMARS1
+#define DMACDMARS2 DMAC.DMARS2
+#define DMACDMARS3 DMAC.DMARS3
+#define DMACDMARS4 DMAC.DMARS4
+#define DMACDMARS5 DMAC.DMARS5
+#define DMACDMARS6 DMAC.DMARS6
+#define DMACDMARS7 DMAC.DMARS7
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/dvdec_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,392 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : dvdec_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef DVDEC_IODEFINE_H
+#define DVDEC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_dvdec
+{                                                          /* DVDEC            */
+    volatile uint16_t ADCCR1;                                 /*  ADCCR1          */
+    volatile uint8_t   dummy1[4];                              /*                  */
+#define DVDEC_TGCRn_COUNT 3
+    volatile uint16_t TGCR1;                                  /*  TGCR1           */
+    volatile uint16_t TGCR2;                                  /*  TGCR2           */
+    volatile uint16_t TGCR3;                                  /*  TGCR3           */
+    volatile uint8_t   dummy2[6];                              /*                  */
+#define DVDEC_SYNSCRn_COUNT 5
+    volatile uint16_t SYNSCR1;                                /*  SYNSCR1         */
+    volatile uint16_t SYNSCR2;                                /*  SYNSCR2         */
+    volatile uint16_t SYNSCR3;                                /*  SYNSCR3         */
+    volatile uint16_t SYNSCR4;                                /*  SYNSCR4         */
+    volatile uint16_t SYNSCR5;                                /*  SYNSCR5         */
+#define DVDEC_HAFCCRn_COUNT 3
+    volatile uint16_t HAFCCR1;                                /*  HAFCCR1         */
+    volatile uint16_t HAFCCR2;                                /*  HAFCCR2         */
+    volatile uint16_t HAFCCR3;                                /*  HAFCCR3         */
+    volatile uint16_t VCDWCR1;                                /*  VCDWCR1         */
+    volatile uint8_t   dummy3[4];                              /*                  */
+#define DVDEC_DCPCRn_COUNT 8
+    volatile uint16_t DCPCR1;                                 /*  DCPCR1          */
+    volatile uint16_t DCPCR2;                                 /*  DCPCR2          */
+    volatile uint16_t DCPCR3;                                 /*  DCPCR3          */
+    volatile uint16_t DCPCR4;                                 /*  DCPCR4          */
+    volatile uint16_t DCPCR5;                                 /*  DCPCR5          */
+    volatile uint16_t DCPCR6;                                 /*  DCPCR6          */
+    volatile uint16_t DCPCR7;                                 /*  DCPCR7          */
+    volatile uint16_t DCPCR8;                                 /*  DCPCR8          */
+    volatile uint16_t NSDCR;                                  /*  NSDCR           */
+    volatile uint16_t BTLCR;                                  /*  BTLCR           */
+    volatile uint16_t BTGPCR;                                 /*  BTGPCR          */
+#define DVDEC_ACCCRn_COUNT 3
+    volatile uint16_t ACCCR1;                                 /*  ACCCR1          */
+    volatile uint16_t ACCCR2;                                 /*  ACCCR2          */
+    volatile uint16_t ACCCR3;                                 /*  ACCCR3          */
+    volatile uint16_t TINTCR;                                 /*  TINTCR          */
+    volatile uint16_t YCDCR;                                  /*  YCDCR           */
+#define DVDEC_AGCCRn_COUNT 2
+    volatile uint16_t AGCCR1;                                 /*  AGCCR1          */
+    volatile uint16_t AGCCR2;                                 /*  AGCCR2          */
+    volatile uint16_t PKLIMITCR;                              /*  PKLIMITCR       */
+#define DVDEC_RGORCRn_COUNT 7
+    volatile uint16_t RGORCR1;                                /*  RGORCR1         */
+    volatile uint16_t RGORCR2;                                /*  RGORCR2         */
+    volatile uint16_t RGORCR3;                                /*  RGORCR3         */
+    volatile uint16_t RGORCR4;                                /*  RGORCR4         */
+    volatile uint16_t RGORCR5;                                /*  RGORCR5         */
+    volatile uint16_t RGORCR6;                                /*  RGORCR6         */
+    volatile uint16_t RGORCR7;                                /*  RGORCR7         */
+    volatile uint8_t   dummy4[24];                             /*                  */
+    volatile uint16_t AFCPFCR;                                /*  AFCPFCR         */
+    volatile uint16_t RUPDCR;                                 /*  RUPDCR          */
+    volatile uint16_t VSYNCSR;                                /*  VSYNCSR         */
+    volatile uint16_t HSYNCSR;                                /*  HSYNCSR         */
+#define DVDEC_DCPSRn_COUNT 2
+    volatile uint16_t DCPSR1;                                 /*  DCPSR1          */
+    volatile uint16_t DCPSR2;                                 /*  DCPSR2          */
+    volatile uint8_t   dummy5[4];                              /*                  */
+    volatile uint16_t NSDSR;                                  /*  NSDSR           */
+#define DVDEC_CROMASRn_COUNT 2
+    volatile uint16_t CROMASR1;                               /*  CROMASR1        */
+    volatile uint16_t CROMASR2;                               /*  CROMASR2        */
+    volatile uint16_t SYNCSSR;                                /*  SYNCSSR         */
+#define DVDEC_AGCCSRn_COUNT 2
+    volatile uint16_t AGCCSR1;                                /*  AGCCSR1         */
+    volatile uint16_t AGCCSR2;                                /*  AGCCSR2         */
+    volatile uint8_t   dummy6[108];                            /*                  */
+#define DVDEC_YCSCRn_COUNT 7
+    volatile uint16_t YCSCR3;                                 /*  YCSCR3          */
+    volatile uint16_t YCSCR4;                                 /*  YCSCR4          */
+    volatile uint16_t YCSCR5;                                 /*  YCSCR5          */
+    volatile uint16_t YCSCR6;                                 /*  YCSCR6          */
+    volatile uint16_t YCSCR7;                                 /*  YCSCR7          */
+    volatile uint16_t YCSCR8;                                 /*  YCSCR8          */
+    volatile uint16_t YCSCR9;                                 /*  YCSCR9          */
+    volatile uint8_t   dummy7[2];                              /*                  */
+    volatile uint16_t YCSCR11;                                /*  YCSCR11         */
+    volatile uint16_t YCSCR12;                                /*  YCSCR12         */
+    volatile uint8_t   dummy8[104];                            /*                  */
+    volatile uint16_t DCPCR9;                                 /*  DCPCR9          */
+    volatile uint8_t   dummy9[16];                             /*                  */
+#define DVDEC_YCTWA_Fn_COUNT 9
+    volatile uint16_t YCTWA_F0;                               /*  YCTWA_F0        */
+    volatile uint16_t YCTWA_F1;                               /*  YCTWA_F1        */
+    volatile uint16_t YCTWA_F2;                               /*  YCTWA_F2        */
+    volatile uint16_t YCTWA_F3;                               /*  YCTWA_F3        */
+    volatile uint16_t YCTWA_F4;                               /*  YCTWA_F4        */
+    volatile uint16_t YCTWA_F5;                               /*  YCTWA_F5        */
+    volatile uint16_t YCTWA_F6;                               /*  YCTWA_F6        */
+    volatile uint16_t YCTWA_F7;                               /*  YCTWA_F7        */
+    volatile uint16_t YCTWA_F8;                               /*  YCTWA_F8        */
+#define DVDEC_YCTWB_Fn_COUNT 9
+    volatile uint16_t YCTWB_F0;                               /*  YCTWB_F0        */
+    volatile uint16_t YCTWB_F1;                               /*  YCTWB_F1        */
+    volatile uint16_t YCTWB_F2;                               /*  YCTWB_F2        */
+    volatile uint16_t YCTWB_F3;                               /*  YCTWB_F3        */
+    volatile uint16_t YCTWB_F4;                               /*  YCTWB_F4        */
+    volatile uint16_t YCTWB_F5;                               /*  YCTWB_F5        */
+    volatile uint16_t YCTWB_F6;                               /*  YCTWB_F6        */
+    volatile uint16_t YCTWB_F7;                               /*  YCTWB_F7        */
+    volatile uint16_t YCTWB_F8;                               /*  YCTWB_F8        */
+#define DVDEC_YCTNA_Fn_COUNT 9
+    volatile uint16_t YCTNA_F0;                               /*  YCTNA_F0        */
+    volatile uint16_t YCTNA_F1;                               /*  YCTNA_F1        */
+    volatile uint16_t YCTNA_F2;                               /*  YCTNA_F2        */
+    volatile uint16_t YCTNA_F3;                               /*  YCTNA_F3        */
+    volatile uint16_t YCTNA_F4;                               /*  YCTNA_F4        */
+    volatile uint16_t YCTNA_F5;                               /*  YCTNA_F5        */
+    volatile uint16_t YCTNA_F6;                               /*  YCTNA_F6        */
+    volatile uint16_t YCTNA_F7;                               /*  YCTNA_F7        */
+    volatile uint16_t YCTNA_F8;                               /*  YCTNA_F8        */
+#define DVDEC_YCTNB_Fn_COUNT 9
+    volatile uint16_t YCTNB_F0;                               /*  YCTNB_F0        */
+    volatile uint16_t YCTNB_F1;                               /*  YCTNB_F1        */
+    volatile uint16_t YCTNB_F2;                               /*  YCTNB_F2        */
+    volatile uint16_t YCTNB_F3;                               /*  YCTNB_F3        */
+    volatile uint16_t YCTNB_F4;                               /*  YCTNB_F4        */
+    volatile uint16_t YCTNB_F5;                               /*  YCTNB_F5        */
+    volatile uint16_t YCTNB_F6;                               /*  YCTNB_F6        */
+    volatile uint16_t YCTNB_F7;                               /*  YCTNB_F7        */
+    volatile uint16_t YCTNB_F8;                               /*  YCTNB_F8        */
+    volatile uint8_t   dummy10[38];                            /*                  */
+    volatile uint16_t YGAINCR;                                /*  YGAINCR         */
+    volatile uint16_t CBGAINCR;                               /*  CBGAINCR        */
+    volatile uint16_t CRGAINCR;                               /*  CRGAINCR        */
+    volatile uint8_t   dummy11[122];                           /*                  */
+    volatile uint16_t PGA_UPDATE;                             /*  PGA_UPDATE      */
+    volatile uint16_t PGACR;                                  /*  PGACR           */
+    volatile uint16_t ADCCR2;                                 /*  ADCCR2          */
+};
+
+
+#define DVDEC1  (*(struct st_dvdec   *)0xFCFFA008uL) /* DVDEC1 */
+#define DVDEC0  (*(struct st_dvdec   *)0xFCFFB808uL) /* DVDEC0 */
+
+
+/* Start of channnel array defines of DVDEC */
+
+/* Channnel array defines of DVDEC */
+/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
+#define DVDEC_COUNT  2
+#define DVDEC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DVDEC0, &DVDEC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of DVDEC */
+
+
+#define ADCCR1_1 DVDEC1.ADCCR1
+#define TGCR1_1 DVDEC1.TGCR1
+#define TGCR2_1 DVDEC1.TGCR2
+#define TGCR3_1 DVDEC1.TGCR3
+#define SYNSCR1_1 DVDEC1.SYNSCR1
+#define SYNSCR2_1 DVDEC1.SYNSCR2
+#define SYNSCR3_1 DVDEC1.SYNSCR3
+#define SYNSCR4_1 DVDEC1.SYNSCR4
+#define SYNSCR5_1 DVDEC1.SYNSCR5
+#define HAFCCR1_1 DVDEC1.HAFCCR1
+#define HAFCCR2_1 DVDEC1.HAFCCR2
+#define HAFCCR3_1 DVDEC1.HAFCCR3
+#define VCDWCR1_1 DVDEC1.VCDWCR1
+#define DCPCR1_1 DVDEC1.DCPCR1
+#define DCPCR2_1 DVDEC1.DCPCR2
+#define DCPCR3_1 DVDEC1.DCPCR3
+#define DCPCR4_1 DVDEC1.DCPCR4
+#define DCPCR5_1 DVDEC1.DCPCR5
+#define DCPCR6_1 DVDEC1.DCPCR6
+#define DCPCR7_1 DVDEC1.DCPCR7
+#define DCPCR8_1 DVDEC1.DCPCR8
+#define NSDCR_1 DVDEC1.NSDCR
+#define BTLCR_1 DVDEC1.BTLCR
+#define BTGPCR_1 DVDEC1.BTGPCR
+#define ACCCR1_1 DVDEC1.ACCCR1
+#define ACCCR2_1 DVDEC1.ACCCR2
+#define ACCCR3_1 DVDEC1.ACCCR3
+#define TINTCR_1 DVDEC1.TINTCR
+#define YCDCR_1 DVDEC1.YCDCR
+#define AGCCR1_1 DVDEC1.AGCCR1
+#define AGCCR2_1 DVDEC1.AGCCR2
+#define PKLIMITCR_1 DVDEC1.PKLIMITCR
+#define RGORCR1_1 DVDEC1.RGORCR1
+#define RGORCR2_1 DVDEC1.RGORCR2
+#define RGORCR3_1 DVDEC1.RGORCR3
+#define RGORCR4_1 DVDEC1.RGORCR4
+#define RGORCR5_1 DVDEC1.RGORCR5
+#define RGORCR6_1 DVDEC1.RGORCR6
+#define RGORCR7_1 DVDEC1.RGORCR7
+#define AFCPFCR_1 DVDEC1.AFCPFCR
+#define RUPDCR_1 DVDEC1.RUPDCR
+#define VSYNCSR_1 DVDEC1.VSYNCSR
+#define HSYNCSR_1 DVDEC1.HSYNCSR
+#define DCPSR1_1 DVDEC1.DCPSR1
+#define DCPSR2_1 DVDEC1.DCPSR2
+#define NSDSR_1 DVDEC1.NSDSR
+#define CROMASR1_1 DVDEC1.CROMASR1
+#define CROMASR2_1 DVDEC1.CROMASR2
+#define SYNCSSR_1 DVDEC1.SYNCSSR
+#define AGCCSR1_1 DVDEC1.AGCCSR1
+#define AGCCSR2_1 DVDEC1.AGCCSR2
+#define YCSCR3_1 DVDEC1.YCSCR3
+#define YCSCR4_1 DVDEC1.YCSCR4
+#define YCSCR5_1 DVDEC1.YCSCR5
+#define YCSCR6_1 DVDEC1.YCSCR6
+#define YCSCR7_1 DVDEC1.YCSCR7
+#define YCSCR8_1 DVDEC1.YCSCR8
+#define YCSCR9_1 DVDEC1.YCSCR9
+#define YCSCR11_1 DVDEC1.YCSCR11
+#define YCSCR12_1 DVDEC1.YCSCR12
+#define DCPCR9_1 DVDEC1.DCPCR9
+#define YCTWA_F0_1 DVDEC1.YCTWA_F0
+#define YCTWA_F1_1 DVDEC1.YCTWA_F1
+#define YCTWA_F2_1 DVDEC1.YCTWA_F2
+#define YCTWA_F3_1 DVDEC1.YCTWA_F3
+#define YCTWA_F4_1 DVDEC1.YCTWA_F4
+#define YCTWA_F5_1 DVDEC1.YCTWA_F5
+#define YCTWA_F6_1 DVDEC1.YCTWA_F6
+#define YCTWA_F7_1 DVDEC1.YCTWA_F7
+#define YCTWA_F8_1 DVDEC1.YCTWA_F8
+#define YCTWB_F0_1 DVDEC1.YCTWB_F0
+#define YCTWB_F1_1 DVDEC1.YCTWB_F1
+#define YCTWB_F2_1 DVDEC1.YCTWB_F2
+#define YCTWB_F3_1 DVDEC1.YCTWB_F3
+#define YCTWB_F4_1 DVDEC1.YCTWB_F4
+#define YCTWB_F5_1 DVDEC1.YCTWB_F5
+#define YCTWB_F6_1 DVDEC1.YCTWB_F6
+#define YCTWB_F7_1 DVDEC1.YCTWB_F7
+#define YCTWB_F8_1 DVDEC1.YCTWB_F8
+#define YCTNA_F0_1 DVDEC1.YCTNA_F0
+#define YCTNA_F1_1 DVDEC1.YCTNA_F1
+#define YCTNA_F2_1 DVDEC1.YCTNA_F2
+#define YCTNA_F3_1 DVDEC1.YCTNA_F3
+#define YCTNA_F4_1 DVDEC1.YCTNA_F4
+#define YCTNA_F5_1 DVDEC1.YCTNA_F5
+#define YCTNA_F6_1 DVDEC1.YCTNA_F6
+#define YCTNA_F7_1 DVDEC1.YCTNA_F7
+#define YCTNA_F8_1 DVDEC1.YCTNA_F8
+#define YCTNB_F0_1 DVDEC1.YCTNB_F0
+#define YCTNB_F1_1 DVDEC1.YCTNB_F1
+#define YCTNB_F2_1 DVDEC1.YCTNB_F2
+#define YCTNB_F3_1 DVDEC1.YCTNB_F3
+#define YCTNB_F4_1 DVDEC1.YCTNB_F4
+#define YCTNB_F5_1 DVDEC1.YCTNB_F5
+#define YCTNB_F6_1 DVDEC1.YCTNB_F6
+#define YCTNB_F7_1 DVDEC1.YCTNB_F7
+#define YCTNB_F8_1 DVDEC1.YCTNB_F8
+#define YGAINCR_1 DVDEC1.YGAINCR
+#define CBGAINCR_1 DVDEC1.CBGAINCR
+#define CRGAINCR_1 DVDEC1.CRGAINCR
+#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE
+#define PGACR_1 DVDEC1.PGACR
+#define ADCCR2_1 DVDEC1.ADCCR2
+#define ADCCR1_0 DVDEC0.ADCCR1
+#define TGCR1_0 DVDEC0.TGCR1
+#define TGCR2_0 DVDEC0.TGCR2
+#define TGCR3_0 DVDEC0.TGCR3
+#define SYNSCR1_0 DVDEC0.SYNSCR1
+#define SYNSCR2_0 DVDEC0.SYNSCR2
+#define SYNSCR3_0 DVDEC0.SYNSCR3
+#define SYNSCR4_0 DVDEC0.SYNSCR4
+#define SYNSCR5_0 DVDEC0.SYNSCR5
+#define HAFCCR1_0 DVDEC0.HAFCCR1
+#define HAFCCR2_0 DVDEC0.HAFCCR2
+#define HAFCCR3_0 DVDEC0.HAFCCR3
+#define VCDWCR1_0 DVDEC0.VCDWCR1
+#define DCPCR1_0 DVDEC0.DCPCR1
+#define DCPCR2_0 DVDEC0.DCPCR2
+#define DCPCR3_0 DVDEC0.DCPCR3
+#define DCPCR4_0 DVDEC0.DCPCR4
+#define DCPCR5_0 DVDEC0.DCPCR5
+#define DCPCR6_0 DVDEC0.DCPCR6
+#define DCPCR7_0 DVDEC0.DCPCR7
+#define DCPCR8_0 DVDEC0.DCPCR8
+#define NSDCR_0 DVDEC0.NSDCR
+#define BTLCR_0 DVDEC0.BTLCR
+#define BTGPCR_0 DVDEC0.BTGPCR
+#define ACCCR1_0 DVDEC0.ACCCR1
+#define ACCCR2_0 DVDEC0.ACCCR2
+#define ACCCR3_0 DVDEC0.ACCCR3
+#define TINTCR_0 DVDEC0.TINTCR
+#define YCDCR_0 DVDEC0.YCDCR
+#define AGCCR1_0 DVDEC0.AGCCR1
+#define AGCCR2_0 DVDEC0.AGCCR2
+#define PKLIMITCR_0 DVDEC0.PKLIMITCR
+#define RGORCR1_0 DVDEC0.RGORCR1
+#define RGORCR2_0 DVDEC0.RGORCR2
+#define RGORCR3_0 DVDEC0.RGORCR3
+#define RGORCR4_0 DVDEC0.RGORCR4
+#define RGORCR5_0 DVDEC0.RGORCR5
+#define RGORCR6_0 DVDEC0.RGORCR6
+#define RGORCR7_0 DVDEC0.RGORCR7
+#define AFCPFCR_0 DVDEC0.AFCPFCR
+#define RUPDCR_0 DVDEC0.RUPDCR
+#define VSYNCSR_0 DVDEC0.VSYNCSR
+#define HSYNCSR_0 DVDEC0.HSYNCSR
+#define DCPSR1_0 DVDEC0.DCPSR1
+#define DCPSR2_0 DVDEC0.DCPSR2
+#define NSDSR_0 DVDEC0.NSDSR
+#define CROMASR1_0 DVDEC0.CROMASR1
+#define CROMASR2_0 DVDEC0.CROMASR2
+#define SYNCSSR_0 DVDEC0.SYNCSSR
+#define AGCCSR1_0 DVDEC0.AGCCSR1
+#define AGCCSR2_0 DVDEC0.AGCCSR2
+#define YCSCR3_0 DVDEC0.YCSCR3
+#define YCSCR4_0 DVDEC0.YCSCR4
+#define YCSCR5_0 DVDEC0.YCSCR5
+#define YCSCR6_0 DVDEC0.YCSCR6
+#define YCSCR7_0 DVDEC0.YCSCR7
+#define YCSCR8_0 DVDEC0.YCSCR8
+#define YCSCR9_0 DVDEC0.YCSCR9
+#define YCSCR11_0 DVDEC0.YCSCR11
+#define YCSCR12_0 DVDEC0.YCSCR12
+#define DCPCR9_0 DVDEC0.DCPCR9
+#define YCTWA_F0_0 DVDEC0.YCTWA_F0
+#define YCTWA_F1_0 DVDEC0.YCTWA_F1
+#define YCTWA_F2_0 DVDEC0.YCTWA_F2
+#define YCTWA_F3_0 DVDEC0.YCTWA_F3
+#define YCTWA_F4_0 DVDEC0.YCTWA_F4
+#define YCTWA_F5_0 DVDEC0.YCTWA_F5
+#define YCTWA_F6_0 DVDEC0.YCTWA_F6
+#define YCTWA_F7_0 DVDEC0.YCTWA_F7
+#define YCTWA_F8_0 DVDEC0.YCTWA_F8
+#define YCTWB_F0_0 DVDEC0.YCTWB_F0
+#define YCTWB_F1_0 DVDEC0.YCTWB_F1
+#define YCTWB_F2_0 DVDEC0.YCTWB_F2
+#define YCTWB_F3_0 DVDEC0.YCTWB_F3
+#define YCTWB_F4_0 DVDEC0.YCTWB_F4
+#define YCTWB_F5_0 DVDEC0.YCTWB_F5
+#define YCTWB_F6_0 DVDEC0.YCTWB_F6
+#define YCTWB_F7_0 DVDEC0.YCTWB_F7
+#define YCTWB_F8_0 DVDEC0.YCTWB_F8
+#define YCTNA_F0_0 DVDEC0.YCTNA_F0
+#define YCTNA_F1_0 DVDEC0.YCTNA_F1
+#define YCTNA_F2_0 DVDEC0.YCTNA_F2
+#define YCTNA_F3_0 DVDEC0.YCTNA_F3
+#define YCTNA_F4_0 DVDEC0.YCTNA_F4
+#define YCTNA_F5_0 DVDEC0.YCTNA_F5
+#define YCTNA_F6_0 DVDEC0.YCTNA_F6
+#define YCTNA_F7_0 DVDEC0.YCTNA_F7
+#define YCTNA_F8_0 DVDEC0.YCTNA_F8
+#define YCTNB_F0_0 DVDEC0.YCTNB_F0
+#define YCTNB_F1_0 DVDEC0.YCTNB_F1
+#define YCTNB_F2_0 DVDEC0.YCTNB_F2
+#define YCTNB_F3_0 DVDEC0.YCTNB_F3
+#define YCTNB_F4_0 DVDEC0.YCTNB_F4
+#define YCTNB_F5_0 DVDEC0.YCTNB_F5
+#define YCTNB_F6_0 DVDEC0.YCTNB_F6
+#define YCTNB_F7_0 DVDEC0.YCTNB_F7
+#define YCTNB_F8_0 DVDEC0.YCTNB_F8
+#define YGAINCR_0 DVDEC0.YGAINCR
+#define CBGAINCR_0 DVDEC0.CBGAINCR
+#define CRGAINCR_0 DVDEC0.CRGAINCR
+#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE
+#define PGACR_0 DVDEC0.PGACR
+#define ADCCR2_0 DVDEC0.ADCCR2
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ether_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,428 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ether_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef ETHER_IODEFINE_H
+#define ETHER_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ether
+{                                                          /* ETHER            */
+    volatile uint32_t  EDSR0;                                  /*  EDSR0           */
+    volatile uint8_t   dummy207[12];                           /*                  */
+    volatile uint32_t  TDLAR0;                                 /*  TDLAR0          */
+    volatile uint32_t  TDFAR0;                                 /*  TDFAR0          */
+    volatile uint32_t  TDFXR0;                                 /*  TDFXR0          */
+    volatile uint32_t  TDFFR0;                                 /*  TDFFR0          */
+    volatile uint8_t   dummy208[16];                           /*                  */
+    volatile uint32_t  RDLAR0;                                 /*  RDLAR0          */
+    volatile uint32_t  RDFAR0;                                 /*  RDFAR0          */
+    volatile uint32_t  RDFXR0;                                 /*  RDFXR0          */
+    volatile uint32_t  RDFFR0;                                 /*  RDFFR0          */
+    volatile uint8_t   dummy209[960];                          /*                  */
+    volatile uint32_t  EDMR0;                                  /*  EDMR0           */
+    volatile uint8_t   dummy210[4];                            /*                  */
+    volatile uint32_t  EDTRR0;                                 /*  EDTRR0          */
+    volatile uint8_t   dummy211[4];                            /*                  */
+    volatile uint32_t  EDRRR0;                                 /*  EDRRR0          */
+    volatile uint8_t   dummy212[20];                           /*                  */
+    volatile uint32_t  EESR0;                                  /*  EESR0           */
+    volatile uint8_t   dummy213[4];                            /*                  */
+    volatile uint32_t  EESIPR0;                                /*  EESIPR0         */
+    volatile uint8_t   dummy214[4];                            /*                  */
+    volatile uint32_t  TRSCER0;                                /*  TRSCER0         */
+    volatile uint8_t   dummy215[4];                            /*                  */
+    volatile uint32_t  RMFCR0;                                 /*  RMFCR0          */
+    volatile uint8_t   dummy216[4];                            /*                  */
+    volatile uint32_t  TFTR0;                                  /*  TFTR0           */
+    volatile uint8_t   dummy217[4];                            /*                  */
+    volatile uint32_t  FDR0;                                   /*  FDR0            */
+    volatile uint8_t   dummy218[4];                            /*                  */
+    volatile uint32_t  RMCR0;                                  /*  RMCR0           */
+    volatile uint8_t   dummy219[4];                            /*                  */
+    volatile uint32_t  RPADIR0;                                /*  RPADIR0         */
+    volatile uint8_t   dummy220[4];                            /*                  */
+    volatile uint32_t  FCFTR0;                                 /*  FCFTR0          */
+    volatile uint8_t   dummy221[120];                          /*                  */
+    volatile uint32_t  CSMR;                                   /*  CSMR            */
+    volatile uint32_t  CSSBM;                                  /*  CSSBM           */
+    volatile uint32_t  CSSMR;                                  /*  CSSMR           */
+    volatile uint8_t   dummy222[16];                           /*                  */
+    volatile uint32_t  ECMR0;                                  /*  ECMR0           */
+    volatile uint8_t   dummy223[4];                            /*                  */
+    volatile uint32_t  RFLR0;                                  /*  RFLR0           */
+    volatile uint8_t   dummy224[4];                            /*                  */
+    volatile uint32_t  ECSR0;                                  /*  ECSR0           */
+    volatile uint8_t   dummy225[4];                            /*                  */
+    volatile uint32_t  ECSIPR0;                                /*  ECSIPR0         */
+    volatile uint8_t   dummy226[4];                            /*                  */
+    volatile uint32_t  PIR0;                                   /*  PIR0            */
+    volatile uint8_t   dummy227[48];                           /*                  */
+    volatile uint32_t  APR0;                                   /*  APR0            */
+    volatile uint32_t  MPR0;                                   /*  MPR0            */
+    volatile uint32_t  PFTCR0;                                 /*  PFTCR0          */
+    volatile uint32_t  PFRCR0;                                 /*  PFRCR0          */
+    volatile uint32_t  TPAUSER0;                               /*  TPAUSER0        */
+    volatile uint8_t   dummy228[88];                           /*                  */
+    volatile uint32_t  MAHR0;                                  /*  MAHR0           */
+    volatile uint8_t   dummy229[4];                            /*                  */
+    volatile uint32_t  MALR0;                                  /*  MALR0           */
+    volatile uint8_t   dummy230[372];                          /*                  */
+    volatile uint32_t  CEFCR0;                                 /*  CEFCR0          */
+    volatile uint8_t   dummy231[4];                            /*                  */
+    volatile uint32_t  FRECR0;                                 /*  FRECR0          */
+    volatile uint8_t   dummy232[4];                            /*                  */
+    volatile uint32_t  TSFRCR0;                                /*  TSFRCR0         */
+    volatile uint8_t   dummy233[4];                            /*                  */
+    volatile uint32_t  TLFRCR0;                                /*  TLFRCR0         */
+    volatile uint8_t   dummy234[4];                            /*                  */
+    volatile uint32_t  RFCR0;                                  /*  RFCR0           */
+    volatile uint8_t   dummy235[20];                           /*                  */
+    volatile uint32_t  MAFCR0;                                 /*  MAFCR0          */
+    volatile uint8_t   dummy236[4228];                         /*                  */
+    volatile uint32_t  ARSTR;                                  /*  ARSTR           */
+    volatile uint32_t  TSU_CTRST;                              /*  TSU_CTRST       */
+    volatile uint8_t   dummy237[80];                           /*                  */
+    volatile uint32_t  TSU_VTAG0;                              /*  TSU_VTAG0       */
+    volatile uint8_t   dummy238[4];                            /*                  */
+    volatile uint32_t  TSU_ADSBSY;                             /*  TSU_ADSBSY      */
+    volatile uint32_t  TSU_TEN;                                /*  TSU_TEN         */
+    volatile uint8_t   dummy239[24];                           /*                  */
+    volatile uint32_t  TXNLCR0;                                /*  TXNLCR0         */
+    volatile uint32_t  TXALCR0;                                /*  TXALCR0         */
+    volatile uint32_t  RXNLCR0;                                /*  RXNLCR0         */
+    volatile uint32_t  RXALCR0;                                /*  RXALCR0         */
+    volatile uint8_t   dummy240[112];                          /*                  */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
+    volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH1;                              /*  TSU_ADRH1       */
+    volatile uint32_t  TSU_ADRL1;                              /*  TSU_ADRL1       */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH2;                              /*  TSU_ADRH2       */
+    volatile uint32_t  TSU_ADRL2;                              /*  TSU_ADRL2       */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH3;                              /*  TSU_ADRH3       */
+    volatile uint32_t  TSU_ADRL3;                              /*  TSU_ADRL3       */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH4;                              /*  TSU_ADRH4       */
+    volatile uint32_t  TSU_ADRL4;                              /*  TSU_ADRL4       */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH5;                              /*  TSU_ADRH5       */
+    volatile uint32_t  TSU_ADRL5;                              /*  TSU_ADRL5       */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH6;                              /*  TSU_ADRH6       */
+    volatile uint32_t  TSU_ADRL6;                              /*  TSU_ADRL6       */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH7;                              /*  TSU_ADRH7       */
+    volatile uint32_t  TSU_ADRL7;                              /*  TSU_ADRL7       */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH8;                              /*  TSU_ADRH8       */
+    volatile uint32_t  TSU_ADRL8;                              /*  TSU_ADRL8       */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH9;                              /*  TSU_ADRH9       */
+    volatile uint32_t  TSU_ADRL9;                              /*  TSU_ADRL9       */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH10;                             /*  TSU_ADRH10      */
+    volatile uint32_t  TSU_ADRL10;                             /*  TSU_ADRL10      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH11;                             /*  TSU_ADRH11      */
+    volatile uint32_t  TSU_ADRL11;                             /*  TSU_ADRL11      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH12;                             /*  TSU_ADRH12      */
+    volatile uint32_t  TSU_ADRL12;                             /*  TSU_ADRL12      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH13;                             /*  TSU_ADRH13      */
+    volatile uint32_t  TSU_ADRL13;                             /*  TSU_ADRL13      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH14;                             /*  TSU_ADRH14      */
+    volatile uint32_t  TSU_ADRL14;                             /*  TSU_ADRL14      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH15;                             /*  TSU_ADRH15      */
+    volatile uint32_t  TSU_ADRL15;                             /*  TSU_ADRL15      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH16;                             /*  TSU_ADRH16      */
+    volatile uint32_t  TSU_ADRL16;                             /*  TSU_ADRL16      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH17;                             /*  TSU_ADRH17      */
+    volatile uint32_t  TSU_ADRL17;                             /*  TSU_ADRL17      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH18;                             /*  TSU_ADRH18      */
+    volatile uint32_t  TSU_ADRL18;                             /*  TSU_ADRL18      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH19;                             /*  TSU_ADRH19      */
+    volatile uint32_t  TSU_ADRL19;                             /*  TSU_ADRL19      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH20;                             /*  TSU_ADRH20      */
+    volatile uint32_t  TSU_ADRL20;                             /*  TSU_ADRL20      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH21;                             /*  TSU_ADRH21      */
+    volatile uint32_t  TSU_ADRL21;                             /*  TSU_ADRL21      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH22;                             /*  TSU_ADRH22      */
+    volatile uint32_t  TSU_ADRL22;                             /*  TSU_ADRL22      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH23;                             /*  TSU_ADRH23      */
+    volatile uint32_t  TSU_ADRL23;                             /*  TSU_ADRL23      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH24;                             /*  TSU_ADRH24      */
+    volatile uint32_t  TSU_ADRL24;                             /*  TSU_ADRL24      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH25;                             /*  TSU_ADRH25      */
+    volatile uint32_t  TSU_ADRL25;                             /*  TSU_ADRL25      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH26;                             /*  TSU_ADRH26      */
+    volatile uint32_t  TSU_ADRL26;                             /*  TSU_ADRL26      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH27;                             /*  TSU_ADRH27      */
+    volatile uint32_t  TSU_ADRL27;                             /*  TSU_ADRL27      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH28;                             /*  TSU_ADRH28      */
+    volatile uint32_t  TSU_ADRL28;                             /*  TSU_ADRL28      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH29;                             /*  TSU_ADRH29      */
+    volatile uint32_t  TSU_ADRL29;                             /*  TSU_ADRL29      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH30;                             /*  TSU_ADRH30      */
+    volatile uint32_t  TSU_ADRL30;                             /*  TSU_ADRL30      */
+/* end of struct st_ether_from_tsu_adrh0 */
+/* start of struct st_ether_from_tsu_adrh0 */
+    volatile uint32_t  TSU_ADRH31;                             /*  TSU_ADRH31      */
+    volatile uint32_t  TSU_ADRL31;                             /*  TSU_ADRL31      */
+/* end of struct st_ether_from_tsu_adrh0 */
+};
+
+
+struct st_ether_from_tsu_adrh0
+{
+    volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
+    volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
+};
+
+
+#define ETHER   (*(struct st_ether   *)0xE8203000uL) /* ETHER */
+
+
+/* Start of channnel array defines of ETHER */
+
+/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
+/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
+#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT  32
+#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
+    &ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
+    &ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
+    &ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
+#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
+#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
+#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
+#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
+#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
+#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
+#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
+#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
+#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
+#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
+#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
+#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
+#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
+#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
+#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
+#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
+#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
+#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
+#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
+#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
+#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
+#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
+#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
+#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
+#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
+#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
+#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
+#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
+#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
+#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
+#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
+
+/* End of channnel array defines of ETHER */
+
+
+#define ETHEREDSR0 ETHER.EDSR0
+#define ETHERTDLAR0 ETHER.TDLAR0
+#define ETHERTDFAR0 ETHER.TDFAR0
+#define ETHERTDFXR0 ETHER.TDFXR0
+#define ETHERTDFFR0 ETHER.TDFFR0
+#define ETHERRDLAR0 ETHER.RDLAR0
+#define ETHERRDFAR0 ETHER.RDFAR0
+#define ETHERRDFXR0 ETHER.RDFXR0
+#define ETHERRDFFR0 ETHER.RDFFR0
+#define ETHEREDMR0 ETHER.EDMR0
+#define ETHEREDTRR0 ETHER.EDTRR0
+#define ETHEREDRRR0 ETHER.EDRRR0
+#define ETHEREESR0 ETHER.EESR0
+#define ETHEREESIPR0 ETHER.EESIPR0
+#define ETHERTRSCER0 ETHER.TRSCER0
+#define ETHERRMFCR0 ETHER.RMFCR0
+#define ETHERTFTR0 ETHER.TFTR0
+#define ETHERFDR0 ETHER.FDR0
+#define ETHERRMCR0 ETHER.RMCR0
+#define ETHERRPADIR0 ETHER.RPADIR0
+#define ETHERFCFTR0 ETHER.FCFTR0
+#define ETHERCSMR ETHER.CSMR
+#define ETHERCSSBM ETHER.CSSBM
+#define ETHERCSSMR ETHER.CSSMR
+#define ETHERECMR0 ETHER.ECMR0
+#define ETHERRFLR0 ETHER.RFLR0
+#define ETHERECSR0 ETHER.ECSR0
+#define ETHERECSIPR0 ETHER.ECSIPR0
+#define ETHERPIR0 ETHER.PIR0
+#define ETHERAPR0 ETHER.APR0
+#define ETHERMPR0 ETHER.MPR0
+#define ETHERPFTCR0 ETHER.PFTCR0
+#define ETHERPFRCR0 ETHER.PFRCR0
+#define ETHERTPAUSER0 ETHER.TPAUSER0
+#define ETHERMAHR0 ETHER.MAHR0
+#define ETHERMALR0 ETHER.MALR0
+#define ETHERCEFCR0 ETHER.CEFCR0
+#define ETHERFRECR0 ETHER.FRECR0
+#define ETHERTSFRCR0 ETHER.TSFRCR0
+#define ETHERTLFRCR0 ETHER.TLFRCR0
+#define ETHERRFCR0 ETHER.RFCR0
+#define ETHERMAFCR0 ETHER.MAFCR0
+#define ETHERARSTR ETHER.ARSTR
+#define ETHERTSU_CTRST ETHER.TSU_CTRST
+#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0
+#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY
+#define ETHERTSU_TEN ETHER.TSU_TEN
+#define ETHERTXNLCR0 ETHER.TXNLCR0
+#define ETHERTXALCR0 ETHER.TXALCR0
+#define ETHERRXNLCR0 ETHER.RXNLCR0
+#define ETHERRXALCR0 ETHER.RXALCR0
+#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0
+#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0
+#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1
+#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1
+#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2
+#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2
+#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3
+#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3
+#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4
+#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4
+#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5
+#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5
+#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6
+#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6
+#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7
+#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7
+#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8
+#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8
+#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9
+#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9
+#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10
+#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10
+#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11
+#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11
+#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12
+#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12
+#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13
+#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13
+#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14
+#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14
+#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15
+#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15
+#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16
+#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16
+#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17
+#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17
+#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18
+#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18
+#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19
+#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19
+#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20
+#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20
+#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21
+#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21
+#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22
+#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22
+#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23
+#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23
+#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24
+#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24
+#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25
+#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25
+#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26
+#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26
+#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27
+#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27
+#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28
+#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28
+#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29
+#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29
+#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30
+#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30
+#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31
+#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/flctl_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : flctl_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef FLCTL_IODEFINE_H
+#define FLCTL_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_flctl
+{                                                          /* FLCTL            */
+    volatile uint32_t  FLCMNCR;                                /*  FLCMNCR         */
+    volatile uint32_t  FLCMDCR;                                /*  FLCMDCR         */
+    volatile uint32_t  FLCMCDR;                                /*  FLCMCDR         */
+    volatile uint32_t  FLADR;                                  /*  FLADR           */
+    volatile uint32_t  FLDATAR;                                /*  FLDATAR         */
+    volatile uint32_t  FLDTCNTR;                               /*  FLDTCNTR        */
+    volatile uint32_t  FLINTDMACR;                             /*  FLINTDMACR      */
+    volatile uint32_t  FLBSYTMR;                               /*  FLBSYTMR        */
+    volatile uint32_t  FLBSYCNT;                               /*  FLBSYCNT        */
+    volatile uint8_t   dummy555[8];                            /*                  */
+    volatile uint8_t   FLTRCR;                                 /*  FLTRCR          */
+    volatile uint8_t   dummy556[15];                           /*                  */
+    volatile uint32_t  FLADR2;                                 /*  FLADR2          */
+    volatile uint8_t   dummy557[16];                           /*                  */
+    volatile uint32_t  FLDTFIFO;                               /*  FLDTFIFO        */
+    volatile uint8_t   dummy558[12];                           /*                  */
+    volatile uint32_t  FLECFIFO;                               /*  FLECFIFO        */
+};
+
+
+#define FLCTL   (*(struct st_flctl   *)0xFCFF4000uL) /* FLCTL */
+
+
+#define FLCTLFLCMNCR FLCTL.FLCMNCR
+#define FLCTLFLCMDCR FLCTL.FLCMDCR
+#define FLCTLFLCMCDR FLCTL.FLCMCDR
+#define FLCTLFLADR FLCTL.FLADR
+#define FLCTLFLDATAR FLCTL.FLDATAR
+#define FLCTLFLDTCNTR FLCTL.FLDTCNTR
+#define FLCTLFLINTDMACR FLCTL.FLINTDMACR
+#define FLCTLFLBSYTMR FLCTL.FLBSYTMR
+#define FLCTLFLBSYCNT FLCTL.FLBSYCNT
+#define FLCTLFLTRCR FLCTL.FLTRCR
+#define FLCTLFLADR2 FLCTL.FLADR2
+#define FLCTLFLDTFIFO FLCTL.FLDTFIFO
+#define FLCTLFLECFIFO FLCTL.FLECFIFO
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/gpio_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1075 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : gpio_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef GPIO_IODEFINE_H
+#define GPIO_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_gpio
+{                                                          /* GPIO             */
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P1;                                     /*  P1              */
+    volatile uint8_t   dummy348[2];                            /*                  */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P2;                                     /*  P2              */
+    volatile uint8_t   dummy349[2];                            /*                  */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P3;                                     /*  P3              */
+    volatile uint8_t   dummy350[2];                            /*                  */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P4;                                     /*  P4              */
+    volatile uint8_t   dummy351[2];                            /*                  */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P5;                                     /*  P5              */
+    volatile uint8_t   dummy352[2];                            /*                  */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P6;                                     /*  P6              */
+    volatile uint8_t   dummy353[2];                            /*                  */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P7;                                     /*  P7              */
+    volatile uint8_t   dummy354[2];                            /*                  */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P8;                                     /*  P8              */
+    volatile uint8_t   dummy355[2];                            /*                  */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P9;                                     /*  P9              */
+    volatile uint8_t   dummy356[2];                            /*                  */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P10;                                    /*  P10             */
+    volatile uint8_t   dummy357[2];                            /*                  */
+/* end of struct st_gpio_from_p1 */
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P11;                                    /*  P11             */
+    volatile uint8_t   dummy3580[2];                           /*                  */
+/* end of struct st_gpio_from_p1 */
+    volatile uint8_t   dummy3581[212];                         /*                  */
+#define GPIO_PSRn_COUNT 11
+    volatile uint32_t  PSR1;                                   /*  PSR1            */
+    volatile uint32_t  PSR2;                                   /*  PSR2            */
+    volatile uint32_t  PSR3;                                   /*  PSR3            */
+    volatile uint32_t  PSR4;                                   /*  PSR4            */
+    volatile uint32_t  PSR5;                                   /*  PSR5            */
+    volatile uint32_t  PSR6;                                   /*  PSR6            */
+    volatile uint32_t  PSR7;                                   /*  PSR7            */
+    volatile uint32_t  PSR8;                                   /*  PSR8            */
+    volatile uint32_t  PSR9;                                   /*  PSR9            */
+    volatile uint32_t  PSR10;                                  /*  PSR10           */
+    volatile uint32_t  PSR11;                                  /*  PSR11           */
+    volatile uint8_t   dummy359[208];                          /*                  */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR0;                                   /*  PPR0            */
+    volatile uint8_t   dummy360[2];                            /*                  */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR1;                                   /*  PPR1            */
+    volatile uint8_t   dummy361[2];                            /*                  */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR2;                                   /*  PPR2            */
+    volatile uint8_t   dummy362[2];                            /*                  */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR3;                                   /*  PPR3            */
+    volatile uint8_t   dummy363[2];                            /*                  */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR4;                                   /*  PPR4            */
+    volatile uint8_t   dummy364[2];                            /*                  */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR5;                                   /*  PPR5            */
+    volatile uint8_t   dummy365[2];                            /*                  */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR6;                                   /*  PPR6            */
+    volatile uint8_t   dummy366[2];                            /*                  */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR7;                                   /*  PPR7            */
+    volatile uint8_t   dummy367[2];                            /*                  */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR8;                                   /*  PPR8            */
+    volatile uint8_t   dummy368[2];                            /*                  */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR9;                                   /*  PPR9            */
+    volatile uint8_t   dummy369[2];                            /*                  */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR10;                                  /*  PPR10           */
+    volatile uint8_t   dummy370[2];                            /*                  */
+/* end of struct st_gpio_from_ppr0 */
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR11;                                  /*  PPR11           */
+    volatile uint8_t   dummy3710[2];                           /*                  */
+/* end of struct st_gpio_from_ppr0 */
+    volatile uint8_t   dummy3711[212];                         /*                  */
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM1;                                    /*  PM1             */
+    volatile uint8_t   dummy372[2];                            /*                  */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM2;                                    /*  PM2             */
+    volatile uint8_t   dummy373[2];                            /*                  */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM3;                                    /*  PM3             */
+    volatile uint8_t   dummy374[2];                            /*                  */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM4;                                    /*  PM4             */
+    volatile uint8_t   dummy375[2];                            /*                  */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM5;                                    /*  PM5             */
+    volatile uint8_t   dummy376[2];                            /*                  */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM6;                                    /*  PM6             */
+    volatile uint8_t   dummy377[2];                            /*                  */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM7;                                    /*  PM7             */
+    volatile uint8_t   dummy378[2];                            /*                  */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM8;                                    /*  PM8             */
+    volatile uint8_t   dummy379[2];                            /*                  */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM9;                                    /*  PM9             */
+    volatile uint8_t   dummy380[2];                            /*                  */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM10;                                   /*  PM10            */
+    volatile uint8_t   dummy381[2];                            /*                  */
+/* end of struct st_gpio_from_pm1 */
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM11;                                   /*  PM11            */
+    volatile uint8_t   dummy3820[2];                           /*                  */
+/* end of struct st_gpio_from_pm1 */
+    volatile uint8_t   dummy3821[208];                         /*                  */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC0;                                   /*  PMC0            */
+    volatile uint8_t   dummy383[2];                            /*                  */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC1;                                   /*  PMC1            */
+    volatile uint8_t   dummy384[2];                            /*                  */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC2;                                   /*  PMC2            */
+    volatile uint8_t   dummy385[2];                            /*                  */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC3;                                   /*  PMC3            */
+    volatile uint8_t   dummy386[2];                            /*                  */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC4;                                   /*  PMC4            */
+    volatile uint8_t   dummy387[2];                            /*                  */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC5;                                   /*  PMC5            */
+    volatile uint8_t   dummy388[2];                            /*                  */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC6;                                   /*  PMC6            */
+    volatile uint8_t   dummy389[2];                            /*                  */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC7;                                   /*  PMC7            */
+    volatile uint8_t   dummy390[2];                            /*                  */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC8;                                   /*  PMC8            */
+    volatile uint8_t   dummy391[2];                            /*                  */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC9;                                   /*  PMC9            */
+    volatile uint8_t   dummy392[2];                            /*                  */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC10;                                  /*  PMC10           */
+    volatile uint8_t   dummy393[2];                            /*                  */
+/* end of struct st_gpio_from_pmc0 */
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC11;                                  /*  PMC11           */
+    volatile uint8_t   dummy3940[2];                           /*                  */
+/* end of struct st_gpio_from_pmc0 */
+    volatile uint8_t   dummy3941[212];                         /*                  */
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC1;                                   /*  PFC1            */
+    volatile uint8_t   dummy395[2];                            /*                  */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC2;                                   /*  PFC2            */
+    volatile uint8_t   dummy396[2];                            /*                  */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC3;                                   /*  PFC3            */
+    volatile uint8_t   dummy397[2];                            /*                  */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC4;                                   /*  PFC4            */
+    volatile uint8_t   dummy398[2];                            /*                  */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC5;                                   /*  PFC5            */
+    volatile uint8_t   dummy399[2];                            /*                  */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC6;                                   /*  PFC6            */
+    volatile uint8_t   dummy400[2];                            /*                  */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC7;                                   /*  PFC7            */
+    volatile uint8_t   dummy401[2];                            /*                  */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC8;                                   /*  PFC8            */
+    volatile uint8_t   dummy402[2];                            /*                  */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC9;                                   /*  PFC9            */
+    volatile uint8_t   dummy403[2];                            /*                  */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC10;                                  /*  PFC10           */
+    volatile uint8_t   dummy404[2];                            /*                  */
+/* end of struct st_gpio_from_pfc1 */
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC11;                                  /*  PFC11           */
+    volatile uint8_t   dummy4050[2];                           /*                  */
+/* end of struct st_gpio_from_pfc1 */
+    volatile uint8_t   dummy4051[212];                         /*                  */
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE1;                                  /*  PFCE1           */
+    volatile uint8_t   dummy406[2];                            /*                  */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE2;                                  /*  PFCE2           */
+    volatile uint8_t   dummy407[2];                            /*                  */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE3;                                  /*  PFCE3           */
+    volatile uint8_t   dummy408[2];                            /*                  */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE4;                                  /*  PFCE4           */
+    volatile uint8_t   dummy409[2];                            /*                  */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE5;                                  /*  PFCE5           */
+    volatile uint8_t   dummy410[2];                            /*                  */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE6;                                  /*  PFCE6           */
+    volatile uint8_t   dummy411[2];                            /*                  */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE7;                                  /*  PFCE7           */
+    volatile uint8_t   dummy412[2];                            /*                  */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE8;                                  /*  PFCE8           */
+    volatile uint8_t   dummy413[2];                            /*                  */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE9;                                  /*  PFCE9           */
+    volatile uint8_t   dummy414[2];                            /*                  */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE10;                                 /*  PFCE10          */
+    volatile uint8_t   dummy415[2];                            /*                  */
+/* end of struct st_gpio_from_pfce1 */
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE11;                                 /*  PFCE11          */
+    volatile uint8_t   dummy4160[2];                           /*                  */
+/* end of struct st_gpio_from_pfce1 */
+    volatile uint8_t   dummy4161[212];                         /*                  */
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT1;                                  /*  PNOT1           */
+    volatile uint8_t   dummy417[2];                            /*                  */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT2;                                  /*  PNOT2           */
+    volatile uint8_t   dummy418[2];                            /*                  */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT3;                                  /*  PNOT3           */
+    volatile uint8_t   dummy419[2];                            /*                  */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT4;                                  /*  PNOT4           */
+    volatile uint8_t   dummy420[2];                            /*                  */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT5;                                  /*  PNOT5           */
+    volatile uint8_t   dummy421[2];                            /*                  */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT6;                                  /*  PNOT6           */
+    volatile uint8_t   dummy422[2];                            /*                  */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT7;                                  /*  PNOT7           */
+    volatile uint8_t   dummy423[2];                            /*                  */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT8;                                  /*  PNOT8           */
+    volatile uint8_t   dummy424[2];                            /*                  */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT9;                                  /*  PNOT9           */
+    volatile uint8_t   dummy425[2];                            /*                  */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT10;                                 /*  PNOT10          */
+    volatile uint8_t   dummy426[2];                            /*                  */
+/* end of struct st_gpio_from_pnot1 */
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT11;                                 /*  PNOT11          */
+    volatile uint8_t   dummy4270[2];                           /*                  */
+/* end of struct st_gpio_from_pnot1 */
+    volatile uint8_t   dummy4271[212];                         /*                  */
+#define GPIO_PMSRn_COUNT 11
+    volatile uint32_t  PMSR1;                                  /*  PMSR1           */
+    volatile uint32_t  PMSR2;                                  /*  PMSR2           */
+    volatile uint32_t  PMSR3;                                  /*  PMSR3           */
+    volatile uint32_t  PMSR4;                                  /*  PMSR4           */
+    volatile uint32_t  PMSR5;                                  /*  PMSR5           */
+    volatile uint32_t  PMSR6;                                  /*  PMSR6           */
+    volatile uint32_t  PMSR7;                                  /*  PMSR7           */
+    volatile uint32_t  PMSR8;                                  /*  PMSR8           */
+    volatile uint32_t  PMSR9;                                  /*  PMSR9           */
+    volatile uint32_t  PMSR10;                                 /*  PMSR10          */
+    volatile uint32_t  PMSR11;                                 /*  PMSR11          */
+    volatile uint8_t   dummy428[208];                          /*                  */
+#define GPIO_PMCSRn_COUNT 12
+    volatile uint32_t  PMCSR0;                                 /*  PMCSR0          */
+    volatile uint32_t  PMCSR1;                                 /*  PMCSR1          */
+    volatile uint32_t  PMCSR2;                                 /*  PMCSR2          */
+    volatile uint32_t  PMCSR3;                                 /*  PMCSR3          */
+    volatile uint32_t  PMCSR4;                                 /*  PMCSR4          */
+    volatile uint32_t  PMCSR5;                                 /*  PMCSR5          */
+    volatile uint32_t  PMCSR6;                                 /*  PMCSR6          */
+    volatile uint32_t  PMCSR7;                                 /*  PMCSR7          */
+    volatile uint32_t  PMCSR8;                                 /*  PMCSR8          */
+    volatile uint32_t  PMCSR9;                                 /*  PMCSR9          */
+    volatile uint32_t  PMCSR10;                                /*  PMCSR10         */
+    volatile uint32_t  PMCSR11;                                /*  PMCSR11         */
+    volatile uint8_t   dummy429[212];                          /*                  */
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
+    volatile uint8_t   dummy430[2];                            /*                  */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE2;                                 /*  PFCAE2          */
+    volatile uint8_t   dummy431[2];                            /*                  */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE3;                                 /*  PFCAE3          */
+    volatile uint8_t   dummy432[2];                            /*                  */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE4;                                 /*  PFCAE4          */
+    volatile uint8_t   dummy433[2];                            /*                  */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE5;                                 /*  PFCAE5          */
+    volatile uint8_t   dummy434[2];                            /*                  */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE6;                                 /*  PFCAE6          */
+    volatile uint8_t   dummy435[2];                            /*                  */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE7;                                 /*  PFCAE7          */
+    volatile uint8_t   dummy436[2];                            /*                  */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE8;                                 /*  PFCAE8          */
+    volatile uint8_t   dummy437[2];                            /*                  */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE9;                                 /*  PFCAE9          */
+    volatile uint8_t   dummy438[2];                            /*                  */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE10;                                /*  PFCAE10         */
+    volatile uint8_t   dummy439[2];                            /*                  */
+/* end of struct st_gpio_from_pfcae1 */
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE11;                                /*  PFCAE11         */
+    volatile uint8_t   dummy4400[2];                           /*                  */
+/* end of struct st_gpio_from_pfcae1 */
+    volatile uint8_t   dummy4401[464];                         /*                  */
+    volatile uint32_t  SNCR;                                   /*  SNCR            */
+    volatile uint8_t   dummy441[13308];                        /*                  */
+    volatile uint16_t PIBC0;                                  /*  PIBC0           */
+    volatile uint8_t   dummy442[2];                            /*                  */
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC1;                                  /*  PIBC1           */
+    volatile uint8_t   dummy443[2];                            /*                  */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC2;                                  /*  PIBC2           */
+    volatile uint8_t   dummy444[2];                            /*                  */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC3;                                  /*  PIBC3           */
+    volatile uint8_t   dummy445[2];                            /*                  */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC4;                                  /*  PIBC4           */
+    volatile uint8_t   dummy446[2];                            /*                  */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC5;                                  /*  PIBC5           */
+    volatile uint8_t   dummy447[2];                            /*                  */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC6;                                  /*  PIBC6           */
+    volatile uint8_t   dummy448[2];                            /*                  */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC7;                                  /*  PIBC7           */
+    volatile uint8_t   dummy449[2];                            /*                  */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC8;                                  /*  PIBC8           */
+    volatile uint8_t   dummy450[2];                            /*                  */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC9;                                  /*  PIBC9           */
+    volatile uint8_t   dummy451[2];                            /*                  */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC10;                                 /*  PIBC10          */
+    volatile uint8_t   dummy452[2];                            /*                  */
+/* end of struct st_gpio_from_pibc1 */
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC11;                                 /*  PIBC11          */
+    volatile uint8_t   dummy4530[2];                           /*                  */
+/* end of struct st_gpio_from_pibc1 */
+    volatile uint8_t   dummy4531[212];                         /*                  */
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC1;                                  /*  PBDC1           */
+    volatile uint8_t   dummy454[2];                            /*                  */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC2;                                  /*  PBDC2           */
+    volatile uint8_t   dummy455[2];                            /*                  */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC3;                                  /*  PBDC3           */
+    volatile uint8_t   dummy456[2];                            /*                  */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC4;                                  /*  PBDC4           */
+    volatile uint8_t   dummy457[2];                            /*                  */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC5;                                  /*  PBDC5           */
+    volatile uint8_t   dummy458[2];                            /*                  */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC6;                                  /*  PBDC6           */
+    volatile uint8_t   dummy459[2];                            /*                  */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC7;                                  /*  PBDC7           */
+    volatile uint8_t   dummy460[2];                            /*                  */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC8;                                  /*  PBDC8           */
+    volatile uint8_t   dummy461[2];                            /*                  */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC9;                                  /*  PBDC9           */
+    volatile uint8_t   dummy462[2];                            /*                  */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC10;                                 /*  PBDC10          */
+    volatile uint8_t   dummy463[2];                            /*                  */
+/* end of struct st_gpio_from_pbdc1 */
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC11;                                 /*  PBDC11          */
+    volatile uint8_t   dummy4640[2];                           /*                  */
+/* end of struct st_gpio_from_pbdc1 */
+    volatile uint8_t   dummy4641[212];                         /*                  */
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC1;                                  /*  PIPC1           */
+    volatile uint8_t   dummy465[2];                            /*                  */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC2;                                  /*  PIPC2           */
+    volatile uint8_t   dummy466[2];                            /*                  */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC3;                                  /*  PIPC3           */
+    volatile uint8_t   dummy467[2];                            /*                  */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC4;                                  /*  PIPC4           */
+    volatile uint8_t   dummy468[2];                            /*                  */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC5;                                  /*  PIPC5           */
+    volatile uint8_t   dummy469[2];                            /*                  */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC6;                                  /*  PIPC6           */
+    volatile uint8_t   dummy470[2];                            /*                  */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC7;                                  /*  PIPC7           */
+    volatile uint8_t   dummy471[2];                            /*                  */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC8;                                  /*  PIPC8           */
+    volatile uint8_t   dummy472[2];                            /*                  */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC9;                                  /*  PIPC9           */
+    volatile uint8_t   dummy473[2];                            /*                  */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC10;                                 /*  PIPC10          */
+    volatile uint8_t   dummy474[2];                            /*                  */
+/* end of struct st_gpio_from_pipc1 */
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC11;                                 /*  PIPC11          */
+    volatile uint8_t   dummy4750[2];                           /*                  */
+/* end of struct st_gpio_from_pipc1 */
+    volatile uint8_t   dummy4751[2288];                        /*                  */
+    volatile uint16_t JPPR0;                                  /*  JPPR0           */
+    volatile uint8_t   dummy476[30];                           /*                  */
+    volatile uint16_t JPMC0;                                  /*  JPMC0           */
+    volatile uint8_t   dummy477[78];                           /*                  */
+    volatile uint32_t  JPMCSR0;                                /*  JPMCSR0         */
+    volatile uint8_t   dummy478[876];                          /*                  */
+    volatile uint16_t JPIBC0;                                 /*  JPIBC0          */
+};
+
+
+struct st_gpio_from_p1
+{
+    volatile uint16_t P1;                                     /*  P1              */
+    volatile uint8_t   dummy1[3];                              /*                  */
+};
+
+
+struct st_gpio_from_ppr0
+{
+    volatile uint16_t PPR0;                                   /*  PPR0            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+};
+
+
+struct st_gpio_from_pm1
+{
+    volatile uint16_t PM1;                                    /*  PM1             */
+    volatile uint8_t   dummy1[2];                              /*                  */
+};
+
+
+struct st_gpio_from_pmc0
+{
+    volatile uint16_t PMC0;                                   /*  PMC0            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+};
+
+
+struct st_gpio_from_pfc1
+{
+    volatile uint16_t PFC1;                                   /*  PFC1            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+};
+
+
+struct st_gpio_from_pfce1
+{
+    volatile uint16_t PFCE1;                                  /*  PFCE1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+};
+
+
+struct st_gpio_from_pnot1
+{
+    volatile uint16_t PNOT1;                                  /*  PNOT1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+};
+
+
+struct st_gpio_from_pfcae1
+{
+    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
+    volatile uint8_t   dummy1[2];                              /*                  */
+};
+
+
+struct st_gpio_from_pibc1
+{
+    volatile uint16_t PIBC1;                                  /*  PIBC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+};
+
+
+struct st_gpio_from_pbdc1
+{
+    volatile uint16_t PBDC1;                                  /*  PBDC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+};
+
+
+struct st_gpio_from_pipc1
+{
+    volatile uint16_t PIPC1;                                  /*  PIPC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+};
+
+
+#define GPIO    (*(struct st_gpio    *)0xFCFE3004uL) /* GPIO */
+
+/* Start of channnel array defines of GPIO */
+
+/* Channnel array defines of GPIO_FROM_PIPC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */
+#define GPIO_FROM_PIPC1_ARRAY_COUNT  11
+#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \
+    &GPIO_FROM_PIPC9, &GPIO_FROM_PIPC10, &GPIO_FROM_PIPC11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PIPC1 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC1) /* GPIO_FROM_PIPC1 */
+#define GPIO_FROM_PIPC2 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC2) /* GPIO_FROM_PIPC2 */
+#define GPIO_FROM_PIPC3 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC3) /* GPIO_FROM_PIPC3 */
+#define GPIO_FROM_PIPC4 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC4) /* GPIO_FROM_PIPC4 */
+#define GPIO_FROM_PIPC5 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC5) /* GPIO_FROM_PIPC5 */
+#define GPIO_FROM_PIPC6 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC6) /* GPIO_FROM_PIPC6 */
+#define GPIO_FROM_PIPC7 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC7) /* GPIO_FROM_PIPC7 */
+#define GPIO_FROM_PIPC8 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC8) /* GPIO_FROM_PIPC8 */
+#define GPIO_FROM_PIPC9 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC9) /* GPIO_FROM_PIPC9 */
+#define GPIO_FROM_PIPC10 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC10) /* GPIO_FROM_PIPC10 */
+#define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PBDC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */
+#define GPIO_FROM_PBDC1_ARRAY_COUNT  11
+#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \
+    &GPIO_FROM_PBDC9, &GPIO_FROM_PBDC10, &GPIO_FROM_PBDC11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PBDC1 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC1) /* GPIO_FROM_PBDC1 */
+#define GPIO_FROM_PBDC2 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC2) /* GPIO_FROM_PBDC2 */
+#define GPIO_FROM_PBDC3 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC3) /* GPIO_FROM_PBDC3 */
+#define GPIO_FROM_PBDC4 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC4) /* GPIO_FROM_PBDC4 */
+#define GPIO_FROM_PBDC5 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC5) /* GPIO_FROM_PBDC5 */
+#define GPIO_FROM_PBDC6 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC6) /* GPIO_FROM_PBDC6 */
+#define GPIO_FROM_PBDC7 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC7) /* GPIO_FROM_PBDC7 */
+#define GPIO_FROM_PBDC8 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC8) /* GPIO_FROM_PBDC8 */
+#define GPIO_FROM_PBDC9 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC9) /* GPIO_FROM_PBDC9 */
+#define GPIO_FROM_PBDC10 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC10) /* GPIO_FROM_PBDC10 */
+#define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PIBC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */
+#define GPIO_FROM_PIBC1_ARRAY_COUNT  11
+#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, &GPIO_FROM_PIBC8, \
+    &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */
+#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */
+#define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */
+#define GPIO_FROM_PIBC4 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC4) /* GPIO_FROM_PIBC4 */
+#define GPIO_FROM_PIBC5 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC5) /* GPIO_FROM_PIBC5 */
+#define GPIO_FROM_PIBC6 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC6) /* GPIO_FROM_PIBC6 */
+#define GPIO_FROM_PIBC7 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC7) /* GPIO_FROM_PIBC7 */
+#define GPIO_FROM_PIBC8 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC8) /* GPIO_FROM_PIBC8 */
+#define GPIO_FROM_PIBC9 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC9) /* GPIO_FROM_PIBC9 */
+#define GPIO_FROM_PIBC10 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC10) /* GPIO_FROM_PIBC10 */
+#define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PFCAE1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */
+#define GPIO_FROM_PFCAE1_ARRAY_COUNT  11
+#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \
+    &GPIO_FROM_PFCAE9, &GPIO_FROM_PFCAE10, &GPIO_FROM_PFCAE11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFCAE1 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE1) /* GPIO_FROM_PFCAE1 */
+#define GPIO_FROM_PFCAE2 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE2) /* GPIO_FROM_PFCAE2 */
+#define GPIO_FROM_PFCAE3 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE3) /* GPIO_FROM_PFCAE3 */
+#define GPIO_FROM_PFCAE4 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE4) /* GPIO_FROM_PFCAE4 */
+#define GPIO_FROM_PFCAE5 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE5) /* GPIO_FROM_PFCAE5 */
+#define GPIO_FROM_PFCAE6 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE6) /* GPIO_FROM_PFCAE6 */
+#define GPIO_FROM_PFCAE7 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE7) /* GPIO_FROM_PFCAE7 */
+#define GPIO_FROM_PFCAE8 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE8) /* GPIO_FROM_PFCAE8 */
+#define GPIO_FROM_PFCAE9 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE9) /* GPIO_FROM_PFCAE9 */
+#define GPIO_FROM_PFCAE10 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE10) /* GPIO_FROM_PFCAE10 */
+#define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */
+
+
+/* Channnel array defines of GPIO_FROM_PNOT1_ARRAY */
+/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */
+#define GPIO_FROM_PNOT1_ARRAY_COUNT  11
+#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \
+    &GPIO_FROM_PNOT9, &GPIO_FROM_PNOT10, &GPIO_FROM_PNOT11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PNOT1 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT1) /* GPIO_FROM_PNOT1 */
+#define GPIO_FROM_PNOT2 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT2) /* GPIO_FROM_PNOT2 */
+#define GPIO_FROM_PNOT3 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT3) /* GPIO_FROM_PNOT3 */
+#define GPIO_FROM_PNOT4 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT4) /* GPIO_FROM_PNOT4 */
+#define GPIO_FROM_PNOT5 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT5) /* GPIO_FROM_PNOT5 */
+#define GPIO_FROM_PNOT6 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT6) /* GPIO_FROM_PNOT6 */
+#define GPIO_FROM_PNOT7 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT7) /* GPIO_FROM_PNOT7 */
+#define GPIO_FROM_PNOT8 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT8) /* GPIO_FROM_PNOT8 */
+#define GPIO_FROM_PNOT9 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT9) /* GPIO_FROM_PNOT9 */
+#define GPIO_FROM_PNOT10 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT10) /* GPIO_FROM_PNOT10 */
+#define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */
+
+
+/* Channnel array defines of GPIO_FROM_PFCE1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */
+#define GPIO_FROM_PFCE1_ARRAY_COUNT  11
+#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \
+    &GPIO_FROM_PFCE9, &GPIO_FROM_PFCE10, &GPIO_FROM_PFCE11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFCE1 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE1) /* GPIO_FROM_PFCE1 */
+#define GPIO_FROM_PFCE2 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE2) /* GPIO_FROM_PFCE2 */
+#define GPIO_FROM_PFCE3 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE3) /* GPIO_FROM_PFCE3 */
+#define GPIO_FROM_PFCE4 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE4) /* GPIO_FROM_PFCE4 */
+#define GPIO_FROM_PFCE5 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE5) /* GPIO_FROM_PFCE5 */
+#define GPIO_FROM_PFCE6 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE6) /* GPIO_FROM_PFCE6 */
+#define GPIO_FROM_PFCE7 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE7) /* GPIO_FROM_PFCE7 */
+#define GPIO_FROM_PFCE8 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE8) /* GPIO_FROM_PFCE8 */
+#define GPIO_FROM_PFCE9 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE9) /* GPIO_FROM_PFCE9 */
+#define GPIO_FROM_PFCE10 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE10) /* GPIO_FROM_PFCE10 */
+#define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */
+
+
+/* Channnel array defines of GPIO_FROM_PFC1_ARRAY */
+/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */
+#define GPIO_FROM_PFC1_ARRAY_COUNT  11
+#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \
+    &GPIO_FROM_PFC9, &GPIO_FROM_PFC10, &GPIO_FROM_PFC11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PFC1 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC1) /* GPIO_FROM_PFC1 */
+#define GPIO_FROM_PFC2 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC2) /* GPIO_FROM_PFC2 */
+#define GPIO_FROM_PFC3 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC3) /* GPIO_FROM_PFC3 */
+#define GPIO_FROM_PFC4 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC4) /* GPIO_FROM_PFC4 */
+#define GPIO_FROM_PFC5 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC5) /* GPIO_FROM_PFC5 */
+#define GPIO_FROM_PFC6 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC6) /* GPIO_FROM_PFC6 */
+#define GPIO_FROM_PFC7 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC7) /* GPIO_FROM_PFC7 */
+#define GPIO_FROM_PFC8 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC8) /* GPIO_FROM_PFC8 */
+#define GPIO_FROM_PFC9 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC9) /* GPIO_FROM_PFC9 */
+#define GPIO_FROM_PFC10 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC10) /* GPIO_FROM_PFC10 */
+#define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PMC0_ARRAY */
+/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */
+#define GPIO_FROM_PMC0_ARRAY_COUNT  12
+#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \
+    &GPIO_FROM_PMC8, &GPIO_FROM_PMC9, &GPIO_FROM_PMC10, &GPIO_FROM_PMC11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PMC0 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC0) /* GPIO_FROM_PMC0 */
+#define GPIO_FROM_PMC1 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC1) /* GPIO_FROM_PMC1 */
+#define GPIO_FROM_PMC2 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC2) /* GPIO_FROM_PMC2 */
+#define GPIO_FROM_PMC3 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC3) /* GPIO_FROM_PMC3 */
+#define GPIO_FROM_PMC4 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC4) /* GPIO_FROM_PMC4 */
+#define GPIO_FROM_PMC5 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC5) /* GPIO_FROM_PMC5 */
+#define GPIO_FROM_PMC6 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC6) /* GPIO_FROM_PMC6 */
+#define GPIO_FROM_PMC7 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC7) /* GPIO_FROM_PMC7 */
+#define GPIO_FROM_PMC8 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC8) /* GPIO_FROM_PMC8 */
+#define GPIO_FROM_PMC9 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC9) /* GPIO_FROM_PMC9 */
+#define GPIO_FROM_PMC10 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC10) /* GPIO_FROM_PMC10 */
+#define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */
+
+
+/* Channnel array defines of GPIO_FROM_PM1_ARRAY */
+/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */
+#define GPIO_FROM_PM1_ARRAY_COUNT  11
+#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \
+    &GPIO_FROM_PM9, &GPIO_FROM_PM10, &GPIO_FROM_PM11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PM1 (*(struct st_gpio_from_pm1 *)&GPIO.PM1)    /* GPIO_FROM_PM1 */
+#define GPIO_FROM_PM2 (*(struct st_gpio_from_pm1 *)&GPIO.PM2)    /* GPIO_FROM_PM2 */
+#define GPIO_FROM_PM3 (*(struct st_gpio_from_pm1 *)&GPIO.PM3)    /* GPIO_FROM_PM3 */
+#define GPIO_FROM_PM4 (*(struct st_gpio_from_pm1 *)&GPIO.PM4)    /* GPIO_FROM_PM4 */
+#define GPIO_FROM_PM5 (*(struct st_gpio_from_pm1 *)&GPIO.PM5)    /* GPIO_FROM_PM5 */
+#define GPIO_FROM_PM6 (*(struct st_gpio_from_pm1 *)&GPIO.PM6)    /* GPIO_FROM_PM6 */
+#define GPIO_FROM_PM7 (*(struct st_gpio_from_pm1 *)&GPIO.PM7)    /* GPIO_FROM_PM7 */
+#define GPIO_FROM_PM8 (*(struct st_gpio_from_pm1 *)&GPIO.PM8)    /* GPIO_FROM_PM8 */
+#define GPIO_FROM_PM9 (*(struct st_gpio_from_pm1 *)&GPIO.PM9)    /* GPIO_FROM_PM9 */
+#define GPIO_FROM_PM10 (*(struct st_gpio_from_pm1 *)&GPIO.PM10)  /* GPIO_FROM_PM10 */
+#define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11)  /* GPIO_FROM_PM11 */
+
+
+/* Channnel array defines of GPIO_FROM_PPR0_ARRAY */
+/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */
+#define GPIO_FROM_PPR0_ARRAY_COUNT  12
+#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \
+    &GPIO_FROM_PPR8, &GPIO_FROM_PPR9, &GPIO_FROM_PPR10, &GPIO_FROM_PPR11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PPR0 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR0) /* GPIO_FROM_PPR0 */
+#define GPIO_FROM_PPR1 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR1) /* GPIO_FROM_PPR1 */
+#define GPIO_FROM_PPR2 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR2) /* GPIO_FROM_PPR2 */
+#define GPIO_FROM_PPR3 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR3) /* GPIO_FROM_PPR3 */
+#define GPIO_FROM_PPR4 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR4) /* GPIO_FROM_PPR4 */
+#define GPIO_FROM_PPR5 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR5) /* GPIO_FROM_PPR5 */
+#define GPIO_FROM_PPR6 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR6) /* GPIO_FROM_PPR6 */
+#define GPIO_FROM_PPR7 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR7) /* GPIO_FROM_PPR7 */
+#define GPIO_FROM_PPR8 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR8) /* GPIO_FROM_PPR8 */
+#define GPIO_FROM_PPR9 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR9) /* GPIO_FROM_PPR9 */
+#define GPIO_FROM_PPR10 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR10) /* GPIO_FROM_PPR10 */
+#define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */
+
+
+/* Channnel array defines of GPIO_FROM_P1_ARRAY */
+/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */
+#define GPIO_FROM_P1_ARRAY_COUNT  11
+#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \
+    &GPIO_FROM_P9, &GPIO_FROM_P10, &GPIO_FROM_P11 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_P1 (*(struct st_gpio_from_p1 *)&GPIO.P1)       /* GPIO_FROM_P1 */
+#define GPIO_FROM_P2 (*(struct st_gpio_from_p1 *)&GPIO.P2)       /* GPIO_FROM_P2 */
+#define GPIO_FROM_P3 (*(struct st_gpio_from_p1 *)&GPIO.P3)       /* GPIO_FROM_P3 */
+#define GPIO_FROM_P4 (*(struct st_gpio_from_p1 *)&GPIO.P4)       /* GPIO_FROM_P4 */
+#define GPIO_FROM_P5 (*(struct st_gpio_from_p1 *)&GPIO.P5)       /* GPIO_FROM_P5 */
+#define GPIO_FROM_P6 (*(struct st_gpio_from_p1 *)&GPIO.P6)       /* GPIO_FROM_P6 */
+#define GPIO_FROM_P7 (*(struct st_gpio_from_p1 *)&GPIO.P7)       /* GPIO_FROM_P7 */
+#define GPIO_FROM_P8 (*(struct st_gpio_from_p1 *)&GPIO.P8)       /* GPIO_FROM_P8 */
+#define GPIO_FROM_P9 (*(struct st_gpio_from_p1 *)&GPIO.P9)       /* GPIO_FROM_P9 */
+#define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10)     /* GPIO_FROM_P10 */
+#define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11)     /* GPIO_FROM_P11 */
+
+/* End of channnel array defines of GPIO */
+
+
+#define GPIOP1 GPIO.P1
+#define GPIOP2 GPIO.P2
+#define GPIOP3 GPIO.P3
+#define GPIOP4 GPIO.P4
+#define GPIOP5 GPIO.P5
+#define GPIOP6 GPIO.P6
+#define GPIOP7 GPIO.P7
+#define GPIOP8 GPIO.P8
+#define GPIOP9 GPIO.P9
+#define GPIOP10 GPIO.P10
+#define GPIOP11 GPIO.P11
+#define GPIOPSR1 GPIO.PSR1
+#define GPIOPSR2 GPIO.PSR2
+#define GPIOPSR3 GPIO.PSR3
+#define GPIOPSR4 GPIO.PSR4
+#define GPIOPSR5 GPIO.PSR5
+#define GPIOPSR6 GPIO.PSR6
+#define GPIOPSR7 GPIO.PSR7
+#define GPIOPSR8 GPIO.PSR8
+#define GPIOPSR9 GPIO.PSR9
+#define GPIOPSR10 GPIO.PSR10
+#define GPIOPSR11 GPIO.PSR11
+#define GPIOPPR0 GPIO.PPR0
+#define GPIOPPR1 GPIO.PPR1
+#define GPIOPPR2 GPIO.PPR2
+#define GPIOPPR3 GPIO.PPR3
+#define GPIOPPR4 GPIO.PPR4
+#define GPIOPPR5 GPIO.PPR5
+#define GPIOPPR6 GPIO.PPR6
+#define GPIOPPR7 GPIO.PPR7
+#define GPIOPPR8 GPIO.PPR8
+#define GPIOPPR9 GPIO.PPR9
+#define GPIOPPR10 GPIO.PPR10
+#define GPIOPPR11 GPIO.PPR11
+#define GPIOPM1 GPIO.PM1
+#define GPIOPM2 GPIO.PM2
+#define GPIOPM3 GPIO.PM3
+#define GPIOPM4 GPIO.PM4
+#define GPIOPM5 GPIO.PM5
+#define GPIOPM6 GPIO.PM6
+#define GPIOPM7 GPIO.PM7
+#define GPIOPM8 GPIO.PM8
+#define GPIOPM9 GPIO.PM9
+#define GPIOPM10 GPIO.PM10
+#define GPIOPM11 GPIO.PM11
+#define GPIOPMC0 GPIO.PMC0
+#define GPIOPMC1 GPIO.PMC1
+#define GPIOPMC2 GPIO.PMC2
+#define GPIOPMC3 GPIO.PMC3
+#define GPIOPMC4 GPIO.PMC4
+#define GPIOPMC5 GPIO.PMC5
+#define GPIOPMC6 GPIO.PMC6
+#define GPIOPMC7 GPIO.PMC7
+#define GPIOPMC8 GPIO.PMC8
+#define GPIOPMC9 GPIO.PMC9
+#define GPIOPMC10 GPIO.PMC10
+#define GPIOPMC11 GPIO.PMC11
+#define GPIOPFC1 GPIO.PFC1
+#define GPIOPFC2 GPIO.PFC2
+#define GPIOPFC3 GPIO.PFC3
+#define GPIOPFC4 GPIO.PFC4
+#define GPIOPFC5 GPIO.PFC5
+#define GPIOPFC6 GPIO.PFC6
+#define GPIOPFC7 GPIO.PFC7
+#define GPIOPFC8 GPIO.PFC8
+#define GPIOPFC9 GPIO.PFC9
+#define GPIOPFC10 GPIO.PFC10
+#define GPIOPFC11 GPIO.PFC11
+#define GPIOPFCE1 GPIO.PFCE1
+#define GPIOPFCE2 GPIO.PFCE2
+#define GPIOPFCE3 GPIO.PFCE3
+#define GPIOPFCE4 GPIO.PFCE4
+#define GPIOPFCE5 GPIO.PFCE5
+#define GPIOPFCE6 GPIO.PFCE6
+#define GPIOPFCE7 GPIO.PFCE7
+#define GPIOPFCE8 GPIO.PFCE8
+#define GPIOPFCE9 GPIO.PFCE9
+#define GPIOPFCE10 GPIO.PFCE10
+#define GPIOPFCE11 GPIO.PFCE11
+#define GPIOPNOT1 GPIO.PNOT1
+#define GPIOPNOT2 GPIO.PNOT2
+#define GPIOPNOT3 GPIO.PNOT3
+#define GPIOPNOT4 GPIO.PNOT4
+#define GPIOPNOT5 GPIO.PNOT5
+#define GPIOPNOT6 GPIO.PNOT6
+#define GPIOPNOT7 GPIO.PNOT7
+#define GPIOPNOT8 GPIO.PNOT8
+#define GPIOPNOT9 GPIO.PNOT9
+#define GPIOPNOT10 GPIO.PNOT10
+#define GPIOPNOT11 GPIO.PNOT11
+#define GPIOPMSR1 GPIO.PMSR1
+#define GPIOPMSR2 GPIO.PMSR2
+#define GPIOPMSR3 GPIO.PMSR3
+#define GPIOPMSR4 GPIO.PMSR4
+#define GPIOPMSR5 GPIO.PMSR5
+#define GPIOPMSR6 GPIO.PMSR6
+#define GPIOPMSR7 GPIO.PMSR7
+#define GPIOPMSR8 GPIO.PMSR8
+#define GPIOPMSR9 GPIO.PMSR9
+#define GPIOPMSR10 GPIO.PMSR10
+#define GPIOPMSR11 GPIO.PMSR11
+#define GPIOPMCSR0 GPIO.PMCSR0
+#define GPIOPMCSR1 GPIO.PMCSR1
+#define GPIOPMCSR2 GPIO.PMCSR2
+#define GPIOPMCSR3 GPIO.PMCSR3
+#define GPIOPMCSR4 GPIO.PMCSR4
+#define GPIOPMCSR5 GPIO.PMCSR5
+#define GPIOPMCSR6 GPIO.PMCSR6
+#define GPIOPMCSR7 GPIO.PMCSR7
+#define GPIOPMCSR8 GPIO.PMCSR8
+#define GPIOPMCSR9 GPIO.PMCSR9
+#define GPIOPMCSR10 GPIO.PMCSR10
+#define GPIOPMCSR11 GPIO.PMCSR11
+#define GPIOPFCAE1 GPIO.PFCAE1
+#define GPIOPFCAE2 GPIO.PFCAE2
+#define GPIOPFCAE3 GPIO.PFCAE3
+#define GPIOPFCAE4 GPIO.PFCAE4
+#define GPIOPFCAE5 GPIO.PFCAE5
+#define GPIOPFCAE6 GPIO.PFCAE6
+#define GPIOPFCAE7 GPIO.PFCAE7
+#define GPIOPFCAE8 GPIO.PFCAE8
+#define GPIOPFCAE9 GPIO.PFCAE9
+#define GPIOPFCAE10 GPIO.PFCAE10
+#define GPIOPFCAE11 GPIO.PFCAE11
+#define GPIOSNCR GPIO.SNCR
+#define GPIOPIBC0 GPIO.PIBC0
+#define GPIOPIBC1 GPIO.PIBC1
+#define GPIOPIBC2 GPIO.PIBC2
+#define GPIOPIBC3 GPIO.PIBC3
+#define GPIOPIBC4 GPIO.PIBC4
+#define GPIOPIBC5 GPIO.PIBC5
+#define GPIOPIBC6 GPIO.PIBC6
+#define GPIOPIBC7 GPIO.PIBC7
+#define GPIOPIBC8 GPIO.PIBC8
+#define GPIOPIBC9 GPIO.PIBC9
+#define GPIOPIBC10 GPIO.PIBC10
+#define GPIOPIBC11 GPIO.PIBC11
+#define GPIOPBDC1 GPIO.PBDC1
+#define GPIOPBDC2 GPIO.PBDC2
+#define GPIOPBDC3 GPIO.PBDC3
+#define GPIOPBDC4 GPIO.PBDC4
+#define GPIOPBDC5 GPIO.PBDC5
+#define GPIOPBDC6 GPIO.PBDC6
+#define GPIOPBDC7 GPIO.PBDC7
+#define GPIOPBDC8 GPIO.PBDC8
+#define GPIOPBDC9 GPIO.PBDC9
+#define GPIOPBDC10 GPIO.PBDC10
+#define GPIOPBDC11 GPIO.PBDC11
+#define GPIOPIPC1 GPIO.PIPC1
+#define GPIOPIPC2 GPIO.PIPC2
+#define GPIOPIPC3 GPIO.PIPC3
+#define GPIOPIPC4 GPIO.PIPC4
+#define GPIOPIPC5 GPIO.PIPC5
+#define GPIOPIPC6 GPIO.PIPC6
+#define GPIOPIPC7 GPIO.PIPC7
+#define GPIOPIPC8 GPIO.PIPC8
+#define GPIOPIPC9 GPIO.PIPC9
+#define GPIOPIPC10 GPIO.PIPC10
+#define GPIOPIPC11 GPIO.PIPC11
+#define GPIOJPPR0 GPIO.JPPR0
+#define GPIOJPMC0 GPIO.JPMC0
+#define GPIOJPMCSR0 GPIO.JPMCSR0
+#define GPIOJPIBC0 GPIO.JPIBC0
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ieb_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,120 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ieb_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef IEB_IODEFINE_H
+#define IEB_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ieb
+{                                                          /* IEB              */
+    volatile uint8_t   B0BCR;                                  /*  B0BCR           */
+    volatile uint8_t   dummy495[3];                            /*                  */
+    volatile uint8_t   B0PSR;                                  /*  B0PSR           */
+    volatile uint8_t   dummy496[3];                            /*                  */
+    volatile uint16_t B0UAR;                                  /*  B0UAR           */
+    volatile uint8_t   dummy497[2];                            /*                  */
+    volatile uint16_t B0SAR;                                  /*  B0SAR           */
+    volatile uint8_t   dummy498[2];                            /*                  */
+    volatile uint16_t B0PAR;                                  /*  B0PAR           */
+    volatile uint8_t   dummy499[2];                            /*                  */
+    volatile uint16_t B0RSA;                                  /*  B0RSA           */
+    volatile uint8_t   dummy500[2];                            /*                  */
+    volatile uint8_t   B0CDR;                                  /*  B0CDR           */
+    volatile uint8_t   dummy501[3];                            /*                  */
+    volatile uint8_t   B0TCD;                                  /*  B0TCD           */
+    volatile uint8_t   dummy502[3];                            /*                  */
+    volatile uint8_t   B0RCD;                                  /*  B0RCD           */
+    volatile uint8_t   dummy503[3];                            /*                  */
+    volatile uint8_t   B0DLR;                                  /*  B0DLR           */
+    volatile uint8_t   dummy504[3];                            /*                  */
+    volatile uint8_t   B0TDL;                                  /*  B0TDL           */
+    volatile uint8_t   dummy505[3];                            /*                  */
+    volatile uint8_t   B0RDL;                                  /*  B0RDL           */
+    volatile uint8_t   dummy506[3];                            /*                  */
+    volatile uint8_t   B0CKS;                                  /*  B0CKS           */
+    volatile uint8_t   dummy507[3];                            /*                  */
+    volatile uint8_t   B0TMS;                                  /*  B0TMS           */
+    volatile uint8_t   dummy508[3];                            /*                  */
+    volatile uint8_t   B0PCR;                                  /*  B0PCR           */
+    volatile uint8_t   dummy509[3];                            /*                  */
+    volatile uint16_t B0BSR;                                  /*  B0BSR           */
+    volatile uint8_t   dummy510[2];                            /*                  */
+    volatile uint8_t   B0SSR;                                  /*  B0SSR           */
+    volatile uint8_t   dummy511[3];                            /*                  */
+    volatile uint8_t   B0USR;                                  /*  B0USR           */
+    volatile uint8_t   dummy512[3];                            /*                  */
+    volatile uint8_t   B0ISR;                                  /*  B0ISR           */
+    volatile uint8_t   dummy513[3];                            /*                  */
+    volatile uint8_t   B0ESR;                                  /*  B0ESR           */
+    volatile uint8_t   dummy514[3];                            /*                  */
+    volatile uint8_t   B0FSR;                                  /*  B0FSR           */
+    volatile uint8_t   dummy515[3];                            /*                  */
+    volatile uint8_t   B0SCR;                                  /*  B0SCR           */
+    volatile uint8_t   dummy516[3];                            /*                  */
+    volatile uint8_t   B0CCR;                                  /*  B0CCR           */
+    volatile uint8_t   dummy517[3];                            /*                  */
+    volatile uint8_t   B0STC0;                                 /*  B0STC0          */
+    volatile uint8_t   dummy518[3];                            /*                  */
+    volatile uint8_t   B0STC1;                                 /*  B0STC1          */
+    volatile uint8_t   dummy519[3];                            /*                  */
+    volatile uint8_t   B0DR;                                   /*  B0DR            */
+};
+
+
+#define IEB     (*(struct st_ieb     *)0xFCFEF000uL) /* IEB */
+
+
+#define IEBB0BCR IEB.B0BCR
+#define IEBB0PSR IEB.B0PSR
+#define IEBB0UAR IEB.B0UAR
+#define IEBB0SAR IEB.B0SAR
+#define IEBB0PAR IEB.B0PAR
+#define IEBB0RSA IEB.B0RSA
+#define IEBB0CDR IEB.B0CDR
+#define IEBB0TCD IEB.B0TCD
+#define IEBB0RCD IEB.B0RCD
+#define IEBB0DLR IEB.B0DLR
+#define IEBB0TDL IEB.B0TDL
+#define IEBB0RDL IEB.B0RDL
+#define IEBB0CKS IEB.B0CKS
+#define IEBB0TMS IEB.B0TMS
+#define IEBB0PCR IEB.B0PCR
+#define IEBB0BSR IEB.B0BSR
+#define IEBB0SSR IEB.B0SSR
+#define IEBB0USR IEB.B0USR
+#define IEBB0ISR IEB.B0ISR
+#define IEBB0ESR IEB.B0ESR
+#define IEBB0FSR IEB.B0FSR
+#define IEBB0SCR IEB.B0SCR
+#define IEBB0CCR IEB.B0CCR
+#define IEBB0STC0 IEB.B0STC0
+#define IEBB0STC1 IEB.B0STC1
+#define IEBB0DR IEB.B0DR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/inb_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,93 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : inb_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef INB_IODEFINE_H
+#define INB_IODEFINE_H
+
+struct st_inb
+{                                                          /* INB              */
+    volatile uint32_t  RMPR;                                   /*  RMPR            */
+#define INB_AXIBUSCTLn_COUNT 11
+    volatile uint32_t  AXIBUSCTL0;                             /*  AXIBUSCTL0      */
+    volatile uint32_t  AXIBUSCTL1;                             /*  AXIBUSCTL1      */
+    volatile uint32_t  AXIBUSCTL2;                             /*  AXIBUSCTL2      */
+    volatile uint32_t  AXIBUSCTL3;                             /*  AXIBUSCTL3      */
+    volatile uint32_t  AXIBUSCTL4;                             /*  AXIBUSCTL4      */
+    volatile uint32_t  AXIBUSCTL5;                             /*  AXIBUSCTL5      */
+    volatile uint32_t  AXIBUSCTL6;                             /*  AXIBUSCTL6      */
+    volatile uint32_t  AXIBUSCTL7;                             /*  AXIBUSCTL7      */
+    volatile uint32_t  AXIBUSCTL8;                             /*  AXIBUSCTL8      */
+    volatile uint32_t  AXIBUSCTL9;                             /*  AXIBUSCTL9      */
+    volatile uint32_t  AXIBUSCTL10;                            /*  AXIBUSCTL10     */
+#define INB_AXIRERRCTLn_COUNT 4
+    volatile uint32_t  AXIRERRCTL0;                            /*  AXIRERRCTL0     */
+    volatile uint32_t  AXIRERRCTL1;                            /*  AXIRERRCTL1     */
+    volatile uint32_t  AXIRERRCTL2;                            /*  AXIRERRCTL2     */
+    volatile uint32_t  AXIRERRCTL3;                            /*  AXIRERRCTL3     */
+#define INB_AXIRERRSTn_COUNT 4
+    volatile uint32_t  AXIRERRST0;                             /*  AXIRERRST0      */
+    volatile uint32_t  AXIRERRST1;                             /*  AXIRERRST1      */
+    volatile uint32_t  AXIRERRST2;                             /*  AXIRERRST2      */
+    volatile uint32_t  AXIRERRST3;                             /*  AXIRERRST3      */
+#define INB_AXIRERRCLRn_COUNT 4
+    volatile uint32_t  AXIRERRCLR0;                            /*  AXIRERRCLR0     */
+    volatile uint32_t  AXIRERRCLR1;                            /*  AXIRERRCLR1     */
+    volatile uint32_t  AXIRERRCLR2;                            /*  AXIRERRCLR2     */
+    volatile uint32_t  AXIRERRCLR3;                            /*  AXIRERRCLR3     */
+};
+
+
+#define INB     (*(struct st_inb     *)0xFCFE1A00uL) /* INB */
+
+
+#define INBRMPR INB.RMPR
+#define INBAXIBUSCTL0 INB.AXIBUSCTL0
+#define INBAXIBUSCTL1 INB.AXIBUSCTL1
+#define INBAXIBUSCTL2 INB.AXIBUSCTL2
+#define INBAXIBUSCTL3 INB.AXIBUSCTL3
+#define INBAXIBUSCTL4 INB.AXIBUSCTL4
+#define INBAXIBUSCTL5 INB.AXIBUSCTL5
+#define INBAXIBUSCTL6 INB.AXIBUSCTL6
+#define INBAXIBUSCTL7 INB.AXIBUSCTL7
+#define INBAXIBUSCTL8 INB.AXIBUSCTL8
+#define INBAXIBUSCTL9 INB.AXIBUSCTL9
+#define INBAXIBUSCTL10 INB.AXIBUSCTL10
+#define INBAXIRERRCTL0 INB.AXIRERRCTL0
+#define INBAXIRERRCTL1 INB.AXIRERRCTL1
+#define INBAXIRERRCTL2 INB.AXIRERRCTL2
+#define INBAXIRERRCTL3 INB.AXIRERRCTL3
+#define INBAXIRERRST0 INB.AXIRERRST0
+#define INBAXIRERRST1 INB.AXIRERRST1
+#define INBAXIRERRST2 INB.AXIRERRST2
+#define INBAXIRERRST3 INB.AXIRERRST3
+#define INBAXIRERRCLR0 INB.AXIRERRCLR0
+#define INBAXIRERRCLR1 INB.AXIRERRCLR1
+#define INBAXIRERRCLR2 INB.AXIRERRCLR2
+#define INBAXIRERRCLR3 INB.AXIRERRCLR3
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/intc_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1027 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : intc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef INTC_IODEFINE_H
+#define INTC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_intc
+{                                                          /* INTC             */
+    volatile uint32_t  ICDDCR;                                 /*  ICDDCR          */
+    volatile uint32_t  ICDICTR;                                /*  ICDICTR         */
+    volatile uint32_t  ICDIIDR;                                /*  ICDIIDR         */
+    volatile uint8_t   dummy193[116];                          /*                  */
+#define INTC_ICDISR0_COUNT 19
+    volatile uint32_t  ICDISR0;                                /*  ICDISR0         */
+    volatile uint32_t  ICDISR1;                                /*  ICDISR1         */
+    volatile uint32_t  ICDISR2;                                /*  ICDISR2         */
+    volatile uint32_t  ICDISR3;                                /*  ICDISR3         */
+    volatile uint32_t  ICDISR4;                                /*  ICDISR4         */
+    volatile uint32_t  ICDISR5;                                /*  ICDISR5         */
+    volatile uint32_t  ICDISR6;                                /*  ICDISR6         */
+    volatile uint32_t  ICDISR7;                                /*  ICDISR7         */
+    volatile uint32_t  ICDISR8;                                /*  ICDISR8         */
+    volatile uint32_t  ICDISR9;                                /*  ICDISR9         */
+    volatile uint32_t  ICDISR10;                               /*  ICDISR10        */
+    volatile uint32_t  ICDISR11;                               /*  ICDISR11        */
+    volatile uint32_t  ICDISR12;                               /*  ICDISR12        */
+    volatile uint32_t  ICDISR13;                               /*  ICDISR13        */
+    volatile uint32_t  ICDISR14;                               /*  ICDISR14        */
+    volatile uint32_t  ICDISR15;                               /*  ICDISR15        */
+    volatile uint32_t  ICDISR16;                               /*  ICDISR16        */
+    volatile uint32_t  ICDISR17;                               /*  ICDISR17        */
+    volatile uint32_t  ICDISR18;                               /*  ICDISR18        */
+    volatile uint8_t   dummy194[52];                           /*                  */
+#define INTC_ICDISER0_COUNT 19
+    volatile uint32_t  ICDISER0;                               /*  ICDISER0        */
+    volatile uint32_t  ICDISER1;                               /*  ICDISER1        */
+    volatile uint32_t  ICDISER2;                               /*  ICDISER2        */
+    volatile uint32_t  ICDISER3;                               /*  ICDISER3        */
+    volatile uint32_t  ICDISER4;                               /*  ICDISER4        */
+    volatile uint32_t  ICDISER5;                               /*  ICDISER5        */
+    volatile uint32_t  ICDISER6;                               /*  ICDISER6        */
+    volatile uint32_t  ICDISER7;                               /*  ICDISER7        */
+    volatile uint32_t  ICDISER8;                               /*  ICDISER8        */
+    volatile uint32_t  ICDISER9;                               /*  ICDISER9        */
+    volatile uint32_t  ICDISER10;                              /*  ICDISER10       */
+    volatile uint32_t  ICDISER11;                              /*  ICDISER11       */
+    volatile uint32_t  ICDISER12;                              /*  ICDISER12       */
+    volatile uint32_t  ICDISER13;                              /*  ICDISER13       */
+    volatile uint32_t  ICDISER14;                              /*  ICDISER14       */
+    volatile uint32_t  ICDISER15;                              /*  ICDISER15       */
+    volatile uint32_t  ICDISER16;                              /*  ICDISER16       */
+    volatile uint32_t  ICDISER17;                              /*  ICDISER17       */
+    volatile uint32_t  ICDISER18;                              /*  ICDISER18       */
+    volatile uint8_t   dummy195[52];                           /*                  */
+#define INTC_ICDICER0_COUNT 19
+    volatile uint32_t  ICDICER0;                               /*  ICDICER0        */
+    volatile uint32_t  ICDICER1;                               /*  ICDICER1        */
+    volatile uint32_t  ICDICER2;                               /*  ICDICER2        */
+    volatile uint32_t  ICDICER3;                               /*  ICDICER3        */
+    volatile uint32_t  ICDICER4;                               /*  ICDICER4        */
+    volatile uint32_t  ICDICER5;                               /*  ICDICER5        */
+    volatile uint32_t  ICDICER6;                               /*  ICDICER6        */
+    volatile uint32_t  ICDICER7;                               /*  ICDICER7        */
+    volatile uint32_t  ICDICER8;                               /*  ICDICER8        */
+    volatile uint32_t  ICDICER9;                               /*  ICDICER9        */
+    volatile uint32_t  ICDICER10;                              /*  ICDICER10       */
+    volatile uint32_t  ICDICER11;                              /*  ICDICER11       */
+    volatile uint32_t  ICDICER12;                              /*  ICDICER12       */
+    volatile uint32_t  ICDICER13;                              /*  ICDICER13       */
+    volatile uint32_t  ICDICER14;                              /*  ICDICER14       */
+    volatile uint32_t  ICDICER15;                              /*  ICDICER15       */
+    volatile uint32_t  ICDICER16;                              /*  ICDICER16       */
+    volatile uint32_t  ICDICER17;                              /*  ICDICER17       */
+    volatile uint32_t  ICDICER18;                              /*  ICDICER18       */
+    volatile uint8_t   dummy196[52];                           /*                  */
+#define INTC_ICDISPR0_COUNT 19
+    volatile uint32_t  ICDISPR0;                               /*  ICDISPR0        */
+    volatile uint32_t  ICDISPR1;                               /*  ICDISPR1        */
+    volatile uint32_t  ICDISPR2;                               /*  ICDISPR2        */
+    volatile uint32_t  ICDISPR3;                               /*  ICDISPR3        */
+    volatile uint32_t  ICDISPR4;                               /*  ICDISPR4        */
+    volatile uint32_t  ICDISPR5;                               /*  ICDISPR5        */
+    volatile uint32_t  ICDISPR6;                               /*  ICDISPR6        */
+    volatile uint32_t  ICDISPR7;                               /*  ICDISPR7        */
+    volatile uint32_t  ICDISPR8;                               /*  ICDISPR8        */
+    volatile uint32_t  ICDISPR9;                               /*  ICDISPR9        */
+    volatile uint32_t  ICDISPR10;                              /*  ICDISPR10       */
+    volatile uint32_t  ICDISPR11;                              /*  ICDISPR11       */
+    volatile uint32_t  ICDISPR12;                              /*  ICDISPR12       */
+    volatile uint32_t  ICDISPR13;                              /*  ICDISPR13       */
+    volatile uint32_t  ICDISPR14;                              /*  ICDISPR14       */
+    volatile uint32_t  ICDISPR15;                              /*  ICDISPR15       */
+    volatile uint32_t  ICDISPR16;                              /*  ICDISPR16       */
+    volatile uint32_t  ICDISPR17;                              /*  ICDISPR17       */
+    volatile uint32_t  ICDISPR18;                              /*  ICDISPR18       */
+    volatile uint8_t   dummy197[52];                           /*                  */
+#define INTC_ICDICPR0_COUNT 19
+    volatile uint32_t  ICDICPR0;                               /*  ICDICPR0        */
+    volatile uint32_t  ICDICPR1;                               /*  ICDICPR1        */
+    volatile uint32_t  ICDICPR2;                               /*  ICDICPR2        */
+    volatile uint32_t  ICDICPR3;                               /*  ICDICPR3        */
+    volatile uint32_t  ICDICPR4;                               /*  ICDICPR4        */
+    volatile uint32_t  ICDICPR5;                               /*  ICDICPR5        */
+    volatile uint32_t  ICDICPR6;                               /*  ICDICPR6        */
+    volatile uint32_t  ICDICPR7;                               /*  ICDICPR7        */
+    volatile uint32_t  ICDICPR8;                               /*  ICDICPR8        */
+    volatile uint32_t  ICDICPR9;                               /*  ICDICPR9        */
+    volatile uint32_t  ICDICPR10;                              /*  ICDICPR10       */
+    volatile uint32_t  ICDICPR11;                              /*  ICDICPR11       */
+    volatile uint32_t  ICDICPR12;                              /*  ICDICPR12       */
+    volatile uint32_t  ICDICPR13;                              /*  ICDICPR13       */
+    volatile uint32_t  ICDICPR14;                              /*  ICDICPR14       */
+    volatile uint32_t  ICDICPR15;                              /*  ICDICPR15       */
+    volatile uint32_t  ICDICPR16;                              /*  ICDICPR16       */
+    volatile uint32_t  ICDICPR17;                              /*  ICDICPR17       */
+    volatile uint32_t  ICDICPR18;                              /*  ICDICPR18       */
+    volatile uint8_t   dummy198[52];                           /*                  */
+#define INTC_ICDABR0_COUNT 19
+    volatile uint32_t  ICDABR0;                                /*  ICDABR0         */
+    volatile uint32_t  ICDABR1;                                /*  ICDABR1         */
+    volatile uint32_t  ICDABR2;                                /*  ICDABR2         */
+    volatile uint32_t  ICDABR3;                                /*  ICDABR3         */
+    volatile uint32_t  ICDABR4;                                /*  ICDABR4         */
+    volatile uint32_t  ICDABR5;                                /*  ICDABR5         */
+    volatile uint32_t  ICDABR6;                                /*  ICDABR6         */
+    volatile uint32_t  ICDABR7;                                /*  ICDABR7         */
+    volatile uint32_t  ICDABR8;                                /*  ICDABR8         */
+    volatile uint32_t  ICDABR9;                                /*  ICDABR9         */
+    volatile uint32_t  ICDABR10;                               /*  ICDABR10        */
+    volatile uint32_t  ICDABR11;                               /*  ICDABR11        */
+    volatile uint32_t  ICDABR12;                               /*  ICDABR12        */
+    volatile uint32_t  ICDABR13;                               /*  ICDABR13        */
+    volatile uint32_t  ICDABR14;                               /*  ICDABR14        */
+    volatile uint32_t  ICDABR15;                               /*  ICDABR15        */
+    volatile uint32_t  ICDABR16;                               /*  ICDABR16        */
+    volatile uint32_t  ICDABR17;                               /*  ICDABR17        */
+    volatile uint32_t  ICDABR18;                               /*  ICDABR18        */
+    volatile uint8_t   dummy199[180];                          /*                  */
+#define INTC_ICDIPR0_COUNT 147
+    volatile uint32_t  ICDIPR0;                                /*  ICDIPR0         */
+    volatile uint32_t  ICDIPR1;                                /*  ICDIPR1         */
+    volatile uint32_t  ICDIPR2;                                /*  ICDIPR2         */
+    volatile uint32_t  ICDIPR3;                                /*  ICDIPR3         */
+    volatile uint32_t  ICDIPR4;                                /*  ICDIPR4         */
+    volatile uint32_t  ICDIPR5;                                /*  ICDIPR5         */
+    volatile uint32_t  ICDIPR6;                                /*  ICDIPR6         */
+    volatile uint32_t  ICDIPR7;                                /*  ICDIPR7         */
+    volatile uint32_t  ICDIPR8;                                /*  ICDIPR8         */
+    volatile uint32_t  ICDIPR9;                                /*  ICDIPR9         */
+    volatile uint32_t  ICDIPR10;                               /*  ICDIPR10        */
+    volatile uint32_t  ICDIPR11;                               /*  ICDIPR11        */
+    volatile uint32_t  ICDIPR12;                               /*  ICDIPR12        */
+    volatile uint32_t  ICDIPR13;                               /*  ICDIPR13        */
+    volatile uint32_t  ICDIPR14;                               /*  ICDIPR14        */
+    volatile uint32_t  ICDIPR15;                               /*  ICDIPR15        */
+    volatile uint32_t  ICDIPR16;                               /*  ICDIPR16        */
+    volatile uint32_t  ICDIPR17;                               /*  ICDIPR17        */
+    volatile uint32_t  ICDIPR18;                               /*  ICDIPR18        */
+    volatile uint32_t  ICDIPR19;                               /*  ICDIPR19        */
+    volatile uint32_t  ICDIPR20;                               /*  ICDIPR20        */
+    volatile uint32_t  ICDIPR21;                               /*  ICDIPR21        */
+    volatile uint32_t  ICDIPR22;                               /*  ICDIPR22        */
+    volatile uint32_t  ICDIPR23;                               /*  ICDIPR23        */
+    volatile uint32_t  ICDIPR24;                               /*  ICDIPR24        */
+    volatile uint32_t  ICDIPR25;                               /*  ICDIPR25        */
+    volatile uint32_t  ICDIPR26;                               /*  ICDIPR26        */
+    volatile uint32_t  ICDIPR27;                               /*  ICDIPR27        */
+    volatile uint32_t  ICDIPR28;                               /*  ICDIPR28        */
+    volatile uint32_t  ICDIPR29;                               /*  ICDIPR29        */
+    volatile uint32_t  ICDIPR30;                               /*  ICDIPR30        */
+    volatile uint32_t  ICDIPR31;                               /*  ICDIPR31        */
+    volatile uint32_t  ICDIPR32;                               /*  ICDIPR32        */
+    volatile uint32_t  ICDIPR33;                               /*  ICDIPR33        */
+    volatile uint32_t  ICDIPR34;                               /*  ICDIPR34        */
+    volatile uint32_t  ICDIPR35;                               /*  ICDIPR35        */
+    volatile uint32_t  ICDIPR36;                               /*  ICDIPR36        */
+    volatile uint32_t  ICDIPR37;                               /*  ICDIPR37        */
+    volatile uint32_t  ICDIPR38;                               /*  ICDIPR38        */
+    volatile uint32_t  ICDIPR39;                               /*  ICDIPR39        */
+    volatile uint32_t  ICDIPR40;                               /*  ICDIPR40        */
+    volatile uint32_t  ICDIPR41;                               /*  ICDIPR41        */
+    volatile uint32_t  ICDIPR42;                               /*  ICDIPR42        */
+    volatile uint32_t  ICDIPR43;                               /*  ICDIPR43        */
+    volatile uint32_t  ICDIPR44;                               /*  ICDIPR44        */
+    volatile uint32_t  ICDIPR45;                               /*  ICDIPR45        */
+    volatile uint32_t  ICDIPR46;                               /*  ICDIPR46        */
+    volatile uint32_t  ICDIPR47;                               /*  ICDIPR47        */
+    volatile uint32_t  ICDIPR48;                               /*  ICDIPR48        */
+    volatile uint32_t  ICDIPR49;                               /*  ICDIPR49        */
+    volatile uint32_t  ICDIPR50;                               /*  ICDIPR50        */
+    volatile uint32_t  ICDIPR51;                               /*  ICDIPR51        */
+    volatile uint32_t  ICDIPR52;                               /*  ICDIPR52        */
+    volatile uint32_t  ICDIPR53;                               /*  ICDIPR53        */
+    volatile uint32_t  ICDIPR54;                               /*  ICDIPR54        */
+    volatile uint32_t  ICDIPR55;                               /*  ICDIPR55        */
+    volatile uint32_t  ICDIPR56;                               /*  ICDIPR56        */
+    volatile uint32_t  ICDIPR57;                               /*  ICDIPR57        */
+    volatile uint32_t  ICDIPR58;                               /*  ICDIPR58        */
+    volatile uint32_t  ICDIPR59;                               /*  ICDIPR59        */
+    volatile uint32_t  ICDIPR60;                               /*  ICDIPR60        */
+    volatile uint32_t  ICDIPR61;                               /*  ICDIPR61        */
+    volatile uint32_t  ICDIPR62;                               /*  ICDIPR62        */
+    volatile uint32_t  ICDIPR63;                               /*  ICDIPR63        */
+    volatile uint32_t  ICDIPR64;                               /*  ICDIPR64        */
+    volatile uint32_t  ICDIPR65;                               /*  ICDIPR65        */
+    volatile uint32_t  ICDIPR66;                               /*  ICDIPR66        */
+    volatile uint32_t  ICDIPR67;                               /*  ICDIPR67        */
+    volatile uint32_t  ICDIPR68;                               /*  ICDIPR68        */
+    volatile uint32_t  ICDIPR69;                               /*  ICDIPR69        */
+    volatile uint32_t  ICDIPR70;                               /*  ICDIPR70        */
+    volatile uint32_t  ICDIPR71;                               /*  ICDIPR71        */
+    volatile uint32_t  ICDIPR72;                               /*  ICDIPR72        */
+    volatile uint32_t  ICDIPR73;                               /*  ICDIPR73        */
+    volatile uint32_t  ICDIPR74;                               /*  ICDIPR74        */
+    volatile uint32_t  ICDIPR75;                               /*  ICDIPR75        */
+    volatile uint32_t  ICDIPR76;                               /*  ICDIPR76        */
+    volatile uint32_t  ICDIPR77;                               /*  ICDIPR77        */
+    volatile uint32_t  ICDIPR78;                               /*  ICDIPR78        */
+    volatile uint32_t  ICDIPR79;                               /*  ICDIPR79        */
+    volatile uint32_t  ICDIPR80;                               /*  ICDIPR80        */
+    volatile uint32_t  ICDIPR81;                               /*  ICDIPR81        */
+    volatile uint32_t  ICDIPR82;                               /*  ICDIPR82        */
+    volatile uint32_t  ICDIPR83;                               /*  ICDIPR83        */
+    volatile uint32_t  ICDIPR84;                               /*  ICDIPR84        */
+    volatile uint32_t  ICDIPR85;                               /*  ICDIPR85        */
+    volatile uint32_t  ICDIPR86;                               /*  ICDIPR86        */
+    volatile uint32_t  ICDIPR87;                               /*  ICDIPR87        */
+    volatile uint32_t  ICDIPR88;                               /*  ICDIPR88        */
+    volatile uint32_t  ICDIPR89;                               /*  ICDIPR89        */
+    volatile uint32_t  ICDIPR90;                               /*  ICDIPR90        */
+    volatile uint32_t  ICDIPR91;                               /*  ICDIPR91        */
+    volatile uint32_t  ICDIPR92;                               /*  ICDIPR92        */
+    volatile uint32_t  ICDIPR93;                               /*  ICDIPR93        */
+    volatile uint32_t  ICDIPR94;                               /*  ICDIPR94        */
+    volatile uint32_t  ICDIPR95;                               /*  ICDIPR95        */
+    volatile uint32_t  ICDIPR96;                               /*  ICDIPR96        */
+    volatile uint32_t  ICDIPR97;                               /*  ICDIPR97        */
+    volatile uint32_t  ICDIPR98;                               /*  ICDIPR98        */
+    volatile uint32_t  ICDIPR99;                               /*  ICDIPR99        */
+    volatile uint32_t  ICDIPR100;                              /*  ICDIPR100       */
+    volatile uint32_t  ICDIPR101;                              /*  ICDIPR101       */
+    volatile uint32_t  ICDIPR102;                              /*  ICDIPR102       */
+    volatile uint32_t  ICDIPR103;                              /*  ICDIPR103       */
+    volatile uint32_t  ICDIPR104;                              /*  ICDIPR104       */
+    volatile uint32_t  ICDIPR105;                              /*  ICDIPR105       */
+    volatile uint32_t  ICDIPR106;                              /*  ICDIPR106       */
+    volatile uint32_t  ICDIPR107;                              /*  ICDIPR107       */
+    volatile uint32_t  ICDIPR108;                              /*  ICDIPR108       */
+    volatile uint32_t  ICDIPR109;                              /*  ICDIPR109       */
+    volatile uint32_t  ICDIPR110;                              /*  ICDIPR110       */
+    volatile uint32_t  ICDIPR111;                              /*  ICDIPR111       */
+    volatile uint32_t  ICDIPR112;                              /*  ICDIPR112       */
+    volatile uint32_t  ICDIPR113;                              /*  ICDIPR113       */
+    volatile uint32_t  ICDIPR114;                              /*  ICDIPR114       */
+    volatile uint32_t  ICDIPR115;                              /*  ICDIPR115       */
+    volatile uint32_t  ICDIPR116;                              /*  ICDIPR116       */
+    volatile uint32_t  ICDIPR117;                              /*  ICDIPR117       */
+    volatile uint32_t  ICDIPR118;                              /*  ICDIPR118       */
+    volatile uint32_t  ICDIPR119;                              /*  ICDIPR119       */
+    volatile uint32_t  ICDIPR120;                              /*  ICDIPR120       */
+    volatile uint32_t  ICDIPR121;                              /*  ICDIPR121       */
+    volatile uint32_t  ICDIPR122;                              /*  ICDIPR122       */
+    volatile uint32_t  ICDIPR123;                              /*  ICDIPR123       */
+    volatile uint32_t  ICDIPR124;                              /*  ICDIPR124       */
+    volatile uint32_t  ICDIPR125;                              /*  ICDIPR125       */
+    volatile uint32_t  ICDIPR126;                              /*  ICDIPR126       */
+    volatile uint32_t  ICDIPR127;                              /*  ICDIPR127       */
+    volatile uint32_t  ICDIPR128;                              /*  ICDIPR128       */
+    volatile uint32_t  ICDIPR129;                              /*  ICDIPR129       */
+    volatile uint32_t  ICDIPR130;                              /*  ICDIPR130       */
+    volatile uint32_t  ICDIPR131;                              /*  ICDIPR131       */
+    volatile uint32_t  ICDIPR132;                              /*  ICDIPR132       */
+    volatile uint32_t  ICDIPR133;                              /*  ICDIPR133       */
+    volatile uint32_t  ICDIPR134;                              /*  ICDIPR134       */
+    volatile uint32_t  ICDIPR135;                              /*  ICDIPR135       */
+    volatile uint32_t  ICDIPR136;                              /*  ICDIPR136       */
+    volatile uint32_t  ICDIPR137;                              /*  ICDIPR137       */
+    volatile uint32_t  ICDIPR138;                              /*  ICDIPR138       */
+    volatile uint32_t  ICDIPR139;                              /*  ICDIPR139       */
+    volatile uint32_t  ICDIPR140;                              /*  ICDIPR140       */
+    volatile uint32_t  ICDIPR141;                              /*  ICDIPR141       */
+    volatile uint32_t  ICDIPR142;                              /*  ICDIPR142       */
+    volatile uint32_t  ICDIPR143;                              /*  ICDIPR143       */
+    volatile uint32_t  ICDIPR144;                              /*  ICDIPR144       */
+    volatile uint32_t  ICDIPR145;                              /*  ICDIPR145       */
+    volatile uint32_t  ICDIPR146;                              /*  ICDIPR146       */
+    volatile uint8_t   dummy200[436];                          /*                  */
+#define INTC_ICDIPTR0_COUNT 147
+    volatile uint32_t  ICDIPTR0;                               /*  ICDIPTR0        */
+    volatile uint32_t  ICDIPTR1;                               /*  ICDIPTR1        */
+    volatile uint32_t  ICDIPTR2;                               /*  ICDIPTR2        */
+    volatile uint32_t  ICDIPTR3;                               /*  ICDIPTR3        */
+    volatile uint32_t  ICDIPTR4;                               /*  ICDIPTR4        */
+    volatile uint32_t  ICDIPTR5;                               /*  ICDIPTR5        */
+    volatile uint32_t  ICDIPTR6;                               /*  ICDIPTR6        */
+    volatile uint32_t  ICDIPTR7;                               /*  ICDIPTR7        */
+    volatile uint32_t  ICDIPTR8;                               /*  ICDIPTR8        */
+    volatile uint32_t  ICDIPTR9;                               /*  ICDIPTR9        */
+    volatile uint32_t  ICDIPTR10;                              /*  ICDIPTR10       */
+    volatile uint32_t  ICDIPTR11;                              /*  ICDIPTR11       */
+    volatile uint32_t  ICDIPTR12;                              /*  ICDIPTR12       */
+    volatile uint32_t  ICDIPTR13;                              /*  ICDIPTR13       */
+    volatile uint32_t  ICDIPTR14;                              /*  ICDIPTR14       */
+    volatile uint32_t  ICDIPTR15;                              /*  ICDIPTR15       */
+    volatile uint32_t  ICDIPTR16;                              /*  ICDIPTR16       */
+    volatile uint32_t  ICDIPTR17;                              /*  ICDIPTR17       */
+    volatile uint32_t  ICDIPTR18;                              /*  ICDIPTR18       */
+    volatile uint32_t  ICDIPTR19;                              /*  ICDIPTR19       */
+    volatile uint32_t  ICDIPTR20;                              /*  ICDIPTR20       */
+    volatile uint32_t  ICDIPTR21;                              /*  ICDIPTR21       */
+    volatile uint32_t  ICDIPTR22;                              /*  ICDIPTR22       */
+    volatile uint32_t  ICDIPTR23;                              /*  ICDIPTR23       */
+    volatile uint32_t  ICDIPTR24;                              /*  ICDIPTR24       */
+    volatile uint32_t  ICDIPTR25;                              /*  ICDIPTR25       */
+    volatile uint32_t  ICDIPTR26;                              /*  ICDIPTR26       */
+    volatile uint32_t  ICDIPTR27;                              /*  ICDIPTR27       */
+    volatile uint32_t  ICDIPTR28;                              /*  ICDIPTR28       */
+    volatile uint32_t  ICDIPTR29;                              /*  ICDIPTR29       */
+    volatile uint32_t  ICDIPTR30;                              /*  ICDIPTR30       */
+    volatile uint32_t  ICDIPTR31;                              /*  ICDIPTR31       */
+    volatile uint32_t  ICDIPTR32;                              /*  ICDIPTR32       */
+    volatile uint32_t  ICDIPTR33;                              /*  ICDIPTR33       */
+    volatile uint32_t  ICDIPTR34;                              /*  ICDIPTR34       */
+    volatile uint32_t  ICDIPTR35;                              /*  ICDIPTR35       */
+    volatile uint32_t  ICDIPTR36;                              /*  ICDIPTR36       */
+    volatile uint32_t  ICDIPTR37;                              /*  ICDIPTR37       */
+    volatile uint32_t  ICDIPTR38;                              /*  ICDIPTR38       */
+    volatile uint32_t  ICDIPTR39;                              /*  ICDIPTR39       */
+    volatile uint32_t  ICDIPTR40;                              /*  ICDIPTR40       */
+    volatile uint32_t  ICDIPTR41;                              /*  ICDIPTR41       */
+    volatile uint32_t  ICDIPTR42;                              /*  ICDIPTR42       */
+    volatile uint32_t  ICDIPTR43;                              /*  ICDIPTR43       */
+    volatile uint32_t  ICDIPTR44;                              /*  ICDIPTR44       */
+    volatile uint32_t  ICDIPTR45;                              /*  ICDIPTR45       */
+    volatile uint32_t  ICDIPTR46;                              /*  ICDIPTR46       */
+    volatile uint32_t  ICDIPTR47;                              /*  ICDIPTR47       */
+    volatile uint32_t  ICDIPTR48;                              /*  ICDIPTR48       */
+    volatile uint32_t  ICDIPTR49;                              /*  ICDIPTR49       */
+    volatile uint32_t  ICDIPTR50;                              /*  ICDIPTR50       */
+    volatile uint32_t  ICDIPTR51;                              /*  ICDIPTR51       */
+    volatile uint32_t  ICDIPTR52;                              /*  ICDIPTR52       */
+    volatile uint32_t  ICDIPTR53;                              /*  ICDIPTR53       */
+    volatile uint32_t  ICDIPTR54;                              /*  ICDIPTR54       */
+    volatile uint32_t  ICDIPTR55;                              /*  ICDIPTR55       */
+    volatile uint32_t  ICDIPTR56;                              /*  ICDIPTR56       */
+    volatile uint32_t  ICDIPTR57;                              /*  ICDIPTR57       */
+    volatile uint32_t  ICDIPTR58;                              /*  ICDIPTR58       */
+    volatile uint32_t  ICDIPTR59;                              /*  ICDIPTR59       */
+    volatile uint32_t  ICDIPTR60;                              /*  ICDIPTR60       */
+    volatile uint32_t  ICDIPTR61;                              /*  ICDIPTR61       */
+    volatile uint32_t  ICDIPTR62;                              /*  ICDIPTR62       */
+    volatile uint32_t  ICDIPTR63;                              /*  ICDIPTR63       */
+    volatile uint32_t  ICDIPTR64;                              /*  ICDIPTR64       */
+    volatile uint32_t  ICDIPTR65;                              /*  ICDIPTR65       */
+    volatile uint32_t  ICDIPTR66;                              /*  ICDIPTR66       */
+    volatile uint32_t  ICDIPTR67;                              /*  ICDIPTR67       */
+    volatile uint32_t  ICDIPTR68;                              /*  ICDIPTR68       */
+    volatile uint32_t  ICDIPTR69;                              /*  ICDIPTR69       */
+    volatile uint32_t  ICDIPTR70;                              /*  ICDIPTR70       */
+    volatile uint32_t  ICDIPTR71;                              /*  ICDIPTR71       */
+    volatile uint32_t  ICDIPTR72;                              /*  ICDIPTR72       */
+    volatile uint32_t  ICDIPTR73;                              /*  ICDIPTR73       */
+    volatile uint32_t  ICDIPTR74;                              /*  ICDIPTR74       */
+    volatile uint32_t  ICDIPTR75;                              /*  ICDIPTR75       */
+    volatile uint32_t  ICDIPTR76;                              /*  ICDIPTR76       */
+    volatile uint32_t  ICDIPTR77;                              /*  ICDIPTR77       */
+    volatile uint32_t  ICDIPTR78;                              /*  ICDIPTR78       */
+    volatile uint32_t  ICDIPTR79;                              /*  ICDIPTR79       */
+    volatile uint32_t  ICDIPTR80;                              /*  ICDIPTR80       */
+    volatile uint32_t  ICDIPTR81;                              /*  ICDIPTR81       */
+    volatile uint32_t  ICDIPTR82;                              /*  ICDIPTR82       */
+    volatile uint32_t  ICDIPTR83;                              /*  ICDIPTR83       */
+    volatile uint32_t  ICDIPTR84;                              /*  ICDIPTR84       */
+    volatile uint32_t  ICDIPTR85;                              /*  ICDIPTR85       */
+    volatile uint32_t  ICDIPTR86;                              /*  ICDIPTR86       */
+    volatile uint32_t  ICDIPTR87;                              /*  ICDIPTR87       */
+    volatile uint32_t  ICDIPTR88;                              /*  ICDIPTR88       */
+    volatile uint32_t  ICDIPTR89;                              /*  ICDIPTR89       */
+    volatile uint32_t  ICDIPTR90;                              /*  ICDIPTR90       */
+    volatile uint32_t  ICDIPTR91;                              /*  ICDIPTR91       */
+    volatile uint32_t  ICDIPTR92;                              /*  ICDIPTR92       */
+    volatile uint32_t  ICDIPTR93;                              /*  ICDIPTR93       */
+    volatile uint32_t  ICDIPTR94;                              /*  ICDIPTR94       */
+    volatile uint32_t  ICDIPTR95;                              /*  ICDIPTR95       */
+    volatile uint32_t  ICDIPTR96;                              /*  ICDIPTR96       */
+    volatile uint32_t  ICDIPTR97;                              /*  ICDIPTR97       */
+    volatile uint32_t  ICDIPTR98;                              /*  ICDIPTR98       */
+    volatile uint32_t  ICDIPTR99;                              /*  ICDIPTR99       */
+    volatile uint32_t  ICDIPTR100;                             /*  ICDIPTR100      */
+    volatile uint32_t  ICDIPTR101;                             /*  ICDIPTR101      */
+    volatile uint32_t  ICDIPTR102;                             /*  ICDIPTR102      */
+    volatile uint32_t  ICDIPTR103;                             /*  ICDIPTR103      */
+    volatile uint32_t  ICDIPTR104;                             /*  ICDIPTR104      */
+    volatile uint32_t  ICDIPTR105;                             /*  ICDIPTR105      */
+    volatile uint32_t  ICDIPTR106;                             /*  ICDIPTR106      */
+    volatile uint32_t  ICDIPTR107;                             /*  ICDIPTR107      */
+    volatile uint32_t  ICDIPTR108;                             /*  ICDIPTR108      */
+    volatile uint32_t  ICDIPTR109;                             /*  ICDIPTR109      */
+    volatile uint32_t  ICDIPTR110;                             /*  ICDIPTR110      */
+    volatile uint32_t  ICDIPTR111;                             /*  ICDIPTR111      */
+    volatile uint32_t  ICDIPTR112;                             /*  ICDIPTR112      */
+    volatile uint32_t  ICDIPTR113;                             /*  ICDIPTR113      */
+    volatile uint32_t  ICDIPTR114;                             /*  ICDIPTR114      */
+    volatile uint32_t  ICDIPTR115;                             /*  ICDIPTR115      */
+    volatile uint32_t  ICDIPTR116;                             /*  ICDIPTR116      */
+    volatile uint32_t  ICDIPTR117;                             /*  ICDIPTR117      */
+    volatile uint32_t  ICDIPTR118;                             /*  ICDIPTR118      */
+    volatile uint32_t  ICDIPTR119;                             /*  ICDIPTR119      */
+    volatile uint32_t  ICDIPTR120;                             /*  ICDIPTR120      */
+    volatile uint32_t  ICDIPTR121;                             /*  ICDIPTR121      */
+    volatile uint32_t  ICDIPTR122;                             /*  ICDIPTR122      */
+    volatile uint32_t  ICDIPTR123;                             /*  ICDIPTR123      */
+    volatile uint32_t  ICDIPTR124;                             /*  ICDIPTR124      */
+    volatile uint32_t  ICDIPTR125;                             /*  ICDIPTR125      */
+    volatile uint32_t  ICDIPTR126;                             /*  ICDIPTR126      */
+    volatile uint32_t  ICDIPTR127;                             /*  ICDIPTR127      */
+    volatile uint32_t  ICDIPTR128;                             /*  ICDIPTR128      */
+    volatile uint32_t  ICDIPTR129;                             /*  ICDIPTR129      */
+    volatile uint32_t  ICDIPTR130;                             /*  ICDIPTR130      */
+    volatile uint32_t  ICDIPTR131;                             /*  ICDIPTR131      */
+    volatile uint32_t  ICDIPTR132;                             /*  ICDIPTR132      */
+    volatile uint32_t  ICDIPTR133;                             /*  ICDIPTR133      */
+    volatile uint32_t  ICDIPTR134;                             /*  ICDIPTR134      */
+    volatile uint32_t  ICDIPTR135;                             /*  ICDIPTR135      */
+    volatile uint32_t  ICDIPTR136;                             /*  ICDIPTR136      */
+    volatile uint32_t  ICDIPTR137;                             /*  ICDIPTR137      */
+    volatile uint32_t  ICDIPTR138;                             /*  ICDIPTR138      */
+    volatile uint32_t  ICDIPTR139;                             /*  ICDIPTR139      */
+    volatile uint32_t  ICDIPTR140;                             /*  ICDIPTR140      */
+    volatile uint32_t  ICDIPTR141;                             /*  ICDIPTR141      */
+    volatile uint32_t  ICDIPTR142;                             /*  ICDIPTR142      */
+    volatile uint32_t  ICDIPTR143;                             /*  ICDIPTR143      */
+    volatile uint32_t  ICDIPTR144;                             /*  ICDIPTR144      */
+    volatile uint32_t  ICDIPTR145;                             /*  ICDIPTR145      */
+    volatile uint32_t  ICDIPTR146;                             /*  ICDIPTR146      */
+    volatile uint8_t   dummy201[436];                          /*                  */
+#define INTC_ICDICFR0_COUNT 37
+    volatile uint32_t  ICDICFR0;                               /*  ICDICFR0        */
+    volatile uint32_t  ICDICFR1;                               /*  ICDICFR1        */
+    volatile uint32_t  ICDICFR2;                               /*  ICDICFR2        */
+    volatile uint32_t  ICDICFR3;                               /*  ICDICFR3        */
+    volatile uint32_t  ICDICFR4;                               /*  ICDICFR4        */
+    volatile uint32_t  ICDICFR5;                               /*  ICDICFR5        */
+    volatile uint32_t  ICDICFR6;                               /*  ICDICFR6        */
+    volatile uint32_t  ICDICFR7;                               /*  ICDICFR7        */
+    volatile uint32_t  ICDICFR8;                               /*  ICDICFR8        */
+    volatile uint32_t  ICDICFR9;                               /*  ICDICFR9        */
+    volatile uint32_t  ICDICFR10;                              /*  ICDICFR10       */
+    volatile uint32_t  ICDICFR11;                              /*  ICDICFR11       */
+    volatile uint32_t  ICDICFR12;                              /*  ICDICFR12       */
+    volatile uint32_t  ICDICFR13;                              /*  ICDICFR13       */
+    volatile uint32_t  ICDICFR14;                              /*  ICDICFR14       */
+    volatile uint32_t  ICDICFR15;                              /*  ICDICFR15       */
+    volatile uint32_t  ICDICFR16;                              /*  ICDICFR16       */
+    volatile uint32_t  ICDICFR17;                              /*  ICDICFR17       */
+    volatile uint32_t  ICDICFR18;                              /*  ICDICFR18       */
+    volatile uint32_t  ICDICFR19;                              /*  ICDICFR19       */
+    volatile uint32_t  ICDICFR20;                              /*  ICDICFR20       */
+    volatile uint32_t  ICDICFR21;                              /*  ICDICFR21       */
+    volatile uint32_t  ICDICFR22;                              /*  ICDICFR22       */
+    volatile uint32_t  ICDICFR23;                              /*  ICDICFR23       */
+    volatile uint32_t  ICDICFR24;                              /*  ICDICFR24       */
+    volatile uint32_t  ICDICFR25;                              /*  ICDICFR25       */
+    volatile uint32_t  ICDICFR26;                              /*  ICDICFR26       */
+    volatile uint32_t  ICDICFR27;                              /*  ICDICFR27       */
+    volatile uint32_t  ICDICFR28;                              /*  ICDICFR28       */
+    volatile uint32_t  ICDICFR29;                              /*  ICDICFR29       */
+    volatile uint32_t  ICDICFR30;                              /*  ICDICFR30       */
+    volatile uint32_t  ICDICFR31;                              /*  ICDICFR31       */
+    volatile uint32_t  ICDICFR32;                              /*  ICDICFR32       */
+    volatile uint32_t  ICDICFR33;                              /*  ICDICFR33       */
+    volatile uint32_t  ICDICFR34;                              /*  ICDICFR34       */
+    volatile uint32_t  ICDICFR35;                              /*  ICDICFR35       */
+    volatile uint32_t  ICDICFR36;                              /*  ICDICFR36       */
+    volatile uint8_t   dummy202[108];                          /*                  */
+    volatile uint32_t  PPI_STATUS;                             /*  PPI_STATUS      */
+#define INTC_SPI_STATUS0_COUNT 17
+    volatile uint32_t  SPI_STATUS0;                            /*  SPI_STATUS0     */
+    volatile uint32_t  SPI_STATUS1;                            /*  SPI_STATUS1     */
+    volatile uint32_t  SPI_STATUS2;                            /*  SPI_STATUS2     */
+    volatile uint32_t  SPI_STATUS3;                            /*  SPI_STATUS3     */
+    volatile uint32_t  SPI_STATUS4;                            /*  SPI_STATUS4     */
+    volatile uint32_t  SPI_STATUS5;                            /*  SPI_STATUS5     */
+    volatile uint32_t  SPI_STATUS6;                            /*  SPI_STATUS6     */
+    volatile uint32_t  SPI_STATUS7;                            /*  SPI_STATUS7     */
+    volatile uint32_t  SPI_STATUS8;                            /*  SPI_STATUS8     */
+    volatile uint32_t  SPI_STATUS9;                            /*  SPI_STATUS9     */
+    volatile uint32_t  SPI_STATUS10;                           /*  SPI_STATUS10    */
+    volatile uint32_t  SPI_STATUS11;                           /*  SPI_STATUS11    */
+    volatile uint32_t  SPI_STATUS12;                           /*  SPI_STATUS12    */
+    volatile uint32_t  SPI_STATUS13;                           /*  SPI_STATUS13    */
+    volatile uint32_t  SPI_STATUS14;                           /*  SPI_STATUS14    */
+    volatile uint32_t  SPI_STATUS15;                           /*  SPI_STATUS15    */
+    volatile uint32_t  SPI_STATUS16;                           /*  SPI_STATUS16    */
+    volatile uint8_t   dummy203[440];                          /*                  */
+    volatile uint32_t  ICDSGIR;                                /*  ICDSGIR         */
+    volatile uint8_t   dummy204[252];                          /*                  */
+    volatile uint32_t  ICCICR;                                 /*  ICCICR          */
+    volatile uint32_t  ICCPMR;                                 /*  ICCPMR          */
+    volatile uint32_t  ICCBPR;                                 /*  ICCBPR          */
+    volatile uint32_t  ICCIAR;                                 /*  ICCIAR          */
+    volatile uint32_t  ICCEOIR;                                /*  ICCEOIR         */
+    volatile uint32_t  ICCRPR;                                 /*  ICCRPR          */
+    volatile uint32_t  ICCHPIR;                                /*  ICCHPIR         */
+    volatile uint32_t  ICCABPR;                                /*  ICCABPR         */
+    volatile uint8_t   dummy205[220];                          /*                  */
+    volatile uint32_t  ICCIIDR;                                /*  ICCIIDR         */
+    volatile uint8_t   dummy206[350148352];                    /*                  */
+    volatile uint16_t ICR0;                                   /*  ICR0            */
+    volatile uint16_t ICR1;                                   /*  ICR1            */
+    volatile uint16_t IRQRR;                                  /*  IRQRR           */
+};
+
+
+#define INTC    (*(struct st_intc    *)0xE8201000uL) /* INTC */
+
+
+#define INTCICDDCR INTC.ICDDCR
+#define INTCICDICTR INTC.ICDICTR
+#define INTCICDIIDR INTC.ICDIIDR
+#define INTCICDISR0 INTC.ICDISR0
+#define INTCICDISR1 INTC.ICDISR1
+#define INTCICDISR2 INTC.ICDISR2
+#define INTCICDISR3 INTC.ICDISR3
+#define INTCICDISR4 INTC.ICDISR4
+#define INTCICDISR5 INTC.ICDISR5
+#define INTCICDISR6 INTC.ICDISR6
+#define INTCICDISR7 INTC.ICDISR7
+#define INTCICDISR8 INTC.ICDISR8
+#define INTCICDISR9 INTC.ICDISR9
+#define INTCICDISR10 INTC.ICDISR10
+#define INTCICDISR11 INTC.ICDISR11
+#define INTCICDISR12 INTC.ICDISR12
+#define INTCICDISR13 INTC.ICDISR13
+#define INTCICDISR14 INTC.ICDISR14
+#define INTCICDISR15 INTC.ICDISR15
+#define INTCICDISR16 INTC.ICDISR16
+#define INTCICDISR17 INTC.ICDISR17
+#define INTCICDISR18 INTC.ICDISR18
+#define INTCICDISER0 INTC.ICDISER0
+#define INTCICDISER1 INTC.ICDISER1
+#define INTCICDISER2 INTC.ICDISER2
+#define INTCICDISER3 INTC.ICDISER3
+#define INTCICDISER4 INTC.ICDISER4
+#define INTCICDISER5 INTC.ICDISER5
+#define INTCICDISER6 INTC.ICDISER6
+#define INTCICDISER7 INTC.ICDISER7
+#define INTCICDISER8 INTC.ICDISER8
+#define INTCICDISER9 INTC.ICDISER9
+#define INTCICDISER10 INTC.ICDISER10
+#define INTCICDISER11 INTC.ICDISER11
+#define INTCICDISER12 INTC.ICDISER12
+#define INTCICDISER13 INTC.ICDISER13
+#define INTCICDISER14 INTC.ICDISER14
+#define INTCICDISER15 INTC.ICDISER15
+#define INTCICDISER16 INTC.ICDISER16
+#define INTCICDISER17 INTC.ICDISER17
+#define INTCICDISER18 INTC.ICDISER18
+#define INTCICDICER0 INTC.ICDICER0
+#define INTCICDICER1 INTC.ICDICER1
+#define INTCICDICER2 INTC.ICDICER2
+#define INTCICDICER3 INTC.ICDICER3
+#define INTCICDICER4 INTC.ICDICER4
+#define INTCICDICER5 INTC.ICDICER5
+#define INTCICDICER6 INTC.ICDICER6
+#define INTCICDICER7 INTC.ICDICER7
+#define INTCICDICER8 INTC.ICDICER8
+#define INTCICDICER9 INTC.ICDICER9
+#define INTCICDICER10 INTC.ICDICER10
+#define INTCICDICER11 INTC.ICDICER11
+#define INTCICDICER12 INTC.ICDICER12
+#define INTCICDICER13 INTC.ICDICER13
+#define INTCICDICER14 INTC.ICDICER14
+#define INTCICDICER15 INTC.ICDICER15
+#define INTCICDICER16 INTC.ICDICER16
+#define INTCICDICER17 INTC.ICDICER17
+#define INTCICDICER18 INTC.ICDICER18
+#define INTCICDISPR0 INTC.ICDISPR0
+#define INTCICDISPR1 INTC.ICDISPR1
+#define INTCICDISPR2 INTC.ICDISPR2
+#define INTCICDISPR3 INTC.ICDISPR3
+#define INTCICDISPR4 INTC.ICDISPR4
+#define INTCICDISPR5 INTC.ICDISPR5
+#define INTCICDISPR6 INTC.ICDISPR6
+#define INTCICDISPR7 INTC.ICDISPR7
+#define INTCICDISPR8 INTC.ICDISPR8
+#define INTCICDISPR9 INTC.ICDISPR9
+#define INTCICDISPR10 INTC.ICDISPR10
+#define INTCICDISPR11 INTC.ICDISPR11
+#define INTCICDISPR12 INTC.ICDISPR12
+#define INTCICDISPR13 INTC.ICDISPR13
+#define INTCICDISPR14 INTC.ICDISPR14
+#define INTCICDISPR15 INTC.ICDISPR15
+#define INTCICDISPR16 INTC.ICDISPR16
+#define INTCICDISPR17 INTC.ICDISPR17
+#define INTCICDISPR18 INTC.ICDISPR18
+#define INTCICDICPR0 INTC.ICDICPR0
+#define INTCICDICPR1 INTC.ICDICPR1
+#define INTCICDICPR2 INTC.ICDICPR2
+#define INTCICDICPR3 INTC.ICDICPR3
+#define INTCICDICPR4 INTC.ICDICPR4
+#define INTCICDICPR5 INTC.ICDICPR5
+#define INTCICDICPR6 INTC.ICDICPR6
+#define INTCICDICPR7 INTC.ICDICPR7
+#define INTCICDICPR8 INTC.ICDICPR8
+#define INTCICDICPR9 INTC.ICDICPR9
+#define INTCICDICPR10 INTC.ICDICPR10
+#define INTCICDICPR11 INTC.ICDICPR11
+#define INTCICDICPR12 INTC.ICDICPR12
+#define INTCICDICPR13 INTC.ICDICPR13
+#define INTCICDICPR14 INTC.ICDICPR14
+#define INTCICDICPR15 INTC.ICDICPR15
+#define INTCICDICPR16 INTC.ICDICPR16
+#define INTCICDICPR17 INTC.ICDICPR17
+#define INTCICDICPR18 INTC.ICDICPR18
+#define INTCICDABR0 INTC.ICDABR0
+#define INTCICDABR1 INTC.ICDABR1
+#define INTCICDABR2 INTC.ICDABR2
+#define INTCICDABR3 INTC.ICDABR3
+#define INTCICDABR4 INTC.ICDABR4
+#define INTCICDABR5 INTC.ICDABR5
+#define INTCICDABR6 INTC.ICDABR6
+#define INTCICDABR7 INTC.ICDABR7
+#define INTCICDABR8 INTC.ICDABR8
+#define INTCICDABR9 INTC.ICDABR9
+#define INTCICDABR10 INTC.ICDABR10
+#define INTCICDABR11 INTC.ICDABR11
+#define INTCICDABR12 INTC.ICDABR12
+#define INTCICDABR13 INTC.ICDABR13
+#define INTCICDABR14 INTC.ICDABR14
+#define INTCICDABR15 INTC.ICDABR15
+#define INTCICDABR16 INTC.ICDABR16
+#define INTCICDABR17 INTC.ICDABR17
+#define INTCICDABR18 INTC.ICDABR18
+#define INTCICDIPR0 INTC.ICDIPR0
+#define INTCICDIPR1 INTC.ICDIPR1
+#define INTCICDIPR2 INTC.ICDIPR2
+#define INTCICDIPR3 INTC.ICDIPR3
+#define INTCICDIPR4 INTC.ICDIPR4
+#define INTCICDIPR5 INTC.ICDIPR5
+#define INTCICDIPR6 INTC.ICDIPR6
+#define INTCICDIPR7 INTC.ICDIPR7
+#define INTCICDIPR8 INTC.ICDIPR8
+#define INTCICDIPR9 INTC.ICDIPR9
+#define INTCICDIPR10 INTC.ICDIPR10
+#define INTCICDIPR11 INTC.ICDIPR11
+#define INTCICDIPR12 INTC.ICDIPR12
+#define INTCICDIPR13 INTC.ICDIPR13
+#define INTCICDIPR14 INTC.ICDIPR14
+#define INTCICDIPR15 INTC.ICDIPR15
+#define INTCICDIPR16 INTC.ICDIPR16
+#define INTCICDIPR17 INTC.ICDIPR17
+#define INTCICDIPR18 INTC.ICDIPR18
+#define INTCICDIPR19 INTC.ICDIPR19
+#define INTCICDIPR20 INTC.ICDIPR20
+#define INTCICDIPR21 INTC.ICDIPR21
+#define INTCICDIPR22 INTC.ICDIPR22
+#define INTCICDIPR23 INTC.ICDIPR23
+#define INTCICDIPR24 INTC.ICDIPR24
+#define INTCICDIPR25 INTC.ICDIPR25
+#define INTCICDIPR26 INTC.ICDIPR26
+#define INTCICDIPR27 INTC.ICDIPR27
+#define INTCICDIPR28 INTC.ICDIPR28
+#define INTCICDIPR29 INTC.ICDIPR29
+#define INTCICDIPR30 INTC.ICDIPR30
+#define INTCICDIPR31 INTC.ICDIPR31
+#define INTCICDIPR32 INTC.ICDIPR32
+#define INTCICDIPR33 INTC.ICDIPR33
+#define INTCICDIPR34 INTC.ICDIPR34
+#define INTCICDIPR35 INTC.ICDIPR35
+#define INTCICDIPR36 INTC.ICDIPR36
+#define INTCICDIPR37 INTC.ICDIPR37
+#define INTCICDIPR38 INTC.ICDIPR38
+#define INTCICDIPR39 INTC.ICDIPR39
+#define INTCICDIPR40 INTC.ICDIPR40
+#define INTCICDIPR41 INTC.ICDIPR41
+#define INTCICDIPR42 INTC.ICDIPR42
+#define INTCICDIPR43 INTC.ICDIPR43
+#define INTCICDIPR44 INTC.ICDIPR44
+#define INTCICDIPR45 INTC.ICDIPR45
+#define INTCICDIPR46 INTC.ICDIPR46
+#define INTCICDIPR47 INTC.ICDIPR47
+#define INTCICDIPR48 INTC.ICDIPR48
+#define INTCICDIPR49 INTC.ICDIPR49
+#define INTCICDIPR50 INTC.ICDIPR50
+#define INTCICDIPR51 INTC.ICDIPR51
+#define INTCICDIPR52 INTC.ICDIPR52
+#define INTCICDIPR53 INTC.ICDIPR53
+#define INTCICDIPR54 INTC.ICDIPR54
+#define INTCICDIPR55 INTC.ICDIPR55
+#define INTCICDIPR56 INTC.ICDIPR56
+#define INTCICDIPR57 INTC.ICDIPR57
+#define INTCICDIPR58 INTC.ICDIPR58
+#define INTCICDIPR59 INTC.ICDIPR59
+#define INTCICDIPR60 INTC.ICDIPR60
+#define INTCICDIPR61 INTC.ICDIPR61
+#define INTCICDIPR62 INTC.ICDIPR62
+#define INTCICDIPR63 INTC.ICDIPR63
+#define INTCICDIPR64 INTC.ICDIPR64
+#define INTCICDIPR65 INTC.ICDIPR65
+#define INTCICDIPR66 INTC.ICDIPR66
+#define INTCICDIPR67 INTC.ICDIPR67
+#define INTCICDIPR68 INTC.ICDIPR68
+#define INTCICDIPR69 INTC.ICDIPR69
+#define INTCICDIPR70 INTC.ICDIPR70
+#define INTCICDIPR71 INTC.ICDIPR71
+#define INTCICDIPR72 INTC.ICDIPR72
+#define INTCICDIPR73 INTC.ICDIPR73
+#define INTCICDIPR74 INTC.ICDIPR74
+#define INTCICDIPR75 INTC.ICDIPR75
+#define INTCICDIPR76 INTC.ICDIPR76
+#define INTCICDIPR77 INTC.ICDIPR77
+#define INTCICDIPR78 INTC.ICDIPR78
+#define INTCICDIPR79 INTC.ICDIPR79
+#define INTCICDIPR80 INTC.ICDIPR80
+#define INTCICDIPR81 INTC.ICDIPR81
+#define INTCICDIPR82 INTC.ICDIPR82
+#define INTCICDIPR83 INTC.ICDIPR83
+#define INTCICDIPR84 INTC.ICDIPR84
+#define INTCICDIPR85 INTC.ICDIPR85
+#define INTCICDIPR86 INTC.ICDIPR86
+#define INTCICDIPR87 INTC.ICDIPR87
+#define INTCICDIPR88 INTC.ICDIPR88
+#define INTCICDIPR89 INTC.ICDIPR89
+#define INTCICDIPR90 INTC.ICDIPR90
+#define INTCICDIPR91 INTC.ICDIPR91
+#define INTCICDIPR92 INTC.ICDIPR92
+#define INTCICDIPR93 INTC.ICDIPR93
+#define INTCICDIPR94 INTC.ICDIPR94
+#define INTCICDIPR95 INTC.ICDIPR95
+#define INTCICDIPR96 INTC.ICDIPR96
+#define INTCICDIPR97 INTC.ICDIPR97
+#define INTCICDIPR98 INTC.ICDIPR98
+#define INTCICDIPR99 INTC.ICDIPR99
+#define INTCICDIPR100 INTC.ICDIPR100
+#define INTCICDIPR101 INTC.ICDIPR101
+#define INTCICDIPR102 INTC.ICDIPR102
+#define INTCICDIPR103 INTC.ICDIPR103
+#define INTCICDIPR104 INTC.ICDIPR104
+#define INTCICDIPR105 INTC.ICDIPR105
+#define INTCICDIPR106 INTC.ICDIPR106
+#define INTCICDIPR107 INTC.ICDIPR107
+#define INTCICDIPR108 INTC.ICDIPR108
+#define INTCICDIPR109 INTC.ICDIPR109
+#define INTCICDIPR110 INTC.ICDIPR110
+#define INTCICDIPR111 INTC.ICDIPR111
+#define INTCICDIPR112 INTC.ICDIPR112
+#define INTCICDIPR113 INTC.ICDIPR113
+#define INTCICDIPR114 INTC.ICDIPR114
+#define INTCICDIPR115 INTC.ICDIPR115
+#define INTCICDIPR116 INTC.ICDIPR116
+#define INTCICDIPR117 INTC.ICDIPR117
+#define INTCICDIPR118 INTC.ICDIPR118
+#define INTCICDIPR119 INTC.ICDIPR119
+#define INTCICDIPR120 INTC.ICDIPR120
+#define INTCICDIPR121 INTC.ICDIPR121
+#define INTCICDIPR122 INTC.ICDIPR122
+#define INTCICDIPR123 INTC.ICDIPR123
+#define INTCICDIPR124 INTC.ICDIPR124
+#define INTCICDIPR125 INTC.ICDIPR125
+#define INTCICDIPR126 INTC.ICDIPR126
+#define INTCICDIPR127 INTC.ICDIPR127
+#define INTCICDIPR128 INTC.ICDIPR128
+#define INTCICDIPR129 INTC.ICDIPR129
+#define INTCICDIPR130 INTC.ICDIPR130
+#define INTCICDIPR131 INTC.ICDIPR131
+#define INTCICDIPR132 INTC.ICDIPR132
+#define INTCICDIPR133 INTC.ICDIPR133
+#define INTCICDIPR134 INTC.ICDIPR134
+#define INTCICDIPR135 INTC.ICDIPR135
+#define INTCICDIPR136 INTC.ICDIPR136
+#define INTCICDIPR137 INTC.ICDIPR137
+#define INTCICDIPR138 INTC.ICDIPR138
+#define INTCICDIPR139 INTC.ICDIPR139
+#define INTCICDIPR140 INTC.ICDIPR140
+#define INTCICDIPR141 INTC.ICDIPR141
+#define INTCICDIPR142 INTC.ICDIPR142
+#define INTCICDIPR143 INTC.ICDIPR143
+#define INTCICDIPR144 INTC.ICDIPR144
+#define INTCICDIPR145 INTC.ICDIPR145
+#define INTCICDIPR146 INTC.ICDIPR146
+#define INTCICDIPTR0 INTC.ICDIPTR0
+#define INTCICDIPTR1 INTC.ICDIPTR1
+#define INTCICDIPTR2 INTC.ICDIPTR2
+#define INTCICDIPTR3 INTC.ICDIPTR3
+#define INTCICDIPTR4 INTC.ICDIPTR4
+#define INTCICDIPTR5 INTC.ICDIPTR5
+#define INTCICDIPTR6 INTC.ICDIPTR6
+#define INTCICDIPTR7 INTC.ICDIPTR7
+#define INTCICDIPTR8 INTC.ICDIPTR8
+#define INTCICDIPTR9 INTC.ICDIPTR9
+#define INTCICDIPTR10 INTC.ICDIPTR10
+#define INTCICDIPTR11 INTC.ICDIPTR11
+#define INTCICDIPTR12 INTC.ICDIPTR12
+#define INTCICDIPTR13 INTC.ICDIPTR13
+#define INTCICDIPTR14 INTC.ICDIPTR14
+#define INTCICDIPTR15 INTC.ICDIPTR15
+#define INTCICDIPTR16 INTC.ICDIPTR16
+#define INTCICDIPTR17 INTC.ICDIPTR17
+#define INTCICDIPTR18 INTC.ICDIPTR18
+#define INTCICDIPTR19 INTC.ICDIPTR19
+#define INTCICDIPTR20 INTC.ICDIPTR20
+#define INTCICDIPTR21 INTC.ICDIPTR21
+#define INTCICDIPTR22 INTC.ICDIPTR22
+#define INTCICDIPTR23 INTC.ICDIPTR23
+#define INTCICDIPTR24 INTC.ICDIPTR24
+#define INTCICDIPTR25 INTC.ICDIPTR25
+#define INTCICDIPTR26 INTC.ICDIPTR26
+#define INTCICDIPTR27 INTC.ICDIPTR27
+#define INTCICDIPTR28 INTC.ICDIPTR28
+#define INTCICDIPTR29 INTC.ICDIPTR29
+#define INTCICDIPTR30 INTC.ICDIPTR30
+#define INTCICDIPTR31 INTC.ICDIPTR31
+#define INTCICDIPTR32 INTC.ICDIPTR32
+#define INTCICDIPTR33 INTC.ICDIPTR33
+#define INTCICDIPTR34 INTC.ICDIPTR34
+#define INTCICDIPTR35 INTC.ICDIPTR35
+#define INTCICDIPTR36 INTC.ICDIPTR36
+#define INTCICDIPTR37 INTC.ICDIPTR37
+#define INTCICDIPTR38 INTC.ICDIPTR38
+#define INTCICDIPTR39 INTC.ICDIPTR39
+#define INTCICDIPTR40 INTC.ICDIPTR40
+#define INTCICDIPTR41 INTC.ICDIPTR41
+#define INTCICDIPTR42 INTC.ICDIPTR42
+#define INTCICDIPTR43 INTC.ICDIPTR43
+#define INTCICDIPTR44 INTC.ICDIPTR44
+#define INTCICDIPTR45 INTC.ICDIPTR45
+#define INTCICDIPTR46 INTC.ICDIPTR46
+#define INTCICDIPTR47 INTC.ICDIPTR47
+#define INTCICDIPTR48 INTC.ICDIPTR48
+#define INTCICDIPTR49 INTC.ICDIPTR49
+#define INTCICDIPTR50 INTC.ICDIPTR50
+#define INTCICDIPTR51 INTC.ICDIPTR51
+#define INTCICDIPTR52 INTC.ICDIPTR52
+#define INTCICDIPTR53 INTC.ICDIPTR53
+#define INTCICDIPTR54 INTC.ICDIPTR54
+#define INTCICDIPTR55 INTC.ICDIPTR55
+#define INTCICDIPTR56 INTC.ICDIPTR56
+#define INTCICDIPTR57 INTC.ICDIPTR57
+#define INTCICDIPTR58 INTC.ICDIPTR58
+#define INTCICDIPTR59 INTC.ICDIPTR59
+#define INTCICDIPTR60 INTC.ICDIPTR60
+#define INTCICDIPTR61 INTC.ICDIPTR61
+#define INTCICDIPTR62 INTC.ICDIPTR62
+#define INTCICDIPTR63 INTC.ICDIPTR63
+#define INTCICDIPTR64 INTC.ICDIPTR64
+#define INTCICDIPTR65 INTC.ICDIPTR65
+#define INTCICDIPTR66 INTC.ICDIPTR66
+#define INTCICDIPTR67 INTC.ICDIPTR67
+#define INTCICDIPTR68 INTC.ICDIPTR68
+#define INTCICDIPTR69 INTC.ICDIPTR69
+#define INTCICDIPTR70 INTC.ICDIPTR70
+#define INTCICDIPTR71 INTC.ICDIPTR71
+#define INTCICDIPTR72 INTC.ICDIPTR72
+#define INTCICDIPTR73 INTC.ICDIPTR73
+#define INTCICDIPTR74 INTC.ICDIPTR74
+#define INTCICDIPTR75 INTC.ICDIPTR75
+#define INTCICDIPTR76 INTC.ICDIPTR76
+#define INTCICDIPTR77 INTC.ICDIPTR77
+#define INTCICDIPTR78 INTC.ICDIPTR78
+#define INTCICDIPTR79 INTC.ICDIPTR79
+#define INTCICDIPTR80 INTC.ICDIPTR80
+#define INTCICDIPTR81 INTC.ICDIPTR81
+#define INTCICDIPTR82 INTC.ICDIPTR82
+#define INTCICDIPTR83 INTC.ICDIPTR83
+#define INTCICDIPTR84 INTC.ICDIPTR84
+#define INTCICDIPTR85 INTC.ICDIPTR85
+#define INTCICDIPTR86 INTC.ICDIPTR86
+#define INTCICDIPTR87 INTC.ICDIPTR87
+#define INTCICDIPTR88 INTC.ICDIPTR88
+#define INTCICDIPTR89 INTC.ICDIPTR89
+#define INTCICDIPTR90 INTC.ICDIPTR90
+#define INTCICDIPTR91 INTC.ICDIPTR91
+#define INTCICDIPTR92 INTC.ICDIPTR92
+#define INTCICDIPTR93 INTC.ICDIPTR93
+#define INTCICDIPTR94 INTC.ICDIPTR94
+#define INTCICDIPTR95 INTC.ICDIPTR95
+#define INTCICDIPTR96 INTC.ICDIPTR96
+#define INTCICDIPTR97 INTC.ICDIPTR97
+#define INTCICDIPTR98 INTC.ICDIPTR98
+#define INTCICDIPTR99 INTC.ICDIPTR99
+#define INTCICDIPTR100 INTC.ICDIPTR100
+#define INTCICDIPTR101 INTC.ICDIPTR101
+#define INTCICDIPTR102 INTC.ICDIPTR102
+#define INTCICDIPTR103 INTC.ICDIPTR103
+#define INTCICDIPTR104 INTC.ICDIPTR104
+#define INTCICDIPTR105 INTC.ICDIPTR105
+#define INTCICDIPTR106 INTC.ICDIPTR106
+#define INTCICDIPTR107 INTC.ICDIPTR107
+#define INTCICDIPTR108 INTC.ICDIPTR108
+#define INTCICDIPTR109 INTC.ICDIPTR109
+#define INTCICDIPTR110 INTC.ICDIPTR110
+#define INTCICDIPTR111 INTC.ICDIPTR111
+#define INTCICDIPTR112 INTC.ICDIPTR112
+#define INTCICDIPTR113 INTC.ICDIPTR113
+#define INTCICDIPTR114 INTC.ICDIPTR114
+#define INTCICDIPTR115 INTC.ICDIPTR115
+#define INTCICDIPTR116 INTC.ICDIPTR116
+#define INTCICDIPTR117 INTC.ICDIPTR117
+#define INTCICDIPTR118 INTC.ICDIPTR118
+#define INTCICDIPTR119 INTC.ICDIPTR119
+#define INTCICDIPTR120 INTC.ICDIPTR120
+#define INTCICDIPTR121 INTC.ICDIPTR121
+#define INTCICDIPTR122 INTC.ICDIPTR122
+#define INTCICDIPTR123 INTC.ICDIPTR123
+#define INTCICDIPTR124 INTC.ICDIPTR124
+#define INTCICDIPTR125 INTC.ICDIPTR125
+#define INTCICDIPTR126 INTC.ICDIPTR126
+#define INTCICDIPTR127 INTC.ICDIPTR127
+#define INTCICDIPTR128 INTC.ICDIPTR128
+#define INTCICDIPTR129 INTC.ICDIPTR129
+#define INTCICDIPTR130 INTC.ICDIPTR130
+#define INTCICDIPTR131 INTC.ICDIPTR131
+#define INTCICDIPTR132 INTC.ICDIPTR132
+#define INTCICDIPTR133 INTC.ICDIPTR133
+#define INTCICDIPTR134 INTC.ICDIPTR134
+#define INTCICDIPTR135 INTC.ICDIPTR135
+#define INTCICDIPTR136 INTC.ICDIPTR136
+#define INTCICDIPTR137 INTC.ICDIPTR137
+#define INTCICDIPTR138 INTC.ICDIPTR138
+#define INTCICDIPTR139 INTC.ICDIPTR139
+#define INTCICDIPTR140 INTC.ICDIPTR140
+#define INTCICDIPTR141 INTC.ICDIPTR141
+#define INTCICDIPTR142 INTC.ICDIPTR142
+#define INTCICDIPTR143 INTC.ICDIPTR143
+#define INTCICDIPTR144 INTC.ICDIPTR144
+#define INTCICDIPTR145 INTC.ICDIPTR145
+#define INTCICDIPTR146 INTC.ICDIPTR146
+#define INTCICDICFR0 INTC.ICDICFR0
+#define INTCICDICFR1 INTC.ICDICFR1
+#define INTCICDICFR2 INTC.ICDICFR2
+#define INTCICDICFR3 INTC.ICDICFR3
+#define INTCICDICFR4 INTC.ICDICFR4
+#define INTCICDICFR5 INTC.ICDICFR5
+#define INTCICDICFR6 INTC.ICDICFR6
+#define INTCICDICFR7 INTC.ICDICFR7
+#define INTCICDICFR8 INTC.ICDICFR8
+#define INTCICDICFR9 INTC.ICDICFR9
+#define INTCICDICFR10 INTC.ICDICFR10
+#define INTCICDICFR11 INTC.ICDICFR11
+#define INTCICDICFR12 INTC.ICDICFR12
+#define INTCICDICFR13 INTC.ICDICFR13
+#define INTCICDICFR14 INTC.ICDICFR14
+#define INTCICDICFR15 INTC.ICDICFR15
+#define INTCICDICFR16 INTC.ICDICFR16
+#define INTCICDICFR17 INTC.ICDICFR17
+#define INTCICDICFR18 INTC.ICDICFR18
+#define INTCICDICFR19 INTC.ICDICFR19
+#define INTCICDICFR20 INTC.ICDICFR20
+#define INTCICDICFR21 INTC.ICDICFR21
+#define INTCICDICFR22 INTC.ICDICFR22
+#define INTCICDICFR23 INTC.ICDICFR23
+#define INTCICDICFR24 INTC.ICDICFR24
+#define INTCICDICFR25 INTC.ICDICFR25
+#define INTCICDICFR26 INTC.ICDICFR26
+#define INTCICDICFR27 INTC.ICDICFR27
+#define INTCICDICFR28 INTC.ICDICFR28
+#define INTCICDICFR29 INTC.ICDICFR29
+#define INTCICDICFR30 INTC.ICDICFR30
+#define INTCICDICFR31 INTC.ICDICFR31
+#define INTCICDICFR32 INTC.ICDICFR32
+#define INTCICDICFR33 INTC.ICDICFR33
+#define INTCICDICFR34 INTC.ICDICFR34
+#define INTCICDICFR35 INTC.ICDICFR35
+#define INTCICDICFR36 INTC.ICDICFR36
+#define INTCPPI_STATUS INTC.PPI_STATUS
+#define INTCSPI_STATUS0 INTC.SPI_STATUS0
+#define INTCSPI_STATUS1 INTC.SPI_STATUS1
+#define INTCSPI_STATUS2 INTC.SPI_STATUS2
+#define INTCSPI_STATUS3 INTC.SPI_STATUS3
+#define INTCSPI_STATUS4 INTC.SPI_STATUS4
+#define INTCSPI_STATUS5 INTC.SPI_STATUS5
+#define INTCSPI_STATUS6 INTC.SPI_STATUS6
+#define INTCSPI_STATUS7 INTC.SPI_STATUS7
+#define INTCSPI_STATUS8 INTC.SPI_STATUS8
+#define INTCSPI_STATUS9 INTC.SPI_STATUS9
+#define INTCSPI_STATUS10 INTC.SPI_STATUS10
+#define INTCSPI_STATUS11 INTC.SPI_STATUS11
+#define INTCSPI_STATUS12 INTC.SPI_STATUS12
+#define INTCSPI_STATUS13 INTC.SPI_STATUS13
+#define INTCSPI_STATUS14 INTC.SPI_STATUS14
+#define INTCSPI_STATUS15 INTC.SPI_STATUS15
+#define INTCSPI_STATUS16 INTC.SPI_STATUS16
+#define INTCICDSGIR INTC.ICDSGIR
+#define INTCICCICR INTC.ICCICR
+#define INTCICCPMR INTC.ICCPMR
+#define INTCICCBPR INTC.ICCBPR
+#define INTCICCIAR INTC.ICCIAR
+#define INTCICCEOIR INTC.ICCEOIR
+#define INTCICCRPR INTC.ICCRPR
+#define INTCICCHPIR INTC.ICCHPIR
+#define INTCICCABPR INTC.ICCABPR
+#define INTCICCIIDR INTC.ICCIIDR
+#define INTCICR0 INTC.ICR0
+#define INTCICR1 INTC.ICR1
+#define INTCIRQRR INTC.IRQRR
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/irda_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,43 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : irda_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef IRDA_IODEFINE_H
+#define IRDA_IODEFINE_H
+
+struct st_irda
+{                                                          /* IRDA             */
+    volatile uint8_t   IRCR;                                   /*  IRCR            */
+};
+
+
+#define IRDA    (*(struct st_irda    *)0xE8014000uL) /* IRDA */
+
+
+#define IRDAIRCR IRDA.IRCR
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/jcu_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,170 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : jcu_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef JCU_IODEFINE_H
+#define JCU_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_jcu
+{                                                          /* JCU              */
+    volatile uint8_t   JCMOD;                                  /*  JCMOD           */
+    volatile uint8_t   JCCMD;                                  /*  JCCMD           */
+    volatile uint8_t   dummy145[1];                            /*                  */
+    volatile uint8_t   JCQTN;                                  /*  JCQTN           */
+    volatile uint8_t   JCHTN;                                  /*  JCHTN           */
+    volatile uint8_t   JCDRIU;                                 /*  JCDRIU          */
+    volatile uint8_t   JCDRID;                                 /*  JCDRID          */
+    volatile uint8_t   JCVSZU;                                 /*  JCVSZU          */
+    volatile uint8_t   JCVSZD;                                 /*  JCVSZD          */
+    volatile uint8_t   JCHSZU;                                 /*  JCHSZU          */
+    volatile uint8_t   JCHSZD;                                 /*  JCHSZD          */
+    volatile uint8_t   JCDTCU;                                 /*  JCDTCU          */
+    volatile uint8_t   JCDTCM;                                 /*  JCDTCM          */
+    volatile uint8_t   JCDTCD;                                 /*  JCDTCD          */
+    volatile uint8_t   JINTE0;                                 /*  JINTE0          */
+    volatile uint8_t   JINTS0;                                 /*  JINTS0          */
+    volatile uint8_t   JCDERR;                                 /*  JCDERR          */
+    volatile uint8_t   JCRST;                                  /*  JCRST           */
+    volatile uint8_t   dummy146[46];                           /*                  */
+    volatile uint32_t  JIFECNT;                                /*  JIFECNT         */
+    volatile uint32_t  JIFESA;                                 /*  JIFESA          */
+    volatile uint32_t  JIFESOFST;                              /*  JIFESOFST       */
+    volatile uint32_t  JIFEDA;                                 /*  JIFEDA          */
+    volatile uint32_t  JIFESLC;                                /*  JIFESLC         */
+    volatile uint32_t  JIFEDDC;                                /*  JIFEDDC         */
+    volatile uint32_t  JIFDCNT;                                /*  JIFDCNT         */
+    volatile uint32_t  JIFDSA;                                 /*  JIFDSA          */
+    volatile uint32_t  JIFDDOFST;                              /*  JIFDDOFST       */
+    volatile uint32_t  JIFDDA;                                 /*  JIFDDA          */
+    volatile uint32_t  JIFDSDC;                                /*  JIFDSDC         */
+    volatile uint32_t  JIFDDLC;                                /*  JIFDDLC         */
+    volatile uint32_t  JIFDADT;                                /*  JIFDADT         */
+    volatile uint8_t   dummy147[24];                           /*                  */
+    volatile uint32_t  JINTE1;                                 /*  JINTE1          */
+    volatile uint32_t  JINTS1;                                 /*  JINTS1          */
+    volatile uint32_t  JIFESVSZ;                               /*  JIFESVSZ        */
+    volatile uint32_t  JIFESHSZ;                               /*  JIFESHSZ        */
+    volatile uint8_t   dummy148[100];                          /*                  */
+/* start of struct st_jcu_from_jcqtbl0 */
+    volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
+    volatile uint8_t   dummy149[63];                           /*                  */
+/* end of struct st_jcu_from_jcqtbl0 */
+/* start of struct st_jcu_from_jcqtbl0 */
+    volatile uint8_t   JCQTBL1;                                /*  JCQTBL1         */
+    volatile uint8_t   dummy150[63];                           /*                  */
+/* end of struct st_jcu_from_jcqtbl0 */
+/* start of struct st_jcu_from_jcqtbl0 */
+    volatile uint8_t   JCQTBL2;                                /*  JCQTBL2         */
+    volatile uint8_t   dummy151[63];                           /*                  */
+/* end of struct st_jcu_from_jcqtbl0 */
+/* start of struct st_jcu_from_jcqtbl0 */
+    volatile uint8_t   JCQTBL3;                                /*  JCQTBL3         */
+    volatile uint8_t   dummy152[63];                           /*                  */
+/* end of struct st_jcu_from_jcqtbl0 */
+    volatile uint8_t   JCHTBD0;                                /*  JCHTBD0         */
+    volatile uint8_t   dummy153[31];                           /*                  */
+    volatile uint8_t   JCHTBA0;                                /*  JCHTBA0         */
+    volatile uint8_t   dummy154[223];                          /*                  */
+    volatile uint8_t   JCHTBD1;                                /*  JCHTBD1         */
+    volatile uint8_t   dummy155[31];                           /*                  */
+    volatile uint8_t   JCHTBA1;                                /*  JCHTBA1         */
+};
+
+
+struct st_jcu_from_jcqtbl0
+{
+    volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
+    volatile uint8_t   dummy1[63];                             /*                  */
+};
+
+
+#define JCU     (*(struct st_jcu     *)0xE8017000uL) /* JCU */
+
+
+/* Start of channnel array defines of JCU */
+
+/* Channnel array defines of JCU_JCQTBL0 */
+/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
+#define JCU_JCQTBL0_COUNT  4
+#define JCU_JCQTBL0_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
+#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
+#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
+#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
+
+/* End of channnel array defines of JCU */
+
+
+#define JCUJCMOD JCU.JCMOD
+#define JCUJCCMD JCU.JCCMD
+#define JCUJCQTN JCU.JCQTN
+#define JCUJCHTN JCU.JCHTN
+#define JCUJCDRIU JCU.JCDRIU
+#define JCUJCDRID JCU.JCDRID
+#define JCUJCVSZU JCU.JCVSZU
+#define JCUJCVSZD JCU.JCVSZD
+#define JCUJCHSZU JCU.JCHSZU
+#define JCUJCHSZD JCU.JCHSZD
+#define JCUJCDTCU JCU.JCDTCU
+#define JCUJCDTCM JCU.JCDTCM
+#define JCUJCDTCD JCU.JCDTCD
+#define JCUJINTE0 JCU.JINTE0
+#define JCUJINTS0 JCU.JINTS0
+#define JCUJCDERR JCU.JCDERR
+#define JCUJCRST JCU.JCRST
+#define JCUJIFECNT JCU.JIFECNT
+#define JCUJIFESA JCU.JIFESA
+#define JCUJIFESOFST JCU.JIFESOFST
+#define JCUJIFEDA JCU.JIFEDA
+#define JCUJIFESLC JCU.JIFESLC
+#define JCUJIFEDDC JCU.JIFEDDC
+#define JCUJIFDCNT JCU.JIFDCNT
+#define JCUJIFDSA JCU.JIFDSA
+#define JCUJIFDDOFST JCU.JIFDDOFST
+#define JCUJIFDDA JCU.JIFDDA
+#define JCUJIFDSDC JCU.JIFDSDC
+#define JCUJIFDDLC JCU.JIFDDLC
+#define JCUJIFDADT JCU.JIFDADT
+#define JCUJINTE1 JCU.JINTE1
+#define JCUJINTS1 JCU.JINTS1
+#define JCUJIFESVSZ JCU.JIFESVSZ
+#define JCUJIFESHSZ JCU.JIFESHSZ
+#define JCUJCQTBL0 JCU.JCQTBL0
+#define JCUJCQTBL1 JCU.JCQTBL1
+#define JCUJCQTBL2 JCU.JCQTBL2
+#define JCUJCQTBL3 JCU.JCQTBL3
+#define JCUJCHTBD0 JCU.JCHTBD0
+#define JCUJCHTBA0 JCU.JCHTBA0
+#define JCUJCHTBD1 JCU.JCHTBD1
+#define JCUJCHTBA1 JCU.JCHTBA1
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/l2c_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,196 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : l2c_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef L2C_IODEFINE_H
+#define L2C_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_l2c
+{                                                          /* L2C              */
+    volatile uint32_t  REG0_CACHE_ID;                          /*  REG0_CACHE_ID   */
+    volatile uint32_t  REG0_CACHE_TYPE;                        /*  REG0_CACHE_TYPE */
+    volatile uint8_t   dummy8[248];                            /*                  */
+    volatile uint32_t  REG1_CONTROL;                           /*  REG1_CONTROL    */
+    volatile uint32_t  REG1_AUX_CONTROL;                       /*  REG1_AUX_CONTROL */
+    volatile uint32_t  REG1_TAG_RAM_CONTROL;                   /*  REG1_TAG_RAM_CONTROL */
+    volatile uint32_t  REG1_DATA_RAM_CONTROL;                  /*  REG1_DATA_RAM_CONTROL */
+    volatile uint8_t   dummy9[240];                            /*                  */
+    volatile uint32_t  REG2_EV_COUNTER_CTRL;                   /*  REG2_EV_COUNTER_CTRL */
+    volatile uint32_t  REG2_EV_COUNTER1_CFG;                   /*  REG2_EV_COUNTER1_CFG */
+    volatile uint32_t  REG2_EV_COUNTER0_CFG;                   /*  REG2_EV_COUNTER0_CFG */
+    volatile uint32_t  REG2_EV_COUNTER1;                       /*  REG2_EV_COUNTER1 */
+    volatile uint32_t  REG2_EV_COUNTER0;                       /*  REG2_EV_COUNTER0 */
+    volatile uint32_t  REG2_INT_MASK;                          /*  REG2_INT_MASK   */
+    volatile uint32_t  REG2_INT_MASK_STATUS;                   /*  REG2_INT_MASK_STATUS */
+    volatile uint32_t  REG2_INT_RAW_STATUS;                    /*  REG2_INT_RAW_STATUS */
+    volatile uint32_t  REG2_INT_CLEAR;                         /*  REG2_INT_CLEAR  */
+    volatile uint8_t   dummy10[1292];                          /*                  */
+    volatile uint32_t  REG7_CACHE_SYNC;                        /*  REG7_CACHE_SYNC */
+    volatile uint8_t   dummy11[60];                            /*                  */
+    volatile uint32_t  REG7_INV_PA;                            /*  REG7_INV_PA     */
+    volatile uint8_t   dummy12[8];                             /*                  */
+    volatile uint32_t  REG7_INV_WAY;                           /*  REG7_INV_WAY    */
+    volatile uint8_t   dummy13[48];                            /*                  */
+    volatile uint32_t  REG7_CLEAN_PA;                          /*  REG7_CLEAN_PA   */
+    volatile uint8_t   dummy14[4];                             /*                  */
+    volatile uint32_t  REG7_CLEAN_INDEX;                       /*  REG7_CLEAN_INDEX */
+    volatile uint32_t  REG7_CLEAN_WAY;                         /*  REG7_CLEAN_WAY  */
+    volatile uint8_t   dummy15[48];                            /*                  */
+    volatile uint32_t  REG7_CLEAN_INV_PA;                      /*  REG7_CLEAN_INV_PA */
+    volatile uint8_t   dummy16[4];                             /*                  */
+    volatile uint32_t  REG7_CLEAN_INV_INDEX;                   /*  REG7_CLEAN_INV_INDEX */
+    volatile uint32_t  REG7_CLEAN_INV_WAY;                     /*  REG7_CLEAN_INV_WAY */
+    volatile uint8_t   dummy17[256];                           /*                  */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
+    volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN1;                       /*  REG9_D_LOCKDOWN1 */
+    volatile uint32_t  REG9_I_LOCKDOWN1;                       /*  REG9_I_LOCKDOWN1 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN2;                       /*  REG9_D_LOCKDOWN2 */
+    volatile uint32_t  REG9_I_LOCKDOWN2;                       /*  REG9_I_LOCKDOWN2 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN3;                       /*  REG9_D_LOCKDOWN3 */
+    volatile uint32_t  REG9_I_LOCKDOWN3;                       /*  REG9_I_LOCKDOWN3 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN4;                       /*  REG9_D_LOCKDOWN4 */
+    volatile uint32_t  REG9_I_LOCKDOWN4;                       /*  REG9_I_LOCKDOWN4 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN5;                       /*  REG9_D_LOCKDOWN5 */
+    volatile uint32_t  REG9_I_LOCKDOWN5;                       /*  REG9_I_LOCKDOWN5 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN6;                       /*  REG9_D_LOCKDOWN6 */
+    volatile uint32_t  REG9_I_LOCKDOWN6;                       /*  REG9_I_LOCKDOWN6 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+/* start of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint32_t  REG9_D_LOCKDOWN7;                       /*  REG9_D_LOCKDOWN7 */
+    volatile uint32_t  REG9_I_LOCKDOWN7;                       /*  REG9_I_LOCKDOWN7 */
+/* end of struct st_l2c_from_reg9_d_lockdown0 */
+    volatile uint8_t   dummy18[16];                            /*                  */
+    volatile uint32_t  REG9_LOCK_LINE_EN;                      /*  REG9_LOCK_LINE_EN */
+    volatile uint32_t  REG9_UNLOCK_WAY;                        /*  REG9_UNLOCK_WAY */
+    volatile uint8_t   dummy19[680];                           /*                  */
+    volatile uint32_t  REG12_ADDR_FILTERING_START;             /*  REG12_ADDR_FILTERING_START */
+    volatile uint32_t  REG12_ADDR_FILTERING_END;               /*  REG12_ADDR_FILTERING_END */
+    volatile uint8_t   dummy20[824];                           /*                  */
+    volatile uint32_t  REG15_DEBUG_CTRL;                       /*  REG15_DEBUG_CTRL */
+    volatile uint8_t   dummy21[28];                            /*                  */
+    volatile uint32_t  REG15_PREFETCH_CTRL;                    /*  REG15_PREFETCH_CTRL */
+    volatile uint8_t   dummy22[28];                            /*                  */
+    volatile uint32_t  REG15_POWER_CTRL;                       /*  REG15_POWER_CTRL */
+};
+
+
+struct st_l2c_from_reg9_d_lockdown0
+{
+    volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
+    volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
+};
+
+
+#define L2C     (*(struct st_l2c     *)0x3FFFF000uL) /* L2C */
+
+
+/* Start of channnel array defines of L2C */
+
+/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
+/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT  8
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
+#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
+#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
+#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
+#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
+#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
+#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
+#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
+
+/* End of channnel array defines of L2C */
+
+
+#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID
+#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE
+#define L2CREG1_CONTROL L2C.REG1_CONTROL
+#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL
+#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL
+#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL
+#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL
+#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG
+#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG
+#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1
+#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0
+#define L2CREG2_INT_MASK L2C.REG2_INT_MASK
+#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS
+#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS
+#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR
+#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC
+#define L2CREG7_INV_PA L2C.REG7_INV_PA
+#define L2CREG7_INV_WAY L2C.REG7_INV_WAY
+#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA
+#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX
+#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY
+#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA
+#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX
+#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY
+#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0
+#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0
+#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1
+#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1
+#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2
+#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2
+#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3
+#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3
+#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4
+#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4
+#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5
+#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5
+#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6
+#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6
+#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7
+#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7
+#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN
+#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY
+#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START
+#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END
+#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL
+#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL
+#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/lin_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,175 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : lin_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef LIN_IODEFINE_H
+#define LIN_IODEFINE_H
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_lin
+{                                                          /* LIN              */
+    volatile uint8_t   dummy1[1];                              /*                  */
+    volatile uint8_t   RLN3nLWBR;                              /*  RLN3nLWBR       */
+    union iodefine_reg16_8_t  RLN3nLBRP01;                     /*  RLN3nLBRP01 */
+    
+    volatile uint8_t   RLN3nLSTC;                              /*  RLN3nLSTC       */
+    volatile uint8_t   dummy2[3];                              /*                  */
+    volatile uint8_t   RLN3nLMD;                               /*  RLN3nLMD        */
+    volatile uint8_t   RLN3nLBFC;                              /*  RLN3nLBFC       */
+    volatile uint8_t   RLN3nLSC;                               /*  RLN3nLSC        */
+    volatile uint8_t   RLN3nLWUP;                              /*  RLN3nLWUP       */
+    volatile uint8_t   RLN3nLIE;                               /*  RLN3nLIE        */
+    volatile uint8_t   RLN3nLEDE;                              /*  RLN3nLEDE       */
+    volatile uint8_t   RLN3nLCUC;                              /*  RLN3nLCUC       */
+    volatile uint8_t   dummy3[1];                              /*                  */
+    volatile uint8_t   RLN3nLTRC;                              /*  RLN3nLTRC       */
+    volatile uint8_t   RLN3nLMST;                              /*  RLN3nLMST       */
+    volatile uint8_t   RLN3nLST;                               /*  RLN3nLST        */
+    volatile uint8_t   RLN3nLEST;                              /*  RLN3nLEST       */
+    volatile uint8_t   RLN3nLDFC;                              /*  RLN3nLDFC       */
+    volatile uint8_t   RLN3nLIDB;                              /*  RLN3nLIDB       */
+    volatile uint8_t   RLN3nLCBR;                              /*  RLN3nLCBR       */
+    volatile uint8_t   RLN3nLUDB0;                             /*  RLN3nLUDB0      */
+#define LIN_LDBn_COUNT 8
+    volatile uint8_t   RLN3nLDBR1;                             /*  RLN3nLDBR1      */
+    volatile uint8_t   RLN3nLDBR2;                             /*  RLN3nLDBR2      */
+    volatile uint8_t   RLN3nLDBR3;                             /*  RLN3nLDBR3      */
+    volatile uint8_t   RLN3nLDBR4;                             /*  RLN3nLDBR4      */
+    volatile uint8_t   RLN3nLDBR5;                             /*  RLN3nLDBR5      */
+    volatile uint8_t   RLN3nLDBR6;                             /*  RLN3nLDBR6      */
+    volatile uint8_t   RLN3nLDBR7;                             /*  RLN3nLDBR7      */
+    volatile uint8_t   RLN3nLDBR8;                             /*  RLN3nLDBR8      */
+    volatile uint8_t   RLN3nLUOER;                             /*  RLN3nLUOER      */
+    volatile uint8_t   RLN3nLUOR1;                             /*  RLN3nLUOR1      */
+    volatile uint8_t   dummy4[2];                              /*                  */
+    union iodefine_reg16_8_t  RLN3nLUTDR;                      /*  RLN3nLUTDR  */
+    union iodefine_reg16_8_t  RLN3nLURDR;                      /*  RLN3nLURDR  */
+    union iodefine_reg16_8_t  RLN3nLUWTDR;                     /*  RLN3nLUWTDR */
+    
+};
+
+
+#define LIN0    (*(struct st_lin     *)0xFCFE9000uL) /* LIN0 */
+#define LIN1    (*(struct st_lin     *)0xFCFE9800uL) /* LIN1 */
+
+
+/* Start of channnel array defines of LIN */
+
+/* Channnel array defines of LIN */
+/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
+#define LIN_COUNT  2
+#define LIN_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &LIN0, &LIN1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of LIN */
+
+
+#define LIN0RLN30LWBR LIN0.RLN3nLWBR
+#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16
+#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L]
+#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H]
+#define LIN0RLN30LSTC LIN0.RLN3nLSTC
+#define LIN0RLN30LMD LIN0.RLN3nLMD
+#define LIN0RLN30LBFC LIN0.RLN3nLBFC
+#define LIN0RLN30LSC LIN0.RLN3nLSC
+#define LIN0RLN30LWUP LIN0.RLN3nLWUP
+#define LIN0RLN30LIE LIN0.RLN3nLIE
+#define LIN0RLN30LEDE LIN0.RLN3nLEDE
+#define LIN0RLN30LCUC LIN0.RLN3nLCUC
+#define LIN0RLN30LTRC LIN0.RLN3nLTRC
+#define LIN0RLN30LMST LIN0.RLN3nLMST
+#define LIN0RLN30LST LIN0.RLN3nLST
+#define LIN0RLN30LEST LIN0.RLN3nLEST
+#define LIN0RLN30LDFC LIN0.RLN3nLDFC
+#define LIN0RLN30LIDB LIN0.RLN3nLIDB
+#define LIN0RLN30LCBR LIN0.RLN3nLCBR
+#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0
+#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1
+#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2
+#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3
+#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4
+#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5
+#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6
+#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7
+#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8
+#define LIN0RLN30LUOER LIN0.RLN3nLUOER
+#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1
+#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16
+#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L]
+#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H]
+#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16
+#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L]
+#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H]
+#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16
+#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L]
+#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H]
+#define LIN1RLN31LWBR LIN1.RLN3nLWBR
+#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16
+#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L]
+#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H]
+#define LIN1RLN31LSTC LIN1.RLN3nLSTC
+#define LIN1RLN31LMD LIN1.RLN3nLMD
+#define LIN1RLN31LBFC LIN1.RLN3nLBFC
+#define LIN1RLN31LSC LIN1.RLN3nLSC
+#define LIN1RLN31LWUP LIN1.RLN3nLWUP
+#define LIN1RLN31LIE LIN1.RLN3nLIE
+#define LIN1RLN31LEDE LIN1.RLN3nLEDE
+#define LIN1RLN31LCUC LIN1.RLN3nLCUC
+#define LIN1RLN31LTRC LIN1.RLN3nLTRC
+#define LIN1RLN31LMST LIN1.RLN3nLMST
+#define LIN1RLN31LST LIN1.RLN3nLST
+#define LIN1RLN31LEST LIN1.RLN3nLEST
+#define LIN1RLN31LDFC LIN1.RLN3nLDFC
+#define LIN1RLN31LIDB LIN1.RLN3nLIDB
+#define LIN1RLN31LCBR LIN1.RLN3nLCBR
+#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0
+#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1
+#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2
+#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3
+#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4
+#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5
+#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6
+#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7
+#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8
+#define LIN1RLN31LUOER LIN1.RLN3nLUOER
+#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1
+#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16
+#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L]
+#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H]
+#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16
+#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L]
+#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H]
+#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16
+#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L]
+#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H]
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/lvds_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,55 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : lvds_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.01a)
+******************************************************************************/
+#ifndef LVDS_IODEFINE_H
+#define LVDS_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_lvds
+{                                                          /* LVDS             */
+    volatile uint32_t  LVDS_UPDATE;                            /*  LVDS_UPDATE     */
+    volatile uint32_t  LVDSFCL;                                /*  LVDSFCL         */
+    volatile uint8_t   dummy608[24];                           /*                  */
+    volatile uint32_t  LCLKSELR;                               /*  LCLKSELR        */
+    volatile uint32_t  LPLLSETR;                               /*  LPLLSETR        */
+    volatile uint8_t   dummy609[4];                            /*                  */
+    volatile uint32_t  LPHYACC;                                /*  LPHYACC         */
+};
+
+
+#define LVDS    (*(struct st_lvds    *)0xFCFF7A30uL) /* LVDS */
+
+
+#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE
+#define LVDSLVDSFCL LVDS.LVDSFCL
+#define LVDSLCLKSELR LVDS.LCLKSELR
+#define LVDSLPLLSETR LVDS.LPLLSETR
+#define LVDSLPHYACC LVDS.LPHYACC
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/mlb_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,499 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mlb_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef MLB_IODEFINE_H
+#define MLB_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_mlb
+{                                                          /* MLB              */
+    volatile uint32_t  DCCR;                                   /*  DCCR            */
+    volatile uint32_t  SSCR;                                   /*  SSCR            */
+    volatile uint32_t  SDCR;                                   /*  SDCR            */
+    volatile uint32_t  SMCR;                                   /*  SMCR            */
+    volatile uint8_t   dummy156[12];                           /*                  */
+    volatile uint32_t  VCCR;                                   /*  VCCR            */
+    volatile uint32_t  SBCR;                                   /*  SBCR            */
+    volatile uint32_t  ABCR;                                   /*  ABCR            */
+    volatile uint32_t  CBCR;                                   /*  CBCR            */
+    volatile uint32_t  IBCR;                                   /*  IBCR            */
+    volatile uint32_t  CICR;                                   /*  CICR            */
+    volatile uint8_t   dummy157[12];                           /*                  */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR0;                                  /*  CECR0           */
+    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
+    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
+    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR1;                                  /*  CECR1           */
+    volatile uint32_t  CSCR1;                                  /*  CSCR1           */
+    volatile uint32_t  CCBCR1;                                 /*  CCBCR1          */
+    volatile uint32_t  CNBCR1;                                 /*  CNBCR1          */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR2;                                  /*  CECR2           */
+    volatile uint32_t  CSCR2;                                  /*  CSCR2           */
+    volatile uint32_t  CCBCR2;                                 /*  CCBCR2          */
+    volatile uint32_t  CNBCR2;                                 /*  CNBCR2          */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR3;                                  /*  CECR3           */
+    volatile uint32_t  CSCR3;                                  /*  CSCR3           */
+    volatile uint32_t  CCBCR3;                                 /*  CCBCR3          */
+    volatile uint32_t  CNBCR3;                                 /*  CNBCR3          */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR4;                                  /*  CECR4           */
+    volatile uint32_t  CSCR4;                                  /*  CSCR4           */
+    volatile uint32_t  CCBCR4;                                 /*  CCBCR4          */
+    volatile uint32_t  CNBCR4;                                 /*  CNBCR4          */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR5;                                  /*  CECR5           */
+    volatile uint32_t  CSCR5;                                  /*  CSCR5           */
+    volatile uint32_t  CCBCR5;                                 /*  CCBCR5          */
+    volatile uint32_t  CNBCR5;                                 /*  CNBCR5          */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR6;                                  /*  CECR6           */
+    volatile uint32_t  CSCR6;                                  /*  CSCR6           */
+    volatile uint32_t  CCBCR6;                                 /*  CCBCR6          */
+    volatile uint32_t  CNBCR6;                                 /*  CNBCR6          */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR7;                                  /*  CECR7           */
+    volatile uint32_t  CSCR7;                                  /*  CSCR7           */
+    volatile uint32_t  CCBCR7;                                 /*  CCBCR7          */
+    volatile uint32_t  CNBCR7;                                 /*  CNBCR7          */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR8;                                  /*  CECR8           */
+    volatile uint32_t  CSCR8;                                  /*  CSCR8           */
+    volatile uint32_t  CCBCR8;                                 /*  CCBCR8          */
+    volatile uint32_t  CNBCR8;                                 /*  CNBCR8          */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR9;                                  /*  CECR9           */
+    volatile uint32_t  CSCR9;                                  /*  CSCR9           */
+    volatile uint32_t  CCBCR9;                                 /*  CCBCR9          */
+    volatile uint32_t  CNBCR9;                                 /*  CNBCR9          */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR10;                                 /*  CECR10          */
+    volatile uint32_t  CSCR10;                                 /*  CSCR10          */
+    volatile uint32_t  CCBCR10;                                /*  CCBCR10         */
+    volatile uint32_t  CNBCR10;                                /*  CNBCR10         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR11;                                 /*  CECR11          */
+    volatile uint32_t  CSCR11;                                 /*  CSCR11          */
+    volatile uint32_t  CCBCR11;                                /*  CCBCR11         */
+    volatile uint32_t  CNBCR11;                                /*  CNBCR11         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR12;                                 /*  CECR12          */
+    volatile uint32_t  CSCR12;                                 /*  CSCR12          */
+    volatile uint32_t  CCBCR12;                                /*  CCBCR12         */
+    volatile uint32_t  CNBCR12;                                /*  CNBCR12         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR13;                                 /*  CECR13          */
+    volatile uint32_t  CSCR13;                                 /*  CSCR13          */
+    volatile uint32_t  CCBCR13;                                /*  CCBCR13         */
+    volatile uint32_t  CNBCR13;                                /*  CNBCR13         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR14;                                 /*  CECR14          */
+    volatile uint32_t  CSCR14;                                 /*  CSCR14          */
+    volatile uint32_t  CCBCR14;                                /*  CCBCR14         */
+    volatile uint32_t  CNBCR14;                                /*  CNBCR14         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR15;                                 /*  CECR15          */
+    volatile uint32_t  CSCR15;                                 /*  CSCR15          */
+    volatile uint32_t  CCBCR15;                                /*  CCBCR15         */
+    volatile uint32_t  CNBCR15;                                /*  CNBCR15         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR16;                                 /*  CECR16          */
+    volatile uint32_t  CSCR16;                                 /*  CSCR16          */
+    volatile uint32_t  CCBCR16;                                /*  CCBCR16         */
+    volatile uint32_t  CNBCR16;                                /*  CNBCR16         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR17;                                 /*  CECR17          */
+    volatile uint32_t  CSCR17;                                 /*  CSCR17          */
+    volatile uint32_t  CCBCR17;                                /*  CCBCR17         */
+    volatile uint32_t  CNBCR17;                                /*  CNBCR17         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR18;                                 /*  CECR18          */
+    volatile uint32_t  CSCR18;                                 /*  CSCR18          */
+    volatile uint32_t  CCBCR18;                                /*  CCBCR18         */
+    volatile uint32_t  CNBCR18;                                /*  CNBCR18         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR19;                                 /*  CECR19          */
+    volatile uint32_t  CSCR19;                                 /*  CSCR19          */
+    volatile uint32_t  CCBCR19;                                /*  CCBCR19         */
+    volatile uint32_t  CNBCR19;                                /*  CNBCR19         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR20;                                 /*  CECR20          */
+    volatile uint32_t  CSCR20;                                 /*  CSCR20          */
+    volatile uint32_t  CCBCR20;                                /*  CCBCR20         */
+    volatile uint32_t  CNBCR20;                                /*  CNBCR20         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR21;                                 /*  CECR21          */
+    volatile uint32_t  CSCR21;                                 /*  CSCR21          */
+    volatile uint32_t  CCBCR21;                                /*  CCBCR21         */
+    volatile uint32_t  CNBCR21;                                /*  CNBCR21         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR22;                                 /*  CECR22          */
+    volatile uint32_t  CSCR22;                                 /*  CSCR22          */
+    volatile uint32_t  CCBCR22;                                /*  CCBCR22         */
+    volatile uint32_t  CNBCR22;                                /*  CNBCR22         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR23;                                 /*  CECR23          */
+    volatile uint32_t  CSCR23;                                 /*  CSCR23          */
+    volatile uint32_t  CCBCR23;                                /*  CCBCR23         */
+    volatile uint32_t  CNBCR23;                                /*  CNBCR23         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR24;                                 /*  CECR24          */
+    volatile uint32_t  CSCR24;                                 /*  CSCR24          */
+    volatile uint32_t  CCBCR24;                                /*  CCBCR24         */
+    volatile uint32_t  CNBCR24;                                /*  CNBCR24         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR25;                                 /*  CECR25          */
+    volatile uint32_t  CSCR25;                                 /*  CSCR25          */
+    volatile uint32_t  CCBCR25;                                /*  CCBCR25         */
+    volatile uint32_t  CNBCR25;                                /*  CNBCR25         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR26;                                 /*  CECR26          */
+    volatile uint32_t  CSCR26;                                 /*  CSCR26          */
+    volatile uint32_t  CCBCR26;                                /*  CCBCR26         */
+    volatile uint32_t  CNBCR26;                                /*  CNBCR26         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR27;                                 /*  CECR27          */
+    volatile uint32_t  CSCR27;                                 /*  CSCR27          */
+    volatile uint32_t  CCBCR27;                                /*  CCBCR27         */
+    volatile uint32_t  CNBCR27;                                /*  CNBCR27         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR28;                                 /*  CECR28          */
+    volatile uint32_t  CSCR28;                                 /*  CSCR28          */
+    volatile uint32_t  CCBCR28;                                /*  CCBCR28         */
+    volatile uint32_t  CNBCR28;                                /*  CNBCR28         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR29;                                 /*  CECR29          */
+    volatile uint32_t  CSCR29;                                 /*  CSCR29          */
+    volatile uint32_t  CCBCR29;                                /*  CCBCR29         */
+    volatile uint32_t  CNBCR29;                                /*  CNBCR29         */
+/* end of struct st_mlb_from_cecr0 */
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR30;                                 /*  CECR30          */
+    volatile uint32_t  CSCR30;                                 /*  CSCR30          */
+    volatile uint32_t  CCBCR30;                                /*  CCBCR30         */
+    volatile uint32_t  CNBCR30;                                /*  CNBCR30         */
+/* end of struct st_mlb_from_cecr0 */
+    volatile uint8_t   dummy158[80];                           /*                  */
+#define MLB_LCBCR0_COUNT 31
+    volatile uint32_t  LCBCR0;                                 /*  LCBCR0          */
+    volatile uint32_t  LCBCR1;                                 /*  LCBCR1          */
+    volatile uint32_t  LCBCR2;                                 /*  LCBCR2          */
+    volatile uint32_t  LCBCR3;                                 /*  LCBCR3          */
+    volatile uint32_t  LCBCR4;                                 /*  LCBCR4          */
+    volatile uint32_t  LCBCR5;                                 /*  LCBCR5          */
+    volatile uint32_t  LCBCR6;                                 /*  LCBCR6          */
+    volatile uint32_t  LCBCR7;                                 /*  LCBCR7          */
+    volatile uint32_t  LCBCR8;                                 /*  LCBCR8          */
+    volatile uint32_t  LCBCR9;                                 /*  LCBCR9          */
+    volatile uint32_t  LCBCR10;                                /*  LCBCR10         */
+    volatile uint32_t  LCBCR11;                                /*  LCBCR11         */
+    volatile uint32_t  LCBCR12;                                /*  LCBCR12         */
+    volatile uint32_t  LCBCR13;                                /*  LCBCR13         */
+    volatile uint32_t  LCBCR14;                                /*  LCBCR14         */
+    volatile uint32_t  LCBCR15;                                /*  LCBCR15         */
+    volatile uint32_t  LCBCR16;                                /*  LCBCR16         */
+    volatile uint32_t  LCBCR17;                                /*  LCBCR17         */
+    volatile uint32_t  LCBCR18;                                /*  LCBCR18         */
+    volatile uint32_t  LCBCR19;                                /*  LCBCR19         */
+    volatile uint32_t  LCBCR20;                                /*  LCBCR20         */
+    volatile uint32_t  LCBCR21;                                /*  LCBCR21         */
+    volatile uint32_t  LCBCR22;                                /*  LCBCR22         */
+    volatile uint32_t  LCBCR23;                                /*  LCBCR23         */
+    volatile uint32_t  LCBCR24;                                /*  LCBCR24         */
+    volatile uint32_t  LCBCR25;                                /*  LCBCR25         */
+    volatile uint32_t  LCBCR26;                                /*  LCBCR26         */
+    volatile uint32_t  LCBCR27;                                /*  LCBCR27         */
+    volatile uint32_t  LCBCR28;                                /*  LCBCR28         */
+    volatile uint32_t  LCBCR29;                                /*  LCBCR29         */
+    volatile uint32_t  LCBCR30;                                /*  LCBCR30         */
+};
+
+
+struct st_mlb_from_cecr0
+{
+    volatile uint32_t  CECR0;                                  /*  CECR0           */
+    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
+    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
+    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
+};
+
+
+#define MLB     (*(struct st_mlb     *)0xE8034000uL) /* MLB */
+
+
+/* Start of channnel array defines of MLB */
+
+/* Channnel array defines of MLB_FROM_CECR0_ARRAY */
+/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */
+#define MLB_FROM_CECR0_ARRAY_COUNT  31
+#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \
+    &MLB_FROM_CECR8, &MLB_FROM_CECR9, &MLB_FROM_CECR10, &MLB_FROM_CECR11, &MLB_FROM_CECR12, &MLB_FROM_CECR13, &MLB_FROM_CECR14, &MLB_FROM_CECR15, \
+    &MLB_FROM_CECR16, &MLB_FROM_CECR17, &MLB_FROM_CECR18, &MLB_FROM_CECR19, &MLB_FROM_CECR20, &MLB_FROM_CECR21, &MLB_FROM_CECR22, &MLB_FROM_CECR23, \
+    &MLB_FROM_CECR24, &MLB_FROM_CECR25, &MLB_FROM_CECR26, &MLB_FROM_CECR27, &MLB_FROM_CECR28, &MLB_FROM_CECR29, &MLB_FROM_CECR30 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define MLB_FROM_CECR0 (*(struct st_mlb_from_cecr0 *)&MLB.CECR0) /* MLB_FROM_CECR0 */
+#define MLB_FROM_CECR1 (*(struct st_mlb_from_cecr0 *)&MLB.CECR1) /* MLB_FROM_CECR1 */
+#define MLB_FROM_CECR2 (*(struct st_mlb_from_cecr0 *)&MLB.CECR2) /* MLB_FROM_CECR2 */
+#define MLB_FROM_CECR3 (*(struct st_mlb_from_cecr0 *)&MLB.CECR3) /* MLB_FROM_CECR3 */
+#define MLB_FROM_CECR4 (*(struct st_mlb_from_cecr0 *)&MLB.CECR4) /* MLB_FROM_CECR4 */
+#define MLB_FROM_CECR5 (*(struct st_mlb_from_cecr0 *)&MLB.CECR5) /* MLB_FROM_CECR5 */
+#define MLB_FROM_CECR6 (*(struct st_mlb_from_cecr0 *)&MLB.CECR6) /* MLB_FROM_CECR6 */
+#define MLB_FROM_CECR7 (*(struct st_mlb_from_cecr0 *)&MLB.CECR7) /* MLB_FROM_CECR7 */
+#define MLB_FROM_CECR8 (*(struct st_mlb_from_cecr0 *)&MLB.CECR8) /* MLB_FROM_CECR8 */
+#define MLB_FROM_CECR9 (*(struct st_mlb_from_cecr0 *)&MLB.CECR9) /* MLB_FROM_CECR9 */
+#define MLB_FROM_CECR10 (*(struct st_mlb_from_cecr0 *)&MLB.CECR10) /* MLB_FROM_CECR10 */
+#define MLB_FROM_CECR11 (*(struct st_mlb_from_cecr0 *)&MLB.CECR11) /* MLB_FROM_CECR11 */
+#define MLB_FROM_CECR12 (*(struct st_mlb_from_cecr0 *)&MLB.CECR12) /* MLB_FROM_CECR12 */
+#define MLB_FROM_CECR13 (*(struct st_mlb_from_cecr0 *)&MLB.CECR13) /* MLB_FROM_CECR13 */
+#define MLB_FROM_CECR14 (*(struct st_mlb_from_cecr0 *)&MLB.CECR14) /* MLB_FROM_CECR14 */
+#define MLB_FROM_CECR15 (*(struct st_mlb_from_cecr0 *)&MLB.CECR15) /* MLB_FROM_CECR15 */
+#define MLB_FROM_CECR16 (*(struct st_mlb_from_cecr0 *)&MLB.CECR16) /* MLB_FROM_CECR16 */
+#define MLB_FROM_CECR17 (*(struct st_mlb_from_cecr0 *)&MLB.CECR17) /* MLB_FROM_CECR17 */
+#define MLB_FROM_CECR18 (*(struct st_mlb_from_cecr0 *)&MLB.CECR18) /* MLB_FROM_CECR18 */
+#define MLB_FROM_CECR19 (*(struct st_mlb_from_cecr0 *)&MLB.CECR19) /* MLB_FROM_CECR19 */
+#define MLB_FROM_CECR20 (*(struct st_mlb_from_cecr0 *)&MLB.CECR20) /* MLB_FROM_CECR20 */
+#define MLB_FROM_CECR21 (*(struct st_mlb_from_cecr0 *)&MLB.CECR21) /* MLB_FROM_CECR21 */
+#define MLB_FROM_CECR22 (*(struct st_mlb_from_cecr0 *)&MLB.CECR22) /* MLB_FROM_CECR22 */
+#define MLB_FROM_CECR23 (*(struct st_mlb_from_cecr0 *)&MLB.CECR23) /* MLB_FROM_CECR23 */
+#define MLB_FROM_CECR24 (*(struct st_mlb_from_cecr0 *)&MLB.CECR24) /* MLB_FROM_CECR24 */
+#define MLB_FROM_CECR25 (*(struct st_mlb_from_cecr0 *)&MLB.CECR25) /* MLB_FROM_CECR25 */
+#define MLB_FROM_CECR26 (*(struct st_mlb_from_cecr0 *)&MLB.CECR26) /* MLB_FROM_CECR26 */
+#define MLB_FROM_CECR27 (*(struct st_mlb_from_cecr0 *)&MLB.CECR27) /* MLB_FROM_CECR27 */
+#define MLB_FROM_CECR28 (*(struct st_mlb_from_cecr0 *)&MLB.CECR28) /* MLB_FROM_CECR28 */
+#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */
+#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */
+
+/* End of channnel array defines of MLB */
+
+
+#define MLBDCCR MLB.DCCR
+#define MLBSSCR MLB.SSCR
+#define MLBSDCR MLB.SDCR
+#define MLBSMCR MLB.SMCR
+#define MLBVCCR MLB.VCCR
+#define MLBSBCR MLB.SBCR
+#define MLBABCR MLB.ABCR
+#define MLBCBCR MLB.CBCR
+#define MLBIBCR MLB.IBCR
+#define MLBCICR MLB.CICR
+#define MLBCECR0 MLB.CECR0
+#define MLBCSCR0 MLB.CSCR0
+#define MLBCCBCR0 MLB.CCBCR0
+#define MLBCNBCR0 MLB.CNBCR0
+#define MLBCECR1 MLB.CECR1
+#define MLBCSCR1 MLB.CSCR1
+#define MLBCCBCR1 MLB.CCBCR1
+#define MLBCNBCR1 MLB.CNBCR1
+#define MLBCECR2 MLB.CECR2
+#define MLBCSCR2 MLB.CSCR2
+#define MLBCCBCR2 MLB.CCBCR2
+#define MLBCNBCR2 MLB.CNBCR2
+#define MLBCECR3 MLB.CECR3
+#define MLBCSCR3 MLB.CSCR3
+#define MLBCCBCR3 MLB.CCBCR3
+#define MLBCNBCR3 MLB.CNBCR3
+#define MLBCECR4 MLB.CECR4
+#define MLBCSCR4 MLB.CSCR4
+#define MLBCCBCR4 MLB.CCBCR4
+#define MLBCNBCR4 MLB.CNBCR4
+#define MLBCECR5 MLB.CECR5
+#define MLBCSCR5 MLB.CSCR5
+#define MLBCCBCR5 MLB.CCBCR5
+#define MLBCNBCR5 MLB.CNBCR5
+#define MLBCECR6 MLB.CECR6
+#define MLBCSCR6 MLB.CSCR6
+#define MLBCCBCR6 MLB.CCBCR6
+#define MLBCNBCR6 MLB.CNBCR6
+#define MLBCECR7 MLB.CECR7
+#define MLBCSCR7 MLB.CSCR7
+#define MLBCCBCR7 MLB.CCBCR7
+#define MLBCNBCR7 MLB.CNBCR7
+#define MLBCECR8 MLB.CECR8
+#define MLBCSCR8 MLB.CSCR8
+#define MLBCCBCR8 MLB.CCBCR8
+#define MLBCNBCR8 MLB.CNBCR8
+#define MLBCECR9 MLB.CECR9
+#define MLBCSCR9 MLB.CSCR9
+#define MLBCCBCR9 MLB.CCBCR9
+#define MLBCNBCR9 MLB.CNBCR9
+#define MLBCECR10 MLB.CECR10
+#define MLBCSCR10 MLB.CSCR10
+#define MLBCCBCR10 MLB.CCBCR10
+#define MLBCNBCR10 MLB.CNBCR10
+#define MLBCECR11 MLB.CECR11
+#define MLBCSCR11 MLB.CSCR11
+#define MLBCCBCR11 MLB.CCBCR11
+#define MLBCNBCR11 MLB.CNBCR11
+#define MLBCECR12 MLB.CECR12
+#define MLBCSCR12 MLB.CSCR12
+#define MLBCCBCR12 MLB.CCBCR12
+#define MLBCNBCR12 MLB.CNBCR12
+#define MLBCECR13 MLB.CECR13
+#define MLBCSCR13 MLB.CSCR13
+#define MLBCCBCR13 MLB.CCBCR13
+#define MLBCNBCR13 MLB.CNBCR13
+#define MLBCECR14 MLB.CECR14
+#define MLBCSCR14 MLB.CSCR14
+#define MLBCCBCR14 MLB.CCBCR14
+#define MLBCNBCR14 MLB.CNBCR14
+#define MLBCECR15 MLB.CECR15
+#define MLBCSCR15 MLB.CSCR15
+#define MLBCCBCR15 MLB.CCBCR15
+#define MLBCNBCR15 MLB.CNBCR15
+#define MLBCECR16 MLB.CECR16
+#define MLBCSCR16 MLB.CSCR16
+#define MLBCCBCR16 MLB.CCBCR16
+#define MLBCNBCR16 MLB.CNBCR16
+#define MLBCECR17 MLB.CECR17
+#define MLBCSCR17 MLB.CSCR17
+#define MLBCCBCR17 MLB.CCBCR17
+#define MLBCNBCR17 MLB.CNBCR17
+#define MLBCECR18 MLB.CECR18
+#define MLBCSCR18 MLB.CSCR18
+#define MLBCCBCR18 MLB.CCBCR18
+#define MLBCNBCR18 MLB.CNBCR18
+#define MLBCECR19 MLB.CECR19
+#define MLBCSCR19 MLB.CSCR19
+#define MLBCCBCR19 MLB.CCBCR19
+#define MLBCNBCR19 MLB.CNBCR19
+#define MLBCECR20 MLB.CECR20
+#define MLBCSCR20 MLB.CSCR20
+#define MLBCCBCR20 MLB.CCBCR20
+#define MLBCNBCR20 MLB.CNBCR20
+#define MLBCECR21 MLB.CECR21
+#define MLBCSCR21 MLB.CSCR21
+#define MLBCCBCR21 MLB.CCBCR21
+#define MLBCNBCR21 MLB.CNBCR21
+#define MLBCECR22 MLB.CECR22
+#define MLBCSCR22 MLB.CSCR22
+#define MLBCCBCR22 MLB.CCBCR22
+#define MLBCNBCR22 MLB.CNBCR22
+#define MLBCECR23 MLB.CECR23
+#define MLBCSCR23 MLB.CSCR23
+#define MLBCCBCR23 MLB.CCBCR23
+#define MLBCNBCR23 MLB.CNBCR23
+#define MLBCECR24 MLB.CECR24
+#define MLBCSCR24 MLB.CSCR24
+#define MLBCCBCR24 MLB.CCBCR24
+#define MLBCNBCR24 MLB.CNBCR24
+#define MLBCECR25 MLB.CECR25
+#define MLBCSCR25 MLB.CSCR25
+#define MLBCCBCR25 MLB.CCBCR25
+#define MLBCNBCR25 MLB.CNBCR25
+#define MLBCECR26 MLB.CECR26
+#define MLBCSCR26 MLB.CSCR26
+#define MLBCCBCR26 MLB.CCBCR26
+#define MLBCNBCR26 MLB.CNBCR26
+#define MLBCECR27 MLB.CECR27
+#define MLBCSCR27 MLB.CSCR27
+#define MLBCCBCR27 MLB.CCBCR27
+#define MLBCNBCR27 MLB.CNBCR27
+#define MLBCECR28 MLB.CECR28
+#define MLBCSCR28 MLB.CSCR28
+#define MLBCCBCR28 MLB.CCBCR28
+#define MLBCNBCR28 MLB.CNBCR28
+#define MLBCECR29 MLB.CECR29
+#define MLBCSCR29 MLB.CSCR29
+#define MLBCCBCR29 MLB.CCBCR29
+#define MLBCNBCR29 MLB.CNBCR29
+#define MLBCECR30 MLB.CECR30
+#define MLBCSCR30 MLB.CSCR30
+#define MLBCCBCR30 MLB.CCBCR30
+#define MLBCNBCR30 MLB.CNBCR30
+#define MLBLCBCR0 MLB.LCBCR0
+#define MLBLCBCR1 MLB.LCBCR1
+#define MLBLCBCR2 MLB.LCBCR2
+#define MLBLCBCR3 MLB.LCBCR3
+#define MLBLCBCR4 MLB.LCBCR4
+#define MLBLCBCR5 MLB.LCBCR5
+#define MLBLCBCR6 MLB.LCBCR6
+#define MLBLCBCR7 MLB.LCBCR7
+#define MLBLCBCR8 MLB.LCBCR8
+#define MLBLCBCR9 MLB.LCBCR9
+#define MLBLCBCR10 MLB.LCBCR10
+#define MLBLCBCR11 MLB.LCBCR11
+#define MLBLCBCR12 MLB.LCBCR12
+#define MLBLCBCR13 MLB.LCBCR13
+#define MLBLCBCR14 MLB.LCBCR14
+#define MLBLCBCR15 MLB.LCBCR15
+#define MLBLCBCR16 MLB.LCBCR16
+#define MLBLCBCR17 MLB.LCBCR17
+#define MLBLCBCR18 MLB.LCBCR18
+#define MLBLCBCR19 MLB.LCBCR19
+#define MLBLCBCR20 MLB.LCBCR20
+#define MLBLCBCR21 MLB.LCBCR21
+#define MLBLCBCR22 MLB.LCBCR22
+#define MLBLCBCR23 MLB.LCBCR23
+#define MLBLCBCR24 MLB.LCBCR24
+#define MLBLCBCR25 MLB.LCBCR25
+#define MLBLCBCR26 MLB.LCBCR26
+#define MLBLCBCR27 MLB.LCBCR27
+#define MLBLCBCR28 MLB.LCBCR28
+#define MLBLCBCR29 MLB.LCBCR29
+#define MLBLCBCR30 MLB.LCBCR30
+/* <-SEC M1.10.1 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/mmc_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,93 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mmc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef MMC_IODEFINE_H
+#define MMC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_mmc
+{                                                          /* MMC              */
+    volatile uint16_t CE_CMD_SETH;                      /*  CE_CMD_SETH */
+    volatile uint16_t CE_CMD_SETL;                      /*  CE_CMD_SETL */
+    volatile uint8_t   dummy182[4];                            /*                  */
+    volatile uint32_t  CE_ARG;                                 /*  CE_ARG          */
+    volatile uint32_t  CE_ARG_CMD12;                           /*  CE_ARG_CMD12    */
+    volatile uint32_t  CE_CMD_CTRL;                            /*  CE_CMD_CTRL     */
+    volatile uint32_t  CE_BLOCK_SET;                           /*  CE_BLOCK_SET    */
+    volatile uint32_t  CE_CLK_CTRL;                            /*  CE_CLK_CTRL     */
+    volatile uint32_t  CE_BUF_ACC;                             /*  CE_BUF_ACC      */
+#define MMC_CE_RESPn_COUNT 4
+    volatile uint32_t  CE_RESP3;                               /*  CE_RESP3        */
+    volatile uint32_t  CE_RESP2;                               /*  CE_RESP2        */
+    volatile uint32_t  CE_RESP1;                               /*  CE_RESP1        */
+    volatile uint32_t  CE_RESP0;                               /*  CE_RESP0        */
+    volatile uint32_t  CE_RESP_CMD12;                          /*  CE_RESP_CMD12   */
+    volatile uint32_t  CE_DATA;                                /*  CE_DATA         */
+    volatile uint8_t   dummy183[8];                            /*                  */
+    volatile uint32_t  CE_INT;                                 /*  CE_INT          */
+    volatile uint32_t  CE_INT_EN;                              /*  CE_INT_EN       */
+    volatile uint32_t  CE_HOST_STS1;                           /*  CE_HOST_STS1    */
+    volatile uint32_t  CE_HOST_STS2;                           /*  CE_HOST_STS2    */
+    volatile uint8_t   dummy184[12];                           /*                  */
+    volatile uint32_t  CE_DMA_MODE;                            /*  CE_DMA_MODE     */
+    volatile uint8_t   dummy185[16];                           /*                  */
+    volatile uint32_t  CE_DETECT;                              /*  CE_DETECT       */
+    volatile uint32_t  CE_ADD_MODE;                            /*  CE_ADD_MODE     */
+    volatile uint8_t   dummy186[4];                            /*                  */
+    volatile uint32_t  CE_VERSION;                             /*  CE_VERSION      */
+};
+
+
+#define MMC     (*(struct st_mmc     *)0xE804C800uL) /* MMC */
+
+
+#define MMCCE_CMD_SETH MMC.CE_CMD_SETH
+#define MMCCE_CMD_SETL MMC.CE_CMD_SETL
+#define MMCCE_ARG MMC.CE_ARG
+#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12
+#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL
+#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET
+#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL
+#define MMCCE_BUF_ACC MMC.CE_BUF_ACC
+#define MMCCE_RESP3 MMC.CE_RESP3
+#define MMCCE_RESP2 MMC.CE_RESP2
+#define MMCCE_RESP1 MMC.CE_RESP1
+#define MMCCE_RESP0 MMC.CE_RESP0
+#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12
+#define MMCCE_DATA MMC.CE_DATA
+#define MMCCE_INT MMC.CE_INT
+#define MMCCE_INT_EN MMC.CE_INT_EN
+#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1
+#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2
+#define MMCCE_DMA_MODE MMC.CE_DMA_MODE
+#define MMCCE_DETECT MMC.CE_DETECT
+#define MMCCE_ADD_MODE MMC.CE_ADD_MODE
+#define MMCCE_VERSION MMC.CE_VERSION
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/mtu2_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,218 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : mtu2_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef MTU2_IODEFINE_H
+#define MTU2_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_mtu2
+{                                                          /* MTU2             */
+    volatile uint8_t   TCR_2;                                  /*  TCR_2           */
+    volatile uint8_t   TMDR_2;                                 /*  TMDR_2          */
+    volatile uint8_t   TIOR_2;                                 /*  TIOR_2          */
+    volatile uint8_t   dummy520[1];                            /*                  */
+    volatile uint8_t   TIER_2;                                 /*  TIER_2          */
+    volatile uint8_t   TSR_2;                                  /*  TSR_2           */
+    volatile uint16_t TCNT_2;                                 /*  TCNT_2          */
+    volatile uint16_t TGRA_2;                                 /*  TGRA_2          */
+    volatile uint16_t TGRB_2;                                 /*  TGRB_2          */
+    volatile uint8_t   dummy521[500];                          /*                  */
+    volatile uint8_t   TCR_3;                                  /*  TCR_3           */
+    volatile uint8_t   TCR_4;                                  /*  TCR_4           */
+    volatile uint8_t   TMDR_3;                                 /*  TMDR_3          */
+    volatile uint8_t   TMDR_4;                                 /*  TMDR_4          */
+    volatile uint8_t   TIORH_3;                                /*  TIORH_3         */
+    volatile uint8_t   TIORL_3;                                /*  TIORL_3         */
+    volatile uint8_t   TIORH_4;                                /*  TIORH_4         */
+    volatile uint8_t   TIORL_4;                                /*  TIORL_4         */
+    volatile uint8_t   TIER_3;                                 /*  TIER_3          */
+    volatile uint8_t   TIER_4;                                 /*  TIER_4          */
+    volatile uint8_t   TOER;                                   /*  TOER            */
+    volatile uint8_t   dummy522[2];                            /*                  */
+    volatile uint8_t   TGCR;                                   /*  TGCR            */
+    volatile uint8_t   TOCR1;                                  /*  TOCR1           */
+    volatile uint8_t   TOCR2;                                  /*  TOCR2           */
+    volatile uint16_t TCNT_3;                                 /*  TCNT_3          */
+    volatile uint16_t TCNT_4;                                 /*  TCNT_4          */
+    volatile uint16_t TCDR;                                   /*  TCDR            */
+    volatile uint16_t TDDR;                                   /*  TDDR            */
+    volatile uint16_t TGRA_3;                                 /*  TGRA_3          */
+    volatile uint16_t TGRB_3;                                 /*  TGRB_3          */
+    volatile uint16_t TGRA_4;                                 /*  TGRA_4          */
+    volatile uint16_t TGRB_4;                                 /*  TGRB_4          */
+    volatile uint16_t TCNTS;                                  /*  TCNTS           */
+    volatile uint16_t TCBR;                                   /*  TCBR            */
+    volatile uint16_t TGRC_3;                                 /*  TGRC_3          */
+    volatile uint16_t TGRD_3;                                 /*  TGRD_3          */
+    volatile uint16_t TGRC_4;                                 /*  TGRC_4          */
+    volatile uint16_t TGRD_4;                                 /*  TGRD_4          */
+    volatile uint8_t   TSR_3;                                  /*  TSR_3           */
+    volatile uint8_t   TSR_4;                                  /*  TSR_4           */
+    volatile uint8_t   dummy523[2];                            /*                  */
+    volatile uint8_t   TITCR;                                  /*  TITCR           */
+    volatile uint8_t   TITCNT;                                 /*  TITCNT          */
+    volatile uint8_t   TBTER;                                  /*  TBTER           */
+    volatile uint8_t   dummy524[1];                            /*                  */
+    volatile uint8_t   TDER;                                   /*  TDER            */
+    volatile uint8_t   dummy525[1];                            /*                  */
+    volatile uint8_t   TOLBR;                                  /*  TOLBR           */
+    volatile uint8_t   dummy526[1];                            /*                  */
+    volatile uint8_t   TBTM_3;                                 /*  TBTM_3          */
+    volatile uint8_t   TBTM_4;                                 /*  TBTM_4          */
+    volatile uint8_t   dummy527[6];                            /*                  */
+    volatile uint16_t TADCR;                                  /*  TADCR           */
+    volatile uint8_t   dummy528[2];                            /*                  */
+    volatile uint16_t TADCORA_4;                              /*  TADCORA_4       */
+    volatile uint16_t TADCORB_4;                              /*  TADCORB_4       */
+    volatile uint16_t TADCOBRA_4;                             /*  TADCOBRA_4      */
+    volatile uint16_t TADCOBRB_4;                             /*  TADCOBRB_4      */
+    volatile uint8_t   dummy529[20];                           /*                  */
+    volatile uint8_t   TWCR;                                   /*  TWCR            */
+    volatile uint8_t   dummy530[31];                           /*                  */
+    volatile uint8_t   TSTR;                                   /*  TSTR            */
+    volatile uint8_t   TSYR;                                   /*  TSYR            */
+    volatile uint8_t   dummy531[2];                            /*                  */
+    volatile uint8_t   TRWER;                                  /*  TRWER           */
+    volatile uint8_t   dummy532[123];                          /*                  */
+    volatile uint8_t   TCR_0;                                  /*  TCR_0           */
+    volatile uint8_t   TMDR_0;                                 /*  TMDR_0          */
+    volatile uint8_t   TIORH_0;                                /*  TIORH_0         */
+    volatile uint8_t   TIORL_0;                                /*  TIORL_0         */
+    volatile uint8_t   TIER_0;                                 /*  TIER_0          */
+    volatile uint8_t   TSR_0;                                  /*  TSR_0           */
+    volatile uint16_t TCNT_0;                                 /*  TCNT_0          */
+    volatile uint16_t TGRA_0;                                 /*  TGRA_0          */
+    volatile uint16_t TGRB_0;                                 /*  TGRB_0          */
+    volatile uint16_t TGRC_0;                                 /*  TGRC_0          */
+    volatile uint16_t TGRD_0;                                 /*  TGRD_0          */
+    volatile uint8_t   dummy533[16];                           /*                  */
+    volatile uint16_t TGRE_0;                                 /*  TGRE_0          */
+    volatile uint16_t TGRF_0;                                 /*  TGRF_0          */
+    volatile uint8_t   TIER2_0;                                /*  TIER2_0         */
+    volatile uint8_t   TSR2_0;                                 /*  TSR2_0          */
+    volatile uint8_t   TBTM_0;                                 /*  TBTM_0          */
+    volatile uint8_t   dummy534[89];                           /*                  */
+    volatile uint8_t   TCR_1;                                  /*  TCR_1           */
+    volatile uint8_t   TMDR_1;                                 /*  TMDR_1          */
+    volatile uint8_t   TIOR_1;                                 /*  TIOR_1          */
+    volatile uint8_t   dummy535[1];                            /*                  */
+    volatile uint8_t   TIER_1;                                 /*  TIER_1          */
+    volatile uint8_t   TSR_1;                                  /*  TSR_1           */
+    volatile uint16_t TCNT_1;                                 /*  TCNT_1          */
+    volatile uint16_t TGRA_1;                                 /*  TGRA_1          */
+    volatile uint16_t TGRB_1;                                 /*  TGRB_1          */
+    volatile uint8_t   dummy536[4];                            /*                  */
+    volatile uint8_t   TICCR;                                  /*  TICCR           */
+};
+
+
+#define MTU2    (*(struct st_mtu2    *)0xFCFF0000uL) /* MTU2 */
+
+
+#define MTU2TCR_2 MTU2.TCR_2
+#define MTU2TMDR_2 MTU2.TMDR_2
+#define MTU2TIOR_2 MTU2.TIOR_2
+#define MTU2TIER_2 MTU2.TIER_2
+#define MTU2TSR_2 MTU2.TSR_2
+#define MTU2TCNT_2 MTU2.TCNT_2
+#define MTU2TGRA_2 MTU2.TGRA_2
+#define MTU2TGRB_2 MTU2.TGRB_2
+#define MTU2TCR_3 MTU2.TCR_3
+#define MTU2TCR_4 MTU2.TCR_4
+#define MTU2TMDR_3 MTU2.TMDR_3
+#define MTU2TMDR_4 MTU2.TMDR_4
+#define MTU2TIORH_3 MTU2.TIORH_3
+#define MTU2TIORL_3 MTU2.TIORL_3
+#define MTU2TIORH_4 MTU2.TIORH_4
+#define MTU2TIORL_4 MTU2.TIORL_4
+#define MTU2TIER_3 MTU2.TIER_3
+#define MTU2TIER_4 MTU2.TIER_4
+#define MTU2TOER MTU2.TOER
+#define MTU2TGCR MTU2.TGCR
+#define MTU2TOCR1 MTU2.TOCR1
+#define MTU2TOCR2 MTU2.TOCR2
+#define MTU2TCNT_3 MTU2.TCNT_3
+#define MTU2TCNT_4 MTU2.TCNT_4
+#define MTU2TCDR MTU2.TCDR
+#define MTU2TDDR MTU2.TDDR
+#define MTU2TGRA_3 MTU2.TGRA_3
+#define MTU2TGRB_3 MTU2.TGRB_3
+#define MTU2TGRA_4 MTU2.TGRA_4
+#define MTU2TGRB_4 MTU2.TGRB_4
+#define MTU2TCNTS MTU2.TCNTS
+#define MTU2TCBR MTU2.TCBR
+#define MTU2TGRC_3 MTU2.TGRC_3
+#define MTU2TGRD_3 MTU2.TGRD_3
+#define MTU2TGRC_4 MTU2.TGRC_4
+#define MTU2TGRD_4 MTU2.TGRD_4
+#define MTU2TSR_3 MTU2.TSR_3
+#define MTU2TSR_4 MTU2.TSR_4
+#define MTU2TITCR MTU2.TITCR
+#define MTU2TITCNT MTU2.TITCNT
+#define MTU2TBTER MTU2.TBTER
+#define MTU2TDER MTU2.TDER
+#define MTU2TOLBR MTU2.TOLBR
+#define MTU2TBTM_3 MTU2.TBTM_3
+#define MTU2TBTM_4 MTU2.TBTM_4
+#define MTU2TADCR MTU2.TADCR
+#define MTU2TADCORA_4 MTU2.TADCORA_4
+#define MTU2TADCORB_4 MTU2.TADCORB_4
+#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4
+#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4
+#define MTU2TWCR MTU2.TWCR
+#define MTU2TSTR MTU2.TSTR
+#define MTU2TSYR MTU2.TSYR
+#define MTU2TRWER MTU2.TRWER
+#define MTU2TCR_0 MTU2.TCR_0
+#define MTU2TMDR_0 MTU2.TMDR_0
+#define MTU2TIORH_0 MTU2.TIORH_0
+#define MTU2TIORL_0 MTU2.TIORL_0
+#define MTU2TIER_0 MTU2.TIER_0
+#define MTU2TSR_0 MTU2.TSR_0
+#define MTU2TCNT_0 MTU2.TCNT_0
+#define MTU2TGRA_0 MTU2.TGRA_0
+#define MTU2TGRB_0 MTU2.TGRB_0
+#define MTU2TGRC_0 MTU2.TGRC_0
+#define MTU2TGRD_0 MTU2.TGRD_0
+#define MTU2TGRE_0 MTU2.TGRE_0
+#define MTU2TGRF_0 MTU2.TGRF_0
+#define MTU2TIER2_0 MTU2.TIER2_0
+#define MTU2TSR2_0 MTU2.TSR2_0
+#define MTU2TBTM_0 MTU2.TBTM_0
+#define MTU2TCR_1 MTU2.TCR_1
+#define MTU2TMDR_1 MTU2.TMDR_1
+#define MTU2TIOR_1 MTU2.TIOR_1
+#define MTU2TIER_1 MTU2.TIER_1
+#define MTU2TSR_1 MTU2.TSR_1
+#define MTU2TCNT_1 MTU2.TCNT_1
+#define MTU2TGRA_1 MTU2.TGRA_1
+#define MTU2TGRB_1 MTU2.TGRB_1
+#define MTU2TICCR MTU2.TICCR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ostm_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,79 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ostm_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef OSTM_IODEFINE_H
+#define OSTM_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ostm
+{                                                          /* OSTM             */
+    volatile uint32_t  OSTMnCMP;                               /*  OSTMnCMP        */
+    volatile uint32_t  OSTMnCNT;                               /*  OSTMnCNT        */
+    volatile uint8_t   dummy1[8];                              /*                  */
+    volatile uint8_t   OSTMnTE;                                /*  OSTMnTE         */
+    volatile uint8_t   dummy2[3];                              /*                  */
+    volatile uint8_t   OSTMnTS;                                /*  OSTMnTS         */
+    volatile uint8_t   dummy3[3];                              /*                  */
+    volatile uint8_t   OSTMnTT;                                /*  OSTMnTT         */
+    volatile uint8_t   dummy4[7];                              /*                  */
+    volatile uint8_t   OSTMnCTL;                               /*  OSTMnCTL        */
+};
+
+
+#define OSTM0   (*(struct st_ostm    *)0xFCFEC000uL) /* OSTM0 */
+#define OSTM1   (*(struct st_ostm    *)0xFCFEC400uL) /* OSTM1 */
+
+
+/* Start of channnel array defines of OSTM */
+
+/* Channnel array defines of OSTM */
+/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
+#define OSTM_COUNT  2
+#define OSTM_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &OSTM0, &OSTM1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of OSTM */
+
+
+#define OSTM0CMP OSTM0.OSTMnCMP
+#define OSTM0CNT OSTM0.OSTMnCNT
+#define OSTM0TE OSTM0.OSTMnTE
+#define OSTM0TS OSTM0.OSTMnTS
+#define OSTM0TT OSTM0.OSTMnTT
+#define OSTM0CTL OSTM0.OSTMnCTL
+#define OSTM1CMP OSTM1.OSTMnCMP
+#define OSTM1CNT OSTM1.OSTMnCNT
+#define OSTM1TE OSTM1.OSTMnTE
+#define OSTM1TS OSTM1.OSTMnTS
+#define OSTM1TT OSTM1.OSTMnTT
+#define OSTM1CTL OSTM1.OSTMnCTL
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/pfv_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,151 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : pfv_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef PFV_IODEFINE_H
+#define PFV_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_pfv
+{                                                          /* PFV              */
+    volatile uint32_t  PFVCR;                                  /*  PFVCR           */
+    volatile uint32_t  PFVICR;                                 /*  PFVICR          */
+    volatile uint32_t  PFVISR;                                 /*  PFVISR          */
+    volatile uint8_t   dummy1[20];                             /*                  */
+#define PFVID_COUNT 8
+    volatile uint32_t  PFVID0;                                 /*  PFVID0          */
+    volatile uint32_t  PFVID1;                                 /*  PFVID1          */
+    volatile uint32_t  PFVID2;                                 /*  PFVID2          */
+    volatile uint32_t  PFVID3;                                 /*  PFVID3          */
+    volatile uint32_t  PFVID4;                                 /*  PFVID4          */
+    volatile uint32_t  PFVID5;                                 /*  PFVID5          */
+    volatile uint32_t  PFVID6;                                 /*  PFVID6          */
+    volatile uint32_t  PFVID7;                                 /*  PFVID7          */
+#define PFVOD_COUNT 8
+    volatile uint32_t  PFVOD0;                                 /*  PFVOD0          */
+    volatile uint32_t  PFVOD1;                                 /*  PFVOD1          */
+    volatile uint32_t  PFVOD2;                                 /*  PFVOD2          */
+    volatile uint32_t  PFVOD3;                                 /*  PFVOD3          */
+    volatile uint32_t  PFVOD4;                                 /*  PFVOD4          */
+    volatile uint32_t  PFVOD5;                                 /*  PFVOD5          */
+    volatile uint32_t  PFVOD6;                                 /*  PFVOD6          */
+    volatile uint32_t  PFVOD7;                                 /*  PFVOD7          */
+    volatile uint8_t   dummy2[4];                              /*                  */
+    volatile uint32_t  PFVIFSR;                                /*  PFVIFSR         */
+    volatile uint32_t  PFVOFSR;                                /*  PFVOFSR         */
+    volatile uint32_t  PFVACR;                                 /*  PFVACR          */
+    volatile uint32_t  PFV_MTX_MODE;                           /*  PFV_MTX_MODE    */
+    volatile uint32_t  PFV_MTX_YG_ADJ0;                        /*  PFV_MTX_YG_ADJ0 */
+    volatile uint32_t  PFV_MTX_YG_ADJ1;                        /*  PFV_MTX_YG_ADJ1 */
+    volatile uint32_t  PFV_MTX_CBB_ADJ0;                       /*  PFV_MTX_CBB_ADJ0 */
+    volatile uint32_t  PFV_MTX_CBB_ADJ1;                       /*  PFV_MTX_CBB_ADJ1 */
+    volatile uint32_t  PFV_MTX_CRR_ADJ0;                       /*  PFV_MTX_CRR_ADJ0 */
+    volatile uint32_t  PFV_MTX_CRR_ADJ1;                       /*  PFV_MTX_CRR_ADJ1 */
+    volatile uint32_t  PFVSZR;                                 /*  PFVSZR          */
+};
+
+
+#define PFV0    (*(struct st_pfv     *)0xE8205000uL) /* PFV0 */
+#define PFV1    (*(struct st_pfv     *)0xE8205800uL) /* PFV1 */
+
+
+/* Start of channnel array defines of PFV */
+
+/* Channnel array defines of PFV */
+/*(Sample) value = PFV[ channel ]->PFVCR; */
+#define PFV_COUNT  2
+#define PFV_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &PFV0, &PFV1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of PFV */
+
+
+#define PFV0PFVCR PFV0.PFVCR
+#define PFV0PFVICR PFV0.PFVICR
+#define PFV0PFVISR PFV0.PFVISR
+#define PFV0PFVID0 PFV0.PFVID0
+#define PFV0PFVID1 PFV0.PFVID1
+#define PFV0PFVID2 PFV0.PFVID2
+#define PFV0PFVID3 PFV0.PFVID3
+#define PFV0PFVID4 PFV0.PFVID4
+#define PFV0PFVID5 PFV0.PFVID5
+#define PFV0PFVID6 PFV0.PFVID6
+#define PFV0PFVID7 PFV0.PFVID7
+#define PFV0PFVOD0 PFV0.PFVOD0
+#define PFV0PFVOD1 PFV0.PFVOD1
+#define PFV0PFVOD2 PFV0.PFVOD2
+#define PFV0PFVOD3 PFV0.PFVOD3
+#define PFV0PFVOD4 PFV0.PFVOD4
+#define PFV0PFVOD5 PFV0.PFVOD5
+#define PFV0PFVOD6 PFV0.PFVOD6
+#define PFV0PFVOD7 PFV0.PFVOD7
+#define PFV0PFVIFSR PFV0.PFVIFSR
+#define PFV0PFVOFSR PFV0.PFVOFSR
+#define PFV0PFVACR PFV0.PFVACR
+#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE
+#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0
+#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1
+#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0
+#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1
+#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0
+#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1
+#define PFV0PFVSZR PFV0.PFVSZR
+#define PFV1PFVCR PFV1.PFVCR
+#define PFV1PFVICR PFV1.PFVICR
+#define PFV1PFVISR PFV1.PFVISR
+#define PFV1PFVID0 PFV1.PFVID0
+#define PFV1PFVID1 PFV1.PFVID1
+#define PFV1PFVID2 PFV1.PFVID2
+#define PFV1PFVID3 PFV1.PFVID3
+#define PFV1PFVID4 PFV1.PFVID4
+#define PFV1PFVID5 PFV1.PFVID5
+#define PFV1PFVID6 PFV1.PFVID6
+#define PFV1PFVID7 PFV1.PFVID7
+#define PFV1PFVOD0 PFV1.PFVOD0
+#define PFV1PFVOD1 PFV1.PFVOD1
+#define PFV1PFVOD2 PFV1.PFVOD2
+#define PFV1PFVOD3 PFV1.PFVOD3
+#define PFV1PFVOD4 PFV1.PFVOD4
+#define PFV1PFVOD5 PFV1.PFVOD5
+#define PFV1PFVOD6 PFV1.PFVOD6
+#define PFV1PFVOD7 PFV1.PFVOD7
+#define PFV1PFVIFSR PFV1.PFVIFSR
+#define PFV1PFVOFSR PFV1.PFVOFSR
+#define PFV1PFVACR PFV1.PFVACR
+#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE
+#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0
+#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1
+#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0
+#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1
+#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0
+#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1
+#define PFV1PFVSZR PFV1.PFVSZR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/pwm_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,136 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : pwm_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef PWM_IODEFINE_H
+#define PWM_IODEFINE_H
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+union reg16_8_t
+{
+    volatile uint16_t  UINT16;                                  /*  16-bit Access   */
+    volatile uint8_t   UINT8[2];                                /*  8-bit Access    */
+};
+
+struct st_pwm
+{                                                          /* PWM              */
+    volatile uint8_t   dummy559[2];                            /*                  */
+    union reg16_8_t  PWBTCR;                          /*  PWBTCR      */
+    
+    volatile uint8_t   dummy560[216];                          /*                  */
+    
+/* start of struct st_pwm_common */
+    union reg16_8_t  PWCR_1;                          /*  PWCR_1      */
+    
+    volatile uint8_t   dummy561[2];                            /*                  */
+    union reg16_8_t  PWPR_1;                          /*  PWPR_1      */
+    
+    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
+    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
+    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
+    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
+    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
+/* end of struct st_pwm_common */
+    
+/* start of struct st_pwm_common */
+    union reg16_8_t  PWCR_2;                          /*  PWCR_2      */
+    
+    volatile uint8_t   dummy562[2];                            /*                  */
+    union reg16_8_t  PWPR_2;                          /*  PWPR_2      */
+    
+    volatile uint16_t PWCYR_2;                                /*  PWCYR_2         */
+    volatile uint16_t PWBFR_2A;                               /*  PWBFR_2A        */
+    volatile uint16_t PWBFR_2C;                               /*  PWBFR_2C        */
+    volatile uint16_t PWBFR_2E;                               /*  PWBFR_2E        */
+    volatile uint16_t PWBFR_2G;                               /*  PWBFR_2G        */
+/* end of struct st_pwm_common */
+};
+
+
+struct st_pwm_common
+{
+    union reg16_8_t  PWCR_1;                          /*  PWCR_1      */
+    
+    volatile uint8_t   dummy572[2];                            /*                  */
+    union reg16_8_t  PWPR_1;                          /*  PWPR_1      */
+    
+    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
+    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
+    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
+    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
+    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
+};
+
+
+#define PWM     (*(struct st_pwm     *)0xFCFF5004uL) /* PWM */
+
+
+/* Start of channnel array defines of PWM */
+
+/* Channnel array defines of PWMn */
+/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */
+#define PWMn_COUNT  2
+#define PWMn_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &PWM1, &PWM2 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define PWM1    (*(struct st_pwm_common *)&PWM.PWCR_1)           /* PWM1 */
+#define PWM2    (*(struct st_pwm_common *)&PWM.PWCR_2)           /* PWM2 */
+
+/* End of channnel array defines of PWM */
+
+
+#define PWMPWBTCR PWM.PWBTCR.UINT16
+#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0]
+#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1]
+#define PWMPWCR_1 PWM.PWCR_1.UINT16
+#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0]
+#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1]
+#define PWMPWPR_1 PWM.PWPR_1.UINT16
+#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0]
+#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1]
+#define PWMPWCYR_1 PWM.PWCYR_1
+#define PWMPWBFR_1A PWM.PWBFR_1A
+#define PWMPWBFR_1C PWM.PWBFR_1C
+#define PWMPWBFR_1E PWM.PWBFR_1E
+#define PWMPWBFR_1G PWM.PWBFR_1G
+#define PWMPWCR_2 PWM.PWCR_2.UINT16
+#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0]
+#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1]
+#define PWMPWPR_2 PWM.PWPR_2.UINT16
+#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0]
+#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1]
+#define PWMPWCYR_2 PWM.PWCYR_2
+#define PWMPWBFR_2A PWM.PWBFR_2A
+#define PWMPWBFR_2C PWM.PWBFR_2C
+#define PWMPWBFR_2E PWM.PWBFR_2E
+#define PWMPWBFR_2G PWM.PWBFR_2G
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/riic_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,557 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : riic_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RIIC_IODEFINE_H
+#define RIIC_IODEFINE_H
+
+#include "reg32_t.h"
+
+struct st_riic
+{                                                          /* RIIC             */
+#define RIICnCRm_COUNT 2
+    union reg32_t  RIICnCR1;                      /*  RIICnCR1        */
+    union reg32_t  RIICnCR2;                      /*  RIICnCR2        */
+#define RIICnMRm_COUNT 3
+    union reg32_t  RIICnMR1;                      /*  RIICnMR1        */
+    union reg32_t  RIICnMR2;                      /*  RIICnMR2        */
+    union reg32_t  RIICnMR3;                      /*  RIICnMR3        */
+    union reg32_t  RIICnFER;                      /*  RIICnFER        */
+    union reg32_t  RIICnSER;                      /*  RIICnSER        */
+    union reg32_t  RIICnIER;                      /*  RIICnIER        */
+#define RIICnSRm_COUNT 2
+    union reg32_t  RIICnSR1;                      /*  RIICnSR1        */
+    union reg32_t  RIICnSR2;                      /*  RIICnSR2        */
+#define RIICnSARm_COUNT 3
+    union reg32_t  RIICnSAR0;                     /*  RIICnSAR0       */
+    union reg32_t  RIICnSAR1;                     /*  RIICnSAR1       */
+    union reg32_t  RIICnSAR2;                     /*  RIICnSAR2       */
+    union reg32_t  RIICnBRL;                      /*  RIICnBRL        */
+    union reg32_t  RIICnBRH;                      /*  RIICnBRH        */
+    union reg32_t  RIICnDRT;                      /*  RIICnDRT        */
+    union reg32_t  RIICnDRR;                      /*  RIICnDRR        */
+    
+};
+
+
+#define RIIC0   (*(struct st_riic    *)0xFCFEE000uL) /* RIIC0 */
+#define RIIC1   (*(struct st_riic    *)0xFCFEE400uL) /* RIIC1 */
+#define RIIC2   (*(struct st_riic    *)0xFCFEE800uL) /* RIIC2 */
+#define RIIC3   (*(struct st_riic    *)0xFCFEEC00uL) /* RIIC3 */
+
+
+/* Start of channnel array defines of RIIC */
+
+/* Channnel array defines of RIIC */
+/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */
+#define RIIC_COUNT  4
+#define RIIC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RIIC0, &RIIC1, &RIIC2, &RIIC3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of RIIC */
+
+
+#define RIIC0CR1 RIIC0.RIICnCR1.UINT32
+#define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L]
+#define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL]
+#define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH]
+#define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H]
+#define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL]
+#define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH]
+#define RIIC0CR2 RIIC0.RIICnCR2.UINT32
+#define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L]
+#define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL]
+#define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH]
+#define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H]
+#define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL]
+#define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH]
+#define RIIC0MR1 RIIC0.RIICnMR1.UINT32
+#define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L]
+#define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL]
+#define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH]
+#define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H]
+#define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL]
+#define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH]
+#define RIIC0MR2 RIIC0.RIICnMR2.UINT32
+#define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L]
+#define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL]
+#define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH]
+#define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H]
+#define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL]
+#define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH]
+#define RIIC0MR3 RIIC0.RIICnMR3.UINT32
+#define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L]
+#define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL]
+#define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH]
+#define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H]
+#define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL]
+#define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH]
+#define RIIC0FER RIIC0.RIICnFER.UINT32
+#define RIIC0FERL RIIC0.RIICnFER.UINT16[L]
+#define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL]
+#define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH]
+#define RIIC0FERH RIIC0.RIICnFER.UINT16[H]
+#define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL]
+#define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH]
+#define RIIC0SER RIIC0.RIICnSER.UINT32
+#define RIIC0SERL RIIC0.RIICnSER.UINT16[L]
+#define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL]
+#define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH]
+#define RIIC0SERH RIIC0.RIICnSER.UINT16[H]
+#define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL]
+#define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH]
+#define RIIC0IER RIIC0.RIICnIER.UINT32
+#define RIIC0IERL RIIC0.RIICnIER.UINT16[L]
+#define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL]
+#define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH]
+#define RIIC0IERH RIIC0.RIICnIER.UINT16[H]
+#define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL]
+#define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH]
+#define RIIC0SR1 RIIC0.RIICnSR1.UINT32
+#define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L]
+#define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL]
+#define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH]
+#define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H]
+#define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL]
+#define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH]
+#define RIIC0SR2 RIIC0.RIICnSR2.UINT32
+#define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L]
+#define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL]
+#define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH]
+#define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H]
+#define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL]
+#define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH]
+#define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32
+#define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L]
+#define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL]
+#define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH]
+#define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H]
+#define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL]
+#define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH]
+#define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32
+#define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L]
+#define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL]
+#define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH]
+#define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H]
+#define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL]
+#define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH]
+#define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32
+#define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L]
+#define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL]
+#define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH]
+#define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H]
+#define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL]
+#define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH]
+#define RIIC0BRL RIIC0.RIICnBRL.UINT32
+#define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L]
+#define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL]
+#define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH]
+#define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H]
+#define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL]
+#define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH]
+#define RIIC0BRH RIIC0.RIICnBRH.UINT32
+#define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L]
+#define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL]
+#define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH]
+#define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H]
+#define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL]
+#define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH]
+#define RIIC0DRT RIIC0.RIICnDRT.UINT32
+#define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L]
+#define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL]
+#define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH]
+#define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H]
+#define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL]
+#define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH]
+#define RIIC0DRR RIIC0.RIICnDRR.UINT32
+#define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L]
+#define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL]
+#define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH]
+#define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H]
+#define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL]
+#define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH]
+#define RIIC1CR1 RIIC1.RIICnCR1.UINT32
+#define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L]
+#define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL]
+#define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH]
+#define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H]
+#define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL]
+#define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH]
+#define RIIC1CR2 RIIC1.RIICnCR2.UINT32
+#define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L]
+#define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL]
+#define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH]
+#define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H]
+#define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL]
+#define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH]
+#define RIIC1MR1 RIIC1.RIICnMR1.UINT32
+#define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L]
+#define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL]
+#define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH]
+#define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H]
+#define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL]
+#define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH]
+#define RIIC1MR2 RIIC1.RIICnMR2.UINT32
+#define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L]
+#define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL]
+#define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH]
+#define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H]
+#define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL]
+#define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH]
+#define RIIC1MR3 RIIC1.RIICnMR3.UINT32
+#define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L]
+#define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL]
+#define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH]
+#define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H]
+#define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL]
+#define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH]
+#define RIIC1FER RIIC1.RIICnFER.UINT32
+#define RIIC1FERL RIIC1.RIICnFER.UINT16[L]
+#define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL]
+#define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH]
+#define RIIC1FERH RIIC1.RIICnFER.UINT16[H]
+#define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL]
+#define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH]
+#define RIIC1SER RIIC1.RIICnSER.UINT32
+#define RIIC1SERL RIIC1.RIICnSER.UINT16[L]
+#define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL]
+#define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH]
+#define RIIC1SERH RIIC1.RIICnSER.UINT16[H]
+#define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL]
+#define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH]
+#define RIIC1IER RIIC1.RIICnIER.UINT32
+#define RIIC1IERL RIIC1.RIICnIER.UINT16[L]
+#define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL]
+#define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH]
+#define RIIC1IERH RIIC1.RIICnIER.UINT16[H]
+#define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL]
+#define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH]
+#define RIIC1SR1 RIIC1.RIICnSR1.UINT32
+#define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L]
+#define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL]
+#define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH]
+#define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H]
+#define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL]
+#define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH]
+#define RIIC1SR2 RIIC1.RIICnSR2.UINT32
+#define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L]
+#define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL]
+#define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH]
+#define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H]
+#define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL]
+#define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH]
+#define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32
+#define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L]
+#define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL]
+#define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH]
+#define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H]
+#define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL]
+#define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH]
+#define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32
+#define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L]
+#define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL]
+#define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH]
+#define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H]
+#define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL]
+#define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH]
+#define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32
+#define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L]
+#define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL]
+#define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH]
+#define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H]
+#define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL]
+#define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH]
+#define RIIC1BRL RIIC1.RIICnBRL.UINT32
+#define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L]
+#define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL]
+#define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH]
+#define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H]
+#define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL]
+#define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH]
+#define RIIC1BRH RIIC1.RIICnBRH.UINT32
+#define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L]
+#define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL]
+#define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH]
+#define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H]
+#define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL]
+#define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH]
+#define RIIC1DRT RIIC1.RIICnDRT.UINT32
+#define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L]
+#define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL]
+#define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH]
+#define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H]
+#define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL]
+#define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH]
+#define RIIC1DRR RIIC1.RIICnDRR.UINT32
+#define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L]
+#define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL]
+#define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH]
+#define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H]
+#define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL]
+#define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH]
+#define RIIC2CR1 RIIC2.RIICnCR1.UINT32
+#define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L]
+#define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL]
+#define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH]
+#define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H]
+#define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL]
+#define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH]
+#define RIIC2CR2 RIIC2.RIICnCR2.UINT32
+#define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L]
+#define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL]
+#define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH]
+#define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H]
+#define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL]
+#define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH]
+#define RIIC2MR1 RIIC2.RIICnMR1.UINT32
+#define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L]
+#define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL]
+#define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH]
+#define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H]
+#define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL]
+#define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH]
+#define RIIC2MR2 RIIC2.RIICnMR2.UINT32
+#define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L]
+#define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL]
+#define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH]
+#define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H]
+#define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL]
+#define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH]
+#define RIIC2MR3 RIIC2.RIICnMR3.UINT32
+#define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L]
+#define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL]
+#define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH]
+#define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H]
+#define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL]
+#define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH]
+#define RIIC2FER RIIC2.RIICnFER.UINT32
+#define RIIC2FERL RIIC2.RIICnFER.UINT16[L]
+#define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL]
+#define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH]
+#define RIIC2FERH RIIC2.RIICnFER.UINT16[H]
+#define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL]
+#define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH]
+#define RIIC2SER RIIC2.RIICnSER.UINT32
+#define RIIC2SERL RIIC2.RIICnSER.UINT16[L]
+#define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL]
+#define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH]
+#define RIIC2SERH RIIC2.RIICnSER.UINT16[H]
+#define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL]
+#define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH]
+#define RIIC2IER RIIC2.RIICnIER.UINT32
+#define RIIC2IERL RIIC2.RIICnIER.UINT16[L]
+#define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL]
+#define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH]
+#define RIIC2IERH RIIC2.RIICnIER.UINT16[H]
+#define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL]
+#define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH]
+#define RIIC2SR1 RIIC2.RIICnSR1.UINT32
+#define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L]
+#define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL]
+#define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH]
+#define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H]
+#define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL]
+#define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH]
+#define RIIC2SR2 RIIC2.RIICnSR2.UINT32
+#define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L]
+#define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL]
+#define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH]
+#define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H]
+#define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL]
+#define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH]
+#define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32
+#define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L]
+#define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL]
+#define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH]
+#define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H]
+#define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL]
+#define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH]
+#define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32
+#define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L]
+#define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL]
+#define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH]
+#define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H]
+#define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL]
+#define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH]
+#define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32
+#define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L]
+#define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL]
+#define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH]
+#define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H]
+#define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL]
+#define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH]
+#define RIIC2BRL RIIC2.RIICnBRL.UINT32
+#define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L]
+#define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL]
+#define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH]
+#define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H]
+#define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL]
+#define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH]
+#define RIIC2BRH RIIC2.RIICnBRH.UINT32
+#define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L]
+#define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL]
+#define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH]
+#define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H]
+#define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL]
+#define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH]
+#define RIIC2DRT RIIC2.RIICnDRT.UINT32
+#define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L]
+#define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL]
+#define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH]
+#define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H]
+#define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL]
+#define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH]
+#define RIIC2DRR RIIC2.RIICnDRR.UINT32
+#define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L]
+#define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL]
+#define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH]
+#define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H]
+#define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL]
+#define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH]
+#define RIIC3CR1 RIIC3.RIICnCR1.UINT32
+#define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L]
+#define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL]
+#define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH]
+#define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H]
+#define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL]
+#define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH]
+#define RIIC3CR2 RIIC3.RIICnCR2.UINT32
+#define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L]
+#define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL]
+#define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH]
+#define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H]
+#define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL]
+#define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH]
+#define RIIC3MR1 RIIC3.RIICnMR1.UINT32
+#define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L]
+#define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL]
+#define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH]
+#define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H]
+#define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL]
+#define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH]
+#define RIIC3MR2 RIIC3.RIICnMR2.UINT32
+#define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L]
+#define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL]
+#define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH]
+#define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H]
+#define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL]
+#define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH]
+#define RIIC3MR3 RIIC3.RIICnMR3.UINT32
+#define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L]
+#define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL]
+#define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH]
+#define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H]
+#define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL]
+#define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH]
+#define RIIC3FER RIIC3.RIICnFER.UINT32
+#define RIIC3FERL RIIC3.RIICnFER.UINT16[L]
+#define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL]
+#define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH]
+#define RIIC3FERH RIIC3.RIICnFER.UINT16[H]
+#define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL]
+#define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH]
+#define RIIC3SER RIIC3.RIICnSER.UINT32
+#define RIIC3SERL RIIC3.RIICnSER.UINT16[L]
+#define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL]
+#define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH]
+#define RIIC3SERH RIIC3.RIICnSER.UINT16[H]
+#define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL]
+#define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH]
+#define RIIC3IER RIIC3.RIICnIER.UINT32
+#define RIIC3IERL RIIC3.RIICnIER.UINT16[L]
+#define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL]
+#define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH]
+#define RIIC3IERH RIIC3.RIICnIER.UINT16[H]
+#define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL]
+#define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH]
+#define RIIC3SR1 RIIC3.RIICnSR1.UINT32
+#define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L]
+#define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL]
+#define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH]
+#define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H]
+#define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL]
+#define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH]
+#define RIIC3SR2 RIIC3.RIICnSR2.UINT32
+#define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L]
+#define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL]
+#define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH]
+#define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H]
+#define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL]
+#define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH]
+#define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32
+#define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L]
+#define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL]
+#define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH]
+#define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H]
+#define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL]
+#define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH]
+#define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32
+#define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L]
+#define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL]
+#define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH]
+#define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H]
+#define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL]
+#define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH]
+#define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32
+#define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L]
+#define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL]
+#define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH]
+#define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H]
+#define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL]
+#define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH]
+#define RIIC3BRL RIIC3.RIICnBRL.UINT32
+#define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L]
+#define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL]
+#define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH]
+#define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H]
+#define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL]
+#define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH]
+#define RIIC3BRH RIIC3.RIICnBRH.UINT32
+#define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L]
+#define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL]
+#define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH]
+#define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H]
+#define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL]
+#define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH]
+#define RIIC3DRT RIIC3.RIICnDRT.UINT32
+#define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L]
+#define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL]
+#define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH]
+#define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H]
+#define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL]
+#define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH]
+#define RIIC3DRR RIIC3.RIICnDRR.UINT32
+#define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L]
+#define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL]
+#define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH]
+#define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H]
+#define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL]
+#define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH]
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/romdec_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,167 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : romdec_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef ROMDEC_IODEFINE_H
+#define ROMDEC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_romdec
+{                                                          /* ROMDEC           */
+    volatile uint8_t   CROMEN;                                 /*  CROMEN          */
+    volatile uint8_t   CROMSY0;                                /*  CROMSY0         */
+#define ROMDEC_CROMCTL0_COUNT 2
+    volatile uint8_t   CROMCTL0;                               /*  CROMCTL0        */
+    volatile uint8_t   CROMCTL1;                               /*  CROMCTL1        */
+    volatile uint8_t   dummy23[1];                             /*                  */
+    volatile uint8_t   CROMCTL3;                               /*  CROMCTL3        */
+    volatile uint8_t   CROMCTL4;                               /*  CROMCTL4        */
+    volatile uint8_t   CROMCTL5;                               /*  CROMCTL5        */
+#define ROMDEC_CROMST0_COUNT 2
+    volatile uint8_t   CROMST0;                                /*  CROMST0         */
+    volatile uint8_t   CROMST1;                                /*  CROMST1         */
+    volatile uint8_t   dummy24[1];                             /*                  */
+    volatile uint8_t   CROMST3;                                /*  CROMST3         */
+    volatile uint8_t   CROMST4;                                /*  CROMST4         */
+    volatile uint8_t   CROMST5;                                /*  CROMST5         */
+    volatile uint8_t   CROMST6;                                /*  CROMST6         */
+    volatile uint8_t   dummy25[5];                             /*                  */
+#define ROMDEC_CBUFST0_COUNT 3
+    volatile uint8_t   CBUFST0;                                /*  CBUFST0         */
+    volatile uint8_t   CBUFST1;                                /*  CBUFST1         */
+    volatile uint8_t   CBUFST2;                                /*  CBUFST2         */
+    volatile uint8_t   dummy26[1];                             /*                  */
+#define ROMDEC_HEAD00_COUNT 4
+    volatile uint8_t   HEAD00;                                 /*  HEAD00          */
+    volatile uint8_t   HEAD01;                                 /*  HEAD01          */
+    volatile uint8_t   HEAD02;                                 /*  HEAD02          */
+    volatile uint8_t   HEAD03;                                 /*  HEAD03          */
+#define ROMDEC_SHEAD00_COUNT 8
+    volatile uint8_t   SHEAD00;                                /*  SHEAD00         */
+    volatile uint8_t   SHEAD01;                                /*  SHEAD01         */
+    volatile uint8_t   SHEAD02;                                /*  SHEAD02         */
+    volatile uint8_t   SHEAD03;                                /*  SHEAD03         */
+    volatile uint8_t   SHEAD04;                                /*  SHEAD04         */
+    volatile uint8_t   SHEAD05;                                /*  SHEAD05         */
+    volatile uint8_t   SHEAD06;                                /*  SHEAD06         */
+    volatile uint8_t   SHEAD07;                                /*  SHEAD07         */
+#define ROMDEC_HEAD20_COUNT 4
+    volatile uint8_t   HEAD20;                                 /*  HEAD20          */
+    volatile uint8_t   HEAD21;                                 /*  HEAD21          */
+    volatile uint8_t   HEAD22;                                 /*  HEAD22          */
+    volatile uint8_t   HEAD23;                                 /*  HEAD23          */
+#define ROMDEC_SHEAD20_COUNT 8
+    volatile uint8_t   SHEAD20;                                /*  SHEAD20         */
+    volatile uint8_t   SHEAD21;                                /*  SHEAD21         */
+    volatile uint8_t   SHEAD22;                                /*  SHEAD22         */
+    volatile uint8_t   SHEAD23;                                /*  SHEAD23         */
+    volatile uint8_t   SHEAD24;                                /*  SHEAD24         */
+    volatile uint8_t   SHEAD25;                                /*  SHEAD25         */
+    volatile uint8_t   SHEAD26;                                /*  SHEAD26         */
+    volatile uint8_t   SHEAD27;                                /*  SHEAD27         */
+    volatile uint8_t   dummy27[16];                            /*                  */
+#define ROMDEC_CBUFCTL0_COUNT 4
+    volatile uint8_t   CBUFCTL0;                               /*  CBUFCTL0        */
+    volatile uint8_t   CBUFCTL1;                               /*  CBUFCTL1        */
+    volatile uint8_t   CBUFCTL2;                               /*  CBUFCTL2        */
+    volatile uint8_t   CBUFCTL3;                               /*  CBUFCTL3        */
+    volatile uint8_t   dummy28[1];                             /*                  */
+    volatile uint8_t   CROMST0M;                               /*  CROMST0M        */
+    volatile uint8_t   dummy29[186];                           /*                  */
+    volatile uint8_t   ROMDECRST;                              /*  ROMDECRST       */
+    volatile uint8_t   RSTSTAT;                                /*  RSTSTAT         */
+    volatile uint8_t   SSI;                                    /*  SSI             */
+    volatile uint8_t   dummy30[5];                             /*                  */
+    volatile uint8_t   INTHOLD;                                /*  INTHOLD         */
+    volatile uint8_t   INHINT;                                 /*  INHINT          */
+    volatile uint8_t   dummy31[246];                           /*                  */
+#define ROMDEC_STRMDIN0_COUNT 2
+    volatile uint16_t STRMDIN0;                               /*  STRMDIN0        */
+    volatile uint16_t STRMDIN2;                               /*  STRMDIN2        */
+    volatile uint16_t STRMDOUT0;                              /*  STRMDOUT0       */
+};
+
+
+#define ROMDEC  (*(struct st_romdec  *)0xE8005000uL) /* ROMDEC */
+
+
+#define ROMDECCROMEN ROMDEC.CROMEN
+#define ROMDECCROMSY0 ROMDEC.CROMSY0
+#define ROMDECCROMCTL0 ROMDEC.CROMCTL0
+#define ROMDECCROMCTL1 ROMDEC.CROMCTL1
+#define ROMDECCROMCTL3 ROMDEC.CROMCTL3
+#define ROMDECCROMCTL4 ROMDEC.CROMCTL4
+#define ROMDECCROMCTL5 ROMDEC.CROMCTL5
+#define ROMDECCROMST0 ROMDEC.CROMST0
+#define ROMDECCROMST1 ROMDEC.CROMST1
+#define ROMDECCROMST3 ROMDEC.CROMST3
+#define ROMDECCROMST4 ROMDEC.CROMST4
+#define ROMDECCROMST5 ROMDEC.CROMST5
+#define ROMDECCROMST6 ROMDEC.CROMST6
+#define ROMDECCBUFST0 ROMDEC.CBUFST0
+#define ROMDECCBUFST1 ROMDEC.CBUFST1
+#define ROMDECCBUFST2 ROMDEC.CBUFST2
+#define ROMDECHEAD00 ROMDEC.HEAD00
+#define ROMDECHEAD01 ROMDEC.HEAD01
+#define ROMDECHEAD02 ROMDEC.HEAD02
+#define ROMDECHEAD03 ROMDEC.HEAD03
+#define ROMDECSHEAD00 ROMDEC.SHEAD00
+#define ROMDECSHEAD01 ROMDEC.SHEAD01
+#define ROMDECSHEAD02 ROMDEC.SHEAD02
+#define ROMDECSHEAD03 ROMDEC.SHEAD03
+#define ROMDECSHEAD04 ROMDEC.SHEAD04
+#define ROMDECSHEAD05 ROMDEC.SHEAD05
+#define ROMDECSHEAD06 ROMDEC.SHEAD06
+#define ROMDECSHEAD07 ROMDEC.SHEAD07
+#define ROMDECHEAD20 ROMDEC.HEAD20
+#define ROMDECHEAD21 ROMDEC.HEAD21
+#define ROMDECHEAD22 ROMDEC.HEAD22
+#define ROMDECHEAD23 ROMDEC.HEAD23
+#define ROMDECSHEAD20 ROMDEC.SHEAD20
+#define ROMDECSHEAD21 ROMDEC.SHEAD21
+#define ROMDECSHEAD22 ROMDEC.SHEAD22
+#define ROMDECSHEAD23 ROMDEC.SHEAD23
+#define ROMDECSHEAD24 ROMDEC.SHEAD24
+#define ROMDECSHEAD25 ROMDEC.SHEAD25
+#define ROMDECSHEAD26 ROMDEC.SHEAD26
+#define ROMDECSHEAD27 ROMDEC.SHEAD27
+#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0
+#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1
+#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2
+#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3
+#define ROMDECCROMST0M ROMDEC.CROMST0M
+#define ROMDECROMDECRST ROMDEC.ROMDECRST
+#define ROMDECRSTSTAT ROMDEC.RSTSTAT
+#define ROMDECSSI ROMDEC.SSI
+#define ROMDECINTHOLD ROMDEC.INTHOLD
+#define ROMDECINHINT ROMDEC.INHINT
+#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0
+#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2
+#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/rscan0_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,9039 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rscan0_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RSCAN0_IODEFINE_H
+#define RSCAN0_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_rscan0
+{                                                          /* RSCAN0           */
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C0CFG;                         /*  C0CFG           */
+    union iodefine_reg32_t  C0CTR;                         /*  C0CTR           */
+    union iodefine_reg32_t  C0STS;                         /*  C0STS           */
+    union iodefine_reg32_t  C0ERFL;                        /*  C0ERFL          */
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C1CFG;                         /*  C1CFG           */
+    union iodefine_reg32_t  C1CTR;                         /*  C1CTR           */
+    union iodefine_reg32_t  C1STS;                         /*  C1STS           */
+    union iodefine_reg32_t  C1ERFL;                        /*  C1ERFL          */
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C2CFG;                         /*  C2CFG           */
+    union iodefine_reg32_t  C2CTR;                         /*  C2CTR           */
+    union iodefine_reg32_t  C2STS;                         /*  C2STS           */
+    union iodefine_reg32_t  C2ERFL;                        /*  C2ERFL          */
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C3CFG;                         /*  C3CFG           */
+    union iodefine_reg32_t  C3CTR;                         /*  C3CTR           */
+    union iodefine_reg32_t  C3STS;                         /*  C3STS           */
+    union iodefine_reg32_t  C3ERFL;                        /*  C3ERFL          */
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C4CFG;                         /*  C4CFG           */
+    union iodefine_reg32_t  C4CTR;                         /*  C4CTR           */
+    union iodefine_reg32_t  C4STS;                         /*  C4STS           */
+    union iodefine_reg32_t  C4ERFL;                        /*  C4ERFL          */
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+    volatile uint8_t   dummy159[52];                           /*                  */
+    union iodefine_reg32_t  GCFG;                          /*  GCFG            */
+    union iodefine_reg32_t  GCTR;                          /*  GCTR            */
+    union iodefine_reg32_t  GSTS;                          /*  GSTS            */
+    union iodefine_reg32_t  GERFL;                         /*  GERFL           */
+    union iodefine_reg32_16_t  GTSC;                       /*  GTSC            */
+    union iodefine_reg32_t  GAFLECTR;                      /*  GAFLECTR        */
+#define RSCAN0_GAFLCFG0_COUNT 2
+    union iodefine_reg32_t  GAFLCFG0;                      /*  GAFLCFG0        */
+    union iodefine_reg32_t  GAFLCFG1;                      /*  GAFLCFG1        */
+    union iodefine_reg32_t  RMNB;                          /*  RMNB            */
+#define RSCAN0_RMND0_COUNT 3
+    union iodefine_reg32_t  RMND0;                         /*  RMND0           */
+    union iodefine_reg32_t  RMND1;                         /*  RMND1           */
+    union iodefine_reg32_t  RMND2;                         /*  RMND2           */
+    
+    volatile uint8_t   dummy160[4];                            /*                  */
+#define RSCAN0_RFCC0_COUNT 8
+    union iodefine_reg32_t  RFCC0;                         /*  RFCC0           */
+    union iodefine_reg32_t  RFCC1;                         /*  RFCC1           */
+    union iodefine_reg32_t  RFCC2;                         /*  RFCC2           */
+    union iodefine_reg32_t  RFCC3;                         /*  RFCC3           */
+    union iodefine_reg32_t  RFCC4;                         /*  RFCC4           */
+    union iodefine_reg32_t  RFCC5;                         /*  RFCC5           */
+    union iodefine_reg32_t  RFCC6;                         /*  RFCC6           */
+    union iodefine_reg32_t  RFCC7;                         /*  RFCC7           */
+#define RSCAN0_RFSTS0_COUNT 8
+    union iodefine_reg32_t  RFSTS0;                        /*  RFSTS0          */
+    union iodefine_reg32_t  RFSTS1;                        /*  RFSTS1          */
+    union iodefine_reg32_t  RFSTS2;                        /*  RFSTS2          */
+    union iodefine_reg32_t  RFSTS3;                        /*  RFSTS3          */
+    union iodefine_reg32_t  RFSTS4;                        /*  RFSTS4          */
+    union iodefine_reg32_t  RFSTS5;                        /*  RFSTS5          */
+    union iodefine_reg32_t  RFSTS6;                        /*  RFSTS6          */
+    union iodefine_reg32_t  RFSTS7;                        /*  RFSTS7          */
+#define RSCAN0_RFPCTR0_COUNT 8
+    union iodefine_reg32_t  RFPCTR0;                       /*  RFPCTR0         */
+    union iodefine_reg32_t  RFPCTR1;                       /*  RFPCTR1         */
+    union iodefine_reg32_t  RFPCTR2;                       /*  RFPCTR2         */
+    union iodefine_reg32_t  RFPCTR3;                       /*  RFPCTR3         */
+    union iodefine_reg32_t  RFPCTR4;                       /*  RFPCTR4         */
+    union iodefine_reg32_t  RFPCTR5;                       /*  RFPCTR5         */
+    union iodefine_reg32_t  RFPCTR6;                       /*  RFPCTR6         */
+    union iodefine_reg32_t  RFPCTR7;                       /*  RFPCTR7         */
+#define RSCAN0_CFCC0_COUNT 15
+    union iodefine_reg32_t  CFCC0;                         /*  CFCC0           */
+    union iodefine_reg32_t  CFCC1;                         /*  CFCC1           */
+    union iodefine_reg32_t  CFCC2;                         /*  CFCC2           */
+    union iodefine_reg32_t  CFCC3;                         /*  CFCC3           */
+    union iodefine_reg32_t  CFCC4;                         /*  CFCC4           */
+    union iodefine_reg32_t  CFCC5;                         /*  CFCC5           */
+    union iodefine_reg32_t  CFCC6;                         /*  CFCC6           */
+    union iodefine_reg32_t  CFCC7;                         /*  CFCC7           */
+    union iodefine_reg32_t  CFCC8;                         /*  CFCC8           */
+    union iodefine_reg32_t  CFCC9;                         /*  CFCC9           */
+    union iodefine_reg32_t  CFCC10;                        /*  CFCC10          */
+    union iodefine_reg32_t  CFCC11;                        /*  CFCC11          */
+    union iodefine_reg32_t  CFCC12;                        /*  CFCC12          */
+    union iodefine_reg32_t  CFCC13;                        /*  CFCC13          */
+    union iodefine_reg32_t  CFCC14;                        /*  CFCC14          */
+    
+    volatile uint8_t   dummy161[36];                           /*                  */
+#define RSCAN0_CFSTS0_COUNT 15
+    union iodefine_reg32_t  CFSTS0;                        /*  CFSTS0          */
+    union iodefine_reg32_t  CFSTS1;                        /*  CFSTS1          */
+    union iodefine_reg32_t  CFSTS2;                        /*  CFSTS2          */
+    union iodefine_reg32_t  CFSTS3;                        /*  CFSTS3          */
+    union iodefine_reg32_t  CFSTS4;                        /*  CFSTS4          */
+    union iodefine_reg32_t  CFSTS5;                        /*  CFSTS5          */
+    union iodefine_reg32_t  CFSTS6;                        /*  CFSTS6          */
+    union iodefine_reg32_t  CFSTS7;                        /*  CFSTS7          */
+    union iodefine_reg32_t  CFSTS8;                        /*  CFSTS8          */
+    union iodefine_reg32_t  CFSTS9;                        /*  CFSTS9          */
+    union iodefine_reg32_t  CFSTS10;                       /*  CFSTS10         */
+    union iodefine_reg32_t  CFSTS11;                       /*  CFSTS11         */
+    union iodefine_reg32_t  CFSTS12;                       /*  CFSTS12         */
+    union iodefine_reg32_t  CFSTS13;                       /*  CFSTS13         */
+    union iodefine_reg32_t  CFSTS14;                       /*  CFSTS14         */
+    
+    volatile uint8_t   dummy162[36];                           /*                  */
+#define RSCAN0_CFPCTR0_COUNT 15
+    union iodefine_reg32_t  CFPCTR0;                       /*  CFPCTR0         */
+    union iodefine_reg32_t  CFPCTR1;                       /*  CFPCTR1         */
+    union iodefine_reg32_t  CFPCTR2;                       /*  CFPCTR2         */
+    union iodefine_reg32_t  CFPCTR3;                       /*  CFPCTR3         */
+    union iodefine_reg32_t  CFPCTR4;                       /*  CFPCTR4         */
+    union iodefine_reg32_t  CFPCTR5;                       /*  CFPCTR5         */
+    union iodefine_reg32_t  CFPCTR6;                       /*  CFPCTR6         */
+    union iodefine_reg32_t  CFPCTR7;                       /*  CFPCTR7         */
+    union iodefine_reg32_t  CFPCTR8;                       /*  CFPCTR8         */
+    union iodefine_reg32_t  CFPCTR9;                       /*  CFPCTR9         */
+    union iodefine_reg32_t  CFPCTR10;                      /*  CFPCTR10        */
+    union iodefine_reg32_t  CFPCTR11;                      /*  CFPCTR11        */
+    union iodefine_reg32_t  CFPCTR12;                      /*  CFPCTR12        */
+    union iodefine_reg32_t  CFPCTR13;                      /*  CFPCTR13        */
+    union iodefine_reg32_t  CFPCTR14;                      /*  CFPCTR14        */
+    
+    volatile uint8_t   dummy163[36];                           /*                  */
+    union iodefine_reg32_t  FESTS;                         /*  FESTS           */
+    union iodefine_reg32_t  FFSTS;                         /*  FFSTS           */
+    union iodefine_reg32_t  FMSTS;                         /*  FMSTS           */
+    union iodefine_reg32_t  RFISTS;                        /*  RFISTS          */
+    union iodefine_reg32_t  CFRISTS;                       /*  CFRISTS         */
+    union iodefine_reg32_t  CFTISTS;                       /*  CFTISTS         */
+    
+#define RSCAN0_TMC0_COUNT 80
+    volatile uint8_t   TMC0;                                   /*  TMC0            */
+    volatile uint8_t   TMC1;                                   /*  TMC1            */
+    volatile uint8_t   TMC2;                                   /*  TMC2            */
+    volatile uint8_t   TMC3;                                   /*  TMC3            */
+    volatile uint8_t   TMC4;                                   /*  TMC4            */
+    volatile uint8_t   TMC5;                                   /*  TMC5            */
+    volatile uint8_t   TMC6;                                   /*  TMC6            */
+    volatile uint8_t   TMC7;                                   /*  TMC7            */
+    volatile uint8_t   TMC8;                                   /*  TMC8            */
+    volatile uint8_t   TMC9;                                   /*  TMC9            */
+    volatile uint8_t   TMC10;                                  /*  TMC10           */
+    volatile uint8_t   TMC11;                                  /*  TMC11           */
+    volatile uint8_t   TMC12;                                  /*  TMC12           */
+    volatile uint8_t   TMC13;                                  /*  TMC13           */
+    volatile uint8_t   TMC14;                                  /*  TMC14           */
+    volatile uint8_t   TMC15;                                  /*  TMC15           */
+    volatile uint8_t   TMC16;                                  /*  TMC16           */
+    volatile uint8_t   TMC17;                                  /*  TMC17           */
+    volatile uint8_t   TMC18;                                  /*  TMC18           */
+    volatile uint8_t   TMC19;                                  /*  TMC19           */
+    volatile uint8_t   TMC20;                                  /*  TMC20           */
+    volatile uint8_t   TMC21;                                  /*  TMC21           */
+    volatile uint8_t   TMC22;                                  /*  TMC22           */
+    volatile uint8_t   TMC23;                                  /*  TMC23           */
+    volatile uint8_t   TMC24;                                  /*  TMC24           */
+    volatile uint8_t   TMC25;                                  /*  TMC25           */
+    volatile uint8_t   TMC26;                                  /*  TMC26           */
+    volatile uint8_t   TMC27;                                  /*  TMC27           */
+    volatile uint8_t   TMC28;                                  /*  TMC28           */
+    volatile uint8_t   TMC29;                                  /*  TMC29           */
+    volatile uint8_t   TMC30;                                  /*  TMC30           */
+    volatile uint8_t   TMC31;                                  /*  TMC31           */
+    volatile uint8_t   TMC32;                                  /*  TMC32           */
+    volatile uint8_t   TMC33;                                  /*  TMC33           */
+    volatile uint8_t   TMC34;                                  /*  TMC34           */
+    volatile uint8_t   TMC35;                                  /*  TMC35           */
+    volatile uint8_t   TMC36;                                  /*  TMC36           */
+    volatile uint8_t   TMC37;                                  /*  TMC37           */
+    volatile uint8_t   TMC38;                                  /*  TMC38           */
+    volatile uint8_t   TMC39;                                  /*  TMC39           */
+    volatile uint8_t   TMC40;                                  /*  TMC40           */
+    volatile uint8_t   TMC41;                                  /*  TMC41           */
+    volatile uint8_t   TMC42;                                  /*  TMC42           */
+    volatile uint8_t   TMC43;                                  /*  TMC43           */
+    volatile uint8_t   TMC44;                                  /*  TMC44           */
+    volatile uint8_t   TMC45;                                  /*  TMC45           */
+    volatile uint8_t   TMC46;                                  /*  TMC46           */
+    volatile uint8_t   TMC47;                                  /*  TMC47           */
+    volatile uint8_t   TMC48;                                  /*  TMC48           */
+    volatile uint8_t   TMC49;                                  /*  TMC49           */
+    volatile uint8_t   TMC50;                                  /*  TMC50           */
+    volatile uint8_t   TMC51;                                  /*  TMC51           */
+    volatile uint8_t   TMC52;                                  /*  TMC52           */
+    volatile uint8_t   TMC53;                                  /*  TMC53           */
+    volatile uint8_t   TMC54;                                  /*  TMC54           */
+    volatile uint8_t   TMC55;                                  /*  TMC55           */
+    volatile uint8_t   TMC56;                                  /*  TMC56           */
+    volatile uint8_t   TMC57;                                  /*  TMC57           */
+    volatile uint8_t   TMC58;                                  /*  TMC58           */
+    volatile uint8_t   TMC59;                                  /*  TMC59           */
+    volatile uint8_t   TMC60;                                  /*  TMC60           */
+    volatile uint8_t   TMC61;                                  /*  TMC61           */
+    volatile uint8_t   TMC62;                                  /*  TMC62           */
+    volatile uint8_t   TMC63;                                  /*  TMC63           */
+    volatile uint8_t   TMC64;                                  /*  TMC64           */
+    volatile uint8_t   TMC65;                                  /*  TMC65           */
+    volatile uint8_t   TMC66;                                  /*  TMC66           */
+    volatile uint8_t   TMC67;                                  /*  TMC67           */
+    volatile uint8_t   TMC68;                                  /*  TMC68           */
+    volatile uint8_t   TMC69;                                  /*  TMC69           */
+    volatile uint8_t   TMC70;                                  /*  TMC70           */
+    volatile uint8_t   TMC71;                                  /*  TMC71           */
+    volatile uint8_t   TMC72;                                  /*  TMC72           */
+    volatile uint8_t   TMC73;                                  /*  TMC73           */
+    volatile uint8_t   TMC74;                                  /*  TMC74           */
+    volatile uint8_t   TMC75;                                  /*  TMC75           */
+    volatile uint8_t   TMC76;                                  /*  TMC76           */
+    volatile uint8_t   TMC77;                                  /*  TMC77           */
+    volatile uint8_t   TMC78;                                  /*  TMC78           */
+    volatile uint8_t   TMC79;                                  /*  TMC79           */
+    volatile uint8_t   dummy164[48];                           /*                  */
+#define RSCAN0_TMSTS0_COUNT 80
+    volatile uint8_t   TMSTS0;                                 /*  TMSTS0          */
+    volatile uint8_t   TMSTS1;                                 /*  TMSTS1          */
+    volatile uint8_t   TMSTS2;                                 /*  TMSTS2          */
+    volatile uint8_t   TMSTS3;                                 /*  TMSTS3          */
+    volatile uint8_t   TMSTS4;                                 /*  TMSTS4          */
+    volatile uint8_t   TMSTS5;                                 /*  TMSTS5          */
+    volatile uint8_t   TMSTS6;                                 /*  TMSTS6          */
+    volatile uint8_t   TMSTS7;                                 /*  TMSTS7          */
+    volatile uint8_t   TMSTS8;                                 /*  TMSTS8          */
+    volatile uint8_t   TMSTS9;                                 /*  TMSTS9          */
+    volatile uint8_t   TMSTS10;                                /*  TMSTS10         */
+    volatile uint8_t   TMSTS11;                                /*  TMSTS11         */
+    volatile uint8_t   TMSTS12;                                /*  TMSTS12         */
+    volatile uint8_t   TMSTS13;                                /*  TMSTS13         */
+    volatile uint8_t   TMSTS14;                                /*  TMSTS14         */
+    volatile uint8_t   TMSTS15;                                /*  TMSTS15         */
+    volatile uint8_t   TMSTS16;                                /*  TMSTS16         */
+    volatile uint8_t   TMSTS17;                                /*  TMSTS17         */
+    volatile uint8_t   TMSTS18;                                /*  TMSTS18         */
+    volatile uint8_t   TMSTS19;                                /*  TMSTS19         */
+    volatile uint8_t   TMSTS20;                                /*  TMSTS20         */
+    volatile uint8_t   TMSTS21;                                /*  TMSTS21         */
+    volatile uint8_t   TMSTS22;                                /*  TMSTS22         */
+    volatile uint8_t   TMSTS23;                                /*  TMSTS23         */
+    volatile uint8_t   TMSTS24;                                /*  TMSTS24         */
+    volatile uint8_t   TMSTS25;                                /*  TMSTS25         */
+    volatile uint8_t   TMSTS26;                                /*  TMSTS26         */
+    volatile uint8_t   TMSTS27;                                /*  TMSTS27         */
+    volatile uint8_t   TMSTS28;                                /*  TMSTS28         */
+    volatile uint8_t   TMSTS29;                                /*  TMSTS29         */
+    volatile uint8_t   TMSTS30;                                /*  TMSTS30         */
+    volatile uint8_t   TMSTS31;                                /*  TMSTS31         */
+    volatile uint8_t   TMSTS32;                                /*  TMSTS32         */
+    volatile uint8_t   TMSTS33;                                /*  TMSTS33         */
+    volatile uint8_t   TMSTS34;                                /*  TMSTS34         */
+    volatile uint8_t   TMSTS35;                                /*  TMSTS35         */
+    volatile uint8_t   TMSTS36;                                /*  TMSTS36         */
+    volatile uint8_t   TMSTS37;                                /*  TMSTS37         */
+    volatile uint8_t   TMSTS38;                                /*  TMSTS38         */
+    volatile uint8_t   TMSTS39;                                /*  TMSTS39         */
+    volatile uint8_t   TMSTS40;                                /*  TMSTS40         */
+    volatile uint8_t   TMSTS41;                                /*  TMSTS41         */
+    volatile uint8_t   TMSTS42;                                /*  TMSTS42         */
+    volatile uint8_t   TMSTS43;                                /*  TMSTS43         */
+    volatile uint8_t   TMSTS44;                                /*  TMSTS44         */
+    volatile uint8_t   TMSTS45;                                /*  TMSTS45         */
+    volatile uint8_t   TMSTS46;                                /*  TMSTS46         */
+    volatile uint8_t   TMSTS47;                                /*  TMSTS47         */
+    volatile uint8_t   TMSTS48;                                /*  TMSTS48         */
+    volatile uint8_t   TMSTS49;                                /*  TMSTS49         */
+    volatile uint8_t   TMSTS50;                                /*  TMSTS50         */
+    volatile uint8_t   TMSTS51;                                /*  TMSTS51         */
+    volatile uint8_t   TMSTS52;                                /*  TMSTS52         */
+    volatile uint8_t   TMSTS53;                                /*  TMSTS53         */
+    volatile uint8_t   TMSTS54;                                /*  TMSTS54         */
+    volatile uint8_t   TMSTS55;                                /*  TMSTS55         */
+    volatile uint8_t   TMSTS56;                                /*  TMSTS56         */
+    volatile uint8_t   TMSTS57;                                /*  TMSTS57         */
+    volatile uint8_t   TMSTS58;                                /*  TMSTS58         */
+    volatile uint8_t   TMSTS59;                                /*  TMSTS59         */
+    volatile uint8_t   TMSTS60;                                /*  TMSTS60         */
+    volatile uint8_t   TMSTS61;                                /*  TMSTS61         */
+    volatile uint8_t   TMSTS62;                                /*  TMSTS62         */
+    volatile uint8_t   TMSTS63;                                /*  TMSTS63         */
+    volatile uint8_t   TMSTS64;                                /*  TMSTS64         */
+    volatile uint8_t   TMSTS65;                                /*  TMSTS65         */
+    volatile uint8_t   TMSTS66;                                /*  TMSTS66         */
+    volatile uint8_t   TMSTS67;                                /*  TMSTS67         */
+    volatile uint8_t   TMSTS68;                                /*  TMSTS68         */
+    volatile uint8_t   TMSTS69;                                /*  TMSTS69         */
+    volatile uint8_t   TMSTS70;                                /*  TMSTS70         */
+    volatile uint8_t   TMSTS71;                                /*  TMSTS71         */
+    volatile uint8_t   TMSTS72;                                /*  TMSTS72         */
+    volatile uint8_t   TMSTS73;                                /*  TMSTS73         */
+    volatile uint8_t   TMSTS74;                                /*  TMSTS74         */
+    volatile uint8_t   TMSTS75;                                /*  TMSTS75         */
+    volatile uint8_t   TMSTS76;                                /*  TMSTS76         */
+    volatile uint8_t   TMSTS77;                                /*  TMSTS77         */
+    volatile uint8_t   TMSTS78;                                /*  TMSTS78         */
+    volatile uint8_t   TMSTS79;                                /*  TMSTS79         */
+    volatile uint8_t   dummy165[48];                           /*                  */
+#define RSCAN0_TMTRSTS0_COUNT 3
+    union iodefine_reg32_t  TMTRSTS0;                      /*  TMTRSTS0        */
+    union iodefine_reg32_t  TMTRSTS1;                      /*  TMTRSTS1        */
+    union iodefine_reg32_t  TMTRSTS2;                      /*  TMTRSTS2        */
+    
+    volatile uint8_t   dummy166[4];                            /*                  */
+#define RSCAN0_TMTARSTS0_COUNT 3
+    union iodefine_reg32_t  TMTARSTS0;                     /*  TMTARSTS0       */
+    union iodefine_reg32_t  TMTARSTS1;                     /*  TMTARSTS1       */
+    union iodefine_reg32_t  TMTARSTS2;                     /*  TMTARSTS2       */
+    
+    volatile uint8_t   dummy167[4];                            /*                  */
+#define RSCAN0_TMTCSTS0_COUNT 3
+    union iodefine_reg32_t  TMTCSTS0;                      /*  TMTCSTS0        */
+    union iodefine_reg32_t  TMTCSTS1;                      /*  TMTCSTS1        */
+    union iodefine_reg32_t  TMTCSTS2;                      /*  TMTCSTS2        */
+    
+    volatile uint8_t   dummy168[4];                            /*                  */
+#define RSCAN0_TMTASTS0_COUNT 3
+    union iodefine_reg32_t  TMTASTS0;                      /*  TMTASTS0        */
+    union iodefine_reg32_t  TMTASTS1;                      /*  TMTASTS1        */
+    union iodefine_reg32_t  TMTASTS2;                      /*  TMTASTS2        */
+    
+    volatile uint8_t   dummy169[4];                            /*                  */
+#define RSCAN0_TMIEC0_COUNT 3
+    union iodefine_reg32_t  TMIEC0;                        /*  TMIEC0          */
+    union iodefine_reg32_t  TMIEC1;                        /*  TMIEC1          */
+    union iodefine_reg32_t  TMIEC2;                        /*  TMIEC2          */
+    
+    volatile uint8_t   dummy170[4];                            /*                  */
+#define RSCAN0_TXQCC0_COUNT 5
+    union iodefine_reg32_t  TXQCC0;                        /*  TXQCC0          */
+    union iodefine_reg32_t  TXQCC1;                        /*  TXQCC1          */
+    union iodefine_reg32_t  TXQCC2;                        /*  TXQCC2          */
+    union iodefine_reg32_t  TXQCC3;                        /*  TXQCC3          */
+    union iodefine_reg32_t  TXQCC4;                        /*  TXQCC4          */
+    
+    volatile uint8_t   dummy171[12];                           /*                  */
+#define RSCAN0_TXQSTS0_COUNT 5
+    union iodefine_reg32_t  TXQSTS0;                       /*  TXQSTS0         */
+    union iodefine_reg32_t  TXQSTS1;                       /*  TXQSTS1         */
+    union iodefine_reg32_t  TXQSTS2;                       /*  TXQSTS2         */
+    union iodefine_reg32_t  TXQSTS3;                       /*  TXQSTS3         */
+    union iodefine_reg32_t  TXQSTS4;                       /*  TXQSTS4         */
+    
+    volatile uint8_t   dummy172[12];                           /*                  */
+#define RSCAN0_TXQPCTR0_COUNT 5
+    union iodefine_reg32_t  TXQPCTR0;                      /*  TXQPCTR0        */
+    union iodefine_reg32_t  TXQPCTR1;                      /*  TXQPCTR1        */
+    union iodefine_reg32_t  TXQPCTR2;                      /*  TXQPCTR2        */
+    union iodefine_reg32_t  TXQPCTR3;                      /*  TXQPCTR3        */
+    union iodefine_reg32_t  TXQPCTR4;                      /*  TXQPCTR4        */
+    
+    volatile uint8_t   dummy173[12];                           /*                  */
+#define RSCAN0_THLCC0_COUNT 5
+    union iodefine_reg32_t  THLCC0;                        /*  THLCC0          */
+    union iodefine_reg32_t  THLCC1;                        /*  THLCC1          */
+    union iodefine_reg32_t  THLCC2;                        /*  THLCC2          */
+    union iodefine_reg32_t  THLCC3;                        /*  THLCC3          */
+    union iodefine_reg32_t  THLCC4;                        /*  THLCC4          */
+    
+    volatile uint8_t   dummy174[12];                           /*                  */
+#define RSCAN0_THLSTS0_COUNT 5
+    union iodefine_reg32_t  THLSTS0;                       /*  THLSTS0         */
+    union iodefine_reg32_t  THLSTS1;                       /*  THLSTS1         */
+    union iodefine_reg32_t  THLSTS2;                       /*  THLSTS2         */
+    union iodefine_reg32_t  THLSTS3;                       /*  THLSTS3         */
+    union iodefine_reg32_t  THLSTS4;                       /*  THLSTS4         */
+    
+    volatile uint8_t   dummy175[12];                           /*                  */
+#define RSCAN0_THLPCTR0_COUNT 5
+    union iodefine_reg32_t  THLPCTR0;                      /*  THLPCTR0        */
+    union iodefine_reg32_t  THLPCTR1;                      /*  THLPCTR1        */
+    union iodefine_reg32_t  THLPCTR2;                      /*  THLPCTR2        */
+    union iodefine_reg32_t  THLPCTR3;                      /*  THLPCTR3        */
+    union iodefine_reg32_t  THLPCTR4;                      /*  THLPCTR4        */
+    
+    volatile uint8_t   dummy176[12];                           /*                  */
+#define RSCAN0_GTINTSTS0_COUNT 2
+    union iodefine_reg32_t  GTINTSTS0;                     /*  GTINTSTS0       */
+    union iodefine_reg32_t  GTINTSTS1;                     /*  GTINTSTS1       */
+    union iodefine_reg32_t  GTSTCFG;                       /*  GTSTCFG         */
+    union iodefine_reg32_t  GTSTCTR;                       /*  GTSTCTR         */
+    
+    volatile uint8_t   dummy177[12];                           /*                  */
+    union iodefine_reg32_16_t  GLOCKK;                     /*  GLOCKK          */
+    
+    volatile uint8_t   dummy178[128];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID0;                       /*  GAFLID0         */
+    union iodefine_reg32_t  GAFLM0;                        /*  GAFLM0          */
+    union iodefine_reg32_t  GAFLP00;                       /*  GAFLP00         */
+    union iodefine_reg32_t  GAFLP10;                       /*  GAFLP10         */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID1;                       /*  GAFLID1         */
+    union iodefine_reg32_t  GAFLM1;                        /*  GAFLM1          */
+    union iodefine_reg32_t  GAFLP01;                       /*  GAFLP01         */
+    union iodefine_reg32_t  GAFLP11;                       /*  GAFLP11         */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID2;                       /*  GAFLID2         */
+    union iodefine_reg32_t  GAFLM2;                        /*  GAFLM2          */
+    union iodefine_reg32_t  GAFLP02;                       /*  GAFLP02         */
+    union iodefine_reg32_t  GAFLP12;                       /*  GAFLP12         */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID3;                       /*  GAFLID3         */
+    union iodefine_reg32_t  GAFLM3;                        /*  GAFLM3          */
+    union iodefine_reg32_t  GAFLP03;                       /*  GAFLP03         */
+    union iodefine_reg32_t  GAFLP13;                       /*  GAFLP13         */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID4;                       /*  GAFLID4         */
+    union iodefine_reg32_t  GAFLM4;                        /*  GAFLM4          */
+    union iodefine_reg32_t  GAFLP04;                       /*  GAFLP04         */
+    union iodefine_reg32_t  GAFLP14;                       /*  GAFLP14         */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID5;                       /*  GAFLID5         */
+    union iodefine_reg32_t  GAFLM5;                        /*  GAFLM5          */
+    union iodefine_reg32_t  GAFLP05;                       /*  GAFLP05         */
+    union iodefine_reg32_t  GAFLP15;                       /*  GAFLP15         */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID6;                       /*  GAFLID6         */
+    union iodefine_reg32_t  GAFLM6;                        /*  GAFLM6          */
+    union iodefine_reg32_t  GAFLP06;                       /*  GAFLP06         */
+    union iodefine_reg32_t  GAFLP16;                       /*  GAFLP16         */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID7;                       /*  GAFLID7         */
+    union iodefine_reg32_t  GAFLM7;                        /*  GAFLM7          */
+    union iodefine_reg32_t  GAFLP07;                       /*  GAFLP07         */
+    union iodefine_reg32_t  GAFLP17;                       /*  GAFLP17         */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID8;                       /*  GAFLID8         */
+    union iodefine_reg32_t  GAFLM8;                        /*  GAFLM8          */
+    union iodefine_reg32_t  GAFLP08;                       /*  GAFLP08         */
+    union iodefine_reg32_t  GAFLP18;                       /*  GAFLP18         */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID9;                       /*  GAFLID9         */
+    union iodefine_reg32_t  GAFLM9;                        /*  GAFLM9          */
+    union iodefine_reg32_t  GAFLP09;                       /*  GAFLP09         */
+    union iodefine_reg32_t  GAFLP19;                       /*  GAFLP19         */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID10;                      /*  GAFLID10        */
+    union iodefine_reg32_t  GAFLM10;                       /*  GAFLM10         */
+    union iodefine_reg32_t  GAFLP010;                      /*  GAFLP010        */
+    union iodefine_reg32_t  GAFLP110;                      /*  GAFLP110        */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID11;                      /*  GAFLID11        */
+    union iodefine_reg32_t  GAFLM11;                       /*  GAFLM11         */
+    union iodefine_reg32_t  GAFLP011;                      /*  GAFLP011        */
+    union iodefine_reg32_t  GAFLP111;                      /*  GAFLP111        */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID12;                      /*  GAFLID12        */
+    union iodefine_reg32_t  GAFLM12;                       /*  GAFLM12         */
+    union iodefine_reg32_t  GAFLP012;                      /*  GAFLP012        */
+    union iodefine_reg32_t  GAFLP112;                      /*  GAFLP112        */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID13;                      /*  GAFLID13        */
+    union iodefine_reg32_t  GAFLM13;                       /*  GAFLM13         */
+    union iodefine_reg32_t  GAFLP013;                      /*  GAFLP013        */
+    union iodefine_reg32_t  GAFLP113;                      /*  GAFLP113        */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID14;                      /*  GAFLID14        */
+    union iodefine_reg32_t  GAFLM14;                       /*  GAFLM14         */
+    union iodefine_reg32_t  GAFLP014;                      /*  GAFLP014        */
+    union iodefine_reg32_t  GAFLP114;                      /*  GAFLP114        */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID15;                      /*  GAFLID15        */
+    union iodefine_reg32_t  GAFLM15;                       /*  GAFLM15         */
+    union iodefine_reg32_t  GAFLP015;                      /*  GAFLP015        */
+    union iodefine_reg32_t  GAFLP115;                      /*  GAFLP115        */
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID0;                         /*  RMID0           */
+    union iodefine_reg32_t  RMPTR0;                        /*  RMPTR0          */
+    union iodefine_reg32_t  RMDF00;                        /*  RMDF00          */
+    union iodefine_reg32_t  RMDF10;                        /*  RMDF10          */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID1;                         /*  RMID1           */
+    union iodefine_reg32_t  RMPTR1;                        /*  RMPTR1          */
+    union iodefine_reg32_t  RMDF01;                        /*  RMDF01          */
+    union iodefine_reg32_t  RMDF11;                        /*  RMDF11          */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID2;                         /*  RMID2           */
+    union iodefine_reg32_t  RMPTR2;                        /*  RMPTR2          */
+    union iodefine_reg32_t  RMDF02;                        /*  RMDF02          */
+    union iodefine_reg32_t  RMDF12;                        /*  RMDF12          */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID3;                         /*  RMID3           */
+    union iodefine_reg32_t  RMPTR3;                        /*  RMPTR3          */
+    union iodefine_reg32_t  RMDF03;                        /*  RMDF03          */
+    union iodefine_reg32_t  RMDF13;                        /*  RMDF13          */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID4;                         /*  RMID4           */
+    union iodefine_reg32_t  RMPTR4;                        /*  RMPTR4          */
+    union iodefine_reg32_t  RMDF04;                        /*  RMDF04          */
+    union iodefine_reg32_t  RMDF14;                        /*  RMDF14          */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID5;                         /*  RMID5           */
+    union iodefine_reg32_t  RMPTR5;                        /*  RMPTR5          */
+    union iodefine_reg32_t  RMDF05;                        /*  RMDF05          */
+    union iodefine_reg32_t  RMDF15;                        /*  RMDF15          */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID6;                         /*  RMID6           */
+    union iodefine_reg32_t  RMPTR6;                        /*  RMPTR6          */
+    union iodefine_reg32_t  RMDF06;                        /*  RMDF06          */
+    union iodefine_reg32_t  RMDF16;                        /*  RMDF16          */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID7;                         /*  RMID7           */
+    union iodefine_reg32_t  RMPTR7;                        /*  RMPTR7          */
+    union iodefine_reg32_t  RMDF07;                        /*  RMDF07          */
+    union iodefine_reg32_t  RMDF17;                        /*  RMDF17          */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID8;                         /*  RMID8           */
+    union iodefine_reg32_t  RMPTR8;                        /*  RMPTR8          */
+    union iodefine_reg32_t  RMDF08;                        /*  RMDF08          */
+    union iodefine_reg32_t  RMDF18;                        /*  RMDF18          */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID9;                         /*  RMID9           */
+    union iodefine_reg32_t  RMPTR9;                        /*  RMPTR9          */
+    union iodefine_reg32_t  RMDF09;                        /*  RMDF09          */
+    union iodefine_reg32_t  RMDF19;                        /*  RMDF19          */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID10;                        /*  RMID10          */
+    union iodefine_reg32_t  RMPTR10;                       /*  RMPTR10         */
+    union iodefine_reg32_t  RMDF010;                       /*  RMDF010         */
+    union iodefine_reg32_t  RMDF110;                       /*  RMDF110         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID11;                        /*  RMID11          */
+    union iodefine_reg32_t  RMPTR11;                       /*  RMPTR11         */
+    union iodefine_reg32_t  RMDF011;                       /*  RMDF011         */
+    union iodefine_reg32_t  RMDF111;                       /*  RMDF111         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID12;                        /*  RMID12          */
+    union iodefine_reg32_t  RMPTR12;                       /*  RMPTR12         */
+    union iodefine_reg32_t  RMDF012;                       /*  RMDF012         */
+    union iodefine_reg32_t  RMDF112;                       /*  RMDF112         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID13;                        /*  RMID13          */
+    union iodefine_reg32_t  RMPTR13;                       /*  RMPTR13         */
+    union iodefine_reg32_t  RMDF013;                       /*  RMDF013         */
+    union iodefine_reg32_t  RMDF113;                       /*  RMDF113         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID14;                        /*  RMID14          */
+    union iodefine_reg32_t  RMPTR14;                       /*  RMPTR14         */
+    union iodefine_reg32_t  RMDF014;                       /*  RMDF014         */
+    union iodefine_reg32_t  RMDF114;                       /*  RMDF114         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID15;                        /*  RMID15          */
+    union iodefine_reg32_t  RMPTR15;                       /*  RMPTR15         */
+    union iodefine_reg32_t  RMDF015;                       /*  RMDF015         */
+    union iodefine_reg32_t  RMDF115;                       /*  RMDF115         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID16;                        /*  RMID16          */
+    union iodefine_reg32_t  RMPTR16;                       /*  RMPTR16         */
+    union iodefine_reg32_t  RMDF016;                       /*  RMDF016         */
+    union iodefine_reg32_t  RMDF116;                       /*  RMDF116         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID17;                        /*  RMID17          */
+    union iodefine_reg32_t  RMPTR17;                       /*  RMPTR17         */
+    union iodefine_reg32_t  RMDF017;                       /*  RMDF017         */
+    union iodefine_reg32_t  RMDF117;                       /*  RMDF117         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID18;                        /*  RMID18          */
+    union iodefine_reg32_t  RMPTR18;                       /*  RMPTR18         */
+    union iodefine_reg32_t  RMDF018;                       /*  RMDF018         */
+    union iodefine_reg32_t  RMDF118;                       /*  RMDF118         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID19;                        /*  RMID19          */
+    union iodefine_reg32_t  RMPTR19;                       /*  RMPTR19         */
+    union iodefine_reg32_t  RMDF019;                       /*  RMDF019         */
+    union iodefine_reg32_t  RMDF119;                       /*  RMDF119         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID20;                        /*  RMID20          */
+    union iodefine_reg32_t  RMPTR20;                       /*  RMPTR20         */
+    union iodefine_reg32_t  RMDF020;                       /*  RMDF020         */
+    union iodefine_reg32_t  RMDF120;                       /*  RMDF120         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID21;                        /*  RMID21          */
+    union iodefine_reg32_t  RMPTR21;                       /*  RMPTR21         */
+    union iodefine_reg32_t  RMDF021;                       /*  RMDF021         */
+    union iodefine_reg32_t  RMDF121;                       /*  RMDF121         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID22;                        /*  RMID22          */
+    union iodefine_reg32_t  RMPTR22;                       /*  RMPTR22         */
+    union iodefine_reg32_t  RMDF022;                       /*  RMDF022         */
+    union iodefine_reg32_t  RMDF122;                       /*  RMDF122         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID23;                        /*  RMID23          */
+    union iodefine_reg32_t  RMPTR23;                       /*  RMPTR23         */
+    union iodefine_reg32_t  RMDF023;                       /*  RMDF023         */
+    union iodefine_reg32_t  RMDF123;                       /*  RMDF123         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID24;                        /*  RMID24          */
+    union iodefine_reg32_t  RMPTR24;                       /*  RMPTR24         */
+    union iodefine_reg32_t  RMDF024;                       /*  RMDF024         */
+    union iodefine_reg32_t  RMDF124;                       /*  RMDF124         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID25;                        /*  RMID25          */
+    union iodefine_reg32_t  RMPTR25;                       /*  RMPTR25         */
+    union iodefine_reg32_t  RMDF025;                       /*  RMDF025         */
+    union iodefine_reg32_t  RMDF125;                       /*  RMDF125         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID26;                        /*  RMID26          */
+    union iodefine_reg32_t  RMPTR26;                       /*  RMPTR26         */
+    union iodefine_reg32_t  RMDF026;                       /*  RMDF026         */
+    union iodefine_reg32_t  RMDF126;                       /*  RMDF126         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID27;                        /*  RMID27          */
+    union iodefine_reg32_t  RMPTR27;                       /*  RMPTR27         */
+    union iodefine_reg32_t  RMDF027;                       /*  RMDF027         */
+    union iodefine_reg32_t  RMDF127;                       /*  RMDF127         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID28;                        /*  RMID28          */
+    union iodefine_reg32_t  RMPTR28;                       /*  RMPTR28         */
+    union iodefine_reg32_t  RMDF028;                       /*  RMDF028         */
+    union iodefine_reg32_t  RMDF128;                       /*  RMDF128         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID29;                        /*  RMID29          */
+    union iodefine_reg32_t  RMPTR29;                       /*  RMPTR29         */
+    union iodefine_reg32_t  RMDF029;                       /*  RMDF029         */
+    union iodefine_reg32_t  RMDF129;                       /*  RMDF129         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID30;                        /*  RMID30          */
+    union iodefine_reg32_t  RMPTR30;                       /*  RMPTR30         */
+    union iodefine_reg32_t  RMDF030;                       /*  RMDF030         */
+    union iodefine_reg32_t  RMDF130;                       /*  RMDF130         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID31;                        /*  RMID31          */
+    union iodefine_reg32_t  RMPTR31;                       /*  RMPTR31         */
+    union iodefine_reg32_t  RMDF031;                       /*  RMDF031         */
+    union iodefine_reg32_t  RMDF131;                       /*  RMDF131         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID32;                        /*  RMID32          */
+    union iodefine_reg32_t  RMPTR32;                       /*  RMPTR32         */
+    union iodefine_reg32_t  RMDF032;                       /*  RMDF032         */
+    union iodefine_reg32_t  RMDF132;                       /*  RMDF132         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID33;                        /*  RMID33          */
+    union iodefine_reg32_t  RMPTR33;                       /*  RMPTR33         */
+    union iodefine_reg32_t  RMDF033;                       /*  RMDF033         */
+    union iodefine_reg32_t  RMDF133;                       /*  RMDF133         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID34;                        /*  RMID34          */
+    union iodefine_reg32_t  RMPTR34;                       /*  RMPTR34         */
+    union iodefine_reg32_t  RMDF034;                       /*  RMDF034         */
+    union iodefine_reg32_t  RMDF134;                       /*  RMDF134         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID35;                        /*  RMID35          */
+    union iodefine_reg32_t  RMPTR35;                       /*  RMPTR35         */
+    union iodefine_reg32_t  RMDF035;                       /*  RMDF035         */
+    union iodefine_reg32_t  RMDF135;                       /*  RMDF135         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID36;                        /*  RMID36          */
+    union iodefine_reg32_t  RMPTR36;                       /*  RMPTR36         */
+    union iodefine_reg32_t  RMDF036;                       /*  RMDF036         */
+    union iodefine_reg32_t  RMDF136;                       /*  RMDF136         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID37;                        /*  RMID37          */
+    union iodefine_reg32_t  RMPTR37;                       /*  RMPTR37         */
+    union iodefine_reg32_t  RMDF037;                       /*  RMDF037         */
+    union iodefine_reg32_t  RMDF137;                       /*  RMDF137         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID38;                        /*  RMID38          */
+    union iodefine_reg32_t  RMPTR38;                       /*  RMPTR38         */
+    union iodefine_reg32_t  RMDF038;                       /*  RMDF038         */
+    union iodefine_reg32_t  RMDF138;                       /*  RMDF138         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID39;                        /*  RMID39          */
+    union iodefine_reg32_t  RMPTR39;                       /*  RMPTR39         */
+    union iodefine_reg32_t  RMDF039;                       /*  RMDF039         */
+    union iodefine_reg32_t  RMDF139;                       /*  RMDF139         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID40;                        /*  RMID40          */
+    union iodefine_reg32_t  RMPTR40;                       /*  RMPTR40         */
+    union iodefine_reg32_t  RMDF040;                       /*  RMDF040         */
+    union iodefine_reg32_t  RMDF140;                       /*  RMDF140         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID41;                        /*  RMID41          */
+    union iodefine_reg32_t  RMPTR41;                       /*  RMPTR41         */
+    union iodefine_reg32_t  RMDF041;                       /*  RMDF041         */
+    union iodefine_reg32_t  RMDF141;                       /*  RMDF141         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID42;                        /*  RMID42          */
+    union iodefine_reg32_t  RMPTR42;                       /*  RMPTR42         */
+    union iodefine_reg32_t  RMDF042;                       /*  RMDF042         */
+    union iodefine_reg32_t  RMDF142;                       /*  RMDF142         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID43;                        /*  RMID43          */
+    union iodefine_reg32_t  RMPTR43;                       /*  RMPTR43         */
+    union iodefine_reg32_t  RMDF043;                       /*  RMDF043         */
+    union iodefine_reg32_t  RMDF143;                       /*  RMDF143         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID44;                        /*  RMID44          */
+    union iodefine_reg32_t  RMPTR44;                       /*  RMPTR44         */
+    union iodefine_reg32_t  RMDF044;                       /*  RMDF044         */
+    union iodefine_reg32_t  RMDF144;                       /*  RMDF144         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID45;                        /*  RMID45          */
+    union iodefine_reg32_t  RMPTR45;                       /*  RMPTR45         */
+    union iodefine_reg32_t  RMDF045;                       /*  RMDF045         */
+    union iodefine_reg32_t  RMDF145;                       /*  RMDF145         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID46;                        /*  RMID46          */
+    union iodefine_reg32_t  RMPTR46;                       /*  RMPTR46         */
+    union iodefine_reg32_t  RMDF046;                       /*  RMDF046         */
+    union iodefine_reg32_t  RMDF146;                       /*  RMDF146         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID47;                        /*  RMID47          */
+    union iodefine_reg32_t  RMPTR47;                       /*  RMPTR47         */
+    union iodefine_reg32_t  RMDF047;                       /*  RMDF047         */
+    union iodefine_reg32_t  RMDF147;                       /*  RMDF147         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID48;                        /*  RMID48          */
+    union iodefine_reg32_t  RMPTR48;                       /*  RMPTR48         */
+    union iodefine_reg32_t  RMDF048;                       /*  RMDF048         */
+    union iodefine_reg32_t  RMDF148;                       /*  RMDF148         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID49;                        /*  RMID49          */
+    union iodefine_reg32_t  RMPTR49;                       /*  RMPTR49         */
+    union iodefine_reg32_t  RMDF049;                       /*  RMDF049         */
+    union iodefine_reg32_t  RMDF149;                       /*  RMDF149         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID50;                        /*  RMID50          */
+    union iodefine_reg32_t  RMPTR50;                       /*  RMPTR50         */
+    union iodefine_reg32_t  RMDF050;                       /*  RMDF050         */
+    union iodefine_reg32_t  RMDF150;                       /*  RMDF150         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID51;                        /*  RMID51          */
+    union iodefine_reg32_t  RMPTR51;                       /*  RMPTR51         */
+    union iodefine_reg32_t  RMDF051;                       /*  RMDF051         */
+    union iodefine_reg32_t  RMDF151;                       /*  RMDF151         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID52;                        /*  RMID52          */
+    union iodefine_reg32_t  RMPTR52;                       /*  RMPTR52         */
+    union iodefine_reg32_t  RMDF052;                       /*  RMDF052         */
+    union iodefine_reg32_t  RMDF152;                       /*  RMDF152         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID53;                        /*  RMID53          */
+    union iodefine_reg32_t  RMPTR53;                       /*  RMPTR53         */
+    union iodefine_reg32_t  RMDF053;                       /*  RMDF053         */
+    union iodefine_reg32_t  RMDF153;                       /*  RMDF153         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID54;                        /*  RMID54          */
+    union iodefine_reg32_t  RMPTR54;                       /*  RMPTR54         */
+    union iodefine_reg32_t  RMDF054;                       /*  RMDF054         */
+    union iodefine_reg32_t  RMDF154;                       /*  RMDF154         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID55;                        /*  RMID55          */
+    union iodefine_reg32_t  RMPTR55;                       /*  RMPTR55         */
+    union iodefine_reg32_t  RMDF055;                       /*  RMDF055         */
+    union iodefine_reg32_t  RMDF155;                       /*  RMDF155         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID56;                        /*  RMID56          */
+    union iodefine_reg32_t  RMPTR56;                       /*  RMPTR56         */
+    union iodefine_reg32_t  RMDF056;                       /*  RMDF056         */
+    union iodefine_reg32_t  RMDF156;                       /*  RMDF156         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID57;                        /*  RMID57          */
+    union iodefine_reg32_t  RMPTR57;                       /*  RMPTR57         */
+    union iodefine_reg32_t  RMDF057;                       /*  RMDF057         */
+    union iodefine_reg32_t  RMDF157;                       /*  RMDF157         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID58;                        /*  RMID58          */
+    union iodefine_reg32_t  RMPTR58;                       /*  RMPTR58         */
+    union iodefine_reg32_t  RMDF058;                       /*  RMDF058         */
+    union iodefine_reg32_t  RMDF158;                       /*  RMDF158         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID59;                        /*  RMID59          */
+    union iodefine_reg32_t  RMPTR59;                       /*  RMPTR59         */
+    union iodefine_reg32_t  RMDF059;                       /*  RMDF059         */
+    union iodefine_reg32_t  RMDF159;                       /*  RMDF159         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID60;                        /*  RMID60          */
+    union iodefine_reg32_t  RMPTR60;                       /*  RMPTR60         */
+    union iodefine_reg32_t  RMDF060;                       /*  RMDF060         */
+    union iodefine_reg32_t  RMDF160;                       /*  RMDF160         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID61;                        /*  RMID61          */
+    union iodefine_reg32_t  RMPTR61;                       /*  RMPTR61         */
+    union iodefine_reg32_t  RMDF061;                       /*  RMDF061         */
+    union iodefine_reg32_t  RMDF161;                       /*  RMDF161         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID62;                        /*  RMID62          */
+    union iodefine_reg32_t  RMPTR62;                       /*  RMPTR62         */
+    union iodefine_reg32_t  RMDF062;                       /*  RMDF062         */
+    union iodefine_reg32_t  RMDF162;                       /*  RMDF162         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID63;                        /*  RMID63          */
+    union iodefine_reg32_t  RMPTR63;                       /*  RMPTR63         */
+    union iodefine_reg32_t  RMDF063;                       /*  RMDF063         */
+    union iodefine_reg32_t  RMDF163;                       /*  RMDF163         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID64;                        /*  RMID64          */
+    union iodefine_reg32_t  RMPTR64;                       /*  RMPTR64         */
+    union iodefine_reg32_t  RMDF064;                       /*  RMDF064         */
+    union iodefine_reg32_t  RMDF164;                       /*  RMDF164         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID65;                        /*  RMID65          */
+    union iodefine_reg32_t  RMPTR65;                       /*  RMPTR65         */
+    union iodefine_reg32_t  RMDF065;                       /*  RMDF065         */
+    union iodefine_reg32_t  RMDF165;                       /*  RMDF165         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID66;                        /*  RMID66          */
+    union iodefine_reg32_t  RMPTR66;                       /*  RMPTR66         */
+    union iodefine_reg32_t  RMDF066;                       /*  RMDF066         */
+    union iodefine_reg32_t  RMDF166;                       /*  RMDF166         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID67;                        /*  RMID67          */
+    union iodefine_reg32_t  RMPTR67;                       /*  RMPTR67         */
+    union iodefine_reg32_t  RMDF067;                       /*  RMDF067         */
+    union iodefine_reg32_t  RMDF167;                       /*  RMDF167         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID68;                        /*  RMID68          */
+    union iodefine_reg32_t  RMPTR68;                       /*  RMPTR68         */
+    union iodefine_reg32_t  RMDF068;                       /*  RMDF068         */
+    union iodefine_reg32_t  RMDF168;                       /*  RMDF168         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID69;                        /*  RMID69          */
+    union iodefine_reg32_t  RMPTR69;                       /*  RMPTR69         */
+    union iodefine_reg32_t  RMDF069;                       /*  RMDF069         */
+    union iodefine_reg32_t  RMDF169;                       /*  RMDF169         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID70;                        /*  RMID70          */
+    union iodefine_reg32_t  RMPTR70;                       /*  RMPTR70         */
+    union iodefine_reg32_t  RMDF070;                       /*  RMDF070         */
+    union iodefine_reg32_t  RMDF170;                       /*  RMDF170         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID71;                        /*  RMID71          */
+    union iodefine_reg32_t  RMPTR71;                       /*  RMPTR71         */
+    union iodefine_reg32_t  RMDF071;                       /*  RMDF071         */
+    union iodefine_reg32_t  RMDF171;                       /*  RMDF171         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID72;                        /*  RMID72          */
+    union iodefine_reg32_t  RMPTR72;                       /*  RMPTR72         */
+    union iodefine_reg32_t  RMDF072;                       /*  RMDF072         */
+    union iodefine_reg32_t  RMDF172;                       /*  RMDF172         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID73;                        /*  RMID73          */
+    union iodefine_reg32_t  RMPTR73;                       /*  RMPTR73         */
+    union iodefine_reg32_t  RMDF073;                       /*  RMDF073         */
+    union iodefine_reg32_t  RMDF173;                       /*  RMDF173         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID74;                        /*  RMID74          */
+    union iodefine_reg32_t  RMPTR74;                       /*  RMPTR74         */
+    union iodefine_reg32_t  RMDF074;                       /*  RMDF074         */
+    union iodefine_reg32_t  RMDF174;                       /*  RMDF174         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID75;                        /*  RMID75          */
+    union iodefine_reg32_t  RMPTR75;                       /*  RMPTR75         */
+    union iodefine_reg32_t  RMDF075;                       /*  RMDF075         */
+    union iodefine_reg32_t  RMDF175;                       /*  RMDF175         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID76;                        /*  RMID76          */
+    union iodefine_reg32_t  RMPTR76;                       /*  RMPTR76         */
+    union iodefine_reg32_t  RMDF076;                       /*  RMDF076         */
+    union iodefine_reg32_t  RMDF176;                       /*  RMDF176         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID77;                        /*  RMID77          */
+    union iodefine_reg32_t  RMPTR77;                       /*  RMPTR77         */
+    union iodefine_reg32_t  RMDF077;                       /*  RMDF077         */
+    union iodefine_reg32_t  RMDF177;                       /*  RMDF177         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID78;                        /*  RMID78          */
+    union iodefine_reg32_t  RMPTR78;                       /*  RMPTR78         */
+    union iodefine_reg32_t  RMDF078;                       /*  RMDF078         */
+    union iodefine_reg32_t  RMDF178;                       /*  RMDF178         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID79;                        /*  RMID79          */
+    union iodefine_reg32_t  RMPTR79;                       /*  RMPTR79         */
+    union iodefine_reg32_t  RMDF079;                       /*  RMDF079         */
+    union iodefine_reg32_t  RMDF179;                       /*  RMDF179         */
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+    volatile uint8_t   dummy179[768];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID0;                         /*  RFID0           */
+    union iodefine_reg32_t  RFPTR0;                        /*  RFPTR0          */
+    union iodefine_reg32_t  RFDF00;                        /*  RFDF00          */
+    union iodefine_reg32_t  RFDF10;                        /*  RFDF10          */
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID1;                         /*  RFID1           */
+    union iodefine_reg32_t  RFPTR1;                        /*  RFPTR1          */
+    union iodefine_reg32_t  RFDF01;                        /*  RFDF01          */
+    union iodefine_reg32_t  RFDF11;                        /*  RFDF11          */
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID2;                         /*  RFID2           */
+    union iodefine_reg32_t  RFPTR2;                        /*  RFPTR2          */
+    union iodefine_reg32_t  RFDF02;                        /*  RFDF02          */
+    union iodefine_reg32_t  RFDF12;                        /*  RFDF12          */
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID3;                         /*  RFID3           */
+    union iodefine_reg32_t  RFPTR3;                        /*  RFPTR3          */
+    union iodefine_reg32_t  RFDF03;                        /*  RFDF03          */
+    union iodefine_reg32_t  RFDF13;                        /*  RFDF13          */
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID4;                         /*  RFID4           */
+    union iodefine_reg32_t  RFPTR4;                        /*  RFPTR4          */
+    union iodefine_reg32_t  RFDF04;                        /*  RFDF04          */
+    union iodefine_reg32_t  RFDF14;                        /*  RFDF14          */
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID5;                         /*  RFID5           */
+    union iodefine_reg32_t  RFPTR5;                        /*  RFPTR5          */
+    union iodefine_reg32_t  RFDF05;                        /*  RFDF05          */
+    union iodefine_reg32_t  RFDF15;                        /*  RFDF15          */
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID6;                         /*  RFID6           */
+    union iodefine_reg32_t  RFPTR6;                        /*  RFPTR6          */
+    union iodefine_reg32_t  RFDF06;                        /*  RFDF06          */
+    union iodefine_reg32_t  RFDF16;                        /*  RFDF16          */
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID7;                         /*  RFID7           */
+    union iodefine_reg32_t  RFPTR7;                        /*  RFPTR7          */
+    union iodefine_reg32_t  RFDF07;                        /*  RFDF07          */
+    union iodefine_reg32_t  RFDF17;                        /*  RFDF17          */
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID0;                         /*  CFID0           */
+    union iodefine_reg32_t  CFPTR0;                        /*  CFPTR0          */
+    union iodefine_reg32_t  CFDF00;                        /*  CFDF00          */
+    union iodefine_reg32_t  CFDF10;                        /*  CFDF10          */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID1;                         /*  CFID1           */
+    union iodefine_reg32_t  CFPTR1;                        /*  CFPTR1          */
+    union iodefine_reg32_t  CFDF01;                        /*  CFDF01          */
+    union iodefine_reg32_t  CFDF11;                        /*  CFDF11          */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID2;                         /*  CFID2           */
+    union iodefine_reg32_t  CFPTR2;                        /*  CFPTR2          */
+    union iodefine_reg32_t  CFDF02;                        /*  CFDF02          */
+    union iodefine_reg32_t  CFDF12;                        /*  CFDF12          */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID3;                         /*  CFID3           */
+    union iodefine_reg32_t  CFPTR3;                        /*  CFPTR3          */
+    union iodefine_reg32_t  CFDF03;                        /*  CFDF03          */
+    union iodefine_reg32_t  CFDF13;                        /*  CFDF13          */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID4;                         /*  CFID4           */
+    union iodefine_reg32_t  CFPTR4;                        /*  CFPTR4          */
+    union iodefine_reg32_t  CFDF04;                        /*  CFDF04          */
+    union iodefine_reg32_t  CFDF14;                        /*  CFDF14          */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID5;                         /*  CFID5           */
+    union iodefine_reg32_t  CFPTR5;                        /*  CFPTR5          */
+    union iodefine_reg32_t  CFDF05;                        /*  CFDF05          */
+    union iodefine_reg32_t  CFDF15;                        /*  CFDF15          */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID6;                         /*  CFID6           */
+    union iodefine_reg32_t  CFPTR6;                        /*  CFPTR6          */
+    union iodefine_reg32_t  CFDF06;                        /*  CFDF06          */
+    union iodefine_reg32_t  CFDF16;                        /*  CFDF16          */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID7;                         /*  CFID7           */
+    union iodefine_reg32_t  CFPTR7;                        /*  CFPTR7          */
+    union iodefine_reg32_t  CFDF07;                        /*  CFDF07          */
+    union iodefine_reg32_t  CFDF17;                        /*  CFDF17          */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID8;                         /*  CFID8           */
+    union iodefine_reg32_t  CFPTR8;                        /*  CFPTR8          */
+    union iodefine_reg32_t  CFDF08;                        /*  CFDF08          */
+    union iodefine_reg32_t  CFDF18;                        /*  CFDF18          */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID9;                         /*  CFID9           */
+    union iodefine_reg32_t  CFPTR9;                        /*  CFPTR9          */
+    union iodefine_reg32_t  CFDF09;                        /*  CFDF09          */
+    union iodefine_reg32_t  CFDF19;                        /*  CFDF19          */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID10;                        /*  CFID10          */
+    union iodefine_reg32_t  CFPTR10;                       /*  CFPTR10         */
+    union iodefine_reg32_t  CFDF010;                       /*  CFDF010         */
+    union iodefine_reg32_t  CFDF110;                       /*  CFDF110         */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID11;                        /*  CFID11          */
+    union iodefine_reg32_t  CFPTR11;                       /*  CFPTR11         */
+    union iodefine_reg32_t  CFDF011;                       /*  CFDF011         */
+    union iodefine_reg32_t  CFDF111;                       /*  CFDF111         */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID12;                        /*  CFID12          */
+    union iodefine_reg32_t  CFPTR12;                       /*  CFPTR12         */
+    union iodefine_reg32_t  CFDF012;                       /*  CFDF012         */
+    union iodefine_reg32_t  CFDF112;                       /*  CFDF112         */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID13;                        /*  CFID13          */
+    union iodefine_reg32_t  CFPTR13;                       /*  CFPTR13         */
+    union iodefine_reg32_t  CFDF013;                       /*  CFDF013         */
+    union iodefine_reg32_t  CFDF113;                       /*  CFDF113         */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID14;                        /*  CFID14          */
+    union iodefine_reg32_t  CFPTR14;                       /*  CFPTR14         */
+    union iodefine_reg32_t  CFDF014;                       /*  CFDF014         */
+    union iodefine_reg32_t  CFDF114;                       /*  CFDF114         */
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+    volatile uint8_t   dummy180[144];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID0;                         /*  TMID0           */
+    union iodefine_reg32_t  TMPTR0;                        /*  TMPTR0          */
+    union iodefine_reg32_t  TMDF00;                        /*  TMDF00          */
+    union iodefine_reg32_t  TMDF10;                        /*  TMDF10          */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID1;                         /*  TMID1           */
+    union iodefine_reg32_t  TMPTR1;                        /*  TMPTR1          */
+    union iodefine_reg32_t  TMDF01;                        /*  TMDF01          */
+    union iodefine_reg32_t  TMDF11;                        /*  TMDF11          */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID2;                         /*  TMID2           */
+    union iodefine_reg32_t  TMPTR2;                        /*  TMPTR2          */
+    union iodefine_reg32_t  TMDF02;                        /*  TMDF02          */
+    union iodefine_reg32_t  TMDF12;                        /*  TMDF12          */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID3;                         /*  TMID3           */
+    union iodefine_reg32_t  TMPTR3;                        /*  TMPTR3          */
+    union iodefine_reg32_t  TMDF03;                        /*  TMDF03          */
+    union iodefine_reg32_t  TMDF13;                        /*  TMDF13          */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID4;                         /*  TMID4           */
+    union iodefine_reg32_t  TMPTR4;                        /*  TMPTR4          */
+    union iodefine_reg32_t  TMDF04;                        /*  TMDF04          */
+    union iodefine_reg32_t  TMDF14;                        /*  TMDF14          */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID5;                         /*  TMID5           */
+    union iodefine_reg32_t  TMPTR5;                        /*  TMPTR5          */
+    union iodefine_reg32_t  TMDF05;                        /*  TMDF05          */
+    union iodefine_reg32_t  TMDF15;                        /*  TMDF15          */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID6;                         /*  TMID6           */
+    union iodefine_reg32_t  TMPTR6;                        /*  TMPTR6          */
+    union iodefine_reg32_t  TMDF06;                        /*  TMDF06          */
+    union iodefine_reg32_t  TMDF16;                        /*  TMDF16          */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID7;                         /*  TMID7           */
+    union iodefine_reg32_t  TMPTR7;                        /*  TMPTR7          */
+    union iodefine_reg32_t  TMDF07;                        /*  TMDF07          */
+    union iodefine_reg32_t  TMDF17;                        /*  TMDF17          */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID8;                         /*  TMID8           */
+    union iodefine_reg32_t  TMPTR8;                        /*  TMPTR8          */
+    union iodefine_reg32_t  TMDF08;                        /*  TMDF08          */
+    union iodefine_reg32_t  TMDF18;                        /*  TMDF18          */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID9;                         /*  TMID9           */
+    union iodefine_reg32_t  TMPTR9;                        /*  TMPTR9          */
+    union iodefine_reg32_t  TMDF09;                        /*  TMDF09          */
+    union iodefine_reg32_t  TMDF19;                        /*  TMDF19          */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID10;                        /*  TMID10          */
+    union iodefine_reg32_t  TMPTR10;                       /*  TMPTR10         */
+    union iodefine_reg32_t  TMDF010;                       /*  TMDF010         */
+    union iodefine_reg32_t  TMDF110;                       /*  TMDF110         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID11;                        /*  TMID11          */
+    union iodefine_reg32_t  TMPTR11;                       /*  TMPTR11         */
+    union iodefine_reg32_t  TMDF011;                       /*  TMDF011         */
+    union iodefine_reg32_t  TMDF111;                       /*  TMDF111         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID12;                        /*  TMID12          */
+    union iodefine_reg32_t  TMPTR12;                       /*  TMPTR12         */
+    union iodefine_reg32_t  TMDF012;                       /*  TMDF012         */
+    union iodefine_reg32_t  TMDF112;                       /*  TMDF112         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID13;                        /*  TMID13          */
+    union iodefine_reg32_t  TMPTR13;                       /*  TMPTR13         */
+    union iodefine_reg32_t  TMDF013;                       /*  TMDF013         */
+    union iodefine_reg32_t  TMDF113;                       /*  TMDF113         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID14;                        /*  TMID14          */
+    union iodefine_reg32_t  TMPTR14;                       /*  TMPTR14         */
+    union iodefine_reg32_t  TMDF014;                       /*  TMDF014         */
+    union iodefine_reg32_t  TMDF114;                       /*  TMDF114         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID15;                        /*  TMID15          */
+    union iodefine_reg32_t  TMPTR15;                       /*  TMPTR15         */
+    union iodefine_reg32_t  TMDF015;                       /*  TMDF015         */
+    union iodefine_reg32_t  TMDF115;                       /*  TMDF115         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID16;                        /*  TMID16          */
+    union iodefine_reg32_t  TMPTR16;                       /*  TMPTR16         */
+    union iodefine_reg32_t  TMDF016;                       /*  TMDF016         */
+    union iodefine_reg32_t  TMDF116;                       /*  TMDF116         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID17;                        /*  TMID17          */
+    union iodefine_reg32_t  TMPTR17;                       /*  TMPTR17         */
+    union iodefine_reg32_t  TMDF017;                       /*  TMDF017         */
+    union iodefine_reg32_t  TMDF117;                       /*  TMDF117         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID18;                        /*  TMID18          */
+    union iodefine_reg32_t  TMPTR18;                       /*  TMPTR18         */
+    union iodefine_reg32_t  TMDF018;                       /*  TMDF018         */
+    union iodefine_reg32_t  TMDF118;                       /*  TMDF118         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID19;                        /*  TMID19          */
+    union iodefine_reg32_t  TMPTR19;                       /*  TMPTR19         */
+    union iodefine_reg32_t  TMDF019;                       /*  TMDF019         */
+    union iodefine_reg32_t  TMDF119;                       /*  TMDF119         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID20;                        /*  TMID20          */
+    union iodefine_reg32_t  TMPTR20;                       /*  TMPTR20         */
+    union iodefine_reg32_t  TMDF020;                       /*  TMDF020         */
+    union iodefine_reg32_t  TMDF120;                       /*  TMDF120         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID21;                        /*  TMID21          */
+    union iodefine_reg32_t  TMPTR21;                       /*  TMPTR21         */
+    union iodefine_reg32_t  TMDF021;                       /*  TMDF021         */
+    union iodefine_reg32_t  TMDF121;                       /*  TMDF121         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID22;                        /*  TMID22          */
+    union iodefine_reg32_t  TMPTR22;                       /*  TMPTR22         */
+    union iodefine_reg32_t  TMDF022;                       /*  TMDF022         */
+    union iodefine_reg32_t  TMDF122;                       /*  TMDF122         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID23;                        /*  TMID23          */
+    union iodefine_reg32_t  TMPTR23;                       /*  TMPTR23         */
+    union iodefine_reg32_t  TMDF023;                       /*  TMDF023         */
+    union iodefine_reg32_t  TMDF123;                       /*  TMDF123         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID24;                        /*  TMID24          */
+    union iodefine_reg32_t  TMPTR24;                       /*  TMPTR24         */
+    union iodefine_reg32_t  TMDF024;                       /*  TMDF024         */
+    union iodefine_reg32_t  TMDF124;                       /*  TMDF124         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID25;                        /*  TMID25          */
+    union iodefine_reg32_t  TMPTR25;                       /*  TMPTR25         */
+    union iodefine_reg32_t  TMDF025;                       /*  TMDF025         */
+    union iodefine_reg32_t  TMDF125;                       /*  TMDF125         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID26;                        /*  TMID26          */
+    union iodefine_reg32_t  TMPTR26;                       /*  TMPTR26         */
+    union iodefine_reg32_t  TMDF026;                       /*  TMDF026         */
+    union iodefine_reg32_t  TMDF126;                       /*  TMDF126         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID27;                        /*  TMID27          */
+    union iodefine_reg32_t  TMPTR27;                       /*  TMPTR27         */
+    union iodefine_reg32_t  TMDF027;                       /*  TMDF027         */
+    union iodefine_reg32_t  TMDF127;                       /*  TMDF127         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID28;                        /*  TMID28          */
+    union iodefine_reg32_t  TMPTR28;                       /*  TMPTR28         */
+    union iodefine_reg32_t  TMDF028;                       /*  TMDF028         */
+    union iodefine_reg32_t  TMDF128;                       /*  TMDF128         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID29;                        /*  TMID29          */
+    union iodefine_reg32_t  TMPTR29;                       /*  TMPTR29         */
+    union iodefine_reg32_t  TMDF029;                       /*  TMDF029         */
+    union iodefine_reg32_t  TMDF129;                       /*  TMDF129         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID30;                        /*  TMID30          */
+    union iodefine_reg32_t  TMPTR30;                       /*  TMPTR30         */
+    union iodefine_reg32_t  TMDF030;                       /*  TMDF030         */
+    union iodefine_reg32_t  TMDF130;                       /*  TMDF130         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID31;                        /*  TMID31          */
+    union iodefine_reg32_t  TMPTR31;                       /*  TMPTR31         */
+    union iodefine_reg32_t  TMDF031;                       /*  TMDF031         */
+    union iodefine_reg32_t  TMDF131;                       /*  TMDF131         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID32;                        /*  TMID32          */
+    union iodefine_reg32_t  TMPTR32;                       /*  TMPTR32         */
+    union iodefine_reg32_t  TMDF032;                       /*  TMDF032         */
+    union iodefine_reg32_t  TMDF132;                       /*  TMDF132         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID33;                        /*  TMID33          */
+    union iodefine_reg32_t  TMPTR33;                       /*  TMPTR33         */
+    union iodefine_reg32_t  TMDF033;                       /*  TMDF033         */
+    union iodefine_reg32_t  TMDF133;                       /*  TMDF133         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID34;                        /*  TMID34          */
+    union iodefine_reg32_t  TMPTR34;                       /*  TMPTR34         */
+    union iodefine_reg32_t  TMDF034;                       /*  TMDF034         */
+    union iodefine_reg32_t  TMDF134;                       /*  TMDF134         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID35;                        /*  TMID35          */
+    union iodefine_reg32_t  TMPTR35;                       /*  TMPTR35         */
+    union iodefine_reg32_t  TMDF035;                       /*  TMDF035         */
+    union iodefine_reg32_t  TMDF135;                       /*  TMDF135         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID36;                        /*  TMID36          */
+    union iodefine_reg32_t  TMPTR36;                       /*  TMPTR36         */
+    union iodefine_reg32_t  TMDF036;                       /*  TMDF036         */
+    union iodefine_reg32_t  TMDF136;                       /*  TMDF136         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID37;                        /*  TMID37          */
+    union iodefine_reg32_t  TMPTR37;                       /*  TMPTR37         */
+    union iodefine_reg32_t  TMDF037;                       /*  TMDF037         */
+    union iodefine_reg32_t  TMDF137;                       /*  TMDF137         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID38;                        /*  TMID38          */
+    union iodefine_reg32_t  TMPTR38;                       /*  TMPTR38         */
+    union iodefine_reg32_t  TMDF038;                       /*  TMDF038         */
+    union iodefine_reg32_t  TMDF138;                       /*  TMDF138         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID39;                        /*  TMID39          */
+    union iodefine_reg32_t  TMPTR39;                       /*  TMPTR39         */
+    union iodefine_reg32_t  TMDF039;                       /*  TMDF039         */
+    union iodefine_reg32_t  TMDF139;                       /*  TMDF139         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID40;                        /*  TMID40          */
+    union iodefine_reg32_t  TMPTR40;                       /*  TMPTR40         */
+    union iodefine_reg32_t  TMDF040;                       /*  TMDF040         */
+    union iodefine_reg32_t  TMDF140;                       /*  TMDF140         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID41;                        /*  TMID41          */
+    union iodefine_reg32_t  TMPTR41;                       /*  TMPTR41         */
+    union iodefine_reg32_t  TMDF041;                       /*  TMDF041         */
+    union iodefine_reg32_t  TMDF141;                       /*  TMDF141         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID42;                        /*  TMID42          */
+    union iodefine_reg32_t  TMPTR42;                       /*  TMPTR42         */
+    union iodefine_reg32_t  TMDF042;                       /*  TMDF042         */
+    union iodefine_reg32_t  TMDF142;                       /*  TMDF142         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID43;                        /*  TMID43          */
+    union iodefine_reg32_t  TMPTR43;                       /*  TMPTR43         */
+    union iodefine_reg32_t  TMDF043;                       /*  TMDF043         */
+    union iodefine_reg32_t  TMDF143;                       /*  TMDF143         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID44;                        /*  TMID44          */
+    union iodefine_reg32_t  TMPTR44;                       /*  TMPTR44         */
+    union iodefine_reg32_t  TMDF044;                       /*  TMDF044         */
+    union iodefine_reg32_t  TMDF144;                       /*  TMDF144         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID45;                        /*  TMID45          */
+    union iodefine_reg32_t  TMPTR45;                       /*  TMPTR45         */
+    union iodefine_reg32_t  TMDF045;                       /*  TMDF045         */
+    union iodefine_reg32_t  TMDF145;                       /*  TMDF145         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID46;                        /*  TMID46          */
+    union iodefine_reg32_t  TMPTR46;                       /*  TMPTR46         */
+    union iodefine_reg32_t  TMDF046;                       /*  TMDF046         */
+    union iodefine_reg32_t  TMDF146;                       /*  TMDF146         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID47;                        /*  TMID47          */
+    union iodefine_reg32_t  TMPTR47;                       /*  TMPTR47         */
+    union iodefine_reg32_t  TMDF047;                       /*  TMDF047         */
+    union iodefine_reg32_t  TMDF147;                       /*  TMDF147         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID48;                        /*  TMID48          */
+    union iodefine_reg32_t  TMPTR48;                       /*  TMPTR48         */
+    union iodefine_reg32_t  TMDF048;                       /*  TMDF048         */
+    union iodefine_reg32_t  TMDF148;                       /*  TMDF148         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID49;                        /*  TMID49          */
+    union iodefine_reg32_t  TMPTR49;                       /*  TMPTR49         */
+    union iodefine_reg32_t  TMDF049;                       /*  TMDF049         */
+    union iodefine_reg32_t  TMDF149;                       /*  TMDF149         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID50;                        /*  TMID50          */
+    union iodefine_reg32_t  TMPTR50;                       /*  TMPTR50         */
+    union iodefine_reg32_t  TMDF050;                       /*  TMDF050         */
+    union iodefine_reg32_t  TMDF150;                       /*  TMDF150         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID51;                        /*  TMID51          */
+    union iodefine_reg32_t  TMPTR51;                       /*  TMPTR51         */
+    union iodefine_reg32_t  TMDF051;                       /*  TMDF051         */
+    union iodefine_reg32_t  TMDF151;                       /*  TMDF151         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID52;                        /*  TMID52          */
+    union iodefine_reg32_t  TMPTR52;                       /*  TMPTR52         */
+    union iodefine_reg32_t  TMDF052;                       /*  TMDF052         */
+    union iodefine_reg32_t  TMDF152;                       /*  TMDF152         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID53;                        /*  TMID53          */
+    union iodefine_reg32_t  TMPTR53;                       /*  TMPTR53         */
+    union iodefine_reg32_t  TMDF053;                       /*  TMDF053         */
+    union iodefine_reg32_t  TMDF153;                       /*  TMDF153         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID54;                        /*  TMID54          */
+    union iodefine_reg32_t  TMPTR54;                       /*  TMPTR54         */
+    union iodefine_reg32_t  TMDF054;                       /*  TMDF054         */
+    union iodefine_reg32_t  TMDF154;                       /*  TMDF154         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID55;                        /*  TMID55          */
+    union iodefine_reg32_t  TMPTR55;                       /*  TMPTR55         */
+    union iodefine_reg32_t  TMDF055;                       /*  TMDF055         */
+    union iodefine_reg32_t  TMDF155;                       /*  TMDF155         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID56;                        /*  TMID56          */
+    union iodefine_reg32_t  TMPTR56;                       /*  TMPTR56         */
+    union iodefine_reg32_t  TMDF056;                       /*  TMDF056         */
+    union iodefine_reg32_t  TMDF156;                       /*  TMDF156         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID57;                        /*  TMID57          */
+    union iodefine_reg32_t  TMPTR57;                       /*  TMPTR57         */
+    union iodefine_reg32_t  TMDF057;                       /*  TMDF057         */
+    union iodefine_reg32_t  TMDF157;                       /*  TMDF157         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID58;                        /*  TMID58          */
+    union iodefine_reg32_t  TMPTR58;                       /*  TMPTR58         */
+    union iodefine_reg32_t  TMDF058;                       /*  TMDF058         */
+    union iodefine_reg32_t  TMDF158;                       /*  TMDF158         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID59;                        /*  TMID59          */
+    union iodefine_reg32_t  TMPTR59;                       /*  TMPTR59         */
+    union iodefine_reg32_t  TMDF059;                       /*  TMDF059         */
+    union iodefine_reg32_t  TMDF159;                       /*  TMDF159         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID60;                        /*  TMID60          */
+    union iodefine_reg32_t  TMPTR60;                       /*  TMPTR60         */
+    union iodefine_reg32_t  TMDF060;                       /*  TMDF060         */
+    union iodefine_reg32_t  TMDF160;                       /*  TMDF160         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID61;                        /*  TMID61          */
+    union iodefine_reg32_t  TMPTR61;                       /*  TMPTR61         */
+    union iodefine_reg32_t  TMDF061;                       /*  TMDF061         */
+    union iodefine_reg32_t  TMDF161;                       /*  TMDF161         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID62;                        /*  TMID62          */
+    union iodefine_reg32_t  TMPTR62;                       /*  TMPTR62         */
+    union iodefine_reg32_t  TMDF062;                       /*  TMDF062         */
+    union iodefine_reg32_t  TMDF162;                       /*  TMDF162         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID63;                        /*  TMID63          */
+    union iodefine_reg32_t  TMPTR63;                       /*  TMPTR63         */
+    union iodefine_reg32_t  TMDF063;                       /*  TMDF063         */
+    union iodefine_reg32_t  TMDF163;                       /*  TMDF163         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID64;                        /*  TMID64          */
+    union iodefine_reg32_t  TMPTR64;                       /*  TMPTR64         */
+    union iodefine_reg32_t  TMDF064;                       /*  TMDF064         */
+    union iodefine_reg32_t  TMDF164;                       /*  TMDF164         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID65;                        /*  TMID65          */
+    union iodefine_reg32_t  TMPTR65;                       /*  TMPTR65         */
+    union iodefine_reg32_t  TMDF065;                       /*  TMDF065         */
+    union iodefine_reg32_t  TMDF165;                       /*  TMDF165         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID66;                        /*  TMID66          */
+    union iodefine_reg32_t  TMPTR66;                       /*  TMPTR66         */
+    union iodefine_reg32_t  TMDF066;                       /*  TMDF066         */
+    union iodefine_reg32_t  TMDF166;                       /*  TMDF166         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID67;                        /*  TMID67          */
+    union iodefine_reg32_t  TMPTR67;                       /*  TMPTR67         */
+    union iodefine_reg32_t  TMDF067;                       /*  TMDF067         */
+    union iodefine_reg32_t  TMDF167;                       /*  TMDF167         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID68;                        /*  TMID68          */
+    union iodefine_reg32_t  TMPTR68;                       /*  TMPTR68         */
+    union iodefine_reg32_t  TMDF068;                       /*  TMDF068         */
+    union iodefine_reg32_t  TMDF168;                       /*  TMDF168         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID69;                        /*  TMID69          */
+    union iodefine_reg32_t  TMPTR69;                       /*  TMPTR69         */
+    union iodefine_reg32_t  TMDF069;                       /*  TMDF069         */
+    union iodefine_reg32_t  TMDF169;                       /*  TMDF169         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID70;                        /*  TMID70          */
+    union iodefine_reg32_t  TMPTR70;                       /*  TMPTR70         */
+    union iodefine_reg32_t  TMDF070;                       /*  TMDF070         */
+    union iodefine_reg32_t  TMDF170;                       /*  TMDF170         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID71;                        /*  TMID71          */
+    union iodefine_reg32_t  TMPTR71;                       /*  TMPTR71         */
+    union iodefine_reg32_t  TMDF071;                       /*  TMDF071         */
+    union iodefine_reg32_t  TMDF171;                       /*  TMDF171         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID72;                        /*  TMID72          */
+    union iodefine_reg32_t  TMPTR72;                       /*  TMPTR72         */
+    union iodefine_reg32_t  TMDF072;                       /*  TMDF072         */
+    union iodefine_reg32_t  TMDF172;                       /*  TMDF172         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID73;                        /*  TMID73          */
+    union iodefine_reg32_t  TMPTR73;                       /*  TMPTR73         */
+    union iodefine_reg32_t  TMDF073;                       /*  TMDF073         */
+    union iodefine_reg32_t  TMDF173;                       /*  TMDF173         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID74;                        /*  TMID74          */
+    union iodefine_reg32_t  TMPTR74;                       /*  TMPTR74         */
+    union iodefine_reg32_t  TMDF074;                       /*  TMDF074         */
+    union iodefine_reg32_t  TMDF174;                       /*  TMDF174         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID75;                        /*  TMID75          */
+    union iodefine_reg32_t  TMPTR75;                       /*  TMPTR75         */
+    union iodefine_reg32_t  TMDF075;                       /*  TMDF075         */
+    union iodefine_reg32_t  TMDF175;                       /*  TMDF175         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID76;                        /*  TMID76          */
+    union iodefine_reg32_t  TMPTR76;                       /*  TMPTR76         */
+    union iodefine_reg32_t  TMDF076;                       /*  TMDF076         */
+    union iodefine_reg32_t  TMDF176;                       /*  TMDF176         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID77;                        /*  TMID77          */
+    union iodefine_reg32_t  TMPTR77;                       /*  TMPTR77         */
+    union iodefine_reg32_t  TMDF077;                       /*  TMDF077         */
+    union iodefine_reg32_t  TMDF177;                       /*  TMDF177         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID78;                        /*  TMID78          */
+    union iodefine_reg32_t  TMPTR78;                       /*  TMPTR78         */
+    union iodefine_reg32_t  TMDF078;                       /*  TMDF078         */
+    union iodefine_reg32_t  TMDF178;                       /*  TMDF178         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID79;                        /*  TMID79          */
+    union iodefine_reg32_t  TMPTR79;                       /*  TMPTR79         */
+    union iodefine_reg32_t  TMDF079;                       /*  TMDF079         */
+    union iodefine_reg32_t  TMDF179;                       /*  TMDF179         */
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+    volatile uint8_t   dummy181[768];                          /*                  */
+#define RSCAN0_THLACC0_COUNT 5
+    union iodefine_reg32_t  THLACC0;                       /*  THLACC0         */
+    union iodefine_reg32_t  THLACC1;                       /*  THLACC1         */
+    union iodefine_reg32_t  THLACC2;                       /*  THLACC2         */
+    union iodefine_reg32_t  THLACC3;                       /*  THLACC3         */
+    union iodefine_reg32_t  THLACC4;                       /*  THLACC4         */
+    
+};
+
+
+struct st_rscan_from_rscan0cncfg
+{
+    union iodefine_reg32_t  CnCFG;                         /*  CnCFG           */
+    union iodefine_reg32_t  CnCTR;                         /*  CnCTR           */
+    union iodefine_reg32_t  CnSTS;                         /*  CnSTS           */
+    union iodefine_reg32_t  CnERFL;                        /*  CnERFL          */
+};
+
+
+struct st_rscan_from_rscan0gaflidj
+{
+    union iodefine_reg32_t  GAFLIDj;                       /*  GAFLIDj         */
+    union iodefine_reg32_t  GAFLMj;                        /*  GAFLMj          */
+    union iodefine_reg32_t  GAFLP0j;                       /*  GAFLP0j         */
+    union iodefine_reg32_t  GAFLP1j;                       /*  GAFLP1j         */
+};
+
+
+struct st_rscan_from_rscan0rmidp
+{
+    union iodefine_reg32_t  RMIDp;                         /*  RMIDp           */
+    union iodefine_reg32_t  RMPTRp;                        /*  RMPTRp          */
+    union iodefine_reg32_t  RMDF0p;                        /*  RMDF0p          */
+    union iodefine_reg32_t  RMDF1p;                        /*  RMDF1p          */
+};
+
+
+struct st_rscan_from_rscan0rfidm
+{
+    union iodefine_reg32_t  RFIDm;                         /*  RFIDm           */
+    union iodefine_reg32_t  RFPTRm;                        /*  RFPTRm          */
+    union iodefine_reg32_t  RFDF0m;                        /*  RFDF0m          */
+    union iodefine_reg32_t  RFDF1m;                        /*  RFDF1m          */
+};
+
+
+struct st_rscan_from_rscan0tmidp
+{
+    union iodefine_reg32_t  TMIDp;                         /*  TMIDp           */
+    union iodefine_reg32_t  TMPTRp;                        /*  TMPTRp          */
+    union iodefine_reg32_t  TMDF0p;                        /*  TMDF0p          */
+    union iodefine_reg32_t  TMDF1p;                        /*  TMDF1p          */
+};
+
+
+struct st_rscan_from_rscan0cfidm
+{
+    union iodefine_reg32_t  CFIDm;                         /*  CFIDm           */
+    union iodefine_reg32_t  CFPTRm;                        /*  CFPTRm          */
+    union iodefine_reg32_t  CFDF0m;                        /*  CFDF0m          */
+    union iodefine_reg32_t  CFDF1m;                        /*  CFDF1m          */
+};
+
+
+#define RSCAN0  (*(struct st_rscan0  *)0xE803A000uL) /* RSCAN0 */
+
+
+/* Start of channnel array defines of RSCAN0 */
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0CFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0CFIDm[ channel ]->CFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0CFIDm_COUNT  15
+#define RSCAN_FROM_RSCAN0CFIDm_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \
+    &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0CFID0 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID0) /* RSCAN_FROM_RSCAN0CFID0 */
+#define RSCAN_FROM_RSCAN0CFID1 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID1) /* RSCAN_FROM_RSCAN0CFID1 */
+#define RSCAN_FROM_RSCAN0CFID2 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID2) /* RSCAN_FROM_RSCAN0CFID2 */
+#define RSCAN_FROM_RSCAN0CFID3 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID3) /* RSCAN_FROM_RSCAN0CFID3 */
+#define RSCAN_FROM_RSCAN0CFID4 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID4) /* RSCAN_FROM_RSCAN0CFID4 */
+#define RSCAN_FROM_RSCAN0CFID5 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID5) /* RSCAN_FROM_RSCAN0CFID5 */
+#define RSCAN_FROM_RSCAN0CFID6 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID6) /* RSCAN_FROM_RSCAN0CFID6 */
+#define RSCAN_FROM_RSCAN0CFID7 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID7) /* RSCAN_FROM_RSCAN0CFID7 */
+#define RSCAN_FROM_RSCAN0CFID8 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID8) /* RSCAN_FROM_RSCAN0CFID8 */
+#define RSCAN_FROM_RSCAN0CFID9 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID9) /* RSCAN_FROM_RSCAN0CFID9 */
+#define RSCAN_FROM_RSCAN0CFID10 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID10) /* RSCAN_FROM_RSCAN0CFID10 */
+#define RSCAN_FROM_RSCAN0CFID11 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID11) /* RSCAN_FROM_RSCAN0CFID11 */
+#define RSCAN_FROM_RSCAN0CFID12 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID12) /* RSCAN_FROM_RSCAN0CFID12 */
+#define RSCAN_FROM_RSCAN0CFID13 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID13) /* RSCAN_FROM_RSCAN0CFID13 */
+#define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0TMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0TMIDp[ channel ]->TMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0TMIDp_COUNT  80
+#define RSCAN_FROM_RSCAN0TMIDp_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \
+    &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \
+    &RSCAN_FROM_RSCAN0TMID16, &RSCAN_FROM_RSCAN0TMID17, &RSCAN_FROM_RSCAN0TMID18, &RSCAN_FROM_RSCAN0TMID19, &RSCAN_FROM_RSCAN0TMID20, &RSCAN_FROM_RSCAN0TMID21, &RSCAN_FROM_RSCAN0TMID22, &RSCAN_FROM_RSCAN0TMID23, \
+    &RSCAN_FROM_RSCAN0TMID24, &RSCAN_FROM_RSCAN0TMID25, &RSCAN_FROM_RSCAN0TMID26, &RSCAN_FROM_RSCAN0TMID27, &RSCAN_FROM_RSCAN0TMID28, &RSCAN_FROM_RSCAN0TMID29, &RSCAN_FROM_RSCAN0TMID30, &RSCAN_FROM_RSCAN0TMID31, \
+    &RSCAN_FROM_RSCAN0TMID32, &RSCAN_FROM_RSCAN0TMID33, &RSCAN_FROM_RSCAN0TMID34, &RSCAN_FROM_RSCAN0TMID35, &RSCAN_FROM_RSCAN0TMID36, &RSCAN_FROM_RSCAN0TMID37, &RSCAN_FROM_RSCAN0TMID38, &RSCAN_FROM_RSCAN0TMID39, \
+    &RSCAN_FROM_RSCAN0TMID40, &RSCAN_FROM_RSCAN0TMID41, &RSCAN_FROM_RSCAN0TMID42, &RSCAN_FROM_RSCAN0TMID43, &RSCAN_FROM_RSCAN0TMID44, &RSCAN_FROM_RSCAN0TMID45, &RSCAN_FROM_RSCAN0TMID46, &RSCAN_FROM_RSCAN0TMID47, \
+    &RSCAN_FROM_RSCAN0TMID48, &RSCAN_FROM_RSCAN0TMID49, &RSCAN_FROM_RSCAN0TMID50, &RSCAN_FROM_RSCAN0TMID51, &RSCAN_FROM_RSCAN0TMID52, &RSCAN_FROM_RSCAN0TMID53, &RSCAN_FROM_RSCAN0TMID54, &RSCAN_FROM_RSCAN0TMID55, \
+    &RSCAN_FROM_RSCAN0TMID56, &RSCAN_FROM_RSCAN0TMID57, &RSCAN_FROM_RSCAN0TMID58, &RSCAN_FROM_RSCAN0TMID59, &RSCAN_FROM_RSCAN0TMID60, &RSCAN_FROM_RSCAN0TMID61, &RSCAN_FROM_RSCAN0TMID62, &RSCAN_FROM_RSCAN0TMID63, \
+    &RSCAN_FROM_RSCAN0TMID64, &RSCAN_FROM_RSCAN0TMID65, &RSCAN_FROM_RSCAN0TMID66, &RSCAN_FROM_RSCAN0TMID67, &RSCAN_FROM_RSCAN0TMID68, &RSCAN_FROM_RSCAN0TMID69, &RSCAN_FROM_RSCAN0TMID70, &RSCAN_FROM_RSCAN0TMID71, \
+    &RSCAN_FROM_RSCAN0TMID72, &RSCAN_FROM_RSCAN0TMID73, &RSCAN_FROM_RSCAN0TMID74, &RSCAN_FROM_RSCAN0TMID75, &RSCAN_FROM_RSCAN0TMID76, &RSCAN_FROM_RSCAN0TMID77, &RSCAN_FROM_RSCAN0TMID78, &RSCAN_FROM_RSCAN0TMID79 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0TMID0 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID0) /* RSCAN_FROM_RSCAN0TMID0 */
+#define RSCAN_FROM_RSCAN0TMID1 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID1) /* RSCAN_FROM_RSCAN0TMID1 */
+#define RSCAN_FROM_RSCAN0TMID2 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID2) /* RSCAN_FROM_RSCAN0TMID2 */
+#define RSCAN_FROM_RSCAN0TMID3 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID3) /* RSCAN_FROM_RSCAN0TMID3 */
+#define RSCAN_FROM_RSCAN0TMID4 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID4) /* RSCAN_FROM_RSCAN0TMID4 */
+#define RSCAN_FROM_RSCAN0TMID5 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID5) /* RSCAN_FROM_RSCAN0TMID5 */
+#define RSCAN_FROM_RSCAN0TMID6 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID6) /* RSCAN_FROM_RSCAN0TMID6 */
+#define RSCAN_FROM_RSCAN0TMID7 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID7) /* RSCAN_FROM_RSCAN0TMID7 */
+#define RSCAN_FROM_RSCAN0TMID8 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID8) /* RSCAN_FROM_RSCAN0TMID8 */
+#define RSCAN_FROM_RSCAN0TMID9 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID9) /* RSCAN_FROM_RSCAN0TMID9 */
+#define RSCAN_FROM_RSCAN0TMID10 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID10) /* RSCAN_FROM_RSCAN0TMID10 */
+#define RSCAN_FROM_RSCAN0TMID11 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID11) /* RSCAN_FROM_RSCAN0TMID11 */
+#define RSCAN_FROM_RSCAN0TMID12 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID12) /* RSCAN_FROM_RSCAN0TMID12 */
+#define RSCAN_FROM_RSCAN0TMID13 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID13) /* RSCAN_FROM_RSCAN0TMID13 */
+#define RSCAN_FROM_RSCAN0TMID14 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID14) /* RSCAN_FROM_RSCAN0TMID14 */
+#define RSCAN_FROM_RSCAN0TMID15 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID15) /* RSCAN_FROM_RSCAN0TMID15 */
+#define RSCAN_FROM_RSCAN0TMID16 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID16) /* RSCAN_FROM_RSCAN0TMID16 */
+#define RSCAN_FROM_RSCAN0TMID17 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID17) /* RSCAN_FROM_RSCAN0TMID17 */
+#define RSCAN_FROM_RSCAN0TMID18 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID18) /* RSCAN_FROM_RSCAN0TMID18 */
+#define RSCAN_FROM_RSCAN0TMID19 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID19) /* RSCAN_FROM_RSCAN0TMID19 */
+#define RSCAN_FROM_RSCAN0TMID20 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID20) /* RSCAN_FROM_RSCAN0TMID20 */
+#define RSCAN_FROM_RSCAN0TMID21 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID21) /* RSCAN_FROM_RSCAN0TMID21 */
+#define RSCAN_FROM_RSCAN0TMID22 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID22) /* RSCAN_FROM_RSCAN0TMID22 */
+#define RSCAN_FROM_RSCAN0TMID23 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID23) /* RSCAN_FROM_RSCAN0TMID23 */
+#define RSCAN_FROM_RSCAN0TMID24 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID24) /* RSCAN_FROM_RSCAN0TMID24 */
+#define RSCAN_FROM_RSCAN0TMID25 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID25) /* RSCAN_FROM_RSCAN0TMID25 */
+#define RSCAN_FROM_RSCAN0TMID26 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID26) /* RSCAN_FROM_RSCAN0TMID26 */
+#define RSCAN_FROM_RSCAN0TMID27 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID27) /* RSCAN_FROM_RSCAN0TMID27 */
+#define RSCAN_FROM_RSCAN0TMID28 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID28) /* RSCAN_FROM_RSCAN0TMID28 */
+#define RSCAN_FROM_RSCAN0TMID29 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID29) /* RSCAN_FROM_RSCAN0TMID29 */
+#define RSCAN_FROM_RSCAN0TMID30 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID30) /* RSCAN_FROM_RSCAN0TMID30 */
+#define RSCAN_FROM_RSCAN0TMID31 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID31) /* RSCAN_FROM_RSCAN0TMID31 */
+#define RSCAN_FROM_RSCAN0TMID32 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID32) /* RSCAN_FROM_RSCAN0TMID32 */
+#define RSCAN_FROM_RSCAN0TMID33 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID33) /* RSCAN_FROM_RSCAN0TMID33 */
+#define RSCAN_FROM_RSCAN0TMID34 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID34) /* RSCAN_FROM_RSCAN0TMID34 */
+#define RSCAN_FROM_RSCAN0TMID35 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID35) /* RSCAN_FROM_RSCAN0TMID35 */
+#define RSCAN_FROM_RSCAN0TMID36 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID36) /* RSCAN_FROM_RSCAN0TMID36 */
+#define RSCAN_FROM_RSCAN0TMID37 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID37) /* RSCAN_FROM_RSCAN0TMID37 */
+#define RSCAN_FROM_RSCAN0TMID38 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID38) /* RSCAN_FROM_RSCAN0TMID38 */
+#define RSCAN_FROM_RSCAN0TMID39 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID39) /* RSCAN_FROM_RSCAN0TMID39 */
+#define RSCAN_FROM_RSCAN0TMID40 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID40) /* RSCAN_FROM_RSCAN0TMID40 */
+#define RSCAN_FROM_RSCAN0TMID41 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID41) /* RSCAN_FROM_RSCAN0TMID41 */
+#define RSCAN_FROM_RSCAN0TMID42 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID42) /* RSCAN_FROM_RSCAN0TMID42 */
+#define RSCAN_FROM_RSCAN0TMID43 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID43) /* RSCAN_FROM_RSCAN0TMID43 */
+#define RSCAN_FROM_RSCAN0TMID44 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID44) /* RSCAN_FROM_RSCAN0TMID44 */
+#define RSCAN_FROM_RSCAN0TMID45 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID45) /* RSCAN_FROM_RSCAN0TMID45 */
+#define RSCAN_FROM_RSCAN0TMID46 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID46) /* RSCAN_FROM_RSCAN0TMID46 */
+#define RSCAN_FROM_RSCAN0TMID47 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID47) /* RSCAN_FROM_RSCAN0TMID47 */
+#define RSCAN_FROM_RSCAN0TMID48 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID48) /* RSCAN_FROM_RSCAN0TMID48 */
+#define RSCAN_FROM_RSCAN0TMID49 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID49) /* RSCAN_FROM_RSCAN0TMID49 */
+#define RSCAN_FROM_RSCAN0TMID50 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID50) /* RSCAN_FROM_RSCAN0TMID50 */
+#define RSCAN_FROM_RSCAN0TMID51 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID51) /* RSCAN_FROM_RSCAN0TMID51 */
+#define RSCAN_FROM_RSCAN0TMID52 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID52) /* RSCAN_FROM_RSCAN0TMID52 */
+#define RSCAN_FROM_RSCAN0TMID53 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID53) /* RSCAN_FROM_RSCAN0TMID53 */
+#define RSCAN_FROM_RSCAN0TMID54 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID54) /* RSCAN_FROM_RSCAN0TMID54 */
+#define RSCAN_FROM_RSCAN0TMID55 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID55) /* RSCAN_FROM_RSCAN0TMID55 */
+#define RSCAN_FROM_RSCAN0TMID56 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID56) /* RSCAN_FROM_RSCAN0TMID56 */
+#define RSCAN_FROM_RSCAN0TMID57 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID57) /* RSCAN_FROM_RSCAN0TMID57 */
+#define RSCAN_FROM_RSCAN0TMID58 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID58) /* RSCAN_FROM_RSCAN0TMID58 */
+#define RSCAN_FROM_RSCAN0TMID59 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID59) /* RSCAN_FROM_RSCAN0TMID59 */
+#define RSCAN_FROM_RSCAN0TMID60 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID60) /* RSCAN_FROM_RSCAN0TMID60 */
+#define RSCAN_FROM_RSCAN0TMID61 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID61) /* RSCAN_FROM_RSCAN0TMID61 */
+#define RSCAN_FROM_RSCAN0TMID62 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID62) /* RSCAN_FROM_RSCAN0TMID62 */
+#define RSCAN_FROM_RSCAN0TMID63 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID63) /* RSCAN_FROM_RSCAN0TMID63 */
+#define RSCAN_FROM_RSCAN0TMID64 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID64) /* RSCAN_FROM_RSCAN0TMID64 */
+#define RSCAN_FROM_RSCAN0TMID65 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID65) /* RSCAN_FROM_RSCAN0TMID65 */
+#define RSCAN_FROM_RSCAN0TMID66 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID66) /* RSCAN_FROM_RSCAN0TMID66 */
+#define RSCAN_FROM_RSCAN0TMID67 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID67) /* RSCAN_FROM_RSCAN0TMID67 */
+#define RSCAN_FROM_RSCAN0TMID68 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID68) /* RSCAN_FROM_RSCAN0TMID68 */
+#define RSCAN_FROM_RSCAN0TMID69 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID69) /* RSCAN_FROM_RSCAN0TMID69 */
+#define RSCAN_FROM_RSCAN0TMID70 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID70) /* RSCAN_FROM_RSCAN0TMID70 */
+#define RSCAN_FROM_RSCAN0TMID71 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID71) /* RSCAN_FROM_RSCAN0TMID71 */
+#define RSCAN_FROM_RSCAN0TMID72 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID72) /* RSCAN_FROM_RSCAN0TMID72 */
+#define RSCAN_FROM_RSCAN0TMID73 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID73) /* RSCAN_FROM_RSCAN0TMID73 */
+#define RSCAN_FROM_RSCAN0TMID74 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID74) /* RSCAN_FROM_RSCAN0TMID74 */
+#define RSCAN_FROM_RSCAN0TMID75 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID75) /* RSCAN_FROM_RSCAN0TMID75 */
+#define RSCAN_FROM_RSCAN0TMID76 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID76) /* RSCAN_FROM_RSCAN0TMID76 */
+#define RSCAN_FROM_RSCAN0TMID77 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID77) /* RSCAN_FROM_RSCAN0TMID77 */
+#define RSCAN_FROM_RSCAN0TMID78 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID78) /* RSCAN_FROM_RSCAN0TMID78 */
+#define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0RFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0RFIDm[ channel ]->RFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0RFIDm_COUNT  8
+#define RSCAN_FROM_RSCAN0RFIDm_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0RFID0 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID0) /* RSCAN_FROM_RSCAN0RFID0 */
+#define RSCAN_FROM_RSCAN0RFID1 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID1) /* RSCAN_FROM_RSCAN0RFID1 */
+#define RSCAN_FROM_RSCAN0RFID2 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID2) /* RSCAN_FROM_RSCAN0RFID2 */
+#define RSCAN_FROM_RSCAN0RFID3 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID3) /* RSCAN_FROM_RSCAN0RFID3 */
+#define RSCAN_FROM_RSCAN0RFID4 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID4) /* RSCAN_FROM_RSCAN0RFID4 */
+#define RSCAN_FROM_RSCAN0RFID5 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID5) /* RSCAN_FROM_RSCAN0RFID5 */
+#define RSCAN_FROM_RSCAN0RFID6 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID6) /* RSCAN_FROM_RSCAN0RFID6 */
+#define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0RMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0RMIDp[ channel ]->RMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0RMIDp_COUNT  80
+#define RSCAN_FROM_RSCAN0RMIDp_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \
+    &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \
+    &RSCAN_FROM_RSCAN0RMID16, &RSCAN_FROM_RSCAN0RMID17, &RSCAN_FROM_RSCAN0RMID18, &RSCAN_FROM_RSCAN0RMID19, &RSCAN_FROM_RSCAN0RMID20, &RSCAN_FROM_RSCAN0RMID21, &RSCAN_FROM_RSCAN0RMID22, &RSCAN_FROM_RSCAN0RMID23, \
+    &RSCAN_FROM_RSCAN0RMID24, &RSCAN_FROM_RSCAN0RMID25, &RSCAN_FROM_RSCAN0RMID26, &RSCAN_FROM_RSCAN0RMID27, &RSCAN_FROM_RSCAN0RMID28, &RSCAN_FROM_RSCAN0RMID29, &RSCAN_FROM_RSCAN0RMID30, &RSCAN_FROM_RSCAN0RMID31, \
+    &RSCAN_FROM_RSCAN0RMID32, &RSCAN_FROM_RSCAN0RMID33, &RSCAN_FROM_RSCAN0RMID34, &RSCAN_FROM_RSCAN0RMID35, &RSCAN_FROM_RSCAN0RMID36, &RSCAN_FROM_RSCAN0RMID37, &RSCAN_FROM_RSCAN0RMID38, &RSCAN_FROM_RSCAN0RMID39, \
+    &RSCAN_FROM_RSCAN0RMID40, &RSCAN_FROM_RSCAN0RMID41, &RSCAN_FROM_RSCAN0RMID42, &RSCAN_FROM_RSCAN0RMID43, &RSCAN_FROM_RSCAN0RMID44, &RSCAN_FROM_RSCAN0RMID45, &RSCAN_FROM_RSCAN0RMID46, &RSCAN_FROM_RSCAN0RMID47, \
+    &RSCAN_FROM_RSCAN0RMID48, &RSCAN_FROM_RSCAN0RMID49, &RSCAN_FROM_RSCAN0RMID50, &RSCAN_FROM_RSCAN0RMID51, &RSCAN_FROM_RSCAN0RMID52, &RSCAN_FROM_RSCAN0RMID53, &RSCAN_FROM_RSCAN0RMID54, &RSCAN_FROM_RSCAN0RMID55, \
+    &RSCAN_FROM_RSCAN0RMID56, &RSCAN_FROM_RSCAN0RMID57, &RSCAN_FROM_RSCAN0RMID58, &RSCAN_FROM_RSCAN0RMID59, &RSCAN_FROM_RSCAN0RMID60, &RSCAN_FROM_RSCAN0RMID61, &RSCAN_FROM_RSCAN0RMID62, &RSCAN_FROM_RSCAN0RMID63, \
+    &RSCAN_FROM_RSCAN0RMID64, &RSCAN_FROM_RSCAN0RMID65, &RSCAN_FROM_RSCAN0RMID66, &RSCAN_FROM_RSCAN0RMID67, &RSCAN_FROM_RSCAN0RMID68, &RSCAN_FROM_RSCAN0RMID69, &RSCAN_FROM_RSCAN0RMID70, &RSCAN_FROM_RSCAN0RMID71, \
+    &RSCAN_FROM_RSCAN0RMID72, &RSCAN_FROM_RSCAN0RMID73, &RSCAN_FROM_RSCAN0RMID74, &RSCAN_FROM_RSCAN0RMID75, &RSCAN_FROM_RSCAN0RMID76, &RSCAN_FROM_RSCAN0RMID77, &RSCAN_FROM_RSCAN0RMID78, &RSCAN_FROM_RSCAN0RMID79 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0RMID0 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID0) /* RSCAN_FROM_RSCAN0RMID0 */
+#define RSCAN_FROM_RSCAN0RMID1 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID1) /* RSCAN_FROM_RSCAN0RMID1 */
+#define RSCAN_FROM_RSCAN0RMID2 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID2) /* RSCAN_FROM_RSCAN0RMID2 */
+#define RSCAN_FROM_RSCAN0RMID3 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID3) /* RSCAN_FROM_RSCAN0RMID3 */
+#define RSCAN_FROM_RSCAN0RMID4 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID4) /* RSCAN_FROM_RSCAN0RMID4 */
+#define RSCAN_FROM_RSCAN0RMID5 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID5) /* RSCAN_FROM_RSCAN0RMID5 */
+#define RSCAN_FROM_RSCAN0RMID6 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID6) /* RSCAN_FROM_RSCAN0RMID6 */
+#define RSCAN_FROM_RSCAN0RMID7 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID7) /* RSCAN_FROM_RSCAN0RMID7 */
+#define RSCAN_FROM_RSCAN0RMID8 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID8) /* RSCAN_FROM_RSCAN0RMID8 */
+#define RSCAN_FROM_RSCAN0RMID9 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID9) /* RSCAN_FROM_RSCAN0RMID9 */
+#define RSCAN_FROM_RSCAN0RMID10 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID10) /* RSCAN_FROM_RSCAN0RMID10 */
+#define RSCAN_FROM_RSCAN0RMID11 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID11) /* RSCAN_FROM_RSCAN0RMID11 */
+#define RSCAN_FROM_RSCAN0RMID12 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID12) /* RSCAN_FROM_RSCAN0RMID12 */
+#define RSCAN_FROM_RSCAN0RMID13 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID13) /* RSCAN_FROM_RSCAN0RMID13 */
+#define RSCAN_FROM_RSCAN0RMID14 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID14) /* RSCAN_FROM_RSCAN0RMID14 */
+#define RSCAN_FROM_RSCAN0RMID15 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID15) /* RSCAN_FROM_RSCAN0RMID15 */
+#define RSCAN_FROM_RSCAN0RMID16 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID16) /* RSCAN_FROM_RSCAN0RMID16 */
+#define RSCAN_FROM_RSCAN0RMID17 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID17) /* RSCAN_FROM_RSCAN0RMID17 */
+#define RSCAN_FROM_RSCAN0RMID18 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID18) /* RSCAN_FROM_RSCAN0RMID18 */
+#define RSCAN_FROM_RSCAN0RMID19 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID19) /* RSCAN_FROM_RSCAN0RMID19 */
+#define RSCAN_FROM_RSCAN0RMID20 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID20) /* RSCAN_FROM_RSCAN0RMID20 */
+#define RSCAN_FROM_RSCAN0RMID21 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID21) /* RSCAN_FROM_RSCAN0RMID21 */
+#define RSCAN_FROM_RSCAN0RMID22 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID22) /* RSCAN_FROM_RSCAN0RMID22 */
+#define RSCAN_FROM_RSCAN0RMID23 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID23) /* RSCAN_FROM_RSCAN0RMID23 */
+#define RSCAN_FROM_RSCAN0RMID24 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID24) /* RSCAN_FROM_RSCAN0RMID24 */
+#define RSCAN_FROM_RSCAN0RMID25 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID25) /* RSCAN_FROM_RSCAN0RMID25 */
+#define RSCAN_FROM_RSCAN0RMID26 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID26) /* RSCAN_FROM_RSCAN0RMID26 */
+#define RSCAN_FROM_RSCAN0RMID27 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID27) /* RSCAN_FROM_RSCAN0RMID27 */
+#define RSCAN_FROM_RSCAN0RMID28 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID28) /* RSCAN_FROM_RSCAN0RMID28 */
+#define RSCAN_FROM_RSCAN0RMID29 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID29) /* RSCAN_FROM_RSCAN0RMID29 */
+#define RSCAN_FROM_RSCAN0RMID30 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID30) /* RSCAN_FROM_RSCAN0RMID30 */
+#define RSCAN_FROM_RSCAN0RMID31 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID31) /* RSCAN_FROM_RSCAN0RMID31 */
+#define RSCAN_FROM_RSCAN0RMID32 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID32) /* RSCAN_FROM_RSCAN0RMID32 */
+#define RSCAN_FROM_RSCAN0RMID33 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID33) /* RSCAN_FROM_RSCAN0RMID33 */
+#define RSCAN_FROM_RSCAN0RMID34 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID34) /* RSCAN_FROM_RSCAN0RMID34 */
+#define RSCAN_FROM_RSCAN0RMID35 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID35) /* RSCAN_FROM_RSCAN0RMID35 */
+#define RSCAN_FROM_RSCAN0RMID36 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID36) /* RSCAN_FROM_RSCAN0RMID36 */
+#define RSCAN_FROM_RSCAN0RMID37 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID37) /* RSCAN_FROM_RSCAN0RMID37 */
+#define RSCAN_FROM_RSCAN0RMID38 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID38) /* RSCAN_FROM_RSCAN0RMID38 */
+#define RSCAN_FROM_RSCAN0RMID39 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID39) /* RSCAN_FROM_RSCAN0RMID39 */
+#define RSCAN_FROM_RSCAN0RMID40 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID40) /* RSCAN_FROM_RSCAN0RMID40 */
+#define RSCAN_FROM_RSCAN0RMID41 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID41) /* RSCAN_FROM_RSCAN0RMID41 */
+#define RSCAN_FROM_RSCAN0RMID42 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID42) /* RSCAN_FROM_RSCAN0RMID42 */
+#define RSCAN_FROM_RSCAN0RMID43 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID43) /* RSCAN_FROM_RSCAN0RMID43 */
+#define RSCAN_FROM_RSCAN0RMID44 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID44) /* RSCAN_FROM_RSCAN0RMID44 */
+#define RSCAN_FROM_RSCAN0RMID45 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID45) /* RSCAN_FROM_RSCAN0RMID45 */
+#define RSCAN_FROM_RSCAN0RMID46 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID46) /* RSCAN_FROM_RSCAN0RMID46 */
+#define RSCAN_FROM_RSCAN0RMID47 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID47) /* RSCAN_FROM_RSCAN0RMID47 */
+#define RSCAN_FROM_RSCAN0RMID48 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID48) /* RSCAN_FROM_RSCAN0RMID48 */
+#define RSCAN_FROM_RSCAN0RMID49 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID49) /* RSCAN_FROM_RSCAN0RMID49 */
+#define RSCAN_FROM_RSCAN0RMID50 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID50) /* RSCAN_FROM_RSCAN0RMID50 */
+#define RSCAN_FROM_RSCAN0RMID51 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID51) /* RSCAN_FROM_RSCAN0RMID51 */
+#define RSCAN_FROM_RSCAN0RMID52 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID52) /* RSCAN_FROM_RSCAN0RMID52 */
+#define RSCAN_FROM_RSCAN0RMID53 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID53) /* RSCAN_FROM_RSCAN0RMID53 */
+#define RSCAN_FROM_RSCAN0RMID54 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID54) /* RSCAN_FROM_RSCAN0RMID54 */
+#define RSCAN_FROM_RSCAN0RMID55 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID55) /* RSCAN_FROM_RSCAN0RMID55 */
+#define RSCAN_FROM_RSCAN0RMID56 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID56) /* RSCAN_FROM_RSCAN0RMID56 */
+#define RSCAN_FROM_RSCAN0RMID57 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID57) /* RSCAN_FROM_RSCAN0RMID57 */
+#define RSCAN_FROM_RSCAN0RMID58 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID58) /* RSCAN_FROM_RSCAN0RMID58 */
+#define RSCAN_FROM_RSCAN0RMID59 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID59) /* RSCAN_FROM_RSCAN0RMID59 */
+#define RSCAN_FROM_RSCAN0RMID60 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID60) /* RSCAN_FROM_RSCAN0RMID60 */
+#define RSCAN_FROM_RSCAN0RMID61 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID61) /* RSCAN_FROM_RSCAN0RMID61 */
+#define RSCAN_FROM_RSCAN0RMID62 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID62) /* RSCAN_FROM_RSCAN0RMID62 */
+#define RSCAN_FROM_RSCAN0RMID63 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID63) /* RSCAN_FROM_RSCAN0RMID63 */
+#define RSCAN_FROM_RSCAN0RMID64 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID64) /* RSCAN_FROM_RSCAN0RMID64 */
+#define RSCAN_FROM_RSCAN0RMID65 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID65) /* RSCAN_FROM_RSCAN0RMID65 */
+#define RSCAN_FROM_RSCAN0RMID66 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID66) /* RSCAN_FROM_RSCAN0RMID66 */
+#define RSCAN_FROM_RSCAN0RMID67 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID67) /* RSCAN_FROM_RSCAN0RMID67 */
+#define RSCAN_FROM_RSCAN0RMID68 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID68) /* RSCAN_FROM_RSCAN0RMID68 */
+#define RSCAN_FROM_RSCAN0RMID69 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID69) /* RSCAN_FROM_RSCAN0RMID69 */
+#define RSCAN_FROM_RSCAN0RMID70 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID70) /* RSCAN_FROM_RSCAN0RMID70 */
+#define RSCAN_FROM_RSCAN0RMID71 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID71) /* RSCAN_FROM_RSCAN0RMID71 */
+#define RSCAN_FROM_RSCAN0RMID72 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID72) /* RSCAN_FROM_RSCAN0RMID72 */
+#define RSCAN_FROM_RSCAN0RMID73 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID73) /* RSCAN_FROM_RSCAN0RMID73 */
+#define RSCAN_FROM_RSCAN0RMID74 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID74) /* RSCAN_FROM_RSCAN0RMID74 */
+#define RSCAN_FROM_RSCAN0RMID75 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID75) /* RSCAN_FROM_RSCAN0RMID75 */
+#define RSCAN_FROM_RSCAN0RMID76 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID76) /* RSCAN_FROM_RSCAN0RMID76 */
+#define RSCAN_FROM_RSCAN0RMID77 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID77) /* RSCAN_FROM_RSCAN0RMID77 */
+#define RSCAN_FROM_RSCAN0RMID78 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID78) /* RSCAN_FROM_RSCAN0RMID78 */
+#define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0GAFLIDj */
+/*(Sample) value = RSCAN_FROM_RSCAN0GAFLIDj[ channel ]->GAFLIDj.UINT32; */
+#define RSCAN_FROM_RSCAN0GAFLIDj_COUNT  16
+#define RSCAN_FROM_RSCAN0GAFLIDj_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \
+    &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0GAFLID0 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID0) /* RSCAN_FROM_RSCAN0GAFLID0 */
+#define RSCAN_FROM_RSCAN0GAFLID1 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID1) /* RSCAN_FROM_RSCAN0GAFLID1 */
+#define RSCAN_FROM_RSCAN0GAFLID2 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID2) /* RSCAN_FROM_RSCAN0GAFLID2 */
+#define RSCAN_FROM_RSCAN0GAFLID3 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID3) /* RSCAN_FROM_RSCAN0GAFLID3 */
+#define RSCAN_FROM_RSCAN0GAFLID4 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID4) /* RSCAN_FROM_RSCAN0GAFLID4 */
+#define RSCAN_FROM_RSCAN0GAFLID5 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID5) /* RSCAN_FROM_RSCAN0GAFLID5 */
+#define RSCAN_FROM_RSCAN0GAFLID6 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID6) /* RSCAN_FROM_RSCAN0GAFLID6 */
+#define RSCAN_FROM_RSCAN0GAFLID7 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID7) /* RSCAN_FROM_RSCAN0GAFLID7 */
+#define RSCAN_FROM_RSCAN0GAFLID8 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID8) /* RSCAN_FROM_RSCAN0GAFLID8 */
+#define RSCAN_FROM_RSCAN0GAFLID9 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID9) /* RSCAN_FROM_RSCAN0GAFLID9 */
+#define RSCAN_FROM_RSCAN0GAFLID10 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID10) /* RSCAN_FROM_RSCAN0GAFLID10 */
+#define RSCAN_FROM_RSCAN0GAFLID11 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID11) /* RSCAN_FROM_RSCAN0GAFLID11 */
+#define RSCAN_FROM_RSCAN0GAFLID12 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID12) /* RSCAN_FROM_RSCAN0GAFLID12 */
+#define RSCAN_FROM_RSCAN0GAFLID13 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID13) /* RSCAN_FROM_RSCAN0GAFLID13 */
+#define RSCAN_FROM_RSCAN0GAFLID14 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID14) /* RSCAN_FROM_RSCAN0GAFLID14 */
+#define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */
+
+
+/* Channnel array defines of RSCAN_FROM_RSCAN0CnCFG */
+/*(Sample) value = RSCAN_FROM_RSCAN0CnCFG[ channel ]->CnCFG.UINT32; */
+#define RSCAN_FROM_RSCAN0CnCFG_COUNT  5
+#define RSCAN_FROM_RSCAN0CnCFG_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define RSCAN_FROM_RSCAN0C0CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C0CFG) /* RSCAN_FROM_RSCAN0C0CFG */
+#define RSCAN_FROM_RSCAN0C1CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C1CFG) /* RSCAN_FROM_RSCAN0C1CFG */
+#define RSCAN_FROM_RSCAN0C2CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C2CFG) /* RSCAN_FROM_RSCAN0C2CFG */
+#define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */
+#define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */
+
+/* End of channnel array defines of RSCAN0 */
+
+
+#define RSCAN0C0CFG RSCAN0.C0CFG.UINT32
+#define RSCAN0C0CFGL RSCAN0.C0CFG.UINT16[L]
+#define RSCAN0C0CFGLL RSCAN0.C0CFG.UINT8[LL]
+#define RSCAN0C0CFGLH RSCAN0.C0CFG.UINT8[LH]
+#define RSCAN0C0CFGH RSCAN0.C0CFG.UINT16[H]
+#define RSCAN0C0CFGHL RSCAN0.C0CFG.UINT8[HL]
+#define RSCAN0C0CFGHH RSCAN0.C0CFG.UINT8[HH]
+#define RSCAN0C0CTR RSCAN0.C0CTR.UINT32
+#define RSCAN0C0CTRL RSCAN0.C0CTR.UINT16[L]
+#define RSCAN0C0CTRLL RSCAN0.C0CTR.UINT8[LL]
+#define RSCAN0C0CTRLH RSCAN0.C0CTR.UINT8[LH]
+#define RSCAN0C0CTRH RSCAN0.C0CTR.UINT16[H]
+#define RSCAN0C0CTRHL RSCAN0.C0CTR.UINT8[HL]
+#define RSCAN0C0CTRHH RSCAN0.C0CTR.UINT8[HH]
+#define RSCAN0C0STS RSCAN0.C0STS.UINT32
+#define RSCAN0C0STSL RSCAN0.C0STS.UINT16[L]
+#define RSCAN0C0STSLL RSCAN0.C0STS.UINT8[LL]
+#define RSCAN0C0STSLH RSCAN0.C0STS.UINT8[LH]
+#define RSCAN0C0STSH RSCAN0.C0STS.UINT16[H]
+#define RSCAN0C0STSHL RSCAN0.C0STS.UINT8[HL]
+#define RSCAN0C0STSHH RSCAN0.C0STS.UINT8[HH]
+#define RSCAN0C0ERFL RSCAN0.C0ERFL.UINT32
+#define RSCAN0C0ERFLL RSCAN0.C0ERFL.UINT16[L]
+#define RSCAN0C0ERFLLL RSCAN0.C0ERFL.UINT8[LL]
+#define RSCAN0C0ERFLLH RSCAN0.C0ERFL.UINT8[LH]
+#define RSCAN0C0ERFLH RSCAN0.C0ERFL.UINT16[H]
+#define RSCAN0C0ERFLHL RSCAN0.C0ERFL.UINT8[HL]
+#define RSCAN0C0ERFLHH RSCAN0.C0ERFL.UINT8[HH]
+#define RSCAN0C1CFG RSCAN0.C1CFG.UINT32
+#define RSCAN0C1CFGL RSCAN0.C1CFG.UINT16[L]
+#define RSCAN0C1CFGLL RSCAN0.C1CFG.UINT8[LL]
+#define RSCAN0C1CFGLH RSCAN0.C1CFG.UINT8[LH]
+#define RSCAN0C1CFGH RSCAN0.C1CFG.UINT16[H]
+#define RSCAN0C1CFGHL RSCAN0.C1CFG.UINT8[HL]
+#define RSCAN0C1CFGHH RSCAN0.C1CFG.UINT8[HH]
+#define RSCAN0C1CTR RSCAN0.C1CTR.UINT32
+#define RSCAN0C1CTRL RSCAN0.C1CTR.UINT16[L]
+#define RSCAN0C1CTRLL RSCAN0.C1CTR.UINT8[LL]
+#define RSCAN0C1CTRLH RSCAN0.C1CTR.UINT8[LH]
+#define RSCAN0C1CTRH RSCAN0.C1CTR.UINT16[H]
+#define RSCAN0C1CTRHL RSCAN0.C1CTR.UINT8[HL]
+#define RSCAN0C1CTRHH RSCAN0.C1CTR.UINT8[HH]
+#define RSCAN0C1STS RSCAN0.C1STS.UINT32
+#define RSCAN0C1STSL RSCAN0.C1STS.UINT16[L]
+#define RSCAN0C1STSLL RSCAN0.C1STS.UINT8[LL]
+#define RSCAN0C1STSLH RSCAN0.C1STS.UINT8[LH]
+#define RSCAN0C1STSH RSCAN0.C1STS.UINT16[H]
+#define RSCAN0C1STSHL RSCAN0.C1STS.UINT8[HL]
+#define RSCAN0C1STSHH RSCAN0.C1STS.UINT8[HH]
+#define RSCAN0C1ERFL RSCAN0.C1ERFL.UINT32
+#define RSCAN0C1ERFLL RSCAN0.C1ERFL.UINT16[L]
+#define RSCAN0C1ERFLLL RSCAN0.C1ERFL.UINT8[LL]
+#define RSCAN0C1ERFLLH RSCAN0.C1ERFL.UINT8[LH]
+#define RSCAN0C1ERFLH RSCAN0.C1ERFL.UINT16[H]
+#define RSCAN0C1ERFLHL RSCAN0.C1ERFL.UINT8[HL]
+#define RSCAN0C1ERFLHH RSCAN0.C1ERFL.UINT8[HH]
+#define RSCAN0C2CFG RSCAN0.C2CFG.UINT32
+#define RSCAN0C2CFGL RSCAN0.C2CFG.UINT16[L]
+#define RSCAN0C2CFGLL RSCAN0.C2CFG.UINT8[LL]
+#define RSCAN0C2CFGLH RSCAN0.C2CFG.UINT8[LH]
+#define RSCAN0C2CFGH RSCAN0.C2CFG.UINT16[H]
+#define RSCAN0C2CFGHL RSCAN0.C2CFG.UINT8[HL]
+#define RSCAN0C2CFGHH RSCAN0.C2CFG.UINT8[HH]
+#define RSCAN0C2CTR RSCAN0.C2CTR.UINT32
+#define RSCAN0C2CTRL RSCAN0.C2CTR.UINT16[L]
+#define RSCAN0C2CTRLL RSCAN0.C2CTR.UINT8[LL]
+#define RSCAN0C2CTRLH RSCAN0.C2CTR.UINT8[LH]
+#define RSCAN0C2CTRH RSCAN0.C2CTR.UINT16[H]
+#define RSCAN0C2CTRHL RSCAN0.C2CTR.UINT8[HL]
+#define RSCAN0C2CTRHH RSCAN0.C2CTR.UINT8[HH]
+#define RSCAN0C2STS RSCAN0.C2STS.UINT32
+#define RSCAN0C2STSL RSCAN0.C2STS.UINT16[L]
+#define RSCAN0C2STSLL RSCAN0.C2STS.UINT8[LL]
+#define RSCAN0C2STSLH RSCAN0.C2STS.UINT8[LH]
+#define RSCAN0C2STSH RSCAN0.C2STS.UINT16[H]
+#define RSCAN0C2STSHL RSCAN0.C2STS.UINT8[HL]
+#define RSCAN0C2STSHH RSCAN0.C2STS.UINT8[HH]
+#define RSCAN0C2ERFL RSCAN0.C2ERFL.UINT32
+#define RSCAN0C2ERFLL RSCAN0.C2ERFL.UINT16[L]
+#define RSCAN0C2ERFLLL RSCAN0.C2ERFL.UINT8[LL]
+#define RSCAN0C2ERFLLH RSCAN0.C2ERFL.UINT8[LH]
+#define RSCAN0C2ERFLH RSCAN0.C2ERFL.UINT16[H]
+#define RSCAN0C2ERFLHL RSCAN0.C2ERFL.UINT8[HL]
+#define RSCAN0C2ERFLHH RSCAN0.C2ERFL.UINT8[HH]
+#define RSCAN0C3CFG RSCAN0.C3CFG.UINT32
+#define RSCAN0C3CFGL RSCAN0.C3CFG.UINT16[L]
+#define RSCAN0C3CFGLL RSCAN0.C3CFG.UINT8[LL]
+#define RSCAN0C3CFGLH RSCAN0.C3CFG.UINT8[LH]
+#define RSCAN0C3CFGH RSCAN0.C3CFG.UINT16[H]
+#define RSCAN0C3CFGHL RSCAN0.C3CFG.UINT8[HL]
+#define RSCAN0C3CFGHH RSCAN0.C3CFG.UINT8[HH]
+#define RSCAN0C3CTR RSCAN0.C3CTR.UINT32
+#define RSCAN0C3CTRL RSCAN0.C3CTR.UINT16[L]
+#define RSCAN0C3CTRLL RSCAN0.C3CTR.UINT8[LL]
+#define RSCAN0C3CTRLH RSCAN0.C3CTR.UINT8[LH]
+#define RSCAN0C3CTRH RSCAN0.C3CTR.UINT16[H]
+#define RSCAN0C3CTRHL RSCAN0.C3CTR.UINT8[HL]
+#define RSCAN0C3CTRHH RSCAN0.C3CTR.UINT8[HH]
+#define RSCAN0C3STS RSCAN0.C3STS.UINT32
+#define RSCAN0C3STSL RSCAN0.C3STS.UINT16[L]
+#define RSCAN0C3STSLL RSCAN0.C3STS.UINT8[LL]
+#define RSCAN0C3STSLH RSCAN0.C3STS.UINT8[LH]
+#define RSCAN0C3STSH RSCAN0.C3STS.UINT16[H]
+#define RSCAN0C3STSHL RSCAN0.C3STS.UINT8[HL]
+#define RSCAN0C3STSHH RSCAN0.C3STS.UINT8[HH]
+#define RSCAN0C3ERFL RSCAN0.C3ERFL.UINT32
+#define RSCAN0C3ERFLL RSCAN0.C3ERFL.UINT16[L]
+#define RSCAN0C3ERFLLL RSCAN0.C3ERFL.UINT8[LL]
+#define RSCAN0C3ERFLLH RSCAN0.C3ERFL.UINT8[LH]
+#define RSCAN0C3ERFLH RSCAN0.C3ERFL.UINT16[H]
+#define RSCAN0C3ERFLHL RSCAN0.C3ERFL.UINT8[HL]
+#define RSCAN0C3ERFLHH RSCAN0.C3ERFL.UINT8[HH]
+#define RSCAN0C4CFG RSCAN0.C4CFG.UINT32
+#define RSCAN0C4CFGL RSCAN0.C4CFG.UINT16[L]
+#define RSCAN0C4CFGLL RSCAN0.C4CFG.UINT8[LL]
+#define RSCAN0C4CFGLH RSCAN0.C4CFG.UINT8[LH]
+#define RSCAN0C4CFGH RSCAN0.C4CFG.UINT16[H]
+#define RSCAN0C4CFGHL RSCAN0.C4CFG.UINT8[HL]
+#define RSCAN0C4CFGHH RSCAN0.C4CFG.UINT8[HH]
+#define RSCAN0C4CTR RSCAN0.C4CTR.UINT32
+#define RSCAN0C4CTRL RSCAN0.C4CTR.UINT16[L]
+#define RSCAN0C4CTRLL RSCAN0.C4CTR.UINT8[LL]
+#define RSCAN0C4CTRLH RSCAN0.C4CTR.UINT8[LH]
+#define RSCAN0C4CTRH RSCAN0.C4CTR.UINT16[H]
+#define RSCAN0C4CTRHL RSCAN0.C4CTR.UINT8[HL]
+#define RSCAN0C4CTRHH RSCAN0.C4CTR.UINT8[HH]
+#define RSCAN0C4STS RSCAN0.C4STS.UINT32
+#define RSCAN0C4STSL RSCAN0.C4STS.UINT16[L]
+#define RSCAN0C4STSLL RSCAN0.C4STS.UINT8[LL]
+#define RSCAN0C4STSLH RSCAN0.C4STS.UINT8[LH]
+#define RSCAN0C4STSH RSCAN0.C4STS.UINT16[H]
+#define RSCAN0C4STSHL RSCAN0.C4STS.UINT8[HL]
+#define RSCAN0C4STSHH RSCAN0.C4STS.UINT8[HH]
+#define RSCAN0C4ERFL RSCAN0.C4ERFL.UINT32
+#define RSCAN0C4ERFLL RSCAN0.C4ERFL.UINT16[L]
+#define RSCAN0C4ERFLLL RSCAN0.C4ERFL.UINT8[LL]
+#define RSCAN0C4ERFLLH RSCAN0.C4ERFL.UINT8[LH]
+#define RSCAN0C4ERFLH RSCAN0.C4ERFL.UINT16[H]
+#define RSCAN0C4ERFLHL RSCAN0.C4ERFL.UINT8[HL]
+#define RSCAN0C4ERFLHH RSCAN0.C4ERFL.UINT8[HH]
+#define RSCAN0GCFG RSCAN0.GCFG.UINT32
+#define RSCAN0GCFGL RSCAN0.GCFG.UINT16[L]
+#define RSCAN0GCFGLL RSCAN0.GCFG.UINT8[LL]
+#define RSCAN0GCFGLH RSCAN0.GCFG.UINT8[LH]
+#define RSCAN0GCFGH RSCAN0.GCFG.UINT16[H]
+#define RSCAN0GCFGHL RSCAN0.GCFG.UINT8[HL]
+#define RSCAN0GCFGHH RSCAN0.GCFG.UINT8[HH]
+#define RSCAN0GCTR RSCAN0.GCTR.UINT32
+#define RSCAN0GCTRL RSCAN0.GCTR.UINT16[L]
+#define RSCAN0GCTRLL RSCAN0.GCTR.UINT8[LL]
+#define RSCAN0GCTRLH RSCAN0.GCTR.UINT8[LH]
+#define RSCAN0GCTRH RSCAN0.GCTR.UINT16[H]
+#define RSCAN0GCTRHL RSCAN0.GCTR.UINT8[HL]
+#define RSCAN0GCTRHH RSCAN0.GCTR.UINT8[HH]
+#define RSCAN0GSTS RSCAN0.GSTS.UINT32
+#define RSCAN0GSTSL RSCAN0.GSTS.UINT16[L]
+#define RSCAN0GSTSLL RSCAN0.GSTS.UINT8[LL]
+#define RSCAN0GSTSLH RSCAN0.GSTS.UINT8[LH]
+#define RSCAN0GSTSH RSCAN0.GSTS.UINT16[H]
+#define RSCAN0GSTSHL RSCAN0.GSTS.UINT8[HL]
+#define RSCAN0GSTSHH RSCAN0.GSTS.UINT8[HH]
+#define RSCAN0GERFL RSCAN0.GERFL.UINT32
+#define RSCAN0GERFLL RSCAN0.GERFL.UINT16[L]
+#define RSCAN0GERFLLL RSCAN0.GERFL.UINT8[LL]
+#define RSCAN0GERFLLH RSCAN0.GERFL.UINT8[LH]
+#define RSCAN0GERFLH RSCAN0.GERFL.UINT16[H]
+#define RSCAN0GERFLHL RSCAN0.GERFL.UINT8[HL]
+#define RSCAN0GERFLHH RSCAN0.GERFL.UINT8[HH]
+#define RSCAN0GTSC RSCAN0.GTSC.UINT32
+#define RSCAN0GTSCL RSCAN0.GTSC.UINT16[L]
+#define RSCAN0GTSCH RSCAN0.GTSC.UINT16[H]
+#define RSCAN0GAFLECTR RSCAN0.GAFLECTR.UINT32
+#define RSCAN0GAFLECTRL RSCAN0.GAFLECTR.UINT16[L]
+#define RSCAN0GAFLECTRLL RSCAN0.GAFLECTR.UINT8[LL]
+#define RSCAN0GAFLECTRLH RSCAN0.GAFLECTR.UINT8[LH]
+#define RSCAN0GAFLECTRH RSCAN0.GAFLECTR.UINT16[H]
+#define RSCAN0GAFLECTRHL RSCAN0.GAFLECTR.UINT8[HL]
+#define RSCAN0GAFLECTRHH RSCAN0.GAFLECTR.UINT8[HH]
+#define RSCAN0GAFLCFG0 RSCAN0.GAFLCFG0.UINT32
+#define RSCAN0GAFLCFG0L RSCAN0.GAFLCFG0.UINT16[L]
+#define RSCAN0GAFLCFG0LL RSCAN0.GAFLCFG0.UINT8[LL]
+#define RSCAN0GAFLCFG0LH RSCAN0.GAFLCFG0.UINT8[LH]
+#define RSCAN0GAFLCFG0H RSCAN0.GAFLCFG0.UINT16[H]
+#define RSCAN0GAFLCFG0HL RSCAN0.GAFLCFG0.UINT8[HL]
+#define RSCAN0GAFLCFG0HH RSCAN0.GAFLCFG0.UINT8[HH]
+#define RSCAN0GAFLCFG1 RSCAN0.GAFLCFG1.UINT32
+#define RSCAN0GAFLCFG1L RSCAN0.GAFLCFG1.UINT16[L]
+#define RSCAN0GAFLCFG1LL RSCAN0.GAFLCFG1.UINT8[LL]
+#define RSCAN0GAFLCFG1LH RSCAN0.GAFLCFG1.UINT8[LH]
+#define RSCAN0GAFLCFG1H RSCAN0.GAFLCFG1.UINT16[H]
+#define RSCAN0GAFLCFG1HL RSCAN0.GAFLCFG1.UINT8[HL]
+#define RSCAN0GAFLCFG1HH RSCAN0.GAFLCFG1.UINT8[HH]
+#define RSCAN0RMNB RSCAN0.RMNB.UINT32
+#define RSCAN0RMNBL RSCAN0.RMNB.UINT16[L]
+#define RSCAN0RMNBLL RSCAN0.RMNB.UINT8[LL]
+#define RSCAN0RMNBLH RSCAN0.RMNB.UINT8[LH]
+#define RSCAN0RMNBH RSCAN0.RMNB.UINT16[H]
+#define RSCAN0RMNBHL RSCAN0.RMNB.UINT8[HL]
+#define RSCAN0RMNBHH RSCAN0.RMNB.UINT8[HH]
+#define RSCAN0RMND0 RSCAN0.RMND0.UINT32
+#define RSCAN0RMND0L RSCAN0.RMND0.UINT16[L]
+#define RSCAN0RMND0LL RSCAN0.RMND0.UINT8[LL]
+#define RSCAN0RMND0LH RSCAN0.RMND0.UINT8[LH]
+#define RSCAN0RMND0H RSCAN0.RMND0.UINT16[H]
+#define RSCAN0RMND0HL RSCAN0.RMND0.UINT8[HL]
+#define RSCAN0RMND0HH RSCAN0.RMND0.UINT8[HH]
+#define RSCAN0RMND1 RSCAN0.RMND1.UINT32
+#define RSCAN0RMND1L RSCAN0.RMND1.UINT16[L]
+#define RSCAN0RMND1LL RSCAN0.RMND1.UINT8[LL]
+#define RSCAN0RMND1LH RSCAN0.RMND1.UINT8[LH]
+#define RSCAN0RMND1H RSCAN0.RMND1.UINT16[H]
+#define RSCAN0RMND1HL RSCAN0.RMND1.UINT8[HL]
+#define RSCAN0RMND1HH RSCAN0.RMND1.UINT8[HH]
+#define RSCAN0RMND2 RSCAN0.RMND2.UINT32
+#define RSCAN0RMND2L RSCAN0.RMND2.UINT16[L]
+#define RSCAN0RMND2LL RSCAN0.RMND2.UINT8[LL]
+#define RSCAN0RMND2LH RSCAN0.RMND2.UINT8[LH]
+#define RSCAN0RMND2H RSCAN0.RMND2.UINT16[H]
+#define RSCAN0RMND2HL RSCAN0.RMND2.UINT8[HL]
+#define RSCAN0RMND2HH RSCAN0.RMND2.UINT8[HH]
+#define RSCAN0RFCC0 RSCAN0.RFCC0.UINT32
+#define RSCAN0RFCC0L RSCAN0.RFCC0.UINT16[L]
+#define RSCAN0RFCC0LL RSCAN0.RFCC0.UINT8[LL]
+#define RSCAN0RFCC0LH RSCAN0.RFCC0.UINT8[LH]
+#define RSCAN0RFCC0H RSCAN0.RFCC0.UINT16[H]
+#define RSCAN0RFCC0HL RSCAN0.RFCC0.UINT8[HL]
+#define RSCAN0RFCC0HH RSCAN0.RFCC0.UINT8[HH]
+#define RSCAN0RFCC1 RSCAN0.RFCC1.UINT32
+#define RSCAN0RFCC1L RSCAN0.RFCC1.UINT16[L]
+#define RSCAN0RFCC1LL RSCAN0.RFCC1.UINT8[LL]
+#define RSCAN0RFCC1LH RSCAN0.RFCC1.UINT8[LH]
+#define RSCAN0RFCC1H RSCAN0.RFCC1.UINT16[H]
+#define RSCAN0RFCC1HL RSCAN0.RFCC1.UINT8[HL]
+#define RSCAN0RFCC1HH RSCAN0.RFCC1.UINT8[HH]
+#define RSCAN0RFCC2 RSCAN0.RFCC2.UINT32
+#define RSCAN0RFCC2L RSCAN0.RFCC2.UINT16[L]
+#define RSCAN0RFCC2LL RSCAN0.RFCC2.UINT8[LL]
+#define RSCAN0RFCC2LH RSCAN0.RFCC2.UINT8[LH]
+#define RSCAN0RFCC2H RSCAN0.RFCC2.UINT16[H]
+#define RSCAN0RFCC2HL RSCAN0.RFCC2.UINT8[HL]
+#define RSCAN0RFCC2HH RSCAN0.RFCC2.UINT8[HH]
+#define RSCAN0RFCC3 RSCAN0.RFCC3.UINT32
+#define RSCAN0RFCC3L RSCAN0.RFCC3.UINT16[L]
+#define RSCAN0RFCC3LL RSCAN0.RFCC3.UINT8[LL]
+#define RSCAN0RFCC3LH RSCAN0.RFCC3.UINT8[LH]
+#define RSCAN0RFCC3H RSCAN0.RFCC3.UINT16[H]
+#define RSCAN0RFCC3HL RSCAN0.RFCC3.UINT8[HL]
+#define RSCAN0RFCC3HH RSCAN0.RFCC3.UINT8[HH]
+#define RSCAN0RFCC4 RSCAN0.RFCC4.UINT32
+#define RSCAN0RFCC4L RSCAN0.RFCC4.UINT16[L]
+#define RSCAN0RFCC4LL RSCAN0.RFCC4.UINT8[LL]
+#define RSCAN0RFCC4LH RSCAN0.RFCC4.UINT8[LH]
+#define RSCAN0RFCC4H RSCAN0.RFCC4.UINT16[H]
+#define RSCAN0RFCC4HL RSCAN0.RFCC4.UINT8[HL]
+#define RSCAN0RFCC4HH RSCAN0.RFCC4.UINT8[HH]
+#define RSCAN0RFCC5 RSCAN0.RFCC5.UINT32
+#define RSCAN0RFCC5L RSCAN0.RFCC5.UINT16[L]
+#define RSCAN0RFCC5LL RSCAN0.RFCC5.UINT8[LL]
+#define RSCAN0RFCC5LH RSCAN0.RFCC5.UINT8[LH]
+#define RSCAN0RFCC5H RSCAN0.RFCC5.UINT16[H]
+#define RSCAN0RFCC5HL RSCAN0.RFCC5.UINT8[HL]
+#define RSCAN0RFCC5HH RSCAN0.RFCC5.UINT8[HH]
+#define RSCAN0RFCC6 RSCAN0.RFCC6.UINT32
+#define RSCAN0RFCC6L RSCAN0.RFCC6.UINT16[L]
+#define RSCAN0RFCC6LL RSCAN0.RFCC6.UINT8[LL]
+#define RSCAN0RFCC6LH RSCAN0.RFCC6.UINT8[LH]
+#define RSCAN0RFCC6H RSCAN0.RFCC6.UINT16[H]
+#define RSCAN0RFCC6HL RSCAN0.RFCC6.UINT8[HL]
+#define RSCAN0RFCC6HH RSCAN0.RFCC6.UINT8[HH]
+#define RSCAN0RFCC7 RSCAN0.RFCC7.UINT32
+#define RSCAN0RFCC7L RSCAN0.RFCC7.UINT16[L]
+#define RSCAN0RFCC7LL RSCAN0.RFCC7.UINT8[LL]
+#define RSCAN0RFCC7LH RSCAN0.RFCC7.UINT8[LH]
+#define RSCAN0RFCC7H RSCAN0.RFCC7.UINT16[H]
+#define RSCAN0RFCC7HL RSCAN0.RFCC7.UINT8[HL]
+#define RSCAN0RFCC7HH RSCAN0.RFCC7.UINT8[HH]
+#define RSCAN0RFSTS0 RSCAN0.RFSTS0.UINT32
+#define RSCAN0RFSTS0L RSCAN0.RFSTS0.UINT16[L]
+#define RSCAN0RFSTS0LL RSCAN0.RFSTS0.UINT8[LL]
+#define RSCAN0RFSTS0LH RSCAN0.RFSTS0.UINT8[LH]
+#define RSCAN0RFSTS0H RSCAN0.RFSTS0.UINT16[H]
+#define RSCAN0RFSTS0HL RSCAN0.RFSTS0.UINT8[HL]
+#define RSCAN0RFSTS0HH RSCAN0.RFSTS0.UINT8[HH]
+#define RSCAN0RFSTS1 RSCAN0.RFSTS1.UINT32
+#define RSCAN0RFSTS1L RSCAN0.RFSTS1.UINT16[L]
+#define RSCAN0RFSTS1LL RSCAN0.RFSTS1.UINT8[LL]
+#define RSCAN0RFSTS1LH RSCAN0.RFSTS1.UINT8[LH]
+#define RSCAN0RFSTS1H RSCAN0.RFSTS1.UINT16[H]
+#define RSCAN0RFSTS1HL RSCAN0.RFSTS1.UINT8[HL]
+#define RSCAN0RFSTS1HH RSCAN0.RFSTS1.UINT8[HH]
+#define RSCAN0RFSTS2 RSCAN0.RFSTS2.UINT32
+#define RSCAN0RFSTS2L RSCAN0.RFSTS2.UINT16[L]
+#define RSCAN0RFSTS2LL RSCAN0.RFSTS2.UINT8[LL]
+#define RSCAN0RFSTS2LH RSCAN0.RFSTS2.UINT8[LH]
+#define RSCAN0RFSTS2H RSCAN0.RFSTS2.UINT16[H]
+#define RSCAN0RFSTS2HL RSCAN0.RFSTS2.UINT8[HL]
+#define RSCAN0RFSTS2HH RSCAN0.RFSTS2.UINT8[HH]
+#define RSCAN0RFSTS3 RSCAN0.RFSTS3.UINT32
+#define RSCAN0RFSTS3L RSCAN0.RFSTS3.UINT16[L]
+#define RSCAN0RFSTS3LL RSCAN0.RFSTS3.UINT8[LL]
+#define RSCAN0RFSTS3LH RSCAN0.RFSTS3.UINT8[LH]
+#define RSCAN0RFSTS3H RSCAN0.RFSTS3.UINT16[H]
+#define RSCAN0RFSTS3HL RSCAN0.RFSTS3.UINT8[HL]
+#define RSCAN0RFSTS3HH RSCAN0.RFSTS3.UINT8[HH]
+#define RSCAN0RFSTS4 RSCAN0.RFSTS4.UINT32
+#define RSCAN0RFSTS4L RSCAN0.RFSTS4.UINT16[L]
+#define RSCAN0RFSTS4LL RSCAN0.RFSTS4.UINT8[LL]
+#define RSCAN0RFSTS4LH RSCAN0.RFSTS4.UINT8[LH]
+#define RSCAN0RFSTS4H RSCAN0.RFSTS4.UINT16[H]
+#define RSCAN0RFSTS4HL RSCAN0.RFSTS4.UINT8[HL]
+#define RSCAN0RFSTS4HH RSCAN0.RFSTS4.UINT8[HH]
+#define RSCAN0RFSTS5 RSCAN0.RFSTS5.UINT32
+#define RSCAN0RFSTS5L RSCAN0.RFSTS5.UINT16[L]
+#define RSCAN0RFSTS5LL RSCAN0.RFSTS5.UINT8[LL]
+#define RSCAN0RFSTS5LH RSCAN0.RFSTS5.UINT8[LH]
+#define RSCAN0RFSTS5H RSCAN0.RFSTS5.UINT16[H]
+#define RSCAN0RFSTS5HL RSCAN0.RFSTS5.UINT8[HL]
+#define RSCAN0RFSTS5HH RSCAN0.RFSTS5.UINT8[HH]
+#define RSCAN0RFSTS6 RSCAN0.RFSTS6.UINT32
+#define RSCAN0RFSTS6L RSCAN0.RFSTS6.UINT16[L]
+#define RSCAN0RFSTS6LL RSCAN0.RFSTS6.UINT8[LL]
+#define RSCAN0RFSTS6LH RSCAN0.RFSTS6.UINT8[LH]
+#define RSCAN0RFSTS6H RSCAN0.RFSTS6.UINT16[H]
+#define RSCAN0RFSTS6HL RSCAN0.RFSTS6.UINT8[HL]
+#define RSCAN0RFSTS6HH RSCAN0.RFSTS6.UINT8[HH]
+#define RSCAN0RFSTS7 RSCAN0.RFSTS7.UINT32
+#define RSCAN0RFSTS7L RSCAN0.RFSTS7.UINT16[L]
+#define RSCAN0RFSTS7LL RSCAN0.RFSTS7.UINT8[LL]
+#define RSCAN0RFSTS7LH RSCAN0.RFSTS7.UINT8[LH]
+#define RSCAN0RFSTS7H RSCAN0.RFSTS7.UINT16[H]
+#define RSCAN0RFSTS7HL RSCAN0.RFSTS7.UINT8[HL]
+#define RSCAN0RFSTS7HH RSCAN0.RFSTS7.UINT8[HH]
+#define RSCAN0RFPCTR0 RSCAN0.RFPCTR0.UINT32
+#define RSCAN0RFPCTR0L RSCAN0.RFPCTR0.UINT16[L]
+#define RSCAN0RFPCTR0LL RSCAN0.RFPCTR0.UINT8[LL]
+#define RSCAN0RFPCTR0LH RSCAN0.RFPCTR0.UINT8[LH]
+#define RSCAN0RFPCTR0H RSCAN0.RFPCTR0.UINT16[H]
+#define RSCAN0RFPCTR0HL RSCAN0.RFPCTR0.UINT8[HL]
+#define RSCAN0RFPCTR0HH RSCAN0.RFPCTR0.UINT8[HH]
+#define RSCAN0RFPCTR1 RSCAN0.RFPCTR1.UINT32
+#define RSCAN0RFPCTR1L RSCAN0.RFPCTR1.UINT16[L]
+#define RSCAN0RFPCTR1LL RSCAN0.RFPCTR1.UINT8[LL]
+#define RSCAN0RFPCTR1LH RSCAN0.RFPCTR1.UINT8[LH]
+#define RSCAN0RFPCTR1H RSCAN0.RFPCTR1.UINT16[H]
+#define RSCAN0RFPCTR1HL RSCAN0.RFPCTR1.UINT8[HL]
+#define RSCAN0RFPCTR1HH RSCAN0.RFPCTR1.UINT8[HH]
+#define RSCAN0RFPCTR2 RSCAN0.RFPCTR2.UINT32
+#define RSCAN0RFPCTR2L RSCAN0.RFPCTR2.UINT16[L]
+#define RSCAN0RFPCTR2LL RSCAN0.RFPCTR2.UINT8[LL]
+#define RSCAN0RFPCTR2LH RSCAN0.RFPCTR2.UINT8[LH]
+#define RSCAN0RFPCTR2H RSCAN0.RFPCTR2.UINT16[H]
+#define RSCAN0RFPCTR2HL RSCAN0.RFPCTR2.UINT8[HL]
+#define RSCAN0RFPCTR2HH RSCAN0.RFPCTR2.UINT8[HH]
+#define RSCAN0RFPCTR3 RSCAN0.RFPCTR3.UINT32
+#define RSCAN0RFPCTR3L RSCAN0.RFPCTR3.UINT16[L]
+#define RSCAN0RFPCTR3LL RSCAN0.RFPCTR3.UINT8[LL]
+#define RSCAN0RFPCTR3LH RSCAN0.RFPCTR3.UINT8[LH]
+#define RSCAN0RFPCTR3H RSCAN0.RFPCTR3.UINT16[H]
+#define RSCAN0RFPCTR3HL RSCAN0.RFPCTR3.UINT8[HL]
+#define RSCAN0RFPCTR3HH RSCAN0.RFPCTR3.UINT8[HH]
+#define RSCAN0RFPCTR4 RSCAN0.RFPCTR4.UINT32
+#define RSCAN0RFPCTR4L RSCAN0.RFPCTR4.UINT16[L]
+#define RSCAN0RFPCTR4LL RSCAN0.RFPCTR4.UINT8[LL]
+#define RSCAN0RFPCTR4LH RSCAN0.RFPCTR4.UINT8[LH]
+#define RSCAN0RFPCTR4H RSCAN0.RFPCTR4.UINT16[H]
+#define RSCAN0RFPCTR4HL RSCAN0.RFPCTR4.UINT8[HL]
+#define RSCAN0RFPCTR4HH RSCAN0.RFPCTR4.UINT8[HH]
+#define RSCAN0RFPCTR5 RSCAN0.RFPCTR5.UINT32
+#define RSCAN0RFPCTR5L RSCAN0.RFPCTR5.UINT16[L]
+#define RSCAN0RFPCTR5LL RSCAN0.RFPCTR5.UINT8[LL]
+#define RSCAN0RFPCTR5LH RSCAN0.RFPCTR5.UINT8[LH]
+#define RSCAN0RFPCTR5H RSCAN0.RFPCTR5.UINT16[H]
+#define RSCAN0RFPCTR5HL RSCAN0.RFPCTR5.UINT8[HL]
+#define RSCAN0RFPCTR5HH RSCAN0.RFPCTR5.UINT8[HH]
+#define RSCAN0RFPCTR6 RSCAN0.RFPCTR6.UINT32
+#define RSCAN0RFPCTR6L RSCAN0.RFPCTR6.UINT16[L]
+#define RSCAN0RFPCTR6LL RSCAN0.RFPCTR6.UINT8[LL]
+#define RSCAN0RFPCTR6LH RSCAN0.RFPCTR6.UINT8[LH]
+#define RSCAN0RFPCTR6H RSCAN0.RFPCTR6.UINT16[H]
+#define RSCAN0RFPCTR6HL RSCAN0.RFPCTR6.UINT8[HL]
+#define RSCAN0RFPCTR6HH RSCAN0.RFPCTR6.UINT8[HH]
+#define RSCAN0RFPCTR7 RSCAN0.RFPCTR7.UINT32
+#define RSCAN0RFPCTR7L RSCAN0.RFPCTR7.UINT16[L]
+#define RSCAN0RFPCTR7LL RSCAN0.RFPCTR7.UINT8[LL]
+#define RSCAN0RFPCTR7LH RSCAN0.RFPCTR7.UINT8[LH]
+#define RSCAN0RFPCTR7H RSCAN0.RFPCTR7.UINT16[H]
+#define RSCAN0RFPCTR7HL RSCAN0.RFPCTR7.UINT8[HL]
+#define RSCAN0RFPCTR7HH RSCAN0.RFPCTR7.UINT8[HH]
+#define RSCAN0CFCC0 RSCAN0.CFCC0.UINT32
+#define RSCAN0CFCC0L RSCAN0.CFCC0.UINT16[L]
+#define RSCAN0CFCC0LL RSCAN0.CFCC0.UINT8[LL]
+#define RSCAN0CFCC0LH RSCAN0.CFCC0.UINT8[LH]
+#define RSCAN0CFCC0H RSCAN0.CFCC0.UINT16[H]
+#define RSCAN0CFCC0HL RSCAN0.CFCC0.UINT8[HL]
+#define RSCAN0CFCC0HH RSCAN0.CFCC0.UINT8[HH]
+#define RSCAN0CFCC1 RSCAN0.CFCC1.UINT32
+#define RSCAN0CFCC1L RSCAN0.CFCC1.UINT16[L]
+#define RSCAN0CFCC1LL RSCAN0.CFCC1.UINT8[LL]
+#define RSCAN0CFCC1LH RSCAN0.CFCC1.UINT8[LH]
+#define RSCAN0CFCC1H RSCAN0.CFCC1.UINT16[H]
+#define RSCAN0CFCC1HL RSCAN0.CFCC1.UINT8[HL]
+#define RSCAN0CFCC1HH RSCAN0.CFCC1.UINT8[HH]
+#define RSCAN0CFCC2 RSCAN0.CFCC2.UINT32
+#define RSCAN0CFCC2L RSCAN0.CFCC2.UINT16[L]
+#define RSCAN0CFCC2LL RSCAN0.CFCC2.UINT8[LL]
+#define RSCAN0CFCC2LH RSCAN0.CFCC2.UINT8[LH]
+#define RSCAN0CFCC2H RSCAN0.CFCC2.UINT16[H]
+#define RSCAN0CFCC2HL RSCAN0.CFCC2.UINT8[HL]
+#define RSCAN0CFCC2HH RSCAN0.CFCC2.UINT8[HH]
+#define RSCAN0CFCC3 RSCAN0.CFCC3.UINT32
+#define RSCAN0CFCC3L RSCAN0.CFCC3.UINT16[L]
+#define RSCAN0CFCC3LL RSCAN0.CFCC3.UINT8[LL]
+#define RSCAN0CFCC3LH RSCAN0.CFCC3.UINT8[LH]
+#define RSCAN0CFCC3H RSCAN0.CFCC3.UINT16[H]
+#define RSCAN0CFCC3HL RSCAN0.CFCC3.UINT8[HL]
+#define RSCAN0CFCC3HH RSCAN0.CFCC3.UINT8[HH]
+#define RSCAN0CFCC4 RSCAN0.CFCC4.UINT32
+#define RSCAN0CFCC4L RSCAN0.CFCC4.UINT16[L]
+#define RSCAN0CFCC4LL RSCAN0.CFCC4.UINT8[LL]
+#define RSCAN0CFCC4LH RSCAN0.CFCC4.UINT8[LH]
+#define RSCAN0CFCC4H RSCAN0.CFCC4.UINT16[H]
+#define RSCAN0CFCC4HL RSCAN0.CFCC4.UINT8[HL]
+#define RSCAN0CFCC4HH RSCAN0.CFCC4.UINT8[HH]
+#define RSCAN0CFCC5 RSCAN0.CFCC5.UINT32
+#define RSCAN0CFCC5L RSCAN0.CFCC5.UINT16[L]
+#define RSCAN0CFCC5LL RSCAN0.CFCC5.UINT8[LL]
+#define RSCAN0CFCC5LH RSCAN0.CFCC5.UINT8[LH]
+#define RSCAN0CFCC5H RSCAN0.CFCC5.UINT16[H]
+#define RSCAN0CFCC5HL RSCAN0.CFCC5.UINT8[HL]
+#define RSCAN0CFCC5HH RSCAN0.CFCC5.UINT8[HH]
+#define RSCAN0CFCC6 RSCAN0.CFCC6.UINT32
+#define RSCAN0CFCC6L RSCAN0.CFCC6.UINT16[L]
+#define RSCAN0CFCC6LL RSCAN0.CFCC6.UINT8[LL]
+#define RSCAN0CFCC6LH RSCAN0.CFCC6.UINT8[LH]
+#define RSCAN0CFCC6H RSCAN0.CFCC6.UINT16[H]
+#define RSCAN0CFCC6HL RSCAN0.CFCC6.UINT8[HL]
+#define RSCAN0CFCC6HH RSCAN0.CFCC6.UINT8[HH]
+#define RSCAN0CFCC7 RSCAN0.CFCC7.UINT32
+#define RSCAN0CFCC7L RSCAN0.CFCC7.UINT16[L]
+#define RSCAN0CFCC7LL RSCAN0.CFCC7.UINT8[LL]
+#define RSCAN0CFCC7LH RSCAN0.CFCC7.UINT8[LH]
+#define RSCAN0CFCC7H RSCAN0.CFCC7.UINT16[H]
+#define RSCAN0CFCC7HL RSCAN0.CFCC7.UINT8[HL]
+#define RSCAN0CFCC7HH RSCAN0.CFCC7.UINT8[HH]
+#define RSCAN0CFCC8 RSCAN0.CFCC8.UINT32
+#define RSCAN0CFCC8L RSCAN0.CFCC8.UINT16[L]
+#define RSCAN0CFCC8LL RSCAN0.CFCC8.UINT8[LL]
+#define RSCAN0CFCC8LH RSCAN0.CFCC8.UINT8[LH]
+#define RSCAN0CFCC8H RSCAN0.CFCC8.UINT16[H]
+#define RSCAN0CFCC8HL RSCAN0.CFCC8.UINT8[HL]
+#define RSCAN0CFCC8HH RSCAN0.CFCC8.UINT8[HH]
+#define RSCAN0CFCC9 RSCAN0.CFCC9.UINT32
+#define RSCAN0CFCC9L RSCAN0.CFCC9.UINT16[L]
+#define RSCAN0CFCC9LL RSCAN0.CFCC9.UINT8[LL]
+#define RSCAN0CFCC9LH RSCAN0.CFCC9.UINT8[LH]
+#define RSCAN0CFCC9H RSCAN0.CFCC9.UINT16[H]
+#define RSCAN0CFCC9HL RSCAN0.CFCC9.UINT8[HL]
+#define RSCAN0CFCC9HH RSCAN0.CFCC9.UINT8[HH]
+#define RSCAN0CFCC10 RSCAN0.CFCC10.UINT32
+#define RSCAN0CFCC10L RSCAN0.CFCC10.UINT16[L]
+#define RSCAN0CFCC10LL RSCAN0.CFCC10.UINT8[LL]
+#define RSCAN0CFCC10LH RSCAN0.CFCC10.UINT8[LH]
+#define RSCAN0CFCC10H RSCAN0.CFCC10.UINT16[H]
+#define RSCAN0CFCC10HL RSCAN0.CFCC10.UINT8[HL]
+#define RSCAN0CFCC10HH RSCAN0.CFCC10.UINT8[HH]
+#define RSCAN0CFCC11 RSCAN0.CFCC11.UINT32
+#define RSCAN0CFCC11L RSCAN0.CFCC11.UINT16[L]
+#define RSCAN0CFCC11LL RSCAN0.CFCC11.UINT8[LL]
+#define RSCAN0CFCC11LH RSCAN0.CFCC11.UINT8[LH]
+#define RSCAN0CFCC11H RSCAN0.CFCC11.UINT16[H]
+#define RSCAN0CFCC11HL RSCAN0.CFCC11.UINT8[HL]
+#define RSCAN0CFCC11HH RSCAN0.CFCC11.UINT8[HH]
+#define RSCAN0CFCC12 RSCAN0.CFCC12.UINT32
+#define RSCAN0CFCC12L RSCAN0.CFCC12.UINT16[L]
+#define RSCAN0CFCC12LL RSCAN0.CFCC12.UINT8[LL]
+#define RSCAN0CFCC12LH RSCAN0.CFCC12.UINT8[LH]
+#define RSCAN0CFCC12H RSCAN0.CFCC12.UINT16[H]
+#define RSCAN0CFCC12HL RSCAN0.CFCC12.UINT8[HL]
+#define RSCAN0CFCC12HH RSCAN0.CFCC12.UINT8[HH]
+#define RSCAN0CFCC13 RSCAN0.CFCC13.UINT32
+#define RSCAN0CFCC13L RSCAN0.CFCC13.UINT16[L]
+#define RSCAN0CFCC13LL RSCAN0.CFCC13.UINT8[LL]
+#define RSCAN0CFCC13LH RSCAN0.CFCC13.UINT8[LH]
+#define RSCAN0CFCC13H RSCAN0.CFCC13.UINT16[H]
+#define RSCAN0CFCC13HL RSCAN0.CFCC13.UINT8[HL]
+#define RSCAN0CFCC13HH RSCAN0.CFCC13.UINT8[HH]
+#define RSCAN0CFCC14 RSCAN0.CFCC14.UINT32
+#define RSCAN0CFCC14L RSCAN0.CFCC14.UINT16[L]
+#define RSCAN0CFCC14LL RSCAN0.CFCC14.UINT8[LL]
+#define RSCAN0CFCC14LH RSCAN0.CFCC14.UINT8[LH]
+#define RSCAN0CFCC14H RSCAN0.CFCC14.UINT16[H]
+#define RSCAN0CFCC14HL RSCAN0.CFCC14.UINT8[HL]
+#define RSCAN0CFCC14HH RSCAN0.CFCC14.UINT8[HH]
+#define RSCAN0CFSTS0 RSCAN0.CFSTS0.UINT32
+#define RSCAN0CFSTS0L RSCAN0.CFSTS0.UINT16[L]
+#define RSCAN0CFSTS0LL RSCAN0.CFSTS0.UINT8[LL]
+#define RSCAN0CFSTS0LH RSCAN0.CFSTS0.UINT8[LH]
+#define RSCAN0CFSTS0H RSCAN0.CFSTS0.UINT16[H]
+#define RSCAN0CFSTS0HL RSCAN0.CFSTS0.UINT8[HL]
+#define RSCAN0CFSTS0HH RSCAN0.CFSTS0.UINT8[HH]
+#define RSCAN0CFSTS1 RSCAN0.CFSTS1.UINT32
+#define RSCAN0CFSTS1L RSCAN0.CFSTS1.UINT16[L]
+#define RSCAN0CFSTS1LL RSCAN0.CFSTS1.UINT8[LL]
+#define RSCAN0CFSTS1LH RSCAN0.CFSTS1.UINT8[LH]
+#define RSCAN0CFSTS1H RSCAN0.CFSTS1.UINT16[H]
+#define RSCAN0CFSTS1HL RSCAN0.CFSTS1.UINT8[HL]
+#define RSCAN0CFSTS1HH RSCAN0.CFSTS1.UINT8[HH]
+#define RSCAN0CFSTS2 RSCAN0.CFSTS2.UINT32
+#define RSCAN0CFSTS2L RSCAN0.CFSTS2.UINT16[L]
+#define RSCAN0CFSTS2LL RSCAN0.CFSTS2.UINT8[LL]
+#define RSCAN0CFSTS2LH RSCAN0.CFSTS2.UINT8[LH]
+#define RSCAN0CFSTS2H RSCAN0.CFSTS2.UINT16[H]
+#define RSCAN0CFSTS2HL RSCAN0.CFSTS2.UINT8[HL]
+#define RSCAN0CFSTS2HH RSCAN0.CFSTS2.UINT8[HH]
+#define RSCAN0CFSTS3 RSCAN0.CFSTS3.UINT32
+#define RSCAN0CFSTS3L RSCAN0.CFSTS3.UINT16[L]
+#define RSCAN0CFSTS3LL RSCAN0.CFSTS3.UINT8[LL]
+#define RSCAN0CFSTS3LH RSCAN0.CFSTS3.UINT8[LH]
+#define RSCAN0CFSTS3H RSCAN0.CFSTS3.UINT16[H]
+#define RSCAN0CFSTS3HL RSCAN0.CFSTS3.UINT8[HL]
+#define RSCAN0CFSTS3HH RSCAN0.CFSTS3.UINT8[HH]
+#define RSCAN0CFSTS4 RSCAN0.CFSTS4.UINT32
+#define RSCAN0CFSTS4L RSCAN0.CFSTS4.UINT16[L]
+#define RSCAN0CFSTS4LL RSCAN0.CFSTS4.UINT8[LL]
+#define RSCAN0CFSTS4LH RSCAN0.CFSTS4.UINT8[LH]
+#define RSCAN0CFSTS4H RSCAN0.CFSTS4.UINT16[H]
+#define RSCAN0CFSTS4HL RSCAN0.CFSTS4.UINT8[HL]
+#define RSCAN0CFSTS4HH RSCAN0.CFSTS4.UINT8[HH]
+#define RSCAN0CFSTS5 RSCAN0.CFSTS5.UINT32
+#define RSCAN0CFSTS5L RSCAN0.CFSTS5.UINT16[L]
+#define RSCAN0CFSTS5LL RSCAN0.CFSTS5.UINT8[LL]
+#define RSCAN0CFSTS5LH RSCAN0.CFSTS5.UINT8[LH]
+#define RSCAN0CFSTS5H RSCAN0.CFSTS5.UINT16[H]
+#define RSCAN0CFSTS5HL RSCAN0.CFSTS5.UINT8[HL]
+#define RSCAN0CFSTS5HH RSCAN0.CFSTS5.UINT8[HH]
+#define RSCAN0CFSTS6 RSCAN0.CFSTS6.UINT32
+#define RSCAN0CFSTS6L RSCAN0.CFSTS6.UINT16[L]
+#define RSCAN0CFSTS6LL RSCAN0.CFSTS6.UINT8[LL]
+#define RSCAN0CFSTS6LH RSCAN0.CFSTS6.UINT8[LH]
+#define RSCAN0CFSTS6H RSCAN0.CFSTS6.UINT16[H]
+#define RSCAN0CFSTS6HL RSCAN0.CFSTS6.UINT8[HL]
+#define RSCAN0CFSTS6HH RSCAN0.CFSTS6.UINT8[HH]
+#define RSCAN0CFSTS7 RSCAN0.CFSTS7.UINT32
+#define RSCAN0CFSTS7L RSCAN0.CFSTS7.UINT16[L]
+#define RSCAN0CFSTS7LL RSCAN0.CFSTS7.UINT8[LL]
+#define RSCAN0CFSTS7LH RSCAN0.CFSTS7.UINT8[LH]
+#define RSCAN0CFSTS7H RSCAN0.CFSTS7.UINT16[H]
+#define RSCAN0CFSTS7HL RSCAN0.CFSTS7.UINT8[HL]
+#define RSCAN0CFSTS7HH RSCAN0.CFSTS7.UINT8[HH]
+#define RSCAN0CFSTS8 RSCAN0.CFSTS8.UINT32
+#define RSCAN0CFSTS8L RSCAN0.CFSTS8.UINT16[L]
+#define RSCAN0CFSTS8LL RSCAN0.CFSTS8.UINT8[LL]
+#define RSCAN0CFSTS8LH RSCAN0.CFSTS8.UINT8[LH]
+#define RSCAN0CFSTS8H RSCAN0.CFSTS8.UINT16[H]
+#define RSCAN0CFSTS8HL RSCAN0.CFSTS8.UINT8[HL]
+#define RSCAN0CFSTS8HH RSCAN0.CFSTS8.UINT8[HH]
+#define RSCAN0CFSTS9 RSCAN0.CFSTS9.UINT32
+#define RSCAN0CFSTS9L RSCAN0.CFSTS9.UINT16[L]
+#define RSCAN0CFSTS9LL RSCAN0.CFSTS9.UINT8[LL]
+#define RSCAN0CFSTS9LH RSCAN0.CFSTS9.UINT8[LH]
+#define RSCAN0CFSTS9H RSCAN0.CFSTS9.UINT16[H]
+#define RSCAN0CFSTS9HL RSCAN0.CFSTS9.UINT8[HL]
+#define RSCAN0CFSTS9HH RSCAN0.CFSTS9.UINT8[HH]
+#define RSCAN0CFSTS10 RSCAN0.CFSTS10.UINT32
+#define RSCAN0CFSTS10L RSCAN0.CFSTS10.UINT16[L]
+#define RSCAN0CFSTS10LL RSCAN0.CFSTS10.UINT8[LL]
+#define RSCAN0CFSTS10LH RSCAN0.CFSTS10.UINT8[LH]
+#define RSCAN0CFSTS10H RSCAN0.CFSTS10.UINT16[H]
+#define RSCAN0CFSTS10HL RSCAN0.CFSTS10.UINT8[HL]
+#define RSCAN0CFSTS10HH RSCAN0.CFSTS10.UINT8[HH]
+#define RSCAN0CFSTS11 RSCAN0.CFSTS11.UINT32
+#define RSCAN0CFSTS11L RSCAN0.CFSTS11.UINT16[L]
+#define RSCAN0CFSTS11LL RSCAN0.CFSTS11.UINT8[LL]
+#define RSCAN0CFSTS11LH RSCAN0.CFSTS11.UINT8[LH]
+#define RSCAN0CFSTS11H RSCAN0.CFSTS11.UINT16[H]
+#define RSCAN0CFSTS11HL RSCAN0.CFSTS11.UINT8[HL]
+#define RSCAN0CFSTS11HH RSCAN0.CFSTS11.UINT8[HH]
+#define RSCAN0CFSTS12 RSCAN0.CFSTS12.UINT32
+#define RSCAN0CFSTS12L RSCAN0.CFSTS12.UINT16[L]
+#define RSCAN0CFSTS12LL RSCAN0.CFSTS12.UINT8[LL]
+#define RSCAN0CFSTS12LH RSCAN0.CFSTS12.UINT8[LH]
+#define RSCAN0CFSTS12H RSCAN0.CFSTS12.UINT16[H]
+#define RSCAN0CFSTS12HL RSCAN0.CFSTS12.UINT8[HL]
+#define RSCAN0CFSTS12HH RSCAN0.CFSTS12.UINT8[HH]
+#define RSCAN0CFSTS13 RSCAN0.CFSTS13.UINT32
+#define RSCAN0CFSTS13L RSCAN0.CFSTS13.UINT16[L]
+#define RSCAN0CFSTS13LL RSCAN0.CFSTS13.UINT8[LL]
+#define RSCAN0CFSTS13LH RSCAN0.CFSTS13.UINT8[LH]
+#define RSCAN0CFSTS13H RSCAN0.CFSTS13.UINT16[H]
+#define RSCAN0CFSTS13HL RSCAN0.CFSTS13.UINT8[HL]
+#define RSCAN0CFSTS13HH RSCAN0.CFSTS13.UINT8[HH]
+#define RSCAN0CFSTS14 RSCAN0.CFSTS14.UINT32
+#define RSCAN0CFSTS14L RSCAN0.CFSTS14.UINT16[L]
+#define RSCAN0CFSTS14LL RSCAN0.CFSTS14.UINT8[LL]
+#define RSCAN0CFSTS14LH RSCAN0.CFSTS14.UINT8[LH]
+#define RSCAN0CFSTS14H RSCAN0.CFSTS14.UINT16[H]
+#define RSCAN0CFSTS14HL RSCAN0.CFSTS14.UINT8[HL]
+#define RSCAN0CFSTS14HH RSCAN0.CFSTS14.UINT8[HH]
+#define RSCAN0CFPCTR0 RSCAN0.CFPCTR0.UINT32
+#define RSCAN0CFPCTR0L RSCAN0.CFPCTR0.UINT16[L]
+#define RSCAN0CFPCTR0LL RSCAN0.CFPCTR0.UINT8[LL]
+#define RSCAN0CFPCTR0LH RSCAN0.CFPCTR0.UINT8[LH]
+#define RSCAN0CFPCTR0H RSCAN0.CFPCTR0.UINT16[H]
+#define RSCAN0CFPCTR0HL RSCAN0.CFPCTR0.UINT8[HL]
+#define RSCAN0CFPCTR0HH RSCAN0.CFPCTR0.UINT8[HH]
+#define RSCAN0CFPCTR1 RSCAN0.CFPCTR1.UINT32
+#define RSCAN0CFPCTR1L RSCAN0.CFPCTR1.UINT16[L]
+#define RSCAN0CFPCTR1LL RSCAN0.CFPCTR1.UINT8[LL]
+#define RSCAN0CFPCTR1LH RSCAN0.CFPCTR1.UINT8[LH]
+#define RSCAN0CFPCTR1H RSCAN0.CFPCTR1.UINT16[H]
+#define RSCAN0CFPCTR1HL RSCAN0.CFPCTR1.UINT8[HL]
+#define RSCAN0CFPCTR1HH RSCAN0.CFPCTR1.UINT8[HH]
+#define RSCAN0CFPCTR2 RSCAN0.CFPCTR2.UINT32
+#define RSCAN0CFPCTR2L RSCAN0.CFPCTR2.UINT16[L]
+#define RSCAN0CFPCTR2LL RSCAN0.CFPCTR2.UINT8[LL]
+#define RSCAN0CFPCTR2LH RSCAN0.CFPCTR2.UINT8[LH]
+#define RSCAN0CFPCTR2H RSCAN0.CFPCTR2.UINT16[H]
+#define RSCAN0CFPCTR2HL RSCAN0.CFPCTR2.UINT8[HL]
+#define RSCAN0CFPCTR2HH RSCAN0.CFPCTR2.UINT8[HH]
+#define RSCAN0CFPCTR3 RSCAN0.CFPCTR3.UINT32
+#define RSCAN0CFPCTR3L RSCAN0.CFPCTR3.UINT16[L]
+#define RSCAN0CFPCTR3LL RSCAN0.CFPCTR3.UINT8[LL]
+#define RSCAN0CFPCTR3LH RSCAN0.CFPCTR3.UINT8[LH]
+#define RSCAN0CFPCTR3H RSCAN0.CFPCTR3.UINT16[H]
+#define RSCAN0CFPCTR3HL RSCAN0.CFPCTR3.UINT8[HL]
+#define RSCAN0CFPCTR3HH RSCAN0.CFPCTR3.UINT8[HH]
+#define RSCAN0CFPCTR4 RSCAN0.CFPCTR4.UINT32
+#define RSCAN0CFPCTR4L RSCAN0.CFPCTR4.UINT16[L]
+#define RSCAN0CFPCTR4LL RSCAN0.CFPCTR4.UINT8[LL]
+#define RSCAN0CFPCTR4LH RSCAN0.CFPCTR4.UINT8[LH]
+#define RSCAN0CFPCTR4H RSCAN0.CFPCTR4.UINT16[H]
+#define RSCAN0CFPCTR4HL RSCAN0.CFPCTR4.UINT8[HL]
+#define RSCAN0CFPCTR4HH RSCAN0.CFPCTR4.UINT8[HH]
+#define RSCAN0CFPCTR5 RSCAN0.CFPCTR5.UINT32
+#define RSCAN0CFPCTR5L RSCAN0.CFPCTR5.UINT16[L]
+#define RSCAN0CFPCTR5LL RSCAN0.CFPCTR5.UINT8[LL]
+#define RSCAN0CFPCTR5LH RSCAN0.CFPCTR5.UINT8[LH]
+#define RSCAN0CFPCTR5H RSCAN0.CFPCTR5.UINT16[H]
+#define RSCAN0CFPCTR5HL RSCAN0.CFPCTR5.UINT8[HL]
+#define RSCAN0CFPCTR5HH RSCAN0.CFPCTR5.UINT8[HH]
+#define RSCAN0CFPCTR6 RSCAN0.CFPCTR6.UINT32
+#define RSCAN0CFPCTR6L RSCAN0.CFPCTR6.UINT16[L]
+#define RSCAN0CFPCTR6LL RSCAN0.CFPCTR6.UINT8[LL]
+#define RSCAN0CFPCTR6LH RSCAN0.CFPCTR6.UINT8[LH]
+#define RSCAN0CFPCTR6H RSCAN0.CFPCTR6.UINT16[H]
+#define RSCAN0CFPCTR6HL RSCAN0.CFPCTR6.UINT8[HL]
+#define RSCAN0CFPCTR6HH RSCAN0.CFPCTR6.UINT8[HH]
+#define RSCAN0CFPCTR7 RSCAN0.CFPCTR7.UINT32
+#define RSCAN0CFPCTR7L RSCAN0.CFPCTR7.UINT16[L]
+#define RSCAN0CFPCTR7LL RSCAN0.CFPCTR7.UINT8[LL]
+#define RSCAN0CFPCTR7LH RSCAN0.CFPCTR7.UINT8[LH]
+#define RSCAN0CFPCTR7H RSCAN0.CFPCTR7.UINT16[H]
+#define RSCAN0CFPCTR7HL RSCAN0.CFPCTR7.UINT8[HL]
+#define RSCAN0CFPCTR7HH RSCAN0.CFPCTR7.UINT8[HH]
+#define RSCAN0CFPCTR8 RSCAN0.CFPCTR8.UINT32
+#define RSCAN0CFPCTR8L RSCAN0.CFPCTR8.UINT16[L]
+#define RSCAN0CFPCTR8LL RSCAN0.CFPCTR8.UINT8[LL]
+#define RSCAN0CFPCTR8LH RSCAN0.CFPCTR8.UINT8[LH]
+#define RSCAN0CFPCTR8H RSCAN0.CFPCTR8.UINT16[H]
+#define RSCAN0CFPCTR8HL RSCAN0.CFPCTR8.UINT8[HL]
+#define RSCAN0CFPCTR8HH RSCAN0.CFPCTR8.UINT8[HH]
+#define RSCAN0CFPCTR9 RSCAN0.CFPCTR9.UINT32
+#define RSCAN0CFPCTR9L RSCAN0.CFPCTR9.UINT16[L]
+#define RSCAN0CFPCTR9LL RSCAN0.CFPCTR9.UINT8[LL]
+#define RSCAN0CFPCTR9LH RSCAN0.CFPCTR9.UINT8[LH]
+#define RSCAN0CFPCTR9H RSCAN0.CFPCTR9.UINT16[H]
+#define RSCAN0CFPCTR9HL RSCAN0.CFPCTR9.UINT8[HL]
+#define RSCAN0CFPCTR9HH RSCAN0.CFPCTR9.UINT8[HH]
+#define RSCAN0CFPCTR10 RSCAN0.CFPCTR10.UINT32
+#define RSCAN0CFPCTR10L RSCAN0.CFPCTR10.UINT16[L]
+#define RSCAN0CFPCTR10LL RSCAN0.CFPCTR10.UINT8[LL]
+#define RSCAN0CFPCTR10LH RSCAN0.CFPCTR10.UINT8[LH]
+#define RSCAN0CFPCTR10H RSCAN0.CFPCTR10.UINT16[H]
+#define RSCAN0CFPCTR10HL RSCAN0.CFPCTR10.UINT8[HL]
+#define RSCAN0CFPCTR10HH RSCAN0.CFPCTR10.UINT8[HH]
+#define RSCAN0CFPCTR11 RSCAN0.CFPCTR11.UINT32
+#define RSCAN0CFPCTR11L RSCAN0.CFPCTR11.UINT16[L]
+#define RSCAN0CFPCTR11LL RSCAN0.CFPCTR11.UINT8[LL]
+#define RSCAN0CFPCTR11LH RSCAN0.CFPCTR11.UINT8[LH]
+#define RSCAN0CFPCTR11H RSCAN0.CFPCTR11.UINT16[H]
+#define RSCAN0CFPCTR11HL RSCAN0.CFPCTR11.UINT8[HL]
+#define RSCAN0CFPCTR11HH RSCAN0.CFPCTR11.UINT8[HH]
+#define RSCAN0CFPCTR12 RSCAN0.CFPCTR12.UINT32
+#define RSCAN0CFPCTR12L RSCAN0.CFPCTR12.UINT16[L]
+#define RSCAN0CFPCTR12LL RSCAN0.CFPCTR12.UINT8[LL]
+#define RSCAN0CFPCTR12LH RSCAN0.CFPCTR12.UINT8[LH]
+#define RSCAN0CFPCTR12H RSCAN0.CFPCTR12.UINT16[H]
+#define RSCAN0CFPCTR12HL RSCAN0.CFPCTR12.UINT8[HL]
+#define RSCAN0CFPCTR12HH RSCAN0.CFPCTR12.UINT8[HH]
+#define RSCAN0CFPCTR13 RSCAN0.CFPCTR13.UINT32
+#define RSCAN0CFPCTR13L RSCAN0.CFPCTR13.UINT16[L]
+#define RSCAN0CFPCTR13LL RSCAN0.CFPCTR13.UINT8[LL]
+#define RSCAN0CFPCTR13LH RSCAN0.CFPCTR13.UINT8[LH]
+#define RSCAN0CFPCTR13H RSCAN0.CFPCTR13.UINT16[H]
+#define RSCAN0CFPCTR13HL RSCAN0.CFPCTR13.UINT8[HL]
+#define RSCAN0CFPCTR13HH RSCAN0.CFPCTR13.UINT8[HH]
+#define RSCAN0CFPCTR14 RSCAN0.CFPCTR14.UINT32
+#define RSCAN0CFPCTR14L RSCAN0.CFPCTR14.UINT16[L]
+#define RSCAN0CFPCTR14LL RSCAN0.CFPCTR14.UINT8[LL]
+#define RSCAN0CFPCTR14LH RSCAN0.CFPCTR14.UINT8[LH]
+#define RSCAN0CFPCTR14H RSCAN0.CFPCTR14.UINT16[H]
+#define RSCAN0CFPCTR14HL RSCAN0.CFPCTR14.UINT8[HL]
+#define RSCAN0CFPCTR14HH RSCAN0.CFPCTR14.UINT8[HH]
+#define RSCAN0FESTS RSCAN0.FESTS.UINT32
+#define RSCAN0FESTSL RSCAN0.FESTS.UINT16[L]
+#define RSCAN0FESTSLL RSCAN0.FESTS.UINT8[LL]
+#define RSCAN0FESTSLH RSCAN0.FESTS.UINT8[LH]
+#define RSCAN0FESTSH RSCAN0.FESTS.UINT16[H]
+#define RSCAN0FESTSHL RSCAN0.FESTS.UINT8[HL]
+#define RSCAN0FESTSHH RSCAN0.FESTS.UINT8[HH]
+#define RSCAN0FFSTS RSCAN0.FFSTS.UINT32
+#define RSCAN0FFSTSL RSCAN0.FFSTS.UINT16[L]
+#define RSCAN0FFSTSLL RSCAN0.FFSTS.UINT8[LL]
+#define RSCAN0FFSTSLH RSCAN0.FFSTS.UINT8[LH]
+#define RSCAN0FFSTSH RSCAN0.FFSTS.UINT16[H]
+#define RSCAN0FFSTSHL RSCAN0.FFSTS.UINT8[HL]
+#define RSCAN0FFSTSHH RSCAN0.FFSTS.UINT8[HH]
+#define RSCAN0FMSTS RSCAN0.FMSTS.UINT32
+#define RSCAN0FMSTSL RSCAN0.FMSTS.UINT16[L]
+#define RSCAN0FMSTSLL RSCAN0.FMSTS.UINT8[LL]
+#define RSCAN0FMSTSLH RSCAN0.FMSTS.UINT8[LH]
+#define RSCAN0FMSTSH RSCAN0.FMSTS.UINT16[H]
+#define RSCAN0FMSTSHL RSCAN0.FMSTS.UINT8[HL]
+#define RSCAN0FMSTSHH RSCAN0.FMSTS.UINT8[HH]
+#define RSCAN0RFISTS RSCAN0.RFISTS.UINT32
+#define RSCAN0RFISTSL RSCAN0.RFISTS.UINT16[L]
+#define RSCAN0RFISTSLL RSCAN0.RFISTS.UINT8[LL]
+#define RSCAN0RFISTSLH RSCAN0.RFISTS.UINT8[LH]
+#define RSCAN0RFISTSH RSCAN0.RFISTS.UINT16[H]
+#define RSCAN0RFISTSHL RSCAN0.RFISTS.UINT8[HL]
+#define RSCAN0RFISTSHH RSCAN0.RFISTS.UINT8[HH]
+#define RSCAN0CFRISTS RSCAN0.CFRISTS.UINT32
+#define RSCAN0CFRISTSL RSCAN0.CFRISTS.UINT16[L]
+#define RSCAN0CFRISTSLL RSCAN0.CFRISTS.UINT8[LL]
+#define RSCAN0CFRISTSLH RSCAN0.CFRISTS.UINT8[LH]
+#define RSCAN0CFRISTSH RSCAN0.CFRISTS.UINT16[H]
+#define RSCAN0CFRISTSHL RSCAN0.CFRISTS.UINT8[HL]
+#define RSCAN0CFRISTSHH RSCAN0.CFRISTS.UINT8[HH]
+#define RSCAN0CFTISTS RSCAN0.CFTISTS.UINT32
+#define RSCAN0CFTISTSL RSCAN0.CFTISTS.UINT16[L]
+#define RSCAN0CFTISTSLL RSCAN0.CFTISTS.UINT8[LL]
+#define RSCAN0CFTISTSLH RSCAN0.CFTISTS.UINT8[LH]
+#define RSCAN0CFTISTSH RSCAN0.CFTISTS.UINT16[H]
+#define RSCAN0CFTISTSHL RSCAN0.CFTISTS.UINT8[HL]
+#define RSCAN0CFTISTSHH RSCAN0.CFTISTS.UINT8[HH]
+#define RSCAN0TMC0 RSCAN0.TMC0
+#define RSCAN0TMC1 RSCAN0.TMC1
+#define RSCAN0TMC2 RSCAN0.TMC2
+#define RSCAN0TMC3 RSCAN0.TMC3
+#define RSCAN0TMC4 RSCAN0.TMC4
+#define RSCAN0TMC5 RSCAN0.TMC5
+#define RSCAN0TMC6 RSCAN0.TMC6
+#define RSCAN0TMC7 RSCAN0.TMC7
+#define RSCAN0TMC8 RSCAN0.TMC8
+#define RSCAN0TMC9 RSCAN0.TMC9
+#define RSCAN0TMC10 RSCAN0.TMC10
+#define RSCAN0TMC11 RSCAN0.TMC11
+#define RSCAN0TMC12 RSCAN0.TMC12
+#define RSCAN0TMC13 RSCAN0.TMC13
+#define RSCAN0TMC14 RSCAN0.TMC14
+#define RSCAN0TMC15 RSCAN0.TMC15
+#define RSCAN0TMC16 RSCAN0.TMC16
+#define RSCAN0TMC17 RSCAN0.TMC17
+#define RSCAN0TMC18 RSCAN0.TMC18
+#define RSCAN0TMC19 RSCAN0.TMC19
+#define RSCAN0TMC20 RSCAN0.TMC20
+#define RSCAN0TMC21 RSCAN0.TMC21
+#define RSCAN0TMC22 RSCAN0.TMC22
+#define RSCAN0TMC23 RSCAN0.TMC23
+#define RSCAN0TMC24 RSCAN0.TMC24
+#define RSCAN0TMC25 RSCAN0.TMC25
+#define RSCAN0TMC26 RSCAN0.TMC26
+#define RSCAN0TMC27 RSCAN0.TMC27
+#define RSCAN0TMC28 RSCAN0.TMC28
+#define RSCAN0TMC29 RSCAN0.TMC29
+#define RSCAN0TMC30 RSCAN0.TMC30
+#define RSCAN0TMC31 RSCAN0.TMC31
+#define RSCAN0TMC32 RSCAN0.TMC32
+#define RSCAN0TMC33 RSCAN0.TMC33
+#define RSCAN0TMC34 RSCAN0.TMC34
+#define RSCAN0TMC35 RSCAN0.TMC35
+#define RSCAN0TMC36 RSCAN0.TMC36
+#define RSCAN0TMC37 RSCAN0.TMC37
+#define RSCAN0TMC38 RSCAN0.TMC38
+#define RSCAN0TMC39 RSCAN0.TMC39
+#define RSCAN0TMC40 RSCAN0.TMC40
+#define RSCAN0TMC41 RSCAN0.TMC41
+#define RSCAN0TMC42 RSCAN0.TMC42
+#define RSCAN0TMC43 RSCAN0.TMC43
+#define RSCAN0TMC44 RSCAN0.TMC44
+#define RSCAN0TMC45 RSCAN0.TMC45
+#define RSCAN0TMC46 RSCAN0.TMC46
+#define RSCAN0TMC47 RSCAN0.TMC47
+#define RSCAN0TMC48 RSCAN0.TMC48
+#define RSCAN0TMC49 RSCAN0.TMC49
+#define RSCAN0TMC50 RSCAN0.TMC50
+#define RSCAN0TMC51 RSCAN0.TMC51
+#define RSCAN0TMC52 RSCAN0.TMC52
+#define RSCAN0TMC53 RSCAN0.TMC53
+#define RSCAN0TMC54 RSCAN0.TMC54
+#define RSCAN0TMC55 RSCAN0.TMC55
+#define RSCAN0TMC56 RSCAN0.TMC56
+#define RSCAN0TMC57 RSCAN0.TMC57
+#define RSCAN0TMC58 RSCAN0.TMC58
+#define RSCAN0TMC59 RSCAN0.TMC59
+#define RSCAN0TMC60 RSCAN0.TMC60
+#define RSCAN0TMC61 RSCAN0.TMC61
+#define RSCAN0TMC62 RSCAN0.TMC62
+#define RSCAN0TMC63 RSCAN0.TMC63
+#define RSCAN0TMC64 RSCAN0.TMC64
+#define RSCAN0TMC65 RSCAN0.TMC65
+#define RSCAN0TMC66 RSCAN0.TMC66
+#define RSCAN0TMC67 RSCAN0.TMC67
+#define RSCAN0TMC68 RSCAN0.TMC68
+#define RSCAN0TMC69 RSCAN0.TMC69
+#define RSCAN0TMC70 RSCAN0.TMC70
+#define RSCAN0TMC71 RSCAN0.TMC71
+#define RSCAN0TMC72 RSCAN0.TMC72
+#define RSCAN0TMC73 RSCAN0.TMC73
+#define RSCAN0TMC74 RSCAN0.TMC74
+#define RSCAN0TMC75 RSCAN0.TMC75
+#define RSCAN0TMC76 RSCAN0.TMC76
+#define RSCAN0TMC77 RSCAN0.TMC77
+#define RSCAN0TMC78 RSCAN0.TMC78
+#define RSCAN0TMC79 RSCAN0.TMC79
+#define RSCAN0TMSTS0 RSCAN0.TMSTS0
+#define RSCAN0TMSTS1 RSCAN0.TMSTS1
+#define RSCAN0TMSTS2 RSCAN0.TMSTS2
+#define RSCAN0TMSTS3 RSCAN0.TMSTS3
+#define RSCAN0TMSTS4 RSCAN0.TMSTS4
+#define RSCAN0TMSTS5 RSCAN0.TMSTS5
+#define RSCAN0TMSTS6 RSCAN0.TMSTS6
+#define RSCAN0TMSTS7 RSCAN0.TMSTS7
+#define RSCAN0TMSTS8 RSCAN0.TMSTS8
+#define RSCAN0TMSTS9 RSCAN0.TMSTS9
+#define RSCAN0TMSTS10 RSCAN0.TMSTS10
+#define RSCAN0TMSTS11 RSCAN0.TMSTS11
+#define RSCAN0TMSTS12 RSCAN0.TMSTS12
+#define RSCAN0TMSTS13 RSCAN0.TMSTS13
+#define RSCAN0TMSTS14 RSCAN0.TMSTS14
+#define RSCAN0TMSTS15 RSCAN0.TMSTS15
+#define RSCAN0TMSTS16 RSCAN0.TMSTS16
+#define RSCAN0TMSTS17 RSCAN0.TMSTS17
+#define RSCAN0TMSTS18 RSCAN0.TMSTS18
+#define RSCAN0TMSTS19 RSCAN0.TMSTS19
+#define RSCAN0TMSTS20 RSCAN0.TMSTS20
+#define RSCAN0TMSTS21 RSCAN0.TMSTS21
+#define RSCAN0TMSTS22 RSCAN0.TMSTS22
+#define RSCAN0TMSTS23 RSCAN0.TMSTS23
+#define RSCAN0TMSTS24 RSCAN0.TMSTS24
+#define RSCAN0TMSTS25 RSCAN0.TMSTS25
+#define RSCAN0TMSTS26 RSCAN0.TMSTS26
+#define RSCAN0TMSTS27 RSCAN0.TMSTS27
+#define RSCAN0TMSTS28 RSCAN0.TMSTS28
+#define RSCAN0TMSTS29 RSCAN0.TMSTS29
+#define RSCAN0TMSTS30 RSCAN0.TMSTS30
+#define RSCAN0TMSTS31 RSCAN0.TMSTS31
+#define RSCAN0TMSTS32 RSCAN0.TMSTS32
+#define RSCAN0TMSTS33 RSCAN0.TMSTS33
+#define RSCAN0TMSTS34 RSCAN0.TMSTS34
+#define RSCAN0TMSTS35 RSCAN0.TMSTS35
+#define RSCAN0TMSTS36 RSCAN0.TMSTS36
+#define RSCAN0TMSTS37 RSCAN0.TMSTS37
+#define RSCAN0TMSTS38 RSCAN0.TMSTS38
+#define RSCAN0TMSTS39 RSCAN0.TMSTS39
+#define RSCAN0TMSTS40 RSCAN0.TMSTS40
+#define RSCAN0TMSTS41 RSCAN0.TMSTS41
+#define RSCAN0TMSTS42 RSCAN0.TMSTS42
+#define RSCAN0TMSTS43 RSCAN0.TMSTS43
+#define RSCAN0TMSTS44 RSCAN0.TMSTS44
+#define RSCAN0TMSTS45 RSCAN0.TMSTS45
+#define RSCAN0TMSTS46 RSCAN0.TMSTS46
+#define RSCAN0TMSTS47 RSCAN0.TMSTS47
+#define RSCAN0TMSTS48 RSCAN0.TMSTS48
+#define RSCAN0TMSTS49 RSCAN0.TMSTS49
+#define RSCAN0TMSTS50 RSCAN0.TMSTS50
+#define RSCAN0TMSTS51 RSCAN0.TMSTS51
+#define RSCAN0TMSTS52 RSCAN0.TMSTS52
+#define RSCAN0TMSTS53 RSCAN0.TMSTS53
+#define RSCAN0TMSTS54 RSCAN0.TMSTS54
+#define RSCAN0TMSTS55 RSCAN0.TMSTS55
+#define RSCAN0TMSTS56 RSCAN0.TMSTS56
+#define RSCAN0TMSTS57 RSCAN0.TMSTS57
+#define RSCAN0TMSTS58 RSCAN0.TMSTS58
+#define RSCAN0TMSTS59 RSCAN0.TMSTS59
+#define RSCAN0TMSTS60 RSCAN0.TMSTS60
+#define RSCAN0TMSTS61 RSCAN0.TMSTS61
+#define RSCAN0TMSTS62 RSCAN0.TMSTS62
+#define RSCAN0TMSTS63 RSCAN0.TMSTS63
+#define RSCAN0TMSTS64 RSCAN0.TMSTS64
+#define RSCAN0TMSTS65 RSCAN0.TMSTS65
+#define RSCAN0TMSTS66 RSCAN0.TMSTS66
+#define RSCAN0TMSTS67 RSCAN0.TMSTS67
+#define RSCAN0TMSTS68 RSCAN0.TMSTS68
+#define RSCAN0TMSTS69 RSCAN0.TMSTS69
+#define RSCAN0TMSTS70 RSCAN0.TMSTS70
+#define RSCAN0TMSTS71 RSCAN0.TMSTS71
+#define RSCAN0TMSTS72 RSCAN0.TMSTS72
+#define RSCAN0TMSTS73 RSCAN0.TMSTS73
+#define RSCAN0TMSTS74 RSCAN0.TMSTS74
+#define RSCAN0TMSTS75 RSCAN0.TMSTS75
+#define RSCAN0TMSTS76 RSCAN0.TMSTS76
+#define RSCAN0TMSTS77 RSCAN0.TMSTS77
+#define RSCAN0TMSTS78 RSCAN0.TMSTS78
+#define RSCAN0TMSTS79 RSCAN0.TMSTS79
+#define RSCAN0TMTRSTS0 RSCAN0.TMTRSTS0.UINT32
+#define RSCAN0TMTRSTS0L RSCAN0.TMTRSTS0.UINT16[L]
+#define RSCAN0TMTRSTS0LL RSCAN0.TMTRSTS0.UINT8[LL]
+#define RSCAN0TMTRSTS0LH RSCAN0.TMTRSTS0.UINT8[LH]
+#define RSCAN0TMTRSTS0H RSCAN0.TMTRSTS0.UINT16[H]
+#define RSCAN0TMTRSTS0HL RSCAN0.TMTRSTS0.UINT8[HL]
+#define RSCAN0TMTRSTS0HH RSCAN0.TMTRSTS0.UINT8[HH]
+#define RSCAN0TMTRSTS1 RSCAN0.TMTRSTS1.UINT32
+#define RSCAN0TMTRSTS1L RSCAN0.TMTRSTS1.UINT16[L]
+#define RSCAN0TMTRSTS1LL RSCAN0.TMTRSTS1.UINT8[LL]
+#define RSCAN0TMTRSTS1LH RSCAN0.TMTRSTS1.UINT8[LH]
+#define RSCAN0TMTRSTS1H RSCAN0.TMTRSTS1.UINT16[H]
+#define RSCAN0TMTRSTS1HL RSCAN0.TMTRSTS1.UINT8[HL]
+#define RSCAN0TMTRSTS1HH RSCAN0.TMTRSTS1.UINT8[HH]
+#define RSCAN0TMTRSTS2 RSCAN0.TMTRSTS2.UINT32
+#define RSCAN0TMTRSTS2L RSCAN0.TMTRSTS2.UINT16[L]
+#define RSCAN0TMTRSTS2LL RSCAN0.TMTRSTS2.UINT8[LL]
+#define RSCAN0TMTRSTS2LH RSCAN0.TMTRSTS2.UINT8[LH]
+#define RSCAN0TMTRSTS2H RSCAN0.TMTRSTS2.UINT16[H]
+#define RSCAN0TMTRSTS2HL RSCAN0.TMTRSTS2.UINT8[HL]
+#define RSCAN0TMTRSTS2HH RSCAN0.TMTRSTS2.UINT8[HH]
+#define RSCAN0TMTARSTS0 RSCAN0.TMTARSTS0.UINT32
+#define RSCAN0TMTARSTS0L RSCAN0.TMTARSTS0.UINT16[L]
+#define RSCAN0TMTARSTS0LL RSCAN0.TMTARSTS0.UINT8[LL]
+#define RSCAN0TMTARSTS0LH RSCAN0.TMTARSTS0.UINT8[LH]
+#define RSCAN0TMTARSTS0H RSCAN0.TMTARSTS0.UINT16[H]
+#define RSCAN0TMTARSTS0HL RSCAN0.TMTARSTS0.UINT8[HL]
+#define RSCAN0TMTARSTS0HH RSCAN0.TMTARSTS0.UINT8[HH]
+#define RSCAN0TMTARSTS1 RSCAN0.TMTARSTS1.UINT32
+#define RSCAN0TMTARSTS1L RSCAN0.TMTARSTS1.UINT16[L]
+#define RSCAN0TMTARSTS1LL RSCAN0.TMTARSTS1.UINT8[LL]
+#define RSCAN0TMTARSTS1LH RSCAN0.TMTARSTS1.UINT8[LH]
+#define RSCAN0TMTARSTS1H RSCAN0.TMTARSTS1.UINT16[H]
+#define RSCAN0TMTARSTS1HL RSCAN0.TMTARSTS1.UINT8[HL]
+#define RSCAN0TMTARSTS1HH RSCAN0.TMTARSTS1.UINT8[HH]
+#define RSCAN0TMTARSTS2 RSCAN0.TMTARSTS2.UINT32
+#define RSCAN0TMTARSTS2L RSCAN0.TMTARSTS2.UINT16[L]
+#define RSCAN0TMTARSTS2LL RSCAN0.TMTARSTS2.UINT8[LL]
+#define RSCAN0TMTARSTS2LH RSCAN0.TMTARSTS2.UINT8[LH]
+#define RSCAN0TMTARSTS2H RSCAN0.TMTARSTS2.UINT16[H]
+#define RSCAN0TMTARSTS2HL RSCAN0.TMTARSTS2.UINT8[HL]
+#define RSCAN0TMTARSTS2HH RSCAN0.TMTARSTS2.UINT8[HH]
+#define RSCAN0TMTCSTS0 RSCAN0.TMTCSTS0.UINT32
+#define RSCAN0TMTCSTS0L RSCAN0.TMTCSTS0.UINT16[L]
+#define RSCAN0TMTCSTS0LL RSCAN0.TMTCSTS0.UINT8[LL]
+#define RSCAN0TMTCSTS0LH RSCAN0.TMTCSTS0.UINT8[LH]
+#define RSCAN0TMTCSTS0H RSCAN0.TMTCSTS0.UINT16[H]
+#define RSCAN0TMTCSTS0HL RSCAN0.TMTCSTS0.UINT8[HL]
+#define RSCAN0TMTCSTS0HH RSCAN0.TMTCSTS0.UINT8[HH]
+#define RSCAN0TMTCSTS1 RSCAN0.TMTCSTS1.UINT32
+#define RSCAN0TMTCSTS1L RSCAN0.TMTCSTS1.UINT16[L]
+#define RSCAN0TMTCSTS1LL RSCAN0.TMTCSTS1.UINT8[LL]
+#define RSCAN0TMTCSTS1LH RSCAN0.TMTCSTS1.UINT8[LH]
+#define RSCAN0TMTCSTS1H RSCAN0.TMTCSTS1.UINT16[H]
+#define RSCAN0TMTCSTS1HL RSCAN0.TMTCSTS1.UINT8[HL]
+#define RSCAN0TMTCSTS1HH RSCAN0.TMTCSTS1.UINT8[HH]
+#define RSCAN0TMTCSTS2 RSCAN0.TMTCSTS2.UINT32
+#define RSCAN0TMTCSTS2L RSCAN0.TMTCSTS2.UINT16[L]
+#define RSCAN0TMTCSTS2LL RSCAN0.TMTCSTS2.UINT8[LL]
+#define RSCAN0TMTCSTS2LH RSCAN0.TMTCSTS2.UINT8[LH]
+#define RSCAN0TMTCSTS2H RSCAN0.TMTCSTS2.UINT16[H]
+#define RSCAN0TMTCSTS2HL RSCAN0.TMTCSTS2.UINT8[HL]
+#define RSCAN0TMTCSTS2HH RSCAN0.TMTCSTS2.UINT8[HH]
+#define RSCAN0TMTASTS0 RSCAN0.TMTASTS0.UINT32
+#define RSCAN0TMTASTS0L RSCAN0.TMTASTS0.UINT16[L]
+#define RSCAN0TMTASTS0LL RSCAN0.TMTASTS0.UINT8[LL]
+#define RSCAN0TMTASTS0LH RSCAN0.TMTASTS0.UINT8[LH]
+#define RSCAN0TMTASTS0H RSCAN0.TMTASTS0.UINT16[H]
+#define RSCAN0TMTASTS0HL RSCAN0.TMTASTS0.UINT8[HL]
+#define RSCAN0TMTASTS0HH RSCAN0.TMTASTS0.UINT8[HH]
+#define RSCAN0TMTASTS1 RSCAN0.TMTASTS1.UINT32
+#define RSCAN0TMTASTS1L RSCAN0.TMTASTS1.UINT16[L]
+#define RSCAN0TMTASTS1LL RSCAN0.TMTASTS1.UINT8[LL]
+#define RSCAN0TMTASTS1LH RSCAN0.TMTASTS1.UINT8[LH]
+#define RSCAN0TMTASTS1H RSCAN0.TMTASTS1.UINT16[H]
+#define RSCAN0TMTASTS1HL RSCAN0.TMTASTS1.UINT8[HL]
+#define RSCAN0TMTASTS1HH RSCAN0.TMTASTS1.UINT8[HH]
+#define RSCAN0TMTASTS2 RSCAN0.TMTASTS2.UINT32
+#define RSCAN0TMTASTS2L RSCAN0.TMTASTS2.UINT16[L]
+#define RSCAN0TMTASTS2LL RSCAN0.TMTASTS2.UINT8[LL]
+#define RSCAN0TMTASTS2LH RSCAN0.TMTASTS2.UINT8[LH]
+#define RSCAN0TMTASTS2H RSCAN0.TMTASTS2.UINT16[H]
+#define RSCAN0TMTASTS2HL RSCAN0.TMTASTS2.UINT8[HL]
+#define RSCAN0TMTASTS2HH RSCAN0.TMTASTS2.UINT8[HH]
+#define RSCAN0TMIEC0 RSCAN0.TMIEC0.UINT32
+#define RSCAN0TMIEC0L RSCAN0.TMIEC0.UINT16[L]
+#define RSCAN0TMIEC0LL RSCAN0.TMIEC0.UINT8[LL]
+#define RSCAN0TMIEC0LH RSCAN0.TMIEC0.UINT8[LH]
+#define RSCAN0TMIEC0H RSCAN0.TMIEC0.UINT16[H]
+#define RSCAN0TMIEC0HL RSCAN0.TMIEC0.UINT8[HL]
+#define RSCAN0TMIEC0HH RSCAN0.TMIEC0.UINT8[HH]
+#define RSCAN0TMIEC1 RSCAN0.TMIEC1.UINT32
+#define RSCAN0TMIEC1L RSCAN0.TMIEC1.UINT16[L]
+#define RSCAN0TMIEC1LL RSCAN0.TMIEC1.UINT8[LL]
+#define RSCAN0TMIEC1LH RSCAN0.TMIEC1.UINT8[LH]
+#define RSCAN0TMIEC1H RSCAN0.TMIEC1.UINT16[H]
+#define RSCAN0TMIEC1HL RSCAN0.TMIEC1.UINT8[HL]
+#define RSCAN0TMIEC1HH RSCAN0.TMIEC1.UINT8[HH]
+#define RSCAN0TMIEC2 RSCAN0.TMIEC2.UINT32
+#define RSCAN0TMIEC2L RSCAN0.TMIEC2.UINT16[L]
+#define RSCAN0TMIEC2LL RSCAN0.TMIEC2.UINT8[LL]
+#define RSCAN0TMIEC2LH RSCAN0.TMIEC2.UINT8[LH]
+#define RSCAN0TMIEC2H RSCAN0.TMIEC2.UINT16[H]
+#define RSCAN0TMIEC2HL RSCAN0.TMIEC2.UINT8[HL]
+#define RSCAN0TMIEC2HH RSCAN0.TMIEC2.UINT8[HH]
+#define RSCAN0TXQCC0 RSCAN0.TXQCC0.UINT32
+#define RSCAN0TXQCC0L RSCAN0.TXQCC0.UINT16[L]
+#define RSCAN0TXQCC0LL RSCAN0.TXQCC0.UINT8[LL]
+#define RSCAN0TXQCC0LH RSCAN0.TXQCC0.UINT8[LH]
+#define RSCAN0TXQCC0H RSCAN0.TXQCC0.UINT16[H]
+#define RSCAN0TXQCC0HL RSCAN0.TXQCC0.UINT8[HL]
+#define RSCAN0TXQCC0HH RSCAN0.TXQCC0.UINT8[HH]
+#define RSCAN0TXQCC1 RSCAN0.TXQCC1.UINT32
+#define RSCAN0TXQCC1L RSCAN0.TXQCC1.UINT16[L]
+#define RSCAN0TXQCC1LL RSCAN0.TXQCC1.UINT8[LL]
+#define RSCAN0TXQCC1LH RSCAN0.TXQCC1.UINT8[LH]
+#define RSCAN0TXQCC1H RSCAN0.TXQCC1.UINT16[H]
+#define RSCAN0TXQCC1HL RSCAN0.TXQCC1.UINT8[HL]
+#define RSCAN0TXQCC1HH RSCAN0.TXQCC1.UINT8[HH]
+#define RSCAN0TXQCC2 RSCAN0.TXQCC2.UINT32
+#define RSCAN0TXQCC2L RSCAN0.TXQCC2.UINT16[L]
+#define RSCAN0TXQCC2LL RSCAN0.TXQCC2.UINT8[LL]
+#define RSCAN0TXQCC2LH RSCAN0.TXQCC2.UINT8[LH]
+#define RSCAN0TXQCC2H RSCAN0.TXQCC2.UINT16[H]
+#define RSCAN0TXQCC2HL RSCAN0.TXQCC2.UINT8[HL]
+#define RSCAN0TXQCC2HH RSCAN0.TXQCC2.UINT8[HH]
+#define RSCAN0TXQCC3 RSCAN0.TXQCC3.UINT32
+#define RSCAN0TXQCC3L RSCAN0.TXQCC3.UINT16[L]
+#define RSCAN0TXQCC3LL RSCAN0.TXQCC3.UINT8[LL]
+#define RSCAN0TXQCC3LH RSCAN0.TXQCC3.UINT8[LH]
+#define RSCAN0TXQCC3H RSCAN0.TXQCC3.UINT16[H]
+#define RSCAN0TXQCC3HL RSCAN0.TXQCC3.UINT8[HL]
+#define RSCAN0TXQCC3HH RSCAN0.TXQCC3.UINT8[HH]
+#define RSCAN0TXQCC4 RSCAN0.TXQCC4.UINT32
+#define RSCAN0TXQCC4L RSCAN0.TXQCC4.UINT16[L]
+#define RSCAN0TXQCC4LL RSCAN0.TXQCC4.UINT8[LL]
+#define RSCAN0TXQCC4LH RSCAN0.TXQCC4.UINT8[LH]
+#define RSCAN0TXQCC4H RSCAN0.TXQCC4.UINT16[H]
+#define RSCAN0TXQCC4HL RSCAN0.TXQCC4.UINT8[HL]
+#define RSCAN0TXQCC4HH RSCAN0.TXQCC4.UINT8[HH]
+#define RSCAN0TXQSTS0 RSCAN0.TXQSTS0.UINT32
+#define RSCAN0TXQSTS0L RSCAN0.TXQSTS0.UINT16[L]
+#define RSCAN0TXQSTS0LL RSCAN0.TXQSTS0.UINT8[LL]
+#define RSCAN0TXQSTS0LH RSCAN0.TXQSTS0.UINT8[LH]
+#define RSCAN0TXQSTS0H RSCAN0.TXQSTS0.UINT16[H]
+#define RSCAN0TXQSTS0HL RSCAN0.TXQSTS0.UINT8[HL]
+#define RSCAN0TXQSTS0HH RSCAN0.TXQSTS0.UINT8[HH]
+#define RSCAN0TXQSTS1 RSCAN0.TXQSTS1.UINT32
+#define RSCAN0TXQSTS1L RSCAN0.TXQSTS1.UINT16[L]
+#define RSCAN0TXQSTS1LL RSCAN0.TXQSTS1.UINT8[LL]
+#define RSCAN0TXQSTS1LH RSCAN0.TXQSTS1.UINT8[LH]
+#define RSCAN0TXQSTS1H RSCAN0.TXQSTS1.UINT16[H]
+#define RSCAN0TXQSTS1HL RSCAN0.TXQSTS1.UINT8[HL]
+#define RSCAN0TXQSTS1HH RSCAN0.TXQSTS1.UINT8[HH]
+#define RSCAN0TXQSTS2 RSCAN0.TXQSTS2.UINT32
+#define RSCAN0TXQSTS2L RSCAN0.TXQSTS2.UINT16[L]
+#define RSCAN0TXQSTS2LL RSCAN0.TXQSTS2.UINT8[LL]
+#define RSCAN0TXQSTS2LH RSCAN0.TXQSTS2.UINT8[LH]
+#define RSCAN0TXQSTS2H RSCAN0.TXQSTS2.UINT16[H]
+#define RSCAN0TXQSTS2HL RSCAN0.TXQSTS2.UINT8[HL]
+#define RSCAN0TXQSTS2HH RSCAN0.TXQSTS2.UINT8[HH]
+#define RSCAN0TXQSTS3 RSCAN0.TXQSTS3.UINT32
+#define RSCAN0TXQSTS3L RSCAN0.TXQSTS3.UINT16[L]
+#define RSCAN0TXQSTS3LL RSCAN0.TXQSTS3.UINT8[LL]
+#define RSCAN0TXQSTS3LH RSCAN0.TXQSTS3.UINT8[LH]
+#define RSCAN0TXQSTS3H RSCAN0.TXQSTS3.UINT16[H]
+#define RSCAN0TXQSTS3HL RSCAN0.TXQSTS3.UINT8[HL]
+#define RSCAN0TXQSTS3HH RSCAN0.TXQSTS3.UINT8[HH]
+#define RSCAN0TXQSTS4 RSCAN0.TXQSTS4.UINT32
+#define RSCAN0TXQSTS4L RSCAN0.TXQSTS4.UINT16[L]
+#define RSCAN0TXQSTS4LL RSCAN0.TXQSTS4.UINT8[LL]
+#define RSCAN0TXQSTS4LH RSCAN0.TXQSTS4.UINT8[LH]
+#define RSCAN0TXQSTS4H RSCAN0.TXQSTS4.UINT16[H]
+#define RSCAN0TXQSTS4HL RSCAN0.TXQSTS4.UINT8[HL]
+#define RSCAN0TXQSTS4HH RSCAN0.TXQSTS4.UINT8[HH]
+#define RSCAN0TXQPCTR0 RSCAN0.TXQPCTR0.UINT32
+#define RSCAN0TXQPCTR0L RSCAN0.TXQPCTR0.UINT16[L]
+#define RSCAN0TXQPCTR0LL RSCAN0.TXQPCTR0.UINT8[LL]
+#define RSCAN0TXQPCTR0LH RSCAN0.TXQPCTR0.UINT8[LH]
+#define RSCAN0TXQPCTR0H RSCAN0.TXQPCTR0.UINT16[H]
+#define RSCAN0TXQPCTR0HL RSCAN0.TXQPCTR0.UINT8[HL]
+#define RSCAN0TXQPCTR0HH RSCAN0.TXQPCTR0.UINT8[HH]
+#define RSCAN0TXQPCTR1 RSCAN0.TXQPCTR1.UINT32
+#define RSCAN0TXQPCTR1L RSCAN0.TXQPCTR1.UINT16[L]
+#define RSCAN0TXQPCTR1LL RSCAN0.TXQPCTR1.UINT8[LL]
+#define RSCAN0TXQPCTR1LH RSCAN0.TXQPCTR1.UINT8[LH]
+#define RSCAN0TXQPCTR1H RSCAN0.TXQPCTR1.UINT16[H]
+#define RSCAN0TXQPCTR1HL RSCAN0.TXQPCTR1.UINT8[HL]
+#define RSCAN0TXQPCTR1HH RSCAN0.TXQPCTR1.UINT8[HH]
+#define RSCAN0TXQPCTR2 RSCAN0.TXQPCTR2.UINT32
+#define RSCAN0TXQPCTR2L RSCAN0.TXQPCTR2.UINT16[L]
+#define RSCAN0TXQPCTR2LL RSCAN0.TXQPCTR2.UINT8[LL]
+#define RSCAN0TXQPCTR2LH RSCAN0.TXQPCTR2.UINT8[LH]
+#define RSCAN0TXQPCTR2H RSCAN0.TXQPCTR2.UINT16[H]
+#define RSCAN0TXQPCTR2HL RSCAN0.TXQPCTR2.UINT8[HL]
+#define RSCAN0TXQPCTR2HH RSCAN0.TXQPCTR2.UINT8[HH]
+#define RSCAN0TXQPCTR3 RSCAN0.TXQPCTR3.UINT32
+#define RSCAN0TXQPCTR3L RSCAN0.TXQPCTR3.UINT16[L]
+#define RSCAN0TXQPCTR3LL RSCAN0.TXQPCTR3.UINT8[LL]
+#define RSCAN0TXQPCTR3LH RSCAN0.TXQPCTR3.UINT8[LH]
+#define RSCAN0TXQPCTR3H RSCAN0.TXQPCTR3.UINT16[H]
+#define RSCAN0TXQPCTR3HL RSCAN0.TXQPCTR3.UINT8[HL]
+#define RSCAN0TXQPCTR3HH RSCAN0.TXQPCTR3.UINT8[HH]
+#define RSCAN0TXQPCTR4 RSCAN0.TXQPCTR4.UINT32
+#define RSCAN0TXQPCTR4L RSCAN0.TXQPCTR4.UINT16[L]
+#define RSCAN0TXQPCTR4LL RSCAN0.TXQPCTR4.UINT8[LL]
+#define RSCAN0TXQPCTR4LH RSCAN0.TXQPCTR4.UINT8[LH]
+#define RSCAN0TXQPCTR4H RSCAN0.TXQPCTR4.UINT16[H]
+#define RSCAN0TXQPCTR4HL RSCAN0.TXQPCTR4.UINT8[HL]
+#define RSCAN0TXQPCTR4HH RSCAN0.TXQPCTR4.UINT8[HH]
+#define RSCAN0THLCC0 RSCAN0.THLCC0.UINT32
+#define RSCAN0THLCC0L RSCAN0.THLCC0.UINT16[L]
+#define RSCAN0THLCC0LL RSCAN0.THLCC0.UINT8[LL]
+#define RSCAN0THLCC0LH RSCAN0.THLCC0.UINT8[LH]
+#define RSCAN0THLCC0H RSCAN0.THLCC0.UINT16[H]
+#define RSCAN0THLCC0HL RSCAN0.THLCC0.UINT8[HL]
+#define RSCAN0THLCC0HH RSCAN0.THLCC0.UINT8[HH]
+#define RSCAN0THLCC1 RSCAN0.THLCC1.UINT32
+#define RSCAN0THLCC1L RSCAN0.THLCC1.UINT16[L]
+#define RSCAN0THLCC1LL RSCAN0.THLCC1.UINT8[LL]
+#define RSCAN0THLCC1LH RSCAN0.THLCC1.UINT8[LH]
+#define RSCAN0THLCC1H RSCAN0.THLCC1.UINT16[H]
+#define RSCAN0THLCC1HL RSCAN0.THLCC1.UINT8[HL]
+#define RSCAN0THLCC1HH RSCAN0.THLCC1.UINT8[HH]
+#define RSCAN0THLCC2 RSCAN0.THLCC2.UINT32
+#define RSCAN0THLCC2L RSCAN0.THLCC2.UINT16[L]
+#define RSCAN0THLCC2LL RSCAN0.THLCC2.UINT8[LL]
+#define RSCAN0THLCC2LH RSCAN0.THLCC2.UINT8[LH]
+#define RSCAN0THLCC2H RSCAN0.THLCC2.UINT16[H]
+#define RSCAN0THLCC2HL RSCAN0.THLCC2.UINT8[HL]
+#define RSCAN0THLCC2HH RSCAN0.THLCC2.UINT8[HH]
+#define RSCAN0THLCC3 RSCAN0.THLCC3.UINT32
+#define RSCAN0THLCC3L RSCAN0.THLCC3.UINT16[L]
+#define RSCAN0THLCC3LL RSCAN0.THLCC3.UINT8[LL]
+#define RSCAN0THLCC3LH RSCAN0.THLCC3.UINT8[LH]
+#define RSCAN0THLCC3H RSCAN0.THLCC3.UINT16[H]
+#define RSCAN0THLCC3HL RSCAN0.THLCC3.UINT8[HL]
+#define RSCAN0THLCC3HH RSCAN0.THLCC3.UINT8[HH]
+#define RSCAN0THLCC4 RSCAN0.THLCC4.UINT32
+#define RSCAN0THLCC4L RSCAN0.THLCC4.UINT16[L]
+#define RSCAN0THLCC4LL RSCAN0.THLCC4.UINT8[LL]
+#define RSCAN0THLCC4LH RSCAN0.THLCC4.UINT8[LH]
+#define RSCAN0THLCC4H RSCAN0.THLCC4.UINT16[H]
+#define RSCAN0THLCC4HL RSCAN0.THLCC4.UINT8[HL]
+#define RSCAN0THLCC4HH RSCAN0.THLCC4.UINT8[HH]
+#define RSCAN0THLSTS0 RSCAN0.THLSTS0.UINT32
+#define RSCAN0THLSTS0L RSCAN0.THLSTS0.UINT16[L]
+#define RSCAN0THLSTS0LL RSCAN0.THLSTS0.UINT8[LL]
+#define RSCAN0THLSTS0LH RSCAN0.THLSTS0.UINT8[LH]
+#define RSCAN0THLSTS0H RSCAN0.THLSTS0.UINT16[H]
+#define RSCAN0THLSTS0HL RSCAN0.THLSTS0.UINT8[HL]
+#define RSCAN0THLSTS0HH RSCAN0.THLSTS0.UINT8[HH]
+#define RSCAN0THLSTS1 RSCAN0.THLSTS1.UINT32
+#define RSCAN0THLSTS1L RSCAN0.THLSTS1.UINT16[L]
+#define RSCAN0THLSTS1LL RSCAN0.THLSTS1.UINT8[LL]
+#define RSCAN0THLSTS1LH RSCAN0.THLSTS1.UINT8[LH]
+#define RSCAN0THLSTS1H RSCAN0.THLSTS1.UINT16[H]
+#define RSCAN0THLSTS1HL RSCAN0.THLSTS1.UINT8[HL]
+#define RSCAN0THLSTS1HH RSCAN0.THLSTS1.UINT8[HH]
+#define RSCAN0THLSTS2 RSCAN0.THLSTS2.UINT32
+#define RSCAN0THLSTS2L RSCAN0.THLSTS2.UINT16[L]
+#define RSCAN0THLSTS2LL RSCAN0.THLSTS2.UINT8[LL]
+#define RSCAN0THLSTS2LH RSCAN0.THLSTS2.UINT8[LH]
+#define RSCAN0THLSTS2H RSCAN0.THLSTS2.UINT16[H]
+#define RSCAN0THLSTS2HL RSCAN0.THLSTS2.UINT8[HL]
+#define RSCAN0THLSTS2HH RSCAN0.THLSTS2.UINT8[HH]
+#define RSCAN0THLSTS3 RSCAN0.THLSTS3.UINT32
+#define RSCAN0THLSTS3L RSCAN0.THLSTS3.UINT16[L]
+#define RSCAN0THLSTS3LL RSCAN0.THLSTS3.UINT8[LL]
+#define RSCAN0THLSTS3LH RSCAN0.THLSTS3.UINT8[LH]
+#define RSCAN0THLSTS3H RSCAN0.THLSTS3.UINT16[H]
+#define RSCAN0THLSTS3HL RSCAN0.THLSTS3.UINT8[HL]
+#define RSCAN0THLSTS3HH RSCAN0.THLSTS3.UINT8[HH]
+#define RSCAN0THLSTS4 RSCAN0.THLSTS4.UINT32
+#define RSCAN0THLSTS4L RSCAN0.THLSTS4.UINT16[L]
+#define RSCAN0THLSTS4LL RSCAN0.THLSTS4.UINT8[LL]
+#define RSCAN0THLSTS4LH RSCAN0.THLSTS4.UINT8[LH]
+#define RSCAN0THLSTS4H RSCAN0.THLSTS4.UINT16[H]
+#define RSCAN0THLSTS4HL RSCAN0.THLSTS4.UINT8[HL]
+#define RSCAN0THLSTS4HH RSCAN0.THLSTS4.UINT8[HH]
+#define RSCAN0THLPCTR0 RSCAN0.THLPCTR0.UINT32
+#define RSCAN0THLPCTR0L RSCAN0.THLPCTR0.UINT16[L]
+#define RSCAN0THLPCTR0LL RSCAN0.THLPCTR0.UINT8[LL]
+#define RSCAN0THLPCTR0LH RSCAN0.THLPCTR0.UINT8[LH]
+#define RSCAN0THLPCTR0H RSCAN0.THLPCTR0.UINT16[H]
+#define RSCAN0THLPCTR0HL RSCAN0.THLPCTR0.UINT8[HL]
+#define RSCAN0THLPCTR0HH RSCAN0.THLPCTR0.UINT8[HH]
+#define RSCAN0THLPCTR1 RSCAN0.THLPCTR1.UINT32
+#define RSCAN0THLPCTR1L RSCAN0.THLPCTR1.UINT16[L]
+#define RSCAN0THLPCTR1LL RSCAN0.THLPCTR1.UINT8[LL]
+#define RSCAN0THLPCTR1LH RSCAN0.THLPCTR1.UINT8[LH]
+#define RSCAN0THLPCTR1H RSCAN0.THLPCTR1.UINT16[H]
+#define RSCAN0THLPCTR1HL RSCAN0.THLPCTR1.UINT8[HL]
+#define RSCAN0THLPCTR1HH RSCAN0.THLPCTR1.UINT8[HH]
+#define RSCAN0THLPCTR2 RSCAN0.THLPCTR2.UINT32
+#define RSCAN0THLPCTR2L RSCAN0.THLPCTR2.UINT16[L]
+#define RSCAN0THLPCTR2LL RSCAN0.THLPCTR2.UINT8[LL]
+#define RSCAN0THLPCTR2LH RSCAN0.THLPCTR2.UINT8[LH]
+#define RSCAN0THLPCTR2H RSCAN0.THLPCTR2.UINT16[H]
+#define RSCAN0THLPCTR2HL RSCAN0.THLPCTR2.UINT8[HL]
+#define RSCAN0THLPCTR2HH RSCAN0.THLPCTR2.UINT8[HH]
+#define RSCAN0THLPCTR3 RSCAN0.THLPCTR3.UINT32
+#define RSCAN0THLPCTR3L RSCAN0.THLPCTR3.UINT16[L]
+#define RSCAN0THLPCTR3LL RSCAN0.THLPCTR3.UINT8[LL]
+#define RSCAN0THLPCTR3LH RSCAN0.THLPCTR3.UINT8[LH]
+#define RSCAN0THLPCTR3H RSCAN0.THLPCTR3.UINT16[H]
+#define RSCAN0THLPCTR3HL RSCAN0.THLPCTR3.UINT8[HL]
+#define RSCAN0THLPCTR3HH RSCAN0.THLPCTR3.UINT8[HH]
+#define RSCAN0THLPCTR4 RSCAN0.THLPCTR4.UINT32
+#define RSCAN0THLPCTR4L RSCAN0.THLPCTR4.UINT16[L]
+#define RSCAN0THLPCTR4LL RSCAN0.THLPCTR4.UINT8[LL]
+#define RSCAN0THLPCTR4LH RSCAN0.THLPCTR4.UINT8[LH]
+#define RSCAN0THLPCTR4H RSCAN0.THLPCTR4.UINT16[H]
+#define RSCAN0THLPCTR4HL RSCAN0.THLPCTR4.UINT8[HL]
+#define RSCAN0THLPCTR4HH RSCAN0.THLPCTR4.UINT8[HH]
+#define RSCAN0GTINTSTS0 RSCAN0.GTINTSTS0.UINT32
+#define RSCAN0GTINTSTS0L RSCAN0.GTINTSTS0.UINT16[L]
+#define RSCAN0GTINTSTS0LL RSCAN0.GTINTSTS0.UINT8[LL]
+#define RSCAN0GTINTSTS0LH RSCAN0.GTINTSTS0.UINT8[LH]
+#define RSCAN0GTINTSTS0H RSCAN0.GTINTSTS0.UINT16[H]
+#define RSCAN0GTINTSTS0HL RSCAN0.GTINTSTS0.UINT8[HL]
+#define RSCAN0GTINTSTS0HH RSCAN0.GTINTSTS0.UINT8[HH]
+#define RSCAN0GTINTSTS1 RSCAN0.GTINTSTS1.UINT32
+#define RSCAN0GTINTSTS1L RSCAN0.GTINTSTS1.UINT16[L]
+#define RSCAN0GTINTSTS1LL RSCAN0.GTINTSTS1.UINT8[LL]
+#define RSCAN0GTINTSTS1LH RSCAN0.GTINTSTS1.UINT8[LH]
+#define RSCAN0GTINTSTS1H RSCAN0.GTINTSTS1.UINT16[H]
+#define RSCAN0GTINTSTS1HL RSCAN0.GTINTSTS1.UINT8[HL]
+#define RSCAN0GTINTSTS1HH RSCAN0.GTINTSTS1.UINT8[HH]
+#define RSCAN0GTSTCFG RSCAN0.GTSTCFG.UINT32
+#define RSCAN0GTSTCFGL RSCAN0.GTSTCFG.UINT16[L]
+#define RSCAN0GTSTCFGLL RSCAN0.GTSTCFG.UINT8[LL]
+#define RSCAN0GTSTCFGLH RSCAN0.GTSTCFG.UINT8[LH]
+#define RSCAN0GTSTCFGH RSCAN0.GTSTCFG.UINT16[H]
+#define RSCAN0GTSTCFGHL RSCAN0.GTSTCFG.UINT8[HL]
+#define RSCAN0GTSTCFGHH RSCAN0.GTSTCFG.UINT8[HH]
+#define RSCAN0GTSTCTR RSCAN0.GTSTCTR.UINT32
+#define RSCAN0GTSTCTRL RSCAN0.GTSTCTR.UINT16[L]
+#define RSCAN0GTSTCTRLL RSCAN0.GTSTCTR.UINT8[LL]
+#define RSCAN0GTSTCTRLH RSCAN0.GTSTCTR.UINT8[LH]
+#define RSCAN0GTSTCTRH RSCAN0.GTSTCTR.UINT16[H]
+#define RSCAN0GTSTCTRHL RSCAN0.GTSTCTR.UINT8[HL]
+#define RSCAN0GTSTCTRHH RSCAN0.GTSTCTR.UINT8[HH]
+#define RSCAN0GLOCKK RSCAN0.GLOCKK.UINT32
+#define RSCAN0GLOCKKL RSCAN0.GLOCKK.UINT16[L]
+#define RSCAN0GLOCKKH RSCAN0.GLOCKK.UINT16[H]
+#define RSCAN0GAFLID0 RSCAN0.GAFLID0.UINT32
+#define RSCAN0GAFLID0L RSCAN0.GAFLID0.UINT16[L]
+#define RSCAN0GAFLID0LL RSCAN0.GAFLID0.UINT8[LL]
+#define RSCAN0GAFLID0LH RSCAN0.GAFLID0.UINT8[LH]
+#define RSCAN0GAFLID0H RSCAN0.GAFLID0.UINT16[H]
+#define RSCAN0GAFLID0HL RSCAN0.GAFLID0.UINT8[HL]
+#define RSCAN0GAFLID0HH RSCAN0.GAFLID0.UINT8[HH]
+#define RSCAN0GAFLM0 RSCAN0.GAFLM0.UINT32
+#define RSCAN0GAFLM0L RSCAN0.GAFLM0.UINT16[L]
+#define RSCAN0GAFLM0LL RSCAN0.GAFLM0.UINT8[LL]
+#define RSCAN0GAFLM0LH RSCAN0.GAFLM0.UINT8[LH]
+#define RSCAN0GAFLM0H RSCAN0.GAFLM0.UINT16[H]
+#define RSCAN0GAFLM0HL RSCAN0.GAFLM0.UINT8[HL]
+#define RSCAN0GAFLM0HH RSCAN0.GAFLM0.UINT8[HH]
+#define RSCAN0GAFLP00 RSCAN0.GAFLP00.UINT32
+#define RSCAN0GAFLP00L RSCAN0.GAFLP00.UINT16[L]
+#define RSCAN0GAFLP00LL RSCAN0.GAFLP00.UINT8[LL]
+#define RSCAN0GAFLP00LH RSCAN0.GAFLP00.UINT8[LH]
+#define RSCAN0GAFLP00H RSCAN0.GAFLP00.UINT16[H]
+#define RSCAN0GAFLP00HL RSCAN0.GAFLP00.UINT8[HL]
+#define RSCAN0GAFLP00HH RSCAN0.GAFLP00.UINT8[HH]
+#define RSCAN0GAFLP10 RSCAN0.GAFLP10.UINT32
+#define RSCAN0GAFLP10L RSCAN0.GAFLP10.UINT16[L]
+#define RSCAN0GAFLP10LL RSCAN0.GAFLP10.UINT8[LL]
+#define RSCAN0GAFLP10LH RSCAN0.GAFLP10.UINT8[LH]
+#define RSCAN0GAFLP10H RSCAN0.GAFLP10.UINT16[H]
+#define RSCAN0GAFLP10HL RSCAN0.GAFLP10.UINT8[HL]
+#define RSCAN0GAFLP10HH RSCAN0.GAFLP10.UINT8[HH]
+#define RSCAN0GAFLID1 RSCAN0.GAFLID1.UINT32
+#define RSCAN0GAFLID1L RSCAN0.GAFLID1.UINT16[L]
+#define RSCAN0GAFLID1LL RSCAN0.GAFLID1.UINT8[LL]
+#define RSCAN0GAFLID1LH RSCAN0.GAFLID1.UINT8[LH]
+#define RSCAN0GAFLID1H RSCAN0.GAFLID1.UINT16[H]
+#define RSCAN0GAFLID1HL RSCAN0.GAFLID1.UINT8[HL]
+#define RSCAN0GAFLID1HH RSCAN0.GAFLID1.UINT8[HH]
+#define RSCAN0GAFLM1 RSCAN0.GAFLM1.UINT32
+#define RSCAN0GAFLM1L RSCAN0.GAFLM1.UINT16[L]
+#define RSCAN0GAFLM1LL RSCAN0.GAFLM1.UINT8[LL]
+#define RSCAN0GAFLM1LH RSCAN0.GAFLM1.UINT8[LH]
+#define RSCAN0GAFLM1H RSCAN0.GAFLM1.UINT16[H]
+#define RSCAN0GAFLM1HL RSCAN0.GAFLM1.UINT8[HL]
+#define RSCAN0GAFLM1HH RSCAN0.GAFLM1.UINT8[HH]
+#define RSCAN0GAFLP01 RSCAN0.GAFLP01.UINT32
+#define RSCAN0GAFLP01L RSCAN0.GAFLP01.UINT16[L]
+#define RSCAN0GAFLP01LL RSCAN0.GAFLP01.UINT8[LL]
+#define RSCAN0GAFLP01LH RSCAN0.GAFLP01.UINT8[LH]
+#define RSCAN0GAFLP01H RSCAN0.GAFLP01.UINT16[H]
+#define RSCAN0GAFLP01HL RSCAN0.GAFLP01.UINT8[HL]
+#define RSCAN0GAFLP01HH RSCAN0.GAFLP01.UINT8[HH]
+#define RSCAN0GAFLP11 RSCAN0.GAFLP11.UINT32
+#define RSCAN0GAFLP11L RSCAN0.GAFLP11.UINT16[L]
+#define RSCAN0GAFLP11LL RSCAN0.GAFLP11.UINT8[LL]
+#define RSCAN0GAFLP11LH RSCAN0.GAFLP11.UINT8[LH]
+#define RSCAN0GAFLP11H RSCAN0.GAFLP11.UINT16[H]
+#define RSCAN0GAFLP11HL RSCAN0.GAFLP11.UINT8[HL]
+#define RSCAN0GAFLP11HH RSCAN0.GAFLP11.UINT8[HH]
+#define RSCAN0GAFLID2 RSCAN0.GAFLID2.UINT32
+#define RSCAN0GAFLID2L RSCAN0.GAFLID2.UINT16[L]
+#define RSCAN0GAFLID2LL RSCAN0.GAFLID2.UINT8[LL]
+#define RSCAN0GAFLID2LH RSCAN0.GAFLID2.UINT8[LH]
+#define RSCAN0GAFLID2H RSCAN0.GAFLID2.UINT16[H]
+#define RSCAN0GAFLID2HL RSCAN0.GAFLID2.UINT8[HL]
+#define RSCAN0GAFLID2HH RSCAN0.GAFLID2.UINT8[HH]
+#define RSCAN0GAFLM2 RSCAN0.GAFLM2.UINT32
+#define RSCAN0GAFLM2L RSCAN0.GAFLM2.UINT16[L]
+#define RSCAN0GAFLM2LL RSCAN0.GAFLM2.UINT8[LL]
+#define RSCAN0GAFLM2LH RSCAN0.GAFLM2.UINT8[LH]
+#define RSCAN0GAFLM2H RSCAN0.GAFLM2.UINT16[H]
+#define RSCAN0GAFLM2HL RSCAN0.GAFLM2.UINT8[HL]
+#define RSCAN0GAFLM2HH RSCAN0.GAFLM2.UINT8[HH]
+#define RSCAN0GAFLP02 RSCAN0.GAFLP02.UINT32
+#define RSCAN0GAFLP02L RSCAN0.GAFLP02.UINT16[L]
+#define RSCAN0GAFLP02LL RSCAN0.GAFLP02.UINT8[LL]
+#define RSCAN0GAFLP02LH RSCAN0.GAFLP02.UINT8[LH]
+#define RSCAN0GAFLP02H RSCAN0.GAFLP02.UINT16[H]
+#define RSCAN0GAFLP02HL RSCAN0.GAFLP02.UINT8[HL]
+#define RSCAN0GAFLP02HH RSCAN0.GAFLP02.UINT8[HH]
+#define RSCAN0GAFLP12 RSCAN0.GAFLP12.UINT32
+#define RSCAN0GAFLP12L RSCAN0.GAFLP12.UINT16[L]
+#define RSCAN0GAFLP12LL RSCAN0.GAFLP12.UINT8[LL]
+#define RSCAN0GAFLP12LH RSCAN0.GAFLP12.UINT8[LH]
+#define RSCAN0GAFLP12H RSCAN0.GAFLP12.UINT16[H]
+#define RSCAN0GAFLP12HL RSCAN0.GAFLP12.UINT8[HL]
+#define RSCAN0GAFLP12HH RSCAN0.GAFLP12.UINT8[HH]
+#define RSCAN0GAFLID3 RSCAN0.GAFLID3.UINT32
+#define RSCAN0GAFLID3L RSCAN0.GAFLID3.UINT16[L]
+#define RSCAN0GAFLID3LL RSCAN0.GAFLID3.UINT8[LL]
+#define RSCAN0GAFLID3LH RSCAN0.GAFLID3.UINT8[LH]
+#define RSCAN0GAFLID3H RSCAN0.GAFLID3.UINT16[H]
+#define RSCAN0GAFLID3HL RSCAN0.GAFLID3.UINT8[HL]
+#define RSCAN0GAFLID3HH RSCAN0.GAFLID3.UINT8[HH]
+#define RSCAN0GAFLM3 RSCAN0.GAFLM3.UINT32
+#define RSCAN0GAFLM3L RSCAN0.GAFLM3.UINT16[L]
+#define RSCAN0GAFLM3LL RSCAN0.GAFLM3.UINT8[LL]
+#define RSCAN0GAFLM3LH RSCAN0.GAFLM3.UINT8[LH]
+#define RSCAN0GAFLM3H RSCAN0.GAFLM3.UINT16[H]
+#define RSCAN0GAFLM3HL RSCAN0.GAFLM3.UINT8[HL]
+#define RSCAN0GAFLM3HH RSCAN0.GAFLM3.UINT8[HH]
+#define RSCAN0GAFLP03 RSCAN0.GAFLP03.UINT32
+#define RSCAN0GAFLP03L RSCAN0.GAFLP03.UINT16[L]
+#define RSCAN0GAFLP03LL RSCAN0.GAFLP03.UINT8[LL]
+#define RSCAN0GAFLP03LH RSCAN0.GAFLP03.UINT8[LH]
+#define RSCAN0GAFLP03H RSCAN0.GAFLP03.UINT16[H]
+#define RSCAN0GAFLP03HL RSCAN0.GAFLP03.UINT8[HL]
+#define RSCAN0GAFLP03HH RSCAN0.GAFLP03.UINT8[HH]
+#define RSCAN0GAFLP13 RSCAN0.GAFLP13.UINT32
+#define RSCAN0GAFLP13L RSCAN0.GAFLP13.UINT16[L]
+#define RSCAN0GAFLP13LL RSCAN0.GAFLP13.UINT8[LL]
+#define RSCAN0GAFLP13LH RSCAN0.GAFLP13.UINT8[LH]
+#define RSCAN0GAFLP13H RSCAN0.GAFLP13.UINT16[H]
+#define RSCAN0GAFLP13HL RSCAN0.GAFLP13.UINT8[HL]
+#define RSCAN0GAFLP13HH RSCAN0.GAFLP13.UINT8[HH]
+#define RSCAN0GAFLID4 RSCAN0.GAFLID4.UINT32
+#define RSCAN0GAFLID4L RSCAN0.GAFLID4.UINT16[L]
+#define RSCAN0GAFLID4LL RSCAN0.GAFLID4.UINT8[LL]
+#define RSCAN0GAFLID4LH RSCAN0.GAFLID4.UINT8[LH]
+#define RSCAN0GAFLID4H RSCAN0.GAFLID4.UINT16[H]
+#define RSCAN0GAFLID4HL RSCAN0.GAFLID4.UINT8[HL]
+#define RSCAN0GAFLID4HH RSCAN0.GAFLID4.UINT8[HH]
+#define RSCAN0GAFLM4 RSCAN0.GAFLM4.UINT32
+#define RSCAN0GAFLM4L RSCAN0.GAFLM4.UINT16[L]
+#define RSCAN0GAFLM4LL RSCAN0.GAFLM4.UINT8[LL]
+#define RSCAN0GAFLM4LH RSCAN0.GAFLM4.UINT8[LH]
+#define RSCAN0GAFLM4H RSCAN0.GAFLM4.UINT16[H]
+#define RSCAN0GAFLM4HL RSCAN0.GAFLM4.UINT8[HL]
+#define RSCAN0GAFLM4HH RSCAN0.GAFLM4.UINT8[HH]
+#define RSCAN0GAFLP04 RSCAN0.GAFLP04.UINT32
+#define RSCAN0GAFLP04L RSCAN0.GAFLP04.UINT16[L]
+#define RSCAN0GAFLP04LL RSCAN0.GAFLP04.UINT8[LL]
+#define RSCAN0GAFLP04LH RSCAN0.GAFLP04.UINT8[LH]
+#define RSCAN0GAFLP04H RSCAN0.GAFLP04.UINT16[H]
+#define RSCAN0GAFLP04HL RSCAN0.GAFLP04.UINT8[HL]
+#define RSCAN0GAFLP04HH RSCAN0.GAFLP04.UINT8[HH]
+#define RSCAN0GAFLP14 RSCAN0.GAFLP14.UINT32
+#define RSCAN0GAFLP14L RSCAN0.GAFLP14.UINT16[L]
+#define RSCAN0GAFLP14LL RSCAN0.GAFLP14.UINT8[LL]
+#define RSCAN0GAFLP14LH RSCAN0.GAFLP14.UINT8[LH]
+#define RSCAN0GAFLP14H RSCAN0.GAFLP14.UINT16[H]
+#define RSCAN0GAFLP14HL RSCAN0.GAFLP14.UINT8[HL]
+#define RSCAN0GAFLP14HH RSCAN0.GAFLP14.UINT8[HH]
+#define RSCAN0GAFLID5 RSCAN0.GAFLID5.UINT32
+#define RSCAN0GAFLID5L RSCAN0.GAFLID5.UINT16[L]
+#define RSCAN0GAFLID5LL RSCAN0.GAFLID5.UINT8[LL]
+#define RSCAN0GAFLID5LH RSCAN0.GAFLID5.UINT8[LH]
+#define RSCAN0GAFLID5H RSCAN0.GAFLID5.UINT16[H]
+#define RSCAN0GAFLID5HL RSCAN0.GAFLID5.UINT8[HL]
+#define RSCAN0GAFLID5HH RSCAN0.GAFLID5.UINT8[HH]
+#define RSCAN0GAFLM5 RSCAN0.GAFLM5.UINT32
+#define RSCAN0GAFLM5L RSCAN0.GAFLM5.UINT16[L]
+#define RSCAN0GAFLM5LL RSCAN0.GAFLM5.UINT8[LL]
+#define RSCAN0GAFLM5LH RSCAN0.GAFLM5.UINT8[LH]
+#define RSCAN0GAFLM5H RSCAN0.GAFLM5.UINT16[H]
+#define RSCAN0GAFLM5HL RSCAN0.GAFLM5.UINT8[HL]
+#define RSCAN0GAFLM5HH RSCAN0.GAFLM5.UINT8[HH]
+#define RSCAN0GAFLP05 RSCAN0.GAFLP05.UINT32
+#define RSCAN0GAFLP05L RSCAN0.GAFLP05.UINT16[L]
+#define RSCAN0GAFLP05LL RSCAN0.GAFLP05.UINT8[LL]
+#define RSCAN0GAFLP05LH RSCAN0.GAFLP05.UINT8[LH]
+#define RSCAN0GAFLP05H RSCAN0.GAFLP05.UINT16[H]
+#define RSCAN0GAFLP05HL RSCAN0.GAFLP05.UINT8[HL]
+#define RSCAN0GAFLP05HH RSCAN0.GAFLP05.UINT8[HH]
+#define RSCAN0GAFLP15 RSCAN0.GAFLP15.UINT32
+#define RSCAN0GAFLP15L RSCAN0.GAFLP15.UINT16[L]
+#define RSCAN0GAFLP15LL RSCAN0.GAFLP15.UINT8[LL]
+#define RSCAN0GAFLP15LH RSCAN0.GAFLP15.UINT8[LH]
+#define RSCAN0GAFLP15H RSCAN0.GAFLP15.UINT16[H]
+#define RSCAN0GAFLP15HL RSCAN0.GAFLP15.UINT8[HL]
+#define RSCAN0GAFLP15HH RSCAN0.GAFLP15.UINT8[HH]
+#define RSCAN0GAFLID6 RSCAN0.GAFLID6.UINT32
+#define RSCAN0GAFLID6L RSCAN0.GAFLID6.UINT16[L]
+#define RSCAN0GAFLID6LL RSCAN0.GAFLID6.UINT8[LL]
+#define RSCAN0GAFLID6LH RSCAN0.GAFLID6.UINT8[LH]
+#define RSCAN0GAFLID6H RSCAN0.GAFLID6.UINT16[H]
+#define RSCAN0GAFLID6HL RSCAN0.GAFLID6.UINT8[HL]
+#define RSCAN0GAFLID6HH RSCAN0.GAFLID6.UINT8[HH]
+#define RSCAN0GAFLM6 RSCAN0.GAFLM6.UINT32
+#define RSCAN0GAFLM6L RSCAN0.GAFLM6.UINT16[L]
+#define RSCAN0GAFLM6LL RSCAN0.GAFLM6.UINT8[LL]
+#define RSCAN0GAFLM6LH RSCAN0.GAFLM6.UINT8[LH]
+#define RSCAN0GAFLM6H RSCAN0.GAFLM6.UINT16[H]
+#define RSCAN0GAFLM6HL RSCAN0.GAFLM6.UINT8[HL]
+#define RSCAN0GAFLM6HH RSCAN0.GAFLM6.UINT8[HH]
+#define RSCAN0GAFLP06 RSCAN0.GAFLP06.UINT32
+#define RSCAN0GAFLP06L RSCAN0.GAFLP06.UINT16[L]
+#define RSCAN0GAFLP06LL RSCAN0.GAFLP06.UINT8[LL]
+#define RSCAN0GAFLP06LH RSCAN0.GAFLP06.UINT8[LH]
+#define RSCAN0GAFLP06H RSCAN0.GAFLP06.UINT16[H]
+#define RSCAN0GAFLP06HL RSCAN0.GAFLP06.UINT8[HL]
+#define RSCAN0GAFLP06HH RSCAN0.GAFLP06.UINT8[HH]
+#define RSCAN0GAFLP16 RSCAN0.GAFLP16.UINT32
+#define RSCAN0GAFLP16L RSCAN0.GAFLP16.UINT16[L]
+#define RSCAN0GAFLP16LL RSCAN0.GAFLP16.UINT8[LL]
+#define RSCAN0GAFLP16LH RSCAN0.GAFLP16.UINT8[LH]
+#define RSCAN0GAFLP16H RSCAN0.GAFLP16.UINT16[H]
+#define RSCAN0GAFLP16HL RSCAN0.GAFLP16.UINT8[HL]
+#define RSCAN0GAFLP16HH RSCAN0.GAFLP16.UINT8[HH]
+#define RSCAN0GAFLID7 RSCAN0.GAFLID7.UINT32
+#define RSCAN0GAFLID7L RSCAN0.GAFLID7.UINT16[L]
+#define RSCAN0GAFLID7LL RSCAN0.GAFLID7.UINT8[LL]
+#define RSCAN0GAFLID7LH RSCAN0.GAFLID7.UINT8[LH]
+#define RSCAN0GAFLID7H RSCAN0.GAFLID7.UINT16[H]
+#define RSCAN0GAFLID7HL RSCAN0.GAFLID7.UINT8[HL]
+#define RSCAN0GAFLID7HH RSCAN0.GAFLID7.UINT8[HH]
+#define RSCAN0GAFLM7 RSCAN0.GAFLM7.UINT32
+#define RSCAN0GAFLM7L RSCAN0.GAFLM7.UINT16[L]
+#define RSCAN0GAFLM7LL RSCAN0.GAFLM7.UINT8[LL]
+#define RSCAN0GAFLM7LH RSCAN0.GAFLM7.UINT8[LH]
+#define RSCAN0GAFLM7H RSCAN0.GAFLM7.UINT16[H]
+#define RSCAN0GAFLM7HL RSCAN0.GAFLM7.UINT8[HL]
+#define RSCAN0GAFLM7HH RSCAN0.GAFLM7.UINT8[HH]
+#define RSCAN0GAFLP07 RSCAN0.GAFLP07.UINT32
+#define RSCAN0GAFLP07L RSCAN0.GAFLP07.UINT16[L]
+#define RSCAN0GAFLP07LL RSCAN0.GAFLP07.UINT8[LL]
+#define RSCAN0GAFLP07LH RSCAN0.GAFLP07.UINT8[LH]
+#define RSCAN0GAFLP07H RSCAN0.GAFLP07.UINT16[H]
+#define RSCAN0GAFLP07HL RSCAN0.GAFLP07.UINT8[HL]
+#define RSCAN0GAFLP07HH RSCAN0.GAFLP07.UINT8[HH]
+#define RSCAN0GAFLP17 RSCAN0.GAFLP17.UINT32
+#define RSCAN0GAFLP17L RSCAN0.GAFLP17.UINT16[L]
+#define RSCAN0GAFLP17LL RSCAN0.GAFLP17.UINT8[LL]
+#define RSCAN0GAFLP17LH RSCAN0.GAFLP17.UINT8[LH]
+#define RSCAN0GAFLP17H RSCAN0.GAFLP17.UINT16[H]
+#define RSCAN0GAFLP17HL RSCAN0.GAFLP17.UINT8[HL]
+#define RSCAN0GAFLP17HH RSCAN0.GAFLP17.UINT8[HH]
+#define RSCAN0GAFLID8 RSCAN0.GAFLID8.UINT32
+#define RSCAN0GAFLID8L RSCAN0.GAFLID8.UINT16[L]
+#define RSCAN0GAFLID8LL RSCAN0.GAFLID8.UINT8[LL]
+#define RSCAN0GAFLID8LH RSCAN0.GAFLID8.UINT8[LH]
+#define RSCAN0GAFLID8H RSCAN0.GAFLID8.UINT16[H]
+#define RSCAN0GAFLID8HL RSCAN0.GAFLID8.UINT8[HL]
+#define RSCAN0GAFLID8HH RSCAN0.GAFLID8.UINT8[HH]
+#define RSCAN0GAFLM8 RSCAN0.GAFLM8.UINT32
+#define RSCAN0GAFLM8L RSCAN0.GAFLM8.UINT16[L]
+#define RSCAN0GAFLM8LL RSCAN0.GAFLM8.UINT8[LL]
+#define RSCAN0GAFLM8LH RSCAN0.GAFLM8.UINT8[LH]
+#define RSCAN0GAFLM8H RSCAN0.GAFLM8.UINT16[H]
+#define RSCAN0GAFLM8HL RSCAN0.GAFLM8.UINT8[HL]
+#define RSCAN0GAFLM8HH RSCAN0.GAFLM8.UINT8[HH]
+#define RSCAN0GAFLP08 RSCAN0.GAFLP08.UINT32
+#define RSCAN0GAFLP08L RSCAN0.GAFLP08.UINT16[L]
+#define RSCAN0GAFLP08LL RSCAN0.GAFLP08.UINT8[LL]
+#define RSCAN0GAFLP08LH RSCAN0.GAFLP08.UINT8[LH]
+#define RSCAN0GAFLP08H RSCAN0.GAFLP08.UINT16[H]
+#define RSCAN0GAFLP08HL RSCAN0.GAFLP08.UINT8[HL]
+#define RSCAN0GAFLP08HH RSCAN0.GAFLP08.UINT8[HH]
+#define RSCAN0GAFLP18 RSCAN0.GAFLP18.UINT32
+#define RSCAN0GAFLP18L RSCAN0.GAFLP18.UINT16[L]
+#define RSCAN0GAFLP18LL RSCAN0.GAFLP18.UINT8[LL]
+#define RSCAN0GAFLP18LH RSCAN0.GAFLP18.UINT8[LH]
+#define RSCAN0GAFLP18H RSCAN0.GAFLP18.UINT16[H]
+#define RSCAN0GAFLP18HL RSCAN0.GAFLP18.UINT8[HL]
+#define RSCAN0GAFLP18HH RSCAN0.GAFLP18.UINT8[HH]
+#define RSCAN0GAFLID9 RSCAN0.GAFLID9.UINT32
+#define RSCAN0GAFLID9L RSCAN0.GAFLID9.UINT16[L]
+#define RSCAN0GAFLID9LL RSCAN0.GAFLID9.UINT8[LL]
+#define RSCAN0GAFLID9LH RSCAN0.GAFLID9.UINT8[LH]
+#define RSCAN0GAFLID9H RSCAN0.GAFLID9.UINT16[H]
+#define RSCAN0GAFLID9HL RSCAN0.GAFLID9.UINT8[HL]
+#define RSCAN0GAFLID9HH RSCAN0.GAFLID9.UINT8[HH]
+#define RSCAN0GAFLM9 RSCAN0.GAFLM9.UINT32
+#define RSCAN0GAFLM9L RSCAN0.GAFLM9.UINT16[L]
+#define RSCAN0GAFLM9LL RSCAN0.GAFLM9.UINT8[LL]
+#define RSCAN0GAFLM9LH RSCAN0.GAFLM9.UINT8[LH]
+#define RSCAN0GAFLM9H RSCAN0.GAFLM9.UINT16[H]
+#define RSCAN0GAFLM9HL RSCAN0.GAFLM9.UINT8[HL]
+#define RSCAN0GAFLM9HH RSCAN0.GAFLM9.UINT8[HH]
+#define RSCAN0GAFLP09 RSCAN0.GAFLP09.UINT32
+#define RSCAN0GAFLP09L RSCAN0.GAFLP09.UINT16[L]
+#define RSCAN0GAFLP09LL RSCAN0.GAFLP09.UINT8[LL]
+#define RSCAN0GAFLP09LH RSCAN0.GAFLP09.UINT8[LH]
+#define RSCAN0GAFLP09H RSCAN0.GAFLP09.UINT16[H]
+#define RSCAN0GAFLP09HL RSCAN0.GAFLP09.UINT8[HL]
+#define RSCAN0GAFLP09HH RSCAN0.GAFLP09.UINT8[HH]
+#define RSCAN0GAFLP19 RSCAN0.GAFLP19.UINT32
+#define RSCAN0GAFLP19L RSCAN0.GAFLP19.UINT16[L]
+#define RSCAN0GAFLP19LL RSCAN0.GAFLP19.UINT8[LL]
+#define RSCAN0GAFLP19LH RSCAN0.GAFLP19.UINT8[LH]
+#define RSCAN0GAFLP19H RSCAN0.GAFLP19.UINT16[H]
+#define RSCAN0GAFLP19HL RSCAN0.GAFLP19.UINT8[HL]
+#define RSCAN0GAFLP19HH RSCAN0.GAFLP19.UINT8[HH]
+#define RSCAN0GAFLID10 RSCAN0.GAFLID10.UINT32
+#define RSCAN0GAFLID10L RSCAN0.GAFLID10.UINT16[L]
+#define RSCAN0GAFLID10LL RSCAN0.GAFLID10.UINT8[LL]
+#define RSCAN0GAFLID10LH RSCAN0.GAFLID10.UINT8[LH]
+#define RSCAN0GAFLID10H RSCAN0.GAFLID10.UINT16[H]
+#define RSCAN0GAFLID10HL RSCAN0.GAFLID10.UINT8[HL]
+#define RSCAN0GAFLID10HH RSCAN0.GAFLID10.UINT8[HH]
+#define RSCAN0GAFLM10 RSCAN0.GAFLM10.UINT32
+#define RSCAN0GAFLM10L RSCAN0.GAFLM10.UINT16[L]
+#define RSCAN0GAFLM10LL RSCAN0.GAFLM10.UINT8[LL]
+#define RSCAN0GAFLM10LH RSCAN0.GAFLM10.UINT8[LH]
+#define RSCAN0GAFLM10H RSCAN0.GAFLM10.UINT16[H]
+#define RSCAN0GAFLM10HL RSCAN0.GAFLM10.UINT8[HL]
+#define RSCAN0GAFLM10HH RSCAN0.GAFLM10.UINT8[HH]
+#define RSCAN0GAFLP010 RSCAN0.GAFLP010.UINT32
+#define RSCAN0GAFLP010L RSCAN0.GAFLP010.UINT16[L]
+#define RSCAN0GAFLP010LL RSCAN0.GAFLP010.UINT8[LL]
+#define RSCAN0GAFLP010LH RSCAN0.GAFLP010.UINT8[LH]
+#define RSCAN0GAFLP010H RSCAN0.GAFLP010.UINT16[H]
+#define RSCAN0GAFLP010HL RSCAN0.GAFLP010.UINT8[HL]
+#define RSCAN0GAFLP010HH RSCAN0.GAFLP010.UINT8[HH]
+#define RSCAN0GAFLP110 RSCAN0.GAFLP110.UINT32
+#define RSCAN0GAFLP110L RSCAN0.GAFLP110.UINT16[L]
+#define RSCAN0GAFLP110LL RSCAN0.GAFLP110.UINT8[LL]
+#define RSCAN0GAFLP110LH RSCAN0.GAFLP110.UINT8[LH]
+#define RSCAN0GAFLP110H RSCAN0.GAFLP110.UINT16[H]
+#define RSCAN0GAFLP110HL RSCAN0.GAFLP110.UINT8[HL]
+#define RSCAN0GAFLP110HH RSCAN0.GAFLP110.UINT8[HH]
+#define RSCAN0GAFLID11 RSCAN0.GAFLID11.UINT32
+#define RSCAN0GAFLID11L RSCAN0.GAFLID11.UINT16[L]
+#define RSCAN0GAFLID11LL RSCAN0.GAFLID11.UINT8[LL]
+#define RSCAN0GAFLID11LH RSCAN0.GAFLID11.UINT8[LH]
+#define RSCAN0GAFLID11H RSCAN0.GAFLID11.UINT16[H]
+#define RSCAN0GAFLID11HL RSCAN0.GAFLID11.UINT8[HL]
+#define RSCAN0GAFLID11HH RSCAN0.GAFLID11.UINT8[HH]
+#define RSCAN0GAFLM11 RSCAN0.GAFLM11.UINT32
+#define RSCAN0GAFLM11L RSCAN0.GAFLM11.UINT16[L]
+#define RSCAN0GAFLM11LL RSCAN0.GAFLM11.UINT8[LL]
+#define RSCAN0GAFLM11LH RSCAN0.GAFLM11.UINT8[LH]
+#define RSCAN0GAFLM11H RSCAN0.GAFLM11.UINT16[H]
+#define RSCAN0GAFLM11HL RSCAN0.GAFLM11.UINT8[HL]
+#define RSCAN0GAFLM11HH RSCAN0.GAFLM11.UINT8[HH]
+#define RSCAN0GAFLP011 RSCAN0.GAFLP011.UINT32
+#define RSCAN0GAFLP011L RSCAN0.GAFLP011.UINT16[L]
+#define RSCAN0GAFLP011LL RSCAN0.GAFLP011.UINT8[LL]
+#define RSCAN0GAFLP011LH RSCAN0.GAFLP011.UINT8[LH]
+#define RSCAN0GAFLP011H RSCAN0.GAFLP011.UINT16[H]
+#define RSCAN0GAFLP011HL RSCAN0.GAFLP011.UINT8[HL]
+#define RSCAN0GAFLP011HH RSCAN0.GAFLP011.UINT8[HH]
+#define RSCAN0GAFLP111 RSCAN0.GAFLP111.UINT32
+#define RSCAN0GAFLP111L RSCAN0.GAFLP111.UINT16[L]
+#define RSCAN0GAFLP111LL RSCAN0.GAFLP111.UINT8[LL]
+#define RSCAN0GAFLP111LH RSCAN0.GAFLP111.UINT8[LH]
+#define RSCAN0GAFLP111H RSCAN0.GAFLP111.UINT16[H]
+#define RSCAN0GAFLP111HL RSCAN0.GAFLP111.UINT8[HL]
+#define RSCAN0GAFLP111HH RSCAN0.GAFLP111.UINT8[HH]
+#define RSCAN0GAFLID12 RSCAN0.GAFLID12.UINT32
+#define RSCAN0GAFLID12L RSCAN0.GAFLID12.UINT16[L]
+#define RSCAN0GAFLID12LL RSCAN0.GAFLID12.UINT8[LL]
+#define RSCAN0GAFLID12LH RSCAN0.GAFLID12.UINT8[LH]
+#define RSCAN0GAFLID12H RSCAN0.GAFLID12.UINT16[H]
+#define RSCAN0GAFLID12HL RSCAN0.GAFLID12.UINT8[HL]
+#define RSCAN0GAFLID12HH RSCAN0.GAFLID12.UINT8[HH]
+#define RSCAN0GAFLM12 RSCAN0.GAFLM12.UINT32
+#define RSCAN0GAFLM12L RSCAN0.GAFLM12.UINT16[L]
+#define RSCAN0GAFLM12LL RSCAN0.GAFLM12.UINT8[LL]
+#define RSCAN0GAFLM12LH RSCAN0.GAFLM12.UINT8[LH]
+#define RSCAN0GAFLM12H RSCAN0.GAFLM12.UINT16[H]
+#define RSCAN0GAFLM12HL RSCAN0.GAFLM12.UINT8[HL]
+#define RSCAN0GAFLM12HH RSCAN0.GAFLM12.UINT8[HH]
+#define RSCAN0GAFLP012 RSCAN0.GAFLP012.UINT32
+#define RSCAN0GAFLP012L RSCAN0.GAFLP012.UINT16[L]
+#define RSCAN0GAFLP012LL RSCAN0.GAFLP012.UINT8[LL]
+#define RSCAN0GAFLP012LH RSCAN0.GAFLP012.UINT8[LH]
+#define RSCAN0GAFLP012H RSCAN0.GAFLP012.UINT16[H]
+#define RSCAN0GAFLP012HL RSCAN0.GAFLP012.UINT8[HL]
+#define RSCAN0GAFLP012HH RSCAN0.GAFLP012.UINT8[HH]
+#define RSCAN0GAFLP112 RSCAN0.GAFLP112.UINT32
+#define RSCAN0GAFLP112L RSCAN0.GAFLP112.UINT16[L]
+#define RSCAN0GAFLP112LL RSCAN0.GAFLP112.UINT8[LL]
+#define RSCAN0GAFLP112LH RSCAN0.GAFLP112.UINT8[LH]
+#define RSCAN0GAFLP112H RSCAN0.GAFLP112.UINT16[H]
+#define RSCAN0GAFLP112HL RSCAN0.GAFLP112.UINT8[HL]
+#define RSCAN0GAFLP112HH RSCAN0.GAFLP112.UINT8[HH]
+#define RSCAN0GAFLID13 RSCAN0.GAFLID13.UINT32
+#define RSCAN0GAFLID13L RSCAN0.GAFLID13.UINT16[L]
+#define RSCAN0GAFLID13LL RSCAN0.GAFLID13.UINT8[LL]
+#define RSCAN0GAFLID13LH RSCAN0.GAFLID13.UINT8[LH]
+#define RSCAN0GAFLID13H RSCAN0.GAFLID13.UINT16[H]
+#define RSCAN0GAFLID13HL RSCAN0.GAFLID13.UINT8[HL]
+#define RSCAN0GAFLID13HH RSCAN0.GAFLID13.UINT8[HH]
+#define RSCAN0GAFLM13 RSCAN0.GAFLM13.UINT32
+#define RSCAN0GAFLM13L RSCAN0.GAFLM13.UINT16[L]
+#define RSCAN0GAFLM13LL RSCAN0.GAFLM13.UINT8[LL]
+#define RSCAN0GAFLM13LH RSCAN0.GAFLM13.UINT8[LH]
+#define RSCAN0GAFLM13H RSCAN0.GAFLM13.UINT16[H]
+#define RSCAN0GAFLM13HL RSCAN0.GAFLM13.UINT8[HL]
+#define RSCAN0GAFLM13HH RSCAN0.GAFLM13.UINT8[HH]
+#define RSCAN0GAFLP013 RSCAN0.GAFLP013.UINT32
+#define RSCAN0GAFLP013L RSCAN0.GAFLP013.UINT16[L]
+#define RSCAN0GAFLP013LL RSCAN0.GAFLP013.UINT8[LL]
+#define RSCAN0GAFLP013LH RSCAN0.GAFLP013.UINT8[LH]
+#define RSCAN0GAFLP013H RSCAN0.GAFLP013.UINT16[H]
+#define RSCAN0GAFLP013HL RSCAN0.GAFLP013.UINT8[HL]
+#define RSCAN0GAFLP013HH RSCAN0.GAFLP013.UINT8[HH]
+#define RSCAN0GAFLP113 RSCAN0.GAFLP113.UINT32
+#define RSCAN0GAFLP113L RSCAN0.GAFLP113.UINT16[L]
+#define RSCAN0GAFLP113LL RSCAN0.GAFLP113.UINT8[LL]
+#define RSCAN0GAFLP113LH RSCAN0.GAFLP113.UINT8[LH]
+#define RSCAN0GAFLP113H RSCAN0.GAFLP113.UINT16[H]
+#define RSCAN0GAFLP113HL RSCAN0.GAFLP113.UINT8[HL]
+#define RSCAN0GAFLP113HH RSCAN0.GAFLP113.UINT8[HH]
+#define RSCAN0GAFLID14 RSCAN0.GAFLID14.UINT32
+#define RSCAN0GAFLID14L RSCAN0.GAFLID14.UINT16[L]
+#define RSCAN0GAFLID14LL RSCAN0.GAFLID14.UINT8[LL]
+#define RSCAN0GAFLID14LH RSCAN0.GAFLID14.UINT8[LH]
+#define RSCAN0GAFLID14H RSCAN0.GAFLID14.UINT16[H]
+#define RSCAN0GAFLID14HL RSCAN0.GAFLID14.UINT8[HL]
+#define RSCAN0GAFLID14HH RSCAN0.GAFLID14.UINT8[HH]
+#define RSCAN0GAFLM14 RSCAN0.GAFLM14.UINT32
+#define RSCAN0GAFLM14L RSCAN0.GAFLM14.UINT16[L]
+#define RSCAN0GAFLM14LL RSCAN0.GAFLM14.UINT8[LL]
+#define RSCAN0GAFLM14LH RSCAN0.GAFLM14.UINT8[LH]
+#define RSCAN0GAFLM14H RSCAN0.GAFLM14.UINT16[H]
+#define RSCAN0GAFLM14HL RSCAN0.GAFLM14.UINT8[HL]
+#define RSCAN0GAFLM14HH RSCAN0.GAFLM14.UINT8[HH]
+#define RSCAN0GAFLP014 RSCAN0.GAFLP014.UINT32
+#define RSCAN0GAFLP014L RSCAN0.GAFLP014.UINT16[L]
+#define RSCAN0GAFLP014LL RSCAN0.GAFLP014.UINT8[LL]
+#define RSCAN0GAFLP014LH RSCAN0.GAFLP014.UINT8[LH]
+#define RSCAN0GAFLP014H RSCAN0.GAFLP014.UINT16[H]
+#define RSCAN0GAFLP014HL RSCAN0.GAFLP014.UINT8[HL]
+#define RSCAN0GAFLP014HH RSCAN0.GAFLP014.UINT8[HH]
+#define RSCAN0GAFLP114 RSCAN0.GAFLP114.UINT32
+#define RSCAN0GAFLP114L RSCAN0.GAFLP114.UINT16[L]
+#define RSCAN0GAFLP114LL RSCAN0.GAFLP114.UINT8[LL]
+#define RSCAN0GAFLP114LH RSCAN0.GAFLP114.UINT8[LH]
+#define RSCAN0GAFLP114H RSCAN0.GAFLP114.UINT16[H]
+#define RSCAN0GAFLP114HL RSCAN0.GAFLP114.UINT8[HL]
+#define RSCAN0GAFLP114HH RSCAN0.GAFLP114.UINT8[HH]
+#define RSCAN0GAFLID15 RSCAN0.GAFLID15.UINT32
+#define RSCAN0GAFLID15L RSCAN0.GAFLID15.UINT16[L]
+#define RSCAN0GAFLID15LL RSCAN0.GAFLID15.UINT8[LL]
+#define RSCAN0GAFLID15LH RSCAN0.GAFLID15.UINT8[LH]
+#define RSCAN0GAFLID15H RSCAN0.GAFLID15.UINT16[H]
+#define RSCAN0GAFLID15HL RSCAN0.GAFLID15.UINT8[HL]
+#define RSCAN0GAFLID15HH RSCAN0.GAFLID15.UINT8[HH]
+#define RSCAN0GAFLM15 RSCAN0.GAFLM15.UINT32
+#define RSCAN0GAFLM15L RSCAN0.GAFLM15.UINT16[L]
+#define RSCAN0GAFLM15LL RSCAN0.GAFLM15.UINT8[LL]
+#define RSCAN0GAFLM15LH RSCAN0.GAFLM15.UINT8[LH]
+#define RSCAN0GAFLM15H RSCAN0.GAFLM15.UINT16[H]
+#define RSCAN0GAFLM15HL RSCAN0.GAFLM15.UINT8[HL]
+#define RSCAN0GAFLM15HH RSCAN0.GAFLM15.UINT8[HH]
+#define RSCAN0GAFLP015 RSCAN0.GAFLP015.UINT32
+#define RSCAN0GAFLP015L RSCAN0.GAFLP015.UINT16[L]
+#define RSCAN0GAFLP015LL RSCAN0.GAFLP015.UINT8[LL]
+#define RSCAN0GAFLP015LH RSCAN0.GAFLP015.UINT8[LH]
+#define RSCAN0GAFLP015H RSCAN0.GAFLP015.UINT16[H]
+#define RSCAN0GAFLP015HL RSCAN0.GAFLP015.UINT8[HL]
+#define RSCAN0GAFLP015HH RSCAN0.GAFLP015.UINT8[HH]
+#define RSCAN0GAFLP115 RSCAN0.GAFLP115.UINT32
+#define RSCAN0GAFLP115L RSCAN0.GAFLP115.UINT16[L]
+#define RSCAN0GAFLP115LL RSCAN0.GAFLP115.UINT8[LL]
+#define RSCAN0GAFLP115LH RSCAN0.GAFLP115.UINT8[LH]
+#define RSCAN0GAFLP115H RSCAN0.GAFLP115.UINT16[H]
+#define RSCAN0GAFLP115HL RSCAN0.GAFLP115.UINT8[HL]
+#define RSCAN0GAFLP115HH RSCAN0.GAFLP115.UINT8[HH]
+#define RSCAN0RMID0 RSCAN0.RMID0.UINT32
+#define RSCAN0RMID0L RSCAN0.RMID0.UINT16[L]
+#define RSCAN0RMID0LL RSCAN0.RMID0.UINT8[LL]
+#define RSCAN0RMID0LH RSCAN0.RMID0.UINT8[LH]
+#define RSCAN0RMID0H RSCAN0.RMID0.UINT16[H]
+#define RSCAN0RMID0HL RSCAN0.RMID0.UINT8[HL]
+#define RSCAN0RMID0HH RSCAN0.RMID0.UINT8[HH]
+#define RSCAN0RMPTR0 RSCAN0.RMPTR0.UINT32
+#define RSCAN0RMPTR0L RSCAN0.RMPTR0.UINT16[L]
+#define RSCAN0RMPTR0LL RSCAN0.RMPTR0.UINT8[LL]
+#define RSCAN0RMPTR0LH RSCAN0.RMPTR0.UINT8[LH]
+#define RSCAN0RMPTR0H RSCAN0.RMPTR0.UINT16[H]
+#define RSCAN0RMPTR0HL RSCAN0.RMPTR0.UINT8[HL]
+#define RSCAN0RMPTR0HH RSCAN0.RMPTR0.UINT8[HH]
+#define RSCAN0RMDF00 RSCAN0.RMDF00.UINT32
+#define RSCAN0RMDF00L RSCAN0.RMDF00.UINT16[L]
+#define RSCAN0RMDF00LL RSCAN0.RMDF00.UINT8[LL]
+#define RSCAN0RMDF00LH RSCAN0.RMDF00.UINT8[LH]
+#define RSCAN0RMDF00H RSCAN0.RMDF00.UINT16[H]
+#define RSCAN0RMDF00HL RSCAN0.RMDF00.UINT8[HL]
+#define RSCAN0RMDF00HH RSCAN0.RMDF00.UINT8[HH]
+#define RSCAN0RMDF10 RSCAN0.RMDF10.UINT32
+#define RSCAN0RMDF10L RSCAN0.RMDF10.UINT16[L]
+#define RSCAN0RMDF10LL RSCAN0.RMDF10.UINT8[LL]
+#define RSCAN0RMDF10LH RSCAN0.RMDF10.UINT8[LH]
+#define RSCAN0RMDF10H RSCAN0.RMDF10.UINT16[H]
+#define RSCAN0RMDF10HL RSCAN0.RMDF10.UINT8[HL]
+#define RSCAN0RMDF10HH RSCAN0.RMDF10.UINT8[HH]
+#define RSCAN0RMID1 RSCAN0.RMID1.UINT32
+#define RSCAN0RMID1L RSCAN0.RMID1.UINT16[L]
+#define RSCAN0RMID1LL RSCAN0.RMID1.UINT8[LL]
+#define RSCAN0RMID1LH RSCAN0.RMID1.UINT8[LH]
+#define RSCAN0RMID1H RSCAN0.RMID1.UINT16[H]
+#define RSCAN0RMID1HL RSCAN0.RMID1.UINT8[HL]
+#define RSCAN0RMID1HH RSCAN0.RMID1.UINT8[HH]
+#define RSCAN0RMPTR1 RSCAN0.RMPTR1.UINT32
+#define RSCAN0RMPTR1L RSCAN0.RMPTR1.UINT16[L]
+#define RSCAN0RMPTR1LL RSCAN0.RMPTR1.UINT8[LL]
+#define RSCAN0RMPTR1LH RSCAN0.RMPTR1.UINT8[LH]
+#define RSCAN0RMPTR1H RSCAN0.RMPTR1.UINT16[H]
+#define RSCAN0RMPTR1HL RSCAN0.RMPTR1.UINT8[HL]
+#define RSCAN0RMPTR1HH RSCAN0.RMPTR1.UINT8[HH]
+#define RSCAN0RMDF01 RSCAN0.RMDF01.UINT32
+#define RSCAN0RMDF01L RSCAN0.RMDF01.UINT16[L]
+#define RSCAN0RMDF01LL RSCAN0.RMDF01.UINT8[LL]
+#define RSCAN0RMDF01LH RSCAN0.RMDF01.UINT8[LH]
+#define RSCAN0RMDF01H RSCAN0.RMDF01.UINT16[H]
+#define RSCAN0RMDF01HL RSCAN0.RMDF01.UINT8[HL]
+#define RSCAN0RMDF01HH RSCAN0.RMDF01.UINT8[HH]
+#define RSCAN0RMDF11 RSCAN0.RMDF11.UINT32
+#define RSCAN0RMDF11L RSCAN0.RMDF11.UINT16[L]
+#define RSCAN0RMDF11LL RSCAN0.RMDF11.UINT8[LL]
+#define RSCAN0RMDF11LH RSCAN0.RMDF11.UINT8[LH]
+#define RSCAN0RMDF11H RSCAN0.RMDF11.UINT16[H]
+#define RSCAN0RMDF11HL RSCAN0.RMDF11.UINT8[HL]
+#define RSCAN0RMDF11HH RSCAN0.RMDF11.UINT8[HH]
+#define RSCAN0RMID2 RSCAN0.RMID2.UINT32
+#define RSCAN0RMID2L RSCAN0.RMID2.UINT16[L]
+#define RSCAN0RMID2LL RSCAN0.RMID2.UINT8[LL]
+#define RSCAN0RMID2LH RSCAN0.RMID2.UINT8[LH]
+#define RSCAN0RMID2H RSCAN0.RMID2.UINT16[H]
+#define RSCAN0RMID2HL RSCAN0.RMID2.UINT8[HL]
+#define RSCAN0RMID2HH RSCAN0.RMID2.UINT8[HH]
+#define RSCAN0RMPTR2 RSCAN0.RMPTR2.UINT32
+#define RSCAN0RMPTR2L RSCAN0.RMPTR2.UINT16[L]
+#define RSCAN0RMPTR2LL RSCAN0.RMPTR2.UINT8[LL]
+#define RSCAN0RMPTR2LH RSCAN0.RMPTR2.UINT8[LH]
+#define RSCAN0RMPTR2H RSCAN0.RMPTR2.UINT16[H]
+#define RSCAN0RMPTR2HL RSCAN0.RMPTR2.UINT8[HL]
+#define RSCAN0RMPTR2HH RSCAN0.RMPTR2.UINT8[HH]
+#define RSCAN0RMDF02 RSCAN0.RMDF02.UINT32
+#define RSCAN0RMDF02L RSCAN0.RMDF02.UINT16[L]
+#define RSCAN0RMDF02LL RSCAN0.RMDF02.UINT8[LL]
+#define RSCAN0RMDF02LH RSCAN0.RMDF02.UINT8[LH]
+#define RSCAN0RMDF02H RSCAN0.RMDF02.UINT16[H]
+#define RSCAN0RMDF02HL RSCAN0.RMDF02.UINT8[HL]
+#define RSCAN0RMDF02HH RSCAN0.RMDF02.UINT8[HH]
+#define RSCAN0RMDF12 RSCAN0.RMDF12.UINT32
+#define RSCAN0RMDF12L RSCAN0.RMDF12.UINT16[L]
+#define RSCAN0RMDF12LL RSCAN0.RMDF12.UINT8[LL]
+#define RSCAN0RMDF12LH RSCAN0.RMDF12.UINT8[LH]
+#define RSCAN0RMDF12H RSCAN0.RMDF12.UINT16[H]
+#define RSCAN0RMDF12HL RSCAN0.RMDF12.UINT8[HL]
+#define RSCAN0RMDF12HH RSCAN0.RMDF12.UINT8[HH]
+#define RSCAN0RMID3 RSCAN0.RMID3.UINT32
+#define RSCAN0RMID3L RSCAN0.RMID3.UINT16[L]
+#define RSCAN0RMID3LL RSCAN0.RMID3.UINT8[LL]
+#define RSCAN0RMID3LH RSCAN0.RMID3.UINT8[LH]
+#define RSCAN0RMID3H RSCAN0.RMID3.UINT16[H]
+#define RSCAN0RMID3HL RSCAN0.RMID3.UINT8[HL]
+#define RSCAN0RMID3HH RSCAN0.RMID3.UINT8[HH]
+#define RSCAN0RMPTR3 RSCAN0.RMPTR3.UINT32
+#define RSCAN0RMPTR3L RSCAN0.RMPTR3.UINT16[L]
+#define RSCAN0RMPTR3LL RSCAN0.RMPTR3.UINT8[LL]
+#define RSCAN0RMPTR3LH RSCAN0.RMPTR3.UINT8[LH]
+#define RSCAN0RMPTR3H RSCAN0.RMPTR3.UINT16[H]
+#define RSCAN0RMPTR3HL RSCAN0.RMPTR3.UINT8[HL]
+#define RSCAN0RMPTR3HH RSCAN0.RMPTR3.UINT8[HH]
+#define RSCAN0RMDF03 RSCAN0.RMDF03.UINT32
+#define RSCAN0RMDF03L RSCAN0.RMDF03.UINT16[L]
+#define RSCAN0RMDF03LL RSCAN0.RMDF03.UINT8[LL]
+#define RSCAN0RMDF03LH RSCAN0.RMDF03.UINT8[LH]
+#define RSCAN0RMDF03H RSCAN0.RMDF03.UINT16[H]
+#define RSCAN0RMDF03HL RSCAN0.RMDF03.UINT8[HL]
+#define RSCAN0RMDF03HH RSCAN0.RMDF03.UINT8[HH]
+#define RSCAN0RMDF13 RSCAN0.RMDF13.UINT32
+#define RSCAN0RMDF13L RSCAN0.RMDF13.UINT16[L]
+#define RSCAN0RMDF13LL RSCAN0.RMDF13.UINT8[LL]
+#define RSCAN0RMDF13LH RSCAN0.RMDF13.UINT8[LH]
+#define RSCAN0RMDF13H RSCAN0.RMDF13.UINT16[H]
+#define RSCAN0RMDF13HL RSCAN0.RMDF13.UINT8[HL]
+#define RSCAN0RMDF13HH RSCAN0.RMDF13.UINT8[HH]
+#define RSCAN0RMID4 RSCAN0.RMID4.UINT32
+#define RSCAN0RMID4L RSCAN0.RMID4.UINT16[L]
+#define RSCAN0RMID4LL RSCAN0.RMID4.UINT8[LL]
+#define RSCAN0RMID4LH RSCAN0.RMID4.UINT8[LH]
+#define RSCAN0RMID4H RSCAN0.RMID4.UINT16[H]
+#define RSCAN0RMID4HL RSCAN0.RMID4.UINT8[HL]
+#define RSCAN0RMID4HH RSCAN0.RMID4.UINT8[HH]
+#define RSCAN0RMPTR4 RSCAN0.RMPTR4.UINT32
+#define RSCAN0RMPTR4L RSCAN0.RMPTR4.UINT16[L]
+#define RSCAN0RMPTR4LL RSCAN0.RMPTR4.UINT8[LL]
+#define RSCAN0RMPTR4LH RSCAN0.RMPTR4.UINT8[LH]
+#define RSCAN0RMPTR4H RSCAN0.RMPTR4.UINT16[H]
+#define RSCAN0RMPTR4HL RSCAN0.RMPTR4.UINT8[HL]
+#define RSCAN0RMPTR4HH RSCAN0.RMPTR4.UINT8[HH]
+#define RSCAN0RMDF04 RSCAN0.RMDF04.UINT32
+#define RSCAN0RMDF04L RSCAN0.RMDF04.UINT16[L]
+#define RSCAN0RMDF04LL RSCAN0.RMDF04.UINT8[LL]
+#define RSCAN0RMDF04LH RSCAN0.RMDF04.UINT8[LH]
+#define RSCAN0RMDF04H RSCAN0.RMDF04.UINT16[H]
+#define RSCAN0RMDF04HL RSCAN0.RMDF04.UINT8[HL]
+#define RSCAN0RMDF04HH RSCAN0.RMDF04.UINT8[HH]
+#define RSCAN0RMDF14 RSCAN0.RMDF14.UINT32
+#define RSCAN0RMDF14L RSCAN0.RMDF14.UINT16[L]
+#define RSCAN0RMDF14LL RSCAN0.RMDF14.UINT8[LL]
+#define RSCAN0RMDF14LH RSCAN0.RMDF14.UINT8[LH]
+#define RSCAN0RMDF14H RSCAN0.RMDF14.UINT16[H]
+#define RSCAN0RMDF14HL RSCAN0.RMDF14.UINT8[HL]
+#define RSCAN0RMDF14HH RSCAN0.RMDF14.UINT8[HH]
+#define RSCAN0RMID5 RSCAN0.RMID5.UINT32
+#define RSCAN0RMID5L RSCAN0.RMID5.UINT16[L]
+#define RSCAN0RMID5LL RSCAN0.RMID5.UINT8[LL]
+#define RSCAN0RMID5LH RSCAN0.RMID5.UINT8[LH]
+#define RSCAN0RMID5H RSCAN0.RMID5.UINT16[H]
+#define RSCAN0RMID5HL RSCAN0.RMID5.UINT8[HL]
+#define RSCAN0RMID5HH RSCAN0.RMID5.UINT8[HH]
+#define RSCAN0RMPTR5 RSCAN0.RMPTR5.UINT32
+#define RSCAN0RMPTR5L RSCAN0.RMPTR5.UINT16[L]
+#define RSCAN0RMPTR5LL RSCAN0.RMPTR5.UINT8[LL]
+#define RSCAN0RMPTR5LH RSCAN0.RMPTR5.UINT8[LH]
+#define RSCAN0RMPTR5H RSCAN0.RMPTR5.UINT16[H]
+#define RSCAN0RMPTR5HL RSCAN0.RMPTR5.UINT8[HL]
+#define RSCAN0RMPTR5HH RSCAN0.RMPTR5.UINT8[HH]
+#define RSCAN0RMDF05 RSCAN0.RMDF05.UINT32
+#define RSCAN0RMDF05L RSCAN0.RMDF05.UINT16[L]
+#define RSCAN0RMDF05LL RSCAN0.RMDF05.UINT8[LL]
+#define RSCAN0RMDF05LH RSCAN0.RMDF05.UINT8[LH]
+#define RSCAN0RMDF05H RSCAN0.RMDF05.UINT16[H]
+#define RSCAN0RMDF05HL RSCAN0.RMDF05.UINT8[HL]
+#define RSCAN0RMDF05HH RSCAN0.RMDF05.UINT8[HH]
+#define RSCAN0RMDF15 RSCAN0.RMDF15.UINT32
+#define RSCAN0RMDF15L RSCAN0.RMDF15.UINT16[L]
+#define RSCAN0RMDF15LL RSCAN0.RMDF15.UINT8[LL]
+#define RSCAN0RMDF15LH RSCAN0.RMDF15.UINT8[LH]
+#define RSCAN0RMDF15H RSCAN0.RMDF15.UINT16[H]
+#define RSCAN0RMDF15HL RSCAN0.RMDF15.UINT8[HL]
+#define RSCAN0RMDF15HH RSCAN0.RMDF15.UINT8[HH]
+#define RSCAN0RMID6 RSCAN0.RMID6.UINT32
+#define RSCAN0RMID6L RSCAN0.RMID6.UINT16[L]
+#define RSCAN0RMID6LL RSCAN0.RMID6.UINT8[LL]
+#define RSCAN0RMID6LH RSCAN0.RMID6.UINT8[LH]
+#define RSCAN0RMID6H RSCAN0.RMID6.UINT16[H]
+#define RSCAN0RMID6HL RSCAN0.RMID6.UINT8[HL]
+#define RSCAN0RMID6HH RSCAN0.RMID6.UINT8[HH]
+#define RSCAN0RMPTR6 RSCAN0.RMPTR6.UINT32
+#define RSCAN0RMPTR6L RSCAN0.RMPTR6.UINT16[L]
+#define RSCAN0RMPTR6LL RSCAN0.RMPTR6.UINT8[LL]
+#define RSCAN0RMPTR6LH RSCAN0.RMPTR6.UINT8[LH]
+#define RSCAN0RMPTR6H RSCAN0.RMPTR6.UINT16[H]
+#define RSCAN0RMPTR6HL RSCAN0.RMPTR6.UINT8[HL]
+#define RSCAN0RMPTR6HH RSCAN0.RMPTR6.UINT8[HH]
+#define RSCAN0RMDF06 RSCAN0.RMDF06.UINT32
+#define RSCAN0RMDF06L RSCAN0.RMDF06.UINT16[L]
+#define RSCAN0RMDF06LL RSCAN0.RMDF06.UINT8[LL]
+#define RSCAN0RMDF06LH RSCAN0.RMDF06.UINT8[LH]
+#define RSCAN0RMDF06H RSCAN0.RMDF06.UINT16[H]
+#define RSCAN0RMDF06HL RSCAN0.RMDF06.UINT8[HL]
+#define RSCAN0RMDF06HH RSCAN0.RMDF06.UINT8[HH]
+#define RSCAN0RMDF16 RSCAN0.RMDF16.UINT32
+#define RSCAN0RMDF16L RSCAN0.RMDF16.UINT16[L]
+#define RSCAN0RMDF16LL RSCAN0.RMDF16.UINT8[LL]
+#define RSCAN0RMDF16LH RSCAN0.RMDF16.UINT8[LH]
+#define RSCAN0RMDF16H RSCAN0.RMDF16.UINT16[H]
+#define RSCAN0RMDF16HL RSCAN0.RMDF16.UINT8[HL]
+#define RSCAN0RMDF16HH RSCAN0.RMDF16.UINT8[HH]
+#define RSCAN0RMID7 RSCAN0.RMID7.UINT32
+#define RSCAN0RMID7L RSCAN0.RMID7.UINT16[L]
+#define RSCAN0RMID7LL RSCAN0.RMID7.UINT8[LL]
+#define RSCAN0RMID7LH RSCAN0.RMID7.UINT8[LH]
+#define RSCAN0RMID7H RSCAN0.RMID7.UINT16[H]
+#define RSCAN0RMID7HL RSCAN0.RMID7.UINT8[HL]
+#define RSCAN0RMID7HH RSCAN0.RMID7.UINT8[HH]
+#define RSCAN0RMPTR7 RSCAN0.RMPTR7.UINT32
+#define RSCAN0RMPTR7L RSCAN0.RMPTR7.UINT16[L]
+#define RSCAN0RMPTR7LL RSCAN0.RMPTR7.UINT8[LL]
+#define RSCAN0RMPTR7LH RSCAN0.RMPTR7.UINT8[LH]
+#define RSCAN0RMPTR7H RSCAN0.RMPTR7.UINT16[H]
+#define RSCAN0RMPTR7HL RSCAN0.RMPTR7.UINT8[HL]
+#define RSCAN0RMPTR7HH RSCAN0.RMPTR7.UINT8[HH]
+#define RSCAN0RMDF07 RSCAN0.RMDF07.UINT32
+#define RSCAN0RMDF07L RSCAN0.RMDF07.UINT16[L]
+#define RSCAN0RMDF07LL RSCAN0.RMDF07.UINT8[LL]
+#define RSCAN0RMDF07LH RSCAN0.RMDF07.UINT8[LH]
+#define RSCAN0RMDF07H RSCAN0.RMDF07.UINT16[H]
+#define RSCAN0RMDF07HL RSCAN0.RMDF07.UINT8[HL]
+#define RSCAN0RMDF07HH RSCAN0.RMDF07.UINT8[HH]
+#define RSCAN0RMDF17 RSCAN0.RMDF17.UINT32
+#define RSCAN0RMDF17L RSCAN0.RMDF17.UINT16[L]
+#define RSCAN0RMDF17LL RSCAN0.RMDF17.UINT8[LL]
+#define RSCAN0RMDF17LH RSCAN0.RMDF17.UINT8[LH]
+#define RSCAN0RMDF17H RSCAN0.RMDF17.UINT16[H]
+#define RSCAN0RMDF17HL RSCAN0.RMDF17.UINT8[HL]
+#define RSCAN0RMDF17HH RSCAN0.RMDF17.UINT8[HH]
+#define RSCAN0RMID8 RSCAN0.RMID8.UINT32
+#define RSCAN0RMID8L RSCAN0.RMID8.UINT16[L]
+#define RSCAN0RMID8LL RSCAN0.RMID8.UINT8[LL]
+#define RSCAN0RMID8LH RSCAN0.RMID8.UINT8[LH]
+#define RSCAN0RMID8H RSCAN0.RMID8.UINT16[H]
+#define RSCAN0RMID8HL RSCAN0.RMID8.UINT8[HL]
+#define RSCAN0RMID8HH RSCAN0.RMID8.UINT8[HH]
+#define RSCAN0RMPTR8 RSCAN0.RMPTR8.UINT32
+#define RSCAN0RMPTR8L RSCAN0.RMPTR8.UINT16[L]
+#define RSCAN0RMPTR8LL RSCAN0.RMPTR8.UINT8[LL]
+#define RSCAN0RMPTR8LH RSCAN0.RMPTR8.UINT8[LH]
+#define RSCAN0RMPTR8H RSCAN0.RMPTR8.UINT16[H]
+#define RSCAN0RMPTR8HL RSCAN0.RMPTR8.UINT8[HL]
+#define RSCAN0RMPTR8HH RSCAN0.RMPTR8.UINT8[HH]
+#define RSCAN0RMDF08 RSCAN0.RMDF08.UINT32
+#define RSCAN0RMDF08L RSCAN0.RMDF08.UINT16[L]
+#define RSCAN0RMDF08LL RSCAN0.RMDF08.UINT8[LL]
+#define RSCAN0RMDF08LH RSCAN0.RMDF08.UINT8[LH]
+#define RSCAN0RMDF08H RSCAN0.RMDF08.UINT16[H]
+#define RSCAN0RMDF08HL RSCAN0.RMDF08.UINT8[HL]
+#define RSCAN0RMDF08HH RSCAN0.RMDF08.UINT8[HH]
+#define RSCAN0RMDF18 RSCAN0.RMDF18.UINT32
+#define RSCAN0RMDF18L RSCAN0.RMDF18.UINT16[L]
+#define RSCAN0RMDF18LL RSCAN0.RMDF18.UINT8[LL]
+#define RSCAN0RMDF18LH RSCAN0.RMDF18.UINT8[LH]
+#define RSCAN0RMDF18H RSCAN0.RMDF18.UINT16[H]
+#define RSCAN0RMDF18HL RSCAN0.RMDF18.UINT8[HL]
+#define RSCAN0RMDF18HH RSCAN0.RMDF18.UINT8[HH]
+#define RSCAN0RMID9 RSCAN0.RMID9.UINT32
+#define RSCAN0RMID9L RSCAN0.RMID9.UINT16[L]
+#define RSCAN0RMID9LL RSCAN0.RMID9.UINT8[LL]
+#define RSCAN0RMID9LH RSCAN0.RMID9.UINT8[LH]
+#define RSCAN0RMID9H RSCAN0.RMID9.UINT16[H]
+#define RSCAN0RMID9HL RSCAN0.RMID9.UINT8[HL]
+#define RSCAN0RMID9HH RSCAN0.RMID9.UINT8[HH]
+#define RSCAN0RMPTR9 RSCAN0.RMPTR9.UINT32
+#define RSCAN0RMPTR9L RSCAN0.RMPTR9.UINT16[L]
+#define RSCAN0RMPTR9LL RSCAN0.RMPTR9.UINT8[LL]
+#define RSCAN0RMPTR9LH RSCAN0.RMPTR9.UINT8[LH]
+#define RSCAN0RMPTR9H RSCAN0.RMPTR9.UINT16[H]
+#define RSCAN0RMPTR9HL RSCAN0.RMPTR9.UINT8[HL]
+#define RSCAN0RMPTR9HH RSCAN0.RMPTR9.UINT8[HH]
+#define RSCAN0RMDF09 RSCAN0.RMDF09.UINT32
+#define RSCAN0RMDF09L RSCAN0.RMDF09.UINT16[L]
+#define RSCAN0RMDF09LL RSCAN0.RMDF09.UINT8[LL]
+#define RSCAN0RMDF09LH RSCAN0.RMDF09.UINT8[LH]
+#define RSCAN0RMDF09H RSCAN0.RMDF09.UINT16[H]
+#define RSCAN0RMDF09HL RSCAN0.RMDF09.UINT8[HL]
+#define RSCAN0RMDF09HH RSCAN0.RMDF09.UINT8[HH]
+#define RSCAN0RMDF19 RSCAN0.RMDF19.UINT32
+#define RSCAN0RMDF19L RSCAN0.RMDF19.UINT16[L]
+#define RSCAN0RMDF19LL RSCAN0.RMDF19.UINT8[LL]
+#define RSCAN0RMDF19LH RSCAN0.RMDF19.UINT8[LH]
+#define RSCAN0RMDF19H RSCAN0.RMDF19.UINT16[H]
+#define RSCAN0RMDF19HL RSCAN0.RMDF19.UINT8[HL]
+#define RSCAN0RMDF19HH RSCAN0.RMDF19.UINT8[HH]
+#define RSCAN0RMID10 RSCAN0.RMID10.UINT32
+#define RSCAN0RMID10L RSCAN0.RMID10.UINT16[L]
+#define RSCAN0RMID10LL RSCAN0.RMID10.UINT8[LL]
+#define RSCAN0RMID10LH RSCAN0.RMID10.UINT8[LH]
+#define RSCAN0RMID10H RSCAN0.RMID10.UINT16[H]
+#define RSCAN0RMID10HL RSCAN0.RMID10.UINT8[HL]
+#define RSCAN0RMID10HH RSCAN0.RMID10.UINT8[HH]
+#define RSCAN0RMPTR10 RSCAN0.RMPTR10.UINT32
+#define RSCAN0RMPTR10L RSCAN0.RMPTR10.UINT16[L]
+#define RSCAN0RMPTR10LL RSCAN0.RMPTR10.UINT8[LL]
+#define RSCAN0RMPTR10LH RSCAN0.RMPTR10.UINT8[LH]
+#define RSCAN0RMPTR10H RSCAN0.RMPTR10.UINT16[H]
+#define RSCAN0RMPTR10HL RSCAN0.RMPTR10.UINT8[HL]
+#define RSCAN0RMPTR10HH RSCAN0.RMPTR10.UINT8[HH]
+#define RSCAN0RMDF010 RSCAN0.RMDF010.UINT32
+#define RSCAN0RMDF010L RSCAN0.RMDF010.UINT16[L]
+#define RSCAN0RMDF010LL RSCAN0.RMDF010.UINT8[LL]
+#define RSCAN0RMDF010LH RSCAN0.RMDF010.UINT8[LH]
+#define RSCAN0RMDF010H RSCAN0.RMDF010.UINT16[H]
+#define RSCAN0RMDF010HL RSCAN0.RMDF010.UINT8[HL]
+#define RSCAN0RMDF010HH RSCAN0.RMDF010.UINT8[HH]
+#define RSCAN0RMDF110 RSCAN0.RMDF110.UINT32
+#define RSCAN0RMDF110L RSCAN0.RMDF110.UINT16[L]
+#define RSCAN0RMDF110LL RSCAN0.RMDF110.UINT8[LL]
+#define RSCAN0RMDF110LH RSCAN0.RMDF110.UINT8[LH]
+#define RSCAN0RMDF110H RSCAN0.RMDF110.UINT16[H]
+#define RSCAN0RMDF110HL RSCAN0.RMDF110.UINT8[HL]
+#define RSCAN0RMDF110HH RSCAN0.RMDF110.UINT8[HH]
+#define RSCAN0RMID11 RSCAN0.RMID11.UINT32
+#define RSCAN0RMID11L RSCAN0.RMID11.UINT16[L]
+#define RSCAN0RMID11LL RSCAN0.RMID11.UINT8[LL]
+#define RSCAN0RMID11LH RSCAN0.RMID11.UINT8[LH]
+#define RSCAN0RMID11H RSCAN0.RMID11.UINT16[H]
+#define RSCAN0RMID11HL RSCAN0.RMID11.UINT8[HL]
+#define RSCAN0RMID11HH RSCAN0.RMID11.UINT8[HH]
+#define RSCAN0RMPTR11 RSCAN0.RMPTR11.UINT32
+#define RSCAN0RMPTR11L RSCAN0.RMPTR11.UINT16[L]
+#define RSCAN0RMPTR11LL RSCAN0.RMPTR11.UINT8[LL]
+#define RSCAN0RMPTR11LH RSCAN0.RMPTR11.UINT8[LH]
+#define RSCAN0RMPTR11H RSCAN0.RMPTR11.UINT16[H]
+#define RSCAN0RMPTR11HL RSCAN0.RMPTR11.UINT8[HL]
+#define RSCAN0RMPTR11HH RSCAN0.RMPTR11.UINT8[HH]
+#define RSCAN0RMDF011 RSCAN0.RMDF011.UINT32
+#define RSCAN0RMDF011L RSCAN0.RMDF011.UINT16[L]
+#define RSCAN0RMDF011LL RSCAN0.RMDF011.UINT8[LL]
+#define RSCAN0RMDF011LH RSCAN0.RMDF011.UINT8[LH]
+#define RSCAN0RMDF011H RSCAN0.RMDF011.UINT16[H]
+#define RSCAN0RMDF011HL RSCAN0.RMDF011.UINT8[HL]
+#define RSCAN0RMDF011HH RSCAN0.RMDF011.UINT8[HH]
+#define RSCAN0RMDF111 RSCAN0.RMDF111.UINT32
+#define RSCAN0RMDF111L RSCAN0.RMDF111.UINT16[L]
+#define RSCAN0RMDF111LL RSCAN0.RMDF111.UINT8[LL]
+#define RSCAN0RMDF111LH RSCAN0.RMDF111.UINT8[LH]
+#define RSCAN0RMDF111H RSCAN0.RMDF111.UINT16[H]
+#define RSCAN0RMDF111HL RSCAN0.RMDF111.UINT8[HL]
+#define RSCAN0RMDF111HH RSCAN0.RMDF111.UINT8[HH]
+#define RSCAN0RMID12 RSCAN0.RMID12.UINT32
+#define RSCAN0RMID12L RSCAN0.RMID12.UINT16[L]
+#define RSCAN0RMID12LL RSCAN0.RMID12.UINT8[LL]
+#define RSCAN0RMID12LH RSCAN0.RMID12.UINT8[LH]
+#define RSCAN0RMID12H RSCAN0.RMID12.UINT16[H]
+#define RSCAN0RMID12HL RSCAN0.RMID12.UINT8[HL]
+#define RSCAN0RMID12HH RSCAN0.RMID12.UINT8[HH]
+#define RSCAN0RMPTR12 RSCAN0.RMPTR12.UINT32
+#define RSCAN0RMPTR12L RSCAN0.RMPTR12.UINT16[L]
+#define RSCAN0RMPTR12LL RSCAN0.RMPTR12.UINT8[LL]
+#define RSCAN0RMPTR12LH RSCAN0.RMPTR12.UINT8[LH]
+#define RSCAN0RMPTR12H RSCAN0.RMPTR12.UINT16[H]
+#define RSCAN0RMPTR12HL RSCAN0.RMPTR12.UINT8[HL]
+#define RSCAN0RMPTR12HH RSCAN0.RMPTR12.UINT8[HH]
+#define RSCAN0RMDF012 RSCAN0.RMDF012.UINT32
+#define RSCAN0RMDF012L RSCAN0.RMDF012.UINT16[L]
+#define RSCAN0RMDF012LL RSCAN0.RMDF012.UINT8[LL]
+#define RSCAN0RMDF012LH RSCAN0.RMDF012.UINT8[LH]
+#define RSCAN0RMDF012H RSCAN0.RMDF012.UINT16[H]
+#define RSCAN0RMDF012HL RSCAN0.RMDF012.UINT8[HL]
+#define RSCAN0RMDF012HH RSCAN0.RMDF012.UINT8[HH]
+#define RSCAN0RMDF112 RSCAN0.RMDF112.UINT32
+#define RSCAN0RMDF112L RSCAN0.RMDF112.UINT16[L]
+#define RSCAN0RMDF112LL RSCAN0.RMDF112.UINT8[LL]
+#define RSCAN0RMDF112LH RSCAN0.RMDF112.UINT8[LH]
+#define RSCAN0RMDF112H RSCAN0.RMDF112.UINT16[H]
+#define RSCAN0RMDF112HL RSCAN0.RMDF112.UINT8[HL]
+#define RSCAN0RMDF112HH RSCAN0.RMDF112.UINT8[HH]
+#define RSCAN0RMID13 RSCAN0.RMID13.UINT32
+#define RSCAN0RMID13L RSCAN0.RMID13.UINT16[L]
+#define RSCAN0RMID13LL RSCAN0.RMID13.UINT8[LL]
+#define RSCAN0RMID13LH RSCAN0.RMID13.UINT8[LH]
+#define RSCAN0RMID13H RSCAN0.RMID13.UINT16[H]
+#define RSCAN0RMID13HL RSCAN0.RMID13.UINT8[HL]
+#define RSCAN0RMID13HH RSCAN0.RMID13.UINT8[HH]
+#define RSCAN0RMPTR13 RSCAN0.RMPTR13.UINT32
+#define RSCAN0RMPTR13L RSCAN0.RMPTR13.UINT16[L]
+#define RSCAN0RMPTR13LL RSCAN0.RMPTR13.UINT8[LL]
+#define RSCAN0RMPTR13LH RSCAN0.RMPTR13.UINT8[LH]
+#define RSCAN0RMPTR13H RSCAN0.RMPTR13.UINT16[H]
+#define RSCAN0RMPTR13HL RSCAN0.RMPTR13.UINT8[HL]
+#define RSCAN0RMPTR13HH RSCAN0.RMPTR13.UINT8[HH]
+#define RSCAN0RMDF013 RSCAN0.RMDF013.UINT32
+#define RSCAN0RMDF013L RSCAN0.RMDF013.UINT16[L]
+#define RSCAN0RMDF013LL RSCAN0.RMDF013.UINT8[LL]
+#define RSCAN0RMDF013LH RSCAN0.RMDF013.UINT8[LH]
+#define RSCAN0RMDF013H RSCAN0.RMDF013.UINT16[H]
+#define RSCAN0RMDF013HL RSCAN0.RMDF013.UINT8[HL]
+#define RSCAN0RMDF013HH RSCAN0.RMDF013.UINT8[HH]
+#define RSCAN0RMDF113 RSCAN0.RMDF113.UINT32
+#define RSCAN0RMDF113L RSCAN0.RMDF113.UINT16[L]
+#define RSCAN0RMDF113LL RSCAN0.RMDF113.UINT8[LL]
+#define RSCAN0RMDF113LH RSCAN0.RMDF113.UINT8[LH]
+#define RSCAN0RMDF113H RSCAN0.RMDF113.UINT16[H]
+#define RSCAN0RMDF113HL RSCAN0.RMDF113.UINT8[HL]
+#define RSCAN0RMDF113HH RSCAN0.RMDF113.UINT8[HH]
+#define RSCAN0RMID14 RSCAN0.RMID14.UINT32
+#define RSCAN0RMID14L RSCAN0.RMID14.UINT16[L]
+#define RSCAN0RMID14LL RSCAN0.RMID14.UINT8[LL]
+#define RSCAN0RMID14LH RSCAN0.RMID14.UINT8[LH]
+#define RSCAN0RMID14H RSCAN0.RMID14.UINT16[H]
+#define RSCAN0RMID14HL RSCAN0.RMID14.UINT8[HL]
+#define RSCAN0RMID14HH RSCAN0.RMID14.UINT8[HH]
+#define RSCAN0RMPTR14 RSCAN0.RMPTR14.UINT32
+#define RSCAN0RMPTR14L RSCAN0.RMPTR14.UINT16[L]
+#define RSCAN0RMPTR14LL RSCAN0.RMPTR14.UINT8[LL]
+#define RSCAN0RMPTR14LH RSCAN0.RMPTR14.UINT8[LH]
+#define RSCAN0RMPTR14H RSCAN0.RMPTR14.UINT16[H]
+#define RSCAN0RMPTR14HL RSCAN0.RMPTR14.UINT8[HL]
+#define RSCAN0RMPTR14HH RSCAN0.RMPTR14.UINT8[HH]
+#define RSCAN0RMDF014 RSCAN0.RMDF014.UINT32
+#define RSCAN0RMDF014L RSCAN0.RMDF014.UINT16[L]
+#define RSCAN0RMDF014LL RSCAN0.RMDF014.UINT8[LL]
+#define RSCAN0RMDF014LH RSCAN0.RMDF014.UINT8[LH]
+#define RSCAN0RMDF014H RSCAN0.RMDF014.UINT16[H]
+#define RSCAN0RMDF014HL RSCAN0.RMDF014.UINT8[HL]
+#define RSCAN0RMDF014HH RSCAN0.RMDF014.UINT8[HH]
+#define RSCAN0RMDF114 RSCAN0.RMDF114.UINT32
+#define RSCAN0RMDF114L RSCAN0.RMDF114.UINT16[L]
+#define RSCAN0RMDF114LL RSCAN0.RMDF114.UINT8[LL]
+#define RSCAN0RMDF114LH RSCAN0.RMDF114.UINT8[LH]
+#define RSCAN0RMDF114H RSCAN0.RMDF114.UINT16[H]
+#define RSCAN0RMDF114HL RSCAN0.RMDF114.UINT8[HL]
+#define RSCAN0RMDF114HH RSCAN0.RMDF114.UINT8[HH]
+#define RSCAN0RMID15 RSCAN0.RMID15.UINT32
+#define RSCAN0RMID15L RSCAN0.RMID15.UINT16[L]
+#define RSCAN0RMID15LL RSCAN0.RMID15.UINT8[LL]
+#define RSCAN0RMID15LH RSCAN0.RMID15.UINT8[LH]
+#define RSCAN0RMID15H RSCAN0.RMID15.UINT16[H]
+#define RSCAN0RMID15HL RSCAN0.RMID15.UINT8[HL]
+#define RSCAN0RMID15HH RSCAN0.RMID15.UINT8[HH]
+#define RSCAN0RMPTR15 RSCAN0.RMPTR15.UINT32
+#define RSCAN0RMPTR15L RSCAN0.RMPTR15.UINT16[L]
+#define RSCAN0RMPTR15LL RSCAN0.RMPTR15.UINT8[LL]
+#define RSCAN0RMPTR15LH RSCAN0.RMPTR15.UINT8[LH]
+#define RSCAN0RMPTR15H RSCAN0.RMPTR15.UINT16[H]
+#define RSCAN0RMPTR15HL RSCAN0.RMPTR15.UINT8[HL]
+#define RSCAN0RMPTR15HH RSCAN0.RMPTR15.UINT8[HH]
+#define RSCAN0RMDF015 RSCAN0.RMDF015.UINT32
+#define RSCAN0RMDF015L RSCAN0.RMDF015.UINT16[L]
+#define RSCAN0RMDF015LL RSCAN0.RMDF015.UINT8[LL]
+#define RSCAN0RMDF015LH RSCAN0.RMDF015.UINT8[LH]
+#define RSCAN0RMDF015H RSCAN0.RMDF015.UINT16[H]
+#define RSCAN0RMDF015HL RSCAN0.RMDF015.UINT8[HL]
+#define RSCAN0RMDF015HH RSCAN0.RMDF015.UINT8[HH]
+#define RSCAN0RMDF115 RSCAN0.RMDF115.UINT32
+#define RSCAN0RMDF115L RSCAN0.RMDF115.UINT16[L]
+#define RSCAN0RMDF115LL RSCAN0.RMDF115.UINT8[LL]
+#define RSCAN0RMDF115LH RSCAN0.RMDF115.UINT8[LH]
+#define RSCAN0RMDF115H RSCAN0.RMDF115.UINT16[H]
+#define RSCAN0RMDF115HL RSCAN0.RMDF115.UINT8[HL]
+#define RSCAN0RMDF115HH RSCAN0.RMDF115.UINT8[HH]
+#define RSCAN0RMID16 RSCAN0.RMID16.UINT32
+#define RSCAN0RMID16L RSCAN0.RMID16.UINT16[L]
+#define RSCAN0RMID16LL RSCAN0.RMID16.UINT8[LL]
+#define RSCAN0RMID16LH RSCAN0.RMID16.UINT8[LH]
+#define RSCAN0RMID16H RSCAN0.RMID16.UINT16[H]
+#define RSCAN0RMID16HL RSCAN0.RMID16.UINT8[HL]
+#define RSCAN0RMID16HH RSCAN0.RMID16.UINT8[HH]
+#define RSCAN0RMPTR16 RSCAN0.RMPTR16.UINT32
+#define RSCAN0RMPTR16L RSCAN0.RMPTR16.UINT16[L]
+#define RSCAN0RMPTR16LL RSCAN0.RMPTR16.UINT8[LL]
+#define RSCAN0RMPTR16LH RSCAN0.RMPTR16.UINT8[LH]
+#define RSCAN0RMPTR16H RSCAN0.RMPTR16.UINT16[H]
+#define RSCAN0RMPTR16HL RSCAN0.RMPTR16.UINT8[HL]
+#define RSCAN0RMPTR16HH RSCAN0.RMPTR16.UINT8[HH]
+#define RSCAN0RMDF016 RSCAN0.RMDF016.UINT32
+#define RSCAN0RMDF016L RSCAN0.RMDF016.UINT16[L]
+#define RSCAN0RMDF016LL RSCAN0.RMDF016.UINT8[LL]
+#define RSCAN0RMDF016LH RSCAN0.RMDF016.UINT8[LH]
+#define RSCAN0RMDF016H RSCAN0.RMDF016.UINT16[H]
+#define RSCAN0RMDF016HL RSCAN0.RMDF016.UINT8[HL]
+#define RSCAN0RMDF016HH RSCAN0.RMDF016.UINT8[HH]
+#define RSCAN0RMDF116 RSCAN0.RMDF116.UINT32
+#define RSCAN0RMDF116L RSCAN0.RMDF116.UINT16[L]
+#define RSCAN0RMDF116LL RSCAN0.RMDF116.UINT8[LL]
+#define RSCAN0RMDF116LH RSCAN0.RMDF116.UINT8[LH]
+#define RSCAN0RMDF116H RSCAN0.RMDF116.UINT16[H]
+#define RSCAN0RMDF116HL RSCAN0.RMDF116.UINT8[HL]
+#define RSCAN0RMDF116HH RSCAN0.RMDF116.UINT8[HH]
+#define RSCAN0RMID17 RSCAN0.RMID17.UINT32
+#define RSCAN0RMID17L RSCAN0.RMID17.UINT16[L]
+#define RSCAN0RMID17LL RSCAN0.RMID17.UINT8[LL]
+#define RSCAN0RMID17LH RSCAN0.RMID17.UINT8[LH]
+#define RSCAN0RMID17H RSCAN0.RMID17.UINT16[H]
+#define RSCAN0RMID17HL RSCAN0.RMID17.UINT8[HL]
+#define RSCAN0RMID17HH RSCAN0.RMID17.UINT8[HH]
+#define RSCAN0RMPTR17 RSCAN0.RMPTR17.UINT32
+#define RSCAN0RMPTR17L RSCAN0.RMPTR17.UINT16[L]
+#define RSCAN0RMPTR17LL RSCAN0.RMPTR17.UINT8[LL]
+#define RSCAN0RMPTR17LH RSCAN0.RMPTR17.UINT8[LH]
+#define RSCAN0RMPTR17H RSCAN0.RMPTR17.UINT16[H]
+#define RSCAN0RMPTR17HL RSCAN0.RMPTR17.UINT8[HL]
+#define RSCAN0RMPTR17HH RSCAN0.RMPTR17.UINT8[HH]
+#define RSCAN0RMDF017 RSCAN0.RMDF017.UINT32
+#define RSCAN0RMDF017L RSCAN0.RMDF017.UINT16[L]
+#define RSCAN0RMDF017LL RSCAN0.RMDF017.UINT8[LL]
+#define RSCAN0RMDF017LH RSCAN0.RMDF017.UINT8[LH]
+#define RSCAN0RMDF017H RSCAN0.RMDF017.UINT16[H]
+#define RSCAN0RMDF017HL RSCAN0.RMDF017.UINT8[HL]
+#define RSCAN0RMDF017HH RSCAN0.RMDF017.UINT8[HH]
+#define RSCAN0RMDF117 RSCAN0.RMDF117.UINT32
+#define RSCAN0RMDF117L RSCAN0.RMDF117.UINT16[L]
+#define RSCAN0RMDF117LL RSCAN0.RMDF117.UINT8[LL]
+#define RSCAN0RMDF117LH RSCAN0.RMDF117.UINT8[LH]
+#define RSCAN0RMDF117H RSCAN0.RMDF117.UINT16[H]
+#define RSCAN0RMDF117HL RSCAN0.RMDF117.UINT8[HL]
+#define RSCAN0RMDF117HH RSCAN0.RMDF117.UINT8[HH]
+#define RSCAN0RMID18 RSCAN0.RMID18.UINT32
+#define RSCAN0RMID18L RSCAN0.RMID18.UINT16[L]
+#define RSCAN0RMID18LL RSCAN0.RMID18.UINT8[LL]
+#define RSCAN0RMID18LH RSCAN0.RMID18.UINT8[LH]
+#define RSCAN0RMID18H RSCAN0.RMID18.UINT16[H]
+#define RSCAN0RMID18HL RSCAN0.RMID18.UINT8[HL]
+#define RSCAN0RMID18HH RSCAN0.RMID18.UINT8[HH]
+#define RSCAN0RMPTR18 RSCAN0.RMPTR18.UINT32
+#define RSCAN0RMPTR18L RSCAN0.RMPTR18.UINT16[L]
+#define RSCAN0RMPTR18LL RSCAN0.RMPTR18.UINT8[LL]
+#define RSCAN0RMPTR18LH RSCAN0.RMPTR18.UINT8[LH]
+#define RSCAN0RMPTR18H RSCAN0.RMPTR18.UINT16[H]
+#define RSCAN0RMPTR18HL RSCAN0.RMPTR18.UINT8[HL]
+#define RSCAN0RMPTR18HH RSCAN0.RMPTR18.UINT8[HH]
+#define RSCAN0RMDF018 RSCAN0.RMDF018.UINT32
+#define RSCAN0RMDF018L RSCAN0.RMDF018.UINT16[L]
+#define RSCAN0RMDF018LL RSCAN0.RMDF018.UINT8[LL]
+#define RSCAN0RMDF018LH RSCAN0.RMDF018.UINT8[LH]
+#define RSCAN0RMDF018H RSCAN0.RMDF018.UINT16[H]
+#define RSCAN0RMDF018HL RSCAN0.RMDF018.UINT8[HL]
+#define RSCAN0RMDF018HH RSCAN0.RMDF018.UINT8[HH]
+#define RSCAN0RMDF118 RSCAN0.RMDF118.UINT32
+#define RSCAN0RMDF118L RSCAN0.RMDF118.UINT16[L]
+#define RSCAN0RMDF118LL RSCAN0.RMDF118.UINT8[LL]
+#define RSCAN0RMDF118LH RSCAN0.RMDF118.UINT8[LH]
+#define RSCAN0RMDF118H RSCAN0.RMDF118.UINT16[H]
+#define RSCAN0RMDF118HL RSCAN0.RMDF118.UINT8[HL]
+#define RSCAN0RMDF118HH RSCAN0.RMDF118.UINT8[HH]
+#define RSCAN0RMID19 RSCAN0.RMID19.UINT32
+#define RSCAN0RMID19L RSCAN0.RMID19.UINT16[L]
+#define RSCAN0RMID19LL RSCAN0.RMID19.UINT8[LL]
+#define RSCAN0RMID19LH RSCAN0.RMID19.UINT8[LH]
+#define RSCAN0RMID19H RSCAN0.RMID19.UINT16[H]
+#define RSCAN0RMID19HL RSCAN0.RMID19.UINT8[HL]
+#define RSCAN0RMID19HH RSCAN0.RMID19.UINT8[HH]
+#define RSCAN0RMPTR19 RSCAN0.RMPTR19.UINT32
+#define RSCAN0RMPTR19L RSCAN0.RMPTR19.UINT16[L]
+#define RSCAN0RMPTR19LL RSCAN0.RMPTR19.UINT8[LL]
+#define RSCAN0RMPTR19LH RSCAN0.RMPTR19.UINT8[LH]
+#define RSCAN0RMPTR19H RSCAN0.RMPTR19.UINT16[H]
+#define RSCAN0RMPTR19HL RSCAN0.RMPTR19.UINT8[HL]
+#define RSCAN0RMPTR19HH RSCAN0.RMPTR19.UINT8[HH]
+#define RSCAN0RMDF019 RSCAN0.RMDF019.UINT32
+#define RSCAN0RMDF019L RSCAN0.RMDF019.UINT16[L]
+#define RSCAN0RMDF019LL RSCAN0.RMDF019.UINT8[LL]
+#define RSCAN0RMDF019LH RSCAN0.RMDF019.UINT8[LH]
+#define RSCAN0RMDF019H RSCAN0.RMDF019.UINT16[H]
+#define RSCAN0RMDF019HL RSCAN0.RMDF019.UINT8[HL]
+#define RSCAN0RMDF019HH RSCAN0.RMDF019.UINT8[HH]
+#define RSCAN0RMDF119 RSCAN0.RMDF119.UINT32
+#define RSCAN0RMDF119L RSCAN0.RMDF119.UINT16[L]
+#define RSCAN0RMDF119LL RSCAN0.RMDF119.UINT8[LL]
+#define RSCAN0RMDF119LH RSCAN0.RMDF119.UINT8[LH]
+#define RSCAN0RMDF119H RSCAN0.RMDF119.UINT16[H]
+#define RSCAN0RMDF119HL RSCAN0.RMDF119.UINT8[HL]
+#define RSCAN0RMDF119HH RSCAN0.RMDF119.UINT8[HH]
+#define RSCAN0RMID20 RSCAN0.RMID20.UINT32
+#define RSCAN0RMID20L RSCAN0.RMID20.UINT16[L]
+#define RSCAN0RMID20LL RSCAN0.RMID20.UINT8[LL]
+#define RSCAN0RMID20LH RSCAN0.RMID20.UINT8[LH]
+#define RSCAN0RMID20H RSCAN0.RMID20.UINT16[H]
+#define RSCAN0RMID20HL RSCAN0.RMID20.UINT8[HL]
+#define RSCAN0RMID20HH RSCAN0.RMID20.UINT8[HH]
+#define RSCAN0RMPTR20 RSCAN0.RMPTR20.UINT32
+#define RSCAN0RMPTR20L RSCAN0.RMPTR20.UINT16[L]
+#define RSCAN0RMPTR20LL RSCAN0.RMPTR20.UINT8[LL]
+#define RSCAN0RMPTR20LH RSCAN0.RMPTR20.UINT8[LH]
+#define RSCAN0RMPTR20H RSCAN0.RMPTR20.UINT16[H]
+#define RSCAN0RMPTR20HL RSCAN0.RMPTR20.UINT8[HL]
+#define RSCAN0RMPTR20HH RSCAN0.RMPTR20.UINT8[HH]
+#define RSCAN0RMDF020 RSCAN0.RMDF020.UINT32
+#define RSCAN0RMDF020L RSCAN0.RMDF020.UINT16[L]
+#define RSCAN0RMDF020LL RSCAN0.RMDF020.UINT8[LL]
+#define RSCAN0RMDF020LH RSCAN0.RMDF020.UINT8[LH]
+#define RSCAN0RMDF020H RSCAN0.RMDF020.UINT16[H]
+#define RSCAN0RMDF020HL RSCAN0.RMDF020.UINT8[HL]
+#define RSCAN0RMDF020HH RSCAN0.RMDF020.UINT8[HH]
+#define RSCAN0RMDF120 RSCAN0.RMDF120.UINT32
+#define RSCAN0RMDF120L RSCAN0.RMDF120.UINT16[L]
+#define RSCAN0RMDF120LL RSCAN0.RMDF120.UINT8[LL]
+#define RSCAN0RMDF120LH RSCAN0.RMDF120.UINT8[LH]
+#define RSCAN0RMDF120H RSCAN0.RMDF120.UINT16[H]
+#define RSCAN0RMDF120HL RSCAN0.RMDF120.UINT8[HL]
+#define RSCAN0RMDF120HH RSCAN0.RMDF120.UINT8[HH]
+#define RSCAN0RMID21 RSCAN0.RMID21.UINT32
+#define RSCAN0RMID21L RSCAN0.RMID21.UINT16[L]
+#define RSCAN0RMID21LL RSCAN0.RMID21.UINT8[LL]
+#define RSCAN0RMID21LH RSCAN0.RMID21.UINT8[LH]
+#define RSCAN0RMID21H RSCAN0.RMID21.UINT16[H]
+#define RSCAN0RMID21HL RSCAN0.RMID21.UINT8[HL]
+#define RSCAN0RMID21HH RSCAN0.RMID21.UINT8[HH]
+#define RSCAN0RMPTR21 RSCAN0.RMPTR21.UINT32
+#define RSCAN0RMPTR21L RSCAN0.RMPTR21.UINT16[L]
+#define RSCAN0RMPTR21LL RSCAN0.RMPTR21.UINT8[LL]
+#define RSCAN0RMPTR21LH RSCAN0.RMPTR21.UINT8[LH]
+#define RSCAN0RMPTR21H RSCAN0.RMPTR21.UINT16[H]
+#define RSCAN0RMPTR21HL RSCAN0.RMPTR21.UINT8[HL]
+#define RSCAN0RMPTR21HH RSCAN0.RMPTR21.UINT8[HH]
+#define RSCAN0RMDF021 RSCAN0.RMDF021.UINT32
+#define RSCAN0RMDF021L RSCAN0.RMDF021.UINT16[L]
+#define RSCAN0RMDF021LL RSCAN0.RMDF021.UINT8[LL]
+#define RSCAN0RMDF021LH RSCAN0.RMDF021.UINT8[LH]
+#define RSCAN0RMDF021H RSCAN0.RMDF021.UINT16[H]
+#define RSCAN0RMDF021HL RSCAN0.RMDF021.UINT8[HL]
+#define RSCAN0RMDF021HH RSCAN0.RMDF021.UINT8[HH]
+#define RSCAN0RMDF121 RSCAN0.RMDF121.UINT32
+#define RSCAN0RMDF121L RSCAN0.RMDF121.UINT16[L]
+#define RSCAN0RMDF121LL RSCAN0.RMDF121.UINT8[LL]
+#define RSCAN0RMDF121LH RSCAN0.RMDF121.UINT8[LH]
+#define RSCAN0RMDF121H RSCAN0.RMDF121.UINT16[H]
+#define RSCAN0RMDF121HL RSCAN0.RMDF121.UINT8[HL]
+#define RSCAN0RMDF121HH RSCAN0.RMDF121.UINT8[HH]
+#define RSCAN0RMID22 RSCAN0.RMID22.UINT32
+#define RSCAN0RMID22L RSCAN0.RMID22.UINT16[L]
+#define RSCAN0RMID22LL RSCAN0.RMID22.UINT8[LL]
+#define RSCAN0RMID22LH RSCAN0.RMID22.UINT8[LH]
+#define RSCAN0RMID22H RSCAN0.RMID22.UINT16[H]
+#define RSCAN0RMID22HL RSCAN0.RMID22.UINT8[HL]
+#define RSCAN0RMID22HH RSCAN0.RMID22.UINT8[HH]
+#define RSCAN0RMPTR22 RSCAN0.RMPTR22.UINT32
+#define RSCAN0RMPTR22L RSCAN0.RMPTR22.UINT16[L]
+#define RSCAN0RMPTR22LL RSCAN0.RMPTR22.UINT8[LL]
+#define RSCAN0RMPTR22LH RSCAN0.RMPTR22.UINT8[LH]
+#define RSCAN0RMPTR22H RSCAN0.RMPTR22.UINT16[H]
+#define RSCAN0RMPTR22HL RSCAN0.RMPTR22.UINT8[HL]
+#define RSCAN0RMPTR22HH RSCAN0.RMPTR22.UINT8[HH]
+#define RSCAN0RMDF022 RSCAN0.RMDF022.UINT32
+#define RSCAN0RMDF022L RSCAN0.RMDF022.UINT16[L]
+#define RSCAN0RMDF022LL RSCAN0.RMDF022.UINT8[LL]
+#define RSCAN0RMDF022LH RSCAN0.RMDF022.UINT8[LH]
+#define RSCAN0RMDF022H RSCAN0.RMDF022.UINT16[H]
+#define RSCAN0RMDF022HL RSCAN0.RMDF022.UINT8[HL]
+#define RSCAN0RMDF022HH RSCAN0.RMDF022.UINT8[HH]
+#define RSCAN0RMDF122 RSCAN0.RMDF122.UINT32
+#define RSCAN0RMDF122L RSCAN0.RMDF122.UINT16[L]
+#define RSCAN0RMDF122LL RSCAN0.RMDF122.UINT8[LL]
+#define RSCAN0RMDF122LH RSCAN0.RMDF122.UINT8[LH]
+#define RSCAN0RMDF122H RSCAN0.RMDF122.UINT16[H]
+#define RSCAN0RMDF122HL RSCAN0.RMDF122.UINT8[HL]
+#define RSCAN0RMDF122HH RSCAN0.RMDF122.UINT8[HH]
+#define RSCAN0RMID23 RSCAN0.RMID23.UINT32
+#define RSCAN0RMID23L RSCAN0.RMID23.UINT16[L]
+#define RSCAN0RMID23LL RSCAN0.RMID23.UINT8[LL]
+#define RSCAN0RMID23LH RSCAN0.RMID23.UINT8[LH]
+#define RSCAN0RMID23H RSCAN0.RMID23.UINT16[H]
+#define RSCAN0RMID23HL RSCAN0.RMID23.UINT8[HL]
+#define RSCAN0RMID23HH RSCAN0.RMID23.UINT8[HH]
+#define RSCAN0RMPTR23 RSCAN0.RMPTR23.UINT32
+#define RSCAN0RMPTR23L RSCAN0.RMPTR23.UINT16[L]
+#define RSCAN0RMPTR23LL RSCAN0.RMPTR23.UINT8[LL]
+#define RSCAN0RMPTR23LH RSCAN0.RMPTR23.UINT8[LH]
+#define RSCAN0RMPTR23H RSCAN0.RMPTR23.UINT16[H]
+#define RSCAN0RMPTR23HL RSCAN0.RMPTR23.UINT8[HL]
+#define RSCAN0RMPTR23HH RSCAN0.RMPTR23.UINT8[HH]
+#define RSCAN0RMDF023 RSCAN0.RMDF023.UINT32
+#define RSCAN0RMDF023L RSCAN0.RMDF023.UINT16[L]
+#define RSCAN0RMDF023LL RSCAN0.RMDF023.UINT8[LL]
+#define RSCAN0RMDF023LH RSCAN0.RMDF023.UINT8[LH]
+#define RSCAN0RMDF023H RSCAN0.RMDF023.UINT16[H]
+#define RSCAN0RMDF023HL RSCAN0.RMDF023.UINT8[HL]
+#define RSCAN0RMDF023HH RSCAN0.RMDF023.UINT8[HH]
+#define RSCAN0RMDF123 RSCAN0.RMDF123.UINT32
+#define RSCAN0RMDF123L RSCAN0.RMDF123.UINT16[L]
+#define RSCAN0RMDF123LL RSCAN0.RMDF123.UINT8[LL]
+#define RSCAN0RMDF123LH RSCAN0.RMDF123.UINT8[LH]
+#define RSCAN0RMDF123H RSCAN0.RMDF123.UINT16[H]
+#define RSCAN0RMDF123HL RSCAN0.RMDF123.UINT8[HL]
+#define RSCAN0RMDF123HH RSCAN0.RMDF123.UINT8[HH]
+#define RSCAN0RMID24 RSCAN0.RMID24.UINT32
+#define RSCAN0RMID24L RSCAN0.RMID24.UINT16[L]
+#define RSCAN0RMID24LL RSCAN0.RMID24.UINT8[LL]
+#define RSCAN0RMID24LH RSCAN0.RMID24.UINT8[LH]
+#define RSCAN0RMID24H RSCAN0.RMID24.UINT16[H]
+#define RSCAN0RMID24HL RSCAN0.RMID24.UINT8[HL]
+#define RSCAN0RMID24HH RSCAN0.RMID24.UINT8[HH]
+#define RSCAN0RMPTR24 RSCAN0.RMPTR24.UINT32
+#define RSCAN0RMPTR24L RSCAN0.RMPTR24.UINT16[L]
+#define RSCAN0RMPTR24LL RSCAN0.RMPTR24.UINT8[LL]
+#define RSCAN0RMPTR24LH RSCAN0.RMPTR24.UINT8[LH]
+#define RSCAN0RMPTR24H RSCAN0.RMPTR24.UINT16[H]
+#define RSCAN0RMPTR24HL RSCAN0.RMPTR24.UINT8[HL]
+#define RSCAN0RMPTR24HH RSCAN0.RMPTR24.UINT8[HH]
+#define RSCAN0RMDF024 RSCAN0.RMDF024.UINT32
+#define RSCAN0RMDF024L RSCAN0.RMDF024.UINT16[L]
+#define RSCAN0RMDF024LL RSCAN0.RMDF024.UINT8[LL]
+#define RSCAN0RMDF024LH RSCAN0.RMDF024.UINT8[LH]
+#define RSCAN0RMDF024H RSCAN0.RMDF024.UINT16[H]
+#define RSCAN0RMDF024HL RSCAN0.RMDF024.UINT8[HL]
+#define RSCAN0RMDF024HH RSCAN0.RMDF024.UINT8[HH]
+#define RSCAN0RMDF124 RSCAN0.RMDF124.UINT32
+#define RSCAN0RMDF124L RSCAN0.RMDF124.UINT16[L]
+#define RSCAN0RMDF124LL RSCAN0.RMDF124.UINT8[LL]
+#define RSCAN0RMDF124LH RSCAN0.RMDF124.UINT8[LH]
+#define RSCAN0RMDF124H RSCAN0.RMDF124.UINT16[H]
+#define RSCAN0RMDF124HL RSCAN0.RMDF124.UINT8[HL]
+#define RSCAN0RMDF124HH RSCAN0.RMDF124.UINT8[HH]
+#define RSCAN0RMID25 RSCAN0.RMID25.UINT32
+#define RSCAN0RMID25L RSCAN0.RMID25.UINT16[L]
+#define RSCAN0RMID25LL RSCAN0.RMID25.UINT8[LL]
+#define RSCAN0RMID25LH RSCAN0.RMID25.UINT8[LH]
+#define RSCAN0RMID25H RSCAN0.RMID25.UINT16[H]
+#define RSCAN0RMID25HL RSCAN0.RMID25.UINT8[HL]
+#define RSCAN0RMID25HH RSCAN0.RMID25.UINT8[HH]
+#define RSCAN0RMPTR25 RSCAN0.RMPTR25.UINT32
+#define RSCAN0RMPTR25L RSCAN0.RMPTR25.UINT16[L]
+#define RSCAN0RMPTR25LL RSCAN0.RMPTR25.UINT8[LL]
+#define RSCAN0RMPTR25LH RSCAN0.RMPTR25.UINT8[LH]
+#define RSCAN0RMPTR25H RSCAN0.RMPTR25.UINT16[H]
+#define RSCAN0RMPTR25HL RSCAN0.RMPTR25.UINT8[HL]
+#define RSCAN0RMPTR25HH RSCAN0.RMPTR25.UINT8[HH]
+#define RSCAN0RMDF025 RSCAN0.RMDF025.UINT32
+#define RSCAN0RMDF025L RSCAN0.RMDF025.UINT16[L]
+#define RSCAN0RMDF025LL RSCAN0.RMDF025.UINT8[LL]
+#define RSCAN0RMDF025LH RSCAN0.RMDF025.UINT8[LH]
+#define RSCAN0RMDF025H RSCAN0.RMDF025.UINT16[H]
+#define RSCAN0RMDF025HL RSCAN0.RMDF025.UINT8[HL]
+#define RSCAN0RMDF025HH RSCAN0.RMDF025.UINT8[HH]
+#define RSCAN0RMDF125 RSCAN0.RMDF125.UINT32
+#define RSCAN0RMDF125L RSCAN0.RMDF125.UINT16[L]
+#define RSCAN0RMDF125LL RSCAN0.RMDF125.UINT8[LL]
+#define RSCAN0RMDF125LH RSCAN0.RMDF125.UINT8[LH]
+#define RSCAN0RMDF125H RSCAN0.RMDF125.UINT16[H]
+#define RSCAN0RMDF125HL RSCAN0.RMDF125.UINT8[HL]
+#define RSCAN0RMDF125HH RSCAN0.RMDF125.UINT8[HH]
+#define RSCAN0RMID26 RSCAN0.RMID26.UINT32
+#define RSCAN0RMID26L RSCAN0.RMID26.UINT16[L]
+#define RSCAN0RMID26LL RSCAN0.RMID26.UINT8[LL]
+#define RSCAN0RMID26LH RSCAN0.RMID26.UINT8[LH]
+#define RSCAN0RMID26H RSCAN0.RMID26.UINT16[H]
+#define RSCAN0RMID26HL RSCAN0.RMID26.UINT8[HL]
+#define RSCAN0RMID26HH RSCAN0.RMID26.UINT8[HH]
+#define RSCAN0RMPTR26 RSCAN0.RMPTR26.UINT32
+#define RSCAN0RMPTR26L RSCAN0.RMPTR26.UINT16[L]
+#define RSCAN0RMPTR26LL RSCAN0.RMPTR26.UINT8[LL]
+#define RSCAN0RMPTR26LH RSCAN0.RMPTR26.UINT8[LH]
+#define RSCAN0RMPTR26H RSCAN0.RMPTR26.UINT16[H]
+#define RSCAN0RMPTR26HL RSCAN0.RMPTR26.UINT8[HL]
+#define RSCAN0RMPTR26HH RSCAN0.RMPTR26.UINT8[HH]
+#define RSCAN0RMDF026 RSCAN0.RMDF026.UINT32
+#define RSCAN0RMDF026L RSCAN0.RMDF026.UINT16[L]
+#define RSCAN0RMDF026LL RSCAN0.RMDF026.UINT8[LL]
+#define RSCAN0RMDF026LH RSCAN0.RMDF026.UINT8[LH]
+#define RSCAN0RMDF026H RSCAN0.RMDF026.UINT16[H]
+#define RSCAN0RMDF026HL RSCAN0.RMDF026.UINT8[HL]
+#define RSCAN0RMDF026HH RSCAN0.RMDF026.UINT8[HH]
+#define RSCAN0RMDF126 RSCAN0.RMDF126.UINT32
+#define RSCAN0RMDF126L RSCAN0.RMDF126.UINT16[L]
+#define RSCAN0RMDF126LL RSCAN0.RMDF126.UINT8[LL]
+#define RSCAN0RMDF126LH RSCAN0.RMDF126.UINT8[LH]
+#define RSCAN0RMDF126H RSCAN0.RMDF126.UINT16[H]
+#define RSCAN0RMDF126HL RSCAN0.RMDF126.UINT8[HL]
+#define RSCAN0RMDF126HH RSCAN0.RMDF126.UINT8[HH]
+#define RSCAN0RMID27 RSCAN0.RMID27.UINT32
+#define RSCAN0RMID27L RSCAN0.RMID27.UINT16[L]
+#define RSCAN0RMID27LL RSCAN0.RMID27.UINT8[LL]
+#define RSCAN0RMID27LH RSCAN0.RMID27.UINT8[LH]
+#define RSCAN0RMID27H RSCAN0.RMID27.UINT16[H]
+#define RSCAN0RMID27HL RSCAN0.RMID27.UINT8[HL]
+#define RSCAN0RMID27HH RSCAN0.RMID27.UINT8[HH]
+#define RSCAN0RMPTR27 RSCAN0.RMPTR27.UINT32
+#define RSCAN0RMPTR27L RSCAN0.RMPTR27.UINT16[L]
+#define RSCAN0RMPTR27LL RSCAN0.RMPTR27.UINT8[LL]
+#define RSCAN0RMPTR27LH RSCAN0.RMPTR27.UINT8[LH]
+#define RSCAN0RMPTR27H RSCAN0.RMPTR27.UINT16[H]
+#define RSCAN0RMPTR27HL RSCAN0.RMPTR27.UINT8[HL]
+#define RSCAN0RMPTR27HH RSCAN0.RMPTR27.UINT8[HH]
+#define RSCAN0RMDF027 RSCAN0.RMDF027.UINT32
+#define RSCAN0RMDF027L RSCAN0.RMDF027.UINT16[L]
+#define RSCAN0RMDF027LL RSCAN0.RMDF027.UINT8[LL]
+#define RSCAN0RMDF027LH RSCAN0.RMDF027.UINT8[LH]
+#define RSCAN0RMDF027H RSCAN0.RMDF027.UINT16[H]
+#define RSCAN0RMDF027HL RSCAN0.RMDF027.UINT8[HL]
+#define RSCAN0RMDF027HH RSCAN0.RMDF027.UINT8[HH]
+#define RSCAN0RMDF127 RSCAN0.RMDF127.UINT32
+#define RSCAN0RMDF127L RSCAN0.RMDF127.UINT16[L]
+#define RSCAN0RMDF127LL RSCAN0.RMDF127.UINT8[LL]
+#define RSCAN0RMDF127LH RSCAN0.RMDF127.UINT8[LH]
+#define RSCAN0RMDF127H RSCAN0.RMDF127.UINT16[H]
+#define RSCAN0RMDF127HL RSCAN0.RMDF127.UINT8[HL]
+#define RSCAN0RMDF127HH RSCAN0.RMDF127.UINT8[HH]
+#define RSCAN0RMID28 RSCAN0.RMID28.UINT32
+#define RSCAN0RMID28L RSCAN0.RMID28.UINT16[L]
+#define RSCAN0RMID28LL RSCAN0.RMID28.UINT8[LL]
+#define RSCAN0RMID28LH RSCAN0.RMID28.UINT8[LH]
+#define RSCAN0RMID28H RSCAN0.RMID28.UINT16[H]
+#define RSCAN0RMID28HL RSCAN0.RMID28.UINT8[HL]
+#define RSCAN0RMID28HH RSCAN0.RMID28.UINT8[HH]
+#define RSCAN0RMPTR28 RSCAN0.RMPTR28.UINT32
+#define RSCAN0RMPTR28L RSCAN0.RMPTR28.UINT16[L]
+#define RSCAN0RMPTR28LL RSCAN0.RMPTR28.UINT8[LL]
+#define RSCAN0RMPTR28LH RSCAN0.RMPTR28.UINT8[LH]
+#define RSCAN0RMPTR28H RSCAN0.RMPTR28.UINT16[H]
+#define RSCAN0RMPTR28HL RSCAN0.RMPTR28.UINT8[HL]
+#define RSCAN0RMPTR28HH RSCAN0.RMPTR28.UINT8[HH]
+#define RSCAN0RMDF028 RSCAN0.RMDF028.UINT32
+#define RSCAN0RMDF028L RSCAN0.RMDF028.UINT16[L]
+#define RSCAN0RMDF028LL RSCAN0.RMDF028.UINT8[LL]
+#define RSCAN0RMDF028LH RSCAN0.RMDF028.UINT8[LH]
+#define RSCAN0RMDF028H RSCAN0.RMDF028.UINT16[H]
+#define RSCAN0RMDF028HL RSCAN0.RMDF028.UINT8[HL]
+#define RSCAN0RMDF028HH RSCAN0.RMDF028.UINT8[HH]
+#define RSCAN0RMDF128 RSCAN0.RMDF128.UINT32
+#define RSCAN0RMDF128L RSCAN0.RMDF128.UINT16[L]
+#define RSCAN0RMDF128LL RSCAN0.RMDF128.UINT8[LL]
+#define RSCAN0RMDF128LH RSCAN0.RMDF128.UINT8[LH]
+#define RSCAN0RMDF128H RSCAN0.RMDF128.UINT16[H]
+#define RSCAN0RMDF128HL RSCAN0.RMDF128.UINT8[HL]
+#define RSCAN0RMDF128HH RSCAN0.RMDF128.UINT8[HH]
+#define RSCAN0RMID29 RSCAN0.RMID29.UINT32
+#define RSCAN0RMID29L RSCAN0.RMID29.UINT16[L]
+#define RSCAN0RMID29LL RSCAN0.RMID29.UINT8[LL]
+#define RSCAN0RMID29LH RSCAN0.RMID29.UINT8[LH]
+#define RSCAN0RMID29H RSCAN0.RMID29.UINT16[H]
+#define RSCAN0RMID29HL RSCAN0.RMID29.UINT8[HL]
+#define RSCAN0RMID29HH RSCAN0.RMID29.UINT8[HH]
+#define RSCAN0RMPTR29 RSCAN0.RMPTR29.UINT32
+#define RSCAN0RMPTR29L RSCAN0.RMPTR29.UINT16[L]
+#define RSCAN0RMPTR29LL RSCAN0.RMPTR29.UINT8[LL]
+#define RSCAN0RMPTR29LH RSCAN0.RMPTR29.UINT8[LH]
+#define RSCAN0RMPTR29H RSCAN0.RMPTR29.UINT16[H]
+#define RSCAN0RMPTR29HL RSCAN0.RMPTR29.UINT8[HL]
+#define RSCAN0RMPTR29HH RSCAN0.RMPTR29.UINT8[HH]
+#define RSCAN0RMDF029 RSCAN0.RMDF029.UINT32
+#define RSCAN0RMDF029L RSCAN0.RMDF029.UINT16[L]
+#define RSCAN0RMDF029LL RSCAN0.RMDF029.UINT8[LL]
+#define RSCAN0RMDF029LH RSCAN0.RMDF029.UINT8[LH]
+#define RSCAN0RMDF029H RSCAN0.RMDF029.UINT16[H]
+#define RSCAN0RMDF029HL RSCAN0.RMDF029.UINT8[HL]
+#define RSCAN0RMDF029HH RSCAN0.RMDF029.UINT8[HH]
+#define RSCAN0RMDF129 RSCAN0.RMDF129.UINT32
+#define RSCAN0RMDF129L RSCAN0.RMDF129.UINT16[L]
+#define RSCAN0RMDF129LL RSCAN0.RMDF129.UINT8[LL]
+#define RSCAN0RMDF129LH RSCAN0.RMDF129.UINT8[LH]
+#define RSCAN0RMDF129H RSCAN0.RMDF129.UINT16[H]
+#define RSCAN0RMDF129HL RSCAN0.RMDF129.UINT8[HL]
+#define RSCAN0RMDF129HH RSCAN0.RMDF129.UINT8[HH]
+#define RSCAN0RMID30 RSCAN0.RMID30.UINT32
+#define RSCAN0RMID30L RSCAN0.RMID30.UINT16[L]
+#define RSCAN0RMID30LL RSCAN0.RMID30.UINT8[LL]
+#define RSCAN0RMID30LH RSCAN0.RMID30.UINT8[LH]
+#define RSCAN0RMID30H RSCAN0.RMID30.UINT16[H]
+#define RSCAN0RMID30HL RSCAN0.RMID30.UINT8[HL]
+#define RSCAN0RMID30HH RSCAN0.RMID30.UINT8[HH]
+#define RSCAN0RMPTR30 RSCAN0.RMPTR30.UINT32
+#define RSCAN0RMPTR30L RSCAN0.RMPTR30.UINT16[L]
+#define RSCAN0RMPTR30LL RSCAN0.RMPTR30.UINT8[LL]
+#define RSCAN0RMPTR30LH RSCAN0.RMPTR30.UINT8[LH]
+#define RSCAN0RMPTR30H RSCAN0.RMPTR30.UINT16[H]
+#define RSCAN0RMPTR30HL RSCAN0.RMPTR30.UINT8[HL]
+#define RSCAN0RMPTR30HH RSCAN0.RMPTR30.UINT8[HH]
+#define RSCAN0RMDF030 RSCAN0.RMDF030.UINT32
+#define RSCAN0RMDF030L RSCAN0.RMDF030.UINT16[L]
+#define RSCAN0RMDF030LL RSCAN0.RMDF030.UINT8[LL]
+#define RSCAN0RMDF030LH RSCAN0.RMDF030.UINT8[LH]
+#define RSCAN0RMDF030H RSCAN0.RMDF030.UINT16[H]
+#define RSCAN0RMDF030HL RSCAN0.RMDF030.UINT8[HL]
+#define RSCAN0RMDF030HH RSCAN0.RMDF030.UINT8[HH]
+#define RSCAN0RMDF130 RSCAN0.RMDF130.UINT32
+#define RSCAN0RMDF130L RSCAN0.RMDF130.UINT16[L]
+#define RSCAN0RMDF130LL RSCAN0.RMDF130.UINT8[LL]
+#define RSCAN0RMDF130LH RSCAN0.RMDF130.UINT8[LH]
+#define RSCAN0RMDF130H RSCAN0.RMDF130.UINT16[H]
+#define RSCAN0RMDF130HL RSCAN0.RMDF130.UINT8[HL]
+#define RSCAN0RMDF130HH RSCAN0.RMDF130.UINT8[HH]
+#define RSCAN0RMID31 RSCAN0.RMID31.UINT32
+#define RSCAN0RMID31L RSCAN0.RMID31.UINT16[L]
+#define RSCAN0RMID31LL RSCAN0.RMID31.UINT8[LL]
+#define RSCAN0RMID31LH RSCAN0.RMID31.UINT8[LH]
+#define RSCAN0RMID31H RSCAN0.RMID31.UINT16[H]
+#define RSCAN0RMID31HL RSCAN0.RMID31.UINT8[HL]
+#define RSCAN0RMID31HH RSCAN0.RMID31.UINT8[HH]
+#define RSCAN0RMPTR31 RSCAN0.RMPTR31.UINT32
+#define RSCAN0RMPTR31L RSCAN0.RMPTR31.UINT16[L]
+#define RSCAN0RMPTR31LL RSCAN0.RMPTR31.UINT8[LL]
+#define RSCAN0RMPTR31LH RSCAN0.RMPTR31.UINT8[LH]
+#define RSCAN0RMPTR31H RSCAN0.RMPTR31.UINT16[H]
+#define RSCAN0RMPTR31HL RSCAN0.RMPTR31.UINT8[HL]
+#define RSCAN0RMPTR31HH RSCAN0.RMPTR31.UINT8[HH]
+#define RSCAN0RMDF031 RSCAN0.RMDF031.UINT32
+#define RSCAN0RMDF031L RSCAN0.RMDF031.UINT16[L]
+#define RSCAN0RMDF031LL RSCAN0.RMDF031.UINT8[LL]
+#define RSCAN0RMDF031LH RSCAN0.RMDF031.UINT8[LH]
+#define RSCAN0RMDF031H RSCAN0.RMDF031.UINT16[H]
+#define RSCAN0RMDF031HL RSCAN0.RMDF031.UINT8[HL]
+#define RSCAN0RMDF031HH RSCAN0.RMDF031.UINT8[HH]
+#define RSCAN0RMDF131 RSCAN0.RMDF131.UINT32
+#define RSCAN0RMDF131L RSCAN0.RMDF131.UINT16[L]
+#define RSCAN0RMDF131LL RSCAN0.RMDF131.UINT8[LL]
+#define RSCAN0RMDF131LH RSCAN0.RMDF131.UINT8[LH]
+#define RSCAN0RMDF131H RSCAN0.RMDF131.UINT16[H]
+#define RSCAN0RMDF131HL RSCAN0.RMDF131.UINT8[HL]
+#define RSCAN0RMDF131HH RSCAN0.RMDF131.UINT8[HH]
+#define RSCAN0RMID32 RSCAN0.RMID32.UINT32
+#define RSCAN0RMID32L RSCAN0.RMID32.UINT16[L]
+#define RSCAN0RMID32LL RSCAN0.RMID32.UINT8[LL]
+#define RSCAN0RMID32LH RSCAN0.RMID32.UINT8[LH]
+#define RSCAN0RMID32H RSCAN0.RMID32.UINT16[H]
+#define RSCAN0RMID32HL RSCAN0.RMID32.UINT8[HL]
+#define RSCAN0RMID32HH RSCAN0.RMID32.UINT8[HH]
+#define RSCAN0RMPTR32 RSCAN0.RMPTR32.UINT32
+#define RSCAN0RMPTR32L RSCAN0.RMPTR32.UINT16[L]
+#define RSCAN0RMPTR32LL RSCAN0.RMPTR32.UINT8[LL]
+#define RSCAN0RMPTR32LH RSCAN0.RMPTR32.UINT8[LH]
+#define RSCAN0RMPTR32H RSCAN0.RMPTR32.UINT16[H]
+#define RSCAN0RMPTR32HL RSCAN0.RMPTR32.UINT8[HL]
+#define RSCAN0RMPTR32HH RSCAN0.RMPTR32.UINT8[HH]
+#define RSCAN0RMDF032 RSCAN0.RMDF032.UINT32
+#define RSCAN0RMDF032L RSCAN0.RMDF032.UINT16[L]
+#define RSCAN0RMDF032LL RSCAN0.RMDF032.UINT8[LL]
+#define RSCAN0RMDF032LH RSCAN0.RMDF032.UINT8[LH]
+#define RSCAN0RMDF032H RSCAN0.RMDF032.UINT16[H]
+#define RSCAN0RMDF032HL RSCAN0.RMDF032.UINT8[HL]
+#define RSCAN0RMDF032HH RSCAN0.RMDF032.UINT8[HH]
+#define RSCAN0RMDF132 RSCAN0.RMDF132.UINT32
+#define RSCAN0RMDF132L RSCAN0.RMDF132.UINT16[L]
+#define RSCAN0RMDF132LL RSCAN0.RMDF132.UINT8[LL]
+#define RSCAN0RMDF132LH RSCAN0.RMDF132.UINT8[LH]
+#define RSCAN0RMDF132H RSCAN0.RMDF132.UINT16[H]
+#define RSCAN0RMDF132HL RSCAN0.RMDF132.UINT8[HL]
+#define RSCAN0RMDF132HH RSCAN0.RMDF132.UINT8[HH]
+#define RSCAN0RMID33 RSCAN0.RMID33.UINT32
+#define RSCAN0RMID33L RSCAN0.RMID33.UINT16[L]
+#define RSCAN0RMID33LL RSCAN0.RMID33.UINT8[LL]
+#define RSCAN0RMID33LH RSCAN0.RMID33.UINT8[LH]
+#define RSCAN0RMID33H RSCAN0.RMID33.UINT16[H]
+#define RSCAN0RMID33HL RSCAN0.RMID33.UINT8[HL]
+#define RSCAN0RMID33HH RSCAN0.RMID33.UINT8[HH]
+#define RSCAN0RMPTR33 RSCAN0.RMPTR33.UINT32
+#define RSCAN0RMPTR33L RSCAN0.RMPTR33.UINT16[L]
+#define RSCAN0RMPTR33LL RSCAN0.RMPTR33.UINT8[LL]
+#define RSCAN0RMPTR33LH RSCAN0.RMPTR33.UINT8[LH]
+#define RSCAN0RMPTR33H RSCAN0.RMPTR33.UINT16[H]
+#define RSCAN0RMPTR33HL RSCAN0.RMPTR33.UINT8[HL]
+#define RSCAN0RMPTR33HH RSCAN0.RMPTR33.UINT8[HH]
+#define RSCAN0RMDF033 RSCAN0.RMDF033.UINT32
+#define RSCAN0RMDF033L RSCAN0.RMDF033.UINT16[L]
+#define RSCAN0RMDF033LL RSCAN0.RMDF033.UINT8[LL]
+#define RSCAN0RMDF033LH RSCAN0.RMDF033.UINT8[LH]
+#define RSCAN0RMDF033H RSCAN0.RMDF033.UINT16[H]
+#define RSCAN0RMDF033HL RSCAN0.RMDF033.UINT8[HL]
+#define RSCAN0RMDF033HH RSCAN0.RMDF033.UINT8[HH]
+#define RSCAN0RMDF133 RSCAN0.RMDF133.UINT32
+#define RSCAN0RMDF133L RSCAN0.RMDF133.UINT16[L]
+#define RSCAN0RMDF133LL RSCAN0.RMDF133.UINT8[LL]
+#define RSCAN0RMDF133LH RSCAN0.RMDF133.UINT8[LH]
+#define RSCAN0RMDF133H RSCAN0.RMDF133.UINT16[H]
+#define RSCAN0RMDF133HL RSCAN0.RMDF133.UINT8[HL]
+#define RSCAN0RMDF133HH RSCAN0.RMDF133.UINT8[HH]
+#define RSCAN0RMID34 RSCAN0.RMID34.UINT32
+#define RSCAN0RMID34L RSCAN0.RMID34.UINT16[L]
+#define RSCAN0RMID34LL RSCAN0.RMID34.UINT8[LL]
+#define RSCAN0RMID34LH RSCAN0.RMID34.UINT8[LH]
+#define RSCAN0RMID34H RSCAN0.RMID34.UINT16[H]
+#define RSCAN0RMID34HL RSCAN0.RMID34.UINT8[HL]
+#define RSCAN0RMID34HH RSCAN0.RMID34.UINT8[HH]
+#define RSCAN0RMPTR34 RSCAN0.RMPTR34.UINT32
+#define RSCAN0RMPTR34L RSCAN0.RMPTR34.UINT16[L]
+#define RSCAN0RMPTR34LL RSCAN0.RMPTR34.UINT8[LL]
+#define RSCAN0RMPTR34LH RSCAN0.RMPTR34.UINT8[LH]
+#define RSCAN0RMPTR34H RSCAN0.RMPTR34.UINT16[H]
+#define RSCAN0RMPTR34HL RSCAN0.RMPTR34.UINT8[HL]
+#define RSCAN0RMPTR34HH RSCAN0.RMPTR34.UINT8[HH]
+#define RSCAN0RMDF034 RSCAN0.RMDF034.UINT32
+#define RSCAN0RMDF034L RSCAN0.RMDF034.UINT16[L]
+#define RSCAN0RMDF034LL RSCAN0.RMDF034.UINT8[LL]
+#define RSCAN0RMDF034LH RSCAN0.RMDF034.UINT8[LH]
+#define RSCAN0RMDF034H RSCAN0.RMDF034.UINT16[H]
+#define RSCAN0RMDF034HL RSCAN0.RMDF034.UINT8[HL]
+#define RSCAN0RMDF034HH RSCAN0.RMDF034.UINT8[HH]
+#define RSCAN0RMDF134 RSCAN0.RMDF134.UINT32
+#define RSCAN0RMDF134L RSCAN0.RMDF134.UINT16[L]
+#define RSCAN0RMDF134LL RSCAN0.RMDF134.UINT8[LL]
+#define RSCAN0RMDF134LH RSCAN0.RMDF134.UINT8[LH]
+#define RSCAN0RMDF134H RSCAN0.RMDF134.UINT16[H]
+#define RSCAN0RMDF134HL RSCAN0.RMDF134.UINT8[HL]
+#define RSCAN0RMDF134HH RSCAN0.RMDF134.UINT8[HH]
+#define RSCAN0RMID35 RSCAN0.RMID35.UINT32
+#define RSCAN0RMID35L RSCAN0.RMID35.UINT16[L]
+#define RSCAN0RMID35LL RSCAN0.RMID35.UINT8[LL]
+#define RSCAN0RMID35LH RSCAN0.RMID35.UINT8[LH]
+#define RSCAN0RMID35H RSCAN0.RMID35.UINT16[H]
+#define RSCAN0RMID35HL RSCAN0.RMID35.UINT8[HL]
+#define RSCAN0RMID35HH RSCAN0.RMID35.UINT8[HH]
+#define RSCAN0RMPTR35 RSCAN0.RMPTR35.UINT32
+#define RSCAN0RMPTR35L RSCAN0.RMPTR35.UINT16[L]
+#define RSCAN0RMPTR35LL RSCAN0.RMPTR35.UINT8[LL]
+#define RSCAN0RMPTR35LH RSCAN0.RMPTR35.UINT8[LH]
+#define RSCAN0RMPTR35H RSCAN0.RMPTR35.UINT16[H]
+#define RSCAN0RMPTR35HL RSCAN0.RMPTR35.UINT8[HL]
+#define RSCAN0RMPTR35HH RSCAN0.RMPTR35.UINT8[HH]
+#define RSCAN0RMDF035 RSCAN0.RMDF035.UINT32
+#define RSCAN0RMDF035L RSCAN0.RMDF035.UINT16[L]
+#define RSCAN0RMDF035LL RSCAN0.RMDF035.UINT8[LL]
+#define RSCAN0RMDF035LH RSCAN0.RMDF035.UINT8[LH]
+#define RSCAN0RMDF035H RSCAN0.RMDF035.UINT16[H]
+#define RSCAN0RMDF035HL RSCAN0.RMDF035.UINT8[HL]
+#define RSCAN0RMDF035HH RSCAN0.RMDF035.UINT8[HH]
+#define RSCAN0RMDF135 RSCAN0.RMDF135.UINT32
+#define RSCAN0RMDF135L RSCAN0.RMDF135.UINT16[L]
+#define RSCAN0RMDF135LL RSCAN0.RMDF135.UINT8[LL]
+#define RSCAN0RMDF135LH RSCAN0.RMDF135.UINT8[LH]
+#define RSCAN0RMDF135H RSCAN0.RMDF135.UINT16[H]
+#define RSCAN0RMDF135HL RSCAN0.RMDF135.UINT8[HL]
+#define RSCAN0RMDF135HH RSCAN0.RMDF135.UINT8[HH]
+#define RSCAN0RMID36 RSCAN0.RMID36.UINT32
+#define RSCAN0RMID36L RSCAN0.RMID36.UINT16[L]
+#define RSCAN0RMID36LL RSCAN0.RMID36.UINT8[LL]
+#define RSCAN0RMID36LH RSCAN0.RMID36.UINT8[LH]
+#define RSCAN0RMID36H RSCAN0.RMID36.UINT16[H]
+#define RSCAN0RMID36HL RSCAN0.RMID36.UINT8[HL]
+#define RSCAN0RMID36HH RSCAN0.RMID36.UINT8[HH]
+#define RSCAN0RMPTR36 RSCAN0.RMPTR36.UINT32
+#define RSCAN0RMPTR36L RSCAN0.RMPTR36.UINT16[L]
+#define RSCAN0RMPTR36LL RSCAN0.RMPTR36.UINT8[LL]
+#define RSCAN0RMPTR36LH RSCAN0.RMPTR36.UINT8[LH]
+#define RSCAN0RMPTR36H RSCAN0.RMPTR36.UINT16[H]
+#define RSCAN0RMPTR36HL RSCAN0.RMPTR36.UINT8[HL]
+#define RSCAN0RMPTR36HH RSCAN0.RMPTR36.UINT8[HH]
+#define RSCAN0RMDF036 RSCAN0.RMDF036.UINT32
+#define RSCAN0RMDF036L RSCAN0.RMDF036.UINT16[L]
+#define RSCAN0RMDF036LL RSCAN0.RMDF036.UINT8[LL]
+#define RSCAN0RMDF036LH RSCAN0.RMDF036.UINT8[LH]
+#define RSCAN0RMDF036H RSCAN0.RMDF036.UINT16[H]
+#define RSCAN0RMDF036HL RSCAN0.RMDF036.UINT8[HL]
+#define RSCAN0RMDF036HH RSCAN0.RMDF036.UINT8[HH]
+#define RSCAN0RMDF136 RSCAN0.RMDF136.UINT32
+#define RSCAN0RMDF136L RSCAN0.RMDF136.UINT16[L]
+#define RSCAN0RMDF136LL RSCAN0.RMDF136.UINT8[LL]
+#define RSCAN0RMDF136LH RSCAN0.RMDF136.UINT8[LH]
+#define RSCAN0RMDF136H RSCAN0.RMDF136.UINT16[H]
+#define RSCAN0RMDF136HL RSCAN0.RMDF136.UINT8[HL]
+#define RSCAN0RMDF136HH RSCAN0.RMDF136.UINT8[HH]
+#define RSCAN0RMID37 RSCAN0.RMID37.UINT32
+#define RSCAN0RMID37L RSCAN0.RMID37.UINT16[L]
+#define RSCAN0RMID37LL RSCAN0.RMID37.UINT8[LL]
+#define RSCAN0RMID37LH RSCAN0.RMID37.UINT8[LH]
+#define RSCAN0RMID37H RSCAN0.RMID37.UINT16[H]
+#define RSCAN0RMID37HL RSCAN0.RMID37.UINT8[HL]
+#define RSCAN0RMID37HH RSCAN0.RMID37.UINT8[HH]
+#define RSCAN0RMPTR37 RSCAN0.RMPTR37.UINT32
+#define RSCAN0RMPTR37L RSCAN0.RMPTR37.UINT16[L]
+#define RSCAN0RMPTR37LL RSCAN0.RMPTR37.UINT8[LL]
+#define RSCAN0RMPTR37LH RSCAN0.RMPTR37.UINT8[LH]
+#define RSCAN0RMPTR37H RSCAN0.RMPTR37.UINT16[H]
+#define RSCAN0RMPTR37HL RSCAN0.RMPTR37.UINT8[HL]
+#define RSCAN0RMPTR37HH RSCAN0.RMPTR37.UINT8[HH]
+#define RSCAN0RMDF037 RSCAN0.RMDF037.UINT32
+#define RSCAN0RMDF037L RSCAN0.RMDF037.UINT16[L]
+#define RSCAN0RMDF037LL RSCAN0.RMDF037.UINT8[LL]
+#define RSCAN0RMDF037LH RSCAN0.RMDF037.UINT8[LH]
+#define RSCAN0RMDF037H RSCAN0.RMDF037.UINT16[H]
+#define RSCAN0RMDF037HL RSCAN0.RMDF037.UINT8[HL]
+#define RSCAN0RMDF037HH RSCAN0.RMDF037.UINT8[HH]
+#define RSCAN0RMDF137 RSCAN0.RMDF137.UINT32
+#define RSCAN0RMDF137L RSCAN0.RMDF137.UINT16[L]
+#define RSCAN0RMDF137LL RSCAN0.RMDF137.UINT8[LL]
+#define RSCAN0RMDF137LH RSCAN0.RMDF137.UINT8[LH]
+#define RSCAN0RMDF137H RSCAN0.RMDF137.UINT16[H]
+#define RSCAN0RMDF137HL RSCAN0.RMDF137.UINT8[HL]
+#define RSCAN0RMDF137HH RSCAN0.RMDF137.UINT8[HH]
+#define RSCAN0RMID38 RSCAN0.RMID38.UINT32
+#define RSCAN0RMID38L RSCAN0.RMID38.UINT16[L]
+#define RSCAN0RMID38LL RSCAN0.RMID38.UINT8[LL]
+#define RSCAN0RMID38LH RSCAN0.RMID38.UINT8[LH]
+#define RSCAN0RMID38H RSCAN0.RMID38.UINT16[H]
+#define RSCAN0RMID38HL RSCAN0.RMID38.UINT8[HL]
+#define RSCAN0RMID38HH RSCAN0.RMID38.UINT8[HH]
+#define RSCAN0RMPTR38 RSCAN0.RMPTR38.UINT32
+#define RSCAN0RMPTR38L RSCAN0.RMPTR38.UINT16[L]
+#define RSCAN0RMPTR38LL RSCAN0.RMPTR38.UINT8[LL]
+#define RSCAN0RMPTR38LH RSCAN0.RMPTR38.UINT8[LH]
+#define RSCAN0RMPTR38H RSCAN0.RMPTR38.UINT16[H]
+#define RSCAN0RMPTR38HL RSCAN0.RMPTR38.UINT8[HL]
+#define RSCAN0RMPTR38HH RSCAN0.RMPTR38.UINT8[HH]
+#define RSCAN0RMDF038 RSCAN0.RMDF038.UINT32
+#define RSCAN0RMDF038L RSCAN0.RMDF038.UINT16[L]
+#define RSCAN0RMDF038LL RSCAN0.RMDF038.UINT8[LL]
+#define RSCAN0RMDF038LH RSCAN0.RMDF038.UINT8[LH]
+#define RSCAN0RMDF038H RSCAN0.RMDF038.UINT16[H]
+#define RSCAN0RMDF038HL RSCAN0.RMDF038.UINT8[HL]
+#define RSCAN0RMDF038HH RSCAN0.RMDF038.UINT8[HH]
+#define RSCAN0RMDF138 RSCAN0.RMDF138.UINT32
+#define RSCAN0RMDF138L RSCAN0.RMDF138.UINT16[L]
+#define RSCAN0RMDF138LL RSCAN0.RMDF138.UINT8[LL]
+#define RSCAN0RMDF138LH RSCAN0.RMDF138.UINT8[LH]
+#define RSCAN0RMDF138H RSCAN0.RMDF138.UINT16[H]
+#define RSCAN0RMDF138HL RSCAN0.RMDF138.UINT8[HL]
+#define RSCAN0RMDF138HH RSCAN0.RMDF138.UINT8[HH]
+#define RSCAN0RMID39 RSCAN0.RMID39.UINT32
+#define RSCAN0RMID39L RSCAN0.RMID39.UINT16[L]
+#define RSCAN0RMID39LL RSCAN0.RMID39.UINT8[LL]
+#define RSCAN0RMID39LH RSCAN0.RMID39.UINT8[LH]
+#define RSCAN0RMID39H RSCAN0.RMID39.UINT16[H]
+#define RSCAN0RMID39HL RSCAN0.RMID39.UINT8[HL]
+#define RSCAN0RMID39HH RSCAN0.RMID39.UINT8[HH]
+#define RSCAN0RMPTR39 RSCAN0.RMPTR39.UINT32
+#define RSCAN0RMPTR39L RSCAN0.RMPTR39.UINT16[L]
+#define RSCAN0RMPTR39LL RSCAN0.RMPTR39.UINT8[LL]
+#define RSCAN0RMPTR39LH RSCAN0.RMPTR39.UINT8[LH]
+#define RSCAN0RMPTR39H RSCAN0.RMPTR39.UINT16[H]
+#define RSCAN0RMPTR39HL RSCAN0.RMPTR39.UINT8[HL]
+#define RSCAN0RMPTR39HH RSCAN0.RMPTR39.UINT8[HH]
+#define RSCAN0RMDF039 RSCAN0.RMDF039.UINT32
+#define RSCAN0RMDF039L RSCAN0.RMDF039.UINT16[L]
+#define RSCAN0RMDF039LL RSCAN0.RMDF039.UINT8[LL]
+#define RSCAN0RMDF039LH RSCAN0.RMDF039.UINT8[LH]
+#define RSCAN0RMDF039H RSCAN0.RMDF039.UINT16[H]
+#define RSCAN0RMDF039HL RSCAN0.RMDF039.UINT8[HL]
+#define RSCAN0RMDF039HH RSCAN0.RMDF039.UINT8[HH]
+#define RSCAN0RMDF139 RSCAN0.RMDF139.UINT32
+#define RSCAN0RMDF139L RSCAN0.RMDF139.UINT16[L]
+#define RSCAN0RMDF139LL RSCAN0.RMDF139.UINT8[LL]
+#define RSCAN0RMDF139LH RSCAN0.RMDF139.UINT8[LH]
+#define RSCAN0RMDF139H RSCAN0.RMDF139.UINT16[H]
+#define RSCAN0RMDF139HL RSCAN0.RMDF139.UINT8[HL]
+#define RSCAN0RMDF139HH RSCAN0.RMDF139.UINT8[HH]
+#define RSCAN0RMID40 RSCAN0.RMID40.UINT32
+#define RSCAN0RMID40L RSCAN0.RMID40.UINT16[L]
+#define RSCAN0RMID40LL RSCAN0.RMID40.UINT8[LL]
+#define RSCAN0RMID40LH RSCAN0.RMID40.UINT8[LH]
+#define RSCAN0RMID40H RSCAN0.RMID40.UINT16[H]
+#define RSCAN0RMID40HL RSCAN0.RMID40.UINT8[HL]
+#define RSCAN0RMID40HH RSCAN0.RMID40.UINT8[HH]
+#define RSCAN0RMPTR40 RSCAN0.RMPTR40.UINT32
+#define RSCAN0RMPTR40L RSCAN0.RMPTR40.UINT16[L]
+#define RSCAN0RMPTR40LL RSCAN0.RMPTR40.UINT8[LL]
+#define RSCAN0RMPTR40LH RSCAN0.RMPTR40.UINT8[LH]
+#define RSCAN0RMPTR40H RSCAN0.RMPTR40.UINT16[H]
+#define RSCAN0RMPTR40HL RSCAN0.RMPTR40.UINT8[HL]
+#define RSCAN0RMPTR40HH RSCAN0.RMPTR40.UINT8[HH]
+#define RSCAN0RMDF040 RSCAN0.RMDF040.UINT32
+#define RSCAN0RMDF040L RSCAN0.RMDF040.UINT16[L]
+#define RSCAN0RMDF040LL RSCAN0.RMDF040.UINT8[LL]
+#define RSCAN0RMDF040LH RSCAN0.RMDF040.UINT8[LH]
+#define RSCAN0RMDF040H RSCAN0.RMDF040.UINT16[H]
+#define RSCAN0RMDF040HL RSCAN0.RMDF040.UINT8[HL]
+#define RSCAN0RMDF040HH RSCAN0.RMDF040.UINT8[HH]
+#define RSCAN0RMDF140 RSCAN0.RMDF140.UINT32
+#define RSCAN0RMDF140L RSCAN0.RMDF140.UINT16[L]
+#define RSCAN0RMDF140LL RSCAN0.RMDF140.UINT8[LL]
+#define RSCAN0RMDF140LH RSCAN0.RMDF140.UINT8[LH]
+#define RSCAN0RMDF140H RSCAN0.RMDF140.UINT16[H]
+#define RSCAN0RMDF140HL RSCAN0.RMDF140.UINT8[HL]
+#define RSCAN0RMDF140HH RSCAN0.RMDF140.UINT8[HH]
+#define RSCAN0RMID41 RSCAN0.RMID41.UINT32
+#define RSCAN0RMID41L RSCAN0.RMID41.UINT16[L]
+#define RSCAN0RMID41LL RSCAN0.RMID41.UINT8[LL]
+#define RSCAN0RMID41LH RSCAN0.RMID41.UINT8[LH]
+#define RSCAN0RMID41H RSCAN0.RMID41.UINT16[H]
+#define RSCAN0RMID41HL RSCAN0.RMID41.UINT8[HL]
+#define RSCAN0RMID41HH RSCAN0.RMID41.UINT8[HH]
+#define RSCAN0RMPTR41 RSCAN0.RMPTR41.UINT32
+#define RSCAN0RMPTR41L RSCAN0.RMPTR41.UINT16[L]
+#define RSCAN0RMPTR41LL RSCAN0.RMPTR41.UINT8[LL]
+#define RSCAN0RMPTR41LH RSCAN0.RMPTR41.UINT8[LH]
+#define RSCAN0RMPTR41H RSCAN0.RMPTR41.UINT16[H]
+#define RSCAN0RMPTR41HL RSCAN0.RMPTR41.UINT8[HL]
+#define RSCAN0RMPTR41HH RSCAN0.RMPTR41.UINT8[HH]
+#define RSCAN0RMDF041 RSCAN0.RMDF041.UINT32
+#define RSCAN0RMDF041L RSCAN0.RMDF041.UINT16[L]
+#define RSCAN0RMDF041LL RSCAN0.RMDF041.UINT8[LL]
+#define RSCAN0RMDF041LH RSCAN0.RMDF041.UINT8[LH]
+#define RSCAN0RMDF041H RSCAN0.RMDF041.UINT16[H]
+#define RSCAN0RMDF041HL RSCAN0.RMDF041.UINT8[HL]
+#define RSCAN0RMDF041HH RSCAN0.RMDF041.UINT8[HH]
+#define RSCAN0RMDF141 RSCAN0.RMDF141.UINT32
+#define RSCAN0RMDF141L RSCAN0.RMDF141.UINT16[L]
+#define RSCAN0RMDF141LL RSCAN0.RMDF141.UINT8[LL]
+#define RSCAN0RMDF141LH RSCAN0.RMDF141.UINT8[LH]
+#define RSCAN0RMDF141H RSCAN0.RMDF141.UINT16[H]
+#define RSCAN0RMDF141HL RSCAN0.RMDF141.UINT8[HL]
+#define RSCAN0RMDF141HH RSCAN0.RMDF141.UINT8[HH]
+#define RSCAN0RMID42 RSCAN0.RMID42.UINT32
+#define RSCAN0RMID42L RSCAN0.RMID42.UINT16[L]
+#define RSCAN0RMID42LL RSCAN0.RMID42.UINT8[LL]
+#define RSCAN0RMID42LH RSCAN0.RMID42.UINT8[LH]
+#define RSCAN0RMID42H RSCAN0.RMID42.UINT16[H]
+#define RSCAN0RMID42HL RSCAN0.RMID42.UINT8[HL]
+#define RSCAN0RMID42HH RSCAN0.RMID42.UINT8[HH]
+#define RSCAN0RMPTR42 RSCAN0.RMPTR42.UINT32
+#define RSCAN0RMPTR42L RSCAN0.RMPTR42.UINT16[L]
+#define RSCAN0RMPTR42LL RSCAN0.RMPTR42.UINT8[LL]
+#define RSCAN0RMPTR42LH RSCAN0.RMPTR42.UINT8[LH]
+#define RSCAN0RMPTR42H RSCAN0.RMPTR42.UINT16[H]
+#define RSCAN0RMPTR42HL RSCAN0.RMPTR42.UINT8[HL]
+#define RSCAN0RMPTR42HH RSCAN0.RMPTR42.UINT8[HH]
+#define RSCAN0RMDF042 RSCAN0.RMDF042.UINT32
+#define RSCAN0RMDF042L RSCAN0.RMDF042.UINT16[L]
+#define RSCAN0RMDF042LL RSCAN0.RMDF042.UINT8[LL]
+#define RSCAN0RMDF042LH RSCAN0.RMDF042.UINT8[LH]
+#define RSCAN0RMDF042H RSCAN0.RMDF042.UINT16[H]
+#define RSCAN0RMDF042HL RSCAN0.RMDF042.UINT8[HL]
+#define RSCAN0RMDF042HH RSCAN0.RMDF042.UINT8[HH]
+#define RSCAN0RMDF142 RSCAN0.RMDF142.UINT32
+#define RSCAN0RMDF142L RSCAN0.RMDF142.UINT16[L]
+#define RSCAN0RMDF142LL RSCAN0.RMDF142.UINT8[LL]
+#define RSCAN0RMDF142LH RSCAN0.RMDF142.UINT8[LH]
+#define RSCAN0RMDF142H RSCAN0.RMDF142.UINT16[H]
+#define RSCAN0RMDF142HL RSCAN0.RMDF142.UINT8[HL]
+#define RSCAN0RMDF142HH RSCAN0.RMDF142.UINT8[HH]
+#define RSCAN0RMID43 RSCAN0.RMID43.UINT32
+#define RSCAN0RMID43L RSCAN0.RMID43.UINT16[L]
+#define RSCAN0RMID43LL RSCAN0.RMID43.UINT8[LL]
+#define RSCAN0RMID43LH RSCAN0.RMID43.UINT8[LH]
+#define RSCAN0RMID43H RSCAN0.RMID43.UINT16[H]
+#define RSCAN0RMID43HL RSCAN0.RMID43.UINT8[HL]
+#define RSCAN0RMID43HH RSCAN0.RMID43.UINT8[HH]
+#define RSCAN0RMPTR43 RSCAN0.RMPTR43.UINT32
+#define RSCAN0RMPTR43L RSCAN0.RMPTR43.UINT16[L]
+#define RSCAN0RMPTR43LL RSCAN0.RMPTR43.UINT8[LL]
+#define RSCAN0RMPTR43LH RSCAN0.RMPTR43.UINT8[LH]
+#define RSCAN0RMPTR43H RSCAN0.RMPTR43.UINT16[H]
+#define RSCAN0RMPTR43HL RSCAN0.RMPTR43.UINT8[HL]
+#define RSCAN0RMPTR43HH RSCAN0.RMPTR43.UINT8[HH]
+#define RSCAN0RMDF043 RSCAN0.RMDF043.UINT32
+#define RSCAN0RMDF043L RSCAN0.RMDF043.UINT16[L]
+#define RSCAN0RMDF043LL RSCAN0.RMDF043.UINT8[LL]
+#define RSCAN0RMDF043LH RSCAN0.RMDF043.UINT8[LH]
+#define RSCAN0RMDF043H RSCAN0.RMDF043.UINT16[H]
+#define RSCAN0RMDF043HL RSCAN0.RMDF043.UINT8[HL]
+#define RSCAN0RMDF043HH RSCAN0.RMDF043.UINT8[HH]
+#define RSCAN0RMDF143 RSCAN0.RMDF143.UINT32
+#define RSCAN0RMDF143L RSCAN0.RMDF143.UINT16[L]
+#define RSCAN0RMDF143LL RSCAN0.RMDF143.UINT8[LL]
+#define RSCAN0RMDF143LH RSCAN0.RMDF143.UINT8[LH]
+#define RSCAN0RMDF143H RSCAN0.RMDF143.UINT16[H]
+#define RSCAN0RMDF143HL RSCAN0.RMDF143.UINT8[HL]
+#define RSCAN0RMDF143HH RSCAN0.RMDF143.UINT8[HH]
+#define RSCAN0RMID44 RSCAN0.RMID44.UINT32
+#define RSCAN0RMID44L RSCAN0.RMID44.UINT16[L]
+#define RSCAN0RMID44LL RSCAN0.RMID44.UINT8[LL]
+#define RSCAN0RMID44LH RSCAN0.RMID44.UINT8[LH]
+#define RSCAN0RMID44H RSCAN0.RMID44.UINT16[H]
+#define RSCAN0RMID44HL RSCAN0.RMID44.UINT8[HL]
+#define RSCAN0RMID44HH RSCAN0.RMID44.UINT8[HH]
+#define RSCAN0RMPTR44 RSCAN0.RMPTR44.UINT32
+#define RSCAN0RMPTR44L RSCAN0.RMPTR44.UINT16[L]
+#define RSCAN0RMPTR44LL RSCAN0.RMPTR44.UINT8[LL]
+#define RSCAN0RMPTR44LH RSCAN0.RMPTR44.UINT8[LH]
+#define RSCAN0RMPTR44H RSCAN0.RMPTR44.UINT16[H]
+#define RSCAN0RMPTR44HL RSCAN0.RMPTR44.UINT8[HL]
+#define RSCAN0RMPTR44HH RSCAN0.RMPTR44.UINT8[HH]
+#define RSCAN0RMDF044 RSCAN0.RMDF044.UINT32
+#define RSCAN0RMDF044L RSCAN0.RMDF044.UINT16[L]
+#define RSCAN0RMDF044LL RSCAN0.RMDF044.UINT8[LL]
+#define RSCAN0RMDF044LH RSCAN0.RMDF044.UINT8[LH]
+#define RSCAN0RMDF044H RSCAN0.RMDF044.UINT16[H]
+#define RSCAN0RMDF044HL RSCAN0.RMDF044.UINT8[HL]
+#define RSCAN0RMDF044HH RSCAN0.RMDF044.UINT8[HH]
+#define RSCAN0RMDF144 RSCAN0.RMDF144.UINT32
+#define RSCAN0RMDF144L RSCAN0.RMDF144.UINT16[L]
+#define RSCAN0RMDF144LL RSCAN0.RMDF144.UINT8[LL]
+#define RSCAN0RMDF144LH RSCAN0.RMDF144.UINT8[LH]
+#define RSCAN0RMDF144H RSCAN0.RMDF144.UINT16[H]
+#define RSCAN0RMDF144HL RSCAN0.RMDF144.UINT8[HL]
+#define RSCAN0RMDF144HH RSCAN0.RMDF144.UINT8[HH]
+#define RSCAN0RMID45 RSCAN0.RMID45.UINT32
+#define RSCAN0RMID45L RSCAN0.RMID45.UINT16[L]
+#define RSCAN0RMID45LL RSCAN0.RMID45.UINT8[LL]
+#define RSCAN0RMID45LH RSCAN0.RMID45.UINT8[LH]
+#define RSCAN0RMID45H RSCAN0.RMID45.UINT16[H]
+#define RSCAN0RMID45HL RSCAN0.RMID45.UINT8[HL]
+#define RSCAN0RMID45HH RSCAN0.RMID45.UINT8[HH]
+#define RSCAN0RMPTR45 RSCAN0.RMPTR45.UINT32
+#define RSCAN0RMPTR45L RSCAN0.RMPTR45.UINT16[L]
+#define RSCAN0RMPTR45LL RSCAN0.RMPTR45.UINT8[LL]
+#define RSCAN0RMPTR45LH RSCAN0.RMPTR45.UINT8[LH]
+#define RSCAN0RMPTR45H RSCAN0.RMPTR45.UINT16[H]
+#define RSCAN0RMPTR45HL RSCAN0.RMPTR45.UINT8[HL]
+#define RSCAN0RMPTR45HH RSCAN0.RMPTR45.UINT8[HH]
+#define RSCAN0RMDF045 RSCAN0.RMDF045.UINT32
+#define RSCAN0RMDF045L RSCAN0.RMDF045.UINT16[L]
+#define RSCAN0RMDF045LL RSCAN0.RMDF045.UINT8[LL]
+#define RSCAN0RMDF045LH RSCAN0.RMDF045.UINT8[LH]
+#define RSCAN0RMDF045H RSCAN0.RMDF045.UINT16[H]
+#define RSCAN0RMDF045HL RSCAN0.RMDF045.UINT8[HL]
+#define RSCAN0RMDF045HH RSCAN0.RMDF045.UINT8[HH]
+#define RSCAN0RMDF145 RSCAN0.RMDF145.UINT32
+#define RSCAN0RMDF145L RSCAN0.RMDF145.UINT16[L]
+#define RSCAN0RMDF145LL RSCAN0.RMDF145.UINT8[LL]
+#define RSCAN0RMDF145LH RSCAN0.RMDF145.UINT8[LH]
+#define RSCAN0RMDF145H RSCAN0.RMDF145.UINT16[H]
+#define RSCAN0RMDF145HL RSCAN0.RMDF145.UINT8[HL]
+#define RSCAN0RMDF145HH RSCAN0.RMDF145.UINT8[HH]
+#define RSCAN0RMID46 RSCAN0.RMID46.UINT32
+#define RSCAN0RMID46L RSCAN0.RMID46.UINT16[L]
+#define RSCAN0RMID46LL RSCAN0.RMID46.UINT8[LL]
+#define RSCAN0RMID46LH RSCAN0.RMID46.UINT8[LH]
+#define RSCAN0RMID46H RSCAN0.RMID46.UINT16[H]
+#define RSCAN0RMID46HL RSCAN0.RMID46.UINT8[HL]
+#define RSCAN0RMID46HH RSCAN0.RMID46.UINT8[HH]
+#define RSCAN0RMPTR46 RSCAN0.RMPTR46.UINT32
+#define RSCAN0RMPTR46L RSCAN0.RMPTR46.UINT16[L]
+#define RSCAN0RMPTR46LL RSCAN0.RMPTR46.UINT8[LL]
+#define RSCAN0RMPTR46LH RSCAN0.RMPTR46.UINT8[LH]
+#define RSCAN0RMPTR46H RSCAN0.RMPTR46.UINT16[H]
+#define RSCAN0RMPTR46HL RSCAN0.RMPTR46.UINT8[HL]
+#define RSCAN0RMPTR46HH RSCAN0.RMPTR46.UINT8[HH]
+#define RSCAN0RMDF046 RSCAN0.RMDF046.UINT32
+#define RSCAN0RMDF046L RSCAN0.RMDF046.UINT16[L]
+#define RSCAN0RMDF046LL RSCAN0.RMDF046.UINT8[LL]
+#define RSCAN0RMDF046LH RSCAN0.RMDF046.UINT8[LH]
+#define RSCAN0RMDF046H RSCAN0.RMDF046.UINT16[H]
+#define RSCAN0RMDF046HL RSCAN0.RMDF046.UINT8[HL]
+#define RSCAN0RMDF046HH RSCAN0.RMDF046.UINT8[HH]
+#define RSCAN0RMDF146 RSCAN0.RMDF146.UINT32
+#define RSCAN0RMDF146L RSCAN0.RMDF146.UINT16[L]
+#define RSCAN0RMDF146LL RSCAN0.RMDF146.UINT8[LL]
+#define RSCAN0RMDF146LH RSCAN0.RMDF146.UINT8[LH]
+#define RSCAN0RMDF146H RSCAN0.RMDF146.UINT16[H]
+#define RSCAN0RMDF146HL RSCAN0.RMDF146.UINT8[HL]
+#define RSCAN0RMDF146HH RSCAN0.RMDF146.UINT8[HH]
+#define RSCAN0RMID47 RSCAN0.RMID47.UINT32
+#define RSCAN0RMID47L RSCAN0.RMID47.UINT16[L]
+#define RSCAN0RMID47LL RSCAN0.RMID47.UINT8[LL]
+#define RSCAN0RMID47LH RSCAN0.RMID47.UINT8[LH]
+#define RSCAN0RMID47H RSCAN0.RMID47.UINT16[H]
+#define RSCAN0RMID47HL RSCAN0.RMID47.UINT8[HL]
+#define RSCAN0RMID47HH RSCAN0.RMID47.UINT8[HH]
+#define RSCAN0RMPTR47 RSCAN0.RMPTR47.UINT32
+#define RSCAN0RMPTR47L RSCAN0.RMPTR47.UINT16[L]
+#define RSCAN0RMPTR47LL RSCAN0.RMPTR47.UINT8[LL]
+#define RSCAN0RMPTR47LH RSCAN0.RMPTR47.UINT8[LH]
+#define RSCAN0RMPTR47H RSCAN0.RMPTR47.UINT16[H]
+#define RSCAN0RMPTR47HL RSCAN0.RMPTR47.UINT8[HL]
+#define RSCAN0RMPTR47HH RSCAN0.RMPTR47.UINT8[HH]
+#define RSCAN0RMDF047 RSCAN0.RMDF047.UINT32
+#define RSCAN0RMDF047L RSCAN0.RMDF047.UINT16[L]
+#define RSCAN0RMDF047LL RSCAN0.RMDF047.UINT8[LL]
+#define RSCAN0RMDF047LH RSCAN0.RMDF047.UINT8[LH]
+#define RSCAN0RMDF047H RSCAN0.RMDF047.UINT16[H]
+#define RSCAN0RMDF047HL RSCAN0.RMDF047.UINT8[HL]
+#define RSCAN0RMDF047HH RSCAN0.RMDF047.UINT8[HH]
+#define RSCAN0RMDF147 RSCAN0.RMDF147.UINT32
+#define RSCAN0RMDF147L RSCAN0.RMDF147.UINT16[L]
+#define RSCAN0RMDF147LL RSCAN0.RMDF147.UINT8[LL]
+#define RSCAN0RMDF147LH RSCAN0.RMDF147.UINT8[LH]
+#define RSCAN0RMDF147H RSCAN0.RMDF147.UINT16[H]
+#define RSCAN0RMDF147HL RSCAN0.RMDF147.UINT8[HL]
+#define RSCAN0RMDF147HH RSCAN0.RMDF147.UINT8[HH]
+#define RSCAN0RMID48 RSCAN0.RMID48.UINT32
+#define RSCAN0RMID48L RSCAN0.RMID48.UINT16[L]
+#define RSCAN0RMID48LL RSCAN0.RMID48.UINT8[LL]
+#define RSCAN0RMID48LH RSCAN0.RMID48.UINT8[LH]
+#define RSCAN0RMID48H RSCAN0.RMID48.UINT16[H]
+#define RSCAN0RMID48HL RSCAN0.RMID48.UINT8[HL]
+#define RSCAN0RMID48HH RSCAN0.RMID48.UINT8[HH]
+#define RSCAN0RMPTR48 RSCAN0.RMPTR48.UINT32
+#define RSCAN0RMPTR48L RSCAN0.RMPTR48.UINT16[L]
+#define RSCAN0RMPTR48LL RSCAN0.RMPTR48.UINT8[LL]
+#define RSCAN0RMPTR48LH RSCAN0.RMPTR48.UINT8[LH]
+#define RSCAN0RMPTR48H RSCAN0.RMPTR48.UINT16[H]
+#define RSCAN0RMPTR48HL RSCAN0.RMPTR48.UINT8[HL]
+#define RSCAN0RMPTR48HH RSCAN0.RMPTR48.UINT8[HH]
+#define RSCAN0RMDF048 RSCAN0.RMDF048.UINT32
+#define RSCAN0RMDF048L RSCAN0.RMDF048.UINT16[L]
+#define RSCAN0RMDF048LL RSCAN0.RMDF048.UINT8[LL]
+#define RSCAN0RMDF048LH RSCAN0.RMDF048.UINT8[LH]
+#define RSCAN0RMDF048H RSCAN0.RMDF048.UINT16[H]
+#define RSCAN0RMDF048HL RSCAN0.RMDF048.UINT8[HL]
+#define RSCAN0RMDF048HH RSCAN0.RMDF048.UINT8[HH]
+#define RSCAN0RMDF148 RSCAN0.RMDF148.UINT32
+#define RSCAN0RMDF148L RSCAN0.RMDF148.UINT16[L]
+#define RSCAN0RMDF148LL RSCAN0.RMDF148.UINT8[LL]
+#define RSCAN0RMDF148LH RSCAN0.RMDF148.UINT8[LH]
+#define RSCAN0RMDF148H RSCAN0.RMDF148.UINT16[H]
+#define RSCAN0RMDF148HL RSCAN0.RMDF148.UINT8[HL]
+#define RSCAN0RMDF148HH RSCAN0.RMDF148.UINT8[HH]
+#define RSCAN0RMID49 RSCAN0.RMID49.UINT32
+#define RSCAN0RMID49L RSCAN0.RMID49.UINT16[L]
+#define RSCAN0RMID49LL RSCAN0.RMID49.UINT8[LL]
+#define RSCAN0RMID49LH RSCAN0.RMID49.UINT8[LH]
+#define RSCAN0RMID49H RSCAN0.RMID49.UINT16[H]
+#define RSCAN0RMID49HL RSCAN0.RMID49.UINT8[HL]
+#define RSCAN0RMID49HH RSCAN0.RMID49.UINT8[HH]
+#define RSCAN0RMPTR49 RSCAN0.RMPTR49.UINT32
+#define RSCAN0RMPTR49L RSCAN0.RMPTR49.UINT16[L]
+#define RSCAN0RMPTR49LL RSCAN0.RMPTR49.UINT8[LL]
+#define RSCAN0RMPTR49LH RSCAN0.RMPTR49.UINT8[LH]
+#define RSCAN0RMPTR49H RSCAN0.RMPTR49.UINT16[H]
+#define RSCAN0RMPTR49HL RSCAN0.RMPTR49.UINT8[HL]
+#define RSCAN0RMPTR49HH RSCAN0.RMPTR49.UINT8[HH]
+#define RSCAN0RMDF049 RSCAN0.RMDF049.UINT32
+#define RSCAN0RMDF049L RSCAN0.RMDF049.UINT16[L]
+#define RSCAN0RMDF049LL RSCAN0.RMDF049.UINT8[LL]
+#define RSCAN0RMDF049LH RSCAN0.RMDF049.UINT8[LH]
+#define RSCAN0RMDF049H RSCAN0.RMDF049.UINT16[H]
+#define RSCAN0RMDF049HL RSCAN0.RMDF049.UINT8[HL]
+#define RSCAN0RMDF049HH RSCAN0.RMDF049.UINT8[HH]
+#define RSCAN0RMDF149 RSCAN0.RMDF149.UINT32
+#define RSCAN0RMDF149L RSCAN0.RMDF149.UINT16[L]
+#define RSCAN0RMDF149LL RSCAN0.RMDF149.UINT8[LL]
+#define RSCAN0RMDF149LH RSCAN0.RMDF149.UINT8[LH]
+#define RSCAN0RMDF149H RSCAN0.RMDF149.UINT16[H]
+#define RSCAN0RMDF149HL RSCAN0.RMDF149.UINT8[HL]
+#define RSCAN0RMDF149HH RSCAN0.RMDF149.UINT8[HH]
+#define RSCAN0RMID50 RSCAN0.RMID50.UINT32
+#define RSCAN0RMID50L RSCAN0.RMID50.UINT16[L]
+#define RSCAN0RMID50LL RSCAN0.RMID50.UINT8[LL]
+#define RSCAN0RMID50LH RSCAN0.RMID50.UINT8[LH]
+#define RSCAN0RMID50H RSCAN0.RMID50.UINT16[H]
+#define RSCAN0RMID50HL RSCAN0.RMID50.UINT8[HL]
+#define RSCAN0RMID50HH RSCAN0.RMID50.UINT8[HH]
+#define RSCAN0RMPTR50 RSCAN0.RMPTR50.UINT32
+#define RSCAN0RMPTR50L RSCAN0.RMPTR50.UINT16[L]
+#define RSCAN0RMPTR50LL RSCAN0.RMPTR50.UINT8[LL]
+#define RSCAN0RMPTR50LH RSCAN0.RMPTR50.UINT8[LH]
+#define RSCAN0RMPTR50H RSCAN0.RMPTR50.UINT16[H]
+#define RSCAN0RMPTR50HL RSCAN0.RMPTR50.UINT8[HL]
+#define RSCAN0RMPTR50HH RSCAN0.RMPTR50.UINT8[HH]
+#define RSCAN0RMDF050 RSCAN0.RMDF050.UINT32
+#define RSCAN0RMDF050L RSCAN0.RMDF050.UINT16[L]
+#define RSCAN0RMDF050LL RSCAN0.RMDF050.UINT8[LL]
+#define RSCAN0RMDF050LH RSCAN0.RMDF050.UINT8[LH]
+#define RSCAN0RMDF050H RSCAN0.RMDF050.UINT16[H]
+#define RSCAN0RMDF050HL RSCAN0.RMDF050.UINT8[HL]
+#define RSCAN0RMDF050HH RSCAN0.RMDF050.UINT8[HH]
+#define RSCAN0RMDF150 RSCAN0.RMDF150.UINT32
+#define RSCAN0RMDF150L RSCAN0.RMDF150.UINT16[L]
+#define RSCAN0RMDF150LL RSCAN0.RMDF150.UINT8[LL]
+#define RSCAN0RMDF150LH RSCAN0.RMDF150.UINT8[LH]
+#define RSCAN0RMDF150H RSCAN0.RMDF150.UINT16[H]
+#define RSCAN0RMDF150HL RSCAN0.RMDF150.UINT8[HL]
+#define RSCAN0RMDF150HH RSCAN0.RMDF150.UINT8[HH]
+#define RSCAN0RMID51 RSCAN0.RMID51.UINT32
+#define RSCAN0RMID51L RSCAN0.RMID51.UINT16[L]
+#define RSCAN0RMID51LL RSCAN0.RMID51.UINT8[LL]
+#define RSCAN0RMID51LH RSCAN0.RMID51.UINT8[LH]
+#define RSCAN0RMID51H RSCAN0.RMID51.UINT16[H]
+#define RSCAN0RMID51HL RSCAN0.RMID51.UINT8[HL]
+#define RSCAN0RMID51HH RSCAN0.RMID51.UINT8[HH]
+#define RSCAN0RMPTR51 RSCAN0.RMPTR51.UINT32
+#define RSCAN0RMPTR51L RSCAN0.RMPTR51.UINT16[L]
+#define RSCAN0RMPTR51LL RSCAN0.RMPTR51.UINT8[LL]
+#define RSCAN0RMPTR51LH RSCAN0.RMPTR51.UINT8[LH]
+#define RSCAN0RMPTR51H RSCAN0.RMPTR51.UINT16[H]
+#define RSCAN0RMPTR51HL RSCAN0.RMPTR51.UINT8[HL]
+#define RSCAN0RMPTR51HH RSCAN0.RMPTR51.UINT8[HH]
+#define RSCAN0RMDF051 RSCAN0.RMDF051.UINT32
+#define RSCAN0RMDF051L RSCAN0.RMDF051.UINT16[L]
+#define RSCAN0RMDF051LL RSCAN0.RMDF051.UINT8[LL]
+#define RSCAN0RMDF051LH RSCAN0.RMDF051.UINT8[LH]
+#define RSCAN0RMDF051H RSCAN0.RMDF051.UINT16[H]
+#define RSCAN0RMDF051HL RSCAN0.RMDF051.UINT8[HL]
+#define RSCAN0RMDF051HH RSCAN0.RMDF051.UINT8[HH]
+#define RSCAN0RMDF151 RSCAN0.RMDF151.UINT32
+#define RSCAN0RMDF151L RSCAN0.RMDF151.UINT16[L]
+#define RSCAN0RMDF151LL RSCAN0.RMDF151.UINT8[LL]
+#define RSCAN0RMDF151LH RSCAN0.RMDF151.UINT8[LH]
+#define RSCAN0RMDF151H RSCAN0.RMDF151.UINT16[H]
+#define RSCAN0RMDF151HL RSCAN0.RMDF151.UINT8[HL]
+#define RSCAN0RMDF151HH RSCAN0.RMDF151.UINT8[HH]
+#define RSCAN0RMID52 RSCAN0.RMID52.UINT32
+#define RSCAN0RMID52L RSCAN0.RMID52.UINT16[L]
+#define RSCAN0RMID52LL RSCAN0.RMID52.UINT8[LL]
+#define RSCAN0RMID52LH RSCAN0.RMID52.UINT8[LH]
+#define RSCAN0RMID52H RSCAN0.RMID52.UINT16[H]
+#define RSCAN0RMID52HL RSCAN0.RMID52.UINT8[HL]
+#define RSCAN0RMID52HH RSCAN0.RMID52.UINT8[HH]
+#define RSCAN0RMPTR52 RSCAN0.RMPTR52.UINT32
+#define RSCAN0RMPTR52L RSCAN0.RMPTR52.UINT16[L]
+#define RSCAN0RMPTR52LL RSCAN0.RMPTR52.UINT8[LL]
+#define RSCAN0RMPTR52LH RSCAN0.RMPTR52.UINT8[LH]
+#define RSCAN0RMPTR52H RSCAN0.RMPTR52.UINT16[H]
+#define RSCAN0RMPTR52HL RSCAN0.RMPTR52.UINT8[HL]
+#define RSCAN0RMPTR52HH RSCAN0.RMPTR52.UINT8[HH]
+#define RSCAN0RMDF052 RSCAN0.RMDF052.UINT32
+#define RSCAN0RMDF052L RSCAN0.RMDF052.UINT16[L]
+#define RSCAN0RMDF052LL RSCAN0.RMDF052.UINT8[LL]
+#define RSCAN0RMDF052LH RSCAN0.RMDF052.UINT8[LH]
+#define RSCAN0RMDF052H RSCAN0.RMDF052.UINT16[H]
+#define RSCAN0RMDF052HL RSCAN0.RMDF052.UINT8[HL]
+#define RSCAN0RMDF052HH RSCAN0.RMDF052.UINT8[HH]
+#define RSCAN0RMDF152 RSCAN0.RMDF152.UINT32
+#define RSCAN0RMDF152L RSCAN0.RMDF152.UINT16[L]
+#define RSCAN0RMDF152LL RSCAN0.RMDF152.UINT8[LL]
+#define RSCAN0RMDF152LH RSCAN0.RMDF152.UINT8[LH]
+#define RSCAN0RMDF152H RSCAN0.RMDF152.UINT16[H]
+#define RSCAN0RMDF152HL RSCAN0.RMDF152.UINT8[HL]
+#define RSCAN0RMDF152HH RSCAN0.RMDF152.UINT8[HH]
+#define RSCAN0RMID53 RSCAN0.RMID53.UINT32
+#define RSCAN0RMID53L RSCAN0.RMID53.UINT16[L]
+#define RSCAN0RMID53LL RSCAN0.RMID53.UINT8[LL]
+#define RSCAN0RMID53LH RSCAN0.RMID53.UINT8[LH]
+#define RSCAN0RMID53H RSCAN0.RMID53.UINT16[H]
+#define RSCAN0RMID53HL RSCAN0.RMID53.UINT8[HL]
+#define RSCAN0RMID53HH RSCAN0.RMID53.UINT8[HH]
+#define RSCAN0RMPTR53 RSCAN0.RMPTR53.UINT32
+#define RSCAN0RMPTR53L RSCAN0.RMPTR53.UINT16[L]
+#define RSCAN0RMPTR53LL RSCAN0.RMPTR53.UINT8[LL]
+#define RSCAN0RMPTR53LH RSCAN0.RMPTR53.UINT8[LH]
+#define RSCAN0RMPTR53H RSCAN0.RMPTR53.UINT16[H]
+#define RSCAN0RMPTR53HL RSCAN0.RMPTR53.UINT8[HL]
+#define RSCAN0RMPTR53HH RSCAN0.RMPTR53.UINT8[HH]
+#define RSCAN0RMDF053 RSCAN0.RMDF053.UINT32
+#define RSCAN0RMDF053L RSCAN0.RMDF053.UINT16[L]
+#define RSCAN0RMDF053LL RSCAN0.RMDF053.UINT8[LL]
+#define RSCAN0RMDF053LH RSCAN0.RMDF053.UINT8[LH]
+#define RSCAN0RMDF053H RSCAN0.RMDF053.UINT16[H]
+#define RSCAN0RMDF053HL RSCAN0.RMDF053.UINT8[HL]
+#define RSCAN0RMDF053HH RSCAN0.RMDF053.UINT8[HH]
+#define RSCAN0RMDF153 RSCAN0.RMDF153.UINT32
+#define RSCAN0RMDF153L RSCAN0.RMDF153.UINT16[L]
+#define RSCAN0RMDF153LL RSCAN0.RMDF153.UINT8[LL]
+#define RSCAN0RMDF153LH RSCAN0.RMDF153.UINT8[LH]
+#define RSCAN0RMDF153H RSCAN0.RMDF153.UINT16[H]
+#define RSCAN0RMDF153HL RSCAN0.RMDF153.UINT8[HL]
+#define RSCAN0RMDF153HH RSCAN0.RMDF153.UINT8[HH]
+#define RSCAN0RMID54 RSCAN0.RMID54.UINT32
+#define RSCAN0RMID54L RSCAN0.RMID54.UINT16[L]
+#define RSCAN0RMID54LL RSCAN0.RMID54.UINT8[LL]
+#define RSCAN0RMID54LH RSCAN0.RMID54.UINT8[LH]
+#define RSCAN0RMID54H RSCAN0.RMID54.UINT16[H]
+#define RSCAN0RMID54HL RSCAN0.RMID54.UINT8[HL]
+#define RSCAN0RMID54HH RSCAN0.RMID54.UINT8[HH]
+#define RSCAN0RMPTR54 RSCAN0.RMPTR54.UINT32
+#define RSCAN0RMPTR54L RSCAN0.RMPTR54.UINT16[L]
+#define RSCAN0RMPTR54LL RSCAN0.RMPTR54.UINT8[LL]
+#define RSCAN0RMPTR54LH RSCAN0.RMPTR54.UINT8[LH]
+#define RSCAN0RMPTR54H RSCAN0.RMPTR54.UINT16[H]
+#define RSCAN0RMPTR54HL RSCAN0.RMPTR54.UINT8[HL]
+#define RSCAN0RMPTR54HH RSCAN0.RMPTR54.UINT8[HH]
+#define RSCAN0RMDF054 RSCAN0.RMDF054.UINT32
+#define RSCAN0RMDF054L RSCAN0.RMDF054.UINT16[L]
+#define RSCAN0RMDF054LL RSCAN0.RMDF054.UINT8[LL]
+#define RSCAN0RMDF054LH RSCAN0.RMDF054.UINT8[LH]
+#define RSCAN0RMDF054H RSCAN0.RMDF054.UINT16[H]
+#define RSCAN0RMDF054HL RSCAN0.RMDF054.UINT8[HL]
+#define RSCAN0RMDF054HH RSCAN0.RMDF054.UINT8[HH]
+#define RSCAN0RMDF154 RSCAN0.RMDF154.UINT32
+#define RSCAN0RMDF154L RSCAN0.RMDF154.UINT16[L]
+#define RSCAN0RMDF154LL RSCAN0.RMDF154.UINT8[LL]
+#define RSCAN0RMDF154LH RSCAN0.RMDF154.UINT8[LH]
+#define RSCAN0RMDF154H RSCAN0.RMDF154.UINT16[H]
+#define RSCAN0RMDF154HL RSCAN0.RMDF154.UINT8[HL]
+#define RSCAN0RMDF154HH RSCAN0.RMDF154.UINT8[HH]
+#define RSCAN0RMID55 RSCAN0.RMID55.UINT32
+#define RSCAN0RMID55L RSCAN0.RMID55.UINT16[L]
+#define RSCAN0RMID55LL RSCAN0.RMID55.UINT8[LL]
+#define RSCAN0RMID55LH RSCAN0.RMID55.UINT8[LH]
+#define RSCAN0RMID55H RSCAN0.RMID55.UINT16[H]
+#define RSCAN0RMID55HL RSCAN0.RMID55.UINT8[HL]
+#define RSCAN0RMID55HH RSCAN0.RMID55.UINT8[HH]
+#define RSCAN0RMPTR55 RSCAN0.RMPTR55.UINT32
+#define RSCAN0RMPTR55L RSCAN0.RMPTR55.UINT16[L]
+#define RSCAN0RMPTR55LL RSCAN0.RMPTR55.UINT8[LL]
+#define RSCAN0RMPTR55LH RSCAN0.RMPTR55.UINT8[LH]
+#define RSCAN0RMPTR55H RSCAN0.RMPTR55.UINT16[H]
+#define RSCAN0RMPTR55HL RSCAN0.RMPTR55.UINT8[HL]
+#define RSCAN0RMPTR55HH RSCAN0.RMPTR55.UINT8[HH]
+#define RSCAN0RMDF055 RSCAN0.RMDF055.UINT32
+#define RSCAN0RMDF055L RSCAN0.RMDF055.UINT16[L]
+#define RSCAN0RMDF055LL RSCAN0.RMDF055.UINT8[LL]
+#define RSCAN0RMDF055LH RSCAN0.RMDF055.UINT8[LH]
+#define RSCAN0RMDF055H RSCAN0.RMDF055.UINT16[H]
+#define RSCAN0RMDF055HL RSCAN0.RMDF055.UINT8[HL]
+#define RSCAN0RMDF055HH RSCAN0.RMDF055.UINT8[HH]
+#define RSCAN0RMDF155 RSCAN0.RMDF155.UINT32
+#define RSCAN0RMDF155L RSCAN0.RMDF155.UINT16[L]
+#define RSCAN0RMDF155LL RSCAN0.RMDF155.UINT8[LL]
+#define RSCAN0RMDF155LH RSCAN0.RMDF155.UINT8[LH]
+#define RSCAN0RMDF155H RSCAN0.RMDF155.UINT16[H]
+#define RSCAN0RMDF155HL RSCAN0.RMDF155.UINT8[HL]
+#define RSCAN0RMDF155HH RSCAN0.RMDF155.UINT8[HH]
+#define RSCAN0RMID56 RSCAN0.RMID56.UINT32
+#define RSCAN0RMID56L RSCAN0.RMID56.UINT16[L]
+#define RSCAN0RMID56LL RSCAN0.RMID56.UINT8[LL]
+#define RSCAN0RMID56LH RSCAN0.RMID56.UINT8[LH]
+#define RSCAN0RMID56H RSCAN0.RMID56.UINT16[H]
+#define RSCAN0RMID56HL RSCAN0.RMID56.UINT8[HL]
+#define RSCAN0RMID56HH RSCAN0.RMID56.UINT8[HH]
+#define RSCAN0RMPTR56 RSCAN0.RMPTR56.UINT32
+#define RSCAN0RMPTR56L RSCAN0.RMPTR56.UINT16[L]
+#define RSCAN0RMPTR56LL RSCAN0.RMPTR56.UINT8[LL]
+#define RSCAN0RMPTR56LH RSCAN0.RMPTR56.UINT8[LH]
+#define RSCAN0RMPTR56H RSCAN0.RMPTR56.UINT16[H]
+#define RSCAN0RMPTR56HL RSCAN0.RMPTR56.UINT8[HL]
+#define RSCAN0RMPTR56HH RSCAN0.RMPTR56.UINT8[HH]
+#define RSCAN0RMDF056 RSCAN0.RMDF056.UINT32
+#define RSCAN0RMDF056L RSCAN0.RMDF056.UINT16[L]
+#define RSCAN0RMDF056LL RSCAN0.RMDF056.UINT8[LL]
+#define RSCAN0RMDF056LH RSCAN0.RMDF056.UINT8[LH]
+#define RSCAN0RMDF056H RSCAN0.RMDF056.UINT16[H]
+#define RSCAN0RMDF056HL RSCAN0.RMDF056.UINT8[HL]
+#define RSCAN0RMDF056HH RSCAN0.RMDF056.UINT8[HH]
+#define RSCAN0RMDF156 RSCAN0.RMDF156.UINT32
+#define RSCAN0RMDF156L RSCAN0.RMDF156.UINT16[L]
+#define RSCAN0RMDF156LL RSCAN0.RMDF156.UINT8[LL]
+#define RSCAN0RMDF156LH RSCAN0.RMDF156.UINT8[LH]
+#define RSCAN0RMDF156H RSCAN0.RMDF156.UINT16[H]
+#define RSCAN0RMDF156HL RSCAN0.RMDF156.UINT8[HL]
+#define RSCAN0RMDF156HH RSCAN0.RMDF156.UINT8[HH]
+#define RSCAN0RMID57 RSCAN0.RMID57.UINT32
+#define RSCAN0RMID57L RSCAN0.RMID57.UINT16[L]
+#define RSCAN0RMID57LL RSCAN0.RMID57.UINT8[LL]
+#define RSCAN0RMID57LH RSCAN0.RMID57.UINT8[LH]
+#define RSCAN0RMID57H RSCAN0.RMID57.UINT16[H]
+#define RSCAN0RMID57HL RSCAN0.RMID57.UINT8[HL]
+#define RSCAN0RMID57HH RSCAN0.RMID57.UINT8[HH]
+#define RSCAN0RMPTR57 RSCAN0.RMPTR57.UINT32
+#define RSCAN0RMPTR57L RSCAN0.RMPTR57.UINT16[L]
+#define RSCAN0RMPTR57LL RSCAN0.RMPTR57.UINT8[LL]
+#define RSCAN0RMPTR57LH RSCAN0.RMPTR57.UINT8[LH]
+#define RSCAN0RMPTR57H RSCAN0.RMPTR57.UINT16[H]
+#define RSCAN0RMPTR57HL RSCAN0.RMPTR57.UINT8[HL]
+#define RSCAN0RMPTR57HH RSCAN0.RMPTR57.UINT8[HH]
+#define RSCAN0RMDF057 RSCAN0.RMDF057.UINT32
+#define RSCAN0RMDF057L RSCAN0.RMDF057.UINT16[L]
+#define RSCAN0RMDF057LL RSCAN0.RMDF057.UINT8[LL]
+#define RSCAN0RMDF057LH RSCAN0.RMDF057.UINT8[LH]
+#define RSCAN0RMDF057H RSCAN0.RMDF057.UINT16[H]
+#define RSCAN0RMDF057HL RSCAN0.RMDF057.UINT8[HL]
+#define RSCAN0RMDF057HH RSCAN0.RMDF057.UINT8[HH]
+#define RSCAN0RMDF157 RSCAN0.RMDF157.UINT32
+#define RSCAN0RMDF157L RSCAN0.RMDF157.UINT16[L]
+#define RSCAN0RMDF157LL RSCAN0.RMDF157.UINT8[LL]
+#define RSCAN0RMDF157LH RSCAN0.RMDF157.UINT8[LH]
+#define RSCAN0RMDF157H RSCAN0.RMDF157.UINT16[H]
+#define RSCAN0RMDF157HL RSCAN0.RMDF157.UINT8[HL]
+#define RSCAN0RMDF157HH RSCAN0.RMDF157.UINT8[HH]
+#define RSCAN0RMID58 RSCAN0.RMID58.UINT32
+#define RSCAN0RMID58L RSCAN0.RMID58.UINT16[L]
+#define RSCAN0RMID58LL RSCAN0.RMID58.UINT8[LL]
+#define RSCAN0RMID58LH RSCAN0.RMID58.UINT8[LH]
+#define RSCAN0RMID58H RSCAN0.RMID58.UINT16[H]
+#define RSCAN0RMID58HL RSCAN0.RMID58.UINT8[HL]
+#define RSCAN0RMID58HH RSCAN0.RMID58.UINT8[HH]
+#define RSCAN0RMPTR58 RSCAN0.RMPTR58.UINT32
+#define RSCAN0RMPTR58L RSCAN0.RMPTR58.UINT16[L]
+#define RSCAN0RMPTR58LL RSCAN0.RMPTR58.UINT8[LL]
+#define RSCAN0RMPTR58LH RSCAN0.RMPTR58.UINT8[LH]
+#define RSCAN0RMPTR58H RSCAN0.RMPTR58.UINT16[H]
+#define RSCAN0RMPTR58HL RSCAN0.RMPTR58.UINT8[HL]
+#define RSCAN0RMPTR58HH RSCAN0.RMPTR58.UINT8[HH]
+#define RSCAN0RMDF058 RSCAN0.RMDF058.UINT32
+#define RSCAN0RMDF058L RSCAN0.RMDF058.UINT16[L]
+#define RSCAN0RMDF058LL RSCAN0.RMDF058.UINT8[LL]
+#define RSCAN0RMDF058LH RSCAN0.RMDF058.UINT8[LH]
+#define RSCAN0RMDF058H RSCAN0.RMDF058.UINT16[H]
+#define RSCAN0RMDF058HL RSCAN0.RMDF058.UINT8[HL]
+#define RSCAN0RMDF058HH RSCAN0.RMDF058.UINT8[HH]
+#define RSCAN0RMDF158 RSCAN0.RMDF158.UINT32
+#define RSCAN0RMDF158L RSCAN0.RMDF158.UINT16[L]
+#define RSCAN0RMDF158LL RSCAN0.RMDF158.UINT8[LL]
+#define RSCAN0RMDF158LH RSCAN0.RMDF158.UINT8[LH]
+#define RSCAN0RMDF158H RSCAN0.RMDF158.UINT16[H]
+#define RSCAN0RMDF158HL RSCAN0.RMDF158.UINT8[HL]
+#define RSCAN0RMDF158HH RSCAN0.RMDF158.UINT8[HH]
+#define RSCAN0RMID59 RSCAN0.RMID59.UINT32
+#define RSCAN0RMID59L RSCAN0.RMID59.UINT16[L]
+#define RSCAN0RMID59LL RSCAN0.RMID59.UINT8[LL]
+#define RSCAN0RMID59LH RSCAN0.RMID59.UINT8[LH]
+#define RSCAN0RMID59H RSCAN0.RMID59.UINT16[H]
+#define RSCAN0RMID59HL RSCAN0.RMID59.UINT8[HL]
+#define RSCAN0RMID59HH RSCAN0.RMID59.UINT8[HH]
+#define RSCAN0RMPTR59 RSCAN0.RMPTR59.UINT32
+#define RSCAN0RMPTR59L RSCAN0.RMPTR59.UINT16[L]
+#define RSCAN0RMPTR59LL RSCAN0.RMPTR59.UINT8[LL]
+#define RSCAN0RMPTR59LH RSCAN0.RMPTR59.UINT8[LH]
+#define RSCAN0RMPTR59H RSCAN0.RMPTR59.UINT16[H]
+#define RSCAN0RMPTR59HL RSCAN0.RMPTR59.UINT8[HL]
+#define RSCAN0RMPTR59HH RSCAN0.RMPTR59.UINT8[HH]
+#define RSCAN0RMDF059 RSCAN0.RMDF059.UINT32
+#define RSCAN0RMDF059L RSCAN0.RMDF059.UINT16[L]
+#define RSCAN0RMDF059LL RSCAN0.RMDF059.UINT8[LL]
+#define RSCAN0RMDF059LH RSCAN0.RMDF059.UINT8[LH]
+#define RSCAN0RMDF059H RSCAN0.RMDF059.UINT16[H]
+#define RSCAN0RMDF059HL RSCAN0.RMDF059.UINT8[HL]
+#define RSCAN0RMDF059HH RSCAN0.RMDF059.UINT8[HH]
+#define RSCAN0RMDF159 RSCAN0.RMDF159.UINT32
+#define RSCAN0RMDF159L RSCAN0.RMDF159.UINT16[L]
+#define RSCAN0RMDF159LL RSCAN0.RMDF159.UINT8[LL]
+#define RSCAN0RMDF159LH RSCAN0.RMDF159.UINT8[LH]
+#define RSCAN0RMDF159H RSCAN0.RMDF159.UINT16[H]
+#define RSCAN0RMDF159HL RSCAN0.RMDF159.UINT8[HL]
+#define RSCAN0RMDF159HH RSCAN0.RMDF159.UINT8[HH]
+#define RSCAN0RMID60 RSCAN0.RMID60.UINT32
+#define RSCAN0RMID60L RSCAN0.RMID60.UINT16[L]
+#define RSCAN0RMID60LL RSCAN0.RMID60.UINT8[LL]
+#define RSCAN0RMID60LH RSCAN0.RMID60.UINT8[LH]
+#define RSCAN0RMID60H RSCAN0.RMID60.UINT16[H]
+#define RSCAN0RMID60HL RSCAN0.RMID60.UINT8[HL]
+#define RSCAN0RMID60HH RSCAN0.RMID60.UINT8[HH]
+#define RSCAN0RMPTR60 RSCAN0.RMPTR60.UINT32
+#define RSCAN0RMPTR60L RSCAN0.RMPTR60.UINT16[L]
+#define RSCAN0RMPTR60LL RSCAN0.RMPTR60.UINT8[LL]
+#define RSCAN0RMPTR60LH RSCAN0.RMPTR60.UINT8[LH]
+#define RSCAN0RMPTR60H RSCAN0.RMPTR60.UINT16[H]
+#define RSCAN0RMPTR60HL RSCAN0.RMPTR60.UINT8[HL]
+#define RSCAN0RMPTR60HH RSCAN0.RMPTR60.UINT8[HH]
+#define RSCAN0RMDF060 RSCAN0.RMDF060.UINT32
+#define RSCAN0RMDF060L RSCAN0.RMDF060.UINT16[L]
+#define RSCAN0RMDF060LL RSCAN0.RMDF060.UINT8[LL]
+#define RSCAN0RMDF060LH RSCAN0.RMDF060.UINT8[LH]
+#define RSCAN0RMDF060H RSCAN0.RMDF060.UINT16[H]
+#define RSCAN0RMDF060HL RSCAN0.RMDF060.UINT8[HL]
+#define RSCAN0RMDF060HH RSCAN0.RMDF060.UINT8[HH]
+#define RSCAN0RMDF160 RSCAN0.RMDF160.UINT32
+#define RSCAN0RMDF160L RSCAN0.RMDF160.UINT16[L]
+#define RSCAN0RMDF160LL RSCAN0.RMDF160.UINT8[LL]
+#define RSCAN0RMDF160LH RSCAN0.RMDF160.UINT8[LH]
+#define RSCAN0RMDF160H RSCAN0.RMDF160.UINT16[H]
+#define RSCAN0RMDF160HL RSCAN0.RMDF160.UINT8[HL]
+#define RSCAN0RMDF160HH RSCAN0.RMDF160.UINT8[HH]
+#define RSCAN0RMID61 RSCAN0.RMID61.UINT32
+#define RSCAN0RMID61L RSCAN0.RMID61.UINT16[L]
+#define RSCAN0RMID61LL RSCAN0.RMID61.UINT8[LL]
+#define RSCAN0RMID61LH RSCAN0.RMID61.UINT8[LH]
+#define RSCAN0RMID61H RSCAN0.RMID61.UINT16[H]
+#define RSCAN0RMID61HL RSCAN0.RMID61.UINT8[HL]
+#define RSCAN0RMID61HH RSCAN0.RMID61.UINT8[HH]
+#define RSCAN0RMPTR61 RSCAN0.RMPTR61.UINT32
+#define RSCAN0RMPTR61L RSCAN0.RMPTR61.UINT16[L]
+#define RSCAN0RMPTR61LL RSCAN0.RMPTR61.UINT8[LL]
+#define RSCAN0RMPTR61LH RSCAN0.RMPTR61.UINT8[LH]
+#define RSCAN0RMPTR61H RSCAN0.RMPTR61.UINT16[H]
+#define RSCAN0RMPTR61HL RSCAN0.RMPTR61.UINT8[HL]
+#define RSCAN0RMPTR61HH RSCAN0.RMPTR61.UINT8[HH]
+#define RSCAN0RMDF061 RSCAN0.RMDF061.UINT32
+#define RSCAN0RMDF061L RSCAN0.RMDF061.UINT16[L]
+#define RSCAN0RMDF061LL RSCAN0.RMDF061.UINT8[LL]
+#define RSCAN0RMDF061LH RSCAN0.RMDF061.UINT8[LH]
+#define RSCAN0RMDF061H RSCAN0.RMDF061.UINT16[H]
+#define RSCAN0RMDF061HL RSCAN0.RMDF061.UINT8[HL]
+#define RSCAN0RMDF061HH RSCAN0.RMDF061.UINT8[HH]
+#define RSCAN0RMDF161 RSCAN0.RMDF161.UINT32
+#define RSCAN0RMDF161L RSCAN0.RMDF161.UINT16[L]
+#define RSCAN0RMDF161LL RSCAN0.RMDF161.UINT8[LL]
+#define RSCAN0RMDF161LH RSCAN0.RMDF161.UINT8[LH]
+#define RSCAN0RMDF161H RSCAN0.RMDF161.UINT16[H]
+#define RSCAN0RMDF161HL RSCAN0.RMDF161.UINT8[HL]
+#define RSCAN0RMDF161HH RSCAN0.RMDF161.UINT8[HH]
+#define RSCAN0RMID62 RSCAN0.RMID62.UINT32
+#define RSCAN0RMID62L RSCAN0.RMID62.UINT16[L]
+#define RSCAN0RMID62LL RSCAN0.RMID62.UINT8[LL]
+#define RSCAN0RMID62LH RSCAN0.RMID62.UINT8[LH]
+#define RSCAN0RMID62H RSCAN0.RMID62.UINT16[H]
+#define RSCAN0RMID62HL RSCAN0.RMID62.UINT8[HL]
+#define RSCAN0RMID62HH RSCAN0.RMID62.UINT8[HH]
+#define RSCAN0RMPTR62 RSCAN0.RMPTR62.UINT32
+#define RSCAN0RMPTR62L RSCAN0.RMPTR62.UINT16[L]
+#define RSCAN0RMPTR62LL RSCAN0.RMPTR62.UINT8[LL]
+#define RSCAN0RMPTR62LH RSCAN0.RMPTR62.UINT8[LH]
+#define RSCAN0RMPTR62H RSCAN0.RMPTR62.UINT16[H]
+#define RSCAN0RMPTR62HL RSCAN0.RMPTR62.UINT8[HL]
+#define RSCAN0RMPTR62HH RSCAN0.RMPTR62.UINT8[HH]
+#define RSCAN0RMDF062 RSCAN0.RMDF062.UINT32
+#define RSCAN0RMDF062L RSCAN0.RMDF062.UINT16[L]
+#define RSCAN0RMDF062LL RSCAN0.RMDF062.UINT8[LL]
+#define RSCAN0RMDF062LH RSCAN0.RMDF062.UINT8[LH]
+#define RSCAN0RMDF062H RSCAN0.RMDF062.UINT16[H]
+#define RSCAN0RMDF062HL RSCAN0.RMDF062.UINT8[HL]
+#define RSCAN0RMDF062HH RSCAN0.RMDF062.UINT8[HH]
+#define RSCAN0RMDF162 RSCAN0.RMDF162.UINT32
+#define RSCAN0RMDF162L RSCAN0.RMDF162.UINT16[L]
+#define RSCAN0RMDF162LL RSCAN0.RMDF162.UINT8[LL]
+#define RSCAN0RMDF162LH RSCAN0.RMDF162.UINT8[LH]
+#define RSCAN0RMDF162H RSCAN0.RMDF162.UINT16[H]
+#define RSCAN0RMDF162HL RSCAN0.RMDF162.UINT8[HL]
+#define RSCAN0RMDF162HH RSCAN0.RMDF162.UINT8[HH]
+#define RSCAN0RMID63 RSCAN0.RMID63.UINT32
+#define RSCAN0RMID63L RSCAN0.RMID63.UINT16[L]
+#define RSCAN0RMID63LL RSCAN0.RMID63.UINT8[LL]
+#define RSCAN0RMID63LH RSCAN0.RMID63.UINT8[LH]
+#define RSCAN0RMID63H RSCAN0.RMID63.UINT16[H]
+#define RSCAN0RMID63HL RSCAN0.RMID63.UINT8[HL]
+#define RSCAN0RMID63HH RSCAN0.RMID63.UINT8[HH]
+#define RSCAN0RMPTR63 RSCAN0.RMPTR63.UINT32
+#define RSCAN0RMPTR63L RSCAN0.RMPTR63.UINT16[L]
+#define RSCAN0RMPTR63LL RSCAN0.RMPTR63.UINT8[LL]
+#define RSCAN0RMPTR63LH RSCAN0.RMPTR63.UINT8[LH]
+#define RSCAN0RMPTR63H RSCAN0.RMPTR63.UINT16[H]
+#define RSCAN0RMPTR63HL RSCAN0.RMPTR63.UINT8[HL]
+#define RSCAN0RMPTR63HH RSCAN0.RMPTR63.UINT8[HH]
+#define RSCAN0RMDF063 RSCAN0.RMDF063.UINT32
+#define RSCAN0RMDF063L RSCAN0.RMDF063.UINT16[L]
+#define RSCAN0RMDF063LL RSCAN0.RMDF063.UINT8[LL]
+#define RSCAN0RMDF063LH RSCAN0.RMDF063.UINT8[LH]
+#define RSCAN0RMDF063H RSCAN0.RMDF063.UINT16[H]
+#define RSCAN0RMDF063HL RSCAN0.RMDF063.UINT8[HL]
+#define RSCAN0RMDF063HH RSCAN0.RMDF063.UINT8[HH]
+#define RSCAN0RMDF163 RSCAN0.RMDF163.UINT32
+#define RSCAN0RMDF163L RSCAN0.RMDF163.UINT16[L]
+#define RSCAN0RMDF163LL RSCAN0.RMDF163.UINT8[LL]
+#define RSCAN0RMDF163LH RSCAN0.RMDF163.UINT8[LH]
+#define RSCAN0RMDF163H RSCAN0.RMDF163.UINT16[H]
+#define RSCAN0RMDF163HL RSCAN0.RMDF163.UINT8[HL]
+#define RSCAN0RMDF163HH RSCAN0.RMDF163.UINT8[HH]
+#define RSCAN0RMID64 RSCAN0.RMID64.UINT32
+#define RSCAN0RMID64L RSCAN0.RMID64.UINT16[L]
+#define RSCAN0RMID64LL RSCAN0.RMID64.UINT8[LL]
+#define RSCAN0RMID64LH RSCAN0.RMID64.UINT8[LH]
+#define RSCAN0RMID64H RSCAN0.RMID64.UINT16[H]
+#define RSCAN0RMID64HL RSCAN0.RMID64.UINT8[HL]
+#define RSCAN0RMID64HH RSCAN0.RMID64.UINT8[HH]
+#define RSCAN0RMPTR64 RSCAN0.RMPTR64.UINT32
+#define RSCAN0RMPTR64L RSCAN0.RMPTR64.UINT16[L]
+#define RSCAN0RMPTR64LL RSCAN0.RMPTR64.UINT8[LL]
+#define RSCAN0RMPTR64LH RSCAN0.RMPTR64.UINT8[LH]
+#define RSCAN0RMPTR64H RSCAN0.RMPTR64.UINT16[H]
+#define RSCAN0RMPTR64HL RSCAN0.RMPTR64.UINT8[HL]
+#define RSCAN0RMPTR64HH RSCAN0.RMPTR64.UINT8[HH]
+#define RSCAN0RMDF064 RSCAN0.RMDF064.UINT32
+#define RSCAN0RMDF064L RSCAN0.RMDF064.UINT16[L]
+#define RSCAN0RMDF064LL RSCAN0.RMDF064.UINT8[LL]
+#define RSCAN0RMDF064LH RSCAN0.RMDF064.UINT8[LH]
+#define RSCAN0RMDF064H RSCAN0.RMDF064.UINT16[H]
+#define RSCAN0RMDF064HL RSCAN0.RMDF064.UINT8[HL]
+#define RSCAN0RMDF064HH RSCAN0.RMDF064.UINT8[HH]
+#define RSCAN0RMDF164 RSCAN0.RMDF164.UINT32
+#define RSCAN0RMDF164L RSCAN0.RMDF164.UINT16[L]
+#define RSCAN0RMDF164LL RSCAN0.RMDF164.UINT8[LL]
+#define RSCAN0RMDF164LH RSCAN0.RMDF164.UINT8[LH]
+#define RSCAN0RMDF164H RSCAN0.RMDF164.UINT16[H]
+#define RSCAN0RMDF164HL RSCAN0.RMDF164.UINT8[HL]
+#define RSCAN0RMDF164HH RSCAN0.RMDF164.UINT8[HH]
+#define RSCAN0RMID65 RSCAN0.RMID65.UINT32
+#define RSCAN0RMID65L RSCAN0.RMID65.UINT16[L]
+#define RSCAN0RMID65LL RSCAN0.RMID65.UINT8[LL]
+#define RSCAN0RMID65LH RSCAN0.RMID65.UINT8[LH]
+#define RSCAN0RMID65H RSCAN0.RMID65.UINT16[H]
+#define RSCAN0RMID65HL RSCAN0.RMID65.UINT8[HL]
+#define RSCAN0RMID65HH RSCAN0.RMID65.UINT8[HH]
+#define RSCAN0RMPTR65 RSCAN0.RMPTR65.UINT32
+#define RSCAN0RMPTR65L RSCAN0.RMPTR65.UINT16[L]
+#define RSCAN0RMPTR65LL RSCAN0.RMPTR65.UINT8[LL]
+#define RSCAN0RMPTR65LH RSCAN0.RMPTR65.UINT8[LH]
+#define RSCAN0RMPTR65H RSCAN0.RMPTR65.UINT16[H]
+#define RSCAN0RMPTR65HL RSCAN0.RMPTR65.UINT8[HL]
+#define RSCAN0RMPTR65HH RSCAN0.RMPTR65.UINT8[HH]
+#define RSCAN0RMDF065 RSCAN0.RMDF065.UINT32
+#define RSCAN0RMDF065L RSCAN0.RMDF065.UINT16[L]
+#define RSCAN0RMDF065LL RSCAN0.RMDF065.UINT8[LL]
+#define RSCAN0RMDF065LH RSCAN0.RMDF065.UINT8[LH]
+#define RSCAN0RMDF065H RSCAN0.RMDF065.UINT16[H]
+#define RSCAN0RMDF065HL RSCAN0.RMDF065.UINT8[HL]
+#define RSCAN0RMDF065HH RSCAN0.RMDF065.UINT8[HH]
+#define RSCAN0RMDF165 RSCAN0.RMDF165.UINT32
+#define RSCAN0RMDF165L RSCAN0.RMDF165.UINT16[L]
+#define RSCAN0RMDF165LL RSCAN0.RMDF165.UINT8[LL]
+#define RSCAN0RMDF165LH RSCAN0.RMDF165.UINT8[LH]
+#define RSCAN0RMDF165H RSCAN0.RMDF165.UINT16[H]
+#define RSCAN0RMDF165HL RSCAN0.RMDF165.UINT8[HL]
+#define RSCAN0RMDF165HH RSCAN0.RMDF165.UINT8[HH]
+#define RSCAN0RMID66 RSCAN0.RMID66.UINT32
+#define RSCAN0RMID66L RSCAN0.RMID66.UINT16[L]
+#define RSCAN0RMID66LL RSCAN0.RMID66.UINT8[LL]
+#define RSCAN0RMID66LH RSCAN0.RMID66.UINT8[LH]
+#define RSCAN0RMID66H RSCAN0.RMID66.UINT16[H]
+#define RSCAN0RMID66HL RSCAN0.RMID66.UINT8[HL]
+#define RSCAN0RMID66HH RSCAN0.RMID66.UINT8[HH]
+#define RSCAN0RMPTR66 RSCAN0.RMPTR66.UINT32
+#define RSCAN0RMPTR66L RSCAN0.RMPTR66.UINT16[L]
+#define RSCAN0RMPTR66LL RSCAN0.RMPTR66.UINT8[LL]
+#define RSCAN0RMPTR66LH RSCAN0.RMPTR66.UINT8[LH]
+#define RSCAN0RMPTR66H RSCAN0.RMPTR66.UINT16[H]
+#define RSCAN0RMPTR66HL RSCAN0.RMPTR66.UINT8[HL]
+#define RSCAN0RMPTR66HH RSCAN0.RMPTR66.UINT8[HH]
+#define RSCAN0RMDF066 RSCAN0.RMDF066.UINT32
+#define RSCAN0RMDF066L RSCAN0.RMDF066.UINT16[L]
+#define RSCAN0RMDF066LL RSCAN0.RMDF066.UINT8[LL]
+#define RSCAN0RMDF066LH RSCAN0.RMDF066.UINT8[LH]
+#define RSCAN0RMDF066H RSCAN0.RMDF066.UINT16[H]
+#define RSCAN0RMDF066HL RSCAN0.RMDF066.UINT8[HL]
+#define RSCAN0RMDF066HH RSCAN0.RMDF066.UINT8[HH]
+#define RSCAN0RMDF166 RSCAN0.RMDF166.UINT32
+#define RSCAN0RMDF166L RSCAN0.RMDF166.UINT16[L]
+#define RSCAN0RMDF166LL RSCAN0.RMDF166.UINT8[LL]
+#define RSCAN0RMDF166LH RSCAN0.RMDF166.UINT8[LH]
+#define RSCAN0RMDF166H RSCAN0.RMDF166.UINT16[H]
+#define RSCAN0RMDF166HL RSCAN0.RMDF166.UINT8[HL]
+#define RSCAN0RMDF166HH RSCAN0.RMDF166.UINT8[HH]
+#define RSCAN0RMID67 RSCAN0.RMID67.UINT32
+#define RSCAN0RMID67L RSCAN0.RMID67.UINT16[L]
+#define RSCAN0RMID67LL RSCAN0.RMID67.UINT8[LL]
+#define RSCAN0RMID67LH RSCAN0.RMID67.UINT8[LH]
+#define RSCAN0RMID67H RSCAN0.RMID67.UINT16[H]
+#define RSCAN0RMID67HL RSCAN0.RMID67.UINT8[HL]
+#define RSCAN0RMID67HH RSCAN0.RMID67.UINT8[HH]
+#define RSCAN0RMPTR67 RSCAN0.RMPTR67.UINT32
+#define RSCAN0RMPTR67L RSCAN0.RMPTR67.UINT16[L]
+#define RSCAN0RMPTR67LL RSCAN0.RMPTR67.UINT8[LL]
+#define RSCAN0RMPTR67LH RSCAN0.RMPTR67.UINT8[LH]
+#define RSCAN0RMPTR67H RSCAN0.RMPTR67.UINT16[H]
+#define RSCAN0RMPTR67HL RSCAN0.RMPTR67.UINT8[HL]
+#define RSCAN0RMPTR67HH RSCAN0.RMPTR67.UINT8[HH]
+#define RSCAN0RMDF067 RSCAN0.RMDF067.UINT32
+#define RSCAN0RMDF067L RSCAN0.RMDF067.UINT16[L]
+#define RSCAN0RMDF067LL RSCAN0.RMDF067.UINT8[LL]
+#define RSCAN0RMDF067LH RSCAN0.RMDF067.UINT8[LH]
+#define RSCAN0RMDF067H RSCAN0.RMDF067.UINT16[H]
+#define RSCAN0RMDF067HL RSCAN0.RMDF067.UINT8[HL]
+#define RSCAN0RMDF067HH RSCAN0.RMDF067.UINT8[HH]
+#define RSCAN0RMDF167 RSCAN0.RMDF167.UINT32
+#define RSCAN0RMDF167L RSCAN0.RMDF167.UINT16[L]
+#define RSCAN0RMDF167LL RSCAN0.RMDF167.UINT8[LL]
+#define RSCAN0RMDF167LH RSCAN0.RMDF167.UINT8[LH]
+#define RSCAN0RMDF167H RSCAN0.RMDF167.UINT16[H]
+#define RSCAN0RMDF167HL RSCAN0.RMDF167.UINT8[HL]
+#define RSCAN0RMDF167HH RSCAN0.RMDF167.UINT8[HH]
+#define RSCAN0RMID68 RSCAN0.RMID68.UINT32
+#define RSCAN0RMID68L RSCAN0.RMID68.UINT16[L]
+#define RSCAN0RMID68LL RSCAN0.RMID68.UINT8[LL]
+#define RSCAN0RMID68LH RSCAN0.RMID68.UINT8[LH]
+#define RSCAN0RMID68H RSCAN0.RMID68.UINT16[H]
+#define RSCAN0RMID68HL RSCAN0.RMID68.UINT8[HL]
+#define RSCAN0RMID68HH RSCAN0.RMID68.UINT8[HH]
+#define RSCAN0RMPTR68 RSCAN0.RMPTR68.UINT32
+#define RSCAN0RMPTR68L RSCAN0.RMPTR68.UINT16[L]
+#define RSCAN0RMPTR68LL RSCAN0.RMPTR68.UINT8[LL]
+#define RSCAN0RMPTR68LH RSCAN0.RMPTR68.UINT8[LH]
+#define RSCAN0RMPTR68H RSCAN0.RMPTR68.UINT16[H]
+#define RSCAN0RMPTR68HL RSCAN0.RMPTR68.UINT8[HL]
+#define RSCAN0RMPTR68HH RSCAN0.RMPTR68.UINT8[HH]
+#define RSCAN0RMDF068 RSCAN0.RMDF068.UINT32
+#define RSCAN0RMDF068L RSCAN0.RMDF068.UINT16[L]
+#define RSCAN0RMDF068LL RSCAN0.RMDF068.UINT8[LL]
+#define RSCAN0RMDF068LH RSCAN0.RMDF068.UINT8[LH]
+#define RSCAN0RMDF068H RSCAN0.RMDF068.UINT16[H]
+#define RSCAN0RMDF068HL RSCAN0.RMDF068.UINT8[HL]
+#define RSCAN0RMDF068HH RSCAN0.RMDF068.UINT8[HH]
+#define RSCAN0RMDF168 RSCAN0.RMDF168.UINT32
+#define RSCAN0RMDF168L RSCAN0.RMDF168.UINT16[L]
+#define RSCAN0RMDF168LL RSCAN0.RMDF168.UINT8[LL]
+#define RSCAN0RMDF168LH RSCAN0.RMDF168.UINT8[LH]
+#define RSCAN0RMDF168H RSCAN0.RMDF168.UINT16[H]
+#define RSCAN0RMDF168HL RSCAN0.RMDF168.UINT8[HL]
+#define RSCAN0RMDF168HH RSCAN0.RMDF168.UINT8[HH]
+#define RSCAN0RMID69 RSCAN0.RMID69.UINT32
+#define RSCAN0RMID69L RSCAN0.RMID69.UINT16[L]
+#define RSCAN0RMID69LL RSCAN0.RMID69.UINT8[LL]
+#define RSCAN0RMID69LH RSCAN0.RMID69.UINT8[LH]
+#define RSCAN0RMID69H RSCAN0.RMID69.UINT16[H]
+#define RSCAN0RMID69HL RSCAN0.RMID69.UINT8[HL]
+#define RSCAN0RMID69HH RSCAN0.RMID69.UINT8[HH]
+#define RSCAN0RMPTR69 RSCAN0.RMPTR69.UINT32
+#define RSCAN0RMPTR69L RSCAN0.RMPTR69.UINT16[L]
+#define RSCAN0RMPTR69LL RSCAN0.RMPTR69.UINT8[LL]
+#define RSCAN0RMPTR69LH RSCAN0.RMPTR69.UINT8[LH]
+#define RSCAN0RMPTR69H RSCAN0.RMPTR69.UINT16[H]
+#define RSCAN0RMPTR69HL RSCAN0.RMPTR69.UINT8[HL]
+#define RSCAN0RMPTR69HH RSCAN0.RMPTR69.UINT8[HH]
+#define RSCAN0RMDF069 RSCAN0.RMDF069.UINT32
+#define RSCAN0RMDF069L RSCAN0.RMDF069.UINT16[L]
+#define RSCAN0RMDF069LL RSCAN0.RMDF069.UINT8[LL]
+#define RSCAN0RMDF069LH RSCAN0.RMDF069.UINT8[LH]
+#define RSCAN0RMDF069H RSCAN0.RMDF069.UINT16[H]
+#define RSCAN0RMDF069HL RSCAN0.RMDF069.UINT8[HL]
+#define RSCAN0RMDF069HH RSCAN0.RMDF069.UINT8[HH]
+#define RSCAN0RMDF169 RSCAN0.RMDF169.UINT32
+#define RSCAN0RMDF169L RSCAN0.RMDF169.UINT16[L]
+#define RSCAN0RMDF169LL RSCAN0.RMDF169.UINT8[LL]
+#define RSCAN0RMDF169LH RSCAN0.RMDF169.UINT8[LH]
+#define RSCAN0RMDF169H RSCAN0.RMDF169.UINT16[H]
+#define RSCAN0RMDF169HL RSCAN0.RMDF169.UINT8[HL]
+#define RSCAN0RMDF169HH RSCAN0.RMDF169.UINT8[HH]
+#define RSCAN0RMID70 RSCAN0.RMID70.UINT32
+#define RSCAN0RMID70L RSCAN0.RMID70.UINT16[L]
+#define RSCAN0RMID70LL RSCAN0.RMID70.UINT8[LL]
+#define RSCAN0RMID70LH RSCAN0.RMID70.UINT8[LH]
+#define RSCAN0RMID70H RSCAN0.RMID70.UINT16[H]
+#define RSCAN0RMID70HL RSCAN0.RMID70.UINT8[HL]
+#define RSCAN0RMID70HH RSCAN0.RMID70.UINT8[HH]
+#define RSCAN0RMPTR70 RSCAN0.RMPTR70.UINT32
+#define RSCAN0RMPTR70L RSCAN0.RMPTR70.UINT16[L]
+#define RSCAN0RMPTR70LL RSCAN0.RMPTR70.UINT8[LL]
+#define RSCAN0RMPTR70LH RSCAN0.RMPTR70.UINT8[LH]
+#define RSCAN0RMPTR70H RSCAN0.RMPTR70.UINT16[H]
+#define RSCAN0RMPTR70HL RSCAN0.RMPTR70.UINT8[HL]
+#define RSCAN0RMPTR70HH RSCAN0.RMPTR70.UINT8[HH]
+#define RSCAN0RMDF070 RSCAN0.RMDF070.UINT32
+#define RSCAN0RMDF070L RSCAN0.RMDF070.UINT16[L]
+#define RSCAN0RMDF070LL RSCAN0.RMDF070.UINT8[LL]
+#define RSCAN0RMDF070LH RSCAN0.RMDF070.UINT8[LH]
+#define RSCAN0RMDF070H RSCAN0.RMDF070.UINT16[H]
+#define RSCAN0RMDF070HL RSCAN0.RMDF070.UINT8[HL]
+#define RSCAN0RMDF070HH RSCAN0.RMDF070.UINT8[HH]
+#define RSCAN0RMDF170 RSCAN0.RMDF170.UINT32
+#define RSCAN0RMDF170L RSCAN0.RMDF170.UINT16[L]
+#define RSCAN0RMDF170LL RSCAN0.RMDF170.UINT8[LL]
+#define RSCAN0RMDF170LH RSCAN0.RMDF170.UINT8[LH]
+#define RSCAN0RMDF170H RSCAN0.RMDF170.UINT16[H]
+#define RSCAN0RMDF170HL RSCAN0.RMDF170.UINT8[HL]
+#define RSCAN0RMDF170HH RSCAN0.RMDF170.UINT8[HH]
+#define RSCAN0RMID71 RSCAN0.RMID71.UINT32
+#define RSCAN0RMID71L RSCAN0.RMID71.UINT16[L]
+#define RSCAN0RMID71LL RSCAN0.RMID71.UINT8[LL]
+#define RSCAN0RMID71LH RSCAN0.RMID71.UINT8[LH]
+#define RSCAN0RMID71H RSCAN0.RMID71.UINT16[H]
+#define RSCAN0RMID71HL RSCAN0.RMID71.UINT8[HL]
+#define RSCAN0RMID71HH RSCAN0.RMID71.UINT8[HH]
+#define RSCAN0RMPTR71 RSCAN0.RMPTR71.UINT32
+#define RSCAN0RMPTR71L RSCAN0.RMPTR71.UINT16[L]
+#define RSCAN0RMPTR71LL RSCAN0.RMPTR71.UINT8[LL]
+#define RSCAN0RMPTR71LH RSCAN0.RMPTR71.UINT8[LH]
+#define RSCAN0RMPTR71H RSCAN0.RMPTR71.UINT16[H]
+#define RSCAN0RMPTR71HL RSCAN0.RMPTR71.UINT8[HL]
+#define RSCAN0RMPTR71HH RSCAN0.RMPTR71.UINT8[HH]
+#define RSCAN0RMDF071 RSCAN0.RMDF071.UINT32
+#define RSCAN0RMDF071L RSCAN0.RMDF071.UINT16[L]
+#define RSCAN0RMDF071LL RSCAN0.RMDF071.UINT8[LL]
+#define RSCAN0RMDF071LH RSCAN0.RMDF071.UINT8[LH]
+#define RSCAN0RMDF071H RSCAN0.RMDF071.UINT16[H]
+#define RSCAN0RMDF071HL RSCAN0.RMDF071.UINT8[HL]
+#define RSCAN0RMDF071HH RSCAN0.RMDF071.UINT8[HH]
+#define RSCAN0RMDF171 RSCAN0.RMDF171.UINT32
+#define RSCAN0RMDF171L RSCAN0.RMDF171.UINT16[L]
+#define RSCAN0RMDF171LL RSCAN0.RMDF171.UINT8[LL]
+#define RSCAN0RMDF171LH RSCAN0.RMDF171.UINT8[LH]
+#define RSCAN0RMDF171H RSCAN0.RMDF171.UINT16[H]
+#define RSCAN0RMDF171HL RSCAN0.RMDF171.UINT8[HL]
+#define RSCAN0RMDF171HH RSCAN0.RMDF171.UINT8[HH]
+#define RSCAN0RMID72 RSCAN0.RMID72.UINT32
+#define RSCAN0RMID72L RSCAN0.RMID72.UINT16[L]
+#define RSCAN0RMID72LL RSCAN0.RMID72.UINT8[LL]
+#define RSCAN0RMID72LH RSCAN0.RMID72.UINT8[LH]
+#define RSCAN0RMID72H RSCAN0.RMID72.UINT16[H]
+#define RSCAN0RMID72HL RSCAN0.RMID72.UINT8[HL]
+#define RSCAN0RMID72HH RSCAN0.RMID72.UINT8[HH]
+#define RSCAN0RMPTR72 RSCAN0.RMPTR72.UINT32
+#define RSCAN0RMPTR72L RSCAN0.RMPTR72.UINT16[L]
+#define RSCAN0RMPTR72LL RSCAN0.RMPTR72.UINT8[LL]
+#define RSCAN0RMPTR72LH RSCAN0.RMPTR72.UINT8[LH]
+#define RSCAN0RMPTR72H RSCAN0.RMPTR72.UINT16[H]
+#define RSCAN0RMPTR72HL RSCAN0.RMPTR72.UINT8[HL]
+#define RSCAN0RMPTR72HH RSCAN0.RMPTR72.UINT8[HH]
+#define RSCAN0RMDF072 RSCAN0.RMDF072.UINT32
+#define RSCAN0RMDF072L RSCAN0.RMDF072.UINT16[L]
+#define RSCAN0RMDF072LL RSCAN0.RMDF072.UINT8[LL]
+#define RSCAN0RMDF072LH RSCAN0.RMDF072.UINT8[LH]
+#define RSCAN0RMDF072H RSCAN0.RMDF072.UINT16[H]
+#define RSCAN0RMDF072HL RSCAN0.RMDF072.UINT8[HL]
+#define RSCAN0RMDF072HH RSCAN0.RMDF072.UINT8[HH]
+#define RSCAN0RMDF172 RSCAN0.RMDF172.UINT32
+#define RSCAN0RMDF172L RSCAN0.RMDF172.UINT16[L]
+#define RSCAN0RMDF172LL RSCAN0.RMDF172.UINT8[LL]
+#define RSCAN0RMDF172LH RSCAN0.RMDF172.UINT8[LH]
+#define RSCAN0RMDF172H RSCAN0.RMDF172.UINT16[H]
+#define RSCAN0RMDF172HL RSCAN0.RMDF172.UINT8[HL]
+#define RSCAN0RMDF172HH RSCAN0.RMDF172.UINT8[HH]
+#define RSCAN0RMID73 RSCAN0.RMID73.UINT32
+#define RSCAN0RMID73L RSCAN0.RMID73.UINT16[L]
+#define RSCAN0RMID73LL RSCAN0.RMID73.UINT8[LL]
+#define RSCAN0RMID73LH RSCAN0.RMID73.UINT8[LH]
+#define RSCAN0RMID73H RSCAN0.RMID73.UINT16[H]
+#define RSCAN0RMID73HL RSCAN0.RMID73.UINT8[HL]
+#define RSCAN0RMID73HH RSCAN0.RMID73.UINT8[HH]
+#define RSCAN0RMPTR73 RSCAN0.RMPTR73.UINT32
+#define RSCAN0RMPTR73L RSCAN0.RMPTR73.UINT16[L]
+#define RSCAN0RMPTR73LL RSCAN0.RMPTR73.UINT8[LL]
+#define RSCAN0RMPTR73LH RSCAN0.RMPTR73.UINT8[LH]
+#define RSCAN0RMPTR73H RSCAN0.RMPTR73.UINT16[H]
+#define RSCAN0RMPTR73HL RSCAN0.RMPTR73.UINT8[HL]
+#define RSCAN0RMPTR73HH RSCAN0.RMPTR73.UINT8[HH]
+#define RSCAN0RMDF073 RSCAN0.RMDF073.UINT32
+#define RSCAN0RMDF073L RSCAN0.RMDF073.UINT16[L]
+#define RSCAN0RMDF073LL RSCAN0.RMDF073.UINT8[LL]
+#define RSCAN0RMDF073LH RSCAN0.RMDF073.UINT8[LH]
+#define RSCAN0RMDF073H RSCAN0.RMDF073.UINT16[H]
+#define RSCAN0RMDF073HL RSCAN0.RMDF073.UINT8[HL]
+#define RSCAN0RMDF073HH RSCAN0.RMDF073.UINT8[HH]
+#define RSCAN0RMDF173 RSCAN0.RMDF173.UINT32
+#define RSCAN0RMDF173L RSCAN0.RMDF173.UINT16[L]
+#define RSCAN0RMDF173LL RSCAN0.RMDF173.UINT8[LL]
+#define RSCAN0RMDF173LH RSCAN0.RMDF173.UINT8[LH]
+#define RSCAN0RMDF173H RSCAN0.RMDF173.UINT16[H]
+#define RSCAN0RMDF173HL RSCAN0.RMDF173.UINT8[HL]
+#define RSCAN0RMDF173HH RSCAN0.RMDF173.UINT8[HH]
+#define RSCAN0RMID74 RSCAN0.RMID74.UINT32
+#define RSCAN0RMID74L RSCAN0.RMID74.UINT16[L]
+#define RSCAN0RMID74LL RSCAN0.RMID74.UINT8[LL]
+#define RSCAN0RMID74LH RSCAN0.RMID74.UINT8[LH]
+#define RSCAN0RMID74H RSCAN0.RMID74.UINT16[H]
+#define RSCAN0RMID74HL RSCAN0.RMID74.UINT8[HL]
+#define RSCAN0RMID74HH RSCAN0.RMID74.UINT8[HH]
+#define RSCAN0RMPTR74 RSCAN0.RMPTR74.UINT32
+#define RSCAN0RMPTR74L RSCAN0.RMPTR74.UINT16[L]
+#define RSCAN0RMPTR74LL RSCAN0.RMPTR74.UINT8[LL]
+#define RSCAN0RMPTR74LH RSCAN0.RMPTR74.UINT8[LH]
+#define RSCAN0RMPTR74H RSCAN0.RMPTR74.UINT16[H]
+#define RSCAN0RMPTR74HL RSCAN0.RMPTR74.UINT8[HL]
+#define RSCAN0RMPTR74HH RSCAN0.RMPTR74.UINT8[HH]
+#define RSCAN0RMDF074 RSCAN0.RMDF074.UINT32
+#define RSCAN0RMDF074L RSCAN0.RMDF074.UINT16[L]
+#define RSCAN0RMDF074LL RSCAN0.RMDF074.UINT8[LL]
+#define RSCAN0RMDF074LH RSCAN0.RMDF074.UINT8[LH]
+#define RSCAN0RMDF074H RSCAN0.RMDF074.UINT16[H]
+#define RSCAN0RMDF074HL RSCAN0.RMDF074.UINT8[HL]
+#define RSCAN0RMDF074HH RSCAN0.RMDF074.UINT8[HH]
+#define RSCAN0RMDF174 RSCAN0.RMDF174.UINT32
+#define RSCAN0RMDF174L RSCAN0.RMDF174.UINT16[L]
+#define RSCAN0RMDF174LL RSCAN0.RMDF174.UINT8[LL]
+#define RSCAN0RMDF174LH RSCAN0.RMDF174.UINT8[LH]
+#define RSCAN0RMDF174H RSCAN0.RMDF174.UINT16[H]
+#define RSCAN0RMDF174HL RSCAN0.RMDF174.UINT8[HL]
+#define RSCAN0RMDF174HH RSCAN0.RMDF174.UINT8[HH]
+#define RSCAN0RMID75 RSCAN0.RMID75.UINT32
+#define RSCAN0RMID75L RSCAN0.RMID75.UINT16[L]
+#define RSCAN0RMID75LL RSCAN0.RMID75.UINT8[LL]
+#define RSCAN0RMID75LH RSCAN0.RMID75.UINT8[LH]
+#define RSCAN0RMID75H RSCAN0.RMID75.UINT16[H]
+#define RSCAN0RMID75HL RSCAN0.RMID75.UINT8[HL]
+#define RSCAN0RMID75HH RSCAN0.RMID75.UINT8[HH]
+#define RSCAN0RMPTR75 RSCAN0.RMPTR75.UINT32
+#define RSCAN0RMPTR75L RSCAN0.RMPTR75.UINT16[L]
+#define RSCAN0RMPTR75LL RSCAN0.RMPTR75.UINT8[LL]
+#define RSCAN0RMPTR75LH RSCAN0.RMPTR75.UINT8[LH]
+#define RSCAN0RMPTR75H RSCAN0.RMPTR75.UINT16[H]
+#define RSCAN0RMPTR75HL RSCAN0.RMPTR75.UINT8[HL]
+#define RSCAN0RMPTR75HH RSCAN0.RMPTR75.UINT8[HH]
+#define RSCAN0RMDF075 RSCAN0.RMDF075.UINT32
+#define RSCAN0RMDF075L RSCAN0.RMDF075.UINT16[L]
+#define RSCAN0RMDF075LL RSCAN0.RMDF075.UINT8[LL]
+#define RSCAN0RMDF075LH RSCAN0.RMDF075.UINT8[LH]
+#define RSCAN0RMDF075H RSCAN0.RMDF075.UINT16[H]
+#define RSCAN0RMDF075HL RSCAN0.RMDF075.UINT8[HL]
+#define RSCAN0RMDF075HH RSCAN0.RMDF075.UINT8[HH]
+#define RSCAN0RMDF175 RSCAN0.RMDF175.UINT32
+#define RSCAN0RMDF175L RSCAN0.RMDF175.UINT16[L]
+#define RSCAN0RMDF175LL RSCAN0.RMDF175.UINT8[LL]
+#define RSCAN0RMDF175LH RSCAN0.RMDF175.UINT8[LH]
+#define RSCAN0RMDF175H RSCAN0.RMDF175.UINT16[H]
+#define RSCAN0RMDF175HL RSCAN0.RMDF175.UINT8[HL]
+#define RSCAN0RMDF175HH RSCAN0.RMDF175.UINT8[HH]
+#define RSCAN0RMID76 RSCAN0.RMID76.UINT32
+#define RSCAN0RMID76L RSCAN0.RMID76.UINT16[L]
+#define RSCAN0RMID76LL RSCAN0.RMID76.UINT8[LL]
+#define RSCAN0RMID76LH RSCAN0.RMID76.UINT8[LH]
+#define RSCAN0RMID76H RSCAN0.RMID76.UINT16[H]
+#define RSCAN0RMID76HL RSCAN0.RMID76.UINT8[HL]
+#define RSCAN0RMID76HH RSCAN0.RMID76.UINT8[HH]
+#define RSCAN0RMPTR76 RSCAN0.RMPTR76.UINT32
+#define RSCAN0RMPTR76L RSCAN0.RMPTR76.UINT16[L]
+#define RSCAN0RMPTR76LL RSCAN0.RMPTR76.UINT8[LL]
+#define RSCAN0RMPTR76LH RSCAN0.RMPTR76.UINT8[LH]
+#define RSCAN0RMPTR76H RSCAN0.RMPTR76.UINT16[H]
+#define RSCAN0RMPTR76HL RSCAN0.RMPTR76.UINT8[HL]
+#define RSCAN0RMPTR76HH RSCAN0.RMPTR76.UINT8[HH]
+#define RSCAN0RMDF076 RSCAN0.RMDF076.UINT32
+#define RSCAN0RMDF076L RSCAN0.RMDF076.UINT16[L]
+#define RSCAN0RMDF076LL RSCAN0.RMDF076.UINT8[LL]
+#define RSCAN0RMDF076LH RSCAN0.RMDF076.UINT8[LH]
+#define RSCAN0RMDF076H RSCAN0.RMDF076.UINT16[H]
+#define RSCAN0RMDF076HL RSCAN0.RMDF076.UINT8[HL]
+#define RSCAN0RMDF076HH RSCAN0.RMDF076.UINT8[HH]
+#define RSCAN0RMDF176 RSCAN0.RMDF176.UINT32
+#define RSCAN0RMDF176L RSCAN0.RMDF176.UINT16[L]
+#define RSCAN0RMDF176LL RSCAN0.RMDF176.UINT8[LL]
+#define RSCAN0RMDF176LH RSCAN0.RMDF176.UINT8[LH]
+#define RSCAN0RMDF176H RSCAN0.RMDF176.UINT16[H]
+#define RSCAN0RMDF176HL RSCAN0.RMDF176.UINT8[HL]
+#define RSCAN0RMDF176HH RSCAN0.RMDF176.UINT8[HH]
+#define RSCAN0RMID77 RSCAN0.RMID77.UINT32
+#define RSCAN0RMID77L RSCAN0.RMID77.UINT16[L]
+#define RSCAN0RMID77LL RSCAN0.RMID77.UINT8[LL]
+#define RSCAN0RMID77LH RSCAN0.RMID77.UINT8[LH]
+#define RSCAN0RMID77H RSCAN0.RMID77.UINT16[H]
+#define RSCAN0RMID77HL RSCAN0.RMID77.UINT8[HL]
+#define RSCAN0RMID77HH RSCAN0.RMID77.UINT8[HH]
+#define RSCAN0RMPTR77 RSCAN0.RMPTR77.UINT32
+#define RSCAN0RMPTR77L RSCAN0.RMPTR77.UINT16[L]
+#define RSCAN0RMPTR77LL RSCAN0.RMPTR77.UINT8[LL]
+#define RSCAN0RMPTR77LH RSCAN0.RMPTR77.UINT8[LH]
+#define RSCAN0RMPTR77H RSCAN0.RMPTR77.UINT16[H]
+#define RSCAN0RMPTR77HL RSCAN0.RMPTR77.UINT8[HL]
+#define RSCAN0RMPTR77HH RSCAN0.RMPTR77.UINT8[HH]
+#define RSCAN0RMDF077 RSCAN0.RMDF077.UINT32
+#define RSCAN0RMDF077L RSCAN0.RMDF077.UINT16[L]
+#define RSCAN0RMDF077LL RSCAN0.RMDF077.UINT8[LL]
+#define RSCAN0RMDF077LH RSCAN0.RMDF077.UINT8[LH]
+#define RSCAN0RMDF077H RSCAN0.RMDF077.UINT16[H]
+#define RSCAN0RMDF077HL RSCAN0.RMDF077.UINT8[HL]
+#define RSCAN0RMDF077HH RSCAN0.RMDF077.UINT8[HH]
+#define RSCAN0RMDF177 RSCAN0.RMDF177.UINT32
+#define RSCAN0RMDF177L RSCAN0.RMDF177.UINT16[L]
+#define RSCAN0RMDF177LL RSCAN0.RMDF177.UINT8[LL]
+#define RSCAN0RMDF177LH RSCAN0.RMDF177.UINT8[LH]
+#define RSCAN0RMDF177H RSCAN0.RMDF177.UINT16[H]
+#define RSCAN0RMDF177HL RSCAN0.RMDF177.UINT8[HL]
+#define RSCAN0RMDF177HH RSCAN0.RMDF177.UINT8[HH]
+#define RSCAN0RMID78 RSCAN0.RMID78.UINT32
+#define RSCAN0RMID78L RSCAN0.RMID78.UINT16[L]
+#define RSCAN0RMID78LL RSCAN0.RMID78.UINT8[LL]
+#define RSCAN0RMID78LH RSCAN0.RMID78.UINT8[LH]
+#define RSCAN0RMID78H RSCAN0.RMID78.UINT16[H]
+#define RSCAN0RMID78HL RSCAN0.RMID78.UINT8[HL]
+#define RSCAN0RMID78HH RSCAN0.RMID78.UINT8[HH]
+#define RSCAN0RMPTR78 RSCAN0.RMPTR78.UINT32
+#define RSCAN0RMPTR78L RSCAN0.RMPTR78.UINT16[L]
+#define RSCAN0RMPTR78LL RSCAN0.RMPTR78.UINT8[LL]
+#define RSCAN0RMPTR78LH RSCAN0.RMPTR78.UINT8[LH]
+#define RSCAN0RMPTR78H RSCAN0.RMPTR78.UINT16[H]
+#define RSCAN0RMPTR78HL RSCAN0.RMPTR78.UINT8[HL]
+#define RSCAN0RMPTR78HH RSCAN0.RMPTR78.UINT8[HH]
+#define RSCAN0RMDF078 RSCAN0.RMDF078.UINT32
+#define RSCAN0RMDF078L RSCAN0.RMDF078.UINT16[L]
+#define RSCAN0RMDF078LL RSCAN0.RMDF078.UINT8[LL]
+#define RSCAN0RMDF078LH RSCAN0.RMDF078.UINT8[LH]
+#define RSCAN0RMDF078H RSCAN0.RMDF078.UINT16[H]
+#define RSCAN0RMDF078HL RSCAN0.RMDF078.UINT8[HL]
+#define RSCAN0RMDF078HH RSCAN0.RMDF078.UINT8[HH]
+#define RSCAN0RMDF178 RSCAN0.RMDF178.UINT32
+#define RSCAN0RMDF178L RSCAN0.RMDF178.UINT16[L]
+#define RSCAN0RMDF178LL RSCAN0.RMDF178.UINT8[LL]
+#define RSCAN0RMDF178LH RSCAN0.RMDF178.UINT8[LH]
+#define RSCAN0RMDF178H RSCAN0.RMDF178.UINT16[H]
+#define RSCAN0RMDF178HL RSCAN0.RMDF178.UINT8[HL]
+#define RSCAN0RMDF178HH RSCAN0.RMDF178.UINT8[HH]
+#define RSCAN0RMID79 RSCAN0.RMID79.UINT32
+#define RSCAN0RMID79L RSCAN0.RMID79.UINT16[L]
+#define RSCAN0RMID79LL RSCAN0.RMID79.UINT8[LL]
+#define RSCAN0RMID79LH RSCAN0.RMID79.UINT8[LH]
+#define RSCAN0RMID79H RSCAN0.RMID79.UINT16[H]
+#define RSCAN0RMID79HL RSCAN0.RMID79.UINT8[HL]
+#define RSCAN0RMID79HH RSCAN0.RMID79.UINT8[HH]
+#define RSCAN0RMPTR79 RSCAN0.RMPTR79.UINT32
+#define RSCAN0RMPTR79L RSCAN0.RMPTR79.UINT16[L]
+#define RSCAN0RMPTR79LL RSCAN0.RMPTR79.UINT8[LL]
+#define RSCAN0RMPTR79LH RSCAN0.RMPTR79.UINT8[LH]
+#define RSCAN0RMPTR79H RSCAN0.RMPTR79.UINT16[H]
+#define RSCAN0RMPTR79HL RSCAN0.RMPTR79.UINT8[HL]
+#define RSCAN0RMPTR79HH RSCAN0.RMPTR79.UINT8[HH]
+#define RSCAN0RMDF079 RSCAN0.RMDF079.UINT32
+#define RSCAN0RMDF079L RSCAN0.RMDF079.UINT16[L]
+#define RSCAN0RMDF079LL RSCAN0.RMDF079.UINT8[LL]
+#define RSCAN0RMDF079LH RSCAN0.RMDF079.UINT8[LH]
+#define RSCAN0RMDF079H RSCAN0.RMDF079.UINT16[H]
+#define RSCAN0RMDF079HL RSCAN0.RMDF079.UINT8[HL]
+#define RSCAN0RMDF079HH RSCAN0.RMDF079.UINT8[HH]
+#define RSCAN0RMDF179 RSCAN0.RMDF179.UINT32
+#define RSCAN0RMDF179L RSCAN0.RMDF179.UINT16[L]
+#define RSCAN0RMDF179LL RSCAN0.RMDF179.UINT8[LL]
+#define RSCAN0RMDF179LH RSCAN0.RMDF179.UINT8[LH]
+#define RSCAN0RMDF179H RSCAN0.RMDF179.UINT16[H]
+#define RSCAN0RMDF179HL RSCAN0.RMDF179.UINT8[HL]
+#define RSCAN0RMDF179HH RSCAN0.RMDF179.UINT8[HH]
+#define RSCAN0RFID0 RSCAN0.RFID0.UINT32
+#define RSCAN0RFID0L RSCAN0.RFID0.UINT16[L]
+#define RSCAN0RFID0LL RSCAN0.RFID0.UINT8[LL]
+#define RSCAN0RFID0LH RSCAN0.RFID0.UINT8[LH]
+#define RSCAN0RFID0H RSCAN0.RFID0.UINT16[H]
+#define RSCAN0RFID0HL RSCAN0.RFID0.UINT8[HL]
+#define RSCAN0RFID0HH RSCAN0.RFID0.UINT8[HH]
+#define RSCAN0RFPTR0 RSCAN0.RFPTR0.UINT32
+#define RSCAN0RFPTR0L RSCAN0.RFPTR0.UINT16[L]
+#define RSCAN0RFPTR0LL RSCAN0.RFPTR0.UINT8[LL]
+#define RSCAN0RFPTR0LH RSCAN0.RFPTR0.UINT8[LH]
+#define RSCAN0RFPTR0H RSCAN0.RFPTR0.UINT16[H]
+#define RSCAN0RFPTR0HL RSCAN0.RFPTR0.UINT8[HL]
+#define RSCAN0RFPTR0HH RSCAN0.RFPTR0.UINT8[HH]
+#define RSCAN0RFDF00 RSCAN0.RFDF00.UINT32
+#define RSCAN0RFDF00L RSCAN0.RFDF00.UINT16[L]
+#define RSCAN0RFDF00LL RSCAN0.RFDF00.UINT8[LL]
+#define RSCAN0RFDF00LH RSCAN0.RFDF00.UINT8[LH]
+#define RSCAN0RFDF00H RSCAN0.RFDF00.UINT16[H]
+#define RSCAN0RFDF00HL RSCAN0.RFDF00.UINT8[HL]
+#define RSCAN0RFDF00HH RSCAN0.RFDF00.UINT8[HH]
+#define RSCAN0RFDF10 RSCAN0.RFDF10.UINT32
+#define RSCAN0RFDF10L RSCAN0.RFDF10.UINT16[L]
+#define RSCAN0RFDF10LL RSCAN0.RFDF10.UINT8[LL]
+#define RSCAN0RFDF10LH RSCAN0.RFDF10.UINT8[LH]
+#define RSCAN0RFDF10H RSCAN0.RFDF10.UINT16[H]
+#define RSCAN0RFDF10HL RSCAN0.RFDF10.UINT8[HL]
+#define RSCAN0RFDF10HH RSCAN0.RFDF10.UINT8[HH]
+#define RSCAN0RFID1 RSCAN0.RFID1.UINT32
+#define RSCAN0RFID1L RSCAN0.RFID1.UINT16[L]
+#define RSCAN0RFID1LL RSCAN0.RFID1.UINT8[LL]
+#define RSCAN0RFID1LH RSCAN0.RFID1.UINT8[LH]
+#define RSCAN0RFID1H RSCAN0.RFID1.UINT16[H]
+#define RSCAN0RFID1HL RSCAN0.RFID1.UINT8[HL]
+#define RSCAN0RFID1HH RSCAN0.RFID1.UINT8[HH]
+#define RSCAN0RFPTR1 RSCAN0.RFPTR1.UINT32
+#define RSCAN0RFPTR1L RSCAN0.RFPTR1.UINT16[L]
+#define RSCAN0RFPTR1LL RSCAN0.RFPTR1.UINT8[LL]
+#define RSCAN0RFPTR1LH RSCAN0.RFPTR1.UINT8[LH]
+#define RSCAN0RFPTR1H RSCAN0.RFPTR1.UINT16[H]
+#define RSCAN0RFPTR1HL RSCAN0.RFPTR1.UINT8[HL]
+#define RSCAN0RFPTR1HH RSCAN0.RFPTR1.UINT8[HH]
+#define RSCAN0RFDF01 RSCAN0.RFDF01.UINT32
+#define RSCAN0RFDF01L RSCAN0.RFDF01.UINT16[L]
+#define RSCAN0RFDF01LL RSCAN0.RFDF01.UINT8[LL]
+#define RSCAN0RFDF01LH RSCAN0.RFDF01.UINT8[LH]
+#define RSCAN0RFDF01H RSCAN0.RFDF01.UINT16[H]
+#define RSCAN0RFDF01HL RSCAN0.RFDF01.UINT8[HL]
+#define RSCAN0RFDF01HH RSCAN0.RFDF01.UINT8[HH]
+#define RSCAN0RFDF11 RSCAN0.RFDF11.UINT32
+#define RSCAN0RFDF11L RSCAN0.RFDF11.UINT16[L]
+#define RSCAN0RFDF11LL RSCAN0.RFDF11.UINT8[LL]
+#define RSCAN0RFDF11LH RSCAN0.RFDF11.UINT8[LH]
+#define RSCAN0RFDF11H RSCAN0.RFDF11.UINT16[H]
+#define RSCAN0RFDF11HL RSCAN0.RFDF11.UINT8[HL]
+#define RSCAN0RFDF11HH RSCAN0.RFDF11.UINT8[HH]
+#define RSCAN0RFID2 RSCAN0.RFID2.UINT32
+#define RSCAN0RFID2L RSCAN0.RFID2.UINT16[L]
+#define RSCAN0RFID2LL RSCAN0.RFID2.UINT8[LL]
+#define RSCAN0RFID2LH RSCAN0.RFID2.UINT8[LH]
+#define RSCAN0RFID2H RSCAN0.RFID2.UINT16[H]
+#define RSCAN0RFID2HL RSCAN0.RFID2.UINT8[HL]
+#define RSCAN0RFID2HH RSCAN0.RFID2.UINT8[HH]
+#define RSCAN0RFPTR2 RSCAN0.RFPTR2.UINT32
+#define RSCAN0RFPTR2L RSCAN0.RFPTR2.UINT16[L]
+#define RSCAN0RFPTR2LL RSCAN0.RFPTR2.UINT8[LL]
+#define RSCAN0RFPTR2LH RSCAN0.RFPTR2.UINT8[LH]
+#define RSCAN0RFPTR2H RSCAN0.RFPTR2.UINT16[H]
+#define RSCAN0RFPTR2HL RSCAN0.RFPTR2.UINT8[HL]
+#define RSCAN0RFPTR2HH RSCAN0.RFPTR2.UINT8[HH]
+#define RSCAN0RFDF02 RSCAN0.RFDF02.UINT32
+#define RSCAN0RFDF02L RSCAN0.RFDF02.UINT16[L]
+#define RSCAN0RFDF02LL RSCAN0.RFDF02.UINT8[LL]
+#define RSCAN0RFDF02LH RSCAN0.RFDF02.UINT8[LH]
+#define RSCAN0RFDF02H RSCAN0.RFDF02.UINT16[H]
+#define RSCAN0RFDF02HL RSCAN0.RFDF02.UINT8[HL]
+#define RSCAN0RFDF02HH RSCAN0.RFDF02.UINT8[HH]
+#define RSCAN0RFDF12 RSCAN0.RFDF12.UINT32
+#define RSCAN0RFDF12L RSCAN0.RFDF12.UINT16[L]
+#define RSCAN0RFDF12LL RSCAN0.RFDF12.UINT8[LL]
+#define RSCAN0RFDF12LH RSCAN0.RFDF12.UINT8[LH]
+#define RSCAN0RFDF12H RSCAN0.RFDF12.UINT16[H]
+#define RSCAN0RFDF12HL RSCAN0.RFDF12.UINT8[HL]
+#define RSCAN0RFDF12HH RSCAN0.RFDF12.UINT8[HH]
+#define RSCAN0RFID3 RSCAN0.RFID3.UINT32
+#define RSCAN0RFID3L RSCAN0.RFID3.UINT16[L]
+#define RSCAN0RFID3LL RSCAN0.RFID3.UINT8[LL]
+#define RSCAN0RFID3LH RSCAN0.RFID3.UINT8[LH]
+#define RSCAN0RFID3H RSCAN0.RFID3.UINT16[H]
+#define RSCAN0RFID3HL RSCAN0.RFID3.UINT8[HL]
+#define RSCAN0RFID3HH RSCAN0.RFID3.UINT8[HH]
+#define RSCAN0RFPTR3 RSCAN0.RFPTR3.UINT32
+#define RSCAN0RFPTR3L RSCAN0.RFPTR3.UINT16[L]
+#define RSCAN0RFPTR3LL RSCAN0.RFPTR3.UINT8[LL]
+#define RSCAN0RFPTR3LH RSCAN0.RFPTR3.UINT8[LH]
+#define RSCAN0RFPTR3H RSCAN0.RFPTR3.UINT16[H]
+#define RSCAN0RFPTR3HL RSCAN0.RFPTR3.UINT8[HL]
+#define RSCAN0RFPTR3HH RSCAN0.RFPTR3.UINT8[HH]
+#define RSCAN0RFDF03 RSCAN0.RFDF03.UINT32
+#define RSCAN0RFDF03L RSCAN0.RFDF03.UINT16[L]
+#define RSCAN0RFDF03LL RSCAN0.RFDF03.UINT8[LL]
+#define RSCAN0RFDF03LH RSCAN0.RFDF03.UINT8[LH]
+#define RSCAN0RFDF03H RSCAN0.RFDF03.UINT16[H]
+#define RSCAN0RFDF03HL RSCAN0.RFDF03.UINT8[HL]
+#define RSCAN0RFDF03HH RSCAN0.RFDF03.UINT8[HH]
+#define RSCAN0RFDF13 RSCAN0.RFDF13.UINT32
+#define RSCAN0RFDF13L RSCAN0.RFDF13.UINT16[L]
+#define RSCAN0RFDF13LL RSCAN0.RFDF13.UINT8[LL]
+#define RSCAN0RFDF13LH RSCAN0.RFDF13.UINT8[LH]
+#define RSCAN0RFDF13H RSCAN0.RFDF13.UINT16[H]
+#define RSCAN0RFDF13HL RSCAN0.RFDF13.UINT8[HL]
+#define RSCAN0RFDF13HH RSCAN0.RFDF13.UINT8[HH]
+#define RSCAN0RFID4 RSCAN0.RFID4.UINT32
+#define RSCAN0RFID4L RSCAN0.RFID4.UINT16[L]
+#define RSCAN0RFID4LL RSCAN0.RFID4.UINT8[LL]
+#define RSCAN0RFID4LH RSCAN0.RFID4.UINT8[LH]
+#define RSCAN0RFID4H RSCAN0.RFID4.UINT16[H]
+#define RSCAN0RFID4HL RSCAN0.RFID4.UINT8[HL]
+#define RSCAN0RFID4HH RSCAN0.RFID4.UINT8[HH]
+#define RSCAN0RFPTR4 RSCAN0.RFPTR4.UINT32
+#define RSCAN0RFPTR4L RSCAN0.RFPTR4.UINT16[L]
+#define RSCAN0RFPTR4LL RSCAN0.RFPTR4.UINT8[LL]
+#define RSCAN0RFPTR4LH RSCAN0.RFPTR4.UINT8[LH]
+#define RSCAN0RFPTR4H RSCAN0.RFPTR4.UINT16[H]
+#define RSCAN0RFPTR4HL RSCAN0.RFPTR4.UINT8[HL]
+#define RSCAN0RFPTR4HH RSCAN0.RFPTR4.UINT8[HH]
+#define RSCAN0RFDF04 RSCAN0.RFDF04.UINT32
+#define RSCAN0RFDF04L RSCAN0.RFDF04.UINT16[L]
+#define RSCAN0RFDF04LL RSCAN0.RFDF04.UINT8[LL]
+#define RSCAN0RFDF04LH RSCAN0.RFDF04.UINT8[LH]
+#define RSCAN0RFDF04H RSCAN0.RFDF04.UINT16[H]
+#define RSCAN0RFDF04HL RSCAN0.RFDF04.UINT8[HL]
+#define RSCAN0RFDF04HH RSCAN0.RFDF04.UINT8[HH]
+#define RSCAN0RFDF14 RSCAN0.RFDF14.UINT32
+#define RSCAN0RFDF14L RSCAN0.RFDF14.UINT16[L]
+#define RSCAN0RFDF14LL RSCAN0.RFDF14.UINT8[LL]
+#define RSCAN0RFDF14LH RSCAN0.RFDF14.UINT8[LH]
+#define RSCAN0RFDF14H RSCAN0.RFDF14.UINT16[H]
+#define RSCAN0RFDF14HL RSCAN0.RFDF14.UINT8[HL]
+#define RSCAN0RFDF14HH RSCAN0.RFDF14.UINT8[HH]
+#define RSCAN0RFID5 RSCAN0.RFID5.UINT32
+#define RSCAN0RFID5L RSCAN0.RFID5.UINT16[L]
+#define RSCAN0RFID5LL RSCAN0.RFID5.UINT8[LL]
+#define RSCAN0RFID5LH RSCAN0.RFID5.UINT8[LH]
+#define RSCAN0RFID5H RSCAN0.RFID5.UINT16[H]
+#define RSCAN0RFID5HL RSCAN0.RFID5.UINT8[HL]
+#define RSCAN0RFID5HH RSCAN0.RFID5.UINT8[HH]
+#define RSCAN0RFPTR5 RSCAN0.RFPTR5.UINT32
+#define RSCAN0RFPTR5L RSCAN0.RFPTR5.UINT16[L]
+#define RSCAN0RFPTR5LL RSCAN0.RFPTR5.UINT8[LL]
+#define RSCAN0RFPTR5LH RSCAN0.RFPTR5.UINT8[LH]
+#define RSCAN0RFPTR5H RSCAN0.RFPTR5.UINT16[H]
+#define RSCAN0RFPTR5HL RSCAN0.RFPTR5.UINT8[HL]
+#define RSCAN0RFPTR5HH RSCAN0.RFPTR5.UINT8[HH]
+#define RSCAN0RFDF05 RSCAN0.RFDF05.UINT32
+#define RSCAN0RFDF05L RSCAN0.RFDF05.UINT16[L]
+#define RSCAN0RFDF05LL RSCAN0.RFDF05.UINT8[LL]
+#define RSCAN0RFDF05LH RSCAN0.RFDF05.UINT8[LH]
+#define RSCAN0RFDF05H RSCAN0.RFDF05.UINT16[H]
+#define RSCAN0RFDF05HL RSCAN0.RFDF05.UINT8[HL]
+#define RSCAN0RFDF05HH RSCAN0.RFDF05.UINT8[HH]
+#define RSCAN0RFDF15 RSCAN0.RFDF15.UINT32
+#define RSCAN0RFDF15L RSCAN0.RFDF15.UINT16[L]
+#define RSCAN0RFDF15LL RSCAN0.RFDF15.UINT8[LL]
+#define RSCAN0RFDF15LH RSCAN0.RFDF15.UINT8[LH]
+#define RSCAN0RFDF15H RSCAN0.RFDF15.UINT16[H]
+#define RSCAN0RFDF15HL RSCAN0.RFDF15.UINT8[HL]
+#define RSCAN0RFDF15HH RSCAN0.RFDF15.UINT8[HH]
+#define RSCAN0RFID6 RSCAN0.RFID6.UINT32
+#define RSCAN0RFID6L RSCAN0.RFID6.UINT16[L]
+#define RSCAN0RFID6LL RSCAN0.RFID6.UINT8[LL]
+#define RSCAN0RFID6LH RSCAN0.RFID6.UINT8[LH]
+#define RSCAN0RFID6H RSCAN0.RFID6.UINT16[H]
+#define RSCAN0RFID6HL RSCAN0.RFID6.UINT8[HL]
+#define RSCAN0RFID6HH RSCAN0.RFID6.UINT8[HH]
+#define RSCAN0RFPTR6 RSCAN0.RFPTR6.UINT32
+#define RSCAN0RFPTR6L RSCAN0.RFPTR6.UINT16[L]
+#define RSCAN0RFPTR6LL RSCAN0.RFPTR6.UINT8[LL]
+#define RSCAN0RFPTR6LH RSCAN0.RFPTR6.UINT8[LH]
+#define RSCAN0RFPTR6H RSCAN0.RFPTR6.UINT16[H]
+#define RSCAN0RFPTR6HL RSCAN0.RFPTR6.UINT8[HL]
+#define RSCAN0RFPTR6HH RSCAN0.RFPTR6.UINT8[HH]
+#define RSCAN0RFDF06 RSCAN0.RFDF06.UINT32
+#define RSCAN0RFDF06L RSCAN0.RFDF06.UINT16[L]
+#define RSCAN0RFDF06LL RSCAN0.RFDF06.UINT8[LL]
+#define RSCAN0RFDF06LH RSCAN0.RFDF06.UINT8[LH]
+#define RSCAN0RFDF06H RSCAN0.RFDF06.UINT16[H]
+#define RSCAN0RFDF06HL RSCAN0.RFDF06.UINT8[HL]
+#define RSCAN0RFDF06HH RSCAN0.RFDF06.UINT8[HH]
+#define RSCAN0RFDF16 RSCAN0.RFDF16.UINT32
+#define RSCAN0RFDF16L RSCAN0.RFDF16.UINT16[L]
+#define RSCAN0RFDF16LL RSCAN0.RFDF16.UINT8[LL]
+#define RSCAN0RFDF16LH RSCAN0.RFDF16.UINT8[LH]
+#define RSCAN0RFDF16H RSCAN0.RFDF16.UINT16[H]
+#define RSCAN0RFDF16HL RSCAN0.RFDF16.UINT8[HL]
+#define RSCAN0RFDF16HH RSCAN0.RFDF16.UINT8[HH]
+#define RSCAN0RFID7 RSCAN0.RFID7.UINT32
+#define RSCAN0RFID7L RSCAN0.RFID7.UINT16[L]
+#define RSCAN0RFID7LL RSCAN0.RFID7.UINT8[LL]
+#define RSCAN0RFID7LH RSCAN0.RFID7.UINT8[LH]
+#define RSCAN0RFID7H RSCAN0.RFID7.UINT16[H]
+#define RSCAN0RFID7HL RSCAN0.RFID7.UINT8[HL]
+#define RSCAN0RFID7HH RSCAN0.RFID7.UINT8[HH]
+#define RSCAN0RFPTR7 RSCAN0.RFPTR7.UINT32
+#define RSCAN0RFPTR7L RSCAN0.RFPTR7.UINT16[L]
+#define RSCAN0RFPTR7LL RSCAN0.RFPTR7.UINT8[LL]
+#define RSCAN0RFPTR7LH RSCAN0.RFPTR7.UINT8[LH]
+#define RSCAN0RFPTR7H RSCAN0.RFPTR7.UINT16[H]
+#define RSCAN0RFPTR7HL RSCAN0.RFPTR7.UINT8[HL]
+#define RSCAN0RFPTR7HH RSCAN0.RFPTR7.UINT8[HH]
+#define RSCAN0RFDF07 RSCAN0.RFDF07.UINT32
+#define RSCAN0RFDF07L RSCAN0.RFDF07.UINT16[L]
+#define RSCAN0RFDF07LL RSCAN0.RFDF07.UINT8[LL]
+#define RSCAN0RFDF07LH RSCAN0.RFDF07.UINT8[LH]
+#define RSCAN0RFDF07H RSCAN0.RFDF07.UINT16[H]
+#define RSCAN0RFDF07HL RSCAN0.RFDF07.UINT8[HL]
+#define RSCAN0RFDF07HH RSCAN0.RFDF07.UINT8[HH]
+#define RSCAN0RFDF17 RSCAN0.RFDF17.UINT32
+#define RSCAN0RFDF17L RSCAN0.RFDF17.UINT16[L]
+#define RSCAN0RFDF17LL RSCAN0.RFDF17.UINT8[LL]
+#define RSCAN0RFDF17LH RSCAN0.RFDF17.UINT8[LH]
+#define RSCAN0RFDF17H RSCAN0.RFDF17.UINT16[H]
+#define RSCAN0RFDF17HL RSCAN0.RFDF17.UINT8[HL]
+#define RSCAN0RFDF17HH RSCAN0.RFDF17.UINT8[HH]
+#define RSCAN0CFID0 RSCAN0.CFID0.UINT32
+#define RSCAN0CFID0L RSCAN0.CFID0.UINT16[L]
+#define RSCAN0CFID0LL RSCAN0.CFID0.UINT8[LL]
+#define RSCAN0CFID0LH RSCAN0.CFID0.UINT8[LH]
+#define RSCAN0CFID0H RSCAN0.CFID0.UINT16[H]
+#define RSCAN0CFID0HL RSCAN0.CFID0.UINT8[HL]
+#define RSCAN0CFID0HH RSCAN0.CFID0.UINT8[HH]
+#define RSCAN0CFPTR0 RSCAN0.CFPTR0.UINT32
+#define RSCAN0CFPTR0L RSCAN0.CFPTR0.UINT16[L]
+#define RSCAN0CFPTR0LL RSCAN0.CFPTR0.UINT8[LL]
+#define RSCAN0CFPTR0LH RSCAN0.CFPTR0.UINT8[LH]
+#define RSCAN0CFPTR0H RSCAN0.CFPTR0.UINT16[H]
+#define RSCAN0CFPTR0HL RSCAN0.CFPTR0.UINT8[HL]
+#define RSCAN0CFPTR0HH RSCAN0.CFPTR0.UINT8[HH]
+#define RSCAN0CFDF00 RSCAN0.CFDF00.UINT32
+#define RSCAN0CFDF00L RSCAN0.CFDF00.UINT16[L]
+#define RSCAN0CFDF00LL RSCAN0.CFDF00.UINT8[LL]
+#define RSCAN0CFDF00LH RSCAN0.CFDF00.UINT8[LH]
+#define RSCAN0CFDF00H RSCAN0.CFDF00.UINT16[H]
+#define RSCAN0CFDF00HL RSCAN0.CFDF00.UINT8[HL]
+#define RSCAN0CFDF00HH RSCAN0.CFDF00.UINT8[HH]
+#define RSCAN0CFDF10 RSCAN0.CFDF10.UINT32
+#define RSCAN0CFDF10L RSCAN0.CFDF10.UINT16[L]
+#define RSCAN0CFDF10LL RSCAN0.CFDF10.UINT8[LL]
+#define RSCAN0CFDF10LH RSCAN0.CFDF10.UINT8[LH]
+#define RSCAN0CFDF10H RSCAN0.CFDF10.UINT16[H]
+#define RSCAN0CFDF10HL RSCAN0.CFDF10.UINT8[HL]
+#define RSCAN0CFDF10HH RSCAN0.CFDF10.UINT8[HH]
+#define RSCAN0CFID1 RSCAN0.CFID1.UINT32
+#define RSCAN0CFID1L RSCAN0.CFID1.UINT16[L]
+#define RSCAN0CFID1LL RSCAN0.CFID1.UINT8[LL]
+#define RSCAN0CFID1LH RSCAN0.CFID1.UINT8[LH]
+#define RSCAN0CFID1H RSCAN0.CFID1.UINT16[H]
+#define RSCAN0CFID1HL RSCAN0.CFID1.UINT8[HL]
+#define RSCAN0CFID1HH RSCAN0.CFID1.UINT8[HH]
+#define RSCAN0CFPTR1 RSCAN0.CFPTR1.UINT32
+#define RSCAN0CFPTR1L RSCAN0.CFPTR1.UINT16[L]
+#define RSCAN0CFPTR1LL RSCAN0.CFPTR1.UINT8[LL]
+#define RSCAN0CFPTR1LH RSCAN0.CFPTR1.UINT8[LH]
+#define RSCAN0CFPTR1H RSCAN0.CFPTR1.UINT16[H]
+#define RSCAN0CFPTR1HL RSCAN0.CFPTR1.UINT8[HL]
+#define RSCAN0CFPTR1HH RSCAN0.CFPTR1.UINT8[HH]
+#define RSCAN0CFDF01 RSCAN0.CFDF01.UINT32
+#define RSCAN0CFDF01L RSCAN0.CFDF01.UINT16[L]
+#define RSCAN0CFDF01LL RSCAN0.CFDF01.UINT8[LL]
+#define RSCAN0CFDF01LH RSCAN0.CFDF01.UINT8[LH]
+#define RSCAN0CFDF01H RSCAN0.CFDF01.UINT16[H]
+#define RSCAN0CFDF01HL RSCAN0.CFDF01.UINT8[HL]
+#define RSCAN0CFDF01HH RSCAN0.CFDF01.UINT8[HH]
+#define RSCAN0CFDF11 RSCAN0.CFDF11.UINT32
+#define RSCAN0CFDF11L RSCAN0.CFDF11.UINT16[L]
+#define RSCAN0CFDF11LL RSCAN0.CFDF11.UINT8[LL]
+#define RSCAN0CFDF11LH RSCAN0.CFDF11.UINT8[LH]
+#define RSCAN0CFDF11H RSCAN0.CFDF11.UINT16[H]
+#define RSCAN0CFDF11HL RSCAN0.CFDF11.UINT8[HL]
+#define RSCAN0CFDF11HH RSCAN0.CFDF11.UINT8[HH]
+#define RSCAN0CFID2 RSCAN0.CFID2.UINT32
+#define RSCAN0CFID2L RSCAN0.CFID2.UINT16[L]
+#define RSCAN0CFID2LL RSCAN0.CFID2.UINT8[LL]
+#define RSCAN0CFID2LH RSCAN0.CFID2.UINT8[LH]
+#define RSCAN0CFID2H RSCAN0.CFID2.UINT16[H]
+#define RSCAN0CFID2HL RSCAN0.CFID2.UINT8[HL]
+#define RSCAN0CFID2HH RSCAN0.CFID2.UINT8[HH]
+#define RSCAN0CFPTR2 RSCAN0.CFPTR2.UINT32
+#define RSCAN0CFPTR2L RSCAN0.CFPTR2.UINT16[L]
+#define RSCAN0CFPTR2LL RSCAN0.CFPTR2.UINT8[LL]
+#define RSCAN0CFPTR2LH RSCAN0.CFPTR2.UINT8[LH]
+#define RSCAN0CFPTR2H RSCAN0.CFPTR2.UINT16[H]
+#define RSCAN0CFPTR2HL RSCAN0.CFPTR2.UINT8[HL]
+#define RSCAN0CFPTR2HH RSCAN0.CFPTR2.UINT8[HH]
+#define RSCAN0CFDF02 RSCAN0.CFDF02.UINT32
+#define RSCAN0CFDF02L RSCAN0.CFDF02.UINT16[L]
+#define RSCAN0CFDF02LL RSCAN0.CFDF02.UINT8[LL]
+#define RSCAN0CFDF02LH RSCAN0.CFDF02.UINT8[LH]
+#define RSCAN0CFDF02H RSCAN0.CFDF02.UINT16[H]
+#define RSCAN0CFDF02HL RSCAN0.CFDF02.UINT8[HL]
+#define RSCAN0CFDF02HH RSCAN0.CFDF02.UINT8[HH]
+#define RSCAN0CFDF12 RSCAN0.CFDF12.UINT32
+#define RSCAN0CFDF12L RSCAN0.CFDF12.UINT16[L]
+#define RSCAN0CFDF12LL RSCAN0.CFDF12.UINT8[LL]
+#define RSCAN0CFDF12LH RSCAN0.CFDF12.UINT8[LH]
+#define RSCAN0CFDF12H RSCAN0.CFDF12.UINT16[H]
+#define RSCAN0CFDF12HL RSCAN0.CFDF12.UINT8[HL]
+#define RSCAN0CFDF12HH RSCAN0.CFDF12.UINT8[HH]
+#define RSCAN0CFID3 RSCAN0.CFID3.UINT32
+#define RSCAN0CFID3L RSCAN0.CFID3.UINT16[L]
+#define RSCAN0CFID3LL RSCAN0.CFID3.UINT8[LL]
+#define RSCAN0CFID3LH RSCAN0.CFID3.UINT8[LH]
+#define RSCAN0CFID3H RSCAN0.CFID3.UINT16[H]
+#define RSCAN0CFID3HL RSCAN0.CFID3.UINT8[HL]
+#define RSCAN0CFID3HH RSCAN0.CFID3.UINT8[HH]
+#define RSCAN0CFPTR3 RSCAN0.CFPTR3.UINT32
+#define RSCAN0CFPTR3L RSCAN0.CFPTR3.UINT16[L]
+#define RSCAN0CFPTR3LL RSCAN0.CFPTR3.UINT8[LL]
+#define RSCAN0CFPTR3LH RSCAN0.CFPTR3.UINT8[LH]
+#define RSCAN0CFPTR3H RSCAN0.CFPTR3.UINT16[H]
+#define RSCAN0CFPTR3HL RSCAN0.CFPTR3.UINT8[HL]
+#define RSCAN0CFPTR3HH RSCAN0.CFPTR3.UINT8[HH]
+#define RSCAN0CFDF03 RSCAN0.CFDF03.UINT32
+#define RSCAN0CFDF03L RSCAN0.CFDF03.UINT16[L]
+#define RSCAN0CFDF03LL RSCAN0.CFDF03.UINT8[LL]
+#define RSCAN0CFDF03LH RSCAN0.CFDF03.UINT8[LH]
+#define RSCAN0CFDF03H RSCAN0.CFDF03.UINT16[H]
+#define RSCAN0CFDF03HL RSCAN0.CFDF03.UINT8[HL]
+#define RSCAN0CFDF03HH RSCAN0.CFDF03.UINT8[HH]
+#define RSCAN0CFDF13 RSCAN0.CFDF13.UINT32
+#define RSCAN0CFDF13L RSCAN0.CFDF13.UINT16[L]
+#define RSCAN0CFDF13LL RSCAN0.CFDF13.UINT8[LL]
+#define RSCAN0CFDF13LH RSCAN0.CFDF13.UINT8[LH]
+#define RSCAN0CFDF13H RSCAN0.CFDF13.UINT16[H]
+#define RSCAN0CFDF13HL RSCAN0.CFDF13.UINT8[HL]
+#define RSCAN0CFDF13HH RSCAN0.CFDF13.UINT8[HH]
+#define RSCAN0CFID4 RSCAN0.CFID4.UINT32
+#define RSCAN0CFID4L RSCAN0.CFID4.UINT16[L]
+#define RSCAN0CFID4LL RSCAN0.CFID4.UINT8[LL]
+#define RSCAN0CFID4LH RSCAN0.CFID4.UINT8[LH]
+#define RSCAN0CFID4H RSCAN0.CFID4.UINT16[H]
+#define RSCAN0CFID4HL RSCAN0.CFID4.UINT8[HL]
+#define RSCAN0CFID4HH RSCAN0.CFID4.UINT8[HH]
+#define RSCAN0CFPTR4 RSCAN0.CFPTR4.UINT32
+#define RSCAN0CFPTR4L RSCAN0.CFPTR4.UINT16[L]
+#define RSCAN0CFPTR4LL RSCAN0.CFPTR4.UINT8[LL]
+#define RSCAN0CFPTR4LH RSCAN0.CFPTR4.UINT8[LH]
+#define RSCAN0CFPTR4H RSCAN0.CFPTR4.UINT16[H]
+#define RSCAN0CFPTR4HL RSCAN0.CFPTR4.UINT8[HL]
+#define RSCAN0CFPTR4HH RSCAN0.CFPTR4.UINT8[HH]
+#define RSCAN0CFDF04 RSCAN0.CFDF04.UINT32
+#define RSCAN0CFDF04L RSCAN0.CFDF04.UINT16[L]
+#define RSCAN0CFDF04LL RSCAN0.CFDF04.UINT8[LL]
+#define RSCAN0CFDF04LH RSCAN0.CFDF04.UINT8[LH]
+#define RSCAN0CFDF04H RSCAN0.CFDF04.UINT16[H]
+#define RSCAN0CFDF04HL RSCAN0.CFDF04.UINT8[HL]
+#define RSCAN0CFDF04HH RSCAN0.CFDF04.UINT8[HH]
+#define RSCAN0CFDF14 RSCAN0.CFDF14.UINT32
+#define RSCAN0CFDF14L RSCAN0.CFDF14.UINT16[L]
+#define RSCAN0CFDF14LL RSCAN0.CFDF14.UINT8[LL]
+#define RSCAN0CFDF14LH RSCAN0.CFDF14.UINT8[LH]
+#define RSCAN0CFDF14H RSCAN0.CFDF14.UINT16[H]
+#define RSCAN0CFDF14HL RSCAN0.CFDF14.UINT8[HL]
+#define RSCAN0CFDF14HH RSCAN0.CFDF14.UINT8[HH]
+#define RSCAN0CFID5 RSCAN0.CFID5.UINT32
+#define RSCAN0CFID5L RSCAN0.CFID5.UINT16[L]
+#define RSCAN0CFID5LL RSCAN0.CFID5.UINT8[LL]
+#define RSCAN0CFID5LH RSCAN0.CFID5.UINT8[LH]
+#define RSCAN0CFID5H RSCAN0.CFID5.UINT16[H]
+#define RSCAN0CFID5HL RSCAN0.CFID5.UINT8[HL]
+#define RSCAN0CFID5HH RSCAN0.CFID5.UINT8[HH]
+#define RSCAN0CFPTR5 RSCAN0.CFPTR5.UINT32
+#define RSCAN0CFPTR5L RSCAN0.CFPTR5.UINT16[L]
+#define RSCAN0CFPTR5LL RSCAN0.CFPTR5.UINT8[LL]
+#define RSCAN0CFPTR5LH RSCAN0.CFPTR5.UINT8[LH]
+#define RSCAN0CFPTR5H RSCAN0.CFPTR5.UINT16[H]
+#define RSCAN0CFPTR5HL RSCAN0.CFPTR5.UINT8[HL]
+#define RSCAN0CFPTR5HH RSCAN0.CFPTR5.UINT8[HH]
+#define RSCAN0CFDF05 RSCAN0.CFDF05.UINT32
+#define RSCAN0CFDF05L RSCAN0.CFDF05.UINT16[L]
+#define RSCAN0CFDF05LL RSCAN0.CFDF05.UINT8[LL]
+#define RSCAN0CFDF05LH RSCAN0.CFDF05.UINT8[LH]
+#define RSCAN0CFDF05H RSCAN0.CFDF05.UINT16[H]
+#define RSCAN0CFDF05HL RSCAN0.CFDF05.UINT8[HL]
+#define RSCAN0CFDF05HH RSCAN0.CFDF05.UINT8[HH]
+#define RSCAN0CFDF15 RSCAN0.CFDF15.UINT32
+#define RSCAN0CFDF15L RSCAN0.CFDF15.UINT16[L]
+#define RSCAN0CFDF15LL RSCAN0.CFDF15.UINT8[LL]
+#define RSCAN0CFDF15LH RSCAN0.CFDF15.UINT8[LH]
+#define RSCAN0CFDF15H RSCAN0.CFDF15.UINT16[H]
+#define RSCAN0CFDF15HL RSCAN0.CFDF15.UINT8[HL]
+#define RSCAN0CFDF15HH RSCAN0.CFDF15.UINT8[HH]
+#define RSCAN0CFID6 RSCAN0.CFID6.UINT32
+#define RSCAN0CFID6L RSCAN0.CFID6.UINT16[L]
+#define RSCAN0CFID6LL RSCAN0.CFID6.UINT8[LL]
+#define RSCAN0CFID6LH RSCAN0.CFID6.UINT8[LH]
+#define RSCAN0CFID6H RSCAN0.CFID6.UINT16[H]
+#define RSCAN0CFID6HL RSCAN0.CFID6.UINT8[HL]
+#define RSCAN0CFID6HH RSCAN0.CFID6.UINT8[HH]
+#define RSCAN0CFPTR6 RSCAN0.CFPTR6.UINT32
+#define RSCAN0CFPTR6L RSCAN0.CFPTR6.UINT16[L]
+#define RSCAN0CFPTR6LL RSCAN0.CFPTR6.UINT8[LL]
+#define RSCAN0CFPTR6LH RSCAN0.CFPTR6.UINT8[LH]
+#define RSCAN0CFPTR6H RSCAN0.CFPTR6.UINT16[H]
+#define RSCAN0CFPTR6HL RSCAN0.CFPTR6.UINT8[HL]
+#define RSCAN0CFPTR6HH RSCAN0.CFPTR6.UINT8[HH]
+#define RSCAN0CFDF06 RSCAN0.CFDF06.UINT32
+#define RSCAN0CFDF06L RSCAN0.CFDF06.UINT16[L]
+#define RSCAN0CFDF06LL RSCAN0.CFDF06.UINT8[LL]
+#define RSCAN0CFDF06LH RSCAN0.CFDF06.UINT8[LH]
+#define RSCAN0CFDF06H RSCAN0.CFDF06.UINT16[H]
+#define RSCAN0CFDF06HL RSCAN0.CFDF06.UINT8[HL]
+#define RSCAN0CFDF06HH RSCAN0.CFDF06.UINT8[HH]
+#define RSCAN0CFDF16 RSCAN0.CFDF16.UINT32
+#define RSCAN0CFDF16L RSCAN0.CFDF16.UINT16[L]
+#define RSCAN0CFDF16LL RSCAN0.CFDF16.UINT8[LL]
+#define RSCAN0CFDF16LH RSCAN0.CFDF16.UINT8[LH]
+#define RSCAN0CFDF16H RSCAN0.CFDF16.UINT16[H]
+#define RSCAN0CFDF16HL RSCAN0.CFDF16.UINT8[HL]
+#define RSCAN0CFDF16HH RSCAN0.CFDF16.UINT8[HH]
+#define RSCAN0CFID7 RSCAN0.CFID7.UINT32
+#define RSCAN0CFID7L RSCAN0.CFID7.UINT16[L]
+#define RSCAN0CFID7LL RSCAN0.CFID7.UINT8[LL]
+#define RSCAN0CFID7LH RSCAN0.CFID7.UINT8[LH]
+#define RSCAN0CFID7H RSCAN0.CFID7.UINT16[H]
+#define RSCAN0CFID7HL RSCAN0.CFID7.UINT8[HL]
+#define RSCAN0CFID7HH RSCAN0.CFID7.UINT8[HH]
+#define RSCAN0CFPTR7 RSCAN0.CFPTR7.UINT32
+#define RSCAN0CFPTR7L RSCAN0.CFPTR7.UINT16[L]
+#define RSCAN0CFPTR7LL RSCAN0.CFPTR7.UINT8[LL]
+#define RSCAN0CFPTR7LH RSCAN0.CFPTR7.UINT8[LH]
+#define RSCAN0CFPTR7H RSCAN0.CFPTR7.UINT16[H]
+#define RSCAN0CFPTR7HL RSCAN0.CFPTR7.UINT8[HL]
+#define RSCAN0CFPTR7HH RSCAN0.CFPTR7.UINT8[HH]
+#define RSCAN0CFDF07 RSCAN0.CFDF07.UINT32
+#define RSCAN0CFDF07L RSCAN0.CFDF07.UINT16[L]
+#define RSCAN0CFDF07LL RSCAN0.CFDF07.UINT8[LL]
+#define RSCAN0CFDF07LH RSCAN0.CFDF07.UINT8[LH]
+#define RSCAN0CFDF07H RSCAN0.CFDF07.UINT16[H]
+#define RSCAN0CFDF07HL RSCAN0.CFDF07.UINT8[HL]
+#define RSCAN0CFDF07HH RSCAN0.CFDF07.UINT8[HH]
+#define RSCAN0CFDF17 RSCAN0.CFDF17.UINT32
+#define RSCAN0CFDF17L RSCAN0.CFDF17.UINT16[L]
+#define RSCAN0CFDF17LL RSCAN0.CFDF17.UINT8[LL]
+#define RSCAN0CFDF17LH RSCAN0.CFDF17.UINT8[LH]
+#define RSCAN0CFDF17H RSCAN0.CFDF17.UINT16[H]
+#define RSCAN0CFDF17HL RSCAN0.CFDF17.UINT8[HL]
+#define RSCAN0CFDF17HH RSCAN0.CFDF17.UINT8[HH]
+#define RSCAN0CFID8 RSCAN0.CFID8.UINT32
+#define RSCAN0CFID8L RSCAN0.CFID8.UINT16[L]
+#define RSCAN0CFID8LL RSCAN0.CFID8.UINT8[LL]
+#define RSCAN0CFID8LH RSCAN0.CFID8.UINT8[LH]
+#define RSCAN0CFID8H RSCAN0.CFID8.UINT16[H]
+#define RSCAN0CFID8HL RSCAN0.CFID8.UINT8[HL]
+#define RSCAN0CFID8HH RSCAN0.CFID8.UINT8[HH]
+#define RSCAN0CFPTR8 RSCAN0.CFPTR8.UINT32
+#define RSCAN0CFPTR8L RSCAN0.CFPTR8.UINT16[L]
+#define RSCAN0CFPTR8LL RSCAN0.CFPTR8.UINT8[LL]
+#define RSCAN0CFPTR8LH RSCAN0.CFPTR8.UINT8[LH]
+#define RSCAN0CFPTR8H RSCAN0.CFPTR8.UINT16[H]
+#define RSCAN0CFPTR8HL RSCAN0.CFPTR8.UINT8[HL]
+#define RSCAN0CFPTR8HH RSCAN0.CFPTR8.UINT8[HH]
+#define RSCAN0CFDF08 RSCAN0.CFDF08.UINT32
+#define RSCAN0CFDF08L RSCAN0.CFDF08.UINT16[L]
+#define RSCAN0CFDF08LL RSCAN0.CFDF08.UINT8[LL]
+#define RSCAN0CFDF08LH RSCAN0.CFDF08.UINT8[LH]
+#define RSCAN0CFDF08H RSCAN0.CFDF08.UINT16[H]
+#define RSCAN0CFDF08HL RSCAN0.CFDF08.UINT8[HL]
+#define RSCAN0CFDF08HH RSCAN0.CFDF08.UINT8[HH]
+#define RSCAN0CFDF18 RSCAN0.CFDF18.UINT32
+#define RSCAN0CFDF18L RSCAN0.CFDF18.UINT16[L]
+#define RSCAN0CFDF18LL RSCAN0.CFDF18.UINT8[LL]
+#define RSCAN0CFDF18LH RSCAN0.CFDF18.UINT8[LH]
+#define RSCAN0CFDF18H RSCAN0.CFDF18.UINT16[H]
+#define RSCAN0CFDF18HL RSCAN0.CFDF18.UINT8[HL]
+#define RSCAN0CFDF18HH RSCAN0.CFDF18.UINT8[HH]
+#define RSCAN0CFID9 RSCAN0.CFID9.UINT32
+#define RSCAN0CFID9L RSCAN0.CFID9.UINT16[L]
+#define RSCAN0CFID9LL RSCAN0.CFID9.UINT8[LL]
+#define RSCAN0CFID9LH RSCAN0.CFID9.UINT8[LH]
+#define RSCAN0CFID9H RSCAN0.CFID9.UINT16[H]
+#define RSCAN0CFID9HL RSCAN0.CFID9.UINT8[HL]
+#define RSCAN0CFID9HH RSCAN0.CFID9.UINT8[HH]
+#define RSCAN0CFPTR9 RSCAN0.CFPTR9.UINT32
+#define RSCAN0CFPTR9L RSCAN0.CFPTR9.UINT16[L]
+#define RSCAN0CFPTR9LL RSCAN0.CFPTR9.UINT8[LL]
+#define RSCAN0CFPTR9LH RSCAN0.CFPTR9.UINT8[LH]
+#define RSCAN0CFPTR9H RSCAN0.CFPTR9.UINT16[H]
+#define RSCAN0CFPTR9HL RSCAN0.CFPTR9.UINT8[HL]
+#define RSCAN0CFPTR9HH RSCAN0.CFPTR9.UINT8[HH]
+#define RSCAN0CFDF09 RSCAN0.CFDF09.UINT32
+#define RSCAN0CFDF09L RSCAN0.CFDF09.UINT16[L]
+#define RSCAN0CFDF09LL RSCAN0.CFDF09.UINT8[LL]
+#define RSCAN0CFDF09LH RSCAN0.CFDF09.UINT8[LH]
+#define RSCAN0CFDF09H RSCAN0.CFDF09.UINT16[H]
+#define RSCAN0CFDF09HL RSCAN0.CFDF09.UINT8[HL]
+#define RSCAN0CFDF09HH RSCAN0.CFDF09.UINT8[HH]
+#define RSCAN0CFDF19 RSCAN0.CFDF19.UINT32
+#define RSCAN0CFDF19L RSCAN0.CFDF19.UINT16[L]
+#define RSCAN0CFDF19LL RSCAN0.CFDF19.UINT8[LL]
+#define RSCAN0CFDF19LH RSCAN0.CFDF19.UINT8[LH]
+#define RSCAN0CFDF19H RSCAN0.CFDF19.UINT16[H]
+#define RSCAN0CFDF19HL RSCAN0.CFDF19.UINT8[HL]
+#define RSCAN0CFDF19HH RSCAN0.CFDF19.UINT8[HH]
+#define RSCAN0CFID10 RSCAN0.CFID10.UINT32
+#define RSCAN0CFID10L RSCAN0.CFID10.UINT16[L]
+#define RSCAN0CFID10LL RSCAN0.CFID10.UINT8[LL]
+#define RSCAN0CFID10LH RSCAN0.CFID10.UINT8[LH]
+#define RSCAN0CFID10H RSCAN0.CFID10.UINT16[H]
+#define RSCAN0CFID10HL RSCAN0.CFID10.UINT8[HL]
+#define RSCAN0CFID10HH RSCAN0.CFID10.UINT8[HH]
+#define RSCAN0CFPTR10 RSCAN0.CFPTR10.UINT32
+#define RSCAN0CFPTR10L RSCAN0.CFPTR10.UINT16[L]
+#define RSCAN0CFPTR10LL RSCAN0.CFPTR10.UINT8[LL]
+#define RSCAN0CFPTR10LH RSCAN0.CFPTR10.UINT8[LH]
+#define RSCAN0CFPTR10H RSCAN0.CFPTR10.UINT16[H]
+#define RSCAN0CFPTR10HL RSCAN0.CFPTR10.UINT8[HL]
+#define RSCAN0CFPTR10HH RSCAN0.CFPTR10.UINT8[HH]
+#define RSCAN0CFDF010 RSCAN0.CFDF010.UINT32
+#define RSCAN0CFDF010L RSCAN0.CFDF010.UINT16[L]
+#define RSCAN0CFDF010LL RSCAN0.CFDF010.UINT8[LL]
+#define RSCAN0CFDF010LH RSCAN0.CFDF010.UINT8[LH]
+#define RSCAN0CFDF010H RSCAN0.CFDF010.UINT16[H]
+#define RSCAN0CFDF010HL RSCAN0.CFDF010.UINT8[HL]
+#define RSCAN0CFDF010HH RSCAN0.CFDF010.UINT8[HH]
+#define RSCAN0CFDF110 RSCAN0.CFDF110.UINT32
+#define RSCAN0CFDF110L RSCAN0.CFDF110.UINT16[L]
+#define RSCAN0CFDF110LL RSCAN0.CFDF110.UINT8[LL]
+#define RSCAN0CFDF110LH RSCAN0.CFDF110.UINT8[LH]
+#define RSCAN0CFDF110H RSCAN0.CFDF110.UINT16[H]
+#define RSCAN0CFDF110HL RSCAN0.CFDF110.UINT8[HL]
+#define RSCAN0CFDF110HH RSCAN0.CFDF110.UINT8[HH]
+#define RSCAN0CFID11 RSCAN0.CFID11.UINT32
+#define RSCAN0CFID11L RSCAN0.CFID11.UINT16[L]
+#define RSCAN0CFID11LL RSCAN0.CFID11.UINT8[LL]
+#define RSCAN0CFID11LH RSCAN0.CFID11.UINT8[LH]
+#define RSCAN0CFID11H RSCAN0.CFID11.UINT16[H]
+#define RSCAN0CFID11HL RSCAN0.CFID11.UINT8[HL]
+#define RSCAN0CFID11HH RSCAN0.CFID11.UINT8[HH]
+#define RSCAN0CFPTR11 RSCAN0.CFPTR11.UINT32
+#define RSCAN0CFPTR11L RSCAN0.CFPTR11.UINT16[L]
+#define RSCAN0CFPTR11LL RSCAN0.CFPTR11.UINT8[LL]
+#define RSCAN0CFPTR11LH RSCAN0.CFPTR11.UINT8[LH]
+#define RSCAN0CFPTR11H RSCAN0.CFPTR11.UINT16[H]
+#define RSCAN0CFPTR11HL RSCAN0.CFPTR11.UINT8[HL]
+#define RSCAN0CFPTR11HH RSCAN0.CFPTR11.UINT8[HH]
+#define RSCAN0CFDF011 RSCAN0.CFDF011.UINT32
+#define RSCAN0CFDF011L RSCAN0.CFDF011.UINT16[L]
+#define RSCAN0CFDF011LL RSCAN0.CFDF011.UINT8[LL]
+#define RSCAN0CFDF011LH RSCAN0.CFDF011.UINT8[LH]
+#define RSCAN0CFDF011H RSCAN0.CFDF011.UINT16[H]
+#define RSCAN0CFDF011HL RSCAN0.CFDF011.UINT8[HL]
+#define RSCAN0CFDF011HH RSCAN0.CFDF011.UINT8[HH]
+#define RSCAN0CFDF111 RSCAN0.CFDF111.UINT32
+#define RSCAN0CFDF111L RSCAN0.CFDF111.UINT16[L]
+#define RSCAN0CFDF111LL RSCAN0.CFDF111.UINT8[LL]
+#define RSCAN0CFDF111LH RSCAN0.CFDF111.UINT8[LH]
+#define RSCAN0CFDF111H RSCAN0.CFDF111.UINT16[H]
+#define RSCAN0CFDF111HL RSCAN0.CFDF111.UINT8[HL]
+#define RSCAN0CFDF111HH RSCAN0.CFDF111.UINT8[HH]
+#define RSCAN0CFID12 RSCAN0.CFID12.UINT32
+#define RSCAN0CFID12L RSCAN0.CFID12.UINT16[L]
+#define RSCAN0CFID12LL RSCAN0.CFID12.UINT8[LL]
+#define RSCAN0CFID12LH RSCAN0.CFID12.UINT8[LH]
+#define RSCAN0CFID12H RSCAN0.CFID12.UINT16[H]
+#define RSCAN0CFID12HL RSCAN0.CFID12.UINT8[HL]
+#define RSCAN0CFID12HH RSCAN0.CFID12.UINT8[HH]
+#define RSCAN0CFPTR12 RSCAN0.CFPTR12.UINT32
+#define RSCAN0CFPTR12L RSCAN0.CFPTR12.UINT16[L]
+#define RSCAN0CFPTR12LL RSCAN0.CFPTR12.UINT8[LL]
+#define RSCAN0CFPTR12LH RSCAN0.CFPTR12.UINT8[LH]
+#define RSCAN0CFPTR12H RSCAN0.CFPTR12.UINT16[H]
+#define RSCAN0CFPTR12HL RSCAN0.CFPTR12.UINT8[HL]
+#define RSCAN0CFPTR12HH RSCAN0.CFPTR12.UINT8[HH]
+#define RSCAN0CFDF012 RSCAN0.CFDF012.UINT32
+#define RSCAN0CFDF012L RSCAN0.CFDF012.UINT16[L]
+#define RSCAN0CFDF012LL RSCAN0.CFDF012.UINT8[LL]
+#define RSCAN0CFDF012LH RSCAN0.CFDF012.UINT8[LH]
+#define RSCAN0CFDF012H RSCAN0.CFDF012.UINT16[H]
+#define RSCAN0CFDF012HL RSCAN0.CFDF012.UINT8[HL]
+#define RSCAN0CFDF012HH RSCAN0.CFDF012.UINT8[HH]
+#define RSCAN0CFDF112 RSCAN0.CFDF112.UINT32
+#define RSCAN0CFDF112L RSCAN0.CFDF112.UINT16[L]
+#define RSCAN0CFDF112LL RSCAN0.CFDF112.UINT8[LL]
+#define RSCAN0CFDF112LH RSCAN0.CFDF112.UINT8[LH]
+#define RSCAN0CFDF112H RSCAN0.CFDF112.UINT16[H]
+#define RSCAN0CFDF112HL RSCAN0.CFDF112.UINT8[HL]
+#define RSCAN0CFDF112HH RSCAN0.CFDF112.UINT8[HH]
+#define RSCAN0CFID13 RSCAN0.CFID13.UINT32
+#define RSCAN0CFID13L RSCAN0.CFID13.UINT16[L]
+#define RSCAN0CFID13LL RSCAN0.CFID13.UINT8[LL]
+#define RSCAN0CFID13LH RSCAN0.CFID13.UINT8[LH]
+#define RSCAN0CFID13H RSCAN0.CFID13.UINT16[H]
+#define RSCAN0CFID13HL RSCAN0.CFID13.UINT8[HL]
+#define RSCAN0CFID13HH RSCAN0.CFID13.UINT8[HH]
+#define RSCAN0CFPTR13 RSCAN0.CFPTR13.UINT32
+#define RSCAN0CFPTR13L RSCAN0.CFPTR13.UINT16[L]
+#define RSCAN0CFPTR13LL RSCAN0.CFPTR13.UINT8[LL]
+#define RSCAN0CFPTR13LH RSCAN0.CFPTR13.UINT8[LH]
+#define RSCAN0CFPTR13H RSCAN0.CFPTR13.UINT16[H]
+#define RSCAN0CFPTR13HL RSCAN0.CFPTR13.UINT8[HL]
+#define RSCAN0CFPTR13HH RSCAN0.CFPTR13.UINT8[HH]
+#define RSCAN0CFDF013 RSCAN0.CFDF013.UINT32
+#define RSCAN0CFDF013L RSCAN0.CFDF013.UINT16[L]
+#define RSCAN0CFDF013LL RSCAN0.CFDF013.UINT8[LL]
+#define RSCAN0CFDF013LH RSCAN0.CFDF013.UINT8[LH]
+#define RSCAN0CFDF013H RSCAN0.CFDF013.UINT16[H]
+#define RSCAN0CFDF013HL RSCAN0.CFDF013.UINT8[HL]
+#define RSCAN0CFDF013HH RSCAN0.CFDF013.UINT8[HH]
+#define RSCAN0CFDF113 RSCAN0.CFDF113.UINT32
+#define RSCAN0CFDF113L RSCAN0.CFDF113.UINT16[L]
+#define RSCAN0CFDF113LL RSCAN0.CFDF113.UINT8[LL]
+#define RSCAN0CFDF113LH RSCAN0.CFDF113.UINT8[LH]
+#define RSCAN0CFDF113H RSCAN0.CFDF113.UINT16[H]
+#define RSCAN0CFDF113HL RSCAN0.CFDF113.UINT8[HL]
+#define RSCAN0CFDF113HH RSCAN0.CFDF113.UINT8[HH]
+#define RSCAN0CFID14 RSCAN0.CFID14.UINT32
+#define RSCAN0CFID14L RSCAN0.CFID14.UINT16[L]
+#define RSCAN0CFID14LL RSCAN0.CFID14.UINT8[LL]
+#define RSCAN0CFID14LH RSCAN0.CFID14.UINT8[LH]
+#define RSCAN0CFID14H RSCAN0.CFID14.UINT16[H]
+#define RSCAN0CFID14HL RSCAN0.CFID14.UINT8[HL]
+#define RSCAN0CFID14HH RSCAN0.CFID14.UINT8[HH]
+#define RSCAN0CFPTR14 RSCAN0.CFPTR14.UINT32
+#define RSCAN0CFPTR14L RSCAN0.CFPTR14.UINT16[L]
+#define RSCAN0CFPTR14LL RSCAN0.CFPTR14.UINT8[LL]
+#define RSCAN0CFPTR14LH RSCAN0.CFPTR14.UINT8[LH]
+#define RSCAN0CFPTR14H RSCAN0.CFPTR14.UINT16[H]
+#define RSCAN0CFPTR14HL RSCAN0.CFPTR14.UINT8[HL]
+#define RSCAN0CFPTR14HH RSCAN0.CFPTR14.UINT8[HH]
+#define RSCAN0CFDF014 RSCAN0.CFDF014.UINT32
+#define RSCAN0CFDF014L RSCAN0.CFDF014.UINT16[L]
+#define RSCAN0CFDF014LL RSCAN0.CFDF014.UINT8[LL]
+#define RSCAN0CFDF014LH RSCAN0.CFDF014.UINT8[LH]
+#define RSCAN0CFDF014H RSCAN0.CFDF014.UINT16[H]
+#define RSCAN0CFDF014HL RSCAN0.CFDF014.UINT8[HL]
+#define RSCAN0CFDF014HH RSCAN0.CFDF014.UINT8[HH]
+#define RSCAN0CFDF114 RSCAN0.CFDF114.UINT32
+#define RSCAN0CFDF114L RSCAN0.CFDF114.UINT16[L]
+#define RSCAN0CFDF114LL RSCAN0.CFDF114.UINT8[LL]
+#define RSCAN0CFDF114LH RSCAN0.CFDF114.UINT8[LH]
+#define RSCAN0CFDF114H RSCAN0.CFDF114.UINT16[H]
+#define RSCAN0CFDF114HL RSCAN0.CFDF114.UINT8[HL]
+#define RSCAN0CFDF114HH RSCAN0.CFDF114.UINT8[HH]
+#define RSCAN0TMID0 RSCAN0.TMID0.UINT32
+#define RSCAN0TMID0L RSCAN0.TMID0.UINT16[L]
+#define RSCAN0TMID0LL RSCAN0.TMID0.UINT8[LL]
+#define RSCAN0TMID0LH RSCAN0.TMID0.UINT8[LH]
+#define RSCAN0TMID0H RSCAN0.TMID0.UINT16[H]
+#define RSCAN0TMID0HL RSCAN0.TMID0.UINT8[HL]
+#define RSCAN0TMID0HH RSCAN0.TMID0.UINT8[HH]
+#define RSCAN0TMPTR0 RSCAN0.TMPTR0.UINT32
+#define RSCAN0TMPTR0L RSCAN0.TMPTR0.UINT16[L]
+#define RSCAN0TMPTR0LL RSCAN0.TMPTR0.UINT8[LL]
+#define RSCAN0TMPTR0LH RSCAN0.TMPTR0.UINT8[LH]
+#define RSCAN0TMPTR0H RSCAN0.TMPTR0.UINT16[H]
+#define RSCAN0TMPTR0HL RSCAN0.TMPTR0.UINT8[HL]
+#define RSCAN0TMPTR0HH RSCAN0.TMPTR0.UINT8[HH]
+#define RSCAN0TMDF00 RSCAN0.TMDF00.UINT32
+#define RSCAN0TMDF00L RSCAN0.TMDF00.UINT16[L]
+#define RSCAN0TMDF00LL RSCAN0.TMDF00.UINT8[LL]
+#define RSCAN0TMDF00LH RSCAN0.TMDF00.UINT8[LH]
+#define RSCAN0TMDF00H RSCAN0.TMDF00.UINT16[H]
+#define RSCAN0TMDF00HL RSCAN0.TMDF00.UINT8[HL]
+#define RSCAN0TMDF00HH RSCAN0.TMDF00.UINT8[HH]
+#define RSCAN0TMDF10 RSCAN0.TMDF10.UINT32
+#define RSCAN0TMDF10L RSCAN0.TMDF10.UINT16[L]
+#define RSCAN0TMDF10LL RSCAN0.TMDF10.UINT8[LL]
+#define RSCAN0TMDF10LH RSCAN0.TMDF10.UINT8[LH]
+#define RSCAN0TMDF10H RSCAN0.TMDF10.UINT16[H]
+#define RSCAN0TMDF10HL RSCAN0.TMDF10.UINT8[HL]
+#define RSCAN0TMDF10HH RSCAN0.TMDF10.UINT8[HH]
+#define RSCAN0TMID1 RSCAN0.TMID1.UINT32
+#define RSCAN0TMID1L RSCAN0.TMID1.UINT16[L]
+#define RSCAN0TMID1LL RSCAN0.TMID1.UINT8[LL]
+#define RSCAN0TMID1LH RSCAN0.TMID1.UINT8[LH]
+#define RSCAN0TMID1H RSCAN0.TMID1.UINT16[H]
+#define RSCAN0TMID1HL RSCAN0.TMID1.UINT8[HL]
+#define RSCAN0TMID1HH RSCAN0.TMID1.UINT8[HH]
+#define RSCAN0TMPTR1 RSCAN0.TMPTR1.UINT32
+#define RSCAN0TMPTR1L RSCAN0.TMPTR1.UINT16[L]
+#define RSCAN0TMPTR1LL RSCAN0.TMPTR1.UINT8[LL]
+#define RSCAN0TMPTR1LH RSCAN0.TMPTR1.UINT8[LH]
+#define RSCAN0TMPTR1H RSCAN0.TMPTR1.UINT16[H]
+#define RSCAN0TMPTR1HL RSCAN0.TMPTR1.UINT8[HL]
+#define RSCAN0TMPTR1HH RSCAN0.TMPTR1.UINT8[HH]
+#define RSCAN0TMDF01 RSCAN0.TMDF01.UINT32
+#define RSCAN0TMDF01L RSCAN0.TMDF01.UINT16[L]
+#define RSCAN0TMDF01LL RSCAN0.TMDF01.UINT8[LL]
+#define RSCAN0TMDF01LH RSCAN0.TMDF01.UINT8[LH]
+#define RSCAN0TMDF01H RSCAN0.TMDF01.UINT16[H]
+#define RSCAN0TMDF01HL RSCAN0.TMDF01.UINT8[HL]
+#define RSCAN0TMDF01HH RSCAN0.TMDF01.UINT8[HH]
+#define RSCAN0TMDF11 RSCAN0.TMDF11.UINT32
+#define RSCAN0TMDF11L RSCAN0.TMDF11.UINT16[L]
+#define RSCAN0TMDF11LL RSCAN0.TMDF11.UINT8[LL]
+#define RSCAN0TMDF11LH RSCAN0.TMDF11.UINT8[LH]
+#define RSCAN0TMDF11H RSCAN0.TMDF11.UINT16[H]
+#define RSCAN0TMDF11HL RSCAN0.TMDF11.UINT8[HL]
+#define RSCAN0TMDF11HH RSCAN0.TMDF11.UINT8[HH]
+#define RSCAN0TMID2 RSCAN0.TMID2.UINT32
+#define RSCAN0TMID2L RSCAN0.TMID2.UINT16[L]
+#define RSCAN0TMID2LL RSCAN0.TMID2.UINT8[LL]
+#define RSCAN0TMID2LH RSCAN0.TMID2.UINT8[LH]
+#define RSCAN0TMID2H RSCAN0.TMID2.UINT16[H]
+#define RSCAN0TMID2HL RSCAN0.TMID2.UINT8[HL]
+#define RSCAN0TMID2HH RSCAN0.TMID2.UINT8[HH]
+#define RSCAN0TMPTR2 RSCAN0.TMPTR2.UINT32
+#define RSCAN0TMPTR2L RSCAN0.TMPTR2.UINT16[L]
+#define RSCAN0TMPTR2LL RSCAN0.TMPTR2.UINT8[LL]
+#define RSCAN0TMPTR2LH RSCAN0.TMPTR2.UINT8[LH]
+#define RSCAN0TMPTR2H RSCAN0.TMPTR2.UINT16[H]
+#define RSCAN0TMPTR2HL RSCAN0.TMPTR2.UINT8[HL]
+#define RSCAN0TMPTR2HH RSCAN0.TMPTR2.UINT8[HH]
+#define RSCAN0TMDF02 RSCAN0.TMDF02.UINT32
+#define RSCAN0TMDF02L RSCAN0.TMDF02.UINT16[L]
+#define RSCAN0TMDF02LL RSCAN0.TMDF02.UINT8[LL]
+#define RSCAN0TMDF02LH RSCAN0.TMDF02.UINT8[LH]
+#define RSCAN0TMDF02H RSCAN0.TMDF02.UINT16[H]
+#define RSCAN0TMDF02HL RSCAN0.TMDF02.UINT8[HL]
+#define RSCAN0TMDF02HH RSCAN0.TMDF02.UINT8[HH]
+#define RSCAN0TMDF12 RSCAN0.TMDF12.UINT32
+#define RSCAN0TMDF12L RSCAN0.TMDF12.UINT16[L]
+#define RSCAN0TMDF12LL RSCAN0.TMDF12.UINT8[LL]
+#define RSCAN0TMDF12LH RSCAN0.TMDF12.UINT8[LH]
+#define RSCAN0TMDF12H RSCAN0.TMDF12.UINT16[H]
+#define RSCAN0TMDF12HL RSCAN0.TMDF12.UINT8[HL]
+#define RSCAN0TMDF12HH RSCAN0.TMDF12.UINT8[HH]
+#define RSCAN0TMID3 RSCAN0.TMID3.UINT32
+#define RSCAN0TMID3L RSCAN0.TMID3.UINT16[L]
+#define RSCAN0TMID3LL RSCAN0.TMID3.UINT8[LL]
+#define RSCAN0TMID3LH RSCAN0.TMID3.UINT8[LH]
+#define RSCAN0TMID3H RSCAN0.TMID3.UINT16[H]
+#define RSCAN0TMID3HL RSCAN0.TMID3.UINT8[HL]
+#define RSCAN0TMID3HH RSCAN0.TMID3.UINT8[HH]
+#define RSCAN0TMPTR3 RSCAN0.TMPTR3.UINT32
+#define RSCAN0TMPTR3L RSCAN0.TMPTR3.UINT16[L]
+#define RSCAN0TMPTR3LL RSCAN0.TMPTR3.UINT8[LL]
+#define RSCAN0TMPTR3LH RSCAN0.TMPTR3.UINT8[LH]
+#define RSCAN0TMPTR3H RSCAN0.TMPTR3.UINT16[H]
+#define RSCAN0TMPTR3HL RSCAN0.TMPTR3.UINT8[HL]
+#define RSCAN0TMPTR3HH RSCAN0.TMPTR3.UINT8[HH]
+#define RSCAN0TMDF03 RSCAN0.TMDF03.UINT32
+#define RSCAN0TMDF03L RSCAN0.TMDF03.UINT16[L]
+#define RSCAN0TMDF03LL RSCAN0.TMDF03.UINT8[LL]
+#define RSCAN0TMDF03LH RSCAN0.TMDF03.UINT8[LH]
+#define RSCAN0TMDF03H RSCAN0.TMDF03.UINT16[H]
+#define RSCAN0TMDF03HL RSCAN0.TMDF03.UINT8[HL]
+#define RSCAN0TMDF03HH RSCAN0.TMDF03.UINT8[HH]
+#define RSCAN0TMDF13 RSCAN0.TMDF13.UINT32
+#define RSCAN0TMDF13L RSCAN0.TMDF13.UINT16[L]
+#define RSCAN0TMDF13LL RSCAN0.TMDF13.UINT8[LL]
+#define RSCAN0TMDF13LH RSCAN0.TMDF13.UINT8[LH]
+#define RSCAN0TMDF13H RSCAN0.TMDF13.UINT16[H]
+#define RSCAN0TMDF13HL RSCAN0.TMDF13.UINT8[HL]
+#define RSCAN0TMDF13HH RSCAN0.TMDF13.UINT8[HH]
+#define RSCAN0TMID4 RSCAN0.TMID4.UINT32
+#define RSCAN0TMID4L RSCAN0.TMID4.UINT16[L]
+#define RSCAN0TMID4LL RSCAN0.TMID4.UINT8[LL]
+#define RSCAN0TMID4LH RSCAN0.TMID4.UINT8[LH]
+#define RSCAN0TMID4H RSCAN0.TMID4.UINT16[H]
+#define RSCAN0TMID4HL RSCAN0.TMID4.UINT8[HL]
+#define RSCAN0TMID4HH RSCAN0.TMID4.UINT8[HH]
+#define RSCAN0TMPTR4 RSCAN0.TMPTR4.UINT32
+#define RSCAN0TMPTR4L RSCAN0.TMPTR4.UINT16[L]
+#define RSCAN0TMPTR4LL RSCAN0.TMPTR4.UINT8[LL]
+#define RSCAN0TMPTR4LH RSCAN0.TMPTR4.UINT8[LH]
+#define RSCAN0TMPTR4H RSCAN0.TMPTR4.UINT16[H]
+#define RSCAN0TMPTR4HL RSCAN0.TMPTR4.UINT8[HL]
+#define RSCAN0TMPTR4HH RSCAN0.TMPTR4.UINT8[HH]
+#define RSCAN0TMDF04 RSCAN0.TMDF04.UINT32
+#define RSCAN0TMDF04L RSCAN0.TMDF04.UINT16[L]
+#define RSCAN0TMDF04LL RSCAN0.TMDF04.UINT8[LL]
+#define RSCAN0TMDF04LH RSCAN0.TMDF04.UINT8[LH]
+#define RSCAN0TMDF04H RSCAN0.TMDF04.UINT16[H]
+#define RSCAN0TMDF04HL RSCAN0.TMDF04.UINT8[HL]
+#define RSCAN0TMDF04HH RSCAN0.TMDF04.UINT8[HH]
+#define RSCAN0TMDF14 RSCAN0.TMDF14.UINT32
+#define RSCAN0TMDF14L RSCAN0.TMDF14.UINT16[L]
+#define RSCAN0TMDF14LL RSCAN0.TMDF14.UINT8[LL]
+#define RSCAN0TMDF14LH RSCAN0.TMDF14.UINT8[LH]
+#define RSCAN0TMDF14H RSCAN0.TMDF14.UINT16[H]
+#define RSCAN0TMDF14HL RSCAN0.TMDF14.UINT8[HL]
+#define RSCAN0TMDF14HH RSCAN0.TMDF14.UINT8[HH]
+#define RSCAN0TMID5 RSCAN0.TMID5.UINT32
+#define RSCAN0TMID5L RSCAN0.TMID5.UINT16[L]
+#define RSCAN0TMID5LL RSCAN0.TMID5.UINT8[LL]
+#define RSCAN0TMID5LH RSCAN0.TMID5.UINT8[LH]
+#define RSCAN0TMID5H RSCAN0.TMID5.UINT16[H]
+#define RSCAN0TMID5HL RSCAN0.TMID5.UINT8[HL]
+#define RSCAN0TMID5HH RSCAN0.TMID5.UINT8[HH]
+#define RSCAN0TMPTR5 RSCAN0.TMPTR5.UINT32
+#define RSCAN0TMPTR5L RSCAN0.TMPTR5.UINT16[L]
+#define RSCAN0TMPTR5LL RSCAN0.TMPTR5.UINT8[LL]
+#define RSCAN0TMPTR5LH RSCAN0.TMPTR5.UINT8[LH]
+#define RSCAN0TMPTR5H RSCAN0.TMPTR5.UINT16[H]
+#define RSCAN0TMPTR5HL RSCAN0.TMPTR5.UINT8[HL]
+#define RSCAN0TMPTR5HH RSCAN0.TMPTR5.UINT8[HH]
+#define RSCAN0TMDF05 RSCAN0.TMDF05.UINT32
+#define RSCAN0TMDF05L RSCAN0.TMDF05.UINT16[L]
+#define RSCAN0TMDF05LL RSCAN0.TMDF05.UINT8[LL]
+#define RSCAN0TMDF05LH RSCAN0.TMDF05.UINT8[LH]
+#define RSCAN0TMDF05H RSCAN0.TMDF05.UINT16[H]
+#define RSCAN0TMDF05HL RSCAN0.TMDF05.UINT8[HL]
+#define RSCAN0TMDF05HH RSCAN0.TMDF05.UINT8[HH]
+#define RSCAN0TMDF15 RSCAN0.TMDF15.UINT32
+#define RSCAN0TMDF15L RSCAN0.TMDF15.UINT16[L]
+#define RSCAN0TMDF15LL RSCAN0.TMDF15.UINT8[LL]
+#define RSCAN0TMDF15LH RSCAN0.TMDF15.UINT8[LH]
+#define RSCAN0TMDF15H RSCAN0.TMDF15.UINT16[H]
+#define RSCAN0TMDF15HL RSCAN0.TMDF15.UINT8[HL]
+#define RSCAN0TMDF15HH RSCAN0.TMDF15.UINT8[HH]
+#define RSCAN0TMID6 RSCAN0.TMID6.UINT32
+#define RSCAN0TMID6L RSCAN0.TMID6.UINT16[L]
+#define RSCAN0TMID6LL RSCAN0.TMID6.UINT8[LL]
+#define RSCAN0TMID6LH RSCAN0.TMID6.UINT8[LH]
+#define RSCAN0TMID6H RSCAN0.TMID6.UINT16[H]
+#define RSCAN0TMID6HL RSCAN0.TMID6.UINT8[HL]
+#define RSCAN0TMID6HH RSCAN0.TMID6.UINT8[HH]
+#define RSCAN0TMPTR6 RSCAN0.TMPTR6.UINT32
+#define RSCAN0TMPTR6L RSCAN0.TMPTR6.UINT16[L]
+#define RSCAN0TMPTR6LL RSCAN0.TMPTR6.UINT8[LL]
+#define RSCAN0TMPTR6LH RSCAN0.TMPTR6.UINT8[LH]
+#define RSCAN0TMPTR6H RSCAN0.TMPTR6.UINT16[H]
+#define RSCAN0TMPTR6HL RSCAN0.TMPTR6.UINT8[HL]
+#define RSCAN0TMPTR6HH RSCAN0.TMPTR6.UINT8[HH]
+#define RSCAN0TMDF06 RSCAN0.TMDF06.UINT32
+#define RSCAN0TMDF06L RSCAN0.TMDF06.UINT16[L]
+#define RSCAN0TMDF06LL RSCAN0.TMDF06.UINT8[LL]
+#define RSCAN0TMDF06LH RSCAN0.TMDF06.UINT8[LH]
+#define RSCAN0TMDF06H RSCAN0.TMDF06.UINT16[H]
+#define RSCAN0TMDF06HL RSCAN0.TMDF06.UINT8[HL]
+#define RSCAN0TMDF06HH RSCAN0.TMDF06.UINT8[HH]
+#define RSCAN0TMDF16 RSCAN0.TMDF16.UINT32
+#define RSCAN0TMDF16L RSCAN0.TMDF16.UINT16[L]
+#define RSCAN0TMDF16LL RSCAN0.TMDF16.UINT8[LL]
+#define RSCAN0TMDF16LH RSCAN0.TMDF16.UINT8[LH]
+#define RSCAN0TMDF16H RSCAN0.TMDF16.UINT16[H]
+#define RSCAN0TMDF16HL RSCAN0.TMDF16.UINT8[HL]
+#define RSCAN0TMDF16HH RSCAN0.TMDF16.UINT8[HH]
+#define RSCAN0TMID7 RSCAN0.TMID7.UINT32
+#define RSCAN0TMID7L RSCAN0.TMID7.UINT16[L]
+#define RSCAN0TMID7LL RSCAN0.TMID7.UINT8[LL]
+#define RSCAN0TMID7LH RSCAN0.TMID7.UINT8[LH]
+#define RSCAN0TMID7H RSCAN0.TMID7.UINT16[H]
+#define RSCAN0TMID7HL RSCAN0.TMID7.UINT8[HL]
+#define RSCAN0TMID7HH RSCAN0.TMID7.UINT8[HH]
+#define RSCAN0TMPTR7 RSCAN0.TMPTR7.UINT32
+#define RSCAN0TMPTR7L RSCAN0.TMPTR7.UINT16[L]
+#define RSCAN0TMPTR7LL RSCAN0.TMPTR7.UINT8[LL]
+#define RSCAN0TMPTR7LH RSCAN0.TMPTR7.UINT8[LH]
+#define RSCAN0TMPTR7H RSCAN0.TMPTR7.UINT16[H]
+#define RSCAN0TMPTR7HL RSCAN0.TMPTR7.UINT8[HL]
+#define RSCAN0TMPTR7HH RSCAN0.TMPTR7.UINT8[HH]
+#define RSCAN0TMDF07 RSCAN0.TMDF07.UINT32
+#define RSCAN0TMDF07L RSCAN0.TMDF07.UINT16[L]
+#define RSCAN0TMDF07LL RSCAN0.TMDF07.UINT8[LL]
+#define RSCAN0TMDF07LH RSCAN0.TMDF07.UINT8[LH]
+#define RSCAN0TMDF07H RSCAN0.TMDF07.UINT16[H]
+#define RSCAN0TMDF07HL RSCAN0.TMDF07.UINT8[HL]
+#define RSCAN0TMDF07HH RSCAN0.TMDF07.UINT8[HH]
+#define RSCAN0TMDF17 RSCAN0.TMDF17.UINT32
+#define RSCAN0TMDF17L RSCAN0.TMDF17.UINT16[L]
+#define RSCAN0TMDF17LL RSCAN0.TMDF17.UINT8[LL]
+#define RSCAN0TMDF17LH RSCAN0.TMDF17.UINT8[LH]
+#define RSCAN0TMDF17H RSCAN0.TMDF17.UINT16[H]
+#define RSCAN0TMDF17HL RSCAN0.TMDF17.UINT8[HL]
+#define RSCAN0TMDF17HH RSCAN0.TMDF17.UINT8[HH]
+#define RSCAN0TMID8 RSCAN0.TMID8.UINT32
+#define RSCAN0TMID8L RSCAN0.TMID8.UINT16[L]
+#define RSCAN0TMID8LL RSCAN0.TMID8.UINT8[LL]
+#define RSCAN0TMID8LH RSCAN0.TMID8.UINT8[LH]
+#define RSCAN0TMID8H RSCAN0.TMID8.UINT16[H]
+#define RSCAN0TMID8HL RSCAN0.TMID8.UINT8[HL]
+#define RSCAN0TMID8HH RSCAN0.TMID8.UINT8[HH]
+#define RSCAN0TMPTR8 RSCAN0.TMPTR8.UINT32
+#define RSCAN0TMPTR8L RSCAN0.TMPTR8.UINT16[L]
+#define RSCAN0TMPTR8LL RSCAN0.TMPTR8.UINT8[LL]
+#define RSCAN0TMPTR8LH RSCAN0.TMPTR8.UINT8[LH]
+#define RSCAN0TMPTR8H RSCAN0.TMPTR8.UINT16[H]
+#define RSCAN0TMPTR8HL RSCAN0.TMPTR8.UINT8[HL]
+#define RSCAN0TMPTR8HH RSCAN0.TMPTR8.UINT8[HH]
+#define RSCAN0TMDF08 RSCAN0.TMDF08.UINT32
+#define RSCAN0TMDF08L RSCAN0.TMDF08.UINT16[L]
+#define RSCAN0TMDF08LL RSCAN0.TMDF08.UINT8[LL]
+#define RSCAN0TMDF08LH RSCAN0.TMDF08.UINT8[LH]
+#define RSCAN0TMDF08H RSCAN0.TMDF08.UINT16[H]
+#define RSCAN0TMDF08HL RSCAN0.TMDF08.UINT8[HL]
+#define RSCAN0TMDF08HH RSCAN0.TMDF08.UINT8[HH]
+#define RSCAN0TMDF18 RSCAN0.TMDF18.UINT32
+#define RSCAN0TMDF18L RSCAN0.TMDF18.UINT16[L]
+#define RSCAN0TMDF18LL RSCAN0.TMDF18.UINT8[LL]
+#define RSCAN0TMDF18LH RSCAN0.TMDF18.UINT8[LH]
+#define RSCAN0TMDF18H RSCAN0.TMDF18.UINT16[H]
+#define RSCAN0TMDF18HL RSCAN0.TMDF18.UINT8[HL]
+#define RSCAN0TMDF18HH RSCAN0.TMDF18.UINT8[HH]
+#define RSCAN0TMID9 RSCAN0.TMID9.UINT32
+#define RSCAN0TMID9L RSCAN0.TMID9.UINT16[L]
+#define RSCAN0TMID9LL RSCAN0.TMID9.UINT8[LL]
+#define RSCAN0TMID9LH RSCAN0.TMID9.UINT8[LH]
+#define RSCAN0TMID9H RSCAN0.TMID9.UINT16[H]
+#define RSCAN0TMID9HL RSCAN0.TMID9.UINT8[HL]
+#define RSCAN0TMID9HH RSCAN0.TMID9.UINT8[HH]
+#define RSCAN0TMPTR9 RSCAN0.TMPTR9.UINT32
+#define RSCAN0TMPTR9L RSCAN0.TMPTR9.UINT16[L]
+#define RSCAN0TMPTR9LL RSCAN0.TMPTR9.UINT8[LL]
+#define RSCAN0TMPTR9LH RSCAN0.TMPTR9.UINT8[LH]
+#define RSCAN0TMPTR9H RSCAN0.TMPTR9.UINT16[H]
+#define RSCAN0TMPTR9HL RSCAN0.TMPTR9.UINT8[HL]
+#define RSCAN0TMPTR9HH RSCAN0.TMPTR9.UINT8[HH]
+#define RSCAN0TMDF09 RSCAN0.TMDF09.UINT32
+#define RSCAN0TMDF09L RSCAN0.TMDF09.UINT16[L]
+#define RSCAN0TMDF09LL RSCAN0.TMDF09.UINT8[LL]
+#define RSCAN0TMDF09LH RSCAN0.TMDF09.UINT8[LH]
+#define RSCAN0TMDF09H RSCAN0.TMDF09.UINT16[H]
+#define RSCAN0TMDF09HL RSCAN0.TMDF09.UINT8[HL]
+#define RSCAN0TMDF09HH RSCAN0.TMDF09.UINT8[HH]
+#define RSCAN0TMDF19 RSCAN0.TMDF19.UINT32
+#define RSCAN0TMDF19L RSCAN0.TMDF19.UINT16[L]
+#define RSCAN0TMDF19LL RSCAN0.TMDF19.UINT8[LL]
+#define RSCAN0TMDF19LH RSCAN0.TMDF19.UINT8[LH]
+#define RSCAN0TMDF19H RSCAN0.TMDF19.UINT16[H]
+#define RSCAN0TMDF19HL RSCAN0.TMDF19.UINT8[HL]
+#define RSCAN0TMDF19HH RSCAN0.TMDF19.UINT8[HH]
+#define RSCAN0TMID10 RSCAN0.TMID10.UINT32
+#define RSCAN0TMID10L RSCAN0.TMID10.UINT16[L]
+#define RSCAN0TMID10LL RSCAN0.TMID10.UINT8[LL]
+#define RSCAN0TMID10LH RSCAN0.TMID10.UINT8[LH]
+#define RSCAN0TMID10H RSCAN0.TMID10.UINT16[H]
+#define RSCAN0TMID10HL RSCAN0.TMID10.UINT8[HL]
+#define RSCAN0TMID10HH RSCAN0.TMID10.UINT8[HH]
+#define RSCAN0TMPTR10 RSCAN0.TMPTR10.UINT32
+#define RSCAN0TMPTR10L RSCAN0.TMPTR10.UINT16[L]
+#define RSCAN0TMPTR10LL RSCAN0.TMPTR10.UINT8[LL]
+#define RSCAN0TMPTR10LH RSCAN0.TMPTR10.UINT8[LH]
+#define RSCAN0TMPTR10H RSCAN0.TMPTR10.UINT16[H]
+#define RSCAN0TMPTR10HL RSCAN0.TMPTR10.UINT8[HL]
+#define RSCAN0TMPTR10HH RSCAN0.TMPTR10.UINT8[HH]
+#define RSCAN0TMDF010 RSCAN0.TMDF010.UINT32
+#define RSCAN0TMDF010L RSCAN0.TMDF010.UINT16[L]
+#define RSCAN0TMDF010LL RSCAN0.TMDF010.UINT8[LL]
+#define RSCAN0TMDF010LH RSCAN0.TMDF010.UINT8[LH]
+#define RSCAN0TMDF010H RSCAN0.TMDF010.UINT16[H]
+#define RSCAN0TMDF010HL RSCAN0.TMDF010.UINT8[HL]
+#define RSCAN0TMDF010HH RSCAN0.TMDF010.UINT8[HH]
+#define RSCAN0TMDF110 RSCAN0.TMDF110.UINT32
+#define RSCAN0TMDF110L RSCAN0.TMDF110.UINT16[L]
+#define RSCAN0TMDF110LL RSCAN0.TMDF110.UINT8[LL]
+#define RSCAN0TMDF110LH RSCAN0.TMDF110.UINT8[LH]
+#define RSCAN0TMDF110H RSCAN0.TMDF110.UINT16[H]
+#define RSCAN0TMDF110HL RSCAN0.TMDF110.UINT8[HL]
+#define RSCAN0TMDF110HH RSCAN0.TMDF110.UINT8[HH]
+#define RSCAN0TMID11 RSCAN0.TMID11.UINT32
+#define RSCAN0TMID11L RSCAN0.TMID11.UINT16[L]
+#define RSCAN0TMID11LL RSCAN0.TMID11.UINT8[LL]
+#define RSCAN0TMID11LH RSCAN0.TMID11.UINT8[LH]
+#define RSCAN0TMID11H RSCAN0.TMID11.UINT16[H]
+#define RSCAN0TMID11HL RSCAN0.TMID11.UINT8[HL]
+#define RSCAN0TMID11HH RSCAN0.TMID11.UINT8[HH]
+#define RSCAN0TMPTR11 RSCAN0.TMPTR11.UINT32
+#define RSCAN0TMPTR11L RSCAN0.TMPTR11.UINT16[L]
+#define RSCAN0TMPTR11LL RSCAN0.TMPTR11.UINT8[LL]
+#define RSCAN0TMPTR11LH RSCAN0.TMPTR11.UINT8[LH]
+#define RSCAN0TMPTR11H RSCAN0.TMPTR11.UINT16[H]
+#define RSCAN0TMPTR11HL RSCAN0.TMPTR11.UINT8[HL]
+#define RSCAN0TMPTR11HH RSCAN0.TMPTR11.UINT8[HH]
+#define RSCAN0TMDF011 RSCAN0.TMDF011.UINT32
+#define RSCAN0TMDF011L RSCAN0.TMDF011.UINT16[L]
+#define RSCAN0TMDF011LL RSCAN0.TMDF011.UINT8[LL]
+#define RSCAN0TMDF011LH RSCAN0.TMDF011.UINT8[LH]
+#define RSCAN0TMDF011H RSCAN0.TMDF011.UINT16[H]
+#define RSCAN0TMDF011HL RSCAN0.TMDF011.UINT8[HL]
+#define RSCAN0TMDF011HH RSCAN0.TMDF011.UINT8[HH]
+#define RSCAN0TMDF111 RSCAN0.TMDF111.UINT32
+#define RSCAN0TMDF111L RSCAN0.TMDF111.UINT16[L]
+#define RSCAN0TMDF111LL RSCAN0.TMDF111.UINT8[LL]
+#define RSCAN0TMDF111LH RSCAN0.TMDF111.UINT8[LH]
+#define RSCAN0TMDF111H RSCAN0.TMDF111.UINT16[H]
+#define RSCAN0TMDF111HL RSCAN0.TMDF111.UINT8[HL]
+#define RSCAN0TMDF111HH RSCAN0.TMDF111.UINT8[HH]
+#define RSCAN0TMID12 RSCAN0.TMID12.UINT32
+#define RSCAN0TMID12L RSCAN0.TMID12.UINT16[L]
+#define RSCAN0TMID12LL RSCAN0.TMID12.UINT8[LL]
+#define RSCAN0TMID12LH RSCAN0.TMID12.UINT8[LH]
+#define RSCAN0TMID12H RSCAN0.TMID12.UINT16[H]
+#define RSCAN0TMID12HL RSCAN0.TMID12.UINT8[HL]
+#define RSCAN0TMID12HH RSCAN0.TMID12.UINT8[HH]
+#define RSCAN0TMPTR12 RSCAN0.TMPTR12.UINT32
+#define RSCAN0TMPTR12L RSCAN0.TMPTR12.UINT16[L]
+#define RSCAN0TMPTR12LL RSCAN0.TMPTR12.UINT8[LL]
+#define RSCAN0TMPTR12LH RSCAN0.TMPTR12.UINT8[LH]
+#define RSCAN0TMPTR12H RSCAN0.TMPTR12.UINT16[H]
+#define RSCAN0TMPTR12HL RSCAN0.TMPTR12.UINT8[HL]
+#define RSCAN0TMPTR12HH RSCAN0.TMPTR12.UINT8[HH]
+#define RSCAN0TMDF012 RSCAN0.TMDF012.UINT32
+#define RSCAN0TMDF012L RSCAN0.TMDF012.UINT16[L]
+#define RSCAN0TMDF012LL RSCAN0.TMDF012.UINT8[LL]
+#define RSCAN0TMDF012LH RSCAN0.TMDF012.UINT8[LH]
+#define RSCAN0TMDF012H RSCAN0.TMDF012.UINT16[H]
+#define RSCAN0TMDF012HL RSCAN0.TMDF012.UINT8[HL]
+#define RSCAN0TMDF012HH RSCAN0.TMDF012.UINT8[HH]
+#define RSCAN0TMDF112 RSCAN0.TMDF112.UINT32
+#define RSCAN0TMDF112L RSCAN0.TMDF112.UINT16[L]
+#define RSCAN0TMDF112LL RSCAN0.TMDF112.UINT8[LL]
+#define RSCAN0TMDF112LH RSCAN0.TMDF112.UINT8[LH]
+#define RSCAN0TMDF112H RSCAN0.TMDF112.UINT16[H]
+#define RSCAN0TMDF112HL RSCAN0.TMDF112.UINT8[HL]
+#define RSCAN0TMDF112HH RSCAN0.TMDF112.UINT8[HH]
+#define RSCAN0TMID13 RSCAN0.TMID13.UINT32
+#define RSCAN0TMID13L RSCAN0.TMID13.UINT16[L]
+#define RSCAN0TMID13LL RSCAN0.TMID13.UINT8[LL]
+#define RSCAN0TMID13LH RSCAN0.TMID13.UINT8[LH]
+#define RSCAN0TMID13H RSCAN0.TMID13.UINT16[H]
+#define RSCAN0TMID13HL RSCAN0.TMID13.UINT8[HL]
+#define RSCAN0TMID13HH RSCAN0.TMID13.UINT8[HH]
+#define RSCAN0TMPTR13 RSCAN0.TMPTR13.UINT32
+#define RSCAN0TMPTR13L RSCAN0.TMPTR13.UINT16[L]
+#define RSCAN0TMPTR13LL RSCAN0.TMPTR13.UINT8[LL]
+#define RSCAN0TMPTR13LH RSCAN0.TMPTR13.UINT8[LH]
+#define RSCAN0TMPTR13H RSCAN0.TMPTR13.UINT16[H]
+#define RSCAN0TMPTR13HL RSCAN0.TMPTR13.UINT8[HL]
+#define RSCAN0TMPTR13HH RSCAN0.TMPTR13.UINT8[HH]
+#define RSCAN0TMDF013 RSCAN0.TMDF013.UINT32
+#define RSCAN0TMDF013L RSCAN0.TMDF013.UINT16[L]
+#define RSCAN0TMDF013LL RSCAN0.TMDF013.UINT8[LL]
+#define RSCAN0TMDF013LH RSCAN0.TMDF013.UINT8[LH]
+#define RSCAN0TMDF013H RSCAN0.TMDF013.UINT16[H]
+#define RSCAN0TMDF013HL RSCAN0.TMDF013.UINT8[HL]
+#define RSCAN0TMDF013HH RSCAN0.TMDF013.UINT8[HH]
+#define RSCAN0TMDF113 RSCAN0.TMDF113.UINT32
+#define RSCAN0TMDF113L RSCAN0.TMDF113.UINT16[L]
+#define RSCAN0TMDF113LL RSCAN0.TMDF113.UINT8[LL]
+#define RSCAN0TMDF113LH RSCAN0.TMDF113.UINT8[LH]
+#define RSCAN0TMDF113H RSCAN0.TMDF113.UINT16[H]
+#define RSCAN0TMDF113HL RSCAN0.TMDF113.UINT8[HL]
+#define RSCAN0TMDF113HH RSCAN0.TMDF113.UINT8[HH]
+#define RSCAN0TMID14 RSCAN0.TMID14.UINT32
+#define RSCAN0TMID14L RSCAN0.TMID14.UINT16[L]
+#define RSCAN0TMID14LL RSCAN0.TMID14.UINT8[LL]
+#define RSCAN0TMID14LH RSCAN0.TMID14.UINT8[LH]
+#define RSCAN0TMID14H RSCAN0.TMID14.UINT16[H]
+#define RSCAN0TMID14HL RSCAN0.TMID14.UINT8[HL]
+#define RSCAN0TMID14HH RSCAN0.TMID14.UINT8[HH]
+#define RSCAN0TMPTR14 RSCAN0.TMPTR14.UINT32
+#define RSCAN0TMPTR14L RSCAN0.TMPTR14.UINT16[L]
+#define RSCAN0TMPTR14LL RSCAN0.TMPTR14.UINT8[LL]
+#define RSCAN0TMPTR14LH RSCAN0.TMPTR14.UINT8[LH]
+#define RSCAN0TMPTR14H RSCAN0.TMPTR14.UINT16[H]
+#define RSCAN0TMPTR14HL RSCAN0.TMPTR14.UINT8[HL]
+#define RSCAN0TMPTR14HH RSCAN0.TMPTR14.UINT8[HH]
+#define RSCAN0TMDF014 RSCAN0.TMDF014.UINT32
+#define RSCAN0TMDF014L RSCAN0.TMDF014.UINT16[L]
+#define RSCAN0TMDF014LL RSCAN0.TMDF014.UINT8[LL]
+#define RSCAN0TMDF014LH RSCAN0.TMDF014.UINT8[LH]
+#define RSCAN0TMDF014H RSCAN0.TMDF014.UINT16[H]
+#define RSCAN0TMDF014HL RSCAN0.TMDF014.UINT8[HL]
+#define RSCAN0TMDF014HH RSCAN0.TMDF014.UINT8[HH]
+#define RSCAN0TMDF114 RSCAN0.TMDF114.UINT32
+#define RSCAN0TMDF114L RSCAN0.TMDF114.UINT16[L]
+#define RSCAN0TMDF114LL RSCAN0.TMDF114.UINT8[LL]
+#define RSCAN0TMDF114LH RSCAN0.TMDF114.UINT8[LH]
+#define RSCAN0TMDF114H RSCAN0.TMDF114.UINT16[H]
+#define RSCAN0TMDF114HL RSCAN0.TMDF114.UINT8[HL]
+#define RSCAN0TMDF114HH RSCAN0.TMDF114.UINT8[HH]
+#define RSCAN0TMID15 RSCAN0.TMID15.UINT32
+#define RSCAN0TMID15L RSCAN0.TMID15.UINT16[L]
+#define RSCAN0TMID15LL RSCAN0.TMID15.UINT8[LL]
+#define RSCAN0TMID15LH RSCAN0.TMID15.UINT8[LH]
+#define RSCAN0TMID15H RSCAN0.TMID15.UINT16[H]
+#define RSCAN0TMID15HL RSCAN0.TMID15.UINT8[HL]
+#define RSCAN0TMID15HH RSCAN0.TMID15.UINT8[HH]
+#define RSCAN0TMPTR15 RSCAN0.TMPTR15.UINT32
+#define RSCAN0TMPTR15L RSCAN0.TMPTR15.UINT16[L]
+#define RSCAN0TMPTR15LL RSCAN0.TMPTR15.UINT8[LL]
+#define RSCAN0TMPTR15LH RSCAN0.TMPTR15.UINT8[LH]
+#define RSCAN0TMPTR15H RSCAN0.TMPTR15.UINT16[H]
+#define RSCAN0TMPTR15HL RSCAN0.TMPTR15.UINT8[HL]
+#define RSCAN0TMPTR15HH RSCAN0.TMPTR15.UINT8[HH]
+#define RSCAN0TMDF015 RSCAN0.TMDF015.UINT32
+#define RSCAN0TMDF015L RSCAN0.TMDF015.UINT16[L]
+#define RSCAN0TMDF015LL RSCAN0.TMDF015.UINT8[LL]
+#define RSCAN0TMDF015LH RSCAN0.TMDF015.UINT8[LH]
+#define RSCAN0TMDF015H RSCAN0.TMDF015.UINT16[H]
+#define RSCAN0TMDF015HL RSCAN0.TMDF015.UINT8[HL]
+#define RSCAN0TMDF015HH RSCAN0.TMDF015.UINT8[HH]
+#define RSCAN0TMDF115 RSCAN0.TMDF115.UINT32
+#define RSCAN0TMDF115L RSCAN0.TMDF115.UINT16[L]
+#define RSCAN0TMDF115LL RSCAN0.TMDF115.UINT8[LL]
+#define RSCAN0TMDF115LH RSCAN0.TMDF115.UINT8[LH]
+#define RSCAN0TMDF115H RSCAN0.TMDF115.UINT16[H]
+#define RSCAN0TMDF115HL RSCAN0.TMDF115.UINT8[HL]
+#define RSCAN0TMDF115HH RSCAN0.TMDF115.UINT8[HH]
+#define RSCAN0TMID16 RSCAN0.TMID16.UINT32
+#define RSCAN0TMID16L RSCAN0.TMID16.UINT16[L]
+#define RSCAN0TMID16LL RSCAN0.TMID16.UINT8[LL]
+#define RSCAN0TMID16LH RSCAN0.TMID16.UINT8[LH]
+#define RSCAN0TMID16H RSCAN0.TMID16.UINT16[H]
+#define RSCAN0TMID16HL RSCAN0.TMID16.UINT8[HL]
+#define RSCAN0TMID16HH RSCAN0.TMID16.UINT8[HH]
+#define RSCAN0TMPTR16 RSCAN0.TMPTR16.UINT32
+#define RSCAN0TMPTR16L RSCAN0.TMPTR16.UINT16[L]
+#define RSCAN0TMPTR16LL RSCAN0.TMPTR16.UINT8[LL]
+#define RSCAN0TMPTR16LH RSCAN0.TMPTR16.UINT8[LH]
+#define RSCAN0TMPTR16H RSCAN0.TMPTR16.UINT16[H]
+#define RSCAN0TMPTR16HL RSCAN0.TMPTR16.UINT8[HL]
+#define RSCAN0TMPTR16HH RSCAN0.TMPTR16.UINT8[HH]
+#define RSCAN0TMDF016 RSCAN0.TMDF016.UINT32
+#define RSCAN0TMDF016L RSCAN0.TMDF016.UINT16[L]
+#define RSCAN0TMDF016LL RSCAN0.TMDF016.UINT8[LL]
+#define RSCAN0TMDF016LH RSCAN0.TMDF016.UINT8[LH]
+#define RSCAN0TMDF016H RSCAN0.TMDF016.UINT16[H]
+#define RSCAN0TMDF016HL RSCAN0.TMDF016.UINT8[HL]
+#define RSCAN0TMDF016HH RSCAN0.TMDF016.UINT8[HH]
+#define RSCAN0TMDF116 RSCAN0.TMDF116.UINT32
+#define RSCAN0TMDF116L RSCAN0.TMDF116.UINT16[L]
+#define RSCAN0TMDF116LL RSCAN0.TMDF116.UINT8[LL]
+#define RSCAN0TMDF116LH RSCAN0.TMDF116.UINT8[LH]
+#define RSCAN0TMDF116H RSCAN0.TMDF116.UINT16[H]
+#define RSCAN0TMDF116HL RSCAN0.TMDF116.UINT8[HL]
+#define RSCAN0TMDF116HH RSCAN0.TMDF116.UINT8[HH]
+#define RSCAN0TMID17 RSCAN0.TMID17.UINT32
+#define RSCAN0TMID17L RSCAN0.TMID17.UINT16[L]
+#define RSCAN0TMID17LL RSCAN0.TMID17.UINT8[LL]
+#define RSCAN0TMID17LH RSCAN0.TMID17.UINT8[LH]
+#define RSCAN0TMID17H RSCAN0.TMID17.UINT16[H]
+#define RSCAN0TMID17HL RSCAN0.TMID17.UINT8[HL]
+#define RSCAN0TMID17HH RSCAN0.TMID17.UINT8[HH]
+#define RSCAN0TMPTR17 RSCAN0.TMPTR17.UINT32
+#define RSCAN0TMPTR17L RSCAN0.TMPTR17.UINT16[L]
+#define RSCAN0TMPTR17LL RSCAN0.TMPTR17.UINT8[LL]
+#define RSCAN0TMPTR17LH RSCAN0.TMPTR17.UINT8[LH]
+#define RSCAN0TMPTR17H RSCAN0.TMPTR17.UINT16[H]
+#define RSCAN0TMPTR17HL RSCAN0.TMPTR17.UINT8[HL]
+#define RSCAN0TMPTR17HH RSCAN0.TMPTR17.UINT8[HH]
+#define RSCAN0TMDF017 RSCAN0.TMDF017.UINT32
+#define RSCAN0TMDF017L RSCAN0.TMDF017.UINT16[L]
+#define RSCAN0TMDF017LL RSCAN0.TMDF017.UINT8[LL]
+#define RSCAN0TMDF017LH RSCAN0.TMDF017.UINT8[LH]
+#define RSCAN0TMDF017H RSCAN0.TMDF017.UINT16[H]
+#define RSCAN0TMDF017HL RSCAN0.TMDF017.UINT8[HL]
+#define RSCAN0TMDF017HH RSCAN0.TMDF017.UINT8[HH]
+#define RSCAN0TMDF117 RSCAN0.TMDF117.UINT32
+#define RSCAN0TMDF117L RSCAN0.TMDF117.UINT16[L]
+#define RSCAN0TMDF117LL RSCAN0.TMDF117.UINT8[LL]
+#define RSCAN0TMDF117LH RSCAN0.TMDF117.UINT8[LH]
+#define RSCAN0TMDF117H RSCAN0.TMDF117.UINT16[H]
+#define RSCAN0TMDF117HL RSCAN0.TMDF117.UINT8[HL]
+#define RSCAN0TMDF117HH RSCAN0.TMDF117.UINT8[HH]
+#define RSCAN0TMID18 RSCAN0.TMID18.UINT32
+#define RSCAN0TMID18L RSCAN0.TMID18.UINT16[L]
+#define RSCAN0TMID18LL RSCAN0.TMID18.UINT8[LL]
+#define RSCAN0TMID18LH RSCAN0.TMID18.UINT8[LH]
+#define RSCAN0TMID18H RSCAN0.TMID18.UINT16[H]
+#define RSCAN0TMID18HL RSCAN0.TMID18.UINT8[HL]
+#define RSCAN0TMID18HH RSCAN0.TMID18.UINT8[HH]
+#define RSCAN0TMPTR18 RSCAN0.TMPTR18.UINT32
+#define RSCAN0TMPTR18L RSCAN0.TMPTR18.UINT16[L]
+#define RSCAN0TMPTR18LL RSCAN0.TMPTR18.UINT8[LL]
+#define RSCAN0TMPTR18LH RSCAN0.TMPTR18.UINT8[LH]
+#define RSCAN0TMPTR18H RSCAN0.TMPTR18.UINT16[H]
+#define RSCAN0TMPTR18HL RSCAN0.TMPTR18.UINT8[HL]
+#define RSCAN0TMPTR18HH RSCAN0.TMPTR18.UINT8[HH]
+#define RSCAN0TMDF018 RSCAN0.TMDF018.UINT32
+#define RSCAN0TMDF018L RSCAN0.TMDF018.UINT16[L]
+#define RSCAN0TMDF018LL RSCAN0.TMDF018.UINT8[LL]
+#define RSCAN0TMDF018LH RSCAN0.TMDF018.UINT8[LH]
+#define RSCAN0TMDF018H RSCAN0.TMDF018.UINT16[H]
+#define RSCAN0TMDF018HL RSCAN0.TMDF018.UINT8[HL]
+#define RSCAN0TMDF018HH RSCAN0.TMDF018.UINT8[HH]
+#define RSCAN0TMDF118 RSCAN0.TMDF118.UINT32
+#define RSCAN0TMDF118L RSCAN0.TMDF118.UINT16[L]
+#define RSCAN0TMDF118LL RSCAN0.TMDF118.UINT8[LL]
+#define RSCAN0TMDF118LH RSCAN0.TMDF118.UINT8[LH]
+#define RSCAN0TMDF118H RSCAN0.TMDF118.UINT16[H]
+#define RSCAN0TMDF118HL RSCAN0.TMDF118.UINT8[HL]
+#define RSCAN0TMDF118HH RSCAN0.TMDF118.UINT8[HH]
+#define RSCAN0TMID19 RSCAN0.TMID19.UINT32
+#define RSCAN0TMID19L RSCAN0.TMID19.UINT16[L]
+#define RSCAN0TMID19LL RSCAN0.TMID19.UINT8[LL]
+#define RSCAN0TMID19LH RSCAN0.TMID19.UINT8[LH]
+#define RSCAN0TMID19H RSCAN0.TMID19.UINT16[H]
+#define RSCAN0TMID19HL RSCAN0.TMID19.UINT8[HL]
+#define RSCAN0TMID19HH RSCAN0.TMID19.UINT8[HH]
+#define RSCAN0TMPTR19 RSCAN0.TMPTR19.UINT32
+#define RSCAN0TMPTR19L RSCAN0.TMPTR19.UINT16[L]
+#define RSCAN0TMPTR19LL RSCAN0.TMPTR19.UINT8[LL]
+#define RSCAN0TMPTR19LH RSCAN0.TMPTR19.UINT8[LH]
+#define RSCAN0TMPTR19H RSCAN0.TMPTR19.UINT16[H]
+#define RSCAN0TMPTR19HL RSCAN0.TMPTR19.UINT8[HL]
+#define RSCAN0TMPTR19HH RSCAN0.TMPTR19.UINT8[HH]
+#define RSCAN0TMDF019 RSCAN0.TMDF019.UINT32
+#define RSCAN0TMDF019L RSCAN0.TMDF019.UINT16[L]
+#define RSCAN0TMDF019LL RSCAN0.TMDF019.UINT8[LL]
+#define RSCAN0TMDF019LH RSCAN0.TMDF019.UINT8[LH]
+#define RSCAN0TMDF019H RSCAN0.TMDF019.UINT16[H]
+#define RSCAN0TMDF019HL RSCAN0.TMDF019.UINT8[HL]
+#define RSCAN0TMDF019HH RSCAN0.TMDF019.UINT8[HH]
+#define RSCAN0TMDF119 RSCAN0.TMDF119.UINT32
+#define RSCAN0TMDF119L RSCAN0.TMDF119.UINT16[L]
+#define RSCAN0TMDF119LL RSCAN0.TMDF119.UINT8[LL]
+#define RSCAN0TMDF119LH RSCAN0.TMDF119.UINT8[LH]
+#define RSCAN0TMDF119H RSCAN0.TMDF119.UINT16[H]
+#define RSCAN0TMDF119HL RSCAN0.TMDF119.UINT8[HL]
+#define RSCAN0TMDF119HH RSCAN0.TMDF119.UINT8[HH]
+#define RSCAN0TMID20 RSCAN0.TMID20.UINT32
+#define RSCAN0TMID20L RSCAN0.TMID20.UINT16[L]
+#define RSCAN0TMID20LL RSCAN0.TMID20.UINT8[LL]
+#define RSCAN0TMID20LH RSCAN0.TMID20.UINT8[LH]
+#define RSCAN0TMID20H RSCAN0.TMID20.UINT16[H]
+#define RSCAN0TMID20HL RSCAN0.TMID20.UINT8[HL]
+#define RSCAN0TMID20HH RSCAN0.TMID20.UINT8[HH]
+#define RSCAN0TMPTR20 RSCAN0.TMPTR20.UINT32
+#define RSCAN0TMPTR20L RSCAN0.TMPTR20.UINT16[L]
+#define RSCAN0TMPTR20LL RSCAN0.TMPTR20.UINT8[LL]
+#define RSCAN0TMPTR20LH RSCAN0.TMPTR20.UINT8[LH]
+#define RSCAN0TMPTR20H RSCAN0.TMPTR20.UINT16[H]
+#define RSCAN0TMPTR20HL RSCAN0.TMPTR20.UINT8[HL]
+#define RSCAN0TMPTR20HH RSCAN0.TMPTR20.UINT8[HH]
+#define RSCAN0TMDF020 RSCAN0.TMDF020.UINT32
+#define RSCAN0TMDF020L RSCAN0.TMDF020.UINT16[L]
+#define RSCAN0TMDF020LL RSCAN0.TMDF020.UINT8[LL]
+#define RSCAN0TMDF020LH RSCAN0.TMDF020.UINT8[LH]
+#define RSCAN0TMDF020H RSCAN0.TMDF020.UINT16[H]
+#define RSCAN0TMDF020HL RSCAN0.TMDF020.UINT8[HL]
+#define RSCAN0TMDF020HH RSCAN0.TMDF020.UINT8[HH]
+#define RSCAN0TMDF120 RSCAN0.TMDF120.UINT32
+#define RSCAN0TMDF120L RSCAN0.TMDF120.UINT16[L]
+#define RSCAN0TMDF120LL RSCAN0.TMDF120.UINT8[LL]
+#define RSCAN0TMDF120LH RSCAN0.TMDF120.UINT8[LH]
+#define RSCAN0TMDF120H RSCAN0.TMDF120.UINT16[H]
+#define RSCAN0TMDF120HL RSCAN0.TMDF120.UINT8[HL]
+#define RSCAN0TMDF120HH RSCAN0.TMDF120.UINT8[HH]
+#define RSCAN0TMID21 RSCAN0.TMID21.UINT32
+#define RSCAN0TMID21L RSCAN0.TMID21.UINT16[L]
+#define RSCAN0TMID21LL RSCAN0.TMID21.UINT8[LL]
+#define RSCAN0TMID21LH RSCAN0.TMID21.UINT8[LH]
+#define RSCAN0TMID21H RSCAN0.TMID21.UINT16[H]
+#define RSCAN0TMID21HL RSCAN0.TMID21.UINT8[HL]
+#define RSCAN0TMID21HH RSCAN0.TMID21.UINT8[HH]
+#define RSCAN0TMPTR21 RSCAN0.TMPTR21.UINT32
+#define RSCAN0TMPTR21L RSCAN0.TMPTR21.UINT16[L]
+#define RSCAN0TMPTR21LL RSCAN0.TMPTR21.UINT8[LL]
+#define RSCAN0TMPTR21LH RSCAN0.TMPTR21.UINT8[LH]
+#define RSCAN0TMPTR21H RSCAN0.TMPTR21.UINT16[H]
+#define RSCAN0TMPTR21HL RSCAN0.TMPTR21.UINT8[HL]
+#define RSCAN0TMPTR21HH RSCAN0.TMPTR21.UINT8[HH]
+#define RSCAN0TMDF021 RSCAN0.TMDF021.UINT32
+#define RSCAN0TMDF021L RSCAN0.TMDF021.UINT16[L]
+#define RSCAN0TMDF021LL RSCAN0.TMDF021.UINT8[LL]
+#define RSCAN0TMDF021LH RSCAN0.TMDF021.UINT8[LH]
+#define RSCAN0TMDF021H RSCAN0.TMDF021.UINT16[H]
+#define RSCAN0TMDF021HL RSCAN0.TMDF021.UINT8[HL]
+#define RSCAN0TMDF021HH RSCAN0.TMDF021.UINT8[HH]
+#define RSCAN0TMDF121 RSCAN0.TMDF121.UINT32
+#define RSCAN0TMDF121L RSCAN0.TMDF121.UINT16[L]
+#define RSCAN0TMDF121LL RSCAN0.TMDF121.UINT8[LL]
+#define RSCAN0TMDF121LH RSCAN0.TMDF121.UINT8[LH]
+#define RSCAN0TMDF121H RSCAN0.TMDF121.UINT16[H]
+#define RSCAN0TMDF121HL RSCAN0.TMDF121.UINT8[HL]
+#define RSCAN0TMDF121HH RSCAN0.TMDF121.UINT8[HH]
+#define RSCAN0TMID22 RSCAN0.TMID22.UINT32
+#define RSCAN0TMID22L RSCAN0.TMID22.UINT16[L]
+#define RSCAN0TMID22LL RSCAN0.TMID22.UINT8[LL]
+#define RSCAN0TMID22LH RSCAN0.TMID22.UINT8[LH]
+#define RSCAN0TMID22H RSCAN0.TMID22.UINT16[H]
+#define RSCAN0TMID22HL RSCAN0.TMID22.UINT8[HL]
+#define RSCAN0TMID22HH RSCAN0.TMID22.UINT8[HH]
+#define RSCAN0TMPTR22 RSCAN0.TMPTR22.UINT32
+#define RSCAN0TMPTR22L RSCAN0.TMPTR22.UINT16[L]
+#define RSCAN0TMPTR22LL RSCAN0.TMPTR22.UINT8[LL]
+#define RSCAN0TMPTR22LH RSCAN0.TMPTR22.UINT8[LH]
+#define RSCAN0TMPTR22H RSCAN0.TMPTR22.UINT16[H]
+#define RSCAN0TMPTR22HL RSCAN0.TMPTR22.UINT8[HL]
+#define RSCAN0TMPTR22HH RSCAN0.TMPTR22.UINT8[HH]
+#define RSCAN0TMDF022 RSCAN0.TMDF022.UINT32
+#define RSCAN0TMDF022L RSCAN0.TMDF022.UINT16[L]
+#define RSCAN0TMDF022LL RSCAN0.TMDF022.UINT8[LL]
+#define RSCAN0TMDF022LH RSCAN0.TMDF022.UINT8[LH]
+#define RSCAN0TMDF022H RSCAN0.TMDF022.UINT16[H]
+#define RSCAN0TMDF022HL RSCAN0.TMDF022.UINT8[HL]
+#define RSCAN0TMDF022HH RSCAN0.TMDF022.UINT8[HH]
+#define RSCAN0TMDF122 RSCAN0.TMDF122.UINT32
+#define RSCAN0TMDF122L RSCAN0.TMDF122.UINT16[L]
+#define RSCAN0TMDF122LL RSCAN0.TMDF122.UINT8[LL]
+#define RSCAN0TMDF122LH RSCAN0.TMDF122.UINT8[LH]
+#define RSCAN0TMDF122H RSCAN0.TMDF122.UINT16[H]
+#define RSCAN0TMDF122HL RSCAN0.TMDF122.UINT8[HL]
+#define RSCAN0TMDF122HH RSCAN0.TMDF122.UINT8[HH]
+#define RSCAN0TMID23 RSCAN0.TMID23.UINT32
+#define RSCAN0TMID23L RSCAN0.TMID23.UINT16[L]
+#define RSCAN0TMID23LL RSCAN0.TMID23.UINT8[LL]
+#define RSCAN0TMID23LH RSCAN0.TMID23.UINT8[LH]
+#define RSCAN0TMID23H RSCAN0.TMID23.UINT16[H]
+#define RSCAN0TMID23HL RSCAN0.TMID23.UINT8[HL]
+#define RSCAN0TMID23HH RSCAN0.TMID23.UINT8[HH]
+#define RSCAN0TMPTR23 RSCAN0.TMPTR23.UINT32
+#define RSCAN0TMPTR23L RSCAN0.TMPTR23.UINT16[L]
+#define RSCAN0TMPTR23LL RSCAN0.TMPTR23.UINT8[LL]
+#define RSCAN0TMPTR23LH RSCAN0.TMPTR23.UINT8[LH]
+#define RSCAN0TMPTR23H RSCAN0.TMPTR23.UINT16[H]
+#define RSCAN0TMPTR23HL RSCAN0.TMPTR23.UINT8[HL]
+#define RSCAN0TMPTR23HH RSCAN0.TMPTR23.UINT8[HH]
+#define RSCAN0TMDF023 RSCAN0.TMDF023.UINT32
+#define RSCAN0TMDF023L RSCAN0.TMDF023.UINT16[L]
+#define RSCAN0TMDF023LL RSCAN0.TMDF023.UINT8[LL]
+#define RSCAN0TMDF023LH RSCAN0.TMDF023.UINT8[LH]
+#define RSCAN0TMDF023H RSCAN0.TMDF023.UINT16[H]
+#define RSCAN0TMDF023HL RSCAN0.TMDF023.UINT8[HL]
+#define RSCAN0TMDF023HH RSCAN0.TMDF023.UINT8[HH]
+#define RSCAN0TMDF123 RSCAN0.TMDF123.UINT32
+#define RSCAN0TMDF123L RSCAN0.TMDF123.UINT16[L]
+#define RSCAN0TMDF123LL RSCAN0.TMDF123.UINT8[LL]
+#define RSCAN0TMDF123LH RSCAN0.TMDF123.UINT8[LH]
+#define RSCAN0TMDF123H RSCAN0.TMDF123.UINT16[H]
+#define RSCAN0TMDF123HL RSCAN0.TMDF123.UINT8[HL]
+#define RSCAN0TMDF123HH RSCAN0.TMDF123.UINT8[HH]
+#define RSCAN0TMID24 RSCAN0.TMID24.UINT32
+#define RSCAN0TMID24L RSCAN0.TMID24.UINT16[L]
+#define RSCAN0TMID24LL RSCAN0.TMID24.UINT8[LL]
+#define RSCAN0TMID24LH RSCAN0.TMID24.UINT8[LH]
+#define RSCAN0TMID24H RSCAN0.TMID24.UINT16[H]
+#define RSCAN0TMID24HL RSCAN0.TMID24.UINT8[HL]
+#define RSCAN0TMID24HH RSCAN0.TMID24.UINT8[HH]
+#define RSCAN0TMPTR24 RSCAN0.TMPTR24.UINT32
+#define RSCAN0TMPTR24L RSCAN0.TMPTR24.UINT16[L]
+#define RSCAN0TMPTR24LL RSCAN0.TMPTR24.UINT8[LL]
+#define RSCAN0TMPTR24LH RSCAN0.TMPTR24.UINT8[LH]
+#define RSCAN0TMPTR24H RSCAN0.TMPTR24.UINT16[H]
+#define RSCAN0TMPTR24HL RSCAN0.TMPTR24.UINT8[HL]
+#define RSCAN0TMPTR24HH RSCAN0.TMPTR24.UINT8[HH]
+#define RSCAN0TMDF024 RSCAN0.TMDF024.UINT32
+#define RSCAN0TMDF024L RSCAN0.TMDF024.UINT16[L]
+#define RSCAN0TMDF024LL RSCAN0.TMDF024.UINT8[LL]
+#define RSCAN0TMDF024LH RSCAN0.TMDF024.UINT8[LH]
+#define RSCAN0TMDF024H RSCAN0.TMDF024.UINT16[H]
+#define RSCAN0TMDF024HL RSCAN0.TMDF024.UINT8[HL]
+#define RSCAN0TMDF024HH RSCAN0.TMDF024.UINT8[HH]
+#define RSCAN0TMDF124 RSCAN0.TMDF124.UINT32
+#define RSCAN0TMDF124L RSCAN0.TMDF124.UINT16[L]
+#define RSCAN0TMDF124LL RSCAN0.TMDF124.UINT8[LL]
+#define RSCAN0TMDF124LH RSCAN0.TMDF124.UINT8[LH]
+#define RSCAN0TMDF124H RSCAN0.TMDF124.UINT16[H]
+#define RSCAN0TMDF124HL RSCAN0.TMDF124.UINT8[HL]
+#define RSCAN0TMDF124HH RSCAN0.TMDF124.UINT8[HH]
+#define RSCAN0TMID25 RSCAN0.TMID25.UINT32
+#define RSCAN0TMID25L RSCAN0.TMID25.UINT16[L]
+#define RSCAN0TMID25LL RSCAN0.TMID25.UINT8[LL]
+#define RSCAN0TMID25LH RSCAN0.TMID25.UINT8[LH]
+#define RSCAN0TMID25H RSCAN0.TMID25.UINT16[H]
+#define RSCAN0TMID25HL RSCAN0.TMID25.UINT8[HL]
+#define RSCAN0TMID25HH RSCAN0.TMID25.UINT8[HH]
+#define RSCAN0TMPTR25 RSCAN0.TMPTR25.UINT32
+#define RSCAN0TMPTR25L RSCAN0.TMPTR25.UINT16[L]
+#define RSCAN0TMPTR25LL RSCAN0.TMPTR25.UINT8[LL]
+#define RSCAN0TMPTR25LH RSCAN0.TMPTR25.UINT8[LH]
+#define RSCAN0TMPTR25H RSCAN0.TMPTR25.UINT16[H]
+#define RSCAN0TMPTR25HL RSCAN0.TMPTR25.UINT8[HL]
+#define RSCAN0TMPTR25HH RSCAN0.TMPTR25.UINT8[HH]
+#define RSCAN0TMDF025 RSCAN0.TMDF025.UINT32
+#define RSCAN0TMDF025L RSCAN0.TMDF025.UINT16[L]
+#define RSCAN0TMDF025LL RSCAN0.TMDF025.UINT8[LL]
+#define RSCAN0TMDF025LH RSCAN0.TMDF025.UINT8[LH]
+#define RSCAN0TMDF025H RSCAN0.TMDF025.UINT16[H]
+#define RSCAN0TMDF025HL RSCAN0.TMDF025.UINT8[HL]
+#define RSCAN0TMDF025HH RSCAN0.TMDF025.UINT8[HH]
+#define RSCAN0TMDF125 RSCAN0.TMDF125.UINT32
+#define RSCAN0TMDF125L RSCAN0.TMDF125.UINT16[L]
+#define RSCAN0TMDF125LL RSCAN0.TMDF125.UINT8[LL]
+#define RSCAN0TMDF125LH RSCAN0.TMDF125.UINT8[LH]
+#define RSCAN0TMDF125H RSCAN0.TMDF125.UINT16[H]
+#define RSCAN0TMDF125HL RSCAN0.TMDF125.UINT8[HL]
+#define RSCAN0TMDF125HH RSCAN0.TMDF125.UINT8[HH]
+#define RSCAN0TMID26 RSCAN0.TMID26.UINT32
+#define RSCAN0TMID26L RSCAN0.TMID26.UINT16[L]
+#define RSCAN0TMID26LL RSCAN0.TMID26.UINT8[LL]
+#define RSCAN0TMID26LH RSCAN0.TMID26.UINT8[LH]
+#define RSCAN0TMID26H RSCAN0.TMID26.UINT16[H]
+#define RSCAN0TMID26HL RSCAN0.TMID26.UINT8[HL]
+#define RSCAN0TMID26HH RSCAN0.TMID26.UINT8[HH]
+#define RSCAN0TMPTR26 RSCAN0.TMPTR26.UINT32
+#define RSCAN0TMPTR26L RSCAN0.TMPTR26.UINT16[L]
+#define RSCAN0TMPTR26LL RSCAN0.TMPTR26.UINT8[LL]
+#define RSCAN0TMPTR26LH RSCAN0.TMPTR26.UINT8[LH]
+#define RSCAN0TMPTR26H RSCAN0.TMPTR26.UINT16[H]
+#define RSCAN0TMPTR26HL RSCAN0.TMPTR26.UINT8[HL]
+#define RSCAN0TMPTR26HH RSCAN0.TMPTR26.UINT8[HH]
+#define RSCAN0TMDF026 RSCAN0.TMDF026.UINT32
+#define RSCAN0TMDF026L RSCAN0.TMDF026.UINT16[L]
+#define RSCAN0TMDF026LL RSCAN0.TMDF026.UINT8[LL]
+#define RSCAN0TMDF026LH RSCAN0.TMDF026.UINT8[LH]
+#define RSCAN0TMDF026H RSCAN0.TMDF026.UINT16[H]
+#define RSCAN0TMDF026HL RSCAN0.TMDF026.UINT8[HL]
+#define RSCAN0TMDF026HH RSCAN0.TMDF026.UINT8[HH]
+#define RSCAN0TMDF126 RSCAN0.TMDF126.UINT32
+#define RSCAN0TMDF126L RSCAN0.TMDF126.UINT16[L]
+#define RSCAN0TMDF126LL RSCAN0.TMDF126.UINT8[LL]
+#define RSCAN0TMDF126LH RSCAN0.TMDF126.UINT8[LH]
+#define RSCAN0TMDF126H RSCAN0.TMDF126.UINT16[H]
+#define RSCAN0TMDF126HL RSCAN0.TMDF126.UINT8[HL]
+#define RSCAN0TMDF126HH RSCAN0.TMDF126.UINT8[HH]
+#define RSCAN0TMID27 RSCAN0.TMID27.UINT32
+#define RSCAN0TMID27L RSCAN0.TMID27.UINT16[L]
+#define RSCAN0TMID27LL RSCAN0.TMID27.UINT8[LL]
+#define RSCAN0TMID27LH RSCAN0.TMID27.UINT8[LH]
+#define RSCAN0TMID27H RSCAN0.TMID27.UINT16[H]
+#define RSCAN0TMID27HL RSCAN0.TMID27.UINT8[HL]
+#define RSCAN0TMID27HH RSCAN0.TMID27.UINT8[HH]
+#define RSCAN0TMPTR27 RSCAN0.TMPTR27.UINT32
+#define RSCAN0TMPTR27L RSCAN0.TMPTR27.UINT16[L]
+#define RSCAN0TMPTR27LL RSCAN0.TMPTR27.UINT8[LL]
+#define RSCAN0TMPTR27LH RSCAN0.TMPTR27.UINT8[LH]
+#define RSCAN0TMPTR27H RSCAN0.TMPTR27.UINT16[H]
+#define RSCAN0TMPTR27HL RSCAN0.TMPTR27.UINT8[HL]
+#define RSCAN0TMPTR27HH RSCAN0.TMPTR27.UINT8[HH]
+#define RSCAN0TMDF027 RSCAN0.TMDF027.UINT32
+#define RSCAN0TMDF027L RSCAN0.TMDF027.UINT16[L]
+#define RSCAN0TMDF027LL RSCAN0.TMDF027.UINT8[LL]
+#define RSCAN0TMDF027LH RSCAN0.TMDF027.UINT8[LH]
+#define RSCAN0TMDF027H RSCAN0.TMDF027.UINT16[H]
+#define RSCAN0TMDF027HL RSCAN0.TMDF027.UINT8[HL]
+#define RSCAN0TMDF027HH RSCAN0.TMDF027.UINT8[HH]
+#define RSCAN0TMDF127 RSCAN0.TMDF127.UINT32
+#define RSCAN0TMDF127L RSCAN0.TMDF127.UINT16[L]
+#define RSCAN0TMDF127LL RSCAN0.TMDF127.UINT8[LL]
+#define RSCAN0TMDF127LH RSCAN0.TMDF127.UINT8[LH]
+#define RSCAN0TMDF127H RSCAN0.TMDF127.UINT16[H]
+#define RSCAN0TMDF127HL RSCAN0.TMDF127.UINT8[HL]
+#define RSCAN0TMDF127HH RSCAN0.TMDF127.UINT8[HH]
+#define RSCAN0TMID28 RSCAN0.TMID28.UINT32
+#define RSCAN0TMID28L RSCAN0.TMID28.UINT16[L]
+#define RSCAN0TMID28LL RSCAN0.TMID28.UINT8[LL]
+#define RSCAN0TMID28LH RSCAN0.TMID28.UINT8[LH]
+#define RSCAN0TMID28H RSCAN0.TMID28.UINT16[H]
+#define RSCAN0TMID28HL RSCAN0.TMID28.UINT8[HL]
+#define RSCAN0TMID28HH RSCAN0.TMID28.UINT8[HH]
+#define RSCAN0TMPTR28 RSCAN0.TMPTR28.UINT32
+#define RSCAN0TMPTR28L RSCAN0.TMPTR28.UINT16[L]
+#define RSCAN0TMPTR28LL RSCAN0.TMPTR28.UINT8[LL]
+#define RSCAN0TMPTR28LH RSCAN0.TMPTR28.UINT8[LH]
+#define RSCAN0TMPTR28H RSCAN0.TMPTR28.UINT16[H]
+#define RSCAN0TMPTR28HL RSCAN0.TMPTR28.UINT8[HL]
+#define RSCAN0TMPTR28HH RSCAN0.TMPTR28.UINT8[HH]
+#define RSCAN0TMDF028 RSCAN0.TMDF028.UINT32
+#define RSCAN0TMDF028L RSCAN0.TMDF028.UINT16[L]
+#define RSCAN0TMDF028LL RSCAN0.TMDF028.UINT8[LL]
+#define RSCAN0TMDF028LH RSCAN0.TMDF028.UINT8[LH]
+#define RSCAN0TMDF028H RSCAN0.TMDF028.UINT16[H]
+#define RSCAN0TMDF028HL RSCAN0.TMDF028.UINT8[HL]
+#define RSCAN0TMDF028HH RSCAN0.TMDF028.UINT8[HH]
+#define RSCAN0TMDF128 RSCAN0.TMDF128.UINT32
+#define RSCAN0TMDF128L RSCAN0.TMDF128.UINT16[L]
+#define RSCAN0TMDF128LL RSCAN0.TMDF128.UINT8[LL]
+#define RSCAN0TMDF128LH RSCAN0.TMDF128.UINT8[LH]
+#define RSCAN0TMDF128H RSCAN0.TMDF128.UINT16[H]
+#define RSCAN0TMDF128HL RSCAN0.TMDF128.UINT8[HL]
+#define RSCAN0TMDF128HH RSCAN0.TMDF128.UINT8[HH]
+#define RSCAN0TMID29 RSCAN0.TMID29.UINT32
+#define RSCAN0TMID29L RSCAN0.TMID29.UINT16[L]
+#define RSCAN0TMID29LL RSCAN0.TMID29.UINT8[LL]
+#define RSCAN0TMID29LH RSCAN0.TMID29.UINT8[LH]
+#define RSCAN0TMID29H RSCAN0.TMID29.UINT16[H]
+#define RSCAN0TMID29HL RSCAN0.TMID29.UINT8[HL]
+#define RSCAN0TMID29HH RSCAN0.TMID29.UINT8[HH]
+#define RSCAN0TMPTR29 RSCAN0.TMPTR29.UINT32
+#define RSCAN0TMPTR29L RSCAN0.TMPTR29.UINT16[L]
+#define RSCAN0TMPTR29LL RSCAN0.TMPTR29.UINT8[LL]
+#define RSCAN0TMPTR29LH RSCAN0.TMPTR29.UINT8[LH]
+#define RSCAN0TMPTR29H RSCAN0.TMPTR29.UINT16[H]
+#define RSCAN0TMPTR29HL RSCAN0.TMPTR29.UINT8[HL]
+#define RSCAN0TMPTR29HH RSCAN0.TMPTR29.UINT8[HH]
+#define RSCAN0TMDF029 RSCAN0.TMDF029.UINT32
+#define RSCAN0TMDF029L RSCAN0.TMDF029.UINT16[L]
+#define RSCAN0TMDF029LL RSCAN0.TMDF029.UINT8[LL]
+#define RSCAN0TMDF029LH RSCAN0.TMDF029.UINT8[LH]
+#define RSCAN0TMDF029H RSCAN0.TMDF029.UINT16[H]
+#define RSCAN0TMDF029HL RSCAN0.TMDF029.UINT8[HL]
+#define RSCAN0TMDF029HH RSCAN0.TMDF029.UINT8[HH]
+#define RSCAN0TMDF129 RSCAN0.TMDF129.UINT32
+#define RSCAN0TMDF129L RSCAN0.TMDF129.UINT16[L]
+#define RSCAN0TMDF129LL RSCAN0.TMDF129.UINT8[LL]
+#define RSCAN0TMDF129LH RSCAN0.TMDF129.UINT8[LH]
+#define RSCAN0TMDF129H RSCAN0.TMDF129.UINT16[H]
+#define RSCAN0TMDF129HL RSCAN0.TMDF129.UINT8[HL]
+#define RSCAN0TMDF129HH RSCAN0.TMDF129.UINT8[HH]
+#define RSCAN0TMID30 RSCAN0.TMID30.UINT32
+#define RSCAN0TMID30L RSCAN0.TMID30.UINT16[L]
+#define RSCAN0TMID30LL RSCAN0.TMID30.UINT8[LL]
+#define RSCAN0TMID30LH RSCAN0.TMID30.UINT8[LH]
+#define RSCAN0TMID30H RSCAN0.TMID30.UINT16[H]
+#define RSCAN0TMID30HL RSCAN0.TMID30.UINT8[HL]
+#define RSCAN0TMID30HH RSCAN0.TMID30.UINT8[HH]
+#define RSCAN0TMPTR30 RSCAN0.TMPTR30.UINT32
+#define RSCAN0TMPTR30L RSCAN0.TMPTR30.UINT16[L]
+#define RSCAN0TMPTR30LL RSCAN0.TMPTR30.UINT8[LL]
+#define RSCAN0TMPTR30LH RSCAN0.TMPTR30.UINT8[LH]
+#define RSCAN0TMPTR30H RSCAN0.TMPTR30.UINT16[H]
+#define RSCAN0TMPTR30HL RSCAN0.TMPTR30.UINT8[HL]
+#define RSCAN0TMPTR30HH RSCAN0.TMPTR30.UINT8[HH]
+#define RSCAN0TMDF030 RSCAN0.TMDF030.UINT32
+#define RSCAN0TMDF030L RSCAN0.TMDF030.UINT16[L]
+#define RSCAN0TMDF030LL RSCAN0.TMDF030.UINT8[LL]
+#define RSCAN0TMDF030LH RSCAN0.TMDF030.UINT8[LH]
+#define RSCAN0TMDF030H RSCAN0.TMDF030.UINT16[H]
+#define RSCAN0TMDF030HL RSCAN0.TMDF030.UINT8[HL]
+#define RSCAN0TMDF030HH RSCAN0.TMDF030.UINT8[HH]
+#define RSCAN0TMDF130 RSCAN0.TMDF130.UINT32
+#define RSCAN0TMDF130L RSCAN0.TMDF130.UINT16[L]
+#define RSCAN0TMDF130LL RSCAN0.TMDF130.UINT8[LL]
+#define RSCAN0TMDF130LH RSCAN0.TMDF130.UINT8[LH]
+#define RSCAN0TMDF130H RSCAN0.TMDF130.UINT16[H]
+#define RSCAN0TMDF130HL RSCAN0.TMDF130.UINT8[HL]
+#define RSCAN0TMDF130HH RSCAN0.TMDF130.UINT8[HH]
+#define RSCAN0TMID31 RSCAN0.TMID31.UINT32
+#define RSCAN0TMID31L RSCAN0.TMID31.UINT16[L]
+#define RSCAN0TMID31LL RSCAN0.TMID31.UINT8[LL]
+#define RSCAN0TMID31LH RSCAN0.TMID31.UINT8[LH]
+#define RSCAN0TMID31H RSCAN0.TMID31.UINT16[H]
+#define RSCAN0TMID31HL RSCAN0.TMID31.UINT8[HL]
+#define RSCAN0TMID31HH RSCAN0.TMID31.UINT8[HH]
+#define RSCAN0TMPTR31 RSCAN0.TMPTR31.UINT32
+#define RSCAN0TMPTR31L RSCAN0.TMPTR31.UINT16[L]
+#define RSCAN0TMPTR31LL RSCAN0.TMPTR31.UINT8[LL]
+#define RSCAN0TMPTR31LH RSCAN0.TMPTR31.UINT8[LH]
+#define RSCAN0TMPTR31H RSCAN0.TMPTR31.UINT16[H]
+#define RSCAN0TMPTR31HL RSCAN0.TMPTR31.UINT8[HL]
+#define RSCAN0TMPTR31HH RSCAN0.TMPTR31.UINT8[HH]
+#define RSCAN0TMDF031 RSCAN0.TMDF031.UINT32
+#define RSCAN0TMDF031L RSCAN0.TMDF031.UINT16[L]
+#define RSCAN0TMDF031LL RSCAN0.TMDF031.UINT8[LL]
+#define RSCAN0TMDF031LH RSCAN0.TMDF031.UINT8[LH]
+#define RSCAN0TMDF031H RSCAN0.TMDF031.UINT16[H]
+#define RSCAN0TMDF031HL RSCAN0.TMDF031.UINT8[HL]
+#define RSCAN0TMDF031HH RSCAN0.TMDF031.UINT8[HH]
+#define RSCAN0TMDF131 RSCAN0.TMDF131.UINT32
+#define RSCAN0TMDF131L RSCAN0.TMDF131.UINT16[L]
+#define RSCAN0TMDF131LL RSCAN0.TMDF131.UINT8[LL]
+#define RSCAN0TMDF131LH RSCAN0.TMDF131.UINT8[LH]
+#define RSCAN0TMDF131H RSCAN0.TMDF131.UINT16[H]
+#define RSCAN0TMDF131HL RSCAN0.TMDF131.UINT8[HL]
+#define RSCAN0TMDF131HH RSCAN0.TMDF131.UINT8[HH]
+#define RSCAN0TMID32 RSCAN0.TMID32.UINT32
+#define RSCAN0TMID32L RSCAN0.TMID32.UINT16[L]
+#define RSCAN0TMID32LL RSCAN0.TMID32.UINT8[LL]
+#define RSCAN0TMID32LH RSCAN0.TMID32.UINT8[LH]
+#define RSCAN0TMID32H RSCAN0.TMID32.UINT16[H]
+#define RSCAN0TMID32HL RSCAN0.TMID32.UINT8[HL]
+#define RSCAN0TMID32HH RSCAN0.TMID32.UINT8[HH]
+#define RSCAN0TMPTR32 RSCAN0.TMPTR32.UINT32
+#define RSCAN0TMPTR32L RSCAN0.TMPTR32.UINT16[L]
+#define RSCAN0TMPTR32LL RSCAN0.TMPTR32.UINT8[LL]
+#define RSCAN0TMPTR32LH RSCAN0.TMPTR32.UINT8[LH]
+#define RSCAN0TMPTR32H RSCAN0.TMPTR32.UINT16[H]
+#define RSCAN0TMPTR32HL RSCAN0.TMPTR32.UINT8[HL]
+#define RSCAN0TMPTR32HH RSCAN0.TMPTR32.UINT8[HH]
+#define RSCAN0TMDF032 RSCAN0.TMDF032.UINT32
+#define RSCAN0TMDF032L RSCAN0.TMDF032.UINT16[L]
+#define RSCAN0TMDF032LL RSCAN0.TMDF032.UINT8[LL]
+#define RSCAN0TMDF032LH RSCAN0.TMDF032.UINT8[LH]
+#define RSCAN0TMDF032H RSCAN0.TMDF032.UINT16[H]
+#define RSCAN0TMDF032HL RSCAN0.TMDF032.UINT8[HL]
+#define RSCAN0TMDF032HH RSCAN0.TMDF032.UINT8[HH]
+#define RSCAN0TMDF132 RSCAN0.TMDF132.UINT32
+#define RSCAN0TMDF132L RSCAN0.TMDF132.UINT16[L]
+#define RSCAN0TMDF132LL RSCAN0.TMDF132.UINT8[LL]
+#define RSCAN0TMDF132LH RSCAN0.TMDF132.UINT8[LH]
+#define RSCAN0TMDF132H RSCAN0.TMDF132.UINT16[H]
+#define RSCAN0TMDF132HL RSCAN0.TMDF132.UINT8[HL]
+#define RSCAN0TMDF132HH RSCAN0.TMDF132.UINT8[HH]
+#define RSCAN0TMID33 RSCAN0.TMID33.UINT32
+#define RSCAN0TMID33L RSCAN0.TMID33.UINT16[L]
+#define RSCAN0TMID33LL RSCAN0.TMID33.UINT8[LL]
+#define RSCAN0TMID33LH RSCAN0.TMID33.UINT8[LH]
+#define RSCAN0TMID33H RSCAN0.TMID33.UINT16[H]
+#define RSCAN0TMID33HL RSCAN0.TMID33.UINT8[HL]
+#define RSCAN0TMID33HH RSCAN0.TMID33.UINT8[HH]
+#define RSCAN0TMPTR33 RSCAN0.TMPTR33.UINT32
+#define RSCAN0TMPTR33L RSCAN0.TMPTR33.UINT16[L]
+#define RSCAN0TMPTR33LL RSCAN0.TMPTR33.UINT8[LL]
+#define RSCAN0TMPTR33LH RSCAN0.TMPTR33.UINT8[LH]
+#define RSCAN0TMPTR33H RSCAN0.TMPTR33.UINT16[H]
+#define RSCAN0TMPTR33HL RSCAN0.TMPTR33.UINT8[HL]
+#define RSCAN0TMPTR33HH RSCAN0.TMPTR33.UINT8[HH]
+#define RSCAN0TMDF033 RSCAN0.TMDF033.UINT32
+#define RSCAN0TMDF033L RSCAN0.TMDF033.UINT16[L]
+#define RSCAN0TMDF033LL RSCAN0.TMDF033.UINT8[LL]
+#define RSCAN0TMDF033LH RSCAN0.TMDF033.UINT8[LH]
+#define RSCAN0TMDF033H RSCAN0.TMDF033.UINT16[H]
+#define RSCAN0TMDF033HL RSCAN0.TMDF033.UINT8[HL]
+#define RSCAN0TMDF033HH RSCAN0.TMDF033.UINT8[HH]
+#define RSCAN0TMDF133 RSCAN0.TMDF133.UINT32
+#define RSCAN0TMDF133L RSCAN0.TMDF133.UINT16[L]
+#define RSCAN0TMDF133LL RSCAN0.TMDF133.UINT8[LL]
+#define RSCAN0TMDF133LH RSCAN0.TMDF133.UINT8[LH]
+#define RSCAN0TMDF133H RSCAN0.TMDF133.UINT16[H]
+#define RSCAN0TMDF133HL RSCAN0.TMDF133.UINT8[HL]
+#define RSCAN0TMDF133HH RSCAN0.TMDF133.UINT8[HH]
+#define RSCAN0TMID34 RSCAN0.TMID34.UINT32
+#define RSCAN0TMID34L RSCAN0.TMID34.UINT16[L]
+#define RSCAN0TMID34LL RSCAN0.TMID34.UINT8[LL]
+#define RSCAN0TMID34LH RSCAN0.TMID34.UINT8[LH]
+#define RSCAN0TMID34H RSCAN0.TMID34.UINT16[H]
+#define RSCAN0TMID34HL RSCAN0.TMID34.UINT8[HL]
+#define RSCAN0TMID34HH RSCAN0.TMID34.UINT8[HH]
+#define RSCAN0TMPTR34 RSCAN0.TMPTR34.UINT32
+#define RSCAN0TMPTR34L RSCAN0.TMPTR34.UINT16[L]
+#define RSCAN0TMPTR34LL RSCAN0.TMPTR34.UINT8[LL]
+#define RSCAN0TMPTR34LH RSCAN0.TMPTR34.UINT8[LH]
+#define RSCAN0TMPTR34H RSCAN0.TMPTR34.UINT16[H]
+#define RSCAN0TMPTR34HL RSCAN0.TMPTR34.UINT8[HL]
+#define RSCAN0TMPTR34HH RSCAN0.TMPTR34.UINT8[HH]
+#define RSCAN0TMDF034 RSCAN0.TMDF034.UINT32
+#define RSCAN0TMDF034L RSCAN0.TMDF034.UINT16[L]
+#define RSCAN0TMDF034LL RSCAN0.TMDF034.UINT8[LL]
+#define RSCAN0TMDF034LH RSCAN0.TMDF034.UINT8[LH]
+#define RSCAN0TMDF034H RSCAN0.TMDF034.UINT16[H]
+#define RSCAN0TMDF034HL RSCAN0.TMDF034.UINT8[HL]
+#define RSCAN0TMDF034HH RSCAN0.TMDF034.UINT8[HH]
+#define RSCAN0TMDF134 RSCAN0.TMDF134.UINT32
+#define RSCAN0TMDF134L RSCAN0.TMDF134.UINT16[L]
+#define RSCAN0TMDF134LL RSCAN0.TMDF134.UINT8[LL]
+#define RSCAN0TMDF134LH RSCAN0.TMDF134.UINT8[LH]
+#define RSCAN0TMDF134H RSCAN0.TMDF134.UINT16[H]
+#define RSCAN0TMDF134HL RSCAN0.TMDF134.UINT8[HL]
+#define RSCAN0TMDF134HH RSCAN0.TMDF134.UINT8[HH]
+#define RSCAN0TMID35 RSCAN0.TMID35.UINT32
+#define RSCAN0TMID35L RSCAN0.TMID35.UINT16[L]
+#define RSCAN0TMID35LL RSCAN0.TMID35.UINT8[LL]
+#define RSCAN0TMID35LH RSCAN0.TMID35.UINT8[LH]
+#define RSCAN0TMID35H RSCAN0.TMID35.UINT16[H]
+#define RSCAN0TMID35HL RSCAN0.TMID35.UINT8[HL]
+#define RSCAN0TMID35HH RSCAN0.TMID35.UINT8[HH]
+#define RSCAN0TMPTR35 RSCAN0.TMPTR35.UINT32
+#define RSCAN0TMPTR35L RSCAN0.TMPTR35.UINT16[L]
+#define RSCAN0TMPTR35LL RSCAN0.TMPTR35.UINT8[LL]
+#define RSCAN0TMPTR35LH RSCAN0.TMPTR35.UINT8[LH]
+#define RSCAN0TMPTR35H RSCAN0.TMPTR35.UINT16[H]
+#define RSCAN0TMPTR35HL RSCAN0.TMPTR35.UINT8[HL]
+#define RSCAN0TMPTR35HH RSCAN0.TMPTR35.UINT8[HH]
+#define RSCAN0TMDF035 RSCAN0.TMDF035.UINT32
+#define RSCAN0TMDF035L RSCAN0.TMDF035.UINT16[L]
+#define RSCAN0TMDF035LL RSCAN0.TMDF035.UINT8[LL]
+#define RSCAN0TMDF035LH RSCAN0.TMDF035.UINT8[LH]
+#define RSCAN0TMDF035H RSCAN0.TMDF035.UINT16[H]
+#define RSCAN0TMDF035HL RSCAN0.TMDF035.UINT8[HL]
+#define RSCAN0TMDF035HH RSCAN0.TMDF035.UINT8[HH]
+#define RSCAN0TMDF135 RSCAN0.TMDF135.UINT32
+#define RSCAN0TMDF135L RSCAN0.TMDF135.UINT16[L]
+#define RSCAN0TMDF135LL RSCAN0.TMDF135.UINT8[LL]
+#define RSCAN0TMDF135LH RSCAN0.TMDF135.UINT8[LH]
+#define RSCAN0TMDF135H RSCAN0.TMDF135.UINT16[H]
+#define RSCAN0TMDF135HL RSCAN0.TMDF135.UINT8[HL]
+#define RSCAN0TMDF135HH RSCAN0.TMDF135.UINT8[HH]
+#define RSCAN0TMID36 RSCAN0.TMID36.UINT32
+#define RSCAN0TMID36L RSCAN0.TMID36.UINT16[L]
+#define RSCAN0TMID36LL RSCAN0.TMID36.UINT8[LL]
+#define RSCAN0TMID36LH RSCAN0.TMID36.UINT8[LH]
+#define RSCAN0TMID36H RSCAN0.TMID36.UINT16[H]
+#define RSCAN0TMID36HL RSCAN0.TMID36.UINT8[HL]
+#define RSCAN0TMID36HH RSCAN0.TMID36.UINT8[HH]
+#define RSCAN0TMPTR36 RSCAN0.TMPTR36.UINT32
+#define RSCAN0TMPTR36L RSCAN0.TMPTR36.UINT16[L]
+#define RSCAN0TMPTR36LL RSCAN0.TMPTR36.UINT8[LL]
+#define RSCAN0TMPTR36LH RSCAN0.TMPTR36.UINT8[LH]
+#define RSCAN0TMPTR36H RSCAN0.TMPTR36.UINT16[H]
+#define RSCAN0TMPTR36HL RSCAN0.TMPTR36.UINT8[HL]
+#define RSCAN0TMPTR36HH RSCAN0.TMPTR36.UINT8[HH]
+#define RSCAN0TMDF036 RSCAN0.TMDF036.UINT32
+#define RSCAN0TMDF036L RSCAN0.TMDF036.UINT16[L]
+#define RSCAN0TMDF036LL RSCAN0.TMDF036.UINT8[LL]
+#define RSCAN0TMDF036LH RSCAN0.TMDF036.UINT8[LH]
+#define RSCAN0TMDF036H RSCAN0.TMDF036.UINT16[H]
+#define RSCAN0TMDF036HL RSCAN0.TMDF036.UINT8[HL]
+#define RSCAN0TMDF036HH RSCAN0.TMDF036.UINT8[HH]
+#define RSCAN0TMDF136 RSCAN0.TMDF136.UINT32
+#define RSCAN0TMDF136L RSCAN0.TMDF136.UINT16[L]
+#define RSCAN0TMDF136LL RSCAN0.TMDF136.UINT8[LL]
+#define RSCAN0TMDF136LH RSCAN0.TMDF136.UINT8[LH]
+#define RSCAN0TMDF136H RSCAN0.TMDF136.UINT16[H]
+#define RSCAN0TMDF136HL RSCAN0.TMDF136.UINT8[HL]
+#define RSCAN0TMDF136HH RSCAN0.TMDF136.UINT8[HH]
+#define RSCAN0TMID37 RSCAN0.TMID37.UINT32
+#define RSCAN0TMID37L RSCAN0.TMID37.UINT16[L]
+#define RSCAN0TMID37LL RSCAN0.TMID37.UINT8[LL]
+#define RSCAN0TMID37LH RSCAN0.TMID37.UINT8[LH]
+#define RSCAN0TMID37H RSCAN0.TMID37.UINT16[H]
+#define RSCAN0TMID37HL RSCAN0.TMID37.UINT8[HL]
+#define RSCAN0TMID37HH RSCAN0.TMID37.UINT8[HH]
+#define RSCAN0TMPTR37 RSCAN0.TMPTR37.UINT32
+#define RSCAN0TMPTR37L RSCAN0.TMPTR37.UINT16[L]
+#define RSCAN0TMPTR37LL RSCAN0.TMPTR37.UINT8[LL]
+#define RSCAN0TMPTR37LH RSCAN0.TMPTR37.UINT8[LH]
+#define RSCAN0TMPTR37H RSCAN0.TMPTR37.UINT16[H]
+#define RSCAN0TMPTR37HL RSCAN0.TMPTR37.UINT8[HL]
+#define RSCAN0TMPTR37HH RSCAN0.TMPTR37.UINT8[HH]
+#define RSCAN0TMDF037 RSCAN0.TMDF037.UINT32
+#define RSCAN0TMDF037L RSCAN0.TMDF037.UINT16[L]
+#define RSCAN0TMDF037LL RSCAN0.TMDF037.UINT8[LL]
+#define RSCAN0TMDF037LH RSCAN0.TMDF037.UINT8[LH]
+#define RSCAN0TMDF037H RSCAN0.TMDF037.UINT16[H]
+#define RSCAN0TMDF037HL RSCAN0.TMDF037.UINT8[HL]
+#define RSCAN0TMDF037HH RSCAN0.TMDF037.UINT8[HH]
+#define RSCAN0TMDF137 RSCAN0.TMDF137.UINT32
+#define RSCAN0TMDF137L RSCAN0.TMDF137.UINT16[L]
+#define RSCAN0TMDF137LL RSCAN0.TMDF137.UINT8[LL]
+#define RSCAN0TMDF137LH RSCAN0.TMDF137.UINT8[LH]
+#define RSCAN0TMDF137H RSCAN0.TMDF137.UINT16[H]
+#define RSCAN0TMDF137HL RSCAN0.TMDF137.UINT8[HL]
+#define RSCAN0TMDF137HH RSCAN0.TMDF137.UINT8[HH]
+#define RSCAN0TMID38 RSCAN0.TMID38.UINT32
+#define RSCAN0TMID38L RSCAN0.TMID38.UINT16[L]
+#define RSCAN0TMID38LL RSCAN0.TMID38.UINT8[LL]
+#define RSCAN0TMID38LH RSCAN0.TMID38.UINT8[LH]
+#define RSCAN0TMID38H RSCAN0.TMID38.UINT16[H]
+#define RSCAN0TMID38HL RSCAN0.TMID38.UINT8[HL]
+#define RSCAN0TMID38HH RSCAN0.TMID38.UINT8[HH]
+#define RSCAN0TMPTR38 RSCAN0.TMPTR38.UINT32
+#define RSCAN0TMPTR38L RSCAN0.TMPTR38.UINT16[L]
+#define RSCAN0TMPTR38LL RSCAN0.TMPTR38.UINT8[LL]
+#define RSCAN0TMPTR38LH RSCAN0.TMPTR38.UINT8[LH]
+#define RSCAN0TMPTR38H RSCAN0.TMPTR38.UINT16[H]
+#define RSCAN0TMPTR38HL RSCAN0.TMPTR38.UINT8[HL]
+#define RSCAN0TMPTR38HH RSCAN0.TMPTR38.UINT8[HH]
+#define RSCAN0TMDF038 RSCAN0.TMDF038.UINT32
+#define RSCAN0TMDF038L RSCAN0.TMDF038.UINT16[L]
+#define RSCAN0TMDF038LL RSCAN0.TMDF038.UINT8[LL]
+#define RSCAN0TMDF038LH RSCAN0.TMDF038.UINT8[LH]
+#define RSCAN0TMDF038H RSCAN0.TMDF038.UINT16[H]
+#define RSCAN0TMDF038HL RSCAN0.TMDF038.UINT8[HL]
+#define RSCAN0TMDF038HH RSCAN0.TMDF038.UINT8[HH]
+#define RSCAN0TMDF138 RSCAN0.TMDF138.UINT32
+#define RSCAN0TMDF138L RSCAN0.TMDF138.UINT16[L]
+#define RSCAN0TMDF138LL RSCAN0.TMDF138.UINT8[LL]
+#define RSCAN0TMDF138LH RSCAN0.TMDF138.UINT8[LH]
+#define RSCAN0TMDF138H RSCAN0.TMDF138.UINT16[H]
+#define RSCAN0TMDF138HL RSCAN0.TMDF138.UINT8[HL]
+#define RSCAN0TMDF138HH RSCAN0.TMDF138.UINT8[HH]
+#define RSCAN0TMID39 RSCAN0.TMID39.UINT32
+#define RSCAN0TMID39L RSCAN0.TMID39.UINT16[L]
+#define RSCAN0TMID39LL RSCAN0.TMID39.UINT8[LL]
+#define RSCAN0TMID39LH RSCAN0.TMID39.UINT8[LH]
+#define RSCAN0TMID39H RSCAN0.TMID39.UINT16[H]
+#define RSCAN0TMID39HL RSCAN0.TMID39.UINT8[HL]
+#define RSCAN0TMID39HH RSCAN0.TMID39.UINT8[HH]
+#define RSCAN0TMPTR39 RSCAN0.TMPTR39.UINT32
+#define RSCAN0TMPTR39L RSCAN0.TMPTR39.UINT16[L]
+#define RSCAN0TMPTR39LL RSCAN0.TMPTR39.UINT8[LL]
+#define RSCAN0TMPTR39LH RSCAN0.TMPTR39.UINT8[LH]
+#define RSCAN0TMPTR39H RSCAN0.TMPTR39.UINT16[H]
+#define RSCAN0TMPTR39HL RSCAN0.TMPTR39.UINT8[HL]
+#define RSCAN0TMPTR39HH RSCAN0.TMPTR39.UINT8[HH]
+#define RSCAN0TMDF039 RSCAN0.TMDF039.UINT32
+#define RSCAN0TMDF039L RSCAN0.TMDF039.UINT16[L]
+#define RSCAN0TMDF039LL RSCAN0.TMDF039.UINT8[LL]
+#define RSCAN0TMDF039LH RSCAN0.TMDF039.UINT8[LH]
+#define RSCAN0TMDF039H RSCAN0.TMDF039.UINT16[H]
+#define RSCAN0TMDF039HL RSCAN0.TMDF039.UINT8[HL]
+#define RSCAN0TMDF039HH RSCAN0.TMDF039.UINT8[HH]
+#define RSCAN0TMDF139 RSCAN0.TMDF139.UINT32
+#define RSCAN0TMDF139L RSCAN0.TMDF139.UINT16[L]
+#define RSCAN0TMDF139LL RSCAN0.TMDF139.UINT8[LL]
+#define RSCAN0TMDF139LH RSCAN0.TMDF139.UINT8[LH]
+#define RSCAN0TMDF139H RSCAN0.TMDF139.UINT16[H]
+#define RSCAN0TMDF139HL RSCAN0.TMDF139.UINT8[HL]
+#define RSCAN0TMDF139HH RSCAN0.TMDF139.UINT8[HH]
+#define RSCAN0TMID40 RSCAN0.TMID40.UINT32
+#define RSCAN0TMID40L RSCAN0.TMID40.UINT16[L]
+#define RSCAN0TMID40LL RSCAN0.TMID40.UINT8[LL]
+#define RSCAN0TMID40LH RSCAN0.TMID40.UINT8[LH]
+#define RSCAN0TMID40H RSCAN0.TMID40.UINT16[H]
+#define RSCAN0TMID40HL RSCAN0.TMID40.UINT8[HL]
+#define RSCAN0TMID40HH RSCAN0.TMID40.UINT8[HH]
+#define RSCAN0TMPTR40 RSCAN0.TMPTR40.UINT32
+#define RSCAN0TMPTR40L RSCAN0.TMPTR40.UINT16[L]
+#define RSCAN0TMPTR40LL RSCAN0.TMPTR40.UINT8[LL]
+#define RSCAN0TMPTR40LH RSCAN0.TMPTR40.UINT8[LH]
+#define RSCAN0TMPTR40H RSCAN0.TMPTR40.UINT16[H]
+#define RSCAN0TMPTR40HL RSCAN0.TMPTR40.UINT8[HL]
+#define RSCAN0TMPTR40HH RSCAN0.TMPTR40.UINT8[HH]
+#define RSCAN0TMDF040 RSCAN0.TMDF040.UINT32
+#define RSCAN0TMDF040L RSCAN0.TMDF040.UINT16[L]
+#define RSCAN0TMDF040LL RSCAN0.TMDF040.UINT8[LL]
+#define RSCAN0TMDF040LH RSCAN0.TMDF040.UINT8[LH]
+#define RSCAN0TMDF040H RSCAN0.TMDF040.UINT16[H]
+#define RSCAN0TMDF040HL RSCAN0.TMDF040.UINT8[HL]
+#define RSCAN0TMDF040HH RSCAN0.TMDF040.UINT8[HH]
+#define RSCAN0TMDF140 RSCAN0.TMDF140.UINT32
+#define RSCAN0TMDF140L RSCAN0.TMDF140.UINT16[L]
+#define RSCAN0TMDF140LL RSCAN0.TMDF140.UINT8[LL]
+#define RSCAN0TMDF140LH RSCAN0.TMDF140.UINT8[LH]
+#define RSCAN0TMDF140H RSCAN0.TMDF140.UINT16[H]
+#define RSCAN0TMDF140HL RSCAN0.TMDF140.UINT8[HL]
+#define RSCAN0TMDF140HH RSCAN0.TMDF140.UINT8[HH]
+#define RSCAN0TMID41 RSCAN0.TMID41.UINT32
+#define RSCAN0TMID41L RSCAN0.TMID41.UINT16[L]
+#define RSCAN0TMID41LL RSCAN0.TMID41.UINT8[LL]
+#define RSCAN0TMID41LH RSCAN0.TMID41.UINT8[LH]
+#define RSCAN0TMID41H RSCAN0.TMID41.UINT16[H]
+#define RSCAN0TMID41HL RSCAN0.TMID41.UINT8[HL]
+#define RSCAN0TMID41HH RSCAN0.TMID41.UINT8[HH]
+#define RSCAN0TMPTR41 RSCAN0.TMPTR41.UINT32
+#define RSCAN0TMPTR41L RSCAN0.TMPTR41.UINT16[L]
+#define RSCAN0TMPTR41LL RSCAN0.TMPTR41.UINT8[LL]
+#define RSCAN0TMPTR41LH RSCAN0.TMPTR41.UINT8[LH]
+#define RSCAN0TMPTR41H RSCAN0.TMPTR41.UINT16[H]
+#define RSCAN0TMPTR41HL RSCAN0.TMPTR41.UINT8[HL]
+#define RSCAN0TMPTR41HH RSCAN0.TMPTR41.UINT8[HH]
+#define RSCAN0TMDF041 RSCAN0.TMDF041.UINT32
+#define RSCAN0TMDF041L RSCAN0.TMDF041.UINT16[L]
+#define RSCAN0TMDF041LL RSCAN0.TMDF041.UINT8[LL]
+#define RSCAN0TMDF041LH RSCAN0.TMDF041.UINT8[LH]
+#define RSCAN0TMDF041H RSCAN0.TMDF041.UINT16[H]
+#define RSCAN0TMDF041HL RSCAN0.TMDF041.UINT8[HL]
+#define RSCAN0TMDF041HH RSCAN0.TMDF041.UINT8[HH]
+#define RSCAN0TMDF141 RSCAN0.TMDF141.UINT32
+#define RSCAN0TMDF141L RSCAN0.TMDF141.UINT16[L]
+#define RSCAN0TMDF141LL RSCAN0.TMDF141.UINT8[LL]
+#define RSCAN0TMDF141LH RSCAN0.TMDF141.UINT8[LH]
+#define RSCAN0TMDF141H RSCAN0.TMDF141.UINT16[H]
+#define RSCAN0TMDF141HL RSCAN0.TMDF141.UINT8[HL]
+#define RSCAN0TMDF141HH RSCAN0.TMDF141.UINT8[HH]
+#define RSCAN0TMID42 RSCAN0.TMID42.UINT32
+#define RSCAN0TMID42L RSCAN0.TMID42.UINT16[L]
+#define RSCAN0TMID42LL RSCAN0.TMID42.UINT8[LL]
+#define RSCAN0TMID42LH RSCAN0.TMID42.UINT8[LH]
+#define RSCAN0TMID42H RSCAN0.TMID42.UINT16[H]
+#define RSCAN0TMID42HL RSCAN0.TMID42.UINT8[HL]
+#define RSCAN0TMID42HH RSCAN0.TMID42.UINT8[HH]
+#define RSCAN0TMPTR42 RSCAN0.TMPTR42.UINT32
+#define RSCAN0TMPTR42L RSCAN0.TMPTR42.UINT16[L]
+#define RSCAN0TMPTR42LL RSCAN0.TMPTR42.UINT8[LL]
+#define RSCAN0TMPTR42LH RSCAN0.TMPTR42.UINT8[LH]
+#define RSCAN0TMPTR42H RSCAN0.TMPTR42.UINT16[H]
+#define RSCAN0TMPTR42HL RSCAN0.TMPTR42.UINT8[HL]
+#define RSCAN0TMPTR42HH RSCAN0.TMPTR42.UINT8[HH]
+#define RSCAN0TMDF042 RSCAN0.TMDF042.UINT32
+#define RSCAN0TMDF042L RSCAN0.TMDF042.UINT16[L]
+#define RSCAN0TMDF042LL RSCAN0.TMDF042.UINT8[LL]
+#define RSCAN0TMDF042LH RSCAN0.TMDF042.UINT8[LH]
+#define RSCAN0TMDF042H RSCAN0.TMDF042.UINT16[H]
+#define RSCAN0TMDF042HL RSCAN0.TMDF042.UINT8[HL]
+#define RSCAN0TMDF042HH RSCAN0.TMDF042.UINT8[HH]
+#define RSCAN0TMDF142 RSCAN0.TMDF142.UINT32
+#define RSCAN0TMDF142L RSCAN0.TMDF142.UINT16[L]
+#define RSCAN0TMDF142LL RSCAN0.TMDF142.UINT8[LL]
+#define RSCAN0TMDF142LH RSCAN0.TMDF142.UINT8[LH]
+#define RSCAN0TMDF142H RSCAN0.TMDF142.UINT16[H]
+#define RSCAN0TMDF142HL RSCAN0.TMDF142.UINT8[HL]
+#define RSCAN0TMDF142HH RSCAN0.TMDF142.UINT8[HH]
+#define RSCAN0TMID43 RSCAN0.TMID43.UINT32
+#define RSCAN0TMID43L RSCAN0.TMID43.UINT16[L]
+#define RSCAN0TMID43LL RSCAN0.TMID43.UINT8[LL]
+#define RSCAN0TMID43LH RSCAN0.TMID43.UINT8[LH]
+#define RSCAN0TMID43H RSCAN0.TMID43.UINT16[H]
+#define RSCAN0TMID43HL RSCAN0.TMID43.UINT8[HL]
+#define RSCAN0TMID43HH RSCAN0.TMID43.UINT8[HH]
+#define RSCAN0TMPTR43 RSCAN0.TMPTR43.UINT32
+#define RSCAN0TMPTR43L RSCAN0.TMPTR43.UINT16[L]
+#define RSCAN0TMPTR43LL RSCAN0.TMPTR43.UINT8[LL]
+#define RSCAN0TMPTR43LH RSCAN0.TMPTR43.UINT8[LH]
+#define RSCAN0TMPTR43H RSCAN0.TMPTR43.UINT16[H]
+#define RSCAN0TMPTR43HL RSCAN0.TMPTR43.UINT8[HL]
+#define RSCAN0TMPTR43HH RSCAN0.TMPTR43.UINT8[HH]
+#define RSCAN0TMDF043 RSCAN0.TMDF043.UINT32
+#define RSCAN0TMDF043L RSCAN0.TMDF043.UINT16[L]
+#define RSCAN0TMDF043LL RSCAN0.TMDF043.UINT8[LL]
+#define RSCAN0TMDF043LH RSCAN0.TMDF043.UINT8[LH]
+#define RSCAN0TMDF043H RSCAN0.TMDF043.UINT16[H]
+#define RSCAN0TMDF043HL RSCAN0.TMDF043.UINT8[HL]
+#define RSCAN0TMDF043HH RSCAN0.TMDF043.UINT8[HH]
+#define RSCAN0TMDF143 RSCAN0.TMDF143.UINT32
+#define RSCAN0TMDF143L RSCAN0.TMDF143.UINT16[L]
+#define RSCAN0TMDF143LL RSCAN0.TMDF143.UINT8[LL]
+#define RSCAN0TMDF143LH RSCAN0.TMDF143.UINT8[LH]
+#define RSCAN0TMDF143H RSCAN0.TMDF143.UINT16[H]
+#define RSCAN0TMDF143HL RSCAN0.TMDF143.UINT8[HL]
+#define RSCAN0TMDF143HH RSCAN0.TMDF143.UINT8[HH]
+#define RSCAN0TMID44 RSCAN0.TMID44.UINT32
+#define RSCAN0TMID44L RSCAN0.TMID44.UINT16[L]
+#define RSCAN0TMID44LL RSCAN0.TMID44.UINT8[LL]
+#define RSCAN0TMID44LH RSCAN0.TMID44.UINT8[LH]
+#define RSCAN0TMID44H RSCAN0.TMID44.UINT16[H]
+#define RSCAN0TMID44HL RSCAN0.TMID44.UINT8[HL]
+#define RSCAN0TMID44HH RSCAN0.TMID44.UINT8[HH]
+#define RSCAN0TMPTR44 RSCAN0.TMPTR44.UINT32
+#define RSCAN0TMPTR44L RSCAN0.TMPTR44.UINT16[L]
+#define RSCAN0TMPTR44LL RSCAN0.TMPTR44.UINT8[LL]
+#define RSCAN0TMPTR44LH RSCAN0.TMPTR44.UINT8[LH]
+#define RSCAN0TMPTR44H RSCAN0.TMPTR44.UINT16[H]
+#define RSCAN0TMPTR44HL RSCAN0.TMPTR44.UINT8[HL]
+#define RSCAN0TMPTR44HH RSCAN0.TMPTR44.UINT8[HH]
+#define RSCAN0TMDF044 RSCAN0.TMDF044.UINT32
+#define RSCAN0TMDF044L RSCAN0.TMDF044.UINT16[L]
+#define RSCAN0TMDF044LL RSCAN0.TMDF044.UINT8[LL]
+#define RSCAN0TMDF044LH RSCAN0.TMDF044.UINT8[LH]
+#define RSCAN0TMDF044H RSCAN0.TMDF044.UINT16[H]
+#define RSCAN0TMDF044HL RSCAN0.TMDF044.UINT8[HL]
+#define RSCAN0TMDF044HH RSCAN0.TMDF044.UINT8[HH]
+#define RSCAN0TMDF144 RSCAN0.TMDF144.UINT32
+#define RSCAN0TMDF144L RSCAN0.TMDF144.UINT16[L]
+#define RSCAN0TMDF144LL RSCAN0.TMDF144.UINT8[LL]
+#define RSCAN0TMDF144LH RSCAN0.TMDF144.UINT8[LH]
+#define RSCAN0TMDF144H RSCAN0.TMDF144.UINT16[H]
+#define RSCAN0TMDF144HL RSCAN0.TMDF144.UINT8[HL]
+#define RSCAN0TMDF144HH RSCAN0.TMDF144.UINT8[HH]
+#define RSCAN0TMID45 RSCAN0.TMID45.UINT32
+#define RSCAN0TMID45L RSCAN0.TMID45.UINT16[L]
+#define RSCAN0TMID45LL RSCAN0.TMID45.UINT8[LL]
+#define RSCAN0TMID45LH RSCAN0.TMID45.UINT8[LH]
+#define RSCAN0TMID45H RSCAN0.TMID45.UINT16[H]
+#define RSCAN0TMID45HL RSCAN0.TMID45.UINT8[HL]
+#define RSCAN0TMID45HH RSCAN0.TMID45.UINT8[HH]
+#define RSCAN0TMPTR45 RSCAN0.TMPTR45.UINT32
+#define RSCAN0TMPTR45L RSCAN0.TMPTR45.UINT16[L]
+#define RSCAN0TMPTR45LL RSCAN0.TMPTR45.UINT8[LL]
+#define RSCAN0TMPTR45LH RSCAN0.TMPTR45.UINT8[LH]
+#define RSCAN0TMPTR45H RSCAN0.TMPTR45.UINT16[H]
+#define RSCAN0TMPTR45HL RSCAN0.TMPTR45.UINT8[HL]
+#define RSCAN0TMPTR45HH RSCAN0.TMPTR45.UINT8[HH]
+#define RSCAN0TMDF045 RSCAN0.TMDF045.UINT32
+#define RSCAN0TMDF045L RSCAN0.TMDF045.UINT16[L]
+#define RSCAN0TMDF045LL RSCAN0.TMDF045.UINT8[LL]
+#define RSCAN0TMDF045LH RSCAN0.TMDF045.UINT8[LH]
+#define RSCAN0TMDF045H RSCAN0.TMDF045.UINT16[H]
+#define RSCAN0TMDF045HL RSCAN0.TMDF045.UINT8[HL]
+#define RSCAN0TMDF045HH RSCAN0.TMDF045.UINT8[HH]
+#define RSCAN0TMDF145 RSCAN0.TMDF145.UINT32
+#define RSCAN0TMDF145L RSCAN0.TMDF145.UINT16[L]
+#define RSCAN0TMDF145LL RSCAN0.TMDF145.UINT8[LL]
+#define RSCAN0TMDF145LH RSCAN0.TMDF145.UINT8[LH]
+#define RSCAN0TMDF145H RSCAN0.TMDF145.UINT16[H]
+#define RSCAN0TMDF145HL RSCAN0.TMDF145.UINT8[HL]
+#define RSCAN0TMDF145HH RSCAN0.TMDF145.UINT8[HH]
+#define RSCAN0TMID46 RSCAN0.TMID46.UINT32
+#define RSCAN0TMID46L RSCAN0.TMID46.UINT16[L]
+#define RSCAN0TMID46LL RSCAN0.TMID46.UINT8[LL]
+#define RSCAN0TMID46LH RSCAN0.TMID46.UINT8[LH]
+#define RSCAN0TMID46H RSCAN0.TMID46.UINT16[H]
+#define RSCAN0TMID46HL RSCAN0.TMID46.UINT8[HL]
+#define RSCAN0TMID46HH RSCAN0.TMID46.UINT8[HH]
+#define RSCAN0TMPTR46 RSCAN0.TMPTR46.UINT32
+#define RSCAN0TMPTR46L RSCAN0.TMPTR46.UINT16[L]
+#define RSCAN0TMPTR46LL RSCAN0.TMPTR46.UINT8[LL]
+#define RSCAN0TMPTR46LH RSCAN0.TMPTR46.UINT8[LH]
+#define RSCAN0TMPTR46H RSCAN0.TMPTR46.UINT16[H]
+#define RSCAN0TMPTR46HL RSCAN0.TMPTR46.UINT8[HL]
+#define RSCAN0TMPTR46HH RSCAN0.TMPTR46.UINT8[HH]
+#define RSCAN0TMDF046 RSCAN0.TMDF046.UINT32
+#define RSCAN0TMDF046L RSCAN0.TMDF046.UINT16[L]
+#define RSCAN0TMDF046LL RSCAN0.TMDF046.UINT8[LL]
+#define RSCAN0TMDF046LH RSCAN0.TMDF046.UINT8[LH]
+#define RSCAN0TMDF046H RSCAN0.TMDF046.UINT16[H]
+#define RSCAN0TMDF046HL RSCAN0.TMDF046.UINT8[HL]
+#define RSCAN0TMDF046HH RSCAN0.TMDF046.UINT8[HH]
+#define RSCAN0TMDF146 RSCAN0.TMDF146.UINT32
+#define RSCAN0TMDF146L RSCAN0.TMDF146.UINT16[L]
+#define RSCAN0TMDF146LL RSCAN0.TMDF146.UINT8[LL]
+#define RSCAN0TMDF146LH RSCAN0.TMDF146.UINT8[LH]
+#define RSCAN0TMDF146H RSCAN0.TMDF146.UINT16[H]
+#define RSCAN0TMDF146HL RSCAN0.TMDF146.UINT8[HL]
+#define RSCAN0TMDF146HH RSCAN0.TMDF146.UINT8[HH]
+#define RSCAN0TMID47 RSCAN0.TMID47.UINT32
+#define RSCAN0TMID47L RSCAN0.TMID47.UINT16[L]
+#define RSCAN0TMID47LL RSCAN0.TMID47.UINT8[LL]
+#define RSCAN0TMID47LH RSCAN0.TMID47.UINT8[LH]
+#define RSCAN0TMID47H RSCAN0.TMID47.UINT16[H]
+#define RSCAN0TMID47HL RSCAN0.TMID47.UINT8[HL]
+#define RSCAN0TMID47HH RSCAN0.TMID47.UINT8[HH]
+#define RSCAN0TMPTR47 RSCAN0.TMPTR47.UINT32
+#define RSCAN0TMPTR47L RSCAN0.TMPTR47.UINT16[L]
+#define RSCAN0TMPTR47LL RSCAN0.TMPTR47.UINT8[LL]
+#define RSCAN0TMPTR47LH RSCAN0.TMPTR47.UINT8[LH]
+#define RSCAN0TMPTR47H RSCAN0.TMPTR47.UINT16[H]
+#define RSCAN0TMPTR47HL RSCAN0.TMPTR47.UINT8[HL]
+#define RSCAN0TMPTR47HH RSCAN0.TMPTR47.UINT8[HH]
+#define RSCAN0TMDF047 RSCAN0.TMDF047.UINT32
+#define RSCAN0TMDF047L RSCAN0.TMDF047.UINT16[L]
+#define RSCAN0TMDF047LL RSCAN0.TMDF047.UINT8[LL]
+#define RSCAN0TMDF047LH RSCAN0.TMDF047.UINT8[LH]
+#define RSCAN0TMDF047H RSCAN0.TMDF047.UINT16[H]
+#define RSCAN0TMDF047HL RSCAN0.TMDF047.UINT8[HL]
+#define RSCAN0TMDF047HH RSCAN0.TMDF047.UINT8[HH]
+#define RSCAN0TMDF147 RSCAN0.TMDF147.UINT32
+#define RSCAN0TMDF147L RSCAN0.TMDF147.UINT16[L]
+#define RSCAN0TMDF147LL RSCAN0.TMDF147.UINT8[LL]
+#define RSCAN0TMDF147LH RSCAN0.TMDF147.UINT8[LH]
+#define RSCAN0TMDF147H RSCAN0.TMDF147.UINT16[H]
+#define RSCAN0TMDF147HL RSCAN0.TMDF147.UINT8[HL]
+#define RSCAN0TMDF147HH RSCAN0.TMDF147.UINT8[HH]
+#define RSCAN0TMID48 RSCAN0.TMID48.UINT32
+#define RSCAN0TMID48L RSCAN0.TMID48.UINT16[L]
+#define RSCAN0TMID48LL RSCAN0.TMID48.UINT8[LL]
+#define RSCAN0TMID48LH RSCAN0.TMID48.UINT8[LH]
+#define RSCAN0TMID48H RSCAN0.TMID48.UINT16[H]
+#define RSCAN0TMID48HL RSCAN0.TMID48.UINT8[HL]
+#define RSCAN0TMID48HH RSCAN0.TMID48.UINT8[HH]
+#define RSCAN0TMPTR48 RSCAN0.TMPTR48.UINT32
+#define RSCAN0TMPTR48L RSCAN0.TMPTR48.UINT16[L]
+#define RSCAN0TMPTR48LL RSCAN0.TMPTR48.UINT8[LL]
+#define RSCAN0TMPTR48LH RSCAN0.TMPTR48.UINT8[LH]
+#define RSCAN0TMPTR48H RSCAN0.TMPTR48.UINT16[H]
+#define RSCAN0TMPTR48HL RSCAN0.TMPTR48.UINT8[HL]
+#define RSCAN0TMPTR48HH RSCAN0.TMPTR48.UINT8[HH]
+#define RSCAN0TMDF048 RSCAN0.TMDF048.UINT32
+#define RSCAN0TMDF048L RSCAN0.TMDF048.UINT16[L]
+#define RSCAN0TMDF048LL RSCAN0.TMDF048.UINT8[LL]
+#define RSCAN0TMDF048LH RSCAN0.TMDF048.UINT8[LH]
+#define RSCAN0TMDF048H RSCAN0.TMDF048.UINT16[H]
+#define RSCAN0TMDF048HL RSCAN0.TMDF048.UINT8[HL]
+#define RSCAN0TMDF048HH RSCAN0.TMDF048.UINT8[HH]
+#define RSCAN0TMDF148 RSCAN0.TMDF148.UINT32
+#define RSCAN0TMDF148L RSCAN0.TMDF148.UINT16[L]
+#define RSCAN0TMDF148LL RSCAN0.TMDF148.UINT8[LL]
+#define RSCAN0TMDF148LH RSCAN0.TMDF148.UINT8[LH]
+#define RSCAN0TMDF148H RSCAN0.TMDF148.UINT16[H]
+#define RSCAN0TMDF148HL RSCAN0.TMDF148.UINT8[HL]
+#define RSCAN0TMDF148HH RSCAN0.TMDF148.UINT8[HH]
+#define RSCAN0TMID49 RSCAN0.TMID49.UINT32
+#define RSCAN0TMID49L RSCAN0.TMID49.UINT16[L]
+#define RSCAN0TMID49LL RSCAN0.TMID49.UINT8[LL]
+#define RSCAN0TMID49LH RSCAN0.TMID49.UINT8[LH]
+#define RSCAN0TMID49H RSCAN0.TMID49.UINT16[H]
+#define RSCAN0TMID49HL RSCAN0.TMID49.UINT8[HL]
+#define RSCAN0TMID49HH RSCAN0.TMID49.UINT8[HH]
+#define RSCAN0TMPTR49 RSCAN0.TMPTR49.UINT32
+#define RSCAN0TMPTR49L RSCAN0.TMPTR49.UINT16[L]
+#define RSCAN0TMPTR49LL RSCAN0.TMPTR49.UINT8[LL]
+#define RSCAN0TMPTR49LH RSCAN0.TMPTR49.UINT8[LH]
+#define RSCAN0TMPTR49H RSCAN0.TMPTR49.UINT16[H]
+#define RSCAN0TMPTR49HL RSCAN0.TMPTR49.UINT8[HL]
+#define RSCAN0TMPTR49HH RSCAN0.TMPTR49.UINT8[HH]
+#define RSCAN0TMDF049 RSCAN0.TMDF049.UINT32
+#define RSCAN0TMDF049L RSCAN0.TMDF049.UINT16[L]
+#define RSCAN0TMDF049LL RSCAN0.TMDF049.UINT8[LL]
+#define RSCAN0TMDF049LH RSCAN0.TMDF049.UINT8[LH]
+#define RSCAN0TMDF049H RSCAN0.TMDF049.UINT16[H]
+#define RSCAN0TMDF049HL RSCAN0.TMDF049.UINT8[HL]
+#define RSCAN0TMDF049HH RSCAN0.TMDF049.UINT8[HH]
+#define RSCAN0TMDF149 RSCAN0.TMDF149.UINT32
+#define RSCAN0TMDF149L RSCAN0.TMDF149.UINT16[L]
+#define RSCAN0TMDF149LL RSCAN0.TMDF149.UINT8[LL]
+#define RSCAN0TMDF149LH RSCAN0.TMDF149.UINT8[LH]
+#define RSCAN0TMDF149H RSCAN0.TMDF149.UINT16[H]
+#define RSCAN0TMDF149HL RSCAN0.TMDF149.UINT8[HL]
+#define RSCAN0TMDF149HH RSCAN0.TMDF149.UINT8[HH]
+#define RSCAN0TMID50 RSCAN0.TMID50.UINT32
+#define RSCAN0TMID50L RSCAN0.TMID50.UINT16[L]
+#define RSCAN0TMID50LL RSCAN0.TMID50.UINT8[LL]
+#define RSCAN0TMID50LH RSCAN0.TMID50.UINT8[LH]
+#define RSCAN0TMID50H RSCAN0.TMID50.UINT16[H]
+#define RSCAN0TMID50HL RSCAN0.TMID50.UINT8[HL]
+#define RSCAN0TMID50HH RSCAN0.TMID50.UINT8[HH]
+#define RSCAN0TMPTR50 RSCAN0.TMPTR50.UINT32
+#define RSCAN0TMPTR50L RSCAN0.TMPTR50.UINT16[L]
+#define RSCAN0TMPTR50LL RSCAN0.TMPTR50.UINT8[LL]
+#define RSCAN0TMPTR50LH RSCAN0.TMPTR50.UINT8[LH]
+#define RSCAN0TMPTR50H RSCAN0.TMPTR50.UINT16[H]
+#define RSCAN0TMPTR50HL RSCAN0.TMPTR50.UINT8[HL]
+#define RSCAN0TMPTR50HH RSCAN0.TMPTR50.UINT8[HH]
+#define RSCAN0TMDF050 RSCAN0.TMDF050.UINT32
+#define RSCAN0TMDF050L RSCAN0.TMDF050.UINT16[L]
+#define RSCAN0TMDF050LL RSCAN0.TMDF050.UINT8[LL]
+#define RSCAN0TMDF050LH RSCAN0.TMDF050.UINT8[LH]
+#define RSCAN0TMDF050H RSCAN0.TMDF050.UINT16[H]
+#define RSCAN0TMDF050HL RSCAN0.TMDF050.UINT8[HL]
+#define RSCAN0TMDF050HH RSCAN0.TMDF050.UINT8[HH]
+#define RSCAN0TMDF150 RSCAN0.TMDF150.UINT32
+#define RSCAN0TMDF150L RSCAN0.TMDF150.UINT16[L]
+#define RSCAN0TMDF150LL RSCAN0.TMDF150.UINT8[LL]
+#define RSCAN0TMDF150LH RSCAN0.TMDF150.UINT8[LH]
+#define RSCAN0TMDF150H RSCAN0.TMDF150.UINT16[H]
+#define RSCAN0TMDF150HL RSCAN0.TMDF150.UINT8[HL]
+#define RSCAN0TMDF150HH RSCAN0.TMDF150.UINT8[HH]
+#define RSCAN0TMID51 RSCAN0.TMID51.UINT32
+#define RSCAN0TMID51L RSCAN0.TMID51.UINT16[L]
+#define RSCAN0TMID51LL RSCAN0.TMID51.UINT8[LL]
+#define RSCAN0TMID51LH RSCAN0.TMID51.UINT8[LH]
+#define RSCAN0TMID51H RSCAN0.TMID51.UINT16[H]
+#define RSCAN0TMID51HL RSCAN0.TMID51.UINT8[HL]
+#define RSCAN0TMID51HH RSCAN0.TMID51.UINT8[HH]
+#define RSCAN0TMPTR51 RSCAN0.TMPTR51.UINT32
+#define RSCAN0TMPTR51L RSCAN0.TMPTR51.UINT16[L]
+#define RSCAN0TMPTR51LL RSCAN0.TMPTR51.UINT8[LL]
+#define RSCAN0TMPTR51LH RSCAN0.TMPTR51.UINT8[LH]
+#define RSCAN0TMPTR51H RSCAN0.TMPTR51.UINT16[H]
+#define RSCAN0TMPTR51HL RSCAN0.TMPTR51.UINT8[HL]
+#define RSCAN0TMPTR51HH RSCAN0.TMPTR51.UINT8[HH]
+#define RSCAN0TMDF051 RSCAN0.TMDF051.UINT32
+#define RSCAN0TMDF051L RSCAN0.TMDF051.UINT16[L]
+#define RSCAN0TMDF051LL RSCAN0.TMDF051.UINT8[LL]
+#define RSCAN0TMDF051LH RSCAN0.TMDF051.UINT8[LH]
+#define RSCAN0TMDF051H RSCAN0.TMDF051.UINT16[H]
+#define RSCAN0TMDF051HL RSCAN0.TMDF051.UINT8[HL]
+#define RSCAN0TMDF051HH RSCAN0.TMDF051.UINT8[HH]
+#define RSCAN0TMDF151 RSCAN0.TMDF151.UINT32
+#define RSCAN0TMDF151L RSCAN0.TMDF151.UINT16[L]
+#define RSCAN0TMDF151LL RSCAN0.TMDF151.UINT8[LL]
+#define RSCAN0TMDF151LH RSCAN0.TMDF151.UINT8[LH]
+#define RSCAN0TMDF151H RSCAN0.TMDF151.UINT16[H]
+#define RSCAN0TMDF151HL RSCAN0.TMDF151.UINT8[HL]
+#define RSCAN0TMDF151HH RSCAN0.TMDF151.UINT8[HH]
+#define RSCAN0TMID52 RSCAN0.TMID52.UINT32
+#define RSCAN0TMID52L RSCAN0.TMID52.UINT16[L]
+#define RSCAN0TMID52LL RSCAN0.TMID52.UINT8[LL]
+#define RSCAN0TMID52LH RSCAN0.TMID52.UINT8[LH]
+#define RSCAN0TMID52H RSCAN0.TMID52.UINT16[H]
+#define RSCAN0TMID52HL RSCAN0.TMID52.UINT8[HL]
+#define RSCAN0TMID52HH RSCAN0.TMID52.UINT8[HH]
+#define RSCAN0TMPTR52 RSCAN0.TMPTR52.UINT32
+#define RSCAN0TMPTR52L RSCAN0.TMPTR52.UINT16[L]
+#define RSCAN0TMPTR52LL RSCAN0.TMPTR52.UINT8[LL]
+#define RSCAN0TMPTR52LH RSCAN0.TMPTR52.UINT8[LH]
+#define RSCAN0TMPTR52H RSCAN0.TMPTR52.UINT16[H]
+#define RSCAN0TMPTR52HL RSCAN0.TMPTR52.UINT8[HL]
+#define RSCAN0TMPTR52HH RSCAN0.TMPTR52.UINT8[HH]
+#define RSCAN0TMDF052 RSCAN0.TMDF052.UINT32
+#define RSCAN0TMDF052L RSCAN0.TMDF052.UINT16[L]
+#define RSCAN0TMDF052LL RSCAN0.TMDF052.UINT8[LL]
+#define RSCAN0TMDF052LH RSCAN0.TMDF052.UINT8[LH]
+#define RSCAN0TMDF052H RSCAN0.TMDF052.UINT16[H]
+#define RSCAN0TMDF052HL RSCAN0.TMDF052.UINT8[HL]
+#define RSCAN0TMDF052HH RSCAN0.TMDF052.UINT8[HH]
+#define RSCAN0TMDF152 RSCAN0.TMDF152.UINT32
+#define RSCAN0TMDF152L RSCAN0.TMDF152.UINT16[L]
+#define RSCAN0TMDF152LL RSCAN0.TMDF152.UINT8[LL]
+#define RSCAN0TMDF152LH RSCAN0.TMDF152.UINT8[LH]
+#define RSCAN0TMDF152H RSCAN0.TMDF152.UINT16[H]
+#define RSCAN0TMDF152HL RSCAN0.TMDF152.UINT8[HL]
+#define RSCAN0TMDF152HH RSCAN0.TMDF152.UINT8[HH]
+#define RSCAN0TMID53 RSCAN0.TMID53.UINT32
+#define RSCAN0TMID53L RSCAN0.TMID53.UINT16[L]
+#define RSCAN0TMID53LL RSCAN0.TMID53.UINT8[LL]
+#define RSCAN0TMID53LH RSCAN0.TMID53.UINT8[LH]
+#define RSCAN0TMID53H RSCAN0.TMID53.UINT16[H]
+#define RSCAN0TMID53HL RSCAN0.TMID53.UINT8[HL]
+#define RSCAN0TMID53HH RSCAN0.TMID53.UINT8[HH]
+#define RSCAN0TMPTR53 RSCAN0.TMPTR53.UINT32
+#define RSCAN0TMPTR53L RSCAN0.TMPTR53.UINT16[L]
+#define RSCAN0TMPTR53LL RSCAN0.TMPTR53.UINT8[LL]
+#define RSCAN0TMPTR53LH RSCAN0.TMPTR53.UINT8[LH]
+#define RSCAN0TMPTR53H RSCAN0.TMPTR53.UINT16[H]
+#define RSCAN0TMPTR53HL RSCAN0.TMPTR53.UINT8[HL]
+#define RSCAN0TMPTR53HH RSCAN0.TMPTR53.UINT8[HH]
+#define RSCAN0TMDF053 RSCAN0.TMDF053.UINT32
+#define RSCAN0TMDF053L RSCAN0.TMDF053.UINT16[L]
+#define RSCAN0TMDF053LL RSCAN0.TMDF053.UINT8[LL]
+#define RSCAN0TMDF053LH RSCAN0.TMDF053.UINT8[LH]
+#define RSCAN0TMDF053H RSCAN0.TMDF053.UINT16[H]
+#define RSCAN0TMDF053HL RSCAN0.TMDF053.UINT8[HL]
+#define RSCAN0TMDF053HH RSCAN0.TMDF053.UINT8[HH]
+#define RSCAN0TMDF153 RSCAN0.TMDF153.UINT32
+#define RSCAN0TMDF153L RSCAN0.TMDF153.UINT16[L]
+#define RSCAN0TMDF153LL RSCAN0.TMDF153.UINT8[LL]
+#define RSCAN0TMDF153LH RSCAN0.TMDF153.UINT8[LH]
+#define RSCAN0TMDF153H RSCAN0.TMDF153.UINT16[H]
+#define RSCAN0TMDF153HL RSCAN0.TMDF153.UINT8[HL]
+#define RSCAN0TMDF153HH RSCAN0.TMDF153.UINT8[HH]
+#define RSCAN0TMID54 RSCAN0.TMID54.UINT32
+#define RSCAN0TMID54L RSCAN0.TMID54.UINT16[L]
+#define RSCAN0TMID54LL RSCAN0.TMID54.UINT8[LL]
+#define RSCAN0TMID54LH RSCAN0.TMID54.UINT8[LH]
+#define RSCAN0TMID54H RSCAN0.TMID54.UINT16[H]
+#define RSCAN0TMID54HL RSCAN0.TMID54.UINT8[HL]
+#define RSCAN0TMID54HH RSCAN0.TMID54.UINT8[HH]
+#define RSCAN0TMPTR54 RSCAN0.TMPTR54.UINT32
+#define RSCAN0TMPTR54L RSCAN0.TMPTR54.UINT16[L]
+#define RSCAN0TMPTR54LL RSCAN0.TMPTR54.UINT8[LL]
+#define RSCAN0TMPTR54LH RSCAN0.TMPTR54.UINT8[LH]
+#define RSCAN0TMPTR54H RSCAN0.TMPTR54.UINT16[H]
+#define RSCAN0TMPTR54HL RSCAN0.TMPTR54.UINT8[HL]
+#define RSCAN0TMPTR54HH RSCAN0.TMPTR54.UINT8[HH]
+#define RSCAN0TMDF054 RSCAN0.TMDF054.UINT32
+#define RSCAN0TMDF054L RSCAN0.TMDF054.UINT16[L]
+#define RSCAN0TMDF054LL RSCAN0.TMDF054.UINT8[LL]
+#define RSCAN0TMDF054LH RSCAN0.TMDF054.UINT8[LH]
+#define RSCAN0TMDF054H RSCAN0.TMDF054.UINT16[H]
+#define RSCAN0TMDF054HL RSCAN0.TMDF054.UINT8[HL]
+#define RSCAN0TMDF054HH RSCAN0.TMDF054.UINT8[HH]
+#define RSCAN0TMDF154 RSCAN0.TMDF154.UINT32
+#define RSCAN0TMDF154L RSCAN0.TMDF154.UINT16[L]
+#define RSCAN0TMDF154LL RSCAN0.TMDF154.UINT8[LL]
+#define RSCAN0TMDF154LH RSCAN0.TMDF154.UINT8[LH]
+#define RSCAN0TMDF154H RSCAN0.TMDF154.UINT16[H]
+#define RSCAN0TMDF154HL RSCAN0.TMDF154.UINT8[HL]
+#define RSCAN0TMDF154HH RSCAN0.TMDF154.UINT8[HH]
+#define RSCAN0TMID55 RSCAN0.TMID55.UINT32
+#define RSCAN0TMID55L RSCAN0.TMID55.UINT16[L]
+#define RSCAN0TMID55LL RSCAN0.TMID55.UINT8[LL]
+#define RSCAN0TMID55LH RSCAN0.TMID55.UINT8[LH]
+#define RSCAN0TMID55H RSCAN0.TMID55.UINT16[H]
+#define RSCAN0TMID55HL RSCAN0.TMID55.UINT8[HL]
+#define RSCAN0TMID55HH RSCAN0.TMID55.UINT8[HH]
+#define RSCAN0TMPTR55 RSCAN0.TMPTR55.UINT32
+#define RSCAN0TMPTR55L RSCAN0.TMPTR55.UINT16[L]
+#define RSCAN0TMPTR55LL RSCAN0.TMPTR55.UINT8[LL]
+#define RSCAN0TMPTR55LH RSCAN0.TMPTR55.UINT8[LH]
+#define RSCAN0TMPTR55H RSCAN0.TMPTR55.UINT16[H]
+#define RSCAN0TMPTR55HL RSCAN0.TMPTR55.UINT8[HL]
+#define RSCAN0TMPTR55HH RSCAN0.TMPTR55.UINT8[HH]
+#define RSCAN0TMDF055 RSCAN0.TMDF055.UINT32
+#define RSCAN0TMDF055L RSCAN0.TMDF055.UINT16[L]
+#define RSCAN0TMDF055LL RSCAN0.TMDF055.UINT8[LL]
+#define RSCAN0TMDF055LH RSCAN0.TMDF055.UINT8[LH]
+#define RSCAN0TMDF055H RSCAN0.TMDF055.UINT16[H]
+#define RSCAN0TMDF055HL RSCAN0.TMDF055.UINT8[HL]
+#define RSCAN0TMDF055HH RSCAN0.TMDF055.UINT8[HH]
+#define RSCAN0TMDF155 RSCAN0.TMDF155.UINT32
+#define RSCAN0TMDF155L RSCAN0.TMDF155.UINT16[L]
+#define RSCAN0TMDF155LL RSCAN0.TMDF155.UINT8[LL]
+#define RSCAN0TMDF155LH RSCAN0.TMDF155.UINT8[LH]
+#define RSCAN0TMDF155H RSCAN0.TMDF155.UINT16[H]
+#define RSCAN0TMDF155HL RSCAN0.TMDF155.UINT8[HL]
+#define RSCAN0TMDF155HH RSCAN0.TMDF155.UINT8[HH]
+#define RSCAN0TMID56 RSCAN0.TMID56.UINT32
+#define RSCAN0TMID56L RSCAN0.TMID56.UINT16[L]
+#define RSCAN0TMID56LL RSCAN0.TMID56.UINT8[LL]
+#define RSCAN0TMID56LH RSCAN0.TMID56.UINT8[LH]
+#define RSCAN0TMID56H RSCAN0.TMID56.UINT16[H]
+#define RSCAN0TMID56HL RSCAN0.TMID56.UINT8[HL]
+#define RSCAN0TMID56HH RSCAN0.TMID56.UINT8[HH]
+#define RSCAN0TMPTR56 RSCAN0.TMPTR56.UINT32
+#define RSCAN0TMPTR56L RSCAN0.TMPTR56.UINT16[L]
+#define RSCAN0TMPTR56LL RSCAN0.TMPTR56.UINT8[LL]
+#define RSCAN0TMPTR56LH RSCAN0.TMPTR56.UINT8[LH]
+#define RSCAN0TMPTR56H RSCAN0.TMPTR56.UINT16[H]
+#define RSCAN0TMPTR56HL RSCAN0.TMPTR56.UINT8[HL]
+#define RSCAN0TMPTR56HH RSCAN0.TMPTR56.UINT8[HH]
+#define RSCAN0TMDF056 RSCAN0.TMDF056.UINT32
+#define RSCAN0TMDF056L RSCAN0.TMDF056.UINT16[L]
+#define RSCAN0TMDF056LL RSCAN0.TMDF056.UINT8[LL]
+#define RSCAN0TMDF056LH RSCAN0.TMDF056.UINT8[LH]
+#define RSCAN0TMDF056H RSCAN0.TMDF056.UINT16[H]
+#define RSCAN0TMDF056HL RSCAN0.TMDF056.UINT8[HL]
+#define RSCAN0TMDF056HH RSCAN0.TMDF056.UINT8[HH]
+#define RSCAN0TMDF156 RSCAN0.TMDF156.UINT32
+#define RSCAN0TMDF156L RSCAN0.TMDF156.UINT16[L]
+#define RSCAN0TMDF156LL RSCAN0.TMDF156.UINT8[LL]
+#define RSCAN0TMDF156LH RSCAN0.TMDF156.UINT8[LH]
+#define RSCAN0TMDF156H RSCAN0.TMDF156.UINT16[H]
+#define RSCAN0TMDF156HL RSCAN0.TMDF156.UINT8[HL]
+#define RSCAN0TMDF156HH RSCAN0.TMDF156.UINT8[HH]
+#define RSCAN0TMID57 RSCAN0.TMID57.UINT32
+#define RSCAN0TMID57L RSCAN0.TMID57.UINT16[L]
+#define RSCAN0TMID57LL RSCAN0.TMID57.UINT8[LL]
+#define RSCAN0TMID57LH RSCAN0.TMID57.UINT8[LH]
+#define RSCAN0TMID57H RSCAN0.TMID57.UINT16[H]
+#define RSCAN0TMID57HL RSCAN0.TMID57.UINT8[HL]
+#define RSCAN0TMID57HH RSCAN0.TMID57.UINT8[HH]
+#define RSCAN0TMPTR57 RSCAN0.TMPTR57.UINT32
+#define RSCAN0TMPTR57L RSCAN0.TMPTR57.UINT16[L]
+#define RSCAN0TMPTR57LL RSCAN0.TMPTR57.UINT8[LL]
+#define RSCAN0TMPTR57LH RSCAN0.TMPTR57.UINT8[LH]
+#define RSCAN0TMPTR57H RSCAN0.TMPTR57.UINT16[H]
+#define RSCAN0TMPTR57HL RSCAN0.TMPTR57.UINT8[HL]
+#define RSCAN0TMPTR57HH RSCAN0.TMPTR57.UINT8[HH]
+#define RSCAN0TMDF057 RSCAN0.TMDF057.UINT32
+#define RSCAN0TMDF057L RSCAN0.TMDF057.UINT16[L]
+#define RSCAN0TMDF057LL RSCAN0.TMDF057.UINT8[LL]
+#define RSCAN0TMDF057LH RSCAN0.TMDF057.UINT8[LH]
+#define RSCAN0TMDF057H RSCAN0.TMDF057.UINT16[H]
+#define RSCAN0TMDF057HL RSCAN0.TMDF057.UINT8[HL]
+#define RSCAN0TMDF057HH RSCAN0.TMDF057.UINT8[HH]
+#define RSCAN0TMDF157 RSCAN0.TMDF157.UINT32
+#define RSCAN0TMDF157L RSCAN0.TMDF157.UINT16[L]
+#define RSCAN0TMDF157LL RSCAN0.TMDF157.UINT8[LL]
+#define RSCAN0TMDF157LH RSCAN0.TMDF157.UINT8[LH]
+#define RSCAN0TMDF157H RSCAN0.TMDF157.UINT16[H]
+#define RSCAN0TMDF157HL RSCAN0.TMDF157.UINT8[HL]
+#define RSCAN0TMDF157HH RSCAN0.TMDF157.UINT8[HH]
+#define RSCAN0TMID58 RSCAN0.TMID58.UINT32
+#define RSCAN0TMID58L RSCAN0.TMID58.UINT16[L]
+#define RSCAN0TMID58LL RSCAN0.TMID58.UINT8[LL]
+#define RSCAN0TMID58LH RSCAN0.TMID58.UINT8[LH]
+#define RSCAN0TMID58H RSCAN0.TMID58.UINT16[H]
+#define RSCAN0TMID58HL RSCAN0.TMID58.UINT8[HL]
+#define RSCAN0TMID58HH RSCAN0.TMID58.UINT8[HH]
+#define RSCAN0TMPTR58 RSCAN0.TMPTR58.UINT32
+#define RSCAN0TMPTR58L RSCAN0.TMPTR58.UINT16[L]
+#define RSCAN0TMPTR58LL RSCAN0.TMPTR58.UINT8[LL]
+#define RSCAN0TMPTR58LH RSCAN0.TMPTR58.UINT8[LH]
+#define RSCAN0TMPTR58H RSCAN0.TMPTR58.UINT16[H]
+#define RSCAN0TMPTR58HL RSCAN0.TMPTR58.UINT8[HL]
+#define RSCAN0TMPTR58HH RSCAN0.TMPTR58.UINT8[HH]
+#define RSCAN0TMDF058 RSCAN0.TMDF058.UINT32
+#define RSCAN0TMDF058L RSCAN0.TMDF058.UINT16[L]
+#define RSCAN0TMDF058LL RSCAN0.TMDF058.UINT8[LL]
+#define RSCAN0TMDF058LH RSCAN0.TMDF058.UINT8[LH]
+#define RSCAN0TMDF058H RSCAN0.TMDF058.UINT16[H]
+#define RSCAN0TMDF058HL RSCAN0.TMDF058.UINT8[HL]
+#define RSCAN0TMDF058HH RSCAN0.TMDF058.UINT8[HH]
+#define RSCAN0TMDF158 RSCAN0.TMDF158.UINT32
+#define RSCAN0TMDF158L RSCAN0.TMDF158.UINT16[L]
+#define RSCAN0TMDF158LL RSCAN0.TMDF158.UINT8[LL]
+#define RSCAN0TMDF158LH RSCAN0.TMDF158.UINT8[LH]
+#define RSCAN0TMDF158H RSCAN0.TMDF158.UINT16[H]
+#define RSCAN0TMDF158HL RSCAN0.TMDF158.UINT8[HL]
+#define RSCAN0TMDF158HH RSCAN0.TMDF158.UINT8[HH]
+#define RSCAN0TMID59 RSCAN0.TMID59.UINT32
+#define RSCAN0TMID59L RSCAN0.TMID59.UINT16[L]
+#define RSCAN0TMID59LL RSCAN0.TMID59.UINT8[LL]
+#define RSCAN0TMID59LH RSCAN0.TMID59.UINT8[LH]
+#define RSCAN0TMID59H RSCAN0.TMID59.UINT16[H]
+#define RSCAN0TMID59HL RSCAN0.TMID59.UINT8[HL]
+#define RSCAN0TMID59HH RSCAN0.TMID59.UINT8[HH]
+#define RSCAN0TMPTR59 RSCAN0.TMPTR59.UINT32
+#define RSCAN0TMPTR59L RSCAN0.TMPTR59.UINT16[L]
+#define RSCAN0TMPTR59LL RSCAN0.TMPTR59.UINT8[LL]
+#define RSCAN0TMPTR59LH RSCAN0.TMPTR59.UINT8[LH]
+#define RSCAN0TMPTR59H RSCAN0.TMPTR59.UINT16[H]
+#define RSCAN0TMPTR59HL RSCAN0.TMPTR59.UINT8[HL]
+#define RSCAN0TMPTR59HH RSCAN0.TMPTR59.UINT8[HH]
+#define RSCAN0TMDF059 RSCAN0.TMDF059.UINT32
+#define RSCAN0TMDF059L RSCAN0.TMDF059.UINT16[L]
+#define RSCAN0TMDF059LL RSCAN0.TMDF059.UINT8[LL]
+#define RSCAN0TMDF059LH RSCAN0.TMDF059.UINT8[LH]
+#define RSCAN0TMDF059H RSCAN0.TMDF059.UINT16[H]
+#define RSCAN0TMDF059HL RSCAN0.TMDF059.UINT8[HL]
+#define RSCAN0TMDF059HH RSCAN0.TMDF059.UINT8[HH]
+#define RSCAN0TMDF159 RSCAN0.TMDF159.UINT32
+#define RSCAN0TMDF159L RSCAN0.TMDF159.UINT16[L]
+#define RSCAN0TMDF159LL RSCAN0.TMDF159.UINT8[LL]
+#define RSCAN0TMDF159LH RSCAN0.TMDF159.UINT8[LH]
+#define RSCAN0TMDF159H RSCAN0.TMDF159.UINT16[H]
+#define RSCAN0TMDF159HL RSCAN0.TMDF159.UINT8[HL]
+#define RSCAN0TMDF159HH RSCAN0.TMDF159.UINT8[HH]
+#define RSCAN0TMID60 RSCAN0.TMID60.UINT32
+#define RSCAN0TMID60L RSCAN0.TMID60.UINT16[L]
+#define RSCAN0TMID60LL RSCAN0.TMID60.UINT8[LL]
+#define RSCAN0TMID60LH RSCAN0.TMID60.UINT8[LH]
+#define RSCAN0TMID60H RSCAN0.TMID60.UINT16[H]
+#define RSCAN0TMID60HL RSCAN0.TMID60.UINT8[HL]
+#define RSCAN0TMID60HH RSCAN0.TMID60.UINT8[HH]
+#define RSCAN0TMPTR60 RSCAN0.TMPTR60.UINT32
+#define RSCAN0TMPTR60L RSCAN0.TMPTR60.UINT16[L]
+#define RSCAN0TMPTR60LL RSCAN0.TMPTR60.UINT8[LL]
+#define RSCAN0TMPTR60LH RSCAN0.TMPTR60.UINT8[LH]
+#define RSCAN0TMPTR60H RSCAN0.TMPTR60.UINT16[H]
+#define RSCAN0TMPTR60HL RSCAN0.TMPTR60.UINT8[HL]
+#define RSCAN0TMPTR60HH RSCAN0.TMPTR60.UINT8[HH]
+#define RSCAN0TMDF060 RSCAN0.TMDF060.UINT32
+#define RSCAN0TMDF060L RSCAN0.TMDF060.UINT16[L]
+#define RSCAN0TMDF060LL RSCAN0.TMDF060.UINT8[LL]
+#define RSCAN0TMDF060LH RSCAN0.TMDF060.UINT8[LH]
+#define RSCAN0TMDF060H RSCAN0.TMDF060.UINT16[H]
+#define RSCAN0TMDF060HL RSCAN0.TMDF060.UINT8[HL]
+#define RSCAN0TMDF060HH RSCAN0.TMDF060.UINT8[HH]
+#define RSCAN0TMDF160 RSCAN0.TMDF160.UINT32
+#define RSCAN0TMDF160L RSCAN0.TMDF160.UINT16[L]
+#define RSCAN0TMDF160LL RSCAN0.TMDF160.UINT8[LL]
+#define RSCAN0TMDF160LH RSCAN0.TMDF160.UINT8[LH]
+#define RSCAN0TMDF160H RSCAN0.TMDF160.UINT16[H]
+#define RSCAN0TMDF160HL RSCAN0.TMDF160.UINT8[HL]
+#define RSCAN0TMDF160HH RSCAN0.TMDF160.UINT8[HH]
+#define RSCAN0TMID61 RSCAN0.TMID61.UINT32
+#define RSCAN0TMID61L RSCAN0.TMID61.UINT16[L]
+#define RSCAN0TMID61LL RSCAN0.TMID61.UINT8[LL]
+#define RSCAN0TMID61LH RSCAN0.TMID61.UINT8[LH]
+#define RSCAN0TMID61H RSCAN0.TMID61.UINT16[H]
+#define RSCAN0TMID61HL RSCAN0.TMID61.UINT8[HL]
+#define RSCAN0TMID61HH RSCAN0.TMID61.UINT8[HH]
+#define RSCAN0TMPTR61 RSCAN0.TMPTR61.UINT32
+#define RSCAN0TMPTR61L RSCAN0.TMPTR61.UINT16[L]
+#define RSCAN0TMPTR61LL RSCAN0.TMPTR61.UINT8[LL]
+#define RSCAN0TMPTR61LH RSCAN0.TMPTR61.UINT8[LH]
+#define RSCAN0TMPTR61H RSCAN0.TMPTR61.UINT16[H]
+#define RSCAN0TMPTR61HL RSCAN0.TMPTR61.UINT8[HL]
+#define RSCAN0TMPTR61HH RSCAN0.TMPTR61.UINT8[HH]
+#define RSCAN0TMDF061 RSCAN0.TMDF061.UINT32
+#define RSCAN0TMDF061L RSCAN0.TMDF061.UINT16[L]
+#define RSCAN0TMDF061LL RSCAN0.TMDF061.UINT8[LL]
+#define RSCAN0TMDF061LH RSCAN0.TMDF061.UINT8[LH]
+#define RSCAN0TMDF061H RSCAN0.TMDF061.UINT16[H]
+#define RSCAN0TMDF061HL RSCAN0.TMDF061.UINT8[HL]
+#define RSCAN0TMDF061HH RSCAN0.TMDF061.UINT8[HH]
+#define RSCAN0TMDF161 RSCAN0.TMDF161.UINT32
+#define RSCAN0TMDF161L RSCAN0.TMDF161.UINT16[L]
+#define RSCAN0TMDF161LL RSCAN0.TMDF161.UINT8[LL]
+#define RSCAN0TMDF161LH RSCAN0.TMDF161.UINT8[LH]
+#define RSCAN0TMDF161H RSCAN0.TMDF161.UINT16[H]
+#define RSCAN0TMDF161HL RSCAN0.TMDF161.UINT8[HL]
+#define RSCAN0TMDF161HH RSCAN0.TMDF161.UINT8[HH]
+#define RSCAN0TMID62 RSCAN0.TMID62.UINT32
+#define RSCAN0TMID62L RSCAN0.TMID62.UINT16[L]
+#define RSCAN0TMID62LL RSCAN0.TMID62.UINT8[LL]
+#define RSCAN0TMID62LH RSCAN0.TMID62.UINT8[LH]
+#define RSCAN0TMID62H RSCAN0.TMID62.UINT16[H]
+#define RSCAN0TMID62HL RSCAN0.TMID62.UINT8[HL]
+#define RSCAN0TMID62HH RSCAN0.TMID62.UINT8[HH]
+#define RSCAN0TMPTR62 RSCAN0.TMPTR62.UINT32
+#define RSCAN0TMPTR62L RSCAN0.TMPTR62.UINT16[L]
+#define RSCAN0TMPTR62LL RSCAN0.TMPTR62.UINT8[LL]
+#define RSCAN0TMPTR62LH RSCAN0.TMPTR62.UINT8[LH]
+#define RSCAN0TMPTR62H RSCAN0.TMPTR62.UINT16[H]
+#define RSCAN0TMPTR62HL RSCAN0.TMPTR62.UINT8[HL]
+#define RSCAN0TMPTR62HH RSCAN0.TMPTR62.UINT8[HH]
+#define RSCAN0TMDF062 RSCAN0.TMDF062.UINT32
+#define RSCAN0TMDF062L RSCAN0.TMDF062.UINT16[L]
+#define RSCAN0TMDF062LL RSCAN0.TMDF062.UINT8[LL]
+#define RSCAN0TMDF062LH RSCAN0.TMDF062.UINT8[LH]
+#define RSCAN0TMDF062H RSCAN0.TMDF062.UINT16[H]
+#define RSCAN0TMDF062HL RSCAN0.TMDF062.UINT8[HL]
+#define RSCAN0TMDF062HH RSCAN0.TMDF062.UINT8[HH]
+#define RSCAN0TMDF162 RSCAN0.TMDF162.UINT32
+#define RSCAN0TMDF162L RSCAN0.TMDF162.UINT16[L]
+#define RSCAN0TMDF162LL RSCAN0.TMDF162.UINT8[LL]
+#define RSCAN0TMDF162LH RSCAN0.TMDF162.UINT8[LH]
+#define RSCAN0TMDF162H RSCAN0.TMDF162.UINT16[H]
+#define RSCAN0TMDF162HL RSCAN0.TMDF162.UINT8[HL]
+#define RSCAN0TMDF162HH RSCAN0.TMDF162.UINT8[HH]
+#define RSCAN0TMID63 RSCAN0.TMID63.UINT32
+#define RSCAN0TMID63L RSCAN0.TMID63.UINT16[L]
+#define RSCAN0TMID63LL RSCAN0.TMID63.UINT8[LL]
+#define RSCAN0TMID63LH RSCAN0.TMID63.UINT8[LH]
+#define RSCAN0TMID63H RSCAN0.TMID63.UINT16[H]
+#define RSCAN0TMID63HL RSCAN0.TMID63.UINT8[HL]
+#define RSCAN0TMID63HH RSCAN0.TMID63.UINT8[HH]
+#define RSCAN0TMPTR63 RSCAN0.TMPTR63.UINT32
+#define RSCAN0TMPTR63L RSCAN0.TMPTR63.UINT16[L]
+#define RSCAN0TMPTR63LL RSCAN0.TMPTR63.UINT8[LL]
+#define RSCAN0TMPTR63LH RSCAN0.TMPTR63.UINT8[LH]
+#define RSCAN0TMPTR63H RSCAN0.TMPTR63.UINT16[H]
+#define RSCAN0TMPTR63HL RSCAN0.TMPTR63.UINT8[HL]
+#define RSCAN0TMPTR63HH RSCAN0.TMPTR63.UINT8[HH]
+#define RSCAN0TMDF063 RSCAN0.TMDF063.UINT32
+#define RSCAN0TMDF063L RSCAN0.TMDF063.UINT16[L]
+#define RSCAN0TMDF063LL RSCAN0.TMDF063.UINT8[LL]
+#define RSCAN0TMDF063LH RSCAN0.TMDF063.UINT8[LH]
+#define RSCAN0TMDF063H RSCAN0.TMDF063.UINT16[H]
+#define RSCAN0TMDF063HL RSCAN0.TMDF063.UINT8[HL]
+#define RSCAN0TMDF063HH RSCAN0.TMDF063.UINT8[HH]
+#define RSCAN0TMDF163 RSCAN0.TMDF163.UINT32
+#define RSCAN0TMDF163L RSCAN0.TMDF163.UINT16[L]
+#define RSCAN0TMDF163LL RSCAN0.TMDF163.UINT8[LL]
+#define RSCAN0TMDF163LH RSCAN0.TMDF163.UINT8[LH]
+#define RSCAN0TMDF163H RSCAN0.TMDF163.UINT16[H]
+#define RSCAN0TMDF163HL RSCAN0.TMDF163.UINT8[HL]
+#define RSCAN0TMDF163HH RSCAN0.TMDF163.UINT8[HH]
+#define RSCAN0TMID64 RSCAN0.TMID64.UINT32
+#define RSCAN0TMID64L RSCAN0.TMID64.UINT16[L]
+#define RSCAN0TMID64LL RSCAN0.TMID64.UINT8[LL]
+#define RSCAN0TMID64LH RSCAN0.TMID64.UINT8[LH]
+#define RSCAN0TMID64H RSCAN0.TMID64.UINT16[H]
+#define RSCAN0TMID64HL RSCAN0.TMID64.UINT8[HL]
+#define RSCAN0TMID64HH RSCAN0.TMID64.UINT8[HH]
+#define RSCAN0TMPTR64 RSCAN0.TMPTR64.UINT32
+#define RSCAN0TMPTR64L RSCAN0.TMPTR64.UINT16[L]
+#define RSCAN0TMPTR64LL RSCAN0.TMPTR64.UINT8[LL]
+#define RSCAN0TMPTR64LH RSCAN0.TMPTR64.UINT8[LH]
+#define RSCAN0TMPTR64H RSCAN0.TMPTR64.UINT16[H]
+#define RSCAN0TMPTR64HL RSCAN0.TMPTR64.UINT8[HL]
+#define RSCAN0TMPTR64HH RSCAN0.TMPTR64.UINT8[HH]
+#define RSCAN0TMDF064 RSCAN0.TMDF064.UINT32
+#define RSCAN0TMDF064L RSCAN0.TMDF064.UINT16[L]
+#define RSCAN0TMDF064LL RSCAN0.TMDF064.UINT8[LL]
+#define RSCAN0TMDF064LH RSCAN0.TMDF064.UINT8[LH]
+#define RSCAN0TMDF064H RSCAN0.TMDF064.UINT16[H]
+#define RSCAN0TMDF064HL RSCAN0.TMDF064.UINT8[HL]
+#define RSCAN0TMDF064HH RSCAN0.TMDF064.UINT8[HH]
+#define RSCAN0TMDF164 RSCAN0.TMDF164.UINT32
+#define RSCAN0TMDF164L RSCAN0.TMDF164.UINT16[L]
+#define RSCAN0TMDF164LL RSCAN0.TMDF164.UINT8[LL]
+#define RSCAN0TMDF164LH RSCAN0.TMDF164.UINT8[LH]
+#define RSCAN0TMDF164H RSCAN0.TMDF164.UINT16[H]
+#define RSCAN0TMDF164HL RSCAN0.TMDF164.UINT8[HL]
+#define RSCAN0TMDF164HH RSCAN0.TMDF164.UINT8[HH]
+#define RSCAN0TMID65 RSCAN0.TMID65.UINT32
+#define RSCAN0TMID65L RSCAN0.TMID65.UINT16[L]
+#define RSCAN0TMID65LL RSCAN0.TMID65.UINT8[LL]
+#define RSCAN0TMID65LH RSCAN0.TMID65.UINT8[LH]
+#define RSCAN0TMID65H RSCAN0.TMID65.UINT16[H]
+#define RSCAN0TMID65HL RSCAN0.TMID65.UINT8[HL]
+#define RSCAN0TMID65HH RSCAN0.TMID65.UINT8[HH]
+#define RSCAN0TMPTR65 RSCAN0.TMPTR65.UINT32
+#define RSCAN0TMPTR65L RSCAN0.TMPTR65.UINT16[L]
+#define RSCAN0TMPTR65LL RSCAN0.TMPTR65.UINT8[LL]
+#define RSCAN0TMPTR65LH RSCAN0.TMPTR65.UINT8[LH]
+#define RSCAN0TMPTR65H RSCAN0.TMPTR65.UINT16[H]
+#define RSCAN0TMPTR65HL RSCAN0.TMPTR65.UINT8[HL]
+#define RSCAN0TMPTR65HH RSCAN0.TMPTR65.UINT8[HH]
+#define RSCAN0TMDF065 RSCAN0.TMDF065.UINT32
+#define RSCAN0TMDF065L RSCAN0.TMDF065.UINT16[L]
+#define RSCAN0TMDF065LL RSCAN0.TMDF065.UINT8[LL]
+#define RSCAN0TMDF065LH RSCAN0.TMDF065.UINT8[LH]
+#define RSCAN0TMDF065H RSCAN0.TMDF065.UINT16[H]
+#define RSCAN0TMDF065HL RSCAN0.TMDF065.UINT8[HL]
+#define RSCAN0TMDF065HH RSCAN0.TMDF065.UINT8[HH]
+#define RSCAN0TMDF165 RSCAN0.TMDF165.UINT32
+#define RSCAN0TMDF165L RSCAN0.TMDF165.UINT16[L]
+#define RSCAN0TMDF165LL RSCAN0.TMDF165.UINT8[LL]
+#define RSCAN0TMDF165LH RSCAN0.TMDF165.UINT8[LH]
+#define RSCAN0TMDF165H RSCAN0.TMDF165.UINT16[H]
+#define RSCAN0TMDF165HL RSCAN0.TMDF165.UINT8[HL]
+#define RSCAN0TMDF165HH RSCAN0.TMDF165.UINT8[HH]
+#define RSCAN0TMID66 RSCAN0.TMID66.UINT32
+#define RSCAN0TMID66L RSCAN0.TMID66.UINT16[L]
+#define RSCAN0TMID66LL RSCAN0.TMID66.UINT8[LL]
+#define RSCAN0TMID66LH RSCAN0.TMID66.UINT8[LH]
+#define RSCAN0TMID66H RSCAN0.TMID66.UINT16[H]
+#define RSCAN0TMID66HL RSCAN0.TMID66.UINT8[HL]
+#define RSCAN0TMID66HH RSCAN0.TMID66.UINT8[HH]
+#define RSCAN0TMPTR66 RSCAN0.TMPTR66.UINT32
+#define RSCAN0TMPTR66L RSCAN0.TMPTR66.UINT16[L]
+#define RSCAN0TMPTR66LL RSCAN0.TMPTR66.UINT8[LL]
+#define RSCAN0TMPTR66LH RSCAN0.TMPTR66.UINT8[LH]
+#define RSCAN0TMPTR66H RSCAN0.TMPTR66.UINT16[H]
+#define RSCAN0TMPTR66HL RSCAN0.TMPTR66.UINT8[HL]
+#define RSCAN0TMPTR66HH RSCAN0.TMPTR66.UINT8[HH]
+#define RSCAN0TMDF066 RSCAN0.TMDF066.UINT32
+#define RSCAN0TMDF066L RSCAN0.TMDF066.UINT16[L]
+#define RSCAN0TMDF066LL RSCAN0.TMDF066.UINT8[LL]
+#define RSCAN0TMDF066LH RSCAN0.TMDF066.UINT8[LH]
+#define RSCAN0TMDF066H RSCAN0.TMDF066.UINT16[H]
+#define RSCAN0TMDF066HL RSCAN0.TMDF066.UINT8[HL]
+#define RSCAN0TMDF066HH RSCAN0.TMDF066.UINT8[HH]
+#define RSCAN0TMDF166 RSCAN0.TMDF166.UINT32
+#define RSCAN0TMDF166L RSCAN0.TMDF166.UINT16[L]
+#define RSCAN0TMDF166LL RSCAN0.TMDF166.UINT8[LL]
+#define RSCAN0TMDF166LH RSCAN0.TMDF166.UINT8[LH]
+#define RSCAN0TMDF166H RSCAN0.TMDF166.UINT16[H]
+#define RSCAN0TMDF166HL RSCAN0.TMDF166.UINT8[HL]
+#define RSCAN0TMDF166HH RSCAN0.TMDF166.UINT8[HH]
+#define RSCAN0TMID67 RSCAN0.TMID67.UINT32
+#define RSCAN0TMID67L RSCAN0.TMID67.UINT16[L]
+#define RSCAN0TMID67LL RSCAN0.TMID67.UINT8[LL]
+#define RSCAN0TMID67LH RSCAN0.TMID67.UINT8[LH]
+#define RSCAN0TMID67H RSCAN0.TMID67.UINT16[H]
+#define RSCAN0TMID67HL RSCAN0.TMID67.UINT8[HL]
+#define RSCAN0TMID67HH RSCAN0.TMID67.UINT8[HH]
+#define RSCAN0TMPTR67 RSCAN0.TMPTR67.UINT32
+#define RSCAN0TMPTR67L RSCAN0.TMPTR67.UINT16[L]
+#define RSCAN0TMPTR67LL RSCAN0.TMPTR67.UINT8[LL]
+#define RSCAN0TMPTR67LH RSCAN0.TMPTR67.UINT8[LH]
+#define RSCAN0TMPTR67H RSCAN0.TMPTR67.UINT16[H]
+#define RSCAN0TMPTR67HL RSCAN0.TMPTR67.UINT8[HL]
+#define RSCAN0TMPTR67HH RSCAN0.TMPTR67.UINT8[HH]
+#define RSCAN0TMDF067 RSCAN0.TMDF067.UINT32
+#define RSCAN0TMDF067L RSCAN0.TMDF067.UINT16[L]
+#define RSCAN0TMDF067LL RSCAN0.TMDF067.UINT8[LL]
+#define RSCAN0TMDF067LH RSCAN0.TMDF067.UINT8[LH]
+#define RSCAN0TMDF067H RSCAN0.TMDF067.UINT16[H]
+#define RSCAN0TMDF067HL RSCAN0.TMDF067.UINT8[HL]
+#define RSCAN0TMDF067HH RSCAN0.TMDF067.UINT8[HH]
+#define RSCAN0TMDF167 RSCAN0.TMDF167.UINT32
+#define RSCAN0TMDF167L RSCAN0.TMDF167.UINT16[L]
+#define RSCAN0TMDF167LL RSCAN0.TMDF167.UINT8[LL]
+#define RSCAN0TMDF167LH RSCAN0.TMDF167.UINT8[LH]
+#define RSCAN0TMDF167H RSCAN0.TMDF167.UINT16[H]
+#define RSCAN0TMDF167HL RSCAN0.TMDF167.UINT8[HL]
+#define RSCAN0TMDF167HH RSCAN0.TMDF167.UINT8[HH]
+#define RSCAN0TMID68 RSCAN0.TMID68.UINT32
+#define RSCAN0TMID68L RSCAN0.TMID68.UINT16[L]
+#define RSCAN0TMID68LL RSCAN0.TMID68.UINT8[LL]
+#define RSCAN0TMID68LH RSCAN0.TMID68.UINT8[LH]
+#define RSCAN0TMID68H RSCAN0.TMID68.UINT16[H]
+#define RSCAN0TMID68HL RSCAN0.TMID68.UINT8[HL]
+#define RSCAN0TMID68HH RSCAN0.TMID68.UINT8[HH]
+#define RSCAN0TMPTR68 RSCAN0.TMPTR68.UINT32
+#define RSCAN0TMPTR68L RSCAN0.TMPTR68.UINT16[L]
+#define RSCAN0TMPTR68LL RSCAN0.TMPTR68.UINT8[LL]
+#define RSCAN0TMPTR68LH RSCAN0.TMPTR68.UINT8[LH]
+#define RSCAN0TMPTR68H RSCAN0.TMPTR68.UINT16[H]
+#define RSCAN0TMPTR68HL RSCAN0.TMPTR68.UINT8[HL]
+#define RSCAN0TMPTR68HH RSCAN0.TMPTR68.UINT8[HH]
+#define RSCAN0TMDF068 RSCAN0.TMDF068.UINT32
+#define RSCAN0TMDF068L RSCAN0.TMDF068.UINT16[L]
+#define RSCAN0TMDF068LL RSCAN0.TMDF068.UINT8[LL]
+#define RSCAN0TMDF068LH RSCAN0.TMDF068.UINT8[LH]
+#define RSCAN0TMDF068H RSCAN0.TMDF068.UINT16[H]
+#define RSCAN0TMDF068HL RSCAN0.TMDF068.UINT8[HL]
+#define RSCAN0TMDF068HH RSCAN0.TMDF068.UINT8[HH]
+#define RSCAN0TMDF168 RSCAN0.TMDF168.UINT32
+#define RSCAN0TMDF168L RSCAN0.TMDF168.UINT16[L]
+#define RSCAN0TMDF168LL RSCAN0.TMDF168.UINT8[LL]
+#define RSCAN0TMDF168LH RSCAN0.TMDF168.UINT8[LH]
+#define RSCAN0TMDF168H RSCAN0.TMDF168.UINT16[H]
+#define RSCAN0TMDF168HL RSCAN0.TMDF168.UINT8[HL]
+#define RSCAN0TMDF168HH RSCAN0.TMDF168.UINT8[HH]
+#define RSCAN0TMID69 RSCAN0.TMID69.UINT32
+#define RSCAN0TMID69L RSCAN0.TMID69.UINT16[L]
+#define RSCAN0TMID69LL RSCAN0.TMID69.UINT8[LL]
+#define RSCAN0TMID69LH RSCAN0.TMID69.UINT8[LH]
+#define RSCAN0TMID69H RSCAN0.TMID69.UINT16[H]
+#define RSCAN0TMID69HL RSCAN0.TMID69.UINT8[HL]
+#define RSCAN0TMID69HH RSCAN0.TMID69.UINT8[HH]
+#define RSCAN0TMPTR69 RSCAN0.TMPTR69.UINT32
+#define RSCAN0TMPTR69L RSCAN0.TMPTR69.UINT16[L]
+#define RSCAN0TMPTR69LL RSCAN0.TMPTR69.UINT8[LL]
+#define RSCAN0TMPTR69LH RSCAN0.TMPTR69.UINT8[LH]
+#define RSCAN0TMPTR69H RSCAN0.TMPTR69.UINT16[H]
+#define RSCAN0TMPTR69HL RSCAN0.TMPTR69.UINT8[HL]
+#define RSCAN0TMPTR69HH RSCAN0.TMPTR69.UINT8[HH]
+#define RSCAN0TMDF069 RSCAN0.TMDF069.UINT32
+#define RSCAN0TMDF069L RSCAN0.TMDF069.UINT16[L]
+#define RSCAN0TMDF069LL RSCAN0.TMDF069.UINT8[LL]
+#define RSCAN0TMDF069LH RSCAN0.TMDF069.UINT8[LH]
+#define RSCAN0TMDF069H RSCAN0.TMDF069.UINT16[H]
+#define RSCAN0TMDF069HL RSCAN0.TMDF069.UINT8[HL]
+#define RSCAN0TMDF069HH RSCAN0.TMDF069.UINT8[HH]
+#define RSCAN0TMDF169 RSCAN0.TMDF169.UINT32
+#define RSCAN0TMDF169L RSCAN0.TMDF169.UINT16[L]
+#define RSCAN0TMDF169LL RSCAN0.TMDF169.UINT8[LL]
+#define RSCAN0TMDF169LH RSCAN0.TMDF169.UINT8[LH]
+#define RSCAN0TMDF169H RSCAN0.TMDF169.UINT16[H]
+#define RSCAN0TMDF169HL RSCAN0.TMDF169.UINT8[HL]
+#define RSCAN0TMDF169HH RSCAN0.TMDF169.UINT8[HH]
+#define RSCAN0TMID70 RSCAN0.TMID70.UINT32
+#define RSCAN0TMID70L RSCAN0.TMID70.UINT16[L]
+#define RSCAN0TMID70LL RSCAN0.TMID70.UINT8[LL]
+#define RSCAN0TMID70LH RSCAN0.TMID70.UINT8[LH]
+#define RSCAN0TMID70H RSCAN0.TMID70.UINT16[H]
+#define RSCAN0TMID70HL RSCAN0.TMID70.UINT8[HL]
+#define RSCAN0TMID70HH RSCAN0.TMID70.UINT8[HH]
+#define RSCAN0TMPTR70 RSCAN0.TMPTR70.UINT32
+#define RSCAN0TMPTR70L RSCAN0.TMPTR70.UINT16[L]
+#define RSCAN0TMPTR70LL RSCAN0.TMPTR70.UINT8[LL]
+#define RSCAN0TMPTR70LH RSCAN0.TMPTR70.UINT8[LH]
+#define RSCAN0TMPTR70H RSCAN0.TMPTR70.UINT16[H]
+#define RSCAN0TMPTR70HL RSCAN0.TMPTR70.UINT8[HL]
+#define RSCAN0TMPTR70HH RSCAN0.TMPTR70.UINT8[HH]
+#define RSCAN0TMDF070 RSCAN0.TMDF070.UINT32
+#define RSCAN0TMDF070L RSCAN0.TMDF070.UINT16[L]
+#define RSCAN0TMDF070LL RSCAN0.TMDF070.UINT8[LL]
+#define RSCAN0TMDF070LH RSCAN0.TMDF070.UINT8[LH]
+#define RSCAN0TMDF070H RSCAN0.TMDF070.UINT16[H]
+#define RSCAN0TMDF070HL RSCAN0.TMDF070.UINT8[HL]
+#define RSCAN0TMDF070HH RSCAN0.TMDF070.UINT8[HH]
+#define RSCAN0TMDF170 RSCAN0.TMDF170.UINT32
+#define RSCAN0TMDF170L RSCAN0.TMDF170.UINT16[L]
+#define RSCAN0TMDF170LL RSCAN0.TMDF170.UINT8[LL]
+#define RSCAN0TMDF170LH RSCAN0.TMDF170.UINT8[LH]
+#define RSCAN0TMDF170H RSCAN0.TMDF170.UINT16[H]
+#define RSCAN0TMDF170HL RSCAN0.TMDF170.UINT8[HL]
+#define RSCAN0TMDF170HH RSCAN0.TMDF170.UINT8[HH]
+#define RSCAN0TMID71 RSCAN0.TMID71.UINT32
+#define RSCAN0TMID71L RSCAN0.TMID71.UINT16[L]
+#define RSCAN0TMID71LL RSCAN0.TMID71.UINT8[LL]
+#define RSCAN0TMID71LH RSCAN0.TMID71.UINT8[LH]
+#define RSCAN0TMID71H RSCAN0.TMID71.UINT16[H]
+#define RSCAN0TMID71HL RSCAN0.TMID71.UINT8[HL]
+#define RSCAN0TMID71HH RSCAN0.TMID71.UINT8[HH]
+#define RSCAN0TMPTR71 RSCAN0.TMPTR71.UINT32
+#define RSCAN0TMPTR71L RSCAN0.TMPTR71.UINT16[L]
+#define RSCAN0TMPTR71LL RSCAN0.TMPTR71.UINT8[LL]
+#define RSCAN0TMPTR71LH RSCAN0.TMPTR71.UINT8[LH]
+#define RSCAN0TMPTR71H RSCAN0.TMPTR71.UINT16[H]
+#define RSCAN0TMPTR71HL RSCAN0.TMPTR71.UINT8[HL]
+#define RSCAN0TMPTR71HH RSCAN0.TMPTR71.UINT8[HH]
+#define RSCAN0TMDF071 RSCAN0.TMDF071.UINT32
+#define RSCAN0TMDF071L RSCAN0.TMDF071.UINT16[L]
+#define RSCAN0TMDF071LL RSCAN0.TMDF071.UINT8[LL]
+#define RSCAN0TMDF071LH RSCAN0.TMDF071.UINT8[LH]
+#define RSCAN0TMDF071H RSCAN0.TMDF071.UINT16[H]
+#define RSCAN0TMDF071HL RSCAN0.TMDF071.UINT8[HL]
+#define RSCAN0TMDF071HH RSCAN0.TMDF071.UINT8[HH]
+#define RSCAN0TMDF171 RSCAN0.TMDF171.UINT32
+#define RSCAN0TMDF171L RSCAN0.TMDF171.UINT16[L]
+#define RSCAN0TMDF171LL RSCAN0.TMDF171.UINT8[LL]
+#define RSCAN0TMDF171LH RSCAN0.TMDF171.UINT8[LH]
+#define RSCAN0TMDF171H RSCAN0.TMDF171.UINT16[H]
+#define RSCAN0TMDF171HL RSCAN0.TMDF171.UINT8[HL]
+#define RSCAN0TMDF171HH RSCAN0.TMDF171.UINT8[HH]
+#define RSCAN0TMID72 RSCAN0.TMID72.UINT32
+#define RSCAN0TMID72L RSCAN0.TMID72.UINT16[L]
+#define RSCAN0TMID72LL RSCAN0.TMID72.UINT8[LL]
+#define RSCAN0TMID72LH RSCAN0.TMID72.UINT8[LH]
+#define RSCAN0TMID72H RSCAN0.TMID72.UINT16[H]
+#define RSCAN0TMID72HL RSCAN0.TMID72.UINT8[HL]
+#define RSCAN0TMID72HH RSCAN0.TMID72.UINT8[HH]
+#define RSCAN0TMPTR72 RSCAN0.TMPTR72.UINT32
+#define RSCAN0TMPTR72L RSCAN0.TMPTR72.UINT16[L]
+#define RSCAN0TMPTR72LL RSCAN0.TMPTR72.UINT8[LL]
+#define RSCAN0TMPTR72LH RSCAN0.TMPTR72.UINT8[LH]
+#define RSCAN0TMPTR72H RSCAN0.TMPTR72.UINT16[H]
+#define RSCAN0TMPTR72HL RSCAN0.TMPTR72.UINT8[HL]
+#define RSCAN0TMPTR72HH RSCAN0.TMPTR72.UINT8[HH]
+#define RSCAN0TMDF072 RSCAN0.TMDF072.UINT32
+#define RSCAN0TMDF072L RSCAN0.TMDF072.UINT16[L]
+#define RSCAN0TMDF072LL RSCAN0.TMDF072.UINT8[LL]
+#define RSCAN0TMDF072LH RSCAN0.TMDF072.UINT8[LH]
+#define RSCAN0TMDF072H RSCAN0.TMDF072.UINT16[H]
+#define RSCAN0TMDF072HL RSCAN0.TMDF072.UINT8[HL]
+#define RSCAN0TMDF072HH RSCAN0.TMDF072.UINT8[HH]
+#define RSCAN0TMDF172 RSCAN0.TMDF172.UINT32
+#define RSCAN0TMDF172L RSCAN0.TMDF172.UINT16[L]
+#define RSCAN0TMDF172LL RSCAN0.TMDF172.UINT8[LL]
+#define RSCAN0TMDF172LH RSCAN0.TMDF172.UINT8[LH]
+#define RSCAN0TMDF172H RSCAN0.TMDF172.UINT16[H]
+#define RSCAN0TMDF172HL RSCAN0.TMDF172.UINT8[HL]
+#define RSCAN0TMDF172HH RSCAN0.TMDF172.UINT8[HH]
+#define RSCAN0TMID73 RSCAN0.TMID73.UINT32
+#define RSCAN0TMID73L RSCAN0.TMID73.UINT16[L]
+#define RSCAN0TMID73LL RSCAN0.TMID73.UINT8[LL]
+#define RSCAN0TMID73LH RSCAN0.TMID73.UINT8[LH]
+#define RSCAN0TMID73H RSCAN0.TMID73.UINT16[H]
+#define RSCAN0TMID73HL RSCAN0.TMID73.UINT8[HL]
+#define RSCAN0TMID73HH RSCAN0.TMID73.UINT8[HH]
+#define RSCAN0TMPTR73 RSCAN0.TMPTR73.UINT32
+#define RSCAN0TMPTR73L RSCAN0.TMPTR73.UINT16[L]
+#define RSCAN0TMPTR73LL RSCAN0.TMPTR73.UINT8[LL]
+#define RSCAN0TMPTR73LH RSCAN0.TMPTR73.UINT8[LH]
+#define RSCAN0TMPTR73H RSCAN0.TMPTR73.UINT16[H]
+#define RSCAN0TMPTR73HL RSCAN0.TMPTR73.UINT8[HL]
+#define RSCAN0TMPTR73HH RSCAN0.TMPTR73.UINT8[HH]
+#define RSCAN0TMDF073 RSCAN0.TMDF073.UINT32
+#define RSCAN0TMDF073L RSCAN0.TMDF073.UINT16[L]
+#define RSCAN0TMDF073LL RSCAN0.TMDF073.UINT8[LL]
+#define RSCAN0TMDF073LH RSCAN0.TMDF073.UINT8[LH]
+#define RSCAN0TMDF073H RSCAN0.TMDF073.UINT16[H]
+#define RSCAN0TMDF073HL RSCAN0.TMDF073.UINT8[HL]
+#define RSCAN0TMDF073HH RSCAN0.TMDF073.UINT8[HH]
+#define RSCAN0TMDF173 RSCAN0.TMDF173.UINT32
+#define RSCAN0TMDF173L RSCAN0.TMDF173.UINT16[L]
+#define RSCAN0TMDF173LL RSCAN0.TMDF173.UINT8[LL]
+#define RSCAN0TMDF173LH RSCAN0.TMDF173.UINT8[LH]
+#define RSCAN0TMDF173H RSCAN0.TMDF173.UINT16[H]
+#define RSCAN0TMDF173HL RSCAN0.TMDF173.UINT8[HL]
+#define RSCAN0TMDF173HH RSCAN0.TMDF173.UINT8[HH]
+#define RSCAN0TMID74 RSCAN0.TMID74.UINT32
+#define RSCAN0TMID74L RSCAN0.TMID74.UINT16[L]
+#define RSCAN0TMID74LL RSCAN0.TMID74.UINT8[LL]
+#define RSCAN0TMID74LH RSCAN0.TMID74.UINT8[LH]
+#define RSCAN0TMID74H RSCAN0.TMID74.UINT16[H]
+#define RSCAN0TMID74HL RSCAN0.TMID74.UINT8[HL]
+#define RSCAN0TMID74HH RSCAN0.TMID74.UINT8[HH]
+#define RSCAN0TMPTR74 RSCAN0.TMPTR74.UINT32
+#define RSCAN0TMPTR74L RSCAN0.TMPTR74.UINT16[L]
+#define RSCAN0TMPTR74LL RSCAN0.TMPTR74.UINT8[LL]
+#define RSCAN0TMPTR74LH RSCAN0.TMPTR74.UINT8[LH]
+#define RSCAN0TMPTR74H RSCAN0.TMPTR74.UINT16[H]
+#define RSCAN0TMPTR74HL RSCAN0.TMPTR74.UINT8[HL]
+#define RSCAN0TMPTR74HH RSCAN0.TMPTR74.UINT8[HH]
+#define RSCAN0TMDF074 RSCAN0.TMDF074.UINT32
+#define RSCAN0TMDF074L RSCAN0.TMDF074.UINT16[L]
+#define RSCAN0TMDF074LL RSCAN0.TMDF074.UINT8[LL]
+#define RSCAN0TMDF074LH RSCAN0.TMDF074.UINT8[LH]
+#define RSCAN0TMDF074H RSCAN0.TMDF074.UINT16[H]
+#define RSCAN0TMDF074HL RSCAN0.TMDF074.UINT8[HL]
+#define RSCAN0TMDF074HH RSCAN0.TMDF074.UINT8[HH]
+#define RSCAN0TMDF174 RSCAN0.TMDF174.UINT32
+#define RSCAN0TMDF174L RSCAN0.TMDF174.UINT16[L]
+#define RSCAN0TMDF174LL RSCAN0.TMDF174.UINT8[LL]
+#define RSCAN0TMDF174LH RSCAN0.TMDF174.UINT8[LH]
+#define RSCAN0TMDF174H RSCAN0.TMDF174.UINT16[H]
+#define RSCAN0TMDF174HL RSCAN0.TMDF174.UINT8[HL]
+#define RSCAN0TMDF174HH RSCAN0.TMDF174.UINT8[HH]
+#define RSCAN0TMID75 RSCAN0.TMID75.UINT32
+#define RSCAN0TMID75L RSCAN0.TMID75.UINT16[L]
+#define RSCAN0TMID75LL RSCAN0.TMID75.UINT8[LL]
+#define RSCAN0TMID75LH RSCAN0.TMID75.UINT8[LH]
+#define RSCAN0TMID75H RSCAN0.TMID75.UINT16[H]
+#define RSCAN0TMID75HL RSCAN0.TMID75.UINT8[HL]
+#define RSCAN0TMID75HH RSCAN0.TMID75.UINT8[HH]
+#define RSCAN0TMPTR75 RSCAN0.TMPTR75.UINT32
+#define RSCAN0TMPTR75L RSCAN0.TMPTR75.UINT16[L]
+#define RSCAN0TMPTR75LL RSCAN0.TMPTR75.UINT8[LL]
+#define RSCAN0TMPTR75LH RSCAN0.TMPTR75.UINT8[LH]
+#define RSCAN0TMPTR75H RSCAN0.TMPTR75.UINT16[H]
+#define RSCAN0TMPTR75HL RSCAN0.TMPTR75.UINT8[HL]
+#define RSCAN0TMPTR75HH RSCAN0.TMPTR75.UINT8[HH]
+#define RSCAN0TMDF075 RSCAN0.TMDF075.UINT32
+#define RSCAN0TMDF075L RSCAN0.TMDF075.UINT16[L]
+#define RSCAN0TMDF075LL RSCAN0.TMDF075.UINT8[LL]
+#define RSCAN0TMDF075LH RSCAN0.TMDF075.UINT8[LH]
+#define RSCAN0TMDF075H RSCAN0.TMDF075.UINT16[H]
+#define RSCAN0TMDF075HL RSCAN0.TMDF075.UINT8[HL]
+#define RSCAN0TMDF075HH RSCAN0.TMDF075.UINT8[HH]
+#define RSCAN0TMDF175 RSCAN0.TMDF175.UINT32
+#define RSCAN0TMDF175L RSCAN0.TMDF175.UINT16[L]
+#define RSCAN0TMDF175LL RSCAN0.TMDF175.UINT8[LL]
+#define RSCAN0TMDF175LH RSCAN0.TMDF175.UINT8[LH]
+#define RSCAN0TMDF175H RSCAN0.TMDF175.UINT16[H]
+#define RSCAN0TMDF175HL RSCAN0.TMDF175.UINT8[HL]
+#define RSCAN0TMDF175HH RSCAN0.TMDF175.UINT8[HH]
+#define RSCAN0TMID76 RSCAN0.TMID76.UINT32
+#define RSCAN0TMID76L RSCAN0.TMID76.UINT16[L]
+#define RSCAN0TMID76LL RSCAN0.TMID76.UINT8[LL]
+#define RSCAN0TMID76LH RSCAN0.TMID76.UINT8[LH]
+#define RSCAN0TMID76H RSCAN0.TMID76.UINT16[H]
+#define RSCAN0TMID76HL RSCAN0.TMID76.UINT8[HL]
+#define RSCAN0TMID76HH RSCAN0.TMID76.UINT8[HH]
+#define RSCAN0TMPTR76 RSCAN0.TMPTR76.UINT32
+#define RSCAN0TMPTR76L RSCAN0.TMPTR76.UINT16[L]
+#define RSCAN0TMPTR76LL RSCAN0.TMPTR76.UINT8[LL]
+#define RSCAN0TMPTR76LH RSCAN0.TMPTR76.UINT8[LH]
+#define RSCAN0TMPTR76H RSCAN0.TMPTR76.UINT16[H]
+#define RSCAN0TMPTR76HL RSCAN0.TMPTR76.UINT8[HL]
+#define RSCAN0TMPTR76HH RSCAN0.TMPTR76.UINT8[HH]
+#define RSCAN0TMDF076 RSCAN0.TMDF076.UINT32
+#define RSCAN0TMDF076L RSCAN0.TMDF076.UINT16[L]
+#define RSCAN0TMDF076LL RSCAN0.TMDF076.UINT8[LL]
+#define RSCAN0TMDF076LH RSCAN0.TMDF076.UINT8[LH]
+#define RSCAN0TMDF076H RSCAN0.TMDF076.UINT16[H]
+#define RSCAN0TMDF076HL RSCAN0.TMDF076.UINT8[HL]
+#define RSCAN0TMDF076HH RSCAN0.TMDF076.UINT8[HH]
+#define RSCAN0TMDF176 RSCAN0.TMDF176.UINT32
+#define RSCAN0TMDF176L RSCAN0.TMDF176.UINT16[L]
+#define RSCAN0TMDF176LL RSCAN0.TMDF176.UINT8[LL]
+#define RSCAN0TMDF176LH RSCAN0.TMDF176.UINT8[LH]
+#define RSCAN0TMDF176H RSCAN0.TMDF176.UINT16[H]
+#define RSCAN0TMDF176HL RSCAN0.TMDF176.UINT8[HL]
+#define RSCAN0TMDF176HH RSCAN0.TMDF176.UINT8[HH]
+#define RSCAN0TMID77 RSCAN0.TMID77.UINT32
+#define RSCAN0TMID77L RSCAN0.TMID77.UINT16[L]
+#define RSCAN0TMID77LL RSCAN0.TMID77.UINT8[LL]
+#define RSCAN0TMID77LH RSCAN0.TMID77.UINT8[LH]
+#define RSCAN0TMID77H RSCAN0.TMID77.UINT16[H]
+#define RSCAN0TMID77HL RSCAN0.TMID77.UINT8[HL]
+#define RSCAN0TMID77HH RSCAN0.TMID77.UINT8[HH]
+#define RSCAN0TMPTR77 RSCAN0.TMPTR77.UINT32
+#define RSCAN0TMPTR77L RSCAN0.TMPTR77.UINT16[L]
+#define RSCAN0TMPTR77LL RSCAN0.TMPTR77.UINT8[LL]
+#define RSCAN0TMPTR77LH RSCAN0.TMPTR77.UINT8[LH]
+#define RSCAN0TMPTR77H RSCAN0.TMPTR77.UINT16[H]
+#define RSCAN0TMPTR77HL RSCAN0.TMPTR77.UINT8[HL]
+#define RSCAN0TMPTR77HH RSCAN0.TMPTR77.UINT8[HH]
+#define RSCAN0TMDF077 RSCAN0.TMDF077.UINT32
+#define RSCAN0TMDF077L RSCAN0.TMDF077.UINT16[L]
+#define RSCAN0TMDF077LL RSCAN0.TMDF077.UINT8[LL]
+#define RSCAN0TMDF077LH RSCAN0.TMDF077.UINT8[LH]
+#define RSCAN0TMDF077H RSCAN0.TMDF077.UINT16[H]
+#define RSCAN0TMDF077HL RSCAN0.TMDF077.UINT8[HL]
+#define RSCAN0TMDF077HH RSCAN0.TMDF077.UINT8[HH]
+#define RSCAN0TMDF177 RSCAN0.TMDF177.UINT32
+#define RSCAN0TMDF177L RSCAN0.TMDF177.UINT16[L]
+#define RSCAN0TMDF177LL RSCAN0.TMDF177.UINT8[LL]
+#define RSCAN0TMDF177LH RSCAN0.TMDF177.UINT8[LH]
+#define RSCAN0TMDF177H RSCAN0.TMDF177.UINT16[H]
+#define RSCAN0TMDF177HL RSCAN0.TMDF177.UINT8[HL]
+#define RSCAN0TMDF177HH RSCAN0.TMDF177.UINT8[HH]
+#define RSCAN0TMID78 RSCAN0.TMID78.UINT32
+#define RSCAN0TMID78L RSCAN0.TMID78.UINT16[L]
+#define RSCAN0TMID78LL RSCAN0.TMID78.UINT8[LL]
+#define RSCAN0TMID78LH RSCAN0.TMID78.UINT8[LH]
+#define RSCAN0TMID78H RSCAN0.TMID78.UINT16[H]
+#define RSCAN0TMID78HL RSCAN0.TMID78.UINT8[HL]
+#define RSCAN0TMID78HH RSCAN0.TMID78.UINT8[HH]
+#define RSCAN0TMPTR78 RSCAN0.TMPTR78.UINT32
+#define RSCAN0TMPTR78L RSCAN0.TMPTR78.UINT16[L]
+#define RSCAN0TMPTR78LL RSCAN0.TMPTR78.UINT8[LL]
+#define RSCAN0TMPTR78LH RSCAN0.TMPTR78.UINT8[LH]
+#define RSCAN0TMPTR78H RSCAN0.TMPTR78.UINT16[H]
+#define RSCAN0TMPTR78HL RSCAN0.TMPTR78.UINT8[HL]
+#define RSCAN0TMPTR78HH RSCAN0.TMPTR78.UINT8[HH]
+#define RSCAN0TMDF078 RSCAN0.TMDF078.UINT32
+#define RSCAN0TMDF078L RSCAN0.TMDF078.UINT16[L]
+#define RSCAN0TMDF078LL RSCAN0.TMDF078.UINT8[LL]
+#define RSCAN0TMDF078LH RSCAN0.TMDF078.UINT8[LH]
+#define RSCAN0TMDF078H RSCAN0.TMDF078.UINT16[H]
+#define RSCAN0TMDF078HL RSCAN0.TMDF078.UINT8[HL]
+#define RSCAN0TMDF078HH RSCAN0.TMDF078.UINT8[HH]
+#define RSCAN0TMDF178 RSCAN0.TMDF178.UINT32
+#define RSCAN0TMDF178L RSCAN0.TMDF178.UINT16[L]
+#define RSCAN0TMDF178LL RSCAN0.TMDF178.UINT8[LL]
+#define RSCAN0TMDF178LH RSCAN0.TMDF178.UINT8[LH]
+#define RSCAN0TMDF178H RSCAN0.TMDF178.UINT16[H]
+#define RSCAN0TMDF178HL RSCAN0.TMDF178.UINT8[HL]
+#define RSCAN0TMDF178HH RSCAN0.TMDF178.UINT8[HH]
+#define RSCAN0TMID79 RSCAN0.TMID79.UINT32
+#define RSCAN0TMID79L RSCAN0.TMID79.UINT16[L]
+#define RSCAN0TMID79LL RSCAN0.TMID79.UINT8[LL]
+#define RSCAN0TMID79LH RSCAN0.TMID79.UINT8[LH]
+#define RSCAN0TMID79H RSCAN0.TMID79.UINT16[H]
+#define RSCAN0TMID79HL RSCAN0.TMID79.UINT8[HL]
+#define RSCAN0TMID79HH RSCAN0.TMID79.UINT8[HH]
+#define RSCAN0TMPTR79 RSCAN0.TMPTR79.UINT32
+#define RSCAN0TMPTR79L RSCAN0.TMPTR79.UINT16[L]
+#define RSCAN0TMPTR79LL RSCAN0.TMPTR79.UINT8[LL]
+#define RSCAN0TMPTR79LH RSCAN0.TMPTR79.UINT8[LH]
+#define RSCAN0TMPTR79H RSCAN0.TMPTR79.UINT16[H]
+#define RSCAN0TMPTR79HL RSCAN0.TMPTR79.UINT8[HL]
+#define RSCAN0TMPTR79HH RSCAN0.TMPTR79.UINT8[HH]
+#define RSCAN0TMDF079 RSCAN0.TMDF079.UINT32
+#define RSCAN0TMDF079L RSCAN0.TMDF079.UINT16[L]
+#define RSCAN0TMDF079LL RSCAN0.TMDF079.UINT8[LL]
+#define RSCAN0TMDF079LH RSCAN0.TMDF079.UINT8[LH]
+#define RSCAN0TMDF079H RSCAN0.TMDF079.UINT16[H]
+#define RSCAN0TMDF079HL RSCAN0.TMDF079.UINT8[HL]
+#define RSCAN0TMDF079HH RSCAN0.TMDF079.UINT8[HH]
+#define RSCAN0TMDF179 RSCAN0.TMDF179.UINT32
+#define RSCAN0TMDF179L RSCAN0.TMDF179.UINT16[L]
+#define RSCAN0TMDF179LL RSCAN0.TMDF179.UINT8[LL]
+#define RSCAN0TMDF179LH RSCAN0.TMDF179.UINT8[LH]
+#define RSCAN0TMDF179H RSCAN0.TMDF179.UINT16[H]
+#define RSCAN0TMDF179HL RSCAN0.TMDF179.UINT8[HL]
+#define RSCAN0TMDF179HH RSCAN0.TMDF179.UINT8[HH]
+#define RSCAN0THLACC0 RSCAN0.THLACC0.UINT32
+#define RSCAN0THLACC0L RSCAN0.THLACC0.UINT16[L]
+#define RSCAN0THLACC0LL RSCAN0.THLACC0.UINT8[LL]
+#define RSCAN0THLACC0LH RSCAN0.THLACC0.UINT8[LH]
+#define RSCAN0THLACC0H RSCAN0.THLACC0.UINT16[H]
+#define RSCAN0THLACC0HL RSCAN0.THLACC0.UINT8[HL]
+#define RSCAN0THLACC0HH RSCAN0.THLACC0.UINT8[HH]
+#define RSCAN0THLACC1 RSCAN0.THLACC1.UINT32
+#define RSCAN0THLACC1L RSCAN0.THLACC1.UINT16[L]
+#define RSCAN0THLACC1LL RSCAN0.THLACC1.UINT8[LL]
+#define RSCAN0THLACC1LH RSCAN0.THLACC1.UINT8[LH]
+#define RSCAN0THLACC1H RSCAN0.THLACC1.UINT16[H]
+#define RSCAN0THLACC1HL RSCAN0.THLACC1.UINT8[HL]
+#define RSCAN0THLACC1HH RSCAN0.THLACC1.UINT8[HH]
+#define RSCAN0THLACC2 RSCAN0.THLACC2.UINT32
+#define RSCAN0THLACC2L RSCAN0.THLACC2.UINT16[L]
+#define RSCAN0THLACC2LL RSCAN0.THLACC2.UINT8[LL]
+#define RSCAN0THLACC2LH RSCAN0.THLACC2.UINT8[LH]
+#define RSCAN0THLACC2H RSCAN0.THLACC2.UINT16[H]
+#define RSCAN0THLACC2HL RSCAN0.THLACC2.UINT8[HL]
+#define RSCAN0THLACC2HH RSCAN0.THLACC2.UINT8[HH]
+#define RSCAN0THLACC3 RSCAN0.THLACC3.UINT32
+#define RSCAN0THLACC3L RSCAN0.THLACC3.UINT16[L]
+#define RSCAN0THLACC3LL RSCAN0.THLACC3.UINT8[LL]
+#define RSCAN0THLACC3LH RSCAN0.THLACC3.UINT8[LH]
+#define RSCAN0THLACC3H RSCAN0.THLACC3.UINT16[H]
+#define RSCAN0THLACC3HL RSCAN0.THLACC3.UINT8[HL]
+#define RSCAN0THLACC3HH RSCAN0.THLACC3.UINT8[HH]
+#define RSCAN0THLACC4 RSCAN0.THLACC4.UINT32
+#define RSCAN0THLACC4L RSCAN0.THLACC4.UINT16[L]
+#define RSCAN0THLACC4LL RSCAN0.THLACC4.UINT8[LL]
+#define RSCAN0THLACC4LH RSCAN0.THLACC4.UINT8[LH]
+#define RSCAN0THLACC4H RSCAN0.THLACC4.UINT16[H]
+#define RSCAN0THLACC4HL RSCAN0.THLACC4.UINT8[HL]
+#define RSCAN0THLACC4HH RSCAN0.THLACC4.UINT8[HH]
+/* <-SEC M1.10.1 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/rspi_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,205 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rspi_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RSPI_IODEFINE_H
+#define RSPI_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+#include "reg32_t.h"
+
+struct st_rspi
+{                                                          /* RSPI             */
+    volatile uint8_t   SPCR;                                   /*  SPCR            */
+    volatile uint8_t   SSLP;                                   /*  SSLP            */
+    volatile uint8_t   SPPCR;                                  /*  SPPCR           */
+    volatile uint8_t   SPSR;                                   /*  SPSR            */
+    union reg32_t  SPDR;                          /*  SPDR            */
+    
+    volatile uint8_t   SPSCR;                                  /*  SPSCR           */
+    volatile uint8_t   SPSSR;                                  /*  SPSSR           */
+    volatile uint8_t   SPBR;                                   /*  SPBR            */
+    volatile uint8_t   SPDCR;                                  /*  SPDCR           */
+    volatile uint8_t   SPCKD;                                  /*  SPCKD           */
+    volatile uint8_t   SSLND;                                  /*  SSLND           */
+    volatile uint8_t   SPND;                                   /*  SPND            */
+    volatile uint8_t   dummy1[1];                              /*                  */
+#define SPCMD_COUNT 4
+    volatile uint16_t SPCMD0;                                 /*  SPCMD0          */
+    volatile uint16_t SPCMD1;                                 /*  SPCMD1          */
+    volatile uint16_t SPCMD2;                                 /*  SPCMD2          */
+    volatile uint16_t SPCMD3;                                 /*  SPCMD3          */
+    volatile uint8_t   dummy2[8];                              /*                  */
+    volatile uint8_t   SPBFCR;                                 /*  SPBFCR          */
+    volatile uint8_t   dummy3[1];                              /*                  */
+    volatile uint16_t SPBFDR;                                 /*  SPBFDR          */
+};
+
+
+#define RSPI0   (*(struct st_rspi    *)0xE800C800uL) /* RSPI0 */
+#define RSPI1   (*(struct st_rspi    *)0xE800D000uL) /* RSPI1 */
+#define RSPI2   (*(struct st_rspi    *)0xE800D800uL) /* RSPI2 */
+#define RSPI3   (*(struct st_rspi    *)0xE800E000uL) /* RSPI3 */
+#define RSPI4   (*(struct st_rspi    *)0xE800E800uL) /* RSPI4 */
+
+
+/* Start of channnel array defines of RSPI */
+
+/* Channnel array defines of RSPI */
+/*(Sample) value = RSPI[ channel ]->SPCR; */
+#define RSPI_COUNT  5
+#define RSPI_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of RSPI */
+
+
+#define SPCR_0 RSPI0.SPCR
+#define SSLP_0 RSPI0.SSLP
+#define SPPCR_0 RSPI0.SPPCR
+#define SPSR_0 RSPI0.SPSR
+#define SPDR_0   RSPI0.SPDR.UINT32
+#define SPDR_0L  RSPI0.SPDR.UINT16[L]
+#define SPDR_0H  RSPI0.SPDR.UINT16[H]
+#define SPDR_0LL RSPI0.SPDR.UINT8[LL]
+#define SPDR_0LH RSPI0.SPDR.UINT8[LH]
+#define SPDR_0HL RSPI0.SPDR.UINT8[HL]
+#define SPDR_0HH RSPI0.SPDR.UINT8[HH]
+#define SPSCR_0 RSPI0.SPSCR
+#define SPSSR_0 RSPI0.SPSSR
+#define SPBR_0 RSPI0.SPBR
+#define SPDCR_0 RSPI0.SPDCR
+#define SPCKD_0 RSPI0.SPCKD
+#define SSLND_0 RSPI0.SSLND
+#define SPND_0 RSPI0.SPND
+#define SPCMD0_0 RSPI0.SPCMD0
+#define SPCMD1_0 RSPI0.SPCMD1
+#define SPCMD2_0 RSPI0.SPCMD2
+#define SPCMD3_0 RSPI0.SPCMD3
+#define SPBFCR_0 RSPI0.SPBFCR
+#define SPBFDR_0 RSPI0.SPBFDR
+#define SPCR_1 RSPI1.SPCR
+#define SSLP_1 RSPI1.SSLP
+#define SPPCR_1 RSPI1.SPPCR
+#define SPSR_1 RSPI1.SPSR
+#define SPDR_1   RSPI1.SPDR.UINT32
+#define SPDR_1L  RSPI1.SPDR.UINT16[L]
+#define SPDR_1H  RSPI1.SPDR.UINT16[H]
+#define SPDR_1LL RSPI1.SPDR.UINT8[LL]
+#define SPDR_1LH RSPI1.SPDR.UINT8[LH]
+#define SPDR_1HL RSPI1.SPDR.UINT8[HL]
+#define SPDR_1HH RSPI1.SPDR.UINT8[HH]
+#define SPSCR_1 RSPI1.SPSCR
+#define SPSSR_1 RSPI1.SPSSR
+#define SPBR_1 RSPI1.SPBR
+#define SPDCR_1 RSPI1.SPDCR
+#define SPCKD_1 RSPI1.SPCKD
+#define SSLND_1 RSPI1.SSLND
+#define SPND_1 RSPI1.SPND
+#define SPCMD0_1 RSPI1.SPCMD0
+#define SPCMD1_1 RSPI1.SPCMD1
+#define SPCMD2_1 RSPI1.SPCMD2
+#define SPCMD3_1 RSPI1.SPCMD3
+#define SPBFCR_1 RSPI1.SPBFCR
+#define SPBFDR_1 RSPI1.SPBFDR
+#define SPCR_2 RSPI2.SPCR
+#define SSLP_2 RSPI2.SSLP
+#define SPPCR_2 RSPI2.SPPCR
+#define SPSR_2 RSPI2.SPSR
+#define SPDR_2   RSPI2.SPDR.UINT32
+#define SPDR_2L  RSPI2.SPDR.UINT16[L]
+#define SPDR_2H  RSPI2.SPDR.UINT16[H]
+#define SPDR_2LL RSPI2.SPDR.UINT8[LL]
+#define SPDR_2LH RSPI2.SPDR.UINT8[LH]
+#define SPDR_2HL RSPI2.SPDR.UINT8[HL]
+#define SPDR_2HH RSPI2.SPDR.UINT8[HH]
+#define SPSCR_2 RSPI2.SPSCR
+#define SPSSR_2 RSPI2.SPSSR
+#define SPBR_2 RSPI2.SPBR
+#define SPDCR_2 RSPI2.SPDCR
+#define SPCKD_2 RSPI2.SPCKD
+#define SSLND_2 RSPI2.SSLND
+#define SPND_2 RSPI2.SPND
+#define SPCMD0_2 RSPI2.SPCMD0
+#define SPCMD1_2 RSPI2.SPCMD1
+#define SPCMD2_2 RSPI2.SPCMD2
+#define SPCMD3_2 RSPI2.SPCMD3
+#define SPBFCR_2 RSPI2.SPBFCR
+#define SPBFDR_2 RSPI2.SPBFDR
+#define SPCR_3 RSPI3.SPCR
+#define SSLP_3 RSPI3.SSLP
+#define SPPCR_3 RSPI3.SPPCR
+#define SPSR_3 RSPI3.SPSR
+#define SPDR_3   RSPI3.SPDR.UINT32
+#define SPDR_3L  RSPI3.SPDR.UINT16[L]
+#define SPDR_3H  RSPI3.SPDR.UINT16[H]
+#define SPDR_3LL RSPI3.SPDR.UINT8[LL]
+#define SPDR_3LH RSPI3.SPDR.UINT8[LH]
+#define SPDR_3HL RSPI3.SPDR.UINT8[HL]
+#define SPDR_3HH RSPI3.SPDR.UINT8[HH]
+#define SPSCR_3 RSPI3.SPSCR
+#define SPSSR_3 RSPI3.SPSSR
+#define SPBR_3 RSPI3.SPBR
+#define SPDCR_3 RSPI3.SPDCR
+#define SPCKD_3 RSPI3.SPCKD
+#define SSLND_3 RSPI3.SSLND
+#define SPND_3 RSPI3.SPND
+#define SPCMD0_3 RSPI3.SPCMD0
+#define SPCMD1_3 RSPI3.SPCMD1
+#define SPCMD2_3 RSPI3.SPCMD2
+#define SPCMD3_3 RSPI3.SPCMD3
+#define SPBFCR_3 RSPI3.SPBFCR
+#define SPBFDR_3 RSPI3.SPBFDR
+#define SPCR_4 RSPI4.SPCR
+#define SSLP_4 RSPI4.SSLP
+#define SPPCR_4 RSPI4.SPPCR
+#define SPSR_4 RSPI4.SPSR
+#define SPDR_4   RSPI4.SPDR.UINT32
+#define SPDR_4L  RSPI4.SPDR.UINT16[L]
+#define SPDR_4H  RSPI4.SPDR.UINT16[H]
+#define SPDR_4LL RSPI4.SPDR.UINT8[LL]
+#define SPDR_4LH RSPI4.SPDR.UINT8[LH]
+#define SPDR_4HL RSPI4.SPDR.UINT8[HL]
+#define SPDR_4HH RSPI4.SPDR.UINT8[HH]
+#define SPSCR_4 RSPI4.SPSCR
+#define SPSSR_4 RSPI4.SPSSR
+#define SPBR_4 RSPI4.SPBR
+#define SPDCR_4 RSPI4.SPDCR
+#define SPCKD_4 RSPI4.SPCKD
+#define SSLND_4 RSPI4.SSLND
+#define SPND_4 RSPI4.SPND
+#define SPCMD0_4 RSPI4.SPCMD0
+#define SPCMD1_4 RSPI4.SPCMD1
+#define SPCMD2_4 RSPI4.SPCMD2
+#define SPCMD3_4 RSPI4.SPCMD3
+#define SPBFCR_4 RSPI4.SPBFCR
+#define SPBFDR_4 RSPI4.SPBFDR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/rtc_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,103 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : rtc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef RTC_IODEFINE_H
+#define RTC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_rtc
+{                                                          /* RTC              */
+    volatile uint8_t   R64CNT;                                 /*  R64CNT          */
+    volatile uint8_t   dummy537[1];                            /*                  */
+    volatile uint8_t   RSECCNT;                                /*  RSECCNT         */
+    volatile uint8_t   dummy538[1];                            /*                  */
+    volatile uint8_t   RMINCNT;                                /*  RMINCNT         */
+    volatile uint8_t   dummy539[1];                            /*                  */
+    volatile uint8_t   RHRCNT;                                 /*  RHRCNT          */
+    volatile uint8_t   dummy540[1];                            /*                  */
+    volatile uint8_t   RWKCNT;                                 /*  RWKCNT          */
+    volatile uint8_t   dummy541[1];                            /*                  */
+    volatile uint8_t   RDAYCNT;                                /*  RDAYCNT         */
+    volatile uint8_t   dummy542[1];                            /*                  */
+    volatile uint8_t   RMONCNT;                                /*  RMONCNT         */
+    volatile uint8_t   dummy543[1];                            /*                  */
+    volatile uint16_t RYRCNT;                                 /*  RYRCNT          */
+    volatile uint8_t   RSECAR;                                 /*  RSECAR          */
+    volatile uint8_t   dummy544[1];                            /*                  */
+    volatile uint8_t   RMINAR;                                 /*  RMINAR          */
+    volatile uint8_t   dummy545[1];                            /*                  */
+    volatile uint8_t   RHRAR;                                  /*  RHRAR           */
+    volatile uint8_t   dummy546[1];                            /*                  */
+    volatile uint8_t   RWKAR;                                  /*  RWKAR           */
+    volatile uint8_t   dummy547[1];                            /*                  */
+    volatile uint8_t   RDAYAR;                                 /*  RDAYAR          */
+    volatile uint8_t   dummy548[1];                            /*                  */
+    volatile uint8_t   RMONAR;                                 /*  RMONAR          */
+    volatile uint8_t   dummy549[1];                            /*                  */
+    volatile uint8_t   RCR1;                                   /*  RCR1            */
+    volatile uint8_t   dummy550[1];                            /*                  */
+    volatile uint8_t   RCR2;                                   /*  RCR2            */
+    volatile uint8_t   dummy551[1];                            /*                  */
+    volatile uint16_t RYRAR;                                  /*  RYRAR           */
+    volatile uint8_t   dummy552[2];                            /*                  */
+    volatile uint8_t   RCR3;                                   /*  RCR3            */
+    volatile uint8_t   dummy553[1];                            /*                  */
+    volatile uint8_t   RCR5;                                   /*  RCR5            */
+    volatile uint8_t   dummy554[3];                            /*                  */
+    volatile uint16_t RFRH;                                   /*  RFRH            */
+    volatile uint16_t RFRL;                                   /*  RFRL            */
+};
+
+
+#define RTC     (*(struct st_rtc     *)0xFCFF1000uL) /* RTC */
+
+
+#define RTCR64CNT RTC.R64CNT
+#define RTCRSECCNT RTC.RSECCNT
+#define RTCRMINCNT RTC.RMINCNT
+#define RTCRHRCNT RTC.RHRCNT
+#define RTCRWKCNT RTC.RWKCNT
+#define RTCRDAYCNT RTC.RDAYCNT
+#define RTCRMONCNT RTC.RMONCNT
+#define RTCRYRCNT RTC.RYRCNT
+#define RTCRSECAR RTC.RSECAR
+#define RTCRMINAR RTC.RMINAR
+#define RTCRHRAR RTC.RHRAR
+#define RTCRWKAR RTC.RWKAR
+#define RTCRDAYAR RTC.RDAYAR
+#define RTCRMONAR RTC.RMONAR
+#define RTCRCR1 RTC.RCR1
+#define RTCRCR2 RTC.RCR2
+#define RTCRYRAR RTC.RYRAR
+#define RTCRCR3 RTC.RCR3
+#define RTCRCR5 RTC.RCR5
+#define RTCRFRH RTC.RFRH
+#define RTCRFRL RTC.RFRL
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/scif_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,183 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scif_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SCIF_IODEFINE_H
+#define SCIF_IODEFINE_H
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_scif
+{                                                          /* SCIF             */
+    volatile uint16_t SCSMR;                                  /*  SCSMR           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+    volatile uint8_t   SCBRR;                                  /*  SCBRR           */
+    volatile uint8_t   dummy2[3];                              /*                  */
+    volatile uint16_t SCSCR;                                  /*  SCSCR           */
+    volatile uint8_t   dummy3[2];                              /*                  */
+    volatile uint8_t   SCFTDR;                                 /*  SCFTDR          */
+    volatile uint8_t   dummy4[3];                              /*                  */
+    volatile uint16_t SCFSR;                                  /*  SCFSR           */
+    volatile uint8_t   dummy5[2];                              /*                  */
+    volatile uint8_t   SCFRDR;                                 /*  SCFRDR          */
+    volatile uint8_t   dummy6[3];                              /*                  */
+    volatile uint16_t SCFCR;                                  /*  SCFCR           */
+    volatile uint8_t   dummy7[2];                              /*                  */
+    volatile uint16_t SCFDR;                                  /*  SCFDR           */
+    volatile uint8_t   dummy8[2];                              /*                  */
+    volatile uint16_t SCSPTR;                                 /*  SCSPTR          */
+    volatile uint8_t   dummy9[2];                              /*                  */
+    volatile uint16_t SCLSR;                                  /*  SCLSR           */
+    volatile uint8_t   dummy10[2];                             /*                  */
+    volatile uint16_t SCEMR;                                  /*  SCEMR           */
+};
+
+
+#define SCIF0   (*(struct st_scif    *)0xE8007000uL) /* SCIF0 */
+#define SCIF1   (*(struct st_scif    *)0xE8007800uL) /* SCIF1 */
+#define SCIF2   (*(struct st_scif    *)0xE8008000uL) /* SCIF2 */
+#define SCIF3   (*(struct st_scif    *)0xE8008800uL) /* SCIF3 */
+#define SCIF4   (*(struct st_scif    *)0xE8009000uL) /* SCIF4 */
+#define SCIF5   (*(struct st_scif    *)0xE8009800uL) /* SCIF5 */
+#define SCIF6   (*(struct st_scif    *)0xE800A000uL) /* SCIF6 */
+#define SCIF7   (*(struct st_scif    *)0xE800A800uL) /* SCIF7 */
+
+#define P_SCIF0   (0xE8007000uL) /* SCIF0 */
+#define P_SCIF1   (0xE8007800uL) /* SCIF1 */
+#define P_SCIF2   (0xE8008000uL) /* SCIF2 */
+#define P_SCIF3   (0xE8008800uL) /* SCIF3 */
+#define P_SCIF4   (0xE8009000uL) /* SCIF4 */
+#define P_SCIF5   (0xE8009800uL) /* SCIF5 */
+#define P_SCIF6   (0xE800A000uL) /* SCIF6 */
+#define P_SCIF7   (0xE800A800uL) /* SCIF7 */
+
+
+/* Start of channnel array defines of SCIF */
+
+/* Channnel array defines of SCIF */
+/*(Sample) value = SCIF[ channel ]->SCSMR; */
+#define SCIF_COUNT  8
+#define SCIF_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SCIF */
+
+
+#define SCSMR_0 SCIF0.SCSMR
+#define SCBRR_0 SCIF0.SCBRR
+#define SCSCR_0 SCIF0.SCSCR
+#define SCFTDR_0 SCIF0.SCFTDR
+#define SCFSR_0 SCIF0.SCFSR
+#define SCFRDR_0 SCIF0.SCFRDR
+#define SCFCR_0 SCIF0.SCFCR
+#define SCFDR_0 SCIF0.SCFDR
+#define SCSPTR_0 SCIF0.SCSPTR
+#define SCLSR_0 SCIF0.SCLSR
+#define SCEMR_0 SCIF0.SCEMR
+#define SCSMR_1 SCIF1.SCSMR
+#define SCBRR_1 SCIF1.SCBRR
+#define SCSCR_1 SCIF1.SCSCR
+#define SCFTDR_1 SCIF1.SCFTDR
+#define SCFSR_1 SCIF1.SCFSR
+#define SCFRDR_1 SCIF1.SCFRDR
+#define SCFCR_1 SCIF1.SCFCR
+#define SCFDR_1 SCIF1.SCFDR
+#define SCSPTR_1 SCIF1.SCSPTR
+#define SCLSR_1 SCIF1.SCLSR
+#define SCEMR_1 SCIF1.SCEMR
+#define SCSMR_2 SCIF2.SCSMR
+#define SCBRR_2 SCIF2.SCBRR
+#define SCSCR_2 SCIF2.SCSCR
+#define SCFTDR_2 SCIF2.SCFTDR
+#define SCFSR_2 SCIF2.SCFSR
+#define SCFRDR_2 SCIF2.SCFRDR
+#define SCFCR_2 SCIF2.SCFCR
+#define SCFDR_2 SCIF2.SCFDR
+#define SCSPTR_2 SCIF2.SCSPTR
+#define SCLSR_2 SCIF2.SCLSR
+#define SCEMR_2 SCIF2.SCEMR
+#define SCSMR_3 SCIF3.SCSMR
+#define SCBRR_3 SCIF3.SCBRR
+#define SCSCR_3 SCIF3.SCSCR
+#define SCFTDR_3 SCIF3.SCFTDR
+#define SCFSR_3 SCIF3.SCFSR
+#define SCFRDR_3 SCIF3.SCFRDR
+#define SCFCR_3 SCIF3.SCFCR
+#define SCFDR_3 SCIF3.SCFDR
+#define SCSPTR_3 SCIF3.SCSPTR
+#define SCLSR_3 SCIF3.SCLSR
+#define SCEMR_3 SCIF3.SCEMR
+#define SCSMR_4 SCIF4.SCSMR
+#define SCBRR_4 SCIF4.SCBRR
+#define SCSCR_4 SCIF4.SCSCR
+#define SCFTDR_4 SCIF4.SCFTDR
+#define SCFSR_4 SCIF4.SCFSR
+#define SCFRDR_4 SCIF4.SCFRDR
+#define SCFCR_4 SCIF4.SCFCR
+#define SCFDR_4 SCIF4.SCFDR
+#define SCSPTR_4 SCIF4.SCSPTR
+#define SCLSR_4 SCIF4.SCLSR
+#define SCEMR_4 SCIF4.SCEMR
+#define SCSMR_5 SCIF5.SCSMR
+#define SCBRR_5 SCIF5.SCBRR
+#define SCSCR_5 SCIF5.SCSCR
+#define SCFTDR_5 SCIF5.SCFTDR
+#define SCFSR_5 SCIF5.SCFSR
+#define SCFRDR_5 SCIF5.SCFRDR
+#define SCFCR_5 SCIF5.SCFCR
+#define SCFDR_5 SCIF5.SCFDR
+#define SCSPTR_5 SCIF5.SCSPTR
+#define SCLSR_5 SCIF5.SCLSR
+#define SCEMR_5 SCIF5.SCEMR
+#define SCSMR_6 SCIF6.SCSMR
+#define SCBRR_6 SCIF6.SCBRR
+#define SCSCR_6 SCIF6.SCSCR
+#define SCFTDR_6 SCIF6.SCFTDR
+#define SCFSR_6 SCIF6.SCFSR
+#define SCFRDR_6 SCIF6.SCFRDR
+#define SCFCR_6 SCIF6.SCFCR
+#define SCFDR_6 SCIF6.SCFDR
+#define SCSPTR_6 SCIF6.SCSPTR
+#define SCLSR_6 SCIF6.SCLSR
+#define SCEMR_6 SCIF6.SCEMR
+#define SCSMR_7 SCIF7.SCSMR
+#define SCBRR_7 SCIF7.SCBRR
+#define SCSCR_7 SCIF7.SCSCR
+#define SCFTDR_7 SCIF7.SCFTDR
+#define SCFSR_7 SCIF7.SCFSR
+#define SCFRDR_7 SCIF7.SCFRDR
+#define SCFCR_7 SCIF7.SCFCR
+#define SCFDR_7 SCIF7.SCFDR
+#define SCSPTR_7 SCIF7.SCSPTR
+#define SCLSR_7 SCIF7.SCLSR
+#define SCEMR_7 SCIF7.SCEMR
+/* <-SEC M1.10.1 */
+/* <-QAC 0857 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/scim_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,88 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scim_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SCIM_IODEFINE_H
+#define SCIM_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_scim
+{                                                          /* SCIM             */
+    volatile uint8_t   SMR;                                    /*  SMR             */
+    volatile uint8_t   BRR;                                    /*  BRR             */
+    volatile uint8_t   SCR;                                    /*  SCR             */
+    volatile uint8_t   TDR;                                    /*  TDR             */
+    volatile uint8_t   SSR;                                    /*  SSR             */
+    volatile uint8_t   RDR;                                    /*  RDR             */
+    volatile uint8_t   SCMR;                                   /*  SCMR            */
+    volatile uint8_t   SEMR;                                   /*  SEMR            */
+    volatile uint8_t   SNFR;                                   /*  SNFR            */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint8_t   SECR;                                   /*  SECR            */
+};
+
+
+#define SCIM0   (*(struct st_scim    *)0xE800B000uL) /* SCIM0 */
+#define SCIM1   (*(struct st_scim    *)0xE800B800uL) /* SCIM1 */
+
+
+/* Start of channnel array defines of SCIM */
+
+/* Channnel array defines of SCIM */
+/*(Sample) value = SCIM[ channel ]->SMR; */
+#define SCIM_COUNT  2
+#define SCIM_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCIM0, &SCIM1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SCIM */
+
+
+#define SMR0 SCIM0.SMR
+#define BRR0 SCIM0.BRR
+#define SCR0 SCIM0.SCR
+#define TDR0 SCIM0.TDR
+#define SSR0 SCIM0.SSR
+#define RDR0 SCIM0.RDR
+#define SCMR0 SCIM0.SCMR
+#define SEMR0 SCIM0.SEMR
+#define SNFR0 SCIM0.SNFR
+#define SECR0 SCIM0.SECR
+#define SMR1 SCIM1.SMR
+#define BRR1 SCIM1.BRR
+#define SCR1 SCIM1.SCR
+#define TDR1 SCIM1.TDR
+#define SSR1 SCIM1.SSR
+#define RDR1 SCIM1.RDR
+#define SCMR1 SCIM1.SCMR
+#define SEMR1 SCIM1.SEMR
+#define SNFR1 SCIM1.SNFR
+#define SECR1 SCIM1.SECR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/scux_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,809 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : scux_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SCUX_IODEFINE_H
+#define SCUX_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_scux
+{                                                          /* SCUX             */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+    volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
+    volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
+    volatile uint8_t   dummy259[248];                          /*                  */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+    volatile uint32_t  IPCIR_IPC0_1;                           /*  IPCIR_IPC0_1    */
+    volatile uint32_t  IPSLR_IPC0_1;                           /*  IPSLR_IPC0_1    */
+    volatile uint8_t   dummy260[248];                          /*                  */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+    volatile uint32_t  IPCIR_IPC0_2;                           /*  IPCIR_IPC0_2    */
+    volatile uint32_t  IPSLR_IPC0_2;                           /*  IPSLR_IPC0_2    */
+    volatile uint8_t   dummy261[248];                          /*                  */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_ipcir_ipc0_n */
+    volatile uint32_t  IPCIR_IPC0_3;                           /*  IPCIR_IPC0_3    */
+    volatile uint32_t  IPSLR_IPC0_3;                           /*  IPSLR_IPC0_3    */
+    volatile uint8_t   dummy262[248];                          /*                  */
+/* end of struct st_scux_from_ipcir_ipc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+    volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
+    volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
+    volatile uint8_t   dummy263[248];                          /*                  */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+    volatile uint32_t  OPCIR_OPC0_1;                           /*  OPCIR_OPC0_1    */
+    volatile uint32_t  OPSLR_OPC0_1;                           /*  OPSLR_OPC0_1    */
+    volatile uint8_t   dummy264[248];                          /*                  */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+    volatile uint32_t  OPCIR_OPC0_2;                           /*  OPCIR_OPC0_2    */
+    volatile uint32_t  OPSLR_OPC0_2;                           /*  OPSLR_OPC0_2    */
+    volatile uint8_t   dummy265[248];                          /*                  */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_opcir_opc0_n */
+    volatile uint32_t  OPCIR_OPC0_3;                           /*  OPCIR_OPC0_3    */
+    volatile uint32_t  OPSLR_OPC0_3;                           /*  OPSLR_OPC0_3    */
+    volatile uint8_t   dummy266[248];                          /*                  */
+/* end of struct st_scux_from_opcir_opc0_n */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
+    volatile uint32_t  FDAIR_FFD0_0;                           /*  FDAIR_FFD0_0    */
+    volatile uint32_t  DRQSR_FFD0_0;                           /*  DRQSR_FFD0_0    */
+    volatile uint32_t  FFDPR_FFD0_0;                           /*  FFDPR_FFD0_0    */
+    volatile uint32_t  FFDBR_FFD0_0;                           /*  FFDBR_FFD0_0    */
+    volatile uint32_t  DEVMR_FFD0_0;                           /*  DEVMR_FFD0_0    */
+    volatile uint8_t   dummy267[4];                            /*                  */
+    volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint8_t   dummy268[224];                          /*                  */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint32_t  FFDIR_FFD0_1;                           /*  FFDIR_FFD0_1    */
+    volatile uint32_t  FDAIR_FFD0_1;                           /*  FDAIR_FFD0_1    */
+    volatile uint32_t  DRQSR_FFD0_1;                           /*  DRQSR_FFD0_1    */
+    volatile uint32_t  FFDPR_FFD0_1;                           /*  FFDPR_FFD0_1    */
+    volatile uint32_t  FFDBR_FFD0_1;                           /*  FFDBR_FFD0_1    */
+    volatile uint32_t  DEVMR_FFD0_1;                           /*  DEVMR_FFD0_1    */
+    volatile uint8_t   dummy269[4];                            /*                  */
+    volatile uint32_t  DEVCR_FFD0_1;                           /*  DEVCR_FFD0_1    */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint8_t   dummy270[224];                          /*                  */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint32_t  FFDIR_FFD0_2;                           /*  FFDIR_FFD0_2    */
+    volatile uint32_t  FDAIR_FFD0_2;                           /*  FDAIR_FFD0_2    */
+    volatile uint32_t  DRQSR_FFD0_2;                           /*  DRQSR_FFD0_2    */
+    volatile uint32_t  FFDPR_FFD0_2;                           /*  FFDPR_FFD0_2    */
+    volatile uint32_t  FFDBR_FFD0_2;                           /*  FFDBR_FFD0_2    */
+    volatile uint32_t  DEVMR_FFD0_2;                           /*  DEVMR_FFD0_2    */
+    volatile uint8_t   dummy271[4];                            /*                  */
+    volatile uint32_t  DEVCR_FFD0_2;                           /*  DEVCR_FFD0_2    */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint8_t   dummy272[224];                          /*                  */
+/* start of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint32_t  FFDIR_FFD0_3;                           /*  FFDIR_FFD0_3    */
+    volatile uint32_t  FDAIR_FFD0_3;                           /*  FDAIR_FFD0_3    */
+    volatile uint32_t  DRQSR_FFD0_3;                           /*  DRQSR_FFD0_3    */
+    volatile uint32_t  FFDPR_FFD0_3;                           /*  FFDPR_FFD0_3    */
+    volatile uint32_t  FFDBR_FFD0_3;                           /*  FFDBR_FFD0_3    */
+    volatile uint32_t  DEVMR_FFD0_3;                           /*  DEVMR_FFD0_3    */
+    volatile uint8_t   dummy273[4];                            /*                  */
+    volatile uint32_t  DEVCR_FFD0_3;                           /*  DEVCR_FFD0_3    */
+/* end of struct st_scux_from_ffdir_ffd0_n */
+    volatile uint8_t   dummy274[224];                          /*                  */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
+    volatile uint32_t  FUAIR_FFU0_0;                           /*  FUAIR_FFU0_0    */
+    volatile uint32_t  URQSR_FFU0_0;                           /*  URQSR_FFU0_0    */
+    volatile uint32_t  FFUPR_FFU0_0;                           /*  FFUPR_FFU0_0    */
+    volatile uint32_t  UEVMR_FFU0_0;                           /*  UEVMR_FFU0_0    */
+    volatile uint8_t   dummy275[4];                            /*                  */
+    volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint8_t   dummy276[228];                          /*                  */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint32_t  FFUIR_FFU0_1;                           /*  FFUIR_FFU0_1    */
+    volatile uint32_t  FUAIR_FFU0_1;                           /*  FUAIR_FFU0_1    */
+    volatile uint32_t  URQSR_FFU0_1;                           /*  URQSR_FFU0_1    */
+    volatile uint32_t  FFUPR_FFU0_1;                           /*  FFUPR_FFU0_1    */
+    volatile uint32_t  UEVMR_FFU0_1;                           /*  UEVMR_FFU0_1    */
+    volatile uint8_t   dummy277[4];                            /*                  */
+    volatile uint32_t  UEVCR_FFU0_1;                           /*  UEVCR_FFU0_1    */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint8_t   dummy278[228];                          /*                  */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint32_t  FFUIR_FFU0_2;                           /*  FFUIR_FFU0_2    */
+    volatile uint32_t  FUAIR_FFU0_2;                           /*  FUAIR_FFU0_2    */
+    volatile uint32_t  URQSR_FFU0_2;                           /*  URQSR_FFU0_2    */
+    volatile uint32_t  FFUPR_FFU0_2;                           /*  FFUPR_FFU0_2    */
+    volatile uint32_t  UEVMR_FFU0_2;                           /*  UEVMR_FFU0_2    */
+    volatile uint8_t   dummy279[4];                            /*                  */
+    volatile uint32_t  UEVCR_FFU0_2;                           /*  UEVCR_FFU0_2    */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint8_t   dummy280[228];                          /*                  */
+/* start of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint32_t  FFUIR_FFU0_3;                           /*  FFUIR_FFU0_3    */
+    volatile uint32_t  FUAIR_FFU0_3;                           /*  FUAIR_FFU0_3    */
+    volatile uint32_t  URQSR_FFU0_3;                           /*  URQSR_FFU0_3    */
+    volatile uint32_t  FFUPR_FFU0_3;                           /*  FFUPR_FFU0_3    */
+    volatile uint32_t  UEVMR_FFU0_3;                           /*  UEVMR_FFU0_3    */
+    volatile uint8_t   dummy281[4];                            /*                  */
+    volatile uint32_t  UEVCR_FFU0_3;                           /*  UEVCR_FFU0_3    */
+/* end of struct st_scux_from_ffuir_ffu0_n */
+    volatile uint8_t   dummy282[228];                          /*                  */
+/* start of struct st_scux_from_srcir0_2src0_n */
+    volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
+    volatile uint32_t  SADIR0_2SRC0_0;                         /*  SADIR0_2SRC0_0  */
+    volatile uint32_t  SRCBR0_2SRC0_0;                         /*  SRCBR0_2SRC0_0  */
+    volatile uint32_t  IFSCR0_2SRC0_0;                         /*  IFSCR0_2SRC0_0  */
+    volatile uint32_t  IFSVR0_2SRC0_0;                         /*  IFSVR0_2SRC0_0  */
+    volatile uint32_t  SRCCR0_2SRC0_0;                         /*  SRCCR0_2SRC0_0  */
+    volatile uint32_t  MNFSR0_2SRC0_0;                         /*  MNFSR0_2SRC0_0  */
+    volatile uint32_t  BFSSR0_2SRC0_0;                         /*  BFSSR0_2SRC0_0  */
+    volatile uint32_t  SC2SR0_2SRC0_0;                         /*  SC2SR0_2SRC0_0  */
+    volatile uint32_t  WATSR0_2SRC0_0;                         /*  WATSR0_2SRC0_0  */
+    volatile uint32_t  SEVMR0_2SRC0_0;                         /*  SEVMR0_2SRC0_0  */
+    volatile uint8_t   dummy283[4];                            /*                  */
+    volatile uint32_t  SEVCR0_2SRC0_0;                         /*  SEVCR0_2SRC0_0  */
+    volatile uint32_t  SRCIR1_2SRC0_0;                         /*  SRCIR1_2SRC0_0  */
+    volatile uint32_t  SADIR1_2SRC0_0;                         /*  SADIR1_2SRC0_0  */
+    volatile uint32_t  SRCBR1_2SRC0_0;                         /*  SRCBR1_2SRC0_0  */
+    volatile uint32_t  IFSCR1_2SRC0_0;                         /*  IFSCR1_2SRC0_0  */
+    volatile uint32_t  IFSVR1_2SRC0_0;                         /*  IFSVR1_2SRC0_0  */
+    volatile uint32_t  SRCCR1_2SRC0_0;                         /*  SRCCR1_2SRC0_0  */
+    volatile uint32_t  MNFSR1_2SRC0_0;                         /*  MNFSR1_2SRC0_0  */
+    volatile uint32_t  BFSSR1_2SRC0_0;                         /*  BFSSR1_2SRC0_0  */
+    volatile uint32_t  SC2SR1_2SRC0_0;                         /*  SC2SR1_2SRC0_0  */
+    volatile uint32_t  WATSR1_2SRC0_0;                         /*  WATSR1_2SRC0_0  */
+    volatile uint32_t  SEVMR1_2SRC0_0;                         /*  SEVMR1_2SRC0_0  */
+    volatile uint8_t   dummy284[4];                            /*                  */
+    volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
+    volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
+/* end of struct st_scux_from_srcir0_2src0_n */
+    volatile uint8_t   dummy285[148];                          /*                  */
+/* start of struct st_scux_from_srcir0_2src0_n */
+    volatile uint32_t  SRCIR0_2SRC0_1;                         /*  SRCIR0_2SRC0_1  */
+    volatile uint32_t  SADIR0_2SRC0_1;                         /*  SADIR0_2SRC0_1  */
+    volatile uint32_t  SRCBR0_2SRC0_1;                         /*  SRCBR0_2SRC0_1  */
+    volatile uint32_t  IFSCR0_2SRC0_1;                         /*  IFSCR0_2SRC0_1  */
+    volatile uint32_t  IFSVR0_2SRC0_1;                         /*  IFSVR0_2SRC0_1  */
+    volatile uint32_t  SRCCR0_2SRC0_1;                         /*  SRCCR0_2SRC0_1  */
+    volatile uint32_t  MNFSR0_2SRC0_1;                         /*  MNFSR0_2SRC0_1  */
+    volatile uint32_t  BFSSR0_2SRC0_1;                         /*  BFSSR0_2SRC0_1  */
+    volatile uint32_t  SC2SR0_2SRC0_1;                         /*  SC2SR0_2SRC0_1  */
+    volatile uint32_t  WATSR0_2SRC0_1;                         /*  WATSR0_2SRC0_1  */
+    volatile uint32_t  SEVMR0_2SRC0_1;                         /*  SEVMR0_2SRC0_1  */
+    volatile uint8_t   dummy286[4];                            /*                  */
+    volatile uint32_t  SEVCR0_2SRC0_1;                         /*  SEVCR0_2SRC0_1  */
+    volatile uint32_t  SRCIR1_2SRC0_1;                         /*  SRCIR1_2SRC0_1  */
+    volatile uint32_t  SADIR1_2SRC0_1;                         /*  SADIR1_2SRC0_1  */
+    volatile uint32_t  SRCBR1_2SRC0_1;                         /*  SRCBR1_2SRC0_1  */
+    volatile uint32_t  IFSCR1_2SRC0_1;                         /*  IFSCR1_2SRC0_1  */
+    volatile uint32_t  IFSVR1_2SRC0_1;                         /*  IFSVR1_2SRC0_1  */
+    volatile uint32_t  SRCCR1_2SRC0_1;                         /*  SRCCR1_2SRC0_1  */
+    volatile uint32_t  MNFSR1_2SRC0_1;                         /*  MNFSR1_2SRC0_1  */
+    volatile uint32_t  BFSSR1_2SRC0_1;                         /*  BFSSR1_2SRC0_1  */
+    volatile uint32_t  SC2SR1_2SRC0_1;                         /*  SC2SR1_2SRC0_1  */
+    volatile uint32_t  WATSR1_2SRC0_1;                         /*  WATSR1_2SRC0_1  */
+    volatile uint32_t  SEVMR1_2SRC0_1;                         /*  SEVMR1_2SRC0_1  */
+    volatile uint8_t   dummy287[4];                            /*                  */
+    volatile uint32_t  SEVCR1_2SRC0_1;                         /*  SEVCR1_2SRC0_1  */
+    volatile uint32_t  SRCIRR_2SRC0_1;                         /*  SRCIRR_2SRC0_1  */
+/* end of struct st_scux_from_srcir0_2src0_n */
+    volatile uint8_t   dummy288[148];                          /*                  */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
+    volatile uint32_t  VADIR_DVU0_0;                           /*  VADIR_DVU0_0    */
+    volatile uint32_t  DVUBR_DVU0_0;                           /*  DVUBR_DVU0_0    */
+    volatile uint32_t  DVUCR_DVU0_0;                           /*  DVUCR_DVU0_0    */
+    volatile uint32_t  ZCMCR_DVU0_0;                           /*  ZCMCR_DVU0_0    */
+    volatile uint32_t  VRCTR_DVU0_0;                           /*  VRCTR_DVU0_0    */
+    volatile uint32_t  VRPDR_DVU0_0;                           /*  VRPDR_DVU0_0    */
+    volatile uint32_t  VRDBR_DVU0_0;                           /*  VRDBR_DVU0_0    */
+    volatile uint32_t  VRWTR_DVU0_0;                           /*  VRWTR_DVU0_0    */
+    volatile uint32_t  VOL0R_DVU0_0;                           /*  VOL0R_DVU0_0    */
+    volatile uint32_t  VOL1R_DVU0_0;                           /*  VOL1R_DVU0_0    */
+    volatile uint32_t  VOL2R_DVU0_0;                           /*  VOL2R_DVU0_0    */
+    volatile uint32_t  VOL3R_DVU0_0;                           /*  VOL3R_DVU0_0    */
+    volatile uint32_t  VOL4R_DVU0_0;                           /*  VOL4R_DVU0_0    */
+    volatile uint32_t  VOL5R_DVU0_0;                           /*  VOL5R_DVU0_0    */
+    volatile uint32_t  VOL6R_DVU0_0;                           /*  VOL6R_DVU0_0    */
+    volatile uint32_t  VOL7R_DVU0_0;                           /*  VOL7R_DVU0_0    */
+    volatile uint32_t  DVUER_DVU0_0;                           /*  DVUER_DVU0_0    */
+    volatile uint32_t  DVUSR_DVU0_0;                           /*  DVUSR_DVU0_0    */
+    volatile uint32_t  VEVMR_DVU0_0;                           /*  VEVMR_DVU0_0    */
+    volatile uint8_t   dummy289[4];                            /*                  */
+    volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint8_t   dummy290[168];                          /*                  */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint32_t  DVUIR_DVU0_1;                           /*  DVUIR_DVU0_1    */
+    volatile uint32_t  VADIR_DVU0_1;                           /*  VADIR_DVU0_1    */
+    volatile uint32_t  DVUBR_DVU0_1;                           /*  DVUBR_DVU0_1    */
+    volatile uint32_t  DVUCR_DVU0_1;                           /*  DVUCR_DVU0_1    */
+    volatile uint32_t  ZCMCR_DVU0_1;                           /*  ZCMCR_DVU0_1    */
+    volatile uint32_t  VRCTR_DVU0_1;                           /*  VRCTR_DVU0_1    */
+    volatile uint32_t  VRPDR_DVU0_1;                           /*  VRPDR_DVU0_1    */
+    volatile uint32_t  VRDBR_DVU0_1;                           /*  VRDBR_DVU0_1    */
+    volatile uint32_t  VRWTR_DVU0_1;                           /*  VRWTR_DVU0_1    */
+    volatile uint32_t  VOL0R_DVU0_1;                           /*  VOL0R_DVU0_1    */
+    volatile uint32_t  VOL1R_DVU0_1;                           /*  VOL1R_DVU0_1    */
+    volatile uint32_t  VOL2R_DVU0_1;                           /*  VOL2R_DVU0_1    */
+    volatile uint32_t  VOL3R_DVU0_1;                           /*  VOL3R_DVU0_1    */
+    volatile uint32_t  VOL4R_DVU0_1;                           /*  VOL4R_DVU0_1    */
+    volatile uint32_t  VOL5R_DVU0_1;                           /*  VOL5R_DVU0_1    */
+    volatile uint32_t  VOL6R_DVU0_1;                           /*  VOL6R_DVU0_1    */
+    volatile uint32_t  VOL7R_DVU0_1;                           /*  VOL7R_DVU0_1    */
+    volatile uint32_t  DVUER_DVU0_1;                           /*  DVUER_DVU0_1    */
+    volatile uint32_t  DVUSR_DVU0_1;                           /*  DVUSR_DVU0_1    */
+    volatile uint32_t  VEVMR_DVU0_1;                           /*  VEVMR_DVU0_1    */
+    volatile uint8_t   dummy291[4];                            /*                  */
+    volatile uint32_t  VEVCR_DVU0_1;                           /*  VEVCR_DVU0_1    */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint8_t   dummy292[168];                          /*                  */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint32_t  DVUIR_DVU0_2;                           /*  DVUIR_DVU0_2    */
+    volatile uint32_t  VADIR_DVU0_2;                           /*  VADIR_DVU0_2    */
+    volatile uint32_t  DVUBR_DVU0_2;                           /*  DVUBR_DVU0_2    */
+    volatile uint32_t  DVUCR_DVU0_2;                           /*  DVUCR_DVU0_2    */
+    volatile uint32_t  ZCMCR_DVU0_2;                           /*  ZCMCR_DVU0_2    */
+    volatile uint32_t  VRCTR_DVU0_2;                           /*  VRCTR_DVU0_2    */
+    volatile uint32_t  VRPDR_DVU0_2;                           /*  VRPDR_DVU0_2    */
+    volatile uint32_t  VRDBR_DVU0_2;                           /*  VRDBR_DVU0_2    */
+    volatile uint32_t  VRWTR_DVU0_2;                           /*  VRWTR_DVU0_2    */
+    volatile uint32_t  VOL0R_DVU0_2;                           /*  VOL0R_DVU0_2    */
+    volatile uint32_t  VOL1R_DVU0_2;                           /*  VOL1R_DVU0_2    */
+    volatile uint32_t  VOL2R_DVU0_2;                           /*  VOL2R_DVU0_2    */
+    volatile uint32_t  VOL3R_DVU0_2;                           /*  VOL3R_DVU0_2    */
+    volatile uint32_t  VOL4R_DVU0_2;                           /*  VOL4R_DVU0_2    */
+    volatile uint32_t  VOL5R_DVU0_2;                           /*  VOL5R_DVU0_2    */
+    volatile uint32_t  VOL6R_DVU0_2;                           /*  VOL6R_DVU0_2    */
+    volatile uint32_t  VOL7R_DVU0_2;                           /*  VOL7R_DVU0_2    */
+    volatile uint32_t  DVUER_DVU0_2;                           /*  DVUER_DVU0_2    */
+    volatile uint32_t  DVUSR_DVU0_2;                           /*  DVUSR_DVU0_2    */
+    volatile uint32_t  VEVMR_DVU0_2;                           /*  VEVMR_DVU0_2    */
+    volatile uint8_t   dummy293[4];                            /*                  */
+    volatile uint32_t  VEVCR_DVU0_2;                           /*  VEVCR_DVU0_2    */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint8_t   dummy294[168];                          /*                  */
+/* start of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint32_t  DVUIR_DVU0_3;                           /*  DVUIR_DVU0_3    */
+    volatile uint32_t  VADIR_DVU0_3;                           /*  VADIR_DVU0_3    */
+    volatile uint32_t  DVUBR_DVU0_3;                           /*  DVUBR_DVU0_3    */
+    volatile uint32_t  DVUCR_DVU0_3;                           /*  DVUCR_DVU0_3    */
+    volatile uint32_t  ZCMCR_DVU0_3;                           /*  ZCMCR_DVU0_3    */
+    volatile uint32_t  VRCTR_DVU0_3;                           /*  VRCTR_DVU0_3    */
+    volatile uint32_t  VRPDR_DVU0_3;                           /*  VRPDR_DVU0_3    */
+    volatile uint32_t  VRDBR_DVU0_3;                           /*  VRDBR_DVU0_3    */
+    volatile uint32_t  VRWTR_DVU0_3;                           /*  VRWTR_DVU0_3    */
+    volatile uint32_t  VOL0R_DVU0_3;                           /*  VOL0R_DVU0_3    */
+    volatile uint32_t  VOL1R_DVU0_3;                           /*  VOL1R_DVU0_3    */
+    volatile uint32_t  VOL2R_DVU0_3;                           /*  VOL2R_DVU0_3    */
+    volatile uint32_t  VOL3R_DVU0_3;                           /*  VOL3R_DVU0_3    */
+    volatile uint32_t  VOL4R_DVU0_3;                           /*  VOL4R_DVU0_3    */
+    volatile uint32_t  VOL5R_DVU0_3;                           /*  VOL5R_DVU0_3    */
+    volatile uint32_t  VOL6R_DVU0_3;                           /*  VOL6R_DVU0_3    */
+    volatile uint32_t  VOL7R_DVU0_3;                           /*  VOL7R_DVU0_3    */
+    volatile uint32_t  DVUER_DVU0_3;                           /*  DVUER_DVU0_3    */
+    volatile uint32_t  DVUSR_DVU0_3;                           /*  DVUSR_DVU0_3    */
+    volatile uint32_t  VEVMR_DVU0_3;                           /*  VEVMR_DVU0_3    */
+    volatile uint8_t   dummy295[4];                            /*                  */
+    volatile uint32_t  VEVCR_DVU0_3;                           /*  VEVCR_DVU0_3    */
+/* end of struct st_scux_from_dvuir_dvu0_n */
+    volatile uint8_t   dummy296[168];                          /*                  */
+    volatile uint32_t  MIXIR_MIX0_0;                           /*  MIXIR_MIX0_0    */
+    volatile uint32_t  MADIR_MIX0_0;                           /*  MADIR_MIX0_0    */
+    volatile uint32_t  MIXBR_MIX0_0;                           /*  MIXBR_MIX0_0    */
+    volatile uint32_t  MIXMR_MIX0_0;                           /*  MIXMR_MIX0_0    */
+    volatile uint32_t  MVPDR_MIX0_0;                           /*  MVPDR_MIX0_0    */
+    volatile uint32_t  MDBAR_MIX0_0;                           /*  MDBAR_MIX0_0    */
+    volatile uint32_t  MDBBR_MIX0_0;                           /*  MDBBR_MIX0_0    */
+    volatile uint32_t  MDBCR_MIX0_0;                           /*  MDBCR_MIX0_0    */
+    volatile uint32_t  MDBDR_MIX0_0;                           /*  MDBDR_MIX0_0    */
+    volatile uint32_t  MDBER_MIX0_0;                           /*  MDBER_MIX0_0    */
+    volatile uint32_t  MIXSR_MIX0_0;                           /*  MIXSR_MIX0_0    */
+    volatile uint8_t   dummy297[212];                          /*                  */
+    volatile uint32_t  SWRSR_CIM;                              /*  SWRSR_CIM       */
+    volatile uint32_t  DMACR_CIM;                              /*  DMACR_CIM       */
+#define SCUX_DMATDn_CIM_COUNT 4
+    union iodefine_reg32_16_t  DMATD0_CIM;                 /*  DMATD0_CIM      */
+    union iodefine_reg32_16_t  DMATD1_CIM;                 /*  DMATD1_CIM      */
+    union iodefine_reg32_16_t  DMATD2_CIM;                 /*  DMATD2_CIM      */
+    union iodefine_reg32_16_t  DMATD3_CIM;                 /*  DMATD3_CIM      */
+#define SCUX_DMATUn_CIM_COUNT 4
+    union iodefine_reg32_16_t  DMATU0_CIM;                 /*  DMATU0_CIM      */
+    union iodefine_reg32_16_t  DMATU1_CIM;                 /*  DMATU1_CIM      */
+    union iodefine_reg32_16_t  DMATU2_CIM;                 /*  DMATU2_CIM      */
+    union iodefine_reg32_16_t  DMATU3_CIM;                 /*  DMATU3_CIM      */
+    
+    volatile uint8_t   dummy298[16];                           /*                  */
+    volatile uint32_t  SSIRSEL_CIM;                            /*  SSIRSEL_CIM     */
+#define SCUX_FDTSELn_CIM_COUNT 4
+    volatile uint32_t  FDTSEL0_CIM;                            /*  FDTSEL0_CIM     */
+    volatile uint32_t  FDTSEL1_CIM;                            /*  FDTSEL1_CIM     */
+    volatile uint32_t  FDTSEL2_CIM;                            /*  FDTSEL2_CIM     */
+    volatile uint32_t  FDTSEL3_CIM;                            /*  FDTSEL3_CIM     */
+#define SCUX_FUTSELn_CIM_COUNT 4
+    volatile uint32_t  FUTSEL0_CIM;                            /*  FUTSEL0_CIM     */
+    volatile uint32_t  FUTSEL1_CIM;                            /*  FUTSEL1_CIM     */
+    volatile uint32_t  FUTSEL2_CIM;                            /*  FUTSEL2_CIM     */
+    volatile uint32_t  FUTSEL3_CIM;                            /*  FUTSEL3_CIM     */
+    volatile uint32_t  SSIPMD_CIM;                             /*  SSIPMD_CIM      */
+    volatile uint32_t  SSICTRL_CIM;                            /*  SSICTRL_CIM     */
+#define SCUX_SRCRSELn_CIM_COUNT 4
+    volatile uint32_t  SRCRSEL0_CIM;                           /*  SRCRSEL0_CIM    */
+    volatile uint32_t  SRCRSEL1_CIM;                           /*  SRCRSEL1_CIM    */
+    volatile uint32_t  SRCRSEL2_CIM;                           /*  SRCRSEL2_CIM    */
+    volatile uint32_t  SRCRSEL3_CIM;                           /*  SRCRSEL3_CIM    */
+    volatile uint32_t  MIXRSEL_CIM;                            /*  MIXRSEL_CIM     */
+};
+
+
+struct st_scux_from_ipcir_ipc0_n
+{
+    volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
+    volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
+    volatile uint8_t   dummy1[248];                            /*                  */
+};
+
+
+struct st_scux_from_opcir_opc0_n
+{
+    volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
+    volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
+    volatile uint8_t   dummy1[248];                            /*                  */
+};
+
+
+struct st_scux_from_ffdir_ffd0_n
+{
+    volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
+    volatile uint32_t  FDAIR_FFD0_0;                           /*  FDAIR_FFD0_0    */
+    volatile uint32_t  DRQSR_FFD0_0;                           /*  DRQSR_FFD0_0    */
+    volatile uint32_t  FFDPR_FFD0_0;                           /*  FFDPR_FFD0_0    */
+    volatile uint32_t  FFDBR_FFD0_0;                           /*  FFDBR_FFD0_0    */
+    volatile uint32_t  DEVMR_FFD0_0;                           /*  DEVMR_FFD0_0    */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
+};
+
+
+struct st_scux_from_ffuir_ffu0_n
+{
+    volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
+    volatile uint32_t  FUAIR_FFU0_0;                           /*  FUAIR_FFU0_0    */
+    volatile uint32_t  URQSR_FFU0_0;                           /*  URQSR_FFU0_0    */
+    volatile uint32_t  FFUPR_FFU0_0;                           /*  FFUPR_FFU0_0    */
+    volatile uint32_t  UEVMR_FFU0_0;                           /*  UEVMR_FFU0_0    */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
+};
+
+
+struct st_scux_from_srcir0_2src0_n
+{
+    volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
+    volatile uint32_t  SADIR0_2SRC0_0;                         /*  SADIR0_2SRC0_0  */
+    volatile uint32_t  SRCBR0_2SRC0_0;                         /*  SRCBR0_2SRC0_0  */
+    volatile uint32_t  IFSCR0_2SRC0_0;                         /*  IFSCR0_2SRC0_0  */
+    volatile uint32_t  IFSVR0_2SRC0_0;                         /*  IFSVR0_2SRC0_0  */
+    volatile uint32_t  SRCCR0_2SRC0_0;                         /*  SRCCR0_2SRC0_0  */
+    volatile uint32_t  MNFSR0_2SRC0_0;                         /*  MNFSR0_2SRC0_0  */
+    volatile uint32_t  BFSSR0_2SRC0_0;                         /*  BFSSR0_2SRC0_0  */
+    volatile uint32_t  SC2SR0_2SRC0_0;                         /*  SC2SR0_2SRC0_0  */
+    volatile uint32_t  WATSR0_2SRC0_0;                         /*  WATSR0_2SRC0_0  */
+    volatile uint32_t  SEVMR0_2SRC0_0;                         /*  SEVMR0_2SRC0_0  */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint32_t  SEVCR0_2SRC0_0;                         /*  SEVCR0_2SRC0_0  */
+    volatile uint32_t  SRCIR1_2SRC0_0;                         /*  SRCIR1_2SRC0_0  */
+    volatile uint32_t  SADIR1_2SRC0_0;                         /*  SADIR1_2SRC0_0  */
+    volatile uint32_t  SRCBR1_2SRC0_0;                         /*  SRCBR1_2SRC0_0  */
+    volatile uint32_t  IFSCR1_2SRC0_0;                         /*  IFSCR1_2SRC0_0  */
+    volatile uint32_t  IFSVR1_2SRC0_0;                         /*  IFSVR1_2SRC0_0  */
+    volatile uint32_t  SRCCR1_2SRC0_0;                         /*  SRCCR1_2SRC0_0  */
+    volatile uint32_t  MNFSR1_2SRC0_0;                         /*  MNFSR1_2SRC0_0  */
+    volatile uint32_t  BFSSR1_2SRC0_0;                         /*  BFSSR1_2SRC0_0  */
+    volatile uint32_t  SC2SR1_2SRC0_0;                         /*  SC2SR1_2SRC0_0  */
+    volatile uint32_t  WATSR1_2SRC0_0;                         /*  WATSR1_2SRC0_0  */
+    volatile uint32_t  SEVMR1_2SRC0_0;                         /*  SEVMR1_2SRC0_0  */
+    volatile uint8_t   dummy2[4];                              /*                  */
+    volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
+    volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
+};
+
+
+struct st_scux_from_dvuir_dvu0_n
+{
+    volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
+    volatile uint32_t  VADIR_DVU0_0;                           /*  VADIR_DVU0_0    */
+    volatile uint32_t  DVUBR_DVU0_0;                           /*  DVUBR_DVU0_0    */
+    volatile uint32_t  DVUCR_DVU0_0;                           /*  DVUCR_DVU0_0    */
+    volatile uint32_t  ZCMCR_DVU0_0;                           /*  ZCMCR_DVU0_0    */
+    volatile uint32_t  VRCTR_DVU0_0;                           /*  VRCTR_DVU0_0    */
+    volatile uint32_t  VRPDR_DVU0_0;                           /*  VRPDR_DVU0_0    */
+    volatile uint32_t  VRDBR_DVU0_0;                           /*  VRDBR_DVU0_0    */
+    volatile uint32_t  VRWTR_DVU0_0;                           /*  VRWTR_DVU0_0    */
+    volatile uint32_t  VOL0R_DVU0_0;                           /*  VOL0R_DVU0_0    */
+    volatile uint32_t  VOL1R_DVU0_0;                           /*  VOL1R_DVU0_0    */
+    volatile uint32_t  VOL2R_DVU0_0;                           /*  VOL2R_DVU0_0    */
+    volatile uint32_t  VOL3R_DVU0_0;                           /*  VOL3R_DVU0_0    */
+    volatile uint32_t  VOL4R_DVU0_0;                           /*  VOL4R_DVU0_0    */
+    volatile uint32_t  VOL5R_DVU0_0;                           /*  VOL5R_DVU0_0    */
+    volatile uint32_t  VOL6R_DVU0_0;                           /*  VOL6R_DVU0_0    */
+    volatile uint32_t  VOL7R_DVU0_0;                           /*  VOL7R_DVU0_0    */
+    volatile uint32_t  DVUER_DVU0_0;                           /*  DVUER_DVU0_0    */
+    volatile uint32_t  DVUSR_DVU0_0;                           /*  DVUSR_DVU0_0    */
+    volatile uint32_t  VEVMR_DVU0_0;                           /*  VEVMR_DVU0_0    */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
+};
+
+
+#define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
+
+
+/* Start of channnel array defines of SCUX */
+
+/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  4
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
+#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
+#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
+#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  2
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
+#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
+
+
+/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  4
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
+#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
+#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
+#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  4
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
+#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
+#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
+#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  4
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
+#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
+#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
+#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
+
+
+/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  4
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
+#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
+#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
+#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
+
+/* End of channnel array defines of SCUX */
+
+
+#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
+#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
+#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
+#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
+#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
+#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
+#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
+#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
+#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
+#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
+#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
+#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
+#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
+#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
+#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
+#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
+#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
+#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
+#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
+#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
+#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
+#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
+#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
+#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
+#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
+#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
+#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
+#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
+#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
+#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
+#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
+#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
+#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
+#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
+#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
+#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
+#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
+#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
+#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
+#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
+#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
+#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
+#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
+#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
+#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
+#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
+#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
+#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
+#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
+#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
+#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
+#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
+#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
+#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
+#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
+#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
+#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
+#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
+#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
+#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
+#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
+#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
+#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
+#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
+#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
+#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
+#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
+#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
+#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
+#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
+#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
+#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
+#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
+#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
+#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
+#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
+#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
+#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
+#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
+#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
+#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
+#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
+#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
+#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
+#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
+#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
+#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
+#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
+#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
+#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
+#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
+#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
+#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
+#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
+#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
+#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
+#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
+#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
+#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
+#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
+#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
+#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
+#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
+#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
+#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
+#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
+#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
+#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
+#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
+#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
+#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
+#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
+#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
+#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
+#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
+#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
+#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
+#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
+#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
+#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
+#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
+#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
+#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
+#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
+#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
+#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
+#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
+#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
+#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
+#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
+#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
+#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
+#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
+#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
+#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
+#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
+#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
+#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
+#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
+#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
+#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
+#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
+#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
+#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
+#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
+#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
+#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
+#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
+#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
+#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
+#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
+#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
+#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
+#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
+#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
+#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
+#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
+#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
+#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
+#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
+#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
+#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
+#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
+#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
+#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
+#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
+#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
+#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
+#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
+#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
+#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
+#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
+#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
+#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
+#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
+#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
+#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
+#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
+#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
+#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
+#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
+#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
+#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
+#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
+#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
+#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
+#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
+#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
+#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
+#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
+#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
+#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
+#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
+#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
+#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
+#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
+#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
+#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
+#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
+#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
+#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
+#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
+#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
+#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
+#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
+#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
+#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
+#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
+#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
+#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
+#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
+#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
+#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
+#define SCUXSWRSR_CIM SCUX.SWRSR_CIM
+#define SCUXDMACR_CIM SCUX.DMACR_CIM
+#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
+#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
+#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
+#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
+#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
+#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
+#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
+#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
+#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
+#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
+#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
+#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
+#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
+#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
+#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
+#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
+#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
+#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
+#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
+#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
+#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
+#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
+#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
+#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
+#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
+#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
+#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
+#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
+#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
+#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
+#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
+#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
+#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
+#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
+#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
+#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
+#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
+#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
+#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
+#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/sdg_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,87 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : sdg_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SDG_IODEFINE_H
+#define SDG_IODEFINE_H
+
+struct st_sdg
+{                                                          /* SDG              */
+    volatile uint8_t   SGCR1;                                  /*  SGCR1           */
+    volatile uint8_t   SGCSR;                                  /*  SGCSR           */
+    volatile uint8_t   SGCR2;                                  /*  SGCR2           */
+    volatile uint8_t   SGLR;                                   /*  SGLR            */
+    volatile uint8_t   SGTFR;                                  /*  SGTFR           */
+    volatile uint8_t   SGSFR;                                  /*  SGSFR           */
+};
+
+
+#define SDG0    (*(struct st_sdg     *)0xFCFF4800uL) /* SDG0 */
+#define SDG1    (*(struct st_sdg     *)0xFCFF4A00uL) /* SDG1 */
+#define SDG2    (*(struct st_sdg     *)0xFCFF4C00uL) /* SDG2 */
+#define SDG3    (*(struct st_sdg     *)0xFCFF4E00uL) /* SDG3 */
+
+
+/* Start of channnel array defines of SDG */
+
+/* Channnel array defines of SDG */
+/*(Sample) value = SDG[ channel ]->SGCR1; */
+#define SDG_COUNT  4
+#define SDG_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SDG0, &SDG1, &SDG2, &SDG3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SDG */
+
+
+#define SGCR1_0 SDG0.SGCR1
+#define SGCSR_0 SDG0.SGCSR
+#define SGCR2_0 SDG0.SGCR2
+#define SGLR_0 SDG0.SGLR
+#define SGTFR_0 SDG0.SGTFR
+#define SGSFR_0 SDG0.SGSFR
+#define SGCR1_1 SDG1.SGCR1
+#define SGCSR_1 SDG1.SGCSR
+#define SGCR2_1 SDG1.SGCR2
+#define SGLR_1 SDG1.SGLR
+#define SGTFR_1 SDG1.SGTFR
+#define SGSFR_1 SDG1.SGSFR
+#define SGCR1_2 SDG2.SGCR1
+#define SGCSR_2 SDG2.SGCSR
+#define SGCR2_2 SDG2.SGCR2
+#define SGLR_2 SDG2.SGLR
+#define SGTFR_2 SDG2.SGTFR
+#define SGSFR_2 SDG2.SGSFR
+#define SGCR1_3 SDG3.SGCR1
+#define SGCSR_3 SDG3.SGCSR
+#define SGCR2_3 SDG3.SGCR2
+#define SGLR_3 SDG3.SGLR
+#define SGTFR_3 SDG3.SGTFR
+#define SGSFR_3 SDG3.SGSFR
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/spdif_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,69 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : spdif_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SPDIF_IODEFINE_H
+#define SPDIF_IODEFINE_H
+
+struct st_spdif
+{                                                          /* SPDIF            */
+    volatile uint32_t  TLCA;                                   /*  TLCA            */
+    volatile uint32_t  TRCA;                                   /*  TRCA            */
+    volatile uint32_t  TLCS;                                   /*  TLCS            */
+    volatile uint32_t  TRCS;                                   /*  TRCS            */
+    volatile uint32_t  TUI;                                    /*  TUI             */
+    volatile uint32_t  RLCA;                                   /*  RLCA            */
+    volatile uint32_t  RRCA;                                   /*  RRCA            */
+    volatile uint32_t  RLCS;                                   /*  RLCS            */
+    volatile uint32_t  RRCS;                                   /*  RRCS            */
+    volatile uint32_t  RUI;                                    /*  RUI             */
+    volatile uint32_t  CTRL;                                   /*  CTRL            */
+    volatile uint32_t  STAT;                                   /*  STAT            */
+    volatile uint32_t  TDAD;                                   /*  TDAD            */
+    volatile uint32_t  RDAD;                                   /*  RDAD            */
+};
+
+
+#define SPDIF   (*(struct st_spdif   *)0xE8012000uL) /* SPDIF */
+
+
+#define SPDIFTLCA SPDIF.TLCA
+#define SPDIFTRCA SPDIF.TRCA
+#define SPDIFTLCS SPDIF.TLCS
+#define SPDIFTRCS SPDIF.TRCS
+#define SPDIFTUI SPDIF.TUI
+#define SPDIFRLCA SPDIF.RLCA
+#define SPDIFRRCA SPDIF.RRCA
+#define SPDIFRLCS SPDIF.RLCS
+#define SPDIFRRCS SPDIF.RRCS
+#define SPDIFRUI SPDIF.RUI
+#define SPDIFCTRL SPDIF.CTRL
+#define SPDIFSTAT SPDIF.STAT
+#define SPDIFTDAD SPDIF.TDAD
+#define SPDIFRDAD SPDIF.RDAD
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/spibsc_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,174 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : spibsc_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SPIBSC_IODEFINE_H
+#define SPIBSC_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_spibsc
+{                                                          /* SPIBSC           */
+    volatile uint32_t  CMNCR;                                  /*  CMNCR           */
+    volatile uint32_t  SSLDR;                                  /*  SSLDR           */
+    volatile uint32_t  SPBCR;                                  /*  SPBCR           */
+    volatile uint32_t  DRCR;                                   /*  DRCR            */
+    volatile uint32_t  DRCMR;                                  /*  DRCMR           */
+    volatile uint32_t  DREAR;                                  /*  DREAR           */
+    volatile uint32_t  DROPR;                                  /*  DROPR           */
+    volatile uint32_t  DRENR;                                  /*  DRENR           */
+    volatile uint32_t  SMCR;                                   /*  SMCR            */
+    volatile uint32_t  SMCMR;                                  /*  SMCMR           */
+    volatile uint32_t  SMADR;                                  /*  SMADR           */
+    volatile uint32_t  SMOPR;                                  /*  SMOPR           */
+    volatile uint32_t  SMENR;                                  /*  SMENR           */
+    volatile uint8_t   dummy1[4];                              /*                  */
+    union iodefine_reg32_t  SMRDR0;                        /*  SMRDR0          */
+    union iodefine_reg32_t  SMRDR1;                        /*  SMRDR1          */
+    union iodefine_reg32_t  SMWDR0;                        /*  SMWDR0          */
+    union iodefine_reg32_t  SMWDR1;                        /*  SMWDR1          */
+    
+    volatile uint32_t  CMNSR;                                  /*  CMNSR           */
+    volatile uint8_t   dummy2[12];                             /*                  */
+    volatile uint32_t  DRDMCR;                                 /*  DRDMCR          */
+    volatile uint32_t  DRDRENR;                                /*  DRDRENR         */
+    volatile uint32_t  SMDMCR;                                 /*  SMDMCR          */
+    volatile uint32_t  SMDRENR;                                /*  SMDRENR         */
+};
+
+
+#define SPIBSC0 (*(struct st_spibsc  *)0x3FEFA000uL) /* SPIBSC0 */
+#define SPIBSC1 (*(struct st_spibsc  *)0x3FEFB000uL) /* SPIBSC1 */
+
+
+/* Start of channnel array defines of SPIBSC */
+
+/* Channnel array defines of SPIBSC */
+/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
+#define SPIBSC_COUNT  2
+#define SPIBSC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SPIBSC0, &SPIBSC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SPIBSC */
+
+
+#define CMNCR_0 SPIBSC0.CMNCR
+#define SSLDR_0 SPIBSC0.SSLDR
+#define SPBCR_0 SPIBSC0.SPBCR
+#define DRCR_0 SPIBSC0.DRCR
+#define DRCMR_0 SPIBSC0.DRCMR
+#define DREAR_0 SPIBSC0.DREAR
+#define DROPR_0 SPIBSC0.DROPR
+#define DRENR_0 SPIBSC0.DRENR
+#define SMCR_0 SPIBSC0.SMCR
+#define SMCMR_0 SPIBSC0.SMCMR
+#define SMADR_0 SPIBSC0.SMADR
+#define SMOPR_0 SPIBSC0.SMOPR
+#define SMENR_0 SPIBSC0.SMENR
+#define SMRDR0_0   SPIBSC0.SMRDR0.UINT32
+#define SMRDR0_0L  SPIBSC0.SMRDR0.UINT16[L]
+#define SMRDR0_0H  SPIBSC0.SMRDR0.UINT16[H]
+#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
+#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
+#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
+#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
+#define SMRDR1_0   SPIBSC0.SMRDR1.UINT32
+#define SMRDR1_0L  SPIBSC0.SMRDR1.UINT16[L]
+#define SMRDR1_0H  SPIBSC0.SMRDR1.UINT16[H]
+#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
+#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
+#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
+#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
+#define SMWDR0_0   SPIBSC0.SMWDR0.UINT32
+#define SMWDR0_0L  SPIBSC0.SMWDR0.UINT16[L]
+#define SMWDR0_0H  SPIBSC0.SMWDR0.UINT16[H]
+#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
+#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
+#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
+#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
+#define SMWDR1_0   SPIBSC0.SMWDR1.UINT32
+#define SMWDR1_0L  SPIBSC0.SMWDR1.UINT16[L]
+#define SMWDR1_0H  SPIBSC0.SMWDR1.UINT16[H]
+#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
+#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
+#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
+#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
+#define CMNSR_0 SPIBSC0.CMNSR
+#define DRDMCR_0 SPIBSC0.DRDMCR
+#define DRDRENR_0 SPIBSC0.DRDRENR
+#define SMDMCR_0 SPIBSC0.SMDMCR
+#define SMDRENR_0 SPIBSC0.SMDRENR
+#define CMNCR_1 SPIBSC1.CMNCR
+#define SSLDR_1 SPIBSC1.SSLDR
+#define SPBCR_1 SPIBSC1.SPBCR
+#define DRCR_1 SPIBSC1.DRCR
+#define DRCMR_1 SPIBSC1.DRCMR
+#define DREAR_1 SPIBSC1.DREAR
+#define DROPR_1 SPIBSC1.DROPR
+#define DRENR_1 SPIBSC1.DRENR
+#define SMCR_1 SPIBSC1.SMCR
+#define SMCMR_1 SPIBSC1.SMCMR
+#define SMADR_1 SPIBSC1.SMADR
+#define SMOPR_1 SPIBSC1.SMOPR
+#define SMENR_1 SPIBSC1.SMENR
+#define SMRDR0_1   SPIBSC1.SMRDR0.UINT32
+#define SMRDR0_1L  SPIBSC1.SMRDR0.UINT16[L]
+#define SMRDR0_1H  SPIBSC1.SMRDR0.UINT16[H]
+#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
+#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
+#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
+#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
+#define SMRDR1_1   SPIBSC1.SMRDR1.UINT32
+#define SMRDR1_1L  SPIBSC1.SMRDR1.UINT16[L]
+#define SMRDR1_1H  SPIBSC1.SMRDR1.UINT16[H]
+#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
+#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
+#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
+#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
+#define SMWDR0_1   SPIBSC1.SMWDR0.UINT32
+#define SMWDR0_1L  SPIBSC1.SMWDR0.UINT16[L]
+#define SMWDR0_1H  SPIBSC1.SMWDR0.UINT16[H]
+#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
+#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
+#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
+#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
+#define SMWDR1_1   SPIBSC1.SMWDR1.UINT32
+#define SMWDR1_1L  SPIBSC1.SMWDR1.UINT16[L]
+#define SMWDR1_1H  SPIBSC1.SMWDR1.UINT16[H]
+#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
+#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
+#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
+#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
+#define CMNSR_1 SPIBSC1.CMNSR
+#define DRDMCR_1 SPIBSC1.DRDMCR
+#define DRDRENR_1 SPIBSC1.DRDRENR
+#define SMDMCR_1 SPIBSC1.SMDMCR
+#define SMDRENR_1 SPIBSC1.SMDRENR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/ssif_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,132 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : ssif_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef SSIF_IODEFINE_H
+#define SSIF_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_ssif
+{                                                          /* SSIF             */
+    volatile uint32_t  SSICR;                                  /*  SSICR           */
+    volatile uint32_t  SSISR;                                  /*  SSISR           */
+    volatile uint8_t   dummy1[8];                              /*                  */
+    volatile uint32_t  SSIFCR;                                 /*  SSIFCR          */
+    volatile uint32_t  SSIFSR;                                 /*  SSIFSR          */
+    volatile uint32_t  SSIFTDR;                                /*  SSIFTDR         */
+    volatile uint32_t  SSIFRDR;                                /*  SSIFRDR         */
+    volatile uint32_t  SSITDMR;                                /*  SSITDMR         */
+    volatile uint32_t  SSIFCCR;                                /*  SSIFCCR         */
+    volatile uint32_t  SSIFCMR;                                /*  SSIFCMR         */
+    volatile uint32_t  SSIFCSR;                                /*  SSIFCSR         */
+};
+
+
+#define SSIF0   (*(struct st_ssif    *)0xE820B000uL) /* SSIF0 */
+#define SSIF1   (*(struct st_ssif    *)0xE820B800uL) /* SSIF1 */
+#define SSIF2   (*(struct st_ssif    *)0xE820C000uL) /* SSIF2 */
+#define SSIF3   (*(struct st_ssif    *)0xE820C800uL) /* SSIF3 */
+#define SSIF4   (*(struct st_ssif    *)0xE820D000uL) /* SSIF4 */
+#define SSIF5   (*(struct st_ssif    *)0xE820D800uL) /* SSIF5 */
+
+
+/* Start of channnel array defines of SSIF */
+
+/* Channnel array defines of SSIF */
+/*(Sample) value = SSIF[ channel ]->SSICR; */
+#define SSIF_COUNT  6
+#define SSIF_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channnel array defines of SSIF */
+
+
+#define SSICR_0 SSIF0.SSICR
+#define SSISR_0 SSIF0.SSISR
+#define SSIFCR_0 SSIF0.SSIFCR
+#define SSIFSR_0 SSIF0.SSIFSR
+#define SSIFTDR_0 SSIF0.SSIFTDR
+#define SSIFRDR_0 SSIF0.SSIFRDR
+#define SSITDMR_0 SSIF0.SSITDMR
+#define SSIFCCR_0 SSIF0.SSIFCCR
+#define SSIFCMR_0 SSIF0.SSIFCMR
+#define SSIFCSR_0 SSIF0.SSIFCSR
+#define SSICR_1 SSIF1.SSICR
+#define SSISR_1 SSIF1.SSISR
+#define SSIFCR_1 SSIF1.SSIFCR
+#define SSIFSR_1 SSIF1.SSIFSR
+#define SSIFTDR_1 SSIF1.SSIFTDR
+#define SSIFRDR_1 SSIF1.SSIFRDR
+#define SSITDMR_1 SSIF1.SSITDMR
+#define SSIFCCR_1 SSIF1.SSIFCCR
+#define SSIFCMR_1 SSIF1.SSIFCMR
+#define SSIFCSR_1 SSIF1.SSIFCSR
+#define SSICR_2 SSIF2.SSICR
+#define SSISR_2 SSIF2.SSISR
+#define SSIFCR_2 SSIF2.SSIFCR
+#define SSIFSR_2 SSIF2.SSIFSR
+#define SSIFTDR_2 SSIF2.SSIFTDR
+#define SSIFRDR_2 SSIF2.SSIFRDR
+#define SSITDMR_2 SSIF2.SSITDMR
+#define SSIFCCR_2 SSIF2.SSIFCCR
+#define SSIFCMR_2 SSIF2.SSIFCMR
+#define SSIFCSR_2 SSIF2.SSIFCSR
+#define SSICR_3 SSIF3.SSICR
+#define SSISR_3 SSIF3.SSISR
+#define SSIFCR_3 SSIF3.SSIFCR
+#define SSIFSR_3 SSIF3.SSIFSR
+#define SSIFTDR_3 SSIF3.SSIFTDR
+#define SSIFRDR_3 SSIF3.SSIFRDR
+#define SSITDMR_3 SSIF3.SSITDMR
+#define SSIFCCR_3 SSIF3.SSIFCCR
+#define SSIFCMR_3 SSIF3.SSIFCMR
+#define SSIFCSR_3 SSIF3.SSIFCSR
+#define SSICR_4 SSIF4.SSICR
+#define SSISR_4 SSIF4.SSISR
+#define SSIFCR_4 SSIF4.SSIFCR
+#define SSIFSR_4 SSIF4.SSIFSR
+#define SSIFTDR_4 SSIF4.SSIFTDR
+#define SSIFRDR_4 SSIF4.SSIFRDR
+#define SSITDMR_4 SSIF4.SSITDMR
+#define SSIFCCR_4 SSIF4.SSIFCCR
+#define SSIFCMR_4 SSIF4.SSIFCMR
+#define SSIFCSR_4 SSIF4.SSIFCSR
+#define SSICR_5 SSIF5.SSICR
+#define SSISR_5 SSIF5.SSISR
+#define SSIFCR_5 SSIF5.SSIFCR
+#define SSIFSR_5 SSIF5.SSIFSR
+#define SSIFTDR_5 SSIF5.SSIFTDR
+#define SSIFRDR_5 SSIF5.SSIFRDR
+#define SSITDMR_5 SSIF5.SSITDMR
+#define SSIFCCR_5 SSIF5.SSIFCCR
+#define SSIFCMR_5 SSIF5.SSIFCMR
+#define SSIFCSR_5 SSIF5.SSIFCSR
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/usb20_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,547 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb20_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef USB20_IODEFINE_H
+#define USB20_IODEFINE_H
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_usb20
+{                                                          /* USB20            */
+    volatile uint16_t SYSCFG0;                                /*  SYSCFG0         */
+    volatile uint16_t BUSWAIT;                                /*  BUSWAIT         */
+    volatile uint16_t SYSSTS0;                                /*  SYSSTS0         */
+    volatile uint8_t   dummy1[2];                              /*                  */
+    volatile uint16_t DVSTCTR0;                               /*  DVSTCTR0        */
+    volatile uint8_t   dummy2[2];                              /*                  */
+    volatile uint16_t TESTMODE;                               /*  TESTMODE        */
+    volatile uint8_t   dummy3[2];                              /*                  */
+#define USB20_D0FBCFG_COUNT 2
+    volatile uint16_t D0FBCFG;                                /*  D0FBCFG         */
+    volatile uint16_t D1FBCFG;                                /*  D1FBCFG         */
+    union iodefine_reg32_t  CFIFO;                         /*  CFIFO           */
+#define USB20_D0FIFO_COUNT 2
+    union iodefine_reg32_t  D0FIFO;                        /*  D0FIFO          */
+    union iodefine_reg32_t  D1FIFO;                        /*  D1FIFO          */
+    
+    volatile uint16_t CFIFOSEL;                               /*  CFIFOSEL        */
+    volatile uint16_t CFIFOCTR;                               /*  CFIFOCTR        */
+    volatile uint8_t   dummy4[4];                              /*                  */
+/* start of struct st_usb20_from_d0fifosel */
+    volatile uint16_t D0FIFOSEL;                              /*  D0FIFOSEL       */
+    volatile uint16_t D0FIFOCTR;                              /*  D0FIFOCTR       */
+/* end of struct st_usb20_from_d0fifosel */
+/* start of struct st_usb20_from_d0fifosel */
+    volatile uint16_t D1FIFOSEL;                              /*  D1FIFOSEL       */
+    volatile uint16_t D1FIFOCTR;                              /*  D1FIFOCTR       */
+/* end of struct st_usb20_from_d0fifosel */
+#define USB20_INTENB0_COUNT 2
+    volatile uint16_t INTENB0;                                /*  INTENB0         */
+    volatile uint16_t INTENB1;                                /*  INTENB1         */
+    volatile uint8_t   dummy5[2];                              /*                  */
+    volatile uint16_t BRDYENB;                                /*  BRDYENB         */
+    volatile uint16_t NRDYENB;                                /*  NRDYENB         */
+    volatile uint16_t BEMPENB;                                /*  BEMPENB         */
+    volatile uint16_t SOFCFG;                                 /*  SOFCFG          */
+    volatile uint8_t   dummy6[2];                              /*                  */
+#define USB20_INTSTS0_COUNT 2
+    volatile uint16_t INTSTS0;                                /*  INTSTS0         */
+    volatile uint16_t INTSTS1;                                /*  INTSTS1         */
+    volatile uint8_t   dummy7[2];                              /*                  */
+    volatile uint16_t BRDYSTS;                                /*  BRDYSTS         */
+    volatile uint16_t NRDYSTS;                                /*  NRDYSTS         */
+    volatile uint16_t BEMPSTS;                                /*  BEMPSTS         */
+    volatile uint16_t FRMNUM;                                 /*  FRMNUM          */
+    volatile uint16_t UFRMNUM;                                /*  UFRMNUM         */
+    volatile uint16_t USBADDR;                                /*  USBADDR         */
+    volatile uint8_t   dummy8[2];                              /*                  */
+    volatile uint16_t USBREQ;                                 /*  USBREQ          */
+    volatile uint16_t USBVAL;                                 /*  USBVAL          */
+    volatile uint16_t USBINDX;                                /*  USBINDX         */
+    volatile uint16_t USBLENG;                                /*  USBLENG         */
+    volatile uint16_t DCPCFG;                                 /*  DCPCFG          */
+    volatile uint16_t DCPMAXP;                                /*  DCPMAXP         */
+    volatile uint16_t DCPCTR;                                 /*  DCPCTR          */
+    volatile uint8_t   dummy9[2];                              /*                  */
+    volatile uint16_t PIPESEL;                                /*  PIPESEL         */
+    volatile uint8_t   dummy10[2];                             /*                  */
+    volatile uint16_t PIPECFG;                                /*  PIPECFG         */
+    volatile uint16_t PIPEBUF;                                /*  PIPEBUF         */
+    volatile uint16_t PIPEMAXP;                               /*  PIPEMAXP        */
+    volatile uint16_t PIPEPERI;                               /*  PIPEPERI        */
+#define USB20_PIPE1CTR_COUNT 0xF
+    volatile uint16_t PIPE1CTR;                               /*  PIPE1CTR        */
+    volatile uint16_t PIPE2CTR;                               /*  PIPE2CTR        */
+    volatile uint16_t PIPE3CTR;                               /*  PIPE3CTR        */
+    volatile uint16_t PIPE4CTR;                               /*  PIPE4CTR        */
+    volatile uint16_t PIPE5CTR;                               /*  PIPE5CTR        */
+    volatile uint16_t PIPE6CTR;                               /*  PIPE6CTR        */
+    volatile uint16_t PIPE7CTR;                               /*  PIPE7CTR        */
+    volatile uint16_t PIPE8CTR;                               /*  PIPE8CTR        */
+    volatile uint16_t PIPE9CTR;                               /*  PIPE9CTR        */
+    volatile uint16_t PIPEACTR;                               /*  PIPEACTR        */
+    volatile uint16_t PIPEBCTR;                               /*  PIPEBCTR        */
+    volatile uint16_t PIPECCTR;                               /*  PIPECCTR        */
+    volatile uint16_t PIPEDCTR;                               /*  PIPEDCTR        */
+    volatile uint16_t PIPEECTR;                               /*  PIPEECTR        */
+    volatile uint16_t PIPEFCTR;                               /*  PIPEFCTR        */
+    volatile uint8_t   dummy11[2];                             /*                  */
+/* start of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPE1TRE;                               /*  PIPE1TRE        */
+    volatile uint16_t PIPE1TRN;                               /*  PIPE1TRN        */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPE2TRE;                               /*  PIPE2TRE        */
+    volatile uint16_t PIPE2TRN;                               /*  PIPE2TRN        */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPE3TRE;                               /*  PIPE3TRE        */
+    volatile uint16_t PIPE3TRN;                               /*  PIPE3TRN        */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPE4TRE;                               /*  PIPE4TRE        */
+    volatile uint16_t PIPE4TRN;                               /*  PIPE4TRN        */
+/* end of struct st_usb20_from_pipe1tre */
+/* start of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPE5TRE;                               /*  PIPE5TRE        */
+    volatile uint16_t PIPE5TRN;                               /*  PIPE5TRN        */
+/* end of struct st_usb20_from_pipe1tre */
+    volatile uint16_t PIPEBTRE;                               /*  PIPEBTRE        */
+    volatile uint16_t PIPEBTRN;                               /*  PIPEBTRN        */
+    volatile uint16_t PIPECTRE;                               /*  PIPECTRE        */
+    volatile uint16_t PIPECTRN;                               /*  PIPECTRN        */
+    volatile uint16_t PIPEDTRE;                               /*  PIPEDTRE        */
+    volatile uint16_t PIPEDTRN;                               /*  PIPEDTRN        */
+    volatile uint16_t PIPEETRE;                               /*  PIPEETRE        */
+    volatile uint16_t PIPEETRN;                               /*  PIPEETRN        */
+    volatile uint16_t PIPEFTRE;                               /*  PIPEFTRE        */
+    volatile uint16_t PIPEFTRN;                               /*  PIPEFTRN        */
+    volatile uint16_t PIPE9TRE;                               /*  PIPE9TRE        */
+    volatile uint16_t PIPE9TRN;                               /*  PIPE9TRN        */
+    volatile uint16_t PIPEATRE;                               /*  PIPEATRE        */
+    volatile uint16_t PIPEATRN;                               /*  PIPEATRN        */
+    volatile uint8_t   dummy12[16];                            /*                  */
+#define USB20_DEVADD0_COUNT 0xB
+    volatile uint16_t DEVADD0;                                /*  DEVADD0         */
+    volatile uint16_t DEVADD1;                                /*  DEVADD1         */
+    volatile uint16_t DEVADD2;                                /*  DEVADD2         */
+    volatile uint16_t DEVADD3;                                /*  DEVADD3         */
+    volatile uint16_t DEVADD4;                                /*  DEVADD4         */
+    volatile uint16_t DEVADD5;                                /*  DEVADD5         */
+    volatile uint16_t DEVADD6;                                /*  DEVADD6         */
+    volatile uint16_t DEVADD7;                                /*  DEVADD7         */
+    volatile uint16_t DEVADD8;                                /*  DEVADD8         */
+    volatile uint16_t DEVADD9;                                /*  DEVADD9         */
+    volatile uint16_t DEVADDA;                                /*  DEVADDA         */
+    volatile uint8_t   dummy13[28];                            /*                  */
+    volatile uint16_t SUSPMODE;                               /*  SUSPMODE        */
+    volatile uint8_t   dummy14[92];                            /*                  */
+/* start of struct st_usb20_from_dmfifob0 */
+    volatile uint32_t  D0FIFOB0;                               /*  D0FIFOB0        */
+    volatile uint32_t  D0FIFOB1;                               /*  D0FIFOB1        */
+    volatile uint32_t  D0FIFOB2;                               /*  D0FIFOB2        */
+    volatile uint32_t  D0FIFOB3;                               /*  D0FIFOB3        */
+    volatile uint32_t  D0FIFOB4;                               /*  D0FIFOB4        */
+    volatile uint32_t  D0FIFOB5;                               /*  D0FIFOB5        */
+    volatile uint32_t  D0FIFOB6;                               /*  D0FIFOB6        */
+    volatile uint32_t  D0FIFOB7;                               /*  D0FIFOB7        */
+/* end of struct st_usb20_from_dmfifob0 */
+/* start of struct st_usb20_from_dmfifob0 */
+    volatile uint32_t  D1FIFOB0;                               /*  D1FIFOB0        */
+    volatile uint32_t  D1FIFOB1;                               /*  D1FIFOB1        */
+    volatile uint32_t  D1FIFOB2;                               /*  D1FIFOB2        */
+    volatile uint32_t  D1FIFOB3;                               /*  D1FIFOB3        */
+    volatile uint32_t  D1FIFOB4;                               /*  D1FIFOB4        */
+    volatile uint32_t  D1FIFOB5;                               /*  D1FIFOB5        */
+    volatile uint32_t  D1FIFOB6;                               /*  D1FIFOB6        */
+    volatile uint32_t  D1FIFOB7;                               /*  D1FIFOB7        */
+/* end of struct st_usb20_from_dmfifob0 */
+};
+
+
+struct st_usb20_from_d0fifosel
+{
+    volatile uint16_t D0FIFOSEL;                              /*  D0FIFOSEL       */
+    volatile uint16_t D0FIFOCTR;                              /*  D0FIFOCTR       */
+};
+
+
+struct st_usb20_from_pipe1tre
+{
+    volatile uint16_t PIPE1TRE;                               /*  PIPE1TRE        */
+    volatile uint16_t PIPE1TRN;                               /*  PIPE1TRN        */
+};
+
+
+struct st_usb20_from_dmfifob0
+{
+#define USB20_D0FIFOB0_COUNT 0x8
+    volatile uint32_t  D0FIFOB0;                               /*  D0FIFOB0        */
+    volatile uint32_t  D0FIFOB1;                               /*  D0FIFOB1        */
+    volatile uint32_t  D0FIFOB2;                               /*  D0FIFOB2        */
+    volatile uint32_t  D0FIFOB3;                               /*  D0FIFOB3        */
+    volatile uint32_t  D0FIFOB4;                               /*  D0FIFOB4        */
+    volatile uint32_t  D0FIFOB5;                               /*  D0FIFOB5        */
+    volatile uint32_t  D0FIFOB6;                               /*  D0FIFOB6        */
+    volatile uint32_t  D0FIFOB7;                               /*  D0FIFOB7        */
+};
+
+
+#define USB200  (*(struct st_usb20   *)0xE8010000uL) /* USB200 */
+#define USB201  (*(struct st_usb20   *)0xE8207000uL) /* USB201 */
+
+
+/* Start of channnel array defines of USB20 */
+
+/* Channnel array defines of USB20 */
+/*(Sample) value = USB20[ channel ]->SYSCFG0; */
+#define USB20_COUNT  2
+#define USB20_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &USB200, &USB201 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channnel array defines of USB20_FROM_D0FIFOB0 */
+/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
+#define USB20_FROM_D0FIFOB0_COUNT  2
+#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
+    &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
+#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
+#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
+#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
+
+
+
+
+/* Channnel array defines of USB20_FROM_PIPE1ATRE */
+/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
+#define USB20_FROM_PIPE1ATRE_COUNT  5
+#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
+    &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
+#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
+#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
+#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
+#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
+#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
+#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
+#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
+#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
+#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
+
+
+
+
+/* Channnel array defines of USB20_FROM_D0FIFOSEL */
+/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
+#define USB20_FROM_D0FIFOSEL_COUNT  2
+#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
+    &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
+#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
+#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
+#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
+
+
+/* End of channnel array defines of USB20 */
+
+
+#define SYSCFG0_0 USB200.SYSCFG0
+#define BUSWAIT_0 USB200.BUSWAIT
+#define SYSSTS0_0 USB200.SYSSTS0
+#define DVSTCTR0_0 USB200.DVSTCTR0
+#define TESTMODE_0 USB200.TESTMODE
+#define D0FBCFG_0 USB200.D0FBCFG
+#define D1FBCFG_0 USB200.D1FBCFG
+#define CFIFO_0   USB200.CFIFO.UINT32
+#define CFIFO_0L  USB200.CFIFO.UINT16[L]
+#define CFIFO_0H  USB200.CFIFO.UINT16[H]
+#define CFIFO_0LL USB200.CFIFO.UINT8[LL]
+#define CFIFO_0LH USB200.CFIFO.UINT8[LH]
+#define CFIFO_0HL USB200.CFIFO.UINT8[HL]
+#define CFIFO_0HH USB200.CFIFO.UINT8[HH]
+#define D0FIFO_0   USB200.D0FIFO.UINT32
+#define D0FIFO_0L  USB200.D0FIFO.UINT16[L]
+#define D0FIFO_0H  USB200.D0FIFO.UINT16[H]
+#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL]
+#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH]
+#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL]
+#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH]
+#define D1FIFO_0   USB200.D1FIFO.UINT32
+#define D1FIFO_0L  USB200.D1FIFO.UINT16[L]
+#define D1FIFO_0H  USB200.D1FIFO.UINT16[H]
+#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL]
+#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH]
+#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL]
+#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH]
+#define CFIFOSEL_0 USB200.CFIFOSEL
+#define CFIFOCTR_0 USB200.CFIFOCTR
+#define D0FIFOSEL_0 USB200.D0FIFOSEL
+#define D0FIFOCTR_0 USB200.D0FIFOCTR
+#define D1FIFOSEL_0 USB200.D1FIFOSEL
+#define D1FIFOCTR_0 USB200.D1FIFOCTR
+#define INTENB0_0 USB200.INTENB0
+#define INTENB1_0 USB200.INTENB1
+#define BRDYENB_0 USB200.BRDYENB
+#define NRDYENB_0 USB200.NRDYENB
+#define BEMPENB_0 USB200.BEMPENB
+#define SOFCFG_0 USB200.SOFCFG
+#define INTSTS0_0 USB200.INTSTS0
+#define INTSTS1_0 USB200.INTSTS1
+#define BRDYSTS_0 USB200.BRDYSTS
+#define NRDYSTS_0 USB200.NRDYSTS
+#define BEMPSTS_0 USB200.BEMPSTS
+#define FRMNUM_0 USB200.FRMNUM
+#define UFRMNUM_0 USB200.UFRMNUM
+#define USBADDR_0 USB200.USBADDR
+#define USBREQ_0 USB200.USBREQ
+#define USBVAL_0 USB200.USBVAL
+#define USBINDX_0 USB200.USBINDX
+#define USBLENG_0 USB200.USBLENG
+#define DCPCFG_0 USB200.DCPCFG
+#define DCPMAXP_0 USB200.DCPMAXP
+#define DCPCTR_0 USB200.DCPCTR
+#define PIPESEL_0 USB200.PIPESEL
+#define PIPECFG_0 USB200.PIPECFG
+#define PIPEBUF_0 USB200.PIPEBUF
+#define PIPEMAXP_0 USB200.PIPEMAXP
+#define PIPEPERI_0 USB200.PIPEPERI
+#define PIPE1CTR_0 USB200.PIPE1CTR
+#define PIPE2CTR_0 USB200.PIPE2CTR
+#define PIPE3CTR_0 USB200.PIPE3CTR
+#define PIPE4CTR_0 USB200.PIPE4CTR
+#define PIPE5CTR_0 USB200.PIPE5CTR
+#define PIPE6CTR_0 USB200.PIPE6CTR
+#define PIPE7CTR_0 USB200.PIPE7CTR
+#define PIPE8CTR_0 USB200.PIPE8CTR
+#define PIPE9CTR_0 USB200.PIPE9CTR
+#define PIPEACTR_0 USB200.PIPEACTR
+#define PIPEBCTR_0 USB200.PIPEBCTR
+#define PIPECCTR_0 USB200.PIPECCTR
+#define PIPEDCTR_0 USB200.PIPEDCTR
+#define PIPEECTR_0 USB200.PIPEECTR
+#define PIPEFCTR_0 USB200.PIPEFCTR
+#define PIPE1TRE_0 USB200.PIPE1TRE
+#define PIPE1TRN_0 USB200.PIPE1TRN
+#define PIPE2TRE_0 USB200.PIPE2TRE
+#define PIPE2TRN_0 USB200.PIPE2TRN
+#define PIPE3TRE_0 USB200.PIPE3TRE
+#define PIPE3TRN_0 USB200.PIPE3TRN
+#define PIPE4TRE_0 USB200.PIPE4TRE
+#define PIPE4TRN_0 USB200.PIPE4TRN
+#define PIPE5TRE_0 USB200.PIPE5TRE
+#define PIPE5TRN_0 USB200.PIPE5TRN
+#define PIPEBTRE_0 USB200.PIPEBTRE
+#define PIPEBTRN_0 USB200.PIPEBTRN
+#define PIPECTRE_0 USB200.PIPECTRE
+#define PIPECTRN_0 USB200.PIPECTRN
+#define PIPEDTRE_0 USB200.PIPEDTRE
+#define PIPEDTRN_0 USB200.PIPEDTRN
+#define PIPEETRE_0 USB200.PIPEETRE
+#define PIPEETRN_0 USB200.PIPEETRN
+#define PIPEFTRE_0 USB200.PIPEFTRE
+#define PIPEFTRN_0 USB200.PIPEFTRN
+#define PIPE9TRE_0 USB200.PIPE9TRE
+#define PIPE9TRN_0 USB200.PIPE9TRN
+#define PIPEATRE_0 USB200.PIPEATRE
+#define PIPEATRN_0 USB200.PIPEATRN
+#define DEVADD0_0 USB200.DEVADD0
+#define DEVADD1_0 USB200.DEVADD1
+#define DEVADD2_0 USB200.DEVADD2
+#define DEVADD3_0 USB200.DEVADD3
+#define DEVADD4_0 USB200.DEVADD4
+#define DEVADD5_0 USB200.DEVADD5
+#define DEVADD6_0 USB200.DEVADD6
+#define DEVADD7_0 USB200.DEVADD7
+#define DEVADD8_0 USB200.DEVADD8
+#define DEVADD9_0 USB200.DEVADD9
+#define DEVADDA_0 USB200.DEVADDA
+#define SUSPMODE_0 USB200.SUSPMODE
+#define D0FIFOB0_0 USB200.D0FIFOB0
+#define D0FIFOB1_0 USB200.D0FIFOB1
+#define D0FIFOB2_0 USB200.D0FIFOB2
+#define D0FIFOB3_0 USB200.D0FIFOB3
+#define D0FIFOB4_0 USB200.D0FIFOB4
+#define D0FIFOB5_0 USB200.D0FIFOB5
+#define D0FIFOB6_0 USB200.D0FIFOB6
+#define D0FIFOB7_0 USB200.D0FIFOB7
+#define D1FIFOB0_0 USB200.D1FIFOB0
+#define D1FIFOB1_0 USB200.D1FIFOB1
+#define D1FIFOB2_0 USB200.D1FIFOB2
+#define D1FIFOB3_0 USB200.D1FIFOB3
+#define D1FIFOB4_0 USB200.D1FIFOB4
+#define D1FIFOB5_0 USB200.D1FIFOB5
+#define D1FIFOB6_0 USB200.D1FIFOB6
+#define D1FIFOB7_0 USB200.D1FIFOB7
+#define SYSCFG0_1 USB201.SYSCFG0
+#define BUSWAIT_1 USB201.BUSWAIT
+#define SYSSTS0_1 USB201.SYSSTS0
+#define DVSTCTR0_1 USB201.DVSTCTR0
+#define TESTMODE_1 USB201.TESTMODE
+#define D0FBCFG_1 USB201.D0FBCFG
+#define D1FBCFG_1 USB201.D1FBCFG
+#define CFIFO_1   USB201.CFIFO.UINT32
+#define CFIFO_1L  USB201.CFIFO.UINT16[L]
+#define CFIFO_1H  USB201.CFIFO.UINT16[H]
+#define CFIFO_1LL USB201.CFIFO.UINT8[LL]
+#define CFIFO_1LH USB201.CFIFO.UINT8[LH]
+#define CFIFO_1HL USB201.CFIFO.UINT8[HL]
+#define CFIFO_1HH USB201.CFIFO.UINT8[HH]
+#define D0FIFO_1   USB201.D0FIFO.UINT32
+#define D0FIFO_1L  USB201.D0FIFO.UINT16[L]
+#define D0FIFO_1H  USB201.D0FIFO.UINT16[H]
+#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL]
+#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH]
+#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL]
+#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH]
+#define D1FIFO_1   USB201.D1FIFO.UINT32
+#define D1FIFO_1L  USB201.D1FIFO.UINT16[L]
+#define D1FIFO_1H  USB201.D1FIFO.UINT16[H]
+#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL]
+#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH]
+#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL]
+#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH]
+#define CFIFOSEL_1 USB201.CFIFOSEL
+#define CFIFOCTR_1 USB201.CFIFOCTR
+#define D0FIFOSEL_1 USB201.D0FIFOSEL
+#define D0FIFOCTR_1 USB201.D0FIFOCTR
+#define D1FIFOSEL_1 USB201.D1FIFOSEL
+#define D1FIFOCTR_1 USB201.D1FIFOCTR
+#define INTENB0_1 USB201.INTENB0
+#define INTENB1_1 USB201.INTENB1
+#define BRDYENB_1 USB201.BRDYENB
+#define NRDYENB_1 USB201.NRDYENB
+#define BEMPENB_1 USB201.BEMPENB
+#define SOFCFG_1 USB201.SOFCFG
+#define INTSTS0_1 USB201.INTSTS0
+#define INTSTS1_1 USB201.INTSTS1
+#define BRDYSTS_1 USB201.BRDYSTS
+#define NRDYSTS_1 USB201.NRDYSTS
+#define BEMPSTS_1 USB201.BEMPSTS
+#define FRMNUM_1 USB201.FRMNUM
+#define UFRMNUM_1 USB201.UFRMNUM
+#define USBADDR_1 USB201.USBADDR
+#define USBREQ_1 USB201.USBREQ
+#define USBVAL_1 USB201.USBVAL
+#define USBINDX_1 USB201.USBINDX
+#define USBLENG_1 USB201.USBLENG
+#define DCPCFG_1 USB201.DCPCFG
+#define DCPMAXP_1 USB201.DCPMAXP
+#define DCPCTR_1 USB201.DCPCTR
+#define PIPESEL_1 USB201.PIPESEL
+#define PIPECFG_1 USB201.PIPECFG
+#define PIPEBUF_1 USB201.PIPEBUF
+#define PIPEMAXP_1 USB201.PIPEMAXP
+#define PIPEPERI_1 USB201.PIPEPERI
+#define PIPE1CTR_1 USB201.PIPE1CTR
+#define PIPE2CTR_1 USB201.PIPE2CTR
+#define PIPE3CTR_1 USB201.PIPE3CTR
+#define PIPE4CTR_1 USB201.PIPE4CTR
+#define PIPE5CTR_1 USB201.PIPE5CTR
+#define PIPE6CTR_1 USB201.PIPE6CTR
+#define PIPE7CTR_1 USB201.PIPE7CTR
+#define PIPE8CTR_1 USB201.PIPE8CTR
+#define PIPE9CTR_1 USB201.PIPE9CTR
+#define PIPEACTR_1 USB201.PIPEACTR
+#define PIPEBCTR_1 USB201.PIPEBCTR
+#define PIPECCTR_1 USB201.PIPECCTR
+#define PIPEDCTR_1 USB201.PIPEDCTR
+#define PIPEECTR_1 USB201.PIPEECTR
+#define PIPEFCTR_1 USB201.PIPEFCTR
+#define PIPE1TRE_1 USB201.PIPE1TRE
+#define PIPE1TRN_1 USB201.PIPE1TRN
+#define PIPE2TRE_1 USB201.PIPE2TRE
+#define PIPE2TRN_1 USB201.PIPE2TRN
+#define PIPE3TRE_1 USB201.PIPE3TRE
+#define PIPE3TRN_1 USB201.PIPE3TRN
+#define PIPE4TRE_1 USB201.PIPE4TRE
+#define PIPE4TRN_1 USB201.PIPE4TRN
+#define PIPE5TRE_1 USB201.PIPE5TRE
+#define PIPE5TRN_1 USB201.PIPE5TRN
+#define PIPEBTRE_1 USB201.PIPEBTRE
+#define PIPEBTRN_1 USB201.PIPEBTRN
+#define PIPECTRE_1 USB201.PIPECTRE
+#define PIPECTRN_1 USB201.PIPECTRN
+#define PIPEDTRE_1 USB201.PIPEDTRE
+#define PIPEDTRN_1 USB201.PIPEDTRN
+#define PIPEETRE_1 USB201.PIPEETRE
+#define PIPEETRN_1 USB201.PIPEETRN
+#define PIPEFTRE_1 USB201.PIPEFTRE
+#define PIPEFTRN_1 USB201.PIPEFTRN
+#define PIPE9TRE_1 USB201.PIPE9TRE
+#define PIPE9TRN_1 USB201.PIPE9TRN
+#define PIPEATRE_1 USB201.PIPEATRE
+#define PIPEATRN_1 USB201.PIPEATRN
+#define DEVADD0_1 USB201.DEVADD0
+#define DEVADD1_1 USB201.DEVADD1
+#define DEVADD2_1 USB201.DEVADD2
+#define DEVADD3_1 USB201.DEVADD3
+#define DEVADD4_1 USB201.DEVADD4
+#define DEVADD5_1 USB201.DEVADD5
+#define DEVADD6_1 USB201.DEVADD6
+#define DEVADD7_1 USB201.DEVADD7
+#define DEVADD8_1 USB201.DEVADD8
+#define DEVADD9_1 USB201.DEVADD9
+#define DEVADDA_1 USB201.DEVADDA
+#define SUSPMODE_1 USB201.SUSPMODE
+#define D0FIFOB0_1 USB201.D0FIFOB0
+#define D0FIFOB1_1 USB201.D0FIFOB1
+#define D0FIFOB2_1 USB201.D0FIFOB2
+#define D0FIFOB3_1 USB201.D0FIFOB3
+#define D0FIFOB4_1 USB201.D0FIFOB4
+#define D0FIFOB5_1 USB201.D0FIFOB5
+#define D0FIFOB6_1 USB201.D0FIFOB6
+#define D0FIFOB7_1 USB201.D0FIFOB7
+#define D1FIFOB0_1 USB201.D1FIFOB0
+#define D1FIFOB1_1 USB201.D1FIFOB1
+#define D1FIFOB2_1 USB201.D1FIFOB2
+#define D1FIFOB3_1 USB201.D1FIFOB3
+#define D1FIFOB4_1 USB201.D1FIFOB4
+#define D1FIFOB5_1 USB201.D1FIFOB5
+#define D1FIFOB6_1 USB201.D1FIFOB6
+#define D1FIFOB7_1 USB201.D1FIFOB7
+/* <-SEC M1.10.1 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/vdc5_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1597 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : vdc5_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef VDC5_IODEFINE_H
+#define VDC5_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->SEC M1.10.1 : Not magic number */
+
+struct st_vdc5
+{                                                          /* VDC5             */
+    volatile uint32_t  INP_UPDATE;                             /*  INP_UPDATE      */
+    volatile uint32_t  INP_SEL_CNT;                            /*  INP_SEL_CNT     */
+    volatile uint32_t  INP_EXT_SYNC_CNT;                       /*  INP_EXT_SYNC_CNT */
+    volatile uint32_t  INP_VSYNC_PH_ADJ;                       /*  INP_VSYNC_PH_ADJ */
+    volatile uint32_t  INP_DLY_ADJ;                            /*  INP_DLY_ADJ     */
+    volatile uint8_t   dummy1[108];                            /*                  */
+    volatile uint32_t  IMGCNT_UPDATE;                          /*  IMGCNT_UPDATE   */
+#define VDC5_IMGCNT_NR_CNT0_COUNT 2
+    volatile uint32_t  IMGCNT_NR_CNT0;                         /*  IMGCNT_NR_CNT0  */
+    volatile uint32_t  IMGCNT_NR_CNT1;                         /*  IMGCNT_NR_CNT1  */
+    volatile uint8_t   dummy2[20];                             /*                  */
+    volatile uint32_t  IMGCNT_MTX_MODE;                        /*  IMGCNT_MTX_MODE */
+    volatile uint32_t  IMGCNT_MTX_YG_ADJ0;                     /*  IMGCNT_MTX_YG_ADJ0 */
+    volatile uint32_t  IMGCNT_MTX_YG_ADJ1;                     /*  IMGCNT_MTX_YG_ADJ1 */
+    volatile uint32_t  IMGCNT_MTX_CBB_ADJ0;                    /*  IMGCNT_MTX_CBB_ADJ0 */
+    volatile uint32_t  IMGCNT_MTX_CBB_ADJ1;                    /*  IMGCNT_MTX_CBB_ADJ1 */
+    volatile uint32_t  IMGCNT_MTX_CRR_ADJ0;                    /*  IMGCNT_MTX_CRR_ADJ0 */
+    volatile uint32_t  IMGCNT_MTX_CRR_ADJ1;                    /*  IMGCNT_MTX_CRR_ADJ1 */
+    volatile uint8_t   dummy3[4];                              /*                  */
+    volatile uint32_t  IMGCNT_DRC_REG;                         /*  IMGCNT_DRC_REG  */
+    volatile uint8_t   dummy4[60];                             /*                  */
+/* start of struct st_vdc5_from_sc0_scl0_update */
+    volatile uint32_t  SC0_SCL0_UPDATE;                        /*  SC0_SCL0_UPDATE */
+#define VDC5_SC0_SCL0_FRC1_COUNT 7
+    volatile uint32_t  SC0_SCL0_FRC1;                          /*  SC0_SCL0_FRC1   */
+    volatile uint32_t  SC0_SCL0_FRC2;                          /*  SC0_SCL0_FRC2   */
+    volatile uint32_t  SC0_SCL0_FRC3;                          /*  SC0_SCL0_FRC3   */
+    volatile uint32_t  SC0_SCL0_FRC4;                          /*  SC0_SCL0_FRC4   */
+    volatile uint32_t  SC0_SCL0_FRC5;                          /*  SC0_SCL0_FRC5   */
+    volatile uint32_t  SC0_SCL0_FRC6;                          /*  SC0_SCL0_FRC6   */
+    volatile uint32_t  SC0_SCL0_FRC7;                          /*  SC0_SCL0_FRC7   */
+    volatile uint8_t   dummy5[4];                              /*                  */
+    volatile uint32_t  SC0_SCL0_FRC9;                          /*  SC0_SCL0_FRC9   */
+    volatile uint16_t SC0_SCL0_MON0;                          /*  SC0_SCL0_MON0   */
+    volatile uint16_t SC0_SCL0_INT;                           /*  SC0_SCL0_INT    */
+#define VDC5_SC0_SCL0_DS1_COUNT 7
+    volatile uint32_t  SC0_SCL0_DS1;                           /*  SC0_SCL0_DS1    */
+    volatile uint32_t  SC0_SCL0_DS2;                           /*  SC0_SCL0_DS2    */
+    volatile uint32_t  SC0_SCL0_DS3;                           /*  SC0_SCL0_DS3    */
+    volatile uint32_t  SC0_SCL0_DS4;                           /*  SC0_SCL0_DS4    */
+    volatile uint32_t  SC0_SCL0_DS5;                           /*  SC0_SCL0_DS5    */
+    volatile uint32_t  SC0_SCL0_DS6;                           /*  SC0_SCL0_DS6    */
+    volatile uint32_t  SC0_SCL0_DS7;                           /*  SC0_SCL0_DS7    */
+#define VDC5_SC0_SCL0_US1_COUNT 8
+    volatile uint32_t  SC0_SCL0_US1;                           /*  SC0_SCL0_US1    */
+    volatile uint32_t  SC0_SCL0_US2;                           /*  SC0_SCL0_US2    */
+    volatile uint32_t  SC0_SCL0_US3;                           /*  SC0_SCL0_US3    */
+    volatile uint32_t  SC0_SCL0_US4;                           /*  SC0_SCL0_US4    */
+    volatile uint32_t  SC0_SCL0_US5;                           /*  SC0_SCL0_US5    */
+    volatile uint32_t  SC0_SCL0_US6;                           /*  SC0_SCL0_US6    */
+    volatile uint32_t  SC0_SCL0_US7;                           /*  SC0_SCL0_US7    */
+    volatile uint32_t  SC0_SCL0_US8;                           /*  SC0_SCL0_US8    */
+    volatile uint8_t   dummy6[4];                              /*                  */
+    volatile uint32_t  SC0_SCL0_OVR1;                          /*  SC0_SCL0_OVR1   */
+    volatile uint8_t   dummy7[16];                             /*                  */
+    volatile uint32_t  SC0_SCL1_UPDATE;                        /*  SC0_SCL1_UPDATE */
+    volatile uint8_t   dummy8[4];                              /*                  */
+#define VDC5_SC0_SCL1_WR1_COUNT 4
+    volatile uint32_t  SC0_SCL1_WR1;                           /*  SC0_SCL1_WR1    */
+    volatile uint32_t  SC0_SCL1_WR2;                           /*  SC0_SCL1_WR2    */
+    volatile uint32_t  SC0_SCL1_WR3;                           /*  SC0_SCL1_WR3    */
+    volatile uint32_t  SC0_SCL1_WR4;                           /*  SC0_SCL1_WR4    */
+    volatile uint8_t   dummy9[4];                              /*                  */
+    volatile uint32_t  SC0_SCL1_WR5;                           /*  SC0_SCL1_WR5    */
+    volatile uint32_t  SC0_SCL1_WR6;                           /*  SC0_SCL1_WR6    */
+    volatile uint32_t  SC0_SCL1_WR7;                           /*  SC0_SCL1_WR7    */
+    volatile uint32_t  SC0_SCL1_WR8;                           /*  SC0_SCL1_WR8    */
+    volatile uint32_t  SC0_SCL1_WR9;                           /*  SC0_SCL1_WR9    */
+    volatile uint32_t  SC0_SCL1_WR10;                          /*  SC0_SCL1_WR10   */
+/* end of struct st_vdc5_from_sc0_scl0_update */
+    volatile uint32_t  SC0_SCL1_WR11;                          /*  SC0_SCL1_WR11   */
+    volatile uint32_t  SC0_SCL1_MON1;                          /*  SC0_SCL1_MON1   */
+/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
+#define VDC5_SC0_SCL1_PBUF0_COUNT 4
+    volatile uint32_t  SC0_SCL1_PBUF0;                         /*  SC0_SCL1_PBUF0  */
+    volatile uint32_t  SC0_SCL1_PBUF1;                         /*  SC0_SCL1_PBUF1  */
+    volatile uint32_t  SC0_SCL1_PBUF2;                         /*  SC0_SCL1_PBUF2  */
+    volatile uint32_t  SC0_SCL1_PBUF3;                         /*  SC0_SCL1_PBUF3  */
+    volatile uint32_t  SC0_SCL1_PBUF_FLD;                      /*  SC0_SCL1_PBUF_FLD */
+    volatile uint32_t  SC0_SCL1_PBUF_CNT;                      /*  SC0_SCL1_PBUF_CNT */
+/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
+    volatile uint8_t   dummy10[44];                            /*                  */
+/* start of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR0_UPDATE;                             /*  GR0_UPDATE      */
+    volatile uint32_t  GR0_FLM_RD;                             /*  GR0_FLM_RD      */
+#define VDC5_GR0_FLM1_COUNT 6
+    volatile uint32_t  GR0_FLM1;                               /*  GR0_FLM1        */
+    volatile uint32_t  GR0_FLM2;                               /*  GR0_FLM2        */
+    volatile uint32_t  GR0_FLM3;                               /*  GR0_FLM3        */
+    volatile uint32_t  GR0_FLM4;                               /*  GR0_FLM4        */
+    volatile uint32_t  GR0_FLM5;                               /*  GR0_FLM5        */
+    volatile uint32_t  GR0_FLM6;                               /*  GR0_FLM6        */
+#define VDC5_GR0_AB1_COUNT 3
+    volatile uint32_t  GR0_AB1;                                /*  GR0_AB1         */
+    volatile uint32_t  GR0_AB2;                                /*  GR0_AB2         */
+    volatile uint32_t  GR0_AB3;                                /*  GR0_AB3         */
+/* end of struct st_vdc5_from_gr0_update */
+    volatile uint8_t   dummy11[12];                            /*                  */
+/* start of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR0_AB7;                                /*  GR0_AB7         */
+    volatile uint32_t  GR0_AB8;                                /*  GR0_AB8         */
+    volatile uint32_t  GR0_AB9;                                /*  GR0_AB9         */
+    volatile uint32_t  GR0_AB10;                               /*  GR0_AB10        */
+    volatile uint32_t  GR0_AB11;                               /*  GR0_AB11        */
+    volatile uint32_t  GR0_BASE;                               /*  GR0_BASE        */
+/* end of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR0_CLUT;                               /*  GR0_CLUT        */
+    volatile uint8_t   dummy12[44];                            /*                  */
+/* start of struct st_vdc5_from_adj0_update */
+    volatile uint32_t  ADJ0_UPDATE;                            /*  ADJ0_UPDATE     */
+    volatile uint32_t  ADJ0_BKSTR_SET;                         /*  ADJ0_BKSTR_SET  */
+#define VDC5_ADJ0_ENH_TIM1_COUNT 3
+    volatile uint32_t  ADJ0_ENH_TIM1;                          /*  ADJ0_ENH_TIM1   */
+    volatile uint32_t  ADJ0_ENH_TIM2;                          /*  ADJ0_ENH_TIM2   */
+    volatile uint32_t  ADJ0_ENH_TIM3;                          /*  ADJ0_ENH_TIM3   */
+#define VDC5_ADJ0_ENH_SHP1_COUNT 6
+    volatile uint32_t  ADJ0_ENH_SHP1;                          /*  ADJ0_ENH_SHP1   */
+    volatile uint32_t  ADJ0_ENH_SHP2;                          /*  ADJ0_ENH_SHP2   */
+    volatile uint32_t  ADJ0_ENH_SHP3;                          /*  ADJ0_ENH_SHP3   */
+    volatile uint32_t  ADJ0_ENH_SHP4;                          /*  ADJ0_ENH_SHP4   */
+    volatile uint32_t  ADJ0_ENH_SHP5;                          /*  ADJ0_ENH_SHP5   */
+    volatile uint32_t  ADJ0_ENH_SHP6;                          /*  ADJ0_ENH_SHP6   */
+#define VDC5_ADJ0_ENH_LTI1_COUNT 2
+    volatile uint32_t  ADJ0_ENH_LTI1;                          /*  ADJ0_ENH_LTI1   */
+    volatile uint32_t  ADJ0_ENH_LTI2;                          /*  ADJ0_ENH_LTI2   */
+    volatile uint32_t  ADJ0_MTX_MODE;                          /*  ADJ0_MTX_MODE   */
+    volatile uint32_t  ADJ0_MTX_YG_ADJ0;                       /*  ADJ0_MTX_YG_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_YG_ADJ1;                       /*  ADJ0_MTX_YG_ADJ1 */
+    volatile uint32_t  ADJ0_MTX_CBB_ADJ0;                      /*  ADJ0_MTX_CBB_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_CBB_ADJ1;                      /*  ADJ0_MTX_CBB_ADJ1 */
+    volatile uint32_t  ADJ0_MTX_CRR_ADJ0;                      /*  ADJ0_MTX_CRR_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_CRR_ADJ1;                      /*  ADJ0_MTX_CRR_ADJ1 */
+/* end of struct st_vdc5_from_adj0_update */
+    volatile uint8_t   dummy13[48];                            /*                  */
+/* start of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR2_UPDATE;                             /*  GR2_UPDATE      */
+    volatile uint32_t  GR2_FLM_RD;                             /*  GR2_FLM_RD      */
+#define VDC5_GR2_FLM1_COUNT 6
+    volatile uint32_t  GR2_FLM1;                               /*  GR2_FLM1        */
+    volatile uint32_t  GR2_FLM2;                               /*  GR2_FLM2        */
+    volatile uint32_t  GR2_FLM3;                               /*  GR2_FLM3        */
+    volatile uint32_t  GR2_FLM4;                               /*  GR2_FLM4        */
+    volatile uint32_t  GR2_FLM5;                               /*  GR2_FLM5        */
+    volatile uint32_t  GR2_FLM6;                               /*  GR2_FLM6        */
+#define VDC5_GR2_AB1_COUNT 3
+    volatile uint32_t  GR2_AB1;                                /*  GR2_AB1         */
+    volatile uint32_t  GR2_AB2;                                /*  GR2_AB2         */
+    volatile uint32_t  GR2_AB3;                                /*  GR2_AB3         */
+/* end of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR2_AB4;                                /*  GR2_AB4         */
+    volatile uint32_t  GR2_AB5;                                /*  GR2_AB5         */
+    volatile uint32_t  GR2_AB6;                                /*  GR2_AB6         */
+/* start of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR2_AB7;                                /*  GR2_AB7         */
+    volatile uint32_t  GR2_AB8;                                /*  GR2_AB8         */
+    volatile uint32_t  GR2_AB9;                                /*  GR2_AB9         */
+    volatile uint32_t  GR2_AB10;                               /*  GR2_AB10        */
+    volatile uint32_t  GR2_AB11;                               /*  GR2_AB11        */
+    volatile uint32_t  GR2_BASE;                               /*  GR2_BASE        */
+/* end of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR2_CLUT;                               /*  GR2_CLUT        */
+    volatile uint32_t  GR2_MON;                                /*  GR2_MON         */
+    volatile uint8_t   dummy14[40];                            /*                  */
+/* start of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR3_UPDATE;                             /*  GR3_UPDATE      */
+    volatile uint32_t  GR3_FLM_RD;                             /*  GR3_FLM_RD      */
+#define VDC5_GR3_FLM1_COUNT 6
+    volatile uint32_t  GR3_FLM1;                               /*  GR3_FLM1        */
+    volatile uint32_t  GR3_FLM2;                               /*  GR3_FLM2        */
+    volatile uint32_t  GR3_FLM3;                               /*  GR3_FLM3        */
+    volatile uint32_t  GR3_FLM4;                               /*  GR3_FLM4        */
+    volatile uint32_t  GR3_FLM5;                               /*  GR3_FLM5        */
+    volatile uint32_t  GR3_FLM6;                               /*  GR3_FLM6        */
+#define VDC5_GR3_AB1_COUNT 3
+    volatile uint32_t  GR3_AB1;                                /*  GR3_AB1         */
+    volatile uint32_t  GR3_AB2;                                /*  GR3_AB2         */
+    volatile uint32_t  GR3_AB3;                                /*  GR3_AB3         */
+/* end of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR3_AB4;                                /*  GR3_AB4         */
+    volatile uint32_t  GR3_AB5;                                /*  GR3_AB5         */
+    volatile uint32_t  GR3_AB6;                                /*  GR3_AB6         */
+/* start of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR3_AB7;                                /*  GR3_AB7         */
+    volatile uint32_t  GR3_AB8;                                /*  GR3_AB8         */
+    volatile uint32_t  GR3_AB9;                                /*  GR3_AB9         */
+    volatile uint32_t  GR3_AB10;                               /*  GR3_AB10        */
+    volatile uint32_t  GR3_AB11;                               /*  GR3_AB11        */
+    volatile uint32_t  GR3_BASE;                               /*  GR3_BASE        */
+/* end of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR3_CLUT_INT;                           /*  GR3_CLUT_INT    */
+    volatile uint32_t  GR3_MON;                                /*  GR3_MON         */
+    volatile uint8_t   dummy15[40];                            /*                  */
+    volatile uint32_t  GAM_G_UPDATE;                           /*  GAM_G_UPDATE    */
+    volatile uint32_t  GAM_SW;                                 /*  GAM_SW          */
+#define VDC5_GAM_G_LUT1_COUNT 16
+    volatile uint32_t  GAM_G_LUT1;                             /*  GAM_G_LUT1      */
+    volatile uint32_t  GAM_G_LUT2;                             /*  GAM_G_LUT2      */
+    volatile uint32_t  GAM_G_LUT3;                             /*  GAM_G_LUT3      */
+    volatile uint32_t  GAM_G_LUT4;                             /*  GAM_G_LUT4      */
+    volatile uint32_t  GAM_G_LUT5;                             /*  GAM_G_LUT5      */
+    volatile uint32_t  GAM_G_LUT6;                             /*  GAM_G_LUT6      */
+    volatile uint32_t  GAM_G_LUT7;                             /*  GAM_G_LUT7      */
+    volatile uint32_t  GAM_G_LUT8;                             /*  GAM_G_LUT8      */
+    volatile uint32_t  GAM_G_LUT9;                             /*  GAM_G_LUT9      */
+    volatile uint32_t  GAM_G_LUT10;                            /*  GAM_G_LUT10     */
+    volatile uint32_t  GAM_G_LUT11;                            /*  GAM_G_LUT11     */
+    volatile uint32_t  GAM_G_LUT12;                            /*  GAM_G_LUT12     */
+    volatile uint32_t  GAM_G_LUT13;                            /*  GAM_G_LUT13     */
+    volatile uint32_t  GAM_G_LUT14;                            /*  GAM_G_LUT14     */
+    volatile uint32_t  GAM_G_LUT15;                            /*  GAM_G_LUT15     */
+    volatile uint32_t  GAM_G_LUT16;                            /*  GAM_G_LUT16     */
+#define VDC5_GAM_G_AREA1_COUNT 8
+    volatile uint32_t  GAM_G_AREA1;                            /*  GAM_G_AREA1     */
+    volatile uint32_t  GAM_G_AREA2;                            /*  GAM_G_AREA2     */
+    volatile uint32_t  GAM_G_AREA3;                            /*  GAM_G_AREA3     */
+    volatile uint32_t  GAM_G_AREA4;                            /*  GAM_G_AREA4     */
+    volatile uint32_t  GAM_G_AREA5;                            /*  GAM_G_AREA5     */
+    volatile uint32_t  GAM_G_AREA6;                            /*  GAM_G_AREA6     */
+    volatile uint32_t  GAM_G_AREA7;                            /*  GAM_G_AREA7     */
+    volatile uint32_t  GAM_G_AREA8;                            /*  GAM_G_AREA8     */
+    volatile uint8_t   dummy16[24];                            /*                  */
+    volatile uint32_t  GAM_B_UPDATE;                           /*  GAM_B_UPDATE    */
+    volatile uint8_t   dummy17[4];                             /*                  */
+#define VDC5_GAM_B_LUT1_COUNT 16
+    volatile uint32_t  GAM_B_LUT1;                             /*  GAM_B_LUT1      */
+    volatile uint32_t  GAM_B_LUT2;                             /*  GAM_B_LUT2      */
+    volatile uint32_t  GAM_B_LUT3;                             /*  GAM_B_LUT3      */
+    volatile uint32_t  GAM_B_LUT4;                             /*  GAM_B_LUT4      */
+    volatile uint32_t  GAM_B_LUT5;                             /*  GAM_B_LUT5      */
+    volatile uint32_t  GAM_B_LUT6;                             /*  GAM_B_LUT6      */
+    volatile uint32_t  GAM_B_LUT7;                             /*  GAM_B_LUT7      */
+    volatile uint32_t  GAM_B_LUT8;                             /*  GAM_B_LUT8      */
+    volatile uint32_t  GAM_B_LUT9;                             /*  GAM_B_LUT9      */
+    volatile uint32_t  GAM_B_LUT10;                            /*  GAM_B_LUT10     */
+    volatile uint32_t  GAM_B_LUT11;                            /*  GAM_B_LUT11     */
+    volatile uint32_t  GAM_B_LUT12;                            /*  GAM_B_LUT12     */
+    volatile uint32_t  GAM_B_LUT13;                            /*  GAM_B_LUT13     */
+    volatile uint32_t  GAM_B_LUT14;                            /*  GAM_B_LUT14     */
+    volatile uint32_t  GAM_B_LUT15;                            /*  GAM_B_LUT15     */
+    volatile uint32_t  GAM_B_LUT16;                            /*  GAM_B_LUT16     */
+#define VDC5_GAM_B_AREA1_COUNT 8
+    volatile uint32_t  GAM_B_AREA1;                            /*  GAM_B_AREA1     */
+    volatile uint32_t  GAM_B_AREA2;                            /*  GAM_B_AREA2     */
+    volatile uint32_t  GAM_B_AREA3;                            /*  GAM_B_AREA3     */
+    volatile uint32_t  GAM_B_AREA4;                            /*  GAM_B_AREA4     */
+    volatile uint32_t  GAM_B_AREA5;                            /*  GAM_B_AREA5     */
+    volatile uint32_t  GAM_B_AREA6;                            /*  GAM_B_AREA6     */
+    volatile uint32_t  GAM_B_AREA7;                            /*  GAM_B_AREA7     */
+    volatile uint32_t  GAM_B_AREA8;                            /*  GAM_B_AREA8     */
+    volatile uint8_t   dummy18[24];                            /*                  */
+    volatile uint32_t  GAM_R_UPDATE;                           /*  GAM_R_UPDATE    */
+    volatile uint8_t   dummy19[4];                             /*                  */
+#define VDC5_GAM_R_LUT1_COUNT 16
+    volatile uint32_t  GAM_R_LUT1;                             /*  GAM_R_LUT1      */
+    volatile uint32_t  GAM_R_LUT2;                             /*  GAM_R_LUT2      */
+    volatile uint32_t  GAM_R_LUT3;                             /*  GAM_R_LUT3      */
+    volatile uint32_t  GAM_R_LUT4;                             /*  GAM_R_LUT4      */
+    volatile uint32_t  GAM_R_LUT5;                             /*  GAM_R_LUT5      */
+    volatile uint32_t  GAM_R_LUT6;                             /*  GAM_R_LUT6      */
+    volatile uint32_t  GAM_R_LUT7;                             /*  GAM_R_LUT7      */
+    volatile uint32_t  GAM_R_LUT8;                             /*  GAM_R_LUT8      */
+    volatile uint32_t  GAM_R_LUT9;                             /*  GAM_R_LUT9      */
+    volatile uint32_t  GAM_R_LUT10;                            /*  GAM_R_LUT10     */
+    volatile uint32_t  GAM_R_LUT11;                            /*  GAM_R_LUT11     */
+    volatile uint32_t  GAM_R_LUT12;                            /*  GAM_R_LUT12     */
+    volatile uint32_t  GAM_R_LUT13;                            /*  GAM_R_LUT13     */
+    volatile uint32_t  GAM_R_LUT14;                            /*  GAM_R_LUT14     */
+    volatile uint32_t  GAM_R_LUT15;                            /*  GAM_R_LUT15     */
+    volatile uint32_t  GAM_R_LUT16;                            /*  GAM_R_LUT16     */
+#define VDC5_GAM_R_AREA1_COUNT 8
+    volatile uint32_t  GAM_R_AREA1;                            /*  GAM_R_AREA1     */
+    volatile uint32_t  GAM_R_AREA2;                            /*  GAM_R_AREA2     */
+    volatile uint32_t  GAM_R_AREA3;                            /*  GAM_R_AREA3     */
+    volatile uint32_t  GAM_R_AREA4;                            /*  GAM_R_AREA4     */
+    volatile uint32_t  GAM_R_AREA5;                            /*  GAM_R_AREA5     */
+    volatile uint32_t  GAM_R_AREA6;                            /*  GAM_R_AREA6     */
+    volatile uint32_t  GAM_R_AREA7;                            /*  GAM_R_AREA7     */
+    volatile uint32_t  GAM_R_AREA8;                            /*  GAM_R_AREA8     */
+    volatile uint8_t   dummy20[24];                            /*                  */
+    volatile uint32_t  TCON_UPDATE;                            /*  TCON_UPDATE     */
+    volatile uint32_t  TCON_TIM;                               /*  TCON_TIM        */
+#define VDC5_TCON_TIM_STVA1_COUNT 2
+    volatile uint32_t  TCON_TIM_STVA1;                         /*  TCON_TIM_STVA1  */
+    volatile uint32_t  TCON_TIM_STVA2;                         /*  TCON_TIM_STVA2  */
+#define VDC5_TCON_TIM_STVB1_COUNT 2
+    volatile uint32_t  TCON_TIM_STVB1;                         /*  TCON_TIM_STVB1  */
+    volatile uint32_t  TCON_TIM_STVB2;                         /*  TCON_TIM_STVB2  */
+#define VDC5_TCON_TIM_STH1_COUNT 2
+    volatile uint32_t  TCON_TIM_STH1;                          /*  TCON_TIM_STH1   */
+    volatile uint32_t  TCON_TIM_STH2;                          /*  TCON_TIM_STH2   */
+#define VDC5_TCON_TIM_STB1_COUNT 2
+    volatile uint32_t  TCON_TIM_STB1;                          /*  TCON_TIM_STB1   */
+    volatile uint32_t  TCON_TIM_STB2;                          /*  TCON_TIM_STB2   */
+#define VDC5_TCON_TIM_CPV1_COUNT 2
+    volatile uint32_t  TCON_TIM_CPV1;                          /*  TCON_TIM_CPV1   */
+    volatile uint32_t  TCON_TIM_CPV2;                          /*  TCON_TIM_CPV2   */
+#define VDC5_TCON_TIM_POLA1_COUNT 2
+    volatile uint32_t  TCON_TIM_POLA1;                         /*  TCON_TIM_POLA1  */
+    volatile uint32_t  TCON_TIM_POLA2;                         /*  TCON_TIM_POLA2  */
+#define VDC5_TCON_TIM_POLB1_COUNT 2
+    volatile uint32_t  TCON_TIM_POLB1;                         /*  TCON_TIM_POLB1  */
+    volatile uint32_t  TCON_TIM_POLB2;                         /*  TCON_TIM_POLB2  */
+    volatile uint32_t  TCON_TIM_DE;                            /*  TCON_TIM_DE     */
+    volatile uint8_t   dummy21[60];                            /*                  */
+    volatile uint32_t  OUT_UPDATE;                             /*  OUT_UPDATE      */
+    volatile uint32_t  OUT_SET;                                /*  OUT_SET         */
+#define VDC5_OUT_BRIGHT1_COUNT 2
+    volatile uint32_t  OUT_BRIGHT1;                            /*  OUT_BRIGHT1     */
+    volatile uint32_t  OUT_BRIGHT2;                            /*  OUT_BRIGHT2     */
+    volatile uint32_t  OUT_CONTRAST;                           /*  OUT_CONTRAST    */
+    volatile uint32_t  OUT_PDTHA;                              /*  OUT_PDTHA       */
+    volatile uint8_t   dummy22[12];                            /*                  */
+    volatile uint32_t  OUT_CLK_PHASE;                          /*  OUT_CLK_PHASE   */
+    volatile uint8_t   dummy23[88];                            /*                  */
+#define VDC5_SYSCNT_INT1_COUNT 6
+    volatile uint32_t  SYSCNT_INT1;                            /*  SYSCNT_INT1     */
+    volatile uint32_t  SYSCNT_INT2;                            /*  SYSCNT_INT2     */
+    volatile uint32_t  SYSCNT_INT3;                            /*  SYSCNT_INT3     */
+    volatile uint32_t  SYSCNT_INT4;                            /*  SYSCNT_INT4     */
+    volatile uint32_t  SYSCNT_INT5;                            /*  SYSCNT_INT5     */
+    volatile uint32_t  SYSCNT_INT6;                            /*  SYSCNT_INT6     */
+    volatile uint16_t SYSCNT_PANEL_CLK;                       /*  SYSCNT_PANEL_CLK */
+    volatile uint16_t SYSCNT_CLUT;                            /*  SYSCNT_CLUT     */
+    volatile uint8_t   dummy24[356];                           /*                  */
+/* start of struct st_vdc5_from_sc0_scl0_update */
+    volatile uint32_t  SC1_SCL0_UPDATE;                        /*  SC1_SCL0_UPDATE */
+#define VDC5_SC1_SCL0_FRC1_COUNT 7
+    volatile uint32_t  SC1_SCL0_FRC1;                          /*  SC1_SCL0_FRC1   */
+    volatile uint32_t  SC1_SCL0_FRC2;                          /*  SC1_SCL0_FRC2   */
+    volatile uint32_t  SC1_SCL0_FRC3;                          /*  SC1_SCL0_FRC3   */
+    volatile uint32_t  SC1_SCL0_FRC4;                          /*  SC1_SCL0_FRC4   */
+    volatile uint32_t  SC1_SCL0_FRC5;                          /*  SC1_SCL0_FRC5   */
+    volatile uint32_t  SC1_SCL0_FRC6;                          /*  SC1_SCL0_FRC6   */
+    volatile uint32_t  SC1_SCL0_FRC7;                          /*  SC1_SCL0_FRC7   */
+    volatile uint8_t   dummy25[4];                             /*                  */
+    volatile uint32_t  SC1_SCL0_FRC9;                          /*  SC1_SCL0_FRC9   */
+    volatile uint16_t SC1_SCL0_MON0;                          /*  SC1_SCL0_MON0   */
+    volatile uint16_t SC1_SCL0_INT;                           /*  SC1_SCL0_INT    */
+#define VDC5_SC1_SC1_SCL0_DS1_COUNT 7
+    volatile uint32_t  SC1_SCL0_DS1;                           /*  SC1_SCL0_DS1    */
+    volatile uint32_t  SC1_SCL0_DS2;                           /*  SC1_SCL0_DS2    */
+    volatile uint32_t  SC1_SCL0_DS3;                           /*  SC1_SCL0_DS3    */
+    volatile uint32_t  SC1_SCL0_DS4;                           /*  SC1_SCL0_DS4    */
+    volatile uint32_t  SC1_SCL0_DS5;                           /*  SC1_SCL0_DS5    */
+    volatile uint32_t  SC1_SCL0_DS6;                           /*  SC1_SCL0_DS6    */
+    volatile uint32_t  SC1_SCL0_DS7;                           /*  SC1_SCL0_DS7    */
+#define VDC5_SC1_SC1_SCL0_US1_COUNT 8
+    volatile uint32_t  SC1_SCL0_US1;                           /*  SC1_SCL0_US1    */
+    volatile uint32_t  SC1_SCL0_US2;                           /*  SC1_SCL0_US2    */
+    volatile uint32_t  SC1_SCL0_US3;                           /*  SC1_SCL0_US3    */
+    volatile uint32_t  SC1_SCL0_US4;                           /*  SC1_SCL0_US4    */
+    volatile uint32_t  SC1_SCL0_US5;                           /*  SC1_SCL0_US5    */
+    volatile uint32_t  SC1_SCL0_US6;                           /*  SC1_SCL0_US6    */
+    volatile uint32_t  SC1_SCL0_US7;                           /*  SC1_SCL0_US7    */
+    volatile uint32_t  SC1_SCL0_US8;                           /*  SC1_SCL0_US8    */
+    volatile uint8_t   dummy26[4];                             /*                  */
+    volatile uint32_t  SC1_SCL0_OVR1;                          /*  SC1_SCL0_OVR1   */
+    volatile uint8_t   dummy27[16];                            /*                  */
+    volatile uint32_t  SC1_SCL1_UPDATE;                        /*  SC1_SCL1_UPDATE */
+    volatile uint8_t   dummy28[4];                             /*                  */
+#define VDC5_SC1_SCL1_WR1_COUNT 4
+    volatile uint32_t  SC1_SCL1_WR1;                           /*  SC1_SCL1_WR1    */
+    volatile uint32_t  SC1_SCL1_WR2;                           /*  SC1_SCL1_WR2    */
+    volatile uint32_t  SC1_SCL1_WR3;                           /*  SC1_SCL1_WR3    */
+    volatile uint32_t  SC1_SCL1_WR4;                           /*  SC1_SCL1_WR4    */
+    volatile uint8_t   dummy29[4];                             /*                  */
+    volatile uint32_t  SC1_SCL1_WR5;                           /*  SC1_SCL1_WR5    */
+    volatile uint32_t  SC1_SCL1_WR6;                           /*  SC1_SCL1_WR6    */
+    volatile uint32_t  SC1_SCL1_WR7;                           /*  SC1_SCL1_WR7    */
+    volatile uint32_t  SC1_SCL1_WR8;                           /*  SC1_SCL1_WR8    */
+    volatile uint32_t  SC1_SCL1_WR9;                           /*  SC1_SCL1_WR9    */
+    volatile uint32_t  SC1_SCL1_WR10;                          /*  SC1_SCL1_WR10   */
+/* end of struct st_vdc5_from_sc0_scl0_update */
+    volatile uint32_t  SC1_SCL1_WR11;                          /*  SC1_SCL1_WR11   */
+    volatile uint32_t  SC1_SCL1_MON1;                          /*  SC1_SCL1_MON1   */
+/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
+#define VDC5_SC1_SCL1_PBUF0_COUNT 4
+    volatile uint32_t  SC1_SCL1_PBUF0;                         /*  SC1_SCL1_PBUF0  */
+    volatile uint32_t  SC1_SCL1_PBUF1;                         /*  SC1_SCL1_PBUF1  */
+    volatile uint32_t  SC1_SCL1_PBUF2;                         /*  SC1_SCL1_PBUF2  */
+    volatile uint32_t  SC1_SCL1_PBUF3;                         /*  SC1_SCL1_PBUF3  */
+    volatile uint32_t  SC1_SCL1_PBUF_FLD;                      /*  SC1_SCL1_PBUF_FLD */
+    volatile uint32_t  SC1_SCL1_PBUF_CNT;                      /*  SC1_SCL1_PBUF_CNT */
+/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
+    volatile uint8_t   dummy30[44];                            /*                  */
+/* start of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR1_UPDATE;                             /*  GR1_UPDATE      */
+    volatile uint32_t  GR1_FLM_RD;                             /*  GR1_FLM_RD      */
+#define VDC5_GR1_FLM1_COUNT 6
+    volatile uint32_t  GR1_FLM1;                               /*  GR1_FLM1        */
+    volatile uint32_t  GR1_FLM2;                               /*  GR1_FLM2        */
+    volatile uint32_t  GR1_FLM3;                               /*  GR1_FLM3        */
+    volatile uint32_t  GR1_FLM4;                               /*  GR1_FLM4        */
+    volatile uint32_t  GR1_FLM5;                               /*  GR1_FLM5        */
+    volatile uint32_t  GR1_FLM6;                               /*  GR1_FLM6        */
+#define VDC5_GR1_AB1_COUNT 3
+    volatile uint32_t  GR1_AB1;                                /*  GR1_AB1         */
+    volatile uint32_t  GR1_AB2;                                /*  GR1_AB2         */
+    volatile uint32_t  GR1_AB3;                                /*  GR1_AB3         */
+/* end of struct st_vdc5_from_gr0_update */
+    volatile uint32_t  GR1_AB4;                                /*  GR1_AB4         */
+    volatile uint32_t  GR1_AB5;                                /*  GR1_AB5         */
+    volatile uint32_t  GR1_AB6;                                /*  GR1_AB6         */
+/* start of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR1_AB7;                                /*  GR1_AB7         */
+    volatile uint32_t  GR1_AB8;                                /*  GR1_AB8         */
+    volatile uint32_t  GR1_AB9;                                /*  GR1_AB9         */
+    volatile uint32_t  GR1_AB10;                               /*  GR1_AB10        */
+    volatile uint32_t  GR1_AB11;                               /*  GR1_AB11        */
+    volatile uint32_t  GR1_BASE;                               /*  GR1_BASE        */
+/* end of struct st_vdc5_from_gr0_ab7 */
+    volatile uint32_t  GR1_CLUT;                               /*  GR1_CLUT        */
+    volatile uint32_t  GR1_MON;                                /*  GR1_MON         */
+    volatile uint8_t   dummy31[40];                            /*                  */
+/* start of struct st_vdc5_from_adj0_update */
+    volatile uint32_t  ADJ1_UPDATE;                            /*  ADJ1_UPDATE     */
+    volatile uint32_t  ADJ1_BKSTR_SET;                         /*  ADJ1_BKSTR_SET  */
+#define VDC5_ADJ1_ENH_TIM1_COUNT 3
+    volatile uint32_t  ADJ1_ENH_TIM1;                          /*  ADJ1_ENH_TIM1   */
+    volatile uint32_t  ADJ1_ENH_TIM2;                          /*  ADJ1_ENH_TIM2   */
+    volatile uint32_t  ADJ1_ENH_TIM3;                          /*  ADJ1_ENH_TIM3   */
+#define VDC5_ADJ1_ENH_SHP1_COUNT 6
+    volatile uint32_t  ADJ1_ENH_SHP1;                          /*  ADJ1_ENH_SHP1   */
+    volatile uint32_t  ADJ1_ENH_SHP2;                          /*  ADJ1_ENH_SHP2   */
+    volatile uint32_t  ADJ1_ENH_SHP3;                          /*  ADJ1_ENH_SHP3   */
+    volatile uint32_t  ADJ1_ENH_SHP4;                          /*  ADJ1_ENH_SHP4   */
+    volatile uint32_t  ADJ1_ENH_SHP5;                          /*  ADJ1_ENH_SHP5   */
+    volatile uint32_t  ADJ1_ENH_SHP6;                          /*  ADJ1_ENH_SHP6   */
+#define VDC5_ADJ1_ENH_LTI1_COUNT 2
+    volatile uint32_t  ADJ1_ENH_LTI1;                          /*  ADJ1_ENH_LTI1   */
+    volatile uint32_t  ADJ1_ENH_LTI2;                          /*  ADJ1_ENH_LTI2   */
+    volatile uint32_t  ADJ1_MTX_MODE;                          /*  ADJ1_MTX_MODE   */
+    volatile uint32_t  ADJ1_MTX_YG_ADJ0;                       /*  ADJ1_MTX_YG_ADJ0 */
+    volatile uint32_t  ADJ1_MTX_YG_ADJ1;                       /*  ADJ1_MTX_YG_ADJ1 */
+    volatile uint32_t  ADJ1_MTX_CBB_ADJ0;                      /*  ADJ1_MTX_CBB_ADJ0 */
+    volatile uint32_t  ADJ1_MTX_CBB_ADJ1;                      /*  ADJ1_MTX_CBB_ADJ1 */
+    volatile uint32_t  ADJ1_MTX_CRR_ADJ0;                      /*  ADJ1_MTX_CRR_ADJ0 */
+    volatile uint32_t  ADJ1_MTX_CRR_ADJ1;                      /*  ADJ1_MTX_CRR_ADJ1 */
+/* end of struct st_vdc5_from_adj0_update */
+    volatile uint8_t   dummy32[48];                            /*                  */
+    volatile uint32_t  GR_VIN_UPDATE;                          /*  GR_VIN_UPDATE   */
+    volatile uint8_t   dummy33[28];                            /*                  */
+#define VDC5_GR_VIN_AB1_COUNT 7
+    volatile uint32_t  GR_VIN_AB1;                             /*  GR_VIN_AB1      */
+    volatile uint32_t  GR_VIN_AB2;                             /*  GR_VIN_AB2      */
+    volatile uint32_t  GR_VIN_AB3;                             /*  GR_VIN_AB3      */
+    volatile uint32_t  GR_VIN_AB4;                             /*  GR_VIN_AB4      */
+    volatile uint32_t  GR_VIN_AB5;                             /*  GR_VIN_AB5      */
+    volatile uint32_t  GR_VIN_AB6;                             /*  GR_VIN_AB6      */
+    volatile uint32_t  GR_VIN_AB7;                             /*  GR_VIN_AB7      */
+    volatile uint8_t   dummy34[16];                            /*                  */
+    volatile uint32_t  GR_VIN_BASE;                            /*  GR_VIN_BASE     */
+    volatile uint8_t   dummy35[4];                             /*                  */
+    volatile uint32_t  GR_VIN_MON;                             /*  GR_VIN_MON      */
+    volatile uint8_t   dummy36[40];                            /*                  */
+    volatile uint32_t  OIR_SCL0_UPDATE;                        /*  OIR_SCL0_UPDATE */
+#define VDC5_OIR_SCL0_FRC1_COUNT 7
+    volatile uint32_t  OIR_SCL0_FRC1;                          /*  OIR_SCL0_FRC1   */
+    volatile uint32_t  OIR_SCL0_FRC2;                          /*  OIR_SCL0_FRC2   */
+    volatile uint32_t  OIR_SCL0_FRC3;                          /*  OIR_SCL0_FRC3   */
+    volatile uint32_t  OIR_SCL0_FRC4;                          /*  OIR_SCL0_FRC4   */
+    volatile uint32_t  OIR_SCL0_FRC5;                          /*  OIR_SCL0_FRC5   */
+    volatile uint32_t  OIR_SCL0_FRC6;                          /*  OIR_SCL0_FRC6   */
+    volatile uint32_t  OIR_SCL0_FRC7;                          /*  OIR_SCL0_FRC7   */
+    volatile uint8_t   dummy37[12];                            /*                  */
+#define VDC5_OIR_SCL0_DS1_COUNT 3
+    volatile uint32_t  OIR_SCL0_DS1;                           /*  OIR_SCL0_DS1    */
+    volatile uint32_t  OIR_SCL0_DS2;                           /*  OIR_SCL0_DS2    */
+    volatile uint32_t  OIR_SCL0_DS3;                           /*  OIR_SCL0_DS3    */
+    volatile uint8_t   dummy38[12];                            /*                  */
+    volatile uint32_t  OIR_SCL0_DS7;                           /*  OIR_SCL0_DS7    */
+    volatile uint32_t  OIR_SCL0_US1;                           /*  OIR_SCL0_US1    */
+    volatile uint32_t  OIR_SCL0_US2;                           /*  OIR_SCL0_US2    */
+    volatile uint32_t  OIR_SCL0_US3;                           /*  OIR_SCL0_US3    */
+    volatile uint8_t   dummy39[16];                            /*                  */
+    volatile uint32_t  OIR_SCL0_US8;                           /*  OIR_SCL0_US8    */
+    volatile uint8_t   dummy40[4];                             /*                  */
+    volatile uint32_t  OIR_SCL0_OVR1;                          /*  OIR_SCL0_OVR1   */
+    volatile uint8_t   dummy41[16];                            /*                  */
+    volatile uint32_t  OIR_SCL1_UPDATE;                        /*  OIR_SCL1_UPDATE */
+    volatile uint8_t   dummy42[4];                             /*                  */
+#define VDC5_OIR_SCL1_WR1_COUNT 4
+    volatile uint32_t  OIR_SCL1_WR1;                           /*  OIR_SCL1_WR1    */
+    volatile uint32_t  OIR_SCL1_WR2;                           /*  OIR_SCL1_WR2    */
+    volatile uint32_t  OIR_SCL1_WR3;                           /*  OIR_SCL1_WR3    */
+    volatile uint32_t  OIR_SCL1_WR4;                           /*  OIR_SCL1_WR4    */
+    volatile uint8_t   dummy43[4];                             /*                  */
+    volatile uint32_t  OIR_SCL1_WR5;                           /*  OIR_SCL1_WR5    */
+    volatile uint32_t  OIR_SCL1_WR6;                           /*  OIR_SCL1_WR6    */
+    volatile uint32_t  OIR_SCL1_WR7;                           /*  OIR_SCL1_WR7    */
+    volatile uint8_t   dummy44[88];                            /*                  */
+    volatile uint32_t  GR_OIR_UPDATE;                          /*  GR_OIR_UPDATE   */
+    volatile uint32_t  GR_OIR_FLM_RD;                          /*  GR_OIR_FLM_RD   */
+#define VDC5_GR_OIR_FLM1_COUNT 6
+    volatile uint32_t  GR_OIR_FLM1;                            /*  GR_OIR_FLM1     */
+    volatile uint32_t  GR_OIR_FLM2;                            /*  GR_OIR_FLM2     */
+    volatile uint32_t  GR_OIR_FLM3;                            /*  GR_OIR_FLM3     */
+    volatile uint32_t  GR_OIR_FLM4;                            /*  GR_OIR_FLM4     */
+    volatile uint32_t  GR_OIR_FLM5;                            /*  GR_OIR_FLM5     */
+    volatile uint32_t  GR_OIR_FLM6;                            /*  GR_OIR_FLM6     */
+#define VDC5_GR_OIR_AB1_COUNT 3
+    volatile uint32_t  GR_OIR_AB1;                             /*  GR_OIR_AB1      */
+    volatile uint32_t  GR_OIR_AB2;                             /*  GR_OIR_AB2      */
+    volatile uint32_t  GR_OIR_AB3;                             /*  GR_OIR_AB3      */
+    volatile uint8_t   dummy45[12];                            /*                  */
+    volatile uint32_t  GR_OIR_AB7;                             /*  GR_OIR_AB7      */
+    volatile uint32_t  GR_OIR_AB8;                             /*  GR_OIR_AB8      */
+    volatile uint32_t  GR_OIR_AB9;                             /*  GR_OIR_AB9      */
+    volatile uint32_t  GR_OIR_AB10;                            /*  GR_OIR_AB10     */
+    volatile uint32_t  GR_OIR_AB11;                            /*  GR_OIR_AB11     */
+    volatile uint32_t  GR_OIR_BASE;                            /*  GR_OIR_BASE     */
+    volatile uint32_t  GR_OIR_CLUT;                            /*  GR_OIR_CLUT     */
+    volatile uint32_t  GR_OIR_MON;                             /*  GR_OIR_MON      */
+};
+
+
+struct st_vdc5_from_gr0_update
+{
+    volatile uint32_t  GR0_UPDATE;                             /*  GR0_UPDATE      */
+    volatile uint32_t  GR0_FLM_RD;                             /*  GR0_FLM_RD      */
+    volatile uint32_t  GR0_FLM1;                               /*  GR0_FLM1        */
+    volatile uint32_t  GR0_FLM2;                               /*  GR0_FLM2        */
+    volatile uint32_t  GR0_FLM3;                               /*  GR0_FLM3        */
+    volatile uint32_t  GR0_FLM4;                               /*  GR0_FLM4        */
+    volatile uint32_t  GR0_FLM5;                               /*  GR0_FLM5        */
+    volatile uint32_t  GR0_FLM6;                               /*  GR0_FLM6        */
+    volatile uint32_t  GR0_AB1;                                /*  GR0_AB1         */
+    volatile uint32_t  GR0_AB2;                                /*  GR0_AB2         */
+    volatile uint32_t  GR0_AB3;                                /*  GR0_AB3         */
+};
+
+
+struct st_vdc5_from_gr0_ab7
+{
+    volatile uint32_t  GR0_AB7;                                /*  GR0_AB7         */
+    volatile uint32_t  GR0_AB8;                                /*  GR0_AB8         */
+    volatile uint32_t  GR0_AB9;                                /*  GR0_AB9         */
+    volatile uint32_t  GR0_AB10;                               /*  GR0_AB10        */
+    volatile uint32_t  GR0_AB11;                               /*  GR0_AB11        */
+    volatile uint32_t  GR0_BASE;                               /*  GR0_BASE        */
+};
+
+
+struct st_vdc5_from_adj0_update
+{
+    volatile uint32_t  ADJ0_UPDATE;                            /*  ADJ0_UPDATE     */
+    volatile uint32_t  ADJ0_BKSTR_SET;                         /*  ADJ0_BKSTR_SET  */
+    volatile uint32_t  ADJ0_ENH_TIM1;                          /*  ADJ0_ENH_TIM1   */
+    volatile uint32_t  ADJ0_ENH_TIM2;                          /*  ADJ0_ENH_TIM2   */
+    volatile uint32_t  ADJ0_ENH_TIM3;                          /*  ADJ0_ENH_TIM3   */
+    volatile uint32_t  ADJ0_ENH_SHP1;                          /*  ADJ0_ENH_SHP1   */
+    volatile uint32_t  ADJ0_ENH_SHP2;                          /*  ADJ0_ENH_SHP2   */
+    volatile uint32_t  ADJ0_ENH_SHP3;                          /*  ADJ0_ENH_SHP3   */
+    volatile uint32_t  ADJ0_ENH_SHP4;                          /*  ADJ0_ENH_SHP4   */
+    volatile uint32_t  ADJ0_ENH_SHP5;                          /*  ADJ0_ENH_SHP5   */
+    volatile uint32_t  ADJ0_ENH_SHP6;                          /*  ADJ0_ENH_SHP6   */
+    volatile uint32_t  ADJ0_ENH_LTI1;                          /*  ADJ0_ENH_LTI1   */
+    volatile uint32_t  ADJ0_ENH_LTI2;                          /*  ADJ0_ENH_LTI2   */
+    volatile uint32_t  ADJ0_MTX_MODE;                          /*  ADJ0_MTX_MODE   */
+    volatile uint32_t  ADJ0_MTX_YG_ADJ0;                       /*  ADJ0_MTX_YG_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_YG_ADJ1;                       /*  ADJ0_MTX_YG_ADJ1 */
+    volatile uint32_t  ADJ0_MTX_CBB_ADJ0;                      /*  ADJ0_MTX_CBB_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_CBB_ADJ1;                      /*  ADJ0_MTX_CBB_ADJ1 */
+    volatile uint32_t  ADJ0_MTX_CRR_ADJ0;                      /*  ADJ0_MTX_CRR_ADJ0 */
+    volatile uint32_t  ADJ0_MTX_CRR_ADJ1;                      /*  ADJ0_MTX_CRR_ADJ1 */
+};
+
+
+struct st_vdc5_from_sc0_scl0_update
+{
+    volatile uint32_t  SC0_SCL0_UPDATE;                        /*  SC0_SCL0_UPDATE */
+    volatile uint32_t  SC0_SCL0_FRC1;                          /*  SC0_SCL0_FRC1   */
+    volatile uint32_t  SC0_SCL0_FRC2;                          /*  SC0_SCL0_FRC2   */
+    volatile uint32_t  SC0_SCL0_FRC3;                          /*  SC0_SCL0_FRC3   */
+    volatile uint32_t  SC0_SCL0_FRC4;                          /*  SC0_SCL0_FRC4   */
+    volatile uint32_t  SC0_SCL0_FRC5;                          /*  SC0_SCL0_FRC5   */
+    volatile uint32_t  SC0_SCL0_FRC6;                          /*  SC0_SCL0_FRC6   */
+    volatile uint32_t  SC0_SCL0_FRC7;                          /*  SC0_SCL0_FRC7   */
+    volatile uint8_t   dummy5[4];                              /*                  */
+    volatile uint32_t  SC0_SCL0_FRC9;                          /*  SC0_SCL0_FRC9   */
+    volatile uint16_t SC0_SCL0_MON0;                          /*  SC0_SCL0_MON0   */
+    volatile uint16_t SC0_SCL0_INT;                           /*  SC0_SCL0_INT    */
+    volatile uint32_t  SC0_SCL0_DS1;                           /*  SC0_SCL0_DS1    */
+    volatile uint32_t  SC0_SCL0_DS2;                           /*  SC0_SCL0_DS2    */
+    volatile uint32_t  SC0_SCL0_DS3;                           /*  SC0_SCL0_DS3    */
+    volatile uint32_t  SC0_SCL0_DS4;                           /*  SC0_SCL0_DS4    */
+    volatile uint32_t  SC0_SCL0_DS5;                           /*  SC0_SCL0_DS5    */
+    volatile uint32_t  SC0_SCL0_DS6;                           /*  SC0_SCL0_DS6    */
+    volatile uint32_t  SC0_SCL0_DS7;                           /*  SC0_SCL0_DS7    */
+    volatile uint32_t  SC0_SCL0_US1;                           /*  SC0_SCL0_US1    */
+    volatile uint32_t  SC0_SCL0_US2;                           /*  SC0_SCL0_US2    */
+    volatile uint32_t  SC0_SCL0_US3;                           /*  SC0_SCL0_US3    */
+    volatile uint32_t  SC0_SCL0_US4;                           /*  SC0_SCL0_US4    */
+    volatile uint32_t  SC0_SCL0_US5;                           /*  SC0_SCL0_US5    */
+    volatile uint32_t  SC0_SCL0_US6;                           /*  SC0_SCL0_US6    */
+    volatile uint32_t  SC0_SCL0_US7;                           /*  SC0_SCL0_US7    */
+    volatile uint32_t  SC0_SCL0_US8;                           /*  SC0_SCL0_US8    */
+    volatile uint8_t   dummy6[4];                              /*                  */
+    volatile uint32_t  SC0_SCL0_OVR1;                          /*  SC0_SCL0_OVR1   */
+    volatile uint8_t   dummy7[16];                             /*                  */
+    volatile uint32_t  SC0_SCL1_UPDATE;                        /*  SC0_SCL1_UPDATE */
+    volatile uint8_t   dummy8[4];                              /*                  */
+    volatile uint32_t  SC0_SCL1_WR1;                           /*  SC0_SCL1_WR1    */
+    volatile uint32_t  SC0_SCL1_WR2;                           /*  SC0_SCL1_WR2    */
+    volatile uint32_t  SC0_SCL1_WR3;                           /*  SC0_SCL1_WR3    */
+    volatile uint32_t  SC0_SCL1_WR4;                           /*  SC0_SCL1_WR4    */
+    volatile uint8_t   dummy9[4];                              /*                  */
+    volatile uint32_t  SC0_SCL1_WR5;                           /*  SC0_SCL1_WR5    */
+    volatile uint32_t  SC0_SCL1_WR6;                           /*  SC0_SCL1_WR6    */
+    volatile uint32_t  SC0_SCL1_WR7;                           /*  SC0_SCL1_WR7    */
+    volatile uint32_t  SC0_SCL1_WR8;                           /*  SC0_SCL1_WR8    */
+    volatile uint32_t  SC0_SCL1_WR9;                           /*  SC0_SCL1_WR9    */
+    volatile uint32_t  SC0_SCL1_WR10;                          /*  SC0_SCL1_WR10   */
+};
+
+
+struct st_vdc5_from_sc0_scl1_pbuf0
+{
+    volatile uint32_t  SC0_SCL1_PBUF0;                         /*  SC0_SCL1_PBUF0  */
+    volatile uint32_t  SC0_SCL1_PBUF1;                         /*  SC0_SCL1_PBUF1  */
+    volatile uint32_t  SC0_SCL1_PBUF2;                         /*  SC0_SCL1_PBUF2  */
+    volatile uint32_t  SC0_SCL1_PBUF3;                         /*  SC0_SCL1_PBUF3  */
+    volatile uint32_t  SC0_SCL1_PBUF_FLD;                      /*  SC0_SCL1_PBUF_FLD */
+    volatile uint32_t  SC0_SCL1_PBUF_CNT;                      /*  SC0_SCL1_PBUF_CNT */
+};
+
+
+#define VDC50   (*(struct st_vdc5    *)0xFCFF7400uL) /* VDC50 */
+#define VDC51   (*(struct st_vdc5    *)0xFCFF9400uL) /* VDC51 */
+
+
+/* Start of channnel array defines of VDC5 */
+
+/* Channnel array defines of VDC5 */
+/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
+#define VDC5_COUNT  2
+#define VDC5_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &VDC50, &VDC51 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC5n_FROM_GR2_AB7_ARRAY_COUNT  2
+#define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
+    &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
+#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
+#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
+#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT  2
+#define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
+    &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
+#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
+#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
+#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */
+/*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
+#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT  2
+#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
+    &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
+#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
+#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
+#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
+#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT  2
+#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
+    &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
+#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
+#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
+#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
+#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT  2
+#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
+    &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
+#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
+#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
+#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC5n_FROM_GR0_AB7_ARRAY_COUNT  2
+#define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
+    &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
+#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
+#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
+#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
+
+
+
+
+/* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */
+/*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT  2
+#define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
+    &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
+#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
+#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
+#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
+
+
+/* End of channnel array defines of VDC5 */
+
+
+#define VDC50INP_UPDATE VDC50.INP_UPDATE
+#define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT
+#define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT
+#define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ
+#define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ
+#define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE
+#define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0
+#define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1
+#define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE
+#define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0
+#define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1
+#define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0
+#define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1
+#define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0
+#define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1
+#define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG
+#define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE
+#define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1
+#define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2
+#define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3
+#define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4
+#define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5
+#define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6
+#define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7
+#define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9
+#define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0
+#define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT
+#define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1
+#define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2
+#define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3
+#define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4
+#define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5
+#define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6
+#define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7
+#define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1
+#define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2
+#define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3
+#define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4
+#define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5
+#define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6
+#define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7
+#define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8
+#define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1
+#define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE
+#define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1
+#define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2
+#define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3
+#define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4
+#define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5
+#define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6
+#define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7
+#define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8
+#define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9
+#define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10
+#define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11
+#define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1
+#define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0
+#define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1
+#define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2
+#define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3
+#define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD
+#define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT
+#define VDC50GR0_UPDATE VDC50.GR0_UPDATE
+#define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD
+#define VDC50GR0_FLM1 VDC50.GR0_FLM1
+#define VDC50GR0_FLM2 VDC50.GR0_FLM2
+#define VDC50GR0_FLM3 VDC50.GR0_FLM3
+#define VDC50GR0_FLM4 VDC50.GR0_FLM4
+#define VDC50GR0_FLM5 VDC50.GR0_FLM5
+#define VDC50GR0_FLM6 VDC50.GR0_FLM6
+#define VDC50GR0_AB1 VDC50.GR0_AB1
+#define VDC50GR0_AB2 VDC50.GR0_AB2
+#define VDC50GR0_AB3 VDC50.GR0_AB3
+#define VDC50GR0_AB7 VDC50.GR0_AB7
+#define VDC50GR0_AB8 VDC50.GR0_AB8
+#define VDC50GR0_AB9 VDC50.GR0_AB9
+#define VDC50GR0_AB10 VDC50.GR0_AB10
+#define VDC50GR0_AB11 VDC50.GR0_AB11
+#define VDC50GR0_BASE VDC50.GR0_BASE
+#define VDC50GR0_CLUT VDC50.GR0_CLUT
+#define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE
+#define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET
+#define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1
+#define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2
+#define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3
+#define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1
+#define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2
+#define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3
+#define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4
+#define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5
+#define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6
+#define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1
+#define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2
+#define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE
+#define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0
+#define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1
+#define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0
+#define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1
+#define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0
+#define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1
+#define VDC50GR2_UPDATE VDC50.GR2_UPDATE
+#define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD
+#define VDC50GR2_FLM1 VDC50.GR2_FLM1
+#define VDC50GR2_FLM2 VDC50.GR2_FLM2
+#define VDC50GR2_FLM3 VDC50.GR2_FLM3
+#define VDC50GR2_FLM4 VDC50.GR2_FLM4
+#define VDC50GR2_FLM5 VDC50.GR2_FLM5
+#define VDC50GR2_FLM6 VDC50.GR2_FLM6
+#define VDC50GR2_AB1 VDC50.GR2_AB1
+#define VDC50GR2_AB2 VDC50.GR2_AB2
+#define VDC50GR2_AB3 VDC50.GR2_AB3
+#define VDC50GR2_AB4 VDC50.GR2_AB4
+#define VDC50GR2_AB5 VDC50.GR2_AB5
+#define VDC50GR2_AB6 VDC50.GR2_AB6
+#define VDC50GR2_AB7 VDC50.GR2_AB7
+#define VDC50GR2_AB8 VDC50.GR2_AB8
+#define VDC50GR2_AB9 VDC50.GR2_AB9
+#define VDC50GR2_AB10 VDC50.GR2_AB10
+#define VDC50GR2_AB11 VDC50.GR2_AB11
+#define VDC50GR2_BASE VDC50.GR2_BASE
+#define VDC50GR2_CLUT VDC50.GR2_CLUT
+#define VDC50GR2_MON VDC50.GR2_MON
+#define VDC50GR3_UPDATE VDC50.GR3_UPDATE
+#define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD
+#define VDC50GR3_FLM1 VDC50.GR3_FLM1
+#define VDC50GR3_FLM2 VDC50.GR3_FLM2
+#define VDC50GR3_FLM3 VDC50.GR3_FLM3
+#define VDC50GR3_FLM4 VDC50.GR3_FLM4
+#define VDC50GR3_FLM5 VDC50.GR3_FLM5
+#define VDC50GR3_FLM6 VDC50.GR3_FLM6
+#define VDC50GR3_AB1 VDC50.GR3_AB1
+#define VDC50GR3_AB2 VDC50.GR3_AB2
+#define VDC50GR3_AB3 VDC50.GR3_AB3
+#define VDC50GR3_AB4 VDC50.GR3_AB4
+#define VDC50GR3_AB5 VDC50.GR3_AB5
+#define VDC50GR3_AB6 VDC50.GR3_AB6
+#define VDC50GR3_AB7 VDC50.GR3_AB7
+#define VDC50GR3_AB8 VDC50.GR3_AB8
+#define VDC50GR3_AB9 VDC50.GR3_AB9
+#define VDC50GR3_AB10 VDC50.GR3_AB10
+#define VDC50GR3_AB11 VDC50.GR3_AB11
+#define VDC50GR3_BASE VDC50.GR3_BASE
+#define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT
+#define VDC50GR3_MON VDC50.GR3_MON
+#define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE
+#define VDC50GAM_SW VDC50.GAM_SW
+#define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1
+#define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2
+#define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3
+#define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4
+#define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5
+#define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6
+#define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7
+#define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8
+#define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9
+#define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10
+#define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11
+#define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12
+#define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13
+#define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14
+#define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15
+#define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16
+#define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1
+#define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2
+#define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3
+#define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4
+#define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5
+#define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6
+#define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7
+#define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8
+#define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE
+#define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1
+#define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2
+#define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3
+#define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4
+#define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5
+#define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6
+#define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7
+#define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8
+#define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9
+#define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10
+#define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11
+#define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12
+#define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13
+#define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14
+#define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15
+#define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16
+#define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1
+#define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2
+#define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3
+#define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4
+#define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5
+#define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6
+#define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7
+#define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8
+#define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE
+#define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1
+#define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2
+#define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3
+#define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4
+#define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5
+#define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6
+#define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7
+#define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8
+#define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9
+#define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10
+#define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11
+#define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12
+#define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13
+#define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14
+#define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15
+#define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16
+#define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1
+#define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2
+#define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3
+#define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4
+#define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5
+#define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6
+#define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7
+#define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8
+#define VDC50TCON_UPDATE VDC50.TCON_UPDATE
+#define VDC50TCON_TIM VDC50.TCON_TIM
+#define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1
+#define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2
+#define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1
+#define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2
+#define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1
+#define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2
+#define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1
+#define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2
+#define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1
+#define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2
+#define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1
+#define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2
+#define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1
+#define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2
+#define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE
+#define VDC50OUT_UPDATE VDC50.OUT_UPDATE
+#define VDC50OUT_SET VDC50.OUT_SET
+#define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1
+#define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2
+#define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST
+#define VDC50OUT_PDTHA VDC50.OUT_PDTHA
+#define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE
+#define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1
+#define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2
+#define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3
+#define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4
+#define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5
+#define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6
+#define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK
+#define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT
+#define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE
+#define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1
+#define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2
+#define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3
+#define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4
+#define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5
+#define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6
+#define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7
+#define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9
+#define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0
+#define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT
+#define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1
+#define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2
+#define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3
+#define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4
+#define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5
+#define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6
+#define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7
+#define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1
+#define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2
+#define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3
+#define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4
+#define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5
+#define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6
+#define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7
+#define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8
+#define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1
+#define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE
+#define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1
+#define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2
+#define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3
+#define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4
+#define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5
+#define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6
+#define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7
+#define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8
+#define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9
+#define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10
+#define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11
+#define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1
+#define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0
+#define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1
+#define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2
+#define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3
+#define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD
+#define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT
+#define VDC50GR1_UPDATE VDC50.GR1_UPDATE
+#define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD
+#define VDC50GR1_FLM1 VDC50.GR1_FLM1
+#define VDC50GR1_FLM2 VDC50.GR1_FLM2
+#define VDC50GR1_FLM3 VDC50.GR1_FLM3
+#define VDC50GR1_FLM4 VDC50.GR1_FLM4
+#define VDC50GR1_FLM5 VDC50.GR1_FLM5
+#define VDC50GR1_FLM6 VDC50.GR1_FLM6
+#define VDC50GR1_AB1 VDC50.GR1_AB1
+#define VDC50GR1_AB2 VDC50.GR1_AB2
+#define VDC50GR1_AB3 VDC50.GR1_AB3
+#define VDC50GR1_AB4 VDC50.GR1_AB4
+#define VDC50GR1_AB5 VDC50.GR1_AB5
+#define VDC50GR1_AB6 VDC50.GR1_AB6
+#define VDC50GR1_AB7 VDC50.GR1_AB7
+#define VDC50GR1_AB8 VDC50.GR1_AB8
+#define VDC50GR1_AB9 VDC50.GR1_AB9
+#define VDC50GR1_AB10 VDC50.GR1_AB10
+#define VDC50GR1_AB11 VDC50.GR1_AB11
+#define VDC50GR1_BASE VDC50.GR1_BASE
+#define VDC50GR1_CLUT VDC50.GR1_CLUT
+#define VDC50GR1_MON VDC50.GR1_MON
+#define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE
+#define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET
+#define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1
+#define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2
+#define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3
+#define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1
+#define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2
+#define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3
+#define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4
+#define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5
+#define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6
+#define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1
+#define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2
+#define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE
+#define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0
+#define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1
+#define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0
+#define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1
+#define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0
+#define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1
+#define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE
+#define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1
+#define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2
+#define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3
+#define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4
+#define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5
+#define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6
+#define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7
+#define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE
+#define VDC50GR_VIN_MON VDC50.GR_VIN_MON
+#define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE
+#define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1
+#define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2
+#define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3
+#define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4
+#define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5
+#define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6
+#define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7
+#define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1
+#define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2
+#define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3
+#define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7
+#define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1
+#define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2
+#define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3
+#define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8
+#define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1
+#define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE
+#define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1
+#define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2
+#define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3
+#define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4
+#define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5
+#define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6
+#define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7
+#define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE
+#define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD
+#define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1
+#define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2
+#define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3
+#define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4
+#define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5
+#define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6
+#define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1
+#define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2
+#define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3
+#define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7
+#define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8
+#define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9
+#define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10
+#define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11
+#define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE
+#define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT
+#define VDC50GR_OIR_MON VDC50.GR_OIR_MON
+#define VDC51INP_UPDATE VDC51.INP_UPDATE
+#define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT
+#define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT
+#define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ
+#define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ
+#define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE
+#define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0
+#define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1
+#define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE
+#define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0
+#define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1
+#define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0
+#define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1
+#define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0
+#define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1
+#define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG
+#define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE
+#define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1
+#define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2
+#define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3
+#define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4
+#define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5
+#define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6
+#define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7
+#define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9
+#define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0
+#define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT
+#define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1
+#define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2
+#define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3
+#define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4
+#define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5
+#define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6
+#define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7
+#define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1
+#define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2
+#define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3
+#define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4
+#define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5
+#define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6
+#define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7
+#define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8
+#define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1
+#define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE
+#define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1
+#define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2
+#define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3
+#define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4
+#define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5
+#define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6
+#define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7
+#define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8
+#define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9
+#define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10
+#define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11
+#define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1
+#define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0
+#define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1
+#define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2
+#define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3
+#define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD
+#define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT
+#define VDC51GR0_UPDATE VDC51.GR0_UPDATE
+#define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD
+#define VDC51GR0_FLM1 VDC51.GR0_FLM1
+#define VDC51GR0_FLM2 VDC51.GR0_FLM2
+#define VDC51GR0_FLM3 VDC51.GR0_FLM3
+#define VDC51GR0_FLM4 VDC51.GR0_FLM4
+#define VDC51GR0_FLM5 VDC51.GR0_FLM5
+#define VDC51GR0_FLM6 VDC51.GR0_FLM6
+#define VDC51GR0_AB1 VDC51.GR0_AB1
+#define VDC51GR0_AB2 VDC51.GR0_AB2
+#define VDC51GR0_AB3 VDC51.GR0_AB3
+#define VDC51GR0_AB7 VDC51.GR0_AB7
+#define VDC51GR0_AB8 VDC51.GR0_AB8
+#define VDC51GR0_AB9 VDC51.GR0_AB9
+#define VDC51GR0_AB10 VDC51.GR0_AB10
+#define VDC51GR0_AB11 VDC51.GR0_AB11
+#define VDC51GR0_BASE VDC51.GR0_BASE
+#define VDC51GR0_CLUT VDC51.GR0_CLUT
+#define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE
+#define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET
+#define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1
+#define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2
+#define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3
+#define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1
+#define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2
+#define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3
+#define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4
+#define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5
+#define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6
+#define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1
+#define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2
+#define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE
+#define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0
+#define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1
+#define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0
+#define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1
+#define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0
+#define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1
+#define VDC51GR2_UPDATE VDC51.GR2_UPDATE
+#define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD
+#define VDC51GR2_FLM1 VDC51.GR2_FLM1
+#define VDC51GR2_FLM2 VDC51.GR2_FLM2
+#define VDC51GR2_FLM3 VDC51.GR2_FLM3
+#define VDC51GR2_FLM4 VDC51.GR2_FLM4
+#define VDC51GR2_FLM5 VDC51.GR2_FLM5
+#define VDC51GR2_FLM6 VDC51.GR2_FLM6
+#define VDC51GR2_AB1 VDC51.GR2_AB1
+#define VDC51GR2_AB2 VDC51.GR2_AB2
+#define VDC51GR2_AB3 VDC51.GR2_AB3
+#define VDC51GR2_AB4 VDC51.GR2_AB4
+#define VDC51GR2_AB5 VDC51.GR2_AB5
+#define VDC51GR2_AB6 VDC51.GR2_AB6
+#define VDC51GR2_AB7 VDC51.GR2_AB7
+#define VDC51GR2_AB8 VDC51.GR2_AB8
+#define VDC51GR2_AB9 VDC51.GR2_AB9
+#define VDC51GR2_AB10 VDC51.GR2_AB10
+#define VDC51GR2_AB11 VDC51.GR2_AB11
+#define VDC51GR2_BASE VDC51.GR2_BASE
+#define VDC51GR2_CLUT VDC51.GR2_CLUT
+#define VDC51GR2_MON VDC51.GR2_MON
+#define VDC51GR3_UPDATE VDC51.GR3_UPDATE
+#define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD
+#define VDC51GR3_FLM1 VDC51.GR3_FLM1
+#define VDC51GR3_FLM2 VDC51.GR3_FLM2
+#define VDC51GR3_FLM3 VDC51.GR3_FLM3
+#define VDC51GR3_FLM4 VDC51.GR3_FLM4
+#define VDC51GR3_FLM5 VDC51.GR3_FLM5
+#define VDC51GR3_FLM6 VDC51.GR3_FLM6
+#define VDC51GR3_AB1 VDC51.GR3_AB1
+#define VDC51GR3_AB2 VDC51.GR3_AB2
+#define VDC51GR3_AB3 VDC51.GR3_AB3
+#define VDC51GR3_AB4 VDC51.GR3_AB4
+#define VDC51GR3_AB5 VDC51.GR3_AB5
+#define VDC51GR3_AB6 VDC51.GR3_AB6
+#define VDC51GR3_AB7 VDC51.GR3_AB7
+#define VDC51GR3_AB8 VDC51.GR3_AB8
+#define VDC51GR3_AB9 VDC51.GR3_AB9
+#define VDC51GR3_AB10 VDC51.GR3_AB10
+#define VDC51GR3_AB11 VDC51.GR3_AB11
+#define VDC51GR3_BASE VDC51.GR3_BASE
+#define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT
+#define VDC51GR3_MON VDC51.GR3_MON
+#define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE
+#define VDC51GAM_SW VDC51.GAM_SW
+#define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1
+#define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2
+#define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3
+#define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4
+#define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5
+#define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6
+#define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7
+#define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8
+#define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9
+#define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10
+#define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11
+#define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12
+#define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13
+#define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14
+#define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15
+#define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16
+#define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1
+#define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2
+#define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3
+#define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4
+#define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5
+#define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6
+#define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7
+#define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8
+#define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE
+#define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1
+#define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2
+#define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3
+#define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4
+#define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5
+#define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6
+#define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7
+#define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8
+#define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9
+#define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10
+#define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11
+#define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12
+#define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13
+#define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14
+#define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15
+#define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16
+#define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1
+#define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2
+#define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3
+#define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4
+#define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5
+#define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6
+#define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7
+#define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8
+#define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE
+#define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1
+#define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2
+#define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3
+#define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4
+#define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5
+#define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6
+#define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7
+#define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8
+#define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9
+#define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10
+#define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11
+#define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12
+#define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13
+#define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14
+#define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15
+#define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16
+#define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1
+#define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2
+#define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3
+#define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4
+#define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5
+#define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6
+#define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7
+#define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8
+#define VDC51TCON_UPDATE VDC51.TCON_UPDATE
+#define VDC51TCON_TIM VDC51.TCON_TIM
+#define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1
+#define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2
+#define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1
+#define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2
+#define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1
+#define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2
+#define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1
+#define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2
+#define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1
+#define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2
+#define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1
+#define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2
+#define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1
+#define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2
+#define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE
+#define VDC51OUT_UPDATE VDC51.OUT_UPDATE
+#define VDC51OUT_SET VDC51.OUT_SET
+#define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1
+#define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2
+#define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST
+#define VDC51OUT_PDTHA VDC51.OUT_PDTHA
+#define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE
+#define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1
+#define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2
+#define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3
+#define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4
+#define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5
+#define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6
+#define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK
+#define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT
+#define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE
+#define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1
+#define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2
+#define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3
+#define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4
+#define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5
+#define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6
+#define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7
+#define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9
+#define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0
+#define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT
+#define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1
+#define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2
+#define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3
+#define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4
+#define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5
+#define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6
+#define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7
+#define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1
+#define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2
+#define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3
+#define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4
+#define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5
+#define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6
+#define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7
+#define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8
+#define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1
+#define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE
+#define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1
+#define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2
+#define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3
+#define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4
+#define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5
+#define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6
+#define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7
+#define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8
+#define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9
+#define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10
+#define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11
+#define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1
+#define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0
+#define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1
+#define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2
+#define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3
+#define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD
+#define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT
+#define VDC51GR1_UPDATE VDC51.GR1_UPDATE
+#define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD
+#define VDC51GR1_FLM1 VDC51.GR1_FLM1
+#define VDC51GR1_FLM2 VDC51.GR1_FLM2
+#define VDC51GR1_FLM3 VDC51.GR1_FLM3
+#define VDC51GR1_FLM4 VDC51.GR1_FLM4
+#define VDC51GR1_FLM5 VDC51.GR1_FLM5
+#define VDC51GR1_FLM6 VDC51.GR1_FLM6
+#define VDC51GR1_AB1 VDC51.GR1_AB1
+#define VDC51GR1_AB2 VDC51.GR1_AB2
+#define VDC51GR1_AB3 VDC51.GR1_AB3
+#define VDC51GR1_AB4 VDC51.GR1_AB4
+#define VDC51GR1_AB5 VDC51.GR1_AB5
+#define VDC51GR1_AB6 VDC51.GR1_AB6
+#define VDC51GR1_AB7 VDC51.GR1_AB7
+#define VDC51GR1_AB8 VDC51.GR1_AB8
+#define VDC51GR1_AB9 VDC51.GR1_AB9
+#define VDC51GR1_AB10 VDC51.GR1_AB10
+#define VDC51GR1_AB11 VDC51.GR1_AB11
+#define VDC51GR1_BASE VDC51.GR1_BASE
+#define VDC51GR1_CLUT VDC51.GR1_CLUT
+#define VDC51GR1_MON VDC51.GR1_MON
+#define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE
+#define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET
+#define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1
+#define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2
+#define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3
+#define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1
+#define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2
+#define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3
+#define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4
+#define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5
+#define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6
+#define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1
+#define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2
+#define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE
+#define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0
+#define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1
+#define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0
+#define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1
+#define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0
+#define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1
+#define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE
+#define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1
+#define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2
+#define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3
+#define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4
+#define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5
+#define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6
+#define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7
+#define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE
+#define VDC51GR_VIN_MON VDC51.GR_VIN_MON
+#define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE
+#define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1
+#define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2
+#define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3
+#define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4
+#define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5
+#define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6
+#define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7
+#define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1
+#define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2
+#define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3
+#define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7
+#define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1
+#define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2
+#define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3
+#define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8
+#define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1
+#define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE
+#define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1
+#define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2
+#define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3
+#define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4
+#define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5
+#define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6
+#define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7
+#define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE
+#define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD
+#define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1
+#define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2
+#define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3
+#define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4
+#define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5
+#define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6
+#define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1
+#define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2
+#define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3
+#define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7
+#define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8
+#define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9
+#define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10
+#define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11
+#define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE
+#define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT
+#define VDC51GR_OIR_MON VDC51.GR_OIR_MON
+/* <-SEC M1.10.1 */
+/* <-QAC 0639 */
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/wdt_iodefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,47 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : wdt_iodefine.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register (V1.00a)
+******************************************************************************/
+#ifndef WDT_IODEFINE_H
+#define WDT_IODEFINE_H
+
+struct st_wdt
+{                                                          /* WDT              */
+    volatile uint16_t WTCSR;                                  /*  WTCSR           */
+    volatile uint16_t WTCNT;                                  /*  WTCNT           */
+    volatile uint16_t WRCSR;                                  /*  WRCSR           */
+};
+
+
+#define WDT     (*(struct st_wdt     *)0xFCFE0000uL) /* WDT */
+
+
+#define WDTWTCSR WDT.WTCSR
+#define WDTWTCNT WDT.WTCNT
+#define WDTWRCSR WDT.WRCSR
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/reg32_t.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,12 @@
+#ifndef __REG32_T
+#define __REG32_T
+
+union reg32_t {
+    volatile uint32_t UINT32;
+    volatile uint16_t UINT16[2];
+    volatile uint8_t  UINT8[4];
+};
+
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/rza_io_regrw.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : rza_io_regrw.h
+* $Rev: 1135 $
+* $Date:: 2014-08-08 10:11:30 +0900#$
+* Description : Low level register read/write header
+*******************************************************************************/
+#ifndef RZA_IO_REGRW_H
+#define RZA_IO_REGRW_H
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+/* ==== includes each bit mask header ==== */
+#include "cpg_iobitmask.h"
+#include "intc_iobitmask.h"
+#include "bsc_iobitmask.h"
+#include "dmac_iobitmask.h"
+#include "mtu2_iobitmask.h"
+#include "ostm_iobitmask.h"
+#include "scif_iobitmask.h"
+#include "rspi_iobitmask.h"
+#include "riic_iobitmask.h"
+#include "usb_iobitmask.h"
+#include "gpio_iobitmask.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+void     RZA_IO_RegWrite_8 (volatile uint8_t  * ioreg, uint8_t  write_value, uint8_t  shift, uint8_t  mask);
+void     RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask);
+void     RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask);
+uint8_t  RZA_IO_RegRead_8  (volatile uint8_t  * ioreg, uint8_t  shift, uint8_t  mask);
+uint16_t RZA_IO_RegRead_16 (volatile uint16_t * ioreg, uint16_t shift, uint16_t mask);
+uint32_t RZA_IO_RegRead_32 (volatile uint32_t * ioreg, uint32_t shift, uint32_t mask);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* RZA_IO_REGRW_H */
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/mmu_Renesas_RZ_A1.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,244 @@
+/**************************************************************************//**
+ * @file     mmu_Renesas_RZ_A1.c
+ * @brief    MMU Startup File for
+ *           mmu_Renesas_RZ_A1 Device Series
+ * @version  V1.01
+ * @date     2 Aug 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#define Renesas_RZ_A1_SPI_MIO_BASE                 (0x3fe00000UL)                        /*!< (SPI_MIO   ) Base Address */
+#define Renesas_RZ_A1_BSC_BASE                     (0x3ff00000UL)                        /*!< (BSC       ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE0                 (0xe8000000UL)                        /*!< (PERIPH0   ) Base Address */
+#define Renesas_RZ_A1_PERIPH_BASE1                 (0xfcf00000UL)                        /*!< (PERIPH1   ) Base Address */
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings.
+//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors place all memory in domain 0
+//There are no restrictions by privilege level (PL0 can access all memory)
+
+#include <stdint.h>
+#include "VKRZA1H.h"
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RO_DATA$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$ZI_DATA$$Base;
+#if !defined ( __ICCARM__ )
+extern uint32_t Image$$TTB$$ZI$$Base;
+#endif 
+
+#if defined( __CC_ARM )
+#elif defined( __ICCARM__ )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Base;
+extern uint32_t Image$$ZI_DATA_NC$$Base;
+#endif
+
+extern uint32_t Image$$VECTORS$$Limit;
+extern uint32_t Image$$RO_DATA$$Limit;
+extern uint32_t Image$$RW_DATA$$Limit;
+extern uint32_t Image$$ZI_DATA$$Limit;
+#if defined( __CC_ARM )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Limit;
+extern uint32_t Image$$ZI_DATA_NC$$Limit;
+#endif
+
+#if defined( __ICCARM__ )
+#define VECTORS_SIZE    (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE    (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE    (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
+#define ZI_DATA_SIZE    (((uint32_t)Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)Image$$ZI_DATA$$Base >> 20) + 1)
+#else
+#define VECTORS_SIZE    (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE    (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE    (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
+#define ZI_DATA_SIZE    (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
+#endif
+
+#if defined( __CC_ARM )
+#else
+#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
+#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
+#endif
+
+static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_NC;  //non-shareable, non-executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k  = 0x0;  //generic
+static uint32_t Page_L1_64k = 0x0;  //generic
+static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+#if defined ( __ICCARM__ )
+__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
+uint32_t Image$$VECTORS$$Base;
+uint32_t Image$$RO_DATA$$Base;
+uint32_t Image$$RW_DATA$$Base;
+uint32_t Image$$ZI_DATA$$Base;
+
+uint32_t Image$$VECTORS$$Limit;
+uint32_t Image$$RO_DATA$$Limit;
+uint32_t Image$$RW_DATA$$Limit;
+uint32_t Image$$ZI_DATA$$Limit;
+#endif
+
+void create_translation_table(void)
+{
+    mmu_region_attributes_Type region;
+#if defined ( __ICCARM__ )
+#pragma section=".intvec"
+#pragma section=".rodata"
+#pragma section=".rwdata"
+#pragma section=".bss"
+
+    Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
+    Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
+    Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
+    Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
+    Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); 
+    Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
+    Image$$ZI_DATA$$Base = (uint32_t) __section_begin(".bss");  
+    Image$$ZI_DATA$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
+#endif
+    /*
+     * Generate descriptors. Refer to VKRZA1H.h to get information about attributes
+     *
+     */
+    //Create descriptors for Vectors, RO, RW, ZI sections
+    section_normal(Sect_Normal, region);
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_ro(Sect_Normal_RO, region);
+    section_normal_rw(Sect_Normal_RW, region);
+    //Create descriptors for peripherals
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+    section_normal_nc(Sect_Normal_NC, region);
+    //Create descriptors for 64k pages
+    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+    //Create descriptors for 4k pages
+    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+    /*
+     *  Define MMU flat-map regions and attributes
+     *
+     */
+
+    //Create 4GB of faulting entries
+    __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+    // R7S72100 memory map.
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0    , 64, Sect_Normal_RO);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1    , 64, Sect_Normal_RO);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0       , 64, Sect_Normal_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1       , 64, Sect_Normal_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0        , 64, Sect_Normal_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1        , 64, Sect_Normal_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0           , 64, Sect_Normal_RO);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1           , 64, Sect_Normal_RO);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE  , 10, Sect_Normal_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE      ,  1, Sect_Device_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE          ,  1, Sect_Device_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0      ,  3, Sect_Device_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1      , 49, Sect_Device_RW);
+
+#if defined( __ICCARM__ )
+    //Define Image
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
+#else
+    //Define Image
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
+#endif
+
+#if defined( __CC_ARM )
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,         10, Sect_Normal_NC);
+#elif defined ( __ICCARM__ ) 
+    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,         10, Sect_Normal_NC);
+
+#else
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
+    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
+#endif
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x0 (Inner WB WA)
+    ; 5     - NOS     0x0 (Non-shared)
+    ; 4:3   - RGN     0x1 (Outer WB WA)
+    ; 2     - IMP     0x0 (Implementation Defined)
+    ; 1     - S       0x0 (Non-shared)
+    ; 0     - IRGN[1] 0x1 (Inner WB WA) */
+    __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(1);
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/nvic_wrapper.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,230 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         nvic_wrapper.c
+* $Rev:  $
+* $Date:: $
+* @brief        Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
+******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "VKRZA1H.h"
+#include "wdt_iodefine.h"
+#include "nvic_wrapper.h"
+#include "gic.h"
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+#define PRIO_BITS            (7)   /* Set binary point to 0 in gic.c */
+#define WDT_WTCNT_WRITE      (0x5A00)
+#define WDT_WTCSR_WRITE      (0xA500)
+#define WDT_WRCSR_WOVF_WRITE (0xA500)
+#define WDT_WRCSR_RSTE_WRITE (0x5A00)
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    GIC_SetBinaryPoint(PriorityGroup);
+}
+
+
+uint32_t NVIC_GetPriorityGrouping(void)
+{
+    return GIC_GetBinaryPoint(0);
+}
+
+
+void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    GIC_EnableIRQ(IRQn);
+}
+
+
+void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    GIC_DisableIRQ(IRQn);
+}
+
+
+uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    uint32_t pending;
+    
+    pending = GIC_GetIRQStatus(IRQn);
+    pending = (pending & 0x00000001);
+    
+    return pending;
+}
+
+
+void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    GIC_SetPendingIRQ(IRQn);
+}
+
+
+void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    GIC_ClearPendingIRQ(IRQn);
+}
+
+
+uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+    uint32_t active;
+    
+    active = GIC_GetIRQStatus(IRQn);
+    active = ((active >> 1) & 0x00000001);
+    
+    return active;
+}
+
+
+void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    GIC_SetPriority(IRQn, (priority << 3));
+}
+
+
+uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+    uint32_t priority_field;
+    
+    priority_field = GIC_GetPriority(IRQn);
+    priority_field = (priority_field >> 3);
+    return priority_field;
+}
+
+
+uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
+
+    return (
+             ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+             ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+           );
+}
+
+
+void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+void NVIC_SystemReset(void)
+{
+    uint16_t reg;
+    uint8_t  dummy_read;
+    /* Use Watch Dog Timer to system reset */
+    
+    /* Set WT/IT bit of WTCSR to 1 = Watch Dog */
+    /* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */
+    reg = (WDT_WTCSR_WRITE | 0x0058);
+    WDTWTCSR = reg;
+    
+    /* Clear Count reg */
+    reg = (WDT_WTCNT_WRITE | 0x0000);
+    WDTWTCNT = reg;
+    
+    /* Clear WOVF flag */
+    dummy_read = WDTWRCSR;
+    reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000));
+    WDTWRCSR = reg;
+    /* Enable Internal Reset */
+    reg = (WDT_WRCSR_RSTE_WRITE | 0x005F);
+    WDTWRCSR = reg;
+    
+    /* Watch Dog start */
+    reg = (WDT_WTCSR_WRITE | 0x0078);
+    WDTWTCSR = reg;
+    
+    while(1);                      /* wait Internal Reset */
+}
+
+/* ##################################    SysTick function  ############################################ */
+uint32_t SysTick_Config(uint32_t ticks)
+{
+    /* Not support this function */
+    /* Use mbed Ticker */
+    return (1);     /* impossible */
+}
+
+
+/* ##################################### Debug In/Output function ########################################### */
+uint32_t ITM_SendChar (uint32_t ch)
+{
+    /* Not support this function */
+    /* Use mbed Serial */
+    return (ch);
+}
+
+
+int32_t ITM_ReceiveChar (void) {
+    /* Not support this function */
+    /* Use mbed Serial */
+    return (-1);    /* no character available */
+}
+
+
+int32_t ITM_CheckChar (void) {
+    /* Not support this function */
+    /* Use mbed Serial */
+    return (0);                                 /* no character available */
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/nvic_wrapper.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,85 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/**************************************************************************//**
+* @file         nvic_wrapper.h
+* $Rev:  $
+* $Date:: $
+* @brief        Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
+******************************************************************************/
+
+#ifndef NVIC_WRAPPER_H
+#define NVIC_WRAPPER_H
+
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+/******************************************************************************
+Variable Externs
+******************************************************************************/
+
+/******************************************************************************
+Functions Prototypes
+******************************************************************************/
+
+/* NVIC functions */
+void     NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+uint32_t NVIC_GetPriorityGrouping(void);
+void     NVIC_EnableIRQ(IRQn_Type IRQn);
+void     NVIC_DisableIRQ(IRQn_Type IRQn);
+uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void     NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void     NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t NVIC_GetActive(IRQn_Type IRQn);
+void     NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
+uint32_t NVIC_GetPriority(IRQn_Type IRQn);
+uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority);
+void     NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+void     NVIC_SystemReset(void);
+/* SysTick function */
+uint32_t SysTick_Config(uint32_t ticks);
+/* Debug In/Output function */
+uint32_t ITM_SendChar (uint32_t ch);
+int32_t  ITM_ReceiveChar (void);
+int32_t  ITM_CheckChar (void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* NVIC_WRAPPER_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/pl310.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,129 @@
+/**************************************************************************//**
+ * @file     pl310.c
+ * @brief    Implementation of PL310 PrimeCell Level 2 Cache Controller functions
+ * @version
+ * @date     3 December 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+#include "VKRZA1H.h"
+
+//Cache Sync operation
+void PL310_Sync(void)
+{
+    PL310->CACHE_SYNC = 0x0;
+}
+
+//return Cache controller cache ID
+int PL310_GetID (void)
+{
+    return PL310->CACHE_ID;
+}
+
+//return Cache controller cache Type
+int PL310_GetType (void)
+{
+    return PL310->CACHE_TYPE;
+}
+
+//Invalidate all cache by way
+void PL310_InvAllByWay (void)
+{
+    unsigned int assoc;
+
+    if (PL310->AUX_CNT & (1<<16))
+        assoc = 16;
+    else
+        assoc =  8;
+
+    PL310->INV_WAY = (1 << assoc) - 1;
+    while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
+
+    PL310_Sync();
+}
+
+//Clean and Invalidate all cache by way
+void PL310_CleanInvAllByWay (void)
+{
+    unsigned int assoc;
+
+    if (PL310->AUX_CNT & (1<<16))
+        assoc = 16;
+    else
+        assoc =  8;
+
+    PL310->CLEAN_INV_WAY = (1 << assoc) - 1;
+    while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
+
+    PL310_Sync();
+}
+
+//Enable Cache
+void PL310_Enable(void)
+{
+    PL310->CONTROL = 0;
+    PL310->INTERRUPT_CLEAR = 0x000001FFuL;
+    PL310->DEBUG_CONTROL = 0;
+    PL310->DATA_LOCK_0_WAY = 0;
+    PL310->CACHE_SYNC = 0;
+
+    PL310->CONTROL = 0x01;
+    PL310_Sync();
+}
+//Disable Cache
+void PL310_Disable(void)
+{
+    PL310->CONTROL = 0x00;
+    PL310_Sync();
+}
+
+//Invalidate cache by physical address
+void PL310_InvPa (void *pa)
+{
+    PL310->INV_LINE_PA = (unsigned int)pa;
+    PL310_Sync();
+}
+
+//Clean cache by physical address
+void PL310_CleanPa (void *pa)
+{
+    PL310->CLEAN_LINE_PA = (unsigned int)pa;
+    PL310_Sync();
+}
+
+//Clean and invalidate cache by physical address
+void PL310_CleanInvPa (void *pa)
+{
+    PL310->CLEAN_INV_LINE_PA = (unsigned int)pa;
+    PL310_Sync();
+}
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/pl310.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,115 @@
+/**************************************************************************//**
+ * @file     pl310.h
+ * @brief    Implementation of pl310 functions
+ * @version
+ * @date     11 June 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#ifndef __PL310
+#define __PL310
+
+typedef struct
+{
+  __I  uint32_t CACHE_ID;                   /*!< Offset: 0x0000   Cache ID Register               */
+  __I  uint32_t CACHE_TYPE;                 /*!< Offset: 0x0004   Cache Type Register             */
+       uint32_t RESERVED0[0x3e];
+  __IO uint32_t CONTROL;                    /*!< Offset: 0x0100   Control Register                */
+  __IO uint32_t AUX_CNT;                    /*!< Offset: 0x0104   Auxiliary Control               */
+       uint32_t RESERVED1[0x3e];
+  __IO uint32_t EVENT_CONTROL;              /*!< Offset: 0x0200   Event Counter Control           */
+  __IO uint32_t EVENT_COUNTER1_CONF;        /*!< Offset: 0x0204   Event Counter 1 Configuration   */
+  __IO uint32_t EVENT_COUNTER0_CONF;        /*!< Offset: 0x0208   Event Counter 1 Configuration   */
+       uint32_t RESERVED2[0x2];
+  __IO uint32_t INTERRUPT_MASK;             /*!< Offset: 0x0214   Interrupt Mask                  */
+  __I  uint32_t MASKED_INT_STATUS;          /*!< Offset: 0x0218   Masked Interrupt Status         */
+  __I  uint32_t RAW_INT_STATUS;             /*!< Offset: 0x021c   Raw Interrupt Status            */
+  __O  uint32_t INTERRUPT_CLEAR;            /*!< Offset: 0x0220   Interrupt Clear                 */
+       uint32_t RESERVED3[0x143];
+  __IO uint32_t CACHE_SYNC;                 /*!< Offset: 0x0730   Cache Sync                      */
+       uint32_t RESERVED4[0xf];
+  __IO uint32_t INV_LINE_PA;                /*!< Offset: 0x0770   Invalidate Line By PA           */
+       uint32_t RESERVED6[2];
+  __IO uint32_t INV_WAY;                    /*!< Offset: 0x077c   Invalidate by Way               */
+       uint32_t RESERVED5[0xc];
+  __IO uint32_t CLEAN_LINE_PA;              /*!< Offset: 0x07b0   Clean Line by PA                */
+       uint32_t RESERVED7[1];
+  __IO uint32_t CLEAN_LINE_INDEX_WAY;       /*!< Offset: 0x07b8   Clean Line by Index/Way         */
+  __IO uint32_t CLEAN_WAY;                  /*!< Offset: 0x07bc   Clean by Way                    */
+       uint32_t RESERVED8[0xc];
+  __IO uint32_t CLEAN_INV_LINE_PA;          /*!< Offset: 0x07f0   Clean and Invalidate Line by PA  */
+       uint32_t RESERVED9[1];
+  __IO uint32_t CLEAN_INV_LINE_INDEX_WAY;   /*!< Offset: 0x07f8   Clean and Invalidate Line by Index/Way  */
+  __IO uint32_t CLEAN_INV_WAY;              /*!< Offset: 0x07fc   Clean and Invalidate by Way     */
+       uint32_t RESERVED10[0x40];
+  __IO uint32_t DATA_LOCK_0_WAY;            /*!< Offset: 0x0900   Data Lockdown 0 by Way          */
+  __IO uint32_t INST_LOCK_0_WAY;            /*!< Offset: 0x0904   Instruction Lockdown 0 by Way   */
+  __IO uint32_t DATA_LOCK_1_WAY;            /*!< Offset: 0x0908   Data Lockdown 1 by Way          */
+  __IO uint32_t INST_LOCK_1_WAY;            /*!< Offset: 0x090c   Instruction Lockdown 1 by Way   */
+  __IO uint32_t DATA_LOCK_2_WAY;            /*!< Offset: 0x0910   Data Lockdown 2 by Way          */
+  __IO uint32_t INST_LOCK_2_WAY;            /*!< Offset: 0x0914   Instruction Lockdown 2 by Way   */
+  __IO uint32_t DATA_LOCK_3_WAY;            /*!< Offset: 0x0918   Data Lockdown 3 by Way          */
+  __IO uint32_t INST_LOCK_3_WAY;            /*!< Offset: 0x091c   Instruction Lockdown 3 by Way   */
+  __IO uint32_t DATA_LOCK_4_WAY;            /*!< Offset: 0x0920   Data Lockdown 4 by Way          */
+  __IO uint32_t INST_LOCK_4_WAY;            /*!< Offset: 0x0924   Instruction Lockdown 4 by Way   */
+  __IO uint32_t DATA_LOCK_5_WAY;            /*!< Offset: 0x0928   Data Lockdown 5 by Way          */
+  __IO uint32_t INST_LOCK_5_WAY;            /*!< Offset: 0x092c   Instruction Lockdown 5 by Way   */
+  __IO uint32_t DATA_LOCK_6_WAY;            /*!< Offset: 0x0930   Data Lockdown 5 by Way          */
+  __IO uint32_t INST_LOCK_6_WAY;            /*!< Offset: 0x0934   Instruction Lockdown 5 by Way   */
+  __IO uint32_t DATA_LOCK_7_WAY;            /*!< Offset: 0x0938   Data Lockdown 6 by Way          */
+  __IO uint32_t INST_LOCK_7_WAY;            /*!< Offset: 0x093c   Instruction Lockdown 6 by Way   */
+       uint32_t RESERVED11[0x4];
+  __IO uint32_t LOCK_LINE_EN;               /*!< Offset: 0x0950   Lockdown by Line Enable         */
+  __IO uint32_t UNLOCK_ALL_BY_WAY;          /*!< Offset: 0x0954   Unlock All Lines by Way         */
+       uint32_t RESERVED12[0xaa];
+  __IO uint32_t ADDRESS_FILTER_START;       /*!< Offset: 0x0c00   Address Filtering Start         */
+  __IO uint32_t ADDRESS_FILTER_END;         /*!< Offset: 0x0c04   Address Filtering End           */
+       uint32_t RESERVED13[0xce];
+  __IO uint32_t DEBUG_CONTROL;              /*!< Offset: 0x0f40   Debug Control Register          */
+
+} PL310_TypeDef;
+
+#define PL310           ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */
+
+extern int PL310_GetID (void);
+extern int PL310_GetType (void);
+extern void PL310_InvAllByWay (void);
+extern void PL310_CleanInvAllByWay(void);
+extern void PL310_Enable(void);
+extern void PL310_Disable(void);
+extern void PL310_InvPa (void *);
+extern void PL310_CleanPa (void *);
+extern void PL310_CleanInvPa (void *);
+
+#endif
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/r_typedefs.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,62 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2013 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : r_typedefs.h
+* $Rev: 788 $
+* $Date:: 2014-04-07 18:57:13 +0900#$
+* Description : basic type definition
+******************************************************************************/
+#ifndef R_TYPEDEFS_H
+#define R_TYPEDEFS_H
+
+/******************************************************************************
+Includes <System Includes> , "Project Includes"
+******************************************************************************/
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#if defined(__ARM_NEON__)
+
+#include <arm_neon.h>
+
+#else /* __ARM_NEON__ */
+
+typedef float               float32_t;
+typedef double              float64_t;
+
+#endif /* __ARM_NEON__ */
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+typedef char                char_t;
+typedef int                 bool_t;
+typedef int                 int_t;
+typedef long double         float128_t;
+typedef signed long         long_t;
+typedef unsigned long       ulong_t;
+
+#endif /* R_TYPEDEFS_H */
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/rza_io_regrw.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,201 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name   : rza_io_regrw.c
+* $Rev: 1121 $
+* $Date:: 2014-08-06 17:09:53 +0900#$
+* Description : Low level register read/write
+*******************************************************************************/
+
+/******************************************************************************
+Includes   <System Includes> , "Project Includes"
+******************************************************************************/
+#include "r_typedefs.h"
+
+#ifdef __CC_ARM
+#pragma arm section code   = "CODE_IO_REGRW"
+#pragma arm section rodata = "CONST_IO_REGRW"
+#pragma arm section rwdata = "DATA_IO_REGRW"
+#pragma arm section zidata = "BSS_IO_REGRW"
+#endif
+
+/******************************************************************************
+Typedef definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Macro definitions
+******************************************************************************/
+
+
+/******************************************************************************
+Imported global variables and functions (from other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+******************************************************************************/
+
+
+/******************************************************************************
+Private global variables and functions
+******************************************************************************/
+
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_8
+* Description  : IO register 8-bit write
+* Arguments    : volatile uint8_t * ioreg : IO register for writing
+*              :                          : Use register definition name of the
+*              :                          : iodefine.h
+*              : uint8_t write_value      : Write value for the IO register
+*              : uint8_t shift            : The number of left shifts to the 
+*              :                          : target bit
+*              : uint8_t mask             : Mask value for the IO register
+*              :                          : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_8(volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask)
+{
+    uint8_t reg_value;
+
+    reg_value = *ioreg;                                         /* Read from register */
+    reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value       */
+    *ioreg    = reg_value;                                      /* Write to register  */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_16
+* Description  : IO register 16-bit write
+* Arguments    : volatile uint16_t * ioreg : IO register for writing
+*              :                           : Use register definition name of the
+*              :                           : iodefine.h
+*              : uint16_t write_value      : Write value for the IO register
+*              : uint16_t shift            : The number of left shifts to the 
+*              :                           : target bit
+*              : uint16_t mask             : Mask value for the IO register
+*              :                           : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask)
+{
+    uint16_t reg_value;
+
+    reg_value = *ioreg;                                         /* Read from register */
+    reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value       */
+    *ioreg    = reg_value;                                      /* Write to register  */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegWrite_32
+* Description  : IO register 32-bit write
+* Arguments    : volatile uint32_t * ioreg : IO register for writing
+*              :                           : Use register definition name of the
+*              :                           : iodefine.h
+*              : uint32_t write_value      : Write value for the IO register
+*              : uint32_t shift            : The number of left shifts to the 
+*              :                           : target bit
+*              : uint32_t mask             : Mask value for the IO register
+*              :                           : (Target bit : "1")
+* Return Value : None
+******************************************************************************/
+void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask)
+{
+    uint32_t reg_value;
+
+    reg_value = *ioreg;                                         /* Read from register */
+    reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value       */
+    *ioreg    = reg_value;                                      /* Write to register  */
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_8
+* Description  : IO register 8-bit read
+* Arguments    : volatile uint8_t * ioreg : IO register for reading
+*              :                          : Use register definition name of the 
+*              :                          : iodefine.h
+*              : uint8_t shift            : The number of right shifts to the 
+*              :                          : target bit
+*              : uint8_t mask             : Mask bit for the IO register
+*              :                          : (Target bit: "1")
+* Return Value : uint8_t : Value of the obtained target bit
+******************************************************************************/
+uint8_t RZA_IO_RegRead_8(volatile uint8_t * ioreg, uint8_t shift, uint8_t mask)
+{
+    uint8_t reg_value;
+
+    reg_value = *ioreg;                         /* Read from register            */
+    reg_value = (reg_value & mask) >> shift;    /* Clear other bit and Bit shift */
+
+    return reg_value;
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_16
+* Description  : IO register 16-bit read
+* Arguments    : volatile uint16_t * ioreg : IO register for reading
+*              :                           : Use register definition name of the 
+*              :                           : iodefine.h
+*              : uint16_t shift            : The number of right shifts to the 
+*              :                           : target bit
+*              : uint16_t mask             : Mask bit for the IO register
+*              :                           : (Target bit: "1")
+* Return Value : uint16_t : Value of the obtained target bit
+******************************************************************************/
+uint16_t RZA_IO_RegRead_16(volatile uint16_t * ioreg, uint16_t shift, uint16_t mask)
+{
+    uint16_t reg_value;
+
+    reg_value = *ioreg;                         /* Read from register            */
+    reg_value = (reg_value & mask) >> shift;    /* Clear other bit and Bit shift */
+
+    return reg_value;
+}
+
+/******************************************************************************
+* Function Name: RZA_IO_RegRead_32
+* Description  : IO register 32-bit read
+* Arguments    : volatile uint32_t * ioreg : IO register for reading
+*              :                           : Use register definition name of the 
+*              :                           : iodefine.h
+*              : uint32_t shift            : The number of right shifts to the 
+*              :                           : target bit
+*              : uint32_t mask             : Mask bit for the IO register
+*              :                           : (Target bit: "1")
+* Return Value : uint32_t : Value of the obtained target bit
+******************************************************************************/
+uint32_t RZA_IO_RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask)
+{
+    uint32_t reg_value;
+
+    reg_value = *ioreg;                         /* Read from register            */
+    reg_value = (reg_value & mask) >> shift;    /* Clear other bit and Bit shift */
+
+    return reg_value;
+}
+
+
+/* End of File */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,522 @@
+/**************************************************************************//**
+ * @file     system_VKRZA1H.c
+ * @brief    CMSIS Device System Source File for
+ *           ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     09 January 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#include <stdint.h>
+#include "VKRZA1H.h"
+#include "RZ_A1_Init.h"
+
+
+#if defined(__ARMCC_VERSION)
+extern void $Super$$main(void);
+__asm void FPUEnable(void);
+#else 
+void FPUEnable(void); 
+
+#endif
+
+#define FRQCR_IFC_MSK          (0x0030)
+#define FRQCR_IFC_SHFT         (8)
+#define FRQCR_IFC_1P1          (0) /* x1/1 */
+#define FRQCR_IFC_2P3          (1) /* x2/3 */
+#define FRQCR_IFC_1P3          (3) /* x1/3 */
+
+uint32_t IRQNestLevel;
+unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
+uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the cache.
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
+ */
+#if defined(__ARMCC_VERSION)
+#pragma push
+#pragma arm
+
+void InitMemorySubsystem(void) {
+
+    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
+     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
+     * You are not required to invalidate the main TLB, even though it is recommended for safety
+     * reasons. This ensures compatibility with future revisions of the processor. */
+
+    unsigned int l2_id;
+
+    /* Invalidate undefined data */
+    __ca9u_inv_tlb_all();
+    __v7_inv_icache_all();
+    __v7_inv_dcache_all();
+    __v7_inv_btac();
+
+    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
+     * invalidate in order to flush the valid data to the next level cache.
+     */
+    __enable_mmu();
+
+    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
+    __enable_caches();
+    __enable_btac();
+
+    /* If present, you may also need to Invalidate and Enable L2 cache here */
+    l2_id = PL310_GetID();
+    if (l2_id)
+    {
+       PL310_InvAllByWay();
+       PL310_Enable();
+    }
+}
+#pragma pop
+
+#elif defined(__GNUC__) 
+
+void InitMemorySubsystem(void) { 
+ 
+    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before 
+     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. 
+     * You are not required to invalidate the main TLB, even though it is recommended for safety 
+     * reasons. This ensures compatibility with future revisions of the processor. */ 
+ 
+    unsigned int l2_id; 
+ 
+    /* Invalidate undefined data */ 
+    __ca9u_inv_tlb_all(); 
+    __v7_inv_icache_all(); 
+    __v7_inv_dcache_all(); 
+    __v7_inv_btac(); 
+ 
+    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and 
+     * invalidate in order to flush the valid data to the next level cache. 
+     */ 
+    __enable_mmu(); 
+ 
+    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ 
+    __enable_caches(); 
+    __enable_btac(); 
+ 
+    /* If present, you may also need to Invalidate and Enable L2 cache here */ 
+    l2_id = PL310_GetID(); 
+    if (l2_id) 
+    { 
+       PL310_InvAllByWay(); 
+       PL310_Enable(); 
+    } 
+} 
+#elif defined ( __ICCARM__ )
+
+void InitMemorySubsystem(void) { 
+ 
+    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before 
+     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. 
+     * You are not required to invalidate the main TLB, even though it is recommended for safety 
+     * reasons. This ensures compatibility with future revisions of the processor. */ 
+ 
+    unsigned int l2_id; 
+ 
+    /* Invalidate undefined data */ 
+    __ca9u_inv_tlb_all(); 
+    __v7_inv_icache_all(); 
+    __v7_inv_dcache_all(); 
+    __v7_inv_btac(); 
+ 
+    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and 
+     * invalidate in order to flush the valid data to the next level cache. 
+     */ 
+    __enable_mmu();
+ 
+    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ 
+    __enable_caches(); 
+    __enable_btac(); 
+ 
+    /* If present, you may also need to Invalidate and Enable L2 cache here */ 
+    l2_id = PL310_GetID(); 
+    if (l2_id) 
+    { 
+       PL310_InvAllByWay(); 
+       PL310_Enable(); 
+    } 
+} 
+#else 
+
+#endif 
+
+
+IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
+
+uint32_t IRQCount = sizeof IRQTable / 4;
+
+uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
+{
+    if (irq < IRQCount) {
+        IRQTable[irq] = handler;
+        return 0;
+    }
+    else {
+        return 1;
+    }
+}
+
+uint32_t InterruptHandlerUnregister (IRQn_Type irq)
+{
+    if (irq < IRQCount) {
+        IRQTable[irq] = 0;
+        return 0;
+    }
+    else {
+        return 1;
+    }
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock.
+ */
+void SystemCoreClockUpdate (void)
+{
+    uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
+
+    switch (frqcr_ifc) {
+        case FRQCR_IFC_1P1:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
+            break;
+        case FRQCR_IFC_2P3:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
+            break;
+        case FRQCR_IFC_1P3:
+            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK  / 3;
+            break;
+        default:
+            /* do nothing */
+            break;
+    }
+}
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+    IRQNestLevel = 0;
+/*       do not use global variables because this function is called before
+         reaching pre-main. RW section maybe overwritten afterwards.          */
+    RZ_A1_InitClock();
+    RZ_A1_InitBus();
+
+	//Configure GIC ICDICFR GIC_SetICDICFR()
+    GIC_Enable();
+    __enable_irq();
+
+}
+
+
+//Fault Status Register (IFSR/DFSR) definitions
+#define FSR_ALIGNMENT_FAULT                  0x01   //DFSR only. Fault on first lookup
+#define FSR_INSTRUCTION_CACHE_MAINTENANCE    0x04   //DFSR only - async/external
+#define FSR_SYNC_EXT_TTB_WALK_FIRST          0x0c   //sync/external
+#define FSR_SYNC_EXT_TTB_WALK_SECOND         0x0e   //sync/external
+#define FSR_SYNC_PARITY_TTB_WALK_FIRST       0x1c   //sync/external
+#define FSR_SYNC_PARITY_TTB_WALK_SECOND      0x1e   //sync/external
+#define FSR_TRANSLATION_FAULT_FIRST          0x05   //MMU Fault - internal
+#define FSR_TRANSLATION_FAULT_SECOND         0x07   //MMU Fault - internal
+#define FSR_ACCESS_FLAG_FAULT_FIRST          0x03   //MMU Fault - internal
+#define FSR_ACCESS_FLAG_FAULT_SECOND         0x06   //MMU Fault - internal
+#define FSR_DOMAIN_FAULT_FIRST               0x09   //MMU Fault - internal
+#define FSR_DOMAIN_FAULT_SECOND              0x0b   //MMU Fault - internal
+#define FSR_PERMISION_FAULT_FIRST            0x0f   //MMU Fault - internal
+#define FSR_PERMISION_FAULT_SECOND           0x0d   //MMU Fault - internal
+#define FSR_DEBUG_EVENT                      0x02   //internal
+#define FSR_SYNC_EXT_ABORT                   0x08   //sync/external
+#define FSR_TLB_CONFLICT_ABORT               0x10   //sync/external
+#define FSR_LOCKDOWN                         0x14   //internal
+#define FSR_COPROCESSOR_ABORT                0x1a   //internal
+#define FSR_SYNC_PARITY_ERROR                0x19   //sync/external
+#define FSR_ASYNC_EXTERNAL_ABORT             0x16   //DFSR only - async/external
+#define FSR_ASYNC_PARITY_ERROR               0x18   //DFSR only - async/external
+
+void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
+    uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
+
+    switch(FS) {
+        //Synchronous parity errors - retry
+        case FSR_SYNC_PARITY_ERROR:
+        case FSR_SYNC_PARITY_TTB_WALK_FIRST:
+        case FSR_SYNC_PARITY_TTB_WALK_SECOND:
+            return;
+
+        //Your code here. Value in DFAR is invalid for some fault statuses.
+        case FSR_ALIGNMENT_FAULT:
+        case FSR_INSTRUCTION_CACHE_MAINTENANCE:
+        case FSR_SYNC_EXT_TTB_WALK_FIRST:
+        case FSR_SYNC_EXT_TTB_WALK_SECOND:
+        case FSR_TRANSLATION_FAULT_FIRST:
+        case FSR_TRANSLATION_FAULT_SECOND:
+        case FSR_ACCESS_FLAG_FAULT_FIRST:
+        case FSR_ACCESS_FLAG_FAULT_SECOND:
+        case FSR_DOMAIN_FAULT_FIRST:
+        case FSR_DOMAIN_FAULT_SECOND:
+        case FSR_PERMISION_FAULT_FIRST:
+        case FSR_PERMISION_FAULT_SECOND:
+        case FSR_DEBUG_EVENT:
+        case FSR_SYNC_EXT_ABORT:
+        case FSR_TLB_CONFLICT_ABORT:
+        case FSR_LOCKDOWN:
+        case FSR_COPROCESSOR_ABORT:
+        case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
+        case FSR_ASYNC_PARITY_ERROR:   //DFAR invalid
+        default:
+            while(1);
+    }
+}
+
+void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
+    uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
+
+    switch(FS) {
+        //Synchronous parity errors - retry
+        case FSR_SYNC_PARITY_ERROR:
+        case FSR_SYNC_PARITY_TTB_WALK_FIRST:
+        case FSR_SYNC_PARITY_TTB_WALK_SECOND:
+            return;
+
+        //Your code here. Value in IFAR is invalid for some fault statuses.
+        case FSR_SYNC_EXT_TTB_WALK_FIRST:
+        case FSR_SYNC_EXT_TTB_WALK_SECOND:
+        case FSR_TRANSLATION_FAULT_FIRST:
+        case FSR_TRANSLATION_FAULT_SECOND:
+        case FSR_ACCESS_FLAG_FAULT_FIRST:
+        case FSR_ACCESS_FLAG_FAULT_SECOND:
+        case FSR_DOMAIN_FAULT_FIRST:
+        case FSR_DOMAIN_FAULT_SECOND:
+        case FSR_PERMISION_FAULT_FIRST:
+        case FSR_PERMISION_FAULT_SECOND:
+        case FSR_DEBUG_EVENT: //IFAR invalid
+        case FSR_SYNC_EXT_ABORT:
+        case FSR_TLB_CONFLICT_ABORT:
+        case FSR_LOCKDOWN:
+        case FSR_COPROCESSOR_ABORT:
+        default:
+            while(1);
+    }
+}
+
+//returns amount to decrement lr by
+//this will be 0 when we have emulated the instruction and want to execute the next instruction
+//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
+//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
+uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
+    const unsigned int THUMB = 2;
+    const unsigned int ARM = 4;
+    //Lazy VFP/NEON initialisation and switching
+
+    // (ARM ARM section A7.5) VFP data processing instruction?
+    // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
+    // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
+    // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
+    if ((state == ARM   && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
+        (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
+        if (((opcode & 0x00000E00) >> 9) == 5) {
+            FPUEnable();
+            return state;
+        }
+    }
+
+    // (ARM ARM section A7.4) NEON data processing instruction?
+    if ((state == ARM   && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
+        (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
+    // (ARM ARM section A7.7) NEON load/store instruction?
+        (state == ARM   && ((opcode >> 24) == 0xF4)) ||
+        (state == THUMB && ((opcode >> 24) == 0xF9))) {
+        FPUEnable();
+        return state;
+    }
+
+    //Add code here for other Undef cases
+    while(1);
+}
+
+#if defined(__ARMCC_VERSION)
+#pragma push
+#pragma arm
+//Critical section, called from undef handler, so systick is disabled
+__asm void FPUEnable(void) {
+        ARM
+
+        //Permit access to VFP/NEON, registers by modifying CPACR
+        MRC     p15,0,R1,c1,c0,2
+        ORR     R1,R1,#0x00F00000
+        MCR     p15,0,R1,c1,c0,2
+
+        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+        ISB
+
+        //Enable VFP/NEON
+        VMRS    R1,FPEXC
+        ORR     R1,R1,#0x40000000
+        VMSR    FPEXC,R1
+
+        //Initialise VFP/NEON registers to 0
+        MOV     R2,#0
+        //Initialise D16 registers to 0
+        VMOV    D0, R2,R2
+        VMOV    D1, R2,R2
+        VMOV    D2, R2,R2
+        VMOV    D3, R2,R2
+        VMOV    D4, R2,R2
+        VMOV    D5, R2,R2
+        VMOV    D6, R2,R2
+        VMOV    D7, R2,R2
+        VMOV    D8, R2,R2
+        VMOV    D9, R2,R2
+        VMOV    D10,R2,R2
+        VMOV    D11,R2,R2
+        VMOV    D12,R2,R2
+        VMOV    D13,R2,R2
+        VMOV    D14,R2,R2
+        VMOV    D15,R2,R2
+        //Initialise D32 registers to 0
+        VMOV    D16,R2,R2
+        VMOV    D17,R2,R2
+        VMOV    D18,R2,R2
+        VMOV    D19,R2,R2
+        VMOV    D20,R2,R2
+        VMOV    D21,R2,R2
+        VMOV    D22,R2,R2
+        VMOV    D23,R2,R2
+        VMOV    D24,R2,R2
+        VMOV    D25,R2,R2
+        VMOV    D26,R2,R2
+        VMOV    D27,R2,R2
+        VMOV    D28,R2,R2
+        VMOV    D29,R2,R2
+        VMOV    D30,R2,R2
+        VMOV    D31,R2,R2
+        //Initialise FPSCR to a known state
+        VMRS    R2,FPSCR
+        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+        AND     R2,R2,R3
+        VMSR    FPSCR,R2
+
+        BX      LR
+}
+#pragma pop
+
+#elif defined(__GNUC__)
+void FPUEnable(void) {
+    __asm__ (
+        ".ARM;"
+
+        //Permit access to VFP/NEON, registers by modifying CPACR
+        "MRC     p15,0,R1,c1,c0,2;"
+        "ORR     R1,R1,#0x00F00000;"
+        "MCR     p15,0,R1,c1,c0,2;"
+
+        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
+        "ISB;"
+
+        //Enable VFP/NEON
+        "VMRS    R1,FPEXC;"
+        "ORR     R1,R1,#0x40000000;"
+        "VMSR    FPEXC,R1;"
+
+        //Initialise VFP/NEON registers to 0
+        "MOV     R2,#0;"
+        //Initialise D16 registers to 0
+        "VMOV    D0, R2,R2;"
+        "VMOV    D1, R2,R2;"
+        "VMOV    D2, R2,R2;"
+        "VMOV    D3, R2,R2;"
+        "VMOV    D4, R2,R2;"
+        "VMOV    D5, R2,R2;"
+        "VMOV    D6, R2,R2;"
+        "VMOV    D7, R2,R2;"
+        "VMOV    D8, R2,R2;"
+        "VMOV    D9, R2,R2;"
+        "VMOV    D10,R2,R2;"
+        "VMOV    D11,R2,R2;"
+        "VMOV    D12,R2,R2;"
+        "VMOV    D13,R2,R2;"
+        "VMOV    D14,R2,R2;"
+        "VMOV    D15,R2,R2;"
+        //Initialise D32 registers to 0
+        "VMOV    D16,R2,R2;"
+        "VMOV    D17,R2,R2;"
+        "VMOV    D18,R2,R2;"
+        "VMOV    D19,R2,R2;"
+        "VMOV    D20,R2,R2;"
+        "VMOV    D21,R2,R2;"
+        "VMOV    D22,R2,R2;"
+        "VMOV    D23,R2,R2;"
+        "VMOV    D24,R2,R2;"
+        "VMOV    D25,R2,R2;"
+        "VMOV    D26,R2,R2;"
+        "VMOV    D27,R2,R2;"
+        "VMOV    D28,R2,R2;"
+        "VMOV    D29,R2,R2;"
+        "VMOV    D30,R2,R2;"
+        "VMOV    D31,R2,R2;"
+
+        //Initialise FPSCR to a known state
+        "VMRS    R2,FPSCR;"
+        "LDR     R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
+        "AND     R2,R2,R3;"
+        "VMSR    FPSCR,R2;"
+
+        //"BX      LR;"
+             :
+             :
+             :"r1", "r2", "r3");
+    return;
+}
+#else
+#endif
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,68 @@
+/**************************************************************************//**
+ * @file     system_VKRZA1H.h
+ * @brief    CMSIS Device System Header File for
+ *           ARMCA9 Device Series
+ * @version  V1.00
+ * @date     11 June 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __SYSTEM_VKRZA1H
+#define __SYSTEM_VKRZA1H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+typedef void(*IRQHandler)();
+uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
+uint32_t InterruptHandlerUnregister(IRQn_Type);
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the Systd short        int16_t;emCoreClock variable.
+ */
+extern void SystemInit (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_VKRZA1H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/arm_common_tables.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/arm_const_structs.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/arm_math.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,7557 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_math.h
+*
+* Description:	Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+   * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+   * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 5.14.0.0
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvprojx
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+   * ARM_MATH_CM7 for building the library on cortex-M7.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   * 
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   * 
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+  #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+  #elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+  #define ARM_MATH_CM0_FAMILY
+#else
+  #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31	   0x400000
+#define TABLE_SPACING_Q15	   0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+  #define __SIMD32_TYPE int32_t __packed
+  #define CMSIS_UNUSED
+#elif defined __GNUC__
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__			/* Cosmic */
+  #define __SIMD32_TYPE int32_t
+  #define CMSIS_UNUSED
+#elif defined __TASKING__
+  #define __SIMD32_TYPE __unaligned int32_t
+  #define CMSIS_UNUSED
+#else
+  #error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+//#define __CLZ __clz
+//#endif
+
+//note: function can be removed when all toolchain support __CLZ for Cortex-M0
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__))  )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+      ((q15_t) x * (q15_t) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f64;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15, complex,  matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Q31, complex, matrix multiplication.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_cmplx_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		 *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q15;
+
+void arm_cfft_q15( 
+    const arm_cfft_instance_q15 * S, 
+    q15_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+
+  /**
+   * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_q31;
+
+void arm_cfft_q31( 
+    const arm_cfft_instance_q31 * S, 
+    q31_t * p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);  
+  
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f64;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_stereo_df2T_f32(
+  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f64(
+  const arm_biquad_cascade_df2T_instance_f64 * S,
+  float64_t * pSrc,
+  float64_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_stereo_df2T_init_f32(
+  arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f64(
+  arm_biquad_cascade_df2T_instance_f64 * S,
+  uint8_t numStages,
+  float64_t * pCoeffs,
+  float64_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f64(
+  const arm_matrix_instance_f64 * src,
+  arm_matrix_instance_f64 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in >= 0.0f)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+   
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("push")         \
+         _Pragma ("O1")
+    #else
+      #define LOW_OPTIMIZATION_ENTER 
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_EXIT \
+         _Pragma ("pop")
+    #else
+      #define LOW_OPTIMIZATION_EXIT  
+    #endif
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+    #ifdef ARM_MATH_CM4
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+         _Pragma ("optimize=low")
+    #else
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+    #endif
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)		// Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)		// TASKING
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_ca9.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,277 @@
+/**************************************************************************//**
+ * @file     core_ca9.h
+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version
+ * @date     25 March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CA9_H_GENERIC
+#define __CORE_CA9_H_GENERIC
+
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_A9
+  @{
+ */
+
+/*  CMSIS CA9 definitions */
+#define __CA9_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CA9_CMSIS_VERSION_SUB   (0x10)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CA9_CMSIS_VERSION       ((__CA9_CMSIS_VERSION_MAIN << 16) | \
+                                    __CA9_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_A                (0x09)                                   /*!< Cortex-A Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+  #define __STATIC_ASM     static __asm
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+  #define __STATIC_ASM     static __asm
+
+#include <stdint.h>
+inline uint32_t __get_PSR(void) {
+	__ASM("mrs r0, cpsr");
+}
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+  #define __STATIC_ASM     static __asm
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+  #define __STATIC_ASM     static __asm
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+  #define __STATIC_ASM     static __asm
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /*!< standard types definitions                      */
+#include "core_caInstr.h"                /*!< Core Instruction Access                         */
+#include "core_caFunc.h"                 /*!< Core Function Access                            */
+#include "core_cm4_simd.h"               /*!< Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CA9_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CA9_H_DEPENDANT
+#define __CORE_CA9_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CA9_REV
+    #define __CA9_REV               0x0000
+    #warning "__CA9_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             1
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    1
+  #endif
+
+  #if __Vendor_SysTickConfig == 0
+    #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_A9 */
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-A processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t reserved1:7;                /*!< bit: 20..23  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */ 
+} APSR_Type;
+
+
+/*@} end of group CMSIS_CORE */
+
+/*@} end of CMSIS_Core_FPUFunctions */
+
+
+#endif /* __CORE_CA9_H_GENERIC */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_caFunc.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1428 @@
+/**************************************************************************//**
+ * @file     core_caFunc.h
+ * @brief    CMSIS Cortex-A Core Function Access Header File
+ * @version  V3.10
+ * @date     30 Oct 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CAFUNC_H__
+#define __CORE_CAFUNC_H__
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+#define MODE_USR 0x10
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_MON 0x16
+#define MODE_ABT 0x17
+#define MODE_HYP 0x1A
+#define MODE_UND 0x1B
+#define MODE_SYS 0x1F
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get CPSR Register
+
+    This function returns the content of the CPSR Register.
+
+    \return               CPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_CPSR(void)
+{
+  register uint32_t __regCPSR          __ASM("cpsr");
+  return(__regCPSR);
+}
+
+/** \brief  Set Stack Pointer
+
+    This function assigns the given value to the current stack pointer.
+
+    \param [in]    topOfStack  Stack Pointer value to set
+ */
+register uint32_t __regSP              __ASM("sp");
+__STATIC_INLINE void __set_SP(uint32_t topOfStack)
+{
+    __regSP = topOfStack;
+}
+
+
+/** \brief  Get link register
+
+    This function returns the value of the link register
+
+    \return    Value of link register
+ */
+register uint32_t __reglr         __ASM("lr");
+__STATIC_INLINE uint32_t __get_LR(void)
+{
+  return(__reglr);
+}
+
+/** \brief  Set link register
+
+    This function sets the value of the link register
+
+    \param [in]    lr  LR value to set
+ */
+__STATIC_INLINE void __set_LR(uint32_t lr)
+{
+  __reglr = lr;
+}
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
+{
+    ARM
+    PRESERVE8
+
+    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned
+    MRS     R1, CPSR
+    CPS     #MODE_SYS   ;no effect in USR mode
+    MOV     SP, R0
+    MSR     CPSR_c, R1  ;no effect in USR mode
+    ISB
+    BX      LR
+
+}
+
+/** \brief  Set User Mode
+
+    This function changes the processor state to User Mode
+ */
+__STATIC_ASM void __set_CPS_USR(void)
+{
+    ARM 
+
+    CPS  #MODE_USR  
+    BX   LR
+}
+
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+/** \brief  Get FPEXC
+
+    This function returns the current value of the Floating Point Exception Control register.
+
+    \return               Floating Point Exception Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  return(__regfpexc);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPEXC
+
+    This function assigns the given value to the Floating Point Exception Control register.
+
+    \param [in]    fpscr  Floating Point Exception Control value to set
+ */
+__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpexc         __ASM("fpexc");
+  __regfpexc = (fpexc);
+#endif
+}
+
+/** \brief  Get CPACR
+
+    This function returns the current value of the Coprocessor Access Control register.
+
+    \return               Coprocessor Access Control register value
+ */
+__STATIC_INLINE uint32_t __get_CPACR(void)
+{
+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+    return __regCPACR;
+}
+
+/** \brief  Set CPACR
+
+    This function assigns the given value to the Coprocessor Access Control register.
+
+    \param [in]    cpacr  Coprocessor Acccess Control value to set
+ */
+__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
+{
+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+    __regCPACR = cpacr;
+    __ISB();
+}
+
+/** \brief  Get CBAR
+
+    This function returns the value of the Configuration Base Address register.
+
+    \return               Configuration Base Address register value
+ */
+__STATIC_INLINE uint32_t __get_CBAR() {
+    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
+    return(__regCBAR);
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__STATIC_INLINE uint32_t __get_TTBR0() {
+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+    return(__regTTBR0);
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+    __regTTBR0 = ttbr0;
+    __ISB();
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__STATIC_INLINE uint32_t __get_DACR() {
+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+    return(__regDACR);
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__STATIC_INLINE void __set_DACR(uint32_t dacr) {
+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+    __regDACR = dacr;
+    __ISB();
+}
+
+/******************************** Cache and BTAC enable  ****************************************************/
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
+{
+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+    __regSCTLR = sctlr;
+}
+
+/** \brief  Get SCTLR
+
+    This function returns the value of the System Control Register.
+
+    \return               System Control Register value
+ */
+__STATIC_INLINE uint32_t __get_SCTLR() {
+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+    return(__regSCTLR);
+}
+
+/** \brief  Enable Caches
+
+    Enable Caches
+ */
+__STATIC_INLINE void __enable_caches(void) {
+    // Set I bit 12 to enable I Cache
+    // Set C bit  2 to enable D Cache
+    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
+}
+
+/** \brief  Disable Caches
+
+    Disable Caches
+ */
+__STATIC_INLINE void __disable_caches(void) {
+    // Clear I bit 12 to disable I Cache
+    // Clear C bit  2 to disable D Cache
+    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
+    __ISB();
+}
+
+/** \brief  Enable BTAC
+
+    Enable BTAC
+ */
+__STATIC_INLINE void __enable_btac(void) {
+    // Set Z bit 11 to enable branch prediction
+    __set_SCTLR( __get_SCTLR() | (1 << 11));
+    __ISB();
+}
+
+/** \brief  Disable BTAC
+
+    Disable BTAC
+ */
+__STATIC_INLINE void __disable_btac(void) {
+    // Clear Z bit 11 to disable branch prediction
+    __set_SCTLR( __get_SCTLR() & ~(1 << 11));
+}
+
+
+/** \brief  Enable MMU
+
+    Enable MMU
+ */
+__STATIC_INLINE void __enable_mmu(void) {
+    // Set M bit 0 to enable the MMU
+    // Set AFE bit to enable simplified access permissions model
+    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+    __ISB();
+}
+
+/** \brief  Disable MMU
+
+    Disable MMU
+ */
+__STATIC_INLINE void __disable_mmu(void) {
+    // Clear M bit 0 to disable the MMU
+    __set_SCTLR( __get_SCTLR() & ~1);
+    __ISB();
+}
+
+/******************************** TLB maintenance operations ************************************************/
+/** \brief  Invalidate the whole tlb
+
+    TLBIALL. Invalidate the whole tlb
+ */
+
+__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
+    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");
+    __TLBIALL = 0;
+    __DSB();
+    __ISB();
+}
+
+/******************************** BTB maintenance operations ************************************************/
+/** \brief  Invalidate entire branch predictor array
+
+    BPIALL. Branch Predictor Invalidate All.
+ */
+
+__STATIC_INLINE void __v7_inv_btac(void) {
+    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");
+    __BPIALL  = 0;
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new state
+}
+
+
+/******************************** L1 cache operations ******************************************************/
+
+/** \brief  Invalidate the whole I$
+
+    ICIALLU. Instruction Cache Invalidate All to PoU
+ */
+__STATIC_INLINE void __v7_inv_icache_all(void) {
+    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
+    __ICIALLU = 0;
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
+/** \brief  Clean D$ by MVA
+
+    DCCMVAC. Data cache clean by MVA to PoC
+ */
+__STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
+    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
+    __DCCMVAC = (uint32_t)va;
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Invalidate D$ by MVA
+
+    DCIMVAC. Data cache invalidate by MVA to PoC
+ */
+__STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
+    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
+    __DCIMVAC = (uint32_t)va;
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate D$ by MVA
+
+    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
+ */
+__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
+    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
+    __DCCIMVAC = (uint32_t)va;
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+
+    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
+ */
+#pragma push
+#pragma arm
+__STATIC_ASM void __v7_all_cache(uint32_t op) {
+        ARM 
+
+        PUSH    {R4-R11}
+
+        MRC     p15, 1, R6, c0, c0, 1      // Read CLIDR
+        ANDS    R3, R6, #0x07000000        // Extract coherency level
+        MOV     R3, R3, LSR #23            // Total cache levels << 1
+        BEQ     Finished                   // If 0, no need to clean
+
+        MOV     R10, #0                    // R10 holds current cache level << 1
+Loop1   ADD     R2, R10, R10, LSR #1       // R2 holds cache "Set" position
+        MOV     R1, R6, LSR R2             // Bottom 3 bits are the Cache-type for this level
+        AND     R1, R1, #7                 // Isolate those lower 3 bits
+        CMP     R1, #2
+        BLT     Skip                       // No cache or only instruction cache at this level
+
+        MCR     p15, 2, R10, c0, c0, 0     // Write the Cache Size selection register
+        ISB                                // ISB to sync the change to the CacheSizeID reg
+        MRC     p15, 1, R1, c0, c0, 0      // Reads current Cache Size ID register
+        AND     R2, R1, #7                 // Extract the line length field
+        ADD     R2, R2, #4                 // Add 4 for the line length offset (log2 16 bytes)
+        LDR     R4, =0x3FF
+        ANDS    R4, R4, R1, LSR #3         // R4 is the max number on the way size (right aligned)
+        CLZ     R5, R4                     // R5 is the bit position of the way size increment
+        LDR     R7, =0x7FFF
+        ANDS    R7, R7, R1, LSR #13        // R7 is the max number of the index size (right aligned)
+
+Loop2   MOV     R9, R4                     // R9 working copy of the max way size (right aligned)
+
+Loop3   ORR     R11, R10, R9, LSL R5       // Factor in the Way number and cache number into R11
+        ORR     R11, R11, R7, LSL R2       // Factor in the Set number
+        CMP     R0, #0
+        BNE     Dccsw
+        MCR     p15, 0, R11, c7, c6, 2     // DCISW. Invalidate by Set/Way
+        B       cont
+Dccsw   CMP     R0, #1
+        BNE     Dccisw
+        MCR     p15, 0, R11, c7, c10, 2    // DCCSW. Clean by Set/Way
+        B       cont
+Dccisw  MCR     p15, 0, R11, c7, c14, 2    // DCCISW. Clean and Invalidate by Set/Way
+cont    SUBS    R9, R9, #1                 // Decrement the Way number
+        BGE     Loop3
+        SUBS    R7, R7, #1                 // Decrement the Set number
+        BGE     Loop2
+Skip    ADD     R10, R10, #2               // Increment the cache number
+        CMP     R3, R10
+        BGT     Loop1
+
+Finished
+        DSB
+        POP    {R4-R11}
+        BX     lr
+
+}
+#pragma pop
+
+
+/** \brief  Invalidate the whole D$
+
+    DCISW. Invalidate by Set/Way
+ */
+
+__STATIC_INLINE void __v7_inv_dcache_all(void) {
+    __v7_all_cache(0);
+}
+
+/** \brief  Clean the whole D$
+
+    DCCSW. Clean by Set/Way
+ */
+
+__STATIC_INLINE void __v7_clean_dcache_all(void) {
+    __v7_all_cache(1);
+}
+
+/** \brief  Clean and invalidate the whole D$
+
+    DCCISW. Clean and Invalidate by Set/Way
+ */
+
+__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
+    __v7_all_cache(2);
+}
+
+#include "core_ca_mmu.h"
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+
+#define __inline inline
+
+inline static uint32_t __disable_irq_iar() {
+  int irq_dis = __get_CPSR() & 0x80;      // 7bit CPSR.I
+  __disable_irq();
+  return irq_dis;
+}
+
+#define MODE_USR 0x10
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_MON 0x16
+#define MODE_ABT 0x17
+#define MODE_HYP 0x1A
+#define MODE_UND 0x1B
+#define MODE_SYS 0x1F
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+// from rt_CMSIS.c
+__arm static inline void __set_PSP(uint32_t topOfProcStack) {
+__asm(
+  "    ARM\n"
+//  "    PRESERVE8\n"
+
+  "    BIC     R0, R0, #7  ;ensure stack is 8-byte aligned \n"
+  "    MRS     R1, CPSR \n"
+  "    CPS     #0x1F   ;no effect in USR mode \n"        // MODE_SYS
+  "    MOV     SP, R0 \n"
+  "    MSR     CPSR_c, R1  ;no effect in USR mode \n"
+  "    ISB \n"
+  "    BX      LR \n");
+}
+
+/** \brief  Set User Mode
+
+    This function changes the processor state to User Mode
+ */
+// from rt_CMSIS.c
+__arm static inline void __set_CPS_USR(void) {
+__asm(
+  "    ARM \n"
+
+  "    CPS  #0x10  \n"                  // MODE_USR
+  "    BX   LR\n");
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+// from mmu_Renesas_RZ_A1.c
+__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+    __MCR(15, 0, ttbr0, 2, 0, 0);      // reg to cp15
+    __ISB();
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+// from mmu_Renesas_RZ_A1.c
+__STATIC_INLINE void __set_DACR(uint32_t dacr) {
+    __MCR(15, 0, dacr, 3, 0, 0);      // reg to cp15
+    __ISB();
+}
+
+
+/******************************** Cache and BTAC enable  ****************************************************/
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+// from __enable_mmu()
+__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
+    __MCR(15, 0, sctlr, 1, 0, 0);      // reg to cp15
+}
+
+/** \brief  Get SCTLR
+
+    This function returns the value of the System Control Register.
+
+    \return               System Control Register value
+ */
+// from __enable_mmu()
+__STATIC_INLINE uint32_t __get_SCTLR() {
+	uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
+	return __regSCTLR;
+}
+
+/** \brief  Enable Caches
+
+    Enable Caches
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __enable_caches(void) {
+    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
+}
+
+/** \brief  Enable BTAC
+
+    Enable BTAC
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __enable_btac(void) {
+    __set_SCTLR( __get_SCTLR() | (1 << 11));
+    __ISB();
+}
+
+/** \brief  Enable MMU
+
+    Enable MMU
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __enable_mmu(void) {
+    // Set M bit 0 to enable the MMU
+    // Set AFE bit to enable simplified access permissions model
+    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+    __ISB();
+}
+
+/******************************** TLB maintenance operations ************************************************/
+/** \brief  Invalidate the whole tlb
+
+    TLBIALL. Invalidate the whole tlb
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
+	uint32_t val = 0;
+    __MCR(15, 0, val, 8, 7, 0);      // reg to cp15
+    __MCR(15, 0, val, 8, 6, 0);      // reg to cp15
+    __MCR(15, 0, val, 8, 5, 0);      // reg to cp15
+    __DSB();
+    __ISB();
+}
+
+/******************************** BTB maintenance operations ************************************************/
+/** \brief  Invalidate entire branch predictor array
+
+    BPIALL. Branch Predictor Invalidate All.
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __v7_inv_btac(void) {
+	uint32_t val = 0;
+    __MCR(15, 0, val, 7, 5, 6);      // reg to cp15
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new state
+}
+
+
+/******************************** L1 cache operations ******************************************************/
+
+/** \brief  Invalidate the whole I$
+
+    ICIALLU. Instruction Cache Invalidate All to PoU
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __v7_inv_icache_all(void) {
+	uint32_t val = 0;
+    __MCR(15, 0, val, 7, 5, 0);      // reg to cp15
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
+// from __v7_inv_dcache_all()
+__arm static inline void __v7_all_cache(uint32_t op) {
+__asm(
+	"        ARM \n"
+
+	"        PUSH    {R4-R11} \n"
+
+	"        MRC     p15, 1, R6, c0, c0, 1\n"      // Read CLIDR
+	"        ANDS    R3, R6, #0x07000000\n"        // Extract coherency level
+	"        MOV     R3, R3, LSR #23\n"            // Total cache levels << 1
+	"        BEQ     Finished\n"                   // If 0, no need to clean
+
+	"        MOV     R10, #0\n"                    // R10 holds current cache level << 1
+    "Loop1:   ADD     R2, R10, R10, LSR #1\n"       // R2 holds cache "Set" position
+	"        MOV     R1, R6, LSR R2 \n"            // Bottom 3 bits are the Cache-type for this level
+	"        AND     R1, R1, #7 \n"                // Isolate those lower 3 bits
+	"        CMP     R1, #2 \n"
+	"        BLT     Skip \n"                      // No cache or only instruction cache at this level
+
+	"        MCR     p15, 2, R10, c0, c0, 0 \n"    // Write the Cache Size selection register
+	"        ISB \n"                               // ISB to sync the change to the CacheSizeID reg
+	"        MRC     p15, 1, R1, c0, c0, 0 \n"     // Reads current Cache Size ID register
+	"        AND     R2, R1, #7 \n"                // Extract the line length field
+	"        ADD     R2, R2, #4 \n"                // Add 4 for the line length offset (log2 16 bytes)
+	"        movw    R4, #0x3FF \n"
+	"        ANDS    R4, R4, R1, LSR #3 \n"        // R4 is the max number on the way size (right aligned)
+	"        CLZ     R5, R4 \n"                    // R5 is the bit position of the way size increment
+	"        movw    R7, #0x7FFF \n"
+	"        ANDS    R7, R7, R1, LSR #13 \n"       // R7 is the max number of the index size (right aligned)
+
+	"Loop2:   MOV     R9, R4 \n"                    // R9 working copy of the max way size (right aligned)
+
+	"Loop3:   ORR     R11, R10, R9, LSL R5 \n"      // Factor in the Way number and cache number into R11
+	"        ORR     R11, R11, R7, LSL R2 \n"      // Factor in the Set number
+	"        CMP     R0, #0 \n"
+	"        BNE     Dccsw \n"
+	"        MCR     p15, 0, R11, c7, c6, 2 \n"    // DCISW. Invalidate by Set/Way
+	"        B       cont \n"
+	"Dccsw:   CMP     R0, #1 \n"
+	"        BNE     Dccisw \n"
+	"        MCR     p15, 0, R11, c7, c10, 2 \n"   // DCCSW. Clean by Set/Way
+	"        B       cont \n"
+	"Dccisw:  MCR     p15, 0, R11, c7, c14, 2 \n"   // DCCISW, Clean and Invalidate by Set/Way
+	"cont:    SUBS    R9, R9, #1 \n"                // Decrement the Way number
+	"        BGE     Loop3 \n"
+	"        SUBS    R7, R7, #1 \n"                // Decrement the Set number
+	"        BGE     Loop2 \n"
+	"Skip:    ADD     R10, R10, #2 \n"              // increment the cache number
+	"        CMP     R3, R10 \n"
+	"        BGT     Loop1 \n"
+
+	"Finished: \n"
+	"        DSB \n"
+	"        POP    {R4-R11} \n"
+	"        BX     lr \n" );
+}
+
+/** \brief  Invalidate the whole D$
+
+    DCISW. Invalidate by Set/Way
+ */
+// from system_Renesas_RZ_A1.c
+__STATIC_INLINE void __v7_inv_dcache_all(void) {
+    __v7_all_cache(0);
+}
+/** \brief  Clean and Invalidate D$ by MVA
+
+    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
+ */
+__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
+    __MCR(15, 0, (uint32_t)va, 7, 14, 1);
+    __DMB();
+}
+
+#include "core_ca_mmu.h"
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+#define MODE_USR 0x10
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_MON 0x16
+#define MODE_ABT 0x17
+#define MODE_HYP 0x1A
+#define MODE_UND 0x1B
+#define MODE_SYS 0x1F
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+    __ASM volatile ("cpsie i");
+}
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("mrs %0, cpsr" : "=r" (result));
+    __ASM volatile ("cpsid i");
+    return(result & 0x80);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+#if 1
+  register uint32_t __regAPSR;
+  __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
+#else
+  register uint32_t __regAPSR          __ASM("apsr");
+#endif
+  return(__regAPSR);
+}
+
+
+/** \brief  Get CPSR Register
+
+    This function returns the content of the CPSR Register.
+
+    \return               CPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
+{
+#if 1
+  register uint32_t __regCPSR;
+  __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
+#else
+  register uint32_t __regCPSR          __ASM("cpsr");
+#endif
+  return(__regCPSR);
+}
+
+#if 0
+/** \brief  Set Stack Pointer
+
+    This function assigns the given value to the current stack pointer.
+
+    \param [in]    topOfStack  Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
+{
+    register uint32_t __regSP       __ASM("sp");
+    __regSP = topOfStack;
+}
+#endif
+
+/** \brief  Get link register
+
+    This function returns the value of the link register
+
+    \return    Value of link register
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
+{
+  register uint32_t __reglr         __ASM("lr");
+  return(__reglr);
+}
+
+#if 0
+/** \brief  Set link register
+
+    This function sets the value of the link register
+
+    \param [in]    lr  LR value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
+{
+  register uint32_t __reglr         __ASM("lr");
+  __reglr = lr;
+}
+#endif
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the USR/SYS Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  USR/SYS Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    __asm__ volatile (
+    ".ARM;"
+    ".eabi_attribute Tag_ABI_align8_preserved,1;"
+
+    "BIC     R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
+    "MRS     R1, CPSR;"
+    "CPS     %0;"         /* ;no effect in USR mode */
+    "MOV     SP, R0;"
+    "MSR     CPSR_c, R1;" /* ;no effect in USR mode */
+    "ISB;"
+    //"BX      LR;"
+    :
+    : "i"(MODE_SYS)
+    : "r0", "r1");
+    return;
+}
+
+/** \brief  Set User Mode
+
+    This function changes the processor state to User Mode
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
+{
+    __asm__ volatile (
+    ".ARM;"
+
+    "CPS  %0;"
+    //"BX   LR;"
+    :
+    : "i"(MODE_USR)
+    : );
+    return;
+}
+
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq()                __asm__ volatile ("cpsie f")
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq()               __asm__ volatile ("cpsid f")
+
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+#if 1
+    uint32_t result;
+
+    __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
+    return (result);
+#else
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#endif
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+#if 1
+    __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
+#else
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+#endif
+}
+
+/** \brief  Get FPEXC
+
+    This function returns the current value of the Floating Point Exception Control register.
+
+    \return               Floating Point Exception Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
+{
+#if (__FPU_PRESENT == 1)
+#if 1
+    uint32_t result;
+
+    __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
+    return (result);
+#else
+  register uint32_t __regfpexc         __ASM("fpexc");
+  return(__regfpexc);
+#endif
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPEXC
+
+    This function assigns the given value to the Floating Point Exception Control register.
+
+    \param [in]    fpscr  Floating Point Exception Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
+{
+#if (__FPU_PRESENT == 1)
+#if 1
+    __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
+#else
+  register uint32_t __regfpexc         __ASM("fpexc");
+  __regfpexc = (fpexc);
+#endif
+#endif
+}
+
+/** \brief  Get CPACR
+
+    This function returns the current value of the Coprocessor Access Control register.
+
+    \return               Coprocessor Access Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
+{
+#if 1
+    register uint32_t __regCPACR;
+    __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
+#else
+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+#endif
+    return __regCPACR;
+}
+
+/** \brief  Set CPACR
+
+    This function assigns the given value to the Coprocessor Access Control register.
+
+    \param [in]    cpacr  Coprocessor Acccess Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
+{
+#if 1
+    __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
+#else
+    register uint32_t __regCPACR         __ASM("cp15:0:c1:c0:2");
+    __regCPACR = cpacr;
+#endif
+    __ISB();
+}
+
+/** \brief  Get CBAR
+
+    This function returns the value of the Configuration Base Address register.
+
+    \return               Configuration Base Address register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
+#if 1
+    register uint32_t __regCBAR;
+    __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
+#else
+    register uint32_t __regCBAR         __ASM("cp15:4:c15:c0:0");
+#endif
+    return(__regCBAR);
+}
+
+/** \brief  Get TTBR0
+
+    This function returns the value of the Translation Table Base Register 0.
+
+    \return               Translation Table Base Register 0 value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
+#if 1
+    register uint32_t __regTTBR0;
+    __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
+#else
+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+#endif
+    return(__regTTBR0);
+}
+
+/** \brief  Set TTBR0
+
+    This function assigns the given value to the Translation Table Base Register 0.
+
+    \param [in]    ttbr0  Translation Table Base Register 0 value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
+#else
+    register uint32_t __regTTBR0        __ASM("cp15:0:c2:c0:0");
+    __regTTBR0 = ttbr0;
+#endif
+    __ISB();
+}
+
+/** \brief  Get DACR
+
+    This function returns the value of the Domain Access Control Register.
+
+    \return               Domain Access Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
+#if 1
+    register uint32_t __regDACR;
+    __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
+#else
+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+#endif
+    return(__regDACR);
+}
+
+/** \brief  Set DACR
+
+    This function assigns the given value to the Domain Access Control Register.
+
+    \param [in]    dacr   Domain Access Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
+#else
+    register uint32_t __regDACR         __ASM("cp15:0:c3:c0:0");
+    __regDACR = dacr;
+#endif
+    __ISB();
+}
+
+/******************************** Cache and BTAC enable  ****************************************************/
+
+/** \brief  Set SCTLR
+
+    This function assigns the given value to the System Control Register.
+
+    \param [in]    sctlr  System Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
+{
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
+#else
+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+    __regSCTLR = sctlr;
+#endif
+}
+
+/** \brief  Get SCTLR
+
+    This function returns the value of the System Control Register.
+
+    \return               System Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
+#if 1
+	register uint32_t __regSCTLR;
+	__ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
+#else
+    register uint32_t __regSCTLR         __ASM("cp15:0:c1:c0:0");
+#endif
+    return(__regSCTLR);
+}
+
+/** \brief  Enable Caches
+
+    Enable Caches
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
+    // Set I bit 12 to enable I Cache
+    // Set C bit  2 to enable D Cache
+    __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
+}
+
+/** \brief  Disable Caches
+
+    Disable Caches
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
+    // Clear I bit 12 to disable I Cache
+    // Clear C bit  2 to disable D Cache
+    __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
+    __ISB();
+}
+
+/** \brief  Enable BTAC
+
+    Enable BTAC
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
+    // Set Z bit 11 to enable branch prediction
+    __set_SCTLR( __get_SCTLR() | (1 << 11));
+    __ISB();
+}
+
+/** \brief  Disable BTAC
+
+    Disable BTAC
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
+    // Clear Z bit 11 to disable branch prediction
+    __set_SCTLR( __get_SCTLR() & ~(1 << 11));
+}
+
+
+/** \brief  Enable MMU
+
+    Enable MMU
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
+    // Set M bit 0 to enable the MMU
+    // Set AFE bit to enable simplified access permissions model
+    // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
+    __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
+    __ISB();
+}
+
+/** \brief  Disable MMU
+
+    Disable MMU
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
+    // Clear M bit 0 to disable the MMU
+    __set_SCTLR( __get_SCTLR() & ~1);
+    __ISB();
+}
+
+/******************************** TLB maintenance operations ************************************************/
+/** \brief  Invalidate the whole tlb
+
+    TLBIALL. Invalidate the whole tlb
+ */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
+#else
+    register uint32_t __TLBIALL         __ASM("cp15:0:c8:c7:0");
+    __TLBIALL = 0;
+#endif
+    __DSB();
+    __ISB();
+}
+
+/******************************** BTB maintenance operations ************************************************/
+/** \brief  Invalidate entire branch predictor array
+
+    BPIALL. Branch Predictor Invalidate All.
+ */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
+#else
+    register uint32_t __BPIALL          __ASM("cp15:0:c7:c5:6");
+    __BPIALL  = 0;
+#endif
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new state
+}
+
+
+/******************************** L1 cache operations ******************************************************/
+
+/** \brief  Invalidate the whole I$
+
+    ICIALLU. Instruction Cache Invalidate All to PoU
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
+#if 1
+	__ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
+#else
+    register uint32_t __ICIALLU         __ASM("cp15:0:c7:c5:0");
+    __ICIALLU = 0;
+#endif
+    __DSB();     //ensure completion of the invalidation
+    __ISB();     //ensure instruction fetch path sees new I cache state
+}
+
+/** \brief  Clean D$ by MVA
+
+    DCCMVAC. Data cache clean by MVA to PoC
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
+#if 1
+    __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
+#else
+    register uint32_t __DCCMVAC         __ASM("cp15:0:c7:c10:1");
+    __DCCMVAC = (uint32_t)va;
+#endif
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Invalidate D$ by MVA
+
+    DCIMVAC. Data cache invalidate by MVA to PoC
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
+#if 1
+    __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
+#else
+    register uint32_t __DCIMVAC         __ASM("cp15:0:c7:c6:1");
+    __DCIMVAC = (uint32_t)va;
+#endif
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate D$ by MVA
+
+    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
+#if 1
+    __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
+#else
+    register uint32_t __DCCIMVAC        __ASM("cp15:0:c7:c14:1");
+    __DCCIMVAC = (uint32_t)va;
+#endif
+    __DMB();     //ensure the ordering of data cache maintenance operations and their effects
+}
+
+/** \brief  Clean and Invalidate the entire data or unified cache
+
+    Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
+ */
+extern void __v7_all_cache(uint32_t op);
+
+
+/** \brief  Invalidate the whole D$
+
+    DCISW. Invalidate by Set/Way
+ */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
+    __v7_all_cache(0);
+}
+
+/** \brief  Clean the whole D$
+
+    DCCSW. Clean by Set/Way
+ */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
+    __v7_all_cache(1);
+}
+
+/** \brief  Clean and invalidate the whole D$
+
+    DCCISW. Clean and Invalidate by Set/Way
+ */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
+    __v7_all_cache(2);
+}
+
+#include "core_ca_mmu.h"
+
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+
+#error TASKING Compiler support not implemented for Cortex-A
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CAFUNC_H__ */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_caInstr.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,46 @@
+/**************************************************************************//**
+ * @file     core_caInstr.h
+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
+ * @version
+ * @date     04. December 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#ifndef __CORE_CAINSTR_H__
+#define __CORE_CAINSTR_H__
+
+#define __CORTEX_M 0x3
+#include "core_cmInstr.h"
+#undef  __CORTEX_M
+
+#endif
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_ca_mmu.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,848 @@
+;/**************************************************************************//**
+; * @file     core_ca_mmu.h
+; * @brief    MMU Startup File for A9_MP Device Series
+; * @version  V1.01
+; * @date     10 Sept 2014
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/* Copyright (c) 2012-2014 ARM LIMITED
+;
+;   All rights reserved.
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions are met:
+;   - Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;   - Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;   - Neither the name of ARM nor the names of its contributors may be used
+;     to endorse or promote products derived from this software without
+;     specific prior written permission.
+;   *
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;   POSSIBILITY OF SUCH DAMAGE.
+;   ---------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef _MMU_FUNC_H
+#define _MMU_FUNC_H
+
+#define SECTION_DESCRIPTOR      (0x2)
+#define SECTION_MASK            (0xFFFFFFFC)
+
+#define SECTION_TEXCB_MASK      (0xFFFF8FF3)
+#define SECTION_B_SHIFT         (2)
+#define SECTION_C_SHIFT         (3)
+#define SECTION_TEX0_SHIFT      (12)
+#define SECTION_TEX1_SHIFT      (13)
+#define SECTION_TEX2_SHIFT      (14)
+
+#define SECTION_XN_MASK         (0xFFFFFFEF)
+#define SECTION_XN_SHIFT        (4)
+
+#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
+#define SECTION_DOMAIN_SHIFT    (5)
+
+#define SECTION_P_MASK          (0xFFFFFDFF)
+#define SECTION_P_SHIFT         (9)
+
+#define SECTION_AP_MASK         (0xFFFF73FF)
+#define SECTION_AP_SHIFT        (10)
+#define SECTION_AP2_SHIFT       (15)
+
+#define SECTION_S_MASK          (0xFFFEFFFF)
+#define SECTION_S_SHIFT         (16)
+
+#define SECTION_NG_MASK         (0xFFFDFFFF)
+#define SECTION_NG_SHIFT        (17)
+
+#define SECTION_NS_MASK         (0xFFF7FFFF)
+#define SECTION_NS_SHIFT        (19)
+
+
+#define PAGE_L1_DESCRIPTOR      (0x1)
+#define PAGE_L1_MASK            (0xFFFFFFFC)
+
+#define PAGE_L2_4K_DESC         (0x2)
+#define PAGE_L2_4K_MASK         (0xFFFFFFFD)
+
+#define PAGE_L2_64K_DESC        (0x1)
+#define PAGE_L2_64K_MASK        (0xFFFFFFFC)
+
+#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
+#define PAGE_4K_B_SHIFT         (2)
+#define PAGE_4K_C_SHIFT         (3)
+#define PAGE_4K_TEX0_SHIFT      (6)
+#define PAGE_4K_TEX1_SHIFT      (7)
+#define PAGE_4K_TEX2_SHIFT      (8)
+
+#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
+#define PAGE_64K_B_SHIFT        (2)
+#define PAGE_64K_C_SHIFT        (3)
+#define PAGE_64K_TEX0_SHIFT     (12)
+#define PAGE_64K_TEX1_SHIFT     (13)
+#define PAGE_64K_TEX2_SHIFT     (14)
+
+#define PAGE_TEXCB_MASK         (0xFFFF8FF3)
+#define PAGE_B_SHIFT            (2)
+#define PAGE_C_SHIFT            (3)
+#define PAGE_TEX_SHIFT          (12)
+
+#define PAGE_XN_4K_MASK         (0xFFFFFFFE)
+#define PAGE_XN_4K_SHIFT        (0)
+#define PAGE_XN_64K_MASK        (0xFFFF7FFF)
+#define PAGE_XN_64K_SHIFT       (15)
+
+
+#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
+#define PAGE_DOMAIN_SHIFT       (5)
+
+#define PAGE_P_MASK             (0xFFFFFDFF)
+#define PAGE_P_SHIFT            (9)
+
+#define PAGE_AP_MASK            (0xFFFFFDCF)
+#define PAGE_AP_SHIFT           (4)
+#define PAGE_AP2_SHIFT          (9)
+
+#define PAGE_S_MASK             (0xFFFFFBFF)
+#define PAGE_S_SHIFT            (10)
+
+#define PAGE_NG_MASK            (0xFFFFF7FF)
+#define PAGE_NG_SHIFT           (11)
+
+#define PAGE_NS_MASK            (0xFFFFFFF7)
+#define PAGE_NS_SHIFT           (3)
+
+#define OFFSET_1M               (0x00100000)
+#define OFFSET_64K              (0x00010000)
+#define OFFSET_4K               (0x00001000)
+
+#define DESCRIPTOR_FAULT        (0x00000000)
+
+/* ###########################  MMU Function Access  ########################### */
+/** \ingroup  MMU_FunctionInterface
+    \defgroup MMU_Functions MMU Functions Interface
+  @{
+ */
+
+/* Attributes enumerations */
+
+/* Region size attributes */
+typedef enum
+{
+   SECTION,
+   PAGE_4k,
+   PAGE_64k,
+} mmu_region_size_Type;
+
+/* Region type attributes */
+typedef enum
+{
+   NORMAL,
+   DEVICE,
+   SHARED_DEVICE,
+   NON_SHARED_DEVICE,
+   STRONGLY_ORDERED
+} mmu_memory_Type;
+
+/* Region cacheability attributes */
+typedef enum
+{
+   NON_CACHEABLE,
+   WB_WA,
+   WT,
+   WB_NO_WA,
+} mmu_cacheability_Type;
+
+/* Region parity check attributes */
+typedef enum
+{
+   ECC_DISABLED,
+   ECC_ENABLED,
+} mmu_ecc_check_Type;
+
+/* Region execution attributes */
+typedef enum
+{
+   EXECUTE,
+   NON_EXECUTE,
+} mmu_execute_Type;
+
+/* Region global attributes */
+typedef enum
+{
+   GLOBAL,
+   NON_GLOBAL,
+} mmu_global_Type;
+
+/* Region shareability attributes */
+typedef enum
+{
+   NON_SHARED,
+   SHARED,
+} mmu_shared_Type;
+
+/* Region security attributes */
+typedef enum
+{
+   SECURE,
+   NON_SECURE,
+} mmu_secure_Type;
+
+/* Region access attributes */
+typedef enum
+{
+   NO_ACCESS,
+   RW,
+   READ,
+} mmu_access_Type;
+
+/* Memory Region definition */
+typedef struct RegionStruct {
+    mmu_region_size_Type rg_t;
+    mmu_memory_Type mem_t;
+    uint8_t domain;
+    mmu_cacheability_Type inner_norm_t;
+    mmu_cacheability_Type outer_norm_t;
+    mmu_ecc_check_Type e_t;
+    mmu_execute_Type xn_t;
+    mmu_global_Type g_t;
+    mmu_secure_Type sec_t;
+    mmu_access_Type priv_t;
+    mmu_access_Type user_t;
+    mmu_shared_Type sh_t;
+
+} mmu_region_attributes_Type;
+
+/** \brief  Set section execution-never attribute
+
+    The function sets section execution-never attribute
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
+
+    \return          0  
+ */
+__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
+{
+    *descriptor_l1 &= SECTION_XN_MASK;
+    *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
+    return 0;
+}
+
+/** \brief  Set section domain
+
+    The function sets section domain
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]            domain  Section domain
+
+    \return          0  
+ */
+__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
+{
+    *descriptor_l1 &= SECTION_DOMAIN_MASK;
+    *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
+    return 0;
+}
+
+/** \brief  Set section parity check
+
+    The function sets section parity check
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+    \return          0  
+ */
+__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+    *descriptor_l1 &= SECTION_P_MASK;
+    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+    return 0;
+}
+
+/** \brief  Set section access privileges
+
+    The function sets section access privileges
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+    \param [in]               afe  Access flag enable
+
+    \return          0  
+ */
+__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
+{
+    uint32_t ap = 0;
+
+    if (afe == 0) { //full access
+        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+    }
+
+    else { //Simplified access
+        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+    }
+
+    *descriptor_l1 &= SECTION_AP_MASK;
+    *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
+    *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
+
+    return 0;
+}
+
+/** \brief  Set section shareability
+
+    The function sets section shareability
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
+
+    \return          0  
+ */
+__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
+{
+    *descriptor_l1 &= SECTION_S_MASK;
+    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
+    return 0;
+}
+
+/** \brief  Set section Global attribute
+
+    The function sets section Global attribute
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
+
+    \return          0  
+ */
+__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
+{
+    *descriptor_l1 &= SECTION_NG_MASK;
+    *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
+    return 0;
+}
+
+/** \brief  Set section Security attribute
+
+    The function sets section Global attribute
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
+
+    \return          0  
+ */
+__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+    *descriptor_l1 &= SECTION_NS_MASK;
+    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
+    return 0;
+}
+
+/* Page 4k or 64k */
+/** \brief  Set 4k/64k page execution-never attribute
+
+    The function sets 4k/64k page execution-never attribute
+
+    \param [out]    descriptor_l2  L2 descriptor.
+    \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
+    \param [in]              page  Page size: PAGE_4k, PAGE_64k,
+   
+    \return          0  
+ */
+__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
+{
+    if (page == PAGE_4k)
+    {
+        *descriptor_l2 &= PAGE_XN_4K_MASK;
+        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
+    }
+    else
+    {
+        *descriptor_l2 &= PAGE_XN_64K_MASK;
+        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
+    }
+    return 0;
+}
+
+/** \brief  Set 4k/64k page domain
+
+    The function sets 4k/64k page domain
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]            domain  Page domain
+
+    \return          0  
+ */
+__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
+{
+    *descriptor_l1 &= PAGE_DOMAIN_MASK;
+    *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
+    return 0;
+}
+
+/** \brief  Set 4k/64k page parity check
+
+    The function sets 4k/64k page parity check
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
+
+    \return          0  
+ */
+__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
+{
+    *descriptor_l1 &= SECTION_P_MASK;
+    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
+    return 0;
+}
+
+/** \brief  Set 4k/64k page access privileges
+
+    The function sets 4k/64k page access privileges
+
+    \param [out]    descriptor_l2  L2 descriptor.
+    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
+    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
+    \param [in]               afe  Access flag enable
+
+    \return          0  
+ */
+__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
+{
+    uint32_t ap = 0;
+
+    if (afe == 0) { //full access
+        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
+        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
+        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+        else if ((priv == READ) && (user == READ))      { ap = 0x6; }
+    }
+
+    else { //Simplified access
+        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
+    }
+
+    *descriptor_l2 &= PAGE_AP_MASK;
+    *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
+    *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
+
+    return 0;
+}
+
+/** \brief  Set 4k/64k page shareability
+
+    The function sets 4k/64k page shareability
+
+    \param [out]    descriptor_l2  L2 descriptor.
+    \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
+
+    \return          0  
+ */
+__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
+{
+    *descriptor_l2 &= PAGE_S_MASK;
+    *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
+    return 0;
+}
+
+/** \brief  Set 4k/64k page Global attribute
+
+    The function sets 4k/64k page Global attribute
+
+    \param [out]    descriptor_l2  L2 descriptor.
+    \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
+
+    \return          0  
+ */
+__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
+{
+    *descriptor_l2 &= PAGE_NG_MASK;
+    *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
+    return 0;
+}
+
+/** \brief  Set 4k/64k page Security attribute
+
+    The function sets 4k/64k page Global attribute
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
+
+    \return          0  
+ */
+__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
+{
+    *descriptor_l1 &= PAGE_NS_MASK;
+    *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
+    return 0;
+}
+
+
+/** \brief  Set Section memory attributes
+
+    The function sets section memory attributes
+
+    \param [out]    descriptor_l1  L1 descriptor.
+    \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+
+    \return          0  
+ */
+__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
+{
+    *descriptor_l1 &= SECTION_TEXCB_MASK;
+
+    if (STRONGLY_ORDERED == mem)
+    {
+        return 0;
+    }
+    else if (SHARED_DEVICE == mem)
+    {
+        *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+    }
+    else if (NON_SHARED_DEVICE == mem)
+    {
+        *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
+    }
+    else if (NORMAL == mem)
+    {
+           *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
+           switch(inner)
+           {
+            case NON_CACHEABLE:
+            break;
+            case WB_WA:
+                *descriptor_l1 |= (1 << SECTION_B_SHIFT);
+                break;
+            case WT:
+                *descriptor_l1 |= 1 << SECTION_C_SHIFT;
+                break;
+            case WB_NO_WA:
+                *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
+                break;
+        }
+        switch(outer)
+        {
+            case NON_CACHEABLE:
+             break;
+            case WB_WA:
+                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
+                break;
+            case WT:
+                *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
+                break;
+            case WB_NO_WA:
+                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
+                break;
+        }
+    }
+
+    return 0;
+}
+
+/** \brief  Set 4k/64k page memory attributes
+
+    The function sets 4k/64k page memory attributes
+
+    \param [out]    descriptor_l2  L2 descriptor.
+    \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
+    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
+
+    \return          0  
+ */
+__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
+{
+    *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
+
+    if (page == PAGE_64k)
+    {
+        //same as section
+        __memory_section(descriptor_l2, mem, outer, inner);
+    }
+    else
+    {
+        if (STRONGLY_ORDERED == mem)
+        {
+            return 0;
+        }
+        else if (SHARED_DEVICE == mem)
+        {
+            *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+        }
+        else if (NON_SHARED_DEVICE == mem)
+        {
+             *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
+        }
+        else if (NORMAL == mem)
+        {
+            *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
+            switch(inner)
+            {
+                case NON_CACHEABLE:
+                break;
+                case WB_WA:
+                     *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
+                     break;
+                case WT:
+                    *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
+                     break;
+                case WB_NO_WA:
+                    *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
+                    break;
+            }
+            switch(outer)
+            {
+                case NON_CACHEABLE:
+                break;
+                case WB_WA:
+                      *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
+                    break;
+                case WT:
+                     *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
+                    break;
+                case WB_NO_WA:
+                    *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
+                    break;
+            }
+        }
+    }
+
+    return 0;
+}
+
+/** \brief  Create a L1 section descriptor
+
+    The function creates a section descriptor.
+    
+    Assumptions:
+    - 16MB super sections not supported
+    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
+    - Functions always return 0
+
+    \param [out]       descriptor  L1 descriptor
+    \param [out]      descriptor2  L2 descriptor
+    \param [in]               reg  Section attributes
+
+    \return          0  
+ */
+__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
+{
+    *descriptor  = 0;
+
+   __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
+   __xn_section(descriptor,reg.xn_t);
+   __domain_section(descriptor, reg.domain);
+   __p_section(descriptor, reg.e_t);
+   __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
+   __shared_section(descriptor,reg.sh_t);
+   __global_section(descriptor,reg.g_t);
+   __secure_section(descriptor,reg.sec_t);
+   *descriptor &= SECTION_MASK;
+   *descriptor |= SECTION_DESCRIPTOR;
+
+   return 0;
+
+}
+
+
+/** \brief  Create a L1 and L2 4k/64k page descriptor
+
+    The function creates a 4k/64k page descriptor.
+    Assumptions:
+    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
+    - Functions always return 0
+
+    \param [out]       descriptor  L1 descriptor
+    \param [out]      descriptor2  L2 descriptor
+    \param [in]               reg  4k/64k page attributes
+
+    \return          0  
+ */
+__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
+{
+    *descriptor  = 0;
+    *descriptor2 = 0;
+
+    switch (reg.rg_t)
+    {
+        case PAGE_4k:
+            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
+            __xn_page(descriptor2, reg.xn_t, PAGE_4k);
+            __domain_page(descriptor, reg.domain);
+            __p_page(descriptor, reg.e_t);
+            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
+            __shared_page(descriptor2,reg.sh_t);
+            __global_page(descriptor2,reg.g_t);
+            __secure_page(descriptor,reg.sec_t);
+            *descriptor &= PAGE_L1_MASK;
+            *descriptor |= PAGE_L1_DESCRIPTOR;
+            *descriptor2 &= PAGE_L2_4K_MASK;
+            *descriptor2 |= PAGE_L2_4K_DESC;
+            break;
+
+        case PAGE_64k:
+            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
+            __xn_page(descriptor2, reg.xn_t, PAGE_64k);
+            __domain_page(descriptor, reg.domain);
+            __p_page(descriptor, reg.e_t);
+            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
+            __shared_page(descriptor2,reg.sh_t);
+            __global_page(descriptor2,reg.g_t);
+            __secure_page(descriptor,reg.sec_t);
+            *descriptor &= PAGE_L1_MASK;
+            *descriptor |= PAGE_L1_DESCRIPTOR;
+            *descriptor2 &= PAGE_L2_64K_MASK;
+            *descriptor2 |= PAGE_L2_64K_DESC;
+            break;
+
+        case SECTION:
+            //error
+            break;    
+
+    }
+
+   return 0;
+
+}
+
+/** \brief  Create a 1MB Section
+
+    \param [in]               ttb  Translation table base address
+    \param [in]      base_address  Section base address
+    \param [in]             count  Number of sections to create
+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
+
+ */
+__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
+{
+    uint32_t offset;
+    uint32_t entry;
+    uint32_t i;
+
+    offset = base_address >> 20;
+    entry  = (base_address & 0xFFF00000) | descriptor_l1;
+
+    //4 bytes aligned
+    ttb = ttb + offset;
+
+    for (i = 0; i < count; i++ )
+    {
+        //4 bytes aligned
+       *ttb++ = entry;
+       entry += OFFSET_1M;
+    }
+}
+
+/** \brief  Create a 4k page entry
+
+    \param [in]               ttb  L1 table base address
+    \param [in]      base_address  4k base address
+    \param [in]             count  Number of 4k pages to create
+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
+    \param [in]            ttb_l2  L2 table base address
+    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
+
+ */
+__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+
+    uint32_t offset, offset2;
+    uint32_t entry, entry2;
+    uint32_t i;
+
+
+    offset = base_address >> 20;
+    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+    //4 bytes aligned
+    ttb += offset;
+    //create l1_entry
+    *ttb = entry;
+
+    offset2 = (base_address & 0xff000) >> 12;
+    ttb_l2 += offset2;
+    entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
+    for (i = 0; i < count; i++ )
+    {
+        //4 bytes aligned
+       *ttb_l2++ = entry2;
+       entry2 += OFFSET_4K;
+    }
+}
+
+/** \brief  Create a 64k page entry
+
+    \param [in]               ttb  L1 table base address
+    \param [in]      base_address  64k base address
+    \param [in]             count  Number of 64k pages to create
+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
+    \param [in]            ttb_l2  L2 table base address
+    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
+
+ */
+__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
+{
+    uint32_t offset, offset2;
+    uint32_t entry, entry2;
+    uint32_t i,j;
+
+
+    offset = base_address >> 20;
+    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
+
+    //4 bytes aligned
+    ttb += offset;
+    //create l1_entry
+    *ttb = entry;
+
+    offset2 = (base_address & 0xff000) >> 12;
+    ttb_l2 += offset2;
+    entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
+    for (i = 0; i < count; i++ )
+    {
+        //create 16 entries
+        for (j = 0; j < 16; j++)
+            //4 bytes aligned
+            *ttb_l2++ = entry2;
+        entry2 += OFFSET_64K;
+    }
+}
+
+/*@} end of MMU_Functions */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_cm0.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,741 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)(IRQn) < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)(IRQn) < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                        /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_cm0plus.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,855 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)(IRQn) < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)(IRQn) < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                        /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_cm3.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1694 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_cm4.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1888 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* CMSIS_VECTAB_VIRTUAL */
+
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_cm4_simd.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,674 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_cm7.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,2398 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16                                             /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16                                             /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2                                             /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[1];
+  __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */
+  __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */
+  __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */
+  __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+       uint32_t RESERVED3[93];
+  __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */
+       uint32_t RESERVED4[15];
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */
+       uint32_t RESERVED5[1];
+  __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */
+       uint32_t RESERVED6[1];
+  __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */
+  __O  uint32_t DCIMVAC;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */
+  __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */
+  __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */
+  __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */
+  __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */
+  __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */
+  __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */
+       uint32_t RESERVED7[6];
+  __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */
+  __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */
+  __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */
+  __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */
+  __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */
+       uint32_t RESERVED8[1];
+  __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* Cache Level ID register */
+#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */
+
+/* Cache Type register */
+#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* Cache Size ID Register */
+#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* Cache Size Selection Register */
+#define SCB_CSSELR_LEVEL_Pos                1                                             /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register */
+#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register*/
+#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Registers */
+#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register */
+#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register */
+#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS control register */
+#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register */
+#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+       uint32_t RESERVED3[981];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+  __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]                = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_FpuFunctions FPU Functions
+    \brief      Function that provides FPU type.
+    @{
+ */
+
+/**
+  \fn          uint32_t SCB_GetFPUType(void)
+  \brief       get FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if        ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
+    return 2UL;           // Double + Single precision FPU
+  } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
+    return 1UL;           // Single precision FPU
+  } else {
+    return 0UL;           // No FPU
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_CacheFunctions Cache Functions
+    \brief      Functions that configure Instruction and Data cache.
+    @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
+
+
+/** \brief Enable I-Cache
+
+    The function turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     // invalidate I-Cache
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  // enable I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable I-Cache
+
+    The function turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  // disable I-Cache
+    SCB->ICIALLU = 0UL;                     // invalidate I-Cache
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Invalidate I-Cache
+
+    The function invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Enable D-Cache
+
+    The function turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
+    ccsidr  = SCB->CCSIDR;
+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+    __DSB();
+
+    do {                                   // invalidate D-Cache
+         uint32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;   // enable D-Cache
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Disable D-Cache
+
+    The function turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
+    ccsidr  = SCB->CCSIDR;
+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  // disable D-Cache
+
+    do {                                    // clean & invalidate D-Cache
+         uint32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Invalidate D-Cache
+
+    The function invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
+    ccsidr  = SCB->CCSIDR;
+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+         uint32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Clean D-Cache
+
+    The function cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
+    ccsidr  = SCB->CCSIDR;
+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+    __DSB();
+
+    do {                                    // clean D-Cache
+         uint32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCSW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/** \brief Clean & Invalidate D-Cache
+
+    The function cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    SCB->CSSELR = (0UL << 1) | 0UL;         // Level 1 data cache
+    ccsidr  = SCB->CCSIDR;
+    sets    = (uint32_t)(CCSIDR_SETS(ccsidr));
+    sshift  = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+    ways    = (uint32_t)(CCSIDR_WAYS(ccsidr));
+    wshift  = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+    __DSB();
+
+    do {                                    // clean & invalidate D-Cache
+         uint32_t tmpways = ways;
+         do {
+              sw = ((tmpways << wshift) | (sets << sshift));
+              SCB->DCCISW = sw;
+            } while(tmpways--);
+        } while(sets--);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \fn          void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+  \brief       D-Cache Invalidate by address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1)
+    int32_t  op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr +=          linesize;
+      op_size -= (int32_t)linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \fn          void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+  \brief       D-Cache Clean by address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1)
+    int32_t  op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr +=          linesize;
+      op_size -= (int32_t)linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \fn          void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+  \brief       D-Cache Clean and Invalidate by address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if (__DCACHE_PRESENT == 1)
+    int32_t  op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+    uint32_t linesize = 32UL;               // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr +=          linesize;
+      op_size -= (int32_t)linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_cmFunc.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,665 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+    or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+	or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_cmInstr.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,917 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+  return(result);
+}
+#endif
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+#endif
+  return(result);
+}
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_cmSecureAccess.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,202 @@
+/**************************************************************************//**
+ * @file     core_cmSecureAccess.h
+ * @brief    CMSIS Cortex-M Core Secure Access Header File
+ * @version  XXX
+ * @date     10. June 2016
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2016 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CM_SECURE_ACCESS_H
+#define __CORE_CM_SECURE_ACCESS_H
+
+
+/* ###########################  Core Secure Access  ########################### */
+
+#ifdef FEATURE_UVISOR
+#include "uvisor-lib.h"
+
+/* Secure uVisor implementation. */
+
+/** Set the value at the target address.
+ *
+ * Equivalent to: `*address = value`.
+ * @param address[in]  Target address
+ * @param value[in]    Value to write at the address location.
+ */
+#define SECURE_WRITE(address, value) \
+    uvisor_write(main, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL)
+
+/** Get the value at the target address.
+ *
+ * @param address[in]  Target address
+ * @returns The value `*address`.
+ */
+#define SECURE_READ(address) \
+    uvisor_read(main, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL)
+
+/** Get the selected bits at the target address.
+ *
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `*address & mask`.
+ */
+#define SECURE_BITS_GET(address, mask) \
+    UVISOR_BITS_GET(main, UVISOR_RGW_SHARED, address, mask)
+
+/** Check the selected bits at the target address.
+ *
+ * @param address[in]  Address at which to check the bits
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `((*address & mask) == mask)`.
+ */
+#define SECURE_BITS_CHECK(address, mask) \
+    UVISOR_BITS_CHECK(main, UVISOR_RGW_SHARED, address, mask)
+
+/** Set the selected bits to 1 at the target address.
+ *
+ * Equivalent to: `*address |= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_SET(address, mask) \
+    UVISOR_BITS_SET(main, UVISOR_RGW_SHARED, address, mask)
+
+/** Clear the selected bits at the target address.
+ *
+ * Equivalent to: `*address &= ~mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_CLEAR(address, mask) \
+    UVISOR_BITS_CLEAR(main, UVISOR_RGW_SHARED, address, mask)
+
+/** Set the selected bits at the target address to the given value.
+ *
+ * Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @param value[in]    Value to write at the address location. Note: The value
+ *                     must be already shifted to the correct bit position
+ */
+#define SECURE_BITS_SET_VALUE(address, mask, value) \
+    UVISOR_BITS_SET_VALUE(main, UVISOR_RGW_SHARED, address, mask, value)
+
+/** Toggle the selected bits at the target address.
+ *
+ * Equivalent to: `*address ^= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_TOGGLE(address, mask) \
+    UVISOR_BITS_TOGGLE(main, UVISOR_RGW_SHARED, address, mask)
+
+#else
+
+/* Insecure fallback implementation. */
+
+/** Set the value at the target address.
+ *
+ * Equivalent to: `*address = value`.
+ * @param address[in]  Target address
+ * @param value[in]    Value to write at the address location.
+ */
+#define SECURE_WRITE(address, value) \
+    *(address) = (value)
+
+/** Get the value at the target address.
+ *
+ * @param address[in]  Target address
+ * @returns The value `*address`.
+ */
+#define SECURE_READ(address) \
+    (*(address))
+
+/** Get the selected bits at the target address.
+ *
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `*address & mask`.
+ */
+#define SECURE_BITS_GET(address, mask) \
+    (*(address) & (mask))
+
+/** Check the selected bits at the target address.
+ *
+ * @param address[in]  Address at which to check the bits
+ * @param mask[in]     Bits to select out of the target address
+ * @returns The value `((*address & mask) == mask)`.
+ */
+#define SECURE_BITS_CHECK(address, mask) \
+    ((*(address) & (mask)) == (mask))
+
+/** Set the selected bits to 1 at the target address.
+ *
+ * Equivalent to: `*address |= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_SET(address, mask) \
+    *(address) |= (mask)
+
+/** Clear the selected bits at the target address.
+ *
+ * Equivalent to: `*address &= ~mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_CLEAR(address, mask) \
+    *(address) &= ~(mask)
+
+/** Set the selected bits at the target address to the given value.
+ *
+ * Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ * @param value[in]    Value to write at the address location. Note: The value
+ *                     must be already shifted to the correct bit position
+ */
+#define SECURE_BITS_SET_VALUE(address, mask, value) \
+    *(address) = (*(address) & ~(mask)) | ((value) & (mask))
+
+/** Toggle the selected bits at the target address.
+ *
+ * Equivalent to: `*address ^= mask`.
+ * @param address[in]  Target address
+ * @param mask[in]     Bits to select out of the target address
+ */
+#define SECURE_BITS_TOGGLE(address, mask) \
+    *(address) ^= (mask)
+
+#endif
+
+#endif /* __CORE_CM_SECURE_ACCESS_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_cmSimd.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,698 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_sc000.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,865 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Control Register                    */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)(IRQn) < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)(IRQn) < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                        /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/cmsis/core_sc300.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1676 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27                                             /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27                                             /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25                                             /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+       uint32_t RESERVED1[129];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Control Register                    */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+       uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8)                       );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)IRQn < 0) {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)IRQn < 0) {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                             /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+    ITM->PORT[0].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/PeripheralNames.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,183 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART0,
+    UART1,
+    UART2,
+    UART3,
+    UART4,
+    UART5,
+    UART6,
+    UART7,
+} UARTName;
+
+// PWMType & 1 == 1 then have to use PWDTR[12] == 1
+typedef enum {
+    PWM1A  = 0,
+    PWM1B,
+    PWM1C,
+    PWM1D,
+    PWM1E,
+    PWM1F,
+    PWM1G,
+    PWM1H,
+    PWM2A  = 0x10,
+    PWM2B,
+    PWM2C,
+    PWM2D,
+    PWM2E,
+    PWM2F,
+    PWM2G,
+    PWM2H,
+} PWMType;
+
+typedef enum {
+    TIOC0A  = 0,
+    TIOC0B,
+    TIOC0C,
+    TIOC0D,
+    TIOC1A = 0x10,
+    TIOC1B,
+    TIOC2A = 0x20,
+    TIOC2B,
+    TIOC3A = 0x30,
+    TIOC3B,
+    TIOC3C,
+    TIOC3D,
+    TIOC4A = 0x40,
+    TIOC4B,
+    TIOC4C,
+    TIOC4D,
+} MTU2_PWMType;
+
+typedef enum {
+    PWM0_PIN  = 0,
+    PWM1_PIN,
+    PWM2_PIN,
+    PWM3_PIN,
+    PWM4_PIN,
+    PWM5_PIN,
+    PWM6_PIN,
+    PWM7_PIN,
+    PWM8_PIN,
+    PWM9_PIN,
+    PWM10_PIN,
+    PWM11_PIN,
+    PWM12_PIN,
+#ifdef MAX_PERI
+    PWM13_PIN,
+    PWM14_PIN,
+    PWM15_PIN,
+    MTU2_PWM0_PIN = 0x20,
+    MTU2_PWM1_PIN,
+    MTU2_PWM2_PIN,
+    MTU2_PWM3_PIN,
+    MTU2_PWM4_PIN,
+    MTU2_PWM5_PIN,
+    MTU2_PWM6_PIN,
+    MTU2_PWM7_PIN,
+    MTU2_PWM8_PIN,
+    MTU2_PWM9_PIN,
+    MTU2_PWM10_PIN,
+    MTU2_PWM11_PIN,
+    MTU2_PWM12_PIN,
+    MTU2_PWM13_PIN,
+    MTU2_PWM14_PIN,
+    MTU2_PWM15_PIN,
+    MTU2_PWM16_PIN,
+    MTU2_PWM17_PIN,
+    MTU2_PWM18_PIN,
+    MTU2_PWM19_PIN,
+    MTU2_PWM20_PIN,
+    MTU2_PWM21_PIN,
+    MTU2_PWM22_PIN,
+    MTU2_PWM23_PIN,
+    MTU2_PWM23_PIN,
+    MTU2_PWM24_PIN,
+    MTU2_PWM25_PIN,
+    MTU2_PWM26_PIN,
+#else
+    MTU2_PWM0_PIN = 0x20,
+    MTU2_PWM1_PIN,
+    MTU2_PWM2_PIN,
+    MTU2_PWM3_PIN,
+    MTU2_PWM4_PIN,
+    MTU2_PWM5_PIN,
+    MTU2_PWM6_PIN,
+    MTU2_PWM7_PIN,
+    MTU2_PWM8_PIN,
+    MTU2_PWM9_PIN,
+    MTU2_PWM10_PIN,
+    MTU2_PWM11_PIN,
+#endif
+} PWMName;
+
+typedef enum {
+    AN0= 0,
+    AN1= 1,
+    AN2= 2,
+    AN3= 3,
+    AN4= 4,
+    AN5= 5,
+    AN6= 6,
+    AN7= 7,
+} ADCName;
+
+typedef enum {
+    SPI_1 = 1,
+    SPI_2,
+    SPI_3,
+    SPI_4,
+} SPIName;
+
+typedef enum {
+    I2C_0 = 0,
+    I2C_1,
+    I2C_2,
+    I2C_3 
+} I2CName;
+
+typedef enum {
+    CAN_0 = 0,
+    CAN_1,
+    CAN_2,
+    CAN_3, 
+    CAN_4
+} CANName;
+
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART3
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/PinNames.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  4
+
+typedef enum {
+    P0_0 = 0,   P0_1, P0_2, P0_3, P0_4, P0_5,
+    P1_0 = 16,  P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15,
+    P2_0,       P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15,
+    P3_0,       P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15,
+    P4_0,       P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15,
+    P5_0,       P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, P5_8, P5_9, P5_10,
+    P6_0 = 96,  P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, P6_8, P6_9, P6_10, P6_11, P6_12, P6_13, P6_14, P6_15,
+    P7_0,       P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7, P7_8, P7_9, P7_10, P7_11, P7_12, P7_13, P7_14, P7_15,
+    P8_0,       P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7, P8_8, P8_9, P8_10, P8_11, P8_12, P8_13, P8_14, P8_15,
+    P9_0,       P9_1, P9_2, P9_3, P9_4, P9_5, P9_6, P9_7,
+    
+    // mbed Pin Names
+    LED1 = P7_1,
+    LED_RED = LED1,
+    // mbed led alias to keep some test happy, becasue physically they are no LED2,LED3 & LED4 on the board
+    LED2 = LED1,
+    LED3 = LED2,
+    LED4 = LED3,
+
+    I2C_SCL = P1_0,
+    I2C_SDA = P1_1,
+
+    USBTX = P8_8,
+    USBRX = P8_9,
+
+    //USER_BUTTON0 = P6_0,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullUp = 0,
+    PullDown = 3,
+    PullNone = 2,
+    OpenDrain = 4,
+    PullDefault = PullDown
+} PinMode;
+
+#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0x0f)
+#define PINNO(pin) ((pin)&0x0f)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/PortNames.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+    Port1 = 1,
+    Port3 = 3,
+    Port4 = 4,
+    Port5 = 5,
+    Port7 = 7,
+    Port8 = 8,
+    Port9 = 9
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/analogin_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,134 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#include "cmsis.h"
+#include "pinmap.h"
+
+#include "adc_iodefine.h"
+#include "cpg_iodefine.h"
+
+#define ANALOGIN_MEDIAN_FILTER      0
+
+#ifdef MAX_PERI
+static const PinMap PinMap_ADC[] = {
+    {P1_8,  AN0, 1},
+    {P1_9,  AN1, 1},
+    {P1_10, AN2, 1},
+    {P1_11, AN3, 1},
+    {P1_12, AN4, 1},
+    {P1_13, AN5, 1},
+    {P1_14, AN6, 1},
+    {P1_15, AN7, 1},
+    {NC,    NC,  0}
+};
+#else
+static const PinMap PinMap_ADC[] = {
+    {P1_8,  AN0, 1},
+    {P1_9,  AN1, 1},
+    {P1_10, AN2, 1},
+    {P1_11, AN3, 1},
+    {P1_12, AN4, 1},
+    {P1_13, AN5, 1},
+    {P1_15, AN7, 1},
+    {NC,    NC,  0}
+};
+#endif
+
+static volatile uint16_t *ADCDR[] = {
+    &ADCADDRA,
+    &ADCADDRB,
+    &ADCADDRC,
+    &ADCADDRD,
+    &ADCADDRE,
+    &ADCADDRF,
+    &ADCADDRG,
+    &ADCADDRH,
+};
+
+void analogin_init(analogin_t *obj, PinName pin) {
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName)NC);
+
+    CPGSTBCR3 &= ~(1 << 1);
+    CPGSTBCR6 &= ~(1 << 7);
+
+    // 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0 
+    //    [8:6] CKS 010 :: 340tclk 
+    //    [5:3] MDS 000 :: single mode 
+    //    [2:0] CH  000 :: AN0 
+    ADCADCSR = 0x0080; 
+
+    pinmap_pinout(pin, PinMap_ADC);
+}
+
+static inline uint32_t adc_read(analogin_t *obj) {
+    volatile uint16_t data;
+
+    // Select the appropriate channel and start conversion
+    ADCADCSR &= 0xfff8;
+    ADCADCSR |= (1 << 13 | (obj->adc & 0x7));
+
+    // Wait end of conversion
+    do {
+        data = ADCADCSR;
+    } while (((data & (1 << 15)) == 0) || ((data & (1 << 13)) != 0));
+
+    // clear flag
+    ADCADCSR &= ~(1 << 15);
+
+    return ((*(ADCDR[obj->adc])) >> 4) & 0x0FFF;   // 12 bits range
+}
+
+#if ANALOGIN_MEDIAN_FILTER
+static inline void order(uint32_t *a, uint32_t *b) {
+    if (*a > *b) {
+        uint32_t t = *a;
+        *a = *b;
+        *b = t;
+    }
+}
+#endif
+
+static inline uint32_t adc_read_u32(analogin_t *obj) {
+    uint32_t value;
+#if ANALOGIN_MEDIAN_FILTER
+    uint32_t v1 = adc_read(obj);
+    uint32_t v2 = adc_read(obj);
+    uint32_t v3 = adc_read(obj);
+    order(&v1, &v2);
+    order(&v2, &v3);
+    order(&v1, &v2);
+    value = v2;
+#else
+    value = adc_read(obj);
+#endif
+    return value;
+}
+
+uint16_t analogin_read_u16(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+
+    return (value << 4) | ((value >> 8) & 0x000F); // 12-bit to 16-bit conversion
+}
+
+float analogin_read(analogin_t *obj) {
+    uint32_t value = adc_read_u32(obj);
+
+    return (float)value * (1.0f / (float)0x0FFF);  // 12 bits range
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/can_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,1027 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "mbed_assert.h"
+#include "can_api.h"
+#include "RZ_A1_Init.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "rscan0_iodefine.h"
+#include "r_typedefs.h"
+#include "VKRZA1H.h"
+
+#define CAN_NUM         5
+#define CAN_SND_RCV     2
+#define IRQ_NUM         8
+
+static void can_rec_irq(uint32_t ch);
+static void can_trx_irq(uint32_t ch);
+static void can_err_irq(uint32_t ch, CanIrqType type);
+static void can0_rec_irq(void);
+static void can1_rec_irq(void);
+static void can2_rec_irq(void);
+static void can3_rec_irq(void);
+static void can4_rec_irq(void);
+static void can0_trx_irq(void);
+static void can1_trx_irq(void);
+static void can2_trx_irq(void);
+static void can3_trx_irq(void);
+static void can4_trx_irq(void);
+static void can0_err_warning_irq(void);
+static void can1_err_warning_irq(void);
+static void can2_err_warning_irq(void);
+static void can3_err_warning_irq(void);
+static void can4_err_warning_irq(void);
+static void can0_overrun_irq(void);
+static void can1_overrun_irq(void);
+static void can2_overrun_irq(void);
+static void can3_overrun_irq(void);
+static void can4_overrun_irq(void);
+static void can0_passive_irq(void);
+static void can1_passive_irq(void);
+static void can2_passive_irq(void);
+static void can3_passive_irq(void);
+static void can4_passive_irq(void);
+static void can0_arb_lost_irq(void);
+static void can1_arb_lost_irq(void);
+static void can2_arb_lost_irq(void);
+static void can3_arb_lost_irq(void);
+static void can4_arb_lost_irq(void);
+static void can0_bus_err_irq(void);
+static void can1_bus_err_irq(void);
+static void can2_bus_err_irq(void);
+static void can3_bus_err_irq(void);
+static void can4_bus_err_irq(void);
+static void can_reset_reg(can_t *obj);
+static void can_reset_recv_rule(can_t *obj);
+static void can_reset_buffer(can_t *obj);
+static void can_reconfigure_channel(void);
+static void can_set_frequency(can_t *obj, int f);
+static void can_set_global_mode(int mode);
+static void can_set_channel_mode(uint32_t ch, int mode);
+
+typedef enum {
+    CAN_SEND = 0,
+    CAN_RECV
+} CANfunc;
+
+typedef enum {
+    GL_OPE = 0,
+    GL_RESET,
+    GL_TEST
+} Globalmode;
+
+typedef enum {
+    CH_COMM = 0,
+    CH_RESET,
+    CH_HOLD
+} Channelmode;
+
+typedef struct {
+    IRQn_Type   int_num;    /* Interrupt number */
+    IRQHandler  handler;    /* Interrupt handler */
+} can_info_int_t;
+
+static can_irq_handler irq_handler;
+static uint32_t can_irq_id[CAN_NUM];
+static int can_initialized[CAN_NUM] = {0};
+
+#ifdef MAX_PERI
+static const PinMap PinMap_CAN_RD[] = {
+    {P7_8  , CAN_0, 4},
+    {P9_1  , CAN_0, 3},
+    {P1_4  , CAN_1, 3},
+    {P5_9  , CAN_1, 5},
+    {P7_11 , CAN_1, 4},
+    {P4_9  , CAN_2, 6},
+    {P6_4  , CAN_2, 3},
+    {P7_2  , CAN_2, 5},
+    {P2_12 , CAN_3, 5},
+    {P4_2  , CAN_3, 4},
+    {P1_5  , CAN_4, 3},
+    {P2_14 , CAN_4, 5},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_CAN_TD[] = {
+    {P7_9  , CAN_0, 4},
+    {P9_0  , CAN_0, 3},
+    {P5_10 , CAN_1, 5},
+    {P7_10 , CAN_1, 4},
+    {P4_8  , CAN_2, 6},
+    {P6_5  , CAN_2, 3},
+    {P7_3  , CAN_2, 5},
+    {P2_13 , CAN_3, 5},
+    {P4_3  , CAN_3, 4},
+    {P4_11 , CAN_4, 6},
+    {P8_10 , CAN_4, 5},
+    {NC    , NC   , 0}
+};
+#else
+static const PinMap PinMap_CAN_RD[] = {
+    {P9_1  , CAN_0, 3},
+    {P1_4  , CAN_1, 3},
+    {P5_9  , CAN_1, 5},
+    {P4_2  , CAN_3, 4},
+    {P1_5  , CAN_4, 3},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_CAN_TD[] = {
+    {P9_0  , CAN_0, 3},
+    {P5_10 , CAN_1, 5},
+    {P4_3  , CAN_3, 4},
+    {P8_10 , CAN_4, 5},
+    {NC    , NC   , 0}
+};
+#endif
+
+static __IO uint32_t *CTR_MATCH[] = {
+    &RSCAN0C0CTR,
+    &RSCAN0C1CTR,
+    &RSCAN0C2CTR,
+    &RSCAN0C3CTR,
+    &RSCAN0C4CTR,
+};
+
+static __IO uint32_t *CFG_MATCH[] = {
+    &RSCAN0C0CFG,
+    &RSCAN0C1CFG,
+    &RSCAN0C2CFG,
+    &RSCAN0C3CFG,
+    &RSCAN0C4CFG,
+};
+
+static __IO uint32_t *RFCC_MATCH[] = {
+    &RSCAN0RFCC0,
+    &RSCAN0RFCC1,
+    &RSCAN0RFCC2,
+    &RSCAN0RFCC3,
+    &RSCAN0RFCC4,
+    &RSCAN0RFCC5,
+    &RSCAN0RFCC6,
+    &RSCAN0RFCC7
+};
+
+static __IO uint32_t *TXQCC_MATCH[] = {
+    &RSCAN0TXQCC0,
+    &RSCAN0TXQCC1,
+    &RSCAN0TXQCC2,
+    &RSCAN0TXQCC3,
+    &RSCAN0TXQCC4,
+};
+
+static __IO uint32_t *THLCC_MATCH[] = {
+    &RSCAN0THLCC0,
+    &RSCAN0THLCC1,
+    &RSCAN0THLCC2,
+    &RSCAN0THLCC3,
+    &RSCAN0THLCC4,
+};
+
+static __IO uint32_t *STS_MATCH[] = {
+    &RSCAN0C0STS,
+    &RSCAN0C1STS,
+    &RSCAN0C2STS,
+    &RSCAN0C3STS,
+    &RSCAN0C4STS,
+};
+
+static __IO uint32_t *ERFL_MATCH[] = {
+    &RSCAN0C0ERFL,
+    &RSCAN0C1ERFL,
+    &RSCAN0C2ERFL,
+    &RSCAN0C3ERFL,
+    &RSCAN0C4ERFL,
+};
+
+static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFCC0 , &RSCAN0CFCC1  },
+    { &RSCAN0CFCC3 , &RSCAN0CFCC4  },
+    { &RSCAN0CFCC6 , &RSCAN0CFCC7  },
+    { &RSCAN0CFCC9 , &RSCAN0CFCC10 },
+    { &RSCAN0CFCC12, &RSCAN0CFCC13 }
+};
+
+static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFSTS0 , &RSCAN0CFSTS1  },
+    { &RSCAN0CFSTS3 , &RSCAN0CFSTS4  },
+    { &RSCAN0CFSTS6 , &RSCAN0CFSTS7  },
+    { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 },
+    { &RSCAN0CFSTS12, &RSCAN0CFSTS13 }
+};
+
+static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1  },
+    { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4  },
+    { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7  },
+    { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 },
+    { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 }
+};
+
+static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFID0 , &RSCAN0CFID1  },
+    { &RSCAN0CFID3 , &RSCAN0CFID4  },
+    { &RSCAN0CFID6 , &RSCAN0CFID7  },
+    { &RSCAN0CFID9 , &RSCAN0CFID10 },
+    { &RSCAN0CFID12, &RSCAN0CFID13 }
+};
+
+static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFPTR0 , &RSCAN0CFPTR1  },
+    { &RSCAN0CFPTR3 , &RSCAN0CFPTR4  },
+    { &RSCAN0CFPTR6 , &RSCAN0CFPTR7  },
+    { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 },
+    { &RSCAN0CFPTR12, &RSCAN0CFPTR13 }
+};
+
+static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFDF00 , &RSCAN0CFDF01  },
+    { &RSCAN0CFDF03 , &RSCAN0CFDF04  },
+    { &RSCAN0CFDF06 , &RSCAN0CFDF07  },
+    { &RSCAN0CFDF09 , &RSCAN0CFDF010 },
+    { &RSCAN0CFDF012, &RSCAN0CFDF013 }
+};
+
+static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = {
+    { &RSCAN0CFDF10 , &RSCAN0CFDF11  },
+    { &RSCAN0CFDF13 , &RSCAN0CFDF14  },
+    { &RSCAN0CFDF16 , &RSCAN0CFDF17  },
+    { &RSCAN0CFDF19 , &RSCAN0CFDF110 },
+    { &RSCAN0CFDF112, &RSCAN0CFDF113 }
+};
+
+static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = 
+{
+    {   /* ch0 */
+        { INTRCAN0REC_IRQn, can0_rec_irq         }, /* RxIrq */
+        { INTRCAN0TRX_IRQn, can0_trx_irq         }, /* TxIrq */
+        { INTRCAN0ERR_IRQn, can0_err_warning_irq }, /* EwIrq */
+        { INTRCAN0ERR_IRQn, can0_overrun_irq     }, /* DoIrq */
+        { INTRCAN0ERR_IRQn, NULL                 }, /* WuIrq(not supported) */
+        { INTRCAN0ERR_IRQn, can0_passive_irq     }, /* EpIrq */
+        { INTRCAN0ERR_IRQn, can0_arb_lost_irq    }, /* AlIrq */
+        { INTRCAN0ERR_IRQn, can0_bus_err_irq     }  /* BeIrq */
+    },
+    {   /* ch1 */
+        { INTRCAN1REC_IRQn, can1_rec_irq         }, /* RxIrq */
+        { INTRCAN1TRX_IRQn, can1_trx_irq         }, /* TxIrq */
+        { INTRCAN1ERR_IRQn, can1_err_warning_irq }, /* EwIrq */
+        { INTRCAN1ERR_IRQn, can1_overrun_irq     }, /* DoIrq */
+        { INTRCAN1ERR_IRQn, NULL                 }, /* WuIrq(not supported) */
+        { INTRCAN1ERR_IRQn, can1_passive_irq     }, /* EpIrq */
+        { INTRCAN1ERR_IRQn, can1_arb_lost_irq    }, /* AlIrq */
+        { INTRCAN1ERR_IRQn, can1_bus_err_irq     }  /* BeIrq */
+    },
+    {   /* ch2 */
+        { INTRCAN2REC_IRQn, can2_rec_irq         }, /* RxIrq */
+        { INTRCAN2TRX_IRQn, can2_trx_irq         }, /* TxIrq */
+        { INTRCAN2ERR_IRQn, can2_err_warning_irq }, /* EwIrq */
+        { INTRCAN2ERR_IRQn, can2_overrun_irq     }, /* DoIrq */
+        { INTRCAN2ERR_IRQn, NULL                 }, /* WuIrq(not supported) */
+        { INTRCAN2ERR_IRQn, can2_passive_irq     }, /* EpIrq */
+        { INTRCAN2ERR_IRQn, can2_arb_lost_irq    }, /* AlIrq */
+        { INTRCAN2ERR_IRQn, can2_bus_err_irq     }  /* BeIrq */
+    },
+    {   /* ch3 */
+        { INTRCAN3REC_IRQn, can3_rec_irq         }, /* RxIrq */
+        { INTRCAN3TRX_IRQn, can3_trx_irq         }, /* TxIrq */
+        { INTRCAN3ERR_IRQn, can3_err_warning_irq }, /* EwIrq */
+        { INTRCAN3ERR_IRQn, can3_overrun_irq     }, /* DoIrq */
+        { INTRCAN3ERR_IRQn, NULL                 }, /* WuIrq(not supported) */
+        { INTRCAN3ERR_IRQn, can3_passive_irq     }, /* EpIrq */
+        { INTRCAN3ERR_IRQn, can3_arb_lost_irq    }, /* AlIrq */
+        { INTRCAN3ERR_IRQn, can3_bus_err_irq     }  /* BeIrq */
+    },
+    {   /* ch4 */
+        { INTRCAN4REC_IRQn, can4_rec_irq         }, /* RxIrq */
+        { INTRCAN4TRX_IRQn, can4_trx_irq         }, /* TxIrq */
+        { INTRCAN4ERR_IRQn, can4_err_warning_irq }, /* EwIrq */
+        { INTRCAN4ERR_IRQn, can4_overrun_irq     }, /* DoIrq */
+        { INTRCAN4ERR_IRQn, NULL                 }, /* WuIrq(not supported) */
+        { INTRCAN4ERR_IRQn, can4_passive_irq     }, /* EpIrq */
+        { INTRCAN4ERR_IRQn, can4_arb_lost_irq    }, /* AlIrq */
+        { INTRCAN4ERR_IRQn, can4_bus_err_irq     }  /* BeIrq */
+    }
+};
+
+static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0;
+static __IO uint32_t *dmy_gaflm  = &RSCAN0GAFLM0;
+static __IO uint32_t *dmy_gaflp0 = &RSCAN0GAFLP00;
+static __IO uint32_t *dmy_gaflp1 = &RSCAN0GAFLP10;
+
+void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    can_irq_id[obj->ch] = id;
+}
+
+void can_irq_free(can_t *obj) {
+    can_irq_id[obj->ch] = 0;
+}
+
+void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
+    __IO uint32_t *dmy_ctr;
+
+    /* Wake-up Irq is not supported */
+    if (type != IRQ_WAKEUP) {
+        if (enable) {
+            dmy_ctr = CTR_MATCH[obj->ch];
+            if (type == IRQ_ERROR) {
+                /* EWIE interrupts is enable */
+                *dmy_ctr |= 0x00000200;
+            } else if (type == IRQ_OVERRUN) {
+                /* OLIE interrupts is enable */
+                *dmy_ctr |= 0x00002000;
+            } else if (type == IRQ_PASSIVE) {
+                /* EPIE interrupts is enable */
+                *dmy_ctr |= 0x00000400;
+            } else if (type == IRQ_ARB) {
+                /* ALIE interrupts is enable */
+                *dmy_ctr |= 0x00008000;
+            } else if (type == IRQ_BUS) {
+                /* BEIE interrupts is enable */
+                *dmy_ctr |= 0x00000100;
+            }
+            InterruptHandlerRegister(can_int_info[obj->ch][type].int_num, can_int_info[obj->ch][type].handler);
+            GIC_SetPriority(can_int_info[obj->ch][type].int_num, 5);
+            GIC_EnableIRQ(can_int_info[obj->ch][type].int_num);
+        } else {
+            GIC_DisableIRQ(can_int_info[obj->ch][type].int_num);
+        }
+    }
+}
+
+static void can_rec_irq(uint32_t ch) {
+    __IO uint32_t *dmy_cfsts;
+
+    dmy_cfsts = CFSTS_TBL[ch][CAN_RECV];
+    *dmy_cfsts &= 0xFFFFFFF7;           // Clear CFRXIF
+
+    irq_handler(can_irq_id[ch], IRQ_RX);
+}
+
+static void can_trx_irq(uint32_t ch) {
+    __IO uint32_t *dmy_cfsts;
+
+    dmy_cfsts = CFSTS_TBL[ch][CAN_SEND];
+    *dmy_cfsts &= 0xFFFFFFEF;           // Clear CFTXIF
+
+    irq_handler(can_irq_id[ch], IRQ_TX);
+}
+
+static void can_err_irq(uint32_t ch, CanIrqType type) {
+    __IO uint32_t *dmy_erfl;
+    int val = 1;
+    
+    dmy_erfl = ERFL_MATCH[ch];
+    switch (type) {
+        case IRQ_ERROR:
+            *dmy_erfl &= 0xFFFFFFFD;    // Clear EWF
+            break;
+        case IRQ_OVERRUN:
+            *dmy_erfl &= 0xFFFFFFDF;    // Clear OVLF
+            break;
+        case IRQ_PASSIVE:
+            *dmy_erfl &= 0xFFFFFFFB;    // Clear EPF
+            break;
+        case IRQ_ARB:
+            *dmy_erfl &= 0xFFFFFF7F;    // Clear ALF
+            break;
+        case IRQ_BUS:
+            *dmy_erfl &= 0xFFFF00FF;    // Clear ADERRAB0ERRAB1ERRACERRAAERRAFERRASERR
+            *dmy_erfl &= 0xFFFFFFFE;    // Clear BEF
+            break;
+        case IRQ_WAKEUP:
+            /* not supported */
+            /* fall through */
+        default:
+            val = 0;
+            break;
+    }
+    if (val == 1) {
+        irq_handler(can_irq_id[ch], type);
+    }
+}
+
+static void can0_rec_irq(void) {
+    can_rec_irq(CAN_0);
+}
+
+static void can1_rec_irq(void) {
+    can_rec_irq(CAN_1);
+}
+
+static void can2_rec_irq(void) {
+    can_rec_irq(CAN_2);
+}
+
+static void can3_rec_irq(void) {
+    can_rec_irq(CAN_3);
+}
+
+static void can4_rec_irq(void) {
+    can_rec_irq(CAN_4);
+}
+
+static void can0_trx_irq(void) {
+    can_trx_irq(CAN_0);
+}
+
+static void can1_trx_irq(void) {
+    can_trx_irq(CAN_1);
+}
+
+static void can2_trx_irq(void) {
+    can_trx_irq(CAN_2);
+}
+
+static void can3_trx_irq(void) {
+    can_trx_irq(CAN_3);
+}
+
+static void can4_trx_irq(void) {
+    can_trx_irq(CAN_4);
+}
+
+static void can0_err_warning_irq(void) {
+    can_err_irq(CAN_0, IRQ_ERROR);
+}
+
+static void can1_err_warning_irq(void) {
+    can_err_irq(CAN_1, IRQ_ERROR);
+}
+
+static void can2_err_warning_irq(void) {
+    can_err_irq(CAN_2, IRQ_ERROR);
+}
+
+static void can3_err_warning_irq(void) {
+    can_err_irq(CAN_3, IRQ_ERROR);
+}
+
+static void can4_err_warning_irq(void) {
+    can_err_irq(CAN_4, IRQ_ERROR);
+}
+
+static void can0_overrun_irq(void) {
+    can_err_irq(CAN_0, IRQ_OVERRUN);
+}
+
+static void can1_overrun_irq(void) {
+    can_err_irq(CAN_1, IRQ_OVERRUN);
+}
+
+static void can2_overrun_irq(void) {
+    can_err_irq(CAN_2, IRQ_OVERRUN);
+}
+
+static void can3_overrun_irq(void) {
+    can_err_irq(CAN_3, IRQ_OVERRUN);
+}
+
+static void can4_overrun_irq(void) {
+    can_err_irq(CAN_4, IRQ_OVERRUN);
+}
+
+static void can0_passive_irq(void) {
+    can_err_irq(CAN_0, IRQ_PASSIVE);
+}
+
+static void can1_passive_irq(void) {
+    can_err_irq(CAN_1, IRQ_PASSIVE);
+}
+
+static void can2_passive_irq(void) {
+    can_err_irq(CAN_2, IRQ_PASSIVE);
+}
+
+static void can3_passive_irq(void) {
+    can_err_irq(CAN_3, IRQ_PASSIVE);
+}
+
+static void can4_passive_irq(void) {
+    can_err_irq(CAN_4, IRQ_PASSIVE);
+}
+
+static void can0_arb_lost_irq(void) {
+    can_err_irq(CAN_0, IRQ_ARB);
+}
+
+static void can1_arb_lost_irq(void) {
+    can_err_irq(CAN_1, IRQ_ARB);
+}
+
+static void can2_arb_lost_irq(void) {
+    can_err_irq(CAN_2, IRQ_ARB);
+}
+
+static void can3_arb_lost_irq(void) {
+    can_err_irq(CAN_3, IRQ_ARB);
+}
+
+static void can4_arb_lost_irq(void) {
+    can_err_irq(CAN_4, IRQ_ARB);
+}
+
+static void can0_bus_err_irq(void) {
+    can_err_irq(CAN_0, IRQ_BUS);
+}
+
+static void can1_bus_err_irq(void) {
+    can_err_irq(CAN_1, IRQ_BUS);
+}
+
+static void can2_bus_err_irq(void) {
+    can_err_irq(CAN_2, IRQ_BUS);
+}
+
+static void can3_bus_err_irq(void) {
+    can_err_irq(CAN_3, IRQ_BUS);
+}
+
+static void can4_bus_err_irq(void) {
+    can_err_irq(CAN_4, IRQ_BUS);
+}
+
+void can_init(can_t *obj, PinName rd, PinName td) {
+    __IO uint32_t *dmy_ctr;
+
+    /* determine the CAN to use */
+    uint32_t can_rx = pinmap_peripheral(rd, PinMap_CAN_RD);
+    uint32_t can_tx = pinmap_peripheral(td, PinMap_CAN_TD);
+    obj->ch = pinmap_merge(can_tx, can_rx);
+    MBED_ASSERT((int)obj->ch != NC);
+
+    /* enable CAN clock */
+    CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP32);
+    /* Has CAN RAM initialisation completed ? */
+    while ((RSCAN0GSTS & 0x08) == 0x08) {
+        __NOP();
+    }
+    /* clear Global Stop mode bit */
+    RSCAN0GCTR &= 0xFFFFFFFB;
+    /* clear Channel Stop mode bit */
+    dmy_ctr = CTR_MATCH[obj->ch];
+    *dmy_ctr &= 0xFFFFFFFB;
+    /* Enter global reset mode */
+    can_set_global_mode(GL_RESET);
+    /* Enter channel reset mode */
+    can_set_channel_mode(obj->ch, CH_RESET);
+    /* reset register */
+    can_reset_reg(obj);
+
+    can_initialized[obj->ch] = 1;
+    /* reconfigure channel which is already initialized */
+    can_reconfigure_channel();
+    
+    /* pin out the can pins */
+    pinmap_pinout(rd, PinMap_CAN_RD);
+    pinmap_pinout(td, PinMap_CAN_TD);
+}
+
+void can_free(can_t *obj) {
+    /* disable CAN clock */
+    CPGSTBCR3 |= CPG_STBCR3_BIT_MSTP32;
+}
+
+int can_frequency(can_t *obj, int f) {
+    int retval = 0;
+    
+    if (f <= 1000000) {
+        /* less than 1Mhz */
+        /* set Channel Reset mode */
+        can_set_channel_mode(obj->ch, CH_RESET);
+        can_set_frequency(obj, f);
+        /* set Channel Communication mode */
+        can_set_channel_mode(obj->ch, CH_COMM);
+        retval = 1;
+    }
+
+    return retval;
+}
+
+void can_reset(can_t *obj) {
+    /* Enter global reset mode */
+    can_set_global_mode(GL_RESET);
+    /* Enter channel reset mode */
+    can_set_channel_mode(obj->ch, CH_RESET);
+    /* reset register */
+    can_reset_reg(obj);
+    /* reconfigure channel which is already initialized */
+    can_reconfigure_channel();
+}
+
+int can_write(can_t *obj, CAN_Message msg, int cc) {
+    __IO uint32_t *dmy_sts;
+    __IO uint32_t *dmy_cfsts;
+    __IO uint32_t *dmy_cfid;
+    __IO uint32_t *dmy_cfptr;
+    __IO uint32_t *dmy_cfdf0;
+    __IO uint32_t *dmy_cfdf1;
+    __IO uint32_t *dmy_cfpctr;
+    int retval = 0;
+
+    /* Wait to become channel communication mode */
+    dmy_sts = STS_MATCH[obj->ch];
+    while ((*dmy_sts & 0x07) != 0) {
+        __NOP();
+    }
+    
+    if (((msg.format == CANStandard) && (msg.id <= 0x07FF)) || ((msg.format == CANExtended) && (msg.id <= 0x03FFFF))) {
+        /* send/receive FIFO buffer isn't full */
+        dmy_cfsts = CFSTS_TBL[obj->ch][CAN_SEND];
+        if ((*dmy_cfsts & 0x02) != 0x02) {
+            /* set format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+            dmy_cfid = CFID_TBL[obj->ch][CAN_SEND];
+            *dmy_cfid = ((msg.format << 31) | (msg.type << 30));
+            if (msg.format == CANStandard) {
+                *dmy_cfid |= (msg.id & 0x07FF);
+            } else {
+                *dmy_cfid |= ((msg.id & 0x03FFFF) << 11);
+            }
+            /* set length */
+            dmy_cfptr = CFPTR_TBL[obj->ch][CAN_SEND];
+            *dmy_cfptr = msg.len << 28;
+            /* set data */
+            dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_SEND];
+            memcpy((void *)dmy_cfdf0, &msg.data[0], 4);
+            dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_SEND];
+            memcpy((void *)dmy_cfdf1, &msg.data[4], 4);
+            /* send request */
+            dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_SEND];
+            *dmy_cfpctr = 0xFF;
+            retval = 1;
+        }
+    }
+    
+    return retval;
+}
+
+int can_read(can_t *obj, CAN_Message *msg, int handle) {
+    __IO uint32_t *dmy_sts;
+    __IO uint32_t *dmy_cfsts;
+    __IO uint32_t *dmy_cfid;
+    __IO uint32_t *dmy_cfptr;
+    __IO uint32_t *dmy_cfdf0;
+    __IO uint32_t *dmy_cfdf1;
+    __IO uint32_t *dmy_cfpctr;
+    int retval = 0;
+
+    /* Wait to become channel communication mode */
+    dmy_sts = STS_MATCH[obj->ch];
+    while ((*dmy_sts & 0x07) != 0) {
+        __NOP();
+    }
+    
+    /* send/receive FIFO buffer isn't empty */
+    dmy_cfsts = CFSTS_TBL[obj->ch][CAN_RECV];
+    while ((*dmy_cfsts & 0x01) != 0x01) {
+        /* get format, frame type and send/receive FIFO buffer ID(b10-0 or b28-11) */
+        dmy_cfid = CFID_TBL[obj->ch][CAN_RECV];
+        msg->format = (CANFormat)(*dmy_cfid >> 31);
+        msg->type = (CANType)(*dmy_cfid >> 30);
+        if (msg->format == CANStandard) {
+            msg->id = (*dmy_cfid & 0x07FF);
+        } else {
+            msg->id = ((*dmy_cfid >> 11) & 0x03FFFF);
+        }
+        /* get length */
+        dmy_cfptr = CFPTR_TBL[obj->ch][CAN_RECV];
+        msg->len = (unsigned char)(*dmy_cfptr >> 28);
+        /* get data */
+        dmy_cfdf0 = CFDF0_TBL[obj->ch][CAN_RECV];
+        memcpy(&msg->data[0], (void *)dmy_cfdf0, 4);
+        dmy_cfdf1 = CFDF1_TBL[obj->ch][CAN_RECV];
+        memcpy(&msg->data[4], (void *)dmy_cfdf1, 4);
+        /* receive(next data) request */
+        dmy_cfpctr = CFPCTR_TBL[obj->ch][CAN_RECV];
+        *dmy_cfpctr = 0xFF;
+        retval = 1;
+    }
+    
+    return retval;
+}
+
+unsigned char can_rderror(can_t *obj) {
+    __IO uint32_t *dmy_sts;
+    
+    dmy_sts = STS_MATCH[obj->ch];
+    return (unsigned char)((*dmy_sts >> 16) & 0xFF);
+}
+
+unsigned char can_tderror(can_t *obj) {
+    __IO uint32_t *dmy_sts;
+    
+    dmy_sts = STS_MATCH[obj->ch];
+    return (unsigned char)((*dmy_sts >> 24) & 0xFF);
+}
+
+int can_mode(can_t *obj, CanMode mode) {
+    __IO uint32_t *dmy_ctr;
+    __IO uint32_t *dmy_sts;
+    __IO uint32_t *dmy_cfcc;
+    int ch_cnt;
+    can_t *tmp_obj;
+    tmp_obj = obj;
+    int retval = 1;
+    
+    switch (mode) {
+        case MODE_RESET:
+            can_set_global_mode(GL_RESET);
+            can_set_channel_mode(obj->ch, CH_RESET);
+            for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
+                can_initialized[ch_cnt] = 0;
+            }
+            break;
+        case MODE_NORMAL:
+            can_set_global_mode(GL_OPE);
+            can_set_channel_mode(obj->ch, CH_COMM);
+            break;
+        case MODE_SILENT:
+            can_set_channel_mode(obj->ch, CH_HOLD);
+            /* set listen only mode, enable communication test mode */
+            dmy_ctr = CTR_MATCH[obj->ch];
+            *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
+            can_set_channel_mode(obj->ch, CH_COMM);
+            break;
+        case MODE_TEST_LOCAL:
+            can_set_channel_mode(obj->ch, CH_HOLD);
+            /* set self test mode 0, enable communication test mode */
+            dmy_ctr = CTR_MATCH[obj->ch];
+            *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x05000000);
+            can_set_channel_mode(obj->ch, CH_COMM);
+            break;
+        case MODE_TEST_GLOBAL:
+            /* set the channel between the communication test on channel 1 and channel 2 */
+            /* set Channel Hold mode */
+            for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) {
+                dmy_sts = STS_MATCH[tmp_obj->ch];
+                if ((*dmy_sts & 0x04) == 0x04) {
+                    /* Channel Stop mode */
+                    /* clear Channel Stop mode bit */
+                    dmy_ctr = CTR_MATCH[tmp_obj->ch];
+                    *dmy_ctr &= 0xFFFFFFFB;
+                    can_set_channel_mode(tmp_obj->ch, CH_RESET);
+                }
+                can_set_channel_mode(tmp_obj->ch, CH_HOLD);
+            }
+            can_set_global_mode(GL_TEST);
+            /* enable communication test between channel1 and channel2 */
+            RSCAN0GTSTCFG = 0x06;
+            RSCAN0GTSTCTR = 0x01;
+            /* send and receive setting of channel1 and channel2 */
+            for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) {
+                can_reset_buffer(tmp_obj);
+                /* set global interrrupt */
+                /* THLEIE, MEIE and DEIE interrupts are disable */
+                RSCAN0GCTR &= 0xFFFFF8FF;
+                /* BLIE, OLIE, BORIE and BOEIE interrupts are disable */
+                /* TAIE, ALIE, EPIE, EWIE and BEIE interrupts are enable */
+                dmy_ctr = CTR_MATCH[tmp_obj->ch];
+                *dmy_ctr &= 0x00018700;
+                can_set_global_mode(GL_OPE);
+                can_set_channel_mode(tmp_obj->ch, CH_COMM);
+                /* Use send/receive FIFO buffer */
+                dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_SEND];
+                *dmy_cfcc |= 0x01;
+                dmy_cfcc = CFCC_TBL[tmp_obj->ch][CAN_RECV];
+                *dmy_cfcc |= 0x01;
+            }
+            break;
+        case MODE_TEST_SILENT:
+            /* not supported */
+            /* fall through */
+        default:
+            retval = 0;
+            break;
+    }
+    
+    return retval;
+}
+
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) {
+    int retval = 0;
+    
+    if ((format == CANStandard) || (format == CANExtended)) {
+        if (((format == CANStandard) && (id <= 0x07FF)) || ((format == CANExtended) && (id <= 0x03FFFF))) {
+            /* set Global Reset mode and Channel Reset mode */
+            can_set_global_mode(GL_RESET);
+            can_set_channel_mode(obj->ch, CH_RESET);
+            /* enable receive rule table writing */
+            RSCAN0GAFLECTR = 0x00000100;
+            /* set the page number of receive rule table(page number = 0) */
+            RSCAN0GAFLECTR |= (obj->ch * 4);
+            /* set IDE format */
+            *dmy_gaflid = (format << 31);
+            if (format == CANExtended) {
+                /* set receive rule ID for bit28-11 */
+                *dmy_gaflid |= (id << 11);
+            } else {
+                /* set receive rule ID for bit10-0 */
+                *dmy_gaflid |= id;
+            }
+            /* set ID mask bit */
+            *dmy_gaflm = (0xC0000000 | mask);
+            /* disable receive rule table writing */
+            RSCAN0GAFLECTR &= 0xFFFFFEFF;
+            /* reconfigure channel which is already initialized */
+            can_reconfigure_channel();
+            retval = 1;
+        }
+    }
+    
+    return retval;
+}
+
+void can_monitor(can_t *obj, int silent) {
+    __IO uint32_t *dmy_ctr;
+
+    /* set Channel Hold mode */
+    can_set_channel_mode(obj->ch, CH_HOLD);
+    if (silent) {
+        /* set listen only mode, enable communication test mode */
+        dmy_ctr = CTR_MATCH[obj->ch];
+        *dmy_ctr = ((*dmy_ctr & 0x00FFFFFF) | 0x03000000);
+        can_set_channel_mode(obj->ch, CH_COMM);
+    } else {
+        /* set normal test mode, disable communication test mode */
+        dmy_ctr = CTR_MATCH[obj->ch];
+        *dmy_ctr &= 0x00FFFFFF;
+        /* reset register */
+        can_reset_reg(obj);
+        /* reconfigure channel which is already initialized */
+        can_reconfigure_channel();
+    }
+}
+
+static void can_reset_reg(can_t *obj) {
+    __IO uint32_t *dmy_ctr;
+
+    /* time stamp source uses peripheral clock (pclk(P1_phi)/2), CAN clock uses clkc(P1_phi/2),           */
+    /* mirror off, DLC not transfer, DLC check permit, transmit buffer priority, clock source not divided */
+    RSCAN0GCFG = 0x00000003;
+    /* set default frequency at 100k */
+    can_set_frequency(obj, 100000);
+    /* set receive rule */
+    can_reset_recv_rule(obj);
+    /* set buffer */
+    can_reset_buffer(obj);
+    /* set global interrrupt */
+    /* THLEIE, MEIE and DEIE interrupts are disable */
+    RSCAN0GCTR &= 0xFFFFF8FF;
+    /* ALIE, BLIE, OLIE, BORIE, BOEIE, EPIE, EWIE and BEIE interrupts are disable */
+    dmy_ctr = CTR_MATCH[obj->ch];
+    *dmy_ctr &= 0xFFFF00FF;
+}
+
+static void can_reset_recv_rule(can_t *obj) {
+    /* number of receive rules of each chanel = 64 */
+    RSCAN0GAFLCFG0 = 0x40404040;
+    RSCAN0GAFLCFG1 = 0x40000000;
+    /* enable receive rule table writing */
+    RSCAN0GAFLECTR = 0x00000100;
+    /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */
+    RSCAN0GAFLECTR |= (obj->ch * 4);
+    /* set standard ID, data frame and receive rule ID */
+    *dmy_gaflid = 0x07FF;
+    /* IDE bit, RTR bit and ID bit(28-0) are not compared */
+    *dmy_gaflm = 0;
+    /* DLC check is 1 bytes, not use a receive buffer */
+    *dmy_gaflp0 = 0x10000000;
+    /* use a send/receive FIFO buffer(ex: if ch = 1, FIFO buffer number = 4 and bit = 12) */
+    *dmy_gaflp1 = (1 << ((obj->ch + 3) * 3));
+    /* disable receive rule table writing */
+    RSCAN0GAFLECTR &= 0xFFFFFEFF;
+}
+
+static void can_reset_buffer(can_t *obj) {
+    __IO uint32_t *dmy_rfcc;
+    __IO uint32_t *dmy_cfcc;
+    __IO uint32_t *dmy_txqcc;
+    __IO uint32_t *dmy_thlcc;
+    int cnt;
+    
+    /* set linked send buffer number(ex: if ch = 1 and mode = send, buffer number = 16), interval timer is pclk/2 */
+    /* number of rows of send/receive FIFO buffer = 4 */
+    dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
+    *dmy_cfcc = 0x00011100;                 /* send/receive FIFO mode is send */
+    dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
+    *dmy_cfcc = 0x00001100;                 /* send/receive FIFO mode is receive */
+    /* receive buffer is not used */
+    RSCAN0RMNB = 0;
+    /* receive FIFO buffer is not used */
+    for (cnt = 0; cnt < 8; cnt++) {
+        dmy_rfcc = RFCC_MATCH[cnt];
+        *dmy_rfcc = 0;
+    }
+    /* send queue is not used */
+    dmy_txqcc = TXQCC_MATCH[obj->ch];
+    *dmy_txqcc = 0;
+    /* send history is not used */
+    dmy_thlcc = THLCC_MATCH[obj->ch];
+    *dmy_thlcc = 0;
+
+    /* CFTXIE and CFRXIE interrupts are enable */
+    dmy_cfcc = CFCC_TBL[obj->ch][CAN_SEND];
+    *dmy_cfcc |= 0x04;
+    dmy_cfcc = CFCC_TBL[obj->ch][CAN_RECV];
+    *dmy_cfcc |= 0x02;
+    /* TMIEp interrupt is disable */
+    RSCAN0TMIEC0 = 0x00000000;
+    RSCAN0TMIEC1 = 0x00000000;
+    RSCAN0TMIEC2 = 0x00000000;
+}
+
+static void can_reconfigure_channel(void) {
+    __IO uint32_t *dmy_cfcc;
+    int ch_cnt;
+
+    for (ch_cnt = 0; ch_cnt < CAN_NUM; ch_cnt++) {
+        if (can_initialized[ch_cnt] == 1) {
+            /* set Global Operation mode and Channel Communication mode */
+            can_set_global_mode(GL_OPE);
+            can_set_channel_mode(ch_cnt, CH_COMM);
+            /* Use send/receive FIFO buffer */
+            dmy_cfcc = CFCC_TBL[ch_cnt][CAN_SEND];
+            *dmy_cfcc |= 0x01;
+            dmy_cfcc = CFCC_TBL[ch_cnt][CAN_RECV];
+            *dmy_cfcc |= 0x01;
+        }
+    }
+}
+
+static void can_set_frequency(can_t *obj, int f) {
+    __IO uint32_t *dmy_cfg;
+    int oldfreq = 0;
+    int newfreq = 0;
+    uint32_t  clkc_val;
+    uint8_t tmp_tq;
+    uint8_t tq = 0;
+    uint8_t tmp_brp;
+    uint8_t brp = 0;
+    uint8_t tseg1 = 0;
+    uint8_t tseg2 = 0;
+    
+    /* set clkc */
+    if (RZ_A1_IsClockMode0() == false) {
+        clkc_val = CM1_RENESAS_RZ_A1_P1_CLK / 2;
+    } else {
+        clkc_val = CM0_RENESAS_RZ_A1_P1_CLK / 2;
+    }
+    /* calculate BRP bit and Choose max value of calculated frequency */
+    for (tmp_tq = 8; tmp_tq <= 25; tmp_tq++) {
+        /* f = fCAN / ((BRP+1) * Tq) */
+        /* BRP = (fCAN / (f * Tq)) - 1 */
+        tmp_brp = ((clkc_val / (f * tmp_tq)) - 1) + 1;   // carry(decimal point is carry)
+        newfreq = clkc_val / ((tmp_brp + 1) * tmp_tq);
+        if (newfreq >= oldfreq) {
+            oldfreq  = newfreq;
+            tq       = tmp_tq;
+            brp      = tmp_brp;
+        }
+    }
+    /* calculate TSEG1 bit and TSEG2 bit */
+    tseg1 = (tq - 1) * 0.666666667;
+    tseg2 = (tq - 1) - tseg1;
+    /* set RSCAN0CmCFG register */
+    dmy_cfg = CFG_MATCH[obj->ch];
+    *dmy_cfg = ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
+}
+
+static void can_set_global_mode(int mode) {
+    /* set Global mode */
+    RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode);
+    /* Wait to cahnge into Global XXXX mode */
+    while ((RSCAN0GSTS & 0x07) != mode) {
+        __NOP();
+    }
+}
+
+static void can_set_channel_mode(uint32_t ch, int mode) {
+    __IO uint32_t *dmy_ctr;
+    __IO uint32_t *dmy_sts;
+
+    /* set Channel mode */
+    dmy_ctr = CTR_MATCH[ch];
+    *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | mode);
+    /* Wait to cahnge into Channel XXXX mode */
+    dmy_sts = STS_MATCH[ch];
+    while ((*dmy_sts & 0x07) != mode) {
+        __NOP();
+    }
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/device.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,49 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+/* ->Take measures about optimization problems of web compiler */
+   /* Web compiler has problem that inlining code may not be generated correctly */
+   /* when "-O3 -Otime" was specified. */
+#if defined(__CC_ARM) && (__ARMCC_VERSION <= 5040027)
+#pragma Ospace
+#endif
+/* <-Take measures about optimization problems of web compiler */
+
+
+
+
+
+
+
+
+
+
+
+#define DEVICE_ID_LENGTH       32
+#define DEVICE_MAC_OFFSET      20
+
+
+
+
+
+#include "objects.h"
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernet_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,696 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "ethernet_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+#include "ether_iodefine.h"
+#include "ethernetext_api.h"
+
+/* Descriptor info */
+#define NUM_OF_TX_DESCRIPTOR    (16)
+#define NUM_OF_RX_DESCRIPTOR    (16)
+#define SIZE_OF_BUFFER          (1600)     /* Must be an integral multiple of 32 */
+#define MAX_SEND_SIZE           (1514)
+/* Ethernet Descriptor Value Define */
+#define TD0_TFP_TOP_BOTTOM      (0x30000000)
+#define TD0_TACT                (0x80000000)
+#define TD0_TDLE                (0x40000000)
+#define RD0_RACT                (0x80000000)
+#define RD0_RDLE                (0x40000000)
+#define RD0_RFE                 (0x08000000)
+#define RD0_RCSE                (0x04000000)
+#define RD0_RFS                 (0x03FF0000)
+#define RD0_RCS                 (0x0000FFFF)
+#define RD0_RFS_RFOF            (0x02000000)
+#define RD0_RFS_RUAF            (0x00400000)
+#define RD0_RFS_RRF             (0x00100000)
+#define RD0_RFS_RTLF            (0x00080000)
+#define RD0_RFS_RTSF            (0x00040000)
+#define RD0_RFS_PRE             (0x00020000)
+#define RD0_RFS_CERF            (0x00010000)
+#define RD0_RFS_ERROR           (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
+                                 RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
+#define RD1_RDL_MSK             (0x0000FFFF)
+/* PHY Register */
+#define BASIC_MODE_CONTROL_REG  (0)
+#define BASIC_MODE_STATUS_REG   (1)
+#define PHY_IDENTIFIER1_REG     (2)
+#define PHY_IDENTIFIER2_REG     (3)
+#define PHY_SP_CTL_STS_REG      (31)
+/* MII management interface access */
+#define PHY_ADDR                (0)        /* Confirm the pin connection of the PHY-LSI */
+#define PHY_ST                  (1)
+#define PHY_WRITE               (1)
+#define PHY_READ                (2)
+#define MDC_WAIT                (6)        /* 400ns/4 */
+#define BASIC_STS_MSK_LINK      (0x0004)   /* Link Status */
+#define BASIC_STS_MSK_AUTO_CMP  (0x0020)   /* Auto-Negotiate Complete */
+#define M_PHY_ID                (0xFFFFFFF0)
+#define PHY_ID_LAN8710A         (0x0007C0F0)
+/* ETHERPIR0 */
+#define PIR0_MDI                (0x00000008)
+#define PIR0_MDO                (0x00000004)
+#define PIR0_MMD                (0x00000002)
+#define PIR0_MDC                (0x00000001)
+#define PIR0_MDC_HIGH           (0x00000001)
+#define PIR0_MDC_LOW            (0x00000000)
+/* ETHEREDRRR0 */
+#define EDRRR0_RR               (0x00000001)
+/* ETHEREDTRR0 */
+#define EDTRR0_TR               (0x00000003)
+/* software wait */
+#define LOOP_100us              (6700)     /* Loop counter for software wait  6666=100us/((1/400MHz)*6cyc) */
+
+#define EDMAC_EESIPR_INI_RECV   (0x0205001F)    /* 0x02000000 : Detect reception suspended */
+                                                /* 0x00040000 : Detect frame reception */
+                                                /* 0x00010000 : Receive FIFO overflow */
+                                                /* 0x00000010 : Residual bit frame reception */
+                                                /* 0x00000008 : Long frame reception */
+                                                /* 0x00000004 : Short frame reception */
+                                                /* 0x00000002 : PHY-LSI reception error */
+                                                /* 0x00000001 : Receive frame CRC error */
+#define EDMAC_EESIPR_INI_EtherC (0x00400000)    /* 0x00400000 : E-MAC status register */
+
+/* Send descriptor */
+typedef struct tag_edmac_send_desc {
+    uint32_t    td0;
+    uint32_t    td1;
+    uint8_t     *td2;
+    uint32_t    padding4;
+} edmac_send_desc_t;
+
+/* Receive descriptor */
+typedef struct tag_edmac_recv_desc {
+    uint32_t    rd0;
+    uint32_t    rd1;
+    uint8_t     *rd2;
+    uint32_t    padding4;
+} edmac_recv_desc_t;
+
+/* memory */
+/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
+/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
+#if defined(__ICCARM__)
+#pragma data_alignment=16
+static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
+                                 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
+                                 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
+                                 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]  //16 bytes aligned!
+                                 @ ".mirrorram";
+#else
+static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
+                                 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
+                                 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
+                                 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
+                                 __attribute((section("NC_BSS"),aligned(16)));  //16 bytes aligned!
+#endif
+static int32_t            rx_read_offset;   /* read offset */
+static int32_t            tx_wite_offset;   /* write offset */
+static uint32_t           send_top_index;
+static uint32_t           recv_top_index;
+static int32_t            Interrupt_priority;
+static edmac_send_desc_t  *p_eth_desc_dsend = NULL;
+static edmac_recv_desc_t  *p_eth_desc_drecv = NULL;
+static edmac_recv_desc_t  *p_recv_end_desc  = NULL;
+static ethernetext_cb_fnc *p_recv_cb_fnc    = NULL;
+static char               mac_addr[6]       = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
+static uint32_t           phy_id            = 0;
+static uint32_t           start_stop        = 1;  /* 0:stop  1:start */
+
+/* function */
+static void lan_reg_reset(void);
+static void lan_desc_create(void);
+static void lan_reg_set(int32_t link);
+static uint16_t phy_reg_read(uint16_t reg_addr);
+static void phy_reg_write(uint16_t reg_addr, uint16_t data);
+static void mii_preamble(void);
+static void mii_cmd(uint16_t reg_addr, uint32_t option);
+static void mii_reg_read(uint16_t *data);
+static void mii_reg_write(uint16_t data);
+static void mii_z(void);
+static void mii_write_1(void);
+static void mii_write_0(void);
+static void set_ether_pir(uint32_t set_data);
+static void wait_100us(int32_t wait_cnt);
+
+
+int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
+    int32_t  i;
+    uint16_t val;
+
+    CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74);  /* enable ETHER clock */
+
+    /* -->4F<-- P1_14(ET_COL) */
+    GPIOPMC1    |=  0x4000;
+    GPIOPFCAE1  &= ~0x4000;
+    GPIOPFCE1   |=  0x4000;
+    GPIOPFC1    |=  0x4000;
+    GPIOPIPC1   |=  0x4000;
+
+    /* -->2F<-- P2_0(ET_TXCLK), P2_1(ET_TXER), P2_2(ET_TXEN), P2_3(ET_CRS), P2_4(ET_TXD0),
+    P2_5(ET_TXD1), P2_6(ET_TXD2), P2_7(ET_TXD3), P2_8(ET_RXD0), P2_9(ET_RXD1), P2_10(ET_RXD2) P2_11(ET_RXD3) */
+    GPIOPMC2    |=  0x0FFF;
+    GPIOPFCAE2  &= ~0x0FFF;
+    GPIOPFCE2   &= ~0x0FFF;
+    GPIOPFC2    |=  0x0FFF;
+    GPIOPIPC2   |=  0x0FFF;
+
+    /* -->3F<-- P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
+    GPIOPMC3    |=  0x0078;
+    GPIOPFCAE3  &= ~0x0078;
+    GPIOPFCE3   &= ~0x0078;
+    GPIOPFC3    |=  0x0078;
+    GPIOPIPC3   |=  0x0078;
+
+    /* -->3F<-- P7_0(ET_MDC) */
+    GPIOPMC7    |=  0x0001;
+    GPIOPFCAE7  &= ~0x0001;
+    GPIOPFCE7   |=  0x0001;
+    GPIOPFC7    &= ~0x0001;
+    GPIOPIPC7   |=  0x0001;
+
+    /* Resets the E-MAC,E-DMAC */
+    lan_reg_reset();
+
+    /* Resets the PHY-LSI */
+    phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
+    for (i = 10000; i > 0; i--) {
+        val = phy_reg_read(BASIC_MODE_CONTROL_REG);
+        if (((uint32_t)val & 0x8000uL) == 0) {
+            break;                  /* Reset complete */
+        }
+    }
+
+    phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
+           |  (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
+
+    Interrupt_priority = p_ethcfg->int_priority;
+    p_recv_cb_fnc      = p_ethcfg->recv_cb;
+    start_stop         = 1;
+
+    if (p_ethcfg->ether_mac != NULL) {
+        (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
+    } else {
+        ethernet_address(mac_addr); /* Get MAC Address */
+    }
+
+    return 0;
+}
+
+void ethernetext_start_stop(int32_t mode) {
+    if (mode == 1) {
+        /* start */
+        ETHEREDTRR0 |= EDTRR0_TR;
+        ETHEREDRRR0 |= EDRRR0_RR;
+        start_stop   = 1;
+    } else {
+        /* stop */
+        ETHEREDTRR0 &= ~EDTRR0_TR;
+        ETHEREDRRR0 &= ~EDRRR0_RR;
+        start_stop   = 0;
+    }
+}
+
+int ethernetext_chk_link_mode(void) {
+    int32_t  link;
+    uint16_t data;
+
+    if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
+        data = phy_reg_read(PHY_SP_CTL_STS_REG);
+        switch (((uint32_t)data >> 2) & 0x00000007) {
+            case 0x0001:
+                link = HALF_10M;
+                break;
+            case 0x0005:
+                link = FULL_10M;
+                break;
+            case 0x0002:
+                link = HALF_TX;
+                break;
+            case 0x0006:
+                link = FULL_TX;
+                break;
+            default:
+                link = NEGO_FAIL;
+                break;
+        }
+    } else {
+        link = NEGO_FAIL;
+    }
+
+    return link;
+}
+
+void ethernetext_set_link_mode(int32_t link) {
+    lan_reg_reset();            /* Resets the E-MAC,E-DMAC */
+    lan_desc_create();          /* Initialize of buffer memory */
+    lan_reg_set(link);          /* E-DMAC, E-MAC initialization */
+}
+
+int ethernet_init() {
+    ethernet_cfg_t ethcfg;
+
+    ethcfg.int_priority = 5;
+    ethcfg.recv_cb      = NULL;
+    ethcfg.ether_mac    = NULL;
+    ethernetext_init(&ethcfg);
+    ethernet_set_link(-1, 0);   /* Auto-Negotiation */
+
+    return 0;
+}
+
+void ethernet_free() {
+    ETHERARSTR |= 0x00000001;            /* ETHER software reset */
+    CPGSTBCR7  |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
+}
+
+int ethernet_write(const char *data, int slen) {
+    edmac_send_desc_t *p_send_desc;
+    int32_t           copy_size;
+
+    if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
+     || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
+        copy_size = 0;
+    } else {
+        p_send_desc = &p_eth_desc_dsend[send_top_index];   /* Current descriptor */
+        if ((p_send_desc->td0 & TD0_TACT) != 0) {
+            copy_size = 0;
+        } else {
+            copy_size = MAX_SEND_SIZE - tx_wite_offset;
+            if (copy_size > slen) {
+                copy_size = slen;
+            }
+            (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
+            tx_wite_offset += copy_size;
+        }
+    }
+
+    return copy_size;
+}
+
+int ethernet_send() {
+    edmac_send_desc_t *p_send_desc;
+    int32_t           ret;
+
+    if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
+        ret = 0;
+    } else {
+        /* Transfer 1 frame */
+        p_send_desc = &p_eth_desc_dsend[send_top_index];   /* Current descriptor */
+
+        /* Sets the frame length */
+        p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
+        tx_wite_offset   = 0;
+
+        /* Sets the transmit descriptor to transmit again */
+        p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
+        p_send_desc->td0 |= TD0_TACT;
+        if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
+            ETHEREDTRR0 |= EDTRR0_TR;
+        }
+
+        /* Update the current descriptor */
+        send_top_index++;
+        if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
+            send_top_index = 0;
+        }
+        ret = 1;
+    }
+
+    return ret;
+}
+
+int ethernet_receive() {
+    edmac_recv_desc_t *p_recv_desc;
+    int32_t           receive_size = 0;
+
+    if (p_eth_desc_drecv != NULL) {
+        if (p_recv_end_desc != NULL) {
+            /* Sets the receive descriptor to receive again */
+            p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
+            p_recv_end_desc->rd0 |= RD0_RACT;
+            if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
+                ETHEREDRRR0 |= EDRRR0_RR;
+            }
+            p_recv_end_desc = NULL;
+        }
+
+        p_recv_desc = &p_eth_desc_drecv[recv_top_index];   /* Current descriptor */
+        if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
+            /* Receives 1 frame */
+            if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
+                /* Receive frame error */
+                /* Sets the receive descriptor to receive again */
+                p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
+                p_recv_desc->rd0 |= RD0_RACT;
+                if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
+                    ETHEREDRRR0 |= EDRRR0_RR;
+                }
+            } else {
+                /* Copies the received frame */
+                rx_read_offset  = 0;
+                p_recv_end_desc = p_recv_desc;
+                receive_size    = (p_recv_desc->rd1 & RD1_RDL_MSK);    /* number of bytes received */
+            }
+
+            /* Update the current descriptor */
+            recv_top_index++;
+            if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
+                recv_top_index = 0;
+            }
+        }
+    }
+
+    return receive_size;
+}
+
+int ethernet_read(char *data, int dlen) {
+    edmac_recv_desc_t *p_recv_desc = p_recv_end_desc;                   /* Read top descriptor */
+    int32_t           copy_size;
+
+    if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
+        copy_size = 0;
+    } else {
+        copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
+        if (copy_size > dlen) {
+            copy_size = dlen;
+        }
+        (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
+        rx_read_offset += copy_size;
+    }
+
+    return copy_size;
+}
+
+void ethernet_address(char *mac) {
+    if (mac != NULL) {
+        mbed_mac_address(mac); /* Get MAC Address */
+    }
+}
+
+int ethernet_link(void) {
+    int32_t  ret;
+    uint16_t data;
+
+    data = phy_reg_read(BASIC_MODE_STATUS_REG);
+    if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
+        ret = 1;
+    } else {
+        ret = 0;
+    }
+
+    return ret;
+}
+
+void ethernet_set_link(int speed, int duplex) {
+    uint16_t data;
+    int32_t  i;
+    int32_t  link;
+
+    if ((speed < 0) || (speed > 1)) {
+        data = 0x1000;      /* Auto-Negotiation Enable */
+        phy_reg_write(BASIC_MODE_CONTROL_REG, data);
+        for (i = 0; i < 1000; i++) {
+            data = phy_reg_read(BASIC_MODE_STATUS_REG);
+            if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
+                break;
+            }
+            wait_100us(10);
+        }
+    } else {
+        data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
+        phy_reg_write(BASIC_MODE_CONTROL_REG, data);
+        wait_100us(1);
+    }
+
+    link = ethernetext_chk_link_mode();
+    ethernetext_set_link_mode(link);
+}
+
+void INT_Ether(void) {
+    uint32_t stat_edmac;
+    uint32_t stat_etherc;
+
+    /* Clear the interrupt request flag */
+    stat_edmac = (ETHEREESR0 & ETHEREESIPR0);       /* Targets are restricted to allowed interrupts */
+    ETHEREESR0 = stat_edmac;
+    /* Reception-related */
+    if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
+        if (p_recv_cb_fnc != NULL) {
+            p_recv_cb_fnc();
+        }
+    }
+    /* E-MAC-related */
+    if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
+        /* Clear the interrupt request flag */
+        stat_etherc = (ETHERECSR0 & ETHERECSIPR0);  /* Targets are restricted to allowed interrupts */
+        ETHERECSR0  = stat_etherc;
+    }
+}
+
+static void lan_reg_reset(void) {
+    volatile int32_t j = 400;    /* Wait for B dia 256 cycles  ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
+
+    ETHERARSTR      |= 0x00000001;      /* ETHER software reset */
+    while (j--) {
+        /* Do Nothing */
+    }
+
+    ETHEREDSR0      |= 0x00000003;      /* E-DMAC software reset */
+    ETHEREDMR0      |= 0x00000003;      /* Set SWRR and SWRT simultaneously */
+
+    /* Check clear software reset */
+    while ((ETHEREDMR0 & 0x00000003) != 0) {
+        /* Do Nothing */
+    }
+}
+
+static void lan_desc_create(void) {
+    int32_t i;
+    uint8_t *p_memory_top;
+
+    (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory));
+    p_memory_top = ethernet_nc_memory;
+
+    /* Descriptor area configuration */
+    p_eth_desc_dsend  = (edmac_send_desc_t *)p_memory_top;
+    p_memory_top     += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
+    p_eth_desc_drecv  = (edmac_recv_desc_t *)p_memory_top;
+    p_memory_top     += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
+
+    /* Transmit descriptor */
+    for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
+        p_eth_desc_dsend[i].td2  = p_memory_top;                     /* TD2 TBA */
+        p_memory_top            += SIZE_OF_BUFFER;
+        p_eth_desc_dsend[i].td1  = 0;                                /* TD1 TDL */
+        p_eth_desc_dsend[i].td0  = TD0_TFP_TOP_BOTTOM;               /* TD0:1frame/1buf1buf, transmission disabled */
+    }
+    p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE;                         /* Set the last descriptor */
+
+    /* Receive descriptor */
+    for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
+        p_eth_desc_drecv[i].rd2  = p_memory_top;                     /* RD2 RBA */
+        p_memory_top            += SIZE_OF_BUFFER;
+        p_eth_desc_drecv[i].rd1  = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
+        p_eth_desc_drecv[i].rd0  = RD0_RACT;                         /* RD0:reception enabled */
+    }
+    p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE;                         /* Set the last descriptor */
+
+    /* Initialize descriptor management information */
+    send_top_index  = 0;
+    recv_top_index  = 0;
+    rx_read_offset  = 0;
+    tx_wite_offset  = 0;
+    p_recv_end_desc = NULL;
+}
+
+static void lan_reg_set(int32_t link) {
+    /* MAC address setting */
+    ETHERMAHR0      = ((uint32_t)mac_addr[0] << 24)
+                    | ((uint32_t)mac_addr[1] << 16)
+                    | ((uint32_t)mac_addr[2] << 8)
+                    |  (uint32_t)mac_addr[3];
+    ETHERMALR0      = ((uint32_t)mac_addr[4] << 8)
+                    |  (uint32_t)mac_addr[5];
+
+    /* E-DMAC */
+    ETHERTDLAR0     = (uint32_t)&p_eth_desc_dsend[0];
+    ETHERRDLAR0     = (uint32_t)&p_eth_desc_drecv[0];
+    ETHERTDFAR0     = (uint32_t)&p_eth_desc_dsend[0];
+    ETHERRDFAR0     = (uint32_t)&p_eth_desc_drecv[0];
+    ETHERTDFXR0     = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
+    ETHERRDFXR0     = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
+    ETHERTDFFR0    |=  0x00000001;      /* TDLF  Transmit Descriptor Queue Last Flag : Last descriptor (1) */
+    ETHERRDFFR0    |=  0x00000001;      /* RDLF  Receive Descriptor Queue Last Flag : Last descriptor (1) */
+    ETHEREDMR0     |=  0x00000040;      /* Little endian */
+    ETHERTRSCER0   &= ~0x0003009F;      /* All clear */
+    ETHERTFTR0     &= ~0x000007FF;      /* TFT[10:0]  Transmit FIFO Threshold : Store and forward modes (H'000) */
+    ETHERFDR0      |=  0x00000707;      /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
+    ETHERRMCR0     |=  0x00000001;      /* RNC  Receive Enable Control : Continuous reception enabled (1) */
+    ETHERFCFTR0    &= ~0x001F00FF;
+    ETHERFCFTR0    |=  0x00070007;
+    ETHERRPADIR0   &= ~0x001FFFFF;      /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
+
+    /* E-MAC */
+    ETHERECMR0     &= ~0x04BF2063;      /* All clear */
+    ETHERRFLR0     &= ~0x0003FFFF;      /* RFL[17:0]  Receive Frame Length : 1518 bytes (H'00000) */
+    ETHERAPR0      &= ~0x0000FFFF;      /* AP[15:0]   Automatic PAUSE : Flow control is disabled (H'0000) */
+    ETHERMPR0      &= ~0x0000FFFF;      /* MP[15:0]   Manual PAUSE : Flow control is disabled (H'0000) */
+    ETHERTPAUSER0  &= ~0x0000FFFF;      /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
+    ETHERCSMR      &= ~0xC000003F;      /* The result of checksum is not written back to the receive descriptor */
+    if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
+        ETHERECMR0 |= 0x00000002;       /* Set to full-duplex mode */
+    } else {
+        ETHERECMR0 &= ~0x00000002;      /* Set to half-duplex mode */
+    }
+
+    /* Interrupt-related */
+    if (p_recv_cb_fnc != NULL) {
+        ETHEREESR0     |=  0xFF7F009F;                     /* Clear all status (by writing 1) */
+        ETHEREESIPR0   |=  0x00040000;                     /* FR  Frame Reception (1) */
+        ETHERECSR0     |=  0x00000011;                     /* Clear all status (clear by writing 1) */
+        ETHERECSIPR0   &= ~0x00000011;                     /* PFROIP Disable, ICDIP Disable */
+        InterruptHandlerRegister(ETHERI_IRQn, INT_Ether);  /* Ethernet interrupt handler registration */
+        GIC_SetPriority(ETHERI_IRQn, Interrupt_priority);  /* Ethernet interrupt priority */
+        GIC_EnableIRQ(ETHERI_IRQn);                        /* Enables the E-DMAC interrupt */
+    }
+
+    ETHERECMR0     |=  0x00000060;      /* RE Enable, TE Enable */
+
+    /* Enable transmission/reception */
+    if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
+        ETHEREDRRR0 |= 0x00000001;       /* RR */
+    }
+}
+
+static uint16_t phy_reg_read(uint16_t reg_addr) {
+    uint16_t data;
+
+    mii_preamble();
+    mii_cmd(reg_addr, PHY_READ);
+    mii_z();
+    mii_reg_read(&data);
+    mii_z();
+
+    return data;
+}
+
+static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
+    mii_preamble();
+    mii_cmd(reg_addr, PHY_WRITE);
+    mii_write_1();
+    mii_write_0();
+    mii_reg_write(data);
+    mii_z();
+}
+
+static void mii_preamble(void) {
+    int32_t i = 32;
+
+    for (i = 32; i > 0; i--) {
+        /* 1 is output via the MII (Media Independent Interface) block. */
+        mii_write_1();
+    }
+}
+
+static void mii_cmd(uint16_t reg_addr, uint32_t option) {
+    int32_t  i;
+    uint16_t data = 0;
+
+    data |= (PHY_ST << 14);             /* ST code      */
+    data |= (option << 12);             /* OP code      */
+    data |= (PHY_ADDR << 7);            /* PHY Address  */
+    data |= (uint16_t)(reg_addr << 2);  /* Reg Address  */
+    for (i = 14; i > 0; i--) {
+        if ((data & 0x8000) == 0) {
+            mii_write_0();
+        } else {
+            mii_write_1();
+        }
+        data <<= 1;
+    }
+}
+
+static void mii_reg_read(uint16_t *data) {
+    int32_t  i;
+    uint16_t reg_data = 0;
+
+    /* Data are read in one bit at a time */
+    for (i = 16; i > 0; i--) {
+        set_ether_pir(PIR0_MDC_LOW);
+        set_ether_pir(PIR0_MDC_HIGH);
+        reg_data <<= 1;
+        reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3);  /* MDI read */
+        set_ether_pir(PIR0_MDC_HIGH);
+        set_ether_pir(PIR0_MDC_LOW);
+    }
+    *data = reg_data;
+}
+
+static void mii_reg_write(uint16_t data) {
+    int32_t i;
+
+    /* Data are written one bit at a time */
+    for (i = 16; i > 0; i--) {
+        if ((data & 0x8000) == 0) {
+            mii_write_0();
+        } else {
+            mii_write_1();
+        }
+        data <<= 1;
+    }
+}
+
+static void mii_z(void) {
+    set_ether_pir(PIR0_MDC_LOW);
+    set_ether_pir(PIR0_MDC_HIGH);
+    set_ether_pir(PIR0_MDC_HIGH);
+    set_ether_pir(PIR0_MDC_LOW);
+}
+
+static void mii_write_1(void) {
+    set_ether_pir(PIR0_MDO | PIR0_MMD);
+    set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
+    set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
+    set_ether_pir(PIR0_MDO | PIR0_MMD);
+}
+
+static void mii_write_0(void) {
+    set_ether_pir(PIR0_MMD);
+    set_ether_pir(PIR0_MMD | PIR0_MDC);
+    set_ether_pir(PIR0_MMD | PIR0_MDC);
+    set_ether_pir(PIR0_MMD);
+}
+
+static void set_ether_pir(uint32_t set_data) {
+    int32_t i;
+
+    for (i = MDC_WAIT; i > 0; i--) {
+        ETHERPIR0 = set_data;
+    }
+}
+
+static void wait_100us(int32_t wait_cnt) {
+    volatile int32_t j = LOOP_100us * wait_cnt;
+
+    while (--j) {
+        /* Do Nothing */
+    }
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/ethernetext_api.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,21 @@
+
+/* PHY link mode */
+#define NEGO_FAIL               (0)
+#define HALF_10M                (1)
+#define FULL_10M                (2)
+#define HALF_TX                 (3)
+#define FULL_TX                 (4)
+
+typedef void (ethernetext_cb_fnc)(void);
+
+typedef struct tag_ethernet_cfg {
+    int                  int_priority;
+    ethernetext_cb_fnc   *recv_cb;
+    char                 *ether_mac;
+} ethernet_cfg_t;
+
+extern int ethernetext_init(ethernet_cfg_t *p_ethcfg);
+extern void ethernetext_start_stop(int32_t mode);
+extern int ethernetext_chk_link_mode(void);
+extern void ethernetext_set_link_mode(int32_t link);
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_addrdefine.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,23 @@
+#ifndef __GPIO_ADDRDEFINE__
+#define __GPIO_ADDRDEFINE__
+
+#define GPIO_BASE  ((long)0xFCFE3000uL) /* GPIO */
+
+#define PORT(n)    (volatile unsigned short *)(GPIO_BASE + 0x000 + ((n)*4))
+#define PSR(n)     (volatile unsigned  long *)(GPIO_BASE + 0x100 + ((n)*4))
+#define PPR(n)     (volatile unsigned short *)(GPIO_BASE + 0x200 + ((n)*4))
+#define PM(n)      (volatile unsigned short *)(GPIO_BASE + 0x300 + ((n)*4))
+#define PMC(n)     (volatile unsigned short *)(GPIO_BASE + 0x400 + ((n)*4))
+#define PFC(n)     (volatile unsigned short *)(GPIO_BASE + 0x500 + ((n)*4))
+#define PFCE(n)    (volatile unsigned short *)(GPIO_BASE + 0x600 + ((n)*4))
+#define PNOT(n)    (volatile unsigned short *)(GPIO_BASE + 0x700 + ((n)*4))
+#define PMSR(n)    (volatile unsigned  long *)(GPIO_BASE + 0x800 + ((n)*4))
+#define PMCSR(n)   (volatile unsigned  long *)(GPIO_BASE + 0x900 + ((n)*4))
+#define PFCAE(n)   (volatile unsigned short *)(GPIO_BASE + 0xa00 + ((n)*4))
+#define PIBC(n)    (volatile unsigned short *)(GPIO_BASE + 0x4000 +((n)*4))
+#define PBDC(n)    (volatile unsigned short *)(GPIO_BASE + 0x4100 +((n)*4))
+#define PIPC(n)    (volatile unsigned short *)(GPIO_BASE + 0x4200 +((n)*4))
+
+#endif/*__GPIO_ADDRDEFINE__*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "gpio_addrdefine.h"
+
+
+uint32_t gpio_set(PinName pin) {
+    pin_function(pin, 0);
+    return (1 << PINNO(pin));
+}
+
+void gpio_init(gpio_t *obj, PinName pin) {
+    int group ;
+    obj->pin = pin;
+    if(pin == NC) return;
+    
+    obj->mask = gpio_set(pin);
+
+    group = PINGROUP(pin);
+    if (group > 9) return;
+
+    obj->reg_set = (volatile uint32_t *) PSR(group);
+    obj->reg_in  = (volatile uint32_t *) PPR(group);
+    obj->reg_dir = (volatile uint32_t *)PMSR(group);
+    obj->reg_buf = (volatile uint32_t *)PIBC(group);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+/* Pull up and Pull down settings aren't supported because RZ/A1H doesn't have pull up/down for pins(signals). */
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+    switch (direction) {
+        case PIN_INPUT :
+            *obj->reg_dir = (obj->mask << 16) | obj->mask;
+            *obj->reg_buf |=  obj->mask;
+            break;
+        case PIN_OUTPUT:
+            *obj->reg_dir = (obj->mask << 16) | 0;
+            *obj->reg_buf &= ~obj->mask;
+            break;
+    }
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_irq_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,224 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+
+#include "gpio_irq_api.h"
+#include "intc_iodefine.h"
+#include "pinmap.h"
+#include "cmsis.h"
+#include "gpio_addrdefine.h"
+
+#define CHANNEL_NUM     8
+
+static void gpio_irq0(void);
+static void gpio_irq1(void);
+static void gpio_irq2(void);
+static void gpio_irq3(void);
+static void gpio_irq4(void);
+static void gpio_irq5(void);
+static void gpio_irq6(void);
+static void gpio_irq7(void);
+
+static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL};
+static gpio_irq_handler irq_handler;
+static const int nIRQn_h = 32;
+extern PinName gpio_multi_guard;
+
+enum {
+    IRQ0,IRQ1, 
+    IRQ2,IRQ3, 
+    IRQ4,IRQ5, 
+    IRQ6,IRQ7, 
+
+} IRQNo;
+
+static const IRQHandler irq_tbl[CHANNEL_NUM] = {
+    &gpio_irq0,
+    &gpio_irq1,
+    &gpio_irq2,
+    &gpio_irq3,
+    &gpio_irq4,
+    &gpio_irq5,
+    &gpio_irq6,
+    &gpio_irq7,
+};
+
+#ifdef MAX_PERI
+static const PinMap PinMap_IRQ[] = {
+    {P1_0,  IRQ0, 4}, {P4_8,  IRQ0, 8}, {P6_8,  IRQ0, 8}, {P7_9,  IRQ0, 8}, {P8_2,  IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8,  IRQ0, 2}, {P9_1,  IRQ0, 4},
+    {P1_1,  IRQ1, 4}, {P4_9,  IRQ1, 8}, {P6_9,  IRQ1, 8}, {P7_8,  IRQ1, 8}, {P8_3,  IRQ1, 6}, {P2_15, IRQ1, 8},
+    {P1_2,  IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8,  IRQ2, 3}, {P3_0,  IRQ2, 3}, {P5_9,  IRQ2, 4}, {P6_3,  IRQ2, 4},
+    {P1_3,  IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9,  IRQ3, 3}, {P6_4,  IRQ3, 4},
+    {P1_4,  IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3,  IRQ4, 3}, {P6_1,  IRQ4, 4},
+    {P1_5,  IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0,  IRQ5, 6}, {P6_0,  IRQ5, 6}, {P8_7,  IRQ5, 4},
+    {P1_6,  IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1,  IRQ6, 3}, {P3_9,  IRQ6, 8}, {P5_6,  IRQ6, 6},
+    {P1_7,  IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2,  IRQ7, 4}, {P2_13, IRQ7, 8},
+    {NC,    NC,     0}
+};
+#else
+static const PinMap PinMap_IRQ[] = {
+    {P9_1,  IRQ0, 4},
+	{P7_8,  IRQ1, 8},
+    {P1_2,  IRQ2, 4}, {P1_8,  IRQ2, 3}, {P3_0,  IRQ2, 3}, {P5_9,  IRQ2, 4},
+    {P1_3,  IRQ3, 4}, {P1_9,  IRQ3, 3},
+    {P1_4,  IRQ4, 4}, {P1_10, IRQ4, 3},
+    {P1_5,  IRQ5, 4}, {P1_11, IRQ5, 3},
+    {P3_1,  IRQ6, 3}, {P3_9,  IRQ6, 8}, {P5_6,  IRQ6, 6},
+    {NC,    NC,     0}
+};
+#endif
+
+static void handle_interrupt_in(int irq_num) {
+    uint16_t irqs;
+    uint16_t edge_req;
+    gpio_irq_t *obj;
+    gpio_irq_event irq_event;
+
+    irqs = INTCIRQRR;
+    if (irqs & (1 << irq_num)) {
+        obj = channel_obj[irq_num];
+        if (obj != NULL) {
+            edge_req = ((INTCICR1 >> (obj->ch * 2)) & 3);
+            if (edge_req == 1) {
+                irq_event = IRQ_FALL;
+            } else if (edge_req == 2) {
+                irq_event = IRQ_RISE;
+            } else {
+                uint32_t      mask    = (1 << (obj->pin & 0x0F));
+                __I  uint32_t *reg_in = (volatile uint32_t *) PPR((int)PINGROUP(obj->pin));
+
+                if ((*reg_in & mask) == 0) {
+                    irq_event = IRQ_FALL;
+                } else {
+                    irq_event = IRQ_RISE;
+                }
+	        }
+            irq_handler(obj->port, irq_event);
+        }
+        INTCIRQRR &= ~(1 << irq_num);
+    }
+}
+
+static void gpio_irq0(void) {
+    handle_interrupt_in(0);
+}
+
+static void gpio_irq1(void) {
+    handle_interrupt_in(1);
+}
+
+static void gpio_irq2(void) {
+    handle_interrupt_in(2);
+}
+
+static void gpio_irq3(void) {
+    handle_interrupt_in(3);
+}
+
+static void gpio_irq4(void) {
+    handle_interrupt_in(4);
+}
+
+static void gpio_irq5(void) {
+    handle_interrupt_in(5);
+}
+
+static void gpio_irq6(void) {
+    handle_interrupt_in(6);
+}
+
+static void gpio_irq7(void) {
+    handle_interrupt_in(7);
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+    int shift;
+    if (pin == NC) return -1;
+
+    obj->ch = pinmap_peripheral(pin, PinMap_IRQ);
+    obj->pin = (int)pin ;
+    obj->port = (int)id ;
+
+    shift = obj->ch*2;
+    channel_obj[obj->ch] = obj;
+    irq_handler = handler;
+    
+    pinmap_pinout(pin, PinMap_IRQ);
+    gpio_multi_guard = pin;           /* Set multi guard */
+
+    // INTC settings
+    InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]);
+    INTCICR1 &= ~(0x3 << shift);
+    INTCICR1 |= (0x3 << shift);
+    GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
+    GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
+    obj->int_enable = 1;
+    __enable_irq();
+
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+    channel_obj[obj->ch] = NULL;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+    int shift = obj->ch*2;
+    uint16_t val = event == IRQ_RISE ? 2 : 
+                   event == IRQ_FALL ? 1 : 0;
+    uint16_t work_icr_val;
+
+    /* check edge interrupt setting */
+    work_icr_val = INTCICR1;
+    if (enable == 1) {
+        /* Set interrupt serect */
+        work_icr_val |=  (val << shift);
+    } else {
+        /* Clear interrupt serect */
+        work_icr_val &= ~(val << shift);
+    }
+
+    if ((work_icr_val & (3 << shift)) == 0) {
+        /* No edge interrupt setting */
+        GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
+        /* Clear Interrupt flags */
+        INTCIRQRR &= ~(1 << obj->ch);
+        INTCICR1  = work_icr_val;
+    } else if (obj->int_enable == 1) {
+        INTCICR1  = work_icr_val;
+        GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
+    } else {
+        INTCICR1  = work_icr_val;
+    }
+}
+
+void gpio_irq_enable(gpio_irq_t *obj) {
+    int shift = obj->ch*2;
+    uint16_t work_icr_val = INTCICR1;
+
+    /* check edge interrupt setting */
+    if ((work_icr_val & (3 << shift)) != 0) {
+        GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
+    }
+    obj->int_enable = 1;
+}
+
+void gpio_irq_disable(gpio_irq_t *obj) {
+    GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
+    obj->int_enable = 0;
+}
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/gpio_object.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_set;
+    __I  uint32_t *reg_in;
+    __IO uint32_t *reg_buf;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+    *obj->reg_set = (obj->mask << 16) | ((value != 0) ? obj->mask : 0);
+}
+
+static inline int gpio_read(gpio_t *obj) {
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/i2c_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,754 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "r_typedefs.h"
+
+#include "riic_iodefine.h"
+#include "RZ_A1_Init.h"
+#include "VKRZA1H.h"
+
+volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
+
+#define REG(N) \
+    RIIC[obj->i2c]->RIICn##N
+
+/* RIICnCR1 */
+#define CR1_RST   (1 << 6)
+#define CR1_ICE   (1 << 7)
+
+/* RIICnCR2 */
+#define CR2_ST    (1 << 1)
+#define CR2_RS    (1 << 2)
+#define CR2_SP    (1 << 3)
+#define CR2_TRS   (1 << 5)
+#define CR2_BBSY  (1 << 7)
+
+/* RIICnMR3 */
+#define MR3_ACKBT (1 << 3)
+#define MR3_ACKWP (1 << 4)
+#define MR3_WAIT  (1 << 6)
+
+/* RIICnSER */
+#define SER_SAR0E (1 << 0)
+
+/* RIICnSR1 */
+#define SR1_AAS0  (1 << 0)
+
+/* RIICnSR2 */
+#define SR2_START (1 << 2)
+#define SR2_STOP  (1 << 3)
+#define SR2_NACKF (1 << 4)
+#define SR2_RDRF  (1 << 5)
+#define SR2_TEND  (1 << 6)
+#define SR2_TDRE  (1 << 7)
+
+#define WAIT_TIMEOUT    (3600000)  /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */
+
+static const PinMap PinMap_I2C_SDA[] = {
+    {P1_1 , I2C_0, 1},
+    {P1_3 , I2C_1, 1},
+    {P1_5 , I2C_2, 1},
+    {P1_7 , I2C_3, 1},
+    {NC   , NC   , 0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+    {P1_0 , I2C_0, 1},
+    {P1_2 , I2C_1, 1},
+    {P1_4 , I2C_2, 1},
+    {P1_6 , I2C_3, 1},
+    {NC   , NC,    0}
+};
+
+
+static inline int i2c_status(i2c_t *obj) {
+    return REG(SR2.UINT8[0]);
+}
+
+static void i2c_reg_reset(i2c_t *obj) {
+    /* full reset */
+    REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
+    REG(CR1.UINT8[0]) |=  CR1_RST; // CR1.IICRST on
+    REG(CR1.UINT8[0]) |=  CR1_ICE; // CR1.ICE on
+
+    REG(MR1.UINT8[0])  =  0x08;    // P_phi /x  9bit (including Ack)
+    REG(SER.UINT8[0])  =  0x00;    // no slave addr enabled
+
+    /* set frequency */
+    REG(MR1.UINT8[0]) |=  obj->pclk_bit;
+    REG(BRL.UINT8[0])  =  obj->width_low;
+    REG(BRH.UINT8[0])  =  obj->width_hi;
+
+    REG(MR2.UINT8[0])  =  0x07;
+    REG(MR3.UINT8[0])  =  0x00;
+
+    REG(FER.UINT8[0])  =  0x72;    // SCLE, NFE enabled, TMOT
+    REG(IER.UINT8[0])  =  0x00;    // no interrupt
+
+    REG(CR1.UINT32) &= ~CR1_RST;   // CR1.IICRST negate reset
+}
+
+static inline int i2c_wait_RDRF(i2c_t *obj) {
+    int timeout = 0;
+    
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_RDRF) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+static int i2c_wait_TDRE(i2c_t *obj) {
+    int timeout = 0;
+
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_TDRE) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+static int i2c_wait_TEND(i2c_t *obj) {
+    int timeout = 0;
+    
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_TEND) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+
+static int i2c_wait_START(i2c_t *obj) {
+    int timeout = 0;
+    
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_START) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+static int i2c_wait_STOP(i2c_t *obj) {
+    int timeout = 0;
+    
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_STOP) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+static int i2c_set_STOP(i2c_t *obj) {
+    /* SR2.STOP = 0 */
+    REG(SR2.UINT32) &= ~SR2_STOP;
+    /* Stop condition */
+    REG(CR2.UINT32) |= CR2_SP;
+
+    return 0;
+}
+
+static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
+    /* SR2.NACKF = 0 */
+    REG(SR2.UINT32) &= ~SR2_NACKF;
+    /* SR2.STOP = 0 */
+    REG(SR2.UINT32) &= ~SR2_STOP;
+}
+
+static void i2c_set_MR3_NACK(i2c_t *obj) {
+    /* send a NOT ACK */
+    REG(MR3.UINT32) |=  MR3_ACKWP;
+    REG(MR3.UINT32) |=  MR3_ACKBT;
+    REG(MR3.UINT32) &= ~MR3_ACKWP;
+}
+
+static void i2c_set_MR3_ACK(i2c_t *obj) {
+    /* send a ACK */
+    REG(MR3.UINT32) |=  MR3_ACKWP;
+    REG(MR3.UINT32) &= ~MR3_ACKBT;
+    REG(MR3.UINT32) &= ~MR3_ACKWP;
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+    volatile uint8_t dummy;
+    switch ((int)obj->i2c) {
+        case I2C_0:
+            CPGSTBCR9 &= ~(0x80);
+            break;
+        case I2C_1:
+            CPGSTBCR9 &= ~(0x40);
+            break;
+        case I2C_2:
+            CPGSTBCR9 &= ~(0x20);
+            break;
+        case I2C_3:
+            CPGSTBCR9 &= ~(0x10);
+            break;
+    }
+    dummy = CPGSTBCR9;
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+    /* determine the I2C to use */
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    obj->i2c = pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT((int)obj->i2c != NC);
+
+    /* enable power */
+    i2c_power_enable(obj);
+
+    /* set default frequency at 100k */
+    i2c_frequency(obj, 100000);
+
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+    
+    obj->last_stop_flag = 1;
+}
+
+inline int i2c_start(i2c_t *obj) {
+    int timeout = 0;
+
+    while ((REG(CR2.UINT32) & CR2_BBSY) != 0) {
+        timeout ++;
+        if (timeout >= obj->bbsy_wait_cnt) {
+            break;
+        }
+    }
+    /* Start Condition */
+    REG(CR2.UINT8[0]) |= CR2_ST;
+
+    return 0;
+}
+
+static inline int i2c_restart(i2c_t *obj) {
+    /* SR2.START = 0 */
+    REG(SR2.UINT32) &= ~SR2_START;
+    /* ReStart condition */
+    REG(CR2.UINT32) |= CR2_RS;
+
+    return 0;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+    (void)i2c_set_STOP(obj);
+    (void)i2c_wait_STOP(obj);
+    i2c_set_SR2_NACKF_STOP(obj);
+    
+    return 0;
+}
+
+static void i2c_set_err_noslave(i2c_t *obj) {
+    (void)i2c_set_STOP(obj);
+    (void)i2c_wait_STOP(obj);
+    i2c_set_SR2_NACKF_STOP(obj);
+    obj->last_stop_flag = 1;
+}
+
+static inline int i2c_do_write(i2c_t *obj, int value) {
+    int timeout = 0;
+
+    /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+    while ((i2c_status(obj) & SR2_TDRE) == 0) {
+        timeout ++;
+        if (timeout >= WAIT_TIMEOUT) {
+            return -1;
+        }
+    }
+    /* write the data */
+    REG(DRT.UINT32) = value;
+
+    return 0;
+}
+
+static inline int i2c_read_address_write(i2c_t *obj, int value) {
+    int status;
+    
+    status = i2c_wait_TDRE(obj);
+    if (status == 0) {
+        /* write the data */
+        REG(DRT.UINT32) = value;
+    }
+    
+    return status;
+
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+    if (last == 2) {
+        /* this time is befor last byte read */
+        /* Set MR3 WAIT bit is 1 */;
+        REG(MR3.UINT32) |= MR3_WAIT;
+    } else if (last == 1) {
+        i2c_set_MR3_NACK(obj);
+    } else {
+        i2c_set_MR3_ACK(obj);
+    }
+
+    /* return the data */
+    return (REG(DRR.UINT32) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+    float64_t pclk_val;
+    float64_t wait_utime;
+    volatile float64_t bps;
+    volatile float64_t L_time;         /* H Width period */
+    volatile float64_t H_time;         /* L Width period */
+    uint32_t tmp_L_width;
+    uint32_t tmp_H_width;
+    uint32_t remainder;
+    uint32_t wk_cks = 0;
+
+    /* set PCLK */
+    if (false == RZ_A1_IsClockMode0()) {
+        pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
+    } else {
+        pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
+    }
+
+    /* Min 10kHz, Max 400kHz */
+    if (hz < 10000) {
+        bps = 10000;
+    } else if (hz > 400000) {
+        bps = 400000;
+    } else {
+        bps = (float64_t)hz;
+    }
+
+    /* Calculation L width time */
+    L_time = (1 / (2 * bps));   /* Harf period of frequency */
+    H_time = L_time;
+
+    /* Check I2C mode of Speed */
+    if (bps > 100000) {
+        /* Fast-mode */
+        L_time -= 102E-9;    /* Falling time of SCL clock. */
+        H_time -= 138E-9;    /* Rising time of SCL clock. */
+        /* Check L wideth */
+        if (L_time < 1.3E-6) {
+            /* Wnen L width less than 1.3us */
+            /* Subtract Rise up and down time for SCL from H/L width */
+            L_time = 1.3E-6;
+            H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
+        }
+    }
+
+    tmp_L_width   = (uint32_t)(L_time * pclk_val * 10);
+    tmp_L_width >>= 1;
+    wk_cks++;
+    while (tmp_L_width >= 341) {
+        tmp_L_width >>= 1;
+        wk_cks++;
+    }
+    remainder   = tmp_L_width % 10;
+    tmp_L_width = ((tmp_L_width + 9) / 10) - 3;       /* carry */
+
+    tmp_H_width   = (uint32_t)(H_time * pclk_val * 10);
+    tmp_H_width >>= wk_cks;
+    if (remainder == 0) {
+        tmp_H_width   = ((tmp_H_width + 9) / 10) - 3; /* carry */
+    } else {
+        remainder    += tmp_H_width % 10;
+        tmp_H_width   = (tmp_H_width / 10) - 3;
+        if (remainder > 10) {
+            tmp_H_width += 1;                         /* fine adjustment */
+        }
+    }
+    /* timeout of BBSY bit is minimum low width by frequency */
+    /* so timeout calculates "(low width) * 2" by frequency */
+    wait_utime = (L_time * 2) * 1000000;
+    /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
+    if (wait_utime <= 0.3) {
+        obj->bbsy_wait_cnt = 1;
+    } else {
+        obj->bbsy_wait_cnt = (int)(wait_utime / 0.3);
+    }
+
+
+    /* I2C Rate */
+    obj->pclk_bit  = (uint8_t)(0x10 * wk_cks);        /* P_phi / xx */
+    obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0);
+    obj->width_hi  = (uint8_t)(tmp_H_width | 0x000000E0);
+
+    /* full reset */
+    i2c_reg_reset(obj);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+    int count = 0;
+    int status;
+    int value;
+    volatile uint32_t work_reg = 0;
+
+    if(length <= 0) {
+        return 0;
+    }
+    i2c_set_MR3_ACK(obj);
+    /* There is a STOP condition for last processing */
+    if (obj->last_stop_flag != 0) {
+        status = i2c_start(obj);
+        if (status != 0) {
+            i2c_set_err_noslave(obj);
+            return I2C_ERROR_BUS_BUSY;
+        }
+    }
+    obj->last_stop_flag = stop;
+    /*  Send Slave address */
+    status = i2c_read_address_write(obj, (address | 0x01));
+    if (status != 0) {
+        i2c_set_err_noslave(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    /* wait RDRF */
+    status = i2c_wait_RDRF(obj);
+    /* check ACK/NACK */
+    if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
+        /* Slave sends NACK */
+        (void)i2c_set_STOP(obj);
+        /* dummy read */
+        value = REG(DRR.UINT32);
+        (void)i2c_wait_STOP(obj);
+        i2c_set_SR2_NACKF_STOP(obj);
+        obj->last_stop_flag = 1;
+        return I2C_ERROR_NO_SLAVE;
+    }
+    /* Read in all except last byte */
+    if (length > 2) {
+        /* dummy read */
+        value = REG(DRR.UINT32);
+        for (count = 0; count < (length - 1); count++) {
+            /* wait for it to arrive */
+            status = i2c_wait_RDRF(obj);
+            if (status != 0) {
+                i2c_set_err_noslave(obj);
+                return I2C_ERROR_NO_SLAVE;
+            }
+            /* Recieve the data */
+            if (count == (length - 2)) {
+                value = i2c_do_read(obj, 1);
+            } else if ((length >= 3) && (count == (length - 3))) {
+                value = i2c_do_read(obj, 2);
+            } else {
+                value = i2c_do_read(obj, 0);
+            }
+            data[count] = (char)value;
+        }
+    } else if (length == 2) {
+        /* Set MR3 WATI bit is 1 */
+        REG(MR3.UINT32) |= MR3_WAIT;
+        /* dummy read */
+        value = REG(DRR.UINT32);
+        /* wait for it to arrive */
+        status = i2c_wait_RDRF(obj);
+        if (status != 0) {
+            i2c_set_err_noslave(obj);
+            return I2C_ERROR_NO_SLAVE;
+        }
+        i2c_set_MR3_NACK(obj);
+        data[count] = (char)REG(DRR.UINT32);
+        count++;
+    } else {
+        /* length == 1 */
+        /* Set MR3 WATI bit is 1 */;
+        REG(MR3.UINT32) |=  MR3_WAIT;
+        i2c_set_MR3_NACK(obj);
+        /* dummy read */
+        value = REG(DRR.UINT32);
+    }
+    /* wait for it to arrive */
+    status = i2c_wait_RDRF(obj);
+    if (status != 0) {
+        i2c_set_err_noslave(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    /* If not repeated start, send stop. */
+    if (stop) {
+        (void)i2c_set_STOP(obj);
+        /* RIICnDRR read */
+        value = (REG(DRR.UINT32) & 0xFF);
+        data[count] = (char)value;
+        /* RIICnMR3.WAIT = 0 */
+        REG(MR3.UINT32) &= ~MR3_WAIT;
+        (void)i2c_wait_STOP(obj);
+        i2c_set_SR2_NACKF_STOP(obj);
+    } else {
+        (void)i2c_restart(obj);
+        /* RIICnDRR read */
+        value = (REG(DRR.UINT32) & 0xFF);
+        data[count] = (char)value;
+        /* RIICnMR3.WAIT = 0 */
+        REG(MR3.UINT32) &= ~MR3_WAIT;
+        (void)i2c_wait_START(obj);
+        /* SR2.START = 0 */
+        REG(SR2.UINT32) &= ~SR2_START;
+    }
+
+    return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+    int cnt;
+    int status;
+
+    if(length <= 0) {
+        return 0;
+    }
+
+    /* There is a STOP condition for last processing */
+    if (obj->last_stop_flag != 0) {
+        status = i2c_start(obj);
+        if (status != 0) {
+            i2c_set_err_noslave(obj);
+            return I2C_ERROR_BUS_BUSY;
+        }
+    }
+    obj->last_stop_flag = stop;
+    /*  Send Slave address */
+    status = i2c_do_write(obj, address);
+    if (status != 0) {
+        i2c_set_err_noslave(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    /* Wait send end */
+    status = i2c_wait_TEND(obj);
+    if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
+        /* Slave sends NACK */
+        i2c_set_err_noslave(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    /* Send Write data */
+    for (cnt=0; cnt<length; cnt++) {
+        status = i2c_do_write(obj, data[cnt]);
+        if(status != 0) {
+            i2c_set_err_noslave(obj);
+            return cnt;
+        } else {
+            /* Wait send end */
+            status = i2c_wait_TEND(obj);
+            if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
+                /* Slave sends NACK */
+                i2c_set_err_noslave(obj);
+                return I2C_ERROR_NO_SLAVE;
+            }
+        }
+    }
+    /* If not repeated start, send stop. */
+    if (stop) {
+        (void)i2c_set_STOP(obj);
+        (void)i2c_wait_STOP(obj);
+        i2c_set_SR2_NACKF_STOP(obj);
+    } else {
+        (void)i2c_restart(obj);
+        (void)i2c_wait_START(obj);
+        /* SR2.START = 0 */
+        REG(SR2.UINT32) &= ~SR2_START;
+
+    }
+    
+    return length;
+}
+
+void i2c_reset(i2c_t *obj) {
+    (void)i2c_set_STOP(obj);
+    (void)i2c_wait_STOP(obj);
+    i2c_set_SR2_NACKF_STOP(obj);
+}
+
+int i2c_byte_read(i2c_t *obj, int last) {
+    int status;
+    int data;
+
+    data = i2c_do_read(obj, last);
+    /* wait for it to arrive */
+    status = i2c_wait_RDRF(obj);
+    if (status != 0) {
+        i2c_set_SR2_NACKF_STOP(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+    
+    return data;
+}
+
+int i2c_byte_write(i2c_t *obj, int data) {
+    int ack = 0;
+    int status;
+    int timeout = 0;
+    
+    status = i2c_do_write(obj, (data & 0xFF));
+    if (status != 0) {
+        i2c_set_SR2_NACKF_STOP(obj);
+    } else {
+        while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) {
+            timeout++;
+            if (timeout >= WAIT_TIMEOUT) {
+                return ack;
+            }
+        }
+        /* check ACK/NACK */
+        if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
+            /* NACK */
+            i2c_set_SR2_NACKF_STOP(obj);
+        } else {
+            ack = 1;
+        }
+    }
+
+    return ack;
+}
+
+void i2c_slave_mode(i2c_t *obj, int enable_slave) {
+    if (enable_slave != 0) {
+        REG(SER.UINT32) |= SER_SAR0E;   // only slave addr 0 is enabled
+    } else {
+        REG(SER.UINT32) &= ~SER_SAR0E;  // no slave addr enabled
+    }
+}
+
+int i2c_slave_receive(i2c_t *obj) {
+    int status;
+    int retval;
+
+    status = (REG(SR1.UINT8[0]) & SR1_AAS0);
+    status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
+
+    switch(status) {
+        case 0x01:
+            /* the master is writing to this slave */
+            retval = 3;
+            break;
+        case 0x02:
+            /* the master is writing to all slave  */
+            retval = 2;
+            break;
+        case 0x03:
+            /* the master has requested a read from this slave */
+            retval = 1;
+            break;
+        default :
+            /* no data */
+            retval = 0;
+            break;
+    }
+
+    return retval;
+}
+
+int i2c_slave_read(i2c_t *obj, char *data, int length) {
+    int timeout = 0;
+    int count;
+    int break_flg = 0;
+
+    if(length <= 0) {
+        return 0;
+    }
+    for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
+        /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
+        while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
+            if ((i2c_status(obj) & SR2_STOP) != 0) {
+                break_flg = 1;
+                break;
+            }
+            timeout ++;
+            if (timeout >= WAIT_TIMEOUT) {
+                return -1;
+            }
+        }
+        if (break_flg == 0) {
+            if (count == 0) {
+                /* dummy read */
+                (void)REG(DRR.UINT32);
+            } else {
+                data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
+            }
+        }
+    }
+    if (break_flg == 0) {
+        (void)i2c_wait_STOP(obj);
+    } else {
+        if ((i2c_status(obj) & SR2_RDRF) != 0) {
+            if (count <= 1) {
+                /* fail safe */
+                /* dummy read */
+                (void)REG(DRR.UINT32);
+            } else {
+                data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
+            }
+        }
+    }
+    /* SR2.STOP = 0 */
+    REG(SR2.UINT32) &= ~SR2_STOP;
+
+    return (count - 1);
+}
+
+int i2c_slave_write(i2c_t *obj, const char *data, int length) {
+    int count = 0;
+    int status = 0;
+
+    if(length <= 0) {
+        return 0;
+    }
+
+    while ((count < length) && (status == 0)) {
+        status = i2c_do_write(obj, data[count]);
+        if(status == 0) {
+            /* Wait send end */
+            status = i2c_wait_TEND(obj);
+            if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) {
+                /* NACK */
+                break;
+            }
+        }
+        count++;
+    }
+    /* dummy read */
+    (void)REG(DRR.UINT32);
+    (void)i2c_wait_STOP(obj);
+    i2c_set_SR2_NACKF_STOP(obj);
+
+    return count;
+}
+
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
+    REG(SAR0.UINT32) = (address & 0xfffffffe);
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/objects.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include <stdint.h>
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "gpio_object.h"
+#include "rspi_iodefine.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct i2c_s {
+    uint32_t i2c;
+    uint32_t dummy;
+    uint8_t  pclk_bit;
+    uint8_t  width_low;
+    uint8_t  width_hi;
+    int      bbsy_wait_cnt;
+    int      last_stop_flag;
+};
+
+struct spi_s {
+    struct st_rspi *spi;
+    uint32_t       bits;
+};
+
+struct gpio_irq_s {
+    uint32_t port;
+    uint32_t pin;
+    uint32_t ch;
+    uint8_t  int_enable;
+};
+
+struct port_s {
+    __IO uint32_t *reg_dir;
+    __IO uint32_t *reg_out;
+    __I  uint32_t *reg_in;
+    __IO uint32_t *reg_buf;
+    PortName port;
+    uint32_t mask;
+};
+
+struct serial_s {
+    struct st_scif *uart;
+    int index;
+};
+
+struct pwmout_s {
+    uint32_t ch;
+    PWMName pwm;
+};
+
+struct analogin_s {
+    ADCName adc;
+};
+
+struct can_s {
+    uint32_t ch;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/pinmap.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,193 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "gpio_addrdefine.h"
+
+PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */
+
+typedef struct {
+    PinName pin;
+    int function;
+    int pm;
+} PinFunc;
+
+#ifdef MAX_PERI
+static const PinFunc PIPC_0_tbl[] = {
+//   pin      func     pm
+    {P4_0   , 2      , -1}, /* TIOC0A */
+    {P5_0   , 6      , -1}, /* TIOC0A */
+    {P7_0   , 7      , -1}, /* TIOC0A */
+    {P4_1   , 2      , -1}, /* TIOC0B */
+    {P5_1   , 6      , -1}, /* TIOC0B */
+    {P7_1   , 7      , -1}, /* TIOC0B */
+    {P4_2   , 2      , -1}, /* TIOC0C */
+    {P5_5   , 6      , -1}, /* TIOC0C */
+    {P7_2   , 7      , -1}, /* TIOC0C */
+    {P4_3   , 2      , -1}, /* TIOC0D */
+    {P5_7   , 6      , -1}, /* TIOC0D */
+    {P7_3   , 7      , -1}, /* TIOC0D */
+    {P2_11  , 5      , -1}, /* TIOC1A */
+    {P6_0   , 5      , -1}, /* TIOC1A */
+    {P7_4   , 7      , -1}, /* TIOC1A */
+    {P8_8   , 5      , -1}, /* TIOC1A */
+    {P9_7   , 4      , -1}, /* TIOC1A */
+    {P2_12  , 8      , -1}, /* TIOC1B */
+    {P5_2   , 6      , -1}, /* TIOC1B */
+    {P6_1   , 5      , -1}, /* TIOC1B */
+    {P7_5   , 7      , -1}, /* TIOC1B */
+    {P8_9   , 5      , -1}, /* TIOC1B */
+    {P2_1   , 6      , -1}, /* TIOC2A */
+    {P6_2   , 6      , -1}, /* TIOC2A */
+    {P7_6   , 7      , -1}, /* TIOC2A */
+    {P8_14  , 4      , -1}, /* TIOC2A */
+    {P2_2   , 6      , -1}, /* TIOC2B */
+    {P6_3   , 6      , -1}, /* TIOC2B */
+    {P7_7   , 7      , -1}, /* TIOC2B */
+    {P8_15  , 4      , -1}, /* TIOC2B */
+    {P3_4   , 6      , -1}, /* TIOC3A */
+    {P7_8   , 7      , -1}, /* TIOC3A */
+    {P8_10  , 4      , -1}, /* TIOC3A */
+    {P3_5   , 6      , -1}, /* TIOC3B */
+    {P7_9   , 7      , -1}, /* TIOC3B */
+    {P8_11  , 4      , -1}, /* TIOC3B */
+    {P3_6   , 6      , -1}, /* TIOC3C */
+    {P5_3   , 6      , -1}, /* TIOC3C */
+    {P7_10  , 7      , -1}, /* TIOC3C */
+    {P8_12  , 4      , -1}, /* TIOC3C */
+    {P3_7   , 6      , -1}, /* TIOC3D */
+    {P5_4   , 6      , -1}, /* TIOC3D */
+    {P7_11  , 7      , -1}, /* TIOC3D */
+    {P8_13  , 4      , -1}, /* TIOC3D */
+    {P3_8   , 6      , -1}, /* TIOC4A */
+    {P4_4   , 3      , -1}, /* TIOC4A */
+    {P7_12  , 7      , -1}, /* TIOC4A */
+    {P3_9   , 6      , -1}, /* TIOC4B */
+    {P4_5   , 3      , -1}, /* TIOC4B */
+    {P7_13  , 7      , -1}, /* TIOC4B */
+    {P3_10  , 6      , -1}, /* TIOC4C */
+    {P4_6   , 3      , -1}, /* TIOC4C */
+    {P7_14  , 7      , -1}, /* TIOC4C */
+    {P3_11  , 6      , -1}, /* TIOC4D */
+    {P4_7   , 3      , -1}, /* TIOC4D */
+    {P7_15  , 7      , -1}, /* TIOC4D */
+    {P5_7   , 1      , 1 }, /* TXOUT0M   */
+    {P5_6   , 1      , 1 }, /* TXOUT0P   */
+    {P5_5   , 1      , 1 }, /* TXOUT1M   */
+    {P5_4   , 1      , 1 }, /* TXOUT1P   */
+    {P5_3   , 1      , 1 }, /* TXOUT2M   */
+    {P5_2   , 1      , 1 }, /* TXOUT2P   */
+    {P5_1   , 1      , 1 }, /* TXCLKOUTM */
+    {P5_0   , 1      , 1 }, /* TXCLKOUTP */
+    {P2_11  , 4      , 0 }, /* SSITxD0 */
+    {P4_7   , 5      , 0 }, /* SSITxD0 */
+    {P7_4   , 6      , 0 }, /* SSITxD1 */
+    {P4_15  , 6      , 0 }, /* SSITxD3 */
+    {P7_11  , 2      , 0 }, /* SSITxD3 */
+    {P2_7   , 4      , 0 }, /* SSITxD5 */
+    {P4_11  , 5      , 0 }, /* SSITxD5 */
+    {P8_10  , 8      , 0 }, /* SSITxD5 */
+    {P3_7   , 8      , 0 }, /* WDTOVF */
+    {NC     , 0      , -1}
+};
+#else
+static const PinFunc PIPC_0_tbl[] = {
+    //   pin      func     pm
+    {P4_0   , 2      , -1}, // TIOC0A
+    {P5_0   , 6      , -1}, // TIOC0A
+    {P4_2   , 2      , -1}, // TIOC0C
+    {P5_5   , 6      , -1}, // TIOC0C
+    //
+    {P8_14  , 4      , -1}, // TIOC2A
+    //
+    {P8_10  , 4      , -1}, // TIOC3A
+    {P5_3   , 6      , -1}, // TIOC3C
+    {P8_12  , 4      , -1}, // TIOC3C
+    //
+    {P3_8   , 6      , -1}, // TIOC4A
+    {P4_4   , 3      , -1}, // TIOC4A
+    {P3_10  , 6      , -1}, // TIOC4C
+    {P4_6   , 3      , -1}, // TIOC4C
+    //
+    {P5_7   , 1      , 1 }, // TXOUT0M
+    {P5_6   , 1      , 1 }, // TXOUT0P
+    {P5_5   , 1      , 1 }, // TXOUT1M
+    {P5_4   , 1      , 1 }, // TXOUT1P
+    {P5_3   , 1      , 1 }, // TXOUT2M
+    {P5_2   , 1      , 1 }, // TXOUT2P
+    {P5_1   , 1      , 1 }, // TXCLKOUTM
+    {P5_0   , 1      , 1 }, // TXCLKOUTP
+    {P4_7   , 5      , 0 }, // SSITxD0
+    {P8_10  , 8      , 0 }, // SSITxD5
+    {P3_7   , 8      , 0 }, // WDTOVF
+    {NC     , 0      , -1}
+};
+#endif
+
+void pin_function(PinName pin, int function) {
+    if (pin == (PinName)NC) return;
+    
+    int n = pin >> 4;
+    int bitmask = 1<<(pin  & 0xf);
+    const PinFunc * Pipc_0_func = PIPC_0_tbl;
+    int pipc_data = 1;
+    
+    if (gpio_multi_guard != pin) {
+        if (function == 0) {
+            // means GPIO mode
+            *PMC(n) &= ~bitmask;
+        } else {
+            // alt-function mode
+            --function;
+
+            if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else  { *PFCAE(n) &= ~bitmask;}
+            if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else  { *PFCE(n) &= ~bitmask;}
+            if (function & (1 << 0)) { *PFC(n) |= bitmask;}else  { *PFC(n) &= ~bitmask;}
+
+            while (Pipc_0_func->pin != NC) {
+                if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) {
+                    pipc_data = 0;
+                    if (Pipc_0_func->pm == 0) {
+                        *PMSR(n) = (bitmask << 16) | 0;
+                    } else if (Pipc_0_func->pm == 1) {
+                        *PMSR(n) = (bitmask << 16) | bitmask;
+                    } else {
+                        // Do Nothing
+                    }
+                    break;
+                }
+                Pipc_0_func++;
+            }
+            if (pipc_data == 1) {
+            *PIPC(n) |= bitmask;
+            } else {
+                *PIPC(n) &= ~bitmask;
+            }
+
+            if (P1_0 <= pin && pin <= P1_7 && function == 0) {
+                *PBDC(n) |= bitmask;
+            }
+            *PMC(n) |= bitmask;
+        }
+    } else {
+        gpio_multi_guard = (PinName)NC;
+    }
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+//    if (pin == (PinName)NC) { return; }
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/port_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,75 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "gpio_addrdefine.h"
+
+PinName port_pin(PortName port, int pin_n) {
+    return (PinName)((port*0x10)+pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
+    obj->port = port;
+    obj->mask = mask;
+    
+    obj->reg_dir = (volatile uint32_t *)PMSR(port);
+    obj->reg_out = (volatile uint32_t *)PORT(port);
+    obj->reg_in  = (volatile uint32_t *)PPR(port);
+    obj->reg_buf = (volatile uint32_t *)PIBC(port);
+    // Do not use masking, because it prevents the use of the unmasked pins
+    // port_reg->FIOMASK = ~mask;
+    
+    uint32_t i;
+    // The function is set per pin: reuse gpio logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            gpio_set(port_pin(obj->port, i));
+        }
+    }
+
+    port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode) {
+    uint32_t i;
+    // The mode is set per pin: reuse pinmap logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir) {
+    switch (dir) {
+        case PIN_INPUT : *obj->reg_dir = (obj->mask << 16) | obj->mask;
+			 *obj->reg_buf |=  obj->mask;
+	break;
+        case PIN_OUTPUT: *obj->reg_dir = (obj->mask << 16) | ~obj->mask;
+			 *obj->reg_buf &= ~obj->mask;
+	break;
+    }
+}
+
+void port_write(port_t *obj, int value) {
+    *obj->reg_out = (obj->mask << 16) | (value & obj->mask);
+}
+
+int port_read(port_t *obj) {
+    return (*obj->reg_in & obj->mask);
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/pwmout_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,706 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "RZ_A1_Init.h"
+#include "cpg_iodefine.h"
+#include "pwm_iodefine.h"
+#include "gpio_addrdefine.h"
+
+#ifdef MAX_PERI
+#define MTU2_PWM_NUM            27
+#define MTU2_PWM_SIGNAL         2
+#define MTU2_PWM_OFFSET         0x20
+
+//  PORT ID, PWM ID, Pin function
+static const PinMap PinMap_PWM[] = {
+    // TIOC0 A,C
+    {P4_0     , MTU2_PWM0_PIN  , 2},	//TIOC0A
+    {P5_0     , MTU2_PWM1_PIN  , 6},	//TIOC0A
+    {P7_0     , MTU2_PWM2_PIN  , 7},	//TIOC0A
+    {P4_2     , MTU2_PWM3_PIN  , 2},	//TIOC0C
+    {P5_5     , MTU2_PWM4_PIN  , 6},	//TIOC0C
+    {P7_2     , MTU2_PWM5_PIN  , 7},	//TIOC0C
+    //TIOC1 A
+    {P2_11    , MTU2_PWM6_PIN  , 5},	//TIOC1A
+    {P6_0     , MTU2_PWM7_PIN  , 5},	//TIOC1A
+    {P7_4     , MTU2_PWM8_PIN  , 7},	//TIOC1A
+    {P8_8     , MTU2_PWM9_PIN  , 5},	//TIOC1A
+    {P9_7     , MTU2_PWM10_PIN , 4},	//TIOC1A
+    //TIOC2 A
+    {P2_1     , MTU2_PWM11_PIN , 6},	//TIOC2A
+    {P6_2     , MTU2_PWM12_PIN , 6},	//TIOC2A
+    {P7_6     , MTU2_PWM13_PIN , 7},	//TIOC2A
+    {P8_14    , MTU2_PWM14_PIN , 4},	//TIOC2A
+    //TIOC3 A,C
+    {P3_4     , MTU2_PWM15_PIN , 6},	//TIOC3A
+    {P7_8     , MTU2_PWM16_PIN , 7},	//TIOC3A
+    {P8_10    , MTU2_PWM17_PIN , 4},	//TIOC3A
+    {P3_6     , MTU2_PWM18_PIN , 6},	//TIOC3C
+    {P7_10    , MTU2_PWM19_PIN , 7},	//TIOC3C
+    {P8_12    , MTU2_PWM20_PIN , 4},	//TIOC3C
+    //TIOC4 A,C
+    {P3_8     , MTU2_PWM21_PIN , 6},	//TIOC4A
+    {P4_4     , MTU2_PWM22_PIN , 3},	//TIOC4A
+    {P7_12    , MTU2_PWM23_PIN , 7},	//TIOC4A
+    {P3_10    , MTU2_PWM24_PIN , 6},	//TIOC4C
+    {P4_6     , MTU2_PWM25_PIN , 3},	//TIOC4C
+    {P7_14    , MTU2_PWM26_PIN , 7},	//TIOC4C
+    //PWM1
+    {P8_8     , PWM0_PIN       , 6},	//PWM1A
+    {P8_9     , PWM1_PIN       , 6},	//PWM1B
+    {P8_10    , PWM2_PIN       , 6},	//PWM1C
+    {P8_11    , PWM3_PIN       , 6},	//PWM1D
+    {P8_12    , PWM4_PIN       , 6},	//PWM1E
+    {P8_13    , PWM5_PIN       , 6},	//PWM1F
+    {P8_14    , PWM6_PIN       , 6},	//PWM1G
+    {P8_15    , PWM7_PIN       , 6},	//PWM1H
+    //PWM2
+    {P3_0     , PWM8_PIN       , 7},	//PWM2A
+    {P3_1     , PWM9_PIN       , 7},	//PWM2B
+    {P3_2     , PWM10_PIN      , 7},	//PWM2C
+    {P3_3     , PWM11_PIN      , 7},	//PWM2D
+    {P4_4     , PWM12_PIN      , 4},	//PWM2E
+    {P4_5     , PWM13_PIN      , 4},	//PWM2F
+    {P4_6     , PWM14_PIN      , 4},	//PWM2G
+    {P4_7     , PWM15_PIN      , 4},	//PWM2H
+    {NC       , NC             , 0}
+};
+
+static const PWMType PORT[] = {
+    PWM1A,          // PWM0_PIN
+    PWM1B,          // PWM1_PIN
+    PWM1C,          // PWM2_PIN
+    PWM1D,          // PWM3_PIN
+    PWM1E,          // PWM4_PIN
+    PWM1F,          // PWM5_PIN
+    PWM1G,          // PWM6_PIN
+    PWM1H,          // PWM7_PIN
+    PWM2A,          // PWM8_PIN
+    PWM2B,          // PWM9_PIN
+    PWM2C,          // PWM10_PIN
+    PWM2D,          // PWM11_PIN
+    PWM2E,          // PWM12_PIN
+    PWM2F,          // PWM13_PIN
+    PWM2G,          // PWM14_PIN
+    PWM2H,          // PWM15_PIN
+};
+
+static const MTU2_PWMType MTU2_PORT[] = {
+    TIOC0A,         // MTU2_PWM0_PIN
+    TIOC0A,         // MTU2_PWM1_PIN
+    TIOC0A,         // MTU2_PWM2_PIN
+    TIOC0C,         // MTU2_PWM3_PIN
+    TIOC0C,         // MTU2_PWM4_PIN
+    TIOC0C,         // MTU2_PWM5_PIN
+    TIOC1A,         // MTU2_PWM6_PIN
+    TIOC1A,         // MTU2_PWM7_PIN
+    TIOC1A,         // MTU2_PWM8_PIN
+    TIOC1A,         // MTU2_PWM9_PIN
+    TIOC1A,         // MTU2_PWM10_PIN
+    TIOC2A,         // MTU2_PWM11_PIN
+    TIOC2A,         // MTU2_PWM12_PIN
+    TIOC2A,         // MTU2_PWM13_PIN
+    TIOC2A,         // MTU2_PWM14_PIN
+    TIOC3A,         // MTU2_PWM15_PIN
+    TIOC3A,         // MTU2_PWM16_PIN
+    TIOC3A,         // MTU2_PWM17_PIN
+    TIOC3C,         // MTU2_PWM18_PIN
+    TIOC3C,         // MTU2_PWM19_PIN
+    TIOC3C,         // MTU2_PWM20_PIN
+    TIOC4A,         // MTU2_PWM21_PIN
+    TIOC4A,         // MTU2_PWM22_PIN
+    TIOC4A,         // MTU2_PWM23_PIN
+    TIOC4C,         // MTU2_PWM24_PIN
+    TIOC4C,         // MTU2_PWM25_PIN
+    TIOC4C,         // MTU2_PWM26_PIN
+};
+
+static __IO uint16_t *PWM_MATCH[] = {
+    &PWMPWBFR_1A,    // PWM0_PIN
+    &PWMPWBFR_1A,    // PWM1_PIN
+    &PWMPWBFR_1C,    // PWM2_PIN
+    &PWMPWBFR_1C,    // PWM3_PIN
+    &PWMPWBFR_1E,    // PWM4_PIN
+    &PWMPWBFR_1E,    // PWM5_PIN
+    &PWMPWBFR_1G,    // PWM6_PIN
+    &PWMPWBFR_1G,    // PWM7_PIN
+    &PWMPWBFR_2A,    // PWM8_PIN
+    &PWMPWBFR_2A,    // PWM9_PIN
+    &PWMPWBFR_2C,    // PWM10_PIN
+    &PWMPWBFR_2C,    // PWM11_PIN
+    &PWMPWBFR_2E,    // PWM12_PIN
+    &PWMPWBFR_2E,    // PWM13_PIN
+    &PWMPWBFR_2G,    // PWM14_PIN
+    &PWMPWBFR_2G,    // PWM15_PIN
+};
+
+static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = {
+    { &MTU2TGRA_0, &MTU2TGRB_0 }		// MTU2_PWM0_PIN
+    { &MTU2TGRA_0, &MTU2TGRB_0 }		// MTU2_PWM1_PIN
+    { &MTU2TGRA_0, &MTU2TGRB_0 }		// MTU2_PWM2_PIN
+    { &MTU2TGRC_0, &MTU2TGRD_0 }		// MTU2_PWM3_PIN
+    { &MTU2TGRC_0, &MTU2TGRD_0 }		// MTU2_PWM4_PIN
+    { &MTU2TGRC_0, &MTU2TGRD_0 }		// MTU2_PWM5_PIN
+    { &MTU2TGRA_1, &MTU2TGRB_1 }		// MTU2_PWM6_PIN
+    { &MTU2TGRA_1, &MTU2TGRB_1 }		// MTU2_PWM7_PIN
+    { &MTU2TGRA_1, &MTU2TGRB_1 }		// MTU2_PWM8_PIN
+    { &MTU2TGRA_1, &MTU2TGRB_1 }		// MTU2_PWM9_PIN
+    { &MTU2TGRA_1, &MTU2TGRB_1 }		// MTU2_PWM10_PIN
+    { &MTU2TGRA_2, &MTU2TGRB_2 }		// MTU2_PWM11_PIN
+    { &MTU2TGRA_2, &MTU2TGRB_2 }		// MTU2_PWM12_PIN
+    { &MTU2TGRA_2, &MTU2TGRB_2 }		// MTU2_PWM13_PIN
+    { &MTU2TGRA_2, &MTU2TGRB_2 }		// MTU2_PWM14_PIN
+    { &MTU2TGRA_3, &MTU2TGRB_3 }		// MTU2_PWM15_PIN
+    { &MTU2TGRA_3, &MTU2TGRB_3 }		// MTU2_PWM16_PIN
+    { &MTU2TGRA_3, &MTU2TGRB_3 }		// MTU2_PWM17_PIN
+    { &MTU2TGRC_3, &MTU2TGRD_3 }		// MTU2_PWM18_PIN
+    { &MTU2TGRC_3, &MTU2TGRD_3 }		// MTU2_PWM19_PIN
+    { &MTU2TGRC_3, &MTU2TGRD_3 }		// MTU2_PWM20_PIN
+    { &MTU2TGRA_4, &MTU2TGRB_2 }		// MTU2_PWM21_PIN
+    { &MTU2TGRA_4, &MTU2TGRB_2 }		// MTU2_PWM22_PIN
+    { &MTU2TGRA_4, &MTU2TGRB_2 }		// MTU2_PWM23_PIN
+    { &MTU2TGRC_4, &MTU2TGRD_4 } 		// MTU2_PWM24_PIN
+    { &MTU2TGRC_4, &MTU2TGRD_4 }		// MTU2_PWM25_PIN
+    { &MTU2TGRC_4, &MTU2TGRD_4 }		// MTU2_PWM26_PIN
+};
+#else
+#define MTU2_PWM_NUM            12
+#define MTU2_PWM_SIGNAL         2
+#define MTU2_PWM_OFFSET         0x20
+
+//  PORT ID, PWM ID, Pin function
+static const PinMap PinMap_PWM[] = {
+    //TIOC0 A,C
+    {P4_0     , MTU2_PWM0_PIN  , 2},	//TIOC0A
+    {P5_0     , MTU2_PWM1_PIN  , 6},	//TIOC0A
+    {P4_2     , MTU2_PWM2_PIN  , 2},	//TIOC0C
+    {P5_5     , MTU2_PWM3_PIN  , 6},	//TIOC0C
+    //TIOC2 A
+    {P8_14    , MTU2_PWM4_PIN  , 4},	//TIOC2A
+    //TIOC3 A,C
+    {P8_10    , MTU2_PWM5_PIN  , 4},	//TIOC3A
+    {P5_3     , MTU2_PWM6_PIN  , 6}, 	//TIOC3C
+    {P8_12    , MTU2_PWM7_PIN  , 4},	//TIOC3C
+    //TIOC4 A,C
+    {P3_8     , MTU2_PWM8_PIN  , 6},	//TIOC4A
+    {P4_4     , MTU2_PWM9_PIN  , 3},	//TIOC4A
+    {P3_10    , MTU2_PWM10_PIN , 6},	//TIOC4C
+    {P4_6     , MTU2_PWM11_PIN , 3},	//TIOC4C
+    //PWM1
+    {P8_10    , PWM0_PIN       , 6},	//PWM1C
+    {P8_11    , PWM1_PIN       , 6},	//PWM1D
+    {P8_12    , PWM2_PIN       , 6},	//PWM1E
+    {P8_13    , PWM3_PIN       , 6},	//PWM1F
+    {P8_14    , PWM4_PIN       , 6},	//PWM1G
+    {P8_15    , PWM5_PIN       , 6},	//PWM1H
+    //PWM2
+    {P3_0     , PWM6_PIN       , 7},	//PWM2A
+    {P3_1     , PWM7_PIN       , 7},	//PWM2B
+    {P3_2     , PWM8_PIN       , 7},	//PWM2C
+    {P4_4     , PWM9_PIN       , 4},	//PWM2E
+    {P4_5     , PWM10_PIN      , 4},	//PWM2F
+    {P4_6     , PWM11_PIN      , 4},	//PWM2G
+    {P4_7     , PWM12_PIN      , 4},	//PWM2H
+    {NC       , NC             , 0}
+};
+
+static const PWMType PORT[] = {
+    PWM1C,          // PWM0_PIN
+    PWM1D,          // PWM1_PIN
+    PWM1E,          // PWM2_PIN
+    PWM1F,          // PWM3_PIN
+    PWM1G,          // PWM4_PIN
+    PWM1H,          // PWM5_PIN
+    PWM2A,          // PWM6_PIN
+    PWM2B,          // PWM7_PIN
+    PWM2C,          // PWM8_PIN
+    PWM2E,          // PWM9_PIN
+    PWM2F,          // PWM10_PIN
+    PWM2G,          // PWM11_PIN
+    PWM2H,          // PWM12_PIN
+};
+
+static const MTU2_PWMType MTU2_PORT[] = {
+    TIOC0A,         // MTU2_PWM0_PIN
+    TIOC0A,         // MTU2_PWM1_PIN
+    TIOC0C,         // MTU2_PWM2_PIN
+    TIOC0C,         // MTU2_PWM3_PIN
+    TIOC2A,         // MTU2_PWM4_PIN
+    TIOC3A,         // MTU2_PWM5_PIN
+    TIOC3C,         // MTU2_PWM6_PIN
+    TIOC3C,         // MTU2_PWM7_PIN
+    TIOC4A,         // MTU2_PWM8_PIN
+    TIOC4A,         // MTU2_PWM9_PIN
+    TIOC4C,         // MTU2_PWM10_PIN
+    TIOC4C,         // MTU2_PWM11_PIN
+};
+
+static __IO uint16_t *PWM_MATCH[] = {
+    &PWMPWBFR_1C,    // PWM0_PIN
+    &PWMPWBFR_1C,    // PWM1_PIN
+    &PWMPWBFR_1E,    // PWM2_PIN
+    &PWMPWBFR_1E,    // PWM3_PIN
+    &PWMPWBFR_1G,    // PWM4_PIN
+    &PWMPWBFR_1G,    // PWM5_PIN
+    &PWMPWBFR_2A,    // PWM6_PIN
+    &PWMPWBFR_2A,    // PWM7_PIN
+    &PWMPWBFR_2C,    // PWM8_PIN
+    &PWMPWBFR_2E,    // PWM9_PIN
+    &PWMPWBFR_2E,    // PWM10_PIN
+    &PWMPWBFR_2G,    // PWM11_PIN
+    &PWMPWBFR_2G,    // PWM12_PIN
+};
+
+static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = {
+    { &MTU2TGRA_0, &MTU2TGRB_0 },		// MTU2_PWM0_PIN
+    { &MTU2TGRA_0, &MTU2TGRB_0 },		// MTU2_PWM1_PIN
+    { &MTU2TGRC_0, &MTU2TGRD_0 },		// MTU2_PWM2_PIN
+    { &MTU2TGRC_0, &MTU2TGRD_0 },		// MTU2_PWM3_PIN
+    { &MTU2TGRA_2, &MTU2TGRB_2 },		// MTU2_PWM4_PIN
+    { &MTU2TGRA_3, &MTU2TGRB_3 },		// MTU2_PWM5_PIN
+    { &MTU2TGRC_3, &MTU2TGRD_3 },		// MTU2_PWM6_PIN
+    { &MTU2TGRC_3, &MTU2TGRD_3 },		// MTU2_PWM7_PIN
+    { &MTU2TGRA_4, &MTU2TGRB_2 },		// MTU2_PWM8_PIN
+    { &MTU2TGRA_4, &MTU2TGRB_2 },		// MTU2_PWM9_PIN
+    { &MTU2TGRC_4, &MTU2TGRD_4 },		// MTU2_PWM10_PIN
+    { &MTU2TGRC_4, &MTU2TGRD_4 },		// MTU2_PWM11_PIN
+};
+#endif
+
+
+static __IO uint8_t *TCR_MATCH[] = {
+    &MTU2TCR_0,
+    &MTU2TCR_1,
+    &MTU2TCR_2,
+    &MTU2TCR_3,
+    &MTU2TCR_4,
+};
+
+static __IO uint8_t *TIORH_MATCH[] = {
+    &MTU2TIORH_0,
+    &MTU2TIOR_1,
+    &MTU2TIOR_2,
+    &MTU2TIORH_3,
+    &MTU2TIORH_4,
+};
+
+static __IO uint8_t *TIORL_MATCH[] = {
+    &MTU2TIORL_0,
+    NULL,
+    NULL,
+    &MTU2TIORL_3,
+    &MTU2TIORL_4,
+};
+
+static __IO uint16_t *TGRA_MATCH[] = {
+    &MTU2TGRA_0,
+    &MTU2TGRA_1,
+    &MTU2TGRA_2,
+    &MTU2TGRA_3,
+    &MTU2TGRA_4,
+};
+
+static __IO uint16_t *TGRC_MATCH[] = {
+    &MTU2TGRC_0,
+    NULL,
+    NULL,
+    &MTU2TGRC_3,
+    &MTU2TGRC_4,
+};
+
+static __IO uint8_t *TMDR_MATCH[] = {
+    &MTU2TMDR_0,
+    &MTU2TMDR_1,
+    &MTU2TMDR_2,
+    &MTU2TMDR_3,
+    &MTU2TMDR_4,
+};
+
+static int MAX_PERIOD[] = {
+    125000,
+    503000,
+    2000000,
+    2000000,
+    2000000,
+};
+
+typedef enum {
+    MODE_PWM = 0,
+    MODE_MTU2
+} PWMmode;
+
+typedef enum {
+    MTU2_PULSE = 0,
+    MTU2_PERIOD
+} MTU2Signal;
+
+static int pwm_mode = MODE_PWM;
+static uint16_t init_period_ch1 = 0;
+static uint16_t init_period_ch2 = 0;
+static uint16_t init_mtu2_period_ch[5] = {0};
+static int32_t  period_ch1 = 1;
+static int32_t  period_ch2 = 1;
+static int32_t  mtu2_period_ch[5] = {1, 1, 1, 1, 1};
+
+void pwmout_init(pwmout_t* obj, PinName pin) {
+    // determine the channel
+    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+    MBED_ASSERT(pwm != (PWMName)NC);
+
+    if (pwm >= MTU2_PWM_OFFSET) {
+        /* PWM by MTU2 */
+        int tmp_pwm;
+        
+        pwm_mode = MODE_MTU2;
+        // power on
+        CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33);
+        
+        obj->pwm = pwm;
+        tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+        if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) {
+            obj->ch  = 4;
+            MTU2TOER |= 0x36;
+        } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) {
+            obj->ch  = 3;
+            MTU2TOER |= 0x09;
+        } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) {
+            obj->ch  = 2;
+        } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) {
+            obj->ch  = 1;
+        } else {
+            obj->ch  = 0;
+        }
+        // Wire pinout
+        pinmap_pinout(pin, PinMap_PWM);
+
+        int bitmask = 1 << (pin  & 0xf);
+
+        *PMSR(PINGROUP(pin)) = (bitmask << 16) | 0;
+
+        // default duty 0.0f
+        pwmout_write(obj, 0);
+        if (init_mtu2_period_ch[obj->ch] == 0) {
+            // default period 1ms
+            pwmout_period_us(obj, 1000);
+            init_mtu2_period_ch[obj->ch] = 1;
+        }
+    } else {
+        /* PWM */
+        pwm_mode = MODE_PWM;
+        // power on
+        CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30);
+
+        obj->pwm = pwm;
+        if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) {
+            obj->ch  = 2;
+            PWMPWPR_2_BYTE_L = 0x00;
+        } else {
+            obj->ch  = 1;
+            PWMPWPR_1_BYTE_L = 0x00;
+        }
+
+        // Wire pinout
+        pinmap_pinout(pin, PinMap_PWM);
+
+        // default to 491us: standard for servos, and fine for e.g. brightness control
+        pwmout_write(obj, 0);
+        if ((obj->ch == 2) && (init_period_ch2 == 0)) {
+            pwmout_period_us(obj, 491);
+            init_period_ch2 = 1;
+        }
+        if ((obj->ch == 1) && (init_period_ch1 == 0)) {
+            pwmout_period_us(obj, 491);
+            init_period_ch1 = 1;
+        }
+    }
+}
+
+void pwmout_free(pwmout_t* obj) {
+    pwmout_write(obj, 0);
+}
+
+void pwmout_write(pwmout_t* obj, float value) {
+    uint32_t wk_cycle;
+    uint16_t v;
+
+    if (pwm_mode == MODE_MTU2) {
+        /* PWM by MTU2 */
+        int tmp_pwm;
+        
+        if (value < 0.0f) {
+            value = 0.0f;
+        } else if (value > 1.0f) {
+            value = 1.0f;
+        } else {
+            // Do Nothing
+        }
+        tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+        wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
+        // set channel match to percentage
+        *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value);
+    } else {
+        /* PWM */
+        if (value < 0.0f) {
+            value = 0.0f;
+        } else if (value > 1.0f) {
+            value = 1.0f;
+        } else {
+            // Do Nothing
+        }
+
+        if (obj->ch == 2) {
+            wk_cycle = PWMPWCYR_2 & 0x03ff;
+        } else {
+            wk_cycle = PWMPWCYR_1 & 0x03ff;
+        }
+
+        // set channel match to percentage
+        v = (uint16_t)((float)wk_cycle * value);
+        *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12));
+    }
+}
+
+float pwmout_read(pwmout_t* obj) {
+    uint32_t wk_cycle;
+    float value;
+
+    if (pwm_mode == MODE_MTU2) {
+        /* PWM by MTU2 */
+        uint32_t wk_pulse;
+        int tmp_pwm;
+        
+        tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+        wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
+        wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff;
+        value = ((float)wk_pulse / (float)wk_cycle);
+    } else {
+        /* PWM */
+        if (obj->ch == 2) {
+            wk_cycle = PWMPWCYR_2 & 0x03ff;
+        } else {
+            wk_cycle = PWMPWCYR_1 & 0x03ff;
+        }
+        value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle);
+    }
+
+    return (value > 1.0f) ? (1.0f) : (value);
+}
+
+void pwmout_period(pwmout_t* obj, float seconds) {
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t* obj, int ms) {
+    pwmout_period_us(obj, ms * 1000);
+}
+
+static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
+    uint16_t wk_pwmpbfr;
+    float    value;
+    uint16_t v;
+
+    wk_pwmpbfr = *p_pwmpbfr;
+    value      = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle);
+    v          = (uint16_t)((float)new_cycle * value);
+    *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000));
+}
+
+static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
+    uint16_t wk_pwmpbfr;
+    float    value;
+
+    wk_pwmpbfr = *p_pwmpbfr;
+    value      = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle);
+    *p_pwmpbfr = (uint16_t)((float)new_cycle * value);
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t* obj, int us) {
+    uint64_t wk_cycle_mtu2;
+    uint32_t pclk_base;
+    uint32_t wk_cycle;
+    uint32_t wk_cks = 0;
+    uint16_t wk_last_cycle;
+    int      max_us = 0;
+
+    if (pwm_mode == MODE_MTU2) {
+        /* PWM by MTU2 */
+        int tmp_pwm;
+        uint16_t tmp_tgra;
+        uint16_t tmp_tgrc;
+        uint8_t tmp_tcr_up;
+        uint8_t tmp_tstr_sp;
+        uint8_t tmp_tstr_st;
+        
+        max_us = MAX_PERIOD[obj->ch];
+        if (us > max_us) {
+            us = max_us;
+        } else if (us < 1) {
+            us = 1;
+        } else {
+            // Do Nothing
+        }
+
+        if (RZ_A1_IsClockMode0() == false) {
+            pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK;
+        } else {
+            pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK;
+        }
+
+        wk_cycle_mtu2 = (uint64_t)pclk_base * us;
+        while (wk_cycle_mtu2 >= 65535000000) {
+            if ((obj->ch == 1) && (wk_cks == 3)) {
+                wk_cks+=2;
+            } else if ((obj->ch == 2) && (wk_cks == 3)) {
+                wk_cycle_mtu2 >>= 2;
+                wk_cks+=3;
+            }
+            wk_cycle_mtu2 >>= 2;
+            wk_cks++;
+        }
+        wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000);
+        
+        tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
+        if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) {
+            tmp_tcr_up = 0xC0;
+        } else {
+            tmp_tcr_up = 0x40;
+        }
+        if ((obj->ch == 4) || (obj->ch == 3)) {
+            tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3)));
+            tmp_tstr_st = (1 << (obj->ch + 3));
+        } else {
+            tmp_tstr_sp = ~(0x38 | (1 << obj->ch));
+            tmp_tstr_st = (1 << obj->ch);
+        }
+        // Counter Stop
+        MTU2TSTR &= tmp_tstr_sp;
+        wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
+        *TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks;
+        *TIORH_MATCH[obj->ch] = 0x21;
+        if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
+            *TIORL_MATCH[obj->ch] = 0x21;
+        }
+        *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle;     // Set period
+
+        // Set duty again(TGRA)
+        tmp_tgra = *TGRA_MATCH[obj->ch];
+        set_mtu2_duty_again(&tmp_tgra, wk_last_cycle, wk_cycle);
+        if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
+            // Set duty again(TGRC)
+            tmp_tgrc = *TGRC_MATCH[obj->ch];
+            set_mtu2_duty_again(&tmp_tgrc, wk_last_cycle, wk_cycle);
+        }
+        *TMDR_MATCH[obj->ch] = 0x02;                                    // PWM mode 1
+
+        // Counter Start
+        MTU2TSTR |= tmp_tstr_st;
+        // Save for future use
+        mtu2_period_ch[obj->ch] = us;
+    } else {
+        /* PWM */
+        if (us > 491) {
+            us = 491;
+        } else if (us < 1) {
+            us = 1;
+        } else {
+            // Do Nothing
+        }
+
+        if (RZ_A1_IsClockMode0() == false) {
+            pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000;
+        } else {
+            pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000;
+        }
+
+        wk_cycle = pclk_base * us;
+        while (wk_cycle >= 102350) {
+            wk_cycle >>= 1;
+            wk_cks++;
+        }
+        wk_cycle = (wk_cycle + 50) / 100;
+
+        if (obj->ch == 2) {
+            wk_last_cycle    = PWMPWCYR_2 & 0x03ff;
+            PWMPWCR_2_BYTE_L = 0xc0 | wk_cks;
+            PWMPWCYR_2       = (uint16_t)wk_cycle;
+
+            // Set duty again
+            set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle);
+
+            // Counter Start
+            PWMPWCR_2_BYTE_L |= 0x08;
+
+            // Save for future use
+            period_ch2 = us;
+        } else {
+            wk_last_cycle    = PWMPWCYR_1 & 0x03ff;
+            PWMPWCR_1_BYTE_L = 0xc0 | wk_cks;
+            PWMPWCYR_1       = (uint16_t)wk_cycle;
+
+            // Set duty again
+            set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle);
+            set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle);
+
+            // Counter Start
+            PWMPWCR_1_BYTE_L |= 0x08;
+
+            // Save for future use
+            period_ch1 = us;
+        }
+    }
+}
+
+void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
+    float value = 0;
+
+    if (pwm_mode == MODE_MTU2) {
+        /* PWM by MTU2 */
+        if (mtu2_period_ch[obj->ch] != 0) {
+            value = (float)us / (float)mtu2_period_ch[obj->ch];
+        }
+    } else {
+        /* PWM */
+        if (obj->ch == 2) {
+            if (period_ch2 != 0) {
+                value = (float)us / (float)period_ch2;
+            }
+        } else {
+            if (period_ch1 != 0) {
+                value = (float)us / (float)period_ch1;
+            }
+        }
+
+        pwmout_write(obj, value);
+    }
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/rtc_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,409 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_assert.h"
+#include "device.h"
+
+#if DEVICE_RTC
+
+#define USE_RTCX1_CLK
+//#define USE_EXTAL_CLK
+//#define USE_RTCX3_CLK
+
+#include "rtc_api.h"
+#include "rtc_iodefine.h"
+
+
+#define RCR1_VAL_ON      (0x08u) // AIE = 1
+#define RCR1_VAL_OFF     (0x00u)
+#define RCR3_VAL         (0x00u)
+#define RCR5_VAL		 (0x00u)
+
+#ifdef USE_RTCX1_CLK
+#define RCR2_VAL_ALLSTOP (0x08u)
+#define RCR2_VAL_START   (0x09u) // START = 1
+#define RCR2_VAL_RESET   (0x0Au) // RESET = 1
+#define RCR5_VAL_RTCX1   (0x00u) // RCKSEL = clock rtc from RTCX1(32.768 kHz)
+#elif defined(USE_EXTAL_CLK)
+#define RCR2_VAL_ALLSTOP (0x00u)
+#define RCR2_VAL_START   (0x01u) // START = 1
+#define RCR2_VAL_RESET   (0x02u) // RESET = 1
+#define RCR5_VAL_EXTAL   (0x01u) // RCKSEL = clock rtc from EXTAL
+#define RFRH_VAL_13333   (0x8003u) // 13.3333MHz (= 64Hz * 0x32DCD) 
+#define RFRL_VAL_13333   (0x2DCDu) //
+#elif defined(USE_RTCX3_CLK)
+#define RCR2_VAL_ALLSTOP (0x08u)
+#define RCR2_VAL_START   (0x09u) // START = 1
+#define RCR2_VAL_RESET   (0x0Au) // RESET = 1
+#define RCR5_VAL_RTCX3	 (0x02u) // RCKSEL = clock rtc from RTCX3(4.000 MHz)
+#define RFRH_VAL_4000   (0x8000u) // 4.000MHz (= 64Hz * 0xF424)
+#define RFRL_VAL_4000   (0xF424u) //
+#else
+#error Select RTC clock input !
+#endif
+
+#define RFRH_VAL_MAX     (0x0007u) // MAX value (= 128Hz * 0x7FFFF)
+#define RFRL_VAL_MAX     (0xFFFFu) //
+
+#define MASK_00_03_POS   (0x000Fu)
+#define MASK_04_07_POS   (0x00F0u)
+#define MASK_08_11_POS   (0x0F00u)
+#define MASK_12_15_POS   (0xF000u)
+#define MASK_16_20_POS   (0x000F0000u)
+#define SHIFT_1_HBYTE    (4u)
+#define SHIFT_2_HBYTE    (8u)
+#define SHIFT_3_HBYTE    (12u)
+#define SHIFT_1BYTE      (8u)
+#define SHIFT_2BYTE      (16u)
+
+#define TIME_ERROR_VAL   (0xFFFFFFFFu)
+
+static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val);
+static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val);
+static uint8_t rtc_hex8_to_dec(uint8_t hex_val);
+static uint16_t rtc_hex16_to_dec(uint16_t hex_val);
+
+
+/*
+ * Setup the RTC based on a time structure.
+ * The rtc_init function should be executed first.
+ * [in]
+ * None.
+ * [out]
+ * None.
+ */
+void rtc_init(void) {
+    volatile uint8_t dummy_read;
+
+    CPG.STBCR6 &= ~(CPG_STBCR6_BIT_MSTP60);
+
+    // Set control register
+    RTC.RCR2 = RCR2_VAL_ALLSTOP;
+    RTC.RCR1 = RCR1_VAL_ON;
+    RTC.RCR3 = RCR3_VAL;
+
+#ifdef USE_RTCX1_CLK
+    RTC.RCR5 = RCR5_VAL_RTCX1;
+    RTC.RFRH = 0;
+    RTC.RFRL = 0;
+#elif defined(USE_EXTAL_CLK)
+    RTC.RCR5 = RCR5_VAL_EXTAL;
+    RTC.RFRH = RFRH_VAL_13333;
+    RTC.RFRL = RFRL_VAL_13333;
+#else
+    RTC.RCR5 = RCR5_VAL_RTCX3;
+    RTC.RFRH = RFRH_VAL_4000;
+    RTC.RFRL = RFRL_VAL_4000;
+#endif
+    // Dummy read
+    dummy_read = RTC.RCR2;
+    dummy_read = RTC.RCR2;
+
+    RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1
+
+    // Dummy read
+    dummy_read = RTC.RCR2;
+    dummy_read = RTC.RCR2;
+
+    // Set timer and alarm. Default value :01-01-1970 00:00:00
+    RTC.RSECCNT = 0;
+    RTC.RMINCNT = 0;
+    RTC.RHRCNT  = 0;
+    RTC.RWKCNT  = 0;
+    RTC.RDAYCNT = 1;
+    RTC.RMONCNT = 1;
+    RTC.RYRCNT  = 0x1970;
+    RTC.RSECAR  = 0;
+    RTC.RMINAR  = 0;
+    RTC.RHRAR   = 0;
+    RTC.RWKAR   = 0;
+    RTC.RDAYAR  = 1;
+    RTC.RMONAR  = 1;
+    RTC.RYRAR   = 0x1970;
+
+    // Dummy read
+    dummy_read = RTC.RYRCNT;
+    dummy_read = RTC.RYRCNT;
+
+}
+
+
+/*
+ * Release the RTC based on a time structure.
+ * [in]
+ * None.
+ * [out]
+ * None.
+ */
+void rtc_free(void) {
+    volatile uint8_t dummy_read;
+
+    // Set control register
+    RTC.RCR2 = RCR2_VAL_ALLSTOP;
+    RTC.RCR1 = RCR1_VAL_OFF;
+    RTC.RCR3 = RCR3_VAL;
+    RTC.RCR5 = RCR5_VAL;
+    RTC.RFRH = RFRH_VAL_MAX;
+    RTC.RFRL = RFRL_VAL_MAX;
+
+    // Dummy read
+    dummy_read = RTC.RCR2;
+    dummy_read = RTC.RCR2;
+    RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1
+
+    // Dummy read
+    dummy_read = RTC.RCR2;
+    dummy_read = RTC.RCR2;
+
+    // Set timer and alarm. Default value :01-01-1970 00:00:00
+    RTC.RSECCNT = 0;
+    RTC.RMINCNT = 0;
+    RTC.RHRCNT  = 0;
+    RTC.RWKCNT  = 0;
+    RTC.RDAYCNT = 1;
+    RTC.RMONCNT = 1;
+    RTC.RYRCNT  = 0x1970;
+    RTC.RSECAR  = 0;
+    RTC.RMINAR  = 0;
+    RTC.RHRAR   = 0;
+    RTC.RWKAR   = 0;
+    RTC.RDAYAR  = 1;
+    RTC.RMONAR  = 1;
+    RTC.RYRAR   = 0x1970;
+
+    // Dummy read
+    dummy_read = RTC.RYRCNT;
+    dummy_read = RTC.RYRCNT;
+
+}
+
+
+/*
+ * Check the RTC has been enabled.
+ * Clock Control Register RTC.RCR1(bit3): 0 = Disabled, 1 = Enabled.
+ * [in]
+ * None.
+ * [out]
+ * 0:Disabled, 1:Enabled.
+ */
+int rtc_isenabled(void) {
+    int ret_val = 0;
+
+    if ((RTC.RCR1 & RCR1_VAL_ON) != 0) { // RTC ON ?
+        ret_val = 1;
+    }
+
+    return ret_val;
+}
+
+
+/*
+ * RTC read function.
+ * [in]
+ * None.
+ * [out]
+ * UNIX timestamp value.
+ */
+time_t rtc_read(void) {
+
+    struct tm timeinfo;
+    int    err = 0;
+    uint8_t tmp_regdata;
+    time_t t;
+
+    if (rtc_isenabled() != 0) {
+        RTC.RCR1 &= ~0x10u; // CIE = 0
+        do {
+            // before reading process
+            tmp_regdata  = RTC.RCR1;
+            tmp_regdata &= ~0x80u; // CF = 0
+            tmp_regdata |= 0x01u;  // AF = 1
+            RTC.RCR1 = tmp_regdata;
+
+            // Read RTC register
+            err  = rtc_dec8_to_hex(RTC.RSECCNT , 0    , &timeinfo.tm_sec);
+            err += rtc_dec8_to_hex(RTC.RMINCNT , 0    , &timeinfo.tm_min);
+            err += rtc_dec8_to_hex(RTC.RHRCNT  , 0    , &timeinfo.tm_hour);
+            err += rtc_dec8_to_hex(RTC.RDAYCNT , 0    , &timeinfo.tm_mday);
+            err += rtc_dec8_to_hex(RTC.RMONCNT , 1    , &timeinfo.tm_mon);
+            err += rtc_dec16_to_hex(RTC.RYRCNT , 1900 , &timeinfo.tm_year);
+        } while ((RTC.RCR1 & 0x80u) != 0);
+    } else {
+        err = 1;
+    }
+
+    if (err == 0) {
+        // Convert to timestamp
+        t = mktime(&timeinfo);
+    } else {
+        // Error
+        t = TIME_ERROR_VAL;
+    }
+
+    return t;
+}
+
+/*
+ * Dec(8bit) to Hex function for RTC.
+ * [in]
+ * dec_val:Decimal value (from 0x00 to 0x99).
+ * offset:Subtract offset from dec_val.
+ * hex_val:Pointer of output hexadecimal value.
+ * [out]
+ * 0:Success
+ * 1:Error
+ */
+static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val) {
+    int err = 0;
+    uint8_t ret_val;
+
+    if (hex_val != NULL) {
+        if (((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) ||
+            ((dec_val & MASK_00_03_POS) >=  0x0A)) {
+            err = 1;
+        } else {
+            ret_val = ((dec_val & MASK_04_07_POS) >> SHIFT_1_HBYTE) * 10 +
+                       (dec_val & MASK_00_03_POS);
+            if (ret_val < offset) {
+                err = 1;
+            } else {
+                *hex_val = ret_val - offset;
+            }
+        }
+    } else {
+        err = 1;
+    }
+
+    return err;
+}
+
+/*
+ * Dec(16bit) to Hex function for RTC
+ * [in]
+ * dec_val:Decimal value (from 0x0000 to 0x9999).
+ * offset:Subtract offset from dec_val.
+ * hex_val:Pointer of output hexadecimal value.
+ * [out]
+ * 0:Success
+ * 1:Error
+ */
+static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val) {
+    int err = 0;
+    uint16_t ret_val;
+
+    if (hex_val != NULL) {
+        if (((dec_val & MASK_12_15_POS) >= (0x0A << SHIFT_3_HBYTE)) ||
+            ((dec_val & MASK_08_11_POS) >= (0x0A << SHIFT_2_HBYTE)) ||
+            ((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) ||
+            ((dec_val & MASK_00_03_POS) >=  0x0A)) {
+            err = 1;
+            *hex_val = 0;
+        } else {
+            ret_val = (((dec_val & MASK_12_15_POS)) >> SHIFT_3_HBYTE) * 1000 +
+                      (((dec_val & MASK_08_11_POS)) >> SHIFT_2_HBYTE) * 100 +
+                      (((dec_val & MASK_04_07_POS)) >> SHIFT_1_HBYTE) * 10 +
+                        (dec_val & MASK_00_03_POS);
+            if (ret_val < offset) {
+                err = 1;
+            } else {
+                *hex_val = ret_val - offset;
+            }
+        }
+    } else {
+        err = 1;
+    }
+    return err;
+}
+
+/*
+ * RTC write function
+ * [in]
+ * t:UNIX timestamp value
+ * [out]
+ * None.
+ */
+void rtc_write(time_t t) {
+
+    struct tm *timeinfo = localtime(&t);
+    volatile uint16_t dummy_read;
+
+    if (rtc_isenabled() != 0) {
+        RTC.RCR2    = RCR2_VAL_ALLSTOP;
+        dummy_read  = (uint16_t)RTC.RCR2;
+        dummy_read  = (uint16_t)RTC.RCR2;
+        RTC.RCR2    = RCR2_VAL_RESET; // RESET = 1
+        dummy_read  = (uint16_t)RTC.RCR2;
+        dummy_read  = (uint16_t)RTC.RCR2;
+
+        RTC.RSECCNT = rtc_hex8_to_dec(timeinfo->tm_sec);
+        RTC.RMINCNT = rtc_hex8_to_dec(timeinfo->tm_min);
+        RTC.RHRCNT  = rtc_hex8_to_dec(timeinfo->tm_hour);
+        RTC.RDAYCNT = rtc_hex8_to_dec(timeinfo->tm_mday);
+        RTC.RMONCNT = rtc_hex8_to_dec(timeinfo->tm_mon + 1);
+        RTC.RYRCNT  = rtc_hex16_to_dec(timeinfo->tm_year + 1900);
+        dummy_read  = (uint16_t)RTC.RYRCNT;
+        dummy_read  = (uint16_t)RTC.RYRCNT;
+
+        RTC.RCR2    = RCR2_VAL_START; // START = 1
+
+        dummy_read  = (uint16_t)RTC.RCR2;
+        dummy_read  = (uint16_t)RTC.RCR2;
+    }
+}
+
+/*
+ * HEX to Dec(8bit) function for RTC.
+ * [in]
+ * hex_val:Hexadecimal value.
+ * [out]
+ * decimal value:From 0x00 to 0x99.
+ */
+static uint8_t rtc_hex8_to_dec(uint8_t hex_val) {
+    uint32_t calc_data;
+
+    calc_data  = hex_val / 10 * 0x10;
+    calc_data += hex_val % 10;
+
+    if (calc_data > 0x99) {
+        calc_data = 0;
+    }
+
+    return (uint8_t)calc_data;
+}
+
+/*
+ * HEX to Dec(16bit) function for RTC.
+ * [in]
+ * hex_val:Hexadecimal value.
+ * [out]
+ * decimal value:From 0x0000 to 0x9999.
+ */
+static uint16_t rtc_hex16_to_dec(uint16_t hex_val) {
+    uint32_t calc_data;
+    calc_data  =   hex_val / 1000       * 0x1000;
+    calc_data += ((hex_val / 100) % 10) * 0x100;
+    calc_data += ((hex_val / 10)  % 10) * 0x10;
+    calc_data +=   hex_val        % 10;
+
+    if (calc_data > 0x9999) {
+        calc_data = 0;
+    }
+    return (uint16_t)calc_data;
+
+}
+
+#endif /* DEVICE_RTC */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/serial_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,733 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include "mbed_assert.h"
+#include <math.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+#include "scif_iodefine.h"
+#include "cpg_iodefine.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+#define PCLK (66666666)     // Define the peripheral clock P1 frequency.
+
+#define UART_NUM    8
+#define IRQ_NUM     2
+
+static void uart0_tx_irq(void);
+static void uart1_tx_irq(void);
+static void uart2_tx_irq(void);
+static void uart3_tx_irq(void);
+static void uart4_tx_irq(void);
+static void uart5_tx_irq(void);
+static void uart6_tx_irq(void);
+static void uart7_tx_irq(void);
+static void uart0_rx_irq(void);
+static void uart1_rx_irq(void);
+static void uart2_rx_irq(void);
+static void uart3_rx_irq(void);
+static void uart4_rx_irq(void);
+static void uart5_rx_irq(void);
+static void uart6_rx_irq(void);
+static void uart7_rx_irq(void);
+
+#ifdef MAX_PERI
+static const PinMap PinMap_UART_TX[] = {
+    {P2_14 , UART0, 6},
+    {P4_9  , UART0, 7},
+    {P6_9  , UART0, 5},
+    {P2_5  , UART1, 6},
+    {P4_12 , UART1, 7},
+    {P6_12 , UART1, 5},
+    {P9_3  , UART1, 4},
+    {P3_0  , UART2, 6},
+    {P3_1  , UART2, 4},
+    {P4_2  , UART2, 5},
+    {P4_14 , UART2, 7},
+    {P6_3  , UART2, 7},
+    {P8_6  , UART2, 7},
+    {P3_5  , UART3, 7},
+    {P5_3  , UART3, 5},
+    {P6_1  , UART3, 7},
+    {P8_8  , UART3, 7},
+    {P5_0  , UART4, 5},
+    {P7_1  , UART4, 4},
+    {P8_14 , UART4, 7},
+    {P6_6  , UART5, 5},
+    {P8_1  , UART5, 4},
+    {P8_13 , UART5, 5},
+    {P5_6  , UART6, 5},
+    {P6_14 , UART6, 4},
+    {P7_4  , UART7, 4},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+    {P2_15 , UART0, 6},
+    {P4_10 , UART0, 7},
+    {P6_10 , UART0, 5},
+    {P2_6  , UART1, 6},
+    {P4_13 , UART1, 7},
+    {P6_13 , UART1, 5},
+    {P9_4  , UART1, 4},
+    {P3_2  , UART2, 4},
+    {P4_3  , UART2, 5},
+    {P4_15 , UART2, 7},
+    {P6_2  , UART2, 7},
+    {P8_4  , UART2, 7},
+    {P3_6  , UART3, 7},
+    {P5_4  , UART3, 5},
+    {P6_0  , UART3, 7},
+    {P8_9  , UART3, 7},
+    {P5_1  , UART4, 5},
+    {P7_2  , UART4, 4},
+    {P8_15 , UART4, 7},
+    {P6_7  , UART5, 5},
+    {P8_2  , UART5, 4},
+    {P8_11 , UART5, 5},
+    {P5_7  , UART6, 5},
+    {P6_15 , UART6, 4},
+    {P7_5  , UART7, 4},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_UART_CTS[] = {
+    {P2_3  , UART1, 6},
+    {P9_5  , UART1, 4},
+    {P6_3  , UART5, 5},
+    {P7_15 , UART5, 4},
+    {P7_6  , UART7, 4},
+    {NC    , NC   , 0}
+};
+static const PinMap PinMap_UART_RTS[] = {
+    {P2_7  , UART1, 6},
+    {P9_6  , UART1, 4},
+    {P6_4  , UART5, 5},
+    {P8_3  , UART5, 4},
+    {P7_7  , UART7, 4},
+    {NC    , NC   , 0}
+};
+#else
+static const PinMap PinMap_UART_TX[] = {
+    {P3_0  , UART2, 6},
+    {P3_1  , UART2, 4},
+    {P4_2  , UART2, 5},
+    {P5_3  , UART3, 5},
+    {P8_8  , UART3, 7},
+    {P5_0  , UART4, 5},
+    {P8_14 , UART4, 7},
+    {P8_13 , UART5, 5},
+    {P5_6  , UART6, 5},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+    {P3_2  , UART2, 4},
+    {P4_3  , UART2, 5},
+    {P5_4  , UART3, 5},
+    {P8_9  , UART3, 7},
+    {P5_1  , UART4, 5},
+    {P8_15 , UART4, 7},
+    {P8_11 , UART5, 5},
+    {P5_7  , UART6, 5},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_UART_CTS[] = {
+    {NC    , NC   , 0}
+};
+static const PinMap PinMap_UART_RTS[] = {
+    {NC    , NC   , 0}
+};
+#endif
+
+static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST;
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+struct serial_global_data_s {
+    uint32_t serial_irq_id;
+    gpio_t sw_rts, sw_cts;
+    uint8_t count, rx_irq_set_flow, rx_irq_set_api;
+};
+
+static struct serial_global_data_s uart_data[UART_NUM];
+
+static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
+    {SCIFRXI0_IRQn, SCIFTXI0_IRQn},
+    {SCIFRXI1_IRQn, SCIFTXI1_IRQn},
+    {SCIFRXI2_IRQn, SCIFTXI2_IRQn},
+    {SCIFRXI3_IRQn, SCIFTXI3_IRQn},
+    {SCIFRXI4_IRQn, SCIFTXI4_IRQn},
+    {SCIFRXI5_IRQn, SCIFTXI5_IRQn},
+    {SCIFRXI6_IRQn, SCIFTXI6_IRQn},
+    {SCIFRXI7_IRQn, SCIFTXI7_IRQn}
+};
+
+static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
+    {uart0_rx_irq, uart0_tx_irq},
+    {uart1_rx_irq, uart1_tx_irq},
+    {uart2_rx_irq, uart2_tx_irq},
+    {uart3_rx_irq, uart3_tx_irq},
+    {uart4_rx_irq, uart4_tx_irq},
+    {uart5_rx_irq, uart5_tx_irq},
+    {uart6_rx_irq, uart6_tx_irq},
+    {uart7_rx_irq, uart7_tx_irq}
+};
+
+static __IO uint16_t *SCSCR_MATCH[] = {
+    &SCSCR_0,
+    &SCSCR_1,
+    &SCSCR_2,
+    &SCSCR_3,
+    &SCSCR_4,
+    &SCSCR_5,
+    &SCSCR_6,
+    &SCSCR_7,
+};
+
+static __IO uint16_t *SCFSR_MATCH[] = {
+    &SCFSR_0,
+    &SCFSR_1,
+    &SCFSR_2,
+    &SCFSR_3,
+    &SCFSR_4,
+    &SCFSR_5,
+    &SCFSR_6,
+    &SCFSR_7,
+};
+
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    volatile uint8_t dummy ;
+    int is_stdio_uart = 0;
+    // determine the UART to use
+    uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
+    uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
+    uint32_t uart = pinmap_merge(uart_tx, uart_rx);
+
+    MBED_ASSERT((int)uart != NC);
+
+    obj->uart = (struct st_scif *)SCIF[uart];
+    // enable power
+    switch (uart) {
+    case UART0:
+        CPG.STBCR4 &= ~(1 <<  7);
+        break;
+    case UART1:
+        CPG.STBCR4 &= ~(1 <<  6);
+        break;
+    case UART2:
+        CPG.STBCR4 &= ~(1 <<  5);
+        break;
+    case UART3:
+        CPG.STBCR4 &= ~(1 <<  4);
+        break;
+    case UART4:
+        CPG.STBCR4 &= ~(1 <<  3);
+        break;
+    case UART5:
+        CPG.STBCR4 &= ~(1 <<  2);
+        break;
+    case UART6:
+        CPG.STBCR4 &= ~(1 <<  1);
+        break;
+    case UART7:
+        CPG.STBCR4 &= ~(1 <<  0);
+        break;
+    }
+    dummy = CPG.STBCR4;
+
+    /* if this uart has been previously configured to tx, wait tx completion befor loading new configuration */
+    if(obj->uart->SCSCR & 0xA0)
+	while(!(obj->uart->SCFSR & 0x0040));
+	
+    /* ==== SCIF initial setting ==== */
+    /* ---- Serial control register (SCSCR) setting ---- */
+    /* B'00 : Internal CLK */
+    obj->uart->SCSCR = 0x0000u;          /* SCIF transmitting and receiving operations stop */
+
+    /* ---- FIFO control register (SCFCR) setting ---- */
+    /* Transmit FIFO reset & Receive FIFO data register reset */
+    obj->uart->SCFCR = 0x0006;
+
+    /* ---- Serial status register (SCFSR) setting ---- */
+    dummy = obj->uart->SCFSR;
+    obj->uart->SCFSR = (dummy & 0xFF6Cu);         /* ER,BRK,DR bit clear */
+
+    /* ---- Line status register (SCLSR) setting ---- */
+    /* ORER bit clear */
+    obj->uart->SCLSR = 0;
+
+    /* ---- Serial extension mode register (SCEMR) setting ----
+    b7 BGDM - Baud rate generator double-speed mode  : Normal mode
+    b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */
+    obj->uart->SCEMR = 0x0000u;
+
+    /* ---- Bit rate register (SCBRR) setting ---- */
+    serial_baud  (obj, 9600);
+    serial_format(obj, 8, ParityNone, 1);
+
+    /* ---- FIFO control register (SCFCR) setting ---- */
+    obj->uart->SCFCR = 0x0030u;
+
+    /* ---- Serial port register (SCSPTR) setting ----
+    b1 SPB2IO - Serial port break output : disabled
+    b0 SPB2DT - Serial port break data   : High-level */
+    obj->uart->SCSPTR = 0x0003u;    // SPB2IO = 1, SPB2DT = 1
+
+    /* ---- Line status register (SCLSR) setting ----
+    b0 ORER - Overrun error detect : clear */
+
+    if (obj->uart->SCLSR & 0x0001) {
+        obj->uart->SCLSR = 0u;      // ORER clear
+    }
+
+    // pinout the chosen uart
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+
+    switch (uart) {
+    case UART0:
+        obj->index = 0;
+        break;
+    case UART1:
+        obj->index = 1;
+        break;
+    case UART2:
+        obj->index = 2;
+        break;
+    case UART3:
+        obj->index = 3;
+        break;
+    case UART4:
+        obj->index = 4;
+        break;
+    case UART5:
+        obj->index = 5;
+        break;
+    case UART6:
+        obj->index = 6;
+        break;
+    case UART7:
+        obj->index = 7;
+        break;
+    }
+    uart_data[obj->index].sw_rts.pin = NC;
+    uart_data[obj->index].sw_cts.pin = NC;
+
+    /* ---- Serial control register (SCSCR) setting ---- */
+    /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */
+    obj->uart->SCSCR = (((uart_tx != (uint32_t)NC)? 0xA0 : 0) | ((uart_rx != (uint32_t)NC)? 0x50 : 0 )); //0x00F0;
+
+    is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
+
+    if (is_stdio_uart) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj) {
+    uart_data[obj->index].serial_irq_id = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+    uint16_t DL;
+
+    obj->uart->SCSMR &= ~0x0003;
+
+    if (baudrate > 32552) {
+        obj->uart->SCEMR = 0x0081;  // BGDM = 1, ABCS = 1
+        DL = PCLK / (8 * baudrate);
+        if (DL > 0) {
+            DL--;
+        }
+        obj->uart->SCBRR = (uint8_t)DL;
+    } else if (baudrate > 16276) {
+        obj->uart->SCEMR = 0x0080;  // BGDM = 1
+        obj->uart->SCBRR = PCLK / (16 * baudrate) - 1;
+    } else if (baudrate > 8138) {
+        obj->uart->SCEMR = 0x0000;
+        obj->uart->SCBRR = PCLK / (32 * baudrate) - 1;
+    } else if (baudrate > 4169) {
+        obj->uart->SCSMR |= 0x0001;
+        obj->uart->SCEMR = 0x0080;  // BGDM = 1
+        obj->uart->SCBRR = PCLK / (64 * baudrate) - 1;
+    } else if (baudrate > 2034) {
+        obj->uart->SCSMR |= 0x0001;
+        obj->uart->SCEMR = 0x0000;
+        obj->uart->SCBRR = PCLK / (128 * baudrate) - 1;
+    } else if (baudrate > 1017) {
+        obj->uart->SCSMR |= 0x0002;
+        obj->uart->SCEMR = 0x0080;  // BGDM = 1
+        obj->uart->SCBRR = PCLK / (256 * baudrate) - 1;
+    } else if (baudrate > 508) {
+        obj->uart->SCSMR |= 0x0002;
+        obj->uart->SCEMR = 0x0000;
+        obj->uart->SCBRR = PCLK / (512 * baudrate) - 1;
+    } else if (baudrate > 254) {
+        obj->uart->SCSMR |= 0x0003;
+        obj->uart->SCEMR = 0x0080;  // BGDM = 1
+        obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1;
+    } else if (baudrate > 127) {
+        obj->uart->SCSMR |= 0x0003;
+        obj->uart->SCEMR = 0x0000;
+        obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1;
+    } else {
+        obj->uart->SCSMR |= 0x0003;
+        obj->uart->SCEMR = 0x0000;
+        obj->uart->SCBRR = 0xFFu;
+    }
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+    int parity_enable;
+    int parity_select;
+
+    MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
+    MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits
+    MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
+                (parity == ParityForced1) || (parity == ParityForced0));
+
+    stop_bits = (stop_bits == 1)? 0:
+                (stop_bits == 2)? 1:
+                0; // must not to be
+
+    data_bits = (data_bits == 8)? 0:
+                (data_bits == 7)? 1:
+                0; // must not to be
+
+    switch (parity) {
+    case ParityNone:
+        parity_enable = 0;
+        parity_select = 0;
+        break;
+    case ParityOdd:
+        parity_enable = 1;
+        parity_select = 1;
+        break;
+    case ParityEven:
+        parity_enable = 1;
+        parity_select = 0;
+        break;
+    case ParityForced1:
+    case ParityForced0:
+    default:
+        parity_enable = 0;
+        parity_select = 0;
+        break;
+    }
+
+    obj->uart->SCSMR = data_bits          << 6
+                       | parity_enable    << 5
+                       | parity_select    << 4
+                       | stop_bits        << 3;
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+
+static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
+    __IO uint16_t *dmy_rd_scscr;
+    __IO uint16_t *dmy_rd_scfsr;
+
+    dmy_rd_scscr = SCSCR_MATCH[index];
+    *dmy_rd_scscr &= 0x007B;                    // Clear TIE and Write to bit15~8,2 is always 0
+    dmy_rd_scfsr = SCFSR_MATCH[index];
+    *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020);  // Clear TDFE
+
+    irq_handler(uart_data[index].serial_irq_id, TxIrq);
+}
+
+static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
+    __IO uint16_t *dmy_rd_scscr;
+    __IO uint16_t *dmy_rd_scfsr;
+
+    dmy_rd_scscr = SCSCR_MATCH[index];
+    *dmy_rd_scscr &= 0x00B3;                    // Clear RIE,REIE and Write to bit15~8,2 is always 0
+    dmy_rd_scfsr = SCFSR_MATCH[index];
+    *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003);  // Clear RDF,DR
+
+    irq_handler(uart_data[index].serial_irq_id, RxIrq);
+}
+
+/* TX handler */
+static void uart0_tx_irq(void)  {
+    uart_tx_irq(SCIFTXI0_IRQn, 0);
+}
+static void uart1_tx_irq(void)  {
+    uart_tx_irq(SCIFTXI1_IRQn, 1);
+}
+static void uart2_tx_irq(void)  {
+    uart_tx_irq(SCIFTXI2_IRQn, 2);
+}
+static void uart3_tx_irq(void)  {
+    uart_tx_irq(SCIFTXI3_IRQn, 3);
+}
+static void uart4_tx_irq(void)  {
+    uart_tx_irq(SCIFTXI4_IRQn, 4);
+}
+static void uart5_tx_irq(void)  {
+    uart_tx_irq(SCIFTXI5_IRQn, 5);
+}
+static void uart6_tx_irq(void)  {
+    uart_tx_irq(SCIFTXI6_IRQn, 6);
+}
+static void uart7_tx_irq(void)  {
+    uart_tx_irq(SCIFTXI7_IRQn, 7);
+}
+/* RX handler */
+static void uart0_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI0_IRQn, 0);
+}
+static void uart1_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI1_IRQn, 1);
+}
+static void uart2_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI2_IRQn, 2);
+}
+static void uart3_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI3_IRQn, 3);
+}
+static void uart4_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI4_IRQn, 4);
+}
+static void uart5_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI5_IRQn, 5);
+}
+static void uart6_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI6_IRQn, 6);
+}
+static void uart7_rx_irq(void)  {
+    uart_rx_irq(SCIFRXI7_IRQn, 7);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+    irq_handler = handler;
+    uart_data[obj->index].serial_irq_id = id;
+}
+
+static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    IRQn_Type IRQn;
+    IRQHandler handler;
+
+    IRQn = irq_set_tbl[obj->index][irq];
+    handler = hander_set_tbl[obj->index][irq];
+
+    if ((obj->index >= 0) && (obj->index <= 7)) {
+        if (enable) {
+            InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
+            GIC_SetPriority(IRQn, 5);
+            GIC_EnableIRQ(IRQn);
+        } else {
+            GIC_DisableIRQ(IRQn);
+        }
+    }
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+    if (RxIrq == irq) {
+        uart_data[obj->index].rx_irq_set_api = enable;
+    }
+    serial_irq_set_internal(obj, irq, enable);
+}
+
+static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
+    uart_data[obj->index].rx_irq_set_flow = enable;
+    serial_irq_set_internal(obj, RxIrq, enable);
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+    uint16_t err_read;
+    int data;
+    int was_masked;
+
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+    if (obj->uart->SCFSR & 0x93) {
+        err_read = obj->uart->SCFSR;
+        obj->uart->SCFSR = (err_read & ~0x93);
+    }
+    obj->uart->SCSCR |= 0x0040;     // Set RIE
+    if (!was_masked) {
+        __enable_irq();
+    }
+
+    if (obj->uart->SCLSR & 0x0001) {
+        obj->uart->SCLSR = 0u;      // ORER clear
+    }
+
+    while (!serial_readable(obj));
+    data = obj->uart->SCFRDR & 0xff;
+
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+    err_read = obj->uart->SCFSR;
+    obj->uart->SCFSR = (err_read & 0xfffD);     // Clear RDF
+    if (!was_masked) {
+        __enable_irq();
+    }
+
+    if (err_read & 0x80) {
+        data = -1;  //err
+    }
+    return data;
+}
+
+void serial_putc(serial_t *obj, int c) {
+    uint16_t dummy_read;
+    int was_masked;
+
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+    obj->uart->SCSCR |= 0x0080;     // Set TIE
+    if (!was_masked) {
+        __enable_irq();
+    }
+    while (!serial_writable(obj));
+    obj->uart->SCFTDR = c;
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+    dummy_read = obj->uart->SCFSR;
+    obj->uart->SCFSR = (dummy_read & 0xff9f);  // Clear TEND/TDFE
+    if (!was_masked) {
+        __enable_irq();
+    }
+    uart_data[obj->index].count++;
+}
+
+int serial_readable(serial_t *obj) {
+    return ((obj->uart->SCFSR & 0x02) != 0);  // RDF
+}
+
+int serial_writable(serial_t *obj) {
+    return ((obj->uart->SCFSR & 0x20) != 0);  // TDFE
+}
+
+void serial_clear(serial_t *obj) {
+    int was_masked;
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+
+    obj->uart->SCFCR |=  0x06;          // TFRST = 1, RFRST = 1
+    obj->uart->SCFCR &= ~0x06;          // TFRST = 0, RFRST = 0
+    obj->uart->SCFSR &= ~0x0093u;       // ER, BRK, RDF, DR = 0
+
+    if (!was_masked) {
+        __enable_irq();
+    }
+}
+
+void serial_pinout_tx(PinName tx) {
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj) {
+    int was_masked;
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+    // TxD Output(L)
+    obj->uart->SCSPTR &= ~0x0001u;  // SPB2DT = 0
+    obj->uart->SCSCR &= ~0x0020u;   // TE = 0 (Output disable)
+    if (!was_masked) {
+        __enable_irq();
+    }
+}
+
+void serial_break_clear(serial_t *obj) {
+    int was_masked;
+#if defined ( __ICCARM__ )
+    was_masked = __disable_irq_iar();
+#else
+    was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+    obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
+    obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1
+    if (!was_masked) {
+        __enable_irq();
+    }
+}
+
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
+    // determine the UART to use
+    int was_masked;
+
+    serial_flow_irq_set(obj, 0);
+
+    if (type == FlowControlRTSCTS) {
+#if defined ( __ICCARM__ )
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+        obj->uart->SCFCR = 0x0008u;   // CTS/RTS enable
+        if (!was_masked) {
+            __enable_irq();
+        }
+        pinmap_pinout(rxflow, PinMap_UART_RTS);
+        pinmap_pinout(txflow, PinMap_UART_CTS);
+    } else {
+#if defined ( __ICCARM__ )
+        was_masked = __disable_irq_iar();
+#else
+        was_masked = __disable_irq();
+#endif /* __ICCARM__ */
+        obj->uart->SCFCR = 0x0000u; // CTS/RTS diable
+        if (!was_masked) {
+            __enable_irq();
+        }
+    }
+}
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/spi_api.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,329 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include <math.h>
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "RZ_A1_Init.h"
+
+
+#ifdef MAX_PERI
+static const PinMap PinMap_SPI_SCLK[] = {
+    {P2_12 , SPI_0, 2},
+    {P7_15 , SPI_0, 2},
+    {P4_4  , SPI_1, 2},
+    {P6_4  , SPI_1, 7},
+    {P8_3  , SPI_2, 3},
+    {P8_14 , SPI_2, 5},
+    {P3_0  , SPI_3, 8},
+    {P5_0  , SPI_3, 8},
+    {P2_8  , SPI_4, 8},
+    {P4_0  , SPI_4, 7},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {P2_13 , SPI_0, 2},
+    {P8_0  , SPI_0, 2},
+    {P4_5  , SPI_1, 2},
+    {P6_5  , SPI_1, 7},
+    {P8_4  , SPI_2, 3},
+    {P8_15 , SPI_2, 5},
+    {P3_1  , SPI_3, 8},
+    {P5_1  , SPI_3, 8},
+    {P2_9  , SPI_4, 8},
+    {P4_1  , SPI_4, 7},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {P2_14 , SPI_0, 2},
+    {P8_1  , SPI_0, 2},
+    {P4_6  , SPI_1, 2},
+    {P6_6  , SPI_1, 7},
+    {P8_5  , SPI_2, 3},
+    {P9_0  , SPI_2, 5},
+    {P3_2  , SPI_3, 8},
+    {P5_2  , SPI_3, 8},
+    {P2_10 , SPI_4, 8},
+    {P4_2  , SPI_4, 7},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {P2_15 , SPI_0, 2},
+    {P8_2  , SPI_0, 2},
+    {P4_7  , SPI_1, 2},
+    {P6_7  , SPI_1, 7},
+    {P8_6  , SPI_2, 3},
+    {P9_1  , SPI_2, 5},
+    {P3_3  , SPI_3, 8},
+    {P5_3  , SPI_3, 8},
+    {P2_11 , SPI_4, 8},
+    {P4_3  , SPI_4, 7},
+    {NC    , NC   , 0}
+};
+#else
+static const PinMap PinMap_SPI_SCLK[] = {
+    {P4_4  , SPI_1, 2},
+    {P8_14 , SPI_2, 5},
+    {P5_0  , SPI_3, 8},
+    {P4_0  , SPI_4, 7},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {P4_5  , SPI_1, 2},
+    {P8_15 , SPI_2, 5},
+    {P5_1  , SPI_3, 8},
+    {P4_1  , SPI_4, 7},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {P4_6  , SPI_1, 2},
+    {P9_0  , SPI_2, 5},
+    {P5_2  , SPI_3, 8},
+    {P4_2  , SPI_4, 7},
+    {NC    , NC   , 0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {P4_7  , SPI_1, 2},
+    {P9_1  , SPI_2, 5},
+    {P5_3  , SPI_3, 8},
+    {P4_3  , SPI_4, 7},
+    {NC    , NC   , 0}
+};
+#endif
+
+
+static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
+
+static inline void spi_disable(spi_t *obj);
+static inline void spi_enable(spi_t *obj);
+static inline int spi_readable(spi_t *obj);
+static inline void spi_write(spi_t *obj, int value);
+static inline int spi_read(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    // determine the SPI to use
+    volatile uint8_t dummy;
+    uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+    uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+    uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+    uint32_t spi      = pinmap_merge(spi_data, spi_cntl);
+
+    MBED_ASSERT((int)spi != NC);
+
+    obj->spi = (struct st_rspi *)RSPI[spi];
+
+    // enable power and clocking
+    switch (spi) {
+        case SPI_1: CPGSTBCR10 &= ~(0x40); break;
+        case SPI_2: CPGSTBCR10 &= ~(0x20); break;
+        case SPI_3: CPGSTBCR10 &= ~(0x10); break;
+        case SPI_4: CPGSTBCR10 &= ~(0x08); break;
+    }
+    dummy = CPGSTBCR10;
+
+    obj->spi->SPCR   = 0x00;  // CTRL to 0
+    obj->spi->SPSCR  = 0x00;  // no sequential operation
+    obj->spi->SSLP   = 0x00;  // SSL 'L' active 
+    obj->spi->SPDCR  = 0x20;  // byte access
+    obj->spi->SPCKD  = 0x00;  // SSL -> enable CLK delay : 1RSPCK
+    obj->spi->SSLND  = 0x00;  // CLK end -> SSL neg delay : 1RSPCK
+    obj->spi->SPND   = 0x00;  // delay between CMD : 1RSPCK + 2P1CLK
+    obj->spi->SPPCR  = 0x20;  // MOSI Idle fixed value equals 0
+    obj->spi->SPBFCR = 0xf0;  // and set trigger count: read 1, write 1
+    obj->spi->SPBFCR = 0x30;  // and reset buffer
+
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if ((int)ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+    int      DSS;      // DSS (data select size)
+    int      polarity  = (mode & 0x2) ? 1 : 0;
+    int      phase     = (mode & 0x1) ? 1 : 0;
+    uint16_t tmp       = 0;
+    uint16_t mask      = 0xf03;
+    uint16_t wk_spcmd0;
+    uint8_t  splw;
+
+    switch (mode) {
+        case 0:
+        case 1:
+        case 2:
+        case 3:
+            // Do Nothing
+            break;
+        default:
+            error("SPI format error");
+            return;
+    }
+
+    switch (bits) {
+        case 8:
+            DSS  = 0x7;
+            splw = 0x20;
+            break;
+        case 16:
+            DSS  = 0xf;
+            splw = 0x40;
+            break;
+        case 32:
+            DSS  = 0x2;
+            splw = 0x60;
+            break;
+        default:
+            error("SPI module don't support other than 8/16/32bits");
+            return;
+    }
+    tmp |= phase;
+    tmp |= (polarity << 1);
+    tmp |= (DSS << 8);
+    obj->bits = bits;
+
+    spi_disable(obj);
+    wk_spcmd0 = obj->spi->SPCMD0;
+    wk_spcmd0 &= ~mask;
+    wk_spcmd0 |= (mask & tmp);
+    obj->spi->SPCMD0 = wk_spcmd0;
+    obj->spi->SPDCR   = splw;
+    if (slave) {
+        obj->spi->SPCR &=~(1 << 3);  // MSTR to 0
+    } else {
+        obj->spi->SPCR |= (1 << 3);  // MSTR to 1
+    }
+    spi_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    uint32_t  pclk_base;
+    uint32_t  div;
+    uint32_t  brdv = 0;
+    uint32_t  hz_max;
+    uint32_t  hz_min;
+    uint16_t  mask = 0x000c;
+    uint16_t  wk_spcmd0;
+
+    /* set PCLK */
+    if (RZ_A1_IsClockMode0() == false) {
+        pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
+    } else {
+        pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
+    }
+
+    hz_min = pclk_base / 2 / 256 / 8;
+    hz_max = pclk_base / 2;
+    if ((hz < hz_min) || (hz > hz_max)) {
+        error("Couldn't setup requested SPI frequency");
+        return;
+    }
+
+    div = (pclk_base / hz / 2);
+    while (div > 256) {
+        div >>= 1;
+        brdv++;
+    }
+    div  -= 1;
+    brdv  = (brdv << 2);
+
+    spi_disable(obj);
+    obj->spi->SPBR = div;
+    wk_spcmd0 = obj->spi->SPCMD0;
+    wk_spcmd0 &= ~mask;
+    wk_spcmd0 |= (mask & brdv);
+    obj->spi->SPCMD0 = wk_spcmd0;
+    spi_enable(obj);
+}
+
+static inline void spi_disable(spi_t *obj) {
+    obj->spi->SPCR &= ~(1 << 6);       // SPE to 0
+}
+
+static inline void spi_enable(spi_t *obj) {
+    obj->spi->SPCR |=  (1 << 6);       // SPE to 1
+}
+
+static inline int spi_readable(spi_t *obj) {
+    return obj->spi->SPSR & (1 << 7);  // SPRF
+}
+
+static inline int spi_tend(spi_t *obj) {
+    return obj->spi->SPSR & (1 << 6);  // TEND
+}
+
+static inline void spi_write(spi_t *obj, int value) {
+    if (obj->bits == 8) {
+        obj->spi->SPDR.UINT8[0]  = (uint8_t)value;
+    } else if (obj->bits == 16) {
+        obj->spi->SPDR.UINT16[0] = (uint16_t)value;
+    } else {
+        obj->spi->SPDR.UINT32    = (uint32_t)value;
+    }
+}
+
+static inline int spi_read(spi_t *obj) {
+    int read_data;
+
+    if (obj->bits == 8) {
+        read_data = obj->spi->SPDR.UINT8[0];
+    } else if (obj->bits == 16) {
+        read_data = obj->spi->SPDR.UINT16[0];
+    } else {
+        read_data = obj->spi->SPDR.UINT32;
+    }
+
+    return read_data;
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    spi_write(obj, value);
+    while(!spi_tend(obj));
+    return spi_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
+}
+
+int spi_slave_read(spi_t *obj) {
+    return spi_read(obj);
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    spi_write(obj, value);
+}
+
+int spi_busy(spi_t *obj) {
+    return 0;
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_VK_RZ_A1H/us_ticker.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,140 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+#include "ostm_iodefine.h"
+
+#include "RZ_A1_Init.h"
+#include "VKRZA1H.h"
+
+#define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn)
+#define CPG_STBCR5_BIT_MSTP50   (0x01u) /* OSTM1 */
+
+#define US_TICKER_CLOCK_US_DEV (1000000)
+
+int us_ticker_inited = 0;
+static double count_clock = 0;
+static uint32_t last_read = 0;
+static uint32_t wrap_arround = 0;
+static uint64_t ticker_us_last64 = 0;
+
+void us_ticker_interrupt(void) {
+    us_ticker_irq_handler();
+}
+
+void us_ticker_init(void) {
+    if (us_ticker_inited) return;
+    us_ticker_inited = 1;
+
+    /* set Counter Clock(us) */
+    if (false == RZ_A1_IsClockMode0()) {
+        count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
+    } else {
+        count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
+    }
+
+    /* Power Control for Peripherals      */
+    CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
+
+    // timer settings
+    OSTM1TT   = 0x01;    /* Stop the counter and clears the OSTM1TE bit.     */
+    OSTM1CTL  = 0x02;    /* Free running timer mode. Interrupt disabled when star counter  */
+
+    OSTM1TS   = 0x1;    /* Start the counter and sets the OSTM0TE bit.     */
+
+    // INTC settings
+    InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
+    GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
+    GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+static uint64_t ticker_read_counter64(void) {
+    uint32_t cnt_val;
+    uint64_t cnt_val64;
+
+    if (!us_ticker_inited)
+        us_ticker_init();
+
+    /* read counter */
+    cnt_val = OSTM1CNT;
+    if (last_read > cnt_val) {
+        wrap_arround++;
+    }
+    last_read = cnt_val;
+    cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val;
+
+    return cnt_val64;
+}
+
+uint32_t us_ticker_read() {
+    uint64_t cnt_val64;
+    uint64_t us_val64;
+    int check_irq_masked;
+
+#if defined ( __ICCARM__)
+    check_irq_masked = __disable_irq_iar();
+#else
+    check_irq_masked = __disable_irq();
+#endif /* __ICCARM__ */
+
+    cnt_val64        = ticker_read_counter64();
+    us_val64         = (cnt_val64 / count_clock);
+    ticker_us_last64 = us_val64;
+
+    if (!check_irq_masked) {
+        __enable_irq();
+    }
+
+    /* clock to us */
+    return (uint32_t)us_val64;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp) {
+    // set match value
+    uint64_t timestamp64;
+    uint64_t set_cmp_val64;
+    volatile uint32_t set_cmp_val;
+    uint64_t count_val_64;
+
+    /* calc compare mach timestamp */
+    timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp;
+    if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) {
+        /* This event is wrap arround */
+        timestamp64 += 0x100000000;
+    }
+
+    /* calc compare mach timestamp */
+    set_cmp_val64  = timestamp64 * count_clock;
+    set_cmp_val    = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF);
+    count_val_64   = ticker_read_counter64();
+    if (set_cmp_val64 <= (count_val_64 + 500)) {
+        GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
+        GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+        return;
+    }
+    OSTM1CMP = set_cmp_val;
+    GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+void us_ticker_disable_interrupt(void) {
+    GIC_DisableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+void us_ticker_clear_interrupt(void) {
+    GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn);
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/Mail.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,110 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MAIL_H
+#define MAIL_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/** The Mail class allow to control, send, receive, or wait for mail.
+ A mail is a memory block that is send to a thread or interrupt service routine.
+  @tparam  T         data type of a single message element.
+  @tparam  queue_sz  maximum number of messages in queue.
+*/
+template<typename T, uint32_t queue_sz>
+class Mail {
+public:
+    /** Create and Initialise Mail queue. */
+    Mail() {
+    #ifdef CMSIS_OS_RTX
+        memset(_mail_q, 0, sizeof(_mail_q));
+        _mail_p[0] = _mail_q;
+
+        memset(_mail_m, 0, sizeof(_mail_m));
+        _mail_p[1] = _mail_m;
+
+        _mail_def.pool = _mail_p;
+        _mail_def.queue_sz = queue_sz;
+        _mail_def.item_sz = sizeof(T);
+    #endif
+        _mail_id = osMailCreate(&_mail_def, NULL);
+    }
+
+    /** Allocate a memory block of type T
+      @param   millisec  timeout value or 0 in case of no time-out. (default: 0).
+      @return  pointer to memory block that can be filled with mail or NULL in case error.
+    */
+    T* alloc(uint32_t millisec=0) {
+        return (T*)osMailAlloc(_mail_id, millisec);
+    }
+
+    /** Allocate a memory block of type T and set memory block to zero.
+      @param   millisec  timeout value or 0 in case of no time-out.  (default: 0).
+      @return  pointer to memory block that can be filled with mail or NULL in case error.
+    */
+    T* calloc(uint32_t millisec=0) {
+        return (T*)osMailCAlloc(_mail_id, millisec);
+    }
+
+    /** Put a mail in the queue.
+      @param   mptr  memory block previously allocated with Mail::alloc or Mail::calloc.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus put(T *mptr) {
+        return osMailPut(_mail_id, (void*)mptr);
+    }
+
+    /** Get a mail from a queue.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  event that contains mail information or error code.
+    */
+    osEvent get(uint32_t millisec=osWaitForever) {
+        return osMailGet(_mail_id, millisec);
+    }
+
+    /** Free a memory block from a mail.
+      @param   mptr  pointer to the memory block that was obtained with Mail::get.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus free(T *mptr) {
+        return osMailFree(_mail_id, (void*)mptr);
+    }
+
+private:
+    osMailQId    _mail_id;
+    osMailQDef_t _mail_def;
+#ifdef CMSIS_OS_RTX
+    uint32_t     _mail_q[4+(queue_sz)];
+    uint32_t     _mail_m[3+((sizeof(T)+3)/4)*(queue_sz)];
+    void        *_mail_p[2];
+#endif
+};
+
+}
+
+#endif
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/MemoryPool.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,83 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MEMORYPOOL_H
+#define MEMORYPOOL_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/** Define and manage fixed-size memory pools of objects of a given type.
+  @tparam  T         data type of a single object (element).
+  @tparam  queue_sz  maximum number of objects (elements) in the memory pool.
+*/
+template<typename T, uint32_t pool_sz>
+class MemoryPool {
+public:
+    /** Create and Initialize a memory pool. */
+    MemoryPool() {
+    #ifdef CMSIS_OS_RTX
+        memset(_pool_m, 0, sizeof(_pool_m));
+        _pool_def.pool = _pool_m;
+
+        _pool_def.pool_sz = pool_sz;
+        _pool_def.item_sz =  sizeof(T);
+    #endif
+        _pool_id = osPoolCreate(&_pool_def);
+    }
+
+    /** Allocate a memory block of type T from a memory pool.
+      @return  address of the allocated memory block or NULL in case of no memory available.
+    */
+    T* alloc(void) {
+        return (T*)osPoolAlloc(_pool_id);
+    }
+
+    /** Allocate a memory block of type T from a memory pool and set memory block to zero.
+      @return  address of the allocated memory block or NULL in case of no memory available.
+    */
+    T* calloc(void) {
+        return (T*)osPoolCAlloc(_pool_id);
+    }
+
+    /** Return an allocated memory block back to a specific memory pool.
+      @param   address of the allocated memory block that is returned to the memory pool.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus free(T *block) {
+        return osPoolFree(_pool_id, (void*)block);
+    }
+
+private:
+    osPoolId    _pool_id;
+    osPoolDef_t _pool_def;
+#ifdef CMSIS_OS_RTX
+    uint32_t    _pool_m[3+((sizeof(T)+3)/4)*(pool_sz)];
+#endif
+};
+
+}
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/Mutex.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "Mutex.h"
+
+#include <string.h>
+#include "mbed_error.h"
+
+namespace rtos {
+
+Mutex::Mutex() {
+#ifdef CMSIS_OS_RTX
+    memset(_mutex_data, 0, sizeof(_mutex_data));
+    _osMutexDef.mutex = _mutex_data;
+#endif
+    _osMutexId = osMutexCreate(&_osMutexDef);
+    if (_osMutexId == NULL) {
+        error("Error initializing the mutex object\n");
+    }
+}
+
+osStatus Mutex::lock(uint32_t millisec) {
+    return osMutexWait(_osMutexId, millisec);
+}
+
+bool Mutex::trylock() {
+    return (osMutexWait(_osMutexId, 0) == osOK);
+}
+
+osStatus Mutex::unlock() {
+    return osMutexRelease(_osMutexId);
+}
+
+Mutex::~Mutex() {
+    osMutexDelete(_osMutexId);
+}
+
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/Mutex.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MUTEX_H
+#define MUTEX_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/** The Mutex class is used to synchronise the execution of threads.
+ This is for example used to protect access to a shared resource.
+*/
+class Mutex {
+public:
+    /** Create and Initialize a Mutex object */
+    Mutex();
+
+    /** Wait until a Mutex becomes available.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever)
+      @return  status code that indicates the execution status of the function.
+     */
+    osStatus lock(uint32_t millisec=osWaitForever);
+
+    /** Try to lock the mutex, and return immediately
+      @return  true if the mutex was acquired, false otherwise.
+     */
+    bool trylock();
+
+    /** Unlock the mutex that has previously been locked by the same thread
+      @return  status code that indicates the execution status of the function.
+     */
+    osStatus unlock();
+
+    ~Mutex();
+
+private:
+    osMutexId _osMutexId;
+    osMutexDef_t _osMutexDef;
+#ifdef CMSIS_OS_RTX
+#if defined(__MBED_CMSIS_RTOS_CA9) || defined(__MBED_CMSIS_RTOS_CM)
+    int32_t _mutex_data[4];
+#else
+    int32_t _mutex_data[3];
+#endif
+#endif
+};
+
+}
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/Queue.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+#include "mbed_error.h"
+
+namespace rtos {
+
+/** The Queue class allow to control, send, receive, or wait for messages.
+ A message can be a integer or pointer value  to a certain type T that is send
+ to a thread or interrupt service routine.
+  @tparam  T         data type of a single message element.
+  @tparam  queue_sz  maximum number of messages in queue.
+*/
+template<typename T, uint32_t queue_sz>
+class Queue {
+public:
+    /** Create and initialise a message Queue. */
+    Queue() {
+    #ifdef CMSIS_OS_RTX
+        memset(_queue_q, 0, sizeof(_queue_q));
+        _queue_def.pool = _queue_q;
+        _queue_def.queue_sz = queue_sz;
+    #endif
+        _queue_id = osMessageCreate(&_queue_def, NULL);
+        if (_queue_id == NULL) {
+            error("Error initialising the queue object\n");
+        }
+    }
+
+    /** Put a message in a Queue.
+      @param   data      message pointer.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: 0)
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus put(T* data, uint32_t millisec=0) {
+        return osMessagePut(_queue_id, (uint32_t)data, millisec);
+    }
+
+    /** Get a message or Wait for a message from a Queue.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  event information that includes the message and the status code.
+    */
+    osEvent get(uint32_t millisec=osWaitForever) {
+        return osMessageGet(_queue_id, millisec);
+    }
+
+private:
+    osMessageQId    _queue_id;
+    osMessageQDef_t _queue_def;
+#ifdef CMSIS_OS_RTX
+    uint32_t        _queue_q[4+(queue_sz)];
+#endif
+};
+
+}
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/RtosTimer.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "RtosTimer.h"
+
+#include <string.h>
+
+#include "mbed.h"
+#include "cmsis_os.h"
+#include "mbed_error.h"
+
+namespace rtos {
+
+void RtosTimer::constructor(mbed::Callback<void()> func, os_timer_type type) {
+#ifdef CMSIS_OS_RTX
+    _timer.ptimer = (void (*)(const void *))Callback<void()>::thunk;
+
+    memset(_timer_data, 0, sizeof(_timer_data));
+    _timer.timer = _timer_data;
+#endif
+    _function = func;
+    _timer_id = osTimerCreate(&_timer, type, &_function);
+}
+
+osStatus RtosTimer::start(uint32_t millisec) {
+    return osTimerStart(_timer_id, millisec);
+}
+
+osStatus RtosTimer::stop(void) {
+    return osTimerStop(_timer_id);
+}
+
+RtosTimer::~RtosTimer() {
+    osTimerDelete(_timer_id);
+}
+
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/RtosTimer.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,102 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef RTOS_TIMER_H
+#define RTOS_TIMER_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+#include "Callback.h"
+#include "toolchain.h"
+
+namespace rtos {
+
+/** The RtosTimer class allow creating and and controlling of timer functions in the system.
+ A timer function is called when a time period expires whereby both on-shot and
+ periodic timers are possible. A timer can be started, restarted, or stopped.
+
+ Timers are handled in the thread osTimerThread.
+ Callback functions run under control of this thread and may use CMSIS-RTOS API calls.
+*/
+class RtosTimer {
+public:
+    /** Create timer.
+      @param   func      function to be executed by this timer.
+      @param   type      osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic)
+      @param   argument  argument to the timer call back function. (default: NULL)
+      @deprecated Replaced with RtosTimer(Callback<void()>, os_timer_type)
+     */
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Replaced with RtosTimer(Callback<void()>, os_timer_type)")
+    RtosTimer(void (*func)(void const *argument), os_timer_type type=osTimerPeriodic, void *argument=NULL) {
+        constructor(mbed::Callback<void()>(argument, (void (*)(void *))func), type);
+    }
+    
+    /** Create timer.
+      @param   func      function to be executed by this timer.
+      @param   type      osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic)
+    */
+    RtosTimer(mbed::Callback<void()> func, os_timer_type type=osTimerPeriodic) {
+        constructor(func, type);
+    }
+    
+    /** Create timer.
+      @param   obj       pointer to the object to call the member function on.
+      @param   method    member function to be executed by this timer.
+      @param   type      osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic)
+    */
+    template <typename T, typename M>
+    RtosTimer(T *obj, M method, os_timer_type type=osTimerPeriodic) {
+        constructor(mbed::Callback<void()>(obj, method), type);
+    }
+
+    /** Stop the timer.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus stop(void);
+
+    /** Start the timer.
+      @param   millisec  time delay value of the timer.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus start(uint32_t millisec);
+
+    ~RtosTimer();
+
+private:
+    // Required to share definitions without
+    // delegated constructors
+    void constructor(mbed::Callback<void()> func, os_timer_type type);
+    
+    mbed::Callback<void()> _function;
+    osTimerId _timer_id;
+    osTimerDef_t _timer;
+#if defined(CMSIS_OS_RTX) && !defined(__MBED_CMSIS_RTOS_CM)
+    uint32_t _timer_data[5];
+#else
+    uint32_t _timer_data[6];
+#endif
+};
+
+}
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/Semaphore.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "Semaphore.h"
+
+#include <string.h>
+
+namespace rtos {
+
+Semaphore::Semaphore(int32_t count) {
+#ifdef CMSIS_OS_RTX
+    memset(_semaphore_data, 0, sizeof(_semaphore_data));
+    _osSemaphoreDef.semaphore = _semaphore_data;
+#endif
+    _osSemaphoreId = osSemaphoreCreate(&_osSemaphoreDef, count);
+}
+
+int32_t Semaphore::wait(uint32_t millisec) {
+    return osSemaphoreWait(_osSemaphoreId, millisec);
+}
+
+osStatus Semaphore::release(void) {
+    return osSemaphoreRelease(_osSemaphoreId);
+}
+
+Semaphore::~Semaphore() {
+    osSemaphoreDelete(_osSemaphoreId);
+}
+
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/Semaphore.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/** The Semaphore class is used to manage and protect access to a set of shared resources. */
+class Semaphore {
+public:
+    /** Create and Initialize a Semaphore object used for managing resources.
+      @param number of available resources; maximum index value is (count-1). (default: 0).
+    */
+    Semaphore(int32_t count=0);
+
+    /** Wait until a Semaphore resource becomes available.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  number of available tokens, or -1 in case of incorrect parameters
+    */
+    int32_t wait(uint32_t millisec=osWaitForever);
+
+    /** Release a Semaphore resource that was obtain with Semaphore::wait.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus release(void);
+
+    ~Semaphore();
+
+private:
+    osSemaphoreId _osSemaphoreId;
+    osSemaphoreDef_t _osSemaphoreDef;
+#ifdef CMSIS_OS_RTX
+    uint32_t _semaphore_data[2];
+#endif
+};
+
+}
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/Thread.cpp	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,349 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "Thread.h"
+
+#include "mbed.h"
+#include "rtos_idle.h"
+
+// rt_tid2ptcb is an internal function which we exposed to get TCB for thread id
+#undef NULL  //Workaround for conflicting macros in rt_TypeDef.h and stdio.h
+#include "rt_TypeDef.h"
+
+extern "C" P_TCB rt_tid2ptcb(osThreadId thread_id);
+
+namespace rtos {
+
+void Thread::constructor(osPriority priority,
+        uint32_t stack_size, unsigned char *stack_pointer) {
+    _tid = 0;
+    _dynamic_stack = (stack_pointer == NULL);
+
+#if defined(__MBED_CMSIS_RTOS_CA9) || defined(__MBED_CMSIS_RTOS_CM)
+    _thread_def.tpriority = priority;
+    _thread_def.stacksize = stack_size;
+    _thread_def.stack_pointer = (uint32_t*)stack_pointer;
+#endif
+}
+
+void Thread::constructor(Callback<void()> task,
+        osPriority priority, uint32_t stack_size, unsigned char *stack_pointer) {
+    constructor(priority, stack_size, stack_pointer);
+
+    switch (start(task)) {
+        case osErrorResource:
+            error("OS ran out of threads!\n");
+            break;
+        case osErrorParameter:
+            error("Thread already running!\n");
+            break;
+        case osErrorNoMemory:
+            error("Error allocating the stack memory\n");
+        default:
+            break;
+    }
+}
+
+osStatus Thread::start(Callback<void()> task) {
+    _mutex.lock();
+
+    if (_tid != 0) {
+        _mutex.unlock();
+        return osErrorParameter;
+    }
+
+#if defined(__MBED_CMSIS_RTOS_CA9) || defined(__MBED_CMSIS_RTOS_CM)
+    _thread_def.pthread = Thread::_thunk;
+    if (_thread_def.stack_pointer == NULL) {
+        _thread_def.stack_pointer = new uint32_t[_thread_def.stacksize/sizeof(uint32_t)];
+        if (_thread_def.stack_pointer == NULL) {
+            _mutex.unlock();
+            return osErrorNoMemory;
+        }
+    }
+
+    //Fill the stack with a magic word for maximum usage checking
+    for (uint32_t i = 0; i < (_thread_def.stacksize / sizeof(uint32_t)); i++) {
+        _thread_def.stack_pointer[i] = 0xE25A2EA5;
+    }
+#endif
+    _task = task;
+    _tid = osThreadCreate(&_thread_def, this);
+    if (_tid == NULL) {
+        if (_dynamic_stack) delete[] (_thread_def.stack_pointer);
+        _mutex.unlock();
+        return osErrorResource;
+    }
+
+    _mutex.unlock();
+    return osOK;
+}
+
+osStatus Thread::terminate() {
+    osStatus ret;
+    _mutex.lock();
+
+    ret = osThreadTerminate(_tid);
+    _tid = (osThreadId)NULL;
+
+    // Wake threads joining the terminated thread
+    _join_sem.release();
+
+    _mutex.unlock();
+    return ret;
+}
+
+osStatus Thread::join() {
+    int32_t ret = _join_sem.wait();
+    if (ret < 0) {
+        return osErrorOS;
+    }
+    // Release sem so any other threads joining this thread wake up
+    _join_sem.release();
+    return osOK;
+}
+
+osStatus Thread::set_priority(osPriority priority) {
+    osStatus ret;
+    _mutex.lock();
+
+    ret = osThreadSetPriority(_tid, priority);
+
+    _mutex.unlock();
+    return ret;
+}
+
+osPriority Thread::get_priority() {
+    osPriority ret;
+    _mutex.lock();
+
+    ret = osThreadGetPriority(_tid);
+
+    _mutex.unlock();
+    return ret;
+}
+
+int32_t Thread::signal_set(int32_t signals) {
+    // osSignalSet is thread safe as long as the underlying
+    // thread does not get terminated or return from main
+    return osSignalSet(_tid, signals);
+}
+
+int32_t Thread::signal_clr(int32_t signals) {
+    // osSignalClear is thread safe as long as the underlying
+    // thread does not get terminated or return from main
+    return osSignalClear(_tid, signals);
+}
+
+Thread::State Thread::get_state() {
+#if !defined(__MBED_CMSIS_RTOS_CA9) && !defined(__MBED_CMSIS_RTOS_CM)
+#ifdef CMSIS_OS_RTX
+    State status = Deleted;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+        status = (State)_thread_def.tcb.state;
+    }
+
+    _mutex.unlock();
+    return status;
+#endif
+#else
+    State status = Deleted;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+        status = (State)osThreadGetState(_tid);
+    }
+
+    _mutex.unlock();
+    return status;
+#endif
+}
+
+uint32_t Thread::stack_size() {
+#ifndef __MBED_CMSIS_RTOS_CA9
+#if defined(CMSIS_OS_RTX) && !defined(__MBED_CMSIS_RTOS_CM)
+    uint32_t size = 0;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+        size = _thread_def.tcb.priv_stack;
+    }
+
+    _mutex.unlock();
+    return size;
+#else
+    uint32_t size = 0;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+        P_TCB tcb = rt_tid2ptcb(_tid);
+        size = tcb->priv_stack;
+    }
+
+    _mutex.unlock();
+    return size;
+#endif
+#else
+    return 0;
+#endif
+}
+
+uint32_t Thread::free_stack() {
+#ifndef __MBED_CMSIS_RTOS_CA9
+#if defined(CMSIS_OS_RTX) && !defined(__MBED_CMSIS_RTOS_CM)
+    uint32_t size = 0;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+        uint32_t bottom = (uint32_t)_thread_def.tcb.stack;
+        size = _thread_def.tcb.tsk_stack - bottom;
+    }
+
+    _mutex.unlock();
+    return size;
+#else
+    uint32_t size = 0;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+        P_TCB tcb = rt_tid2ptcb(_tid);
+        uint32_t bottom = (uint32_t)tcb->stack;
+        size = tcb->tsk_stack - bottom;
+    }
+
+    _mutex.unlock();
+    return size;
+#endif
+#else
+    return 0;
+#endif
+}
+
+uint32_t Thread::used_stack() {
+#ifndef __MBED_CMSIS_RTOS_CA9
+#if defined(CMSIS_OS_RTX) && !defined(__MBED_CMSIS_RTOS_CM)
+    uint32_t size = 0;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+        uint32_t top = (uint32_t)_thread_def.tcb.stack + _thread_def.tcb.priv_stack;
+        size = top - _thread_def.tcb.tsk_stack;
+    }
+
+    _mutex.unlock();
+    return size;
+#else
+    uint32_t size = 0;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+        P_TCB tcb = rt_tid2ptcb(_tid);
+        uint32_t top = (uint32_t)tcb->stack + tcb->priv_stack;
+        size =  top - tcb->tsk_stack;
+    }
+
+    _mutex.unlock();
+    return size;
+#endif
+#else
+    return 0;
+#endif
+}
+
+uint32_t Thread::max_stack() {
+#ifndef __MBED_CMSIS_RTOS_CA9
+#if defined(CMSIS_OS_RTX) && !defined(__MBED_CMSIS_RTOS_CM)
+    uint32_t size = 0;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+        uint32_t high_mark = 0;
+        while (_thread_def.tcb.stack[high_mark] == 0xE25A2EA5)
+            high_mark++;
+        size = _thread_def.tcb.priv_stack - (high_mark * 4);
+    }
+
+    _mutex.unlock();
+    return size;
+#else
+    uint32_t size = 0;
+    _mutex.lock();
+
+    if (_tid != NULL) {
+        P_TCB tcb = rt_tid2ptcb(_tid);
+        uint32_t high_mark = 0;
+        while (tcb->stack[high_mark] == 0xE25A2EA5)
+            high_mark++;
+        size = tcb->priv_stack - (high_mark * 4);
+    }
+
+    _mutex.unlock();
+    return size;
+#endif
+#else
+    return 0;
+#endif
+}
+
+osEvent Thread::signal_wait(int32_t signals, uint32_t millisec) {
+    return osSignalWait(signals, millisec);
+}
+
+osStatus Thread::wait(uint32_t millisec) {
+    return osDelay(millisec);
+}
+
+osStatus Thread::yield() {
+    return osThreadYield();
+}
+
+osThreadId Thread::gettid() {
+    return osThreadGetId();
+}
+
+void Thread::attach_idle_hook(void (*fptr)(void)) {
+    rtos_attach_idle_hook(fptr);
+}
+
+Thread::~Thread() {
+    // terminate is thread safe
+    terminate();
+#ifdef __MBED_CMSIS_RTOS_CM
+    if (_dynamic_stack) {
+        delete[] (_thread_def.stack_pointer);
+    }
+#endif
+}
+
+void Thread::_thunk(const void * thread_ptr)
+{
+    Thread *t = (Thread*)thread_ptr;
+    t->_task();
+    t->_mutex.lock();
+    t->_tid = (osThreadId)NULL;
+    t->_join_sem.release();
+    // rtos will release the mutex automatically
+}
+
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/Thread.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,295 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef THREAD_H
+#define THREAD_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+#include "Callback.h"
+#include "toolchain.h"
+#include "Semaphore.h"
+#include "Mutex.h"
+
+namespace rtos {
+
+/** The Thread class allow defining, creating, and controlling thread functions in the system. */
+class Thread {
+public:
+    /** Allocate a new thread without starting execution
+      @param   priority       initial priority of the thread function. (default: osPriorityNormal).
+      @param   stack_size      stack size (in bytes) requirements for the thread function. (default: DEFAULT_STACK_SIZE).
+      @param   stack_pointer  pointer to the stack area to be used by this thread (default: NULL).
+    */
+    Thread(osPriority priority=osPriorityNormal,
+           uint32_t stack_size=DEFAULT_STACK_SIZE,
+           unsigned char *stack_pointer=NULL) {
+        constructor(priority, stack_size, stack_pointer);
+    }
+
+    /** Create a new thread, and start it executing the specified function.
+      @param   task           function to be executed by this thread.
+      @param   argument       pointer that is passed to the thread function as start argument. (default: NULL).
+      @param   priority       initial priority of the thread function. (default: osPriorityNormal).
+      @param   stack_size      stack size (in bytes) requirements for the thread function. (default: DEFAULT_STACK_SIZE).
+      @param   stack_pointer  pointer to the stack area to be used by this thread (default: NULL).
+      @deprecated
+        Thread-spawning constructors hide errors and may lead to complex
+        program state when a thread is declared.
+
+        The explicit Thread::start member function should be used to spawn
+        a thread.
+    */
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Thread-spawning constructors hide errors and may lead to complex "
+        "program state when a thread is declared")
+    Thread(mbed::Callback<void()> task,
+           osPriority priority=osPriorityNormal,
+           uint32_t stack_size=DEFAULT_STACK_SIZE,
+           unsigned char *stack_pointer=NULL) {
+        constructor(task, priority, stack_size, stack_pointer);
+    }
+
+    /** Create a new thread, and start it executing the specified function.
+      @param   obj            argument to task.
+      @param   method         function to be executed by this thread.
+      @param   argument       pointer that is passed to the thread function as start argument. (default: NULL).
+      @param   priority       initial priority of the thread function. (default: osPriorityNormal).
+      @param   stack_size      stack size (in bytes) requirements for the thread function. (default: DEFAULT_STACK_SIZE).
+      @param   stack_pointer  pointer to the stack area to be used by this thread (default: NULL).
+      @deprecated
+        Thread-spawning constructors hide errors and may lead to complex
+        program state when a thread is declared.
+
+        The explicit Thread::start member function should be used to spawn
+        a thread.
+    */
+    template <typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Thread-spawning constructors hide errors and may lead to complex "
+        "program state when a thread is declared")
+    Thread(T *obj, void (T::*method)(),
+           osPriority priority=osPriorityNormal,
+           uint32_t stack_size=DEFAULT_STACK_SIZE,
+           unsigned char *stack_pointer=NULL) {
+        constructor(mbed::Callback<void()>(obj, method),
+                    priority, stack_size, stack_pointer);
+    }
+
+    /** Create a new thread, and start it executing the specified function.
+      @param   obj            argument to task.
+      @param   method         function to be executed by this thread.
+      @param   argument       pointer that is passed to the thread function as start argument. (default: NULL).
+      @param   priority       initial priority of the thread function. (default: osPriorityNormal).
+      @param   stack_size      stack size (in bytes) requirements for the thread function. (default: DEFAULT_STACK_SIZE).
+      @param   stack_pointer  pointer to the stack area to be used by this thread (default: NULL).
+      @deprecated
+        Thread-spawning constructors hide errors and may lead to complex
+        program state when a thread is declared.
+
+        The explicit Thread::start member function should be used to spawn
+        a thread.
+    */
+    template <typename T>
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Thread-spawning constructors hide errors and may lead to complex "
+        "program state when a thread is declared")
+    Thread(T *obj, void (*method)(T *),
+           osPriority priority=osPriorityNormal,
+           uint32_t stack_size=DEFAULT_STACK_SIZE,
+           unsigned char *stack_pointer=NULL) {
+        constructor(mbed::Callback<void()>(obj, method),
+                    priority, stack_size, stack_pointer);
+    }
+
+    /** Create a new thread, and start it executing the specified function.
+        Provided for backwards compatibility
+      @param   task           function to be executed by this thread.
+      @param   argument       pointer that is passed to the thread function as start argument. (default: NULL).
+      @param   priority       initial priority of the thread function. (default: osPriorityNormal).
+      @param   stack_size      stack size (in bytes) requirements for the thread function. (default: DEFAULT_STACK_SIZE).
+      @param   stack_pointer  pointer to the stack area to be used by this thread (default: NULL).
+      @deprecated
+        Thread-spawning constructors hide errors and may lead to complex
+        program state when a thread is declared.
+
+        The explicit Thread::start member function should be used to spawn
+        a thread.
+    */
+    MBED_DEPRECATED_SINCE("mbed-os-5.1",
+        "Thread-spawning constructors hide errors and may lead to complex "
+        "program state when a thread is declared")
+    Thread(void (*task)(void const *argument), void *argument=NULL,
+           osPriority priority=osPriorityNormal,
+           uint32_t stack_size=DEFAULT_STACK_SIZE,
+           unsigned char *stack_pointer=NULL) {
+        constructor(mbed::Callback<void()>(argument, (void (*)(void *))task),
+                    priority, stack_size, stack_pointer);
+    }
+
+    /** Starts a thread executing the specified function.
+      @param   task           function to be executed by this thread.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus start(mbed::Callback<void()> task);
+
+    /** Starts a thread executing the specified function.
+      @param   obj            argument to task
+      @param   method         function to be executed by this thread.
+      @return  status code that indicates the execution status of the function.
+    */
+    template <typename T, typename M>
+    osStatus start(T *obj, M method) {
+        return start(mbed::Callback<void()>(obj, method));
+    }
+
+    /** Wait for thread to terminate
+      @return  status code that indicates the execution status of the function.
+      @note not callable from interrupt
+    */
+    osStatus join();
+
+    /** Terminate execution of a thread and remove it from Active Threads
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus terminate();
+
+    /** Set priority of an active thread
+      @param   priority  new priority value for the thread function.
+      @return  status code that indicates the execution status of the function.
+    */
+    osStatus set_priority(osPriority priority);
+
+    /** Get priority of an active thread
+      @return  current priority value of the thread function.
+    */
+    osPriority get_priority();
+
+    /** Set the specified Signal Flags of an active thread.
+      @param   signals  specifies the signal flags of the thread that should be set.
+      @return  previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+    */
+    int32_t signal_set(int32_t signals);
+
+    /** Clears the specified Signal Flags of an active thread.
+      @param   signals  specifies the signal flags of the thread that should be cleared.
+      @return  resultant signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+    */
+    int32_t signal_clr(int32_t signals);
+
+    /** State of the Thread */
+    enum State {
+        Inactive,           /**< Not created or terminated */
+        Ready,              /**< Ready to run */
+        Running,            /**< Running */
+        WaitingDelay,       /**< Waiting for a delay to occur */
+        WaitingInterval,    /**< Waiting for an interval to occur */
+        WaitingOr,          /**< Waiting for one event in a set to occur */
+        WaitingAnd,         /**< Waiting for multiple events in a set to occur */
+        WaitingSemaphore,   /**< Waiting for a semaphore event to occur */
+        WaitingMailbox,     /**< Waiting for a mailbox event to occur */
+        WaitingMutex,       /**< Waiting for a mutex event to occur */
+
+        /* Not in sync with RTX below here */
+        Deleted,            /**< The task has been deleted */
+    };
+
+    /** State of this Thread
+      @return  the State of this Thread
+    */
+    State get_state();
+    
+    /** Get the total stack memory size for this Thread
+      @return  the total stack memory size in bytes
+    */
+    uint32_t stack_size();
+    
+    /** Get the currently unused stack memory for this Thread
+      @return  the currently unused stack memory in bytes
+    */
+    uint32_t free_stack();
+    
+    /** Get the currently used stack memory for this Thread
+      @return  the currently used stack memory in bytes
+    */
+    uint32_t used_stack();
+    
+    /** Get the maximum stack memory usage to date for this Thread
+      @return  the maximum stack memory usage to date in bytes
+    */
+    uint32_t max_stack();
+
+    /** Wait for one or more Signal Flags to become signaled for the current RUNNING thread.
+      @param   signals   wait until all specified signal flags set or 0 for any single signal flag.
+      @param   millisec  timeout value or 0 in case of no time-out. (default: osWaitForever).
+      @return  event flag information or error code.
+      @note not callable from interrupt
+    */
+    static osEvent signal_wait(int32_t signals, uint32_t millisec=osWaitForever);
+
+    /** Wait for a specified time period in millisec:
+      @param   millisec  time delay value
+      @return  status code that indicates the execution status of the function.
+      @note not callable from interrupt
+    */
+    static osStatus wait(uint32_t millisec);
+
+    /** Pass control to next thread that is in state READY.
+      @return  status code that indicates the execution status of the function.
+      @note not callable from interrupt
+    */
+    static osStatus yield();
+
+    /** Get the thread id of the current running thread.
+      @return  thread ID for reference by other functions or NULL in case of error.
+    */
+    static osThreadId gettid();
+    
+    /** Attach a function to be called by the RTOS idle task
+      @param   fptr  pointer to the function to be called
+    */
+    static void attach_idle_hook(void (*fptr)(void));
+
+    virtual ~Thread();
+
+private:
+    // Required to share definitions without
+    // delegated constructors
+    void constructor(osPriority priority=osPriorityNormal,
+                     uint32_t stack_size=DEFAULT_STACK_SIZE,
+                     unsigned char *stack_pointer=NULL);
+    void constructor(mbed::Callback<void()> task,
+                     osPriority priority=osPriorityNormal,
+                     uint32_t stack_size=DEFAULT_STACK_SIZE,
+                     unsigned char *stack_pointer=NULL);
+    static void _thunk(const void * thread_ptr);
+
+    mbed::Callback<void()> _task;
+    osThreadId _tid;
+    osThreadDef_t _thread_def;
+    bool _dynamic_stack;
+    Semaphore _join_sem;
+    Mutex _mutex;
+};
+
+}
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/rtos.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef RTOS_H
+#define RTOS_H
+
+#include "Thread.h"
+#include "Mutex.h"
+#include "RtosTimer.h"
+#include "Semaphore.h"
+#include "Mail.h"
+#include "MemoryPool.h"
+#include "Queue.h"
+
+using namespace rtos;
+
+/* Get mbed lib version number, as RTOS depends on mbed lib features
+   like mbed_error, Callback and others.
+*/
+#include "mbed.h"
+
+#if (MBED_LIBRARY_VERSION < 122)
+#error "This version of RTOS requires mbed library version > 121"
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/rtos_idle.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "rtos_idle.h"
+
+static void default_idle_hook(void)
+{
+    /* Sleep: ideally, we should put the chip to sleep.
+     Unfortunately, this usually requires disconnecting the interface chip (debugger).
+     This can be done, but it would break the local file system.
+    */
+    // sleep();
+}
+static void (*idle_hook_fptr)(void) = &default_idle_hook;
+
+void rtos_attach_idle_hook(void (*fptr)(void))
+{
+    //Attach the specified idle hook, or the default idle hook in case of a NULL pointer
+    if (fptr != NULL) {
+        idle_hook_fptr = fptr;
+    } else {
+        idle_hook_fptr = default_idle_hook;
+    }
+}
+
+void rtos_idle_loop(void)
+{
+    //Continuously call the idle hook function pointer
+    while (1) {
+        idle_hook_fptr();
+    }
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtos/rtos_idle.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef RTOS_IDLE_H
+#define RTOS_IDLE_H
+
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void rtos_attach_idle_hook(void (*fptr)(void));
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/HAL_CA.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,125 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    HAL_CA.C
+ *      Purpose: Hardware Abstraction Layer for Cortex-A
+ *      Rev.:
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_HAL_CA.h"
+
+/*--------------------------- os_init_context -------------------------------*/
+
+void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
+  /* Prepare TCB and saved context for a first time start of a task. */
+  U32 *stk,i,size;
+
+  /* Prepare a complete interrupt frame for first task start */
+  size = p_TCB->priv_stack >> 2;
+  if (size == 0) {
+    size = (U16)os_stackinfo >> 2;
+  }
+  /* Write to the top of stack. */
+  stk = &p_TCB->stack[size];
+
+  /* Auto correct to 8-byte ARM stack alignment. */
+  if ((U32)stk & 0x04) {
+    stk--;
+  }
+
+  stk -= 16;
+
+  /* Initial PC and default CPSR */
+  stk[14] = (U32)task_body;
+  /* Task run mode is inherited from the startup file. */
+  /*  (non-privileged USER or privileged SYSTEM mode)  */
+  stk[15] = (os_flags & 1) ? INIT_CPSR_SYS : INIT_CPSR_USER;
+  /* Set T-bit if task function in Thumb mode. */
+  if ((U32)task_body & 1) {
+    stk[15] |= CPSR_T_BIT;
+  }
+  /* Assign a void pointer to R0. */
+  stk[8]  = (U32)p_TCB->msg;
+  /* Clear R1-R12,LR registers. */
+  for (i = 0; i < 8; i++) {
+    stk[i] = 0;
+  }
+  for (i = 9; i < 14; i++) {
+    stk[i] = 0;
+  }
+
+  /* Initial Task stack pointer. */
+  p_TCB->tsk_stack = (U32)stk;
+
+  /* Task entry point. */
+  p_TCB->ptask = task_body;
+
+  /* Set a magic word for checking of stack overflow. */
+  p_TCB->stack[0] = MAGIC_WORD;
+}
+
+
+/*--------------------------- rt_ret_val ----------------------------------*/
+
+static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
+  /* Get pointer to task return value registers (R0..R3) in Stack */
+  if (p_TCB->stack_frame & 0x4) {
+    /* NEON/D32 Stack Frame: D0-31,FPSCR,Reserved,R4-R11,R0-R3,R12,LR,PC,xPSR */
+    return (U32 *)(p_TCB->tsk_stack + 8*4 + 2*4 + 32*8);
+  } else if (p_TCB->stack_frame & 0x2) {
+    /* VFP/D16 Stack Frame: D0-D15/S0-31,FPSCR,Reserved,R4-R11,R0-R3,R12,LR,PC,xPSR */
+    return (U32 *)(p_TCB->tsk_stack + 8*4 + 2*4 + 32*4);
+  } else {
+    /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
+    return (U32 *)(p_TCB->tsk_stack + 8*4);
+  }
+}
+
+void rt_ret_val (P_TCB p_TCB, U32 v0) {
+  U32 *ret;
+
+  ret = rt_ret_regs(p_TCB);
+  ret[0] = v0;
+}
+
+void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
+  U32 *ret;
+
+  ret = rt_ret_regs(p_TCB);
+  ret[0] = v0;
+  ret[1] = v1;
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/RTX_CM_lib.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,564 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_CM_LIB.H
+ *      Purpose: RTX Kernel System Configuration
+ *      Rev.:    V4.73
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#if   defined (__CC_ARM)
+#include <rt_misc.h>
+#pragma O3
+#define __USED __attribute__((used))
+#elif defined (__GNUC__)
+#pragma GCC optimize ("O3")
+#define __USED __attribute__((used))
+#elif defined (__ICCARM__)
+#define __USED __root
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      Definitions
+ *---------------------------------------------------------------------------*/
+
+#define _declare_box(pool,size,cnt)  uint32_t pool[(((size)+3)/4)*(cnt) + 3]
+#define _declare_box8(pool,size,cnt) uint64_t pool[(((size)+7)/8)*(cnt) + 2]
+
+#define OS_TCB_SIZE     60
+#define OS_TMR_SIZE     8
+
+#if defined (__CC_ARM) && !defined (__MICROLIB)
+
+typedef void    *OS_ID;
+typedef uint32_t OS_TID;
+typedef uint32_t OS_MUT[4];
+typedef uint32_t OS_RESULT;
+
+#define runtask_id()    rt_tsk_self()
+#define mutex_init(m)   rt_mut_init(m)
+#define mutex_wait(m)   os_mut_wait(m,0xFFFF)
+#define mutex_rel(m)    os_mut_release(m)
+
+extern OS_TID    rt_tsk_self    (void);
+extern void      rt_mut_init    (OS_ID mutex);
+extern OS_RESULT rt_mut_release (OS_ID mutex);
+extern OS_RESULT rt_mut_wait    (OS_ID mutex, uint16_t timeout);
+
+#define os_mut_wait(mutex,timeout) _os_mut_wait((uint32_t)rt_mut_wait,mutex,timeout)
+#define os_mut_release(mutex)      _os_mut_release((uint32_t)rt_mut_release,mutex)
+
+OS_RESULT _os_mut_release (uint32_t p, OS_ID mutex)                   __svc_indirect(0);
+OS_RESULT _os_mut_wait    (uint32_t p, OS_ID mutex, uint16_t timeout) __svc_indirect(0);
+
+#elif defined (__ICCARM__)
+
+typedef void    *OS_ID;
+typedef uint32_t OS_TID;
+typedef uint32_t OS_MUT[4];
+typedef uint32_t OS_RESULT;
+
+#define runtask_id()    rt_tsk_self()
+#define mutex_init(m)   rt_mut_init(m)
+#define mutex_del(m)    os_mut_delete(m)
+#define mutex_wait(m)   os_mut_wait(m,0xFFFF)
+#define mutex_rel(m)    os_mut_release(m)
+
+extern OS_TID    rt_tsk_self    (void);
+extern void      rt_mut_init    (OS_ID mutex);
+extern OS_RESULT rt_mut_delete  (OS_ID mutex);
+extern OS_RESULT rt_mut_release (OS_ID mutex);
+extern OS_RESULT rt_mut_wait    (OS_ID mutex, uint16_t timeout);
+
+#pragma swi_number=0
+__swi OS_RESULT _os_mut_delete  (OS_ID mutex);
+
+static inline OS_RESULT os_mut_delete(OS_ID mutex)
+{
+    __asm("mov r12,%0\n" :: "r"(&rt_mut_delete) : "r12" );
+    return _os_mut_delete(mutex);
+}
+
+#pragma swi_number=0
+__swi OS_RESULT _os_mut_release (OS_ID mutex);
+
+static inline OS_RESULT os_mut_release(OS_ID mutex)
+{
+    __asm("mov r12,%0\n" :: "r"(&rt_mut_release) : "r12" );
+    return _os_mut_release(mutex);
+}
+
+#pragma swi_number=0
+__swi OS_RESULT _os_mut_wait    (OS_ID mutex, uint16_t timeout);
+
+static inline OS_RESULT os_mut_wait(OS_ID mutex, uint16_t timeout)
+{
+    __asm("mov r12,%0\n" :: "r"(&rt_mut_wait) : "r12" );
+    return _os_mut_wait(mutex, timeout);
+}
+
+#include <yvals.h> /* for include DLib_Thread.h */
+
+void __iar_system_Mtxinit(__iar_Rmtx *);
+void __iar_system_Mtxdst(__iar_Rmtx *);
+void __iar_system_Mtxlock(__iar_Rmtx *);
+void __iar_system_Mtxunlock(__iar_Rmtx *);
+
+
+
+
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+#if (OS_TIMERS != 0)
+#define OS_TASK_CNT (OS_TASKCNT + 1)
+#ifndef __MBED_CMSIS_RTOS_CA9
+#define OS_PRIV_CNT (OS_PRIVCNT + 2)
+#define OS_STACK_SZ (4*(OS_PRIVSTKSIZE+OS_MAINSTKSIZE+OS_TIMERSTKSZ))
+#endif
+#else
+#define OS_TASK_CNT  OS_TASKCNT
+#ifndef __MBED_CMSIS_RTOS_CA9
+#define OS_PRIV_CNT (OS_PRIVCNT + 1)
+#define OS_STACK_SZ (4*(OS_PRIVSTKSIZE+OS_MAINSTKSIZE))
+#endif
+#endif
+
+uint16_t const os_maxtaskrun = OS_TASK_CNT;
+#ifdef __MBED_CMSIS_RTOS_CA9
+uint32_t const os_stackinfo  = (OS_STKCHECK<<24)| (OS_IDLESTKSIZE*4);
+#else
+uint32_t const os_stackinfo  = (OS_STKCHECK<<24)| (OS_PRIV_CNT<<16) | (OS_STKSIZE*4);
+#endif
+uint32_t const os_rrobin     = (OS_ROBIN << 16) | OS_ROBINTOUT;
+uint32_t const os_tickfreq   = OS_CLOCK;
+uint16_t const os_tickus_i   = OS_CLOCK/1000000;
+uint16_t const os_tickus_f   = (((uint64_t)(OS_CLOCK-1000000*(OS_CLOCK/1000000)))<<16)/1000000;
+uint32_t const os_trv        = OS_TRV;
+uint8_t  const os_flags      = OS_RUNPRIV;
+
+/* Export following defines to uVision debugger. */
+__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS;
+__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX;
+__USED uint32_t const os_clockrate = OS_TICK;
+__USED uint32_t const os_timernum  = 0;
+
+/* Memory pool for TCB allocation    */
+_declare_box  (mp_tcb, OS_TCB_SIZE, OS_TASK_CNT);
+uint16_t const mp_tcb_size = sizeof(mp_tcb);
+
+#ifdef __MBED_CMSIS_RTOS_CA9
+/* Memory pool for os_idle_demon stack allocation. */
+_declare_box8 (mp_stk, OS_IDLESTKSIZE*4, 1);
+uint32_t const mp_stk_size = sizeof(mp_stk);
+#else
+/* Memory pool for System stack allocation (+os_idle_demon). */
+_declare_box8 (mp_stk, OS_STKSIZE*4, OS_TASK_CNT-OS_PRIV_CNT+1);
+uint32_t const mp_stk_size = sizeof(mp_stk);
+
+/* Memory pool for user specified stack allocation (+main, +timer) */
+uint64_t       os_stack_mem[2+OS_PRIV_CNT+(OS_STACK_SZ/8)];
+uint32_t const os_stack_sz = sizeof(os_stack_mem);
+#endif
+
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+/* Fifo Queue buffer for ISR requests.*/
+uint32_t       os_fifo[OS_FIFOSZ*2+1];
+uint8_t  const os_fifo_size = OS_FIFOSZ;
+
+/* An array of Active task pointers. */
+void *os_active_TCB[OS_TASK_CNT];
+
+/* User Timers Resources */
+#if (OS_TIMERS != 0)
+extern void osTimerThread (void const *argument);
+#ifdef __MBED_CMSIS_RTOS_CA9
+osThreadDef(osTimerThread, (osPriority)(OS_TIMERPRIO-3), 4*OS_TIMERSTKSZ);
+#else
+osThreadDef(osTimerThread, (osPriority)(OS_TIMERPRIO-3), 1, 4*OS_TIMERSTKSZ);
+#endif
+osThreadId osThreadId_osTimerThread;
+osMessageQDef(osTimerMessageQ, OS_TIMERCBQS, void *);
+osMessageQId osMessageQId_osTimerMessageQ;
+#else
+osThreadDef_t os_thread_def_osTimerThread = { NULL };
+osThreadId osThreadId_osTimerThread;
+osMessageQDef(osTimerMessageQ, 0, void *);
+osMessageQId osMessageQId_osTimerMessageQ;
+#endif
+
+/* Legacy RTX User Timers not used */
+uint32_t       os_tmr = 0;
+uint32_t const *m_tmr = NULL;
+uint16_t const mp_tmr_size = 0;
+
+/* singleton mutex */
+osMutexId singleton_mutex_id;
+osMutexDef(singleton_mutex);
+
+#if defined (__CC_ARM) && !defined (__MICROLIB)
+ /* A memory space for arm standard library. */
+ static uint32_t std_libspace[OS_TASK_CNT][96/4];
+ static OS_MUT   std_libmutex[OS_MUTEXCNT];
+ static uint32_t nr_mutex;
+ extern void  *__libspace_start;
+#elif defined (__ICCARM__)
+typedef struct os_mut_array {
+    OS_MUT   mutex;
+    uint32_t used;
+} os_mut_array_t;
+
+static os_mut_array_t std_libmutex[OS_MUTEXCNT];/* must be Zero clear */
+static uint32_t nr_mutex = 0;
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Optimizations (empty functions)
+ *---------------------------------------------------------------------------*/
+
+#if OS_ROBIN == 0
+ void rt_init_robin (void) {;}
+ void rt_chk_robin  (void) {;}
+#endif
+
+#if OS_STKCHECK == 0
+ void rt_stk_check  (void) {;}
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      Standard Library multithreading interface
+ *---------------------------------------------------------------------------*/
+
+#if defined (__CC_ARM) && !defined (__MICROLIB)
+
+/*--------------------------- __user_perthread_libspace ---------------------*/
+
+void *__user_perthread_libspace (void) {
+  /* Provide a separate libspace for each task. */
+  uint32_t idx;
+
+  idx = runtask_id ();
+  if (idx == 0) {
+    /* RTX not running yet. */
+    return (&__libspace_start);
+  }
+  return ((void *)&std_libspace[idx-1]);
+}
+
+/*--------------------------- _mutex_initialize -----------------------------*/
+
+int _mutex_initialize (OS_ID *mutex) {
+  /* Allocate and initialize a system mutex. */
+
+  if (nr_mutex >= OS_MUTEXCNT) {
+    /* If you are here, you need to increase the number OS_MUTEXCNT. */
+    for (;;);
+  }
+  *mutex = &std_libmutex[nr_mutex++];
+  mutex_init (*mutex);
+  return (1);
+}
+
+
+/*--------------------------- _mutex_acquire --------------------------------*/
+
+__attribute__((used)) void _mutex_acquire (OS_ID *mutex) {
+  /* Acquire a system mutex, lock stdlib resources. */
+  if (runtask_id ()) {
+    /* RTX running, acquire a mutex. */
+    mutex_wait (*mutex);
+  }
+}
+
+
+/*--------------------------- _mutex_release --------------------------------*/
+
+__attribute__((used)) void _mutex_release (OS_ID *mutex) {
+  /* Release a system mutex, unlock stdlib resources. */
+  if (runtask_id ()) {
+    /* RTX running, release a mutex. */
+    mutex_rel (*mutex);
+  }
+}
+
+#elif defined (__ICCARM__)
+
+/*--------------------------- __iar_system_Mtxinit --------------------------*/
+
+void __iar_system_Mtxinit(__iar_Rmtx *mutex)
+{
+    /* Allocate and initialize a system mutex. */
+    int32_t idx;
+
+    for (idx = 0; idx < OS_MUTEXCNT; idx++)
+    {
+        if (std_libmutex[idx].used == 0)
+        {
+            std_libmutex[idx].used = 1;
+            *mutex = &std_libmutex[idx].mutex;
+            nr_mutex++;
+            break;
+        }
+    }
+    if (nr_mutex >= OS_MUTEXCNT)
+    {
+        /* If you are here, you need to increase the number OS_MUTEXCNT. */
+        for (;;);
+    }
+  
+    mutex_init (*mutex);
+}
+
+/*--------------------------- __iar_system_Mtxdst ---------------------------*/
+
+void __iar_system_Mtxdst(__iar_Rmtx *mutex)
+{
+    /* Free a system mutex. */
+    int32_t idx;
+
+    if (nr_mutex == 0)
+    {
+        for (;;);
+    }
+
+    idx = ((((uint32_t)mutex) - ((uint32_t)&std_libmutex[0].mutex))
+           / sizeof(os_mut_array_t));
+
+    if (idx >= OS_MUTEXCNT)
+    {
+        for (;;);
+    }
+
+    mutex_del (*mutex);
+    std_libmutex[idx].used = 0;
+}
+
+/*--------------------------- __iar_system_Mtxlock --------------------------*/
+
+void __iar_system_Mtxlock(__iar_Rmtx *mutex)
+{
+    /* Acquire a system mutex, lock stdlib resources. */
+    if (runtask_id ())
+    {
+        /* RTX running, acquire a mutex. */
+        mutex_wait (*mutex);
+    }
+}
+
+/*--------------------------- __iar_system_Mtxunlock ------------------------*/
+
+void __iar_system_Mtxunlock(__iar_Rmtx *mutex)
+{
+    /* Release a system mutex, unlock stdlib resources. */
+    if (runtask_id ())
+    {
+        /* RTX running, release a mutex. */
+        mutex_rel (*mutex);
+    }
+}
+
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Startup
+ *---------------------------------------------------------------------------*/
+
+/* Main Thread definition */
+extern void pre_main (void);
+#ifdef __MBED_CMSIS_RTOS_CA9
+uint32_t os_thread_def_stack_main [(4 * OS_MAINSTKSIZE) / sizeof(uint32_t)];
+osThreadDef_t os_thread_def_main = {(os_pthread)pre_main, osPriorityNormal, 1, 4*OS_MAINSTKSIZE, os_thread_def_stack_main };
+#else
+osThreadDef_t os_thread_def_main = {(os_pthread)pre_main, osPriorityNormal, 1, 4*OS_MAINSTKSIZE };
+#endif
+
+#if defined (__CC_ARM)
+
+#ifdef __MICROLIB
+
+int main(void);
+void _main_init (void) __attribute__((section(".ARM.Collect$$$$000000FF")));
+void $Super$$__cpp_initialize__aeabi_(void);
+
+#if __TARGET_ARCH_ARM
+#pragma push
+#pragma arm
+#endif
+void _main_init (void) {
+  osKernelInitialize();
+  osThreadCreate(&os_thread_def_main, NULL);
+  osKernelStart();
+  for (;;);
+}
+#if __TARGET_ARCH_ARM
+#pragma pop
+#endif
+
+void $Sub$$__cpp_initialize__aeabi_(void)  
+{  
+  // this should invoke C++ initializers prior _main_init, we keep this empty and  
+  // invoke them after _main_init (=starts RTX kernel)  
+}  
+
+void pre_main()  
+{  
+  singleton_mutex_id = osMutexCreate(osMutex(singleton_mutex));
+  $Super$$__cpp_initialize__aeabi_();  
+  main();  
+}
+
+#else
+
+void * armcc_heap_base;
+void * armcc_heap_top;
+
+int main(void);
+
+void pre_main (void)
+{
+    singleton_mutex_id = osMutexCreate(osMutex(singleton_mutex));
+    __rt_lib_init((unsigned)armcc_heap_base, (unsigned)armcc_heap_top);
+    main();
+}
+
+__asm void __rt_entry (void) {
+
+  IMPORT  __user_setup_stackheap
+  IMPORT  os_thread_def_main
+  IMPORT  armcc_heap_base
+  IMPORT  armcc_heap_top
+  IMPORT  osKernelInitialize
+  IMPORT  osKernelStart
+  IMPORT  osThreadCreate
+
+  BL      __user_setup_stackheap
+  LDR     R3,=armcc_heap_base
+  LDR     R4,=armcc_heap_top
+  STR     R0,[R3]
+  STR     R2,[R4]
+  BL      osKernelInitialize
+  LDR     R0,=os_thread_def_main
+  MOVS    R1,#0
+  BL      osThreadCreate
+  BL      osKernelStart
+  /* osKernelStart should not return */
+  B       .
+
+  ALIGN
+}
+#endif
+
+#elif defined (__GNUC__)
+extern int atexit(void (*func)(void));
+extern void __libc_fini_array(void);
+extern void __libc_init_array (void);
+extern int main(int argc, char **argv);
+
+void pre_main(void) {
+    singleton_mutex_id = osMutexCreate(osMutex(singleton_mutex));
+    atexit(__libc_fini_array);
+    __libc_init_array();
+    main(0, NULL);
+}
+
+__attribute__((naked)) void software_init_hook_rtos (void) {
+  __asm (
+    ".syntax unified\n"
+    ".arm\n"
+    "bl   osKernelInitialize\n"
+    "ldr  r0,=os_thread_def_main\n"
+    "movs r1,#0\n"
+    "bl   osThreadCreate\n"
+    "bl   osKernelStart\n"
+    /* osKernelStart should not return */ 
+    "B       .\n"
+  );
+}
+
+#elif defined (__ICCARM__)
+extern void* __vector_core_a9;
+extern int  __low_level_init(void);
+extern void __iar_data_init3(void);
+extern __weak void __iar_init_core( void );
+extern __weak void __iar_init_vfp( void );
+extern void __iar_dynamic_initialization(void);
+extern void mbed_sdk_init(void);
+extern void mbed_main(void);
+extern int main(void);
+static uint8_t low_level_init_needed;
+
+void pre_main(void) {
+    singleton_mutex_id = osMutexCreate(osMutex(singleton_mutex));
+    if (low_level_init_needed) {
+        __iar_dynamic_initialization();
+    }
+    mbed_main();
+    main();
+}
+
+#pragma required=__vector_core_a9
+void __iar_program_start( void )
+{
+  __iar_init_core();
+  __iar_init_vfp();
+  
+  uint8_t low_level_init_needed_local;
+  
+  low_level_init_needed_local = __low_level_init();
+  if (low_level_init_needed_local) {
+     __iar_data_init3();
+     mbed_sdk_init();
+   }
+  /* Store in a global variable after RAM has been initialized */
+  low_level_init_needed = low_level_init_needed_local;
+  osKernelInitialize();
+  osThreadCreate(&os_thread_def_main, NULL);
+  osKernelStart();
+  /* osKernelStart should not return */
+  while (1);
+}
+
+#endif
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,333 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_Conf_CM.C
+ *      Purpose: Configuration of CMSIS RTX Kernel
+ *      Rev.:    V4.60
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+#if defined(MBED_RTOS_SINGLE_THREAD)
+#define OS_TASKCNT  1
+#define OS_TIMERS   0
+#endif
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>Thread Configuration
+// =======================
+//
+//   <o>Number of concurrent running threads <0-250>
+//   <i> Defines max. number of threads that will run at the same time.
+//   <i> Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT     25
+#endif
+
+#ifdef __MBED_CMSIS_RTOS_CA9
+//   <o>Idle stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines default stack size for the Idle thread.
+#ifndef OS_IDLESTKSIZE
+ #define OS_IDLESTKSIZE 128
+#endif
+#else // __MBED_CMSIS_RTOS_CA9
+//   <o>Default Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines default stack size for threads with osThreadDef stacksz = 0
+//   <i> Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE     200
+#endif
+#endif // __MBED_CMSIS_RTOS_CA9
+
+//   <o>Main Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines stack size for main thread.
+//   <i> Default: 4096
+#ifndef OS_MAINSTKSIZE
+ #define OS_MAINSTKSIZE 4096
+#endif
+
+#ifndef __MBED_CMSIS_RTOS_CA9
+//   <o>Number of threads with user-provided stack size <0-250>
+//   <i> Defines the number of threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT     0
+#endif
+
+//   <o>Total stack size [bytes] for threads with user-provided stack size <0-4096:8><#/4>
+//   <i> Defines the combined stack size for threads with user-provided stack size.
+//   <i> Default: 0
+#ifndef OS_PRIVSTKSIZE
+ #define OS_PRIVSTKSIZE 0
+#endif
+#endif // __MBED_CMSIS_RTOS_CA9
+
+// <q>Check for stack overflow
+// <i> Includes the stack checking code for stack overflow.
+// <i> Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+
+// <o>Processor mode for thread execution
+//   <0=> Unprivileged mode
+//   <1=> Privileged mode
+// <i> Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+
+// </h>
+
+// <h>RTX Kernel Timer Tick Configuration
+// ======================================
+// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
+// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
+#ifndef OS_SYSTICK
+ #define OS_SYSTICK     0
+#endif
+//
+//   <o>Timer clock value [Hz] <1-1000000000>
+//   <i> Defines the timer clock value.
+//   <i> Default: 12000000  (12MHz)
+#ifndef OS_CLOCK
+#  if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
+ #define OS_CLOCK       12000000
+#  else
+#    error "no target defined"
+#  endif
+#endif
+
+//   <o>Timer tick value [us] <1-1000000>
+//   <i> Defines the timer tick value.
+//   <i> Default: 1000  (1ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+
+// </h>
+
+// <h>System Configuration
+// =======================
+//
+// <e>Round-Robin Thread switching
+// ===============================
+//
+// <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+
+//   <o>Round-Robin Timeout [ticks] <1-1000>
+//   <i> Defines how long a thread will execute before a thread switch.
+//   <i> Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+
+// </e>
+
+// <e>User Timers
+// ==============
+//   <i> Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS      1
+#endif
+
+//   <o>Timer Thread Priority
+//                        <1=> Low
+//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
+//                        <5=> High
+//                        <6=> Realtime (highest)
+//   <i> Defines priority for Timer Thread
+//   <i> Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO   5
+#endif
+
+//   <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
+//   <i> Defines stack size for Timer thread.
+//   <i> Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ  WORDS_STACK_SIZE
+#endif
+
+//   <o>Timer Callback Queue size <1-32>
+//   <i> Number of concurrent active timer callback functions.
+//   <i> Default: 4
+#ifndef OS_TIMERCBQS
+ #define OS_TIMERCBQS   4
+#endif
+
+// </e>
+
+//   <o>ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//   <i> ISR functions store requests to this buffer,
+//   <i> when they are called from the interrupt handler.
+//   <i> Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+// </h>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    12
+#endif
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+extern void rtos_idle_loop(void);
+
+void os_idle_demon (void) {
+  /* The idle demon is a system thread, running when no other thread is      */
+  /* ready to run.                                                           */
+  rtos_idle_loop();
+}
+
+#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
+
+/*--------------------------- os_tick_init ----------------------------------*/
+#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
+#define OSTM0   (0xFCFEC000uL) /* OSTM0 */
+#define OSTM1   (0xFCFEC400uL) /* OSTM1 */
+#define CPG     (0xFCFE0410uL) /* CPG */
+
+#define CPGSTBCR5 (*((volatile unsigned char*)(CPG    + 0x00000018uL)))
+
+#define OSTM0CMP (*((volatile unsigned long*)(OSTM0   + 0x00000000uL)))
+#define OSTM0CNT (*((volatile unsigned long*)(OSTM0   + 0x00000004uL)))
+#define OSTM0TE  (*((volatile unsigned char*)(OSTM0   + 0x00000010uL)))
+#define OSTM0TS  (*((volatile unsigned char*)(OSTM0   + 0x00000014uL)))
+#define OSTM0TT  (*((volatile unsigned char*)(OSTM0   + 0x00000018uL)))
+#define OSTM0CTL (*((volatile unsigned char*)(OSTM0   + 0x00000020uL)))
+
+#define OSTM1CMP (*((volatile unsigned long*)(OSTM1   + 0x00000000uL)))
+#define OSTM1CNT (*((volatile unsigned long*)(OSTM1   + 0x00000004uL)))
+#define OSTM1TE  (*((volatile unsigned char*)(OSTM1   + 0x00000010uL)))
+#define OSTM1TS  (*((volatile unsigned char*)(OSTM1   + 0x00000014uL)))
+#define OSTM1TT  (*((volatile unsigned char*)(OSTM1   + 0x00000018uL)))
+#define OSTM1CTL (*((volatile unsigned char*)(OSTM1   + 0x00000020uL)))
+
+#define CPG_STBCR5_BIT_MSTP51   (0x02u) /* OSTM0 */
+#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
+#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
+
+typedef enum
+{
+    IRQ_SGI0       = 0,
+    IRQ_OSTMI0TINT = 134
+} IRQn_Type;
+
+typedef void(*IRQHandler)();
+
+extern void PendSV_Handler(uint32_t);
+extern void OS_Tick_Handler(uint32_t);
+extern uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler);
+#endif
+
+// Initialize alternative hardware timer as RTX kernel timer
+// Return: IRQ number of the alternative hardware timer
+int os_tick_init (void) {
+#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
+  CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); /* enable OSTM0 clock */
+
+  OSTM0TT   = 0x1;    /* Stop the counter and clears the OSTM0TE bit.     */
+  OSTM0CTL  = 0x1;    /* Interval timer mode. Interrupt enabled  */
+
+  OSTM0CMP  = (uint32_t)(((double)CM0_RENESAS_RZ_A1_P0_CLK*(double)OS_TICK)/1E6);
+
+  OSTM0TS   = 0x1;    /* Start the counter and sets the OSTM0TE bit.     */
+
+  InterruptHandlerRegister(IRQ_SGI0    , (IRQHandler)PendSV_Handler);
+  InterruptHandlerRegister(IRQ_OSTMI0TINT, (IRQHandler)OS_Tick_Handler);
+
+
+  return IRQ_OSTMI0TINT; /* Return IRQ number of timer (0..239) */
+              /* RTX will set and configure the interrupt */
+#endif
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+// Acknowledge alternative hardware timer interrupt
+void os_tick_irqack (void) {
+  /* ... */
+}
+
+#endif   // (OS_SYSTICK == 0)
+
+/*--------------------------- os_error --------------------------------------*/
+extern void mbed_die(void);
+
+void os_error (uint32_t err_code) {
+  /* This function is called when a runtime error is detected. Parameter */
+  /* 'err_code' holds the runtime error code (defined in RTL.H).         */
+    mbed_die();
+
+  /* HERE: include optional code to be executed on runtime error. */
+  for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_CM_lib.h"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/RTX_Config.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,79 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_CONFIG.H
+ *      Purpose: Exported functions of RTX_Config.c
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+
+/* Error Codes */
+#define OS_ERR_STK_OVF          1
+#define OS_ERR_FIFO_OVF         2
+#define OS_ERR_MBX_OVF          3
+
+/* Definitions */
+#define BOX_ALIGN_8                   0x80000000
+#define _declare_box(pool,size,cnt)   U32 pool[(((size)+3)/4)*(cnt) + 3]
+#define _declare_box8(pool,size,cnt)  U64 pool[(((size)+7)/8)*(cnt) + 2]
+#define _init_box8(pool,size,bsize)   _init_box (pool,size,(bsize) | BOX_ALIGN_8)
+
+/* Variables */
+extern U32 mp_tcb[];
+extern U64 mp_stk[];
+extern U32 os_fifo[];
+extern void *os_active_TCB[];
+
+/* Constants */
+extern U16 const os_maxtaskrun;
+extern U32 const os_trv;
+extern U8  const os_flags;
+extern U32 const os_stackinfo;
+extern U32 const os_rrobin;
+extern U32 const os_clockrate;
+extern U32 const os_timernum;
+extern U16 const mp_tcb_size;
+extern U32 const mp_stk_size;
+extern U32 const *m_tmr;
+extern U16 const mp_tmr_size;
+extern U8  const os_fifo_size;
+
+/* Functions */
+extern void os_idle_demon   (void);
+extern int  os_tick_init    (void);
+extern U32  os_tick_val     (void);
+extern U32  os_tick_ovf     (void);
+extern void os_tick_irqack  (void);
+extern void os_tmr_call     (U16  info);
+extern void os_error        (U32 err_code);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/HAL_CA9.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,438 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    HAL_CA9.c
+ *      Purpose: Hardware Abstraction Layer for Cortex-A9
+ *      Rev.:    8 April 2015
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2012 - 2015 ARM Limited
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_Task.h"
+#include "rt_List.h"
+#include "rt_MemBox.h"
+#include "rt_HAL_CA.h"
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+//For A-class, set USR/SYS stack
+__asm void rt_set_PSP (U32 stack) {
+        ARM
+
+        MRS     R1, CPSR
+        CPS     #MODE_SYS   ;no effect in USR mode
+        ISB
+        MOV     SP, R0
+        MSR     CPSR_c, R1  ;no effect in USR mode
+        ISB
+        BX      LR
+
+}
+
+//For A-class, get USR/SYS stack
+__asm U32 rt_get_PSP (void) {
+        ARM
+
+        MRS     R1, CPSR
+        CPS     #MODE_SYS   ;no effect in USR mode
+        ISB
+        MOV     R0, SP
+        MSR     CPSR_c, R1  ;no effect in USR mode
+        ISB
+        BX      LR
+}
+
+/*--------------------------- _alloc_box ------------------------------------*/
+__asm void *_alloc_box (void *box_mem) {
+    /* Function wrapper for Unprivileged/Privileged mode. */
+        ARM
+
+        LDR     R12,=__cpp(rt_alloc_box)
+        MRS     R2, CPSR
+        LSLS    R2, #28
+        BXNE    R12
+        SVC     0
+        BX      LR
+}
+
+
+/*--------------------------- _free_box -------------------------------------*/
+__asm int _free_box (void *box_mem, void *box) {
+   /* Function wrapper for Unprivileged/Privileged mode. */
+        ARM
+
+        LDR     R12,=__cpp(rt_free_box)
+        MRS     R2, CPSR
+        LSLS    R2, #28
+        BXNE    R12
+        SVC     0
+        BX      LR
+
+}
+
+/*-------------------------- SVC_Handler -----------------------------------*/
+
+#pragma push
+#pragma arm
+__asm void SVC_Handler (void) {
+        PRESERVE8
+        ARM
+
+        IMPORT  rt_tsk_lock
+        IMPORT  rt_tsk_unlock
+        IMPORT  SVC_Count
+        IMPORT  SVC_Table
+        IMPORT  rt_stk_check
+        IMPORT  FPUEnable
+        IMPORT  scheduler_suspended    ; flag set by rt_suspend, cleared by rt_resume, read by SVC_Handler
+
+Mode_SVC        EQU     0x13
+
+        SRSFD   SP!, #Mode_SVC         ; Push LR_SVC and SPRS_SVC onto SVC mode stack
+        PUSH    {R4}                   ; Push R4 so we can use it as a temp
+
+        MRS     R4,SPSR                ; Get SPSR
+        TST     R4,#CPSR_T_BIT         ; Check Thumb Bit
+        LDRNEH  R4,[LR,#-2]            ; Thumb: Load Halfword
+        BICNE   R4,R4,#0xFF00          ;        Extract SVC Number
+        LDREQ   R4,[LR,#-4]            ; ARM:   Load Word
+        BICEQ   R4,R4,#0xFF000000      ;        Extract SVC Number
+
+        /* Lock out systick and re-enable interrupts */
+        PUSH    {R0-R3,R12,LR}
+
+        AND     R12, SP, #4            ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R12            ; Adjust stack
+        PUSH    {R12, LR}              ; Store stack adjustment and dummy LR to SVC stack
+
+        BLX     rt_tsk_lock
+        CPSIE   i
+
+        POP     {R12, LR}              ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R12            ; Unadjust stack
+
+        POP     {R0-R3,R12,LR}
+
+        CMP     R4,#0
+        BNE     SVC_User
+
+        MRS     R4,SPSR
+        PUSH    {R4}                    ; Push R4 so we can use it as a temp
+        AND     R4, SP, #4              ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R4              ; Adjust stack
+        PUSH    {R4, LR}                ; Store stack adjustment and dummy LR
+        BLX     R12
+        POP     {R4, LR}                ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R4              ; Unadjust stack
+        POP     {R4}                    ; Restore R4
+        MSR     SPSR_CXSF,R4
+
+        /* Here we will be in SVC mode (even if coming in from PendSV_Handler or OS_Tick_Handler) */
+Sys_Switch
+        LDR     LR,=__cpp(&os_tsk)
+        LDM     LR,{R4,LR}              ; os_tsk.run, os_tsk.new_tsk
+        CMP     R4,LR
+        BNE     switching
+
+        PUSH    {R0-R3,R12,LR}
+
+        AND     R12, SP, #4             ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R12             ; Adjust stack
+        PUSH    {R12, LR}               ; Store stack adjustment and dummy LR to SVC stack
+
+        CPSID   i
+        ; Do not unlock scheduler if it has just been suspended by rt_suspend()
+        LDR     R1,=scheduler_suspended
+        LDRB    R0, [R1]
+        CMP     R0, #1
+        BEQ     dont_unlock
+        BLX     rt_tsk_unlock
+dont_unlock
+
+        POP     {R12, LR}               ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R12             ; Unadjust stack
+
+        POP     {R0-R3,R12,LR}
+        POP     {R4}
+        RFEFD   SP!                     ; Return from exception, no task switch
+
+switching
+        CLREX
+        CMP     R4,#0
+        ADDEQ   SP,SP,#12               ; Original R4, LR & SPSR do not need to be popped when we are paging in a different task
+        BEQ     SVC_Next                ; Runtask deleted?
+
+
+        PUSH    {R8-R11} //R4 and LR already stacked
+        MOV     R10,R4                  ; Preserve os_tsk.run
+        MOV     R11,LR                  ; Preserve os_tsk.new_tsk
+
+        ADD     R8,SP,#16               ; Unstack R4,LR
+        LDMIA   R8,{R4,LR}
+
+        SUB     SP,SP,#4                ; Make space on the stack for the next instn
+        STMIA   SP,{SP}^                ; Put User SP onto stack
+        POP     {R8}                    ; Pop User SP into R8
+
+        MRS     R9,SPSR
+        STMDB   R8!,{R9}                ; User CPSR
+        STMDB   R8!,{LR}                ; User PC
+        STMDB   R8,{LR}^                ; User LR
+        SUB     R8,R8,#4                ; No writeback for store of User LR
+        STMDB   R8!,{R0-R3,R12}         ; User R0-R3,R12
+        MOV     R3,R10                  ; os_tsk.run
+        MOV     LR,R11                  ; os_tsk.new_tsk
+        POP     {R9-R12}
+        ADD     SP,SP,#12               ; Fix up SP for unstack of R4, LR & SPSR
+        STMDB   R8!,{R4-R7,R9-R12}      ; User R4-R11
+
+        //If applicable, stack VFP/NEON state
+        MRC     p15,0,R1,c1,c0,2        ; VFP/NEON access enabled? (CPACR)
+        AND     R2,R1,#0x00F00000
+        CMP     R2,#0x00F00000
+        BNE     no_outgoing_vfp
+        VMRS    R2,FPSCR
+        STMDB   R8!,{R2,R4}             ; Push FPSCR, maintain 8-byte alignment
+        VSTMDB  R8!,{D0-D15}
+        VSTMDB  R8!,{D16-D31}
+        LDRB    R2,[R3,#TCB_STACKF]     ; Record in TCB that NEON/D32 state is stacked
+        ORR     R2,#4
+        STRB    R2,[R3,#TCB_STACKF]
+
+no_outgoing_vfp
+        STR     R8,[R3,#TCB_TSTACK]
+        MOV     R4,LR
+
+        PUSH    {R4}                    ; Push R4 so we can use it as a temp
+        AND     R4, SP, #4              ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R4              ; Adjust stack
+        PUSH    {R4, LR}                ; Store stack adjustment and dummy LR to SVC stack
+
+        BLX     rt_stk_check
+
+        POP     {R4, LR}                ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R4              ; Unadjust stack
+        POP     {R4}                    ; Restore R4
+
+        MOV     LR,R4
+
+SVC_Next  //R4 == os_tsk.run, LR == os_tsk.new_tsk, R0-R3, R5-R12 corruptible
+        LDR     R1,=__cpp(&os_tsk)      ; os_tsk.run = os_tsk.new_tsk
+        STR     LR,[R1]
+        LDRB    R1,[LR,#TCB_TID]        ; os_tsk.run->task_id
+        LSL     R1,#8                   ; Store PROCID
+        MCR     p15,0,R1,c13,c0,1       ; Write CONTEXTIDR
+
+        LDR     R0,[LR,#TCB_TSTACK]     ; os_tsk.run->tsk_stack
+
+        //Does incoming task have VFP/NEON state in stack?
+        LDRB    R3,[LR,#TCB_STACKF]
+        ANDS    R3, R3, #0x6
+        MRC     p15,0,R1,c1,c0,2        ; Read CPACR
+        ANDEQ   R1,R1,#0xFF0FFFFF       ; Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state
+        ORRNE   R1,R1,#0x00F00000       ; Enable VFP/NEON access if incoming task does have stacked VFP/NEON state
+        MCR     p15,0,R1,c1,c0,2        ; Write CPACR
+        BEQ     no_incoming_vfp
+        ISB                             ; We only need the sync if we enabled, otherwise we will context switch before next VFP/NEON instruction anyway
+        VLDMIA  R0!,{D16-D31}
+        VLDMIA  R0!,{D0-D15}
+        LDR     R2,[R0]
+        VMSR    FPSCR,R2
+        ADD     R0,R0,#8
+
+no_incoming_vfp
+        LDR     R1,[R0,#60]             ; Restore User CPSR
+        MSR     SPSR_CXSF,R1
+        LDMIA   R0!,{R4-R11}            ; Restore User R4-R11
+        ADD     R0,R0,#4                ; Restore User R1-R3,R12
+        LDMIA   R0!,{R1-R3,R12}
+        LDMIA   R0,{LR}^                ; Restore User LR
+        ADD     R0,R0,#4                ; No writeback for load to user LR
+        LDMIA   R0!,{LR}                ; Restore User PC
+        ADD     R0,R0,#4                ; Correct User SP for unstacked user CPSR
+
+        PUSH    {R0}                    ; Push R0 onto stack
+        LDMIA   SP,{SP}^                ; Get R0 off stack into User SP
+        ADD     SP,SP,#4                ; Put SP back
+
+        LDR     R0,[R0,#-32]            ; Restore R0
+
+        PUSH    {R0-R3,R12,LR}
+
+        AND     R12, SP, #4             ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R12             ; Adjust stack
+        PUSH    {R12, LR}               ; Store stack adjustment and dummy LR to SVC stack
+
+        CPSID   i
+        BLX     rt_tsk_unlock
+
+        POP     {R12, LR}               ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R12             ; Unadjust stack
+
+        POP     {R0-R3,R12,LR}
+
+        MOVS    PC,LR                   ; Return from exception
+
+
+        /*------------------- User SVC -------------------------------*/
+
+SVC_User
+        LDR     R12,=SVC_Count
+        LDR     R12,[R12]
+        CMP     R4,R12                  ; Check for overflow
+        BHI     SVC_Done
+
+        LDR     R12,=SVC_Table-4
+        LDR     R12,[R12,R4,LSL #2]     ; Load SVC Function Address
+        MRS     R4,SPSR                 ; Save SPSR
+        PUSH    {R4}                    ; Push R4 so we can use it as a temp
+        AND     R4, SP, #4              ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R4              ; Adjust stack
+        PUSH    {R4, LR}                ; Store stack adjustment and dummy LR
+        BLX     R12                     ; Call SVC Function
+        POP     {R4, LR}                ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R4              ; Unadjust stack
+        POP     {R4}                    ; Restore R4
+        MSR     SPSR_CXSF,R4            ; Restore SPSR
+
+SVC_Done
+        PUSH    {R0-R3,R12,LR}
+
+        PUSH    {R4}                    ; Push R4 so we can use it as a temp
+        AND     R4, SP, #4              ; Ensure stack is 8-byte aligned
+        SUB     SP, SP, R4              ; Adjust stack
+        PUSH    {R4, LR}                ; Store stack adjustment and dummy LR
+
+        CPSID   i
+        BLX     rt_tsk_unlock
+
+        POP     {R4, LR}                ; Get stack adjustment & discard dummy LR
+        ADD     SP, SP, R4              ; Unadjust stack
+        POP     {R4}                    ; Restore R4
+
+        POP     {R0-R3,R12,LR}
+        POP     {R4}
+        RFEFD   SP!                     ; Return from exception
+}
+#pragma pop
+
+#pragma push
+#pragma arm
+__asm void PendSV_Handler (U32 IRQn) {
+    ARM
+
+    IMPORT  rt_tsk_lock
+    IMPORT  IRQNestLevel                ; Flag indicates whether inside an ISR, and the depth of nesting.  0 = not in ISR.
+    IMPORT  seen_id0_active             ; Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s
+
+    ADD     SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
+
+    //Disable systick interrupts, then write EOIR. We want interrupts disabled before we enter the context switcher.
+    PUSH    {R0, R1}
+    BLX     rt_tsk_lock
+    POP     {R0, R1}
+    LDR     R1, =__cpp(&GICInterface_BASE)
+    LDR     R1, [R1, #0]
+    STR     R0, [R1, #0x10]
+
+    ; If it was interrupt ID0, clear the seen flag, otherwise return as normal
+    CMP     R0, #0
+    LDREQ   R1, =seen_id0_active
+    STRBEQ  R0, [R1]                    ; Clear the seen flag, using R0 (which is 0), to save loading another register
+
+    LDR     R0, =IRQNestLevel           ; Get address of nesting counter
+    LDR     R1, [R0]
+    SUB     R1, R1, #1                  ; Decrement nesting counter
+    STR     R1, [R0]
+
+    BLX     __cpp(rt_pop_req)
+
+    POP     {R1, LR}                ; Get stack adjustment & discard dummy LR
+    ADD     SP, SP, R1              ; Unadjust stack
+
+    LDR     R0,[SP,#24]
+    MSR     SPSR_CXSF,R0
+    POP     {R0-R3,R12}             ; Leave SPSR & LR on the stack
+    PUSH    {R4}
+    B       Sys_Switch
+}
+#pragma pop
+
+
+#pragma push
+#pragma arm
+__asm void OS_Tick_Handler (U32 IRQn) {
+    ARM
+
+    IMPORT  rt_tsk_lock
+    IMPORT  IRQNestLevel                ; Flag indicates whether inside an ISR, and the depth of nesting.  0 = not in ISR.
+    IMPORT  seen_id0_active             ; Flag used to workaround GIC 390 errata 733075 - set in startup_Renesas_RZ_A1.s
+
+    ADD     SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
+
+    PUSH    {R0, R1}
+    BLX     rt_tsk_lock
+    POP     {R0, R1}
+    LDR     R1, =__cpp(&GICInterface_BASE)
+    LDR     R1, [R1, #0]
+    STR     R0, [R1, #0x10]
+
+    ; If it was interrupt ID0, clear the seen flag, otherwise return as normal
+    CMP     R0, #0
+    LDREQ   R1, =seen_id0_active
+    STRBEQ  R0, [R1]                    ; Clear the seen flag, using R0 (which is 0), to save loading another register
+
+    LDR     R0, =IRQNestLevel           ; Get address of nesting counter
+    LDR     R1, [R0]
+    SUB     R1, R1, #1                  ; Decrement nesting counter
+    STR     R1, [R0]
+
+    BLX      __cpp(os_tick_irqack)
+    BLX      __cpp(rt_systick)
+
+    POP     {R1, LR}                ; Get stack adjustment & discard dummy LR
+    ADD     SP, SP, R1              ; Unadjust stack
+
+    LDR     R0,[SP,#24]
+    MSR     SPSR_CXSF,R0
+    POP     {R0-R3,R12}             ; Leave SPSR & LR on the stack
+    PUSH    {R4}
+    B       Sys_Switch
+}
+#pragma pop
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/TOOLCHAIN_ARM/SVC_Table.S	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,58 @@
+;/*----------------------------------------------------------------------------
+; *      RL-ARM - RTX
+; *----------------------------------------------------------------------------
+; *      Name:    SVC_TABLE.S
+; *      Purpose: Pre-defined SVC Table for Cortex-M
+; *      Rev.:    V4.70
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+; * All rights reserved.
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *  - Redistributions of source code must retain the above copyright
+; *    notice, this list of conditions and the following disclaimer.
+; *  - Redistributions in binary form must reproduce the above copyright
+; *    notice, this list of conditions and the following disclaimer in the
+; *    documentation and/or other materials provided with the distribution.
+; *  - Neither the name of ARM  nor the names of its contributors may be used
+; *    to endorse or promote products derived from this software without
+; *    specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; * POSSIBILITY OF SUCH DAMAGE.
+; *---------------------------------------------------------------------------*/
+
+
+                AREA    SVC_TABLE, CODE, READONLY
+
+                EXPORT  SVC_Count
+
+SVC_Cnt         EQU    (SVC_End-SVC_Table)/4
+SVC_Count       DCD     SVC_Cnt
+
+; Import user SVC functions here.
+;                IMPORT  __SVC_1
+
+                EXPORT  SVC_Table
+SVC_Table
+; Insert user SVC functions here. SVC 0 used by RTL Kernel.
+;                DCD     __SVC_1                 ; InitMemorySubsystem
+
+SVC_End
+
+                END
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/cmsis_os.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,840 @@
+/* ----------------------------------------------------------------------
+ * $Date:        5. February 2013
+ * $Revision:    V1.02
+ *
+ * Project:      CMSIS-RTOS API
+ * Title:        cmsis_os.h RTX header file
+ *
+ * Version 0.02
+ *    Initial Proposal Phase
+ * Version 0.03
+ *    osKernelStart added, optional feature: main started as thread
+ *    osSemaphores have standard behavior
+ *    osTimerCreate does not start the timer, added osTimerStart
+ *    osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ *    Support for C++ interface
+ *     - const attribute removed from the osXxxxDef_t typedef's
+ *     - const attribute added to the osXxxxDef macros
+ *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ *    Added: osKernelInitialize
+ * Version 1.02
+ *    Control functions for short timeouts in microsecond resolution:
+ *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
+ *    Removed: osSignalGet 
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2013 ARM LIMITED
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/**
+\page cmsis_os_h Header File Template: cmsis_os.h
+
+The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).
+Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents
+its implementation.
+
+The file cmsis_os.h contains:
+ - CMSIS-RTOS API function definitions
+ - struct definitions for parameters and return types
+ - status and priority values used by CMSIS-RTOS API functions
+ - macros for defining threads and other kernel objects
+
+
+<b>Name conventions and header file modifications</b>
+
+All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
+Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
+All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.
+
+Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.
+These definitions can be specific to the underlying RTOS kernel.
+
+Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
+compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.
+
+
+<b>Function calls from interrupt service routines</b>
+
+The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):
+  - \ref osSignalSet
+  - \ref osSemaphoreRelease
+  - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree
+  - \ref osMessagePut, \ref osMessageGet
+  - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree
+
+Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
+from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
+
+Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
+If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive.
+
+
+<b>Define and reference object definitions</b>
+
+With <b>\#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header file
+that is used throughout a project as shown below:
+
+<i>Header File</i>
+\code
+#include <cmsis_os.h>                                         // CMSIS RTOS header file
+
+// Thread definition
+extern void thread_sample (void const *argument);             // function prototype
+osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
+
+// Pool definition
+osPoolDef(MyPool, 10, long);
+\endcode
+
+
+This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is
+present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
+used throughout the whole project.
+
+<i>Example</i>
+\code
+#include "osObjects.h"     // Definition of the CMSIS-RTOS objects
+\endcode
+
+\code
+#define osObjectExternal   // Objects will be defined as external symbols
+#include "osObjects.h"     // Reference to the CMSIS-RTOS objects
+\endcode
+
+*/
+
+#ifndef _CMSIS_OS_H
+#define _CMSIS_OS_H
+
+/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
+#define osCMSIS           0x10002      ///< API version (main [31:16] .sub [15:0])
+
+/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
+#define osCMSIS_RTX     ((4<<16)|74)   ///< RTOS identification and version (main [31:16] .sub [15:0])
+
+/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
+#define osKernelSystemId "RTX V4.74"   ///< RTOS identification string
+
+#define CMSIS_OS_RTX
+#define CMSIS_OS_RTX_CA          /* new define for Coretex-A */
+
+// The stack space occupied is mainly dependent on the underling C standard library
+#if defined(TOOLCHAIN_GCC) || defined(TOOLCHAIN_ARM_STD) || defined(TOOLCHAIN_IAR)
+#    define WORDS_STACK_SIZE   512
+#elif defined(TOOLCHAIN_ARM_MICRO)
+#    define WORDS_STACK_SIZE   128
+#endif
+
+#define DEFAULT_STACK_SIZE         (WORDS_STACK_SIZE*4)
+
+/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
+#define osFeature_MainThread   1       ///< main thread      1=main can be thread, 0=not available
+#define osFeature_Pool         1       ///< Memory Pools:    1=available, 0=not available
+#define osFeature_MailQ        1       ///< Mail Queues:     1=available, 0=not available
+#define osFeature_MessageQ     1       ///< Message Queues:  1=available, 0=not available
+#define osFeature_Signals      16      ///< maximum number of Signal Flags available per thread
+#define osFeature_Semaphore    65535   ///< maximum count for \ref osSemaphoreCreate function
+#define osFeature_Wait         0       ///< osWait function: 1=available, 0=not available
+#define osFeature_SysTick      1       ///< osKernelSysTick functions: 1=available, 0=not available
+
+#if defined (__CC_ARM)
+#define os_InRegs __value_in_regs      // Compiler specific: force struct in registers
+#else
+#define os_InRegs
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+
+// ==== Enumeration, structures, defines ====
+
+/// Priority used for thread control.
+/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osPriorityIdle          = -3,          ///< priority: idle (lowest)
+  osPriorityLow           = -2,          ///< priority: low
+  osPriorityBelowNormal   = -1,          ///< priority: below normal
+  osPriorityNormal        =  0,          ///< priority: normal (default)
+  osPriorityAboveNormal   = +1,          ///< priority: above normal
+  osPriorityHigh          = +2,          ///< priority: high
+  osPriorityRealtime      = +3,          ///< priority: realtime (highest)
+  osPriorityError         =  0x84        ///< system cannot determine priority or thread has illegal priority
+} osPriority;
+
+/// Timeout value.
+/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
+#define osWaitForever     0xFFFFFFFF     ///< wait forever timeout value
+
+/// Status code values returned by CMSIS-RTOS functions.
+/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osOK                    =     0,       ///< function completed; no error or event occurred.
+  osEventSignal           =  0x08,       ///< function completed; signal event occurred.
+  osEventMessage          =  0x10,       ///< function completed; message event occurred.
+  osEventMail             =  0x20,       ///< function completed; mail event occurred.
+  osEventTimeout          =  0x40,       ///< function completed; timeout occurred.
+  osErrorParameter        =  0x80,       ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
+  osErrorResource         =  0x81,       ///< resource not available: a specified resource was not available.
+  osErrorTimeoutResource  =  0xC1,       ///< resource not available within given time: a specified resource was not available within the timeout period.
+  osErrorISR              =  0x82,       ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
+  osErrorISRRecursive     =  0x83,       ///< function called multiple times from ISR with same object.
+  osErrorPriority         =  0x84,       ///< system cannot determine priority or thread has illegal priority.
+  osErrorNoMemory         =  0x85,       ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
+  osErrorValue            =  0x86,       ///< value of a parameter is out of range.
+  osErrorOS               =  0xFF,       ///< unspecified RTOS error: run-time error but no other error message fits.
+  os_status_reserved      =  0x7FFFFFFF  ///< prevent from enum down-size compiler optimization.
+} osStatus;
+
+
+/// Timer type value for the timer definition.
+/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
+typedef enum  {
+  osTimerOnce             =     0,       ///< one-shot timer
+  osTimerPeriodic         =     1        ///< repeating timer
+} os_timer_type;
+
+/// Entry point of a thread.
+/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
+typedef void (*os_pthread) (void const *argument);
+
+/// Entry point of a timer call back function.
+/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
+typedef void (*os_ptimer) (void const *argument);
+
+// >>> the following data type definitions may shall adapted towards a specific RTOS
+
+/// Thread ID identifies the thread (pointer to a thread control block).
+/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_cb *osThreadId;
+
+/// Timer ID identifies the timer (pointer to a timer control block).
+/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_cb *osTimerId;
+
+/// Mutex ID identifies the mutex (pointer to a mutex control block).
+/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_cb *osMutexId;
+
+/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
+/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_cb *osSemaphoreId;
+
+/// Pool ID identifies the memory pool (pointer to a memory pool control block).
+/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_cb *osPoolId;
+
+/// Message ID identifies the message queue (pointer to a message queue control block).
+/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_cb *osMessageQId;
+
+/// Mail ID identifies the mail queue (pointer to a mail queue control block).
+/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_cb *osMailQId;
+
+
+/// Thread Definition structure contains startup information of a thread.
+/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_thread_def  {
+  os_pthread               pthread;    ///< start address of thread function
+  osPriority             tpriority;    ///< initial thread priority
+  uint32_t               instances;    ///< maximum number of instances of that thread function
+  uint32_t               stacksize;    ///< stack size requirements in bytes; 0 is default stack size
+#ifdef __MBED_CMSIS_RTOS_CA9
+  uint32_t               *stack_pointer;  ///< pointer to the stack memory block
+#endif
+} osThreadDef_t;
+
+/// Timer Definition structure contains timer parameters.
+/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_timer_def  {
+  os_ptimer                 ptimer;    ///< start address of a timer function
+  void                      *timer;    ///< pointer to internal data
+} osTimerDef_t;
+
+/// Mutex Definition structure contains setup information for a mutex.
+/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mutex_def  {
+  void                      *mutex;    ///< pointer to internal data
+} osMutexDef_t;
+
+/// Semaphore Definition structure contains setup information for a semaphore.
+/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_semaphore_def  {
+  void                  *semaphore;    ///< pointer to internal data
+} osSemaphoreDef_t;
+
+/// Definition structure for memory block allocation.
+/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_pool_def  {
+  uint32_t                 pool_sz;    ///< number of items (elements) in the pool
+  uint32_t                 item_sz;    ///< size of an item
+  void                       *pool;    ///< pointer to memory for pool
+} osPoolDef_t;
+
+/// Definition structure for message queue.
+/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_messageQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  void                       *pool;    ///< memory array for messages
+} osMessageQDef_t;
+
+/// Definition structure for mail queue.
+/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
+typedef struct os_mailQ_def  {
+  uint32_t                queue_sz;    ///< number of elements in the queue
+  uint32_t                 item_sz;    ///< size of an item
+  void                       *pool;    ///< memory array for mail
+} osMailQDef_t;
+
+/// Event structure contains detailed information about an event.
+/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
+///       However the struct may be extended at the end.
+typedef struct  {
+  osStatus                 status;     ///< status code: event or error information
+  union  {
+    uint32_t                    v;     ///< message as 32-bit value
+    void                       *p;     ///< message or mail as void pointer
+    int32_t               signals;     ///< signal flags
+  } value;                             ///< event value
+  union  {
+    osMailQId             mail_id;     ///< mail id obtained by \ref osMailCreate
+    osMessageQId       message_id;     ///< message id obtained by \ref osMessageCreate
+  } def;                               ///< event definition
+} osEvent;
+
+
+//  ==== Kernel Control Functions ====
+
+/// Initialize the RTOS Kernel for creating objects.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
+osStatus osKernelInitialize (void);
+
+/// Start the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
+osStatus osKernelStart (void);
+
+/// Check if the RTOS kernel is already started.
+/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+int32_t osKernelRunning(void);
+
+#if (defined (osFeature_SysTick)  &&  (osFeature_SysTick != 0))     // System Timer available
+
+extern uint32_t const os_tickfreq;
+extern uint16_t const os_tickus_i;
+extern uint16_t const os_tickus_f;
+
+/// Get the RTOS kernel system timer counter.
+/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
+/// \return RTOS kernel system timer as 32-bit value 
+uint32_t osKernelSysTick (void);
+
+/// The RTOS kernel system timer frequency in Hz.
+/// \note Reflects the system timer setting and is typically defined in a configuration file.
+#define osKernelSysTickFrequency os_tickfreq
+
+/// Convert a microseconds value to a RTOS kernel system timer value.
+/// \param         microsec     time value in microseconds.
+/// \return time value normalized to the \ref osKernelSysTickFrequency
+/*
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
+*/
+#define osKernelSysTickMicroSec(microsec) ((microsec * os_tickus_i) + ((microsec * os_tickus_f) >> 16))
+
+#endif    // System Timer available
+
+//  ==== Thread Management ====
+
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param         name         name of the thread function.
+/// \param         priority     initial priority of the thread function.
+/// \param         instances    number of possible thread instances.
+/// \param         stacksz      stack size (in bytes) requirements for the thread function.
+/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osThreadDef(name, priority, instances, stacksz)  \
+extern const osThreadDef_t os_thread_def_##name
+#else                            // define the object
+#ifdef __MBED_CMSIS_RTOS_CA9
+#define osThreadDef(name, priority, stacksz)  \
+uint32_t os_thread_def_stack_##name [stacksz / sizeof(uint32_t)]; \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), (priority), 1, (stacksz), (os_thread_def_stack_##name) }
+#else
+#define osThreadDef(name, priority, instances, stacksz)  \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), (priority), (instances), (stacksz)  }
+#endif
+#endif
+
+/// Access a Thread definition.
+/// \param         name          name of the thread definition object.
+/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osThread(name)  \
+&os_thread_def_##name
+
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in]     thread_def    thread definition referenced with \ref osThread.
+/// \param[in]     argument      pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
+osThreadId osThreadGetId (void);
+
+/// Terminate execution of a thread and remove it from Active Threads.
+/// \param[in]     thread_id   thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
+osStatus osThreadTerminate (osThreadId thread_id);
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
+osStatus osThreadYield (void);
+
+/// Change priority of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     priority      new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+
+/// Get current priority of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the thread function.
+/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
+osPriority osThreadGetPriority (osThreadId thread_id);
+
+#ifdef __MBED_CMSIS_RTOS_CA9
+/// Get current thread state.
+uint8_t osThreadGetState (osThreadId thread_id);
+#endif
+
+//  ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay).
+/// \param[in]     millisec      time delay value
+/// \return status code that indicates the execution status of the function.
+osStatus osDelay (uint32_t millisec);
+
+#if (defined (osFeature_Wait)  &&  (osFeature_Wait != 0))     // Generic Wait available
+
+/// Wait for Signal, Message, Mail, or Timeout.
+/// \param[in] millisec          timeout value or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
+os_InRegs osEvent osWait (uint32_t millisec);
+
+#endif  // Generic Wait available
+
+
+//  ==== Timer Management Functions ====
+/// Define a Timer object.
+/// \param         name          name of the timer object.
+/// \param         function      name of the timer call back function.
+/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osTimerDef(name, function)  \
+extern const osTimerDef_t os_timer_def_##name
+#else                            // define the object
+#define osTimerDef(name, function)  \
+uint32_t os_timer_cb_##name[5]; \
+const osTimerDef_t os_timer_def_##name = \
+{ (function), (os_timer_cb_##name) }
+#endif
+
+/// Access a Timer definition.
+/// \param         name          name of the timer object.
+/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osTimer(name) \
+&os_timer_def_##name
+
+/// Create a timer.
+/// \param[in]     timer_def     timer object referenced with \ref osTimer.
+/// \param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in]     argument      argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
+
+/// Start or restart a timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \param[in]     millisec      time delay value of the timer.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+
+/// Stop the timer.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
+osStatus osTimerStop (osTimerId timer_id);
+
+/// Delete a timer that was created by \ref osTimerCreate.
+/// \param[in]     timer_id      timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
+osStatus osTimerDelete (osTimerId timer_id);
+
+
+//  ==== Signal Management ====
+
+/// Set the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
+int32_t osSignalSet (osThreadId thread_id, int32_t signals);
+
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in]     thread_id     thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in]     signals       specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
+int32_t osSignalClear (osThreadId thread_id, int32_t signals);
+
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return event flag information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
+os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
+
+
+//  ==== Mutex Management ====
+
+/// Define a Mutex.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMutexDef(name)  \
+extern const osMutexDef_t os_mutex_def_##name
+#else                            // define the object
+#define osMutexDef(name)  \
+uint32_t os_mutex_cb_##name[4] = { 0 }; \
+const osMutexDef_t os_mutex_def_##name = { (os_mutex_cb_##name) }
+#endif
+
+/// Access a Mutex definition.
+/// \param         name          name of the mutex object.
+/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMutex(name)  \
+&os_mutex_def_##name
+
+/// Create and Initialize a Mutex object.
+/// \param[in]     mutex_def     mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
+
+/// Wait until a Mutex becomes available.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+
+/// Release a Mutex that was obtained by \ref osMutexWait.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
+osStatus osMutexRelease (osMutexId mutex_id);
+
+/// Delete a Mutex that was created by \ref osMutexCreate.
+/// \param[in]     mutex_id      mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
+osStatus osMutexDelete (osMutexId mutex_id);
+
+
+//  ==== Semaphore Management Functions ====
+
+#if (defined (osFeature_Semaphore)  &&  (osFeature_Semaphore != 0))     // Semaphore available
+
+/// Define a Semaphore object.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osSemaphoreDef(name)  \
+extern const osSemaphoreDef_t os_semaphore_def_##name
+#else                            // define the object
+#define osSemaphoreDef(name)  \
+uint32_t os_semaphore_cb_##name[2] = { 0 }; \
+const osSemaphoreDef_t os_semaphore_def_##name = { (os_semaphore_cb_##name) }
+#endif
+
+/// Access a Semaphore definition.
+/// \param         name          name of the semaphore object.
+/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osSemaphore(name)  \
+&os_semaphore_def_##name
+
+/// Create and Initialize a Semaphore object used for managing resources.
+/// \param[in]     semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in]     count         number of available resources.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
+
+/// Wait until a Semaphore token becomes available.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+
+/// Release a Semaphore token.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+
+/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
+/// \param[in]     semaphore_id  semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
+
+#endif     // Semaphore available
+
+
+//  ==== Memory Pool Management Functions ====
+
+#if (defined (osFeature_Pool)  &&  (osFeature_Pool != 0))  // Memory Pool Management available
+
+/// \brief Define a Memory Pool.
+/// \param         name          name of the memory pool.
+/// \param         no            maximum number of blocks (objects) in the memory pool.
+/// \param         type          data type of a single block (object).
+/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osPoolDef(name, no, type)   \
+extern const osPoolDef_t os_pool_def_##name
+#else                            // define the object
+#define osPoolDef(name, no, type)   \
+uint32_t os_pool_m_##name[3+((sizeof(type)+3)/4)*(no)]; \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), (os_pool_m_##name) }
+#endif
+
+/// \brief Access a Memory Pool definition.
+/// \param         name          name of the memory pool
+/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osPool(name) \
+&os_pool_def_##name
+
+/// Create and Initialize a memory pool.
+/// \param[in]     pool_def      memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
+osPoolId osPoolCreate (const osPoolDef_t *pool_def);
+
+/// Allocate a memory block from a memory pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolAlloc (osPoolId pool_id);
+
+/// Allocate a memory block from a memory pool and set memory block to zero.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
+void *osPoolCAlloc (osPoolId pool_id);
+
+/// Return an allocated memory block back to a specific memory pool.
+/// \param[in]     pool_id       memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in]     block         address of the allocated memory block that is returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+
+#endif   // Memory Pool Management available
+
+
+//  ==== Message Queue Management Functions ====
+
+#if (defined (osFeature_MessageQ)  &&  (osFeature_MessageQ != 0))     // Message Queues available
+
+/// \brief Create a Message Queue Definition.
+/// \param         name          name of the queue.
+/// \param         queue_sz      maximum number of messages in the queue.
+/// \param         type          data type of a single message element (for debugger).
+/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMessageQDef(name, queue_sz, type)   \
+extern const osMessageQDef_t os_messageQ_def_##name
+#else                            // define the object
+#define osMessageQDef(name, queue_sz, type)   \
+uint32_t os_messageQ_q_##name[4+(queue_sz)] = { 0 }; \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), (os_messageQ_q_##name) }
+#endif
+
+/// \brief Access a Message Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+
+/// Create and Initialize a Message Queue.
+/// \param[in]     queue_def     queue definition referenced with \ref osMessageQ.
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+
+/// Put a Message to a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     info          message information.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+
+/// Get a Message or Wait for a Message from a Queue.
+/// \param[in]     queue_id      message queue ID obtained with \ref osMessageCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out.
+/// \return event information that includes status code.
+/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
+os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+
+#endif     // Message Queues available
+
+
+//  ==== Mail Queue Management Functions ====
+
+#if (defined (osFeature_MailQ)  &&  (osFeature_MailQ != 0))     // Mail Queues available
+
+/// \brief Create a Mail Queue Definition.
+/// \param         name          name of the queue
+/// \param         queue_sz      maximum number of messages in queue
+/// \param         type          data type of a single message element
+/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal)  // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern const osMailQDef_t os_mailQ_def_##name
+#else                            // define the object
+#define osMailQDef(name, queue_sz, type) \
+uint32_t os_mailQ_q_##name[4+(queue_sz)] = { 0 }; \
+uint32_t os_mailQ_m_##name[3+((sizeof(type)+3)/4)*(queue_sz)]; \
+void *   os_mailQ_p_##name[2] = { (os_mailQ_q_##name), os_mailQ_m_##name }; \
+const osMailQDef_t os_mailQ_def_##name =  \
+{ (queue_sz), sizeof(type), (os_mailQ_p_##name) }
+#endif
+
+/// \brief Access a Mail Queue Definition.
+/// \param         name          name of the queue
+/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
+///       macro body is implementation specific in every CMSIS-RTOS.
+#define osMailQ(name)  \
+&os_mailQ_def_##name
+
+/// Create and Initialize mail queue.
+/// \param[in]     queue_def     reference to the mail queue definition obtain with \ref osMailQ
+/// \param[in]     thread_id     thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
+
+/// Allocate a memory block from a mail.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Allocate a memory block from a mail and set memory block to zero.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Put a mail to a queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
+osStatus osMailPut (osMailQId queue_id, void *mail);
+
+/// Get a mail from a queue.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     millisec      timeout value or 0 in case of no time-out
+/// \return event that contains mail information or error code.
+/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
+os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+
+/// Free a memory block from a mail.
+/// \param[in]     queue_id      mail queue ID obtained with \ref osMailCreate.
+/// \param[in]     mail          pointer to the memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+
+#endif  // Mail Queues available
+
+
+//  ==== RTX Extensions ====
+
+/// os_suspend: http://www.keil.com/support/man/docs/rlarm/rlarm_os_suspend.htm
+uint32_t os_suspend (void);
+
+/// os_resume: http://www.keil.com/support/man/docs/rlarm/rlarm_os_resume.htm
+void os_resume (uint32_t sleep_time);
+
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif  // _CMSIS_OS_H
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_CMSIS.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,2187 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    rt_CMSIS.c
+ *      Purpose: CMSIS RTOS API
+ *      Rev.:    V4.74
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#define __CMSIS_GENERIC
+
+#if defined (__CORTEX_M4) || defined (__CORTEX_M4F)
+  #include "core_cm4.h"
+#elif defined (__CORTEX_M3)
+  #include "core_cm3.h"
+#elif defined (__CORTEX_M0)
+  #include "core_cm0.h"
+#elif defined (__CORTEX_A9)
+  #include "core_ca9.h"
+#else
+  #error "Missing __CORTEX_xx definition"
+#endif
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_Task.h"
+#include "rt_Event.h"
+#include "rt_List.h"
+#include "rt_Time.h"
+#include "rt_Mutex.h"
+#include "rt_Semaphore.h"
+#include "rt_Mailbox.h"
+#include "rt_MemBox.h"
+#include "rt_Memory.h"
+#include "rt_HAL_CM.h"
+
+#define os_thread_cb OS_TCB
+
+#include "cmsis_os.h"
+
+#if (osFeature_Signals != 16)
+#error Invalid "osFeature_Signals" value!
+#endif
+#if (osFeature_Semaphore > 65535)
+#error Invalid "osFeature_Semaphore" value!
+#endif
+#if (osFeature_Wait != 0)
+#error osWait not supported!
+#endif
+
+
+// ==== Enumeration, structures, defines ====
+
+// Service Calls defines
+
+#if defined (__CC_ARM)          /* ARM Compiler */
+
+#define __NO_RETURN __declspec(noreturn)
+
+#define osEvent_type       osEvent
+#define osEvent_ret_status ret
+#define osEvent_ret_value  ret
+#define osEvent_ret_msg    ret
+#define osEvent_ret_mail   ret
+
+#define osCallback_type    osCallback
+#define osCallback_ret     ret
+
+#define SVC_0_1(f,t,...)                                                       \
+__svc_indirect(0) t  _##f (t(*)());                                            \
+                  t     f (void);                                              \
+__attribute__((always_inline))                                                 \
+static __inline   t __##f (void) {                                             \
+  return _##f(f);                                                              \
+}
+
+#define SVC_1_0(f,t,t1,...)                                                    \
+__svc_indirect(0) t  _##f (t(*)(t1),t1);                                       \
+                  t     f (t1 a1);                                             \
+__attribute__((always_inline))                                                 \
+static __inline   t __##f (t1 a1) {                                            \
+  _##f(f,a1);                                                                  \
+}
+
+#define SVC_1_1(f,t,t1,...)                                                    \
+__svc_indirect(0) t  _##f (t(*)(t1),t1);                                       \
+                  t     f (t1 a1);                                             \
+__attribute__((always_inline))                                                 \
+static __inline   t __##f (t1 a1) {                                            \
+  return _##f(f,a1);                                                           \
+}
+
+#define SVC_2_1(f,t,t1,t2,...)                                                 \
+__svc_indirect(0) t  _##f (t(*)(t1,t2),t1,t2);                                 \
+                  t     f (t1 a1, t2 a2);                                      \
+__attribute__((always_inline))                                                 \
+static __inline   t __##f (t1 a1, t2 a2) {                                     \
+  return _##f(f,a1,a2);                                                        \
+}
+
+#define SVC_3_1(f,t,t1,t2,t3,...)                                              \
+__svc_indirect(0) t  _##f (t(*)(t1,t2,t3),t1,t2,t3);                           \
+                  t     f (t1 a1, t2 a2, t3 a3);                               \
+__attribute__((always_inline))                                                 \
+static __inline   t __##f (t1 a1, t2 a2, t3 a3) {                              \
+  return _##f(f,a1,a2,a3);                                                     \
+}
+
+#define SVC_4_1(f,t,t1,t2,t3,t4,...)                                           \
+__svc_indirect(0) t  _##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4);                     \
+                  t     f (t1 a1, t2 a2, t3 a3, t4 a4);                        \
+__attribute__((always_inline))                                                 \
+static __inline   t __##f (t1 a1, t2 a2, t3 a3, t4 a4) {                       \
+  return _##f(f,a1,a2,a3,a4);                                                  \
+}
+
+#define SVC_1_2 SVC_1_1
+#define SVC_1_3 SVC_1_1
+#define SVC_2_3 SVC_2_1
+
+#elif defined (__GNUC__)        /* GNU Compiler */
+
+#define __NO_RETURN __attribute__((noreturn))
+
+typedef uint32_t __attribute__((vector_size(8)))  ret64;
+typedef uint32_t __attribute__((vector_size(16))) ret128;
+
+#define RET_pointer    __r0
+#define RET_int32_t    __r0
+#define RET_uint32_t   __r0
+#define RET_osStatus   __r0
+#define RET_osPriority __r0
+#define RET_osEvent    {(osStatus)__r0, {(uint32_t)__r1}, {(void *)__r2}}
+#define RET_osCallback {(void *)__r0, (void *)__r1}
+
+#if defined (__ARM_PCS_VFP)
+
+#define osEvent_type        void
+#define osEvent_ret_status {  __asm ("MOV r0, %0;"      \
+                                     : /* no outputs */ \
+                                     : "r"(ret.status)  \
+                                     : "r0"             \
+                                     );                 \
+                           }
+#define osEvent_ret_value  {  __asm ("MOV r1, %0;"         \
+                                     "MOV r0, %1;"         \
+                                     :   /* no outputs */  \
+                                     :   "r"(ret.value.v), \
+                                         "r"(ret.status)   \
+                                     : "r0", "r1"          \
+                                     );                    \
+                           }
+#define osEvent_ret_msg    {  __asm ("MOV r2, %0;"                \
+                                     "MOV r1, %1;"                \
+                                     "MOV r0, %2;"                \
+                                     : /* no outputs */           \
+                                     :   "r"(ret.def.message_id), \
+                                         "r"(ret.value.v),        \
+                                         "r"(ret.status)          \
+                                     : "r0", "r1" , "r2"          \
+                                     );                           \
+                           }
+
+#define osEvent_ret_mail   {  __asm ("MOV r2, %0;"             \
+                                     "MOV r1, %1;"             \
+                                     "MOV r0, %2;"             \
+                                     : /* no outputs */        \
+                                     :   "r"(ret.def.mail_id), \
+                                         "r"(ret.value.v),     \
+                                         "r"(ret.status)       \
+                                     : "r0", "r1" , "r2"       \
+                                     );                        \
+                           }
+
+#define osCallback_type     void
+#define osCallback_ret     {  __asm ("MOV r1, %0;"      \
+                                     "MOV r0, %1;"      \
+                                     : /* no outputs */ \
+                                     : "r"(ret.arg),    \
+                                       "r"(ret.fp)      \
+                                     : "r0", "r1"       \
+                                     );                 \
+                           }
+
+#else /* defined (__ARM_PCS_VFP) */
+
+#define osEvent_type        ret128
+#define osEvent_ret_status (ret128){ret.status}
+#define osEvent_ret_value  (ret128){ret.status, ret.value.v}
+#define osEvent_ret_msg    (ret128){ret.status, ret.value.v, (uint32_t)ret.def.message_id}
+#define osEvent_ret_mail   (ret128){ret.status, ret.value.v, (uint32_t)ret.def.mail_id}
+
+#define osCallback_type     ret64
+#define osCallback_ret     (ret64) {(uint32_t)ret.fp, (uint32_t)ret.arg}
+
+#endif /* defined (__ARM_PCS_VFP) */
+
+#define SVC_ArgN(n) \
+  register int __r##n __asm("r"#n);
+
+#define SVC_ArgR(n,t,a) \
+  register t   __r##n __asm("r"#n) = a;
+
+#define SVC_Arg0()                                                             \
+  SVC_ArgN(0)                                                                  \
+  SVC_ArgN(1)                                                                  \
+  SVC_ArgN(2)                                                                  \
+  SVC_ArgN(3)
+
+#define SVC_Arg1(t1)                                                           \
+  SVC_ArgR(0,t1,a1)                                                            \
+  SVC_ArgN(1)                                                                  \
+  SVC_ArgN(2)                                                                  \
+  SVC_ArgN(3)
+
+#define SVC_Arg2(t1,t2)                                                        \
+  SVC_ArgR(0,t1,a1)                                                            \
+  SVC_ArgR(1,t2,a2)                                                            \
+  SVC_ArgN(2)                                                                  \
+  SVC_ArgN(3)
+
+#define SVC_Arg3(t1,t2,t3)                                                     \
+  SVC_ArgR(0,t1,a1)                                                            \
+  SVC_ArgR(1,t2,a2)                                                            \
+  SVC_ArgR(2,t3,a3)                                                            \
+  SVC_ArgN(3)
+
+#define SVC_Arg4(t1,t2,t3,t4)                                                  \
+  SVC_ArgR(0,t1,a1)                                                            \
+  SVC_ArgR(1,t2,a2)                                                            \
+  SVC_ArgR(2,t3,a3)                                                            \
+  SVC_ArgR(3,t4,a4)
+
+#if (defined (__CORTEX_M0))
+#define SVC_Call(f)                                                            \
+  __asm volatile                                                                 \
+  (                                                                            \
+    "ldr r7,="#f"\n\t"                                                         \
+    "mov r12,r7\n\t"                                                           \
+    "svc 0"                                                                    \
+    :               "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3)         \
+    :                "r" (__r0),  "r" (__r1),  "r" (__r2),  "r" (__r3)         \
+    : "r7", "r12", "lr", "cc"                                                  \
+  );
+#else
+#define SVC_Call(f)                                                            \
+  __asm volatile                                                                 \
+  (                                                                            \
+    "ldr r12,="#f"\n\t"                                                        \
+    "svc 0"                                                                    \
+    :               "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3)         \
+    :                "r" (__r0),  "r" (__r1),  "r" (__r2),  "r" (__r3)         \
+    : "r12", "lr", "cc"                                                        \
+  );
+#endif
+
+#define SVC_0_1(f,t,rv)                                                        \
+__attribute__((always_inline))                                                 \
+static inline  t __##f (void) {                                                \
+  SVC_Arg0();                                                                  \
+  SVC_Call(f);                                                                 \
+  return (t) rv;                                                               \
+}
+
+#define SVC_1_0(f,t,t1)                                                        \
+__attribute__((always_inline))                                                 \
+static inline  t __##f (t1 a1) {                                               \
+  SVC_Arg1(t1);                                                                \
+  SVC_Call(f);                                                                 \
+}
+
+#define SVC_1_1(f,t,t1,rv)                                                     \
+__attribute__((always_inline))                                                 \
+static inline  t __##f (t1 a1) {                                               \
+  SVC_Arg1(t1);                                                                \
+  SVC_Call(f);                                                                 \
+  return (t) rv;                                                               \
+}
+
+#define SVC_2_1(f,t,t1,t2,rv)                                                  \
+__attribute__((always_inline))                                                 \
+static inline  t __##f (t1 a1, t2 a2) {                                        \
+  SVC_Arg2(t1,t2);                                                             \
+  SVC_Call(f);                                                                 \
+  return (t) rv;                                                               \
+}
+
+#define SVC_3_1(f,t,t1,t2,t3,rv)                                               \
+__attribute__((always_inline))                                                 \
+static inline  t __##f (t1 a1, t2 a2, t3 a3) {                                 \
+  SVC_Arg3(t1,t2,t3);                                                          \
+  SVC_Call(f);                                                                 \
+  return (t) rv;                                                               \
+}
+
+#define SVC_4_1(f,t,t1,t2,t3,t4,rv)                                            \
+__attribute__((always_inline))                                                 \
+static inline  t __##f (t1 a1, t2 a2, t3 a3, t4 a4) {                          \
+  SVC_Arg4(t1,t2,t3,t4);                                                       \
+  SVC_Call(f);                                                                 \
+  return (t) rv;                                                               \
+}
+
+#define SVC_1_2 SVC_1_1
+#define SVC_1_3 SVC_1_1
+#define SVC_2_3 SVC_2_1
+
+#elif defined (__ICCARM__)      /* IAR Compiler */
+
+#define __NO_RETURN __noreturn
+
+#define RET_osEvent        "=r"(ret.status), "=r"(ret.value), "=r"(ret.def)
+#define RET_osCallback     "=r"(ret.fp), "=r"(ret.arg)
+
+#define osEvent_type       osEvent
+#define osEvent_ret_status ret
+#define osEvent_ret_value  ret
+#define osEvent_ret_msg    ret
+#define osEvent_ret_mail   ret
+
+#define osCallback_type    uint64_t
+#define osCallback_ret     ((uint64_t)ret.fp | ((uint64_t)ret.arg)<<32)
+
+#define SVC_Setup(f)                                                           \
+  __asm(                                                                         \
+    "mov r12,%0\n"                                                             \
+    :: "r"(&f): "r12"                                                          \
+  );
+
+#define SVC_Ret3()                                                             \
+  __asm(                                                                         \
+    "ldr r0,[sp,#0]\n"                                                         \
+    "ldr r1,[sp,#4]\n"                                                         \
+    "ldr r2,[sp,#8]\n"                                                         \
+  );
+
+#define SVC_0_1(f,t,...)                                                       \
+t f (void);                                                                    \
+_Pragma("swi_number=0") __swi t _##f (void);                                   \
+static inline t __##f (void) {                                                 \
+  SVC_Setup(f);                                                                \
+  return _##f();                                                               \
+}
+
+#define SVC_1_0(f,t,t1,...)                                                    \
+t f (t1 a1);                                                                   \
+_Pragma("swi_number=0") __swi t _##f (t1 a1);                                  \
+static inline t __##f (t1 a1) {                                                \
+  SVC_Setup(f);                                                                \
+  _##f(a1);                                                                    \
+}
+
+#define SVC_1_1(f,t,t1,...)                                                    \
+t f (t1 a1);                                                                   \
+_Pragma("swi_number=0") __swi t _##f (t1 a1);                                  \
+static inline t __##f (t1 a1) {                                                \
+  SVC_Setup(f);                                                                \
+  return _##f(a1);                                                             \
+}
+
+#define SVC_2_1(f,t,t1,t2,...)                                                 \
+t f (t1 a1, t2 a2);                                                            \
+_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2);                           \
+static inline t __##f (t1 a1, t2 a2) {                                         \
+  SVC_Setup(f);                                                                \
+  return _##f(a1,a2);                                                          \
+}
+
+#define SVC_3_1(f,t,t1,t2,t3,...)                                              \
+t f (t1 a1, t2 a2, t3 a3);                                                     \
+_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3);                    \
+static inline t __##f (t1 a1, t2 a2, t3 a3) {                                  \
+  SVC_Setup(f);                                                                \
+  return _##f(a1,a2,a3);                                                       \
+}
+
+#define SVC_4_1(f,t,t1,t2,t3,t4,...)                                           \
+t f (t1 a1, t2 a2, t3 a3, t4 a4);                                              \
+_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3, t4 a4);             \
+static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) {                           \
+  SVC_Setup(f);                                                                \
+  return _##f(a1,a2,a3,a4);                                                    \
+}
+
+#define SVC_1_2(f,t,t1,rr)                                                     \
+uint64_t f (t1 a1);                                                            \
+_Pragma("swi_number=0") __swi uint64_t _##f (t1 a1);                           \
+static inline t __##f (t1 a1) {                                                \
+  t ret;                                                                       \
+  SVC_Setup(f);                                                                \
+  _##f(a1);                                                                    \
+  __asm("" : rr : :);                                                            \
+  return ret;                                                                  \
+}
+
+#define SVC_1_3(f,t,t1,rr)                                                     \
+t f (t1 a1);                                                                   \
+void f##_ (t1 a1) {                                                            \
+  f(a1);                                                                       \
+  SVC_Ret3();                                                                  \
+}                                                                              \
+_Pragma("swi_number=0") __swi void _##f (t1 a1);                               \
+static inline t __##f (t1 a1) {                                                \
+  t ret;                                                                       \
+  SVC_Setup(f##_);                                                             \
+  _##f(a1);                                                                    \
+  __asm("" : rr : :);                                                            \
+  return ret;                                                                  \
+}
+
+#define SVC_2_3(f,t,t1,t2,rr)                                                  \
+t f (t1 a1, t2 a2);                                                            \
+void f##_ (t1 a1, t2 a2) {                                                     \
+  f(a1,a2);                                                                    \
+  SVC_Ret3();                                                                  \
+}                                                                              \
+_Pragma("swi_number=0") __swi void _##f (t1 a1, t2 a2);                        \
+static inline t __##f (t1 a1, t2 a2) {                                         \
+  t ret;                                                                       \
+  SVC_Setup(f##_);                                                             \
+  _##f(a1,a2);                                                                 \
+  __asm("" : rr : :);                                                            \
+  return ret;                                                                  \
+}
+
+#endif
+
+
+// Callback structure
+typedef struct {
+  void *fp;             // Function pointer
+  void *arg;            // Function argument
+} osCallback;
+
+
+// OS Section definitions
+#ifdef OS_SECTIONS_LINK_INFO
+extern const uint32_t  os_section_id$$Base;
+extern const uint32_t  os_section_id$$Limit;
+#endif
+
+#ifndef __MBED_CMSIS_RTOS_CA9
+// OS Stack Memory for Threads definitions
+extern       uint64_t  os_stack_mem[];
+extern const uint32_t  os_stack_sz;
+#endif
+
+// OS Timers external resources
+extern const osThreadDef_t   os_thread_def_osTimerThread;
+extern       osThreadId      osThreadId_osTimerThread;
+extern const osMessageQDef_t os_messageQ_def_osTimerMessageQ;
+extern       osMessageQId    osMessageQId_osTimerMessageQ;
+
+extern U32 IRQNestLevel; /* Indicates whether inside an ISR, and the depth of nesting.  0 = not in ISR. */
+
+
+// ==== Helper Functions ====
+
+/// Convert timeout in millisec to system ticks
+static uint32_t rt_ms2tick (uint32_t millisec) {
+  uint32_t tick;
+
+  if (millisec == osWaitForever) return 0xFFFF; // Indefinite timeout
+  if (millisec > 4000000) return 0xFFFE;        // Max ticks supported
+
+  tick = ((1000 * millisec) + os_clockrate - 1)  / os_clockrate;
+  if (tick > 0xFFFE) return 0xFFFE;
+
+  return tick;
+}
+
+/// Convert Thread ID to TCB pointer
+static P_TCB rt_tid2ptcb (osThreadId thread_id) {
+  P_TCB ptcb;
+
+  if (thread_id == NULL) return NULL;
+
+  if ((uint32_t)thread_id & 3) return NULL;
+
+#ifdef OS_SECTIONS_LINK_INFO
+  if ((os_section_id$$Base != 0) && (os_section_id$$Limit != 0)) {
+    if (thread_id  < (osThreadId)os_section_id$$Base)  return NULL;
+    if (thread_id >= (osThreadId)os_section_id$$Limit) return NULL;
+  }
+#endif
+
+  ptcb = thread_id;
+
+  if (ptcb->cb_type != TCB) return NULL;
+
+  return ptcb;
+}
+
+/// Convert ID pointer to Object pointer
+static void *rt_id2obj (void *id) {
+
+  if ((uint32_t)id & 3) return NULL;
+
+#ifdef OS_SECTIONS_LINK_INFO
+  if ((os_section_id$$Base != 0) && (os_section_id$$Limit != 0)) {
+    if (id  < (void *)os_section_id$$Base)  return NULL;
+    if (id >= (void *)os_section_id$$Limit) return NULL;
+  }
+#endif
+
+  return id;
+}
+
+// === Helper functions for system call interface ===
+
+static __inline char __get_mode(void) {
+    return (char)(__get_CPSR() & 0x1f);
+}
+
+static __inline char __exceptional_mode(void) {
+    switch(__get_mode()) {
+        case MODE_USR:
+        case MODE_SYS:
+            return 0;
+        case MODE_SVC:
+            if (IRQNestLevel == 0)
+                return 0; /* handling a regular service call */
+            else
+                return 1; /* handling an ISR in SVC mode */
+        default:
+            return 1;
+    }
+}
+
+// ==== Kernel Control ====
+
+uint8_t os_initialized;                         // Kernel Initialized flag
+uint8_t os_running;                             // Kernel Running flag
+
+// Kernel Control Service Calls declarations
+SVC_0_1(svcKernelInitialize, osStatus, RET_osStatus)
+SVC_0_1(svcKernelStart,      osStatus, RET_osStatus)
+SVC_0_1(svcKernelRunning,    int32_t,  RET_int32_t)
+SVC_0_1(svcKernelSysTick,    uint32_t, RET_uint32_t)
+
+static void  sysThreadError   (osStatus status);
+osThreadId   svcThreadCreate  (const osThreadDef_t *thread_def, void *argument);
+osMessageQId svcMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+
+// Kernel Control Service Calls
+
+/// Initialize the RTOS Kernel for creating objects
+osStatus svcKernelInitialize (void) {
+#ifdef __MBED_CMSIS_RTOS_CA9
+  if (!os_initialized) {
+    rt_sys_init();                              // RTX System Initialization
+  }
+#else
+  int ret;
+
+  if (!os_initialized) {
+
+    // Init Thread Stack Memory (must be 8-byte aligned)
+    if ((uint32_t)os_stack_mem & 7) return osErrorNoMemory;
+    ret = rt_init_mem(os_stack_mem, os_stack_sz);
+    if (ret != 0) return osErrorNoMemory;
+
+    rt_sys_init();                              // RTX System Initialization
+  }
+#endif
+
+  os_tsk.run->prio = 255;                       // Highest priority
+
+  if (!os_initialized) {
+    // Create OS Timers resources (Message Queue & Thread)
+    osMessageQId_osTimerMessageQ = svcMessageCreate (&os_messageQ_def_osTimerMessageQ, NULL);
+    osThreadId_osTimerThread = svcThreadCreate(&os_thread_def_osTimerThread, NULL);
+  }
+
+  sysThreadError(osOK);
+
+  os_initialized = 1;
+  os_running = 0;
+
+  return osOK;
+}
+
+/// Start the RTOS Kernel
+osStatus svcKernelStart (void) {
+
+  if (os_running) return osOK;
+
+  rt_tsk_prio(0, os_tsk.run->prio_base);        // Restore priority
+  if (os_tsk.run->task_id == 0xFF) {            // Idle Thread
+    __set_PSP(os_tsk.run->tsk_stack + 8*4);     // Setup PSP
+  }
+  os_tsk.run = NULL;                            // Force context switch
+
+  rt_sys_start();
+
+  os_running = 1;
+
+  return osOK;
+}
+
+/// Check if the RTOS kernel is already started
+int32_t svcKernelRunning(void) {
+  return os_running;
+}
+
+/// Get the RTOS kernel system timer counter
+uint32_t svcKernelSysTick (void) {
+  uint32_t tick, tick0;
+
+  tick = os_tick_val();
+  if (os_tick_ovf()) {
+    tick0 = os_tick_val();
+    if (tick0 < tick) tick = tick0;
+    tick += (os_trv + 1) * (os_time + 1);
+  } else {
+    tick += (os_trv + 1) *  os_time;
+  }
+
+  return tick;
+}
+
+// Kernel Control Public API
+
+/// Initialize the RTOS Kernel for creating objects
+osStatus osKernelInitialize (void) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  if (__get_mode() != MODE_USR) {
+    return   svcKernelInitialize();
+  } else {
+    return __svcKernelInitialize();
+  }
+}
+
+/// Start the RTOS Kernel
+osStatus osKernelStart (void) {
+  char mode = __get_mode();
+
+  switch(mode) {
+    case MODE_USR:
+      if (os_flags & 1) return osErrorOS;  // Privileged Thread mode requested from Unprivileged
+      break;
+    case MODE_SYS:
+      if (!(os_flags & 1)) {
+        __set_CPS_USR();
+      }
+      break;
+    default:
+      return osErrorISR;                   // Not allowed in ISR
+  }
+  return __svcKernelStart();
+}
+
+/// Check if the RTOS kernel is already started
+int32_t osKernelRunning(void) {
+  if(__get_mode() != MODE_USR) {
+    return os_running;
+  } else {
+    return __svcKernelRunning();
+  }
+}
+
+/// Get the RTOS kernel system timer counter
+uint32_t osKernelSysTick (void) {
+  if (__exceptional_mode()) return 0;              // Not allowed in ISR
+  return __svcKernelSysTick();
+}
+
+
+// ==== Thread Management ====
+
+/// Set Thread Error (for Create functions which return IDs)
+static void sysThreadError (osStatus status) {
+  // To Do
+}
+
+__NO_RETURN void osThreadExit (void);
+
+// Thread Service Calls declarations
+SVC_2_1(svcThreadCreate,      osThreadId, const osThreadDef_t *, void *,     RET_pointer)
+SVC_0_1(svcThreadGetId,       osThreadId,                                    RET_pointer)
+SVC_1_1(svcThreadTerminate,   osStatus,         osThreadId,                  RET_osStatus)
+SVC_0_1(svcThreadYield,       osStatus,                                      RET_osStatus)
+SVC_2_1(svcThreadSetPriority, osStatus,         osThreadId,      osPriority, RET_osStatus)
+SVC_1_1(svcThreadGetPriority, osPriority,       osThreadId,                  RET_osPriority)
+
+// Thread Service Calls
+
+/// Create a thread and add it to Active Threads and set it to state READY
+osThreadId svcThreadCreate (const osThreadDef_t *thread_def, void *argument) {
+  P_TCB  ptcb;
+  OS_TID tsk;
+  void  *stk;
+
+  if ((thread_def == NULL) ||
+      (thread_def->pthread == NULL) ||
+      (thread_def->tpriority < osPriorityIdle) ||
+      (thread_def->tpriority > osPriorityRealtime)) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+#ifdef __MBED_CMSIS_RTOS_CA9
+  if (thread_def->stacksize != 0) {             // Custom stack size
+    stk = (void *)thread_def->stack_pointer;
+  } else {                                      // Default stack size
+    stk = NULL;
+  }
+#else
+  if (thread_def->stacksize != 0) {             // Custom stack size
+    stk = rt_alloc_mem(                         // Allocate stack
+      os_stack_mem,
+      thread_def->stacksize
+    );
+    if (stk == NULL) {
+      sysThreadError(osErrorNoMemory);          // Out of memory
+      return NULL;
+    }
+  } else {                                      // Default stack size
+    stk = NULL;
+  }
+#endif
+
+  tsk = rt_tsk_create(                          // Create task
+    (FUNCP)thread_def->pthread,                 // Task function pointer
+    (thread_def->tpriority-osPriorityIdle+1) |  // Task priority
+    (thread_def->stacksize << 8),               // Task stack size in bytes
+    stk,                                        // Pointer to task's stack
+    argument                                    // Argument to the task
+  );
+
+  if (tsk == 0) {                               // Invalid task ID
+#ifndef __MBED_CMSIS_RTOS_CA9
+    if (stk != NULL) {
+      rt_free_mem(os_stack_mem, stk);           // Free allocated stack
+    }
+#endif
+    sysThreadError(osErrorNoMemory);            // Create task failed (Out of memory)
+    return NULL;
+  }
+
+  ptcb = (P_TCB)os_active_TCB[tsk - 1];         // TCB pointer
+
+  *((uint32_t *)ptcb->tsk_stack + 13) = (uint32_t)osThreadExit;
+
+  return ptcb;
+}
+
+/// Return the thread ID of the current running thread
+osThreadId svcThreadGetId (void) {
+  OS_TID tsk;
+
+  tsk = rt_tsk_self();
+  if (tsk == 0) return NULL;
+  return (P_TCB)os_active_TCB[tsk - 1];
+}
+
+/// Terminate execution of a thread and remove it from ActiveThreads
+osStatus svcThreadTerminate (osThreadId thread_id) {
+  OS_RESULT res;
+  P_TCB     ptcb;
+#ifndef __MBED_CMSIS_RTOS_CA9
+  void     *stk;
+#endif
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return osErrorParameter;
+
+#ifndef __MBED_CMSIS_RTOS_CA9
+  stk = ptcb->priv_stack ? ptcb->stack : NULL;  // Private stack
+#endif
+
+  res = rt_tsk_delete(ptcb->task_id);           // Delete task
+
+  if (res == OS_R_NOK) return osErrorResource;  // Delete task failed
+
+#ifndef __MBED_CMSIS_RTOS_CA9
+  if (stk != NULL) {
+    rt_free_mem(os_stack_mem, stk);             // Free private stack
+  }
+#endif
+
+  return osOK;
+}
+
+/// Pass control to next thread that is in state READY
+osStatus svcThreadYield (void) {
+  rt_tsk_pass();                                // Pass control to next task
+  return osOK;
+}
+
+/// Change priority of an active thread
+osStatus svcThreadSetPriority (osThreadId thread_id, osPriority priority) {
+  OS_RESULT res;
+  P_TCB     ptcb;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return osErrorParameter;
+
+  if ((priority < osPriorityIdle) || (priority > osPriorityRealtime)) {
+    return osErrorValue;
+  }
+
+  res = rt_tsk_prio(                            // Change task priority
+    ptcb->task_id,                              // Task ID
+    priority - osPriorityIdle + 1               // New task priority
+  );
+
+  if (res == OS_R_NOK) return osErrorResource;  // Change task priority failed
+
+  return osOK;
+}
+
+/// Get current priority of an active thread
+osPriority svcThreadGetPriority (osThreadId thread_id) {
+  P_TCB ptcb;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return osPriorityError;
+
+  return (osPriority)(ptcb->prio - 1 + osPriorityIdle);
+}
+
+
+// Thread Public API
+
+/// Create a thread and add it to Active Threads and set it to state READY
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) {
+  if (__exceptional_mode()) return NULL;           // Not allowed in ISR
+  if ((__get_mode() != MODE_USR) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcThreadCreate(thread_def, argument);
+  } else {
+    return __svcThreadCreate(thread_def, argument);
+  }
+}
+
+/// Return the thread ID of the current running thread
+osThreadId osThreadGetId (void) {
+  if (__exceptional_mode()) return NULL;           // Not allowed in ISR
+  return __svcThreadGetId();
+}
+
+/// Terminate execution of a thread and remove it from ActiveThreads
+osStatus osThreadTerminate (osThreadId thread_id) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcThreadTerminate(thread_id);
+}
+
+/// Pass control to next thread that is in state READY
+osStatus osThreadYield (void) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcThreadYield();
+}
+
+/// Change priority of an active thread
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcThreadSetPriority(thread_id, priority);
+}
+
+/// Get current priority of an active thread
+osPriority osThreadGetPriority (osThreadId thread_id) {
+  if (__exceptional_mode()) return osPriorityError;// Not allowed in ISR
+  return __svcThreadGetPriority(thread_id);
+}
+
+/// INTERNAL - Not Public
+/// Auto Terminate Thread on exit (used implicitly when thread exists)
+__NO_RETURN void osThreadExit (void) {
+  __svcThreadTerminate(__svcThreadGetId());
+  for (;;);                                     // Should never come here
+}
+
+#ifdef __MBED_CMSIS_RTOS_CA9
+/// Get current thread state
+uint8_t osThreadGetState (osThreadId thread_id) {
+  P_TCB ptcb;
+
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return INACTIVE;
+
+  return ptcb->state;
+}
+#endif
+
+// ==== Generic Wait Functions ====
+
+// Generic Wait Service Calls declarations
+SVC_1_1(svcDelay,           osStatus, uint32_t, RET_osStatus)
+#if osFeature_Wait != 0
+SVC_1_3(svcWait,  os_InRegs osEvent,  uint32_t, RET_osEvent)
+#endif
+
+// Generic Wait Service Calls
+
+/// Wait for Timeout (Time Delay)
+osStatus svcDelay (uint32_t millisec) {
+  if (millisec == 0) return osOK;
+  rt_dly_wait(rt_ms2tick(millisec));
+  return osEventTimeout;
+}
+
+/// Wait for Signal, Message, Mail, or Timeout
+#if osFeature_Wait != 0
+os_InRegs osEvent_type svcWait (uint32_t millisec) {
+  osEvent ret;
+
+  if (millisec == 0) {
+    ret.status = osOK;
+#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
+    osEvent_ret_status;
+    return;
+#else
+    return osEvent_ret_status;
+#endif
+  }
+
+  /* To Do: osEventSignal, osEventMessage, osEventMail */
+  rt_dly_wait(rt_ms2tick(millisec));
+  ret.status = osEventTimeout;
+
+#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
+  osEvent_ret_status;
+  return;
+#else
+  return osEvent_ret_status;
+#endif
+}
+#endif
+
+
+// Generic Wait API
+
+/// Wait for Timeout (Time Delay)
+osStatus osDelay (uint32_t millisec) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcDelay(millisec);
+}
+
+/// Wait for Signal, Message, Mail, or Timeout
+os_InRegs osEvent osWait (uint32_t millisec) {
+  osEvent ret;
+
+#if osFeature_Wait == 0
+  ret.status = osErrorOS;
+  return ret;
+#else
+  if (__exceptional_mode()) {                      // Not allowed in ISR
+    ret.status = osErrorISR;
+    return ret;
+  }
+  return __svcWait(millisec);
+#endif
+}
+
+
+// ==== Timer Management ====
+
+// Timer definitions
+#define osTimerInvalid  0
+#define osTimerStopped  1
+#define osTimerRunning  2
+
+// Timer structures
+
+typedef struct os_timer_cb_ {                   // Timer Control Block
+  struct os_timer_cb_ *next;                    // Pointer to next active Timer
+  uint8_t             state;                    // Timer State
+  uint8_t              type;                    // Timer Type (Periodic/One-shot)
+  uint16_t         reserved;                    // Reserved
+  uint16_t             tcnt;                    // Timer Delay Count
+  uint16_t             icnt;                    // Timer Initial Count
+  void                 *arg;                    // Timer Function Argument
+  const osTimerDef_t *timer;                    // Pointer to Timer definition
+} os_timer_cb;
+
+// Timer variables
+os_timer_cb *os_timer_head;                     // Pointer to first active Timer
+
+
+// Timer Helper Functions
+
+// Insert Timer into the list sorted by time
+static void rt_timer_insert (os_timer_cb *pt, uint32_t tcnt) {
+  os_timer_cb *p, *prev;
+
+  prev = NULL;
+  p = os_timer_head;
+  while (p != NULL) {
+    if (tcnt < p->tcnt) break;
+    tcnt -= p->tcnt;
+    prev = p;
+    p = p->next;
+  }
+  pt->next = p;
+  pt->tcnt = (uint16_t)tcnt;
+  if (p != NULL) {
+    p->tcnt -= pt->tcnt;
+  }
+  if (prev != NULL) {
+    prev->next = pt;
+  } else {
+    os_timer_head = pt;
+  }
+}
+
+// Remove Timer from the list
+static int rt_timer_remove (os_timer_cb *pt) {
+  os_timer_cb *p, *prev;
+
+  prev = NULL;
+  p = os_timer_head;
+  while (p != NULL) {
+    if (p == pt) break;
+    prev = p;
+    p = p->next;
+  }
+  if (p == NULL) return -1;
+  if (prev != NULL) {
+    prev->next = pt->next;
+  } else {
+    os_timer_head = pt->next;
+  }
+  if (pt->next != NULL) {
+    pt->next->tcnt += pt->tcnt;
+  }
+
+  return 0;
+}
+
+
+// Timer Service Calls declarations
+SVC_3_1(svcTimerCreate,           osTimerId,  const osTimerDef_t *, os_timer_type, void *, RET_pointer)
+SVC_2_1(svcTimerStart,            osStatus,         osTimerId,      uint32_t,              RET_osStatus)
+SVC_1_1(svcTimerStop,             osStatus,         osTimerId,                             RET_osStatus)
+SVC_1_1(svcTimerDelete,           osStatus,         osTimerId,                             RET_osStatus)
+SVC_1_2(svcTimerCall,   os_InRegs osCallback,       osTimerId,                             RET_osCallback)
+
+// Timer Management Service Calls
+
+/// Create timer
+osTimerId svcTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
+  os_timer_cb *pt;
+
+  if ((timer_def == NULL) || (timer_def->ptimer == NULL)) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  pt = timer_def->timer;
+  if (pt == NULL) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  if ((type != osTimerOnce) && (type != osTimerPeriodic)) {
+    sysThreadError(osErrorValue);
+    return NULL;
+  }
+
+  if (osThreadId_osTimerThread == NULL) {
+    sysThreadError(osErrorResource);
+    return NULL;
+  }
+
+  if (pt->state != osTimerInvalid){
+    sysThreadError(osErrorResource);
+    return NULL;
+  }
+
+  pt->next  = NULL;
+  pt->state = osTimerStopped;
+  pt->type  =  (uint8_t)type;
+  pt->arg   = argument;
+  pt->timer = timer_def;
+
+  return (osTimerId)pt;
+}
+
+/// Start or restart timer
+osStatus svcTimerStart (osTimerId timer_id, uint32_t millisec) {
+  os_timer_cb *pt;
+  uint32_t     tcnt;
+
+  pt = rt_id2obj(timer_id);
+  if (pt == NULL) return osErrorParameter;
+
+  tcnt = rt_ms2tick(millisec);
+  if (tcnt == 0) return osErrorValue;
+
+  switch (pt->state) {
+    case osTimerRunning:
+      if (rt_timer_remove(pt) != 0) {
+        return osErrorResource;
+      }
+      break;
+    case osTimerStopped:
+      pt->state = osTimerRunning;
+      pt->icnt  = (uint16_t)tcnt;
+      break;
+    default:
+      return osErrorResource;
+  }
+
+  rt_timer_insert(pt, tcnt);
+
+  return osOK;
+}
+
+/// Stop timer
+osStatus svcTimerStop (osTimerId timer_id) {
+  os_timer_cb *pt;
+
+  pt = rt_id2obj(timer_id);
+  if (pt == NULL) return osErrorParameter;
+
+  if (pt->state != osTimerRunning) return osErrorResource;
+
+  pt->state = osTimerStopped;
+
+  if (rt_timer_remove(pt) != 0) {
+    return osErrorResource;
+  }
+
+  return osOK;
+}
+
+/// Delete timer
+osStatus svcTimerDelete (osTimerId timer_id) {
+  os_timer_cb *pt;
+
+  pt = rt_id2obj(timer_id);
+  if (pt == NULL) return osErrorParameter;
+
+  switch (pt->state) {
+    case osTimerRunning:
+      rt_timer_remove(pt);
+      break;
+    case osTimerStopped:
+      break;
+    default:
+      return osErrorResource;
+  }
+
+  pt->state = osTimerInvalid;
+
+  return osOK;
+}
+
+/// Get timer callback parameters
+os_InRegs osCallback_type svcTimerCall (osTimerId timer_id) {
+  os_timer_cb *pt;
+  osCallback   ret;
+
+  pt = rt_id2obj(timer_id);
+  if (pt == NULL) {
+    ret.fp  = NULL;
+    ret.arg = NULL;
+#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
+    osCallback_ret;
+    return;
+#else
+    return osCallback_ret;
+#endif
+  }
+
+  ret.fp  = (void *)pt->timer->ptimer;
+  ret.arg = pt->arg;
+
+#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
+  osCallback_ret;
+  return;
+#else
+  return osCallback_ret;
+#endif
+}
+
+static __INLINE osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+
+/// Timer Tick (called each SysTick)
+void sysTimerTick (void) {
+  os_timer_cb *pt, *p;
+
+  p = os_timer_head;
+  if (p == NULL) return;
+
+  p->tcnt--;
+  while ((p != NULL) && (p->tcnt == 0)) {
+    pt = p;
+    p = p->next;
+    os_timer_head = p;
+    isrMessagePut(osMessageQId_osTimerMessageQ, (uint32_t)pt, 0);
+    if (pt->type == osTimerPeriodic) {
+      rt_timer_insert(pt, pt->icnt);
+    } else {
+      pt->state = osTimerStopped;
+    }
+  }
+}
+
+/// Get user timers wake-up time 
+uint32_t sysUserTimerWakeupTime (void) {
+
+  if (os_timer_head) {
+    return os_timer_head->tcnt;
+  }
+  return 0xFFFF;
+}
+
+/// Update user timers on resume
+void sysUserTimerUpdate (uint32_t sleep_time) {
+
+  while (os_timer_head && sleep_time) {
+    if (sleep_time >= os_timer_head->tcnt) {
+      sleep_time -= os_timer_head->tcnt;
+      os_timer_head->tcnt = 1;
+      sysTimerTick();
+    } else {
+      os_timer_head->tcnt -= sleep_time;
+      break;
+    }
+  }
+}
+
+
+// Timer Management Public API
+
+/// Create timer
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
+  if (__exceptional_mode()) return NULL;           // Not allowed in ISR
+  if ((__get_mode() != MODE_USR) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcTimerCreate(timer_def, type, argument);
+  } else {
+    return __svcTimerCreate(timer_def, type, argument);
+  }
+}
+
+/// Start or restart timer
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcTimerStart(timer_id, millisec);
+}
+
+/// Stop timer
+osStatus osTimerStop (osTimerId timer_id) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcTimerStop(timer_id);
+}
+
+/// Delete timer
+osStatus osTimerDelete (osTimerId timer_id) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcTimerDelete(timer_id);
+}
+
+/// INTERNAL - Not Public
+/// Get timer callback parameters (used by OS Timer Thread)
+os_InRegs osCallback osTimerCall (osTimerId timer_id) {
+  return __svcTimerCall(timer_id);
+}
+
+
+// Timer Thread
+__NO_RETURN void osTimerThread (void const *argument) {
+  osCallback cb;
+  osEvent    evt;
+
+  for (;;) {
+    evt = osMessageGet(osMessageQId_osTimerMessageQ, osWaitForever);
+    if (evt.status == osEventMessage) {
+      cb = osTimerCall(evt.value.p);
+      if (cb.fp != NULL) {
+        (*(os_ptimer)cb.fp)(cb.arg);
+      }
+    }
+  }
+}
+
+
+// ==== Signal Management ====
+
+// Signal Service Calls declarations
+SVC_2_1(svcSignalSet,             int32_t, osThreadId, int32_t,  RET_int32_t)
+SVC_2_1(svcSignalClear,           int32_t, osThreadId, int32_t,  RET_int32_t)
+SVC_2_3(svcSignalWait,  os_InRegs osEvent, int32_t,    uint32_t, RET_osEvent)
+
+// Signal Service Calls
+
+/// Set the specified Signal Flags of an active thread
+int32_t svcSignalSet (osThreadId thread_id, int32_t signals) {
+  P_TCB   ptcb;
+  int32_t sig;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return 0x80000000;
+
+  if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000;
+
+  sig = ptcb->events;                           // Previous signal flags
+
+  rt_evt_set(signals, ptcb->task_id);           // Set event flags
+
+  return sig;
+}
+
+/// Clear the specified Signal Flags of an active thread
+int32_t svcSignalClear (osThreadId thread_id, int32_t signals) {
+  P_TCB   ptcb;
+  int32_t sig;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return 0x80000000;
+
+  if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000;
+
+  sig = ptcb->events;                           // Previous signal flags
+
+  rt_evt_clr(signals, ptcb->task_id);           // Clear event flags
+
+  return sig;
+}
+
+/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread
+os_InRegs osEvent_type svcSignalWait (int32_t signals, uint32_t millisec) {
+  OS_RESULT res;
+  osEvent   ret;
+
+  if (signals & (0xFFFFFFFF << osFeature_Signals)) {
+    ret.status = osErrorValue;
+#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
+    osEvent_ret_status;
+    return;
+#else
+    return osEvent_ret_status;
+#endif
+  }
+
+  if (signals != 0) {                           // Wait for all specified signals
+    res = rt_evt_wait(signals, rt_ms2tick(millisec), __TRUE);
+  } else {                                      // Wait for any signal
+    res = rt_evt_wait(0xFFFF,  rt_ms2tick(millisec), __FALSE);
+  }
+
+  if (res == OS_R_EVT) {
+    ret.status = osEventSignal;
+    ret.value.signals = signals ? signals : os_tsk.run->waits;
+  } else {
+    ret.status = millisec ? osEventTimeout : osOK;
+    ret.value.signals = 0;
+  }
+
+#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
+  osEvent_ret_value;
+  return;
+#else
+  return osEvent_ret_value;
+#endif
+}
+
+
+// Signal ISR Calls
+
+/// Set the specified Signal Flags of an active thread
+static __INLINE int32_t isrSignalSet (osThreadId thread_id, int32_t signals) {
+  P_TCB   ptcb;
+  int32_t sig;
+
+  ptcb = rt_tid2ptcb(thread_id);                // Get TCB pointer
+  if (ptcb == NULL) return 0x80000000;
+
+  if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000;
+
+  sig = ptcb->events;                           // Previous signal flags
+
+  isr_evt_set(signals, ptcb->task_id);          // Set event flags
+
+  return sig;
+}
+
+
+// Signal Public API
+
+/// Set the specified Signal Flags of an active thread
+int32_t osSignalSet (osThreadId thread_id, int32_t signals) {
+  if (__exceptional_mode()) {                      // in ISR
+    return   isrSignalSet(thread_id, signals);
+  } else {                                      // in Thread
+    return __svcSignalSet(thread_id, signals);
+  }
+}
+
+/// Clear the specified Signal Flags of an active thread
+int32_t osSignalClear (osThreadId thread_id, int32_t signals) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcSignalClear(thread_id, signals);
+}
+
+/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread
+os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec) {
+  osEvent ret;
+
+  if (__exceptional_mode()) {                      // Not allowed in ISR
+    ret.status = osErrorISR;
+    return ret;
+  }
+  return __svcSignalWait(signals, millisec);
+}
+
+
+// ==== Mutex Management ====
+
+// Mutex Service Calls declarations
+SVC_1_1(svcMutexCreate,  osMutexId, const osMutexDef_t *,           RET_pointer)
+SVC_2_1(svcMutexWait,    osStatus,        osMutexId,      uint32_t, RET_osStatus)
+SVC_1_1(svcMutexRelease, osStatus,        osMutexId,                RET_osStatus)
+SVC_1_1(svcMutexDelete,  osStatus,        osMutexId,                RET_osStatus)
+
+// Mutex Service Calls
+
+/// Create and Initialize a Mutex object
+osMutexId svcMutexCreate (const osMutexDef_t *mutex_def) {
+  OS_ID mut;
+
+  if (mutex_def == NULL) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  mut = mutex_def->mutex;
+  if (mut == NULL) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  if (((P_MUCB)mut)->cb_type != 0) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  rt_mut_init(mut);                             // Initialize Mutex
+
+  return mut;
+}
+
+/// Wait until a Mutex becomes available
+osStatus svcMutexWait (osMutexId mutex_id, uint32_t millisec) {
+  OS_ID     mut;
+  OS_RESULT res;
+
+  mut = rt_id2obj(mutex_id);
+  if (mut == NULL) return osErrorParameter;
+
+  if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter;
+
+  res = rt_mut_wait(mut, rt_ms2tick(millisec)); // Wait for Mutex
+
+  if (res == OS_R_TMO) {
+    return (millisec ? osErrorTimeoutResource : osErrorResource);
+  }
+
+  return osOK;
+}
+
+/// Release a Mutex that was obtained with osMutexWait
+osStatus svcMutexRelease (osMutexId mutex_id) {
+  OS_ID     mut;
+  OS_RESULT res;
+
+  mut = rt_id2obj(mutex_id);
+  if (mut == NULL) return osErrorParameter;
+
+  if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter;
+
+  res = rt_mut_release(mut);                    // Release Mutex
+
+  if (res == OS_R_NOK) return osErrorResource;  // Thread not owner or Zero Counter
+
+  return osOK;
+}
+
+/// Delete a Mutex that was created by osMutexCreate
+osStatus svcMutexDelete (osMutexId mutex_id) {
+  OS_ID mut;
+
+  mut = rt_id2obj(mutex_id);
+  if (mut == NULL) return osErrorParameter;
+
+  if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter;
+
+  rt_mut_delete(mut);                           // Release Mutex
+
+  return osOK;
+}
+
+
+// Mutex Public API
+
+/// Create and Initialize a Mutex object
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def) {
+  if (__exceptional_mode()) return NULL;           // Not allowed in ISR
+  if ((__get_mode() != MODE_USR) && (os_running == 0)) {
+    // Privileged and not running
+    return    svcMutexCreate(mutex_def);
+  } else {
+    return __svcMutexCreate(mutex_def);
+  }
+}
+
+/// Wait until a Mutex becomes available
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcMutexWait(mutex_id, millisec);
+}
+
+/// Release a Mutex that was obtained with osMutexWait
+osStatus osMutexRelease (osMutexId mutex_id) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcMutexRelease(mutex_id);
+}
+
+/// Delete a Mutex that was created by osMutexCreate
+osStatus osMutexDelete (osMutexId mutex_id) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcMutexDelete(mutex_id);
+}
+
+
+// ==== Semaphore Management ====
+
+// Semaphore Service Calls declarations
+SVC_2_1(svcSemaphoreCreate,  osSemaphoreId, const osSemaphoreDef_t *,  int32_t, RET_pointer)
+SVC_2_1(svcSemaphoreWait,    int32_t,             osSemaphoreId,      uint32_t, RET_int32_t)
+SVC_1_1(svcSemaphoreRelease, osStatus,            osSemaphoreId,                RET_osStatus)
+SVC_1_1(svcSemaphoreDelete,  osStatus,            osSemaphoreId,                RET_osStatus)
+
+// Semaphore Service Calls
+
+/// Create and Initialize a Semaphore object
+osSemaphoreId svcSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
+  OS_ID sem;
+
+  if (semaphore_def == NULL) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  sem = semaphore_def->semaphore;
+  if (sem == NULL) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  if (((P_SCB)sem)->cb_type != 0) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  if (count > osFeature_Semaphore) {
+    sysThreadError(osErrorValue);
+    return NULL;
+  }
+
+  rt_sem_init(sem, count);                      // Initialize Semaphore
+
+  return sem;
+}
+
+/// Wait until a Semaphore becomes available
+int32_t svcSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
+  OS_ID     sem;
+  OS_RESULT res;
+
+  sem = rt_id2obj(semaphore_id);
+  if (sem == NULL) return -1;
+
+  if (((P_SCB)sem)->cb_type != SCB) return -1;
+
+  res = rt_sem_wait(sem, rt_ms2tick(millisec)); // Wait for Semaphore
+
+  if (res == OS_R_TMO) return 0;                // Timeout
+
+  return (((P_SCB)sem)->tokens + 1);
+}
+
+/// Release a Semaphore
+osStatus svcSemaphoreRelease (osSemaphoreId semaphore_id) {
+  OS_ID sem;
+
+  sem = rt_id2obj(semaphore_id);
+  if (sem == NULL) return osErrorParameter;
+
+  if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter;
+
+  if (((P_SCB)sem)->tokens == osFeature_Semaphore) return osErrorResource;
+
+  rt_sem_send(sem);                             // Release Semaphore
+
+  return osOK;
+}
+
+/// Delete a Semaphore that was created by osSemaphoreCreate
+osStatus svcSemaphoreDelete (osSemaphoreId semaphore_id) {
+  OS_ID sem;
+
+  sem = rt_id2obj(semaphore_id);
+  if (sem == NULL) return osErrorParameter;
+
+  if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter;
+
+  rt_sem_delete(sem);                           // Delete Semaphore
+
+  return osOK;
+}
+
+
+// Semaphore ISR Calls
+
+/// Release a Semaphore
+static __INLINE osStatus isrSemaphoreRelease (osSemaphoreId semaphore_id) {
+  OS_ID sem;
+
+  sem = rt_id2obj(semaphore_id);
+  if (sem == NULL) return osErrorParameter;
+
+  if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter;
+
+  if (((P_SCB)sem)->tokens == osFeature_Semaphore) return osErrorResource;
+
+  isr_sem_send(sem);                            // Release Semaphore
+
+  return osOK;
+}
+
+
+// Semaphore Public API
+
+/// Create and Initialize a Semaphore object
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
+  if (__exceptional_mode()) return NULL;           // Not allowed in ISR
+  if ((__get_mode() != MODE_USR) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcSemaphoreCreate(semaphore_def, count);
+  } else {
+    return __svcSemaphoreCreate(semaphore_def, count);
+  }
+}
+
+/// Wait until a Semaphore becomes available
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
+  if (__exceptional_mode()) return -1;             // Not allowed in ISR
+  return __svcSemaphoreWait(semaphore_id, millisec);
+}
+
+/// Release a Semaphore
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id) {
+  if (__exceptional_mode()) {                      // in ISR
+    return   isrSemaphoreRelease(semaphore_id);
+  } else {                                      // in Thread
+    return __svcSemaphoreRelease(semaphore_id);
+  }
+}
+
+/// Delete a Semaphore that was created by osSemaphoreCreate
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id) {
+  if (__exceptional_mode()) return osErrorISR;     // Not allowed in ISR
+  return __svcSemaphoreDelete(semaphore_id);
+}
+
+
+// ==== Memory Management Functions ====
+
+// Memory Management Helper Functions
+
+// Clear Memory Box (Zero init)
+static void rt_clr_box (void *box_mem, void *box) {
+  uint32_t *p, n;
+
+  if (box) {
+    p = box;
+    for (n = ((P_BM)box_mem)->blk_size; n; n -= 4) {
+      *p++ = 0;
+    }
+  }
+}
+
+// Memory Management Service Calls declarations
+SVC_1_1(svcPoolCreate, osPoolId, const osPoolDef_t *,           RET_pointer)
+SVC_2_1(sysPoolAlloc,  void *,         osPoolId,      uint32_t, RET_pointer)
+SVC_2_1(sysPoolFree,   osStatus,       osPoolId,      void *,   RET_osStatus)
+
+// Memory Management Service & ISR Calls
+
+/// Create and Initialize memory pool
+osPoolId svcPoolCreate (const osPoolDef_t *pool_def) {
+  uint32_t blk_sz;
+
+  if ((pool_def == NULL) ||
+      (pool_def->pool_sz == 0) ||
+      (pool_def->item_sz == 0) ||
+      (pool_def->pool == NULL)) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  blk_sz = (pool_def->item_sz + 3) & ~3;
+
+  _init_box(pool_def->pool, sizeof(struct OS_BM) + pool_def->pool_sz * blk_sz, blk_sz);
+
+  return pool_def->pool;
+}
+
+/// Allocate a memory block from a memory pool
+void *sysPoolAlloc (osPoolId pool_id, uint32_t clr) {
+  void *ptr;
+
+  if (pool_id == NULL) return NULL;
+
+  ptr = rt_alloc_box(pool_id);
+  if (clr) {
+    rt_clr_box(pool_id, ptr);
+  }
+
+  return ptr;
+}
+
+/// Return an allocated memory block back to a specific memory pool
+osStatus sysPoolFree (osPoolId pool_id, void *block) {
+  int32_t res;
+
+  if (pool_id == NULL) return osErrorParameter;
+
+  res = rt_free_box(pool_id, block);
+  if (res != 0) return osErrorValue;
+
+  return osOK;
+}
+
+
+// Memory Management Public API
+
+/// Create and Initialize memory pool
+osPoolId osPoolCreate (const osPoolDef_t *pool_def) {
+  if (__exceptional_mode()) return NULL;           // Not allowed in ISR
+  if ((__get_mode() != MODE_USR) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcPoolCreate(pool_def);
+  } else {
+    return __svcPoolCreate(pool_def);
+  }
+}
+
+/// Allocate a memory block from a memory pool
+void *osPoolAlloc (osPoolId pool_id) {
+  if (__get_mode() != MODE_USR) {               // in ISR or Privileged
+    return   sysPoolAlloc(pool_id, 0);
+  } else {                                      // in Thread
+    return __sysPoolAlloc(pool_id, 0);
+  }
+}
+
+/// Allocate a memory block from a memory pool and set memory block to zero
+void *osPoolCAlloc (osPoolId pool_id) {
+  if (__get_mode() != MODE_USR) {               // in ISR or Privileged
+    return   sysPoolAlloc(pool_id, 1);
+  } else {                                      // in Thread
+    return __sysPoolAlloc(pool_id, 1);
+  }
+}
+
+/// Return an allocated memory block back to a specific memory pool
+osStatus osPoolFree (osPoolId pool_id, void *block) {
+  if (__get_mode() != MODE_USR) {               // in ISR or Privileged
+    return   sysPoolFree(pool_id, block);
+  } else {                                      // in Thread
+    return __sysPoolFree(pool_id, block);
+  }
+}
+
+
+// ==== Message Queue Management Functions ====
+
+// Message Queue Management Service Calls declarations
+SVC_2_1(svcMessageCreate,        osMessageQId, const osMessageQDef_t *, osThreadId,           RET_pointer)
+SVC_3_1(svcMessagePut,           osStatus,           osMessageQId,      uint32_t,   uint32_t, RET_osStatus)
+SVC_2_3(svcMessageGet, os_InRegs osEvent,            osMessageQId,      uint32_t,             RET_osEvent)
+
+// Message Queue Service Calls
+
+/// Create and Initialize Message Queue
+osMessageQId svcMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
+
+  if ((queue_def == NULL) ||
+      (queue_def->queue_sz == 0) ||
+      (queue_def->pool == NULL)) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  if (((P_MCB)queue_def->pool)->cb_type != 0) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  rt_mbx_init(queue_def->pool, 4*(queue_def->queue_sz + 4));
+
+  return queue_def->pool;
+}
+
+/// Put a Message to a Queue
+osStatus svcMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
+  OS_RESULT res;
+
+  if (queue_id == NULL) return osErrorParameter;
+
+  if (((P_MCB)queue_id)->cb_type != MCB) return osErrorParameter;
+
+  res = rt_mbx_send(queue_id, (void *)info, rt_ms2tick(millisec));
+
+  if (res == OS_R_TMO) {
+    return (millisec ? osErrorTimeoutResource : osErrorResource);
+  }
+
+  return osOK;
+}
+
+/// Get a Message or Wait for a Message from a Queue
+os_InRegs osEvent_type svcMessageGet (osMessageQId queue_id, uint32_t millisec) {
+  OS_RESULT res;
+  osEvent   ret;
+
+  if (queue_id == NULL) {
+    ret.status = osErrorParameter;
+#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
+    osEvent_ret_status;
+    return;
+#else
+    return osEvent_ret_status;
+#endif
+  }
+
+  if (((P_MCB)queue_id)->cb_type != MCB) {
+    ret.status = osErrorParameter;
+#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
+    osEvent_ret_status;
+    return;
+#else
+    return osEvent_ret_status;
+#endif
+  }
+
+  res = rt_mbx_wait(queue_id, &ret.value.p, rt_ms2tick(millisec));
+
+  if (res == OS_R_TMO) {
+    ret.status = millisec ? osEventTimeout : osOK;
+#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
+    osEvent_ret_value;
+    return;
+#else
+    return osEvent_ret_value;
+#endif
+  }
+
+  ret.status = osEventMessage;
+
+#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
+  osEvent_ret_value;
+  return;
+#else
+  return osEvent_ret_value;
+#endif
+}
+
+
+// Message Queue ISR Calls
+
+/// Put a Message to a Queue
+static __INLINE osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
+
+  if ((queue_id == NULL) || (millisec != 0)) {
+    return osErrorParameter;
+  }
+
+  if (((P_MCB)queue_id)->cb_type != MCB) return osErrorParameter;
+
+  if (rt_mbx_check(queue_id) == 0) {            // Check if Queue is full
+    return osErrorResource;
+  }
+
+  isr_mbx_send(queue_id, (void *)info);
+
+  return osOK;
+}
+
+/// Get a Message or Wait for a Message from a Queue
+static __INLINE os_InRegs osEvent isrMessageGet (osMessageQId queue_id, uint32_t millisec) {
+  OS_RESULT res;
+  osEvent   ret;
+
+  if ((queue_id == NULL) || (millisec != 0)) {
+    ret.status = osErrorParameter;
+    return ret;
+  }
+
+  if (((P_MCB)queue_id)->cb_type != MCB) {
+    ret.status = osErrorParameter;
+    return ret;
+  }
+
+  res = isr_mbx_receive(queue_id, &ret.value.p);
+
+  if (res != OS_R_MBX) {
+    ret.status = osOK;
+    return ret;
+  }
+
+  ret.status = osEventMessage;
+
+  return ret;
+}
+
+
+// Message Queue Management Public API
+
+/// Create and Initialize Message Queue
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
+  if (__exceptional_mode()) return NULL;           // Not allowed in ISR
+  if ((__get_mode() != MODE_USR) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcMessageCreate(queue_def, thread_id);
+  } else {
+    return __svcMessageCreate(queue_def, thread_id);
+  }
+}
+
+/// Put a Message to a Queue
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
+  if (__exceptional_mode()) {                      // in ISR
+    return   isrMessagePut(queue_id, info, millisec);
+  } else {                                      // in Thread
+    return __svcMessagePut(queue_id, info, millisec);
+  }
+}
+
+/// Get a Message or Wait for a Message from a Queue
+os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {
+  if (__exceptional_mode()) {                      // in ISR
+    return   isrMessageGet(queue_id, millisec);
+  } else {                                      // in Thread
+    return __svcMessageGet(queue_id, millisec);
+  }
+}
+
+
+// ==== Mail Queue Management Functions ====
+
+// Mail Queue Management Service Calls declarations
+SVC_2_1(svcMailCreate, osMailQId, const osMailQDef_t *, osThreadId,                   RET_pointer)
+SVC_4_1(sysMailAlloc,  void *,          osMailQId,      uint32_t, uint32_t, uint32_t, RET_pointer)
+SVC_3_1(sysMailFree,   osStatus,        osMailQId,      void *,   uint32_t,           RET_osStatus)
+
+// Mail Queue Management Service & ISR Calls
+
+/// Create and Initialize mail queue
+osMailQId svcMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
+  uint32_t blk_sz;
+  P_MCB    pmcb;
+  void    *pool;
+
+  if ((queue_def == NULL) ||
+      (queue_def->queue_sz == 0) ||
+      (queue_def->item_sz  == 0) ||
+      (queue_def->pool == NULL)) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  pmcb = *(((void **)queue_def->pool) + 0);
+  pool = *(((void **)queue_def->pool) + 1);
+
+  if ((pool == NULL) || (pmcb == NULL) || (pmcb->cb_type != 0)) {
+    sysThreadError(osErrorParameter);
+    return NULL;
+  }
+
+  blk_sz = (queue_def->item_sz + 3) & ~3;
+
+  _init_box(pool, sizeof(struct OS_BM) + queue_def->queue_sz * blk_sz, blk_sz);
+
+  rt_mbx_init(pmcb, 4*(queue_def->queue_sz + 4));
+
+  return queue_def->pool;
+}
+
+/// Allocate a memory block from a mail
+void *sysMailAlloc (osMailQId queue_id, uint32_t millisec, uint32_t isr, uint32_t clr) {
+  P_MCB pmcb;
+  void *pool;
+  void *mem;
+
+  if (queue_id == NULL) return NULL;
+
+  pmcb = *(((void **)queue_id) + 0);
+  pool = *(((void **)queue_id) + 1);
+
+  if ((pool == NULL) || (pmcb == NULL)) return NULL;
+
+  if (isr && (millisec != 0)) return NULL;
+
+  mem = rt_alloc_box(pool);
+  if (clr) {
+    rt_clr_box(pool, mem);
+  }
+
+  if ((mem == NULL) && (millisec != 0)) {
+    // Put Task to sleep when Memory not available
+    if (pmcb->p_lnk != NULL) {
+      rt_put_prio((P_XCB)pmcb, os_tsk.run);
+    } else {
+      pmcb->p_lnk = os_tsk.run;
+      os_tsk.run->p_lnk = NULL;
+      os_tsk.run->p_rlnk = (P_TCB)pmcb;
+      // Task is waiting to allocate a message
+      pmcb->state = 3;
+    }
+    rt_block(rt_ms2tick(millisec), WAIT_MBX);
+  }
+
+  return mem;
+}
+
+/// Free a memory block from a mail
+osStatus sysMailFree (osMailQId queue_id, void *mail, uint32_t isr) {
+  P_MCB   pmcb;
+  P_TCB   ptcb;
+  void   *pool;
+  void   *mem;
+  int32_t res;
+
+  if (queue_id == NULL) return osErrorParameter;
+
+  pmcb = *(((void **)queue_id) + 0);
+  pool = *(((void **)queue_id) + 1);
+
+  if ((pmcb == NULL) || (pool == NULL)) return osErrorParameter;
+
+  res = rt_free_box(pool, mail);
+
+  if (res != 0) return osErrorValue;
+
+  if ((pmcb->p_lnk != NULL) && (pmcb->state == 3)) {
+    // Task is waiting to allocate a message
+    if (isr) {
+      rt_psq_enq (pmcb, (U32)pool);
+      rt_psh_req ();
+    } else {
+      mem = rt_alloc_box(pool);
+      if (mem != NULL) {
+        ptcb = rt_get_first((P_XCB)pmcb);
+        rt_ret_val(ptcb, (U32)mem);
+        rt_rmv_dly(ptcb);
+        rt_dispatch(ptcb);
+      }
+    }
+  }
+
+  return osOK;
+}
+
+
+// Mail Queue Management Public API
+
+/// Create and Initialize mail queue
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
+  if (__exceptional_mode()) return NULL;           // Not allowed in ISR
+  if ((__get_mode() != MODE_USR) && (os_running == 0)) {
+    // Privileged and not running
+    return   svcMailCreate(queue_def, thread_id);
+  } else {
+    return __svcMailCreate(queue_def, thread_id);
+  }
+}
+
+/// Allocate a memory block from a mail
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec) {
+  if (__exceptional_mode()) {                      // in ISR
+    return   sysMailAlloc(queue_id, millisec, 1, 0);
+  } else {                                      // in Thread
+    return __sysMailAlloc(queue_id, millisec, 0, 0);
+  }
+}
+
+/// Allocate a memory block from a mail and set memory block to zero
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {
+  if (__exceptional_mode()) {                      // in ISR
+    return   sysMailAlloc(queue_id, millisec, 1, 1);
+  } else {                                      // in Thread
+    return __sysMailAlloc(queue_id, millisec, 0, 1);
+  }
+}
+
+/// Free a memory block from a mail
+osStatus osMailFree (osMailQId queue_id, void *mail) {
+  if (__exceptional_mode()) {                      // in ISR
+    return   sysMailFree(queue_id, mail, 1);
+  } else {                                      // in Thread
+    return __sysMailFree(queue_id, mail, 0);
+  }
+}
+
+/// Put a mail to a queue
+osStatus osMailPut (osMailQId queue_id, void *mail) {
+  if (queue_id == NULL) return osErrorParameter;
+  if (mail == NULL)     return osErrorValue;
+  return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0);
+}
+
+#ifdef __CC_ARM
+#pragma push
+#pragma Ospace
+#endif // __arm__
+/// Get a mail from a queue
+os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) {
+  osEvent ret;
+
+  if (queue_id == NULL) {
+    ret.status = osErrorParameter;
+    return ret;
+  }
+
+  ret = osMessageGet(*((void **)queue_id), millisec);
+  if (ret.status == osEventMessage) ret.status = osEventMail;
+
+  return ret;
+}
+#ifdef __CC_ARM
+#pragma pop
+#endif // __arm__
+
+
+//  ==== RTX Extensions ====
+
+// Service Calls declarations
+SVC_0_1(rt_suspend, uint32_t, RET_uint32_t)
+SVC_1_0(rt_resume,  void,     uint32_t)
+
+
+// Public API
+
+/// Suspends the OS task scheduler
+uint32_t os_suspend (void) {
+  return __rt_suspend();
+}
+
+/// Resumes the OS task scheduler
+void os_resume (uint32_t sleep_time) {
+  __rt_resume(sleep_time);
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Event.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,195 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_EVENT.C
+ *      Purpose: Implements waits and wake-ups for event flags
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_Event.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#ifdef __CORTEX_A9
+#include "rt_HAL_CA.h"
+#else
+#include "rt_HAL_CM.h"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_evt_wait -----------------------------------*/
+
+OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait) {
+  /* Wait for one or more event flags with optional time-out.                */
+  /* "wait_flags" identifies the flags to wait for.                          */
+  /* "timeout" is the time-out limit in system ticks (0xffff if no time-out) */
+  /* "and_wait" specifies the AND-ing of "wait_flags" as condition to be met */
+  /* to complete the wait. (OR-ing if set to 0).                             */
+  U32 block_state;
+
+  if (and_wait) {
+    /* Check for AND-connected events */
+    if ((os_tsk.run->events & wait_flags) == wait_flags) {
+      os_tsk.run->events &= ~wait_flags;
+      return (OS_R_EVT);
+    }
+    block_state = WAIT_AND;
+  }
+  else {
+    /* Check for OR-connected events */
+    if (os_tsk.run->events & wait_flags) {
+      os_tsk.run->waits = os_tsk.run->events & wait_flags;
+      os_tsk.run->events &= ~wait_flags;
+      return (OS_R_EVT);
+    }
+    block_state = WAIT_OR;
+  }
+  /* Task has to wait */
+  os_tsk.run->waits = wait_flags;
+  rt_block (timeout, (U8)block_state);
+  return (OS_R_TMO);
+}
+
+
+/*--------------------------- rt_evt_set ------------------------------------*/
+
+void rt_evt_set (U16 event_flags, OS_TID task_id) {
+  /* Set one or more event flags of a selectable task. */
+  P_TCB p_tcb;
+
+  p_tcb = os_active_TCB[task_id-1];
+  if (p_tcb == NULL) {
+    return;
+  }
+  p_tcb->events |= event_flags;
+  event_flags    = p_tcb->waits;
+  /* If the task is not waiting for an event, it should not be put */
+  /* to ready state. */
+  if (p_tcb->state == WAIT_AND) {
+    /* Check for AND-connected events */
+    if ((p_tcb->events & event_flags) == event_flags) {
+      goto wkup;
+    }
+  }
+  if (p_tcb->state == WAIT_OR) {
+    /* Check for OR-connected events */
+    if (p_tcb->events & event_flags) {
+      p_tcb->waits  &= p_tcb->events;
+wkup: p_tcb->events &= ~event_flags;
+      rt_rmv_dly (p_tcb);
+      p_tcb->state   = READY;
+#ifdef __CMSIS_RTOS
+      rt_ret_val2(p_tcb, 0x08/*osEventSignal*/, p_tcb->waits);
+#else
+      rt_ret_val (p_tcb, OS_R_EVT);
+#endif
+      rt_dispatch (p_tcb);
+    }
+  }
+}
+
+
+/*--------------------------- rt_evt_clr ------------------------------------*/
+
+void rt_evt_clr (U16 clear_flags, OS_TID task_id) {
+  /* Clear one or more event flags (identified by "clear_flags") of a */
+  /* selectable task (identified by "task"). */
+  P_TCB task = os_active_TCB[task_id-1];
+
+  if (task == NULL) {
+    return;
+  }
+  task->events &= ~clear_flags;
+}
+
+
+/*--------------------------- isr_evt_set -----------------------------------*/
+
+void isr_evt_set (U16 event_flags, OS_TID task_id) {
+  /* Same function as "os_evt_set", but to be called by ISRs. */
+  P_TCB p_tcb = os_active_TCB[task_id-1];
+
+  if (p_tcb == NULL) {
+    return;
+  }
+  rt_psq_enq (p_tcb, event_flags);
+  rt_psh_req ();
+}
+
+
+/*--------------------------- rt_evt_get ------------------------------------*/
+
+U16 rt_evt_get (void) {
+  /* Get events of a running task after waiting for OR connected events. */
+  return (os_tsk.run->waits);
+}
+
+
+/*--------------------------- rt_evt_psh ------------------------------------*/
+
+void rt_evt_psh (P_TCB p_CB, U16 set_flags) {
+  /* Check if task has to be waken up */
+  U16 event_flags;
+
+  p_CB->events |= set_flags;
+  event_flags = p_CB->waits;
+  if (p_CB->state == WAIT_AND) {
+    /* Check for AND-connected events */
+    if ((p_CB->events & event_flags) == event_flags) {
+      goto rdy;
+    }
+  }
+  if (p_CB->state == WAIT_OR) {
+    /* Check for OR-connected events */
+    if (p_CB->events & event_flags) {
+      p_CB->waits  &= p_CB->events;
+rdy:  p_CB->events &= ~event_flags;
+      rt_rmv_dly (p_CB);
+      p_CB->state   = READY;
+#ifdef __CMSIS_RTOS
+      rt_ret_val2(p_CB, 0x08/*osEventSignal*/, p_CB->waits);
+#else
+      rt_ret_val (p_CB, OS_R_EVT);
+#endif
+      rt_put_prio (&os_rdy, p_CB);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Event.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,47 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_EVENT.H
+ *      Purpose: Implements waits and wake-ups for event flags
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern OS_RESULT rt_evt_wait (U16 wait_flags,  U16 timeout, BOOL and_wait);
+extern void      rt_evt_set  (U16 event_flags, OS_TID task_id);
+extern void      rt_evt_clr  (U16 clear_flags, OS_TID task_id);
+extern void      isr_evt_set (U16 event_flags, OS_TID task_id);
+extern U16       rt_evt_get  (void);
+extern void      rt_evt_psh  (P_TCB p_CB, U16 set_flags);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,243 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_HAL_CA.H
+ *      Purpose: Hardware Abstraction Layer for Cortex-A definitions
+ *      Rev.:    14th Jan 2014
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Definitions */
+#define INIT_CPSR_SYS   0x4000001F
+#define INIT_CPSR_USER  0x40000010
+
+#define CPSR_T_BIT      0x20
+#define CPSR_I_BIT      0x80
+#define CPSR_F_BIT      0x40
+
+#define MODE_USR        0x10
+#define MODE_FIQ        0x11
+#define MODE_IRQ        0x12
+#define MODE_SVC        0x13
+#define MODE_ABT        0x17
+#define MODE_UND        0x1B
+#define MODE_SYS        0x1F
+
+#define MAGIC_WORD      0xE25A2EA5
+
+#include "core_ca9.h"
+
+#if defined (__CC_ARM)          /* ARM Compiler */
+
+#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !defined(NO_EXCLUSIVE_ACCESS))
+ #define __USE_EXCLUSIVE_ACCESS
+#else
+ #undef  __USE_EXCLUSIVE_ACCESS
+#endif
+
+/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
+#ifdef __USE_EXCLUSIVE_ACCESS
+#pragma diag_suppress 3731
+#endif
+
+#elif defined (__GNUC__)        /* GNU Compiler */
+
+#undef  __USE_EXCLUSIVE_ACCESS
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#define __TARGET_FPU_VFP 1
+#else
+#define __TARGET_FPU_VFP 0
+#endif
+
+#define __inline inline
+#define __weak   __attribute__((weak))
+
+#elif defined (__ICCARM__)      /* IAR Compiler */
+
+#endif
+
+static U8 priority = 0xff;
+
+extern const U32 GICDistributor_BASE;
+extern const U32 GICInterface_BASE;
+
+/* GIC registers - Distributor */
+#define GICD_ICDICER0   (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */
+#define GICD_ICDISER0   (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */
+#define GICD_ICDIPR0    (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */
+#define GICD_ICDSGIR    (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */
+#define GICD_ICDICERx(irq)   *(volatile U32 *)(&GICD_ICDICER0 + irq/32)
+#define GICD_ICDISERx(irq)   *(volatile U32 *)(&GICD_ICDISER0 + irq/32)
+
+/* GIC register  - CPU Interface  */
+#define GICI_ICCPMR     (*((volatile U32 *)(GICInterface_BASE + 0x004))) /* - RW - Interrupt Priority Mask Register */
+
+#define SGI_PENDSV      0 /* SGI0 */
+#define SGI_PENDSV_BIT  ((U32)(1 << (SGI_PENDSV & 0xf)))
+
+//Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded.
+#if defined (__ICCARM__)
+#define OS_LOCK() int irq_dis = __disable_irq_iar();\
+                  priority = GICI_ICCPMR; \
+                  GICI_ICCPMR = 0xff; \
+                  GICI_ICCPMR = GICI_ICCPMR - 1; \
+                  __DSB();\
+                  if(!irq_dis) __enable_irq(); \
+
+#else
+#define OS_LOCK() int irq_dis = __disable_irq();\
+                  priority = GICI_ICCPMR; \
+                  GICI_ICCPMR = 0xff; \
+                  GICI_ICCPMR = GICI_ICCPMR - 1; \
+                  __DSB();\
+                  if(!irq_dis) __enable_irq(); \
+
+#endif
+
+//Restore priority filter. Re-enable timer and PendSV signaling
+#define OS_UNLOCK() __DSB(); \
+                    GICI_ICCPMR = priority; \
+
+#define OS_PEND_IRQ() GICD_ICDSGIR = 0x0010000 | SGI_PENDSV
+#define OS_PEND(fl,p) if(p) OS_PEND_IRQ();
+#define OS_UNPEND(fl)
+
+/* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c-
+ * OS_X_INIT enables the IRQ n in the GIC */
+#define OS_X_INIT(n) volatile char *reg; \
+                     reg = (char *)(&GICD_ICDIPR0 + n / 4); \
+                     reg += n % 4; \
+                     *reg = (char)0xff; \
+                     *reg = *reg - 1; \
+                     GICD_ICDISERx(n) = (U32)(1 << n % 32);
+#define OS_X_LOCK(n) OS_LOCK()
+#define OS_X_UNLOCK(n) OS_UNLOCK()
+#define OS_X_PEND_IRQ() OS_PEND_IRQ()
+#define OS_X_PEND(fl,p) if(p) OS_X_PEND_IRQ();
+#define OS_X_UNPEND(fl)
+
+
+/* Functions */
+#ifdef __USE_EXCLUSIVE_ACCESS
+ #define rt_inc(p)     while(__strex((__ldrex(p)+1),p))
+ #define rt_dec(p)     while(__strex((__ldrex(p)-1),p))
+#else
+#if defined (__ICCARM__)
+ #define rt_inc(p)     { int irq_dis = __disable_irq_iar();(*p)++;if(!irq_dis) __enable_irq(); }
+ #define rt_dec(p)     { int irq_dis = __disable_irq_iar();(*p)--;if(!irq_dis) __enable_irq(); }
+#else
+ #define rt_inc(p)     { int irq_dis = __disable_irq();(*p)++;if(!irq_dis) __enable_irq(); }
+ #define rt_dec(p)     { int irq_dis = __disable_irq();(*p)--;if(!irq_dis) __enable_irq(); }
+#endif /* __ICCARM__ */
+#endif /* __USE_EXCLUSIVE_ACCESS */
+
+__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
+  U32 cnt,c2;
+#ifdef __USE_EXCLUSIVE_ACCESS
+  do {
+    if ((cnt = __ldrex(count)) == size) {
+      __clrex();
+      return (cnt); }
+  } while (__strex(cnt+1, count));
+  do {
+    c2 = (cnt = __ldrex(first)) + 1;
+    if (c2 == size) c2 = 0;
+  } while (__strex(c2, first));
+#else
+  int irq_dis;
+ #if defined (__ICCARM__)
+  irq_dis = __disable_irq_iar();
+ #else
+  irq_dis = __disable_irq();
+ #endif /* __ICCARM__ */
+  if ((cnt = *count) < size) {
+    *count = cnt+1;
+    c2 = (cnt = *first) + 1;
+    if (c2 == size) c2 = 0;
+    *first = c2;
+  }
+  if(!irq_dis) __enable_irq ();
+#endif
+  return (cnt);
+}
+
+__inline static void rt_systick_init (void) {
+  /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
+  /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
+}
+
+__inline static U32 rt_systick_val (void) {
+  /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
+  /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
+  return 0;
+}
+
+__inline static U32 rt_systick_ovf (void) {
+  /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */
+  /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */
+  return 0;
+}
+
+__inline static void rt_svc_init (void) {
+  /* Register pendSV - through SGI */
+  volatile char *reg;
+
+  reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4);
+  reg += SGI_PENDSV % 4;
+  /* Write 0xff to read priority level */
+  *reg = (char)0xff;
+  /* Read priority level and set the lowest possible*/
+  *reg = *reg - 1;
+
+  GICD_ICDISERx(SGI_PENDSV) = (U32)SGI_PENDSV_BIT;
+}
+
+extern void rt_set_PSP (U32 stack);
+extern U32  rt_get_PSP (void);
+extern void os_set_env (P_TCB p_TCB);
+extern void *_alloc_box (void *box_mem);
+extern int  _free_box (void *box_mem, void *box);
+
+extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
+extern void rt_ret_val  (P_TCB p_TCB, U32 v0);
+extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
+
+extern void dbg_init (void);
+extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
+extern void dbg_task_switch (U32 task_id);
+
+#define DBG_INIT()
+#define DBG_TASK_NOTIFY(p_tcb,create)
+#define DBG_TASK_SWITCH(task_id)
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CM.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,290 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_HAL_CM.H
+ *      Purpose: Hardware Abstraction Layer for Cortex-M definitions
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Definitions */
+#define INITIAL_xPSR    0x01000000
+#define DEMCR_TRCENA    0x01000000
+#define ITM_ITMENA      0x00000001
+#define MAGIC_WORD      0xE25A2EA5
+
+#if defined (__CC_ARM)          /* ARM Compiler */
+
+#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !defined(NO_EXCLUSIVE_ACCESS))
+ #define __USE_EXCLUSIVE_ACCESS
+#else
+ #undef  __USE_EXCLUSIVE_ACCESS
+#endif
+
+/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
+#ifdef __USE_EXCLUSIVE_ACCESS
+#pragma diag_suppress 3731
+#endif
+
+#elif defined (__GNUC__)        /* GNU Compiler */
+
+#undef  __USE_EXCLUSIVE_ACCESS
+
+#if defined (__CORTEX_M0)
+#define __TARGET_ARCH_6S_M 1
+#else
+#define __TARGET_ARCH_6S_M 0
+#endif
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#define __TARGET_FPU_VFP 1
+#else
+#define __TARGET_FPU_VFP 0
+#endif
+
+#define __inline inline
+#define __weak   __attribute__((weak))
+
+#ifndef __CMSIS_GENERIC
+
+__attribute__((always_inline)) static inline void __enable_irq(void)
+{
+  __asm volatile ("cpsie i");
+}
+
+__attribute__((always_inline)) static inline U32 __disable_irq(void)
+{
+  U32 result;
+
+  __asm volatile ("mrs %0, primask" : "=r" (result));
+  __asm volatile ("cpsid i");
+  return(result & 1);
+}
+
+#endif
+
+__attribute__(( always_inline)) static inline U8 __clz(U32 value)
+{
+  U8 result;
+
+  __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
+  return(result);
+}
+
+#elif defined (__ICCARM__)      /* IAR Compiler */
+
+#undef  __USE_EXCLUSIVE_ACCESS
+
+#if (__CORE__ == __ARM6M__)
+#define __TARGET_ARCH_6S_M 1
+#else
+#define __TARGET_ARCH_6S_M 0
+#endif
+
+#if defined __ARMVFP__
+#define __TARGET_FPU_VFP 1
+#else
+#define __TARGET_FPU_VFP 0
+#endif
+
+#define __inline inline
+
+#ifndef __CMSIS_GENERIC
+
+static inline void __enable_irq(void)
+{
+  __asm volatile ("cpsie i");
+}
+
+static inline U32 __disable_irq(void)
+{
+  U32 result;
+
+  __asm volatile ("mrs %0, primask" : "=r" (result));
+  __asm volatile ("cpsid i");
+  return(result & 1);
+}
+
+#endif
+
+static inline U8 __clz(U32 value)
+{
+  U8 result;
+
+  __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
+  return(result);
+}
+
+#endif
+
+/* NVIC registers */
+#define NVIC_ST_CTRL    (*((volatile U32 *)0xE000E010))
+#define NVIC_ST_RELOAD  (*((volatile U32 *)0xE000E014))
+#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
+#define NVIC_ISER         ((volatile U32 *)0xE000E100)
+#define NVIC_ICER         ((volatile U32 *)0xE000E180)
+#if (__TARGET_ARCH_6S_M)
+#define NVIC_IP           ((volatile U32 *)0xE000E400)
+#else
+#define NVIC_IP           ((volatile U8  *)0xE000E400)
+#endif
+#define NVIC_INT_CTRL   (*((volatile U32 *)0xE000ED04))
+#define NVIC_AIR_CTRL   (*((volatile U32 *)0xE000ED0C))
+#define NVIC_SYS_PRI2   (*((volatile U32 *)0xE000ED1C))
+#define NVIC_SYS_PRI3   (*((volatile U32 *)0xE000ED20))
+
+#define OS_PEND_IRQ()   NVIC_INT_CTRL  = (1<<28)
+#define OS_PENDING      ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
+#define OS_UNPEND(fl)   NVIC_INT_CTRL  = (*fl = OS_PENDING) << 25
+#define OS_PEND(fl,p)   NVIC_INT_CTRL  = (fl | p<<2) << 26
+#define OS_LOCK()       NVIC_ST_CTRL   =  0x0005
+#define OS_UNLOCK()     NVIC_ST_CTRL   =  0x0007
+
+#define OS_X_PENDING    ((NVIC_INT_CTRL >> 28) & 1)
+#define OS_X_UNPEND(fl) NVIC_INT_CTRL  = (*fl = OS_X_PENDING) << 27
+#define OS_X_PEND(fl,p) NVIC_INT_CTRL  = (fl | p) << 28
+#if (__TARGET_ARCH_6S_M)
+#define OS_X_INIT(n)    NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
+                        NVIC_ISER[n>>5] = 1 << (n & 0x1F)
+#else
+#define OS_X_INIT(n)    NVIC_IP[n] = 0xFF; \
+                        NVIC_ISER[n>>5] = 1 << (n & 0x1F)
+#endif
+#define OS_X_LOCK(n)    NVIC_ICER[n>>5] = 1 << (n & 0x1F)
+#define OS_X_UNLOCK(n)  NVIC_ISER[n>>5] = 1 << (n & 0x1F)
+
+/* Core Debug registers */
+#define DEMCR           (*((volatile U32 *)0xE000EDFC))
+
+/* ITM registers */
+#define ITM_CONTROL     (*((volatile U32 *)0xE0000E80))
+#define ITM_ENABLE      (*((volatile U32 *)0xE0000E00))
+#define ITM_PORT30_U32  (*((volatile U32 *)0xE0000078))
+#define ITM_PORT31_U32  (*((volatile U32 *)0xE000007C))
+#define ITM_PORT31_U16  (*((volatile U16 *)0xE000007C))
+#define ITM_PORT31_U8   (*((volatile U8  *)0xE000007C))
+
+/* Variables */
+extern BIT dbg_msg;
+
+/* Functions */
+#ifdef __USE_EXCLUSIVE_ACCESS
+ #define rt_inc(p)     while(__strex((__ldrex(p)+1),p))
+ #define rt_dec(p)     while(__strex((__ldrex(p)-1),p))
+#else
+ #define rt_inc(p)     __disable_irq();(*p)++;__enable_irq();
+ #define rt_dec(p)     __disable_irq();(*p)--;__enable_irq();
+#endif
+
+__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
+  U32 cnt,c2;
+#ifdef __USE_EXCLUSIVE_ACCESS
+  do {
+    if ((cnt = __ldrex(count)) == size) {
+      __clrex();
+      return (cnt); }
+  } while (__strex(cnt+1, count));
+  do {
+    c2 = (cnt = __ldrex(first)) + 1;
+    if (c2 == size) c2 = 0;
+  } while (__strex(c2, first));
+#else
+  __disable_irq();
+  if ((cnt = *count) < size) {
+    *count = cnt+1;
+    c2 = (cnt = *first) + 1;
+    if (c2 == size) c2 = 0;
+    *first = c2;
+  }
+  __enable_irq ();
+#endif
+  return (cnt);
+}
+
+__inline static void rt_systick_init (void) {
+  NVIC_ST_RELOAD  = os_trv;
+  NVIC_ST_CURRENT = 0;
+  NVIC_ST_CTRL    = 0x0007;
+  NVIC_SYS_PRI3  |= 0xFF000000;
+}
+
+__inline static U32 rt_systick_val (void) {
+  return (os_trv - NVIC_ST_CURRENT);
+}
+
+__inline static U32 rt_systick_ovf (void) {
+  return ((NVIC_INT_CTRL >> 26) & 1);
+}
+
+__inline static void rt_svc_init (void) {
+#if !(__TARGET_ARCH_6S_M)
+  int sh,prigroup;
+#endif
+  NVIC_SYS_PRI3 |= 0x00FF0000;
+#if (__TARGET_ARCH_6S_M)
+  NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
+#else
+  sh       = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
+  prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
+  if (prigroup >= sh) {
+    sh = prigroup + 1;
+  }
+  NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
+#endif
+}
+
+extern void rt_set_PSP (U32 stack);
+extern U32  rt_get_PSP (void);
+extern void os_set_env (void);
+extern void *_alloc_box (void *box_mem);
+extern int  _free_box (void *box_mem, void *box);
+
+extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
+extern void rt_ret_val  (P_TCB p_TCB, U32 v0);
+extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
+
+extern void dbg_init (void);
+extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
+extern void dbg_task_switch (U32 task_id);
+
+#ifdef DBG_MSG
+#define DBG_INIT() dbg_init()
+#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
+#define DBG_TASK_SWITCH(task_id)      if (dbg_msg && (os_tsk.new_tsk!=os_tsk.run)) \
+                                                   dbg_task_switch(task_id)
+#else
+#define DBG_INIT()
+#define DBG_TASK_NOTIFY(p_tcb,create)
+#define DBG_TASK_SWITCH(task_id)
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_List.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,325 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_LIST.C
+ *      Purpose: Functions for the management of different lists
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+#ifdef __CORTEX_A9
+#include "rt_HAL_CA.h"
+#else
+#include "rt_HAL_CM.h"
+#endif
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* List head of chained ready tasks */
+struct OS_XCB  os_rdy;
+/* List head of chained delay tasks */
+struct OS_XCB  os_dly;
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_put_prio -----------------------------------*/
+
+void rt_put_prio (P_XCB p_CB, P_TCB p_task) {
+  /* Put task identified with "p_task" into list ordered by priority.       */
+  /* "p_CB" points to head of list; list has always an element at end with  */
+  /* a priority less than "p_task->prio".                                   */
+  P_TCB p_CB2;
+  U32 prio;
+  BOOL sem_mbx = __FALSE;
+
+  if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) {
+    sem_mbx = __TRUE;
+  }
+  prio = p_task->prio;
+  p_CB2 = p_CB->p_lnk;
+  /* Search for an entry in the list */
+  while (p_CB2 != NULL && prio <= p_CB2->prio) {
+    p_CB = (P_XCB)p_CB2;
+    p_CB2 = p_CB2->p_lnk;
+  }
+  /* Entry found, insert the task into the list */
+  p_task->p_lnk = p_CB2;
+  p_CB->p_lnk = p_task;
+  if (sem_mbx) {
+    if (p_CB2 != NULL) {
+      p_CB2->p_rlnk = p_task;
+    }
+    p_task->p_rlnk = (P_TCB)p_CB;
+  }
+  else {
+    p_task->p_rlnk = NULL;
+  }
+}
+
+
+/*--------------------------- rt_get_first ----------------------------------*/
+
+P_TCB rt_get_first (P_XCB p_CB) {
+  /* Get task at head of list: it is the task with highest priority. */
+  /* "p_CB" points to head of list. */
+  P_TCB p_first;
+
+  p_first = p_CB->p_lnk;
+  p_CB->p_lnk = p_first->p_lnk;
+  if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) {
+    if (p_first->p_lnk != NULL) {
+      p_first->p_lnk->p_rlnk = (P_TCB)p_CB;
+      p_first->p_lnk = NULL;
+    }
+    p_first->p_rlnk = NULL;
+  }
+  else {
+    p_first->p_lnk = NULL;
+  }
+  return (p_first);
+}
+
+
+/*--------------------------- rt_put_rdy_first ------------------------------*/
+
+void rt_put_rdy_first (P_TCB p_task) {
+  /* Put task identified with "p_task" at the head of the ready list. The   */
+  /* task must have at least a priority equal to highest priority in list.  */
+  p_task->p_lnk = os_rdy.p_lnk;
+  p_task->p_rlnk = NULL;
+  os_rdy.p_lnk = p_task;
+}
+
+
+/*--------------------------- rt_get_same_rdy_prio --------------------------*/
+
+P_TCB rt_get_same_rdy_prio (void) {
+  /* Remove a task of same priority from ready list if any exists. Other-   */
+  /* wise return NULL.                                                      */
+  P_TCB p_first;
+
+  p_first = os_rdy.p_lnk;
+  if (p_first->prio == os_tsk.run->prio) {
+    os_rdy.p_lnk = os_rdy.p_lnk->p_lnk;
+    return (p_first);
+  }
+  return (NULL);
+}
+
+
+/*--------------------------- rt_resort_prio --------------------------------*/
+
+void rt_resort_prio (P_TCB p_task) {
+  /* Re-sort ordered lists after the priority of 'p_task' has changed.      */
+  P_TCB p_CB;
+
+  if (p_task->p_rlnk == NULL) {
+    if (p_task->state == READY) {
+      /* Task is chained into READY list. */
+      p_CB = (P_TCB)&os_rdy;
+      goto res;
+    }
+  }
+  else {
+    p_CB = p_task->p_rlnk;
+    while (p_CB->cb_type == TCB) {
+      /* Find a header of this task chain list. */
+      p_CB = p_CB->p_rlnk;
+    }
+res:rt_rmv_list (p_task);
+    rt_put_prio ((P_XCB)p_CB, p_task);
+  }
+}
+
+
+/*--------------------------- rt_put_dly ------------------------------------*/
+
+void rt_put_dly (P_TCB p_task, U16 delay) {
+  /* Put a task identified with "p_task" into chained delay wait list using */
+  /* a delay value of "delay".                                              */
+  P_TCB p;
+  U32 delta,idelay = delay;
+
+  p = (P_TCB)&os_dly;
+  if (p->p_dlnk == NULL) {
+    /* Delay list empty */
+    delta = 0;
+    goto last;
+  }
+  delta = os_dly.delta_time;
+  while (delta < idelay) {
+    if (p->p_dlnk == NULL) {
+      /* End of list found */
+last: p_task->p_dlnk = NULL;
+      p->p_dlnk = p_task;
+      p_task->p_blnk = p;
+      p->delta_time = (U16)(idelay - delta);
+      p_task->delta_time = 0;
+      return;
+    }
+    p = p->p_dlnk;
+    delta += p->delta_time;
+  }
+  /* Right place found */
+  p_task->p_dlnk = p->p_dlnk;
+  p->p_dlnk = p_task;
+  p_task->p_blnk = p;
+  if (p_task->p_dlnk != NULL) {
+    p_task->p_dlnk->p_blnk = p_task;
+  }
+  p_task->delta_time = (U16)(delta - idelay);
+  p->delta_time -= p_task->delta_time;
+}
+
+
+/*--------------------------- rt_dec_dly ------------------------------------*/
+
+void rt_dec_dly (void) {
+  /* Decrement delta time of list head: remove tasks having a value of zero.*/
+  P_TCB p_rdy;
+
+  if (os_dly.p_dlnk == NULL) {
+    return;
+  }
+  os_dly.delta_time--;
+  while ((os_dly.delta_time == 0) && (os_dly.p_dlnk != NULL)) {
+    p_rdy = os_dly.p_dlnk;
+    if (p_rdy->p_rlnk != NULL) {
+      /* Task is really enqueued, remove task from semaphore/mailbox */
+      /* timeout waiting list. */
+      p_rdy->p_rlnk->p_lnk = p_rdy->p_lnk;
+      if (p_rdy->p_lnk != NULL) {
+        p_rdy->p_lnk->p_rlnk = p_rdy->p_rlnk;
+        p_rdy->p_lnk = NULL;
+      }
+      p_rdy->p_rlnk = NULL;
+    }
+    rt_put_prio (&os_rdy, p_rdy);
+    os_dly.delta_time = p_rdy->delta_time;
+    if (p_rdy->state == WAIT_ITV) {
+      /* Calculate the next time for interval wait. */
+      p_rdy->delta_time = p_rdy->interval_time + (U16)os_time;
+    }
+    p_rdy->state   = READY;
+    os_dly.p_dlnk = p_rdy->p_dlnk;
+    if (p_rdy->p_dlnk != NULL) {
+      p_rdy->p_dlnk->p_blnk =  (P_TCB)&os_dly;
+      p_rdy->p_dlnk = NULL;
+    }
+    p_rdy->p_blnk = NULL;
+  }
+}
+
+
+/*--------------------------- rt_rmv_list -----------------------------------*/
+
+void rt_rmv_list (P_TCB p_task) {
+  /* Remove task identified with "p_task" from ready, semaphore or mailbox  */
+  /* waiting list if enqueued.                                              */
+  P_TCB p_b;
+
+  if (p_task->p_rlnk != NULL) {
+    /* A task is enqueued in semaphore / mailbox waiting list. */
+    p_task->p_rlnk->p_lnk = p_task->p_lnk;
+    if (p_task->p_lnk != NULL) {
+      p_task->p_lnk->p_rlnk = p_task->p_rlnk;
+    }
+    return;
+  }
+
+  p_b = (P_TCB)&os_rdy;
+  while (p_b != NULL) {
+    /* Search the ready list for task "p_task" */
+    if (p_b->p_lnk == p_task) {
+      p_b->p_lnk = p_task->p_lnk;
+      return;
+    }
+    p_b = p_b->p_lnk;
+  }
+}
+
+
+/*--------------------------- rt_rmv_dly ------------------------------------*/
+
+void rt_rmv_dly (P_TCB p_task) {
+  /* Remove task identified with "p_task" from delay list if enqueued.      */
+  P_TCB p_b;
+
+  p_b = p_task->p_blnk;
+  if (p_b != NULL) {
+    /* Task is really enqueued */
+    p_b->p_dlnk = p_task->p_dlnk;
+    if (p_task->p_dlnk != NULL) {
+      /* 'p_task' is in the middle of list */
+      p_b->delta_time += p_task->delta_time;
+      p_task->p_dlnk->p_blnk = p_b;
+      p_task->p_dlnk = NULL;
+    }
+    else {
+      /* 'p_task' is at the end of list */
+      p_b->delta_time = 0;
+    }
+    p_task->p_blnk = NULL;
+  }
+}
+
+
+/*--------------------------- rt_psq_enq ------------------------------------*/
+
+void rt_psq_enq (OS_ID entry, U32 arg) {
+  /* Insert post service request "entry" into ps-queue. */
+  U32 idx;
+
+  idx = rt_inc_qi (os_psq->size, &os_psq->count, &os_psq->first);
+  if (idx < os_psq->size) {
+    os_psq->q[idx].id  = entry;
+    os_psq->q[idx].arg = arg;
+  }
+  else {
+    os_error (OS_ERR_FIFO_OVF);
+  }
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_List.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,68 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_LIST.H
+ *      Purpose: Functions for the management of different lists
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Definitions */
+
+/* Values for 'cb_type' */
+#define TCB             0
+#define MCB             1
+#define SCB             2
+#define MUCB            3
+#define HCB             4
+
+/* Variables */
+extern struct OS_XCB os_rdy;
+extern struct OS_XCB os_dly;
+
+/* Functions */
+extern void  rt_put_prio      (P_XCB p_CB, P_TCB p_task);
+extern P_TCB rt_get_first     (P_XCB p_CB);
+extern void  rt_put_rdy_first (P_TCB p_task);
+extern P_TCB rt_get_same_rdy_prio (void);
+extern void  rt_resort_prio   (P_TCB p_task);
+extern void  rt_put_dly       (P_TCB p_task, U16 delay);
+extern void  rt_dec_dly       (void);
+extern void  rt_rmv_list      (P_TCB p_task);
+extern void  rt_rmv_dly       (P_TCB p_task);
+extern void  rt_psq_enq       (OS_ID entry, U32 arg);
+
+/* This is a fast macro generating in-line code */
+#define rt_rdy_prio(void) (os_rdy.p_lnk->prio)
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,297 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MAILBOX.C
+ *      Purpose: Implements waits and wake-ups for mailbox messages
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Mailbox.h"
+#include "rt_MemBox.h"
+#include "rt_Task.h"
+#ifdef __CORTEX_A9
+#include "rt_HAL_CA.h"
+#else
+#include "rt_HAL_CM.h"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_mbx_init -----------------------------------*/
+
+void rt_mbx_init (OS_ID mailbox, U16 mbx_size) {
+  /* Initialize a mailbox */
+  P_MCB p_MCB = mailbox;
+
+  p_MCB->cb_type = MCB;
+  p_MCB->state   = 0;
+  p_MCB->isr_st  = 0;
+  p_MCB->p_lnk   = NULL;
+  p_MCB->first   = 0;
+  p_MCB->last    = 0;
+  p_MCB->count   = 0;
+  p_MCB->size    = (mbx_size + sizeof(void *) - sizeof(struct OS_MCB)) /
+                                                     (U32)sizeof (void *);
+}
+
+
+/*--------------------------- rt_mbx_send -----------------------------------*/
+
+OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout) {
+  /* Send message to a mailbox */
+  P_MCB p_MCB = mailbox;
+  P_TCB p_TCB;
+
+  if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 1)) {
+    /* A task is waiting for message */
+    p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+    rt_ret_val2(p_TCB, 0x10/*osEventMessage*/, (U32)p_msg);
+#else
+    *p_TCB->msg = p_msg;
+    rt_ret_val (p_TCB, OS_R_MBX);
+#endif
+    rt_rmv_dly (p_TCB);
+    rt_dispatch (p_TCB);
+  }
+  else {
+    /* Store message in mailbox queue */
+    if (p_MCB->count == p_MCB->size) {
+      /* No free message entry, wait for one. If message queue is full, */
+      /* then no task is waiting for message. The 'p_MCB->p_lnk' list   */
+      /* pointer can now be reused for send message waits task list.    */
+      if (timeout == 0) {
+        return (OS_R_TMO);
+      }
+      if (p_MCB->p_lnk != NULL) {
+        rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+      }
+      else {
+        p_MCB->p_lnk = os_tsk.run;
+        os_tsk.run->p_lnk  = NULL;
+        os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+        /* Task is waiting to send a message */
+        p_MCB->state = 2;
+      }
+      os_tsk.run->msg = p_msg;
+      rt_block (timeout, WAIT_MBX);
+      return (OS_R_TMO);
+    }
+    /* Yes, there is a free entry in a mailbox. */
+    p_MCB->msg[p_MCB->first] = p_msg;
+    rt_inc (&p_MCB->count);
+    if (++p_MCB->first == p_MCB->size) {
+      p_MCB->first = 0;
+    }
+  }
+  return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mbx_wait -----------------------------------*/
+
+OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout) {
+  /* Receive a message; possibly wait for it */
+  P_MCB p_MCB = mailbox;
+  P_TCB p_TCB;
+
+  /* If a message is available in the fifo buffer */
+  /* remove it from the fifo buffer and return. */
+  if (p_MCB->count) {
+    *message = p_MCB->msg[p_MCB->last];
+    if (++p_MCB->last == p_MCB->size) {
+      p_MCB->last = 0;
+    }
+    if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 2)) {
+      /* A task is waiting to send message */
+      p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+      rt_ret_val(p_TCB, 0/*osOK*/);
+#else
+      rt_ret_val(p_TCB, OS_R_OK);
+#endif
+      p_MCB->msg[p_MCB->first] = p_TCB->msg;
+      if (++p_MCB->first == p_MCB->size) {
+        p_MCB->first = 0;
+      }
+      rt_rmv_dly (p_TCB);
+      rt_dispatch (p_TCB);
+    }
+    else {
+      rt_dec (&p_MCB->count);
+    }
+    return (OS_R_OK);
+  }
+  /* No message available: wait for one */
+  if (timeout == 0) {
+    return (OS_R_TMO);
+  }
+  if (p_MCB->p_lnk != NULL) {
+    rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+  }
+  else {
+    p_MCB->p_lnk = os_tsk.run;
+    os_tsk.run->p_lnk = NULL;
+    os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+    /* Task is waiting to receive a message */
+    p_MCB->state = 1;
+  }
+  rt_block(timeout, WAIT_MBX);
+#ifndef __CMSIS_RTOS
+  os_tsk.run->msg = message;
+#endif
+  return (OS_R_TMO);
+}
+
+
+/*--------------------------- rt_mbx_check ----------------------------------*/
+
+OS_RESULT rt_mbx_check (OS_ID mailbox) {
+  /* Check for free space in a mailbox. Returns the number of messages     */
+  /* that can be stored to a mailbox. It returns 0 when mailbox is full.   */
+  P_MCB p_MCB = mailbox;
+
+  return (p_MCB->size - p_MCB->count);
+}
+
+
+/*--------------------------- isr_mbx_send ----------------------------------*/
+
+void isr_mbx_send (OS_ID mailbox, void *p_msg) {
+  /* Same function as "os_mbx_send", but to be called by ISRs. */
+  P_MCB p_MCB = mailbox;
+
+  rt_psq_enq (p_MCB, (U32)p_msg);
+  rt_psh_req ();
+}
+
+
+/*--------------------------- isr_mbx_receive -------------------------------*/
+
+OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message) {
+  /* Receive a message in the interrupt function. The interrupt function   */
+  /* should not wait for a message since this would block the rtx os.      */
+  P_MCB p_MCB = mailbox;
+
+  if (p_MCB->count) {
+    /* A message is available in the fifo buffer. */
+    *message = p_MCB->msg[p_MCB->last];
+    if (p_MCB->state == 2) {
+      /* A task is locked waiting to send message */
+      rt_psq_enq (p_MCB, 0);
+      rt_psh_req ();
+    }
+    rt_dec (&p_MCB->count);
+    if (++p_MCB->last == p_MCB->size) {
+      p_MCB->last = 0;
+    }
+    return (OS_R_MBX);
+  }
+  return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mbx_psh ------------------------------------*/
+
+void rt_mbx_psh (P_MCB p_CB, void *p_msg) {
+  /* Store the message to the mailbox queue or pass it to task directly. */
+  P_TCB p_TCB;
+  void *mem;
+
+  if (p_CB->p_lnk != NULL) switch (p_CB->state) {
+#ifdef __CMSIS_RTOS
+    case 3:
+      /* Task is waiting to allocate memory, remove it from the waiting list */
+      mem = rt_alloc_box(p_msg);
+      if (mem == NULL) break;
+      p_TCB = rt_get_first ((P_XCB)p_CB);
+      rt_ret_val(p_TCB, (U32)mem);
+      p_TCB->state = READY;
+      rt_rmv_dly (p_TCB);
+      rt_put_prio (&os_rdy, p_TCB);
+      break;
+#endif
+    case 2:
+      /* Task is waiting to send a message, remove it from the waiting list */
+      p_TCB = rt_get_first ((P_XCB)p_CB);
+#ifdef __CMSIS_RTOS
+      rt_ret_val(p_TCB, 0/*osOK*/);
+#else
+      rt_ret_val(p_TCB, OS_R_OK);
+#endif
+      p_CB->msg[p_CB->first] = p_TCB->msg;
+      rt_inc (&p_CB->count);
+      if (++p_CB->first == p_CB->size) {
+        p_CB->first = 0;
+      }
+      p_TCB->state = READY;
+      rt_rmv_dly (p_TCB);
+      rt_put_prio (&os_rdy, p_TCB);
+      break;
+    case 1:
+      /* Task is waiting for a message, pass the message to the task directly */
+      p_TCB = rt_get_first ((P_XCB)p_CB);
+#ifdef __CMSIS_RTOS
+      rt_ret_val2(p_TCB, 0x10/*osEventMessage*/, (U32)p_msg);
+#else
+      *p_TCB->msg = p_msg;
+      rt_ret_val (p_TCB, OS_R_MBX);
+#endif
+      p_TCB->state = READY;
+      rt_rmv_dly (p_TCB);
+      rt_put_prio (&os_rdy, p_TCB);
+      break;
+  } else {
+    /* No task is waiting for a message, store it to the mailbox queue */
+    if (p_CB->count < p_CB->size) {
+      p_CB->msg[p_CB->first] = p_msg;
+      rt_inc (&p_CB->count);
+      if (++p_CB->first == p_CB->size) {
+        p_CB->first = 0;
+      }
+    }
+    else {
+      os_error (OS_ERR_MBX_OVF);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Mailbox.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,49 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MAILBOX.H
+ *      Purpose: Implements waits and wake-ups for mailbox messages
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern void      rt_mbx_init  (OS_ID mailbox, U16 mbx_size);
+extern OS_RESULT rt_mbx_send  (OS_ID mailbox, void *p_msg,    U16 timeout);
+extern OS_RESULT rt_mbx_wait  (OS_ID mailbox, void **message, U16 timeout);
+extern OS_RESULT rt_mbx_check (OS_ID mailbox);
+extern void      isr_mbx_send (OS_ID mailbox, void *p_msg);
+extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message);
+extern void      rt_mbx_psh   (P_MCB p_CB,    void *p_msg);
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,180 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MEMBOX.C
+ *      Purpose: Interface functions for fixed memory block management system
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_MemBox.h"
+#ifdef __CORTEX_A9
+#include "rt_HAL_CA.h"
+#else
+#include "rt_HAL_CM.h"
+#endif
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- _init_box -------------------------------------*/
+
+int _init_box  (void *box_mem, U32 box_size, U32 blk_size) {
+  /* Initialize memory block system, returns 0 if OK, 1 if fails. */
+  void *end;
+  void *blk;
+  void *next;
+  U32  sizeof_bm;
+
+  /* Create memory structure. */
+  if (blk_size & BOX_ALIGN_8) {
+    /* Memory blocks 8-byte aligned. */
+    blk_size = ((blk_size & ~BOX_ALIGN_8) + 7) & ~7;
+    sizeof_bm = (sizeof (struct OS_BM) + 7) & ~7;
+  }
+  else {
+    /* Memory blocks 4-byte aligned. */
+    blk_size = (blk_size + 3) & ~3;
+    sizeof_bm = sizeof (struct OS_BM);
+  }
+  if (blk_size == 0) {
+    return (1);
+  }
+  if ((blk_size + sizeof_bm) > box_size) {
+    return (1);
+  }
+  /* Create a Memory structure. */
+  blk = ((U8 *) box_mem) + sizeof_bm;
+  ((P_BM) box_mem)->free = blk;
+  end = ((U8 *) box_mem) + box_size;
+  ((P_BM) box_mem)->end      = end;
+  ((P_BM) box_mem)->blk_size = blk_size;
+
+  /* Link all free blocks using offsets. */
+  end = ((U8 *) end) - blk_size;
+  while (1)  {
+    next = ((U8 *) blk) + blk_size;
+    if (next > end)  break;
+    *((void **)blk) = next;
+    blk = next;
+  }
+  /* end marker */
+  *((void **)blk) = 0;
+  return (0);
+}
+
+/*--------------------------- rt_alloc_box ----------------------------------*/
+
+void *rt_alloc_box (void *box_mem) {
+  /* Allocate a memory block and return start address. */
+  void **free;
+#ifndef __USE_EXCLUSIVE_ACCESS
+  int  irq_dis;
+
+
+#if defined (__ICCARM__)
+  irq_dis = __disable_irq_iar();
+#else
+  irq_dis = __disable_irq ();
+#endif /* __ICCARM__ */
+  free = ((P_BM) box_mem)->free;
+  if (free) {
+    ((P_BM) box_mem)->free = *free;
+  }
+  if (!irq_dis) __enable_irq ();
+#else
+  do {
+    if ((free = (void **)__ldrex(&((P_BM) box_mem)->free)) == 0) {
+      __clrex();
+      break;
+    }
+  } while (__strex((U32)*free, &((P_BM) box_mem)->free));
+#endif
+  return (free);
+}
+
+
+/*--------------------------- _calloc_box -----------------------------------*/
+
+void *_calloc_box (void *box_mem)  {
+  /* Allocate a 0-initialized memory block and return start address. */
+  void *free;
+  U32 *p;
+  U32 i;
+
+  free = _alloc_box (box_mem);
+  if (free)  {
+    p = free;
+    for (i = ((P_BM) box_mem)->blk_size; i; i -= 4)  {
+      *p = 0;
+      p++;
+    }
+  }
+  return (free);
+}
+
+
+/*--------------------------- rt_free_box -----------------------------------*/
+
+int rt_free_box (void *box_mem, void *box) {
+  /* Free a memory block, returns 0 if OK, 1 if box does not belong to box_mem */
+#ifndef __USE_EXCLUSIVE_ACCESS
+  int irq_dis;
+#endif
+
+  if (box < box_mem || box >= ((P_BM) box_mem)->end) {
+    return (1);
+  }
+
+#ifndef __USE_EXCLUSIVE_ACCESS
+#if defined (__ICCARM__)
+  irq_dis = __disable_irq_iar();
+#else
+  irq_dis = __disable_irq ();
+#endif /* __ICCARM__ */
+  *((void **)box) = ((P_BM) box_mem)->free;
+  ((P_BM) box_mem)->free = box;
+  if (!irq_dis) __enable_irq ();
+#else
+  do {
+    *((void **)box) = (void *)__ldrex(&((P_BM) box_mem)->free);
+  } while (__strex ((U32)box, &((P_BM) box_mem)->free));
+#endif
+  return (0);
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_MemBox.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,47 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MEMBOX.H
+ *      Purpose: Interface functions for fixed memory block management system
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+#define rt_init_box     _init_box
+#define rt_calloc_box   _calloc_box
+extern int     _init_box   (void *box_mem, U32 box_size, U32 blk_size);
+extern void *rt_alloc_box  (void *box_mem);
+extern void *  _calloc_box (void *box_mem);
+extern int   rt_free_box   (void *box_mem, void *box);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Memory.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,141 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MEMORY.C
+ *      Purpose: Interface functions for Dynamic Memory Management System
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "rt_Memory.h"
+
+
+/* Functions */
+
+// Initialize Dynamic Memory pool
+//   Parameters:
+//     pool:    Pointer to memory pool
+//     size:    Size of memory pool in bytes
+//   Return:    0 - OK, 1 - Error
+
+int rt_init_mem (void *pool, U32 size) {
+  MEMP *ptr;
+
+  if ((pool == NULL) || (size < sizeof(MEMP))) return (1);
+
+  ptr = (MEMP *)pool;
+  ptr->next = (MEMP *)((U32)pool + size - sizeof(MEMP *));
+  ptr->next->next = NULL;
+  ptr->len = 0;
+
+  return (0);
+}
+
+// Allocate Memory from Memory pool
+//   Parameters:
+//     pool:    Pointer to memory pool
+//     size:    Size of memory in bytes to allocate
+//   Return:    Pointer to allocated memory
+
+void *rt_alloc_mem (void *pool, U32 size) {
+  MEMP *p, *p_search, *p_new;
+  U32   hole_size;
+
+  if ((pool == NULL) || (size == 0)) return NULL;
+
+  /* Add header offset to 'size' */
+  size += sizeof(MEMP);
+  /* Make sure that block is 4-byte aligned  */
+  size = (size + 3) & ~3;
+
+  p_search = (MEMP *)pool;
+  while (1) {
+    hole_size  = (U32)p_search->next - (U32)p_search;
+    hole_size -= p_search->len;
+    /* Check if hole size is big enough */
+    if (hole_size >= size) break;
+    p_search = p_search->next;
+    if (p_search->next == NULL) {
+      /* Failed, we are at the end of the list */
+      return NULL;
+    }
+  }
+
+  if (p_search->len == 0) {
+    /* No block is allocated, set the Length of the first element */
+    p_search->len = size;
+    p = (MEMP *)(((U32)p_search) + sizeof(MEMP));
+  } else {
+    /* Insert new list element into the memory list */
+    p_new       = (MEMP *)((U32)p_search + p_search->len);
+    p_new->next = p_search->next;
+    p_new->len  = size;
+    p_search->next = p_new;
+    p = (MEMP *)(((U32)p_new) + sizeof(MEMP));
+  }
+
+  return (p);
+}
+
+// Free Memory and return it to Memory pool
+//   Parameters:
+//     pool:    Pointer to memory pool
+//     mem:     Pointer to memory to free
+//   Return:    0 - OK, 1 - Error
+
+int rt_free_mem (void *pool, void *mem) {
+  MEMP *p_search, *p_prev, *p_return;
+
+  if ((pool == NULL) || (mem == NULL)) return (1);
+
+  p_return = (MEMP *)((U32)mem - sizeof(MEMP));
+
+  /* Set list header */
+  p_prev = NULL;
+  p_search = (MEMP *)pool;
+  while (p_search != p_return) {
+    p_prev   = p_search;
+    p_search = p_search->next;
+    if (p_search == NULL) {
+      /* Valid Memory block not found */
+      return (1);
+    }
+  }
+
+  if (p_prev == NULL) {
+    /* First block to be released, only set length to 0 */
+    p_search->len = 0;
+  } else {
+    /* Discard block from chain list */
+    p_prev->next = p_search->next;
+  }
+
+  return (0);
+}
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Memory.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,45 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MEMORY.H
+ *      Purpose: Interface functions for Dynamic Memory Management System
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Types */
+typedef struct mem {              /* << Memory Pool management struct >>     */
+  struct mem *next;               /* Next Memory Block in the list           */
+  U32         len;                /* Length of data block                    */
+} MEMP;
+
+/* Functions */
+extern int   rt_init_mem  (void *pool, U32  size);
+extern void *rt_alloc_mem (void *pool, U32  size);
+extern int   rt_free_mem  (void *pool, void *mem);
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,268 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MUTEX.C
+ *      Purpose: Implements mutex synchronization objects
+ *      Rev.:    V4.73
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Mutex.h"
+#ifdef __CORTEX_A9
+#include "rt_HAL_CA.h"
+#else
+#include "rt_HAL_CM.h"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_mut_init -----------------------------------*/
+
+void rt_mut_init (OS_ID mutex) {
+  /* Initialize a mutex object */
+  P_MUCB p_MCB = mutex;
+
+  p_MCB->cb_type = MUCB;
+  p_MCB->level   = 0;
+  p_MCB->p_lnk   = NULL;
+  p_MCB->owner   = NULL;
+  p_MCB->p_mlnk  = NULL;
+}
+
+
+/*--------------------------- rt_mut_delete ---------------------------------*/
+
+#ifdef __CMSIS_RTOS
+OS_RESULT rt_mut_delete (OS_ID mutex) {
+  /* Delete a mutex object */
+  P_MUCB p_MCB = mutex;
+  P_TCB  p_TCB;
+  P_MUCB p_mlnk;
+  U8     prio;
+
+  __DMB();
+  /* Restore owner task's priority. */
+  if (p_MCB->level != 0) {
+
+    p_TCB = p_MCB->owner;
+
+    /* Remove mutex from task mutex owner list. */
+    p_mlnk = p_TCB->p_mlnk;
+    if (p_mlnk == p_MCB) {
+      p_TCB->p_mlnk = p_MCB->p_mlnk;
+    }
+    else {
+      while (p_mlnk) {
+        if (p_mlnk->p_mlnk == p_MCB) {
+          p_mlnk->p_mlnk = p_MCB->p_mlnk;
+          break;
+        }
+        p_mlnk = p_mlnk->p_mlnk;
+      }
+    }
+
+    /* Restore owner task's priority. */
+    prio = p_TCB->prio_base;
+    p_mlnk = p_TCB->p_mlnk;
+    while (p_mlnk) {
+      if (p_mlnk->p_lnk && (p_mlnk->p_lnk->prio > prio)) {
+        /* A task with higher priority is waiting for mutex. */
+        prio = p_mlnk->p_lnk->prio;
+      }
+      p_mlnk = p_mlnk->p_mlnk;
+    }
+    if (p_TCB->prio != prio) {
+      p_TCB->prio = prio;
+      if (p_TCB != os_tsk.run) {
+        rt_resort_prio (p_TCB);
+    }
+  }
+
+  }
+
+  while (p_MCB->p_lnk != NULL) {
+    /* A task is waiting for mutex. */
+    p_TCB = rt_get_first ((P_XCB)p_MCB);
+    rt_ret_val(p_TCB, 0/*osOK*/);
+    rt_rmv_dly(p_TCB);
+    p_TCB->state = READY;
+    rt_put_prio (&os_rdy, p_TCB);
+  }
+
+  if (os_rdy.p_lnk && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
+    /* preempt running task */
+    rt_put_prio (&os_rdy, os_tsk.run);
+    os_tsk.run->state = READY;
+    rt_dispatch (NULL);
+  }
+
+  p_MCB->cb_type = 0;
+
+  return (OS_R_OK);
+}
+#endif
+
+
+/*--------------------------- rt_mut_release --------------------------------*/
+
+OS_RESULT rt_mut_release (OS_ID mutex) {
+  /* Release a mutex object */
+  P_MUCB p_MCB = mutex;
+  P_TCB  p_TCB;
+  P_MUCB p_mlnk;
+  U8     prio;
+
+  if (p_MCB->level == 0 || p_MCB->owner != os_tsk.run) {
+    /* Unbalanced mutex release or task is not the owner */
+    return (OS_R_NOK);
+  }
+  __DMB();
+  if (--p_MCB->level != 0) {
+    return (OS_R_OK);
+  }
+
+  /* Remove mutex from task mutex owner list. */
+  p_mlnk = os_tsk.run->p_mlnk;
+  if (p_mlnk == p_MCB) {
+    os_tsk.run->p_mlnk = p_MCB->p_mlnk;
+  }
+  else {
+    while (p_mlnk) {
+      if (p_mlnk->p_mlnk == p_MCB) {
+        p_mlnk->p_mlnk = p_MCB->p_mlnk;
+        break;
+      }
+      p_mlnk = p_mlnk->p_mlnk;
+    }
+  }
+
+  /* Restore owner task's priority. */
+  prio = os_tsk.run->prio_base;
+  p_mlnk = os_tsk.run->p_mlnk;
+  while (p_mlnk) {
+    if (p_mlnk->p_lnk && (p_mlnk->p_lnk->prio > prio)) {
+      /* A task with higher priority is waiting for mutex. */
+      prio = p_mlnk->p_lnk->prio;
+    }
+    p_mlnk = p_mlnk->p_mlnk;
+  }
+  os_tsk.run->prio = prio;
+
+  if (p_MCB->p_lnk != NULL) {
+    /* A task is waiting for mutex. */
+    p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+    rt_ret_val(p_TCB, 0/*osOK*/);
+#else
+    rt_ret_val(p_TCB, OS_R_MUT);
+#endif
+    rt_rmv_dly (p_TCB);
+    /* A waiting task becomes the owner of this mutex. */
+    p_MCB->level     = 1;
+    p_MCB->owner     = p_TCB;
+    p_MCB->p_mlnk = p_TCB->p_mlnk;
+    p_TCB->p_mlnk = p_MCB; 
+    /* Priority inversion, check which task continues. */
+    if (os_tsk.run->prio >= rt_rdy_prio()) {
+      rt_dispatch (p_TCB);
+    }
+    else {
+      /* Ready task has higher priority than running task. */
+      rt_put_prio (&os_rdy, os_tsk.run);
+      rt_put_prio (&os_rdy, p_TCB);
+      os_tsk.run->state = READY;
+      p_TCB->state      = READY;
+      rt_dispatch (NULL);
+    }
+  }
+  else {
+    /* Check if own priority lowered by priority inversion. */
+    if (rt_rdy_prio() > os_tsk.run->prio) {
+      rt_put_prio (&os_rdy, os_tsk.run);
+      os_tsk.run->state = READY;
+      rt_dispatch (NULL);
+    }
+  }
+  return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mut_wait -----------------------------------*/
+
+OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout) {
+  /* Wait for a mutex, continue when mutex is free. */
+  P_MUCB p_MCB = mutex;
+
+  if (p_MCB->level == 0) {
+    p_MCB->owner = os_tsk.run;
+    p_MCB->p_mlnk = os_tsk.run->p_mlnk;
+    os_tsk.run->p_mlnk = p_MCB; 
+    goto inc;
+  }
+  if (p_MCB->owner == os_tsk.run) {
+    /* OK, running task is the owner of this mutex. */
+inc:p_MCB->level++;
+    __DMB();
+    return (OS_R_OK);
+  }
+  /* Mutex owned by another task, wait until released. */
+  if (timeout == 0) {
+    return (OS_R_TMO);
+  }
+  /* Raise the owner task priority if lower than current priority. */
+  /* This priority inversion is called priority inheritance.       */
+  if (p_MCB->owner->prio < os_tsk.run->prio) {
+    p_MCB->owner->prio = os_tsk.run->prio;
+    rt_resort_prio (p_MCB->owner);
+  }
+  if (p_MCB->p_lnk != NULL) {
+    rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+  }
+  else {
+    p_MCB->p_lnk = os_tsk.run;
+    os_tsk.run->p_lnk  = NULL;
+    os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+  }
+  rt_block(timeout, WAIT_MUT);
+  return (OS_R_TMO);
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Mutex.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,45 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_MUTEX.H
+ *      Purpose: Implements mutex synchronization objects
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern void      rt_mut_init    (OS_ID mutex);
+extern OS_RESULT rt_mut_delete  (OS_ID mutex);
+extern OS_RESULT rt_mut_release (OS_ID mutex);
+extern OS_RESULT rt_mut_wait    (OS_ID mutex, U16 timeout);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Robin.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,89 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_ROBIN.C
+ *      Purpose: Round Robin Task switching
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+#include "rt_Robin.h"
+#ifdef __CORTEX_A9
+#include "rt_HAL_CA.h"
+#else
+#include "rt_HAL_CM.h"
+#endif
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+struct OS_ROBIN os_robin;
+
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- rt_init_robin ---------------------------------*/
+
+__weak void rt_init_robin (void) {
+  /* Initialize Round Robin variables. */
+  os_robin.task = NULL;
+  os_robin.tout = (U16)os_rrobin;
+}
+
+/*--------------------------- rt_chk_robin ----------------------------------*/
+
+__weak void rt_chk_robin (void) {
+  /* Check if Round Robin timeout expired and switch to the next ready task.*/
+  P_TCB p_new;
+
+  if (os_robin.task != os_rdy.p_lnk) {
+    /* New task was suspended, reset Round Robin timeout. */
+    os_robin.task = os_rdy.p_lnk;
+    os_robin.time = (U16)os_time + os_robin.tout - 1;
+  }
+  if (os_robin.time == (U16)os_time) {
+    /* Round Robin timeout has expired, swap Robin tasks. */
+    os_robin.task = NULL;
+    p_new = rt_get_first (&os_rdy);
+    rt_put_prio ((P_XCB)&os_rdy, p_new);
+  }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Robin.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,46 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_ROBIN.H
+ *      Purpose: Round Robin Task switching definitions
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Variables */
+extern struct OS_ROBIN os_robin;
+
+/* Functions */
+extern void rt_init_robin (void);
+extern void rt_chk_robin  (void);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,192 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_SEMAPHORE.C
+ *      Purpose: Implements binary and counting semaphores
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Semaphore.h"
+#ifdef __CORTEX_A9
+#include "rt_HAL_CA.h"
+#else
+#include "rt_HAL_CM.h"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_sem_init -----------------------------------*/
+
+void rt_sem_init (OS_ID semaphore, U16 token_count) {
+  /* Initialize a semaphore */
+  P_SCB p_SCB = semaphore;
+
+  p_SCB->cb_type = SCB;
+  p_SCB->p_lnk  = NULL;
+  p_SCB->tokens = token_count;
+}
+
+
+/*--------------------------- rt_sem_delete ---------------------------------*/
+
+#ifdef __CMSIS_RTOS
+OS_RESULT rt_sem_delete (OS_ID semaphore) {
+  /* Delete semaphore */
+  P_SCB p_SCB = semaphore;
+  P_TCB p_TCB;
+
+  __DMB();
+  while (p_SCB->p_lnk != NULL) {
+    /* A task is waiting for token */
+    p_TCB = rt_get_first ((P_XCB)p_SCB);
+    rt_ret_val(p_TCB, 0);
+    rt_rmv_dly(p_TCB);
+    p_TCB->state = READY;
+    rt_put_prio (&os_rdy, p_TCB);
+  }
+
+  if (os_rdy.p_lnk && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
+    /* preempt running task */
+    rt_put_prio (&os_rdy, os_tsk.run);
+    os_tsk.run->state = READY;
+    rt_dispatch (NULL);
+  }
+
+  p_SCB->cb_type = 0;
+
+  return (OS_R_OK);
+}
+#endif
+
+
+/*--------------------------- rt_sem_send -----------------------------------*/
+
+OS_RESULT rt_sem_send (OS_ID semaphore) {
+  /* Return a token to semaphore */
+  P_SCB p_SCB = semaphore;
+  P_TCB p_TCB;
+
+  __DMB();
+  if (p_SCB->p_lnk != NULL) {
+    /* A task is waiting for token */
+    p_TCB = rt_get_first ((P_XCB)p_SCB);
+#ifdef __CMSIS_RTOS
+    rt_ret_val(p_TCB, 1);
+#else
+    rt_ret_val(p_TCB, OS_R_SEM);
+#endif
+    rt_rmv_dly (p_TCB);
+    rt_dispatch (p_TCB);
+  }
+  else {
+    /* Store token. */
+    p_SCB->tokens++;
+  }
+  return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_sem_wait -----------------------------------*/
+
+OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout) {
+  /* Obtain a token; possibly wait for it */
+  P_SCB p_SCB = semaphore;
+
+  if (p_SCB->tokens) {
+    p_SCB->tokens--;
+    __DMB();
+    return (OS_R_OK);
+  }
+  /* No token available: wait for one */
+  if (timeout == 0) {
+    return (OS_R_TMO);
+  }
+  if (p_SCB->p_lnk != NULL) {
+    rt_put_prio ((P_XCB)p_SCB, os_tsk.run);
+  }
+  else {
+    p_SCB->p_lnk = os_tsk.run;
+    os_tsk.run->p_lnk = NULL;
+    os_tsk.run->p_rlnk = (P_TCB)p_SCB;
+  }
+  rt_block(timeout, WAIT_SEM);
+  return (OS_R_TMO);
+}
+
+
+/*--------------------------- isr_sem_send ----------------------------------*/
+
+void isr_sem_send (OS_ID semaphore) {
+  /* Same function as "os_sem_send", but to be called by ISRs */
+  P_SCB p_SCB = semaphore;
+
+  rt_psq_enq (p_SCB, 0);
+  rt_psh_req ();
+}
+
+
+/*--------------------------- rt_sem_psh ------------------------------------*/
+
+void rt_sem_psh (P_SCB p_CB) {
+  /* Check if task has to be waken up */
+  P_TCB p_TCB;
+
+  __DMB();
+  if (p_CB->p_lnk != NULL) {
+    /* A task is waiting for token */
+    p_TCB = rt_get_first ((P_XCB)p_CB);
+    rt_rmv_dly (p_TCB);
+    p_TCB->state   = READY;
+#ifdef __CMSIS_RTOS
+    rt_ret_val(p_TCB, 1);
+#else
+    rt_ret_val(p_TCB, OS_R_SEM);
+#endif
+    rt_put_prio (&os_rdy, p_TCB);
+  }
+  else {
+    /* Store token */
+    p_CB->tokens++;
+  }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Semaphore.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,47 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_SEMAPHORE.H
+ *      Purpose: Implements binary and counting semaphores
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern void      rt_sem_init  (OS_ID semaphore, U16 token_count);
+extern OS_RESULT rt_sem_delete(OS_ID semaphore);
+extern OS_RESULT rt_sem_send  (OS_ID semaphore);
+extern OS_RESULT rt_sem_wait  (OS_ID semaphore, U16 timeout);
+extern void      isr_sem_send (OS_ID semaphore);
+extern void      rt_sem_psh (P_SCB p_CB);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_System.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,338 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_SYSTEM.C
+ *      Purpose: System Task Manager
+ *      Rev.:    8 April 2015
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_Task.h"
+#include "rt_System.h"
+#include "rt_Event.h"
+#include "rt_List.h"
+#include "rt_Mailbox.h"
+#include "rt_Semaphore.h"
+#include "rt_Time.h"
+#include "rt_Timer.h"
+#include "rt_Robin.h"
+#ifdef __CORTEX_A9
+#include "rt_HAL_CA.h"
+#else
+#include "rt_HAL_CM.h"
+#endif
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+int os_tick_irqn;
+U8  scheduler_suspended = 0;    // flag set by rt_suspend, cleared by rt_resume, read by SVC_Handler
+
+/*----------------------------------------------------------------------------
+ *      Local Variables
+ *---------------------------------------------------------------------------*/
+
+static volatile BIT os_lock;
+static volatile BIT os_psh_flag;
+#ifndef __CORTEX_A9
+static          U8  pend_flags;
+#endif
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+#define RL_RTX_VER      0x473
+
+#if defined (__CC_ARM)
+__asm void $$RTX$$version (void) {
+   /* Export a version number symbol for a version control. */
+
+                EXPORT  __RL_RTX_VER
+
+__RL_RTX_VER    EQU     RL_RTX_VER
+}
+#endif
+
+
+/*--------------------------- rt_suspend ------------------------------------*/
+
+extern U32 sysUserTimerWakeupTime(void);
+
+U32 rt_suspend (void) {
+  /* Suspend OS scheduler */
+  U32 delta = 0xFFFF;
+#ifdef __CMSIS_RTOS
+  U32 sleep;
+#endif
+
+  rt_tsk_lock();
+  scheduler_suspended = 1;
+
+  if (os_dly.p_dlnk) {
+    delta = os_dly.delta_time;
+  }
+#ifdef __CMSIS_RTOS
+  sleep = sysUserTimerWakeupTime();
+  if (sleep < delta) delta = sleep;
+#else
+  if (os_tmr.next) {
+    if (os_tmr.tcnt < delta) delta = os_tmr.tcnt;
+  }
+#endif
+
+  return (delta);
+}
+
+
+/*--------------------------- rt_resume -------------------------------------*/
+
+extern void sysUserTimerUpdate (U32 sleep_time);
+
+void rt_resume (U32 sleep_time) {
+  /* Resume OS scheduler after suspend */
+  P_TCB next;
+  U32   delta;
+
+  os_tsk.run->state = READY;
+  rt_put_rdy_first (os_tsk.run);
+
+  os_robin.task = NULL;
+
+  /* Update delays. */
+  if (os_dly.p_dlnk) {
+    delta = sleep_time;
+    if (delta >= os_dly.delta_time) {
+      delta   -= os_dly.delta_time;
+      os_time += os_dly.delta_time;
+      os_dly.delta_time = 1;
+      while (os_dly.p_dlnk) {
+        rt_dec_dly();
+        if (delta == 0) break;
+        delta--;
+        os_time++;
+      }
+    } else {
+      os_time           += delta;
+      os_dly.delta_time -= delta;
+    }
+  } else {
+    os_time += sleep_time;
+  }
+
+  /* Check the user timers. */
+#ifdef __CMSIS_RTOS
+  sysUserTimerUpdate(sleep_time);
+#else
+  if (os_tmr.next) {
+    delta = sleep_time;
+    if (delta >= os_tmr.tcnt) {
+      delta   -= os_tmr.tcnt;
+      os_tmr.tcnt = 1;
+      while (os_tmr.next) {
+        rt_tmr_tick();
+        if (delta == 0) break;
+        delta--;
+      }
+    } else {
+      os_tmr.tcnt -= delta;
+    }
+  }
+#endif
+
+  /* Switch back to highest ready task */
+  next = rt_get_first (&os_rdy);
+  rt_switch_req (next);
+
+  scheduler_suspended = 0;
+  rt_tsk_unlock();
+}
+
+
+/*--------------------------- rt_tsk_lock -----------------------------------*/
+
+void rt_tsk_lock (void) {
+  /* Prevent task switching by locking out scheduler */
+  if (os_lock == __TRUE) // don't lock again if already locked
+    return;
+
+  if (os_tick_irqn < 0) {
+    OS_LOCK();
+    os_lock = __TRUE;
+    OS_UNPEND (&pend_flags);
+  } else {
+    OS_X_LOCK(os_tick_irqn);
+    os_lock = __TRUE;
+    OS_X_UNPEND (&pend_flags);
+  }
+}
+
+
+/*--------------------------- rt_tsk_unlock ---------------------------------*/
+
+void rt_tsk_unlock (void) {
+  /* Unlock scheduler and re-enable task switching */
+  if (os_tick_irqn < 0) {
+    OS_UNLOCK();
+    os_lock = __FALSE;
+    OS_PEND (pend_flags, os_psh_flag);
+    os_psh_flag = __FALSE;
+  } else {
+    OS_X_UNLOCK(os_tick_irqn);
+    os_lock = __FALSE;
+    OS_X_PEND (pend_flags, os_psh_flag);
+    os_psh_flag = __FALSE;
+  }
+}
+
+
+/*--------------------------- rt_psh_req ------------------------------------*/
+
+void rt_psh_req (void) {
+  /* Initiate a post service handling request if required. */
+  if (os_lock == __FALSE) {
+    OS_PEND_IRQ ();
+  }
+  else {
+    os_psh_flag = __TRUE;
+  }
+}
+
+
+/*--------------------------- rt_pop_req ------------------------------------*/
+
+void rt_pop_req (void) {
+  /* Process an ISR post service requests. */
+  struct OS_XCB *p_CB;
+  P_TCB next;
+  U32  idx;
+
+  os_tsk.run->state = READY;
+  rt_put_rdy_first (os_tsk.run);
+
+  idx = os_psq->last;
+  while (os_psq->count) {
+    p_CB = os_psq->q[idx].id;
+    if (p_CB->cb_type == TCB) {
+      /* Is of TCB type */
+      rt_evt_psh ((P_TCB)p_CB, (U16)os_psq->q[idx].arg);
+    }
+    else if (p_CB->cb_type == MCB) {
+      /* Is of MCB type */
+      rt_mbx_psh ((P_MCB)p_CB, (void *)os_psq->q[idx].arg);
+    }
+    else {
+      /* Must be of SCB type */
+      rt_sem_psh ((P_SCB)p_CB);
+    }
+    if (++idx == os_psq->size) idx = 0;
+    rt_dec (&os_psq->count);
+  }
+  os_psq->last = idx;
+
+  next = rt_get_first (&os_rdy);
+  rt_switch_req (next);
+}
+
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+__weak int os_tick_init (void) {
+  /* Initialize SysTick timer as system tick timer. */
+  rt_systick_init ();
+  return (-1);  /* Return IRQ number of SysTick timer */
+}
+
+/*--------------------------- os_tick_val -----------------------------------*/
+
+__weak U32 os_tick_val (void) {
+  /* Get SysTick timer current value (0 .. OS_TRV). */
+  return rt_systick_val();
+}
+
+/*--------------------------- os_tick_ovf -----------------------------------*/
+
+__weak U32 os_tick_ovf (void) {
+  /* Get SysTick timer overflow flag */
+  return rt_systick_ovf();
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+__weak void os_tick_irqack (void) {
+  /* Acknowledge timer interrupt. */
+}
+
+
+/*--------------------------- rt_systick ------------------------------------*/
+
+extern void sysTimerTick(void);
+
+void rt_systick (void) {
+  /* Check for system clock update, suspend running task. */
+  P_TCB next;
+
+  os_tsk.run->state = READY;
+  rt_put_rdy_first (os_tsk.run);
+
+  /* Check Round Robin timeout. */
+  rt_chk_robin ();
+
+  /* Update delays. */
+  os_time++;
+  rt_dec_dly ();
+
+  /* Check the user timers. */
+#ifdef __CMSIS_RTOS
+  sysTimerTick();
+#else
+  rt_tmr_tick ();
+#endif
+
+  /* Switch back to highest ready task */
+  next = rt_get_first (&os_rdy);
+  rt_switch_req (next);
+}
+
+/*--------------------------- rt_stk_check ----------------------------------*/
+
+__weak void rt_stk_check (void) {
+  /* Check for stack overflow. */
+  if ((os_tsk.run->tsk_stack < (U32)os_tsk.run->stack) ||
+      (os_tsk.run->stack[0] != MAGIC_WORD)) {
+    os_error (OS_ERR_STK_OVF);
+  }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_System.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,53 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_SYSTEM.H
+ *      Purpose: System Task Manager definitions
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Variables */
+#define os_psq  ((P_PSQ)&os_fifo)
+extern int os_tick_irqn;
+
+/* Functions */
+extern U32  rt_suspend    (void);
+extern void rt_resume     (U32 sleep_time);
+extern void rt_tsk_lock   (void);
+extern void rt_tsk_unlock (void);
+extern void rt_psh_req    (void);
+extern void rt_pop_req    (void);
+extern void rt_systick    (void);
+extern void rt_stk_check  (void);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Task.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,437 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_TASK.C
+ *      Purpose: Task functions and system start up.
+ *      Rev.:    V4.73
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_Task.h"
+#include "rt_List.h"
+#include "rt_MemBox.h"
+#include "rt_Robin.h"
+#ifdef __CORTEX_A9
+#include "rt_HAL_CA.h"
+#else
+#include "rt_HAL_CM.h"
+#endif
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* Running and next task info. */
+struct OS_TSK os_tsk;
+
+/* Task Control Blocks of idle demon */
+struct OS_TCB os_idle_TCB;
+
+
+/*----------------------------------------------------------------------------
+ *      Local Functions
+ *---------------------------------------------------------------------------*/
+
+static OS_TID rt_get_TID (void) {
+  U32 tid;
+
+  for (tid = 1; tid <= os_maxtaskrun; tid++) {
+    if (os_active_TCB[tid-1] == NULL) {
+      return ((OS_TID)tid);
+    }
+  }
+  return (0);
+}
+
+
+/*--------------------------- rt_init_context -------------------------------*/
+
+static void rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body) {
+  /* Initialize general part of the Task Control Block. */
+  p_TCB->cb_type = TCB;
+  p_TCB->state   = READY;
+  p_TCB->prio    = priority;
+  p_TCB->prio_base = priority;
+  p_TCB->p_lnk   = NULL;
+  p_TCB->p_rlnk  = NULL;
+  p_TCB->p_dlnk  = NULL;
+  p_TCB->p_blnk  = NULL;
+  p_TCB->p_mlnk    = NULL;
+  p_TCB->delta_time    = 0;
+  p_TCB->interval_time = 0;
+  p_TCB->events  = 0;
+  p_TCB->waits   = 0;
+  p_TCB->stack_frame = 0;
+
+  if (p_TCB->priv_stack == 0) {
+    /* Allocate the memory space for the stack. */
+    p_TCB->stack = rt_alloc_box (mp_stk);
+  }
+  rt_init_stack (p_TCB, task_body);
+}
+
+
+/*--------------------------- rt_switch_req ---------------------------------*/
+
+void rt_switch_req (P_TCB p_new) {
+  /* Switch to next task (identified by "p_new"). */
+  os_tsk.new_tsk   = p_new;
+  p_new->state = RUNNING;
+  DBG_TASK_SWITCH(p_new->task_id);
+}
+
+
+/*--------------------------- rt_dispatch -----------------------------------*/
+
+void rt_dispatch (P_TCB next_TCB) {
+  /* Dispatch next task if any identified or dispatch highest ready task    */
+  /* "next_TCB" identifies a task to run or has value NULL (=no next task)  */
+  if (next_TCB == NULL) {
+    /* Running task was blocked: continue with highest ready task */
+    next_TCB = rt_get_first (&os_rdy);
+    rt_switch_req (next_TCB);
+  }
+  else {
+    /* Check which task continues */
+    if (next_TCB->prio > os_tsk.run->prio) {
+      /* preempt running task */
+      rt_put_rdy_first (os_tsk.run);
+      os_tsk.run->state = READY;
+      rt_switch_req (next_TCB);
+    }
+    else {
+      /* put next task into ready list, no task switch takes place */
+      next_TCB->state = READY;
+      rt_put_prio (&os_rdy, next_TCB);
+    }
+  }
+}
+
+
+/*--------------------------- rt_block --------------------------------------*/
+
+void rt_block (U16 timeout, U8 block_state) {
+  /* Block running task and choose next ready task.                         */
+  /* "timeout" sets a time-out value or is 0xffff (=no time-out).           */
+  /* "block_state" defines the appropriate task state */
+  P_TCB next_TCB;
+
+  if (timeout) {
+    if (timeout < 0xffff) {
+      rt_put_dly (os_tsk.run, timeout);
+    }
+    os_tsk.run->state = block_state;
+    next_TCB = rt_get_first (&os_rdy);
+    rt_switch_req (next_TCB);
+  }
+}
+
+
+/*--------------------------- rt_tsk_pass -----------------------------------*/
+
+void rt_tsk_pass (void) {
+  /* Allow tasks of same priority level to run cooperatively.*/
+  P_TCB p_new;
+
+  p_new = rt_get_same_rdy_prio();
+  if (p_new != NULL) {
+    rt_put_prio ((P_XCB)&os_rdy, os_tsk.run);
+    os_tsk.run->state = READY;
+    rt_switch_req (p_new);
+  }
+}
+
+
+/*--------------------------- rt_tsk_self -----------------------------------*/
+
+OS_TID rt_tsk_self (void) {
+  /* Return own task identifier value. */
+  if (os_tsk.run == NULL) {
+    return (0);
+  }
+  return (os_tsk.run->task_id);
+}
+
+
+/*--------------------------- rt_tsk_prio -----------------------------------*/
+
+OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio) {
+  /* Change execution priority of a task to "new_prio". */
+  P_TCB p_task;
+
+  if (task_id == 0) {
+    /* Change execution priority of calling task. */
+    os_tsk.run->prio = new_prio;
+    os_tsk.run->prio_base = new_prio;
+run:if (rt_rdy_prio() > new_prio) {
+      rt_put_prio (&os_rdy, os_tsk.run);
+      os_tsk.run->state   = READY;
+      rt_dispatch (NULL);
+    }
+    return (OS_R_OK);
+  }
+
+  /* Find the task in the "os_active_TCB" array. */
+  if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) {
+    /* Task with "task_id" not found or not started. */
+    return (OS_R_NOK);
+  }
+  p_task = os_active_TCB[task_id-1];
+  p_task->prio = new_prio;
+  p_task->prio_base = new_prio;
+  if (p_task == os_tsk.run) {
+    goto run;
+  }
+  rt_resort_prio (p_task);
+  if (p_task->state == READY) {
+    /* Task enqueued in a ready list. */
+    p_task = rt_get_first (&os_rdy);
+    rt_dispatch (p_task);
+  }
+  return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_tsk_create ---------------------------------*/
+
+OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv) {
+  /* Start a new task declared with "task". */
+  P_TCB task_context;
+  U32 i;
+
+  /* Priority 0 is reserved for idle task! */
+  if ((prio_stksz & 0xFF) == 0) {
+    prio_stksz += 1;
+  }
+  task_context = rt_alloc_box (mp_tcb);
+  if (task_context == NULL) {
+    return (0);
+  }
+  /* If "size != 0" use a private user provided stack. */
+  task_context->stack      = stk;
+  task_context->priv_stack = prio_stksz >> 8;
+  /* Pass parameter 'argv' to 'rt_init_context' */
+  task_context->msg = argv;
+  /* For 'size == 0' system allocates the user stack from the memory pool. */
+  rt_init_context (task_context, prio_stksz & 0xFF, task);
+
+  /* Find a free entry in 'os_active_TCB' table. */
+  i = rt_get_TID ();
+  os_active_TCB[i-1] = task_context;
+  task_context->task_id = i;
+  DBG_TASK_NOTIFY(task_context, __TRUE);
+  rt_dispatch (task_context);
+  return ((OS_TID)i);
+}
+
+
+/*--------------------------- rt_tsk_delete ---------------------------------*/
+
+OS_RESULT rt_tsk_delete (OS_TID task_id) {
+  /* Terminate the task identified with "task_id". */
+  P_TCB task_context;
+  P_TCB  p_TCB;
+  P_MUCB p_MCB, p_MCB0;
+
+  if (task_id == 0 || task_id == os_tsk.run->task_id) {
+    /* Terminate itself. */
+    os_tsk.run->state     = INACTIVE;
+    os_tsk.run->tsk_stack = rt_get_PSP ();
+    rt_stk_check ();
+    p_MCB = os_tsk.run->p_mlnk;
+    while (p_MCB) {
+      /* Release mutexes owned by this task */
+      if (p_MCB->p_lnk) {
+        /* A task is waiting for mutex. */
+        p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+        rt_ret_val(p_TCB, 0/*osOK*/);
+#else
+        rt_ret_val(p_TCB, OS_R_MUT); 
+#endif
+        rt_rmv_dly (p_TCB);
+        p_TCB->state = READY;
+        rt_put_prio (&os_rdy, p_TCB);
+        /* A waiting task becomes the owner of this mutex. */
+        p_MCB0 = p_MCB;
+        p_MCB->level  = 1;
+        p_MCB->owner  = p_TCB;
+        p_MCB->p_mlnk = p_TCB->p_mlnk;
+        p_TCB->p_mlnk = p_MCB; 
+        p_MCB = p_MCB0->p_mlnk;
+      }
+      else {
+        p_MCB = p_MCB->p_mlnk;
+      }
+    }
+    os_active_TCB[os_tsk.run->task_id-1] = NULL;
+    rt_free_box (mp_stk, os_tsk.run->stack);
+    os_tsk.run->stack = NULL;
+    DBG_TASK_NOTIFY(os_tsk.run, __FALSE);
+    rt_free_box (mp_tcb, os_tsk.run);
+    os_tsk.run = NULL;
+    rt_dispatch (NULL);
+    /* The program should never come to this point. */
+  }
+  else {
+    /* Find the task in the "os_active_TCB" array. */
+    if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) {
+      /* Task with "task_id" not found or not started. */
+      return (OS_R_NOK);
+    }
+    task_context = os_active_TCB[task_id-1];
+    rt_rmv_list (task_context);
+    rt_rmv_dly (task_context);
+    p_MCB = task_context->p_mlnk;
+    while (p_MCB) {
+      /* Release mutexes owned by this task */
+      if (p_MCB->p_lnk) {
+        /* A task is waiting for mutex. */
+        p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+        rt_ret_val(p_TCB, 0/*osOK*/);
+#else
+        rt_ret_val(p_TCB, OS_R_MUT); 
+#endif
+        rt_rmv_dly (p_TCB);
+        p_TCB->state = READY;
+        rt_put_prio (&os_rdy, p_TCB);
+        /* A waiting task becomes the owner of this mutex. */
+        p_MCB0 = p_MCB;
+        p_MCB->level  = 1;
+        p_MCB->owner  = p_TCB;
+        p_MCB->p_mlnk = p_TCB->p_mlnk;
+        p_TCB->p_mlnk = p_MCB; 
+        p_MCB = p_MCB0->p_mlnk;
+      }
+      else {
+        p_MCB = p_MCB->p_mlnk;
+      }
+    }
+    os_active_TCB[task_id-1] = NULL;
+    rt_free_box (mp_stk, task_context->stack);
+    task_context->stack = NULL;
+    DBG_TASK_NOTIFY(task_context, __FALSE);
+    rt_free_box (mp_tcb, task_context);
+    if (rt_rdy_prio() > os_tsk.run->prio) {
+      /* Ready task has higher priority than running task. */
+      os_tsk.run->state = READY;
+      rt_put_prio (&os_rdy, os_tsk.run);
+      rt_dispatch (NULL);
+    }
+  }
+  return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_sys_init -----------------------------------*/
+
+#ifdef __CMSIS_RTOS
+void rt_sys_init (void) {
+#else
+void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk) {
+#endif
+  /* Initialize system and start up task declared with "first_task". */
+  U32 i;
+
+  DBG_INIT();
+
+  /* Initialize dynamic memory and task TCB pointers to NULL. */
+  for (i = 0; i < os_maxtaskrun; i++) {
+    os_active_TCB[i] = NULL;
+  }
+  rt_init_box (&mp_tcb, mp_tcb_size, sizeof(struct OS_TCB));
+  rt_init_box (&mp_stk, mp_stk_size, BOX_ALIGN_8 | (U16)(os_stackinfo));
+  rt_init_box ((U32 *)m_tmr, mp_tmr_size, sizeof(struct OS_TMR));
+
+  /* Set up TCB of idle demon */
+  os_idle_TCB.task_id    = 255;
+  os_idle_TCB.priv_stack = 0;
+  rt_init_context (&os_idle_TCB, 0, os_idle_demon);
+
+  /* Set up ready list: initially empty */
+  os_rdy.cb_type = HCB;
+  os_rdy.p_lnk   = NULL;
+  /* Set up delay list: initially empty */
+  os_dly.cb_type = HCB;
+  os_dly.p_dlnk  = NULL;
+  os_dly.p_blnk  = NULL;
+  os_dly.delta_time = 0;
+
+  /* Fix SP and system variables to assume idle task is running  */
+  /* Transform main program into idle task by assuming idle TCB */
+#ifndef __CMSIS_RTOS
+  rt_set_PSP (os_idle_TCB.tsk_stack+32);
+#endif
+  os_tsk.run = &os_idle_TCB;
+  os_tsk.run->state = RUNNING;
+
+  /* Initialize ps queue */
+  os_psq->first = 0;
+  os_psq->last  = 0;
+  os_psq->size  = os_fifo_size;
+
+  rt_init_robin ();
+
+  /* Initialize SVC and PendSV */
+  rt_svc_init ();
+
+#ifndef __CMSIS_RTOS
+  /* Initialize and start system clock timer */
+  os_tick_irqn = os_tick_init ();
+  if (os_tick_irqn >= 0) {
+    OS_X_INIT(os_tick_irqn);
+  }
+
+  /* Start up first user task before entering the endless loop */
+  rt_tsk_create (first_task, prio_stksz, stk, NULL);
+#endif
+}
+
+
+/*--------------------------- rt_sys_start ----------------------------------*/
+
+#ifdef __CMSIS_RTOS
+void rt_sys_start (void) {
+  /* Start system */
+
+  /* Initialize and start system clock timer */
+  os_tick_irqn = os_tick_init ();
+  if (os_tick_irqn >= 0) {
+    OS_X_INIT(os_tick_irqn);
+  }
+}
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Task.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,88 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_TASK.H
+ *      Purpose: Task functions and system start up.
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Definitions */
+
+/* Values for 'state'   */
+#define INACTIVE        0
+#define READY           1
+#define RUNNING         2
+#define WAIT_DLY        3
+#define WAIT_ITV        4
+#define WAIT_OR         5
+#define WAIT_AND        6
+#define WAIT_SEM        7
+#define WAIT_MBX        8
+#define WAIT_MUT        9
+
+/* Return codes */
+#define OS_R_TMO        0x01
+#define OS_R_EVT        0x02
+#define OS_R_SEM        0x03
+#define OS_R_MBX        0x04
+#define OS_R_MUT        0x05
+
+#define OS_R_OK         0x00
+#define OS_R_NOK        0xff
+
+/* Variables */
+extern struct OS_TSK os_tsk;
+extern struct OS_TCB os_idle_TCB;
+
+/* Functions */
+extern void      rt_switch_req (P_TCB p_new);
+extern void      rt_dispatch   (P_TCB next_TCB);
+extern void      rt_block      (U16 timeout, U8 block_state);
+extern void      rt_tsk_pass   (void);
+extern OS_TID    rt_tsk_self   (void);
+extern OS_RESULT rt_tsk_prio   (OS_TID task_id, U8 new_prio);
+extern OS_TID    rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv);
+extern OS_RESULT rt_tsk_delete (OS_TID task_id);
+#ifdef __CMSIS_RTOS
+extern void      rt_sys_init   (void);
+extern void      rt_sys_start  (void);
+#else
+extern void      rt_sys_init   (FUNCP first_task, U32 prio_stksz, void *stk);
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
+
+
+
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Time.c	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,95 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_TIME.C
+ *      Purpose: Delay and interval wait functions
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+
+/*----------------------------------------------------------------------------
+ *      Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* Free running system tick counter */
+U32 os_time;
+
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_time_get -----------------------------------*/
+
+U32 rt_time_get (void) {
+  /* Get system time tick */
+  return (os_time);
+}
+
+
+/*--------------------------- rt_dly_wait -----------------------------------*/
+
+void rt_dly_wait (U16 delay_time) {
+  /* Delay task by "delay_time" */
+  rt_block (delay_time, WAIT_DLY);
+}
+
+
+/*--------------------------- rt_itv_set ------------------------------------*/
+
+void rt_itv_set (U16 interval_time) {
+  /* Set interval length and define start of first interval */
+  os_tsk.run->interval_time = interval_time;
+  os_tsk.run->delta_time = interval_time + (U16)os_time;
+}
+
+
+/*--------------------------- rt_itv_wait -----------------------------------*/
+
+void rt_itv_wait (void) {
+  /* Wait for interval end and define start of next one */
+  U16 delta;
+
+  delta = os_tsk.run->delta_time - (U16)os_time;
+  os_tsk.run->delta_time += os_tsk.run->interval_time;
+  if ((delta & 0x8000) == 0) {
+    rt_block (delta, WAIT_ITV);
+  }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Time.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,48 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_TIME.H
+ *      Purpose: Delay and interval wait functions definitions
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Variables */
+extern U32 os_time;
+
+/* Functions */
+extern U32  rt_time_get (void);
+extern void rt_dly_wait (U16 delay_time);
+extern void rt_itv_set  (U16 interval_time);
+extern void rt_itv_wait (void);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_Timer.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,47 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_TIMER.H
+ *      Purpose: User timer functions
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Variables */
+extern struct OS_XTMR os_tmr;
+
+/* Functions */
+extern void  rt_tmr_tick   (void);
+extern OS_ID rt_tmr_create (U16 tcnt, U16 info);
+extern OS_ID rt_tmr_kill   (OS_ID timer);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/rtos/rtx/TARGET_CORTEX_A/rt_TypeDef.h	Thu Feb 16 10:23:48 2017 +0000
@@ -0,0 +1,187 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RT_TYPEDEF.H
+ *      Purpose: Type Definitions
+ *      Rev.:    V4.73 (plus large stack)
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Types */
+typedef char               S8;
+typedef unsigned char      U8;
+typedef short              S16;
+typedef unsigned short     U16;
+typedef int                S32;
+typedef unsigned int       U32;
+typedef long long          S64;
+typedef unsigned long long U64;
+typedef unsigned char      BIT;
+typedef unsigned int       BOOL;
+typedef void               (*FUNCP)(void);
+
+typedef U32     OS_TID;
+typedef void    *OS_ID;
+typedef U32     OS_RESULT;
+
+typedef struct OS_TCB {
+  /* General part: identical for all implementations.                        */
+  U8     cb_type;                 /* Control Block Type                      */
+  U8     state;                   /* Task state                              */
+  U8     prio;                    /* Execution priority                      */
+  U8     task_id;                 /* Task ID value for optimized TCB access  */
+  struct OS_TCB *p_lnk;           /* Link pointer for ready/sem. wait list   */
+  struct OS_TCB *p_rlnk;          /* Link pointer for sem./mbx lst backwards */
+  struct OS_TCB *p_dlnk;          /* Link pointer for delay list             */
+  struct OS_TCB *p_blnk;          /* Link pointer for delay list backwards   */
+  U16    delta_time;              /* Time until time out                     */
+  U16    interval_time;           /* Time interval for periodic waits        */
+  U16    events;                  /* Event flags                             */
+  U16    waits;                   /* Wait flags                              */
+  void   **msg;                   /* Direct message passing when task waits  */
+  struct OS_MUCB *p_mlnk;         /* Link pointer for mutex owner list       */
+  U8     prio_base;               /* Base priority                           */
+
+  /* Hardware dependant part: specific for Cortex processor                  */
+  U8     stack_frame;             /* Stack frame: 0x0 Basic, 0x1 Extended, 0x2 VFP/D16 stacked, 0x4 NEON/D32 stacked */
+#if defined (__ICCARM__)
+#ifndef __LARGE_PRIV_STACK
+  U16    priv_stack;              /* Private stack size, 0= system assigned  */
+#else
+  U16    reserved;                /* Reserved (padding)                      */
+  U32    priv_stack;              /* Private stack size for LARGE_STACK, 0= system assigned  */
+#endif /* __LARGE_PRIV_STACK */
+#else
+  U16    reserved;                /* Reserved (padding)                      */
+  U32    priv_stack;              /* Private stack size for LARGE_STACK, 0= system assigned  */
+#endif
+  U32    tsk_stack;               /* Current task Stack pointer (R13)        */
+  U32    *stack;                  /* Pointer to Task Stack memory block      */
+
+  /* Task entry point used for uVision debugger                              */
+  FUNCP  ptask;                   /* Task entry address                      */
+} *P_TCB;
+#define TCB_TID          3        /* 'task id' offset                        */
+#define TCB_STACKF      37        /* 'stack_frame' offset                    */
+#if defined (__ICCARM__)
+#ifndef __LARGE_PRIV_STACK
+#define TCB_TSTACK      40        /* 'tsk_stack' offset                      */
+#else
+#define TCB_TSTACK      44        /* 'tsk_stack' offset for LARGE_STACK      */
+#endif /* __LARGE_PRIV_STACK */
+#else
+#define TCB_TSTACK      44        /* 'tsk_stack' offset for LARGE_STACK      */
+#endif
+
+typedef struct OS_PSFE {          /* Post Service Fifo Entry                 */
+  void  *id;                      /* Object Identification                   */
+  U32    arg;                     /* Object Argument                         */
+} *P_PSFE;
+
+typedef struct OS_PSQ {           /* Post Service Queue                      */
+  U8     first;                   /* FIFO Head Index                         */
+  U8     last;                    /* FIFO Tail Index                         */
+  U8     count;                   /* Number of stored items in FIFO          */
+  U8     size;                    /* FIFO Size                               */
+  struct OS_PSFE q[1];            /* FIFO Content                            */
+} *P_PSQ;
+
+typedef struct OS_TSK {
+  P_TCB  run;                     /* Current running task                    */
+  P_TCB  new_tsk;                 /* Scheduled task to run                   */
+} *P_TSK;
+
+typedef struct OS_ROBIN {         /* Round Robin Control                     */
+  P_TCB  task;                    /* Round Robin task                        */
+  U16    time;                    /* Round Robin switch time                 */
+  U16    tout;                    /* Round Robin timeout                     */
+} *P_ROBIN;
+
+typedef struct OS_XCB {
+  U8     cb_type;                 /* Control Block Type                      */
+  struct OS_TCB *p_lnk;           /* Link pointer for ready/sem. wait list   */
+  struct OS_TCB *p_rlnk;          /* Link pointer for sem./mbx lst backwards */
+  struct OS_TCB *p_dlnk;          /* Link pointer for delay list             */
+  struct OS_TCB *p_blnk;          /* Link pointer for delay list backwards   */
+  U16    delta_time;              /* Time until time out                     */
+} *P_XCB;
+
+typedef struct OS_MCB {
+  U8     cb_type;                 /* Control Block Type                      */
+  U8     state;                   /* State flag variable                     */
+  U8     isr_st;                  /* State flag variable for isr functions   */
+  struct OS_TCB *p_lnk;           /* Chain of tasks waiting for message      */
+  U16    first;                   /* Index of the message list begin         */
+  U16    last;                    /* Index of the message list end           */
+  U16    count;                   /* Actual number of stored messages        */
+  U16    size;                    /* Maximum number of stored messages       */
+  void   *msg[1];                 /* FIFO for Message pointers 1st element   */
+} *P_MCB;
+
+typedef struct OS_SCB {
+  U8     cb_type;                 /* Control Block Type                      */
+  U8     mask;                    /* Semaphore token mask                    */
+  U16    tokens;                  /* Semaphore tokens                        */
+  struct OS_TCB *p_lnk;           /* Chain of tasks waiting for tokens       */
+} *P_SCB;
+
+typedef struct OS_MUCB {
+  U8     cb_type;                 /* Control Block Type                      */
+  U16    level;                   /* Call nesting level                      */
+  struct OS_TCB *p_lnk;           /* Chain of tasks waiting for mutex        */
+  struct OS_TCB *owner;           /* Mutex owner task                        */
+  struct OS_MUCB *p_mlnk;         /* Chain of mutexes by owner task          */
+} *P_MUCB;
+
+typedef struct OS_XTMR {
+  struct OS_TMR  *next;
+  U16    tcnt;
+} *P_XTMR;
+
+typedef struct OS_TMR {
+  struct OS_TMR  *next;           /* Link pointer to Next timer              */
+  U16    tcnt;                    /* Timer delay count                       */
+  U16    info;                    /* User defined call info                  */
+} *P_TMR;
+
+typedef struct OS_BM {
+  void *free;                     /* Pointer to first free memory block      */
+  void *end;                      /* Pointer to memory block end             */
+  U32  blk_size;                  /* Memory block size                       */
+} *P_BM;
+
+/* Definitions */
+#define __TRUE          1
+#define __FALSE         0
+#define NULL            ((void *) 0)
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
+